2.6.0-test9-r8169-8110S.patch

   1 diff -ruN linux-2.6.0-test9.old/drivers/net/r8169.c linux-2.6.0-test9/drivers/net/r8169.c
   2 --- linux-2.6.0-test9.old/drivers/net/r8169.c   2003-10-25 14:43:40.000000000 -0400
   3 +++ linux-2.6.0-test9/drivers/net/r8169.c       2003-10-26 11:56:01.785147792 -0500
   4 @@ -1,6 +1,6 @@
   5  /*
   6  =========================================================================
   7 - r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
   8 + r8169.c: A RealTek RTL8169s/8110s Gigabit Ethernet driver for Linux kernel 2.4.x.
   9   --------------------------------------------------------------------
  10
  11   History:
  12 @@ -10,59 +10,78 @@
  13    1. The media can be forced in 5 modes.
  14          Command: 'insmod r8169 media = SET_MEDIA'
  15          Ex:      'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex.
  16 -
  17 +
  18          SET_MEDIA can be:
  19                 _10_Half        = 0x01
  20                 _10_Full        = 0x02
  21                 _100_Half       = 0x04
  22                 _100_Full       = 0x08
  23                 _1000_Full      = 0x10
  24 -
  25 +
  26    2. Support TBI mode.
  27 -=========================================================================
  28 -VERSION 1.1    <2002/10/4>
  29 +//=========================================================================
  30 +RTL8169_VERSION "1.1"  <2002/10/4>
  31
  32         The bit4:0 of MII register 4 is called "selector field", and have to be
  33         00001b to indicate support of IEEE std 802.3 during NWay process of
  34 -       exchanging Link Code Word (FLP).
  35 -
  36 -VERSION 1.2    <2002/11/30>
  37 -
  38 -       - Large style cleanup
  39 -       - Use ether_crc in stock kernel (linux/crc32.h)
  40 -       - Copy mc_filter setup code from 8139cp
  41 -         (includes an optimization, and avoids set_bit use)
  42 +       exchanging Link Code Word (FLP).
  43
  44 +RTL8169_VERSION "1.2"  <2003/6/17>
  45 +       Update driver module name.
  46 +       Modify ISR.
  47 +        Add chip mac_version.
  48 +
  49 +RTL8169_VERSION "1.3"  <2003/6/20>
  50 +        Add chip phy_version.
  51 +       Add priv->phy_timer_t, rtl8169_phy_timer_t_handler()
  52 +       Add rtl8169_hw_PHY_config()
  53 +       Add rtl8169_hw_PHY_reset()
  54 +
  55 +RTL8169_VERSION "1.4"  <2003/7/14>
  56 +       Add tx_bytes, rx_bytes.
  57 +
  58 +RTL8169_VERSION "1.5"  <2003/7/18>
  59 +       Set 0x0000 to PHY at offset 0x0b.
  60 +       Modify chip mac_version, phy_version
  61 +       Force media for multiple card.
  62 +RTL8169_VERSION "1.6"  <2003/8/25>
  63 +       Modify receive data buffer.
  64  */
  65
  66 +
  67  #include <linux/module.h>
  68  #include <linux/pci.h>
  69  #include <linux/netdevice.h>
  70  #include <linux/etherdevice.h>
  71  #include <linux/delay.h>
  72 -#include <linux/crc32.h>
  73 +
  74 +#include <linux/timer.h>
  75  #include <linux/init.h>
  76
  77 -#include <asm/io.h>
  78
  79 -#define RTL8169_VERSION "1.2"
  80 -#define MODULENAME "r8169"
  81 +#define RTL8169_VERSION "1.6 <2003-08-25>"
  82 +#define MODULENAME "RTL8169s/8110s"
  83  #define RTL8169_DRIVER_NAME   MODULENAME " Gigabit Ethernet driver " RTL8169_VERSION
  84  #define PFX MODULENAME ": "
  85
  86 +
  87 +#undef RTL8169_DEBUG
  88 +
  89  #ifdef RTL8169_DEBUG
  90  #define assert(expr) \
  91          if(!(expr)) {                                  \
  92 -               printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  93 -               #expr,__FILE__,__FUNCTION__,__LINE__);          \
  94 +               printk( "Assertion failed! %s,%s,%s,line=%d\n", #expr,__FILE__,__FUNCTION__,__LINE__);          \
  95          }
  96 +#define DBG_PRINT( fmt, args...)   printk("r8169: " fmt, ## args);
  97  #else
  98  #define assert(expr) do {} while (0)
  99 -#endif
 100 +#define DBG_PRINT( fmt, args...)   ;
 101 +#endif // end of #ifdef RTL8169_DEBUG
 102 +
 103
 104  /* media options */
 105  #define MAX_UNITS 8
 106 -static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
 107 +static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
 108
 109  /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
 110  static int max_interrupt_work = 20;
 111 @@ -77,18 +96,20 @@
 112  /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
 113  #define MAX_ETH_FRAME_SIZE     1536
 114
 115 -#define TX_FIFO_THRESH 256     /* In bytes */
 116 +#define TX_FIFO_THRESH 256             /* In bytes */
 117 +
 118 +#define RX_FIFO_THRESH 7               /* 7 means NO threshold, Rx buffer level before first PCI xfer.  */
 119 +#define RX_DMA_BURST   6               /* Maximum PCI burst, '6' is 1024 */
 120 +#define TX_DMA_BURST   6               /* Maximum PCI burst, '6' is 1024 */
 121 +#define ETTh   0x3F            /* 0x3F means NO threshold */
 122 +#define RxPacketMaxSize        0x0800          /* Maximum size supported is 16K-1 */
 123 +#define InterFrameGap  0x03            /* 3 means InterFrameGap = the shortest one */
 124 +
 125 +#define NUM_TX_DESC    64              /* Number of Tx descriptor registers*/
 126 +#define NUM_RX_DESC    64              /* Number of Rx descriptor registers*/
 127 +#define RX_BUF_SIZE    1536            /* Rx Buffer size */
 128
 129 -#define RX_FIFO_THRESH 7       /* 7 means NO threshold, Rx buffer level before first PCI xfer.  */
 130 -#define RX_DMA_BURST   6       /* Maximum PCI burst, '6' is 1024 */
 131 -#define TX_DMA_BURST   6       /* Maximum PCI burst, '6' is 1024 */
 132 -#define EarlyTxThld    0x3F    /* 0x3F means NO early transmit */
 133 -#define RxPacketMaxSize        0x0800  /* Maximum size supported is 16K-1 */
 134 -#define InterFrameGap  0x03    /* 3 means InterFrameGap = the shortest one */
 135 -
 136 -#define NUM_TX_DESC    64      /* Number of Tx descriptor registers */
 137 -#define NUM_RX_DESC    64      /* Number of Rx descriptor registers */
 138 -#define RX_BUF_SIZE    1536    /* Rx Buffer size */
 139 +#define MAX_RX_SKBDATA_SIZE 1600
 140
 141  #define RTL_MIN_IO_SIZE 0x80
 142  #define TX_TIMEOUT  (6*HZ)
 143 @@ -101,87 +122,178 @@
 144  #define RTL_R16(reg)           readw (ioaddr + (reg))
 145  #define RTL_R32(reg)           ((unsigned long) readl (ioaddr + (reg)))
 146
 147 -static struct {
 148 +
 149 +#define RTL_GIGA_MAC_VER_B  0x00    //MAC version 0000
 150 +//#define RTL_GIGA_MAC_VER_C  0x03
 151 +#define RTL_GIGA_MAC_VER_D  0x01    //MAC version 0001
 152 +#define RTL_GIGA_MAC_VER_E  0x02    //MAC version 0002
 153 +
 154 +#define RTL_GET_MAC_VERSION(mac_version)     \
 155 +{\
 156 +       mac_version = RTL_GIGA_MAC_VER_B;\
 157 +       if( (RTL_R32(TxConfig)&0x7c800000) & (0x1<<26) ){ \
 158 +               mac_version = RTL_GIGA_MAC_VER_E;\
 159 +       }\
 160 +       else if( (RTL_R32(TxConfig)&0x7c800000) & (0x1<<23) ){\
 161 +               mac_version = RTL_GIGA_MAC_VER_D;\
 162 +       }\
 163 +       else if( (RTL_R32(TxConfig)&0x7c800000) == 0x00000000 ){\
 164 +               mac_version = RTL_GIGA_MAC_VER_B;\
 165 +       }\
 166 +}
 167 +
 168 +#define RTL_PRINT_MAC_VERSION(mac_version) \
 169 +{\
 170 +       switch(mac_version) \
 171 +       { \
 172 +               case RTL_GIGA_MAC_VER_E: \
 173 +                       DBG_PRINT("mac_version == RTL_GIGA_MAC_VER_E (0002)\n"); \
 174 +                       break; \
 175 +               case RTL_GIGA_MAC_VER_D: \
 176 +                       DBG_PRINT("mac_version == RTL_GIGA_MAC_VER_D (0001)\n"); \
 177 +                       break; \
 178 +               case RTL_GIGA_MAC_VER_B: \
 179 +                       DBG_PRINT("mac_version == RTL_GIGA_MAC_VER_B (0000)\n"); \
 180 +                       break; \
 181 +               default: \
 182 +                       DBG_PRINT("mac_version == Unknown\n"); \
 183 +                       break; \
 184 +       } \
 185 +}
 186 +
 187 +#define RTL_GIGA_PHY_VER_C    0x03     //PHY Reg 0x03 bit0-3 == 0x0000
 188 +#define RTL_GIGA_PHY_VER_D    0x04     //PHY Reg 0x03 bit0-3 == 0x0000
 189 +#define RTL_GIGA_PHY_VER_E    0x05     //PHY Reg 0x03 bit0-3 == 0x0000
 190 +#define RTL_GIGA_PHY_VER_F    0x06     //PHY Reg 0x03 bit0-3 == 0x0001
 191 +#define RTL_GIGA_PHY_VER_G    0x07     //PHY Reg 0x03 bit0-3 == 0x0002
 192 +
 193 +#define RTL_GET_PHY_VERSION(phy_version)     \
 194 +{\
 195 +       phy_version = RTL_GIGA_PHY_VER_D;\
 196 +       if( (RTL8169_READ_GMII_REG(ioaddr,3)&0x000f) == 0x0002 ){ \
 197 +               phy_version = RTL_GIGA_PHY_VER_G;\
 198 +       } \
 199 +       else if( (RTL8169_READ_GMII_REG(ioaddr,3)&0x000f) == 0x0001 ){ \
 200 +               phy_version = RTL_GIGA_PHY_VER_F;\
 201 +       } \
 202 +       else if( (RTL8169_READ_GMII_REG(ioaddr,3)&0x000f) == 0x0000 ){ \
 203 +               phy_version = RTL_GIGA_PHY_VER_E;\
 204 +       } \
 205 +}
 206 +
 207 +#define RTL_PRINT_PHY_VERSION(phy_version)  \
 208 +{\
 209 +       switch(phy_version)\
 210 +       { \
 211 +               case RTL_GIGA_PHY_VER_G: \
 212 +                       DBG_PRINT("phy_version == RTL_GIGA_PHY_VER_G (0002)\n"); \
 213 +                       break; \
 214 +               case RTL_GIGA_PHY_VER_F: \
 215 +                       DBG_PRINT("phy_version == RTL_GIGA_PHY_VER_F (0001)\n"); \
 216 +                       break; \
 217 +               case RTL_GIGA_PHY_VER_E: \
 218 +                       DBG_PRINT("phy_version == RTL_GIGA_PHY_VER_E (0000)\n"); \
 219 +                       break; \
 220 +               case RTL_GIGA_PHY_VER_D: \
 221 +                       DBG_PRINT("phy_version == RTL_GIGA_PHY_VER_D (0000)\n"); \
 222 +                       break; \
 223 +               default: \
 224 +                       DBG_PRINT("phy_version == Unknown\n"); \
 225 +                       break; \
 226 +       } \
 227 +}
 228 +
 229 +
 230 +const static struct {
 231         const char *name;
 232 -} board_info[] __devinitdata = {
 233 -       {
 234 -"RealTek RTL8169 Gigabit Ethernet"},};
 235 +       u8 mac_version;          /* depend on RTL8169 docs */
 236 +       u32 RxConfigMask;       /* should clear the bits supported by this chip */
 237 +} rtl_chip_info[] = {
 238 +       { "RTL8169",  RTL_GIGA_MAC_VER_B,  0xff7e1880 },
 239 +       { "RTL8169s/8110s",  RTL_GIGA_MAC_VER_D,  0xff7e1880 },
 240 +       { "RTL8169s/8110s",  RTL_GIGA_MAC_VER_E,  0xff7e1880 },
 241 +};
 242 +
 243
 244 -static struct pci_device_id rtl8169_pci_tbl[] = {
 245 -       {0x10ec, 0x8169, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 246 +
 247 +
 248 +static struct pci_device_id rtl8169_pci_tbl[] __devinitdata = {
 249 +       { 0x10ec, 0x8169, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
 250         {0,},
 251  };
 252
 253 -MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 254 +
 255 +
 256 +MODULE_DEVICE_TABLE (pci, rtl8169_pci_tbl);
 257
 258  enum RTL8169_registers {
 259 -       MAC0 = 0,               /* Ethernet hardware address. */
 260 -       MAR0 = 8,               /* Multicast filter. */
 261 -       TxDescStartAddr = 0x20,
 262 -       TxHDescStartAddr = 0x28,
 263 -       FLASH = 0x30,
 264 -       ERSR = 0x36,
 265 -       ChipCmd = 0x37,
 266 -       TxPoll = 0x38,
 267 +       MAC0 = 0x0,             /* Ethernet hardware address. */
 268 +       MAR0 = 0x8,             /* Multicast filter. */
 269 +       TxDescStartAddr = 0x20,
 270 +       TxHDescStartAddr= 0x28,
 271 +       FLASH   = 0x30,
 272 +       ERSR    = 0x36,
 273 +       ChipCmd = 0x37,
 274 +       TxPoll  = 0x38,
 275         IntrMask = 0x3C,
 276         IntrStatus = 0x3E,
 277         TxConfig = 0x40,
 278         RxConfig = 0x44,
 279         RxMissed = 0x4C,
 280         Cfg9346 = 0x50,
 281 -       Config0 = 0x51,
 282 -       Config1 = 0x52,
 283 -       Config2 = 0x53,
 284 -       Config3 = 0x54,
 285 -       Config4 = 0x55,
 286 -       Config5 = 0x56,
 287 +       Config0 = 0x51,
 288 +       Config1 = 0x52,
 289 +       Config2 = 0x53,
 290 +       Config3 = 0x54,
 291 +       Config4 = 0x55,
 292 +       Config5 = 0x56,
 293         MultiIntr = 0x5C,
 294 -       PHYAR = 0x60,
 295 -       TBICSR = 0x64,
 296 +       PHYAR   = 0x60,
 297 +       TBICSR  = 0x64,
 298         TBI_ANAR = 0x68,
 299         TBI_LPAR = 0x6A,
 300         PHYstatus = 0x6C,
 301         RxMaxSize = 0xDA,
 302         CPlusCmd = 0xE0,
 303 -       RxDescStartAddr = 0xE4,
 304 -       EarlyTxThres = 0xEC,
 305 -       FuncEvent = 0xF0,
 306 -       FuncEventMask = 0xF4,
 307 -       FuncPresetState = 0xF8,
 308 -       FuncForceEvent = 0xFC,
 309 +       RxDescStartAddr = 0xE4,
 310 +       ETThReg = 0xEC,
 311 +       FuncEvent       = 0xF0,
 312 +       FuncEventMask   = 0xF4,
 313 +       FuncPresetState = 0xF8,
 314 +       FuncForceEvent  = 0xFC,
 315  };
 316
 317  enum RTL8169_register_content {
 318 -       /*InterruptStatusBits */
 319 -       SYSErr = 0x8000,
 320 -       PCSTimeout = 0x4000,
 321 -       SWInt = 0x0100,
 322 -       TxDescUnavail = 0x80,
 323 -       RxFIFOOver = 0x40,
 324 -       RxUnderrun = 0x20,
 325 -       RxOverflow = 0x10,
 326 -       TxErr = 0x08,
 327 -       TxOK = 0x04,
 328 -       RxErr = 0x02,
 329 -       RxOK = 0x01,
 330 +       /*InterruptStatusBits*/
 331 +       SYSErr          = 0x8000,
 332 +       PCSTimeout      = 0x4000,
 333 +       SWInt           = 0x0100,
 334 +       TxDescUnavail   = 0x80,
 335 +       RxFIFOOver      = 0x40,
 336 +       LinkChg         = 0x20,
 337 +       RxOverflow      = 0x10,
 338 +       TxErr   = 0x08,
 339 +       TxOK    = 0x04,
 340 +       RxErr   = 0x02,
 341 +       RxOK    = 0x01,
 342
 343 -       /*RxStatusDesc */
 344 +       /*RxStatusDesc*/
 345         RxRES = 0x00200000,
 346         RxCRC = 0x00080000,
 347 -       RxRUNT = 0x00100000,
 348 +       RxRUNT= 0x00100000,
 349         RxRWT = 0x00400000,
 350
 351 -       /*ChipCmdBits */
 352 +       /*ChipCmdBits*/
 353         CmdReset = 0x10,
 354         CmdRxEnb = 0x08,
 355         CmdTxEnb = 0x04,
 356         RxBufEmpty = 0x01,
 357
 358 -       /*Cfg9346Bits */
 359 +       /*Cfg9346Bits*/
 360         Cfg9346_Lock = 0x00,
 361         Cfg9346_Unlock = 0xC0,
 362
 363 -       /*rx_mode_bits */
 364 +       /*rx_mode_bits*/
 365         AcceptErr = 0x20,
 366         AcceptRunt = 0x10,
 367         AcceptBroadcast = 0x08,
 368 @@ -189,793 +301,1139 @@
 369         AcceptMyPhys = 0x02,
 370         AcceptAllPhys = 0x01,
 371
 372 -       /*RxConfigBits */
 373 +       /*RxConfigBits*/
 374         RxCfgFIFOShift = 13,
 375         RxCfgDMAShift = 8,
 376
 377 -       /*TxConfigBits */
 378 +       /*TxConfigBits*/
 379         TxInterFrameGapShift = 24,
 380         TxDMAShift = 8,         /* DMA burst value (0-7) is shift this many bits */
 381
 382 -       /*rtl8169_PHYstatus */
 383 -       TBI_Enable = 0x80,
 384 -       TxFlowCtrl = 0x40,
 385 -       RxFlowCtrl = 0x20,
 386 -       _1000bpsF = 0x10,
 387 -       _100bps = 0x08,
 388 -       _10bps = 0x04,
 389 -       LinkStatus = 0x02,
 390 -       FullDup = 0x01,
 391 +       /*rtl8169_PHYstatus*/
 392 +       TBI_Enable      = 0x80,
 393 +       TxFlowCtrl      = 0x40,
 394 +       RxFlowCtrl      = 0x20,
 395 +       _1000bpsF       = 0x10,
 396 +       _100bps         = 0x08,
 397 +       _10bps          = 0x04,
 398 +       LinkStatus      = 0x02,
 399 +       FullDup         = 0x01,
 400
 401 -       /*GIGABIT_PHY_registers */
 402 +       /*GIGABIT_PHY_registers*/
 403         PHY_CTRL_REG = 0,
 404         PHY_STAT_REG = 1,
 405         PHY_AUTO_NEGO_REG = 4,
 406         PHY_1000_CTRL_REG = 9,
 407
 408 -       /*GIGABIT_PHY_REG_BIT */
 409 -       PHY_Restart_Auto_Nego = 0x0200,
 410 -       PHY_Enable_Auto_Nego = 0x1000,
 411 +       /*GIGABIT_PHY_REG_BIT*/
 412 +       PHY_Restart_Auto_Nego   = 0x0200,
 413 +       PHY_Enable_Auto_Nego    = 0x1000,
 414
 415         //PHY_STAT_REG = 1;
 416 -       PHY_Auto_Neco_Comp = 0x0020,
 417 +       PHY_Auto_Neco_Comp      = 0x0020,
 418
 419         //PHY_AUTO_NEGO_REG = 4;
 420 -       PHY_Cap_10_Half = 0x0020,
 421 -       PHY_Cap_10_Full = 0x0040,
 422 -       PHY_Cap_100_Half = 0x0080,
 423 -       PHY_Cap_100_Full = 0x0100,
 424 +       PHY_Cap_10_Half         = 0x0020,
 425 +       PHY_Cap_10_Full         = 0x0040,
 426 +       PHY_Cap_100_Half        = 0x0080,
 427 +       PHY_Cap_100_Full        = 0x0100,
 428
 429         //PHY_1000_CTRL_REG = 9;
 430 -       PHY_Cap_1000_Full = 0x0200,
 431 +       PHY_Cap_1000_Full       = 0x0200,
 432 +
 433 +       PHY_Cap_Null            = 0x0,
 434
 435 -       PHY_Cap_Null = 0x0,
 436
 437         /*_MediaType*/
 438 -       _10_Half = 0x01,
 439 -       _10_Full = 0x02,
 440 -       _100_Half = 0x04,
 441 -       _100_Full = 0x08,
 442 -       _1000_Full = 0x10,
 443 +       _10_Half        = 0x01,
 444 +       _10_Full        = 0x02,
 445 +       _100_Half       = 0x04,
 446 +       _100_Full       = 0x08,
 447 +       _1000_Full      = 0x10,
 448
 449         /*_TBICSRBit*/
 450 -       TBILinkOK = 0x02000000,
 451 +       TBILinkOK       = 0x02000000,
 452  };
 453
 454 -const static struct {
 455 -       const char *name;
 456 -       u8 version;             /* depend on RTL8169 docs */
 457 -       u32 RxConfigMask;       /* should clear the bits supported by this chip */
 458 -} rtl_chip_info[] = {
 459 -       {
 460 -"RTL-8169", 0x00, 0xff7e1880,},};
 461 +
 462
 463  enum _DescStatusBit {
 464 -       OWNbit = 0x80000000,
 465 -       EORbit = 0x40000000,
 466 -       FSbit = 0x20000000,
 467 -       LSbit = 0x10000000,
 468 +       OWNbit  = 0x80000000,
 469 +       EORbit  = 0x40000000,
 470 +       FSbit   = 0x20000000,
 471 +       LSbit   = 0x10000000,
 472  };
 473
 474 +
 475  struct TxDesc {
 476 -       u32 status;
 477 -       u32 vlan_tag;
 478 -       u32 buf_addr;
 479 -       u32 buf_Haddr;
 480 +       u32             status;
 481 +       u32             vlan_tag;
 482 +       u32             buf_addr;
 483 +       u32             buf_Haddr;
 484  };
 485
 486  struct RxDesc {
 487 -       u32 status;
 488 -       u32 vlan_tag;
 489 -       u32 buf_addr;
 490 -       u32 buf_Haddr;
 491 +       u32             status;
 492 +       u32             vlan_tag;
 493 +       u32             buf_addr;
 494 +       u32             buf_Haddr;
 495  };
 496
 497 +//#ifndef timer_t
 498 +//typedef struct timer_list timer_t;
 499 +//#endif //#ifndef timer_t
 500 +
 501  struct rtl8169_private {
 502 -       void *mmio_addr;        /* memory map physical address */
 503 -       struct pci_dev *pci_dev;        /* Index of PCI device  */
 504 -       struct net_device_stats stats;  /* statistics of net device */
 505 -       spinlock_t lock;        /* spin lock flag */
 506 +       void *mmio_addr;                                /* memory map physical address*/
 507 +       struct pci_dev *pci_dev;                        /* Index of PCI device  */
 508 +       struct net_device_stats stats;                  /* statistics of net device */
 509 +       spinlock_t lock;                                /* spin lock flag */
 510         int chipset;
 511 -       unsigned long cur_rx;   /* Index into the Rx descriptor buffer of next Rx pkt. */
 512 -       unsigned long cur_tx;   /* Index into the Tx descriptor buffer of next Rx pkt. */
 513 +       int mac_version;
 514 +       int phy_version;
 515 +       struct timer_list phy_timer_t;
 516 +       unsigned long phy_link_down_cnt;
 517 +       unsigned long cur_rx;                           /* Index into the Rx descriptor buffer of next Rx pkt. */
 518 +       unsigned long cur_tx;                           /* Index into the Tx descriptor buffer of next Rx pkt. */
 519         unsigned long dirty_tx;
 520 -       unsigned char *TxDescArrays;    /* Index of Tx Descriptor buffer */
 521 -       unsigned char *RxDescArrays;    /* Index of Rx Descriptor buffer */
 522 -       struct TxDesc *TxDescArray;     /* Index of 256-alignment Tx Descriptor buffer */
 523 -       struct RxDesc *RxDescArray;     /* Index of 256-alignment Rx Descriptor buffer */
 524 -       unsigned char *RxBufferRings;   /* Index of Rx Buffer  */
 525 -       unsigned char *RxBufferRing[NUM_RX_DESC];       /* Index of Rx Buffer array */
 526 -       struct sk_buff *Tx_skbuff[NUM_TX_DESC]; /* Index of Transmit data buffer */
 527 +       unsigned char   *TxDescArrays;                  /* Index of Tx Descriptor buffer */
 528 +       unsigned char   *RxDescArrays;                  /* Index of Rx Descriptor buffer */
 529 +       struct  TxDesc  *TxDescArray;                   /* Index of 256-alignment Tx Descriptor buffer */
 530 +       struct  RxDesc  *RxDescArray;                   /* Index of 256-alignment Rx Descriptor buffer */
 531 +       struct  sk_buff *Tx_skbuff[NUM_TX_DESC];        /* Index of Transmit data buffer */
 532 +       struct  sk_buff *Rx_skbuff[NUM_RX_DESC];        /* Receive data buffer */
 533 +       unsigned char   drvinit_fail;
 534  };
 535
 536 -MODULE_AUTHOR("Realtek");
 537 -MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 538 -MODULE_PARM(media, "1-" __MODULE_STRING(MAX_UNITS) "i");
 539 -
 540 -static int rtl8169_open(struct net_device *dev);
 541 -static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
 542 -static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance,
 543 -                             struct pt_regs *regs);
 544 -static void rtl8169_init_ring(struct net_device *dev);
 545 -static void rtl8169_hw_start(struct net_device *dev);
 546 -static int rtl8169_close(struct net_device *dev);
 547 -static void rtl8169_set_rx_mode(struct net_device *dev);
 548 -static void rtl8169_tx_timeout(struct net_device *dev);
 549 +
 550 +MODULE_AUTHOR ("Realtek");
 551 +MODULE_DESCRIPTION ("RealTek RTL-8169 Gigabit Ethernet driver");
 552 +MODULE_PARM (media, "1-" __MODULE_STRING(MAX_UNITS) "i");
 553 +
 554 +static int rtl8169_open (struct net_device *dev);
 555 +static int rtl8169_start_xmit (struct sk_buff *skb, struct net_device *dev);
 556 +static irqreturn_t rtl8169_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
 557 +static void rtl8169_init_ring (struct net_device *dev);
 558 +static void rtl8169_hw_start (struct net_device *dev);
 559 +static int rtl8169_close (struct net_device *dev);
 560 +static inline u32 ether_crc (int length, unsigned char *data);
 561 +static void rtl8169_set_rx_mode (struct net_device *dev);
 562 +static void rtl8169_tx_timeout (struct net_device *dev);
 563  static struct net_device_stats *rtl8169_get_stats(struct net_device *netdev);
 564
 565 -static const u16 rtl8169_intr_mask =
 566 -    SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr | TxOK |
 567 -    RxErr | RxOK;
 568 -static const unsigned int rtl8169_rx_config =
 569 -    (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 570 +static void rtl8169_hw_PHY_config (struct net_device *dev);
 571 +static void rtl8169_hw_PHY_reset(struct net_device *dev);
 572 +static const u16 rtl8169_intr_mask = LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK ;
 573 +static const unsigned int rtl8169_rx_config = (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift) ;
 574
 575 -void
 576 -mdio_write(void *ioaddr, int RegAddr, int value)
 577 +
 578 +#define RTL8169_WRITE_GMII_REG_BIT( ioaddr, reg, bitnum, bitval )\
 579 +{ \
 580 +       int val; \
 581 +       if( bitval == 1 ){ val = ( RTL8169_READ_GMII_REG( ioaddr, reg ) | (bitval<<bitnum) ) & 0xffff ; } \
 582 +       else{ val = ( RTL8169_READ_GMII_REG( ioaddr, reg ) & (~(0x0001<<bitnum)) ) & 0xffff ; } \
 583 +       RTL8169_WRITE_GMII_REG( ioaddr, reg, val ); \
 584 +}
 585 +
 586 +
 587 +
 588 +#ifdef RTL8169_DEBUG
 589 +unsigned alloc_rxskb_cnt = 0;
 590 +#define RTL8169_ALLOC_RXSKB(bufsize)   dev_alloc_skb(bufsize); alloc_rxskb_cnt ++ ;
 591 +#define RTL8169_FREE_RXSKB(skb)        kfree_skb(skb); alloc_rxskb_cnt -- ;
 592 +#define RTL8169_NETIF_RX(skb)          netif_rx(skb); alloc_rxskb_cnt -- ;
 593 +#else
 594 +#define RTL8169_ALLOC_RXSKB(bufsize)   dev_alloc_skb(bufsize);
 595 +#define RTL8169_FREE_RXSKB(skb)        kfree_skb(skb);
 596 +#define RTL8169_NETIF_RX(skb)          netif_rx(skb);
 597 +#endif //end #ifdef RTL8169_DEBUG
 598 +
 599 +
 600 +
 601 +
 602 +//=================================================================
 603 +//     PHYAR
 604 +//     bit             Symbol
 605 +//     31              Flag
 606 +//     30-21   reserved
 607 +//     20-16   5-bit GMII/MII register address
 608 +//     15-0    16-bit GMII/MII register data
 609 +//=================================================================
 610 +void RTL8169_WRITE_GMII_REG( void *ioaddr, int RegAddr, int value )
 611  {
 612 -       int i;
 613 +       int     i;
 614
 615 -       RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
 616 +       RTL_W32 ( PHYAR, 0x80000000 | (RegAddr&0xFF)<<16 | value);
 617         udelay(1000);
 618
 619 -       for (i = 2000; i > 0; i--) {
 620 +       for( i = 2000; i > 0 ; i -- ){
 621                 // Check if the RTL8169 has completed writing to the specified MII register
 622 -               if (!(RTL_R32(PHYAR) & 0x80000000)) {
 623 +               if( ! (RTL_R32(PHYAR)&0x80000000) ){
 624                         break;
 625 -               } else {
 626 -                       udelay(100);
 627                 }
 628 -       }
 629 +               else{
 630 +                       udelay(100);
 631 +               }// end of if( ! (RTL_R32(PHYAR)&0x80000000) )
 632 +       }// end of for() loop
 633  }
 634 -
 635 -int
 636 -mdio_read(void *ioaddr, int RegAddr)
 637 +//=================================================================
 638 +int RTL8169_READ_GMII_REG( void *ioaddr, int RegAddr )
 639  {
 640         int i, value = -1;
 641
 642 -       RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
 643 +       RTL_W32 ( PHYAR, 0x0 | (RegAddr&0xFF)<<16 );
 644         udelay(1000);
 645
 646 -       for (i = 2000; i > 0; i--) {
 647 +       for( i = 2000; i > 0 ; i -- ){
 648                 // Check if the RTL8169 has completed retrieving data from the specified MII register
 649 -               if (RTL_R32(PHYAR) & 0x80000000) {
 650 -                       value = (int) (RTL_R32(PHYAR) & 0xFFFF);
 651 +               if( RTL_R32(PHYAR) & 0x80000000 ){
 652 +                       value = (int)( RTL_R32(PHYAR)&0xFFFF );
 653                         break;
 654 -               } else {
 655 +               }
 656 +               else{
 657                         udelay(100);
 658 +               }// end of if( RTL_R32(PHYAR) & 0x80000000 )
 659 +       }// end of for() loop
 660 +       return value;
 661 +}
 662 +
 663 +
 664 +
 665 +#define rtl8169_request_timer( timer, timer_expires, timer_func, timer_data ) \
 666 +{ \
 667 +       init_timer(timer); \
 668 +       timer->expires = (unsigned long)(jiffies + timer_expires); \
 669 +       timer->data = (unsigned long)(timer_data); \
 670 +       timer->function = (void *)(timer_func); \
 671 +       add_timer(timer); \
 672 +       DBG_PRINT("request_timer at 0x%08lx\n", (unsigned long)timer); \
 673 +}
 674 +
 675 +#define rtl8169_delete_timer( del_timer_t ) \
 676 +{ \
 677 +       del_timer(del_timer_t); \
 678 +       DBG_PRINT("delete_timer at 0x%08lx\n", (unsigned long)del_timer_t); \
 679 +}
 680 +
 681 +#define rtl8169_mod_timer( timer, timer_expires ) \
 682 +{ \
 683 +       mod_timer( timer, jiffies + timer_expires ); \
 684 +}
 685 +
 686 +
 687 +
 688 +
 689 +//======================================================================================================
 690 +//======================================================================================================
 691 +void rtl8169_phy_timer_t_handler( void *timer_data )
 692 +{
 693 +       struct net_device *dev = (struct net_device *)timer_data;
 694 +       struct rtl8169_private *priv = (struct rtl8169_private *) (dev->priv);
 695 +       void *ioaddr = priv->mmio_addr;
 696 +
 697 +       assert( priv->mac_version > RTL_GIGA_MAC_VER_B );
 698 +       assert( priv->phy_version < RTL_GIGA_PHY_VER_G );
 699 +
 700 +       if( RTL_R8(PHYstatus) & LinkStatus ){
 701 +               priv->phy_link_down_cnt = 0 ;
 702 +       }
 703 +       else{
 704 +               priv->phy_link_down_cnt ++ ;
 705 +               if( priv->phy_link_down_cnt >= 12 ){
 706 +                       // If link on 1000, perform phy reset.
 707 +                       if( RTL8169_READ_GMII_REG( ioaddr, PHY_1000_CTRL_REG ) & PHY_Cap_1000_Full )
 708 +                       {
 709 +                               rtl8169_hw_PHY_reset( dev );
 710 +                       }
 711 +
 712 +                       priv->phy_link_down_cnt = 0 ;
 713                 }
 714         }
 715 -       return value;
 716 +
 717 +       //---------------------------------------------------------------------------
 718 +       //mod_timer is a more efficient way to update the expire field of an active timer.
 719 +       //---------------------------------------------------------------------------
 720 +       rtl8169_mod_timer( (&priv->phy_timer_t), 100 );
 721  }
 722
 723 -static int __devinit
 724 -rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
 725 -                  void **ioaddr_out)
 726 +
 727 +
 728 +
 729 +//======================================================================================================
 730 +//======================================================================================================
 731 +static int __devinit rtl8169_init_board ( struct pci_dev *pdev, struct net_device **dev_out, void **ioaddr_out)
 732  {
 733         void *ioaddr = NULL;
 734         struct net_device *dev;
 735 -       struct rtl8169_private *tp;
 736 +       struct rtl8169_private *priv;
 737         int rc, i;
 738         unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
 739 -       u32 tmp;
 740
 741 -       assert(pdev != NULL);
 742 -       assert(ioaddr_out != NULL);
 743 +
 744 +       assert (pdev != NULL);
 745 +       assert (ioaddr_out != NULL);
 746
 747         *ioaddr_out = NULL;
 748         *dev_out = NULL;
 749
 750 -       // dev zeroed in alloc_etherdev
 751 -       dev = alloc_etherdev(sizeof (*tp));
 752 +       // dev zeroed in init_etherdev
 753 +       dev = init_etherdev (NULL, sizeof (*priv));
 754         if (dev == NULL) {
 755 -               printk(KERN_ERR PFX "unable to alloc new ethernet\n");
 756 +               printk (KERN_ERR PFX "unable to alloc new ethernet\n");
 757                 return -ENOMEM;
 758         }
 759
 760         SET_MODULE_OWNER(dev);
 761 -       SET_NETDEV_DEV(dev, &pdev->dev);
 762 -       tp = dev->priv;
 763 +       priv = dev->priv;
 764
 765         // enable device (incl. PCI PM wakeup and hotplug setup)
 766 -       rc = pci_enable_device(pdev);
 767 +       rc = pci_enable_device (pdev);
 768         if (rc)
 769                 goto err_out;
 770
 771 -       mmio_start = pci_resource_start(pdev, 1);
 772 -       mmio_end = pci_resource_end(pdev, 1);
 773 -       mmio_flags = pci_resource_flags(pdev, 1);
 774 -       mmio_len = pci_resource_len(pdev, 1);
 775 +       mmio_start = pci_resource_start (pdev, 1);
 776 +       mmio_end = pci_resource_end (pdev, 1);
 777 +       mmio_flags = pci_resource_flags (pdev, 1);
 778 +       mmio_len = pci_resource_len (pdev, 1);
 779
 780         // make sure PCI base addr 1 is MMIO
 781         if (!(mmio_flags & IORESOURCE_MEM)) {
 782 -               printk(KERN_ERR PFX
 783 -                      "region #1 not an MMIO resource, aborting\n");
 784 +               printk (KERN_ERR PFX "region #1 not an MMIO resource, aborting\n");
 785                 rc = -ENODEV;
 786 -               goto err_out_disable;
 787 +               goto err_out;
 788         }
 789 +
 790         // check for weird/broken PCI region reporting
 791 -       if (mmio_len < RTL_MIN_IO_SIZE) {
 792 -               printk(KERN_ERR PFX "Invalid PCI region size(s), aborting\n");
 793 +       if ( mmio_len < RTL_MIN_IO_SIZE ) {
 794 +               printk (KERN_ERR PFX "Invalid PCI region size(s), aborting\n");
 795                 rc = -ENODEV;
 796 -               goto err_out_disable;
 797 +               goto err_out;
 798         }
 799
 800 -       rc = pci_request_regions(pdev, dev->name);
 801 +
 802 +       rc = pci_request_regions (pdev, dev->name);
 803         if (rc)
 804 -               goto err_out_disable;
 805 +               goto err_out;
 806
 807         // enable PCI bus-mastering
 808 -       pci_set_master(pdev);
 809 +       pci_set_master (pdev);
 810 +
 811
 812 -       // ioremap MMIO region
 813 -       ioaddr = ioremap(mmio_start, mmio_len);
 814 +       // ioremap MMIO region
 815 +       ioaddr = ioremap (mmio_start, mmio_len);
 816         if (ioaddr == NULL) {
 817 -               printk(KERN_ERR PFX "cannot remap MMIO, aborting\n");
 818 +               printk (KERN_ERR PFX "cannot remap MMIO, aborting\n");
 819                 rc = -EIO;
 820                 goto err_out_free_res;
 821         }
 822
 823 -       // Soft reset the chip.
 824 -       RTL_W8(ChipCmd, CmdReset);
 825 +
 826 +       // Soft reset the chip.
 827 +       RTL_W8 ( ChipCmd, CmdReset);
 828
 829         // Check that the chip has finished the reset.
 830 -       for (i = 1000; i > 0; i--)
 831 -               if ((RTL_R8(ChipCmd) & CmdReset) == 0)
 832 +       for (i = 1000; i > 0; i--){
 833 +               if ( (RTL_R8(ChipCmd) & CmdReset) == 0){
 834                         break;
 835 -               else
 836 -                       udelay(10);
 837 +               }
 838 +               else{
 839 +                       udelay (10);
 840 +               }
 841 +       }
 842
 843         // identify chip attached to board
 844 -       tmp = RTL_R32(TxConfig);
 845 -       tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24;
 846 +       RTL_GET_MAC_VERSION(priv->mac_version);
 847 +       RTL_GET_PHY_VERSION(priv->phy_version);
 848 +
 849 +       RTL_PRINT_MAC_VERSION(priv->mac_version);
 850 +       RTL_PRINT_PHY_VERSION(priv->phy_version);
 851 +
 852
 853 -       for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--)
 854 -               if (tmp == rtl_chip_info[i].version) {
 855 -                       tp->chipset = i;
 856 +
 857 +       for (i = ARRAY_SIZE (rtl_chip_info) - 1; i >= 0; i--){
 858 +               if (priv->mac_version == rtl_chip_info[i].mac_version) {
 859 +                       priv->chipset = i;
 860                         goto match;
 861                 }
 862 +       }
 863 +
 864         //if unknown chip, assume array element #0, original RTL-8169 in this case
 865 -       printk(KERN_DEBUG PFX
 866 -              "PCI device %s: unknown chip version, assuming RTL-8169\n",
 867 -              pci_name(pdev));
 868 -       printk(KERN_DEBUG PFX "PCI device %s: TxConfig = 0x%lx\n",
 869 -              pci_name(pdev), (unsigned long) RTL_R32(TxConfig));
 870 -       tp->chipset = 0;
 871 +       printk (KERN_DEBUG PFX "PCI device %s: unknown chip version, assuming RTL-8169\n", pdev->slot_name);
 872 +       priv->chipset = 0;
 873
 874  match:
 875 +
 876         *ioaddr_out = ioaddr;
 877         *dev_out = dev;
 878         return 0;
 879
 880 -err_out_free_res:
 881 -       pci_release_regions(pdev);
 882 +//err_out_iounmap:
 883 +//     assert (ioaddr > 0);
 884 +//     iounmap (ioaddr);
 885
 886 -err_out_disable:
 887 -       pci_disable_device(pdev);
 888 +err_out_free_res:
 889 +       pci_release_regions (pdev);
 890
 891  err_out:
 892 -       free_netdev(dev);
 893 +       unregister_netdev (dev);
 894 +       kfree (dev);
 895         return rc;
 896  }
 897
 898 -static int __devinit
 899 -rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 900 +
 901 +
 902 +
 903 +
 904 +
 905 +
 906 +//======================================================================================================
 907 +static int __devinit rtl8169_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
 908  {
 909         struct net_device *dev = NULL;
 910 -       struct rtl8169_private *tp = NULL;
 911 +       struct rtl8169_private *priv = NULL;
 912         void *ioaddr = NULL;
 913         static int board_idx = -1;
 914 -       static int printed_version = 0;
 915 -       int i, rc;
 916 +       int i;
 917         int option = -1, Cap10_100 = 0, Cap1000 = 0;
 918
 919 -       assert(pdev != NULL);
 920 -       assert(ent != NULL);
 921 +
 922 +       assert (pdev != NULL);
 923 +       assert (ent != NULL);
 924
 925         board_idx++;
 926
 927 -       if (!printed_version) {
 928 -               printk(KERN_INFO RTL8169_DRIVER_NAME " loaded\n");
 929 -               printed_version = 1;
 930 +
 931 +       i = rtl8169_init_board (pdev, &dev, &ioaddr);
 932 +       if (i < 0) {
 933 +               return i;
 934         }
 935
 936 -       rc = rtl8169_init_board(pdev, &dev, &ioaddr);
 937 -       if (rc)
 938 -               return rc;
 939 +       priv = dev->priv;
 940
 941 -       tp = dev->priv;
 942 -       assert(ioaddr != NULL);
 943 -       assert(dev != NULL);
 944 -       assert(tp != NULL);
 945 -
 946 -       // Get MAC address.  FIXME: read EEPROM
 947 -       for (i = 0; i < MAC_ADDR_LEN; i++)
 948 -               dev->dev_addr[i] = RTL_R8(MAC0 + i);
 949 -
 950 -       dev->open = rtl8169_open;
 951 -       dev->hard_start_xmit = rtl8169_start_xmit;
 952 -       dev->get_stats = rtl8169_get_stats;
 953 -       dev->stop = rtl8169_close;
 954 -       dev->tx_timeout = rtl8169_tx_timeout;
 955 -       dev->set_multicast_list = rtl8169_set_rx_mode;
 956 -       dev->watchdog_timeo = TX_TIMEOUT;
 957 -       dev->irq = pdev->irq;
 958 -       dev->base_addr = (unsigned long) ioaddr;
 959 -//      dev->do_ioctl           = mii_ioctl;
 960 -
 961 -       tp = dev->priv;         // private data //
 962 -       tp->pci_dev = pdev;
 963 -       tp->mmio_addr = ioaddr;
 964 -
 965 -       spin_lock_init(&tp->lock);
 966 -
 967 -       rc = register_netdev(dev);
 968 -       if (rc) {
 969 -               iounmap(ioaddr);
 970 -               pci_release_regions(pdev);
 971 -               pci_disable_device(pdev);
 972 -               free_netdev(dev);
 973 -               return rc;
 974 +       assert (ioaddr != NULL);
 975 +       assert (dev != NULL);
 976 +       assert (priv != NULL);
 977 +
 978 +       // Get MAC address //
 979 +       for (i = 0; i < MAC_ADDR_LEN ; i++){
 980 +               dev->dev_addr[i] = RTL_R8( MAC0 + i );
 981         }
 982
 983 -       printk(KERN_DEBUG "%s: Identified chip type is '%s'.\n", dev->name,
 984 -              rtl_chip_info[tp->chipset].name);
 985 +       dev->open               = rtl8169_open;
 986 +       dev->hard_start_xmit    = rtl8169_start_xmit;
 987 +       dev->get_stats          = rtl8169_get_stats;
 988 +       dev->stop               = rtl8169_close;
 989 +       dev->tx_timeout         = rtl8169_tx_timeout;
 990 +       dev->set_multicast_list = rtl8169_set_rx_mode;
 991 +       dev->watchdog_timeo     = TX_TIMEOUT;
 992 +       dev->irq                = pdev->irq;
 993 +       dev->base_addr          = (unsigned long) ioaddr;
 994 +//     dev->do_ioctl           = mii_ioctl;
 995 +
 996 +       priv = dev->priv;                               // private data //
 997 +       priv->pci_dev   = pdev;
 998 +       priv->mmio_addr         = ioaddr;
 999 +
1000 +       spin_lock_init (&priv->lock);
1001
1002 +       //pdev->driver_data = dev;
1003         pci_set_drvdata(pdev, dev);
1004
1005 -       printk(KERN_INFO "%s: %s at 0x%lx, "
1006 -              "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1007 -              "IRQ %d\n",
1008 -              dev->name,
1009 -              board_info[ent->driver_data].name,
1010 -              dev->base_addr,
1011 -              dev->dev_addr[0], dev->dev_addr[1],
1012 -              dev->dev_addr[2], dev->dev_addr[3],
1013 -              dev->dev_addr[4], dev->dev_addr[5], dev->irq);
1014 +       printk (KERN_DEBUG "%s: Identified chip type is '%s'.\n",dev->name,rtl_chip_info[priv->chipset].name);
1015 +       printk (KERN_INFO "%s: %s at 0x%lx, "
1016 +                               "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1017 +                               "IRQ %d\n",
1018 +                               dev->name,
1019 +                               RTL8169_DRIVER_NAME,
1020 +                               dev->base_addr,
1021 +                               dev->dev_addr[0], dev->dev_addr[1],
1022 +                               dev->dev_addr[2], dev->dev_addr[3],
1023 +                               dev->dev_addr[4], dev->dev_addr[5],
1024 +                               dev->irq);
1025 +
1026 +
1027 +       // Config PHY
1028 +       rtl8169_hw_PHY_config(dev);
1029 +
1030 +       DBG_PRINT("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1031 +       RTL_W8( 0x82, 0x01 );
1032 +
1033 +
1034 +       if( priv->mac_version < RTL_GIGA_MAC_VER_E ){
1035 +               DBG_PRINT("Set PCI Latency=0x40\n");
1036 +               pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
1037 +       }
1038 +
1039 +       if( priv->mac_version == RTL_GIGA_MAC_VER_D ){
1040 +               DBG_PRINT("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1041 +               RTL_W8( 0x82, 0x01 );
1042 +               DBG_PRINT("Set PHY Reg 0x0bh = 0x00h\n");
1043 +               RTL8169_WRITE_GMII_REG( ioaddr, 0x0b, 0x0000 ); //w 0x0b 15 0 0
1044 +       }
1045
1046         // if TBI is not endbled
1047 -       if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
1048 -               int val = mdio_read(ioaddr, PHY_AUTO_NEGO_REG);
1049 +       if( !(RTL_R8(PHYstatus) & TBI_Enable) ){
1050 +               int     val = RTL8169_READ_GMII_REG( ioaddr, PHY_AUTO_NEGO_REG );
1051
1052                 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1053                 // Force RTL8169 in 10/100/1000 Full/Half mode.
1054 -               if (option > 0) {
1055 -                       printk(KERN_INFO "%s: Force-mode Enabled.\n",
1056 -                              dev->name);
1057 -                       Cap10_100 = 0, Cap1000 = 0;
1058 -                       switch (option) {
1059 -                       case _10_Half:
1060 -                               Cap10_100 = PHY_Cap_10_Half;
1061 -                               Cap1000 = PHY_Cap_Null;
1062 -                               break;
1063 -                       case _10_Full:
1064 -                               Cap10_100 = PHY_Cap_10_Full;
1065 -                               Cap1000 = PHY_Cap_Null;
1066 -                               break;
1067 -                       case _100_Half:
1068 -                               Cap10_100 = PHY_Cap_100_Half;
1069 -                               Cap1000 = PHY_Cap_Null;
1070 -                               break;
1071 -                       case _100_Full:
1072 -                               Cap10_100 = PHY_Cap_100_Full;
1073 -                               Cap1000 = PHY_Cap_Null;
1074 -                               break;
1075 -                       case _1000_Full:
1076 -                               Cap10_100 = PHY_Cap_Null;
1077 -                               Cap1000 = PHY_Cap_1000_Full;
1078 -                               break;
1079 -                       default:
1080 -                               break;
1081 +               if( option > 0 ){
1082 +                       printk(KERN_INFO "%s: Force-mode Enabled. \n", dev->name);
1083 +                       Cap10_100 = 0;
1084 +                       Cap1000 = 0;
1085 +                       switch( option ){
1086 +                               case _10_Half:
1087 +                                               Cap10_100 = PHY_Cap_10_Half;
1088 +                                               Cap1000 = PHY_Cap_Null;
1089 +                                               break;
1090 +                               case _10_Full:
1091 +                                               Cap10_100 = PHY_Cap_10_Full | PHY_Cap_10_Half;
1092 +                                               Cap1000 = PHY_Cap_Null;
1093 +                                               break;
1094 +                               case _100_Half:
1095 +                                               Cap10_100 = PHY_Cap_100_Half | PHY_Cap_10_Full | PHY_Cap_10_Half;
1096 +                                               Cap1000 = PHY_Cap_Null;
1097 +                                               break;
1098 +                               case _100_Full:
1099 +                                               Cap10_100 = PHY_Cap_100_Full | PHY_Cap_100_Half | PHY_Cap_10_Full | PHY_Cap_10_Half;
1100 +                                               Cap1000 = PHY_Cap_Null;
1101 +                                               break;
1102 +                               case _1000_Full:
1103 +                                               Cap10_100 = PHY_Cap_100_Full | PHY_Cap_100_Half | PHY_Cap_10_Full | PHY_Cap_10_Half;
1104 +                                               Cap1000 = PHY_Cap_1000_Full;
1105 +                                               break;
1106 +                               default:
1107 +                                               break;
1108                         }
1109 -                       mdio_write(ioaddr, PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F));        //leave PHY_AUTO_NEGO_REG bit4:0 unchanged
1110 -                       mdio_write(ioaddr, PHY_1000_CTRL_REG, Cap1000);
1111 -               } else {
1112 -                       printk(KERN_INFO "%s: Auto-negotiation Enabled.\n",
1113 -                              dev->name);
1114 +                       RTL8169_WRITE_GMII_REG( ioaddr, PHY_AUTO_NEGO_REG, Cap10_100 | ( val&0x1F ) );  //leave PHY_AUTO_NEGO_REG bit4:0 unchanged
1115 +                       RTL8169_WRITE_GMII_REG( ioaddr, PHY_1000_CTRL_REG, Cap1000 );
1116 +               }
1117 +               else{
1118 +                       printk(KERN_INFO "%s: Auto-negotiation Enabled.\n", dev->name);
1119
1120                         // enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged
1121 -                       mdio_write(ioaddr, PHY_AUTO_NEGO_REG,
1122 -                                  PHY_Cap_10_Half | PHY_Cap_10_Full |
1123 -                                  PHY_Cap_100_Half | PHY_Cap_100_Full | (val &
1124 -                                                                         0x1F));
1125 +                       RTL8169_WRITE_GMII_REG( ioaddr, PHY_AUTO_NEGO_REG,
1126 +                               PHY_Cap_10_Half | PHY_Cap_10_Full | PHY_Cap_100_Half | PHY_Cap_100_Full | ( val&0x1F ) );
1127
1128                         // enable 1000 Full Mode
1129 -                       mdio_write(ioaddr, PHY_1000_CTRL_REG,
1130 -                                  PHY_Cap_1000_Full);
1131 +                       RTL8169_WRITE_GMII_REG( ioaddr, PHY_1000_CTRL_REG, PHY_Cap_1000_Full );
1132
1133 -               }
1134 +               }// end of if( option > 0 )
1135
1136                 // Enable auto-negotiation and restart auto-nigotiation
1137 -               mdio_write(ioaddr, PHY_CTRL_REG,
1138 -                          PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego);
1139 +               RTL8169_WRITE_GMII_REG( ioaddr, PHY_CTRL_REG, PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego );
1140                 udelay(100);
1141
1142                 // wait for auto-negotiation process
1143 -               for (i = 10000; i > 0; i--) {
1144 +               for( i = 10000; i > 0; i-- ){
1145                         //check if auto-negotiation complete
1146 -                       if (mdio_read(ioaddr, PHY_STAT_REG) &
1147 -                           PHY_Auto_Neco_Comp) {
1148 +                       if( RTL8169_READ_GMII_REG(ioaddr, PHY_STAT_REG) & PHY_Auto_Neco_Comp ){
1149                                 udelay(100);
1150                                 option = RTL_R8(PHYstatus);
1151 -                               if (option & _1000bpsF) {
1152 -                                       printk(KERN_INFO
1153 -                                              "%s: 1000Mbps Full-duplex operation.\n",
1154 -                                              dev->name);
1155 -                               } else {
1156 -                                       printk(KERN_INFO
1157 -                                              "%s: %sMbps %s-duplex operation.\n",
1158 -                                              dev->name,
1159 -                                              (option & _100bps) ? "100" :
1160 -                                              "10",
1161 -                                              (option & FullDup) ? "Full" :
1162 -                                              "Half");
1163 +                               if( option & _1000bpsF ){
1164 +                                       printk(KERN_INFO "%s: 1000Mbps Full-duplex operation.\n", dev->name);
1165 +                               }
1166 +                               else{
1167 +                                       printk(KERN_INFO "%s: %sMbps %s-duplex operation.\n", dev->name,
1168 +                                                       (option & _100bps) ? "100" : "10", (option & FullDup) ? "Full" : "Half" );
1169                                 }
1170                                 break;
1171 -                       } else {
1172 -                               udelay(100);
1173                         }
1174 -               }               // end for-loop to wait for auto-negotiation process
1175 +                       else{
1176 +                               udelay(100);
1177 +                       }// end of if( RTL8169_READ_GMII_REG(ioaddr, 1) & 0x20 )
1178 +               }// end for-loop to wait for auto-negotiation process
1179
1180 -       } else {
1181 +       }// end of TBI is not enabled
1182 +       else{
1183                 udelay(100);
1184 -               printk(KERN_INFO
1185 -                      "%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
1186 -                      dev->name,
1187 -                      (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
1188 +               printk(KERN_INFO "%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
1189 +                                                       dev->name, (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed" );
1190
1191 -       }
1192 +       }// end of TBI is not enabled
1193
1194         return 0;
1195  }
1196
1197 -static void __devexit
1198 -rtl8169_remove_one(struct pci_dev *pdev)
1199 +
1200 +
1201 +
1202 +
1203 +
1204 +
1205 +//======================================================================================================
1206 +static void __devexit rtl8169_remove_one (struct pci_dev *pdev)
1207  {
1208 +       //struct net_device *dev = pdev->driver_data;
1209         struct net_device *dev = pci_get_drvdata(pdev);
1210 -       struct rtl8169_private *tp = dev->priv;
1211 +       struct rtl8169_private *priv = (struct rtl8169_private *) (dev->priv);
1212
1213 -       assert(dev != NULL);
1214 -       assert(tp != NULL);
1215 +       assert (dev != NULL);
1216 +       assert (priv != NULL);
1217
1218 -       unregister_netdev(dev);
1219 -       iounmap(tp->mmio_addr);
1220 -       pci_release_regions(pdev);
1221 +       unregister_netdev (dev);
1222 +       iounmap (priv->mmio_addr);
1223 +       pci_release_regions (pdev);
1224
1225 -       // poison memory before freeing
1226 -       memset(dev, 0xBC,
1227 -              sizeof (struct net_device) + sizeof (struct rtl8169_private));
1228 +       // poison memory before freeing
1229 +       memset (dev, 0xBC, sizeof (struct net_device) + sizeof (struct rtl8169_private));
1230
1231 -       pci_disable_device(pdev);
1232 -       free_netdev(dev);
1233 +       kfree (dev);
1234 +       //pdev->driver_data = NULL;
1235         pci_set_drvdata(pdev, NULL);
1236  }
1237
1238 -static int
1239 -rtl8169_open(struct net_device *dev)
1240 +
1241 +
1242 +
1243 +
1244 +
1245 +
1246 +//======================================================================================================
1247 +static int rtl8169_open (struct net_device *dev)
1248  {
1249 -       struct rtl8169_private *tp = dev->priv;
1250 +       struct rtl8169_private *priv = dev->priv;
1251         int retval;
1252         u8 diff;
1253         u32 TxPhyAddr, RxPhyAddr;
1254
1255 -       retval =
1256 -           request_irq(dev->irq, rtl8169_interrupt, SA_SHIRQ, dev->name, dev);
1257 +
1258 +       if( priv->drvinit_fail == 1 ){
1259 +               printk("%s: Gigabit driver open failed.\n", dev->name );
1260 +               return -ENOMEM;
1261 +       }
1262 +
1263 +       retval = request_irq (dev->irq, rtl8169_interrupt, SA_SHIRQ, dev->name, dev);
1264         if (retval) {
1265                 return retval;
1266         }
1267
1268 -       tp->TxDescArrays =
1269 -           kmalloc(NUM_TX_DESC * sizeof (struct TxDesc) + 256, GFP_KERNEL);
1270 +
1271 +       //////////////////////////////////////////////////////////////////////////////
1272 +       priv->TxDescArrays = kmalloc( NUM_TX_DESC * sizeof(struct TxDesc)+256 , GFP_KERNEL );
1273         // Tx Desscriptor needs 256 bytes alignment;
1274 -       TxPhyAddr = virt_to_bus(tp->TxDescArrays);
1275 -       diff = 256 - (TxPhyAddr - ((TxPhyAddr >> 8) << 8));
1276 +       TxPhyAddr = virt_to_bus(priv->TxDescArrays);
1277 +       diff = 256 - (TxPhyAddr-((TxPhyAddr >> 8)<< 8));
1278         TxPhyAddr += diff;
1279 -       tp->TxDescArray = (struct TxDesc *) (tp->TxDescArrays + diff);
1280 +       priv->TxDescArray = (struct TxDesc *)(priv->TxDescArrays + diff);
1281
1282 -       tp->RxDescArrays =
1283 -           kmalloc(NUM_RX_DESC * sizeof (struct RxDesc) + 256, GFP_KERNEL);
1284 +       priv->RxDescArrays = kmalloc( NUM_RX_DESC * sizeof(struct RxDesc)+256 , GFP_KERNEL );
1285         // Rx Desscriptor needs 256 bytes alignment;
1286 -       RxPhyAddr = virt_to_bus(tp->RxDescArrays);
1287 -       diff = 256 - (RxPhyAddr - ((RxPhyAddr >> 8) << 8));
1288 +       RxPhyAddr = virt_to_bus(priv->RxDescArrays);
1289 +       diff = 256 - (RxPhyAddr-((RxPhyAddr >> 8)<< 8));
1290         RxPhyAddr += diff;
1291 -       tp->RxDescArray = (struct RxDesc *) (tp->RxDescArrays + diff);
1292 +       priv->RxDescArray = (struct RxDesc *)(priv->RxDescArrays + diff);
1293
1294 -       if (tp->TxDescArrays == NULL || tp->RxDescArrays == NULL) {
1295 -               printk(KERN_INFO
1296 -                      "Allocate RxDescArray or TxDescArray failed\n");
1297 +       if ( priv->TxDescArrays == NULL || priv->RxDescArrays == NULL ) {
1298 +               printk(KERN_INFO"Allocate RxDescArray or TxDescArray failed\n");
1299                 free_irq(dev->irq, dev);
1300 -               if (tp->TxDescArrays)
1301 -                       kfree(tp->TxDescArrays);
1302 -               if (tp->RxDescArrays)
1303 -                       kfree(tp->RxDescArrays);
1304 +               if (priv->TxDescArrays) kfree(priv->TxDescArrays);
1305 +               if (priv->RxDescArrays) kfree(priv->RxDescArrays);
1306                 return -ENOMEM;
1307         }
1308 -       tp->RxBufferRings = kmalloc(RX_BUF_SIZE * NUM_RX_DESC, GFP_KERNEL);
1309 -       if (tp->RxBufferRings == NULL) {
1310 -               printk(KERN_INFO "Allocate RxBufferRing failed\n");
1311 +
1312 +       {
1313 +        int i;
1314 +               struct sk_buff *skb = NULL;
1315 +
1316 +               for(i=0;i<NUM_RX_DESC;i++){
1317 +                       skb = RTL8169_ALLOC_RXSKB(MAX_RX_SKBDATA_SIZE);
1318 +                       if( skb != NULL ) {
1319 +                               skb_reserve (skb, 2);   // 16 byte align the IP fields. //
1320 +                               priv->Rx_skbuff[i] = skb;
1321 +                       }
1322 +                       else{
1323 +                               printk("%s: Gigabit driver failed to allocate skbuff.\n", dev->name);
1324 +                               priv->drvinit_fail = 1;
1325 +                       }
1326 +               }
1327 +       }
1328 +
1329 +
1330 +       //////////////////////////////////////////////////////////////////////////////
1331 +       rtl8169_init_ring (dev);
1332 +       rtl8169_hw_start (dev);
1333 +
1334 +       // ------------------------------------------------------
1335 +       if( (priv->mac_version > RTL_GIGA_MAC_VER_B) && (priv->phy_version < RTL_GIGA_PHY_VER_G) ){
1336 +               DBG_PRINT("FIX PCS -> rtl8169_request_timer\n");
1337 +               rtl8169_request_timer( (&priv->phy_timer_t), 100, rtl8169_phy_timer_t_handler, ((void *)dev) );  //in open()
1338 +               priv->phy_link_down_cnt = 0;
1339         }
1340
1341 -       rtl8169_init_ring(dev);
1342 -       rtl8169_hw_start(dev);
1343 +       DBG_PRINT("%s: %s() alloc_rxskb_cnt = %d\n", dev->name, __FUNCTION__, alloc_rxskb_cnt );
1344
1345         return 0;
1346
1347 +}//end of rtl8169_open (struct net_device *dev)
1348 +
1349 +
1350 +
1351 +
1352 +
1353 +//======================================================================================================
1354 +static void rtl8169_hw_PHY_reset(struct net_device *dev)
1355 +{
1356 +       int val, phy_reset_expiretime = 50;
1357 +       struct rtl8169_private *priv = dev->priv;
1358 +       void *ioaddr = priv->mmio_addr;
1359 +
1360 +       DBG_PRINT("%s: Reset RTL8169s PHY\n", dev->name);
1361 +
1362 +       val = ( RTL8169_READ_GMII_REG( ioaddr, 0 ) | 0x8000 ) & 0xffff;
1363 +       RTL8169_WRITE_GMII_REG( ioaddr, 0, val );
1364 +
1365 +       do //waiting for phy reset
1366 +       {
1367 +               if( RTL8169_READ_GMII_REG( ioaddr, 0 ) & 0x8000 ){
1368 +                       phy_reset_expiretime --;
1369 +                       udelay(100);
1370 +               }
1371 +               else{
1372 +                       break;
1373 +               }
1374 +       }while( phy_reset_expiretime >= 0 );
1375 +
1376 +       assert( phy_reset_expiretime > 0 );
1377  }
1378
1379 -static void
1380 -rtl8169_hw_start(struct net_device *dev)
1381 +
1382 +
1383 +
1384 +//======================================================================================================
1385 +static void rtl8169_hw_PHY_config (struct net_device *dev)
1386  {
1387 -       struct rtl8169_private *tp = dev->priv;
1388 -       void *ioaddr = tp->mmio_addr;
1389 +       struct rtl8169_private *priv = dev->priv;
1390 +       void *ioaddr = priv->mmio_addr;
1391 +       int val;
1392 +
1393 +       RTL_PRINT_MAC_VERSION(priv->mac_version);
1394 +       RTL_PRINT_PHY_VERSION(priv->phy_version);
1395 +
1396 +       if( (priv->mac_version > RTL_GIGA_MAC_VER_B) && ( priv->phy_version < RTL_GIGA_PHY_VER_F ) )
1397 +       {
1398 +                       DBG_PRINT("MAC version!=0 && PHY version == 0 or 1\n");
1399 +                       DBG_PRINT("Do final_reg2.cfg\n");
1400 +                       // phy config for RTL8169s mac_version C chip
1401 +                       RTL8169_WRITE_GMII_REG( ioaddr, 31, 0x0001 );   //w 31 2 0 1
1402 +                       RTL8169_WRITE_GMII_REG( ioaddr, 21, 0x1000 );   //w 21 15 0 1000
1403 +                       RTL8169_WRITE_GMII_REG( ioaddr, 24, 0x65c7 );   //w 24 15 0 65c7
1404 +                       RTL8169_WRITE_GMII_REG_BIT( ioaddr, 4, 11, 0 ); //w 4 11 11 0
1405 +                       val = RTL8169_READ_GMII_REG( ioaddr, 4 ) & 0x0fff;
1406 +                       RTL8169_WRITE_GMII_REG( ioaddr, 4, val );       //w 4 15 12 0
1407 +                       RTL8169_WRITE_GMII_REG( ioaddr, 3, 0x00a1 );    //w 3 15 0 00a1
1408 +                       RTL8169_WRITE_GMII_REG( ioaddr, 2, 0x0008 );    //w 2 15 0 0008
1409 +                       RTL8169_WRITE_GMII_REG( ioaddr, 1, 0x1020 );    //w 1 15 0 1020
1410 +                       RTL8169_WRITE_GMII_REG( ioaddr, 0, 0x1000 );    //w 0 15 0 1000
1411 +                       RTL8169_WRITE_GMII_REG_BIT( ioaddr, 4, 11, 1 ); //w 4 11 11 1
1412 +                       RTL8169_WRITE_GMII_REG_BIT( ioaddr, 4, 11, 0 ); //w 4 11 11 0
1413 +                       val = ( RTL8169_READ_GMII_REG( ioaddr, 4 ) & 0x0fff ) | 0x7000;
1414 +                       RTL8169_WRITE_GMII_REG( ioaddr, 4, val );       //w 4 15 12 7
1415 +                       RTL8169_WRITE_GMII_REG( ioaddr, 3, 0xff41 );    //w 3 15 0 ff41
1416 +                       RTL8169_WRITE_GMII_REG( ioaddr, 2, 0xde60 );    //w 2 15 0 de60
1417 +                       RTL8169_WRITE_GMII_REG( ioaddr, 1, 0x0140 );    //w 1 15 0 0140
1418 +                       RTL8169_WRITE_GMII_REG( ioaddr, 0, 0x0077 );    //w 0 15 0 0077
1419 +                       RTL8169_WRITE_GMII_REG_BIT( ioaddr, 4, 11, 1 ); //w 4 11 11 1
1420 +                       RTL8169_WRITE_GMII_REG_BIT( ioaddr, 4, 11, 0 ); //w 4 11 11 0
1421 +                       val = ( RTL8169_READ_GMII_REG( ioaddr, 4 ) & 0x0fff ) | 0xa000;
1422 +                       RTL8169_WRITE_GMII_REG( ioaddr, 4, val );       //w 4 15 12 a
1423 +                       RTL8169_WRITE_GMII_REG( ioaddr, 3, 0xdf01 );    //w 3 15 0 df01
1424 +                       RTL8169_WRITE_GMII_REG( ioaddr, 2, 0xdf20 );    //w 2 15 0 df20
1425 +                       RTL8169_WRITE_GMII_REG( ioaddr, 1, 0xff95 );    //w 1 15 0 ff95
1426 +                       RTL8169_WRITE_GMII_REG( ioaddr, 0, 0xfa00 );    //w 0 15 0 fa00
1427 +                       RTL8169_WRITE_GMII_REG_BIT( ioaddr, 4, 11, 1 ); //w 4 11 11 1
1428 +                       RTL8169_WRITE_GMII_REG_BIT( ioaddr, 4, 11, 0 ); //w 4 11 11 0
1429 +                       val = ( RTL8169_READ_GMII_REG( ioaddr, 4 ) & 0x0fff ) | 0xb000;
1430 +                       RTL8169_WRITE_GMII_REG( ioaddr, 4, val );       //w 4 15 12 b
1431 +                       RTL8169_WRITE_GMII_REG( ioaddr, 3, 0xff41 );    //w 3 15 0 ff41
1432 +                       RTL8169_WRITE_GMII_REG( ioaddr, 2, 0xde20 );    //w 2 15 0 de20
1433 +                       RTL8169_WRITE_GMII_REG( ioaddr, 1, 0x0140 );    //w 1 15 0 0140
1434 +                       RTL8169_WRITE_GMII_REG( ioaddr, 0, 0x00bb );    //w 0 15 0 00bb
1435 +                       RTL8169_WRITE_GMII_REG_BIT( ioaddr, 4, 11, 1 ); //w 4 11 11 1
1436 +                       RTL8169_WRITE_GMII_REG_BIT( ioaddr, 4, 11, 0 ); //w 4 11 11 0
1437 +                       val = ( RTL8169_READ_GMII_REG( ioaddr, 4 ) & 0x0fff ) | 0xf000;
1438 +                       RTL8169_WRITE_GMII_REG( ioaddr, 4, val );       //w 4 15 12 f
1439 +                       RTL8169_WRITE_GMII_REG( ioaddr, 3, 0xdf01 );    //w 3 15 0 df01
1440 +                       RTL8169_WRITE_GMII_REG( ioaddr, 2, 0xdf20 );    //w 2 15 0 df20
1441 +                       RTL8169_WRITE_GMII_REG( ioaddr, 1, 0xff95 );    //w 1 15 0 ff95
1442 +                       RTL8169_WRITE_GMII_REG( ioaddr, 0, 0xbf00 );    //w 0 15 0 bf00
1443 +                       RTL8169_WRITE_GMII_REG_BIT( ioaddr, 4, 11, 1 ); //w 4 11 11 1
1444 +                       RTL8169_WRITE_GMII_REG_BIT( ioaddr, 4, 11, 0 ); //w 4 11 11 0
1445 +                       RTL8169_WRITE_GMII_REG( ioaddr, 31, 0x0000 );   //w 31 2 0 0
1446 +       }
1447 +}
1448 +
1449 +
1450 +
1451 +
1452 +
1453 +
1454 +
1455 +
1456 +
1457 +
1458 +//======================================================================================================
1459 +static void rtl8169_hw_start (struct net_device *dev)
1460 +{
1461 +       struct rtl8169_private *priv = dev->priv;
1462 +       void *ioaddr = priv->mmio_addr;
1463         u32 i;
1464
1465 +
1466         /* Soft reset the chip. */
1467 -       RTL_W8(ChipCmd, CmdReset);
1468 +       RTL_W8 ( ChipCmd, CmdReset);
1469
1470         /* Check that the chip has finished the reset. */
1471 -       for (i = 1000; i > 0; i--) {
1472 -               if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1473 -                       break;
1474 -               else
1475 -                       udelay(10);
1476 +       for (i = 1000; i > 0; i--){
1477 +               if ((RTL_R8( ChipCmd ) & CmdReset) == 0) break;
1478 +               else udelay (10);
1479         }
1480
1481 -       RTL_W8(Cfg9346, Cfg9346_Unlock);
1482 -       RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1483 -       RTL_W8(EarlyTxThres, EarlyTxThld);
1484 +       RTL_W8 ( Cfg9346, Cfg9346_Unlock);
1485 +       RTL_W8 ( ChipCmd, CmdTxEnb | CmdRxEnb);
1486 +       RTL_W8 ( ETThReg, ETTh);
1487
1488         // For gigabit rtl8169
1489 -       RTL_W16(RxMaxSize, RxPacketMaxSize);
1490 +       RTL_W16 ( RxMaxSize, RxPacketMaxSize );
1491
1492         // Set Rx Config register
1493 -       i = rtl8169_rx_config | (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].
1494 -                                RxConfigMask);
1495 -       RTL_W32(RxConfig, i);
1496 +       i = rtl8169_rx_config | ( RTL_R32( RxConfig ) & rtl_chip_info[priv->chipset].RxConfigMask);
1497 +       RTL_W32 ( RxConfig, i);
1498
1499         /* Set DMA burst size and Interframe Gap Time */
1500 -       RTL_W32(TxConfig,
1501 -               (TX_DMA_BURST << TxDMAShift) | (InterFrameGap <<
1502 -                                               TxInterFrameGapShift));
1503 +       RTL_W32 ( TxConfig, (TX_DMA_BURST << TxDMAShift) | (InterFrameGap << TxInterFrameGapShift) );
1504 +
1505 +       RTL_W16( CPlusCmd, RTL_R16(CPlusCmd) );
1506 +
1507 +       //2003-07-18
1508 +       if( priv->mac_version == RTL_GIGA_MAC_VER_D ){
1509 +               DBG_PRINT("Set MAC Reg C+CR Offset 0xE0: bit-3 and bit-14 MUST be 1\n");
1510 +               RTL_W16( CPlusCmd, (RTL_R16(CPlusCmd)|(1<<14)|(1<<3)) );
1511 +       }
1512
1513 -       tp->cur_rx = 0;
1514 +       priv->cur_rx = 0;
1515
1516 -       RTL_W32(TxDescStartAddr, virt_to_bus(tp->TxDescArray));
1517 -       RTL_W32(RxDescStartAddr, virt_to_bus(tp->RxDescArray));
1518 -       RTL_W8(Cfg9346, Cfg9346_Lock);
1519 -       udelay(10);
1520 +       RTL_W32 ( TxDescStartAddr, virt_to_bus(priv->TxDescArray));
1521 +       RTL_W32 ( RxDescStartAddr, virt_to_bus(priv->RxDescArray));
1522 +       RTL_W8 ( Cfg9346, Cfg9346_Lock );
1523 +       udelay (10);
1524
1525 -       RTL_W32(RxMissed, 0);
1526 +       RTL_W32 ( RxMissed, 0 );
1527
1528 -       rtl8169_set_rx_mode(dev);
1529 +       rtl8169_set_rx_mode (dev);
1530
1531         /* no early-rx interrupts */
1532 -       RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1533 +       RTL_W16 ( MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1534
1535         /* Enable all known interrupts by setting the interrupt mask. */
1536 -       RTL_W16(IntrMask, rtl8169_intr_mask);
1537 +       RTL_W16 ( IntrMask, rtl8169_intr_mask);
1538 +
1539 +       netif_start_queue (dev);
1540 +
1541 +}//end of rtl8169_hw_start (struct net_device *dev)
1542 +
1543 +
1544 +
1545 +
1546
1547 -       netif_start_queue(dev);
1548
1549 -}
1550
1551 -static void
1552 -rtl8169_init_ring(struct net_device *dev)
1553 +//======================================================================================================
1554 +static void rtl8169_init_ring (struct net_device *dev)
1555  {
1556 -       struct rtl8169_private *tp = dev->priv;
1557 +       struct rtl8169_private *priv = dev->priv;
1558         int i;
1559
1560 -       tp->cur_rx = 0;
1561 -       tp->cur_tx = 0;
1562 -       tp->dirty_tx = 0;
1563 -       memset(tp->TxDescArray, 0x0, NUM_TX_DESC * sizeof (struct TxDesc));
1564 -       memset(tp->RxDescArray, 0x0, NUM_RX_DESC * sizeof (struct RxDesc));
1565 -
1566 -       for (i = 0; i < NUM_TX_DESC; i++) {
1567 -               tp->Tx_skbuff[i] = NULL;
1568 -       }
1569 -       for (i = 0; i < NUM_RX_DESC; i++) {
1570 -               if (i == (NUM_RX_DESC - 1))
1571 -                       tp->RxDescArray[i].status =
1572 -                           (OWNbit | EORbit) + RX_BUF_SIZE;
1573 +       priv->cur_rx = 0;
1574 +       priv->cur_tx = 0;
1575 +       priv->dirty_tx = 0;
1576 +       memset(priv->TxDescArray, 0x0, NUM_TX_DESC*sizeof(struct TxDesc));
1577 +       memset(priv->RxDescArray, 0x0, NUM_RX_DESC*sizeof(struct RxDesc));
1578 +
1579 +       for (i=0 ; i<NUM_TX_DESC ; i++){
1580 +               priv->Tx_skbuff[i]=NULL;
1581 +       }
1582 +       for (i=0; i <NUM_RX_DESC; i++) {
1583 +               if(i==(NUM_RX_DESC-1))
1584 +                       priv->RxDescArray[i].status = (OWNbit | EORbit) + RX_BUF_SIZE;
1585                 else
1586 -                       tp->RxDescArray[i].status = OWNbit + RX_BUF_SIZE;
1587 +                       priv->RxDescArray[i].status = OWNbit + RX_BUF_SIZE;
1588 +
1589 +               {//-----------------------------------------------------------------------
1590 +                       struct sk_buff *skb = priv->Rx_skbuff[i];
1591 +
1592 +                       if( skb != NULL ){
1593 +                               priv->RxDescArray[i].buf_addr = virt_to_bus( skb->data );
1594 +                       }
1595 +                       else{
1596 +                               DBG_PRINT("%s: %s() Rx_skbuff == NULL\n", dev->name, __FUNCTION__);
1597 +                               priv->drvinit_fail = 1;
1598 +                       }
1599 +               }//-----------------------------------------------------------------------
1600
1601 -               tp->RxBufferRing[i] = &(tp->RxBufferRings[i * RX_BUF_SIZE]);
1602 -               tp->RxDescArray[i].buf_addr = virt_to_bus(tp->RxBufferRing[i]);
1603         }
1604  }
1605
1606 -static void
1607 -rtl8169_tx_clear(struct rtl8169_private *tp)
1608 +
1609 +
1610 +
1611 +
1612 +
1613 +
1614 +//======================================================================================================
1615 +static void rtl8169_tx_clear (struct rtl8169_private *priv)
1616  {
1617         int i;
1618
1619 -       tp->cur_tx = 0;
1620 -       for (i = 0; i < NUM_TX_DESC; i++) {
1621 -               if (tp->Tx_skbuff[i] != NULL) {
1622 -                       dev_kfree_skb(tp->Tx_skbuff[i]);
1623 -                       tp->Tx_skbuff[i] = NULL;
1624 -                       tp->stats.tx_dropped++;
1625 +       priv->cur_tx = 0;
1626 +       for ( i = 0 ; i < NUM_TX_DESC ; i++ ){
1627 +               if ( priv->Tx_skbuff[i] != NULL ) {
1628 +                       dev_kfree_skb ( priv->Tx_skbuff[i] );
1629 +                       priv->Tx_skbuff[i] = NULL;
1630 +                       priv->stats.tx_dropped++;
1631                 }
1632         }
1633  }
1634
1635 -static void
1636 -rtl8169_tx_timeout(struct net_device *dev)
1637 +
1638 +
1639 +
1640 +
1641 +
1642 +
1643 +//======================================================================================================
1644 +static void rtl8169_tx_timeout (struct net_device *dev)
1645  {
1646 -       struct rtl8169_private *tp = dev->priv;
1647 -       void *ioaddr = tp->mmio_addr;
1648 +       struct rtl8169_private *priv = dev->priv;
1649 +       void *ioaddr = priv->mmio_addr;
1650         u8 tmp8;
1651
1652         /* disable Tx, if not already */
1653 -       tmp8 = RTL_R8(ChipCmd);
1654 -       if (tmp8 & CmdTxEnb)
1655 -               RTL_W8(ChipCmd, tmp8 & ~CmdTxEnb);
1656 +       tmp8 = RTL_R8( ChipCmd );
1657 +       if (tmp8 & CmdTxEnb){
1658 +               RTL_W8 ( ChipCmd, tmp8 & ~CmdTxEnb);
1659 +       }
1660
1661         /* Disable interrupts by clearing the interrupt mask. */
1662 -       RTL_W16(IntrMask, 0x0000);
1663 +       RTL_W16 ( IntrMask, 0x0000);
1664
1665         /* Stop a shared interrupt from scavenging while we are. */
1666 -       spin_lock_irq(&tp->lock);
1667 -       rtl8169_tx_clear(tp);
1668 -       spin_unlock_irq(&tp->lock);
1669 +       spin_lock_irq (&priv->lock);
1670 +       rtl8169_tx_clear (priv);
1671 +       spin_unlock_irq (&priv->lock);
1672
1673         /* ...and finally, reset everything */
1674 -       rtl8169_hw_start(dev);
1675 +       rtl8169_hw_start (dev);
1676
1677 -       netif_wake_queue(dev);
1678 +       netif_wake_queue (dev);
1679  }
1680
1681 -static int
1682 -rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
1683 -{
1684 -       struct rtl8169_private *tp = dev->priv;
1685 -       void *ioaddr = tp->mmio_addr;
1686 -       int entry = tp->cur_tx % NUM_TX_DESC;
1687
1688 -       if (skb->len < ETH_ZLEN) {
1689 -               skb = skb_padto(skb, ETH_ZLEN);
1690 -               if (skb == NULL)
1691 -                       return 0;
1692 -       }
1693 -
1694 -       spin_lock_irq(&tp->lock);
1695
1696 -       if ((tp->TxDescArray[entry].status & OWNbit) == 0) {
1697 -               tp->Tx_skbuff[entry] = skb;
1698 -               tp->TxDescArray[entry].buf_addr = virt_to_bus(skb->data);
1699 -               if (entry != (NUM_TX_DESC - 1))
1700 -                       tp->TxDescArray[entry].status =
1701 -                           (OWNbit | FSbit | LSbit) | ((skb->len > ETH_ZLEN) ?
1702 -                                                       skb->len : ETH_ZLEN);
1703 -               else
1704 -                       tp->TxDescArray[entry].status =
1705 -                           (OWNbit | EORbit | FSbit | LSbit) |
1706 -                           ((skb->len > ETH_ZLEN) ? skb->len : ETH_ZLEN);
1707
1708 -               RTL_W8(TxPoll, 0x40);   //set polling bit
1709
1710 -               dev->trans_start = jiffies;
1711
1712 -               tp->cur_tx++;
1713 -       }
1714
1715 -       spin_unlock_irq(&tp->lock);
1716 +//======================================================================================================
1717 +static int rtl8169_start_xmit (struct sk_buff *skb, struct net_device *dev)
1718 +{
1719 +       struct rtl8169_private *priv = dev->priv;
1720 +       void *ioaddr = priv->mmio_addr;
1721 +       int entry = priv->cur_tx % NUM_TX_DESC;
1722 +
1723 +       spin_lock_irq (&priv->lock);
1724 +
1725 +       if( (priv->TxDescArray[entry].status & OWNbit)==0 ){
1726 +               priv->Tx_skbuff[entry] = skb;
1727 +               priv->TxDescArray[entry].buf_addr = virt_to_bus(skb->data);
1728 +               if( entry != (NUM_TX_DESC-1) )
1729 +                       priv->TxDescArray[entry].status = (OWNbit | FSbit | LSbit) | ( (skb->len > ETH_ZLEN) ? skb->len : ETH_ZLEN);
1730 +               else
1731 +                       priv->TxDescArray[entry].status = (OWNbit | EORbit | FSbit | LSbit) | ( (skb->len > ETH_ZLEN) ? skb->len : ETH_ZLEN);
1732 +
1733 +               RTL_W8 ( TxPoll, 0x40);         //set polling bit
1734
1735 -       if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx) {
1736 -               netif_stop_queue(dev);
1737 +               dev->trans_start = jiffies;
1738 +
1739 +               priv->stats.tx_bytes += ( (skb->len > ETH_ZLEN) ? skb->len : ETH_ZLEN);
1740 +               priv->cur_tx++;
1741 +       }//end of if( (priv->TxDescArray[entry].status & 0x80000000)==0 )
1742 +
1743 +       spin_unlock_irq (&priv->lock);
1744 +
1745 +       if ( (priv->cur_tx - NUM_TX_DESC) == priv->dirty_tx ){
1746 +               netif_stop_queue (dev);
1747 +       }
1748 +       else{
1749 +               if (netif_queue_stopped (dev)){
1750 +                       netif_wake_queue (dev);
1751 +               }
1752         }
1753
1754         return 0;
1755  }
1756
1757 -static void
1758 -rtl8169_tx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
1759 -                    void *ioaddr)
1760 -{
1761 -       unsigned long dirty_tx, tx_left = 0;
1762 -       int entry = tp->cur_tx % NUM_TX_DESC;
1763 -
1764 -       assert(dev != NULL);
1765 -       assert(tp != NULL);
1766 -       assert(ioaddr != NULL);
1767
1768 -       dirty_tx = tp->dirty_tx;
1769 -       tx_left = tp->cur_tx - dirty_tx;
1770 +
1771 +
1772 +
1773 +
1774 +
1775 +//======================================================================================================
1776 +static void rtl8169_tx_interrupt (struct net_device *dev, struct rtl8169_private *priv, void *ioaddr)
1777 +{
1778 +       unsigned long dirty_tx, tx_left=0;
1779 +       int entry = priv->cur_tx % NUM_TX_DESC;
1780 +
1781 +       assert (dev != NULL);
1782 +       assert (priv != NULL);
1783 +       assert (ioaddr != NULL);
1784 +
1785 +
1786 +       dirty_tx = priv->dirty_tx;
1787 +       tx_left = priv->cur_tx - dirty_tx;
1788
1789         while (tx_left > 0) {
1790 -               if ((tp->TxDescArray[entry].status & OWNbit) == 0) {
1791 -                       dev_kfree_skb_irq(tp->
1792 -                                         Tx_skbuff[dirty_tx % NUM_TX_DESC]);
1793 -                       tp->Tx_skbuff[dirty_tx % NUM_TX_DESC] = NULL;
1794 -                       tp->stats.tx_packets++;
1795 +               if( (priv->TxDescArray[entry].status & OWNbit) == 0 ){
1796 +                       dev_kfree_skb_irq( priv->Tx_skbuff[dirty_tx % NUM_TX_DESC] );
1797 +                       priv->Tx_skbuff[dirty_tx % NUM_TX_DESC] = NULL;
1798 +                       priv->stats.tx_packets++;
1799                         dirty_tx++;
1800                         tx_left--;
1801                         entry++;
1802                 }
1803         }
1804
1805 -       if (tp->dirty_tx != dirty_tx) {
1806 -               tp->dirty_tx = dirty_tx;
1807 -               if (netif_queue_stopped(dev))
1808 -                       netif_wake_queue(dev);
1809 +       if (priv->dirty_tx != dirty_tx) {
1810 +               priv->dirty_tx = dirty_tx;
1811 +               if (netif_queue_stopped (dev))
1812 +                       netif_wake_queue (dev);
1813         }
1814  }
1815
1816 -static void
1817 -rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
1818 -                    void *ioaddr)
1819 +
1820 +
1821 +
1822 +
1823 +
1824 +//======================================================================================================
1825 +static void rtl8169_rx_interrupt (struct net_device *dev, struct rtl8169_private *priv, void *ioaddr)
1826  {
1827         int cur_rx;
1828 -       struct sk_buff *skb;
1829 -       int pkt_size = 0;
1830 +//     struct sk_buff *skb;
1831 +       int pkt_size = 0 ;
1832 +    int rxdesc_cnt = 0;
1833 +       int ret;
1834 +       struct sk_buff *n_skb = NULL;
1835 +       struct sk_buff *rx_skb = priv->Rx_skbuff[cur_rx];
1836 +       struct sk_buff *cur_skb;
1837 +
1838 +       assert (dev != NULL);
1839 +       assert (priv != NULL);
1840 +       assert (ioaddr != NULL);
1841 +
1842
1843 -       assert(dev != NULL);
1844 -       assert(tp != NULL);
1845 -       assert(ioaddr != NULL);
1846 +       cur_rx = priv->cur_rx;
1847
1848 -       cur_rx = tp->cur_rx;
1849 +       while ( ((priv->RxDescArray[cur_rx].status & OWNbit)== 0) && (rxdesc_cnt < 20) ){
1850
1851 -       while ((tp->RxDescArray[cur_rx].status & OWNbit) == 0) {
1852 +           rxdesc_cnt++;
1853
1854 -               if (tp->RxDescArray[cur_rx].status & RxRES) {
1855 +               if( priv->RxDescArray[cur_rx].status & RxRES ){
1856                         printk(KERN_INFO "%s: Rx ERROR!!!\n", dev->name);
1857 -                       tp->stats.rx_errors++;
1858 -                       if (tp->RxDescArray[cur_rx].status & (RxRWT | RxRUNT))
1859 -                               tp->stats.rx_length_errors++;
1860 -                       if (tp->RxDescArray[cur_rx].status & RxCRC)
1861 -                               tp->stats.rx_crc_errors++;
1862 -               } else {
1863 -                       pkt_size =
1864 -                           (int) (tp->RxDescArray[cur_rx].
1865 -                                  status & 0x00001FFF) - 4;
1866 -                       skb = dev_alloc_skb(pkt_size + 2);
1867 -                       if (skb != NULL) {
1868 -                               skb->dev = dev;
1869 -                               skb_reserve(skb, 2);    // 16 byte align the IP fields. //
1870 -                               eth_copy_and_sum(skb, tp->RxBufferRing[cur_rx],
1871 -                                                pkt_size, 0);
1872 -                               skb_put(skb, pkt_size);
1873 -                               skb->protocol = eth_type_trans(skb, dev);
1874 -                               netif_rx(skb);
1875 -
1876 -                               if (cur_rx == (NUM_RX_DESC - 1))
1877 -                                       tp->RxDescArray[cur_rx].status =
1878 -                                           (OWNbit | EORbit) + RX_BUF_SIZE;
1879 -                               else
1880 -                                       tp->RxDescArray[cur_rx].status =
1881 -                                           OWNbit + RX_BUF_SIZE;
1882 -
1883 -                               tp->RxDescArray[cur_rx].buf_addr =
1884 -                                   virt_to_bus(tp->RxBufferRing[cur_rx]);
1885 -                               dev->last_rx = jiffies;
1886 -                               tp->stats.rx_bytes += pkt_size;
1887 -                               tp->stats.rx_packets++;
1888 -                       } else {
1889 -                               printk(KERN_WARNING
1890 -                                      "%s: Memory squeeze, deferring packet.\n",
1891 -                                      dev->name);
1892 -                               /* We should check that some rx space is free.
1893 -                                  If not, free one and mark stats->rx_dropped++. */
1894 -                               tp->stats.rx_dropped++;
1895 -                       }
1896 -               }
1897 +                       priv->stats.rx_errors++;
1898 +                       if (priv->RxDescArray[cur_rx].status & (RxRWT|RxRUNT) )
1899 +                               priv->stats.rx_length_errors++;
1900 +                       if (priv->RxDescArray[cur_rx].status & RxCRC)
1901 +                               priv->stats.rx_crc_errors++;
1902 +           }
1903 +           else{
1904 +                       pkt_size=(int)(priv->RxDescArray[cur_rx].status & 0x00001FFF)-4;
1905 +                       {// -----------------------------------------------------
1906 +                               rx_skb = priv->Rx_skbuff[cur_rx];
1907 +
1908 +                               //n_skb = NULL;
1909 +                               n_skb = RTL8169_ALLOC_RXSKB(MAX_RX_SKBDATA_SIZE);
1910 +                               if( n_skb != NULL ) {
1911 +                                       skb_reserve (n_skb, 2); // 16 byte align the IP fields. //
1912 +
1913 +                                       // Indicate rx_skb
1914 +                                       if( rx_skb != NULL ){
1915 +                                               rx_skb->dev = dev;
1916 +                                               skb_put ( rx_skb, pkt_size );
1917 +                                               rx_skb->protocol = eth_type_trans ( rx_skb, dev );
1918 +                                               ret = RTL8169_NETIF_RX (rx_skb);
1919 +
1920 +                                               dev->last_rx = jiffies;
1921 +                                               priv->stats.rx_bytes += pkt_size;
1922 +                                               priv->stats.rx_packets++;
1923 +#if 0
1924 +                                               switch(ret)
1925 +                                               {
1926 +                                               case NET_RX_SUCCESS:    printk("%s: NETIF_RX_SUCCESS\n", dev->name);    break;
1927 +                                               case NET_RX_CN_LOW:     printk("%s: NETIF_RX_CN_LOW\n", dev->name);     break;
1928 +                                               case NET_RX_CN_MOD:     printk("%s: NETIF_CN_MOD\n", dev->name);        break;
1929 +                                               case NET_RX_CN_HIGH:    printk("%s: NETIF_CN_HIGH\n", dev->name);       break;
1930 +                                               case NET_RX_DROP:       printk("%s: NETIF_RX_DROP\n", dev->name);       break;
1931 +                                               default:                printk("%s: netif_rx():Unknown\n", dev->name);  break;
1932 +                                               }
1933 +#endif
1934 +                                       }//end if( rx_skb != NULL )
1935 +
1936 +                                       priv->Rx_skbuff[cur_rx] = n_skb;
1937 +                               }
1938 +                               else{
1939 +                                       priv->Rx_skbuff[cur_rx] = rx_skb;
1940 +                               }
1941 +
1942 +                               // Update rx descriptor
1943 +                               if( cur_rx == (NUM_RX_DESC-1) ){
1944 +                                       priv->RxDescArray[cur_rx].status  = (OWNbit | EORbit) + RX_BUF_SIZE;
1945 +                               }
1946 +                               else{
1947 +                                       priv->RxDescArray[cur_rx].status  = OWNbit + RX_BUF_SIZE;
1948 +                               }
1949 +
1950 +                               cur_skb = priv->Rx_skbuff[cur_rx];
1951 +                               if( cur_skb != NULL ){
1952 +                                       priv->RxDescArray[cur_rx].buf_addr = virt_to_bus( cur_skb->data );
1953 +                               }
1954 +                               else{
1955 +                                       DBG_PRINT("%s: %s() cur_skb == NULL\n", dev->name, __FUNCTION__);
1956 +                               }
1957 +
1958 +                       }//------------------------------------------------------------
1959
1960 -               cur_rx = (cur_rx + 1) % NUM_RX_DESC;
1961 +           }// end of if( priv->RxDescArray[cur_rx].status & RxRES )
1962
1963 +           cur_rx = (cur_rx +1) % NUM_RX_DESC;
1964 +
1965 +       }// end of while ( (priv->RxDescArray[cur_rx].status & 0x80000000)== 0)
1966 +
1967 +
1968 +       if( rxdesc_cnt == 20 ){
1969 +               printk("rxdesc_cnt == 20 ----------\n");
1970         }
1971
1972 -       tp->cur_rx = cur_rx;
1973 +
1974 +       priv->cur_rx = cur_rx;
1975  }
1976
1977 +
1978 +
1979 +
1980 +
1981 +
1982 +
1983 +
1984 +//======================================================================================================
1985  /* The interrupt handler does all of the Rx thread work and cleans up after the Tx thread. */
1986 -static irqreturn_t
1987 -rtl8169_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1988 +static irqreturn_t rtl8169_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
1989  {
1990         struct net_device *dev = (struct net_device *) dev_instance;
1991 -       struct rtl8169_private *tp = dev->priv;
1992 +       struct rtl8169_private *priv = dev->priv;
1993         int boguscnt = max_interrupt_work;
1994 -       void *ioaddr = tp->mmio_addr;
1995 +       void *ioaddr = priv->mmio_addr;
1996         int status = 0;
1997         int handled = 0;
1998
1999 @@ -988,158 +1446,225 @@
2000
2001                 handled = 1;
2002  /*
2003 -               if (status & RxUnderrun)
2004 +               if (status & LinkChg)
2005                         link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2006  */
2007 -               RTL_W16(IntrStatus,
2008 -                       (status & RxFIFOOver) ? (status | RxOverflow) : status);
2009
2010 -               if ((status &
2011 -                    (SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver
2012 -                     | TxErr | TxOK | RxErr | RxOK)) == 0)
2013 +               RTL_W16( IntrStatus, status );
2014 +
2015 +
2016 +               if ( (status & rtl8169_intr_mask ) == 0 )
2017                         break;
2018
2019 -               // Rx interrupt
2020 -               if (status & (RxOK | RxUnderrun | RxOverflow | RxFIFOOver)) {
2021 -                       rtl8169_rx_interrupt(dev, tp, ioaddr);
2022 -               }
2023 +
2024 +               // Rx interrupt
2025 +//             if (status & (RxOK | LinkChg | RxOverflow | RxFIFOOver)){
2026 +                       rtl8169_rx_interrupt (dev, priv, ioaddr);
2027 +//             }
2028 +
2029                 // Tx interrupt
2030 -               if (status & (TxOK | TxErr)) {
2031 -                       spin_lock(&tp->lock);
2032 -                       rtl8169_tx_interrupt(dev, tp, ioaddr);
2033 -                       spin_unlock(&tp->lock);
2034 -               }
2035 +//             if (status & (TxOK | TxErr)) {
2036 +                       spin_lock (&priv->lock);
2037 +                       rtl8169_tx_interrupt (dev, priv, ioaddr);
2038 +                       spin_unlock (&priv->lock);
2039 +//             }
2040
2041                 boguscnt--;
2042         } while (boguscnt > 0);
2043
2044         if (boguscnt <= 0) {
2045 -               printk(KERN_WARNING "%s: Too much work at interrupt!\n",
2046 -                      dev->name);
2047 +               printk (KERN_WARNING "%s: Too much work at interrupt!\n", dev->name);
2048                 /* Clear all interrupt sources. */
2049 -               RTL_W16(IntrStatus, 0xffff);
2050 +               RTL_W16( IntrStatus, 0xffff);
2051         }
2052         return IRQ_RETVAL(handled);
2053  }
2054
2055 -static int
2056 -rtl8169_close(struct net_device *dev)
2057 +
2058 +
2059 +
2060 +
2061 +
2062 +
2063 +//======================================================================================================
2064 +static int rtl8169_close (struct net_device *dev)
2065  {
2066 -       struct rtl8169_private *tp = dev->priv;
2067 -       void *ioaddr = tp->mmio_addr;
2068 +       struct rtl8169_private *priv = dev->priv;
2069 +       void *ioaddr = priv->mmio_addr;
2070         int i;
2071
2072 -       netif_stop_queue(dev);
2073 +       //////////////////////////////////////////////////////////////////////////////
2074 +       // ------------------------------------------------------
2075 +       if( (priv->mac_version > RTL_GIGA_MAC_VER_B) && (priv->phy_version < RTL_GIGA_PHY_VER_G) ){
2076 +               DBG_PRINT("FIX PCS -> rtl8169_delete_timer\n");
2077 +               rtl8169_delete_timer( &(priv->phy_timer_t) ); //in close()
2078 +               priv->phy_link_down_cnt = 0;
2079 +       }
2080
2081 -       spin_lock_irq(&tp->lock);
2082 +       netif_stop_queue (dev);
2083 +
2084 +       spin_lock_irq (&priv->lock);
2085
2086         /* Stop the chip's Tx and Rx DMA processes. */
2087 -       RTL_W8(ChipCmd, 0x00);
2088 +       RTL_W8 ( ChipCmd, 0x00);
2089
2090         /* Disable interrupts by clearing the interrupt mask. */
2091 -       RTL_W16(IntrMask, 0x0000);
2092 +       RTL_W16 ( IntrMask, 0x0000);
2093
2094         /* Update the error counts. */
2095 -       tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2096 -       RTL_W32(RxMissed, 0);
2097 +       priv->stats.rx_missed_errors += RTL_R32(RxMissed);
2098 +       RTL_W32( RxMissed, 0);
2099
2100 -       spin_unlock_irq(&tp->lock);
2101 +       spin_unlock_irq (&priv->lock);
2102
2103 -       synchronize_irq(dev->irq);
2104 -       free_irq(dev->irq, dev);
2105 +       synchronize_irq ();
2106 +       free_irq (dev->irq, dev);
2107
2108 -       rtl8169_tx_clear(tp);
2109 -       kfree(tp->TxDescArrays);
2110 -       kfree(tp->RxDescArrays);
2111 -       tp->TxDescArrays = NULL;
2112 -       tp->RxDescArrays = NULL;
2113 -       tp->TxDescArray = NULL;
2114 -       tp->RxDescArray = NULL;
2115 -       kfree(tp->RxBufferRings);
2116 -       for (i = 0; i < NUM_RX_DESC; i++) {
2117 -               tp->RxBufferRing[i] = NULL;
2118 -       }
2119 +       rtl8169_tx_clear (priv);
2120 +       kfree(priv->TxDescArrays);
2121 +       kfree(priv->RxDescArrays);
2122 +       priv->TxDescArrays = NULL;
2123 +       priv->RxDescArrays = NULL;
2124 +       priv->TxDescArray = NULL;
2125 +       priv->RxDescArray = NULL;
2126 +
2127 +       {//-----------------------------------------------------------------------------
2128 +               for(i=0;i<NUM_RX_DESC;i++){
2129 +                       if( priv->Rx_skbuff[i] != NULL ) {
2130 +                               RTL8169_FREE_RXSKB ( priv->Rx_skbuff[i] );
2131 +                       }
2132 +               }
2133 +       }//-----------------------------------------------------------------------------
2134 +
2135 +       DBG_PRINT("%s: %s() alloc_rxskb_cnt = %d\n", dev->name, __FUNCTION__, alloc_rxskb_cnt );
2136
2137         return 0;
2138  }
2139
2140 -static void
2141 -rtl8169_set_rx_mode(struct net_device *dev)
2142 +
2143 +
2144 +
2145 +
2146 +
2147 +
2148 +//======================================================================================================
2149 +static unsigned const ethernet_polynomial = 0x04c11db7U;
2150 +static inline u32 ether_crc (int length, unsigned char *data)
2151 +{
2152 +       int crc = -1;
2153 +
2154 +
2155 +       while (--length >= 0) {
2156 +               unsigned char current_octet = *data++;
2157 +               int bit;
2158 +               for (bit = 0; bit < 8; bit++, current_octet >>= 1)
2159 +                       crc = (crc << 1) ^ ((crc < 0) ^ (current_octet & 1) ? ethernet_polynomial : 0);
2160 +       }
2161 +
2162 +       return crc;
2163 +}
2164 +
2165 +
2166 +
2167 +
2168 +
2169 +
2170 +
2171 +
2172 +//======================================================================================================
2173 +static void rtl8169_set_rx_mode (struct net_device *dev)
2174  {
2175 -       struct rtl8169_private *tp = dev->priv;
2176 -       void *ioaddr = tp->mmio_addr;
2177 +       struct rtl8169_private *priv = dev->priv;
2178 +       void *ioaddr = priv->mmio_addr;
2179         unsigned long flags;
2180         u32 mc_filter[2];       /* Multicast hash filter */
2181         int i, rx_mode;
2182 -       u32 tmp = 0;
2183 +       u32 tmp=0;
2184 +
2185
2186         if (dev->flags & IFF_PROMISC) {
2187                 /* Unconditionally log net taps. */
2188 -               printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2189 -                      dev->name);
2190 -               rx_mode =
2191 -                   AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2192 -                   AcceptAllPhys;
2193 +               printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
2194 +               rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys | AcceptAllPhys;
2195                 mc_filter[1] = mc_filter[0] = 0xffffffff;
2196 -       } else if ((dev->mc_count > multicast_filter_limit)
2197 -                  || (dev->flags & IFF_ALLMULTI)) {
2198 +       } else if ((dev->mc_count > multicast_filter_limit) || (dev->flags & IFF_ALLMULTI)) {
2199                 /* Too many to filter perfectly -- accept all multicasts. */
2200                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2201                 mc_filter[1] = mc_filter[0] = 0xffffffff;
2202         } else {
2203                 struct dev_mc_list *mclist;
2204 -               rx_mode = AcceptBroadcast | AcceptMyPhys;
2205 +               rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2206                 mc_filter[1] = mc_filter[0] = 0;
2207 -               for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2208 -                    i++, mclist = mclist->next) {
2209 -                       int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2210 -                       mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2211 -                       rx_mode |= AcceptMulticast;
2212 -               }
2213 +               for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; i++, mclist = mclist->next)
2214 +                       set_bit (ether_crc (ETH_ALEN, mclist->dmi_addr) >> 26, mc_filter);
2215         }
2216
2217 -       spin_lock_irqsave(&tp->lock, flags);
2218 +       spin_lock_irqsave (&priv->lock, flags);
2219 +
2220 +       tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) & rtl_chip_info[priv->chipset].RxConfigMask);
2221 +
2222 +       RTL_W32 ( RxConfig, tmp);
2223 +       RTL_W32 ( MAR0 + 0, mc_filter[0]);
2224 +       RTL_W32 ( MAR0 + 4, mc_filter[1]);
2225 +
2226 +       spin_unlock_irqrestore (&priv->lock, flags);
2227 +
2228 +}//end of rtl8169_set_rx_mode (struct net_device *dev)
2229
2230 -       tmp =
2231 -           rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
2232 -                                          rtl_chip_info[tp->chipset].
2233 -                                          RxConfigMask);
2234
2235 -       RTL_W32(RxConfig, tmp);
2236 -       RTL_W32(MAR0 + 0, mc_filter[0]);
2237 -       RTL_W32(MAR0 + 4, mc_filter[1]);
2238
2239 -       spin_unlock_irqrestore(&tp->lock, flags);
2240 -}
2241
2242 -struct net_device_stats *
2243 -rtl8169_get_stats(struct net_device *dev)
2244 +
2245 +
2246 +
2247 +//================================================================================
2248 +struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
2249 +
2250  {
2251 -       struct rtl8169_private *tp = dev->priv;
2252 +       struct rtl8169_private *priv = dev->priv;
2253
2254 -       return &tp->stats;
2255 +    return &priv->stats;
2256  }
2257
2258 +
2259 +
2260 +
2261 +
2262 +
2263 +
2264 +
2265 +//================================================================================
2266  static struct pci_driver rtl8169_pci_driver = {
2267 -       .name           = MODULENAME,
2268 -       .id_table       = rtl8169_pci_tbl,
2269 -       .probe          = rtl8169_init_one,
2270 -       .remove         = __devexit_p(rtl8169_remove_one),
2271 -       .suspend        = NULL,
2272 -       .resume         = NULL,
2273 +       name:           MODULENAME,
2274 +       id_table:       rtl8169_pci_tbl,
2275 +       probe:          rtl8169_init_one,
2276 +       remove:         rtl8169_remove_one,
2277 +       suspend:        NULL,
2278 +       resume:         NULL,
2279  };
2280
2281 -static int __init
2282 -rtl8169_init_module(void)
2283 +
2284 +
2285 +
2286 +
2287 +//======================================================================================================
2288 +static int __init rtl8169_init_module (void)
2289  {
2290 -       return pci_module_init(&rtl8169_pci_driver);
2291 +       return pci_module_init (&rtl8169_pci_driver);   // pci_register_driver (drv)
2292  }
2293
2294 -static void __exit
2295 -rtl8169_cleanup_module(void)
2296 +
2297 +
2298 +
2299 +//======================================================================================================
2300 +static void __exit rtl8169_cleanup_module (void)
2301  {
2302 -       pci_unregister_driver(&rtl8169_pci_driver);
2303 +       pci_unregister_driver (&rtl8169_pci_driver);
2304  }
2305
2306 +
2307 +
2308 +
2309 +//======================================================================================================
2310  module_init(rtl8169_init_module);
2311  module_exit(rtl8169_cleanup_module);