2 # This patch can be found at http://www.uclinux.org/pub/uClinux/m68k-elf-tools/
4 diff -u -r gcc-2.95.3-orig/ChangeLog gcc-2.95.3/ChangeLog
5 --- gcc-2.95.3-orig/ChangeLog Fri Mar 16 22:52:01 2001
6 +++ gcc-2.95.3/ChangeLog Tue Feb 26 06:52:47 2002
11 + Tue Feb 13 08:08:47 EST 2001 Paul Dale (pauli@lineo.com)
13 + * invoke.teki: Added documentation for the -msep-data and
14 + -mno-sep-data m68k specific options.
16 Tue Mar 7 21:48:55 2000 Jeffrey A Law (law@cygnus.com)
18 * config.guess: Fix detection of ReliantUNIX.
19 diff -u -r gcc-2.95.3-orig/gcc/ChangeLog gcc-2.95.3/gcc/ChangeLog
20 --- gcc-2.95.3-orig/gcc/ChangeLog Fri Mar 16 22:52:02 2001
21 +++ gcc-2.95.3/gcc/ChangeLog Tue Feb 26 06:52:47 2002
23 * expr.h (expand_builtin_setjmp, expand_builtin_setjmp_receiver):
26 +2001-02-13 Paul Dale <pauli@lineo.com>
28 + * lb1sf68.asm: Support build of libgcc.a for position
30 + * m68k-none.h (CPP_SPEC): Define __pic__ and __PIC__ when
31 + generating position independent code.
32 + * m68k.c (override_options): Enable -fPIC when -msep-data
34 + * m68k.c (output_function_prologue): Disable A5 save/restore
35 + code generation when -msep-data is active.
36 + * m68k.c (output_function_epilogue): Disable A5 restore code
37 + generation when -msep-data is active.
38 + * m68k.c (legitimize_pic_address): Don't mark A5 as live if
39 + the -msep-data option is active.
40 + * m68k.h: Define the -msep-data and -mno-sep-data options.
41 + * m68k.h (OVERRIDE_OPTIONS): Allow -fPIC on targets below 68020 and
42 + enable function common subexpressions if generating position
43 + independent code that calls functions via the global offset table.
44 + * m68k.md: Modified PIC call sequences for sub 68020 targets to
45 + either determine relative address inline or to call functions via
46 + the global offset table.
47 + * m68kelf.h (OVERRIDE_OPTIONS): Support -fPIC on sub 68020 targets,
48 + enable function CSE when calling procedures via the GOT and
49 + include call to override_options().
50 + * t-m68kelf: Enable multilib build of -msep-data libraries.
52 2001-01-25 Bernd Schmidt <bernds@redhat.co.uk>
55 diff -u -r gcc-2.95.3-orig/gcc/config/m68k/lb1sf68.asm gcc-2.95.3/gcc/config/m68k/lb1sf68.asm
56 --- gcc-2.95.3-orig/gcc/config/m68k/lb1sf68.asm Tue Mar 2 01:06:44 1999
57 +++ gcc-2.95.3/gcc/config/m68k/lb1sf68.asm Tue Feb 26 06:52:47 2002
64 +/* Provide a few macros to allow for PIC code support.
65 + * With PIC, data is stored A5 relative so we've got to take a bit of special
66 + * care to ensure that all loads of global data is via A5. PIC also requires
67 + * jumps and subroutine calls to be PC relative rather than absolute. We cheat
68 + * a little on this and in the PIC case, we use short offset branches and
69 + * hope that the final object code is within range (which it should be).
72 +/* Non pic (absolute/relocatable) versions */
73 +#define LEA(sym,reg) lea sym, reg
74 +#define PEA(sym,areg) pea sym
75 +#define CALL(addr) jbsr addr
76 +#define JUMP(addr) jmp addr
78 +#ifdef __ID_SHARED_LIBRARY__
79 +/* shared library version */
80 +#define LEA(sym,reg) movel a5@(_current_shared_library_a5_offset_), reg; \
81 + movel CONCAT1(sym, @GOT(reg)), reg
82 +#define PEA(sym,areg) movel a5@(_current_shared_library_a5_offset_), areg; \
83 + movel CONCAT1(sym, @GOT(areg)), sp@-
85 +/* msep-data version */
86 +#define LEA(sym,reg) movel CONCAT1(sym, @GOT(a5)), reg
87 +#define PEA(sym,areg) movel CONCAT1(sym, @GOT(a5)), sp@-
89 +#define CALL(addr) bsr addr
90 +#define JUMP(addr) bra addr
97 | void __clear_sticky_bits(void);
98 SYM (__clear_sticky_bit):
100 + LEA( SYM (_fpCCR),a0)
102 movew IMM (0),a0@(STICK)
108 - lea SYM (_fpCCR),a0
109 + LEA( SYM (_fpCCR),a0)
110 movew d7,a0@(EBITS) | set __exception_bits
112 orw d7,a0@(STICK) | and __sticky_bits
117 - pea SYM (_fpCCR) | yes, push address of _fpCCR
118 + PEA( SYM (_fpCCR),a1)| yes, push address of _fpCCR
119 trap IMM (FPTRAP) | and trap
121 1: moveml sp@+,d2-d7 | restore data registers
126 - jbsr SYM (__udivsi3) /* divide abs(dividend) by abs(divisor) */
127 + CALL( SYM (__udivsi3))/* divide abs(dividend) by abs(divisor) */
131 @@ -441,13 +471,13 @@
132 movel sp@(4), d0 /* d0 = dividend */
135 - jbsr SYM (__udivsi3)
136 + CALL( SYM (__udivsi3))
138 movel sp@(8), d1 /* d1 = divisor */
142 - jbsr SYM (__mulsi3) /* d0 = (a/b)*b */
143 + CALL( SYM (__mulsi3)) /* d0 = (a/b)*b */
147 @@ -467,13 +497,13 @@
148 movel sp@(4), d0 /* d0 = dividend */
151 - jbsr SYM (__divsi3)
152 + CALL( SYM (__divsi3))
154 movel sp@(8), d1 /* d1 = divisor */
158 - jbsr SYM (__mulsi3) /* d0 = (a/b)*b */
159 + CALL( SYM (__mulsi3)) /* d0 = (a/b)*b */
165 movew IMM (INEXACT_RESULT+UNDERFLOW),d7
166 moveq IMM (DOUBLE_FLOAT),d6
167 - jmp $_exception_handler
168 + JUMP( $_exception_handler)
174 movew IMM (INEXACT_RESULT+OVERFLOW),d7
175 moveq IMM (DOUBLE_FLOAT),d6
176 - jmp $_exception_handler
177 + JUMP( $_exception_handler)
180 | Return 0 and set the exception flags
183 movew IMM (INEXACT_RESULT+UNDERFLOW),d7
184 moveq IMM (DOUBLE_FLOAT),d6
185 - jmp $_exception_handler
186 + JUMP( $_exception_handler)
189 | Return a quiet NaN and set the exception flags
192 movew IMM (INEXACT_RESULT+INVALID_OPERATION),d7
193 moveq IMM (DOUBLE_FLOAT),d6
194 - jmp $_exception_handler
195 + JUMP( $_exception_handler)
198 | Return a properly signed INFINITY and set the exception flags
201 movew IMM (INEXACT_RESULT+DIVIDE_BY_ZERO),d7
202 moveq IMM (DOUBLE_FLOAT),d6
203 - jmp $_exception_handler
204 + JUMP( $_exception_handler)
206 |=============================================================================
207 |=============================================================================
208 @@ -1015,8 +1045,8 @@
212 - lea Ladddf$5,a0 | to return from rounding routine
213 - lea SYM (_fpCCR),a1 | check the rounding mode
214 + lea pc@(Ladddf$5),a0 | to return from rounding routine
215 + LEA( SYM (_fpCCR),a1)| check the rounding mode
219 @@ -1123,8 +1153,8 @@
223 - lea Lsubdf$1,a0 | to return from rounding routine
224 - lea SYM (_fpCCR),a1 | check the rounding mode
225 + lea pc@(Lsubdf$1),a0 | to return from rounding routine
226 + LEA( SYM (_fpCCR),a1)| check the rounding mode
230 @@ -1168,7 +1198,7 @@
234 - lea SYM (_fpCCR),a0
235 + LEA( SYM (_fpCCR),a0)
238 moveml sp@+,d2-d7 | restore data registers
239 @@ -1190,7 +1220,7 @@
243 - lea SYM (_fpCCR),a0
244 + LEA( SYM (_fpCCR),a0)
247 moveml sp@+,d2-d7 | restore data registers
248 @@ -1248,7 +1278,7 @@
252 - lea SYM (_fpCCR),a0
253 + LEA( SYM (_fpCCR),a0)
255 orl d7,d0 | put sign bit back
257 @@ -1610,7 +1640,7 @@
258 bclr IMM (31),d2 | clear sign bit
259 1: cmpl IMM (0x7ff00000),d2 | check for non-finiteness
260 bge Ld$inop | in case NaN or +/-INFINITY return NaN
261 - lea SYM (_fpCCR),a0
262 + LEA( SYM (_fpCCR),a0)
266 @@ -1895,7 +1925,7 @@
268 1: movel IMM (0),d0 | else return zero
270 - lea SYM (_fpCCR),a0 | clear exception flags
271 + LEA( SYM (_fpCCR),a0)| clear exception flags
275 @@ -2035,8 +2065,8 @@
276 orl d7,d3 | the bits which were flushed right
277 movel a0,d7 | get back sign bit into d7
278 | Now call the rounding routine (which takes care of denormalized numbers):
279 - lea Lround$0,a0 | to return from rounding routine
280 - lea SYM (_fpCCR),a1 | check the rounding mode
281 + lea pc@(Lround$0),a0 | to return from rounding routine
282 + LEA( SYM (_fpCCR),a1)| check the rounding mode
286 @@ -2084,7 +2114,7 @@
288 orl d7,d0 | and sign also
290 - lea SYM (_fpCCR),a0
291 + LEA( SYM (_fpCCR),a0)
295 @@ -2126,7 +2156,7 @@
296 movel d0,d7 | else get sign and return INFINITY
297 andl IMM (0x80000000),d7
299 -1: lea SYM (_fpCCR),a0
300 +1: LEA( SYM (_fpCCR),a0)
304 @@ -2424,7 +2454,7 @@
306 movew IMM (INEXACT_RESULT+UNDERFLOW),d7
307 moveq IMM (SINGLE_FLOAT),d6
308 - jmp $_exception_handler
309 + JUMP( $_exception_handler)
313 @@ -2433,21 +2463,21 @@
315 movew IMM (INEXACT_RESULT+OVERFLOW),d7
316 moveq IMM (SINGLE_FLOAT),d6
317 - jmp $_exception_handler
318 + JUMP( $_exception_handler)
321 | Return 0 and set the exception flags
323 movew IMM (INEXACT_RESULT+UNDERFLOW),d7
324 moveq IMM (SINGLE_FLOAT),d6
325 - jmp $_exception_handler
326 + JUMP( $_exception_handler)
329 | Return a quiet NaN and set the exception flags
330 movel IMM (QUIET_NaN),d0
331 movew IMM (INEXACT_RESULT+INVALID_OPERATION),d7
332 moveq IMM (SINGLE_FLOAT),d6
333 - jmp $_exception_handler
334 + JUMP( $_exception_handler)
337 | Return a properly signed INFINITY and set the exception flags
338 @@ -2455,7 +2485,7 @@
340 movew IMM (INEXACT_RESULT+DIVIDE_BY_ZERO),d7
341 moveq IMM (SINGLE_FLOAT),d6
342 - jmp $_exception_handler
343 + JUMP( $_exception_handler)
345 |=============================================================================
346 |=============================================================================
347 @@ -2737,8 +2767,8 @@
351 - lea Laddsf$4,a0 | to return from rounding routine
352 - lea SYM (_fpCCR),a1 | check the rounding mode
353 + lea pc@(Laddsf$4),a0 | to return from rounding routine
354 + LEA( SYM (_fpCCR),a1)| check the rounding mode
358 @@ -2802,8 +2832,8 @@
359 | Note that we do not have to normalize, since in the subtraction bit
360 | #FLT_MANT_DIG+1 is never set, and denormalized numbers are handled by
361 | the rounding routines themselves.
362 - lea Lsubsf$1,a0 | to return from rounding routine
363 - lea SYM (_fpCCR),a1 | check the rounding mode
364 + lea pc@(Lsubsf$1),a0 | to return from rounding routine
365 + LEA( SYM (_fpCCR),a1)| check the rounding mode
369 @@ -2834,7 +2864,7 @@
370 | check for finiteness or zero).
373 - lea SYM (_fpCCR),a0
374 + LEA( SYM (_fpCCR),a0)
377 moveml sp@+,d2-d7 | restore data registers
378 @@ -2848,7 +2878,7 @@
382 - lea SYM (_fpCCR),a0
383 + LEA( SYM (_fpCCR),a0)
386 moveml sp@+,d2-d7 | restore data registers
387 @@ -2905,7 +2935,7 @@
389 | Normal exit (a and b nonzero, result is not NaN nor +/-infty).
390 | We have to clear the exception flags (just the exception type).
391 - lea SYM (_fpCCR),a0
392 + LEA( SYM (_fpCCR),a0)
394 orl d7,d0 | put sign bit
396 @@ -3141,7 +3171,7 @@
397 1: bclr IMM (31),d1 | clear sign bit
398 cmpl IMM (INFINITY),d1 | and check for a large exponent
399 bge Lf$inop | if b is +/-INFINITY or NaN return NaN
400 - lea SYM (_fpCCR),a0 | else return zero
401 + LEA( SYM (_fpCCR),a0)| else return zero
405 @@ -3341,7 +3371,7 @@
406 cmpl IMM (INFINITY),d1 | check for NaN
408 movel IMM (0),d0 | else return zero
409 - lea SYM (_fpCCR),a0 |
410 + LEA( SYM (_fpCCR),a0) |
414 @@ -3444,8 +3474,8 @@
415 2: orl d6,d1 | this is a trick so we don't lose '
416 | the extra bits which were flushed right
417 | Now call the rounding routine (which takes care of denormalized numbers):
418 - lea Lround$0,a0 | to return from rounding routine
419 - lea SYM (_fpCCR),a1 | check the rounding mode
420 + lea pc@(Lround$0),a0 | to return from rounding routine
421 + LEA( SYM (_fpCCR),a1)| check the rounding mode
425 @@ -3493,7 +3523,7 @@
427 orl d7,d0 | and sign also
429 - lea SYM (_fpCCR),a0
430 + LEA( SYM (_fpCCR),a0)
434 @@ -3534,7 +3564,7 @@
435 movel d0,d7 | else get sign and return INFINITY
436 andl IMM (0x80000000),d7
438 -1: lea SYM (_fpCCR),a0
439 +1: LEA( SYM (_fpCCR),a0)
443 @@ -3742,7 +3772,7 @@
447 - jbsr SYM (__cmpdf2)
448 + CALL( SYM (__cmpdf2))
452 @@ -3757,7 +3787,7 @@
456 - jbsr SYM (__cmpdf2)
457 + CALL( SYM (__cmpdf2))
461 @@ -3772,7 +3802,7 @@
465 - jbsr SYM (__cmpdf2)
466 + CALL( SYM (__cmpdf2))
470 @@ -3787,7 +3817,7 @@
474 - jbsr SYM (__cmpdf2)
475 + CALL( SYM (__cmpdf2))
479 @@ -3802,7 +3832,7 @@
483 - jbsr SYM (__cmpdf2)
484 + CALL( SYM (__cmpdf2))
488 @@ -3817,7 +3847,7 @@
492 - jbsr SYM (__cmpdf2)
493 + CALL( SYM (__cmpdf2))
497 @@ -3833,7 +3863,7 @@
501 - jbsr SYM (__cmpsf2)
502 + CALL( SYM (__cmpsf2))
506 @@ -3846,7 +3876,7 @@
510 - jbsr SYM (__cmpsf2)
511 + CALL( SYM (__cmpsf2))
515 @@ -3859,7 +3889,7 @@
519 - jbsr SYM (__cmpsf2)
520 + CALL( SYM (__cmpsf2))
524 @@ -3872,7 +3902,7 @@
528 - jbsr SYM (__cmpsf2)
529 + CALL( SYM (__cmpsf2))
533 @@ -3885,7 +3915,7 @@
537 - jbsr SYM (__cmpsf2)
538 + CALL( SYM (__cmpsf2))
542 @@ -3898,7 +3928,7 @@
546 - jbsr SYM (__cmpsf2)
547 + CALL( SYM (__cmpsf2))
551 diff -u -r gcc-2.95.3-orig/gcc/config/m68k/m68k-none.h gcc-2.95.3/gcc/config/m68k/m68k-none.h
552 --- gcc-2.95.3-orig/gcc/config/m68k/m68k-none.h Thu Dec 17 07:06:54 1998
553 +++ gcc-2.95.3/gcc/config/m68k/m68k-none.h Tue Feb 26 06:52:47 2002
556 #if TARGET_DEFAULT & MASK_68881
557 #define CPP_FPU_SPEC "\
558 -%{!mc68000:%{!m68000:%{!m68302:%{!mcpu32:%{!m68332:%{!m5200:%{!msoft-float:%{!mno-68881:%{!mfpa:%{!msky:-D__HAVE_68881__ }}}}}}}}}} \
559 +%{!mc68000:%{!m68000:%{!m68302:%{!mcpu32:%{!m68332:%{!m5200:%{!m5307:%{!msoft-float:%{!mno-68881:%{!mfpa:%{!msky:-D__HAVE_68881__ }}}}}}}}}}} \
560 %{m68881:-D__HAVE_68881__ }%{mfpa:-D__HAVE_FPA__ }%{msky:-D__HAVE_SKY__ }"
562 /* This can't currently happen, but we code it anyway to show how it's done. */
564 -m68332: define mc68332 mcpu32
565 -mcpu32: define mcpu32
566 -m5200: define mcf5200
567 + -m5307: define mcf5307
568 default: define as above appropriately
570 GCC won't automatically add __'d versions, we have to mention them
575 -%(cpp_fpu)%{!ansi:%{m68302:-Dmc68302 }%{m68010:-Dmc68010 }%{m68020:-Dmc68020 }%{mc68020:-Dmc68020 }%{m68030:-Dmc68030 }%{m68040:-Dmc68040 }%{m68020-40:-Dmc68020 -Dmc68030 -Dmc68040 }%{m68020-60:-Dmc68020 -Dmc68030 -Dmc68040 -Dmc68060 }%{m68060:-Dmc68060 }%{mcpu32:-Dmcpu32 } %{m68332:-Dmc68332 -Dmcpu32 }%{m5200:-Dmcf5200 }} \
576 -%{m68302:-D__mc68302__ -D__mc68302 }%{m68010:-D__mc68010__ -D__mc68010 }%{m68020:-D__mc68020__ -D__mc68020 }%{mc68020:-D__mc68020__ -D__mc68020 }%{m68030:-D__mc68030__ -D__mc68030 }%{m68040:-D__mc68040__ -D__mc68040 }%{m68020-40:-D__mc68020__ -D__mc68030__ -D__mc68040__ -D__mc68020 -D__mc68030 -D__mc68040 }%{m68020-60:-D__mc68020__ -D__mc68030__ -D__mc68040__ -D__mc68020 -D__mc68030 -D__mc68040 -D__mc68060__ -D__mc68060 }%{m68060:-D__mc68060__ -D__mc68060 }%{mcpu32:-D__mcpu32__ -D__mcpu32 }%{m68332:-D__mc68332__ -D__mc68332 -D__mcpu32__ -D__mcpu32 }%{m5200:-D__mcf5200__ -D__mcf5200 } \
577 -%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32: %{!m68332:%{!m5200:%(cpp_cpu_default)}}}}}}}}}}}}}} \
578 +%(cpp_fpu)%{!ansi:%{m68302:-Dmc68302 }%{m68010:-Dmc68010 }%{m68020:-Dmc68020 }%{mc68020:-Dmc68020 }%{m68030:-Dmc68030 }%{m68040:-Dmc68040 }%{m68020-40:-Dmc68020 -Dmc68030 -Dmc68040 }%{m68020-60:-Dmc68020 -Dmc68030 -Dmc68040 -Dmc68060 }%{m68060:-Dmc68060 }%{mcpu32:-Dmcpu32 } %{m68332:-Dmc68332 -Dmcpu32 }%{m5200:-Dmcf5200 }%{m5307:-Dmcf5307 -Dmcf5200 }} \
579 +%{m68302:-D__mc68302__ -D__mc68302 }%{m68010:-D__mc68010__ -D__mc68010 }%{m68020:-D__mc68020__ -D__mc68020 }%{mc68020:-D__mc68020__ -D__mc68020 }%{m68030:-D__mc68030__ -D__mc68030 }%{m68040:-D__mc68040__ -D__mc68040 }%{m68020-40:-D__mc68020__ -D__mc68030__ -D__mc68040__ -D__mc68020 -D__mc68030 -D__mc68040 }%{m68020-60:-D__mc68020__ -D__mc68030__ -D__mc68040__ -D__mc68020 -D__mc68030 -D__mc68040 -D__mc68060__ -D__mc68060 }%{m68060:-D__mc68060__ -D__mc68060 }%{mcpu32:-D__mcpu32__ -D__mcpu32 }%{m68332:-D__mc68332__ -D__mc68332 -D__mcpu32__ -D__mcpu32 }%{m5200:-D__mcf5200__ -D__mcf5200 }%{m5307:-D__mcf5307__ -D__mcf5307 -D__mcf5200__ -D__mcf5200 } \
580 +%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32: %{!m68332:%{!m5200:%{!m5307:%(cpp_cpu_default)}}}}}}}}}}}}}}} \
581 +%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{msep-data:-D__PIC__ -D__pic__} %{mid-shared-library:-D__PIC__ -D__pic__ -D__ID_SHARED_LIBRARY__} \
589 -%{m68851}%{mno-68851}%{m68881}%{mno-68881}%{msoft-float:-mno-68881 }%{m68000}%{m68302}%{mc68000}%{m68010}%{m68020}%{mc68020}%{m68030}%{m68040}%{m68020-40:-mc68040 }%{m68020-60:-mc68040 }%{m68060}%{mcpu32}%{m68332}%{m5200}%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32:%{!m68332:%{!m5200:%(asm_cpu_default) }}}}}}}}}}}}}} \
590 +%{m68851}%{mno-68851}%{m68881}%{mno-68881}%{msoft-float:-mno-68881 }%{m68000}%{m68302}%{mc68000}%{m68010}%{m68020}%{mc68020}%{m68030}%{m68040}%{m68020-40:-mc68040 }%{m68020-60:-mc68040 }%{m68060}%{mcpu32}%{m68332}%{m5200}%{m5307}%{mhwdiv}%{mno-hwdiv}%{mmac}%{mno-mac}%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32:%{!m68332:%{!m5200:%{!m5307:%(asm_cpu_default) }}}}}}}}}}}}}}} \
591 +%{fPIC:--pcrel} %{fpic:--pcrel} %{msep-data:--pcrel} %{mid-shared-library:--pcrel} \
594 /* cc1/cc1plus always receives all the -m flags. If the specs strings above
595 diff -u -r gcc-2.95.3-orig/gcc/config/m68k/m68k.c gcc-2.95.3/gcc/config/m68k/m68k.c
596 --- gcc-2.95.3-orig/gcc/config/m68k/m68k.c Mon Aug 2 14:51:08 1999
597 +++ gcc-2.95.3/gcc/config/m68k/m68k.c Tue Feb 26 08:14:52 2002
599 /* Needed for use_return_insn. */
602 +#define MUST_SAVE_REGISTER(regno) \
603 + (! TREE_THIS_VOLATILE (current_function_decl) \
604 + && (regno != STACK_POINTER_REGNUM) \
605 + /* Save any call saved register that was used. */ \
606 + && (regs_ever_live[regno] && !call_used_regs[regno]) \
607 + /* Save any register used in an interrupt handler. */ \
608 + || (regs_ever_live[regno] && interrupt_handler) \
609 + /* Save call clobbered registers in non-leaf interrupt handlers. */ \
610 + || (call_used_regs[regno] && interrupt_handler && !current_function_is_leaf))
613 #ifdef SUPPORT_SUN_FPA
615 /* Index into this array by (register number >> 3) to find the
617 const char *m68k_align_jumps_string;
618 /* Specify power of two alignment used for functions. */
619 const char *m68k_align_funcs_string;
620 +/* Specified the identification number of the library being built */
621 +const char *m68k_library_id_string;
623 /* Specify power of two alignment used for loops. */
624 int m68k_align_loops;
626 int m68k_align_jumps;
627 /* Specify power of two alignment used for functions. */
628 int m68k_align_funcs;
629 +/* Specify library identification number */
630 +int m68k_library_id;
632 /* Nonzero if the last compare/test insn had FP operands. The
633 sCC expanders peek at this to determine what to do for the
637 m68k_align_funcs = def_align;
639 + /* Library identification */
640 + if (m68k_library_id_string)
642 + if (! TARGET_ID_SHARED_LIBRARY)
643 + fatal("-mshared-library-id= specified without -mid-shared-library");
644 + m68k_library_id = atoi (m68k_library_id_string);
645 + if (m68k_library_id < 0 || m68k_library_id > MAX_LIBRARY_ID)
646 + fatal ("-mshared-library-id=%d is not between 0 and %d",
647 + m68k_library_id, MAX_LIBRARY_ID);
650 + m68k_library_id = -1;
652 + /* Sanity check to ensure that msep-data and mid-sahred-library are not
653 + * both specified together. Doing so simply doesn't make sense.
655 + if (TARGET_SEP_DATA && TARGET_ID_SHARED_LIBRARY)
656 + fatal("cannot specify both -msep-data and -mid-sahred-library");
658 + /* If we're generating code for a separate A5 relative data segment,
659 + * we've got to enable -fPIC as well. This might be relaxable to
660 + * -fpic but it hasn't been tested properly.
662 + if (TARGET_SEP_DATA || TARGET_ID_SHARED_LIBRARY)
666 /* This function generates the assembly code for function entry.
668 extern char call_used_regs[];
669 int fsize = (size + 3) & -4;
670 int cfa_offset = INCOMING_FRAME_SP_OFFSET, cfa_store_offset = cfa_offset;
671 + int interrupt_handler = m68k_interrupt_function_p (current_function_decl);
674 if (frame_pointer_needed)
677 #ifdef SUPPORT_SUN_FPA
678 for (regno = 24; regno < 56; regno++)
679 - if (regs_ever_live[regno] && ! call_used_regs[regno])
680 + if (MUST_SAVE_REGISTER(regno))
683 asm_fprintf (stream, "\tfpmovd %s,-(%Rsp)\n",
687 for (regno = 16; regno < 24; regno++)
688 - if (regs_ever_live[regno] && ! call_used_regs[regno])
689 + if (MUST_SAVE_REGISTER(regno))
691 mask |= 1 << (regno - 16);
696 for (regno = 0; regno < 16; regno++)
697 - if (regs_ever_live[regno] && ! call_used_regs[regno])
698 + if (MUST_SAVE_REGISTER(regno))
700 mask |= 1 << (15 - regno);
703 mask &= ~ (1 << (15 - FRAME_POINTER_REGNUM));
706 - if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
707 + if (! TARGET_SEP_DATA && flag_pic &&
708 + (regs_ever_live[PIC_OFFSET_TABLE_REGNUM] ||
709 + ( ! current_function_is_leaf && TARGET_ID_SHARED_LIBRARY)))
711 mask |= 1 << (15 - PIC_OFFSET_TABLE_REGNUM);
713 @@ -462,18 +506,39 @@
714 -cfa_store_offset + n_regs++ * 4);
717 - if (flag_pic && current_function_uses_pic_offset_table)
718 + if (! TARGET_SEP_DATA && flag_pic &&
719 + (current_function_uses_pic_offset_table ||
720 + ( ! current_function_is_leaf && TARGET_ID_SHARED_LIBRARY)))
722 + if (! TARGET_ID_SHARED_LIBRARY)
725 - asm_fprintf (stream, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
726 - reg_names[PIC_OFFSET_TABLE_REGNUM]);
727 + asm_fprintf (stream, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
728 + reg_names[PIC_OFFSET_TABLE_REGNUM]);
730 - asm_fprintf (stream, "\tmovel %0I__GLOBAL_OFFSET_TABLE_, %s\n",
731 - reg_names[PIC_OFFSET_TABLE_REGNUM]);
732 - asm_fprintf (stream, "\tlea %Rpc@(0,%s:l),%s\n",
733 - reg_names[PIC_OFFSET_TABLE_REGNUM],
734 - reg_names[PIC_OFFSET_TABLE_REGNUM]);
735 + asm_fprintf (stream, "\tmovel %0I__GLOBAL_OFFSET_TABLE_, %s\n",
736 + reg_names[PIC_OFFSET_TABLE_REGNUM]);
737 + asm_fprintf (stream, "\tlea %Rpc@(0,%s:l),%s\n",
738 + reg_names[PIC_OFFSET_TABLE_REGNUM],
739 + reg_names[PIC_OFFSET_TABLE_REGNUM]);
744 + if (m68k_library_id > 0)
746 + asm_fprintf (stream, "\tmovel %s@(%d), %s\n",
747 + reg_names[PIC_OFFSET_TABLE_REGNUM],
748 + m68k_library_id * -4 - 4,
749 + reg_names[PIC_OFFSET_TABLE_REGNUM]);
753 + asm_fprintf (stream, "\tmovel %s@(_current_shared_library_a5_offset_), %s\n",
754 + reg_names[PIC_OFFSET_TABLE_REGNUM],
755 + reg_names[PIC_OFFSET_TABLE_REGNUM]);
761 @@ -483,15 +554,23 @@
765 + int interrupt_handler = m68k_interrupt_function_p (current_function_decl);
767 if (!reload_completed || frame_pointer_needed || get_frame_size () != 0)
770 + /* Check for needing a5 for PIC duties and thus epilogue... */
771 + if (! TARGET_SEP_DATA && flag_pic &&
772 + (regs_ever_live[PIC_OFFSET_TABLE_REGNUM] ||
773 + current_function_uses_pic_offset_table ||
774 + ( ! current_function_is_leaf && TARGET_ID_SHARED_LIBRARY)))
777 /* Copied from output_function_epilogue (). We should probably create a
778 separate layout routine to perform the common work. */
780 for (regno = 0 ; regno < FIRST_PSEUDO_REGISTER ; regno++)
781 - if (regs_ever_live[regno] && ! call_used_regs[regno])
782 + if (MUST_SAVE_REGISTER(regno))
788 rtx insn = get_last_insn ();
789 int restore_from_sp = 0;
790 + int interrupt_handler = m68k_interrupt_function_p (current_function_decl);
792 /* If the last insn was a BARRIER, we don't have to write any code. */
793 if (GET_CODE (insn) == NOTE)
795 nregs = 0; fmask = 0; fpoffset = 0;
796 #ifdef SUPPORT_SUN_FPA
797 for (regno = 24 ; regno < 56 ; regno++)
798 - if (regs_ever_live[regno] && ! call_used_regs[regno])
799 + if (MUST_SAVE_REGISTER(regno))
801 fpoffset = nregs * 8;
806 for (regno = 16; regno < 24; regno++)
807 - if (regs_ever_live[regno] && ! call_used_regs[regno])
808 + if (MUST_SAVE_REGISTER(regno))
811 fmask |= 1 << (23 - regno);
812 @@ -563,12 +643,14 @@
813 if (frame_pointer_needed)
814 regs_ever_live[FRAME_POINTER_REGNUM] = 0;
815 for (regno = 0; regno < 16; regno++)
816 - if (regs_ever_live[regno] && ! call_used_regs[regno])
817 + if (MUST_SAVE_REGISTER(regno))
822 - if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
823 + if (! TARGET_SEP_DATA && flag_pic &&
824 + (regs_ever_live[PIC_OFFSET_TABLE_REGNUM] ||
825 + ( ! current_function_is_leaf && TARGET_ID_SHARED_LIBRARY)))
828 mask |= 1 << PIC_OFFSET_TABLE_REGNUM;
829 @@ -583,14 +665,28 @@
831 && (mask || fmask || fpoffset))
833 + /* Because the ColdFire doesn't support moveml with
834 + complex address modes we make an extra correction here */
838 + asm_fprintf (stream, "\t%Omove.l %0I%d,%Ra1\n", -fsize - offset);
840 + asm_fprintf (stream, "\tmovel %0I%d,%Ra1\n", -fsize - offset );
846 - asm_fprintf (stream, "\t%Omove.l %0I%d,%Ra1\n", -fsize);
847 + asm_fprintf (stream, "\t%Omove.l %0I%d,%Ra1\n", -fsize);
849 - asm_fprintf (stream, "\tmovel %0I%d,%Ra1\n", -fsize);
850 + asm_fprintf (stream, "\tmovel %0I%d,%Ra1\n", -fsize);
856 - if (TARGET_5200 || nregs <= 2)
859 /* Restore each separately in the same order moveml does.
860 Using two movel instructions instead of a single moveml
861 @@ -644,41 +740,85 @@
867 + /* The ColdFire requires special handling due to its limited moveml insn */
874 - asm_fprintf (stream, "\tmovm.l -%d(%s,%Ra1.l),%0I0x%x\n",
876 - reg_names[FRAME_POINTER_REGNUM],
878 + asm_fprintf (stream, "\tadd.l %s,%Ra1\n", reg_names[FRAME_POINTER_REGNUM]);
879 + asm_fprintf (stream, "\tmovm.l (%Ra1),%0I0x%x\n", mask);
881 - asm_fprintf (stream, "\tmoveml %s@(-%d,%Ra1:l),%0I0x%x\n",
882 - reg_names[FRAME_POINTER_REGNUM],
883 - offset + fsize, mask);
884 + asm_fprintf (stream, "\taddl %s,%Ra1\n", reg_names[FRAME_POINTER_REGNUM]);
885 + asm_fprintf (stream, "\tmoveml %Ra1@,%0I0x%x\n", mask);
888 - else if (restore_from_sp)
891 + else if (restore_from_sp)
894 - asm_fprintf (stream, "\tmovm.l (%Rsp)+,%0I0x%x\n", mask);
895 + asm_fprintf (stream, "\tmovm.l (%Rsp),%0I0x%x\n", mask);
896 + asm_fprintf (stream, "\tlea (%d,%Rsp),%Rsp\n", nregs*4);
898 - asm_fprintf (stream, "\tmoveml %Rsp@+,%0I0x%x\n", mask);
899 + asm_fprintf (stream, "\tmoveml %Rsp@,%0I0x%x\n", mask);
900 + asm_fprintf (stream, "\tlea %Rsp@(%d),%Rsp\n", nregs*4);
908 + asm_fprintf (stream, "\tmovm.l -%d(%s),%0I0x%x\n",
910 + reg_names[FRAME_POINTER_REGNUM],
913 + asm_fprintf (stream, "\tmoveml %s@(-%d),%0I0x%x\n",
914 + reg_names[FRAME_POINTER_REGNUM],
915 + offset + fsize, mask);
926 - asm_fprintf (stream, "\tmovm.l -%d(%s),%0I0x%x\n",
928 - reg_names[FRAME_POINTER_REGNUM],
930 + asm_fprintf (stream, "\tmovm.l -%d(%s,%Ra1.l),%0I0x%x\n",
932 + reg_names[FRAME_POINTER_REGNUM],
935 - asm_fprintf (stream, "\tmoveml %s@(-%d),%0I0x%x\n",
936 - reg_names[FRAME_POINTER_REGNUM],
937 - offset + fsize, mask);
938 + asm_fprintf (stream, "\tmoveml %s@(-%d,%Ra1:l),%0I0x%x\n",
939 + reg_names[FRAME_POINTER_REGNUM],
940 + offset + fsize, mask);
945 + else if (restore_from_sp)
948 + asm_fprintf (stream, "\tmovm.l (%Rsp)+,%0I0x%x\n", mask);
950 + asm_fprintf (stream, "\tmoveml %Rsp@+,%0I0x%x\n", mask);
956 + asm_fprintf (stream, "\tmovm.l -%d(%s),%0I0x%x\n",
958 + reg_names[FRAME_POINTER_REGNUM],
961 + asm_fprintf (stream, "\tmoveml %s@(-%d),%0I0x%x\n",
962 + reg_names[FRAME_POINTER_REGNUM],
963 + offset + fsize, mask);
975 for (regno = 55; regno >= 24; regno--)
976 - if (regs_ever_live[regno] && ! call_used_regs[regno])
977 + if (MUST_SAVE_REGISTER(regno))
981 @@ -827,11 +967,18 @@
982 asm_fprintf (stream, "\taddl %0I%d,%Rsp\n", fsize + 4);
986 - if (current_function_pops_args)
987 - asm_fprintf (stream, "\trtd %0I%d\n", current_function_pops_args);
989 + if (interrupt_handler)
991 + fprintf (stream, "\trte\n");
994 - fprintf (stream, "\trts\n");
996 + if (current_function_pops_args)
997 + asm_fprintf (stream, "\trtd %0I%d\n", current_function_pops_args);
999 + fprintf (stream, "\trts\n");
1003 /* Similar to general_operand, but exclude stack_pointer_rtx. */
1004 @@ -1334,7 +1481,7 @@
1005 gen_rtx_PLUS (Pmode,
1006 pic_offset_table_rtx, orig));
1007 current_function_uses_pic_offset_table = 1;
1008 - if (reload_in_progress)
1009 + if (! TARGET_SEP_DATA && reload_in_progress)
1010 regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
1011 RTX_UNCHANGING_P (pic_ref) = 1;
1012 emit_move_insn (reg, pic_ref);
1013 @@ -1424,7 +1571,7 @@
1014 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1018 + return TARGET_5200 ? 1 : 2;
1022 @@ -3397,3 +3544,76 @@
1024 return "eor%.l %2,%0";
1027 +/* Return nonzero if ATTR is a valid attribute for DECL.
1028 + ATTRIBUTES are any existing attributes and ARGS are the arguments
1029 + supplied with ATTR.
1031 + Supported attributes:
1033 + interrupt -- specifies this function is an interrupt handler.
1037 +m68k_valid_machine_decl_attribute (decl, attributes, attr, args)
1043 + if (args != NULL_TREE)
1046 + if (is_attribute_p ("interrupt", attr))
1047 + return TREE_CODE (decl) == FUNCTION_DECL;
1052 +/* Return nonzero if FUNC is an interrupt function as specified by the
1053 + "interrupt" attribute. */
1056 +m68k_interrupt_function_p(func)
1061 + if (TREE_CODE (func) != FUNCTION_DECL)
1064 + a = lookup_attribute ("interrupt", DECL_MACHINE_ATTRIBUTES (func));
1065 + return (a != NULL_TREE);
1068 +/* Return the initial difference between the
1069 + frame pointer reg contents and the stack pointer reg contents,
1070 + as of the start of the function body. This depends on the layout
1071 + of the fixed parts of the stack frame and on how registers are saved.
1073 + On the 68k, if we have a frame, we must add one word to its length
1074 + to allow for the place that a6 is stored when we do have a frame pointer.
1075 + Otherwise, we would need to compute the offset from the frame pointer
1076 + of a local variable as a function of frame_pointer_needed, which
1080 +initial_fp_offset(void) {
1081 + int interrupt_handler = m68k_interrupt_function_p (current_function_decl);
1085 + for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++)
1086 + if (MUST_SAVE_REGISTER(regno))
1088 + for (regno = 0; regno < 16; regno++)
1089 + if (MUST_SAVE_REGISTER(regno))
1091 + if (flag_pic && ! TARGET_SEP_DATA &&
1092 + (current_function_uses_pic_offset_table ||
1093 + ( ! current_function_is_leaf && TARGET_ID_SHARED_LIBRARY)))
1095 + return (offset + ((get_frame_size () + 3) & -4)
1096 + + (get_frame_size () == 0 ? 0 : 4));
1099 diff -u -r gcc-2.95.3-orig/gcc/config/m68k/m68k.h gcc-2.95.3/gcc/config/m68k/m68k.h
1100 --- gcc-2.95.3-orig/gcc/config/m68k/m68k.h Fri Jan 26 00:03:34 2001
1101 +++ gcc-2.95.3/gcc/config/m68k/m68k.h Tue Feb 26 06:52:47 2002
1102 @@ -120,6 +120,29 @@
1103 #define MASK_ALIGN_INT 4096
1104 #define TARGET_ALIGN_INT (target_flags & MASK_ALIGN_INT)
1106 +/* Support A5 relative data seperate from text.
1107 + * This option implies -fPIC, however it inhibits the generation of the
1108 + * A5 save/restore in functions and the loading of a5 with a got pointer.
1110 +#define MASK_SEP_DATA 8192
1111 +#define TARGET_SEP_DATA (target_flags & MASK_SEP_DATA)
1113 +/* Compile for ColdFire with hardware divide (5307 etc.) */
1114 +#define MASK_CF_HWDIV 16384
1115 +#define TARGET_CF_HWDIV (target_flags & MASK_CF_HWDIV)
1117 +#define TARGET_5200_HWDIV (TARGET_5200 && TARGET_CF_HWDIV)
1119 +/* Compile for mcf5300 */
1120 +#define MASK_5300 32768
1121 +#define TARGET_5300 (target_flags & MASK_5300)
1123 +/* Compile using library ID based shared libraries.
1124 + * Set a specific ID using the -mshared-library-id=xxx option.
1126 +#define MASK_ID_SHARED_LIBRARY 65536
1127 +#define TARGET_ID_SHARED_LIBRARY (target_flags & MASK_ID_SHARED_LIBRARY)
1129 /* Compile for a CPU32 */
1130 /* A 68020 without bitfields is a good heuristic for a CPU32 */
1131 #define TARGET_CPU32 (TARGET_68020 && !TARGET_BITFIELD)
1133 { "5200", - (MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
1134 |MASK_BITFIELD|MASK_68881)}, \
1135 { "5200", (MASK_5200)}, \
1136 + { "5307", - (MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
1137 + |MASK_BITFIELD|MASK_68881)}, \
1138 + { "5307", (MASK_5200|MASK_5300|MASK_CF_HWDIV)}, \
1141 { "68302", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
1142 @@ -182,6 +208,14 @@
1143 { "cpu32", MASK_68020}, \
1144 { "align-int", MASK_ALIGN_INT }, \
1145 { "no-align-int", -MASK_ALIGN_INT }, \
1146 + { "sep-data", MASK_SEP_DATA, "Enable separate data segment" }, \
1147 + { "no-sep-data", -MASK_SEP_DATA, "Disable separate data segment" }, \
1148 + { "id-shared-library", MASK_ID_SHARED_LIBRARY, "Enable ID based shared library" }, \
1149 + { "no-id-shared-library", -MASK_ID_SHARED_LIBRARY, "Disable ID based shared library" }, \
1150 + { "hwdiv", MASK_CF_HWDIV }, \
1151 + { "no-hwdiv", -MASK_CF_HWDIV }, \
1153 + { "no-mac", 0 }, \
1154 SUBTARGET_SWITCHES \
1155 { "", TARGET_DEFAULT}}
1156 /* TARGET_DEFAULT is defined in sun*.h and isi.h, etc. */
1158 { { "align-loops=", &m68k_align_loops_string }, \
1159 { "align-jumps=", &m68k_align_jumps_string }, \
1160 { "align-functions=", &m68k_align_funcs_string }, \
1161 + { "shared-library-id=", &m68k_library_id_string }, \
1166 #define OVERRIDE_OPTIONS \
1168 override_options(); \
1169 - if (! TARGET_68020 && flag_pic == 2) \
1170 - error("-fPIC is not currently supported on the 68000 or 68010\n"); \
1171 + if (flag_pic && (! optimize_size || TARGET_68020) && \
1172 + ! TARGET_ID_SHARED_LIBRARY ) \
1173 + flag_no_function_cse = 1; \
1174 SUBTARGET_OVERRIDE_OPTIONS; \
1178 /* Maximum power of 2 that code can be aligned to. */
1179 #define MAX_CODE_ALIGN 2 /* 4 byte alignment */
1181 +/* Maximum number of library ids we permit */
1182 +#define MAX_LIBRARY_ID 255
1184 /* Align loop starts for optimal branching. */
1185 #define LOOP_ALIGN(LABEL) (m68k_align_loops)
1187 @@ -414,6 +453,12 @@
1189 #endif /* defined SUPPORT_SUN_FPA */
1191 +/* A C expression whose value is nonzero if IDENTIFIER with arguments ARGS
1192 + is a valid machine specific attribute for DECL.
1193 + The attributes in ATTRIBUTES have previously been assigned to DECL. */
1194 +extern int m68k_valid_machine_decl_attribute ();
1195 +#define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, IDENTIFIER, ARGS) \
1196 +m68k_valid_machine_decl_attribute (DECL, ATTRIBUTES, IDENTIFIER, ARGS)
1198 /* Make sure everything's fine if we *don't* have a given processor.
1199 This assumes that putting a register in fixed_regs will keep the
1200 @@ -1178,7 +1223,7 @@
1201 /* Determine if the epilogue should be output as RTL.
1202 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1203 #define USE_RETURN_INSN use_return_insn ()
1206 /* Store in the variable DEPTH the initial difference between the
1207 frame pointer reg contents and the stack pointer reg contents,
1208 as of the start of the function body. This depends on the layout
1209 @@ -1190,20 +1235,8 @@
1210 of a local variable as a function of frame_pointer_needed, which
1213 -#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
1215 - int offset = -4; \
1216 - for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \
1217 - if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1219 - for (regno = 0; regno < 16; regno++) \
1220 - if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1222 - if (flag_pic && current_function_uses_pic_offset_table) \
1224 - (DEPTH) = (offset + ((get_frame_size () + 3) & -4) \
1225 - + (get_frame_size () == 0 ? 0 : 4)); \
1227 +#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = initial_fp_offset();
1230 /* Output assembler code for a block containing the constant parts
1231 of a trampoline, leaving space for the variable parts. */
1232 @@ -1640,9 +1673,10 @@
1233 relative to an average of the time for add and the time for shift,
1234 taking away a little more because sometimes move insns are needed. */
1235 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */
1236 -#define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : 13)
1237 -#define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : 5)
1238 -#define DIVW_COST (TARGET_68020 ? 27 : 12)
1239 +#define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : TARGET_5300 ? 3 : TARGET_5200 ? 10 : 13)
1240 +#define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : \
1241 + TARGET_5300 ? 2 : 5)
1242 +#define DIVW_COST (TARGET_68020 ? 27 : TARGET_CF_HWDIV ? 11 : 12)
1244 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1246 @@ -1654,15 +1688,19 @@
1247 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1248 && (INTVAL (XEXP (XEXP (X, 0), 1)) == 2 \
1249 || INTVAL (XEXP (XEXP (X, 0), 1)) == 4 \
1250 - || INTVAL (XEXP (XEXP (X, 0), 1)) == 8)) \
1251 - return COSTS_N_INSNS (3); /* lea an@(dx:l:i),am */ \
1252 + || INTVAL (XEXP (XEXP (X, 0), 1)) == 8)) { \
1253 + if (TARGET_5200) \
1254 + return COSTS_N_INSNS (2); \
1256 + return COSTS_N_INSNS (3); /* lea an@(dx:l:i),am */ \
1263 return COSTS_N_INSNS(1); \
1264 - if (! TARGET_68020) \
1265 + if (! TARGET_68020 && ! TARGET_5200) \
1267 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
1269 @@ -1680,8 +1718,12 @@
1270 return COSTS_N_INSNS (2); /* clrw;swap */ \
1271 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1272 && !(INTVAL (XEXP (X, 1)) > 0 \
1273 - && INTVAL (XEXP (X, 1)) <= 8)) \
1274 - return COSTS_N_INSNS (3); /* lsr #i,dn */ \
1275 + && INTVAL (XEXP (X, 1)) <= 8)) { \
1276 + if (TARGET_5200) \
1277 + return COSTS_N_INSNS(1); \
1279 + return COSTS_N_INSNS (3); /* lsr #i,dn */ \
1283 if ((GET_CODE (XEXP (X, 0)) == ZERO_EXTEND \
1284 @@ -1698,6 +1740,8 @@
1286 if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \
1287 return COSTS_N_INSNS (DIVW_COST); /* div.w */ \
1288 + if (TARGET_CF_HWDIV) \
1289 + return COSTS_N_INSNS(18); \
1290 return COSTS_N_INSNS (43); /* div.l */
1292 /* Tell final.c how to eliminate redundant test instructions. */
1293 @@ -2083,6 +2127,11 @@
1295 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1297 +/* The maximum alignment which the object file format can support. */
1298 +#undef MAX_OFILE_ALIGNMENT
1299 +#define MAX_OFILE_ALIGNMENT 128
1302 /* Define functions defined in aux-output.c and used in templates. */
1304 extern char *output_move_const_into_data_reg ();
1305 @@ -2115,6 +2164,8 @@
1306 extern const char *m68k_align_loops_string;
1307 extern const char *m68k_align_jumps_string;
1308 extern const char *m68k_align_funcs_string;
1309 +extern const char *m68k_library_id_string;
1310 +extern int m68k_library_id;
1311 extern int m68k_align_loops;
1312 extern int m68k_align_jumps;
1313 extern int m68k_align_funcs;
1314 @@ -2133,6 +2184,7 @@
1315 extern void notice_update_cc ();
1316 extern void finalize_pic ();
1317 extern void override_options ();
1318 +extern int initial_fp_offset ();
1322 diff -u -r gcc-2.95.3-orig/gcc/config/m68k/m68k.md gcc-2.95.3/gcc/config/m68k/m68k.md
1323 --- gcc-2.95.3-orig/gcc/config/m68k/m68k.md Thu Aug 5 16:22:05 1999
1324 +++ gcc-2.95.3/gcc/config/m68k/m68k.md Tue Feb 26 06:52:47 2002
1325 @@ -3516,13 +3516,23 @@
1327 ;; Remainder instructions.
1329 -(define_insn "divmodsi4"
1330 +(define_expand "divmodsi4"
1332 + [(set (match_operand:SI 0 "general_operand" "")
1333 + (div:SI (match_operand:SI 1 "general_operand" "")
1334 + (match_operand:SI 2 "general_operand" "")))
1335 + (set (match_operand:SI 3 "general_operand" "")
1336 + (mod:SI (match_dup 1) (match_dup 2)))])]
1337 + "TARGET_68020 || TARGET_5200_HWDIV"
1341 [(set (match_operand:SI 0 "general_operand" "=d")
1342 (div:SI (match_operand:SI 1 "general_operand" "0")
1343 (match_operand:SI 2 "general_operand" "dmsK")))
1344 (set (match_operand:SI 3 "general_operand" "=d")
1345 (mod:SI (match_dup 1) (match_dup 2)))]
1346 - "TARGET_68020 && !TARGET_5200"
1350 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1351 @@ -3531,13 +3541,40 @@
1352 return \"divsl%.l %2,%3:%0\";
1355 -(define_insn "udivmodsi4"
1357 + [(set (match_operand:SI 0 "general_operand" "=d")
1358 + (div:SI (match_operand:SI 1 "general_operand" "0")
1359 + (match_operand:SI 2 "general_operand" "dQ")))
1360 + (set (match_operand:SI 3 "general_operand" "=&d")
1361 + (mod:SI (match_dup 1) (match_dup 2)))]
1362 + "TARGET_5200_HWDIV"
1365 + if (find_reg_note (insn, REG_UNUSED, operands[3]))
1366 + return \"divs%.l %2,%0\";
1367 + else if (find_reg_note (insn, REG_UNUSED, operands[0]))
1368 + return \"rems%.l %2,%3:%0\";
1370 + return \"rems%.l %2,%3:%0\;divs%.l %2,%0\";
1373 +(define_expand "udivmodsi4"
1375 + [(set (match_operand:SI 0 "general_operand" "")
1376 + (udiv:SI (match_operand:SI 1 "general_operand" "")
1377 + (match_operand:SI 2 "general_operand" "")))
1378 + (set (match_operand:SI 3 "general_operand" "")
1379 + (umod:SI (match_dup 1) (match_dup 2)))])]
1380 + "TARGET_68020 || TARGET_5200_HWDIV"
1384 [(set (match_operand:SI 0 "general_operand" "=d")
1385 (udiv:SI (match_operand:SI 1 "general_operand" "0")
1386 (match_operand:SI 2 "general_operand" "dmsK")))
1387 (set (match_operand:SI 3 "general_operand" "=d")
1388 (umod:SI (match_dup 1) (match_dup 2)))]
1389 - "TARGET_68020 && !TARGET_5200"
1393 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1394 @@ -3546,13 +3583,30 @@
1395 return \"divul%.l %2,%3:%0\";
1399 + [(set (match_operand:SI 0 "general_operand" "=d")
1400 + (udiv:SI (match_operand:SI 1 "general_operand" "0")
1401 + (match_operand:SI 2 "general_operand" "dQ")))
1402 + (set (match_operand:SI 3 "general_operand" "=&d")
1403 + (umod:SI (match_dup 1) (match_dup 2)))]
1404 + "TARGET_5200_HWDIV"
1407 + if (find_reg_note (insn, REG_UNUSED, operands[3]))
1408 + return \"divu%.l %2,%0\";
1409 + else if (find_reg_note (insn, REG_UNUSED, operands[0]))
1410 + return \"remu%.l %2,%3:%0\";
1412 + return \"remu%.l %2,%3:%0\;divu%.l %2,%0\";
1415 (define_insn "divmodhi4"
1416 [(set (match_operand:HI 0 "general_operand" "=d")
1417 (div:HI (match_operand:HI 1 "general_operand" "0")
1418 (match_operand:HI 2 "general_operand" "dmsK")))
1419 (set (match_operand:HI 3 "general_operand" "=d")
1420 (mod:HI (match_dup 1) (match_dup 2)))]
1422 + "!TARGET_5200 || TARGET_5200_HWDIV"
1426 @@ -3575,7 +3629,7 @@
1427 (match_operand:HI 2 "general_operand" "dmsK")))
1428 (set (match_operand:HI 3 "general_operand" "=d")
1429 (umod:HI (match_dup 1) (match_dup 2)))]
1431 + "!TARGET_5200 || TARGET_5200_HWDIV"
1435 @@ -3591,6 +3645,8 @@
1442 ;; logical-and instructions
1444 @@ -6830,7 +6886,19 @@
1446 return \"bsr.l %0@PLTPC\";
1448 - return \"bsr %0@PLTPC\";
1449 + /* We output a bsr instruction if we've using -fpic or we're building for
1450 + * a target that supports long branches. If we're building -fPIC on the
1451 + * 68000. 68010 or coldfire we're generate one of two sequences
1452 + * a shorter one that uses a GOT entry or a longer one that doesn't.
1453 + * We'll use the -Os commandline flag to decide which to generate.
1454 + * Both sequences take the same time to execute on the coldfire.
1456 + if (flag_pic == 1 || TARGET_68020)
1457 + return \"bsr %0@PLTPC\";
1458 + else if (optimize_size || TARGET_ID_SHARED_LIBRARY)
1459 + return \"move.l %0@GOT(%%a5), %%a1\\n\\tjsr (%%a1)\";
1461 + return \"lea %0-.-8,%%a1\;jsr 0(%%pc,%%a1)\";
1465 @@ -6894,7 +6962,18 @@
1467 return \"bsr.l %1@PLTPC\";
1469 + /* We output a bsr instruction if we've using -fpic or we're building for
1470 + * a target that supports long branches. If we're building -fPIC on the
1471 + * 68000. 68010 or coldfire we're generate one of two sequences
1472 + * a shorter one that uses a GOT entry or a longer one that doesn't.
1473 + * We'll use the -Os commandline flag to decide which to generate.
1475 + if (flag_pic == 1 || TARGET_68020)
1476 return \"bsr %1@PLTPC\";
1477 + else if (optimize_size || TARGET_ID_SHARED_LIBRARY)
1478 + return \"move.l %1@GOT(%%a5), %%a1\\n\\tjsr (%%a1)\";
1480 + return \"lea %1-.-8,%%a1\;jsr 0(%%pc,%%a1)\";
1484 diff -u -r gcc-2.95.3-orig/gcc/config/m68k/m68kelf.h gcc-2.95.3/gcc/config/m68k/m68kelf.h
1485 --- gcc-2.95.3-orig/gcc/config/m68k/m68kelf.h Fri Feb 19 02:00:12 1999
1486 +++ gcc-2.95.3/gcc/config/m68k/m68kelf.h Tue Feb 26 06:52:47 2002
1487 @@ -255,12 +255,17 @@
1488 the PLT entry for `foo'. Doing function cse will cause the address of `foo'
1489 to be loaded into a register, which is exactly what we want to avoid when
1490 we are doing PIC on svr4 m68k. */
1491 +/* We allow function cse if we're optimising for size not on the 68020 or
1492 + * above since all function calls are going via the got anyway so loading the
1493 + * address isn't a problem.
1495 #undef OVERRIDE_OPTIONS
1496 #define OVERRIDE_OPTIONS \
1498 - if (flag_pic) flag_no_function_cse = 1; \
1499 - if (! TARGET_68020 && flag_pic == 2) \
1500 - error("-fPIC is not currently supported on the 68000 or 68010\n"); \
1501 + override_options(); \
1502 + if (flag_pic && (! optimize_size || TARGET_68020) && \
1503 + ! TARGET_ID_SHARED_LIBRARY ) \
1504 + flag_no_function_cse = 1; \
1506 /* end of stuff from m68kv4.h */
1508 diff -u -r gcc-2.95.3-orig/gcc/config/m68k/t-m68kbare gcc-2.95.3/gcc/config/m68k/t-m68kbare
1509 --- gcc-2.95.3-orig/gcc/config/m68k/t-m68kbare Thu Dec 17 07:07:29 1998
1510 +++ gcc-2.95.3/gcc/config/m68k/t-m68kbare Tue Feb 26 06:52:47 2002
1512 echo '#define EXTFLOAT' > xfgnulib.c
1513 cat $(srcdir)/config/m68k/fpgnulib.c >> xfgnulib.c
1515 -MULTILIB_OPTIONS = m68000/m68020/m5200/mcpu32 m68881/msoft-float
1516 +MULTILIB_OPTIONS = m68000/m68020/m5200/mcpu32 m68881/msoft-float/mhwdiv
1518 MULTILIB_MATCHES = m68000=mc68000 m68000=m68302 mcpu32=m68332 m68020=mc68020 m68020=m68040 m68020=m68060
1519 -MULTILIB_EXCEPTIONS = m68000/msoft-float m5200/m68881 m5200/msoft-float mcpu32/m68881 mcpu32/msoft-float
1520 +MULTILIB_EXCEPTIONS = mhwdiv m68000/msoft-float m68000/mhwdiv m68020/mhwdiv m5200/m68881 m5200/msoft-float mcpu32/m68881 mcpu32/msoft-float mcpu32/mhwdiv
1522 LIBGCC = stmp-multilib
1523 INSTALL_LIBGCC = install-multilib
1524 diff -u -r gcc-2.95.3-orig/gcc/config/m68k/t-m68kelf gcc-2.95.3/gcc/config/m68k/t-m68kelf
1525 --- gcc-2.95.3-orig/gcc/config/m68k/t-m68kelf Thu Dec 17 07:07:30 1998
1526 +++ gcc-2.95.3/gcc/config/m68k/t-m68kelf Tue Feb 26 06:52:47 2002
1528 echo '#define EXTFLOAT' > xfgnulib.c
1529 cat $(srcdir)/config/m68k/fpgnulib.c >> xfgnulib.c
1531 -MULTILIB_OPTIONS = m68000/m68020/m5200/mcpu32 m68881/msoft-float
1532 +MULTILIB_OPTIONS = m68000/m68020/m5200/m5307/mcpu32 m68881/msoft-float msep-data/mid-shared-library
1534 MULTILIB_MATCHES = m68000=mc68000 m68000=m68302 mcpu32=m68332 m68020=mc68020 m68020=m68040 m68020=m68060
1535 -MULTILIB_EXCEPTIONS = m68000/msoft-float m5200/m68881 m5200/msoft-float mcpu32/m68881 mcpu32/msoft-float
1536 +MULTILIB_EXCEPTIONS = m68000/msoft-float* m5200/m68881* m5200/msoft-float* mcpu32/m68881* mcpu32/msoft-float* \
1537 + msep-data msoft-float/msep-data m5307/m68881* m5307/msoft-float* \
1538 + mid-shared-library msoft-float/mid-shared-library
1539 +# MULTILIB_EXTRA_OPTS =
1541 LIBGCC = stmp-multilib
1542 INSTALL_LIBGCC = install-multilib
1543 diff -u -r gcc-2.95.3-orig/gcc/invoke.texi gcc-2.95.3/gcc/invoke.texi
1544 --- gcc-2.95.3-orig/gcc/invoke.texi Fri Jan 26 00:03:17 2001
1545 +++ gcc-2.95.3/gcc/invoke.texi Tue Feb 26 06:52:47 2002
1547 -m68000 -m68020 -m68020-40 -m68020-60 -m68030 -m68040
1548 -m68060 -mcpu32 -m5200 -m68881 -mbitfield -mc68000 -mc68020
1549 -mfpa -mnobitfield -mrtd -mshort -msoft-float
1551 +-malign-int -msep-data -mno-sep-data -mmac -mno-mac -mhwdiv -mno-hwdiv
1552 +-mshared-library-id=n -mid-shared-library -mno-id-shared-library
1556 @@ -3226,7 +3227,7 @@
1557 when the compiler is configured for 520X-based systems.
1559 Use this option for microcontroller with a 5200 core, including
1560 -the MCF5202, MCF5203, MCF5204 and MCF5202.
1561 +the MCF5202, MCF5204, MCF5206e and MCF5307.
1565 @@ -3299,6 +3300,44 @@
1566 @strong{Warning:} if you use the @samp{-malign-int} switch, GCC will
1567 align structures containing the above types differently than
1568 most published application binary interface specifications for the m68k.
1572 +Control the generation of output containing divide instructions that
1573 +will only work on ColdFire processors with a hardware divide unit. This
1574 +option is only available when compiling for the ColdFire. The default is
1579 +Control the availability of ColdFire Multiply and ACcumulate instructions.
1580 +This does not affect the code generated only the availablity of the
1581 +instructions to assembler contained within the C. The default is
1584 +@item -mno-sep-data
1585 +Generate code that assumes that the data segment follows the text segment.
1586 +This is the default.
1589 +Generate code that allows the data segment to be located in a different
1590 +area of memory from the text segment. This allows for execute in place in
1591 +an environment without virtual memory management. This option implies -fPIC.
1593 +@item -mid-shared-library
1594 +Generate code that supports shared libraries via the library ID method.
1595 +This allows for execute in place and shared libraries in an environment
1596 +without virtual memory management. This option implies -fPIC.
1598 +@item -mno-id-shared-library
1599 +Generate code that doesn't assume ID based shared libraries are being used.
1600 +This is the default.
1602 +@item -mshared-library-id=n
1603 +Specified the identification number of the ID based shared library being
1604 +compiled. Specifying a value of 0 will generate more compact code, specifying
1605 +other values will force the allocation of that number to the current
1606 +library but is no more space or time efficient than omitting this option.
1610 diff -u -r gcc-2.95.3-orig/gcc/longlong.h gcc-2.95.3/gcc/longlong.h
1611 --- gcc-2.95.3-orig/gcc/longlong.h Thu Jan 7 06:44:39 1999
1612 +++ gcc-2.95.3/gcc/longlong.h Tue Feb 26 06:52:47 2002
1613 @@ -514,8 +514,43 @@
1614 "dmi" ((USItype) (d)))
1616 #else /* not mc68020 */
1617 -#if !defined(__mcf5200__)
1618 /* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */
1619 +#if defined(__mcf5200__)
1620 +#define umul_ppmm(xh, xl, a, b) \
1621 + __asm__ ("| Inlined umul_ppmm
1639 + add%.l %#65536,%/d1
1646 + move%.l %/d0,%0" \
1647 + : "=g" ((USItype) (xh)), \
1648 + "=g" ((USItype) (xl)) \
1649 + : "g" ((USItype) (a)), \
1650 + "g" ((USItype) (b)) \
1651 + : "d0", "d1", "d2", "d3", "d4")
1652 +#define UMUL_TIME 100
1653 +#define UDIV_TIME 400
1654 +#else /* not mcf5200 */
1655 #define umul_ppmm(xh, xl, a, b) \
1656 __asm__ ("| Inlined umul_ppmm
1658 diff -u -r gcc-2.95.3-orig/gcc/version.c gcc-2.95.3/gcc/version.c
1659 --- gcc-2.95.3-orig/gcc/version.c Fri Mar 16 22:52:12 2001
1660 +++ gcc-2.95.3/gcc/version.c Tue Feb 26 06:52:47 2002
1662 -char *version_string = "2.95.3 20010315 (release)";
1663 +char *version_string = "2.95.3 20010315 (release)(ColdFire patches - 20010318 from http://fiddes.net/coldfire/)(uClinux XIP and shared lib patches from http://www.snapgear.com/)";