- rel 4

[packages/crossavr-libc.git] / 999-avr-libc-new-headers.patch

diff -urN avr-libc-1.8.0.orig/include/avr/avr-headers-version.txt avr-libc-1.8.0/include/avr/avr-headers-version.txt
--- avr-libc-1.8.0.orig/include/avr/avr-headers-version.txt	1970-01-01 01:00:00.000000000 +0100
+++ avr-libc-1.8.0/include/avr/avr-headers-version.txt	2013-06-12 12:21:34.000000000 +0200
@@ -0,0 +1 @@
+6.1.3.1475 20130410
diff -urN avr-libc-1.8.0.orig/include/avr/eeprom.h avr-libc-1.8.0/include/avr/eeprom.h
--- avr-libc-1.8.0.orig/include/avr/eeprom.h	2013-06-12 12:22:36.132171065 +0200
+++ avr-libc-1.8.0/include/avr/eeprom.h	2013-06-12 12:21:34.000000000 +0200
@@ -107,14 +107,14 @@
 # define _EEPROM_SUFFIX  _m1284p
 #elif defined (__AVR_ATmega128RFA1__)
 # define _EEPROM_SUFFIX  _m128rfa1
+#elif defined (__AVR_ATmega128RFA2__)
+# define _EEPROM_SUFFIX  _m128rfa2
 #elif defined (__AVR_ATmega128RFR2__)
 # define _EEPROM_SUFFIX  _m128rfr2
-#elif defined (__AVR_ATmega1284RFR2__)
-# define _EEPROM_SUFFIX  _m1284rfr2
+#elif defined (__AVR_ATmega256RFA2__)
+# define _EEPROM_SUFFIX  _m256rfa2
 #elif defined (__AVR_ATmega256RFR2__)
 # define _EEPROM_SUFFIX  _m256rfr2
-#elif defined (__AVR_ATmega2564RFR2__)
-# define _EEPROM_SUFFIX  _m2564rfr2
 #elif defined (__AVR_ATmega2560__)
 # define _EEPROM_SUFFIX  _m2560
 #elif defined (__AVR_ATmega2561__)
@@ -137,10 +137,10 @@
 # define _EEPROM_SUFFIX _usb1286
 #elif defined (__AVR_AT90USB1287__)
 # define _EEPROM_SUFFIX _usb1287
+#elif defined (__AVR_ATmega64RFA2__)
+# define _EEPROM_SUFFIX  _m64rfa2
 #elif defined (__AVR_ATmega64RFR2__)
 # define _EEPROM_SUFFIX  _m64rfr2
-#elif defined (__AVR_ATmega644RFR2__)
-# define _EEPROM_SUFFIX  _m644rfr2
 #elif defined (__AVR_ATmega64__)
 # define _EEPROM_SUFFIX  _m64
 #elif defined (__AVR_ATmega64A__)
@@ -235,8 +235,6 @@
 # define _EEPROM_SUFFIX  _m32hvbrevb
 #elif defined (__AVR_ATmega64HVE__)
 # define _EEPROM_SUFFIX  _m64hve
-#elif defined (__AVR_ATmega64HVE2__)
-# define _EEPROM_SUFFIX  _m64hve2
 #elif defined (__AVR_ATmega406__)
 # define _EEPROM_SUFFIX  _m406
 #elif defined (__AVR_ATmega16__)
@@ -289,6 +287,8 @@
 # define _EEPROM_SUFFIX  _m16hvb
 #elif defined (__AVR_ATmega16HVBREVB__)
 # define _EEPROM_SUFFIX  _m16hvbrevb
+#elif defined (__AVR_ATmega26HVG__)
+# define _EEPROM_SUFFIX  _m26hvg
 #elif defined (__AVR_ATmega8__)
 # define _EEPROM_SUFFIX  _m8
 #elif defined (__AVR_ATmega8A__)
@@ -297,6 +297,8 @@
 # define _EEPROM_SUFFIX  _m48
 #elif defined (__AVR_ATmega48A__)
 # define _EEPROM_SUFFIX  _m48a
+#elif defined (__AVR_ATmega48HVF__)
+# define _EEPROM_SUFFIX  _m48hvf
 #elif defined (__AVR_ATmega48PA__)
 # define _EEPROM_SUFFIX  _m48pa
 #elif defined (__AVR_ATmega48P__)
@@ -381,8 +383,8 @@
 # define _EEPROM_SUFFIX _tn43u
 #elif defined (__AVR_ATtiny48__)
 # define _EEPROM_SUFFIX _tn48
-#elif defined (__AVR_ATtiny828__)
-# define _EEPROM_SUFFIX _tn828
+#elif defined (__AVR_ATtiny80__)
+# define _EEPROM_SUFFIX _tn80
 #elif defined (__AVR_ATtiny88__)
 # define _EEPROM_SUFFIX _tn88
 #elif defined (__AVR_ATtiny87__)
@@ -409,12 +411,8 @@
 # define _EEPROM_SUFFIX   _x32c4
 #elif defined (__AVR_ATxmega32D4__)
 # define _EEPROM_SUFFIX   _x32d4
-#elif defined (__AVR_ATxmega8E5__)
-#define _EEPROM_SUFFIX	  _x8e5
-#elif defined (__AVR_ATxmega16E5__)
-#define _EEPROM_SUFFIX	  _x16e5
-#elif defined (__AVR_ATxmega32E5__)
-# define _EEPROM_SUFFIX   _x32e5
+#elif defined (__AVR_ATxmega32X1__)
+# define _EEPROM_SUFFIX   _x32x1
 #elif defined (__AVR_ATxmega64A1__)
 # define _EEPROM_SUFFIX   _x64a1
 #elif defined (__AVR_ATxmega64A1U__)
@@ -479,24 +477,8 @@
 # define _EEPROM_SUFFIX   _x384c3
 #elif defined (__AVR_ATxmega384D3__)
 # define _EEPROM_SUFFIX   _x384d3
-#elif defined (__AVR_ATA5505__)
-# define _EEPROM_SUFFIX _a5505
-#elif defined (__AVR_ATA5272__)
-# define _EEPROM_SUFFIX _a5272
-#elif defined (__AVR_ATA6285__)
-# define _EEPROM_SUFFIX _a6285
-#elif defined (__AVR_ATA6286__)
-# define _EEPROM_SUFFIX _a6286
 #elif defined (__AVR_ATA6289__)
 # define _EEPROM_SUFFIX _a6289
-#elif defined (__AVR_ATA5790__)
-# define _EEPROM_SUFFIX _a5790
-#elif defined (__AVR_ATA5790N__)
-# define _EEPROM_SUFFIX _a5790n
-#elif defined (__AVR_ATA5795__)
-# define _EEPROM_SUFFIX _a5795
-#elif defined (__AVR_ATA5831__)
-# define _EEPROM_SUFFIX _a5831
 /* avr1: the following only supported for assembler programs */
 #elif defined (__AVR_ATtiny28__)
 # define _EEPROM_SUFFIX _tn28
diff -urN avr-libc-1.8.0.orig/include/avr/io90pwm161.h avr-libc-1.8.0/include/avr/io90pwm161.h
--- avr-libc-1.8.0.orig/include/avr/io90pwm161.h	1970-01-01 01:00:00.000000000 +0100
+++ avr-libc-1.8.0/include/avr/io90pwm161.h	2013-06-12 12:21:34.000000000 +0200
@@ -0,0 +1,866 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2013 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+
+#ifndef _AVR_AT90PWM161_H_INCLUDED
+#define _AVR_AT90PWM161_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "io90pwm161.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define ACSR    _SFR_IO8(0x00)
+#define AC1O    1
+#define AC2O    2
+#define AC3O    3
+#define AC1IF   5
+#define AC2IF   6
+#define AC3IF   7
+
+#define TIMSK1  _SFR_IO8(0x01)
+#define TOIE1   0
+#define ICIE1   5
+
+#define TIFR1   _SFR_IO8(0x02)
+#define TOV1    0
+#define ICF1    5
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDRB7   7
+#define DDRB6   6
+#define DDRB5   5
+#define DDRB4   4
+#define DDRB3   3
+#define DDRB2   2
+#define DDRB1   1
+#define DDRB0   0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define ADCSRA  _SFR_IO8(0x06)
+#define ADPS0   0
+#define ADPS1   1
+#define ADPS2   2
+#define ADIE    3
+#define ADIF    4
+#define ADATE   5
+#define ADSC    6
+#define ADEN    7
+
+#define ADCSRB  _SFR_IO8(0x07)
+#define ADTS0   0
+#define ADTS1   1
+#define ADTS2   2
+#define ADTS3   3
+#define ADSSEN  4
+#define ADNCDIS 6
+#define ADHSM   7
+
+#define ADMUX   _SFR_IO8(0x08)
+#define MUX0    0
+#define MUX1    1
+#define MUX2    2
+#define MUX3    3
+#define ADLAR   5
+#define REFS0   6
+#define REFS1   7
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDRD7   7
+#define DDRD6   6
+#define DDRD5   5
+#define DDRD4   4
+#define DDRD3   3
+#define DDRD2   2
+#define DDRD1   1
+#define DDRD0   0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PORTD7  7
+#define PORTD6  6
+#define PORTD5  5
+#define PORTD4  4
+#define PORTD3  3
+#define PORTD2  2
+#define PORTD1  1
+#define PORTD0  0
+
+#define PINE    _SFR_IO8(0x0C)
+#define PINE7   7
+#define PINE6   6
+#define PINE5   5
+#define PINE4   4
+#define PINE3   3
+#define PINE2   2
+#define PINE1   1
+#define PINE0   0
+
+#define DDRE    _SFR_IO8(0x0D)
+#define DDRE7   7
+#define DDRE6   6
+#define DDRE5   5
+#define DDRE4   4
+#define DDRE3   3
+#define DDRE2   2
+#define DDRE1   1
+#define DDRE0   0
+
+#define PORTE   _SFR_IO8(0x0E)
+#define PORTE7  7
+#define PORTE6  6
+#define PORTE5  5
+#define PORTE4  4
+#define PORTE3  3
+#define PORTE2  2
+#define PORTE1  1
+#define PORTE0  0
+
+#define PIM0    _SFR_IO8(0x0F)
+#define PEOPE0  0
+#define PEOEPE0 1
+#define PEVE0A  3
+#define PEVE0B  4
+
+#define PIFR0   _SFR_IO8(0x10)
+#define PEOP0   0
+#define PRN00   1
+#define PRN01   2
+#define PEV0A   3
+#define PEV0B   4
+#define POAC0A  6
+#define POAC0B  7
+
+#define PCNF0   _SFR_IO8(0x11)
+#define PCLKSEL0 1
+#define POP0    2
+#define PMODE00 3
+#define PMODE01 4
+#define PLOCK0  5
+#define PALOCK0 6
+#define PFIFTY0 7
+
+#define PCTL0   _SFR_IO8(0x12)
+#define PRUN0   0
+#define PCCYC0  1
+#define PAOC0A  3
+#define PAOC0B  4
+#define PBFM00  2
+#define PBFM01  5
+#define PPRE00  6
+#define PPRE01  7
+
+#define PIM2    _SFR_IO8(0x13)
+#define PEOPE2  0
+#define PEOEPE2 1
+#define PEVE2A  3
+#define PEVE2B  4
+#define PSEIE2  5
+
+#define PIFR2   _SFR_IO8(0x14)
+#define PEOP2   0
+#define PRN20   1
+#define PRN21   2
+#define PEV2A   3
+#define PEV2B   4
+#define PSEI2   5
+#define POAC2A  6
+#define POAC2B  7
+
+#define PCNF2   _SFR_IO8(0x15)
+#define POME2   0
+#define PCLKSEL2 1
+#define POP2    2
+#define PMODE20 3
+#define PMODE21 4
+#define PLOCK2  5
+#define PALOCK2 6
+#define PFIFTY2 7
+
+#define PCTL2   _SFR_IO8(0x16)
+#define PRUN2   0
+#define PCCYC2  1
+#define PARUN2  2
+#define PAOC2A  3
+#define PAOC2B  4
+#define PBFM2   5
+#define PPRE20  6
+#define PPRE21  7
+
+#define SPCR    _SFR_IO8(0x17)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x18)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define GPIOR0  _SFR_IO8(0x19)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define GPIOR1  _SFR_IO8(0x1A)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2  _SFR_IO8(0x1B)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define EECR    _SFR_IO8(0x1C)
+#define EERE    0
+#define EEWE    1
+#define EEMWE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+#define EEPAGE  6
+#define NVMBSY  7
+
+#define EEDR    _SFR_IO8(0x1D)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x1E)
+
+#define EEARL   _SFR_IO8(0x1E)
+#define EEARH   _SFR_IO8(0x1F)
+
+#define EIFR    _SFR_IO8(0x20)
+#define INTF0   0
+#define INTF1   1
+#define INTF2   2
+
+#define EIMSK   _SFR_IO8(0x21)
+#define INT0    0
+#define INT1    1
+#define INT2    2
+
+/* Combine OCR0SBL and OCR0SBH */
+#define OCR0SB  _SFR_IO16(0x22)
+
+#define OCR0SBL _SFR_IO8(0x22)
+#define OCR0SBH _SFR_IO8(0x23)
+
+/* Combine OCR0RBL and OCR0RBH */
+#define OCR0RB  _SFR_IO16(0x24)
+
+#define OCR0RBL _SFR_IO8(0x24)
+#define OCR0RBH _SFR_IO8(0x25)
+
+/* Combine OCR2SBL and OCR2SBH */
+#define OCR2SB  _SFR_IO16(0x26)
+
+#define OCR2SBL _SFR_IO8(0x26)
+#define OCR2SBH _SFR_IO8(0x27)
+
+/* Combine OCR2RBL and OCR2RBH */
+#define OCR2RB  _SFR_IO16(0x28)
+
+#define OCR2RBL _SFR_IO8(0x28)
+#define OCR2RBH _SFR_IO8(0x29)
+
+/* Combine OCR0RAL and OCR0RAH */
+#define OCR0RA  _SFR_IO16(0x2A)
+
+#define OCR0RAL _SFR_IO8(0x2A)
+#define OCR0RAH _SFR_IO8(0x2B)
+
+/* Combine ADCL and ADCH */
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_IO16(0x2C)
+#endif
+#define ADCW    _SFR_IO16(0x2C)
+
+#define ADCL    _SFR_IO8(0x2C)
+#define ADCH    _SFR_IO8(0x2D)
+
+/* Combine OCR2RAL and OCR2RAH */
+#define OCR2RA  _SFR_IO16(0x2E)
+
+#define OCR2RAL _SFR_IO8(0x2E)
+#define OCR2RAH _SFR_IO8(0x2F)
+
+/* Reserved [0x30..0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define MCUSR   _SFR_IO8(0x34)
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+
+#define MCUCR   _SFR_IO8(0x35)
+#define IVCE    0
+#define IVSEL   1
+#define CKRC81  2
+#define RSTDIS  3
+#define PUD     4
+
+#define SPDR    _SFR_IO8(0x36)
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define RWWSRE  4
+#define SIGRD   5
+#define RWWSB   6
+#define SPMIE   7
+
+#define DACL    _SFR_IO8(0x38)
+#define DACL0   0
+#define DACL1   1
+#define DACL2   2
+#define DACL3   3
+#define DACL4   4
+#define DACL5   5
+#define DACL6   6
+#define DACL7   7
+
+#define DACH    _SFR_IO8(0x39)
+#define DACH0   0
+#define DACH1   1
+#define DACH2   2
+#define DACH3   3
+#define DACH4   4
+#define DACH5   5
+#define DACH6   6
+#define DACH7   7
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_IO16(0x3A)
+
+#define TCNT1L  _SFR_IO8(0x3A)
+#define TCNT1H  _SFR_IO8(0x3B)
+
+/* Reserved [0x3C] */
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+/* Combine OCR0SAL and OCR0SAH */
+#define OCR0SA  _SFR_MEM16(0x60)
+
+#define OCR0SAL _SFR_MEM8(0x60)
+#define OCR0SAH _SFR_MEM8(0x61)
+
+#define PFRC0A  _SFR_MEM8(0x62)
+#define PRFM0A0 0
+#define PRFM0A1 1
+#define PRFM0A2 2
+#define PRFM0A3 3
+#define PFLTE0A 4
+#define PELEV0A 5
+#define PISEL0A 6
+#define PCAE0A  7
+
+#define PFRC0B  _SFR_MEM8(0x63)
+#define PRFM0B0 0
+#define PRFM0B1 1
+#define PRFM0B2 2
+#define PRFM0B3 3
+#define PFLTE0B 4
+#define PELEV0B 5
+#define PISEL0B 6
+#define PCAE0B  7
+
+/* Combine OCR2SAL and OCR2SAH */
+#define OCR2SA  _SFR_MEM16(0x64)
+
+#define OCR2SAL _SFR_MEM8(0x64)
+#define OCR2SAH _SFR_MEM8(0x65)
+
+#define PFRC2A  _SFR_MEM8(0x66)
+#define PRFM2A0 0
+#define PRFM2A1 1
+#define PRFM2A2 2
+#define PRFM2A3 3
+#define PFLTE2A 4
+#define PELEV2A 5
+#define PISEL2A 6
+#define PCAE2A  7
+
+#define PFRC2B  _SFR_MEM8(0x67)
+#define PRFM2B0 0
+#define PRFM2B1 1
+#define PRFM2B2 2
+#define PRFM2B3 3
+#define PFLTE2B 4
+#define PELEV2B 5
+#define PISEL2B 6
+#define PCAE2B  7
+
+/* Combine PICR0L and PICR0H */
+#define PICR0   _SFR_MEM16(0x68)
+
+#define PICR0L  _SFR_MEM8(0x68)
+#define PICR0H  _SFR_MEM8(0x69)
+
+#define PSOC0   _SFR_MEM8(0x6A)
+#define POEN0A  0
+#define POEN0B  2
+#define PSYNC00 4
+#define PSYNC01 5
+#define PISEL0B1 6
+#define PISEL0A1 7
+
+/* Reserved [0x6B] */
+
+#define PICR2L  _SFR_MEM8(0x6C)
+
+#define PICR2H  _SFR_MEM8(0x6D)
+#define PICR28  0
+#define PICR29  1
+#define PICR210 2
+#define PICR211 3
+#define PCST2   7
+
+#define PSOC2   _SFR_MEM8(0x6E)
+#define POEN2A  0
+#define POEN2C  1
+#define POEN2B  2
+#define POEN2D  3
+#define PSYNC20 4
+#define PSYNC21 5
+#define POS22   6
+#define POS23   7
+
+#define POM2    _SFR_MEM8(0x6F)
+#define POMV2A0 0
+#define POMV2A1 1
+#define POMV2A2 2
+#define POMV2A3 3
+#define POMV2B0 4
+#define POMV2B1 5
+#define POMV2B2 6
+#define POMV2B3 7
+
+#define PCNFE2  _SFR_MEM8(0x70)
+#define PISEL2B1 0
+#define PISEL2A1 1
+#define PELEV2B1 2
+#define PELEV2A1 3
+#define PBFM21  4
+#define PASDLK20 5
+#define PASDLK21 6
+#define PASDLK22 7
+
+#define PASDLY2 _SFR_MEM8(0x71)
+
+/* Reserved [0x72..0x75] */
+
+#define DACON   _SFR_MEM8(0x76)
+#define DAEN    0
+#define DALA    2
+#define DATS0   4
+#define DATS1   5
+#define DATS2   6
+#define DAATE   7
+
+#define DIDR0   _SFR_MEM8(0x77)
+#define ADC0D   0
+#define ADC1D   1
+#define ADC2D   2
+#define ADC3D   3
+#define ADC4D   4
+#define ADC5D   5
+#define ADC6D   6
+#define ADC7D   7
+
+#define DIDR1   _SFR_MEM8(0x78)
+#define ADC9D   0
+#define ADC10D  1
+#define AMP0POSD 2
+#define ACMP1MD 3
+
+#define AMP0CSR _SFR_MEM8(0x79)
+#define AMP0TS0 0
+#define AMP0TS1 1
+#define AMP0GS  3
+#define AMP0G0  4
+#define AMP0G1  5
+#define AMP0IS  6
+#define AMP0EN  7
+
+#define AC1ECON _SFR_MEM8(0x7A)
+#define AC1H0   0
+#define AC1H1   1
+#define AC1H2   2
+#define AC1ICE  3
+#define AC1OE   4
+#define AC1OI   5
+
+#define AC2ECON _SFR_MEM8(0x7B)
+#define AC2H0   0
+#define AC2H1   1
+#define AC2H2   2
+#define AC2OE   4
+#define AC2OI   5
+
+#define AC3ECON _SFR_MEM8(0x7C)
+#define AC3H0   0
+#define AC3H1   1
+#define AC3H2   2
+#define AC3OE   4
+#define AC3OI   5
+
+#define AC1CON  _SFR_MEM8(0x7D)
+#define AC1M0   0
+#define AC1M1   1
+#define AC1M2   2
+#define AC1IS0  4
+#define AC1IS1  5
+#define AC1IE   6
+#define AC1EN   7
+
+#define AC2CON  _SFR_MEM8(0x7E)
+#define AC2M0   0
+#define AC2M1   1
+#define AC2M2   2
+#define AC2IS0  4
+#define AC2IS1  5
+#define AC2IE   6
+#define AC2EN   7
+
+#define AC3CON  _SFR_MEM8(0x7F)
+#define AC3M0   0
+#define AC3M1   1
+#define AC3M2   2
+#define AC3OEA  3
+#define AC3IS0  4
+#define AC3IS1  5
+#define AC3IE   6
+#define AC3EN   7
+
+#define BGCRR   _SFR_MEM8(0x80)
+#define BGCR0   0
+#define BGCR1   1
+#define BGCR2   2
+#define BGCR3   3
+
+#define BGCCR   _SFR_MEM8(0x81)
+#define BGCC0   0
+#define BGCC1   1
+#define BGCC2   2
+#define BGCC3   3
+
+#define WDTCSR  _SFR_MEM8(0x82)
+#define WDE     3
+#define WDCE    4
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDP3    5
+#define WDIE    6
+#define WDIF    7
+
+#define CLKPR   _SFR_MEM8(0x83)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLKPS3  3
+#define CLKPCE  7
+
+#define CLKCSR  _SFR_MEM8(0x84)
+#define CLKC0   0
+#define CLKC1   1
+#define CLKC2   2
+#define CLKC3   3
+#define CLKRDY  4
+#define CLKCCE  7
+
+#define CLKSELR _SFR_MEM8(0x85)
+#define CKSEL0  0
+#define CKSEL1  1
+#define CKSEL2  2
+#define CKSEL3  3
+#define CSUT0   4
+#define CSUT1   5
+#define COUT    6
+
+#define PRR     _SFR_MEM8(0x86)
+#define PRADC   0
+#define PRSPI   2
+#define PRTIM1  4
+#define PRPSCR  5
+#define PRPSC2  7
+
+#define PLLCSR  _SFR_MEM8(0x87)
+#define PLOCK   0
+#define PLLE    1
+#define PLLF0   2
+#define PLLF1   3
+#define PLLF2   4
+#define PLLF3   5
+
+#define OSCCAL  _SFR_MEM8(0x88)
+
+#define EICRA   _SFR_MEM8(0x89)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+#define ISC20   4
+#define ISC21   5
+
+#define TCCR1B  _SFR_MEM8(0x8A)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+#define WGM13   4
+#define ICES1   6
+#define ICNC1   7
+
+/* Reserved [0x8B] */
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x8C)
+
+#define ICR1L   _SFR_MEM8(0x8C)
+#define ICR1H   _SFR_MEM8(0x8D)
+
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* PSC2 Capture Event */
+#define PSC2_CAPT_vect            _VECTOR(1)
+#define PSC2_CAPT_vect_num        1
+
+/* PSC2 End Cycle */
+#define PSC2_EC_vect            _VECTOR(2)
+#define PSC2_EC_vect_num        2
+
+/* PSC2 End Of Enhanced Cycle */
+#define PSC2_EEC_vect            _VECTOR(3)
+#define PSC2_EEC_vect_num        3
+
+/* PSC0 Capture Event */
+#define PSC0_CAPT_vect            _VECTOR(4)
+#define PSC0_CAPT_vect_num        4
+
+/* PSC0 End Cycle */
+#define PSC0_EC_vect            _VECTOR(5)
+#define PSC0_EC_vect_num        5
+
+/* PSC0 End Of Enhanced Cycle */
+#define PSC0_EEC_vect            _VECTOR(6)
+#define PSC0_EEC_vect_num        6
+
+/* Analog Comparator 1 */
+#define ANALOG_COMP_1_vect            _VECTOR(7)
+#define ANALOG_COMP_1_vect_num        7
+
+/* Analog Comparator 2 */
+#define ANALOG_COMP_2_vect            _VECTOR(8)
+#define ANALOG_COMP_2_vect_num        8
+
+/* Analog Comparator 3 */
+#define ANALOG_COMP_3_vect            _VECTOR(9)
+#define ANALOG_COMP_3_vect_num        9
+
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(10)
+#define INT0_vect_num        10
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect            _VECTOR(11)
+#define TIMER1_CAPT_vect_num        11
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect            _VECTOR(12)
+#define TIMER1_OVF_vect_num        12
+
+/* ADC Conversion Complete */
+#define ADC_vect            _VECTOR(13)
+#define ADC_vect_num        13
+
+/* External Interrupt Request 1 */
+#define INT1_vect            _VECTOR(14)
+#define INT1_vect_num        14
+
+/* SPI Serial Transfer Complet */
+#define SPI_STC_vect            _VECTOR(15)
+#define SPI_STC_vect_num        15
+
+/* External Interrupt Request 2 */
+#define INT2_vect            _VECTOR(16)
+#define INT2_vect_num        16
+
+/* Watchdog Timeout Interrupt */
+#define WDT_vect            _VECTOR(17)
+#define WDT_vect_num        17
+
+/* EEPROM Ready */
+#define EE_READY_vect            _VECTOR(18)
+#define EE_READY_vect_num        18
+
+/* Store Program Memory Read */
+#define SPM_READY_vect            _VECTOR(19)
+#define SPM_READY_vect_num        19
+
+#define _VECTORS_SIZE 80
+
+
+/* Constants */
+
+#define SPM_PAGESIZE 128
+#define FLASHSTART   0x0000
+#define FLASHEND     0x3FFF
+#define RAMSTART     0x0100
+#define RAMSIZE      1024
+#define RAMEND       0x04FF
+#define E2START     0
+#define E2SIZE      512
+#define E2PAGESIZE  4
+#define E2END       0x01FF
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
+#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
+#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
+#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
+#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
+#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST     (unsigned char)~_BV(0)
+#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
+#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_DWEN        (unsigned char)~_BV(6)
+#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
+
+/* Extended Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define FUSE_PSCINRB     (unsigned char)~_BV(3)
+#define FUSE_PSCRV       (unsigned char)~_BV(4)
+#define FUSE_PSC0RB      (unsigned char)~_BV(5)
+#define FUSE_PSC2RBA     (unsigned char)~_BV(6)
+#define FUSE_PSC2RB      (unsigned char)~_BV(7)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x94
+#define SIGNATURE_2 0x8B
+
+
+#endif /* #ifdef _AVR_AT90PWM161_H_INCLUDED */
+
diff -urN avr-libc-1.8.0.orig/include/avr/ioa5272.h avr-libc-1.8.0/include/avr/ioa5272.h
--- avr-libc-1.8.0.orig/include/avr/ioa5272.h	1970-01-01 01:00:00.000000000 +0100
+++ avr-libc-1.8.0/include/avr/ioa5272.h	2013-06-12 12:21:34.000000000 +0200
@@ -0,0 +1,737 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2013 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATA5272_H_INCLUDED
+#define _AVR_ATA5272_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "ioa5272.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PINA    _SFR_IO8(0x00)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0x01)
+#define DDRA7   7
+#define DDRA6   6
+#define DDRA5   5
+#define DDRA4   4
+#define DDRA3   3
+#define DDRA2   2
+#define DDRA1   1
+#define DDRA0   0
+
+#define PORTA   _SFR_IO8(0x02)
+#define PORTA7  7
+#define PORTA6  6
+#define PORTA5  5
+#define PORTA4  4
+#define PORTA3  3
+#define PORTA2  2
+#define PORTA1  1
+#define PORTA0  0
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDRB7   7
+#define DDRB6   6
+#define DDRB5   5
+#define DDRB4   4
+#define DDRB3   3
+#define DDRB2   2
+#define DDRB1   1
+#define DDRB0   0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+/* Reserved [0x06..0x11] */
+
+#define PORTCR  _SFR_IO8(0x12)
+
+/* Reserved [0x13..0x14] */
+
+#define TIFR0   _SFR_IO8(0x15)
+#define TOV0    0
+#define OCF0A   1
+
+#define TIFR1   _SFR_IO8(0x16)
+#define TOV1    0
+#define OCF1A   1
+#define OCF1B   2
+#define ICF1    5
+
+/* Reserved [0x17..0x1A] */
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF0   0
+#define PCIF1   1
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF0   0
+#define INTF1   1
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT0    0
+#define INT1    1
+
+#define GPIOR0  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEPE    1
+#define EEMPE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define GTCCR   _SFR_IO8(0x23)
+#define PSR1    0
+#define PSR0    1
+#define TSM     7
+
+/* Reserved [0x24] */
+
+#define TCCR0A  _SFR_IO8(0x25)
+#define WGM00   0
+#define WGM01   1
+#define COM0A0  6
+#define COM0A1  7
+
+#define TCCR0B  _SFR_IO8(0x26)
+#define CS00    0
+#define CS01    1
+#define CS02    2
+#define FOC0A   7
+
+#define TCNT2   _SFR_IO8(0x27)
+
+#define OCR0A   _SFR_IO8(0x28)
+
+/* Reserved [0x29] */
+
+#define GPIOR1  _SFR_IO8(0x2A)
+
+#define GPIOR2  _SFR_IO8(0x2B)
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACIS0   0
+#define ACIS1   1
+#define ACIC    2
+#define ACIE    3
+#define ACI     4
+#define ACO     5
+#define ACIRS   6
+#define ACD     7
+
+#define DWDR    _SFR_IO8(0x31)
+
+/* Reserved [0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+
+#define MCUSR   _SFR_IO8(0x34)
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+
+#define MCUCR   _SFR_IO8(0x35)
+#define PUD     4
+#define BODS    5
+#define BODSE   6
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT   2
+#define RFLB    3
+#define CTPB    4
+#define SIGRD   5
+#define RWWSB   6
+
+/* Reserved [0x38..0x3C] */
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define WDTCR   _SFR_MEM8(0x60)
+#define WDE     3
+#define WDCE    4
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDP3    5
+#define WDIE    6
+#define WDIF    7
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLKPS3  3
+#define CLKPCE  7
+
+#define CLKCSR  _SFR_MEM8(0x62)
+#define CLKC0   0
+#define CLKC1   1
+#define CLKC2   2
+#define CLKC3   3
+#define CLKRDY  4
+#define CLKCCE  7
+
+#define CLKSELR _SFR_MEM8(0x63)
+#define CSEL0   0
+#define CSEL1   1
+#define CSEL2   2
+#define CSEL3   3
+#define CSUT0   4
+#define CSUT1   5
+#define COUT    6
+
+#define PRR     _SFR_MEM8(0x64)
+#define PRADC   0
+#define PRUSI   1
+#define PRTIM0  2
+#define PRTIM1  3
+#define PRSPI   4
+#define PRLIN   5
+
+/* Reserved [0x65] */
+
+#define OSCCAL  _SFR_MEM8(0x66)
+
+/* Reserved [0x67] */
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE0   0
+#define PCIE1   1
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+
+/* Reserved [0x6A] */
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+/* Reserved [0x6D] */
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define TOIE0   0
+#define OCIE0A  1
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define TOIE1   0
+#define OCIE1A  1
+#define OCIE1B  2
+#define ICIE1   5
+
+/* Reserved [0x70..0x76] */
+
+#define AMISCR  _SFR_MEM8(0x77)
+#define XREFEN  1
+#define AREFEN  2
+#define ISRCEN  0
+
+/* Combine ADCL and ADCH */
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_MEM16(0x78)
+#endif
+#define ADCW    _SFR_MEM16(0x78)
+
+#define ADCL    _SFR_MEM8(0x78)
+#define ADCH    _SFR_MEM8(0x79)
+
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADPS0   0
+#define ADPS1   1
+#define ADPS2   2
+#define ADIE    3
+#define ADIF    4
+#define ADATE   5
+#define ADSC    6
+#define ADEN    7
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ADTS0   0
+#define ADTS1   1
+#define ADTS2   2
+#define BIN     7
+#define ACIR0   4
+#define ACIR1   5
+#define ACME    6
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define MUX0    0
+#define MUX1    1
+#define MUX2    2
+#define MUX3    3
+#define MUX4    4
+#define ADLAR   5
+#define REFS0   6
+#define REFS1   7
+
+/* Reserved [0x7D] */
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC0D   0
+#define ADC1D   1
+#define ADC2D   2
+#define ADC3D   3
+#define ADC4D   4
+#define ADC5D   5
+#define ADC6D   6
+#define ADC7D   7
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define ADC8D   0
+#define ADC9D   1
+#define ADC10D  2
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define WGM10   0
+#define WGM11   1
+#define COM1B0  4
+#define COM1B1  5
+#define COM1A0  6
+#define COM1A1  7
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+#define WGM12   3
+#define WGM13   4
+#define ICES1   6
+#define ICNC1   7
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1B   6
+#define FOC1A   7
+
+#define TCCR1D  _SFR_MEM8(0x83)
+#define OC1AU   0
+#define OC1AV   1
+#define OC1AW   2
+#define OC1AX   3
+#define OC1BU   4
+#define OC1BV   5
+#define OC1BW   6
+#define OC1BX   7
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Reserved [0x8C..0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define TCR0BUB 0
+#define TCR0AUB 1
+#define OCR0AUB 3
+#define TCN0UB  4
+#define AS0     5
+#define EXCLK   6
+
+/* Reserved [0xB7] */
+
+#define USICR   _SFR_MEM8(0xB8)
+#define USITC   0
+#define USICLK  1
+#define USICS0  2
+#define USICS1  3
+#define USIWM0  4
+#define USIWM1  5
+#define USIOIE  6
+#define USISIE  7
+
+#define USISR   _SFR_MEM8(0xB9)
+#define USICNT0 0
+#define USICNT1 1
+#define USICNT2 2
+#define USICNT3 3
+#define USIDC   4
+#define USIPF   5
+#define USIOIF  6
+#define USISIF  7
+
+#define USIDR   _SFR_MEM8(0xBA)
+
+#define USIBR   _SFR_MEM8(0xBB)
+
+#define USIPP   _SFR_MEM8(0xBC)
+
+/* Reserved [0xBD..0xC7] */
+
+#define LINCR   _SFR_MEM8(0xC8)
+#define LCMD0   0
+#define LCMD1   1
+#define LCMD2   2
+#define LENA    3
+#define LCONF0  4
+#define LCONF1  5
+#define LIN13   6
+#define LSWRES  7
+
+#define LINSIR  _SFR_MEM8(0xC9)
+#define LRXOK   0
+#define LTXOK   1
+#define LIDOK   2
+#define LERR    3
+#define LBUSY   4
+#define LIDST0  5
+#define LIDST1  6
+#define LIDST2  7
+
+#define LINENIR _SFR_MEM8(0xCA)
+#define LENRXOK 0
+#define LENTXOK 1
+#define LENIDOK 2
+#define LENERR  3
+
+#define LINERR  _SFR_MEM8(0xCB)
+#define LBERR   0
+#define LCERR   1
+#define LPERR   2
+#define LSERR   3
+#define LFERR   4
+#define LOVERR  5
+#define LTOERR  6
+#define LABORT  7
+
+#define LINBTR  _SFR_MEM8(0xCC)
+#define LBT0    0
+#define LBT1    1
+#define LBT2    2
+#define LBT3    3
+#define LBT4    4
+#define LBT5    5
+#define LDISR   7
+
+#define LINBRRL _SFR_MEM8(0xCD)
+#define LDIV0   0
+#define LDIV1   1
+#define LDIV2   2
+#define LDIV3   3
+#define LDIV4   4
+#define LDIV5   5
+#define LDIV6   6
+#define LDIV7   7
+
+#define LINBRRH _SFR_MEM8(0xCE)
+#define LDIV8   0
+#define LDIV9   1
+#define LDIV10  2
+#define LDIV11  3
+
+#define LINDLR  _SFR_MEM8(0xCF)
+#define LRXDL0  0
+#define LRXDL1  1
+#define LRXDL2  2
+#define LRXDL3  3
+#define LTXDL0  4
+#define LTXDL1  5
+#define LTXDL2  6
+#define LTXDL3  7
+
+#define LINIDR  _SFR_MEM8(0xD0)
+#define LID0    0
+#define LID1    1
+#define LID2    2
+#define LID3    3
+#define LID4    4
+#define LID5    5
+#define LP0     6
+#define LP1     7
+
+#define LINSEL  _SFR_MEM8(0xD1)
+#define LINDX0  0
+#define LINDX1  1
+#define LINDX2  2
+#define LAINC   3
+
+#define LINDAT  _SFR_MEM8(0xD2)
+#define LDATA0  0
+#define LDATA1  1
+#define LDATA2  2
+#define LDATA3  3
+#define LDATA4  4
+#define LDATA5  5
+#define LDATA6  6
+#define LDATA7  7
+
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
+
+/* External Interrupt Request 1 */
+#define INT1_vect            _VECTOR(2)
+#define INT1_vect_num        2
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect            _VECTOR(3)
+#define PCINT0_vect_num        3
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect            _VECTOR(4)
+#define PCINT1_vect_num        4
+
+/* Watchdog Time-Out Interrupt */
+#define WDT_vect            _VECTOR(5)
+#define WDT_vect_num        5
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect            _VECTOR(6)
+#define TIMER1_CAPT_vect_num        6
+
+/* Timer/Counter1 Compare Match 1A */
+#define TIMER1_COMPA_vect            _VECTOR(7)
+#define TIMER1_COMPA_vect_num        7
+
+/* Timer/Counter1 Compare Match 1B */
+#define TIMER1_COMPB_vect            _VECTOR(8)
+#define TIMER1_COMPB_vect_num        8
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect            _VECTOR(9)
+#define TIMER1_OVF_vect_num        9
+
+/* Timer/Counter0 Compare Match 0A */
+#define TIMER0_COMPA_vect            _VECTOR(10)
+#define TIMER0_COMPA_vect_num        10
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect            _VECTOR(11)
+#define TIMER0_OVF_vect_num        11
+
+/* LIN Transfer Complete */
+#define LIN_TC_vect            _VECTOR(12)
+#define LIN_TC_vect_num        12
+
+/* LIN Error */
+#define LIN_ERR_vect            _VECTOR(13)
+#define LIN_ERR_vect_num        13
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect            _VECTOR(14)
+#define SPI_STC_vect_num        14
+
+/* ADC Conversion Complete */
+#define ADC_vect            _VECTOR(15)
+#define ADC_vect_num        15
+
+/* EEPROM Ready */
+#define EE_RDY_vect            _VECTOR(16)
+#define EE_RDY_vect_num        16
+
+/* Analog Comparator */
+#define ANA_COMP_vect            _VECTOR(34)
+#define ANA_COMP_vect_num        34
+
+/* USI Start */
+#define USI_START_vect            _VECTOR(36)
+#define USI_START_vect_num        36
+
+/* USI Overflow */
+#define USI_OVF_vect            _VECTOR(19)
+#define USI_OVF_vect_num        19
+
+#define _VECTORS_SIZE 40
+
+
+/* Constants */
+
+#define SPM_PAGESIZE 128
+#define FLASHSTART   0x0000
+#define FLASHEND     0x1FFF
+#define RAMSTART     0x0100
+#define RAMSIZE      512
+#define RAMEND       0x02FF
+#define E2START     0
+#define E2SIZE      512
+#define E2PAGESIZE  4
+#define E2END       0x01FF
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
+#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
+#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
+#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
+#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
+#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+
+/* High Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_DWEN        (unsigned char)~_BV(6)
+#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
+
+/* Extended Fuse Byte */
+#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x93
+#define SIGNATURE_2 0x87
+
+
+#endif /* #ifdef _AVR_ATA5272_H_INCLUDED */
+
diff -urN avr-libc-1.8.0.orig/include/avr/ioa5505.h avr-libc-1.8.0/include/avr/ioa5505.h
--- avr-libc-1.8.0.orig/include/avr/ioa5505.h	1970-01-01 01:00:00.000000000 +0100
+++ avr-libc-1.8.0/include/avr/ioa5505.h	2013-06-12 12:21:34.000000000 +0200
@@ -0,0 +1,737 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2013 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATA5505_H_INCLUDED
+#define _AVR_ATA5505_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "ioa5505.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PINA    _SFR_IO8(0x00)
+#define PINA7   7
+#define PINA6   6
+#define PINA5   5
+#define PINA4   4
+#define PINA3   3
+#define PINA2   2
+#define PINA1   1
+#define PINA0   0
+
+#define DDRA    _SFR_IO8(0x01)
+#define DDRA7   7
+#define DDRA6   6
+#define DDRA5   5
+#define DDRA4   4
+#define DDRA3   3
+#define DDRA2   2
+#define DDRA1   1
+#define DDRA0   0
+
+#define PORTA   _SFR_IO8(0x02)
+#define PORTA7  7
+#define PORTA6  6
+#define PORTA5  5
+#define PORTA4  4
+#define PORTA3  3
+#define PORTA2  2
+#define PORTA1  1
+#define PORTA0  0
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDRB7   7
+#define DDRB6   6
+#define DDRB5   5
+#define DDRB4   4
+#define DDRB3   3
+#define DDRB2   2
+#define DDRB1   1
+#define DDRB0   0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+/* Reserved [0x06..0x11] */
+
+#define PORTCR  _SFR_IO8(0x12)
+
+/* Reserved [0x13..0x14] */
+
+#define TIFR0   _SFR_IO8(0x15)
+#define TOV0    0
+#define OCF0A   1
+
+#define TIFR1   _SFR_IO8(0x16)
+#define TOV1    0
+#define OCF1A   1
+#define OCF1B   2
+#define ICF1    5
+
+/* Reserved [0x17..0x1A] */
+
+#define PCIFR   _SFR_IO8(0x1B)
+#define PCIF0   0
+#define PCIF1   1
+
+#define EIFR    _SFR_IO8(0x1C)
+#define INTF0   0
+#define INTF1   1
+
+#define EIMSK   _SFR_IO8(0x1D)
+#define INT0    0
+#define INT1    1
+
+#define GPIOR0  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEPE    1
+#define EEMPE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define GTCCR   _SFR_IO8(0x23)
+#define PSR1    0
+#define PSR0    1
+#define TSM     7
+
+/* Reserved [0x24] */
+
+#define TCCR0A  _SFR_IO8(0x25)
+#define WGM00   0
+#define WGM01   1
+#define COM0A0  6
+#define COM0A1  7
+
+#define TCCR0B  _SFR_IO8(0x26)
+#define CS00    0
+#define CS01    1
+#define CS02    2
+#define FOC0A   7
+
+#define TCNT2   _SFR_IO8(0x27)
+
+#define OCR0A   _SFR_IO8(0x28)
+
+/* Reserved [0x29] */
+
+#define GPIOR1  _SFR_IO8(0x2A)
+
+#define GPIOR2  _SFR_IO8(0x2B)
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+/* Reserved [0x2F] */
+
+#define ACSR    _SFR_IO8(0x30)
+#define ACIS0   0
+#define ACIS1   1
+#define ACIC    2
+#define ACIE    3
+#define ACI     4
+#define ACO     5
+#define ACIRS   6
+#define ACD     7
+
+#define DWDR    _SFR_IO8(0x31)
+
+/* Reserved [0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+
+#define MCUSR   _SFR_IO8(0x34)
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+
+#define MCUCR   _SFR_IO8(0x35)
+#define PUD     4
+#define BODS    5
+#define BODSE   6
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT   2
+#define RFLB    3
+#define CTPB    4
+#define SIGRD   5
+#define RWWSB   6
+
+/* Reserved [0x38..0x3C] */
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define WDTCR   _SFR_MEM8(0x60)
+#define WDE     3
+#define WDCE    4
+#define WDP0    0
+#define WDP1    1
+#define WDP2    2
+#define WDP3    5
+#define WDIE    6
+#define WDIF    7
+
+#define CLKPR   _SFR_MEM8(0x61)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLKPS3  3
+#define CLKPCE  7
+
+#define CLKCSR  _SFR_MEM8(0x62)
+#define CLKC0   0
+#define CLKC1   1
+#define CLKC2   2
+#define CLKC3   3
+#define CLKRDY  4
+#define CLKCCE  7
+
+#define CLKSELR _SFR_MEM8(0x63)
+#define CSEL0   0
+#define CSEL1   1
+#define CSEL2   2
+#define CSEL3   3
+#define CSUT0   4
+#define CSUT1   5
+#define COUT    6
+
+#define PRR     _SFR_MEM8(0x64)
+#define PRADC   0
+#define PRUSI   1
+#define PRTIM0  2
+#define PRTIM1  3
+#define PRSPI   4
+#define PRLIN   5
+
+/* Reserved [0x65] */
+
+#define OSCCAL  _SFR_MEM8(0x66)
+
+/* Reserved [0x67] */
+
+#define PCICR   _SFR_MEM8(0x68)
+#define PCIE0   0
+#define PCIE1   1
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+
+/* Reserved [0x6A] */
+
+#define PCMSK0  _SFR_MEM8(0x6B)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6C)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+/* Reserved [0x6D] */
+
+#define TIMSK0  _SFR_MEM8(0x6E)
+#define TOIE0   0
+#define OCIE0A  1
+
+#define TIMSK1  _SFR_MEM8(0x6F)
+#define TOIE1   0
+#define OCIE1A  1
+#define OCIE1B  2
+#define ICIE1   5
+
+/* Reserved [0x70..0x76] */
+
+#define AMISCR  _SFR_MEM8(0x77)
+#define XREFEN  1
+#define AREFEN  2
+#define ISRCEN  0
+
+/* Combine ADCL and ADCH */
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_MEM16(0x78)
+#endif
+#define ADCW    _SFR_MEM16(0x78)
+
+#define ADCL    _SFR_MEM8(0x78)
+#define ADCH    _SFR_MEM8(0x79)
+
+#define ADCSRA  _SFR_MEM8(0x7A)
+#define ADPS0   0
+#define ADPS1   1
+#define ADPS2   2
+#define ADIE    3
+#define ADIF    4
+#define ADATE   5
+#define ADSC    6
+#define ADEN    7
+
+#define ADCSRB  _SFR_MEM8(0x7B)
+#define ADTS0   0
+#define ADTS1   1
+#define ADTS2   2
+#define BIN     7
+#define ACIR0   4
+#define ACIR1   5
+#define ACME    6
+
+#define ADMUX   _SFR_MEM8(0x7C)
+#define MUX0    0
+#define MUX1    1
+#define MUX2    2
+#define MUX3    3
+#define MUX4    4
+#define ADLAR   5
+#define REFS0   6
+#define REFS1   7
+
+/* Reserved [0x7D] */
+
+#define DIDR0   _SFR_MEM8(0x7E)
+#define ADC0D   0
+#define ADC1D   1
+#define ADC2D   2
+#define ADC3D   3
+#define ADC4D   4
+#define ADC5D   5
+#define ADC6D   6
+#define ADC7D   7
+
+#define DIDR1   _SFR_MEM8(0x7F)
+#define ADC8D   0
+#define ADC9D   1
+#define ADC10D  2
+
+#define TCCR1A  _SFR_MEM8(0x80)
+#define WGM10   0
+#define WGM11   1
+#define COM1B0  4
+#define COM1B1  5
+#define COM1A0  6
+#define COM1A1  7
+
+#define TCCR1B  _SFR_MEM8(0x81)
+#define CS10    0
+#define CS11    1
+#define CS12    2
+#define WGM12   3
+#define WGM13   4
+#define ICES1   6
+#define ICNC1   7
+
+#define TCCR1C  _SFR_MEM8(0x82)
+#define FOC1B   6
+#define FOC1A   7
+
+#define TCCR1D  _SFR_MEM8(0x83)
+#define OC1AU   0
+#define OC1AV   1
+#define OC1AW   2
+#define OC1AX   3
+#define OC1BU   4
+#define OC1BV   5
+#define OC1BW   6
+#define OC1BX   7
+
+/* Combine TCNT1L and TCNT1H */
+#define TCNT1   _SFR_MEM16(0x84)
+
+#define TCNT1L  _SFR_MEM8(0x84)
+#define TCNT1H  _SFR_MEM8(0x85)
+
+/* Combine ICR1L and ICR1H */
+#define ICR1    _SFR_MEM16(0x86)
+
+#define ICR1L   _SFR_MEM8(0x86)
+#define ICR1H   _SFR_MEM8(0x87)
+
+/* Combine OCR1AL and OCR1AH */
+#define OCR1A   _SFR_MEM16(0x88)
+
+#define OCR1AL  _SFR_MEM8(0x88)
+#define OCR1AH  _SFR_MEM8(0x89)
+
+/* Combine OCR1BL and OCR1BH */
+#define OCR1B   _SFR_MEM16(0x8A)
+
+#define OCR1BL  _SFR_MEM8(0x8A)
+#define OCR1BH  _SFR_MEM8(0x8B)
+
+/* Reserved [0x8C..0xB5] */
+
+#define ASSR    _SFR_MEM8(0xB6)
+#define TCR0BUB 0
+#define TCR0AUB 1
+#define OCR0AUB 3
+#define TCN0UB  4
+#define AS0     5
+#define EXCLK   6
+
+/* Reserved [0xB7] */
+
+#define USICR   _SFR_MEM8(0xB8)
+#define USITC   0
+#define USICLK  1
+#define USICS0  2
+#define USICS1  3
+#define USIWM0  4
+#define USIWM1  5
+#define USIOIE  6
+#define USISIE  7
+
+#define USISR   _SFR_MEM8(0xB9)
+#define USICNT0 0
+#define USICNT1 1
+#define USICNT2 2
+#define USICNT3 3
+#define USIDC   4
+#define USIPF   5
+#define USIOIF  6
+#define USISIF  7
+
+#define USIDR   _SFR_MEM8(0xBA)
+
+#define USIBR   _SFR_MEM8(0xBB)
+
+#define USIPP   _SFR_MEM8(0xBC)
+
+/* Reserved [0xBD..0xC7] */
+
+#define LINCR   _SFR_MEM8(0xC8)
+#define LCMD0   0
+#define LCMD1   1
+#define LCMD2   2
+#define LENA    3
+#define LCONF0  4
+#define LCONF1  5
+#define LIN13   6
+#define LSWRES  7
+
+#define LINSIR  _SFR_MEM8(0xC9)
+#define LRXOK   0
+#define LTXOK   1
+#define LIDOK   2
+#define LERR    3
+#define LBUSY   4
+#define LIDST0  5
+#define LIDST1  6
+#define LIDST2  7
+
+#define LINENIR _SFR_MEM8(0xCA)
+#define LENRXOK 0
+#define LENTXOK 1
+#define LENIDOK 2
+#define LENERR  3
+
+#define LINERR  _SFR_MEM8(0xCB)
+#define LBERR   0
+#define LCERR   1
+#define LPERR   2
+#define LSERR   3
+#define LFERR   4
+#define LOVERR  5
+#define LTOERR  6
+#define LABORT  7
+
+#define LINBTR  _SFR_MEM8(0xCC)
+#define LBT0    0
+#define LBT1    1
+#define LBT2    2
+#define LBT3    3
+#define LBT4    4
+#define LBT5    5
+#define LDISR   7
+
+#define LINBRRL _SFR_MEM8(0xCD)
+#define LDIV0   0
+#define LDIV1   1
+#define LDIV2   2
+#define LDIV3   3
+#define LDIV4   4
+#define LDIV5   5
+#define LDIV6   6
+#define LDIV7   7
+
+#define LINBRRH _SFR_MEM8(0xCE)
+#define LDIV8   0
+#define LDIV9   1
+#define LDIV10  2
+#define LDIV11  3
+
+#define LINDLR  _SFR_MEM8(0xCF)
+#define LRXDL0  0
+#define LRXDL1  1
+#define LRXDL2  2
+#define LRXDL3  3
+#define LTXDL0  4
+#define LTXDL1  5
+#define LTXDL2  6
+#define LTXDL3  7
+
+#define LINIDR  _SFR_MEM8(0xD0)
+#define LID0    0
+#define LID1    1
+#define LID2    2
+#define LID3    3
+#define LID4    4
+#define LID5    5
+#define LP0     6
+#define LP1     7
+
+#define LINSEL  _SFR_MEM8(0xD1)
+#define LINDX0  0
+#define LINDX1  1
+#define LINDX2  2
+#define LAINC   3
+
+#define LINDAT  _SFR_MEM8(0xD2)
+#define LDATA0  0
+#define LDATA1  1
+#define LDATA2  2
+#define LDATA3  3
+#define LDATA4  4
+#define LDATA5  5
+#define LDATA6  6
+#define LDATA7  7
+
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
+
+/* External Interrupt Request 1 */
+#define INT1_vect            _VECTOR(2)
+#define INT1_vect_num        2
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect            _VECTOR(3)
+#define PCINT0_vect_num        3
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect            _VECTOR(4)
+#define PCINT1_vect_num        4
+
+/* Watchdog Time-Out Interrupt */
+#define WDT_vect            _VECTOR(5)
+#define WDT_vect_num        5
+
+/* Timer/Counter1 Capture Event */
+#define TIMER1_CAPT_vect            _VECTOR(6)
+#define TIMER1_CAPT_vect_num        6
+
+/* Timer/Counter1 Compare Match 1A */
+#define TIMER1_COMPA_vect            _VECTOR(7)
+#define TIMER1_COMPA_vect_num        7
+
+/* Timer/Counter1 Compare Match 1B */
+#define TIMER1_COMPB_vect            _VECTOR(8)
+#define TIMER1_COMPB_vect_num        8
+
+/* Timer/Counter1 Overflow */
+#define TIMER1_OVF_vect            _VECTOR(9)
+#define TIMER1_OVF_vect_num        9
+
+/* Timer/Counter0 Compare Match 0A */
+#define TIMER0_COMPA_vect            _VECTOR(10)
+#define TIMER0_COMPA_vect_num        10
+
+/* Timer/Counter0 Overflow */
+#define TIMER0_OVF_vect            _VECTOR(11)
+#define TIMER0_OVF_vect_num        11
+
+/* LIN Transfer Complete */
+#define LIN_TC_vect            _VECTOR(12)
+#define LIN_TC_vect_num        12
+
+/* LIN Error */
+#define LIN_ERR_vect            _VECTOR(13)
+#define LIN_ERR_vect_num        13
+
+/* SPI Serial Transfer Complete */
+#define SPI_STC_vect            _VECTOR(14)
+#define SPI_STC_vect_num        14
+
+/* ADC Conversion Complete */
+#define ADC_vect            _VECTOR(15)
+#define ADC_vect_num        15
+
+/* EEPROM Ready */
+#define EE_RDY_vect            _VECTOR(16)
+#define EE_RDY_vect_num        16
+
+/* Analog Comparator */
+#define ANA_COMP_vect            _VECTOR(17)
+#define ANA_COMP_vect_num        17
+
+/* USI Start */
+#define USI_START_vect            _VECTOR(18)
+#define USI_START_vect_num        18
+
+/* USI Overflow */
+#define USI_OVF_vect            _VECTOR(19)
+#define USI_OVF_vect_num        19
+
+#define _VECTORS_SIZE 80
+
+
+/* Constants */
+
+#define SPM_PAGESIZE 128
+#define FLASHSTART   0x0000
+#define FLASHEND     0x3FFF
+#define RAMSTART     0x0100
+#define RAMSIZE      512
+#define RAMEND       0x02FF
+#define E2START     0
+#define E2SIZE      512
+#define E2PAGESIZE  4
+#define E2END       0x01FF
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(0)
+#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(1)
+#define FUSE_SUT_CKSEL2  (unsigned char)~_BV(2)
+#define FUSE_SUT_CKSEL3  (unsigned char)~_BV(3)
+#define FUSE_SUT_CKSEL4  (unsigned char)~_BV(4)
+#define FUSE_SUT_CKSEL5  (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+
+/* High Fuse Byte */
+#define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
+#define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
+#define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_DWEN        (unsigned char)~_BV(6)
+#define FUSE_RSTDISBL    (unsigned char)~_BV(7)
+
+/* Extended Fuse Byte */
+#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x94
+#define SIGNATURE_2 0x87
+
+
+#endif /* #ifdef _AVR_ATA5505_H_INCLUDED */
+
diff -urN avr-libc-1.8.0.orig/include/avr/ioa5790.h avr-libc-1.8.0/include/avr/ioa5790.h
--- avr-libc-1.8.0.orig/include/avr/ioa5790.h	1970-01-01 01:00:00.000000000 +0100
+++ avr-libc-1.8.0/include/avr/ioa5790.h	2013-06-12 12:21:34.000000000 +0200
@@ -0,0 +1,834 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2013 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATA5790_H_INCLUDED
+#define _AVR_ATA5790_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "ioa5790.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDRB7   7
+#define DDRB6   6
+#define DDRB5   5
+#define DDRB4   4
+#define DDRB3   3
+#define DDRB2   2
+#define DDRB1   1
+#define DDRB0   0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDRC7   7
+#define DDRC6   6
+#define DDRC5   5
+#define DDRC4   4
+#define DDRC3   3
+#define DDRC2   2
+#define DDRC1   1
+#define DDRC0   0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PORTC7  7
+#define PORTC6  6
+#define PORTC5  5
+#define PORTC4  4
+#define PORTC3  3
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDRD7   7
+#define DDRD6   6
+#define DDRD5   5
+#define DDRD4   4
+#define DDRD3   3
+#define DDRD2   2
+#define DDRD1   1
+#define DDRD0   0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PORTD7  7
+#define PORTD6  6
+#define PORTD5  5
+#define PORTD4  4
+#define PORTD3  3
+#define PORTD2  2
+#define PORTD1  1
+#define PORTD0  0
+
+/* Reserved [0x0C] */
+
+#define TPCR    _SFR_IO8(0x0D)
+#define TPMA    0
+#define TPMOD   1
+#define TPMS0   2
+#define TPMS1   3
+#define TPMD0   4
+#define TPMD1   5
+#define TPPSD   6
+#define TPD     7
+
+#define TPFR    _SFR_IO8(0x0E)
+#define TPF     0
+#define TPA     1
+#define TPGAP   2
+#define TPPSW   3
+
+#define CMCR    _SFR_IO8(0x0F)
+#define CMM0    0
+#define CMM1    1
+#define SRCD    2
+#define CO32D   3
+#define CCS     4
+#define ECINS   5
+#define CMONEN  6
+#define CMCCE   7
+
+#define CMSR    _SFR_IO8(0x10)
+#define ECF     0
+#define SXF     1
+#define RTCF    2
+
+#define T2CR    _SFR_IO8(0x11)
+#define T2OTM   0
+#define T2CTM   1
+#define T2CRM   2
+#define T2GRM   3
+#define T2TOP   4
+#define T2RES   5
+#define T2TS    6
+#define T2E     7
+
+#define T3CR    _SFR_IO8(0x12)
+#define T3OTM   0
+#define T3CTM   1
+#define T3CRM   2
+#define T3CPRM  3
+#define T3TOP   4
+#define T3RES   5
+#define T3CPTM  6
+#define T3E     7
+
+#define AESCR   _SFR_IO8(0x13)
+#define AESWK   0
+#define AESWD   1
+#define AESIM   2
+#define AESD    3
+#define AESXOR  4
+#define AESRES  5
+#define AESE    7
+
+#define AESSR   _SFR_IO8(0x14)
+#define AESRF   0
+#define AESERF  7
+
+#define TMIFR   _SFR_IO8(0x15)
+#define TMRXF   0
+#define TMTXF   1
+#define TMTCF   2
+#define TMRXS   3
+#define TMTXS   4
+
+#define VMSR    _SFR_IO8(0x16)
+#define VMF     0
+
+#define PCIFR   _SFR_IO8(0x17)
+#define PCIF0   0
+#define PCIF1   1
+
+#define LFFR    _SFR_IO8(0x18)
+#define LFID0F  0
+#define LFID1F  1
+#define LFFEF   2
+#define LFDBF   3
+#define LFRSF   4
+#define LFSDF   5
+#define LFMDF   6
+#define LFCAF   7
+
+#define T0IFR   _SFR_IO8(0x19)
+#define T0F     0
+
+#define T1IFR   _SFR_IO8(0x1A)
+#define T1F     0
+
+#define T2IFR   _SFR_IO8(0x1B)
+#define T2OFF   0
+#define T2COF   1
+
+#define T3IFR   _SFR_IO8(0x1C)
+#define T3OFF   0
+#define T3COF   1
+#define T3ICF   2
+
+#define EIFR    _SFR_IO8(0x1D)
+#define INTF0   0
+
+#define GPIOR   _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEWE    1
+#define EEMWE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+#define EELP    6
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define EEPR    _SFR_IO8(0x23)
+#define EEAP0   0
+#define EEAP1   1
+#define EEAP2   2
+#define EEAP3   3
+
+#define EECCR   _SFR_IO8(0x24)
+#define EEL0    0
+#define EEL1    1
+#define EEL2    2
+#define EEL3    3
+
+/* Reserved [0x25] */
+
+#define PCICR   _SFR_IO8(0x26)
+#define PCIE0   0
+#define PCIE1   1
+
+#define EIMSK   _SFR_IO8(0x27)
+#define INT0    0
+
+#define TMDR    _SFR_IO8(0x28)
+
+#define AESDR   _SFR_IO8(0x29)
+
+#define AESKR   _SFR_IO8(0x2A)
+#define AESKR0  0
+#define AESKR1  1
+#define AESKR2  2
+#define AESKR3  3
+#define AESKR4  4
+#define AESKR5  5
+#define AESKR6  6
+#define AESKR7  7
+
+#define VMCR    _SFR_IO8(0x2B)
+#define VMLS0   0
+#define VMLS1   1
+#define VMLS2   2
+#define VMLS3   3
+#define VMIM    4
+#define VMPS    5
+#define BODPD   6
+#define BODLS   7
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+#define LFCR0   _SFR_IO8(0x2F)
+#define LFCE1   0
+#define LFCE2   1
+#define LFCE3   2
+#define LFBRS   3
+#define LFRBS   4
+#define LFMG    5
+#define LFVC0   6
+#define LFVC1   7
+
+#define LFCR1   _SFR_IO8(0x30)
+#define LFM0    0
+#define LFM1    1
+#define LFFM0   2
+#define LFFM1   3
+#define LFRMS   4
+#define LFRMSA  5
+#define LFQCE   6
+#define LFRE    7
+
+/* Reserved [0x31] */
+
+#define LFRDB   _SFR_IO8(0x32)
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define MCUSR   _SFR_IO8(0x34)
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+#define TPRF    5
+
+#define MCUCR   _SFR_IO8(0x35)
+#define IVCE    0
+#define IVSEL   1
+#define PUD     4
+
+#define LFSR    _SFR_IO8(0x36)
+#define LFES    0
+#define LFSD    1
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define RWWSRE  4
+#define SIGRD   5
+#define RWWSB   6
+#define SPMIE   7
+
+#define T1CR    _SFR_IO8(0x38)
+#define T1PS0   0
+#define T1PS1   1
+#define T1IE    2
+#define T1CS0   3
+#define T1CS1   4
+#define T1E     7
+
+#define T0CR    _SFR_IO8(0x39)
+#define T0PS0   0
+#define T0PS1   1
+#define T0PS2   2
+#define T0IE    3
+#define T0PR    4
+
+/* Reserved [0x3A] */
+
+#define CMIMR   _SFR_IO8(0x3B)
+#define ECIE    0
+#define SXIE    1
+#define RTCIE   2
+
+#define CLKPR   _SFR_IO8(0x3C)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLTPS0  3
+#define CLTPS1  4
+#define CLTPS2  5
+#define CLKPCE  7
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define WDTCR   _SFR_MEM8(0x60)
+#define WDPS0   0
+#define WDPS1   1
+#define WDPS2   2
+#define WDE     3
+#define WDCE    4
+
+/* Reserved [0x61..0x62] */
+
+#define PRR0    _SFR_MEM8(0x63)
+#define PRLFR   0
+#define PRT1    1
+#define PRT2    2
+#define PRT3    3
+#define PRTM    4
+#define PRCU    5
+#define PRDS    6
+#define PRVM    7
+
+#define PRR1    _SFR_MEM8(0x64)
+#define PRCI    0
+#define PRSPI   1
+
+#define SRCCAL  _SFR_MEM8(0x65)
+
+#define FRCCAL  _SFR_MEM8(0x66)
+
+/* Reserved [0x67..0x68] */
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC00   0
+#define ISC01   1
+
+#define PCMSK0  _SFR_MEM8(0x6A)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6B)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+/* Reserved [0x6C] */
+
+#define LDCR    _SFR_MEM8(0x6D)
+#define LDE     0
+#define LDCS0   1
+#define LDCS1   2
+
+/* Reserved [0x6E..0x6F] */
+
+#define T2CNT   _SFR_MEM8(0x70)
+
+#define T2COR   _SFR_MEM8(0x71)
+
+/* Reserved [0x72] */
+
+#define T2MR    _SFR_MEM8(0x73)
+#define T2CS0   0
+#define T2CS1   1
+#define T2CS2   2
+#define T2PS0   3
+#define T2PS1   4
+#define T2PS2   5
+#define T2D0    6
+#define T2D1    7
+
+#define T2IMR   _SFR_MEM8(0x74)
+#define T2OIM   0
+#define T2CIM   1
+
+/* Reserved [0x75] */
+
+#define T3CNT   _SFR_MEM8(0x76)
+
+#define T3COR   _SFR_MEM8(0x77)
+
+#define T3ICR   _SFR_MEM8(0x78)
+
+#define T3MRA   _SFR_MEM8(0x79)
+#define T3CS0   0
+#define T3CS1   1
+#define T3SCE   2
+#define T3CE0   3
+#define T3CE1   4
+#define T3CNC   5
+#define T3ICS0  6
+#define T3ICS1  7
+
+#define T3MRB   _SFR_MEM8(0x7A)
+#define T3PS0   0
+#define T3PS1   1
+#define T3PS2   2
+
+#define T3IMR   _SFR_MEM8(0x7B)
+#define T3OIM   0
+#define T3CIM   1
+#define T3CPIM  2
+
+/* Reserved [0x7C] */
+
+#define TMCR    _SFR_MEM8(0x7D)
+#define MI1S0   0
+#define MI1S1   1
+#define MI2S0   2
+#define MI2S1   3
+#define MI4S0   4
+#define MI4S1   5
+#define TMCPOL  6
+#define TMSSIE  7
+
+#define TMMR    _SFR_MEM8(0x7E)
+#define MOS0    0
+#define MOS1    1
+#define MSCS0   2
+#define MSCS1   3
+#define MOUTC   4
+#define TMMS0   5
+#define TMMS1   6
+#define TM12S   7
+
+#define TMIMR   _SFR_MEM8(0x7F)
+#define TMRXIM  0
+#define TMTXIM  1
+#define TMTCIM  2
+
+/* Reserved [0x80..0x81] */
+
+#define LFIMR   _SFR_MEM8(0x82)
+#define LFID0IM 0
+#define LFID1IM 1
+#define LFFEIM  2
+#define LFDBIM  3
+#define LFRSIM  4
+#define LFSDIM  5
+#define LFMDIM  6
+
+#define LFCAD   _SFR_MEM8(0x83)
+
+#define LFID00  _SFR_MEM8(0x84)
+
+#define LFID01  _SFR_MEM8(0x85)
+
+#define LFID02  _SFR_MEM8(0x86)
+
+#define LFID03  _SFR_MEM8(0x87)
+
+#define LFID10  _SFR_MEM8(0x88)
+
+#define LFID11  _SFR_MEM8(0x89)
+
+#define LFID12  _SFR_MEM8(0x8A)
+
+#define LFID13  _SFR_MEM8(0x8B)
+
+#define LFRD0   _SFR_MEM8(0x8C)
+
+#define LFRD1   _SFR_MEM8(0x8D)
+
+#define LFRD2   _SFR_MEM8(0x8E)
+
+#define LFRD3   _SFR_MEM8(0x8F)
+
+#define LFID0M  _SFR_MEM8(0x90)
+#define ID0FS0  0
+#define ID0FS1  1
+#define ID0FS2  2
+#define ID0FS3  3
+#define ID0FS4  4
+#define ID0E    7
+
+#define LFID1M  _SFR_MEM8(0x91)
+#define ID1FS0  0
+#define ID1FS1  1
+#define ID1FS2  2
+#define ID1FS3  3
+#define ID1FS4  4
+#define ID1E    7
+
+#define LFRDF   _SFR_MEM8(0x92)
+#define RDFS0   0
+#define RDFS1   1
+#define RDFS2   2
+#define RDFS3   3
+#define RDFS4   4
+#define RDFE    7
+
+#define LFRSD1  _SFR_MEM8(0x93)
+
+#define LFRSD2  _SFR_MEM8(0x94)
+
+#define LFRSD3  _SFR_MEM8(0x95)
+
+#define LFCC1   _SFR_MEM8(0x96)
+
+#define LFCC2   _SFR_MEM8(0x97)
+
+#define LFCC3   _SFR_MEM8(0x98)
+
+/* Reserved [0x99..0x9B] */
+
+#define TPIMR   _SFR_MEM8(0x9C)
+#define TPIM    0
+
+/* Reserved [0x9D] */
+
+#define RTCCR   _SFR_MEM8(0x9E)
+#define RTCR    0
+
+#define RTCDR   _SFR_MEM8(0x9F)
+
+/* Reserved [0xA0..0xA7] */
+
+#define TMMDR   _SFR_MEM8(0xA8)
+
+#define TMBDR   _SFR_MEM8(0xA9)
+
+#define TMTDR   _SFR_MEM8(0xAA)
+
+#define TMSR    _SFR_MEM8(0xAB)
+
+/* Reserved [0xAC] */
+
+#define CRCDR   _SFR_MEM8(0xAD)
+
+#define CRCCR   _SFR_MEM8(0xAE)
+#define CRCN0   0
+#define CRCN1   1
+#define CRCN2   2
+#define CRCSEL  3
+#define REFLI   4
+#define REFLO   5
+#define CRCRS   7
+
+#define CRCSR   _SFR_MEM8(0xAF)
+#define CRCBF   0
+
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* Transponder Mode Interrupt */
+#define TPINT_vect            _VECTOR(1)
+#define TPINT_vect_num        1
+
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(2)
+#define INT0_vect_num        2
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect            _VECTOR(3)
+#define PCINT0_vect_num        3
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect            _VECTOR(4)
+#define PCINT1_vect_num        4
+
+/* Voltage Monitoring Interrupt */
+#define VMINT_vect            _VECTOR(5)
+#define VMINT_vect_num        5
+
+/* Timer0 Interval Interrupt */
+#define T0INT_vect            _VECTOR(6)
+#define T0INT_vect_num        6
+
+/* LF-Receiver Identifier 0 Interrupt */
+#define LFID0INT_vect            _VECTOR(7)
+#define LFID0INT_vect_num        7
+
+/* LF-Receiver Identifier 1 Interrupt */
+#define LFID1INT_vect            _VECTOR(8)
+#define LFID1INT_vect_num        8
+
+/* LF-Receiver Frame End Interrupt */
+#define LFFEINT_vect            _VECTOR(9)
+#define LFFEINT_vect_num        9
+
+/* LF-Receiver Data Buffer full Interrupt */
+#define LFDBINT_vect            _VECTOR(10)
+#define LFDBINT_vect_num        10
+
+/* Timer/Counter3 Capture Event Interrupt */
+#define T3CAPINT_vect            _VECTOR(11)
+#define T3CAPINT_vect_num        11
+
+/* Timer/Counter3 Compare Match Interrupt */
+#define T3COMINT_vect            _VECTOR(12)
+#define T3COMINT_vect_num        12
+
+/* Timer/Counter3 Overflow Interrupt */
+#define T3OVFINT_vect            _VECTOR(13)
+#define T3OVFINT_vect_num        13
+
+/* Timer/Counter2 Compare Match Interrupt */
+#define T2COMINT_vect            _VECTOR(14)
+#define T2COMINT_vect_num        14
+
+/* Timer/Counter2 Overflow Interrupt */
+#define T2OVFINT_vect            _VECTOR(15)
+#define T2OVFINT_vect_num        15
+
+/* Timer 1 Interval Interrupt */
+#define T1INT_vect            _VECTOR(16)
+#define T1INT_vect_num        16
+
+/* SPI Serial Transfer Complete Interrupt */
+#define SPISTC_vect            _VECTOR(17)
+#define SPISTC_vect_num        17
+
+/* Timer Modulator SSI Receive Buffer Interrupt */
+#define TMRXBINT_vect            _VECTOR(18)
+#define TMRXBINT_vect_num        18
+
+/* Timer Modulator SSI Transmit Buffer Interrupt */
+#define TMTXBINT_vect            _VECTOR(19)
+#define TMTXBINT_vect_num        19
+
+/* Timer Modulator Transmit Complete Interrupt */
+#define TMTXCINT_vect            _VECTOR(20)
+#define TMTXCINT_vect_num        20
+
+/* AES Interrupt */
+#define AESINT_vect            _VECTOR(21)
+#define AESINT_vect_num        21
+
+/* LF-Receiver RSSi measurement Interrupt */
+#define LFRSSINT_vect            _VECTOR(22)
+#define LFRSSINT_vect_num        22
+
+/* LF-Receiver Signal Detect Interrupt */
+#define LFSDINT_vect            _VECTOR(23)
+#define LFSDINT_vect_num        23
+
+/* LF-Receiver Manchester Decoder error Interrupt  */
+#define LFMDINT_vect            _VECTOR(24)
+#define LFMDINT_vect_num        24
+
+/* External Input Clock Monitoring Interrupt */
+#define EXCMINT_vect            _VECTOR(25)
+#define EXCMINT_vect_num        25
+
+/* External XTAL Oscillator Break Down Interrupt */
+#define EXXMINT_vect            _VECTOR(26)
+#define EXXMINT_vect_num        26
+
+/* Real Time Clock Interrupt */
+#define RTCINT_vect            _VECTOR(27)
+#define RTCINT_vect_num        27
+
+/* EEPROM Ready Interrupt */
+#define EEREADY_vect            _VECTOR(28)
+#define EEREADY_vect_num        28
+
+/* Store Program Memory Ready  */
+#define SPMREADY_vect            _VECTOR(29)
+#define SPMREADY_vect_num        29
+
+#define _VECTORS_SIZE 120
+
+
+/* Constants */
+
+#define SPM_PAGESIZE 128
+#define FLASHSTART   0x0000
+#define FLASHEND     0x3FFF
+#define RAMSTART     0x0100
+#define RAMSIZE      512
+#define RAMEND       0x02FF
+#define E2START     0
+#define E2SIZE      2048
+#define E2PAGESIZE  16
+#define E2END       0x07FF
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 1
+
+/* Fuse Byte */
+#define FUSE_CKDIV8 (unsigned char)~_BV(128)
+#define FUSE_DWEN (unsigned char)~_BV(64)
+#define FUSE_SPIEN (unsigned char)~_BV(32)
+#define FUSE_WDTON (unsigned char)~_BV(16)
+#define FUSE_EESAVE (unsigned char)~_BV(8)
+#define FUSE_Reserved (unsigned char)~_BV(4)
+#define FUSE__32OEN (unsigned char)~_BV(2)
+#define FUSE_EXTCLKEN (unsigned char)~_BV(1)
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x94
+#define SIGNATURE_2 0x61
+
+
+#endif /* #ifdef _AVR_ATA5790_H_INCLUDED */
+
diff -urN avr-libc-1.8.0.orig/include/avr/ioa5790n.h avr-libc-1.8.0/include/avr/ioa5790n.h
--- avr-libc-1.8.0.orig/include/avr/ioa5790n.h	1970-01-01 01:00:00.000000000 +0100
+++ avr-libc-1.8.0/include/avr/ioa5790n.h	2013-06-12 12:21:34.000000000 +0200
@@ -0,0 +1,850 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2013 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATA5790N_H_INCLUDED
+#define _AVR_ATA5790N_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "ioa5790n.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDRB7   7
+#define DDRB6   6
+#define DDRB5   5
+#define DDRB4   4
+#define DDRB3   3
+#define DDRB2   2
+#define DDRB1   1
+#define DDRB0   0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDRC7   7
+#define DDRC6   6
+#define DDRC5   5
+#define DDRC4   4
+#define DDRC3   3
+#define DDRC2   2
+#define DDRC1   1
+#define DDRC0   0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PORTC7  7
+#define PORTC6  6
+#define PORTC5  5
+#define PORTC4  4
+#define PORTC3  3
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDRD7   7
+#define DDRD6   6
+#define DDRD5   5
+#define DDRD4   4
+#define DDRD3   3
+#define DDRD2   2
+#define DDRD1   1
+#define DDRD0   0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PORTD7  7
+#define PORTD6  6
+#define PORTD5  5
+#define PORTD4  4
+#define PORTD3  3
+#define PORTD2  2
+#define PORTD1  1
+#define PORTD0  0
+
+#define T3CR2   _SFR_IO8(0x0C)
+#define T3GRES  0
+#define T3C2TM  1
+#define T3C2RM  2
+
+#define TPCR    _SFR_IO8(0x0D)
+#define TPMA    0
+#define TPMOD   1
+#define TPMS0   2
+#define TPMS1   3
+#define TPMD0   4
+#define TPMD1   5
+#define TPPSD   6
+#define TPD     7
+
+#define TPFR    _SFR_IO8(0x0E)
+#define TPF     0
+#define TPA     1
+#define TPGAP   2
+#define TPPSW   3
+
+#define CMCR    _SFR_IO8(0x0F)
+#define CMM0    0
+#define CMM1    1
+#define SRCD    2
+#define CO32D   3
+#define CCS     4
+#define ECINS   5
+#define CMONEN  6
+#define CMCCE   7
+
+#define CMSR    _SFR_IO8(0x10)
+#define ECF     0
+#define SXF     1
+#define RTCF    2
+
+#define T2CR    _SFR_IO8(0x11)
+#define T2OTM   0
+#define T2CTM   1
+#define T2CRM   2
+#define T2GRM   3
+#define T2TOP   4
+#define T2RES   5
+#define T2TS    6
+#define T2E     7
+
+#define T3CR    _SFR_IO8(0x12)
+#define T3OTM   0
+#define T3CTM   1
+#define T3CRM   2
+#define T3CPRM  3
+#define T3TOP   4
+#define T3RES   5
+#define T3CPTM  6
+#define T3E     7
+
+#define AESCR   _SFR_IO8(0x13)
+#define AESWK   0
+#define AESWD   1
+#define AESIM   2
+#define AESD    3
+#define AESXOR  4
+#define AESRES  5
+#define AESE    7
+
+#define AESSR   _SFR_IO8(0x14)
+#define AESRF   0
+#define AESERF  7
+
+#define TMIFR   _SFR_IO8(0x15)
+#define TMRXF   0
+#define TMTXF   1
+#define TMTCF   2
+#define TMRXS   3
+#define TMTXS   4
+
+#define VMSR    _SFR_IO8(0x16)
+#define VMF     0
+
+#define PCIFR   _SFR_IO8(0x17)
+#define PCIF0   0
+#define PCIF1   1
+
+#define LFFR    _SFR_IO8(0x18)
+#define LFID0F  0
+#define LFID1F  1
+#define LFFEF   2
+#define LFDBF   3
+#define LFRSF   4
+#define LFSDF   5
+#define LFMDF   6
+#define LFCAF   7
+
+#define T0IFR   _SFR_IO8(0x19)
+#define T0F     0
+
+#define T1IFR   _SFR_IO8(0x1A)
+#define T1F     0
+
+#define T2IFR   _SFR_IO8(0x1B)
+#define T2OFF   0
+#define T2COF   1
+
+#define T3IFR   _SFR_IO8(0x1C)
+#define T3OFF   0
+#define T3COF   1
+#define T3ICF   2
+#define T3CO2F  3
+
+#define EIFR    _SFR_IO8(0x1D)
+#define INTF0   0
+
+#define GPIOR   _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEWE    1
+#define EEMWE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+#define EELP    6
+#define NVMBSY  7
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define EEPR    _SFR_IO8(0x23)
+#define EEAP0   0
+#define EEAP1   1
+#define EEAP2   2
+#define EEAP3   3
+
+#define EECCR   _SFR_IO8(0x24)
+#define EEL0    0
+#define EEL1    1
+#define EEL2    2
+#define EEL3    3
+
+#define EECR2   _SFR_IO8(0x25)
+#define EEBRE   0
+#define EEPAGE  1
+
+#define PCICR   _SFR_IO8(0x26)
+#define PCIE0   0
+#define PCIE1   1
+
+#define EIMSK   _SFR_IO8(0x27)
+#define INT0    0
+
+#define TMDR    _SFR_IO8(0x28)
+
+#define AESDR   _SFR_IO8(0x29)
+
+#define AESKR   _SFR_IO8(0x2A)
+#define AESKR0  0
+#define AESKR1  1
+#define AESKR2  2
+#define AESKR3  3
+#define AESKR4  4
+#define AESKR5  5
+#define AESKR6  6
+#define AESKR7  7
+
+#define VMCR    _SFR_IO8(0x2B)
+#define VMLS0   0
+#define VMLS1   1
+#define VMLS2   2
+#define VMLS3   3
+#define VMIM    4
+#define VMPS    5
+#define BODPD   6
+#define BODLS   7
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+#define LFCR0   _SFR_IO8(0x2F)
+#define LFCE1   0
+#define LFCE2   1
+#define LFCE3   2
+#define LFBRS   3
+#define LFRBS   4
+#define LFMG    5
+#define LFVC0   6
+#define LFVC1   7
+
+#define LFCR1   _SFR_IO8(0x30)
+#define LFM0    0
+#define LFM1    1
+#define LFFM0   2
+#define LFFM1   3
+#define LFRMS   4
+#define LFRMSA  5
+#define LFQCE   6
+#define LFRE    7
+
+/* Reserved [0x31] */
+
+#define LFRDB   _SFR_IO8(0x32)
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define MCUSR   _SFR_IO8(0x34)
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+#define TPRF    5
+
+#define MCUCR   _SFR_IO8(0x35)
+#define IVCE    0
+#define IVSEL   1
+#define PUD     4
+
+#define LFSR    _SFR_IO8(0x36)
+#define LFES    0
+#define LFSD    1
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define RWWSRE  4
+#define SIGRD   5
+#define RWWSB   6
+#define SPMIE   7
+
+#define T1CR    _SFR_IO8(0x38)
+#define T1PS0   0
+#define T1PS1   1
+#define T1IE    2
+#define T1CS0   3
+#define T1CS1   4
+#define T1E     7
+
+#define T0CR    _SFR_IO8(0x39)
+#define T0PS0   0
+#define T0PS1   1
+#define T0PS2   2
+#define T0IE    3
+#define T0PR    4
+
+/* Reserved [0x3A] */
+
+#define CMIMR   _SFR_IO8(0x3B)
+#define ECIE    0
+#define SXIE    1
+#define RTCIE   2
+
+#define CLKPR   _SFR_IO8(0x3C)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLTPS0  3
+#define CLTPS1  4
+#define CLTPS2  5
+#define CLKPCE  7
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define WDTCR   _SFR_MEM8(0x60)
+#define WDPS0   0
+#define WDPS1   1
+#define WDPS2   2
+#define WDE     3
+#define WDCE    4
+
+/* Reserved [0x61..0x62] */
+
+#define PRR0    _SFR_MEM8(0x63)
+#define PRLFR   0
+#define PRT1    1
+#define PRT2    2
+#define PRT3    3
+#define PRTM    4
+#define PRCU    5
+#define PRDS    6
+#define PRVM    7
+
+#define PRR1    _SFR_MEM8(0x64)
+#define PRCI    0
+#define PRSPI   1
+
+#define SRCCAL  _SFR_MEM8(0x65)
+
+#define FRCCAL  _SFR_MEM8(0x66)
+
+/* Reserved [0x67..0x68] */
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC00   0
+#define ISC01   1
+
+#define PCMSK0  _SFR_MEM8(0x6A)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6B)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+/* Reserved [0x6C] */
+
+#define LDCR    _SFR_MEM8(0x6D)
+#define LDE     0
+#define LDCS0   1
+#define LDCS1   2
+
+/* Reserved [0x6E..0x6F] */
+
+#define T2CNT   _SFR_MEM8(0x70)
+
+#define T2COR   _SFR_MEM8(0x71)
+
+/* Reserved [0x72] */
+
+#define T2MR    _SFR_MEM8(0x73)
+#define T2CS0   0
+#define T2CS1   1
+#define T2CS2   2
+#define T2PS0   3
+#define T2PS1   4
+#define T2PS2   5
+#define T2D0    6
+#define T2D1    7
+
+#define T2IMR   _SFR_MEM8(0x74)
+#define T2OIM   0
+#define T2CIM   1
+
+#define T3CO2R  _SFR_MEM8(0x75)
+
+#define T3CNT   _SFR_MEM8(0x76)
+
+#define T3COR   _SFR_MEM8(0x77)
+
+#define T3ICR   _SFR_MEM8(0x78)
+
+#define T3MRA   _SFR_MEM8(0x79)
+#define T3CS0   0
+#define T3CS1   1
+#define T3SCE   2
+#define T3CE0   3
+#define T3CE1   4
+#define T3CNC   5
+#define T3ICS0  6
+#define T3ICS1  7
+
+#define T3MRB   _SFR_MEM8(0x7A)
+#define T3PS0   0
+#define T3PS1   1
+#define T3PS2   2
+
+#define T3IMR   _SFR_MEM8(0x7B)
+#define T3OIM   0
+#define T3CIM   1
+#define T3CPIM  2
+#define T3C2IM  3
+
+/* Reserved [0x7C] */
+
+#define TMCR    _SFR_MEM8(0x7D)
+#define MI1S0   0
+#define MI1S1   1
+#define MI2S0   2
+#define MI2S1   3
+#define MI4S0   4
+#define MI4S1   5
+#define TMCPOL  6
+#define TMSSIE  7
+
+#define TMMR    _SFR_MEM8(0x7E)
+#define MOS0    0
+#define MOS1    1
+#define MSCS0   2
+#define MSCS1   3
+#define MOUTC   4
+#define TMMS0   5
+#define TMMS1   6
+#define TM12S   7
+
+#define TMIMR   _SFR_MEM8(0x7F)
+#define TMRXIM  0
+#define TMTXIM  1
+#define TMTCIM  2
+
+/* Reserved [0x80..0x81] */
+
+#define LFIMR   _SFR_MEM8(0x82)
+#define LFID0IM 0
+#define LFID1IM 1
+#define LFFEIM  2
+#define LFDBIM  3
+#define LFRSIM  4
+#define LFSDIM  5
+#define LFMDIM  6
+
+#define LFCAD   _SFR_MEM8(0x83)
+
+#define LFID00  _SFR_MEM8(0x84)
+
+#define LFID01  _SFR_MEM8(0x85)
+
+#define LFID02  _SFR_MEM8(0x86)
+
+#define LFID03  _SFR_MEM8(0x87)
+
+#define LFID10  _SFR_MEM8(0x88)
+
+#define LFID11  _SFR_MEM8(0x89)
+
+#define LFID12  _SFR_MEM8(0x8A)
+
+#define LFID13  _SFR_MEM8(0x8B)
+
+#define LFRD0   _SFR_MEM8(0x8C)
+
+#define LFRD1   _SFR_MEM8(0x8D)
+
+#define LFRD2   _SFR_MEM8(0x8E)
+
+#define LFRD3   _SFR_MEM8(0x8F)
+
+#define LFID0M  _SFR_MEM8(0x90)
+#define ID0FS0  0
+#define ID0FS1  1
+#define ID0FS2  2
+#define ID0FS3  3
+#define ID0FS4  4
+#define ID0E    7
+
+#define LFID1M  _SFR_MEM8(0x91)
+#define ID1FS0  0
+#define ID1FS1  1
+#define ID1FS2  2
+#define ID1FS3  3
+#define ID1FS4  4
+#define ID1E    7
+
+#define LFRDF   _SFR_MEM8(0x92)
+#define RDFS0   0
+#define RDFS1   1
+#define RDFS2   2
+#define RDFS3   3
+#define RDFS4   4
+#define RDFE    7
+
+#define LFRSD1  _SFR_MEM8(0x93)
+
+#define LFRSD2  _SFR_MEM8(0x94)
+
+#define LFRSD3  _SFR_MEM8(0x95)
+
+#define LFCC1   _SFR_MEM8(0x96)
+
+#define LFCC2   _SFR_MEM8(0x97)
+
+#define LFCC3   _SFR_MEM8(0x98)
+
+#define LFQCR   _SFR_MEM8(0x99)
+#define LFQCLL  0
+
+/* Reserved [0x9A..0x9B] */
+
+#define TPIMR   _SFR_MEM8(0x9C)
+#define TPIM    0
+
+/* Reserved [0x9D] */
+
+#define RTCCR   _SFR_MEM8(0x9E)
+#define RTCR    0
+
+#define RTCDR   _SFR_MEM8(0x9F)
+
+/* Reserved [0xA0..0xA7] */
+
+#define TMMDR   _SFR_MEM8(0xA8)
+
+#define TMBDR   _SFR_MEM8(0xA9)
+
+#define TMTDR   _SFR_MEM8(0xAA)
+
+#define TMSR    _SFR_MEM8(0xAB)
+
+#define CRCPOL  _SFR_MEM8(0xAC)
+
+#define CRCDR   _SFR_MEM8(0xAD)
+
+#define CRCCR   _SFR_MEM8(0xAE)
+#define CRCN0   0
+#define CRCN1   1
+#define CRCN2   2
+#define CRCSEL  3
+#define REFLI   4
+#define REFLO   5
+#define STVAL   6
+#define CRCRS   7
+
+#define CRCSR   _SFR_MEM8(0xAF)
+#define CRCBF   0
+
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* Transponder Mode Interrupt */
+#define TPINT_vect            _VECTOR(1)
+#define TPINT_vect_num        1
+
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(2)
+#define INT0_vect_num        2
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect            _VECTOR(3)
+#define PCINT0_vect_num        3
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect            _VECTOR(4)
+#define PCINT1_vect_num        4
+
+/* Voltage Monitoring Interrupt */
+#define VMINT_vect            _VECTOR(5)
+#define VMINT_vect_num        5
+
+/* Timer0 Interval Interrupt */
+#define T0INT_vect            _VECTOR(6)
+#define T0INT_vect_num        6
+
+/* LF-Receiver Identifier 0 Interrupt */
+#define LFID0INT_vect            _VECTOR(7)
+#define LFID0INT_vect_num        7
+
+/* LF-Receiver Identifier 1 Interrupt */
+#define LFID1INT_vect            _VECTOR(8)
+#define LFID1INT_vect_num        8
+
+/* LF-Receiver Frame End Interrupt */
+#define LFFEINT_vect            _VECTOR(9)
+#define LFFEINT_vect_num        9
+
+/* LF-Receiver Data Buffer full Interrupt */
+#define LFDBINT_vect            _VECTOR(10)
+#define LFDBINT_vect_num        10
+
+/* Timer/Counter3 Capture Event Interrupt */
+#define T3CAPINT_vect            _VECTOR(11)
+#define T3CAPINT_vect_num        11
+
+/* Timer/Counter3 Compare Match Interrupt */
+#define T3COMINT_vect            _VECTOR(12)
+#define T3COMINT_vect_num        12
+
+/* Timer/Counter3 Overflow Interrupt */
+#define T3OVFINT_vect            _VECTOR(13)
+#define T3OVFINT_vect_num        13
+
+/* Timer/Counter3 Compare Match 2 Interrupt */
+#define T3COM2INT_vect            _VECTOR(14)
+#define T3COM2INT_vect_num        14
+
+/* Timer/Counter2 Compare Match Interrupt */
+#define T2COMINT_vect            _VECTOR(15)
+#define T2COMINT_vect_num        15
+
+/* Timer/Counter2 Overflow Interrupt */
+#define T2OVFINT_vect            _VECTOR(16)
+#define T2OVFINT_vect_num        16
+
+/* Timer 1 Interval Interrupt */
+#define T1INT_vect            _VECTOR(17)
+#define T1INT_vect_num        17
+
+/* SPI Serial Transfer Complete Interrupt */
+#define SPISTC_vect            _VECTOR(18)
+#define SPISTC_vect_num        18
+
+/* Timer Modulator SSI Receive Buffer Interrupt */
+#define TMRXBINT_vect            _VECTOR(19)
+#define TMRXBINT_vect_num        19
+
+/* Timer Modulator SSI Transmit Buffer Interrupt */
+#define TMTXBINT_vect            _VECTOR(20)
+#define TMTXBINT_vect_num        20
+
+/* Timer Modulator Transmit Complete Interrupt */
+#define TMTXCINT_vect            _VECTOR(21)
+#define TMTXCINT_vect_num        21
+
+/* AES Interrupt */
+#define AESINT_vect            _VECTOR(22)
+#define AESINT_vect_num        22
+
+/* LF-Receiver RSSi measurement Interrupt */
+#define LFRSSINT_vect            _VECTOR(23)
+#define LFRSSINT_vect_num        23
+
+/* LF-Receiver Signal Detect Interrupt */
+#define LFSDINT_vect            _VECTOR(24)
+#define LFSDINT_vect_num        24
+
+/* LF-Receiver Manchester Decoder error Interrupt  */
+#define LFMDINT_vect            _VECTOR(25)
+#define LFMDINT_vect_num        25
+
+/* External Input Clock Monitoring Interrupt */
+#define EXCMINT_vect            _VECTOR(26)
+#define EXCMINT_vect_num        26
+
+/* External XTAL Oscillator Break Down Interrupt */
+#define EXXMINT_vect            _VECTOR(27)
+#define EXXMINT_vect_num        27
+
+/* Real Time Clock Interrupt */
+#define RTCINT_vect            _VECTOR(28)
+#define RTCINT_vect_num        28
+
+/* EEPROM Ready Interrupt */
+#define EEREADY_vect            _VECTOR(29)
+#define EEREADY_vect_num        29
+
+/* Store Program Memory Ready  */
+#define SPMREADY_vect            _VECTOR(30)
+#define SPMREADY_vect_num        30
+
+#define _VECTORS_SIZE 124
+
+
+/* Constants */
+
+#define SPM_PAGESIZE 128
+#define FLASHSTART   0x0000
+#define FLASHEND     0x3FFF
+#define RAMSTART     0x0100
+#define RAMSIZE      512
+#define RAMEND       0x02FF
+#define E2START     0
+#define E2SIZE      2048
+#define E2PAGESIZE  16
+#define E2END       0x07FF
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 1
+
+/* Fuse Byte */
+#define FUSE_CKDIV8 (unsigned char)~_BV(128)
+#define FUSE_DWEN (unsigned char)~_BV(64)
+#define FUSE_SPIEN (unsigned char)~_BV(32)
+#define FUSE_WDTON (unsigned char)~_BV(16)
+#define FUSE_EESAVE (unsigned char)~_BV(8)
+#define FUSE_Reserved (unsigned char)~_BV(4)
+#define FUSE__32OEN (unsigned char)~_BV(2)
+#define FUSE_EXTCLKEN (unsigned char)~_BV(1)
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x94
+#define SIGNATURE_2 0x62
+
+
+#endif /* #ifdef _AVR_ATA5790N_H_INCLUDED */
+
diff -urN avr-libc-1.8.0.orig/include/avr/ioa5795.h avr-libc-1.8.0/include/avr/ioa5795.h
--- avr-libc-1.8.0.orig/include/avr/ioa5795.h	1970-01-01 01:00:00.000000000 +0100
+++ avr-libc-1.8.0/include/avr/ioa5795.h	2013-06-12 12:21:34.000000000 +0200
@@ -0,0 +1,700 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2013 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATA5795_H_INCLUDED
+#define _AVR_ATA5795_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "ioa5795.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDRB7   7
+#define DDRB6   6
+#define DDRB5   5
+#define DDRB4   4
+#define DDRB3   3
+#define DDRB2   2
+#define DDRB1   1
+#define DDRB0   0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDRC7   7
+#define DDRC6   6
+#define DDRC5   5
+#define DDRC4   4
+#define DDRC3   3
+#define DDRC2   2
+#define DDRC1   1
+#define DDRC0   0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PORTC7  7
+#define PORTC6  6
+#define PORTC5  5
+#define PORTC4  4
+#define PORTC3  3
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDRD7   7
+#define DDRD6   6
+#define DDRD5   5
+#define DDRD4   4
+#define DDRD3   3
+#define DDRD2   2
+#define DDRD1   1
+#define DDRD0   0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PORTD7  7
+#define PORTD6  6
+#define PORTD5  5
+#define PORTD4  4
+#define PORTD3  3
+#define PORTD2  2
+#define PORTD1  1
+#define PORTD0  0
+
+/* Reserved [0x0C] */
+
+#define TPCR    _SFR_IO8(0x0D)
+#define TPMA    0
+#define TPMOD   1
+#define TPMS0   2
+#define TPMS1   3
+#define TPMD0   4
+#define TPMD1   5
+#define TPPSD   6
+#define TPD     7
+
+#define TPFR    _SFR_IO8(0x0E)
+#define TPF     0
+#define TPA     1
+#define TPGAP   2
+#define TPPSW   3
+
+#define CMCR    _SFR_IO8(0x0F)
+#define CMM0    0
+#define CMM1    1
+#define SRCD    2
+#define CO32D   3
+#define CCS     4
+#define ECINS   5
+#define CMONEN  6
+#define CMCCE   7
+
+#define CMSR    _SFR_IO8(0x10)
+#define ECF     0
+#define SXF     1
+#define RTCF    2
+
+#define T2CR    _SFR_IO8(0x11)
+#define T2OTM   0
+#define T2CTM   1
+#define T2CRM   2
+#define T2GRM   3
+#define T2TOP   4
+#define T2RES   5
+#define T2TS    6
+#define T2E     7
+
+#define T3CR    _SFR_IO8(0x12)
+#define T3OTM   0
+#define T3CTM   1
+#define T3CRM   2
+#define T3CPRM  3
+#define T3TOP   4
+#define T3RES   5
+#define T3CPTM  6
+#define T3E     7
+
+#define AESCR   _SFR_IO8(0x13)
+#define AESWK   0
+#define AESWD   1
+#define AESIM   2
+#define AESD    3
+#define AESXOR  4
+#define AESRES  5
+#define AESE    7
+
+#define AESSR   _SFR_IO8(0x14)
+#define AESRF   0
+#define AESERF  7
+
+#define TMIFR   _SFR_IO8(0x15)
+#define TMRXF   0
+#define TMTXF   1
+#define TMTCF   2
+#define TMRXS   3
+#define TMTXS   4
+
+#define VMSR    _SFR_IO8(0x16)
+#define VMF     0
+
+#define PCIFR   _SFR_IO8(0x17)
+#define PCIF0   0
+#define PCIF1   1
+
+/* Reserved [0x18] */
+
+#define T0IFR   _SFR_IO8(0x19)
+#define T0F     0
+
+#define T1IFR   _SFR_IO8(0x1A)
+#define T1F     0
+
+#define T2IFR   _SFR_IO8(0x1B)
+#define T2OFF   0
+#define T2COF   1
+
+#define T3IFR   _SFR_IO8(0x1C)
+#define T3OFF   0
+#define T3COF   1
+#define T3ICF   2
+
+#define EIFR    _SFR_IO8(0x1D)
+#define INTF0   0
+
+#define GPIOR0  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEWE    1
+#define EEMWE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+#define EELP    6
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define EEPR    _SFR_IO8(0x23)
+#define EEAP0   0
+#define EEAP1   1
+#define EEAP2   2
+#define EEAP3   3
+
+#define EECCR   _SFR_IO8(0x24)
+#define EEL0    0
+#define EEL1    1
+#define EEL2    2
+#define EEL3    3
+
+/* Reserved [0x25] */
+
+#define PCICR   _SFR_IO8(0x26)
+#define PCIE0   0
+#define PCIE1   1
+
+#define EIMSK   _SFR_IO8(0x27)
+#define INT0    0
+
+#define TMDR    _SFR_IO8(0x28)
+
+#define AESDR   _SFR_IO8(0x29)
+
+#define AESKR   _SFR_IO8(0x2A)
+#define AESKR0  0
+#define AESKR1  1
+#define AESKR2  2
+#define AESKR3  3
+#define AESKR4  4
+#define AESKR5  5
+#define AESKR6  6
+#define AESKR7  7
+
+#define VMCR    _SFR_IO8(0x2B)
+#define VMLS0   0
+#define VMLS1   1
+#define VMLS2   2
+#define VMLS3   3
+#define VMIM    4
+#define VMPS    5
+#define BODPD   6
+#define BODLS   7
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+/* Reserved [0x2F..0x32] */
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define MCUSR   _SFR_IO8(0x34)
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+#define TPRF    5
+
+#define MCUCR   _SFR_IO8(0x35)
+#define IVCE    0
+#define IVSEL   1
+#define PUD     4
+
+/* Reserved [0x36] */
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SPMEN   0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define RWWSRE  4
+#define SIGRD   5
+#define RWWSB   6
+#define SPMIE   7
+
+#define T1CR    _SFR_IO8(0x38)
+#define T1PS0   0
+#define T1PS1   1
+#define T1IE    2
+#define T1CS0   3
+#define T1CS1   4
+#define T1E     7
+
+#define T0CR    _SFR_IO8(0x39)
+#define T0PS0   0
+#define T0PS1   1
+#define T0PS2   2
+#define T0IE    3
+#define T0PR    4
+
+/* Reserved [0x3A] */
+
+#define CMIMR   _SFR_IO8(0x3B)
+#define ECIE    0
+#define SXIE    1
+#define RTCIE   2
+
+#define CLKPR   _SFR_IO8(0x3C)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLTPS0  3
+#define CLTPS1  4
+#define CLTPS2  5
+#define CLKPCE  7
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define WDTCR   _SFR_MEM8(0x60)
+#define WDPS0   0
+#define WDPS1   1
+#define WDPS2   2
+#define WDE     3
+#define WDCE    4
+
+/* Reserved [0x61..0x62] */
+
+#define PRR0    _SFR_MEM8(0x63)
+#define PRT1    1
+#define PRT2    2
+#define PRT3    3
+#define PRTM    4
+#define PRCU    5
+#define PRDS    6
+#define PRVM    7
+
+#define PRR1    _SFR_MEM8(0x64)
+#define PRCI    0
+#define PRSPI   1
+
+#define SRCCAL  _SFR_MEM8(0x65)
+
+#define FRCCAL  _SFR_MEM8(0x66)
+
+/* Reserved [0x67..0x68] */
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC00   0
+#define ISC01   1
+
+#define PCMSK0  _SFR_MEM8(0x6A)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6B)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+/* Reserved [0x6C] */
+
+#define LDCR    _SFR_MEM8(0x6D)
+#define LDE     0
+#define LDCS0   1
+#define LDCS1   2
+
+/* Reserved [0x6E..0x6F] */
+
+#define T2CNT   _SFR_MEM8(0x70)
+
+#define T2COR   _SFR_MEM8(0x71)
+
+/* Reserved [0x72] */
+
+#define T2MR    _SFR_MEM8(0x73)
+#define T2CS0   0
+#define T2CS1   1
+#define T2CS2   2
+#define T2PS0   3
+#define T2PS1   4
+#define T2PS2   5
+#define T2D0    6
+#define T2D1    7
+
+#define T2IMR   _SFR_MEM8(0x74)
+#define T2OIM   0
+#define T2CIM   1
+
+/* Reserved [0x75] */
+
+#define T3CNT   _SFR_MEM8(0x76)
+
+#define T3COR   _SFR_MEM8(0x77)
+
+#define T3ICR   _SFR_MEM8(0x78)
+
+#define T3MRA   _SFR_MEM8(0x79)
+#define T3CS0   0
+#define T3CS1   1
+#define T3SCE   2
+#define T3CE0   3
+#define T3CE1   4
+#define T3CNC   5
+#define T3ICS0  6
+#define T3ICS1  7
+
+#define T3MRB   _SFR_MEM8(0x7A)
+#define T3PS0   0
+#define T3PS1   1
+#define T3PS2   2
+
+#define T3IMR   _SFR_MEM8(0x7B)
+#define T3OIM   0
+#define T3CIM   1
+#define T3CPIM  2
+
+/* Reserved [0x7C] */
+
+#define TMCR    _SFR_MEM8(0x7D)
+#define MI1S0   0
+#define MI1S1   1
+#define MI2S0   2
+#define MI2S1   3
+#define MI4S0   4
+#define MI4S1   5
+#define TMCPOL  6
+#define TMSSIE  7
+
+#define TMMR    _SFR_MEM8(0x7E)
+#define MOS0    0
+#define MOS1    1
+#define MSCS0   2
+#define MSCS1   3
+#define MOUTC   4
+#define TMMS0   5
+#define TMMS1   6
+#define TM12S   7
+
+#define TMIMR   _SFR_MEM8(0x7F)
+#define TMRXIM  0
+#define TMTXIM  1
+#define TMTCIM  2
+
+/* Reserved [0x80..0x9B] */
+
+#define TPIMR   _SFR_MEM8(0x9C)
+#define TPIM    0
+
+/* Reserved [0x9D] */
+
+#define RTCCR   _SFR_MEM8(0x9E)
+#define RTCR    0
+
+#define RTCDR   _SFR_MEM8(0x9F)
+
+/* Reserved [0xA0..0xA7] */
+
+#define TMMDR   _SFR_MEM8(0xA8)
+
+#define TMBDR   _SFR_MEM8(0xA9)
+
+#define TMTDR   _SFR_MEM8(0xAA)
+
+#define TMSR    _SFR_MEM8(0xAB)
+
+/* Reserved [0xAC] */
+
+#define CRCDR   _SFR_MEM8(0xAD)
+
+#define CRCCR   _SFR_MEM8(0xAE)
+#define CRCN0   0
+#define CRCN1   1
+#define CRCN2   2
+#define CRCSEL  3
+#define REFLI   4
+#define REFLO   5
+#define CRCRS   7
+
+#define CRCSR   _SFR_MEM8(0xAF)
+#define CRCBF   0
+
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* Transponder Mode Interrupt */
+#define TPINT_vect            _VECTOR(2)
+#define TPINT_vect_num        2
+
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(4)
+#define INT0_vect_num        4
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect            _VECTOR(6)
+#define PCINT0_vect_num        6
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect            _VECTOR(8)
+#define PCINT1_vect_num        8
+
+/* Voltage Monitor Interrupt */
+#define VMINT_vect            _VECTOR(10)
+#define VMINT_vect_num        10
+
+/* Timer0 Interval Interrupt */
+#define T0INT_vect            _VECTOR(12)
+#define T0INT_vect_num        12
+
+/* Timer3 Capture Interrupt */
+#define T3CAPINT_vect            _VECTOR(14)
+#define T3CAPINT_vect_num        14
+
+/* Timer3 Compare Match Interrupt */
+#define T3COMINT_vect            _VECTOR(16)
+#define T3COMINT_vect_num        16
+
+/* Timer3 Overflow Interrupt */
+#define T3OVFINT_vect            _VECTOR(18)
+#define T3OVFINT_vect_num        18
+
+/* Timer2 Compare Match Interrupt */
+#define T2COMINT_vect            _VECTOR(20)
+#define T2COMINT_vect_num        20
+
+/* Timer2 Overflow Interrupt */
+#define T2OVFINT_vect            _VECTOR(22)
+#define T2OVFINT_vect_num        22
+
+/* Timer1 Interval Interrupt */
+#define T1INT_vect            _VECTOR(24)
+#define T1INT_vect_num        24
+
+/* SPI Serial Transfer Complete */
+#define SPISTC_vect            _VECTOR(26)
+#define SPISTC_vect_num        26
+
+/* Timer Modulator SSI Receive Buffer Interrupt */
+#define TMRXBINT_vect            _VECTOR(28)
+#define TMRXBINT_vect_num        28
+
+/* Timer Modulator SSI Transmit Buffer Interrupt */
+#define TMTXBINT_vect            _VECTOR(30)
+#define TMTXBINT_vect_num        30
+
+/* Timer Modulator Transmit Complete Interrupt */
+#define TMTXCINT_vect            _VECTOR(32)
+#define TMTXCINT_vect_num        32
+
+/* AES Interrupt */
+#define AESINT_vect            _VECTOR(34)
+#define AESINT_vect_num        34
+
+/* External Input Clock Monitoring Interrupt */
+#define EXCMINT_vect            _VECTOR(36)
+#define EXCMINT_vect_num        36
+
+/* External XTAL Oscillator Break Down Interrupt */
+#define EXXMINT_vect            _VECTOR(38)
+#define EXXMINT_vect_num        38
+
+/* Real Time Clock Interrupt */
+#define RTCINT_vect            _VECTOR(40)
+#define RTCINT_vect_num        40
+
+/* EEPROM Ready Interrupt */
+#define EEREADY_vect            _VECTOR(42)
+#define EEREADY_vect_num        42
+
+/* Store Program Memory Ready  */
+#define SPMREADY_vect            _VECTOR(44)
+#define SPMREADY_vect_num        44
+
+#define _VECTORS_SIZE 46
+
+
+/* Constants */
+
+#define SPM_PAGESIZE 64
+#define FLASHSTART   0x0000
+#define FLASHEND     0x1FFF
+#define RAMSTART     0x0100
+#define RAMSIZE      512
+#define RAMEND       0x02FF
+#define E2START     0
+#define E2SIZE      2048
+#define E2PAGESIZE  16
+#define E2END       0x07FF
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 1
+
+/* Fuse Byte */
+#define FUSE_CKDIV8 (unsigned char)~_BV(128)
+#define FUSE_DWEN (unsigned char)~_BV(64)
+#define FUSE_SPIEN (unsigned char)~_BV(32)
+#define FUSE_WDTON (unsigned char)~_BV(16)
+#define FUSE_EESAVE (unsigned char)~_BV(8)
+#define FUSE_Reserved (unsigned char)~_BV(4)
+#define FUSE__32OEN (unsigned char)~_BV(2)
+#define FUSE_EXTCLKEN (unsigned char)~_BV(1)
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x93
+#define SIGNATURE_2 0x61
+
+
+#endif /* #ifdef _AVR_ATA5795_H_INCLUDED */
+
diff -urN avr-libc-1.8.0.orig/include/avr/ioa5831.h avr-libc-1.8.0/include/avr/ioa5831.h
--- avr-libc-1.8.0.orig/include/avr/ioa5831.h	1970-01-01 01:00:00.000000000 +0100
+++ avr-libc-1.8.0/include/avr/ioa5831.h	2013-06-12 12:21:34.000000000 +0200
@@ -0,0 +1,1891 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2013 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATA5831_H_INCLUDED
+#define _AVR_ATA5831_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "ioa5831.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PRR0    _SFR_IO8(0x01)
+#define PRSPI   0
+#define PRRXDC  1
+#define PRTXDC  2
+#define PRCRC   3
+#define PRVM    4
+#define PRCO    5
+
+#define PRR1    _SFR_IO8(0x02)
+#define PRT1    0
+#define PRT2    1
+#define PRT3    2
+#define PRT4    3
+#define PRT5    4
+
+#define PRR2    _SFR_IO8(0x03)
+#define PRXB    0
+#define PRXA    1
+#define PRSF    2
+#define PRDF    3
+#define PRIDS   4
+#define PRRS    5
+#define PRTM    6
+#define PRSSM   7
+
+#define RDPR    _SFR_IO8(0x04)
+#define PRPTB   0
+#define PRPTA   1
+#define PRFLT   2
+#define PRTMP   3
+#define APRPTB  4
+#define APRPTA  5
+#define ARDPRF  6
+#define RDPRF   7
+
+#define PINB    _SFR_IO8(0x05)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x06)
+#define DDRB7   7
+#define DDRB6   6
+#define DDRB5   5
+#define DDRB4   4
+#define DDRB3   3
+#define DDRB2   2
+#define DDRB1   1
+#define DDRB0   0
+
+#define PORTB   _SFR_IO8(0x07)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINC    _SFR_IO8(0x08)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x09)
+#define DDRC7   7
+#define DDRC6   6
+#define DDRC5   5
+#define DDRC4   4
+#define DDRC3   3
+#define DDRC2   2
+#define DDRC1   1
+#define DDRC0   0
+
+#define PORTC   _SFR_IO8(0x0A)
+#define PORTC7  7
+#define PORTC6  6
+#define PORTC5  5
+#define PORTC4  4
+#define PORTC3  3
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+#define FSCR    _SFR_IO8(0x0B)
+#define TXMOD   0
+#define SFM     1
+#define TXMS0   2
+#define TXMS1   3
+#define PAOER   4
+#define PAON    7
+
+/* Reserved [0x0C] */
+
+#define RDSIFR  _SFR_IO8(0x0D)
+#define NBITA   0
+#define NBITB   1
+#define EOTA    2
+#define EOTB    3
+#define SOTA    4
+#define SOTB    5
+#define WCOA    6
+#define WCOB    7
+
+#define MCUCR   _SFR_IO8(0x0E)
+#define IVCE    0
+#define IVSEL   1
+#define SPIIO   2
+#define ENPS    3
+#define PUD     4
+#define PB4HS   5
+#define PB7LS   6
+#define PB7HS   7
+
+#define PCIFR   _SFR_IO8(0x0F)
+#define PCIF0   0
+#define PCIF1   1
+
+#define T0CR    _SFR_IO8(0x10)
+#define T0PS0   0
+#define T0PS1   1
+#define T0PS2   2
+#define T0IE    3
+#define T0PR    4
+
+#define T1CR    _SFR_IO8(0x11)
+#define T1OTM   0
+#define T1CTM   1
+#define T1CRM   2
+#define T1TOP   4
+#define T1RES   5
+#define T1TOS   6
+#define T1ENA   7
+
+#define T2CR    _SFR_IO8(0x12)
+#define T2OTM   0
+#define T2CTM   1
+#define T2CRM   2
+#define T2TOP   4
+#define T2RES   5
+#define T2TOS   6
+#define T2ENA   7
+
+#define T3CR    _SFR_IO8(0x13)
+#define T3OTM   0
+#define T3CTM   1
+#define T3CRM   2
+#define T3CPRM  3
+#define T3TOP   4
+#define T3RES   5
+#define T3TOS   6
+#define T3ENA   7
+
+#define T4CR    _SFR_IO8(0x14)
+#define T4OTM   0
+#define T4CTM   1
+#define T4CRM   2
+#define T4CPRM  3
+#define T4TOP   4
+#define T4RES   5
+#define T4TOS   6
+#define T4ENA   7
+
+#define T1IFR   _SFR_IO8(0x15)
+#define T1OFF   0
+#define T1COF   1
+
+#define T2IFR   _SFR_IO8(0x16)
+#define T2OFF   0
+#define T2COF   1
+
+#define T3IFR   _SFR_IO8(0x17)
+#define T3OFF   0
+#define T3COF   1
+#define T3ICF   2
+
+#define T4IFR   _SFR_IO8(0x18)
+#define T4OFF   0
+#define T4COF   1
+#define T4ICF   2
+
+#define T5IFR   _SFR_IO8(0x19)
+#define T5OFF   0
+#define T5COF   1
+
+#define GPIOR0  _SFR_IO8(0x1A)
+
+#define GPIOR3  _SFR_IO8(0x1B)
+
+#define GPIOR4  _SFR_IO8(0x1C)
+
+#define GPIOR5  _SFR_IO8(0x1D)
+
+#define GPIOR6  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEWE    1
+#define EEMWE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+#define EEPAGE  6
+#define NVMBSY  7
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define EEPR    _SFR_IO8(0x23)
+#define EEAP0   0
+#define EEAP1   1
+#define EEAP2   2
+#define EEAP3   3
+
+#define GPIOR1  _SFR_IO8(0x24)
+
+#define GPIOR2  _SFR_IO8(0x25)
+
+#define PCICR   _SFR_IO8(0x26)
+#define PCIE0   0
+#define PCIE1   1
+
+#define EIMSK   _SFR_IO8(0x27)
+#define INT0    0
+#define INT1    1
+
+#define EIFR    _SFR_IO8(0x28)
+#define INTF0   0
+#define INTF1   1
+
+#define CRCDIR  _SFR_IO8(0x29)
+
+#define VMCSR   _SFR_IO8(0x2A)
+#define VMLS0   0
+#define VMLS1   1
+#define VMLS2   2
+#define VMLS3   3
+#define VMIM    4
+#define VMF     5
+
+#define MCUSR   _SFR_IO8(0x2B)
+#define PORF    0
+#define EXTRF   1
+#define WDRF    3
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define RXIF    4
+#define TXIF    5
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+#define T0IFR   _SFR_IO8(0x2F)
+#define T0F     0
+
+/* Reserved [0x30] */
+
+#define DWDR    _SFR_IO8(0x31)
+
+/* Reserved [0x32] */
+
+#define RDCR    _SFR_IO8(0x33)
+#define RDPU    0
+#define ADIVEN  1
+#define RDEN    2
+
+#define EOTSA   _SFR_IO8(0x34)
+#define CARFA   0
+#define AMPFA   1
+#define SYTFA   2
+#define MANFA   3
+#define TMOFA   4
+#define TELRA   5
+#define RRFA    6
+#define EOTBF   7
+
+#define EOTCA   _SFR_IO8(0x35)
+#define CARFEA  0
+#define AMPFEA  1
+#define SYTFEA  2
+#define MANFEA  3
+#define TMOFEA  4
+#define TELREA  5
+#define RRFEA   6
+#define EOTBFE  7
+
+#define EOTSB   _SFR_IO8(0x36)
+#define CARFB   0
+#define AMPFB   1
+#define SYTFB   2
+#define MANFB   3
+#define TMOFB   4
+#define TELRB   5
+#define RRFB    6
+#define EOTAF   7
+
+#define EOTCB   _SFR_IO8(0x37)
+#define CARFEB  0
+#define AMPFEB  1
+#define SYTFEB  2
+#define MANFEB  3
+#define TMOFEB  4
+#define TELREB  5
+#define RRFEB   6
+#define EOTAFE  7
+
+#define SMCR    _SFR_IO8(0x38)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define CMCR    _SFR_IO8(0x39)
+#define CMM0    0
+#define CMM1    1
+#define CMM2    2
+#define CCS     3
+#define SRCD    4
+#define CMONEN  6
+#define CMCCE   7
+
+#define CMIMR   _SFR_IO8(0x3A)
+#define ECIE    0
+
+#define CLPR    _SFR_IO8(0x3B)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLTPS0  3
+#define CLTPS1  4
+#define CLTPS2  5
+#define CLPCE   7
+
+#define SPMCSR  _SFR_IO8(0x3C)
+#define SELFPRGEN 0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define SPMIE   7
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define FSEN    _SFR_MEM8(0x60)
+#define SDPU    0
+#define SDEN    1
+#define GAEN    2
+#define PEEN    3
+#define ASEN    4
+#define ANTT    5
+
+#define FSFCR   _SFR_MEM8(0x61)
+#define BTSEL0  0
+#define BTSEL1  1
+#define ASDIV0  4
+#define ASDIV1  5
+#define ASDIV2  6
+#define ASDIV3  7
+
+/* Combine GACDIVL and GACDIVH */
+#define GACDIV  _SFR_MEM16(0x62)
+
+#define GACDIVL _SFR_MEM8(0x62)
+#define GACDIVH _SFR_MEM8(0x63)
+
+#define FFREQ1L _SFR_MEM8(0x64)
+
+#define FFREQ1M _SFR_MEM8(0x65)
+
+#define FFREQ1H _SFR_MEM8(0x66)
+
+#define FFREQ2L _SFR_MEM8(0x67)
+
+#define FFREQ2M _SFR_MEM8(0x68)
+
+#define FFREQ2H _SFR_MEM8(0x69)
+
+/* Reserved [0x6A] */
+
+#define EICRA   _SFR_MEM8(0x6B)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+
+#define PCMSK0  _SFR_MEM8(0x6C)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6D)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+
+#define WDTCR   _SFR_MEM8(0x6E)
+#define WDPS0   0
+#define WDPS1   1
+#define WDPS2   2
+#define WDE     3
+#define WDCE    4
+
+#define T1CNT   _SFR_MEM8(0x6F)
+
+#define T1COR   _SFR_MEM8(0x70)
+
+#define T1MR    _SFR_MEM8(0x71)
+#define T1CS0   0
+#define T1CS1   1
+#define T1PS0   2
+#define T1PS1   3
+#define T1PS2   4
+#define T1PS3   5
+#define T1DC0   6
+#define T1DC1   7
+
+#define T1IMR   _SFR_MEM8(0x72)
+#define T1OIM   0
+#define T1CIM   1
+
+#define T2CNT   _SFR_MEM8(0x73)
+
+#define T2COR   _SFR_MEM8(0x74)
+
+#define T2MR    _SFR_MEM8(0x75)
+#define T2CS0   0
+#define T2CS1   1
+#define T2PS0   2
+#define T2PS1   3
+#define T2PS2   4
+#define T2PS3   5
+#define T2DC0   6
+#define T2DC1   7
+
+#define T2IMR   _SFR_MEM8(0x76)
+#define T2OIM   0
+#define T2CIM   1
+
+/* Combine T3CNTL and T3CNTH */
+#define T3CNT   _SFR_MEM16(0x77)
+
+#define T3CNTL  _SFR_MEM8(0x77)
+#define T3CNTH  _SFR_MEM8(0x78)
+
+/* Combine T3CORL and T3CORH */
+#define T3COR   _SFR_MEM16(0x79)
+
+#define T3CORL  _SFR_MEM8(0x79)
+#define T3CORH  _SFR_MEM8(0x7A)
+
+/* Combine T3ICRL and T3ICRH */
+#define T3ICR   _SFR_MEM16(0x7B)
+
+#define T3ICRL  _SFR_MEM8(0x7B)
+#define T3ICRH  _SFR_MEM8(0x7C)
+
+#define T3MRA   _SFR_MEM8(0x7D)
+#define T3CS0   0
+#define T3CS1   1
+#define T3PS0   2
+#define T3PS1   3
+#define T3PS2   4
+
+#define T3MRB   _SFR_MEM8(0x7E)
+#define T3SCE   1
+#define T3CNC   2
+#define T3CE0   3
+#define T3CE1   4
+#define T3ICS0  5
+#define T3ICS1  6
+#define T3ICS2  7
+
+#define T3IMR   _SFR_MEM8(0x7F)
+#define T3OIM   0
+#define T3CIM   1
+#define T3CPIM  2
+
+/* Combine T4CNTL and T4CNTH */
+#define T4CNT   _SFR_MEM16(0x80)
+
+#define T4CNTL  _SFR_MEM8(0x80)
+#define T4CNTH  _SFR_MEM8(0x81)
+
+/* Combine T4CORL and T4CORH */
+#define T4COR   _SFR_MEM16(0x82)
+
+#define T4CORL  _SFR_MEM8(0x82)
+#define T4CORH  _SFR_MEM8(0x83)
+
+/* Combine T4ICRL and T4ICRH */
+#define T4ICR   _SFR_MEM16(0x84)
+
+#define T4ICRL  _SFR_MEM8(0x84)
+#define T4ICRH  _SFR_MEM8(0x85)
+
+#define T4MRA   _SFR_MEM8(0x86)
+#define T4CS0   0
+#define T4CS1   1
+#define T4PS0   2
+#define T4PS1   3
+#define T4PS2   4
+
+#define T4MRB   _SFR_MEM8(0x87)
+#define T4SCE   1
+#define T4CNC   2
+#define T4CE0   3
+#define T4CE1   4
+#define T4ICS0  5
+#define T4ICS1  6
+#define T4ICS2  7
+
+#define T4IMR   _SFR_MEM8(0x88)
+#define T4OIM   0
+#define T4CIM   1
+#define T4CPIM  2
+
+/* Reserved [0x89] */
+
+/* Combine T5OCRL and T5OCRH */
+#define T5OCR   _SFR_MEM16(0x8A)
+
+#define T5OCRL  _SFR_MEM8(0x8A)
+#define T5OCRH  _SFR_MEM8(0x8B)
+
+#define T5CCR   _SFR_MEM8(0x8C)
+#define T5CS0   0
+#define T5CS1   1
+#define T5CS2   2
+#define T5CTC   3
+
+/* Combine T5CNTL and T5CNTH */
+#define T5CNT   _SFR_MEM16(0x8D)
+
+#define T5CNTL  _SFR_MEM8(0x8D)
+#define T5CNTH  _SFR_MEM8(0x8E)
+
+#define T5IMR   _SFR_MEM8(0x8F)
+#define T5OIM   0
+#define T5CIM   1
+
+#define GTCCR   _SFR_MEM8(0x90)
+#define PSR10   0
+#define TSM     7
+
+#define SOTSB   _SFR_MEM8(0x91)
+#define CAROB   0
+#define AMPOB   1
+#define SYTOB   2
+#define MANOB   3
+#define WUPOB   4
+#define SFIDOB  5
+#define RROB    6
+#define WCOAO   7
+
+#define SOTSA   _SFR_MEM8(0x92)
+#define CAROA   0
+#define AMPOA   1
+#define SYTOA   2
+#define MANOA   3
+#define WUPOA   4
+#define SFIDOA  5
+#define RROA    6
+#define WCOBO   7
+
+#define SOTCB   _SFR_MEM8(0x93)
+#define CAROEB  0
+#define AMPOEB  1
+#define SYTOEB  2
+#define MANOEB  3
+#define WUPEB   4
+#define SFIDEB  5
+#define RROEB   6
+#define WCOAOE  7
+
+#define SOTCA   _SFR_MEM8(0x94)
+#define CAROEA  0
+#define AMPOEA  1
+#define SYTOEA  2
+#define MANOEA  3
+#define WUPEA   4
+#define SFIDEA  5
+#define RROEA   6
+#define WCOBOE  7
+
+#define TESRB   _SFR_MEM8(0x95)
+#define CRCOB   0
+#define EOTLB0  1
+#define EOTLB1  2
+
+#define TESRA   _SFR_MEM8(0x96)
+#define CRCOA   0
+#define EOTLA0  1
+#define EOTLA1  2
+
+/* Reserved [0x97] */
+
+#define RDSIMR  _SFR_MEM8(0x98)
+#define NBITAM  0
+#define NBITBM  1
+#define EOTAM   2
+#define EOTBM   3
+#define SOTAM   4
+#define SOTBM   5
+#define WCOAM   6
+#define WCOBM   7
+
+#define RDOCR   _SFR_MEM8(0x99)
+#define TMDS0   1
+#define TMDS1   2
+#define ETRPA   3
+#define ETRPB   4
+#define RDSIDA  5
+#define RDSIDB  6
+
+/* Reserved [0x9A] */
+
+#define TEMPL   _SFR_MEM8(0x9B)
+
+#define TEMPH   _SFR_MEM8(0x9C)
+
+#define SYCB    _SFR_MEM8(0x9D)
+#define SYCSB0  0
+#define SYCSB1  1
+#define SYCSB2  2
+#define SYCSB3  3
+#define SYTLB0  4
+#define SYTLB1  5
+#define SYTLB2  6
+#define SYTLB3  7
+
+#define SYCA    _SFR_MEM8(0x9E)
+#define SYCSA0  0
+#define SYCSA1  1
+#define SYCSA2  2
+#define SYCSA3  3
+#define SYTLA0  4
+#define SYTLA1  5
+#define SYTLA2  6
+#define SYTLA3  7
+
+#define RXFOB   _SFR_MEM8(0x9F)
+
+#define RXFOA   _SFR_MEM8(0xA0)
+
+#define DMMB    _SFR_MEM8(0xA1)
+#define DMATB0  0
+#define DMATB1  1
+#define DMATB2  2
+#define DMATB3  3
+#define DMATB4  4
+#define DMPB    5
+#define DMHB    6
+#define DMNEB   7
+
+#define DMMA    _SFR_MEM8(0xA2)
+#define DMATA0  0
+#define DMATA1  1
+#define DMATA2  2
+#define DMATA3  3
+#define DMATA4  4
+#define DMPA    5
+#define DMHA    6
+#define DMNEA   7
+
+#define DMCDB   _SFR_MEM8(0xA3)
+#define DMCLB0  0
+#define DMCLB1  1
+#define DMCLB2  2
+#define DMCLB3  3
+#define DMCLB4  4
+#define DMCTB0  5
+#define DMCTB1  6
+#define DMCTB2  7
+
+#define DMCDA   _SFR_MEM8(0xA4)
+#define DMCLA0  0
+#define DMCLA1  1
+#define DMCLA2  2
+#define DMCLA3  3
+#define DMCLA4  4
+#define DMCTA0  5
+#define DMCTA1  6
+#define DMCTA2  7
+
+#define DMCRB   _SFR_MEM8(0xA5)
+#define DMPGB0  0
+#define DMPGB1  1
+#define DMPGB2  2
+#define DMPGB3  3
+#define DMPGB4  4
+#define SASKB   5
+#define SY1TB   6
+#define DMARB   7
+
+#define DMCRA   _SFR_MEM8(0xA6)
+#define DMPGA0  0
+#define DMPGA1  1
+#define DMPGA2  2
+#define DMPGA3  3
+#define DMPGA4  4
+#define SASKA   5
+#define SY1TA   6
+#define DMARA   7
+
+#define DMDRB   _SFR_MEM8(0xA7)
+#define DMAB0   0
+#define DMAB1   1
+#define DMAB2   2
+#define DMAB3   3
+#define DMDNB0  4
+#define DMDNB1  5
+#define DMDNB2  6
+#define DMDNB3  7
+
+#define DMDRA   _SFR_MEM8(0xA8)
+#define DMAA0   0
+#define DMAA1   1
+#define DMAA2   2
+#define DMAA3   3
+#define DMDNA0  4
+#define DMDNA1  5
+#define DMDNA2  6
+#define DMDNA3  7
+
+#define CHCR    _SFR_MEM8(0xA9)
+#define BWM0    0
+#define BWM1    1
+#define BWM2    2
+#define BWM3    3
+
+#define CHDN    _SFR_MEM8(0xAA)
+#define BBDN0   0
+#define BBDN1   1
+#define BBDN2   2
+#define BBDN3   3
+#define BBDN4   4
+#define ADCDN   5
+
+#define SFIDCB  _SFR_MEM8(0xAB)
+#define SFIDTB0 0
+#define SFIDTB1 1
+#define SFIDTB2 2
+#define SFIDTB3 3
+#define SFIDTB4 4
+#define SEMEB   7
+
+#define SFIDLB  _SFR_MEM8(0xAC)
+#define SFIDLB0 0
+#define SFIDLB1 1
+#define SFIDLB2 2
+#define SFIDLB3 3
+#define SFIDLB4 4
+#define SFIDLB5 5
+
+#define WUPTB   _SFR_MEM8(0xAD)
+#define WUPTB0  0
+#define WUPTB1  1
+#define WUPTB2  2
+#define WUPTB3  3
+#define WUPTB4  4
+
+#define WUPLB   _SFR_MEM8(0xAE)
+#define WUPLB0  0
+#define WUPLB1  1
+#define WUPLB2  2
+#define WUPLB3  3
+#define WUPLB4  4
+#define WUPLB5  5
+
+#define SFID1B  _SFR_MEM8(0xAF)
+
+#define SFID2B  _SFR_MEM8(0xB0)
+
+#define SFID3B  _SFR_MEM8(0xB1)
+
+#define SFID4B  _SFR_MEM8(0xB2)
+
+#define WUP1B   _SFR_MEM8(0xB3)
+
+#define WUP2B   _SFR_MEM8(0xB4)
+
+#define WUP3B   _SFR_MEM8(0xB5)
+
+#define WUP4B   _SFR_MEM8(0xB6)
+
+#define SFIDCA  _SFR_MEM8(0xB7)
+#define SFIDTA0 0
+#define SFIDTA1 1
+#define SFIDTA2 2
+#define SFIDTA3 3
+#define SFIDTA4 4
+#define SEMEA   7
+
+#define SFIDLA  _SFR_MEM8(0xB8)
+#define SFIDLA0 0
+#define SFIDLA1 1
+#define SFIDLA2 2
+#define SFIDLA3 3
+#define SFIDLA4 4
+#define SFIDLA5 5
+
+#define WUPTA   _SFR_MEM8(0xB9)
+#define WUPTA0  0
+#define WUPTA1  1
+#define WUPTA2  2
+#define WUPTA3  3
+#define WUPTA4  4
+
+#define WUPLA   _SFR_MEM8(0xBA)
+#define WUPLA0  0
+#define WUPLA1  1
+#define WUPLA2  2
+#define WUPLA3  3
+#define WUPLA4  4
+#define WUPLA5  5
+
+#define SFID1A  _SFR_MEM8(0xBB)
+
+#define SFID2A  _SFR_MEM8(0xBC)
+
+#define SFID3A  _SFR_MEM8(0xBD)
+
+#define SFID4A  _SFR_MEM8(0xBE)
+
+#define WUP1A   _SFR_MEM8(0xBF)
+
+#define WUP2A   _SFR_MEM8(0xC0)
+
+#define WUP3A   _SFR_MEM8(0xC1)
+
+#define WUP4A   _SFR_MEM8(0xC2)
+
+#define CLKOD   _SFR_MEM8(0xC3)
+
+#define CLKOCR  _SFR_MEM8(0xC4)
+#define CLKOS0  0
+#define CLKOS1  1
+#define CLKOEN  2
+
+#define XFUSE   _SFR_MEM8(0xC5)
+
+#define SRCCAL  _SFR_MEM8(0xC6)
+#define SRCCAL0 0
+#define SRCCAL1 1
+#define SRCCAL2 2
+#define SRCCAL3 3
+#define SRCCAL4 4
+#define SRCCAL5 5
+#define SRCTC0  6
+#define SRCTC1  7
+
+#define FRCCAL  _SFR_MEM8(0xC7)
+#define FRCCAL0 0
+#define FRCCAL1 1
+#define FRCCAL2 2
+#define FRCCAL3 3
+#define FRCCAL4 4
+#define FRCTC   5
+
+#define CMSR    _SFR_MEM8(0xC8)
+#define ECF     0
+
+#define CMOCR   _SFR_MEM8(0xC9)
+#define FRCAO   0
+#define SRCAO   1
+#define FRCACT  2
+#define SRCACT  3
+
+#define SUPFR   _SFR_MEM8(0xCA)
+#define AVCCRF  0
+#define AVCCLF  1
+
+#define SUPCR   _SFR_MEM8(0xCB)
+#define AVCCRM  0
+#define AVCCLM  1
+#define PVEN    2
+#define DVDIS   4
+#define AVEN    5
+#define AVDIC   6
+
+#define SUPCA1  _SFR_MEM8(0xCC)
+#define PV22    2
+#define PVDIC   3
+#define PVCAL0  4
+#define PVCAL1  5
+#define PVCAL2  6
+#define PVCAL3  7
+
+#define SUPCA2  _SFR_MEM8(0xCD)
+#define BGCAL0  0
+#define BGCAL1  1
+#define BGCAL2  2
+#define BGCAL3  3
+
+#define SUPCA3  _SFR_MEM8(0xCE)
+#define ACAL4   0
+#define ACAL5   1
+#define ACAL6   2
+#define ACAL7   3
+#define DCAL4   4
+#define DCAL5   5
+#define DCAL6   6
+
+#define SUPCA4  _SFR_MEM8(0xCF)
+#define ACAL0   0
+#define ACAL1   1
+#define ACAL2   2
+#define ACAL3   3
+#define DCAL0   4
+#define DCAL1   5
+#define DCAL2   6
+#define DCAL3   7
+
+#define CALRDY  _SFR_MEM8(0xD0)
+
+#define VMCAL   _SFR_MEM8(0xD1)
+#define VMCAL0  0
+#define VMCAL1  1
+#define VMCAL2  2
+
+#define DFS     _SFR_MEM8(0xD2)
+#define DFFLRF  0
+#define DFUFL   1
+#define DFOFL   2
+
+/* Combine DFTLL and DFTLH */
+#define DFTL    _SFR_MEM16(0xD3)
+
+#define DFTLL   _SFR_MEM8(0xD3)
+#define DFTLH   _SFR_MEM8(0xD4)
+
+#define DFL     _SFR_MEM8(0xD5)
+#define DFFLS0  0
+#define DFFLS1  1
+#define DFFLS2  2
+#define DFFLS3  3
+#define DFFLS4  4
+#define DFFLS5  5
+#define DFCLR   7
+
+#define DFWP    _SFR_MEM8(0xD6)
+#define DFWP0   0
+#define DFWP1   1
+#define DFWP2   2
+#define DFWP3   3
+#define DFWP4   4
+#define DFWP5   5
+
+#define DFRP    _SFR_MEM8(0xD7)
+#define DFRP0   0
+#define DFRP1   1
+#define DFRP2   2
+#define DFRP3   3
+#define DFRP4   4
+#define DFRP5   5
+
+#define DFD     _SFR_MEM8(0xD8)
+
+#define DFI     _SFR_MEM8(0xD9)
+#define DFFLIM  0
+#define DFERIM  1
+
+#define DFC     _SFR_MEM8(0xDA)
+#define DFFLC0  0
+#define DFFLC1  1
+#define DFFLC2  2
+#define DFFLC3  3
+#define DFFLC4  4
+#define DFFLC5  5
+#define DFDRA   7
+
+#define SFS     _SFR_MEM8(0xDB)
+#define SFFLRF  0
+#define SFUFL   1
+#define SFOFL   2
+
+#define SFL     _SFR_MEM8(0xDC)
+#define SFFLS0  0
+#define SFFLS1  1
+#define SFFLS2  2
+#define SFFLS3  3
+#define SFFLS4  4
+#define SFCLR   7
+
+#define SFWP    _SFR_MEM8(0xDD)
+#define SFWP0   0
+#define SFWP1   1
+#define SFWP2   2
+#define SFWP3   3
+#define SFWP4   4
+
+#define SFRP    _SFR_MEM8(0xDE)
+#define SFRP0   0
+#define SFRP1   1
+#define SFRP2   2
+#define SFRP3   3
+#define SFRP4   4
+
+#define SFD     _SFR_MEM8(0xDF)
+
+#define SFI     _SFR_MEM8(0xE0)
+#define SFFLIM  0
+#define SFERIM  1
+
+#define SFC     _SFR_MEM8(0xE1)
+#define SFFLC0  0
+#define SFFLC1  1
+#define SFFLC2  2
+#define SFFLC3  3
+#define SFFLC4  4
+#define SFDRA   7
+
+#define SSMCR   _SFR_MEM8(0xE2)
+#define SSMTX   0
+#define SSMTM   1
+#define SSMTGE  2
+#define SSMTPE  3
+#define SSMPVE  4
+#define SSMTAE  5
+#define SETRPA  6
+#define SETRPB  7
+
+#define SSMRCR  _SFR_MEM8(0xE3)
+#define SSMPA   0
+#define SSMPB   1
+#define SSMADA  2
+#define SSMADB  3
+#define SSMPVS  4
+#define SSMIFA  5
+#define SSMIDSE 6
+#define SSMTMOE 7
+
+#define SSMFBR  _SFR_MEM8(0xE4)
+#define SSMFID0 0
+#define SSMFID1 1
+#define SSMFID2 2
+#define SSMDFDT 3
+#define SSMHADT 4
+#define SSMPLDT 5
+
+#define SSMRR   _SFR_MEM8(0xE5)
+#define SSMR    0
+#define SSMST   1
+
+#define SSMSR   _SFR_MEM8(0xE6)
+#define SSMESM0 0
+#define SSMESM1 1
+#define SSMESM2 2
+#define SSMESM3 3
+#define SSMERR  7
+
+#define SSMIFR  _SFR_MEM8(0xE7)
+#define SSMIF   0
+
+#define SSMIMR  _SFR_MEM8(0xE8)
+#define SSMIM   0
+
+#define MSMSTR  _SFR_MEM8(0xE9)
+#define SSMMST0 0
+#define SSMMST1 1
+#define SSMMST2 2
+#define SSMMST3 3
+#define SSMMST4 4
+
+#define SSMSTR  _SFR_MEM8(0xEA)
+#define SSMSTA0 0
+#define SSMSTA1 1
+#define SSMSTA2 2
+#define SSMSTA3 3
+#define SSMSTA4 4
+#define SSMSTA5 5
+
+#define SSMXSR  _SFR_MEM8(0xEB)
+#define SSMSTB0 0
+#define SSMSTB1 1
+#define SSMSTB2 2
+#define SSMSTB3 3
+#define SSMSTB4 4
+#define SSMSTB5 5
+
+#define MSMCR1  _SFR_MEM8(0xEC)
+#define MSMSM00 0
+#define MSMSM01 1
+#define MSMSM02 2
+#define MSMSM03 3
+#define MSMSM10 4
+#define MSMSM11 5
+#define MSMSM12 6
+#define MSMSM13 7
+
+#define MSMCR2  _SFR_MEM8(0xED)
+#define MSMSM20 0
+#define MSMSM21 1
+#define MSMSM22 2
+#define MSMSM23 3
+#define MSMSM30 4
+#define MSMSM31 5
+#define MSMSM32 6
+#define MSMSM33 7
+
+#define MSMCR3  _SFR_MEM8(0xEE)
+#define MSMSM40 0
+#define MSMSM41 1
+#define MSMSM42 2
+#define MSMSM43 3
+#define MSMSM50 4
+#define MSMSM51 5
+#define MSMSM52 6
+#define MSMSM53 7
+
+#define MSMCR4  _SFR_MEM8(0xEF)
+#define MSMSM60 0
+#define MSMSM61 1
+#define MSMSM62 2
+#define MSMSM63 3
+#define MSMSM70 4
+#define MSMSM71 5
+#define MSMSM72 6
+#define MSMSM73 7
+
+#define GTCR    _SFR_MEM8(0xF0)
+#define RXTEHA  0
+#define GAPMA   1
+#define DARA    2
+#define IWUPA   3
+#define RXTEHB  4
+#define GAPMB   5
+#define DARB    6
+#define IWUPB   7
+
+#define SOTC1A  _SFR_MEM8(0xF1)
+#define CAROEA1 0
+#define AMPOEA1 1
+#define SYTOEA1 2
+#define MANOEA1 3
+#define WUPEA1  4
+#define SFIDEA1 5
+#define RROEA1  6
+#define WCOBOE1 7
+
+#define SOTC2A  _SFR_MEM8(0xF2)
+#define CAROEA2 0
+#define AMPOEA2 1
+#define SYTOEA2 2
+#define MANOEA2 3
+#define WUPEA2  4
+#define SFIDEA2 5
+#define RROEA2  6
+#define WCOBOE2 7
+
+#define SOTC1B  _SFR_MEM8(0xF3)
+#define CAROEB1 0
+#define AMPOEB1 1
+#define SYTOEB1 2
+#define MANOEB1 3
+#define WUPEB1  4
+#define SFIDEB1 5
+#define RROEB1  6
+#define WCOAOE1 7
+
+#define SOTC2B  _SFR_MEM8(0xF4)
+#define CAROEB2 0
+#define AMPOEB2 1
+#define SYTOEB2 2
+#define MANOEB2 3
+#define WUPEB2  4
+#define SFIDEB2 5
+#define RROEB2  6
+#define WCOAOE2 7
+
+#define EOTC1A  _SFR_MEM8(0xF5)
+#define CARFEA1 0
+#define AMPFEA1 1
+#define SYTFEA1 2
+#define MANFEA1 3
+#define TMOFEA1 4
+#define TELREA1 5
+#define RRFEA1  6
+#define EOTBFE1 7
+
+#define EOTC2A  _SFR_MEM8(0xF6)
+#define CARFEA2 0
+#define AMPFEA2 1
+#define SYTFEA2 2
+#define MANFEA2 3
+#define TMOFEA2 4
+#define TELREA2 5
+#define RRFEA2  6
+#define EOTBFE2 7
+
+#define EOTC3A  _SFR_MEM8(0xF7)
+#define CARFEA3 0
+#define AMPFEA3 1
+#define SYTFEA3 2
+#define MANFEA3 3
+#define TMOFEA3 4
+#define TELREA3 5
+#define RRFEA3  6
+#define EOTBFE3 7
+
+#define EOTC1B  _SFR_MEM8(0xF8)
+#define CARFEB1 0
+#define AMPFEB1 1
+#define SYTFEB1 2
+#define MANFEB1 3
+#define TMOFEB1 4
+#define TELREB1 5
+#define RRFEB1  6
+#define EOTAFE1 7
+
+#define EOTC2B  _SFR_MEM8(0xF9)
+#define CARFEB2 0
+#define AMPFEB2 1
+#define SYTFEB2 2
+#define MANFEB2 3
+#define TMOFEB2 4
+#define TELREB2 5
+#define RRFEB2  6
+#define EOTAFE2 7
+
+#define EOTC3B  _SFR_MEM8(0xFA)
+#define CARFEB3 0
+#define AMPFEB3 1
+#define SYTFEB3 2
+#define MANFEB3 3
+#define TMOFEB3 4
+#define TELREB3 5
+#define RRFEB3  6
+#define EOTAFE3 7
+
+#define WCOTOA  _SFR_MEM8(0xFB)
+
+#define WCOTOB  _SFR_MEM8(0xFC)
+
+#define SOTTOA  _SFR_MEM8(0xFD)
+
+#define SOTTOB  _SFR_MEM8(0xFE)
+
+#define SSMFCR  _SFR_MEM8(0xFF)
+#define SSMIDSO 0
+#define SSMIDSF 1
+
+#define FESR    _SFR_MEM8(0x100)
+#define LBSAT   0
+#define HBSAT   1
+#define XRDY    2
+#define PLCK    3
+#define ANTS    4
+
+#define FEEN1   _SFR_MEM8(0x101)
+#define PLEN    0
+#define PLCAL   1
+#define XTOEN   2
+#define LNAEN   3
+#define ADEN    4
+#define ADCLK   5
+#define PLSP1   6
+#define ATEN    7
+
+#define FEEN2   _SFR_MEM8(0x102)
+#define SDRX    0
+#define SDTX    1
+#define PAEN    2
+#define TMPM    3
+#define PLPEN   4
+#define XTPEN   5
+#define CPBIA   6
+
+#define FELNA   _SFR_MEM8(0x103)
+#define LBH0    0
+#define LBH1    1
+#define LBH2    2
+#define LBH3    3
+#define LBL0    4
+#define LBL1    5
+#define LBL2    6
+#define LBL3    7
+
+#define FEAT    _SFR_MEM8(0x104)
+#define ANTN0   0
+#define ANTN1   1
+#define ANTN2   2
+#define ANTN3   3
+
+#define FEPAC   _SFR_MEM8(0x105)
+
+#define FEVCT   _SFR_MEM8(0x106)
+#define FEVCT0  0
+#define FEVCT1  1
+#define FEVCT2  2
+#define FEVCT3  3
+
+#define FEBT    _SFR_MEM8(0x107)
+#define CTN20   0
+#define CTN21   1
+#define RTN20   2
+#define RTN21   3
+
+#define FEMS    _SFR_MEM8(0x108)
+#define PLLS0   0
+#define PLLS1   1
+#define PLLS2   2
+#define PLLS3   3
+#define PLLM0   4
+#define PLLM1   5
+#define PLLM2   6
+#define PLLM3   7
+
+#define FETN4   _SFR_MEM8(0x109)
+#define CTN40   0
+#define CTN41   1
+#define CTN42   2
+#define CTN43   3
+#define RTN40   4
+#define RTN41   5
+#define RTN42   6
+#define RTN43   7
+
+#define FECR    _SFR_MEM8(0x10A)
+#define LBNHB   0
+#define S4N3    1
+#define ANDP    2
+#define ADHS    3
+#define PLCKG   4
+#define ANPS    5
+
+#define FEVCO   _SFR_MEM8(0x10B)
+#define CPCC0   0
+#define CPCC1   1
+#define CPCC2   2
+#define CPCC3   3
+#define VCOB0   4
+#define VCOB1   5
+#define VCOB2   6
+#define VCOB3   7
+
+#define FEALR   _SFR_MEM8(0x10C)
+#define RNGE0   0
+#define RNGE1   1
+
+#define FEANT   _SFR_MEM8(0x10D)
+#define LVLC0   0
+#define LVLC1   1
+#define LVLC2   2
+#define LVLC3   3
+
+#define FEBIA   _SFR_MEM8(0x10E)
+#define IFAEN   7
+
+/* Reserved [0x10F..0x11F] */
+
+#define TMFSM   _SFR_MEM8(0x120)
+#define TMSSM0  0
+#define TMSSM1  1
+#define TMSSM2  2
+#define TMSSM3  3
+#define TMMSM0  4
+#define TMMSM1  5
+#define TMMSM2  6
+
+/* Combine TMCRL and TMCRH */
+#define TMCR    _SFR_MEM16(0x121)
+
+#define TMCRL   _SFR_MEM8(0x121)
+#define TMCRH   _SFR_MEM8(0x122)
+
+#define TMCSB   _SFR_MEM8(0x123)
+
+/* Combine TMCIL and TMCIH */
+#define TMCI    _SFR_MEM16(0x124)
+
+#define TMCIL   _SFR_MEM8(0x124)
+#define TMCIH   _SFR_MEM8(0x125)
+
+/* Combine TMCPL and TMCPH */
+#define TMCP    _SFR_MEM16(0x126)
+
+#define TMCPL   _SFR_MEM8(0x126)
+#define TMCPH   _SFR_MEM8(0x127)
+
+#define TMSHR   _SFR_MEM8(0x128)
+
+/* Combine TMTLL and TMTLH */
+#define TMTL    _SFR_MEM16(0x129)
+
+#define TMTLL   _SFR_MEM8(0x129)
+#define TMTLH   _SFR_MEM8(0x12A)
+
+#define TMSSC   _SFR_MEM8(0x12B)
+#define TMSSP0  0
+#define TMSSP1  1
+#define TMSSP2  2
+#define TMSSP3  3
+#define TMSSL0  4
+#define TMSSL1  5
+#define TMSSL2  6
+#define TMSSH   7
+
+#define TMSR    _SFR_MEM8(0x12C)
+#define TMTCF   0
+
+#define TMCR2   _SFR_MEM8(0x12D)
+#define TMCRCE  0
+#define TMCRCL0 1
+#define TMCRCL1 2
+#define TMNRZE  3
+#define TMPOL   4
+#define TMSSE   5
+#define TMMSB   6
+
+#define TMCR1   _SFR_MEM8(0x12E)
+#define TMPIS0  0
+#define TMPIS1  1
+#define TMPIS2  2
+#define TMSCS   3
+#define TMCIM   4
+
+#define RXBC1   _SFR_MEM8(0x12F)
+#define RXCEA   0
+#define RXCBLA0 1
+#define RXCBLA1 2
+#define RXMSBA  3
+#define RXCEB   4
+#define RXCBLB0 5
+#define RXCBLB1 6
+#define RXMSBB  7
+
+#define RXBC2   _SFR_MEM8(0x130)
+#define RXBPB   0
+#define RXBF    1
+#define RXBCLR  2
+
+#define RXTLLB  _SFR_MEM8(0x131)
+
+#define RXTLHB  _SFR_MEM8(0x132)
+#define RXTLHB0 0
+#define RXTLHB1 1
+#define RXTLHB2 2
+#define RXTLHB3 3
+
+#define RXCRLB  _SFR_MEM8(0x133)
+
+#define RXCRHB  _SFR_MEM8(0x134)
+
+#define RXCSBB  _SFR_MEM8(0x135)
+
+#define RXCILB  _SFR_MEM8(0x136)
+
+#define RXCIHB  _SFR_MEM8(0x137)
+
+#define RXCPLB  _SFR_MEM8(0x138)
+
+#define RXCPHB  _SFR_MEM8(0x139)
+
+#define RXDSB   _SFR_MEM8(0x13A)
+
+#define RXTLLA  _SFR_MEM8(0x13B)
+
+#define RXTLHA  _SFR_MEM8(0x13C)
+#define RXTLHA0 0
+#define RXTLHA1 1
+#define RXTLHA2 2
+#define RXTLHA3 3
+
+#define RXCRLA  _SFR_MEM8(0x13D)
+
+#define RXCRHA  _SFR_MEM8(0x13E)
+
+#define RXCSBA  _SFR_MEM8(0x13F)
+
+#define RXCILA  _SFR_MEM8(0x140)
+
+#define RXCIHA  _SFR_MEM8(0x141)
+
+#define RXCPLA  _SFR_MEM8(0x142)
+
+#define RXCPHA  _SFR_MEM8(0x143)
+
+#define RXDSA   _SFR_MEM8(0x144)
+
+#define CRCCR   _SFR_MEM8(0x145)
+#define CRCRS   0
+#define REFLI   1
+#define REFLO   2
+
+#define CRCDOR  _SFR_MEM8(0x146)
+
+#define IDB0    _SFR_MEM8(0x147)
+
+#define IDB1    _SFR_MEM8(0x148)
+
+#define IDB2    _SFR_MEM8(0x149)
+
+#define IDB3    _SFR_MEM8(0x14A)
+
+#define IDC     _SFR_MEM8(0x14B)
+#define IDL0    0
+#define IDL1    1
+#define IDBO0   2
+#define IDBO1   3
+#define IDFIM   5
+#define IDCLR   6
+#define IDCE    7
+
+#define IDS     _SFR_MEM8(0x14C)
+#define IDOK    0
+#define IDFULL  1
+
+#define RSSAV   _SFR_MEM8(0x14D)
+
+#define RSSPK   _SFR_MEM8(0x14E)
+
+#define RSSL    _SFR_MEM8(0x14F)
+
+#define RSSH    _SFR_MEM8(0x150)
+
+#define RSSC    _SFR_MEM8(0x151)
+#define RSUP0   0
+#define RSUP1   1
+#define RSUP2   2
+#define RSUP3   3
+#define RSWLH   4
+#define RSHRX   5
+#define RSPKF   6
+
+#define DBCR    _SFR_MEM8(0x152)
+#define DBMD    0
+#define DBCS    1
+#define DBTMS   2
+#define DBHA    3
+
+#define DBTC    _SFR_MEM8(0x153)
+
+#define DBENB   _SFR_MEM8(0x154)
+
+#define DBENC   _SFR_MEM8(0x155)
+
+#define DBGSW   _SFR_MEM8(0x156)
+#define DBGGS0  0
+#define DBGGS1  1
+#define DBGGS2  2
+#define DBGGS3  3
+#define CPBFOS0 4
+#define CPBFOS1 5
+#define CPBF    6
+#define DBGSE   7
+
+#define SFFR    _SFR_MEM8(0x157)
+#define RFL0    0
+#define RFL1    1
+#define RFL2    2
+#define RFC     3
+#define TFL0    4
+#define TFL1    5
+#define TFL2    6
+#define TFC     7
+
+#define SFIR    _SFR_MEM8(0x158)
+#define RIL0    0
+#define RIL1    1
+#define RIL2    2
+#define SRIE    3
+#define TIL0    4
+#define TIL1    5
+#define TIL2    6
+#define STIE    7
+
+#define EECR2   _SFR_MEM8(0x159)
+#define EEBRE   0
+
+#define PGMST   _SFR_MEM8(0x15A)
+#define PGMSYN0 0
+#define PGMSYN1 1
+#define PGMSYN2 2
+#define PGMSYN3 3
+#define PGMSYN4 4
+
+#define EEST    _SFR_MEM8(0x15B)
+#define EESYN0  0
+#define EESYN1  1
+#define EESYN2  2
+#define EESYN3  3
+
+#define RSIFG   _SFR_MEM8(0x15C)
+
+#define RSLDV   _SFR_MEM8(0x15D)
+
+#define RSHDV   _SFR_MEM8(0x15E)
+
+#define RSCOM   _SFR_MEM8(0x15F)
+#define RSDC    0
+#define RSIFC   1
+
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
+
+/* External Interrupt Request 1 */
+#define INT1_vect            _VECTOR(2)
+#define INT1_vect_num        2
+
+/* Pin Change Interrupt Request 0 */
+#define PCI0_vect            _VECTOR(3)
+#define PCI0_vect_num        3
+
+/* Pin Change Interrupt Request 1 */
+#define PCI1_vect            _VECTOR(4)
+#define PCI1_vect_num        4
+
+/* Voltage Monitoring Interrupt */
+#define VMON_vect            _VECTOR(5)
+#define VMON_vect_num        5
+
+/* AVCC Reset Interrupt */
+#define AVCCR_vect            _VECTOR(6)
+#define AVCCR_vect_num        6
+
+/* AVCC Low Interrupt */
+#define AVCCL_vect            _VECTOR(7)
+#define AVCCL_vect_num        7
+
+/* Timer 0 Interval Interrupt */
+#define T0INT_vect            _VECTOR(8)
+#define T0INT_vect_num        8
+
+/* Timer/Counter1 Compare Match Interrupt */
+#define T1COMP_vect            _VECTOR(9)
+#define T1COMP_vect_num        9
+
+/* Timer/Counter1 Overflow Interrupt */
+#define T1OVF_vect            _VECTOR(10)
+#define T1OVF_vect_num        10
+
+/* Timer/Counter2 Compare Match Interrupt */
+#define T2COMP_vect            _VECTOR(11)
+#define T2COMP_vect_num        11
+
+/* Timer/Counter2 Overflow Interrupt */
+#define T2OVF_vect            _VECTOR(12)
+#define T2OVF_vect_num        12
+
+/* Timer/Counter3 Capture Event Interrupt */
+#define T3CAP_vect            _VECTOR(13)
+#define T3CAP_vect_num        13
+
+/* Timer/Counter3 Compare Match Interrupt */
+#define T3COMP_vect            _VECTOR(14)
+#define T3COMP_vect_num        14
+
+/* Timer/Counter3 Overflow Interrupt */
+#define T3OVF_vect            _VECTOR(15)
+#define T3OVF_vect_num        15
+
+/* Timer/Counter4 Capture Event Interrupt */
+#define T4CAP_vect            _VECTOR(16)
+#define T4CAP_vect_num        16
+
+/* Timer/Counter4 Compare Match Interrupt */
+#define T4COMP_vect            _VECTOR(17)
+#define T4COMP_vect_num        17
+
+/* Timer/Counter4 Overflow Interrupt */
+#define T4OVF_vect            _VECTOR(18)
+#define T4OVF_vect_num        18
+
+/* Timer/Counter5 Compare Match Interrupt */
+#define T5COMP_vect            _VECTOR(19)
+#define T5COMP_vect_num        19
+
+/* Timer/Counter5 Overflow Interrupt */
+#define T5OVF_vect            _VECTOR(20)
+#define T5OVF_vect_num        20
+
+/* SPI Serial Transfer Complete Interrupt */
+#define SPI_vect            _VECTOR(21)
+#define SPI_vect_num        21
+
+/* SPI Rx Buffer Interrupt */
+#define SRX_FIFO_vect            _VECTOR(22)
+#define SRX_FIFO_vect_num        22
+
+/* SPI Tx Buffer Interrupt */
+#define STX_FIFO_vect            _VECTOR(23)
+#define STX_FIFO_vect_num        23
+
+/* Sequencer State Machine Interrupt */
+#define SSM_vect            _VECTOR(24)
+#define SSM_vect_num        24
+
+/* Data FIFO fill level reached Interrupt */
+#define DFFLR_vect            _VECTOR(25)
+#define DFFLR_vect_num        25
+
+/* Data FIFO overflow or underflow error Interrupt */
+#define DFOUE_vect            _VECTOR(26)
+#define DFOUE_vect_num        26
+
+/* RSSI/Preamble FIFO fill level reached Interrupt */
+#define SFFLR_vect            _VECTOR(27)
+#define SFFLR_vect_num        27
+
+/* RSSI/Preamble FIFO overflow or underflow error Interrupt */
+#define SFOUE_vect            _VECTOR(28)
+#define SFOUE_vect_num        28
+
+/* Tx Modulator Telegram Finish Interrupt */
+#define TMTCF_vect            _VECTOR(29)
+#define TMTCF_vect_num        29
+
+/* UHF receiver wake up ok on Rx path B */
+#define UHF_WCOB_vect            _VECTOR(30)
+#define UHF_WCOB_vect_num        30
+
+/* UHF receiver wake up ok on Rx path A */
+#define UHF_WCOA_vect            _VECTOR(31)
+#define UHF_WCOA_vect_num        31
+
+/* UHF receiver start of telegram ok on Rx path B */
+#define UHF_SOTB_vect            _VECTOR(32)
+#define UHF_SOTB_vect_num        32
+
+/* UHF receiver start of telegram ok on Rx path A */
+#define UHF_SOTA_vect            _VECTOR(33)
+#define UHF_SOTA_vect_num        33
+
+/* UHF receiver end of telegram on Rx path B */
+#define UHF_EOTB_vect            _VECTOR(34)
+#define UHF_EOTB_vect_num        34
+
+/* UHF receiver end of telegram on Rx path A */
+#define UHF_EOTA_vect            _VECTOR(35)
+#define UHF_EOTA_vect_num        35
+
+/* UHF receiver new bit on Rx path B */
+#define UHF_NBITB_vect            _VECTOR(36)
+#define UHF_NBITB_vect_num        36
+
+/* UHF receiver new bit on Rx path A */
+#define UHF_NBITA_vect            _VECTOR(37)
+#define UHF_NBITA_vect_num        37
+
+/* External input Clock monitoring Interrupt */
+#define EXCM_vect            _VECTOR(38)
+#define EXCM_vect_num        38
+
+/* EEPROM Ready Interrupt */
+#define ERDY_vect            _VECTOR(39)
+#define ERDY_vect_num        39
+
+/* Store Program Memory Ready */
+#define SPMR_vect            _VECTOR(40)
+#define SPMR_vect_num        40
+
+/* IDSCAN Full Interrupt */
+#define IDFULL_vect            _VECTOR(41)
+#define IDFULL_vect_num        41
+
+#define _VECTORS_SIZE 168
+
+
+/* Constants */
+
+#define SPM_PAGESIZE 64
+#define FLASHSTART   0x8000
+#define FLASHEND     0xCFFF
+#define RAMSTART     0x0200
+#define RAMSIZE      1024
+#define RAMEND       0x05FF
+#define E2START     0
+#define E2SIZE      1152
+#define E2PAGESIZE  16
+#define E2END       0x047F
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 1
+
+/* Fuse Byte */
+#define FUSE_CKDIV8 (unsigned char)~_BV(128)
+#define FUSE_DWEN (unsigned char)~_BV(64)
+#define FUSE_SPIEN (unsigned char)~_BV(32)
+#define FUSE_WDTON (unsigned char)~_BV(16)
+#define FUSE_EESAVE (unsigned char)~_BV(8)
+#define FUSE_BOOTRST (unsigned char)~_BV(4)
+#define FUSE_RSTDISBL (unsigned char)~_BV(2)
+#define FUSE_EXTCLKEN (unsigned char)~_BV(1)
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x95
+#define SIGNATURE_2 0x61
+
+
+#endif /* #ifdef _AVR_ATA5831_H_INCLUDED */
+
diff -urN avr-libc-1.8.0.orig/include/avr/ioa5832.h avr-libc-1.8.0/include/avr/ioa5832.h
--- avr-libc-1.8.0.orig/include/avr/ioa5832.h	1970-01-01 01:00:00.000000000 +0100
+++ avr-libc-1.8.0/include/avr/ioa5832.h	2013-06-12 12:21:34.000000000 +0200
@@ -0,0 +1,1891 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2013 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATA5832_H_INCLUDED
+#define _AVR_ATA5832_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "ioa5832.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PRR0    _SFR_IO8(0x01)
+#define PRSPI   0
+#define PRRXDC  1
+#define PRTXDC  2
+#define PRCRC   3
+#define PRVM    4
+#define PRCO    5
+
+#define PRR1    _SFR_IO8(0x02)
+#define PRT1    0
+#define PRT2    1
+#define PRT3    2
+#define PRT4    3
+#define PRT5    4
+
+#define PRR2    _SFR_IO8(0x03)
+#define PRXB    0
+#define PRXA    1
+#define PRSF    2
+#define PRDF    3
+#define PRIDS   4
+#define PRRS    5
+#define PRTM    6
+#define PRSSM   7
+
+#define RDPR    _SFR_IO8(0x04)
+#define PRPTB   0
+#define PRPTA   1
+#define PRFLT   2
+#define PRTMP   3
+#define APRPTB  4
+#define APRPTA  5
+#define ARDPRF  6
+#define RDPRF   7
+
+#define PINB    _SFR_IO8(0x05)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x06)
+#define DDRB7   7
+#define DDRB6   6
+#define DDRB5   5
+#define DDRB4   4
+#define DDRB3   3
+#define DDRB2   2
+#define DDRB1   1
+#define DDRB0   0
+
+#define PORTB   _SFR_IO8(0x07)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINC    _SFR_IO8(0x08)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x09)
+#define DDRC7   7
+#define DDRC6   6
+#define DDRC5   5
+#define DDRC4   4
+#define DDRC3   3
+#define DDRC2   2
+#define DDRC1   1
+#define DDRC0   0
+
+#define PORTC   _SFR_IO8(0x0A)
+#define PORTC7  7
+#define PORTC6  6
+#define PORTC5  5
+#define PORTC4  4
+#define PORTC3  3
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+#define FSCR    _SFR_IO8(0x0B)
+#define TXMOD   0
+#define SFM     1
+#define TXMS0   2
+#define TXMS1   3
+#define PAOER   4
+#define PAON    7
+
+/* Reserved [0x0C] */
+
+#define RDSIFR  _SFR_IO8(0x0D)
+#define NBITA   0
+#define NBITB   1
+#define EOTA    2
+#define EOTB    3
+#define SOTA    4
+#define SOTB    5
+#define WCOA    6
+#define WCOB    7
+
+#define MCUCR   _SFR_IO8(0x0E)
+#define IVCE    0
+#define IVSEL   1
+#define SPIIO   2
+#define ENPS    3
+#define PUD     4
+#define PB4HS   5
+#define PB7LS   6
+#define PB7HS   7
+
+#define PCIFR   _SFR_IO8(0x0F)
+#define PCIF0   0
+#define PCIF1   1
+
+#define T0CR    _SFR_IO8(0x10)
+#define T0PS0   0
+#define T0PS1   1
+#define T0PS2   2
+#define T0IE    3
+#define T0PR    4
+
+#define T1CR    _SFR_IO8(0x11)
+#define T1OTM   0
+#define T1CTM   1
+#define T1CRM   2
+#define T1TOP   4
+#define T1RES   5
+#define T1TOS   6
+#define T1ENA   7
+
+#define T2CR    _SFR_IO8(0x12)
+#define T2OTM   0
+#define T2CTM   1
+#define T2CRM   2
+#define T2TOP   4
+#define T2RES   5
+#define T2TOS   6
+#define T2ENA   7
+
+#define T3CR    _SFR_IO8(0x13)
+#define T3OTM   0
+#define T3CTM   1
+#define T3CRM   2
+#define T3CPRM  3
+#define T3TOP   4
+#define T3RES   5
+#define T3TOS   6
+#define T3ENA   7
+
+#define T4CR    _SFR_IO8(0x14)
+#define T4OTM   0
+#define T4CTM   1
+#define T4CRM   2
+#define T4CPRM  3
+#define T4TOP   4
+#define T4RES   5
+#define T4TOS   6
+#define T4ENA   7
+
+#define T1IFR   _SFR_IO8(0x15)
+#define T1OFF   0
+#define T1COF   1
+
+#define T2IFR   _SFR_IO8(0x16)
+#define T2OFF   0
+#define T2COF   1
+
+#define T3IFR   _SFR_IO8(0x17)
+#define T3OFF   0
+#define T3COF   1
+#define T3ICF   2
+
+#define T4IFR   _SFR_IO8(0x18)
+#define T4OFF   0
+#define T4COF   1
+#define T4ICF   2
+
+#define T5IFR   _SFR_IO8(0x19)
+#define T5OFF   0
+#define T5COF   1
+
+#define GPIOR0  _SFR_IO8(0x1A)
+
+#define GPIOR3  _SFR_IO8(0x1B)
+
+#define GPIOR4  _SFR_IO8(0x1C)
+
+#define GPIOR5  _SFR_IO8(0x1D)
+
+#define GPIOR6  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEWE    1
+#define EEMWE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+#define EEPAGE  6
+#define NVMBSY  7
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define EEPR    _SFR_IO8(0x23)
+#define EEAP0   0
+#define EEAP1   1
+#define EEAP2   2
+#define EEAP3   3
+
+#define GPIOR1  _SFR_IO8(0x24)
+
+#define GPIOR2  _SFR_IO8(0x25)
+
+#define PCICR   _SFR_IO8(0x26)
+#define PCIE0   0
+#define PCIE1   1
+
+#define EIMSK   _SFR_IO8(0x27)
+#define INT0    0
+#define INT1    1
+
+#define EIFR    _SFR_IO8(0x28)
+#define INTF0   0
+#define INTF1   1
+
+#define CRCDIR  _SFR_IO8(0x29)
+
+#define VMCSR   _SFR_IO8(0x2A)
+#define VMLS0   0
+#define VMLS1   1
+#define VMLS2   2
+#define VMLS3   3
+#define VMIM    4
+#define VMF     5
+
+#define MCUSR   _SFR_IO8(0x2B)
+#define PORF    0
+#define EXTRF   1
+#define WDRF    3
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define RXIF    4
+#define TXIF    5
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+#define T0IFR   _SFR_IO8(0x2F)
+#define T0F     0
+
+/* Reserved [0x30] */
+
+#define DWDR    _SFR_IO8(0x31)
+
+/* Reserved [0x32] */
+
+#define RDCR    _SFR_IO8(0x33)
+#define RDPU    0
+#define ADIVEN  1
+#define RDEN    2
+
+#define EOTSA   _SFR_IO8(0x34)
+#define CARFA   0
+#define AMPFA   1
+#define SYTFA   2
+#define MANFA   3
+#define TMOFA   4
+#define TELRA   5
+#define RRFA    6
+#define EOTBF   7
+
+#define EOTCA   _SFR_IO8(0x35)
+#define CARFEA  0
+#define AMPFEA  1
+#define SYTFEA  2
+#define MANFEA  3
+#define TMOFEA  4
+#define TELREA  5
+#define RRFEA   6
+#define EOTBFE  7
+
+#define EOTSB   _SFR_IO8(0x36)
+#define CARFB   0
+#define AMPFB   1
+#define SYTFB   2
+#define MANFB   3
+#define TMOFB   4
+#define TELRB   5
+#define RRFB    6
+#define EOTAF   7
+
+#define EOTCB   _SFR_IO8(0x37)
+#define CARFEB  0
+#define AMPFEB  1
+#define SYTFEB  2
+#define MANFEB  3
+#define TMOFEB  4
+#define TELREB  5
+#define RRFEB   6
+#define EOTAFE  7
+
+#define SMCR    _SFR_IO8(0x38)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define CMCR    _SFR_IO8(0x39)
+#define CMM0    0
+#define CMM1    1
+#define CMM2    2
+#define CCS     3
+#define SRCD    4
+#define CMONEN  6
+#define CMCCE   7
+
+#define CMIMR   _SFR_IO8(0x3A)
+#define ECIE    0
+
+#define CLPR    _SFR_IO8(0x3B)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLTPS0  3
+#define CLTPS1  4
+#define CLTPS2  5
+#define CLPCE   7
+
+#define SPMCSR  _SFR_IO8(0x3C)
+#define SELFPRGEN 0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define SPMIE   7
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define FSEN    _SFR_MEM8(0x60)
+#define SDPU    0
+#define SDEN    1
+#define GAEN    2
+#define PEEN    3
+#define ASEN    4
+#define ANTT    5
+
+#define FSFCR   _SFR_MEM8(0x61)
+#define BTSEL0  0
+#define BTSEL1  1
+#define ASDIV0  4
+#define ASDIV1  5
+#define ASDIV2  6
+#define ASDIV3  7
+
+/* Combine GACDIVL and GACDIVH */
+#define GACDIV  _SFR_MEM16(0x62)
+
+#define GACDIVL _SFR_MEM8(0x62)
+#define GACDIVH _SFR_MEM8(0x63)
+
+#define FFREQ1L _SFR_MEM8(0x64)
+
+#define FFREQ1M _SFR_MEM8(0x65)
+
+#define FFREQ1H _SFR_MEM8(0x66)
+
+#define FFREQ2L _SFR_MEM8(0x67)
+
+#define FFREQ2M _SFR_MEM8(0x68)
+
+#define FFREQ2H _SFR_MEM8(0x69)
+
+/* Reserved [0x6A] */
+
+#define EICRA   _SFR_MEM8(0x6B)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+
+#define PCMSK0  _SFR_MEM8(0x6C)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6D)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+
+#define WDTCR   _SFR_MEM8(0x6E)
+#define WDPS0   0
+#define WDPS1   1
+#define WDPS2   2
+#define WDE     3
+#define WDCE    4
+
+#define T1CNT   _SFR_MEM8(0x6F)
+
+#define T1COR   _SFR_MEM8(0x70)
+
+#define T1MR    _SFR_MEM8(0x71)
+#define T1CS0   0
+#define T1CS1   1
+#define T1PS0   2
+#define T1PS1   3
+#define T1PS2   4
+#define T1PS3   5
+#define T1DC0   6
+#define T1DC1   7
+
+#define T1IMR   _SFR_MEM8(0x72)
+#define T1OIM   0
+#define T1CIM   1
+
+#define T2CNT   _SFR_MEM8(0x73)
+
+#define T2COR   _SFR_MEM8(0x74)
+
+#define T2MR    _SFR_MEM8(0x75)
+#define T2CS0   0
+#define T2CS1   1
+#define T2PS0   2
+#define T2PS1   3
+#define T2PS2   4
+#define T2PS3   5
+#define T2DC0   6
+#define T2DC1   7
+
+#define T2IMR   _SFR_MEM8(0x76)
+#define T2OIM   0
+#define T2CIM   1
+
+/* Combine T3CNTL and T3CNTH */
+#define T3CNT   _SFR_MEM16(0x77)
+
+#define T3CNTL  _SFR_MEM8(0x77)
+#define T3CNTH  _SFR_MEM8(0x78)
+
+/* Combine T3CORL and T3CORH */
+#define T3COR   _SFR_MEM16(0x79)
+
+#define T3CORL  _SFR_MEM8(0x79)
+#define T3CORH  _SFR_MEM8(0x7A)
+
+/* Combine T3ICRL and T3ICRH */
+#define T3ICR   _SFR_MEM16(0x7B)
+
+#define T3ICRL  _SFR_MEM8(0x7B)
+#define T3ICRH  _SFR_MEM8(0x7C)
+
+#define T3MRA   _SFR_MEM8(0x7D)
+#define T3CS0   0
+#define T3CS1   1
+#define T3PS0   2
+#define T3PS1   3
+#define T3PS2   4
+
+#define T3MRB   _SFR_MEM8(0x7E)
+#define T3SCE   1
+#define T3CNC   2
+#define T3CE0   3
+#define T3CE1   4
+#define T3ICS0  5
+#define T3ICS1  6
+#define T3ICS2  7
+
+#define T3IMR   _SFR_MEM8(0x7F)
+#define T3OIM   0
+#define T3CIM   1
+#define T3CPIM  2
+
+/* Combine T4CNTL and T4CNTH */
+#define T4CNT   _SFR_MEM16(0x80)
+
+#define T4CNTL  _SFR_MEM8(0x80)
+#define T4CNTH  _SFR_MEM8(0x81)
+
+/* Combine T4CORL and T4CORH */
+#define T4COR   _SFR_MEM16(0x82)
+
+#define T4CORL  _SFR_MEM8(0x82)
+#define T4CORH  _SFR_MEM8(0x83)
+
+/* Combine T4ICRL and T4ICRH */
+#define T4ICR   _SFR_MEM16(0x84)
+
+#define T4ICRL  _SFR_MEM8(0x84)
+#define T4ICRH  _SFR_MEM8(0x85)
+
+#define T4MRA   _SFR_MEM8(0x86)
+#define T4CS0   0
+#define T4CS1   1
+#define T4PS0   2
+#define T4PS1   3
+#define T4PS2   4
+
+#define T4MRB   _SFR_MEM8(0x87)
+#define T4SCE   1
+#define T4CNC   2
+#define T4CE0   3
+#define T4CE1   4
+#define T4ICS0  5
+#define T4ICS1  6
+#define T4ICS2  7
+
+#define T4IMR   _SFR_MEM8(0x88)
+#define T4OIM   0
+#define T4CIM   1
+#define T4CPIM  2
+
+/* Reserved [0x89] */
+
+/* Combine T5OCRL and T5OCRH */
+#define T5OCR   _SFR_MEM16(0x8A)
+
+#define T5OCRL  _SFR_MEM8(0x8A)
+#define T5OCRH  _SFR_MEM8(0x8B)
+
+#define T5CCR   _SFR_MEM8(0x8C)
+#define T5CS0   0
+#define T5CS1   1
+#define T5CS2   2
+#define T5CTC   3
+
+/* Combine T5CNTL and T5CNTH */
+#define T5CNT   _SFR_MEM16(0x8D)
+
+#define T5CNTL  _SFR_MEM8(0x8D)
+#define T5CNTH  _SFR_MEM8(0x8E)
+
+#define T5IMR   _SFR_MEM8(0x8F)
+#define T5OIM   0
+#define T5CIM   1
+
+#define GTCCR   _SFR_MEM8(0x90)
+#define PSR10   0
+#define TSM     7
+
+#define SOTSB   _SFR_MEM8(0x91)
+#define CAROB   0
+#define AMPOB   1
+#define SYTOB   2
+#define MANOB   3
+#define WUPOB   4
+#define SFIDOB  5
+#define RROB    6
+#define WCOAO   7
+
+#define SOTSA   _SFR_MEM8(0x92)
+#define CAROA   0
+#define AMPOA   1
+#define SYTOA   2
+#define MANOA   3
+#define WUPOA   4
+#define SFIDOA  5
+#define RROA    6
+#define WCOBO   7
+
+#define SOTCB   _SFR_MEM8(0x93)
+#define CAROEB  0
+#define AMPOEB  1
+#define SYTOEB  2
+#define MANOEB  3
+#define WUPEB   4
+#define SFIDEB  5
+#define RROEB   6
+#define WCOAOE  7
+
+#define SOTCA   _SFR_MEM8(0x94)
+#define CAROEA  0
+#define AMPOEA  1
+#define SYTOEA  2
+#define MANOEA  3
+#define WUPEA   4
+#define SFIDEA  5
+#define RROEA   6
+#define WCOBOE  7
+
+#define TESRB   _SFR_MEM8(0x95)
+#define CRCOB   0
+#define EOTLB0  1
+#define EOTLB1  2
+
+#define TESRA   _SFR_MEM8(0x96)
+#define CRCOA   0
+#define EOTLA0  1
+#define EOTLA1  2
+
+/* Reserved [0x97] */
+
+#define RDSIMR  _SFR_MEM8(0x98)
+#define NBITAM  0
+#define NBITBM  1
+#define EOTAM   2
+#define EOTBM   3
+#define SOTAM   4
+#define SOTBM   5
+#define WCOAM   6
+#define WCOBM   7
+
+#define RDOCR   _SFR_MEM8(0x99)
+#define TMDS0   1
+#define TMDS1   2
+#define ETRPA   3
+#define ETRPB   4
+#define RDSIDA  5
+#define RDSIDB  6
+
+/* Reserved [0x9A] */
+
+#define TEMPL   _SFR_MEM8(0x9B)
+
+#define TEMPH   _SFR_MEM8(0x9C)
+
+#define SYCB    _SFR_MEM8(0x9D)
+#define SYCSB0  0
+#define SYCSB1  1
+#define SYCSB2  2
+#define SYCSB3  3
+#define SYTLB0  4
+#define SYTLB1  5
+#define SYTLB2  6
+#define SYTLB3  7
+
+#define SYCA    _SFR_MEM8(0x9E)
+#define SYCSA0  0
+#define SYCSA1  1
+#define SYCSA2  2
+#define SYCSA3  3
+#define SYTLA0  4
+#define SYTLA1  5
+#define SYTLA2  6
+#define SYTLA3  7
+
+#define RXFOB   _SFR_MEM8(0x9F)
+
+#define RXFOA   _SFR_MEM8(0xA0)
+
+#define DMMB    _SFR_MEM8(0xA1)
+#define DMATB0  0
+#define DMATB1  1
+#define DMATB2  2
+#define DMATB3  3
+#define DMATB4  4
+#define DMPB    5
+#define DMHB    6
+#define DMNEB   7
+
+#define DMMA    _SFR_MEM8(0xA2)
+#define DMATA0  0
+#define DMATA1  1
+#define DMATA2  2
+#define DMATA3  3
+#define DMATA4  4
+#define DMPA    5
+#define DMHA    6
+#define DMNEA   7
+
+#define DMCDB   _SFR_MEM8(0xA3)
+#define DMCLB0  0
+#define DMCLB1  1
+#define DMCLB2  2
+#define DMCLB3  3
+#define DMCLB4  4
+#define DMCTB0  5
+#define DMCTB1  6
+#define DMCTB2  7
+
+#define DMCDA   _SFR_MEM8(0xA4)
+#define DMCLA0  0
+#define DMCLA1  1
+#define DMCLA2  2
+#define DMCLA3  3
+#define DMCLA4  4
+#define DMCTA0  5
+#define DMCTA1  6
+#define DMCTA2  7
+
+#define DMCRB   _SFR_MEM8(0xA5)
+#define DMPGB0  0
+#define DMPGB1  1
+#define DMPGB2  2
+#define DMPGB3  3
+#define DMPGB4  4
+#define SASKB   5
+#define SY1TB   6
+#define DMARB   7
+
+#define DMCRA   _SFR_MEM8(0xA6)
+#define DMPGA0  0
+#define DMPGA1  1
+#define DMPGA2  2
+#define DMPGA3  3
+#define DMPGA4  4
+#define SASKA   5
+#define SY1TA   6
+#define DMARA   7
+
+#define DMDRB   _SFR_MEM8(0xA7)
+#define DMAB0   0
+#define DMAB1   1
+#define DMAB2   2
+#define DMAB3   3
+#define DMDNB0  4
+#define DMDNB1  5
+#define DMDNB2  6
+#define DMDNB3  7
+
+#define DMDRA   _SFR_MEM8(0xA8)
+#define DMAA0   0
+#define DMAA1   1
+#define DMAA2   2
+#define DMAA3   3
+#define DMDNA0  4
+#define DMDNA1  5
+#define DMDNA2  6
+#define DMDNA3  7
+
+#define CHCR    _SFR_MEM8(0xA9)
+#define BWM0    0
+#define BWM1    1
+#define BWM2    2
+#define BWM3    3
+
+#define CHDN    _SFR_MEM8(0xAA)
+#define BBDN0   0
+#define BBDN1   1
+#define BBDN2   2
+#define BBDN3   3
+#define BBDN4   4
+#define ADCDN   5
+
+#define SFIDCB  _SFR_MEM8(0xAB)
+#define SFIDTB0 0
+#define SFIDTB1 1
+#define SFIDTB2 2
+#define SFIDTB3 3
+#define SFIDTB4 4
+#define SEMEB   7
+
+#define SFIDLB  _SFR_MEM8(0xAC)
+#define SFIDLB0 0
+#define SFIDLB1 1
+#define SFIDLB2 2
+#define SFIDLB3 3
+#define SFIDLB4 4
+#define SFIDLB5 5
+
+#define WUPTB   _SFR_MEM8(0xAD)
+#define WUPTB0  0
+#define WUPTB1  1
+#define WUPTB2  2
+#define WUPTB3  3
+#define WUPTB4  4
+
+#define WUPLB   _SFR_MEM8(0xAE)
+#define WUPLB0  0
+#define WUPLB1  1
+#define WUPLB2  2
+#define WUPLB3  3
+#define WUPLB4  4
+#define WUPLB5  5
+
+#define SFID1B  _SFR_MEM8(0xAF)
+
+#define SFID2B  _SFR_MEM8(0xB0)
+
+#define SFID3B  _SFR_MEM8(0xB1)
+
+#define SFID4B  _SFR_MEM8(0xB2)
+
+#define WUP1B   _SFR_MEM8(0xB3)
+
+#define WUP2B   _SFR_MEM8(0xB4)
+
+#define WUP3B   _SFR_MEM8(0xB5)
+
+#define WUP4B   _SFR_MEM8(0xB6)
+
+#define SFIDCA  _SFR_MEM8(0xB7)
+#define SFIDTA0 0
+#define SFIDTA1 1
+#define SFIDTA2 2
+#define SFIDTA3 3
+#define SFIDTA4 4
+#define SEMEA   7
+
+#define SFIDLA  _SFR_MEM8(0xB8)
+#define SFIDLA0 0
+#define SFIDLA1 1
+#define SFIDLA2 2
+#define SFIDLA3 3
+#define SFIDLA4 4
+#define SFIDLA5 5
+
+#define WUPTA   _SFR_MEM8(0xB9)
+#define WUPTA0  0
+#define WUPTA1  1
+#define WUPTA2  2
+#define WUPTA3  3
+#define WUPTA4  4
+
+#define WUPLA   _SFR_MEM8(0xBA)
+#define WUPLA0  0
+#define WUPLA1  1
+#define WUPLA2  2
+#define WUPLA3  3
+#define WUPLA4  4
+#define WUPLA5  5
+
+#define SFID1A  _SFR_MEM8(0xBB)
+
+#define SFID2A  _SFR_MEM8(0xBC)
+
+#define SFID3A  _SFR_MEM8(0xBD)
+
+#define SFID4A  _SFR_MEM8(0xBE)
+
+#define WUP1A   _SFR_MEM8(0xBF)
+
+#define WUP2A   _SFR_MEM8(0xC0)
+
+#define WUP3A   _SFR_MEM8(0xC1)
+
+#define WUP4A   _SFR_MEM8(0xC2)
+
+#define CLKOD   _SFR_MEM8(0xC3)
+
+#define CLKOCR  _SFR_MEM8(0xC4)
+#define CLKOS0  0
+#define CLKOS1  1
+#define CLKOEN  2
+
+#define XFUSE   _SFR_MEM8(0xC5)
+
+#define SRCCAL  _SFR_MEM8(0xC6)
+#define SRCCAL0 0
+#define SRCCAL1 1
+#define SRCCAL2 2
+#define SRCCAL3 3
+#define SRCCAL4 4
+#define SRCCAL5 5
+#define SRCTC0  6
+#define SRCTC1  7
+
+#define FRCCAL  _SFR_MEM8(0xC7)
+#define FRCCAL0 0
+#define FRCCAL1 1
+#define FRCCAL2 2
+#define FRCCAL3 3
+#define FRCCAL4 4
+#define FRCTC   5
+
+#define CMSR    _SFR_MEM8(0xC8)
+#define ECF     0
+
+#define CMOCR   _SFR_MEM8(0xC9)
+#define FRCAO   0
+#define SRCAO   1
+#define FRCACT  2
+#define SRCACT  3
+
+#define SUPFR   _SFR_MEM8(0xCA)
+#define AVCCRF  0
+#define AVCCLF  1
+
+#define SUPCR   _SFR_MEM8(0xCB)
+#define AVCCRM  0
+#define AVCCLM  1
+#define PVEN    2
+#define DVDIS   4
+#define AVEN    5
+#define AVDIC   6
+
+#define SUPCA1  _SFR_MEM8(0xCC)
+#define PV22    2
+#define PVDIC   3
+#define PVCAL0  4
+#define PVCAL1  5
+#define PVCAL2  6
+#define PVCAL3  7
+
+#define SUPCA2  _SFR_MEM8(0xCD)
+#define BGCAL0  0
+#define BGCAL1  1
+#define BGCAL2  2
+#define BGCAL3  3
+
+#define SUPCA3  _SFR_MEM8(0xCE)
+#define ACAL4   0
+#define ACAL5   1
+#define ACAL6   2
+#define ACAL7   3
+#define DCAL4   4
+#define DCAL5   5
+#define DCAL6   6
+
+#define SUPCA4  _SFR_MEM8(0xCF)
+#define ACAL0   0
+#define ACAL1   1
+#define ACAL2   2
+#define ACAL3   3
+#define DCAL0   4
+#define DCAL1   5
+#define DCAL2   6
+#define DCAL3   7
+
+#define CALRDY  _SFR_MEM8(0xD0)
+
+#define VMCAL   _SFR_MEM8(0xD1)
+#define VMCAL0  0
+#define VMCAL1  1
+#define VMCAL2  2
+
+#define DFS     _SFR_MEM8(0xD2)
+#define DFFLRF  0
+#define DFUFL   1
+#define DFOFL   2
+
+/* Combine DFTLL and DFTLH */
+#define DFTL    _SFR_MEM16(0xD3)
+
+#define DFTLL   _SFR_MEM8(0xD3)
+#define DFTLH   _SFR_MEM8(0xD4)
+
+#define DFL     _SFR_MEM8(0xD5)
+#define DFFLS0  0
+#define DFFLS1  1
+#define DFFLS2  2
+#define DFFLS3  3
+#define DFFLS4  4
+#define DFFLS5  5
+#define DFCLR   7
+
+#define DFWP    _SFR_MEM8(0xD6)
+#define DFWP0   0
+#define DFWP1   1
+#define DFWP2   2
+#define DFWP3   3
+#define DFWP4   4
+#define DFWP5   5
+
+#define DFRP    _SFR_MEM8(0xD7)
+#define DFRP0   0
+#define DFRP1   1
+#define DFRP2   2
+#define DFRP3   3
+#define DFRP4   4
+#define DFRP5   5
+
+#define DFD     _SFR_MEM8(0xD8)
+
+#define DFI     _SFR_MEM8(0xD9)
+#define DFFLIM  0
+#define DFERIM  1
+
+#define DFC     _SFR_MEM8(0xDA)
+#define DFFLC0  0
+#define DFFLC1  1
+#define DFFLC2  2
+#define DFFLC3  3
+#define DFFLC4  4
+#define DFFLC5  5
+#define DFDRA   7
+
+#define SFS     _SFR_MEM8(0xDB)
+#define SFFLRF  0
+#define SFUFL   1
+#define SFOFL   2
+
+#define SFL     _SFR_MEM8(0xDC)
+#define SFFLS0  0
+#define SFFLS1  1
+#define SFFLS2  2
+#define SFFLS3  3
+#define SFFLS4  4
+#define SFCLR   7
+
+#define SFWP    _SFR_MEM8(0xDD)
+#define SFWP0   0
+#define SFWP1   1
+#define SFWP2   2
+#define SFWP3   3
+#define SFWP4   4
+
+#define SFRP    _SFR_MEM8(0xDE)
+#define SFRP0   0
+#define SFRP1   1
+#define SFRP2   2
+#define SFRP3   3
+#define SFRP4   4
+
+#define SFD     _SFR_MEM8(0xDF)
+
+#define SFI     _SFR_MEM8(0xE0)
+#define SFFLIM  0
+#define SFERIM  1
+
+#define SFC     _SFR_MEM8(0xE1)
+#define SFFLC0  0
+#define SFFLC1  1
+#define SFFLC2  2
+#define SFFLC3  3
+#define SFFLC4  4
+#define SFDRA   7
+
+#define SSMCR   _SFR_MEM8(0xE2)
+#define SSMTX   0
+#define SSMTM   1
+#define SSMTGE  2
+#define SSMTPE  3
+#define SSMPVE  4
+#define SSMTAE  5
+#define SETRPA  6
+#define SETRPB  7
+
+#define SSMRCR  _SFR_MEM8(0xE3)
+#define SSMPA   0
+#define SSMPB   1
+#define SSMADA  2
+#define SSMADB  3
+#define SSMPVS  4
+#define SSMIFA  5
+#define SSMIDSE 6
+#define SSMTMOE 7
+
+#define SSMFBR  _SFR_MEM8(0xE4)
+#define SSMFID0 0
+#define SSMFID1 1
+#define SSMFID2 2
+#define SSMDFDT 3
+#define SSMHADT 4
+#define SSMPLDT 5
+
+#define SSMRR   _SFR_MEM8(0xE5)
+#define SSMR    0
+#define SSMST   1
+
+#define SSMSR   _SFR_MEM8(0xE6)
+#define SSMESM0 0
+#define SSMESM1 1
+#define SSMESM2 2
+#define SSMESM3 3
+#define SSMERR  7
+
+#define SSMIFR  _SFR_MEM8(0xE7)
+#define SSMIF   0
+
+#define SSMIMR  _SFR_MEM8(0xE8)
+#define SSMIM   0
+
+#define MSMSTR  _SFR_MEM8(0xE9)
+#define SSMMST0 0
+#define SSMMST1 1
+#define SSMMST2 2
+#define SSMMST3 3
+#define SSMMST4 4
+
+#define SSMSTR  _SFR_MEM8(0xEA)
+#define SSMSTA0 0
+#define SSMSTA1 1
+#define SSMSTA2 2
+#define SSMSTA3 3
+#define SSMSTA4 4
+#define SSMSTA5 5
+
+#define SSMXSR  _SFR_MEM8(0xEB)
+#define SSMSTB0 0
+#define SSMSTB1 1
+#define SSMSTB2 2
+#define SSMSTB3 3
+#define SSMSTB4 4
+#define SSMSTB5 5
+
+#define MSMCR1  _SFR_MEM8(0xEC)
+#define MSMSM00 0
+#define MSMSM01 1
+#define MSMSM02 2
+#define MSMSM03 3
+#define MSMSM10 4
+#define MSMSM11 5
+#define MSMSM12 6
+#define MSMSM13 7
+
+#define MSMCR2  _SFR_MEM8(0xED)
+#define MSMSM20 0
+#define MSMSM21 1
+#define MSMSM22 2
+#define MSMSM23 3
+#define MSMSM30 4
+#define MSMSM31 5
+#define MSMSM32 6
+#define MSMSM33 7
+
+#define MSMCR3  _SFR_MEM8(0xEE)
+#define MSMSM40 0
+#define MSMSM41 1
+#define MSMSM42 2
+#define MSMSM43 3
+#define MSMSM50 4
+#define MSMSM51 5
+#define MSMSM52 6
+#define MSMSM53 7
+
+#define MSMCR4  _SFR_MEM8(0xEF)
+#define MSMSM60 0
+#define MSMSM61 1
+#define MSMSM62 2
+#define MSMSM63 3
+#define MSMSM70 4
+#define MSMSM71 5
+#define MSMSM72 6
+#define MSMSM73 7
+
+#define GTCR    _SFR_MEM8(0xF0)
+#define RXTEHA  0
+#define GAPMA   1
+#define DARA    2
+#define IWUPA   3
+#define RXTEHB  4
+#define GAPMB   5
+#define DARB    6
+#define IWUPB   7
+
+#define SOTC1A  _SFR_MEM8(0xF1)
+#define CAROEA1 0
+#define AMPOEA1 1
+#define SYTOEA1 2
+#define MANOEA1 3
+#define WUPEA1  4
+#define SFIDEA1 5
+#define RROEA1  6
+#define WCOBOE1 7
+
+#define SOTC2A  _SFR_MEM8(0xF2)
+#define CAROEA2 0
+#define AMPOEA2 1
+#define SYTOEA2 2
+#define MANOEA2 3
+#define WUPEA2  4
+#define SFIDEA2 5
+#define RROEA2  6
+#define WCOBOE2 7
+
+#define SOTC1B  _SFR_MEM8(0xF3)
+#define CAROEB1 0
+#define AMPOEB1 1
+#define SYTOEB1 2
+#define MANOEB1 3
+#define WUPEB1  4
+#define SFIDEB1 5
+#define RROEB1  6
+#define WCOAOE1 7
+
+#define SOTC2B  _SFR_MEM8(0xF4)
+#define CAROEB2 0
+#define AMPOEB2 1
+#define SYTOEB2 2
+#define MANOEB2 3
+#define WUPEB2  4
+#define SFIDEB2 5
+#define RROEB2  6
+#define WCOAOE2 7
+
+#define EOTC1A  _SFR_MEM8(0xF5)
+#define CARFEA1 0
+#define AMPFEA1 1
+#define SYTFEA1 2
+#define MANFEA1 3
+#define TMOFEA1 4
+#define TELREA1 5
+#define RRFEA1  6
+#define EOTBFE1 7
+
+#define EOTC2A  _SFR_MEM8(0xF6)
+#define CARFEA2 0
+#define AMPFEA2 1
+#define SYTFEA2 2
+#define MANFEA2 3
+#define TMOFEA2 4
+#define TELREA2 5
+#define RRFEA2  6
+#define EOTBFE2 7
+
+#define EOTC3A  _SFR_MEM8(0xF7)
+#define CARFEA3 0
+#define AMPFEA3 1
+#define SYTFEA3 2
+#define MANFEA3 3
+#define TMOFEA3 4
+#define TELREA3 5
+#define RRFEA3  6
+#define EOTBFE3 7
+
+#define EOTC1B  _SFR_MEM8(0xF8)
+#define CARFEB1 0
+#define AMPFEB1 1
+#define SYTFEB1 2
+#define MANFEB1 3
+#define TMOFEB1 4
+#define TELREB1 5
+#define RRFEB1  6
+#define EOTAFE1 7
+
+#define EOTC2B  _SFR_MEM8(0xF9)
+#define CARFEB2 0
+#define AMPFEB2 1
+#define SYTFEB2 2
+#define MANFEB2 3
+#define TMOFEB2 4
+#define TELREB2 5
+#define RRFEB2  6
+#define EOTAFE2 7
+
+#define EOTC3B  _SFR_MEM8(0xFA)
+#define CARFEB3 0
+#define AMPFEB3 1
+#define SYTFEB3 2
+#define MANFEB3 3
+#define TMOFEB3 4
+#define TELREB3 5
+#define RRFEB3  6
+#define EOTAFE3 7
+
+#define WCOTOA  _SFR_MEM8(0xFB)
+
+#define WCOTOB  _SFR_MEM8(0xFC)
+
+#define SOTTOA  _SFR_MEM8(0xFD)
+
+#define SOTTOB  _SFR_MEM8(0xFE)
+
+#define SSMFCR  _SFR_MEM8(0xFF)
+#define SSMIDSO 0
+#define SSMIDSF 1
+
+#define FESR    _SFR_MEM8(0x100)
+#define LBSAT   0
+#define HBSAT   1
+#define XRDY    2
+#define PLCK    3
+#define ANTS    4
+
+#define FEEN1   _SFR_MEM8(0x101)
+#define PLEN    0
+#define PLCAL   1
+#define XTOEN   2
+#define LNAEN   3
+#define ADEN    4
+#define ADCLK   5
+#define PLSP1   6
+#define ATEN    7
+
+#define FEEN2   _SFR_MEM8(0x102)
+#define SDRX    0
+#define SDTX    1
+#define PAEN    2
+#define TMPM    3
+#define PLPEN   4
+#define XTPEN   5
+#define CPBIA   6
+
+#define FELNA   _SFR_MEM8(0x103)
+#define LBH0    0
+#define LBH1    1
+#define LBH2    2
+#define LBH3    3
+#define LBL0    4
+#define LBL1    5
+#define LBL2    6
+#define LBL3    7
+
+#define FEAT    _SFR_MEM8(0x104)
+#define ANTN0   0
+#define ANTN1   1
+#define ANTN2   2
+#define ANTN3   3
+
+#define FEPAC   _SFR_MEM8(0x105)
+
+#define FEVCT   _SFR_MEM8(0x106)
+#define FEVCT0  0
+#define FEVCT1  1
+#define FEVCT2  2
+#define FEVCT3  3
+
+#define FEBT    _SFR_MEM8(0x107)
+#define CTN20   0
+#define CTN21   1
+#define RTN20   2
+#define RTN21   3
+
+#define FEMS    _SFR_MEM8(0x108)
+#define PLLS0   0
+#define PLLS1   1
+#define PLLS2   2
+#define PLLS3   3
+#define PLLM0   4
+#define PLLM1   5
+#define PLLM2   6
+#define PLLM3   7
+
+#define FETN4   _SFR_MEM8(0x109)
+#define CTN40   0
+#define CTN41   1
+#define CTN42   2
+#define CTN43   3
+#define RTN40   4
+#define RTN41   5
+#define RTN42   6
+#define RTN43   7
+
+#define FECR    _SFR_MEM8(0x10A)
+#define LBNHB   0
+#define S4N3    1
+#define ANDP    2
+#define ADHS    3
+#define PLCKG   4
+#define ANPS    5
+
+#define FEVCO   _SFR_MEM8(0x10B)
+#define CPCC0   0
+#define CPCC1   1
+#define CPCC2   2
+#define CPCC3   3
+#define VCOB0   4
+#define VCOB1   5
+#define VCOB2   6
+#define VCOB3   7
+
+#define FEALR   _SFR_MEM8(0x10C)
+#define RNGE0   0
+#define RNGE1   1
+
+#define FEANT   _SFR_MEM8(0x10D)
+#define LVLC0   0
+#define LVLC1   1
+#define LVLC2   2
+#define LVLC3   3
+
+#define FEBIA   _SFR_MEM8(0x10E)
+#define IFAEN   7
+
+/* Reserved [0x10F..0x11F] */
+
+#define TMFSM   _SFR_MEM8(0x120)
+#define TMSSM0  0
+#define TMSSM1  1
+#define TMSSM2  2
+#define TMSSM3  3
+#define TMMSM0  4
+#define TMMSM1  5
+#define TMMSM2  6
+
+/* Combine TMCRL and TMCRH */
+#define TMCR    _SFR_MEM16(0x121)
+
+#define TMCRL   _SFR_MEM8(0x121)
+#define TMCRH   _SFR_MEM8(0x122)
+
+#define TMCSB   _SFR_MEM8(0x123)
+
+/* Combine TMCIL and TMCIH */
+#define TMCI    _SFR_MEM16(0x124)
+
+#define TMCIL   _SFR_MEM8(0x124)
+#define TMCIH   _SFR_MEM8(0x125)
+
+/* Combine TMCPL and TMCPH */
+#define TMCP    _SFR_MEM16(0x126)
+
+#define TMCPL   _SFR_MEM8(0x126)
+#define TMCPH   _SFR_MEM8(0x127)
+
+#define TMSHR   _SFR_MEM8(0x128)
+
+/* Combine TMTLL and TMTLH */
+#define TMTL    _SFR_MEM16(0x129)
+
+#define TMTLL   _SFR_MEM8(0x129)
+#define TMTLH   _SFR_MEM8(0x12A)
+
+#define TMSSC   _SFR_MEM8(0x12B)
+#define TMSSP0  0
+#define TMSSP1  1
+#define TMSSP2  2
+#define TMSSP3  3
+#define TMSSL0  4
+#define TMSSL1  5
+#define TMSSL2  6
+#define TMSSH   7
+
+#define TMSR    _SFR_MEM8(0x12C)
+#define TMTCF   0
+
+#define TMCR2   _SFR_MEM8(0x12D)
+#define TMCRCE  0
+#define TMCRCL0 1
+#define TMCRCL1 2
+#define TMNRZE  3
+#define TMPOL   4
+#define TMSSE   5
+#define TMMSB   6
+
+#define TMCR1   _SFR_MEM8(0x12E)
+#define TMPIS0  0
+#define TMPIS1  1
+#define TMPIS2  2
+#define TMSCS   3
+#define TMCIM   4
+
+#define RXBC1   _SFR_MEM8(0x12F)
+#define RXCEA   0
+#define RXCBLA0 1
+#define RXCBLA1 2
+#define RXMSBA  3
+#define RXCEB   4
+#define RXCBLB0 5
+#define RXCBLB1 6
+#define RXMSBB  7
+
+#define RXBC2   _SFR_MEM8(0x130)
+#define RXBPB   0
+#define RXBF    1
+#define RXBCLR  2
+
+#define RXTLLB  _SFR_MEM8(0x131)
+
+#define RXTLHB  _SFR_MEM8(0x132)
+#define RXTLHB0 0
+#define RXTLHB1 1
+#define RXTLHB2 2
+#define RXTLHB3 3
+
+#define RXCRLB  _SFR_MEM8(0x133)
+
+#define RXCRHB  _SFR_MEM8(0x134)
+
+#define RXCSBB  _SFR_MEM8(0x135)
+
+#define RXCILB  _SFR_MEM8(0x136)
+
+#define RXCIHB  _SFR_MEM8(0x137)
+
+#define RXCPLB  _SFR_MEM8(0x138)
+
+#define RXCPHB  _SFR_MEM8(0x139)
+
+#define RXDSB   _SFR_MEM8(0x13A)
+
+#define RXTLLA  _SFR_MEM8(0x13B)
+
+#define RXTLHA  _SFR_MEM8(0x13C)
+#define RXTLHA0 0
+#define RXTLHA1 1
+#define RXTLHA2 2
+#define RXTLHA3 3
+
+#define RXCRLA  _SFR_MEM8(0x13D)
+
+#define RXCRHA  _SFR_MEM8(0x13E)
+
+#define RXCSBA  _SFR_MEM8(0x13F)
+
+#define RXCILA  _SFR_MEM8(0x140)
+
+#define RXCIHA  _SFR_MEM8(0x141)
+
+#define RXCPLA  _SFR_MEM8(0x142)
+
+#define RXCPHA  _SFR_MEM8(0x143)
+
+#define RXDSA   _SFR_MEM8(0x144)
+
+#define CRCCR   _SFR_MEM8(0x145)
+#define CRCRS   0
+#define REFLI   1
+#define REFLO   2
+
+#define CRCDOR  _SFR_MEM8(0x146)
+
+#define IDB0    _SFR_MEM8(0x147)
+
+#define IDB1    _SFR_MEM8(0x148)
+
+#define IDB2    _SFR_MEM8(0x149)
+
+#define IDB3    _SFR_MEM8(0x14A)
+
+#define IDC     _SFR_MEM8(0x14B)
+#define IDL0    0
+#define IDL1    1
+#define IDBO0   2
+#define IDBO1   3
+#define IDFIM   5
+#define IDCLR   6
+#define IDCE    7
+
+#define IDS     _SFR_MEM8(0x14C)
+#define IDOK    0
+#define IDFULL  1
+
+#define RSSAV   _SFR_MEM8(0x14D)
+
+#define RSSPK   _SFR_MEM8(0x14E)
+
+#define RSSL    _SFR_MEM8(0x14F)
+
+#define RSSH    _SFR_MEM8(0x150)
+
+#define RSSC    _SFR_MEM8(0x151)
+#define RSUP0   0
+#define RSUP1   1
+#define RSUP2   2
+#define RSUP3   3
+#define RSWLH   4
+#define RSHRX   5
+#define RSPKF   6
+
+#define DBCR    _SFR_MEM8(0x152)
+#define DBMD    0
+#define DBCS    1
+#define DBTMS   2
+#define DBHA    3
+
+#define DBTC    _SFR_MEM8(0x153)
+
+#define DBENB   _SFR_MEM8(0x154)
+
+#define DBENC   _SFR_MEM8(0x155)
+
+#define DBGSW   _SFR_MEM8(0x156)
+#define DBGGS0  0
+#define DBGGS1  1
+#define DBGGS2  2
+#define DBGGS3  3
+#define CPBFOS0 4
+#define CPBFOS1 5
+#define CPBF    6
+#define DBGSE   7
+
+#define SFFR    _SFR_MEM8(0x157)
+#define RFL0    0
+#define RFL1    1
+#define RFL2    2
+#define RFC     3
+#define TFL0    4
+#define TFL1    5
+#define TFL2    6
+#define TFC     7
+
+#define SFIR    _SFR_MEM8(0x158)
+#define RIL0    0
+#define RIL1    1
+#define RIL2    2
+#define SRIE    3
+#define TIL0    4
+#define TIL1    5
+#define TIL2    6
+#define STIE    7
+
+#define EECR2   _SFR_MEM8(0x159)
+#define EEBRE   0
+
+#define PGMST   _SFR_MEM8(0x15A)
+#define PGMSYN0 0
+#define PGMSYN1 1
+#define PGMSYN2 2
+#define PGMSYN3 3
+#define PGMSYN4 4
+
+#define EEST    _SFR_MEM8(0x15B)
+#define EESYN0  0
+#define EESYN1  1
+#define EESYN2  2
+#define EESYN3  3
+
+#define RSIFG   _SFR_MEM8(0x15C)
+
+#define RSLDV   _SFR_MEM8(0x15D)
+
+#define RSHDV   _SFR_MEM8(0x15E)
+
+#define RSCOM   _SFR_MEM8(0x15F)
+#define RSDC    0
+#define RSIFC   1
+
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
+
+/* External Interrupt Request 1 */
+#define INT1_vect            _VECTOR(2)
+#define INT1_vect_num        2
+
+/* Pin Change Interrupt Request 0 */
+#define PCI0_vect            _VECTOR(3)
+#define PCI0_vect_num        3
+
+/* Pin Change Interrupt Request 1 */
+#define PCI1_vect            _VECTOR(4)
+#define PCI1_vect_num        4
+
+/* Voltage Monitoring Interrupt */
+#define VMON_vect            _VECTOR(5)
+#define VMON_vect_num        5
+
+/* AVCC Reset Interrupt */
+#define AVCCR_vect            _VECTOR(6)
+#define AVCCR_vect_num        6
+
+/* AVCC Low Interrupt */
+#define AVCCL_vect            _VECTOR(7)
+#define AVCCL_vect_num        7
+
+/* Timer 0 Interval Interrupt */
+#define T0INT_vect            _VECTOR(8)
+#define T0INT_vect_num        8
+
+/* Timer/Counter1 Compare Match Interrupt */
+#define T1COMP_vect            _VECTOR(9)
+#define T1COMP_vect_num        9
+
+/* Timer/Counter1 Overflow Interrupt */
+#define T1OVF_vect            _VECTOR(10)
+#define T1OVF_vect_num        10
+
+/* Timer/Counter2 Compare Match Interrupt */
+#define T2COMP_vect            _VECTOR(11)
+#define T2COMP_vect_num        11
+
+/* Timer/Counter2 Overflow Interrupt */
+#define T2OVF_vect            _VECTOR(12)
+#define T2OVF_vect_num        12
+
+/* Timer/Counter3 Capture Event Interrupt */
+#define T3CAP_vect            _VECTOR(13)
+#define T3CAP_vect_num        13
+
+/* Timer/Counter3 Compare Match Interrupt */
+#define T3COMP_vect            _VECTOR(14)
+#define T3COMP_vect_num        14
+
+/* Timer/Counter3 Overflow Interrupt */
+#define T3OVF_vect            _VECTOR(15)
+#define T3OVF_vect_num        15
+
+/* Timer/Counter4 Capture Event Interrupt */
+#define T4CAP_vect            _VECTOR(16)
+#define T4CAP_vect_num        16
+
+/* Timer/Counter4 Compare Match Interrupt */
+#define T4COMP_vect            _VECTOR(17)
+#define T4COMP_vect_num        17
+
+/* Timer/Counter4 Overflow Interrupt */
+#define T4OVF_vect            _VECTOR(18)
+#define T4OVF_vect_num        18
+
+/* Timer/Counter5 Compare Match Interrupt */
+#define T5COMP_vect            _VECTOR(19)
+#define T5COMP_vect_num        19
+
+/* Timer/Counter5 Overflow Interrupt */
+#define T5OVF_vect            _VECTOR(20)
+#define T5OVF_vect_num        20
+
+/* SPI Serial Transfer Complete Interrupt */
+#define SPI_vect            _VECTOR(21)
+#define SPI_vect_num        21
+
+/* SPI Rx Buffer Interrupt */
+#define SRX_FIFO_vect            _VECTOR(22)
+#define SRX_FIFO_vect_num        22
+
+/* SPI Tx Buffer Interrupt */
+#define STX_FIFO_vect            _VECTOR(23)
+#define STX_FIFO_vect_num        23
+
+/* Sequencer State Machine Interrupt */
+#define SSM_vect            _VECTOR(24)
+#define SSM_vect_num        24
+
+/* Data FIFO fill level reached Interrupt */
+#define DFFLR_vect            _VECTOR(25)
+#define DFFLR_vect_num        25
+
+/* Data FIFO overflow or underflow error Interrupt */
+#define DFOUE_vect            _VECTOR(26)
+#define DFOUE_vect_num        26
+
+/* RSSI/Preamble FIFO fill level reached Interrupt */
+#define SFFLR_vect            _VECTOR(27)
+#define SFFLR_vect_num        27
+
+/* RSSI/Preamble FIFO overflow or underflow error Interrupt */
+#define SFOUE_vect            _VECTOR(28)
+#define SFOUE_vect_num        28
+
+/* Tx Modulator Telegram Finish Interrupt */
+#define TMTCF_vect            _VECTOR(29)
+#define TMTCF_vect_num        29
+
+/* UHF receiver wake up ok on Rx path B */
+#define UHF_WCOB_vect            _VECTOR(30)
+#define UHF_WCOB_vect_num        30
+
+/* UHF receiver wake up ok on Rx path A */
+#define UHF_WCOA_vect            _VECTOR(31)
+#define UHF_WCOA_vect_num        31
+
+/* UHF receiver start of telegram ok on Rx path B */
+#define UHF_SOTB_vect            _VECTOR(32)
+#define UHF_SOTB_vect_num        32
+
+/* UHF receiver start of telegram ok on Rx path A */
+#define UHF_SOTA_vect            _VECTOR(33)
+#define UHF_SOTA_vect_num        33
+
+/* UHF receiver end of telegram on Rx path B */
+#define UHF_EOTB_vect            _VECTOR(34)
+#define UHF_EOTB_vect_num        34
+
+/* UHF receiver end of telegram on Rx path A */
+#define UHF_EOTA_vect            _VECTOR(35)
+#define UHF_EOTA_vect_num        35
+
+/* UHF receiver new bit on Rx path B */
+#define UHF_NBITB_vect            _VECTOR(36)
+#define UHF_NBITB_vect_num        36
+
+/* UHF receiver new bit on Rx path A */
+#define UHF_NBITA_vect            _VECTOR(37)
+#define UHF_NBITA_vect_num        37
+
+/* External input Clock monitoring Interrupt */
+#define EXCM_vect            _VECTOR(38)
+#define EXCM_vect_num        38
+
+/* EEPROM Ready Interrupt */
+#define ERDY_vect            _VECTOR(39)
+#define ERDY_vect_num        39
+
+/* Store Program Memory Ready */
+#define SPMR_vect            _VECTOR(40)
+#define SPMR_vect_num        40
+
+/* IDSCAN Full Interrupt */
+#define IDFULL_vect            _VECTOR(41)
+#define IDFULL_vect_num        41
+
+#define _VECTORS_SIZE 168
+
+
+/* Constants */
+
+#define SPM_PAGESIZE 64
+#define FLASHSTART   0x8000
+#define FLASHEND     0xCFFF
+#define RAMSTART     0x0200
+#define RAMSIZE      1024
+#define RAMEND       0x05FF
+#define E2START     0
+#define E2SIZE      1152
+#define E2PAGESIZE  16
+#define E2END       0x047F
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 1
+
+/* Fuse Byte */
+#define FUSE_CKDIV8 (unsigned char)~_BV(128)
+#define FUSE_DWEN (unsigned char)~_BV(64)
+#define FUSE_SPIEN (unsigned char)~_BV(32)
+#define FUSE_WDTON (unsigned char)~_BV(16)
+#define FUSE_EESAVE (unsigned char)~_BV(8)
+#define FUSE_BOOTRST (unsigned char)~_BV(4)
+#define FUSE_RSTDISBL (unsigned char)~_BV(2)
+#define FUSE_EXTCLKEN (unsigned char)~_BV(1)
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x95
+#define SIGNATURE_2 0x62
+
+
+#endif /* #ifdef _AVR_ATA5832_H_INCLUDED */
+
diff -urN avr-libc-1.8.0.orig/include/avr/ioa5833.h avr-libc-1.8.0/include/avr/ioa5833.h
--- avr-libc-1.8.0.orig/include/avr/ioa5833.h	1970-01-01 01:00:00.000000000 +0100
+++ avr-libc-1.8.0/include/avr/ioa5833.h	2013-06-12 12:21:34.000000000 +0200
@@ -0,0 +1,1891 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2013 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATA5833_H_INCLUDED
+#define _AVR_ATA5833_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "ioa5833.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PRR0    _SFR_IO8(0x01)
+#define PRSPI   0
+#define PRRXDC  1
+#define PRTXDC  2
+#define PRCRC   3
+#define PRVM    4
+#define PRCO    5
+
+#define PRR1    _SFR_IO8(0x02)
+#define PRT1    0
+#define PRT2    1
+#define PRT3    2
+#define PRT4    3
+#define PRT5    4
+
+#define PRR2    _SFR_IO8(0x03)
+#define PRXB    0
+#define PRXA    1
+#define PRSF    2
+#define PRDF    3
+#define PRIDS   4
+#define PRRS    5
+#define PRTM    6
+#define PRSSM   7
+
+#define RDPR    _SFR_IO8(0x04)
+#define PRPTB   0
+#define PRPTA   1
+#define PRFLT   2
+#define PRTMP   3
+#define APRPTB  4
+#define APRPTA  5
+#define ARDPRF  6
+#define RDPRF   7
+
+#define PINB    _SFR_IO8(0x05)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x06)
+#define DDRB7   7
+#define DDRB6   6
+#define DDRB5   5
+#define DDRB4   4
+#define DDRB3   3
+#define DDRB2   2
+#define DDRB1   1
+#define DDRB0   0
+
+#define PORTB   _SFR_IO8(0x07)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINC    _SFR_IO8(0x08)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x09)
+#define DDRC7   7
+#define DDRC6   6
+#define DDRC5   5
+#define DDRC4   4
+#define DDRC3   3
+#define DDRC2   2
+#define DDRC1   1
+#define DDRC0   0
+
+#define PORTC   _SFR_IO8(0x0A)
+#define PORTC7  7
+#define PORTC6  6
+#define PORTC5  5
+#define PORTC4  4
+#define PORTC3  3
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+#define FSCR    _SFR_IO8(0x0B)
+#define TXMOD   0
+#define SFM     1
+#define TXMS0   2
+#define TXMS1   3
+#define PAOER   4
+#define PAON    7
+
+/* Reserved [0x0C] */
+
+#define RDSIFR  _SFR_IO8(0x0D)
+#define NBITA   0
+#define NBITB   1
+#define EOTA    2
+#define EOTB    3
+#define SOTA    4
+#define SOTB    5
+#define WCOA    6
+#define WCOB    7
+
+#define MCUCR   _SFR_IO8(0x0E)
+#define IVCE    0
+#define IVSEL   1
+#define SPIIO   2
+#define ENPS    3
+#define PUD     4
+#define PB4HS   5
+#define PB7LS   6
+#define PB7HS   7
+
+#define PCIFR   _SFR_IO8(0x0F)
+#define PCIF0   0
+#define PCIF1   1
+
+#define T0CR    _SFR_IO8(0x10)
+#define T0PS0   0
+#define T0PS1   1
+#define T0PS2   2
+#define T0IE    3
+#define T0PR    4
+
+#define T1CR    _SFR_IO8(0x11)
+#define T1OTM   0
+#define T1CTM   1
+#define T1CRM   2
+#define T1TOP   4
+#define T1RES   5
+#define T1TOS   6
+#define T1ENA   7
+
+#define T2CR    _SFR_IO8(0x12)
+#define T2OTM   0
+#define T2CTM   1
+#define T2CRM   2
+#define T2TOP   4
+#define T2RES   5
+#define T2TOS   6
+#define T2ENA   7
+
+#define T3CR    _SFR_IO8(0x13)
+#define T3OTM   0
+#define T3CTM   1
+#define T3CRM   2
+#define T3CPRM  3
+#define T3TOP   4
+#define T3RES   5
+#define T3TOS   6
+#define T3ENA   7
+
+#define T4CR    _SFR_IO8(0x14)
+#define T4OTM   0
+#define T4CTM   1
+#define T4CRM   2
+#define T4CPRM  3
+#define T4TOP   4
+#define T4RES   5
+#define T4TOS   6
+#define T4ENA   7
+
+#define T1IFR   _SFR_IO8(0x15)
+#define T1OFF   0
+#define T1COF   1
+
+#define T2IFR   _SFR_IO8(0x16)
+#define T2OFF   0
+#define T2COF   1
+
+#define T3IFR   _SFR_IO8(0x17)
+#define T3OFF   0
+#define T3COF   1
+#define T3ICF   2
+
+#define T4IFR   _SFR_IO8(0x18)
+#define T4OFF   0
+#define T4COF   1
+#define T4ICF   2
+
+#define T5IFR   _SFR_IO8(0x19)
+#define T5OFF   0
+#define T5COF   1
+
+#define GPIOR0  _SFR_IO8(0x1A)
+
+#define GPIOR3  _SFR_IO8(0x1B)
+
+#define GPIOR4  _SFR_IO8(0x1C)
+
+#define GPIOR5  _SFR_IO8(0x1D)
+
+#define GPIOR6  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEWE    1
+#define EEMWE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+#define EEPAGE  6
+#define NVMBSY  7
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define EEPR    _SFR_IO8(0x23)
+#define EEAP0   0
+#define EEAP1   1
+#define EEAP2   2
+#define EEAP3   3
+
+#define GPIOR1  _SFR_IO8(0x24)
+
+#define GPIOR2  _SFR_IO8(0x25)
+
+#define PCICR   _SFR_IO8(0x26)
+#define PCIE0   0
+#define PCIE1   1
+
+#define EIMSK   _SFR_IO8(0x27)
+#define INT0    0
+#define INT1    1
+
+#define EIFR    _SFR_IO8(0x28)
+#define INTF0   0
+#define INTF1   1
+
+#define CRCDIR  _SFR_IO8(0x29)
+
+#define VMCSR   _SFR_IO8(0x2A)
+#define VMLS0   0
+#define VMLS1   1
+#define VMLS2   2
+#define VMLS3   3
+#define VMIM    4
+#define VMF     5
+
+#define MCUSR   _SFR_IO8(0x2B)
+#define PORF    0
+#define EXTRF   1
+#define WDRF    3
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define RXIF    4
+#define TXIF    5
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+#define T0IFR   _SFR_IO8(0x2F)
+#define T0F     0
+
+/* Reserved [0x30] */
+
+#define DWDR    _SFR_IO8(0x31)
+
+/* Reserved [0x32] */
+
+#define RDCR    _SFR_IO8(0x33)
+#define RDPU    0
+#define ADIVEN  1
+#define RDEN    2
+
+#define EOTSA   _SFR_IO8(0x34)
+#define CARFA   0
+#define AMPFA   1
+#define SYTFA   2
+#define MANFA   3
+#define TMOFA   4
+#define TELRA   5
+#define RRFA    6
+#define EOTBF   7
+
+#define EOTCA   _SFR_IO8(0x35)
+#define CARFEA  0
+#define AMPFEA  1
+#define SYTFEA  2
+#define MANFEA  3
+#define TMOFEA  4
+#define TELREA  5
+#define RRFEA   6
+#define EOTBFE  7
+
+#define EOTSB   _SFR_IO8(0x36)
+#define CARFB   0
+#define AMPFB   1
+#define SYTFB   2
+#define MANFB   3
+#define TMOFB   4
+#define TELRB   5
+#define RRFB    6
+#define EOTAF   7
+
+#define EOTCB   _SFR_IO8(0x37)
+#define CARFEB  0
+#define AMPFEB  1
+#define SYTFEB  2
+#define MANFEB  3
+#define TMOFEB  4
+#define TELREB  5
+#define RRFEB   6
+#define EOTAFE  7
+
+#define SMCR    _SFR_IO8(0x38)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define CMCR    _SFR_IO8(0x39)
+#define CMM0    0
+#define CMM1    1
+#define CMM2    2
+#define CCS     3
+#define SRCD    4
+#define CMONEN  6
+#define CMCCE   7
+
+#define CMIMR   _SFR_IO8(0x3A)
+#define ECIE    0
+
+#define CLPR    _SFR_IO8(0x3B)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLTPS0  3
+#define CLTPS1  4
+#define CLTPS2  5
+#define CLPCE   7
+
+#define SPMCSR  _SFR_IO8(0x3C)
+#define SELFPRGEN 0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define SPMIE   7
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define FSEN    _SFR_MEM8(0x60)
+#define SDPU    0
+#define SDEN    1
+#define GAEN    2
+#define PEEN    3
+#define ASEN    4
+#define ANTT    5
+
+#define FSFCR   _SFR_MEM8(0x61)
+#define BTSEL0  0
+#define BTSEL1  1
+#define ASDIV0  4
+#define ASDIV1  5
+#define ASDIV2  6
+#define ASDIV3  7
+
+/* Combine GACDIVL and GACDIVH */
+#define GACDIV  _SFR_MEM16(0x62)
+
+#define GACDIVL _SFR_MEM8(0x62)
+#define GACDIVH _SFR_MEM8(0x63)
+
+#define FFREQ1L _SFR_MEM8(0x64)
+
+#define FFREQ1M _SFR_MEM8(0x65)
+
+#define FFREQ1H _SFR_MEM8(0x66)
+
+#define FFREQ2L _SFR_MEM8(0x67)
+
+#define FFREQ2M _SFR_MEM8(0x68)
+
+#define FFREQ2H _SFR_MEM8(0x69)
+
+/* Reserved [0x6A] */
+
+#define EICRA   _SFR_MEM8(0x6B)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+
+#define PCMSK0  _SFR_MEM8(0x6C)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6D)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+
+#define WDTCR   _SFR_MEM8(0x6E)
+#define WDPS0   0
+#define WDPS1   1
+#define WDPS2   2
+#define WDE     3
+#define WDCE    4
+
+#define T1CNT   _SFR_MEM8(0x6F)
+
+#define T1COR   _SFR_MEM8(0x70)
+
+#define T1MR    _SFR_MEM8(0x71)
+#define T1CS0   0
+#define T1CS1   1
+#define T1PS0   2
+#define T1PS1   3
+#define T1PS2   4
+#define T1PS3   5
+#define T1DC0   6
+#define T1DC1   7
+
+#define T1IMR   _SFR_MEM8(0x72)
+#define T1OIM   0
+#define T1CIM   1
+
+#define T2CNT   _SFR_MEM8(0x73)
+
+#define T2COR   _SFR_MEM8(0x74)
+
+#define T2MR    _SFR_MEM8(0x75)
+#define T2CS0   0
+#define T2CS1   1
+#define T2PS0   2
+#define T2PS1   3
+#define T2PS2   4
+#define T2PS3   5
+#define T2DC0   6
+#define T2DC1   7
+
+#define T2IMR   _SFR_MEM8(0x76)
+#define T2OIM   0
+#define T2CIM   1
+
+/* Combine T3CNTL and T3CNTH */
+#define T3CNT   _SFR_MEM16(0x77)
+
+#define T3CNTL  _SFR_MEM8(0x77)
+#define T3CNTH  _SFR_MEM8(0x78)
+
+/* Combine T3CORL and T3CORH */
+#define T3COR   _SFR_MEM16(0x79)
+
+#define T3CORL  _SFR_MEM8(0x79)
+#define T3CORH  _SFR_MEM8(0x7A)
+
+/* Combine T3ICRL and T3ICRH */
+#define T3ICR   _SFR_MEM16(0x7B)
+
+#define T3ICRL  _SFR_MEM8(0x7B)
+#define T3ICRH  _SFR_MEM8(0x7C)
+
+#define T3MRA   _SFR_MEM8(0x7D)
+#define T3CS0   0
+#define T3CS1   1
+#define T3PS0   2
+#define T3PS1   3
+#define T3PS2   4
+
+#define T3MRB   _SFR_MEM8(0x7E)
+#define T3SCE   1
+#define T3CNC   2
+#define T3CE0   3
+#define T3CE1   4
+#define T3ICS0  5
+#define T3ICS1  6
+#define T3ICS2  7
+
+#define T3IMR   _SFR_MEM8(0x7F)
+#define T3OIM   0
+#define T3CIM   1
+#define T3CPIM  2
+
+/* Combine T4CNTL and T4CNTH */
+#define T4CNT   _SFR_MEM16(0x80)
+
+#define T4CNTL  _SFR_MEM8(0x80)
+#define T4CNTH  _SFR_MEM8(0x81)
+
+/* Combine T4CORL and T4CORH */
+#define T4COR   _SFR_MEM16(0x82)
+
+#define T4CORL  _SFR_MEM8(0x82)
+#define T4CORH  _SFR_MEM8(0x83)
+
+/* Combine T4ICRL and T4ICRH */
+#define T4ICR   _SFR_MEM16(0x84)
+
+#define T4ICRL  _SFR_MEM8(0x84)
+#define T4ICRH  _SFR_MEM8(0x85)
+
+#define T4MRA   _SFR_MEM8(0x86)
+#define T4CS0   0
+#define T4CS1   1
+#define T4PS0   2
+#define T4PS1   3
+#define T4PS2   4
+
+#define T4MRB   _SFR_MEM8(0x87)
+#define T4SCE   1
+#define T4CNC   2
+#define T4CE0   3
+#define T4CE1   4
+#define T4ICS0  5
+#define T4ICS1  6
+#define T4ICS2  7
+
+#define T4IMR   _SFR_MEM8(0x88)
+#define T4OIM   0
+#define T4CIM   1
+#define T4CPIM  2
+
+/* Reserved [0x89] */
+
+/* Combine T5OCRL and T5OCRH */
+#define T5OCR   _SFR_MEM16(0x8A)
+
+#define T5OCRL  _SFR_MEM8(0x8A)
+#define T5OCRH  _SFR_MEM8(0x8B)
+
+#define T5CCR   _SFR_MEM8(0x8C)
+#define T5CS0   0
+#define T5CS1   1
+#define T5CS2   2
+#define T5CTC   3
+
+/* Combine T5CNTL and T5CNTH */
+#define T5CNT   _SFR_MEM16(0x8D)
+
+#define T5CNTL  _SFR_MEM8(0x8D)
+#define T5CNTH  _SFR_MEM8(0x8E)
+
+#define T5IMR   _SFR_MEM8(0x8F)
+#define T5OIM   0
+#define T5CIM   1
+
+#define GTCCR   _SFR_MEM8(0x90)
+#define PSR10   0
+#define TSM     7
+
+#define SOTSB   _SFR_MEM8(0x91)
+#define CAROB   0
+#define AMPOB   1
+#define SYTOB   2
+#define MANOB   3
+#define WUPOB   4
+#define SFIDOB  5
+#define RROB    6
+#define WCOAO   7
+
+#define SOTSA   _SFR_MEM8(0x92)
+#define CAROA   0
+#define AMPOA   1
+#define SYTOA   2
+#define MANOA   3
+#define WUPOA   4
+#define SFIDOA  5
+#define RROA    6
+#define WCOBO   7
+
+#define SOTCB   _SFR_MEM8(0x93)
+#define CAROEB  0
+#define AMPOEB  1
+#define SYTOEB  2
+#define MANOEB  3
+#define WUPEB   4
+#define SFIDEB  5
+#define RROEB   6
+#define WCOAOE  7
+
+#define SOTCA   _SFR_MEM8(0x94)
+#define CAROEA  0
+#define AMPOEA  1
+#define SYTOEA  2
+#define MANOEA  3
+#define WUPEA   4
+#define SFIDEA  5
+#define RROEA   6
+#define WCOBOE  7
+
+#define TESRB   _SFR_MEM8(0x95)
+#define CRCOB   0
+#define EOTLB0  1
+#define EOTLB1  2
+
+#define TESRA   _SFR_MEM8(0x96)
+#define CRCOA   0
+#define EOTLA0  1
+#define EOTLA1  2
+
+/* Reserved [0x97] */
+
+#define RDSIMR  _SFR_MEM8(0x98)
+#define NBITAM  0
+#define NBITBM  1
+#define EOTAM   2
+#define EOTBM   3
+#define SOTAM   4
+#define SOTBM   5
+#define WCOAM   6
+#define WCOBM   7
+
+#define RDOCR   _SFR_MEM8(0x99)
+#define TMDS0   1
+#define TMDS1   2
+#define ETRPA   3
+#define ETRPB   4
+#define RDSIDA  5
+#define RDSIDB  6
+
+/* Reserved [0x9A] */
+
+#define TEMPL   _SFR_MEM8(0x9B)
+
+#define TEMPH   _SFR_MEM8(0x9C)
+
+#define SYCB    _SFR_MEM8(0x9D)
+#define SYCSB0  0
+#define SYCSB1  1
+#define SYCSB2  2
+#define SYCSB3  3
+#define SYTLB0  4
+#define SYTLB1  5
+#define SYTLB2  6
+#define SYTLB3  7
+
+#define SYCA    _SFR_MEM8(0x9E)
+#define SYCSA0  0
+#define SYCSA1  1
+#define SYCSA2  2
+#define SYCSA3  3
+#define SYTLA0  4
+#define SYTLA1  5
+#define SYTLA2  6
+#define SYTLA3  7
+
+#define RXFOB   _SFR_MEM8(0x9F)
+
+#define RXFOA   _SFR_MEM8(0xA0)
+
+#define DMMB    _SFR_MEM8(0xA1)
+#define DMATB0  0
+#define DMATB1  1
+#define DMATB2  2
+#define DMATB3  3
+#define DMATB4  4
+#define DMPB    5
+#define DMHB    6
+#define DMNEB   7
+
+#define DMMA    _SFR_MEM8(0xA2)
+#define DMATA0  0
+#define DMATA1  1
+#define DMATA2  2
+#define DMATA3  3
+#define DMATA4  4
+#define DMPA    5
+#define DMHA    6
+#define DMNEA   7
+
+#define DMCDB   _SFR_MEM8(0xA3)
+#define DMCLB0  0
+#define DMCLB1  1
+#define DMCLB2  2
+#define DMCLB3  3
+#define DMCLB4  4
+#define DMCTB0  5
+#define DMCTB1  6
+#define DMCTB2  7
+
+#define DMCDA   _SFR_MEM8(0xA4)
+#define DMCLA0  0
+#define DMCLA1  1
+#define DMCLA2  2
+#define DMCLA3  3
+#define DMCLA4  4
+#define DMCTA0  5
+#define DMCTA1  6
+#define DMCTA2  7
+
+#define DMCRB   _SFR_MEM8(0xA5)
+#define DMPGB0  0
+#define DMPGB1  1
+#define DMPGB2  2
+#define DMPGB3  3
+#define DMPGB4  4
+#define SASKB   5
+#define SY1TB   6
+#define DMARB   7
+
+#define DMCRA   _SFR_MEM8(0xA6)
+#define DMPGA0  0
+#define DMPGA1  1
+#define DMPGA2  2
+#define DMPGA3  3
+#define DMPGA4  4
+#define SASKA   5
+#define SY1TA   6
+#define DMARA   7
+
+#define DMDRB   _SFR_MEM8(0xA7)
+#define DMAB0   0
+#define DMAB1   1
+#define DMAB2   2
+#define DMAB3   3
+#define DMDNB0  4
+#define DMDNB1  5
+#define DMDNB2  6
+#define DMDNB3  7
+
+#define DMDRA   _SFR_MEM8(0xA8)
+#define DMAA0   0
+#define DMAA1   1
+#define DMAA2   2
+#define DMAA3   3
+#define DMDNA0  4
+#define DMDNA1  5
+#define DMDNA2  6
+#define DMDNA3  7
+
+#define CHCR    _SFR_MEM8(0xA9)
+#define BWM0    0
+#define BWM1    1
+#define BWM2    2
+#define BWM3    3
+
+#define CHDN    _SFR_MEM8(0xAA)
+#define BBDN0   0
+#define BBDN1   1
+#define BBDN2   2
+#define BBDN3   3
+#define BBDN4   4
+#define ADCDN   5
+
+#define SFIDCB  _SFR_MEM8(0xAB)
+#define SFIDTB0 0
+#define SFIDTB1 1
+#define SFIDTB2 2
+#define SFIDTB3 3
+#define SFIDTB4 4
+#define SEMEB   7
+
+#define SFIDLB  _SFR_MEM8(0xAC)
+#define SFIDLB0 0
+#define SFIDLB1 1
+#define SFIDLB2 2
+#define SFIDLB3 3
+#define SFIDLB4 4
+#define SFIDLB5 5
+
+#define WUPTB   _SFR_MEM8(0xAD)
+#define WUPTB0  0
+#define WUPTB1  1
+#define WUPTB2  2
+#define WUPTB3  3
+#define WUPTB4  4
+
+#define WUPLB   _SFR_MEM8(0xAE)
+#define WUPLB0  0
+#define WUPLB1  1
+#define WUPLB2  2
+#define WUPLB3  3
+#define WUPLB4  4
+#define WUPLB5  5
+
+#define SFID1B  _SFR_MEM8(0xAF)
+
+#define SFID2B  _SFR_MEM8(0xB0)
+
+#define SFID3B  _SFR_MEM8(0xB1)
+
+#define SFID4B  _SFR_MEM8(0xB2)
+
+#define WUP1B   _SFR_MEM8(0xB3)
+
+#define WUP2B   _SFR_MEM8(0xB4)
+
+#define WUP3B   _SFR_MEM8(0xB5)
+
+#define WUP4B   _SFR_MEM8(0xB6)
+
+#define SFIDCA  _SFR_MEM8(0xB7)
+#define SFIDTA0 0
+#define SFIDTA1 1
+#define SFIDTA2 2
+#define SFIDTA3 3
+#define SFIDTA4 4
+#define SEMEA   7
+
+#define SFIDLA  _SFR_MEM8(0xB8)
+#define SFIDLA0 0
+#define SFIDLA1 1
+#define SFIDLA2 2
+#define SFIDLA3 3
+#define SFIDLA4 4
+#define SFIDLA5 5
+
+#define WUPTA   _SFR_MEM8(0xB9)
+#define WUPTA0  0
+#define WUPTA1  1
+#define WUPTA2  2
+#define WUPTA3  3
+#define WUPTA4  4
+
+#define WUPLA   _SFR_MEM8(0xBA)
+#define WUPLA0  0
+#define WUPLA1  1
+#define WUPLA2  2
+#define WUPLA3  3
+#define WUPLA4  4
+#define WUPLA5  5
+
+#define SFID1A  _SFR_MEM8(0xBB)
+
+#define SFID2A  _SFR_MEM8(0xBC)
+
+#define SFID3A  _SFR_MEM8(0xBD)
+
+#define SFID4A  _SFR_MEM8(0xBE)
+
+#define WUP1A   _SFR_MEM8(0xBF)
+
+#define WUP2A   _SFR_MEM8(0xC0)
+
+#define WUP3A   _SFR_MEM8(0xC1)
+
+#define WUP4A   _SFR_MEM8(0xC2)
+
+#define CLKOD   _SFR_MEM8(0xC3)
+
+#define CLKOCR  _SFR_MEM8(0xC4)
+#define CLKOS0  0
+#define CLKOS1  1
+#define CLKOEN  2
+
+#define XFUSE   _SFR_MEM8(0xC5)
+
+#define SRCCAL  _SFR_MEM8(0xC6)
+#define SRCCAL0 0
+#define SRCCAL1 1
+#define SRCCAL2 2
+#define SRCCAL3 3
+#define SRCCAL4 4
+#define SRCCAL5 5
+#define SRCTC0  6
+#define SRCTC1  7
+
+#define FRCCAL  _SFR_MEM8(0xC7)
+#define FRCCAL0 0
+#define FRCCAL1 1
+#define FRCCAL2 2
+#define FRCCAL3 3
+#define FRCCAL4 4
+#define FRCTC   5
+
+#define CMSR    _SFR_MEM8(0xC8)
+#define ECF     0
+
+#define CMOCR   _SFR_MEM8(0xC9)
+#define FRCAO   0
+#define SRCAO   1
+#define FRCACT  2
+#define SRCACT  3
+
+#define SUPFR   _SFR_MEM8(0xCA)
+#define AVCCRF  0
+#define AVCCLF  1
+
+#define SUPCR   _SFR_MEM8(0xCB)
+#define AVCCRM  0
+#define AVCCLM  1
+#define PVEN    2
+#define DVDIS   4
+#define AVEN    5
+#define AVDIC   6
+
+#define SUPCA1  _SFR_MEM8(0xCC)
+#define PV22    2
+#define PVDIC   3
+#define PVCAL0  4
+#define PVCAL1  5
+#define PVCAL2  6
+#define PVCAL3  7
+
+#define SUPCA2  _SFR_MEM8(0xCD)
+#define BGCAL0  0
+#define BGCAL1  1
+#define BGCAL2  2
+#define BGCAL3  3
+
+#define SUPCA3  _SFR_MEM8(0xCE)
+#define ACAL4   0
+#define ACAL5   1
+#define ACAL6   2
+#define ACAL7   3
+#define DCAL4   4
+#define DCAL5   5
+#define DCAL6   6
+
+#define SUPCA4  _SFR_MEM8(0xCF)
+#define ACAL0   0
+#define ACAL1   1
+#define ACAL2   2
+#define ACAL3   3
+#define DCAL0   4
+#define DCAL1   5
+#define DCAL2   6
+#define DCAL3   7
+
+#define CALRDY  _SFR_MEM8(0xD0)
+
+#define VMCAL   _SFR_MEM8(0xD1)
+#define VMCAL0  0
+#define VMCAL1  1
+#define VMCAL2  2
+
+#define DFS     _SFR_MEM8(0xD2)
+#define DFFLRF  0
+#define DFUFL   1
+#define DFOFL   2
+
+/* Combine DFTLL and DFTLH */
+#define DFTL    _SFR_MEM16(0xD3)
+
+#define DFTLL   _SFR_MEM8(0xD3)
+#define DFTLH   _SFR_MEM8(0xD4)
+
+#define DFL     _SFR_MEM8(0xD5)
+#define DFFLS0  0
+#define DFFLS1  1
+#define DFFLS2  2
+#define DFFLS3  3
+#define DFFLS4  4
+#define DFFLS5  5
+#define DFCLR   7
+
+#define DFWP    _SFR_MEM8(0xD6)
+#define DFWP0   0
+#define DFWP1   1
+#define DFWP2   2
+#define DFWP3   3
+#define DFWP4   4
+#define DFWP5   5
+
+#define DFRP    _SFR_MEM8(0xD7)
+#define DFRP0   0
+#define DFRP1   1
+#define DFRP2   2
+#define DFRP3   3
+#define DFRP4   4
+#define DFRP5   5
+
+#define DFD     _SFR_MEM8(0xD8)
+
+#define DFI     _SFR_MEM8(0xD9)
+#define DFFLIM  0
+#define DFERIM  1
+
+#define DFC     _SFR_MEM8(0xDA)
+#define DFFLC0  0
+#define DFFLC1  1
+#define DFFLC2  2
+#define DFFLC3  3
+#define DFFLC4  4
+#define DFFLC5  5
+#define DFDRA   7
+
+#define SFS     _SFR_MEM8(0xDB)
+#define SFFLRF  0
+#define SFUFL   1
+#define SFOFL   2
+
+#define SFL     _SFR_MEM8(0xDC)
+#define SFFLS0  0
+#define SFFLS1  1
+#define SFFLS2  2
+#define SFFLS3  3
+#define SFFLS4  4
+#define SFCLR   7
+
+#define SFWP    _SFR_MEM8(0xDD)
+#define SFWP0   0
+#define SFWP1   1
+#define SFWP2   2
+#define SFWP3   3
+#define SFWP4   4
+
+#define SFRP    _SFR_MEM8(0xDE)
+#define SFRP0   0
+#define SFRP1   1
+#define SFRP2   2
+#define SFRP3   3
+#define SFRP4   4
+
+#define SFD     _SFR_MEM8(0xDF)
+
+#define SFI     _SFR_MEM8(0xE0)
+#define SFFLIM  0
+#define SFERIM  1
+
+#define SFC     _SFR_MEM8(0xE1)
+#define SFFLC0  0
+#define SFFLC1  1
+#define SFFLC2  2
+#define SFFLC3  3
+#define SFFLC4  4
+#define SFDRA   7
+
+#define SSMCR   _SFR_MEM8(0xE2)
+#define SSMTX   0
+#define SSMTM   1
+#define SSMTGE  2
+#define SSMTPE  3
+#define SSMPVE  4
+#define SSMTAE  5
+#define SETRPA  6
+#define SETRPB  7
+
+#define SSMRCR  _SFR_MEM8(0xE3)
+#define SSMPA   0
+#define SSMPB   1
+#define SSMADA  2
+#define SSMADB  3
+#define SSMPVS  4
+#define SSMIFA  5
+#define SSMIDSE 6
+#define SSMTMOE 7
+
+#define SSMFBR  _SFR_MEM8(0xE4)
+#define SSMFID0 0
+#define SSMFID1 1
+#define SSMFID2 2
+#define SSMDFDT 3
+#define SSMHADT 4
+#define SSMPLDT 5
+
+#define SSMRR   _SFR_MEM8(0xE5)
+#define SSMR    0
+#define SSMST   1
+
+#define SSMSR   _SFR_MEM8(0xE6)
+#define SSMESM0 0
+#define SSMESM1 1
+#define SSMESM2 2
+#define SSMESM3 3
+#define SSMERR  7
+
+#define SSMIFR  _SFR_MEM8(0xE7)
+#define SSMIF   0
+
+#define SSMIMR  _SFR_MEM8(0xE8)
+#define SSMIM   0
+
+#define MSMSTR  _SFR_MEM8(0xE9)
+#define SSMMST0 0
+#define SSMMST1 1
+#define SSMMST2 2
+#define SSMMST3 3
+#define SSMMST4 4
+
+#define SSMSTR  _SFR_MEM8(0xEA)
+#define SSMSTA0 0
+#define SSMSTA1 1
+#define SSMSTA2 2
+#define SSMSTA3 3
+#define SSMSTA4 4
+#define SSMSTA5 5
+
+#define SSMXSR  _SFR_MEM8(0xEB)
+#define SSMSTB0 0
+#define SSMSTB1 1
+#define SSMSTB2 2
+#define SSMSTB3 3
+#define SSMSTB4 4
+#define SSMSTB5 5
+
+#define MSMCR1  _SFR_MEM8(0xEC)
+#define MSMSM00 0
+#define MSMSM01 1
+#define MSMSM02 2
+#define MSMSM03 3
+#define MSMSM10 4
+#define MSMSM11 5
+#define MSMSM12 6
+#define MSMSM13 7
+
+#define MSMCR2  _SFR_MEM8(0xED)
+#define MSMSM20 0
+#define MSMSM21 1
+#define MSMSM22 2
+#define MSMSM23 3
+#define MSMSM30 4
+#define MSMSM31 5
+#define MSMSM32 6
+#define MSMSM33 7
+
+#define MSMCR3  _SFR_MEM8(0xEE)
+#define MSMSM40 0
+#define MSMSM41 1
+#define MSMSM42 2
+#define MSMSM43 3
+#define MSMSM50 4
+#define MSMSM51 5
+#define MSMSM52 6
+#define MSMSM53 7
+
+#define MSMCR4  _SFR_MEM8(0xEF)
+#define MSMSM60 0
+#define MSMSM61 1
+#define MSMSM62 2
+#define MSMSM63 3
+#define MSMSM70 4
+#define MSMSM71 5
+#define MSMSM72 6
+#define MSMSM73 7
+
+#define GTCR    _SFR_MEM8(0xF0)
+#define RXTEHA  0
+#define GAPMA   1
+#define DARA    2
+#define IWUPA   3
+#define RXTEHB  4
+#define GAPMB   5
+#define DARB    6
+#define IWUPB   7
+
+#define SOTC1A  _SFR_MEM8(0xF1)
+#define CAROEA1 0
+#define AMPOEA1 1
+#define SYTOEA1 2
+#define MANOEA1 3
+#define WUPEA1  4
+#define SFIDEA1 5
+#define RROEA1  6
+#define WCOBOE1 7
+
+#define SOTC2A  _SFR_MEM8(0xF2)
+#define CAROEA2 0
+#define AMPOEA2 1
+#define SYTOEA2 2
+#define MANOEA2 3
+#define WUPEA2  4
+#define SFIDEA2 5
+#define RROEA2  6
+#define WCOBOE2 7
+
+#define SOTC1B  _SFR_MEM8(0xF3)
+#define CAROEB1 0
+#define AMPOEB1 1
+#define SYTOEB1 2
+#define MANOEB1 3
+#define WUPEB1  4
+#define SFIDEB1 5
+#define RROEB1  6
+#define WCOAOE1 7
+
+#define SOTC2B  _SFR_MEM8(0xF4)
+#define CAROEB2 0
+#define AMPOEB2 1
+#define SYTOEB2 2
+#define MANOEB2 3
+#define WUPEB2  4
+#define SFIDEB2 5
+#define RROEB2  6
+#define WCOAOE2 7
+
+#define EOTC1A  _SFR_MEM8(0xF5)
+#define CARFEA1 0
+#define AMPFEA1 1
+#define SYTFEA1 2
+#define MANFEA1 3
+#define TMOFEA1 4
+#define TELREA1 5
+#define RRFEA1  6
+#define EOTBFE1 7
+
+#define EOTC2A  _SFR_MEM8(0xF6)
+#define CARFEA2 0
+#define AMPFEA2 1
+#define SYTFEA2 2
+#define MANFEA2 3
+#define TMOFEA2 4
+#define TELREA2 5
+#define RRFEA2  6
+#define EOTBFE2 7
+
+#define EOTC3A  _SFR_MEM8(0xF7)
+#define CARFEA3 0
+#define AMPFEA3 1
+#define SYTFEA3 2
+#define MANFEA3 3
+#define TMOFEA3 4
+#define TELREA3 5
+#define RRFEA3  6
+#define EOTBFE3 7
+
+#define EOTC1B  _SFR_MEM8(0xF8)
+#define CARFEB1 0
+#define AMPFEB1 1
+#define SYTFEB1 2
+#define MANFEB1 3
+#define TMOFEB1 4
+#define TELREB1 5
+#define RRFEB1  6
+#define EOTAFE1 7
+
+#define EOTC2B  _SFR_MEM8(0xF9)
+#define CARFEB2 0
+#define AMPFEB2 1
+#define SYTFEB2 2
+#define MANFEB2 3
+#define TMOFEB2 4
+#define TELREB2 5
+#define RRFEB2  6
+#define EOTAFE2 7
+
+#define EOTC3B  _SFR_MEM8(0xFA)
+#define CARFEB3 0
+#define AMPFEB3 1
+#define SYTFEB3 2
+#define MANFEB3 3
+#define TMOFEB3 4
+#define TELREB3 5
+#define RRFEB3  6
+#define EOTAFE3 7
+
+#define WCOTOA  _SFR_MEM8(0xFB)
+
+#define WCOTOB  _SFR_MEM8(0xFC)
+
+#define SOTTOA  _SFR_MEM8(0xFD)
+
+#define SOTTOB  _SFR_MEM8(0xFE)
+
+#define SSMFCR  _SFR_MEM8(0xFF)
+#define SSMIDSO 0
+#define SSMIDSF 1
+
+#define FESR    _SFR_MEM8(0x100)
+#define LBSAT   0
+#define HBSAT   1
+#define XRDY    2
+#define PLCK    3
+#define ANTS    4
+
+#define FEEN1   _SFR_MEM8(0x101)
+#define PLEN    0
+#define PLCAL   1
+#define XTOEN   2
+#define LNAEN   3
+#define ADEN    4
+#define ADCLK   5
+#define PLSP1   6
+#define ATEN    7
+
+#define FEEN2   _SFR_MEM8(0x102)
+#define SDRX    0
+#define SDTX    1
+#define PAEN    2
+#define TMPM    3
+#define PLPEN   4
+#define XTPEN   5
+#define CPBIA   6
+
+#define FELNA   _SFR_MEM8(0x103)
+#define LBH0    0
+#define LBH1    1
+#define LBH2    2
+#define LBH3    3
+#define LBL0    4
+#define LBL1    5
+#define LBL2    6
+#define LBL3    7
+
+#define FEAT    _SFR_MEM8(0x104)
+#define ANTN0   0
+#define ANTN1   1
+#define ANTN2   2
+#define ANTN3   3
+
+#define FEPAC   _SFR_MEM8(0x105)
+
+#define FEVCT   _SFR_MEM8(0x106)
+#define FEVCT0  0
+#define FEVCT1  1
+#define FEVCT2  2
+#define FEVCT3  3
+
+#define FEBT    _SFR_MEM8(0x107)
+#define CTN20   0
+#define CTN21   1
+#define RTN20   2
+#define RTN21   3
+
+#define FEMS    _SFR_MEM8(0x108)
+#define PLLS0   0
+#define PLLS1   1
+#define PLLS2   2
+#define PLLS3   3
+#define PLLM0   4
+#define PLLM1   5
+#define PLLM2   6
+#define PLLM3   7
+
+#define FETN4   _SFR_MEM8(0x109)
+#define CTN40   0
+#define CTN41   1
+#define CTN42   2
+#define CTN43   3
+#define RTN40   4
+#define RTN41   5
+#define RTN42   6
+#define RTN43   7
+
+#define FECR    _SFR_MEM8(0x10A)
+#define LBNHB   0
+#define S4N3    1
+#define ANDP    2
+#define ADHS    3
+#define PLCKG   4
+#define ANPS    5
+
+#define FEVCO   _SFR_MEM8(0x10B)
+#define CPCC0   0
+#define CPCC1   1
+#define CPCC2   2
+#define CPCC3   3
+#define VCOB0   4
+#define VCOB1   5
+#define VCOB2   6
+#define VCOB3   7
+
+#define FEALR   _SFR_MEM8(0x10C)
+#define RNGE0   0
+#define RNGE1   1
+
+#define FEANT   _SFR_MEM8(0x10D)
+#define LVLC0   0
+#define LVLC1   1
+#define LVLC2   2
+#define LVLC3   3
+
+#define FEBIA   _SFR_MEM8(0x10E)
+#define IFAEN   7
+
+/* Reserved [0x10F..0x11F] */
+
+#define TMFSM   _SFR_MEM8(0x120)
+#define TMSSM0  0
+#define TMSSM1  1
+#define TMSSM2  2
+#define TMSSM3  3
+#define TMMSM0  4
+#define TMMSM1  5
+#define TMMSM2  6
+
+/* Combine TMCRL and TMCRH */
+#define TMCR    _SFR_MEM16(0x121)
+
+#define TMCRL   _SFR_MEM8(0x121)
+#define TMCRH   _SFR_MEM8(0x122)
+
+#define TMCSB   _SFR_MEM8(0x123)
+
+/* Combine TMCIL and TMCIH */
+#define TMCI    _SFR_MEM16(0x124)
+
+#define TMCIL   _SFR_MEM8(0x124)
+#define TMCIH   _SFR_MEM8(0x125)
+
+/* Combine TMCPL and TMCPH */
+#define TMCP    _SFR_MEM16(0x126)
+
+#define TMCPL   _SFR_MEM8(0x126)
+#define TMCPH   _SFR_MEM8(0x127)
+
+#define TMSHR   _SFR_MEM8(0x128)
+
+/* Combine TMTLL and TMTLH */
+#define TMTL    _SFR_MEM16(0x129)
+
+#define TMTLL   _SFR_MEM8(0x129)
+#define TMTLH   _SFR_MEM8(0x12A)
+
+#define TMSSC   _SFR_MEM8(0x12B)
+#define TMSSP0  0
+#define TMSSP1  1
+#define TMSSP2  2
+#define TMSSP3  3
+#define TMSSL0  4
+#define TMSSL1  5
+#define TMSSL2  6
+#define TMSSH   7
+
+#define TMSR    _SFR_MEM8(0x12C)
+#define TMTCF   0
+
+#define TMCR2   _SFR_MEM8(0x12D)
+#define TMCRCE  0
+#define TMCRCL0 1
+#define TMCRCL1 2
+#define TMNRZE  3
+#define TMPOL   4
+#define TMSSE   5
+#define TMMSB   6
+
+#define TMCR1   _SFR_MEM8(0x12E)
+#define TMPIS0  0
+#define TMPIS1  1
+#define TMPIS2  2
+#define TMSCS   3
+#define TMCIM   4
+
+#define RXBC1   _SFR_MEM8(0x12F)
+#define RXCEA   0
+#define RXCBLA0 1
+#define RXCBLA1 2
+#define RXMSBA  3
+#define RXCEB   4
+#define RXCBLB0 5
+#define RXCBLB1 6
+#define RXMSBB  7
+
+#define RXBC2   _SFR_MEM8(0x130)
+#define RXBPB   0
+#define RXBF    1
+#define RXBCLR  2
+
+#define RXTLLB  _SFR_MEM8(0x131)
+
+#define RXTLHB  _SFR_MEM8(0x132)
+#define RXTLHB0 0
+#define RXTLHB1 1
+#define RXTLHB2 2
+#define RXTLHB3 3
+
+#define RXCRLB  _SFR_MEM8(0x133)
+
+#define RXCRHB  _SFR_MEM8(0x134)
+
+#define RXCSBB  _SFR_MEM8(0x135)
+
+#define RXCILB  _SFR_MEM8(0x136)
+
+#define RXCIHB  _SFR_MEM8(0x137)
+
+#define RXCPLB  _SFR_MEM8(0x138)
+
+#define RXCPHB  _SFR_MEM8(0x139)
+
+#define RXDSB   _SFR_MEM8(0x13A)
+
+#define RXTLLA  _SFR_MEM8(0x13B)
+
+#define RXTLHA  _SFR_MEM8(0x13C)
+#define RXTLHA0 0
+#define RXTLHA1 1
+#define RXTLHA2 2
+#define RXTLHA3 3
+
+#define RXCRLA  _SFR_MEM8(0x13D)
+
+#define RXCRHA  _SFR_MEM8(0x13E)
+
+#define RXCSBA  _SFR_MEM8(0x13F)
+
+#define RXCILA  _SFR_MEM8(0x140)
+
+#define RXCIHA  _SFR_MEM8(0x141)
+
+#define RXCPLA  _SFR_MEM8(0x142)
+
+#define RXCPHA  _SFR_MEM8(0x143)
+
+#define RXDSA   _SFR_MEM8(0x144)
+
+#define CRCCR   _SFR_MEM8(0x145)
+#define CRCRS   0
+#define REFLI   1
+#define REFLO   2
+
+#define CRCDOR  _SFR_MEM8(0x146)
+
+#define IDB0    _SFR_MEM8(0x147)
+
+#define IDB1    _SFR_MEM8(0x148)
+
+#define IDB2    _SFR_MEM8(0x149)
+
+#define IDB3    _SFR_MEM8(0x14A)
+
+#define IDC     _SFR_MEM8(0x14B)
+#define IDL0    0
+#define IDL1    1
+#define IDBO0   2
+#define IDBO1   3
+#define IDFIM   5
+#define IDCLR   6
+#define IDCE    7
+
+#define IDS     _SFR_MEM8(0x14C)
+#define IDOK    0
+#define IDFULL  1
+
+#define RSSAV   _SFR_MEM8(0x14D)
+
+#define RSSPK   _SFR_MEM8(0x14E)
+
+#define RSSL    _SFR_MEM8(0x14F)
+
+#define RSSH    _SFR_MEM8(0x150)
+
+#define RSSC    _SFR_MEM8(0x151)
+#define RSUP0   0
+#define RSUP1   1
+#define RSUP2   2
+#define RSUP3   3
+#define RSWLH   4
+#define RSHRX   5
+#define RSPKF   6
+
+#define DBCR    _SFR_MEM8(0x152)
+#define DBMD    0
+#define DBCS    1
+#define DBTMS   2
+#define DBHA    3
+
+#define DBTC    _SFR_MEM8(0x153)
+
+#define DBENB   _SFR_MEM8(0x154)
+
+#define DBENC   _SFR_MEM8(0x155)
+
+#define DBGSW   _SFR_MEM8(0x156)
+#define DBGGS0  0
+#define DBGGS1  1
+#define DBGGS2  2
+#define DBGGS3  3
+#define CPBFOS0 4
+#define CPBFOS1 5
+#define CPBF    6
+#define DBGSE   7
+
+#define SFFR    _SFR_MEM8(0x157)
+#define RFL0    0
+#define RFL1    1
+#define RFL2    2
+#define RFC     3
+#define TFL0    4
+#define TFL1    5
+#define TFL2    6
+#define TFC     7
+
+#define SFIR    _SFR_MEM8(0x158)
+#define RIL0    0
+#define RIL1    1
+#define RIL2    2
+#define SRIE    3
+#define TIL0    4
+#define TIL1    5
+#define TIL2    6
+#define STIE    7
+
+#define EECR2   _SFR_MEM8(0x159)
+#define EEBRE   0
+
+#define PGMST   _SFR_MEM8(0x15A)
+#define PGMSYN0 0
+#define PGMSYN1 1
+#define PGMSYN2 2
+#define PGMSYN3 3
+#define PGMSYN4 4
+
+#define EEST    _SFR_MEM8(0x15B)
+#define EESYN0  0
+#define EESYN1  1
+#define EESYN2  2
+#define EESYN3  3
+
+#define RSIFG   _SFR_MEM8(0x15C)
+
+#define RSLDV   _SFR_MEM8(0x15D)
+
+#define RSHDV   _SFR_MEM8(0x15E)
+
+#define RSCOM   _SFR_MEM8(0x15F)
+#define RSDC    0
+#define RSIFC   1
+
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
+
+/* External Interrupt Request 1 */
+#define INT1_vect            _VECTOR(2)
+#define INT1_vect_num        2
+
+/* Pin Change Interrupt Request 0 */
+#define PCI0_vect            _VECTOR(3)
+#define PCI0_vect_num        3
+
+/* Pin Change Interrupt Request 1 */
+#define PCI1_vect            _VECTOR(4)
+#define PCI1_vect_num        4
+
+/* Voltage Monitoring Interrupt */
+#define VMON_vect            _VECTOR(5)
+#define VMON_vect_num        5
+
+/* AVCC Reset Interrupt */
+#define AVCCR_vect            _VECTOR(6)
+#define AVCCR_vect_num        6
+
+/* AVCC Low Interrupt */
+#define AVCCL_vect            _VECTOR(7)
+#define AVCCL_vect_num        7
+
+/* Timer 0 Interval Interrupt */
+#define T0INT_vect            _VECTOR(8)
+#define T0INT_vect_num        8
+
+/* Timer/Counter1 Compare Match Interrupt */
+#define T1COMP_vect            _VECTOR(9)
+#define T1COMP_vect_num        9
+
+/* Timer/Counter1 Overflow Interrupt */
+#define T1OVF_vect            _VECTOR(10)
+#define T1OVF_vect_num        10
+
+/* Timer/Counter2 Compare Match Interrupt */
+#define T2COMP_vect            _VECTOR(11)
+#define T2COMP_vect_num        11
+
+/* Timer/Counter2 Overflow Interrupt */
+#define T2OVF_vect            _VECTOR(12)
+#define T2OVF_vect_num        12
+
+/* Timer/Counter3 Capture Event Interrupt */
+#define T3CAP_vect            _VECTOR(13)
+#define T3CAP_vect_num        13
+
+/* Timer/Counter3 Compare Match Interrupt */
+#define T3COMP_vect            _VECTOR(14)
+#define T3COMP_vect_num        14
+
+/* Timer/Counter3 Overflow Interrupt */
+#define T3OVF_vect            _VECTOR(15)
+#define T3OVF_vect_num        15
+
+/* Timer/Counter4 Capture Event Interrupt */
+#define T4CAP_vect            _VECTOR(16)
+#define T4CAP_vect_num        16
+
+/* Timer/Counter4 Compare Match Interrupt */
+#define T4COMP_vect            _VECTOR(17)
+#define T4COMP_vect_num        17
+
+/* Timer/Counter4 Overflow Interrupt */
+#define T4OVF_vect            _VECTOR(18)
+#define T4OVF_vect_num        18
+
+/* Timer/Counter5 Compare Match Interrupt */
+#define T5COMP_vect            _VECTOR(19)
+#define T5COMP_vect_num        19
+
+/* Timer/Counter5 Overflow Interrupt */
+#define T5OVF_vect            _VECTOR(20)
+#define T5OVF_vect_num        20
+
+/* SPI Serial Transfer Complete Interrupt */
+#define SPI_vect            _VECTOR(21)
+#define SPI_vect_num        21
+
+/* SPI Rx Buffer Interrupt */
+#define SRX_FIFO_vect            _VECTOR(22)
+#define SRX_FIFO_vect_num        22
+
+/* SPI Tx Buffer Interrupt */
+#define STX_FIFO_vect            _VECTOR(23)
+#define STX_FIFO_vect_num        23
+
+/* Sequencer State Machine Interrupt */
+#define SSM_vect            _VECTOR(24)
+#define SSM_vect_num        24
+
+/* Data FIFO fill level reached Interrupt */
+#define DFFLR_vect            _VECTOR(25)
+#define DFFLR_vect_num        25
+
+/* Data FIFO overflow or underflow error Interrupt */
+#define DFOUE_vect            _VECTOR(26)
+#define DFOUE_vect_num        26
+
+/* RSSI/Preamble FIFO fill level reached Interrupt */
+#define SFFLR_vect            _VECTOR(27)
+#define SFFLR_vect_num        27
+
+/* RSSI/Preamble FIFO overflow or underflow error Interrupt */
+#define SFOUE_vect            _VECTOR(28)
+#define SFOUE_vect_num        28
+
+/* Tx Modulator Telegram Finish Interrupt */
+#define TMTCF_vect            _VECTOR(29)
+#define TMTCF_vect_num        29
+
+/* UHF receiver wake up ok on Rx path B */
+#define UHF_WCOB_vect            _VECTOR(30)
+#define UHF_WCOB_vect_num        30
+
+/* UHF receiver wake up ok on Rx path A */
+#define UHF_WCOA_vect            _VECTOR(31)
+#define UHF_WCOA_vect_num        31
+
+/* UHF receiver start of telegram ok on Rx path B */
+#define UHF_SOTB_vect            _VECTOR(32)
+#define UHF_SOTB_vect_num        32
+
+/* UHF receiver start of telegram ok on Rx path A */
+#define UHF_SOTA_vect            _VECTOR(33)
+#define UHF_SOTA_vect_num        33
+
+/* UHF receiver end of telegram on Rx path B */
+#define UHF_EOTB_vect            _VECTOR(34)
+#define UHF_EOTB_vect_num        34
+
+/* UHF receiver end of telegram on Rx path A */
+#define UHF_EOTA_vect            _VECTOR(35)
+#define UHF_EOTA_vect_num        35
+
+/* UHF receiver new bit on Rx path B */
+#define UHF_NBITB_vect            _VECTOR(36)
+#define UHF_NBITB_vect_num        36
+
+/* UHF receiver new bit on Rx path A */
+#define UHF_NBITA_vect            _VECTOR(37)
+#define UHF_NBITA_vect_num        37
+
+/* External input Clock monitoring Interrupt */
+#define EXCM_vect            _VECTOR(38)
+#define EXCM_vect_num        38
+
+/* EEPROM Ready Interrupt */
+#define ERDY_vect            _VECTOR(39)
+#define ERDY_vect_num        39
+
+/* Store Program Memory Ready */
+#define SPMR_vect            _VECTOR(40)
+#define SPMR_vect_num        40
+
+/* IDSCAN Full Interrupt */
+#define IDFULL_vect            _VECTOR(41)
+#define IDFULL_vect_num        41
+
+#define _VECTORS_SIZE 168
+
+
+/* Constants */
+
+#define SPM_PAGESIZE 64
+#define FLASHSTART   0x8000
+#define FLASHEND     0xCFFF
+#define RAMSTART     0x0200
+#define RAMSIZE      1024
+#define RAMEND       0x05FF
+#define E2START     0
+#define E2SIZE      1152
+#define E2PAGESIZE  16
+#define E2END       0x047F
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 1
+
+/* Fuse Byte */
+#define FUSE_CKDIV8 (unsigned char)~_BV(128)
+#define FUSE_DWEN (unsigned char)~_BV(64)
+#define FUSE_SPIEN (unsigned char)~_BV(32)
+#define FUSE_WDTON (unsigned char)~_BV(16)
+#define FUSE_EESAVE (unsigned char)~_BV(8)
+#define FUSE_BOOTRST (unsigned char)~_BV(4)
+#define FUSE_RSTDISBL (unsigned char)~_BV(2)
+#define FUSE_EXTCLKEN (unsigned char)~_BV(1)
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x95
+#define SIGNATURE_2 0x63
+
+
+#endif /* #ifdef _AVR_ATA5833_H_INCLUDED */
+
diff -urN avr-libc-1.8.0.orig/include/avr/ioa6285.h avr-libc-1.8.0/include/avr/ioa6285.h
--- avr-libc-1.8.0.orig/include/avr/ioa6285.h	1970-01-01 01:00:00.000000000 +0100
+++ avr-libc-1.8.0/include/avr/ioa6285.h	2013-06-12 12:21:34.000000000 +0200
@@ -0,0 +1,706 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2013 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATA6285_H_INCLUDED
+#define _AVR_ATA6285_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "ioa6285.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDRB7   7
+#define DDRB6   6
+#define DDRB5   5
+#define DDRB4   4
+#define DDRB3   3
+#define DDRB2   2
+#define DDRB1   1
+#define DDRB0   0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDRC7   7
+#define DDRC6   6
+#define DDRC5   5
+#define DDRC4   4
+#define DDRC3   3
+#define DDRC2   2
+#define DDRC1   1
+#define DDRC0   0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PORTC7  7
+#define PORTC6  6
+#define PORTC5  5
+#define PORTC4  4
+#define PORTC3  3
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDRD7   7
+#define DDRD6   6
+#define DDRD5   5
+#define DDRD4   4
+#define DDRD3   3
+#define DDRD2   2
+#define DDRD1   1
+#define DDRD0   0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PORTD7  7
+#define PORTD6  6
+#define PORTD5  5
+#define PORTD4  4
+#define PORTD3  3
+#define PORTD2  2
+#define PORTD1  1
+#define PORTD0  0
+
+/* Reserved [0x0C..0x0E] */
+
+#define CMCR    _SFR_IO8(0x0F)
+#define CMM0    0
+#define CMM1    1
+#define SRCD    2
+#define CMONEN  3
+#define CCS     4
+#define ECINS   5
+#define CMCCE   7
+
+#define CMSR    _SFR_IO8(0x10)
+#define ECF     0
+
+#define T2CRA   _SFR_IO8(0x11)
+#define T2OTM   0
+#define T2CTM   1
+#define T2CR    2
+#define T2CRM   3
+#define T2ICS   5
+#define T2TS    6
+#define T2E     7
+
+#define T2CRB   _SFR_IO8(0x12)
+#define T2SCE   0
+
+/* Reserved [0x13] */
+
+#define T3CRA   _SFR_IO8(0x14)
+#define T3AC    0
+#define T3SCE   1
+#define T3CR    2
+#define T3TS    6
+#define T3E     7
+
+/* Reserved [0x15] */
+
+#define VMCSR   _SFR_IO8(0x16)
+#define VMEN    0
+#define VMLS0   1
+#define VMLS1   2
+#define VMLS2   3
+#define VMIM    4
+#define VMF     5
+#define BODPD   6
+#define BODLS   7
+
+#define PCIFR   _SFR_IO8(0x17)
+#define PCIF0   0
+#define PCIF1   1
+#define PCIF2   2
+
+#define LFFR    _SFR_IO8(0x18)
+#define LFWPF   0
+#define LFBF    1
+#define LFEDF   2
+#define LFRF    3
+
+#define SSFR    _SFR_IO8(0x19)
+#define MSENF   0
+#define MSENO   1
+
+#define T10IFR  _SFR_IO8(0x1A)
+#define T0F     0
+#define T1F     1
+
+#define T2IFR   _SFR_IO8(0x1B)
+#define T2OFF   0
+#define T2COF   1
+#define T2ICF   2
+#define T2RXF   3
+#define T2TXF   4
+#define T2TCF   5
+
+#define T3IFR   _SFR_IO8(0x1C)
+#define T3OFF   0
+#define T3COAF  1
+#define T3COBF  2
+#define T3ICF   3
+
+#define EIFR    _SFR_IO8(0x1D)
+#define INTF0   0
+#define INTF1   1
+
+#define GPIOR0  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEWE    1
+#define EEMWE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define PCICR   _SFR_IO8(0x23)
+#define PCIE0   0
+#define PCIE1   1
+#define PCIE2   2
+
+#define EIMSK   _SFR_IO8(0x24)
+#define INT0    0
+#define INT1    1
+
+/* Reserved [0x25..0x26] */
+
+#define SVCR    _SFR_IO8(0x27)
+
+#define SCR     _SFR_IO8(0x28)
+#define SMS     0
+#define SEN0    1
+#define SEN1    2
+#define SMEN    3
+
+#define SCCR    _SFR_IO8(0x29)
+#define SRCC0   0
+#define SRCC1   1
+#define SCCS0   2
+#define SCCS1   3
+#define SCCS2   4
+
+#define GPIOR1  _SFR_IO8(0x2A)
+
+#define GPIOR2  _SFR_IO8(0x2B)
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+#define T2MDR   _SFR_IO8(0x2F)
+
+#define LFRR    _SFR_IO8(0x30)
+
+/* Reserved [0x31] */
+
+#define LFCDR   _SFR_IO8(0x32)
+#define LFDO    0
+#define LFRST   6
+#define LFSCE   7
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define MCUSR   _SFR_IO8(0x34)
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+#define TSRF    5
+
+#define MCUCR   _SFR_IO8(0x35)
+#define IVCE    0
+#define IVSEL   1
+#define PUD     4
+
+#define LFRB    _SFR_IO8(0x36)
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SELFPRGEN 0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define RWWSRE  4
+#define RWWSB   6
+#define SPMIE   7
+
+#define T1CR    _SFR_IO8(0x38)
+#define T1PS0   0
+#define T1PS1   1
+#define T1PS2   2
+#define T1CS0   3
+#define T1CS1   4
+#define T1CS2   5
+#define T1IE    7
+
+#define T0CR    _SFR_IO8(0x39)
+#define T0PAS0  0
+#define T0PAS1  1
+#define T0PAS2  2
+#define T0IE    3
+#define T0PR    4
+#define T0PBS0  5
+#define T0PBS1  6
+#define T0PBS2  7
+
+/* Reserved [0x3A] */
+
+#define CMIMR   _SFR_IO8(0x3B)
+#define ECIE    0
+
+#define CLKPR   _SFR_IO8(0x3C)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLTPS0  3
+#define CLTPS1  4
+#define CLTPS2  5
+#define CLPCE   7
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define WDTCR   _SFR_MEM8(0x60)
+#define WDPS0   0
+#define WDPS1   1
+#define WDPS2   2
+#define WDE     3
+#define WDCE    4
+
+#define SIMSK   _SFR_MEM8(0x61)
+#define MSIE    0
+
+/* Reserved [0x62..0x63] */
+
+#define TSCR    _SFR_MEM8(0x64)
+#define TSSD    0
+
+#define SRCCAL  _SFR_MEM8(0x65)
+
+#define FRCCAL  _SFR_MEM8(0x66)
+
+#define MSVCAL  _SFR_MEM8(0x67)
+
+/* Reserved [0x68] */
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+
+#define PCMSK0  _SFR_MEM8(0x6A)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6B)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+
+#define PCMSK2  _SFR_MEM8(0x6C)
+#define PCINT16 0
+#define PCINT17 1
+#define PCINT18 2
+#define PCINT19 3
+#define PCINT20 4
+#define PCINT21 5
+#define PCINT22 6
+#define PCINT23 7
+
+/* Reserved [0x6D] */
+
+#define T2ICRL  _SFR_MEM8(0x6E)
+
+#define T2ICR   _SFR_MEM8(0x6F)
+
+/* Combine T2CORL and T2CORH */
+#define T2COR   _SFR_MEM16(0x70)
+
+#define T2CORL  _SFR_MEM8(0x70)
+#define T2CORH  _SFR_MEM8(0x71)
+
+#define T2MRA   _SFR_MEM8(0x72)
+#define T2CS0   0
+#define T2CS1   1
+#define T2CS2   2
+#define T2CE0   3
+#define T2CE1   4
+#define T2CNC   5
+#define T2TP0   6
+#define T2TP1   7
+
+#define T2MRB   _SFR_MEM8(0x73)
+#define T2M0    0
+#define T2M1    1
+#define T2M2    2
+#define T2M3    3
+#define T2TOP   4
+#define T2CPOL  6
+#define T2SSIE  7
+
+#define T2IMR   _SFR_MEM8(0x74)
+#define T2OIM   0
+#define T2CIM   1
+#define T2CPIM  2
+#define T2RXIM  3
+#define T2TXIM  4
+#define T2TCIM  5
+
+/* Reserved [0x75] */
+
+/* Combine T3ICRL and T3ICRH */
+#define T3ICR   _SFR_MEM16(0x76)
+
+#define T3ICRL  _SFR_MEM8(0x76)
+#define T3ICRH  _SFR_MEM8(0x77)
+
+/* Combine T3CORAL and T3CORAH */
+#define T3CORA  _SFR_MEM16(0x78)
+
+#define T3CORAL _SFR_MEM8(0x78)
+#define T3CORAH _SFR_MEM8(0x79)
+
+/* Combine T3CORBL and T3CORBH */
+#define T3CORB  _SFR_MEM16(0x7A)
+
+#define T3CORBL _SFR_MEM8(0x7A)
+#define T3CORBH _SFR_MEM8(0x7B)
+
+#define T3MRA   _SFR_MEM8(0x7C)
+#define T3CS0   0
+#define T3CS1   1
+#define T3CS2   2
+#define T3CE0   3
+#define T3CE1   4
+#define T3CNC   5
+#define T3ICS0  6
+#define T3ICS1  7
+
+#define T3MRB   _SFR_MEM8(0x7D)
+#define T3M0    0
+#define T3M1    1
+#define T3M2    2
+#define T3TOP   4
+
+#define T3CRB   _SFR_MEM8(0x7E)
+#define T3CTMA  0
+#define T3SAMA  1
+#define T3CRMA  2
+#define T3CTMB  3
+#define T3SAMB  4
+#define T3CRMB  5
+#define T3CPRM  6
+
+#define T3IMR   _SFR_MEM8(0x7F)
+#define T3OIM   0
+#define T3CAIM  1
+#define T3CBIM  2
+#define T3CPIM  3
+
+/* Reserved [0x80] */
+
+#define LFIMR   _SFR_MEM8(0x81)
+#define LFWIM   0
+#define LFBIM   1
+#define LFEIM   2
+
+#define LFRCR   _SFR_MEM8(0x82)
+#define LFEN    0
+#define LFBM    1
+#define LFWM0   2
+#define LFWM1   3
+#define LFRSS   4
+#define LFCS0   5
+#define LFCS1   6
+#define LFCS2   7
+
+#define LFHCR   _SFR_MEM8(0x83)
+
+/* Combine LFIDCL and LFIDCH */
+#define LFIDC   _SFR_MEM16(0x84)
+
+#define LFIDCL  _SFR_MEM8(0x84)
+#define LFIDCH  _SFR_MEM8(0x85)
+
+/* Combine LFCALL and LFCALH */
+#define LFCAL   _SFR_MEM16(0x86)
+
+#define LFCALL  _SFR_MEM8(0x86)
+#define LFCALH  _SFR_MEM8(0x87)
+
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
+
+/* External Interrupt Request 1 */
+#define INT1_vect            _VECTOR(2)
+#define INT1_vect_num        2
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect            _VECTOR(3)
+#define PCINT0_vect_num        3
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect            _VECTOR(4)
+#define PCINT1_vect_num        4
+
+/* Pin Change Interrupt Request 2 */
+#define PCINT2_vect            _VECTOR(5)
+#define PCINT2_vect_num        5
+
+/* Voltage Monitor Interrupt */
+#define INTVM_vect            _VECTOR(6)
+#define INTVM_vect_num        6
+
+/* Sensor Interface Interrupt */
+#define SENINT_vect            _VECTOR(7)
+#define SENINT_vect_num        7
+
+/* Timer0 Interval Interrupt */
+#define INTT0_vect            _VECTOR(8)
+#define INTT0_vect_num        8
+
+/* LF-Receiver Wake-up Interrupt */
+#define LFWP_vect            _VECTOR(9)
+#define LFWP_vect_num        9
+
+/* Timer/Counter3 Capture Event */
+#define T3CAP_vect            _VECTOR(10)
+#define T3CAP_vect_num        10
+
+/* Timer/Counter3 Compare Match A */
+#define T3COMA_vect            _VECTOR(11)
+#define T3COMA_vect_num        11
+
+/* Timer/Counter3 Compare Match B */
+#define T3COMB_vect            _VECTOR(12)
+#define T3COMB_vect_num        12
+
+/* Timer/Counter3 Overflow */
+#define T3OVF_vect            _VECTOR(13)
+#define T3OVF_vect_num        13
+
+/* Timer/Counter2 Capture Event */
+#define T2CAP_vect            _VECTOR(14)
+#define T2CAP_vect_num        14
+
+/* Timer/Counter2 Compare Match */
+#define T2COM_vect            _VECTOR(15)
+#define T2COM_vect_num        15
+
+/* Timer/Counter2 Overflow */
+#define T2OVF_vect            _VECTOR(16)
+#define T2OVF_vect_num        16
+
+/* SPI Serial Transfer Complete */
+#define SPISTC_vect            _VECTOR(17)
+#define SPISTC_vect_num        17
+
+/* LF Receive Buffer Interrupt */
+#define LFRXB_vect            _VECTOR(18)
+#define LFRXB_vect_num        18
+
+/* Timer1 Interval Interrupt */
+#define INTT1_vect            _VECTOR(19)
+#define INTT1_vect_num        19
+
+/* Timer2 SSI Receive Buffer Interrupt */
+#define T2RXB_vect            _VECTOR(20)
+#define T2RXB_vect_num        20
+
+/* Timer2 SSI Transmit Buffer Interrupt */
+#define T2TXB_vect            _VECTOR(21)
+#define T2TXB_vect_num        21
+
+/* Timer2 SSI Transmit Complete Interrupt */
+#define T2TXC_vect            _VECTOR(22)
+#define T2TXC_vect_num        22
+
+/* LF-Receiver End of Burst Interrupt */
+#define LFREOB_vect            _VECTOR(23)
+#define LFREOB_vect_num        23
+
+/* External Input Clock break down Interrupt */
+#define EXCM_vect            _VECTOR(24)
+#define EXCM_vect_num        24
+
+/* EEPROM Ready Interrupt */
+#define EEREADY_vect            _VECTOR(25)
+#define EEREADY_vect_num        25
+
+/* Store Program Memory Ready */
+#define SPM_RDY_vect            _VECTOR(26)
+#define SPM_RDY_vect_num        26
+
+#define _VECTORS_SIZE 54
+
+
+/* Constants */
+
+#define SPM_PAGESIZE 64
+#define FLASHSTART   0x0000
+#define FLASHEND     0x1FFF
+#define RAMSTART     0x0100
+#define RAMSIZE      512
+#define RAMEND       0x02FF
+#define E2START     0
+#define E2SIZE      320
+#define E2PAGESIZE  4
+#define E2END       0x013F
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 2
+
+/* Low Fuse Byte */
+#define FUSE_TSRDI       (unsigned char)~_BV(0)
+#define FUSE_BODEN       (unsigned char)~_BV(1)
+#define FUSE_FRCFS       (unsigned char)~_BV(2)
+#define FUSE_WDRCON      (unsigned char)~_BV(3)
+#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(4)
+#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST     (unsigned char)~_BV(0)
+#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
+#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_DWEN        (unsigned char)~_BV(6)
+#define FUSE_EELOCK      (unsigned char)~_BV(7)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x93
+#define SIGNATURE_2 0x82
+
+
+#endif /* #ifdef _AVR_ATA6285_H_INCLUDED */
+
diff -urN avr-libc-1.8.0.orig/include/avr/ioa6286.h avr-libc-1.8.0/include/avr/ioa6286.h
--- avr-libc-1.8.0.orig/include/avr/ioa6286.h	1970-01-01 01:00:00.000000000 +0100
+++ avr-libc-1.8.0/include/avr/ioa6286.h	2013-06-12 12:21:34.000000000 +0200
@@ -0,0 +1,706 @@
+/*****************************************************************************
+ *
+ * Copyright (C) 2013 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****************************************************************************/
+
+
+#ifndef _AVR_ATA6286_H_INCLUDED
+#define _AVR_ATA6286_H_INCLUDED
+
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "ioa6286.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+/* Registers and associated bit numbers */
+
+#define PINB    _SFR_IO8(0x03)
+#define PINB7   7
+#define PINB6   6
+#define PINB5   5
+#define PINB4   4
+#define PINB3   3
+#define PINB2   2
+#define PINB1   1
+#define PINB0   0
+
+#define DDRB    _SFR_IO8(0x04)
+#define DDRB7   7
+#define DDRB6   6
+#define DDRB5   5
+#define DDRB4   4
+#define DDRB3   3
+#define DDRB2   2
+#define DDRB1   1
+#define DDRB0   0
+
+#define PORTB   _SFR_IO8(0x05)
+#define PORTB7  7
+#define PORTB6  6
+#define PORTB5  5
+#define PORTB4  4
+#define PORTB3  3
+#define PORTB2  2
+#define PORTB1  1
+#define PORTB0  0
+
+#define PINC    _SFR_IO8(0x06)
+#define PINC7   7
+#define PINC6   6
+#define PINC5   5
+#define PINC4   4
+#define PINC3   3
+#define PINC2   2
+#define PINC1   1
+#define PINC0   0
+
+#define DDRC    _SFR_IO8(0x07)
+#define DDRC7   7
+#define DDRC6   6
+#define DDRC5   5
+#define DDRC4   4
+#define DDRC3   3
+#define DDRC2   2
+#define DDRC1   1
+#define DDRC0   0
+
+#define PORTC   _SFR_IO8(0x08)
+#define PORTC7  7
+#define PORTC6  6
+#define PORTC5  5
+#define PORTC4  4
+#define PORTC3  3
+#define PORTC2  2
+#define PORTC1  1
+#define PORTC0  0
+
+#define PIND    _SFR_IO8(0x09)
+#define PIND7   7
+#define PIND6   6
+#define PIND5   5
+#define PIND4   4
+#define PIND3   3
+#define PIND2   2
+#define PIND1   1
+#define PIND0   0
+
+#define DDRD    _SFR_IO8(0x0A)
+#define DDRD7   7
+#define DDRD6   6
+#define DDRD5   5
+#define DDRD4   4
+#define DDRD3   3
+#define DDRD2   2
+#define DDRD1   1
+#define DDRD0   0
+
+#define PORTD   _SFR_IO8(0x0B)
+#define PORTD7  7
+#define PORTD6  6
+#define PORTD5  5
+#define PORTD4  4
+#define PORTD3  3
+#define PORTD2  2
+#define PORTD1  1
+#define PORTD0  0
+
+/* Reserved [0x0C..0x0E] */
+
+#define CMCR    _SFR_IO8(0x0F)
+#define CMM0    0
+#define CMM1    1
+#define SRCD    2
+#define CMONEN  3
+#define CCS     4
+#define ECINS   5
+#define CMCCE   7
+
+#define CMSR    _SFR_IO8(0x10)
+#define ECF     0
+
+#define T2CRA   _SFR_IO8(0x11)
+#define T2OTM   0
+#define T2CTM   1
+#define T2CR    2
+#define T2CRM   3
+#define T2ICS   5
+#define T2TS    6
+#define T2E     7
+
+#define T2CRB   _SFR_IO8(0x12)
+#define T2SCE   0
+
+/* Reserved [0x13] */
+
+#define T3CRA   _SFR_IO8(0x14)
+#define T3AC    0
+#define T3SCE   1
+#define T3CR    2
+#define T3TS    6
+#define T3E     7
+
+/* Reserved [0x15] */
+
+#define VMCSR   _SFR_IO8(0x16)
+#define VMEN    0
+#define VMLS0   1
+#define VMLS1   2
+#define VMLS2   3
+#define VMIM    4
+#define VMF     5
+#define BODPD   6
+#define BODLS   7
+
+#define PCIFR   _SFR_IO8(0x17)
+#define PCIF0   0
+#define PCIF1   1
+#define PCIF2   2
+
+#define LFFR    _SFR_IO8(0x18)
+#define LFWPF   0
+#define LFBF    1
+#define LFEDF   2
+#define LFRF    3
+
+#define SSFR    _SFR_IO8(0x19)
+#define MSENF   0
+#define MSENO   1
+
+#define T10IFR  _SFR_IO8(0x1A)
+#define T0F     0
+#define T1F     1
+
+#define T2IFR   _SFR_IO8(0x1B)
+#define T2OFF   0
+#define T2COF   1
+#define T2ICF   2
+#define T2RXF   3
+#define T2TXF   4
+#define T2TCF   5
+
+#define T3IFR   _SFR_IO8(0x1C)
+#define T3OFF   0
+#define T3COAF  1
+#define T3COBF  2
+#define T3ICF   3
+
+#define EIFR    _SFR_IO8(0x1D)
+#define INTF0   0
+#define INTF1   1
+
+#define GPIOR0  _SFR_IO8(0x1E)
+
+#define EECR    _SFR_IO8(0x1F)
+#define EERE    0
+#define EEWE    1
+#define EEMWE   2
+#define EERIE   3
+#define EEPM0   4
+#define EEPM1   5
+
+#define EEDR    _SFR_IO8(0x20)
+
+/* Combine EEARL and EEARH */
+#define EEAR    _SFR_IO16(0x21)
+
+#define EEARL   _SFR_IO8(0x21)
+#define EEARH   _SFR_IO8(0x22)
+
+#define PCICR   _SFR_IO8(0x23)
+#define PCIE0   0
+#define PCIE1   1
+#define PCIE2   2
+
+#define EIMSK   _SFR_IO8(0x24)
+#define INT0    0
+#define INT1    1
+
+/* Reserved [0x25..0x26] */
+
+#define SVCR    _SFR_IO8(0x27)
+
+#define SCR     _SFR_IO8(0x28)
+#define SMS     0
+#define SEN0    1
+#define SEN1    2
+#define SMEN    3
+
+#define SCCR    _SFR_IO8(0x29)
+#define SRCC0   0
+#define SRCC1   1
+#define SCCS0   2
+#define SCCS1   3
+#define SCCS2   4
+
+#define GPIOR1  _SFR_IO8(0x2A)
+
+#define GPIOR2  _SFR_IO8(0x2B)
+
+#define SPCR    _SFR_IO8(0x2C)
+#define SPR0    0
+#define SPR1    1
+#define CPHA    2
+#define CPOL    3
+#define MSTR    4
+#define DORD    5
+#define SPE     6
+#define SPIE    7
+
+#define SPSR    _SFR_IO8(0x2D)
+#define SPI2X   0
+#define WCOL    6
+#define SPIF    7
+
+#define SPDR    _SFR_IO8(0x2E)
+
+#define T2MDR   _SFR_IO8(0x2F)
+
+#define LFRR    _SFR_IO8(0x30)
+
+/* Reserved [0x31] */
+
+#define LFCDR   _SFR_IO8(0x32)
+#define LFDO    0
+#define LFRST   6
+#define LFSCE   7
+
+#define SMCR    _SFR_IO8(0x33)
+#define SE      0
+#define SM0     1
+#define SM1     2
+#define SM2     3
+
+#define MCUSR   _SFR_IO8(0x34)
+#define PORF    0
+#define EXTRF   1
+#define BORF    2
+#define WDRF    3
+#define TSRF    5
+
+#define MCUCR   _SFR_IO8(0x35)
+#define IVCE    0
+#define IVSEL   1
+#define PUD     4
+
+#define LFRB    _SFR_IO8(0x36)
+
+#define SPMCSR  _SFR_IO8(0x37)
+#define SELFPRGEN 0
+#define PGERS   1
+#define PGWRT   2
+#define BLBSET  3
+#define RWWSRE  4
+#define RWWSB   6
+#define SPMIE   7
+
+#define T1CR    _SFR_IO8(0x38)
+#define T1PS0   0
+#define T1PS1   1
+#define T1PS2   2
+#define T1CS0   3
+#define T1CS1   4
+#define T1CS2   5
+#define T1IE    7
+
+#define T0CR    _SFR_IO8(0x39)
+#define T0PAS0  0
+#define T0PAS1  1
+#define T0PAS2  2
+#define T0IE    3
+#define T0PR    4
+#define T0PBS0  5
+#define T0PBS1  6
+#define T0PBS2  7
+
+/* Reserved [0x3A] */
+
+#define CMIMR   _SFR_IO8(0x3B)
+#define ECIE    0
+
+#define CLKPR   _SFR_IO8(0x3C)
+#define CLKPS0  0
+#define CLKPS1  1
+#define CLKPS2  2
+#define CLTPS0  3
+#define CLTPS1  4
+#define CLTPS2  5
+#define CLPCE   7
+
+/* SP [0x3D..0x3E] */
+
+/* SREG [0x3F] */
+
+#define WDTCR   _SFR_MEM8(0x60)
+#define WDPS0   0
+#define WDPS1   1
+#define WDPS2   2
+#define WDE     3
+#define WDCE    4
+
+#define SIMSK   _SFR_MEM8(0x61)
+#define MSIE    0
+
+/* Reserved [0x62..0x63] */
+
+#define TSCR    _SFR_MEM8(0x64)
+#define TSSD    0
+
+#define SRCCAL  _SFR_MEM8(0x65)
+
+#define FRCCAL  _SFR_MEM8(0x66)
+
+#define MSVCAL  _SFR_MEM8(0x67)
+
+/* Reserved [0x68] */
+
+#define EICRA   _SFR_MEM8(0x69)
+#define ISC00   0
+#define ISC01   1
+#define ISC10   2
+#define ISC11   3
+
+#define PCMSK0  _SFR_MEM8(0x6A)
+#define PCINT0  0
+#define PCINT1  1
+#define PCINT2  2
+#define PCINT3  3
+#define PCINT4  4
+#define PCINT5  5
+#define PCINT6  6
+#define PCINT7  7
+
+#define PCMSK1  _SFR_MEM8(0x6B)
+#define PCINT8  0
+#define PCINT9  1
+#define PCINT10 2
+
+#define PCMSK2  _SFR_MEM8(0x6C)
+#define PCINT16 0
+#define PCINT17 1
+#define PCINT18 2
+#define PCINT19 3
+#define PCINT20 4
+#define PCINT21 5
+#define PCINT22 6
+#define PCINT23 7
+
+/* Reserved [0x6D] */
+
+#define T2ICRL  _SFR_MEM8(0x6E)
+
+#define T2ICR   _SFR_MEM8(0x6F)
+
+/* Combine T2CORL and T2CORH */
+#define T2COR   _SFR_MEM16(0x70)
+
+#define T2CORL  _SFR_MEM8(0x70)
+#define T2CORH  _SFR_MEM8(0x71)
+
+#define T2MRA   _SFR_MEM8(0x72)
+#define T2CS0   0
+#define T2CS1   1
+#define T2CS2   2
+#define T2CE0   3
+#define T2CE1   4
+#define T2CNC   5
+#define T2TP0   6
+#define T2TP1   7
+
+#define T2MRB   _SFR_MEM8(0x73)
+#define T2M0    0
+#define T2M1    1
+#define T2M2    2
+#define T2M3    3
+#define T2TOP   4
+#define T2CPOL  6
+#define T2SSIE  7
+
+#define T2IMR   _SFR_MEM8(0x74)
+#define T2OIM   0
+#define T2CIM   1
+#define T2CPIM  2
+#define T2RXIM  3
+#define T2TXIM  4
+#define T2TCIM  5
+
+/* Reserved [0x75] */
+
+/* Combine T3ICRL and T3ICRH */
+#define T3ICR   _SFR_MEM16(0x76)
+
+#define T3ICRL  _SFR_MEM8(0x76)
+#define T3ICRH  _SFR_MEM8(0x77)
+
+/* Combine T3CORAL and T3CORAH */
+#define T3CORA  _SFR_MEM16(0x78)
+
+#define T3CORAL _SFR_MEM8(0x78)
+#define T3CORAH _SFR_MEM8(0x79)
+
+/* Combine T3CORBL and T3CORBH */
+#define T3CORB  _SFR_MEM16(0x7A)
+
+#define T3CORBL _SFR_MEM8(0x7A)
+#define T3CORBH _SFR_MEM8(0x7B)
+
+#define T3MRA   _SFR_MEM8(0x7C)
+#define T3CS0   0
+#define T3CS1   1
+#define T3CS2   2
+#define T3CE0   3
+#define T3CE1   4
+#define T3CNC   5
+#define T3ICS0  6
+#define T3ICS1  7
+
+#define T3MRB   _SFR_MEM8(0x7D)
+#define T3M0    0
+#define T3M1    1
+#define T3M2    2
+#define T3TOP   4
+
+#define T3CRB   _SFR_MEM8(0x7E)
+#define T3CTMA  0
+#define T3SAMA  1
+#define T3CRMA  2
+#define T3CTMB  3
+#define T3SAMB  4
+#define T3CRMB  5
+#define T3CPRM  6
+
+#define T3IMR   _SFR_MEM8(0x7F)
+#define T3OIM   0
+#define T3CAIM  1
+#define T3CBIM  2
+#define T3CPIM  3
+
+/* Reserved [0x80] */
+
+#define LFIMR   _SFR_MEM8(0x81)
+#define LFWIM   0
+#define LFBIM   1
+#define LFEIM   2
+
+#define LFRCR   _SFR_MEM8(0x82)
+#define LFEN    0
+#define LFBM    1
+#define LFWM0   2
+#define LFWM1   3
+#define LFRSS   4
+#define LFCS0   5
+#define LFCS1   6
+#define LFCS2   7
+
+#define LFHCR   _SFR_MEM8(0x83)
+
+/* Combine LFIDCL and LFIDCH */
+#define LFIDC   _SFR_MEM16(0x84)
+
+#define LFIDCL  _SFR_MEM8(0x84)
+#define LFIDCH  _SFR_MEM8(0x85)
+
+/* Combine LFCALL and LFCALH */
+#define LFCAL   _SFR_MEM16(0x86)
+
+#define LFCALL  _SFR_MEM8(0x86)
+#define LFCALH  _SFR_MEM8(0x87)
+
+
+
+/* Interrupt vectors */
+/* Vector 0 is the reset vector */
+/* External Interrupt Request 0 */
+#define INT0_vect            _VECTOR(1)
+#define INT0_vect_num        1
+
+/* External Interrupt Request 1 */
+#define INT1_vect            _VECTOR(2)
+#define INT1_vect_num        2
+
+/* Pin Change Interrupt Request 0 */
+#define PCINT0_vect            _VECTOR(3)
+#define PCINT0_vect_num        3
+
+/* Pin Change Interrupt Request 1 */
+#define PCINT1_vect            _VECTOR(4)
+#define PCINT1_vect_num        4
+
+/* Pin Change Interrupt Request 2 */
+#define PCINT2_vect            _VECTOR(5)
+#define PCINT2_vect_num        5
+
+/* Voltage Monitor Interrupt */
+#define INTVM_vect            _VECTOR(6)
+#define INTVM_vect_num        6
+
+/* Sensor Interface Interrupt */
+#define SENINT_vect            _VECTOR(7)
+#define SENINT_vect_num        7
+
+/* Timer0 Interval Interrupt */
+#define INTT0_vect            _VECTOR(8)
+#define INTT0_vect_num        8
+
+/* LF-Receiver Wake-up Interrupt */
+#define LFWP_vect            _VECTOR(9)
+#define LFWP_vect_num        9
+
+/* Timer/Counter3 Capture Event */
+#define T3CAP_vect            _VECTOR(10)
+#define T3CAP_vect_num        10
+
+/* Timer/Counter3 Compare Match A */
+#define T3COMA_vect            _VECTOR(11)
+#define T3COMA_vect_num        11
+
+/* Timer/Counter3 Compare Match B */
+#define T3COMB_vect            _VECTOR(12)
+#define T3COMB_vect_num        12
+
+/* Timer/Counter3 Overflow */
+#define T3OVF_vect            _VECTOR(13)
+#define T3OVF_vect_num        13
+
+/* Timer/Counter2 Capture Event */
+#define T2CAP_vect            _VECTOR(14)
+#define T2CAP_vect_num        14
+
+/* Timer/Counter2 Compare Match */
+#define T2COM_vect            _VECTOR(15)
+#define T2COM_vect_num        15
+
+/* Timer/Counter2 Overflow */
+#define T2OVF_vect            _VECTOR(16)
+#define T2OVF_vect_num        16
+
+/* SPI Serial Transfer Complete */
+#define SPISTC_vect            _VECTOR(17)
+#define SPISTC_vect_num        17
+
+/* LF Receive Buffer Interrupt */
+#define LFRXB_vect            _VECTOR(18)
+#define LFRXB_vect_num        18
+
+/* Timer1 Interval Interrupt */
+#define INTT1_vect            _VECTOR(19)
+#define INTT1_vect_num        19
+
+/* Timer2 SSI Receive Buffer Interrupt */
+#define T2RXB_vect            _VECTOR(20)
+#define T2RXB_vect_num        20
+
+/* Timer2 SSI Transmit Buffer Interrupt */
+#define T2TXB_vect            _VECTOR(21)
+#define T2TXB_vect_num        21
+
+/* Timer2 SSI Transmit Complete Interrupt */
+#define T2TXC_vect            _VECTOR(22)
+#define T2TXC_vect_num        22
+
+/* LF-Receiver End of Burst Interrupt */
+#define LFREOB_vect            _VECTOR(23)
+#define LFREOB_vect_num        23
+
+/* External Input Clock break down Interrupt */
+#define EXCM_vect            _VECTOR(24)
+#define EXCM_vect_num        24
+
+/* EEPROM Ready Interrupt */
+#define EEREADY_vect            _VECTOR(25)
+#define EEREADY_vect_num        25
+
+/* Store Program Memory Ready */
+#define SPM_RDY_vect            _VECTOR(26)
+#define SPM_RDY_vect_num        26
+
+#define _VECTORS_SIZE 54
+
+
+/* Constants */
+
+#define SPM_PAGESIZE 64
+#define FLASHSTART   0x0000
+#define FLASHEND     0x1FFF
+#define RAMSTART     0x0100
+#define RAMSIZE      512
+#define RAMEND       0x02FF
+#define E2START     0
+#define E2SIZE      320
+#define E2PAGESIZE  4
+#define E2END       0x013F
+#define XRAMEND      RAMEND
+
+
+/* Fuses */
+
+#define FUSE_MEMORY_SIZE 2
+
+/* Low Fuse Byte */
+#define FUSE_TSRDI       (unsigned char)~_BV(0)
+#define FUSE_BODEN       (unsigned char)~_BV(1)
+#define FUSE_FRCFS       (unsigned char)~_BV(2)
+#define FUSE_WDRCON      (unsigned char)~_BV(3)
+#define FUSE_SUT_CKSEL0  (unsigned char)~_BV(4)
+#define FUSE_SUT_CKSEL1  (unsigned char)~_BV(5)
+#define FUSE_CKOUT       (unsigned char)~_BV(6)
+#define FUSE_CKDIV8      (unsigned char)~_BV(7)
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST     (unsigned char)~_BV(0)
+#define FUSE_BOOTSZ0     (unsigned char)~_BV(1)
+#define FUSE_BOOTSZ1     (unsigned char)~_BV(2)
+#define FUSE_EESAVE      (unsigned char)~_BV(3)
+#define FUSE_WDTON       (unsigned char)~_BV(4)
+#define FUSE_SPIEN       (unsigned char)~_BV(5)
+#define FUSE_DWEN        (unsigned char)~_BV(6)
+#define FUSE_EELOCK      (unsigned char)~_BV(7)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x93
+#define SIGNATURE_2 0x82
+
+
+#endif /* #ifdef _AVR_ATA6286_H_INCLUDED */
+
diff -urN avr-libc-1.8.0.orig/include/avr/io.h avr-libc-1.8.0/include/avr/io.h
--- avr-libc-1.8.0.orig/include/avr/io.h	2013-06-12 12:22:36.138837799 +0200
+++ avr-libc-1.8.0/include/avr/io.h	2013-06-12 12:21:34.000000000 +0200
@@ -1,5 +1,4 @@
-/* Copyright (c) 2002,2003,2005,2006,2007 Marek Michalkiewicz, Joerg Wunsch
-   Copyright (c) 2007 Eric B. Weddington
+/* Copyright (c) 20012 Atmel Corporation
    All rights reserved.
 
    Redistribution and use in source and binary forms, with or without
@@ -29,7 +28,6 @@
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE. */
 
-/* $Id: io.h 2211 2011-02-14 14:04:25Z aboyapati $ */
 
 /** \file */
 /** \defgroup avr_io <avr/io.h>: AVR device-specific IO definitions
@@ -98,485 +96,450 @@
 
 #include <avr/sfr_defs.h>
 
-#if defined (__AVR_AT94K__)
-#  include <avr/ioat94k.h>
-#elif defined (__AVR_AT43USB320__)
-#  include <avr/io43u32x.h>
-#elif defined (__AVR_AT43USB355__)
-#  include <avr/io43u35x.h>
-#elif defined (__AVR_AT76C711__)
-#  include <avr/io76c711.h>
-#elif defined (__AVR_AT86RF401__)
-#  include <avr/io86r401.h>
-#elif defined (__AVR_AT90PWM1__)
-#  include <avr/io90pwm1.h>
-#elif defined (__AVR_AT90PWM2__)
-#  include <avr/io90pwmx.h>
-#elif defined (__AVR_AT90PWM2B__)
-#  include <avr/io90pwm2b.h>
-#elif defined (__AVR_AT90PWM3__)
-#  include <avr/io90pwmx.h>
-#elif defined (__AVR_AT90PWM3B__)
-#  include <avr/io90pwm3b.h>
-#elif defined (__AVR_AT90PWM216__)
-#  include <avr/io90pwm216.h>
-#elif defined (__AVR_AT90PWM316__)
-#  include <avr/io90pwm316.h>
-#elif defined (__AVR_AT90PWM161__)
-#  include <avr/io90pwm161.h>
-#elif defined (__AVR_AT90PWM81__)
-#  include <avr/io90pwm81.h>
-#elif defined (__AVR_ATmega8U2__)
-#  include <avr/iom8u2.h>
-#elif defined (__AVR_ATmega16M1__)
-#  include <avr/iom16m1.h>
-#elif defined (__AVR_ATmega16U2__)
-#  include <avr/iom16u2.h>
-#elif defined (__AVR_ATmega16U4__)
-#  include <avr/iom16u4.h>
-#elif defined (__AVR_ATmega32C1__)
-#  include <avr/iom32c1.h>
-#elif defined (__AVR_ATmega32M1__)
-#  include <avr/iom32m1.h>
-#elif defined (__AVR_ATmega32U2__)
-#  include <avr/iom32u2.h>
-#elif defined (__AVR_ATmega32U4__)
-#  include <avr/iom32u4.h>
-#elif defined (__AVR_ATmega32U6__)
-#  include <avr/iom32u6.h>
-#elif defined (__AVR_ATmega64C1__)
-#  include <avr/iom64c1.h>
-#elif defined (__AVR_ATmega64M1__)
-#  include <avr/iom64m1.h>
-#elif defined (__AVR_ATmega128__)
-#  include <avr/iom128.h>
-#elif defined (__AVR_ATmega128A__)
-#  include <avr/iom128a.h>
-#elif defined (__AVR_ATmega1280__)
-#  include <avr/iom1280.h>
-#elif defined (__AVR_ATmega1281__)
-#  include <avr/iom1281.h>
-#elif defined (__AVR_ATmega1284__)
-#  include <avr/iom1284.h>
-#elif defined (__AVR_ATmega1284P__)
-#  include <avr/iom1284p.h>
-#elif defined (__AVR_ATmega128RFA1__)
-#  include <avr/iom128rfa1.h>
-#elif defined (__AVR_ATmega128RFR2__)
-#  include <avr/iom128rfr2.h>
-#elif defined (__AVR_ATmega1284RFR2__)
-#  include <avr/iom1284rfr2.h>
-#elif defined (__AVR_ATmega256RFR2__)
-#  include <avr/iom256rfr2.h>
-#elif defined (__AVR_ATmega2564RFR2__)
-#  include <avr/iom2564rfr2.h>
-#elif defined (__AVR_ATmega2560__)
-#  include <avr/iom2560.h>
-#elif defined (__AVR_ATmega2561__)
-#  include <avr/iom2561.h>
-#elif defined (__AVR_AT90CAN32__)
-#  include <avr/iocan32.h>
-#elif defined (__AVR_AT90CAN64__)
-#  include <avr/iocan64.h>
-#elif defined (__AVR_AT90CAN128__)
-#  include <avr/iocan128.h>
-#elif defined (__AVR_AT90USB82__)
-#  include <avr/iousb82.h>
-#elif defined (__AVR_AT90USB162__)
-#  include <avr/iousb162.h>
-#elif defined (__AVR_AT90USB646__)
-#  include <avr/iousb646.h>
-#elif defined (__AVR_AT90USB647__)
-#  include <avr/iousb647.h>
-#elif defined (__AVR_AT90USB1286__)
-#  include <avr/iousb1286.h>
-#elif defined (__AVR_AT90USB1287__)
-#  include <avr/iousb1287.h>
-#elif defined (__AVR_ATmega64RFR2__)
-#  include <avr/iom64rfr2.h>
-#elif defined (__AVR_ATmega644RFR2__)
-#  include <avr/iom644rfr2.h>
-#elif defined (__AVR_ATmega64__)
-#  include <avr/iom64.h>
-#elif defined (__AVR_ATmega64A__)
-#  include <avr/iom64a.h>
-#elif defined (__AVR_ATmega640__)
-#  include <avr/iom640.h>
-#elif defined (__AVR_ATmega644__) 
-#  include <avr/iom644.h>
-#elif (defined __AVR_ATmega644A__)
-#include <avr/iom644a.h>
-#elif defined (__AVR_ATmega644P__)
-#  include <avr/iom644p.h>
-#elif defined (__AVR_ATmega644PA__)
-#  include <avr/iom644pa.h>
-#elif defined (__AVR_ATmega645__)
-#  include <avr/iom645.h>
-#elif (defined __AVR_ATmega645A__)
-#include <avr/iom645a.h>
-#elif (defined __AVR_ATmega645P__)
-#include <avr/iom645p.h>
-#elif defined (__AVR_ATmega6450__)
-#  include <avr/iom6450.h>
-#elif (defined __AVR_ATmega6450A__)
-#include <avr/iom6450a.h>
-#elif (defined __AVR_ATmega6450P__)
-#include <avr/iom6450p.h>
-#elif defined (__AVR_ATmega649__)
-#  include <avr/iom649.h>
-#elif (defined __AVR_ATmega649A__)
-#include <avr/iom649a.h>
-#elif defined (__AVR_ATmega6490__)
-#  include <avr/iom6490.h>
-#elif (defined __AVR_ATmega6490A__)
-#include <avr/iom6490a.h>
-#elif (defined __AVR_ATmega6490P__)
-#include <avr/iom6490p.h>
-#elif defined (__AVR_ATmega649P__)
-#  include <avr/iom649p.h>
-#elif defined (__AVR_ATmega64HVE__)
-#  include <avr/iom64hve.h>
-#elif defined (__AVR_ATmega64HVE2__)
-#  include <avr/iom64hve2.h>
-#elif defined (__AVR_ATmega103__)
-#  include <avr/iom103.h>
-#elif defined (__AVR_ATmega32__)
-#  include <avr/iom32.h>
-#elif defined (__AVR_ATmega32A__)
-#  include <avr/iom32a.h>
-#elif defined (__AVR_ATmega323__)
-#  include <avr/iom323.h>
-#elif defined (__AVR_ATmega324P__)
-#  include <avr/iom324p.h>
+#if (defined __AVR_ATmega26HVG__)
+#include <avr/iom26hvg.h>
+#elif (defined __AVR_ATmega48HVF__)
+#include <avr/iom48hvf.h>
+#elif (defined __AVR_AT90PWM161__)
+#include <avr/io90pwm161.h>
+#elif (defined __AVR_ATmega256RFA2__)
+#include <avr/iom256rfa2.h>
+#elif (defined __AVR_ATmega128RFA2__)
+#include <avr/iom128rfa2.h>
+#elif (defined __AVR_ATmega64RFA2__)
+#include <avr/iom64rfa2.h>
+#elif (defined __AVR_ATmega256RFR2__)
+#include <avr/iom256rfr2.h>
+#elif (defined __AVR_ATmega128RFR2__)
+#include <avr/iom128rfr2.h>
+#elif (defined __AVR_ATmega64RFR2__)
+#include <avr/iom64rfr2.h>
+#elif (defined __AVR_ATmega2564RFR2__)
+#include <avr/iom2564rfr2.h>
+#elif (defined __AVR_ATmega1284RFR2__)
+#include <avr/iom1284rfr2.h>
+#elif (defined __AVR_ATmega644RFR2__)
+#include <avr/iom644rfr2.h>
+#elif (defined __AVR_ATmega32C1__)
+#include <avr/iom32c1.h>
+#elif (defined __AVR_ATmega64C1__)
+#include <avr/iom64c1.h>
+#elif (defined __AVR_ATA5831__)
+#include <avr/ioa5831.h>
+#elif (defined __AVR_ATA5832__)
+#include <avr/ioa5832.h>
+#elif (defined __AVR_ATA5833__)
+#include <avr/ioa5833.h>
+#elif (defined __AVR_ATA5272__)
+#include <avr/ioa5272.h>
+#elif (defined __AVR_ATA5505__)
+#include <avr/ioa5505.h>
+#elif (defined __AVR_ATA5790__)
+#include <avr/ioa5790.h>
+#elif (defined __AVR_ATA5795__)
+#include <avr/ioa5795.h>
+#elif (defined __AVR_ATA5790N__)
+#include <avr/ioa5790n.h>
+#elif (defined __AVR_ATA6285__)
+#include <avr/ioa6285.h>
+#elif (defined __AVR_ATA6286__)
+#include <avr/ioa6286.h>
+#elif (defined __AVR_AT90CAN128__)
+#include <avr/iocan128.h>
+#elif (defined __AVR_AT90CAN32__)
+#include <avr/iocan32.h>
+#elif (defined __AVR_AT90CAN64__)
+#include <avr/iocan64.h>
+#elif (defined __AVR_AT90PWM1__)
+#include <avr/io90pwm1.h>
+#elif (defined __AVR_AT90PWM216__)
+#include <avr/io90pwm216.h>
+#elif (defined __AVR_AT90PWM2B__)
+#include <avr/io90pwm2b.h>
+#elif (defined __AVR_AT90PWM316__)
+#include <avr/io90pwm316.h>
+#elif (defined __AVR_AT90PWM3B__)
+#include <avr/io90pwm3b.h>
+#elif (defined __AVR_AT90PWM81__)
+#include <avr/io90pwm81.h>
+#elif (defined __AVR_AT90USB1286__)
+#include <avr/iousb1286.h>
+#elif (defined __AVR_AT90USB1287__)
+#include <avr/iousb1287.h>
+#elif (defined __AVR_AT90USB162__)
+#include <avr/iousb162.h>
+#elif (defined __AVR_AT90USB646__)
+#include <avr/iousb646.h>
+#elif (defined __AVR_AT90USB647__)
+#include <avr/iousb647.h>
+#elif (defined __AVR_AT90USB82__)
+#include <avr/iousb82.h>
+#elif (defined __AVR_ATmega128__)
+#include <avr/iom128.h>
+#elif (defined __AVR_ATmega1280__)
+#include <avr/iom1280.h>
+#elif (defined __AVR_ATmega1281__)
+#include <avr/iom1281.h>
+#elif (defined __AVR_ATmega1284__)
+#include <avr/iom1284.h>
+#elif (defined __AVR_ATmega1284P__)
+#include <avr/iom1284p.h>
+#elif (defined __AVR_ATmega128A__)
+#include <avr/iom128a.h>
+#elif (defined __AVR_ATmega128RFA1__)
+#include <avr/iom128rfa1.h>
+#elif (defined __AVR_ATmega16__)
+#include <avr/iom16.h>
+#elif (defined __AVR_ATmega162__)
+#include <avr/iom162.h>
+#elif (defined __AVR_ATmega164A__)
+#include <avr/iom164a.h>
+#elif (defined __AVR_ATmega164P__)
+#include <avr/iom164p.h>
+#elif (defined __AVR_ATmega164PA__)
+#include <avr/iom164pa.h>
+#elif (defined __AVR_ATmega165A__)
+#include <avr/iom165a.h>
+#elif (defined __AVR_ATmega165P__)
+#include <avr/iom165p.h>
+#elif (defined __AVR_ATmega165PA__)
+#include <avr/iom165pa.h>
+#elif (defined __AVR_ATmega168__)
+#include <avr/iom168.h>
+#elif (defined __AVR_ATmega168A__)
+#include <avr/iom168a.h>
+#elif (defined __AVR_ATmega168P__)
+#include <avr/iom168p.h>
+#elif (defined __AVR_ATmega168PA__)
+#include <avr/iom168pa.h>
+#elif (defined __AVR_ATmega169A__)
+#include <avr/iom169a.h>
+#elif (defined __AVR_ATmega169P__)
+#include <avr/iom169p.h>
+#elif (defined __AVR_ATmega169PA__)
+#include <avr/iom169pa.h>
+#elif (defined __AVR_ATmega16A__)
+#include <avr/iom16a.h>
+#elif (defined __AVR_ATmega16HVB__)
+#include <avr/iom16hvb.h>
+#elif (defined __AVR_ATmega16HVBrevB__)
+#include <avr/iom16hvbrevb.h>
+#elif (defined __AVR_ATmega16HVA__)
+#include <avr/iom16hva.h>
+#elif (defined __AVR_ATmega16M1__)
+#include <avr/iom16m1.h>
+#elif (defined __AVR_ATmega16U2__)
+#include <avr/iom16u2.h>
+#elif (defined __AVR_ATmega16U4__)
+#include <avr/iom16u4.h>
+#elif (defined __AVR_ATmega2560__)
+#include <avr/iom2560.h>
+#elif (defined __AVR_ATmega2561__)
+#include <avr/iom2561.h>
+#elif (defined __AVR_ATmega32__)
+#include <avr/iom32.h>
 #elif (defined __AVR_ATmega324A__)
 #include <avr/iom324a.h>
-#elif defined (__AVR_ATmega324PA__)
-#  include <avr/iom324pa.h>
-#elif defined (__AVR_ATmega325__)
-#  include <avr/iom325.h>
-#elif (defined __AVR_ATmega325A__)
-#include <avr/iom325a.h>
-#elif defined (__AVR_ATmega325P__)
-#  include <avr/iom325p.h>
-#elif defined (__AVR_ATmega325PA__)
-#  include <avr/iom325pa.h>  
-#elif defined (__AVR_ATmega3250__) 
-#  include <avr/iom3250.h>
+#elif (defined __AVR_ATmega324P__)
+#include <avr/iom324p.h>
+#elif (defined __AVR_ATmega324PA__)
+#include <avr/iom324pa.h>
+#elif (defined __AVR_ATmega325__)
+#include <avr/iom325.h>
+#elif (defined __AVR_ATmega3250__)
+#include <avr/iom3250.h>
 #elif (defined __AVR_ATmega3250A__)
 #include <avr/iom3250a.h>
-#elif defined (__AVR_ATmega3250P__)
-#  include <avr/iom3250p.h>
-#elif defined (__AVR_ATmega3250PA__)
-#  include <avr/iom3250pa.h>  
-#elif defined (__AVR_ATmega328P__)
-#  include <avr/iom328p.h>
+#elif (defined __AVR_ATmega3250P__)
+#include <avr/iom3250p.h>
+#elif (defined __AVR_ATmega3250PA__)
+#include <avr/iom3250pa.h>
+#elif (defined __AVR_ATmega325A__)
+#include <avr/iom325a.h>
+#elif (defined __AVR_ATmega325P__)
+#include <avr/iom325p.h>
+#elif (defined __AVR_ATmega325PA__)
+#include <avr/iom325pa.h>
 #elif (defined __AVR_ATmega328__)
 #include <avr/iom328.h>
-#elif defined (__AVR_ATmega329__)
-#  include <avr/iom329.h>
+#elif (defined __AVR_ATmega328P__)
+#include <avr/iom328p.h>
+#elif (defined __AVR_ATmega329__)
+#include <avr/iom329.h>
+#elif (defined __AVR_ATmega3290__)
+#include <avr/iom3290.h>
+#elif (defined __AVR_ATmega3290A__)
+#include <avr/iom3290a.h>
+#elif (defined __AVR_ATmega3290P__)
+#include <avr/iom3290.h>
+#elif (defined __AVR_ATmega3290PA__)
+#include <avr/iom3290pa.h>
 #elif (defined __AVR_ATmega329A__)
 #include <avr/iom329a.h>
-#elif defined (__AVR_ATmega329P__) 
-#  include <avr/iom329p.h>
+#elif (defined __AVR_ATmega329P__)
+#include <avr/iom329p.h>
 #elif (defined __AVR_ATmega329PA__)
 #include <avr/iom329pa.h>
-#elif (defined __AVR_ATmega3290PA__)
-#include <avr/iom3290pa.h>
-#elif defined (__AVR_ATmega3290__)
-#  include <avr/iom3290.h>
-#elif (defined __AVR_ATmega3290A__)
-#include <avr/iom3290a.h>
-#elif defined (__AVR_ATmega3290P__)
-#  include <avr/iom3290.h>
-#elif defined (__AVR_ATmega32HVB__)
-#  include <avr/iom32hvb.h>
-#elif defined (__AVR_ATmega32HVBREVB__)
-#  include <avr/iom32hvbrevb.h>
-#elif defined (__AVR_ATmega406__)
-#  include <avr/iom406.h>
-#elif defined (__AVR_ATmega16__)
-#  include <avr/iom16.h>
-#elif defined (__AVR_ATmega16A__)
-#  include <avr/iom16a.h>
-#elif defined (__AVR_ATmega161__)
-#  include <avr/iom161.h>
-#elif defined (__AVR_ATmega162__)
-#  include <avr/iom162.h>
-#elif defined (__AVR_ATmega163__)
-#  include <avr/iom163.h>
-#elif defined (__AVR_ATmega164P__)
-#  include <avr/iom164p.h>
-#elif (defined __AVR_ATmega164A__)
-#include <avr/iom164a.h>
-#elif defined (__AVR_ATmega164PA__)
-#  include <avr/iom164pa.h>
-#elif defined (__AVR_ATmega165__)
-#  include <avr/iom165.h>
-#elif (defined __AVR_ATmega165A__)
-#include <avr/iom165a.h>
-#elif defined (__AVR_ATmega165P__)
-#  include <avr/iom165p.h>
-#elif defined (__AVR_ATmega165PA__)
-#  include <avr/iom165pa.h>
-#elif defined (__AVR_ATmega168__)
-#  include <avr/iom168.h>
-#elif (defined __AVR_ATmega168A__)
-#include <avr/iom168a.h>
-#elif defined (__AVR_ATmega168P__)
-#  include <avr/iom168p.h>
-#elif defined (__AVR_ATmega168PA__)
-#  include <avr/iom168pa.h>
-#elif defined (__AVR_ATmega169__)
-#  include <avr/iom169.h>
-#elif (defined __AVR_ATmega169A__)
-#include <avr/iom169a.h>
-#elif defined (__AVR_ATmega169P__)
-#  include <avr/iom169p.h>
-#elif defined (__AVR_ATmega169PA__)
-#  include <avr/iom169pa.h>
-#elif defined (__AVR_ATmega8HVA__)
-#  include <avr/iom8hva.h>
-#elif defined (__AVR_ATmega16HVA__)
-#  include <avr/iom16hva.h>
-#elif defined (__AVR_ATmega16HVA2__)
-#  include <avr/iom16hva2.h>
-#elif defined (__AVR_ATmega16HVB__)
-#  include <avr/iom16hvb.h>
-#elif defined (__AVR_ATmega16HVBREVB__)
-#  include <avr/iom16hvbrevb.h>
-#elif defined (__AVR_ATmega8__)
-#  include <avr/iom8.h>
-#elif defined (__AVR_ATmega8A__)
-#  include <avr/iom8a.h>
+#elif (defined __AVR_ATmega32A__)
+#include <avr/iom32a.h>
+#elif (defined __AVR_ATmega32HVB__)
+#include <avr/iom32hvb.h>
+#elif (defined __AVR_ATmega32HVBrevB__)
+#include <avr/iom32hvbrevb.h>
+#elif (defined __AVR_ATmega32M1__)
+#include <avr/iom32m1.h>
+#elif (defined __AVR_ATmega32U2__)
+#include <avr/iom32u2.h>
+#elif (defined __AVR_ATmega32U4__)
+#include <avr/iom32u4.h>
+#elif (defined __AVR_ATmega48__)
+#include <avr/iom48.h>
 #elif (defined __AVR_ATmega48A__)
-#  include <avr/iom48a.h>
-#elif defined (__AVR_ATmega48__)
-#  include <avr/iom48.h>
-#elif defined (__AVR_ATmega48PA__)
-#  include <avr/iom48pa.h>
-#elif defined (__AVR_ATmega48P__)
-#  include <avr/iom48p.h>
-#elif defined (__AVR_ATmega88__)
-#  include <avr/iom88.h>
+#include <avr/iom48a.h>
+#elif (defined __AVR_ATmega48P__)
+#include <avr/iom48p.h>
+#elif (defined __AVR_ATmega48PA__)
+#include <avr/iom48pa.h>
+#elif (defined __AVR_ATmega64__)
+#include <avr/iom64.h>
+#elif (defined __AVR_ATmega640__)
+#include <avr/iom640.h>
+#elif (defined __AVR_ATmega644__)
+#include <avr/iom644.h>
+#elif (defined __AVR_ATmega644A__)
+#include <avr/iom644a.h>
+#elif (defined __AVR_ATmega644P__)
+#include <avr/iom644p.h>
+#elif (defined __AVR_ATmega644PA__)
+#include <avr/iom644pa.h>
+#elif (defined __AVR_ATmega645__)
+#include <avr/iom645.h>
+#elif (defined __AVR_ATmega6450__)
+#include <avr/iom6450.h>
+#elif (defined __AVR_ATmega6450A__)
+#include <avr/iom6450a.h>
+#elif (defined __AVR_ATmega6450P__)
+#include <avr/iom6450p.h>
+#elif (defined __AVR_ATmega645A__)
+#include <avr/iom645a.h>
+#elif (defined __AVR_ATmega645P__)
+#include <avr/iom645p.h>
+#elif (defined __AVR_ATmega649__)
+#include <avr/iom649.h>
+#elif (defined __AVR_ATmega6490__)
+#include <avr/iom6490.h>
+#elif (defined __AVR_ATmega6490A__)
+#include <avr/iom6490a.h>
+#elif (defined __AVR_ATmega6490P__)
+#include <avr/iom6490p.h>
+#elif (defined __AVR_ATmega649A__)
+#include <avr/iom649a.h>
+#elif (defined __AVR_ATmega649P__)
+#include <avr/iom649p.h>
+#elif (defined __AVR_ATmega64A__)
+#include <avr/iom64a.h>
+#elif (defined __AVR_ATmega64HVE2__)
+#include <avr/iom64hve2.h>
+#elif (defined __AVR_ATmega64M1__)
+#include <avr/iom64m1.h>
+#elif (defined __AVR_ATmega8__)
+#include <avr/iom8.h>
+#elif (defined __AVR_ATmega8HVA__)
+#include <avr/iom8hva.h>
+#elif (defined __AVR_ATmega8515__)
+#include <avr/iom8515.h>
+#elif (defined __AVR_ATmega8535__)
+#include <avr/iom8535.h>
+#elif (defined __AVR_ATmega88__)
+#include <avr/iom88.h>
 #elif (defined __AVR_ATmega88A__)
-#  include <avr/iom88a.h>
-#elif defined (__AVR_ATmega88P__)
-#  include <avr/iom88p.h>
-#elif defined (__AVR_ATmega88PA__)
-#  include <avr/iom88pa.h>
-#elif defined (__AVR_ATmega8515__)
-#  include <avr/iom8515.h>
-#elif defined (__AVR_ATmega8535__)
-#  include <avr/iom8535.h>
-#elif defined (__AVR_AT90S8535__)
-#  include <avr/io8535.h>
-#elif defined (__AVR_AT90C8534__)
-#  include <avr/io8534.h>
-#elif defined (__AVR_AT90S8515__)
-#  include <avr/io8515.h>
-#elif defined (__AVR_AT90S4434__)
-#  include <avr/io4434.h>
-#elif defined (__AVR_AT90S4433__)
-#  include <avr/io4433.h>
-#elif defined (__AVR_AT90S4414__)
-#  include <avr/io4414.h>
-#elif defined (__AVR_ATtiny22__)
-#  include <avr/iotn22.h>
-#elif defined (__AVR_ATtiny26__)
-#  include <avr/iotn26.h>
-#elif defined (__AVR_AT90S2343__)
-#  include <avr/io2343.h>
-#elif defined (__AVR_AT90S2333__)
-#  include <avr/io2333.h>
-#elif defined (__AVR_AT90S2323__)
-#  include <avr/io2323.h>
-#elif defined (__AVR_AT90S2313__)
-#  include <avr/io2313.h>
-#elif defined (__AVR_ATtiny4__)
-#  include <avr/iotn4.h>
-#elif defined (__AVR_ATtiny5__)
-#  include <avr/iotn5.h>
-#elif defined (__AVR_ATtiny9__)
-#  include <avr/iotn9.h>
-#elif defined (__AVR_ATtiny10__)
-#  include <avr/iotn10.h>
-#elif defined (__AVR_ATtiny20__)
-#  include <avr/iotn20.h>
-#elif defined (__AVR_ATtiny40__)
-#  include <avr/iotn40.h>
-#elif defined (__AVR_ATtiny2313__)
-#  include <avr/iotn2313.h>
-#elif defined (__AVR_ATtiny2313A__)
-#  include <avr/iotn2313a.h>
-#elif defined (__AVR_ATtiny13__)
-#  include <avr/iotn13.h>
-#elif defined (__AVR_ATtiny13A__)
-#  include <avr/iotn13a.h>
-#elif defined (__AVR_ATtiny25__)
-#  include <avr/iotn25.h>
-#elif defined (__AVR_ATtiny4313__)
-#  include <avr/iotn4313.h>
-#elif defined (__AVR_ATtiny45__)
-#  include <avr/iotn45.h>
-#elif defined (__AVR_ATtiny85__)
-#  include <avr/iotn85.h>
-#elif defined (__AVR_ATtiny24__)
-#  include <avr/iotn24.h>
-#elif defined (__AVR_ATtiny24A__)
-#  include <avr/iotn24a.h>
-#elif defined (__AVR_ATtiny44__)
-#  include <avr/iotn44.h>
-#elif defined (__AVR_ATtiny44A__)
-#  include <avr/iotn44a.h>
-#elif defined (__AVR_ATtiny84__)
-#  include <avr/iotn84.h>
-#elif defined (__AVR_ATtiny84A__)
-#  include <avr/iotn84a.h>  
-#elif defined (__AVR_ATtiny261__)
-#  include <avr/iotn261.h>
-#elif defined (__AVR_ATtiny261A__)
-#  include <avr/iotn261a.h>
-#elif defined (__AVR_ATtiny461__)
-#  include <avr/iotn461.h>
-#elif defined (__AVR_ATtiny461A__)
-#  include <avr/iotn461a.h>
-#elif defined (__AVR_ATtiny861__)
-#  include <avr/iotn861.h>
-#elif defined (__AVR_ATtiny861A__)
-#  include <avr/iotn861a.h>
-#elif defined (__AVR_ATtiny43U__)
-#  include <avr/iotn43u.h>
-#elif defined (__AVR_ATtiny48__)
-#  include <avr/iotn48.h>
-#elif defined (__AVR_ATtiny88__)
-#  include <avr/iotn88.h>
-#elif defined (__AVR_ATtiny828__)
-#  include <avr/iotn828.h>
-#elif defined (__AVR_ATtiny87__)
-#  include <avr/iotn87.h>
-#elif defined (__AVR_ATtiny167__)
-#  include <avr/iotn167.h>
-#elif defined (__AVR_ATtiny1634__)
-#  include <avr/iotn1634.h>
-#elif defined (__AVR_AT90SCR100__)
-#  include <avr/io90scr100.h>
-#elif defined (__AVR_ATxmega16A4__)
-#  include <avr/iox16a4.h>
-#elif defined (__AVR_ATxmega16A4U__)
-#  include <avr/iox16a4u.h>
-#elif defined (__AVR_ATxmega16C4__)
-#  include <avr/iox16c4.h>
-#elif defined (__AVR_ATxmega16D4__)
-#  include <avr/iox16d4.h>
-#elif defined (__AVR_ATxmega32A4__)
-#  include <avr/iox32a4.h>
-#elif defined (__AVR_ATxmega32A4U__)
-#  include <avr/iox32a4u.h>
-#elif defined (__AVR_ATxmega32C4__)
-#  include <avr/iox32c4.h>
-#elif defined (__AVR_ATxmega32D4__)
-#  include <avr/iox32d4.h>
-#elif defined (__AVR_ATxmega8E5__)
-#  include <avr/iox8e5.h>
-#elif defined (__AVR_ATxmega16E5__)
-#  include <avr/iox16e5.h>
-#elif defined (__AVR_ATxmega32E5__)
-#  include <avr/iox32e5.h>
-#elif defined (__AVR_ATxmega64A1__)
-#  include <avr/iox64a1.h>
-#elif defined (__AVR_ATxmega64A1U__)
-#  include <avr/iox64a1u.h>
-#elif defined (__AVR_ATxmega64A3__)
-#  include <avr/iox64a3.h>
-#elif defined (__AVR_ATxmega64A3U__)
-#  include <avr/iox64a3u.h>
-#elif defined (__AVR_ATxmega64A4U__)
-#  include <avr/iox64a4u.h>
-#elif defined (__AVR_ATxmega64B1__)
-#  include <avr/iox64b1.h>
-#elif defined (__AVR_ATxmega64B3__)
-#  include <avr/iox64b3.h>
-#elif defined (__AVR_ATxmega64C3__)
-#  include <avr/iox64c3.h>
-#elif defined (__AVR_ATxmega64D3__)
-#  include <avr/iox64d3.h>
-#elif defined (__AVR_ATxmega64D4__)
-#  include <avr/iox64d4.h>
-#elif defined (__AVR_ATxmega128A1__)
-#  include <avr/iox128a1.h>
-#elif defined (__AVR_ATxmega128A1U__)
-#  include <avr/iox128a1u.h>
-#elif defined (__AVR_ATxmega128A4U__)
-#  include <avr/iox128a4u.h>
-#elif defined (__AVR_ATxmega128A3__)
-#  include <avr/iox128a3.h>
-#elif defined (__AVR_ATxmega128A3U__)
-#  include <avr/iox128a3u.h>
-#elif defined (__AVR_ATxmega128B1__)
-#  include <avr/iox128b1.h>
-#elif defined (__AVR_ATxmega128B3__)
-#  include <avr/iox128b3.h>
-#elif defined (__AVR_ATxmega128C3__)
-#  include <avr/iox128c3.h>
-#elif defined (__AVR_ATxmega128D3__)
-#  include <avr/iox128d3.h>
-#elif defined (__AVR_ATxmega128D4__)
-#  include <avr/iox128d4.h>
-#elif defined (__AVR_ATxmega192A3__)
-#  include <avr/iox192a3.h>
-#elif defined (__AVR_ATxmega192A3U__)
-#  include <avr/iox192a3u.h>
-#elif defined (__AVR_ATxmega192C3__)
-#  include <avr/iox192c3.h>
-#elif defined (__AVR_ATxmega192D3__)
-#  include <avr/iox192d3.h>
-#elif defined (__AVR_ATxmega256A3__)
-#  include <avr/iox256a3.h>
-#elif defined (__AVR_ATxmega256A3U__)
-#  include <avr/iox256a3u.h>
-#elif defined (__AVR_ATxmega256A3B__)
-#  include <avr/iox256a3b.h>
-#elif defined (__AVR_ATxmega256A3BU__)
-#  include <avr/iox256a3bu.h>
-#elif defined (__AVR_ATxmega256C3__)
-#  include <avr/iox256c3.h>
-#elif defined (__AVR_ATxmega256D3__)
-#  include <avr/iox256d3.h>
-#elif defined (__AVR_ATxmega384C3__)
-#  include <avr/iox384c3.h>
-#elif defined (__AVR_ATxmega384D3__)
-#  include <avr/iox384d3.h>
-#elif defined (__AVR_ATA5790__)
-#  include <avr/ioa5790.h>
-#elif defined (__AVR_ATA5790N__)
-#  include <avr/ioa5790n.h>
-#elif defined (__AVR_ATA5272__)
-#  include <avr/ioa5272.h>
-#elif defined (__AVR_ATA5505__)
-#  include <avr/ioa5505.h>
-#elif defined (__AVR_ATA5795__)
-#  include <avr/ioa5795.h>
-#elif defined (__AVR_ATA5831__)
-#  include <avr/ioa5831.h>
-#elif defined (__AVR_ATA6285__)
-#  include <avr/ioa6285.h>
-#elif defined (__AVR_ATA6286__)
-#  include <avr/ioa6286.h>
-#elif defined (__AVR_ATA6289__)
-#  include <avr/ioa6289.h>
-/* avr1: the following only supported for assembler programs */
-#elif defined (__AVR_ATtiny28__)
-#  include <avr/iotn28.h>
-#elif defined (__AVR_AT90S1200__)
-#  include <avr/io1200.h>
-#elif defined (__AVR_ATtiny15__)
-#  include <avr/iotn15.h>
-#elif defined (__AVR_ATtiny12__)
-#  include <avr/iotn12.h>
-#elif defined (__AVR_ATtiny11__)
-#  include <avr/iotn11.h>
-#elif defined (__AVR_M3000__)
-#  include <avr/iom3000.h>
+#include <avr/iom88a.h>
+#elif (defined __AVR_ATmega88P__)
+#include <avr/iom88p.h>
+#elif (defined __AVR_ATmega88PA__)
+#include <avr/iom88pa.h>
+#elif (defined __AVR_ATmega8A__)
+#include <avr/iom8a.h>
+#elif (defined __AVR_ATmega8U2__)
+#include <avr/iom8u2.h>
+#elif (defined __AVR_ATtiny10__)
+#include <avr/iotn10.h>
+#elif (defined __AVR_ATtiny13__)
+#include <avr/iotn13.h>
+#elif (defined __AVR_ATtiny13A__)
+#include <avr/iotn13a.h>
+#elif (defined __AVR_ATtiny167__)
+#include <avr/iotn167.h>
+#elif (defined __AVR_ATtiny20__)
+#include <avr/iotn20.h>
+#elif (defined __AVR_ATtiny2313__)
+#include <avr/iotn2313.h>
+#elif (defined __AVR_ATtiny2313A__)
+#include <avr/iotn2313a.h>
+#elif (defined __AVR_ATtiny24__)
+#include <avr/iotn24.h>
+#elif (defined __AVR_ATtiny24A__)
+#include <avr/iotn24a.h>
+#elif (defined __AVR_ATtiny25__)
+#include <avr/iotn25.h>
+#elif (defined __AVR_ATtiny26__)
+#include <avr/iotn26.h>
+#elif (defined __AVR_ATtiny261__)
+#include <avr/iotn261.h>
+#elif (defined __AVR_ATtiny261A__)
+#include <avr/iotn261a.h>
+#elif (defined __AVR_ATtiny28__)
+#include <avr/iotn28.h>
+#elif (defined __AVR_ATtiny4__)
+#include <avr/iotn4.h>
+#elif (defined __AVR_ATtiny40__)
+#include <avr/iotn40.h>
+#elif (defined __AVR_ATtiny4313__)
+#include <avr/iotn4313.h>
+#elif (defined __AVR_ATtiny43U__)
+#include <avr/iotn43u.h>
+#elif (defined __AVR_ATtiny44__)
+#include <avr/iotn44.h>
+#elif (defined __AVR_ATtiny44A__)
+#include <avr/iotn44a.h>
+#elif (defined __AVR_ATtiny45__)
+#include <avr/iotn45.h>
+#elif (defined __AVR_ATtiny48__)
+#include <avr/iotn48.h>
+#elif (defined __AVR_ATtiny461__)
+#include <avr/iotn461.h>
+#elif (defined __AVR_ATtiny461A__)
+#include <avr/iotn461a.h>
+#elif (defined __AVR_ATtiny474__)
+#include <avr/iotn474.h>
+#elif (defined __AVR_ATtiny5__)
+#include <avr/iotn5.h>
+#elif (defined __AVR_ATtiny84__)
+#include <avr/iotn84.h>
+#elif (defined __AVR_ATtiny84A__)
+#include <avr/iotn84a.h>
+#elif (defined __AVR_ATtiny841__)
+#include <avr/iotn841.h>
+#elif (defined __AVR_ATtiny85__)
+#include <avr/iotn85.h>
+#elif (defined __AVR_ATtiny861__)
+#include <avr/iotn861.h>
+#elif (defined __AVR_ATtiny861A__)
+#include <avr/iotn861a.h>
+#elif (defined __AVR_ATtiny87__)
+#include <avr/iotn87.h>
+#elif (defined __AVR_ATtiny88__)
+#include <avr/iotn88.h>
+#elif (defined __AVR_ATtiny9__)
+#include <avr/iotn9.h>
+#elif (defined __AVR_ATtiny1634__)
+#include <avr/iotn1634.h>
+#elif (defined __AVR_ATtiny80__)
+#include <avr/iotn80.h>
+#elif (defined __AVR_ATtiny828__)
+#include <avr/iotn828.h>
+#elif (defined __AVR_ATxmega128B1__)
+#include <avr/iox128b1.h>
+#elif (defined __AVR_ATxmega64B1__)
+#include <avr/iox64b1.h>
+#elif (defined __AVR_ATxmega64B3__)
+#include <avr/iox64b3.h>
+#elif (defined __AVR_ATxmega128B3__)
+#include <avr/iox128b3.h>
+#elif (defined __AVR_ATxmega32A4U__)
+#include <avr/iox32a4u.h>
+#elif (defined __AVR_ATxmega16A4U__)
+#include <avr/iox16a4u.h>
+#elif (defined __AVR_ATxmega32A4__)
+#include <avr/iox32a4.h>
+#elif (defined __AVR_ATxmega16A4__)
+#include <avr/iox16a4.h>
+#elif (defined __AVR_ATxmega32D4__)
+#include <avr/iox32d4.h>
+#elif (defined __AVR_ATxmega16D4__)
+#include <avr/iox16d4.h>
+#elif (defined __AVR_ATxmega128A1U__)
+#include <avr/iox128a1u.h>
+#elif (defined __AVR_ATxmega64A1U__)
+#include <avr/iox64a1u.h>
+#elif (defined __AVR_ATxmega128A1__)
+#include <avr/iox128a1.h>
+#elif (defined __AVR_ATxmega64A1__)
+#include <avr/iox64a1.h>
+#elif (defined __AVR_ATxmega256A3BU__)
+#include <avr/iox256a3bu.h>
+#elif (defined __AVR_ATxmega256A3B__)
+#include <avr/iox256a3b.h>
+#elif (defined __AVR_ATxmega256A3U__)
+#include <avr/iox256a3u.h>
+#elif (defined __AVR_ATxmega192A3U__)
+#include <avr/iox192a3u.h>
+#elif (defined __AVR_ATxmega128A3U__)
+#include <avr/iox128a3u.h>
+#elif (defined __AVR_ATxmega64A3U__)
+#include <avr/iox64a3u.h>
+#elif (defined __AVR_ATxmega256A3__)
+#include <avr/iox256a3.h>
+#elif (defined __AVR_ATxmega192A3__)
+#include <avr/iox192a3.h>
+#elif (defined __AVR_ATxmega128A3__)
+#include <avr/iox128a3.h>
+#elif (defined __AVR_ATxmega64A3__)
+#include <avr/iox64a3.h>
+#elif (defined __AVR_ATxmega256D3__)
+#include <avr/iox256d3.h>
+#elif (defined __AVR_ATxmega192D3__)
+#include <avr/iox192d3.h>
+#elif (defined __AVR_ATxmega128D3__)
+#include <avr/iox128d3.h>
+#elif (defined __AVR_ATxmega64D3__)
+#include <avr/iox64d3.h>
+#elif (defined __AVR_ATxmega384C3__)
+#include <avr/iox384c3.h>
+#elif (defined __AVR_ATxmega384D3__)
+#include <avr/iox384d3.h>
+#elif (defined __AVR_ATxmega128A4U__)
+#include <avr/iox128a4u.h>
+#elif (defined __AVR_ATxmega64A4U__)
+#include <avr/iox64a4u.h>
+#elif (defined __AVR_ATxmega128D4__)
+#include <avr/iox128d4.h>
+#elif (defined __AVR_ATxmega64D4__)
+#include <avr/iox64d4.h>
+#elif (defined __AVR_ATxmega32X1__)
+#include <avr/iox32x1.h>
+#elif (defined __AVR_ATxmega256C3__)
+#include <avr/iox256c3.h>
+#elif (defined __AVR_ATxmega192C3__)
+#include <avr/iox192c3.h>
+#elif (defined __AVR_ATxmega128C3__)
+#include <avr/iox128c3.h>
+#elif (defined __AVR_ATxmega64C3__)
+#include <avr/iox64c3.h>
+#elif (defined __AVR_ATxmega32C4__)
+#include <avr/iox32c4.h>
+#elif (defined __AVR_ATxmega16C4__)
+#include <avr/iox16c4.h>
+#elif (defined __AVR_ATmXT540S__)
+#include <avr/iomxt540s.h>
+#elif (defined __AVR_ATmXT540SrevA__)
+#include <avr/iomxt540sreva.h>
+#elif (defined __AVR_ATmXT336S__)
+#include <avr/iomxt336s.h>
+#elif (defined __AVR_ATmXT112SL__)
+#include <avr/iomxt112sl.h>
+#elif (defined __AVR_ATmXT224E__)
+#include <avr/iomxt224e.h>
+#elif (defined __AVR_ATmXT224__)
+#include <avr/iomxt224.h>
+#elif (defined __AVR_ATmXTS200__)
+#include <avr/iomxts200.h>
+#elif (defined __AVR_ATxmega32E5__)
+#include <avr/iox32e5.h>
+#elif (defined __AVR_ATxmega16E5__)
+#include <avr/iox16e5.h>
+#elif (defined __AVR_ATxmega8E5__)
+#include <avr/iox8e5.h>
 #else
 #  if !defined(__COMPILING_AVR_LIBC__)
 #    warning "device type not defined"
diff -urN avr-libc-1.8.0.orig/include/avr/iom103.h avr-libc-1.8.0/include/avr/iom103.h
--- avr-libc-1.8.0.orig/include/avr/iom103.h	2011-12-29 09:51:50.000000000 +0100
+++ avr-libc-1.8.0/include/avr/iom103.h	2013-06-12 12:21:34.000000000 +0200
@@ -202,7 +202,7 @@
 /* Timer/Counter Interrupt MaSK register */
 #define TIMSK	_SFR_IO8(0x37)