- cleanup, updated BRs, stub texinfo build (not packaged and would require patch...

[packages/crossavr-gcc.git] / 503-gcc-avrtc-513.patch

diff -Naurp gcc/config/avr/avr.c gcc/config/avr/avr.c
--- gcc/config/avr/avr.c	2012-12-06 19:22:10.000000000 +0530
+++ gcc/config/avr/avr.c	2012-12-06 19:23:44.000000000 +0530
@@ -169,7 +169,7 @@ static bool avr_rtx_costs (rtx, int, int
 #define FIRST_CUM_REG 26
 
 /* Last call saved register */
-#define LAST_CALLEE_SAVED_REG (AVR_TINY ? 21 : 17)
+#define LAST_CALLEE_SAVED_REG (AVR_TINY ? 19 : 17)
 
 /* Implicit target register of LPM instruction (R0) */
 extern GTY(()) rtx lpm_reg_rtx;
@@ -7451,7 +7451,8 @@ avr_assemble_integer (rtx x, unsigned in
 static bool
 avr_class_likely_spilled_p (reg_class_t c)
 {
-  return (c != ALL_REGS && c != ADDW_REGS);
+  return (c != ALL_REGS &&
+           (AVR_TINY ? 1 : c != ADDW_REGS));
 }
 
 /* Valid attributes:
@@ -8168,12 +8169,13 @@ order_regs_for_local_alloc (void)
     32,33,34,35
   };
   static const int tiny_order_0[] = {
-    24,25,
+    20,21,
     22,23,
+    24,25,
     30,31,
     26,27,
     28,29,
-    21,20,19,18,
+    19,18,
     16,17,
     32,33,34,35,
     15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0
@@ -8220,7 +8222,7 @@ order_regs_for_local_alloc (void)
   devices has only 16 registers, so different allocation order should be used
   */ 
   const int *order = (TARGET_ORDER_1 ? (AVR_TINY ? tiny_order_1 : order_1) :
-             TARGET_ORDER_2 ? (AVR_TINY ? tiny_order_1 : order_2) :
+             TARGET_ORDER_2 ? (AVR_TINY ? tiny_order_0 : order_2) :
                                        (AVR_TINY ? tiny_order_0 : order_0));
 
   for (i=0; i < ARRAY_SIZE (order_0); ++i)
@@ -10090,12 +10092,13 @@ avr_conditional_register_usage(void) {
     unsigned int i;
 
     const int tiny_reg_alloc_order[] = {
-      24,25,
+      20,21,
       22,23,
+      24,25,
       30,31,
       26,27,
       28,29,
-      21,20,19,18,
+      19,18,
       16,17,
       32,33,34,35,
       15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0