--- /dev/null
+--- cpqarrayd-2.2/configure.ac.orig 2005-07-28 16:33:41.000000000 +0200
++++ cpqarrayd-2.2/configure.ac 2006-03-09 11:31:02.000000000 +0100
+@@ -19,7 +19,7 @@
+ dnl Check for pathed kernel sources with ida_ioctl.h
+ AC_MSG_CHECKING(for SmartArray header directories)
+ found_kernel_dir=""
+-for kernel_dir in /usr/src/linux /usr/src/linux-2.4
++for kernel_dir in .
+ do
+ if test -d $kernel_dir ; then
+ CFLAGS="$CFLAGS -I$kernel_dir/include -I$kernel_dir/drivers/block"
+diff -Nur cpqarrayd-2.2/drivers.orig/block/cpqarray.h cpqarrayd-2.2/drivers/block/cpqarray.h
+--- cpqarrayd-2.2/drivers.orig/block/cpqarray.h 1970-01-01 01:00:00.000000000 +0100
++++ cpqarrayd-2.2/drivers/block/cpqarray.h 2005-11-17 16:51:31.000000000 +0100
+@@ -0,0 +1,132 @@
++/*
++ * Disk Array driver for Compaq SMART2 Controllers
++ * Copyright 1998 Compaq Computer Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
++ * NON INFRINGEMENT. See the GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ * Questions/Comments/Bugfixes to arrays@compaq.com
++ *
++ * If you want to make changes, improve or add functionality to this
++ * driver, you'll probably need the Compaq Array Controller Interface
++ * Specificiation (Document number ECG086/1198)
++ */
++#ifndef CPQARRAY_H
++#define CPQARRAY_H
++
++#ifdef __KERNEL__
++#include <linux/blkdev.h>
++#include <linux/locks.h>
++#include <linux/slab.h>
++#include <linux/proc_fs.h>
++#include <linux/timer.h>
++#endif
++
++#include "ida_cmd.h"
++
++#define IO_OK 0
++#define IO_ERROR 1
++#define NWD 16
++#define NWD_SHIFT 4
++#define IDA_MAX_PART 16
++
++#define IDA_TIMER (5*HZ)
++#define IDA_TIMEOUT (10*HZ)
++
++#define MISC_NONFATAL_WARN 0x01
++
++typedef struct {
++ unsigned blk_size;
++ unsigned nr_blks;
++ unsigned cylinders;
++ unsigned heads;
++ unsigned sectors;
++ int usage_count;
++} drv_info_t;
++
++#ifdef __KERNEL__
++
++struct ctlr_info;
++typedef struct ctlr_info ctlr_info_t;
++
++struct access_method {
++ void (*submit_command)(ctlr_info_t *h, cmdlist_t *c);
++ void (*set_intr_mask)(ctlr_info_t *h, unsigned long val);
++ unsigned long (*fifo_full)(ctlr_info_t *h);
++ unsigned long (*intr_pending)(ctlr_info_t *h);
++ unsigned long (*command_completed)(ctlr_info_t *h);
++};
++
++struct board_type {
++ __u32 board_id;
++ char *product_name;
++ struct access_method *access;
++};
++
++struct ctlr_info {
++ int ctlr;
++ char devname[8];
++ __u32 log_drv_map;
++ __u32 drv_assign_map;
++ __u32 drv_spare_map;
++ __u32 mp_failed_drv_map;
++
++ char firm_rev[4];
++ struct pci_dev *pdev;
++ int ctlr_sig;
++
++ int log_drives;
++ int highest_lun;
++ int phys_drives;
++
++ struct pci_dev *pci_dev; /* NULL if EISA */
++ __u32 board_id;
++ char *product_name;
++
++ void *vaddr;
++ unsigned long paddr;
++ unsigned long io_mem_addr;
++ unsigned long io_mem_length;
++ int intr;
++ int usage_count;
++ drv_info_t drv[NWD];
++ struct proc_dir_entry *proc;
++
++ struct access_method access;
++
++ cmdlist_t *reqQ;
++ cmdlist_t *cmpQ;
++ cmdlist_t *cmd_pool;
++ dma_addr_t cmd_pool_dhandle;
++ __u32 *cmd_pool_bits;
++
++ unsigned int Qdepth;
++ unsigned int maxQsinceinit;
++
++ unsigned int nr_requests;
++ unsigned int nr_allocs;
++ unsigned int nr_frees;
++ struct timer_list timer;
++ unsigned int misc_tflags;
++ // Disk structures we need to pass back
++ struct gendisk gendisk;
++ // Index by Minor Numbers
++ struct hd_struct hd[256];
++ int sizes[256];
++ int blocksizes[256];
++ int hardsizes[256];
++};
++#endif
++
++#endif /* CPQARRAY_H */
+diff -Nur cpqarrayd-2.2/drivers.orig/block/ida_cmd.h cpqarrayd-2.2/drivers/block/ida_cmd.h
+--- cpqarrayd-2.2/drivers.orig/block/ida_cmd.h 1970-01-01 01:00:00.000000000 +0100
++++ cpqarrayd-2.2/drivers/block/ida_cmd.h 2005-11-17 16:51:31.000000000 +0100
+@@ -0,0 +1,351 @@
++/*
++ * Disk Array driver for Compaq SMART2 Controllers
++ * Copyright 1998 Compaq Computer Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
++ * NON INFRINGEMENT. See the GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ * Questions/Comments/Bugfixes to arrays@compaq.com
++ *
++ */
++#ifndef ARRAYCMD_H
++#define ARRAYCMD_H
++
++#include <asm/types.h>
++#if 0
++#include <linux/blkdev.h>
++#endif
++
++/* for the Smart Array 42XX cards */
++#define S42XX_REQUEST_PORT_OFFSET 0x40
++#define S42XX_REPLY_INTR_MASK_OFFSET 0x34
++#define S42XX_REPLY_PORT_OFFSET 0x44
++#define S42XX_INTR_STATUS 0x30
++
++#define S42XX_INTR_OFF 0x08
++#define S42XX_INTR_PENDING 0x08
++
++#define COMMAND_FIFO 0x04
++#define COMMAND_COMPLETE_FIFO 0x08
++#define INTR_MASK 0x0C
++#define INTR_STATUS 0x10
++#define INTR_PENDING 0x14
++
++#define FIFO_NOT_EMPTY 0x01
++#define FIFO_NOT_FULL 0x02
++
++#define BIG_PROBLEM 0x40
++#define LOG_NOT_CONF 2
++
++#pragma pack(1)
++typedef struct {
++ __u32 size;
++ __u32 addr;
++} sg_t;
++
++#define RCODE_NONFATAL 0x02
++#define RCODE_FATAL 0x04
++#define RCODE_INVREQ 0x10
++typedef struct {
++ __u16 next;
++ __u8 cmd;
++ __u8 rcode;
++ __u32 blk;
++ __u16 blk_cnt;
++ __u8 sg_cnt;
++ __u8 reserved;
++} rhdr_t;
++
++#define SG_MAX 32
++typedef struct {
++ rhdr_t hdr;
++ sg_t sg[SG_MAX];
++ __u32 bp;
++} rblk_t;
++
++typedef struct {
++ __u8 unit;
++ __u8 prio;
++ __u16 size;
++} chdr_t;
++
++#define CMD_RWREQ 0x00
++#define CMD_IOCTL_PEND 0x01
++
++typedef struct cmdlist {
++ chdr_t hdr;
++ rblk_t req;
++ __u32 size;
++ int retry_cnt;
++ __u32 busaddr;
++ int ctlr;
++ struct cmdlist *prev;
++ struct cmdlist *next;
++ struct request *rq;
++ struct completion *waiting;
++ int type;
++} cmdlist_t;
++
++#define ID_CTLR 0x11
++typedef struct {
++ __u8 nr_drvs;
++ __u32 cfg_sig;
++ __u8 firm_rev[4];
++ __u8 rom_rev[4];
++ __u8 hw_rev;
++ __u32 bb_rev;
++ __u32 drv_present_map;
++ __u32 ext_drv_map;
++ __u32 board_id;
++ __u8 cfg_error;
++ __u32 non_disk_bits;
++ __u8 bad_ram_addr;
++ __u8 cpu_rev;
++ __u8 pdpi_rev;
++ __u8 epic_rev;
++ __u8 wcxc_rev;
++ __u8 marketing_rev;
++ __u8 ctlr_flags;
++ __u8 host_flags;
++ __u8 expand_dis;
++ __u8 scsi_chips;
++ __u32 max_req_blocks;
++ __u32 ctlr_clock;
++ __u8 drvs_per_bus;
++ __u16 big_drv_present_map[8];
++ __u16 big_ext_drv_map[8];
++ __u16 big_non_disk_map[8];
++ __u16 task_flags;
++ __u8 icl_bus;
++ __u8 red_modes;
++ __u8 cur_red_mode;
++ __u8 red_ctlr_stat;
++ __u8 red_fail_reason;
++ __u8 reserved[403];
++} id_ctlr_t;
++
++typedef struct {
++ __u16 cyl;
++ __u8 heads;
++ __u8 xsig;
++ __u8 psectors;
++ __u16 wpre;
++ __u8 maxecc;
++ __u8 drv_ctrl;
++ __u16 pcyls;
++ __u8 pheads;
++ __u16 landz;
++ __u8 sect_per_track;
++ __u8 cksum;
++} drv_param_t;
++
++#define ID_LOG_DRV 0x10
++typedef struct {
++ __u16 blk_size;
++ __u32 nr_blks;
++ drv_param_t drv;
++ __u8 fault_tol;
++ __u8 reserved;
++ __u8 bios_disable;
++} id_log_drv_t;
++
++#define ID_LOG_DRV_EXT 0x18
++typedef struct {
++ __u32 log_drv_id;
++ __u8 log_drv_label[64];
++ __u8 reserved[418];
++} id_log_drv_ext_t;
++
++#define SENSE_LOG_DRV_STAT 0x12
++typedef struct {
++ __u8 status;
++ __u32 fail_map;
++ __u16 read_err[32];
++ __u16 write_err[32];
++ __u8 drv_err_data[256];
++ __u8 drq_timeout[32];
++ __u32 blks_to_recover;
++ __u8 drv_recovering;
++ __u16 remap_cnt[32];
++ __u32 replace_drv_map;
++ __u32 act_spare_map;
++ __u8 spare_stat;
++ __u8 spare_repl_map[32];
++ __u32 repl_ok_map;
++ __u8 media_exch;
++ __u8 cache_fail;
++ __u8 expn_fail;
++ __u8 unit_flags;
++ __u16 big_fail_map[8];
++ __u16 big_remap_map[128];
++ __u16 big_repl_map[8];
++ __u16 big_act_spare_map[8];
++ __u8 big_spar_repl_map[128];
++ __u16 big_repl_ok_map[8];
++ __u8 big_drv_rebuild;
++ __u8 reserved[36];
++} sense_log_drv_stat_t;
++
++#define START_RECOVER 0x13
++
++#define ID_PHYS_DRV 0x15
++typedef struct {
++ __u8 scsi_bus;
++ __u8 scsi_id;
++ __u16 blk_size;
++ __u32 nr_blks;
++ __u32 rsvd_blks;
++ __u8 drv_model[40];
++ __u8 drv_sn[40];
++ __u8 drv_fw[8];
++ __u8 scsi_iq_bits;
++ __u8 compaq_drv_stmp;
++ __u8 last_fail;
++ __u8 phys_drv_flags;
++ __u8 phys_drv_flags1;
++ __u8 scsi_lun;
++ __u8 phys_drv_flags2;
++ __u8 reserved;
++ __u32 spi_speed_rules;
++ __u8 phys_connector[2];
++ __u8 phys_box_on_bus;
++ __u8 phys_bay_in_box;
++} id_phys_drv_t;
++
++#define BLINK_DRV_LEDS 0x16
++typedef struct {
++ __u32 blink_duration;
++ __u32 reserved;
++ __u8 blink[256];
++ __u8 reserved1[248];
++} blink_drv_leds_t;
++
++#define SENSE_BLINK_LEDS 0x17
++typedef struct {
++ __u32 blink_duration;
++ __u32 btime_elap;
++ __u8 blink[256];
++ __u8 reserved1[248];
++} sense_blink_leds_t;
++
++#define IDA_READ 0x20
++#define IDA_WRITE 0x30
++#define IDA_WRITE_MEDIA 0x31
++#define RESET_TO_DIAG 0x40
++#define DIAG_PASS_THRU 0x41
++
++#define SENSE_CONFIG 0x50
++#define SET_CONFIG 0x51
++typedef struct {
++ __u32 cfg_sig;
++ __u16 compat_port;
++ __u8 data_dist_mode;
++ __u8 surf_an_ctrl;
++ __u16 ctlr_phys_drv;
++ __u16 log_unit_phys_drv;
++ __u16 fault_tol_mode;
++ __u8 phys_drv_param[16];
++ drv_param_t drv;
++ __u32 drv_asgn_map;
++ __u16 dist_factor;
++ __u32 spare_asgn_map;
++ __u8 reserved[6];
++ __u16 os;
++ __u8 ctlr_order;
++ __u8 extra_info;
++ __u32 data_offs;
++ __u8 parity_backedout_write_drvs;
++ __u8 parity_dist_mode;
++ __u8 parity_shift_fact;
++ __u8 bios_disable_flag;
++ __u32 blks_on_vol;
++ __u32 blks_per_drv;
++ __u8 scratch[16];
++ __u16 big_drv_map[8];
++ __u16 big_spare_map[8];
++ __u8 ss_source_vol;
++ __u8 mix_drv_cap_range;
++ struct {
++ __u16 big_drv_map[8];
++ __u32 blks_per_drv;
++ __u16 fault_tol_mode;
++ __u16 dist_factor;
++ } MDC_range[4];
++ __u8 reserved1[248];
++} config_t;
++
++#define BYPASS_VOL_STATE 0x52
++#define SS_CREATE_VOL 0x53
++#define CHANGE_CONFIG 0x54
++#define SENSE_ORIG_CONF 0x55
++#define REORDER_LOG_DRV 0x56
++typedef struct {
++ __u8 old_units[32];
++} reorder_log_drv_t;
++
++#define LABEL_LOG_DRV 0x57
++typedef struct {
++ __u8 log_drv_label[64];
++} label_log_drv_t;
++
++#define SS_TO_VOL 0x58
++
++#define SET_SURF_DELAY 0x60
++typedef struct {
++ __u16 delay;
++ __u8 reserved[510];
++} surf_delay_t;
++
++#define SET_OVERHEAT_DELAY 0x61
++typedef struct {
++ __u16 delay;
++} overhead_delay_t;
++
++#define SET_MP_DELAY
++typedef struct {
++ __u16 delay;
++ __u8 reserved[510];
++} mp_delay_t;
++
++#define SENSE_SURF_STATUS 0x70
++
++#define PASSTHRU_A 0x91
++typedef struct {
++ __u8 target;
++ __u8 bus;
++ __u8 lun;
++ __u32 timeout;
++ __u32 flags;
++ __u8 status;
++ __u8 error;
++ __u8 cdb_len;
++ __u8 sense_error;
++ __u8 sense_key;
++ __u32 sense_info;
++ __u8 sense_code;
++ __u8 sense_qual;
++ __u32 residual;
++ __u8 reserved[4];
++ __u8 cdb[12];
++} scsi_param_t;
++
++#define RESUME_BACKGROUND_ACTIVITY 0x99
++#define SENSE_CONTROLLER_PERFORMANCE 0xa8
++#define FLUSH_CACHE 0xc2
++#define COLLECT_BUFFER 0xd2
++#define READ_FLASH_ROM 0xf6
++#define WRITE_FLASH_ROM 0xf7
++#pragma pack()
++
++#endif /* ARRAYCMD_H */
+diff -Nur cpqarrayd-2.2/drivers.orig/block/ida_ioctl.h cpqarrayd-2.2/drivers/block/ida_ioctl.h
+--- cpqarrayd-2.2/drivers.orig/block/ida_ioctl.h 1970-01-01 01:00:00.000000000 +0100
++++ cpqarrayd-2.2/drivers/block/ida_ioctl.h 2005-11-17 16:51:31.000000000 +0100
+@@ -0,0 +1,121 @@
++/*
++ * Disk Array driver for Compaq SMART2 Controllers
++ * Copyright 1998 Compaq Computer Corporation
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
++ * NON INFRINGEMENT. See the GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
++ *
++ * Questions/Comments/Bugfixes to arrays@compaq.com
++ *
++ */
++#ifndef IDA_IOCTL_H
++#define IDA_IOCTL_H
++
++#include "ida_cmd.h"
++#include "cpqarray.h"
++
++#define IDAGETDRVINFO 0x27272828
++#define IDAPASSTHRU 0x28282929
++#define IDAGETCTLRSIG 0x29293030
++#define IDAREVALIDATEVOLS 0x30303131
++#define IDADRIVERVERSION 0x31313232
++#define IDAGETPCIINFO 0x32323333
++#define IDADEREGDISK 0x33333434
++#define IDAREGNEWDISK 0x34343535
++#define IDAGETLOGINFO 0x35353636
++#define IDABIGPASSTHRU 0x36363535
++
++typedef struct _ida_pci_info_struct
++{
++ unsigned char bus;
++ unsigned char dev_fn;
++ __u32 board_id;
++} ida_pci_info_struct;
++
++typedef struct _idaLogvolInfo_struct{
++int LogVolID;
++int num_opens; /* number of opens on the logical volume */
++int num_parts; /* number of partitions configured on logvol */
++} idaLogvolInfo_struct;
++
++/*
++ * Normally, the ioctl determines the logical unit for this command by
++ * the major,minor number of the fd passed to ioctl. If you need to send
++ * a command to a different/nonexistant unit (such as during config), you
++ * can override the normal behavior by setting the unit valid bit. (Normally,
++ * it should be zero) The controller the command is sent to is still
++ * determined by the major number of the open device.
++ */
++
++#define UNITVALID 0x80
++typedef struct {
++ __u8 cmd;
++ __u8 rcode;
++ __u8 unit;
++ __u32 blk;
++ __u16 blk_cnt;
++
++/* currently, sg_cnt is assumed to be 1: only the 0th element of sg is used */
++ struct {
++ void *addr;
++ size_t size;
++ } sg[SG_MAX];
++ int sg_cnt;
++
++ union ctlr_cmds {
++ drv_info_t drv;
++ unsigned char buf[1024];
++
++ id_ctlr_t id_ctlr;
++ drv_param_t drv_param;
++ id_log_drv_t id_log_drv;
++ id_log_drv_ext_t id_log_drv_ext;
++ sense_log_drv_stat_t sense_log_drv_stat;
++ id_phys_drv_t id_phys_drv;
++ blink_drv_leds_t blink_drv_leds;
++ sense_blink_leds_t sense_blink_leds;
++ config_t config;
++ reorder_log_drv_t reorder_log_drv;
++ label_log_drv_t label_log_drv;
++ surf_delay_t surf_delay;
++ overhead_delay_t overhead_delay;
++ mp_delay_t mp_delay;
++ scsi_param_t scsi_param;
++ } c;
++} ida_ioctl_t;
++
++#define IDA_MAX_KMALLOC_SIZE 128000
++
++/* transfer type of the commands */
++#define IDA_XFER_NONE 0x00
++#define IDA_XFER_READ 0x01
++#define IDA_XFER_WRITE 0x02
++#define IDA_XFER_BOTH 0x03
++
++typedef struct {
++ __u8 cmd;
++ __u8 rcode;
++ __u8 unit;
++ __u32 blk;
++ __u16 blk_cnt;
++
++ __u8 xfer_type;
++ __u8 *buff;
++ size_t buff_size;
++ __u32 buff_malloc_size;
++ scsi_param_t *scsi_param; /* used only for PASSTHRU_A */
++
++} ida_big_ioctl_t;
++
++#endif /* IDA_IOCTL_H */
projects / packages / cpqarrayd.git / commitdiff