X11-radeon-dynamic-clocks.patch

   1 --- xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c.ati-radeon-dynamic-clocks-fix    2005-04-14 14:07:38.000000000 -0400
   2 +++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c  2005-04-14 14:10:50.000000000 -0400
   3 @@ -4512,7 +4512,7 @@
   4
   5      RADEONSave(pScrn);
   6
   7 -    if ((!info->IsSecondary) && info->IsMobility) {
   8 +    if ((!info->IsSecondary)) {
   9          if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) {
  10             RADEONSetDynamicClock(pScrn, 1);
  11          } else {
  12 @@ -7808,6 +7808,34 @@
  13      CARD32 tmp;
  14      switch(mode) {
  15          case 0: /* Turn everything OFF (ForceON to everything)*/
  16 +#if 1
  17 +           /* some chips seem to have problems with the method of
  18 +            * forcing everything on as per below; thus we revert to the old
  19 +            * forceON behavior
  20 +            */
  21 +           if (info->HasCRTC2) {
  22 +               tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
  23 +               OUTPLL(RADEON_SCLK_CNTL, ((tmp & ~RADEON_DYN_STOP_LAT_MASK) |
  24 +                                               RADEON_CP_MAX_DYN_STOP_LAT |
  25 +                                               RADEON_SCLK_FORCEON_MASK));
  26 +
  27 +               if (info->ChipFamily == CHIP_FAMILY_RV200) {
  28 +                   tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL);
  29 +                   OUTPLL(RADEON_SCLK_MORE_CNTL, tmp | RADEON_SCLK_MORE_FORCEON);
  30 +               }
  31 +
  32 +           }
  33 +
  34 +           tmp = INPLL(pScrn, RADEON_MCLK_CNTL);
  35 +           OUTPLL(RADEON_MCLK_CNTL, (tmp |
  36 +                               RADEON_FORCEON_MCLKA |
  37 +                               RADEON_FORCEON_MCLKB |
  38 +                               RADEON_FORCEON_YCLKA |
  39 +                               RADEON_FORCEON_YCLKB |
  40 +                               RADEON_FORCEON_MC |
  41 +                               RADEON_FORCEON_AIC));
  42 +
  43 +#else
  44              if ( !info->HasCRTC2 ) {
  45                  tmp = INPLL(pScrn, RADEON_SCLK_CNTL);
  46                  tmp |= (RADEON_SCLK_FORCE_CP   | RADEON_SCLK_FORCE_HDP |
  47 @@ -7945,6 +7973,7 @@
  48                          RADEON_PIXCLK_DAC_ALWAYS_ONb);
  49                  OUTPLL(RADEON_VCLK_ECP_CNTL, tmp);
  50             }
  51 +#endif
  52             xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Dynamic Clock Scaling Disabled\n");
  53              break;
  54          case 1: