1 diff --git a/docs/news.html b/docs/news.html
2 index eea6cd6..70b38c6 100644
9 +<h2>July 31, 2011</h2>
12 +<a href="relnotes-7.11.html">Mesa 7.11</a> is released. This is a new
13 +release with many new features.
16 <h2>June 13, 2011</h2>
19 diff --git a/docs/relnotes-7.11.html b/docs/relnotes-7.11.html
20 index 79776d3..52033cf 100644
21 --- a/docs/relnotes-7.11.html
22 +++ b/docs/relnotes-7.11.html
23 @@ -30,7 +30,12 @@ for DRI hardware acceleration.
25 <h2>MD5 checksums</h2>
28 +fa2c7068503133fb2453244cda11cb2a MesaLib-7.11.tar.gz
29 +ff03aca82d0560009a076a87c888cf13 MesaLib-7.11.tar.bz2
30 +ede1ac0976f6f05df586093fc17d63ed MesaLib-7.11.zip
31 +b4fb81a47c5caedaefad49af7702c23d MesaGLUT-7.11.tar.gz
32 +77a9a0bbd7f8bca882aa5709b88cb071 MesaGLUT-7.11.tar.bz2
33 +c19ef0c6eb61188c96ed4ccedd70717c MesaGLUT-7.11.zip
37 diff --git a/src/gallium/drivers/i915/i915_state_dynamic.c b/src/gallium/drivers/i915/i915_state_dynamic.c
38 index 204cee6..1a21433 100644
39 --- a/src/gallium/drivers/i915/i915_state_dynamic.c
40 +++ b/src/gallium/drivers/i915/i915_state_dynamic.c
41 @@ -268,8 +268,8 @@ static void upload_SCISSOR_RECT(struct i915_context *i915)
43 unsigned x1 = i915->scissor.minx;
44 unsigned y1 = i915->scissor.miny;
45 - unsigned x2 = i915->scissor.maxx;
46 - unsigned y2 = i915->scissor.maxy;
47 + unsigned x2 = i915->scissor.maxx - 1;
48 + unsigned y2 = i915->scissor.maxy - 1;
51 sc[0] = _3DSTATE_SCISSOR_RECT_0_CMD;
52 diff --git a/src/gallium/drivers/r300/r300_emit.c b/src/gallium/drivers/r300/r300_emit.c
53 index d214af4..09ce470 100644
54 --- a/src/gallium/drivers/r300/r300_emit.c
55 +++ b/src/gallium/drivers/r300/r300_emit.c
56 @@ -1237,13 +1237,12 @@ validate:
57 r300->rws->cs_add_reloc(r300->cs, r300_resource(index_buffer)->cs_buf,
58 r300_resource(index_buffer)->domain, 0);
60 - /* Now do the validation. */
61 + /* Now do the validation (flush is called inside cs_validate on failure). */
62 if (!r300->rws->cs_validate(r300->cs)) {
63 /* Ooops, an infinite loop, give up. */
67 - r300_flush(&r300->context, RADEON_FLUSH_ASYNC, NULL);
71 diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
72 index 0139de1..1dcc7e1 100644
73 --- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
74 +++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
75 @@ -115,6 +115,7 @@ static void radeon_cs_context_cleanup(struct radeon_cs_context *csc)
79 + csc->validated_crelocs = 0;
80 csc->chunks[0].length_dw = 0;
81 csc->chunks[1].length_dw = 0;
83 @@ -307,9 +308,37 @@ static void radeon_drm_cs_add_reloc(struct radeon_winsys_cs *rcs,
84 static boolean radeon_drm_cs_validate(struct radeon_winsys_cs *rcs)
86 struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
88 + cs->csc->used_gart < cs->ws->gart_size * 0.8 &&
89 + cs->csc->used_vram < cs->ws->vram_size * 0.8;
91 - return cs->csc->used_gart < cs->ws->gart_size * 0.8 &&
92 - cs->csc->used_vram < cs->ws->vram_size * 0.8;
94 + cs->csc->validated_crelocs = cs->csc->crelocs;
96 + /* Remove lately-added relocations. The validation failed with them
97 + * and the CS is about to be flushed because of that. Keep only
98 + * the already-validated relocations. */
101 + for (i = cs->csc->validated_crelocs; i < cs->csc->crelocs; i++) {
102 + p_atomic_dec(&cs->csc->relocs_bo[i]->num_cs_references);
103 + radeon_bo_reference(&cs->csc->relocs_bo[i], NULL);
105 + cs->csc->crelocs = cs->csc->validated_crelocs;
107 + /* Flush if there are any relocs. Clean up otherwise. */
108 + if (cs->csc->crelocs) {
109 + cs->flush_cs(cs->flush_data, RADEON_FLUSH_ASYNC);
111 + radeon_cs_context_cleanup(cs->csc);
113 + assert(cs->base.cdw == 0);
114 + if (cs->base.cdw != 0) {
115 + fprintf(stderr, "radeon: Unexpected error in %s.\n", __func__);
122 static void radeon_drm_cs_write_reloc(struct radeon_winsys_cs *rcs,
123 diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.h b/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
124 index 339beed..fc51f45 100644
125 --- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
126 +++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
127 @@ -41,6 +41,7 @@ struct radeon_cs_context {
131 + unsigned validated_crelocs;
132 struct radeon_bo **relocs_bo;
133 struct drm_radeon_cs_reloc *relocs;
135 diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h b/src/gallium/winsys/radeon/drm/radeon_winsys.h
136 index 3a64e4a..41c26c6 100644
137 --- a/src/gallium/winsys/radeon/drm/radeon_winsys.h
138 +++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h
139 @@ -271,7 +271,9 @@ struct radeon_winsys {
142 * Return TRUE if there is enough memory in VRAM and GTT for the relocs
144 + * added so far. If the validation fails, all the relocations which have
145 + * been added since the last call of cs_validate will be removed and
146 + * the CS will be flushed (provided there are still any relocations).
148 * \param cs A command stream to validate.
150 diff --git a/src/glx/drisw_glx.c b/src/glx/drisw_glx.c
151 index 07d4955..a57b327 100644
152 --- a/src/glx/drisw_glx.c
153 +++ b/src/glx/drisw_glx.c
154 @@ -100,6 +100,13 @@ XCreateDrawable(struct drisw_drawable * pdp,
156 0); /* bytes_per_line */
159 + * swrast does not handle 24-bit depth with 24 bpp, so let X do the
160 + * the conversion for us.
162 + if (pdp->ximage->bits_per_pixel == 24)
163 + pdp->ximage->bits_per_pixel = 32;
168 diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_dataflow.c b/src/mesa/drivers/dri/r300/compiler/radeon_dataflow.c
169 index b0deb75..a8decac 100644
170 --- a/src/mesa/drivers/dri/r300/compiler/radeon_dataflow.c
171 +++ b/src/mesa/drivers/dri/r300/compiler/radeon_dataflow.c
172 @@ -687,7 +687,7 @@ static void get_readers_for_single_write(
173 struct rc_instruction * tmp;
174 unsigned int branch_depth = 0;
175 struct rc_instruction * endloop = NULL;
176 - unsigned int abort_on_read_at_endloop;
177 + unsigned int abort_on_read_at_endloop = 0;
178 struct get_readers_callback_data * d = userdata;
180 d->ReaderData->Writer = writer;
181 diff --git a/src/mesa/drivers/dri/r300/compiler/radeon_optimize.c b/src/mesa/drivers/dri/r300/compiler/radeon_optimize.c
182 index ac73608..39dcb21 100644
183 --- a/src/mesa/drivers/dri/r300/compiler/radeon_optimize.c
184 +++ b/src/mesa/drivers/dri/r300/compiler/radeon_optimize.c
185 @@ -560,32 +560,30 @@ static int peephole_add_presub_add(
186 struct radeon_compiler * c,
187 struct rc_instruction * inst_add)
189 - struct rc_src_register * src0 = NULL;
190 - struct rc_src_register * src1 = NULL;
193 - if (!is_presub_candidate(c, inst_add))
195 + unsigned dstmask = inst_add->U.I.DstReg.WriteMask;
196 + unsigned src0_neg = inst_add->U.I.SrcReg[0].Negate & dstmask;
197 + unsigned src1_neg = inst_add->U.I.SrcReg[1].Negate & dstmask;
199 if (inst_add->U.I.SrcReg[0].Swizzle != inst_add->U.I.SrcReg[1].Swizzle)
202 - /* src0 and src1 can't have absolute values only one can be negative and they must be all negative or all positive. */
203 - for (i = 0; i < 2; i++) {
204 - if (inst_add->U.I.SrcReg[i].Abs)
206 - if ((inst_add->U.I.SrcReg[i].Negate
207 - & inst_add->U.I.DstReg.WriteMask) ==
208 - inst_add->U.I.DstReg.WriteMask) {
209 - src0 = &inst_add->U.I.SrcReg[i];
210 - } else if (!src1) {
211 - src1 = &inst_add->U.I.SrcReg[i];
213 - src0 = &inst_add->U.I.SrcReg[i];
216 + /* src0 and src1 can't have absolute values */
217 + if (inst_add->U.I.SrcReg[0].Abs || inst_add->U.I.SrcReg[1].Abs)
220 + /* presub_replace_add() assumes only one is negative */
221 + if (inst_add->U.I.SrcReg[0].Negate && inst_add->U.I.SrcReg[1].Negate)
224 + /* if src0 is negative, at least all bits of dstmask have to be set */
225 + if (inst_add->U.I.SrcReg[0].Negate && src0_neg != dstmask)
229 + /* if src1 is negative, at least all bits of dstmask have to be set */
230 + if (inst_add->U.I.SrcReg[1].Negate && src1_neg != dstmask)
233 + if (!is_presub_candidate(c, inst_add))
236 if (presub_helper(c, inst_add, RC_PRESUB_ADD, presub_replace_add)) {
237 @@ -618,7 +616,7 @@ static void presub_replace_inv(
238 * of the add instruction must have the constatnt 1 swizzle. This function
239 * does not check const registers to see if their value is 1.0, so it should
240 * be called after the constant_folding optimization.
243 * 0 if the ADD instruction is still part of the program.
244 * 1 if the ADD instruction is no longer part of the program.
246 diff --git a/src/mesa/vbo/vbo_exec_array.c b/src/mesa/vbo/vbo_exec_array.c
247 index 7959337..5903ae23 100644
248 --- a/src/mesa/vbo/vbo_exec_array.c
249 +++ b/src/mesa/vbo/vbo_exec_array.c
250 @@ -909,11 +909,10 @@ vbo_exec_DrawRangeElementsBaseVertex(GLenum mode,
252 _mesa_print_arrays(ctx);
255 /* 'end' was out of bounds, but now let's check the actual array
256 * indexes to see if any of them are out of bounds.
260 GLuint max = _mesa_max_buffer_index(ctx, count, type, indices,
261 ctx->Array.ElementArrayBufferObj);
262 if (max >= ctx->Array.ArrayObj->_MaxElement) {
263 @@ -934,7 +933,6 @@ vbo_exec_DrawRangeElementsBaseVertex(GLenum mode,
269 /* Set 'end' to the max possible legal value */
270 assert(ctx->Array.ArrayObj->_MaxElement >= 1);