2 ===================================================================
3 --- configure (.../tags/gcc_4_5_2_release) (wersja 170084)
4 +++ configure (.../branches/gcc-4_5-branch) (wersja 170084)
11 ppllibs=" -lppl_c -lppl -lgmpxx"
15 if test "x$with_ppl" != "xno" -a "${ENABLE_PPL_CHECK}" = "yes"; then
16 saved_CFLAGS="$CFLAGS"
17 CFLAGS="$CFLAGS $pplinc $gmpinc"
18 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for version $ppl_major_version.$ppl_minor_version of PPL" >&5
19 -$as_echo_n "checking for version $ppl_major_version.$ppl_minor_version of PPL... " >&6; }
20 + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for version 0.10 (or later revision) of PPL" >&5
21 +$as_echo_n "checking for version 0.10 (or later revision) of PPL... " >&6; }
22 cat confdefs.h - <<_ACEOF >conftest.$ac_ext
29 - #if PPL_VERSION_MAJOR != $ppl_major_version || PPL_VERSION_MINOR != $ppl_minor_version
30 + #if PPL_VERSION_MAJOR != 0 || PPL_VERSION_MINOR < 10
34 Index: libgomp/configure.tgt
35 ===================================================================
36 --- libgomp/configure.tgt (.../tags/gcc_4_5_2_release) (wersja 170084)
37 +++ libgomp/configure.tgt (.../branches/gcc-4_5-branch) (wersja 170084)
39 config_path="bsd posix"
43 + # Need to link with -lpthread so libgomp.so is self-contained.
44 + XLDFLAGS="${XLDFLAGS} -lpthread"
49 Index: libgomp/ChangeLog
50 ===================================================================
51 --- libgomp/ChangeLog (.../tags/gcc_4_5_2_release) (wersja 170084)
52 +++ libgomp/ChangeLog (.../branches/gcc-4_5-branch) (wersja 170084)
54 +2011-01-16 Jakub Jelinek <jakub@redhat.com>
56 + Backport from mainline
57 + 2010-12-14 Jakub Jelinek <jakub@redhat.com>
60 + * libgomp.fortran/allocatable6.f90: New test.
62 +2010-12-17 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
64 + Backport from mainline:
65 + 2010-12-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
67 + * configure.tgt (mips-sgi-irix6*): Add -lpthread to XLDFLAGS.
69 2010-12-16 Release Manager
72 Index: libgomp/testsuite/libgomp.fortran/allocatable6.f90
73 ===================================================================
74 --- libgomp/testsuite/libgomp.fortran/allocatable6.f90 (.../tags/gcc_4_5_2_release) (wersja 0)
75 +++ libgomp/testsuite/libgomp.fortran/allocatable6.f90 (.../branches/gcc-4_5-branch) (wersja 170084)
81 + subroutine sub (a, b, c, d, n)
83 + integer, allocatable :: a(:), b(:), c(:), d(:)
87 + integer, allocatable :: a(:), b(:), c(:), d(:)
89 + allocate (a(50), b(50), c(50), d(50))
91 + a(i) = 2 + modulo (i, 7)
92 + b(i) = 179 - modulo (i, 11)
96 + call sub (a, b, c, d, 50)
101 + else if (i .gt. 1 .and. i .lt. 9) then
104 + if (c(i) .ne. j) call abort
105 + j = 179 - modulo (i, 11)
106 + if (i .gt. 1 .and. i .lt. 9) j = i
107 + if (d(i) .ne. j) call abort
109 + deallocate (a, b, c, d)
112 +subroutine sub (a, b, c, d, n)
114 + integer, allocatable :: a(:), b(:), c(:), d(:)
115 +!$omp parallel do shared(a, b) reduction(+:c) reduction(min:d)
117 + c(a(i)) = c(a(i)) + 1
118 + d(i) = min(d(i), b(i))
119 + d(a(i)) = min(d(a(i)), a(i))
122 Index: gcc/tree-vrp.c
123 ===================================================================
124 --- gcc/tree-vrp.c (.../tags/gcc_4_5_2_release) (wersja 170084)
125 +++ gcc/tree-vrp.c (.../branches/gcc-4_5-branch) (wersja 170084)
126 @@ -7290,6 +7290,7 @@
128 prop_value_t *single_val_range;
129 bool do_value_subst_p;
130 + unsigned num = num_ssa_names;
134 @@ -7301,10 +7302,10 @@
135 /* We may have ended with ranges that have exactly one value. Those
136 values can be substituted as any other const propagated
137 value using substitute_and_fold. */
138 - single_val_range = XCNEWVEC (prop_value_t, num_ssa_names);
139 + single_val_range = XCNEWVEC (prop_value_t, num);
141 do_value_subst_p = false;
142 - for (i = 0; i < num_ssa_names; i++)
143 + for (i = 0; i < num; i++)
145 && vr_value[i]->type == VR_RANGE
146 && vr_value[i]->min == vr_value[i]->max
147 @@ -7332,7 +7333,7 @@
148 identify_jump_threads ();
150 /* Free allocated memory. */
151 - for (i = 0; i < num_ssa_names; i++)
152 + for (i = 0; i < num; i++)
155 BITMAP_FREE (vr_value[i]->equiv);
156 Index: gcc/doc/extend.texi
157 ===================================================================
158 --- gcc/doc/extend.texi (.../tags/gcc_4_5_2_release) (wersja 170084)
159 +++ gcc/doc/extend.texi (.../branches/gcc-4_5-branch) (wersja 170084)
160 @@ -11873,6 +11873,12 @@
161 vector float vec_div (vector float, vector float);
162 vector double vec_div (vector double, vector double);
163 vector double vec_floor (vector double);
164 +vector double vec_ld (int, const vector double *);
165 +vector double vec_ld (int, const double *);
166 +vector double vec_ldl (int, const vector double *);
167 +vector double vec_ldl (int, const double *);
168 +vector unsigned char vec_lvsl (int, const volatile double *);
169 +vector unsigned char vec_lvsr (int, const volatile double *);
170 vector double vec_madd (vector double, vector double, vector double);
171 vector double vec_max (vector double, vector double);
172 vector double vec_min (vector double, vector double);
173 @@ -11899,6 +11905,8 @@
174 vector double vec_sub (vector double, vector double);
175 vector float vec_sqrt (vector float);
176 vector double vec_sqrt (vector double);
177 +void vec_st (vector double, int, vector double *);
178 +void vec_st (vector double, int, double *);
179 vector double vec_trunc (vector double);
180 vector double vec_xor (vector double, vector double);
181 vector double vec_xor (vector double, vector bool long);
182 @@ -11927,8 +11935,66 @@
183 int vec_any_nle (vector double, vector double);
184 int vec_any_nlt (vector double, vector double);
185 int vec_any_numeric (vector double);
187 +vector double vec_vsx_ld (int, const vector double *);
188 +vector double vec_vsx_ld (int, const double *);
189 +vector float vec_vsx_ld (int, const vector float *);
190 +vector float vec_vsx_ld (int, const float *);
191 +vector bool int vec_vsx_ld (int, const vector bool int *);
192 +vector signed int vec_vsx_ld (int, const vector signed int *);
193 +vector signed int vec_vsx_ld (int, const int *);
194 +vector signed int vec_vsx_ld (int, const long *);
195 +vector unsigned int vec_vsx_ld (int, const vector unsigned int *);
196 +vector unsigned int vec_vsx_ld (int, const unsigned int *);
197 +vector unsigned int vec_vsx_ld (int, const unsigned long *);
198 +vector bool short vec_vsx_ld (int, const vector bool short *);
199 +vector pixel vec_vsx_ld (int, const vector pixel *);
200 +vector signed short vec_vsx_ld (int, const vector signed short *);
201 +vector signed short vec_vsx_ld (int, const short *);
202 +vector unsigned short vec_vsx_ld (int, const vector unsigned short *);
203 +vector unsigned short vec_vsx_ld (int, const unsigned short *);
204 +vector bool char vec_vsx_ld (int, const vector bool char *);
205 +vector signed char vec_vsx_ld (int, const vector signed char *);
206 +vector signed char vec_vsx_ld (int, const signed char *);
207 +vector unsigned char vec_vsx_ld (int, const vector unsigned char *);
208 +vector unsigned char vec_vsx_ld (int, const unsigned char *);
210 +void vec_vsx_st (vector double, int, vector double *);
211 +void vec_vsx_st (vector double, int, double *);
212 +void vec_vsx_st (vector float, int, vector float *);
213 +void vec_vsx_st (vector float, int, float *);
214 +void vec_vsx_st (vector signed int, int, vector signed int *);
215 +void vec_vsx_st (vector signed int, int, int *);
216 +void vec_vsx_st (vector unsigned int, int, vector unsigned int *);
217 +void vec_vsx_st (vector unsigned int, int, unsigned int *);
218 +void vec_vsx_st (vector bool int, int, vector bool int *);
219 +void vec_vsx_st (vector bool int, int, unsigned int *);
220 +void vec_vsx_st (vector bool int, int, int *);
221 +void vec_vsx_st (vector signed short, int, vector signed short *);
222 +void vec_vsx_st (vector signed short, int, short *);
223 +void vec_vsx_st (vector unsigned short, int, vector unsigned short *);
224 +void vec_vsx_st (vector unsigned short, int, unsigned short *);
225 +void vec_vsx_st (vector bool short, int, vector bool short *);
226 +void vec_vsx_st (vector bool short, int, unsigned short *);
227 +void vec_vsx_st (vector pixel, int, vector pixel *);
228 +void vec_vsx_st (vector pixel, int, unsigned short *);
229 +void vec_vsx_st (vector pixel, int, short *);
230 +void vec_vsx_st (vector bool short, int, short *);
231 +void vec_vsx_st (vector signed char, int, vector signed char *);
232 +void vec_vsx_st (vector signed char, int, signed char *);
233 +void vec_vsx_st (vector unsigned char, int, vector unsigned char *);
234 +void vec_vsx_st (vector unsigned char, int, unsigned char *);
235 +void vec_vsx_st (vector bool char, int, vector bool char *);
236 +void vec_vsx_st (vector bool char, int, unsigned char *);
237 +void vec_vsx_st (vector bool char, int, signed char *);
240 +Note that the @samp{vec_ld} and @samp{vec_st} builtins will always
241 +generate the Altivec @samp{LVX} and @samp{STVX} instructions even
242 +if the VSX instruction set is available. The @samp{vec_vsx_ld} and
243 +@samp{vec_vsx_st} builtins will always generate the VSX @samp{LXVD2X},
244 +@samp{LXVW4X}, @samp{STXVD2X}, and @samp{STXVW4X} instructions.
246 GCC provides a few other builtins on Powerpc to access certain instructions:
248 float __builtin_recipdivf (float, float);
249 @@ -12799,7 +12865,7 @@
250 be a @var{constant-expression}, as defined in 5.19.2 of the ANSI/ISO C++
253 -See @uref{http://people.redhat.com/drepper/tls.pdf,
254 +See @uref{http://www.akkadia.org/drepper/tls.pdf,
255 ELF Handling For Thread-Local Storage} for a detailed explanation of
256 the four thread-local storage addressing models, and how the run-time
257 is expected to function.
258 Index: gcc/doc/install.texi
259 ===================================================================
260 --- gcc/doc/install.texi (.../tags/gcc_4_5_2_release) (wersja 170084)
261 +++ gcc/doc/install.texi (.../branches/gcc-4_5-branch) (wersja 170084)
263 @settitle Installing GCC: GNU Free Documentation License
266 -@c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
267 -@c 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
268 -@c 2010 Free Software Foundation, Inc.
269 +@c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997,
270 +@c 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
271 +@c 2009, 2010, 2011 Free Software Foundation, Inc.
272 @c *** Converted to texinfo by Dean Wakerley, dean@wakerley.com
274 @c IMPORTANT: whenever you modify this file, run `install.texi2html' to
276 @c Part 2 Summary Description and Copyright
278 Copyright @copyright{} 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997,
279 -1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
280 -2008 Free Software Foundation, Inc.
281 +1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008,
282 +2009, 2010, 2011 Free Software Foundation, Inc.
284 Permission is granted to copy, distribute and/or modify this document
285 under the terms of the GNU Free Documentation License, Version 1.2 or
286 @@ -2784,10 +2784,6 @@
290 -Motorola 68HC11/68HC12---@uref{http://www.gnu-m68hc11.org,,GNU
291 -Development Tools for the Motorola 68HC11/68HC12}.
294 @uref{http://www.sco.com/skunkware/devtools/index.html#gcc,,SCO
295 OpenServer/Unixware}.
297 @@ -3311,23 +3307,8 @@
298 @heading @anchor{hppa-hp-hpux10}hppa*-hp-hpux10
300 For hpux10.20, we @emph{highly} recommend you pick up the latest sed patch
301 -@code{PHCO_19798} from HP@. HP has two sites which provide patches free of
303 +@code{PHCO_19798} from HP@.
308 -<a href="http://us.itrc.hp.com/service/home/home.do">US, Canada, Asia-Pacific, and
312 -@uref{http://us.itrc.hp.com/service/home/home.do,,} US, Canada, Asia-Pacific,
316 -@uref{http://europe.itrc.hp.com/service/home/home.do,,} Europe.
319 The C++ ABI has changed incompatibly in GCC 4.0. COMDAT subspaces are
320 used for one-only code and data. This resolves many of the previous
321 problems in using C++ on this target. However, the ABI is not compatible
322 Index: gcc/tree-ssa-loop-im.c
323 ===================================================================
324 --- gcc/tree-ssa-loop-im.c (.../tags/gcc_4_5_2_release) (wersja 170084)
325 +++ gcc/tree-ssa-loop-im.c (.../branches/gcc-4_5-branch) (wersja 170084)
326 @@ -2139,7 +2139,7 @@
329 for (i = 0; VEC_iterate (edge, exits, i, ex); i++)
330 - if (ex->flags & EDGE_ABNORMAL)
331 + if (ex->flags & (EDGE_ABNORMAL | EDGE_EH))
335 Index: gcc/tree-loop-distribution.c
336 ===================================================================
337 --- gcc/tree-loop-distribution.c (.../tags/gcc_4_5_2_release) (wersja 170084)
338 +++ gcc/tree-loop-distribution.c (.../branches/gcc-4_5-branch) (wersja 170084)
341 /* Generate a call to memset. Return true when the operation succeeded. */
345 generate_memset_zero (gimple stmt, tree op0, tree nb_iter,
346 gimple_stmt_iterator bsi)
348 @@ -265,45 +265,27 @@
352 - if (!dr_analyze_innermost (dr))
354 + res = dr_analyze_innermost (dr);
355 + gcc_assert (res && stride_of_unit_type_p (DR_STEP (dr), TREE_TYPE (op0)));
357 - /* Test for a positive stride, iterating over every element. */
358 - if (integer_zerop (size_binop (MINUS_EXPR,
359 - fold_convert (sizetype, DR_STEP (dr)),
360 - TYPE_SIZE_UNIT (TREE_TYPE (op0)))))
362 - addr_base = fold_convert_loc (loc, sizetype,
363 - size_binop_loc (loc, PLUS_EXPR,
366 - addr_base = fold_build2_loc (loc, POINTER_PLUS_EXPR,
367 - TREE_TYPE (DR_BASE_ADDRESS (dr)),
368 - DR_BASE_ADDRESS (dr), addr_base);
369 + nb_bytes = build_size_arg_loc (loc, nb_iter, op0, &stmt_list);
370 + addr_base = size_binop_loc (loc, PLUS_EXPR, DR_OFFSET (dr), DR_INIT (dr));
371 + addr_base = fold_convert_loc (loc, sizetype, addr_base);
373 - nb_bytes = build_size_arg_loc (loc, nb_iter, op0, &stmt_list);
376 /* Test for a negative stride, iterating over every element. */
377 - else if (integer_zerop (size_binop (PLUS_EXPR,
378 - TYPE_SIZE_UNIT (TREE_TYPE (op0)),
379 - fold_convert (sizetype, DR_STEP (dr)))))
380 + if (integer_zerop (size_binop (PLUS_EXPR,
381 + TYPE_SIZE_UNIT (TREE_TYPE (op0)),
382 + fold_convert (sizetype, DR_STEP (dr)))))
384 - nb_bytes = build_size_arg_loc (loc, nb_iter, op0, &stmt_list);
386 - addr_base = size_binop_loc (loc, PLUS_EXPR, DR_OFFSET (dr), DR_INIT (dr));
387 - addr_base = fold_convert_loc (loc, sizetype, addr_base);
388 addr_base = size_binop_loc (loc, MINUS_EXPR, addr_base,
389 fold_convert_loc (loc, sizetype, nb_bytes));
390 addr_base = size_binop_loc (loc, PLUS_EXPR, addr_base,
391 TYPE_SIZE_UNIT (TREE_TYPE (op0)));
392 - addr_base = fold_build2_loc (loc, POINTER_PLUS_EXPR,
393 - TREE_TYPE (DR_BASE_ADDRESS (dr)),
394 - DR_BASE_ADDRESS (dr), addr_base);
399 + addr_base = fold_build2_loc (loc, POINTER_PLUS_EXPR,
400 + TREE_TYPE (DR_BASE_ADDRESS (dr)),
401 + DR_BASE_ADDRESS (dr), addr_base);
402 mem = force_gimple_operand (addr_base, &stmts, true, NULL);
403 gimple_seq_add_seq (&stmt_list, stmts);
405 @@ -311,14 +293,11 @@
406 fn_call = gimple_build_call (fn, 3, mem, integer_zero_node, nb_bytes);
407 gimple_seq_add_stmt (&stmt_list, fn_call);
408 gsi_insert_seq_after (&bsi, stmt_list, GSI_CONTINUE_LINKING);
411 if (dump_file && (dump_flags & TDF_DETAILS))
412 fprintf (dump_file, "generated memset zero\n");
419 /* Tries to generate a builtin function for the instructions of LOOP
425 gimple_stmt_iterator bsi;
426 tree nb_iter = number_of_exit_cond_executions (loop);
428 @@ -368,26 +346,17 @@
433 + if (!stmt_with_adjacent_zero_store_dr_p (write))
436 - op0 = gimple_assign_lhs (write);
437 - op1 = gimple_assign_rhs1 (write);
439 - if (!(TREE_CODE (op0) == ARRAY_REF
440 - || TREE_CODE (op0) == INDIRECT_REF))
443 /* The new statements will be placed before LOOP. */
444 bsi = gsi_last_bb (loop_preheader_edge (loop)->src);
445 + generate_memset_zero (write, gimple_assign_lhs (write), nb_iter, bsi);
448 - if (gimple_assign_rhs_code (write) == INTEGER_CST
449 - && (integer_zerop (op1) || real_zerop (op1)))
450 - res = generate_memset_zero (write, op0, nb_iter, bsi);
452 /* If this is the last partition for which we generate code, we have
453 to destroy the loop. */
454 - if (res && !copy_p)
457 unsigned nbbs = loop->num_nodes;
458 edge exit = single_exit (loop);
460 static void rdg_flag_vertex_and_dependent (struct graph *, int, bitmap, bitmap,
463 -/* Flag all the uses of U. */
466 -rdg_flag_all_uses (struct graph *rdg, int u, bitmap partition, bitmap loops,
467 - bitmap processed, bool *part_has_writes)
469 - struct graph_edge *e;
471 - for (e = rdg->vertices[u].succ; e; e = e->succ_next)
472 - if (!bitmap_bit_p (processed, e->dest))
474 - rdg_flag_vertex_and_dependent (rdg, e->dest, partition, loops,
475 - processed, part_has_writes);
476 - rdg_flag_all_uses (rdg, e->dest, partition, loops, processed,
481 /* Flag the uses of U stopping following the information from
482 upstream_mem_writes. */
484 @@ -720,68 +671,13 @@
488 -/* Flag all the nodes of RDG containing memory accesses that could
489 - potentially belong to arrays already accessed in the current
493 -rdg_flag_similar_memory_accesses (struct graph *rdg, bitmap partition,
494 - bitmap loops, bitmap processed,
495 - VEC (int, heap) **other_stores)
500 - bitmap_iterator ii;
501 - struct graph_edge *e;
503 - EXECUTE_IF_SET_IN_BITMAP (partition, 0, i, ii)
504 - if (RDG_MEM_WRITE_STMT (rdg, i)
505 - || RDG_MEM_READS_STMT (rdg, i))
507 - for (j = 0; j < rdg->n_vertices; j++)
508 - if (!bitmap_bit_p (processed, j)
509 - && (RDG_MEM_WRITE_STMT (rdg, j)
510 - || RDG_MEM_READS_STMT (rdg, j))
511 - && rdg_has_similar_memory_accesses (rdg, i, j))
513 - /* Flag first the node J itself, and all the nodes that
514 - are needed to compute J. */
515 - rdg_flag_vertex_and_dependent (rdg, j, partition, loops,
518 - /* When J is a read, we want to coalesce in the same
519 - PARTITION all the nodes that are using J: this is
520 - needed for better cache locality. */
521 - rdg_flag_all_uses (rdg, j, partition, loops, processed, &foo);
523 - /* Remove from OTHER_STORES the vertex that we flagged. */
524 - if (RDG_MEM_WRITE_STMT (rdg, j))
525 - for (k = 0; VEC_iterate (int, *other_stores, k, kk); k++)
528 - VEC_unordered_remove (int, *other_stores, k);
533 - /* If the node I has two uses, then keep these together in the
535 - for (n = 0, e = rdg->vertices[i].succ; e; e = e->succ_next, n++);
538 - rdg_flag_all_uses (rdg, i, partition, loops, processed, &foo);
542 /* Returns a bitmap in which all the statements needed for computing
543 the strongly connected component C of the RDG are flagged, also
544 including the loop exit conditions. */
547 build_rdg_partition_for_component (struct graph *rdg, rdgc c,
548 - bool *part_has_writes,
549 - VEC (int, heap) **other_stores)
550 + bool *part_has_writes)
553 bitmap partition = BITMAP_ALLOC (NULL);
555 rdg_flag_vertex_and_dependent (rdg, v, partition, loops, processed,
558 - /* Also iterate on the array of stores not in the starting vertices,
559 - and determine those vertices that have some memory affinity with
560 - the current nodes in the component: these are stores to the same
561 - arrays, i.e. we're taking care of cache locality. */
562 - rdg_flag_similar_memory_accesses (rdg, partition, loops, processed,
565 rdg_flag_loop_exits (rdg, loops, partition, processed, part_has_writes);
567 BITMAP_FREE (processed);
569 BITMAP_FREE (saved_components);
572 +/* Returns true when it is possible to generate a builtin pattern for
573 + the PARTITION of RDG. For the moment we detect only the memset
577 +can_generate_builtin (struct graph *rdg, bitmap partition)
580 + bitmap_iterator bi;
583 + int stores_zero = 0;
585 + EXECUTE_IF_SET_IN_BITMAP (partition, 0, i, bi)
586 + if (RDG_MEM_READS_STMT (rdg, i))
588 + else if (RDG_MEM_WRITE_STMT (rdg, i))
591 + if (stmt_with_adjacent_zero_store_dr_p (RDG_STMT (rdg, i)))
595 + return stores_zero == 1 && nb_writes == 1 && nb_reads == 0;
598 +/* Returns true when PARTITION1 and PARTITION2 have similar memory
599 + accesses in RDG. */
602 +similar_memory_accesses (struct graph *rdg, bitmap partition1,
606 + bitmap_iterator bi, bj;
608 + EXECUTE_IF_SET_IN_BITMAP (partition1, 0, i, bi)
609 + if (RDG_MEM_WRITE_STMT (rdg, i)
610 + || RDG_MEM_READS_STMT (rdg, i))
611 + EXECUTE_IF_SET_IN_BITMAP (partition2, 0, j, bj)
612 + if (RDG_MEM_WRITE_STMT (rdg, j)
613 + || RDG_MEM_READS_STMT (rdg, j))
614 + if (rdg_has_similar_memory_accesses (rdg, i, j))
620 +/* Fuse all the partitions from PARTITIONS that contain similar memory
621 + references, i.e., we're taking care of cache locality. This
622 + function does not fuse those partitions that contain patterns that
623 + can be code generated with builtins. */
626 +fuse_partitions_with_similar_memory_accesses (struct graph *rdg,
627 + VEC (bitmap, heap) **partitions)
630 + bitmap partition1, partition2;
632 + for (p1 = 0; VEC_iterate (bitmap, *partitions, p1, partition1); p1++)
633 + if (!can_generate_builtin (rdg, partition1))
634 + for (p2 = 0; VEC_iterate (bitmap, *partitions, p2, partition2); p2++)
636 + && !can_generate_builtin (rdg, partition2)
637 + && similar_memory_accesses (rdg, partition1, partition2))
639 + bitmap_ior_into (partition1, partition2);
640 + VEC_ordered_remove (bitmap, *partitions, p2);
645 /* Aggregate several components into a useful partition that is
646 registered in the PARTITIONS vector. Partitions will be
647 distributed in different loops. */
649 if (bitmap_bit_p (processed, v))
652 - np = build_rdg_partition_for_component (rdg, x, &part_has_writes,
654 + np = build_rdg_partition_for_component (rdg, x, &part_has_writes);
655 bitmap_ior_into (partition, np);
656 bitmap_ior_into (processed, np);
659 VEC_safe_push (bitmap, heap, *partitions, partition);
661 BITMAP_FREE (partition);
663 + fuse_partitions_with_similar_memory_accesses (rdg, partitions);
666 /* Dump to FILE the PARTITIONS. */
668 ===================================================================
669 --- gcc/DATESTAMP (.../tags/gcc_4_5_2_release) (wersja 170084)
670 +++ gcc/DATESTAMP (.../branches/gcc-4_5-branch) (wersja 170084)
675 ===================================================================
676 --- gcc/DEV-PHASE (.../tags/gcc_4_5_2_release) (wersja 170084)
677 +++ gcc/DEV-PHASE (.../branches/gcc-4_5-branch) (wersja 170084)
680 Index: gcc/tree-ssa-sccvn.c
681 ===================================================================
682 --- gcc/tree-ssa-sccvn.c (.../tags/gcc_4_5_2_release) (wersja 170084)
683 +++ gcc/tree-ssa-sccvn.c (.../branches/gcc-4_5-branch) (wersja 170084)
687 static tree *last_vuse_ptr;
688 +static vn_lookup_kind vn_walk_kind;
690 /* Callback for walk_non_aliased_vuses. Adjusts the vn_reference_t VR_
691 with the current VUSE and performs the expression lookup. */
692 @@ -1063,6 +1064,7 @@
693 size2 = TREE_INT_CST_LOW (gimple_call_arg (def_stmt, 2)) * 8;
694 if ((unsigned HOST_WIDE_INT)size2 / 8
695 == TREE_INT_CST_LOW (gimple_call_arg (def_stmt, 2))
697 && operand_equal_p (base, base2, 0)
699 && offset2 + size2 >= offset + maxsize)
700 @@ -1086,7 +1088,8 @@
701 HOST_WIDE_INT offset2, size2, maxsize2;
702 base2 = get_ref_base_and_extent (gimple_assign_lhs (def_stmt),
703 &offset2, &size2, &maxsize2);
704 - if (operand_equal_p (base, base2, 0)
706 + && operand_equal_p (base, base2, 0)
708 && offset2 + size2 >= offset + maxsize)
710 @@ -1101,7 +1104,8 @@
712 /* For aggregate copies translate the reference through them if
713 the copy kills ref. */
714 - else if (gimple_assign_single_p (def_stmt)
715 + else if (vn_walk_kind == VN_WALKREWRITE
716 + && gimple_assign_single_p (def_stmt)
717 && (DECL_P (gimple_assign_rhs1 (def_stmt))
718 || INDIRECT_REF_P (gimple_assign_rhs1 (def_stmt))
719 || handled_component_p (gimple_assign_rhs1 (def_stmt))))
720 @@ -1116,7 +1120,8 @@
721 /* See if the assignment kills REF. */
722 base2 = get_ref_base_and_extent (gimple_assign_lhs (def_stmt),
723 &offset2, &size2, &maxsize2);
724 - if (!operand_equal_p (base, base2, 0)
726 + || !operand_equal_p (base, base2, 0)
728 || offset2 + size2 < offset + maxsize)
730 @@ -1190,7 +1195,7 @@
732 vn_reference_lookup_pieces (tree vuse, alias_set_type set, tree type,
733 VEC (vn_reference_op_s, heap) *operands,
734 - vn_reference_t *vnresult, bool maywalk)
735 + vn_reference_t *vnresult, vn_lookup_kind kind)
737 struct vn_reference_s vr1;
739 @@ -1215,10 +1220,11 @@
740 vn_reference_lookup_1 (&vr1, vnresult);
744 + && kind != VN_NOWALK
748 + vn_walk_kind = kind;
749 if (ao_ref_init_from_vn_reference (&r, set, type, vr1.operands))
751 (vn_reference_t)walk_non_aliased_vuses (&r, vr1.vuse,
752 @@ -1241,7 +1247,7 @@
753 stored in the hashtable if one exists. */
756 -vn_reference_lookup (tree op, tree vuse, bool maywalk,
757 +vn_reference_lookup (tree op, tree vuse, vn_lookup_kind kind,
758 vn_reference_t *vnresult)
760 VEC (vn_reference_op_s, heap) *operands;
761 @@ -1256,12 +1262,13 @@
762 vr1.set = get_alias_set (op);
763 vr1.hashcode = vn_reference_compute_hash (&vr1);
766 + if (kind != VN_NOWALK
769 vn_reference_t wvnresult;
771 ao_ref_init (&r, op);
772 + vn_walk_kind = kind;
774 (vn_reference_t)walk_non_aliased_vuses (&r, vr1.vuse,
775 vn_reference_lookup_2,
776 @@ -1980,14 +1987,14 @@
778 last_vuse = gimple_vuse (stmt);
779 last_vuse_ptr = &last_vuse;
780 - result = vn_reference_lookup (op, gimple_vuse (stmt), true, NULL);
781 + result = vn_reference_lookup (op, gimple_vuse (stmt), VN_WALKREWRITE, NULL);
782 last_vuse_ptr = NULL;
784 /* If we have a VCE, try looking up its operand as it might be stored in
786 if (!result && TREE_CODE (op) == VIEW_CONVERT_EXPR)
787 result = vn_reference_lookup (TREE_OPERAND (op, 0), gimple_vuse (stmt),
789 + VN_WALKREWRITE, NULL);
791 /* We handle type-punning through unions by value-numbering based
792 on offset and size of the access. Be prepared to handle a
793 @@ -2098,7 +2105,7 @@
794 Otherwise, the vdefs for the store are used when inserting into
795 the table, since the store generates a new memory state. */
797 - result = vn_reference_lookup (lhs, gimple_vuse (stmt), false, NULL);
798 + result = vn_reference_lookup (lhs, gimple_vuse (stmt), VN_NOWALK, NULL);
802 Index: gcc/tree-ssa-sccvn.h
803 ===================================================================
804 --- gcc/tree-ssa-sccvn.h (.../tags/gcc_4_5_2_release) (wersja 170084)
805 +++ gcc/tree-ssa-sccvn.h (.../branches/gcc-4_5-branch) (wersja 170084)
806 @@ -185,10 +185,11 @@
807 void copy_reference_ops_from_call (gimple, VEC(vn_reference_op_s, heap) **);
808 bool ao_ref_init_from_vn_reference (ao_ref *, alias_set_type, tree,
809 VEC (vn_reference_op_s, heap) *);
810 +typedef enum { VN_NOWALK, VN_WALK, VN_WALKREWRITE } vn_lookup_kind;
811 tree vn_reference_lookup_pieces (tree, alias_set_type, tree,
812 VEC (vn_reference_op_s, heap) *,
813 - vn_reference_t *, bool);
814 -tree vn_reference_lookup (tree, tree, bool, vn_reference_t *);
815 + vn_reference_t *, vn_lookup_kind);
816 +tree vn_reference_lookup (tree, tree, vn_lookup_kind, vn_reference_t *);
817 vn_reference_t vn_reference_insert (tree, tree, tree);
818 vn_reference_t vn_reference_insert_pieces (tree, alias_set_type, tree,
819 VEC (vn_reference_op_s, heap) *,
821 ===================================================================
822 --- gcc/ChangeLog (.../tags/gcc_4_5_2_release) (wersja 170084)
823 +++ gcc/ChangeLog (.../branches/gcc-4_5-branch) (wersja 170084)
825 +2011-02-11 Bernd Schmidt <bernds@codesourcery.com>
827 + PR rtl-optimization/47166
828 + * reload1.c (emit_reload_insns): Disable the spill_reg_store
829 + mechanism for PRE_MODIFY and POST_MODIFY.
830 + (inc_for_reload): For PRE_MODIFY, return the insn that sets the
833 +2011-02-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
835 + Backport from mainline:
836 + 2011-02-07 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
838 + * config.gcc (hppa[12]*-*-hpux11*): Don't set extra_parts.
839 + * config/pa/stublib.c (pthread_default_stacksize_np, pthread_mutex_lock,
840 + pthread_mutex_unlock): Remove.
841 + * config/pa/t-pa-hpux11: Remove rules to build pthread stubs.
842 + * config/pa/t-pa64: Likewise.
843 + * config/pa/pa64-hpux.h (LIB_SPEC): In static links, link against
844 + shared libc if not linking against libpthread.
845 + * config/pa/pa-hpux11.h (LIB_SPEC): Likewise.
847 +2011-02-03 Michael Meissner <meissner@linux.vnet.ibm.com>
849 + Backport from mainline:
850 + 2011-02-02 Michael Meissner <meissner@linux.vnet.ibm.com>
853 + * doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):
854 + Document using vector double with the load/store builtins, and
855 + that the load/store builtins always use Altivec instructions.
857 + * config/rs6000/vector.md (vector_altivec_load_<mode>): New insns
858 + to use altivec memory instructions, even on VSX.
859 + (vector_altivec_store_<mode>): Ditto.
861 + * config/rs6000/rs6000-protos.h (rs6000_address_for_altivec): New
864 + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
865 + V2DF, V2DI support to load/store overloaded builtins.
867 + * config/rs6000/rs6000-builtin.def (ALTIVEC_BUILTIN_*): Add
868 + altivec load/store builtins for V2DF/V2DI types.
870 + * config/rs6000/rs6000.c (rs6000_option_override_internal): Don't
871 + set avoid indexed addresses on power6 if -maltivec.
872 + (altivec_expand_ld_builtin): Add V2DF, V2DI support, use
873 + vector_altivec_load/vector_altivec_store builtins.
874 + (altivec_expand_st_builtin): Ditto.
875 + (altivec_expand_builtin): Add VSX memory builtins.
876 + (rs6000_init_builtins): Add V2DI types to internal types.
877 + (altivec_init_builtins): Add support for V2DF/V2DI altivec
878 + load/store builtins.
879 + (rs6000_address_for_altivec): Insure memory address is appropriate
882 + * config/rs6000/vsx.md (vsx_load_<mode>): New expanders for
883 + vec_vsx_ld and vec_vsx_st.
884 + (vsx_store_<mode>): Ditto.
886 + * config/rs6000/rs6000.h (RS6000_BTI_long_long): New type
887 + variables to hold long long types for VSX vector memory builtins.
888 + (RS6000_BTI_unsigned_long_long): Ditto.
889 + (long_long_integer_type_internal_node): Ditti.
890 + (long_long_unsigned_type_internal_node): Ditti.
892 + * config/rs6000/altivec.md (UNSPEC_LVX): New UNSPEC.
893 + (altivec_lvx_<mode>): Make altivec_lvx use a mode iterator.
894 + (altivec_stvx_<mode>): Make altivec_stvx use a mode iterator.
896 + * config/rs6000/altivec.h (vec_vsx_ld): Define VSX memory builtin
898 + (vec_vsx_st): Ditto.
900 + Backport from mainline:
901 + 2011-02-01 Michael Meissner <meissner@linux.vnet.ibm.com>
904 + * config/rs6000/vsx.md (vsx_float<VSi><mode>2): Use
905 + gpc_reg_operand instead of vsx_register_operand to match rs6000.md
906 + generator functions.
907 + (vsx_floatuns<VSi><mode>2): Ditto.
908 + (vsx_fix_trunc<mode><VSi>2): Ditto.
909 + (vsx_fixuns_trunc<mode><VSi>2): Ditto.
911 +2011-02-02 Nick Clifton <nickc@redhat.com>
913 + Import these patches from the mainline:
914 + 2011-01-31 Nick Clifton <nickc@redhat.com>
916 + * config/rx/rx.c (rx_get_stack_layout): Only save call clobbered
917 + registers inside interrupt handlers if the handler is not a leaf
920 + 2011-01-25 Nick Clifton <nickc@redhat.com>
922 + * config/rx/rx.h (LIBCALL_VALUE): Do not promote complex types.
923 + * config/rx/rx.c (rx_function_value): Likewise.
924 + (rx_promote_function_mode): Likewise.
925 + (gen_safe_add): Place an outsized immediate value inside an UNSPEC
926 + in order to make it legitimate.
927 + * config/rx/rx.md (adddi3_internal): If the second operand is a
928 + MEM make sure that the first operand is the same as the result
930 + (addsi3_unspec): Delete.
931 + (subdi3): Do not accept immediate operands.
932 + (subdi3_internal): Likewise.
934 + 2011-01-24 Richard Henderson <rth@redhat.com>
936 + * config/rx/predicates.md (rx_fp_comparison_operator): Don't accept
937 + compound unordered comparisons.
938 + * config/rx/rx.c (rx_split_fp_compare): Remove.
939 + * config/rx/rx-protos.h: Update.
940 + * config/rx/rx.md (gcc_conds, rx_conds): Remove.
941 + (cbranchsf4): Don't call rx_split_fp_compare.
942 + (*cbranchsf4): Use rx_split_cbranch.
943 + (*cmpsf): Don't accept "i" constraint.
944 + (*conditional_branch): Only valid after reload.
945 + (cstoresf4): Merge expander with insn. Don't call
946 + rx_split_fp_compare.
948 + 2011-01-22 Nick Clifton <nickc@redhat.com>
950 + * config/rx/rx.md (cstoresf4): Pass comparison operator to
951 + rx_split_fp_compare.
953 + 2011-01-22 Nick Clifton <nickc@redhat.com>
955 + * config/rx/rx.md (UNSPEC_CONST): New.
956 + (deallocate_and_return): Wrap the amount popped off the stack in
957 + an UNSPEC_CONST in order to stop it being rejected by
958 + -mmax-constant-size.
959 + (pop_and_return): Add a "(return)" rtx.
960 + (call): Drop the immediate operand.
961 + (call_internal): Likewise.
962 + (call_value): Likewise.
963 + (call_value_internal): Likewise.
964 + (sibcall_internal): Likewise.
965 + (sibcall_value_internal): Likewise.
966 + (sibcall): Likewise. Generate an explicit call using
968 + (sibcall_value): Likewise.
969 + (mov<>): FAIL if a constant operand is not legitimate.
970 + (addsi3_unpsec): New pattern.
972 + * config/rx/rx.c (rx_print_operand_address): Handle UNPSEC
974 + (ok_for_max_constant): New function.
975 + (gen_safe_add): New function.
976 + (rx_expand_prologue): Use gen_safe_add.
977 + (rx_expand_epilogue): Likewise.
978 + (rx_is_legitimate_constant): Use ok_for_max_constant. Handle
981 + 2011-01-17 Richard Henderson <rth@redhat.com>
983 + * config/rx/predicates.md (rx_constshift_operand): Use match_test.
984 + (rx_restricted_mem_operand): New.
985 + (rx_shift_operand): Use register_operand.
986 + (rx_source_operand, rx_compare_operand): Likewise.
987 + * config/rx/rx.md (addsi3_flags): New expander.
988 + (adddi3): Rewrite as expander.
989 + (adc_internal, *adc_flags, adddi3_internal): New patterns.
990 + (subsi3_flags): New expander.
991 + (subdi3): Rewrite as expander.
992 + (sbb_internal, *sbb_flags, subdi3_internal): New patterns.
994 + * config/rx/rx.c (RX_BUILTIN_SAT): Remove.
995 + (rx_init_builtins): Remove sat builtin.
996 + (rx_expand_builtin): Likewise.
997 + * config/rx/rx.md (ssaddsi3): New.
998 + (*sat): Rename from sat. Represent the CC_REG input.
1000 + * config/rx/predicates.md (rshift_operator): New.
1001 + * config/rx/rx.c (rx_expand_insv): Remove.
1002 + * config/rx/rx-protos.h: Update.
1003 + * config/rx/rx.md (*bitset): Rename from bitset. Swap the ashift
1004 + operand to the canonical position.
1005 + (*bitset_in_memory, *bitinvert, *bitinvert_in_memory): Similarly.
1006 + (*bitclr, *bitclr_in_memory): Similarly.
1007 + (*insv_imm, rx_insv_reg, *insv_cond, *bmcc, *insv_cond_lt): New.
1008 + (insv): Retain the zero_extract in the expansion.
1010 + * config/rx/rx.md (bswapsi2): Use = not + for output reload.
1011 + (bswaphi2, bitinvert, revw): Likewise.
1013 + * config/rx/rx.c (gen_rx_store_vector): Use VOIDmode for gen_rtx_SET.
1014 + (gen_rx_rtsd_vector, gen_rx_popm_vector): Likewise.
1015 + * config/rx/rx.md (pop_and_return): Use VOIDmode for SET.
1016 + (stack_push, stack_pushm, stack_pop, stack_popm): Likewise.
1017 + (bitset, bitset_in_memory): Likewise.
1018 + (bitinvert, bitinvert_in_memory): Likewise.
1019 + (bitclr, bitclr_in_memory): Likewise.
1020 + (insv, sync_lock_test_and_setsi, movstr, rx_movstr): Likewise.
1021 + (rx_strend, rx_cmpstrn): Likewise.
1022 + (rx_setmem): Likewise. Make the source BLKmode to match the dest.
1023 + (bitop peep2 patterns): Remove.
1025 + * config/rx/rx.c (rx_match_ccmode): New.
1026 + * config/rx/rx-protos.h: Update.
1027 + * config/rx/rx.md (abssi2): Clobber, don't set flags.
1028 + (addsi3, adddi3, andsi3, negsi2, one_cmplsi2, iorsi3): Likewise.
1029 + (rotlsi3, rotrsi3, ashrsi3, lshrsi3, ashlsi3): Likewise.
1030 + (subsi3, subdi3, xorsi3, addsf3, divsf3, mulsf3, subsf3): Likewise.
1031 + (fix_truncsfsi2, floatsisf2): Likewise.
1032 + (*abssi2_flags, *addsi3_flags, *andsi3_flags, *negsi2_flags): New.
1033 + (*one_cmplsi2_flags, *iorsi3_flags, *rotlsi3_flags): New.
1034 + (*rotrsi3_flags, *ashrsi3_flags, *lshrsi3_flags, *ashlsi3_flags): New.
1035 + (*subsi3_flags, *xorsi3_flags): New.
1037 + * config/rx/rx.md (cstoresf4, *cstoresf4): New patterns.
1039 + * config/rx/rx.c (rx_print_operand): Remove workaround for
1040 + unsplit comparison operations.
1042 + * config/rx/rx.md (movsicc): Split after reload.
1043 + (*movsicc): Merge *movsieq and *movsine via match_operator.
1044 + (*stcc): New pattern.
1046 + * config/rx/rx.c (rx_float_compare_mode): Remove.
1047 + * config/rx/rx.h (rx_float_compare_mode): Remove.
1048 + * config/rx/rx.md (cstoresi4): Split after reload.
1049 + (*sccc): New pattern.
1051 + * config/rx/predicates.md (label_ref_operand): New.
1052 + (rx_z_comparison_operator): New.
1053 + (rx_zs_comparison_operator): New.
1054 + (rx_fp_comparison_operator): New.
1055 + * config/rx/rx.c (rx_print_operand) [B]: Examine comparison modes.
1056 + Validate that the flags are set properly for the comparison.
1057 + (rx_gen_cond_branch_template): Remove.
1058 + (rx_cc_modes_compatible): Remove.
1059 + (mode_from_flags): New.
1060 + (flags_from_code): Rename from flags_needed_for_conditional.
1061 + (rx_cc_modes_compatible): Re-write in terms of flags_from_mode.
1062 + (rx_select_cc_mode): Likewise.
1063 + (rx_split_fp_compare): New.
1064 + (rx_split_cbranch): New.
1065 + * config/rx/rx.md (most_cond, zs_cond): Remove iterators.
1066 + (*cbranchsi4): Use match_operator and rx_split_cbranch.
1067 + (*cbranchsf4): Similarly.
1068 + (*cbranchsi4_tst): Rename from *tstbranchsi4_<code>. Use
1069 + match_operator and rx_split_cbranch.
1070 + (*cbranchsi4_tst_ext): Combine *tstbranchsi4m_eq and
1071 + tstbranchsi4m_ne. Use match_operator and rx_split_cbranch.
1072 + (*cmpsi): Rename from cmpsi.
1073 + (*tstsi): Rename from tstsi.
1074 + (*cmpsf): Rename from cmpsf; use CC_Fmode.
1075 + (*conditional_branch): Rename from conditional_branch.
1076 + (*reveresed_conditional_branch): Remove.
1077 + (b<code>): Remove expander.
1078 + * config/rx/rx-protos.h: Update.
1080 + * config/rx/rx.c (rx_compare_redundant): Remove.
1081 + * config/rx/rx.md (cmpsi): Don't use it.
1082 + * config/rx/rx-protos.h: Update.
1084 + * config/rx/rx-modes.def (CC_F): New mode.
1085 + * config/rx/rx.c (rx_select_cc_mode): New.
1086 + * config/rx/rx.h (SELECT_CC_MODE): Use it.
1087 + * config/rx/rx-protos.h: Update.
1089 +2011-02-01 Richard Guenther <rguenther@suse.de>
1091 + PR tree-optimization/47541
1092 + * tree-ssa-structalias.c (push_fields_onto_fieldstack): Make
1093 + sure to have a field at offset zero.
1095 +2011-01-31 Nathan Froyd <froydnj@codesourcery.com>
1097 + Backport from mainline:
1098 + 2010-12-30 Nathan Froyd <froydnj@codesourcery.com>
1101 + * reload1.c (choose_reload_regs): Don't look for equivalences for
1102 + output reloads of constant loads.
1104 +2011-01-30 Gerald Pfeifer <gerald@pfeifer.com>
1106 + * doc/install.texi (hppa-hp-hpux10): Remove references to HP
1109 +2011-01-30 Gerald Pfeifer <gerald@pfeifer.com>
1111 + * doc/install.texi: Update copyright years.
1113 +2011-01-30 Gerald Pfeifer <gerald@pfeifer.com>
1115 + * doc/install.texi (Binaries): Remove outdated reference for
1116 + Motorola 68HC11/68HC12 downloads.
1118 +2011-01-30 Gerald Pfeifer <gerald@pfeifer.com>
1120 + * doc/extend.texi (Thread-Local): Adjust reference to Ulrich
1123 +2011-01-29 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1125 + Backport from mainline:
1126 + 2010-08-22 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1129 + * gthr-posix.h (__gthread_active_init): Delete.
1130 + (__gthread_active_p): Do activity check here.
1131 + Don't include errno.h on hppa-hpux. Update comment.
1132 + * gthr-posix95.h (__gthread_active_init): Delete.
1133 + (__gthread_active_p): Do activity check here.
1134 + Don't include errno.h on hppa-hpux. Update comment.
1135 + * config.gcc (hppa[12]*-*-hpux11*): Define extra_parts.
1136 + * config/pa/pa64-hpux.h (LIB_SPEC): When -static is specified, only
1137 + add -lpthread when -mt or -pthread is specified.
1138 + * config/pa/pa-hpux11.h (LIB_SPEC): likewise.
1139 + (LINK_GCC_C_SEQUENCE_SPEC): Define.
1140 + * config/pa/t-pa-hpux11 (LIBGCCSTUB_OBJS): Define.
1141 + (stublib.c, pthread_default_stacksize_np-stub.o,
1142 + pthread_mutex_lock-stub.o, pthread_mutex_unlock-stub.o,
1143 + $(T)libgcc_stub.a): Add methods.
1144 + * config/pa/t-pa64 (LIBGCCSTUB_OBJS): Add pthread stubs.
1145 + (stublib.c, pthread_default_stacksize_np-stub.o,
1146 + pthread_mutex_lock-stub.o, pthread_mutex_unlock-stub.o): Add methods.
1147 + * config/pa/stublib.c (pthread_default_stacksize_np, pthread_mutex_lock,
1148 + pthread_mutex_unlock): New stubs.
1150 +2011-01-26 Eric Botcazou <ebotcazou@adacore.com>
1152 + PR rtl-optimization/44469
1153 + * cfgcleanup.c (try_optimize_cfg): Iterate in CFG layout mode too
1154 + after removing trivially dead basic blocks.
1156 +2011-01-25 Richard Guenther <rguenther@suse.de>
1158 + PR tree-optimization/47411
1159 + Backport from mainline
1160 + 2010-06-30 Michael Matz <matz@suse.de>
1162 + PR bootstrap/44699
1163 + * tree-vrp.c (vrp_finalize): Deal with changing num_ssa_names.
1165 +2011-01-21 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1167 + Backport from mainline.
1168 + 2010-09-08 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1171 + * config/arm/arm.md (bswapsi2): Handle condition correctly
1172 + for armv6 and optimize_size.
1174 +2011-01-21 Richard Guenther <rguenther@suse.de>
1176 + PR tree-optimization/47365
1177 + * tree-ssa-sccvn.h (vn_lookup_kind): Declare.
1178 + (vn_reference_lookup_pieces): Adjust.
1179 + (vn_reference_lookup): Likewise.
1180 + * tree-ssa-sccvn.c (vn_walk_kind): New static global.
1181 + (vn_reference_lookup_3): Only look through kills if in
1182 + VN_WALKREWRITE mode.
1183 + (vn_reference_lookup_pieces): Adjust.
1184 + (vn_reference_lookup): Likewise.
1185 + (visit_reference_op_load): Likewise.
1186 + (visit_reference_op_store): Likewise.
1187 + * tree-ssa-pre.c (phi_translate_1): Use VN_WALK mode.
1188 + (compute_avail): Likewise.
1189 + (eliminate): Likewise.
1191 +2011-01-20 Richard Guenther <rguenther@suse.de>
1193 + PR tree-optimization/47167
1194 + * tree-ssa-copyrename.c (copy_rename_partition_coalesce):
1195 + Revert previous change, only avoid enumeral type changes.
1197 +2011-01-17 H.J. Lu <hongjiu.lu@intel.com>
1199 + Backport from mainline
1200 + 2011-01-17 H.J. Lu <hongjiu.lu@intel.com>
1203 + * config/i386/avxintrin.h (_mm_maskload_pd): Change mask to
1205 + (_mm_maskstore_pd): Likewise.
1206 + (_mm_maskload_ps): Likewise.
1207 + (_mm_maskstore_ps): Likewise.
1208 + (_mm256_maskload_pd): Change mask to __m256i.
1209 + (_mm256_maskstore_pd): Likewise.
1210 + (_mm256_maskload_ps): Likewise.
1211 + (_mm256_maskstore_ps): Likewise.
1213 + * config/i386/i386-builtin-types.def: Updated.
1214 + (ix86_expand_special_args_builtin): Likewise.
1216 + * config/i386/i386.c (bdesc_special_args): Update
1217 + __builtin_ia32_maskloadpd, __builtin_ia32_maskloadps,
1218 + __builtin_ia32_maskloadpd256, __builtin_ia32_maskloadps256,
1219 + __builtin_ia32_maskstorepd, __builtin_ia32_maskstoreps,
1220 + __builtin_ia32_maskstorepd256 and __builtin_ia32_maskstoreps256.
1222 + * config/i386/sse.md (avx_maskload<ssemodesuffix><avxmodesuffix>):
1223 + Use <avxpermvecmode> on mask register.
1224 + (avx_maskstore<ssemodesuffix><avxmodesuffix>): Likewise.
1226 +2011-01-17 Olivier Hainque <hainque@adacore.com>
1227 + Michael Haubenwallner <michael.haubenwallner@salomon.at>
1228 + Eric Botcazou <ebotcazou@adacore.com>
1231 + * xcoffout.c (ASM_OUTPUT_LINE): Output line only if positive, and only
1232 + if <= USHRT_MAX in 32-bit mode.
1234 +2011-01-17 Richard Guenther <rguenther@suse.de>
1236 + Backport from mainline
1237 + PR tree-optimization/47286
1238 + * tree-ssa-structalias.c (new_var_info): Register variables
1241 + PR tree-optimization/44592
1242 + * tree-ssa-ccp.c (gimplify_and_update_call_from_tree): Copy
1245 +2011-01-16 Jakub Jelinek <jakub@redhat.com>
1247 + Backport from mainline
1248 + 2011-01-07 Jakub Jelinek <jakub@redhat.com>
1251 + * config/i386/i386.c (ix86_delegitimize_address): If
1252 + simplify_gen_subreg fails, return orig_x.
1254 + 2011-01-06 Jakub Jelinek <jakub@redhat.com>
1257 + * c-convert.c (convert): When converting a complex expression
1258 + other than COMPLEX_EXPR to a different complex type, ensure
1259 + c_save_expr is called instead of save_expr, unless in_late_binary_op.
1260 + * c-typeck.c (convert_for_assignment): Set in_late_binary_op also
1261 + when converting COMPLEX_TYPE.
1263 + 2010-12-21 Jakub Jelinek <jakub@redhat.com>
1266 + * config/i386/sse.md (sse2_loadlpd, sse2_movsd): Fix shufpd source
1269 + PR middle-end/45852
1270 + * expr.c (store_expr): Ignore alt_rtl if equal to target,
1271 + but has side-effects.
1273 + 2010-12-16 Jakub Jelinek <jakub@redhat.com>
1275 + PR tree-optimization/43655
1276 + * tree-ssa-ter.c (is_replaceable_p): Don't use
1277 + gimple_references_memory_p for -O0, instead check for load
1278 + by looking at rhs.
1281 + * cfgexpand.c (expand_debug_expr): If GET_MODE (op0) is VOIDmode,
1282 + use TYPE_MODE (TREE_TYPE (tem)) instead of mode1.
1284 + 2010-12-10 Jakub Jelinek <jakub@redhat.com>
1286 + PR rtl-optimization/46804
1287 + * regmove.c (optimize_reg_copy_3): Look for REG_EQUAL note
1288 + on the setter of src_reg rather than on insn. If it is
1289 + equal to the setter's original SET_SRC, replace it with its
1290 + zero or sign extension instead of dropping it.
1292 + PR rtl-optimization/46865
1293 + * rtl.c (rtx_equal_p_cb, rtx_equal_p): For last operand of
1294 + ASM_OPERANDS and ASM_INPUT if integers are different,
1296 + * jump.c (rtx_renumbered_equal_p): Likewise.
1298 + PR tree-optimization/46864
1299 + * tree-ssa-loop-im.c (loop_suitable_for_sm): Return false even
1300 + when there are EDGE_EH exit edges.
1302 + 2010-12-09 Jakub Jelinek <jakub@redhat.com>
1305 + * config/rs6000/rs6000.c (rs6000_expand_vector_extract): Use stvx
1306 + instead of stve*x.
1307 + (altivec_expand_stv_builtin): For op0 use mode of operand 1 instead
1309 + * config/rs6000/altivec.md (VI_scalar): New mode attr.
1310 + (altivec_stve<VI_char>x, *altivec_stvesfx): Use scalar instead of
1311 + vector mode for operand 0, put operand 1 into UNSPEC.
1313 +2011-01-13 Nick Clifton <nickc@redhat.com>
1315 + Import this fix from the mainline:
1316 + 2010-10-19 Nick Clifton <nickc@redhat.com>
1318 + * config/rx/rx.c (rx_function_value): Small integer types are
1319 + promoted to SImode.
1320 + (rx_promote_function_mode): New function.
1321 + (TARGET_PROMOTE_FUNCTION_MODE): Define.
1323 +2011-01-07 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
1325 + Backport from mainline:
1326 + 2011-01-06 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
1329 + * config/i386/i386.c (legitimize_tls_address)
1330 + <TLS_MODEL_INITIAL_EXEC>: Handle TARGET_64BIT && TARGET_SUN_TLS.
1331 + * config/i386/i386.md (UNSPEC_TLS_IE_SUN): Declare.
1332 + (tls_initial_exec_64_sun): New pattern.
1334 +2011-01-03 Eric Botcazou <ebotcazou@adacore.com>
1336 + Backport from mainline
1337 + 2010-12-30 Eric Botcazou <ebotcazou@adacore.com>
1340 + * config/sparc/sparc.c (sparc_file_end): Call resolve_unique_section
1341 + on the GOT helper if USE_HIDDEN_LINKONCE.
1343 + 2010-12-02 Eric Botcazou <ebotcazou@adacore.com>
1346 + * config/sparc/sparc.c (can_use_mov_pic_label_ref): New predicate.
1347 + (sparc_expand_move): Call it to decide whether to emit the special
1348 + mov{si,di}_pic_label_ref patterns.
1349 + (sparc_legitimize_pic_address): Call it to decide whether to emit
1350 + the regular PIC sequence for labels. Fix long line.
1351 + (sparc_file_end): Set is_thunk for the PIC helper.
1353 +2010-12-30 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1355 + * config/pa/pa.md: Add ",*" condition to 64-bit add/subtract boolean
1358 +2010-12-27 Yao Qi <yao@codesourcery.com>
1360 + Backport from mainline:
1361 + 2010-10-14 Yao Qi <yao@codesourcery.com>
1364 + * config/arm/arm.c (arm_build_builtin_va_list): Assign
1365 + va_list_name to TYPE_STUB_DECL (va_list_type).
1367 +2010-12-23 Sebastian Pop <sebastian.pop@amd.com>
1368 + Richard Guenther <rguenther@suse.de>
1370 + PR tree-optimization/46758
1371 + * graphite-sese-to-poly.c (scan_tree_for_params_right_scev): Use
1372 + tree_int_to_gmp instead of int_cst_value.
1373 + (scan_tree_for_params_int): Same.
1374 + (scan_tree_for_params): Same.
1375 + (pdr_add_data_dimensions): Use ppl_set_inhomogeneous_tree.
1377 +2010-12-23 Sebastian Pop <sebastian.pop@amd.com>
1379 + Backport from mainline
1380 + Fix PR45758: reset scevs before Graphite.
1381 + 2010-09-24 Sebastian Pop <sebastian.pop@amd.com>
1383 + PR tree-optimization/45552
1384 + * graphite.c (graphite_initialize): Call scev_reset.
1386 +2010-12-23 Sebastian Pop <sebastian.pop@amd.com>
1388 + PR tree-optimization/43023
1389 + * tree-data-ref.c (mem_write_stride_of_same_size_as_unit_type_p):
1391 + (stores_zero_from_loop): Call stmt_stores_zero.
1392 + (stmt_with_adjacent_zero_store_dr_p): New.
1393 + * tree-data-ref.h (stmt_with_adjacent_zero_store_dr_p): Declared.
1394 + (stride_of_unit_type_p): New.
1395 + * tree-loop-distribution.c (generate_memset_zero): Do not return a
1396 + boolean. Call gcc_assert on stride_of_unit_type_p.
1397 + (generate_builtin): Call stmt_stores_zero.
1398 + (rdg_flag_all_uses): Removed.
1399 + (rdg_flag_similar_memory_accesses): Removed.
1400 + (build_rdg_partition_for_component): Removed parameter
1401 + other_stores. Removed call to rdg_flag_similar_memory_accesses.
1402 + (can_generate_builtin): New.
1403 + (similar_memory_accesses): New.
1404 + (fuse_partitions_with_similar_memory_accesses): New.
1405 + (rdg_build_partitions): Call
1406 + fuse_partitions_with_similar_memory_accesses.
1408 +2010-12-21 Martin Jambor <mjambor@suse.cz>
1410 + Backport from mainline:
1411 + 2010-12-09 Martin Jambor <mjambor@suse.cz>
1413 + PR middle-end/46734
1414 + * tree-sra.c (splice_param_accesses): Check that there are not
1415 + multiple ADDRESSABLE types.
1417 +2010-12-19 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1419 + Backport from mainline:
1420 + 2010-12-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
1423 + * config/pa/pa.c (branch_to_delay_slot_p): Use next_active_insn instead
1424 + of next_real_insn. Search forward checking for both ASM_INPUT and
1425 + ASM_OPERANDS asms until exit condition is found.
1426 + (branch_needs_nop_p): Likewise.
1427 + (use_skip_p): New function.
1428 + (output_cbranch): Use use_skip_p.
1429 + (output_bb, output_bvb): Likewise.
1431 +2010-12-19 Eric Botcazou <ebotcazou@adacore.com>
1434 + * config/sparc/sparc.h (GLOBAL_OFFSET_TABLE_REGNUM): New macro.
1435 + (PIC_OFFSET_TABLE_REGNUM): Rewrite in terms of above macro.
1436 + * config/sparc/sparc.c (pic_helper_needed): Delete.
1437 + (global_offset_table): Likewise.
1438 + (pic_helper_symbol): Rename to...
1439 + (got_helper_rtx): ...this.
1440 + (global_offset_table_rtx): New global variable.
1441 + (sparc_got_symbol): Likewise.
1442 + (sparc_got): New static function.
1443 + (check_pic): Use local variable and call sparc_got.
1444 + (sparc_tls_symbol): Initialize to NULL_RTX.
1445 + (sparc_tls_got): In non-PIC mode, reload the GOT register for Sun TLS
1446 + and 32-bit ABI and copy the GOT symbol to a new register otherwise.
1447 + (get_pc_thunk_name): Rename local variable.
1448 + (gen_load_pcrel_sym): New wrapper around load_pcrel_sym{si,di}.
1449 + (load_pic_register): Rename to...
1450 + (load_got_register): ...this. Adjust and call gen_load_pcrel_sym.
1451 + (sparc_expand_prologue): Do not test flag_pic.
1452 + (sparc_output_mi_thunk): Use pic_offset_table_rtx directly.
1453 + (sparc_file_end): Test got_helper_rtx instead of pic_helper_needed.
1454 + Rename local variable and do not call get_pc_thunk_name again.
1455 + * config/sparc/sparc.md (load_pcrel_sym): Add operand #3.
1457 +2010-12-18 Alexandre Oliva <aoliva@redhat.com>
1460 + * jump.c (mark_all_labels): Skip debug insns.
1462 +2010-12-18 Alexandre Oliva <aoliva@redhat.com>
1465 + * cfgcleanup.c (try_forward_edges): Skip debug insns.
1467 +2010-12-16 Eric Botcazou <ebotcazou@adacore.com>
1469 + * tree-ssa-sccvn.c (vn_reference_lookup_3): Always punt if the call to
1470 + get_ref_base_and_extent returns -1 as the max size.
1472 +2010-12-16 Richard Guenther <rguenther@suse.de>
1474 + * DEV-PHASE: Set back to prerelease.
1475 + * BASE-VER: Bump to 4.5.3.
1477 2010-12-16 Release Manager
1479 * GCC 4.5.2 released.
1480 Index: gcc/testsuite/gcc.c-torture/compile/pr47150.c
1481 ===================================================================
1482 --- gcc/testsuite/gcc.c-torture/compile/pr47150.c (.../tags/gcc_4_5_2_release) (wersja 0)
1483 +++ gcc/testsuite/gcc.c-torture/compile/pr47150.c (.../branches/gcc-4_5-branch) (wersja 170084)
1487 +float _Complex foo (float, float);
1494 + b = 0.5 * (foo (0, w) + foo (1, w) / w);
1496 Index: gcc/testsuite/gcc.c-torture/compile/20110126-1.c
1497 ===================================================================
1498 --- gcc/testsuite/gcc.c-torture/compile/20110126-1.c (.../tags/gcc_4_5_2_release) (wersja 0)
1499 +++ gcc/testsuite/gcc.c-torture/compile/20110126-1.c (.../branches/gcc-4_5-branch) (wersja 170084)
1501 +/* PR rtl-optimization/44469 */
1502 +/* Testcase by Siarhei Siamashka <siarhei.siamashka@gmail.com> */
1504 +int a (int *t, const char *p)
1511 + p = (const char *)t;
1514 + __builtin_unreachable();
1519 Index: gcc/testsuite/gcc.target/arm/pr45447.c
1520 ===================================================================
1521 --- gcc/testsuite/gcc.target/arm/pr45447.c (.../tags/gcc_4_5_2_release) (wersja 0)
1522 +++ gcc/testsuite/gcc.target/arm/pr45447.c (.../branches/gcc-4_5-branch) (wersja 170084)
1524 +/* { dg-do compile } */
1525 +/* { dg-options "-g -femit-struct-debug-baseonly" } */
1526 +typedef __builtin_va_list x;
1527 Index: gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c
1528 ===================================================================
1529 --- gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c (.../tags/gcc_4_5_2_release) (wersja 0)
1530 +++ gcc/testsuite/gcc.target/powerpc/vsx-builtin-8.c (.../branches/gcc-4_5-branch) (wersja 170084)
1532 +/* { dg-do compile { target { powerpc*-*-* } } } */
1533 +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
1534 +/* { dg-require-effective-target powerpc_vsx_ok } */
1535 +/* { dg-options "-O3 -mcpu=power7" } */
1537 +/* Test the various load/store varients. */
1539 +#include <altivec.h>
1541 +#define TEST_COPY(NAME, TYPE) \
1542 +void NAME ## _copy_native (vector TYPE *a, vector TYPE *b) \
1547 +void NAME ## _copy_vec (vector TYPE *a, vector TYPE *b) \
1549 + vector TYPE x = vec_ld (0, b); \
1550 + vec_st (x, 0, a); \
1553 +#define TEST_COPYL(NAME, TYPE) \
1554 +void NAME ## _lvxl (vector TYPE *a, vector TYPE *b) \
1556 + vector TYPE x = vec_ldl (0, b); \
1557 + vec_stl (x, 0, a); \
1560 +#define TEST_VSX_COPY(NAME, TYPE) \
1561 +void NAME ## _copy_vsx (vector TYPE *a, vector TYPE *b) \
1563 + vector TYPE x = vec_vsx_ld (0, b); \
1564 + vec_vsx_st (x, 0, a); \
1567 +#define TEST_ALIGN(NAME, TYPE) \
1568 +void NAME ## _align (vector unsigned char *a, TYPE *b) \
1570 + vector unsigned char x = vec_lvsl (0, b); \
1571 + vector unsigned char y = vec_lvsr (0, b); \
1572 + vec_st (x, 0, a); \
1573 + vec_st (y, 8, a); \
1577 +TEST_COPY(uchar, unsigned char)
1578 +TEST_COPY(schar, signed char)
1579 +TEST_COPY(bchar, bool char)
1580 +TEST_COPY(ushort, unsigned short)
1581 +TEST_COPY(sshort, signed short)
1582 +TEST_COPY(bshort, bool short)
1583 +TEST_COPY(uint, unsigned int)
1584 +TEST_COPY(sint, signed int)
1585 +TEST_COPY(bint, bool int)
1586 +TEST_COPY(float, float)
1587 +TEST_COPY(double, double)
1588 +#endif /* NO_COPY */
1591 +TEST_COPYL(uchar, unsigned char)
1592 +TEST_COPYL(schar, signed char)
1593 +TEST_COPYL(bchar, bool char)
1594 +TEST_COPYL(ushort, unsigned short)
1595 +TEST_COPYL(sshort, signed short)
1596 +TEST_COPYL(bshort, bool short)
1597 +TEST_COPYL(uint, unsigned int)
1598 +TEST_COPYL(sint, signed int)
1599 +TEST_COPYL(bint, bool int)
1600 +TEST_COPYL(float, float)
1601 +TEST_COPYL(double, double)
1602 +#endif /* NO_COPYL */
1605 +TEST_ALIGN(uchar, unsigned char)
1606 +TEST_ALIGN(schar, signed char)
1607 +TEST_ALIGN(ushort, unsigned short)
1608 +TEST_ALIGN(sshort, signed short)
1609 +TEST_ALIGN(uint, unsigned int)
1610 +TEST_ALIGN(sint, signed int)
1611 +TEST_ALIGN(float, float)
1612 +TEST_ALIGN(double, double)
1613 +#endif /* NO_ALIGN */
1616 +#ifndef NO_VSX_COPY
1617 +TEST_VSX_COPY(uchar, unsigned char)
1618 +TEST_VSX_COPY(schar, signed char)
1619 +TEST_VSX_COPY(bchar, bool char)
1620 +TEST_VSX_COPY(ushort, unsigned short)
1621 +TEST_VSX_COPY(sshort, signed short)
1622 +TEST_VSX_COPY(bshort, bool short)
1623 +TEST_VSX_COPY(uint, unsigned int)
1624 +TEST_VSX_COPY(sint, signed int)
1625 +TEST_VSX_COPY(bint, bool int)
1626 +TEST_VSX_COPY(float, float)
1627 +TEST_VSX_COPY(double, double)
1628 +#endif /* NO_VSX_COPY */
1629 Index: gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c
1630 ===================================================================
1631 --- gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c (.../tags/gcc_4_5_2_release) (wersja 170084)
1632 +++ gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c (.../branches/gcc-4_5-branch) (wersja 170084)
1634 /* { dg-do run { target { powerpc64-*-* && { lp64 && dfprt } } } } */
1635 +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
1636 /* { dg-options "-std=gnu99 -O2 -fno-strict-aliasing" } */
1638 /* Testcase to check for ABI compliance of parameter passing
1643 -/* Testcase could break on future gcc's, if parameter regs
1644 - are changed before this asm. */
1645 +/* Wrapper to save the GPRs and FPRs and then jump to the real function. */
1646 +#define WRAPPER(NAME) \
1647 +__asm__ ("\t.globl\t" #NAME "_asm\n\t" \
1648 + ".section \".opd\",\"aw\"\n\t" \
1650 + #NAME "_asm:\n\t" \
1651 + ".quad .L." #NAME "_asm,.TOC.@tocbase,0\n\t" \
1653 + ".type " #NAME "_asm, @function\n" \
1654 + ".L." #NAME "_asm:\n\t" \
1655 + "ld 11,gparms@got(2)\n\t" \
1656 + "std 3,0(11)\n\t" \
1657 + "std 4,8(11)\n\t" \
1658 + "std 5,16(11)\n\t" \
1659 + "std 6,24(11)\n\t" \
1660 + "std 7,32(11)\n\t" \
1661 + "std 8,40(11)\n\t" \
1662 + "std 9,48(11)\n\t" \
1663 + "std 10,56(11)\n\t" \
1664 + "stfd 1,64(11)\n\t" \
1665 + "stfd 2,72(11)\n\t" \
1666 + "stfd 3,80(11)\n\t" \
1667 + "stfd 4,88(11)\n\t" \
1668 + "stfd 5,96(11)\n\t" \
1669 + "stfd 6,104(11)\n\t" \
1670 + "stfd 7,112(11)\n\t" \
1671 + "stfd 8,120(11)\n\t" \
1672 + "stfd 9,128(11)\n\t" \
1673 + "stfd 10,136(11)\n\t" \
1674 + "stfd 11,144(11)\n\t" \
1675 + "stfd 12,152(11)\n\t" \
1676 + "stfd 13,160(11)\n\t" \
1677 + "b " #NAME "\n\t" \
1679 + ".byte 0,0,0,0,0,0,0,0\n\t" \
1680 + ".size " #NAME ",.-" #NAME "\n")
1683 -#define save_parms(lparms) \
1684 - asm volatile ("ld 11,gparms@got(2)\n\t" \
1685 - "std 3,0(11)\n\t" \
1686 - "std 4,8(11)\n\t" \
1687 - "std 5,16(11)\n\t" \
1688 - "std 6,24(11)\n\t" \
1689 - "std 7,32(11)\n\t" \
1690 - "std 8,40(11)\n\t" \
1691 - "std 9,48(11)\n\t" \
1692 - "std 10,56(11)\n\t" \
1693 - "stfd 1,64(11)\n\t" \
1694 - "stfd 2,72(11)\n\t" \
1695 - "stfd 3,80(11)\n\t" \
1696 - "stfd 4,88(11)\n\t" \
1697 - "stfd 5,96(11)\n\t" \
1698 - "stfd 6,104(11)\n\t" \
1699 - "stfd 7,112(11)\n\t" \
1700 - "stfd 8,120(11)\n\t" \
1701 - "stfd 9,128(11)\n\t" \
1702 - "stfd 10,136(11)\n\t" \
1703 - "stfd 11,144(11)\n\t" \
1704 - "stfd 12,152(11)\n\t" \
1705 - "stfd 13,160(11)\n\t":::"11", "memory"); \
1708 -#define save_parms(lparms) \
1709 - asm volatile ("ld r11,gparms@got(r2)\n\t" \
1710 - "std r3,0(r11)\n\t" \
1711 - "std r4,8(r11)\n\t" \
1712 - "std r5,16(r11)\n\t" \
1713 - "std r6,24(r11)\n\t" \
1714 - "std r7,32(r11)\n\t" \
1715 - "std r8,40(r11)\n\t" \
1716 - "std r9,48(r11)\n\t" \
1717 - "std r10,56(r11)\n\t" \
1718 - "stfd f1,64(r11)\n\t" \
1719 - "stfd f2,72(r11)\n\t" \
1720 - "stfd f3,80(r11)\n\t" \
1721 - "stfd f4,88(r11)\n\t" \
1722 - "stfd f5,96(r11)\n\t" \
1723 - "stfd f6,104(r11)\n\t" \
1724 - "stfd f7,112(r11)\n\t" \
1725 - "stfd f8,120(r11)\n\t" \
1726 - "stfd f9,128(r11)\n\t" \
1727 - "stfd f10,136(r11)\n\t" \
1728 - "stfd f11,144(r11)\n\t" \
1729 - "stfd f12,152(r11)\n\t" \
1730 - "stfd f13,160(r11)\n\t":::"r11", "memory"); \
1736 struct sf *backchain;
1738 unsigned long slot[100];
1741 +extern void func0_asm (double, double, double, double, double, double,
1742 + double, double, double, double, double, double,
1744 + _Decimal64, _Decimal128, _Decimal64);
1748 /* Fill up floating point registers with double arguments, forcing
1749 decimal float arguments into the parameter save area. */
1750 void __attribute__ ((noinline))
1751 @@ -105,186 +95,209 @@
1752 double a13, double a14,
1753 _Decimal64 a15, _Decimal128 a16, _Decimal64 a17)
1755 - reg_parms_t lparms;
1758 - save_parms (lparms);
1759 sp = __builtin_frame_address (0);
1762 - if (a1 != lparms.fprs[0]) FAILURE
1763 - if (a2 != lparms.fprs[1]) FAILURE
1764 - if (a3 != lparms.fprs[2]) FAILURE
1765 - if (a4 != lparms.fprs[3]) FAILURE
1766 - if (a5 != lparms.fprs[4]) FAILURE
1767 - if (a6 != lparms.fprs[5]) FAILURE
1768 - if (a7 != lparms.fprs[6]) FAILURE
1769 - if (a8 != lparms.fprs[7]) FAILURE
1770 - if (a9 != lparms.fprs[8]) FAILURE
1771 - if (a10 != lparms.fprs[9]) FAILURE
1772 - if (a11 != lparms.fprs[10]) FAILURE
1773 - if (a12 != lparms.fprs[11]) FAILURE
1774 - if (a13 != lparms.fprs[12]) FAILURE
1775 + if (a1 != gparms.fprs[0]) FAILURE
1776 + if (a2 != gparms.fprs[1]) FAILURE
1777 + if (a3 != gparms.fprs[2]) FAILURE
1778 + if (a4 != gparms.fprs[3]) FAILURE
1779 + if (a5 != gparms.fprs[4]) FAILURE
1780 + if (a6 != gparms.fprs[5]) FAILURE
1781 + if (a7 != gparms.fprs[6]) FAILURE
1782 + if (a8 != gparms.fprs[7]) FAILURE
1783 + if (a9 != gparms.fprs[8]) FAILURE
1784 + if (a10 != gparms.fprs[9]) FAILURE
1785 + if (a11 != gparms.fprs[10]) FAILURE
1786 + if (a12 != gparms.fprs[11]) FAILURE
1787 + if (a13 != gparms.fprs[12]) FAILURE
1788 if (a14 != *(double *)&sp->slot[13]) FAILURE
1789 if (a15 != *(_Decimal64 *)&sp->slot[14]) FAILURE
1790 if (a16 != *(_Decimal128 *)&sp->slot[15]) FAILURE
1791 if (a17 != *(_Decimal64 *)&sp->slot[17]) FAILURE
1794 +extern void func1_asm (double, double, double, double, double, double,
1795 + double, double, double, double, double, double,
1796 + double, _Decimal128 );
1800 void __attribute__ ((noinline))
1801 func1 (double a1, double a2, double a3, double a4, double a5, double a6,
1802 double a7, double a8, double a9, double a10, double a11, double a12,
1803 double a13, _Decimal128 a14)
1805 - reg_parms_t lparms;
1808 - save_parms (lparms);
1809 sp = __builtin_frame_address (0);
1812 - if (a1 != lparms.fprs[0]) FAILURE
1813 - if (a2 != lparms.fprs[1]) FAILURE
1814 - if (a3 != lparms.fprs[2]) FAILURE
1815 - if (a4 != lparms.fprs[3]) FAILURE
1816 - if (a5 != lparms.fprs[4]) FAILURE
1817 - if (a6 != lparms.fprs[5]) FAILURE
1818 - if (a7 != lparms.fprs[6]) FAILURE
1819 - if (a8 != lparms.fprs[7]) FAILURE
1820 - if (a9 != lparms.fprs[8]) FAILURE
1821 - if (a10 != lparms.fprs[9]) FAILURE
1822 - if (a11 != lparms.fprs[10]) FAILURE
1823 - if (a12 != lparms.fprs[11]) FAILURE
1824 - if (a13 != lparms.fprs[12]) FAILURE
1825 + if (a1 != gparms.fprs[0]) FAILURE
1826 + if (a2 != gparms.fprs[1]) FAILURE
1827 + if (a3 != gparms.fprs[2]) FAILURE
1828 + if (a4 != gparms.fprs[3]) FAILURE
1829 + if (a5 != gparms.fprs[4]) FAILURE
1830 + if (a6 != gparms.fprs[5]) FAILURE
1831 + if (a7 != gparms.fprs[6]) FAILURE
1832 + if (a8 != gparms.fprs[7]) FAILURE
1833 + if (a9 != gparms.fprs[8]) FAILURE
1834 + if (a10 != gparms.fprs[9]) FAILURE
1835 + if (a11 != gparms.fprs[10]) FAILURE
1836 + if (a12 != gparms.fprs[11]) FAILURE
1837 + if (a13 != gparms.fprs[12]) FAILURE
1838 if (a14 != *(_Decimal128 *)&sp->slot[13]) FAILURE
1841 +extern void func2_asm (double, double, double, double, double, double,
1842 + double, double, double, double, double, double,
1847 void __attribute__ ((noinline))
1848 func2 (double a1, double a2, double a3, double a4, double a5, double a6,
1849 double a7, double a8, double a9, double a10, double a11, double a12,
1852 - reg_parms_t lparms;
1855 - save_parms (lparms);
1856 sp = __builtin_frame_address (0);
1859 - if (a1 != lparms.fprs[0]) FAILURE
1860 - if (a2 != lparms.fprs[1]) FAILURE
1861 - if (a3 != lparms.fprs[2]) FAILURE
1862 - if (a4 != lparms.fprs[3]) FAILURE
1863 - if (a5 != lparms.fprs[4]) FAILURE
1864 - if (a6 != lparms.fprs[5]) FAILURE
1865 - if (a7 != lparms.fprs[6]) FAILURE
1866 - if (a8 != lparms.fprs[7]) FAILURE
1867 - if (a9 != lparms.fprs[8]) FAILURE
1868 - if (a10 != lparms.fprs[9]) FAILURE
1869 - if (a11 != lparms.fprs[10]) FAILURE
1870 - if (a12 != lparms.fprs[11]) FAILURE
1871 + if (a1 != gparms.fprs[0]) FAILURE
1872 + if (a2 != gparms.fprs[1]) FAILURE
1873 + if (a3 != gparms.fprs[2]) FAILURE
1874 + if (a4 != gparms.fprs[3]) FAILURE
1875 + if (a5 != gparms.fprs[4]) FAILURE
1876 + if (a6 != gparms.fprs[5]) FAILURE
1877 + if (a7 != gparms.fprs[6]) FAILURE
1878 + if (a8 != gparms.fprs[7]) FAILURE
1879 + if (a9 != gparms.fprs[8]) FAILURE
1880 + if (a10 != gparms.fprs[9]) FAILURE
1881 + if (a11 != gparms.fprs[10]) FAILURE
1882 + if (a12 != gparms.fprs[11]) FAILURE
1883 if (a13 != *(_Decimal128 *)&sp->slot[12]) FAILURE
1886 +extern void func3_asm (_Decimal64, _Decimal128, _Decimal64, _Decimal128,
1887 + _Decimal64, _Decimal128, _Decimal64, _Decimal128,
1888 + _Decimal64, _Decimal128);
1892 void __attribute__ ((noinline))
1893 func3 (_Decimal64 a1, _Decimal128 a2, _Decimal64 a3, _Decimal128 a4,
1894 _Decimal64 a5, _Decimal128 a6, _Decimal64 a7, _Decimal128 a8,
1895 _Decimal64 a9, _Decimal128 a10)
1897 - reg_parms_t lparms;
1900 - save_parms (lparms);
1901 sp = __builtin_frame_address (0);
1904 - if (a1 != *(_Decimal64 *)&lparms.fprs[0]) FAILURE /* f1 */
1905 - if (a2 != *(_Decimal128 *)&lparms.fprs[1]) FAILURE /* f2 & f3 */
1906 - if (a3 != *(_Decimal64 *)&lparms.fprs[3]) FAILURE /* f4 */
1907 - if (a4 != *(_Decimal128 *)&lparms.fprs[5]) FAILURE /* f6 & f7 */
1908 - if (a5 != *(_Decimal64 *)&lparms.fprs[7]) FAILURE /* f8 */
1909 - if (a6 != *(_Decimal128 *)&lparms.fprs[9]) FAILURE /* f10 & f11 */
1910 - if (a7 != *(_Decimal64 *)&lparms.fprs[11]) FAILURE /* f12 */
1911 + if (a1 != *(_Decimal64 *)&gparms.fprs[0]) FAILURE /* f1 */
1912 + if (a2 != *(_Decimal128 *)&gparms.fprs[1]) FAILURE /* f2 & f3 */
1913 + if (a3 != *(_Decimal64 *)&gparms.fprs[3]) FAILURE /* f4 */
1914 + if (a4 != *(_Decimal128 *)&gparms.fprs[5]) FAILURE /* f6 & f7 */
1915 + if (a5 != *(_Decimal64 *)&gparms.fprs[7]) FAILURE /* f8 */
1916 + if (a6 != *(_Decimal128 *)&gparms.fprs[9]) FAILURE /* f10 & f11 */
1917 + if (a7 != *(_Decimal64 *)&gparms.fprs[11]) FAILURE /* f12 */
1918 if (a8 != *(_Decimal128 *)&sp->slot[10]) FAILURE
1919 if (a9 != *(_Decimal64 *)&sp->slot[12]) FAILURE
1920 if (a10 != *(_Decimal128 *)&sp->slot[13]) FAILURE
1923 +extern void func4_asm (_Decimal128, _Decimal64, _Decimal128, _Decimal64,
1924 + _Decimal128, _Decimal64, _Decimal128, _Decimal64);
1928 void __attribute__ ((noinline))
1929 func4 (_Decimal128 a1, _Decimal64 a2, _Decimal128 a3, _Decimal64 a4,
1930 _Decimal128 a5, _Decimal64 a6, _Decimal128 a7, _Decimal64 a8)
1932 - reg_parms_t lparms;
1935 - save_parms (lparms);
1936 sp = __builtin_frame_address (0);
1939 - if (a1 != *(_Decimal128 *)&lparms.fprs[1]) FAILURE /* f2 & f3 */
1940 - if (a2 != *(_Decimal64 *)&lparms.fprs[3]) FAILURE /* f4 */
1941 - if (a3 != *(_Decimal128 *)&lparms.fprs[5]) FAILURE /* f6 & f7 */
1942 - if (a4 != *(_Decimal64 *)&lparms.fprs[7]) FAILURE /* f8 */
1943 - if (a5 != *(_Decimal128 *)&lparms.fprs[9]) FAILURE /* f10 & f11 */
1944 - if (a6 != *(_Decimal64 *)&lparms.fprs[11]) FAILURE /* f12 */
1945 + if (a1 != *(_Decimal128 *)&gparms.fprs[1]) FAILURE /* f2 & f3 */
1946 + if (a2 != *(_Decimal64 *)&gparms.fprs[3]) FAILURE /* f4 */
1947 + if (a3 != *(_Decimal128 *)&gparms.fprs[5]) FAILURE /* f6 & f7 */
1948 + if (a4 != *(_Decimal64 *)&gparms.fprs[7]) FAILURE /* f8 */
1949 + if (a5 != *(_Decimal128 *)&gparms.fprs[9]) FAILURE /* f10 & f11 */
1950 + if (a6 != *(_Decimal64 *)&gparms.fprs[11]) FAILURE /* f12 */
1951 if (a7 != *(_Decimal128 *)&sp->slot[9]) FAILURE
1952 if (a8 != *(_Decimal64 *)&sp->slot[11]) FAILURE
1955 +extern void func5_asm (_Decimal32, _Decimal32, _Decimal32, _Decimal32,
1956 + _Decimal32, _Decimal32, _Decimal32, _Decimal32,
1957 + _Decimal32, _Decimal32, _Decimal32, _Decimal32,
1958 + _Decimal32, _Decimal32, _Decimal32, _Decimal32);
1962 void __attribute__ ((noinline))
1963 func5 (_Decimal32 a1, _Decimal32 a2, _Decimal32 a3, _Decimal32 a4,
1964 _Decimal32 a5, _Decimal32 a6, _Decimal32 a7, _Decimal32 a8,
1965 _Decimal32 a9, _Decimal32 a10, _Decimal32 a11, _Decimal32 a12,
1966 _Decimal32 a13, _Decimal32 a14, _Decimal32 a15, _Decimal32 a16)
1968 - reg_parms_t lparms;
1971 - save_parms (lparms);
1972 sp = __builtin_frame_address (0);
1975 /* _Decimal32 is passed in the lower half of an FPR or parameter slot. */
1976 - if (a1 != ((d32parm_t *)&lparms.fprs[0])->d) FAILURE /* f1 */
1977 - if (a2 != ((d32parm_t *)&lparms.fprs[1])->d) FAILURE /* f2 */
1978 - if (a3 != ((d32parm_t *)&lparms.fprs[2])->d) FAILURE /* f3 */
1979 - if (a4 != ((d32parm_t *)&lparms.fprs[3])->d) FAILURE /* f4 */
1980 - if (a5 != ((d32parm_t *)&lparms.fprs[4])->d) FAILURE /* f5 */
1981 - if (a6 != ((d32parm_t *)&lparms.fprs[5])->d) FAILURE /* f6 */
1982 - if (a7 != ((d32parm_t *)&lparms.fprs[6])->d) FAILURE /* f7 */
1983 - if (a8 != ((d32parm_t *)&lparms.fprs[7])->d) FAILURE /* f8 */
1984 - if (a9 != ((d32parm_t *)&lparms.fprs[8])->d) FAILURE /* f9 */
1985 - if (a10 != ((d32parm_t *)&lparms.fprs[9])->d) FAILURE /* f10 */
1986 - if (a11 != ((d32parm_t *)&lparms.fprs[10])->d) FAILURE /* f11 */
1987 - if (a12 != ((d32parm_t *)&lparms.fprs[11])->d) FAILURE /* f12 */
1988 - if (a13 != ((d32parm_t *)&lparms.fprs[12])->d) FAILURE /* f13 */
1989 + if (a1 != ((d32parm_t *)&gparms.fprs[0])->d) FAILURE /* f1 */
1990 + if (a2 != ((d32parm_t *)&gparms.fprs[1])->d) FAILURE /* f2 */
1991 + if (a3 != ((d32parm_t *)&gparms.fprs[2])->d) FAILURE /* f3 */
1992 + if (a4 != ((d32parm_t *)&gparms.fprs[3])->d) FAILURE /* f4 */
1993 + if (a5 != ((d32parm_t *)&gparms.fprs[4])->d) FAILURE /* f5 */
1994 + if (a6 != ((d32parm_t *)&gparms.fprs[5])->d) FAILURE /* f6 */
1995 + if (a7 != ((d32parm_t *)&gparms.fprs[6])->d) FAILURE /* f7 */
1996 + if (a8 != ((d32parm_t *)&gparms.fprs[7])->d) FAILURE /* f8 */
1997 + if (a9 != ((d32parm_t *)&gparms.fprs[8])->d) FAILURE /* f9 */
1998 + if (a10 != ((d32parm_t *)&gparms.fprs[9])->d) FAILURE /* f10 */
1999 + if (a11 != ((d32parm_t *)&gparms.fprs[10])->d) FAILURE /* f11 */
2000 + if (a12 != ((d32parm_t *)&gparms.fprs[11])->d) FAILURE /* f12 */
2001 + if (a13 != ((d32parm_t *)&gparms.fprs[12])->d) FAILURE /* f13 */
2002 if (a14 != ((d32parm_t *)&sp->slot[13])->d) FAILURE
2003 if (a15 != ((d32parm_t *)&sp->slot[14])->d) FAILURE
2004 if (a16 != ((d32parm_t *)&sp->slot[15])->d) FAILURE
2007 +extern void func6_asm (_Decimal32, _Decimal64, _Decimal128,
2008 + _Decimal32, _Decimal64, _Decimal128,
2009 + _Decimal32, _Decimal64, _Decimal128,
2010 + _Decimal32, _Decimal64, _Decimal128);
2014 void __attribute__ ((noinline))
2015 func6 (_Decimal32 a1, _Decimal64 a2, _Decimal128 a3,
2016 _Decimal32 a4, _Decimal64 a5, _Decimal128 a6,
2017 _Decimal32 a7, _Decimal64 a8, _Decimal128 a9,
2018 _Decimal32 a10, _Decimal64 a11, _Decimal128 a12)
2020 - reg_parms_t lparms;
2023 - save_parms (lparms);
2024 sp = __builtin_frame_address (0);
2027 - if (a1 != ((d32parm_t *)&lparms.fprs[0])->d) FAILURE /* f1 */
2028 - if (a2 != *(_Decimal64 *)&lparms.fprs[1]) FAILURE /* f2 */
2029 - if (a3 != *(_Decimal128 *)&lparms.fprs[3]) FAILURE /* f4 & f5 */
2030 - if (a4 != ((d32parm_t *)&lparms.fprs[5])->d) FAILURE /* f6 */
2031 - if (a5 != *(_Decimal64 *)&lparms.fprs[6]) FAILURE /* f7 */
2032 - if (a6 != *(_Decimal128 *)&lparms.fprs[7]) FAILURE /* f8 & f9 */
2033 - if (a7 != ((d32parm_t *)&lparms.fprs[9])->d) FAILURE /* f10 */
2034 - if (a8 != *(_Decimal64 *)&lparms.fprs[10]) FAILURE /* f11 */
2035 - if (a9 != *(_Decimal128 *)&lparms.fprs[11]) FAILURE /* f12 & f13 */
2036 + if (a1 != ((d32parm_t *)&gparms.fprs[0])->d) FAILURE /* f1 */
2037 + if (a2 != *(_Decimal64 *)&gparms.fprs[1]) FAILURE /* f2 */
2038 + if (a3 != *(_Decimal128 *)&gparms.fprs[3]) FAILURE /* f4 & f5 */
2039 + if (a4 != ((d32parm_t *)&gparms.fprs[5])->d) FAILURE /* f6 */
2040 + if (a5 != *(_Decimal64 *)&gparms.fprs[6]) FAILURE /* f7 */
2041 + if (a6 != *(_Decimal128 *)&gparms.fprs[7]) FAILURE /* f8 & f9 */
2042 + if (a7 != ((d32parm_t *)&gparms.fprs[9])->d) FAILURE /* f10 */
2043 + if (a8 != *(_Decimal64 *)&gparms.fprs[10]) FAILURE /* f11 */
2044 + if (a9 != *(_Decimal128 *)&gparms.fprs[11]) FAILURE /* f12 & f13 */
2045 if (a10 != ((d32parm_t *)&sp->slot[12])->d) FAILURE
2046 if (a11 != *(_Decimal64 *)&sp->slot[13]) FAILURE
2048 @@ -292,23 +305,23 @@
2052 - func0 (1.5, 2.5, 3.5, 4.5, 5.5, 6.5, 7.5, 8.5, 9.5, 10.5, 11.5, 12.5, 13.5,
2053 - 14.5, 15.2dd, 16.2dl, 17.2dd);
2054 - func1 (101.5, 102.5, 103.5, 104.5, 105.5, 106.5, 107.5, 108.5, 109.5,
2055 - 110.5, 111.5, 112.5, 113.5, 114.2dd);
2056 - func2 (201.5, 202.5, 203.5, 204.5, 205.5, 206.5, 207.5, 208.5, 209.5,
2057 - 210.5, 211.5, 212.5, 213.2dd);
2058 - func3 (301.2dd, 302.2dl, 303.2dd, 304.2dl, 305.2dd, 306.2dl, 307.2dd,
2059 - 308.2dl, 309.2dd, 310.2dl);
2060 - func4 (401.2dl, 402.2dd, 403.2dl, 404.2dd, 405.2dl, 406.2dd, 407.2dl,
2062 + func0_asm (1.5, 2.5, 3.5, 4.5, 5.5, 6.5, 7.5, 8.5, 9.5, 10.5, 11.5, 12.5, 13.5,
2063 + 14.5, 15.2dd, 16.2dl, 17.2dd);
2064 + func1_asm (101.5, 102.5, 103.5, 104.5, 105.5, 106.5, 107.5, 108.5, 109.5,
2065 + 110.5, 111.5, 112.5, 113.5, 114.2dd);
2066 + func2_asm (201.5, 202.5, 203.5, 204.5, 205.5, 206.5, 207.5, 208.5, 209.5,
2067 + 210.5, 211.5, 212.5, 213.2dd);
2068 + func3_asm (301.2dd, 302.2dl, 303.2dd, 304.2dl, 305.2dd, 306.2dl, 307.2dd,
2069 + 308.2dl, 309.2dd, 310.2dl);
2070 + func4_asm (401.2dl, 402.2dd, 403.2dl, 404.2dd, 405.2dl, 406.2dd, 407.2dl,
2073 /* _Decimal32 doesn't yet follow the ABI; enable this when it does. */
2074 - func5 (501.2df, 502.2df, 503.2df, 504.2df, 505.2df, 506.2df, 507.2df,
2075 - 508.2df, 509.2df, 510.2df, 511.2df, 512.2df, 513.2df, 514.2df,
2076 - 515.2df, 516.2df);
2077 - func6 (601.2df, 602.2dd, 603.2dl, 604.2df, 605.2dd, 606.2dl,
2078 - 607.2df, 608.2dd, 609.2dl, 610.2df, 611.2dd, 612.2dl);
2079 + func5_asm (501.2df, 502.2df, 503.2df, 504.2df, 505.2df, 506.2df, 507.2df,
2080 + 508.2df, 509.2df, 510.2df, 511.2df, 512.2df, 513.2df, 514.2df,
2081 + 515.2df, 516.2df);
2082 + func6_asm (601.2df, 602.2dd, 603.2dl, 604.2df, 605.2dd, 606.2dl,
2083 + 607.2df, 608.2dd, 609.2dl, 610.2df, 611.2dd, 612.2dl);
2087 Index: gcc/testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c
2088 ===================================================================
2089 --- gcc/testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c (.../tags/gcc_4_5_2_release) (wersja 170084)
2090 +++ gcc/testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c (.../branches/gcc-4_5-branch) (wersja 170084)
2096 -/* Testcase could break on future gcc's, if parameter regs
2097 - are changed before this asm. */
2099 -#define save_parms(lparms) \
2100 - asm volatile ("lis 11,gparms@ha\n\t" \
2101 - "la 11,gparms@l(11)\n\t" \
2102 - "st 3,0(11)\n\t" \
2103 - "st 4,4(11)\n\t" \
2104 - "st 5,8(11)\n\t" \
2105 - "st 6,12(11)\n\t" \
2106 - "st 7,16(11)\n\t" \
2107 - "st 8,20(11)\n\t" \
2108 - "st 9,24(11)\n\t" \
2109 - "st 10,28(11)\n\t" \
2110 - "stfd 1,32(11)\n\t" \
2111 - "stfd 2,40(11)\n\t" \
2112 - "stfd 3,48(11)\n\t" \
2113 - "stfd 4,56(11)\n\t" \
2114 - "stfd 5,64(11)\n\t" \
2115 - "stfd 6,72(11)\n\t" \
2116 - "stfd 7,80(11)\n\t" \
2117 - "stfd 8,88(11)\n\t":::"11", "memory"); \
2122 struct sf *backchain;
2123 @@ -62,115 +37,159 @@
2124 unsigned int slot[200];
2127 +/* Wrapper to save the GPRs and FPRs and then jump to the real function. */
2128 +#define WRAPPER(NAME) \
2129 +__asm__ ("\t.globl\t" #NAME "_asm\n\t" \
2131 + ".type " #NAME "_asm, @function\n" \
2132 + #NAME "_asm:\n\t" \
2133 + "lis 11,gparms@ha\n\t" \
2134 + "la 11,gparms@l(11)\n\t" \
2135 + "st 3,0(11)\n\t" \
2136 + "st 4,4(11)\n\t" \
2137 + "st 5,8(11)\n\t" \
2138 + "st 6,12(11)\n\t" \
2139 + "st 7,16(11)\n\t" \
2140 + "st 8,20(11)\n\t" \
2141 + "st 9,24(11)\n\t" \
2142 + "st 10,28(11)\n\t" \
2143 + "stfd 1,32(11)\n\t" \
2144 + "stfd 2,40(11)\n\t" \
2145 + "stfd 3,48(11)\n\t" \
2146 + "stfd 4,56(11)\n\t" \
2147 + "stfd 5,64(11)\n\t" \
2148 + "stfd 6,72(11)\n\t" \
2149 + "stfd 7,80(11)\n\t" \
2150 + "stfd 8,88(11)\n\t" \
2151 + "b " #NAME "\n\t" \
2152 + ".size " #NAME ",.-" #NAME "\n")
2154 /* Fill up floating point registers with double arguments, forcing
2155 decimal float arguments into the parameter save area. */
2156 +extern void func0_asm (double, double, double, double, double,
2157 + double, double, double, _Decimal64, _Decimal128);
2161 void __attribute__ ((noinline))
2162 func0 (double a1, double a2, double a3, double a4, double a5,
2163 double a6, double a7, double a8, _Decimal64 a9, _Decimal128 a10)
2165 - reg_parms_t lparms;
2168 - save_parms (lparms);
2169 sp = __builtin_frame_address (0);
2172 - if (a1 != lparms.fprs[0]) FAILURE
2173 - if (a2 != lparms.fprs[1]) FAILURE
2174 - if (a3 != lparms.fprs[2]) FAILURE
2175 - if (a4 != lparms.fprs[3]) FAILURE
2176 - if (a5 != lparms.fprs[4]) FAILURE
2177 - if (a6 != lparms.fprs[5]) FAILURE
2178 - if (a7 != lparms.fprs[6]) FAILURE
2179 - if (a8 != lparms.fprs[7]) FAILURE
2180 + if (a1 != gparms.fprs[0]) FAILURE
2181 + if (a2 != gparms.fprs[1]) FAILURE
2182 + if (a3 != gparms.fprs[2]) FAILURE
2183 + if (a4 != gparms.fprs[3]) FAILURE
2184 + if (a5 != gparms.fprs[4]) FAILURE
2185 + if (a6 != gparms.fprs[5]) FAILURE
2186 + if (a7 != gparms.fprs[6]) FAILURE
2187 + if (a8 != gparms.fprs[7]) FAILURE
2188 if (a9 != *(_Decimal64 *)&sp->slot[0]) FAILURE
2189 if (a10 != *(_Decimal128 *)&sp->slot[2]) FAILURE
2192 /* Alternate 64-bit and 128-bit decimal float arguments, checking that
2193 _Decimal128 is always passed in even/odd register pairs. */
2194 +extern void func1_asm (_Decimal64, _Decimal128, _Decimal64, _Decimal128,
2195 + _Decimal64, _Decimal128, _Decimal64, _Decimal128);
2199 void __attribute__ ((noinline))
2200 func1 (_Decimal64 a1, _Decimal128 a2, _Decimal64 a3, _Decimal128 a4,
2201 _Decimal64 a5, _Decimal128 a6, _Decimal64 a7, _Decimal128 a8)
2203 - reg_parms_t lparms;
2206 - save_parms (lparms);
2207 sp = __builtin_frame_address (0);
2210 - if (a1 != *(_Decimal64 *)&lparms.fprs[0]) FAILURE /* f1 */
2211 - if (a2 != *(_Decimal128 *)&lparms.fprs[1]) FAILURE /* f2 & f3 */
2212 - if (a3 != *(_Decimal64 *)&lparms.fprs[3]) FAILURE /* f4 */
2213 - if (a4 != *(_Decimal128 *)&lparms.fprs[5]) FAILURE /* f6 & f7 */
2214 - if (a5 != *(_Decimal64 *)&lparms.fprs[7]) FAILURE /* f8 */
2215 + if (a1 != *(_Decimal64 *)&gparms.fprs[0]) FAILURE /* f1 */
2216 + if (a2 != *(_Decimal128 *)&gparms.fprs[1]) FAILURE /* f2 & f3 */
2217 + if (a3 != *(_Decimal64 *)&gparms.fprs[3]) FAILURE /* f4 */
2218 + if (a4 != *(_Decimal128 *)&gparms.fprs[5]) FAILURE /* f6 & f7 */
2219 + if (a5 != *(_Decimal64 *)&gparms.fprs[7]) FAILURE /* f8 */
2220 if (a6 != *(_Decimal128 *)&sp->slot[0]) FAILURE
2221 if (a7 != *(_Decimal64 *)&sp->slot[4]) FAILURE
2222 if (a8 != *(_Decimal128 *)&sp->slot[6]) FAILURE
2225 +extern void func2_asm (_Decimal128, _Decimal64, _Decimal128, _Decimal64,
2226 + _Decimal128, _Decimal64, _Decimal128, _Decimal64);
2230 void __attribute__ ((noinline))
2231 func2 (_Decimal128 a1, _Decimal64 a2, _Decimal128 a3, _Decimal64 a4,
2232 _Decimal128 a5, _Decimal64 a6, _Decimal128 a7, _Decimal64 a8)
2234 - reg_parms_t lparms;
2237 - save_parms (lparms);
2238 sp = __builtin_frame_address (0);
2241 - if (a1 != *(_Decimal128 *)&lparms.fprs[1]) FAILURE /* f2 & f3 */
2242 - if (a2 != *(_Decimal64 *)&lparms.fprs[3]) FAILURE /* f4 */
2243 - if (a3 != *(_Decimal128 *)&lparms.fprs[5]) FAILURE /* f6 & f7 */
2244 - if (a4 != *(_Decimal64 *)&lparms.fprs[7]) FAILURE /* f8 */
2245 + if (a1 != *(_Decimal128 *)&gparms.fprs[1]) FAILURE /* f2 & f3 */
2246 + if (a2 != *(_Decimal64 *)&gparms.fprs[3]) FAILURE /* f4 */
2247 + if (a3 != *(_Decimal128 *)&gparms.fprs[5]) FAILURE /* f6 & f7 */
2248 + if (a4 != *(_Decimal64 *)&gparms.fprs[7]) FAILURE /* f8 */
2249 if (a5 != *(_Decimal128 *)&sp->slot[0]) FAILURE
2250 if (a6 != *(_Decimal64 *)&sp->slot[4]) FAILURE
2251 if (a7 != *(_Decimal128 *)&sp->slot[6]) FAILURE
2252 if (a8 != *(_Decimal64 *)&sp->slot[10]) FAILURE
2255 +extern void func3_asm (_Decimal64, _Decimal128, _Decimal64, _Decimal128,
2260 void __attribute__ ((noinline))
2261 func3 (_Decimal64 a1, _Decimal128 a2, _Decimal64 a3, _Decimal128 a4,
2264 - reg_parms_t lparms;
2267 - save_parms (lparms);
2268 sp = __builtin_frame_address (0);
2271 - if (a1 != *(_Decimal64 *)&lparms.fprs[0]) FAILURE /* f1 */
2272 - if (a2 != *(_Decimal128 *)&lparms.fprs[1]) FAILURE /* f2 & f3 */
2273 - if (a3 != *(_Decimal64 *)&lparms.fprs[3]) FAILURE /* f4 */
2274 - if (a4 != *(_Decimal128 *)&lparms.fprs[5]) FAILURE /* f6 & f7 */
2275 + if (a1 != *(_Decimal64 *)&gparms.fprs[0]) FAILURE /* f1 */
2276 + if (a2 != *(_Decimal128 *)&gparms.fprs[1]) FAILURE /* f2 & f3 */
2277 + if (a3 != *(_Decimal64 *)&gparms.fprs[3]) FAILURE /* f4 */
2278 + if (a4 != *(_Decimal128 *)&gparms.fprs[5]) FAILURE /* f6 & f7 */
2279 if (a5 != *(_Decimal128 *)&sp->slot[0]) FAILURE
2282 +extern void func4_asm (_Decimal32, _Decimal32, _Decimal32, _Decimal32,
2283 + _Decimal32, _Decimal32, _Decimal32, _Decimal32,
2284 + _Decimal32, _Decimal32, _Decimal32, _Decimal32,
2285 + _Decimal32, _Decimal32, _Decimal32, _Decimal32);
2289 void __attribute__ ((noinline))
2290 func4 (_Decimal32 a1, _Decimal32 a2, _Decimal32 a3, _Decimal32 a4,
2291 _Decimal32 a5, _Decimal32 a6, _Decimal32 a7, _Decimal32 a8,
2292 _Decimal32 a9, _Decimal32 a10, _Decimal32 a11, _Decimal32 a12,
2293 _Decimal32 a13, _Decimal32 a14, _Decimal32 a15, _Decimal32 a16)
2295 - reg_parms_t lparms;
2298 - save_parms (lparms);
2299 sp = __builtin_frame_address (0);
2302 /* _Decimal32 is passed in the lower half of an FPR, or in parameter slot. */
2303 - if (a1 != ((d32parm_t *)&lparms.fprs[0])->d) FAILURE /* f1 */
2304 - if (a2 != ((d32parm_t *)&lparms.fprs[1])->d) FAILURE /* f2 */
2305 - if (a3 != ((d32parm_t *)&lparms.fprs[2])->d) FAILURE /* f3 */
2306 - if (a4 != ((d32parm_t *)&lparms.fprs[3])->d) FAILURE /* f4 */
2307 - if (a5 != ((d32parm_t *)&lparms.fprs[4])->d) FAILURE /* f5 */
2308 - if (a6 != ((d32parm_t *)&lparms.fprs[5])->d) FAILURE /* f6 */
2309 - if (a7 != ((d32parm_t *)&lparms.fprs[6])->d) FAILURE /* f7 */
2310 - if (a8 != ((d32parm_t *)&lparms.fprs[7])->d) FAILURE /* f8 */
2311 + if (a1 != ((d32parm_t *)&gparms.fprs[0])->d) FAILURE /* f1 */
2312 + if (a2 != ((d32parm_t *)&gparms.fprs[1])->d) FAILURE /* f2 */
2313 + if (a3 != ((d32parm_t *)&gparms.fprs[2])->d) FAILURE /* f3 */
2314 + if (a4 != ((d32parm_t *)&gparms.fprs[3])->d) FAILURE /* f4 */
2315 + if (a5 != ((d32parm_t *)&gparms.fprs[4])->d) FAILURE /* f5 */
2316 + if (a6 != ((d32parm_t *)&gparms.fprs[5])->d) FAILURE /* f6 */
2317 + if (a7 != ((d32parm_t *)&gparms.fprs[6])->d) FAILURE /* f7 */
2318 + if (a8 != ((d32parm_t *)&gparms.fprs[7])->d) FAILURE /* f8 */
2319 if (a9 != *(_Decimal32 *)&sp->slot[0]) FAILURE
2320 if (a10 != *(_Decimal32 *)&sp->slot[1]) FAILURE
2321 if (a11 != *(_Decimal32 *)&sp->slot[2]) FAILURE
2322 @@ -181,24 +200,29 @@
2323 if (a16 != *(_Decimal32 *)&sp->slot[7]) FAILURE
2326 +extern void func5_asm (_Decimal32, _Decimal64, _Decimal128,
2327 + _Decimal32, _Decimal64, _Decimal128,
2328 + _Decimal32, _Decimal64, _Decimal128,
2329 + _Decimal32, _Decimal64, _Decimal128);
2333 void __attribute__ ((noinline))
2334 func5 (_Decimal32 a1, _Decimal64 a2, _Decimal128 a3,
2335 _Decimal32 a4, _Decimal64 a5, _Decimal128 a6,
2336 _Decimal32 a7, _Decimal64 a8, _Decimal128 a9,
2337 _Decimal32 a10, _Decimal64 a11, _Decimal128 a12)
2339 - reg_parms_t lparms;
2342 - save_parms (lparms);
2343 sp = __builtin_frame_address (0);
2346 - if (a1 != ((d32parm_t *)&lparms.fprs[0])->d) FAILURE /* f1 */
2347 - if (a2 != *(_Decimal64 *)&lparms.fprs[1]) FAILURE /* f2 */
2348 - if (a3 != *(_Decimal128 *)&lparms.fprs[3]) FAILURE /* f4 & f5 */
2349 - if (a4 != ((d32parm_t *)&lparms.fprs[5])->d) FAILURE /* f6 */
2350 - if (a5 != *(_Decimal64 *)&lparms.fprs[6]) FAILURE /* f7 */
2351 + if (a1 != ((d32parm_t *)&gparms.fprs[0])->d) FAILURE /* f1 */
2352 + if (a2 != *(_Decimal64 *)&gparms.fprs[1]) FAILURE /* f2 */
2353 + if (a3 != *(_Decimal128 *)&gparms.fprs[3]) FAILURE /* f4 & f5 */
2354 + if (a4 != ((d32parm_t *)&gparms.fprs[5])->d) FAILURE /* f6 */
2355 + if (a5 != *(_Decimal64 *)&gparms.fprs[6]) FAILURE /* f7 */
2357 if (a6 != *(_Decimal128 *)&sp->slot[0]) FAILURE
2358 if (a7 != *(_Decimal32 *)&sp->slot[4]) FAILURE
2359 @@ -212,15 +236,15 @@
2363 - func0 (1., 2., 3., 4., 5., 6., 7., 8., 9.dd, 10.dl);
2364 - func1 (1.dd, 2.dl, 3.dd, 4.dl, 5.dd, 6.dl, 7.dd, 8.dl);
2365 - func2 (1.dl, 2.dd, 3.dl, 4.dd, 5.dl, 6.dd, 7.dl, 8.dd);
2366 - func3 (1.dd, 2.dl, 3.dd, 4.dl, 5.dl);
2367 - func4 (501.2df, 502.2df, 503.2df, 504.2df, 505.2df, 506.2df, 507.2df,
2368 - 508.2df, 509.2df, 510.2df, 511.2df, 512.2df, 513.2df, 514.2df,
2369 - 515.2df, 516.2df);
2370 - func5 (601.2df, 602.2dd, 603.2dl, 604.2df, 605.2dd, 606.2dl,
2371 - 607.2df, 608.2dd, 609.2dl, 610.2df, 611.2dd, 612.2dl);
2372 + func0_asm (1., 2., 3., 4., 5., 6., 7., 8., 9.dd, 10.dl);
2373 + func1_asm (1.dd, 2.dl, 3.dd, 4.dl, 5.dd, 6.dl, 7.dd, 8.dl);
2374 + func2_asm (1.dl, 2.dd, 3.dl, 4.dd, 5.dl, 6.dd, 7.dl, 8.dd);
2375 + func3_asm (1.dd, 2.dl, 3.dd, 4.dl, 5.dl);
2376 + func4_asm (501.2df, 502.2df, 503.2df, 504.2df, 505.2df, 506.2df, 507.2df,
2377 + 508.2df, 509.2df, 510.2df, 511.2df, 512.2df, 513.2df, 514.2df,
2378 + 515.2df, 516.2df);
2379 + func5_asm (601.2df, 602.2dd, 603.2dl, 604.2df, 605.2dd, 606.2dl,
2380 + 607.2df, 608.2dd, 609.2dl, 610.2df, 611.2dd, 612.2dl);
2384 Index: gcc/testsuite/gcc.target/powerpc/avoid-indexed-addresses.c
2385 ===================================================================
2386 --- gcc/testsuite/gcc.target/powerpc/avoid-indexed-addresses.c (.../tags/gcc_4_5_2_release) (wersja 170084)
2387 +++ gcc/testsuite/gcc.target/powerpc/avoid-indexed-addresses.c (.../branches/gcc-4_5-branch) (wersja 170084)
2389 /* { dg-do compile { target { powerpc*-*-* } } } */
2390 -/* { dg-options "-O2 -mavoid-indexed-addresses" } */
2391 +/* { dg-options "-O2 -mavoid-indexed-addresses -mno-altivec -mno-vsx" } */
2393 /* { dg-final { scan-assembler-not "lbzx" } }
2395 Index: gcc/testsuite/gcc.target/i386/avx-check.h
2396 ===================================================================
2397 --- gcc/testsuite/gcc.target/i386/avx-check.h (.../tags/gcc_4_5_2_release) (wersja 170084)
2398 +++ gcc/testsuite/gcc.target/i386/avx-check.h (.../branches/gcc-4_5-branch) (wersja 170084)
2402 /* Run AVX test only if host has AVX support. */
2403 - if (ecx & bit_AVX)
2404 + if ((ecx & (bit_AVX | bit_OSXSAVE)) == (bit_AVX | bit_OSXSAVE))
2408 Index: gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-1.c
2409 ===================================================================
2410 --- gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-1.c (.../tags/gcc_4_5_2_release) (wersja 170084)
2411 +++ gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-1.c (.../branches/gcc-4_5-branch) (wersja 170084)
2414 int m[8] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3), mask_v(4), mask_v(5), mask_v(6), mask_v(7)};
2415 float s[8] = {1,2,3,4,5,6,7,8};
2419 float e [8] = {0.0};
2421 - mask.x = _mm256_loadu_ps ((float*)m);
2422 + mask.x = _mm256_loadu_si256 ((__m256i *)m);
2423 u.x = _mm256_maskload_ps (s, mask.x);
2425 for (i = 0 ; i < 8; i++)
2426 Index: gcc/testsuite/gcc.target/i386/pr46880.c
2427 ===================================================================
2428 --- gcc/testsuite/gcc.target/i386/pr46880.c (.../tags/gcc_4_5_2_release) (wersja 0)
2429 +++ gcc/testsuite/gcc.target/i386/pr46880.c (.../branches/gcc-4_5-branch) (wersja 170084)
2431 +/* PR target/46880 */
2432 +/* { dg-do run } */
2433 +/* { dg-options "-O2 -fno-strict-aliasing -msse2" } */
2434 +/* { dg-require-effective-target sse2_runtime } */
2436 +typedef double __m128d __attribute__ ((__vector_size__ (16), __may_alias__));
2437 +typedef double (*T)[2];
2439 +static __attribute__ ((noinline, noclone)) __m128d
2440 +foo (__m128d c, __m128d d)
2444 + __m128d e = { (*cp)[1], (*dp)[1] };
2451 + __m128d c = { 1.0, 2.0 };
2452 + __m128d d = { 3.0, 4.0 };
2453 + union { __m128d x; double d[2]; } u;
2455 + if (u.d[0] != 2.0 || u.d[1] != 4.0)
2456 + __builtin_abort ();
2459 Index: gcc/testsuite/gcc.target/i386/avx-vmaskmovps-1.c
2460 ===================================================================
2461 --- gcc/testsuite/gcc.target/i386/avx-vmaskmovps-1.c (.../tags/gcc_4_5_2_release) (wersja 0)
2462 +++ gcc/testsuite/gcc.target/i386/avx-vmaskmovps-1.c (.../branches/gcc-4_5-branch) (wersja 170084)
2464 +/* { dg-do run } */
2465 +/* { dg-require-effective-target avx } */
2466 +/* { dg-options "-O2 -mavx" } */
2468 +#include "avx-check.h"
2474 +#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 31)
2480 + int m[4] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3)};
2481 + float s[4] = {1,2,3,4};
2484 + float e[4] = {0.0};
2486 + mask.x = _mm_loadu_si128 ((__m128i *)m);
2487 + u.x = _mm_maskload_ps (s, mask.x);
2489 + for (i = 0 ; i < 4; i++)
2490 + e[i] = m[i] ? s[i] : 0;
2492 + if (check_union128 (u, e))
2495 Index: gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-1.c
2496 ===================================================================
2497 --- gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-1.c (.../tags/gcc_4_5_2_release) (wersja 170084)
2498 +++ gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-1.c (.../branches/gcc-4_5-branch) (wersja 170084)
2503 - long long m[8] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3)};
2504 + long long m[4] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3)};
2505 double s[4] = {1.1, 2.2, 3.3, 4.4};
2506 - union256d u, mask;
2509 double e [4] = {0.0};
2511 - mask.x = _mm256_loadu_pd ((double*)m);
2512 + mask.x = _mm256_loadu_si256 ((__m256i *)m);
2513 u.x = _mm256_maskload_pd (s, mask.x);
2515 for (i = 0 ; i < 4; i++)
2516 Index: gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-1.c
2517 ===================================================================
2518 --- gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-1.c (.../tags/gcc_4_5_2_release) (wersja 0)
2519 +++ gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-1.c (.../branches/gcc-4_5-branch) (wersja 170084)
2521 +/* { dg-do run } */
2522 +/* { dg-require-effective-target avx } */
2523 +/* { dg-options "-O2 -mavx" } */
2525 +#include "avx-check.h"
2531 +#define mask_v(pos) (((MASK & (0x1ULL << (pos))) >> (pos)) << 63)
2537 + long long m[2] = {mask_v(0), mask_v(1)};
2538 + double s[2] = {1.1, 2.2};
2541 + double e[2] = {0.0};
2543 + mask.x = _mm_loadu_si128 ((__m128i *)m);
2544 + u.x = _mm_maskload_pd (s, mask.x);
2546 + for (i = 0 ; i < 2; i++)
2547 + e[i] = m[i] ? s[i] : 0;
2549 + if (check_union128d (u, e))
2552 Index: gcc/testsuite/gcc.target/i386/pr46865-1.c
2553 ===================================================================
2554 --- gcc/testsuite/gcc.target/i386/pr46865-1.c (.../tags/gcc_4_5_2_release) (wersja 0)
2555 +++ gcc/testsuite/gcc.target/i386/pr46865-1.c (.../branches/gcc-4_5-branch) (wersja 170084)
2557 +/* PR rtl-optimization/46865 */
2558 +/* { dg-do compile } */
2559 +/* { dg-options "-O2" } */
2561 +extern unsigned long f;
2565 + asm volatile ("nop /* asmnop */\n"); \
2567 + asm volatile ("nop /* asmnop */\n");
2571 + asm volatile ("nop /* asmnop */\n" : : "i" (6) : "cx"); \
2573 + asm volatile ("nop /* asmnop */\n" : : "i" (6) : "cx");
2587 +/* { dg-final { scan-assembler-times "asmnop" 2 } } */
2588 Index: gcc/testsuite/gcc.target/i386/pr45852.c
2589 ===================================================================
2590 --- gcc/testsuite/gcc.target/i386/pr45852.c (.../tags/gcc_4_5_2_release) (wersja 0)
2591 +++ gcc/testsuite/gcc.target/i386/pr45852.c (.../branches/gcc-4_5-branch) (wersja 170084)
2593 +/* PR middle-end/45852 */
2594 +/* { dg-options "-O2 -mcmodel=small" } */
2595 +/* { dg-do compile { target { { i?86-*-linux* x86_64-*-linux* } && lp64 } } } */
2596 +/* { dg-require-visibility "" } */
2598 +struct S { int s; };
2600 +volatile struct S globvar __attribute__((visibility ("hidden"))) = { -6 };
2605 + globvar = globvar;
2608 +/* { dg-final { scan-assembler-times "globvar.%?rip" 2 } } */
2609 Index: gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-2.c
2610 ===================================================================
2611 --- gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-2.c (.../tags/gcc_4_5_2_release) (wersja 170084)
2612 +++ gcc/testsuite/gcc.target/i386/avx-vmaskmovps-256-2.c (.../branches/gcc-4_5-branch) (wersja 170084)
2615 int m[8] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3), mask_v(4), mask_v(5), mask_v(6), mask_v(7)};
2616 float s[8] = {1,2,3,4,5,6,7,8};
2617 - union256 src, mask;
2620 float e [8] = {0.0};
2621 float d [8] = {0.0};
2623 src.x = _mm256_loadu_ps (s);
2624 - mask.x = _mm256_loadu_ps ((float *)m);
2625 + mask.x = _mm256_loadu_si256 ((__m256i *)m);
2626 _mm256_maskstore_ps (d, mask.x, src.x);
2628 for (i = 0 ; i < 8; i++)
2629 Index: gcc/testsuite/gcc.target/i386/avx-vmaskmovps-2.c
2630 ===================================================================
2631 --- gcc/testsuite/gcc.target/i386/avx-vmaskmovps-2.c (.../tags/gcc_4_5_2_release) (wersja 0)
2632 +++ gcc/testsuite/gcc.target/i386/avx-vmaskmovps-2.c (.../branches/gcc-4_5-branch) (wersja 170084)
2634 +/* { dg-do run } */
2635 +/* { dg-require-effective-target avx } */
2636 +/* { dg-options "-O2 -mavx" } */
2638 +#include "avx-check.h"
2644 +#define mask_v(pos) (((MASK & (0x1 << (pos))) >> (pos)) << 31)
2650 + int m[4] = {mask_v(0), mask_v(1), mask_v(2), mask_v(3)};
2651 + float s[4] = {1,2,3,4};
2654 + float e[4] = {0.0};
2655 + float d[4] = {0.0};
2657 + src.x = _mm_loadu_ps (s);
2658 + mask.x = _mm_loadu_si128 ((__m128i *)m);
2659 + _mm_maskstore_ps (d, mask.x, src.x);
2661 + for (i = 0 ; i < 4; i++)
2662 + e[i] = m[i] ? s[i] : 0;
2664 + if (checkVf (d, e, 4))
2667 Index: gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-2.c
2668 ===================================================================
2669 --- gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-2.c (.../tags/gcc_4_5_2_release) (wersja 170084)
2670 +++ gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-256-2.c (.../branches/gcc-4_5-branch) (wersja 170084)
2672 double s[4] = {1.1, 2.2, 3.3, 4.4};
2673 double e [4] = {0.0};
2674 double d [4] = {0.0};
2675 - union256d src, mask;
2679 src.x = _mm256_loadu_pd (s);
2680 - mask.x = _mm256_loadu_pd ((double*)m);
2681 + mask.x = _mm256_loadu_si256 ((__m256i *)m);
2682 _mm256_maskstore_pd (d, mask.x, src.x);
2684 for (i = 0 ; i < 4; i++)
2685 Index: gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-2.c
2686 ===================================================================
2687 --- gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-2.c (.../tags/gcc_4_5_2_release) (wersja 0)
2688 +++ gcc/testsuite/gcc.target/i386/avx-vmaskmovpd-2.c (.../branches/gcc-4_5-branch) (wersja 170084)
2690 +/* { dg-do run } */
2691 +/* { dg-require-effective-target avx } */
2692 +/* { dg-options "-O2 -mavx" } */
2694 +#include "avx-check.h"
2700 +#define mask_v(pos) (((MASK & (0x1ULL << (pos))) >> (pos)) << 63)
2706 + long long m[2] = {mask_v(0), mask_v(1)};
2707 + double s[2] = {1.1, 2.2};
2708 + double e[2] = {0.0};
2709 + double d[2] = {0.0};
2713 + src.x = _mm_loadu_pd (s);
2714 + mask.x = _mm_loadu_si128 ((__m128i *)m);
2715 + _mm_maskstore_pd (d, mask.x, src.x);
2717 + for (i = 0 ; i < 2; i++)
2718 + e[i] = m[i] ? s[i] : 0;
2720 + if (checkVd (d, e, 2))
2723 Index: gcc/testsuite/gcc.target/i386/pr46865-2.c
2724 ===================================================================
2725 --- gcc/testsuite/gcc.target/i386/pr46865-2.c (.../tags/gcc_4_5_2_release) (wersja 0)
2726 +++ gcc/testsuite/gcc.target/i386/pr46865-2.c (.../branches/gcc-4_5-branch) (wersja 170084)
2728 +/* PR rtl-optimization/46865 */
2729 +/* { dg-do compile } */
2730 +/* { dg-options "-O2 -save-temps" } */
2732 +extern unsigned long f;
2736 + asm volatile ("nop /* asmnop */\n"); \
2738 + asm volatile ("nop /* asmnop */\n");
2742 + asm volatile ("nop /* asmnop */\n" : : "i" (6) : "cx"); \
2744 + asm volatile ("nop /* asmnop */\n" : : "i" (6) : "cx");
2758 +/* { dg-final { scan-assembler-times "asmnop" 2 } } */
2759 +/* { dg-final { cleanup-saved-temps } } */
2760 Index: gcc/testsuite/gcc.target/mips/save-restore-1.c
2761 ===================================================================
2762 --- gcc/testsuite/gcc.target/mips/save-restore-1.c (.../tags/gcc_4_5_2_release) (wersja 170084)
2763 +++ gcc/testsuite/gcc.target/mips/save-restore-1.c (.../branches/gcc-4_5-branch) (wersja 170084)
2765 /* Check that we can use the save instruction to save varargs. */
2766 /* { dg-options "(-mips16) isa_rev>=1 -mabi=32 -O2" } */
2767 +/* { dg-skip-if "PR target/46610" { mips-sgi-irix6* } } */
2771 Index: gcc/testsuite/gcc.target/mips/save-restore-3.c
2772 ===================================================================
2773 --- gcc/testsuite/gcc.target/mips/save-restore-3.c (.../tags/gcc_4_5_2_release) (wersja 170084)
2774 +++ gcc/testsuite/gcc.target/mips/save-restore-3.c (.../branches/gcc-4_5-branch) (wersja 170084)
2776 /* Check that we can use the save instruction to save spilled arguments
2777 when the argument save area is out of range of a direct load or store. */
2778 /* { dg-options "(-mips16) isa_rev>=1 -mabi=32 -O2" } */
2779 +/* { dg-skip-if "PR target/46610" { mips-sgi-irix6* } } */
2783 Index: gcc/testsuite/gcc.target/mips/save-restore-4.c
2784 ===================================================================
2785 --- gcc/testsuite/gcc.target/mips/save-restore-4.c (.../tags/gcc_4_5_2_release) (wersja 170084)
2786 +++ gcc/testsuite/gcc.target/mips/save-restore-4.c (.../branches/gcc-4_5-branch) (wersja 170084)
2788 /* Check that we can use the save instruction to save $16, $17 and $31. */
2789 /* { dg-options "(-mips16) isa_rev>=1 -mabi=32 -O2" } */
2790 +/* { dg-skip-if "PR target/46610" { mips-sgi-irix6* } } */
2794 Index: gcc/testsuite/gcc.target/mips/save-restore-5.c
2795 ===================================================================
2796 --- gcc/testsuite/gcc.target/mips/save-restore-5.c (.../tags/gcc_4_5_2_release) (wersja 170084)
2797 +++ gcc/testsuite/gcc.target/mips/save-restore-5.c (.../branches/gcc-4_5-branch) (wersja 170084)
2799 /* Check that we don't try to save the same register twice. */
2800 /* { dg-options "(-mips16) isa_rev>=1 -mgp32 -O2" } */
2801 +/* { dg-skip-if "PR target/46610" { mips-sgi-irix6* } } */
2803 int bar (int, int, int, int);
2805 Index: gcc/testsuite/gnat.dg/opt13.adb
2806 ===================================================================
2807 --- gcc/testsuite/gnat.dg/opt13.adb (.../tags/gcc_4_5_2_release) (wersja 0)
2808 +++ gcc/testsuite/gnat.dg/opt13.adb (.../branches/gcc-4_5-branch) (wersja 170084)
2811 +-- { dg-options "-O" }
2813 +with Opt13_Pkg; use Opt13_Pkg;
2820 + raise Program_Error;
2823 Index: gcc/testsuite/gnat.dg/opt13_pkg.adb
2824 ===================================================================
2825 --- gcc/testsuite/gnat.dg/opt13_pkg.adb (.../tags/gcc_4_5_2_release) (wersja 0)
2826 +++ gcc/testsuite/gnat.dg/opt13_pkg.adb (.../branches/gcc-4_5-branch) (wersja 170084)
2828 +package body Opt13_Pkg is
2830 + subtype Index_Type is Natural range 0 .. 16;
2832 + type Arr is array (Index_Type range <>) of Integer;
2834 + type Rec is record
2835 + F1, F2, F3 : Float;
2841 + type Data (D : Index_Type) is record
2846 + Zero : constant Rec := (0.0, 0.0, 0.0, 0, False, False, 0.0);
2848 + procedure Allocate (T : out My_Type) is
2850 + T := new Data (Index_Type'last);
2853 + for I in 1 .. T.A'last loop
2859 Index: gcc/testsuite/gnat.dg/opt13_pkg.ads
2860 ===================================================================
2861 --- gcc/testsuite/gnat.dg/opt13_pkg.ads (.../tags/gcc_4_5_2_release) (wersja 0)
2862 +++ gcc/testsuite/gnat.dg/opt13_pkg.ads (.../branches/gcc-4_5-branch) (wersja 170084)
2864 +package Opt13_Pkg is
2868 + type My_Type is private;
2870 + procedure Allocate (T : out My_Type);
2876 + type My_Type is access Data;
2879 Index: gcc/testsuite/gcc.dg/pr47201.c
2880 ===================================================================
2881 --- gcc/testsuite/gcc.dg/pr47201.c (.../tags/gcc_4_5_2_release) (wersja 0)
2882 +++ gcc/testsuite/gcc.dg/pr47201.c (.../branches/gcc-4_5-branch) (wersja 170084)
2884 +/* PR target/47201 */
2885 +/* { dg-do compile } */
2886 +/* { dg-options "-O -fpic -g" { target fpic } } */
2890 + __UINTPTR_TYPE__ m;
2898 + (__UINTPTR_TYPE__)&u
2900 + return u.d == v.d;
2902 Index: gcc/testsuite/gcc.dg/pr46893.c
2903 ===================================================================
2904 --- gcc/testsuite/gcc.dg/pr46893.c (.../tags/gcc_4_5_2_release) (wersja 0)
2905 +++ gcc/testsuite/gcc.dg/pr46893.c (.../branches/gcc-4_5-branch) (wersja 170084)
2907 +/* PR debug/46893 */
2908 +/* { dg-do compile } */
2909 +/* { dg-options "-O -g" } */
2914 + union { unsigned long long l; double d; } u = { 0x7ff0000000000000ULL };
2915 + double v = 0, w = -u.d;
2920 Index: gcc/testsuite/gcc.dg/20061124-1.c
2921 ===================================================================
2922 --- gcc/testsuite/gcc.dg/20061124-1.c (.../tags/gcc_4_5_2_release) (wersja 170084)
2923 +++ gcc/testsuite/gcc.dg/20061124-1.c (.../branches/gcc-4_5-branch) (wersja 170084)
2926 /* { dg-require-effective-target sync_char_short } */
2927 +/* { dg-options "-mcpu=v9" { target sparc*-*-* } } */
2929 /* This testcase failed on s390 because no compare instruction for
2930 the check of FLAG was emitted. */
2931 Index: gcc/testsuite/gcc.dg/compat/vector-1b_main.c
2932 ===================================================================
2933 --- gcc/testsuite/gcc.dg/compat/vector-1b_main.c (.../tags/gcc_4_5_2_release) (wersja 170084)
2934 +++ gcc/testsuite/gcc.dg/compat/vector-1b_main.c (.../branches/gcc-4_5-branch) (wersja 170084)
2936 /* { dg-skip-if "test AVX vector" { ! { i?86-*-* x86_64-*-* } } } */
2937 -/* { dg-require-effective-target avx } */
2938 +/* { dg-require-effective-target avx_runtime } */
2940 /* Test compatibility of vector types: layout between separately-compiled
2941 modules, parameter passing, and function return. This test uses
2942 vectors of integer values. */
2946 extern void vector_1_x (void);
2947 extern void exit (int);
2953 - unsigned int eax, ebx, ecx, edx;
2955 - if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
2958 - /* Run AVX vector test only if host has AVX support. */
2959 - if (ecx & bit_AVX)
2965 Index: gcc/testsuite/gcc.dg/compat/vector-2b_main.c
2966 ===================================================================
2967 --- gcc/testsuite/gcc.dg/compat/vector-2b_main.c (.../tags/gcc_4_5_2_release) (wersja 170084)
2968 +++ gcc/testsuite/gcc.dg/compat/vector-2b_main.c (.../branches/gcc-4_5-branch) (wersja 170084)
2970 /* { dg-skip-if "test AVX support" { ! { i?86-*-* x86_64-*-* } } } */
2971 -/* { dg-require-effective-target avx } */
2972 +/* { dg-require-effective-target avx_runtime } */
2974 /* Test compatibility of vector types: layout between separately-compiled
2975 modules, parameter passing, and function return. This test uses
2976 vectors of floating points values. */
2980 extern void vector_2_x (void);
2981 extern void exit (int);
2987 - unsigned int eax, ebx, ecx, edx;
2989 - if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
2992 - /* Run AVX vector test only if host has AVX support. */
2993 - if (ecx & bit_AVX)
2999 Index: gcc/testsuite/gcc.dg/debug/pr46782.c
3000 ===================================================================
3001 --- gcc/testsuite/gcc.dg/debug/pr46782.c (.../tags/gcc_4_5_2_release) (wersja 0)
3002 +++ gcc/testsuite/gcc.dg/debug/pr46782.c (.../branches/gcc-4_5-branch) (wersja 170084)
3004 +/* PR debug/46782 */
3005 +/* { dg-do compile } */
3006 +/* { dg-options "-w -O0 -fvar-tracking -fcompare-debug" } */
3015 Index: gcc/testsuite/gcc.dg/graphite/run-id-pr46758.c
3016 ===================================================================
3017 --- gcc/testsuite/gcc.dg/graphite/run-id-pr46758.c (.../tags/gcc_4_5_2_release) (wersja 0)
3018 +++ gcc/testsuite/gcc.dg/graphite/run-id-pr46758.c (.../branches/gcc-4_5-branch) (wersja 170084)
3021 +movegt (int y, long long a)
3025 + for (i = 0; i < y; i++)
3026 + if (a == -1LL << 33)
3034 + if (movegt (1, -1LL << 33) != -1)
3035 + __builtin_abort ();
3038 Index: gcc/testsuite/gcc.dg/graphite/pr45552.c
3039 ===================================================================
3040 --- gcc/testsuite/gcc.dg/graphite/pr45552.c (.../tags/gcc_4_5_2_release) (wersja 0)
3041 +++ gcc/testsuite/gcc.dg/graphite/pr45552.c (.../branches/gcc-4_5-branch) (wersja 170084)
3061 +static void *array_from_ObjectSmooth( ObjectSmooth *obj )
3064 + VertexArray *array = (VertexArray *) __builtin_malloc( sizeof( VertexArray ) );
3065 + array->vertex = (float *) __builtin_malloc( 3*sizeof(float)*obj->num_vertex );
3066 + array->normal = (float *) __builtin_malloc( 3*sizeof(float)*obj->num_vertex );
3067 + for (i=0, j=0; i<obj->num_vertex; ++i) {
3068 + array->normal[j++] = 9;
3069 + array->vertex[j] = obj->vertex[i].z;
3070 + array->normal[j++] = 1;
3073 +static void draw_cell( void )
3075 + glCallList( array_from_ObjectSmooth( (ObjectSmooth *) __builtin_malloc(10) ));
3077 +static int render( State *st)
3080 + for (b=0; b<st->num_cells; ++b) {
3085 +reshape_glcells( int width, int height )
3089 Index: gcc/testsuite/gcc.dg/torture/pr47365.c
3090 ===================================================================
3091 --- gcc/testsuite/gcc.dg/torture/pr47365.c (.../tags/gcc_4_5_2_release) (wersja 0)
3092 +++ gcc/testsuite/gcc.dg/torture/pr47365.c (.../branches/gcc-4_5-branch) (wersja 170084)
3094 +/* { dg-do run } */
3107 +struct B b = { 0, 3 };
3112 + if (b.a[0].i != i)
3119 + if (b.a[1].i == i)
3120 + __builtin_abort ();
3122 + if (b.a[0].i == 0)
3123 + __builtin_abort ();
3133 Index: gcc/testsuite/gcc.dg/torture/pr47411.c
3134 ===================================================================
3135 --- gcc/testsuite/gcc.dg/torture/pr47411.c (.../tags/gcc_4_5_2_release) (wersja 0)
3136 +++ gcc/testsuite/gcc.dg/torture/pr47411.c (.../branches/gcc-4_5-branch) (wersja 170084)
3138 +/* { dg-do compile } */
3140 +typedef long unsigned int size_t;
3142 +static __inline void *
3143 +__inline_memcpy_chk (void *__dest, const void *__src, size_t __len)
3145 + return __builtin___memcpy_chk (__dest, __src, __len, __builtin_object_size (__dest, 0));
3148 +extern void *xmalloc (size_t) __attribute__ ((__malloc__));
3150 +struct htab { void ** entries; };
3152 +typedef struct htab *htab_t;
3154 +extern void ** htab_find_slot (htab_t, const void *);
3156 +enum mode_class { MODE_RANDOM, MODE_CC, MODE_INT, MAX_MODE_CLASS };
3160 + struct mode_data *next;
3161 + enum mode_class cl;
3164 +static const struct mode_data blank_mode = { 0, MAX_MODE_CLASS };
3166 +static htab_t modes_by_name;
3171 + struct mode_data *m
3172 + = ((struct mode_data *) xmalloc (sizeof (struct mode_data)));
3174 + ((__builtin_object_size (m, 0) != (size_t) -1) ? __builtin___memcpy_chk (m, &blank_mode, sizeof (struct mode_data), __builtin_object_size (m, 0)) : __inline_memcpy_chk (m, &blank_mode, sizeof (struct mode_data)));
3176 + *htab_find_slot (modes_by_name, m) = m;
3180 Index: gcc/testsuite/gcc.dg/tree-ssa/pr47392.c
3181 ===================================================================
3182 --- gcc/testsuite/gcc.dg/tree-ssa/pr47392.c (.../tags/gcc_4_5_2_release) (wersja 0)
3183 +++ gcc/testsuite/gcc.dg/tree-ssa/pr47392.c (.../branches/gcc-4_5-branch) (wersja 170084)
3185 +/* { dg-do run } */
3186 +/* { dg-options "-O2 -fdump-tree-pre-stats" } */
3199 +struct B b = { 0, 3 };
3204 + if (b.a[0].i != i)
3211 + if (b.a[1].i == i)
3212 + __builtin_abort ();
3214 + if (b.a[0].i == 0)
3215 + __builtin_abort ();
3225 +/* { dg-final { scan-tree-dump "Eliminated: 1" "pre" } } */
3226 +/* { dg-final { cleanup-tree-dump "pre" } } */
3227 Index: gcc/testsuite/gcc.dg/tree-ssa/pr47286.c
3228 ===================================================================
3229 --- gcc/testsuite/gcc.dg/tree-ssa/pr47286.c (.../tags/gcc_4_5_2_release) (wersja 0)
3230 +++ gcc/testsuite/gcc.dg/tree-ssa/pr47286.c (.../branches/gcc-4_5-branch) (wersja 170084)
3232 +/* { dg-do compile } */
3233 +/* { dg-skip-if "" { ! { i?86-*-* x86_64-*-* } } { "*" } { "" } } */
3234 +/* { dg-options "-O2 -fdump-tree-optimized" } */
3236 +struct thread_info { int preempt_count; };
3237 +static inline struct thread_info *current_thread_info(void)
3239 + register struct thread_info *sp asm("esp");
3242 +void testcase(void)
3244 + current_thread_info()->preempt_count += 1;
3247 +/* We have to make sure that alias analysis treats sp as pointing
3248 + to globals and thus the store not optimized away. */
3250 +/* { dg-final { scan-tree-dump "->preempt_count =" "optimized" } } */
3251 +/* { dg-final { cleanup-tree-dump "optimized" } } */
3252 Index: gcc/testsuite/gcc.dg/tree-ssa/pr42585.c
3253 ===================================================================
3254 --- gcc/testsuite/gcc.dg/tree-ssa/pr42585.c (.../tags/gcc_4_5_2_release) (wersja 170084)
3255 +++ gcc/testsuite/gcc.dg/tree-ssa/pr42585.c (.../branches/gcc-4_5-branch) (wersja 170084)
3259 /* The local aggregates . */
3260 -/* { dg-final { scan-tree-dump-times "struct _fat_ptr _ans" 0 "optimized"} } */
3261 -/* { dg-final { scan-tree-dump-times "struct _fat_ptr _T2" 0 "optimized"} } */
3262 +/* Whether the structs are totally scalarized or not depends on the
3263 + MOVE_RATIO macro defintion in the back end. The scalarization will
3264 + not take place when using small values for MOVE_RATIO. */
3265 +/* { dg-final { scan-tree-dump-times "struct _fat_ptr _ans" 0 "optimized" { target { ! "powerpc*-*-* arm-*-* sh*-*-* s390*-*-*" } } } } */
3266 +/* { dg-final { scan-tree-dump-times "struct _fat_ptr _T2" 0 "optimized" { target { ! "powerpc*-*-* arm-*-* sh*-*-* s390*-*-*" } } } } */
3267 /* { dg-final { cleanup-tree-dump "optimized" } } */
3268 Index: gcc/testsuite/gcc.dg/pr28796-2.c
3269 ===================================================================
3270 --- gcc/testsuite/gcc.dg/pr28796-2.c (.../tags/gcc_4_5_2_release) (wersja 170084)
3271 +++ gcc/testsuite/gcc.dg/pr28796-2.c (.../branches/gcc-4_5-branch) (wersja 170084)
3273 /* { dg-options "-O2 -funsafe-math-optimizations -fno-finite-math-only -DUNSAFE" } */
3274 /* { dg-add-options ieee } */
3275 /* { dg-skip-if "No Inf/NaN support" { spu-*-* } } */
3276 +/* { dg-skip-if "Bug in _Q_dtoq" { sparc*-sun-solaris2.8 } } */
3278 #include "tg-tests.h"
3280 Index: gcc/testsuite/gcc.dg/pr44606.c
3281 ===================================================================
3282 --- gcc/testsuite/gcc.dg/pr44606.c (.../tags/gcc_4_5_2_release) (wersja 0)
3283 +++ gcc/testsuite/gcc.dg/pr44606.c (.../branches/gcc-4_5-branch) (wersja 170084)
3285 +/* PR target/44606 */
3286 +/* { dg-do run } */
3287 +/* { dg-options "-O2" } */
3291 +extern void abort (void);
3293 + typedef struct _PixelPacket { unsigned char r, g, b; }
3295 +#define ARRAYLEN(X) (sizeof(X)/sizeof(X[0]))
3297 +#define COLS (ARRAYLEN(q) - 1)
3298 +PixelPacket p[2*COLS + 22];
3299 +#define Minify(POS, WEIGHT) do { \
3300 + total_r += (WEIGHT)*(p[POS].r); \
3301 + total_g += (WEIGHT)*(p[POS].g); \
3302 + total_b += (WEIGHT)*(p[POS].b); \
3304 +unsigned long columns = COLS;
3307 + static const unsigned char answers[COLS] = { 31, 32, 34, 35, 36 };
3309 + for (x = 0; x < sizeof(p)/sizeof(p[0]); x++) {
3310 + p[x].b = (x + 34) | 1;
3312 + for (x = 0; x < columns; x++) {
3313 + double total_r = 0, total_g = 0, total_b = 0;
3314 + double saved_r = 0, saved_g = 0, saved_b = 0;
3315 + Minify(2*x + 0, 3.0);
3316 + Minify(2*x + 1, 7.0);
3317 + Minify(2*x + 2, 7.0);
3318 + saved_r = total_r;
3319 + saved_g = total_g;
3320 + Minify(2*x + 11, 15.0);
3321 + Minify(2*x + 12, 7.0);
3322 + Minify(2*x + 18, 7.0);
3323 + Minify(2*x + 19, 15.0);
3324 + Minify(2*x + 20, 15.0);
3325 + Minify(2*x + 21, 7.0);
3326 + q[x].r = (unsigned char)(total_r/128.0 + 0.5);
3327 + q[x].g = (unsigned char)(total_g/128.0 + 0.5);
3328 + q[x].b = (unsigned char)(total_b/128.0 + 0.5);
3329 + fprintf(stderr, "r:%f g:%f b:%f\n", saved_r, saved_g, saved_b);
3331 + for (x = 0; x < COLS; x++) {
3332 + if (answers[x] != q[x].b)
3337 Index: gcc/testsuite/gcc.dg/vect/pr43430-1.c
3338 ===================================================================
3339 --- gcc/testsuite/gcc.dg/vect/pr43430-1.c (.../tags/gcc_4_5_2_release) (wersja 170084)
3340 +++ gcc/testsuite/gcc.dg/vect/pr43430-1.c (.../branches/gcc-4_5-branch) (wersja 170084)
3342 return foo (data_ch1, data_ch2, 1);
3345 -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
3346 +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_condition } } } */
3347 /* { dg-final { cleanup-tree-dump "vect" } } */
3348 Index: gcc/testsuite/gcc.dg/vect/slp-multitypes-2.c
3349 ===================================================================
3350 --- gcc/testsuite/gcc.dg/vect/slp-multitypes-2.c (.../tags/gcc_4_5_2_release) (wersja 170084)
3351 +++ gcc/testsuite/gcc.dg/vect/slp-multitypes-2.c (.../branches/gcc-4_5-branch) (wersja 170084)
3353 /* { dg-require-effective-target vect_int } */
3354 +/* { dg-do run { xfail { sparc*-*-* && ilp32 } } } PR rtl-opt/46603 */
3358 Index: gcc/testsuite/ChangeLog
3359 ===================================================================
3360 --- gcc/testsuite/ChangeLog (.../tags/gcc_4_5_2_release) (wersja 170084)
3361 +++ gcc/testsuite/ChangeLog (.../branches/gcc-4_5-branch) (wersja 170084)
3363 +2011-02-10 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
3366 + * gcc.target/mips/save-restore-1.c: Skip on mips-sgi-irix6*.
3367 + * gcc.target/mips/save-restore-3.c: Likewise.
3368 + * gcc.target/mips/save-restore-4.c: Likewise.
3369 + * gcc.target/mips/save-restore-5.c: Likewise.
3372 + * g++.dg/tree-prof/partition1.C: Skip on mips-sgi-irix*.
3373 + * g++.dg/tree-prof/partition2.C: Likewise.
3375 +2011-02-07 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
3377 + Backport from mainline:
3378 + 2010-07-23 Uros Bizjak <ubizjak@gmail.com>
3380 + * lib/target-supports.exp (check_avx_hw_available): New procedure.
3381 + (check_effective_target_avx_runtime): New procedure.
3383 + * gcc.dg/compat/vector-1b_main.c: Use avx_runtime effective target.
3384 + Remove cpuid.h include and __get_cpuid test.
3385 + * gcc.dg/compat/vector-2b_main.c: Ditto.
3387 + * gcc.target/i386/avx-check.h (main): Also check bit_OSXSAVE.
3389 +2011-02-03 Michael Meissner <meissner@linux.vnet.ibm.com>
3391 + Backport from mainline:
3392 + 2011-02-02 Michael Meissner <meissner@linux.vnet.ibm.com>
3394 + * gcc.target/powerpc/vsx-builtin-8.c: New file, test vec_vsx_ld
3397 + * gcc.target/powerpc/avoid-indexed-addresses.c: Disable altivec
3398 + and vsx so a default --with-cpu=power7 doesn't give an error
3399 + when -mavoid-indexed-addresses is used.
3401 + * gcc.target/powerpc/ppc32-abi-dfp-1.c: Rewrite to use an asm
3402 + wrapper function to save the arguments and then jump to the real
3403 + function, rather than depending on the compiler not to move stuff
3405 + * gcc.target/powerpc/ppc64-abi-dfp-2.c: Ditto.
3407 +2011-02-03 Jonathan Wakely <jwakely.gcc@gmail.com>
3410 + * g++.dg/pr47589.C: New test.
3412 +2011-02-01 Richard Guenther <rguenther@suse.de>
3414 + PR tree-optimization/47541
3415 + * g++.dg/torture/pr47541.C: New testcase.
3417 +2011-01-31 Nathan Froyd <froydnj@codesourcery.com>
3419 + Backport from mainline:
3420 + 2010-12-30 Nathan Froyd <froydnj@codesourcery.com>
3423 + * gcc.dg/pr44606.c: New test.
3425 +2011-01-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
3427 + * gcc.dg/tree-ssa/pr42585.c: Disable on power, arm, sh, s390 and
3430 +2011-01-26 Eric Botcazou <ebotcazou@adacore.com>
3432 + * gcc.c-torture/compile/20110126-1.c: New test.
3434 +2011-01-25 Tobias Burnus <burnus@net-b.de>
3436 + Backport from mainline
3437 + 2011-01-17 Jakub Jelinek <jakub@redhat.com>
3440 + * gfortran.dg/gomp/pr47331.f90: New test.
3442 +2011-01-25 Tobias Burnus <burnus@net-b.de>
3445 + * gfortran.dg/redefined_intrinsic_assignment_2.f90: New.
3447 +2011-01-25 Richard Guenther <rguenther@suse.de>
3449 + PR middle-end/47411
3450 + * gcc.dg/torture/pr47411.c: New testcase.
3452 +2011-01-24 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
3454 + * gfortran.dg/cray_pointers_2.f90: Avoid cycling through
3455 + optimization options.
3457 +2011-01-24 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
3459 + * gfortran.dg/array_constructor_33.f90: Use dg-timeout-factor 4.
3461 +2011-01-21 Richard Guenther <rguenther@suse.de>
3463 + PR tree-optimization/47365
3464 + * gcc.dg/torture/pr47365.c: New testcase.
3465 + * gcc.dg/tree-ssa/pr47392.c: Likewise.
3467 +2011-01-21 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
3469 + * g++.dg/other/anon5.C: Skip on mips-sgi-irix*.
3471 +2011-01-17 Eric Botcazou <ebotcazou@adacore.com>
3473 + Backport from mainline
3474 + 2010-11-22 Eric Botcazou <ebotcazou@adacore.com>
3476 + * gcc.dg/pr28796-2.c: SKIP on SPARC/Solaris 8.
3478 + PR rtl-optimization/46603
3479 + * gcc.dg/vect/slp-multitypes-2.c: XFAIL execution on SPARC 32-bit.
3481 + 2010-08-31 Bingfeng Mei <bmei@broadcom.com>
3483 + * gcc.dg/vect/pr43430-1.c: Requires vect_condition target.
3485 +2011-01-17 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
3487 + * g++.old-deja/g++.other/init19.C: Don't XFAIL on mips-sgi-irix*.
3489 +2011-01-17 H.J. Lu <hongjiu.lu@intel.com>
3491 + Backport from mainline
3492 + 2011-01-17 H.J. Lu <hongjiu.lu@intel.com>
3495 + * gcc.target/i386/avx-vmaskmovpd-1.c: New.
3496 + * gcc.target/i386/avx-vmaskmovpd-2.c: Likewise.
3497 + * gcc.target/i386/avx-vmaskmovps-1.c: Likewise.
3498 + * gcc.target/i386/avx-vmaskmovps-1.c: Likewise.
3500 + * gcc.target/i386/avx-vmaskmovpd-256-1.c (avx_test): Load mask
3502 + * gcc.target/i386/avx-vmaskmovpd-256-2.c (avx_test): Likewise.
3503 + * gcc.target/i386/avx-vmaskmovps-256-1.c (avx_test): Likewise.
3504 + * gcc.target/i386/avx-vmaskmovps-256-2.c (avx_test): Likewise.
3506 +2011-01-17 Richard Guenther <rguenther@suse.de>
3508 + Backport from mainline
3509 + PR tree-optimization/47286
3510 + * gcc.dg/tree-ssa/pr47286.c: New testcase.
3512 + PR tree-optimization/44592
3513 + * gfortran.dg/pr44592.f90: New testcase.
3515 +2011-01-16 Jakub Jelinek <jakub@redhat.com>
3517 + Backport from mainline
3518 + 2011-01-07 Jakub Jelinek <jakub@redhat.com>
3521 + * gcc.dg/pr47201.c: New test.
3523 + 2011-01-06 Jakub Jelinek <jakub@redhat.com>
3526 + * gcc.c-torture/compile/pr47150.c: New test.
3528 + 2010-12-21 Jakub Jelinek <jakub@redhat.com>
3531 + * gcc.target/i386/pr46880.c: New test.
3533 + PR middle-end/45852
3534 + * gcc.target/i386/pr45852.c: New test.
3536 + 2010-12-16 Jakub Jelinek <jakub@redhat.com>
3538 + PR tree-optimization/43655
3539 + * g++.dg/opt/pr43655.C: New test.
3542 + * gcc.dg/pr46893.c: New test.
3544 + 2010-12-10 Jakub Jelinek <jakub@redhat.com>
3546 + PR rtl-optimization/46804
3547 + * gfortran.dg/pr46804.f90: New test.
3549 + PR rtl-optimization/46865
3550 + * gcc.target/i386/pr46865-1.c: New test.
3551 + * gcc.target/i386/pr46865-2.c: New test.
3553 + PR tree-optimization/46864
3554 + * g++.dg/opt/pr46864.C: New test.
3556 +2011-01-13 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
3558 + * gfortran.dg/cray_pointers_2.f90: Use dg-timeout-factor 4.
3560 +2011-01-12 Eric Botcazou <ebotcazou@adacore.com>
3562 + PR testsuite/33033
3563 + * gcc.dg/20061124-1.c: Pass -mcpu=v9 on the SPARC.
3565 +2011-02-01 Thomas Koenig <tkoenig@gcc.gnu.org>
3567 + Backport from mainline
3569 + * gfortran.dg/userdef_operator_2.f90: New test case.
3571 +2010-12-27 Yao Qi <yao@codesourcery.com>
3573 + Backport from mainline:
3574 + 2010-10-14 Yao Qi <yao@codesourcery.com>
3577 + * gcc.target/arm/pr45447.c: New test.
3579 +2010-12-24 Eric Botcazou <ebotcazou@adacore.com>
3581 + * gnat.dg/opt13_pkg.ad[sb]: Fix line ending.
3583 +2010-12-22 Sebastian Pop <sebastian.pop@amd.com>
3585 + PR tree-optimization/46758
3586 + * gcc.dg/graphite/run-id-pr46758.c: New.
3588 +2010-12-23 Sebastian Pop <sebastian.pop@amd.com>
3590 + PR tree-optimization/45552
3591 + * gcc.dg/graphite/pr45552.c
3594 +2010-12-23 Sebastian Pop <sebastian.pop@amd.com>
3596 + PR tree-optimization/43023
3597 + * gfortran.dg/ldist-1.f90: Adjust pattern.
3598 + * gfortran.dg/ldist-pr43023.f90: New.
3600 +2010-12-21 Martin Jambor <mjambor@suse.cz>
3602 + PR middle-end/46734
3603 + * g++.dg/tree-ssa/pr46734.C: New test.
3605 +2010-12-18 Alexandre Oliva <aoliva@redhat.com>
3608 + * gfortran.dg/debug/pr46756.f: New.
3610 +2010-12-18 Alexandre Oliva <aoliva@redhat.com>
3613 + * gcc.dg/debug/pr46782.c: New.
3615 +2010-12-17 Daniel Kraft <d@domob.eu>
3618 + * gfortran.dg/power2.f90: Initialize variables.
3620 +2010-12-16 Eric Botcazou <ebotcazou@adacore.com>
3622 + * gnat.dg/opt13.adb: New test.
3623 + * gnat.dg/opt13_pkg.ad[sb]: New helper.
3625 2010-12-16 Release Manager
3627 * GCC 4.5.2 released.
3628 Index: gcc/testsuite/g++.old-deja/g++.other/init19.C
3629 ===================================================================
3630 --- gcc/testsuite/g++.old-deja/g++.other/init19.C (.../tags/gcc_4_5_2_release) (wersja 170084)
3631 +++ gcc/testsuite/g++.old-deja/g++.other/init19.C (.../branches/gcc-4_5-branch) (wersja 170084)
3633 -// { dg-do run { xfail { { ! cxa_atexit } && { ! *-*-solaris2* } } } }
3634 +// { dg-do run { xfail { { ! cxa_atexit } && { ! { mips-sgi-irix* *-*-solaris2* } } } } }
3637 #define assert(x) do { if (! (x)) abort(); } while (0)
3638 Index: gcc/testsuite/g++.dg/other/anon5.C
3639 ===================================================================
3640 --- gcc/testsuite/g++.dg/other/anon5.C (.../tags/gcc_4_5_2_release) (wersja 170084)
3641 +++ gcc/testsuite/g++.dg/other/anon5.C (.../branches/gcc-4_5-branch) (wersja 170084)
3644 -// { dg-do link { target { ! { *-*-darwin* *-*-hpux* *-*-solaris2.* alpha*-dec-osf* } } } }
3645 +// { dg-do link { target { ! { *-*-darwin* *-*-hpux* *-*-solaris2.* alpha*-dec-osf* mips-sgi-irix* } } } }
3646 // { dg-options "-g" }
3649 Index: gcc/testsuite/g++.dg/pr47589.C
3650 ===================================================================
3651 --- gcc/testsuite/g++.dg/pr47589.C (.../tags/gcc_4_5_2_release) (wersja 0)
3652 +++ gcc/testsuite/g++.dg/pr47589.C (.../branches/gcc-4_5-branch) (wersja 170084)
3655 +// { dg-do compile }
3659 + typedef void(*Cb)();
3666 + template<class D> static void f();
3672 + TF() : F(C::f<D>) { }
3675 +struct DTC : TF<DTC>
3680 Index: gcc/testsuite/g++.dg/tree-ssa/pr46734.C
3681 ===================================================================
3682 --- gcc/testsuite/g++.dg/tree-ssa/pr46734.C (.../tags/gcc_4_5_2_release) (wersja 0)
3683 +++ gcc/testsuite/g++.dg/tree-ssa/pr46734.C (.../branches/gcc-4_5-branch) (wersja 170084)
3685 +/* { dg-do compile } */
3686 +/* { dg-options "-O -fipa-sra" } */
3691 + A() {p = (int *) -1;}
3692 + ~A() {if (p && p != (int *) -1) *p = 0;}
3699 + B() : a() {data[0] = 0;}
3707 +static int * __attribute__ ((noinline)) foo (B *b, void *z)
3709 + __builtin_memcpy (gz, z, 28);
3714 +int *bar (B *b, void *z)
3717 + return foo (b, z);
3719 Index: gcc/testsuite/g++.dg/opt/pr43655.C
3720 ===================================================================
3721 --- gcc/testsuite/g++.dg/opt/pr43655.C (.../tags/gcc_4_5_2_release) (wersja 0)
3722 +++ gcc/testsuite/g++.dg/opt/pr43655.C (.../branches/gcc-4_5-branch) (wersja 170084)
3724 +// PR tree-optimization/43655
3726 +// { dg-options "-O0 -ftree-ter" }
3728 +extern "C" void abort ();
3732 + C (int i) : val(i) { }
3733 + C (const C& c) : val(c.val) { }
3734 + ~C (void) { val = 999; }
3735 + C& operator = (const C& c) { val = c.val; return *this; }
3736 + C& inc (int i) { val += i; return *this; }
3749 + return f ().inc (i);
3755 + if (f (2).val != 5)
3758 Index: gcc/testsuite/g++.dg/opt/pr46864.C
3759 ===================================================================
3760 --- gcc/testsuite/g++.dg/opt/pr46864.C (.../tags/gcc_4_5_2_release) (wersja 0)
3761 +++ gcc/testsuite/g++.dg/opt/pr46864.C (.../branches/gcc-4_5-branch) (wersja 170084)
3763 +// PR tree-optimization/46864
3764 +// { dg-do compile }
3765 +// { dg-options "-O -fnon-call-exceptions" }
3772 + bool bar () throw ()
3775 + for (int i = 0; i < m; i++)
3786 + while (baz () && s->bar ())
3789 Index: gcc/testsuite/g++.dg/tree-prof/partition1.C
3790 ===================================================================
3791 --- gcc/testsuite/g++.dg/tree-prof/partition1.C (.../tags/gcc_4_5_2_release) (wersja 170084)
3792 +++ gcc/testsuite/g++.dg/tree-prof/partition1.C (.../branches/gcc-4_5-branch) (wersja 170084)
3794 /* { dg-require-effective-target freorder } */
3795 /* { dg-options "-O2 -freorder-blocks-and-partition" } */
3796 +/* { dg-skip-if "PR target/47683" { mips-sgi-irix* } } */
3798 struct A { A () __attribute__((noinline)); ~A () __attribute__((noinline)); };
3799 A::A () { asm volatile ("" : : : "memory"); }
3800 Index: gcc/testsuite/g++.dg/tree-prof/partition2.C
3801 ===================================================================
3802 --- gcc/testsuite/g++.dg/tree-prof/partition2.C (.../tags/gcc_4_5_2_release) (wersja 170084)
3803 +++ gcc/testsuite/g++.dg/tree-prof/partition2.C (.../branches/gcc-4_5-branch) (wersja 170084)
3805 // PR middle-end/45458
3806 // { dg-require-effective-target freorder }
3807 // { dg-options "-fnon-call-exceptions -freorder-blocks-and-partition" }
3808 +// { dg-skip-if "PR target/47683" { mips-sgi-irix* } }
3812 Index: gcc/testsuite/g++.dg/torture/pr47541.C
3813 ===================================================================
3814 --- gcc/testsuite/g++.dg/torture/pr47541.C (.../tags/gcc_4_5_2_release) (wersja 0)
3815 +++ gcc/testsuite/g++.dg/torture/pr47541.C (.../branches/gcc-4_5-branch) (wersja 170084)
3817 +/* { dg-do run } */
3820 +struct RefCount : public Dummy {
3821 + ~RefCount(); /* Has to be non-pod. */
3825 +RefCount::~RefCount(){}
3826 +struct Wrapper : public Dummy { RefCount ref; };
3827 +void __attribute__((noinline,noclone))
3832 +extern "C" void abort (void);
3844 Index: gcc/testsuite/lib/target-supports.exp
3845 ===================================================================
3846 --- gcc/testsuite/lib/target-supports.exp (.../tags/gcc_4_5_2_release) (wersja 170084)
3847 +++ gcc/testsuite/lib/target-supports.exp (.../branches/gcc-4_5-branch) (wersja 170084)
3849 -# Copyright (C) 1999, 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
3850 -# Free Software Foundation, Inc.
3851 +# Copyright (C) 1999, 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
3852 +# 2011 Free Software Foundation, Inc.
3854 # This program is free software; you can redistribute it and/or modify
3855 # it under the terms of the GNU General Public License as published by
3856 @@ -1005,6 +1005,30 @@
3860 +# Return 1 if the target supports executing AVX instructions, 0
3861 +# otherwise. Cache the result.
3863 +proc check_avx_hw_available { } {
3864 + return [check_cached_effective_target avx_hw_available {
3865 + # If this is not the right target then we can skip the test.
3866 + if { !([istarget x86_64-*-*] || [istarget i?86-*-*]) } {
3869 + check_runtime_nocache avx_hw_available {
3870 + #include "cpuid.h"
3873 + unsigned int eax, ebx, ecx, edx;
3874 + if (__get_cpuid (1, &eax, &ebx, &ecx, &edx))
3875 + return ((ecx & (bit_AVX | bit_OSXSAVE))
3876 + != (bit_AVX | bit_OSXSAVE));
3884 # Return 1 if the target supports running SSE executables, 0 otherwise.
3886 proc check_effective_target_sse_runtime { } {
3887 @@ -1025,6 +1049,16 @@
3891 +# Return 1 if the target supports running AVX executables, 0 otherwise.
3893 +proc check_effective_target_avx_runtime { } {
3894 + if { [check_effective_target_avx]
3895 + && [check_avx_hw_available] } {
3901 # Return 1 if the target supports executing VSX instructions, 0
3902 # otherwise. Cache the result.
3904 Index: gcc/testsuite/gfortran.dg/gomp/pr47331.f90
3905 ===================================================================
3906 --- gcc/testsuite/gfortran.dg/gomp/pr47331.f90 (.../tags/gcc_4_5_2_release) (wersja 0)
3907 +++ gcc/testsuite/gfortran.dg/gomp/pr47331.f90 (.../branches/gcc-4_5-branch) (wersja 170084)
3910 +! { dg-do compile }
3911 +! { dg-options "-fopenmp -fwhole-file" }
3916 + !$omp end parallel
3932 +end program pr47331
3933 Index: gcc/testsuite/gfortran.dg/ldist-1.f90
3934 ===================================================================
3935 --- gcc/testsuite/gfortran.dg/ldist-1.f90 (.../tags/gcc_4_5_2_release) (wersja 170084)
3936 +++ gcc/testsuite/gfortran.dg/ldist-1.f90 (.../branches/gcc-4_5-branch) (wersja 170084)
3939 end Subroutine PADEC
3941 -! { dg-final { scan-tree-dump-times "distributed: split to 4 loops" 1 "ldist" } }
3942 +! There are 5 legal partitions in this code. Based on the data
3943 +! locality heuristic, this loop should not be split.
3945 +! { dg-final { scan-tree-dump-not "distributed: split to" "ldist" } }
3946 ! { dg-final { cleanup-tree-dump "ldist" } }
3947 Index: gcc/testsuite/gfortran.dg/redefined_intrinsic_assignment_2.f90
3948 ===================================================================
3949 --- gcc/testsuite/gfortran.dg/redefined_intrinsic_assignment_2.f90 (.../tags/gcc_4_5_2_release) (wersja 0)
3950 +++ gcc/testsuite/gfortran.dg/redefined_intrinsic_assignment_2.f90 (.../branches/gcc-4_5-branch) (wersja 170084)
3952 +! { dg-do compile }
3956 +! ASSIGNMENT(=) checks. Defined assignment is allowed if and only if
3957 +! it does not override an intrinsic assignment.
3961 + interface assignment(=)
3962 + module procedure valid, valid2
3965 + ! Valid: scalar = array
3966 + subroutine valid (lhs,rhs)
3967 + integer, intent(out) :: lhs
3968 + integer, intent(in) :: rhs(:)
3970 + end subroutine valid
3972 + ! Valid: array of different ranks
3973 + subroutine valid2 (lhs,rhs)
3974 + integer, intent(out) :: lhs(:)
3975 + integer, intent(in) :: rhs(:,:)
3977 + end subroutine valid2
3981 + interface assignment(=)
3982 + module procedure invalid
3985 + ! Invalid: scalar = scalar
3986 + subroutine invalid (lhs,rhs) ! { dg-error "must not redefine an INTRINSIC type assignment" }
3987 + integer, intent(out) :: lhs
3988 + integer, intent(in) :: rhs
3990 + end subroutine invalid
3994 + interface assignment(=)
3995 + module procedure invalid2
3998 + ! Invalid: array = scalar
3999 + subroutine invalid2 (lhs,rhs) ! { dg-error "must not redefine an INTRINSIC type assignment" }
4000 + integer, intent(out) :: lhs(:)
4001 + integer, intent(in) :: rhs
4003 + end subroutine invalid2
4007 + interface assignment(=)
4008 + module procedure invalid3
4011 + ! Invalid: array = array for same rank
4012 + subroutine invalid3 (lhs,rhs) ! { dg-error "must not redefine an INTRINSIC type assignment" }
4013 + integer, intent(out) :: lhs(:)
4014 + integer, intent(in) :: rhs(:)
4016 + end subroutine invalid3
4019 +! { dg-final { cleanup-modules "test1" } }
4020 Index: gcc/testsuite/gfortran.dg/debug/pr46756.f
4021 ===================================================================
4022 --- gcc/testsuite/gfortran.dg/debug/pr46756.f (.../tags/gcc_4_5_2_release) (wersja 0)
4023 +++ gcc/testsuite/gfortran.dg/debug/pr46756.f (.../branches/gcc-4_5-branch) (wersja 170084)
4025 +C PR debug/46756, reduced from ../20010519-1.f
4026 +C { dg-do compile }
4027 +C { dg-options "-O -fcompare-debug" }
4028 + LOGICAL QDISK,QDW,QCMPCT
4029 + LOGICAL LNOMA,LRAISE,LSCI,LBIG
4030 + ASSIGN 801 TO I800 ! { dg-warning "Deleted feature: ASSIGN" "Deleted feature: ASSIGN" }
4033 + ASSIGN 761 TO I760 ! { dg-warning "Deleted feature: ASSIGN" "Deleted feature: ASSIGN" }
4039 + DO WHILE((CVGMX.GT.TOLDIM).AND.(ITER.LT.ITMX))
4041 + ASSIGN 641 to I640 ! { dg-warning "Deleted feature: ASSIGN" "Deleted feature: ASSIGN" }
4048 + GOTO I640 ! { dg-warning "Deleted feature: Assigned" "Assigned GO TO" }
4050 + GOTO I760 ! { dg-warning "Deleted feature: Assigned" "Assigned GO TO" }
4052 + GOTO I800 ! { dg-warning "Deleted feature: Assigned" "Assigned GO TO" }
4054 Index: gcc/testsuite/gfortran.dg/cray_pointers_2.f90
4055 ===================================================================
4056 --- gcc/testsuite/gfortran.dg/cray_pointers_2.f90 (.../tags/gcc_4_5_2_release) (wersja 170084)
4057 +++ gcc/testsuite/gfortran.dg/cray_pointers_2.f90 (.../branches/gcc-4_5-branch) (wersja 170084)
4060 -! { dg-options "-fcray-pointer -fbounds-check" }
4061 +! Using two spaces between dg-do and run is a hack to keep gfortran-dg-runtest
4062 +! from cycling through optimization options for this expensive test.
4064 +! { dg-options "-O3 -fcray-pointer -fbounds-check" }
4065 +! { dg-timeout-factor 4 }
4066 ! Series of routines for testing a Cray pointer implementation
4068 common /errors/errors(400)
4069 Index: gcc/testsuite/gfortran.dg/dependency_39.f90
4070 ===================================================================
4071 --- gcc/testsuite/gfortran.dg/dependency_39.f90 (.../tags/gcc_4_5_2_release) (wersja 0)
4072 +++ gcc/testsuite/gfortran.dg/dependency_39.f90 (.../branches/gcc-4_5-branch) (wersja 170084)
4075 +! PR 45777 - component ref aliases when both are pointers
4078 + integer, dimension(:), allocatable :: data
4081 + subroutine s1(t,d)
4082 + integer, dimension(:), pointer :: d
4083 + type(t1), pointer :: t
4084 + d(1:5)=t%data(3:7)
4086 + subroutine s2(d,t)
4087 + integer, dimension(:), pointer :: d
4088 + type(t1), pointer :: t
4089 + t%data(3:7) = d(1:5)
4095 + type(t1), pointer :: t
4096 + integer, dimension(:), pointer :: d
4098 + allocate(t%data(10))
4099 + t%data=(/(i,i=1,10)/)
4102 + if (any(d.ne.(/3,4,5,6,7/))) call abort()
4103 + t%data=(/(i,i=1,10)/)
4106 + if (any(t%data.ne.(/1,2,1,2,3,4,5,8,9,10/))) call abort
4107 + deallocate(t%data)
4110 +! { dg-final { cleanup-modules "m1" } }
4111 Index: gcc/testsuite/gfortran.dg/ldist-pr43023.f90
4112 ===================================================================
4113 --- gcc/testsuite/gfortran.dg/ldist-pr43023.f90 (.../tags/gcc_4_5_2_release) (wersja 0)
4114 +++ gcc/testsuite/gfortran.dg/ldist-pr43023.f90 (.../branches/gcc-4_5-branch) (wersja 170084)
4116 +! { dg-do compile }
4117 +! { dg-options "-O2 -ftree-loop-distribution" }
4124 +real, dimension(:,:), allocatable :: Angle
4125 +real, dimension(:), allocatable :: exth, ezth, hxth, hyth, hyphi
4129 +SUBROUTINE NFT_Init()
4138 + exth(n) = cos(fi)*cos(th)
4139 + ezth(n) = -sin(th)
4140 + hxth(n) = -sin(fi)
4142 + hyphi(n) = -sin(fi)
4144 +END SUBROUTINE NFT_Init
4147 Index: gcc/testsuite/gfortran.dg/pr44592.f90
4148 ===================================================================
4149 --- gcc/testsuite/gfortran.dg/pr44592.f90 (.../tags/gcc_4_5_2_release) (wersja 0)
4150 +++ gcc/testsuite/gfortran.dg/pr44592.f90 (.../branches/gcc-4_5-branch) (wersja 170084)
4153 +! { dg-options "-O3" }
4154 +! From forall_12.f90
4155 +! Fails with loop reversal at -O3
4157 + character(len=1) :: b(4) = (/"1","2","3","4"/), c(4)
4160 + ! This statement must be here for the abort below
4161 + b(1:3)(i:i) = b(2:4)(i:i)
4164 + b(4:2:-1)(i:i) = b(3:1:-1)(i:i)
4166 + ! This fails. If the condition is printed, the result is F F F F
4167 + if (any (b .ne. (/"1","1","2","3"/))) i = 2
4169 + print *, b .ne. (/"1","1","2","3"/)
4170 + if (i == 2) call abort
4172 Index: gcc/testsuite/gfortran.dg/userdef_operator_2.f90
4173 ===================================================================
4174 --- gcc/testsuite/gfortran.dg/userdef_operator_2.f90 (.../tags/gcc_4_5_2_release) (wersja 0)
4175 +++ gcc/testsuite/gfortran.dg/userdef_operator_2.f90 (.../branches/gcc-4_5-branch) (wersja 170084)
4177 +! { dg-do compile }
4178 +! PR 45338 - no ICE when cmp is not used explicitly.
4179 +! Test case by Simon Smart
4183 + subroutine test_fn (cmp)
4184 + interface operator(.myop.)
4185 + pure function cmp (a, b) result(ret)
4186 + integer, intent(in) :: a, b
4191 + print*, a .myop. b
4192 + end subroutine test_fn
4193 +end module test_mod
4194 Index: gcc/testsuite/gfortran.dg/array_constructor_33.f90
4195 ===================================================================
4196 --- gcc/testsuite/gfortran.dg/array_constructor_33.f90 (.../tags/gcc_4_5_2_release) (wersja 170084)
4197 +++ gcc/testsuite/gfortran.dg/array_constructor_33.f90 (.../branches/gcc-4_5-branch) (wersja 170084)
4200 +! { dg-timeout-factor 4 }
4201 ! PR20923 gfortran slow for large array constructors.
4202 ! Test case prepared from PR by Jerry DeLisle <jvdelisle@gcc.gnu.org>
4204 Index: gcc/testsuite/gfortran.dg/pr46804.f90
4205 ===================================================================
4206 --- gcc/testsuite/gfortran.dg/pr46804.f90 (.../tags/gcc_4_5_2_release) (wersja 0)
4207 +++ gcc/testsuite/gfortran.dg/pr46804.f90 (.../branches/gcc-4_5-branch) (wersja 170084)
4209 +! PR rtl-optimization/46804
4211 +! { dg-options "-O -fPIC -fexpensive-optimizations -fgcse -foptimize-register-move -fpeel-loops -fno-tree-loop-optimize" }
4214 + integer, parameter :: n1 = 2, n2 = 3, n3 = 4, slen = 3
4215 + character (len = slen), dimension (n1, n2, n3) :: a
4216 + integer (kind = 1), dimension (2, 4) :: shift1
4217 + integer (kind = 2), dimension (2, 4) :: shift2
4218 + integer (kind = 4), dimension (2, 4) :: shift3
4222 + a (i1, i2, i3) = 'ab'(i1:i1) // 'cde'(i2:i2) // 'fghi'(i3:i3)
4226 + shift1 (1, :) = (/ 4, 11, 19, 20 /)
4227 + shift1 (2, :) = (/ 55, 5, 1, 2 /)
4230 + call test (cshift (a, shift2, 2))
4231 + call test (cshift (a, shift3, 2))
4233 + subroutine test (b)
4234 + character (len = slen), dimension (n1, n2, n3) :: b
4238 + i2p = mod (shift1 (i1, i3) + i2 - 1, n2) + 1
4239 + if (b (i1, i2, i3) .ne. a (i1, i2p, i3)) call abort
4243 + end subroutine test
4245 Index: gcc/testsuite/gfortran.dg/power2.f90
4246 ===================================================================
4247 --- gcc/testsuite/gfortran.dg/power2.f90 (.../tags/gcc_4_5_2_release) (wersja 170084)
4248 +++ gcc/testsuite/gfortran.dg/power2.f90 (.../branches/gcc-4_5-branch) (wersja 170084)
4250 INTEGER(KIND=1) :: k1
4251 INTEGER(KIND=2) :: k2
4259 Index: gcc/tree-ssa-copyrename.c
4260 ===================================================================
4261 --- gcc/tree-ssa-copyrename.c (.../tags/gcc_4_5_2_release) (wersja 170084)
4262 +++ gcc/tree-ssa-copyrename.c (.../branches/gcc-4_5-branch) (wersja 170084)
4263 @@ -225,11 +225,16 @@
4267 - /* Don't coalesce if the two variables are not of the same type. */
4268 - if (TREE_TYPE (root1) != TREE_TYPE (root2))
4269 + /* Don't coalesce if the two variables aren't type compatible . */
4270 + if (!types_compatible_p (TREE_TYPE (root1), TREE_TYPE (root2))
4271 + /* There is a disconnect between the middle-end type-system and
4272 + VRP, avoid coalescing enum types with different bounds. */
4273 + || ((TREE_CODE (TREE_TYPE (root1)) == ENUMERAL_TYPE
4274 + || TREE_CODE (TREE_TYPE (root2)) == ENUMERAL_TYPE)
4275 + && TREE_TYPE (root1) != TREE_TYPE (root2)))
4278 - fprintf (debug, " : Different types. No coalesce.\n");
4279 + fprintf (debug, " : Incompatible types. No coalesce.\n");
4283 Index: gcc/tree-ssa-ccp.c
4284 ===================================================================
4285 --- gcc/tree-ssa-ccp.c (.../tags/gcc_4_5_2_release) (wersja 170084)
4286 +++ gcc/tree-ssa-ccp.c (.../branches/gcc-4_5-branch) (wersja 170084)
4287 @@ -3355,7 +3355,9 @@
4288 is replaced. If the call is expected to produces a result, then it
4289 is replaced by an assignment of the new RHS to the result variable.
4290 If the result is to be ignored, then the call is replaced by a
4292 + GIMPLE_NOP. A proper VDEF chain is retained by making the first
4293 + VUSE and the last VDEF of the whole sequence be the same as the replaced
4294 + statement and using new SSA names for stores in between. */
4297 gimplify_and_update_call_from_tree (gimple_stmt_iterator *si_p, tree expr)
4298 @@ -3366,17 +3368,36 @@
4299 gimple_stmt_iterator i;
4300 gimple_seq stmts = gimple_seq_alloc();
4301 struct gimplify_ctx gctx;
4302 + gimple last = NULL;
4303 + gimple laststore = NULL;
4304 + tree reaching_vuse;
4306 stmt = gsi_stmt (*si_p);
4308 gcc_assert (is_gimple_call (stmt));
4310 lhs = gimple_call_lhs (stmt);
4311 + reaching_vuse = gimple_vuse (stmt);
4313 push_gimplify_context (&gctx);
4315 if (lhs == NULL_TREE)
4316 - gimplify_and_add (expr, &stmts);
4318 + gimplify_and_add (expr, &stmts);
4319 + /* We can end up with folding a memcpy of an empty class assignment
4320 + which gets optimized away by C++ gimplification. */
4321 + if (gimple_seq_empty_p (stmts))
4323 + pop_gimplify_context (NULL);
4324 + if (gimple_in_ssa_p (cfun))
4326 + unlink_stmt_vdef (stmt);
4327 + release_defs (stmt);
4329 + gsi_remove (si_p, true);
4334 tmp = get_initialized_tmp_var (expr, &stmts, NULL);
4336 @@ -3387,26 +3408,95 @@
4338 /* The replacement can expose previously unreferenced variables. */
4339 for (i = gsi_start (stmts); !gsi_end_p (i); gsi_next (&i))
4341 - new_stmt = gsi_stmt (i);
4342 - find_new_referenced_vars (new_stmt);
4343 - gsi_insert_before (si_p, new_stmt, GSI_NEW_STMT);
4344 - mark_symbols_for_renaming (new_stmt);
4350 + gsi_insert_before (si_p, last, GSI_NEW_STMT);
4353 + new_stmt = gsi_stmt (i);
4354 + if (gimple_in_ssa_p (cfun))
4356 + find_new_referenced_vars (new_stmt);
4357 + mark_symbols_for_renaming (new_stmt);
4359 + /* If the new statement has a VUSE, update it with exact SSA name we
4360 + know will reach this one. */
4361 + if (gimple_vuse (new_stmt))
4363 + /* If we've also seen a previous store create a new VDEF for
4364 + the latter one, and make that the new reaching VUSE. */
4367 + reaching_vuse = make_ssa_name (gimple_vop (cfun), laststore);
4368 + gimple_set_vdef (laststore, reaching_vuse);
4369 + update_stmt (laststore);
4372 + gimple_set_vuse (new_stmt, reaching_vuse);
4373 + gimple_set_modified (new_stmt, true);
4375 + if (gimple_assign_single_p (new_stmt)
4376 + && !is_gimple_reg (gimple_assign_lhs (new_stmt)))
4378 + laststore = new_stmt;
4383 if (lhs == NULL_TREE)
4385 - new_stmt = gimple_build_nop ();
4386 - unlink_stmt_vdef (stmt);
4387 - release_defs (stmt);
4388 + /* If we replace a call without LHS that has a VDEF and our new
4389 + sequence ends with a store we must make that store have the same
4390 + vdef in order not to break the sequencing. This can happen
4391 + for instance when folding memcpy calls into assignments. */
4392 + if (gimple_vdef (stmt) && laststore)
4394 + gimple_set_vdef (laststore, gimple_vdef (stmt));
4395 + if (TREE_CODE (gimple_vdef (stmt)) == SSA_NAME)
4396 + SSA_NAME_DEF_STMT (gimple_vdef (stmt)) = laststore;
4397 + update_stmt (laststore);
4399 + else if (gimple_in_ssa_p (cfun))
4401 + unlink_stmt_vdef (stmt);
4402 + release_defs (stmt);
4410 + gsi_insert_before (si_p, last, GSI_NEW_STMT);
4413 + if (laststore && is_gimple_reg (lhs))
4415 + gimple_set_vdef (laststore, gimple_vdef (stmt));
4416 + update_stmt (laststore);
4417 + if (TREE_CODE (gimple_vdef (stmt)) == SSA_NAME)
4418 + SSA_NAME_DEF_STMT (gimple_vdef (stmt)) = laststore;
4421 + else if (laststore)
4423 + reaching_vuse = make_ssa_name (gimple_vop (cfun), laststore);
4424 + gimple_set_vdef (laststore, reaching_vuse);
4425 + update_stmt (laststore);
4428 new_stmt = gimple_build_assign (lhs, tmp);
4429 - gimple_set_vuse (new_stmt, gimple_vuse (stmt));
4430 - gimple_set_vdef (new_stmt, gimple_vdef (stmt));
4431 - move_ssa_defining_stmt_for_defs (new_stmt, stmt);
4432 + if (!is_gimple_reg (tmp))
4433 + gimple_set_vuse (new_stmt, reaching_vuse);
4434 + if (!is_gimple_reg (lhs))
4436 + gimple_set_vdef (new_stmt, gimple_vdef (stmt));
4437 + if (TREE_CODE (gimple_vdef (stmt)) == SSA_NAME)
4438 + SSA_NAME_DEF_STMT (gimple_vdef (stmt)) = new_stmt;
4440 + else if (reaching_vuse == gimple_vuse (stmt))
4441 + unlink_stmt_vdef (stmt);
4444 gimple_set_location (new_stmt, gimple_location (stmt));
4445 Index: gcc/xcoffout.c
4446 ===================================================================
4447 --- gcc/xcoffout.c (.../tags/gcc_4_5_2_release) (wersja 170084)
4448 +++ gcc/xcoffout.c (.../branches/gcc-4_5-branch) (wersja 170084)
4450 #define ASM_OUTPUT_LINE(FILE,LINENUM) \
4453 + /* Make sure we're in a function and prevent output of .line 0, as \
4454 + line # 0 is meant for symbol addresses in xcoff. Additionally, \
4455 + line numbers are 'unsigned short' in 32-bit mode. */ \
4456 if (xcoff_begin_function_line >= 0) \
4457 - fprintf (FILE, "\t.line\t%d\n", ABS_OR_RELATIVE_LINENO (LINENUM)); \
4459 + int lno = ABS_OR_RELATIVE_LINENO (LINENUM); \
4460 + if (lno > 0 && (TARGET_64BIT || lno <= (int)USHRT_MAX)) \
4461 + fprintf (FILE, "\t.line\t%d\n", lno); \
4467 ===================================================================
4468 --- gcc/jump.c (.../tags/gcc_4_5_2_release) (wersja 170084)
4469 +++ gcc/jump.c (.../branches/gcc-4_5-branch) (wersja 170084)
4471 rtx prev_nonjump_insn = NULL;
4473 for (insn = f; insn; insn = NEXT_INSN (insn))
4474 - if (INSN_P (insn))
4475 + if (NONDEBUG_INSN_P (insn))
4477 mark_jump_label (PATTERN (insn), insn, 0);
4479 @@ -1728,7 +1728,13 @@
4482 if (XINT (x, i) != XINT (y, i))
4485 + if (((code == ASM_OPERANDS && i == 6)
4486 + || (code == ASM_INPUT && i == 1))
4487 + && locator_eq (XINT (x, i), XINT (y, i)))
4495 ===================================================================
4496 --- gcc/expr.c (.../tags/gcc_4_5_2_release) (wersja 170084)
4497 +++ gcc/expr.c (.../branches/gcc-4_5-branch) (wersja 170084)
4498 @@ -4730,7 +4730,10 @@
4499 /* If store_expr stores a DECL whose DECL_RTL(exp) == TARGET,
4500 but TARGET is not valid memory reference, TEMP will differ
4501 from TARGET although it is really the same location. */
4502 - && !(alt_rtl && rtx_equal_p (alt_rtl, target))
4504 + && rtx_equal_p (alt_rtl, target)
4505 + && !side_effects_p (alt_rtl)
4506 + && !side_effects_p (target))
4507 /* If there's nothing to copy, don't bother. Don't call
4508 expr_size unless necessary, because some front-ends (C++)
4509 expr_size-hook must not be given objects that are not
4510 Index: gcc/ada/ChangeLog
4511 ===================================================================
4512 --- gcc/ada/ChangeLog (.../tags/gcc_4_5_2_release) (wersja 170084)
4513 +++ gcc/ada/ChangeLog (.../branches/gcc-4_5-branch) (wersja 170084)
4515 +2011-02-08 Eric Botcazou <ebotcazou@adacore.com>
4517 + * gcc-interface/Makefile.in (x86-64 darwin): Handle multilibs.
4519 +2011-01-04 Eric Botcazou <ebotcazou@adacore.com>
4521 + * gcc-interface/trans.c (Subprogram_Body_to_gnu): Evaluate the
4522 + expressions of the parameter cache within the statement group of
4523 + the CICO mechanism.
4525 2010-12-16 Release Manager
4527 * GCC 4.5.2 released.
4528 Index: gcc/ada/gcc-interface/Makefile.in
4529 ===================================================================
4530 --- gcc/ada/gcc-interface/Makefile.in (.../tags/gcc_4_5_2_release) (wersja 170084)
4531 +++ gcc/ada/gcc-interface/Makefile.in (.../branches/gcc-4_5-branch) (wersja 170084)
4532 @@ -2143,11 +2143,17 @@
4533 s-taprop.adb<s-taprop-posix.adb \
4534 s-taspri.ads<s-taspri-posix.ads \
4535 s-tpopsp.adb<s-tpopsp-posix-foreign.adb \
4536 - a-numaux.ads<a-numaux-x86.ads \
4537 - a-numaux.adb<a-numaux-x86.adb \
4538 g-trasym.ads<g-trasym-unimplemented.ads \
4539 g-trasym.adb<g-trasym-unimplemented.adb \
4540 - system.ads<system-darwin-x86_64.ads
4541 + a-numaux.ads<a-numaux-x86.ads \
4542 + a-numaux.adb<a-numaux-x86.adb
4543 + ifeq ($(strip $(MULTISUBDIR)),/i386)
4544 + LIBGNAT_TARGET_PAIRS += \
4545 + system.ads<system-darwin-x86.ads
4547 + LIBGNAT_TARGET_PAIRS += \
4548 + system.ads<system-darwin-x86_64.ads
4552 ifeq ($(strip $(filter-out powerpc%,$(arch))),)
4553 Index: gcc/ada/gcc-interface/trans.c
4554 ===================================================================
4555 --- gcc/ada/gcc-interface/trans.c (.../tags/gcc_4_5_2_release) (wersja 170084)
4556 +++ gcc/ada/gcc-interface/trans.c (.../branches/gcc-4_5-branch) (wersja 170084)
4557 @@ -2303,6 +2303,31 @@
4559 gnu_result = end_stmt_group ();
4561 + /* If we populated the parameter attributes cache, we need to make sure that
4562 + the cached expressions are evaluated on all the possible paths leading to
4563 + their uses. So we force their evaluation on entry of the function. */
4564 + cache = DECL_STRUCT_FUNCTION (gnu_subprog_decl)->language->parm_attr_cache;
4567 + struct parm_attr_d *pa;
4570 + start_stmt_group ();
4572 + for (i = 0; VEC_iterate (parm_attr, cache, i, pa); i++)
4575 + add_stmt_with_node (pa->first, gnat_node);
4577 + add_stmt_with_node (pa->last, gnat_node);
4579 + add_stmt_with_node (pa->length, gnat_node);
4582 + add_stmt (gnu_result);
4583 + gnu_result = end_stmt_group ();
4586 /* If we are dealing with a return from an Ada procedure with parameters
4587 passed by copy-in/copy-out, we need to return a record containing the
4588 final values of these parameters. If the list contains only one entry,
4589 @@ -2341,30 +2366,6 @@
4591 pop_stack (&gnu_return_label_stack);
4593 - /* If we populated the parameter attributes cache, we need to make sure
4594 - that the cached expressions are evaluated on all possible paths. */
4595 - cache = DECL_STRUCT_FUNCTION (gnu_subprog_decl)->language->parm_attr_cache;
4598 - struct parm_attr_d *pa;
4601 - start_stmt_group ();
4603 - for (i = 0; VEC_iterate (parm_attr, cache, i, pa); i++)
4606 - add_stmt_with_node (pa->first, gnat_node);
4608 - add_stmt_with_node (pa->last, gnat_node);
4610 - add_stmt_with_node (pa->length, gnat_node);
4613 - add_stmt (gnu_result);
4614 - gnu_result = end_stmt_group ();
4617 /* Set the end location. */
4619 ((Present (End_Label (Handled_Statement_Sequence (gnat_node)))
4620 Index: gcc/fortran/openmp.c
4621 ===================================================================
4622 --- gcc/fortran/openmp.c (.../tags/gcc_4_5_2_release) (wersja 170084)
4623 +++ gcc/fortran/openmp.c (.../branches/gcc-4_5-branch) (wersja 170084)
4624 @@ -1363,6 +1363,31 @@
4628 +/* Save and clear openmp.c private state. */
4631 +gfc_omp_save_and_clear_state (struct gfc_omp_saved_state *state)
4633 + state->ptrs[0] = omp_current_ctx;
4634 + state->ptrs[1] = omp_current_do_code;
4635 + state->ints[0] = omp_current_do_collapse;
4636 + omp_current_ctx = NULL;
4637 + omp_current_do_code = NULL;
4638 + omp_current_do_collapse = 0;
4642 +/* Restore openmp.c private state from the saved state. */
4645 +gfc_omp_restore_state (struct gfc_omp_saved_state *state)
4647 + omp_current_ctx = (struct omp_context *) state->ptrs[0];
4648 + omp_current_do_code = (gfc_code *) state->ptrs[1];
4649 + omp_current_do_collapse = state->ints[0];
4653 /* Note a DO iterator variable. This is special in !$omp parallel
4654 construct, where they are predetermined private. */
4656 Index: gcc/fortran/interface.c
4657 ===================================================================
4658 --- gcc/fortran/interface.c (.../tags/gcc_4_5_2_release) (wersja 170084)
4659 +++ gcc/fortran/interface.c (.../branches/gcc-4_5-branch) (wersja 170084)
4660 @@ -624,11 +624,12 @@
4662 /* Allowed are (per F2003, 12.3.2.1.2 Defined assignments):
4663 - First argument an array with different rank than second,
4664 - - Types and kinds do not conform, and
4665 + - First argument is a scalar and second an array,
4666 + - Types and kinds do not conform, or
4667 - First argument is of derived type. */
4668 if (sym->formal->sym->ts.type != BT_DERIVED
4669 && sym->formal->sym->ts.type != BT_CLASS
4670 - && (r1 == 0 || r1 == r2)
4671 + && (r2 == 0 || r1 == r2)
4672 && (sym->formal->sym->ts.type == sym->formal->next->sym->ts.type
4673 || (gfc_numeric_ts (&sym->formal->sym->ts)
4674 && gfc_numeric_ts (&sym->formal->next->sym->ts))))
4675 Index: gcc/fortran/trans-array.c
4676 ===================================================================
4677 --- gcc/fortran/trans-array.c (.../tags/gcc_4_5_2_release) (wersja 170084)
4678 +++ gcc/fortran/trans-array.c (.../branches/gcc-4_5-branch) (wersja 170084)
4679 @@ -3389,7 +3389,38 @@
4683 +/* Return true if both symbols could refer to the same data object. Does
4684 + not take account of aliasing due to equivalence statements. */
4687 +symbols_could_alias (gfc_symbol *lsym, gfc_symbol *rsym, bool lsym_pointer,
4688 + bool lsym_target, bool rsym_pointer, bool rsym_target)
4690 + /* Aliasing isn't possible if the symbols have different base types. */
4691 + if (gfc_compare_types (&lsym->ts, &rsym->ts) == 0)
4694 + /* Pointers can point to other pointers and target objects. */
4696 + if ((lsym_pointer && (rsym_pointer || rsym_target))
4697 + || (rsym_pointer && (lsym_pointer || lsym_target)))
4700 + /* Special case: Argument association, cf. F90 12.4.1.6, F2003 12.4.1.7
4701 + and F2008 12.5.2.13 items 3b and 4b. The pointer case (a) is already
4703 + if (lsym->attr.target && rsym->attr.target
4704 + && ((lsym->attr.dummy
4705 + && (!lsym->attr.dimension || lsym->as->type == AS_ASSUMED_SHAPE))
4706 + || (rsym->attr.dummy
4707 + && (!rsym->attr.dimension
4708 + || rsym->as->type == AS_ASSUMED_SHAPE))))
4715 /* Return true if the two SS could be aliased, i.e. both point to the same data
4717 /* TODO: resolve aliases based on frontend expressions. */
4718 @@ -3401,10 +3432,18 @@
4722 + bool lsym_pointer, lsym_target, rsym_pointer, rsym_target;
4724 lsym = lss->expr->symtree->n.sym;
4725 rsym = rss->expr->symtree->n.sym;
4726 - if (gfc_symbols_could_alias (lsym, rsym))
4728 + lsym_pointer = lsym->attr.pointer;
4729 + lsym_target = lsym->attr.target;
4730 + rsym_pointer = rsym->attr.pointer;
4731 + rsym_target = rsym->attr.target;
4733 + if (symbols_could_alias (lsym, rsym, lsym_pointer, lsym_target,
4734 + rsym_pointer, rsym_target))
4737 if (rsym->ts.type != BT_DERIVED
4738 @@ -3419,27 +3458,75 @@
4739 if (lref->type != REF_COMPONENT)
4742 - if (gfc_symbols_could_alias (lref->u.c.sym, rsym))
4743 + lsym_pointer = lsym_pointer || lref->u.c.sym->attr.pointer;
4744 + lsym_target = lsym_target || lref->u.c.sym->attr.target;
4746 + if (symbols_could_alias (lref->u.c.sym, rsym, lsym_pointer, lsym_target,
4747 + rsym_pointer, rsym_target))
4750 + if ((lsym_pointer && (rsym_pointer || rsym_target))
4751 + || (rsym_pointer && (lsym_pointer || lsym_target)))
4753 + if (gfc_compare_types (&lref->u.c.component->ts,
4758 for (rref = rss->expr->ref; rref != rss->data.info.ref;
4761 if (rref->type != REF_COMPONENT)
4764 - if (gfc_symbols_could_alias (lref->u.c.sym, rref->u.c.sym))
4765 + rsym_pointer = rsym_pointer || rref->u.c.sym->attr.pointer;
4766 + rsym_target = lsym_target || rref->u.c.sym->attr.target;
4768 + if (symbols_could_alias (lref->u.c.sym, rref->u.c.sym,
4769 + lsym_pointer, lsym_target,
4770 + rsym_pointer, rsym_target))
4773 + if ((lsym_pointer && (rsym_pointer || rsym_target))
4774 + || (rsym_pointer && (lsym_pointer || lsym_target)))
4776 + if (gfc_compare_types (&lref->u.c.component->ts,
4777 + &rref->u.c.sym->ts))
4779 + if (gfc_compare_types (&lref->u.c.sym->ts,
4780 + &rref->u.c.component->ts))
4782 + if (gfc_compare_types (&lref->u.c.component->ts,
4783 + &rref->u.c.component->ts))
4789 + lsym_pointer = lsym->attr.pointer;
4790 + lsym_target = lsym->attr.target;
4791 + lsym_pointer = lsym->attr.pointer;
4792 + lsym_target = lsym->attr.target;
4794 for (rref = rss->expr->ref; rref != rss->data.info.ref; rref = rref->next)
4796 if (rref->type != REF_COMPONENT)
4799 - if (gfc_symbols_could_alias (rref->u.c.sym, lsym))
4800 + rsym_pointer = rsym_pointer || rref->u.c.sym->attr.pointer;
4801 + rsym_target = lsym_target || rref->u.c.sym->attr.target;
4803 + if (symbols_could_alias (rref->u.c.sym, lsym,
4804 + lsym_pointer, lsym_target,
4805 + rsym_pointer, rsym_target))
4808 + if ((lsym_pointer && (rsym_pointer || rsym_target))
4809 + || (rsym_pointer && (lsym_pointer || lsym_target)))
4811 + if (gfc_compare_types (&lsym->ts, &rref->u.c.component->ts))
4817 Index: gcc/fortran/symbol.c
4818 ===================================================================
4819 --- gcc/fortran/symbol.c (.../tags/gcc_4_5_2_release) (wersja 170084)
4820 +++ gcc/fortran/symbol.c (.../branches/gcc-4_5-branch) (wersja 170084)
4821 @@ -2733,41 +2733,6 @@
4825 -/* Return true if both symbols could refer to the same data object. Does
4826 - not take account of aliasing due to equivalence statements. */
4829 -gfc_symbols_could_alias (gfc_symbol *lsym, gfc_symbol *rsym)
4831 - /* Aliasing isn't possible if the symbols have different base types. */
4832 - if (gfc_compare_types (&lsym->ts, &rsym->ts) == 0)
4835 - /* Pointers can point to other pointers, target objects and allocatable
4836 - objects. Two allocatable objects cannot share the same storage. */
4837 - if (lsym->attr.pointer
4838 - && (rsym->attr.pointer || rsym->attr.allocatable || rsym->attr.target))
4840 - if (lsym->attr.target && rsym->attr.pointer)
4842 - if (lsym->attr.allocatable && rsym->attr.pointer)
4845 - /* Special case: Argument association, cf. F90 12.4.1.6, F2003 12.4.1.7
4846 - and F2008 12.5.2.13 items 3b and 4b. The pointer case (a) is already
4848 - if (lsym->attr.target && rsym->attr.target
4849 - && ((lsym->attr.dummy
4850 - && (!lsym->attr.dimension || lsym->as->type == AS_ASSUMED_SHAPE))
4851 - || (rsym->attr.dummy
4852 - && (!rsym->attr.dimension
4853 - || rsym->as->type == AS_ASSUMED_SHAPE))))
4860 /* Undoes all the changes made to symbols in the current statement.
4861 This subroutine is made simpler due to the fact that attributes are
4862 never removed once added. */
4863 Index: gcc/fortran/trans-openmp.c
4864 ===================================================================
4865 --- gcc/fortran/trans-openmp.c (.../tags/gcc_4_5_2_release) (wersja 170084)
4866 +++ gcc/fortran/trans-openmp.c (.../branches/gcc-4_5-branch) (wersja 170084)
4867 @@ -480,13 +480,23 @@
4868 gfc_symbol init_val_sym, outer_sym, intrinsic_sym;
4869 gfc_expr *e1, *e2, *e3, *e4;
4871 - tree decl, backend_decl, stmt;
4872 + tree decl, backend_decl, stmt, type, outer_decl;
4873 locus old_loc = gfc_current_locus;
4877 decl = OMP_CLAUSE_DECL (c);
4878 gfc_current_locus = where;
4879 + type = TREE_TYPE (decl);
4880 + outer_decl = create_tmp_var_raw (type, NULL);
4881 + if (TREE_CODE (decl) == PARM_DECL
4882 + && TREE_CODE (type) == REFERENCE_TYPE
4883 + && GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (type))
4884 + && GFC_TYPE_ARRAY_AKIND (TREE_TYPE (type)) == GFC_ARRAY_ALLOCATABLE)
4886 + decl = build_fold_indirect_ref (decl);
4887 + type = TREE_TYPE (type);
4890 /* Create a fake symbol for init value. */
4891 memset (&init_val_sym, 0, sizeof (init_val_sym));
4893 outer_sym.attr.dummy = 0;
4894 outer_sym.attr.result = 0;
4895 outer_sym.attr.flavor = FL_VARIABLE;
4896 - outer_sym.backend_decl = create_tmp_var_raw (TREE_TYPE (decl), NULL);
4897 + outer_sym.backend_decl = outer_decl;
4898 + if (decl != OMP_CLAUSE_DECL (c))
4899 + outer_sym.backend_decl = build_fold_indirect_ref (outer_decl);
4901 /* Create fake symtrees for it. */
4902 symtree1 = gfc_new_symtree (&root1, sym->name);
4903 @@ -622,12 +634,12 @@
4905 /* Create the init statement list. */
4907 - if (GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (decl))
4908 - && GFC_TYPE_ARRAY_AKIND (TREE_TYPE (decl)) == GFC_ARRAY_ALLOCATABLE)
4909 + if (GFC_DESCRIPTOR_TYPE_P (type)
4910 + && GFC_TYPE_ARRAY_AKIND (type) == GFC_ARRAY_ALLOCATABLE)
4912 /* If decl is an allocatable array, it needs to be allocated
4913 with the same bounds as the outer var. */
4914 - tree type = TREE_TYPE (decl), rank, size, esize, ptr;
4915 + tree rank, size, esize, ptr;
4918 gfc_start_block (&block);
4921 /* Create the merge statement list. */
4923 - if (GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (decl))
4924 - && GFC_TYPE_ARRAY_AKIND (TREE_TYPE (decl)) == GFC_ARRAY_ALLOCATABLE)
4925 + if (GFC_DESCRIPTOR_TYPE_P (type)
4926 + && GFC_TYPE_ARRAY_AKIND (type) == GFC_ARRAY_ALLOCATABLE)
4928 /* If decl is an allocatable array, it needs to be deallocated
4931 OMP_CLAUSE_REDUCTION_MERGE (c) = stmt;
4933 /* And stick the placeholder VAR_DECL into the clause as well. */
4934 - OMP_CLAUSE_REDUCTION_PLACEHOLDER (c) = outer_sym.backend_decl;
4935 + OMP_CLAUSE_REDUCTION_PLACEHOLDER (c) = outer_decl;
4937 gfc_current_locus = old_loc;
4939 Index: gcc/fortran/gfortran.h
4940 ===================================================================
4941 --- gcc/fortran/gfortran.h (.../tags/gcc_4_5_2_release) (wersja 170084)
4942 +++ gcc/fortran/gfortran.h (.../branches/gcc-4_5-branch) (wersja 170084)
4943 @@ -2483,8 +2483,6 @@
4944 int gfc_get_ha_symbol (const char *, gfc_symbol **);
4945 int gfc_get_ha_sym_tree (const char *, gfc_symtree **);
4947 -int gfc_symbols_could_alias (gfc_symbol *, gfc_symbol *);
4949 void gfc_undo_symbols (void);
4950 void gfc_commit_symbols (void);
4951 void gfc_commit_symbol (gfc_symbol *);
4952 @@ -2577,11 +2575,14 @@
4953 gfc_expr *gfc_get_parentheses (gfc_expr *);
4956 +struct gfc_omp_saved_state { void *ptrs[2]; int ints[1]; };
4957 void gfc_free_omp_clauses (gfc_omp_clauses *);
4958 void gfc_resolve_omp_directive (gfc_code *, gfc_namespace *);
4959 void gfc_resolve_do_iterator (gfc_code *, gfc_symbol *);
4960 void gfc_resolve_omp_parallel_blocks (gfc_code *, gfc_namespace *);
4961 void gfc_resolve_omp_do_blocks (gfc_code *, gfc_namespace *);
4962 +void gfc_omp_save_and_clear_state (struct gfc_omp_saved_state *);
4963 +void gfc_omp_restore_state (struct gfc_omp_saved_state *);
4966 void gfc_free_actual_arglist (gfc_actual_arglist *);
4967 Index: gcc/fortran/error.c
4968 ===================================================================
4969 --- gcc/fortran/error.c (.../tags/gcc_4_5_2_release) (wersja 170084)
4970 +++ gcc/fortran/error.c (.../branches/gcc-4_5-branch) (wersja 170084)
4974 if (flag_fatal_errors)
4976 + exit (FATAL_EXIT_CODE);
4981 error_print (_("Fatal Error:"), _(gmsgid), argp);
4985 + exit (FATAL_EXIT_CODE);
4989 @@ -1019,7 +1019,7 @@
4990 gfc_increment_error_count();
4992 if (flag_fatal_errors)
4994 + exit (FATAL_EXIT_CODE);
4998 Index: gcc/fortran/ChangeLog
4999 ===================================================================
5000 --- gcc/fortran/ChangeLog (.../tags/gcc_4_5_2_release) (wersja 170084)
5001 +++ gcc/fortran/ChangeLog (.../branches/gcc-4_5-branch) (wersja 170084)
5003 +2011-01-25 Tobias Burnus <burnus@net-b.de>
5005 + Backport from mainline
5006 + 2011-01-17 Jakub Jelinek <jakub@redhat.com>
5009 + * gfortran.h (struct gfc_omp_saved_state): New type.
5010 + (gfc_omp_save_and_clear_state, gfc_omp_restore_state): New prototypes.
5011 + * resolve.c (resolve_global_procedure): Call it around gfc_resolve
5013 + * openmp.c (gfc_omp_save_and_clear_state, gfc_omp_restore_state): New
5016 +2011-01-25 Tobias Burnus <burnus@net-b.de>
5019 + * interface.c (gfc_check_operator_interface): Fix
5020 + defined-assignment check.
5022 +2011-01-21 Tobias Burnus <burnus@net-b.de>
5025 + * error.c (gfc_error_now, gfc_fatal_error, gfc_error_check):
5026 + Use defined instead of magic number exit status codes.
5027 + * scanner.c (include_line, gfc_new_file): Ditto.
5028 + * gfortranspec.c (lang_specific_driver): Ditto.
5030 +2011-01-16 Jakub Jelinek <jakub@redhat.com>
5032 + Backport from mainline
5033 + 2010-12-14 Jakub Jelinek <jakub@redhat.com>
5036 + * trans-openmp.c (gfc_trans_omp_array_reduction): Handle allocatable
5039 +2011-01-16 Thomas Koenig <tkoenig@gcc.gnu.org>
5041 + Backport from trunk
5043 + * symbol.c (gfc_symbols_could_alias): Strip gfc_ prefix,
5044 + make static and move in front of its only caller, to ...
5045 + * trans-array.c (symbols_could_alias): ... here.
5046 + Pass information about pointer and target status as
5047 + arguments. Allocatable arrays don't alias anything
5048 + unless they have the POINTER attribute.
5049 + (gfc_could_be_alias): Keep track of pointer and target
5050 + status when following references. Also check if typespecs
5051 + of components match those of other components or symbols.
5052 + * gfortran.h: Remove prototype for gfc_symbols_could_alias.
5054 +2011-01-02 Thomas Koenig <tkoenig@gcc.gnu.org>
5056 + Backport from mainline
5058 + * resolve.c (resolve_operator): Mark function for user-defined
5059 + operator as referenced.
5061 2010-12-16 Release Manager
5063 * GCC 4.5.2 released.
5064 Index: gcc/fortran/scanner.c
5065 ===================================================================
5066 --- gcc/fortran/scanner.c (.../tags/gcc_4_5_2_release) (wersja 170084)
5067 +++ gcc/fortran/scanner.c (.../branches/gcc-4_5-branch) (wersja 170084)
5068 @@ -1841,7 +1841,7 @@
5070 filename = gfc_widechar_to_char (begin, -1);
5071 if (load_file (filename, NULL, false) == FAILURE)
5073 + exit (FATAL_EXIT_CODE);
5075 gfc_free (filename);
5077 @@ -2045,7 +2045,7 @@
5078 printf ("%s:%3d %s\n", LOCATION_FILE (line_head->location),
5079 LOCATION_LINE (line_head->location), line_head->line);
5082 + exit (SUCCESS_EXIT_CODE);
5086 Index: gcc/fortran/gfortranspec.c
5087 ===================================================================
5088 --- gcc/fortran/gfortranspec.c (.../tags/gcc_4_5_2_release) (wersja 170084)
5089 +++ gcc/fortran/gfortranspec.c (.../branches/gcc-4_5-branch) (wersja 170084)
5091 You may redistribute copies of GNU Fortran\n\
5092 under the terms of the GNU General Public License.\n\
5093 For more information about these matters, see the file named COPYING\n\n"));
5095 + exit (SUCCESS_EXIT_CODE);
5099 Index: gcc/fortran/resolve.c
5100 ===================================================================
5101 --- gcc/fortran/resolve.c (.../tags/gcc_4_5_2_release) (wersja 170084)
5102 +++ gcc/fortran/resolve.c (.../branches/gcc-4_5-branch) (wersja 170084)
5103 @@ -1810,11 +1810,14 @@
5104 if (!gsym->ns->resolved)
5106 gfc_dt_list *old_dt_list;
5107 + struct gfc_omp_saved_state old_omp_state;
5109 /* Stash away derived types so that the backend_decls do not
5111 old_dt_list = gfc_derived_types;
5112 gfc_derived_types = NULL;
5113 + /* And stash away openmp state. */
5114 + gfc_omp_save_and_clear_state (&old_omp_state);
5116 gfc_resolve (gsym->ns);
5118 @@ -1824,6 +1827,8 @@
5120 /* Restore the derived types of this namespace. */
5121 gfc_derived_types = old_dt_list;
5122 + /* And openmp state. */
5123 + gfc_omp_restore_state (&old_omp_state);
5126 /* Make sure that translation for the gsymbol occurs before
5127 @@ -3577,9 +3582,12 @@
5128 sprintf (msg, _("Operand of user operator '%s' at %%L is %s"),
5129 e->value.op.uop->name, gfc_typename (&op1->ts));
5131 - sprintf (msg, _("Operands of user operator '%s' at %%L are %s/%s"),
5132 - e->value.op.uop->name, gfc_typename (&op1->ts),
5133 - gfc_typename (&op2->ts));
5135 + sprintf (msg, _("Operands of user operator '%s' at %%L are %s/%s"),
5136 + e->value.op.uop->name, gfc_typename (&op1->ts),
5137 + gfc_typename (&op2->ts));
5138 + e->value.op.uop->op->sym->attr.referenced = 1;
5143 Index: gcc/regmove.c
5144 ===================================================================
5145 --- gcc/regmove.c (.../tags/gcc_4_5_2_release) (wersja 170084)
5146 +++ gcc/regmove.c (.../branches/gcc-4_5-branch) (wersja 170084)
5148 rtx src_reg = XEXP (src, 0);
5149 int src_no = REGNO (src_reg);
5150 int dst_no = REGNO (dest);
5152 + rtx p, set, set_insn;
5153 enum machine_mode old_mode;
5154 basic_block bb = BLOCK_FOR_INSN (insn);
5157 GET_MODE_BITSIZE (GET_MODE (src_reg))))
5161 old_mode = GET_MODE (src_reg);
5162 PUT_MODE (src_reg, GET_MODE (src));
5163 XEXP (src, 0) = SET_SRC (set);
5164 @@ -583,9 +584,19 @@
5168 - rtx note = find_reg_note (p, REG_EQUAL, NULL_RTX);
5169 + rtx note = find_reg_note (set_insn, REG_EQUAL, NULL_RTX);
5171 - remove_note (p, note);
5173 + if (rtx_equal_p (XEXP (note, 0), XEXP (src, 0)))
5176 + = gen_rtx_fmt_e (GET_CODE (src), GET_MODE (src),
5178 + df_notes_rescan (set_insn);
5181 + remove_note (set_insn, note);
5187 ===================================================================
5188 --- gcc/BASE-VER (.../tags/gcc_4_5_2_release) (wersja 170084)
5189 +++ gcc/BASE-VER (.../branches/gcc-4_5-branch) (wersja 170084)
5193 Index: gcc/tree-data-ref.c
5194 ===================================================================
5195 --- gcc/tree-data-ref.c (.../tags/gcc_4_5_2_release) (wersja 170084)
5196 +++ gcc/tree-data-ref.c (.../branches/gcc-4_5-branch) (wersja 170084)
5197 @@ -4594,7 +4594,7 @@
5198 for (e = v->succ; e; e = e->succ_next)
5199 fprintf (file, " %d", e->dest);
5201 - fprintf (file, ") \n");
5202 + fprintf (file, ")\n");
5203 print_gimple_stmt (file, RDGV_STMT (v), 0, TDF_VOPS|TDF_MEMSYMS);
5204 fprintf (file, ")\n");
5206 @@ -4991,6 +4991,38 @@
5210 +/* Returns true when the statement at STMT is of the form "A[i] = 0"
5211 + that contains a data reference on its LHS with a stride of the same
5212 + size as its unit type. */
5215 +stmt_with_adjacent_zero_store_dr_p (gimple stmt)
5219 + struct data_reference *dr;
5222 + || !gimple_vdef (stmt)
5223 + || !is_gimple_assign (stmt)
5224 + || !gimple_assign_single_p (stmt)
5225 + || !(op1 = gimple_assign_rhs1 (stmt))
5226 + || !(integer_zerop (op1) || real_zerop (op1)))
5229 + dr = XCNEW (struct data_reference);
5230 + op0 = gimple_assign_lhs (stmt);
5232 + DR_STMT (dr) = stmt;
5233 + DR_REF (dr) = op0;
5235 + res = dr_analyze_innermost (dr)
5236 + && stride_of_unit_type_p (DR_STEP (dr), TREE_TYPE (op0));
5238 + free_data_ref (dr);
5242 /* For a data reference REF, return the declaration of its base
5243 address or NULL_TREE if the base is not determined. */
5245 Index: gcc/tree-data-ref.h
5246 ===================================================================
5247 --- gcc/tree-data-ref.h (.../tags/gcc_4_5_2_release) (wersja 170084)
5248 +++ gcc/tree-data-ref.h (.../branches/gcc-4_5-branch) (wersja 170084)
5249 @@ -567,7 +567,19 @@
5250 void remove_similar_memory_refs (VEC (gimple, heap) **);
5251 bool rdg_defs_used_in_other_loops_p (struct graph *, int);
5252 bool have_similar_memory_accesses (gimple, gimple);
5253 +bool stmt_with_adjacent_zero_store_dr_p (gimple);
5255 +/* Returns true when STRIDE is equal in absolute value to the size of
5256 + the unit type of TYPE. */
5259 +stride_of_unit_type_p (tree stride, tree type)
5261 + return tree_int_cst_equal (fold_unary (ABS_EXPR, TREE_TYPE (stride),
5263 + TYPE_SIZE_UNIT (type));
5266 /* Determines whether RDG vertices V1 and V2 access to similar memory
5267 locations, in which case they have to be in the same partition. */
5269 Index: gcc/c-typeck.c
5270 ===================================================================
5271 --- gcc/c-typeck.c (.../tags/gcc_4_5_2_release) (wersja 170084)
5272 +++ gcc/c-typeck.c (.../branches/gcc-4_5-branch) (wersja 170084)
5273 @@ -5025,10 +5025,10 @@
5276 bool save = in_late_binary_op;
5277 - if (codel == BOOLEAN_TYPE)
5278 + if (codel == BOOLEAN_TYPE || codel == COMPLEX_TYPE)
5279 in_late_binary_op = true;
5280 ret = convert_and_check (type, orig_rhs);
5281 - if (codel == BOOLEAN_TYPE)
5282 + if (codel == BOOLEAN_TYPE || codel == COMPLEX_TYPE)
5283 in_late_binary_op = save;
5286 Index: gcc/cfgexpand.c
5287 ===================================================================
5288 --- gcc/cfgexpand.c (.../tags/gcc_4_5_2_release) (wersja 170084)
5289 +++ gcc/cfgexpand.c (.../branches/gcc-4_5-branch) (wersja 170084)
5290 @@ -2578,7 +2578,7 @@
5291 enum machine_mode opmode = GET_MODE (op0);
5293 if (opmode == VOIDmode)
5295 + opmode = TYPE_MODE (TREE_TYPE (tem));
5297 /* This condition may hold if we're expanding the address
5298 right past the end of an array that turned out not to
5299 @@ -2599,7 +2599,8 @@
5301 : ZERO_EXTRACT, mode,
5302 GET_MODE (op0) != VOIDmode
5303 - ? GET_MODE (op0) : mode1,
5305 + : TYPE_MODE (TREE_TYPE (tem)),
5306 op0, GEN_INT (bitsize), GEN_INT (bitpos));
5309 Index: gcc/graphite.c
5310 ===================================================================
5311 --- gcc/graphite.c (.../tags/gcc_4_5_2_release) (wersja 170084)
5312 +++ gcc/graphite.c (.../branches/gcc-4_5-branch) (wersja 170084)
5318 recompute_all_dominators ();
5319 initialize_original_copy_tables ();
5320 cloog_initialize ();
5321 Index: gcc/tree-ssa-pre.c
5322 ===================================================================
5323 --- gcc/tree-ssa-pre.c (.../tags/gcc_4_5_2_release) (wersja 170084)
5324 +++ gcc/tree-ssa-pre.c (.../branches/gcc-4_5-branch) (wersja 170084)
5325 @@ -1701,7 +1701,7 @@
5326 tree result = vn_reference_lookup_pieces (newvuse, ref->set,
5330 + &newref, VN_WALK);
5332 VEC_free (vn_reference_op_s, heap, newoperands);
5334 @@ -2558,6 +2558,10 @@
5336 if (dump_file && (dump_flags & TDF_DETAILS))
5337 fprintf (dump_file, "Starting iteration %d\n", num_iterations);
5338 + /* ??? We need to clear our PHI translation cache here as the
5339 + ANTIC sets shrink and we restrict valid translations to
5340 + those having operands with leaders in ANTIC. Same below
5341 + for PA ANTIC computation. */
5344 for (i = n_basic_blocks - NUM_FIXED_BLOCKS - 1; i >= 0; i--)
5345 @@ -3965,7 +3969,7 @@
5346 copy_reference_ops_from_call (stmt, &ops);
5347 vn_reference_lookup_pieces (gimple_vuse (stmt), 0,
5348 gimple_expr_type (stmt),
5349 - ops, &ref, false);
5350 + ops, &ref, VN_NOWALK);
5351 VEC_free (vn_reference_op_s, heap, ops);
5354 @@ -4035,7 +4039,7 @@
5356 vn_reference_lookup (gimple_assign_rhs1 (stmt),
5363 @@ -4265,7 +4269,7 @@
5364 tree rhs = gimple_assign_rhs1 (stmt);
5366 val = vn_reference_lookup (gimple_assign_lhs (stmt),
5367 - gimple_vuse (stmt), true, NULL);
5368 + gimple_vuse (stmt), VN_WALK, NULL);
5369 if (TREE_CODE (rhs) == SSA_NAME)
5370 rhs = VN_INFO (rhs)->valnum;
5372 Index: gcc/cfgcleanup.c
5373 ===================================================================
5374 --- gcc/cfgcleanup.c (.../tags/gcc_4_5_2_release) (wersja 170084)
5375 +++ gcc/cfgcleanup.c (.../branches/gcc-4_5-branch) (wersja 170084)
5376 @@ -482,15 +482,20 @@
5377 /* When not optimizing, ensure that edges or forwarder
5378 blocks with different locus are not optimized out. */
5379 int locus = single_succ_edge (target)->goto_locus;
5382 if (locus && goto_locus && !locator_eq (locus, goto_locus))
5383 counter = n_basic_blocks;
5387 - if (INSN_P (BB_END (target)))
5388 + last = BB_END (target);
5389 + if (DEBUG_INSN_P (last))
5390 + last = prev_nondebug_insn (last);
5392 + if (last && INSN_P (last))
5394 - locus = INSN_LOCATOR (BB_END (target));
5395 + locus = INSN_LOCATOR (last);
5397 if (locus && goto_locus
5398 && !locator_eq (locus, goto_locus))
5399 @@ -1923,8 +1928,7 @@
5402 delete_basic_block (b);
5403 - if (!(mode & CLEANUP_CFGLAYOUT))
5406 /* Avoid trying to remove ENTRY_BLOCK_PTR. */
5407 b = (c == ENTRY_BLOCK_PTR ? c->next_bb : c);
5409 Index: gcc/tree-sra.c
5410 ===================================================================
5411 --- gcc/tree-sra.c (.../tags/gcc_4_5_2_release) (wersja 170084)
5412 +++ gcc/tree-sra.c (.../branches/gcc-4_5-branch) (wersja 170084)
5413 @@ -3413,7 +3413,10 @@
5414 else if (ac2->size != access->size)
5417 - if (access_precludes_ipa_sra_p (ac2))
5418 + if (access_precludes_ipa_sra_p (ac2)
5419 + || (ac2->type != access->type
5420 + && (TREE_ADDRESSABLE (ac2->type)
5421 + || TREE_ADDRESSABLE (access->type))))
5424 modification |= ac2->write;
5425 Index: gcc/c-convert.c
5426 ===================================================================
5427 --- gcc/c-convert.c (.../tags/gcc_4_5_2_release) (wersja 170084)
5428 +++ gcc/c-convert.c (.../branches/gcc-4_5-branch) (wersja 170084)
5429 @@ -131,6 +131,32 @@
5433 + /* If converting from COMPLEX_TYPE to a different COMPLEX_TYPE
5434 + and e is not COMPLEX_EXPR, convert_to_complex uses save_expr,
5435 + but for the C FE c_save_expr needs to be called instead. */
5436 + if (TREE_CODE (TREE_TYPE (e)) == COMPLEX_TYPE)
5438 + tree subtype = TREE_TYPE (type);
5439 + tree elt_type = TREE_TYPE (TREE_TYPE (e));
5441 + if (TYPE_MAIN_VARIANT (elt_type) != TYPE_MAIN_VARIANT (subtype)
5442 + && TREE_CODE (e) != COMPLEX_EXPR)
5444 + if (in_late_binary_op)
5445 + e = save_expr (e);
5447 + e = c_save_expr (e);
5449 + = fold_build2 (COMPLEX_EXPR, type,
5451 + fold_build1 (REALPART_EXPR,
5454 + fold_build1 (IMAGPART_EXPR,
5459 ret = convert_to_complex (type, e);
5462 Index: gcc/tree-ssa-ter.c
5463 ===================================================================
5464 --- gcc/tree-ssa-ter.c (.../tags/gcc_4_5_2_release) (wersja 170084)
5465 +++ gcc/tree-ssa-ter.c (.../branches/gcc-4_5-branch) (wersja 170084)
5469 /* Without alias info we can't move around loads. */
5470 - if (gimple_references_memory_p (stmt) && !optimize)
5472 + && gimple_assign_single_p (stmt)
5473 + && !is_gimple_val (gimple_assign_rhs1 (stmt)))
5476 /* Float expressions must go through memory if float-store is on. */
5478 ===================================================================
5479 --- gcc/rtl.c (.../tags/gcc_4_5_2_release) (wersja 170084)
5480 +++ gcc/rtl.c (.../branches/gcc-4_5-branch) (wersja 170084)
5481 @@ -429,7 +429,15 @@
5484 if (XINT (x, i) != XINT (y, i))
5487 +#ifndef GENERATOR_FILE
5488 + if (((code == ASM_OPERANDS && i == 6)
5489 + || (code == ASM_INPUT && i == 1))
5490 + && locator_eq (XINT (x, i), XINT (y, i)))
5498 @@ -549,7 +557,15 @@
5501 if (XINT (x, i) != XINT (y, i))
5504 +#ifndef GENERATOR_FILE
5505 + if (((code == ASM_OPERANDS && i == 6)
5506 + || (code == ASM_INPUT && i == 1))
5507 + && locator_eq (XINT (x, i), XINT (y, i)))
5515 Index: gcc/graphite-sese-to-poly.c
5516 ===================================================================
5517 --- gcc/graphite-sese-to-poly.c (.../tags/gcc_4_5_2_release) (wersja 170084)
5518 +++ gcc/graphite-sese-to-poly.c (.../branches/gcc-4_5-branch) (wersja 170084)
5520 gcc_assert (TREE_CODE (e) == INTEGER_CST);
5523 - value_set_si (val, int_cst_value (e));
5524 + tree_int_to_gmp (e, val);
5525 add_value_to_dim (l, expr, val);
5528 @@ -729,16 +729,13 @@
5531 ppl_Coefficient_t coef;
5532 - int v = int_cst_value (cst);
5533 + tree type = TREE_TYPE (cst);
5536 - value_set_si (val, 0);
5538 /* Necessary to not get "-1 = 2^n - 1". */
5540 - value_sub_int (val, val, -v);
5542 - value_add_int (val, val, v);
5543 + mpz_set_double_int (val, double_int_sext (tree_to_double_int (cst),
5544 + TYPE_PRECISION (type)), false);
5546 value_multiply (val, val, k);
5547 ppl_new_Coefficient (&coef);
5550 gcc_assert (host_integerp (TREE_OPERAND (e, 1), 0));
5552 - value_set_si (val, int_cst_value (TREE_OPERAND (e, 1)));
5553 + tree_int_to_gmp (TREE_OPERAND (e, 1), val);
5554 value_multiply (val, val, k);
5555 scan_tree_for_params (s, TREE_OPERAND (e, 0), c, val);
5559 gcc_assert (host_integerp (TREE_OPERAND (e, 0), 0));
5561 - value_set_si (val, int_cst_value (TREE_OPERAND (e, 0)));
5562 + tree_int_to_gmp (TREE_OPERAND (e, 0), val);
5563 value_multiply (val, val, k);
5564 scan_tree_for_params (s, TREE_OPERAND (e, 1), c, val);
5566 @@ -1717,10 +1714,13 @@
5567 /* subscript - low >= 0 */
5568 if (host_integerp (low, 0))
5572 ppl_new_Linear_Expression_with_dimension (&expr, accessp_nb_dims);
5573 ppl_set_coef (expr, subscript, 1);
5575 - ppl_set_inhomogeneous (expr, -int_cst_value (low));
5576 + minus_low = fold_build1 (NEGATE_EXPR, TREE_TYPE (low), low);
5577 + ppl_set_inhomogeneous_tree (expr, minus_low);
5579 ppl_new_Constraint (&cstr, expr, PPL_CONSTRAINT_TYPE_GREATER_OR_EQUAL);
5580 ppl_Polyhedron_add_constraint (accesses, cstr);
5581 @@ -1740,7 +1740,7 @@
5582 ppl_new_Linear_Expression_with_dimension (&expr, accessp_nb_dims);
5583 ppl_set_coef (expr, subscript, -1);
5585 - ppl_set_inhomogeneous (expr, int_cst_value (high));
5586 + ppl_set_inhomogeneous_tree (expr, high);
5588 ppl_new_Constraint (&cstr, expr, PPL_CONSTRAINT_TYPE_GREATER_OR_EQUAL);
5589 ppl_Polyhedron_add_constraint (accesses, cstr);
5590 Index: gcc/config.gcc
5591 ===================================================================
5592 --- gcc/config.gcc (.../tags/gcc_4_5_2_release) (wersja 170084)
5593 +++ gcc/config.gcc (.../branches/gcc-4_5-branch) (wersja 170084)
5595 # GCC target-specific configuration file.
5596 # Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
5597 -# 2008, 2009, 2010 Free Software Foundation, Inc.
5598 +# 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
5600 #This file is part of GCC.
5602 Index: gcc/tree-ssa-structalias.c
5603 ===================================================================
5604 --- gcc/tree-ssa-structalias.c (.../tags/gcc_4_5_2_release) (wersja 170084)
5605 +++ gcc/tree-ssa-structalias.c (.../branches/gcc-4_5-branch) (wersja 170084)
5606 @@ -369,7 +369,11 @@
5607 ret->may_have_pointers = true;
5608 ret->is_global_var = (t == NULL_TREE);
5609 if (t && DECL_P (t))
5610 - ret->is_global_var = is_global_var (t);
5611 + ret->is_global_var = (is_global_var (t)
5612 + /* We have to treat even local register variables
5613 + as escape points. */
5614 + || (TREE_CODE (t) == VAR_DECL
5615 + && DECL_HARD_REGISTER (t)));
5616 ret->solution = BITMAP_ALLOC (&pta_obstack);
5617 ret->oldsolution = BITMAP_ALLOC (&oldpta_obstack);
5619 @@ -4305,6 +4309,17 @@
5620 if (!VEC_empty (fieldoff_s, *fieldstack))
5621 pair = VEC_last (fieldoff_s, *fieldstack);
5624 + && offset + foff != 0)
5626 + pair = VEC_safe_push (fieldoff_s, heap, *fieldstack, NULL);
5628 + pair->size = offset + foff;
5629 + pair->has_unknown_size = false;
5630 + pair->may_have_pointers = false;
5631 + pair->only_restrict_pointers = false;
5634 if (!DECL_SIZE (field)
5635 || !host_integerp (DECL_SIZE (field), 1))
5636 has_unknown_size = true;
5637 Index: gcc/gthr-posix.h
5638 ===================================================================
5639 --- gcc/gthr-posix.h (.../tags/gcc_4_5_2_release) (wersja 170084)
5640 +++ gcc/gthr-posix.h (.../branches/gcc-4_5-branch) (wersja 170084)
5642 /* Threads compatibility routines for libgcc2 and libobjc. */
5643 /* Compile this one with gcc. */
5644 /* Copyright (C) 1997, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
5645 - 2008, 2009 Free Software Foundation, Inc.
5646 + 2008, 2009, 2011 Free Software Foundation, Inc.
5648 This file is part of GCC.
5650 @@ -250,61 +250,34 @@
5651 calls in shared flavors of the HP-UX C library. Most of the stubs
5652 have no functionality. The details are described in the "libc cumulative
5653 patch" for each subversion of HP-UX 11. There are two special interfaces
5654 - provided for checking whether an application is linked to a pthread
5655 + provided for checking whether an application is linked to a shared pthread
5656 library or not. However, these interfaces aren't available in early
5657 - libc versions. We also can't use pthread_once as some libc versions
5658 - call the init function. So, we use pthread_create to check whether it
5659 - is possible to create a thread or not. The stub implementation returns
5660 - the error number ENOSYS. */
5661 + libpthread libraries. We also need a test that works for archive
5662 + libraries. We can't use pthread_once as some libc versions call the
5663 + init function. We also can't use pthread_create or pthread_attr_init
5664 + as these create a thread and thereby prevent changing the default stack
5665 + size. The function pthread_default_stacksize_np is available in both
5666 + the archive and shared versions of libpthread. It can be used to
5667 + determine the default pthread stack size. There is a stub in some
5668 + shared libc versions which returns a zero size if pthreads are not
5669 + active. We provide an equivalent stub to handle cases where libc
5670 + doesn't provide one. */
5672 #if defined(__hppa__) && defined(__hpux__)
5676 static volatile int __gthread_active = -1;
5679 -__gthread_start (void *__arg __attribute__((unused)))
5684 -static void __gthread_active_init (void) __attribute__((noinline));
5686 -__gthread_active_init (void)
5688 - static pthread_mutex_t __gthread_active_mutex = PTHREAD_MUTEX_INITIALIZER;
5690 - pthread_attr_t __a;
5693 - __gthrw_(pthread_mutex_lock) (&__gthread_active_mutex);
5694 - if (__gthread_active < 0)
5696 - __gthrw_(pthread_attr_init) (&__a);
5697 - __gthrw_(pthread_attr_setdetachstate) (&__a, PTHREAD_CREATE_DETACHED);
5698 - __result = __gthrw_(pthread_create) (&__t, &__a, __gthread_start, NULL);
5699 - if (__result != ENOSYS)
5700 - __gthread_active = 1;
5702 - __gthread_active = 0;
5703 - __gthrw_(pthread_attr_destroy) (&__a);
5705 - __gthrw_(pthread_mutex_unlock) (&__gthread_active_mutex);
5709 __gthread_active_p (void)
5711 /* Avoid reading __gthread_active twice on the main code path. */
5712 int __gthread_active_latest_value = __gthread_active;
5715 - /* This test is not protected to avoid taking a lock on the main code
5716 - path so every update of __gthread_active in a threaded program must
5717 - be atomic with regard to the result of the test. */
5718 if (__builtin_expect (__gthread_active_latest_value < 0, 0))
5720 - __gthread_active_init ();
5721 + pthread_default_stacksize_np (0, &__s);
5722 + __gthread_active = __s ? 1 : 0;
5723 __gthread_active_latest_value = __gthread_active;
5726 Index: gcc/config/sparc/sparc.md
5727 ===================================================================
5728 --- gcc/config/sparc/sparc.md (.../tags/gcc_4_5_2_release) (wersja 170084)
5729 +++ gcc/config/sparc/sparc.md (.../branches/gcc-4_5-branch) (wersja 170084)
5730 @@ -1106,14 +1106,15 @@
5732 ;; Load in operand 0 the (absolute) address of operand 1, which is a symbolic
5733 ;; value subject to a PC-relative relocation. Operand 2 is a helper function
5734 -;; that adds the PC value at the call point to operand 0.
5735 +;; that adds the PC value at the call point to register #(operand 3).
5737 (define_insn "load_pcrel_sym<P:mode>"
5738 [(set (match_operand:P 0 "register_operand" "=r")
5739 (unspec:P [(match_operand:P 1 "symbolic_operand" "")
5740 - (match_operand:P 2 "call_address_operand" "")] UNSPEC_LOAD_PCREL_SYM))
5741 + (match_operand:P 2 "call_address_operand" "")
5742 + (match_operand:P 3 "const_int_operand" "")] UNSPEC_LOAD_PCREL_SYM))
5743 (clobber (reg:P 15))]
5745 + "REGNO (operands[0]) == INTVAL (operands[3])"
5747 if (flag_delayed_branch)
5748 return "sethi\t%%hi(%a1-4), %0\n\tcall\t%a2\n\t add\t%0, %%lo(%a1+4), %0";
5749 Index: gcc/config/sparc/sparc.c
5750 ===================================================================
5751 --- gcc/config/sparc/sparc.c (.../tags/gcc_4_5_2_release) (wersja 170084)
5752 +++ gcc/config/sparc/sparc.c (.../branches/gcc-4_5-branch) (wersja 170084)
5754 static int epilogue_renumber (rtx *, int);
5755 static bool sparc_assemble_integer (rtx, unsigned int, int);
5756 static int set_extends (rtx);
5757 -static void load_pic_register (void);
5758 +static void load_got_register (void);
5759 static int save_or_restore_regs (int, int, rtx, int, int);
5760 static void emit_save_or_restore_regs (int);
5761 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT);
5762 @@ -966,6 +966,36 @@
5766 +/* Return true if the address of LABEL can be loaded by means of the
5767 + mov{si,di}_pic_label_ref patterns in PIC mode. */
5770 +can_use_mov_pic_label_ref (rtx label)
5772 + /* VxWorks does not impose a fixed gap between segments; the run-time
5773 + gap can be different from the object-file gap. We therefore can't
5774 + assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
5775 + are absolutely sure that X is in the same segment as the GOT.
5776 + Unfortunately, the flexibility of linker scripts means that we
5777 + can't be sure of that in general, so assume that GOT-relative
5778 + accesses are never valid on VxWorks. */
5779 + if (TARGET_VXWORKS_RTP)
5782 + /* Similarly, if the label is non-local, it might end up being placed
5783 + in a different section than the current one; now mov_pic_label_ref
5784 + requires the label and the code to be in the same section. */
5785 + if (LABEL_REF_NONLOCAL_P (label))
5788 + /* Finally, if we are reordering basic blocks and partition into hot
5789 + and cold sections, this might happen for any label. */
5790 + if (flag_reorder_blocks_and_partition)
5796 /* Expand a move instruction. Return true if all work is done. */
5799 @@ -1000,14 +1030,9 @@
5800 if (pic_address_needs_scratch (operands[1]))
5801 operands[1] = legitimize_pic_address (operands[1], NULL_RTX);
5803 - /* VxWorks does not impose a fixed gap between segments; the run-time
5804 - gap can be different from the object-file gap. We therefore can't
5805 - assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
5806 - are absolutely sure that X is in the same segment as the GOT.
5807 - Unfortunately, the flexibility of linker scripts means that we
5808 - can't be sure of that in general, so assume that _G_O_T_-relative
5809 - accesses are never valid on VxWorks. */
5810 - if (GET_CODE (operands[1]) == LABEL_REF && !TARGET_VXWORKS_RTP)
5811 + /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */
5812 + if (GET_CODE (operands[1]) == LABEL_REF
5813 + && can_use_mov_pic_label_ref (operands[1]))
5817 @@ -2907,26 +2932,39 @@
5822 -static GTY(()) bool pic_helper_needed = false;
5823 -static GTY(()) rtx pic_helper_symbol;
5824 -static GTY(()) rtx global_offset_table;
5825 +/* Global Offset Table support. */
5826 +static GTY(()) rtx got_helper_rtx = NULL_RTX;
5827 +static GTY(()) rtx global_offset_table_rtx = NULL_RTX;
5829 +/* Return the SYMBOL_REF for the Global Offset Table. */
5831 +static GTY(()) rtx sparc_got_symbol = NULL_RTX;
5836 + if (!sparc_got_symbol)
5837 + sparc_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
5839 + return sparc_got_symbol;
5842 /* Ensure that we are not using patterns that are not OK with PIC. */
5852 - gcc_assert (GET_CODE (recog_data.operand[i]) != SYMBOL_REF
5853 - && (GET_CODE (recog_data.operand[i]) != CONST
5854 - || (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
5855 - && (XEXP (XEXP (recog_data.operand[i], 0), 0)
5856 - == global_offset_table)
5857 - && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
5859 + op = recog_data.operand[i];
5860 + gcc_assert (GET_CODE (op) != SYMBOL_REF
5861 + && (GET_CODE (op) != CONST
5862 + || (GET_CODE (XEXP (op, 0)) == MINUS
5863 + && XEXP (XEXP (op, 0), 0) == sparc_got ()
5864 + && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST)));
5868 @@ -3161,9 +3199,9 @@
5872 -/* Construct the SYMBOL_REF for the tls_get_offset function. */
5873 +/* Return the SYMBOL_REF for the tls_get_addr function. */
5875 -static GTY(()) rtx sparc_tls_symbol;
5876 +static GTY(()) rtx sparc_tls_symbol = NULL_RTX;
5879 sparc_tls_get_addr (void)
5880 @@ -3174,21 +3212,28 @@
5881 return sparc_tls_symbol;
5884 +/* Return the Global Offset Table to be used in TLS mode. */
5887 sparc_tls_got (void)
5890 + /* In PIC mode, this is just the PIC offset table. */
5893 crtl->uses_pic_offset_table = 1;
5894 return pic_offset_table_rtx;
5897 - if (!global_offset_table)
5898 - global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
5899 - temp = gen_reg_rtx (Pmode);
5900 - emit_move_insn (temp, global_offset_table);
5902 + /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for
5903 + the GOT symbol with the 32-bit ABI, so we reload the GOT register. */
5904 + if (TARGET_SUN_TLS && TARGET_ARCH32)
5906 + load_got_register ();
5907 + return global_offset_table_rtx;
5910 + /* In all other cases, we load a new pseudo with the GOT symbol. */
5911 + return copy_to_reg (sparc_got ());
5914 /* Return true if X contains a thread-local symbol. */
5915 @@ -3369,7 +3414,7 @@
5917 if (GET_CODE (orig) == SYMBOL_REF
5918 /* See the comment in sparc_expand_move. */
5919 - || (TARGET_VXWORKS_RTP && GET_CODE (orig) == LABEL_REF))
5920 + || (GET_CODE (orig) == LABEL_REF && !can_use_mov_pic_label_ref (orig)))
5922 rtx pic_ref, address;
5924 @@ -3420,11 +3465,13 @@
5928 - pic_ref = gen_const_mem (Pmode,
5929 - gen_rtx_PLUS (Pmode,
5930 - pic_offset_table_rtx, address));
5932 + = gen_const_mem (Pmode,
5933 + gen_rtx_PLUS (Pmode,
5934 + pic_offset_table_rtx, address));
5935 insn = emit_move_insn (reg, pic_ref);
5938 /* Put a REG_EQUAL note on this insn, so that it can be optimized
5940 set_unique_reg_note (insn, REG_EQUAL, orig);
5941 @@ -3462,9 +3509,8 @@
5942 return gen_rtx_PLUS (Pmode, base, offset);
5944 else if (GET_CODE (orig) == LABEL_REF)
5945 - /* ??? Why do we do this? */
5946 - /* Now movsi_pic_label_ref uses it, but we ought to be checking that
5947 - the register is live instead, in case it is eliminated. */
5948 + /* ??? We ought to be checking that the register is live instead, in case
5949 + it is eliminated. */
5950 crtl->uses_pic_offset_table = 1;
5953 @@ -3529,59 +3575,69 @@
5955 get_pc_thunk_name (char name[32], unsigned int regno)
5957 - const char *pic_name = reg_names[regno];
5958 + const char *reg_name = reg_names[regno];
5960 /* Skip the leading '%' as that cannot be used in a
5965 if (USE_HIDDEN_LINKONCE)
5966 - sprintf (name, "__sparc_get_pc_thunk.%s", pic_name);
5967 + sprintf (name, "__sparc_get_pc_thunk.%s", reg_name);
5969 ASM_GENERATE_INTERNAL_LABEL (name, "LADDPC", regno);
5972 -/* Emit code to load the PIC register. */
5973 +/* Wrapper around the load_pcrel_sym{si,di} patterns. */
5976 -load_pic_register (void)
5978 +gen_load_pcrel_sym (rtx op0, rtx op1, rtx op2, rtx op3)
5980 int orig_flag_pic = flag_pic;
5983 - if (TARGET_VXWORKS_RTP)
5985 - emit_insn (gen_vxworks_load_got ());
5986 - emit_use (pic_offset_table_rtx);
5989 + /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
5991 + if (TARGET_ARCH64)
5992 + insn = gen_load_pcrel_symdi (op0, op1, op2, op3);
5994 + insn = gen_load_pcrel_symsi (op0, op1, op2, op3);
5995 + flag_pic = orig_flag_pic;
5997 - /* If we haven't initialized the special PIC symbols, do so now. */
5998 - if (!pic_helper_needed)
6004 - pic_helper_needed = true;
6005 +/* Emit code to load the GOT register. */
6007 - get_pc_thunk_name (name, REGNO (pic_offset_table_rtx));
6008 - pic_helper_symbol = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
6010 +load_got_register (void)
6012 + /* In PIC mode, this will retrieve pic_offset_table_rtx. */
6013 + if (!global_offset_table_rtx)
6014 + global_offset_table_rtx = gen_rtx_REG (Pmode, GLOBAL_OFFSET_TABLE_REGNUM);
6016 - global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
6017 + if (TARGET_VXWORKS_RTP)
6018 + emit_insn (gen_vxworks_load_got ());
6021 + /* The GOT symbol is subject to a PC-relative relocation so we need a
6022 + helper function to add the PC value and thus get the final value. */
6023 + if (!got_helper_rtx)
6026 + get_pc_thunk_name (name, GLOBAL_OFFSET_TABLE_REGNUM);
6027 + got_helper_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
6030 + emit_insn (gen_load_pcrel_sym (global_offset_table_rtx, sparc_got (),
6032 + GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM)));
6036 - if (TARGET_ARCH64)
6037 - emit_insn (gen_load_pcrel_symdi (pic_offset_table_rtx, global_offset_table,
6038 - pic_helper_symbol));
6040 - emit_insn (gen_load_pcrel_symsi (pic_offset_table_rtx, global_offset_table,
6041 - pic_helper_symbol));
6042 - flag_pic = orig_flag_pic;
6044 /* Need to emit this whether or not we obey regdecls,
6045 since setjmp/longjmp can cause life info to screw up.
6046 ??? In the case where we don't obey regdecls, this is not sufficient
6047 since we may not fall out the bottom. */
6048 - emit_use (pic_offset_table_rtx);
6049 + emit_use (global_offset_table_rtx);
6052 /* Emit a call instruction with the pattern given by PAT. ADDR is the
6053 @@ -4113,7 +4169,7 @@
6055 /* Expand the function prologue. The prologue is responsible for reserving
6056 storage for the frame, saving the call-saved registers and loading the
6057 - PIC register if needed. */
6058 + GOT register if needed. */
6061 sparc_expand_prologue (void)
6062 @@ -4215,9 +4271,9 @@
6064 emit_save_or_restore_regs (SORR_SAVE);
6066 - /* Load the PIC register if needed. */
6067 - if (flag_pic && crtl->uses_pic_offset_table)
6068 - load_pic_register ();
6069 + /* Load the GOT register if needed. */
6070 + if (crtl->uses_pic_offset_table)
6071 + load_got_register ();
6074 /* This function generates the assembly code for function entry, which boils
6075 @@ -8705,7 +8761,7 @@
6076 /* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
6077 This is achieved by means of a manual dynamic stack space allocation in
6078 the current frame. We make the assumption that SEQ doesn't contain any
6079 - function calls, with the possible exception of calls to the PIC helper. */
6080 + function calls, with the possible exception of calls to the GOT helper. */
6083 emit_and_preserve (rtx seq, rtx reg, rtx reg2)
6084 @@ -8868,20 +8924,19 @@
6086 /* The hoops we have to jump through in order to generate a sibcall
6087 without using delay slots... */
6088 - rtx spill_reg, spill_reg2, seq, scratch = gen_rtx_REG (Pmode, 1);
6089 + rtx spill_reg, seq, scratch = gen_rtx_REG (Pmode, 1);
6093 spill_reg = gen_rtx_REG (word_mode, 15); /* %o7 */
6094 - spill_reg2 = gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM);
6096 - /* Delay emitting the PIC helper function because it needs to
6097 + /* Delay emitting the GOT helper function because it needs to
6098 change the section and we are emitting assembly code. */
6099 - load_pic_register (); /* clobbers %o7 */
6100 + load_got_register (); /* clobbers %o7 */
6101 scratch = legitimize_pic_address (funexp, scratch);
6104 - emit_and_preserve (seq, spill_reg, spill_reg2);
6105 + emit_and_preserve (seq, spill_reg, pic_offset_table_rtx);
6107 else if (TARGET_ARCH32)
6109 @@ -9032,17 +9087,15 @@
6111 sparc_file_end (void)
6113 - /* If need to emit the special PIC helper function, do so now. */
6114 - if (pic_helper_needed)
6115 + /* If we need to emit the special GOT helper function, do so now. */
6116 + if (got_helper_rtx)
6118 - unsigned int regno = REGNO (pic_offset_table_rtx);
6119 - const char *pic_name = reg_names[regno];
6121 + const char *name = XSTR (got_helper_rtx, 0);
6122 + const char *reg_name = reg_names[GLOBAL_OFFSET_TABLE_REGNUM];
6123 #ifdef DWARF2_UNWIND_INFO
6127 - get_pc_thunk_name (name, regno);
6128 if (USE_HIDDEN_LINKONCE)
6130 tree decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
6131 @@ -9055,7 +9108,9 @@
6132 make_decl_one_only (decl, DECL_ASSEMBLER_NAME (decl));
6133 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN;
6134 DECL_VISIBILITY_SPECIFIED (decl) = 1;
6135 + resolve_unique_section (decl, 0, flag_function_sections);
6136 allocate_struct_function (decl, true);
6137 + cfun->is_thunk = 1;
6138 current_function_decl = decl;
6139 init_varasm_status ();
6140 assemble_start_function (decl, name);
6141 @@ -9076,10 +9131,10 @@
6143 if (flag_delayed_branch)
6144 fprintf (asm_out_file, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
6145 - pic_name, pic_name);
6146 + reg_name, reg_name);
6148 fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
6149 - pic_name, pic_name);
6150 + reg_name, reg_name);
6151 #ifdef DWARF2_UNWIND_INFO
6153 fprintf (asm_out_file, "\t.cfi_endproc\n");
6154 Index: gcc/config/sparc/sparc.h
6155 ===================================================================
6156 --- gcc/config/sparc/sparc.h (.../tags/gcc_4_5_2_release) (wersja 170084)
6157 +++ gcc/config/sparc/sparc.h (.../branches/gcc-4_5-branch) (wersja 170084)
6158 @@ -964,10 +964,15 @@
6159 not be a register used by the prologue. */
6160 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
6162 +/* Register which holds the global offset table, if any. */
6164 +#define GLOBAL_OFFSET_TABLE_REGNUM 23
6166 /* Register which holds offset table for position-independent
6169 -#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 23 : INVALID_REGNUM)
6170 +#define PIC_OFFSET_TABLE_REGNUM \
6171 + (flag_pic ? GLOBAL_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
6173 /* Pick a default value we can notice from override_options:
6175 Index: gcc/config/rx/rx.h
6176 ===================================================================
6177 --- gcc/config/rx/rx.h (.../tags/gcc_4_5_2_release) (wersja 170084)
6178 +++ gcc/config/rx/rx.h (.../branches/gcc-4_5-branch) (wersja 170084)
6180 /* GCC backend definitions for the Renesas RX processor.
6181 - Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.
6182 + Copyright (C) 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
6183 Contributed by Red Hat.
6185 This file is part of GCC.
6187 builtin_define ("__RX__"); \
6188 builtin_assert ("cpu=RX"); \
6189 if (rx_cpu_type == RX610) \
6190 - builtin_assert ("machine=RX610"); \
6192 + builtin_define ("__RX610__"); \
6193 + builtin_assert ("machine=RX610"); \
6196 builtin_assert ("machine=RX600"); \
6198 @@ -144,6 +147,10 @@
6199 #define SIZE_TYPE "long unsigned int"
6201 #define PTRDIFF_TYPE "long int"
6203 +#define WCHAR_TYPE "long int"
6204 +#undef WCHAR_TYPE_SIZE
6205 +#define WCHAR_TYPE_SIZE BITS_PER_WORD
6206 #define POINTERS_EXTEND_UNSIGNED 1
6207 #define FUNCTION_MODE QImode
6208 #define CASE_VECTOR_MODE Pmode
6211 #define LIBCALL_VALUE(MODE) \
6212 gen_rtx_REG (((GET_MODE_CLASS (MODE) != MODE_INT \
6213 + || COMPLEX_MODE_P (MODE) \
6214 || GET_MODE_SIZE (MODE) >= 4) \
6219 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
6220 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", "cc" \
6224 #define ADDITIONAL_REGISTER_NAMES \
6227 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
6228 rx_print_operand_address (FILE, ADDR)
6230 -extern int rx_float_compare_mode;
6232 /* This is a version of REG_P that also returns TRUE for SUBREGs. */
6233 #define RX_REG_P(rtl) (REG_P (rtl) || GET_CODE (rtl) == SUBREG)
6235 @@ -655,12 +661,5 @@
6236 #define REGISTER_MOVE_COST(MODE, FROM, TO) 2
6237 #define MEMORY_MOVE_COST(MODE, REGCLASS, IN) (2 + memory_move_secondary_cost (MODE, REGCLASS, IN))
6239 -#define SELECT_CC_MODE(OP,X,Y) \
6240 - (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CC_ZSmode : \
6241 - (GET_CODE (X) == PLUS || GET_CODE (X) == MINUS ? CC_ZSCmode : \
6242 - (GET_CODE (X) == ABS ? CC_ZSOmode : \
6243 - (GET_CODE (X) == AND || GET_CODE (X) == NOT || GET_CODE (X) == IOR \
6244 - || GET_CODE (X) == XOR || GET_CODE (X) == ROTATE \
6245 - || GET_CODE (X) == ROTATERT || GET_CODE (X) == ASHIFTRT \
6246 - || GET_CODE (X) == LSHIFTRT || GET_CODE (X) == ASHIFT ? CC_ZSmode : \
6248 +#define SELECT_CC_MODE(OP,X,Y) rx_select_cc_mode ((OP), (X), (Y))
6250 Index: gcc/config/rx/predicates.md
6251 ===================================================================
6252 --- gcc/config/rx/predicates.md (.../tags/gcc_4_5_2_release) (wersja 170084)
6253 +++ gcc/config/rx/predicates.md (.../branches/gcc-4_5-branch) (wersja 170084)
6255 ;; Predicate definitions for Renesas RX.
6256 -;; Copyright (C) 2008, 2009 Free Software Foundation, Inc.
6257 +;; Copyright (C) 2008, 2009, 2011 Free Software Foundation, Inc.
6258 ;; Contributed by Red Hat.
6260 ;; This file is part of GCC.
6262 ;; Only small integers or a value in a register are permitted.
6264 (define_predicate "rx_shift_operand"
6265 - (match_code "const_int,reg")
6267 - if (CONST_INT_P (op))
6268 - return IN_RANGE (INTVAL (op), 0, 31);
6271 + (ior (match_operand 0 "register_operand")
6272 + (and (match_code "const_int")
6273 + (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
6276 (define_predicate "rx_constshift_operand"
6277 - (match_code "const_int")
6279 - return IN_RANGE (INTVAL (op), 0, 31);
6281 + (and (match_code "const_int")
6282 + (match_test "IN_RANGE (INTVAL (op), 0, 31)"))
6285 +(define_predicate "rx_restricted_mem_operand"
6286 + (and (match_code "mem")
6287 + (match_test "rx_is_restricted_memory_address (XEXP (op, 0), mode)"))
6290 ;; Check that the operand is suitable as the source operand
6291 ;; for a logic or arithmeitc instruction. Registers, integers
6292 ;; and a restricted subset of memory addresses are allowed.
6294 (define_predicate "rx_source_operand"
6295 - (match_code "const_int,const_double,const,symbol_ref,label_ref,reg,mem")
6297 - if (CONSTANT_P (op))
6298 - return rx_is_legitimate_constant (op);
6303 - /* Do not allow size conversions whilst accessing memory. */
6304 - if (GET_MODE (op) != mode)
6307 - return rx_is_restricted_memory_address (XEXP (op, 0), mode);
6309 + (ior (match_operand 0 "register_operand")
6310 + (match_operand 0 "immediate_operand")
6311 + (match_operand 0 "rx_restricted_mem_operand"))
6314 ;; Check that the operand is suitable as the source operand
6316 ;; CONST_INTs are not.
6318 (define_predicate "rx_compare_operand"
6319 - (match_code "subreg,reg,mem")
6321 - if (GET_CODE (op) == SUBREG)
6322 - return REG_P (XEXP (op, 0));
6327 - return rx_is_restricted_memory_address (XEXP (op, 0), mode);
6329 + (ior (match_operand 0 "register_operand")
6330 + (match_operand 0 "rx_restricted_mem_operand"))
6333 ;; Return true if OP is a store multiple operation. This looks like:
6334 @@ -293,3 +274,24 @@
6335 element = XVECEXP (op, 0, count - 1);
6336 return GET_CODE (element) == RETURN;
6339 +(define_predicate "label_ref_operand"
6340 + (match_code "label_ref")
6343 +(define_predicate "rx_z_comparison_operator"
6344 + (match_code "eq,ne")
6347 +(define_predicate "rx_zs_comparison_operator"
6348 + (match_code "eq,ne")
6351 +;; GT and LE omitted due to operand swap required.
6352 +(define_predicate "rx_fp_comparison_operator"
6353 + (match_code "eq,ne,lt,ge,ordered,unordered")
6356 +(define_predicate "rshift_operator"
6357 + (match_code "ashiftrt,lshiftrt")
6359 Index: gcc/config/rx/rx-protos.h
6360 ===================================================================
6361 --- gcc/config/rx/rx-protos.h (.../tags/gcc_4_5_2_release) (wersja 170084)
6362 +++ gcc/config/rx/rx-protos.h (.../branches/gcc-4_5-branch) (wersja 170084)
6364 /* Exported function prototypes from the Renesas RX backend.
6365 - Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.
6366 + Copyright (C) 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
6367 Contributed by Red Hat.
6369 This file is part of GCC.
6371 extern void rx_emit_stack_popm (rtx *, bool);
6372 extern void rx_emit_stack_pushm (rtx *);
6373 extern void rx_expand_epilogue (bool);
6374 -extern bool rx_expand_insv (rtx *);
6375 extern const char * rx_gen_cond_branch_template (rtx, bool);
6376 extern char * rx_gen_move_template (rtx *, bool);
6377 extern bool rx_is_legitimate_constant (rtx);
6378 extern bool rx_is_mode_dependent_addr (rtx);
6379 extern bool rx_is_restricted_memory_address (rtx, Mmode);
6380 +extern bool rx_match_ccmode (rtx, Mmode);
6381 extern void rx_notice_update_cc (rtx body, rtx insn);
6382 extern void rx_print_operand (FILE *, rtx, int);
6383 extern void rx_print_operand_address (FILE *, rtx);
6384 +extern Mmode rx_select_cc_mode (enum rtx_code, rtx, rtx);
6385 +extern void rx_split_cbranch (Mmode, enum rtx_code, rtx, rtx, rtx);
6389 Index: gcc/config/rx/rx.md
6390 ===================================================================
6391 --- gcc/config/rx/rx.md (.../tags/gcc_4_5_2_release) (wersja 170084)
6392 +++ gcc/config/rx/rx.md (.../branches/gcc-4_5-branch) (wersja 170084)
6394 ;; Machine Description for Renesas RX processors
6395 -;; Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.
6396 +;; Copyright (C) 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
6397 ;; Contributed by Red Hat.
6399 ;; This file is part of GCC.
6401 ;; <http://www.gnu.org/licenses/>.
6404 -;; This code iterator allows all branch instructions to
6405 -;; be generated from a single define_expand template.
6406 -(define_code_iterator most_cond [eq ne gt ge lt le gtu geu ltu leu
6407 - unordered ordered ])
6409 -;; Likewise, but only the ones that use Z or S.
6410 -(define_code_iterator zs_cond [eq ne gtu geu ltu leu ])
6412 ;; This code iterator is used for sign- and zero- extensions.
6413 (define_mode_iterator small_int_modes [(HI "") (QI "")])
6416 [(SF "ALLOW_RX_FPU_INSNS") (SI "") (HI "") (QI "")])
6419 -;; Used to map RX condition names to GCC
6420 -;; condition names for builtin instructions.
6421 -(define_code_iterator gcc_conds [eq ne gt ge lt le gtu geu ltu leu
6422 - unge unlt uneq ltgt])
6423 -(define_code_attr rx_conds [(eq "eq") (ne "ne") (gt "gt") (ge "ge") (lt "lt")
6424 - (le "le") (gtu "gtu") (geu "geu") (ltu "ltu")
6425 - (leu "leu") (unge "pz") (unlt "n") (uneq "o")
6440 (define_insn_reservation "throughput_18_latency_18" 1
6441 (eq_attr "timings" "1818") "throughput*18")
6443 +;; ----------------------------------------------------------------------------
6447 ;; Note - we do not specify the two instructions necessary to perform
6448 @@ -160,254 +146,164 @@
6450 (define_expand "cbranchsi4"
6452 - (if_then_else (match_operator 0 "comparison_operator"
6453 - [(match_operand:SI 1 "register_operand")
6454 - (match_operand:SI 2 "rx_source_operand")])
6455 - (label_ref (match_operand 3 ""))
6459 + (match_operator 0 "comparison_operator"
6460 + [(match_operand:SI 1 "register_operand")
6461 + (match_operand:SI 2 "rx_source_operand")])
6462 + (label_ref (match_operand 3 ""))
6468 -(define_insn_and_split "*cbranchsi4_<code>"
6469 +(define_insn_and_split "*cbranchsi4"
6471 - (if_then_else (most_cond (match_operand:SI 0 "register_operand" "r")
6472 - (match_operand:SI 1 "rx_source_operand" "riQ"))
6473 - (label_ref (match_operand 2 "" ""))
6477 + (match_operator 3 "comparison_operator"
6478 + [(match_operand:SI 0 "register_operand" "r")
6479 + (match_operand:SI 1 "rx_source_operand" "riQ")])
6480 + (match_operand 2 "label_ref_operand" "")
6487 - /* We contstruct the split by hand as otherwise the JUMP_LABEL
6488 - attribute is not set correctly on the jump insn. */
6489 - emit_insn (gen_cmpsi (operands[0], operands[1]));
6491 - emit_jump_insn (gen_conditional_branch (operands[2],
6492 - gen_rtx_fmt_ee (<most_cond:CODE>, CCmode,
6493 - gen_rtx_REG (CCmode, CC_REG), const0_rtx)));
6496 + rx_split_cbranch (CCmode, GET_CODE (operands[3]),
6497 + operands[0], operands[1], operands[2]);
6501 +(define_insn "*cmpsi"
6502 + [(set (reg:CC CC_REG)
6503 + (compare:CC (match_operand:SI 0 "register_operand" "r,r,r,r,r,r,r")
6504 + (match_operand:SI 1 "rx_source_operand" "r,Uint04,Int08,Sint16,Sint24,i,Q")))]
6505 + "reload_completed"
6507 + [(set_attr "timings" "11,11,11,11,11,11,33")
6508 + (set_attr "length" "2,2,3,4,5,6,5")]
6511 -;; -----------------------------------------------------------------------------
6512 -;; These two are the canonical TST/branch insns. However, GCC
6513 -;; generates a wide variety of tst-like patterns, we catch those
6515 -(define_insn_and_split "*tstbranchsi4_<code>"
6516 +;; Canonical method for representing TST.
6517 +(define_insn_and_split "*cbranchsi4_tst"
6519 - (if_then_else (zs_cond (and:SI (match_operand:SI 0 "register_operand" "r")
6520 - (match_operand:SI 1 "rx_source_operand" "riQ"))
6522 - (label_ref (match_operand 2 "" ""))
6526 + (match_operator 3 "rx_zs_comparison_operator"
6527 + [(and:SI (match_operand:SI 0 "register_operand" "r")
6528 + (match_operand:SI 1 "rx_source_operand" "riQ"))
6530 + (match_operand 2 "label_ref_operand" "")
6537 - emit_insn (gen_tstsi (operands[0], operands[1]));
6539 - emit_jump_insn (gen_conditional_branch (operands[2],
6540 - gen_rtx_fmt_ee (<zs_cond:CODE>, CCmode,
6541 - gen_rtx_REG (CCmode, CC_REG), const0_rtx)));
6545 + rx_split_cbranch (CC_ZSmode, GET_CODE (operands[3]),
6546 + XEXP (operands[3], 0), XEXP (operands[3], 1),
6551 -;; Inverse of above
6552 -(define_insn_and_split "*tstbranchsi4_<code>"
6553 +;; Various other ways that GCC codes "var & const"
6554 +(define_insn_and_split "*cbranchsi4_tst_ext"
6556 - (if_then_else (zs_cond (and:SI (match_operand:SI 0 "register_operand" "r")
6557 - (match_operand:SI 1 "rx_source_operand" "riQ"))
6560 - (label_ref (match_operand 2 "" ""))))
6563 + (match_operator 4 "rx_z_comparison_operator"
6565 + (match_operand:SI 0 "register_operand" "r")
6566 + (match_operand:SI 1 "rx_constshift_operand" "")
6567 + (match_operand:SI 2 "rx_constshift_operand" ""))
6569 + (match_operand 3 "label_ref_operand" "")
6576 - emit_insn (gen_tstsi (operands[0], operands[1]));
6578 - emit_jump_insn (gen_conditional_branch (operands[2],
6579 - gen_rtx_fmt_ee (reverse_condition (<zs_cond:CODE>), CCmode,
6580 - gen_rtx_REG (CCmode, CC_REG), const0_rtx)));
6584 + HOST_WIDE_INT mask;
6587 -;; Various other ways that GCC codes "var & const"
6589 + mask <<= INTVAL (operands[1]);
6591 + mask <<= INTVAL (operands[2]);
6592 + x = gen_rtx_AND (SImode, operands[0], gen_int_mode (mask, SImode));
6594 -(define_insn_and_split "*tstbranchsi4m_eq"
6596 - (if_then_else (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
6597 - (match_operand 1 "rx_constshift_operand" "i")
6598 - (match_operand 2 "rx_constshift_operand" "i"))
6600 - (label_ref (match_operand 3 "" ""))
6607 - (if_then_else (eq (and:SI (match_dup 0)
6610 - (label_ref (match_dup 3))
6613 - "operands[4] = GEN_INT (((1 << INTVAL (operands[1]))-1) << INTVAL (operands[2]));"
6615 + rx_split_cbranch (CC_ZSmode, GET_CODE (operands[4]),
6616 + x, const0_rtx, operands[3]);
6620 -(define_insn_and_split "*tstbranchsi4m_ne"
6622 - (if_then_else (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
6623 - (match_operand 1 "rx_constshift_operand" "i")
6624 - (match_operand 2 "rx_constshift_operand" "i"))
6626 - (label_ref (match_operand 3 "" ""))
6633 - (if_then_else (ne (and:SI (match_dup 0)
6636 - (label_ref (match_dup 3))
6639 - "operands[4] = GEN_INT (((1 << INTVAL (operands[1]))-1) << INTVAL (operands[2]));"
6640 +(define_insn "*tstsi"
6641 + [(set (reg:CC_ZS CC_REG)
6643 + (and:SI (match_operand:SI 0 "register_operand" "r,r,r")
6644 + (match_operand:SI 1 "rx_source_operand" "r,i,Q"))
6646 + "reload_completed"
6648 + [(set_attr "timings" "11,11,33")
6649 + (set_attr "length" "3,7,6")]
6652 -;; -----------------------------------------------------------------------------
6654 (define_expand "cbranchsf4"
6656 - (if_then_else (match_operator 0 "comparison_operator"
6657 - [(match_operand:SF 1 "register_operand")
6658 - (match_operand:SF 2 "rx_source_operand")])
6659 - (label_ref (match_operand 3 ""))
6663 + (match_operator 0 "rx_fp_comparison_operator"
6664 + [(match_operand:SF 1 "register_operand")
6665 + (match_operand:SF 2 "rx_source_operand")])
6666 + (label_ref (match_operand 3 ""))
6668 "ALLOW_RX_FPU_INSNS"
6672 -(define_insn_and_split "*cbranchsf4_<code>"
6673 +(define_insn_and_split "*cbranchsf4"
6675 - (if_then_else (most_cond (match_operand:SF 0 "register_operand" "r")
6676 - (match_operand:SF 1 "rx_source_operand" "rFiQ"))
6677 - (label_ref (match_operand 2 "" ""))
6681 + (match_operator 3 "rx_fp_comparison_operator"
6682 + [(match_operand:SF 0 "register_operand" "r")
6683 + (match_operand:SF 1 "rx_source_operand" "rFQ")])
6684 + (match_operand 2 "label_ref_operand" "")
6686 "ALLOW_RX_FPU_INSNS"
6688 "&& reload_completed"
6691 - /* We contstruct the split by hand as otherwise the JUMP_LABEL
6692 - attribute is not set correctly on the jump insn. */
6693 - emit_insn (gen_cmpsf (operands[0], operands[1]));
6695 - emit_jump_insn (gen_conditional_branch (operands[2],
6696 - gen_rtx_fmt_ee (<most_cond:CODE>, CCmode,
6697 - gen_rtx_REG (CCmode, CC_REG), const0_rtx)));
6701 + rx_split_cbranch (CC_Fmode, GET_CODE (operands[3]),
6702 + operands[0], operands[1], operands[2]);
6706 -(define_insn "tstsi"
6707 - [(set (reg:CC_ZS CC_REG)
6708 - (compare:CC_ZS (and:SI (match_operand:SI 0 "register_operand" "r,r,r")
6709 - (match_operand:SI 1 "rx_source_operand" "r,i,Q"))
6713 - rx_float_compare_mode = false;
6714 - return "tst\t%Q1, %0";
6716 +(define_insn "*cmpsf"
6717 + [(set (reg:CC_F CC_REG)
6719 + (match_operand:SF 0 "register_operand" "r,r,r")
6720 + (match_operand:SF 1 "rx_source_operand" "r,F,Q")))]
6721 + "ALLOW_RX_FPU_INSNS && reload_completed"
6723 [(set_attr "timings" "11,11,33")
6724 - (set_attr "length" "3,7,6")]
6727 -(define_insn "cmpsi"
6728 - [(set (reg:CC CC_REG)
6729 - (compare:CC (match_operand:SI 0 "register_operand" "r,r,r,r,r,r,r")
6730 - (match_operand:SI 1 "rx_source_operand" "r,Uint04,Int08,Sint16,Sint24,i,Q")))]
6733 - rx_float_compare_mode = false;
6734 - if (rx_compare_redundant (insn))
6735 - return "; Compare Eliminated: cmp %Q1, %0";
6736 - return "cmp\t%Q1, %0";
6738 - [(set_attr "timings" "11,11,11,11,11,11,33")
6739 - (set_attr "length" "2,2,3,4,5,6,5")]
6742 -;; This pattern is disabled when -fnon-call-exceptions is active because
6743 -;; it could generate a floating point exception, which would introduce an
6744 -;; edge into the flow graph between this insn and the conditional branch
6745 -;; insn to follow, thus breaking the cc0 relationship. Run the g++ test
6746 -;; g++.dg/eh/080514-1.C to see this happen.
6747 -(define_insn "cmpsf"
6748 - [(set (reg:CC_ZSO CC_REG)
6749 - (compare:CC_ZSO (match_operand:SF 0 "register_operand" "r,r,r")
6750 - (match_operand:SF 1 "rx_source_operand" "r,iF,Q")))]
6751 - "ALLOW_RX_FPU_INSNS"
6753 - rx_float_compare_mode = true;
6754 - return "fcmp\t%1, %0";
6756 - [(set_attr "timings" "11,11,33")
6757 (set_attr "length" "3,7,5")]
6760 ;; Flow Control Instructions:
6762 -(define_expand "b<code>"
6763 +(define_insn "*conditional_branch"
6765 - (if_then_else (most_cond (reg:CC CC_REG) (const_int 0))
6766 - (label_ref (match_operand 0))
6772 -(define_insn "conditional_branch"
6774 - (if_then_else (match_operator 1 "comparison_operator"
6775 - [(reg:CC CC_REG) (const_int 0)])
6776 - (label_ref (match_operand 0 "" ""))
6780 - return rx_gen_cond_branch_template (operands[1], false);
6783 + (match_operator 1 "comparison_operator"
6784 + [(reg CC_REG) (const_int 0)])
6785 + (label_ref (match_operand 0 "" ""))
6787 + "reload_completed"
6789 [(set_attr "length" "8") ;; This length is wrong, but it is
6790 ;; too hard to compute statically.
6791 (set_attr "timings" "33")] ;; The timing assumes that the branch is taken.
6794 -(define_insn "*reveresed_conditional_branch"
6796 - (if_then_else (match_operator 1 "comparison_operator"
6797 - [(reg:CC CC_REG) (const_int 0)])
6799 - (label_ref (match_operand 0 "" ""))))]
6802 - return rx_gen_cond_branch_template (operands[1], true);
6804 - [(set_attr "length" "8") ;; This length is wrong, but it is
6805 - ;; too hard to compute statically.
6806 - (set_attr "timings" "33")] ;; The timing assumes that the branch is taken.
6808 +;; ----------------------------------------------------------------------------
6812 @@ -448,10 +344,12 @@
6813 (set_attr "timings" "55")]
6816 +;; Unspec used so that the constant will not be invalid
6817 +;; if -mmax-constant-size has been specified.
6818 (define_insn "deallocate_and_return"
6819 [(set (reg:SI SP_REG)
6820 (plus:SI (reg:SI SP_REG)
6821 - (match_operand:SI 0 "immediate_operand" "i")))
6822 + (const:SI (unspec:SI [(match_operand 0 "const_int_operand" "n")] UNSPEC_CONST))))
6826 @@ -461,9 +359,10 @@
6828 (define_insn "pop_and_return"
6829 [(match_parallel 1 "rx_rtsd_vector"
6830 - [(set:SI (reg:SI SP_REG)
6831 - (plus:SI (reg:SI SP_REG)
6832 - (match_operand:SI 0 "const_int_operand" "n")))])]
6833 + [(set (reg:SI SP_REG)
6834 + (plus:SI (reg:SI SP_REG)
6835 + (match_operand:SI 0 "const_int_operand" "n")))])
6839 rx_emit_stack_popm (operands, false);
6840 @@ -513,14 +412,14 @@
6842 if (! rx_call_operand (dest, Pmode))
6843 dest = force_reg (Pmode, dest);
6844 - emit_call_insn (gen_call_internal (dest, operands[1]));
6845 + emit_call_insn (gen_call_internal (dest));
6850 (define_insn "call_internal"
6851 [(call (mem:QI (match_operand:SI 0 "rx_call_operand" "r,Symbol"))
6852 - (match_operand:SI 1 "general_operand" "g,g"))
6854 (clobber (reg:CC CC_REG))]
6859 if (! rx_call_operand (dest, Pmode))
6860 dest = force_reg (Pmode, dest);
6861 - emit_call_insn (gen_call_value_internal (operands[0], dest, operands[2]));
6862 + emit_call_insn (gen_call_value_internal (operands[0], dest));
6867 (define_insn "call_value_internal"
6868 [(set (match_operand 0 "register_operand" "=r,r")
6869 (call (mem:QI (match_operand:SI 1 "rx_call_operand" "r,Symbol"))
6870 - (match_operand:SI 2 "general_operand" "g,g")))
6872 (clobber (reg:CC CC_REG))]
6875 @@ -572,12 +471,14 @@
6877 if (MEM_P (operands[0]))
6878 operands[0] = XEXP (operands[0], 0);
6879 + emit_call_insn (gen_sibcall_internal (operands[0]));
6884 (define_insn "sibcall_internal"
6885 [(call (mem:QI (match_operand:SI 0 "rx_symbolic_call_operand" "Symbol"))
6886 - (match_operand:SI 1 "general_operand" "g"))
6891 @@ -595,13 +496,15 @@
6893 if (MEM_P (operands[1]))
6894 operands[1] = XEXP (operands[1], 0);
6895 + emit_call_insn (gen_sibcall_value_internal (operands[0], operands[1]));
6900 (define_insn "sibcall_value_internal"
6901 [(set (match_operand 0 "register_operand" "=r")
6902 (call (mem:QI (match_operand:SI 1 "rx_symbolic_call_operand" "Symbol"))
6903 - (match_operand:SI 2 "general_operand" "g")))
6910 if (MEM_P (operand0) && MEM_P (operand1))
6911 operands[1] = copy_to_mode_reg (<register_modes:MODE>mode, operand1);
6912 + if (CONST_INT_P (operand1)
6913 + && ! rx_is_legitimate_constant (operand1))
6918 @@ -688,11 +594,11 @@
6921 (define_insn "stack_push"
6922 - [(set:SI (reg:SI SP_REG)
6923 - (minus:SI (reg:SI SP_REG)
6925 - (set:SI (mem:SI (reg:SI SP_REG))
6926 - (match_operand:SI 0 "register_operand" "r"))]
6927 + [(set (reg:SI SP_REG)
6928 + (minus:SI (reg:SI SP_REG)
6930 + (set (mem:SI (reg:SI SP_REG))
6931 + (match_operand:SI 0 "register_operand" "r"))]
6934 [(set_attr "length" "2")]
6937 (define_insn "stack_pushm"
6938 [(match_parallel 1 "rx_store_multiple_vector"
6939 - [(set:SI (reg:SI SP_REG)
6940 - (minus:SI (reg:SI SP_REG)
6941 - (match_operand:SI 0 "const_int_operand" "n")))])]
6942 + [(set (reg:SI SP_REG)
6943 + (minus:SI (reg:SI SP_REG)
6944 + (match_operand:SI 0 "const_int_operand" "n")))])]
6947 rx_emit_stack_pushm (operands);
6948 @@ -713,11 +619,11 @@
6951 (define_insn "stack_pop"
6952 - [(set:SI (match_operand:SI 0 "register_operand" "=r")
6953 - (mem:SI (reg:SI SP_REG)))
6954 - (set:SI (reg:SI SP_REG)
6955 - (plus:SI (reg:SI SP_REG)
6957 + [(set (match_operand:SI 0 "register_operand" "=r")
6958 + (mem:SI (reg:SI SP_REG)))
6959 + (set (reg:SI SP_REG)
6960 + (plus:SI (reg:SI SP_REG)
6964 [(set_attr "length" "2")
6967 (define_insn "stack_popm"
6968 [(match_parallel 1 "rx_load_multiple_vector"
6969 - [(set:SI (reg:SI SP_REG)
6970 - (plus:SI (reg:SI SP_REG)
6971 - (match_operand:SI 0 "const_int_operand" "n")))])]
6972 + [(set (reg:SI SP_REG)
6973 + (plus:SI (reg:SI SP_REG)
6974 + (match_operand:SI 0 "const_int_operand" "n")))])]
6977 rx_emit_stack_popm (operands, true);
6978 @@ -738,68 +644,139 @@
6979 (set_attr "timings" "45")] ;; The timing is a guesstimate average timing.
6982 -;; FIXME: Add memory destination options ?
6983 -(define_insn "cstoresi4"
6984 - [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
6985 +(define_insn_and_split "cstoresi4"
6986 + [(set (match_operand:SI 0 "register_operand" "=r")
6987 (match_operator:SI 1 "comparison_operator"
6988 - [(match_operand:SI 2 "register_operand" "r,r,r,r,r,r,r")
6989 - (match_operand:SI 3 "rx_source_operand" "r,Uint04,Int08,Sint16,Sint24,i,Q")]))
6990 - (clobber (reg:CC CC_REG))] ;; Because the cc flags are set based on comparing ops 2 & 3 not the value in op 0.
6991 + [(match_operand:SI 2 "register_operand" "r")
6992 + (match_operand:SI 3 "rx_source_operand" "riQ")]))
6993 + (clobber (reg:CC CC_REG))]
6996 - rx_float_compare_mode = false;
6997 - return "cmp\t%Q3, %Q2\n\tsc%B1.L\t%0";
6999 - [(set_attr "timings" "22,22,22,22,22,22,44")
7000 - (set_attr "length" "5,5,6,7,8,9,8")]
7002 + "reload_completed"
7007 + flags = gen_rtx_REG (CCmode, CC_REG);
7008 + x = gen_rtx_COMPARE (CCmode, operands[2], operands[3]);
7009 + x = gen_rtx_SET (VOIDmode, flags, x);
7012 + x = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode, flags, const0_rtx);
7013 + x = gen_rtx_SET (VOIDmode, operands[0], x);
7018 +(define_insn "*sccc"
7019 + [(set (match_operand:SI 0 "register_operand" "=r")
7020 + (match_operator:SI 1 "comparison_operator"
7021 + [(reg CC_REG) (const_int 0)]))]
7022 + "reload_completed"
7024 + [(set_attr "length" "3")]
7027 +(define_insn_and_split "cstoresf4"
7028 + [(set (match_operand:SI 0 "register_operand" "=r")
7029 + (match_operator:SI 1 "rx_fp_comparison_operator"
7030 + [(match_operand:SF 2 "register_operand" "r")
7031 + (match_operand:SF 3 "rx_source_operand" "rFQ")]))]
7032 + "ALLOW_RX_FPU_INSNS"
7034 + "reload_completed"
7039 + flags = gen_rtx_REG (CC_Fmode, CC_REG);
7040 + x = gen_rtx_COMPARE (CC_Fmode, operands[2], operands[3]);
7041 + x = gen_rtx_SET (VOIDmode, flags, x);
7044 + x = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode, flags, const0_rtx);
7045 + x = gen_rtx_SET (VOIDmode, operands[0], x);
7050 (define_expand "movsicc"
7052 [(set (match_operand:SI 0 "register_operand")
7053 (if_then_else:SI (match_operand:SI 1 "comparison_operator")
7054 (match_operand:SI 2 "nonmemory_operand")
7055 - (match_operand:SI 3 "immediate_operand")))
7056 - (clobber (reg:CC CC_REG))])] ;; See cstoresi4
7057 + (match_operand:SI 3 "nonmemory_operand")))
7058 + (clobber (reg:CC CC_REG))])]
7061 - if (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE)
7063 - if (! CONST_INT_P (operands[3]))
7068 + /* ??? Support other conditions via cstore into a temporary? */
7069 + if (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE)
7071 + /* One operand must be a constant. */
7072 + if (!CONSTANT_P (operands[2]) && !CONSTANT_P (operands[3]))
7076 -(define_insn "*movsieq"
7077 - [(set (match_operand:SI 0 "register_operand" "=r,r,r")
7078 - (if_then_else:SI (eq (match_operand:SI 3 "register_operand" "r,r,r")
7079 - (match_operand:SI 4 "rx_source_operand" "riQ,riQ,riQ"))
7080 - (match_operand:SI 1 "nonmemory_operand" "0,i,r")
7081 - (match_operand:SI 2 "immediate_operand" "i,i,i")))
7082 - (clobber (reg:CC CC_REG))] ;; See cstoresi4
7085 - cmp\t%Q4, %Q3\n\tstnz\t%2, %0
7086 - cmp\t%Q4, %Q3\n\tmov.l\t%2, %0\n\tstz\t%1, %0
7087 - cmp\t%Q4, %Q3\n\tmov.l\t%1, %0\n\tstnz\t%2, %0"
7088 - [(set_attr "length" "13,19,15")
7089 - (set_attr "timings" "22,33,33")]
7091 +(define_insn_and_split "*movsicc"
7092 + [(set (match_operand:SI 0 "register_operand" "=r,r")
7094 + (match_operator 5 "rx_z_comparison_operator"
7095 + [(match_operand:SI 3 "register_operand" "r,r")
7096 + (match_operand:SI 4 "rx_source_operand" "riQ,riQ")])
7097 + (match_operand:SI 1 "nonmemory_operand" "i,ri")
7098 + (match_operand:SI 2 "nonmemory_operand" "ri,i")))
7099 + (clobber (reg:CC CC_REG))]
7100 + "CONSTANT_P (operands[1]) || CONSTANT_P (operands[2])"
7102 + "&& reload_completed"
7105 + rtx x, flags, op0, op1, op2;
7106 + enum rtx_code cmp_code;
7108 -(define_insn "*movsine"
7109 - [(set (match_operand:SI 0 "register_operand" "=r,r,r")
7110 - (if_then_else:SI (ne (match_operand:SI 3 "register_operand" "r,r,r")
7111 - (match_operand:SI 4 "rx_source_operand" "riQ,riQ,riQ"))
7112 - (match_operand:SI 1 "nonmemory_operand" "0,i,r")
7113 - (match_operand:SI 2 "immediate_operand" "i,i,i")))
7114 - (clobber (reg:CC CC_REG))] ;; See cstoresi4
7117 - cmp\t%Q4, %Q3\n\tstz\t%2, %0
7118 - cmp\t%Q4, %Q3\n\tmov.l\t%2, %0\n\tstnz\t%1, %0
7119 - cmp\t%Q4, %Q3\n\tmov.l\t%1, %0\n\tstz\t%2, %0"
7120 - [(set_attr "length" "13,19,15")
7121 - (set_attr "timings" "22,33,33")]
7122 + flags = gen_rtx_REG (CCmode, CC_REG);
7123 + x = gen_rtx_COMPARE (CCmode, operands[3], operands[4]);
7124 + emit_insn (gen_rtx_SET (VOIDmode, flags, x));
7126 + cmp_code = GET_CODE (operands[5]);
7127 + op0 = operands[0];
7128 + op1 = operands[1];
7129 + op2 = operands[2];
7131 + /* If OP2 is the constant, reverse the sense of the move. */
7132 + if (!CONSTANT_P (operands[1]))
7134 + x = op1, op1 = op2, op2 = x;
7135 + cmp_code = reverse_condition (cmp_code);
7138 + /* If OP2 does not match the output, copy it into place. We have allowed
7139 + these alternatives so that the destination can legitimately be one of
7140 + the comparison operands without increasing register pressure. */
7141 + if (!rtx_equal_p (op0, op2))
7142 + emit_move_insn (op0, op2);
7144 + x = gen_rtx_fmt_ee (cmp_code, VOIDmode, flags, const0_rtx);
7145 + x = gen_rtx_IF_THEN_ELSE (SImode, x, op1, op0);
7146 + emit_insn (gen_rtx_SET (VOIDmode, op0, x));
7150 +(define_insn "*stcc"
7151 + [(set (match_operand:SI 0 "register_operand" "+r,r,r,r")
7153 + (match_operator 2 "rx_z_comparison_operator"
7154 + [(reg CC_REG) (const_int 0)])
7155 + (match_operand:SI 1 "immediate_operand" "Sint08,Sint16,Sint24,i")
7157 + "reload_completed"
7159 + if (GET_CODE (operands[2]) == EQ)
7160 + return "stz\t%1, %0";
7162 + return "stnz\t%1, %0";
7164 + [(set_attr "length" "4,5,6,7")]
7167 ;; Arithmetic Instructions
7169 (define_insn "abssi2"
7170 [(set (match_operand:SI 0 "register_operand" "=r,r")
7171 (abs:SI (match_operand:SI 1 "register_operand" "0,r")))
7172 - (set (reg:CC_ZSO CC_REG)
7173 - (compare:CC_ZSO (abs:SI (match_dup 1))
7175 + (clobber (reg:CC CC_REG))]
7179 @@ -817,13 +792,24 @@
7180 [(set_attr "length" "2,3")]
7183 +(define_insn "*abssi2_flags"
7184 + [(set (match_operand:SI 0 "register_operand" "=r,r")
7185 + (abs:SI (match_operand:SI 1 "register_operand" "0,r")))
7187 + (compare (abs:SI (match_dup 1))
7189 + "reload_completed && rx_match_ccmode (insn, CC_ZSOmode)"
7193 + [(set_attr "length" "2,3")]
7196 (define_insn "addsi3"
7197 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r,r,r,r,r,r")
7198 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,0,r,r,r,r,r,r,0")
7199 (match_operand:SI 2 "rx_source_operand" "r,Uint04,NEGint4,Sint08,Sint16,Sint24,i,0,r,Sint08,Sint16,Sint24,i,Q")))
7200 - (set (reg:CC_ZSC CC_REG) ;; See subsi3
7201 - (compare:CC_ZSC (plus:SI (match_dup 1) (match_dup 2))
7203 + (clobber (reg:CC CC_REG))]
7207 @@ -844,27 +830,170 @@
7208 (set_attr "length" "2,2,2,3,4,5,6,2,3,3,4,5,6,5")]
7211 -(define_insn "adddi3"
7212 - [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r")
7213 - (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,0,0")
7214 - (match_operand:DI 2 "rx_source_operand"
7215 - "r,Sint08,Sint16,Sint24,i,Q")))
7216 - (set (reg:CC_ZSC CC_REG) ;; See subsi3
7217 - (compare:CC_ZSC (plus:DI (match_dup 1) (match_dup 2))
7220 - "add\t%L2, %L0\n\tadc\t%H2, %H0"
7221 - [(set_attr "timings" "22,22,22,22,22,44")
7222 - (set_attr "length" "5,7,9,11,13,11")]
7223 +(define_insn "*addsi3_flags"
7224 + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r,r,r,r,r,r")
7225 + (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,0,r,r,r,r,r,r,0")
7226 + (match_operand:SI 2 "rx_source_operand" "r,Uint04,NEGint4,Sint08,Sint16,Sint24,i,0,r,Sint08,Sint16,Sint24,i,Q")))
7228 + (compare (plus:SI (match_dup 1) (match_dup 2))
7230 + "reload_completed && rx_match_ccmode (insn, CC_ZSCmode)"
7246 + [(set_attr "timings" "11,11,11,11,11,11,11,11,11,11,11,11,11,33")
7247 + (set_attr "length" "2,2,2,3,4,5,6,2,3,3,4,5,6,5")]
7250 +;; A helper to expand the above with the CC_MODE filled in.
7251 +(define_expand "addsi3_flags"
7252 + [(parallel [(set (match_operand:SI 0 "register_operand")
7253 + (plus:SI (match_operand:SI 1 "register_operand")
7254 + (match_operand:SI 2 "rx_source_operand")))
7255 + (set (reg:CC_ZSC CC_REG)
7256 + (compare:CC_ZSC (plus:SI (match_dup 1) (match_dup 2))
7257 + (const_int 0)))])]
7260 +(define_insn "adc_internal"
7261 + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
7264 + (ltu:SI (reg:CC CC_REG) (const_int 0))
7265 + (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0"))
7266 + (match_operand:SI 2 "rx_source_operand" "r,Sint08,Sint16,Sint24,i,Q")))
7267 + (clobber (reg:CC CC_REG))]
7268 + "reload_completed"
7270 + [(set_attr "timings" "11,11,11,11,11,33")
7271 + (set_attr "length" "3,4,5,6,7,6")]
7274 +(define_insn "*adc_flags"
7275 + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
7278 + (ltu:SI (reg:CC CC_REG) (const_int 0))
7279 + (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0"))
7280 + (match_operand:SI 2 "rx_source_operand" "r,Sint08,Sint16,Sint24,i,Q")))
7285 + (ltu:SI (reg:CC CC_REG) (const_int 0))
7289 + "reload_completed && rx_match_ccmode (insn, CC_ZSCmode)"
7291 + [(set_attr "timings" "11,11,11,11,11,33")
7292 + (set_attr "length" "3,4,5,6,7,6")]
7295 +(define_expand "adddi3"
7296 + [(set (match_operand:DI 0 "register_operand")
7297 + (plus:DI (match_operand:DI 1 "register_operand")
7298 + (match_operand:DI 2 "rx_source_operand")))]
7301 + rtx op0l, op0h, op1l, op1h, op2l, op2h;
7303 + op0l = gen_lowpart (SImode, operands[0]);
7304 + op1l = gen_lowpart (SImode, operands[1]);
7305 + op2l = gen_lowpart (SImode, operands[2]);
7306 + op0h = gen_highpart (SImode, operands[0]);
7307 + op1h = gen_highpart (SImode, operands[1]);
7308 + op2h = gen_highpart_mode (SImode, DImode, operands[2]);
7310 + emit_insn (gen_adddi3_internal (op0l, op0h, op1l, op2l, op1h, op2h));
7314 +(define_insn_and_split "adddi3_internal"
7315 + [(set (match_operand:SI 0 "register_operand" "=r")
7316 + (plus:SI (match_operand:SI 2 "register_operand" "r")
7317 + (match_operand:SI 3 "rx_source_operand" "riQ")))
7318 + (set (match_operand:SI 1 "register_operand" "=r")
7321 + (ltu:SI (plus:SI (match_dup 2) (match_dup 3)) (match_dup 2))
7322 + (match_operand:SI 4 "register_operand" "%1"))
7323 + (match_operand:SI 5 "rx_source_operand" "riQ")))
7324 + (clobber (match_scratch:SI 6 "=&r"))
7325 + (clobber (reg:CC CC_REG))]
7328 + "reload_completed"
7331 + rtx op0l = operands[0];
7332 + rtx op0h = operands[1];
7333 + rtx op1l = operands[2];
7334 + rtx op2l = operands[3];
7335 + rtx op1h = operands[4];
7336 + rtx op2h = operands[5];
7337 + rtx scratch = operands[6];
7340 + if (reg_overlap_mentioned_p (op0l, op1h))
7342 + emit_move_insn (scratch, op0l);
7344 + if (reg_overlap_mentioned_p (op0l, op2h))
7347 + else if (reg_overlap_mentioned_p (op0l, op2h))
7349 + emit_move_insn (scratch, op0l);
7353 + if (rtx_equal_p (op0l, op1l))
7355 + /* It is preferable that op0l == op1l... */
7356 + else if (rtx_equal_p (op0l, op2l))
7357 + x = op1l, op1l = op2l, op2l = x;
7358 + /* ... but it is only a requirement if op2l == MEM. */
7359 + else if (MEM_P (op2l))
7361 + /* Let's hope that we still have a scratch register free. */
7362 + gcc_assert (op1h != scratch);
7363 + emit_move_insn (scratch, op2l);
7367 + emit_insn (gen_addsi3_flags (op0l, op1l, op2l));
7369 + if (rtx_equal_p (op0h, op1h))
7371 + else if (rtx_equal_p (op0h, op2h))
7372 + x = op1h, op1h = op2h, op2h = x;
7375 + emit_move_insn (op0h, op1h);
7378 + emit_insn (gen_adc_internal (op0h, op1h, op2h));
7382 (define_insn "andsi3"
7383 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r")
7384 (and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0")
7385 (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q")))
7386 - (set (reg:CC_ZS CC_REG)
7387 - (compare:CC_ZS (and:SI (match_dup 1) (match_dup 2))
7389 + (clobber (reg:CC CC_REG))]
7393 @@ -880,9 +1009,31 @@
7394 (set_attr "length" "2,2,3,4,5,6,2,5,5")]
7397 +(define_insn "*andsi3_flags"
7398 + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r")
7399 + (and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0")
7400 + (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q")))
7402 + (compare (and:SI (match_dup 1) (match_dup 2))
7404 + "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
7415 + [(set_attr "timings" "11,11,11,11,11,11,11,33,33")
7416 + (set_attr "length" "2,2,3,4,5,6,2,5,5")]
7419 ;; Byte swap (single 32-bit value).
7420 (define_insn "bswapsi2"
7421 - [(set (match_operand:SI 0 "register_operand" "+r")
7422 + [(set (match_operand:SI 0 "register_operand" "=r")
7423 (bswap:SI (match_operand:SI 1 "register_operand" "r")))]
7426 @@ -891,7 +1042,7 @@
7428 ;; Byte swap (single 16-bit value). Note - we ignore the swapping of the high 16-bits.
7429 (define_insn "bswaphi2"
7430 - [(set (match_operand:HI 0 "register_operand" "+r")
7431 + [(set (match_operand:HI 0 "register_operand" "=r")
7432 (bswap:HI (match_operand:HI 1 "register_operand" "r")))]
7435 @@ -999,24 +1150,33 @@
7436 (define_insn "negsi2"
7437 [(set (match_operand:SI 0 "register_operand" "=r,r")
7438 (neg:SI (match_operand:SI 1 "register_operand" "0,r")))
7439 - (set (reg:CC CC_REG)
7440 - (compare:CC (neg:SI (match_dup 1))
7442 - ;; The NEG instruction does not comply with -fwrapv semantics.
7443 - ;; See gcc.c-torture/execute/pr22493-1.c for an example of this.
7445 + (clobber (reg:CC CC_REG))]
7450 [(set_attr "length" "2,3")]
7453 +;; Note that the O and C flags are not set as per a normal compare,
7454 +;; and thus are unusable in that context.
7455 +(define_insn "*negsi2_flags"
7456 + [(set (match_operand:SI 0 "register_operand" "=r,r")
7457 + (neg:SI (match_operand:SI 1 "register_operand" "0,r")))
7459 + (compare (neg:SI (match_dup 1))
7461 + "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
7465 + [(set_attr "length" "2,3")]
7468 (define_insn "one_cmplsi2"
7469 [(set (match_operand:SI 0 "register_operand" "=r,r")
7470 (not:SI (match_operand:SI 1 "register_operand" "0,r")))
7471 - (set (reg:CC_ZS CC_REG)
7472 - (compare:CC_ZS (not:SI (match_dup 1))
7474 + (clobber (reg:CC CC_REG))]
7478 @@ -1024,13 +1184,24 @@
7479 [(set_attr "length" "2,3")]
7482 +(define_insn "*one_cmplsi2_flags"
7483 + [(set (match_operand:SI 0 "register_operand" "=r,r")
7484 + (not:SI (match_operand:SI 1 "register_operand" "0,r")))
7486 + (compare (not:SI (match_dup 1))
7488 + "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
7492 + [(set_attr "length" "2,3")]
7495 (define_insn "iorsi3"
7496 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r")
7497 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0")
7498 (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q")))
7499 - (set (reg:CC_ZS CC_REG)
7500 - (compare:CC_ZS (ior:SI (match_dup 1) (match_dup 2))
7502 + (clobber (reg:CC CC_REG))]
7506 @@ -1046,37 +1217,77 @@
7507 (set_attr "length" "2,2,3,4,5,6,2,3,5")]
7510 +(define_insn "*iorsi3_flags"
7511 + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r")
7512 + (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0")
7513 + (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q")))
7515 + (compare (ior:SI (match_dup 1) (match_dup 2))
7517 + "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
7528 + [(set_attr "timings" "11,11,11,11,11,11,11,11,33")
7529 + (set_attr "length" "2,2,3,4,5,6,2,3,5")]
7532 (define_insn "rotlsi3"
7533 [(set (match_operand:SI 0 "register_operand" "=r")
7534 (rotate:SI (match_operand:SI 1 "register_operand" "0")
7535 (match_operand:SI 2 "rx_shift_operand" "rn")))
7536 - (set (reg:CC_ZS CC_REG)
7537 - (compare:CC_ZS (rotate:SI (match_dup 1) (match_dup 2))
7539 + (clobber (reg:CC CC_REG))]
7542 [(set_attr "length" "3")]
7545 +(define_insn "*rotlsi3_flags"
7546 + [(set (match_operand:SI 0 "register_operand" "=r")
7547 + (rotate:SI (match_operand:SI 1 "register_operand" "0")
7548 + (match_operand:SI 2 "rx_shift_operand" "rn")))
7550 + (compare (rotate:SI (match_dup 1) (match_dup 2))
7552 + "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
7554 + [(set_attr "length" "3")]
7557 (define_insn "rotrsi3"
7558 [(set (match_operand:SI 0 "register_operand" "=r")
7559 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
7560 (match_operand:SI 2 "rx_shift_operand" "rn")))
7561 - (set (reg:CC_ZS CC_REG)
7562 - (compare:CC_ZS (rotatert:SI (match_dup 1) (match_dup 2))
7564 + (clobber (reg:CC CC_REG))]
7567 [(set_attr "length" "3")]
7570 +(define_insn "*rotrsi3_flags"
7571 + [(set (match_operand:SI 0 "register_operand" "=r")
7572 + (rotatert:SI (match_operand:SI 1 "register_operand" "0")
7573 + (match_operand:SI 2 "rx_shift_operand" "rn")))
7575 + (compare (rotatert:SI (match_dup 1) (match_dup 2))
7577 + "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
7579 + [(set_attr "length" "3")]
7582 (define_insn "ashrsi3"
7583 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
7584 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
7585 (match_operand:SI 2 "rx_shift_operand" "r,n,n")))
7586 - (set (reg:CC_ZS CC_REG)
7587 - (compare:CC_ZS (ashiftrt:SI (match_dup 1) (match_dup 2))
7589 + (clobber (reg:CC CC_REG))]
7593 @@ -1085,13 +1296,26 @@
7594 [(set_attr "length" "3,2,3")]
7597 +(define_insn "*ashrsi3_flags"
7598 + [(set (match_operand:SI 0 "register_operand" "=r,r,r")
7599 + (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
7600 + (match_operand:SI 2 "rx_shift_operand" "r,n,n")))
7602 + (compare (ashiftrt:SI (match_dup 1) (match_dup 2))
7604 + "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
7609 + [(set_attr "length" "3,2,3")]
7612 (define_insn "lshrsi3"
7613 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
7614 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
7615 (match_operand:SI 2 "rx_shift_operand" "r,n,n")))
7616 - (set (reg:CC_ZS CC_REG)
7617 - (compare:CC_ZS (lshiftrt:SI (match_dup 1) (match_dup 2))
7619 + (clobber (reg:CC CC_REG))]
7623 @@ -1100,13 +1324,26 @@
7624 [(set_attr "length" "3,2,3")]
7627 +(define_insn "*lshrsi3_flags"
7628 + [(set (match_operand:SI 0 "register_operand" "=r,r,r")
7629 + (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
7630 + (match_operand:SI 2 "rx_shift_operand" "r,n,n")))
7632 + (compare (lshiftrt:SI (match_dup 1) (match_dup 2))
7634 + "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
7639 + [(set_attr "length" "3,2,3")]
7642 (define_insn "ashlsi3"
7643 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
7644 (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r")
7645 (match_operand:SI 2 "rx_shift_operand" "r,n,n")))
7646 - (set (reg:CC_ZS CC_REG)
7647 - (compare:CC_ZS (ashift:SI (match_dup 1) (match_dup 2))
7649 + (clobber (reg:CC CC_REG))]
7653 @@ -1115,16 +1352,57 @@
7654 [(set_attr "length" "3,2,3")]
7657 +(define_insn "*ashlsi3_flags"
7658 + [(set (match_operand:SI 0 "register_operand" "=r,r,r")
7659 + (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r")
7660 + (match_operand:SI 2 "rx_shift_operand" "r,n,n")))
7662 + (compare (ashift:SI (match_dup 1) (match_dup 2))
7664 + "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
7669 + [(set_attr "length" "3,2,3")]
7672 +;; Saturate to 32-bits
7673 +(define_insn_and_split "ssaddsi3"
7674 + [(set (match_operand:SI 0 "register_operand" "=r")
7675 + (ss_plus:SI (match_operand:SI 1 "register_operand" "r")
7676 + (match_operand:SI 2 "rx_source_operand" "riQ")))
7677 + (clobber (reg:CC CC_REG))]
7680 + "reload_completed"
7681 + [(parallel [(set (match_dup 0)
7682 + (plus:SI (match_dup 1) (match_dup 2)))
7683 + (set (reg:CC_ZSC CC_REG)
7685 + (plus:SI (match_dup 1) (match_dup 2))
7687 + (set (match_dup 0)
7688 + (unspec:SI [(match_dup 0) (reg:CC CC_REG)]
7689 + UNSPEC_BUILTIN_SAT))]
7693 +(define_insn "*sat"
7694 + [(set (match_operand:SI 0 "register_operand" "=r")
7695 + (unspec:SI [(match_operand:SI 1 "register_operand" "0")
7697 + UNSPEC_BUILTIN_SAT))]
7698 + "reload_completed"
7700 + [(set_attr "length" "2")]
7703 (define_insn "subsi3"
7704 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
7705 (minus:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0")
7706 (match_operand:SI 2 "rx_source_operand" "r,Uint04,n,r,Q")))
7707 - (set (reg:CC_ZSC CC_REG)
7708 - ;; Note - we do not acknowledge that the SUB instruction sets the Overflow
7709 - ;; flag because its interpretation is different from comparing the result
7710 - ;; against zero. Compile and run gcc.c-torture/execute/cmpsi-1.c to see this.
7711 - (compare:CC_ZSC (minus:SI (match_dup 1) (match_dup 2))
7713 + (clobber (reg:CC CC_REG))]
7717 @@ -1136,32 +1414,134 @@
7718 (set_attr "length" "2,2,6,3,5")]
7721 -(define_insn "subdi3"
7722 - [(set (match_operand:DI 0 "register_operand" "=r,r")
7723 - (minus:DI (match_operand:DI 1 "register_operand" "0,0")
7724 - (match_operand:DI 2 "rx_source_operand" "r,Q")))
7725 - (set (reg:CC_ZSC CC_REG) ;; See subsi3
7726 - (compare:CC_ZSC (minus:DI (match_dup 1) (match_dup 2))
7729 - "sub\t%L2, %L0\n\tsbb\t%H2, %H0"
7730 - [(set_attr "timings" "22,44")
7731 - (set_attr "length" "5,11")]
7732 +;; Note that the O flag is set as if (compare op1 op2) not for
7733 +;; what is described here, (compare op0 0).
7734 +(define_insn "*subsi3_flags"
7735 + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
7736 + (minus:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0")
7737 + (match_operand:SI 2 "rx_source_operand" "r,Uint04,n,r,Q")))
7739 + (compare (minus:SI (match_dup 1) (match_dup 2))
7741 + "reload_completed && rx_match_ccmode (insn, CC_ZSCmode)"
7748 + [(set_attr "timings" "11,11,11,11,33")
7749 + (set_attr "length" "2,2,6,3,5")]
7752 +;; A helper to expand the above with the CC_MODE filled in.
7753 +(define_expand "subsi3_flags"
7754 + [(parallel [(set (match_operand:SI 0 "register_operand")
7755 + (minus:SI (match_operand:SI 1 "register_operand")
7756 + (match_operand:SI 2 "rx_source_operand")))
7757 + (set (reg:CC_ZSC CC_REG)
7758 + (compare:CC_ZSC (minus:SI (match_dup 1) (match_dup 2))
7759 + (const_int 0)))])]
7762 +(define_insn "sbb_internal"
7763 + [(set (match_operand:SI 0 "register_operand" "=r,r")
7766 + (match_operand:SI 1 "register_operand" " 0,0")
7767 + (match_operand:SI 2 "rx_compare_operand" " r,Q"))
7768 + (geu:SI (reg:CC CC_REG) (const_int 0))))
7769 + (clobber (reg:CC CC_REG))]
7770 + "reload_completed"
7772 + [(set_attr "timings" "11,33")
7773 + (set_attr "length" "3,6")]
7776 +(define_insn "*sbb_flags"
7777 + [(set (match_operand:SI 0 "register_operand" "=r,r")
7780 + (match_operand:SI 1 "register_operand" " 0,0")
7781 + (match_operand:SI 2 "rx_compare_operand" " r,Q"))
7782 + (geu:SI (reg:CC CC_REG) (const_int 0))))
7786 + (minus:SI (match_dup 1) (match_dup 2))
7787 + (geu:SI (reg:CC CC_REG) (const_int 0)))
7789 + "reload_completed"
7791 + [(set_attr "timings" "11,33")
7792 + (set_attr "length" "3,6")]
7795 +(define_expand "subdi3"
7796 + [(set (match_operand:DI 0 "register_operand")
7797 + (minus:DI (match_operand:DI 1 "register_operand")
7798 + (match_operand:DI 2 "rx_compare_operand")))]
7801 + rtx op0l, op0h, op1l, op1h, op2l, op2h;
7803 + op0l = gen_lowpart (SImode, operands[0]);
7804 + op1l = gen_lowpart (SImode, operands[1]);
7805 + op2l = gen_lowpart (SImode, operands[2]);
7806 + op0h = gen_highpart (SImode, operands[0]);
7807 + op1h = gen_highpart (SImode, operands[1]);
7808 + op2h = gen_highpart_mode (SImode, DImode, operands[2]);
7810 + emit_insn (gen_subdi3_internal (op0l, op0h, op1l, op2l, op1h, op2h));
7814 +(define_insn_and_split "subdi3_internal"
7815 + [(set (match_operand:SI 0 "register_operand" "=&r,&r")
7816 + (minus:SI (match_operand:SI 2 "register_operand" " 0, r")
7817 + (match_operand:SI 3 "rx_compare_operand" "rQ, r")))
7818 + (set (match_operand:SI 1 "register_operand" "= r, r")
7821 + (match_operand:SI 4 "register_operand" " 1, 1")
7822 + (match_operand:SI 5 "rx_compare_operand" " rQ,rQ"))
7823 + (geu:SI (match_dup 2) (match_dup 3))))
7824 + (clobber (reg:CC CC_REG))]
7827 + "reload_completed"
7830 + emit_insn (gen_subsi3_flags (operands[0], operands[2], operands[3]));
7831 + emit_insn (gen_sbb_internal (operands[1], operands[4], operands[5]));
7835 (define_insn "xorsi3"
7836 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
7837 (xor:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
7838 (match_operand:SI 2 "rx_source_operand"
7839 "r,Sint08,Sint16,Sint24,i,Q")))
7840 - (set (reg:CC_ZS CC_REG)
7841 - (compare:CC_ZS (xor:SI (match_dup 1) (match_dup 2))
7843 + (clobber (reg:CC CC_REG))]
7846 [(set_attr "timings" "11,11,11,11,11,33")
7847 (set_attr "length" "3,4,5,6,7,6")]
7850 +(define_insn "*xorsi3_flags"
7851 + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
7852 + (xor:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
7853 + (match_operand:SI 2 "rx_source_operand"
7854 + "r,Sint08,Sint16,Sint24,i,Q")))
7856 + (compare (xor:SI (match_dup 1) (match_dup 2))
7858 + "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
7860 + [(set_attr "timings" "11,11,11,11,11,33")
7861 + (set_attr "length" "3,4,5,6,7,6")]
7864 ;; Floating Point Instructions
7866 @@ -1169,9 +1549,7 @@
7867 [(set (match_operand:SF 0 "register_operand" "=r,r,r")
7868 (plus:SF (match_operand:SF 1 "register_operand" "%0,0,0")
7869 (match_operand:SF 2 "rx_source_operand" "r,F,Q")))
7870 - (set (reg:CC_ZS CC_REG)
7871 - (compare:CC_ZS (plus:SF (match_dup 1) (match_dup 2))
7873 + (clobber (reg:CC CC_REG))]
7874 "ALLOW_RX_FPU_INSNS"
7876 [(set_attr "timings" "44,44,66")
7877 @@ -1182,9 +1560,7 @@
7878 [(set (match_operand:SF 0 "register_operand" "=r,r,r")
7879 (div:SF (match_operand:SF 1 "register_operand" "0,0,0")
7880 (match_operand:SF 2 "rx_source_operand" "r,F,Q")))
7881 - (set (reg:CC_ZS CC_REG)
7882 - (compare:CC_ZS (div:SF (match_dup 1) (match_dup 2))
7884 + (clobber (reg:CC CC_REG))]
7885 "ALLOW_RX_FPU_INSNS"
7887 [(set_attr "timings" "1616,1616,1818")
7888 @@ -1195,9 +1571,7 @@
7889 [(set (match_operand:SF 0 "register_operand" "=r,r,r")
7890 (mult:SF (match_operand:SF 1 "register_operand" "%0,0,0")
7891 (match_operand:SF 2 "rx_source_operand" "r,F,Q")))
7892 - (set (reg:CC_ZS CC_REG)
7893 - (compare:CC_ZS (mult:SF (match_dup 1) (match_dup 2))
7895 + (clobber (reg:CC CC_REG))]
7896 "ALLOW_RX_FPU_INSNS"
7898 [(set_attr "timings" "33,33,55")
7899 @@ -1208,9 +1582,7 @@
7900 [(set (match_operand:SF 0 "register_operand" "=r,r,r")
7901 (minus:SF (match_operand:SF 1 "register_operand" "0,0,0")
7902 (match_operand:SF 2 "rx_source_operand" "r,F,Q")))
7903 - (set (reg:CC_ZS CC_REG)
7904 - (compare:CC_ZS (minus:SF (match_dup 1) (match_dup 2))
7906 + (clobber (reg:CC CC_REG))]
7907 "ALLOW_RX_FPU_INSNS"
7909 [(set_attr "timings" "44,44,66")
7910 @@ -1220,9 +1592,7 @@
7911 (define_insn "fix_truncsfsi2"
7912 [(set (match_operand:SI 0 "register_operand" "=r,r")
7913 (fix:SI (match_operand:SF 1 "rx_compare_operand" "r,Q")))
7914 - (set (reg:CC_ZS CC_REG)
7915 - (compare:CC_ZS (fix:SI (match_dup 1))
7917 + (clobber (reg:CC CC_REG))]
7918 "ALLOW_RX_FPU_INSNS"
7920 [(set_attr "timings" "22,44")
7921 @@ -1232,9 +1602,7 @@
7922 (define_insn "floatsisf2"
7923 [(set (match_operand:SF 0 "register_operand" "=r,r")
7924 (float:SF (match_operand:SI 1 "rx_compare_operand" "r,Q")))
7925 - (set (reg:CC_ZS CC_REG)
7926 - (compare:CC_ZS (float:SF (match_dup 1))
7928 + (clobber (reg:CC CC_REG))]
7929 "ALLOW_RX_FPU_INSNS"
7931 [(set_attr "timings" "22,44")
7932 @@ -1242,217 +1610,216 @@
7935 ;; Bit manipulation instructions.
7936 -;; Note - there are two versions of each pattern because the memory
7937 -;; accessing versions use QImode whilst the register accessing
7938 -;; versions use SImode.
7939 -;; The peephole are here because the combiner only looks at a maximum
7940 -;; of three instructions at a time.
7942 -(define_insn "bitset"
7943 - [(set:SI (match_operand:SI 0 "register_operand" "=r")
7944 - (ior:SI (match_operand:SI 1 "register_operand" "0")
7945 - (ashift:SI (const_int 1)
7946 - (match_operand:SI 2 "nonmemory_operand" "ri"))))]
7947 +;; ??? The *_in_memory patterns will not be matched without further help.
7948 +;; At one time we had the insv expander generate them, but I suspect that
7949 +;; in general we get better performance by exposing the register load to
7952 +;; An alternate solution would be to re-organize these patterns such
7953 +;; that allow both register and memory operands. This would allow the
7954 +;; register allocator to spill and not load the register operand. This
7955 +;; would be possible only for operations for which we have a constant
7956 +;; bit offset, so that we can adjust the address by ofs/8 and replace
7957 +;; the offset in the insn by ofs%8.
7959 +(define_insn "*bitset"
7960 + [(set (match_operand:SI 0 "register_operand" "=r")
7961 + (ior:SI (ashift:SI (const_int 1)
7962 + (match_operand:SI 1 "rx_shift_operand" "ri"))
7963 + (match_operand:SI 2 "register_operand" "0")))]
7967 [(set_attr "length" "3")]
7970 -(define_insn "bitset_in_memory"
7971 - [(set:QI (match_operand:QI 0 "memory_operand" "=m")
7972 - (ior:QI (match_operand:QI 1 "memory_operand" "0")
7973 - (ashift:QI (const_int 1)
7974 - (match_operand:QI 2 "nonmemory_operand" "ri"))))]
7975 +(define_insn "*bitset_in_memory"
7976 + [(set (match_operand:QI 0 "memory_operand" "+Q")
7977 + (ior:QI (ashift:QI (const_int 1)
7978 + (match_operand:QI 1 "nonmemory_operand" "ri"))
7983 [(set_attr "length" "3")
7984 (set_attr "timings" "34")]
7987 -;; (set (reg A) (const_int 1))
7988 -;; (set (reg A) (ashift (reg A) (reg B)))
7989 -;; (set (reg C) (ior (reg A) (reg C)))
7991 - [(set:SI (match_operand:SI 0 "register_operand" "")
7993 - (set:SI (match_dup 0)
7994 - (ashift:SI (match_dup 0)
7995 - (match_operand:SI 1 "register_operand" "")))
7996 - (set:SI (match_operand:SI 2 "register_operand" "")
7997 - (ior:SI (match_dup 0)
7999 - "dead_or_set_p (insn, operands[0])"
8000 - [(set:SI (match_dup 2)
8001 - (ior:SI (match_dup 2)
8002 - (ashift:SI (const_int 1)
8006 -;; (set (reg A) (const_int 1))
8007 -;; (set (reg A) (ashift (reg A) (reg B)))
8008 -;; (set (reg A) (ior (reg A) (reg C)))
8009 -;; (set (reg C) (reg A)
8011 - [(set:SI (match_operand:SI 0 "register_operand" "")
8013 - (set:SI (match_dup 0)
8014 - (ashift:SI (match_dup 0)
8015 - (match_operand:SI 1 "register_operand" "")))
8016 - (set:SI (match_dup 0)
8017 - (ior:SI (match_dup 0)
8018 - (match_operand:SI 2 "register_operand" "")))
8019 - (set:SI (match_dup 2) (match_dup 0))]
8020 - "dead_or_set_p (insn, operands[0])"
8021 - [(set:SI (match_dup 2)
8022 - (ior:SI (match_dup 2)
8023 - (ashift:SI (const_int 1)
8027 -(define_insn "bitinvert"
8028 - [(set:SI (match_operand:SI 0 "register_operand" "+r")
8029 - (xor:SI (match_operand:SI 1 "register_operand" "0")
8030 - (ashift:SI (const_int 1)
8031 - (match_operand:SI 2 "nonmemory_operand" "ri"))))]
8032 +(define_insn "*bitinvert"
8033 + [(set (match_operand:SI 0 "register_operand" "=r")
8034 + (xor:SI (ashift:SI (const_int 1)
8035 + (match_operand:SI 1 "rx_shift_operand" "ri"))
8036 + (match_operand:SI 2 "register_operand" "0")))]
8040 [(set_attr "length" "3")]
8043 -(define_insn "bitinvert_in_memory"
8044 - [(set:QI (match_operand:QI 0 "memory_operand" "+m")
8045 - (xor:QI (match_operand:QI 1 "register_operand" "0")
8046 - (ashift:QI (const_int 1)
8047 - (match_operand:QI 2 "nonmemory_operand" "ri"))))]
8048 +(define_insn "*bitinvert_in_memory"
8049 + [(set (match_operand:QI 0 "memory_operand" "+Q")
8050 + (xor:QI (ashift:QI (const_int 1)
8051 + (match_operand:QI 1 "nonmemory_operand" "ri"))
8056 [(set_attr "length" "5")
8057 (set_attr "timings" "33")]
8060 -;; (set (reg A) (const_int 1))
8061 -;; (set (reg A) (ashift (reg A) (reg B)))
8062 -;; (set (reg C) (xor (reg A) (reg C)))
8064 - [(set:SI (match_operand:SI 0 "register_operand" "")
8066 - (set:SI (match_dup 0)
8067 - (ashift:SI (match_dup 0)
8068 - (match_operand:SI 1 "register_operand" "")))
8069 - (set:SI (match_operand:SI 2 "register_operand" "")
8070 - (xor:SI (match_dup 0)
8072 - "dead_or_set_p (insn, operands[0])"
8073 - [(set:SI (match_dup 2)
8074 - (xor:SI (match_dup 2)
8075 - (ashift:SI (const_int 1)
8077 +(define_insn "*bitclr"
8078 + [(set (match_operand:SI 0 "register_operand" "=r")
8082 + (match_operand:SI 1 "rx_shift_operand" "ri")))
8083 + (match_operand:SI 2 "register_operand" "0")))]
8086 + [(set_attr "length" "3")]
8089 -;; (set (reg A) (const_int 1))
8090 -;; (set (reg A) (ashift (reg A) (reg B)))
8091 -;; (set (reg A) (xor (reg A) (reg C)))
8092 -;; (set (reg C) (reg A))
8094 - [(set:SI (match_operand:SI 0 "register_operand" "")
8096 - (set:SI (match_dup 0)
8097 - (ashift:SI (match_dup 0)
8098 - (match_operand:SI 1 "register_operand" "")))
8099 - (set:SI (match_dup 0)
8100 - (xor:SI (match_dup 0)
8101 - (match_operand:SI 2 "register_operand" "")))
8102 - (set:SI (match_dup 2) (match_dup 0))]
8103 - "dead_or_set_p (insn, operands[0])"
8104 - [(set:SI (match_dup 2)
8105 - (xor:SI (match_dup 2)
8106 - (ashift:SI (const_int 1)
8109 +(define_insn "*bitclr_in_memory"
8110 + [(set (match_operand:QI 0 "memory_operand" "+Q")
8114 + (match_operand:QI 1 "nonmemory_operand" "ri")))
8118 + [(set_attr "length" "3")
8119 + (set_attr "timings" "34")]
8122 -(define_insn "bitclr"
8123 - [(set:SI (match_operand:SI 0 "register_operand" "+r")
8124 - (and:SI (match_operand:SI 1 "register_operand" "0")
8125 - (not:SI (ashift:SI (const_int 1)
8126 - (match_operand:SI 2 "nonmemory_operand" "ri")))))]
8127 +(define_insn "*insv_imm"
8128 + [(set (zero_extract:SI
8129 + (match_operand:SI 0 "register_operand" "+r")
8131 + (match_operand:SI 1 "rx_shift_operand" "ri"))
8132 + (match_operand:SI 2 "const_int_operand" ""))]
8136 + if (INTVAL (operands[2]) & 1)
8137 + return "bset\t%1, %0";
8139 + return "bclr\t%1, %0";
8141 [(set_attr "length" "3")]
8144 -(define_insn "bitclr_in_memory"
8145 - [(set:QI (match_operand:QI 0 "memory_operand" "+m")
8146 - (and:QI (match_operand:QI 1 "memory_operand" "0")
8147 - (not:QI (ashift:QI (const_int 1)
8148 - (match_operand:QI 2 "nonmemory_operand" "ri")))))]
8149 +(define_insn_and_split "rx_insv_reg"
8150 + [(set (zero_extract:SI
8151 + (match_operand:SI 0 "register_operand" "+r")
8153 + (match_operand:SI 1 "const_int_operand" ""))
8154 + (match_operand:SI 2 "register_operand" "r"))
8155 + (clobber (reg:CC CC_REG))]
8158 - [(set_attr "length" "3")
8159 - (set_attr "timings" "34")]
8161 + "reload_completed"
8162 + [(set (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1))
8167 + /* Emit tst #1, op2. */
8168 + flags = gen_rtx_REG (CC_ZSmode, CC_REG);
8169 + x = gen_rtx_AND (SImode, operands[2], const1_rtx);
8170 + x = gen_rtx_COMPARE (CC_ZSmode, x, const0_rtx);
8171 + x = gen_rtx_SET (VOIDmode, flags, x);
8175 + operands[3] = gen_rtx_NE (SImode, flags, const0_rtx);
8178 +(define_insn_and_split "*insv_cond"
8179 + [(set (zero_extract:SI
8180 + (match_operand:SI 0 "register_operand" "+r")
8182 + (match_operand:SI 1 "const_int_operand" ""))
8183 + (match_operator:SI 4 "comparison_operator"
8184 + [(match_operand:SI 2 "register_operand" "r")
8185 + (match_operand:SI 3 "rx_source_operand" "riQ")]))
8186 + (clobber (reg:CC CC_REG))]
8189 + "reload_completed"
8190 + [(set (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1))
8195 + flags = gen_rtx_REG (CCmode, CC_REG);
8196 + x = gen_rtx_COMPARE (CCmode, operands[2], operands[3]);
8197 + x = gen_rtx_SET (VOIDmode, flags, x);
8200 + operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
8201 + flags, const0_rtx);
8204 +(define_insn "*bmcc"
8205 + [(set (zero_extract:SI
8206 + (match_operand:SI 0 "register_operand" "+r")
8208 + (match_operand:SI 1 "const_int_operand" ""))
8209 + (match_operator:SI 2 "comparison_operator"
8210 + [(reg CC_REG) (const_int 0)]))]
8211 + "reload_completed"
8213 + [(set_attr "length" "3")]
8216 -;; (set (reg A) (const_int -2))
8217 -;; (set (reg A) (rotate (reg A) (reg B)))
8218 -;; (set (reg C) (and (reg A) (reg C)))
8220 - [(set:SI (match_operand:SI 0 "register_operand" "")
8222 - (set:SI (match_dup 0)
8223 - (rotate:SI (match_dup 0)
8224 - (match_operand:SI 1 "register_operand" "")))
8225 - (set:SI (match_operand:SI 2 "register_operand" "")
8226 - (and:SI (match_dup 0)
8228 - "dead_or_set_p (insn, operands[0])"
8229 - [(set:SI (match_dup 2)
8230 - (and:SI (match_dup 2)
8231 - (not:SI (ashift:SI (const_int 1)
8232 - (match_dup 1)))))]
8233 +;; Work around the fact that X=Y<0 is preferentially expanded as a shift.
8234 +(define_insn_and_split "*insv_cond_lt"
8235 + [(set (zero_extract:SI
8236 + (match_operand:SI 0 "register_operand" "+r")
8238 + (match_operand:SI 1 "const_int_operand" ""))
8239 + (match_operator:SI 3 "rshift_operator"
8240 + [(match_operand:SI 2 "register_operand" "r")
8242 + (clobber (reg:CC CC_REG))]
8246 + [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1))
8247 + (lt:SI (match_dup 2) (const_int 0)))
8248 + (clobber (reg:CC CC_REG))])]
8252 -;; (set (reg A) (const_int -2))
8253 -;; (set (reg A) (rotate (reg A) (reg B)))
8254 -;; (set (reg A) (and (reg A) (reg C)))
8255 -;; (set (reg C) (reg A)
8257 - [(set:SI (match_operand:SI 0 "register_operand" "")
8259 - (set:SI (match_dup 0)
8260 - (rotate:SI (match_dup 0)
8261 - (match_operand:SI 1 "register_operand" "")))
8262 - (set:SI (match_dup 0)
8263 - (and:SI (match_dup 0)
8264 - (match_operand:SI 2 "register_operand" "")))
8265 - (set:SI (match_dup 2) (match_dup 0))]
8266 - "dead_or_set_p (insn, operands[0])"
8267 - [(set:SI (match_dup 2)
8268 - (and:SI (match_dup 2)
8269 - (not:SI (ashift:SI (const_int 1)
8270 - (match_dup 1)))))]
8273 (define_expand "insv"
8274 - [(set:SI (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand") ;; Destination
8275 - (match_operand 1 "immediate_operand") ;; # of bits to set
8276 - (match_operand 2 "immediate_operand")) ;; Starting bit
8277 - (match_operand 3 "immediate_operand"))] ;; Bits to insert
8278 + [(set (zero_extract:SI
8279 + (match_operand:SI 0 "register_operand") ;; Destination
8280 + (match_operand:SI 1 "const_int_operand") ;; # of bits to set
8281 + (match_operand:SI 2 "nonmemory_operand")) ;; Starting bit
8282 + (match_operand:SI 3 "nonmemory_operand"))] ;; Bits to insert
8285 - if (rx_expand_insv (operands))
8287 + /* We only handle single-bit inserts. */
8288 + if (!CONST_INT_P (operands[1]) || INTVAL (operands[1]) != 1)
8291 + /* Either the bit to insert or the position must be constant. */
8292 + if (CONST_INT_P (operands[3]))
8293 + operands[3] = GEN_INT (INTVAL (operands[3]) & 1);
8294 + else if (CONST_INT_P (operands[2]))
8296 + emit_insn (gen_rx_insv_reg (operands[0], operands[2], operands[3]));
8305 ;; Atomic exchange operation.
8307 (define_insn "sync_lock_test_and_setsi"
8308 - [(set:SI (match_operand:SI 0 "register_operand" "=r,r")
8309 - (match_operand:SI 1 "rx_compare_operand" "=r,Q"))
8310 - (set:SI (match_dup 1)
8311 - (match_operand:SI 2 "register_operand" "0,0"))]
8312 + [(set (match_operand:SI 0 "register_operand" "=r,r")
8313 + (match_operand:SI 1 "rx_compare_operand" "=r,Q"))
8314 + (set (match_dup 1)
8315 + (match_operand:SI 2 "register_operand" "0,0"))]
8318 [(set_attr "length" "3,6")
8319 @@ -1462,9 +1829,9 @@
8320 ;; Block move functions.
8322 (define_expand "movstr"
8323 - [(set:SI (match_operand:BLK 1 "memory_operand") ;; Dest
8324 - (match_operand:BLK 2 "memory_operand")) ;; Source
8325 - (use (match_operand:SI 0 "register_operand")) ;; Updated Dest
8326 + [(set (match_operand:BLK 1 "memory_operand") ;; Dest
8327 + (match_operand:BLK 2 "memory_operand")) ;; Source
8328 + (use (match_operand:SI 0 "register_operand")) ;; Updated Dest
8332 @@ -1487,8 +1854,8 @@
8335 (define_insn "rx_movstr"
8336 - [(set:SI (mem:BLK (reg:SI 1))
8337 - (mem:BLK (reg:SI 2)))
8338 + [(set (mem:BLK (reg:SI 1))
8339 + (mem:BLK (reg:SI 2)))
8340 (unspec_volatile:BLK [(reg:SI 1) (reg:SI 2) (reg:SI 3)] UNSPEC_MOVSTR)
8341 (clobber (reg:SI 1))
8342 (clobber (reg:SI 2))
8343 @@ -1500,8 +1867,8 @@
8346 (define_insn "rx_strend"
8347 - [(set:SI (match_operand:SI 0 "register_operand" "=r")
8348 - (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
8349 + [(set (match_operand:SI 0 "register_operand" "=r")
8350 + (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
8351 (reg:SI 3)] UNSPEC_STRLEN))
8352 (clobber (reg:SI 1))
8353 (clobber (reg:SI 2))
8354 @@ -1582,8 +1949,8 @@
8357 (define_insn "rx_setmem"
8358 - [(set:BLK (mem:BLK (reg:SI 1)) (reg 2))
8359 - (unspec_volatile:BLK [(reg:SI 1) (reg:SI 2) (reg:SI 3)] UNSPEC_SETMEM)
8360 + [(set (mem:BLK (reg:SI 1))
8361 + (unspec_volatile:BLK [(reg:SI 1) (reg:SI 2) (reg:SI 3)] UNSPEC_SETMEM))
8362 (clobber (reg:SI 1))
8363 (clobber (reg:SI 3))]
8365 @@ -1636,11 +2003,11 @@
8368 (define_insn "rx_cmpstrn"
8369 - [(set:SI (match_operand:SI 0 "register_operand" "=r")
8370 - (unspec_volatile:SI [(reg:SI 1) (reg:SI 2) (reg:SI 3)]
8372 - (use (match_operand:BLK 1 "memory_operand" "m"))
8373 - (use (match_operand:BLK 2 "memory_operand" "m"))
8374 + [(set (match_operand:SI 0 "register_operand" "=r")
8375 + (unspec_volatile:SI [(reg:SI 1) (reg:SI 2) (reg:SI 3)]
8377 + (use (match_operand:BLK 1 "memory_operand" "m"))
8378 + (use (match_operand:BLK 2 "memory_operand" "m"))
8379 (clobber (reg:SI 1))
8380 (clobber (reg:SI 2))
8381 (clobber (reg:SI 3))
8382 @@ -1773,7 +2140,7 @@
8384 ;; Byte swap (two 16-bit values).
8386 - [(set (match_operand:SI 0 "register_operand" "+r")
8387 + [(set (match_operand:SI 0 "register_operand" "=r")
8388 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
8389 UNSPEC_BUILTIN_REVW))]
8391 @@ -1807,7 +2174,7 @@
8393 ;; Clear Processor Status Word
8394 (define_insn "clrpsw"
8395 - [(unspec:SI [(match_operand:SI 0 "immediate_operand" "i")]
8396 + [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")]
8397 UNSPEC_BUILTIN_CLRPSW)
8398 (clobber (reg:CC CC_REG))]
8400 @@ -1817,7 +2184,7 @@
8402 ;; Set Processor Status Word
8403 (define_insn "setpsw"
8404 - [(unspec:SI [(match_operand:SI 0 "immediate_operand" "i")]
8405 + [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")]
8406 UNSPEC_BUILTIN_SETPSW)
8407 (clobber (reg:CC CC_REG))]
8409 @@ -1828,7 +2195,7 @@
8410 ;; Move from control register
8412 [(set (match_operand:SI 0 "register_operand" "=r")
8413 - (unspec:SI [(match_operand:SI 1 "immediate_operand" "i")]
8414 + (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")]
8415 UNSPEC_BUILTIN_MVFC))]
8418 @@ -1837,7 +2204,7 @@
8420 ;; Move to control register
8422 - [(unspec:SI [(match_operand:SI 0 "immediate_operand" "i,i")
8423 + [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i,i")
8424 (match_operand:SI 1 "nonmemory_operand" "r,i")]
8425 UNSPEC_BUILTIN_MVTC)]
8427 @@ -1852,7 +2219,7 @@
8429 ;; Move to interrupt priority level
8430 (define_insn "mvtipl"
8431 - [(unspec:SI [(match_operand:SI 0 "immediate_operand" "Uint04")]
8432 + [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "Uint04")]
8433 UNSPEC_BUILTIN_MVTIPL)]
8436 Index: gcc/config/rx/rx.c
8437 ===================================================================
8438 --- gcc/config/rx/rx.c (.../tags/gcc_4_5_2_release) (wersja 170084)
8439 +++ gcc/config/rx/rx.c (.../branches/gcc-4_5-branch) (wersja 170084)
8441 /* Subroutines used for code generation on Renesas RX processors.
8442 - Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.
8443 + Copyright (C) 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
8444 Contributed by Red Hat.
8446 This file is part of GCC.
8448 #include "target-def.h"
8449 #include "langhooks.h"
8451 +#define CC_FLAG_S (1 << 0)
8452 +#define CC_FLAG_Z (1 << 1)
8453 +#define CC_FLAG_O (1 << 2)
8454 +#define CC_FLAG_C (1 << 3)
8455 +#define CC_FLAG_FP (1 << 4) /* Fake, to differentiate CC_Fmode. */
8457 enum rx_cpu_types rx_cpu_type = RX600;
8459 /* Return true if OP is a reference to an object in a small data area. */
8460 @@ -312,9 +318,18 @@
8465 + if (GET_CODE (XEXP (addr, 0)) == UNSPEC)
8467 + addr = XEXP (addr, 0);
8468 + gcc_assert (XINT (addr, 1) == UNSPEC_CONST);
8470 + addr = XVECEXP (addr, 0, 0);
8471 + gcc_assert (CONST_INT_P (addr));
8473 + /* Fall through. */
8477 fprintf (file, "#");
8479 output_addr_const (file, addr);
8480 @@ -351,9 +366,76 @@
8484 +/* Convert a CC_MODE to the set of flags that it represents. */
8486 -int rx_float_compare_mode;
8487 +static unsigned int
8488 +flags_from_mode (enum machine_mode mode)
8493 + return CC_FLAG_S | CC_FLAG_Z;
8495 + return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_O;
8497 + return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_C;
8499 + return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_O | CC_FLAG_C;
8501 + return CC_FLAG_FP;
8503 + gcc_unreachable ();
8507 +/* Convert a set of flags to a CC_MODE that can implement it. */
8509 +static enum machine_mode
8510 +mode_from_flags (unsigned int f)
8512 + if (f & CC_FLAG_FP)
8514 + if (f & CC_FLAG_O)
8516 + if (f & CC_FLAG_C)
8519 + return CC_ZSOmode;
8521 + else if (f & CC_FLAG_C)
8522 + return CC_ZSCmode;
8527 +/* Convert an RTX_CODE to the set of flags needed to implement it.
8528 + This assumes an integer comparison. */
8530 +static unsigned int
8531 +flags_from_code (enum rtx_code code)
8537 + return CC_FLAG_S | CC_FLAG_O;
8540 + return CC_FLAG_S | CC_FLAG_O | CC_FLAG_Z;
8546 + return CC_FLAG_C | CC_FLAG_Z;
8551 + gcc_unreachable ();
8555 /* Handles the insertion of a single operand into the assembler output.
8556 The %<letter> directives supported are:
8558 @@ -393,22 +475,49 @@
8562 - switch (GET_CODE (op))
8564 - case LT: fprintf (file, "lt"); break;
8565 - case GE: fprintf (file, "ge"); break;
8566 - case GT: fprintf (file, "gt"); break;
8567 - case LE: fprintf (file, "le"); break;
8568 - case GEU: fprintf (file, "geu"); break;
8569 - case LTU: fprintf (file, "ltu"); break;
8570 - case GTU: fprintf (file, "gtu"); break;
8571 - case LEU: fprintf (file, "leu"); break;
8572 - case EQ: fprintf (file, "eq"); break;
8573 - case NE: fprintf (file, "ne"); break;
8574 - default: debug_rtx (op); gcc_unreachable ();
8578 + enum rtx_code code = GET_CODE (op);
8579 + enum machine_mode mode = GET_MODE (XEXP (op, 0));
8582 + if (mode == CC_Fmode)
8584 + /* C flag is undefined, and O flag carries unordered. None of the
8585 + branch combinations that include O use it helpfully. */
8588 + case ORDERED: ret = "no"; break;
8589 + case UNORDERED: ret = "o"; break;
8590 + case LT: ret = "n"; break;
8591 + case GE: ret = "pz"; break;
8592 + case EQ: ret = "eq"; break;
8593 + case NE: ret = "ne"; break;
8594 + default: gcc_unreachable ();
8601 + case LT: ret = "lt"; break;
8602 + case GE: ret = "ge"; break;
8603 + case GT: ret = "gt"; break;
8604 + case LE: ret = "le"; break;
8605 + case GEU: ret = "geu"; break;
8606 + case LTU: ret = "ltu"; break;
8607 + case GTU: ret = "gtu"; break;
8608 + case LEU: ret = "leu"; break;
8609 + case EQ: ret = "eq"; break;
8610 + case NE: ret = "ne"; break;
8611 + default: gcc_unreachable ();
8613 + gcc_assert ((flags_from_code (code)
8614 + & ~flags_from_mode (mode)) == 0);
8616 + fputs (ret, file);
8621 gcc_assert (CONST_INT_P (op));
8622 switch (INTVAL (op))
8623 @@ -698,51 +807,6 @@
8624 extension, src_template, dst_template);
8625 return out_template;
8628 -/* Returns an assembler template for a conditional branch instruction. */
8631 -rx_gen_cond_branch_template (rtx condition, bool reversed)
8633 - enum rtx_code code = GET_CODE (condition);
8637 - if (rx_float_compare_mode)
8638 - code = reverse_condition_maybe_unordered (code);
8640 - code = reverse_condition (code);
8643 - /* We do not worry about encoding the branch length here as GAS knows
8644 - how to choose the smallest version, and how to expand a branch that
8645 - is to a destination that is out of range. */
8649 - case UNEQ: return "bo\t1f\n\tbeq\t%0\n1:";
8650 - case LTGT: return "bo\t1f\n\tbne\t%0\n1:";
8651 - case UNLT: return "bo\t1f\n\tbn\t%0\n1:";
8652 - case UNGE: return "bo\t1f\n\tbpz\t%0\n1:";
8653 - case UNLE: return "bo\t1f\n\tbgt\t1f\n\tbra\t%0\n1:";
8654 - case UNGT: return "bo\t1f\n\tble\t1f\n\tbra\t%0\n1:";
8655 - case UNORDERED: return "bo\t%0";
8656 - case ORDERED: return "bno\t%0";
8658 - case LT: return rx_float_compare_mode ? "bn\t%0" : "blt\t%0";
8659 - case GE: return rx_float_compare_mode ? "bpz\t%0" : "bge\t%0";
8660 - case GT: return "bgt\t%0";
8661 - case LE: return "ble\t%0";
8662 - case GEU: return "bgeu\t%0";
8663 - case LTU: return "bltu\t%0";
8664 - case GTU: return "bgtu\t%0";
8665 - case LEU: return "bleu\t%0";
8666 - case EQ: return "beq\t%0";
8667 - case NE: return "bne\t%0";
8669 - gcc_unreachable ();
8673 /* Return VALUE rounded up to the next ALIGNMENT boundary. */
8675 @@ -821,9 +885,37 @@
8676 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
8677 bool outgoing ATTRIBUTE_UNUSED)
8679 - return gen_rtx_REG (TYPE_MODE (ret_type), FUNC_RETURN_REGNUM);
8680 + enum machine_mode mode = TYPE_MODE (ret_type);
8682 + /* RX ABI specifies that small integer types are
8683 + promoted to int when returned by a function. */
8684 + if (GET_MODE_SIZE (mode) > 0
8685 + && GET_MODE_SIZE (mode) < 4
8686 + && ! COMPLEX_MODE_P (mode))
8687 + return gen_rtx_REG (SImode, FUNC_RETURN_REGNUM);
8689 + return gen_rtx_REG (mode, FUNC_RETURN_REGNUM);
8692 +/* TARGET_PROMOTE_FUNCTION_MODE must behave in the same way with
8693 + regard to function returns as does TARGET_FUNCTION_VALUE. */
8695 +static enum machine_mode
8696 +rx_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
8697 + enum machine_mode mode,
8698 + int * punsignedp ATTRIBUTE_UNUSED,
8699 + const_tree funtype ATTRIBUTE_UNUSED,
8702 + if (for_return != 1
8703 + || GET_MODE_SIZE (mode) >= 4
8704 + || COMPLEX_MODE_P (mode)
8705 + || GET_MODE_SIZE (mode) < 1)
8712 rx_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
8714 @@ -1058,7 +1150,13 @@
8716 for (save_mask = high = low = 0, reg = 1; reg < CC_REGNUM; reg++)
8718 - if (df_regs_ever_live_p (reg)
8719 + if ((df_regs_ever_live_p (reg)
8720 + /* Always save all call clobbered registers inside non-leaf
8721 + interrupt handlers, even if they are not live - they may
8722 + be used in (non-interrupt aware) routines called from this one. */
8723 + || (call_used_regs[reg]
8724 + && is_interrupt_func (NULL_TREE)
8725 + && ! current_function_is_leaf))
8726 && (! call_used_regs[reg]
8727 /* Even call clobbered registered must
8728 be pushed inside interrupt handlers. */
8729 @@ -1213,6 +1311,59 @@
8734 +ok_for_max_constant (HOST_WIDE_INT val)
8736 + if (rx_max_constant_size == 0 || rx_max_constant_size == 4)
8737 + /* If there is no constraint on the size of constants
8738 + used as operands, then any value is legitimate. */
8741 + /* rx_max_constant_size specifies the maximum number
8742 + of bytes that can be used to hold a signed value. */
8743 + return IN_RANGE (val, (-1 << (rx_max_constant_size * 8)),
8744 + ( 1 << (rx_max_constant_size * 8)));
8747 +/* Generate an ADD of SRC plus VAL into DEST.
8748 + Handles the case where VAL is too big for max_constant_value.
8749 + Sets FRAME_RELATED_P on the insn if IS_FRAME_RELATED is true. */
8752 +gen_safe_add (rtx dest, rtx src, rtx val, bool is_frame_related)
8756 + if (val == NULL_RTX || INTVAL (val) == 0)
8758 + gcc_assert (dest != src);
8760 + insn = emit_move_insn (dest, src);
8762 + else if (ok_for_max_constant (INTVAL (val)))
8763 + insn = emit_insn (gen_addsi3 (dest, src, val));
8766 + /* Wrap VAL in an UNSPEC so that rx_is_legitimate_constant
8767 + will not reject it. */
8768 + val = gen_rtx_CONST (SImode, gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_CONST));
8769 + insn = emit_insn (gen_addsi3 (dest, src, val));
8771 + if (is_frame_related)
8772 + /* We have to provide our own frame related note here
8773 + as the dwarf2out code cannot be expected to grok
8775 + add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8776 + gen_rtx_SET (SImode, dest,
8777 + gen_rtx_PLUS (SImode, src, val)));
8781 + if (is_frame_related)
8782 + RTX_FRAME_RELATED_P (insn) = 1;
8787 rx_expand_prologue (void)
8789 @@ -1298,24 +1449,13 @@
8790 emit_insn (gen_stack_pushm (GEN_INT (2 * UNITS_PER_WORD),
8791 gen_rx_store_vector (acc_low, acc_high)));
8794 - frame_size += 2 * UNITS_PER_WORD;
8797 /* If needed, set up the frame pointer. */
8798 if (frame_pointer_needed)
8801 - insn = emit_insn (gen_addsi3 (frame_pointer_rtx, stack_pointer_rtx,
8802 - GEN_INT (- (HOST_WIDE_INT) frame_size)));
8804 - insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
8805 + gen_safe_add (frame_pointer_rtx, stack_pointer_rtx,
8806 + GEN_INT (- (HOST_WIDE_INT) frame_size), true);
8808 - RTX_FRAME_RELATED_P (insn) = 1;
8813 /* Allocate space for the outgoing args.
8814 If the stack frame has not already been set up then handle this as well. */
8816 @@ -1323,29 +1463,26 @@
8819 if (frame_pointer_needed)
8820 - insn = emit_insn (gen_addsi3 (stack_pointer_rtx, frame_pointer_rtx,
8821 - GEN_INT (- (HOST_WIDE_INT)
8823 + gen_safe_add (stack_pointer_rtx, frame_pointer_rtx,
8824 + GEN_INT (- (HOST_WIDE_INT) stack_size), true);
8826 - insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
8827 - GEN_INT (- (HOST_WIDE_INT)
8828 - (frame_size + stack_size))));
8829 + gen_safe_add (stack_pointer_rtx, stack_pointer_rtx,
8830 + GEN_INT (- (HOST_WIDE_INT) (frame_size + stack_size)),
8834 - insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
8835 - GEN_INT (- (HOST_WIDE_INT) stack_size)));
8836 + gen_safe_add (stack_pointer_rtx, stack_pointer_rtx,
8837 + GEN_INT (- (HOST_WIDE_INT) stack_size), true);
8839 else if (frame_size)
8841 if (! frame_pointer_needed)
8842 - insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
8843 - GEN_INT (- (HOST_WIDE_INT) frame_size)));
8844 + gen_safe_add (stack_pointer_rtx, stack_pointer_rtx,
8845 + GEN_INT (- (HOST_WIDE_INT) frame_size), true);
8847 - insn = emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
8848 + gen_safe_add (stack_pointer_rtx, frame_pointer_rtx, NULL_RTX,
8852 - if (insn != NULL_RTX)
8853 - RTX_FRAME_RELATED_P (insn) = 1;
8857 @@ -1523,8 +1660,8 @@
8859 /* Cannot use the special instructions - deconstruct by hand. */
8861 - emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
8862 - GEN_INT (total_size)));
8863 + gen_safe_add (stack_pointer_rtx, stack_pointer_rtx,
8864 + GEN_INT (total_size), false);
8866 if (MUST_SAVE_ACC_REGISTER)
8868 @@ -1615,8 +1752,8 @@
8872 - emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
8873 - GEN_INT (total_size)));
8874 + gen_safe_add (stack_pointer_rtx, stack_pointer_rtx,
8875 + GEN_INT (total_size), false);
8879 @@ -1893,7 +2030,7 @@
8880 if (rx_cpu_type == RX610)
8883 - if (! CONST_INT_P (arg) || ! IN_RANGE (arg, 0, (1 << 4) - 1))
8884 + if (! CONST_INT_P (arg) || ! IN_RANGE (INTVAL (arg), 0, (1 << 4) - 1))
8887 emit_insn (gen_mvtipl (arg));
8888 @@ -1962,6 +2099,31 @@
8893 +valid_psw_flag (rtx op, const char *which)
8895 + static int mvtc_inform_done = 0;
8897 + if (GET_CODE (op) == CONST_INT)
8898 + switch (INTVAL (op))
8900 + case 0: case 'c': case 'C':
8901 + case 1: case 'z': case 'Z':
8902 + case 2: case 's': case 'S':
8903 + case 3: case 'o': case 'O':
8904 + case 8: case 'i': case 'I':
8905 + case 9: case 'u': case 'U':
8909 + error ("__builtin_rx_%s takes 'C', 'Z', 'S', 'O', 'I', or 'U'", which);
8910 + if (!mvtc_inform_done)
8911 + error ("use __builtin_rx_mvtc (0, ... ) to write arbitrary values to PSW");
8912 + mvtc_inform_done = 1;
8918 rx_expand_builtin (tree exp,
8920 @@ -1977,10 +2139,14 @@
8923 case RX_BUILTIN_BRK: emit_insn (gen_brk ()); return NULL_RTX;
8924 - case RX_BUILTIN_CLRPSW: return rx_expand_void_builtin_1_arg
8925 - (op, gen_clrpsw, false);
8926 - case RX_BUILTIN_SETPSW: return rx_expand_void_builtin_1_arg
8927 - (op, gen_setpsw, false);
8928 + case RX_BUILTIN_CLRPSW:
8929 + if (! valid_psw_flag (op, "clrpsw"))
8931 + return rx_expand_void_builtin_1_arg (op, gen_clrpsw, false);
8932 + if (! valid_psw_flag (op, "setpsw"))
8934 + return rx_expand_void_builtin_1_arg (op, gen_setpsw, false);
8935 + case RX_BUILTIN_SETPSW:
8936 case RX_BUILTIN_INT: return rx_expand_void_builtin_1_arg
8937 (op, gen_int, false);
8938 case RX_BUILTIN_MACHI: return rx_expand_builtin_mac (exp, gen_machi);
8939 @@ -2186,7 +2352,6 @@
8940 error ("Changing the FPU insns/math optimizations pairing is not supported");
8946 rx_allocate_stack_slots_for_args (void)
8947 @@ -2233,50 +2398,10 @@
8949 rx_is_ms_bitfield_layout (const_tree record_type ATTRIBUTE_UNUSED)
8952 + /* The packed attribute overrides the MS behaviour. */
8953 + return ! TYPE_PACKED (record_type);
8956 -/* Try to generate code for the "isnv" pattern which inserts bits
8958 - operands[0] => Location to be altered.
8959 - operands[1] => Number of bits to change.
8960 - operands[2] => Starting bit.
8961 - operands[3] => Value to insert.
8962 - Returns TRUE if successful, FALSE otherwise. */
8965 -rx_expand_insv (rtx * operands)
8967 - if (INTVAL (operands[1]) != 1
8968 - || ! CONST_INT_P (operands[3]))
8971 - if (MEM_P (operands[0])
8972 - && INTVAL (operands[2]) > 7)
8975 - switch (INTVAL (operands[3]))
8978 - if (MEM_P (operands[0]))
8979 - emit_insn (gen_bitclr_in_memory (operands[0], operands[0],
8982 - emit_insn (gen_bitclr (operands[0], operands[0], operands[2]));
8986 - if (MEM_P (operands[0]))
8987 - emit_insn (gen_bitset_in_memory (operands[0], operands[0],
8990 - emit_insn (gen_bitset (operands[0], operands[0], operands[2]));
8998 /* Returns true if X a legitimate constant for an immediate
8999 operand on the RX. X is already known to satisfy CONSTANT_P. */
9000 @@ -2284,8 +2409,6 @@
9002 rx_is_legitimate_constant (rtx x)
9004 - HOST_WIDE_INT val;
9006 switch (GET_CODE (x))
9009 @@ -2308,7 +2431,9 @@
9013 - /* One day we may have to handle UNSPEC constants here. */
9015 + return XINT (x, 1) == UNSPEC_CONST;
9018 /* FIXME: Can this ever happen ? */
9020 @@ -2328,17 +2453,7 @@
9024 - if (rx_max_constant_size == 0 || rx_max_constant_size == 4)
9025 - /* If there is no constraint on the size of constants
9026 - used as operands, then any value is legitimate. */
9031 - /* rx_max_constant_size specifies the maximum number
9032 - of bytes that can be used to hold a signed value. */
9033 - return IN_RANGE (val, (-1 << (rx_max_constant_size * 8)),
9034 - ( 1 << (rx_max_constant_size * 8)));
9035 + return ok_for_max_constant (INTVAL (x));
9039 @@ -2462,211 +2577,83 @@
9043 +/* Return a CC_MODE of which both M1 and M2 are subsets. */
9045 static enum machine_mode
9046 rx_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
9054 + /* Early out for identical modes. */
9057 - if (m1 == CC_ZSmode)
9059 - if (m2 == CC_ZSmode)
9063 + /* There's no valid combination for FP vs non-FP. */
9064 + f = flags_from_mode (m1) | flags_from_mode (m2);
9065 + if (f & CC_FLAG_FP)
9068 + /* Otherwise, see what mode can implement all the flags. */
9069 + return mode_from_flags (f);
9072 -#define CC_FLAG_S (1 << 0)
9073 -#define CC_FLAG_Z (1 << 1)
9074 -#define CC_FLAG_O (1 << 2)
9075 -#define CC_FLAG_C (1 << 3)
9076 +/* Return the minimal CC mode needed to implement (CMP_CODE X Y). */
9078 -static unsigned int
9079 -flags_needed_for_conditional (rtx conditional)
9081 +rx_select_cc_mode (enum rtx_code cmp_code, rtx x, rtx y ATTRIBUTE_UNUSED)
9083 - switch (GET_CODE (conditional))
9086 - case GT: return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_O;
9087 + if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
9091 - case GTU: return CC_FLAG_Z | CC_FLAG_C;
9092 + return mode_from_flags (flags_from_code (cmp_code));
9096 - case GE: return CC_FLAG_S | CC_FLAG_O;
9097 +/* Split the conditional branch. Emit (COMPARE C1 C2) into CC_REG with
9098 + CC_MODE, and use that in branches based on that compare. */
9101 - case GEU: return CC_FLAG_C;
9103 +rx_split_cbranch (enum machine_mode cc_mode, enum rtx_code cmp1,
9104 + rtx c1, rtx c2, rtx label)
9109 - case NE: return CC_FLAG_Z;
9110 + flags = gen_rtx_REG (cc_mode, CC_REG);
9111 + x = gen_rtx_COMPARE (cc_mode, c1, c2);
9112 + x = gen_rtx_SET (VOIDmode, flags, x);
9115 - default: gcc_unreachable ();
9117 + x = gen_rtx_fmt_ee (cmp1, VOIDmode, flags, const0_rtx);
9118 + x = gen_rtx_IF_THEN_ELSE (VOIDmode, x, label, pc_rtx);
9119 + x = gen_rtx_SET (VOIDmode, pc_rtx, x);
9120 + emit_jump_insn (x);
9123 -static unsigned int
9124 -flags_from_mode (enum machine_mode mode)
9128 - case CCmode: return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_O | CC_FLAG_C;
9129 - case CC_ZSmode: return CC_FLAG_S | CC_FLAG_Z;
9130 - case CC_ZSOmode: return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_O;
9131 - case CC_ZSCmode: return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_C;
9132 - default: gcc_unreachable ();
9135 +/* A helper function for matching parallels that set the flags. */
9137 -/* Returns true if a compare insn is redundant because it
9138 - would only set flags that are already set correctly. */
9141 -rx_compare_redundant (rtx cmp)
9142 +rx_match_ccmode (rtx insn, enum machine_mode cc_mode)
9144 - unsigned int flags_needed;
9145 - unsigned int flags_set;
9150 - static rtx cc_reg = NULL_RTX;
9152 + enum machine_mode flags_mode;
9154 - if (cc_reg == NULL_RTX)
9155 - cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
9156 + gcc_assert (XVECLEN (PATTERN (insn), 0) == 2);
9158 - /* We can only eliminate compares against 0. */
9159 - if (GET_CODE (XEXP (SET_SRC (PATTERN (cmp)), 1)) != CONST_INT
9160 - || INTVAL (XEXP (SET_SRC (PATTERN (cmp)), 1)) != 0)
9162 + op1 = XVECEXP (PATTERN (insn), 0, 1);
9163 + gcc_assert (GET_CODE (SET_SRC (op1)) == COMPARE);
9165 - /* Locate the branch insn that follows the
9166 - compare and which tests the bits in the PSW. */
9170 - /* If we have found an insn that sets or clobbers the CC
9171 - register and it was not the IF_THEN_ELSE insn that we
9172 - are looking for, then the comparison is redundant. */
9173 - if (next != cmp && reg_mentioned_p (cc_reg, PATTERN (next)))
9175 + flags = SET_DEST (op1);
9176 + flags_mode = GET_MODE (flags);
9178 - next = next_nonnote_insn (next);
9179 + if (GET_MODE (SET_SRC (op1)) != flags_mode)
9181 + if (GET_MODE_CLASS (flags_mode) != MODE_CC)
9184 - /* If we run out of insns without finding the
9185 - user then the comparison is unnecessary. */
9186 - if (next == NULL_RTX)
9188 + /* Ensure that the mode of FLAGS is compatible with CC_MODE. */
9189 + if (flags_from_mode (flags_mode) & ~flags_from_mode (cc_mode))
9192 - /* If we have found another comparison
9193 - insn then the first one is redundant. */
9195 - && GET_CODE (PATTERN (next)) == SET
9196 - && REG_P (SET_DEST (PATTERN (next)))
9197 - && REGNO (SET_DEST (PATTERN (next))) == CC_REGNUM)
9200 - /* If we have found another arithmetic/logic insn that
9201 - sets the PSW flags then the comparison is redundant. */
9203 - && GET_CODE (PATTERN (next)) == PARALLEL
9204 - && GET_CODE (XVECEXP (PATTERN (next), 0, 1)) == SET
9205 - && REG_P (SET_DEST (XVECEXP (PATTERN (next), 0, 1)))
9206 - && REGNO (SET_DEST (XVECEXP (PATTERN (next), 0, 1))) == CC_REGNUM)
9209 - /* If we have found an unconditional branch then the
9210 - PSW flags might be carried along with the jump, so
9211 - the comparison is necessary. */
9212 - if (INSN_P (next) && JUMP_P (next))
9214 - if (GET_CODE (PATTERN (next)) != SET)
9215 - /* If the jump does not involve setting the PC
9216 - then it is a return of some kind, and we know
9217 - that the comparison is not used. */
9220 - if (GET_CODE (SET_SRC (PATTERN (next))) != IF_THEN_ELSE)
9224 - while (! INSN_P (next)
9225 - || DEBUG_INSN_P (next)
9226 - || GET_CODE (PATTERN (next)) != SET
9227 - || GET_CODE (SET_SRC (PATTERN (next))) != IF_THEN_ELSE);
9229 - flags_needed = flags_needed_for_conditional (XEXP (SET_SRC (PATTERN (next)), 0));
9231 - /* Now look to see if there was a previous
9232 - instruction which set the PSW bits. */
9233 - source = XEXP (SET_SRC (PATTERN (cmp)), 0);
9237 - /* If this insn uses/sets/clobbers the CC register
9238 - and it is not the insn that we are looking for
9239 - below, then we must need the comparison. */
9240 - if (prev != cmp && reg_mentioned_p (cc_reg, PATTERN (prev)))
9243 - prev = prev_nonnote_insn (prev);
9245 - if (prev == NULL_RTX)
9248 - /* If we encounter an insn which changes the contents of
9249 - the register which is the source of the comparison then
9250 - we will definitely need the comparison. */
9252 - && GET_CODE (PATTERN (prev)) == SET
9253 - && rtx_equal_p (SET_DEST (PATTERN (prev)), source))
9255 - /* Unless this instruction is a simple register move
9256 - instruction. In which case we can continue our
9257 - scan backwards, but now using the *source* of this
9258 - set instruction. */
9259 - if (REG_P (SET_SRC (PATTERN (prev))))
9260 - source = SET_SRC (PATTERN (prev));
9261 - /* We can also survive a sign-extension if the test is
9262 - for EQ/NE. Note the same does not apply to zero-
9263 - extension as this can turn a non-zero bit-pattern
9265 - else if (flags_needed == CC_FLAG_Z
9266 - && GET_CODE (SET_SRC (PATTERN (prev))) == SIGN_EXTEND)
9267 - source = XEXP (SET_SRC (PATTERN (prev)), 0);
9272 - /* A label means a possible branch into the
9273 - code here, so we have to stop scanning. */
9274 - if (LABEL_P (prev))
9277 - while (! INSN_P (prev)
9278 - || DEBUG_INSN_P (prev)
9279 - || GET_CODE (PATTERN (prev)) != PARALLEL
9280 - || GET_CODE (XVECEXP (PATTERN (prev), 0, 1)) != SET
9281 - || ! REG_P (SET_DEST (XVECEXP (PATTERN (prev), 0, 1)))
9282 - || REGNO (SET_DEST (XVECEXP (PATTERN (prev), 0, 1))) != CC_REGNUM);
9284 - flags_set = flags_from_mode (GET_MODE (SET_DEST (XVECEXP (PATTERN (prev), 0, 1))));
9286 - dest = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
9287 - /* The destination of the previous arithmetic/logic instruction
9288 - must match the source in the comparison operation. For registers
9289 - we ignore the mode as there may have been a sign-extension involved. */
9290 - if (! rtx_equal_p (source, dest))
9292 - if (REG_P (source) && REG_P (dest) && REGNO (dest) == REGNO (source))
9298 - return ((flags_set & flags_needed) == flags_needed);
9302 #undef TARGET_FUNCTION_VALUE
9303 @@ -2759,6 +2746,9 @@
9304 #undef TARGET_CC_MODES_COMPATIBLE
9305 #define TARGET_CC_MODES_COMPATIBLE rx_cc_modes_compatible
9307 +#undef TARGET_PROMOTE_FUNCTION_MODE
9308 +#define TARGET_PROMOTE_FUNCTION_MODE rx_promote_function_mode
9310 struct gcc_target targetm = TARGET_INITIALIZER;
9312 /* #include "gt-rx.h" */
9313 Index: gcc/config/rx/rx-modes.def
9314 ===================================================================
9315 --- gcc/config/rx/rx-modes.def (.../tags/gcc_4_5_2_release) (wersja 170084)
9316 +++ gcc/config/rx/rx-modes.def (.../branches/gcc-4_5-branch) (wersja 170084)
9318 -/* Definitions of target machine for GNU compiler, for RX.
9319 - Copyright (C) 2010 by Nick Clifton (nickc@redhat.com).
9320 +/* Definitions of target specific machine modes for the RX.
9321 + Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.
9322 + Contributed by Red Hat.
9324 This file is part of GCC.
9331 +CC_MODE (CC_F); /* fcmp */
9332 Index: gcc/config/i386/i386.md
9333 ===================================================================
9334 --- gcc/config/i386/i386.md (.../tags/gcc_4_5_2_release) (wersja 170084)
9335 +++ gcc/config/i386/i386.md (.../branches/gcc-4_5-branch) (wersja 170084)
9338 (UNSPEC_TLS_LD_BASE 22)
9340 + (UNSPEC_TLS_IE_SUN 24)
9342 ; Other random patterns
9344 @@ -14702,6 +14703,18 @@
9345 (set_attr "memory" "load")
9346 (set_attr "imm_disp" "false")])
9348 +;; The Sun linker took the AMD64 TLS spec literally and can only handle
9349 +;; %rax as destination of the initial executable code sequence.
9350 +(define_insn "tls_initial_exec_64_sun"
9351 + [(set (match_operand:DI 0 "register_operand" "=a")
9353 + [(match_operand:DI 1 "tls_symbolic_operand" "")]
9354 + UNSPEC_TLS_IE_SUN))
9355 + (clobber (reg:CC FLAGS_REG))]
9356 + "TARGET_64BIT && TARGET_SUN_TLS"
9357 + "mov{q}\t{%%fs:0, %0|%0, QWORD PTR fs:0}\n\tadd{q}\t{%a1@gottpoff(%%rip), %0|%0, %a1@gottpoff[rip]}"
9358 + [(set_attr "type" "multi")])
9360 ;; GNU2 TLS patterns can be split.
9362 (define_expand "tls_dynamic_gnu2_32"
9363 Index: gcc/config/i386/sse.md
9364 ===================================================================
9365 --- gcc/config/i386/sse.md (.../tags/gcc_4_5_2_release) (wersja 170084)
9366 +++ gcc/config/i386/sse.md (.../branches/gcc-4_5-branch) (wersja 170084)
9367 @@ -5011,7 +5011,7 @@
9368 movsd\t{%2, %0|%0, %2}
9369 movlpd\t{%2, %0|%0, %2}
9370 movsd\t{%2, %0|%0, %2}
9371 - shufpd\t{$2, %2, %0|%0, %2, 2}
9372 + shufpd\t{$2, %1, %0|%0, %1, 2}
9373 movhpd\t{%H1, %0|%0, %H1}
9376 @@ -5090,7 +5090,7 @@
9377 movsd\t{%2, %0|%0, %2}
9378 movlpd\t{%2, %0|%0, %2}
9379 movlpd\t{%2, %0|%0, %2}
9380 - shufpd\t{$2, %2, %0|%0, %2, 2}
9381 + shufpd\t{$2, %1, %0|%0, %1, 2}
9382 movhps\t{%H1, %0|%0, %H1}
9383 movhps\t{%1, %H0|%H0, %1}"
9384 [(set_attr "type" "ssemov,ssemov,ssemov,sselog,ssemov,ssemov")
9385 @@ -12097,7 +12097,7 @@
9386 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
9388 [(match_operand:AVXMODEF2P 1 "memory_operand" "m")
9389 - (match_operand:AVXMODEF2P 2 "register_operand" "x")
9390 + (match_operand:<avxpermvecmode> 2 "register_operand" "x")
9394 @@ -12110,7 +12110,7 @@
9395 (define_insn "avx_maskstorep<avxmodesuffixf2c><avxmodesuffix>"
9396 [(set (match_operand:AVXMODEF2P 0 "memory_operand" "=m")
9398 - [(match_operand:AVXMODEF2P 1 "register_operand" "x")
9399 + [(match_operand:<avxpermvecmode> 1 "register_operand" "x")
9400 (match_operand:AVXMODEF2P 2 "register_operand" "x")
9403 Index: gcc/config/i386/i386-builtin-types.def
9404 ===================================================================
9405 --- gcc/config/i386/i386-builtin-types.def (.../tags/gcc_4_5_2_release) (wersja 170084)
9406 +++ gcc/config/i386/i386-builtin-types.def (.../branches/gcc-4_5-branch) (wersja 170084)
9408 DEF_FUNCTION_TYPE (V1DI, V1DI, V1DI)
9409 DEF_FUNCTION_TYPE (V1DI, V2SI, V2SI)
9410 DEF_FUNCTION_TYPE (V1DI, V8QI, V8QI)
9411 -DEF_FUNCTION_TYPE (V2DF, PCV2DF, V2DF)
9412 +DEF_FUNCTION_TYPE (V2DF, PCV2DF, V2DI)
9413 DEF_FUNCTION_TYPE (V2DF, V2DF, DI)
9414 DEF_FUNCTION_TYPE (V2DF, V2DF, INT)
9415 DEF_FUNCTION_TYPE (V2DF, V2DF, PCDOUBLE)
9417 DEF_FUNCTION_TYPE (V2SI, V2SI, SI)
9418 DEF_FUNCTION_TYPE (V2SI, V2SI, V2SI)
9419 DEF_FUNCTION_TYPE (V2SI, V4HI, V4HI)
9420 -DEF_FUNCTION_TYPE (V4DF, PCV4DF, V4DF)
9421 +DEF_FUNCTION_TYPE (V4DF, PCV4DF, V4DI)
9422 DEF_FUNCTION_TYPE (V4DF, V4DF, INT)
9423 DEF_FUNCTION_TYPE (V4DF, V4DF, V4DF)
9424 DEF_FUNCTION_TYPE (V4DF, V4DF, V4DI)
9426 DEF_FUNCTION_TYPE (V4HI, V4HI, SI)
9427 DEF_FUNCTION_TYPE (V4HI, V4HI, V4HI)
9428 DEF_FUNCTION_TYPE (V4HI, V8QI, V8QI)
9429 -DEF_FUNCTION_TYPE (V4SF, PCV4SF, V4SF)
9430 +DEF_FUNCTION_TYPE (V4SF, PCV4SF, V4SI)
9431 DEF_FUNCTION_TYPE (V4SF, V4SF, DI)
9432 DEF_FUNCTION_TYPE (V4SF, V4SF, INT)
9433 DEF_FUNCTION_TYPE (V4SF, V4SF, PCV2SF)
9435 DEF_FUNCTION_TYPE (V8HI, V8HI, V8HI)
9436 DEF_FUNCTION_TYPE (V8QI, V4HI, V4HI)
9437 DEF_FUNCTION_TYPE (V8QI, V8QI, V8QI)
9438 -DEF_FUNCTION_TYPE (V8SF, PCV8SF, V8SF)
9439 +DEF_FUNCTION_TYPE (V8SF, PCV8SF, V8SI)
9440 DEF_FUNCTION_TYPE (V8SF, V8SF, INT)
9441 DEF_FUNCTION_TYPE (V8SF, V8SF, V8SF)
9442 DEF_FUNCTION_TYPE (V8SF, V8SF, V8SI)
9443 @@ -343,10 +343,10 @@
9444 DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, INT)
9445 DEF_FUNCTION_TYPE (V8SI, V8SI, V8SI, V8SI)
9446 DEF_FUNCTION_TYPE (VOID, PCVOID, UNSIGNED, UNSIGNED)
9447 -DEF_FUNCTION_TYPE (VOID, PV2DF, V2DF, V2DF)
9448 -DEF_FUNCTION_TYPE (VOID, PV4DF, V4DF, V4DF)
9449 -DEF_FUNCTION_TYPE (VOID, PV4SF, V4SF, V4SF)
9450 -DEF_FUNCTION_TYPE (VOID, PV8SF, V8SF, V8SF)
9451 +DEF_FUNCTION_TYPE (VOID, PV2DF, V2DI, V2DF)
9452 +DEF_FUNCTION_TYPE (VOID, PV4DF, V4DI, V4DF)
9453 +DEF_FUNCTION_TYPE (VOID, PV4SF, V4SI, V4SF)
9454 +DEF_FUNCTION_TYPE (VOID, PV8SF, V8SI, V8SF)
9455 DEF_FUNCTION_TYPE (VOID, UINT, UINT, UINT)
9456 DEF_FUNCTION_TYPE (VOID, UINT64, UINT, UINT)
9457 DEF_FUNCTION_TYPE (VOID, V16QI, V16QI, PCHAR)
9458 Index: gcc/config/i386/avxintrin.h
9459 ===================================================================
9460 --- gcc/config/i386/avxintrin.h (.../tags/gcc_4_5_2_release) (wersja 170084)
9461 +++ gcc/config/i386/avxintrin.h (.../branches/gcc-4_5-branch) (wersja 170084)
9462 @@ -890,55 +890,55 @@
9465 extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
9466 -_mm_maskload_pd (double const *__P, __m128d __M)
9467 +_mm_maskload_pd (double const *__P, __m128i __M)
9469 return (__m128d) __builtin_ia32_maskloadpd ((const __v2df *)__P,
9474 extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
9475 -_mm_maskstore_pd (double *__P, __m128d __M, __m128d __A)
9476 +_mm_maskstore_pd (double *__P, __m128i __M, __m128d __A)
9478 - __builtin_ia32_maskstorepd ((__v2df *)__P, (__v2df)__M, (__v2df)__A);
9479 + __builtin_ia32_maskstorepd ((__v2df *)__P, (__v2di)__M, (__v2df)__A);
9482 extern __inline __m256d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
9483 -_mm256_maskload_pd (double const *__P, __m256d __M)
9484 +_mm256_maskload_pd (double const *__P, __m256i __M)
9486 return (__m256d) __builtin_ia32_maskloadpd256 ((const __v4df *)__P,
9491 extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
9492 -_mm256_maskstore_pd (double *__P, __m256d __M, __m256d __A)
9493 +_mm256_maskstore_pd (double *__P, __m256i __M, __m256d __A)
9495 - __builtin_ia32_maskstorepd256 ((__v4df *)__P, (__v4df)__M, (__v4df)__A);
9496 + __builtin_ia32_maskstorepd256 ((__v4df *)__P, (__v4di)__M, (__v4df)__A);
9499 extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
9500 -_mm_maskload_ps (float const *__P, __m128 __M)
9501 +_mm_maskload_ps (float const *__P, __m128i __M)
9503 return (__m128) __builtin_ia32_maskloadps ((const __v4sf *)__P,
9508 extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
9509 -_mm_maskstore_ps (float *__P, __m128 __M, __m128 __A)
9510 +_mm_maskstore_ps (float *__P, __m128i __M, __m128 __A)
9512 - __builtin_ia32_maskstoreps ((__v4sf *)__P, (__v4sf)__M, (__v4sf)__A);
9513 + __builtin_ia32_maskstoreps ((__v4sf *)__P, (__v4si)__M, (__v4sf)__A);
9516 extern __inline __m256 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
9517 -_mm256_maskload_ps (float const *__P, __m256 __M)
9518 +_mm256_maskload_ps (float const *__P, __m256i __M)
9520 return (__m256) __builtin_ia32_maskloadps256 ((const __v8sf *)__P,
9525 extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
9526 -_mm256_maskstore_ps (float *__P, __m256 __M, __m256 __A)
9527 +_mm256_maskstore_ps (float *__P, __m256i __M, __m256 __A)
9529 - __builtin_ia32_maskstoreps256 ((__v8sf *)__P, (__v8sf)__M, (__v8sf)__A);
9530 + __builtin_ia32_maskstoreps256 ((__v8sf *)__P, (__v8si)__M, (__v8sf)__A);
9533 extern __inline __m256 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
9534 Index: gcc/config/i386/i386.c
9535 ===================================================================
9536 --- gcc/config/i386/i386.c (.../tags/gcc_4_5_2_release) (wersja 170084)
9537 +++ gcc/config/i386/i386.c (.../branches/gcc-4_5-branch) (wersja 170084)
9538 @@ -10438,6 +10438,17 @@
9539 case TLS_MODEL_INITIAL_EXEC:
9542 + if (TARGET_SUN_TLS)
9544 + /* The Sun linker took the AMD64 TLS spec literally
9545 + and can only handle %rax as destination of the
9546 + initial executable code sequence. */
9548 + dest = gen_reg_rtx (Pmode);
9549 + emit_insn (gen_tls_initial_exec_64_sun (dest, x));
9554 type = UNSPEC_GOTNTPOFF;
9556 @@ -11027,7 +11038,11 @@
9558 x = XVECEXP (XEXP (x, 0), 0, 0);
9559 if (GET_MODE (orig_x) != Pmode)
9560 - return simplify_gen_subreg (GET_MODE (orig_x), x, Pmode, 0);
9562 + x = simplify_gen_subreg (GET_MODE (orig_x), x, Pmode, 0);
9563 + if (x == NULL_RTX)
9569 @@ -11096,7 +11111,11 @@
9572 if (GET_MODE (orig_x) != Pmode && MEM_P (orig_x))
9573 - return simplify_gen_subreg (GET_MODE (orig_x), result, Pmode, 0);
9575 + result = simplify_gen_subreg (GET_MODE (orig_x), result, Pmode, 0);
9576 + if (result == NULL_RTX)
9582 @@ -21638,14 +21657,14 @@
9583 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
9584 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
9586 - { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF },
9587 - { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF },
9588 - { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF },
9589 - { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF },
9590 - { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_V2DF },
9591 - { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_V4SF },
9592 - { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_V4DF },
9593 - { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_V8SF },
9594 + { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
9595 + { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
9596 + { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
9597 + { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
9598 + { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
9599 + { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
9600 + { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
9601 + { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
9603 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
9604 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
9605 @@ -23927,18 +23946,18 @@
9609 - case V8SF_FTYPE_PCV8SF_V8SF:
9610 - case V4DF_FTYPE_PCV4DF_V4DF:
9611 - case V4SF_FTYPE_PCV4SF_V4SF:
9612 - case V2DF_FTYPE_PCV2DF_V2DF:
9613 + case V8SF_FTYPE_PCV8SF_V8SI:
9614 + case V4DF_FTYPE_PCV4DF_V4DI:
9615 + case V4SF_FTYPE_PCV4SF_V4SI:
9616 + case V2DF_FTYPE_PCV2DF_V2DI:
9621 - case VOID_FTYPE_PV8SF_V8SF_V8SF:
9622 - case VOID_FTYPE_PV4DF_V4DF_V4DF:
9623 - case VOID_FTYPE_PV4SF_V4SF_V4SF:
9624 - case VOID_FTYPE_PV2DF_V2DF_V2DF:
9625 + case VOID_FTYPE_PV8SF_V8SI_V8SF:
9626 + case VOID_FTYPE_PV4DF_V4DI_V4DF:
9627 + case VOID_FTYPE_PV4SF_V4SI_V4SF:
9628 + case VOID_FTYPE_PV2DF_V2DI_V2DF:
9631 /* Reserve memory operand for target. */
9632 Index: gcc/config/rs6000/vector.md
9633 ===================================================================
9634 --- gcc/config/rs6000/vector.md (.../tags/gcc_4_5_2_release) (wersja 170084)
9635 +++ gcc/config/rs6000/vector.md (.../branches/gcc-4_5-branch) (wersja 170084)
9637 ;; expander, and the actual vector instructions will be in altivec.md and
9640 -;; Copyright (C) 2009, 2010
9641 +;; Copyright (C) 2009, 2010, 2011
9642 ;; Free Software Foundation, Inc.
9643 ;; Contributed by Michael Meissner <meissner@linux.vnet.ibm.com>
9645 @@ -123,6 +123,43 @@
9649 +;; Vector floating point load/store instructions that uses the Altivec
9650 +;; instructions even if we are compiling for VSX, since the Altivec
9651 +;; instructions silently ignore the bottom 3 bits of the address, and VSX does
9653 +(define_expand "vector_altivec_load_<mode>"
9654 + [(set (match_operand:VEC_M 0 "vfloat_operand" "")
9655 + (match_operand:VEC_M 1 "memory_operand" ""))]
9656 + "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
9659 + gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode));
9661 + if (VECTOR_MEM_VSX_P (<MODE>mode))
9663 + operands[1] = rs6000_address_for_altivec (operands[1]);
9664 + emit_insn (gen_altivec_lvx_<mode> (operands[0], operands[1]));
9669 +(define_expand "vector_altivec_store_<mode>"
9670 + [(set (match_operand:VEC_M 0 "memory_operand" "")
9671 + (match_operand:VEC_M 1 "vfloat_operand" ""))]
9672 + "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
9675 + gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode));
9677 + if (VECTOR_MEM_VSX_P (<MODE>mode))
9679 + operands[0] = rs6000_address_for_altivec (operands[0]);
9680 + emit_insn (gen_altivec_stvx_<mode> (operands[0], operands[1]));
9687 ;; Reload patterns for vector operations. We may need an addtional base
9688 ;; register to convert the reg+offset addressing to reg+reg for vector
9689 Index: gcc/config/rs6000/rs6000-protos.h
9690 ===================================================================
9691 --- gcc/config/rs6000/rs6000-protos.h (.../tags/gcc_4_5_2_release) (wersja 170084)
9692 +++ gcc/config/rs6000/rs6000-protos.h (.../branches/gcc-4_5-branch) (wersja 170084)
9694 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
9695 - Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
9696 + Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
9698 Free Software Foundation, Inc.
9699 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
9703 extern rtx rs6000_machopic_legitimize_pic_address (rtx, enum machine_mode,
9705 +extern rtx rs6000_address_for_altivec (rtx);
9706 #endif /* RTX_CODE */
9709 Index: gcc/config/rs6000/rs6000-builtin.def
9710 ===================================================================
9711 --- gcc/config/rs6000/rs6000-builtin.def (.../tags/gcc_4_5_2_release) (wersja 170084)
9712 +++ gcc/config/rs6000/rs6000-builtin.def (.../branches/gcc-4_5-branch) (wersja 170084)
9714 /* Builtin functions for rs6000/powerpc.
9715 - Copyright (C) 2009, 2010
9716 + Copyright (C) 2009, 2010, 2011
9717 Free Software Foundation, Inc.
9718 Contributed by Michael Meissner (meissner@linux.vnet.ibm.com)
9721 RS6000_BUILTIN(ALTIVEC_BUILTIN_LD_INTERNAL_16qi, RS6000_BTC_MEM)
9722 RS6000_BUILTIN(ALTIVEC_BUILTIN_ST_INTERNAL_4sf, RS6000_BTC_MEM)
9723 RS6000_BUILTIN(ALTIVEC_BUILTIN_LD_INTERNAL_4sf, RS6000_BTC_MEM)
9724 +RS6000_BUILTIN(ALTIVEC_BUILTIN_ST_INTERNAL_2df, RS6000_BTC_MEM)
9725 +RS6000_BUILTIN(ALTIVEC_BUILTIN_LD_INTERNAL_2df, RS6000_BTC_MEM)
9726 +RS6000_BUILTIN(ALTIVEC_BUILTIN_ST_INTERNAL_2di, RS6000_BTC_MEM)
9727 +RS6000_BUILTIN(ALTIVEC_BUILTIN_LD_INTERNAL_2di, RS6000_BTC_MEM)
9728 RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDUBM, RS6000_BTC_CONST)
9729 RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDUHM, RS6000_BTC_CONST)
9730 RS6000_BUILTIN(ALTIVEC_BUILTIN_VADDUWM, RS6000_BTC_CONST)
9731 @@ -774,12 +778,20 @@
9734 RS6000_BUILTIN(VSX_BUILTIN_LXSDX, RS6000_BTC_MEM)
9735 -RS6000_BUILTIN(VSX_BUILTIN_LXVD2X, RS6000_BTC_MEM)
9736 +RS6000_BUILTIN(VSX_BUILTIN_LXVD2X_V2DF, RS6000_BTC_MEM)
9737 +RS6000_BUILTIN(VSX_BUILTIN_LXVD2X_V2DI, RS6000_BTC_MEM)
9738 RS6000_BUILTIN(VSX_BUILTIN_LXVDSX, RS6000_BTC_MEM)
9739 -RS6000_BUILTIN(VSX_BUILTIN_LXVW4X, RS6000_BTC_MEM)
9740 +RS6000_BUILTIN(VSX_BUILTIN_LXVW4X_V4SF, RS6000_BTC_MEM)
9741 +RS6000_BUILTIN(VSX_BUILTIN_LXVW4X_V4SI, RS6000_BTC_MEM)
9742 +RS6000_BUILTIN(VSX_BUILTIN_LXVW4X_V8HI, RS6000_BTC_MEM)
9743 +RS6000_BUILTIN(VSX_BUILTIN_LXVW4X_V16QI, RS6000_BTC_MEM)
9744 RS6000_BUILTIN(VSX_BUILTIN_STXSDX, RS6000_BTC_MEM)
9745 -RS6000_BUILTIN(VSX_BUILTIN_STXVD2X, RS6000_BTC_MEM)
9746 -RS6000_BUILTIN(VSX_BUILTIN_STXVW4X, RS6000_BTC_MEM)
9747 +RS6000_BUILTIN(VSX_BUILTIN_STXVD2X_V2DF, RS6000_BTC_MEM)
9748 +RS6000_BUILTIN(VSX_BUILTIN_STXVD2X_V2DI, RS6000_BTC_MEM)
9749 +RS6000_BUILTIN(VSX_BUILTIN_STXVW4X_V4SF, RS6000_BTC_MEM)
9750 +RS6000_BUILTIN(VSX_BUILTIN_STXVW4X_V4SI, RS6000_BTC_MEM)
9751 +RS6000_BUILTIN(VSX_BUILTIN_STXVW4X_V8HI, RS6000_BTC_MEM)
9752 +RS6000_BUILTIN(VSX_BUILTIN_STXVW4X_V16QI, RS6000_BTC_MEM)
9753 RS6000_BUILTIN(VSX_BUILTIN_XSABSDP, RS6000_BTC_CONST)
9754 RS6000_BUILTIN(VSX_BUILTIN_XSADDDP, RS6000_BTC_FP_PURE)
9755 RS6000_BUILTIN(VSX_BUILTIN_XSCMPODP, RS6000_BTC_FP_PURE)
9756 @@ -975,8 +987,10 @@
9757 RS6000_BUILTIN(VSX_BUILTIN_VEC_XXSLDWI, RS6000_BTC_MISC)
9758 RS6000_BUILTIN(VSX_BUILTIN_VEC_XXSPLTD, RS6000_BTC_MISC)
9759 RS6000_BUILTIN(VSX_BUILTIN_VEC_XXSPLTW, RS6000_BTC_MISC)
9760 +RS6000_BUILTIN(VSX_BUILTIN_VEC_LD, RS6000_BTC_MISC)
9761 +RS6000_BUILTIN(VSX_BUILTIN_VEC_ST, RS6000_BTC_MISC)
9762 RS6000_BUILTIN_EQUATE(VSX_BUILTIN_OVERLOADED_LAST,
9763 - VSX_BUILTIN_VEC_XXSPLTW)
9764 + VSX_BUILTIN_VEC_ST)
9766 /* Combined VSX/Altivec builtins. */
9767 RS6000_BUILTIN(VECTOR_BUILTIN_FLOAT_V4SI_V4SF, RS6000_BTC_FP_PURE)
9768 Index: gcc/config/rs6000/rs6000-c.c
9769 ===================================================================
9770 --- gcc/config/rs6000/rs6000-c.c (.../tags/gcc_4_5_2_release) (wersja 170084)
9771 +++ gcc/config/rs6000/rs6000-c.c (.../branches/gcc-4_5-branch) (wersja 170084)
9772 @@ -965,6 +965,15 @@
9773 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP,
9774 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 },
9775 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
9776 + RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
9777 + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
9778 + RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
9779 + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
9780 + RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
9781 + ~RS6000_BTI_unsigned_V2DI, 0 },
9782 + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
9783 + RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
9784 + { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
9785 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
9786 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX,
9787 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
9788 @@ -1077,9 +1086,19 @@
9789 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
9790 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
9791 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
9792 - RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 },
9793 + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
9794 + ~RS6000_BTI_unsigned_V16QI, 0 },
9795 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
9796 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
9797 + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
9798 + RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
9799 + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
9800 + RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
9801 + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
9802 + RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
9803 + ~RS6000_BTI_unsigned_V2DI, 0 },
9804 + { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL,
9805 + RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
9806 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
9807 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
9808 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
9809 @@ -1098,6 +1117,17 @@
9810 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
9811 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
9812 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
9813 + { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
9814 + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
9815 + { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
9816 + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
9817 + { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
9818 + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
9819 + { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
9820 + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
9821 + { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL,
9822 + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
9823 + ~RS6000_BTI_unsigned_long_long, 0 },
9824 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
9825 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
9826 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
9827 @@ -1116,6 +1146,17 @@
9828 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
9829 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
9830 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
9831 + { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
9832 + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 },
9833 + { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
9834 + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 },
9835 + { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
9836 + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 },
9837 + { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
9838 + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 },
9839 + { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR,
9840 + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
9841 + ~RS6000_BTI_unsigned_long_long, 0 },
9842 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
9843 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
9844 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX,
9845 @@ -2609,6 +2650,16 @@
9846 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI,
9847 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_NOT_OPAQUE },
9848 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
9849 + RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
9850 + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
9851 + RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
9852 + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
9853 + RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
9854 + ~RS6000_BTI_unsigned_V2DI },
9855 + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
9856 + RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
9857 + ~RS6000_BTI_bool_V2DI },
9858 + { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
9859 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
9860 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX,
9861 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
9862 @@ -2774,6 +2825,18 @@
9863 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
9864 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
9865 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI },
9866 + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
9867 + RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
9868 + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
9869 + RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double },
9870 + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
9871 + RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
9872 + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
9873 + RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
9874 + ~RS6000_BTI_unsigned_V2DI },
9875 + { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL,
9876 + RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
9877 + ~RS6000_BTI_bool_V2DI },
9878 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
9879 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
9880 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX,
9881 @@ -2967,6 +3030,135 @@
9882 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
9883 RS6000_BTI_NOT_OPAQUE },
9885 + { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF,
9886 + RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 },
9887 + { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
9888 + RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 },
9889 + { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
9890 + RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
9891 + ~RS6000_BTI_unsigned_V2DI, 0 },
9892 + { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI,
9893 + RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 },
9894 + { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
9895 + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 },
9896 + { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF,
9897 + RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 },
9898 + { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
9899 + RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 },
9900 + { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
9901 + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 },
9902 + { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
9903 + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 },
9904 + { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
9905 + RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 },
9906 + { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
9907 + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
9908 + ~RS6000_BTI_unsigned_V4SI, 0 },
9909 + { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
9910 + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 },
9911 + { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI,
9912 + RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
9913 + ~RS6000_BTI_unsigned_long, 0 },
9914 + { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
9915 + RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 },
9916 + { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
9917 + RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 },
9918 + { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
9919 + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 },
9920 + { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
9921 + RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 },
9922 + { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
9923 + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
9924 + ~RS6000_BTI_unsigned_V8HI, 0 },
9925 + { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI,
9926 + RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 },
9927 + { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
9928 + RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 },
9929 + { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
9930 + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 },
9931 + { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
9932 + RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 },
9933 + { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
9934 + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
9935 + ~RS6000_BTI_unsigned_V16QI, 0 },
9936 + { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI,
9937 + RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 },
9939 + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF,
9940 + RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF },
9941 + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
9942 + RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI },
9943 + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
9944 + RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI,
9945 + ~RS6000_BTI_unsigned_V2DI },
9946 + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI,
9947 + RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI,
9948 + ~RS6000_BTI_bool_V2DI },
9949 + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF,
9950 + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF },
9951 + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF,
9952 + RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float },
9953 + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
9954 + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI },
9955 + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
9956 + RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI },
9957 + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
9958 + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
9959 + ~RS6000_BTI_unsigned_V4SI },
9960 + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
9961 + RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI,
9962 + ~RS6000_BTI_UINTSI },
9963 + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
9964 + RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
9965 + ~RS6000_BTI_bool_V4SI },
9966 + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
9967 + RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
9968 + ~RS6000_BTI_UINTSI },
9969 + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI,
9970 + RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI,
9971 + ~RS6000_BTI_INTSI },
9972 + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
9973 + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI },
9974 + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
9975 + RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI },
9976 + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
9977 + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
9978 + ~RS6000_BTI_unsigned_V8HI },
9979 + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
9980 + RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI,
9981 + ~RS6000_BTI_UINTHI },
9982 + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
9983 + RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
9984 + ~RS6000_BTI_bool_V8HI },
9985 + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
9986 + RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
9987 + ~RS6000_BTI_UINTHI },
9988 + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI,
9989 + RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI,
9990 + ~RS6000_BTI_INTHI },
9991 + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
9992 + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI },
9993 + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
9994 + RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI },
9995 + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
9996 + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
9997 + ~RS6000_BTI_unsigned_V16QI },
9998 + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
9999 + RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI,
10000 + ~RS6000_BTI_UINTQI },
10001 + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
10002 + RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
10003 + ~RS6000_BTI_bool_V16QI },
10004 + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
10005 + RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
10006 + ~RS6000_BTI_UINTQI },
10007 + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
10008 + RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI,
10009 + ~RS6000_BTI_INTQI },
10010 + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI,
10011 + RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI,
10012 + ~RS6000_BTI_pixel_V8HI },
10015 { ALTIVEC_BUILTIN_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P,
10016 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI },
10017 Index: gcc/config/rs6000/rs6000.c
10018 ===================================================================
10019 --- gcc/config/rs6000/rs6000.c (.../tags/gcc_4_5_2_release) (wersja 170084)
10020 +++ gcc/config/rs6000/rs6000.c (.../branches/gcc-4_5-branch) (wersja 170084)
10021 @@ -2865,9 +2865,12 @@
10022 /* If not explicitly specified via option, decide whether to generate indexed
10023 load/store instructions. */
10024 if (TARGET_AVOID_XFORM == -1)
10025 - /* Avoid indexed addressing when targeting Power6 in order to avoid
10026 - the DERAT mispredict penalty. */
10027 - TARGET_AVOID_XFORM = (rs6000_cpu == PROCESSOR_POWER6 && TARGET_CMPB);
10028 + /* Avoid indexed addressing when targeting Power6 in order to avoid the
10029 + DERAT mispredict penalty. However the LVE and STVE altivec instructions
10030 + need indexed accesses and the type used is the scalar type of the element
10031 + being loaded or stored. */
10032 + TARGET_AVOID_XFORM = (rs6000_cpu == PROCESSOR_POWER6 && TARGET_CMPB
10033 + && !TARGET_ALTIVEC);
10035 rs6000_init_hard_regno_mode_ok ();
10037 @@ -4472,7 +4475,7 @@
10039 enum machine_mode mode = GET_MODE (vec);
10040 enum machine_mode inner_mode = GET_MODE_INNER (mode);
10044 if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
10046 @@ -4485,17 +4488,11 @@
10047 /* Allocate mode-sized buffer. */
10048 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
10050 + emit_move_insn (mem, vec);
10052 /* Add offset to field within buffer matching vector element. */
10053 - mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));
10054 + mem = adjust_address_nv (mem, inner_mode, elt * GET_MODE_SIZE (inner_mode));
10056 - /* Store single field into mode-sized buffer. */
10057 - x = gen_rtx_UNSPEC (VOIDmode,
10058 - gen_rtvec (1, const0_rtx), UNSPEC_STVE);
10059 - emit_insn (gen_rtx_PARALLEL (VOIDmode,
10061 - gen_rtx_SET (VOIDmode,
10064 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
10067 @@ -9897,6 +9894,7 @@
10068 rtx op2 = expand_normal (arg2);
10070 enum machine_mode tmode = insn_data[icode].operand[0].mode;
10071 + enum machine_mode smode = insn_data[icode].operand[1].mode;
10072 enum machine_mode mode1 = Pmode;
10073 enum machine_mode mode2 = Pmode;
10075 @@ -9906,8 +9904,8 @@
10076 || arg2 == error_mark_node)
10079 - if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
10080 - op0 = copy_to_mode_reg (tmode, op0);
10081 + if (! (*insn_data[icode].operand[1].predicate) (op0, smode))
10082 + op0 = copy_to_mode_reg (smode, op0);
10084 op2 = copy_to_mode_reg (mode2, op2);
10086 @@ -10041,17 +10039,23 @@
10089 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
10090 - icode = CODE_FOR_vector_load_v16qi;
10091 + icode = CODE_FOR_vector_altivec_load_v16qi;
10093 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
10094 - icode = CODE_FOR_vector_load_v8hi;
10095 + icode = CODE_FOR_vector_altivec_load_v8hi;
10097 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
10098 - icode = CODE_FOR_vector_load_v4si;
10099 + icode = CODE_FOR_vector_altivec_load_v4si;
10101 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
10102 - icode = CODE_FOR_vector_load_v4sf;
10103 + icode = CODE_FOR_vector_altivec_load_v4sf;
10105 + case ALTIVEC_BUILTIN_LD_INTERNAL_2df:
10106 + icode = CODE_FOR_vector_altivec_load_v2df;
10108 + case ALTIVEC_BUILTIN_LD_INTERNAL_2di:
10109 + icode = CODE_FOR_vector_altivec_load_v2di;
10112 *expandedp = false;
10114 @@ -10094,17 +10098,23 @@
10117 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
10118 - icode = CODE_FOR_vector_store_v16qi;
10119 + icode = CODE_FOR_vector_altivec_store_v16qi;
10121 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
10122 - icode = CODE_FOR_vector_store_v8hi;
10123 + icode = CODE_FOR_vector_altivec_store_v8hi;
10125 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
10126 - icode = CODE_FOR_vector_store_v4si;
10127 + icode = CODE_FOR_vector_altivec_store_v4si;
10129 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
10130 - icode = CODE_FOR_vector_store_v4sf;
10131 + icode = CODE_FOR_vector_altivec_store_v4sf;
10133 + case ALTIVEC_BUILTIN_ST_INTERNAL_2df:
10134 + icode = CODE_FOR_vector_altivec_store_v2df;
10136 + case ALTIVEC_BUILTIN_ST_INTERNAL_2di:
10137 + icode = CODE_FOR_vector_altivec_store_v2di;
10140 *expandedp = false;
10142 @@ -10336,7 +10346,7 @@
10145 case ALTIVEC_BUILTIN_STVX:
10146 - return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, exp);
10147 + return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si, exp);
10148 case ALTIVEC_BUILTIN_STVEBX:
10149 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
10150 case ALTIVEC_BUILTIN_STVEHX:
10151 @@ -10355,6 +10365,19 @@
10152 case ALTIVEC_BUILTIN_STVRXL:
10153 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
10155 + case VSX_BUILTIN_STXVD2X_V2DF:
10156 + return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp);
10157 + case VSX_BUILTIN_STXVD2X_V2DI:
10158 + return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di, exp);
10159 + case VSX_BUILTIN_STXVW4X_V4SF:
10160 + return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf, exp);
10161 + case VSX_BUILTIN_STXVW4X_V4SI:
10162 + return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si, exp);
10163 + case VSX_BUILTIN_STXVW4X_V8HI:
10164 + return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi, exp);
10165 + case VSX_BUILTIN_STXVW4X_V16QI:
10166 + return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp);
10168 case ALTIVEC_BUILTIN_MFVSCR:
10169 icode = CODE_FOR_altivec_mfvscr;
10170 tmode = insn_data[icode].operand[0].mode;
10171 @@ -10479,7 +10502,7 @@
10172 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
10173 exp, target, false);
10174 case ALTIVEC_BUILTIN_LVX:
10175 - return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
10176 + return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si,
10177 exp, target, false);
10178 case ALTIVEC_BUILTIN_LVLX:
10179 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
10180 @@ -10493,6 +10516,25 @@
10181 case ALTIVEC_BUILTIN_LVRXL:
10182 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,
10183 exp, target, true);
10184 + case VSX_BUILTIN_LXVD2X_V2DF:
10185 + return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df,
10186 + exp, target, false);
10187 + case VSX_BUILTIN_LXVD2X_V2DI:
10188 + return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di,
10189 + exp, target, false);
10190 + case VSX_BUILTIN_LXVW4X_V4SF:
10191 + return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf,
10192 + exp, target, false);
10193 + case VSX_BUILTIN_LXVW4X_V4SI:
10194 + return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si,
10195 + exp, target, false);
10196 + case VSX_BUILTIN_LXVW4X_V8HI:
10197 + return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi,
10198 + exp, target, false);
10199 + case VSX_BUILTIN_LXVW4X_V16QI:
10200 + return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi,
10201 + exp, target, false);
10205 /* Fall through. */
10206 @@ -11099,6 +11141,8 @@
10208 long_integer_type_internal_node = long_integer_type_node;
10209 long_unsigned_type_internal_node = long_unsigned_type_node;
10210 + long_long_integer_type_internal_node = long_long_integer_type_node;
10211 + long_long_unsigned_type_internal_node = long_long_unsigned_type_node;
10212 intQI_type_internal_node = intQI_type_node;
10213 uintQI_type_internal_node = unsigned_intQI_type_node;
10214 intHI_type_internal_node = intHI_type_node;
10215 @@ -11108,7 +11152,7 @@
10216 intDI_type_internal_node = intDI_type_node;
10217 uintDI_type_internal_node = unsigned_intDI_type_node;
10218 float_type_internal_node = float_type_node;
10219 - double_type_internal_node = float_type_node;
10220 + double_type_internal_node = double_type_node;
10221 void_type_internal_node = void_type_node;
10223 /* Initialize the modes for builtin_function_type, mapping a machine mode to
10224 @@ -11631,20 +11675,12 @@
10228 - tree pfloat_type_node = build_pointer_type (float_type_node);
10229 - tree pint_type_node = build_pointer_type (integer_type_node);
10230 - tree pshort_type_node = build_pointer_type (short_integer_type_node);
10231 - tree pchar_type_node = build_pointer_type (char_type_node);
10233 tree pvoid_type_node = build_pointer_type (void_type_node);
10235 - tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
10236 - tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
10237 - tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
10238 - tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
10239 + tree pcvoid_type_node
10240 + = build_pointer_type (build_qualified_type (void_type_node,
10241 + TYPE_QUAL_CONST));
10243 - tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
10245 tree int_ftype_opaque
10246 = build_function_type_list (integer_type_node,
10247 opaque_V4SI_type_node, NULL_TREE);
10248 @@ -11666,26 +11702,6 @@
10249 = build_function_type_list (integer_type_node,
10250 integer_type_node, V4SI_type_node,
10251 V4SI_type_node, NULL_TREE);
10252 - tree v4sf_ftype_pcfloat
10253 - = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
10254 - tree void_ftype_pfloat_v4sf
10255 - = build_function_type_list (void_type_node,
10256 - pfloat_type_node, V4SF_type_node, NULL_TREE);
10257 - tree v4si_ftype_pcint
10258 - = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
10259 - tree void_ftype_pint_v4si
10260 - = build_function_type_list (void_type_node,
10261 - pint_type_node, V4SI_type_node, NULL_TREE);
10262 - tree v8hi_ftype_pcshort
10263 - = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
10264 - tree void_ftype_pshort_v8hi
10265 - = build_function_type_list (void_type_node,
10266 - pshort_type_node, V8HI_type_node, NULL_TREE);
10267 - tree v16qi_ftype_pcchar
10268 - = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
10269 - tree void_ftype_pchar_v16qi
10270 - = build_function_type_list (void_type_node,
10271 - pchar_type_node, V16QI_type_node, NULL_TREE);
10272 tree void_ftype_v4si
10273 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
10274 tree v8hi_ftype_void
10275 @@ -11697,16 +11713,32 @@
10277 tree opaque_ftype_long_pcvoid
10278 = build_function_type_list (opaque_V4SI_type_node,
10279 - long_integer_type_node, pcvoid_type_node, NULL_TREE);
10280 + long_integer_type_node, pcvoid_type_node,
10282 tree v16qi_ftype_long_pcvoid
10283 = build_function_type_list (V16QI_type_node,
10284 - long_integer_type_node, pcvoid_type_node, NULL_TREE);
10285 + long_integer_type_node, pcvoid_type_node,
10287 tree v8hi_ftype_long_pcvoid
10288 = build_function_type_list (V8HI_type_node,
10289 - long_integer_type_node, pcvoid_type_node, NULL_TREE);
10290 + long_integer_type_node, pcvoid_type_node,
10292 tree v4si_ftype_long_pcvoid
10293 = build_function_type_list (V4SI_type_node,
10294 - long_integer_type_node, pcvoid_type_node, NULL_TREE);
10295 + long_integer_type_node, pcvoid_type_node,
10297 + tree v4sf_ftype_long_pcvoid
10298 + = build_function_type_list (V4SF_type_node,
10299 + long_integer_type_node, pcvoid_type_node,
10301 + tree v2df_ftype_long_pcvoid
10302 + = build_function_type_list (V2DF_type_node,
10303 + long_integer_type_node, pcvoid_type_node,
10305 + tree v2di_ftype_long_pcvoid
10306 + = build_function_type_list (V2DI_type_node,
10307 + long_integer_type_node, pcvoid_type_node,
10310 tree void_ftype_opaque_long_pvoid
10311 = build_function_type_list (void_type_node,
10312 @@ -11724,6 +11756,18 @@
10313 = build_function_type_list (void_type_node,
10314 V8HI_type_node, long_integer_type_node,
10315 pvoid_type_node, NULL_TREE);
10316 + tree void_ftype_v4sf_long_pvoid
10317 + = build_function_type_list (void_type_node,
10318 + V4SF_type_node, long_integer_type_node,
10319 + pvoid_type_node, NULL_TREE);
10320 + tree void_ftype_v2df_long_pvoid
10321 + = build_function_type_list (void_type_node,
10322 + V2DF_type_node, long_integer_type_node,
10323 + pvoid_type_node, NULL_TREE);
10324 + tree void_ftype_v2di_long_pvoid
10325 + = build_function_type_list (void_type_node,
10326 + V2DI_type_node, long_integer_type_node,
10327 + pvoid_type_node, NULL_TREE);
10328 tree int_ftype_int_v8hi_v8hi
10329 = build_function_type_list (integer_type_node,
10330 integer_type_node, V8HI_type_node,
10331 @@ -11755,22 +11799,6 @@
10332 pcvoid_type_node, integer_type_node,
10333 integer_type_node, NULL_TREE);
10335 - def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
10336 - ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
10337 - def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
10338 - ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
10339 - def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
10340 - ALTIVEC_BUILTIN_LD_INTERNAL_4si);
10341 - def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
10342 - ALTIVEC_BUILTIN_ST_INTERNAL_4si);
10343 - def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
10344 - ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
10345 - def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
10346 - ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
10347 - def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
10348 - ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
10349 - def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
10350 - ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
10351 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
10352 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
10353 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
10354 @@ -11802,6 +11830,35 @@
10355 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
10356 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
10358 + def_builtin (MASK_VSX, "__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid,
10359 + VSX_BUILTIN_LXVD2X_V2DF);
10360 + def_builtin (MASK_VSX, "__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid,
10361 + VSX_BUILTIN_LXVD2X_V2DI);
10362 + def_builtin (MASK_VSX, "__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid,
10363 + VSX_BUILTIN_LXVW4X_V4SF);
10364 + def_builtin (MASK_VSX, "__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid,
10365 + VSX_BUILTIN_LXVW4X_V4SI);
10366 + def_builtin (MASK_VSX, "__builtin_vsx_lxvw4x_v8hi",
10367 + v8hi_ftype_long_pcvoid, VSX_BUILTIN_LXVW4X_V8HI);
10368 + def_builtin (MASK_VSX, "__builtin_vsx_lxvw4x_v16qi",
10369 + v16qi_ftype_long_pcvoid, VSX_BUILTIN_LXVW4X_V16QI);
10370 + def_builtin (MASK_VSX, "__builtin_vsx_stxvd2x_v2df",
10371 + void_ftype_v2df_long_pvoid, VSX_BUILTIN_STXVD2X_V2DF);
10372 + def_builtin (MASK_VSX, "__builtin_vsx_stxvd2x_v2di",
10373 + void_ftype_v2di_long_pvoid, VSX_BUILTIN_STXVD2X_V2DI);
10374 + def_builtin (MASK_VSX, "__builtin_vsx_stxvw4x_v4sf",
10375 + void_ftype_v4sf_long_pvoid, VSX_BUILTIN_STXVW4X_V4SF);
10376 + def_builtin (MASK_VSX, "__builtin_vsx_stxvw4x_v4si",
10377 + void_ftype_v4si_long_pvoid, VSX_BUILTIN_STXVW4X_V4SI);
10378 + def_builtin (MASK_VSX, "__builtin_vsx_stxvw4x_v8hi",
10379 + void_ftype_v8hi_long_pvoid, VSX_BUILTIN_STXVW4X_V8HI);
10380 + def_builtin (MASK_VSX, "__builtin_vsx_stxvw4x_v16qi",
10381 + void_ftype_v16qi_long_pvoid, VSX_BUILTIN_STXVW4X_V16QI);
10382 + def_builtin (MASK_VSX, "__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
10383 + VSX_BUILTIN_VEC_LD);
10384 + def_builtin (MASK_VSX, "__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid,
10385 + VSX_BUILTIN_VEC_ST);
10387 if (rs6000_cpu == PROCESSOR_CELL)
10389 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
10390 @@ -25811,4 +25868,29 @@
10394 +/* Given a memory reference, if it is not in the form for altivec memory
10395 + reference instructions (i.e. reg or reg+reg addressing with AND of -16),
10396 + convert to the altivec format. */
10399 +rs6000_address_for_altivec (rtx x)
10401 + gcc_assert (MEM_P (x));
10402 + if (!altivec_indexed_or_indirect_operand (x, GET_MODE (x)))
10404 + rtx addr = XEXP (x, 0);
10405 + int strict_p = (reload_in_progress || reload_completed);
10407 + if (!legitimate_indexed_address_p (addr, strict_p)
10408 + && !legitimate_indirect_address_p (addr, strict_p))
10409 + addr = copy_to_mode_reg (Pmode, addr);
10411 + addr = gen_rtx_AND (Pmode, addr, GEN_INT (-16));
10412 + x = change_address (x, GET_MODE (x), addr);
10419 #include "gt-rs6000.h"
10420 Index: gcc/config/rs6000/vsx.md
10421 ===================================================================
10422 --- gcc/config/rs6000/vsx.md (.../tags/gcc_4_5_2_release) (wersja 170084)
10423 +++ gcc/config/rs6000/vsx.md (.../branches/gcc-4_5-branch) (wersja 170084)
10426 -;; Copyright (C) 2009
10427 +;; Copyright (C) 2009, 2010, 2011
10428 ;; Free Software Foundation, Inc.
10429 ;; Contributed by Michael Meissner <meissner@linux.vnet.ibm.com>
10431 @@ -309,6 +309,19 @@
10433 [(set_attr "type" "vecstore,vecload,vecsimple,*,*,*,vecsimple,*,vecstore,vecload")])
10435 +;; Explicit load/store expanders for the builtin functions
10436 +(define_expand "vsx_load_<mode>"
10437 + [(set (match_operand:VSX_M 0 "vsx_register_operand" "")
10438 + (match_operand:VSX_M 1 "memory_operand" ""))]
10439 + "VECTOR_MEM_VSX_P (<MODE>mode)"
10442 +(define_expand "vsx_store_<mode>"
10443 + [(set (match_operand:VEC_M 0 "memory_operand" "")
10444 + (match_operand:VEC_M 1 "vsx_register_operand" ""))]
10445 + "VECTOR_MEM_VSX_P (<MODE>mode)"
10449 ;; VSX scalar and vector floating point arithmetic instructions
10450 (define_insn "*vsx_add<mode>3"
10451 @@ -866,33 +879,34 @@
10452 ;; the fprs because we don't want to add the altivec registers to movdi/movsi.
10453 ;; For the unsigned tests, there isn't a generic double -> unsigned conversion
10454 ;; in rs6000.md so don't test VECTOR_UNIT_VSX_P, just test against VSX.
10455 +;; Don't use vsx_register_operand here, use gpc_reg_operand to match rs6000.md.
10456 (define_insn "vsx_float<VSi><mode>2"
10457 - [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")
10458 - (float:VSX_B (match_operand:<VSI> 1 "vsx_register_operand" "<VSr2>,<VSr3>")))]
10459 + [(set (match_operand:VSX_B 0 "gpc_reg_operand" "=<VSr>,?wa")
10460 + (float:VSX_B (match_operand:<VSI> 1 "gpc_reg_operand" "<VSr2>,<VSr3>")))]
10461 "VECTOR_UNIT_VSX_P (<MODE>mode)"
10462 "x<VSv>cvsx<VSc><VSs> %x0,%x1"
10463 [(set_attr "type" "<VStype_simple>")
10464 (set_attr "fp_type" "<VSfptype_simple>")])
10466 (define_insn "vsx_floatuns<VSi><mode>2"
10467 - [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")
10468 - (unsigned_float:VSX_B (match_operand:<VSI> 1 "vsx_register_operand" "<VSr2>,<VSr3>")))]
10469 + [(set (match_operand:VSX_B 0 "gpc_reg_operand" "=<VSr>,?wa")
10470 + (unsigned_float:VSX_B (match_operand:<VSI> 1 "gpc_reg_operand" "<VSr2>,<VSr3>")))]
10471 "VECTOR_UNIT_VSX_P (<MODE>mode)"
10472 "x<VSv>cvux<VSc><VSs> %x0,%x1"
10473 [(set_attr "type" "<VStype_simple>")
10474 (set_attr "fp_type" "<VSfptype_simple>")])
10476 (define_insn "vsx_fix_trunc<mode><VSi>2"
10477 - [(set (match_operand:<VSI> 0 "vsx_register_operand" "=<VSr2>,?<VSr3>")
10478 - (fix:<VSI> (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")))]
10479 + [(set (match_operand:<VSI> 0 "gpc_reg_operand" "=<VSr2>,?<VSr3>")
10480 + (fix:<VSI> (match_operand:VSX_B 1 "gpc_reg_operand" "<VSr>,wa")))]
10481 "VECTOR_UNIT_VSX_P (<MODE>mode)"
10482 "x<VSv>cv<VSs>sx<VSc>s %x0,%x1"
10483 [(set_attr "type" "<VStype_simple>")
10484 (set_attr "fp_type" "<VSfptype_simple>")])
10486 (define_insn "vsx_fixuns_trunc<mode><VSi>2"
10487 - [(set (match_operand:<VSI> 0 "vsx_register_operand" "=<VSr2>,?<VSr3>")
10488 - (unsigned_fix:<VSI> (match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")))]
10489 + [(set (match_operand:<VSI> 0 "gpc_reg_operand" "=<VSr2>,?<VSr3>")
10490 + (unsigned_fix:<VSI> (match_operand:VSX_B 1 "gpc_reg_operand" "<VSr>,wa")))]
10491 "VECTOR_UNIT_VSX_P (<MODE>mode)"
10492 "x<VSv>cv<VSs>ux<VSc>s %x0,%x1"
10493 [(set_attr "type" "<VStype_simple>")
10494 Index: gcc/config/rs6000/rs6000.h
10495 ===================================================================
10496 --- gcc/config/rs6000/rs6000.h (.../tags/gcc_4_5_2_release) (wersja 170084)
10497 +++ gcc/config/rs6000/rs6000.h (.../branches/gcc-4_5-branch) (wersja 170084)
10499 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
10500 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
10501 - 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
10502 + 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
10504 Free Software Foundation, Inc.
10505 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
10507 @@ -2489,6 +2490,8 @@
10508 RS6000_BTI_pixel_V8HI, /* __vector __pixel */
10509 RS6000_BTI_long, /* long_integer_type_node */
10510 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */
10511 + RS6000_BTI_long_long, /* long_long_integer_type_node */
10512 + RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */
10513 RS6000_BTI_INTQI, /* intQI_type_node */
10514 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */
10515 RS6000_BTI_INTHI, /* intHI_type_node */
10516 @@ -2532,6 +2535,8 @@
10517 #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI])
10518 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
10520 +#define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long])
10521 +#define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long])
10522 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
10523 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
10524 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI])
10525 Index: gcc/config/rs6000/altivec.md
10526 ===================================================================
10527 --- gcc/config/rs6000/altivec.md (.../tags/gcc_4_5_2_release) (wersja 170084)
10528 +++ gcc/config/rs6000/altivec.md (.../branches/gcc-4_5-branch) (wersja 170084)
10530 ;; AltiVec patterns.
10531 -;; Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
10532 +;; Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
10533 ;; Free Software Foundation, Inc.
10534 ;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
10538 (UNSPEC_SET_VSCR 213)
10539 (UNSPEC_GET_VRSAVE 214)
10542 (UNSPEC_REDUC_PLUS 217)
10544 (UNSPEC_EXTEVEN_V4SI 220)
10545 @@ -171,6 +171,7 @@
10546 (define_mode_iterator VM2 [V4SI V8HI V16QI V4SF V2DF V2DI])
10548 (define_mode_attr VI_char [(V4SI "w") (V8HI "h") (V16QI "b")])
10549 +(define_mode_attr VI_scalar [(V4SI "SI") (V8HI "HI") (V16QI "QI")])
10551 ;; Vector move instructions.
10552 (define_insn "*altivec_mov<mode>"
10553 @@ -1751,17 +1752,19 @@
10555 [(set_attr "type" "vecload")])
10557 -(define_insn "altivec_lvx"
10558 - [(set (match_operand:V4SI 0 "register_operand" "=v")
10559 - (match_operand:V4SI 1 "memory_operand" "Z"))]
10560 +(define_insn "altivec_lvx_<mode>"
10562 + [(set (match_operand:VM2 0 "register_operand" "=v")
10563 + (match_operand:VM2 1 "memory_operand" "Z"))
10564 + (unspec [(const_int 0)] UNSPEC_LVX)])]
10567 [(set_attr "type" "vecload")])
10569 -(define_insn "altivec_stvx"
10570 +(define_insn "altivec_stvx_<mode>"
10572 - [(set (match_operand:V4SI 0 "memory_operand" "=Z")
10573 - (match_operand:V4SI 1 "register_operand" "v"))
10574 + [(set (match_operand:VM2 0 "memory_operand" "=Z")
10575 + (match_operand:VM2 1 "register_operand" "v"))
10576 (unspec [(const_int 0)] UNSPEC_STVX)])]
10579 @@ -1777,19 +1780,15 @@
10580 [(set_attr "type" "vecstore")])
10582 (define_insn "altivec_stve<VI_char>x"
10584 - [(set (match_operand:VI 0 "memory_operand" "=Z")
10585 - (match_operand:VI 1 "register_operand" "v"))
10586 - (unspec [(const_int 0)] UNSPEC_STVE)])]
10587 + [(set (match_operand:<VI_scalar> 0 "memory_operand" "=Z")
10588 + (unspec:<VI_scalar> [(match_operand:VI 1 "register_operand" "v")] UNSPEC_STVE))]
10590 "stve<VI_char>x %1,%y0"
10591 [(set_attr "type" "vecstore")])
10593 (define_insn "*altivec_stvesfx"
10595 - [(set (match_operand:V4SF 0 "memory_operand" "=Z")
10596 - (match_operand:V4SF 1 "register_operand" "v"))
10597 - (unspec [(const_int 0)] UNSPEC_STVE)])]
10598 + [(set (match_operand:SF 0 "memory_operand" "=Z")
10599 + (unspec:SF [(match_operand:V4SF 1 "register_operand" "v")] UNSPEC_STVE))]
10602 [(set_attr "type" "vecstore")])
10603 Index: gcc/config/rs6000/altivec.h
10604 ===================================================================
10605 --- gcc/config/rs6000/altivec.h (.../tags/gcc_4_5_2_release) (wersja 170084)
10606 +++ gcc/config/rs6000/altivec.h (.../branches/gcc-4_5-branch) (wersja 170084)
10608 /* PowerPC AltiVec include file.
10609 - Copyright (C) 2002, 2003, 2004, 2005, 2008, 2009 Free Software Foundation, Inc.
10610 + Copyright (C) 2002, 2003, 2004, 2005, 2008, 2009, 2010, 2011
10611 + Free Software Foundation, Inc.
10612 Contributed by Aldy Hernandez (aldyh@redhat.com).
10613 Rewritten by Paolo Bonzini (bonzini@gnu.org).
10615 @@ -315,6 +316,8 @@
10616 #define vec_nearbyint __builtin_vec_nearbyint
10617 #define vec_rint __builtin_vec_rint
10618 #define vec_sqrt __builtin_vec_sqrt
10619 +#define vec_vsx_ld __builtin_vec_vsx_ld
10620 +#define vec_vsx_st __builtin_vec_vsx_st
10624 Index: gcc/config/arm/arm.c
10625 ===================================================================
10626 --- gcc/config/arm/arm.c (.../tags/gcc_4_5_2_release) (wersja 170084)
10627 +++ gcc/config/arm/arm.c (.../branches/gcc-4_5-branch) (wersja 170084)
10628 @@ -1114,6 +1114,7 @@
10630 DECL_ARTIFICIAL (va_list_name) = 1;
10631 TYPE_NAME (va_list_type) = va_list_name;
10632 + TYPE_STUB_DECL (va_list_type) = va_list_name;
10633 /* Create the __ap field. */
10634 ap_field = build_decl (BUILTINS_LOCATION,
10636 Index: gcc/config/arm/arm.md
10637 ===================================================================
10638 --- gcc/config/arm/arm.md (.../tags/gcc_4_5_2_release) (wersja 170084)
10639 +++ gcc/config/arm/arm.md (.../branches/gcc-4_5-branch) (wersja 170084)
10640 @@ -11273,34 +11273,29 @@
10641 (define_expand "bswapsi2"
10642 [(set (match_operand:SI 0 "s_register_operand" "=r")
10643 (bswap:SI (match_operand:SI 1 "s_register_operand" "r")))]
10645 +"TARGET_EITHER && (arm_arch6 || !optimize_size)"
10649 - if (!optimize_size)
10651 - rtx op2 = gen_reg_rtx (SImode);
10652 - rtx op3 = gen_reg_rtx (SImode);
10655 + rtx op2 = gen_reg_rtx (SImode);
10656 + rtx op3 = gen_reg_rtx (SImode);
10658 - if (TARGET_THUMB)
10660 - rtx op4 = gen_reg_rtx (SImode);
10661 - rtx op5 = gen_reg_rtx (SImode);
10662 + if (TARGET_THUMB)
10664 + rtx op4 = gen_reg_rtx (SImode);
10665 + rtx op5 = gen_reg_rtx (SImode);
10667 - emit_insn (gen_thumb_legacy_rev (operands[0], operands[1],
10668 - op2, op3, op4, op5));
10672 - emit_insn (gen_arm_legacy_rev (operands[0], operands[1],
10675 + emit_insn (gen_thumb_legacy_rev (operands[0], operands[1],
10676 + op2, op3, op4, op5));
10680 + emit_insn (gen_arm_legacy_rev (operands[0], operands[1],
10694 Index: gcc/config/pa/pa64-hpux.h
10695 ===================================================================
10696 --- gcc/config/pa/pa64-hpux.h (.../tags/gcc_4_5_2_release) (wersja 170084)
10697 +++ gcc/config/pa/pa64-hpux.h (.../branches/gcc-4_5-branch) (wersja 170084)
10699 /* Definitions of target machine for GNU compiler, for HPs running
10700 HPUX using the 64bit runtime model.
10701 - Copyright (C) 1999, 2000, 2001, 2002, 2004, 2005, 2007, 2008
10702 + Copyright (C) 1999, 2000, 2001, 2002, 2004, 2005, 2007, 2008, 2011
10703 Free Software Foundation, Inc.
10705 This file is part of GCC.
10706 @@ -59,36 +59,42 @@
10707 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_GNU_LD)
10710 - %{!p:%{!pg:%{static|mt|pthread:%{fopenmp:%{static:-a shared} -lrt\
10711 - %{static:-a archive}} -lpthread} -lc\
10712 - %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}}\
10713 + %{!p:%{!pg:%{fopenmp:%{static:-a shared} -lrt %{static:-a archive}}\
10714 + %{mt|pthread:-lpthread} -lc\
10715 + %{static:%{!nolibdld:-a shared -ldld -a archive -lc}\
10716 + %{!mt:%{!pthread:-a shared -lc -a archive}}}}}\
10717 %{p:%{!pg:%{static:%{!mhp-ld:-a shared}%{mhp-ld:-a archive_shared}}\
10718 -lprof %{static:-a archive}\
10719 - %{static|mt|pthread:%{fopenmp:%{static:-a shared} -lrt\
10720 - %{static:-a archive}} -lpthread} -lc\
10721 - %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}}\
10722 + %{fopenmp:%{static:-a shared} -lrt %{static:-a archive}}\
10723 + %{mt|pthread:-lpthread} -lc\
10724 + %{static:%{!nolibdld:-a shared -ldld -a archive -lc}\
10725 + %{!mt:%{!pthread:-a shared -lc -a archive}}}}}\
10726 %{pg:%{static:%{!mhp-ld:-a shared}%{mhp-ld:-a archive_shared}}\
10727 -lgprof %{static:-a archive}\
10728 - %{static|mt|pthread:%{fopenmp:%{static:-a shared} -lrt\
10729 - %{static:-a archive}} -lpthread} -lc\
10730 - %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}}\
10731 + %{fopenmp:%{static:-a shared} -lrt %{static:-a archive}}\
10732 + %{mt|pthread:-lpthread} -lc\
10733 + %{static:%{!nolibdld:-a shared -ldld -a archive -lc}\
10734 + %{!mt:%{!pthread:-a shared -lc -a archive}}}}}\
10735 %{shared:%{mt|pthread:-lpthread}}"
10739 - %{!p:%{!pg:%{static|mt|pthread:%{fopenmp:%{static:-a shared} -lrt\
10740 - %{static:-a archive}} -lpthread} -lc\
10741 - %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}}\
10742 + %{!p:%{!pg:%{fopenmp:%{static:-a shared} -lrt %{static:-a archive}}\
10743 + %{mt|pthread:-lpthread} -lc\
10744 + %{static:%{!nolibdld:-a shared -ldld -a archive -lc}\
10745 + %{!mt:%{!pthread:-a shared -lc -a archive}}}}}\
10746 %{p:%{!pg:%{static:%{mgnu-ld:-a shared}%{!mgnu-ld:-a archive_shared}}\
10747 -lprof %{static:-a archive}\
10748 - %{static|mt|pthread:%{fopenmp:%{static:-a shared} -lrt\
10749 - %{static:-a archive}} -lpthread} -lc\
10750 - %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}}\
10751 + %{fopenmp:%{static:-a shared} -lrt %{static:-a archive}}\
10752 + %{mt|pthread:-lpthread} -lc\
10753 + %{static:%{!nolibdld:-a shared -ldld -a archive -lc}\
10754 + %{!mt:%{!pthread:-a shared -lc -a archive}}}}}\
10755 %{pg:%{static:%{mgnu-ld:-a shared}%{!mgnu-ld:-a archive_shared}}\
10756 -lgprof %{static:-a archive}\
10757 - %{static|mt|pthread:%{fopenmp:%{static:-a shared} -lrt\
10758 - %{static:-a archive}} -lpthread} -lc\
10759 - %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}}\
10760 + %{fopenmp:%{static:-a shared} -lrt %{static:-a archive}}\
10761 + %{mt|pthread:-lpthread} -lc\
10762 + %{static:%{!nolibdld:-a shared -ldld -a archive -lc}\
10763 + %{!mt:%{!pthread:-a shared -lc -a archive}}}}}\
10764 %{shared:%{mt|pthread:-lpthread}}"
10767 Index: gcc/config/pa/pa.md
10768 ===================================================================
10769 --- gcc/config/pa/pa.md (.../tags/gcc_4_5_2_release) (wersja 170084)
10770 +++ gcc/config/pa/pa.md (.../branches/gcc-4_5-branch) (wersja 170084)
10771 @@ -811,7 +811,7 @@
10772 (match_operand:DI 3 "arith11_operand" "rI"))
10773 (match_operand:DI 1 "register_operand" "r")))]
10775 - "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0"
10776 + "sub%I3,* %3,%2,%%r0\;add,dc %%r0,%1,%0"
10777 [(set_attr "type" "binary")
10778 (set_attr "length" "8")])
10780 @@ -833,7 +833,7 @@
10781 (match_operand:DI 3 "register_operand" "r"))
10782 (match_operand:DI 1 "register_operand" "r")))]
10784 - "sub %2,%3,%%r0\;add,dc %%r0,%1,%0"
10785 + "sub,* %2,%3,%%r0\;add,dc %%r0,%1,%0"
10786 [(set_attr "type" "binary")
10787 (set_attr "length" "8")])
10789 @@ -856,7 +856,7 @@
10790 (match_operand:DI 3 "int11_operand" "I"))
10791 (match_operand:DI 1 "register_operand" "r")))]
10793 - "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0"
10794 + "addi,* %k3,%2,%%r0\;add,dc %%r0,%1,%0"
10795 [(set_attr "type" "binary")
10796 (set_attr "length" "8")])
10798 @@ -902,7 +902,7 @@
10799 (gtu:DI (match_operand:DI 2 "register_operand" "r")
10800 (match_operand:DI 3 "arith11_operand" "rI"))))]
10802 - "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0"
10803 + "sub%I3,* %3,%2,%%r0\;sub,db %1,%%r0,%0"
10804 [(set_attr "type" "binary")
10805 (set_attr "length" "8")])
10807 @@ -924,7 +924,7 @@
10808 (match_operand:DI 3 "arith11_operand" "rI")))
10809 (match_operand:DI 4 "register_operand" "r")))]
10811 - "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0"
10812 + "sub%I3,* %3,%2,%%r0\;sub,db %1,%4,%0"
10813 [(set_attr "type" "binary")
10814 (set_attr "length" "8")])
10816 @@ -946,7 +946,7 @@
10817 (ltu:DI (match_operand:DI 2 "register_operand" "r")
10818 (match_operand:DI 3 "register_operand" "r"))))]
10820 - "sub %2,%3,%%r0\;sub,db %1,%%r0,%0"
10821 + "sub,* %2,%3,%%r0\;sub,db %1,%%r0,%0"
10822 [(set_attr "type" "binary")
10823 (set_attr "length" "8")])
10825 @@ -968,7 +968,7 @@
10826 (match_operand:DI 3 "register_operand" "r")))
10827 (match_operand:DI 4 "register_operand" "r")))]
10829 - "sub %2,%3,%%r0\;sub,db %1,%4,%0"
10830 + "sub,* %2,%3,%%r0\;sub,db %1,%4,%0"
10831 [(set_attr "type" "binary")
10832 (set_attr "length" "8")])
10834 @@ -991,7 +991,7 @@
10835 (leu:DI (match_operand:DI 2 "register_operand" "r")
10836 (match_operand:DI 3 "int11_operand" "I"))))]
10838 - "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0"
10839 + "addi,* %k3,%2,%%r0\;sub,db %1,%%r0,%0"
10840 [(set_attr "type" "binary")
10841 (set_attr "length" "8")])
10843 @@ -1013,7 +1013,7 @@
10844 (match_operand:DI 3 "int11_operand" "I")))
10845 (match_operand:DI 4 "register_operand" "r")))]
10847 - "addi %k3,%2,%%r0\;sub,db %1,%4,%0"
10848 + "addi,* %k3,%2,%%r0\;sub,db %1,%4,%0"
10849 [(set_attr "type" "binary")
10850 (set_attr "length" "8")])
10852 Index: gcc/config/pa/pa-hpux11.h
10853 ===================================================================
10854 --- gcc/config/pa/pa-hpux11.h (.../tags/gcc_4_5_2_release) (wersja 170084)
10855 +++ gcc/config/pa/pa-hpux11.h (.../branches/gcc-4_5-branch) (wersja 170084)
10857 /* Definitions of target machine for GNU compiler, for HP PA-RISC
10858 - Copyright (C) 1998, 1999, 2000, 2002, 2003, 2004, 2005, 2007, 2008
10859 + Copyright (C) 1998, 1999, 2000, 2002, 2003, 2004, 2005, 2007, 2008, 2011
10860 Free Software Foundation, Inc.
10862 This file is part of GCC.
10863 @@ -114,16 +114,17 @@
10864 -z %{mlinker-opt:-O} %{!shared:-u main -u __gcc_plt_call}\
10865 %{static:-a archive} %{shared:-b}"
10867 -/* HP-UX 11 has posix threads. HP libc contains pthread stubs so that
10868 - non-threaded applications can be linked with a thread-safe libc
10869 - without a subsequent loss of performance. For more details, see
10870 - <http://docs.hp.com/en/1896/pthreads.html>. */
10871 +/* HP-UX 11 has posix threads. HP's shared libc contains pthread stubs
10872 + so that non-threaded applications can be linked with a thread-safe
10873 + libc without a subsequent loss of performance. For more details,
10874 + see <http://docs.hp.com/en/1896/pthreads.html>. */
10878 - %{static|mt|pthread:%{fopenmp:%{static:-a archive_shared} -lrt\
10879 - %{static:-a archive}} -lpthread} -lc\
10880 - %{static:%{!nolibdld:-a archive_shared -ldld -a archive -lc}}}\
10881 + %{fopenmp:%{static:-a archive_shared} -lrt %{static:-a archive}}\
10882 + %{mt|pthread:-lpthread} -lc\
10883 + %{static:%{!nolibdld:-a archive_shared -ldld -a archive -lc}\
10884 + %{!mt:%{!pthread:-a shared -lc -a archive}}}}\
10885 %{shared:%{mt|pthread:-lpthread}}"
10887 #undef STARTFILE_SPEC
10888 Index: gcc/config/pa/t-pa64
10889 ===================================================================
10890 --- gcc/config/pa/t-pa64 (.../tags/gcc_4_5_2_release) (wersja 170084)
10891 +++ gcc/config/pa/t-pa64 (.../branches/gcc-4_5-branch) (wersja 170084)
10893 # Copyright (C) 2000, 2001, 2002, 2004, 2006,
10894 -# 2007 Free Software Foundation, Inc.
10895 +# 2007, 2011 Free Software Foundation, Inc.
10897 # This file is part of GCC.
10899 Index: gcc/config/pa/pa.c
10900 ===================================================================
10901 --- gcc/config/pa/pa.c (.../tags/gcc_4_5_2_release) (wersja 170084)
10902 +++ gcc/config/pa/pa.c (.../branches/gcc-4_5-branch) (wersja 170084)
10903 @@ -6097,37 +6097,94 @@
10906 /* Return TRUE if INSN, a jump insn, has an unfilled delay slot and
10907 - it branches to the next real instruction. Otherwise, return FALSE. */
10908 + it branches into the delay slot. Otherwise, return FALSE. */
10911 branch_to_delay_slot_p (rtx insn)
10915 if (dbr_sequence_length ())
10918 - return next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn);
10919 + jump_insn = next_active_insn (JUMP_LABEL (insn));
10922 + insn = next_active_insn (insn);
10923 + if (jump_insn == insn)
10926 + /* We can't rely on the length of asms. So, we return FALSE when
10927 + the branch is followed by an asm. */
10929 + || GET_CODE (PATTERN (insn)) == ASM_INPUT
10930 + || extract_asm_operands (PATTERN (insn)) != NULL_RTX
10931 + || get_attr_length (insn) > 0)
10938 -/* Return TRUE if INSN, a jump insn, needs a nop in its delay slot.
10939 +/* Return TRUE if INSN, a forward jump insn, needs a nop in its delay slot.
10941 This occurs when INSN has an unfilled delay slot and is followed
10942 - by an ASM_INPUT. Disaster can occur if the ASM_INPUT is empty and
10943 - the jump branches into the delay slot. So, we add a nop in the delay
10944 - slot just to be safe. This messes up our instruction count, but we
10945 - don't know how big the ASM_INPUT insn is anyway. */
10946 + by an asm. Disaster can occur if the asm is empty and the jump
10947 + branches into the delay slot. So, we add a nop in the delay slot
10948 + when this occurs. */
10951 branch_needs_nop_p (rtx insn)
10956 if (dbr_sequence_length ())
10959 - next_insn = next_real_insn (insn);
10960 - return GET_CODE (PATTERN (next_insn)) == ASM_INPUT;
10961 + jump_insn = next_active_insn (JUMP_LABEL (insn));
10964 + insn = next_active_insn (insn);
10965 + if (!insn || jump_insn == insn)
10968 + if (!(GET_CODE (PATTERN (insn)) == ASM_INPUT
10969 + || extract_asm_operands (PATTERN (insn)) != NULL_RTX)
10970 + && get_attr_length (insn) > 0)
10977 +/* Return TRUE if INSN, a forward jump insn, can use nullification
10978 + to skip the following instruction. This avoids an extra cycle due
10979 + to a mis-predicted branch when we fall through. */
10982 +use_skip_p (rtx insn)
10984 + rtx jump_insn = next_active_insn (JUMP_LABEL (insn));
10988 + insn = next_active_insn (insn);
10990 + /* We can't rely on the length of asms, so we can't skip asms. */
10992 + || GET_CODE (PATTERN (insn)) == ASM_INPUT
10993 + || extract_asm_operands (PATTERN (insn)) != NULL_RTX)
10995 + if (get_attr_length (insn) == 4
10996 + && jump_insn == next_active_insn (insn))
10998 + if (get_attr_length (insn) > 0)
11005 /* This routine handles all the normal conditional branch sequences we
11006 might need to generate. It handles compare immediate vs compare
11007 register, nullification of delay slots, varying length branches,
11008 @@ -6139,7 +6196,7 @@
11009 output_cbranch (rtx *operands, int negated, rtx insn)
11011 static char buf[100];
11014 int nullify = INSN_ANNULLED_BRANCH_P (insn);
11015 int length = get_attr_length (insn);
11017 @@ -6177,12 +6234,7 @@
11018 /* A forward branch over a single nullified insn can be done with a
11019 comclr instruction. This avoids a single cycle penalty due to
11020 mis-predicted branch if we fall through (branch not taken). */
11022 - && next_real_insn (insn) != 0
11023 - && get_attr_length (next_real_insn (insn)) == 4
11024 - && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
11027 + useskip = (length == 4 && nullify) ? use_skip_p (insn) : FALSE;
11031 @@ -6470,7 +6522,7 @@
11032 output_bb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which)
11034 static char buf[100];
11037 int nullify = INSN_ANNULLED_BRANCH_P (insn);
11038 int length = get_attr_length (insn);
11040 @@ -6496,14 +6548,8 @@
11041 /* A forward branch over a single nullified insn can be done with a
11042 extrs instruction. This avoids a single cycle penalty due to
11043 mis-predicted branch if we fall through (branch not taken). */
11044 + useskip = (length == 4 && nullify) ? use_skip_p (insn) : FALSE;
11047 - && next_real_insn (insn) != 0
11048 - && get_attr_length (next_real_insn (insn)) == 4
11049 - && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
11056 @@ -6661,7 +6707,7 @@
11057 output_bvb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which)
11059 static char buf[100];
11062 int nullify = INSN_ANNULLED_BRANCH_P (insn);
11063 int length = get_attr_length (insn);
11065 @@ -6687,14 +6733,8 @@
11066 /* A forward branch over a single nullified insn can be done with a
11067 extrs instruction. This avoids a single cycle penalty due to
11068 mis-predicted branch if we fall through (branch not taken). */
11069 + useskip = (length == 4 && nullify) ? use_skip_p (insn) : FALSE;
11072 - && next_real_insn (insn) != 0
11073 - && get_attr_length (next_real_insn (insn)) == 4
11074 - && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
11081 Index: gcc/config/pa/stublib.c
11082 ===================================================================
11083 --- gcc/config/pa/stublib.c (.../tags/gcc_4_5_2_release) (wersja 170084)
11084 +++ gcc/config/pa/stublib.c (.../branches/gcc-4_5-branch) (wersja 170084)
11087 - Copyright (C) 2006, 2009 Free Software Foundation, Inc.
11088 + Copyright (C) 2006, 2009, 2011 Free Software Foundation, Inc.
11090 This file is part of GCC.
11092 Index: gcc/reload1.c
11093 ===================================================================
11094 --- gcc/reload1.c (.../tags/gcc_4_5_2_release) (wersja 170084)
11095 +++ gcc/reload1.c (.../branches/gcc-4_5-branch) (wersja 170084)
11097 /* Reload pseudo regs into hard regs for insns that require hard regs.
11098 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
11099 - 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
11100 - Free Software Foundation, Inc.
11101 + 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
11102 + 2011 Free Software Foundation, Inc.
11104 This file is part of GCC.
11106 @@ -6266,18 +6266,7 @@
11107 && (rld[r].nregs == max_group_size
11108 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
11109 search_equiv = rld[r].in;
11110 - /* If this is an output reload from a simple move insn, look
11111 - if an equivalence for the input is available. */
11112 - else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
11114 - rtx set = single_set (insn);
11117 - && rtx_equal_p (rld[r].out, SET_DEST (set))
11118 - && CONSTANT_P (SET_SRC (set)))
11119 - search_equiv = SET_SRC (set);
11125 @@ -7759,10 +7748,22 @@
11126 /* Maybe the spill reg contains a copy of reload_out. */
11127 if (rld[r].out != 0
11128 && (REG_P (rld[r].out)
11129 -#ifdef AUTO_INC_DEC
11130 - || ! rld[r].out_reg
11132 - || REG_P (rld[r].out_reg)))
11133 + || (rld[r].out_reg
11134 + ? REG_P (rld[r].out_reg)
11135 + /* The reload value is an auto-modification of
11136 + some kind. For PRE_INC, POST_INC, PRE_DEC
11137 + and POST_DEC, we record an equivalence
11138 + between the reload register and the operand
11139 + on the optimistic assumption that we can make
11140 + the equivalence hold. reload_as_needed must
11141 + then either make it hold or invalidate the
11144 + PRE_MODIFY and POST_MODIFY addresses are reloaded
11145 + somewhat differently, and allowing them here leads
11147 + : (GET_CODE (rld[r].out) != POST_MODIFY
11148 + && GET_CODE (rld[r].out) != PRE_MODIFY))))
11151 enum machine_mode mode;
11152 @@ -8706,7 +8707,7 @@
11153 be used as an address. */
11156 - emit_insn (gen_move_insn (reloadreg, incloc));
11157 + add_insn = emit_insn (gen_move_insn (reloadreg, incloc));
11161 Index: gcc/gthr-posix95.h
11162 ===================================================================
11163 --- gcc/gthr-posix95.h (.../tags/gcc_4_5_2_release) (wersja 170084)
11164 +++ gcc/gthr-posix95.h (.../branches/gcc-4_5-branch) (wersja 170084)
11166 /* Threads compatibility routines for libgcc2 and libobjc. */
11167 /* Compile this one with gcc. */
11168 -/* Copyright (C) 2004, 2005, 2007, 2008, 2009 Free Software Foundation, Inc.
11169 +/* Copyright (C) 2004, 2005, 2007, 2008, 2009, 2011
11170 + Free Software Foundation, Inc.
11172 This file is part of GCC.
11174 @@ -184,61 +185,34 @@
11175 calls in shared flavors of the HP-UX C library. Most of the stubs
11176 have no functionality. The details are described in the "libc cumulative
11177 patch" for each subversion of HP-UX 11. There are two special interfaces
11178 - provided for checking whether an application is linked to a pthread
11179 + provided for checking whether an application is linked to a shared pthread
11180 library or not. However, these interfaces aren't available in early
11181 - libc versions. We also can't use pthread_once as some libc versions
11182 - call the init function. So, we use pthread_create to check whether it
11183 - is possible to create a thread or not. The stub implementation returns
11184 - the error number ENOSYS. */
11185 + pthread libraries. We also need a test that works for archive
11186 + libraries. We can't use pthread_once as some libc versions call the
11187 + init function. We also can't use pthread_create or pthread_attr_init
11188 + as these create a thread and thereby prevent changing the default stack
11189 + size. The function pthread_default_stacksize_np is available in both
11190 + the archive and shared versions of libpthread. It can be used to
11191 + determine the default pthread stack size. There is a stub in some
11192 + shared libc versions which returns a zero size if pthreads are not
11193 + active. We provide an equivalent stub to handle cases where libc
11194 + doesn't provide one. */
11196 #if defined(__hppa__) && defined(__hpux__)
11198 -#include <errno.h>
11200 static volatile int __gthread_active = -1;
11203 -__gthread_start (void *arg __attribute__((unused)))
11208 -static void __gthread_active_init (void) __attribute__((noinline));
11210 -__gthread_active_init (void)
11212 - static pthread_mutex_t __gthread_active_mutex = PTHREAD_MUTEX_INITIALIZER;
11214 - pthread_attr_t a;
11217 - __gthrw_(pthread_mutex_lock) (&__gthread_active_mutex);
11218 - if (__gthread_active < 0)
11220 - __gthrw_(pthread_attr_init) (&a);
11221 - __gthrw_(pthread_attr_setdetachstate) (&a, PTHREAD_CREATE_DETACHED);
11222 - result = __gthrw_(pthread_create) (&t, &a, __gthread_start, NULL);
11223 - if (result != ENOSYS)
11224 - __gthread_active = 1;
11226 - __gthread_active = 0;
11227 - __gthrw_(pthread_attr_destroy) (&a);
11229 - __gthrw_(pthread_mutex_unlock) (&__gthread_active_mutex);
11233 __gthread_active_p (void)
11235 /* Avoid reading __gthread_active twice on the main code path. */
11236 int __gthread_active_latest_value = __gthread_active;
11239 - /* This test is not protected to avoid taking a lock on the main code
11240 - path so every update of __gthread_active in a threaded program must
11241 - be atomic with regard to the result of the test. */
11242 if (__builtin_expect (__gthread_active_latest_value < 0, 0))
11244 - __gthread_active_init ();
11245 + pthread_default_stacksize_np (0, &__s);
11246 + __gthread_active = __s ? 1 : 0;
11247 __gthread_active_latest_value = __gthread_active;
11250 Index: libstdc++-v3/src/bitmap_allocator.cc
11251 ===================================================================
11252 --- libstdc++-v3/src/bitmap_allocator.cc (.../tags/gcc_4_5_2_release) (wersja 170084)
11253 +++ libstdc++-v3/src/bitmap_allocator.cc (.../branches/gcc-4_5-branch) (wersja 170084)
11256 #if defined __GTHREADS
11257 __mutex_type& __bfl_mutex = _M_get_mutex();
11258 + __bfl_mutex.lock();
11260 const vector_type& __free_list = _M_get_free_list();
11261 using __gnu_cxx::__detail::__lower_bound;
11262 Index: libstdc++-v3/doc/xml/gnu/gpl-2.0.xml
11263 ===================================================================
11264 --- libstdc++-v3/doc/xml/gnu/gpl-2.0.xml (.../tags/gcc_4_5_2_release) (wersja 170084)
11265 +++ libstdc++-v3/doc/xml/gnu/gpl-2.0.xml (.../branches/gcc-4_5-branch) (wersja 170084)
11267 -<?xml version='1.0' encoding='ISO-8859-1'?>
11268 -<!DOCTYPE appendix PUBLIC "-//OASIS//DTD DocBook XML V4.5//EN"
11269 - "http://www.oasis-open.org/docbook/xml/4.5/docbookx.dtd">
11270 -<appendix id="appendix.gpl-2.0">
11272 - <title>GNU General Public License</title>
11273 - <pubdate>Version 2, June 1991</pubdate>
11275 - <year>1989, 1991</year>
11276 - <holder>Free Software Foundation, Inc.</holder>
11278 - <legalnotice id="gpl-legalnotice">
11280 - <address>Free Software Foundation, Inc.
11281 - <street>51 Franklin Street, Fifth Floor</street>,
11282 - <city>Boston</city>, <state>MA</state> <postcode>02110-1301</postcode>
11283 - <country>USA</country>
11286 - <para>Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed.</para>
11288 - <releaseinfo>Version 2, June 1991</releaseinfo>
11290 - <title>GNU General Public License</title>
11291 - <section id="gpl-1">
11292 - <title>Preamble</title>
11293 - <para>The licenses for most software are designed to take away your
11294 - freedom to share and change it. By contrast, the GNU General Public License is
11295 - intended to guarantee your freedom to share and change
11296 - free software - to make sure the software is free for all its users.
11297 - This General Public License applies to most of the Free Software
11298 - Foundation's software and to any other program whose authors commit
11299 - to using it. (Some other Free Software Foundation software is covered
11300 - by the GNU Library General Public License instead.) You can apply it
11301 - to your programs, too.</para>
11303 - <para>When we speak of free software, we are referring to freedom, not price.
11304 - Our General Public Licenses are designed to make sure that you have the
11305 - freedom to distribute copies of free software (and charge for this
11306 - service if you wish), that you receive source code or can get it if you
11307 - want it, that you can change the software or use pieces of it in new free
11308 - programs; and that you know you can do these things.</para>
11310 - <para>To protect your rights, we need to make restrictions that forbid anyone
11311 - to deny you these rights or to ask you to surrender the rights. These
11312 - restrictions translate to certain responsibilities for you if you distribute
11313 - copies of the software, or if you modify it.</para>
11315 - <para>For example, if you distribute copies of such a program, whether gratis or
11316 - for a fee, you must give the recipients all the rights that you have. You
11317 - must make sure that they, too, receive or can get the source code. And you
11318 - must show them these terms so they know their rights.</para>
11320 - <para>We protect your rights with two steps:
11323 - <para>copyright the software, and</para>
11326 - <para>offer you this license which gives you legal permission to copy,
11327 - distribute and/or modify the software.</para>
11332 - <para>Also, for each author's protection and ours, we want to make certain that
11333 - everyone understands that there is no warranty for this free software. If
11334 - the software is modified by someone else and passed on, we want its
11335 - recipients to know that what they have is not the original, so that any
11336 - problems introduced by others will not reflect on the original authors'
11337 - reputations.</para>
11339 - <para>Finally, any free program is threatened constantly by software patents.
11340 - We wish to avoid the danger that redistributors of a free program will
11341 - individually obtain patent licenses, in effect making the program
11342 - proprietary. To prevent this, we have made it clear that any patent must be
11343 - licensed for everyone's free use or not licensed at all.</para>
11345 - <para>The precise terms and conditions for copying, distribution and modification
11348 - <section id="gpl-2">
11349 - <title>TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION</title>
11350 - <section id="gpl-2-0">
11351 - <title>Section 0</title>
11352 - <para>This License applies to any program or other work which contains a notice
11353 - placed by the copyright holder saying it may be distributed under the terms
11354 - of this General Public License. The <quote>Program</quote>, below, refers to any such
11355 - program or work, and a
11356 - <quote>work based on the Program</quote> means either
11357 - the Program or any derivative work under copyright law: that is to say, a
11358 - work containing the Program or a portion of it, either verbatim or with
11359 - modifications and/or translated into another language. (Hereinafter, translation
11360 - is included without limitation in the term
11361 - <quote>modification</quote>.) Each licensee is addressed as <quote>you</quote>.</para>
11363 - <para>Activities other than copying, distribution and modification are not covered by
11364 - this License; they are outside its scope. The act of running the Program is not
11365 - restricted, and the output from the Program is covered only if its contents
11366 - constitute a work based on the Program (independent of having been made by running
11367 - the Program). Whether that is true depends on what the Program does.</para>
11369 - <section id="gpl-2-1">
11370 - <title>Section 1</title>
11371 - <para>You may copy and distribute verbatim copies of the Program's source code as you
11372 - receive it, in any medium, provided that you conspicuously and appropriately
11373 - publish on each copy an appropriate copyright notice and disclaimer of warranty;
11374 - keep intact all the notices that refer to this License and to the absence of any
11375 - warranty; and give any other recipients of the Program a copy of this License
11376 - along with the Program.</para>
11378 - <para>You may charge a fee for the physical act of transferring a copy, and you may at
11379 - your option offer warranty protection in exchange for a fee.</para>
11381 - <section id="gpl-2-2">
11382 - <title>Section 2</title>
11383 - <para>You may modify your copy or copies of the Program or any portion of it, thus
11384 - forming a work based on the Program, and copy and distribute such modifications
11385 - or work under the terms of
11386 - <link linkend="gpl-2-1">Section 1</link> above, provided
11387 - that you also meet all of these conditions:
11388 - <orderedlist numeration="loweralpha">
11390 - <para>You must cause the modified files to carry prominent notices stating that
11391 - you changed the files and the date of any change.</para>
11394 - <para>You must cause any work that you distribute or publish, that in whole or
11395 - in part contains or is derived from the Program or any part thereof, to be
11396 - licensed as a whole at no charge to all third parties under the terms of
11397 - this License.</para>
11400 - <para>If the modified program normally reads commands interactively when run, you
11401 - must cause it, when started running for such interactive use in the most
11402 - ordinary way, to print or display an announcement including an appropriate
11403 - copyright notice and a notice that there is no warranty (or else, saying
11404 - that you provide a warranty) and that users may redistribute the program
11405 - under these conditions, and telling the user how to view a copy of this
11406 - License. (Exception: If the Program itself is interactive but does not
11407 - normally print such an announcement, your work based on the Program is not
11408 - required to print an announcement.)</para>
11413 - <para>These requirements apply to the modified work as a whole. If identifiable sections
11414 - of that work are not derived from the Program, and can be reasonably considered
11415 - independent and separate works in themselves, then this License, and its terms,
11416 - do not apply to those sections when you distribute them as separate works. But when
11417 - you distribute the same sections as part of a whole which is a work based on the
11418 - Program, the distribution of the whole must be on the terms of this License, whose
11419 - permissions for other licensees extend to the entire whole, and thus to each and
11420 - every part regardless of who wrote it.</para>
11422 - <para>Thus, it is not the intent of this section to claim rights or contest your rights
11423 - to work written entirely by you; rather, the intent is to exercise the right to control
11424 - the distribution of derivative or collective works based on the Program.</para>
11426 - <para>In addition, mere aggregation of another work not based on the Program with the Program
11427 - (or with a work based on the Program) on a volume of a storage or distribution medium
11428 - does not bring the other work under the scope of this License.</para>
11430 - <section id="gpl-2-3">
11431 - <title>Section 3</title>
11432 - <para>You may copy and distribute the Program (or a work based on it, under
11433 - <link linkend="gpl-2-2">Section 2</link> in object code or executable form under the terms of
11434 - <link linkend="gpl-2-1">Sections 1</link> and
11435 - <link linkend="gpl-2-2">2</link> above provided that you also do one of the following:
11436 - <orderedlist numeration="loweralpha">
11438 - <para>Accompany it with the complete corresponding machine-readable source code, which
11439 - must be distributed under the terms of Sections 1 and 2 above on a medium
11440 - customarily used for software interchange; or,</para>
11443 - <para>Accompany it with a written offer, valid for at least three years, to give any
11444 - third party, for a charge no more than your cost of physically performing source
11445 - distribution, a complete machine-readable copy of the corresponding source code,
11446 - to be distributed under the terms of Sections 1 and 2 above on a medium customarily
11447 - used for software interchange; or,</para>
11450 - <para>Accompany it with the information you received as to the offer to distribute
11451 - corresponding source code. (This alternative is allowed only for noncommercial
11452 - distribution and only if you received the program in object code or executable form
11453 - with such an offer, in accord with Subsection b above.)</para>
11458 - <para>The source code for a work means the preferred form of the work for making modifications
11459 - to it. For an executable work, complete source code means all the source code for all modules
11460 - it contains, plus any associated interface definition files, plus the scripts used to control
11461 - compilation and installation of the executable. However, as a special exception, the source
11462 - code distributed need not include anything that is normally distributed (in either source or
11463 - binary form) with the major components (compiler, kernel, and so on) of the operating system
11464 - on which the executable runs, unless that component itself accompanies the executable.</para>
11466 - <para>If distribution of executable or object code is made by offering access to copy from a
11467 - designated place, then offering equivalent access to copy the source code from the same place
11468 - counts as distribution of the source code, even though third parties are not compelled to
11469 - copy the source along with the object code.</para>
11471 - <section id="gpl-2-4">
11472 - <title>Section 4</title>
11473 - <para>You may not copy, modify, sublicense, or distribute the Program except as expressly provided
11474 - under this License. Any attempt otherwise to copy, modify, sublicense or distribute the
11475 - Program is void, and will automatically terminate your rights under this License. However,
11476 - parties who have received copies, or rights, from you under this License will not have their
11477 - licenses terminated so long as such parties remain in full compliance.</para>
11479 - <section id="gpl-2-5">
11480 - <title>Section 5</title>
11481 - <para>You are not required to accept this License, since you have not signed it. However, nothing
11482 - else grants you permission to modify or distribute the Program or its derivative works.
11483 - These actions are prohibited by law if you do not accept this License. Therefore, by modifying
11484 - or distributing the Program (or any work based on the Program), you indicate your acceptance
11485 - of this License to do so, and all its terms and conditions for copying, distributing or
11486 - modifying the Program or works based on it.</para>
11488 - <section id="gpl-2-6">
11489 - <title>Section 6</title>
11490 - <para>Each time you redistribute the Program (or any work based on the Program), the recipient
11491 - automatically receives a license from the original licensor to copy, distribute or modify
11492 - the Program subject to these terms and conditions. You may not impose any further restrictions
11493 - on the recipients' exercise of the rights granted herein. You are not responsible for enforcing
11494 - compliance by third parties to this License.</para>
11496 - <section id="gpl-2-7">
11497 - <title>Section 7</title>
11498 - <para>If, as a consequence of a court judgment or allegation of patent infringement or for any other
11499 - reason (not limited to patent issues), conditions are imposed on you (whether by court order,
11500 - agreement or otherwise) that contradict the conditions of this License, they do not excuse you
11501 - from the conditions of this License. If you cannot distribute so as to satisfy simultaneously
11502 - your obligations under this License and any other pertinent obligations, then as a consequence
11503 - you may not distribute the Program at all. For example, if a patent license would not permit
11504 - royalty-free redistribution of the Program by all those who receive copies directly or
11505 - indirectly through you, then the only way you could satisfy both it and this License would be
11506 - to refrain entirely from distribution of the Program.</para>
11508 - <para>If any portion of this section is held invalid or unenforceable under any particular circumstance,
11509 - the balance of the section is intended to apply and the section as a whole is intended to apply
11510 - in other circumstances.</para>
11512 - <para>It is not the purpose of this section to induce you to infringe any patents or other property
11513 - right claims or to contest validity of any such claims; this section has the sole purpose of
11514 - protecting the integrity of the free software distribution system, which is implemented by public
11515 - license practices. Many people have made generous contributions to the wide range of software
11516 - distributed through that system in reliance on consistent application of that system; it is up
11517 - to the author/donor to decide if he or she is willing to distribute software through any other
11518 - system and a licensee cannot impose that choice.</para>
11520 - <para>This section is intended to make thoroughly clear what is believed to be a consequence of the
11521 - rest of this License.</para>
11523 - <section id="gpl-2-8">
11524 - <title>Section 8</title>
11525 - <para>If the distribution and/or use of the Program is restricted in certain countries either by patents
11526 - or by copyrighted interfaces, the original copyright holder who places the Program under this License
11527 - may add an explicit geographical distribution limitation excluding those countries, so that
11528 - distribution is permitted only in or among countries not thus excluded. In such case, this License
11529 - incorporates the limitation as if written in the body of this License.</para>
11531 - <section id="gpl-2-9">
11532 - <title>Section 9</title>
11533 - <para>The Free Software Foundation may publish revised and/or new versions of the General Public License
11534 - from time to time. Such new versions will be similar in spirit to the present version, but may differ
11535 - in detail to address new problems or concerns.</para>
11537 - <para>Each version is given a distinguishing version number. If the Program specifies a version number of
11538 - this License which applies to it and <quote>any later version</quote>, you have the option of following the terms
11539 - and conditions either of that version or of any later version published by the Free Software
11540 - Foundation. If the Program does not specify a version number of this License, you may choose any
11541 - version ever published by the Free Software Foundation.</para>
11543 - <section id="gpl-2-10">
11544 - <title>Section 10</title>
11545 - <para>If you wish to incorporate parts of the Program into other free programs whose distribution
11546 - conditions are different, write to the author to ask for permission. For software which is copyrighted
11547 - by the Free Software Foundation, write to the Free Software Foundation; we sometimes make exceptions
11548 - for this. Our decision will be guided by the two goals of preserving the free status of all
11549 - derivatives of our free software and of promoting the sharing and reuse of software generally.</para>
11551 - <section id="gpl-2-11">
11552 - <title>NO WARRANTY Section 11</title>
11553 - <para>BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT
11554 - PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR
11555 - OTHER PARTIES PROVIDE THE PROGRAM <quote>AS IS</quote> WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED,
11556 - INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
11557 - PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
11558 - PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION.</para>
11560 - <section id="gpl-2-12">
11561 - <title>Section 12</title>
11562 - <para>IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR
11563 - ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU
11564 - FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
11565 - USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED
11566 - INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH
11567 - ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
11570 - <para>END OF TERMS AND CONDITIONS</para>
11573 - <section id="gpl-3">
11574 - <title>How to Apply These Terms to Your New Programs</title>
11575 - <para>If you develop a new program, and you want it to be of the greatest
11576 - possible use to the public, the best way to achieve this is to make it
11577 - free software which everyone can redistribute and change under these terms.</para>
11579 - <para>To do so, attach the following notices to the program. It is safest
11580 - to attach them to the start of each source file to most effectively
11581 - convey the exclusion of warranty; and each file should have at least
11582 - the <quote>copyright</quote> line and a pointer to where the full notice is found.</para>
11584 - <para><one line to give the program's name and a brief idea of what it does.>
11585 - Copyright (C) <year> <name of author></para>
11587 - <para>This program is free software; you can redistribute it and/or modify
11588 - it under the terms of the GNU General Public License as published by
11589 - the Free Software Foundation; either version 2 of the License, or
11590 - (at your option) any later version.</para>
11592 - <para>This program is distributed in the hope that it will be useful,
11593 - but WITHOUT ANY WARRANTY; without even the implied warranty of
11594 - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11595 - GNU General Public License for more details.</para>
11597 - <para>You should have received a copy of the GNU General Public License
11598 - along with this program; if not, write to the Free Software
11599 - Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA</para>
11601 - <para>Also add information on how to contact you by electronic and paper mail.</para>
11603 - <para>If the program is interactive, make it output a short notice like this
11604 - when it starts in an interactive mode:</para>
11606 - <para>Gnomovision version 69, Copyright (C) year name of author
11607 - Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type <quote>show w</quote>.
11608 - This is free software, and you are welcome to redistribute it
11609 - under certain conditions; type <quote>show c</quote> for details.</para>
11611 - <para>The hypothetical commands <quote>show w</quote> and <quote>show c</quote> should
11612 - show the appropriate parts of the General Public License. Of course, the commands you
11613 - use may be called something other than <quote>show w</quote> and <quote>show c</quote>;
11614 - they could even be mouse-clicks or menu items--whatever suits your program.</para>
11616 - <para>You should also get your employer (if you work as a programmer) or your
11617 - school, if any, to sign a <quote>copyright disclaimer</quote> for the program, if
11618 - necessary. Here is a sample; alter the names:</para>
11620 - <para>Yoyodyne, Inc., hereby disclaims all copyright interest in the program
11621 - <quote>Gnomovision</quote> (which makes passes at compilers) written by James Hacker.</para>
11623 - <para><signature of Ty Coon>, 1 April 1989
11624 - Ty Coon, President of Vice</para>
11626 - <para>This General Public License does not permit incorporating your program into
11627 - proprietary programs. If your program is a subroutine library, you may
11628 - consider it more useful to permit linking proprietary applications with the
11629 - library. If this is what you want to do, use the GNU Library General
11630 - Public License instead of this License.</para>
11633 Index: libstdc++-v3/doc/xml/manual/codecvt.xml
11634 ===================================================================
11635 --- libstdc++-v3/doc/xml/manual/codecvt.xml (.../tags/gcc_4_5_2_release) (wersja 170084)
11636 +++ libstdc++-v3/doc/xml/manual/codecvt.xml (.../branches/gcc-4_5-branch) (wersja 170084)
11637 @@ -595,7 +595,7 @@
11640 <biblioid class="uri">
11641 - <ulink url="http://www.opengroup.org/austin">
11642 + <ulink url="http://www.opengroup.org/austin/">
11644 System Interface Definitions, Issue 7 (IEEE Std. 1003.1-2008)
11646 Index: libstdc++-v3/doc/xml/manual/using_exceptions.xml
11647 ===================================================================
11648 --- libstdc++-v3/doc/xml/manual/using_exceptions.xml (.../tags/gcc_4_5_2_release) (wersja 170084)
11649 +++ libstdc++-v3/doc/xml/manual/using_exceptions.xml (.../branches/gcc-4_5-branch) (wersja 170084)
11650 @@ -440,7 +440,7 @@
11653 <biblioid class="uri">
11654 - <ulink url="http://www.opengroup.org/austin">
11655 + <ulink url="http://www.opengroup.org/austin/">
11657 System Interface Definitions, Issue 7 (IEEE Std. 1003.1-2008)
11659 Index: libstdc++-v3/doc/xml/manual/debug.xml
11660 ===================================================================
11661 --- libstdc++-v3/doc/xml/manual/debug.xml (.../tags/gcc_4_5_2_release) (wersja 170084)
11662 +++ libstdc++-v3/doc/xml/manual/debug.xml (.../branches/gcc-4_5-branch) (wersja 170084)
11664 communicate information about source constructs can be changed via
11665 <code>-gdwarf-2</code> or <code>-gstabs</code> flags: some debugging
11666 formats permit more expressive type and scope information to be
11667 - shown in gdb. Expressiveness can be enhanced by flags like
11668 + shown in GDB. Expressiveness can be enhanced by flags like
11669 <code>-g3</code>. The default debug information for a particular
11670 platform can be identified via the value set by the
11671 PREFERRED_DEBUGGING_TYPE macro in the gcc sources.
11672 @@ -197,14 +197,14 @@
11676 - Many options are available for gdb itself: please see <ulink
11677 - url="http://sources.redhat.com/gdb/current/onlinedocs/gdb_13.html#SEC125">
11678 - "GDB features for C++" </ulink> in the gdb documentation. Also
11679 + Many options are available for GDB itself: please see <ulink
11680 + url="http://sources.redhat.com/gdb/current/onlinedocs/gdb/">
11681 + "GDB features for C++" </ulink> in the GDB documentation. Also
11682 recommended: the other parts of this manual.
11686 - These settings can either be switched on in at the gdb command line,
11687 + These settings can either be switched on in at the GDB command line,
11688 or put into a .gdbint file to establish default debugging
11689 characteristics, like so:
11691 Index: libstdc++-v3/doc/xml/manual/locale.xml
11692 ===================================================================
11693 --- libstdc++-v3/doc/xml/manual/locale.xml (.../tags/gcc_4_5_2_release) (wersja 170084)
11694 +++ libstdc++-v3/doc/xml/manual/locale.xml (.../branches/gcc-4_5-branch) (wersja 170084)
11695 @@ -571,7 +571,7 @@
11698 <biblioid class="uri">
11699 - <ulink url="http://www.opengroup.org/austin">
11700 + <ulink url="http://www.opengroup.org/austin/">
11702 System Interface Definitions, Issue 7 (IEEE Std. 1003.1-2008)
11704 Index: libstdc++-v3/doc/xml/manual/messages.xml
11705 ===================================================================
11706 --- libstdc++-v3/doc/xml/manual/messages.xml (.../tags/gcc_4_5_2_release) (wersja 170084)
11707 +++ libstdc++-v3/doc/xml/manual/messages.xml (.../branches/gcc-4_5-branch) (wersja 170084)
11708 @@ -498,7 +498,7 @@
11711 <biblioid class="uri">
11712 - <ulink url="http://www.opengroup.org/austin">
11713 + <ulink url="http://www.opengroup.org/austin/">
11715 System Interface Definitions, Issue 7 (IEEE Std. 1003.1-2008)
11717 Index: libstdc++-v3/doc/Makefile.in
11718 ===================================================================
11719 --- libstdc++-v3/doc/Makefile.in (.../tags/gcc_4_5_2_release) (wersja 170084)
11720 +++ libstdc++-v3/doc/Makefile.in (.../branches/gcc-4_5-branch) (wersja 170084)
11721 @@ -343,7 +343,6 @@
11723 xml_sources_extra = \
11724 ${xml_dir}/gnu/fdl-1.2.xml \
11725 - ${xml_dir}/gnu/gpl-2.0.xml \
11726 ${xml_dir}/gnu/gpl-3.0.xml
11729 Index: libstdc++-v3/doc/Makefile.am
11730 ===================================================================
11731 --- libstdc++-v3/doc/Makefile.am (.../tags/gcc_4_5_2_release) (wersja 170084)
11732 +++ libstdc++-v3/doc/Makefile.am (.../branches/gcc-4_5-branch) (wersja 170084)
11733 @@ -204,7 +204,6 @@
11735 xml_sources_extra = \
11736 ${xml_dir}/gnu/fdl-1.2.xml \
11737 - ${xml_dir}/gnu/gpl-2.0.xml \
11738 ${xml_dir}/gnu/gpl-3.0.xml
11741 Index: libstdc++-v3/include/bits/atomic_0.h
11742 ===================================================================
11743 --- libstdc++-v3/include/bits/atomic_0.h (.../tags/gcc_4_5_2_release) (wersja 170084)
11744 +++ libstdc++-v3/include/bits/atomic_0.h (.../branches/gcc-4_5-branch) (wersja 170084)
11746 // -*- C++ -*- header.
11748 -// Copyright (C) 2008, 2009
11749 +// Copyright (C) 2008, 2009, 2010, 2011
11750 // Free Software Foundation, Inc.
11752 // This file is part of the GNU ISO C++ Library. This library is free
11753 @@ -49,34 +49,34 @@
11754 atomic_flag_clear_explicit(__g, __x); \
11757 -#define _ATOMIC_STORE_(__a, __m, __x) \
11758 +#define _ATOMIC_STORE_(__a, __n, __x) \
11759 ({__typeof__ _ATOMIC_MEMBER_* __p = &_ATOMIC_MEMBER_; \
11760 - __typeof__(__m) __v = (__m); \
11761 + __typeof__(__n) __w = (__n); \
11762 __atomic_flag_base* __g = __atomic_flag_for_address(__p); \
11763 __atomic_flag_wait_explicit(__g, __x); \
11766 atomic_flag_clear_explicit(__g, __x); \
11770 -#define _ATOMIC_MODIFY_(__a, __o, __m, __x) \
11771 +#define _ATOMIC_MODIFY_(__a, __o, __n, __x) \
11772 ({__typeof__ _ATOMIC_MEMBER_* __p = &_ATOMIC_MEMBER_; \
11773 - __typeof__(__m) __v = (__m); \
11774 + __typeof__(__n) __w = (__n); \
11775 __atomic_flag_base* __g = __atomic_flag_for_address(__p); \
11776 __atomic_flag_wait_explicit(__g, __x); \
11777 __typeof__ _ATOMIC_MEMBER_ __r = *__p; \
11780 atomic_flag_clear_explicit(__g, __x); \
11783 -#define _ATOMIC_CMPEXCHNG_(__a, __e, __m, __x) \
11784 +#define _ATOMIC_CMPEXCHNG_(__a, __e, __n, __x) \
11785 ({__typeof__ _ATOMIC_MEMBER_* __p = &_ATOMIC_MEMBER_; \
11786 __typeof__(__e) __q = (__e); \
11787 - __typeof__(__m) __v = (__m); \
11788 + __typeof__(__n) __w = (__n); \
11790 __atomic_flag_base* __g = __atomic_flag_for_address(__p); \
11791 __atomic_flag_wait_explicit(__g, __x); \
11792 __typeof__ _ATOMIC_MEMBER_ __t__ = *__p; \
11793 - if (__t__ == *__q) { *__p = __v; __r = true; } \
11794 + if (__t__ == *__q) { *__p = __w; __r = true; } \
11795 else { *__q = __t__; __r = false; } \
11796 atomic_flag_clear_explicit(__g, __x); \
11798 Index: libstdc++-v3/ChangeLog
11799 ===================================================================
11800 --- libstdc++-v3/ChangeLog (.../tags/gcc_4_5_2_release) (wersja 170084)
11801 +++ libstdc++-v3/ChangeLog (.../branches/gcc-4_5-branch) (wersja 170084)
11803 +2011-02-08 Jonathan Wakely <jwakely.gcc@gmail.com>
11805 + * doc/xml/gnu/gpl-2.0.xml: Remove.
11806 + * doc/Makefile.am: Update.
11807 + * doc/Makefile.in: Regenerate.
11809 +2011-02-06 Gerald Pfeifer <gerald@pfeifer.com>
11811 + * doc/xml/manual/debug.xml: Use GDB instead of gdb.
11812 + Adjust link to GDB manual.
11814 +2011-02-01 Paolo Carlini <paolo.carlini@oracle.com>
11816 + PR libstdc++/46914
11817 + * include/bits/atomic_0.h (_ATOMIC_STORE_, _ATOMIC_MODIFY_,
11818 + _ATOMIC_CMPEXCHNG_): Rename __v -> __w, and __m -> __n, to
11819 + avoid name conflicts.
11821 +2011-01-30 Gerald Pfeifer <gerald@pfeifer.com>
11823 + * doc/xml/manual/codecvt.xml: Fix link to The Austin Common
11824 + Standards Revision Group.
11825 + * doc/xml/manual/locale.xml: Ditto.
11826 + * doc/xml/manual/messages.xml: Ditto.
11827 + * doc/xml/manual/using_exceptions.xml: Ditto.
11829 +2011-01-19 Graham Reed <greed@pobox.com>
11831 + PR libstdc++/47354
11832 + * src/bitmap_allocator.cc (free_list::_M_get): Lock mutex.
11834 +2010-12-17 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
11836 + Backport from mainline:
11837 + 2010-12-10 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
11839 + * testsuite/lib/libstdc++.exp (v3-build_support): Delete
11840 + libtestc++.a before creation.
11842 2010-12-16 Release Manager
11844 * GCC 4.5.2 released.
11845 Index: libstdc++-v3/testsuite/lib/libstdc++.exp
11846 ===================================================================
11847 --- libstdc++-v3/testsuite/lib/libstdc++.exp (.../tags/gcc_4_5_2_release) (wersja 170084)
11848 +++ libstdc++-v3/testsuite/lib/libstdc++.exp (.../branches/gcc-4_5-branch) (wersja 170084)
11849 @@ -586,6 +586,15 @@
11852 # Collect into libtestc++.a
11853 + # Delete libtestc++.a first. Mixed 32 and 64-bit archives cannot be
11854 + # linked on IRIX 6.
11855 + # Use same procedure as gcc-dg.exp (remove-build-file).
11856 + if [is_remote host] {
11857 + # Ensure the host knows the file is gone by deleting there
11859 + remote_file host delete "./libtestc++.a"
11861 + remote_file build delete "./libtestc++.a"
11862 if [info exists env(AR)] {
11865 Index: configure.ac
11866 ===================================================================
11867 --- configure.ac (.../tags/gcc_4_5_2_release) (wersja 170084)
11868 +++ configure.ac (.../branches/gcc-4_5-branch) (wersja 170084)
11869 @@ -1510,8 +1510,6 @@
11870 AC_SUBST(poststage1_ldflags)
11873 -ppl_major_version=0
11874 -ppl_minor_version=10
11875 ppllibs=" -lppl_c -lppl -lgmpxx"
11878 @@ -1552,9 +1550,9 @@
11879 if test "x$with_ppl" != "xno" -a "${ENABLE_PPL_CHECK}" = "yes"; then
11880 saved_CFLAGS="$CFLAGS"
11881 CFLAGS="$CFLAGS $pplinc $gmpinc"
11882 - AC_MSG_CHECKING([for version $ppl_major_version.$ppl_minor_version of PPL])
11883 + AC_MSG_CHECKING([for version 0.10 (or later revision) of PPL])
11884 AC_TRY_COMPILE([#include "ppl_c.h"],[
11885 - #if PPL_VERSION_MAJOR != $ppl_major_version || PPL_VERSION_MINOR != $ppl_minor_version
11886 + #if PPL_VERSION_MAJOR != 0 || PPL_VERSION_MINOR < 10
11889 ], [AC_MSG_RESULT([yes])], [AC_MSG_RESULT([no]); ppllibs= ; pplinc= ; with_ppl=no ])
11891 ===================================================================
11892 --- ChangeLog (.../tags/gcc_4_5_2_release) (wersja 170084)
11893 +++ ChangeLog (.../branches/gcc-4_5-branch) (wersja 170084)
11895 +2011-01-25 Richard Guenther <rguenther@suse.de>
11897 + Backport from mainline
11898 + 2010-05-05 Sebastian Pop <sebastian.pop@amd.com>
11900 + * configure.ac: Allow all the versions greater than 0.10 of PPL.
11901 + * configure: Regenerated.
11903 2010-12-16 Release Manager
11905 * GCC 4.5.2 released.
11906 Index: libffi/ChangeLog
11907 ===================================================================
11908 --- libffi/ChangeLog (.../tags/gcc_4_5_2_release) (wersja 170084)
11909 +++ libffi/ChangeLog (.../branches/gcc-4_5-branch) (wersja 170084)
11911 +2011-02-09 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
11914 + * testsuite/libffi.call/cls_pointer.c (main): Cast void * to
11916 + * testsuite/libffi.call/cls_pointer_stack.c (main): Likewise.
11918 +2010-12-17 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
11920 + Backport from mainline:
11921 + 2010-12-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
11923 + * testsuite/libffi.call/ffitest.h [__sgi] (PRId64, PRIu64): Define.
11924 + (PRIuPTR): Define.
11926 2010-12-16 Release Manager
11928 * GCC 4.5.2 released.
11929 Index: libffi/testsuite/libffi.call/cls_pointer.c
11930 ===================================================================
11931 --- libffi/testsuite/libffi.call/cls_pointer.c (.../tags/gcc_4_5_2_release) (wersja 170084)
11932 +++ libffi/testsuite/libffi.call/cls_pointer.c (.../branches/gcc-4_5-branch) (wersja 170084)
11935 CHECK(ffi_prep_closure_loc(pcl, &cif, cls_pointer_gn, NULL, code) == FFI_OK);
11937 - res = (ffi_arg)((void*(*)(void*, void*))(code))(arg1, arg2);
11938 + res = (ffi_arg)(uintptr_t)((void*(*)(void*, void*))(code))(arg1, arg2);
11939 /* { dg-output "\n0x12345678 0x89abcdef: 0x9be02467" } */
11940 printf("res: 0x%08x\n", (unsigned int) res);
11941 /* { dg-output "\nres: 0x9be02467" } */
11942 Index: libffi/testsuite/libffi.call/cls_pointer_stack.c
11943 ===================================================================
11944 --- libffi/testsuite/libffi.call/cls_pointer_stack.c (.../tags/gcc_4_5_2_release) (wersja 170084)
11945 +++ libffi/testsuite/libffi.call/cls_pointer_stack.c (.../branches/gcc-4_5-branch) (wersja 170084)
11946 @@ -129,7 +129,7 @@
11948 CHECK(ffi_prep_closure_loc(pcl, &cif, cls_pointer_gn, NULL, code) == FFI_OK);
11950 - res = (ffi_arg)((void*(*)(void*, void*))(code))(arg1, arg2);
11951 + res = (ffi_arg)(uintptr_t)((void*(*)(void*, void*))(code))(arg1, arg2);
11953 printf("res: 0x%08x\n", (unsigned int) res);
11954 // { dg-output "\n0x01234567 0x89abcdef: 0x8acf1356" }
11955 Index: libffi/testsuite/libffi.call/ffitest.h
11956 ===================================================================
11957 --- libffi/testsuite/libffi.call/ffitest.h (.../tags/gcc_4_5_2_release) (wersja 170084)
11958 +++ libffi/testsuite/libffi.call/ffitest.h (.../branches/gcc-4_5-branch) (wersja 170084)
11960 #define PRIuPTR "lu"
11963 +/* IRIX kludge. */
11964 +#if defined(__sgi)
11965 +/* IRIX 6.5 <inttypes.h> provides all definitions, but only for C99
11967 +#if (_MIPS_SZLONG == 32)
11968 +#define PRId64 "lld"
11969 +#define PRIu64 "llu"
11971 +/* This doesn't match <inttypes.h>, which always has "lld" here, but the
11972 + arguments are uint64_t, int64_t, which are unsigned long, long for
11973 + 64-bit in <sgidefs.h>. */
11974 +#if (_MIPS_SZLONG == 64)
11975 +#define PRId64 "ld"
11976 +#define PRIu64 "lu"
11978 +/* This doesn't match <inttypes.h>, which has "u" here, but the arguments
11979 + are uintptr_t, which is always unsigned long. */
11980 +#define PRIuPTR "lu"
11983 /* Solaris < 10 kludge. */
11984 #if defined(__sun__) && defined(__svr4__) && !defined(PRIuPTR)
11985 #if defined(__arch64__) || defined (__x86_64__)
11986 Index: libjava/classpath/lib/java/security/VMAccessController.class
11987 ===================================================================
11988 Nie można wyświetlić: plik binarny.
11989 svn:mime-type = application/octet-stream
11990 Index: libjava/ChangeLog
11991 ===================================================================
11992 --- libjava/ChangeLog (.../tags/gcc_4_5_2_release) (wersja 170084)
11993 +++ libjava/ChangeLog (.../branches/gcc-4_5-branch) (wersja 170084)
11995 +2011-01-07 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
11997 + Backport from mainline:
11998 + 2011-01-06 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
12000 + * testsuite/libjava.jni/jni.exp (gcj_jni_get_cxxflags_invocation):
12001 + Add -shared-libgcc to cxxflags for *-*-solaris*.
12004 +2010-12-13 Andrew John Hughes <ahughes@redhat.com>
12007 + * libjava/java/security/VMAccessController.java:
12008 + (DEFAULT_CONTEXT): Create ProtectionDomain with
12009 + four argument constructor (arguments are the same
12010 + as those implied by the two argument constructor).
12011 + (getContext()): Create ProtectionDomain instances
12012 + with four argument constructor using a null Principal
12013 + array (as before) but including the classloader, which
12014 + was always null before.
12016 2010-12-16 Release Manager
12018 * GCC 4.5.2 released.
12019 Index: libjava/testsuite/libjava.jni/jni.exp
12020 ===================================================================
12021 --- libjava/testsuite/libjava.jni/jni.exp (.../tags/gcc_4_5_2_release) (wersja 170084)
12022 +++ libjava/testsuite/libjava.jni/jni.exp (.../branches/gcc-4_5-branch) (wersja 170084)
12023 @@ -274,8 +274,10 @@
12024 eval lappend cxxflags "-shared-libgcc -lgcj $libiconv"
12027 + # Make sure libgcc unwinder is used on 64-bit Solaris 10+/x86 rather than
12029 if { [istarget "*-*-solaris*"] } {
12030 - lappend cxxflags "-lsocket"
12031 + lappend cxxflags "-shared-libgcc"
12035 Index: libjava/java/security/VMAccessController.java
12036 ===================================================================
12037 --- libjava/java/security/VMAccessController.java (.../tags/gcc_4_5_2_release) (wersja 170084)
12038 +++ libjava/java/security/VMAccessController.java (.../branches/gcc-4_5-branch) (wersja 170084)
12040 Permissions permissions = new Permissions();
12041 permissions.add(new AllPermission());
12042 ProtectionDomain[] domain = new ProtectionDomain[] {
12043 - new ProtectionDomain(source, permissions)
12044 + new ProtectionDomain(source, permissions, null, null)
12046 DEFAULT_CONTEXT = new AccessControlContext(domain);
12048 @@ -178,12 +178,13 @@
12049 for (int i = 3; i < classes.length; i++)
12051 Class clazz = classes[i];
12052 + ClassLoader loader = clazz.getClassLoader();
12056 debug("checking " + clazz);
12057 // subject to getClassLoader RuntimePermission
12058 - debug("loader = " + clazz.getClassLoader());
12059 + debug("loader = " + loader);
12062 if (privileged && i == classes.length - 2)
12063 @@ -208,7 +209,8 @@
12064 // Create a static snapshot of this domain, which may change over time
12065 // if the current policy changes.
12066 domains.add(new ProtectionDomain(domain.getCodeSource(),
12067 - domain.getPermissions()));
12068 + domain.getPermissions(),
12073 Index: libcpp/directives.c
12074 ===================================================================
12075 --- libcpp/directives.c (.../tags/gcc_4_5_2_release) (wersja 170084)
12076 +++ libcpp/directives.c (.../branches/gcc-4_5-branch) (wersja 170084)
12077 @@ -280,16 +280,17 @@
12079 end_directive (cpp_reader *pfile, int skip_line)
12081 - if (pfile->state.in_deferred_pragma)
12083 - else if (CPP_OPTION (pfile, traditional))
12084 + if (CPP_OPTION (pfile, traditional))
12086 /* Revert change of prepare_directive_trad. */
12087 - pfile->state.prevent_expansion--;
12088 + if (!pfile->state.in_deferred_pragma)
12089 + pfile->state.prevent_expansion--;
12091 if (pfile->directive != &dtable[T_DEFINE])
12092 _cpp_remove_overlay (pfile);
12094 + else if (pfile->state.in_deferred_pragma)
12096 /* We don't skip for an assembler #. */
12097 else if (skip_line)
12099 Index: libcpp/ChangeLog
12100 ===================================================================
12101 --- libcpp/ChangeLog (.../tags/gcc_4_5_2_release) (wersja 170084)
12102 +++ libcpp/ChangeLog (.../branches/gcc-4_5-branch) (wersja 170084)
12104 +2011-11-04 Eric Botcazou <ebotcazou@adacore.com>
12105 + Jakub Jelinek <jakub@redhat.com>
12107 + PR preprocessor/39213
12108 + * directives.c (end_directive): Call _cpp_remove_overlay for deferred
12109 + pragmas as well in traditional mode.
12111 2010-12-16 Release Manager
12113 * GCC 4.5.2 released.