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Commit | Line | Data |
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5384b728 | 1 | 2002-05-05 Jakub Jelinek <jakub@redhat.com> |
2 | ||
3 | * config/sparc/sparc.md (ashlsi3): If shift count is const1_rtx, | |
4 | use add instead of shift. | |
5 | (ashldi3_sp64): Likewise. | |
6 | (ashlsi3_const1, ashldi3_const1): Remove. | |
7 | * config/sparc/sparc.h (PREDICATE_CODES): Add const1_operand. | |
8 | * config/sparc/sparc.c (const1_operand): New. | |
9 | ||
10 | --- gcc/config/sparc/sparc.md.jj Sun May 5 21:56:45 2002 | |
11 | +++ gcc/config/sparc/sparc.md Sun May 5 23:33:31 2002 | |
12 | @@ -7559,18 +7559,13 @@ | |
13 | && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 31) | |
14 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); | |
15 | ||
16 | + if (operands[2] == const1_rtx) | |
17 | + return \"add\\t%1, %1, %0\"; | |
18 | return \"sll\\t%1, %2, %0\"; | |
19 | }" | |
20 | - [(set_attr "type" "shift")]) | |
21 | - | |
22 | -;; We special case multiplication by two, as add can be done | |
23 | -;; in both ALUs, while shift only in IEU0 on UltraSPARC. | |
24 | -(define_insn "*ashlsi3_const1" | |
25 | - [(set (match_operand:SI 0 "register_operand" "=r") | |
26 | - (ashift:SI (match_operand:SI 1 "register_operand" "r") | |
27 | - (const_int 1)))] | |
28 | - "" | |
29 | - "add\\t%1, %1, %0") | |
30 | + [(set (attr "type") | |
31 | + (if_then_else (match_operand 2 "const1_operand" "") | |
32 | + (const_string "ialu") (const_string "shift")))]) | |
33 | ||
34 | (define_expand "ashldi3" | |
35 | [(set (match_operand:DI 0 "register_operand" "=r") | |
36 | @@ -7588,15 +7583,6 @@ | |
37 | } | |
38 | }") | |
39 | ||
40 | -;; We special case multiplication by two, as add can be done | |
41 | -;; in both ALUs, while shift only in IEU0 on UltraSPARC. | |
42 | -(define_insn "*ashldi3_const1" | |
43 | - [(set (match_operand:DI 0 "register_operand" "=r") | |
44 | - (ashift:DI (match_operand:DI 1 "register_operand" "r") | |
45 | - (const_int 1)))] | |
46 | - "TARGET_ARCH64" | |
47 | - "add\\t%1, %1, %0") | |
48 | - | |
49 | (define_insn "*ashldi3_sp64" | |
50 | [(set (match_operand:DI 0 "register_operand" "=r") | |
51 | (ashift:DI (match_operand:DI 1 "register_operand" "r") | |
52 | @@ -7608,9 +7594,13 @@ | |
53 | && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 63) | |
54 | operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); | |
55 | ||
56 | + if (operands[2] == const1_rtx) | |
57 | + return \"add\\t%1, %1, %0\"; | |
58 | return \"sllx\\t%1, %2, %0\"; | |
59 | }" | |
60 | - [(set_attr "type" "shift")]) | |
61 | + [(set (attr "type") | |
62 | + (if_then_else (match_operand 2 "const1_operand" "") | |
63 | + (const_string "ialu") (const_string "shift")))]) | |
64 | ||
65 | ;; XXX UGH! | |
66 | (define_insn "ashldi3_v8plus" | |
67 | --- gcc/config/sparc/sparc.h.jj Fri May 3 22:57:33 2002 | |
68 | +++ gcc/config/sparc/sparc.h Sun May 5 23:20:48 2002 | |
69 | @@ -3014,6 +3014,7 @@ do { \ | |
70 | ||
71 | #define PREDICATE_CODES \ | |
72 | {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ | |
73 | +{"const1_operand", {CONST_INT}}, \ | |
74 | {"fp_zero_operand", {CONST_DOUBLE}}, \ | |
75 | {"fp_register_operand", {SUBREG, REG}}, \ | |
76 | {"intreg_operand", {SUBREG, REG}}, \ | |
77 | --- gcc/config/sparc/sparc.c.jj Fri May 3 22:57:33 2002 | |
78 | +++ gcc/config/sparc/sparc.c Sun May 5 23:24:18 2002 | |
79 | @@ -478,6 +478,16 @@ reg_or_0_operand (op, mode) | |
80 | return 0; | |
81 | } | |
82 | ||
83 | +/* Return non-zero only if OP is const1_rtx. */ | |
84 | + | |
85 | +int | |
86 | +const1_operand (op, mode) | |
87 | + rtx op; | |
88 | + enum machine_mode mode ATTRIBUTE_UNUSED; | |
89 | +{ | |
90 | + return op == const1_rtx; | |
91 | +} | |
92 | + | |
93 | /* Nonzero if OP is a floating point value with value 0.0. */ | |
94 | ||
95 | int |