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Commit | Line | Data |
---|---|---|
1 | --- XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/s3/newmmio.h.fix Mon Jul 2 19:46:04 2001 | |
2 | +++ XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/s3/newmmio.h Mon Jan 21 08:18:14 2002 | |
3 | @@ -251,7 +251,7 @@ | |
4 | #define WaitQueue(v) \ | |
5 | if(!(pS3->PCIRetry)) { \ | |
6 | mem_barrier(); \ | |
7 | - while(inb(GP_STAT) & (0x0100 >> (v))); \ | |
8 | + while(mmio_INB_GP_STAT() & (0x0100 >> (v))); \ | |
9 | } | |
10 | ||
11 | #define CMD_REG_WIDTH 0x200 /* select 32bit command register */ | |
12 | --- XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/s3/s3_accel.c.fix Sun Oct 28 12:33:44 2001 | |
13 | +++ XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/s3/s3_accel.c Mon Jan 21 08:22:08 2002 | |
14 | @@ -46,6 +46,7 @@ | |
15 | ||
16 | static void S3Sync(ScrnInfoPtr pScrn) | |
17 | { | |
18 | + S3Ptr pS3 = S3PTR(pScrn); | |
19 | WaitIdle(); | |
20 | } | |
21 | ||
22 | @@ -64,9 +65,7 @@ | |
23 | static void S3SubsequentSolidFillRect(ScrnInfoPtr pScrn, int x, int y, | |
24 | int w, int h) | |
25 | { | |
26 | -#ifdef S3_NEWMMIO | |
27 | S3Ptr pS3 = S3PTR(pScrn); | |
28 | -#endif | |
29 | ||
30 | WaitQueue(5); | |
31 | SET_CURPT((short)x, (short)y); | |
32 | @@ -303,9 +302,8 @@ | |
33 | int major, int minor, | |
34 | int err, int len, int octant) | |
35 | { | |
36 | -#ifdef S3_NEWMMIO | |
37 | S3Ptr pS3 = S3PTR(pScrn); | |
38 | -#endif | |
39 | + | |
40 | unsigned short cmd; | |
41 | int error, e1, e2; | |
42 | ||
43 | --- XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/s3/s3_dga.c.fix Mon Jul 2 19:46:04 2001 | |
44 | +++ XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/s3/s3_dga.c Mon Jan 21 08:18:14 2002 | |
45 | @@ -314,5 +314,6 @@ | |
46 | ||
47 | static void S3_Sync(ScrnInfoPtr pScrn) | |
48 | { | |
49 | + S3Ptr pS3 = S3PTR(pScrn); | |
50 | WaitIdle(); | |
51 | } | |
52 | --- XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/s3/s3_driver.c.fix Thu Dec 27 07:24:19 2001 | |
53 | +++ XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/s3/s3_driver.c Mon Jan 21 08:18:14 2002 | |
54 | @@ -1569,7 +1569,20 @@ | |
55 | ||
56 | outb(0x3c6, 0x00); | |
57 | ||
58 | - outw(SUBSYS_CNTL, 0x8000 | 0x1000); | |
59 | +/* | |
60 | +* XXX: resetting the Trio64V2/GX causes trouble with the SGRAM memory bus | |
61 | +* (gets out of sync? same as setting CR88_6) which I don't know to fix, | |
62 | +* so better not reset that chip and cross fingers... | |
63 | +* This happens at least for some IBM Netfinity boxes (e.g. 7000M10) with 1MB SGRAM. | |
64 | +*/ | |
65 | + if (pS3->Chipset == PCI_CHIP_TRIO64V2_DXGX) { | |
66 | + outb(vgaCRIndex, 0x36); | |
67 | + tmp = inb(vgaCRReg); | |
68 | + if ((tmp & 0x0c) != 0x04) /* no SGRAM */ | |
69 | + outw(SUBSYS_CNTL, 0x8000 | 0x1000); | |
70 | + } | |
71 | + else /* do normal reset for S3 chip... */ | |
72 | + outw(SUBSYS_CNTL, 0x8000 | 0x1000); | |
73 | outw(SUBSYS_CNTL, 0x4000 | 0x1000); | |
74 | ||
75 | inw(SUBSYS_STAT); | |
76 | @@ -1603,6 +1616,12 @@ | |
77 | ||
78 | WaitQueue(5); | |
79 | SET_SCISSORS(0, 0, pS3->s3ScissR, pS3->s3ScissB); | |
80 | + if(pS3->s3Bpp > 2) { | |
81 | + if(pS3->S3NewMMIO) | |
82 | + SET_MULT_MISC(0x200); | |
83 | + else | |
84 | + SET_MULT_MISC(0); | |
85 | + } | |
86 | ||
87 | outb(vgaCRIndex, 0x6f); | |
88 | ||
89 | --- XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/s3/s3_reg.h.fix Mon Jul 2 19:46:04 2001 | |
90 | +++ XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/s3/s3_reg.h Mon Jan 21 08:18:14 2002 | |
91 | @@ -148,10 +148,23 @@ | |
92 | outw(p, (n) >> 16); \ | |
93 | } else outw(p, n) | |
94 | ||
95 | +/* | |
96 | + * mmio reads from GP_STAT | |
97 | + */ | |
98 | +#if !defined(__alpha__) | |
99 | +#define mmio_INB_GP_STAT() (*(((volatile unsigned char*)pS3->MMIOBase)+GP_STAT) & 0xff) | |
100 | +#define mmio_INW_GP_STAT() (*(((volatile unsigned short*)pS3->MMIOBase)+GP_STAT/2)) | |
101 | +#else | |
102 | +#define mmio_INB_GP_STAT() inb(GP_STAT) | |
103 | +#define mmio_INW_GP_STAT() inw(GP_STAT) | |
104 | +#endif | |
105 | ||
106 | #define WaitIdle() do { \ | |
107 | mem_barrier(); \ | |
108 | - while(inw(GP_STAT) & GPBUSY); \ | |
109 | + if (pS3->S3NewMMIO) \ | |
110 | + while(mmio_INW_GP_STAT() & GPBUSY); \ | |
111 | + else \ | |
112 | + while(inw(GP_STAT) & GPBUSY); \ | |
113 | } while(0) | |
114 | ||
115 | ||
116 | @@ -184,9 +197,12 @@ | |
117 | ||
118 | #define CMD_REG_WIDTH 0x0000 | |
119 | ||
120 | -#define WaitQueue(n) do { \ | |
121 | +#define WaitQueue(n) do { \ | |
122 | mem_barrier(); \ | |
123 | - while(inb(GP_STAT) & (0x0100 >> (n))); \ | |
124 | + if (pS3->S3NewMMIO) \ | |
125 | + while(mmio_INB_GP_STAT() & (0x0100 >> (n))); \ | |
126 | + else \ | |
127 | + while(inb(GP_STAT) & (0x0100 >> (n))); \ | |
128 | } while (0) | |
129 | ||
130 | #define WaitQueue16_32(n16,n32) \ |