tg3: Fix io failures after chip reset

Changed files:
    kernel-small_fixes.patch -> 1.37

diff --git a/kernel-small_fixes.patch b/kernel-small_fixes.patch
index ec974aaf1001ade6659bc2bfd3090520da89207b..7679e41d0a939def5b8d962c18eadb4a82a8e486 100644 (file)
--- a/kernel-small_fixes.patch
+++ b/kernel-small_fixes.patch
@@ -801,3 +801,60 @@ index 7f7b424..8fd4a07 100644
  
        trace_xfs_file_read(ip, size, iocb->ki_pos, ioflags);
  
+commit 9e975cc291d80d5e4562d6bed15ec171e896d69b
+Author: Matt Carlson <mcarlson@broadcom.com>
+Date:   Wed Jul 20 10:20:50 2011 +0000
+
+    tg3: Fix io failures after chip reset
+    
+    Commit f2096f94b514d88593355995d5dd276961e88af1, entitled
+    "tg3: Add 5720 H2BMC support", needed to add code to preserve some bits
+    set by firmware.  Unfortunately the new code causes throughput to stop
+    after a chip reset because it enables state machines before they are
+    ready.  This patch undoes the problematic code.  The bits will be
+    restored later in the init sequence.
+    
+    Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
+    Reviewed-by: Michael Chan <mchan@broadcom.com>
+    Signed-off-by: David S. Miller <davem@davemloft.net>
+
+diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
+index a5ff82d..5bf7671 100644
+--- a/drivers/net/tg3.c
++++ b/drivers/net/tg3.c
+@@ -7412,16 +7412,11 @@ static int tg3_chip_reset(struct tg3 *tp)
+               tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
+       }
+ 
+-      if (tg3_flag(tp, ENABLE_APE))
+-              tp->mac_mode = MAC_MODE_APE_TX_EN |
+-                             MAC_MODE_APE_RX_EN |
+-                             MAC_MODE_TDE_ENABLE;
+-
+       if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
+-              tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
++              tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
+               val = tp->mac_mode;
+       } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
+-              tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
++              tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
+               val = tp->mac_mode;
+       } else
+               val = 0;
+@@ -8559,12 +8554,11 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
+               udelay(10);
+       }
+ 
+-      if (tg3_flag(tp, ENABLE_APE))
+-              tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
+-      else
+-              tp->mac_mode = 0;
+       tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
+-              MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
++                      MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
++                      MAC_MODE_FHDE_ENABLE;
++      if (tg3_flag(tp, ENABLE_APE))
++              tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
+       if (!tg3_flag(tp, 5705_PLUS) &&
+           !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
+           GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)