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Commit | Line | Data |
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1 | Description: Enable Coffee Lake support | |
2 | ||
3 | Little change is needed here because the graphics core is the same as | |
4 | Kaby Lake. Includes all PCI IDs currently supported by the kernel driver | |
5 | in the drm-intel tree (Coffee Lake S, H and U devices in GT 1, 2 and 3 | |
6 | configurations). | |
7 | ||
8 | Origin: upstream 7e181af2ea4d37f67406f2563c0e13fa1fdbb14b | |
9 | Author: Mark Thompson | |
10 | ||
11 | --- a/backend/src/backend/gen_program.cpp | |
12 | +++ b/backend/src/backend/gen_program.cpp | |
13 | @@ -209,6 +209,8 @@ namespace gbe { | |
14 | ctx = GBE_NEW(BxtContext, unit, name, deviceID, relaxMath); | |
15 | } else if (IS_KABYLAKE(deviceID)) { | |
16 | ctx = GBE_NEW(KblContext, unit, name, deviceID, relaxMath); | |
17 | + } else if (IS_COFFEELAKE(deviceID)) { | |
18 | + ctx = GBE_NEW(KblContext, unit, name, deviceID, relaxMath); | |
19 | } else if (IS_GEMINILAKE(deviceID)) { | |
20 | ctx = GBE_NEW(GlkContext, unit, name, deviceID, relaxMath); | |
21 | } | |
22 | @@ -328,6 +330,7 @@ namespace gbe { | |
23 | (IS_SKYLAKE(deviceID) && MATCH_SKL_HEADER(binary)) || \ | |
24 | (IS_BROXTON(deviceID) && MATCH_BXT_HEADER(binary)) || \ | |
25 | (IS_KABYLAKE(deviceID) && MATCH_KBL_HEADER(binary)) || \ | |
26 | + (IS_COFFEELAKE(deviceID) && MATCH_KBL_HEADER(binary)) || \ | |
27 | (IS_GEMINILAKE(deviceID) && MATCH_GLK_HEADER(binary)) \ | |
28 | ) | |
29 | ||
30 | @@ -436,6 +439,8 @@ namespace gbe { | |
31 | FILL_BXT_HEADER(*binary); | |
32 | }else if(IS_KABYLAKE(prog->deviceID)){ | |
33 | FILL_KBL_HEADER(*binary); | |
34 | + }else if(IS_COFFEELAKE(prog->deviceID)){ | |
35 | + FILL_KBL_HEADER(*binary); | |
36 | }else if(IS_GEMINILAKE(prog->deviceID)){ | |
37 | FILL_GLK_HEADER(*binary); | |
38 | }else { | |
39 | --- a/src/cl_device_data.h | |
40 | +++ b/src/cl_device_data.h | |
41 | @@ -372,7 +372,59 @@ | |
42 | (devid == PCI_CHIP_GLK_3x6 || \ | |
43 | devid == PCI_CHIP_GLK_2x6) | |
44 | ||
45 | -#define IS_GEN9(devid) (IS_SKYLAKE(devid) || IS_BROXTON(devid) || IS_KABYLAKE(devid) || IS_GEMINILAKE(devid)) | |
46 | +#define PCI_CHIP_COFFEELAKE_S_GT1_1 0x3E90 | |
47 | +#define PCI_CHIP_COFFEELAKE_S_GT1_2 0x3E93 | |
48 | +#define PCI_CHIP_COFFEELAKE_S_GT1_3 0x3E99 | |
49 | + | |
50 | +#define PCI_CHIP_COFFEELAKE_U_GT1_1 0x3EA1 | |
51 | +#define PCI_CHIP_COFFEELAKE_U_GT1_2 0x3EA4 | |
52 | + | |
53 | +#define PCI_CHIP_COFFEELAKE_S_GT2_1 0x3E91 | |
54 | +#define PCI_CHIP_COFFEELAKE_S_GT2_2 0x3E92 | |
55 | +#define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96 | |
56 | +#define PCI_CHIP_COFFEELAKE_S_GT2_4 0x3E9A | |
57 | + | |
58 | +#define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E94 | |
59 | +#define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E9B | |
60 | + | |
61 | +#define PCI_CHIP_COFFEELAKE_U_GT2_1 0x3EA0 | |
62 | +#define PCI_CHIP_COFFEELAKE_U_GT2_2 0x3EA3 | |
63 | +#define PCI_CHIP_COFFEELAKE_U_GT2_3 0x3EA9 | |
64 | + | |
65 | +#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA2 | |
66 | +#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA5 | |
67 | +#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA6 | |
68 | +#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA7 | |
69 | +#define PCI_CHIP_COFFEELAKE_U_GT3_5 0x3EA8 | |
70 | + | |
71 | +#define IS_CFL_GT1(devid) \ | |
72 | + (devid == PCI_CHIP_COFFEELAKE_S_GT1_1 || \ | |
73 | + devid == PCI_CHIP_COFFEELAKE_S_GT1_2 || \ | |
74 | + devid == PCI_CHIP_COFFEELAKE_S_GT1_3 || \ | |
75 | + devid == PCI_CHIP_COFFEELAKE_U_GT1_1 || \ | |
76 | + devid == PCI_CHIP_COFFEELAKE_U_GT1_2) | |
77 | + | |
78 | +#define IS_CFL_GT2(devid) \ | |
79 | + (devid == PCI_CHIP_COFFEELAKE_S_GT2_1 || \ | |
80 | + devid == PCI_CHIP_COFFEELAKE_S_GT2_2 || \ | |
81 | + devid == PCI_CHIP_COFFEELAKE_S_GT2_3 || \ | |
82 | + devid == PCI_CHIP_COFFEELAKE_S_GT2_4 || \ | |
83 | + devid == PCI_CHIP_COFFEELAKE_H_GT2_1 || \ | |
84 | + devid == PCI_CHIP_COFFEELAKE_H_GT2_2 || \ | |
85 | + devid == PCI_CHIP_COFFEELAKE_U_GT2_1 || \ | |
86 | + devid == PCI_CHIP_COFFEELAKE_U_GT2_2 || \ | |
87 | + devid == PCI_CHIP_COFFEELAKE_U_GT2_3) | |
88 | + | |
89 | +#define IS_CFL_GT3(devid) \ | |
90 | + (devid == PCI_CHIP_COFFEELAKE_U_GT3_1 || \ | |
91 | + devid == PCI_CHIP_COFFEELAKE_U_GT3_2 || \ | |
92 | + devid == PCI_CHIP_COFFEELAKE_U_GT3_3 || \ | |
93 | + devid == PCI_CHIP_COFFEELAKE_U_GT3_4 || \ | |
94 | + devid == PCI_CHIP_COFFEELAKE_U_GT3_5) | |
95 | + | |
96 | +#define IS_COFFEELAKE(devid) (IS_CFL_GT1(devid) || IS_CFL_GT2(devid) || IS_CFL_GT3(devid)) | |
97 | + | |
98 | +#define IS_GEN9(devid) (IS_SKYLAKE(devid) || IS_BROXTON(devid) || IS_KABYLAKE(devid) || IS_GEMINILAKE(devid) || IS_COFFEELAKE(devid)) | |
99 | ||
100 | #define MAX_OCLVERSION(devid) (IS_GEN9(devid) ? 200 : 120) | |
101 | ||
102 | --- a/src/cl_device_id.c | |
103 | +++ b/src/cl_device_id.c | |
104 | @@ -274,6 +274,36 @@ static struct _cl_device_id intel_glk12eu_device = { | |
105 | #include "cl_gen9_device.h" | |
106 | }; | |
107 | ||
108 | +static struct _cl_device_id intel_cfl_gt1_device = { | |
109 | + .max_compute_unit = 12, | |
110 | + .max_thread_per_unit = 7, | |
111 | + .sub_slice_count = 2, | |
112 | + .max_work_item_sizes = {512, 512, 512}, | |
113 | + .max_work_group_size = 256, | |
114 | + .max_clock_frequency = 1000, | |
115 | +#include "cl_gen9_device.h" | |
116 | +}; | |
117 | + | |
118 | +static struct _cl_device_id intel_cfl_gt2_device = { | |
119 | + .max_compute_unit = 24, | |
120 | + .max_thread_per_unit = 7, | |
121 | + .sub_slice_count = 3, | |
122 | + .max_work_item_sizes = {512, 512, 512}, | |
123 | + .max_work_group_size = 256, | |
124 | + .max_clock_frequency = 1000, | |
125 | +#include "cl_gen9_device.h" | |
126 | +}; | |
127 | + | |
128 | +static struct _cl_device_id intel_cfl_gt3_device = { | |
129 | + .max_compute_unit = 48, | |
130 | + .max_thread_per_unit = 7, | |
131 | + .sub_slice_count = 6, | |
132 | + .max_work_item_sizes = {512, 512, 512}, | |
133 | + .max_work_group_size = 256, | |
134 | + .max_clock_frequency = 1000, | |
135 | +#include "cl_gen9_device.h" | |
136 | +}; | |
137 | + | |
138 | LOCAL cl_device_id | |
139 | cl_get_gt_device(cl_device_type device_type) | |
140 | { | |
141 | @@ -785,6 +815,64 @@ glk12eu_break: | |
142 | cl_intel_platform_enable_extension(ret, cl_khr_fp16_ext_id); | |
143 | break; | |
144 | ||
145 | + case PCI_CHIP_COFFEELAKE_S_GT1_1: | |
146 | + case PCI_CHIP_COFFEELAKE_S_GT1_2: | |
147 | + case PCI_CHIP_COFFEELAKE_S_GT1_3: | |
148 | + DECL_INFO_STRING(cfl_gt1_break, intel_cfl_gt1_device, name, "Intel(R) UHD Graphics Coffee Lake Desktop GT1"); | |
149 | + case PCI_CHIP_COFFEELAKE_U_GT1_1: | |
150 | + case PCI_CHIP_COFFEELAKE_U_GT1_2: | |
151 | + DECL_INFO_STRING(cfl_gt1_break, intel_cfl_gt1_device, name, "Intel(R) UHD Graphics Coffee Lake Mobile GT1"); | |
152 | +cfl_gt1_break: | |
153 | + intel_cfl_gt1_device.device_id = device_id; | |
154 | + intel_cfl_gt1_device.platform = cl_get_platform_default(); | |
155 | + ret = &intel_cfl_gt1_device; | |
156 | + cl_intel_platform_get_default_extension(ret); | |
157 | +#ifdef ENABLE_FP64 | |
158 | + cl_intel_platform_enable_extension(ret, cl_khr_fp64_ext_id); | |
159 | +#endif | |
160 | + cl_intel_platform_enable_extension(ret, cl_khr_fp16_ext_id); | |
161 | + break; | |
162 | + | |
163 | + case PCI_CHIP_COFFEELAKE_S_GT2_1: | |
164 | + case PCI_CHIP_COFFEELAKE_S_GT2_2: | |
165 | + case PCI_CHIP_COFFEELAKE_S_GT2_3: | |
166 | + case PCI_CHIP_COFFEELAKE_S_GT2_4: | |
167 | + DECL_INFO_STRING(cfl_gt2_break, intel_cfl_gt2_device, name, "Intel(R) UHD Graphics Coffee Lake Desktop GT2"); | |
168 | + case PCI_CHIP_COFFEELAKE_H_GT2_1: | |
169 | + case PCI_CHIP_COFFEELAKE_H_GT2_2: | |
170 | + DECL_INFO_STRING(cfl_gt2_break, intel_cfl_gt2_device, name, "Intel(R) UHD Graphics Coffee Lake Halo GT2"); | |
171 | + case PCI_CHIP_COFFEELAKE_U_GT2_1: | |
172 | + case PCI_CHIP_COFFEELAKE_U_GT2_2: | |
173 | + case PCI_CHIP_COFFEELAKE_U_GT2_3: | |
174 | + DECL_INFO_STRING(cfl_gt2_break, intel_cfl_gt2_device, name, "Intel(R) UHD Graphics Coffee Lake Mobile GT2"); | |
175 | +cfl_gt2_break: | |
176 | + intel_cfl_gt2_device.device_id = device_id; | |
177 | + intel_cfl_gt2_device.platform = cl_get_platform_default(); | |
178 | + ret = &intel_cfl_gt2_device; | |
179 | + cl_intel_platform_get_default_extension(ret); | |
180 | +#ifdef ENABLE_FP64 | |
181 | + cl_intel_platform_enable_extension(ret, cl_khr_fp64_ext_id); | |
182 | +#endif | |
183 | + cl_intel_platform_enable_extension(ret, cl_khr_fp16_ext_id); | |
184 | + break; | |
185 | + | |
186 | + case PCI_CHIP_COFFEELAKE_U_GT3_1: | |
187 | + case PCI_CHIP_COFFEELAKE_U_GT3_2: | |
188 | + case PCI_CHIP_COFFEELAKE_U_GT3_3: | |
189 | + case PCI_CHIP_COFFEELAKE_U_GT3_4: | |
190 | + case PCI_CHIP_COFFEELAKE_U_GT3_5: | |
191 | + DECL_INFO_STRING(cfl_gt3_break, intel_cfl_gt3_device, name, "Intel(R) UHD Graphics Coffee Lake Mobile GT3"); | |
192 | +cfl_gt3_break: | |
193 | + intel_cfl_gt3_device.device_id = device_id; | |
194 | + intel_cfl_gt3_device.platform = cl_get_platform_default(); | |
195 | + ret = &intel_cfl_gt3_device; | |
196 | + cl_intel_platform_get_default_extension(ret); | |
197 | +#ifdef ENABLE_FP64 | |
198 | + cl_intel_platform_enable_extension(ret, cl_khr_fp64_ext_id); | |
199 | +#endif | |
200 | + cl_intel_platform_enable_extension(ret, cl_khr_fp16_ext_id); | |
201 | + break; | |
202 | + | |
203 | case PCI_CHIP_SANDYBRIDGE_BRIDGE: | |
204 | case PCI_CHIP_SANDYBRIDGE_GT1: | |
205 | case PCI_CHIP_SANDYBRIDGE_GT2: | |
206 | @@ -992,7 +1080,10 @@ LOCAL cl_bool is_gen_device(cl_device_id device) { | |
207 | device == &intel_kbl_gt3_device || | |
208 | device == &intel_kbl_gt4_device || | |
209 | device == &intel_glk18eu_device || | |
210 | - device == &intel_glk12eu_device; | |
211 | + device == &intel_glk12eu_device || | |
212 | + device == &intel_cfl_gt1_device || | |
213 | + device == &intel_cfl_gt2_device || | |
214 | + device == &intel_cfl_gt3_device; | |
215 | } | |
216 | ||
217 | LOCAL cl_int | |
218 | @@ -1420,7 +1511,9 @@ cl_device_get_version(cl_device_id device, cl_int *ver) | |
219 | || device == &intel_bxt18eu_device || device == &intel_bxt12eu_device || device == &intel_kbl_gt1_device | |
220 | || device == &intel_kbl_gt2_device || device == &intel_kbl_gt3_device | |
221 | || device == &intel_kbl_gt4_device || device == &intel_kbl_gt15_device | |
222 | - || device == &intel_glk18eu_device || device == &intel_glk12eu_device) { | |
223 | + || device == &intel_glk18eu_device || device == &intel_glk12eu_device | |
224 | + || device == &intel_cfl_gt1_device || device == &intel_cfl_gt1_device | |
225 | + || device == &intel_cfl_gt3_device) { | |
226 | *ver = 9; | |
227 | } else | |
228 | return CL_INVALID_VALUE; |