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Commit | Line | Data |
---|---|---|
bb2ee0f1 | 1 | This patch reverts the following change: |
40812fd2 | 2 | |
bb2ee0f1 JR |
3 | From 657445fe8660100ad174600ebfa61536392b7624 Mon Sep 17 00:00:00 2001 |
4 | From: Daniel Vetter <daniel.vetter@ffwll.ch> | |
5 | Date: Sat, 04 May 2013 08:09:18 +0000 | |
6 | Subject: Revert "drm/i915: revert eDP bpp clamping code changes" | |
40812fd2 | 7 | |
bb2ee0f1 | 8 | This reverts commit 57c219633275c7e7413f8bc7be250dc092887458. |
40812fd2 | 9 | |
bb2ee0f1 JR |
10 | It's an ugly hack for a Haswell SDV platform where the vbt doesn't |
11 | seem to fully agree with the panel. Since it seems to cause issues on | |
12 | real eDP platform let's just kill this hack again. | |
40812fd2 | 13 | |
bb2ee0f1 JR |
14 | Reported-and-tested-by: Josh Boyer <jwboyer@gmail.com> |
15 | References: https://lkml.org/lkml/2013/5/3/467 | |
16 | Cc: Paulo Zanoni <przanoni@gmail.com> | |
17 | Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> | |
40812fd2 | 18 | |
40812fd2 | 19 | |
40812fd2 | 20 | diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c |
bb2ee0f1 | 21 | index fc3bd9b..0ab9813 100644 |
40812fd2 JR |
22 | --- a/drivers/gpu/drm/i915/intel_dp.c |
23 | +++ b/drivers/gpu/drm/i915/intel_dp.c | |
bb2ee0f1 JR |
24 | @@ -702,9 +702,6 @@ intel_dp_compute_config(struct intel_encoder *encoder, |
25 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 | |
26 | * bpc in between. */ | |
27 | bpp = min_t(int, 8*3, pipe_config->pipe_bpp); | |
28 | - if (is_edp(intel_dp) && dev_priv->edp.bpp) | |
29 | - bpp = min_t(int, bpp, dev_priv->edp.bpp); | |
30 | - | |
31 | for (; bpp >= 6*3; bpp -= 2*3) { | |
32 | mode_rate = intel_dp_link_required(target_clock, bpp); | |
33 | ||
34 | @@ -739,7 +742,6 @@ found: | |
35 | intel_dp->link_bw = bws[clock]; | |
36 | intel_dp->lane_count = lane_count; | |
86931f4c | 37 | adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); |
bb2ee0f1 | 38 | - pipe_config->pipe_bpp = bpp; |
86931f4c | 39 | pipe_config->pixel_target_clock = target_clock; |
40812fd2 | 40 | |
86931f4c | 41 | DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", |
bb2ee0f1 JR |
42 | @@ -751,6 +755,20 @@ found: |
43 | target_clock, adjusted_mode->clock, | |
44 | &pipe_config->dp_m_n); | |
45 | ||
46 | + /* | |
47 | + * XXX: We have a strange regression where using the vbt edp bpp value | |
48 | + * for the link bw computation results in black screens, the panel only | |
49 | + * works when we do the computation at the usual 24bpp (but still | |
50 | + * requires us to use 18bpp). Until that's fully debugged, stay | |
51 | + * bug-for-bug compatible with the old code. | |
52 | + */ | |
53 | + if (is_edp(intel_dp) && dev_priv->edp.bpp) { | |
54 | + DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", | |
55 | + bpp, dev_priv->edp.bpp); | |
56 | + bpp = min_t(int, bpp, dev_priv->edp.bpp); | |
57 | + } | |
58 | + pipe_config->pipe_bpp = bpp; | |
59 | + | |
60 | return true; | |
61 | } | |
62 |