projects / packages / beignet.git / blame
| Commit | Line | Data |
|---|---|---|
| 7d3d7cb5 JB |
1 | Description: Fix grammar in documentation |
| 2 | ||
| 3 | Author: Rebecca N. Palmer <rebecca_palmer@zoho.com> | |
| 4 | Forwarded: https://lists.freedesktop.org/archives/beignet/2017-October/009179.html | |
| 5 | ||
| 6 | --- a/docs/Beignet/Backend.mdwn | |
| 7 | +++ b/docs/Beignet/Backend.mdwn | |
| 8 | @@ -9,10 +9,10 @@ Status | |
| 9 | ------ | |
| 10 | ||
| 11 | After two years development, beignet is mature now. It now supports all the | |
| 12 | -OpenCL 1.2 mandatory features. Beignet get almost 100% pass rate with both | |
| 13 | -OpenCV 3.0 test suite and the piglit opencl test suite. There are some | |
| 14 | -performance tuning related items remained, see [[here|Backend/TODO]] for a | |
| 15 | -(incomplete) lists of things to do. | |
| 16 | +OpenCL 1.2 mandatory features. Beignet gets almost 100% pass rate with both | |
| 17 | +the OpenCV 3.0 test suite and the piglit opencl test suite. There are some | |
| 18 | +performance tuning related items remained, see [[here|Backend/TODO]] for an | |
| 19 | +(incomplete) list of things to do. | |
| 20 | ||
| 21 | Interface with the run-time | |
| 22 | --------------------------- | |
| 23 | @@ -61,7 +61,7 @@ Environment variables are used all over | |
| 24 | - `OCL_OUTPUT_REG_ALLOC` `(0 or 1)`. Output Gen register allocations, including | |
| 25 | virtual register to physical register mapping, live ranges. | |
| 26 | ||
| 27 | -- `OCL_OUTPUT_BUILD_LOG` `(0 or 1)`. Output error messages if there is any | |
| 28 | +- `OCL_OUTPUT_BUILD_LOG` `(0 or 1)`. Output error messages if there are any | |
| 29 | during CL kernel compiling and linking. | |
| 30 | ||
| 31 | - `OCL_OUTPUT_CFG` `(0 or 1)`. Output control flow graph in .dot file. | |
| 32 | @@ -70,22 +70,22 @@ Environment variables are used all over | |
| 33 | but without instructions in each BasicBlock. | |
| 34 | ||
| 35 | - `OCL_PRE_ALLOC_INSN_SCHEDULE` `(0 or 1)`. The instruction scheduler in | |
| 36 | - beignet are currently splitted into two passes: before and after register | |
| 37 | - allocation. The pre-alloc scheduler tend to decrease register pressure. | |
| 38 | + beignet is currently split into two passes: before and after register | |
| 39 | + allocation. The pre-alloc scheduler tends to decrease register pressure. | |
| 40 | This variable is used to disable/enable pre-alloc scheduler. This pass is | |
| 41 | disabled now for some bugs. | |
| 42 | ||
| 43 | - `OCL_POST_ALLOC_INSN_SCHEDULE` `(0 or 1)`. Disable/enable post-alloc | |
| 44 | - instruction scheduler. The post-alloc scheduler tend to reduce instruction | |
| 45 | + instruction scheduler. The post-alloc scheduler tends to reduce instruction | |
| 46 | latency. By default, this is enabled now. | |
| 47 | ||
| 48 | -- `OCL_SIMD16_SPILL_THRESHOLD` `(0 to 256)`. Tune how much registers can be | |
| 49 | - spilled under SIMD16. Default value is 16. We find spill too much register | |
| 50 | - under SIMD16 is not as good as fall back to SIMD8 mode. So we set the | |
| 51 | +- `OCL_SIMD16_SPILL_THRESHOLD` `(0 to 256)`. Tune how many registers can be | |
| 52 | + spilled under SIMD16. Default value is 16. We find spilling too many registers | |
| 53 | + under SIMD16 is not as good as falling back to SIMD8 mode. So we set the | |
| 54 | variable to control spilled register number under SIMD16. | |
| 55 | ||
| 56 | - `OCL_USE_PCH` `(0 or 1)`. The default value is 1. If it is enabled, we use | |
| 57 | - a pre compiled header file which include all basic ocl headers. This would | |
| 58 | + a pre compiled header file which includes all basic ocl headers. This would | |
| 59 | reduce the compile time. | |
| 60 | ||
| 61 | Implementation details |