]>
Commit | Line | Data |
---|---|---|
0e570730 | 1 | diff -ru usr/src/nv/nv-linux.h usr/src/nv.1361053/nv-linux.h |
2 | --- usr/src/nv/nv-linux.h 2005-03-22 16:19:09.000000000 +0100 | |
3 | +++ usr/src/nv.1361053/nv-linux.h 2005-10-11 19:01:57.647002680 +0200 | |
4 | @@ -1018,15 +1018,50 @@ | |
5 | #define NV_CHANGE_PAGE_ATTR_BUG_PRESENT 1 | |
6 | #endif | |
7 | ||
8 | +#if defined(NVCPU_X86) || defined(NVCPU_X86_64) | |
9 | +/* | |
10 | + * On Linux/x86-64 (and recent Linux/x86) kernels, the PAGE_KERNEL | |
11 | + * and PAGE_KERNEL_NOCACHE protection bit masks include _PAGE_NX | |
12 | + * to indicate that the no-execute protection page feature is used | |
13 | + * for the page in question. | |
14 | + * | |
15 | + * We need to be careful to mask out _PAGE_NX when the host system | |
16 | + * doesn't support this feature or when it's disabled: the kernel | |
17 | + * may not do this in its implementation of the change_page_attr() | |
18 | + * interface. | |
19 | + */ | |
20 | +#ifndef X86_FEATURE_NX | |
21 | +#define X86_FEATURE_NX (1*32+20) | |
22 | +#endif | |
23 | +#ifndef boot_cpu_has | |
24 | +#define boot_cpu_has(x) test_bit(x, boot_cpu_data.x86_capability) | |
25 | +#endif | |
26 | +#ifndef MSR_EFER | |
27 | +#define MSR_EFER 0xc0000080 | |
28 | +#endif | |
29 | +#ifndef EFER_NX | |
30 | +#define EFER_NX (1 << 11) | |
31 | +#endif | |
32 | +#ifndef _PAGE_NX | |
33 | +#define _PAGE_NX ((NvU64)1 << 63) | |
34 | +#endif | |
35 | +extern NvU64 __nv_supported_pte_mask; | |
36 | +#endif | |
37 | + | |
38 | #if defined(NV_CHANGE_PAGE_ATTR_PRESENT) && !defined(NV_CHANGE_PAGE_ATTR_BUG_PRESENT) | |
39 | static inline void NV_SET_PAGE_ATTRIB_UNCACHED(nv_pte_t *page_ptr) | |
40 | { | |
41 | struct page *page = virt_to_page(__va(page_ptr->phys_addr)); | |
42 | - change_page_attr(page, 1, PAGE_KERNEL_NOCACHE); | |
43 | + pgprot_t prot = PAGE_KERNEL_NOCACHE; | |
44 | +#if defined(NVCPU_X86) || defined(NVCPU_X86_64) | |
45 | + pgprot_val(prot) &= __nv_supported_pte_mask; | |
46 | +#endif | |
47 | + change_page_attr(page, 1, prot); | |
48 | } | |
49 | static inline void NV_SET_PAGE_ATTRIB_CACHED(nv_pte_t *page_ptr) | |
50 | { | |
51 | struct page *page = virt_to_page(__va(page_ptr->phys_addr)); | |
52 | + pgprot_t prot = PAGE_KERNEL; | |
53 | #ifdef CONFIG_SWIOTLB | |
54 | if (page_ptr->orig_phys_addr) | |
55 | { | |
56 | @@ -1034,7 +1069,10 @@ | |
57 | os_dbg_breakpoint(); | |
58 | } | |
59 | #endif | |
60 | - change_page_attr(page, 1, PAGE_KERNEL); | |
61 | +#if defined(NVCPU_X86) || defined(NVCPU_X86_64) | |
62 | + pgprot_val(prot) &= __nv_supported_pte_mask; | |
63 | +#endif | |
64 | + change_page_attr(page, 1, prot); | |
65 | } | |
66 | #else | |
67 | #define NV_SET_PAGE_ATTRIB_UNCACHED(page_list) | |
68 | diff -ru usr/src/nv/nv.c usr/src/nv.1361053/nv.c | |
69 | --- usr/src/nv/nv.c 2005-03-22 16:19:09.000000000 +0100 | |
70 | +++ usr/src/nv.1361053/nv.c 2005-10-11 18:59:20.347915776 +0200 | |
71 | @@ -38,6 +38,10 @@ | |
72 | static int nv_disable_pat = 0; | |
73 | NV_MODULE_PARAMETER(nv_disable_pat); | |
74 | ||
75 | +#if defined(NVCPU_X86) || defined(NVCPU_X86_64) | |
76 | +NvU64 __nv_supported_pte_mask = ~_PAGE_NX; | |
77 | +#endif | |
78 | + | |
79 | /* | |
80 | * And one for the control device | |
81 | */ | |
82 | @@ -1024,6 +1028,16 @@ | |
83 | __nv_enable_pat_support(); | |
84 | } | |
85 | #endif | |
86 | + | |
87 | +#if defined(NVCPU_X86_64) || (defined(NVCPU_X86) && defined(CONFIG_X86_PAE)) | |
88 | + if (boot_cpu_has(X86_FEATURE_NX)) | |
89 | + { | |
90 | + U032 __eax, __edx; | |
91 | + rdmsr(MSR_EFER, __eax, __edx); | |
92 | + if ((__eax & EFER_NX) != 0) | |
93 | + __nv_supported_pte_mask |= _PAGE_NX; | |
94 | + } | |
95 | +#endif | |
96 | ||
97 | return 0; | |
98 |