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Commit | Line | Data |
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e5bb550c PS |
1 | diff -uNr valgrind-3.6.0.orig/coregrind/m_main.c valgrind-3.6.0/coregrind/m_main.c |
2 | --- valgrind-3.6.0.orig/coregrind/m_main.c 2010-10-20 22:19:45.000000000 +0200 | |
3 | +++ valgrind-3.6.0/coregrind/m_main.c 2011-01-17 20:38:26.676472616 +0100 | |
4 | @@ -519,6 +519,8 @@ | |
5 | VG_(clo_vex_control).guest_chase_thresh, 0, 99) {} | |
6 | else if VG_BOOL_CLO(arg, "--vex-guest-chase-cond", | |
7 | VG_(clo_vex_control).guest_chase_cond) {} | |
8 | + else if VG_BOOL_CLO(arg, "--vex-native-cpuid", | |
9 | + VG_(clo_vex_control).iropt_native_cpuid) {} | |
10 | ||
11 | else if VG_INT_CLO(arg, "--log-fd", tmp_log_fd) { | |
12 | log_to = VgLogTo_Fd; | |
13 | diff -uNr valgrind-3.6.0.orig/VEX/priv/guest_amd64_defs.h valgrind-3.6.0/VEX/priv/guest_amd64_defs.h | |
14 | --- valgrind-3.6.0.orig/VEX/priv/guest_amd64_defs.h 2010-10-20 22:19:51.000000000 +0200 | |
15 | +++ valgrind-3.6.0/VEX/priv/guest_amd64_defs.h 2011-01-17 20:38:57.815124615 +0100 | |
16 | @@ -147,6 +147,7 @@ | |
17 | extern void amd64g_dirtyhelper_CPUID_baseline ( VexGuestAMD64State* st ); | |
18 | extern void amd64g_dirtyhelper_CPUID_sse3_and_cx16 ( VexGuestAMD64State* st ); | |
19 | extern void amd64g_dirtyhelper_CPUID_sse42_and_cx16 ( VexGuestAMD64State* st ); | |
20 | +extern void amd64g_dirtyhelper_CPUID_native ( VexGuestAMD64State* st ); | |
21 | ||
22 | extern void amd64g_dirtyhelper_FINIT ( VexGuestAMD64State* ); | |
23 | ||
24 | diff -uNr valgrind-3.6.0.orig/VEX/priv/guest_amd64_helpers.c valgrind-3.6.0/VEX/priv/guest_amd64_helpers.c | |
25 | --- valgrind-3.6.0.orig/VEX/priv/guest_amd64_helpers.c 2010-10-20 22:19:51.000000000 +0200 | |
26 | +++ valgrind-3.6.0/VEX/priv/guest_amd64_helpers.c 2011-01-17 20:36:00.884903903 +0100 | |
27 | @@ -2170,6 +2170,20 @@ | |
28 | } | |
29 | ||
30 | ||
31 | +void amd64g_dirtyhelper_CPUID_native ( VexGuestAMD64State* st ) | |
32 | +{ | |
33 | +# if defined(__x86_64__) | |
34 | + __asm__ __volatile__ ("cpuid" : "=a" (st->guest_RAX), | |
35 | + "=b" (st->guest_RBX), | |
36 | + "=c" (st->guest_RCX), | |
37 | + "=d" (st->guest_RDX) | |
38 | + : "0" (st->guest_RAX), "2" (st->guest_RCX)); | |
39 | +# else | |
40 | +/* do nothing */ | |
41 | +# endif | |
42 | +} | |
43 | + | |
44 | + | |
45 | ULong amd64g_calculate_RCR ( ULong arg, | |
46 | ULong rot_amt, | |
47 | ULong rflags_in, | |
48 | diff -uNr valgrind-3.6.0.orig/VEX/priv/guest_amd64_toIR.c valgrind-3.6.0/VEX/priv/guest_amd64_toIR.c | |
49 | --- valgrind-3.6.0.orig/VEX/priv/guest_amd64_toIR.c 2011-01-17 20:35:34.380376775 +0100 | |
50 | +++ valgrind-3.6.0/VEX/priv/guest_amd64_toIR.c 2011-01-17 20:36:00.891571709 +0100 | |
51 | @@ -17620,7 +17620,11 @@ | |
52 | HChar* fName = NULL; | |
53 | void* fAddr = NULL; | |
54 | if (haveF2orF3(pfx)) goto decode_failure; | |
55 | - if (archinfo->hwcaps == (VEX_HWCAPS_AMD64_SSE3 | |
56 | + if (vex_control.iropt_native_cpuid) { | |
57 | + fName = "amd64g_dirtyhelper_CPUID_native"; | |
58 | + fAddr = &amd64g_dirtyhelper_CPUID_native; | |
59 | + } | |
60 | + else if (archinfo->hwcaps == (VEX_HWCAPS_AMD64_SSE3 | |
61 | |VEX_HWCAPS_AMD64_CX16)) { | |
62 | //fName = "amd64g_dirtyhelper_CPUID_sse3_and_cx16"; | |
63 | //fAddr = &amd64g_dirtyhelper_CPUID_sse3_and_cx16; | |
64 | diff -uNr valgrind-3.6.0.orig/VEX/pub/libvex.h valgrind-3.6.0/VEX/pub/libvex.h | |
65 | --- valgrind-3.6.0.orig/VEX/pub/libvex.h 2010-10-20 22:19:52.000000000 +0200 | |
66 | +++ valgrind-3.6.0/VEX/pub/libvex.h 2011-01-17 20:41:02.906490947 +0100 | |
67 | @@ -60,7 +60,6 @@ | |
68 | } | |
69 | VexArch; | |
70 | ||
71 | - | |
72 | /* For a given architecture, these specify extra capabilities beyond | |
73 | the minimum supported (baseline) capabilities. They may be OR'd | |
74 | together, although some combinations don't make sense. (eg, SSE2 | |
75 | @@ -270,6 +269,8 @@ | |
76 | /* EXPERIMENTAL: chase across conditional branches? Not all | |
77 | front ends honour this. Default: NO. */ | |
78 | Bool guest_chase_cond; | |
79 | + /* For x86 and amd64 allow the use of native cpuid inst */ | |
80 | + Int iropt_native_cpuid; | |
81 | } | |
82 | VexControl; | |
83 |