projects / packages / openssl.git / blame
| Commit | Line | Data |
|---|---|---|
| 6bd2fbde JR |
1 | UpstreamStatus: Pending |
| 2 | ||
| 3 | Received from H J Liu @ Intel | |
| 4 | Make the assembly syntax compatible with x32 gcc. Othewise x32 gcc throws errors. | |
| 5 | Signed-Off-By: Nitin A Kamble <nitin.a.kamble@intel.com> 2011/07/13 | |
| 6 | ||
| 7 | ported the patch to the 1.0.0e version | |
| 8 | Signed-Off-By: Nitin A Kamble <nitin.a.kamble@intel.com> 2011/12/01 | |
| fc48a532 ER |
9 | @@ -362,6 +362,7 @@ |
| 10 | "linux-ia64-ecc","ecc:-DL_ENDIAN $ENV{OPTFLAGS} -Wall -no_cpprt::-D_REENTRANT::-ldl:SIXTY_FOUR_BIT_LONG RC4_CHUNK DES_INT:${ia64_asm}:dlfcn:linux-shared:-fPIC::.so.\$(SHLIB_MAJOR).\$(SHLIB_MINOR)", | |
| 11 | "linux-ia64-icc","icc:-DL_ENDIAN $ENV{OPTFLAGS} -Wall -no_cpprt::-D_REENTRANT::-ldl:SIXTY_FOUR_BIT_LONG RC4_CHUNK DES_RISC1 DES_INT:${ia64_asm}:dlfcn:linux-shared:-fPIC::.so.\$(SHLIB_MAJOR).\$(SHLIB_MINOR)", | |
| 12 | "linux-x86_64", "gcc:-m64 -DL_ENDIAN $ENV{OPTFLAGS} -Wall::-D_REENTRANT::-ldl:SIXTY_FOUR_BIT_LONG RC4_CHUNK DES_INT DES_UNROLL:${x86_64_asm}:elf:dlfcn:linux-shared:-fPIC:-m64:.so.\$(SHLIB_MAJOR).\$(SHLIB_MINOR):::64", | |
| 13 | +"linux-x32", "gcc:-mx32 -DL_ENDIAN $ENV{OPTFLAGS} -Wall -DMD32_REG_T=int::-D_REENTRANT::-ldl:SIXTY_FOUR_BIT RC4_CHUNK DES_INT DES_UNROLL:${x86_64_asm}:elf:dlfcn:linux-shared:-fPIC:-mx32:.so.\$(SHLIB_MAJOR).\$(SHLIB_MINOR):::x32", | |
| 14 | "linux64-s390x", "gcc:-m64 -DB_ENDIAN $ENV{OPTFLAGS} -Wall::-D_REENTRANT::-ldl:SIXTY_FOUR_BIT_LONG RC4_CHAR RC4_CHUNK DES_INT DES_UNROLL:${s390x_asm}:64:dlfcn:linux-shared:-fPIC:-m64:.so.\$(SHLIB_MAJOR).\$(SHLIB_MINOR):::64", | |
| 6bd2fbde JR |
15 | #### So called "highgprs" target for z/Architecture CPUs |
| 16 | # "Highgprs" is kernel feature first implemented in Linux 2.6.32, see | |
| fc48a532 ER |
17 | --- openssl-1.0.1m/crypto/bn/asm/x86_64-gcc.c~ 2015-03-20 13:57:28.000000000 +0200 |
| 18 | +++ openssl-1.0.1m/crypto/bn/asm/x86_64-gcc.c 2015-03-20 13:58:12.103076972 +0200 | |
| 19 | @@ -211,9 +211,9 @@ | |
| 6bd2fbde | 20 | |
| fc48a532 ER |
21 | asm volatile (" subq %2,%2 \n" |
| 22 | ".p2align 4 \n" | |
| 23 | - "1: movq (%4,%2,8),%0 \n" | |
| 24 | - " adcq (%5,%2,8),%0 \n" | |
| 25 | - " movq %0,(%3,%2,8) \n" | |
| 26 | + "1: movq (%q4,%2,8),%0 \n" | |
| 27 | + " adcq (%q5,%2,8),%0 \n" | |
| 28 | + " movq %0,(%q3,%2,8) \n" | |
| 29 | " leaq 1(%2),%2 \n" | |
| 30 | " loop 1b \n" | |
| 31 | " sbbq %0,%0 \n":"=&a" (ret), "+c"(n), | |
| 32 | @@ -235,9 +235,9 @@ | |
| 33 | ||
| 34 | asm volatile (" subq %2,%2 \n" | |
| 35 | ".p2align 4 \n" | |
| 36 | - "1: movq (%4,%2,8),%0 \n" | |
| 37 | - " sbbq (%5,%2,8),%0 \n" | |
| 38 | - " movq %0,(%3,%2,8) \n" | |
| 39 | + "1: movq (%q4,%2,8),%0 \n" | |
| 40 | + " sbbq (%q5,%2,8),%0 \n" | |
| 41 | + " movq %0,(%q3,%2,8) \n" | |
| 42 | " leaq 1(%2),%2 \n" | |
| 43 | " loop 1b \n" | |
| 44 | " sbbq %0,%0 \n":"=&a" (ret), "+c"(n), |