From 99c6565bad5c39e21a6fb94e18467b5229c46425 Mon Sep 17 00:00:00 2001 From: Jan Palus Date: Sun, 5 Sep 2021 00:43:52 +0200 Subject: [PATCH] add support for turris omnia - include patch for atheros chip initialization failure from: https://lore.kernel.org/linux-pci/20210505163357.16012-1-pali@kernel.org/ --- atheros-disallow-retrain-nongen1-pcie.patch | 287 ++++++++++++++++++++ kernel-arm.config | 53 +++- kernel.spec | 2 + 3 files changed, 341 insertions(+), 1 deletion(-) create mode 100644 atheros-disallow-retrain-nongen1-pcie.patch diff --git a/atheros-disallow-retrain-nongen1-pcie.patch b/atheros-disallow-retrain-nongen1-pcie.patch new file mode 100644 index 00000000..54746c83 --- /dev/null +++ b/atheros-disallow-retrain-nongen1-pcie.patch @@ -0,0 +1,287 @@ +From mboxrd@z Thu Jan 1 00:00:00 1970 +Return-Path: +X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on + aws-us-west-2-korg-lkml-1.web.codeaurora.org +X-Spam-Level: +X-Spam-Status: No, score=-19.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, + DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, + MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT + autolearn=unavailable autolearn_force=no version=3.4.0 +Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) + by smtp.lore.kernel.org (Postfix) with ESMTP id 5293AC433ED + for ; Wed, 5 May 2021 16:46:38 +0000 (UTC) +Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) + by mail.kernel.org (Postfix) with ESMTP id 336FB613BE + for ; Wed, 5 May 2021 16:46:38 +0000 (UTC) +Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand + id S236089AbhEEQrX (ORCPT ); + Wed, 5 May 2021 12:47:23 -0400 +Received: from mail.kernel.org ([198.145.29.99]:39944 "EHLO mail.kernel.org" + rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP + id S235175AbhEEQn0 (ORCPT ); + Wed, 5 May 2021 12:43:26 -0400 +Received: by mail.kernel.org (Postfix) with ESMTPSA id 7196361879; + Wed, 5 May 2021 16:35:00 +0000 (UTC) +DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; + s=k20201202; t=1620232500; + bh=fPfmCTyAQD8PT6TZkO8THxra9rEY81AdAkfBo+IZ5tU=; + h=From:To:Cc:Subject:Date:In-Reply-To:References:From; + b=GGQEKTJt6sQkhGf+9veu8zkPNAFhEHpim85V7tVqJPqB4sraqNoIP0BWX1keInmv1 + ZKmmiJG5OUg5J9Es8W0iw0yQNPVmz34gbFy4b/BRUc7EKu46CVXeOvY7+dX1ivCaHW + ikKmjPxAXiMqLH3vRNqoFgDWvRRAhatZ2B9XuscrV7BPfXufja4ykhb29irvNL2akj + Hc4a6H7NHXnuVMvnnogfrZDleFUOYf/BVnamTiRmKRbnoBOWJPt6XCS+yoB5gVy3H7 + /pzDotZdZ51NWdc/HzZfBT+40TkFWyD6fV5hW9V0Yi5BVVD/2LZDvbLecJkOQJfTqD + +rF2SH3dN0A9Q== +Received: by pali.im (Postfix) + id 09BEF79D; Wed, 5 May 2021 18:34:57 +0200 (CEST) +From: =?UTF-8?q?Pali=20Roh=C3=A1r?= +To: Bjorn Helgaas , + Kalle Valo , + =?UTF-8?q?Toke=20H=C3=B8iland-J=C3=B8rgensen?= , + =?UTF-8?q?Marek=20Beh=C3=BAn?= , + =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= +Cc: vtolkm@gmail.com, Rob Herring , + Ilias Apalodimas , + Thomas Petazzoni , + linux-pci@vger.kernel.org, ath10k@lists.infradead.org, + linux-wireless@vger.kernel.org, linux-kernel@vger.kernel.org +Subject: [PATCH v3] PCI: Disallow retraining link for Atheros chips on non-Gen1 PCIe bridges +Date: Wed, 5 May 2021 18:33:57 +0200 +Message-Id: <20210505163357.16012-1-pali@kernel.org> +X-Mailer: git-send-email 2.20.1 +In-Reply-To: <20210326124326.21163-1-pali@kernel.org> +References: <20210326124326.21163-1-pali@kernel.org> +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit +Precedence: bulk +List-ID: +X-Mailing-List: linux-pci@vger.kernel.org + +Atheros AR9xxx and QCA9xxx chips have behaviour issues not only after a +bus reset, but also after doing retrain link, if PCIe bridge is not in +GEN1 mode (at 2.5 GT/s speed): + +- QCA9880 and QCA9890 chips throw a Link Down event and completely + disappear from the bus and their config space is not accessible + afterwards. + +- QCA9377 chip throws a Link Down event followed by Link Up event, the + config space is accessible and PCI device ID is correct. But trying to + access chip's I/O space causes Uncorrected (Non-Fatal) AER error, + followed by Synchronous external abort 96000210 and Segmentation fault + of insmod while loading ath10k_pci.ko module. + +- AR9390 chip throws a Link Down event followed by Link Up event, config + space is accessible, but contains nonsense values. PCI device ID is + 0xABCD which indicates HW bug that chip itself was not able to read + values from internal EEPROM/OTP. + +- AR9287 chip throws also Link Down and Link Up events, also has + accessible config space containing correct values. But ath9k driver + fails to initialize card from this state as it is unable to access HW + registers. This also indicates that the chip iself is not able to read + values from internal EEPROM/OTP. + +These issues related to PCI device ID 0xABCD and to reading internal +EEPROM/OTP were previously discussed at ath9k-devel mailing list in +following thread: + + https://www.mail-archive.com/ath9k-devel@lists.ath9k.org/msg07529.html + +After experiments we've come up with a solution: it seems that Retrain +link can be called only when using GEN1 PCIe bridge or when PCIe bridge +link speed is forced to 2.5 GT/s. Applying this workaround fixes all +mentioned cards. + +This issue was reproduced with more cards: +- Compex WLE900VX (QCA9880 based / device ID 0x003c) +- QCNFA435 (QCA9377 based / device ID 0x0042) +- Compex WLE200NX (AR9287 based / device ID 0x002e) +- "noname" card (QCA9890 based / device ID 0x003c) +- Wistron NKR-DNXAH1 (AR9390 based / device ID 0x0030) +on Armada 385 with pci-mvebu.c driver and also on Armada 3720 with +pci-aardvark.c driver. + +To workaround this issue, this change introduces a new PCI quirk called +PCI_DEV_FLAGS_NO_RETRAIN_LINK_WHEN_NOT_GEN1, which is enabled for all +Atheros chips with PCI_DEV_FLAGS_NO_BUS_RESET quirk, and also for Atheros +chip AR9287. + +When this quirk is set, kernel disallows triggering PCI_EXP_LNKCTL_RL +bit in config space of PCIe Bridge in the case when PCIe Bridge is +capable of higher speed than 2.5 GT/s and this higher speed is already +allowed. When PCIe Bridge has accessible LNKCTL2 register, we try to +force target link speed to 2.5 GT/s. After this change it is possible +to trigger PCI_EXP_LNKCTL_RL bit without issues. + +Currently only PCIe ASPM kernel code triggers this PCI_EXP_LNKCTL_RL bit, +so quirk check is added only into pcie/aspm.c file. + +Signed-off-by: Pali Rohár +Reported-by: Toke Høiland-Jørgensen +Tested-by: Toke Høiland-Jørgensen +Tested-by: Marek Behún +BugLink: https://lore.kernel.org/linux-pci/87h7l8axqp.fsf@toke.dk/ +BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=84821 +BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=192441 +BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=209833 +Cc: stable@vger.kernel.org # c80851f6ce63a ("PCI: Add PCI_EXP_LNKCTL2_TLS* macros") + +--- +Changes since v1: +* Move whole quirk code into pcie_downgrade_link_to_gen1() function +* Reformat to 80 chars per line where possible +* Add quirk also for cards with AR9287 chip (PCI ID 0x002e) +* Extend commit message description and add information about 0xABCD + +Changes since v2: +* Add quirk also for Atheros QCA9377 chip +--- + drivers/pci/pcie/aspm.c | 44 +++++++++++++++++++++++++++++++++++++++++ + drivers/pci/quirks.c | 39 ++++++++++++++++++++++++++++-------- + include/linux/pci.h | 2 ++ + 3 files changed, 77 insertions(+), 8 deletions(-) + +diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c +index ac0557a305af..729b0389562b 100644 +--- a/drivers/pci/pcie/aspm.c ++++ b/drivers/pci/pcie/aspm.c +@@ -192,12 +192,56 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) + link->clkpm_disable = blacklist ? 1 : 0; + } + ++static int pcie_downgrade_link_to_gen1(struct pci_dev *parent) ++{ ++ u16 reg16; ++ u32 reg32; ++ int ret; ++ ++ /* Check if link is capable of higher speed than 2.5 GT/s */ ++ pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, ®32); ++ if ((reg32 & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB) ++ return 0; ++ ++ /* Check if link speed can be downgraded to 2.5 GT/s */ ++ pcie_capability_read_dword(parent, PCI_EXP_LNKCAP2, ®32); ++ if (!(reg32 & PCI_EXP_LNKCAP2_SLS_2_5GB)) { ++ pci_err(parent, "ASPM: Bridge does not support changing Link Speed to 2.5 GT/s\n"); ++ return -EOPNOTSUPP; ++ } ++ ++ /* Force link speed to 2.5 GT/s */ ++ ret = pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL2, ++ PCI_EXP_LNKCTL2_TLS, ++ PCI_EXP_LNKCTL2_TLS_2_5GT); ++ if (!ret) { ++ /* Verify that new value was really set */ ++ pcie_capability_read_word(parent, PCI_EXP_LNKCTL2, ®16); ++ if ((reg16 & PCI_EXP_LNKCTL2_TLS) != PCI_EXP_LNKCTL2_TLS_2_5GT) ++ ret = -EINVAL; ++ } ++ ++ if (ret) { ++ pci_err(parent, "ASPM: Changing Target Link Speed to 2.5 GT/s failed: %d\n", ret); ++ return ret; ++ } ++ ++ pci_info(parent, "ASPM: Target Link Speed changed to 2.5 GT/s due to quirk\n"); ++ return 0; ++} ++ + static bool pcie_retrain_link(struct pcie_link_state *link) + { + struct pci_dev *parent = link->pdev; + unsigned long end_jiffies; + u16 reg16; + ++ if ((link->downstream->dev_flags & PCI_DEV_FLAGS_NO_RETRAIN_LINK_WHEN_NOT_GEN1) && ++ pcie_downgrade_link_to_gen1(parent)) { ++ pci_err(parent, "ASPM: Retrain Link at higher speed is disallowed by quirk\n"); ++ return false; ++ } ++ + pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); + reg16 |= PCI_EXP_LNKCTL_RL; + pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16); +diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c +index 653660e3ba9e..4999ad9d08b8 100644 +--- a/drivers/pci/quirks.c ++++ b/drivers/pci/quirks.c +@@ -3553,30 +3553,53 @@ static void mellanox_check_broken_intx_masking(struct pci_dev *pdev) + dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; + } + ++static void quirk_no_bus_reset_and_no_retrain_link(struct pci_dev *dev) ++{ ++ dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET | ++ PCI_DEV_FLAGS_NO_RETRAIN_LINK_WHEN_NOT_GEN1; ++} ++ + /* + * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be + * prevented for those affected devices. + */ + static void quirk_nvidia_no_bus_reset(struct pci_dev *dev) + { + if ((dev->device & 0xffc0) == 0x2340) + quirk_no_bus_reset(dev); + } + DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, + quirk_nvidia_no_bus_reset); + + /* +- * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. ++ * Atheros AR9xxx and QCA9xxx chips do not behave after a bus reset and also ++ * after retrain link when PCIe bridge is not in GEN1 mode at 2.5 GT/s speed. + * The device will throw a Link Down error on AER-capable systems and + * regardless of AER, config space of the device is never accessible again + * and typically causes the system to hang or reset when access is attempted. ++ * Or if config space is accessible again then it contains only dummy values ++ * like fixed PCI device ID 0xABCD or values not initialized at all. ++ * Retrain link can be called only when using GEN1 PCIe bridge or when ++ * PCIe bridge has forced link speed to 2.5 GT/s via PCI_EXP_LNKCTL2 register. ++ * To reset these cards it is required to do PCIe Warm Reset via PERST# pin. + * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/ ++ * https://lore.kernel.org/r/87h7l8axqp.fsf@toke.dk/ ++ * https://www.mail-archive.com/ath9k-devel@lists.ath9k.org/msg07529.html + */ +-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); +-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); +-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); +-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); +-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x002e, ++ quirk_no_bus_reset_and_no_retrain_link); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, ++ quirk_no_bus_reset_and_no_retrain_link); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, ++ quirk_no_bus_reset_and_no_retrain_link); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, ++ quirk_no_bus_reset_and_no_retrain_link); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, ++ quirk_no_bus_reset_and_no_retrain_link); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, ++ quirk_no_bus_reset_and_no_retrain_link); ++DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0042, ++ quirk_no_bus_reset_and_no_retrain_link); + + /* + * Root port on some Cavium CN8xxx chips do not successfully complete a bus +diff --git a/include/linux/pci.h b/include/linux/pci.h +index 86c799c97b77..fdbf7254e4ab 100644 +--- a/include/linux/pci.h ++++ b/include/linux/pci.h +@@ -227,6 +227,8 @@ enum pci_dev_flags { + PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), + /* Don't use Relaxed Ordering for TLPs directed at this device */ + PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), ++ /* Don't Retrain Link for device when bridge is not in GEN1 mode */ ++ PCI_DEV_FLAGS_NO_RETRAIN_LINK_WHEN_NOT_GEN1 = (__force pci_dev_flags_t) (1 << 12), + }; + + enum pci_irq_reroute_variant { +-- +2.20.1 + + diff --git a/kernel-arm.config b/kernel-arm.config index c72f646c..1613d5b5 100644 --- a/kernel-arm.config +++ b/kernel-arm.config @@ -304,7 +304,13 @@ ARCH_MSTARV7 arm=n #- #- *** FILE: arch/arm/mach-mvebu/Kconfig *** #- -ARCH_MVEBU arm=n +ARCH_MVEBU arm=y +MACH_ARMADA_370 arm=n +MACH_ARMADA_375 arm=n +MACH_ARMADA_38X arm=y +MACH_ARMADA_39X arm=n +MACH_ARMADA_XP arm=n +MACH_DOVE arm=n #- #- *** FILE: arch/arm/mach-npcm/Kconfig *** @@ -433,6 +439,7 @@ ARCH_ZYNQ arm=n ARM_LPAE arm=n ARM_THUMBEE arm=n SWP_EMULATE arm=n +CPU_BIG_ENDIAN arm=n CPU_ICACHE_DISABLE arm=n CPU_ICACHE_MISMATCH_WORKAROUND arm=y CPU_DCACHE_DISABLE arm=n @@ -440,6 +447,8 @@ CPU_BPREDICT_DISABLE arm=n KUSER_HELPERS arm=y VDSO arm=y DMA_CACHE_RWFO arm=y +CACHE_FEROCEON_L2 arm=y +CACHE_FEROCEON_L2_WRITETHROUGH arm=n CACHE_L2X0 arm=y CACHE_L2X0_PMU arm=n PL310_ERRATA_588369 arm=y @@ -461,6 +470,8 @@ CPUFREQ_DT arm=m #- #- *** FILE: drivers/cpufreq/Kconfig.arm *** #- +ARM_ARMADA_37XX_CPUFREQ arm=m +ARM_ARMADA_8K_CPUFREQ arm=m ARM_SCPI_CPUFREQ arm=m ARM_RASPBERRYPI_CPUFREQ arm=m @@ -470,6 +481,7 @@ ARM_RASPBERRYPI_CPUFREQ arm=m ARM_CPUIDLE arm=y ARM_PSCI_CPUIDLE arm=n ARM_HIGHBANK_CPUIDLE arm=n +ARM_MVEBU_V7_CPUIDLE arm=y #- #- *** FILE: drivers/firmware/Kconfig *** @@ -477,6 +489,7 @@ ARM_HIGHBANK_CPUIDLE arm=n ARM_SCMI_PROTOCOL arm=n RASPBERRYPI_FIRMWARE arm=y TRUSTED_FOUNDATIONS arm=n +TURRIS_MOX_RWTM arm=m #- file drivers/firmware/broadcom/Kconfig goes here #- file drivers/firmware/google/Kconfig goes here #- file drivers/firmware/efi/Kconfig goes here @@ -502,6 +515,7 @@ ARM_SMCCC_SOC_ID arm=y #- ADI_AXI_ADC arm=m AHCI_CEVA arm=m +AHCI_MVEBU arm=m AHCI_QORIQ arm=m AK8974 arm=m ALTERA_PR_IP_CORE_PLAT arm=m @@ -514,6 +528,9 @@ ARCH_SOCFPGA arm=n ARCH_TANGO arm=n ARCH_ZX arm=n ARCX_ANYBUS_CONTROLLER arm=m +ARMADA_37XX_RWTM_MBOX arm=m +ARMADA_37XX_WATCHDOG arm=m +ARMADA_THERMAL arm=m ARM_ARCH_TIMER_EVTSTREAM arm=y ARM_CCI400_PMU arm=y ARM_CCI5xx_PMU arm=y @@ -580,6 +597,7 @@ CROS_EC_RPMSG arm=m CROS_EC_VBC arm=m CRYPTO_AEGIS128_SIMD arm=y CRYPTO_DEV_CCREE arm=m +CRYPTO_DEV_MARVELL_CESA arm=m CS89x0_PLATFORM arm=n DA9062_THERMAL arm=m DAX arm=m @@ -729,6 +747,7 @@ DRM_VC4 arm=m DRM_VC4_HDMI_CEC arm=y DVB_C8SECTPFE arm=m DW_AXI_DMAC arm=m +EDAC_ARMADA_XP arm=y ENVELOPE_DETECTOR arm=m ETHERNET arm=y EZCHIP_NPS_MANAGEMENT_ENET arm=m @@ -790,6 +809,7 @@ HVC_DCC arm=n HW_RANDOM_BCM2835 arm=m HW_RANDOM_CCTRNG arm=m HW_RANDOM_IPROC_RNG200 arm=m +HW_RANDOM_OMAP arm=m HW_RANDOM_OPTEE arm=m I2C_ARB_GPIO_CHALLENGE arm=m I2C_BCM2835 arm=m @@ -799,7 +819,10 @@ I2C_FSI arm=m I2C_HID_OF arm=m I2C_HID_OF_GOODIX arm=m I2C_MUX_GPMUX arm=m +I2C_MV64XXX arm=m I2C_NOMADIK arm=m +I2C_PXA arm=m +I2C_PXA_SLAVE arm=y I2C_RK3X arm=m IIO_MUX arm=m IIO_RESCALE arm=m @@ -845,6 +868,7 @@ LEDS_PM8058 arm=m LEDS_RT4505 arm=m LEDS_SPI_BYTE arm=m LEDS_SYSCON arm=y +LEDS_TURRIS_OMNIA arm=m LITEX_SOC_CONTROLLER arm=m LITEX_SUBREG_SIZE arm=4 MAILBOX_TEST arm=m @@ -888,6 +912,7 @@ MMC_DW_HI3798CV200 arm=m MMC_DW_K3 arm=m MMC_DW_PCI arm=m MMC_DW_PLTFM arm=m +MMC_MVSDIO arm=m MMC_SDHCI_AM654 arm=m MMC_SDHCI_CADENCE arm=m MMC_SDHCI_IPROC arm=m @@ -906,11 +931,19 @@ MTD_LPDDR2_NVM arm=m MTD_NAND_BRCMNAND arm=m MTD_NAND_CADENCE arm=m MTD_NAND_INTEL_LGM arm=m +MTD_NAND_MARVELL arm=m +MTD_NAND_ORION arm=m MTD_PHYSMAP_GEMINI arm=n MTD_PHYSMAP_IXP4XX arm=n MTD_PHYSMAP_VERSATILE arm=n MTD_QINFO_PROBE arm=m MUX_MMIO arm=m +MV643XX_ETH arm=m +MVEBU_DEVBUS arm=y +MVNETA arm=m +MVNETA_BM_ENABLE arm=m +MVPP2 arm=m +MV_XOR arm=y NBPFAXI_DMA arm=m NET_VENDOR_BROADCOM arm=y NET_VENDOR_CHELSIO arm=y @@ -938,9 +971,11 @@ OMAP5_DSS_HDMI arm=n OPROFILE arm=m OPTEE arm=m OPTEE_SHM_NUM_PRIV_PAGES arm=1 +ORION_WATCHDOG arm=m PACKING arm=y PCIE_ALTERA arm=m PCIE_ALTERA_MSI arm=m +PCIE_ARMADA_8K arm=y PCIE_BRCMSTB arm=m PCIE_CADENCE_PLAT_EP arm=n PCIE_CADENCE_PLAT_HOST arm=n @@ -952,6 +987,7 @@ PCI_J721E_EP arm=n PCI_J721E_HOST arm=n PCI_LAYERSCAPE arm=n PCI_LAYERSCAPE_EP arm=n +PCI_MVEBU arm=y PCI_V3_SEMI arm=n PHY_CADENCE_DPHY arm=m PHY_CADENCE_SALVO arm=m @@ -960,6 +996,11 @@ PHY_CADENCE_TORRENT arm=m PHY_FSL_IMX8MQ_USB arm=m PHY_MAPPHONE_MDM6600 arm=m PHY_MIXEL_MIPI_DPHY arm=m +PHY_MVEBU_A3700_COMPHY arm=m +PHY_MVEBU_A3700_UTMI arm=m +PHY_MVEBU_A38X_COMPHY arm=m +PHY_MVEBU_CP110_COMPHY arm=m +PHY_MVEBU_CP110_UTMI arm=m PHY_OCELOT_SERDES arm=m PID_IN_CONTEXTIDR arm=n PINCTRL arm=y @@ -978,7 +1019,9 @@ POWER_RESET_BRCMKONA arm=n POWER_RESET_BRCMSTB arm=n POWER_RESET_GPIO arm=y POWER_RESET_GPIO_RESTART arm=y +POWER_RESET_LINKSTATION arm=m POWER_RESET_LTC2952 arm=n +POWER_RESET_QNAP arm=y POWER_RESET_REGULATOR arm=n POWER_RESET_SYSCON arm=y POWER_RESET_SYSCON_POWEROFF arm=y @@ -1028,12 +1071,14 @@ RESET_INTEL_GW arm=n RESET_RASPBERRYPI arm=m RN5T618_ADC arm=m RN5T618_POWER arm=m +RTC_DRV_ARMADA38X arm=m RTC_DRV_CADENCE arm=m RTC_DRV_CPCAP arm=m RTC_DRV_GOLDFISH arm=m RTC_DRV_HYM8563 arm=m RTC_DRV_ISL12026 arm=m RTC_DRV_MAX77686 arm=m +RTC_DRV_MV arm=m RTC_DRV_NTXEC arm=m RTC_DRV_PL030 arm=m RTC_DRV_PL031 arm=m @@ -1071,6 +1116,8 @@ SND_ARMAACI arm=m SND_AUDIO_GRAPH_CARD arm=m SND_BCM2835 arm=m SND_BCM2835_SOC_I2S arm=m +SND_KIRKWOOD_SOC arm=m +SND_KIRKWOOD_SOC_ARMADA370_DB arm=m SND_RPI_WM8804_SOUNDCARD arm=m SND_SOC_CPCAP arm=m SND_SOC_CX2072X arm=m @@ -1085,6 +1132,7 @@ SND_SOC_RT711_SDCA_SDW arm=m SND_SOC_RT715_SDCA_SDW arm=m SND_SOC_SOF_OF arm=m SOC_BRCMSTB arm=n +SPI_ARMADA_3700 arm=m SPI_BCM2835 arm=m SPI_BCM2835AUX arm=m SPI_BCM_QSPI arm=m @@ -1092,6 +1140,7 @@ SPI_CADENCE_QUADSPI arm=m SPI_FSI arm=m SPI_FSL_SPI arm=m SPI_MEM arm=y +SPI_ORION arm=m SPI_PL022 arm=m STACKTRACE arm=y STAGING_BOARD arm=n @@ -1117,11 +1166,13 @@ USB_DWC2_HOST arm=n USB_DWC2_PCI arm=m USB_DWC2_PERIPHERAL arm=n USB_DWC3_OF_SIMPLE arm=m +USB_EHCI_HCD_ORION arm=m USB_EHCI_HCD_PLATFORM arm=m USB_GADGET_XILINX arm=m USB_HCD_SSB arm=m USB_SNP_UDC_PLAT arm=m USB_ULPI arm=y +USB_XHCI_MVEBU arm=m USB_XHCI_PLATFORM arm=m VEXPRESS_CONFIG arm=m VF610_ADC arm=m diff --git a/kernel.spec b/kernel.spec index 6e1f28e5..515cde0a 100644 --- a/kernel.spec +++ b/kernel.spec @@ -219,6 +219,7 @@ Patch7000: kernel-inittmpfs.patch # ARM only Patch8000: rpi-wm8804.patch Patch8001: kernel-pinebook-pro.patch +Patch8002: atheros-disallow-retrain-nongen1-pcie.patch # Do not remove this line, please. It is easier for me to uncomment two lines, then patch # kernel.spec every time. @@ -687,6 +688,7 @@ cd linux-%{basever} %ifarch %{arm} aarch64 %patch8000 -p1 %patch8001 -p1 +%patch8002 -p1 %endif %if %{with rt} -- 2.43.0