--- linux-2.4.20-orig/drivers/ide/ide-cd.h	2002-12-10 17:46:28 +0900
+++ linux-2.4.20/drivers/ide/ide-cd.h	2003-05-16 00:59:53 +0900
@@ -437,7 +437,7 @@
 
 	byte     curlba[3];
 	byte     nslots;
-	__u8 short slot_tablelen;
+	__u8     slot_tablelen;
 };
 
 
--- linux-2.4.20-orig/net/core/rtnetlink.c	2002-12-09 16:38:46 +0900
+++ linux-2.4.20/net/core/rtnetlink.c	2003-05-16 01:31:20 +0900
@@ -394,7 +394,7 @@
  * Malformed skbs with wrong lengths of messages are discarded silently.
  */
 
-extern __inline__ int rtnetlink_rcv_skb(struct sk_buff *skb)
+__inline__ int rtnetlink_rcv_skb(struct sk_buff *skb)
 {
 	int err;
 	struct nlmsghdr * nlh;
--- linux-2.4.20/drivers/atm/ambassador.c.orig	Thu Sep 13 22:21:32 2001
+++ linux-2.4.20/drivers/atm/ambassador.c	Wed Jun 11 08:42:37 2003
@@ -290,12 +290,12 @@
 /********** microcode **********/
 
 #ifdef AMB_NEW_MICROCODE
-#define UCODE(x) UCODE1(atmsar12.,x)
+#define UCODE(x) UCODE1(atmsar12,x)
 #else
-#define UCODE(x) UCODE1(atmsar11.,x)
+#define UCODE(x) UCODE1(atmsar11,x)
 #endif
 #define UCODE2(x) #x
-#define UCODE1(x,y) UCODE2(x ## y)
+#define UCODE1(x,y) UCODE2(x.y)
 
 static u32 __initdata ucode_start = 
 #include UCODE(start)
--- linux-2.4.20/include/linux/mtd/nftl.h.org	Fri Jun  6 15:46:54 2003
+++ linux-2.4.20/include/linux/mtd/nftl.h	Wed Jun 11 13:49:12 2003
@@ -97,7 +97,7 @@
 	__u16 lastEUN;                  /* should be suppressed */
 	__u16 numfreeEUNs;
 	__u16 LastFreeEUN; 		/* To speed up finding a free EUN */
-	__u32 long nr_sects;
+	__u32 nr_sects;
 	int head,sect,cyl;
 	__u16 *EUNtable; 		/* [numvunits]: First EUN for each virtual unit  */
 	__u16 *ReplUnitTable; 		/* [numEUNs]: ReplUnitNumber for each */
diff -Nur --exclude='*.orig' --exclude='*.o' linux-2.4.20.old/drivers/net/fealnx.c linux-2.4.20/drivers/net/fealnx.c
--- linux-2.4.20.old/drivers/net/fealnx.c	Mon Jun 16 13:16:08 2003
+++ linux-2.4.20/drivers/net/fealnx.c	Mon Jun 16 13:16:09 2003
@@ -1198,7 +1198,7 @@
 		printk("\n");
 	}
 
-	   + dev->if_port = np->default_port;
+	dev->if_port = np->default_port;
 	/* Reinit. Gross */
 
 	/* Reset the chip's Tx and Rx processes. */
diff -Nur --exclude='*.orig' --exclude='*.o' linux-2.4.20.old/drivers/net/irda/ma600.c linux-2.4.20/drivers/net/irda/ma600.c
--- linux-2.4.20.old/drivers/net/irda/ma600.c	Mon Jun 16 13:16:08 2003
+++ linux-2.4.20/drivers/net/irda/ma600.c	Mon Jun 16 13:16:09 2003
@@ -47,9 +47,9 @@
 	#undef ASSERT(expr, func)
 	#define ASSERT(expr, func) \
 	if(!(expr)) { \
-	        printk( "Assertion failed! %s,%s,%s,line=%d\n",\
-        	#expr,__FILE__,__FUNCTION__,__LINE__); \
-	        ##func}
+	        printk( "Assertion failed! %s,%s,line=%d\n",\
+        	__FILE__,__FUNCTION__,__LINE__); \
+		}
 #endif
 
 /* convert hex value to ascii hex */
diff -Nur --exclude='*.orig' --exclude='*.o' linux-2.4.20.old/drivers/video/controlfb.c linux-2.4.20/drivers/video/controlfb.c
--- linux-2.4.20.old/drivers/video/controlfb.c	Mon Jun 16 13:16:08 2003
+++ linux-2.4.20/drivers/video/controlfb.c	Mon Jun 16 13:16:09 2003
@@ -132,7 +132,7 @@
 };
 
 /* control register access macro */
-#define CNTRL_REG(INFO,REG) (&(((INFO)->control_regs-> ## REG).r))
+#define CNTRL_REG(INFO,REG) (&(((INFO)->control_regs-> REG).r))
 
 
 /******************** Prototypes for exported functions ********************/
diff -Nur --exclude='*.orig' --exclude='*.o' linux-2.4.20.old/include/asm-ppc/unistd.h linux-2.4.20/include/asm-ppc/unistd.h
--- linux-2.4.20.old/include/asm-ppc/unistd.h	Mon Jun 16 13:16:08 2003
+++ linux-2.4.20/include/asm-ppc/unistd.h	Mon Jun 16 13:16:09 2003
@@ -250,7 +250,7 @@
 	       (type) __sc_ret
 
 #define __syscall_clobbers \
-	"r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12"
+	"r6", "r7", "r8", "r9", "r10", "r11", "r12"
 
 #define _syscall0(type,name)						\
 type name(void)								\
diff -Nur --exclude='*.orig' --exclude='*.o' linux-2.4.20.old/drivers/scsi/aic7xxx/aic79xx_osm.c linux-2.4.20/drivers/scsi/aic7xxx/aic79xx_osm.c
--- linux-2.4.20.old/drivers/scsi/aic7xxx/aic79xx_osm.c	Mon Jun 16 13:16:08 2003
+++ linux-2.4.20/drivers/scsi/aic7xxx/aic79xx_osm.c	Mon Jun 16 13:26:12 2003
@@ -336,31 +336,31 @@
 MODULE_LICENSE("Dual BSD/GPL");
 #endif
 MODULE_PARM(aic79xx, "s");
-MODULE_PARM_DESC(aic79xx, "period delimited, options string.
-	verbose			Enable verbose/diagnostic logging
-	debug			Bitmask of debug values to enable
-	no_reset		Supress initial bus resets
-	extended		Enable extended geometry on all controllers
-	periodic_otag		Send an ordered tagged transaction periodically
-				to prevent tag starvation.  This may be
-				required by some older disk drives/RAID arrays. 
-	reverse_scan		Sort PCI devices highest Bus/Slot to lowest
-	tag_info:<tag_str>	Set per-target tag depth
-	rd_strm:<rd_strm_masks> Set per-target read streaming setting.
-	seltime:<int>		Selection Timeout(0/256ms,1/128ms,2/64ms,3/32ms)
-
-	Sample /etc/modules.conf line:
-		Enable verbose logging
-		Set tag depth on Controller 2/Target 2 to 10 tags
-		Shorten the selection timeout to 128ms from its default of 256
-
-	options aic79xx='\"verbose.tag_info:{{}.{}.{..10}}.seltime:1\"'
-
-	Sample /etc/modules.conf line:
-		Change Read Streaming for Controller's 2 and 3
-
-	options aic79xx='\"rd_strm:{..0xFFF0.0xC0F0}\"'
-");
+MODULE_PARM_DESC(aic79xx, "period delimited, options string."\
+"	verbose			Enable verbose/diagnostic logging"\
+"	debug			Bitmask of debug values to enable"\
+"	no_reset		Supress initial bus resets"\
+"	extended		Enable extended geometry on all controllers"\
+"	periodic_otag		Send an ordered tagged transaction periodically"\
+"				to prevent tag starvation.  This may be"\
+"				required by some older disk drives/RAID arrays. "\
+"	reverse_scan		Sort PCI devices highest Bus/Slot to lowest"\
+"	tag_info:<tag_str>	Set per-target tag depth"\
+"	rd_strm:<rd_strm_masks> Set per-target read streaming setting."\
+"	seltime:<int>		Selection Timeout(0/256ms,1/128ms,2/64ms,3/32ms)"\
+""\
+"	Sample /etc/modules.conf line:"\
+"		Enable verbose logging"\
+"		Set tag depth on Controller 2/Target 2 to 10 tags"\
+"		Shorten the selection timeout to 128ms from its default of 256"\
+""\
+"	options aic79xx='\"verbose.tag_info:{{}.{}.{..10}}.seltime:1\"'"\
+""\
+"	Sample /etc/modules.conf line:"\
+"		Change Read Streaming for Controller's 2 and 3"\
+""\
+"	options aic79xx='\"rd_strm:{..0xFFF0.0xC0F0}\"'"
+);
 #endif
 
 static void ahd_linux_handle_scsi_status(struct ahd_softc *,
diff -Nur --exclude='*.orig' --exclude='*.o' linux-2.4.20.old/drivers/scsi/aic7xxx/aic7xxx_osm.c linux-2.4.20/drivers/scsi/aic7xxx/aic7xxx_osm.c
--- linux-2.4.20.old/drivers/scsi/aic7xxx/aic7xxx_osm.c	Mon Jun 16 13:16:08 2003
+++ linux-2.4.20/drivers/scsi/aic7xxx/aic7xxx_osm.c	Mon Jun 16 13:16:09 2003
@@ -417,26 +417,26 @@
 MODULE_LICENSE("Dual BSD/GPL");
 #endif
 MODULE_PARM(aic7xxx, "s");
-MODULE_PARM_DESC(aic7xxx, "period delimited, options string.
-	verbose			Enable verbose/diagnostic logging
-	no_probe		Disable EISA/VLB controller probing
-	no_reset		Supress initial bus resets
-	extended		Enable extended geometry on all controllers
-	periodic_otag		Send an ordered tagged transaction periodically
-				to prevent tag starvation.  This may be
-				required by some older disk drives/RAID arrays. 
-	reverse_scan		Sort PCI devices highest Bus/Slot to lowest
-	tag_info:<tag_str>	Set per-target tag depth
-	seltime:<int>		Selection Timeout(0/256ms,1/128ms,2/64ms,3/32ms)
-
-	Sample /etc/modules.conf line:
-		Enable verbose logging
-		Disable EISA/VLB probing
-		Set tag depth on Controller 2/Target 2 to 10 tags
-		Shorten the selection timeout to 128ms from its default of 256
-
-	options aic7xxx='\"verbose.no_probe.tag_info:{{}.{}.{..10}}.seltime:1\"'
-");
+MODULE_PARM_DESC(aic7xxx, "period delimited, options string." \
+"	verbose			Enable verbose/diagnostic logging" \
+"	no_probe		Disable EISA/VLB controller probing" \
+"	no_reset		Supress initial bus resets" \
+"	extended		Enable extended geometry on all controllers" \
+"	periodic_otag		Send an ordered tagged transaction periodically" \
+"				to prevent tag starvation.  This may be" \
+"				required by some older disk drives/RAID arrays." \
+"	reverse_scan		Sort PCI devices highest Bus/Slot to lowest" \
+"	tag_info:<tag_str>	Set per-target tag depth" \
+"	seltime:<int>		Selection Timeout(0/256ms,1/128ms,2/64ms,3/32ms)" \
+" " \
+"	Sample /etc/modules.conf line:" \
+"		Enable verbose logging" \
+"		Disable EISA/VLB probing" \
+"		Set tag depth on Controller 2/Target 2 to 10 tags" \
+"		Shorten the selection timeout to 128ms from its default of 256" \
+" " \
+"	options aic7xxx='\"verbose.no_probe.tag_info:{{}.{}.{..10}}.seltime:1\"'"
+);
 #endif
 
 static void ahc_linux_handle_scsi_status(struct ahc_softc *,
diff -Nur --exclude='*.orig' linux-2.4.20.org/drivers/sound/cs46xx.c linux-2.4.20/drivers/sound/cs46xx.c
--- linux-2.4.20.org/drivers/sound/cs46xx.c	Sat Aug  3 00:39:44 2002
+++ linux-2.4.20/drivers/sound/cs46xx.c	Tue Jun 17 06:25:18 2003
@@ -947,8 +947,8 @@
 
 struct InitStruct
 {
-    u32 long off;
-    u32 long val;
+    u32 off;
+    u32 val;
 } InitArray[] = { {0x00000040, 0x3fc0000f},
                   {0x0000004c, 0x04800000},
 
diff -Nur --exclude='*.orig' linux-2.4.20.org/fs/reiserfs/super.c linux-2.4.20/fs/reiserfs/super.c
--- linux-2.4.20.org/fs/reiserfs/super.c	Tue Jun 17 07:17:19 2003
+++ linux-2.4.20/fs/reiserfs/super.c	Tue Jun 17 06:44:51 2003
@@ -944,8 +944,7 @@
     ll_rw_block(READ, 1, &(SB_AP_BITMAP(s)[i].bh)) ;
     wait_on_buffer(SB_AP_BITMAP(s)[i].bh) ;
     if (!buffer_uptodate(SB_AP_BITMAP(s)[i].bh)) {
-      printk("reread_meta_blocks, error reading bitmap block number %d at
-      %ld\n", i, SB_AP_BITMAP(s)[i].bh->b_blocknr) ;
+      printk("reread_meta_blocks, error reading bitmap block number %d at %ld\n", i, SB_AP_BITMAP(s)[i].bh->b_blocknr) ;
       return 1 ;
     }
   }
diff -Nur --exclude='*.orig' linux-2.4.20.org/net/ipv4/netfilter/ip_nat_core.c linux-2.4.20/net/ipv4/netfilter/ip_nat_core.c
--- linux-2.4.20.org/net/ipv4/netfilter/ip_nat_core.c	Tue Jun 17 07:17:18 2003
+++ linux-2.4.20/net/ipv4/netfilter/ip_nat_core.c	Tue Jun 17 07:05:01 2003
@@ -851,8 +851,7 @@
 			if (exp_for_packet(exp, pskb)) {
 				/* FIXME: May be true multiple times in the
 				 * case of UDP!! */
-				DEBUGP("calling nat helper (exp=%p) for
-					packet\n", exp);
+				DEBUGP("calling nat helper (exp=%p) for packet\n", exp);
 				ret = helper->help(ct, exp, info, ctinfo, 
 						   hooknum, pskb);
 				if (ret != NF_ACCEPT) {
diff -Nur --exclude='*.orig' --exclude='*.org' linux-2.4.20.org/drivers/net/tokenring/olympic.c linux-2.4.20/drivers/net/tokenring/olympic.c
--- linux-2.4.20.org/drivers/net/tokenring/olympic.c	2002-11-28 23:53:14.000000000 +0000
+++ linux-2.4.20/drivers/net/tokenring/olympic.c	2003-06-20 12:23:35.000000000 +0000
@@ -655,8 +655,8 @@
 	printk(" stat_ring[7]: %p\n", &(olympic_priv->olympic_rx_status_ring[7])  );
 
 	printk("RXCDA: %x, rx_ring[0]: %p\n",readl(olympic_mmio+RXCDA),&olympic_priv->olympic_rx_ring[0]);
-	printk("Rx_ring_dma_addr = %08x, rx_status_dma_addr =
-%08x\n",olympic_priv->rx_ring_dma_addr,olympic_priv->rx_status_ring_dma_addr) ; 
+	printk("Rx_ring_dma_addr = %08x, rx_status_dma_addr =%08x\n",
+		olympic_priv->rx_ring_dma_addr,olympic_priv->rx_status_ring_dma_addr) ; 
 #endif
 
 	writew((((readw(olympic_mmio+RXENQ)) & 0x8000) ^ 0x8000) | i,olympic_mmio+RXENQ);
diff -Nur --exclude='*.orig' --exclude='*.org' linux-2.4.20.org/drivers/net/wan/sbni.c linux-2.4.20/drivers/net/wan/sbni.c
--- linux-2.4.20.org/drivers/net/wan/sbni.c	2002-11-28 23:53:14.000000000 +0000
+++ linux-2.4.20/drivers/net/wan/sbni.c	2003-06-20 12:47:13.000000000 +0000
@@ -1547,88 +1547,6 @@
 
 /* -------------------------------------------------------------------------- */
 
-#ifdef ASM_CRC
-
-static u32
-calc_crc32( u32  crc,  u8  *p,  u32  len )
-{
-	register u32  _crc __asm ( "ax" );
-	_crc = crc;
-	
-	__asm __volatile (
-		"xorl	%%ebx, %%ebx\n"
-		"movl	%1, %%esi\n" 
-		"movl	%2, %%ecx\n" 
-		"movl	$crc32tab, %%edi\n"
-		"shrl	$2, %%ecx\n"
-		"jz	1f\n"
-
-		".align 4\n"
-	"0:\n"
-		"movb	%%al, %%bl\n"
-		"movl	(%%esi), %%edx\n"
-		"shrl	$8, %%eax\n"
-		"xorb	%%dl, %%bl\n"
-		"shrl	$8, %%edx\n"
-		"xorl	(%%edi,%%ebx,4), %%eax\n"
-
-		"movb	%%al, %%bl\n"
-		"shrl	$8, %%eax\n"
-		"xorb	%%dl, %%bl\n"
-		"shrl	$8, %%edx\n"
-		"xorl	(%%edi,%%ebx,4), %%eax\n"
-
-		"movb	%%al, %%bl\n"
-		"shrl	$8, %%eax\n"
-		"xorb	%%dl, %%bl\n"
-		"movb	%%dh, %%dl\n" 
-		"xorl	(%%edi,%%ebx,4), %%eax\n"
-
-		"movb	%%al, %%bl\n"
-		"shrl	$8, %%eax\n"
-		"xorb	%%dl, %%bl\n"
-		"addl	$4, %%esi\n"
-		"xorl	(%%edi,%%ebx,4), %%eax\n"
-
-		"decl	%%ecx\n"
-		"jnz	0b\n"
-
-	"1:\n"
-		"movl	%2, %%ecx\n"
-		"andl	$3, %%ecx\n"
-		"jz	2f\n"
-
-		"movb	%%al, %%bl\n"
-		"shrl	$8, %%eax\n"
-		"xorb	(%%esi), %%bl\n"
-		"xorl	(%%edi,%%ebx,4), %%eax\n"
-
-		"decl	%%ecx\n"
-		"jz	2f\n"
-
-		"movb	%%al, %%bl\n"
-		"shrl	$8, %%eax\n"
-		"xorb	1(%%esi), %%bl\n"
-		"xorl	(%%edi,%%ebx,4), %%eax\n"
-
-		"decl	%%ecx\n"
-		"jz	2f\n"
-
-		"movb	%%al, %%bl\n"
-		"shrl	$8, %%eax\n"
-		"xorb	2(%%esi), %%bl\n"
-		"xorl	(%%edi,%%ebx,4), %%eax\n"
-	"2:\n"
-		:
-		: "a" (_crc), "g" (p), "g" (len)
-		: "ax", "bx", "cx", "dx", "si", "di"
-	);
-
-	return  _crc;
-}
-
-#else	/* ASM_CRC */
-
 static u32
 calc_crc32( u32  crc,  u8  *p,  u32  len )
 {
@@ -1638,8 +1556,6 @@
 	return  crc;
 }
 
-#endif	/* ASM_CRC */
-
 
 static u32  crc32tab[] __attribute__ ((aligned(8))) = {
 	0xD202EF8D,  0xA505DF1B,  0x3C0C8EA1,  0x4B0BBE37,
diff -Nur --exclude='*.orig' --exclude='*.org' linux-2.4.20.org/drivers/net/wan/sdla_chdlc.c linux-2.4.20/drivers/net/wan/sdla_chdlc.c
--- linux-2.4.20.org/drivers/net/wan/sdla_chdlc.c	2003-06-20 12:41:46.000000000 +0000
+++ linux-2.4.20/drivers/net/wan/sdla_chdlc.c	2003-06-20 12:41:03.000000000 +0000
@@ -591,8 +591,7 @@
 	
 
 		if (chdlc_set_intr_mode(card, APP_INT_ON_TIMER)){
-			printk (KERN_INFO "%s: 
-				Failed to set interrupt triggers!\n",
+			printk (KERN_INFO "%s: Failed to set interrupt triggers!\n",
 				card->devname);
 			return -EIO;	
         	}
--- linux-2.4.20/net/decnet/dn_table.c.org	Fri Dec 21 17:42:05 2001
+++ linux-2.4.20/net/decnet/dn_table.c	Mon Jun 23 13:23:27 2003
@@ -836,8 +836,8 @@
                 return NULL;
 
         if (in_interrupt() && net_ratelimit()) {
-                printk(KERN_DEBUG "DECnet: BUG! Attempt to create routing table 
-from interrupt\n"); 
+                printk(KERN_DEBUG 
+		"DECnet: BUG! Attempt to create routing table from interrupt\n"); 
                 return NULL;
         }
         if ((t = kmalloc(sizeof(struct dn_fib_table), GFP_KERNEL)) == NULL)
--- linux-2.4.20/arch/i386/math-emu/poly.h~	Thu Jul 26 20:37:38 2001
+++ linux-2.4.20/arch/i386/math-emu/poly.h	Thu Jul 10 02:09:29 2003
@@ -64,7 +64,7 @@
 				      const unsigned long arg2)
 {
   int retval;
-  asm volatile ("mull %2; movl %%edx,%%eax" \
+  asm volatile ("mull %2; movl %%edx,%%eax; " \
 		:"=a" (retval) \
 		:"0" (arg1), "g" (arg2) \
 		:"dx");
@@ -75,10 +75,10 @@
 /* Add the 12 byte Xsig x2 to Xsig dest, with no checks for overflow. */
 static inline void add_Xsig_Xsig(Xsig *dest, const Xsig *x2)
 {
-  asm volatile ("movl %1,%%edi; movl %2,%%esi;
-                 movl (%%esi),%%eax; addl %%eax,(%%edi);
-                 movl 4(%%esi),%%eax; adcl %%eax,4(%%edi);
-                 movl 8(%%esi),%%eax; adcl %%eax,8(%%edi);"
+  asm volatile ("movl %1,%%edi; movl %2,%%esi; "
+                 "movl (%%esi),%%eax; addl %%eax,(%%edi); "
+                 "movl 4(%%esi),%%eax; adcl %%eax,4(%%edi); "
+                 "movl 8(%%esi),%%eax; adcl %%eax,8(%%edi); "
                  :"=g" (*dest):"g" (dest), "g" (x2)
                  :"ax","si","di");
 }
@@ -90,16 +90,16 @@
    problem, but keep fingers crossed! */
 static inline void add_two_Xsig(Xsig *dest, const Xsig *x2, long int *exp)
 {
-  asm volatile ("movl %2,%%ecx; movl %3,%%esi;
-                 movl (%%esi),%%eax; addl %%eax,(%%ecx);
-                 movl 4(%%esi),%%eax; adcl %%eax,4(%%ecx);
-                 movl 8(%%esi),%%eax; adcl %%eax,8(%%ecx);
-                 jnc 0f;
-		 rcrl 8(%%ecx); rcrl 4(%%ecx); rcrl (%%ecx)
-                 movl %4,%%ecx; incl (%%ecx)
-                 movl $1,%%eax; jmp 1f;
-                 0: xorl %%eax,%%eax;
-                 1:"
+  asm volatile ("movl %2,%%ecx; movl %3,%%esi; "
+                 "movl (%%esi),%%eax; addl %%eax,(%%ecx); "
+                 "movl 4(%%esi),%%eax; adcl %%eax,4(%%ecx); "
+                 "movl 8(%%esi),%%eax; adcl %%eax,8(%%ecx); "
+                 "jnc 0f; "
+		 "rcrl 8(%%ecx); rcrl 4(%%ecx); rcrl (%%ecx); "
+                 "movl %4,%%ecx; incl (%%ecx); "
+                 "movl $1,%%eax; jmp 1f; "
+                 "0: xorl %%eax,%%eax; "
+                 "1:"
 		:"=g" (*exp), "=g" (*dest)
 		:"g" (dest), "g" (x2), "g" (exp)
 		:"cx","si","ax");
@@ -110,11 +110,11 @@
 /* This is faster in a loop on my 386 than using the "neg" instruction. */
 static inline void negate_Xsig(Xsig *x)
 {
-  asm volatile("movl %1,%%esi; "
-               "xorl %%ecx,%%ecx; "
-               "movl %%ecx,%%eax; subl (%%esi),%%eax; movl %%eax,(%%esi); "
-               "movl %%ecx,%%eax; sbbl 4(%%esi),%%eax; movl %%eax,4(%%esi); "
-               "movl %%ecx,%%eax; sbbl 8(%%esi),%%eax; movl %%eax,8(%%esi); "
+  asm volatile("movl %1,%%esi; " \
+               "xorl %%ecx,%%ecx; " \
+               "movl %%ecx,%%eax; subl (%%esi),%%eax; movl %%eax,(%%esi); " \
+               "movl %%ecx,%%eax; sbbl 4(%%esi),%%eax; movl %%eax,4(%%esi); " \
+               "movl %%ecx,%%eax; sbbl 8(%%esi),%%eax; movl %%eax,8(%%esi); " \
                :"=g" (*x):"g" (x):"si","ax","cx");
 }
 
--- linux-2.4.20/include/asm-alpha/mmu_context.h~	2000-12-29 22:07:23.000000000 +0000
+++ linux-2.4.20/include/asm-alpha/mmu_context.h	2003-07-15 20:08:39.000000000 +0000
@@ -32,7 +32,7 @@
 		"call_pal %2 #__reload_thread"
 		: "=r"(v0), "=r"(a0)
 		: "i"(PAL_swpctx), "r"(a0)
-		: "$1", "$16", "$22", "$23", "$24", "$25");
+		: "$1", "$22", "$23", "$24", "$25");
 
 	return v0;
 }
diff -urN linux-2.4.20/arch/alpha/lib/ev6-strncpy_from_user.S linux-2.4.20/arch/alpha/lib/ev6-strncpy_from_user.S
--- linux-2.4.20/arch/alpha/lib/ev6-strncpy_from_user.S	2003-07-15 22:30:41.000000000 +0000
+++ linux-2.4.20/arch/alpha/lib/ev6-strncpy_from_user.S	2003-07-15 22:33:29.000000000 +0000
@@ -27,7 +27,7 @@
 
 
 #include <asm/errno.h>
-#include <alpha/regdef.h>
+#include <asm/regdef.h>
 
 
 /* Allow an exception for an insn; exit if we get one.  */
diff -urN linux-2.4.20/arch/alpha/lib/ev6-stxcpy.S linux-2.4.20/arch/alpha/lib/ev6-stxcpy.S
--- linux-2.4.20/arch/alpha/lib/ev6-stxcpy.S	2003-07-15 22:30:41.000000000 +0000
+++ linux-2.4.20/arch/alpha/lib/ev6-stxcpy.S	2003-07-15 22:33:29.000000000 +0000
@@ -30,7 +30,7 @@
  * Try not to change the actual algorithm if possible for consistency.
  */
 
-#include <alpha/regdef.h>
+#include <asm/regdef.h>
 
 	.set noat
 	.set noreorder
diff -urN linux-2.4.20/arch/alpha/lib/ev6-stxncpy.S linux-2.4.20/arch/alpha/lib/ev6-stxncpy.S
--- linux-2.4.20/arch/alpha/lib/ev6-stxncpy.S	2003-07-15 22:30:41.000000000 +0000
+++ linux-2.4.20/arch/alpha/lib/ev6-stxncpy.S	2003-07-15 22:33:29.000000000 +0000
@@ -38,7 +38,7 @@
  * Try not to change the actual algorithm if possible for consistency.
  */
 
-#include <alpha/regdef.h>
+#include <asm/regdef.h>
 
 	.set noat
 	.set noreorder
diff -urN linux-2.4.20/arch/alpha/lib/ev67-strchr.S linux-2.4.20/arch/alpha/lib/ev67-strchr.S
--- linux-2.4.20/arch/alpha/lib/ev67-strchr.S	2003-07-15 22:30:41.000000000 +0000
+++ linux-2.4.20/arch/alpha/lib/ev67-strchr.S	2003-07-15 22:33:29.000000000 +0000
@@ -16,7 +16,7 @@
  * Try not to change the actual algorithm if possible for consistency.
  */
 
-#include <alpha/regdef.h>
+#include <asm/regdef.h>
 
 	.set noreorder
 	.set noat
diff -urN linux-2.4.20/arch/alpha/lib/ev67-strlen_user.S linux-2.4.20/arch/alpha/lib/ev67-strlen_user.S
--- linux-2.4.20/arch/alpha/lib/ev67-strlen_user.S	2003-07-15 22:30:41.000000000 +0000
+++ linux-2.4.20/arch/alpha/lib/ev67-strlen_user.S	2003-07-15 22:33:29.000000000 +0000
@@ -23,7 +23,7 @@
  * Try not to change the actual algorithm if possible for consistency.
  */
 
-#include <alpha/regdef.h>
+#include <asm/regdef.h>
 
 
 /* Allow an exception for an insn; exit if we get one.  */
diff -urN linux-2.4.20/arch/alpha/lib/ev67-strrchr.S linux-2.4.20/arch/alpha/lib/ev67-strrchr.S
--- linux-2.4.20/arch/alpha/lib/ev67-strrchr.S	2003-07-15 22:30:41.000000000 +0000
+++ linux-2.4.20/arch/alpha/lib/ev67-strrchr.S	2003-07-15 22:33:29.000000000 +0000
@@ -19,7 +19,7 @@
  */
 
 
-#include <alpha/regdef.h>
+#include <asm/regdef.h>
 
 	.set noreorder
 	.set noat
diff -urN linux-2.4.20/arch/alpha/lib/strchr.S linux-2.4.20/arch/alpha/lib/strchr.S
--- linux-2.4.20/arch/alpha/lib/strchr.S	2003-07-15 22:30:41.000000000 +0000
+++ linux-2.4.20/arch/alpha/lib/strchr.S	2003-07-15 22:33:29.000000000 +0000
@@ -6,7 +6,7 @@
  * string, or null if it is not found.
  */
 
-#include <alpha/regdef.h>
+#include <asm/regdef.h>
 
 	.set noreorder
 	.set noat
diff -urN linux-2.4.20/arch/alpha/lib/strlen_user.S linux-2.4.20/arch/alpha/lib/strlen_user.S
--- linux-2.4.20/arch/alpha/lib/strlen_user.S	2003-07-15 22:30:41.000000000 +0000
+++ linux-2.4.20/arch/alpha/lib/strlen_user.S	2003-07-15 22:33:29.000000000 +0000
@@ -12,7 +12,7 @@
  * boundary when doing so.
  */
 
-#include <alpha/regdef.h>
+#include <asm/regdef.h>
 
 
 /* Allow an exception for an insn; exit if we get one.  */
diff -urN linux-2.4.20/arch/alpha/lib/strncpy_from_user.S linux-2.4.20/arch/alpha/lib/strncpy_from_user.S
--- linux-2.4.20/arch/alpha/lib/strncpy_from_user.S	2003-07-15 22:30:41.000000000 +0000
+++ linux-2.4.20/arch/alpha/lib/strncpy_from_user.S	2003-07-15 22:33:29.000000000 +0000
@@ -12,7 +12,7 @@
 
 
 #include <asm/errno.h>
-#include <alpha/regdef.h>
+#include <asm/regdef.h>
 
 
 /* Allow an exception for an insn; exit if we get one.  */
diff -urN linux-2.4.20/arch/alpha/lib/strrchr.S linux-2.4.20/arch/alpha/lib/strrchr.S
--- linux-2.4.20/arch/alpha/lib/strrchr.S	2003-07-15 22:30:41.000000000 +0000
+++ linux-2.4.20/arch/alpha/lib/strrchr.S	2003-07-15 22:33:29.000000000 +0000
@@ -6,7 +6,7 @@
  * within a null-terminated string, or null if it is not found.
  */
 
-#include <alpha/regdef.h>
+#include <asm/regdef.h>
 
 	.set noreorder
 	.set noat
diff -urN linux-2.4.20/arch/alpha/lib/stxcpy.S linux-2.4.20/arch/alpha/lib/stxcpy.S
--- linux-2.4.20/arch/alpha/lib/stxcpy.S	2003-07-15 22:30:41.000000000 +0000
+++ linux-2.4.20/arch/alpha/lib/stxcpy.S	2003-07-15 22:33:29.000000000 +0000
@@ -20,7 +20,7 @@
  * Furthermore, v0, a3-a5, t11, and t12 are untouched.
  */
 
-#include <alpha/regdef.h>
+#include <asm/regdef.h>
 
 	.set noat
 	.set noreorder
diff -urN linux-2.4.20/arch/alpha/lib/stxncpy.S linux-2.4.20/arch/alpha/lib/stxncpy.S
--- linux-2.4.20/arch/alpha/lib/stxncpy.S	2003-07-15 22:30:41.000000000 +0000
+++ linux-2.4.20/arch/alpha/lib/stxncpy.S	2003-07-15 22:33:29.000000000 +0000
@@ -28,7 +28,7 @@
  * Furthermore, v0, a3-a5, t11, t12, and $at are untouched.
  */
 
-#include <alpha/regdef.h>
+#include <asm/regdef.h>
 
 	.set noat
 	.set noreorder
--- /dev/null	Tue May  5 22:32:27 1998
+++ linux-2.6.0-test1/include/asm-alpha/regdef.h	Mon Jul 14 05:32:34 2003
@@ -0,0 +1,44 @@
+#ifndef __alpha_regdef_h__
+#define __alpha_regdef_h__
+
+#define v0	$0	/* function return value */
+
+#define t0	$1	/* temporary registers (caller-saved) */
+#define t1	$2
+#define t2	$3
+#define t3	$4
+#define t4	$5
+#define t5	$6
+#define t6	$7
+#define t7	$8
+
+#define	s0	$9	/* saved-registers (callee-saved registers) */
+#define	s1	$10
+#define	s2	$11
+#define	s3	$12
+#define	s4	$13
+#define	s5	$14
+#define	s6	$15
+#define	fp	s6	/* frame-pointer (s6 in frame-less procedures) */
+
+#define a0	$16	/* argument registers (caller-saved) */
+#define a1	$17
+#define a2	$18
+#define a3	$19
+#define a4	$20
+#define a5	$21
+
+#define t8	$22	/* more temps (caller-saved) */
+#define t9	$23
+#define t10	$24
+#define t11	$25
+#define ra	$26	/* return address register */
+#define t12	$27
+
+#define pv	t12	/* procedure-variable register */
+#define AT	$at	/* assembler temporary */
+#define gp	$29	/* global pointer */
+#define sp	$30	/* stack pointer */
+#define zero	$31	/* reads as zero, writes are noops */
+
+#endif /* __alpha_regdef_h__ */
--- linux-2.4.20/include/asm-alpha/xor.h.orig	2000-11-13 03:39:51.000000000 +0000
+++ linux-2.4.20/include/asm-alpha/xor.h	2003-07-16 11:41:27.000000000 +0000
@@ -32,809 +32,809 @@
 				 unsigned long *, unsigned long *,
 				 unsigned long *, unsigned long *);
 
-asm("
-	.text
-	.align 3
-	.ent xor_alpha_2
-xor_alpha_2:
-	.prologue 0
-	srl $16, 6, $16
-	.align 4
-2:
-	ldq $0,0($17)
-	ldq $1,0($18)
-	ldq $2,8($17)
-	ldq $3,8($18)
-
-	ldq $4,16($17)
-	ldq $5,16($18)
-	ldq $6,24($17)
-	ldq $7,24($18)
-
-	ldq $19,32($17)
-	ldq $20,32($18)
-	ldq $21,40($17)
-	ldq $22,40($18)
-
-	ldq $23,48($17)
-	ldq $24,48($18)
-	ldq $25,56($17)
-	xor $0,$1,$0		# 7 cycles from $1 load
-
-	ldq $27,56($18)
-	xor $2,$3,$2
-	stq $0,0($17)
-	xor $4,$5,$4
-
-	stq $2,8($17)
-	xor $6,$7,$6
-	stq $4,16($17)
-	xor $19,$20,$19
-
-	stq $6,24($17)
-	xor $21,$22,$21
-	stq $19,32($17)
-	xor $23,$24,$23
-
-	stq $21,40($17)
-	xor $25,$27,$25
-	stq $23,48($17)
-	subq $16,1,$16
-
-	stq $25,56($17)
-	addq $17,64,$17
-	addq $18,64,$18
-	bgt $16,2b
-
-	ret
-	.end xor_alpha_2
-
-	.align 3
-	.ent xor_alpha_3
-xor_alpha_3:
-	.prologue 0
-	srl $16, 6, $16
-	.align 4
-3:
-	ldq $0,0($17)
-	ldq $1,0($18)
-	ldq $2,0($19)
-	ldq $3,8($17)
-
-	ldq $4,8($18)
-	ldq $6,16($17)
-	ldq $7,16($18)
-	ldq $21,24($17)
-
-	ldq $22,24($18)
-	ldq $24,32($17)
-	ldq $25,32($18)
-	ldq $5,8($19)
-
-	ldq $20,16($19)
-	ldq $23,24($19)
-	ldq $27,32($19)
-	nop
-
-	xor $0,$1,$1		# 8 cycles from $0 load
-	xor $3,$4,$4		# 6 cycles from $4 load
-	xor $6,$7,$7		# 6 cycles from $7 load
-	xor $21,$22,$22		# 5 cycles from $22 load
-
-	xor $1,$2,$2		# 9 cycles from $2 load
-	xor $24,$25,$25		# 5 cycles from $25 load
-	stq $2,0($17)
-	xor $4,$5,$5		# 6 cycles from $5 load
-
-	stq $5,8($17)
-	xor $7,$20,$20		# 7 cycles from $20 load
-	stq $20,16($17)
-	xor $22,$23,$23		# 7 cycles from $23 load
-
-	stq $23,24($17)
-	xor $25,$27,$27		# 7 cycles from $27 load
-	stq $27,32($17)
-	nop
-
-	ldq $0,40($17)
-	ldq $1,40($18)
-	ldq $3,48($17)
-	ldq $4,48($18)
-
-	ldq $6,56($17)
-	ldq $7,56($18)
-	ldq $2,40($19)
-	ldq $5,48($19)
-
-	ldq $20,56($19)
-	xor $0,$1,$1		# 4 cycles from $1 load
-	xor $3,$4,$4		# 5 cycles from $4 load
-	xor $6,$7,$7		# 5 cycles from $7 load
-
-	xor $1,$2,$2		# 4 cycles from $2 load
-	xor $4,$5,$5		# 5 cycles from $5 load
-	stq $2,40($17)
-	xor $7,$20,$20		# 4 cycles from $20 load
-
-	stq $5,48($17)
-	subq $16,1,$16
-	stq $20,56($17)
-	addq $19,64,$19
-
-	addq $18,64,$18
-	addq $17,64,$17
-	bgt $16,3b
-	ret
-	.end xor_alpha_3
-
-	.align 3
-	.ent xor_alpha_4
-xor_alpha_4:
-	.prologue 0
-	srl $16, 6, $16
-	.align 4
-4:
-	ldq $0,0($17)
-	ldq $1,0($18)
-	ldq $2,0($19)
-	ldq $3,0($20)
-
-	ldq $4,8($17)
-	ldq $5,8($18)
-	ldq $6,8($19)
-	ldq $7,8($20)
-
-	ldq $21,16($17)
-	ldq $22,16($18)
-	ldq $23,16($19)
-	ldq $24,16($20)
-
-	ldq $25,24($17)
-	xor $0,$1,$1		# 6 cycles from $1 load
-	ldq $27,24($18)
-	xor $2,$3,$3		# 6 cycles from $3 load
-
-	ldq $0,24($19)
-	xor $1,$3,$3
-	ldq $1,24($20)
-	xor $4,$5,$5		# 7 cycles from $5 load
-
-	stq $3,0($17)
-	xor $6,$7,$7
-	xor $21,$22,$22		# 7 cycles from $22 load
-	xor $5,$7,$7
-
-	stq $7,8($17)
-	xor $23,$24,$24		# 7 cycles from $24 load
-	ldq $2,32($17)
-	xor $22,$24,$24
-
-	ldq $3,32($18)
-	ldq $4,32($19)
-	ldq $5,32($20)
-	xor $25,$27,$27		# 8 cycles from $27 load
-
-	ldq $6,40($17)
-	ldq $7,40($18)
-	ldq $21,40($19)
-	ldq $22,40($20)
-
-	stq $24,16($17)
-	xor $0,$1,$1		# 9 cycles from $1 load
-	xor $2,$3,$3		# 5 cycles from $3 load
-	xor $27,$1,$1
-
-	stq $1,24($17)
-	xor $4,$5,$5		# 5 cycles from $5 load
-	ldq $23,48($17)
-	ldq $24,48($18)
-
-	ldq $25,48($19)
-	xor $3,$5,$5
-	ldq $27,48($20)
-	ldq $0,56($17)
-
-	ldq $1,56($18)
-	ldq $2,56($19)
-	xor $6,$7,$7		# 8 cycles from $6 load
-	ldq $3,56($20)
-
-	stq $5,32($17)
-	xor $21,$22,$22		# 8 cycles from $22 load
-	xor $7,$22,$22
-	xor $23,$24,$24		# 5 cycles from $24 load
-
-	stq $22,40($17)
-	xor $25,$27,$27		# 5 cycles from $27 load
-	xor $24,$27,$27
-	xor $0,$1,$1		# 5 cycles from $1 load
-
-	stq $27,48($17)
-	xor $2,$3,$3		# 4 cycles from $3 load
-	xor $1,$3,$3
-	subq $16,1,$16
-
-	stq $3,56($17)
-	addq $20,64,$20
-	addq $19,64,$19
-	addq $18,64,$18
-
-	addq $17,64,$17
-	bgt $16,4b
-	ret
-	.end xor_alpha_4
-
-	.align 3
-	.ent xor_alpha_5
-xor_alpha_5:
-	.prologue 0
-	srl $16, 6, $16
-	.align 4
-5:
-	ldq $0,0($17)
-	ldq $1,0($18)
-	ldq $2,0($19)
-	ldq $3,0($20)
-
-	ldq $4,0($21)
-	ldq $5,8($17)
-	ldq $6,8($18)
-	ldq $7,8($19)
-
-	ldq $22,8($20)
-	ldq $23,8($21)
-	ldq $24,16($17)
-	ldq $25,16($18)
-
-	ldq $27,16($19)
-	xor $0,$1,$1		# 6 cycles from $1 load
-	ldq $28,16($20)
-	xor $2,$3,$3		# 6 cycles from $3 load
-
-	ldq $0,16($21)
-	xor $1,$3,$3
-	ldq $1,24($17)
-	xor $3,$4,$4		# 7 cycles from $4 load
-
-	stq $4,0($17)
-	xor $5,$6,$6		# 7 cycles from $6 load
-	xor $7,$22,$22		# 7 cycles from $22 load
-	xor $6,$23,$23		# 7 cycles from $23 load
-
-	ldq $2,24($18)
-	xor $22,$23,$23
-	ldq $3,24($19)
-	xor $24,$25,$25		# 8 cycles from $25 load
-
-	stq $23,8($17)
-	xor $25,$27,$27		# 8 cycles from $27 load
-	ldq $4,24($20)
-	xor $28,$0,$0		# 7 cycles from $0 load
-
-	ldq $5,24($21)
-	xor $27,$0,$0
-	ldq $6,32($17)
-	ldq $7,32($18)
-
-	stq $0,16($17)
-	xor $1,$2,$2		# 6 cycles from $2 load
-	ldq $22,32($19)
-	xor $3,$4,$4		# 4 cycles from $4 load
-	
-	ldq $23,32($20)
-	xor $2,$4,$4
-	ldq $24,32($21)
-	ldq $25,40($17)
-
-	ldq $27,40($18)
-	ldq $28,40($19)
-	ldq $0,40($20)
-	xor $4,$5,$5		# 7 cycles from $5 load
-
-	stq $5,24($17)
-	xor $6,$7,$7		# 7 cycles from $7 load
-	ldq $1,40($21)
-	ldq $2,48($17)
-
-	ldq $3,48($18)
-	xor $7,$22,$22		# 7 cycles from $22 load
-	ldq $4,48($19)
-	xor $23,$24,$24		# 6 cycles from $24 load
-
-	ldq $5,48($20)
-	xor $22,$24,$24
-	ldq $6,48($21)
-	xor $25,$27,$27		# 7 cycles from $27 load
-
-	stq $24,32($17)
-	xor $27,$28,$28		# 8 cycles from $28 load
-	ldq $7,56($17)
-	xor $0,$1,$1		# 6 cycles from $1 load
-
-	ldq $22,56($18)
-	ldq $23,56($19)
-	ldq $24,56($20)
-	ldq $25,56($21)
-
-	xor $28,$1,$1
-	xor $2,$3,$3		# 9 cycles from $3 load
-	xor $3,$4,$4		# 9 cycles from $4 load
-	xor $5,$6,$6		# 8 cycles from $6 load
-
-	stq $1,40($17)
-	xor $4,$6,$6
-	xor $7,$22,$22		# 7 cycles from $22 load
-	xor $23,$24,$24		# 6 cycles from $24 load
-
-	stq $6,48($17)
-	xor $22,$24,$24
-	subq $16,1,$16
-	xor $24,$25,$25		# 8 cycles from $25 load
-
-	stq $25,56($17)
-	addq $21,64,$21
-	addq $20,64,$20
-	addq $19,64,$19
-
-	addq $18,64,$18
-	addq $17,64,$17
-	bgt $16,5b
-	ret
-	.end xor_alpha_5
-
-	.align 3
-	.ent xor_alpha_prefetch_2
-xor_alpha_prefetch_2:
-	.prologue 0
-	srl $16, 6, $16
-
-	ldq $31, 0($17)
-	ldq $31, 0($18)
-
-	ldq $31, 64($17)
-	ldq $31, 64($18)
-
-	ldq $31, 128($17)
-	ldq $31, 128($18)
-
-	ldq $31, 192($17)
-	ldq $31, 192($18)
-	.align 4
-2:
-	ldq $0,0($17)
-	ldq $1,0($18)
-	ldq $2,8($17)
-	ldq $3,8($18)
-
-	ldq $4,16($17)
-	ldq $5,16($18)
-	ldq $6,24($17)
-	ldq $7,24($18)
-
-	ldq $19,32($17)
-	ldq $20,32($18)
-	ldq $21,40($17)
-	ldq $22,40($18)
-
-	ldq $23,48($17)
-	ldq $24,48($18)
-	ldq $25,56($17)
-	ldq $27,56($18)
-
-	ldq $31,256($17)
-	xor $0,$1,$0		# 8 cycles from $1 load
-	ldq $31,256($18)
-	xor $2,$3,$2
-
-	stq $0,0($17)
-	xor $4,$5,$4
-	stq $2,8($17)
-	xor $6,$7,$6
-
-	stq $4,16($17)
-	xor $19,$20,$19
-	stq $6,24($17)
-	xor $21,$22,$21
-
-	stq $19,32($17)
-	xor $23,$24,$23
-	stq $21,40($17)
-	xor $25,$27,$25
-
-	stq $23,48($17)
-	subq $16,1,$16
-	stq $25,56($17)
-	addq $17,64,$17
-
-	addq $18,64,$18
-	bgt $16,2b
-	ret
-	.end xor_alpha_prefetch_2
-
-	.align 3
-	.ent xor_alpha_prefetch_3
-xor_alpha_prefetch_3:
-	.prologue 0
-	srl $16, 6, $16
-
-	ldq $31, 0($17)
-	ldq $31, 0($18)
-	ldq $31, 0($19)
-
-	ldq $31, 64($17)
-	ldq $31, 64($18)
-	ldq $31, 64($19)
-
-	ldq $31, 128($17)
-	ldq $31, 128($18)
-	ldq $31, 128($19)
-
-	ldq $31, 192($17)
-	ldq $31, 192($18)
-	ldq $31, 192($19)
-	.align 4
-3:
-	ldq $0,0($17)
-	ldq $1,0($18)
-	ldq $2,0($19)
-	ldq $3,8($17)
-
-	ldq $4,8($18)
-	ldq $6,16($17)
-	ldq $7,16($18)
-	ldq $21,24($17)
-
-	ldq $22,24($18)
-	ldq $24,32($17)
-	ldq $25,32($18)
-	ldq $5,8($19)
-
-	ldq $20,16($19)
-	ldq $23,24($19)
-	ldq $27,32($19)
-	nop
-
-	xor $0,$1,$1		# 8 cycles from $0 load
-	xor $3,$4,$4		# 7 cycles from $4 load
-	xor $6,$7,$7		# 6 cycles from $7 load
-	xor $21,$22,$22		# 5 cycles from $22 load
-
-	xor $1,$2,$2		# 9 cycles from $2 load
-	xor $24,$25,$25		# 5 cycles from $25 load
-	stq $2,0($17)
-	xor $4,$5,$5		# 6 cycles from $5 load
-
-	stq $5,8($17)
-	xor $7,$20,$20		# 7 cycles from $20 load
-	stq $20,16($17)
-	xor $22,$23,$23		# 7 cycles from $23 load
-
-	stq $23,24($17)
-	xor $25,$27,$27		# 7 cycles from $27 load
-	stq $27,32($17)
-	nop
-
-	ldq $0,40($17)
-	ldq $1,40($18)
-	ldq $3,48($17)
-	ldq $4,48($18)
-
-	ldq $6,56($17)
-	ldq $7,56($18)
-	ldq $2,40($19)
-	ldq $5,48($19)
-
-	ldq $20,56($19)
-	ldq $31,256($17)
-	ldq $31,256($18)
-	ldq $31,256($19)
-
-	xor $0,$1,$1		# 6 cycles from $1 load
-	xor $3,$4,$4		# 5 cycles from $4 load
-	xor $6,$7,$7		# 5 cycles from $7 load
-	xor $1,$2,$2		# 4 cycles from $2 load
-	
-	xor $4,$5,$5		# 5 cycles from $5 load
-	xor $7,$20,$20		# 4 cycles from $20 load
-	stq $2,40($17)
-	subq $16,1,$16
-
-	stq $5,48($17)
-	addq $19,64,$19
-	stq $20,56($17)
-	addq $18,64,$18
-
-	addq $17,64,$17
-	bgt $16,3b
-	ret
-	.end xor_alpha_prefetch_3
-
-	.align 3
-	.ent xor_alpha_prefetch_4
-xor_alpha_prefetch_4:
-	.prologue 0
-	srl $16, 6, $16
-
-	ldq $31, 0($17)
-	ldq $31, 0($18)
-	ldq $31, 0($19)
-	ldq $31, 0($20)
-
-	ldq $31, 64($17)
-	ldq $31, 64($18)
-	ldq $31, 64($19)
-	ldq $31, 64($20)
-
-	ldq $31, 128($17)
-	ldq $31, 128($18)
-	ldq $31, 128($19)
-	ldq $31, 128($20)
-
-	ldq $31, 192($17)
-	ldq $31, 192($18)
-	ldq $31, 192($19)
-	ldq $31, 192($20)
-	.align 4
-4:
-	ldq $0,0($17)
-	ldq $1,0($18)
-	ldq $2,0($19)
-	ldq $3,0($20)
-
-	ldq $4,8($17)
-	ldq $5,8($18)
-	ldq $6,8($19)
-	ldq $7,8($20)
-
-	ldq $21,16($17)
-	ldq $22,16($18)
-	ldq $23,16($19)
-	ldq $24,16($20)
-
-	ldq $25,24($17)
-	xor $0,$1,$1		# 6 cycles from $1 load
-	ldq $27,24($18)
-	xor $2,$3,$3		# 6 cycles from $3 load
-
-	ldq $0,24($19)
-	xor $1,$3,$3
-	ldq $1,24($20)
-	xor $4,$5,$5		# 7 cycles from $5 load
-
-	stq $3,0($17)
-	xor $6,$7,$7
-	xor $21,$22,$22		# 7 cycles from $22 load
-	xor $5,$7,$7
-
-	stq $7,8($17)
-	xor $23,$24,$24		# 7 cycles from $24 load
-	ldq $2,32($17)
-	xor $22,$24,$24
-
-	ldq $3,32($18)
-	ldq $4,32($19)
-	ldq $5,32($20)
-	xor $25,$27,$27		# 8 cycles from $27 load
-
-	ldq $6,40($17)
-	ldq $7,40($18)
-	ldq $21,40($19)
-	ldq $22,40($20)
-
-	stq $24,16($17)
-	xor $0,$1,$1		# 9 cycles from $1 load
-	xor $2,$3,$3		# 5 cycles from $3 load
-	xor $27,$1,$1
-
-	stq $1,24($17)
-	xor $4,$5,$5		# 5 cycles from $5 load
-	ldq $23,48($17)
-	xor $3,$5,$5
-
-	ldq $24,48($18)
-	ldq $25,48($19)
-	ldq $27,48($20)
-	ldq $0,56($17)
-
-	ldq $1,56($18)
-	ldq $2,56($19)
-	ldq $3,56($20)
-	xor $6,$7,$7		# 8 cycles from $6 load
-
-	ldq $31,256($17)
-	xor $21,$22,$22		# 8 cycles from $22 load
-	ldq $31,256($18)
-	xor $7,$22,$22
-
-	ldq $31,256($19)
-	xor $23,$24,$24		# 6 cycles from $24 load
-	ldq $31,256($20)
-	xor $25,$27,$27		# 6 cycles from $27 load
-
-	stq $5,32($17)
-	xor $24,$27,$27
-	xor $0,$1,$1		# 7 cycles from $1 load
-	xor $2,$3,$3		# 6 cycles from $3 load
-
-	stq $22,40($17)
-	xor $1,$3,$3
-	stq $27,48($17)
-	subq $16,1,$16
-
-	stq $3,56($17)
-	addq $20,64,$20
-	addq $19,64,$19
-	addq $18,64,$18
-
-	addq $17,64,$17
-	bgt $16,4b
-	ret
-	.end xor_alpha_prefetch_4
-
-	.align 3
-	.ent xor_alpha_prefetch_5
-xor_alpha_prefetch_5:
-	.prologue 0
-	srl $16, 6, $16
-
-	ldq $31, 0($17)
-	ldq $31, 0($18)
-	ldq $31, 0($19)
-	ldq $31, 0($20)
-	ldq $31, 0($21)
-
-	ldq $31, 64($17)
-	ldq $31, 64($18)
-	ldq $31, 64($19)
-	ldq $31, 64($20)
-	ldq $31, 64($21)
-
-	ldq $31, 128($17)
-	ldq $31, 128($18)
-	ldq $31, 128($19)
-	ldq $31, 128($20)
-	ldq $31, 128($21)
-
-	ldq $31, 192($17)
-	ldq $31, 192($18)
-	ldq $31, 192($19)
-	ldq $31, 192($20)
-	ldq $31, 192($21)
-	.align 4
-5:
-	ldq $0,0($17)
-	ldq $1,0($18)
-	ldq $2,0($19)
-	ldq $3,0($20)
-
-	ldq $4,0($21)
-	ldq $5,8($17)
-	ldq $6,8($18)
-	ldq $7,8($19)
-
-	ldq $22,8($20)
-	ldq $23,8($21)
-	ldq $24,16($17)
-	ldq $25,16($18)
-
-	ldq $27,16($19)
-	xor $0,$1,$1		# 6 cycles from $1 load
-	ldq $28,16($20)
-	xor $2,$3,$3		# 6 cycles from $3 load
-
-	ldq $0,16($21)
-	xor $1,$3,$3
-	ldq $1,24($17)
-	xor $3,$4,$4		# 7 cycles from $4 load
-
-	stq $4,0($17)
-	xor $5,$6,$6		# 7 cycles from $6 load
-	xor $7,$22,$22		# 7 cycles from $22 load
-	xor $6,$23,$23		# 7 cycles from $23 load
-
-	ldq $2,24($18)
-	xor $22,$23,$23
-	ldq $3,24($19)
-	xor $24,$25,$25		# 8 cycles from $25 load
-
-	stq $23,8($17)
-	xor $25,$27,$27		# 8 cycles from $27 load
-	ldq $4,24($20)
-	xor $28,$0,$0		# 7 cycles from $0 load
-
-	ldq $5,24($21)
-	xor $27,$0,$0
-	ldq $6,32($17)
-	ldq $7,32($18)
-
-	stq $0,16($17)
-	xor $1,$2,$2		# 6 cycles from $2 load
-	ldq $22,32($19)
-	xor $3,$4,$4		# 4 cycles from $4 load
-	
-	ldq $23,32($20)
-	xor $2,$4,$4
-	ldq $24,32($21)
-	ldq $25,40($17)
-
-	ldq $27,40($18)
-	ldq $28,40($19)
-	ldq $0,40($20)
-	xor $4,$5,$5		# 7 cycles from $5 load
-
-	stq $5,24($17)
-	xor $6,$7,$7		# 7 cycles from $7 load
-	ldq $1,40($21)
-	ldq $2,48($17)
-
-	ldq $3,48($18)
-	xor $7,$22,$22		# 7 cycles from $22 load
-	ldq $4,48($19)
-	xor $23,$24,$24		# 6 cycles from $24 load
-
-	ldq $5,48($20)
-	xor $22,$24,$24
-	ldq $6,48($21)
-	xor $25,$27,$27		# 7 cycles from $27 load
-
-	stq $24,32($17)
-	xor $27,$28,$28		# 8 cycles from $28 load
-	ldq $7,56($17)
-	xor $0,$1,$1		# 6 cycles from $1 load
-
-	ldq $22,56($18)
-	ldq $23,56($19)
-	ldq $24,56($20)
-	ldq $25,56($21)
-
-	ldq $31,256($17)
-	xor $28,$1,$1
-	ldq $31,256($18)
-	xor $2,$3,$3		# 9 cycles from $3 load
-
-	ldq $31,256($19)
-	xor $3,$4,$4		# 9 cycles from $4 load
-	ldq $31,256($20)
-	xor $5,$6,$6		# 8 cycles from $6 load
-
-	stq $1,40($17)
-	xor $4,$6,$6
-	xor $7,$22,$22		# 7 cycles from $22 load
-	xor $23,$24,$24		# 6 cycles from $24 load
-
-	stq $6,48($17)
-	xor $22,$24,$24
-	ldq $31,256($21)
-	xor $24,$25,$25		# 8 cycles from $25 load
-
-	stq $25,56($17)
-	subq $16,1,$16
-	addq $21,64,$21
-	addq $20,64,$20
-
-	addq $19,64,$19
-	addq $18,64,$18
-	addq $17,64,$17
-	bgt $16,5b
-
-	ret
-	.end xor_alpha_prefetch_5
+asm("								\n\
+	.text							\n\
+	.align 3						\n\
+	.ent xor_alpha_2					\n\
+xor_alpha_2:							\n\
+	.prologue 0						\n\
+	srl $16, 6, $16						\n\
+	.align 4						\n\
+2:								\n\
+	ldq $0,0($17)						\n\
+	ldq $1,0($18)						\n\
+	ldq $2,8($17)						\n\
+	ldq $3,8($18)						\n\
+								\n\
+	ldq $4,16($17)						\n\
+	ldq $5,16($18)						\n\
+	ldq $6,24($17)						\n\
+	ldq $7,24($18)						\n\
+								\n\
+	ldq $19,32($17)						\n\
+	ldq $20,32($18)						\n\
+	ldq $21,40($17)						\n\
+	ldq $22,40($18)						\n\
+								\n\
+	ldq $23,48($17)						\n\
+	ldq $24,48($18)						\n\
+	ldq $25,56($17)						\n\
+	xor $0,$1,$0		# 7 cycles from $1 load		\n\
+								\n\
+	ldq $27,56($18)						\n\
+	xor $2,$3,$2						\n\
+	stq $0,0($17)						\n\
+	xor $4,$5,$4						\n\
+								\n\
+	stq $2,8($17)						\n\
+	xor $6,$7,$6						\n\
+	stq $4,16($17)						\n\
+	xor $19,$20,$19						\n\
+								\n\
+	stq $6,24($17)						\n\
+	xor $21,$22,$21						\n\
+	stq $19,32($17)						\n\
+	xor $23,$24,$23						\n\
+								\n\
+	stq $21,40($17)						\n\
+	xor $25,$27,$25						\n\
+	stq $23,48($17)						\n\
+	subq $16,1,$16						\n\
+								\n\
+	stq $25,56($17)						\n\
+	addq $17,64,$17						\n\
+	addq $18,64,$18						\n\
+	bgt $16,2b						\n\
+								\n\
+	ret							\n\
+	.end xor_alpha_2					\n\
+								\n\
+	.align 3						\n\
+	.ent xor_alpha_3					\n\
+xor_alpha_3:							\n\
+	.prologue 0						\n\
+	srl $16, 6, $16						\n\
+	.align 4						\n\
+3:								\n\
+	ldq $0,0($17)						\n\
+	ldq $1,0($18)						\n\
+	ldq $2,0($19)						\n\
+	ldq $3,8($17)						\n\
+								\n\
+	ldq $4,8($18)						\n\
+	ldq $6,16($17)						\n\
+	ldq $7,16($18)						\n\
+	ldq $21,24($17)						\n\
+								\n\
+	ldq $22,24($18)						\n\
+	ldq $24,32($17)						\n\
+	ldq $25,32($18)						\n\
+	ldq $5,8($19)						\n\
+								\n\
+	ldq $20,16($19)						\n\
+	ldq $23,24($19)						\n\
+	ldq $27,32($19)						\n\
+	nop							\n\
+								\n\
+	xor $0,$1,$1		# 8 cycles from $0 load		\n\
+	xor $3,$4,$4		# 6 cycles from $4 load		\n\
+	xor $6,$7,$7		# 6 cycles from $7 load		\n\
+	xor $21,$22,$22		# 5 cycles from $22 load	\n\
+								\n\
+	xor $1,$2,$2		# 9 cycles from $2 load		\n\
+	xor $24,$25,$25		# 5 cycles from $25 load	\n\
+	stq $2,0($17)						\n\
+	xor $4,$5,$5		# 6 cycles from $5 load		\n\
+								\n\
+	stq $5,8($17)						\n\
+	xor $7,$20,$20		# 7 cycles from $20 load	\n\
+	stq $20,16($17)						\n\
+	xor $22,$23,$23		# 7 cycles from $23 load	\n\
+								\n\
+	stq $23,24($17)						\n\
+	xor $25,$27,$27		# 7 cycles from $27 load	\n\
+	stq $27,32($17)						\n\
+	nop							\n\
+								\n\
+	ldq $0,40($17)						\n\
+	ldq $1,40($18)						\n\
+	ldq $3,48($17)						\n\
+	ldq $4,48($18)						\n\
+								\n\
+	ldq $6,56($17)						\n\
+	ldq $7,56($18)						\n\
+	ldq $2,40($19)						\n\
+	ldq $5,48($19)						\n\
+								\n\
+	ldq $20,56($19)						\n\
+	xor $0,$1,$1		# 4 cycles from $1 load		\n\
+	xor $3,$4,$4		# 5 cycles from $4 load		\n\
+	xor $6,$7,$7		# 5 cycles from $7 load		\n\
+								\n\
+	xor $1,$2,$2		# 4 cycles from $2 load		\n\
+	xor $4,$5,$5		# 5 cycles from $5 load		\n\
+	stq $2,40($17)						\n\
+	xor $7,$20,$20		# 4 cycles from $20 load	\n\
+								\n\
+	stq $5,48($17)						\n\
+	subq $16,1,$16						\n\
+	stq $20,56($17)						\n\
+	addq $19,64,$19						\n\
+								\n\
+	addq $18,64,$18						\n\
+	addq $17,64,$17						\n\
+	bgt $16,3b						\n\
+	ret							\n\
+	.end xor_alpha_3					\n\
+								\n\
+	.align 3						\n\
+	.ent xor_alpha_4					\n\
+xor_alpha_4:							\n\
+	.prologue 0						\n\
+	srl $16, 6, $16						\n\
+	.align 4						\n\
+4:								\n\
+	ldq $0,0($17)						\n\
+	ldq $1,0($18)						\n\
+	ldq $2,0($19)						\n\
+	ldq $3,0($20)						\n\
+								\n\
+	ldq $4,8($17)						\n\
+	ldq $5,8($18)						\n\
+	ldq $6,8($19)						\n\
+	ldq $7,8($20)						\n\
+								\n\
+	ldq $21,16($17)						\n\
+	ldq $22,16($18)						\n\
+	ldq $23,16($19)						\n\
+	ldq $24,16($20)						\n\
+								\n\
+	ldq $25,24($17)						\n\
+	xor $0,$1,$1		# 6 cycles from $1 load		\n\
+	ldq $27,24($18)						\n\
+	xor $2,$3,$3		# 6 cycles from $3 load		\n\
+								\n\
+	ldq $0,24($19)						\n\
+	xor $1,$3,$3						\n\
+	ldq $1,24($20)						\n\
+	xor $4,$5,$5		# 7 cycles from $5 load		\n\
+								\n\
+	stq $3,0($17)						\n\
+	xor $6,$7,$7						\n\
+	xor $21,$22,$22		# 7 cycles from $22 load	\n\
+	xor $5,$7,$7						\n\
+								\n\
+	stq $7,8($17)						\n\
+	xor $23,$24,$24		# 7 cycles from $24 load	\n\
+	ldq $2,32($17)						\n\
+	xor $22,$24,$24						\n\
+								\n\
+	ldq $3,32($18)						\n\
+	ldq $4,32($19)						\n\
+	ldq $5,32($20)						\n\
+	xor $25,$27,$27		# 8 cycles from $27 load	\n\
+								\n\
+	ldq $6,40($17)						\n\
+	ldq $7,40($18)						\n\
+	ldq $21,40($19)						\n\
+	ldq $22,40($20)						\n\
+								\n\
+	stq $24,16($17)						\n\
+	xor $0,$1,$1		# 9 cycles from $1 load		\n\
+	xor $2,$3,$3		# 5 cycles from $3 load		\n\
+	xor $27,$1,$1						\n\
+								\n\
+	stq $1,24($17)						\n\
+	xor $4,$5,$5		# 5 cycles from $5 load		\n\
+	ldq $23,48($17)						\n\
+	ldq $24,48($18)						\n\
+								\n\
+	ldq $25,48($19)						\n\
+	xor $3,$5,$5						\n\
+	ldq $27,48($20)						\n\
+	ldq $0,56($17)						\n\
+								\n\
+	ldq $1,56($18)						\n\
+	ldq $2,56($19)						\n\
+	xor $6,$7,$7		# 8 cycles from $6 load		\n\
+	ldq $3,56($20)						\n\
+								\n\
+	stq $5,32($17)						\n\
+	xor $21,$22,$22		# 8 cycles from $22 load	\n\
+	xor $7,$22,$22						\n\
+	xor $23,$24,$24		# 5 cycles from $24 load	\n\
+								\n\
+	stq $22,40($17)						\n\
+	xor $25,$27,$27		# 5 cycles from $27 load	\n\
+	xor $24,$27,$27						\n\
+	xor $0,$1,$1		# 5 cycles from $1 load		\n\
+								\n\
+	stq $27,48($17)						\n\
+	xor $2,$3,$3		# 4 cycles from $3 load		\n\
+	xor $1,$3,$3						\n\
+	subq $16,1,$16						\n\
+								\n\
+	stq $3,56($17)						\n\
+	addq $20,64,$20						\n\
+	addq $19,64,$19						\n\
+	addq $18,64,$18						\n\
+								\n\
+	addq $17,64,$17						\n\
+	bgt $16,4b						\n\
+	ret							\n\
+	.end xor_alpha_4					\n\
+								\n\
+	.align 3						\n\
+	.ent xor_alpha_5					\n\
+xor_alpha_5:							\n\
+	.prologue 0						\n\
+	srl $16, 6, $16						\n\
+	.align 4						\n\
+5:								\n\
+	ldq $0,0($17)						\n\
+	ldq $1,0($18)						\n\
+	ldq $2,0($19)						\n\
+	ldq $3,0($20)						\n\
+								\n\
+	ldq $4,0($21)						\n\
+	ldq $5,8($17)						\n\
+	ldq $6,8($18)						\n\
+	ldq $7,8($19)						\n\
+								\n\
+	ldq $22,8($20)						\n\
+	ldq $23,8($21)						\n\
+	ldq $24,16($17)						\n\
+	ldq $25,16($18)						\n\
+								\n\
+	ldq $27,16($19)						\n\
+	xor $0,$1,$1		# 6 cycles from $1 load		\n\
+	ldq $28,16($20)						\n\
+	xor $2,$3,$3		# 6 cycles from $3 load		\n\
+								\n\
+	ldq $0,16($21)						\n\
+	xor $1,$3,$3						\n\
+	ldq $1,24($17)						\n\
+	xor $3,$4,$4		# 7 cycles from $4 load		\n\
+								\n\
+	stq $4,0($17)						\n\
+	xor $5,$6,$6		# 7 cycles from $6 load		\n\
+	xor $7,$22,$22		# 7 cycles from $22 load	\n\
+	xor $6,$23,$23		# 7 cycles from $23 load	\n\
+								\n\
+	ldq $2,24($18)						\n\
+	xor $22,$23,$23						\n\
+	ldq $3,24($19)						\n\
+	xor $24,$25,$25		# 8 cycles from $25 load	\n\
+								\n\
+	stq $23,8($17)						\n\
+	xor $25,$27,$27		# 8 cycles from $27 load	\n\
+	ldq $4,24($20)						\n\
+	xor $28,$0,$0		# 7 cycles from $0 load		\n\
+								\n\
+	ldq $5,24($21)						\n\
+	xor $27,$0,$0						\n\
+	ldq $6,32($17)						\n\
+	ldq $7,32($18)						\n\
+								\n\
+	stq $0,16($17)						\n\
+	xor $1,$2,$2		# 6 cycles from $2 load		\n\
+	ldq $22,32($19)						\n\
+	xor $3,$4,$4		# 4 cycles from $4 load		\n\
+								\n\
+	ldq $23,32($20)						\n\
+	xor $2,$4,$4						\n\
+	ldq $24,32($21)						\n\
+	ldq $25,40($17)						\n\
+								\n\
+	ldq $27,40($18)						\n\
+	ldq $28,40($19)						\n\
+	ldq $0,40($20)						\n\
+	xor $4,$5,$5		# 7 cycles from $5 load		\n\
+								\n\
+	stq $5,24($17)						\n\
+	xor $6,$7,$7		# 7 cycles from $7 load		\n\
+	ldq $1,40($21)						\n\
+	ldq $2,48($17)						\n\
+								\n\
+	ldq $3,48($18)						\n\
+	xor $7,$22,$22		# 7 cycles from $22 load	\n\
+	ldq $4,48($19)						\n\
+	xor $23,$24,$24		# 6 cycles from $24 load	\n\
+								\n\
+	ldq $5,48($20)						\n\
+	xor $22,$24,$24						\n\
+	ldq $6,48($21)						\n\
+	xor $25,$27,$27		# 7 cycles from $27 load	\n\
+								\n\
+	stq $24,32($17)						\n\
+	xor $27,$28,$28		# 8 cycles from $28 load	\n\
+	ldq $7,56($17)						\n\
+	xor $0,$1,$1		# 6 cycles from $1 load		\n\
+								\n\
+	ldq $22,56($18)						\n\
+	ldq $23,56($19)						\n\
+	ldq $24,56($20)						\n\
+	ldq $25,56($21)						\n\
+								\n\
+	xor $28,$1,$1						\n\
+	xor $2,$3,$3		# 9 cycles from $3 load		\n\
+	xor $3,$4,$4		# 9 cycles from $4 load		\n\
+	xor $5,$6,$6		# 8 cycles from $6 load		\n\
+								\n\
+	stq $1,40($17)						\n\
+	xor $4,$6,$6						\n\
+	xor $7,$22,$22		# 7 cycles from $22 load	\n\
+	xor $23,$24,$24		# 6 cycles from $24 load	\n\
+								\n\
+	stq $6,48($17)						\n\
+	xor $22,$24,$24						\n\
+	subq $16,1,$16						\n\
+	xor $24,$25,$25		# 8 cycles from $25 load	\n\
+								\n\
+	stq $25,56($17)						\n\
+	addq $21,64,$21						\n\
+	addq $20,64,$20						\n\
+	addq $19,64,$19						\n\
+								\n\
+	addq $18,64,$18						\n\
+	addq $17,64,$17						\n\
+	bgt $16,5b						\n\
+	ret							\n\
+	.end xor_alpha_5					\n\
+								\n\
+	.align 3						\n\
+	.ent xor_alpha_prefetch_2				\n\
+xor_alpha_prefetch_2:						\n\
+	.prologue 0						\n\
+	srl $16, 6, $16						\n\
+								\n\
+	ldq $31, 0($17)						\n\
+	ldq $31, 0($18)						\n\
+								\n\
+	ldq $31, 64($17)					\n\
+	ldq $31, 64($18)					\n\
+								\n\
+	ldq $31, 128($17)					\n\
+	ldq $31, 128($18)					\n\
+								\n\
+	ldq $31, 192($17)					\n\
+	ldq $31, 192($18)					\n\
+	.align 4						\n\
+2:								\n\
+	ldq $0,0($17)						\n\
+	ldq $1,0($18)						\n\
+	ldq $2,8($17)						\n\
+	ldq $3,8($18)						\n\
+								\n\
+	ldq $4,16($17)						\n\
+	ldq $5,16($18)						\n\
+	ldq $6,24($17)						\n\
+	ldq $7,24($18)						\n\
+								\n\
+	ldq $19,32($17)						\n\
+	ldq $20,32($18)						\n\
+	ldq $21,40($17)						\n\
+	ldq $22,40($18)						\n\
+								\n\
+	ldq $23,48($17)						\n\
+	ldq $24,48($18)						\n\
+	ldq $25,56($17)						\n\
+	ldq $27,56($18)						\n\
+								\n\
+	ldq $31,256($17)					\n\
+	xor $0,$1,$0		# 8 cycles from $1 load		\n\
+	ldq $31,256($18)					\n\
+	xor $2,$3,$2						\n\
+								\n\
+	stq $0,0($17)						\n\
+	xor $4,$5,$4						\n\
+	stq $2,8($17)						\n\
+	xor $6,$7,$6						\n\
+								\n\
+	stq $4,16($17)						\n\
+	xor $19,$20,$19						\n\
+	stq $6,24($17)						\n\
+	xor $21,$22,$21						\n\
+								\n\
+	stq $19,32($17)						\n\
+	xor $23,$24,$23						\n\
+	stq $21,40($17)						\n\
+	xor $25,$27,$25						\n\
+								\n\
+	stq $23,48($17)						\n\
+	subq $16,1,$16						\n\
+	stq $25,56($17)						\n\
+	addq $17,64,$17						\n\
+								\n\
+	addq $18,64,$18						\n\
+	bgt $16,2b						\n\
+	ret							\n\
+	.end xor_alpha_prefetch_2				\n\
+								\n\
+	.align 3						\n\
+	.ent xor_alpha_prefetch_3				\n\
+xor_alpha_prefetch_3:						\n\
+	.prologue 0						\n\
+	srl $16, 6, $16						\n\
+								\n\
+	ldq $31, 0($17)						\n\
+	ldq $31, 0($18)						\n\
+	ldq $31, 0($19)						\n\
+								\n\
+	ldq $31, 64($17)					\n\
+	ldq $31, 64($18)					\n\
+	ldq $31, 64($19)					\n\
+								\n\
+	ldq $31, 128($17)					\n\
+	ldq $31, 128($18)					\n\
+	ldq $31, 128($19)					\n\
+								\n\
+	ldq $31, 192($17)					\n\
+	ldq $31, 192($18)					\n\
+	ldq $31, 192($19)					\n\
+	.align 4						\n\
+3:								\n\
+	ldq $0,0($17)						\n\
+	ldq $1,0($18)						\n\
+	ldq $2,0($19)						\n\
+	ldq $3,8($17)						\n\
+								\n\
+	ldq $4,8($18)						\n\
+	ldq $6,16($17)						\n\
+	ldq $7,16($18)						\n\
+	ldq $21,24($17)						\n\
+								\n\
+	ldq $22,24($18)						\n\
+	ldq $24,32($17)						\n\
+	ldq $25,32($18)						\n\
+	ldq $5,8($19)						\n\
+								\n\
+	ldq $20,16($19)						\n\
+	ldq $23,24($19)						\n\
+	ldq $27,32($19)						\n\
+	nop							\n\
+								\n\
+	xor $0,$1,$1		# 8 cycles from $0 load		\n\
+	xor $3,$4,$4		# 7 cycles from $4 load		\n\
+	xor $6,$7,$7		# 6 cycles from $7 load		\n\
+	xor $21,$22,$22		# 5 cycles from $22 load	\n\
+								\n\
+	xor $1,$2,$2		# 9 cycles from $2 load		\n\
+	xor $24,$25,$25		# 5 cycles from $25 load	\n\
+	stq $2,0($17)						\n\
+	xor $4,$5,$5		# 6 cycles from $5 load		\n\
+								\n\
+	stq $5,8($17)						\n\
+	xor $7,$20,$20		# 7 cycles from $20 load	\n\
+	stq $20,16($17)						\n\
+	xor $22,$23,$23		# 7 cycles from $23 load	\n\
+								\n\
+	stq $23,24($17)						\n\
+	xor $25,$27,$27		# 7 cycles from $27 load	\n\
+	stq $27,32($17)						\n\
+	nop							\n\
+								\n\
+	ldq $0,40($17)						\n\
+	ldq $1,40($18)						\n\
+	ldq $3,48($17)						\n\
+	ldq $4,48($18)						\n\
+								\n\
+	ldq $6,56($17)						\n\
+	ldq $7,56($18)						\n\
+	ldq $2,40($19)						\n\
+	ldq $5,48($19)						\n\
+								\n\
+	ldq $20,56($19)						\n\
+	ldq $31,256($17)					\n\
+	ldq $31,256($18)					\n\
+	ldq $31,256($19)					\n\
+								\n\
+	xor $0,$1,$1		# 6 cycles from $1 load		\n\
+	xor $3,$4,$4		# 5 cycles from $4 load		\n\
+	xor $6,$7,$7		# 5 cycles from $7 load		\n\
+	xor $1,$2,$2		# 4 cycles from $2 load		\n\
+								\n\
+	xor $4,$5,$5		# 5 cycles from $5 load		\n\
+	xor $7,$20,$20		# 4 cycles from $20 load	\n\
+	stq $2,40($17)						\n\
+	subq $16,1,$16						\n\
+								\n\
+	stq $5,48($17)						\n\
+	addq $19,64,$19						\n\
+	stq $20,56($17)						\n\
+	addq $18,64,$18						\n\
+								\n\
+	addq $17,64,$17						\n\
+	bgt $16,3b						\n\
+	ret							\n\
+	.end xor_alpha_prefetch_3				\n\
+								\n\
+	.align 3						\n\
+	.ent xor_alpha_prefetch_4				\n\
+xor_alpha_prefetch_4:						\n\
+	.prologue 0						\n\
+	srl $16, 6, $16						\n\
+								\n\
+	ldq $31, 0($17)						\n\
+	ldq $31, 0($18)						\n\
+	ldq $31, 0($19)						\n\
+	ldq $31, 0($20)						\n\
+								\n\
+	ldq $31, 64($17)					\n\
+	ldq $31, 64($18)					\n\
+	ldq $31, 64($19)					\n\
+	ldq $31, 64($20)					\n\
+								\n\
+	ldq $31, 128($17)					\n\
+	ldq $31, 128($18)					\n\
+	ldq $31, 128($19)					\n\
+	ldq $31, 128($20)					\n\
+								\n\
+	ldq $31, 192($17)					\n\
+	ldq $31, 192($18)					\n\
+	ldq $31, 192($19)					\n\
+	ldq $31, 192($20)					\n\
+	.align 4						\n\
+4:								\n\
+	ldq $0,0($17)						\n\
+	ldq $1,0($18)						\n\
+	ldq $2,0($19)						\n\
+	ldq $3,0($20)						\n\
+								\n\
+	ldq $4,8($17)						\n\
+	ldq $5,8($18)						\n\
+	ldq $6,8($19)						\n\
+	ldq $7,8($20)						\n\
+								\n\
+	ldq $21,16($17)						\n\
+	ldq $22,16($18)						\n\
+	ldq $23,16($19)						\n\
+	ldq $24,16($20)						\n\
+								\n\
+	ldq $25,24($17)						\n\
+	xor $0,$1,$1		# 6 cycles from $1 load		\n\
+	ldq $27,24($18)						\n\
+	xor $2,$3,$3		# 6 cycles from $3 load		\n\
+								\n\
+	ldq $0,24($19)						\n\
+	xor $1,$3,$3						\n\
+	ldq $1,24($20)						\n\
+	xor $4,$5,$5		# 7 cycles from $5 load		\n\
+								\n\
+	stq $3,0($17)						\n\
+	xor $6,$7,$7						\n\
+	xor $21,$22,$22		# 7 cycles from $22 load	\n\
+	xor $5,$7,$7						\n\
+								\n\
+	stq $7,8($17)						\n\
+	xor $23,$24,$24		# 7 cycles from $24 load	\n\
+	ldq $2,32($17)						\n\
+	xor $22,$24,$24						\n\
+								\n\
+	ldq $3,32($18)						\n\
+	ldq $4,32($19)						\n\
+	ldq $5,32($20)						\n\
+	xor $25,$27,$27		# 8 cycles from $27 load	\n\
+								\n\
+	ldq $6,40($17)						\n\
+	ldq $7,40($18)						\n\
+	ldq $21,40($19)						\n\
+	ldq $22,40($20)						\n\
+								\n\
+	stq $24,16($17)						\n\
+	xor $0,$1,$1		# 9 cycles from $1 load		\n\
+	xor $2,$3,$3		# 5 cycles from $3 load		\n\
+	xor $27,$1,$1						\n\
+								\n\
+	stq $1,24($17)						\n\
+	xor $4,$5,$5		# 5 cycles from $5 load		\n\
+	ldq $23,48($17)						\n\
+	xor $3,$5,$5						\n\
+								\n\
+	ldq $24,48($18)						\n\
+	ldq $25,48($19)						\n\
+	ldq $27,48($20)						\n\
+	ldq $0,56($17)						\n\
+								\n\
+	ldq $1,56($18)						\n\
+	ldq $2,56($19)						\n\
+	ldq $3,56($20)						\n\
+	xor $6,$7,$7		# 8 cycles from $6 load		\n\
+								\n\
+	ldq $31,256($17)					\n\
+	xor $21,$22,$22		# 8 cycles from $22 load	\n\
+	ldq $31,256($18)					\n\
+	xor $7,$22,$22						\n\
+								\n\
+	ldq $31,256($19)					\n\
+	xor $23,$24,$24		# 6 cycles from $24 load	\n\
+	ldq $31,256($20)					\n\
+	xor $25,$27,$27		# 6 cycles from $27 load	\n\
+								\n\
+	stq $5,32($17)						\n\
+	xor $24,$27,$27						\n\
+	xor $0,$1,$1		# 7 cycles from $1 load		\n\
+	xor $2,$3,$3		# 6 cycles from $3 load		\n\
+								\n\
+	stq $22,40($17)						\n\
+	xor $1,$3,$3						\n\
+	stq $27,48($17)						\n\
+	subq $16,1,$16						\n\
+								\n\
+	stq $3,56($17)						\n\
+	addq $20,64,$20						\n\
+	addq $19,64,$19						\n\
+	addq $18,64,$18						\n\
+								\n\
+	addq $17,64,$17						\n\
+	bgt $16,4b						\n\
+	ret							\n\
+	.end xor_alpha_prefetch_4				\n\
+								\n\
+	.align 3						\n\
+	.ent xor_alpha_prefetch_5				\n\
+xor_alpha_prefetch_5:						\n\
+	.prologue 0						\n\
+	srl $16, 6, $16						\n\
+								\n\
+	ldq $31, 0($17)						\n\
+	ldq $31, 0($18)						\n\
+	ldq $31, 0($19)						\n\
+	ldq $31, 0($20)						\n\
+	ldq $31, 0($21)						\n\
+								\n\
+	ldq $31, 64($17)					\n\
+	ldq $31, 64($18)					\n\
+	ldq $31, 64($19)					\n\
+	ldq $31, 64($20)					\n\
+	ldq $31, 64($21)					\n\
+								\n\
+	ldq $31, 128($17)					\n\
+	ldq $31, 128($18)					\n\
+	ldq $31, 128($19)					\n\
+	ldq $31, 128($20)					\n\
+	ldq $31, 128($21)					\n\
+								\n\
+	ldq $31, 192($17)					\n\
+	ldq $31, 192($18)					\n\
+	ldq $31, 192($19)					\n\
+	ldq $31, 192($20)					\n\
+	ldq $31, 192($21)					\n\
+	.align 4						\n\
+5:								\n\
+	ldq $0,0($17)						\n\
+	ldq $1,0($18)						\n\
+	ldq $2,0($19)						\n\
+	ldq $3,0($20)						\n\
+								\n\
+	ldq $4,0($21)						\n\
+	ldq $5,8($17)						\n\
+	ldq $6,8($18)						\n\
+	ldq $7,8($19)						\n\
+								\n\
+	ldq $22,8($20)						\n\
+	ldq $23,8($21)						\n\
+	ldq $24,16($17)						\n\
+	ldq $25,16($18)						\n\
+								\n\
+	ldq $27,16($19)						\n\
+	xor $0,$1,$1		# 6 cycles from $1 load		\n\
+	ldq $28,16($20)						\n\
+	xor $2,$3,$3		# 6 cycles from $3 load		\n\
+								\n\
+	ldq $0,16($21)						\n\
+	xor $1,$3,$3						\n\
+	ldq $1,24($17)						\n\
+	xor $3,$4,$4		# 7 cycles from $4 load		\n\
+								\n\
+	stq $4,0($17)						\n\
+	xor $5,$6,$6		# 7 cycles from $6 load		\n\
+	xor $7,$22,$22		# 7 cycles from $22 load	\n\
+	xor $6,$23,$23		# 7 cycles from $23 load	\n\
+								\n\
+	ldq $2,24($18)						\n\
+	xor $22,$23,$23						\n\
+	ldq $3,24($19)						\n\
+	xor $24,$25,$25		# 8 cycles from $25 load	\n\
+								\n\
+	stq $23,8($17)						\n\
+	xor $25,$27,$27		# 8 cycles from $27 load	\n\
+	ldq $4,24($20)						\n\
+	xor $28,$0,$0		# 7 cycles from $0 load		\n\
+								\n\
+	ldq $5,24($21)						\n\
+	xor $27,$0,$0						\n\
+	ldq $6,32($17)						\n\
+	ldq $7,32($18)						\n\
+								\n\
+	stq $0,16($17)						\n\
+	xor $1,$2,$2		# 6 cycles from $2 load		\n\
+	ldq $22,32($19)						\n\
+	xor $3,$4,$4		# 4 cycles from $4 load		\n\
+								\n\
+	ldq $23,32($20)						\n\
+	xor $2,$4,$4						\n\
+	ldq $24,32($21)						\n\
+	ldq $25,40($17)						\n\
+								\n\
+	ldq $27,40($18)						\n\
+	ldq $28,40($19)						\n\
+	ldq $0,40($20)						\n\
+	xor $4,$5,$5		# 7 cycles from $5 load		\n\
+								\n\
+	stq $5,24($17)						\n\
+	xor $6,$7,$7		# 7 cycles from $7 load		\n\
+	ldq $1,40($21)						\n\
+	ldq $2,48($17)						\n\
+								\n\
+	ldq $3,48($18)						\n\
+	xor $7,$22,$22		# 7 cycles from $22 load	\n\
+	ldq $4,48($19)						\n\
+	xor $23,$24,$24		# 6 cycles from $24 load	\n\
+								\n\
+	ldq $5,48($20)						\n\
+	xor $22,$24,$24						\n\
+	ldq $6,48($21)						\n\
+	xor $25,$27,$27		# 7 cycles from $27 load	\n\
+								\n\
+	stq $24,32($17)						\n\
+	xor $27,$28,$28		# 8 cycles from $28 load	\n\
+	ldq $7,56($17)						\n\
+	xor $0,$1,$1		# 6 cycles from $1 load		\n\
+								\n\
+	ldq $22,56($18)						\n\
+	ldq $23,56($19)						\n\
+	ldq $24,56($20)						\n\
+	ldq $25,56($21)						\n\
+								\n\
+	ldq $31,256($17)					\n\
+	xor $28,$1,$1						\n\
+	ldq $31,256($18)					\n\
+	xor $2,$3,$3		# 9 cycles from $3 load		\n\
+								\n\
+	ldq $31,256($19)					\n\
+	xor $3,$4,$4		# 9 cycles from $4 load		\n\
+	ldq $31,256($20)					\n\
+	xor $5,$6,$6		# 8 cycles from $6 load		\n\
+								\n\
+	stq $1,40($17)						\n\
+	xor $4,$6,$6						\n\
+	xor $7,$22,$22		# 7 cycles from $22 load	\n\
+	xor $23,$24,$24		# 6 cycles from $24 load	\n\
+								\n\
+	stq $6,48($17)						\n\
+	xor $22,$24,$24						\n\
+	ldq $31,256($21)					\n\
+	xor $24,$25,$25		# 8 cycles from $25 load	\n\
+								\n\
+	stq $25,56($17)						\n\
+	subq $16,1,$16						\n\
+	addq $21,64,$21						\n\
+	addq $20,64,$20						\n\
+								\n\
+	addq $19,64,$19						\n\
+	addq $18,64,$18						\n\
+	addq $17,64,$17						\n\
+	bgt $16,5b						\n\
+								\n\
+	ret							\n\
+	.end xor_alpha_prefetch_5				\n\
 ");
 
 static struct xor_block_template xor_block_alpha = {
-	name: "alpha",
-	do_2: xor_alpha_2,
-	do_3: xor_alpha_3,
-	do_4: xor_alpha_4,
-	do_5: xor_alpha_5,
+	.name	= "alpha",
+	.do_2	= xor_alpha_2,
+	.do_3	= xor_alpha_3,
+	.do_4	= xor_alpha_4,
+	.do_5	= xor_alpha_5,
 };
 
 static struct xor_block_template xor_block_alpha_prefetch = {
-	name: "alpha prefetch",
-	do_2: xor_alpha_prefetch_2,
-	do_3: xor_alpha_prefetch_3,
-	do_4: xor_alpha_prefetch_4,
-	do_5: xor_alpha_prefetch_5,
+	.name	= "alpha prefetch",
+	.do_2	= xor_alpha_prefetch_2,
+	.do_3	= xor_alpha_prefetch_3,
+	.do_4	= xor_alpha_prefetch_4,
+	.do_5	= xor_alpha_prefetch_5,
 };
 
 /* For grins, also test the generic routines.  */