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38a49943 PS |
1 | Index: gcc/doc/invoke.texi |
2 | =================================================================== | |
bed1487f PS |
3 | --- gcc/doc/invoke.texi (.../tags/gcc_4_4_0_release) (revision 146537) |
4 | +++ gcc/doc/invoke.texi (.../branches/ix86/gcc-4_4-branch) (revision 146537) | |
5 | @@ -584,7 +584,7 @@ | |
6 | -m96bit-long-double -mregparm=@var{num} -msseregparm @gol | |
7 | -mveclibabi=@var{type} -mpc32 -mpc64 -mpc80 -mstackrealign @gol | |
8 | -momit-leaf-frame-pointer -mno-red-zone -mno-tls-direct-seg-refs @gol | |
9 | --mcmodel=@var{code-model} @gol | |
10 | +-mcmodel=@var{code-model} -mabi=@var{name} @gol | |
11 | -m32 -m64 -mlarge-data-threshold=@var{num} @gol | |
12 | -mfused-madd -mno-fused-madd -msse2avx} | |
13 | ||
14 | @@ -10959,6 +10959,9 @@ | |
15 | @item core2 | |
16 | Intel Core2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3 | |
17 | instruction set support. | |
18 | +@item atom | |
19 | +Intel Atom CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3 | |
20 | +instruction set support. | |
21 | @item k6 | |
22 | AMD K6 CPU with MMX instruction set support. | |
23 | @item k6-2, k6-3 | |
24 | @@ -11394,6 +11397,16 @@ | |
25 | @option{-funsafe-math-optimizations} have to be enabled. A SVML or ACML ABI | |
26 | compatible library will have to be specified at link time. | |
27 | ||
28 | +@item -mabi=@var{name} | |
29 | +@opindex mabi | |
30 | +Generate code for the specified calling convention. Permissible values | |
31 | +are: @samp{sysv} for the ABI used on GNU/Linux and other systems and | |
32 | +@samp{ms} for the Microsoft ABI. The default is to use the Microsoft | |
33 | +ABI when targeting Windows. On all other systems, the default is the | |
34 | +SYSV ABI. You can control this behavior for a specific function by | |
35 | +using the function attribute @samp{ms_abi}/@samp{sysv_abi}. | |
36 | +@xref{Function Attributes}. | |
37 | + | |
38 | @item -mpush-args | |
39 | @itemx -mno-push-args | |
40 | @opindex mpush-args | |
41 | Index: gcc/doc/md.texi | |
38a49943 | 42 | =================================================================== |
bed1487f PS |
43 | --- gcc/doc/md.texi (.../tags/gcc_4_4_0_release) (revision 146537) |
44 | +++ gcc/doc/md.texi (.../branches/ix86/gcc-4_4-branch) (revision 146537) | |
45 | @@ -7506,6 +7506,11 @@ | |
46 | recognize complicated bypasses, e.g.@: when the consumer is only an address | |
47 | of insn @samp{store} (not a stored value). | |
48 | ||
49 | +If there are more one bypass with the same output and input insns, the | |
50 | +chosen bypass is the first bypass with a guard in description whose | |
51 | +guard function returns nonzero. If there is no such bypass, then | |
52 | +bypass without the guard function is chosen. | |
53 | + | |
54 | @findex exclusion_set | |
55 | @findex presence_set | |
56 | @findex final_presence_set | |
57 | Index: gcc/genautomata.c | |
38a49943 | 58 | =================================================================== |
bed1487f PS |
59 | --- gcc/genautomata.c (.../tags/gcc_4_4_0_release) (revision 146537) |
60 | +++ gcc/genautomata.c (.../branches/ix86/gcc-4_4-branch) (revision 146537) | |
61 | @@ -1,5 +1,5 @@ | |
62 | /* Pipeline hazard description translator. | |
63 | - Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008 | |
64 | + Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 | |
65 | Free Software Foundation, Inc. | |
66 | ||
67 | Written by Vladimir Makarov <vmakarov@redhat.com> | |
68 | @@ -22,21 +22,25 @@ | |
69 | ||
70 | /* References: | |
71 | ||
72 | - 1. Detecting pipeline structural hazards quickly. T. Proebsting, | |
73 | + 1. The finite state automaton based pipeline hazard recognizer and | |
74 | + instruction scheduler in GCC. V. Makarov. Proceedings of GCC | |
75 | + summit, 2003. | |
76 | + | |
77 | + 2. Detecting pipeline structural hazards quickly. T. Proebsting, | |
78 | C. Fraser. Proceedings of ACM SIGPLAN-SIGACT Symposium on | |
79 | Principles of Programming Languages, pages 280--286, 1994. | |
80 | ||
81 | This article is a good start point to understand usage of finite | |
82 | state automata for pipeline hazard recognizers. But I'd | |
83 | - recommend the 2nd article for more deep understanding. | |
84 | + recommend the 1st and 3rd article for more deep understanding. | |
85 | ||
86 | - 2. Efficient Instruction Scheduling Using Finite State Automata: | |
87 | + 3. Efficient Instruction Scheduling Using Finite State Automata: | |
88 | V. Bala and N. Rubin, Proceedings of MICRO-28. This is the best | |
89 | article about usage of finite state automata for pipeline hazard | |
90 | recognizers. | |
91 | ||
92 | - The current implementation is different from the 2nd article in the | |
93 | - following: | |
94 | + The current implementation is described in the 1st article and it | |
95 | + is different from the 3rd article in the following: | |
96 | ||
97 | 1. New operator `|' (alternative) is permitted in functional unit | |
98 | reservation which can be treated deterministically and | |
99 | @@ -463,7 +467,10 @@ | |
100 | insn. */ | |
101 | int insn_num; | |
102 | /* The following field value is list of bypasses in which given insn | |
103 | - is output insn. */ | |
104 | + is output insn. Bypasses with the same input insn stay one after | |
105 | + another in the list in the same order as their occurrences in the | |
106 | + description but the bypass without a guard stays always the last | |
107 | + in a row of bypasses with the same input insn. */ | |
108 | struct bypass_decl *bypass_list; | |
109 | ||
110 | /* The following fields are defined by automaton generator. */ | |
111 | @@ -2367,18 +2374,67 @@ | |
38a49943 PS |
112 | } |
113 | ||
bed1487f PS |
114 | |
115 | -/* The function searches for bypass with given IN_INSN_RESERV in given | |
116 | - BYPASS_LIST. */ | |
117 | -static struct bypass_decl * | |
118 | -find_bypass (struct bypass_decl *bypass_list, | |
119 | - struct insn_reserv_decl *in_insn_reserv) | |
120 | +/* The function inserts BYPASS in the list of bypasses of the | |
121 | + corresponding output insn. The order of bypasses in the list is | |
122 | + decribed in a comment for member `bypass_list' (see above). If | |
123 | + there is already the same bypass in the list the function reports | |
124 | + this and does nothing. */ | |
38a49943 | 125 | +static void |
bed1487f PS |
126 | +insert_bypass (struct bypass_decl *bypass) |
127 | { | |
128 | - struct bypass_decl *bypass; | |
129 | - | |
130 | - for (bypass = bypass_list; bypass != NULL; bypass = bypass->next) | |
131 | - if (bypass->in_insn_reserv == in_insn_reserv) | |
132 | - break; | |
133 | - return bypass; | |
134 | + struct bypass_decl *curr, *last; | |
135 | + struct insn_reserv_decl *out_insn_reserv = bypass->out_insn_reserv; | |
136 | + struct insn_reserv_decl *in_insn_reserv = bypass->in_insn_reserv; | |
137 | + | |
138 | + for (curr = out_insn_reserv->bypass_list, last = NULL; | |
139 | + curr != NULL; | |
140 | + last = curr, curr = curr->next) | |
141 | + if (curr->in_insn_reserv == in_insn_reserv) | |
142 | + { | |
143 | + if ((bypass->bypass_guard_name != NULL | |
144 | + && curr->bypass_guard_name != NULL | |
145 | + && ! strcmp (bypass->bypass_guard_name, curr->bypass_guard_name)) | |
146 | + || bypass->bypass_guard_name == curr->bypass_guard_name) | |
147 | + { | |
148 | + if (bypass->bypass_guard_name == NULL) | |
149 | + { | |
150 | + if (!w_flag) | |
151 | + error ("the same bypass `%s - %s' is already defined", | |
152 | + bypass->out_insn_name, bypass->in_insn_name); | |
153 | + else | |
154 | + warning (0, "the same bypass `%s - %s' is already defined", | |
155 | + bypass->out_insn_name, bypass->in_insn_name); | |
156 | + } | |
157 | + else if (!w_flag) | |
158 | + error ("the same bypass `%s - %s' (guard %s) is already defined", | |
159 | + bypass->out_insn_name, bypass->in_insn_name, | |
160 | + bypass->bypass_guard_name); | |
161 | + else | |
162 | + warning | |
163 | + (0, "the same bypass `%s - %s' (guard %s) is already defined", | |
164 | + bypass->out_insn_name, bypass->in_insn_name, | |
165 | + bypass->bypass_guard_name); | |
166 | + return; | |
167 | + } | |
168 | + if (curr->bypass_guard_name == NULL) | |
169 | + break; | |
170 | + if (curr->next == NULL || curr->next->in_insn_reserv != in_insn_reserv) | |
171 | + { | |
172 | + last = curr; | |
173 | + break; | |
174 | + } | |
175 | + | |
176 | + } | |
177 | + if (last == NULL) | |
38a49943 | 178 | + { |
bed1487f PS |
179 | + bypass->next = out_insn_reserv->bypass_list; |
180 | + out_insn_reserv->bypass_list = bypass; | |
38a49943 | 181 | + } |
bed1487f | 182 | + else |
38a49943 | 183 | + { |
bed1487f PS |
184 | + bypass->next = last->next; |
185 | + last->next = bypass; | |
38a49943 | 186 | + } |
bed1487f PS |
187 | } |
188 | ||
189 | /* The function processes pipeline description declarations, checks | |
190 | @@ -2391,7 +2447,6 @@ | |
191 | decl_t decl_in_table; | |
192 | decl_t out_insn_reserv; | |
193 | decl_t in_insn_reserv; | |
194 | - struct bypass_decl *bypass; | |
195 | int automaton_presence; | |
196 | int i; | |
197 | ||
198 | @@ -2514,36 +2569,7 @@ | |
199 | = DECL_INSN_RESERV (out_insn_reserv); | |
200 | DECL_BYPASS (decl)->in_insn_reserv | |
201 | = DECL_INSN_RESERV (in_insn_reserv); | |
202 | - bypass | |
203 | - = find_bypass (DECL_INSN_RESERV (out_insn_reserv)->bypass_list, | |
204 | - DECL_BYPASS (decl)->in_insn_reserv); | |
205 | - if (bypass != NULL) | |
206 | - { | |
207 | - if (DECL_BYPASS (decl)->latency == bypass->latency) | |
208 | - { | |
209 | - if (!w_flag) | |
210 | - error | |
211 | - ("the same bypass `%s - %s' is already defined", | |
212 | - DECL_BYPASS (decl)->out_insn_name, | |
213 | - DECL_BYPASS (decl)->in_insn_name); | |
214 | - else | |
215 | - warning | |
216 | - (0, "the same bypass `%s - %s' is already defined", | |
217 | - DECL_BYPASS (decl)->out_insn_name, | |
218 | - DECL_BYPASS (decl)->in_insn_name); | |
219 | - } | |
220 | - else | |
221 | - error ("bypass `%s - %s' is already defined", | |
222 | - DECL_BYPASS (decl)->out_insn_name, | |
223 | - DECL_BYPASS (decl)->in_insn_name); | |
224 | - } | |
225 | - else | |
226 | - { | |
227 | - DECL_BYPASS (decl)->next | |
228 | - = DECL_INSN_RESERV (out_insn_reserv)->bypass_list; | |
229 | - DECL_INSN_RESERV (out_insn_reserv)->bypass_list | |
230 | - = DECL_BYPASS (decl); | |
231 | - } | |
232 | + insert_bypass (DECL_BYPASS (decl)); | |
233 | } | |
234 | } | |
235 | } | |
236 | @@ -8159,19 +8185,32 @@ | |
237 | (advance_cycle_insn_decl)->insn_num)); | |
238 | fprintf (output_file, " case %d:\n", | |
239 | bypass->in_insn_reserv->insn_num); | |
240 | - if (bypass->bypass_guard_name == NULL) | |
241 | - fprintf (output_file, " return %d;\n", | |
242 | - bypass->latency); | |
243 | - else | |
244 | + for (;;) | |
245 | { | |
246 | - fprintf (output_file, | |
247 | - " if (%s (%s, %s))\n", | |
248 | - bypass->bypass_guard_name, INSN_PARAMETER_NAME, | |
249 | - INSN2_PARAMETER_NAME); | |
250 | - fprintf (output_file, | |
251 | - " return %d;\n break;\n", | |
252 | - bypass->latency); | |
253 | + if (bypass->bypass_guard_name == NULL) | |
254 | + { | |
255 | + gcc_assert (bypass->next == NULL | |
256 | + || (bypass->in_insn_reserv | |
257 | + != bypass->next->in_insn_reserv)); | |
258 | + fprintf (output_file, " return %d;\n", | |
259 | + bypass->latency); | |
260 | + } | |
261 | + else | |
262 | + { | |
263 | + fprintf (output_file, | |
264 | + " if (%s (%s, %s))\n", | |
265 | + bypass->bypass_guard_name, INSN_PARAMETER_NAME, | |
266 | + INSN2_PARAMETER_NAME); | |
267 | + fprintf (output_file, " return %d;\n", | |
268 | + bypass->latency); | |
269 | + } | |
270 | + if (bypass->next == NULL | |
271 | + || bypass->in_insn_reserv != bypass->next->in_insn_reserv) | |
272 | + break; | |
273 | + bypass = bypass->next; | |
274 | } | |
275 | + if (bypass->bypass_guard_name != NULL) | |
276 | + fprintf (output_file, " break;\n"); | |
277 | } | |
278 | fputs (" }\n break;\n", output_file); | |
279 | } | |
280 | Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4a.c | |
38a49943 | 281 | =================================================================== |
bed1487f PS |
282 | --- gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4a.c (.../tags/gcc_4_4_0_release) (revision 0) |
283 | +++ gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4a.c (.../branches/ix86/gcc-4_4-branch) (revision 146537) | |
284 | @@ -0,0 +1,24 @@ | |
285 | +/* Test for cross x86_64<->w64 abi va_list calls. */ | |
286 | +/* { dg-do run { target i?86-*-linux* x86_64-*-linux* } } */ | |
287 | +/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin" } */ | |
288 | +/* { dg-additional-sources "vaarg-4b.c" } */ | |
38a49943 | 289 | + |
bed1487f PS |
290 | +extern __SIZE_TYPE__ __attribute__ ((sysv_abi)) strlen (const char *); |
291 | +extern int __attribute__ ((sysv_abi)) sprintf (char *,const char *, ...); | |
292 | +extern void __attribute__ ((sysv_abi)) abort (void); | |
38a49943 | 293 | + |
bed1487f | 294 | +extern void do_cpy (char *, ...); |
38a49943 | 295 | + |
bed1487f PS |
296 | +int __attribute__ ((sysv_abi)) |
297 | +main () | |
38a49943 | 298 | +{ |
bed1487f | 299 | + char s[256]; |
38a49943 | 300 | + |
bed1487f | 301 | + do_cpy (s, "1","2","3","4", "5", "6", "7", ""); |
38a49943 | 302 | + |
bed1487f PS |
303 | + if (s[0] != '1' || s[1] !='2' || s[2] != '3' || s[3] != '4' |
304 | + || s[4] != '5' || s[5] != '6' || s[6] != '7' || s[7] != 0) | |
305 | + abort (); | |
38a49943 | 306 | + |
bed1487f | 307 | + return 0; |
38a49943 | 308 | +} |
bed1487f | 309 | Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4b.c |
38a49943 | 310 | =================================================================== |
bed1487f PS |
311 | --- gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4b.c (.../tags/gcc_4_4_0_release) (revision 0) |
312 | +++ gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4b.c (.../branches/ix86/gcc-4_4-branch) (revision 146537) | |
313 | @@ -0,0 +1,31 @@ | |
314 | +/* Test for cross x86_64<->w64 abi va_list calls. */ | |
315 | +/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin" } */ | |
38a49943 | 316 | + |
bed1487f | 317 | +#include <stdarg.h> |
38a49943 | 318 | + |
bed1487f PS |
319 | +extern __SIZE_TYPE__ __attribute__ ((sysv_abi)) strlen (const char *); |
320 | +extern int __attribute__ ((sysv_abi)) sprintf (char *, const char *, ...); | |
38a49943 | 321 | + |
bed1487f PS |
322 | +static void |
323 | +vdo_cpy (char *s, va_list argp) | |
38a49943 | 324 | +{ |
bed1487f PS |
325 | + __SIZE_TYPE__ len; |
326 | + char *r = s; | |
327 | + char *e; | |
328 | + *r = 0; | |
329 | + for (;;) { | |
330 | + e = va_arg (argp, char *); | |
331 | + if (*e == 0) break; | |
332 | + sprintf (r,"%s", e); | |
333 | + r += strlen (r); | |
334 | + } | |
335 | +} | |
38a49943 | 336 | + |
bed1487f PS |
337 | +void |
338 | +do_cpy (char *s, ...) | |
339 | +{ | |
340 | + va_list argp; | |
341 | + va_start (argp, s); | |
342 | + vdo_cpy (s, argp); | |
343 | + va_end (argp); | |
38a49943 | 344 | +} |
bed1487f | 345 | Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5a.c |
38a49943 | 346 | =================================================================== |
bed1487f PS |
347 | --- gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5a.c (.../tags/gcc_4_4_0_release) (revision 0) |
348 | +++ gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5a.c (.../branches/ix86/gcc-4_4-branch) (revision 146537) | |
349 | @@ -0,0 +1,17 @@ | |
350 | +/* Test for cross x86_64<->w64 abi va_list calls. */ | |
351 | +/* { dg-do run { target i?86-*-linux* x86_64-*-linux* } } */ | |
352 | +/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin" } */ | |
353 | +/* { dg-additional-sources "vaarg-5b.c" } */ | |
38a49943 | 354 | + |
bed1487f PS |
355 | +extern void __attribute__ ((sysv_abi)) abort (void); |
356 | +extern int fct2 (int, ...); | |
38a49943 | 357 | + |
bed1487f | 358 | +#define SZ_ARGS 1ll,2ll,3ll,4ll,5ll,6ll,7ll,0ll |
38a49943 | 359 | + |
bed1487f PS |
360 | +int __attribute__ ((sysv_abi)) |
361 | +main() | |
38a49943 | 362 | +{ |
bed1487f PS |
363 | + if (fct2 (-1, SZ_ARGS) != 0) |
364 | + abort (); | |
38a49943 PS |
365 | + return 0; |
366 | +} | |
bed1487f | 367 | Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5b.c |
38a49943 | 368 | =================================================================== |
bed1487f PS |
369 | --- gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5b.c (.../tags/gcc_4_4_0_release) (revision 0) |
370 | +++ gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5b.c (.../branches/ix86/gcc-4_4-branch) (revision 146537) | |
371 | @@ -0,0 +1,37 @@ | |
372 | +/* Test for cross x86_64<->w64 abi va_list calls. */ | |
373 | +/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin" } */ | |
38a49943 | 374 | + |
bed1487f | 375 | +#include <stdarg.h> |
38a49943 | 376 | + |
bed1487f | 377 | +#define SZ_ARGS 1ll,2ll,3ll,4ll,5ll,6ll,7ll,0ll |
38a49943 | 378 | + |
bed1487f PS |
379 | +static int __attribute__ ((sysv_abi)) |
380 | +fct1 (va_list argp, ...) | |
38a49943 | 381 | +{ |
bed1487f PS |
382 | + long long p1,p2; |
383 | + int ret = 1; | |
384 | + __builtin_sysv_va_list argp_2; | |
385 | + | |
386 | + __builtin_sysv_va_start (argp_2, argp); | |
387 | + do { | |
388 | + p1 = va_arg (argp_2, long long); | |
389 | + p2 = va_arg (argp, long long); | |
390 | + if (p1 != p2) | |
391 | + ret = 0; | |
392 | + } while (ret && p1 != 0); | |
393 | + __builtin_sysv_va_end (argp_2); | |
394 | + | |
395 | + return ret; | |
38a49943 PS |
396 | +} |
397 | + | |
bed1487f PS |
398 | +int |
399 | +fct2 (int dummy, ...) | |
38a49943 | 400 | +{ |
bed1487f PS |
401 | + va_list argp; |
402 | + int ret = dummy; | |
38a49943 | 403 | + |
bed1487f PS |
404 | + va_start (argp, dummy); |
405 | + ret += fct1 (argp, SZ_ARGS); | |
406 | + va_end (argp); | |
407 | + return ret; | |
38a49943 | 408 | +} |
bed1487f | 409 | Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2a.c |
38a49943 | 410 | =================================================================== |
bed1487f PS |
411 | --- gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2a.c (.../tags/gcc_4_4_0_release) (revision 0) |
412 | +++ gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2a.c (.../branches/ix86/gcc-4_4-branch) (revision 146537) | |
413 | @@ -0,0 +1,17 @@ | |
414 | +/* Test for cross x86_64<->w64 abi standard calls via variable. */ | |
415 | +/* { dg-do run { target i?86-*-linux* x86_64-*-linux* } } */ | |
416 | +/* { dg-options "-O2 -mabi=ms -std=gnu99 -ffast-math -fno-builtin" } */ | |
417 | +/* { dg-additional-sources "func-indirect-2b.c" } */ | |
418 | + | |
419 | +extern void __attribute__ ((sysv_abi)) abort (void); | |
420 | +typedef int (*func)(void *, char *, char *, short, long long); | |
421 | +extern func get_callback (void); | |
422 | + | |
423 | +int __attribute__ ((sysv_abi)) | |
424 | +main () | |
38a49943 | 425 | +{ |
bed1487f PS |
426 | + func callme = get_callback (); |
427 | + if (callme (0, 0, 0, 0x1234, 0x1234567890abcdefLL)) | |
428 | + abort (); | |
429 | + return 0; | |
38a49943 | 430 | +} |
bed1487f PS |
431 | Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2a.c |
432 | =================================================================== | |
433 | --- gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2a.c (.../tags/gcc_4_4_0_release) (revision 0) | |
434 | +++ gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2a.c (.../branches/ix86/gcc-4_4-branch) (revision 146537) | |
435 | @@ -0,0 +1,27 @@ | |
436 | +/* Test for cross x86_64<->w64 abi standard calls. */ | |
437 | +/* { dg-do run { target i?86-*-linux* x86_64-*-linux* } } */ | |
438 | +/* { dg-options "-O2 -mabi=ms -std=gnu99 -ffast-math -fno-builtin" } */ | |
439 | +/* { dg-additional-sources "func-2b.c" } */ | |
440 | + | |
441 | +extern void __attribute__ ((sysv_abi)) abort (void); | |
442 | +long double func_cross (long double, double, float, long, int, char); | |
443 | + | |
444 | +long double __attribute__ ((sysv_abi)) | |
445 | +func_native (long double a, double b, float c, long d, int e, char f) | |
38a49943 | 446 | +{ |
bed1487f PS |
447 | + long double ret; |
448 | + ret = a + (long double) b + (long double) c; | |
449 | + ret *= (long double) (d + (long) e); | |
450 | + if (f>0) | |
451 | + ret += func_native (a,b,c,d,e,-f); | |
452 | + return ret; | |
453 | +} | |
38a49943 | 454 | + |
bed1487f PS |
455 | +int __attribute__ ((sysv_abi)) |
456 | +main () | |
457 | +{ | |
458 | + if (func_cross (1.0,2.0,3.0,1,2,3) | |
459 | + != func_native (1.0,2.0,3.0,1,2,3)) | |
460 | + abort (); | |
461 | + return 0; | |
38a49943 | 462 | +} |
bed1487f | 463 | Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2b.c |
38a49943 | 464 | =================================================================== |
bed1487f PS |
465 | --- gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2b.c (.../tags/gcc_4_4_0_release) (revision 0) |
466 | +++ gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2b.c (.../branches/ix86/gcc-4_4-branch) (revision 146537) | |
467 | @@ -0,0 +1,24 @@ | |
468 | +/* Test for cross x86_64<->w64 abi standard calls via variable. */ | |
469 | +/* { dg-options "-O2 -mabi=ms -std=gnu99 -ffast-math -fno-builtin" } */ | |
38a49943 | 470 | + |
bed1487f | 471 | +typedef int (*func)(void *, char *, char *, short, long long); |
38a49943 | 472 | + |
bed1487f PS |
473 | +static int |
474 | +callback (void *ptr, char *string1, char *string2, short number, | |
475 | + long long rand) | |
38a49943 | 476 | +{ |
bed1487f PS |
477 | + if (ptr != 0 |
478 | + || string1 != 0 | |
479 | + || string2 != 0 | |
480 | + || number != 0x1234 | |
481 | + || rand != 0x1234567890abcdefLL) | |
482 | + return 1; | |
483 | + else | |
484 | + return 0; | |
38a49943 PS |
485 | +} |
486 | + | |
bed1487f PS |
487 | +func |
488 | +get_callback (void) | |
38a49943 | 489 | +{ |
bed1487f | 490 | + return callback; |
38a49943 | 491 | +} |
bed1487f | 492 | Index: gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2b.c |
38a49943 | 493 | =================================================================== |
bed1487f PS |
494 | --- gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2b.c (.../tags/gcc_4_4_0_release) (revision 0) |
495 | +++ gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2b.c (.../branches/ix86/gcc-4_4-branch) (revision 146537) | |
496 | @@ -0,0 +1,13 @@ | |
497 | +/* Test for cross x86_64<->w64 abi standard calls. */ | |
498 | +/* { dg-options "-mabi=ms -std=gnu99 -ffast-math -fno-builtin" } */ | |
499 | + | |
500 | +long double func_cross (long double a, double b, float c, long d, int e, | |
501 | + char f) | |
38a49943 | 502 | +{ |
bed1487f PS |
503 | + long double ret; |
504 | + ret = a + (long double) b + (long double) c; | |
505 | + ret *= (long double) (d + (long) e); | |
506 | + if (f>0) | |
507 | + ret += func_cross (a,b,c,d,e,-f); | |
508 | + return ret; | |
38a49943 | 509 | +} |
bed1487f PS |
510 | |
511 | Property changes on: gcc/testsuite/gcc.target/x86_64/abi/callabi | |
512 | ___________________________________________________________________ | |
513 | Deleted: svn:mergeinfo | |
514 | ||
515 | Index: gcc/testsuite/ChangeLog.ix86 | |
516 | =================================================================== | |
517 | --- gcc/testsuite/ChangeLog.ix86 (.../tags/gcc_4_4_0_release) (revision 0) | |
518 | +++ gcc/testsuite/ChangeLog.ix86 (.../branches/ix86/gcc-4_4-branch) (revision 146537) | |
519 | @@ -0,0 +1,14 @@ | |
520 | +2009-03-27 H.J. Lu <hongjiu.lu@intel.com> | |
38a49943 | 521 | + |
bed1487f PS |
522 | + Backport from mainline: |
523 | + 2009-03-27 H.J. Lu <hongjiu.lu@intel.com> | |
524 | + | |
525 | + PR target/39472 | |
526 | + * gcc.target/x86_64/abi/callabi/func-2a.c: New. | |
527 | + * gcc.target/x86_64/abi/callabi/func-2b.c: Likewise. | |
528 | + * gcc.target/x86_64/abi/callabi/func-indirect-2a.c: Likewise. | |
529 | + * gcc.target/x86_64/abi/callabi/func-indirect-2b.c: Likewise. | |
530 | + * gcc.target/x86_64/abi/callabi/vaarg-4a.c: Likewise. | |
531 | + * gcc.target/x86_64/abi/callabi/vaarg-4b.c: Likewise. | |
532 | + * gcc.target/x86_64/abi/callabi/vaarg-5a.c: Likewise. | |
533 | + * gcc.target/x86_64/abi/callabi/vaarg-5b.c: Likewise. | |
534 | ||
535 | Property changes on: gcc/testsuite/gcc.dg/torture/pr36227.c | |
536 | ___________________________________________________________________ | |
537 | Deleted: svn:mergeinfo | |
538 | ||
539 | ||
540 | Property changes on: gcc/testsuite/g++.dg/cpp0x/decltype-38655.C | |
541 | ___________________________________________________________________ | |
542 | Deleted: svn:mergeinfo | |
543 | ||
544 | ||
545 | Property changes on: gcc/testsuite/ChangeLog-2008 | |
546 | ___________________________________________________________________ | |
547 | Deleted: svn:mergeinfo | |
548 | ||
549 | ||
550 | Property changes on: gcc/cp/ChangeLog-2007 | |
551 | ___________________________________________________________________ | |
552 | Deleted: svn:mergeinfo | |
553 | ||
554 | ||
555 | Property changes on: gcc/cp/ChangeLog-2008 | |
556 | ___________________________________________________________________ | |
557 | Deleted: svn:mergeinfo | |
558 | ||
559 | Index: gcc/rtl.def | |
38a49943 | 560 | =================================================================== |
bed1487f PS |
561 | --- gcc/rtl.def (.../tags/gcc_4_4_0_release) (revision 146537) |
562 | +++ gcc/rtl.def (.../branches/ix86/gcc-4_4-branch) (revision 146537) | |
563 | @@ -1088,7 +1088,11 @@ | |
564 | guard for the bypass. The function will get the two insns as | |
565 | parameters. If the function returns zero the bypass will be | |
566 | ignored for this case. Additional guard is necessary to recognize | |
567 | - complicated bypasses, e.g. when consumer is load address. */ | |
568 | + complicated bypasses, e.g. when consumer is load address. If there | |
569 | + are more one bypass with the same output and input insns, the | |
570 | + chosen bypass is the first bypass with a guard in description whose | |
571 | + guard function returns nonzero. If there is no such bypass, then | |
572 | + bypass without the guard function is chosen. */ | |
573 | DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA) | |
574 | ||
575 | /* (define_automaton string) describes names of automata generated and | |
576 | ||
577 | Property changes on: gcc/ChangeLog-2008 | |
578 | ___________________________________________________________________ | |
579 | Deleted: svn:mergeinfo | |
580 | ||
581 | Index: gcc/ChangeLog.ix86 | |
38a49943 | 582 | =================================================================== |
bed1487f PS |
583 | --- gcc/ChangeLog.ix86 (.../tags/gcc_4_4_0_release) (revision 0) |
584 | +++ gcc/ChangeLog.ix86 (.../branches/ix86/gcc-4_4-branch) (revision 146537) | |
585 | @@ -0,0 +1,171 @@ | |
586 | +2009-04-20 H.J. Lu <hongjiu.lu@intel.com> | |
38a49943 | 587 | + |
bed1487f PS |
588 | + Backport from mainline: |
589 | + 2009-04-20 Joey Ye <joey.ye@intel.com> | |
590 | + Xuepeng Guo <xuepeng.guo@intel.com> | |
591 | + H.J. Lu <hongjiu.lu@intel.com> | |
38a49943 | 592 | + |
bed1487f | 593 | + * config/i386/atom.md: Add bypasses with ix86_dep_by_shift_count. |
38a49943 | 594 | + |
bed1487f PS |
595 | + * config/i386/i386.c (LEA_SEARCH_THRESHOLD): New macro. |
596 | + (IX86_LEA_PRIORITY): Likewise. | |
597 | + (distance_non_agu_define): New function. | |
598 | + (distance_agu_use): Likewise. | |
599 | + (ix86_lea_for_add_ok): Likewise. | |
600 | + (ix86_dep_by_shift_count): Likewise. | |
38a49943 | 601 | + |
bed1487f PS |
602 | + * config/i386/i386.md: Call ix86_lea_for_add_ok to decide we |
603 | + should split for LEA. | |
38a49943 | 604 | + |
bed1487f PS |
605 | + * config/i386/i386-protos.h (ix86_lea_for_add_ok): Declare new |
606 | + function. | |
607 | + (ix86_dep_by_shift_count): Likewise. | |
38a49943 | 608 | + |
bed1487f | 609 | +2009-04-07 H.J. Lu <hongjiu.lu@intel.com> |
38a49943 | 610 | + |
bed1487f PS |
611 | + Backport from mainline: |
612 | + 2009-04-07 H.J. Lu <hongjiu.lu@intel.com> | |
38a49943 | 613 | + |
bed1487f | 614 | + * doc/invoke.texi: Document Atom support. |
38a49943 | 615 | + |
bed1487f | 616 | +2009-04-06 H.J. Lu <hongjiu.lu@intel.com> |
38a49943 | 617 | + |
bed1487f | 618 | + * config/i386/i386.md: Revert 2 accidental checkins. |
38a49943 | 619 | + |
bed1487f | 620 | +2009-04-06 H.J. Lu <hongjiu.lu@intel.com> |
38a49943 PS |
621 | + |
622 | + Backport from mainline: | |
bed1487f PS |
623 | + 2009-04-06 Joey Ye <joey.ye@intel.com> |
624 | + Xuepeng Guo <xuepeng.guo@intel.com> | |
625 | + H.J. Lu <hongjiu.lu@intel.com> | |
626 | + | |
627 | + Atom pipeline model, tuning and insn selection. | |
628 | + * config.gcc (atom): Add atom config options and target. | |
629 | + | |
630 | + * config/i386/atom.md: New. | |
631 | + | |
632 | + * config/i386/i386.c (atom_cost): New cost. | |
633 | + (m_ATOM): New macro flag. | |
634 | + (initial_ix86_tune_features): Set m_ATOM. | |
635 | + (x86_accumulate_outgoing_args): Likewise. | |
636 | + (x86_arch_always_fancy_math_387): Likewise. | |
637 | + (processor_target): Add Atom cost. | |
638 | + (cpu_names): Add Atom cpu name. | |
639 | + (override_options): Set Atom ISA. | |
640 | + (ix86_issue_rate): New case PROCESSOR_ATOM. | |
641 | + (ix86_adjust_cost): Likewise. | |
642 | + | |
643 | + * config/i386/i386.h (TARGET_ATOM): New target macro. | |
644 | + (ix86_tune_indices): Add X86_TUNE_OPT_AGU. | |
645 | + (TARGET_OPT_AGU): New target option. | |
646 | + (target_cpu_default): Add TARGET_CPU_DEFAULT_atom. | |
647 | + (processor_type): Add PROCESSOR_ATOM. | |
648 | + | |
649 | + * config/i386/i386.md (cpu): Add new value "atom". | |
650 | + (use_carry, movu): New attr. | |
651 | + (atom.md): Include atom.md. | |
652 | + (adddi3_carry_rex64): Set attr "use_carry". | |
653 | + (addqi3_carry): Likewise. | |
654 | + (addhi3_carry): Likewise. | |
655 | + (addsi3_carry): Likewise. | |
656 | + (*addsi3_carry_zext): Likewise. | |
657 | + (subdi3_carry_rex64): Likewise. | |
658 | + (subqi3_carry): Likewise. | |
659 | + (subhi3_carry): Likewise. | |
660 | + (subsi3_carry): Likewise. | |
661 | + (x86_movdicc_0_m1_rex64): Likewise. | |
662 | + (*x86_movdicc_0_m1_se): Likewise. | |
663 | + (x86_movsicc_0_m1): Likewise. | |
664 | + (*x86_movsicc_0_m1_se): Likewise. | |
665 | + (*adddi_1_rex64): Emit add insn as much as possible. | |
666 | + (*addsi_1): Likewise. | |
667 | + (return_internal): Set atom_unit. | |
668 | + (return_internal_long): Likewise. | |
669 | + (return_pop_internal): Likewise. | |
670 | + (*rcpsf2_sse): Set atom_sse_attr attr. | |
671 | + (*qrt<mode>2_sse): Likewise. | |
672 | + | |
673 | +2009-04-02 H.J. Lu <hongjiu.lu@intel.com> | |
38a49943 PS |
674 | + |
675 | + Backport from mainline: | |
bed1487f | 676 | + 2009-04-02 H.J. Lu <hongjiu.lu@intel.com> |
38a49943 | 677 | + |
bed1487f PS |
678 | + * config/i386/i386.c (ix86_abi): Move initialization to ... |
679 | + (override_options): Here. | |
38a49943 | 680 | + |
bed1487f | 681 | +2009-03-29 H.J. Lu <hongjiu.lu@intel.com> |
38a49943 | 682 | + |
bed1487f PS |
683 | + Backport from mainline: |
684 | + 2009-03-29 H.J. Lu <hongjiu.lu@intel.com> | |
38a49943 | 685 | + |
bed1487f | 686 | + * config/i386/i386-protos.h (ix86_agi_dependent): New. |
38a49943 | 687 | + |
bed1487f PS |
688 | + * config/i386/i386.c (ix86_agi_dependent): Rewrite. |
689 | + (ix86_adjust_cost): Updated. | |
38a49943 | 690 | + |
bed1487f | 691 | +2009-03-27 H.J. Lu <hongjiu.lu@intel.com> |
38a49943 | 692 | + |
bed1487f PS |
693 | + Backport from mainline: |
694 | + 2009-03-27 H.J. Lu <hongjiu.lu@intel.com> | |
695 | + | |
696 | + PR target/39472 | |
697 | + * config/i386/i386.c (ix86_abi): New. | |
698 | + (override_options): Handle -mabi=. | |
699 | + (ix86_function_arg_regno_p): Replace DEFAULT_ABI with | |
700 | + ix86_abi. | |
701 | + (ix86_call_abi_override): Likewise. | |
702 | + (init_cumulative_args): Likewise. | |
703 | + (function_arg_advance): Likewise. | |
704 | + (function_arg_64): Likewise. | |
705 | + (function_arg): Likewise. | |
706 | + (ix86_pass_by_reference): Likewise. | |
707 | + (ix86_function_value_regno_p): Likewise. | |
708 | + (ix86_build_builtin_va_list_abi): Likewise. | |
709 | + (setup_incoming_varargs_64): Likewise. | |
710 | + (is_va_list_char_pointer): Likewise. | |
711 | + (ix86_init_machine_status): Likewise. | |
712 | + (ix86_reg_parm_stack_space): Use enum calling_abi on | |
713 | + call_abi. | |
714 | + (ix86_function_type_abi): Return enum calling_abi. Rewrite | |
715 | + for 64bit. Replace DEFAULT_ABI with ix86_abi. | |
716 | + (ix86_function_abi): Make it static and return enum | |
717 | + calling_abi. | |
718 | + (ix86_cfun_abi): Return enum calling_abi. Replace DEFAULT_ABI | |
719 | + with ix86_abi. | |
720 | + (ix86_fn_abi_va_list): Updated. | |
721 | + | |
722 | + * config/i386/i386.h (ix86_abi): New. | |
723 | + (STACK_BOUNDARY): Replace DEFAULT_ABI with ix86_abi. | |
724 | + (CONDITIONAL_REGISTER_USAGE): Likewise. | |
725 | + (CUMULATIVE_ARGS): Change call_abi type to enum calling_abi. | |
726 | + (machine_function): Likewise. | |
727 | + | |
728 | + * config/i386/i386.md (untyped_call): Replace DEFAULT_ABI | |
729 | + with ix86_abi. | |
730 | + * config/i386/cygming.h (TARGET_64BIT_MS_ABI): Likewise. | |
731 | + (STACK_BOUNDARY): Likewise. | |
732 | + * config/i386/mingw32.h (EXTRA_OS_CPP_BUILTINS): Likewise. | |
733 | + | |
734 | + * config/i386/i386.opt (mabi=): New. | |
735 | + | |
736 | + * config/i386/i386-protos.h (ix86_cfun_abi): Changed to | |
737 | + return enum calling_abi. | |
738 | + (ix86_function_type_abi): Likewise. | |
739 | + (ix86_function_abi): Removed. | |
740 | + | |
741 | +2009-03-27 H.J. Lu <hongjiu.lu@intel.com> | |
38a49943 | 742 | + |
bed1487f PS |
743 | + Backport from mainline: |
744 | + 2009-03-27 Vladimir Makarov <vmakarov@redhat.com> | |
745 | + | |
746 | + * genautomata.c: Add a new year to the copyright. Add a new | |
747 | + reference. | |
748 | + (struct insn_reserv_decl): Add comments for member bypass_list. | |
749 | + (find_bypass): Remove. | |
750 | + (insert_bypass): New. | |
751 | + (process_decls): Use insert_bypass. | |
752 | + (output_internal_insn_latency_func): Output all bypasses with the | |
753 | + same input insn in one switch case. | |
754 | + | |
755 | + * rtl.def (define_bypass): Describe bypass choice. | |
756 | + * doc/md.texi (define_bypass): Ditto. | |
757 | Index: gcc/config.gcc | |
38a49943 | 758 | =================================================================== |
bed1487f PS |
759 | --- gcc/config.gcc (.../tags/gcc_4_4_0_release) (revision 146537) |
760 | +++ gcc/config.gcc (.../branches/ix86/gcc-4_4-branch) (revision 146537) | |
761 | @@ -1088,7 +1088,7 @@ | |
762 | tmake_file="${tmake_file} i386/t-linux64" | |
763 | need_64bit_hwint=yes | |
764 | case X"${with_cpu}" in | |
765 | - Xgeneric|Xcore2|Xnocona|Xx86-64|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx) | |
766 | + Xgeneric|Xatom|Xcore2|Xnocona|Xx86-64|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx) | |
767 | ;; | |
768 | X) | |
769 | if test x$with_cpu_64 = x; then | |
770 | @@ -1097,7 +1097,7 @@ | |
771 | ;; | |
772 | *) | |
773 | echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2 | |
774 | - echo "generic core2 nocona x86-64 amdfam10 barcelona k8 opteron athlon64 athlon-fx" 1>&2 | |
775 | + echo "generic atom core2 nocona x86-64 amdfam10 barcelona k8 opteron athlon64 athlon-fx" 1>&2 | |
776 | exit 1 | |
777 | ;; | |
778 | esac | |
779 | @@ -1202,7 +1202,7 @@ | |
780 | # libgcc/configure.ac instead. | |
781 | need_64bit_hwint=yes | |
782 | case X"${with_cpu}" in | |
783 | - Xgeneric|Xcore2|Xnocona|Xx86-64|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx) | |
784 | + Xgeneric|Xatom|Xcore2|Xnocona|Xx86-64|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx) | |
785 | ;; | |
786 | X) | |
787 | if test x$with_cpu_64 = x; then | |
788 | @@ -1211,7 +1211,7 @@ | |
789 | ;; | |
790 | *) | |
791 | echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2 | |
792 | - echo "generic core2 nocona x86-64 amdfam10 barcelona k8 opteron athlon64 athlon-fx" 1>&2 | |
793 | + echo "generic atom core2 nocona x86-64 amdfam10 barcelona k8 opteron athlon64 athlon-fx" 1>&2 | |
794 | exit 1 | |
795 | ;; | |
796 | esac | |
797 | @@ -2805,7 +2805,7 @@ | |
798 | esac | |
799 | # OK | |
800 | ;; | |
801 | - "" | amdfam10 | barcelona | k8 | opteron | athlon64 | athlon-fx | nocona | core2 | generic) | |
802 | + "" | amdfam10 | barcelona | k8 | opteron | athlon64 | athlon-fx | nocona | core2 | atom | generic) | |
803 | # OK | |
804 | ;; | |
805 | *) | |
806 | Index: gcc/config/i386/i386.h | |
38a49943 | 807 | =================================================================== |
bed1487f PS |
808 | --- gcc/config/i386/i386.h (.../tags/gcc_4_4_0_release) (revision 146537) |
809 | +++ gcc/config/i386/i386.h (.../branches/ix86/gcc-4_4-branch) (revision 146537) | |
810 | @@ -236,6 +236,7 @@ | |
811 | #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64) | |
812 | #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64) | |
813 | #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) | |
814 | +#define TARGET_ATOM (ix86_tune == PROCESSOR_ATOM) | |
38a49943 | 815 | |
bed1487f PS |
816 | /* Feature tests against the various tunings. */ |
817 | enum ix86_tune_indices { | |
818 | @@ -300,6 +301,7 @@ | |
819 | X86_TUNE_USE_VECTOR_FP_CONVERTS, | |
820 | X86_TUNE_USE_VECTOR_CONVERTS, | |
821 | X86_TUNE_FUSE_CMP_AND_BRANCH, | |
822 | + X86_TUNE_OPT_AGU, | |
823 | ||
824 | X86_TUNE_LAST | |
38a49943 | 825 | }; |
bed1487f PS |
826 | @@ -387,6 +389,7 @@ |
827 | ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS] | |
828 | #define TARGET_FUSE_CMP_AND_BRANCH \ | |
829 | ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH] | |
830 | +#define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU] | |
38a49943 | 831 | |
bed1487f PS |
832 | /* Feature tests against the various architecture variations. */ |
833 | enum ix86_arch_indices { | |
834 | @@ -470,7 +473,10 @@ | |
835 | MS_ABI = 1 | |
836 | }; | |
38a49943 | 837 | |
bed1487f PS |
838 | -/* The default abi form used by target. */ |
839 | +/* The abi used by target. */ | |
840 | +extern enum calling_abi ix86_abi; | |
38a49943 | 841 | + |
bed1487f PS |
842 | +/* The default abi used by target. */ |
843 | #define DEFAULT_ABI SYSV_ABI | |
844 | ||
845 | /* Subtargets may reset this to 1 in order to enable 96-bit long double | |
846 | @@ -569,6 +575,7 @@ | |
847 | TARGET_CPU_DEFAULT_prescott, | |
848 | TARGET_CPU_DEFAULT_nocona, | |
849 | TARGET_CPU_DEFAULT_core2, | |
850 | + TARGET_CPU_DEFAULT_atom, | |
851 | ||
852 | TARGET_CPU_DEFAULT_geode, | |
853 | TARGET_CPU_DEFAULT_k6, | |
854 | @@ -658,7 +665,7 @@ | |
855 | ||
856 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
857 | #define STACK_BOUNDARY \ | |
858 | - (TARGET_64BIT && DEFAULT_ABI == MS_ABI ? 128 : BITS_PER_WORD) | |
859 | + (TARGET_64BIT && ix86_abi == MS_ABI ? 128 : BITS_PER_WORD) | |
860 | ||
861 | /* Stack boundary of the main function guaranteed by OS. */ | |
862 | #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) | |
863 | @@ -954,7 +961,7 @@ | |
864 | fixed_regs[j] = call_used_regs[j] = 1; \ | |
865 | if (TARGET_64BIT \ | |
866 | && ((cfun && cfun->machine->call_abi == MS_ABI) \ | |
867 | - || (!cfun && DEFAULT_ABI == MS_ABI))) \ | |
868 | + || (!cfun && ix86_abi == MS_ABI))) \ | |
869 | { \ | |
870 | call_used_regs[SI_REG] = 0; \ | |
871 | call_used_regs[DI_REG] = 0; \ | |
872 | @@ -1614,7 +1621,7 @@ | |
873 | int maybe_vaarg; /* true for calls to possibly vardic fncts. */ | |
874 | int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should | |
875 | be passed in SSE registers. Otherwise 0. */ | |
876 | - int call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise | |
877 | + enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise | |
878 | MS_ABI for ms abi. */ | |
879 | } CUMULATIVE_ARGS; | |
880 | ||
881 | @@ -2260,6 +2267,7 @@ | |
882 | PROCESSOR_GENERIC32, | |
883 | PROCESSOR_GENERIC64, | |
884 | PROCESSOR_AMDFAM10, | |
885 | + PROCESSOR_ATOM, | |
886 | PROCESSOR_max | |
887 | }; | |
888 | ||
889 | @@ -2433,7 +2441,7 @@ | |
890 | int tls_descriptor_call_expanded_p; | |
891 | /* This value is used for amd64 targets and specifies the current abi | |
892 | to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */ | |
893 | - int call_abi; | |
894 | + enum calling_abi call_abi; | |
38a49943 PS |
895 | }; |
896 | ||
bed1487f PS |
897 | #define ix86_stack_locals (cfun->machine->stack_locals) |
898 | Index: gcc/config/i386/cygming.h | |
899 | =================================================================== | |
900 | --- gcc/config/i386/cygming.h (.../tags/gcc_4_4_0_release) (revision 146537) | |
901 | +++ gcc/config/i386/cygming.h (.../branches/ix86/gcc-4_4-branch) (revision 146537) | |
902 | @@ -34,7 +34,7 @@ | |
903 | #endif | |
904 | ||
905 | #undef TARGET_64BIT_MS_ABI | |
906 | -#define TARGET_64BIT_MS_ABI (!cfun ? DEFAULT_ABI == MS_ABI : TARGET_64BIT && cfun->machine->call_abi == MS_ABI) | |
907 | +#define TARGET_64BIT_MS_ABI (!cfun ? ix86_abi == MS_ABI : TARGET_64BIT && cfun->machine->call_abi == MS_ABI) | |
908 | ||
909 | #undef DEFAULT_ABI | |
910 | #define DEFAULT_ABI (TARGET_64BIT ? MS_ABI : SYSV_ABI) | |
911 | @@ -202,7 +202,7 @@ | |
912 | #define CHECK_STACK_LIMIT 4000 | |
913 | ||
914 | #undef STACK_BOUNDARY | |
915 | -#define STACK_BOUNDARY (DEFAULT_ABI == MS_ABI ? 128 : BITS_PER_WORD) | |
916 | +#define STACK_BOUNDARY (ix86_abi == MS_ABI ? 128 : BITS_PER_WORD) | |
917 | ||
918 | /* By default, target has a 80387, uses IEEE compatible arithmetic, | |
919 | returns float values in the 387 and needs stack probes. | |
920 | Index: gcc/config/i386/i386.md | |
921 | =================================================================== | |
922 | --- gcc/config/i386/i386.md (.../tags/gcc_4_4_0_release) (revision 146537) | |
923 | +++ gcc/config/i386/i386.md (.../branches/ix86/gcc-4_4-branch) (revision 146537) | |
924 | @@ -316,7 +316,7 @@ | |
925 | ||
926 | \f | |
927 | ;; Processor type. | |
928 | -(define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2, | |
929 | +(define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,atom, | |
930 | generic64,amdfam10" | |
931 | (const (symbol_ref "ix86_schedule"))) | |
932 | ||
933 | @@ -612,6 +612,12 @@ | |
934 | (define_attr "i387_cw" "trunc,floor,ceil,mask_pm,uninitialized,any" | |
935 | (const_string "any")) | |
936 | ||
937 | +;; Define attribute to classify add/sub insns that consumes carry flag (CF) | |
938 | +(define_attr "use_carry" "0,1" (const_string "0")) | |
939 | + | |
940 | +;; Define attribute to indicate unaligned ssemov insns | |
941 | +(define_attr "movu" "0,1" (const_string "0")) | |
942 | + | |
943 | ;; Describe a user's asm statement. | |
944 | (define_asm_attributes | |
945 | [(set_attr "length" "128") | |
946 | @@ -727,6 +733,7 @@ | |
947 | (include "k6.md") | |
948 | (include "athlon.md") | |
949 | (include "geode.md") | |
950 | +(include "atom.md") | |
951 | ||
952 | \f | |
953 | ;; Operand and operator predicates and constraints | |
954 | @@ -5790,6 +5797,7 @@ | |
955 | "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)" | |
956 | "adc{q}\t{%2, %0|%0, %2}" | |
957 | [(set_attr "type" "alu") | |
958 | + (set_attr "use_carry" "1") | |
959 | (set_attr "pent_pair" "pu") | |
960 | (set_attr "mode" "DI")]) | |
961 | ||
962 | @@ -5864,6 +5872,7 @@ | |
963 | "ix86_binary_operator_ok (PLUS, QImode, operands)" | |
964 | "adc{b}\t{%2, %0|%0, %2}" | |
965 | [(set_attr "type" "alu") | |
966 | + (set_attr "use_carry" "1") | |
967 | (set_attr "pent_pair" "pu") | |
968 | (set_attr "mode" "QI")]) | |
969 | ||
970 | @@ -5876,6 +5885,7 @@ | |
971 | "ix86_binary_operator_ok (PLUS, HImode, operands)" | |
972 | "adc{w}\t{%2, %0|%0, %2}" | |
973 | [(set_attr "type" "alu") | |
974 | + (set_attr "use_carry" "1") | |
975 | (set_attr "pent_pair" "pu") | |
976 | (set_attr "mode" "HI")]) | |
977 | ||
978 | @@ -5888,6 +5898,7 @@ | |
979 | "ix86_binary_operator_ok (PLUS, SImode, operands)" | |
980 | "adc{l}\t{%2, %0|%0, %2}" | |
981 | [(set_attr "type" "alu") | |
982 | + (set_attr "use_carry" "1") | |
983 | (set_attr "pent_pair" "pu") | |
984 | (set_attr "mode" "SI")]) | |
985 | ||
986 | @@ -5901,6 +5912,7 @@ | |
987 | "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)" | |
988 | "adc{l}\t{%2, %k0|%k0, %2}" | |
989 | [(set_attr "type" "alu") | |
990 | + (set_attr "use_carry" "1") | |
991 | (set_attr "pent_pair" "pu") | |
992 | (set_attr "mode" "SI")]) | |
993 | ||
994 | @@ -6130,9 +6142,9 @@ | |
995 | (set_attr "mode" "SI")]) | |
996 | ||
997 | (define_insn "*adddi_1_rex64" | |
998 | - [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r") | |
999 | - (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r") | |
1000 | - (match_operand:DI 2 "x86_64_general_operand" "rme,re,le"))) | |
1001 | + [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r") | |
1002 | + (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r,r") | |
1003 | + (match_operand:DI 2 "x86_64_general_operand" "rme,re,0,le"))) | |
1004 | (clobber (reg:CC FLAGS_REG))] | |
1005 | "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)" | |
1006 | { | |
1007 | @@ -6153,6 +6165,10 @@ | |
1008 | } | |
1009 | ||
1010 | default: | |
1011 | + /* Use add as much as possible to replace lea for AGU optimization. */ | |
1012 | + if (which_alternative == 2 && TARGET_OPT_AGU) | |
1013 | + return "add{q}\t{%1, %0|%0, %1}"; | |
1014 | + | |
1015 | gcc_assert (rtx_equal_p (operands[0], operands[1])); | |
1016 | ||
1017 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
1018 | @@ -6171,8 +6187,11 @@ | |
1019 | } | |
1020 | } | |
1021 | [(set (attr "type") | |
1022 | - (cond [(eq_attr "alternative" "2") | |
1023 | + (cond [(and (eq_attr "alternative" "2") | |
1024 | + (eq (symbol_ref "TARGET_OPT_AGU") (const_int 0))) | |
1025 | (const_string "lea") | |
1026 | + (eq_attr "alternative" "3") | |
1027 | + (const_string "lea") | |
1028 | ; Current assemblers are broken and do not allow @GOTOFF in | |
1029 | ; ought but a memory context. | |
1030 | (match_operand:DI 2 "pic_symbolic_operand" "") | |
1031 | @@ -6189,8 +6208,8 @@ | |
1032 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
1033 | (match_operand:DI 2 "x86_64_nonmemory_operand" ""))) | |
1034 | (clobber (reg:CC FLAGS_REG))] | |
1035 | - "TARGET_64BIT && reload_completed | |
1036 | - && true_regnum (operands[0]) != true_regnum (operands[1])" | |
1037 | + "TARGET_64BIT && reload_completed | |
1038 | + && ix86_lea_for_add_ok (PLUS, insn, operands)" | |
1039 | [(set (match_dup 0) | |
1040 | (plus:DI (match_dup 1) | |
1041 | (match_dup 2)))] | |
1042 | @@ -6394,9 +6413,9 @@ | |
1043 | ||
1044 | ||
1045 | (define_insn "*addsi_1" | |
1046 | - [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r") | |
1047 | - (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r") | |
1048 | - (match_operand:SI 2 "general_operand" "g,ri,li"))) | |
1049 | + [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r,r") | |
1050 | + (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r,r") | |
1051 | + (match_operand:SI 2 "general_operand" "g,ri,0,li"))) | |
1052 | (clobber (reg:CC FLAGS_REG))] | |
1053 | "ix86_binary_operator_ok (PLUS, SImode, operands)" | |
1054 | { | |
1055 | @@ -6417,6 +6436,10 @@ | |
1056 | } | |
1057 | ||
1058 | default: | |
1059 | + /* Use add as much as possible to replace lea for AGU optimization. */ | |
1060 | + if (which_alternative == 2 && TARGET_OPT_AGU) | |
1061 | + return "add{l}\t{%1, %0|%0, %1}"; | |
38a49943 | 1062 | + |
bed1487f PS |
1063 | gcc_assert (rtx_equal_p (operands[0], operands[1])); |
1064 | ||
1065 | /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'. | |
1066 | @@ -6433,7 +6456,10 @@ | |
1067 | } | |
1068 | } | |
1069 | [(set (attr "type") | |
1070 | - (cond [(eq_attr "alternative" "2") | |
1071 | + (cond [(and (eq_attr "alternative" "2") | |
1072 | + (eq (symbol_ref "TARGET_OPT_AGU") (const_int 0))) | |
1073 | + (const_string "lea") | |
1074 | + (eq_attr "alternative" "3") | |
1075 | (const_string "lea") | |
1076 | ; Current assemblers are broken and do not allow @GOTOFF in | |
1077 | ; ought but a memory context. | |
1078 | @@ -6451,8 +6477,7 @@ | |
1079 | (plus (match_operand 1 "register_operand" "") | |
1080 | (match_operand 2 "nonmemory_operand" ""))) | |
1081 | (clobber (reg:CC FLAGS_REG))] | |
1082 | - "reload_completed | |
1083 | - && true_regnum (operands[0]) != true_regnum (operands[1])" | |
1084 | + "reload_completed && ix86_lea_for_add_ok (PLUS, insn, operands)" | |
1085 | [(const_int 0)] | |
1086 | { | |
1087 | rtx pat; | |
1088 | @@ -7553,6 +7578,7 @@ | |
1089 | "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)" | |
1090 | "sbb{q}\t{%2, %0|%0, %2}" | |
1091 | [(set_attr "type" "alu") | |
1092 | + (set_attr "use_carry" "1") | |
1093 | (set_attr "pent_pair" "pu") | |
1094 | (set_attr "mode" "DI")]) | |
1095 | ||
1096 | @@ -7601,6 +7627,7 @@ | |
1097 | "ix86_binary_operator_ok (MINUS, QImode, operands)" | |
1098 | "sbb{b}\t{%2, %0|%0, %2}" | |
1099 | [(set_attr "type" "alu") | |
1100 | + (set_attr "use_carry" "1") | |
1101 | (set_attr "pent_pair" "pu") | |
1102 | (set_attr "mode" "QI")]) | |
1103 | ||
1104 | @@ -7613,6 +7640,7 @@ | |
1105 | "ix86_binary_operator_ok (MINUS, HImode, operands)" | |
1106 | "sbb{w}\t{%2, %0|%0, %2}" | |
1107 | [(set_attr "type" "alu") | |
1108 | + (set_attr "use_carry" "1") | |
1109 | (set_attr "pent_pair" "pu") | |
1110 | (set_attr "mode" "HI")]) | |
1111 | ||
1112 | @@ -7625,6 +7653,7 @@ | |
1113 | "ix86_binary_operator_ok (MINUS, SImode, operands)" | |
1114 | "sbb{l}\t{%2, %0|%0, %2}" | |
1115 | [(set_attr "type" "alu") | |
1116 | + (set_attr "use_carry" "1") | |
1117 | (set_attr "pent_pair" "pu") | |
1118 | (set_attr "mode" "SI")]) | |
1119 | ||
1120 | @@ -15164,7 +15193,7 @@ | |
1121 | ? gen_rtx_REG (XCmode, FIRST_FLOAT_REG) : NULL), | |
1122 | operands[0], const0_rtx, | |
1123 | GEN_INT ((TARGET_64BIT | |
1124 | - ? (DEFAULT_ABI == SYSV_ABI | |
1125 | + ? (ix86_abi == SYSV_ABI | |
1126 | ? X86_64_SSE_REGPARM_MAX | |
1127 | : X64_SSE_REGPARM_MAX) | |
1128 | : X86_32_SSE_REGPARM_MAX) | |
1129 | @@ -15244,6 +15273,7 @@ | |
1130 | "reload_completed" | |
1131 | "ret" | |
1132 | [(set_attr "length" "1") | |
1133 | + (set_attr "atom_unit" "jeu") | |
1134 | (set_attr "length_immediate" "0") | |
1135 | (set_attr "modrm" "0")]) | |
1136 | ||
1137 | @@ -15256,6 +15286,7 @@ | |
1138 | "reload_completed" | |
1139 | "rep\;ret" | |
1140 | [(set_attr "length" "1") | |
1141 | + (set_attr "atom_unit" "jeu") | |
1142 | (set_attr "length_immediate" "0") | |
1143 | (set_attr "prefix_rep" "1") | |
1144 | (set_attr "modrm" "0")]) | |
1145 | @@ -15266,6 +15297,7 @@ | |
1146 | "reload_completed" | |
1147 | "ret\t%0" | |
1148 | [(set_attr "length" "3") | |
1149 | + (set_attr "atom_unit" "jeu") | |
1150 | (set_attr "length_immediate" "2") | |
1151 | (set_attr "modrm" "0")]) | |
1152 | ||
1153 | @@ -16387,6 +16419,7 @@ | |
1154 | "TARGET_SSE_MATH" | |
1155 | "%vrcpss\t{%1, %d0|%d0, %1}" | |
1156 | [(set_attr "type" "sse") | |
1157 | + (set_attr "atom_sse_attr" "rcp") | |
1158 | (set_attr "prefix" "maybe_vex") | |
1159 | (set_attr "mode" "SF")]) | |
1160 | ||
1161 | @@ -16738,6 +16771,7 @@ | |
1162 | "TARGET_SSE_MATH" | |
1163 | "%vrsqrtss\t{%1, %d0|%d0, %1}" | |
1164 | [(set_attr "type" "sse") | |
1165 | + (set_attr "atom_sse_attr" "rcp") | |
1166 | (set_attr "prefix" "maybe_vex") | |
1167 | (set_attr "mode" "SF")]) | |
1168 | ||
1169 | @@ -16758,6 +16792,7 @@ | |
1170 | "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH" | |
1171 | "%vsqrts<ssemodefsuffix>\t{%1, %d0|%d0, %1}" | |
1172 | [(set_attr "type" "sse") | |
1173 | + (set_attr "atom_sse_attr" "sqrt") | |
1174 | (set_attr "prefix" "maybe_vex") | |
1175 | (set_attr "mode" "<MODE>") | |
1176 | (set_attr "athlon_decode" "*") | |
1177 | @@ -19811,6 +19846,7 @@ | |
1178 | ; Since we don't have the proper number of operands for an alu insn, | |
1179 | ; fill in all the blanks. | |
1180 | [(set_attr "type" "alu") | |
1181 | + (set_attr "use_carry" "1") | |
1182 | (set_attr "pent_pair" "pu") | |
1183 | (set_attr "memory" "none") | |
1184 | (set_attr "imm_disp" "false") | |
1185 | @@ -19826,6 +19862,7 @@ | |
1186 | "" | |
1187 | "sbb{q}\t%0, %0" | |
1188 | [(set_attr "type" "alu") | |
1189 | + (set_attr "use_carry" "1") | |
1190 | (set_attr "pent_pair" "pu") | |
1191 | (set_attr "memory" "none") | |
1192 | (set_attr "imm_disp" "false") | |
1193 | @@ -19869,6 +19906,7 @@ | |
1194 | ; Since we don't have the proper number of operands for an alu insn, | |
1195 | ; fill in all the blanks. | |
1196 | [(set_attr "type" "alu") | |
1197 | + (set_attr "use_carry" "1") | |
1198 | (set_attr "pent_pair" "pu") | |
1199 | (set_attr "memory" "none") | |
1200 | (set_attr "imm_disp" "false") | |
1201 | @@ -19884,6 +19922,7 @@ | |
1202 | "" | |
1203 | "sbb{l}\t%0, %0" | |
1204 | [(set_attr "type" "alu") | |
1205 | + (set_attr "use_carry" "1") | |
1206 | (set_attr "pent_pair" "pu") | |
1207 | (set_attr "memory" "none") | |
1208 | (set_attr "imm_disp" "false") | |
1209 | @@ -20216,7 +20255,8 @@ | |
1210 | } | |
1211 | } | |
1212 | [(set (attr "type") | |
1213 | - (cond [(eq_attr "alternative" "0") | |
1214 | + (cond [(and (eq_attr "alternative" "0") | |
1215 | + (eq (symbol_ref "TARGET_OPT_AGU") (const_int 0))) | |
1216 | (const_string "alu") | |
1217 | (match_operand:SI 2 "const0_operand" "") | |
1218 | (const_string "imov") | |
1219 | @@ -20259,7 +20299,8 @@ | |
1220 | } | |
1221 | } | |
1222 | [(set (attr "type") | |
1223 | - (cond [(eq_attr "alternative" "0") | |
1224 | + (cond [(and (eq_attr "alternative" "0") | |
1225 | + (eq (symbol_ref "TARGET_OPT_AGU") (const_int 0))) | |
1226 | (const_string "alu") | |
1227 | (match_operand:DI 2 "const0_operand" "") | |
1228 | (const_string "imov") | |
1229 | @@ -21751,6 +21792,7 @@ | |
1230 | return patterns[locality]; | |
1231 | } | |
1232 | [(set_attr "type" "sse") | |
1233 | + (set_attr "atom_sse_attr" "prefetch") | |
1234 | (set_attr "memory" "none")]) | |
1235 | ||
1236 | (define_insn "*prefetch_sse_rex" | |
1237 | @@ -21769,6 +21811,7 @@ | |
1238 | return patterns[locality]; | |
1239 | } | |
1240 | [(set_attr "type" "sse") | |
1241 | + (set_attr "atom_sse_attr" "prefetch") | |
1242 | (set_attr "memory" "none")]) | |
1243 | ||
1244 | (define_insn "*prefetch_3dnow" | |
1245 | Index: gcc/config/i386/atom.md | |
1246 | =================================================================== | |
1247 | --- gcc/config/i386/atom.md (.../tags/gcc_4_4_0_release) (revision 0) | |
1248 | +++ gcc/config/i386/atom.md (.../branches/ix86/gcc-4_4-branch) (revision 146537) | |
1249 | @@ -0,0 +1,795 @@ | |
1250 | +;; Atom Scheduling | |
1251 | +;; Copyright (C) 2009 Free Software Foundation, Inc. | |
1252 | +;; | |
1253 | +;; This file is part of GCC. | |
1254 | +;; | |
1255 | +;; GCC is free software; you can redistribute it and/or modify | |
1256 | +;; it under the terms of the GNU General Public License as published by | |
1257 | +;; the Free Software Foundation; either version 3, or (at your option) | |
1258 | +;; any later version. | |
1259 | +;; | |
1260 | +;; GCC is distributed in the hope that it will be useful, | |
1261 | +;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
1262 | +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
1263 | +;; GNU General Public License for more details. | |
1264 | +;; | |
1265 | +;; You should have received a copy of the GNU General Public License | |
1266 | +;; along with GCC; see the file COPYING3. If not see | |
1267 | +;; <http://www.gnu.org/licenses/>. | |
1268 | +;; | |
1269 | +;; Atom is an in-order core with two integer pipelines. | |
1270 | + | |
1271 | + | |
1272 | +(define_attr "atom_unit" "sishuf,simul,jeu,complex,other" | |
1273 | + (const_string "other")) | |
1274 | + | |
1275 | +(define_attr "atom_sse_attr" "rcp,movdup,lfence,fence,prefetch,sqrt,mxcsr,other" | |
1276 | + (const_string "other")) | |
1277 | + | |
1278 | +(define_automaton "atom") | |
1279 | + | |
1280 | +;; Atom has two ports: port 0 and port 1 connecting to all execution units | |
1281 | +(define_cpu_unit "atom-port-0,atom-port-1" "atom") | |
1282 | + | |
1283 | +;; EU: Execution Unit | |
1284 | +;; Atom EUs are connected by port 0 or port 1. | |
1285 | + | |
1286 | +(define_cpu_unit "atom-eu-0, atom-eu-1, | |
1287 | + atom-imul-1, atom-imul-2, atom-imul-3, atom-imul-4" | |
1288 | + "atom") | |
1289 | + | |
1290 | +;; Some EUs have duplicated copied and can be accessed via either | |
1291 | +;; port 0 or port 1 | |
1292 | +;; (define_reservation "atom-port-either" "(atom-port-0 | atom-port-1)") | |
1293 | + | |
1294 | +;;; Some instructions is dual-pipe execution, need both ports | |
1295 | +;;; Complex multi-op macro-instructoins need both ports and all EUs | |
1296 | +(define_reservation "atom-port-dual" "(atom-port-0 + atom-port-1)") | |
1297 | +(define_reservation "atom-all-eu" "(atom-eu-0 + atom-eu-1 + | |
1298 | + atom-imul-1 + atom-imul-2 + atom-imul-3 + | |
1299 | + atom-imul-4)") | |
1300 | + | |
1301 | +;;; Most of simple instructions have 1 cycle latency. Some of them | |
1302 | +;;; issue in port 0, some in port 0 and some in either port. | |
1303 | +(define_reservation "atom-simple-0" "(atom-port-0 + atom-eu-0)") | |
1304 | +(define_reservation "atom-simple-1" "(atom-port-1 + atom-eu-1)") | |
1305 | +(define_reservation "atom-simple-either" "(atom-simple-0 | atom-simple-1)") | |
1306 | + | |
1307 | +;;; Some insn issues in port 0 with 3 cycle latency and 1 cycle tput | |
1308 | +(define_reservation "atom-eu-0-3-1" "(atom-port-0 + atom-eu-0, nothing*2)") | |
1309 | + | |
1310 | +;;; fmul insn can have 4 or 5 cycles latency | |
1311 | +(define_reservation "atom-fmul-5c" "(atom-port-0 + atom-eu-0), nothing*4") | |
1312 | +(define_reservation "atom-fmul-4c" "(atom-port-0 + atom-eu-0), nothing*3") | |
1313 | + | |
1314 | +;;; fadd can has 5 cycles latency depends on instruction forms | |
1315 | +(define_reservation "atom-fadd-5c" "(atom-port-1 + atom-eu-1), nothing*5") | |
1316 | + | |
1317 | +;;; imul insn has 5 cycles latency | |
1318 | +(define_reservation "atom-imul-32" | |
1319 | + "atom-imul-1, atom-imul-2, atom-imul-3, atom-imul-4, | |
1320 | + atom-port-0") | |
1321 | +;;; imul instruction excludes other non-FP instructions. | |
1322 | +(exclusion_set "atom-eu-0, atom-eu-1" | |
1323 | + "atom-imul-1, atom-imul-2, atom-imul-3, atom-imul-4") | |
1324 | + | |
1325 | +;;; dual-execution instructions can have 1,2,4,5 cycles latency depends on | |
1326 | +;;; instruction forms | |
1327 | +(define_reservation "atom-dual-1c" "(atom-port-dual + atom-eu-0 + atom-eu-1)") | |
1328 | +(define_reservation "atom-dual-2c" | |
1329 | + "(atom-port-dual + atom-eu-0 + atom-eu-1, nothing)") | |
1330 | +(define_reservation "atom-dual-5c" | |
1331 | + "(atom-port-dual + atom-eu-0 + atom-eu-1, nothing*4)") | |
1332 | + | |
1333 | +;;; Complex macro-instruction has variants of latency, and uses both ports. | |
1334 | +(define_reservation "atom-complex" "(atom-port-dual + atom-all-eu)") | |
1335 | + | |
1336 | +(define_insn_reservation "atom_other" 9 | |
1337 | + (and (eq_attr "cpu" "atom") | |
1338 | + (and (eq_attr "type" "other") | |
1339 | + (eq_attr "atom_unit" "!jeu"))) | |
1340 | + "atom-complex, atom-all-eu*8") | |
1341 | + | |
1342 | +;; return has type "other" with atom_unit "jeu" | |
1343 | +(define_insn_reservation "atom_other_2" 1 | |
1344 | + (and (eq_attr "cpu" "atom") | |
1345 | + (and (eq_attr "type" "other") | |
1346 | + (eq_attr "atom_unit" "jeu"))) | |
1347 | + "atom-dual-1c") | |
1348 | + | |
1349 | +(define_insn_reservation "atom_multi" 9 | |
1350 | + (and (eq_attr "cpu" "atom") | |
1351 | + (eq_attr "type" "multi")) | |
1352 | + "atom-complex, atom-all-eu*8") | |
1353 | + | |
1354 | +;; Normal alu insns without carry | |
1355 | +(define_insn_reservation "atom_alu" 1 | |
1356 | + (and (eq_attr "cpu" "atom") | |
1357 | + (and (eq_attr "type" "alu") | |
1358 | + (and (eq_attr "memory" "none") | |
1359 | + (eq_attr "use_carry" "0")))) | |
1360 | + "atom-simple-either") | |
1361 | + | |
1362 | +;; Normal alu insns without carry | |
1363 | +(define_insn_reservation "atom_alu_mem" 1 | |
1364 | + (and (eq_attr "cpu" "atom") | |
1365 | + (and (eq_attr "type" "alu") | |
1366 | + (and (eq_attr "memory" "!none") | |
1367 | + (eq_attr "use_carry" "0")))) | |
1368 | + "atom-simple-either") | |
1369 | + | |
1370 | +;; Alu insn consuming CF, such as add/sbb | |
1371 | +(define_insn_reservation "atom_alu_carry" 1 | |
1372 | + (and (eq_attr "cpu" "atom") | |
1373 | + (and (eq_attr "type" "alu") | |
1374 | + (and (eq_attr "memory" "none") | |
1375 | + (eq_attr "use_carry" "1")))) | |
1376 | + "atom-simple-either") | |
1377 | + | |
1378 | +;; Alu insn consuming CF, such as add/sbb | |
1379 | +(define_insn_reservation "atom_alu_carry_mem" 1 | |
1380 | + (and (eq_attr "cpu" "atom") | |
1381 | + (and (eq_attr "type" "alu") | |
1382 | + (and (eq_attr "memory" "!none") | |
1383 | + (eq_attr "use_carry" "1")))) | |
1384 | + "atom-simple-either") | |
1385 | + | |
1386 | +(define_insn_reservation "atom_alu1" 1 | |
1387 | + (and (eq_attr "cpu" "atom") | |
1388 | + (and (eq_attr "type" "alu1") | |
1389 | + (eq_attr "memory" "none"))) | |
1390 | + "atom-simple-either") | |
1391 | + | |
1392 | +(define_insn_reservation "atom_alu1_mem" 1 | |
1393 | + (and (eq_attr "cpu" "atom") | |
1394 | + (and (eq_attr "type" "alu1") | |
1395 | + (eq_attr "memory" "!none"))) | |
1396 | + "atom-simple-either") | |
1397 | + | |
1398 | +(define_insn_reservation "atom_negnot" 1 | |
1399 | + (and (eq_attr "cpu" "atom") | |
1400 | + (and (eq_attr "type" "negnot") | |
1401 | + (eq_attr "memory" "none"))) | |
1402 | + "atom-simple-either") | |
1403 | + | |
1404 | +(define_insn_reservation "atom_negnot_mem" 1 | |
1405 | + (and (eq_attr "cpu" "atom") | |
1406 | + (and (eq_attr "type" "negnot") | |
1407 | + (eq_attr "memory" "!none"))) | |
1408 | + "atom-simple-either") | |
1409 | + | |
1410 | +(define_insn_reservation "atom_imov" 1 | |
1411 | + (and (eq_attr "cpu" "atom") | |
1412 | + (and (eq_attr "type" "imov") | |
1413 | + (eq_attr "memory" "none"))) | |
1414 | + "atom-simple-either") | |
1415 | + | |
1416 | +(define_insn_reservation "atom_imov_mem" 1 | |
1417 | + (and (eq_attr "cpu" "atom") | |
1418 | + (and (eq_attr "type" "imov") | |
1419 | + (eq_attr "memory" "!none"))) | |
1420 | + "atom-simple-either") | |
1421 | + | |
1422 | +;; 16<-16, 32<-32 | |
1423 | +(define_insn_reservation "atom_imovx" 1 | |
1424 | + (and (eq_attr "cpu" "atom") | |
1425 | + (and (eq_attr "type" "imovx") | |
1426 | + (and (eq_attr "memory" "none") | |
1427 | + (ior (and (match_operand:HI 0 "register_operand") | |
1428 | + (match_operand:HI 1 "general_operand")) | |
1429 | + (and (match_operand:SI 0 "register_operand") | |
1430 | + (match_operand:SI 1 "general_operand")))))) | |
1431 | + "atom-simple-either") | |
1432 | + | |
1433 | +;; 16<-16, 32<-32, mem | |
1434 | +(define_insn_reservation "atom_imovx_mem" 1 | |
1435 | + (and (eq_attr "cpu" "atom") | |
1436 | + (and (eq_attr "type" "imovx") | |
1437 | + (and (eq_attr "memory" "!none") | |
1438 | + (ior (and (match_operand:HI 0 "register_operand") | |
1439 | + (match_operand:HI 1 "general_operand")) | |
1440 | + (and (match_operand:SI 0 "register_operand") | |
1441 | + (match_operand:SI 1 "general_operand")))))) | |
1442 | + "atom-simple-either") | |
1443 | + | |
1444 | +;; 32<-16, 32<-8, 64<-16, 64<-8, 64<-32, 8<-8 | |
1445 | +(define_insn_reservation "atom_imovx_2" 1 | |
1446 | + (and (eq_attr "cpu" "atom") | |
1447 | + (and (eq_attr "type" "imovx") | |
1448 | + (and (eq_attr "memory" "none") | |
1449 | + (ior (match_operand:QI 0 "register_operand") | |
1450 | + (ior (and (match_operand:SI 0 "register_operand") | |
1451 | + (not (match_operand:SI 1 "general_operand"))) | |
1452 | + (match_operand:DI 0 "register_operand")))))) | |
1453 | + "atom-simple-0") | |
1454 | + | |
1455 | +;; 32<-16, 32<-8, 64<-16, 64<-8, 64<-32, 8<-8, mem | |
1456 | +(define_insn_reservation "atom_imovx_2_mem" 1 | |
1457 | + (and (eq_attr "cpu" "atom") | |
1458 | + (and (eq_attr "type" "imovx") | |
1459 | + (and (eq_attr "memory" "!none") | |
1460 | + (ior (match_operand:QI 0 "register_operand") | |
1461 | + (ior (and (match_operand:SI 0 "register_operand") | |
1462 | + (not (match_operand:SI 1 "general_operand"))) | |
1463 | + (match_operand:DI 0 "register_operand")))))) | |
1464 | + "atom-simple-0") | |
1465 | + | |
1466 | +;; 16<-8 | |
1467 | +(define_insn_reservation "atom_imovx_3" 3 | |
1468 | + (and (eq_attr "cpu" "atom") | |
1469 | + (and (eq_attr "type" "imovx") | |
1470 | + (and (match_operand:HI 0 "register_operand") | |
1471 | + (match_operand:QI 1 "general_operand")))) | |
1472 | + "atom-complex, atom-all-eu*2") | |
1473 | + | |
1474 | +(define_insn_reservation "atom_lea" 1 | |
1475 | + (and (eq_attr "cpu" "atom") | |
1476 | + (and (eq_attr "type" "lea") | |
1477 | + (eq_attr "mode" "!HI"))) | |
1478 | + "atom-simple-either") | |
1479 | + | |
1480 | +;; lea 16bit address is complex insn | |
1481 | +(define_insn_reservation "atom_lea_2" 2 | |
1482 | + (and (eq_attr "cpu" "atom") | |
1483 | + (and (eq_attr "type" "lea") | |
1484 | + (eq_attr "mode" "HI"))) | |
1485 | + "atom-complex, atom-all-eu") | |
1486 | + | |
1487 | +(define_insn_reservation "atom_incdec" 1 | |
1488 | + (and (eq_attr "cpu" "atom") | |
1489 | + (and (eq_attr "type" "incdec") | |
1490 | + (eq_attr "memory" "none"))) | |
1491 | + "atom-simple-either") | |
1492 | + | |
1493 | +(define_insn_reservation "atom_incdec_mem" 1 | |
1494 | + (and (eq_attr "cpu" "atom") | |
1495 | + (and (eq_attr "type" "incdec") | |
1496 | + (eq_attr "memory" "!none"))) | |
1497 | + "atom-simple-either") | |
1498 | + | |
1499 | +;; simple shift instruction use SHIFT eu, none memory | |
1500 | +(define_insn_reservation "atom_ishift" 1 | |
1501 | + (and (eq_attr "cpu" "atom") | |
1502 | + (and (eq_attr "type" "ishift") | |
1503 | + (and (eq_attr "memory" "none") (eq_attr "prefix_0f" "0")))) | |
1504 | + "atom-simple-0") | |
1505 | + | |
1506 | +;; simple shift instruction use SHIFT eu, memory | |
1507 | +(define_insn_reservation "atom_ishift_mem" 1 | |
1508 | + (and (eq_attr "cpu" "atom") | |
1509 | + (and (eq_attr "type" "ishift") | |
1510 | + (and (eq_attr "memory" "!none") (eq_attr "prefix_0f" "0")))) | |
1511 | + "atom-simple-0") | |
1512 | + | |
1513 | +;; DF shift (prefixed with 0f) is complex insn with latency of 7 cycles | |
1514 | +(define_insn_reservation "atom_ishift_3" 7 | |
1515 | + (and (eq_attr "cpu" "atom") | |
1516 | + (and (eq_attr "type" "ishift") | |
1517 | + (eq_attr "prefix_0f" "1"))) | |
1518 | + "atom-complex, atom-all-eu*6") | |
1519 | + | |
1520 | +(define_insn_reservation "atom_ishift1" 1 | |
1521 | + (and (eq_attr "cpu" "atom") | |
1522 | + (and (eq_attr "type" "ishift1") | |
1523 | + (eq_attr "memory" "none"))) | |
1524 | + "atom-simple-0") | |
1525 | + | |
1526 | +(define_insn_reservation "atom_ishift1_mem" 1 | |
1527 | + (and (eq_attr "cpu" "atom") | |
1528 | + (and (eq_attr "type" "ishift1") | |
1529 | + (eq_attr "memory" "!none"))) | |
1530 | + "atom-simple-0") | |
1531 | + | |
1532 | +(define_insn_reservation "atom_rotate" 1 | |
1533 | + (and (eq_attr "cpu" "atom") | |
1534 | + (and (eq_attr "type" "rotate") | |
1535 | + (eq_attr "memory" "none"))) | |
1536 | + "atom-simple-0") | |
1537 | + | |
1538 | +(define_insn_reservation "atom_rotate_mem" 1 | |
1539 | + (and (eq_attr "cpu" "atom") | |
1540 | + (and (eq_attr "type" "rotate") | |
1541 | + (eq_attr "memory" "!none"))) | |
1542 | + "atom-simple-0") | |
1543 | + | |
1544 | +(define_insn_reservation "atom_rotate1" 1 | |
1545 | + (and (eq_attr "cpu" "atom") | |
1546 | + (and (eq_attr "type" "rotate1") | |
1547 | + (eq_attr "memory" "none"))) | |
1548 | + "atom-simple-0") | |
1549 | + | |
1550 | +(define_insn_reservation "atom_rotate1_mem" 1 | |
1551 | + (and (eq_attr "cpu" "atom") | |
1552 | + (and (eq_attr "type" "rotate1") | |
1553 | + (eq_attr "memory" "!none"))) | |
1554 | + "atom-simple-0") | |
1555 | + | |
1556 | +(define_insn_reservation "atom_imul" 5 | |
1557 | + (and (eq_attr "cpu" "atom") | |
1558 | + (and (eq_attr "type" "imul") | |
1559 | + (and (eq_attr "memory" "none") (eq_attr "mode" "SI")))) | |
1560 | + "atom-imul-32") | |
1561 | + | |
1562 | +(define_insn_reservation "atom_imul_mem" 5 | |
1563 | + (and (eq_attr "cpu" "atom") | |
1564 | + (and (eq_attr "type" "imul") | |
1565 | + (and (eq_attr "memory" "!none") (eq_attr "mode" "SI")))) | |
1566 | + "atom-imul-32") | |
1567 | + | |
1568 | +;; latency set to 10 as common 64x64 imul | |
1569 | +(define_insn_reservation "atom_imul_3" 10 | |
1570 | + (and (eq_attr "cpu" "atom") | |
1571 | + (and (eq_attr "type" "imul") | |
1572 | + (eq_attr "mode" "!SI"))) | |
1573 | + "atom-complex, atom-all-eu*9") | |
1574 | + | |
1575 | +(define_insn_reservation "atom_idiv" 65 | |
1576 | + (and (eq_attr "cpu" "atom") | |
1577 | + (eq_attr "type" "idiv")) | |
1578 | + "atom-complex, atom-all-eu*32, nothing*32") | |
1579 | + | |
1580 | +(define_insn_reservation "atom_icmp" 1 | |
1581 | + (and (eq_attr "cpu" "atom") | |
1582 | + (and (eq_attr "type" "icmp") | |
1583 | + (eq_attr "memory" "none"))) | |
1584 | + "atom-simple-either") | |
1585 | + | |
1586 | +(define_insn_reservation "atom_icmp_mem" 1 | |
1587 | + (and (eq_attr "cpu" "atom") | |
1588 | + (and (eq_attr "type" "icmp") | |
1589 | + (eq_attr "memory" "!none"))) | |
1590 | + "atom-simple-either") | |
1591 | + | |
1592 | +(define_insn_reservation "atom_test" 1 | |
1593 | + (and (eq_attr "cpu" "atom") | |
1594 | + (and (eq_attr "type" "test") | |
1595 | + (eq_attr "memory" "none"))) | |
1596 | + "atom-simple-either") | |
1597 | + | |
1598 | +(define_insn_reservation "atom_test_mem" 1 | |
1599 | + (and (eq_attr "cpu" "atom") | |
1600 | + (and (eq_attr "type" "test") | |
1601 | + (eq_attr "memory" "!none"))) | |
1602 | + "atom-simple-either") | |
1603 | + | |
1604 | +(define_insn_reservation "atom_ibr" 1 | |
1605 | + (and (eq_attr "cpu" "atom") | |
1606 | + (and (eq_attr "type" "ibr") | |
1607 | + (eq_attr "memory" "!load"))) | |
1608 | + "atom-simple-1") | |
1609 | + | |
1610 | +;; complex if jump target is from address | |
1611 | +(define_insn_reservation "atom_ibr_2" 2 | |
1612 | + (and (eq_attr "cpu" "atom") | |
1613 | + (and (eq_attr "type" "ibr") | |
1614 | + (eq_attr "memory" "load"))) | |
1615 | + "atom-complex, atom-all-eu") | |
1616 | + | |
1617 | +(define_insn_reservation "atom_setcc" 1 | |
1618 | + (and (eq_attr "cpu" "atom") | |
1619 | + (and (eq_attr "type" "setcc") | |
1620 | + (eq_attr "memory" "!store"))) | |
1621 | + "atom-simple-either") | |
1622 | + | |
1623 | +;; 2 cycles complex if target is in memory | |
1624 | +(define_insn_reservation "atom_setcc_2" 2 | |
1625 | + (and (eq_attr "cpu" "atom") | |
1626 | + (and (eq_attr "type" "setcc") | |
1627 | + (eq_attr "memory" "store"))) | |
1628 | + "atom-complex, atom-all-eu") | |
1629 | + | |
1630 | +(define_insn_reservation "atom_icmov" 1 | |
1631 | + (and (eq_attr "cpu" "atom") | |
1632 | + (and (eq_attr "type" "icmov") | |
1633 | + (eq_attr "memory" "none"))) | |
1634 | + "atom-simple-either") | |
1635 | + | |
1636 | +(define_insn_reservation "atom_icmov_mem" 1 | |
1637 | + (and (eq_attr "cpu" "atom") | |
1638 | + (and (eq_attr "type" "icmov") | |
1639 | + (eq_attr "memory" "!none"))) | |
1640 | + "atom-simple-either") | |
1641 | + | |
1642 | +;; UCODE if segreg, ignored | |
1643 | +(define_insn_reservation "atom_push" 2 | |
1644 | + (and (eq_attr "cpu" "atom") | |
1645 | + (eq_attr "type" "push")) | |
1646 | + "atom-dual-2c") | |
1647 | + | |
1648 | +;; pop r64 is 1 cycle. UCODE if segreg, ignored | |
1649 | +(define_insn_reservation "atom_pop" 1 | |
1650 | + (and (eq_attr "cpu" "atom") | |
1651 | + (and (eq_attr "type" "pop") | |
1652 | + (eq_attr "mode" "DI"))) | |
1653 | + "atom-dual-1c") | |
1654 | + | |
1655 | +;; pop non-r64 is 2 cycles. UCODE if segreg, ignored | |
1656 | +(define_insn_reservation "atom_pop_2" 2 | |
1657 | + (and (eq_attr "cpu" "atom") | |
1658 | + (and (eq_attr "type" "pop") | |
1659 | + (eq_attr "mode" "!DI"))) | |
1660 | + "atom-dual-2c") | |
1661 | + | |
1662 | +;; UCODE if segreg, ignored | |
1663 | +(define_insn_reservation "atom_call" 1 | |
1664 | + (and (eq_attr "cpu" "atom") | |
1665 | + (eq_attr "type" "call")) | |
1666 | + "atom-dual-1c") | |
1667 | + | |
1668 | +(define_insn_reservation "atom_callv" 1 | |
1669 | + (and (eq_attr "cpu" "atom") | |
1670 | + (eq_attr "type" "callv")) | |
1671 | + "atom-dual-1c") | |
1672 | + | |
1673 | +(define_insn_reservation "atom_leave" 3 | |
1674 | + (and (eq_attr "cpu" "atom") | |
1675 | + (eq_attr "type" "leave")) | |
1676 | + "atom-complex, atom-all-eu*2") | |
1677 | + | |
1678 | +(define_insn_reservation "atom_str" 3 | |
1679 | + (and (eq_attr "cpu" "atom") | |
1680 | + (eq_attr "type" "str")) | |
1681 | + "atom-complex, atom-all-eu*2") | |
1682 | + | |
1683 | +(define_insn_reservation "atom_sselog" 1 | |
1684 | + (and (eq_attr "cpu" "atom") | |
1685 | + (and (eq_attr "type" "sselog") | |
1686 | + (eq_attr "memory" "none"))) | |
1687 | + "atom-simple-either") | |
1688 | + | |
1689 | +(define_insn_reservation "atom_sselog_mem" 1 | |
1690 | + (and (eq_attr "cpu" "atom") | |
1691 | + (and (eq_attr "type" "sselog") | |
1692 | + (eq_attr "memory" "!none"))) | |
1693 | + "atom-simple-either") | |
1694 | + | |
1695 | +(define_insn_reservation "atom_sselog1" 1 | |
1696 | + (and (eq_attr "cpu" "atom") | |
1697 | + (and (eq_attr "type" "sselog1") | |
1698 | + (eq_attr "memory" "none"))) | |
1699 | + "atom-simple-0") | |
1700 | + | |
1701 | +(define_insn_reservation "atom_sselog1_mem" 1 | |
1702 | + (and (eq_attr "cpu" "atom") | |
1703 | + (and (eq_attr "type" "sselog1") | |
1704 | + (eq_attr "memory" "!none"))) | |
1705 | + "atom-simple-0") | |
1706 | + | |
1707 | +;; not pmad, not psad | |
1708 | +(define_insn_reservation "atom_sseiadd" 1 | |
1709 | + (and (eq_attr "cpu" "atom") | |
1710 | + (and (eq_attr "type" "sseiadd") | |
1711 | + (and (not (match_operand:V2DI 0 "register_operand")) | |
1712 | + (and (eq_attr "atom_unit" "!simul") | |
1713 | + (eq_attr "atom_unit" "!complex"))))) | |
1714 | + "atom-simple-either") | |
1715 | + | |
1716 | +;; pmad, psad and 64 | |
1717 | +(define_insn_reservation "atom_sseiadd_2" 4 | |
1718 | + (and (eq_attr "cpu" "atom") | |
1719 | + (and (eq_attr "type" "sseiadd") | |
1720 | + (and (not (match_operand:V2DI 0 "register_operand")) | |
1721 | + (and (eq_attr "atom_unit" "simul" ) | |
1722 | + (eq_attr "mode" "DI"))))) | |
1723 | + "atom-fmul-4c") | |
1724 | + | |
1725 | +;; pmad, psad and 128 | |
1726 | +(define_insn_reservation "atom_sseiadd_3" 5 | |
1727 | + (and (eq_attr "cpu" "atom") | |
1728 | + (and (eq_attr "type" "sseiadd") | |
1729 | + (and (not (match_operand:V2DI 0 "register_operand")) | |
1730 | + (and (eq_attr "atom_unit" "simul" ) | |
1731 | + (eq_attr "mode" "TI"))))) | |
1732 | + "atom-fmul-5c") | |
1733 | + | |
1734 | +;; if paddq(64 bit op), phadd/phsub | |
1735 | +(define_insn_reservation "atom_sseiadd_4" 6 | |
1736 | + (and (eq_attr "cpu" "atom") | |
1737 | + (and (eq_attr "type" "sseiadd") | |
1738 | + (ior (match_operand:V2DI 0 "register_operand") | |
1739 | + (eq_attr "atom_unit" "complex")))) | |
1740 | + "atom-complex, atom-all-eu*5") | |
1741 | + | |
1742 | +;; if immediate op. | |
1743 | +(define_insn_reservation "atom_sseishft" 1 | |
1744 | + (and (eq_attr "cpu" "atom") | |
1745 | + (and (eq_attr "type" "sseishft") | |
1746 | + (and (eq_attr "atom_unit" "!sishuf") | |
1747 | + (match_operand 2 "immediate_operand")))) | |
1748 | + "atom-simple-either") | |
1749 | + | |
1750 | +;; if palignr or psrldq | |
1751 | +(define_insn_reservation "atom_sseishft_2" 1 | |
1752 | + (and (eq_attr "cpu" "atom") | |
1753 | + (and (eq_attr "type" "sseishft") | |
1754 | + (and (eq_attr "atom_unit" "sishuf") | |
1755 | + (match_operand 2 "immediate_operand")))) | |
1756 | + "atom-simple-0") | |
1757 | + | |
1758 | +;; if reg/mem op | |
1759 | +(define_insn_reservation "atom_sseishft_3" 2 | |
1760 | + (and (eq_attr "cpu" "atom") | |
1761 | + (and (eq_attr "type" "sseishft") | |
1762 | + (not (match_operand 2 "immediate_operand")))) | |
1763 | + "atom-complex, atom-all-eu") | |
1764 | + | |
1765 | +(define_insn_reservation "atom_sseimul" 1 | |
1766 | + (and (eq_attr "cpu" "atom") | |
1767 | + (eq_attr "type" "sseimul")) | |
1768 | + "atom-simple-0") | |
1769 | + | |
1770 | +;; rcpss or rsqrtss | |
1771 | +(define_insn_reservation "atom_sse" 4 | |
1772 | + (and (eq_attr "cpu" "atom") | |
1773 | + (and (eq_attr "type" "sse") | |
1774 | + (and (eq_attr "atom_sse_attr" "rcp") (eq_attr "mode" "SF")))) | |
1775 | + "atom-fmul-4c") | |
1776 | + | |
1777 | +;; movshdup, movsldup. Suggest to type sseishft | |
1778 | +(define_insn_reservation "atom_sse_2" 1 | |
1779 | + (and (eq_attr "cpu" "atom") | |
1780 | + (and (eq_attr "type" "sse") | |
1781 | + (eq_attr "atom_sse_attr" "movdup"))) | |
1782 | + "atom-simple-0") | |
1783 | + | |
1784 | +;; lfence | |
1785 | +(define_insn_reservation "atom_sse_3" 1 | |
1786 | + (and (eq_attr "cpu" "atom") | |
1787 | + (and (eq_attr "type" "sse") | |
1788 | + (eq_attr "atom_sse_attr" "lfence"))) | |
1789 | + "atom-simple-either") | |
1790 | + | |
1791 | +;; sfence,clflush,mfence, prefetch | |
1792 | +(define_insn_reservation "atom_sse_4" 1 | |
1793 | + (and (eq_attr "cpu" "atom") | |
1794 | + (and (eq_attr "type" "sse") | |
1795 | + (ior (eq_attr "atom_sse_attr" "fence") | |
1796 | + (eq_attr "atom_sse_attr" "prefetch")))) | |
1797 | + "atom-simple-0") | |
1798 | + | |
1799 | +;; rcpps, rsqrtss, sqrt, ldmxcsr | |
1800 | +(define_insn_reservation "atom_sse_5" 7 | |
1801 | + (and (eq_attr "cpu" "atom") | |
1802 | + (and (eq_attr "type" "sse") | |
1803 | + (ior (ior (eq_attr "atom_sse_attr" "sqrt") | |
1804 | + (eq_attr "atom_sse_attr" "mxcsr")) | |
1805 | + (and (eq_attr "atom_sse_attr" "rcp") | |
1806 | + (eq_attr "mode" "V4SF"))))) | |
1807 | + "atom-complex, atom-all-eu*6") | |
1808 | + | |
1809 | +;; xmm->xmm | |
1810 | +(define_insn_reservation "atom_ssemov" 1 | |
1811 | + (and (eq_attr "cpu" "atom") | |
1812 | + (and (eq_attr "type" "ssemov") | |
1813 | + (and (match_operand 0 "register_operand" "xy") (match_operand 1 "register_operand" "xy")))) | |
1814 | + "atom-simple-either") | |
1815 | + | |
1816 | +;; reg->xmm | |
1817 | +(define_insn_reservation "atom_ssemov_2" 1 | |
1818 | + (and (eq_attr "cpu" "atom") | |
1819 | + (and (eq_attr "type" "ssemov") | |
1820 | + (and (match_operand 0 "register_operand" "xy") (match_operand 1 "register_operand" "r")))) | |
1821 | + "atom-simple-0") | |
1822 | + | |
1823 | +;; xmm->reg | |
1824 | +(define_insn_reservation "atom_ssemov_3" 3 | |
1825 | + (and (eq_attr "cpu" "atom") | |
1826 | + (and (eq_attr "type" "ssemov") | |
1827 | + (and (match_operand 0 "register_operand" "r") (match_operand 1 "register_operand" "xy")))) | |
1828 | + "atom-eu-0-3-1") | |
1829 | + | |
1830 | +;; mov mem | |
1831 | +(define_insn_reservation "atom_ssemov_4" 1 | |
1832 | + (and (eq_attr "cpu" "atom") | |
1833 | + (and (eq_attr "type" "ssemov") | |
1834 | + (and (eq_attr "movu" "0") (eq_attr "memory" "!none")))) | |
1835 | + "atom-simple-0") | |
1836 | + | |
1837 | +;; movu mem | |
1838 | +(define_insn_reservation "atom_ssemov_5" 2 | |
1839 | + (and (eq_attr "cpu" "atom") | |
1840 | + (and (eq_attr "type" "ssemov") | |
1841 | + (ior (eq_attr "movu" "1") (eq_attr "memory" "!none")))) | |
1842 | + "atom-complex, atom-all-eu") | |
1843 | + | |
1844 | +;; no memory simple | |
1845 | +(define_insn_reservation "atom_sseadd" 5 | |
1846 | + (and (eq_attr "cpu" "atom") | |
1847 | + (and (eq_attr "type" "sseadd") | |
1848 | + (and (eq_attr "memory" "none") | |
1849 | + (and (eq_attr "mode" "!V2DF") | |
1850 | + (eq_attr "atom_unit" "!complex"))))) | |
1851 | + "atom-fadd-5c") | |
1852 | + | |
1853 | +;; memory simple | |
1854 | +(define_insn_reservation "atom_sseadd_mem" 5 | |
1855 | + (and (eq_attr "cpu" "atom") | |
1856 | + (and (eq_attr "type" "sseadd") | |
1857 | + (and (eq_attr "memory" "!none") | |
1858 | + (and (eq_attr "mode" "!V2DF") | |
1859 | + (eq_attr "atom_unit" "!complex"))))) | |
1860 | + "atom-dual-5c") | |
1861 | + | |
1862 | +;; maxps, minps, *pd, hadd, hsub | |
1863 | +(define_insn_reservation "atom_sseadd_3" 8 | |
1864 | + (and (eq_attr "cpu" "atom") | |
1865 | + (and (eq_attr "type" "sseadd") | |
1866 | + (ior (eq_attr "mode" "V2DF") (eq_attr "atom_unit" "complex")))) | |
1867 | + "atom-complex, atom-all-eu*7") | |
1868 | + | |
1869 | +;; Except dppd/dpps | |
1870 | +(define_insn_reservation "atom_ssemul" 5 | |
1871 | + (and (eq_attr "cpu" "atom") | |
1872 | + (and (eq_attr "type" "ssemul") | |
1873 | + (eq_attr "mode" "!SF"))) | |
1874 | + "atom-fmul-5c") | |
1875 | + | |
1876 | +;; Except dppd/dpps, 4 cycle if mulss | |
1877 | +(define_insn_reservation "atom_ssemul_2" 4 | |
1878 | + (and (eq_attr "cpu" "atom") | |
1879 | + (and (eq_attr "type" "ssemul") | |
1880 | + (eq_attr "mode" "SF"))) | |
1881 | + "atom-fmul-4c") | |
1882 | + | |
1883 | +(define_insn_reservation "atom_ssecmp" 1 | |
1884 | + (and (eq_attr "cpu" "atom") | |
1885 | + (eq_attr "type" "ssecmp")) | |
1886 | + "atom-simple-either") | |
1887 | + | |
1888 | +(define_insn_reservation "atom_ssecomi" 10 | |
1889 | + (and (eq_attr "cpu" "atom") | |
1890 | + (eq_attr "type" "ssecomi")) | |
1891 | + "atom-complex, atom-all-eu*9") | |
1892 | + | |
1893 | +;; no memory and cvtpi2ps, cvtps2pi, cvttps2pi | |
1894 | +(define_insn_reservation "atom_ssecvt" 5 | |
1895 | + (and (eq_attr "cpu" "atom") | |
1896 | + (and (eq_attr "type" "ssecvt") | |
1897 | + (ior (and (match_operand:V2SI 0 "register_operand") | |
1898 | + (match_operand:V4SF 1 "register_operand")) | |
1899 | + (and (match_operand:V4SF 0 "register_operand") | |
1900 | + (match_operand:V2SI 1 "register_operand"))))) | |
1901 | + "atom-fadd-5c") | |
1902 | + | |
1903 | +;; memory and cvtpi2ps, cvtps2pi, cvttps2pi | |
1904 | +(define_insn_reservation "atom_ssecvt_2" 5 | |
1905 | + (and (eq_attr "cpu" "atom") | |
1906 | + (and (eq_attr "type" "ssecvt") | |
1907 | + (ior (and (match_operand:V2SI 0 "register_operand") | |
1908 | + (match_operand:V4SF 1 "memory_operand")) | |
1909 | + (and (match_operand:V4SF 0 "register_operand") | |
1910 | + (match_operand:V2SI 1 "memory_operand"))))) | |
1911 | + "atom-dual-5c") | |
1912 | + | |
1913 | +;; otherwise. 7 cycles average for cvtss2sd | |
1914 | +(define_insn_reservation "atom_ssecvt_3" 7 | |
1915 | + (and (eq_attr "cpu" "atom") | |
1916 | + (and (eq_attr "type" "ssecvt") | |
1917 | + (not (ior (and (match_operand:V2SI 0 "register_operand") | |
1918 | + (match_operand:V4SF 1 "nonimmediate_operand")) | |
1919 | + (and (match_operand:V4SF 0 "register_operand") | |
1920 | + (match_operand:V2SI 1 "nonimmediate_operand")))))) | |
1921 | + "atom-complex, atom-all-eu*6") | |
1922 | + | |
1923 | +;; memory and cvtsi2sd | |
1924 | +(define_insn_reservation "atom_sseicvt" 5 | |
1925 | + (and (eq_attr "cpu" "atom") | |
1926 | + (and (eq_attr "type" "sseicvt") | |
1927 | + (and (match_operand:V2DF 0 "register_operand") | |
1928 | + (match_operand:SI 1 "memory_operand")))) | |
1929 | + "atom-dual-5c") | |
1930 | + | |
1931 | +;; otherwise. 8 cycles average for cvtsd2si | |
1932 | +(define_insn_reservation "atom_sseicvt_2" 8 | |
1933 | + (and (eq_attr "cpu" "atom") | |
1934 | + (and (eq_attr "type" "sseicvt") | |
1935 | + (not (and (match_operand:V2DF 0 "register_operand") | |
1936 | + (match_operand:SI 1 "memory_operand"))))) | |
1937 | + "atom-complex, atom-all-eu*7") | |
1938 | + | |
1939 | +(define_insn_reservation "atom_ssediv" 62 | |
1940 | + (and (eq_attr "cpu" "atom") | |
1941 | + (eq_attr "type" "ssediv")) | |
1942 | + "atom-complex, atom-all-eu*12, nothing*49") | |
1943 | + | |
1944 | +;; simple for fmov | |
1945 | +(define_insn_reservation "atom_fmov" 1 | |
1946 | + (and (eq_attr "cpu" "atom") | |
1947 | + (and (eq_attr "type" "fmov") | |
1948 | + (eq_attr "memory" "none"))) | |
1949 | + "atom-simple-either") | |
1950 | + | |
1951 | +;; simple for fmov | |
1952 | +(define_insn_reservation "atom_fmov_mem" 1 | |
1953 | + (and (eq_attr "cpu" "atom") | |
1954 | + (and (eq_attr "type" "fmov") | |
1955 | + (eq_attr "memory" "!none"))) | |
1956 | + "atom-simple-either") | |
1957 | + | |
1958 | +;; Define bypass here | |
1959 | + | |
1960 | +;; There will be no stall from lea to non-mem EX insns | |
1961 | +(define_bypass 0 "atom_lea" | |
1962 | + "atom_alu_carry, | |
1963 | + atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx, | |
1964 | + atom_incdec, atom_setcc, atom_icmov, atom_pop") | |
1965 | + | |
1966 | +(define_bypass 0 "atom_lea" | |
1967 | + "atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem, | |
1968 | + atom_imovx_mem, atom_imovx_2_mem, | |
1969 | + atom_imov_mem, atom_icmov_mem, atom_fmov_mem" | |
1970 | + "!ix86_agi_dependent") | |
1971 | + | |
1972 | +;; There will be 3 cycles stall from EX insns to AGAN insns LEA | |
1973 | +(define_bypass 4 "atom_alu_carry, | |
1974 | + atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx, | |
1975 | + atom_incdec,atom_ishift,atom_ishift1,atom_rotate, | |
1976 | + atom_rotate1, atom_setcc, atom_icmov, atom_pop, | |
1977 | + atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem, | |
1978 | + atom_imovx_mem, atom_imovx_2_mem, | |
1979 | + atom_imov_mem, atom_icmov_mem, atom_fmov_mem" | |
1980 | + "atom_lea") | |
1981 | + | |
1982 | +;; There will be 3 cycles stall from EX insns to insns need addr calculation | |
1983 | +(define_bypass 4 "atom_alu_carry, | |
1984 | + atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx, | |
1985 | + atom_incdec,atom_ishift,atom_ishift1,atom_rotate, | |
1986 | + atom_rotate1, atom_setcc, atom_icmov, atom_pop, | |
1987 | + atom_imovx_mem, atom_imovx_2_mem, | |
1988 | + atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem, | |
1989 | + atom_imov_mem, atom_icmov_mem, atom_fmov_mem" | |
1990 | + "atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem, | |
1991 | + atom_negnot_mem, atom_imov_mem, atom_incdec_mem, | |
1992 | + atom_imovx_mem, atom_imovx_2_mem, | |
1993 | + atom_imul_mem, atom_icmp_mem, | |
1994 | + atom_test_mem, atom_icmov_mem, atom_sselog_mem, | |
1995 | + atom_sselog1_mem, atom_fmov_mem, atom_sseadd_mem, | |
1996 | + atom_ishift_mem, atom_ishift1_mem, | |
1997 | + atom_rotate_mem, atom_rotate1_mem" | |
1998 | + "ix86_agi_dependent") | |
1999 | + | |
2000 | +;; Stall from imul to lea is 8 cycles. | |
2001 | +(define_bypass 9 "atom_imul, atom_imul_mem" "atom_lea") | |
2002 | + | |
2003 | +;; Stall from imul to memory address is 8 cycles. | |
2004 | +(define_bypass 9 "atom_imul, atom_imul_mem" | |
2005 | + "atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem, | |
2006 | + atom_negnot_mem, atom_imov_mem, atom_incdec_mem, | |
2007 | + atom_ishift_mem, atom_ishift1_mem, atom_rotate_mem, | |
2008 | + atom_rotate1_mem, atom_imul_mem, atom_icmp_mem, | |
2009 | + atom_test_mem, atom_icmov_mem, atom_sselog_mem, | |
2010 | + atom_sselog1_mem, atom_fmov_mem, atom_sseadd_mem" | |
2011 | + "ix86_agi_dependent") | |
2012 | + | |
2013 | +;; There will be 0 cycle stall from cmp/test to jcc | |
2014 | + | |
2015 | +;; There will be 1 cycle stall from flag producer to cmov and adc/sbb | |
2016 | +(define_bypass 2 "atom_icmp, atom_test, atom_alu, atom_alu_carry, | |
2017 | + atom_alu1, atom_negnot, atom_incdec, atom_ishift, | |
2018 | + atom_ishift1, atom_rotate, atom_rotate1" | |
2019 | + "atom_icmov, atom_alu_carry") | |
2020 | + | |
2021 | +;; lea to shift count stall is 2 cycles | |
2022 | +(define_bypass 3 "atom_lea" | |
2023 | + "atom_ishift, atom_ishift1, atom_rotate, atom_rotate1, | |
2024 | + atom_ishift_mem, atom_ishift1_mem, | |
2025 | + atom_rotate_mem, atom_rotate1_mem" | |
2026 | + "ix86_dep_by_shift_count") | |
2027 | + | |
2028 | +;; lea to shift source stall is 1 cycle | |
2029 | +(define_bypass 2 "atom_lea" | |
2030 | + "atom_ishift, atom_ishift1, atom_rotate, atom_rotate1" | |
2031 | + "!ix86_dep_by_shift_count") | |
2032 | + | |
2033 | +;; non-lea to shift count stall is 1 cycle | |
2034 | +(define_bypass 2 "atom_alu_carry, | |
2035 | + atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx, | |
2036 | + atom_incdec,atom_ishift,atom_ishift1,atom_rotate, | |
2037 | + atom_rotate1, atom_setcc, atom_icmov, atom_pop, | |
2038 | + atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem, | |
2039 | + atom_imovx_mem, atom_imovx_2_mem, | |
2040 | + atom_imov_mem, atom_icmov_mem, atom_fmov_mem" | |
2041 | + "atom_ishift, atom_ishift1, atom_rotate, atom_rotate1, | |
2042 | + atom_ishift_mem, atom_ishift1_mem, | |
2043 | + atom_rotate_mem, atom_rotate1_mem" | |
2044 | + "ix86_dep_by_shift_count") | |
2045 | Index: gcc/config/i386/sse.md | |
2046 | =================================================================== | |
2047 | --- gcc/config/i386/sse.md (.../tags/gcc_4_4_0_release) (revision 146537) | |
2048 | +++ gcc/config/i386/sse.md (.../branches/ix86/gcc-4_4-branch) (revision 146537) | |
2049 | @@ -338,6 +338,7 @@ | |
2050 | && !(MEM_P (operands[0]) && MEM_P (operands[1]))" | |
2051 | "vmovup<avxmodesuffixf2c>\t{%1, %0|%0, %1}" | |
2052 | [(set_attr "type" "ssemov") | |
2053 | + (set_attr "movu" "1") | |
2054 | (set_attr "prefix" "vex") | |
2055 | (set_attr "mode" "<MODE>")]) | |
2056 | ||
2057 | @@ -363,6 +364,7 @@ | |
2058 | && !(MEM_P (operands[0]) && MEM_P (operands[1]))" | |
2059 | "movup<ssemodesuffixf2c>\t{%1, %0|%0, %1}" | |
2060 | [(set_attr "type" "ssemov") | |
2061 | + (set_attr "movu" "1") | |
2062 | (set_attr "mode" "<MODE>")]) | |
2063 | ||
2064 | (define_insn "avx_movdqu<avxmodesuffix>" | |
2065 | @@ -373,6 +375,7 @@ | |
2066 | "TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))" | |
2067 | "vmovdqu\t{%1, %0|%0, %1}" | |
2068 | [(set_attr "type" "ssemov") | |
2069 | + (set_attr "movu" "1") | |
2070 | (set_attr "prefix" "vex") | |
2071 | (set_attr "mode" "<avxvecmode>")]) | |
2072 | ||
2073 | @@ -383,6 +386,7 @@ | |
2074 | "TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))" | |
2075 | "movdqu\t{%1, %0|%0, %1}" | |
2076 | [(set_attr "type" "ssemov") | |
2077 | + (set_attr "movu" "1") | |
2078 | (set_attr "prefix_data16" "1") | |
2079 | (set_attr "mode" "TI")]) | |
2080 | ||
2081 | @@ -424,7 +428,7 @@ | |
2082 | UNSPEC_MOVNT))] | |
2083 | "TARGET_SSE2" | |
2084 | "movntdq\t{%1, %0|%0, %1}" | |
2085 | - [(set_attr "type" "ssecvt") | |
2086 | + [(set_attr "type" "ssemov") | |
2087 | (set_attr "prefix_data16" "1") | |
2088 | (set_attr "mode" "TI")]) | |
2089 | ||
2090 | @@ -434,7 +438,7 @@ | |
2091 | UNSPEC_MOVNT))] | |
2092 | "TARGET_SSE2" | |
2093 | "movnti\t{%1, %0|%0, %1}" | |
2094 | - [(set_attr "type" "ssecvt") | |
2095 | + [(set_attr "type" "ssemov") | |
2096 | (set_attr "mode" "V2DF")]) | |
2097 | ||
2098 | (define_insn "avx_lddqu<avxmodesuffix>" | |
2099 | @@ -445,6 +449,7 @@ | |
2100 | "TARGET_AVX" | |
2101 | "vlddqu\t{%1, %0|%0, %1}" | |
2102 | [(set_attr "type" "ssecvt") | |
2103 | + (set_attr "movu" "1") | |
2104 | (set_attr "prefix" "vex") | |
2105 | (set_attr "mode" "<avxvecmode>")]) | |
2106 | ||
2107 | @@ -454,7 +459,8 @@ | |
2108 | UNSPEC_LDDQU))] | |
2109 | "TARGET_SSE3" | |
2110 | "lddqu\t{%1, %0|%0, %1}" | |
2111 | - [(set_attr "type" "ssecvt") | |
2112 | + [(set_attr "type" "ssemov") | |
2113 | + (set_attr "movu" "1") | |
2114 | (set_attr "prefix_rep" "1") | |
2115 | (set_attr "mode" "TI")]) | |
2116 | ||
2117 | @@ -761,6 +767,7 @@ | |
2118 | "TARGET_SSE" | |
2119 | "%vrcpps\t{%1, %0|%0, %1}" | |
2120 | [(set_attr "type" "sse") | |
2121 | + (set_attr "atom_sse_attr" "rcp") | |
2122 | (set_attr "prefix" "maybe_vex") | |
2123 | (set_attr "mode" "V4SF")]) | |
2124 | ||
2125 | @@ -787,6 +794,7 @@ | |
2126 | "TARGET_SSE" | |
2127 | "rcpss\t{%1, %0|%0, %1}" | |
2128 | [(set_attr "type" "sse") | |
2129 | + (set_attr "atom_sse_attr" "rcp") | |
2130 | (set_attr "mode" "SF")]) | |
2131 | ||
2132 | (define_expand "sqrtv8sf2" | |
2133 | @@ -832,6 +840,7 @@ | |
2134 | "TARGET_SSE" | |
2135 | "%vsqrtps\t{%1, %0|%0, %1}" | |
2136 | [(set_attr "type" "sse") | |
2137 | + (set_attr "atom_sse_attr" "sqrt") | |
2138 | (set_attr "prefix" "maybe_vex") | |
2139 | (set_attr "mode" "V4SF")]) | |
2140 | ||
2141 | @@ -876,6 +885,7 @@ | |
2142 | "SSE_VEC_FLOAT_MODE_P (<MODE>mode)" | |
2143 | "sqrts<ssemodesuffixf2c>\t{%1, %0|%0, %1}" | |
2144 | [(set_attr "type" "sse") | |
2145 | + (set_attr "atom_sse_attr" "sqrt") | |
2146 | (set_attr "mode" "<ssescalarmode>")]) | |
2147 | ||
2148 | (define_expand "rsqrtv8sf2" | |
2149 | @@ -1039,7 +1049,7 @@ | |
2150 | (const_int 1)))] | |
2151 | "SSE_VEC_FLOAT_MODE_P (<MODE>mode)" | |
2152 | "<maxminfprefix>s<ssemodesuffixf2c>\t{%2, %0|%0, %2}" | |
2153 | - [(set_attr "type" "sse") | |
2154 | + [(set_attr "type" "sseadd") | |
2155 | (set_attr "mode" "<ssescalarmode>")]) | |
2156 | ||
2157 | ;; These versions of the min/max patterns implement exactly the operations | |
2158 | @@ -1175,6 +1185,7 @@ | |
2159 | "TARGET_SSE3" | |
2160 | "addsubpd\t{%2, %0|%0, %2}" | |
2161 | [(set_attr "type" "sseadd") | |
2162 | + (set_attr "atom_unit" "complex") | |
2163 | (set_attr "mode" "V2DF")]) | |
2164 | ||
2165 | (define_insn "avx_h<plusminus_insn>v4df3" | |
2166 | @@ -1298,6 +1309,7 @@ | |
2167 | "TARGET_SSE3" | |
2168 | "h<plusminus_mnemonic>ps\t{%2, %0|%0, %2}" | |
2169 | [(set_attr "type" "sseadd") | |
2170 | + (set_attr "atom_unit" "complex") | |
2171 | (set_attr "prefix_rep" "1") | |
2172 | (set_attr "mode" "V4SF")]) | |
2173 | ||
2174 | @@ -5066,6 +5078,7 @@ | |
2175 | "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)" | |
2176 | "pmaddwd\t{%2, %0|%0, %2}" | |
2177 | [(set_attr "type" "sseiadd") | |
2178 | + (set_attr "atom_unit" "simul") | |
2179 | (set_attr "prefix_data16" "1") | |
2180 | (set_attr "mode" "TI")]) | |
2181 | ||
2182 | @@ -7025,6 +7038,7 @@ | |
2183 | movq\t{%H1, %0|%0, %H1} | |
2184 | mov{q}\t{%H1, %0|%0, %H1}" | |
2185 | [(set_attr "type" "ssemov,sseishft,ssemov,imov") | |
2186 | + (set_attr "atom_unit" "*,sishuf,*,*") | |
2187 | (set_attr "memory" "*,none,*,*") | |
2188 | (set_attr "mode" "V2SF,TI,TI,DI")]) | |
2189 | ||
2190 | @@ -7057,6 +7071,7 @@ | |
2191 | psrldq\t{$8, %0|%0, 8} | |
2192 | movq\t{%H1, %0|%0, %H1}" | |
2193 | [(set_attr "type" "ssemov,sseishft,ssemov") | |
2194 | + (set_attr "atom_unit" "*,sishuf,*") | |
2195 | (set_attr "memory" "*,none,*") | |
2196 | (set_attr "mode" "V2SF,TI,TI")]) | |
2197 | ||
2198 | @@ -7614,6 +7629,7 @@ | |
2199 | "TARGET_SSE2" | |
2200 | "psadbw\t{%2, %0|%0, %2}" | |
2201 | [(set_attr "type" "sseiadd") | |
2202 | + (set_attr "atom_unit" "simul") | |
2203 | (set_attr "prefix_data16" "1") | |
2204 | (set_attr "mode" "TI")]) | |
2205 | ||
2206 | @@ -7635,7 +7651,7 @@ | |
2207 | UNSPEC_MOVMSK))] | |
2208 | "SSE_VEC_FLOAT_MODE_P (<MODE>mode)" | |
2209 | "%vmovmskp<ssemodesuffixf2c>\t{%1, %0|%0, %1}" | |
2210 | - [(set_attr "type" "ssecvt") | |
2211 | + [(set_attr "type" "ssemov") | |
2212 | (set_attr "prefix" "maybe_vex") | |
2213 | (set_attr "mode" "<MODE>")]) | |
2214 | ||
2215 | @@ -7645,7 +7661,7 @@ | |
2216 | UNSPEC_MOVMSK))] | |
2217 | "TARGET_SSE2" | |
2218 | "%vpmovmskb\t{%1, %0|%0, %1}" | |
2219 | - [(set_attr "type" "ssecvt") | |
2220 | + [(set_attr "type" "ssemov") | |
2221 | (set_attr "prefix_data16" "1") | |
2222 | (set_attr "prefix" "maybe_vex") | |
2223 | (set_attr "mode" "SI")]) | |
2224 | @@ -7668,7 +7684,7 @@ | |
2225 | "TARGET_SSE2 && !TARGET_64BIT" | |
2226 | ;; @@@ check ordering of operands in intel/nonintel syntax | |
2227 | "%vmaskmovdqu\t{%2, %1|%1, %2}" | |
2228 | - [(set_attr "type" "ssecvt") | |
2229 | + [(set_attr "type" "ssemov") | |
2230 | (set_attr "prefix_data16" "1") | |
2231 | (set_attr "prefix" "maybe_vex") | |
2232 | (set_attr "mode" "TI")]) | |
2233 | @@ -7682,7 +7698,7 @@ | |
2234 | "TARGET_SSE2 && TARGET_64BIT" | |
2235 | ;; @@@ check ordering of operands in intel/nonintel syntax | |
2236 | "%vmaskmovdqu\t{%2, %1|%1, %2}" | |
2237 | - [(set_attr "type" "ssecvt") | |
2238 | + [(set_attr "type" "ssemov") | |
2239 | (set_attr "prefix_data16" "1") | |
2240 | (set_attr "prefix" "maybe_vex") | |
2241 | (set_attr "mode" "TI")]) | |
2242 | @@ -7693,6 +7709,7 @@ | |
2243 | "TARGET_SSE" | |
2244 | "%vldmxcsr\t%0" | |
2245 | [(set_attr "type" "sse") | |
2246 | + (set_attr "atom_sse_attr" "mxcsr") | |
2247 | (set_attr "prefix" "maybe_vex") | |
2248 | (set_attr "memory" "load")]) | |
2249 | ||
2250 | @@ -7702,6 +7719,7 @@ | |
2251 | "TARGET_SSE" | |
2252 | "%vstmxcsr\t%0" | |
2253 | [(set_attr "type" "sse") | |
2254 | + (set_attr "atom_sse_attr" "mxcsr") | |
2255 | (set_attr "prefix" "maybe_vex") | |
2256 | (set_attr "memory" "store")]) | |
2257 | ||
2258 | @@ -7720,6 +7738,7 @@ | |
2259 | "TARGET_SSE || TARGET_3DNOW_A" | |
2260 | "sfence" | |
2261 | [(set_attr "type" "sse") | |
2262 | + (set_attr "atom_sse_attr" "fence") | |
2263 | (set_attr "memory" "unknown")]) | |
2264 | ||
2265 | (define_insn "sse2_clflush" | |
2266 | @@ -7728,6 +7747,7 @@ | |
2267 | "TARGET_SSE2" | |
2268 | "clflush\t%a0" | |
2269 | [(set_attr "type" "sse") | |
2270 | + (set_attr "atom_sse_attr" "fence") | |
2271 | (set_attr "memory" "unknown")]) | |
2272 | ||
2273 | (define_expand "sse2_mfence" | |
2274 | @@ -7745,6 +7765,7 @@ | |
2275 | "TARGET_64BIT || TARGET_SSE2" | |
2276 | "mfence" | |
2277 | [(set_attr "type" "sse") | |
2278 | + (set_attr "atom_sse_attr" "fence") | |
2279 | (set_attr "memory" "unknown")]) | |
2280 | ||
2281 | (define_expand "sse2_lfence" | |
2282 | @@ -7762,6 +7783,7 @@ | |
2283 | "TARGET_SSE2" | |
2284 | "lfence" | |
2285 | [(set_attr "type" "sse") | |
2286 | + (set_attr "atom_sse_attr" "lfence") | |
2287 | (set_attr "memory" "unknown")]) | |
2288 | ||
2289 | (define_insn "sse3_mwait" | |
2290 | @@ -7885,6 +7907,7 @@ | |
2291 | "TARGET_SSSE3" | |
2292 | "phaddw\t{%2, %0|%0, %2}" | |
2293 | [(set_attr "type" "sseiadd") | |
2294 | + (set_attr "atom_unit" "complex") | |
2295 | (set_attr "prefix_data16" "1") | |
2296 | (set_attr "prefix_extra" "1") | |
2297 | (set_attr "mode" "TI")]) | |
2298 | @@ -7913,6 +7936,7 @@ | |
2299 | "TARGET_SSSE3" | |
2300 | "phaddw\t{%2, %0|%0, %2}" | |
2301 | [(set_attr "type" "sseiadd") | |
2302 | + (set_attr "atom_unit" "complex") | |
2303 | (set_attr "prefix_extra" "1") | |
2304 | (set_attr "mode" "DI")]) | |
2305 | ||
2306 | @@ -7967,6 +7991,7 @@ | |
2307 | "TARGET_SSSE3" | |
2308 | "phaddd\t{%2, %0|%0, %2}" | |
2309 | [(set_attr "type" "sseiadd") | |
2310 | + (set_attr "atom_unit" "complex") | |
2311 | (set_attr "prefix_data16" "1") | |
2312 | (set_attr "prefix_extra" "1") | |
2313 | (set_attr "mode" "TI")]) | |
2314 | @@ -7987,6 +8012,7 @@ | |
2315 | "TARGET_SSSE3" | |
2316 | "phaddd\t{%2, %0|%0, %2}" | |
2317 | [(set_attr "type" "sseiadd") | |
2318 | + (set_attr "atom_unit" "complex") | |
2319 | (set_attr "prefix_extra" "1") | |
2320 | (set_attr "mode" "DI")]) | |
2321 | ||
2322 | @@ -8073,6 +8099,7 @@ | |
2323 | "TARGET_SSSE3" | |
2324 | "phaddsw\t{%2, %0|%0, %2}" | |
2325 | [(set_attr "type" "sseiadd") | |
2326 | + (set_attr "atom_unit" "complex") | |
2327 | (set_attr "prefix_data16" "1") | |
2328 | (set_attr "prefix_extra" "1") | |
2329 | (set_attr "mode" "TI")]) | |
2330 | @@ -8101,6 +8128,7 @@ | |
2331 | "TARGET_SSSE3" | |
2332 | "phaddsw\t{%2, %0|%0, %2}" | |
2333 | [(set_attr "type" "sseiadd") | |
2334 | + (set_attr "atom_unit" "complex") | |
2335 | (set_attr "prefix_extra" "1") | |
2336 | (set_attr "mode" "DI")]) | |
2337 | ||
2338 | @@ -8187,6 +8215,7 @@ | |
2339 | "TARGET_SSSE3" | |
2340 | "phsubw\t{%2, %0|%0, %2}" | |
2341 | [(set_attr "type" "sseiadd") | |
2342 | + (set_attr "atom_unit" "complex") | |
2343 | (set_attr "prefix_data16" "1") | |
2344 | (set_attr "prefix_extra" "1") | |
2345 | (set_attr "mode" "TI")]) | |
2346 | @@ -8215,6 +8244,7 @@ | |
2347 | "TARGET_SSSE3" | |
2348 | "phsubw\t{%2, %0|%0, %2}" | |
2349 | [(set_attr "type" "sseiadd") | |
2350 | + (set_attr "atom_unit" "complex") | |
2351 | (set_attr "prefix_extra" "1") | |
2352 | (set_attr "mode" "DI")]) | |
2353 | ||
2354 | @@ -8269,6 +8299,7 @@ | |
2355 | "TARGET_SSSE3" | |
2356 | "phsubd\t{%2, %0|%0, %2}" | |
2357 | [(set_attr "type" "sseiadd") | |
2358 | + (set_attr "atom_unit" "complex") | |
2359 | (set_attr "prefix_data16" "1") | |
2360 | (set_attr "prefix_extra" "1") | |
2361 | (set_attr "mode" "TI")]) | |
2362 | @@ -8289,6 +8320,7 @@ | |
2363 | "TARGET_SSSE3" | |
2364 | "phsubd\t{%2, %0|%0, %2}" | |
2365 | [(set_attr "type" "sseiadd") | |
2366 | + (set_attr "atom_unit" "complex") | |
2367 | (set_attr "prefix_extra" "1") | |
2368 | (set_attr "mode" "DI")]) | |
2369 | ||
2370 | @@ -8375,6 +8407,7 @@ | |
2371 | "TARGET_SSSE3" | |
2372 | "phsubsw\t{%2, %0|%0, %2}" | |
2373 | [(set_attr "type" "sseiadd") | |
2374 | + (set_attr "atom_unit" "complex") | |
2375 | (set_attr "prefix_data16" "1") | |
2376 | (set_attr "prefix_extra" "1") | |
2377 | (set_attr "mode" "TI")]) | |
2378 | @@ -8403,6 +8436,7 @@ | |
2379 | "TARGET_SSSE3" | |
2380 | "phsubsw\t{%2, %0|%0, %2}" | |
2381 | [(set_attr "type" "sseiadd") | |
2382 | + (set_attr "atom_unit" "complex") | |
2383 | (set_attr "prefix_extra" "1") | |
2384 | (set_attr "mode" "DI")]) | |
2385 | ||
2386 | @@ -8509,6 +8543,7 @@ | |
2387 | "TARGET_SSSE3" | |
2388 | "pmaddubsw\t{%2, %0|%0, %2}" | |
2389 | [(set_attr "type" "sseiadd") | |
2390 | + (set_attr "atom_unit" "simul") | |
2391 | (set_attr "prefix_data16" "1") | |
2392 | (set_attr "prefix_extra" "1") | |
2393 | (set_attr "mode" "TI")]) | |
2394 | @@ -8547,6 +8582,7 @@ | |
2395 | "TARGET_SSSE3" | |
2396 | "pmaddubsw\t{%2, %0|%0, %2}" | |
2397 | [(set_attr "type" "sseiadd") | |
2398 | + (set_attr "atom_unit" "simul") | |
2399 | (set_attr "prefix_extra" "1") | |
2400 | (set_attr "mode" "DI")]) | |
2401 | ||
2402 | @@ -8754,6 +8790,7 @@ | |
2403 | return "palignr\t{%3, %2, %0|%0, %2, %3}"; | |
2404 | } | |
2405 | [(set_attr "type" "sseishft") | |
2406 | + (set_attr "atom_unit" "sishuf") | |
2407 | (set_attr "prefix_data16" "1") | |
2408 | (set_attr "prefix_extra" "1") | |
2409 | (set_attr "mode" "TI")]) | |
2410 | @@ -8770,6 +8807,7 @@ | |
2411 | return "palignr\t{%3, %2, %0|%0, %2, %3}"; | |
2412 | } | |
2413 | [(set_attr "type" "sseishft") | |
2414 | + (set_attr "atom_unit" "sishuf") | |
2415 | (set_attr "prefix_extra" "1") | |
2416 | (set_attr "mode" "DI")]) | |
2417 | ||
2418 | @@ -8956,7 +8994,7 @@ | |
2419 | UNSPEC_MOVNTDQA))] | |
2420 | "TARGET_SSE4_1" | |
2421 | "%vmovntdqa\t{%1, %0|%0, %1}" | |
2422 | - [(set_attr "type" "ssecvt") | |
2423 | + [(set_attr "type" "ssemov") | |
2424 | (set_attr "prefix_extra" "1") | |
2425 | (set_attr "prefix" "maybe_vex") | |
2426 | (set_attr "mode" "TI")]) | |
2427 | Index: gcc/config/i386/i386.opt | |
2428 | =================================================================== | |
2429 | --- gcc/config/i386/i386.opt (.../tags/gcc_4_4_0_release) (revision 146537) | |
2430 | +++ gcc/config/i386/i386.opt (.../branches/ix86/gcc-4_4-branch) (revision 146537) | |
2431 | @@ -228,6 +228,10 @@ | |
2432 | Target RejectNegative Joined Var(ix86_tune_string) | |
2433 | Schedule code for given CPU | |
2434 | ||
2435 | +mabi= | |
2436 | +Target RejectNegative Joined Var(ix86_abi_string) | |
2437 | +Generate code that conforms to the given ABI | |
2438 | + | |
2439 | mveclibabi= | |
2440 | Target RejectNegative Joined Var(ix86_veclibabi_string) | |
2441 | Vector library ABI to use | |
2442 | Index: gcc/config/i386/i386-c.c | |
2443 | =================================================================== | |
2444 | --- gcc/config/i386/i386-c.c (.../tags/gcc_4_4_0_release) (revision 146537) | |
2445 | +++ gcc/config/i386/i386-c.c (.../branches/ix86/gcc-4_4-branch) (revision 146537) | |
2446 | @@ -119,6 +119,10 @@ | |
2447 | def_or_undef (parse_in, "__core2"); | |
2448 | def_or_undef (parse_in, "__core2__"); | |
2449 | break; | |
2450 | + case PROCESSOR_ATOM: | |
2451 | + def_or_undef (parse_in, "__atom"); | |
2452 | + def_or_undef (parse_in, "__atom__"); | |
2453 | + break; | |
2454 | /* use PROCESSOR_max to not set/unset the arch macro. */ | |
2455 | case PROCESSOR_max: | |
2456 | break; | |
2457 | @@ -187,6 +191,9 @@ | |
2458 | case PROCESSOR_CORE2: | |
2459 | def_or_undef (parse_in, "__tune_core2__"); | |
2460 | break; | |
2461 | + case PROCESSOR_ATOM: | |
2462 | + def_or_undef (parse_in, "__tune_atom__"); | |
2463 | + break; | |
2464 | case PROCESSOR_GENERIC32: | |
2465 | case PROCESSOR_GENERIC64: | |
2466 | break; | |
2467 | Index: gcc/config/i386/mingw32.h | |
2468 | =================================================================== | |
2469 | --- gcc/config/i386/mingw32.h (.../tags/gcc_4_4_0_release) (revision 146537) | |
2470 | +++ gcc/config/i386/mingw32.h (.../branches/ix86/gcc-4_4-branch) (revision 146537) | |
2471 | @@ -38,7 +38,7 @@ | |
2472 | builtin_define_std ("WINNT"); \ | |
2473 | builtin_define_with_int_value ("_INTEGRAL_MAX_BITS", \ | |
2474 | TYPE_PRECISION (intmax_type_node));\ | |
2475 | - if (TARGET_64BIT && DEFAULT_ABI == MS_ABI) \ | |
2476 | + if (TARGET_64BIT && ix86_abi == MS_ABI) \ | |
2477 | { \ | |
2478 | builtin_define ("__MINGW64__"); \ | |
2479 | builtin_define_std ("WIN64"); \ | |
2480 | Index: gcc/config/i386/i386-protos.h | |
2481 | =================================================================== | |
2482 | --- gcc/config/i386/i386-protos.h (.../tags/gcc_4_4_0_release) (revision 146537) | |
2483 | +++ gcc/config/i386/i386-protos.h (.../branches/ix86/gcc-4_4-branch) (revision 146537) | |
2484 | @@ -85,6 +85,9 @@ | |
2485 | extern void ix86_expand_binary_operator (enum rtx_code, | |
2486 | enum machine_mode, rtx[]); | |
2487 | extern int ix86_binary_operator_ok (enum rtx_code, enum machine_mode, rtx[]); | |
2488 | +extern bool ix86_lea_for_add_ok (enum rtx_code, rtx, rtx[]); | |
2489 | +extern bool ix86_dep_by_shift_count (const_rtx set_insn, const_rtx use_insn); | |
2490 | +extern bool ix86_agi_dependent (rtx set_insn, rtx use_insn); | |
2491 | extern void ix86_expand_unary_operator (enum rtx_code, enum machine_mode, | |
2492 | rtx[]); | |
2493 | extern rtx ix86_build_const_vector (enum machine_mode, bool, rtx); | |
2494 | @@ -139,9 +142,8 @@ | |
2495 | extern bool ix86_sol10_return_in_memory (const_tree,const_tree); | |
2496 | extern rtx ix86_force_to_memory (enum machine_mode, rtx); | |
2497 | extern void ix86_free_from_memory (enum machine_mode); | |
2498 | -extern int ix86_cfun_abi (void); | |
2499 | -extern int ix86_function_abi (const_tree); | |
2500 | -extern int ix86_function_type_abi (const_tree); | |
2501 | +extern enum calling_abi ix86_cfun_abi (void); | |
2502 | +extern enum calling_abi ix86_function_type_abi (const_tree); | |
2503 | extern void ix86_call_abi_override (const_tree); | |
2504 | extern tree ix86_fn_abi_va_list (tree); | |
2505 | extern tree ix86_canonical_va_list_type (tree); | |
2506 | Index: gcc/config/i386/i386.c | |
2507 | =================================================================== | |
2508 | --- gcc/config/i386/i386.c (.../tags/gcc_4_4_0_release) (revision 146537) | |
2509 | +++ gcc/config/i386/i386.c (.../branches/ix86/gcc-4_4-branch) (revision 146537) | |
2510 | @@ -1036,6 +1036,79 @@ | |
2511 | 1, /* cond_not_taken_branch_cost. */ | |
38a49943 PS |
2512 | }; |
2513 | ||
bed1487f PS |
2514 | +static const |
2515 | +struct processor_costs atom_cost = { | |
2516 | + COSTS_N_INSNS (1), /* cost of an add instruction */ | |
2517 | + COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */ | |
2518 | + COSTS_N_INSNS (1), /* variable shift costs */ | |
2519 | + COSTS_N_INSNS (1), /* constant shift costs */ | |
2520 | + {COSTS_N_INSNS (3), /* cost of starting multiply for QI */ | |
2521 | + COSTS_N_INSNS (4), /* HI */ | |
2522 | + COSTS_N_INSNS (3), /* SI */ | |
2523 | + COSTS_N_INSNS (4), /* DI */ | |
2524 | + COSTS_N_INSNS (2)}, /* other */ | |
2525 | + 0, /* cost of multiply per each bit set */ | |
2526 | + {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */ | |
2527 | + COSTS_N_INSNS (26), /* HI */ | |
2528 | + COSTS_N_INSNS (42), /* SI */ | |
2529 | + COSTS_N_INSNS (74), /* DI */ | |
2530 | + COSTS_N_INSNS (74)}, /* other */ | |
2531 | + COSTS_N_INSNS (1), /* cost of movsx */ | |
2532 | + COSTS_N_INSNS (1), /* cost of movzx */ | |
2533 | + 8, /* "large" insn */ | |
2534 | + 17, /* MOVE_RATIO */ | |
2535 | + 2, /* cost for loading QImode using movzbl */ | |
2536 | + {4, 4, 4}, /* cost of loading integer registers | |
2537 | + in QImode, HImode and SImode. | |
2538 | + Relative to reg-reg move (2). */ | |
2539 | + {4, 4, 4}, /* cost of storing integer registers */ | |
2540 | + 4, /* cost of reg,reg fld/fst */ | |
2541 | + {12, 12, 12}, /* cost of loading fp registers | |
2542 | + in SFmode, DFmode and XFmode */ | |
2543 | + {6, 6, 8}, /* cost of storing fp registers | |
2544 | + in SFmode, DFmode and XFmode */ | |
2545 | + 2, /* cost of moving MMX register */ | |
2546 | + {8, 8}, /* cost of loading MMX registers | |
2547 | + in SImode and DImode */ | |
2548 | + {8, 8}, /* cost of storing MMX registers | |
2549 | + in SImode and DImode */ | |
2550 | + 2, /* cost of moving SSE register */ | |
2551 | + {8, 8, 8}, /* cost of loading SSE registers | |
2552 | + in SImode, DImode and TImode */ | |
2553 | + {8, 8, 8}, /* cost of storing SSE registers | |
2554 | + in SImode, DImode and TImode */ | |
2555 | + 5, /* MMX or SSE register to integer */ | |
2556 | + 32, /* size of l1 cache. */ | |
2557 | + 256, /* size of l2 cache. */ | |
2558 | + 64, /* size of prefetch block */ | |
2559 | + 6, /* number of parallel prefetches */ | |
2560 | + 3, /* Branch cost */ | |
2561 | + COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */ | |
2562 | + COSTS_N_INSNS (8), /* cost of FMUL instruction. */ | |
2563 | + COSTS_N_INSNS (20), /* cost of FDIV instruction. */ | |
2564 | + COSTS_N_INSNS (8), /* cost of FABS instruction. */ | |
2565 | + COSTS_N_INSNS (8), /* cost of FCHS instruction. */ | |
2566 | + COSTS_N_INSNS (40), /* cost of FSQRT instruction. */ | |
2567 | + {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}}, | |
2568 | + {libcall, {{32, loop}, {64, rep_prefix_4_byte}, | |
2569 | + {8192, rep_prefix_8_byte}, {-1, libcall}}}}, | |
2570 | + {{libcall, {{8, loop}, {15, unrolled_loop}, | |
2571 | + {2048, rep_prefix_4_byte}, {-1, libcall}}}, | |
2572 | + {libcall, {{24, loop}, {32, unrolled_loop}, | |
2573 | + {8192, rep_prefix_8_byte}, {-1, libcall}}}}, | |
2574 | + 1, /* scalar_stmt_cost. */ | |
2575 | + 1, /* scalar load_cost. */ | |
2576 | + 1, /* scalar_store_cost. */ | |
2577 | + 1, /* vec_stmt_cost. */ | |
2578 | + 1, /* vec_to_scalar_cost. */ | |
2579 | + 1, /* scalar_to_vec_cost. */ | |
2580 | + 1, /* vec_align_load_cost. */ | |
2581 | + 2, /* vec_unalign_load_cost. */ | |
2582 | + 1, /* vec_store_cost. */ | |
2583 | + 3, /* cond_taken_branch_cost. */ | |
2584 | + 1, /* cond_not_taken_branch_cost. */ | |
2585 | +}; | |
2586 | + | |
2587 | /* Generic64 should produce code tuned for Nocona and K8. */ | |
2588 | static const | |
2589 | struct processor_costs generic64_cost = { | |
2590 | @@ -1194,6 +1267,7 @@ | |
2591 | #define m_PENT4 (1<<PROCESSOR_PENTIUM4) | |
2592 | #define m_NOCONA (1<<PROCESSOR_NOCONA) | |
2593 | #define m_CORE2 (1<<PROCESSOR_CORE2) | |
2594 | +#define m_ATOM (1<<PROCESSOR_ATOM) | |
38a49943 | 2595 | |
bed1487f PS |
2596 | #define m_GEODE (1<<PROCESSOR_GEODE) |
2597 | #define m_K6 (1<<PROCESSOR_K6) | |
2598 | @@ -1231,10 +1305,11 @@ | |
2599 | m_486 | m_PENT, | |
2600 | ||
2601 | /* X86_TUNE_UNROLL_STRLEN */ | |
2602 | - m_486 | m_PENT | m_PPRO | m_AMD_MULTIPLE | m_K6 | m_CORE2 | m_GENERIC, | |
2603 | + m_486 | m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_K6 | |
2604 | + | m_CORE2 | m_GENERIC, | |
2605 | ||
2606 | /* X86_TUNE_DEEP_BRANCH_PREDICTION */ | |
2607 | - m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC, | |
2608 | + m_ATOM | m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC, | |
2609 | ||
2610 | /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based | |
2611 | on simulation result. But after P4 was made, no performance benefit | |
2612 | @@ -1246,12 +1321,12 @@ | |
2613 | ~m_386, | |
2614 | ||
2615 | /* X86_TUNE_USE_SAHF */ | |
2616 | - m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4 | |
2617 | + m_ATOM | m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4 | |
2618 | | m_NOCONA | m_CORE2 | m_GENERIC, | |
2619 | ||
2620 | /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid | |
2621 | partial dependencies. */ | |
2622 | - m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA | |
2623 | + m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_PENT4 | m_NOCONA | |
2624 | | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */, | |
2625 | ||
2626 | /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial | |
2627 | @@ -1271,13 +1346,13 @@ | |
2628 | m_386 | m_486 | m_K6_GEODE, | |
2629 | ||
2630 | /* X86_TUNE_USE_SIMODE_FIOP */ | |
2631 | - ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_CORE2 | m_GENERIC), | |
2632 | + ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_ATOM | m_CORE2 | m_GENERIC), | |
2633 | ||
2634 | /* X86_TUNE_USE_MOV0 */ | |
2635 | m_K6, | |
2636 | ||
2637 | /* X86_TUNE_USE_CLTD */ | |
2638 | - ~(m_PENT | m_K6 | m_CORE2 | m_GENERIC), | |
2639 | + ~(m_PENT | m_ATOM | m_K6 | m_CORE2 | m_GENERIC), | |
2640 | ||
2641 | /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */ | |
2642 | m_PENT4, | |
2643 | @@ -1292,8 +1367,8 @@ | |
2644 | ~(m_PENT | m_PPRO), | |
2645 | ||
2646 | /* X86_TUNE_PROMOTE_QIMODE */ | |
2647 | - m_K6_GEODE | m_PENT | m_386 | m_486 | m_AMD_MULTIPLE | m_CORE2 | |
2648 | - | m_GENERIC /* | m_PENT4 ? */, | |
2649 | + m_K6_GEODE | m_PENT | m_ATOM | m_386 | m_486 | m_AMD_MULTIPLE | |
2650 | + | m_CORE2 | m_GENERIC /* | m_PENT4 ? */, | |
2651 | ||
2652 | /* X86_TUNE_FAST_PREFIX */ | |
2653 | ~(m_PENT | m_486 | m_386), | |
2654 | @@ -1317,26 +1392,28 @@ | |
2655 | m_PPRO, | |
2656 | ||
2657 | /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */ | |
2658 | - m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC, | |
2659 | + m_ATOM | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA | |
2660 | + | m_CORE2 | m_GENERIC, | |
2661 | ||
2662 | /* X86_TUNE_ADD_ESP_8 */ | |
2663 | - m_AMD_MULTIPLE | m_PPRO | m_K6_GEODE | m_386 | |
2664 | + m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_K6_GEODE | m_386 | |
2665 | | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC, | |
2666 | ||
2667 | /* X86_TUNE_SUB_ESP_4 */ | |
2668 | - m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC, | |
2669 | + m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | |
2670 | + | m_GENERIC, | |
2671 | ||
2672 | /* X86_TUNE_SUB_ESP_8 */ | |
2673 | - m_AMD_MULTIPLE | m_PPRO | m_386 | m_486 | |
2674 | + m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_386 | m_486 | |
2675 | | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC, | |
2676 | ||
2677 | /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred | |
2678 | for DFmode copies */ | |
2679 | - ~(m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | |
2680 | + ~(m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | |
2681 | | m_GENERIC | m_GEODE), | |
2682 | ||
2683 | /* X86_TUNE_PARTIAL_REG_DEPENDENCY */ | |
2684 | - m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC, | |
2685 | + m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC, | |
2686 | ||
2687 | /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a | |
2688 | conflict here in between PPro/Pentium4 based chips that thread 128bit | |
2689 | @@ -1347,7 +1424,8 @@ | |
2690 | shows that disabling this option on P4 brings over 20% SPECfp regression, | |
2691 | while enabling it on K8 brings roughly 2.4% regression that can be partly | |
2692 | masked by careful scheduling of moves. */ | |
2693 | - m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC | m_AMDFAM10, | |
2694 | + m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC | |
2695 | + | m_AMDFAM10, | |
2696 | ||
2697 | /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */ | |
2698 | m_AMDFAM10, | |
2699 | @@ -1365,13 +1443,13 @@ | |
2700 | m_PPRO | m_PENT4 | m_NOCONA, | |
2701 | ||
2702 | /* X86_TUNE_MEMORY_MISMATCH_STALL */ | |
2703 | - m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC, | |
2704 | + m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC, | |
2705 | ||
2706 | /* X86_TUNE_PROLOGUE_USING_MOVE */ | |
2707 | - m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC, | |
2708 | + m_ATHLON_K8 | m_ATOM | m_PPRO | m_CORE2 | m_GENERIC, | |
2709 | ||
2710 | /* X86_TUNE_EPILOGUE_USING_MOVE */ | |
2711 | - m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC, | |
2712 | + m_ATHLON_K8 | m_ATOM | m_PPRO | m_CORE2 | m_GENERIC, | |
2713 | ||
2714 | /* X86_TUNE_SHIFT1 */ | |
2715 | ~m_486, | |
2716 | @@ -1380,29 +1458,32 @@ | |
2717 | m_AMD_MULTIPLE, | |
2718 | ||
2719 | /* X86_TUNE_INTER_UNIT_MOVES */ | |
2720 | - ~(m_AMD_MULTIPLE | m_GENERIC), | |
2721 | + ~(m_AMD_MULTIPLE | m_ATOM | m_GENERIC), | |
2722 | ||
2723 | /* X86_TUNE_INTER_UNIT_CONVERSIONS */ | |
2724 | ~(m_AMDFAM10), | |
2725 | ||
2726 | /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more | |
2727 | than 4 branch instructions in the 16 byte window. */ | |
2728 | - m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC, | |
2729 | + m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | |
2730 | + | m_GENERIC, | |
2731 | ||
2732 | /* X86_TUNE_SCHEDULE */ | |
2733 | - m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_CORE2 | m_GENERIC, | |
2734 | + m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_ATOM | m_CORE2 | |
2735 | + | m_GENERIC, | |
2736 | ||
2737 | /* X86_TUNE_USE_BT */ | |
2738 | - m_AMD_MULTIPLE | m_CORE2 | m_GENERIC, | |
2739 | + m_AMD_MULTIPLE | m_ATOM | m_CORE2 | m_GENERIC, | |
2740 | ||
2741 | /* X86_TUNE_USE_INCDEC */ | |
2742 | - ~(m_PENT4 | m_NOCONA | m_GENERIC), | |
2743 | + ~(m_PENT4 | m_NOCONA | m_GENERIC | m_ATOM), | |
2744 | ||
2745 | /* X86_TUNE_PAD_RETURNS */ | |
2746 | m_AMD_MULTIPLE | m_CORE2 | m_GENERIC, | |
2747 | ||
2748 | /* X86_TUNE_EXT_80387_CONSTANTS */ | |
2749 | - m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC, | |
2750 | + m_K6_GEODE | m_ATHLON_K8 | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | |
2751 | + | m_CORE2 | m_GENERIC, | |
2752 | ||
2753 | /* X86_TUNE_SHORTEN_X87_SSE */ | |
2754 | ~m_K8, | |
2755 | @@ -1447,6 +1528,10 @@ | |
2756 | with a subsequent conditional jump instruction into a single | |
2757 | compare-and-branch uop. */ | |
2758 | m_CORE2, | |
2759 | + | |
2760 | + /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag | |
2761 | + will impact LEA instruction selection. */ | |
2762 | + m_ATOM, | |
2763 | }; | |
2764 | ||
2765 | /* Feature tests against the various architecture variations. */ | |
2766 | @@ -1472,10 +1557,11 @@ | |
2767 | }; | |
2768 | ||
2769 | static const unsigned int x86_accumulate_outgoing_args | |
2770 | - = m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC; | |
2771 | + = m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | |
2772 | + | m_GENERIC; | |
2773 | ||
2774 | static const unsigned int x86_arch_always_fancy_math_387 | |
2775 | - = m_PENT | m_PPRO | m_AMD_MULTIPLE | m_PENT4 | |
2776 | + = m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_PENT4 | |
2777 | | m_NOCONA | m_CORE2 | m_GENERIC; | |
2778 | ||
2779 | static enum stringop_alg stringop_alg = no_stringop; | |
2780 | @@ -1743,6 +1829,9 @@ | |
2781 | /* Alignment for incoming stack boundary in bits. */ | |
2782 | unsigned int ix86_incoming_stack_boundary; | |
2783 | ||
2784 | +/* The abi used by target. */ | |
2785 | +enum calling_abi ix86_abi; | |
38a49943 | 2786 | + |
bed1487f PS |
2787 | /* Values 1-5: see jump.c */ |
2788 | int ix86_branch_cost; | |
2789 | ||
2790 | @@ -1819,6 +1908,8 @@ | |
2791 | static bool ix86_can_inline_p (tree, tree); | |
2792 | static void ix86_set_current_function (tree); | |
2793 | ||
2794 | +static enum calling_abi ix86_function_abi (const_tree); | |
2795 | + | |
2796 | \f | |
2797 | /* The svr4 ABI for the i386 says that records and unions are returned | |
2798 | in memory. */ | |
2799 | @@ -1953,7 +2044,8 @@ | |
2800 | {&core2_cost, 16, 10, 16, 10, 16}, | |
2801 | {&generic32_cost, 16, 7, 16, 7, 16}, | |
2802 | {&generic64_cost, 16, 10, 16, 10, 16}, | |
2803 | - {&amdfam10_cost, 32, 24, 32, 7, 32} | |
2804 | + {&amdfam10_cost, 32, 24, 32, 7, 32}, | |
2805 | + {&atom_cost, 16, 7, 16, 7, 16} | |
2806 | }; | |
2807 | ||
2808 | static const char *const cpu_names[TARGET_CPU_DEFAULT_max] = | |
2809 | @@ -1971,6 +2063,7 @@ | |
2810 | "prescott", | |
2811 | "nocona", | |
2812 | "core2", | |
2813 | + "atom", | |
2814 | "geode", | |
2815 | "k6", | |
2816 | "k6-2", | |
2817 | @@ -2529,6 +2622,9 @@ | |
2818 | {"core2", PROCESSOR_CORE2, CPU_CORE2, | |
2819 | PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | |
2820 | | PTA_SSSE3 | PTA_CX16}, | |
2821 | + {"atom", PROCESSOR_ATOM, CPU_ATOM, | |
2822 | + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | |
2823 | + | PTA_SSSE3 | PTA_CX16}, | |
2824 | {"geode", PROCESSOR_GEODE, CPU_GEODE, | |
2825 | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A |PTA_PREFETCH_SSE}, | |
2826 | {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX}, | |
2827 | @@ -2716,6 +2812,20 @@ | |
2828 | error ("bad value (%s) for %sarch=%s %s", | |
2829 | ix86_arch_string, prefix, suffix, sw); | |
2830 | ||
2831 | + /* Validate -mabi= value. */ | |
2832 | + if (ix86_abi_string) | |
38a49943 | 2833 | + { |
bed1487f PS |
2834 | + if (strcmp (ix86_abi_string, "sysv") == 0) |
2835 | + ix86_abi = SYSV_ABI; | |
2836 | + else if (strcmp (ix86_abi_string, "ms") == 0) | |
2837 | + ix86_abi = MS_ABI; | |
2838 | + else | |
2839 | + error ("unknown ABI (%s) for %sabi=%s %s", | |
2840 | + ix86_abi_string, prefix, suffix, sw); | |
38a49943 | 2841 | + } |
bed1487f PS |
2842 | + else |
2843 | + ix86_abi = DEFAULT_ABI; | |
38a49943 | 2844 | + |
bed1487f PS |
2845 | if (ix86_cmodel_string != 0) |
2846 | { | |
2847 | if (!strcmp (ix86_cmodel_string, "small")) | |
2848 | @@ -4515,14 +4625,14 @@ | |
2849 | default ABI. */ | |
2850 | ||
2851 | /* RAX is used as hidden argument to va_arg functions. */ | |
2852 | - if (DEFAULT_ABI == SYSV_ABI && regno == AX_REG) | |
2853 | + if (ix86_abi == SYSV_ABI && regno == AX_REG) | |
2854 | return true; | |
2855 | ||
2856 | - if (DEFAULT_ABI == MS_ABI) | |
2857 | + if (ix86_abi == MS_ABI) | |
2858 | parm_regs = x86_64_ms_abi_int_parameter_registers; | |
2859 | else | |
2860 | parm_regs = x86_64_int_parameter_registers; | |
2861 | - for (i = 0; i < (DEFAULT_ABI == MS_ABI ? X64_REGPARM_MAX | |
2862 | + for (i = 0; i < (ix86_abi == MS_ABI ? X64_REGPARM_MAX | |
2863 | : X86_64_REGPARM_MAX); i++) | |
2864 | if (regno == parm_regs[i]) | |
2865 | return true; | |
2866 | @@ -4550,7 +4660,7 @@ | |
2867 | int | |
2868 | ix86_reg_parm_stack_space (const_tree fndecl) | |
2869 | { | |
2870 | - int call_abi = SYSV_ABI; | |
2871 | + enum calling_abi call_abi = SYSV_ABI; | |
2872 | if (fndecl != NULL_TREE && TREE_CODE (fndecl) == FUNCTION_DECL) | |
2873 | call_abi = ix86_function_abi (fndecl); | |
2874 | else | |
2875 | @@ -4562,37 +4672,39 @@ | |
2876 | ||
2877 | /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the | |
2878 | call abi used. */ | |
2879 | -int | |
2880 | +enum calling_abi | |
2881 | ix86_function_type_abi (const_tree fntype) | |
2882 | { | |
2883 | if (TARGET_64BIT && fntype != NULL) | |
2884 | { | |
2885 | - int abi; | |
2886 | - if (DEFAULT_ABI == SYSV_ABI) | |
2887 | - abi = lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype)) ? MS_ABI : SYSV_ABI; | |
2888 | - else | |
2889 | - abi = lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype)) ? SYSV_ABI : MS_ABI; | |
2890 | - | |
2891 | + enum calling_abi abi = ix86_abi; | |
2892 | + if (abi == SYSV_ABI) | |
2893 | + { | |
2894 | + if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype))) | |
2895 | + abi = MS_ABI; | |
2896 | + } | |
2897 | + else if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype))) | |
2898 | + abi = SYSV_ABI; | |
2899 | return abi; | |
2900 | } | |
2901 | - return DEFAULT_ABI; | |
2902 | + return ix86_abi; | |
2903 | } | |
2904 | ||
2905 | -int | |
2906 | +static enum calling_abi | |
2907 | ix86_function_abi (const_tree fndecl) | |
2908 | { | |
2909 | if (! fndecl) | |
2910 | - return DEFAULT_ABI; | |
2911 | + return ix86_abi; | |
2912 | return ix86_function_type_abi (TREE_TYPE (fndecl)); | |
2913 | } | |
2914 | ||
2915 | /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the | |
2916 | call abi used. */ | |
2917 | -int | |
2918 | +enum calling_abi | |
2919 | ix86_cfun_abi (void) | |
2920 | { | |
2921 | if (! cfun || ! TARGET_64BIT) | |
2922 | - return DEFAULT_ABI; | |
2923 | + return ix86_abi; | |
2924 | return cfun->machine->call_abi; | |
2925 | } | |
2926 | ||
2927 | @@ -4606,7 +4718,7 @@ | |
2928 | ix86_call_abi_override (const_tree fndecl) | |
2929 | { | |
2930 | if (fndecl == NULL_TREE) | |
2931 | - cfun->machine->call_abi = DEFAULT_ABI; | |
2932 | + cfun->machine->call_abi = ix86_abi; | |
2933 | else | |
2934 | cfun->machine->call_abi = ix86_function_type_abi (TREE_TYPE (fndecl)); | |
38a49943 | 2935 | } |
bed1487f PS |
2936 | @@ -4646,8 +4758,8 @@ |
2937 | cum->nregs = ix86_regparm; | |
2938 | if (TARGET_64BIT) | |
2939 | { | |
2940 | - if (cum->call_abi != DEFAULT_ABI) | |
2941 | - cum->nregs = DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX | |
2942 | + if (cum->call_abi != ix86_abi) | |
2943 | + cum->nregs = ix86_abi != SYSV_ABI ? X86_64_REGPARM_MAX | |
2944 | : X64_REGPARM_MAX; | |
2945 | } | |
2946 | if (TARGET_SSE) | |
2947 | @@ -4655,8 +4767,8 @@ | |
2948 | cum->sse_nregs = SSE_REGPARM_MAX; | |
2949 | if (TARGET_64BIT) | |
2950 | { | |
2951 | - if (cum->call_abi != DEFAULT_ABI) | |
2952 | - cum->sse_nregs = DEFAULT_ABI != SYSV_ABI ? X86_64_SSE_REGPARM_MAX | |
2953 | + if (cum->call_abi != ix86_abi) | |
2954 | + cum->sse_nregs = ix86_abi != SYSV_ABI ? X86_64_SSE_REGPARM_MAX | |
2955 | : X64_SSE_REGPARM_MAX; | |
2956 | } | |
2957 | } | |
2958 | @@ -5619,7 +5731,7 @@ | |
2959 | if (type) | |
2960 | mode = type_natural_mode (type, NULL); | |
38a49943 | 2961 | |
bed1487f PS |
2962 | - if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI) |
2963 | + if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI) | |
2964 | function_arg_advance_ms_64 (cum, bytes, words); | |
2965 | else if (TARGET_64BIT) | |
2966 | function_arg_advance_64 (cum, mode, type, words, named); | |
2967 | @@ -5765,9 +5877,9 @@ | |
2968 | if (mode == VOIDmode) | |
2969 | return GEN_INT (cum->maybe_vaarg | |
2970 | ? (cum->sse_nregs < 0 | |
2971 | - ? (cum->call_abi == DEFAULT_ABI | |
2972 | + ? (cum->call_abi == ix86_abi | |
2973 | ? SSE_REGPARM_MAX | |
2974 | - : (DEFAULT_ABI != SYSV_ABI ? X86_64_SSE_REGPARM_MAX | |
2975 | + : (ix86_abi != SYSV_ABI ? X86_64_SSE_REGPARM_MAX | |
2976 | : X64_SSE_REGPARM_MAX)) | |
2977 | : cum->sse_regno) | |
2978 | : -1); | |
2979 | @@ -5861,7 +5973,7 @@ | |
2980 | if (type && TREE_CODE (type) == VECTOR_TYPE) | |
2981 | mode = type_natural_mode (type, cum); | |
2982 | ||
2983 | - if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI) | |
2984 | + if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI) | |
2985 | return function_arg_ms_64 (cum, mode, omode, named, bytes); | |
2986 | else if (TARGET_64BIT) | |
2987 | return function_arg_64 (cum, mode, omode, type, named); | |
2988 | @@ -5881,7 +5993,7 @@ | |
2989 | const_tree type, bool named ATTRIBUTE_UNUSED) | |
2990 | { | |
2991 | /* See Windows x64 Software Convention. */ | |
2992 | - if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI) | |
2993 | + if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI) | |
2994 | { | |
2995 | int msize = (int) GET_MODE_SIZE (mode); | |
2996 | if (type) | |
2997 | @@ -6021,7 +6133,7 @@ | |
2998 | /* TODO: The function should depend on current function ABI but | |
2999 | builtins.c would need updating then. Therefore we use the | |
3000 | default ABI. */ | |
3001 | - if (TARGET_64BIT && DEFAULT_ABI == MS_ABI) | |
3002 | + if (TARGET_64BIT && ix86_abi == MS_ABI) | |
3003 | return false; | |
3004 | return TARGET_FLOAT_RETURNS_IN_80387; | |
3005 | ||
3006 | @@ -6417,13 +6529,13 @@ | |
3007 | static tree | |
3008 | ix86_build_builtin_va_list (void) | |
3009 | { | |
3010 | - tree ret = ix86_build_builtin_va_list_abi (DEFAULT_ABI); | |
3011 | + tree ret = ix86_build_builtin_va_list_abi (ix86_abi); | |
3012 | ||
3013 | /* Initialize abi specific va_list builtin types. */ | |
3014 | if (TARGET_64BIT) | |
3015 | { | |
3016 | tree t; | |
3017 | - if (DEFAULT_ABI == MS_ABI) | |
3018 | + if (ix86_abi == MS_ABI) | |
3019 | { | |
3020 | t = ix86_build_builtin_va_list_abi (SYSV_ABI); | |
3021 | if (TREE_CODE (t) != RECORD_TYPE) | |
3022 | @@ -6437,7 +6549,7 @@ | |
3023 | t = build_variant_type_copy (t); | |
3024 | sysv_va_list_type_node = t; | |
3025 | } | |
3026 | - if (DEFAULT_ABI != MS_ABI) | |
3027 | + if (ix86_abi != MS_ABI) | |
3028 | { | |
3029 | t = ix86_build_builtin_va_list_abi (MS_ABI); | |
3030 | if (TREE_CODE (t) != RECORD_TYPE) | |
3031 | @@ -6470,8 +6582,8 @@ | |
3032 | int i; | |
3033 | int regparm = ix86_regparm; | |
3034 | ||
3035 | - if (cum->call_abi != DEFAULT_ABI) | |
3036 | - regparm = DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX : X64_REGPARM_MAX; | |
3037 | + if (cum->call_abi != ix86_abi) | |
3038 | + regparm = ix86_abi != SYSV_ABI ? X86_64_REGPARM_MAX : X64_REGPARM_MAX; | |
3039 | ||
3040 | /* GPR size of varargs save area. */ | |
3041 | if (cfun->va_list_gpr_size) | |
3042 | @@ -6624,7 +6736,7 @@ | |
3043 | return true; | |
3044 | canonic = ix86_canonical_va_list_type (type); | |
3045 | return (canonic == ms_va_list_type_node | |
3046 | - || (DEFAULT_ABI == MS_ABI && canonic == va_list_type_node)); | |
3047 | + || (ix86_abi == MS_ABI && canonic == va_list_type_node)); | |
3048 | } | |
3049 | ||
3050 | /* Implement va_start. */ | |
3051 | @@ -12903,6 +13015,316 @@ | |
3052 | emit_move_insn (operands[0], dst); | |
3053 | } | |
3054 | ||
3055 | +#define LEA_SEARCH_THRESHOLD 12 | |
3056 | + | |
3057 | +/* Search backward for non-agu definition of register number REGNO1 | |
3058 | + or register number REGNO2 in INSN's basic block until | |
3059 | + 1. Pass LEA_SEARCH_THRESHOLD instructions, or | |
3060 | + 2. Reach BB boundary, or | |
3061 | + 3. Reach agu definition. | |
3062 | + Returns the distance between the non-agu definition point and INSN. | |
3063 | + If no definition point, returns -1. */ | |
3064 | + | |
3065 | +static int | |
3066 | +distance_non_agu_define (unsigned int regno1, unsigned int regno2, | |
3067 | + rtx insn) | |
3068 | +{ | |
3069 | + basic_block bb = BLOCK_FOR_INSN (insn); | |
3070 | + int distance = 0; | |
3071 | + df_ref *def_rec; | |
3072 | + enum attr_type insn_type; | |
3073 | + | |
3074 | + if (insn != BB_HEAD (bb)) | |
3075 | + { | |
3076 | + rtx prev = PREV_INSN (insn); | |
3077 | + while (prev && distance < LEA_SEARCH_THRESHOLD) | |
3078 | + { | |
3079 | + if (INSN_P (prev)) | |
3080 | + { | |
3081 | + distance++; | |
3082 | + for (def_rec = DF_INSN_DEFS (prev); *def_rec; def_rec++) | |
3083 | + if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF | |
3084 | + && !DF_REF_IS_ARTIFICIAL (*def_rec) | |
3085 | + && (regno1 == DF_REF_REGNO (*def_rec) | |
3086 | + || regno2 == DF_REF_REGNO (*def_rec))) | |
3087 | + { | |
3088 | + insn_type = get_attr_type (prev); | |
3089 | + if (insn_type != TYPE_LEA) | |
3090 | + goto done; | |
3091 | + } | |
3092 | + } | |
3093 | + if (prev == BB_HEAD (bb)) | |
3094 | + break; | |
3095 | + prev = PREV_INSN (prev); | |
3096 | + } | |
3097 | + } | |
3098 | + | |
3099 | + if (distance < LEA_SEARCH_THRESHOLD) | |
3100 | + { | |
3101 | + edge e; | |
3102 | + edge_iterator ei; | |
3103 | + bool simple_loop = false; | |
3104 | + | |
3105 | + FOR_EACH_EDGE (e, ei, bb->preds) | |
3106 | + if (e->src == bb) | |
3107 | + { | |
3108 | + simple_loop = true; | |
3109 | + break; | |
3110 | + } | |
3111 | + | |
3112 | + if (simple_loop) | |
3113 | + { | |
3114 | + rtx prev = BB_END (bb); | |
3115 | + while (prev | |
3116 | + && prev != insn | |
3117 | + && distance < LEA_SEARCH_THRESHOLD) | |
3118 | + { | |
3119 | + if (INSN_P (prev)) | |
3120 | + { | |
3121 | + distance++; | |
3122 | + for (def_rec = DF_INSN_DEFS (prev); *def_rec; def_rec++) | |
3123 | + if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF | |
3124 | + && !DF_REF_IS_ARTIFICIAL (*def_rec) | |
3125 | + && (regno1 == DF_REF_REGNO (*def_rec) | |
3126 | + || regno2 == DF_REF_REGNO (*def_rec))) | |
3127 | + { | |
3128 | + insn_type = get_attr_type (prev); | |
3129 | + if (insn_type != TYPE_LEA) | |
3130 | + goto done; | |
3131 | + } | |
3132 | + } | |
3133 | + prev = PREV_INSN (prev); | |
3134 | + } | |
3135 | + } | |
3136 | + } | |
3137 | + | |
3138 | + distance = -1; | |
3139 | + | |
3140 | +done: | |
3141 | + /* get_attr_type may modify recog data. We want to make sure | |
3142 | + that recog data is valid for instruction INSN, on which | |
3143 | + distance_non_agu_define is called. INSN is unchanged here. */ | |
3144 | + extract_insn_cached (insn); | |
3145 | + return distance; | |
3146 | +} | |
38a49943 | 3147 | + |
bed1487f PS |
3148 | +/* Return the distance between INSN and the next insn that uses |
3149 | + register number REGNO0 in memory address. Return -1 if no such | |
3150 | + a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */ | |
3151 | + | |
3152 | +static int | |
3153 | +distance_agu_use (unsigned int regno0, rtx insn) | |
38a49943 | 3154 | +{ |
bed1487f PS |
3155 | + basic_block bb = BLOCK_FOR_INSN (insn); |
3156 | + int distance = 0; | |
3157 | + df_ref *def_rec; | |
3158 | + df_ref *use_rec; | |
3159 | + | |
3160 | + if (insn != BB_END (bb)) | |
38a49943 | 3161 | + { |
bed1487f PS |
3162 | + rtx next = NEXT_INSN (insn); |
3163 | + while (next && distance < LEA_SEARCH_THRESHOLD) | |
3164 | + { | |
3165 | + if (INSN_P (next)) | |
3166 | + { | |
3167 | + distance++; | |
3168 | + | |
3169 | + for (use_rec = DF_INSN_USES (next); *use_rec; use_rec++) | |
3170 | + if ((DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_LOAD | |
3171 | + || DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_STORE) | |
3172 | + && regno0 == DF_REF_REGNO (*use_rec)) | |
3173 | + { | |
3174 | + /* Return DISTANCE if OP0 is used in memory | |
3175 | + address in NEXT. */ | |
3176 | + return distance; | |
3177 | + } | |
3178 | + | |
3179 | + for (def_rec = DF_INSN_DEFS (next); *def_rec; def_rec++) | |
3180 | + if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF | |
3181 | + && !DF_REF_IS_ARTIFICIAL (*def_rec) | |
3182 | + && regno0 == DF_REF_REGNO (*def_rec)) | |
3183 | + { | |
3184 | + /* Return -1 if OP0 is set in NEXT. */ | |
3185 | + return -1; | |
3186 | + } | |
3187 | + } | |
3188 | + if (next == BB_END (bb)) | |
3189 | + break; | |
3190 | + next = NEXT_INSN (next); | |
3191 | + } | |
38a49943 PS |
3192 | + } |
3193 | + | |
bed1487f | 3194 | + if (distance < LEA_SEARCH_THRESHOLD) |
38a49943 | 3195 | + { |
bed1487f PS |
3196 | + edge e; |
3197 | + edge_iterator ei; | |
3198 | + bool simple_loop = false; | |
3199 | + | |
3200 | + FOR_EACH_EDGE (e, ei, bb->succs) | |
3201 | + if (e->dest == bb) | |
3202 | + { | |
3203 | + simple_loop = true; | |
3204 | + break; | |
3205 | + } | |
3206 | + | |
3207 | + if (simple_loop) | |
3208 | + { | |
3209 | + rtx next = BB_HEAD (bb); | |
3210 | + while (next | |
3211 | + && next != insn | |
3212 | + && distance < LEA_SEARCH_THRESHOLD) | |
3213 | + { | |
3214 | + if (INSN_P (next)) | |
3215 | + { | |
3216 | + distance++; | |
3217 | + | |
3218 | + for (use_rec = DF_INSN_USES (next); *use_rec; use_rec++) | |
3219 | + if ((DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_LOAD | |
3220 | + || DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_STORE) | |
3221 | + && regno0 == DF_REF_REGNO (*use_rec)) | |
3222 | + { | |
3223 | + /* Return DISTANCE if OP0 is used in memory | |
3224 | + address in NEXT. */ | |
3225 | + return distance; | |
3226 | + } | |
3227 | + | |
3228 | + for (def_rec = DF_INSN_DEFS (next); *def_rec; def_rec++) | |
3229 | + if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF | |
3230 | + && !DF_REF_IS_ARTIFICIAL (*def_rec) | |
3231 | + && regno0 == DF_REF_REGNO (*def_rec)) | |
3232 | + { | |
3233 | + /* Return -1 if OP0 is set in NEXT. */ | |
3234 | + return -1; | |
3235 | + } | |
3236 | + | |
3237 | + } | |
3238 | + next = NEXT_INSN (next); | |
3239 | + } | |
3240 | + } | |
3241 | + } | |
3242 | + | |
3243 | + return -1; | |
3244 | +} | |
3245 | + | |
3246 | +/* Define this macro to tune LEA priority vs ADD, it take effect when | |
3247 | + there is a dilemma of choicing LEA or ADD | |
3248 | + Negative value: ADD is more preferred than LEA | |
3249 | + Zero: Netrual | |
3250 | + Positive value: LEA is more preferred than ADD*/ | |
3251 | +#define IX86_LEA_PRIORITY 2 | |
3252 | + | |
3253 | +/* Return true if it is ok to optimize an ADD operation to LEA | |
3254 | + operation to avoid flag register consumation. For the processors | |
3255 | + like ATOM, if the destination register of LEA holds an actual | |
3256 | + address which will be used soon, LEA is better and otherwise ADD | |
3257 | + is better. */ | |
3258 | + | |
3259 | +bool | |
3260 | +ix86_lea_for_add_ok (enum rtx_code code ATTRIBUTE_UNUSED, | |
3261 | + rtx insn, rtx operands[]) | |
3262 | +{ | |
3263 | + unsigned int regno0 = true_regnum (operands[0]); | |
3264 | + unsigned int regno1 = true_regnum (operands[1]); | |
3265 | + unsigned int regno2; | |
3266 | + | |
3267 | + if (!TARGET_OPT_AGU || optimize_function_for_size_p (cfun)) | |
3268 | + return regno0 != regno1; | |
3269 | + | |
3270 | + regno2 = true_regnum (operands[2]); | |
3271 | + | |
3272 | + /* If a = b + c, (a!=b && a!=c), must use lea form. */ | |
3273 | + if (regno0 != regno1 && regno0 != regno2) | |
3274 | + return true; | |
3275 | + else | |
3276 | + { | |
3277 | + int dist_define, dist_use; | |
3278 | + dist_define = distance_non_agu_define (regno1, regno2, insn); | |
3279 | + if (dist_define <= 0) | |
3280 | + return true; | |
3281 | + | |
3282 | + /* If this insn has both backward non-agu dependence and forward | |
3283 | + agu dependence, the one with short distance take effect. */ | |
3284 | + dist_use = distance_agu_use (regno0, insn); | |
3285 | + if (dist_use <= 0 | |
3286 | + || (dist_define + IX86_LEA_PRIORITY) < dist_use) | |
3287 | + return false; | |
3288 | + | |
3289 | + return true; | |
38a49943 | 3290 | + } |
bed1487f | 3291 | +} |
38a49943 | 3292 | + |
bed1487f PS |
3293 | +/* Return true if destination reg of SET_BODY is shift count of |
3294 | + USE_BODY. */ | |
3295 | + | |
3296 | +static bool | |
3297 | +ix86_dep_by_shift_count_body (const_rtx set_body, const_rtx use_body) | |
3298 | +{ | |
3299 | + rtx set_dest; | |
3300 | + rtx shift_rtx; | |
3301 | + int i; | |
3302 | + | |
3303 | + /* Retrieve destination of SET_BODY. */ | |
3304 | + switch (GET_CODE (set_body)) | |
3305 | + { | |
3306 | + case SET: | |
3307 | + set_dest = SET_DEST (set_body); | |
3308 | + if (!set_dest || !REG_P (set_dest)) | |
3309 | + return false; | |
3310 | + break; | |
3311 | + case PARALLEL: | |
3312 | + for (i = XVECLEN (set_body, 0) - 1; i >= 0; i--) | |
3313 | + if (ix86_dep_by_shift_count_body (XVECEXP (set_body, 0, i), | |
3314 | + use_body)) | |
3315 | + return true; | |
3316 | + default: | |
3317 | + return false; | |
3318 | + break; | |
3319 | + } | |
3320 | + | |
3321 | + /* Retrieve shift count of USE_BODY. */ | |
3322 | + switch (GET_CODE (use_body)) | |
3323 | + { | |
3324 | + case SET: | |
3325 | + shift_rtx = XEXP (use_body, 1); | |
3326 | + break; | |
3327 | + case PARALLEL: | |
3328 | + for (i = XVECLEN (use_body, 0) - 1; i >= 0; i--) | |
3329 | + if (ix86_dep_by_shift_count_body (set_body, | |
3330 | + XVECEXP (use_body, 0, i))) | |
3331 | + return true; | |
3332 | + default: | |
3333 | + return false; | |
3334 | + break; | |
3335 | + } | |
3336 | + | |
3337 | + if (shift_rtx | |
3338 | + && (GET_CODE (shift_rtx) == ASHIFT | |
3339 | + || GET_CODE (shift_rtx) == LSHIFTRT | |
3340 | + || GET_CODE (shift_rtx) == ASHIFTRT | |
3341 | + || GET_CODE (shift_rtx) == ROTATE | |
3342 | + || GET_CODE (shift_rtx) == ROTATERT)) | |
3343 | + { | |
3344 | + rtx shift_count = XEXP (shift_rtx, 1); | |
3345 | + | |
3346 | + /* Return true if shift count is dest of SET_BODY. */ | |
3347 | + if (REG_P (shift_count) | |
3348 | + && true_regnum (set_dest) == true_regnum (shift_count)) | |
3349 | + return true; | |
3350 | + } | |
3351 | + | |
3352 | + return false; | |
3353 | +} | |
3354 | + | |
3355 | +/* Return true if destination reg of SET_INSN is shift count of | |
3356 | + USE_INSN. */ | |
3357 | + | |
3358 | +bool | |
3359 | +ix86_dep_by_shift_count (const_rtx set_insn, const_rtx use_insn) | |
3360 | +{ | |
3361 | + return ix86_dep_by_shift_count_body (PATTERN (set_insn), | |
3362 | + PATTERN (use_insn)); | |
38a49943 PS |
3363 | +} |
3364 | + | |
bed1487f PS |
3365 | /* Return TRUE or FALSE depending on whether the unary operator meets the |
3366 | appropriate constraints. */ | |
38a49943 | 3367 | |
bed1487f PS |
3368 | @@ -18761,7 +19183,7 @@ |
3369 | f = GGC_CNEW (struct machine_function); | |
3370 | f->use_fast_prologue_epilogue_nregs = -1; | |
3371 | f->tls_descriptor_call_expanded_p = 0; | |
3372 | - f->call_abi = DEFAULT_ABI; | |
3373 | + f->call_abi = ix86_abi; | |
38a49943 | 3374 | |
bed1487f PS |
3375 | return f; |
3376 | } | |
3377 | @@ -19022,6 +19444,7 @@ | |
3378 | switch (ix86_tune) | |
3379 | { | |
3380 | case PROCESSOR_PENTIUM: | |
3381 | + case PROCESSOR_ATOM: | |
3382 | case PROCESSOR_K6: | |
3383 | return 2; | |
3384 | ||
3385 | @@ -19088,41 +19511,21 @@ | |
3386 | return 1; | |
3387 | } | |
3388 | ||
3389 | -/* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory | |
3390 | - address with operands set by DEP_INSN. */ | |
3391 | +/* Return true iff USE_INSN has a memory address with operands set by | |
3392 | + SET_INSN. */ | |
3393 | ||
3394 | -static int | |
3395 | -ix86_agi_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type) | |
3396 | +bool | |
3397 | +ix86_agi_dependent (rtx set_insn, rtx use_insn) | |
3398 | { | |
3399 | - rtx addr; | |
3400 | - | |
3401 | - if (insn_type == TYPE_LEA | |
3402 | - && TARGET_PENTIUM) | |
3403 | - { | |
3404 | - addr = PATTERN (insn); | |
3405 | - | |
3406 | - if (GET_CODE (addr) == PARALLEL) | |
3407 | - addr = XVECEXP (addr, 0, 0); | |
3408 | - | |
3409 | - gcc_assert (GET_CODE (addr) == SET); | |
3410 | - | |
3411 | - addr = SET_SRC (addr); | |
3412 | - } | |
3413 | - else | |
3414 | - { | |
3415 | - int i; | |
3416 | - extract_insn_cached (insn); | |
3417 | - for (i = recog_data.n_operands - 1; i >= 0; --i) | |
3418 | - if (MEM_P (recog_data.operand[i])) | |
3419 | - { | |
3420 | - addr = XEXP (recog_data.operand[i], 0); | |
3421 | - goto found; | |
3422 | - } | |
3423 | - return 0; | |
3424 | - found:; | |
3425 | - } | |
3426 | - | |
3427 | - return modified_in_p (addr, dep_insn); | |
3428 | + int i; | |
3429 | + extract_insn_cached (use_insn); | |
3430 | + for (i = recog_data.n_operands - 1; i >= 0; --i) | |
3431 | + if (MEM_P (recog_data.operand[i])) | |
3432 | + { | |
3433 | + rtx addr = XEXP (recog_data.operand[i], 0); | |
3434 | + return modified_in_p (addr, set_insn) != 0; | |
3435 | + } | |
3436 | + return false; | |
3437 | } | |
3438 | ||
3439 | static int | |
3440 | @@ -19150,7 +19553,20 @@ | |
3441 | { | |
3442 | case PROCESSOR_PENTIUM: | |
3443 | /* Address Generation Interlock adds a cycle of latency. */ | |
3444 | - if (ix86_agi_dependent (insn, dep_insn, insn_type)) | |
3445 | + if (insn_type == TYPE_LEA) | |
3446 | + { | |
3447 | + rtx addr = PATTERN (insn); | |
38a49943 | 3448 | + |
bed1487f PS |
3449 | + if (GET_CODE (addr) == PARALLEL) |
3450 | + addr = XVECEXP (addr, 0, 0); | |
3451 | + | |
3452 | + gcc_assert (GET_CODE (addr) == SET); | |
3453 | + | |
3454 | + addr = SET_SRC (addr); | |
3455 | + if (modified_in_p (addr, dep_insn)) | |
3456 | + cost += 1; | |
3457 | + } | |
3458 | + else if (ix86_agi_dependent (dep_insn, insn)) | |
3459 | cost += 1; | |
3460 | ||
3461 | /* ??? Compares pair with jump/setcc. */ | |
3462 | @@ -19160,7 +19576,7 @@ | |
3463 | /* Floating point stores require value to be ready one cycle earlier. */ | |
3464 | if (insn_type == TYPE_FMOV | |
3465 | && get_attr_memory (insn) == MEMORY_STORE | |
3466 | - && !ix86_agi_dependent (insn, dep_insn, insn_type)) | |
3467 | + && !ix86_agi_dependent (dep_insn, insn)) | |
3468 | cost += 1; | |
3469 | break; | |
3470 | ||
3471 | @@ -19183,7 +19599,7 @@ | |
3472 | in parallel with previous instruction in case | |
3473 | previous instruction is not needed to compute the address. */ | |
3474 | if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH) | |
3475 | - && !ix86_agi_dependent (insn, dep_insn, insn_type)) | |
3476 | + && !ix86_agi_dependent (dep_insn, insn)) | |
3477 | { | |
3478 | /* Claim moves to take one cycle, as core can issue one load | |
3479 | at time and the next load can start cycle later. */ | |
3480 | @@ -19212,7 +19628,7 @@ | |
3481 | in parallel with previous instruction in case | |
3482 | previous instruction is not needed to compute the address. */ | |
3483 | if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH) | |
3484 | - && !ix86_agi_dependent (insn, dep_insn, insn_type)) | |
3485 | + && !ix86_agi_dependent (dep_insn, insn)) | |
3486 | { | |
3487 | /* Claim moves to take one cycle, as core can issue one load | |
3488 | at time and the next load can start cycle later. */ | |
3489 | @@ -19229,6 +19645,7 @@ | |
3490 | case PROCESSOR_ATHLON: | |
3491 | case PROCESSOR_K8: | |
3492 | case PROCESSOR_AMDFAM10: | |
3493 | + case PROCESSOR_ATOM: | |
3494 | case PROCESSOR_GENERIC32: | |
3495 | case PROCESSOR_GENERIC64: | |
3496 | memory = get_attr_memory (insn); | |
3497 | @@ -19237,7 +19654,7 @@ | |
3498 | in parallel with previous instruction in case | |
3499 | previous instruction is not needed to compute the address. */ | |
3500 | if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH) | |
3501 | - && !ix86_agi_dependent (insn, dep_insn, insn_type)) | |
3502 | + && !ix86_agi_dependent (dep_insn, insn)) | |
3503 | { | |
3504 | enum attr_unit unit = get_attr_unit (insn); | |
3505 | int loadcost = 3; | |
3506 | @@ -29480,14 +29897,11 @@ | |
3507 | tree | |
3508 | ix86_fn_abi_va_list (tree fndecl) | |
3509 | { | |
3510 | - int abi; | |
3511 | - | |
3512 | if (!TARGET_64BIT) | |
3513 | return va_list_type_node; | |
3514 | gcc_assert (fndecl != NULL_TREE); | |
3515 | - abi = ix86_function_abi ((const_tree) fndecl); | |
38a49943 | 3516 | |
bed1487f PS |
3517 | - if (abi == MS_ABI) |
3518 | + if (ix86_function_abi ((const_tree) fndecl) == MS_ABI) | |
3519 | return ms_va_list_type_node; | |
3520 | else | |
3521 | return sysv_va_list_type_node; | |
3522 | ||
3523 | Property changes on: libstdc++-v3/testsuite/27_io/basic_ofstream/cons/char/1.cc | |
3524 | ___________________________________________________________________ | |
3525 | Deleted: svn:mergeinfo | |
3526 | ||
3527 | ||
3528 | Property changes on: libstdc++-v3/testsuite/27_io/basic_ofstream/pthread2.cc | |
3529 | ___________________________________________________________________ | |
3530 | Deleted: svn:mergeinfo | |
3531 | ||
3532 | ||
3533 | Property changes on: libstdc++-v3/testsuite/27_io/basic_fstream/open/char/1.cc | |
3534 | ___________________________________________________________________ | |
3535 | Deleted: svn:mergeinfo | |
3536 | ||
3537 | ||
3538 | Property changes on: libstdc++-v3/testsuite/27_io/basic_fstream/cons/1.cc | |
3539 | ___________________________________________________________________ | |
3540 | Deleted: svn:mergeinfo | |
3541 | ||
3542 | ||
3543 | Property changes on: libstdc++-v3/testsuite/27_io/basic_ostringstream/pthread3.cc | |
3544 | ___________________________________________________________________ | |
3545 | Deleted: svn:mergeinfo | |
3546 | ||
3547 | ||
3548 | Property changes on: libstdc++-v3/testsuite/18_support/pthread_guard.cc | |
3549 | ___________________________________________________________________ | |
3550 | Deleted: svn:mergeinfo | |
3551 | ||
3552 | ||
3553 | Property changes on: libstdc++-v3/testsuite/21_strings/char_traits/requirements/explicit_instantiation/wchar_t/1.cc | |
3554 | ___________________________________________________________________ | |
3555 | Deleted: svn:mergeinfo | |
3556 | ||
3557 | ||
3558 | Property changes on: libstdc++-v3/testsuite/21_strings/char_traits/requirements/explicit_instantiation/char/1.cc | |
3559 | ___________________________________________________________________ | |
3560 | Deleted: svn:mergeinfo | |
3561 | ||
3562 | ||
3563 | Property changes on: libstdc++-v3/testsuite/21_strings/basic_string/pthread18185.cc | |
3564 | ___________________________________________________________________ | |
3565 | Deleted: svn:mergeinfo | |
3566 | ||
3567 | ||
3568 | Property changes on: libstdc++-v3/testsuite/21_strings/basic_string/pthread4.cc | |
3569 | ___________________________________________________________________ | |
3570 | Deleted: svn:mergeinfo | |
3571 | ||
3572 | ||
3573 | Property changes on: libstdc++-v3/testsuite/30_threads/thread/members | |
3574 | ___________________________________________________________________ | |
3575 | Deleted: svn:mergeinfo | |
3576 | ||
3577 | ||
3578 | Property changes on: libstdc++-v3/testsuite/30_threads/thread/swap | |
3579 | ___________________________________________________________________ | |
3580 | Deleted: svn:mergeinfo | |
3581 | ||
3582 | ||
3583 | Property changes on: libstdc++-v3/testsuite/30_threads/condition_variable/members | |
3584 | ___________________________________________________________________ | |
3585 | Deleted: svn:mergeinfo | |
3586 | ||
3587 | ||
3588 | Property changes on: libstdc++-v3/testsuite/30_threads/this_thread | |
3589 | ___________________________________________________________________ | |
3590 | Deleted: svn:mergeinfo | |
3591 | ||
3592 | ||
3593 | Property changes on: libstdc++-v3/testsuite/ext/rope/pthread7-rope.cc | |
3594 | ___________________________________________________________________ | |
3595 | Deleted: svn:mergeinfo | |
3596 | ||
3597 | ||
3598 | Property changes on: libstdc++-v3/testsuite/tr1/6_containers/unordered_multimap/requirements/typedefs.cc | |
3599 | ___________________________________________________________________ | |
3600 | Deleted: svn:mergeinfo | |
3601 | ||
3602 | ||
3603 | Property changes on: libstdc++-v3/testsuite/tr1/6_containers/unordered_set/requirements/typedefs.cc | |
3604 | ___________________________________________________________________ | |
3605 | Deleted: svn:mergeinfo | |
3606 | ||
3607 | ||
3608 | Property changes on: libstdc++-v3/testsuite/tr1/6_containers/unordered_map/requirements/typedefs.cc | |
3609 | ___________________________________________________________________ | |
3610 | Deleted: svn:mergeinfo | |
3611 | ||
3612 | ||
3613 | Property changes on: libstdc++-v3/testsuite/tr1/6_containers/unordered_multiset/requirements/typedefs.cc | |
3614 | ___________________________________________________________________ | |
3615 | Deleted: svn:mergeinfo | |
3616 | ||
3617 | ||
3618 | Property changes on: libstdc++-v3/testsuite/23_containers/unordered_map/requirements/typedefs.cc | |
3619 | ___________________________________________________________________ | |
3620 | Deleted: svn:mergeinfo | |
3621 | ||
3622 | ||
3623 | Property changes on: libstdc++-v3/testsuite/23_containers/unordered_multimap/requirements/typedefs.cc | |
3624 | ___________________________________________________________________ | |
3625 | Deleted: svn:mergeinfo | |
3626 | ||
3627 | ||
3628 | Property changes on: libstdc++-v3/testsuite/23_containers/unordered_set/requirements/typedefs.cc | |
3629 | ___________________________________________________________________ | |
3630 | Deleted: svn:mergeinfo | |
3631 | ||
3632 | ||
3633 | Property changes on: libstdc++-v3/testsuite/23_containers/headers/forward_list/synopsis.cc | |
3634 | ___________________________________________________________________ | |
3635 | Deleted: svn:mergeinfo | |
3636 | ||
3637 | ||
3638 | Property changes on: libstdc++-v3/testsuite/23_containers/list/pthread5.cc | |
3639 | ___________________________________________________________________ | |
3640 | Deleted: svn:mergeinfo | |
3641 | ||
3642 | ||
3643 | Property changes on: libstdc++-v3/testsuite/23_containers/list/pthread1.cc | |
3644 | ___________________________________________________________________ | |
3645 | Deleted: svn:mergeinfo | |
3646 | ||
3647 | ||
3648 | Property changes on: libstdc++-v3/testsuite/23_containers/unordered_multiset/requirements/typedefs.cc | |
3649 | ___________________________________________________________________ | |
3650 | Deleted: svn:mergeinfo | |
3651 | ||
3652 | ||
3653 | Property changes on: libstdc++-v3/testsuite/23_containers/map/pthread6.cc | |
3654 | ___________________________________________________________________ | |
3655 | Deleted: svn:mergeinfo | |
3656 | ||
3657 | ||
3658 | Property changes on: libstdc++-v3/testsuite/20_util/unique_ptr/assign/assign_neg.cc | |
3659 | ___________________________________________________________________ | |
3660 | Deleted: svn:mergeinfo | |
3661 | ||
3662 | ||
3663 | Property changes on: libstdc++-v3/testsuite/20_util/ratio/cons/cons_overflow_neg.cc | |
3664 | ___________________________________________________________________ | |
3665 | Deleted: svn:mergeinfo | |
3666 | ||
3667 | ||
3668 | Property changes on: libstdc++-v3/testsuite/20_util/ratio/operations/ops_overflow_neg.cc | |
3669 | ___________________________________________________________________ | |
3670 | Deleted: svn:mergeinfo | |
3671 | ||
3672 | ||
3673 | Property changes on: libstdc++-v3/testsuite/20_util/shared_ptr/cons/unique_ptr_deleter_ref_1.cc | |
3674 | ___________________________________________________________________ | |
3675 | Deleted: svn:mergeinfo | |
3676 | ||
3677 | ||
3678 | Property changes on: libjava/classpath | |
3679 | ___________________________________________________________________ | |
3680 | Deleted: svn:mergeinfo | |
3681 | Reverse-merged /branches/CLASSPATH/libjava/classpath:r144110 | |
3682 | ||
38a49943 PS |
3683 | |
3684 | Property changes on: . | |
3685 | ___________________________________________________________________ | |
3686 | Added: svn:mergeinfo | |
bed1487f PS |
3687 | Merged /branches/gcc-4_4-branch:r145147-146513 |
3688 | Merged /trunk:r145624 | |
38a49943 | 3689 |