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[packages/crossm68k-gcc.git] / crossm68k-gcc-coldfire-targets.patch
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1b8f31c8 1
2Rename the ColdFire target macro to TARGET_COLDFIRE instead of
3the less appropriate TARGET_5200.
4
5Add options for new ColdFire targets.
6
7(based on Peter Barada's CVS tree for ColdFire targets)
8
9diff -Nru gcc-3.3.1.orig/gcc/config/m68k/coff.h gcc-3.3.1/gcc/config/m68k/coff.h
10--- gcc-3.3.1.orig/gcc/config/m68k/coff.h 2003-01-28 23:18:15.000000000 +0100
11+++ gcc-3.3.1/gcc/config/m68k/coff.h 2003-07-25 00:25:30.000000000 +0200
12@@ -57,7 +57,7 @@
13
14 #define ASM_RETURN_CASE_JUMP \
15 do { \
16- if (TARGET_5200) \
17+ if (TARGET_COLDFIRE) \
18 { \
19 if (ADDRESS_REG_P (operands[0])) \
20 return "jmp %%pc@(2,%0:l)"; \
21diff -Nru gcc-3.3.1.orig/gcc/config/m68k/lb1sf68.asm gcc-3.3.1/gcc/config/m68k/lb1sf68.asm
22--- gcc-3.3.1.orig/gcc/config/m68k/lb1sf68.asm 2001-05-17 05:16:01.000000000 +0200
23+++ gcc-3.3.1/gcc/config/m68k/lb1sf68.asm 2003-07-25 00:25:30.000000000 +0200
24@@ -214,7 +214,7 @@
25 | void __clear_sticky_bits(void);
26 SYM (__clear_sticky_bit):
27 lea SYM (_fpCCR),a0
28-#ifndef __mcf5200__
29+#ifndef __mcoldfire__
30 movew IMM (0),a0@(STICK)
31 #else
32 clr.w a0@(STICK)
33@@ -248,7 +248,7 @@
34 $_exception_handler:
35 lea SYM (_fpCCR),a0
36 movew d7,a0@(EBITS) | set __exception_bits
37-#ifndef __mcf5200__
38+#ifndef __mcoldfire__
39 orw d7,a0@(STICK) | and __sticky_bits
40 #else
41 movew a0@(STICK),d4
42@@ -259,7 +259,7 @@
43 movew d5,a0@(LASTO) | and __last_operation
44
45 | Now put the operands in place:
46-#ifndef __mcf5200__
47+#ifndef __mcoldfire__
48 cmpw IMM (SINGLE_FLOAT),d6
49 #else
50 cmpl IMM (SINGLE_FLOAT),d6
51@@ -274,7 +274,7 @@
52 movel a6@(12),a0@(OPER2)
53 2:
54 | And check whether the exception is trap-enabled:
55-#ifndef __mcf5200__
56+#ifndef __mcoldfire__
57 andw a0@(TRAPE),d7 | is exception trap-enabled?
58 #else
59 clrl d6
60@@ -284,7 +284,7 @@
61 beq 1f | no, exit
62 pea SYM (_fpCCR) | yes, push address of _fpCCR
63 trap IMM (FPTRAP) | and trap
64-#ifndef __mcf5200__
65+#ifndef __mcoldfire__
66 1: moveml sp@+,d2-d7 | restore data registers
67 #else
68 1: moveml sp@,d2-d7
69@@ -304,7 +304,7 @@
70 muluw sp@(10), d0 /* x0*y1 */
71 movew sp@(6), d1 /* x1 -> d1 */
72 muluw sp@(8), d1 /* x1*y0 */
73-#ifndef __mcf5200__
74+#ifndef __mcoldfire__
75 addw d1, d0
76 #else
77 addl d1, d0
78@@ -323,7 +323,7 @@
79 .proc
80 .globl SYM (__udivsi3)
81 SYM (__udivsi3):
82-#ifndef __mcf5200__
83+#ifndef __mcoldfire__
84 movel d2, sp@-
85 movel sp@(12), d1 /* d1 = divisor */
86 movel sp@(8), d0 /* d0 = dividend */
87@@ -368,7 +368,7 @@
88 L6: movel sp@+, d2
89 rts
90
91-#else /* __mcf5200__ */
92+#else /* __mcoldfire__ */
93
94 /* Coldfire implementation of non-restoring division algorithm from
95 Hennessy & Patterson, Appendix A. */
96@@ -390,7 +390,7 @@
97 moveml sp@,d2-d4 | restore data registers
98 unlk a6 | and return
99 rts
100-#endif /* __mcf5200__ */
101+#endif /* __mcoldfire__ */
102
103 #endif /* L_udivsi3 */
104
105@@ -405,7 +405,7 @@
106 movel sp@(12), d1 /* d1 = divisor */
107 jpl L1
108 negl d1
109-#ifndef __mcf5200__
110+#ifndef __mcoldfire__
111 negb d2 /* change sign because divisor <0 */
112 #else
113 negl d2 /* change sign because divisor <0 */
114@@ -413,7 +413,7 @@
115 L1: movel sp@(8), d0 /* d0 = dividend */
116 jpl L2
117 negl d0
118-#ifndef __mcf5200__
119+#ifndef __mcoldfire__
120 negb d2
121 #else
122 negl d2
123@@ -444,7 +444,7 @@
124 jbsr SYM (__udivsi3)
125 addql IMM (8), sp
126 movel sp@(8), d1 /* d1 = divisor */
127-#ifndef __mcf5200__
128+#ifndef __mcoldfire__
129 movel d1, sp@-
130 movel d0, sp@-
131 jbsr SYM (__mulsi3) /* d0 = (a/b)*b */
132@@ -470,7 +470,7 @@
133 jbsr SYM (__divsi3)
134 addql IMM (8), sp
135 movel sp@(8), d1 /* d1 = divisor */
136-#ifndef __mcf5200__
137+#ifndef __mcoldfire__
138 movel d1, sp@-
139 movel d0, sp@-
140 jbsr SYM (__mulsi3) /* d0 = (a/b)*b */
141@@ -611,7 +611,7 @@
142
143 | double __adddf3(double, double);
144 SYM (__adddf3):
145-#ifndef __mcf5200__
146+#ifndef __mcoldfire__
147 link a6,IMM (0) | everything will be done in registers
148 moveml d2-d7,sp@- | save all data registers and a2 (but d0-d1)
149 #else
150@@ -635,7 +635,7 @@
151
152 andl IMM (0x80000000),d7 | isolate a's sign bit '
153 swap d6 | and also b's sign bit '
154-#ifndef __mcf5200__
155+#ifndef __mcoldfire__
156 andw IMM (0x8000),d6 |
157 orw d6,d7 | and combine them into d7, so that a's sign '
158 | bit is in the high word and b's is in the '
159@@ -662,7 +662,7 @@
160 orl d7,d0 | and put hidden bit back
161 Ladddf$1:
162 swap d4 | shift right exponent so that it starts
163-#ifndef __mcf5200__
164+#ifndef __mcoldfire__
165 lsrw IMM (5),d4 | in bit 0 and not bit 20
166 #else
167 lsrl IMM (5),d4 | in bit 0 and not bit 20
168@@ -678,7 +678,7 @@
169 orl d7,d2 | and put hidden bit back
170 Ladddf$2:
171 swap d5 | shift right exponent so that it starts
172-#ifndef __mcf5200__
173+#ifndef __mcoldfire__
174 lsrw IMM (5),d5 | in bit 0 and not bit 20
175 #else
176 lsrl IMM (5),d5 | in bit 0 and not bit 20
177@@ -693,7 +693,7 @@
178 | and d4-d5-d6-d7 for the second. To do this we store (temporarily) the
179 | exponents in a2-a3.
180
181-#ifndef __mcf5200__
182+#ifndef __mcoldfire__
183 moveml a2-a3,sp@- | save the address registers
184 #else
185 movel a2,sp@-
186@@ -713,7 +713,7 @@
187
188 | Here we shift the numbers until the exponents are the same, and put
189 | the largest exponent in a2.
190-#ifndef __mcf5200__
191+#ifndef __mcoldfire__
192 exg d4,a2 | get exponents back
193 exg d5,a3 |
194 cmpw d4,d5 | compare the exponents
195@@ -732,7 +732,7 @@
196 | Here we have a's exponent larger than b's, so we have to shift b. We do
197 | this by using as counter d2:
198 1: movew d4,d2 | move largest exponent to d2
199-#ifndef __mcf5200__
200+#ifndef __mcoldfire__
201 subw d5,d2 | and subtract second exponent
202 exg d4,a2 | get back the longs we saved
203 exg d5,a3 |
204@@ -746,20 +746,20 @@
205 movel a4,a3
206 #endif
207 | if difference is too large we don't shift (actually, we can just exit) '
208-#ifndef __mcf5200__
209+#ifndef __mcoldfire__
210 cmpw IMM (DBL_MANT_DIG+2),d2
211 #else
212 cmpl IMM (DBL_MANT_DIG+2),d2
213 #endif
214 bge Ladddf$b$small
215-#ifndef __mcf5200__
216+#ifndef __mcoldfire__
217 cmpw IMM (32),d2 | if difference >= 32, shift by longs
218 #else
219 cmpl IMM (32),d2 | if difference >= 32, shift by longs
220 #endif
221 bge 5f
222 2:
223-#ifndef __mcf5200__
224+#ifndef __mcoldfire__
225 cmpw IMM (16),d2 | if difference >= 16, shift by words
226 #else
227 cmpl IMM (16),d2 | if difference >= 16, shift by words
228@@ -768,7 +768,7 @@
229 bra 3f | enter dbra loop
230
231 4:
232-#ifndef __mcf5200__
233+#ifndef __mcoldfire__
234 lsrl IMM (1),d4
235 roxrl IMM (1),d5
236 roxrl IMM (1),d6
237@@ -789,7 +789,7 @@
238 12: lsrl IMM (1),d4
239 #endif
240 3:
241-#ifndef __mcf5200__
242+#ifndef __mcoldfire__
243 dbra d2,4b
244 #else
245 subql IMM (1),d2
246@@ -803,7 +803,7 @@
247 movel d5,d6
248 movel d4,d5
249 movel IMM (0),d4
250-#ifndef __mcf5200__
251+#ifndef __mcoldfire__
252 subw IMM (32),d2
253 #else
254 subl IMM (32),d2
255@@ -818,7 +818,7 @@
256 swap d5
257 movew IMM (0),d4
258 swap d4
259-#ifndef __mcf5200__
260+#ifndef __mcoldfire__
261 subw IMM (16),d2
262 #else
263 subl IMM (16),d2
264@@ -826,7 +826,7 @@
265 bra 3b
266
267 9:
268-#ifndef __mcf5200__
269+#ifndef __mcoldfire__
270 exg d4,d5
271 movew d4,d6
272 subw d5,d6 | keep d5 (largest exponent) in d4
273@@ -845,20 +845,20 @@
274 movel a4,a3
275 #endif
276 | if difference is too large we don't shift (actually, we can just exit) '
277-#ifndef __mcf5200__
278+#ifndef __mcoldfire__
279 cmpw IMM (DBL_MANT_DIG+2),d6
280 #else
281 cmpl IMM (DBL_MANT_DIG+2),d6
282 #endif
283 bge Ladddf$a$small
284-#ifndef __mcf5200__
285+#ifndef __mcoldfire__
286 cmpw IMM (32),d6 | if difference >= 32, shift by longs
287 #else
288 cmpl IMM (32),d6 | if difference >= 32, shift by longs
289 #endif
290 bge 5f
291 2:
292-#ifndef __mcf5200__
293+#ifndef __mcoldfire__
294 cmpw IMM (16),d6 | if difference >= 16, shift by words
295 #else
296 cmpl IMM (16),d6 | if difference >= 16, shift by words
297@@ -867,7 +867,7 @@
298 bra 3f | enter dbra loop
299
300 4:
301-#ifndef __mcf5200__
302+#ifndef __mcoldfire__
303 lsrl IMM (1),d0
304 roxrl IMM (1),d1
305 roxrl IMM (1),d2
306@@ -888,7 +888,7 @@
307 12: lsrl IMM (1),d0
308 #endif
309 3:
310-#ifndef __mcf5200__
311+#ifndef __mcoldfire__
312 dbra d6,4b
313 #else
314 subql IMM (1),d6
315@@ -902,7 +902,7 @@
316 movel d1,d2
317 movel d0,d1
318 movel IMM (0),d0
319-#ifndef __mcf5200__
320+#ifndef __mcoldfire__
321 subw IMM (32),d6
322 #else
323 subl IMM (32),d6
324@@ -917,14 +917,14 @@
325 swap d1
326 movew IMM (0),d0
327 swap d0
328-#ifndef __mcf5200__
329+#ifndef __mcoldfire__
330 subw IMM (16),d6
331 #else
332 subl IMM (16),d6
333 #endif
334 bra 3b
335 Ladddf$3:
336-#ifndef __mcf5200__
337+#ifndef __mcoldfire__
338 exg d4,a2
339 exg d5,a3
340 #else
341@@ -940,7 +940,7 @@
342 | the signs in a4.
343
344 | Here we have to decide whether to add or subtract the numbers:
345-#ifndef __mcf5200__
346+#ifndef __mcoldfire__
347 exg d7,a0 | get the signs
348 exg d6,a3 | a3 is free to be used
349 #else
350@@ -958,7 +958,7 @@
351 eorl d7,d6 | compare the signs
352 bmi Lsubdf$0 | if the signs are different we have
353 | to subtract
354-#ifndef __mcf5200__
355+#ifndef __mcoldfire__
356 exg d7,a0 | else we add the numbers
357 exg d6,a3 |
358 #else
359@@ -978,7 +978,7 @@
360 movel a0,d7 |
361 andl IMM (0x80000000),d7 | d7 now has the sign
362
363-#ifndef __mcf5200__
364+#ifndef __mcoldfire__
365 moveml sp@+,a2-a3
366 #else
367 movel sp@+,a4
368@@ -992,7 +992,7 @@
369 | one more bit we check this:
370 btst IMM (DBL_MANT_DIG+1),d0
371 beq 1f
372-#ifndef __mcf5200__
373+#ifndef __mcoldfire__
374 lsrl IMM (1),d0
375 roxrl IMM (1),d1
376 roxrl IMM (1),d2
377@@ -1017,12 +1017,12 @@
378 1:
379 lea Ladddf$5,a0 | to return from rounding routine
380 lea SYM (_fpCCR),a1 | check the rounding mode
381-#ifdef __mcf5200__
382+#ifdef __mcoldfire__
383 clrl d6
384 #endif
385 movew a1@(6),d6 | rounding mode in d6
386 beq Lround$to$nearest
387-#ifndef __mcf5200__
388+#ifndef __mcoldfire__
389 cmpw IMM (ROUND_TO_PLUS),d6
390 #else
391 cmpl IMM (ROUND_TO_PLUS),d6
392@@ -1032,20 +1032,20 @@
393 bra Lround$to$plus
394 Ladddf$5:
395 | Put back the exponent and check for overflow
396-#ifndef __mcf5200__
397+#ifndef __mcoldfire__
398 cmpw IMM (0x7ff),d4 | is the exponent big?
399 #else
400 cmpl IMM (0x7ff),d4 | is the exponent big?
401 #endif
402 bge 1f
403 bclr IMM (DBL_MANT_DIG-1),d0
404-#ifndef __mcf5200__
405+#ifndef __mcoldfire__
406 lslw IMM (4),d4 | put exponent back into position
407 #else
408 lsll IMM (4),d4 | put exponent back into position
409 #endif
410 swap d0 |
411-#ifndef __mcf5200__
412+#ifndef __mcoldfire__
413 orw d4,d0 |
414 #else
415 orl d4,d0 |
416@@ -1058,7 +1058,7 @@
417
418 Lsubdf$0:
419 | Here we do the subtraction.
420-#ifndef __mcf5200__
421+#ifndef __mcoldfire__
422 exg d7,a0 | put sign back in a0
423 exg d6,a3 |
424 #else
425@@ -1086,7 +1086,7 @@
426 movel a2,d4 | return exponent to d4
427 movel a0,d7
428 andl IMM (0x80000000),d7 | isolate sign bit
429-#ifndef __mcf5200__
430+#ifndef __mcoldfire__
431 moveml sp@+,a2-a3 |
432 #else
433 movel sp@+,a4
434@@ -1100,7 +1100,7 @@
435 | one more bit we check this:
436 btst IMM (DBL_MANT_DIG+1),d0
437 beq 1f
438-#ifndef __mcf5200__
439+#ifndef __mcoldfire__
440 lsrl IMM (1),d0
441 roxrl IMM (1),d1
442 roxrl IMM (1),d2
443@@ -1125,12 +1125,12 @@
444 1:
445 lea Lsubdf$1,a0 | to return from rounding routine
446 lea SYM (_fpCCR),a1 | check the rounding mode
447-#ifdef __mcf5200__
448+#ifdef __mcoldfire__
449 clrl d6
450 #endif
451 movew a1@(6),d6 | rounding mode in d6
452 beq Lround$to$nearest
453-#ifndef __mcf5200__
454+#ifndef __mcoldfire__
455 cmpw IMM (ROUND_TO_PLUS),d6
456 #else
457 cmpl IMM (ROUND_TO_PLUS),d6
458@@ -1141,13 +1141,13 @@
459 Lsubdf$1:
460 | Put back the exponent and sign (we don't have overflow). '
461 bclr IMM (DBL_MANT_DIG-1),d0
462-#ifndef __mcf5200__
463+#ifndef __mcoldfire__
464 lslw IMM (4),d4 | put exponent back into position
465 #else
466 lsll IMM (4),d4 | put exponent back into position
467 #endif
468 swap d0 |
469-#ifndef __mcf5200__
470+#ifndef __mcoldfire__
471 orw d4,d0 |
472 #else
473 orl d4,d0 |
474@@ -1159,7 +1159,7 @@
475 | DBL_MANT_DIG+1) we return the other (and now we don't have to '
476 | check for finiteness or zero).
477 Ladddf$a$small:
478-#ifndef __mcf5200__
479+#ifndef __mcoldfire__
480 moveml sp@+,a2-a3
481 #else
482 movel sp@+,a4
483@@ -1170,7 +1170,7 @@
484 movel a6@(20),d1
485 lea SYM (_fpCCR),a0
486 movew IMM (0),a0@
487-#ifndef __mcf5200__
488+#ifndef __mcoldfire__
489 moveml sp@+,d2-d7 | restore data registers
490 #else
491 moveml sp@,d2-d7
492@@ -1181,7 +1181,7 @@
493 rts
494
495 Ladddf$b$small:
496-#ifndef __mcf5200__
497+#ifndef __mcoldfire__
498 moveml sp@+,a2-a3
499 #else
500 movel sp@+,a4
501@@ -1192,7 +1192,7 @@
502 movel a6@(12),d1
503 lea SYM (_fpCCR),a0
504 movew IMM (0),a0@
505-#ifndef __mcf5200__
506+#ifndef __mcoldfire__
507 moveml sp@+,d2-d7 | restore data registers
508 #else
509 moveml sp@,d2-d7
510@@ -1238,7 +1238,7 @@
511 bra Ld$infty |
512
513 Ladddf$ret$1:
514-#ifndef __mcf5200__
515+#ifndef __mcoldfire__
516 moveml sp@+,a2-a3 | restore regs and exit
517 #else
518 movel sp@+,a4
519@@ -1251,7 +1251,7 @@
520 lea SYM (_fpCCR),a0
521 movew IMM (0),a0@
522 orl d7,d0 | put sign bit back
523-#ifndef __mcf5200__
524+#ifndef __mcoldfire__
525 moveml sp@+,d2-d7
526 #else
527 moveml sp@,d2-d7
528@@ -1263,7 +1263,7 @@
529
530 Ladddf$ret$den:
531 | Return a denormalized number.
532-#ifndef __mcf5200__
533+#ifndef __mcoldfire__
534 lsrl IMM (1),d0 | shift right once more
535 roxrl IMM (1),d1 |
536 #else
537@@ -1329,7 +1329,7 @@
538
539 | double __muldf3(double, double);
540 SYM (__muldf3):
541-#ifndef __mcf5200__
542+#ifndef __mcoldfire__
543 link a6,IMM (0)
544 moveml d2-d7,sp@-
545 #else
546@@ -1370,7 +1370,7 @@
547 andl d6,d0 | isolate fraction
548 orl IMM (0x00100000),d0 | and put hidden bit back
549 swap d4 | I like exponents in the first byte
550-#ifndef __mcf5200__
551+#ifndef __mcoldfire__
552 lsrw IMM (4),d4 |
553 #else
554 lsrl IMM (4),d4 |
555@@ -1381,13 +1381,13 @@
556 andl d6,d2 |
557 orl IMM (0x00100000),d2 | and put hidden bit back
558 swap d5 |
559-#ifndef __mcf5200__
560+#ifndef __mcoldfire__
561 lsrw IMM (4),d5 |
562 #else
563 lsrl IMM (4),d5 |
564 #endif
565 Lmuldf$2: |
566-#ifndef __mcf5200__
567+#ifndef __mcoldfire__
568 addw d5,d4 | add exponents
569 subw IMM (D_BIAS+1),d4 | and subtract bias (plus one)
570 #else
571@@ -1405,7 +1405,7 @@
572 | enough to keep everything in them. So we use the address registers to keep
573 | some intermediate data.
574
575-#ifndef __mcf5200__
576+#ifndef __mcoldfire__
577 moveml a2-a3,sp@- | save a2 and a3 for temporary use
578 #else
579 movel a2,sp@-
580@@ -1416,7 +1416,7 @@
581 movel d4,a3 | and a3 will preserve the exponent
582
583 | First, shift d2-d3 so bit 20 becomes bit 31:
584-#ifndef __mcf5200__
585+#ifndef __mcoldfire__
586 rorl IMM (5),d2 | rotate d2 5 places right
587 swap d2 | and swap it
588 rorl IMM (5),d3 | do the same thing with d3
589@@ -1447,7 +1447,7 @@
590
591 | We use a1 as counter:
592 movel IMM (DBL_MANT_DIG-1),a1
593-#ifndef __mcf5200__
594+#ifndef __mcoldfire__
595 exg d7,a1
596 #else
597 movel d7,a4
598@@ -1456,7 +1456,7 @@
599 #endif
600
601 1:
602-#ifndef __mcf5200__
603+#ifndef __mcoldfire__
604 exg d7,a1 | put counter back in a1
605 #else
606 movel d7,a4
607@@ -1470,7 +1470,7 @@
608 addl d7,d7 |
609 addxl d6,d6 |
610 bcc 2f | if bit clear skip the following
611-#ifndef __mcf5200__
612+#ifndef __mcoldfire__
613 exg d7,a2 |
614 #else
615 movel d7,a4
616@@ -1481,7 +1481,7 @@
617 addxl d4,d2 |
618 addxl d7,d1 |
619 addxl d7,d0 |
620-#ifndef __mcf5200__
621+#ifndef __mcoldfire__
622 exg d7,a2 |
623 #else
624 movel d7,a4
625@@ -1489,7 +1489,7 @@
626 movel a4,a2
627 #endif
628 2:
629-#ifndef __mcf5200__
630+#ifndef __mcoldfire__
631 exg d7,a1 | put counter in d7
632 dbf d7,1b | decrement and branch
633 #else
634@@ -1501,7 +1501,7 @@
635 #endif
636
637 movel a3,d4 | restore exponent
638-#ifndef __mcf5200__
639+#ifndef __mcoldfire__
640 moveml sp@+,a2-a3
641 #else
642 movel sp@+,a4
643@@ -1520,7 +1520,7 @@
644 swap d3
645 movew d3,d2
646 movew IMM (0),d3
647-#ifndef __mcf5200__
648+#ifndef __mcoldfire__
649 lsrl IMM (1),d0
650 roxrl IMM (1),d1
651 roxrl IMM (1),d2
652@@ -1556,7 +1556,7 @@
653
654 btst IMM (DBL_MANT_DIG+1-32),d0
655 beq Lround$exit
656-#ifndef __mcf5200__
657+#ifndef __mcoldfire__
658 lsrl IMM (1),d0
659 roxrl IMM (1),d1
660 addw IMM (1),d4
661@@ -1592,7 +1592,7 @@
662 | NaN, in which case we return NaN.
663 Lmuldf$b$0:
664 movew IMM (MULTIPLY),d5
665-#ifndef __mcf5200__
666+#ifndef __mcoldfire__
667 exg d2,d0 | put b (==0) into d0-d1
668 exg d3,d1 | and a (with sign bit cleared) into d2-d3
669 #else
670@@ -1612,7 +1612,7 @@
671 bge Ld$inop | in case NaN or +/-INFINITY return NaN
672 lea SYM (_fpCCR),a0
673 movew IMM (0),a0@
674-#ifndef __mcf5200__
675+#ifndef __mcoldfire__
676 moveml sp@+,d2-d7
677 #else
678 moveml sp@,d2-d7
679@@ -1631,7 +1631,7 @@
680 andl d6,d0
681 1: addl d1,d1 | shift a left until bit 20 is set
682 addxl d0,d0 |
683-#ifndef __mcf5200__
684+#ifndef __mcoldfire__
685 subw IMM (1),d4 | and adjust exponent
686 #else
687 subl IMM (1),d4 | and adjust exponent
688@@ -1645,7 +1645,7 @@
689 andl d6,d2
690 1: addl d3,d3 | shift b left until bit 20 is set
691 addxl d2,d2 |
692-#ifndef __mcf5200__
693+#ifndef __mcoldfire__
694 subw IMM (1),d5 | and adjust exponent
695 #else
696 subql IMM (1),d5 | and adjust exponent
697@@ -1661,7 +1661,7 @@
698
699 | double __divdf3(double, double);
700 SYM (__divdf3):
701-#ifndef __mcf5200__
702+#ifndef __mcoldfire__
703 link a6,IMM (0)
704 moveml d2-d7,sp@-
705 #else
706@@ -1706,7 +1706,7 @@
707 andl d6,d0 | and isolate fraction
708 orl IMM (0x00100000),d0 | and put hidden bit back
709 swap d4 | I like exponents in the first byte
710-#ifndef __mcf5200__
711+#ifndef __mcoldfire__
712 lsrw IMM (4),d4 |
713 #else
714 lsrl IMM (4),d4 |
715@@ -1717,13 +1717,13 @@
716 andl d6,d2 |
717 orl IMM (0x00100000),d2
718 swap d5 |
719-#ifndef __mcf5200__
720+#ifndef __mcoldfire__
721 lsrw IMM (4),d5 |
722 #else
723 lsrl IMM (4),d5 |
724 #endif
725 Ldivdf$2: |
726-#ifndef __mcf5200__
727+#ifndef __mcoldfire__
728 subw d5,d4 | subtract exponents
729 addw IMM (D_BIAS),d4 | and add bias
730 #else
731@@ -1760,7 +1760,7 @@
732 bset d5,d6 | set the corresponding bit in d6
733 3: addl d1,d1 | shift a by 1
734 addxl d0,d0 |
735-#ifndef __mcf5200__
736+#ifndef __mcoldfire__
737 dbra d5,1b | and branch back
738 #else
739 subql IMM (1), d5
740@@ -1782,7 +1782,7 @@
741 bset d5,d7 | set the corresponding bit in d7
742 3: addl d1,d1 | shift a by 1
743 addxl d0,d0 |
744-#ifndef __mcf5200__
745+#ifndef __mcoldfire__
746 dbra d5,1b | and branch back
747 #else
748 subql IMM (1), d5
749@@ -1800,7 +1800,7 @@
750 beq 3f | if d0==d2 check d1 and d3
751 2: addl d1,d1 | shift a by 1
752 addxl d0,d0 |
753-#ifndef __mcf5200__
754+#ifndef __mcoldfire__
755 dbra d5,1b | and branch back
756 #else
757 subql IMM (1), d5
758@@ -1816,7 +1816,7 @@
759 | to it; if you don't do this the algorithm loses in some cases). '
760 movel IMM (0),d2
761 movel d2,d3
762-#ifndef __mcf5200__
763+#ifndef __mcoldfire__
764 subw IMM (DBL_MANT_DIG),d5
765 addw IMM (63),d5
766 cmpw IMM (31),d5
767@@ -1828,7 +1828,7 @@
768 bhi 2f
769 1: bset d5,d3
770 bra 5f
771-#ifndef __mcf5200__
772+#ifndef __mcoldfire__
773 subw IMM (32),d5
774 #else
775 subl IMM (32),d5
776@@ -1847,7 +1847,7 @@
777 | not set:
778 btst IMM (DBL_MANT_DIG-32+1),d0
779 beq 1f
780-#ifndef __mcf5200__
781+#ifndef __mcoldfire__
782 lsrl IMM (1),d0
783 roxrl IMM (1),d1
784 roxrl IMM (1),d2
785@@ -1897,7 +1897,7 @@
786 movel d0,d1 |
787 lea SYM (_fpCCR),a0 | clear exception flags
788 movew IMM (0),a0@ |
789-#ifndef __mcf5200__
790+#ifndef __mcoldfire__
791 moveml sp@+,d2-d7 |
792 #else
793 moveml sp@,d2-d7 |
794@@ -1945,7 +1945,7 @@
795 andl d6,d0
796 1: addl d1,d1 | shift a left until bit 20 is set
797 addxl d0,d0
798-#ifndef __mcf5200__
799+#ifndef __mcoldfire__
800 subw IMM (1),d4 | and adjust exponent
801 #else
802 subl IMM (1),d4 | and adjust exponent
803@@ -1959,7 +1959,7 @@
804 andl d6,d2
805 1: addl d3,d3 | shift b left until bit 20 is set
806 addxl d2,d2
807-#ifndef __mcf5200__
808+#ifndef __mcoldfire__
809 subw IMM (1),d5 | and adjust exponent
810 #else
811 subql IMM (1),d5 | and adjust exponent
812@@ -1974,7 +1974,7 @@
813 | so that 2^21 <= d0 < 2^22, and the exponent is in the lower byte of d4.
814
815 | First check for underlow in the exponent:
816-#ifndef __mcf5200__
817+#ifndef __mcoldfire__
818 cmpw IMM (-DBL_MANT_DIG-1),d4
819 #else
820 cmpl IMM (-DBL_MANT_DIG-1),d4
821@@ -1987,14 +1987,14 @@
822 movel d7,a0 |
823 movel IMM (0),d6 | use d6-d7 to collect bits flushed right
824 movel d6,d7 | use d6-d7 to collect bits flushed right
825-#ifndef __mcf5200__
826+#ifndef __mcoldfire__
827 cmpw IMM (1),d4 | if the exponent is less than 1 we
828 #else
829 cmpl IMM (1),d4 | if the exponent is less than 1 we
830 #endif
831 bge 2f | have to shift right (denormalize)
832 1:
833-#ifndef __mcf5200__
834+#ifndef __mcoldfire__
835 addw IMM (1),d4 | adjust the exponent
836 lsrl IMM (1),d0 | shift right once
837 roxrl IMM (1),d1 |
838@@ -2037,12 +2037,12 @@
839 | Now call the rounding routine (which takes care of denormalized numbers):
840 lea Lround$0,a0 | to return from rounding routine
841 lea SYM (_fpCCR),a1 | check the rounding mode
842-#ifdef __mcf5200__
843+#ifdef __mcoldfire__
844 clrl d6
845 #endif
846 movew a1@(6),d6 | rounding mode in d6
847 beq Lround$to$nearest
848-#ifndef __mcf5200__
849+#ifndef __mcoldfire__
850 cmpw IMM (ROUND_TO_PLUS),d6
851 #else
852 cmpl IMM (ROUND_TO_PLUS),d6
853@@ -2058,7 +2058,7 @@
854 | check again for underflow!). We have to check for overflow or for a
855 | denormalized number (which also signals underflow).
856 | Check for overflow (i.e., exponent >= 0x7ff).
857-#ifndef __mcf5200__
858+#ifndef __mcoldfire__
859 cmpw IMM (0x07ff),d4
860 #else
861 cmpl IMM (0x07ff),d4
862@@ -2069,14 +2069,14 @@
863 beq Ld$den
864 1:
865 | Put back the exponents and sign and return.
866-#ifndef __mcf5200__
867+#ifndef __mcoldfire__
868 lslw IMM (4),d4 | exponent back to fourth byte
869 #else
870 lsll IMM (4),d4 | exponent back to fourth byte
871 #endif
872 bclr IMM (DBL_MANT_DIG-32-1),d0
873 swap d0 | and put back exponent
874-#ifndef __mcf5200__
875+#ifndef __mcoldfire__
876 orw d4,d0 |
877 #else
878 orl d4,d0 |
879@@ -2086,7 +2086,7 @@
880
881 lea SYM (_fpCCR),a0
882 movew IMM (0),a0@
883-#ifndef __mcf5200__
884+#ifndef __mcoldfire__
885 moveml sp@+,d2-d7
886 #else
887 moveml sp@,d2-d7
888@@ -2102,7 +2102,7 @@
889
890 | double __negdf2(double, double);
891 SYM (__negdf2):
892-#ifndef __mcf5200__
893+#ifndef __mcoldfire__
894 link a6,IMM (0)
895 moveml d2-d7,sp@-
896 #else
897@@ -2128,7 +2128,7 @@
898 bra Ld$infty
899 1: lea SYM (_fpCCR),a0
900 movew IMM (0),a0@
901-#ifndef __mcf5200__
902+#ifndef __mcoldfire__
903 moveml sp@+,d2-d7
904 #else
905 moveml sp@,d2-d7
906@@ -2150,7 +2150,7 @@
907
908 | int __cmpdf2(double, double);
909 SYM (__cmpdf2):
910-#ifndef __mcf5200__
911+#ifndef __mcoldfire__
912 link a6,IMM (0)
913 moveml d2-d7,sp@- | save registers
914 #else
915@@ -2194,7 +2194,7 @@
916 tstl d6
917 bpl 1f
918 | If both are negative exchange them
919-#ifndef __mcf5200__
920+#ifndef __mcoldfire__
921 exg d0,d2
922 exg d1,d3
923 #else
924@@ -2217,7 +2217,7 @@
925 bne Lcmpdf$a$gt$b | |b| < |a|
926 | If we got here a == b.
927 movel IMM (EQUAL),d0
928-#ifndef __mcf5200__
929+#ifndef __mcoldfire__
930 moveml sp@+,d2-d7 | put back the registers
931 #else
932 moveml sp@,d2-d7
933@@ -2228,7 +2228,7 @@
934 rts
935 Lcmpdf$a$gt$b:
936 movel IMM (GREATER),d0
937-#ifndef __mcf5200__
938+#ifndef __mcoldfire__
939 moveml sp@+,d2-d7 | put back the registers
940 #else
941 moveml sp@,d2-d7
942@@ -2239,7 +2239,7 @@
943 rts
944 Lcmpdf$b$gt$a:
945 movel IMM (LESS),d0
946-#ifndef __mcf5200__
947+#ifndef __mcoldfire__
948 moveml sp@+,d2-d7 | put back the registers
949 #else
950 moveml sp@,d2-d7
951@@ -2287,7 +2287,7 @@
952 | Normalize shifting left until bit #DBL_MANT_DIG-32 is set or the exponent
953 | is one (remember that a denormalized number corresponds to an
954 | exponent of -D_BIAS+1).
955-#ifndef __mcf5200__
956+#ifndef __mcoldfire__
957 cmpw IMM (1),d4 | remember that the exponent is at least one
958 #else
959 cmpl IMM (1),d4 | remember that the exponent is at least one
960@@ -2297,7 +2297,7 @@
961 addxl d2,d2 |
962 addxl d1,d1 |
963 addxl d0,d0 |
964-#ifndef __mcf5200__
965+#ifndef __mcoldfire__
966 dbra d4,1b |
967 #else
968 subql IMM (1), d4
969@@ -2325,7 +2325,7 @@
970 addxl d2,d0
971 | Shift right once (because we used bit #DBL_MANT_DIG-32!).
972 2:
973-#ifndef __mcf5200__
974+#ifndef __mcoldfire__
975 lsrl IMM (1),d0
976 roxrl IMM (1),d1
977 #else
978@@ -2340,7 +2340,7 @@
979 | 'fraction overflow' ...).
980 btst IMM (DBL_MANT_DIG-32),d0
981 beq 1f
982-#ifndef __mcf5200__
983+#ifndef __mcoldfire__
984 lsrl IMM (1),d0
985 roxrl IMM (1),d1
986 addw IMM (1),d4
987@@ -2491,7 +2491,7 @@
988
989 | float __addsf3(float, float);
990 SYM (__addsf3):
991-#ifndef __mcf5200__
992+#ifndef __mcoldfire__
993 link a6,IMM (0) | everything will be done in registers
994 moveml d2-d7,sp@- | save all data registers but d0-d1
995 #else
996@@ -2551,7 +2551,7 @@
997 | same, and put the largest exponent in d6. Note that we are using two
998 | registers for each number (see the discussion by D. Knuth in "Seminumerical
999 | Algorithms").
1000-#ifndef __mcf5200__
1001+#ifndef __mcoldfire__
1002 cmpw d6,d7 | compare exponents
1003 #else
1004 cmpl d6,d7 | compare exponents
1005@@ -2561,32 +2561,32 @@
1006 1:
1007 subl d6,d7 | keep the largest exponent
1008 negl d7
1009-#ifndef __mcf5200__
1010+#ifndef __mcoldfire__
1011 lsrw IMM (8),d7 | put difference in lower byte
1012 #else
1013 lsrl IMM (8),d7 | put difference in lower byte
1014 #endif
1015 | if difference is too large we don't shift (actually, we can just exit) '
1016-#ifndef __mcf5200__
1017+#ifndef __mcoldfire__
1018 cmpw IMM (FLT_MANT_DIG+2),d7
1019 #else
1020 cmpl IMM (FLT_MANT_DIG+2),d7
1021 #endif
1022 bge Laddsf$b$small
1023-#ifndef __mcf5200__
1024+#ifndef __mcoldfire__
1025 cmpw IMM (16),d7 | if difference >= 16 swap
1026 #else
1027 cmpl IMM (16),d7 | if difference >= 16 swap
1028 #endif
1029 bge 4f
1030 2:
1031-#ifndef __mcf5200__
1032+#ifndef __mcoldfire__
1033 subw IMM (1),d7
1034 #else
1035 subql IMM (1), d7
1036 #endif
1037 3:
1038-#ifndef __mcf5200__
1039+#ifndef __mcoldfire__
1040 lsrl IMM (1),d2 | shift right second operand
1041 roxrl IMM (1),d3
1042 dbra d7,3b
1043@@ -2605,7 +2605,7 @@
1044 swap d3
1045 movew d3,d2
1046 swap d2
1047-#ifndef __mcf5200__
1048+#ifndef __mcoldfire__
1049 subw IMM (16),d7
1050 #else
1051 subl IMM (16),d7
1052@@ -2613,7 +2613,7 @@
1053 bne 2b | if still more bits, go back to normal case
1054 bra Laddsf$3
1055 5:
1056-#ifndef __mcf5200__
1057+#ifndef __mcoldfire__
1058 exg d6,d7 | exchange the exponents
1059 #else
1060 eorl d6,d7
1061@@ -2622,32 +2622,32 @@
1062 #endif
1063 subl d6,d7 | keep the largest exponent
1064 negl d7 |
1065-#ifndef __mcf5200__
1066+#ifndef __mcoldfire__
1067 lsrw IMM (8),d7 | put difference in lower byte
1068 #else
1069 lsrl IMM (8),d7 | put difference in lower byte
1070 #endif
1071 | if difference is too large we don't shift (and exit!) '
1072-#ifndef __mcf5200__
1073+#ifndef __mcoldfire__
1074 cmpw IMM (FLT_MANT_DIG+2),d7
1075 #else
1076 cmpl IMM (FLT_MANT_DIG+2),d7
1077 #endif
1078 bge Laddsf$a$small
1079-#ifndef __mcf5200__
1080+#ifndef __mcoldfire__
1081 cmpw IMM (16),d7 | if difference >= 16 swap
1082 #else
1083 cmpl IMM (16),d7 | if difference >= 16 swap
1084 #endif
1085 bge 8f
1086 6:
1087-#ifndef __mcf5200__
1088+#ifndef __mcoldfire__
1089 subw IMM (1),d7
1090 #else
1091 subl IMM (1),d7
1092 #endif
1093 7:
1094-#ifndef __mcf5200__
1095+#ifndef __mcoldfire__
1096 lsrl IMM (1),d0 | shift right first operand
1097 roxrl IMM (1),d1
1098 dbra d7,7b
1099@@ -2666,7 +2666,7 @@
1100 swap d1
1101 movew d1,d0
1102 swap d0
1103-#ifndef __mcf5200__
1104+#ifndef __mcoldfire__
1105 subw IMM (16),d7
1106 #else
1107 subl IMM (16),d7
1108@@ -2679,7 +2679,7 @@
1109
1110 Laddsf$3:
1111 | Here we have to decide whether to add or subtract the numbers
1112-#ifndef __mcf5200__
1113+#ifndef __mcoldfire__
1114 exg d6,a0 | get signs back
1115 exg d7,a1 | and save the exponents
1116 #else
1117@@ -2696,7 +2696,7 @@
1118 | numbers
1119
1120 | Here we have both positive or both negative
1121-#ifndef __mcf5200__
1122+#ifndef __mcoldfire__
1123 exg d6,a0 | now we have the exponent in d6
1124 #else
1125 movel d6,d4
1126@@ -2713,7 +2713,7 @@
1127 | Put the exponent, in the first byte, in d2, to use the "standard" rounding
1128 | routines:
1129 movel d6,d2
1130-#ifndef __mcf5200__
1131+#ifndef __mcoldfire__
1132 lsrw IMM (8),d2
1133 #else
1134 lsrl IMM (8),d2
1135@@ -2725,7 +2725,7 @@
1136 | one more bit we check this:
1137 btst IMM (FLT_MANT_DIG+1),d0
1138 beq 1f
1139-#ifndef __mcf5200__
1140+#ifndef __mcoldfire__
1141 lsrl IMM (1),d0
1142 roxrl IMM (1),d1
1143 #else
1144@@ -2739,12 +2739,12 @@
1145 1:
1146 lea Laddsf$4,a0 | to return from rounding routine
1147 lea SYM (_fpCCR),a1 | check the rounding mode
1148-#ifdef __mcf5200__
1149+#ifdef __mcoldfire__
1150 clrl d6
1151 #endif
1152 movew a1@(6),d6 | rounding mode in d6
1153 beq Lround$to$nearest
1154-#ifndef __mcf5200__
1155+#ifndef __mcoldfire__
1156 cmpw IMM (ROUND_TO_PLUS),d6
1157 #else
1158 cmpl IMM (ROUND_TO_PLUS),d6
1159@@ -2754,14 +2754,14 @@
1160 bra Lround$to$plus
1161 Laddsf$4:
1162 | Put back the exponent, but check for overflow.
1163-#ifndef __mcf5200__
1164+#ifndef __mcoldfire__
1165 cmpw IMM (0xff),d2
1166 #else
1167 cmpl IMM (0xff),d2
1168 #endif
1169 bhi 1f
1170 bclr IMM (FLT_MANT_DIG-1),d0
1171-#ifndef __mcf5200__
1172+#ifndef __mcoldfire__
1173 lslw IMM (7),d2
1174 #else
1175 lsll IMM (7),d2
1176@@ -2787,7 +2787,7 @@
1177 negl d1
1178 negxl d0
1179 1:
1180-#ifndef __mcf5200__
1181+#ifndef __mcoldfire__
1182 exg d2,a0 | now we have the exponent in d2
1183 lsrw IMM (8),d2 | put it in the first byte
1184 #else
1185@@ -2804,12 +2804,12 @@
1186 | the rounding routines themselves.
1187 lea Lsubsf$1,a0 | to return from rounding routine
1188 lea SYM (_fpCCR),a1 | check the rounding mode
1189-#ifdef __mcf5200__
1190+#ifdef __mcoldfire__
1191 clrl d6
1192 #endif
1193 movew a1@(6),d6 | rounding mode in d6
1194 beq Lround$to$nearest
1195-#ifndef __mcf5200__
1196+#ifndef __mcoldfire__
1197 cmpw IMM (ROUND_TO_PLUS),d6
1198 #else
1199 cmpl IMM (ROUND_TO_PLUS),d6
1200@@ -2820,7 +2820,7 @@
1201 Lsubsf$1:
1202 | Put back the exponent (we can't have overflow!). '
1203 bclr IMM (FLT_MANT_DIG-1),d0
1204-#ifndef __mcf5200__
1205+#ifndef __mcoldfire__
1206 lslw IMM (7),d2
1207 #else
1208 lsll IMM (7),d2
1209@@ -2836,7 +2836,7 @@
1210 movel a6@(12),d0
1211 lea SYM (_fpCCR),a0
1212 movew IMM (0),a0@
1213-#ifndef __mcf5200__
1214+#ifndef __mcoldfire__
1215 moveml sp@+,d2-d7 | restore data registers
1216 #else
1217 moveml sp@,d2-d7
1218@@ -2850,7 +2850,7 @@
1219 movel a6@(8),d0
1220 lea SYM (_fpCCR),a0
1221 movew IMM (0),a0@
1222-#ifndef __mcf5200__
1223+#ifndef __mcoldfire__
1224 moveml sp@+,d2-d7 | restore data registers
1225 #else
1226 moveml sp@,d2-d7
1227@@ -2908,7 +2908,7 @@
1228 lea SYM (_fpCCR),a0
1229 movew IMM (0),a0@
1230 orl d7,d0 | put sign bit
1231-#ifndef __mcf5200__
1232+#ifndef __mcoldfire__
1233 moveml sp@+,d2-d7 | restore data registers
1234 #else
1235 moveml sp@,d2-d7
1236@@ -2975,7 +2975,7 @@
1237
1238 | float __mulsf3(float, float);
1239 SYM (__mulsf3):
1240-#ifndef __mcf5200__
1241+#ifndef __mcoldfire__
1242 link a6,IMM (0)
1243 moveml d2-d7,sp@-
1244 #else
1245@@ -3010,7 +3010,7 @@
1246 andl d5,d0 | and isolate fraction
1247 orl d4,d0 | and put hidden bit back
1248 swap d2 | I like exponents in the first byte
1249-#ifndef __mcf5200__
1250+#ifndef __mcoldfire__
1251 lsrw IMM (7),d2 |
1252 #else
1253 lsrl IMM (7),d2 |
1254@@ -3021,13 +3021,13 @@
1255 andl d5,d1 |
1256 orl d4,d1 |
1257 swap d3 |
1258-#ifndef __mcf5200__
1259+#ifndef __mcoldfire__
1260 lsrw IMM (7),d3 |
1261 #else
1262 lsrl IMM (7),d3 |
1263 #endif
1264 Lmulsf$2: |
1265-#ifndef __mcf5200__
1266+#ifndef __mcoldfire__
1267 addw d3,d2 | add exponents
1268 subw IMM (F_BIAS+1),d2 | and subtract bias (plus one)
1269 #else
1270@@ -3060,7 +3060,7 @@
1271 addl d5,d1 | add a
1272 addxl d4,d0
1273 2:
1274-#ifndef __mcf5200__
1275+#ifndef __mcoldfire__
1276 dbf d3,1b | loop back
1277 #else
1278 subql IMM (1),d3
1279@@ -3070,7 +3070,7 @@
1280 | Now we have the product in d0-d1, with bit (FLT_MANT_DIG - 1) + FLT_MANT_DIG
1281 | (mod 32) of d0 set. The first thing to do now is to normalize it so bit
1282 | FLT_MANT_DIG is set (to do the rounding).
1283-#ifndef __mcf5200__
1284+#ifndef __mcoldfire__
1285 rorl IMM (6),d1
1286 swap d1
1287 movew d1,d3
1288@@ -3089,7 +3089,7 @@
1289 lsll IMM (8),d0
1290 addl d0,d0
1291 addl d0,d0
1292-#ifndef __mcf5200__
1293+#ifndef __mcoldfire__
1294 orw d3,d0
1295 #else
1296 orl d3,d0
1297@@ -3099,7 +3099,7 @@
1298
1299 btst IMM (FLT_MANT_DIG+1),d0
1300 beq Lround$exit
1301-#ifndef __mcf5200__
1302+#ifndef __mcoldfire__
1303 lsrl IMM (1),d0
1304 roxrl IMM (1),d1
1305 addw IMM (1),d2
1306@@ -3143,7 +3143,7 @@
1307 bge Lf$inop | if b is +/-INFINITY or NaN return NaN
1308 lea SYM (_fpCCR),a0 | else return zero
1309 movew IMM (0),a0@ |
1310-#ifndef __mcf5200__
1311+#ifndef __mcoldfire__
1312 moveml sp@+,d2-d7 |
1313 #else
1314 moveml sp@,d2-d7
1315@@ -3161,7 +3161,7 @@
1316 movel IMM (1),d2
1317 andl d5,d0
1318 1: addl d0,d0 | shift a left (until bit 23 is set)
1319-#ifndef __mcf5200__
1320+#ifndef __mcoldfire__
1321 subw IMM (1),d2 | and adjust exponent
1322 #else
1323 subql IMM (1),d2 | and adjust exponent
1324@@ -3174,7 +3174,7 @@
1325 movel IMM (1),d3
1326 andl d5,d1
1327 1: addl d1,d1 | shift b left until bit 23 is set
1328-#ifndef __mcf5200__
1329+#ifndef __mcoldfire__
1330 subw IMM (1),d3 | and adjust exponent
1331 #else
1332 subl IMM (1),d3 | and adjust exponent
1333@@ -3189,7 +3189,7 @@
1334
1335 | float __divsf3(float, float);
1336 SYM (__divsf3):
1337-#ifndef __mcf5200__
1338+#ifndef __mcoldfire__
1339 link a6,IMM (0)
1340 moveml d2-d7,sp@-
1341 #else
1342@@ -3226,7 +3226,7 @@
1343 andl d5,d0 | and isolate fraction
1344 orl d4,d0 | and put hidden bit back
1345 swap d2 | I like exponents in the first byte
1346-#ifndef __mcf5200__
1347+#ifndef __mcoldfire__
1348 lsrw IMM (7),d2 |
1349 #else
1350 lsrl IMM (7),d2 |
1351@@ -3237,13 +3237,13 @@
1352 andl d5,d1 |
1353 orl d4,d1 |
1354 swap d3 |
1355-#ifndef __mcf5200__
1356+#ifndef __mcoldfire__
1357 lsrw IMM (7),d3 |
1358 #else
1359 lsrl IMM (7),d3 |
1360 #endif
1361 Ldivsf$2: |
1362-#ifndef __mcf5200__
1363+#ifndef __mcoldfire__
1364 subw d3,d2 | subtract exponents
1365 addw IMM (F_BIAS),d2 | and add bias
1366 #else
1367@@ -3270,7 +3270,7 @@
1368 subl d1,d0 | if a >= b a <-- a-b
1369 beq 3f | if a is zero, exit
1370 2: addl d0,d0 | multiply a by 2
1371-#ifndef __mcf5200__
1372+#ifndef __mcoldfire__
1373 dbra d3,1b
1374 #else
1375 subql IMM (1),d3
1376@@ -3282,7 +3282,7 @@
1377 1: cmpl d0,d1
1378 ble 2f
1379 addl d0,d0
1380-#ifndef __mcf5200__
1381+#ifndef __mcoldfire__
1382 dbra d3,1b
1383 #else
1384 subql IMM(1),d3
1385@@ -3291,7 +3291,7 @@
1386 movel IMM (0),d1
1387 bra 3f
1388 2: movel IMM (0),d1
1389-#ifndef __mcf5200__
1390+#ifndef __mcoldfire__
1391 subw IMM (FLT_MANT_DIG),d3
1392 addw IMM (31),d3
1393 #else
1394@@ -3309,7 +3309,7 @@
1395 btst IMM (FLT_MANT_DIG+1),d0
1396 beq 1f | if it is not set, then bit 24 is set
1397 lsrl IMM (1),d0 |
1398-#ifndef __mcf5200__
1399+#ifndef __mcoldfire__
1400 addw IMM (1),d2 |
1401 #else
1402 addl IMM (1),d2 |
1403@@ -3343,7 +3343,7 @@
1404 movel IMM (0),d0 | else return zero
1405 lea SYM (_fpCCR),a0 |
1406 movew IMM (0),a0@ |
1407-#ifndef __mcf5200__
1408+#ifndef __mcoldfire__
1409 moveml sp@+,d2-d7 |
1410 #else
1411 moveml sp@,d2-d7 |
1412@@ -3375,7 +3375,7 @@
1413 movel IMM (1),d2
1414 andl d5,d0
1415 1: addl d0,d0 | shift a left until bit FLT_MANT_DIG-1 is set
1416-#ifndef __mcf5200__
1417+#ifndef __mcoldfire__
1418 subw IMM (1),d2 | and adjust exponent
1419 #else
1420 subl IMM (1),d2 | and adjust exponent
1421@@ -3388,7 +3388,7 @@
1422 movel IMM (1),d3
1423 andl d5,d1
1424 1: addl d1,d1 | shift b left until bit FLT_MANT_DIG is set
1425-#ifndef __mcf5200__
1426+#ifndef __mcoldfire__
1427 subw IMM (1),d3 | and adjust exponent
1428 #else
1429 subl IMM (1),d3 | and adjust exponent
1430@@ -3401,7 +3401,7 @@
1431 | This is a common exit point for __mulsf3 and __divsf3.
1432
1433 | First check for underlow in the exponent:
1434-#ifndef __mcf5200__
1435+#ifndef __mcoldfire__
1436 cmpw IMM (-FLT_MANT_DIG-1),d2
1437 #else
1438 cmpl IMM (-FLT_MANT_DIG-1),d2
1439@@ -3412,14 +3412,14 @@
1440 | exponent until it becomes 1 or the fraction is zero (in the latter case
1441 | we signal underflow and return zero).
1442 movel IMM (0),d6 | d6 is used temporarily
1443-#ifndef __mcf5200__
1444+#ifndef __mcoldfire__
1445 cmpw IMM (1),d2 | if the exponent is less than 1 we
1446 #else
1447 cmpl IMM (1),d2 | if the exponent is less than 1 we
1448 #endif
1449 bge 2f | have to shift right (denormalize)
1450 1:
1451-#ifndef __mcf5200__
1452+#ifndef __mcoldfire__
1453 addw IMM (1),d2 | adjust the exponent
1454 lsrl IMM (1),d0 | shift right once
1455 roxrl IMM (1),d1 |
1456@@ -3446,12 +3446,12 @@
1457 | Now call the rounding routine (which takes care of denormalized numbers):
1458 lea Lround$0,a0 | to return from rounding routine
1459 lea SYM (_fpCCR),a1 | check the rounding mode
1460-#ifdef __mcf5200__
1461+#ifdef __mcoldfire__
1462 clrl d6
1463 #endif
1464 movew a1@(6),d6 | rounding mode in d6
1465 beq Lround$to$nearest
1466-#ifndef __mcf5200__
1467+#ifndef __mcoldfire__
1468 cmpw IMM (ROUND_TO_PLUS),d6
1469 #else
1470 cmpl IMM (ROUND_TO_PLUS),d6
1471@@ -3467,7 +3467,7 @@
1472 | check again for underflow!). We have to check for overflow or for a
1473 | denormalized number (which also signals underflow).
1474 | Check for overflow (i.e., exponent >= 255).
1475-#ifndef __mcf5200__
1476+#ifndef __mcoldfire__
1477 cmpw IMM (0x00ff),d2
1478 #else
1479 cmpl IMM (0x00ff),d2
1480@@ -3478,14 +3478,14 @@
1481 beq Lf$den
1482 1:
1483 | Put back the exponents and sign and return.
1484-#ifndef __mcf5200__
1485+#ifndef __mcoldfire__
1486 lslw IMM (7),d2 | exponent back to fourth byte
1487 #else
1488 lsll IMM (7),d2 | exponent back to fourth byte
1489 #endif
1490 bclr IMM (FLT_MANT_DIG-1),d0
1491 swap d0 | and put back exponent
1492-#ifndef __mcf5200__
1493+#ifndef __mcoldfire__
1494 orw d2,d0 |
1495 #else
1496 orl d2,d0
1497@@ -3495,7 +3495,7 @@
1498
1499 lea SYM (_fpCCR),a0
1500 movew IMM (0),a0@
1501-#ifndef __mcf5200__
1502+#ifndef __mcoldfire__
1503 moveml sp@+,d2-d7
1504 #else
1505 moveml sp@,d2-d7
1506@@ -3514,7 +3514,7 @@
1507
1508 | float __negsf2(float);
1509 SYM (__negsf2):
1510-#ifndef __mcf5200__
1511+#ifndef __mcoldfire__
1512 link a6,IMM (0)
1513 moveml d2-d7,sp@-
1514 #else
1515@@ -3536,7 +3536,7 @@
1516 bra Lf$infty
1517 1: lea SYM (_fpCCR),a0
1518 movew IMM (0),a0@
1519-#ifndef __mcf5200__
1520+#ifndef __mcoldfire__
1521 moveml sp@+,d2-d7
1522 #else
1523 moveml sp@,d2-d7
1524@@ -3558,7 +3558,7 @@
1525
1526 | int __cmpsf2(float, float);
1527 SYM (__cmpsf2):
1528-#ifndef __mcf5200__
1529+#ifndef __mcoldfire__
1530 link a6,IMM (0)
1531 moveml d2-d7,sp@- | save registers
1532 #else
1533@@ -3595,7 +3595,7 @@
1534 tstl d6
1535 bpl 1f
1536 | If both are negative exchange them
1537-#ifndef __mcf5200__
1538+#ifndef __mcoldfire__
1539 exg d0,d1
1540 #else
1541 movel d0,d7
1542@@ -3610,7 +3610,7 @@
1543 bne Lcmpsf$a$gt$b | |b| < |a|
1544 | If we got here a == b.
1545 movel IMM (EQUAL),d0
1546-#ifndef __mcf5200__
1547+#ifndef __mcoldfire__
1548 moveml sp@+,d2-d7 | put back the registers
1549 #else
1550 moveml sp@,d2-d7
1551@@ -3619,7 +3619,7 @@
1552 rts
1553 Lcmpsf$a$gt$b:
1554 movel IMM (GREATER),d0
1555-#ifndef __mcf5200__
1556+#ifndef __mcoldfire__
1557 moveml sp@+,d2-d7 | put back the registers
1558 #else
1559 moveml sp@,d2-d7
1560@@ -3630,7 +3630,7 @@
1561 rts
1562 Lcmpsf$b$gt$a:
1563 movel IMM (LESS),d0
1564-#ifndef __mcf5200__
1565+#ifndef __mcoldfire__
1566 moveml sp@+,d2-d7 | put back the registers
1567 #else
1568 moveml sp@,d2-d7
1569@@ -3668,7 +3668,7 @@
1570 | Normalize shifting left until bit #FLT_MANT_DIG is set or the exponent
1571 | is one (remember that a denormalized number corresponds to an
1572 | exponent of -F_BIAS+1).
1573-#ifndef __mcf5200__
1574+#ifndef __mcoldfire__
1575 cmpw IMM (1),d2 | remember that the exponent is at least one
1576 #else
1577 cmpl IMM (1),d2 | remember that the exponent is at least one
1578@@ -3676,7 +3676,7 @@
1579 beq 2f | an exponent of one means denormalized
1580 addl d1,d1 | else shift and adjust the exponent
1581 addxl d0,d0 |
1582-#ifndef __mcf5200__
1583+#ifndef __mcoldfire__
1584 dbra d2,1b |
1585 #else
1586 subql IMM (1),d2
1587@@ -3705,7 +3705,7 @@
1588 btst IMM (FLT_MANT_DIG),d0
1589 beq 1f
1590 lsrl IMM (1),d0
1591-#ifndef __mcf5200__
1592+#ifndef __mcoldfire__
1593 addw IMM (1),d2
1594 #else
1595 addql IMM (1),d2
1596diff -Nru gcc-3.3.1.orig/gcc/config/m68k/linux.h gcc-3.3.1/gcc/config/m68k/linux.h
1597--- gcc-3.3.1.orig/gcc/config/m68k/linux.h 2003-01-28 23:18:15.000000000 +0100
1598+++ gcc-3.3.1/gcc/config/m68k/linux.h 2003-07-25 00:25:30.000000000 +0200
1599@@ -196,7 +196,7 @@
1600 #undef ASM_OUTPUT_CASE_LABEL
1601 #define ASM_RETURN_CASE_JUMP \
1602 do { \
1603- if (TARGET_5200) \
1604+ if (TARGET_COLDFIRE) \
1605 { \
1606 if (ADDRESS_REG_P (operands[0])) \
1607 return "jmp %%pc@(2,%0:l)"; \
1608diff -Nru gcc-3.3.1.orig/gcc/config/m68k/m68k-none.h gcc-3.3.1/gcc/config/m68k/m68k-none.h
1609--- gcc-3.3.1.orig/gcc/config/m68k/m68k-none.h 1998-12-16 22:06:54.000000000 +0100
1610+++ gcc-3.3.1/gcc/config/m68k/m68k-none.h 2003-07-25 00:25:30.000000000 +0200
1611@@ -97,7 +97,7 @@
1612 #undef CPP_FPU_SPEC
1613 #if TARGET_DEFAULT & MASK_68881
1614 #define CPP_FPU_SPEC "\
1615-%{!mc68000:%{!m68000:%{!m68302:%{!mcpu32:%{!m68332:%{!m5200:%{!msoft-float:%{!mno-68881:%{!mfpa:%{!msky:-D__HAVE_68881__ }}}}}}}}}} \
1616+%{!mc68000:%{!m68000:%{!m68302:%{!mcpu32:%{!m68332:%{!m5200:%{!m5206e:%{!m528x:%{!m5307:%{!m5407:%{!msoft-float:%{!mno-68881:%{!mfpa:%{!msky:-D__HAVE_68881__ }}}}}}}}}}}}}} \
1617 %{m68881:-D__HAVE_68881__ }%{mfpa:-D__HAVE_FPA__ }%{msky:-D__HAVE_SKY__ }"
1618 #else
1619 /* This can't currently happen, but we code it anyway to show how it's done. */
1620@@ -125,7 +125,12 @@
1621 -m68302: define mc68302
1622 -m68332: define mc68332 mcpu32
1623 -mcpu32: define mcpu32
1624- -m5200: define mcf5200
1625+ -m5200: define mcoldfire mcf5200
1626+ -m5206e: define mcoldfire mcf5200 mcf5206e
1627+ -m528x: define mcoldfire mc5200 mc528x
1628+ -m5307: define mcoldfire mc5300 mc5307
1629+ -m5407: define mcoldfire mc5400 mc5407
1630+
1631 default: define as above appropriately
1632
1633 GCC won't automatically add __'d versions, we have to mention them
1634@@ -133,9 +138,13 @@
1635
1636 #undef CPP_SPEC
1637 #define CPP_SPEC "\
1638-%(cpp_fpu)%{!ansi:%{m68302:-Dmc68302 }%{m68010:-Dmc68010 }%{m68020:-Dmc68020 }%{mc68020:-Dmc68020 }%{m68030:-Dmc68030 }%{m68040:-Dmc68040 }%{m68020-40:-Dmc68020 -Dmc68030 -Dmc68040 }%{m68020-60:-Dmc68020 -Dmc68030 -Dmc68040 -Dmc68060 }%{m68060:-Dmc68060 }%{mcpu32:-Dmcpu32 } %{m68332:-Dmc68332 -Dmcpu32 }%{m5200:-Dmcf5200 }} \
1639-%{m68302:-D__mc68302__ -D__mc68302 }%{m68010:-D__mc68010__ -D__mc68010 }%{m68020:-D__mc68020__ -D__mc68020 }%{mc68020:-D__mc68020__ -D__mc68020 }%{m68030:-D__mc68030__ -D__mc68030 }%{m68040:-D__mc68040__ -D__mc68040 }%{m68020-40:-D__mc68020__ -D__mc68030__ -D__mc68040__ -D__mc68020 -D__mc68030 -D__mc68040 }%{m68020-60:-D__mc68020__ -D__mc68030__ -D__mc68040__ -D__mc68020 -D__mc68030 -D__mc68040 -D__mc68060__ -D__mc68060 }%{m68060:-D__mc68060__ -D__mc68060 }%{mcpu32:-D__mcpu32__ -D__mcpu32 }%{m68332:-D__mc68332__ -D__mc68332 -D__mcpu32__ -D__mcpu32 }%{m5200:-D__mcf5200__ -D__mcf5200 } \
1640-%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32: %{!m68332:%{!m5200:%(cpp_cpu_default)}}}}}}}}}}}}}} \
1641+%(cpp_fpu)%{!ansi:%{m68302:-Dmc68302 }%{m68010:-Dmc68010 }%{m68020:-Dmc68020 }%{mc68020:-Dmc68020 }%{m68030:-Dmc68030 }%{m68040:-Dmc68040 }%{m68020-40:-Dmc68020 -Dmc68030 -Dmc68040 }%{m68020-60:-Dmc68020 -Dmc68030 -Dmc68040 -Dmc68060 }%{m68060:-Dmc68060 }%{mcpu32:-Dmcpu32 } %{m68332:-Dmc68332 -Dmcpu32 }%{m5200:-Dmcoldfire -Dmcf5200 }%{m5206e:-Dmcoldfire -Dmcf5200 -Dmcf5206e }%{m528x:-Dmcoldfire -Dmcf5200 -Dmcf528x }%{m5307:-Dmcoldfire -Dmcf5300 -Dmcf5307 }%{m5407: -Dmcoldfire -Dmcf5400 -Dmcf5407 }} \
1642+%{m68302:-D__mc68302__ -D__mc68302 }%{m68010:-D__mc68010__ -D__mc68010 }%{m68020:-D__mc68020__ -D__mc68020 }%{mc68020:-D__mc68020__ -D__mc68020 }%{m68030:-D__mc68030__ -D__mc68030 }%{m68040:-D__mc68040__ -D__mc68040 }%{m68020-40:-D__mc68020__ -D__mc68030__ -D__mc68040__ -D__mc68020 -D__mc68030 -D__mc68040 }%{m68020-60:-D__mc68020__ -D__mc68030__ -D__mc68040__ -D__mc68020 -D__mc68030 -D__mc68040 -D__mc68060__ -D__mc68060 }%{m68060:-D__mc68060__ -D__mc68060 }%{mcpu32:-D__mcpu32__ -D__mcpu32 }%{m68332:-D__mc68332__ -D__mc68332 -D__mcpu32__ -D__mcpu32 }%{m5200:-D__mcf5200__ -D__mcf5200 -D__mcoldfire__ } \
1643+%{m5206e:-D__mcoldfire__ -D__mcf5200__ -D__mcf5200 -D__mcf5206e__ -D__mcf5206e } \
1644+%{m528x:-D__mcoldfire__ -D__mcf5200__ -D__mcf5200 -D__mcf528x__ -D__mcf528x } \
1645+%{m5307:-D__mcoldfire__ -D__mcf5300__ -D__mcf5300 -D__mcf5307__ -D__mcf5307 } \
1646+%{m5407:-D__mcoldfire__ -D__mcf5400__ -D__mcf5400 -D__mcf5407__ -D__mcf5407 } \
1647+%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32: %{!m68332:%{!m5200:%{!m5206e:%{!m528x:%{!m5307:%{!m5407:%(cpp_cpu_default)}}}}}}}}}}}}}}}}}} \
1648 %(cpp_subtarget) \
1649 "
1650
1651@@ -143,7 +152,7 @@
1652
1653 #undef ASM_SPEC
1654 #define ASM_SPEC "\
1655-%{m68851}%{mno-68851}%{m68881}%{mno-68881}%{msoft-float:-mno-68881 }%{m68000}%{m68302}%{mc68000}%{m68010}%{m68020}%{mc68020}%{m68030}%{m68040}%{m68020-40:-mc68040 }%{m68020-60:-mc68040 }%{m68060}%{mcpu32}%{m68332}%{m5200}%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32:%{!m68332:%{!m5200:%(asm_cpu_default) }}}}}}}}}}}}}} \
1656+%{m68851}%{mno-68851}%{m68881}%{mno-68881}%{msoft-float:-mno-68881 }%{m68000}%{m68302}%{mc68000}%{m68010}%{m68020}%{mc68020}%{m68030}%{m68040}%{m68020-40:-mc68040 }%{m68020-60:-mc68040 }%{m68060}%{mcpu32}%{m68332}%{m5200}%{m5206e}%{m528x}%{m5307}%{m5407}%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32:%{!m68332:%{!m5200:%{!m5206e:%{!m528x:%{!m5307:%{!m5407:%(asm_cpu_default) }}}}}}}}}}}}}}}}}} \
1657 "
1658
1659 /* cc1/cc1plus always receives all the -m flags. If the specs strings above
1660diff -Nru gcc-3.3.1.orig/gcc/config/m68k/m68k.c gcc-3.3.1/gcc/config/m68k/m68k.c
1661--- gcc-3.3.1.orig/gcc/config/m68k/m68k.c 2003-06-28 02:27:04.000000000 +0200
1662+++ gcc-3.3.1/gcc/config/m68k/m68k.c 2003-07-25 00:25:30.000000000 +0200
1663@@ -397,7 +397,7 @@
1664 #ifndef NO_ADDSUB_Q
1665 if (fsize + 4 <= 8)
1666 {
1667- if (!TARGET_5200)
1668+ if (!TARGET_COLDFIRE)
1669 {
1670 /* asm_fprintf() cannot handle %. */
1671 #ifdef MOTOROLA
1672@@ -595,7 +595,7 @@
1673 }
1674 else if (mask)
1675 {
1676- if (TARGET_5200)
1677+ if (TARGET_COLDFIRE)
1678 {
1679 /* The coldfire does not support the predecrement form of the
1680 movml instruction, so we must adjust the stack pointer and
1681@@ -872,7 +872,7 @@
1682 #endif
1683 fsize = 0, big = 1;
1684 }
1685- if (TARGET_5200 || nregs <= 2)
1686+ if (TARGET_COLDFIRE || nregs <= 2)
1687 {
1688 /* Restore each separately in the same order moveml does.
1689 Using two movel instructions instead of a single moveml
1690@@ -1048,7 +1048,7 @@
1691 #ifndef NO_ADDSUB_Q
1692 if (fsize + 4 <= 8)
1693 {
1694- if (!TARGET_5200)
1695+ if (!TARGET_COLDFIRE)
1696 {
1697 #ifdef MOTOROLA
1698 asm_fprintf (stream, "\taddq.w %0I%d,%Rsp\n", fsize + 4);
1699@@ -1343,7 +1343,7 @@
1700 }
1701 else
1702 {
1703- if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (loperands[0]))
1704+ if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[0]))
1705 output_asm_insn ("tst%.l %0", loperands);
1706 else
1707 {
1708@@ -1360,7 +1360,7 @@
1709 output_asm_insn ("jne %l4", loperands);
1710 #endif
1711
1712- if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (loperands[1]))
1713+ if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[1]))
1714 output_asm_insn ("tst%.l %1", loperands);
1715 else
1716 {
1717@@ -1678,7 +1678,7 @@
1718
1719 /* The Coldfire doesn't have byte or word operations. */
1720 /* FIXME: This may not be useful for the m68060 either */
1721- if (!TARGET_5200)
1722+ if (!TARGET_COLDFIRE)
1723 {
1724 /* if -256 < N < 256 but N is not in range for a moveq
1725 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1726@@ -1783,7 +1783,7 @@
1727 || GET_CODE (operands[0]) == MEM)
1728 /* clr insns on 68000 read before writing.
1729 This isn't so on the 68010, but we have no TARGET_68010. */
1730- && ((TARGET_68020 || TARGET_5200)
1731+ && ((TARGET_68020 || TARGET_COLDFIRE)
1732 || !(GET_CODE (operands[0]) == MEM
1733 && MEM_VOLATILE_P (operands[0]))))
1734 return "clr%.l %0";
1735@@ -1833,7 +1833,7 @@
1736 || GET_CODE (operands[0]) == MEM)
1737 /* clr insns on 68000 read before writing.
1738 This isn't so on the 68010, but we have no TARGET_68010. */
1739- && ((TARGET_68020 || TARGET_5200)
1740+ && ((TARGET_68020 || TARGET_COLDFIRE)
1741 || !(GET_CODE (operands[0]) == MEM
1742 && MEM_VOLATILE_P (operands[0]))))
1743 return "clr%.w %0";
1744@@ -1905,7 +1905,7 @@
1745 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
1746 && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx
1747 && ! ADDRESS_REG_P (operands[1])
1748- && ! TARGET_5200)
1749+ && ! TARGET_COLDFIRE)
1750 {
1751 xoperands[1] = operands[1];
1752 xoperands[2]
1753@@ -1930,12 +1930,12 @@
1754 /* clr and st insns on 68000 read before writing.
1755 This isn't so on the 68010, but we have no TARGET_68010. */
1756 if (!ADDRESS_REG_P (operands[0])
1757- && ((TARGET_68020 || TARGET_5200)
1758+ && ((TARGET_68020 || TARGET_COLDFIRE)
1759 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1760 {
1761 if (operands[1] == const0_rtx)
1762 return "clr%.b %0";
1763- if ((!TARGET_5200 || DATA_REG_P (operands[0]))
1764+ if ((!TARGET_COLDFIRE || DATA_REG_P (operands[0]))
1765 && GET_CODE (operands[1]) == CONST_INT
1766 && (INTVAL (operands[1]) & 255) == 255)
1767 {
1768@@ -1972,7 +1972,7 @@
1769 if (operands[1] == const0_rtx
1770 /* clr insns on 68000 read before writing.
1771 This isn't so on the 68010, but we have no TARGET_68010. */
1772- && ((TARGET_68020 || TARGET_5200)
1773+ && ((TARGET_68020 || TARGET_COLDFIRE)
1774 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1775 return "clr%.w %0";
1776 return "move%.w %1,%0";
1777@@ -1985,7 +1985,7 @@
1778 if (operands[1] == const0_rtx
1779 /* clr insns on 68000 read before writing.
1780 This isn't so on the 68010, but we have no TARGET_68010. */
1781- && ((TARGET_68020 || TARGET_5200)
1782+ && ((TARGET_68020 || TARGET_COLDFIRE)
1783 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1784 return "clr%.b %0";
1785 return "move%.b %1,%0";
1786@@ -3718,7 +3718,7 @@
1787 && (INTVAL (operands[2]) | 0xffff) == 0xffffffff
1788 && (DATA_REG_P (operands[0])
1789 || offsettable_memref_p (operands[0]))
1790- && !TARGET_5200)
1791+ && !TARGET_COLDFIRE)
1792 {
1793 if (GET_CODE (operands[0]) != REG)
1794 operands[0] = adjust_address (operands[0], HImode, 2);
1795@@ -3759,7 +3759,7 @@
1796 && INTVAL (operands[2]) >> 16 == 0
1797 && (DATA_REG_P (operands[0])
1798 || offsettable_memref_p (operands[0]))
1799- && !TARGET_5200)
1800+ && !TARGET_COLDFIRE)
1801 {
1802 if (GET_CODE (operands[0]) != REG)
1803 operands[0] = adjust_address (operands[0], HImode, 2);
1804@@ -3795,7 +3795,7 @@
1805 if (GET_CODE (operands[2]) == CONST_INT
1806 && INTVAL (operands[2]) >> 16 == 0
1807 && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0]))
1808- && !TARGET_5200)
1809+ && !TARGET_COLDFIRE)
1810 {
1811 if (! DATA_REG_P (operands[0]))
1812 operands[0] = adjust_address (operands[0], HImode, 2);
1813diff -Nru gcc-3.3.1.orig/gcc/config/m68k/m68k.h gcc-3.3.1/gcc/config/m68k/m68k.h
1814--- gcc-3.3.1.orig/gcc/config/m68k/m68k.h 2002-12-03 20:45:30.000000000 +0100
1815+++ gcc-3.3.1/gcc/config/m68k/m68k.h 2003-07-25 00:25:30.000000000 +0200
1816@@ -151,6 +151,30 @@
1817 #define MASK_NO_STRICT_ALIGNMENT 16384
1818 #define TARGET_STRICT_ALIGNMENT (~target_flags & MASK_NO_STRICT_ALIGNMENT)
1819
1820+/* Build for ColdFire v3 */
1821+#define MASK_CFV3 0x8000
1822+#define TARGET_CFV3 (target_flags & MASK_CFV3)
1823+
1824+/* Build for ColdFire v4 */
1825+#define MASK_CFV4 0x10000
1826+#define TARGET_CFV4 (target_flags & MASK_CFV4)
1827+
1828+/* Divide support for ColdFire */
1829+#define MASK_CF_HWDIV 0x40000
1830+#define TARGET_CF_HWDIV (target_flags & MASK_CF_HWDIV)
1831+
1832+/* Compile for mcf582 */
1833+#define MASK_528x 0x80000
1834+#define TARGET_528x (target_flags & MASK_528x)
1835+
1836+
1837+/* Is the target a coldfire */
1838+#define MASK_COLDFIRE (MASK_5200|MASK_528x|MASK_CFV3|MASK_CFV4)
1839+#define TARGET_COLDFIRE (target_flags & MASK_COLDFIRE)
1840+
1841+/* Which bits can be set by specifying a coldfire */
1842+#define MASK_ALL_CF_BITS (MASK_COLDFIRE|MASK_CF_HWDIV)
1843+
1844 /* Macro to define tables used to set the flags.
1845 This is a list in braces of pairs in braces,
1846 each pair being { "NAME", VALUE }
1847@@ -158,16 +182,16 @@
1848 An empty string NAME is used to identify the default VALUE. */
1849
1850 #define TARGET_SWITCHES \
1851- { { "68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \
1852+ { { "68020", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \
1853 N_("Generate code for a 68020") }, \
1854- { "c68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \
1855+ { "c68020", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \
1856 N_("Generate code for a 68020") }, \
1857 { "68020", (MASK_68020|MASK_BITFIELD), "" }, \
1858 { "c68020", (MASK_68020|MASK_BITFIELD), "" }, \
1859- { "68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
1860+ { "68000", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
1861 |MASK_68020|MASK_BITFIELD|MASK_68881), \
1862 N_("Generate code for a 68000") }, \
1863- { "c68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
1864+ { "c68000", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
1865 |MASK_68020|MASK_BITFIELD|MASK_68881), \
1866 N_("Generate code for a 68000") }, \
1867 { "bitfield", MASK_BITFIELD, \
1868@@ -198,40 +222,56 @@
1869 { "68881", MASK_68881, "" }, \
1870 { "soft-float", - (MASK_FPA|MASK_SKY|MASK_68040_ONLY|MASK_68881), \
1871 N_("Generate code with library calls for floating point") }, \
1872- { "68020-40", -(MASK_5200|MASK_68060|MASK_68040_ONLY), \
1873+ { "68020-40", -(MASK_ALL_CF_BITS|MASK_68060|MASK_68040_ONLY), \
1874 N_("Generate code for a 68040, without any new instructions") }, \
1875 { "68020-40", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040), ""},\
1876- { "68020-60", -(MASK_5200|MASK_68040_ONLY), \
1877+ { "68020-60", -(MASK_ALL_CF_BITS|MASK_68040_ONLY), \
1878 N_("Generate code for a 68060, without any new instructions") }, \
1879 { "68020-60", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040 \
1880 |MASK_68060), "" }, \
1881- { "68030", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY), \
1882+ { "68030", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY), \
1883 N_("Generate code for a 68030") }, \
1884 { "68030", (MASK_68020|MASK_BITFIELD), "" }, \
1885- { "68040", - (MASK_5200|MASK_68060), \
1886+ { "68040", - (MASK_ALL_CF_BITS|MASK_68060), \
1887 N_("Generate code for a 68040") }, \
1888 { "68040", (MASK_68020|MASK_68881|MASK_BITFIELD \
1889 |MASK_68040_ONLY|MASK_68040), "" }, \
1890- { "68060", - (MASK_5200|MASK_68040), \
1891+ { "68060", - (MASK_ALL_CF_BITS|MASK_68040), \
1892 N_("Generate code for a 68060") }, \
1893 { "68060", (MASK_68020|MASK_68881|MASK_BITFIELD \
1894 |MASK_68040_ONLY|MASK_68060), "" }, \
1895- { "5200", - (MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
1896+ { "5200", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
1897 |MASK_BITFIELD|MASK_68881), \
1898 N_("Generate code for a 520X") }, \
1899 { "5200", (MASK_5200), "" }, \
1900+ { "5206e", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
1901+ |MASK_BITFIELD|MASK_68881), \
1902+ N_("Generate code for a 5206e") }, \
1903+ { "5206e", (MASK_5200|MASK_CF_HWDIV), "" }, \
1904+ { "528x", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
1905+ |MASK_BITFIELD|MASK_68881), \
1906+ N_("Generate code for a 5206e") }, \
1907+ { "528x", (MASK_528x|MASK_CF_HWDIV), "" }, \
1908+ { "5307", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
1909+ |MASK_BITFIELD|MASK_68881), \
1910+ N_("Generate code for a 5307") }, \
1911+ { "5307", (MASK_CFV3|MASK_CF_HWDIV), "" }, \
1912+ { "5407", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020 \
1913+ |MASK_BITFIELD|MASK_68881), \
1914+ N_("Generate code for a 5407") }, \
1915+ { "5407", (MASK_CFV4|MASK_CF_HWDIV), "" }, \
1916 { "68851", 0, \
1917 N_("Generate code for a 68851") }, \
1918 { "no-68851", 0, \
1919 N_("Do no generate code for a 68851") }, \
1920- { "68302", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
1921+ { "68302", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
1922 |MASK_68020|MASK_BITFIELD|MASK_68881), \
1923 N_("Generate code for a 68302") }, \
1924- { "68332", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
1925+ { "68332", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
1926 |MASK_BITFIELD|MASK_68881), \
1927 N_("Generate code for a 68332") }, \
1928 { "68332", MASK_68020, "" }, \
1929- { "cpu32", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY \
1930+ { "cpu32", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY \
1931 |MASK_BITFIELD|MASK_68881), \
1932 N_("Generate code for a cpu32") }, \
1933 { "cpu32", MASK_68020, "" }, \
1934@@ -933,12 +973,12 @@
1935 this says how many the stack pointer really advances by.
1936 On the 68000, sp@- in a byte insn really pushes a word.
1937 On the 5200 (coldfire), sp@- in a byte insn pushes just a byte. */
1938-#define PUSH_ROUNDING(BYTES) (TARGET_5200 ? BYTES : ((BYTES) + 1) & ~1)
1939+#define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1)
1940
1941 /* We want to avoid trying to push bytes. */
1942 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
1943 (move_by_pieces_ninsns (SIZE, ALIGN) < MOVE_RATIO \
1944- && (((SIZE) >=16 && (ALIGN) >= 16) || (TARGET_5200)))
1945+ && (((SIZE) >=16 && (ALIGN) >= 16) || (TARGET_COLDFIRE)))
1946
1947 /* Offset of first parameter from the argument pointer register value. */
1948 #define FIRST_PARM_OFFSET(FNDECL) 8
1949@@ -1385,7 +1425,7 @@
1950 /* coldfire/5200 does not allow HImode index registers. */
1951 #define LEGITIMATE_INDEX_REG_P(X) \
1952 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1953- || (! TARGET_5200 \
1954+ || (! TARGET_COLDFIRE \
1955 && GET_CODE (X) == SIGN_EXTEND \
1956 && GET_CODE (XEXP (X, 0)) == REG \
1957 && GET_MODE (XEXP (X, 0)) == HImode \
1958@@ -1396,12 +1436,12 @@
1959
1960 #define LEGITIMATE_INDEX_P(X) \
1961 (LEGITIMATE_INDEX_REG_P (X) \
1962- || ((TARGET_68020 || TARGET_5200) && GET_CODE (X) == MULT \
1963+ || ((TARGET_68020 || TARGET_COLDFIRE) && GET_CODE (X) == MULT \
1964 && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
1965 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1966 && (INTVAL (XEXP (X, 1)) == 2 \
1967 || INTVAL (XEXP (X, 1)) == 4 \
1968- || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_5200))))
1969+ || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_COLDFIRE))))
1970
1971 /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */
1972 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1973diff -Nru gcc-3.3.1.orig/gcc/config/m68k/m68k.md gcc-3.3.1/gcc/config/m68k/m68k.md
1974--- gcc-3.3.1.orig/gcc/config/m68k/m68k.md 2003-06-12 23:56:59.000000000 +0200
1975+++ gcc-3.3.1/gcc/config/m68k/m68k.md 2003-07-25 00:25:30.000000000 +0200
1976@@ -24,7 +24,7 @@
1977 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
1978 ;;- 68k ISA. Differences include reduced support for byte and word
1979 ;;- operands and the removal of BCD, bitfield, rotate, and integer
1980-;;- divide instructions. The TARGET_5200 flag turns the use of the
1981+;;- divide instructions. The TARGET_COLDFIRE flag turns the use of the
1982 ;;- removed opcodes and addressing modes off.
1983 ;;-
1984
1985@@ -360,7 +360,7 @@
1986 /* ISI's assembler fails to handle tstl a0. */
1987 if (! ADDRESS_REG_P (operands[0]))
1988 #else
1989- if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
1990+ if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
1991 #endif
1992 return \"tst%.l %0\";
1993 /* If you think that the 68020 does not support tstl a0,
1994@@ -519,7 +519,7 @@
1995 [(set (cc0)
1996 (compare (match_operand:SI 0 "nonimmediate_operand" "rKT,rKs,mSr,mSa,>")
1997 (match_operand:SI 1 "general_src_operand" "mSr,mSa,KTr,Ksr,>")))]
1998- "!TARGET_5200"
1999+ "!TARGET_COLDFIRE"
2000 "*
2001 {
2002 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
2003@@ -559,7 +559,7 @@
2004 [(set (cc0)
2005 (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
2006 (match_operand:SI 1 "general_operand" "r,mrKs")))]
2007- "TARGET_5200"
2008+ "TARGET_COLDFIRE"
2009 "*
2010 {
2011 if (REG_P (operands[1])
2012@@ -582,14 +582,14 @@
2013 [(set (cc0)
2014 (compare (match_operand:HI 0 "nonimmediate_src_operand" "")
2015 (match_operand:HI 1 "general_src_operand" "")))]
2016- "!TARGET_5200"
2017+ "!TARGET_COLDFIRE"
2018 "m68k_last_compare_had_fp_operands = 0;")
2019
2020 (define_insn ""
2021 [(set (cc0)
2022 (compare (match_operand:HI 0 "nonimmediate_src_operand" "rnmS,d,n,mS,>")
2023 (match_operand:HI 1 "general_src_operand" "d,rnmS,mS,n,>")))]
2024- "!TARGET_5200"
2025+ "!TARGET_COLDFIRE"
2026 "*
2027 {
2028 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
2029@@ -618,14 +618,14 @@
2030 [(set (cc0)
2031 (compare (match_operand:QI 0 "nonimmediate_src_operand" "")
2032 (match_operand:QI 1 "general_src_operand" "")))]
2033- "!TARGET_5200"
2034+ "!TARGET_COLDFIRE"
2035 "m68k_last_compare_had_fp_operands = 0;")
2036
2037 (define_insn ""
2038 [(set (cc0)
2039 (compare (match_operand:QI 0 "nonimmediate_src_operand" "dn,dmS,>")
2040 (match_operand:QI 1 "general_src_operand" "dmS,nd,>")))]
2041- "!TARGET_5200"
2042+ "!TARGET_COLDFIRE"
2043 "*
2044 {
2045 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
2046@@ -769,7 +769,7 @@
2047 (const_int 1)
2048 (minus:SI (const_int 7)
2049 (match_operand:SI 1 "general_operand" "di"))))]
2050- "!TARGET_5200"
2051+ "!TARGET_COLDFIRE"
2052 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
2053
2054 ;; This is the same as the above pattern except for the constraints. The 'i'
2055@@ -780,7 +780,7 @@
2056 (const_int 1)
2057 (minus:SI (const_int 7)
2058 (match_operand:SI 1 "general_operand" "d"))))]
2059- "TARGET_5200"
2060+ "TARGET_COLDFIRE"
2061 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
2062
2063 (define_insn ""
2064@@ -821,7 +821,7 @@
2065 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
2066 (const_int 1)
2067 (match_operand:SI 1 "const_int_operand" "n")))]
2068- "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_5200"
2069+ "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_COLDFIRE"
2070 "*
2071 {
2072 operands[1] = GEN_INT (7 - INTVAL (operands[1]));
2073@@ -832,7 +832,7 @@
2074 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
2075 (const_int 1)
2076 (match_operand:SI 1 "const_int_operand" "n")))]
2077- "!TARGET_5200"
2078+ "!TARGET_COLDFIRE"
2079 "*
2080 {
2081 if (GET_CODE (operands[0]) == MEM)
2082@@ -853,7 +853,7 @@
2083 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ")
2084 (const_int 1)
2085 (match_operand:SI 1 "const_int_operand" "n")))]
2086- "TARGET_5200"
2087+ "TARGET_COLDFIRE"
2088 "*
2089 {
2090 if (GET_CODE (operands[0]) == MEM)
2091@@ -900,7 +900,7 @@
2092 (const_int 0))]
2093 ;; clr insns on 68000 read before writing.
2094 ;; This isn't so on the 68010, but we have no TARGET_68010.
2095- "((TARGET_68020 || TARGET_5200)
2096+ "((TARGET_68020 || TARGET_COLDFIRE)
2097 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
2098 "*
2099 {
2100@@ -924,7 +924,7 @@
2101 }
2102 }
2103 /* moveq is faster on the 68000. */
2104- if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_5200))
2105+ if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_COLDFIRE))
2106 #if defined(MOTOROLA) && !defined(CRDS)
2107 return \"moveq%.l %#0,%0\";
2108 #else
2109@@ -980,7 +980,7 @@
2110 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d,a<,y,!*x*r*m")
2111 (match_operand:SI 1 "general_src_operand" "daymSKT,n,i,g,*x*r*m"))]
2112
2113- "!TARGET_5200"
2114+ "!TARGET_COLDFIRE"
2115 "*
2116 {
2117 if (which_alternative == 4)
2118@@ -993,7 +993,7 @@
2119 (define_insn ""
2120 [(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g")
2121 (match_operand:SI 1 "general_operand" "g,r<Q>"))]
2122- "TARGET_5200"
2123+ "TARGET_COLDFIRE"
2124 "* return output_move_simode (operands);")
2125
2126 ;; Special case of fullword move, where we need to get a non-GOT PIC
2127@@ -1018,13 +1018,13 @@
2128 (define_insn ""
2129 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
2130 (match_operand:HI 1 "general_src_operand" "gS"))]
2131- "!TARGET_5200"
2132+ "!TARGET_COLDFIRE"
2133 "* return output_move_himode (operands);")
2134
2135 (define_insn ""
2136 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<Q>,g")
2137 (match_operand:HI 1 "general_operand" "g,r<Q>"))]
2138- "TARGET_5200"
2139+ "TARGET_COLDFIRE"
2140 "* return output_move_himode (operands);")
2141
2142 (define_expand "movstricthi"
2143@@ -1036,13 +1036,13 @@
2144 (define_insn ""
2145 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
2146 (match_operand:HI 1 "general_src_operand" "rmSn"))]
2147- "!TARGET_5200"
2148+ "!TARGET_COLDFIRE"
2149 "* return output_move_stricthi (operands);")
2150
2151 (define_insn ""
2152 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+d,m"))
2153 (match_operand:HI 1 "general_src_operand" "rmn,r"))]
2154- "TARGET_5200"
2155+ "TARGET_COLDFIRE"
2156 "* return output_move_stricthi (operands);")
2157
2158 (define_expand "movqi"
2159@@ -1054,13 +1054,13 @@
2160 (define_insn ""
2161 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,*a,m")
2162 (match_operand:QI 1 "general_src_operand" "dmSi*a,di*a,dmSi"))]
2163- "!TARGET_5200"
2164+ "!TARGET_COLDFIRE"
2165 "* return output_move_qimode (operands);")
2166
2167 (define_insn ""
2168 [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>,dm,d*a")
2169 (match_operand:QI 1 "general_src_operand" "dmi,d<Q>,di*a"))]
2170- "TARGET_5200"
2171+ "TARGET_COLDFIRE"
2172 "* return output_move_qimode (operands);")
2173
2174 (define_expand "movstrictqi"
2175@@ -1072,20 +1072,20 @@
2176 (define_insn ""
2177 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
2178 (match_operand:QI 1 "general_src_operand" "dmSn"))]
2179- "!TARGET_5200"
2180+ "!TARGET_COLDFIRE"
2181 "* return output_move_strictqi (operands);")
2182
2183 (define_insn ""
2184 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+d,m"))
2185 (match_operand:QI 1 "general_src_operand" "dmn,d"))]
2186- "TARGET_5200"
2187+ "TARGET_COLDFIRE"
2188 "* return output_move_strictqi (operands);")
2189
2190 (define_expand "pushqi1"
2191 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int -2)))
2192 (set (mem:QI (plus:SI (reg:SI 15) (const_int 1)))
2193 (match_operand:QI 0 "general_operand" ""))]
2194- "!TARGET_5200"
2195+ "!TARGET_COLDFIRE"
2196 "")
2197
2198 (define_expand "movsf"
2199@@ -1099,7 +1099,7 @@
2200 (match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))]
2201 ; [(set (match_operand:SF 0 "nonimmediate_operand" "=rmf")
2202 ; (match_operand:SF 1 "general_operand" "rmfF"))]
2203- "!TARGET_5200"
2204+ "!TARGET_COLDFIRE"
2205 "*
2206 {
2207 if (which_alternative >= 4)
2208@@ -1140,7 +1140,7 @@
2209 if (operands[1] == CONST0_RTX (SFmode)
2210 /* clr insns on 68000 read before writing.
2211 This isn't so on the 68010, but we have no TARGET_68010. */
2212- && ((TARGET_68020 || TARGET_5200)
2213+ && ((TARGET_68020 || TARGET_COLDFIRE)
2214 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
2215 {
2216 if (ADDRESS_REG_P (operands[0]))
2217@@ -1163,7 +1163,7 @@
2218 }
2219 }
2220 /* moveq is faster on the 68000. */
2221- if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_5200))
2222+ if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_COLDFIRE))
2223 {
2224 #if defined(MOTOROLA) && !defined(CRDS)
2225 return \"moveq%.l %#0,%0\";
2226@@ -1179,7 +1179,7 @@
2227 (define_insn ""
2228 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,g")
2229 (match_operand:SF 1 "general_operand" "g,r"))]
2230- "TARGET_5200"
2231+ "TARGET_COLDFIRE"
2232 "* return \"move%.l %1,%0\";")
2233
2234 (define_expand "movdf"
2235@@ -1195,7 +1195,7 @@
2236 "*rf,m,0,*rofE<>,*rmE,y,xH,*rm,x"))]
2237 ; [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,&rf,&rof<>")
2238 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
2239- "!TARGET_5200"
2240+ "!TARGET_COLDFIRE"
2241 "*
2242 {
2243 if (which_alternative == 7)
2244@@ -1248,7 +1248,7 @@
2245 (define_insn ""
2246 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,g")
2247 (match_operand:DF 1 "general_operand" "g,r"))]
2248- "TARGET_5200"
2249+ "TARGET_COLDFIRE"
2250 "* return output_move_double (operands);")
2251
2252 (define_expand "movxf"
2253@@ -1319,7 +1319,7 @@
2254 (define_insn ""
2255 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
2256 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
2257- "! TARGET_68881 && ! TARGET_5200"
2258+ "! TARGET_68881 && ! TARGET_COLDFIRE"
2259 "*
2260 {
2261 if (FP_REG_P (operands[0]))
2262@@ -1360,7 +1360,7 @@
2263 (define_insn ""
2264 [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
2265 (match_operand:XF 1 "nonimmediate_operand" "g,r"))]
2266- "! TARGET_68881 && TARGET_5200"
2267+ "! TARGET_68881 && TARGET_COLDFIRE"
2268 "* return output_move_double (operands);")
2269
2270 (define_expand "movdi"
2271@@ -1379,7 +1379,7 @@
2272 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))]
2273 ; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&rf,&ro<>,!&rm,!&f")
2274 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
2275- "!TARGET_5200"
2276+ "!TARGET_COLDFIRE"
2277 "*
2278 {
2279 if (which_alternative == 8)
2280@@ -1419,7 +1419,7 @@
2281 (define_insn ""
2282 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,g")
2283 (match_operand:DI 1 "general_operand" "g,r"))]
2284- "TARGET_5200"
2285+ "TARGET_COLDFIRE"
2286 "* return output_move_double (operands);")
2287
2288 ;; Thus goes after the move instructions
2289@@ -1534,7 +1534,7 @@
2290 (define_insn "*zero_extendsidi2_cf"
2291 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,m")
2292 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm,r")))]
2293- "TARGET_5200"
2294+ "TARGET_COLDFIRE"
2295 "*
2296 {
2297 CC_STATUS_INIT;
2298@@ -1558,7 +1558,7 @@
2299 (define_insn "*zero_extendsidi2"
2300 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
2301 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
2302- "!TARGET_5200"
2303+ "!TARGET_COLDFIRE"
2304 "*
2305 {
2306 CC_STATUS_INIT;
2307@@ -1659,9 +1659,9 @@
2308 {
2309 if (GET_CODE (operands[1]) == REG
2310 && REGNO (operands[0]) == REGNO (operands[1]))
2311- return (!TARGET_5200 ? \"and%.w %#0xFF,%0\" : \"and%.l %#0xFF,%0\");
2312+ return (!TARGET_COLDFIRE ? \"and%.w %#0xFF,%0\" : \"and%.l %#0xFF,%0\");
2313 if (reg_mentioned_p (operands[0], operands[1]))
2314- return (!TARGET_5200 ? \"move%.b %1,%0\;and%.w %#0xFF,%0\"
2315+ return (!TARGET_COLDFIRE ? \"move%.b %1,%0\;and%.w %#0xFF,%0\"
2316 : \"move%.b %1,%0\;and%.l %#0xFF,%0\");
2317 return \"clr%.w %0\;move%.b %1,%0\";
2318 }
2319@@ -1751,7 +1751,7 @@
2320 {
2321 CC_STATUS_INIT;
2322 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2323- if (TARGET_68020 || TARGET_5200)
2324+ if (TARGET_68020 || TARGET_COLDFIRE)
2325 return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
2326 else
2327 return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
2328@@ -1766,7 +1766,7 @@
2329 {
2330 CC_STATUS_INIT;
2331 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2332- if (TARGET_68020 || TARGET_5200)
2333+ if (TARGET_68020 || TARGET_COLDFIRE)
2334 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
2335 else
2336 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
2337@@ -1781,7 +1781,7 @@
2338 {
2339 CC_STATUS_INIT;
2340 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2341- if (TARGET_68020 || TARGET_5200)
2342+ if (TARGET_68020 || TARGET_COLDFIRE)
2343 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
2344 else
2345 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
2346@@ -1813,7 +1813,7 @@
2347 output_asm_insn (\"add%.l %2,%3\", operands);
2348 else
2349 output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands);
2350- if (TARGET_68020 || TARGET_5200)
2351+ if (TARGET_68020 || TARGET_COLDFIRE)
2352 return \"smi %0\;extb%.l %0\";
2353 else
2354 return \"smi %0\;ext%.w %0\;ext%.l %0\";
2355@@ -1840,7 +1840,7 @@
2356 (define_insn "extendqisi2"
2357 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2358 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
2359- "TARGET_68020 || TARGET_5200"
2360+ "TARGET_68020 || TARGET_COLDFIRE"
2361 "extb%.l %0")
2362 \f
2363 ;; Conversions between float and double.
2364@@ -2139,7 +2139,7 @@
2365 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2366 output_asm_insn (\"move%.l %4,%3\", operands);
2367 output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
2368- if (TARGET_68020 || TARGET_5200)
2369+ if (TARGET_68020 || TARGET_COLDFIRE)
2370 output_asm_insn (\"extb%.l %2\", operands);
2371 else
2372 output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
2373@@ -2156,7 +2156,7 @@
2374 (const_int 32))
2375 (match_operand:DI 2 "general_operand" "0,0,0,0")))
2376 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2377- "!TARGET_5200"
2378+ "!TARGET_COLDFIRE"
2379 "*
2380 {
2381 CC_STATUS_INIT;
2382@@ -2348,14 +2348,14 @@
2383 (match_operand:SI 2 "general_src_operand" "dIKLT,rJK,a,mSrIKLT,mSrIKLs")))]
2384
2385
2386- "! TARGET_5200"
2387+ "! TARGET_COLDFIRE"
2388 "* return output_addsi3 (operands);")
2389
2390 (define_insn "*addsi3_5200"
2391 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,r")
2392 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2393 (match_operand:SI 2 "general_src_operand" "d,rJK,a,mrIKLs")))]
2394- "TARGET_5200"
2395+ "TARGET_COLDFIRE"
2396 "* return output_addsi3 (operands);")
2397
2398 (define_insn ""
2399@@ -2363,14 +2363,14 @@
2400 (plus:SI (match_operand:SI 1 "general_operand" "0")
2401 (sign_extend:SI
2402 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2403- "!TARGET_5200"
2404+ "!TARGET_COLDFIRE"
2405 "add%.w %2,%0")
2406
2407 (define_insn "addhi3"
2408 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
2409 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2410 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2411- "!TARGET_5200"
2412+ "!TARGET_COLDFIRE"
2413 "*
2414 {
2415 if (GET_CODE (operands[2]) == CONST_INT)
2416@@ -2432,7 +2432,7 @@
2417 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2418 (plus:HI (match_dup 0)
2419 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2420- "!TARGET_5200"
2421+ "!TARGET_COLDFIRE"
2422 "*
2423 {
2424 if (GET_CODE (operands[1]) == CONST_INT)
2425@@ -2488,7 +2488,7 @@
2426 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2427 (plus:HI (match_operand:HI 1 "general_src_operand" "dn,rmSn")
2428 (match_dup 0)))]
2429- "!TARGET_5200"
2430+ "!TARGET_COLDFIRE"
2431 "*
2432 {
2433 if (GET_CODE (operands[1]) == CONST_INT)
2434@@ -2544,7 +2544,7 @@
2435 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
2436 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2437 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2438- "!TARGET_5200"
2439+ "!TARGET_COLDFIRE"
2440 "*
2441 {
2442 #ifndef NO_ADDSUB_Q
2443@@ -2570,7 +2570,7 @@
2444 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2445 (plus:QI (match_dup 0)
2446 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2447- "!TARGET_5200"
2448+ "!TARGET_COLDFIRE"
2449 "*
2450 {
2451 #ifndef NO_ADDSUB_Q
2452@@ -2596,7 +2596,7 @@
2453 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2454 (plus:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
2455 (match_dup 0)))]
2456- "!TARGET_5200"
2457+ "!TARGET_COLDFIRE"
2458 "*
2459 {
2460 #ifndef NO_ADDSUB_Q
2461@@ -2738,7 +2738,7 @@
2462 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2463 (const_int 32))))
2464 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2465- "!TARGET_5200"
2466+ "!TARGET_COLDFIRE"
2467 "*
2468 {
2469 CC_STATUS_INIT;
2470@@ -2872,35 +2872,35 @@
2471 (minus:SI (match_operand:SI 1 "general_operand" "0")
2472 (sign_extend:SI
2473 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2474- "!TARGET_5200"
2475+ "!TARGET_COLDFIRE"
2476 "sub%.w %2,%0")
2477
2478 (define_insn "subhi3"
2479 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
2480 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2481 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2482- "!TARGET_5200"
2483+ "!TARGET_COLDFIRE"
2484 "sub%.w %2,%0")
2485
2486 (define_insn ""
2487 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2488 (minus:HI (match_dup 0)
2489 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2490- "!TARGET_5200"
2491+ "!TARGET_COLDFIRE"
2492 "sub%.w %1,%0")
2493
2494 (define_insn "subqi3"
2495 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
2496 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2497 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2498- "!TARGET_5200"
2499+ "!TARGET_COLDFIRE"
2500 "sub%.b %2,%0")
2501
2502 (define_insn ""
2503 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2504 (minus:QI (match_dup 0)
2505 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2506- "!TARGET_5200"
2507+ "!TARGET_COLDFIRE"
2508 "sub%.b %1,%0")
2509
2510 (define_expand "subdf3"
2511@@ -3066,7 +3066,7 @@
2512 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2513 (mult:SI (match_operand:SI 1 "general_operand" "")
2514 (match_operand:SI 2 "general_operand" "")))]
2515- "TARGET_68020 || TARGET_5200"
2516+ "TARGET_68020 || TARGET_COLDFIRE"
2517 "")
2518
2519 (define_insn ""
2520@@ -3081,7 +3081,7 @@
2521 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2522 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2523 (match_operand:SI 2 "general_operand" "d<Q>")))]
2524- "TARGET_5200"
2525+ "TARGET_COLDFIRE"
2526 "muls%.l %2,%0")
2527
2528 (define_insn "umulhisi3"
2529@@ -3127,7 +3127,7 @@
2530 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2531 (zero_extend:DI (match_dup 2)))
2532 (const_int 32))))])]
2533- "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2534+ "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2535 "")
2536
2537 (define_insn ""
2538@@ -3138,7 +3138,7 @@
2539 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2540 (zero_extend:DI (match_dup 2)))
2541 (const_int 32))))]
2542- "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2543+ "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2544 "mulu%.l %2,%3:%0")
2545
2546 ; Match immediate case. For 2.4 only match things < 2^31.
2547@@ -3153,7 +3153,7 @@
2548 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
2549 (match_dup 2))
2550 (const_int 32))))]
2551- "TARGET_68020 && !TARGET_68060 && !TARGET_5200
2552+ "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE
2553 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
2554 "mulu%.l %2,%3:%0")
2555
2556@@ -3166,7 +3166,7 @@
2557 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2558 (sign_extend:DI (match_dup 2)))
2559 (const_int 32))))])]
2560- "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2561+ "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2562 "")
2563
2564 (define_insn ""
2565@@ -3177,7 +3177,7 @@
2566 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2567 (sign_extend:DI (match_dup 2)))
2568 (const_int 32))))]
2569- "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2570+ "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2571 "muls%.l %2,%3:%0")
2572
2573 (define_insn ""
2574@@ -3188,7 +3188,7 @@
2575 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
2576 (match_dup 2))
2577 (const_int 32))))]
2578- "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2579+ "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2580 "muls%.l %2,%3:%0")
2581
2582 (define_expand "umulsi3_highpart"
2583@@ -3200,7 +3200,7 @@
2584 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
2585 (const_int 32))))
2586 (clobber (match_dup 3))])]
2587- "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2588+ "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2589 "
2590 {
2591 operands[3] = gen_reg_rtx (SImode);
2592@@ -3225,7 +3225,7 @@
2593 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
2594 (const_int 32))))
2595 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2596- "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2597+ "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2598 "mulu%.l %3,%0:%1")
2599
2600 (define_insn "const_umulsi3_highpart"
2601@@ -3236,7 +3236,7 @@
2602 (match_operand:DI 3 "const_uint32_operand" "n"))
2603 (const_int 32))))
2604 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2605- "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2606+ "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2607 "mulu%.l %3,%0:%1")
2608
2609 (define_expand "smulsi3_highpart"
2610@@ -3248,7 +3248,7 @@
2611 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
2612 (const_int 32))))
2613 (clobber (match_dup 3))])]
2614- "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2615+ "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2616 "
2617 {
2618 operands[3] = gen_reg_rtx (SImode);
2619@@ -3269,7 +3269,7 @@
2620 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
2621 (const_int 32))))
2622 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2623- "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2624+ "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2625 "muls%.l %3,%0:%1")
2626
2627 (define_insn "const_smulsi3_highpart"
2628@@ -3280,7 +3280,7 @@
2629 (match_operand:DI 3 "const_sint32_operand" "n"))
2630 (const_int 32))))
2631 (clobber (match_operand:SI 1 "register_operand" "=d"))]
2632- "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
2633+ "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
2634 "muls%.l %3,%0:%1")
2635
2636 (define_expand "muldf3"
2637@@ -3574,13 +3574,40 @@
2638 \f
2639 ;; Remainder instructions.
2640
2641-(define_insn "divmodsi4"
2642+(define_expand "divmodsi4"
2643+ [(parallel
2644+ [(set (match_operand:SI 0 "nonimmediate_operand" "")
2645+ (div:SI (match_operand:SI 1 "general_operand" "")
2646+ (match_operand:SI 2 "general_src_operand" "")))
2647+ (set (match_operand:SI 3 "nonimmediate_operand" "")
2648+ (mod:SI (match_dup 1) (match_dup 2)))])]
2649+ "TARGET_68020 || TARGET_CF_HWDIV"
2650+ "")
2651+
2652+(define_insn ""
2653+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2654+ (div:SI (match_operand:SI 1 "general_operand" "0")
2655+ (match_operand:SI 2 "general_src_operand" "d<Q>U")))
2656+ (set (match_operand:SI 3 "nonimmediate_operand" "=&d")
2657+ (mod:SI (match_dup 1) (match_dup 2)))]
2658+ "TARGET_CF_HWDIV"
2659+ "*
2660+{
2661+ if (find_reg_note (insn, REG_UNUSED, operands[3]))
2662+ return \"divs%.l %2,%0\";
2663+ else if (find_reg_note (insn, REG_UNUSED, operands[0]))
2664+ return \"rems%.l %2,%3:%0\";
2665+ else
2666+ return \"rems%.l %2,%3:%0\;divs%.l %2,%0\";
2667+}")
2668+
2669+(define_insn ""
2670 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2671 (div:SI (match_operand:SI 1 "general_operand" "0")
2672 (match_operand:SI 2 "general_src_operand" "dmSTK")))
2673 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
2674 (mod:SI (match_dup 1) (match_dup 2)))]
2675- "TARGET_68020 && !TARGET_5200"
2676+ "TARGET_68020"
2677 "*
2678 {
2679 if (find_reg_note (insn, REG_UNUSED, operands[3]))
2680@@ -3589,13 +3616,40 @@
2681 return \"divsl%.l %2,%3:%0\";
2682 }")
2683
2684-(define_insn "udivmodsi4"
2685+(define_expand "udivmodsi4"
2686+ [(parallel
2687+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2688+ (udiv:SI (match_operand:SI 1 "general_operand" "0")
2689+ (match_operand:SI 2 "general_src_operand" "dmSTK")))
2690+ (set (match_operand:SI 3 "nonimmediate_operand" "=d")
2691+ (umod:SI (match_dup 1) (match_dup 2)))])]
2692+ "TARGET_68020 || TARGET_CF_HWDIV"
2693+ "")
2694+
2695+(define_insn ""
2696+ [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2697+ (udiv:SI (match_operand:SI 1 "general_operand" "0")
2698+ (match_operand:SI 2 "general_src_operand" "d<Q>U")))
2699+ (set (match_operand:SI 3 "nonimmediate_operand" "=&d")
2700+ (umod:SI (match_dup 1) (match_dup 2)))]
2701+ "TARGET_CF_HWDIV"
2702+ "*
2703+{
2704+ if (find_reg_note (insn, REG_UNUSED, operands[3]))
2705+ return \"divu%.l %2,%0\";
2706+ else if (find_reg_note (insn, REG_UNUSED, operands[0]))
2707+ return \"remu%.l %2,%3:%0\";
2708+ else
2709+ return \"remu%.l %2,%3:%0\;divu%.l %2,%0\";
2710+}")
2711+
2712+(define_insn ""
2713 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
2714 (udiv:SI (match_operand:SI 1 "general_operand" "0")
2715 (match_operand:SI 2 "general_src_operand" "dmSTK")))
2716 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
2717 (umod:SI (match_dup 1) (match_dup 2)))]
2718- "TARGET_68020 && !TARGET_5200"
2719+ "TARGET_68020 && !TARGET_COLDFIRE"
2720 "*
2721 {
2722 if (find_reg_note (insn, REG_UNUSED, operands[3]))
2723@@ -3610,7 +3664,7 @@
2724 (match_operand:HI 2 "general_src_operand" "dmSKT")))
2725 (set (match_operand:HI 3 "nonimmediate_operand" "=d")
2726 (mod:HI (match_dup 1) (match_dup 2)))]
2727- "!TARGET_5200"
2728+ "!TARGET_COLDFIRE || TARGET_CF_HWDIV"
2729 "*
2730 {
2731 #ifdef MOTOROLA
2732@@ -3633,7 +3687,7 @@
2733 (match_operand:HI 2 "general_src_operand" "dmSKT")))
2734 (set (match_operand:HI 3 "nonimmediate_operand" "=d")
2735 (umod:HI (match_dup 1) (match_dup 2)))]
2736- "!TARGET_5200"
2737+ "!TARGET_COLDFIRE || TARGET_CF_HWDIV"
2738 "*
2739 {
2740 #ifdef MOTOROLA
2741@@ -3657,7 +3711,7 @@
2742 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
2743 (and:DI (match_operand:DI 1 "general_operand" "%0,0")
2744 (match_operand:DI 2 "general_operand" "dn,don")))]
2745- "!TARGET_5200"
2746+ "!TARGET_COLDFIRE"
2747 "*
2748 {
2749 CC_STATUS_INIT;
2750@@ -3734,7 +3788,7 @@
2751 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
2752 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
2753 (match_operand:SI 2 "general_src_operand" "dKT,dmSM")))]
2754- "!TARGET_5200"
2755+ "!TARGET_COLDFIRE"
2756 "*
2757 {
2758 return output_andsi3 (operands);
2759@@ -3744,49 +3798,49 @@
2760 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
2761 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
2762 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
2763- "TARGET_5200"
2764+ "TARGET_COLDFIRE"
2765 "and%.l %2,%0")
2766
2767 (define_insn "andhi3"
2768 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
2769 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
2770 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
2771- "!TARGET_5200"
2772+ "!TARGET_COLDFIRE"
2773 "and%.w %2,%0")
2774
2775 (define_insn ""
2776 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2777 (and:HI (match_dup 0)
2778 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
2779- "!TARGET_5200"
2780+ "!TARGET_COLDFIRE"
2781 "and%.w %1,%0")
2782
2783 (define_insn ""
2784 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2785 (and:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
2786 (match_dup 0)))]
2787- "!TARGET_5200"
2788+ "!TARGET_COLDFIRE"
2789 "and%.w %1,%0")
2790
2791 (define_insn "andqi3"
2792 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
2793 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
2794 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2795- "!TARGET_5200"
2796+ "!TARGET_COLDFIRE"
2797 "and%.b %2,%0")
2798
2799 (define_insn ""
2800 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2801 (and:QI (match_dup 0)
2802 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2803- "!TARGET_5200"
2804+ "!TARGET_COLDFIRE"
2805 "and%.b %1,%0")
2806
2807 (define_insn ""
2808 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2809 (and:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
2810 (match_dup 0)))]
2811- "!TARGET_5200"
2812+ "!TARGET_COLDFIRE"
2813 "and%.b %1,%0")
2814 \f
2815 ;; inclusive-or instructions
2816@@ -3795,7 +3849,7 @@
2817 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
2818 (ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn"))
2819 (match_operand:DI 2 "general_operand" "0,0")))]
2820- "!TARGET_5200"
2821+ "!TARGET_COLDFIRE"
2822 "*
2823 {
2824 int byte_mode;
2825@@ -3822,7 +3876,7 @@
2826 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
2827 (ior:DI (match_operand:DI 1 "general_operand" "%0,0")
2828 (match_operand:DI 2 "general_operand" "dn,don")))]
2829- "!TARGET_5200"
2830+ "!TARGET_COLDFIRE"
2831 "*
2832 {
2833 CC_STATUS_INIT;
2834@@ -3899,7 +3953,7 @@
2835 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
2836 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
2837 (match_operand:SI 2 "general_src_operand" "dKT,dmSMT")))]
2838- "! TARGET_5200"
2839+ "! TARGET_COLDFIRE"
2840 "*
2841 {
2842 return output_iorsi3 (operands);
2843@@ -3909,49 +3963,49 @@
2844 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
2845 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
2846 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
2847- "TARGET_5200"
2848+ "TARGET_COLDFIRE"
2849 "or%.l %2,%0")
2850
2851 (define_insn "iorhi3"
2852 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
2853 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
2854 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
2855- "!TARGET_5200"
2856+ "!TARGET_COLDFIRE"
2857 "or%.w %2,%0")
2858
2859 (define_insn ""
2860 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2861 (ior:HI (match_dup 0)
2862 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
2863- "!TARGET_5200"
2864+ "!TARGET_COLDFIRE"
2865 "or%.w %1,%0")
2866
2867 (define_insn ""
2868 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2869 (ior:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
2870 (match_dup 0)))]
2871- "!TARGET_5200"
2872+ "!TARGET_COLDFIRE"
2873 "or%.w %1,%0")
2874
2875 (define_insn "iorqi3"
2876 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
2877 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
2878 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2879- "!TARGET_5200"
2880+ "!TARGET_COLDFIRE"
2881 "or%.b %2,%0")
2882
2883 (define_insn ""
2884 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2885 (ior:QI (match_dup 0)
2886 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2887- "!TARGET_5200"
2888+ "!TARGET_COLDFIRE"
2889 "or%.b %1,%0")
2890
2891 (define_insn ""
2892 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2893 (ior:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
2894 (match_dup 0)))]
2895- "!TARGET_5200"
2896+ "!TARGET_COLDFIRE"
2897 "or%.b %1,%0")
2898
2899 ;; On all 68k models, this makes faster code in a special case.
2900@@ -3978,7 +4032,7 @@
2901 [(set (match_operand:SI 0 "nonimmediate_operand" "=o,d")
2902 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
2903 (match_operand:SI 2 "general_operand" "0,0")))]
2904- "!TARGET_5200"
2905+ "!TARGET_COLDFIRE"
2906 "*
2907 {
2908 int byte_mode;
2909@@ -4001,7 +4055,7 @@
2910 [(set (match_operand:DI 0 "nonimmediate_operand" "=od")
2911 (xor:DI (match_operand:DI 1 "general_operand" "%0")
2912 (match_operand:DI 2 "general_operand" "dn")))]
2913- "!TARGET_5200"
2914+ "!TARGET_COLDFIRE"
2915 "*
2916 {
2917 CC_STATUS_INIT;
2918@@ -4082,7 +4136,7 @@
2919 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
2920 (match_operand:SI 2 "general_operand" "di,dKT")))]
2921
2922- "!TARGET_5200"
2923+ "!TARGET_COLDFIRE"
2924 "*
2925 {
2926 return output_xorsi3 (operands);
2927@@ -4092,49 +4146,49 @@
2928 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm,d")
2929 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
2930 (match_operand:SI 2 "general_operand" "d,Ks")))]
2931- "TARGET_5200"
2932+ "TARGET_COLDFIRE"
2933 "eor%.l %2,%0")
2934
2935 (define_insn "xorhi3"
2936 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
2937 (xor:HI (match_operand:HI 1 "general_operand" "%0")
2938 (match_operand:HI 2 "general_operand" "dn")))]
2939- "!TARGET_5200"
2940+ "!TARGET_COLDFIRE"
2941 "eor%.w %2,%0")
2942
2943 (define_insn ""
2944 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
2945 (xor:HI (match_dup 0)
2946 (match_operand:HI 1 "general_operand" "dn")))]
2947- "!TARGET_5200"
2948+ "!TARGET_COLDFIRE"
2949 "eor%.w %1,%0")
2950
2951 (define_insn ""
2952 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
2953 (xor:HI (match_operand:HI 1 "general_operand" "dn")
2954 (match_dup 0)))]
2955- "!TARGET_5200"
2956+ "!TARGET_COLDFIRE"
2957 "eor%.w %1,%0")
2958
2959 (define_insn "xorqi3"
2960 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
2961 (xor:QI (match_operand:QI 1 "general_operand" "%0")
2962 (match_operand:QI 2 "general_operand" "dn")))]
2963- "!TARGET_5200"
2964+ "!TARGET_COLDFIRE"
2965 "eor%.b %2,%0")
2966
2967 (define_insn ""
2968 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
2969 (xor:QI (match_dup 0)
2970 (match_operand:QI 1 "general_operand" "dn")))]
2971- "!TARGET_5200"
2972+ "!TARGET_COLDFIRE"
2973 "eor%.b %1,%0")
2974
2975 (define_insn ""
2976 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
2977 (xor:QI (match_operand:QI 1 "general_operand" "dn")
2978 (match_dup 0)))]
2979- "!TARGET_5200"
2980+ "!TARGET_COLDFIRE"
2981 "eor%.b %1,%0")
2982 \f
2983 ;; negation instructions
2984@@ -4145,7 +4199,7 @@
2985 ""
2986 "
2987 {
2988- if (TARGET_5200)
2989+ if (TARGET_COLDFIRE)
2990 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
2991 else
2992 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
2993@@ -4155,7 +4209,7 @@
2994 (define_insn "negdi2_internal"
2995 [(set (match_operand:DI 0 "nonimmediate_operand" "=<,do,!*a")
2996 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
2997- "!TARGET_5200"
2998+ "!TARGET_COLDFIRE"
2999 "*
3000 {
3001 if (which_alternative == 0)
3002@@ -4173,7 +4227,7 @@
3003 (define_insn "negdi2_5200"
3004 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3005 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
3006- "TARGET_5200"
3007+ "TARGET_COLDFIRE"
3008 "*
3009 {
3010 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3011@@ -4186,7 +4240,7 @@
3012 ""
3013 "
3014 {
3015- if (TARGET_5200)
3016+ if (TARGET_COLDFIRE)
3017 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
3018 else
3019 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
3020@@ -4196,37 +4250,37 @@
3021 (define_insn "negsi2_internal"
3022 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
3023 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3024- "!TARGET_5200"
3025+ "!TARGET_COLDFIRE"
3026 "neg%.l %0")
3027
3028 (define_insn "negsi2_5200"
3029 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3030 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
3031- "TARGET_5200"
3032+ "TARGET_COLDFIRE"
3033 "neg%.l %0")
3034
3035 (define_insn "neghi2"
3036 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
3037 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
3038- "!TARGET_5200"
3039+ "!TARGET_COLDFIRE"
3040 "neg%.w %0")
3041
3042 (define_insn ""
3043 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
3044 (neg:HI (match_dup 0)))]
3045- "!TARGET_5200"
3046+ "!TARGET_COLDFIRE"
3047 "neg%.w %0")
3048
3049 (define_insn "negqi2"
3050 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
3051 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
3052- "!TARGET_5200"
3053+ "!TARGET_COLDFIRE"
3054 "neg%.b %0")
3055
3056 (define_insn ""
3057 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
3058 (neg:QI (match_dup 0)))]
3059- "!TARGET_5200"
3060+ "!TARGET_COLDFIRE"
3061 "neg%.b %0")
3062
3063 ;; If using software floating point, just flip the sign bit.
3064@@ -4466,7 +4520,7 @@
3065 (define_insn "one_cmpldi2"
3066 [(set (match_operand:DI 0 "nonimmediate_operand" "=dm")
3067 (not:DI (match_operand:DI 1 "general_operand" "0")))]
3068- "!TARGET_5200"
3069+ "!TARGET_COLDFIRE"
3070 "*
3071 {
3072 CC_STATUS_INIT;
3073@@ -4486,7 +4540,7 @@
3074 ""
3075 "
3076 {
3077- if (TARGET_5200)
3078+ if (TARGET_COLDFIRE)
3079 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
3080 else
3081 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
3082@@ -4496,37 +4550,37 @@
3083 (define_insn "one_cmplsi2_internal"
3084 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
3085 (not:SI (match_operand:SI 1 "general_operand" "0")))]
3086- "!TARGET_5200"
3087+ "!TARGET_COLDFIRE"
3088 "not%.l %0")
3089
3090 (define_insn "one_cmplsi2_5200"
3091 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3092 (not:SI (match_operand:SI 1 "general_operand" "0")))]
3093- "TARGET_5200"
3094+ "TARGET_COLDFIRE"
3095 "not%.l %0")
3096
3097 (define_insn "one_cmplhi2"
3098 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
3099 (not:HI (match_operand:HI 1 "general_operand" "0")))]
3100- "!TARGET_5200"
3101+ "!TARGET_COLDFIRE"
3102 "not%.w %0")
3103
3104 (define_insn ""
3105 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
3106 (not:HI (match_dup 0)))]
3107- "!TARGET_5200"
3108+ "!TARGET_COLDFIRE"
3109 "not%.w %0")
3110
3111 (define_insn "one_cmplqi2"
3112 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
3113 (not:QI (match_operand:QI 1 "general_operand" "0")))]
3114- "!TARGET_5200"
3115+ "!TARGET_COLDFIRE"
3116 "not%.b %0")
3117
3118 (define_insn ""
3119 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
3120 (not:QI (match_dup 0)))]
3121- "!TARGET_5200"
3122+ "!TARGET_COLDFIRE"
3123 "not%.b %0")
3124 \f
3125 ;; arithmetic shift instructions
3126@@ -4610,7 +4664,7 @@
3127 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3128 (ashift:DI (match_operand:DI 1 "general_operand" "0")
3129 (match_operand 2 "const_int_operand" "n")))]
3130- "(!TARGET_5200
3131+ "(!TARGET_COLDFIRE
3132 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
3133 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
3134 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
3135@@ -4642,7 +4696,7 @@
3136 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3137 (ashift:DI (match_operand:DI 1 "general_operand" "")
3138 (match_operand 2 "const_int_operand" "")))]
3139- "!TARGET_5200"
3140+ "!TARGET_COLDFIRE"
3141 "
3142 {
3143 /* ??? This is a named pattern like this is not allowed to FAIL based
3144@@ -4676,7 +4730,7 @@
3145 [(set (match_operand:SI 0 "register_operand" "=d")
3146 (ashift:SI (match_operand:SI 1 "register_operand" "0")
3147 (match_operand:SI 2 "const_int_operand" "n")))]
3148- "(! TARGET_68020 && !TARGET_5200
3149+ "(! TARGET_68020 && !TARGET_COLDFIRE
3150 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
3151 "*
3152 {
3153@@ -4705,28 +4759,28 @@
3154 [(set (match_operand:HI 0 "register_operand" "=d")
3155 (ashift:HI (match_operand:HI 1 "register_operand" "0")
3156 (match_operand:HI 2 "general_operand" "dI")))]
3157- "!TARGET_5200"
3158+ "!TARGET_COLDFIRE"
3159 "lsl%.w %2,%0")
3160
3161 (define_insn ""
3162 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
3163 (ashift:HI (match_dup 0)
3164 (match_operand:HI 1 "general_operand" "dI")))]
3165- "!TARGET_5200"
3166+ "!TARGET_COLDFIRE"
3167 "lsl%.w %1,%0")
3168
3169 (define_insn "ashlqi3"
3170 [(set (match_operand:QI 0 "register_operand" "=d")
3171 (ashift:QI (match_operand:QI 1 "register_operand" "0")
3172 (match_operand:QI 2 "general_operand" "dI")))]
3173- "!TARGET_5200"
3174+ "!TARGET_COLDFIRE"
3175 "lsl%.b %2,%0")
3176
3177 (define_insn ""
3178 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
3179 (ashift:QI (match_dup 0)
3180 (match_operand:QI 1 "general_operand" "dI")))]
3181- "!TARGET_5200"
3182+ "!TARGET_COLDFIRE"
3183 "lsl%.b %1,%0")
3184
3185 ;; On most 68k models, this makes faster code in a special case.
3186@@ -4744,7 +4798,7 @@
3187 [(set (match_operand:SI 0 "register_operand" "=d")
3188 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
3189 (match_operand:SI 2 "const_int_operand" "n")))]
3190- "(! TARGET_68020 && !TARGET_5200
3191+ "(! TARGET_68020 && !TARGET_COLDFIRE
3192 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
3193 "*
3194 {
3195@@ -4813,7 +4867,7 @@
3196 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3197 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
3198 (match_operand 2 "const_int_operand" "n")))]
3199- "(!TARGET_5200
3200+ "(!TARGET_COLDFIRE
3201 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
3202 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
3203 || INTVAL (operands[2]) == 31
3204@@ -4853,7 +4907,7 @@
3205 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3206 (ashiftrt:DI (match_operand:DI 1 "general_operand" "")
3207 (match_operand 2 "const_int_operand" "")))]
3208- "!TARGET_5200"
3209+ "!TARGET_COLDFIRE"
3210 "
3211 {
3212 /* ??? This is a named pattern like this is not allowed to FAIL based
3213@@ -4888,28 +4942,28 @@
3214 [(set (match_operand:HI 0 "register_operand" "=d")
3215 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
3216 (match_operand:HI 2 "general_operand" "dI")))]
3217- "!TARGET_5200"
3218+ "!TARGET_COLDFIRE"
3219 "asr%.w %2,%0")
3220
3221 (define_insn ""
3222 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
3223 (ashiftrt:HI (match_dup 0)
3224 (match_operand:HI 1 "general_operand" "dI")))]
3225- "!TARGET_5200"
3226+ "!TARGET_COLDFIRE"
3227 "asr%.w %1,%0")
3228
3229 (define_insn "ashrqi3"
3230 [(set (match_operand:QI 0 "register_operand" "=d")
3231 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
3232 (match_operand:QI 2 "general_operand" "dI")))]
3233- "!TARGET_5200"
3234+ "!TARGET_COLDFIRE"
3235 "asr%.b %2,%0")
3236
3237 (define_insn ""
3238 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
3239 (ashiftrt:QI (match_dup 0)
3240 (match_operand:QI 1 "general_operand" "dI")))]
3241- "!TARGET_5200"
3242+ "!TARGET_COLDFIRE"
3243 "asr%.b %1,%0")
3244 \f
3245 ;; logical shift instructions
3246@@ -4986,7 +5040,7 @@
3247 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
3248 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
3249 (match_operand 2 "const_int_operand" "n")))]
3250- "(!TARGET_5200
3251+ "(!TARGET_COLDFIRE
3252 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
3253 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
3254 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
3255@@ -5021,7 +5075,7 @@
3256 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3257 (lshiftrt:DI (match_operand:DI 1 "general_operand" "")
3258 (match_operand 2 "const_int_operand" "")))]
3259- "!TARGET_5200"
3260+ "!TARGET_COLDFIRE"
3261 "
3262 {
3263 /* ??? This is a named pattern like this is not allowed to FAIL based
3264@@ -5064,7 +5118,7 @@
3265 [(set (match_operand:SI 0 "register_operand" "=d")
3266 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
3267 (match_operand:SI 2 "const_int_operand" "n")))]
3268- "(! TARGET_68020 && !TARGET_5200
3269+ "(! TARGET_68020 && !TARGET_COLDFIRE
3270 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
3271 "*
3272 {
3273@@ -5084,28 +5138,28 @@
3274 [(set (match_operand:HI 0 "register_operand" "=d")
3275 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
3276 (match_operand:HI 2 "general_operand" "dI")))]
3277- "!TARGET_5200"
3278+ "!TARGET_COLDFIRE"
3279 "lsr%.w %2,%0")
3280
3281 (define_insn ""
3282 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
3283 (lshiftrt:HI (match_dup 0)
3284 (match_operand:HI 1 "general_operand" "dI")))]
3285- "!TARGET_5200"
3286+ "!TARGET_COLDFIRE"
3287 "lsr%.w %1,%0")
3288
3289 (define_insn "lshrqi3"
3290 [(set (match_operand:QI 0 "register_operand" "=d")
3291 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
3292 (match_operand:QI 2 "general_operand" "dI")))]
3293- "!TARGET_5200"
3294+ "!TARGET_COLDFIRE"
3295 "lsr%.b %2,%0")
3296
3297 (define_insn ""
3298 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
3299 (lshiftrt:QI (match_dup 0)
3300 (match_operand:QI 1 "general_operand" "dI")))]
3301- "!TARGET_5200"
3302+ "!TARGET_COLDFIRE"
3303 "lsr%.b %1,%0")
3304 \f
3305 ;; rotate instructions
3306@@ -5114,7 +5168,7 @@
3307 [(set (match_operand:SI 0 "register_operand" "=d")
3308 (rotate:SI (match_operand:SI 1 "register_operand" "0")
3309 (match_operand:SI 2 "general_operand" "dINO")))]
3310- "!TARGET_5200"
3311+ "!TARGET_COLDFIRE"
3312 "*
3313 {
3314 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
3315@@ -5132,7 +5186,7 @@
3316 [(set (match_operand:HI 0 "register_operand" "=d")
3317 (rotate:HI (match_operand:HI 1 "register_operand" "0")
3318 (match_operand:HI 2 "general_operand" "dIP")))]
3319- "!TARGET_5200"
3320+ "!TARGET_COLDFIRE"
3321 "*
3322 {
3323 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
3324@@ -5148,7 +5202,7 @@
3325 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
3326 (rotate:HI (match_dup 0)
3327 (match_operand:HI 1 "general_operand" "dIP")))]
3328- "!TARGET_5200"
3329+ "!TARGET_COLDFIRE"
3330 "*
3331 {
3332 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
3333@@ -5164,7 +5218,7 @@
3334 [(set (match_operand:QI 0 "register_operand" "=d")
3335 (rotate:QI (match_operand:QI 1 "register_operand" "0")
3336 (match_operand:QI 2 "general_operand" "dI")))]
3337- "!TARGET_5200"
3338+ "!TARGET_COLDFIRE"
3339 "*
3340 {
3341 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
3342@@ -5180,7 +5234,7 @@
3343 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
3344 (rotate:QI (match_dup 0)
3345 (match_operand:QI 1 "general_operand" "dI")))]
3346- "!TARGET_5200"
3347+ "!TARGET_COLDFIRE"
3348 "*
3349 {
3350 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
3351@@ -5196,35 +5250,35 @@
3352 [(set (match_operand:SI 0 "register_operand" "=d")
3353 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
3354 (match_operand:SI 2 "general_operand" "dI")))]
3355- "!TARGET_5200"
3356+ "!TARGET_COLDFIRE"
3357 "ror%.l %2,%0")
3358
3359 (define_insn "rotrhi3"
3360 [(set (match_operand:HI 0 "register_operand" "=d")
3361 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
3362 (match_operand:HI 2 "general_operand" "dI")))]
3363- "!TARGET_5200"
3364+ "!TARGET_COLDFIRE"
3365 "ror%.w %2,%0")
3366
3367 (define_insn ""
3368 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
3369 (rotatert:HI (match_dup 0)
3370 (match_operand:HI 1 "general_operand" "dI")))]
3371- "!TARGET_5200"
3372+ "!TARGET_COLDFIRE"
3373 "ror%.w %1,%0")
3374
3375 (define_insn "rotrqi3"
3376 [(set (match_operand:QI 0 "register_operand" "=d")
3377 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
3378 (match_operand:QI 2 "general_operand" "dI")))]
3379- "!TARGET_5200"
3380+ "!TARGET_COLDFIRE"
3381 "ror%.b %2,%0")
3382
3383 (define_insn ""
3384 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
3385 (rotatert:QI (match_dup 0)
3386 (match_operand:QI 1 "general_operand" "dI")))]
3387- "!TARGET_5200"
3388+ "!TARGET_COLDFIRE"
3389 "ror%.b %1,%0")
3390 \f
3391
3392@@ -5688,7 +5742,7 @@
3393 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
3394 (match_operator 1 "valid_dbcc_comparison_p"
3395 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
3396- "! TARGET_5200"
3397+ "! TARGET_COLDFIRE"
3398 "*
3399 {
3400 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
3401@@ -5698,7 +5752,7 @@
3402 [(set (match_operand:QI 0 "nonimmediate_operand" "=d")
3403 (match_operator 1 "valid_dbcc_comparison_p"
3404 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
3405- "TARGET_5200"
3406+ "TARGET_COLDFIRE"
3407 "*
3408 {
3409 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
3410@@ -5709,7 +5763,7 @@
3411 (match_operator 1 "valid_dbcc_comparison_p"
3412 [(match_operand:DI 2 "general_operand" "ro,r")
3413 (match_operand:DI 3 "general_operand" "r,ro")]))]
3414- "! TARGET_5200"
3415+ "! TARGET_COLDFIRE"
3416 "*
3417 {
3418 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
3419@@ -5720,7 +5774,7 @@
3420 (match_operator 1 "valid_dbcc_comparison_p"
3421 [(match_operand:DI 2 "general_operand" "ro,r")
3422 (match_operand:DI 3 "general_operand" "r,ro")]))]
3423- "TARGET_5200"
3424+ "TARGET_COLDFIRE"
3425 "*
3426 {
3427 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
3428@@ -6167,7 +6221,7 @@
3429 #endif
3430 }
3431 operands[4] = gen_label_rtx();
3432- if (TARGET_68020 || TARGET_5200)
3433+ if (TARGET_68020 || TARGET_COLDFIRE)
3434 {
3435 #ifdef MOTOROLA
3436 output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands);
3437@@ -6246,7 +6300,7 @@
3438 return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\";
3439 #endif
3440 }
3441- if (TARGET_68020 || TARGET_5200)
3442+ if (TARGET_68020 || TARGET_COLDFIRE)
3443 {
3444 #ifdef MOTOROLA
3445 return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\";
3446@@ -6301,7 +6355,7 @@
3447 }
3448 }
3449 CC_STATUS_INIT;
3450- if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
3451+ if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
3452 output_asm_insn(\"tst%.l %0\", operands);
3453 else
3454 {
3455@@ -6353,7 +6407,7 @@
3456 }
3457 }
3458 CC_STATUS_INIT;
3459- if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
3460+ if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
3461 output_asm_insn(\"tst%.l %0\", operands);
3462 else
3463 {
3464@@ -6972,7 +7026,7 @@
3465 #else
3466 #ifdef SGS
3467 #ifdef ASM_OUTPUT_CASE_LABEL
3468- if (TARGET_5200)
3469+ if (TARGET_COLDFIRE)
3470 {
3471 if (ADDRESS_REG_P (operands[0]))
3472 return \"jmp 6(%%pc,%0.l)\";
3473@@ -6982,7 +7036,7 @@
3474 else
3475 return \"jmp 6(%%pc,%0.w)\";
3476 #else
3477- if (TARGET_5200)
3478+ if (TARGET_COLDFIRE)
3479 {
3480 if (ADDRESS_REG_P (operands[0]))
3481 {
3482@@ -7011,7 +7065,7 @@
3483 }
3484 #endif
3485 #else /* not SGS */
3486- if (TARGET_5200)
3487+ if (TARGET_COLDFIRE)
3488 {
3489 if (ADDRESS_REG_P (operands[0]))
3490 {
3491@@ -7053,7 +7107,7 @@
3492 (set (match_dup 0)
3493 (plus:HI (match_dup 0)
3494 (const_int -1)))]
3495- "!TARGET_5200"
3496+ "!TARGET_COLDFIRE"
3497 "*
3498 {
3499 CC_STATUS_INIT;
3500@@ -7096,7 +7150,7 @@
3501 (set (match_dup 0)
3502 (plus:SI (match_dup 0)
3503 (const_int -1)))]
3504- "!TARGET_5200"
3505+ "!TARGET_COLDFIRE"
3506 "*
3507 {
3508 CC_STATUS_INIT;
3509@@ -7143,7 +7197,7 @@
3510 (set (match_dup 0)
3511 (plus:HI (match_dup 0)
3512 (const_int -1)))]
3513- "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
3514+ "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)"
3515 "*
3516 {
3517 CC_STATUS_INIT;
3518@@ -7202,7 +7256,7 @@
3519 (set (match_dup 0)
3520 (plus:SI (match_dup 0)
3521 (const_int -1)))]
3522- "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
3523+ "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)"
3524 "*
3525 {
3526 CC_STATUS_INIT;
3527@@ -7563,7 +7617,7 @@
3528 #ifndef NO_ADDSUB_Q
3529 if (INTVAL (xoperands[1]) <= 8)
3530 {
3531- if (!TARGET_5200)
3532+ if (!TARGET_COLDFIRE)
3533 output_asm_insn (\"addq%.w %1,%0\", xoperands);
3534 else
3535 output_asm_insn (\"addq%.l %1,%0\", xoperands);
3536@@ -7613,7 +7667,7 @@
3537 #ifndef NO_ADDSUB_Q
3538 if (INTVAL (xoperands[1]) <= 8)
3539 {
3540- if (!TARGET_5200)
3541+ if (!TARGET_COLDFIRE)
3542 output_asm_insn (\"addq%.w %1,%0\", xoperands);
3543 else
3544 output_asm_insn (\"addq%.l %1,%0\", xoperands);
3545@@ -7664,7 +7718,7 @@
3546 xoperands[2]
3547 = gen_rtx_MEM (QImode, plus_constant (stack_pointer_rtx, 3));
3548 xoperands[3] = stack_pointer_rtx;
3549- if (!TARGET_5200)
3550+ if (!TARGET_COLDFIRE)
3551 output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
3552 else
3553 output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands);
3554@@ -7686,7 +7740,7 @@
3555 || GET_CODE (operands[0]) == MEM)
3556 /* clr insns on 68000 read before writing.
3557 This isn't so on the 68010, but we have no TARGET_68010. */
3558- && ((TARGET_68020 || TARGET_5200)
3559+ && ((TARGET_68020 || TARGET_COLDFIRE)
3560 || !(GET_CODE (operands[0]) == MEM
3561 && MEM_VOLATILE_P (operands[0]))))
3562 return \"clr%.w %0\";
3563@@ -7726,7 +7780,7 @@
3564 (set (match_dup 0)
3565 (plus:HI (match_dup 0)
3566 (const_int -1)))])]
3567- "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
3568+ "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
3569 "*
3570 {
3571 CC_STATUS_INIT;
3572@@ -7749,7 +7803,7 @@
3573 (set (match_dup 0)
3574 (plus:SI (match_dup 0)
3575 (const_int -1)))])]
3576- "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
3577+ "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
3578 "*
3579 {
3580 CC_STATUS_INIT;
3581@@ -7773,7 +7827,7 @@
3582 (set (match_dup 0)
3583 (plus:HI (match_dup 0)
3584 (const_int -1)))])]
3585- "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
3586+ "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
3587 "*
3588 {
3589 CC_STATUS_INIT;
3590@@ -7797,7 +7851,7 @@
3591 (set (match_dup 0)
3592 (plus:SI (match_dup 0)
3593 (const_int -1)))])]
3594- "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
3595+ "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
3596 "*
3597 {
3598 CC_STATUS_INIT;
3599diff -Nru gcc-3.3.1.orig/gcc/config/m68k/m68kelf.h gcc-3.3.1/gcc/config/m68k/m68kelf.h
3600--- gcc-3.3.1.orig/gcc/config/m68k/m68kelf.h 2003-01-28 23:18:19.000000000 +0100
3601+++ gcc-3.3.1/gcc/config/m68k/m68kelf.h 2003-07-25 00:25:30.000000000 +0200
3602@@ -75,7 +75,7 @@
3603
3604 #define ASM_RETURN_CASE_JUMP \
3605 do { \
3606- if (TARGET_5200) \
3607+ if (TARGET_COLDFIRE) \
3608 { \
3609 if (ADDRESS_REG_P (operands[0])) \
3610 return "jmp %%pc@(2,%0:l)"; \
3611diff -Nru gcc-3.3.1.orig/gcc/config/m68k/mot3300.h gcc-3.3.1/gcc/config/m68k/mot3300.h
3612--- gcc-3.3.1.orig/gcc/config/m68k/mot3300.h 2003-01-28 23:18:19.000000000 +0100
3613+++ gcc-3.3.1/gcc/config/m68k/mot3300.h 2003-07-25 00:25:30.000000000 +0200
3614@@ -439,7 +439,7 @@
3615
3616 #define ASM_RETURN_CASE_JUMP \
3617 do { \
3618- if (TARGET_5200) \
3619+ if (TARGET_COLDFIRE) \
3620 { \
3621 if (ADDRESS_REG_P (operands[0])) \
3622 return "jmp 8(%%pc,%0.l)"; \
3623diff -Nru gcc-3.3.1.orig/gcc/config/m68k/netbsd-elf.h gcc-3.3.1/gcc/config/m68k/netbsd-elf.h
3624--- gcc-3.3.1.orig/gcc/config/m68k/netbsd-elf.h 2003-01-28 23:18:19.000000000 +0100
3625+++ gcc-3.3.1/gcc/config/m68k/netbsd-elf.h 2003-07-25 00:25:30.000000000 +0200
3626@@ -217,7 +217,7 @@
3627 #undef ASM_OUTPUT_CASE_LABEL
3628 #define ASM_RETURN_CASE_JUMP \
3629 do { \
3630- if (TARGET_5200) \
3631+ if (TARGET_COLDFIRE) \
3632 { \
3633 if (ADDRESS_REG_P (operands[0])) \
3634 return "jmp %%pc@(2,%0:l)"; \
3635diff -Nru gcc-3.3.1.orig/gcc/config/m68k/pbb.h gcc-3.3.1/gcc/config/m68k/pbb.h
3636--- gcc-3.3.1.orig/gcc/config/m68k/pbb.h 2003-01-28 23:18:20.000000000 +0100
3637+++ gcc-3.3.1/gcc/config/m68k/pbb.h 2003-07-25 00:25:30.000000000 +0200
3638@@ -111,7 +111,7 @@
3639
3640 #define ASM_RETURN_CASE_JUMP \
3641 do { \
3642- if (TARGET_5200) \
3643+ if (TARGET_COLDFIRE) \
3644 { \
3645 if (ADDRESS_REG_P (operands[0])) \
3646 return "jmp %%pc@(2,%0:l)"; \
3647diff -Nru gcc-3.3.1.orig/gcc/config/m68k/t-m68kelf gcc-3.3.1/gcc/config/m68k/t-m68kelf
3648--- gcc-3.3.1.orig/gcc/config/m68k/t-m68kelf 2002-01-24 02:21:48.000000000 +0100
3649+++ gcc-3.3.1/gcc/config/m68k/t-m68kelf 2003-07-25 00:25:30.000000000 +0200
3650@@ -12,11 +12,14 @@
3651 echo '#define EXTFLOAT' > xfgnulib.c
3652 cat $(srcdir)/config/m68k/fpgnulib.c >> xfgnulib.c
3653
3654-MULTILIB_OPTIONS = m68000/m68020/m5200/mcpu32/m68040/m68060 m68881/msoft-float
3655+MULTILIB_OPTIONS = m68000/m68020/m5200/m5206e/m528x/m5307/m5407/mcpu32/m68040/m68060 m68881/msoft-float
3656 MULTILIB_DIRNAMES =
3657-MULTILIB_MATCHES = m68000=mc68000 m68000=m68302 mcpu32=m68332 m68020=mc68020
3658-MULTILIB_EXCEPTIONS = m68000/msoft-float m5200/m68881 m5200/msoft-float mcpu32/m68881 mcpu32/msoft-float m68040/m68881 m68040/msoft-float m68060/m68881 m68060/msoft-float
3659-
3660+MULTILIB_MATCHES = m68000=mc68000 m68000=m68302 mcpu32=m68332 m68020=mc68020 m5206e=m5272
3661+MULTILIB_EXCEPTIONS = m68000/msoft-float m5200/m68881 m5200/msoft-float \
3662+ m5206e/m68881 m5206e/msoft-float m528x/m68881 m528x/msoft-float \
3663+ m5307/m68881 m5307/msoft-float m5407/m68881 m5407/msoft-float \
3664+ mcpu32/m68881 mcpu32/msoft-float m68040/m68881 m68040/msoft-float \
3665+ m68060/m68881 m68060/msoft-float
3666 LIBGCC = stmp-multilib
3667 INSTALL_LIBGCC = install-multilib
3668
3669diff -Nru gcc-3.3.1.orig/gcc/longlong.h gcc-3.3.1/gcc/longlong.h
3670--- gcc-3.3.1.orig/gcc/longlong.h 2002-10-03 22:39:08.000000000 +0200
3671+++ gcc-3.3.1/gcc/longlong.h 2003-07-25 00:25:30.000000000 +0200
3672@@ -448,7 +448,42 @@
3673 "dmi" ((USItype) (d)))
3674
3675 #else /* not mc68020 */
3676-#if !defined(__mcf5200__)
3677+#if defined(__mcoldfire__)
3678+#define umul_ppmm(xh, xl, a, b) \
3679+ __asm__ ("| Inlined umul_ppmm\n" \
3680+ " move%.l %2,%/d0\n" \
3681+ " move%.l %3,%/d1\n" \
3682+ " move%.l %/d0,%/d2\n" \
3683+ " swap %/d0\n" \
3684+ " move%.l %/d1,%/d3\n" \
3685+ " swap %/d1\n" \
3686+ " move%.w %/d2,%/d4\n" \
3687+ " mulu %/d3,%/d4\n" \
3688+ " mulu %/d1,%/d2\n" \
3689+ " mulu %/d0,%/d3\n" \
3690+ " mulu %/d0,%/d1\n" \
3691+ " move%.l %/d4,%/d0\n" \
3692+ " clr%.w %/d0\n" \
3693+ " swap %/d0\n" \
3694+ " add%.l %/d0,%/d2\n" \
3695+ " add%.l %/d3,%/d2\n" \
3696+ " jcc 1f\n" \
3697+ " add%.l %#65536,%/d1\n" \
3698+ "1: swap %/d2\n" \
3699+ " moveq %#0,%/d0\n" \
3700+ " move%.w %/d2,%/d0\n" \
3701+ " move%.w %/d4,%/d2\n" \
3702+ " move%.l %/d2,%1\n" \
3703+ " add%.l %/d1,%/d0\n" \
3704+ " move%.l %/d0,%0" \
3705+ : "=g" ((USItype) (xh)), \
3706+ "=g" ((USItype) (xl)) \
3707+ : "g" ((USItype) (a)), \
3708+ "g" ((USItype) (b)) \
3709+ : "d0", "d1", "d2", "d3", "d4")
3710+#define UMUL_TIME 100
3711+#define UDIV_TIME 400
3712+#else /* not ColdFire */
3713 /* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */
3714 #define umul_ppmm(xh, xl, a, b) \
3715 __asm__ ("| Inlined umul_ppmm\n" \
3716@@ -484,7 +519,7 @@
3717 : "d0", "d1", "d2", "d3", "d4")
3718 #define UMUL_TIME 100
3719 #define UDIV_TIME 400
3720-#endif /* not mcf5200 */
3721+#endif /* not ColdFire */
3722 #endif /* not mc68020 */
3723
3724 /* The '020, '030, '040 and '060 have bitfield insns. */
Cross m68k GNU binary utility development utilities - gcc
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