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1 | --- cpqarrayd-2.2/configure.ac.orig 2005-07-28 16:33:41.000000000 +0200 |
2 | +++ cpqarrayd-2.2/configure.ac 2006-03-09 11:31:02.000000000 +0100 | |
3 | @@ -19,7 +19,7 @@ | |
4 | dnl Check for pathed kernel sources with ida_ioctl.h | |
5 | AC_MSG_CHECKING(for SmartArray header directories) | |
6 | found_kernel_dir="" | |
7 | -for kernel_dir in /usr/src/linux /usr/src/linux-2.4 | |
8 | +for kernel_dir in . | |
9 | do | |
10 | if test -d $kernel_dir ; then | |
11 | CFLAGS="$CFLAGS -I$kernel_dir/include -I$kernel_dir/drivers/block" | |
12 | diff -Nur cpqarrayd-2.2/drivers.orig/block/cpqarray.h cpqarrayd-2.2/drivers/block/cpqarray.h | |
13 | --- cpqarrayd-2.2/drivers.orig/block/cpqarray.h 1970-01-01 01:00:00.000000000 +0100 | |
14 | +++ cpqarrayd-2.2/drivers/block/cpqarray.h 2005-11-17 16:51:31.000000000 +0100 | |
15 | @@ -0,0 +1,132 @@ | |
16 | +/* | |
17 | + * Disk Array driver for Compaq SMART2 Controllers | |
18 | + * Copyright 1998 Compaq Computer Corporation | |
19 | + * | |
20 | + * This program is free software; you can redistribute it and/or modify | |
21 | + * it under the terms of the GNU General Public License as published by | |
22 | + * the Free Software Foundation; either version 2 of the License, or | |
23 | + * (at your option) any later version. | |
24 | + * | |
25 | + * This program is distributed in the hope that it will be useful, | |
26 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
27 | + * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
28 | + * NON INFRINGEMENT. See the GNU General Public License for more details. | |
29 | + * | |
30 | + * You should have received a copy of the GNU General Public License | |
31 | + * along with this program; if not, write to the Free Software | |
32 | + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
33 | + * | |
34 | + * Questions/Comments/Bugfixes to arrays@compaq.com | |
35 | + * | |
36 | + * If you want to make changes, improve or add functionality to this | |
37 | + * driver, you'll probably need the Compaq Array Controller Interface | |
38 | + * Specificiation (Document number ECG086/1198) | |
39 | + */ | |
40 | +#ifndef CPQARRAY_H | |
41 | +#define CPQARRAY_H | |
42 | + | |
43 | +#ifdef __KERNEL__ | |
44 | +#include <linux/blkdev.h> | |
45 | +#include <linux/locks.h> | |
46 | +#include <linux/slab.h> | |
47 | +#include <linux/proc_fs.h> | |
48 | +#include <linux/timer.h> | |
49 | +#endif | |
50 | + | |
51 | +#include "ida_cmd.h" | |
52 | + | |
53 | +#define IO_OK 0 | |
54 | +#define IO_ERROR 1 | |
55 | +#define NWD 16 | |
56 | +#define NWD_SHIFT 4 | |
57 | +#define IDA_MAX_PART 16 | |
58 | + | |
59 | +#define IDA_TIMER (5*HZ) | |
60 | +#define IDA_TIMEOUT (10*HZ) | |
61 | + | |
62 | +#define MISC_NONFATAL_WARN 0x01 | |
63 | + | |
64 | +typedef struct { | |
65 | + unsigned blk_size; | |
66 | + unsigned nr_blks; | |
67 | + unsigned cylinders; | |
68 | + unsigned heads; | |
69 | + unsigned sectors; | |
70 | + int usage_count; | |
71 | +} drv_info_t; | |
72 | + | |
73 | +#ifdef __KERNEL__ | |
74 | + | |
75 | +struct ctlr_info; | |
76 | +typedef struct ctlr_info ctlr_info_t; | |
77 | + | |
78 | +struct access_method { | |
79 | + void (*submit_command)(ctlr_info_t *h, cmdlist_t *c); | |
80 | + void (*set_intr_mask)(ctlr_info_t *h, unsigned long val); | |
81 | + unsigned long (*fifo_full)(ctlr_info_t *h); | |
82 | + unsigned long (*intr_pending)(ctlr_info_t *h); | |
83 | + unsigned long (*command_completed)(ctlr_info_t *h); | |
84 | +}; | |
85 | + | |
86 | +struct board_type { | |
87 | + __u32 board_id; | |
88 | + char *product_name; | |
89 | + struct access_method *access; | |
90 | +}; | |
91 | + | |
92 | +struct ctlr_info { | |
93 | + int ctlr; | |
94 | + char devname[8]; | |
95 | + __u32 log_drv_map; | |
96 | + __u32 drv_assign_map; | |
97 | + __u32 drv_spare_map; | |
98 | + __u32 mp_failed_drv_map; | |
99 | + | |
100 | + char firm_rev[4]; | |
101 | + struct pci_dev *pdev; | |
102 | + int ctlr_sig; | |
103 | + | |
104 | + int log_drives; | |
105 | + int highest_lun; | |
106 | + int phys_drives; | |
107 | + | |
108 | + struct pci_dev *pci_dev; /* NULL if EISA */ | |
109 | + __u32 board_id; | |
110 | + char *product_name; | |
111 | + | |
112 | + void *vaddr; | |
113 | + unsigned long paddr; | |
114 | + unsigned long io_mem_addr; | |
115 | + unsigned long io_mem_length; | |
116 | + int intr; | |
117 | + int usage_count; | |
118 | + drv_info_t drv[NWD]; | |
119 | + struct proc_dir_entry *proc; | |
120 | + | |
121 | + struct access_method access; | |
122 | + | |
123 | + cmdlist_t *reqQ; | |
124 | + cmdlist_t *cmpQ; | |
125 | + cmdlist_t *cmd_pool; | |
126 | + dma_addr_t cmd_pool_dhandle; | |
127 | + __u32 *cmd_pool_bits; | |
128 | + | |
129 | + unsigned int Qdepth; | |
130 | + unsigned int maxQsinceinit; | |
131 | + | |
132 | + unsigned int nr_requests; | |
133 | + unsigned int nr_allocs; | |
134 | + unsigned int nr_frees; | |
135 | + struct timer_list timer; | |
136 | + unsigned int misc_tflags; | |
137 | + // Disk structures we need to pass back | |
138 | + struct gendisk gendisk; | |
139 | + // Index by Minor Numbers | |
140 | + struct hd_struct hd[256]; | |
141 | + int sizes[256]; | |
142 | + int blocksizes[256]; | |
143 | + int hardsizes[256]; | |
144 | +}; | |
145 | +#endif | |
146 | + | |
147 | +#endif /* CPQARRAY_H */ | |
148 | diff -Nur cpqarrayd-2.2/drivers.orig/block/ida_cmd.h cpqarrayd-2.2/drivers/block/ida_cmd.h | |
149 | --- cpqarrayd-2.2/drivers.orig/block/ida_cmd.h 1970-01-01 01:00:00.000000000 +0100 | |
150 | +++ cpqarrayd-2.2/drivers/block/ida_cmd.h 2005-11-17 16:51:31.000000000 +0100 | |
151 | @@ -0,0 +1,351 @@ | |
152 | +/* | |
153 | + * Disk Array driver for Compaq SMART2 Controllers | |
154 | + * Copyright 1998 Compaq Computer Corporation | |
155 | + * | |
156 | + * This program is free software; you can redistribute it and/or modify | |
157 | + * it under the terms of the GNU General Public License as published by | |
158 | + * the Free Software Foundation; either version 2 of the License, or | |
159 | + * (at your option) any later version. | |
160 | + * | |
161 | + * This program is distributed in the hope that it will be useful, | |
162 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
163 | + * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
164 | + * NON INFRINGEMENT. See the GNU General Public License for more details. | |
165 | + * | |
166 | + * You should have received a copy of the GNU General Public License | |
167 | + * along with this program; if not, write to the Free Software | |
168 | + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
169 | + * | |
170 | + * Questions/Comments/Bugfixes to arrays@compaq.com | |
171 | + * | |
172 | + */ | |
173 | +#ifndef ARRAYCMD_H | |
174 | +#define ARRAYCMD_H | |
175 | + | |
176 | +#include <asm/types.h> | |
177 | +#if 0 | |
178 | +#include <linux/blkdev.h> | |
179 | +#endif | |
180 | + | |
181 | +/* for the Smart Array 42XX cards */ | |
182 | +#define S42XX_REQUEST_PORT_OFFSET 0x40 | |
183 | +#define S42XX_REPLY_INTR_MASK_OFFSET 0x34 | |
184 | +#define S42XX_REPLY_PORT_OFFSET 0x44 | |
185 | +#define S42XX_INTR_STATUS 0x30 | |
186 | + | |
187 | +#define S42XX_INTR_OFF 0x08 | |
188 | +#define S42XX_INTR_PENDING 0x08 | |
189 | + | |
190 | +#define COMMAND_FIFO 0x04 | |
191 | +#define COMMAND_COMPLETE_FIFO 0x08 | |
192 | +#define INTR_MASK 0x0C | |
193 | +#define INTR_STATUS 0x10 | |
194 | +#define INTR_PENDING 0x14 | |
195 | + | |
196 | +#define FIFO_NOT_EMPTY 0x01 | |
197 | +#define FIFO_NOT_FULL 0x02 | |
198 | + | |
199 | +#define BIG_PROBLEM 0x40 | |
200 | +#define LOG_NOT_CONF 2 | |
201 | + | |
202 | +#pragma pack(1) | |
203 | +typedef struct { | |
204 | + __u32 size; | |
205 | + __u32 addr; | |
206 | +} sg_t; | |
207 | + | |
208 | +#define RCODE_NONFATAL 0x02 | |
209 | +#define RCODE_FATAL 0x04 | |
210 | +#define RCODE_INVREQ 0x10 | |
211 | +typedef struct { | |
212 | + __u16 next; | |
213 | + __u8 cmd; | |
214 | + __u8 rcode; | |
215 | + __u32 blk; | |
216 | + __u16 blk_cnt; | |
217 | + __u8 sg_cnt; | |
218 | + __u8 reserved; | |
219 | +} rhdr_t; | |
220 | + | |
221 | +#define SG_MAX 32 | |
222 | +typedef struct { | |
223 | + rhdr_t hdr; | |
224 | + sg_t sg[SG_MAX]; | |
225 | + __u32 bp; | |
226 | +} rblk_t; | |
227 | + | |
228 | +typedef struct { | |
229 | + __u8 unit; | |
230 | + __u8 prio; | |
231 | + __u16 size; | |
232 | +} chdr_t; | |
233 | + | |
234 | +#define CMD_RWREQ 0x00 | |
235 | +#define CMD_IOCTL_PEND 0x01 | |
236 | + | |
237 | +typedef struct cmdlist { | |
238 | + chdr_t hdr; | |
239 | + rblk_t req; | |
240 | + __u32 size; | |
241 | + int retry_cnt; | |
242 | + __u32 busaddr; | |
243 | + int ctlr; | |
244 | + struct cmdlist *prev; | |
245 | + struct cmdlist *next; | |
246 | + struct request *rq; | |
247 | + struct completion *waiting; | |
248 | + int type; | |
249 | +} cmdlist_t; | |
250 | + | |
251 | +#define ID_CTLR 0x11 | |
252 | +typedef struct { | |
253 | + __u8 nr_drvs; | |
254 | + __u32 cfg_sig; | |
255 | + __u8 firm_rev[4]; | |
256 | + __u8 rom_rev[4]; | |
257 | + __u8 hw_rev; | |
258 | + __u32 bb_rev; | |
259 | + __u32 drv_present_map; | |
260 | + __u32 ext_drv_map; | |
261 | + __u32 board_id; | |
262 | + __u8 cfg_error; | |
263 | + __u32 non_disk_bits; | |
264 | + __u8 bad_ram_addr; | |
265 | + __u8 cpu_rev; | |
266 | + __u8 pdpi_rev; | |
267 | + __u8 epic_rev; | |
268 | + __u8 wcxc_rev; | |
269 | + __u8 marketing_rev; | |
270 | + __u8 ctlr_flags; | |
271 | + __u8 host_flags; | |
272 | + __u8 expand_dis; | |
273 | + __u8 scsi_chips; | |
274 | + __u32 max_req_blocks; | |
275 | + __u32 ctlr_clock; | |
276 | + __u8 drvs_per_bus; | |
277 | + __u16 big_drv_present_map[8]; | |
278 | + __u16 big_ext_drv_map[8]; | |
279 | + __u16 big_non_disk_map[8]; | |
280 | + __u16 task_flags; | |
281 | + __u8 icl_bus; | |
282 | + __u8 red_modes; | |
283 | + __u8 cur_red_mode; | |
284 | + __u8 red_ctlr_stat; | |
285 | + __u8 red_fail_reason; | |
286 | + __u8 reserved[403]; | |
287 | +} id_ctlr_t; | |
288 | + | |
289 | +typedef struct { | |
290 | + __u16 cyl; | |
291 | + __u8 heads; | |
292 | + __u8 xsig; | |
293 | + __u8 psectors; | |
294 | + __u16 wpre; | |
295 | + __u8 maxecc; | |
296 | + __u8 drv_ctrl; | |
297 | + __u16 pcyls; | |
298 | + __u8 pheads; | |
299 | + __u16 landz; | |
300 | + __u8 sect_per_track; | |
301 | + __u8 cksum; | |
302 | +} drv_param_t; | |
303 | + | |
304 | +#define ID_LOG_DRV 0x10 | |
305 | +typedef struct { | |
306 | + __u16 blk_size; | |
307 | + __u32 nr_blks; | |
308 | + drv_param_t drv; | |
309 | + __u8 fault_tol; | |
310 | + __u8 reserved; | |
311 | + __u8 bios_disable; | |
312 | +} id_log_drv_t; | |
313 | + | |
314 | +#define ID_LOG_DRV_EXT 0x18 | |
315 | +typedef struct { | |
316 | + __u32 log_drv_id; | |
317 | + __u8 log_drv_label[64]; | |
318 | + __u8 reserved[418]; | |
319 | +} id_log_drv_ext_t; | |
320 | + | |
321 | +#define SENSE_LOG_DRV_STAT 0x12 | |
322 | +typedef struct { | |
323 | + __u8 status; | |
324 | + __u32 fail_map; | |
325 | + __u16 read_err[32]; | |
326 | + __u16 write_err[32]; | |
327 | + __u8 drv_err_data[256]; | |
328 | + __u8 drq_timeout[32]; | |
329 | + __u32 blks_to_recover; | |
330 | + __u8 drv_recovering; | |
331 | + __u16 remap_cnt[32]; | |
332 | + __u32 replace_drv_map; | |
333 | + __u32 act_spare_map; | |
334 | + __u8 spare_stat; | |
335 | + __u8 spare_repl_map[32]; | |
336 | + __u32 repl_ok_map; | |
337 | + __u8 media_exch; | |
338 | + __u8 cache_fail; | |
339 | + __u8 expn_fail; | |
340 | + __u8 unit_flags; | |
341 | + __u16 big_fail_map[8]; | |
342 | + __u16 big_remap_map[128]; | |
343 | + __u16 big_repl_map[8]; | |
344 | + __u16 big_act_spare_map[8]; | |
345 | + __u8 big_spar_repl_map[128]; | |
346 | + __u16 big_repl_ok_map[8]; | |
347 | + __u8 big_drv_rebuild; | |
348 | + __u8 reserved[36]; | |
349 | +} sense_log_drv_stat_t; | |
350 | + | |
351 | +#define START_RECOVER 0x13 | |
352 | + | |
353 | +#define ID_PHYS_DRV 0x15 | |
354 | +typedef struct { | |
355 | + __u8 scsi_bus; | |
356 | + __u8 scsi_id; | |
357 | + __u16 blk_size; | |
358 | + __u32 nr_blks; | |
359 | + __u32 rsvd_blks; | |
360 | + __u8 drv_model[40]; | |
361 | + __u8 drv_sn[40]; | |
362 | + __u8 drv_fw[8]; | |
363 | + __u8 scsi_iq_bits; | |
364 | + __u8 compaq_drv_stmp; | |
365 | + __u8 last_fail; | |
366 | + __u8 phys_drv_flags; | |
367 | + __u8 phys_drv_flags1; | |
368 | + __u8 scsi_lun; | |
369 | + __u8 phys_drv_flags2; | |
370 | + __u8 reserved; | |
371 | + __u32 spi_speed_rules; | |
372 | + __u8 phys_connector[2]; | |
373 | + __u8 phys_box_on_bus; | |
374 | + __u8 phys_bay_in_box; | |
375 | +} id_phys_drv_t; | |
376 | + | |
377 | +#define BLINK_DRV_LEDS 0x16 | |
378 | +typedef struct { | |
379 | + __u32 blink_duration; | |
380 | + __u32 reserved; | |
381 | + __u8 blink[256]; | |
382 | + __u8 reserved1[248]; | |
383 | +} blink_drv_leds_t; | |
384 | + | |
385 | +#define SENSE_BLINK_LEDS 0x17 | |
386 | +typedef struct { | |
387 | + __u32 blink_duration; | |
388 | + __u32 btime_elap; | |
389 | + __u8 blink[256]; | |
390 | + __u8 reserved1[248]; | |
391 | +} sense_blink_leds_t; | |
392 | + | |
393 | +#define IDA_READ 0x20 | |
394 | +#define IDA_WRITE 0x30 | |
395 | +#define IDA_WRITE_MEDIA 0x31 | |
396 | +#define RESET_TO_DIAG 0x40 | |
397 | +#define DIAG_PASS_THRU 0x41 | |
398 | + | |
399 | +#define SENSE_CONFIG 0x50 | |
400 | +#define SET_CONFIG 0x51 | |
401 | +typedef struct { | |
402 | + __u32 cfg_sig; | |
403 | + __u16 compat_port; | |
404 | + __u8 data_dist_mode; | |
405 | + __u8 surf_an_ctrl; | |
406 | + __u16 ctlr_phys_drv; | |
407 | + __u16 log_unit_phys_drv; | |
408 | + __u16 fault_tol_mode; | |
409 | + __u8 phys_drv_param[16]; | |
410 | + drv_param_t drv; | |
411 | + __u32 drv_asgn_map; | |
412 | + __u16 dist_factor; | |
413 | + __u32 spare_asgn_map; | |
414 | + __u8 reserved[6]; | |
415 | + __u16 os; | |
416 | + __u8 ctlr_order; | |
417 | + __u8 extra_info; | |
418 | + __u32 data_offs; | |
419 | + __u8 parity_backedout_write_drvs; | |
420 | + __u8 parity_dist_mode; | |
421 | + __u8 parity_shift_fact; | |
422 | + __u8 bios_disable_flag; | |
423 | + __u32 blks_on_vol; | |
424 | + __u32 blks_per_drv; | |
425 | + __u8 scratch[16]; | |
426 | + __u16 big_drv_map[8]; | |
427 | + __u16 big_spare_map[8]; | |
428 | + __u8 ss_source_vol; | |
429 | + __u8 mix_drv_cap_range; | |
430 | + struct { | |
431 | + __u16 big_drv_map[8]; | |
432 | + __u32 blks_per_drv; | |
433 | + __u16 fault_tol_mode; | |
434 | + __u16 dist_factor; | |
435 | + } MDC_range[4]; | |
436 | + __u8 reserved1[248]; | |
437 | +} config_t; | |
438 | + | |
439 | +#define BYPASS_VOL_STATE 0x52 | |
440 | +#define SS_CREATE_VOL 0x53 | |
441 | +#define CHANGE_CONFIG 0x54 | |
442 | +#define SENSE_ORIG_CONF 0x55 | |
443 | +#define REORDER_LOG_DRV 0x56 | |
444 | +typedef struct { | |
445 | + __u8 old_units[32]; | |
446 | +} reorder_log_drv_t; | |
447 | + | |
448 | +#define LABEL_LOG_DRV 0x57 | |
449 | +typedef struct { | |
450 | + __u8 log_drv_label[64]; | |
451 | +} label_log_drv_t; | |
452 | + | |
453 | +#define SS_TO_VOL 0x58 | |
454 | + | |
455 | +#define SET_SURF_DELAY 0x60 | |
456 | +typedef struct { | |
457 | + __u16 delay; | |
458 | + __u8 reserved[510]; | |
459 | +} surf_delay_t; | |
460 | + | |
461 | +#define SET_OVERHEAT_DELAY 0x61 | |
462 | +typedef struct { | |
463 | + __u16 delay; | |
464 | +} overhead_delay_t; | |
465 | + | |
466 | +#define SET_MP_DELAY | |
467 | +typedef struct { | |
468 | + __u16 delay; | |
469 | + __u8 reserved[510]; | |
470 | +} mp_delay_t; | |
471 | + | |
472 | +#define SENSE_SURF_STATUS 0x70 | |
473 | + | |
474 | +#define PASSTHRU_A 0x91 | |
475 | +typedef struct { | |
476 | + __u8 target; | |
477 | + __u8 bus; | |
478 | + __u8 lun; | |
479 | + __u32 timeout; | |
480 | + __u32 flags; | |
481 | + __u8 status; | |
482 | + __u8 error; | |
483 | + __u8 cdb_len; | |
484 | + __u8 sense_error; | |
485 | + __u8 sense_key; | |
486 | + __u32 sense_info; | |
487 | + __u8 sense_code; | |
488 | + __u8 sense_qual; | |
489 | + __u32 residual; | |
490 | + __u8 reserved[4]; | |
491 | + __u8 cdb[12]; | |
492 | +} scsi_param_t; | |
493 | + | |
494 | +#define RESUME_BACKGROUND_ACTIVITY 0x99 | |
495 | +#define SENSE_CONTROLLER_PERFORMANCE 0xa8 | |
496 | +#define FLUSH_CACHE 0xc2 | |
497 | +#define COLLECT_BUFFER 0xd2 | |
498 | +#define READ_FLASH_ROM 0xf6 | |
499 | +#define WRITE_FLASH_ROM 0xf7 | |
500 | +#pragma pack() | |
501 | + | |
502 | +#endif /* ARRAYCMD_H */ | |
503 | diff -Nur cpqarrayd-2.2/drivers.orig/block/ida_ioctl.h cpqarrayd-2.2/drivers/block/ida_ioctl.h | |
504 | --- cpqarrayd-2.2/drivers.orig/block/ida_ioctl.h 1970-01-01 01:00:00.000000000 +0100 | |
505 | +++ cpqarrayd-2.2/drivers/block/ida_ioctl.h 2005-11-17 16:51:31.000000000 +0100 | |
506 | @@ -0,0 +1,121 @@ | |
507 | +/* | |
508 | + * Disk Array driver for Compaq SMART2 Controllers | |
509 | + * Copyright 1998 Compaq Computer Corporation | |
510 | + * | |
511 | + * This program is free software; you can redistribute it and/or modify | |
512 | + * it under the terms of the GNU General Public License as published by | |
513 | + * the Free Software Foundation; either version 2 of the License, or | |
514 | + * (at your option) any later version. | |
515 | + * | |
516 | + * This program is distributed in the hope that it will be useful, | |
517 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
518 | + * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
519 | + * NON INFRINGEMENT. See the GNU General Public License for more details. | |
520 | + * | |
521 | + * You should have received a copy of the GNU General Public License | |
522 | + * along with this program; if not, write to the Free Software | |
523 | + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
524 | + * | |
525 | + * Questions/Comments/Bugfixes to arrays@compaq.com | |
526 | + * | |
527 | + */ | |
528 | +#ifndef IDA_IOCTL_H | |
529 | +#define IDA_IOCTL_H | |
530 | + | |
531 | +#include "ida_cmd.h" | |
532 | +#include "cpqarray.h" | |
533 | + | |
534 | +#define IDAGETDRVINFO 0x27272828 | |
535 | +#define IDAPASSTHRU 0x28282929 | |
536 | +#define IDAGETCTLRSIG 0x29293030 | |
537 | +#define IDAREVALIDATEVOLS 0x30303131 | |
538 | +#define IDADRIVERVERSION 0x31313232 | |
539 | +#define IDAGETPCIINFO 0x32323333 | |
540 | +#define IDADEREGDISK 0x33333434 | |
541 | +#define IDAREGNEWDISK 0x34343535 | |
542 | +#define IDAGETLOGINFO 0x35353636 | |
543 | +#define IDABIGPASSTHRU 0x36363535 | |
544 | + | |
545 | +typedef struct _ida_pci_info_struct | |
546 | +{ | |
547 | + unsigned char bus; | |
548 | + unsigned char dev_fn; | |
549 | + __u32 board_id; | |
550 | +} ida_pci_info_struct; | |
551 | + | |
552 | +typedef struct _idaLogvolInfo_struct{ | |
553 | +int LogVolID; | |
554 | +int num_opens; /* number of opens on the logical volume */ | |
555 | +int num_parts; /* number of partitions configured on logvol */ | |
556 | +} idaLogvolInfo_struct; | |
557 | + | |
558 | +/* | |
559 | + * Normally, the ioctl determines the logical unit for this command by | |
560 | + * the major,minor number of the fd passed to ioctl. If you need to send | |
561 | + * a command to a different/nonexistant unit (such as during config), you | |
562 | + * can override the normal behavior by setting the unit valid bit. (Normally, | |
563 | + * it should be zero) The controller the command is sent to is still | |
564 | + * determined by the major number of the open device. | |
565 | + */ | |
566 | + | |
567 | +#define UNITVALID 0x80 | |
568 | +typedef struct { | |
569 | + __u8 cmd; | |
570 | + __u8 rcode; | |
571 | + __u8 unit; | |
572 | + __u32 blk; | |
573 | + __u16 blk_cnt; | |
574 | + | |
575 | +/* currently, sg_cnt is assumed to be 1: only the 0th element of sg is used */ | |
576 | + struct { | |
577 | + void *addr; | |
578 | + size_t size; | |
579 | + } sg[SG_MAX]; | |
580 | + int sg_cnt; | |
581 | + | |
582 | + union ctlr_cmds { | |
583 | + drv_info_t drv; | |
584 | + unsigned char buf[1024]; | |
585 | + | |
586 | + id_ctlr_t id_ctlr; | |
587 | + drv_param_t drv_param; | |
588 | + id_log_drv_t id_log_drv; | |
589 | + id_log_drv_ext_t id_log_drv_ext; | |
590 | + sense_log_drv_stat_t sense_log_drv_stat; | |
591 | + id_phys_drv_t id_phys_drv; | |
592 | + blink_drv_leds_t blink_drv_leds; | |
593 | + sense_blink_leds_t sense_blink_leds; | |
594 | + config_t config; | |
595 | + reorder_log_drv_t reorder_log_drv; | |
596 | + label_log_drv_t label_log_drv; | |
597 | + surf_delay_t surf_delay; | |
598 | + overhead_delay_t overhead_delay; | |
599 | + mp_delay_t mp_delay; | |
600 | + scsi_param_t scsi_param; | |
601 | + } c; | |
602 | +} ida_ioctl_t; | |
603 | + | |
604 | +#define IDA_MAX_KMALLOC_SIZE 128000 | |
605 | + | |
606 | +/* transfer type of the commands */ | |
607 | +#define IDA_XFER_NONE 0x00 | |
608 | +#define IDA_XFER_READ 0x01 | |
609 | +#define IDA_XFER_WRITE 0x02 | |
610 | +#define IDA_XFER_BOTH 0x03 | |
611 | + | |
612 | +typedef struct { | |
613 | + __u8 cmd; | |
614 | + __u8 rcode; | |
615 | + __u8 unit; | |
616 | + __u32 blk; | |
617 | + __u16 blk_cnt; | |
618 | + | |
619 | + __u8 xfer_type; | |
620 | + __u8 *buff; | |
621 | + size_t buff_size; | |
622 | + __u32 buff_malloc_size; | |
623 | + scsi_param_t *scsi_param; /* used only for PASSTHRU_A */ | |
624 | + | |
625 | +} ida_big_ioctl_t; | |
626 | + | |
627 | +#endif /* IDA_IOCTL_H */ |