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0a221a90 | 1 | diff -ru SVGATextMode-1.10.orig/XFREE/riva128_clock.c SVGATextMode-1.10/XFREE/riva128_clock.c |
2 | --- SVGATextMode-1.10.orig/XFREE/riva128_clock.c 2000-07-18 04:47:15.000000000 +0200 | |
3 | +++ SVGATextMode-1.10/XFREE/riva128_clock.c 2004-05-25 20:45:25.594991568 +0200 | |
4 | @@ -80,9 +80,96 @@ | |
5 | #define PCI_DEVICE_ID_NVIDIA_TNT 0x0020 | |
6 | #define PCI_DEVICE_ID_NVIDIA_TNT2 0x0028 | |
7 | #define PCI_DEVICE_ID_NVIDIA_UTNT2 0x0029 | |
8 | +#define PCI_DEVICE_ID_NVIDIA_UNKNOWN_TNT2 0x002A | |
9 | #define PCI_DEVICE_ID_NVIDIA_VTNT2 0x002C | |
10 | #define PCI_DEVICE_ID_NVIDIA_UVTNT2 0x002D | |
11 | #define PCI_DEVICE_ID_NVIDIA_ITNT2 0x00A0 | |
12 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR 0x0100 | |
13 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR 0x0101 | |
14 | +#define PCI_DEVICE_ID_NVIDIA_QUADRO 0x0103 | |
15 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX400 0x0110 | |
16 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX200 0x0111 | |
17 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO 0x0112 | |
18 | +#define PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR 0x0113 | |
19 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS 0x0150 | |
20 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2 0x0151 | |
21 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA 0x0152 | |
22 | +#define PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO 0x0153 | |
23 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460 0x0170 | |
24 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440 0x0171 | |
25 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420 0x0172 | |
26 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX440SE 0x0173 | |
27 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO 0x0174 | |
28 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO 0x0175 | |
29 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO32 0x0176 | |
30 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_460GO 0x0177 | |
31 | +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL 0x0178 | |
32 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_460_GO64 0x0179 | |
33 | +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_200 0x017A | |
34 | +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL 0x017B | |
35 | +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL 0x017C | |
36 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_410_GO16 0x017D | |
37 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX440_AGP8x 0x0181 | |
38 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX440SE_AGP8x 0x0182 | |
39 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX420_AGP8x 0x0183 | |
40 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_448_GO 0x0186 | |
41 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_488_GO 0x0187 | |
42 | +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_580_XGL 0x0188 | |
43 | +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_280_NVS 0x018A | |
44 | +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_380_XGL 0x018B | |
45 | +#define PCI_DEVICE_ID_NVIDIA_IGEFORCE2 0x01a0 | |
46 | +#define PCI_DEVICE_ID_NVIDIA_IGEFORCE4_MX 0x01F0 | |
47 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE3 0x0200 | |
48 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_TI200 0x0201 | |
49 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_TI500 0x0202 | |
50 | +#define PCI_DEVICE_ID_NVIDIA_QUADRO_DCC 0x0203 | |
51 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI4600 0x0250 | |
52 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI4400 0x0251 | |
53 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI4200 0x0253 | |
54 | +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL 0x0258 | |
55 | +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL 0x0259 | |
56 | +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL 0x025B | |
57 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI4800 0x0280 | |
58 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI4200_AGP8x 0x0281 | |
59 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI4800SE 0x0282 | |
60 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_4200GO 0x0286 | |
61 | +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_700GOGL 0x028C | |
62 | +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_980XGL 0x0288 | |
63 | +#define PCI_DEVICE_ID_NVIDIA_QUADRO4_780XGL 0x0289 | |
64 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800U 0x0301 | |
65 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800 0x0302 | |
66 | +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_2000 0x0308 | |
67 | +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1000 0x0309 | |
68 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600U 0x0311 | |
69 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600 0x0312 | |
70 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600SE 0x0314 | |
71 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5600 0x031A | |
72 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5650 0x031B | |
73 | +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO700 0x031C | |
74 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200 0x0320 | |
75 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200U 0x0321 | |
76 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_U 0x0322 | |
77 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200SE 0x0323 | |
78 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200 0x0324 | |
79 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250 0x0325 | |
80 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200_32M_64M 0x0328 | |
81 | +#define PCI_DEVICE_ID_NVIDIA_QUADRO_NVS_280_PCI 0x032A | |
82 | +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_500 0x032B | |
83 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5300 0x032C | |
84 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5100 0x032D | |
85 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900U 0x0330 | |
86 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900 0x0331 | |
87 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900XT 0x0332 | |
88 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5950U 0x0333 | |
89 | +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_3000 0x0338 | |
90 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700U 0x0341 | |
91 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700 0x0342 | |
92 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700LE 0x0343 | |
93 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700VE 0x0344 | |
94 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700 0x0347 | |
95 | +#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_ 0x0348 | |
96 | +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000 0x034C | |
97 | +#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100 0x034E | |
98 | ||
99 | vgaPCIInformation *vgaPCIInfo; | |
100 | ||
101 | @@ -92,14 +179,16 @@ | |
102 | #define PRAMDAC_PLL_COEFF 0x00000508 | |
103 | #define PRAMDAC_PLL_COEFF_SELECT 0x0000050C | |
104 | ||
105 | + | |
106 | +#define PEXTDEV_BASE 0x00101000 | |
107 | + | |
108 | #define NV3_MIN_CLOCK_IN_KHZ 25000 // Not sure about this, but it seems reasonable | |
109 | #define NV3_MAX_CLOCK_IN_KHZ 230000 | |
110 | #define NV4_MAX_CLOCK_IN_KHZ 350000 | |
111 | ||
112 | static int max_clock, is_nv3, pll_coeff; | |
113 | ||
114 | -/* NTSC cards have approx 14.3Mhz. Need to detect, but leave for now*/ | |
115 | -#define PLL_INPUT_FREQ 13500 | |
116 | +static int PLL_INPUT_FREQ; | |
117 | #define M_MIN 7 | |
118 | #define M_MAX 13 | |
119 | ||
120 | @@ -107,79 +196,102 @@ | |
121 | #define P_MAX 4 /* Not sure about this. Could be 4 */ | |
122 | ||
123 | //=== Function section === | |
124 | -// From xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/riva_hw.c in XFree86 3.3.6 | |
125 | +// From xc/programs/Xserver/hw/xfree86/drivers/nv/nv_hw.c in X11R6.7.0 | |
126 | /* | |
127 | * Calculate the Video Clock parameters for the PLL. | |
128 | */ | |
129 | -static int CalcVClock | |
130 | -( | |
131 | +static void CalcVClock ( | |
132 | int clockIn, | |
133 | - int double_scan, | |
134 | int *clockOut, | |
135 | - int *mOut, | |
136 | - int *nOut, | |
137 | - int *pOut/*, | |
138 | - RIVA_HW_INST *chip*/ | |
139 | + unsigned int *pllOut | |
140 | ) | |
141 | { | |
142 | - unsigned lowM, highM, highP; | |
143 | + unsigned lowM, highM; | |
144 | unsigned DeltaNew, DeltaOld; | |
145 | unsigned VClk, Freq; | |
146 | unsigned M, N, P; | |
147 | - | |
148 | + | |
149 | DeltaOld = 0xFFFFFFFF; | |
150 | ||
151 | - VClk = (unsigned)clockIn; | |
152 | - if (double_scan) | |
153 | - VClk *= 2; | |
154 | - | |
155 | - if (/*chip->CrystalFreqKHz*/PLL_INPUT_FREQ == 14318) | |
156 | - { | |
157 | - lowM = 8; | |
158 | - highM = 14 - (/*chip->Architecture == NV_ARCH_03*/is_nv3); | |
159 | - } | |
160 | - else | |
161 | - { | |
162 | + VClk = (unsigned)clockIn; | |
163 | + | |
164 | + if (/*pNv->CrystalFreqKHz*/ PLL_INPUT_FREQ == 13500) { | |
165 | lowM = 7; | |
166 | highM = 13 - (/*chip->Architecture == NV_ARCH_03*/is_nv3); | |
167 | + } else { | |
168 | + lowM = 8; | |
169 | + highM = 14 - (/*chip->Architecture == NV_ARCH_03*/is_nv3); | |
170 | } | |
171 | ||
172 | - highP = 4 - (/*chip->Architecture == NV_ARCH_03*/is_nv3); | |
173 | - for (P = 0; P <= highP; P ++) | |
174 | - { | |
175 | + for (P = 0; P <= 4 - is_nv3; P++) { | |
176 | Freq = VClk << P; | |
177 | - if ((Freq >= 128000) && (Freq <= /*chip->MaxVClockFreqKHz*/max_clock)) | |
178 | - { | |
179 | - for (M = lowM; M <= highM; M++) | |
180 | - { | |
181 | - N = (VClk * M / /*chip->CrystalFreqKHz*/PLL_INPUT_FREQ) << P; | |
182 | - Freq = (/*chip->CrystalFreqKHz*/PLL_INPUT_FREQ * N / M) >> P; | |
183 | - if (Freq > VClk) | |
184 | - DeltaNew = Freq - VClk; | |
185 | - else | |
186 | - DeltaNew = VClk - Freq; | |
187 | - if (DeltaNew < DeltaOld) | |
188 | - { | |
189 | - *mOut = M; | |
190 | - *nOut = N; | |
191 | - *pOut = P; | |
192 | - *clockOut = Freq; | |
193 | - DeltaOld = DeltaNew; | |
194 | + if ((Freq >= 128000) && (Freq <= max_clock)) { | |
195 | + for (M = lowM; M <= highM; M++) { | |
196 | + N = ((VClk << P) * M) / /* pNv->CrystalFreqKHz */ PLL_INPUT_FREQ; | |
197 | + if(N <= 255) { | |
198 | + Freq = ((/*pNv->CrystalFreqKHz*/ PLL_INPUT_FREQ * N) / M) >> P; | |
199 | + if (Freq > VClk) | |
200 | + DeltaNew = Freq - VClk; | |
201 | + else | |
202 | + DeltaNew = VClk - Freq; | |
203 | + if (DeltaNew < DeltaOld) { | |
204 | + *pllOut = (P << 16) | (N << 8) | M; | |
205 | + *clockOut = Freq; | |
206 | + DeltaOld = DeltaNew; | |
207 | + } | |
208 | } | |
209 | } | |
210 | } | |
211 | } | |
212 | - return (DeltaOld != 0xFFFFFFFF); | |
213 | +} | |
214 | + | |
215 | +static void CalcVClock2Stage ( | |
216 | + int clockIn, | |
217 | + int *clockOut, | |
218 | + unsigned int *pllOut, | |
219 | + unsigned int *pllBOut | |
220 | +) | |
221 | +{ | |
222 | + unsigned DeltaNew, DeltaOld; | |
223 | + unsigned VClk, Freq; | |
224 | + unsigned M, N, P; | |
225 | + | |
226 | + DeltaOld = 0xFFFFFFFF; | |
227 | + | |
228 | + *pllBOut = 0x80000401; /* fixed at x4 for now */ | |
229 | + | |
230 | + VClk = (unsigned)clockIn; | |
231 | ||
232 | + for (P = 0; P <= 6; P++) { | |
233 | + Freq = VClk << P; | |
234 | + if ((Freq >= 400000) && (Freq <= 1000000)) { | |
235 | + for (M = 1; M <= 13; M++) { | |
236 | + N = ((VClk << P) * M) / (PLL_INPUT_FREQ << 2); | |
237 | + if((N >= 5) && (N <= 255)) { | |
238 | + Freq = (((PLL_INPUT_FREQ << 2) * N) / M) >> P; | |
239 | + if (Freq > VClk) | |
240 | + DeltaNew = Freq - VClk; | |
241 | + else | |
242 | + DeltaNew = VClk - Freq; | |
243 | + if (DeltaNew < DeltaOld) { | |
244 | + *pllOut = (P << 16) | (N << 8) | M; | |
245 | + *clockOut = Freq; | |
246 | + DeltaOld = DeltaNew; | |
247 | + } | |
248 | + } | |
249 | + } | |
250 | + } | |
251 | + } | |
252 | } | |
253 | ||
254 | // Set the clock to the given speed (in KHz) | |
255 | Bool RIVA128ClockSelect( int clockspeed ) | |
256 | { | |
257 | - int *ptr; | |
258 | + int *ptr, *ptr2; | |
259 | + int implementation = 0; | |
260 | ||
261 | - int out; | |
262 | - int m, n, p, value; | |
263 | + int clockout; | |
264 | + int pll, pllB; | |
265 | int i = 0; | |
266 | pciConfigPtr pcr = NULL; | |
267 | int fd; | |
268 | @@ -203,13 +315,101 @@ | |
269 | if (pcr->_device == PCI_DEVICE_ID_NVIDIA_TNT || | |
270 | pcr->_device == PCI_DEVICE_ID_NVIDIA_TNT2 || | |
271 | pcr->_device == PCI_DEVICE_ID_NVIDIA_UTNT2 || | |
272 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_UNKNOWN_TNT2 || | |
273 | pcr->_device == PCI_DEVICE_ID_NVIDIA_VTNT2 || | |
274 | pcr->_device == PCI_DEVICE_ID_NVIDIA_UVTNT2 || | |
275 | - pcr->_device == PCI_DEVICE_ID_NVIDIA_ITNT2) | |
276 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_ITNT2 || | |
277 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR || | |
278 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR || | |
279 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO || | |
280 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX400 || | |
281 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX200 || | |
282 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO || | |
283 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR || | |
284 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS || | |
285 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2 || | |
286 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA || | |
287 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO || | |
288 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460 || | |
289 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440 || | |
290 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420 || | |
291 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX440SE || | |
292 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO || | |
293 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO || | |
294 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO32 || | |
295 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_460GO || | |
296 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL || | |
297 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_460_GO64 || | |
298 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO4_200 || | |
299 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL || | |
300 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL || | |
301 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_410_GO16 || | |
302 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX440_AGP8x || | |
303 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX440SE_AGP8x || | |
304 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX420_AGP8x || | |
305 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_448_GO || | |
306 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_488_GO || | |
307 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO4_580_XGL || | |
308 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO4_280_NVS || | |
309 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO4_380_XGL || | |
310 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_IGEFORCE2 || | |
311 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_IGEFORCE4_MX || | |
312 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE3 || | |
313 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE3_TI200 || | |
314 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE3_TI500 || | |
315 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO_DCC || | |
316 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI4600 || | |
317 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI4400 || | |
318 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI4200 || | |
319 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL || | |
320 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL || | |
321 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL || | |
322 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI4800 || | |
323 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI4200_AGP8x || | |
324 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI4800SE || | |
325 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE4_4200GO || | |
326 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO4_700GOGL || | |
327 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO4_980XGL || | |
328 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO4_780XGL || | |
329 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800U || | |
330 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800 || | |
331 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO_FX_2000 || | |
332 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1000 || | |
333 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600U || | |
334 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600 || | |
335 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600SE || | |
336 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5600 || | |
337 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5650 || | |
338 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO700 || | |
339 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200 || | |
340 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200U || | |
341 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200 || | |
342 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200SE || | |
343 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200 || | |
344 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250 || | |
345 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200_32M_64M || | |
346 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO_NVS_280_PCI || | |
347 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO_FX_500 || | |
348 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5300 || | |
349 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5100 || | |
350 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900U || | |
351 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900 || | |
352 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900XT || | |
353 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5950U || | |
354 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO_FX_3000 || | |
355 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700U || | |
356 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700 || | |
357 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700LE || | |
358 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700VE || | |
359 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700 || | |
360 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700 || | |
361 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000 || | |
362 | + pcr->_device == PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100) | |
363 | { | |
364 | is_nv3 = 0; | |
365 | pll_coeff = 0x00010700; | |
366 | max_clock = NV4_MAX_CLOCK_IN_KHZ; | |
367 | + implementation = pcr->_device & 0x0ff0; | |
368 | break; | |
369 | } | |
370 | ||
371 | @@ -249,6 +449,33 @@ | |
372 | return FALSE; | |
373 | } | |
374 | ||
375 | + ptr2 = (int*)mmap(0, 0x1000,PROT_READ|PROT_WRITE,MAP_SHARED, fd, (off_t)(pcr->_base0) + PEXTDEV_BASE); | |
376 | + | |
377 | + if( ptr2 == (int*)-1 ) | |
378 | + { | |
379 | + PERROR(( "Error mmap'ing /dev/mem" )); | |
380 | + return FALSE; | |
381 | + } | |
382 | + | |
383 | + if(is_nv3) | |
384 | + { | |
385 | + PLL_INPUT_FREQ = (ptr2[0x00000000/4]&0x20) ? 13500 : 14318; | |
386 | + } | |
387 | + else | |
388 | + { | |
389 | + PLL_INPUT_FREQ = (ptr2[0x00000000/4]&0x40) ? 14318 : 13500; | |
390 | + } | |
391 | + | |
392 | + if((implementation == 0x0170) || | |
393 | + (implementation == 0x0180) || | |
394 | + (implementation == 0x01F0) || | |
395 | + (implementation >= 0x0250)) | |
396 | + { | |
397 | + if(ptr2[0x00000000/4] & (1 << 22)) PLL_INPUT_FREQ = 27000; | |
398 | + } | |
399 | + | |
400 | + munmap(ptr2, 0x1000); | |
401 | + | |
402 | close( fd ); | |
403 | #else | |
404 | ptr=(int*) malloc(0x4000); | |
405 | @@ -261,13 +488,15 @@ | |
406 | ||
407 | // Calculate the clock | |
408 | //NV3ClockSelect( (float)clockspeed, &out, &m, &n, &p ); | |
409 | - CalcVClock ((float) clockspeed, 0, &out, &m, &n, &p); | |
410 | - | |
411 | - value = (m) + (n<<8) + (p<<16); | |
412 | + if ((implementation == 0x0310) || (implementation == 0x0340)) { | |
413 | + CalcVClock2Stage ((float) clockspeed, &clockout, &pll, &pllB); | |
414 | + } else { | |
415 | + CalcVClock ((float) clockspeed, &clockout, &pll); | |
416 | + } | |
417 | ||
418 | // But of debug info | |
419 | - PDEBUG(( "Wanted %dkHz, got %dkHz (m=%d, n=%d, p=%d, value=0x%08X)\n", | |
420 | - clockspeed, (int)out, m, n, p, value )); | |
421 | + PDEBUG(( "Wanted %dkHz, got %dkHz (pll=0x%08X)\n", | |
422 | + clockspeed, (int)clockout, pll)); | |
423 | ||
424 | // Default value is 0x00000100 (NV3) | |
425 | // X uses 0x10010100 (NV3) or 0x10000700 (NV4) | |
426 | @@ -275,8 +504,10 @@ | |
427 | ptr[PRAMDAC_PLL_COEFF_SELECT/4] = pll_coeff; // could use |= | |
428 | ||
429 | // Divide by 4 because we're dealing with integers | |
430 | - ptr[PRAMDAC_PLL_COEFF/4] = value; | |
431 | - | |
432 | + ptr[PRAMDAC_PLL_COEFF/4] = pll; | |
433 | + if ((implementation == 0x0310) || (implementation == 0x0340)) { | |
434 | + ptr[0x00000578/4] = pllB; | |
435 | + } | |
436 | #ifndef DOS | |
437 | // Unmap memory | |
438 | munmap( ptr, 0x1000 ); | |
439 |