X-Git-Url: http://git.pld-linux.org/?a=blobdiff_plain;f=kernel-small_fixes.patch;h=2323e82bef2aec4ea226bd5112c7899247210b6d;hb=6c88592afde13241e264054f937ee11f183f1fd4;hp=d30a20a8f0dd8539d7b0631c3e04ff36fed67b6c;hpb=2dfbb2745b90341e805bedf0d3b3bb0a878216c6;p=packages%2Fkernel.git diff --git a/kernel-small_fixes.patch b/kernel-small_fixes.patch index d30a20a8..2323e82b 100644 --- a/kernel-small_fixes.patch +++ b/kernel-small_fixes.patch @@ -27,666 +27,73 @@ fi done -diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c -index 7a0c800..ec5ebbb 100644 ---- a/drivers/net/ethernet/realtek/r8169.c -+++ b/drivers/net/ethernet/realtek/r8169.c -@@ -4103,6 +4103,14 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) - /* Get MAC address */ - for (i = 0; i < ETH_ALEN; i++) - dev->dev_addr[i] = RTL_R8(MAC0 + i); -+ -+ if (!is_valid_ether_addr(dev->dev_addr)) { -+ /* Report it and use a random ethernet address instead */ -+ netdev_err(dev, "Invalid MAC address: %pM\n", dev->dev_addr); -+ random_ether_addr(dev->dev_addr); -+ netdev_info(dev, "Using random MAC address: %pM\n", -+ dev->dev_addr); -+ } - memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); - - SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops); --- -1.7.7.3 - - ---- linux-3.4/fs/unionfs/commonfops.c.org 2012-05-29 20:40:20.756489877 +0200 -+++ linux-3.4/fs/unionfs/commonfops.c 2012-05-29 21:07:12.021252743 +0200 -@@ -766,7 +766,7 @@ - unsigned int cmd, unsigned long arg) - { - int err = 0; -- fd_set branchlist; -+ unsigned long branchlist = 0; - int bstart = 0, bend = 0, bindex = 0; - int orig_bstart, orig_bend; - struct dentry *dentry, *lower_dentry; -@@ -781,14 +781,12 @@ - bstart = dbstart(dentry); - bend = dbend(dentry); - -- FD_ZERO(&branchlist); -- - for (bindex = bstart; bindex <= bend; bindex++) { - lower_dentry = unionfs_lower_dentry_idx(dentry, bindex); - if (!lower_dentry) - continue; - if (likely(lower_dentry->d_inode)) -- FD_SET(bindex, &branchlist); -+ __set_bit(bindex, &branchlist); - /* purge any lower objects after partial_lookup */ - if (bindex < orig_bstart || bindex > orig_bend) { - dput(lower_dentry); - -From patchwork Sun Aug 12 11:57:49 2012 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -Subject: sp5100_tco: Add SB8x0 chipset support -Date: Sun, 12 Aug 2012 11:57:49 -0000 -From: Takahisa Tanaka -X-Patchwork-Id: 1309571 -Message-Id: <1344772669-2872-1-git-send-email-mc74hc00@gmail.com> -To: linux-watchdog@vger.kernel.org -Cc: wim@iguana.be, stable@kernel.org, - paulepanter@users.sourceforge.net, post+kernel@ralfj.de, - linux-kernel@vger.kernel.org, Takahisa Tanaka - -The current sp5100_tco driver only supports SP5100/SB7x0 chipset, doesn't -support SB8x0 chipset, because current sp5100_tco driver doesn't know that the -offset address for watchdog timer was changed from SB8x0 chipset. - -The offset address of SP5100 and SB7x0 chipsets are as follows, quote from the -AMD SB700/710/750 Register Reference Guide(Page 164) and the AMD SP5100 -Register Reference Guide(Page 166). - - WatchDogTimerControl 69h - WatchDogTimerBase0 6Ch - WatchDogTimerBase1 6Dh - WatchDogTimerBase2 6Eh - WatchDogTimerBase3 6Fh - -In contrast, the offset address of SB8x0 chipset is as follows, quote from -AMD SB800-Series Southbridges Register Reference Guide(Page 147). - - WatchDogTimerEn 48h - WatchDogTimerConfig 4Ch - -So, In the case of SB8x0 chipset, sp5100_tco reads meaningless MMIO -address(for example, 0xbafe00) from wrong offset address, and the following -message is logged. - - SP5100 TCO timer: mmio address 0xbafe00 already in use - -With this patch, sp5100_tco driver supports SB8x0 chipset, and can avoid -iomem resource conflict. The processing of this patch is as follows. - - Step 1) Attempt to get the watchdog base address from indirect I/O(0xCD6 - and 0xCD7). - - Go to the step 7 if obtained address hasn't conflicted with other - resource. But, currently, the address(0xfec000f0) conflicts with the - IOAPIC MMIO address, and the following message is logged. - - SP5100 TCO timer: mmio address 0xfec000f0 already in use - 0xfec000f0 is recommended by AMD BIOS Developer's Guide. So, go to the - next step. +Hi all, + There is a risk of data loss with md/raid6 arrays running on Linux since + 2.6.32. + If: + - the array is doubly degraded + - one or both failed devices are being recovered, and + - the array is written to + + then it is possible for data on the array to be lost. The patch below fixes + the problem. If you apply the patch to an older kernel which has separate + handle_stripe5() and handle_stripe6() functions, be sure that patch changes + handle_stripe6(). + + There is no risk to an optimal array or a singly-degraded array. There is + also no risk on a doubly-degraded array which is not recovering a device or + is not receiving write requests. + + If you have data on a RAID6 array, please consider how to avoid corruption, + possibly by applying the patch, possibly by removing any hot spares so + recovery does not automatically start. + + This patch will be sent upstream shortly and will subsequently appear in + future "-stable" kernels. + +NeilBrown + +From f94e37dce722ec7b6666fd04be357f422daa02b5 Mon Sep 17 00:00:00 2001 +From: NeilBrown +Date: Wed, 13 Aug 2014 09:57:07 +1000 +Subject: [PATCH] md/raid6: avoid data corruption during recovery of + double-degraded RAID6 + +During recovery of a double-degraded RAID6 it is possible for +some blocks not to be recovered properly, leading to corruption. + +If a write happens to one block in a stripe that would be written to a +missing device, and at the same time that stripe is recovering data +to the other missing device, then that recovered data may not be written. + +This patch skips, in the double-degraded case, an optimisation that is +only safe for single-degraded arrays. + +Bug was introduced in 2.6.32 and fix is suitable for any kernel since +then. In an older kernel with separate handle_stripe5() and +handle_stripe6() functions that patch must change handle_stripe6(). + +Cc: stable@vger.kernel.org (2.6.32+) +Fixes: 6c0069c0ae9659e3a91b68eaed06a5c6c37f45c8 +Cc: Yuri Tikhonov +Cc: Dan Williams +Reported-by: "Manibalan P" +Resolves: https://bugzilla.redhat.com/show_bug.cgi?id=1090423 +Signed-off-by: NeilBrown + +diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c +index 6b2d615d1094..183588b11fc1 100644 +--- a/drivers/md/raid5.c ++++ b/drivers/md/raid5.c +@@ -3817,6 +3817,8 @@ static void handle_stripe(struct stripe_head *sh) + set_bit(R5_Wantwrite, &dev->flags); + if (prexor) + continue; ++ if (s.failed > 1) ++ continue; + if (!test_bit(R5_Insync, &dev->flags) || + ((i == sh->pd_idx || i == sh->qd_idx) && + s.failed == 0)) - Step 2) Attempt to get the SBResource_MMIO base address from AcpiMmioEN(for - SB8x0, PM_Reg:24h) or SBResource_MMIO(SP5100/SB7x0, PCI_Reg:9Ch) - register. - - Go to the step 7 if these register has enabled by BIOS, and obtained - address hasn't conflicted with other resource. - - If above condition isn't true, go to the next step. - Step 3) Attempt to get the free MMIO address from allocate_resource(). - - Go to the step 7 if these register has enabled by BIOS, and obtained - address hasn't conflicted with other resource. - - Driver initialization has failed if obtained address has conflicted - with other resource, and no 'force_addr' parameter is specified. - - Step 4) Use the specified address If 'force_addr' parameter is specified. - - allocate_resource() function may fail, when the PCI bridge device occupies - iomem resource from 0xf0000000 to 0xffffffff. To handle such a case, - I added 'force_addr' parameter to sp5100_tco driver. With 'force_addr' - parameter, sp5100_tco driver directly can assign MMIO address for watchdog - timer from free iomem region. Note that It's dangerous to specify wrong - address in the 'force_addr' parameter. - - Example of force_addr parameter use - # cat /proc/iomem - ...snip... - fec00000-fec003ff : IOAPIC 0 - <--- free MMIO region - fec10000-fec1001f : pnp 00:0b - fec20000-fec203ff : IOAPIC 1 - ...snip... - # cat /etc/modprobe.d/sp5100_tco.conf - options sp5100_tco force_addr=0xfec00800 - # modprobe sp5100_tco - # cat /proc/iomem - ...snip... - fec00000-fec003ff : IOAPIC 0 - fec00800-fec00807 : SP5100 TCO <--- watchdog timer MMIO address - fec10000-fec1001f : pnp 00:0b - fec20000-fec203ff : IOAPIC 1 - ...snip... - # - - - Driver initialization has failed if specified address has conflicted - with other resource. - - Step 5) Disable the watchdog timer - - To rewrite the watchdog timer register of the chipset, absolutely - guarantee that the watchdog timer is disabled. - - Step 6) Re-program the watchdog timer MMIO address to chipset. - - Re-program the obtained MMIO address in Step 3 or Step 4 to chipset via - indirect I/O(0xCD6 and 0xCD7). - - Step 7) Enable and setup the watchdog timer - -This patch has worked fine on my test environment(ASUS M4A89GTD-PRO/USB3 and -DL165G7). therefore I believe that it's no problem to re-program the MMIO -address for watchdog timer to chipset during disabled watchdog. However, -I'm not sure about it, because I don't know much about chipset programming. - -So, any comments will be welcome. - -Tested-by: Paul Menzel -CC: stable@kernel.org -Signed-off-by: Takahisa Tanaka - ---- -drivers/watchdog/sp5100_tco.c | 291 ++++++++++++++++++++++++++++++++++++------ - drivers/watchdog/sp5100_tco.h | 46 +++++-- - 2 files changed, 286 insertions(+), 51 deletions(-) - -diff --git a/drivers/watchdog/sp5100_tco.c b/drivers/watchdog/sp5100_tco.c -index ae5e82c..36e917f 100644 ---- a/drivers/watchdog/sp5100_tco.c -+++ b/drivers/watchdog/sp5100_tco.c -@@ -13,7 +13,9 @@ - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * -- * See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide" -+ * See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide", -+ * AMD Publication 45482 "AMD SB800-Series Sourthbridges Register -+ * Reference Guide" - */ - - /* -@@ -38,18 +40,23 @@ - #include "sp5100_tco.h" - - /* Module and version information */ --#define TCO_VERSION "0.01" -+#define TCO_VERSION "0.03" - #define TCO_MODULE_NAME "SP5100 TCO timer" - #define TCO_DRIVER_NAME TCO_MODULE_NAME ", v" TCO_VERSION - - /* internal variables */ - static u32 tcobase_phys; -+static u32 resbase_phys; - static void __iomem *tcobase; - static unsigned int pm_iobase; - static DEFINE_SPINLOCK(tco_lock); /* Guards the hardware */ - static unsigned long timer_alive; - static char tco_expect_close; - static struct pci_dev *sp5100_tco_pci; -+static struct resource wdt_res = { -+ .name = "Watchdog Timer", -+ .flags = IORESOURCE_MEM, -+}; - - /* the watchdog platform device */ - static struct platform_device *sp5100_tco_platform_device; -@@ -67,6 +74,12 @@ module_param(nowayout, bool, 0); - MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started" - " (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); - -+static unsigned int force_addr; -+module_param(force_addr, uint, 0); -+MODULE_PARM_DESC(force_addr, "Force the use of specified MMIO address, " -+ "default is disabled. DON'T USE THIS PARAMETER ONLY " -+ "IF YOU REALLY KNOW WHAT YOU ARE DOING"); -+ - /* - * Some TCO specific functions - */ -@@ -122,6 +135,79 @@ static int tco_timer_set_heartbeat(int t) - return 0; - } - -+static void tco_timer_enable(void) -+{ -+ int val; -+ -+ if (sp5100_tco_pci->revision >= 0x40) { -+ /* For SB800 or later */ -+ /* Set the Watchdog timer resolution to 1 sec */ -+ outb(SB800_PM_WATCHDOG_CONFIG, SB800_IO_PM_INDEX_REG); -+ val = inb(SB800_IO_PM_DATA_REG); -+ val |= SB800_PM_WATCHDOG_SECOND_RES; -+ outb(val, SB800_IO_PM_DATA_REG); -+ -+ /* Enable watchdog decode bit and watchdog timer */ -+ outb(SB800_PM_WATCHDOG_CONTROL, SB800_IO_PM_INDEX_REG); -+ val = inb(SB800_IO_PM_DATA_REG); -+ val |= SB800_PCI_WATCHDOG_DECODE_EN; -+ val &= ~SB800_PM_WATCHDOG_DISABLE; -+ outb(val, SB800_IO_PM_DATA_REG); -+ } else { -+ /* For SP5100 or SB7x0 */ -+ /* Enable watchdog decode bit */ -+ pci_read_config_dword(sp5100_tco_pci, -+ SP5100_PCI_WATCHDOG_MISC_REG, -+ &val); -+ -+ val |= SP5100_PCI_WATCHDOG_DECODE_EN; -+ -+ pci_write_config_dword(sp5100_tco_pci, -+ SP5100_PCI_WATCHDOG_MISC_REG, -+ val); -+ -+ /* Enable Watchdog timer and set the resolution to 1 sec */ -+ outb(SP5100_PM_WATCHDOG_CONTROL, SP5100_IO_PM_INDEX_REG); -+ val = inb(SP5100_IO_PM_DATA_REG); -+ val |= SP5100_PM_WATCHDOG_SECOND_RES; -+ val &= ~SP5100_PM_WATCHDOG_DISABLE; -+ outb(val, SP5100_IO_PM_DATA_REG); -+ } -+} -+ -+static void tco_timer_disable(void) -+{ -+ int val; -+ -+ if (sp5100_tco_pci->revision >= 0x40) { -+ /* For SB800 or later */ -+ /* Enable watchdog decode bit and Disable watchdog timer */ -+ outb(SB800_PM_WATCHDOG_CONTROL, SB800_IO_PM_INDEX_REG); -+ val = inb(SB800_IO_PM_DATA_REG); -+ val |= SB800_PCI_WATCHDOG_DECODE_EN; -+ val |= SB800_PM_WATCHDOG_DISABLE; -+ outb(val, SB800_IO_PM_DATA_REG); -+ } else { -+ /* For SP5100 or SB7x0 */ -+ /* Enable watchdog decode bit */ -+ pci_read_config_dword(sp5100_tco_pci, -+ SP5100_PCI_WATCHDOG_MISC_REG, -+ &val); -+ -+ val |= SP5100_PCI_WATCHDOG_DECODE_EN; -+ -+ pci_write_config_dword(sp5100_tco_pci, -+ SP5100_PCI_WATCHDOG_MISC_REG, -+ val); -+ -+ /* Disable Watchdog timer */ -+ outb(SP5100_PM_WATCHDOG_CONTROL, SP5100_IO_PM_INDEX_REG); -+ val = inb(SP5100_IO_PM_DATA_REG); -+ val |= SP5100_PM_WATCHDOG_DISABLE; -+ outb(val, SP5100_IO_PM_DATA_REG); -+ } -+} -+ - /* - * /dev/watchdog handling - */ -@@ -270,11 +356,12 @@ MODULE_DEVICE_TABLE(pci, sp5100_tco_pci_tbl); - /* - * Init & exit routines - */ -- - static unsigned char __devinit sp5100_tco_setupdevice(void) - { - struct pci_dev *dev = NULL; -+ const char *dev_name = NULL; - u32 val; -+ u32 index_reg, data_reg, base_addr; - - /* Match the PCI device */ - for_each_pci_dev(dev) { -@@ -287,29 +374,158 @@ static unsigned char __devinit sp5100_tco_setupdevice(void) - if (!sp5100_tco_pci) - return 0; - -+ pr_info("PCI Revision ID: 0x%x\n", sp5100_tco_pci->revision); -+ -+ /* -+ * Determine type of southbridge chipset. -+ */ -+ if (sp5100_tco_pci->revision >= 0x40) { -+ dev_name = SB800_DEVNAME; -+ index_reg = SB800_IO_PM_INDEX_REG; -+ data_reg = SB800_IO_PM_DATA_REG; -+ base_addr = SB800_PM_WATCHDOG_BASE; -+ } else { -+ dev_name = SP5100_DEVNAME; -+ index_reg = SP5100_IO_PM_INDEX_REG; -+ data_reg = SP5100_IO_PM_DATA_REG; -+ base_addr = SP5100_PM_WATCHDOG_BASE; -+ } -+ - /* Request the IO ports used by this driver */ - pm_iobase = SP5100_IO_PM_INDEX_REG; -- if (!request_region(pm_iobase, SP5100_PM_IOPORTS_SIZE, "SP5100 TCO")) { -- pr_err("I/O address 0x%04x already in use\n", pm_iobase); -+ if (!request_region(pm_iobase, SP5100_PM_IOPORTS_SIZE, dev_name)) { -+ pr_err("I/O address 0x%08x already in use\n", pm_iobase); - goto exit; - } - -- /* Find the watchdog base address. */ -- outb(SP5100_PM_WATCHDOG_BASE3, SP5100_IO_PM_INDEX_REG); -- val = inb(SP5100_IO_PM_DATA_REG); -- outb(SP5100_PM_WATCHDOG_BASE2, SP5100_IO_PM_INDEX_REG); -- val = val << 8 | inb(SP5100_IO_PM_DATA_REG); -- outb(SP5100_PM_WATCHDOG_BASE1, SP5100_IO_PM_INDEX_REG); -- val = val << 8 | inb(SP5100_IO_PM_DATA_REG); -- outb(SP5100_PM_WATCHDOG_BASE0, SP5100_IO_PM_INDEX_REG); -- /* Low three bits of BASE0 are reserved. */ -- val = val << 8 | (inb(SP5100_IO_PM_DATA_REG) & 0xf8); -+ /* -+ * First, Find the watchdog timer MMIO address from indirect I/O. -+ */ -+ outb(base_addr+3, index_reg); -+ val = inb(data_reg); -+ outb(base_addr+2, index_reg); -+ val = val << 8 | inb(data_reg); -+ outb(base_addr+1, index_reg); -+ val = val << 8 | inb(data_reg); -+ outb(base_addr+0, index_reg); -+ /* Low three bits of BASE are reserved */ -+ val = val << 8 | (inb(data_reg) & 0xf8); -+ -+ pr_debug("Got 0x%08x from indirect I/O\n", val); -+ -+ /* Check MMIO address conflict */ -+ if (request_mem_region_exclusive(val, SP5100_WDT_MEM_MAP_SIZE, -+ dev_name)) -+ goto setup_wdt; -+ else -+ pr_debug("MMIO address 0x%08x already in use\n", val); -+ -+ /* -+ * Second, Find the watchdog timer MMIO address -+ * from SBResource_MMIO register. -+ */ -+ if (sp5100_tco_pci->revision >= 0x40) { -+ /* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */ -+ outb(SB800_PM_ACPI_MMIO_EN+3, SB800_IO_PM_INDEX_REG); -+ val = inb(SB800_IO_PM_DATA_REG); -+ outb(SB800_PM_ACPI_MMIO_EN+2, SB800_IO_PM_INDEX_REG); -+ val = val << 8 | inb(SB800_IO_PM_DATA_REG); -+ outb(SB800_PM_ACPI_MMIO_EN+1, SB800_IO_PM_INDEX_REG); -+ val = val << 8 | inb(SB800_IO_PM_DATA_REG); -+ outb(SB800_PM_ACPI_MMIO_EN+0, SB800_IO_PM_INDEX_REG); -+ val = val << 8 | inb(SB800_IO_PM_DATA_REG); -+ } else { -+ /* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */ -+ pci_read_config_dword(sp5100_tco_pci, -+ SP5100_SB_RESOURCE_MMIO_BASE, &val); -+ } -+ -+ /* The SBResource_MMIO is enabled and mapped memory space? */ -+ if ((val & (SB800_ACPI_MMIO_DECODE_EN | SB800_ACPI_MMIO_SEL)) == -+ SB800_ACPI_MMIO_DECODE_EN) { -+ /* Clear unnecessary the low twelve bits */ -+ val &= ~0xFFF; -+ /* Add the Watchdog Timer offset to base address. */ -+ val += SB800_PM_WDT_MMIO_OFFSET; -+ /* Check mmio base address conflict */ -+ if (request_mem_region_exclusive(val, SP5100_WDT_MEM_MAP_SIZE, -+ dev_name)) { -+ pr_debug("Got 0x%08x from SBResource_MMIO register\n", -+ val); -+ goto setup_wdt; -+ } else -+ pr_debug("MMIO address 0x%08x already in use\n", val); -+ } else -+ pr_debug("SBResource_MMIO is disabled(0x%08x)\n", val); -+ -+ /* -+ * Lastly re-programming the watchdog MMIO address, -+ * This method is a last resort... -+ * -+ * Before re-programming, to ensure that the watchdog timer -+ * is disabled, disable the watchdog timer. -+ */ -+ tco_timer_disable(); -+ -+ if (force_addr) { -+ /* Force the use of base address */ -+ val = force_addr; -+ /* The alignment of the MMIO address to a 8byte boundary */ -+ val &= ~0x7; -+ -+ pr_info("Force the use of 0x%08x as MMIO address\n", val); -+ } else { -+ /* -+ * Get empty slot into the resource tree for watchdog timer. -+ */ -+ if (allocate_resource(&iomem_resource, -+ &wdt_res, -+ SP5100_WDT_MEM_MAP_SIZE, -+ 0xf0000000, -+ 0xfffffff8, -+ 0x8, -+ NULL, -+ NULL)) { -+ pr_err("MMIO allocation failed\n"); -+ goto unreg_region; -+ } -+ -+ val = resbase_phys = wdt_res.start; -+ pr_debug("Got 0x%08x from resource tree\n", val); -+ } -+ -+ /* Restore to the low three bits, if chipset is SB8x0(or later) */ -+ if (sp5100_tco_pci->revision >= 0x40) { -+ u8 reserved_bit; -+ reserved_bit = inb(base_addr) & 0x7; -+ val |= (u32)reserved_bit; -+ } -+ -+ /* Re-programming the watchdog timer base address */ -+ outb(base_addr+0, index_reg); -+ /* Low three bits of BASE are reserved */ -+ outb((val >> 0) & 0xf8, data_reg); -+ outb(base_addr+1, index_reg); -+ outb((val >> 8) & 0xff, data_reg); -+ outb(base_addr+2, index_reg); -+ outb((val >> 16) & 0xff, data_reg); -+ outb(base_addr+3, index_reg); -+ outb((val >> 24) & 0xff, data_reg); -+ -+ /* -+ * Clear unnecessary the low three bits, -+ * if chipset is SB8x0(or later) -+ */ -+ if (sp5100_tco_pci->revision >= 0x40) -+ val &= ~0x7; - - if (!request_mem_region_exclusive(val, SP5100_WDT_MEM_MAP_SIZE, -- "SP5100 TCO")) { -- pr_err("mmio address 0x%04x already in use\n", val); -- goto unreg_region; -+ dev_name)) { -+ pr_err("MMIO address 0x%08x already in use\n", val); -+ goto unreg_resource; - } -+ -+setup_wdt: - tcobase_phys = val; - - tcobase = ioremap(val, SP5100_WDT_MEM_MAP_SIZE); -@@ -318,25 +534,12 @@ static unsigned char __devinit sp5100_tco_setupdevice(void) - goto unreg_mem_region; - } - -- /* Enable watchdog decode bit */ -- pci_read_config_dword(sp5100_tco_pci, -- SP5100_PCI_WATCHDOG_MISC_REG, -- &val); -- -- val |= SP5100_PCI_WATCHDOG_DECODE_EN; -- -- pci_write_config_dword(sp5100_tco_pci, -- SP5100_PCI_WATCHDOG_MISC_REG, -- val); -+ pr_info("Using 0x%08x for watchdog MMIO address\n", val); - -- /* Enable Watchdog timer and set the resolution to 1 sec. */ -- outb(SP5100_PM_WATCHDOG_CONTROL, SP5100_IO_PM_INDEX_REG); -- val = inb(SP5100_IO_PM_DATA_REG); -- val |= SP5100_PM_WATCHDOG_SECOND_RES; -- val &= ~SP5100_PM_WATCHDOG_DISABLE; -- outb(val, SP5100_IO_PM_DATA_REG); -+ /* Setup the watchdog timer */ -+ tco_timer_enable(); - -- /* Check that the watchdog action is set to reset the system. */ -+ /* Check that the watchdog action is set to reset the system */ - val = readl(SP5100_WDT_CONTROL(tcobase)); - val &= ~SP5100_PM_WATCHDOG_ACTION_RESET; - writel(val, SP5100_WDT_CONTROL(tcobase)); -@@ -355,6 +558,9 @@ static unsigned char __devinit sp5100_tco_setupdevice(void) - - unreg_mem_region: - release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE); -+unreg_resource: -+ if (resbase_phys) -+ release_resource(&wdt_res); - unreg_region: - release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE); - exit: -@@ -400,14 +606,17 @@ static int __devinit sp5100_tco_init(struct platform_device *dev) - - clear_bit(0, &timer_alive); - -- pr_info("initialized (0x%p). heartbeat=%d sec (nowayout=%d)\n", -- tcobase, heartbeat, nowayout); -+ pr_info("initialized (0x%p). heartbeat=%d sec (nowayout=%d, " -+ "force_addr=0x%x)\n", -+ tcobase, heartbeat, nowayout, force_addr); - - return 0; - - exit: - iounmap(tcobase); - release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE); -+ if (resbase_phys) -+ release_resource(&wdt_res); - release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE); - return ret; - } -@@ -422,6 +631,8 @@ static void __devexit sp5100_tco_cleanup(void) - misc_deregister(&sp5100_tco_miscdev); - iounmap(tcobase); - release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE); -+ if (resbase_phys) -+ release_resource(&wdt_res); - release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE); - } - -@@ -451,7 +662,7 @@ static int __init sp5100_tco_init_module(void) - { - int err; - -- pr_info("SP5100 TCO WatchDog Timer Driver v%s\n", TCO_VERSION); -+ pr_info("SP5100/SB800 TCO WatchDog Timer Driver v%s\n", TCO_VERSION); - - err = platform_driver_register(&sp5100_tco_driver); - if (err) -@@ -475,13 +686,13 @@ static void __exit sp5100_tco_cleanup_module(void) - { - platform_device_unregister(sp5100_tco_platform_device); - platform_driver_unregister(&sp5100_tco_driver); -- pr_info("SP5100 TCO Watchdog Module Unloaded\n"); -+ pr_info("SP5100/SB800 TCO Watchdog Module Unloaded\n"); - } - - module_init(sp5100_tco_init_module); - module_exit(sp5100_tco_cleanup_module); - - MODULE_AUTHOR("Priyanka Gupta"); --MODULE_DESCRIPTION("TCO timer driver for SP5100 chipset"); -+MODULE_DESCRIPTION("TCO timer driver for SP5100/SB800 chipset"); - MODULE_LICENSE("GPL"); - MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); -diff --git a/drivers/watchdog/sp5100_tco.h b/drivers/watchdog/sp5100_tco.h -index a5a16cc..71594a0 100644 ---- a/drivers/watchdog/sp5100_tco.h -+++ b/drivers/watchdog/sp5100_tco.h -@@ -9,33 +9,57 @@ - /* - * Some address definitions for the Watchdog - */ -- - #define SP5100_WDT_MEM_MAP_SIZE 0x08 - #define SP5100_WDT_CONTROL(base) ((base) + 0x00) /* Watchdog Control */ - #define SP5100_WDT_COUNT(base) ((base) + 0x04) /* Watchdog Count */ - --#define SP5100_WDT_START_STOP_BIT 1 -+#define SP5100_WDT_START_STOP_BIT (1 << 0) - #define SP5100_WDT_TRIGGER_BIT (1 << 7) - --#define SP5100_PCI_WATCHDOG_MISC_REG 0x41 --#define SP5100_PCI_WATCHDOG_DECODE_EN (1 << 3) -- - #define SP5100_PM_IOPORTS_SIZE 0x02 - --/* These two IO registers are hardcoded and there doesn't seem to be a way to -+/* -+ * These two IO registers are hardcoded and there doesn't seem to be a way to - * read them from a register. - */ -+ -+/* For SP5100/SB7x0 chipset */ - #define SP5100_IO_PM_INDEX_REG 0xCD6 - #define SP5100_IO_PM_DATA_REG 0xCD7 - -+#define SP5100_SB_RESOURCE_MMIO_BASE 0x9C -+ - #define SP5100_PM_WATCHDOG_CONTROL 0x69 --#define SP5100_PM_WATCHDOG_BASE0 0x6C --#define SP5100_PM_WATCHDOG_BASE1 0x6D --#define SP5100_PM_WATCHDOG_BASE2 0x6E --#define SP5100_PM_WATCHDOG_BASE3 0x6F -+#define SP5100_PM_WATCHDOG_BASE 0x6C - - #define SP5100_PM_WATCHDOG_FIRED (1 << 1) - #define SP5100_PM_WATCHDOG_ACTION_RESET (1 << 2) - --#define SP5100_PM_WATCHDOG_DISABLE 1 -+#define SP5100_PCI_WATCHDOG_MISC_REG 0x41 -+#define SP5100_PCI_WATCHDOG_DECODE_EN (1 << 3) -+ -+#define SP5100_PM_WATCHDOG_DISABLE (1 << 0) - #define SP5100_PM_WATCHDOG_SECOND_RES (3 << 1) -+ -+#define SP5100_DEVNAME "SP5100 TCO" -+ -+ -+/* For SB8x0(or later) chipset */ -+#define SB800_IO_PM_INDEX_REG 0xCD6 -+#define SB800_IO_PM_DATA_REG 0xCD7 -+ -+#define SB800_PM_ACPI_MMIO_EN 0x24 -+#define SB800_PM_WATCHDOG_CONTROL 0x48 -+#define SB800_PM_WATCHDOG_BASE 0x48 -+#define SB800_PM_WATCHDOG_CONFIG 0x4C -+ -+#define SB800_PCI_WATCHDOG_DECODE_EN (1 << 0) -+#define SB800_PM_WATCHDOG_DISABLE (1 << 2) -+#define SB800_PM_WATCHDOG_SECOND_RES (3 << 0) -+#define SB800_ACPI_MMIO_DECODE_EN (1 << 0) -+#define SB800_ACPI_MMIO_SEL (1 << 2) -+ -+ -+#define SB800_PM_WDT_MMIO_OFFSET 0xB00 -+ -+#define SB800_DEVNAME "SB800 TCO"