1 --- linux/drivers/net/wan/Kconfig 2008-01-24 23:58:37.000000000 +0100
2 +++ linux/drivers/net/wan/Kconfig 2008-01-30 14:04:26.000000000 +0100
4 comment "X.25/LAPB support is disabled"
5 depends on HDLC && (LAPB!=m || HDLC!=m) && LAPB!=y
8 + tristate "Tahoe 9xx support"
9 + depends on HDLC && PCI
11 + This driver is for Tahoe 931/932/971/972 cards
12 + If you have such a card, say Y or M here and see
13 + <http://www.tahoe.pl/>
15 + If you want to compile the driver as a module ( = code which can be
16 + inserted in and removed from the running kernel whenever you want),
17 + say M here and read <file:Documentation/modules.txt>. The module
18 + will be called tahoe9xx.o.
20 + If unsure, say N here.
23 tristate "Goramo PCI200SYN support"
24 depends on HDLC && PCI
25 --- linux/drivers/net/wan/Makefile 2008-01-24 23:58:37.000000000 +0100
26 +++ linux/drivers/net/wan/Makefile 2008-01-30 14:04:26.000000000 +0100
28 obj-$(CONFIG_PC300) += pc300.o
29 obj-$(CONFIG_N2) += n2.o
30 obj-$(CONFIG_C101) += c101.o
31 +obj-$(CONFIG_TAHOE9XX) += tahoe9xx.o
32 obj-$(CONFIG_WANXL) += wanxl.o
33 obj-$(CONFIG_PCI200SYN) += pci200syn.o
34 obj-$(CONFIG_PC300TOO) += pc300too.o
35 --- linux/drivers/net/wan/tahoe9xx.c 1970-01-01 01:00:00.000000000 +0100
36 +++ linux/drivers/net/wan/tahoe9xx.c 2008-01-30 14:27:09.000000000 +0100
39 + * Tahoe 9xx synchronous serial card driver for Linux
41 + * Copyright (C) 2002-2003 Krzysztof Halasa <khc@pm.waw.pl>
42 + * Copyright (C) 2003 Piotr Kaczmarzyk <piotr@tahoe.pl>
44 + * This program is free software; you can redistribute it and/or modify it
45 + * under the terms of version 2 of the GNU General Public License
46 + * as published by the Free Software Foundation.
48 + * For information see http://hq.pm.waw.pl/hdlc/
50 + * Sources of information:
51 + * Hitachi HD64570 SCA User's Manual
52 + * PLX Technology Inc. PCI9052 Data Book
53 + * Dallas Semiconductor DS21554 Datasheet
56 +#include <linux/module.h>
57 +#include <linux/kernel.h>
58 +#include <linux/slab.h>
59 +#include <linux/sched.h>
60 +#include <linux/types.h>
61 +#include <linux/fcntl.h>
62 +#include <linux/in.h>
63 +#include <linux/string.h>
64 +#include <linux/errno.h>
65 +#include <linux/init.h>
66 +#include <linux/ioport.h>
67 +#include <linux/moduleparam.h>
68 +#include <linux/netdevice.h>
69 +#include <linux/hdlc.h>
70 +#include <linux/pci.h>
71 +#include <asm/delay.h>
76 +static const char* version = "Tahoe 9xx driver version: 1.16t";
77 +static const char* devname = "TAHOE9XX";
79 +#define TAHOE9XX_PLX_SIZE 0x80 /* PLX control window size (128b) */
80 +#define TAHOE9XX_SCA_SIZE 0x100 /* SCA window size (256b) */
81 +#define ALL_PAGES_ALWAYS_MAPPED
82 +#define NEED_DETECT_RAM
83 +#define NEED_SCA_MSCI_INTR
84 +#define MAX_TX_BUFFERS 10
86 +#define CLOCK_BASE 9216000
91 +#define DEFAULT_LICR 0x80
93 +#define PCI_VENDOR_ID_TAHOE 0x8246
94 +#define PCI_DEVICE_ID_TAHOE931 0x0931
95 +#define PCI_DEVICE_ID_TAHOE932 0x0932
96 +#define PCI_DEVICE_ID_TAHOE971 0x0971
97 +#define PCI_DEVICE_ID_TAHOE972 0x0972
100 + * PLX PCI9052 local configuration and shared runtime registers.
101 + * This structure can be used to access 9052 registers (memory mapped).
104 + u32 loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */
105 + u32 loc_rom_range; /* 10h : Local ROM Range */
106 + u32 loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */
107 + u32 loc_rom_base; /* 24h : Local ROM Base */
108 + u32 loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */
109 + u32 rom_bus_descr; /* 38h : ROM Bus Descriptor */
110 + u32 cs_base[4]; /* 3C-48h : Chip Select Base Addrs */
111 + u32 intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */
112 + u32 init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */
119 +typedef struct ds21554_s {
120 + u8 vcr1; /* Counter: Violation Error */
122 + u8 crccr1; /* Counter: CRC4 Error */
124 + u8 ebcr1; /* Counter: E-bit Error (FEBE) */
126 + u8 sr1; /* Status: Status Register 1 */
127 + u8 sr2; /* Status: Status Register 2 */
128 + u8 rir; /* Status: Receive Information */
130 + u8 idr; /* Misc: Device Indentification */
131 + u8 rcr1; /* Control: Receive Control 1 */
132 + u8 rcr2; /* Control: Receive Control 2 */
133 + u8 tcr1; /* Control: Transmit Control 1 */
134 + u8 tcr2; /* Control: Transmit Control 2 */
135 + u8 ccr1; /* Control: Common Control 1 */
137 + u8 imr1; /* Interrupt Mask 1 */
138 + u8 imr2; /* Interrupt Mask 2 */
139 + u8 licr; /* Control: Line interface */
141 + u8 ccr2; /* Control: Common Control 2 */
142 + u8 ccr3; /* Control: Common Control 3 */
143 + u8 tsacr; /* Control: Transmit Sa bit */
144 + u8 ccr6; /* Control: Common Control 6 */
145 + u8 ssr; /* Status: Synchronizer Status */
146 + u8 rnaf; /* Receive non-align frame */
147 + u8 taf; /* Transmit align frame */
148 + u8 tnaf; /* Transmit non-align frame */
149 + u8 tcbr1; /* Transmit channel blocking */
153 + u8 tir1; /* Transmit idle */
157 + u8 tidr; /* Transmit idle definition */
158 + u8 rcbr1; /* Receive channel blocking */
162 + u8 raf; /* Receive align frame */
163 + u8 rs1; /* Receive signalling */
179 + u8 ts1; /* Transmit signaling */
195 + u8 tsiaf; /* Transmit Si Bits Align Frame */
196 + u8 tsinaf; /* Transmit Si Bits Non-align Frame */
197 + u8 tra; /* Transmit Remote Alarm Bits */
198 + u8 tsa4; /* Transmit Sa Bits */
203 + u8 rsiaf; /* Receive Si Bits Align Frame */
204 + u8 rsinaf; /* Receive Si Bits Non-Align Frame */
205 + u8 rra; /* Receive Remote Alarm Bits */
206 + u8 rsa4; /* Receive Sa Bits */
211 + u8 tc1; /* Transmit channel */
243 + u8 rc1; /* Receive channel */
275 + u8 tcc1; /* Transmit channel control */
279 + u8 rcc1; /* Receive channel control */
283 + u8 ccr4; /* Control: Common Control 4 */
284 + u8 tds0m; /* Transmit DS0 Monitor */
285 + u8 ccr5; /* Control: Common Control 5 */
286 + u8 rds0m; /* Receive DS0 Monitor */
289 + u8 hcr; /* HDLC Control */
290 + u8 hsr; /* HDLC Status */
291 + u8 himr; /* HDLC Interrupt Mask */
292 + u8 rhir; /* Receive HDLC Information */
293 + u8 rhfr; /* Receive HDLC FIFO */
294 + u8 ibo; /* Interleave Bus Operation */
295 + u8 thir; /* Transmit HDLC Information */
296 + u8 thfr; /* Transmit HDLC FIFO */
297 + u8 rdc1; /* Receive HDLC DS0 Control 1 */
298 + u8 rdc2; /* Receive HDLC DS0 Control 2 */
299 + u8 tdc1; /* Transmit HDLC DS0 Control 1 */
300 + u8 tdc2; /* Transmit HDLC DS0 Control 2 */
304 +typedef struct port_s {
305 + struct net_device *dev;
306 + struct card_s *card;
307 + spinlock_t lock; /* TX lock */
308 + te1_settings settings;
309 + int rxpart; /* partial frame received, next frame invalid*/
310 + unsigned short encoding;
311 + unsigned short parity;
312 + u16 rxin; /* rx ring buffer 'in' pointer */
313 + u16 txin; /* tx ring buffer 'in' and 'last' pointers */
315 + u8 rxs, txs, tmc; /* SCA registers */
316 + u8 phy_node; /* physical port # - 0 or 1 */
317 + u32 dsphys; /* DS21544 memory base (physical) */
318 + ds21554_t* dsbase; /* DS21544 memory base (virtual) */
319 + u8 g703_on; /* Enable/disable G.703 transceiver */
320 + u8 g703_coding; /* G.703 line coding */
321 + u8 g703_idlecode; /* G.703 idle timeslots contents */
324 +typedef struct card_s {
325 + u8* __iomem rambase; /* buffer memory base (virtual) */
326 + u8* __iomem scabase; /* SCA memory base (virtual) */
327 + plx9052* __iomem plxbase; /* PLX registers memory base (virtual) */
328 + u16 rx_ring_buffers; /* number of buffers in a ring */
329 + u16 tx_ring_buffers;
330 + u16 buff_offset; /* offset of first buffer of first channel */
331 + u8 irq; /* interrupt request level */
332 + u8 no_ports; /* number of ports */
333 + char dev_name[10]; /* device name */
337 +#define sca_in(reg, card) readb(card->scabase + (reg))
338 +#define sca_out(value, reg, card) writeb(value, card->scabase + (reg))
339 +#define sca_inw(reg, card) readw(card->scabase + (reg))
340 +#define sca_outw(value, reg, card) writew(value, card->scabase + (reg))
341 +#define sca_inl(reg, card) readl(card->scabase + (reg))
342 +#define sca_outl(value, reg, card) writel(value, card->scabase + (reg))
344 +#define port_to_card(port) (port->card)
345 +#define log_node(port) (port->phy_node)
346 +#define phy_node(port) (port->phy_node)
347 +#define winbase(card) (card->rambase)
348 +#define get_port(card, port) (&card->ports[port])
349 +#define sca_flush(card) (sca_in(IER0, card));
351 +static inline void new_memcpy_toio(char __iomem *dest, char *src, int length)
356 + len = length > 64 ? 64 : length; /* 32 */
357 + memcpy_toio(dest, src, len);
366 +#define memcpy_toio new_memcpy_toio
368 +#include "hd6457x.c"
370 +void init_ds21554(port_t *port);
372 +static void t9xx_set_iface(port_t *port)
374 + card_t *card = port->card;
375 + u8 msci = get_msci(port);
376 + u8 rxs = port->rxs & CLK_BRG_MASK;
377 + u8 txs = port->txs & CLK_BRG_MASK;
379 + if (port->dsbase) {
380 + init_ds21554(port);
383 + rxs |= CLK_LINE_RX; /* RXC input */
384 + txs |= CLK_LINE_TX; /* TXC input */
388 + sca_out(rxs, msci + RXS, card);
389 + sca_out(txs, msci + TXS, card);
390 + sca_set_port(port);
395 +static int t9xx_open(struct net_device *dev)
397 + port_t *port = dev_to_port(dev);
399 + int result = hdlc_open(dev);
404 + t9xx_set_iface(port);
405 + sca_flush(port_to_card(port));
411 +static int t9xx_close(struct net_device *dev)
414 + sca_flush(port_to_card(dev_to_port(dev)));
421 +static int t9xx_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
423 + const size_t size = sizeof(te1_settings);
424 + te1_settings new_line;
425 + te1_settings __user *line = ifr->ifr_settings.ifs_ifsu.te1;
426 + port_t *port = dev_to_port(dev);
429 + if (cmd == SIOCDEVPRIVATE) {
430 + sca_dump_rings(dev);
434 + if (cmd != SIOCWANDEV)
435 + return hdlc_ioctl(dev, ifr, cmd);
437 + switch(ifr->ifr_settings.type) {
440 + ifr->ifr_settings.type = IF_IFACE_E1;
442 + ifr->ifr_settings.type = IF_IFACE_V35;
443 + if (ifr->ifr_settings.size < size) {
444 + ifr->ifr_settings.size = size; /* data size wanted */
447 + if (copy_to_user(line, &port->settings, size))
453 + if (!capable(CAP_NET_ADMIN))
456 + if (copy_from_user(&new_line, line, size))
459 + if (new_line.clock_type != CLOCK_EXT)
460 + return -EINVAL; /* No such clock setting */
462 + if (new_line.loopback > 3)
465 + memcpy(&port->settings, &new_line, size); /* Update settings */
466 + t9xx_set_iface(port);
467 + sca_flush(port_to_card(port));
471 + return hdlc_ioctl(dev, ifr, cmd);
477 +static void t9xx_pci_remove_one(struct pci_dev *pdev)
480 + card_t *card = pci_get_drvdata(pdev);
482 + if ((pdev->subsystem_device == PCI_DEVICE_ID_TAHOE932) ||
483 + (pdev->subsystem_device == PCI_DEVICE_ID_TAHOE972))
487 + for(i = 0; i < ports; i++)
488 + if (card->ports[i].card) {
489 + struct net_device *dev = port_to_dev(&card->ports[i]);
490 + unregister_hdlc_device(dev);
494 + iounmap(card->rambase);
496 + iounmap(card->scabase);
498 + iounmap(card->plxbase);
500 + pci_release_regions(pdev);
501 + pci_disable_device(pdev);
502 + pci_set_drvdata(pdev, NULL);
503 + if (card->ports[0].dev)
504 + free_netdev(card->ports[0].dev);
505 + if ((ports == 2) && (card->ports[1].dev))
506 + free_netdev(card->ports[1].dev);
510 +static void ds21554_update_licr(port_t *port)
512 + port->dsbase->licr = DEFAULT_LICR | (port->settings.egl << 4) | (port->g703_on == 0);
515 +static void ds21554_update_registers(port_t *port)
517 + ds21554_t *ds = port->dsbase;
519 + if (port->settings.slot_map == 0xffffffff) {
521 + ds->ccr1 = 0x08 | (port->g703_coding << 6) | (port->g703_coding << 2);
524 + ds->ccr2 = 0x80; //84
525 + ds->tir1 = 0; ds->tir2 = 0; ds->tir3 = 0; ds->tir4 = 0;
526 + ds->tcc1 = 0; ds->tcc2 = 0; ds->tcc3 = 0; ds->tcc4 = 0;
527 + ds->rcc1 = 0; ds->rcc2 = 0; ds->rcc3 = 0; ds->rcc4 = 0;
528 + ds->rcbr1 = 0xff; ds->rcbr2 = 0xff;
529 + ds->rcbr3 = 0xff; ds->rcbr4 = 0xff;
530 + ds->tcbr1 = 0xff; ds->tcbr2 = 0xff;
531 + ds->tcbr3 = 0xff; ds->tcbr4 = 0xff;
538 + ds->ccr6 = 0x03; /* elastic buffers reset */
540 + ds->ccr6 = 0x00; /* elastic buffers reset */
542 + ds->ccr5 = 0x60; /* elastic buffers align */
546 + ds->ccr1 = 0x08 | (port->g703_coding << 6) | (port->g703_coding << 2)
547 + | (port->settings.crc4 << 4) | (port->settings.crc4);
549 + ds->ccr2 = 0x94; /* Automatic alarm generation */
551 + /* Receive channels */
552 + ds->rcbr1 = port->settings.slot_map & 0xff;
553 + ds->rcbr2 = (port->settings.slot_map >> 8) & 0xff;
554 + ds->rcbr3 = (port->settings.slot_map >> 16) & 0xff;
555 + ds->rcbr4 = (port->settings.slot_map >> 24) & 0xff;
557 + /* Transmit channels */
558 + ds->tcbr1 = port->settings.slot_map & 0xff;
559 + ds->tcbr2 = (port->settings.slot_map >> 8) & 0xff;
560 + ds->tcbr3 = (port->settings.slot_map >> 16) & 0xff;
561 + ds->tcbr4 = (port->settings.slot_map >> 24) & 0xff;
563 + /* Transmit idle */
564 + /* (remaining timeslots are filled with idle code) */
565 + ds->tir1 = ~port->settings.slot_map & 0xfe; /* Slot 0 is never idle */
566 + ds->tir2 = (~port->settings.slot_map >> 8) & 0xff;
567 + ds->tir3 = (~port->settings.slot_map >> 16) & 0xff;
568 + ds->tir4 = (~port->settings.slot_map >> 24) & 0xff;
569 + ds->rcr2 = 0x06; /* RSYSCLK = 2048, rx elastic store enabled */
570 + ds->ccr3 = 0x82; /* TSYSCLK = 2048, tx elastic store enabled */
572 + ds->ccr6 = 0x07; /* elastic buffers reset */
574 + ds->ccr6 = 0x04; /* elastic buffers reset */
576 + ds->ccr5 = 0x60; /* elastic buffers align */
582 +void init_ds21554(port_t *port)
584 + ds21554_t *ds = port->dsbase;
588 + ds->ccr5 = 0x80; /* Line Interface Reset */
591 + ds->ccr5 = 0xe0; /* Elastic Buffers Reset */
594 + ds->ccr6 = 0x04; /* TCLK from RCLK */
596 + ds21554_update_licr(port);
598 + /* Setup HDB3, CRC4, CAS/CCS, G.802 */
599 + ds21554_update_registers(port);
601 + ds->ccr2 = 0x94; /* Automatic alarm generation */
606 + ds21554_update_registers(port);
608 + ds->tidr = port->g703_idlecode;
610 +// ds->ccr4 |= 0x40;
614 +static int __devinit t9xx_pci_init_one(struct pci_dev *pdev,
615 + const struct pci_device_id *ent)
618 + u8 rev_id, tahoe97x = 0;
622 + u32 ramphys; /* buffer memory base */
623 + u32 scaphys; /* SCA memory base */
624 + u32 plxphys; /* PLX registers memory base */
627 + static int printed_version;
628 + if (!printed_version++)
629 + printk(KERN_INFO "%s\n", version);
632 + i = pci_enable_device(pdev);
636 + i = pci_request_regions(pdev, "Tahoe9xx");
638 + pci_disable_device(pdev);
642 + card = kmalloc(sizeof(card_t), GFP_KERNEL);
643 + if (card == NULL) {
644 + printk(KERN_ERR "%s: unable to allocate memory\n", card->dev_name);
645 + pci_release_regions(pdev);
646 + pci_disable_device(pdev);
649 + memset(card, 0, sizeof(card_t));
650 + pci_set_drvdata(pdev, card);
651 + card->ports[0].dev = alloc_hdlcdev(&card->ports[0]);
652 + card->ports[1].dev = alloc_hdlcdev(&card->ports[1]);
653 + if (!card->ports[0].dev || !card->ports[1].dev) {
654 + printk(KERN_ERR "tahoe9xx: unable to allocate memory\n");
655 + t9xx_pci_remove_one(pdev);
659 + sprintf(card->dev_name, "Tahoe");
660 + switch (pdev->subsystem_device) {
661 + case PCI_DEVICE_ID_TAHOE931:
662 + strcat(card->dev_name, "931");
663 + card->no_ports = 1;
665 + case PCI_DEVICE_ID_TAHOE932:
666 + strcat(card->dev_name, "932");
667 + card->no_ports = 2;
669 + case PCI_DEVICE_ID_TAHOE971:
670 + strcat(card->dev_name, "971");
672 + card->no_ports = 1;
674 + case PCI_DEVICE_ID_TAHOE972:
675 + strcat(card->dev_name, "972");
677 + card->no_ports = 2;
680 + strcat(card->dev_name, "9xx");
681 + card->no_ports = 0;
685 + pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
686 + if (pci_resource_len(pdev, 0) != TAHOE9XX_PLX_SIZE ||
687 + pci_resource_len(pdev, 2) != TAHOE9XX_SCA_SIZE ||
688 + pci_resource_len(pdev, 3) < 16384) {
689 + printk(KERN_ERR "%s: invalid card EEPROM parameters\n", card->dev_name);
690 + t9xx_pci_remove_one(pdev);
694 + plxphys = pci_resource_start(pdev,0) & PCI_BASE_ADDRESS_MEM_MASK;
695 + card->plxbase = ioremap(plxphys, TAHOE9XX_PLX_SIZE);
697 + scaphys = pci_resource_start(pdev,2) & PCI_BASE_ADDRESS_MEM_MASK;
698 + card->scabase = ioremap(scaphys, TAHOE9XX_SCA_SIZE);
700 + ramphys = pci_resource_start(pdev,3) & PCI_BASE_ADDRESS_MEM_MASK;
701 + card->rambase = ioremap(ramphys, pci_resource_len(pdev,3));
704 + for (i=0; i < card->no_ports; i++) {
705 + card->ports[i].dsphys = pci_resource_start(pdev,4+i) & PCI_BASE_ADDRESS_MEM_MASK;
706 + card->ports[i].dsbase = (ds21554_t *)ioremap(card->ports[i].dsphys, pci_resource_len(pdev,4+i));
709 + for (i=0; i < card->no_ports; i++)
710 + card->ports[i].dsbase = (ds21554_t *)0;
713 + if (card->plxbase == NULL ||
714 + card->scabase == NULL ||
715 + card->rambase == NULL) {
716 + printk(KERN_ERR "tahoe9xx: ioremap() failed\n");
717 + t9xx_pci_remove_one(pdev);
721 + p = &card->plxbase->init_ctrl;
722 + writel(readl(p) | 0x40000000, p);
723 + readl(p); /* Flush the write - do not use sca_flush */
726 + writel(readl(p) & ~0x40000000, p);
727 + readl(p); /* Flush the write - do not use sca_flush */
730 + ramsize = sca_detect_ram(card, card->rambase,
731 + pci_resource_len(pdev,3));
733 + /* number of TX + RX buffers for one port - this is dual port card */
734 + i = ramsize / (2 * (sizeof(pkt_desc) + HDLC_MAX_MRU));
735 + card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS);
736 + card->rx_ring_buffers = i - card->tx_ring_buffers;
738 + card->buff_offset = 2 * sizeof(pkt_desc) * (card->tx_ring_buffers +
739 + card->rx_ring_buffers);
741 + printk(KERN_INFO "%s: %u KB RAM at 0x%x, IRQ%u, using %u TX +"
742 + " %u RX packets rings\n", card->dev_name, ramsize / 1024,
743 + ramphys, pdev->irq,
744 + card->tx_ring_buffers, card->rx_ring_buffers);
746 + for (i=0; i < card->no_ports; i++) {
747 + /* Make sure DS21554 is there */
748 + card->ports[i].dsbase->idr = 0x00;
749 + card->ports[i].dsbase->tc1 = 0xaa;
750 + card->ports[i].dsbase->rc1 = 0x55;
751 + if (((card->ports[i].dsbase->idr & 0xf0) == 0xa0) && (card->ports[i].dsbase->tc1 == 0xaa) && (card->ports[i].dsbase->rc1 == 0x55)) {
752 + printk(KERN_INFO "%s: DS21554 (port %d) detected at 0x%x\n", card->dev_name, i, card->ports[i].dsphys);
753 + /* Clear registers */
754 + memset(card->ports[i].dsbase, 0, 256);
755 + /* Default settings */
756 + card->ports[i].g703_on = 1;
757 + card->ports[i].settings.egl = 0;
758 + card->ports[i].g703_coding = G703_HDB3;
759 + card->ports[i].g703_idlecode = 0x54;
760 + card->ports[i].settings.crc4 = 1;
762 + card->ports[i].settings.slot_map = 0xffffffff;
763 + init_ds21554(&card->ports[i]);
765 + printk(KERN_INFO "%s: DS21554 (port %d) test failed!\n", card->dev_name, i);
769 + if (card->tx_ring_buffers < 1) {
770 + printk(KERN_ERR "%s: RAM test failed\n", card->dev_name);
771 + t9xx_pci_remove_one(pdev);
775 + /* Enable interrupts on the PCI bridge */
776 + p = &card->plxbase->intr_ctrl_stat;
777 + writew(readw(p) | 0x0040, p);
780 + if(request_irq(pdev->irq, sca_intr, IRQF_SHARED, devname, card)) {
781 + printk(KERN_WARNING "%s: could not allocate IRQ%d.\n", card->dev_name,
783 + t9xx_pci_remove_one(pdev);
786 + card->irq = pdev->irq;
790 + for(i = 0; i < card->no_ports; i++) {
791 + port_t *port = &card->ports[i];
792 + struct net_device *dev = port_to_dev(port);
793 + hdlc_device *hdlc = dev_to_hdlc(dev);
794 + port->phy_node = i;
796 + spin_lock_init(&port->lock);
797 + dev->irq = card->irq;
798 + dev->mem_start = ramphys;
799 + dev->mem_end = ramphys + ramsize - 1;
800 + dev->tx_queue_len = 50;
801 + dev->do_ioctl = t9xx_ioctl;
802 + dev->open = t9xx_open;
803 + dev->stop = t9xx_close;
804 + hdlc->attach = sca_attach;
805 + hdlc->xmit = sca_xmit;
806 + port->settings.clock_type = CLOCK_EXT;
808 + if(register_hdlc_device(dev)) {
809 + printk(KERN_ERR "%s: unable to register hdlc "
810 + "device\n", card->dev_name);
812 + t9xx_pci_remove_one(pdev);
815 + sca_init_sync_port(port); /* Set up SCA memory */
817 + printk(KERN_INFO "%s: %s node %d\n",
818 + dev->name, card->dev_name, port->phy_node);
827 +static struct pci_device_id t9xx_pci_tbl[] __devinitdata = {
828 + { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
829 + PCI_VENDOR_ID_TAHOE, PCI_ANY_ID,
834 +static struct pci_driver t9xx_pci_driver = {
836 + id_table: t9xx_pci_tbl,
837 + probe: t9xx_pci_init_one,
838 + remove: t9xx_pci_remove_one,
841 +static int __init t9xx_init_module(void)
844 + printk(KERN_INFO "%s\n", version);
846 + return pci_register_driver(&t9xx_pci_driver);
851 +static void __exit t9xx_cleanup_module(void)
853 + pci_unregister_driver(&t9xx_pci_driver);
856 +MODULE_AUTHOR("Piotr Kaczmarzyk <piotr@tahoe.pl>");
857 +MODULE_DESCRIPTION("Tahoe 9xx serial port driver");
858 +MODULE_LICENSE("GPL v2");
859 +MODULE_DEVICE_TABLE(pci, t9xx_pci_tbl);
860 +module_init(t9xx_init_module);
861 +module_exit(t9xx_cleanup_module);
862 --- linux/include/linux/hdlc/ioctl.h 2008-01-24 23:58:37.000000000 +0100
863 +++ linux/include/linux/hdlc/ioctl.h 2008-01-30 14:04:26.000000000 +0100
865 unsigned int clock_type; /* internal, external, TX-internal etc. */
866 unsigned short loopback;
867 unsigned int slot_map;
868 + unsigned short crc4;
869 + unsigned short egl;
870 } te1_settings; /* T1, E1 */