1 2005-10-28 Gwenole Beauchesne <gbeauchesne@mandriva.com>
3 * Various additional hacks for GCC4.
5 --- qemu-0.7.2/target-i386/ops_sse.h.gcc4-hacks 2005-09-04 19:11:31.000000000 +0200
6 +++ qemu-0.7.2/target-i386/ops_sse.h 2005-10-28 10:09:21.000000000 +0200
11 +#if defined(__i386__) && __GNUC__ >= 4
12 +#define RegCopy(d, s) __builtin_memcpy(&(d), &(s), sizeof(d))
15 +#define RegCopy(d, s) d = s
18 void OPPROTO glue(op_psrlw, SUFFIX)(void)
20 @@ -570,7 +576,7 @@ void OPPROTO glue(op_pshufw, SUFFIX) (vo
21 r.W(1) = s->W((order >> 2) & 3);
22 r.W(2) = s->W((order >> 4) & 3);
23 r.W(3) = s->W((order >> 6) & 3);
28 void OPPROTO op_shufps(void)
29 --- qemu-0.7.2/target-i386/helper.c.gcc4-hacks 2005-09-04 19:11:31.000000000 +0200
30 +++ qemu-0.7.2/target-i386/helper.c 2005-10-28 10:09:21.000000000 +0200
31 @@ -3130,8 +3130,15 @@ void helper_fxrstor(target_ulong ptr, in
32 nb_xmm_regs = 8 << data64;
34 for(i = 0; i < nb_xmm_regs; i++) {
35 +#if defined(__i386__) && __GNUC__ >= 4
36 + env->xmm_regs[i].XMM_L(0) = ldl(addr);
37 + env->xmm_regs[i].XMM_L(1) = ldl(addr + 4);
38 + env->xmm_regs[i].XMM_L(2) = ldl(addr + 8);
39 + env->xmm_regs[i].XMM_L(3) = ldl(addr + 12);
41 env->xmm_regs[i].XMM_Q(0) = ldq(addr);
42 env->xmm_regs[i].XMM_Q(1) = ldq(addr + 8);
47 --- qemu-0.7.2/cpu-all.h.gcc4-hacks 2005-09-04 19:11:31.000000000 +0200
48 +++ qemu-0.7.2/cpu-all.h 2005-10-28 10:09:21.000000000 +0200
51 static inline void stq_le_p(void *ptr, uint64_t v)
53 +#if defined(__i386__) && __GNUC__ >= 4
54 + const union { uint64_t v; uint32_t p[2]; } x = { .v = v };
55 + ((uint32_t *)ptr)[0] = x.p[0];
56 + ((uint32_t *)ptr)[1] = x.p[1];
63 --- qemu-0.7.2/softmmu_header.h.gcc4-hacks 2005-10-28 10:08:08.000000000 +0200
64 +++ qemu-0.7.2/softmmu_header.h 2005-10-28 10:09:21.000000000 +0200
66 void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int is_user);
68 #if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
69 - (ACCESS_TYPE <= 1) && defined(ASM_SOFTMMU)
70 + (ACCESS_TYPE <= 1) && defined(ASM_SOFTMMU) && (__GNUC__ < 4)
72 #define CPU_TLB_ENTRY_BITS 4
74 @@ -131,7 +131,7 @@ static inline RES_TYPE glue(glue(ld, USU
75 "m" (*(uint32_t *)offsetof(CPUState, tlb_read[CPU_MEM_INDEX][0].address)),
77 "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
78 - : "%eax", "%ecx", "%edx", "memory", "cc");
79 + : "%eax", "%edx", "memory", "cc");
83 @@ -178,13 +178,14 @@ static inline int glue(glue(lds, SUFFIX)
84 "m" (*(uint32_t *)offsetof(CPUState, tlb_read[CPU_MEM_INDEX][0].address)),
86 "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
87 - : "%eax", "%ecx", "%edx", "memory", "cc");
88 + : "%eax", "%edx", "memory", "cc");
93 -static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)
94 +static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE val)
97 asm volatile ("movl %0, %%edx\n"
100 @@ -236,16 +237,14 @@
104 -/* NOTE: 'q' would be needed as constraint, but we could not use it
108 "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
109 "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
110 "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
111 "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MEM_INDEX][0].addr_write)),
113 "m" (*(uint8_t *)&glue(glue(__st, SUFFIX), MMUSUFFIX))
114 - : "%eax", "%ecx", "%edx", "memory", "cc");
115 + : "%eax", "%edx", "memory", "cc");
118 /* TODO: handle 64-bit access sizes and addresses */