linux-2.6-sk98lin-8.36.1.3.patch

   1 diff -ruN linux/drivers/net/sk98lin/Makefile linux-new/drivers/net/sk98lin/Makefile
   2 --- linux/drivers/net/sk98lin/Makefile  2006-09-20 05:42:06.000000000 +0200
   3 +++ linux-new/drivers/net/sk98lin/Makefile      2006-09-20 18:58:01.423265750 +0200
   4 @@ -1,6 +1,59 @@
   5 +#******************************************************************************
   6  #
   7 -# Makefile for the SysKonnect SK-98xx device driver.
   8 +# Name:         skge.c
   9 +# Project:      GEnesis, PCI Gigabit Ethernet Adapter
  10 +# Version:      $Revision$
  11 +# Date:         $Date$
  12 +# Purpose:      The main driver source module
  13  #
  14 +#******************************************************************************
  15 +
  16 +#******************************************************************************
  17 +#
  18 +#      (C)Copyright 1998-2002 SysKonnect GmbH.
  19 +#      (C)Copyright 2002-2005 Marvell.
  20 +#
  21 +#      Makefile for Marvell Yukon chipset and SysKonnect Gigabit Ethernet
  22 +#      Server Adapter driver. (Kernel 2.6)
  23 +#
  24 +#      Author: Mirko Lindner (mlindner@syskonnect.de)
  25 +#              Ralph Roesler (rroesler@syskonnect.de)
  26 +#
  27 +#      Address all question to: linux@syskonnect.de
  28 +#
  29 +#      This program is free software; you can redistribute it and/or modify
  30 +#      it under the terms of the GNU General Public License as published by
  31 +#      the Free Software Foundation; either version 2 of the License, or
  32 +#      (at your option) any later version.
  33 +#
  34 +#      The information in this file is provided "AS IS" without warranty.
  35 +#
  36 +#******************************************************************************
  37 +
  38 +#******************************************************************************
  39 +#
  40 +# History:
  41 +#
  42 +#      $Log$
  43 +#      Revision 1.9.2.1  2005/04/11 09:01:18  mlindner
  44 +#      Fix: Copyright year changed
  45 +#
  46 +#      Revision 1.9  2004/07/13 15:54:50  rroesler
  47 +#      Add: file skethtool.c
  48 +#      Fix: corrected header regarding copyright
  49 +#      Fix: minor typos corrected
  50 +#
  51 +#      Revision 1.8  2004/06/08 08:39:38  mlindner
  52 +#      Fix: Add CONFIG_SK98LIN_ZEROCOPY as default
  53 +#
  54 +#      Revision 1.7  2004/06/03 16:06:56  mlindner
  55 +#      Fix: Added compile flag SK_DIAG_SUPPORT
  56 +#
  57 +#      Revision 1.6  2004/06/02 08:02:59  mlindner
  58 +#      Add: Changed header information and inserted a GPL statement
  59 +#
  60 +#
  61 +#******************************************************************************
  62
  63
  64  #
  65 @@ -13,20 +66,24 @@
  66  obj-$(CONFIG_SK98LIN) += sk98lin.o
  67  sk98lin-objs    :=     \
  68                 skge.o          \
  69 +               sky2.o          \
  70                 skethtool.o     \
  71 +               sky2le.o        \
  72                 skdim.o         \
  73                 skaddr.o        \
  74                 skgehwt.o       \
  75                 skgeinit.o      \
  76                 skgepnmi.o      \
  77                 skgesirq.o      \
  78 -               ski2c.o         \
  79 +               sktwsi.o                \
  80                 sklm80.o        \
  81                 skqueue.o       \
  82                 skrlmt.o        \
  83                 sktimer.o       \
  84                 skvpd.o         \
  85 -               skxmac2.o
  86 +               skxmac2.o       \
  87 +               skproc.o        \
  88 +               skcsum.o
  89
  90  # DBGDEF =  \
  91  # -DDEBUG
  92 @@ -75,13 +132,11 @@
  93  # SK_DBGCAT_DRV_INT_SRC         0x04000000      interrupts sources
  94  # SK_DBGCAT_DRV_EVENT           0x08000000      driver events
  95
  96 -EXTRA_CFLAGS += -Idrivers/net/sk98lin -DSK_DIAG_SUPPORT -DGENESIS -DYUKON $(DBGDEF) $(SKPARAM)
  97 +EXTRA_CFLAGS += -Idrivers/net/sk98lin -DSK_USE_CSUM -DSK_DIAG_SUPPORT \
  98 +               -DGENESIS -DYUKON -DYUK2 -DCONFIG_SK98LIN_ZEROCOPY \
  99 +               $(DBGDEF) $(SKPARAM)
 100
 101  clean:
 102         rm -f core *.o *.a *.s
 103
 104
 105 -
 106 -
 107 -
 108 -
 109 diff -ruN linux/drivers/net/sk98lin/h/lm80.h linux-new/drivers/net/sk98lin/h/lm80.h
 110 --- linux/drivers/net/sk98lin/h/lm80.h  2006-09-20 05:42:06.000000000 +0200
 111 +++ linux-new/drivers/net/sk98lin/h/lm80.h      2006-07-28 14:13:54.000000000 +0200
 112 @@ -2,8 +2,8 @@
 113   *
 114   * Name:       lm80.h
 115   * Project:    Gigabit Ethernet Adapters, Common Modules
 116 - * Version:    $Revision$
 117 - * Date:       $Date$
 118 + * Version:    $Revision$
 119 + * Date:       $Date$
 120   * Purpose:    Contains all defines for the LM80 Chip
 121   *             (National Semiconductor).
 122   *
 123 @@ -11,6 +11,7 @@
 124
 125  /******************************************************************************
 126   *
 127 + *     LICENSE:
 128   *     (C)Copyright 1998-2002 SysKonnect.
 129   *     (C)Copyright 2002-2003 Marvell.
 130   *
 131 @@ -20,6 +21,7 @@
 132   *     (at your option) any later version.
 133   *
 134   *     The information in this file is provided "AS IS" without warranty.
 135 + *     /LICENSE
 136   *
 137   ******************************************************************************/
 138
 139 diff -ruN linux/drivers/net/sk98lin/h/skaddr.h linux-new/drivers/net/sk98lin/h/skaddr.h
 140 --- linux/drivers/net/sk98lin/h/skaddr.h        2006-09-20 05:42:06.000000000 +0200
 141 +++ linux-new/drivers/net/sk98lin/h/skaddr.h    2006-07-28 14:13:54.000000000 +0200
 142 @@ -2,14 +2,15 @@
 143   *
 144   * Name:       skaddr.h
 145   * Project:    Gigabit Ethernet Adapters, ADDR-Modul
 146 - * Version:    $Revision$
 147 - * Date:       $Date$
 148 + * Version:    $Revision$
 149 + * Date:       $Date$
 150   * Purpose:    Header file for Address Management (MC, UC, Prom).
 151   *
 152   ******************************************************************************/
 153
 154  /******************************************************************************
 155   *
 156 + *     LICENSE:
 157   *     (C)Copyright 1998-2002 SysKonnect GmbH.
 158   *     (C)Copyright 2002-2003 Marvell.
 159   *
 160 @@ -19,6 +20,7 @@
 161   *     (at your option) any later version.
 162   *
 163   *     The information in this file is provided "AS IS" without warranty.
 164 + *     /LICENSE
 165   *
 166   ******************************************************************************/
 167
 168 @@ -236,6 +238,18 @@
 169         SK_U32  PortNumber,
 170         int     Flags);
 171
 172 +extern int     SkAddrXmacMcClear(
 173 +       SK_AC   *pAC,
 174 +       SK_IOC  IoC,
 175 +       SK_U32  PortNumber,
 176 +       int     Flags);
 177 +
 178 +extern int     SkAddrGmacMcClear(
 179 +       SK_AC   *pAC,
 180 +       SK_IOC  IoC,
 181 +       SK_U32  PortNumber,
 182 +       int     Flags);
 183 +
 184  extern int     SkAddrMcAdd(
 185         SK_AC           *pAC,
 186         SK_IOC          IoC,
 187 @@ -243,11 +257,41 @@
 188         SK_MAC_ADDR     *pMc,
 189         int             Flags);
 190
 191 +extern int     SkAddrXmacMcAdd(
 192 +       SK_AC           *pAC,
 193 +       SK_IOC          IoC,
 194 +       SK_U32          PortNumber,
 195 +       SK_MAC_ADDR     *pMc,
 196 +       int             Flags);
 197 +
 198 +extern SK_U32  SkXmacMcHash(
 199 +       unsigned char *pMc);
 200 +
 201 +extern int     SkAddrGmacMcAdd(
 202 +       SK_AC           *pAC,
 203 +       SK_IOC          IoC,
 204 +       SK_U32          PortNumber,
 205 +       SK_MAC_ADDR     *pMc,
 206 +       int             Flags);
 207 +
 208 +extern SK_U32  SkGmacMcHash(
 209 +       unsigned char *pMc);
 210 +
 211  extern int     SkAddrMcUpdate(
 212         SK_AC   *pAC,
 213         SK_IOC  IoC,
 214         SK_U32  PortNumber);
 215
 216 +extern int     SkAddrXmacMcUpdate(
 217 +       SK_AC   *pAC,
 218 +       SK_IOC  IoC,
 219 +       SK_U32  PortNumber);
 220 +
 221 +extern int     SkAddrGmacMcUpdate(
 222 +       SK_AC   *pAC,
 223 +       SK_IOC  IoC,
 224 +       SK_U32  PortNumber);
 225 +
 226  extern int     SkAddrOverride(
 227         SK_AC           *pAC,
 228         SK_IOC          IoC,
 229 @@ -261,6 +305,18 @@
 230         SK_U32  PortNumber,
 231         int     NewPromMode);
 232
 233 +extern int     SkAddrXmacPromiscuousChange(
 234 +       SK_AC   *pAC,
 235 +       SK_IOC  IoC,
 236 +       SK_U32  PortNumber,
 237 +       int     NewPromMode);
 238 +
 239 +extern int     SkAddrGmacPromiscuousChange(
 240 +       SK_AC   *pAC,
 241 +       SK_IOC  IoC,
 242 +       SK_U32  PortNumber,
 243 +       int     NewPromMode);
 244 +
 245  #ifndef SK_SLIM
 246  extern int     SkAddrSwap(
 247         SK_AC   *pAC,
 248 diff -ruN linux/drivers/net/sk98lin/h/skcsum.h linux-new/drivers/net/sk98lin/h/skcsum.h
 249 --- linux/drivers/net/sk98lin/h/skcsum.h        2006-09-20 05:42:06.000000000 +0200
 250 +++ linux-new/drivers/net/sk98lin/h/skcsum.h    2006-07-28 14:13:54.000000000 +0200
 251 @@ -2,14 +2,15 @@
 252   *
 253   * Name:       skcsum.h
 254   * Project:    GEnesis - SysKonnect SK-NET Gigabit Ethernet (SK-98xx)
 255 - * Version:    $Revision$
 256 - * Date:       $Date$
 257 + * Version:    $Revision$
 258 + * Date:       $Date$
 259   * Purpose:    Store/verify Internet checksum in send/receive packets.
 260   *
 261   ******************************************************************************/
 262
 263  /******************************************************************************
 264   *
 265 + *     LICENSE:
 266   *     (C)Copyright 1998-2001 SysKonnect GmbH.
 267   *
 268   *     This program is free software; you can redistribute it and/or modify
 269 @@ -18,6 +19,7 @@
 270   *     (at your option) any later version.
 271   *
 272   *     The information in this file is provided "AS IS" without warranty.
 273 + *     /LICENSE
 274   *
 275   ******************************************************************************/
 276
 277 @@ -157,9 +159,7 @@
 278  typedef struct s_Csum {
 279         /* Enabled receive SK_PROTO_XXX bit flags. */
 280         unsigned ReceiveFlags[SK_MAX_NETS];
 281 -#ifdef TX_CSUM
 282         unsigned TransmitFlags[SK_MAX_NETS];
 283 -#endif /* TX_CSUM */
 284
 285         /* The protocol statistics structure; one per supported protocol. */
 286         SKCS_PROTO_STATS ProtoStats[SK_MAX_NETS][SKCS_NUM_PROTOCOLS];
 287 @@ -203,6 +203,12 @@
 288         unsigned        Checksum2,
 289         int                     NetNumber);
 290
 291 +extern void SkCsGetSendInfo(
 292 +       SK_AC                           *pAc,
 293 +       void                            *pIpHeader,
 294 +       SKCS_PACKET_INFO        *pPacketInfo,
 295 +       int                                     NetNumber);
 296 +
 297  extern void SkCsSetReceiveFlags(
 298         SK_AC           *pAc,
 299         unsigned        ReceiveFlags,
 300 diff -ruN linux/drivers/net/sk98lin/h/skdebug.h linux-new/drivers/net/sk98lin/h/skdebug.h
 301 --- linux/drivers/net/sk98lin/h/skdebug.h       2006-09-20 05:42:06.000000000 +0200
 302 +++ linux-new/drivers/net/sk98lin/h/skdebug.h   2006-07-28 14:13:54.000000000 +0200
 303 @@ -2,23 +2,24 @@
 304   *
 305   * Name:       skdebug.h
 306   * Project:    Gigabit Ethernet Adapters, Common Modules
 307 - * Version:    $Revision$
 308 - * Date:       $Date$
 309 + * Version:    $Revision$
 310 + * Date:       $Date$
 311   * Purpose:    SK specific DEBUG support
 312   *
 313   ******************************************************************************/
 314
 315  /******************************************************************************
 316   *
 317 + *     LICENSE:
 318   *     (C)Copyright 1998-2002 SysKonnect.
 319 - *     (C)Copyright 2002-2003 Marvell.
 320 + *     (C)Copyright 2002-2005 Marvell.
 321   *
 322   *     This program is free software; you can redistribute it and/or modify
 323   *     it under the terms of the GNU General Public License as published by
 324   *     the Free Software Foundation; either version 2 of the License, or
 325   *     (at your option) any later version.
 326 - *
 327   *     The information in this file is provided "AS IS" without warranty.
 328 + *     /LICENSE
 329   *
 330   ******************************************************************************/
 331
 332 @@ -28,9 +29,9 @@
 333  #ifdef DEBUG
 334  #ifndef SK_DBG_MSG
 335  #define SK_DBG_MSG(pAC,comp,cat,arg) \
 336 -               if ( ((comp) & SK_DBG_CHKMOD(pAC)) &&   \
 337 -                     ((cat) & SK_DBG_CHKCAT(pAC)) ) {  \
 338 -                       SK_DBG_PRINTF arg ;             \
 339 +               if ( ((comp) & SK_DBG_CHKMOD(pAC)) &&   \
 340 +                     ((cat) & SK_DBG_CHKCAT(pAC)) ) {  \
 341 +                       SK_DBG_PRINTF arg;              \
 342                 }
 343  #endif
 344  #else
 345 @@ -58,6 +59,13 @@
 346  #define SK_DBGMOD_ADDR 0x00000080L     /* ADDR module */
 347  #define SK_DBGMOD_PECP 0x00000100L     /* PECP module */
 348  #define SK_DBGMOD_POWM 0x00000200L     /* Power Management module */
 349 +#ifdef SK_ASF
 350 +#define SK_DBGMOD_ASF  0x00000400L     /* ASF module */
 351 +#endif
 352 +#ifdef SK_LBFO
 353 +#define SK_DBGMOD_LACP 0x00000800L     /* link aggregation control protocol */
 354 +#define SK_DBGMOD_FD   0x00001000L     /* frame distributor (link aggregation) */
 355 +#endif /* SK_LBFO */
 356
 357  /* Debug events */
 358
 359 diff -ruN linux/drivers/net/sk98lin/h/skdrv1st.h linux-new/drivers/net/sk98lin/h/skdrv1st.h
 360 --- linux/drivers/net/sk98lin/h/skdrv1st.h      2006-09-20 05:42:06.000000000 +0200
 361 +++ linux-new/drivers/net/sk98lin/h/skdrv1st.h  2006-07-28 14:13:56.000000000 +0200
 362 @@ -2,8 +2,8 @@
 363   *
 364   * Name:       skdrv1st.h
 365   * Project:    GEnesis, PCI Gigabit Ethernet Adapter
 366 - * Version:    $Revision$
 367 - * Date:       $Date$
 368 + * Version:    $Revision$
 369 + * Date:       $Date$
 370   * Purpose:    First header file for driver and all other modules
 371   *
 372   ******************************************************************************/
 373 @@ -11,7 +11,7 @@
 374  /******************************************************************************
 375   *
 376   *     (C)Copyright 1998-2002 SysKonnect GmbH.
 377 - *     (C)Copyright 2002-2003 Marvell.
 378 + *     (C)Copyright 2002-2005 Marvell.
 379   *
 380   *     This program is free software; you can redistribute it and/or modify
 381   *     it under the terms of the GNU General Public License as published by
 382 @@ -22,23 +22,12 @@
 383   *
 384   ******************************************************************************/
 385
 386 -/******************************************************************************
 387 - *
 388 - * Description:
 389 - *
 390 - * This is the first include file of the driver, which includes all
 391 - * neccessary system header files and some of the GEnesis header files.
 392 - * It also defines some basic items.
 393 - *
 394 - * Include File Hierarchy:
 395 - *
 396 - *     see skge.c
 397 - *
 398 - ******************************************************************************/
 399 -
 400  #ifndef __INC_SKDRV1ST_H
 401  #define __INC_SKDRV1ST_H
 402
 403 +/* Check kernel version */
 404 +#include <linux/version.h>
 405 +
 406  typedef struct s_AC    SK_AC;
 407
 408  /* Set card versions */
 409 @@ -55,6 +44,9 @@
 410
 411  #define SK_ADDR_EQUAL(a1,a2)           (!memcmp(a1,a2,6))
 412
 413 +#define SK_STRNCMP(s1,s2,len)          strncmp(s1,s2,len)
 414 +#define SK_STRCPY(dest,src)            strcpy(dest,src)
 415 +
 416  #include <linux/types.h>
 417  #include <linux/kernel.h>
 418  #include <linux/string.h>
 419 @@ -63,10 +55,9 @@
 420  #include <linux/slab.h>
 421  #include <linux/interrupt.h>
 422  #include <linux/pci.h>
 423 -#include <linux/bitops.h>
 424  #include <asm/byteorder.h>
 425 +#include <asm/bitops.h>
 426  #include <asm/io.h>
 427 -#include <asm/irq.h>
 428  #include <linux/netdevice.h>
 429  #include <linux/etherdevice.h>
 430  #include <linux/skbuff.h>
 431 @@ -76,11 +67,7 @@
 432  #include <net/checksum.h>
 433
 434  #define SK_CS_CALCULATE_CHECKSUM
 435 -#ifndef CONFIG_X86_64
 436 -#define SkCsCalculateChecksum(p,l)     ((~ip_compute_csum(p, l)) & 0xffff)
 437 -#else
 438 -#define SkCsCalculateChecksum(p,l)     ((~ip_fast_csum(p, l)) & 0xffff)
 439 -#endif
 440 +#define SkCsCalculateChecksum(p,l)     (~csum_fold(csum_partial(p, l, 0)))
 441
 442  #include       "h/sktypes.h"
 443  #include       "h/skerror.h"
 444 @@ -88,10 +75,15 @@
 445  #include       "h/lm80.h"
 446  #include       "h/xmac_ii.h"
 447
 448 +#ifndef SK_BMU_RX_WM_PEX
 449 +#define SK_BMU_RX_WM_PEX 0x80
 450 +#endif
 451 +
 452  #ifdef __LITTLE_ENDIAN
 453  #define SK_LITTLE_ENDIAN
 454  #else
 455  #define SK_BIG_ENDIAN
 456 +#define SK_USE_REV_DESC
 457  #endif
 458
 459  #define SK_NET_DEVICE  net_device
 460 @@ -107,7 +99,7 @@
 461  #define SK_MAX_MACS            2
 462  #define SK_MAX_NETS            2
 463
 464 -#define SK_IOC                 char __iomem *
 465 +#define SK_IOC                 char*
 466
 467  typedef struct s_DrvRlmtMbuf SK_MBUF;
 468
 469 @@ -186,3 +178,8 @@
 470
 471  #endif
 472
 473 +/*******************************************************************************
 474 + *
 475 + * End of file
 476 + *
 477 + ******************************************************************************/
 478 diff -ruN linux/drivers/net/sk98lin/h/skdrv2nd.h linux-new/drivers/net/sk98lin/h/skdrv2nd.h
 479 --- linux/drivers/net/sk98lin/h/skdrv2nd.h      2006-09-20 05:42:06.000000000 +0200
 480 +++ linux-new/drivers/net/sk98lin/h/skdrv2nd.h  2006-07-28 14:13:56.000000000 +0200
 481 @@ -1,17 +1,17 @@
 482  /******************************************************************************
 483   *
 484 - * Name:       skdrv2nd.h
 485 - * Project:    GEnesis, PCI Gigabit Ethernet Adapter
 486 - * Version:    $Revision$
 487 - * Date:       $Date$
 488 - * Purpose:    Second header file for driver and all other modules
 489 + * Name:        skdrv2nd.h
 490 + * Project:     GEnesis, PCI Gigabit Ethernet Adapter
 491 + * Version:     $Revision$
 492 + * Date:        $Date$
 493 + * Purpose:     Second header file for driver and all other modules
 494   *
 495   ******************************************************************************/
 496
 497  /******************************************************************************
 498   *
 499   *     (C)Copyright 1998-2002 SysKonnect GmbH.
 500 - *     (C)Copyright 2002-2003 Marvell.
 501 + *     (C)Copyright 2002-2005 Marvell.
 502   *
 503   *     This program is free software; you can redistribute it and/or modify
 504   *     it under the terms of the GNU General Public License as published by
 505 @@ -42,10 +42,11 @@
 506  #include "h/skqueue.h"
 507  #include "h/skgehwt.h"
 508  #include "h/sktimer.h"
 509 -#include "h/ski2c.h"
 510 +#include "h/sktwsi.h"
 511  #include "h/skgepnmi.h"
 512  #include "h/skvpd.h"
 513  #include "h/skgehw.h"
 514 +#include "h/sky2le.h"
 515  #include "h/skgeinit.h"
 516  #include "h/skaddr.h"
 517  #include "h/skgesirq.h"
 518 @@ -53,103 +54,191 @@
 519  #include "h/skrlmt.h"
 520  #include "h/skgedrv.h"
 521
 522 +/* Defines for the poll cotroller */
 523 +#define SK_NETDUMP_POLL
 524
 525 -extern SK_MBUF         *SkDrvAllocRlmtMbuf(SK_AC*, SK_IOC, unsigned);
 526 -extern void            SkDrvFreeRlmtMbuf(SK_AC*, SK_IOC, SK_MBUF*);
 527 -extern SK_U64          SkOsGetTime(SK_AC*);
 528 -extern int             SkPciReadCfgDWord(SK_AC*, int, SK_U32*);
 529 -extern int             SkPciReadCfgWord(SK_AC*, int, SK_U16*);
 530 -extern int             SkPciReadCfgByte(SK_AC*, int, SK_U8*);
 531 -extern int             SkPciWriteCfgWord(SK_AC*, int, SK_U16);
 532 -extern int             SkPciWriteCfgByte(SK_AC*, int, SK_U8);
 533 -extern int             SkDrvEvent(SK_AC*, SK_IOC IoC, SK_U32, SK_EVPARA);
 534 -
 535 -#ifdef SK_DIAG_SUPPORT
 536 -extern int             SkDrvEnterDiagMode(SK_AC *pAc);
 537 -extern int             SkDrvLeaveDiagMode(SK_AC *pAc);
 538 +#ifdef SK_NETDUMP_POLL
 539 +#ifdef HAVE_POLL_CONTROLLER
 540 +#define SK_POLL_CONTROLLER
 541 +#define CONFIG_SK98LIN_NAPI
 542 +#elif CONFIG_NET_POLL_CONTROLLER
 543 +#define SK_POLL_CONTROLLER
 544 +#define CONFIG_SK98LIN_NAPI
 545  #endif
 546 +#endif
 547 +
 548 +
 549 +/******************************************************************************
 550 + *
 551 + * Generic driver defines
 552 + *
 553 + ******************************************************************************/
 554 +
 555 +#define USE_TIST_FOR_RESET     /* Use timestamp for reset */
 556 +#define Y2_RECOVERY            /* use specific recovery yukon2 functions */
 557 +#define Y2_LE_CHECK            /* activate check for LE order */
 558 +#define Y2_SYNC_CHECK          /* activate check for receiver in sync */
 559 +#define SK_YUKON2              /* Enable Yukon2 dual net support */
 560 +#define USE_SK_TX_CHECKSUM     /* use the tx hw checksum driver functionality */
 561 +#define USE_SK_RX_CHECKSUM     /* use the rx hw checksum driver functionality */
 562 +#define USE_SK_TSO_FEATURE     /* use TCP segmentation offload if possible */
 563 +#define SK_COPY_THRESHOLD 50   /* threshold for copying small RX frames;
 564 +                                * 0 avoids copying, 9001 copies all */
 565 +#define SK_MAX_CARD_PARAM 16   /* number of adapters that can be configured via
 566 +                                * command line params */
 567 +//#define USE_TX_COMPLETE      /* use of a transmit complete interrupt */
 568 +#define Y2_RX_CHECK            /* RX Check timestamp */
 569 +
 570 +/*
 571 + * use those defines for a compile-in version of the driver instead
 572 + * of command line parameters
 573 + */
 574 +// #define LINK_SPEED_A        {"Auto",}
 575 +// #define LINK_SPEED_B        {"Auto",}
 576 +// #define AUTO_NEG_A  {"Sense",}
 577 +// #define AUTO_NEG_B  {"Sense"}
 578 +// #define DUP_CAP_A   {"Both",}
 579 +// #define DUP_CAP_B   {"Both",}
 580 +// #define FLOW_CTRL_A {"SymOrRem",}
 581 +// #define FLOW_CTRL_B {"SymOrRem",}
 582 +// #define ROLE_A      {"Auto",}
 583 +// #define ROLE_B      {"Auto",}
 584 +// #define PREF_PORT   {"A",}
 585 +// #define CON_TYPE    {"Auto",}
 586 +// #define RLMT_MODE   {"CheckLinkState",}
 587 +
 588 +#ifdef Y2_RECOVERY
 589 +#define CHECK_TRANSMIT_TIMEOUT
 590 +#define Y2_RESYNC_WATERMARK     1000000L
 591 +#endif
 592 +
 593 +
 594 +/******************************************************************************
 595 + *
 596 + * Generic ISR defines
 597 + *
 598 + ******************************************************************************/
 599 +
 600 +#define SkIsrRetVar     irqreturn_t
 601 +#define SkIsrRetNone    IRQ_NONE
 602 +#define SkIsrRetHandled IRQ_HANDLED
 603 +
 604 +#define DEV_KFREE_SKB(skb) dev_kfree_skb(skb)
 605 +#define DEV_KFREE_SKB_IRQ(skb) dev_kfree_skb_irq(skb)
 606 +#define DEV_KFREE_SKB_ANY(skb) dev_kfree_skb_any(skb)
 607 +
 608 +/******************************************************************************
 609 + *
 610 + * Global function prototypes
 611 + *
 612 + ******************************************************************************/
 613 +
 614 +extern SK_MBUF *SkDrvAllocRlmtMbuf(SK_AC*, SK_IOC, unsigned);
 615 +extern void SkDrvFreeRlmtMbuf(SK_AC*, SK_IOC, SK_MBUF*);
 616 +extern SK_U64 SkOsGetTime(SK_AC*);
 617 +extern int SkPciReadCfgDWord(SK_AC*, int, SK_U32*);
 618 +extern int SkPciReadCfgWord(SK_AC*, int, SK_U16*);
 619 +extern int SkPciReadCfgByte(SK_AC*, int, SK_U8*);
 620 +extern int SkPciWriteCfgDWord(SK_AC*, int, SK_U32);
 621 +extern int SkPciWriteCfgWord(SK_AC*, int, SK_U16);
 622 +extern int SkPciWriteCfgByte(SK_AC*, int, SK_U8);
 623 +extern int SkDrvEvent(SK_AC*, SK_IOC IoC, SK_U32, SK_EVPARA);
 624 +extern int SkDrvEnterDiagMode(SK_AC *pAc);
 625 +extern int SkDrvLeaveDiagMode(SK_AC *pAc);
 626 +
 627 +/******************************************************************************
 628 + *
 629 + * Linux specific RLMT buffer structure (SK_MBUF typedef in skdrv1st)!
 630 + *
 631 + ******************************************************************************/
 632
 633  struct s_DrvRlmtMbuf {
 634 -       SK_MBUF         *pNext;         /* Pointer to next RLMT Mbuf. */
 635 -       SK_U8           *pData;         /* Data buffer (virtually contig.). */
 636 -       unsigned        Size;           /* Data buffer size. */
 637 -       unsigned        Length;         /* Length of packet (<= Size). */
 638 -       SK_U32          PortIdx;        /* Receiving/transmitting port. */
 639 +       SK_MBUF         *pNext;    /* Pointer to next RLMT Mbuf.       */
 640 +       SK_U8           *pData;    /* Data buffer (virtually contig.). */
 641 +       unsigned         Size;     /* Data buffer size.                */
 642 +       unsigned         Length;   /* Length of packet (<= Size).      */
 643 +       SK_U32           PortIdx;  /* Receiving/transmitting port.     */
 644  #ifdef SK_RLMT_MBUF_PRIVATE
 645 -       SK_RLMT_MBUF    Rlmt;           /* Private part for RLMT. */
 646 -#endif  /* SK_RLMT_MBUF_PRIVATE */
 647 -       struct sk_buff  *pOs;           /* Pointer to message block */
 648 +       SK_RLMT_MBUF     Rlmt;     /* Private part for RLMT.           */
 649 +#endif
 650 +       struct sk_buff  *pOs;      /* Pointer to message block         */
 651  };
 652
 653 +/******************************************************************************
 654 + *
 655 + * Linux specific TIME defines
 656 + *
 657 + ******************************************************************************/
 658
 659 -/*
 660 - * Time macros
 661 - */
 662  #if SK_TICKS_PER_SEC == 100
 663  #define SK_PNMI_HUNDREDS_SEC(t)        (t)
 664  #else
 665 -#define SK_PNMI_HUNDREDS_SEC(t)        ((((unsigned long)t) * 100) / \
 666 -                                                                               (SK_TICKS_PER_SEC))
 667 +#define SK_PNMI_HUNDREDS_SEC(t) ((((unsigned long)t)*100)/(SK_TICKS_PER_SEC))
 668  #endif
 669
 670 -/*
 671 - * New SkOsGetTime
 672 - */
 673  #define SkOsGetTimeCurrent(pAC, pUsec) {\
 674 +       static struct timeval prev_t; \
 675         struct timeval t;\
 676         do_gettimeofday(&t);\
 677 -       *pUsec = ((((t.tv_sec) * 1000000L)+t.tv_usec)/10000);\
 678 +       if (prev_t.tv_sec == t.tv_sec) { \
 679 +               if (prev_t.tv_usec > t.tv_usec) { \
 680 +                       t.tv_usec = prev_t.tv_usec; \
 681 +               } else { \
 682 +                       prev_t.tv_usec = t.tv_usec; \
 683 +               } \
 684 +       } else { \
 685 +               prev_t = t; \
 686 +       } \
 687 +       *pUsec = ((t.tv_sec*100L)+(t.tv_usec/10000));\
 688  }
 689
 690 +/******************************************************************************
 691 + *
 692 + * Linux specific IOCTL defines and typedefs
 693 + *
 694 + ******************************************************************************/
 695
 696 -/*
 697 - * ioctl definitions
 698 - */
 699 -#define                SK_IOCTL_BASE           (SIOCDEVPRIVATE)
 700 -#define                SK_IOCTL_GETMIB         (SK_IOCTL_BASE + 0)
 701 -#define                SK_IOCTL_SETMIB         (SK_IOCTL_BASE + 1)
 702 -#define                SK_IOCTL_PRESETMIB      (SK_IOCTL_BASE + 2)
 703 -#define                SK_IOCTL_GEN            (SK_IOCTL_BASE + 3)
 704 -#define                SK_IOCTL_DIAG           (SK_IOCTL_BASE + 4)
 705 -
 706 -typedef struct s_IOCTL SK_GE_IOCTL;
 707 +#define        SK_IOCTL_BASE       (SIOCDEVPRIVATE)
 708 +#define        SK_IOCTL_GETMIB     (SK_IOCTL_BASE + 0)
 709 +#define        SK_IOCTL_SETMIB     (SK_IOCTL_BASE + 1)
 710 +#define        SK_IOCTL_PRESETMIB  (SK_IOCTL_BASE + 2)
 711 +#define        SK_IOCTL_GEN        (SK_IOCTL_BASE + 3)
 712 +#define        SK_IOCTL_DIAG       (SK_IOCTL_BASE + 4)
 713
 714 +typedef struct s_IOCTL SK_GE_IOCTL;
 715  struct s_IOCTL {
 716         char __user *   pData;
 717         unsigned int    Len;
 718  };
 719
 720 +/******************************************************************************
 721 + *
 722 + * Generic sizes and length definitions
 723 + *
 724 + ******************************************************************************/
 725
 726 -/*
 727 - * define sizes of descriptor rings in bytes
 728 - */
 729 -
 730 -#define                TX_RING_SIZE    (8*1024)
 731 -#define                RX_RING_SIZE    (24*1024)
 732 -
 733 -/*
 734 - * Buffer size for ethernet packets
 735 - */
 736 -#define        ETH_BUF_SIZE    1540
 737 -#define        ETH_MAX_MTU     1514
 738 -#define ETH_MIN_MTU    60
 739 -#define ETH_MULTICAST_BIT      0x01
 740 -#define SK_JUMBO_MTU   9000
 741 -
 742 -/*
 743 - * transmit priority selects the queue: LOW=asynchron, HIGH=synchron
 744 - */
 745 -#define TX_PRIO_LOW    0
 746 -#define TX_PRIO_HIGH   1
 747 +#define TX_RING_SIZE  (24*1024)                        /* GEnesis/Yukon */
 748 +#define RX_RING_SIZE  (24*1024)                        /* GEnesis/Yukon */
 749 +#define RX_MAX_NBR_BUFFERS   128               /* Yukon-EC/-II */
 750 +#define TX_MAX_NBR_BUFFERS   128               /* Yukon-EC/-II */
 751 +#define MAXIMUM_LOW_ADDRESS 0xFFFFFFFF         /* Max. low address */
 752 +
 753 +#define        ETH_BUF_SIZE        1560                /* multiples of 8 bytes */
 754 +#define        ETH_MAX_MTU         1514
 755 +#define ETH_MIN_MTU         60
 756 +#define ETH_MULTICAST_BIT   0x01
 757 +#define SK_JUMBO_MTU        9000
 758 +
 759 +#define TX_PRIO_LOW    0 /* asynchronous queue */
 760 +#define TX_PRIO_HIGH   1 /* synchronous queue */
 761 +#define DESCR_ALIGN   64 /* alignment of Rx/Tx descriptors */
 762
 763 -/*
 764 - * alignment of rx/tx descriptors
 765 - */
 766 -#define DESCR_ALIGN    64
 767 +/******************************************************************************
 768 + *
 769 + * PNMI related definitions
 770 + *
 771 + ******************************************************************************/
 772
 773 -/*
 774 - * definitions for pnmi. TODO
 775 - */
 776  #define SK_DRIVER_RESET(pAC, IoC)      0
 777  #define SK_DRIVER_SENDEVENT(pAC, IoC)  0
 778  #define SK_DRIVER_SELFTEST(pAC, IoC)   0
 779 @@ -158,20 +247,16 @@
 780  #define SK_DRIVER_SET_MTU(pAc,IoC,i,v) 0
 781  #define SK_DRIVER_PRESET_MTU(pAc,IoC,i,v)      0
 782
 783 -/*
 784 -** Interim definition of SK_DRV_TIMER placed in this file until
 785 -** common modules have boon finallized
 786 -*/
 787 -#define SK_DRV_TIMER                   11
 788 -#define        SK_DRV_MODERATION_TIMER         1
 789 -#define SK_DRV_MODERATION_TIMER_LENGTH  1000000  /* 1 second */
 790 -#define SK_DRV_RX_CLEANUP_TIMER                2
 791 -#define SK_DRV_RX_CLEANUP_TIMER_LENGTH 1000000  /* 100 millisecs */
 792
 793 -/*
 794 -** Definitions regarding transmitting frames
 795 -** any calculating any checksum.
 796 -*/
 797 +/******************************************************************************
 798 + *
 799 + * Various offsets and sizes
 800 + *
 801 + ******************************************************************************/
 802 +
 803 +#define        SK_DRV_MODERATION_TIMER         1   /* id */
 804 +#define SK_DRV_MODERATION_TIMER_LENGTH  1   /* 1 second */
 805 +
 806  #define C_LEN_ETHERMAC_HEADER_DEST_ADDR 6
 807  #define C_LEN_ETHERMAC_HEADER_SRC_ADDR  6
 808  #define C_LEN_ETHERMAC_HEADER_LENTYPE   2
 809 @@ -197,112 +282,445 @@
 810  #define C_PROTO_ID_UDP                  17       /* refer to RFC 790 or Stevens'   */
 811  #define C_PROTO_ID_TCP                  6        /* TCP/IP illustrated for details */
 812
 813 -/* TX and RX descriptors *****************************************************/
 814 +/******************************************************************************
 815 + *
 816 + * Tx and Rx descriptor definitions
 817 + *
 818 + ******************************************************************************/
 819
 820  typedef struct s_RxD RXD; /* the receive descriptor */
 821 -
 822  struct s_RxD {
 823 -       volatile SK_U32 RBControl;      /* Receive Buffer Control */
 824 -       SK_U32          VNextRxd;       /* Next receive descriptor,low dword */
 825 -       SK_U32          VDataLow;       /* Receive buffer Addr, low dword */
 826 -       SK_U32          VDataHigh;      /* Receive buffer Addr, high dword */
 827 -       SK_U32          FrameStat;      /* Receive Frame Status word */
 828 -       SK_U32          TimeStamp;      /* Time stamp from XMAC */
 829 -       SK_U32          TcpSums;        /* TCP Sum 2 / TCP Sum 1 */
 830 -       SK_U32          TcpSumStarts;   /* TCP Sum Start 2 / TCP Sum Start 1 */
 831 -       RXD             *pNextRxd;      /* Pointer to next Rxd */
 832 -       struct sk_buff  *pMBuf;         /* Pointer to Linux' socket buffer */
 833 +       volatile SK_U32  RBControl;     /* Receive Buffer Control            */
 834 +       SK_U32           VNextRxd;      /* Next receive descriptor,low dword */
 835 +       SK_U32           VDataLow;      /* Receive buffer Addr, low dword    */
 836 +       SK_U32           VDataHigh;     /* Receive buffer Addr, high dword   */
 837 +       SK_U32           FrameStat;     /* Receive Frame Status word         */
 838 +       SK_U32           TimeStamp;     /* Time stamp from XMAC              */
 839 +       SK_U32           TcpSums;       /* TCP Sum 2 / TCP Sum 1             */
 840 +       SK_U32           TcpSumStarts;  /* TCP Sum Start 2 / TCP Sum Start 1 */
 841 +       RXD             *pNextRxd;      /* Pointer to next Rxd               */
 842 +       struct sk_buff  *pMBuf;         /* Pointer to Linux' socket buffer   */
 843  };
 844
 845  typedef struct s_TxD TXD; /* the transmit descriptor */
 846 -
 847  struct s_TxD {
 848 -       volatile SK_U32 TBControl;      /* Transmit Buffer Control */
 849 -       SK_U32          VNextTxd;       /* Next transmit descriptor,low dword */
 850 -       SK_U32          VDataLow;       /* Transmit Buffer Addr, low dword */
 851 -       SK_U32          VDataHigh;      /* Transmit Buffer Addr, high dword */
 852 -       SK_U32          FrameStat;      /* Transmit Frame Status Word */
 853 -       SK_U32          TcpSumOfs;      /* Reserved / TCP Sum Offset */
 854 -       SK_U16          TcpSumSt;       /* TCP Sum Start */
 855 -       SK_U16          TcpSumWr;       /* TCP Sum Write */
 856 -       SK_U32          TcpReserved;    /* not used */
 857 -       TXD             *pNextTxd;      /* Pointer to next Txd */
 858 -       struct sk_buff  *pMBuf;         /* Pointer to Linux' socket buffer */
 859 +       volatile SK_U32  TBControl;     /* Transmit Buffer Control            */
 860 +       SK_U32           VNextTxd;      /* Next transmit descriptor,low dword */
 861 +       SK_U32           VDataLow;      /* Transmit Buffer Addr, low dword    */
 862 +       SK_U32           VDataHigh;     /* Transmit Buffer Addr, high dword   */
 863 +       SK_U32           FrameStat;     /* Transmit Frame Status Word         */
 864 +       SK_U32           TcpSumOfs;     /* Reserved / TCP Sum Offset          */
 865 +       SK_U16           TcpSumSt;      /* TCP Sum Start                      */
 866 +       SK_U16           TcpSumWr;      /* TCP Sum Write                      */
 867 +       SK_U32           TcpReserved;   /* not used                           */
 868 +       TXD             *pNextTxd;      /* Pointer to next Txd                */
 869 +       struct sk_buff  *pMBuf;         /* Pointer to Linux' socket buffer    */
 870 +};
 871 +
 872 +/******************************************************************************
 873 + *
 874 + * Generic Yukon-II defines
 875 + *
 876 + ******************************************************************************/
 877 +
 878 +#define LE_SIZE   sizeof(SK_HWLE)
 879 +#define MAX_NUM_FRAGS   (MAX_SKB_FRAGS + 1)
 880 +#define MIN_LEN_OF_LE_TAB   128
 881 +#define MAX_LEN_OF_LE_TAB   4096
 882 +#define MAX_UNUSED_RX_LE_WORKING   8
 883 +#ifdef MAX_FRAG_OVERHEAD
 884 +#undef MAX_FRAG_OVERHEAD
 885 +#define MAX_FRAG_OVERHEAD   4
 886 +#endif
 887 +// as we have a maximum of 16 physical fragments,
 888 +// maximum 1 ADDR64 per physical fragment
 889 +// maximum 4 LEs for VLAN, Csum, LargeSend, Packet
 890 +#define MIN_LE_FREE_REQUIRED   ((16*2) + 4)
 891 +#define IS_GMAC(pAc)   (!pAc->GIni.GIGenesis)
 892 +#ifdef USE_SYNC_TX_QUEUE
 893 +#define TXS_MAX_LE   256
 894 +#else /* !USE_SYNC_TX_QUEUE */
 895 +#define TXS_MAX_LE   0
 896 +#endif
 897 +
 898 +#define ETHER_MAC_HDR_LEN   (6+6+2) // MAC SRC ADDR, MAC DST ADDR, TYPE
 899 +#define IP_HDR_LEN   20
 900 +#define TCP_CSUM_OFFS   0x10
 901 +#define UDP_CSUM_OFFS   0x06
 902 +#define TXA_MAX_LE   256
 903 +#define RX_MAX_LE   256
 904 +#define ST_MAX_LE   (SK_MAX_MACS)*((3*RX_MAX_LE)+(TXA_MAX_LE)+(TXS_MAX_LE))
 905 +
 906 +#if (defined (Y2_RECOVERY) || defined (Y2_LE_CHECK))
 907 +/* event for recovery from tx hang or rx out of sync */
 908 +#define SK_DRV_RECOVER                  17
 909 +#endif
 910 +/******************************************************************************
 911 + *
 912 + * Structures specific for Yukon-II
 913 + *
 914 + ******************************************************************************/
 915 +
 916 +typedef        struct s_frag SK_FRAG;
 917 +struct s_frag {
 918 +       SK_FRAG       *pNext;
 919 +       char          *pVirt;
 920 +       SK_U64         pPhys;
 921 +       unsigned int   FragLen;
 922  };
 923
 924 -/* Used interrupt bits in the interrupts source register *********************/
 925 +typedef        struct s_packet SK_PACKET;
 926 +struct s_packet {
 927 +       /* Common infos: */
 928 +       SK_PACKET       *pNext;         /* pointer for packet queues          */
 929 +       unsigned int     PacketLen;     /* length of packet                   */
 930 +       unsigned int     NumFrags;      /* nbr of fragments (for Rx always 1) */
 931 +       SK_FRAG         *pFrag;         /* fragment list                      */
 932 +       SK_FRAG          FragArray[MAX_NUM_FRAGS]; /* TX fragment array       */
 933 +       unsigned int     NextLE;        /* next LE to use for the next packet */
 934 +
 935 +       /* Private infos: */
 936 +       struct sk_buff  *pMBuf;         /* Pointer to Linux' socket buffer    */
 937 +};
 938 +
 939 +typedef        struct s_queue SK_PKT_QUEUE;
 940 +struct s_queue {
 941 +       SK_PACKET       *pHead;
 942 +       SK_PACKET       *pTail;
 943 +       spinlock_t       QueueLock;     /* serialize packet accesses          */
 944 +};
 945 +
 946 +/*******************************************************************************
 947 + *
 948 + * Macros specific for Yukon-II queues
 949 + *
 950 + ******************************************************************************/
 951 +
 952 +#define IS_Q_EMPTY(pQueue)  ((pQueue)->pHead != NULL) ? SK_FALSE : SK_TRUE
 953 +#define IS_Q_LOCKED(pQueue) spin_is_locked(&((pQueue)->QueueLock))
 954 +
 955 +#define PLAIN_POP_FIRST_PKT_FROM_QUEUE(pQueue, pPacket)        {       \
 956 +        if ((pQueue)->pHead != NULL) {                         \
 957 +               (pPacket)       = (pQueue)->pHead;              \
 958 +               (pQueue)->pHead = (pPacket)->pNext;             \
 959 +               if ((pQueue)->pHead == NULL) {                  \
 960 +                       (pQueue)->pTail = NULL;                 \
 961 +               }                                               \
 962 +               (pPacket)->pNext = NULL;                        \
 963 +       } else {                                                \
 964 +               (pPacket) = NULL;                               \
 965 +       }                                                       \
 966 +}
 967 +
 968 +#define PLAIN_PUSH_PKT_AS_FIRST_IN_QUEUE(pQueue, pPacket) {    \
 969 +       if ((pQueue)->pHead != NULL) {                          \
 970 +               (pPacket)->pNext = (pQueue)->pHead;             \
 971 +       } else {                                                \
 972 +               (pPacket)->pNext = NULL;                        \
 973 +               (pQueue)->pTail  = (pPacket);                   \
 974 +       }                                                       \
 975 +       (pQueue)->pHead  = (pPacket);                           \
 976 +}
 977 +
 978 +#define PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(pQueue, pPacket) {     \
 979 +       (pPacket)->pNext = NULL;                                \
 980 +       if ((pQueue)->pTail != NULL) {                          \
 981 +               (pQueue)->pTail->pNext = (pPacket);             \
 982 +       } else {                                                \
 983 +               (pQueue)->pHead        = (pPacket);             \
 984 +       }                                                       \
 985 +       (pQueue)->pTail = (pPacket);                            \
 986 +}
 987 +
 988 +#define PLAIN_PUSH_MULTIPLE_PKT_AS_LAST_IN_QUEUE(pQueue,pPktGrpStart,pPktGrpEnd) { \
 989 +       if ((pPktGrpStart) != NULL) {                                   \
 990 +               if ((pQueue)->pTail != NULL) {                          \
 991 +                       (pQueue)->pTail->pNext = (pPktGrpStart);        \
 992 +               } else {                                                \
 993 +                       (pQueue)->pHead = (pPktGrpStart);               \
 994 +               }                                                       \
 995 +               (pQueue)->pTail = (pPktGrpEnd);                         \
 996 +       }                                                               \
 997 +}
 998 +
 999 +/* Required: 'Flags' */
1000 +#define POP_FIRST_PKT_FROM_QUEUE(pQueue, pPacket)      {       \
1001 +       spin_lock_irqsave(&((pQueue)->QueueLock), Flags);       \
1002 +       if ((pQueue)->pHead != NULL) {                          \
1003 +               (pPacket)       = (pQueue)->pHead;              \
1004 +               (pQueue)->pHead = (pPacket)->pNext;             \
1005 +               if ((pQueue)->pHead == NULL) {                  \
1006 +                       (pQueue)->pTail = NULL;                 \
1007 +               }                                               \
1008 +               (pPacket)->pNext = NULL;                        \
1009 +       } else {                                                \
1010 +               (pPacket) = NULL;                               \
1011 +       }                                                       \
1012 +       spin_unlock_irqrestore(&((pQueue)->QueueLock), Flags);  \
1013 +}
1014 +
1015 +/* Required: 'Flags' */
1016 +#define PUSH_PKT_AS_FIRST_IN_QUEUE(pQueue, pPacket)    {       \
1017 +       spin_lock_irqsave(&(pQueue)->QueueLock, Flags);         \
1018 +       if ((pQueue)->pHead != NULL) {                          \
1019 +               (pPacket)->pNext = (pQueue)->pHead;             \
1020 +       } else {                                                \
1021 +               (pPacket)->pNext = NULL;                        \
1022 +               (pQueue)->pTail  = (pPacket);                   \
1023 +       }                                                       \
1024 +       (pQueue)->pHead = (pPacket);                            \
1025 +       spin_unlock_irqrestore(&(pQueue)->QueueLock, Flags);    \
1026 +}
1027 +
1028 +/* Required: 'Flags' */
1029 +#define PUSH_PKT_AS_LAST_IN_QUEUE(pQueue, pPacket)     {       \
1030 +       (pPacket)->pNext = NULL;                                \
1031 +       spin_lock_irqsave(&(pQueue)->QueueLock, Flags);         \
1032 +       if ((pQueue)->pTail != NULL) {                          \
1033 +               (pQueue)->pTail->pNext = (pPacket);             \
1034 +       } else {                                                \
1035 +               (pQueue)->pHead = (pPacket);                    \
1036 +       }                                                       \
1037 +       (pQueue)->pTail = (pPacket);                            \
1038 +       spin_unlock_irqrestore(&(pQueue)->QueueLock, Flags);    \
1039 +}
1040 +
1041 +/* Required: 'Flags' */
1042 +#define PUSH_MULTIPLE_PKT_AS_LAST_IN_QUEUE(pQueue,pPktGrpStart,pPktGrpEnd) {   \
1043 +       if ((pPktGrpStart) != NULL) {                                   \
1044 +               spin_lock_irqsave(&(pQueue)->QueueLock, Flags);         \
1045 +               if ((pQueue)->pTail != NULL) {                          \
1046 +                       (pQueue)->pTail->pNext = (pPktGrpStart);        \
1047 +               } else {                                                \
1048 +                       (pQueue)->pHead = (pPktGrpStart);               \
1049 +               }                                                       \
1050 +               (pQueue)->pTail = (pPktGrpEnd);                         \
1051 +               spin_unlock_irqrestore(&(pQueue)->QueueLock, Flags);    \
1052 +       }                                                               \
1053 +}
1054 +
1055 +/*
1056 + *Check if the low address (32 bit) is near the 4G limit or over it.
1057 + * Set the high address to a wrong value.
1058 + * Doing so we force to write the ADDR64 LE.
1059 + */
1060 +#define CHECK_LOW_ADDRESS( _HighAddress, _LowAddress , _Length) {      \
1061 +       if ((~0-_LowAddress) <_Length) {                                \
1062 +               _HighAddress= MAXIMUM_LOW_ADDRESS;                      \
1063 +               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,                       \
1064 +                       ("High Address must be set for HW. LowAddr = %d  Length = %d\n",        \
1065 +                       _LowAddress, _Length));                         \
1066 +       }                                                               \
1067 +}
1068 +
1069 +/*******************************************************************************
1070 + *
1071 + * Macros specific for Yukon-II queues (tist)
1072 + *
1073 + ******************************************************************************/
1074 +
1075 +#ifdef USE_TIST_FOR_RESET
1076 +/* port is fully operational */
1077 +#define SK_PSTATE_NOT_WAITING_FOR_TIST                  0
1078 +/* port in reset until any tist LE */
1079 +#define SK_PSTATE_WAITING_FOR_ANY_TIST          BIT_0
1080 +/* port in reset until timer reaches pAC->MinTistLo */
1081 +#define SK_PSTATE_WAITING_FOR_SPECIFIC_TIST     BIT_1
1082 +#define SK_PSTATE_PORT_SHIFT    4
1083 +#define SK_PSTATE_PORT_MASK             ((1 << SK_PSTATE_PORT_SHIFT) - 1)
1084 +
1085 +/* use this + Port to build OP_MOD_TXINDEX_NO_PORT_A|B */
1086 +#define OP_MOD_TXINDEX 0x71
1087 +/* opcode for a TX_INDEX LE in which Port A has to be ignored */
1088 +#define OP_MOD_TXINDEX_NO_PORT_A 0x71
1089 +/* opcode for a TX_INDEX LE in which Port B has to be ignored */
1090 +#define OP_MOD_TXINDEX_NO_PORT_B 0x72
1091 +/* opcode for LE to be ignored because port is still in reset */
1092 +#define OP_MOD_LE 0x7F
1093 +
1094 +/* set tist wait mode Bit for port */
1095 +#define SK_SET_WAIT_BIT_FOR_PORT(pAC, Bit, Port)        \
1096 +       { \
1097 +               (pAC)->AdapterResetState |= ((Bit) << (SK_PSTATE_PORT_SHIFT * Port)); \
1098 +       }
1099 +
1100 +/* reset tist waiting for specified port */
1101 +#define SK_CLR_STATE_FOR_PORT(pAC, Port)        \
1102 +       { \
1103 +               (pAC)->AdapterResetState &= \
1104 +                       ~(SK_PSTATE_PORT_MASK << (SK_PSTATE_PORT_SHIFT * Port)); \
1105 +       }
1106 +
1107 +/* return SK_TRUE when port is in reset waiting for tist */
1108 +#define SK_PORT_WAITING_FOR_TIST(pAC, Port) \
1109 +       ((((pAC)->AdapterResetState >> (SK_PSTATE_PORT_SHIFT * Port)) & \
1110 +               SK_PSTATE_PORT_MASK) != SK_PSTATE_NOT_WAITING_FOR_TIST)
1111 +
1112 +/* return SK_TRUE when port is in reset waiting for any tist */
1113 +#define SK_PORT_WAITING_FOR_ANY_TIST(pAC, Port) \
1114 +       ((((pAC)->AdapterResetState >> (SK_PSTATE_PORT_SHIFT * Port)) & \
1115 +               SK_PSTATE_WAITING_FOR_ANY_TIST) == SK_PSTATE_WAITING_FOR_ANY_TIST)
1116 +
1117 +/* return SK_TRUE when port is in reset waiting for a specific tist */
1118 +#define SK_PORT_WAITING_FOR_SPECIFIC_TIST(pAC, Port) \
1119 +       ((((pAC)->AdapterResetState >> (SK_PSTATE_PORT_SHIFT * Port)) & \
1120 +               SK_PSTATE_WAITING_FOR_SPECIFIC_TIST) == \
1121 +               SK_PSTATE_WAITING_FOR_SPECIFIC_TIST)
1122 +
1123 +/* return whether adapter is expecting a tist LE */
1124 +#define SK_ADAPTER_WAITING_FOR_TIST(pAC)        ((pAC)->AdapterResetState != 0)
1125 +
1126 +/* enable timestamp timer and force creation of tist LEs */
1127 +#define Y2_ENABLE_TIST(IoC) \
1128 +       SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8) GMT_ST_START)
1129 +
1130 +/* disable timestamp timer and stop creation of tist LEs */
1131 +#define Y2_DISABLE_TIST(IoC) \
1132 +       SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8) GMT_ST_STOP)
1133 +
1134 +/* get current value of timestamp timer */
1135 +#define Y2_GET_TIST_LOW_VAL(IoC, pVal) \
1136 +       SK_IN32(IoC, GMAC_TI_ST_VAL, pVal)
1137
1138 -#define DRIVER_IRQS    ((IS_IRQ_SW)   | \
1139 -                       (IS_R1_F)      |(IS_R2_F)  | \
1140 -                       (IS_XS1_F)     |(IS_XA1_F) | \
1141 -                       (IS_XS2_F)     |(IS_XA2_F))
1142 -
1143 -#define SPECIAL_IRQS   ((IS_HW_ERR)   |(IS_I2C_READY)  | \
1144 -                       (IS_EXT_REG)   |(IS_TIMINT)     | \
1145 -                       (IS_PA_TO_RX1) |(IS_PA_TO_RX2)  | \
1146 -                       (IS_PA_TO_TX1) |(IS_PA_TO_TX2)  | \
1147 -                       (IS_MAC1)      |(IS_LNK_SYNC_M1)| \
1148 -                       (IS_MAC2)      |(IS_LNK_SYNC_M2)| \
1149 -                       (IS_R1_C)      |(IS_R2_C)       | \
1150 -                       (IS_XS1_C)     |(IS_XA1_C)      | \
1151 -                       (IS_XS2_C)     |(IS_XA2_C))
1152 -
1153 -#define IRQ_MASK       ((IS_IRQ_SW)   | \
1154 -                       (IS_R1_B)      |(IS_R1_F)     |(IS_R2_B) |(IS_R2_F) | \
1155 -                       (IS_XS1_B)     |(IS_XS1_F)    |(IS_XA1_B)|(IS_XA1_F)| \
1156 -                       (IS_XS2_B)     |(IS_XS2_F)    |(IS_XA2_B)|(IS_XA2_F)| \
1157 -                       (IS_HW_ERR)    |(IS_I2C_READY)| \
1158 -                       (IS_EXT_REG)   |(IS_TIMINT)   | \
1159 -                       (IS_PA_TO_RX1) |(IS_PA_TO_RX2)| \
1160 -                       (IS_PA_TO_TX1) |(IS_PA_TO_TX2)| \
1161 -                       (IS_MAC1)      |(IS_MAC2)     | \
1162 -                       (IS_R1_C)      |(IS_R2_C)     | \
1163 -                       (IS_XS1_C)     |(IS_XA1_C)    | \
1164 -                       (IS_XS2_C)     |(IS_XA2_C))
1165 +#endif
1166
1167 -#define IRQ_HWE_MASK   (IS_ERR_MSK) /* enable all HW irqs */
1168 +
1169 +/*******************************************************************************
1170 + *
1171 + * Used interrupt bits in the interrupts source register
1172 + *
1173 + ******************************************************************************/
1174 +
1175 +#define DRIVER_IRQS    ((IS_IRQ_SW) | \
1176 +                        (IS_R1_F)   | (IS_R2_F)  | \
1177 +                        (IS_XS1_F)  | (IS_XA1_F) | \
1178 +                        (IS_XS2_F)  | (IS_XA2_F))
1179 +
1180 +#define TX_COMPL_IRQS  ((IS_XS1_B)  | (IS_XS1_F) | \
1181 +                        (IS_XA1_B)  | (IS_XA1_F) | \
1182 +                        (IS_XS2_B)  | (IS_XS2_F) | \
1183 +                        (IS_XA2_B)  | (IS_XA2_F))
1184 +
1185 +#define NAPI_DRV_IRQS  ((IS_R1_F)   | (IS_R2_F) | \
1186 +                        (IS_XS1_F)  | (IS_XA1_F)| \
1187 +                        (IS_XS2_F)  | (IS_XA2_F))
1188 +
1189 +#define Y2_DRIVER_IRQS ((Y2_IS_STAT_BMU) | (Y2_IS_IRQ_SW) | (Y2_IS_POLL_CHK))
1190 +
1191 +#define SPECIAL_IRQS   ((IS_HW_ERR)    |(IS_I2C_READY)  | \
1192 +                        (IS_EXT_REG)   |(IS_TIMINT)     | \
1193 +                        (IS_PA_TO_RX1) |(IS_PA_TO_RX2)  | \
1194 +                        (IS_PA_TO_TX1) |(IS_PA_TO_TX2)  | \
1195 +                        (IS_MAC1)      |(IS_LNK_SYNC_M1)| \
1196 +                        (IS_MAC2)      |(IS_LNK_SYNC_M2)| \
1197 +                        (IS_R1_C)      |(IS_R2_C)       | \
1198 +                        (IS_XS1_C)     |(IS_XA1_C)      | \
1199 +                        (IS_XS2_C)     |(IS_XA2_C))
1200 +
1201 +#define Y2_SPECIAL_IRQS        ((Y2_IS_HW_ERR)   |(Y2_IS_ASF)      | \
1202 +                        (Y2_IS_TWSI_RDY) |(Y2_IS_TIMINT)   | \
1203 +                        (Y2_IS_IRQ_PHY2) |(Y2_IS_IRQ_MAC2) | \
1204 +                        (Y2_IS_CHK_RX2)  |(Y2_IS_CHK_TXS2) | \
1205 +                        (Y2_IS_CHK_TXA2) |(Y2_IS_IRQ_PHY1) | \
1206 +                        (Y2_IS_IRQ_MAC1) |(Y2_IS_CHK_RX1)  | \
1207 +                        (Y2_IS_CHK_TXS1) |(Y2_IS_CHK_TXA1))
1208 +
1209 +#define IRQ_MASK       ((IS_IRQ_SW)    | \
1210 +                        (IS_R1_F)      |(IS_R2_F)     | \
1211 +                        (IS_XS1_F)     |(IS_XA1_F)    | \
1212 +                        (IS_XS2_F)     |(IS_XA2_F)    | \
1213 +                        (IS_HW_ERR)    |(IS_I2C_READY)| \
1214 +                        (IS_EXT_REG)   |(IS_TIMINT)   | \
1215 +                        (IS_PA_TO_RX1) |(IS_PA_TO_RX2)| \
1216 +                        (IS_PA_TO_TX1) |(IS_PA_TO_TX2)| \
1217 +                        (IS_MAC1)      |(IS_MAC2)     | \
1218 +                        (IS_R1_C)      |(IS_R2_C)     | \
1219 +                        (IS_XS1_C)     |(IS_XA1_C)    | \
1220 +                        (IS_XS2_C)     |(IS_XA2_C))
1221 +
1222 +#define Y2_IRQ_MASK    ((Y2_DRIVER_IRQS) | (Y2_SPECIAL_IRQS))
1223 +
1224 +#define IRQ_HWE_MASK   (IS_ERR_MSK)            /* enable all HW irqs */
1225 +#define Y2_IRQ_HWE_MASK        (Y2_HWE_ALL_MSK)        /* enable all HW irqs */
1226
1227  typedef struct s_DevNet DEV_NET;
1228
1229  struct s_DevNet {
1230 -       int             PortNr;
1231 -       int             NetNr;
1232 -       SK_AC   *pAC;
1233 +       struct          proc_dir_entry *proc;
1234 +       int             PortNr;
1235 +       int             NetNr;
1236 +       char            InitialDevName[20];
1237 +       SK_BOOL         NetConsoleMode;
1238 +#ifdef Y2_RECOVERY
1239 +       struct          timer_list KernelTimer; /* Kernel timer struct  */
1240 +       int             TransmitTimeoutTimer;   /* Transmit timer       */
1241 +       SK_BOOL         TimerExpired;           /* Transmit timer       */
1242 +       SK_BOOL         InRecover;              /* Recover flag         */
1243 +#ifdef Y2_RX_CHECK
1244 +       SK_U32          PreviousMACFifoRP;      /* Backup of the FRP    */
1245 +       SK_U32          PreviousMACFifoRLev;    /* Backup of the FRL    */
1246 +       SK_U32          PreviousRXFifoRP;       /* Backup of the RX FRP */
1247 +       SK_U8           PreviousRXFifoRLev;     /* Backup of the RX FRL */
1248 +       SK_U32          LastJiffies;            /* Backup of the jiffies*/
1249 +#endif
1250 +#endif
1251 +       SK_AC           *pAC;
1252  };
1253
1254 -typedef struct s_TxPort                TX_PORT;
1255 +/*******************************************************************************
1256 + *
1257 + * Rx/Tx Port structures
1258 + *
1259 + ******************************************************************************/
1260
1261 -struct s_TxPort {
1262 -       /* the transmit descriptor rings */
1263 -       caddr_t         pTxDescrRing;   /* descriptor area memory */
1264 -       SK_U64          VTxDescrRing;   /* descr. area bus virt. addr. */
1265 -       TXD             *pTxdRingHead;  /* Head of Tx rings */
1266 -       TXD             *pTxdRingTail;  /* Tail of Tx rings */
1267 -       TXD             *pTxdRingPrev;  /* descriptor sent previously */
1268 -       int             TxdRingFree;    /* # of free entrys */
1269 -       spinlock_t      TxDesRingLock;  /* serialize descriptor accesses */
1270 -       SK_IOC          HwAddr;         /* bmu registers address */
1271 -       int             PortIndex;      /* index number of port (0 or 1) */
1272 +typedef struct s_TxPort        TX_PORT;
1273 +struct s_TxPort {                       /* the transmit descriptor rings */
1274 +       caddr_t         pTxDescrRing;   /* descriptor area memory        */
1275 +       SK_U64          VTxDescrRing;   /* descr. area bus virt. addr.   */
1276 +       TXD            *pTxdRingHead;   /* Head of Tx rings              */
1277 +       TXD            *pTxdRingTail;   /* Tail of Tx rings              */
1278 +       TXD            *pTxdRingPrev;   /* descriptor sent previously    */
1279 +       int             TxdRingPrevFree;/* previously # of free entrys   */
1280 +       int             TxdRingFree;    /* # of free entrys              */
1281 +       spinlock_t      TxDesRingLock;  /* serialize descriptor accesses */
1282 +       caddr_t         HwAddr;         /* bmu registers address         */
1283 +       int             PortIndex;      /* index number of port (0 or 1) */
1284 +       SK_PACKET      *TransmitPacketTable;
1285 +       SK_LE_TABLE     TxALET;         /* tx (async) list element table */
1286 +       SK_LE_TABLE     TxSLET;         /* tx (sync) list element table  */
1287 +       SK_PKT_QUEUE    TxQ_free;
1288 +       SK_PKT_QUEUE    TxAQ_waiting;
1289 +       SK_PKT_QUEUE    TxSQ_waiting;
1290 +       SK_PKT_QUEUE    TxAQ_working;
1291 +       SK_PKT_QUEUE    TxSQ_working;
1292 +       unsigned        LastDone;
1293  };
1294
1295 -typedef struct s_RxPort                RX_PORT;
1296 -
1297 -struct s_RxPort {
1298 -       /* the receive descriptor rings */
1299 -       caddr_t         pRxDescrRing;   /* descriptor area memory */
1300 -       SK_U64          VRxDescrRing;   /* descr. area bus virt. addr. */
1301 -       RXD             *pRxdRingHead;  /* Head of Rx rings */
1302 -       RXD             *pRxdRingTail;  /* Tail of Rx rings */
1303 -       RXD             *pRxdRingPrev;  /* descriptor given to BMU previously */
1304 -       int             RxdRingFree;    /* # of free entrys */
1305 -       int             RxCsum;         /* use receive checksum hardware */
1306 -       spinlock_t      RxDesRingLock;  /* serialize descriptor accesses */
1307 -       int             RxFillLimit;    /* limit for buffers in ring */
1308 -       SK_IOC          HwAddr;         /* bmu registers address */
1309 -       int             PortIndex;      /* index number of port (0 or 1) */
1310 +typedef struct s_RxPort        RX_PORT;
1311 +struct s_RxPort {                       /* the receive descriptor rings  */
1312 +       caddr_t         pRxDescrRing;   /* descriptor area memory        */
1313 +       SK_U64          VRxDescrRing;   /* descr. area bus virt. addr.   */
1314 +       RXD            *pRxdRingHead;   /* Head of Rx rings              */
1315 +       RXD            *pRxdRingTail;   /* Tail of Rx rings              */
1316 +       RXD            *pRxdRingPrev;   /* descr given to BMU previously */
1317 +       int             RxdRingFree;    /* # of free entrys              */
1318 +       spinlock_t      RxDesRingLock;  /* serialize descriptor accesses */
1319 +       int             RxFillLimit;    /* limit for buffers in ring     */
1320 +       caddr_t         HwAddr;         /* bmu registers address         */
1321 +       int             PortIndex;      /* index number of port (0 or 1) */
1322 +       SK_BOOL         UseRxCsum;      /* use Rx checksumming (yes/no)  */
1323 +       SK_PACKET      *ReceivePacketTable;
1324 +       SK_LE_TABLE     RxLET;          /* rx list element table         */
1325 +       SK_PKT_QUEUE    RxQ_working;
1326 +       SK_PKT_QUEUE    RxQ_waiting;
1327 +       int             RxBufSize;
1328  };
1329
1330 -/* Definitions needed for interrupt moderation *******************************/
1331 +/*******************************************************************************
1332 + *
1333 + * Interrupt masks used in combination with interrupt moderation
1334 + *
1335 + ******************************************************************************/
1336
1337  #define IRQ_EOF_AS_TX     ((IS_XA1_F)     | (IS_XA2_F))
1338  #define IRQ_EOF_SY_TX     ((IS_XS1_F)     | (IS_XS2_F))
1339 @@ -314,134 +732,151 @@
1340  #define IRQ_MASK_SP_TX    ((SPECIAL_IRQS)    | (IRQ_MASK_TX_ONLY))
1341  #define IRQ_MASK_RX_TX_SP ((SPECIAL_IRQS)    | (IRQ_MASK_TX_RX))
1342
1343 -#define C_INT_MOD_NONE                 1
1344 -#define C_INT_MOD_STATIC               2
1345 -#define C_INT_MOD_DYNAMIC              4
1346 -
1347 -#define C_CLK_FREQ_GENESIS      53215000 /* shorter: 53.125 MHz  */
1348 -#define C_CLK_FREQ_YUKON        78215000 /* shorter: 78.125 MHz  */
1349 -
1350 -#define C_INTS_PER_SEC_DEFAULT      2000
1351 -#define C_INT_MOD_ENABLE_PERCENTAGE   50 /* if higher 50% enable */
1352 -#define C_INT_MOD_DISABLE_PERCENTAGE  50 /* if lower 50% disable */
1353 -#define C_INT_MOD_IPS_LOWER_RANGE     30
1354 -#define C_INT_MOD_IPS_UPPER_RANGE     40000
1355 -
1356 -
1357 -typedef struct s_DynIrqModInfo  DIM_INFO;
1358 -struct s_DynIrqModInfo {
1359 -       unsigned long   PrevTimeVal;
1360 -       unsigned int    PrevSysLoad;
1361 -       unsigned int    PrevUsedTime;
1362 -       unsigned int    PrevTotalTime;
1363 -       int             PrevUsedDescrRatio;
1364 -       int             NbrProcessedDescr;
1365 -        SK_U64          PrevPort0RxIntrCts;
1366 -        SK_U64          PrevPort1RxIntrCts;
1367 -        SK_U64          PrevPort0TxIntrCts;
1368 -        SK_U64          PrevPort1TxIntrCts;
1369 -       SK_BOOL         ModJustEnabled;     /* Moderation just enabled yes/no */
1370 -
1371 -       int             MaxModIntsPerSec;            /* Moderation Threshold */
1372 -       int             MaxModIntsPerSecUpperLimit;  /* Upper limit for DIM  */
1373 -       int             MaxModIntsPerSecLowerLimit;  /* Lower limit for DIM  */
1374 -
1375 -       long            MaskIrqModeration;   /* ModIrqType (eg. 'TxRx')      */
1376 -       SK_BOOL         DisplayStats;        /* Stats yes/no                 */
1377 -       SK_BOOL         AutoSizing;          /* Resize DIM-timer on/off      */
1378 -       int             IntModTypeSelect;    /* EnableIntMod (eg. 'dynamic') */
1379 +#define IRQ_MASK_Y2_TX_ONLY  (Y2_IS_STAT_BMU)
1380 +#define IRQ_MASK_Y2_RX_ONLY  (Y2_IS_STAT_BMU)
1381 +#define IRQ_MASK_Y2_SP_ONLY  (SPECIAL_IRQS)
1382 +#define IRQ_MASK_Y2_TX_RX    ((IRQ_MASK_TX_ONLY)| (IRQ_MASK_RX_ONLY))
1383 +#define IRQ_MASK_Y2_SP_RX    ((SPECIAL_IRQS)    | (IRQ_MASK_RX_ONLY))
1384 +#define IRQ_MASK_Y2_SP_TX    ((SPECIAL_IRQS)    | (IRQ_MASK_TX_ONLY))
1385 +#define IRQ_MASK_Y2_RX_TX_SP ((SPECIAL_IRQS)    | (IRQ_MASK_TX_RX))
1386
1387 -       SK_TIMER        ModTimer; /* just some timer */
1388 -};
1389 +/*******************************************************************************
1390 + *
1391 + * Defines and typedefs regarding interrupt moderation
1392 + *
1393 + ******************************************************************************/
1394
1395 -typedef struct s_PerStrm       PER_STRM;
1396 +#define C_INT_MOD_NONE                 1
1397 +#define C_INT_MOD_STATIC               2
1398 +#define C_INT_MOD_DYNAMIC              4
1399 +
1400 +#define C_CLK_FREQ_GENESIS              53215000 /* or:  53.125 MHz */
1401 +#define C_CLK_FREQ_YUKON                78215000 /* or:  78.125 MHz */
1402 +#define C_CLK_FREQ_YUKON_EC            125000000 /* or: 125.000 MHz */
1403 +
1404 +#define C_Y2_INTS_PER_SEC_DEFAULT      5000
1405 +#define C_INTS_PER_SEC_DEFAULT         2000
1406 +#define C_INT_MOD_IPS_LOWER_RANGE      30        /* in IRQs/second */
1407 +#define C_INT_MOD_IPS_UPPER_RANGE      40000     /* in IRQs/second */
1408 +
1409 +typedef struct s_DynIrqModInfo {
1410 +       SK_U64     PrevPort0RxIntrCts;
1411 +       SK_U64     PrevPort1RxIntrCts;
1412 +       SK_U64     PrevPort0TxIntrCts;
1413 +       SK_U64     PrevPort1TxIntrCts;
1414 +       SK_U64     PrevPort0StatusLeIntrCts;
1415 +       SK_U64     PrevPort1StatusLeIntrCts;
1416 +       int        MaxModIntsPerSec;            /* Moderation Threshold   */
1417 +       int        MaxModIntsPerSecUpperLimit;  /* Upper limit for DIM    */
1418 +       int        MaxModIntsPerSecLowerLimit;  /* Lower limit for DIM    */
1419 +       long       MaskIrqModeration;           /* IRQ Mask (eg. 'TxRx')  */
1420 +       int        IntModTypeSelect;            /* Type  (eg. 'dynamic')  */
1421 +       int        DynIrqModSampleInterval;     /* expressed in seconds!  */
1422 +       SK_TIMER   ModTimer;                    /* Timer for dynamic mod. */
1423 +} DIM_INFO;
1424
1425 -#define SK_ALLOC_IRQ   0x00000001
1426 +/*******************************************************************************
1427 + *
1428 + * Defines and typedefs regarding wake-on-lan
1429 + *
1430 + ******************************************************************************/
1431 +
1432 +typedef struct s_WakeOnLanInfo {
1433 +       SK_U32     SupportedWolOptions;         /* e.g. WAKE_PHY...         */
1434 +       SK_U32     ConfiguredWolOptions;        /* e.g. WAKE_PHY...         */
1435 +} WOL_INFO;
1436
1437 -#ifdef SK_DIAG_SUPPORT
1438 +#define SK_ALLOC_IRQ   0x00000001
1439  #define        DIAG_ACTIVE             1
1440  #define        DIAG_NOTACTIVE          0
1441 -#endif
1442
1443  /****************************************************************************
1444 + *
1445   * Per board structure / Adapter Context structure:
1446 - *     Allocated within attach(9e) and freed within detach(9e).
1447 - *     Contains all 'per device' necessary handles, flags, locks etc.:
1448 - */
1449 + * Contains all 'per device' necessary handles, flags, locks etc.:
1450 + *
1451 + ******************************************************************************/
1452 +
1453  struct s_AC  {
1454 -       SK_GEINIT       GIni;           /* GE init struct */
1455 -       SK_PNMI         Pnmi;           /* PNMI data struct */
1456 -       SK_VPD          vpd;            /* vpd data struct */
1457 -       SK_QUEUE        Event;          /* Event queue */
1458 -       SK_HWT          Hwt;            /* Hardware Timer control struct */
1459 -       SK_TIMCTRL      Tim;            /* Software Timer control struct */
1460 -       SK_I2C          I2c;            /* I2C relevant data structure */
1461 -       SK_ADDR         Addr;           /* for Address module */
1462 -       SK_CSUM         Csum;           /* for checksum module */
1463 -       SK_RLMT         Rlmt;           /* for rlmt module */
1464 -       spinlock_t      SlowPathLock;   /* Normal IRQ lock */
1465 -       struct timer_list BlinkTimer;   /* for LED blinking */
1466 -       int             LedsOn;
1467 -       SK_PNMI_STRUCT_DATA PnmiStruct; /* structure to get all Pnmi-Data */
1468 -       int                     RlmtMode;       /* link check mode to set */
1469 -       int                     RlmtNets;       /* Number of nets */
1470 -
1471 -       SK_IOC          IoBase;         /* register set of adapter */
1472 -       int             BoardLevel;     /* level of active hw init (0-2) */
1473 -
1474 -       SK_U32          AllocFlag;      /* flag allocation of resources */
1475 -       struct pci_dev  *PciDev;        /* for access to pci config space */
1476 -       struct SK_NET_DEVICE    *dev[2];        /* pointer to device struct */
1477 -
1478 -       int             RxBufSize;      /* length of receive buffers */
1479 -        struct net_device_stats stats; /* linux 'netstat -i' statistics */
1480 -       int             Index;          /* internal board index number */
1481 -
1482 -       /* adapter RAM sizes for queues of active port */
1483 -       int             RxQueueSize;    /* memory used for receive queue */
1484 -       int             TxSQueueSize;   /* memory used for sync. tx queue */
1485 -       int             TxAQueueSize;   /* memory used for async. tx queue */
1486 -
1487 -       int             PromiscCount;   /* promiscuous mode counter  */
1488 -       int             AllMultiCount;  /* allmulticast mode counter */
1489 -       int             MulticCount;    /* number of different MC    */
1490 -                                       /*  addresses for this board */
1491 -                                       /*  (may be more than HW can)*/
1492 -
1493 -       int             HWRevision;     /* Hardware revision */
1494 -       int             ActivePort;     /* the active XMAC port */
1495 -       int             MaxPorts;               /* number of activated ports */
1496 -       int             TxDescrPerRing; /* # of descriptors per tx ring */
1497 -       int             RxDescrPerRing; /* # of descriptors per rx ring */
1498 -
1499 -       caddr_t         pDescrMem;      /* Pointer to the descriptor area */
1500 -       dma_addr_t      pDescrMemDMA;   /* PCI DMA address of area */
1501 -
1502 -       /* the port structures with descriptor rings */
1503 -       TX_PORT         TxPort[SK_MAX_MACS][2];
1504 -       RX_PORT         RxPort[SK_MAX_MACS];
1505 -
1506 -       SK_BOOL         CheckQueue;     /* check event queue soon */
1507 -       SK_TIMER        DrvCleanupTimer;/* to check for pending descriptors */
1508 -       DIM_INFO        DynIrqModInfo;  /* all data related to DIM */
1509 -
1510 -       /* Only for tests */
1511 -       int             PortDown;
1512 -       int             ChipsetType;    /*  Chipset family type
1513 -                                        *  0 == Genesis family support
1514 -                                        *  1 == Yukon family support
1515 -                                        */
1516 -#ifdef SK_DIAG_SUPPORT
1517 -       SK_U32          DiagModeActive;         /* is diag active?      */
1518 -       SK_BOOL         DiagFlowCtrl;           /* for control purposes */
1519 -       SK_PNMI_STRUCT_DATA PnmiBackup;         /* backup structure for all Pnmi-Data */
1520 -       SK_BOOL         WasIfUp[SK_MAX_MACS];   /* for OpenClose while
1521 -                                                * DIAG is busy with NIC
1522 -                                                */
1523 +       SK_GEINIT                GIni;          /* GE init struct             */
1524 +       SK_PNMI                  Pnmi;          /* PNMI data struct           */
1525 +       SK_VPD                   vpd;           /* vpd data struct            */
1526 +       SK_QUEUE                 Event;         /* Event queue                */
1527 +       SK_HWT                   Hwt;           /* Hardware Timer ctrl struct */
1528 +       SK_TIMCTRL               Tim;           /* Software Timer ctrl struct */
1529 +       SK_I2C                   I2c;           /* I2C relevant data structure*/
1530 +       SK_ADDR                  Addr;          /* for Address module         */
1531 +       SK_CSUM                  Csum;          /* for checksum module        */
1532 +       SK_RLMT                  Rlmt;          /* for rlmt module            */
1533 +       spinlock_t               SlowPathLock;  /* Normal IRQ lock            */
1534 +       spinlock_t               InitLock;      /* Init lock                  */
1535 +       spinlock_t               TxQueueLock;   /* TX Queue lock              */
1536 +       SK_PNMI_STRUCT_DATA      PnmiStruct;    /* struct for all Pnmi-Data   */
1537 +       int                      RlmtMode;      /* link check mode to set     */
1538 +       int                      RlmtNets;      /* Number of nets             */
1539 +       SK_IOC                   IoBase;        /* register set of adapter    */
1540 +       int                      BoardLevel;    /* level of hw init (0-2)     */
1541 +       char                     DeviceStr[80]; /* adapter string from vpd    */
1542 +       SK_U32                   AllocFlag;     /* alloc flag of resources    */
1543 +       struct pci_dev          *PciDev;        /* for access to pci cfg space*/
1544 +       SK_U32                   PciDevId;      /* pci device id              */
1545 +       struct SK_NET_DEVICE    *dev[2];        /* pointer to device struct   */
1546 +       char                     Name[30];      /* driver name                */
1547 +       struct SK_NET_DEVICE    *Next;          /* link all devs for cleanup  */
1548 +       struct net_device_stats  stats;         /* linux 'netstat -i' stats   */
1549 +       int                      Index;         /* internal board idx number  */
1550 +       int                      RxQueueSize;   /* memory used for RX queue   */
1551 +       int                      TxSQueueSize;  /* memory used for TXS queue  */
1552 +       int                      TxAQueueSize;  /* memory used for TXA queue  */
1553 +       int                      PromiscCount;  /* promiscuous mode counter   */
1554 +       int                      AllMultiCount; /* allmulticast mode counter  */
1555 +       int                      MulticCount;   /* number of MC addresses used*/
1556 +       int                      HWRevision;    /* Hardware revision          */
1557 +       int                      ActivePort;    /* the active XMAC port       */
1558 +       int                      MaxPorts;      /* number of activated ports  */
1559 +       int                      TxDescrPerRing;/* # of descriptors TX ring   */
1560 +       int                      RxDescrPerRing;/* # of descriptors RX ring   */
1561 +       caddr_t                  pDescrMem;     /* Ptr to the descriptor area */
1562 +       dma_addr_t               pDescrMemDMA;  /* PCI DMA address of area    */
1563 +       SK_U32                   PciState[16];  /* PCI state */
1564 +       TX_PORT                  TxPort[SK_MAX_MACS][2];
1565 +       RX_PORT                  RxPort[SK_MAX_MACS];
1566 +       SK_LE_TABLE              StatusLETable;
1567 +       unsigned                 SizeOfAlignedLETables;
1568 +       spinlock_t               SetPutIndexLock;
1569 +       int                      MaxUnusedRxLeWorking;
1570 +       unsigned int             CsOfs1;        /* for checksum calculation   */
1571 +       unsigned int             CsOfs2;        /* for checksum calculation   */
1572 +       SK_U32                   CsOfs;         /* for checksum calculation   */
1573 +       SK_BOOL                  CheckQueue;    /* check event queue soon     */
1574 +       DIM_INFO                 DynIrqModInfo; /* all data related to IntMod */
1575 +       WOL_INFO                 WolInfo;       /* all info regarding WOL     */
1576 +       int                      ChipsetType;   /* 0=GENESIS; 1=Yukon         */
1577 +       SK_BOOL                  LowLatency;    /* LowLatency optimization on?*/
1578 +       SK_U32                   DiagModeActive;/* is diag active?            */
1579 +       SK_BOOL                  DiagFlowCtrl;  /* for control purposes       */
1580 +       SK_PNMI_STRUCT_DATA      PnmiBackup;    /* backup structure for PNMI  */
1581 +       SK_BOOL                  WasIfUp[SK_MAX_MACS];
1582 +#ifdef USE_TIST_FOR_RESET
1583 +       int                      AdapterResetState;
1584 +       SK_U32                   MinTistLo;
1585 +       SK_U32                   MinTistHi;
1586 +#endif
1587 +#ifdef Y2_RECOVERY
1588 +       int                      LastPort;       /* port for curr. handled rx */
1589 +        int                      LastOpc;        /* last rx LEs opcode       */
1590 +#endif
1591 +#ifdef Y2_SYNC_CHECK
1592 +       unsigned long            FramesWithoutSyncCheck; /* since last check  */
1593  #endif
1594 -
1595  };
1596
1597
1598 -#endif /* __INC_SKDRV2ND_H */
1599
1600 +#endif
1601 +
1602 +/*******************************************************************************
1603 + *
1604 + * End of file
1605 + *
1606 + ******************************************************************************/
1607 diff -ruN linux/drivers/net/sk98lin/h/skerror.h linux-new/drivers/net/sk98lin/h/skerror.h
1608 --- linux/drivers/net/sk98lin/h/skerror.h       2006-09-20 05:42:06.000000000 +0200
1609 +++ linux-new/drivers/net/sk98lin/h/skerror.h   2006-07-28 14:13:54.000000000 +0200
1610 @@ -2,23 +2,24 @@
1611   *
1612   * Name:       skerror.h
1613   * Project:    Gigabit Ethernet Adapters, Common Modules
1614 - * Version:    $Revision$
1615 - * Date:       $Date$
1616 + * Version:    $Revision$
1617 + * Date:       $Date$
1618   * Purpose:    SK specific Error log support
1619   *
1620   ******************************************************************************/
1621
1622  /******************************************************************************
1623   *
1624 + *     LICENSE:
1625   *     (C)Copyright 1998-2002 SysKonnect.
1626 - *     (C)Copyright 2002-2003 Marvell.
1627 + *     (C)Copyright 2002-2004 Marvell.
1628   *
1629   *     This program is free software; you can redistribute it and/or modify
1630   *     it under the terms of the GNU General Public License as published by
1631   *     the Free Software Foundation; either version 2 of the License, or
1632   *     (at your option) any later version.
1633 - *
1634   *     The information in this file is provided "AS IS" without warranty.
1635 + *     /LICENSE
1636   *
1637   ******************************************************************************/
1638
1639 @@ -36,7 +37,6 @@
1640  #define        SK_ERRCL_HW                     (1L<<4) /* Hardware Failure */
1641  #define        SK_ERRCL_COMM           (1L<<5) /* Communication error */
1642
1643 -
1644  /*
1645   * Define Error Code Bases
1646   */
1647 @@ -49,7 +49,9 @@
1648  #define        SK_ERRBASE_I2C           700    /* Base Error number for I2C module */
1649  #define        SK_ERRBASE_QUEUE         800    /* Base Error number for Scheduler */
1650  #define        SK_ERRBASE_ADDR          900    /* Base Error number for Address module */
1651 -#define SK_ERRBASE_PECP                1000    /* Base Error number for PECP */
1652 +#define SK_ERRBASE_PECP                1000    /* Base Error number for PECP */
1653  #define        SK_ERRBASE_DRV          1100    /* Base Error number for Driver */
1654 +#define SK_ERRBASE_ASF         1200    /* Base Error number for ASF */
1655
1656  #endif /* _INC_SKERROR_H_ */
1657 +
1658 diff -ruN linux/drivers/net/sk98lin/h/skgedrv.h linux-new/drivers/net/sk98lin/h/skgedrv.h
1659 --- linux/drivers/net/sk98lin/h/skgedrv.h       2006-09-20 05:42:06.000000000 +0200
1660 +++ linux-new/drivers/net/sk98lin/h/skgedrv.h   2006-07-28 14:13:54.000000000 +0200
1661 @@ -2,23 +2,24 @@
1662   *
1663   * Name:       skgedrv.h
1664   * Project:    Gigabit Ethernet Adapters, Common Modules
1665 - * Version:    $Revision$
1666 - * Date:       $Date$
1667 + * Version:    $Revision$
1668 + * Date:       $Date$
1669   * Purpose:    Interface with the driver
1670   *
1671   ******************************************************************************/
1672
1673  /******************************************************************************
1674   *
1675 + *     LICENSE:
1676   *     (C)Copyright 1998-2002 SysKonnect.
1677 - *     (C)Copyright 2002-2003 Marvell.
1678 + *     (C)Copyright 2002-2006 Marvell.
1679   *
1680   *     This program is free software; you can redistribute it and/or modify
1681   *     it under the terms of the GNU General Public License as published by
1682   *     the Free Software Foundation; either version 2 of the License, or
1683   *     (at your option) any later version.
1684 - *
1685   *     The information in this file is provided "AS IS" without warranty.
1686 + *     /LICENSE
1687   *
1688   ******************************************************************************/
1689
1690 @@ -33,7 +34,7 @@
1691   * In case of the driver we put the definition of the events here.
1692   */
1693  #define SK_DRV_PORT_RESET               1      /* The port needs to be reset */
1694 -#define SK_DRV_NET_UP                   2      /* The net is operational */
1695 +#define SK_DRV_NET_UP                   2      /* The net is operational */
1696  #define SK_DRV_NET_DOWN                         3      /* The net is down */
1697  #define SK_DRV_SWITCH_SOFT              4      /* Ports switch with both links connected */
1698  #define SK_DRV_SWITCH_HARD              5      /* Port switch due to link failure */
1699 @@ -44,8 +45,11 @@
1700  #define SK_DRV_POWER_DOWN              10      /* Power down mode */
1701  #define SK_DRV_TIMER                   11      /* Timer for free use */
1702  #ifdef SK_NO_RLMT
1703 -#define SK_DRV_LINK_UP                 12      /* Link Up event for driver */
1704 +#define SK_DRV_LINK_UP                 12      /* Link Up event for driver */
1705  #define SK_DRV_LINK_DOWN               13      /* Link Down event for driver */
1706  #endif
1707  #define SK_DRV_DOWNSHIFT_DET   14      /* Downshift 4-Pair / 2-Pair (YUKON only) */
1708 +#define SK_DRV_RX_OVERFLOW             15      /* Receive Overflow */
1709 +#define SK_DRV_LIPA_NOT_AN_ABLE        16      /* Link Partner not Auto-Negotiation able */
1710 +#define SK_DRV_PEX_LINK_WIDTH  17      /* PEX negotiated Link width not maximum */
1711  #endif /* __INC_SKGEDRV_H_ */
1712 diff -ruN linux/drivers/net/sk98lin/h/skgehw.h linux-new/drivers/net/sk98lin/h/skgehw.h
1713 --- linux/drivers/net/sk98lin/h/skgehw.h        2006-09-20 05:42:06.000000000 +0200
1714 +++ linux-new/drivers/net/sk98lin/h/skgehw.h    2006-07-28 14:13:54.000000000 +0200
1715 @@ -2,23 +2,24 @@
1716   *
1717   * Name:       skgehw.h
1718   * Project:    Gigabit Ethernet Adapters, Common Modules
1719 - * Version:    $Revision$
1720 - * Date:       $Date$
1721 + * Version:    $Revision$
1722 + * Date:       $Date$
1723   * Purpose:    Defines and Macros for the Gigabit Ethernet Adapter Product Family
1724   *
1725   ******************************************************************************/
1726
1727  /******************************************************************************
1728   *
1729 + *     LICENSE:
1730   *     (C)Copyright 1998-2002 SysKonnect.
1731 - *     (C)Copyright 2002-2003 Marvell.
1732 + *     (C)Copyright 2002-2006 Marvell.
1733   *
1734   *     This program is free software; you can redistribute it and/or modify
1735   *     it under the terms of the GNU General Public License as published by
1736   *     the Free Software Foundation; either version 2 of the License, or
1737   *     (at your option) any later version.
1738 - *
1739   *     The information in this file is provided "AS IS" without warranty.
1740 + *     /LICENSE
1741   *
1742   ******************************************************************************/
1743
1744 @@ -114,6 +115,16 @@
1745  #define SHIFT1(x)      ((x) << 1)
1746  #define SHIFT0(x)      ((x) << 0)
1747
1748 +/* Macro for arbitrary alignment of a given pointer */
1749 +#define ALIGN_ADDR( ADDRESS, GRANULARITY ) { \
1750 +       SK_UPTR addr = (SK_UPTR)(ADDRESS); \
1751 +       if (addr & ((GRANULARITY)-1)) { \
1752 +               addr += (GRANULARITY); \
1753 +               addr &= ~(SK_UPTR)((GRANULARITY)-1); \
1754 +               ADDRESS = (void *)addr; \
1755 +       }\
1756 +}
1757 +
1758  /*
1759   * Configuration Space header
1760   * Since this module is used for different OS', those may be
1761 @@ -132,34 +143,81 @@
1762  #define PCI_BIST               0x0f    /*  8 bit       Built-in selftest */
1763  #define PCI_BASE_1ST   0x10    /* 32 bit       1st Base address */
1764  #define PCI_BASE_2ND   0x14    /* 32 bit       2nd Base address */
1765 -       /* Byte 0x18..0x2b:     reserved */
1766 +       /* Bytes 0x18..0x2b:    reserved */
1767  #define PCI_SUB_VID            0x2c    /* 16 bit       Subsystem Vendor ID */
1768  #define PCI_SUB_ID             0x2e    /* 16 bit       Subsystem ID */
1769  #define PCI_BASE_ROM   0x30    /* 32 bit       Expansion ROM Base Address */
1770 -#define PCI_CAP_PTR            0x34    /*  8 bit       Capabilities Ptr */
1771 -       /* Byte 0x35..0x3b:     reserved */
1772 +#define PCI_CAP_PTR            0x34    /*  8 bit       Capabilities Pointer */
1773 +       /* Bytes 0x35..0x3b:    reserved */
1774  #define PCI_IRQ_LINE   0x3c    /*  8 bit       Interrupt Line */
1775  #define PCI_IRQ_PIN            0x3d    /*  8 bit       Interrupt Pin */
1776  #define PCI_MIN_GNT            0x3e    /*  8 bit       Min_Gnt */
1777  #define PCI_MAX_LAT            0x3f    /*  8 bit       Max_Lat */
1778         /* Device Dependent Region */
1779 -#define PCI_OUR_REG_1  0x40    /* 32 bit       Our Register 1 */
1780 -#define PCI_OUR_REG_2  0x44    /* 32 bit       Our Register 2 */
1781 +#define PCI_OUR_REG_1  0x40    /* 32 bit       Our Register 1 */
1782 +#define PCI_OUR_REG_2  0x44    /* 32 bit       Our Register 2 */
1783         /* Power Management Region */
1784 -#define PCI_PM_CAP_ID  0x48    /*  8 bit       Power Management Cap. ID */
1785 -#define PCI_PM_NITEM   0x49    /*  8 bit       Next Item Ptr */
1786 -#define PCI_PM_CAP_REG 0x4a    /* 16 bit       Power Management Capabilities */
1787 -#define PCI_PM_CTL_STS 0x4c    /* 16 bit       Power Manag. Control/Status */
1788 +#define PCI_PM_CAP_ID  0x48    /*  8 bit       Power Management Cap. ID */
1789 +#define PCI_PM_NITEM   0x49    /*  8 bit       PM Next Item Pointer */
1790 +#define PCI_PM_CAP_REG 0x4a    /* 16 bit       Power Management Capabilities */
1791 +#define PCI_PM_CTL_STS 0x4c    /* 16 bit       Power Manag. Control/Status */
1792         /* Byte 0x4e:   reserved */
1793 -#define PCI_PM_DAT_REG 0x4f    /*  8 bit       Power Manag. Data Register */
1794 +#define PCI_PM_DAT_REG 0x4f    /*  8 bit       Power Manag. Data Register */
1795         /* VPD Region */
1796 -#define PCI_VPD_CAP_ID 0x50    /*  8 bit       VPD Cap. ID */
1797 -#define PCI_VPD_NITEM  0x51    /*  8 bit       Next Item Ptr */
1798 -#define PCI_VPD_ADR_REG        0x52    /* 16 bit       VPD Address Register */
1799 -#define PCI_VPD_DAT_REG        0x54    /* 32 bit       VPD Data Register */
1800 -       /* Byte 0x58..0x59:     reserved */
1801 -#define PCI_SER_LD_CTRL        0x5a    /* 16 bit       SEEPROM Loader Ctrl (YUKON only) */
1802 -       /* Byte 0x5c..0xff:     reserved */
1803 +#define PCI_VPD_CAP_ID 0x50    /*  8 bit       VPD Cap. ID */
1804 +#define PCI_VPD_NITEM  0x51    /*  8 bit       VPD Next Item Pointer */
1805 +#define PCI_VPD_ADR_REG        0x52    /* 16 bit       VPD Address Register */
1806 +#define PCI_VPD_DAT_REG        0x54    /* 32 bit       VPD Data Register */
1807 +       /* Bytes 0x58..0x59:    reserved */
1808 +#define PCI_SER_LD_CTRL        0x5a    /* 16 bit       SEEPROM Loader Ctrl (YUKON only) */
1809 +       /* Bytes 0x5c..0xfc:    used by Yukon-2 */
1810 +#define PCI_MSI_CAP_ID 0x5c    /*  8 bit       MSI Capability ID Register */
1811 +#define PCI_MSI_NITEM  0x5d    /*  8 bit       MSI Next Item Pointer */
1812 +#define PCI_MSI_CTRL   0x5e    /* 16 bit       MSI Message Control */
1813 +#define PCI_MSI_ADR_LO 0x60    /* 32 bit       MSI Message Address (Lower) */
1814 +#define PCI_MSI_ADR_HI 0x64    /* 32 bit       MSI Message Address (Upper) */
1815 +#define PCI_MSI_DATA   0x68    /* 16 bit       MSI Message Data */
1816 +       /* Bytes 0x6a..0x6b:    reserved */
1817 +#define PCI_X_CAP_ID   0x6c    /*  8 bit       PCI-X Capability ID Register */
1818 +#define PCI_X_NITEM            0x6d    /*  8 bit       PCI-X Next Item Pointer */
1819 +#define PCI_X_COMMAND  0x6e    /* 16 bit       PCI-X Command */
1820 +#define PCI_X_PE_STAT  0x70    /* 32 bit       PCI-X / PE Status */
1821 +#define PCI_CAL_CTRL   0x74    /* 16 bit       PCI Calibration Control Register */
1822 +#define PCI_CAL_STAT   0x76    /* 16 bit       PCI Calibration Status Register */
1823 +#define PCI_DISC_CNT   0x78    /* 16 bit       PCI Discard Counter */
1824 +#define PCI_RETRY_CNT  0x7a    /*  8 bit       PCI Retry Counter */
1825 +       /* Byte 0x7b:   reserved */
1826 +#define PCI_OUR_STATUS 0x7c    /* 32 bit       Adapter Status Register */
1827 +#define PCI_OUR_REG_3  0x80    /* 32 bit       Our Register 3 (Yukon-ECU only) */
1828 +#define PCI_OUR_REG_4  0x84    /* 32 bit       Our Register 4 (Yukon-ECU only) */
1829 +#define PCI_OUR_REG_5  0x88    /* 32 bit       Our Register 5 (Yukon-ECU only) */
1830 +       /* Bytes 0x8c..0xdf:    reserved */
1831 +
1832 +/* PCI Express Capability */
1833 +#define PEX_CAP_ID             0xe0    /*  8 bit       PEX Capability ID */
1834 +#define PEX_NITEM              0xe1    /*  8 bit       PEX Next Item Pointer */
1835 +#define PEX_CAP_REG            0xe2    /* 16 bit       PEX Capability Register */
1836 +#define PEX_DEV_CAP            0xe4    /* 32 bit       PEX Device Capabilities */
1837 +#define PEX_DEV_CTRL   0xe8    /* 16 bit       PEX Device Control */
1838 +#define PEX_DEV_STAT   0xea    /* 16 bit       PEX Device Status */
1839 +#define PEX_LNK_CAP            0xec    /* 32 bit       PEX Link Capabilities */
1840 +#define PEX_LNK_CTRL   0xf0    /* 16 bit       PEX Link Control */
1841 +#define PEX_LNK_STAT   0xf2    /* 16 bit       PEX Link Status */
1842 +       /* Bytes 0xf4..0xff:    reserved */
1843 +
1844 +/* PCI Express Extended Capabilities */
1845 +#define PEX_ADV_ERR_REP                0x100   /* 32 bit       PEX Advanced Error Reporting */
1846 +#define PEX_UNC_ERR_STAT       0x104   /* 32 bit       PEX Uncorr. Errors Status */
1847 +#define PEX_UNC_ERR_MASK       0x108   /* 32 bit       PEX Uncorr. Errors Mask */
1848 +#define PEX_UNC_ERR_SEV                0x10c   /* 32 bit       PEX Uncorr. Errors Severity */
1849 +#define PEX_COR_ERR_STAT       0x110   /* 32 bit       PEX Correc. Errors Status */
1850 +#define PEX_COR_ERR_MASK       0x114   /* 32 bit       PEX Correc. Errors Mask */
1851 +#define PEX_ADV_ERR_CAP_C      0x118   /* 32 bit       PEX Advanced Error Cap./Ctrl */
1852 +#define PEX_HEADER_LOG         0x11c   /* 4x32 bit     PEX Header Log Register */
1853 +
1854 +/* PCI Express Ack Timer for 1x Link */
1855 +#define PEX_ACK_LAT_TOX1       0x228   /* 16 bit       PEX Ack Latency Timeout x1 */
1856 +#define PEX_ACK_RPLY_TOX1      0x22a   /* 16 bit       PEX Ack Reply Timeout val x1 */
1857
1858  /*
1859   * I2C Address (PCI Config)
1860 @@ -180,13 +238,13 @@
1861  #define PCI_ADSTEP             BIT_7S          /* Address Stepping */
1862  #define PCI_PERREN             BIT_6S          /* Parity Report Response enable */
1863  #define PCI_VGA_SNOOP  BIT_5S          /* VGA palette snoop */
1864 -#define PCI_MWIEN              BIT_4S          /* Memory write an inv cycl ena */
1865 +#define PCI_MWIEN              BIT_4S          /* Memory write an inv cycl enable */
1866  #define PCI_SCYCEN             BIT_3S          /* Special Cycle enable */
1867  #define PCI_BMEN               BIT_2S          /* Bus Master enable */
1868  #define PCI_MEMEN              BIT_1S          /* Memory Space Access enable */
1869  #define PCI_IOEN               BIT_0S          /* I/O Space Access enable */
1870
1871 -#define PCI_COMMAND_VAL        (PCI_FBTEN | PCI_SERREN | PCI_PERREN | PCI_MWIEN |\
1872 +#define PCI_COMMAND_VAL        (PCI_INT_DIS | PCI_SERREN | PCI_PERREN | \
1873                                                  PCI_BMEN | PCI_MEMEN | PCI_IOEN)
1874
1875  /*     PCI_STATUS      16 bit  Status */
1876 @@ -220,7 +278,7 @@
1877
1878  /*     PCI_HEADER_T    8 bit   Header Type */
1879  #define PCI_HD_MF_DEV  BIT_7S  /* 0= single, 1= multi-func dev */
1880 -#define PCI_HD_TYPE            0x7f    /* Bit 6..0:    Header Layout 0= normal */
1881 +#define PCI_HD_TYPE            0x7f    /* Bit 6..0:    Header Layout (0=normal) */
1882
1883  /*     PCI_BIST        8 bit   Built-in selftest */
1884  /*     Built-in Self test not supported (optional) */
1885 @@ -229,33 +287,42 @@
1886  #define PCI_MEMSIZE            0x4000L         /* use 16 kB Memory Base */
1887  #define PCI_MEMBASE_MSK 0xffffc000L    /* Bit 31..14:  Memory Base Address */
1888  #define PCI_MEMSIZE_MSK 0x00003ff0L    /* Bit 13.. 4:  Memory Size Req. */
1889 -#define PCI_PREFEN             BIT_3           /* Prefetchable */
1890 -#define PCI_MEM_TYP            (3L<<2)         /* Bit  2.. 1:  Memory Type */
1891 +#define PCI_PREFEN             BIT_3           /* Prefetch enable */
1892 +#define PCI_MEM_TYP_MSK        (3L<<1)         /* Bit  2.. 1:  Memory Type Mask */
1893 +#define PCI_MEMSPACE   BIT_0           /* Memory Space Indicator */
1894 +
1895  #define PCI_MEM32BIT   (0L<<1)         /* Base addr anywhere in 32 Bit range */
1896  #define PCI_MEM1M              (1L<<1)         /* Base addr below 1 MegaByte */
1897  #define PCI_MEM64BIT   (2L<<1)         /* Base addr anywhere in 64 Bit range */
1898 -#define PCI_MEMSPACE   BIT_0           /* Memory Space Indicator */
1899
1900  /*     PCI_BASE_2ND    32 bit  2nd Base address */
1901  #define PCI_IOBASE             0xffffff00L     /* Bit 31.. 8:  I/O Base address */
1902  #define PCI_IOSIZE             0x000000fcL     /* Bit  7.. 2:  I/O Size Requirements */
1903 -                                                                       /* Bit  1:      reserved */
1904 +                                                               /* Bit  1:      reserved */
1905  #define PCI_IOSPACE            BIT_0           /* I/O Space Indicator */
1906
1907  /*     PCI_BASE_ROM    32 bit  Expansion ROM Base Address */
1908  #define PCI_ROMBASE_MSK        0xfffe0000L     /* Bit 31..17:  ROM Base address */
1909  #define PCI_ROMBASE_SIZ        (0x1cL<<14)     /* Bit 16..14:  Treat as Base or Size */
1910  #define PCI_ROMSIZE            (0x38L<<11)     /* Bit 13..11:  ROM Size Requirements */
1911 -                                                                       /* Bit 10.. 1:  reserved */
1912 +                                                               /* Bit 10.. 1:  reserved */
1913  #define PCI_ROMEN              BIT_0           /* Address Decode enable */
1914
1915  /* Device Dependent Region */
1916  /*     PCI_OUR_REG_1           32 bit  Our Register 1 */
1917 -                                                                       /* Bit 31..29:  reserved */
1918 +                                                               /* Bit 31..29:  reserved */
1919  #define PCI_PHY_COMA   BIT_28          /* Set PHY to Coma Mode (YUKON only) */
1920  #define PCI_TEST_CAL   BIT_27          /* Test PCI buffer calib. (YUKON only) */
1921  #define PCI_EN_CAL             BIT_26          /* Enable PCI buffer calib. (YUKON only) */
1922  #define PCI_VIO                        BIT_25          /* PCI I/O Voltage, 0 = 3.3V, 1 = 5V */
1923 +/* Yukon-2 */
1924 +#define PCI_Y2_PIG_ENA         BIT_31  /* Enable Plug-in-Go (YUKON-2) */
1925 +#define PCI_Y2_DLL_DIS         BIT_30  /* Disable PCI DLL (YUKON-2) */
1926 +#define PCI_Y2_PHY2_COMA       BIT_29  /* Set PHY 2 to Coma Mode (YUKON-2) */
1927 +#define PCI_Y2_PHY1_COMA       BIT_28  /* Set PHY 1 to Coma Mode (YUKON-2) */
1928 +#define PCI_Y2_PHY2_POWD       BIT_27  /* Set PHY 2 to Power Down (YUKON-2) */
1929 +#define PCI_Y2_PHY1_POWD       BIT_26  /* Set PHY 1 to Power Down (YUKON-2) */
1930 +                                                               /* Bit 25:      reserved */
1931  #define PCI_DIS_BOOT   BIT_24          /* Disable BOOT via ROM */
1932  #define PCI_EN_IO              BIT_23          /* Mapping to I/O space */
1933  #define PCI_EN_FPROM   BIT_22          /* Enable FLASH mapping to memory */
1934 @@ -266,9 +333,10 @@
1935  #define PCI_PAGE_32K   (1L<<20)        /*              32 k pages      */
1936  #define PCI_PAGE_64K   (2L<<20)        /*              64 k pages      */
1937  #define PCI_PAGE_128K  (3L<<20)        /*              128 k pages     */
1938 -                                                                       /* Bit 19:      reserved        */
1939 -#define PCI_PAGEREG            (7L<<16)        /* Bit 18..16:  Page Register   */
1940 +                                                               /* Bit 19:      reserved        */
1941 +#define PCI_PAGEREG            (7L<<16)        /* Bit 18..16:  Page Register */
1942  #define PCI_NOTAR              BIT_15          /* No turnaround cycle */
1943 +#define PCI_PEX_LEGNAT BIT_15          /* PEX PM legacy/native mode (YUKON-2) */
1944  #define PCI_FORCE_BE   BIT_14          /* Assert all BEs on MR */
1945  #define PCI_DIS_MRL            BIT_13          /* Disable Mem Read Line */
1946  #define PCI_DIS_MRM            BIT_12          /* Disable Mem Read Multiple */
1947 @@ -278,13 +346,21 @@
1948  #define PCI_DIS_PCI_CLK        BIT_8           /* Disable PCI clock driving */
1949  #define PCI_SKEW_DAS   (0xfL<<4)       /* Bit  7.. 4:  Skew Ctrl, DAS Ext */
1950  #define PCI_SKEW_BASE  0xfL            /* Bit  3.. 0:  Skew Ctrl, Base */
1951 +#define PCI_CLS_OPT            BIT_3           /* Cache Line Size opt. PCI-X (YUKON-2) */
1952
1953 +/* Yukon-EC Ultra only */
1954 +                                                               /* Bit 14..10:  reserved */
1955 +#define PCI_PHY_LNK_TIM_MSK    (3L<<8) /* Bit  9.. 8:  GPHY Link Trigger Timer */
1956 +#define PCI_ENA_L1_EVENT       BIT_7   /* Enable PEX L1 Event */
1957 +#define PCI_ENA_GPHY_LNK       BIT_6   /* Enable PEX L1 on GPHY Link down */
1958 +#define PCI_FORCE_PEX_L1       BIT_5   /* Force to PEX L1 */
1959 +                                                               /* Bit  4.. 0:  reserved */
1960
1961  /*     PCI_OUR_REG_2           32 bit  Our Register 2 */
1962  #define PCI_VPD_WR_THR (0xffL<<24)     /* Bit 31..24:  VPD Write Threshold */
1963  #define PCI_DEV_SEL            (0x7fL<<17)     /* Bit 23..17:  EEPROM Device Select */
1964  #define PCI_VPD_ROM_SZ (7L<<14)        /* Bit 16..14:  VPD ROM Size    */
1965 -                                                                       /* Bit 13..12:  reserved        */
1966 +                                                               /* Bit 13..12:  reserved        */
1967  #define PCI_PATCH_DIR  (0xfL<<8)       /* Bit 11.. 8:  Ext Patches dir 3..0 */
1968  #define PCI_PATCH_DIR_3        BIT_11
1969  #define PCI_PATCH_DIR_2        BIT_10
1970 @@ -296,22 +372,21 @@
1971  #define PCI_EXT_PATCH_1        BIT_5
1972  #define PCI_EXT_PATCH_0        BIT_4
1973  #define PCI_EN_DUMMY_RD        BIT_3           /* Enable Dummy Read */
1974 -#define PCI_REV_DESC   BIT_2           /* Reverse Desc. Bytes */
1975 -                                                                       /* Bit  1:      reserved */
1976 +#define PCI_REV_DESC   BIT_2           /* Reverse Descriptor Bytes */
1977 +                                                               /* Bit  1:      reserved */
1978  #define PCI_USEDATA64  BIT_0           /* Use 64Bit Data bus ext */
1979
1980 -
1981 -/* Power Management Region */
1982 +/* Power Management (PM) Region */
1983  /*     PCI_PM_CAP_REG          16 bit  Power Management Capabilities */
1984 -#define PCI_PME_SUP_MSK        (0x1f<<11)      /* Bit 15..11:  PM Event Support Mask */
1985 -#define PCI_PME_D3C_SUP        BIT_15S         /* PME from D3cold Support (if Vaux) */
1986 +#define PCI_PME_SUP_MSK        (0x1f<<11)      /* Bit 15..11:  PM Event (PME) Supp. Mask */
1987 +#define PCI_PME_D3C_SUP        BIT_15S         /* PME from D3cold Support (if VAUX) */
1988  #define PCI_PME_D3H_SUP        BIT_14S         /* PME from D3hot Support */
1989  #define PCI_PME_D2_SUP BIT_13S         /* PME from D2 Support */
1990  #define PCI_PME_D1_SUP BIT_12S         /* PME from D1 Support */
1991  #define PCI_PME_D0_SUP BIT_11S         /* PME from D0 Support */
1992  #define PCI_PM_D2_SUP  BIT_10S         /* D2 Support in 33 MHz mode */
1993  #define PCI_PM_D1_SUP  BIT_9S          /* D1 Support */
1994 -                                                                       /* Bit  8.. 6:  reserved */
1995 +                                                               /* Bit  8.. 6:  reserved */
1996  #define PCI_PM_DSI             BIT_5S          /* Device Specific Initialization */
1997  #define PCI_PM_APS             BIT_4S          /* Auxialiary Power Source */
1998  #define PCI_PME_CLOCK  BIT_3S          /* PM Event Clock */
1999 @@ -322,7 +397,7 @@
2000  #define PCI_PM_DAT_SCL (3<<13)         /* Bit 14..13:  Data Reg. scaling factor */
2001  #define PCI_PM_DAT_SEL (0xf<<9)        /* Bit 12.. 9:  PM data selector field */
2002  #define PCI_PME_EN             BIT_8S          /* Enable PME# generation (YUKON only) */
2003 -                                                                       /* Bit  7.. 2:  reserved */
2004 +                                                               /* Bit  7.. 2:  reserved */
2005  #define PCI_PM_STATE_MSK       3               /* Bit  1.. 0:  Power Management State */
2006
2007  #define PCI_PM_STATE_D0                0               /* D0:  Operational (default) */
2008 @@ -333,7 +408,151 @@
2009  /* VPD Region */
2010  /*     PCI_VPD_ADR_REG         16 bit  VPD Address Register */
2011  #define PCI_VPD_FLAG   BIT_15S         /* starts VPD rd/wr cycle */
2012 -#define PCI_VPD_ADR_MSK        0x7fffL         /* Bit 14.. 0:  VPD address mask */
2013 +#define PCI_VPD_ADR_MSK        0x7fffL         /* Bit 14.. 0:  VPD Address Mask */
2014 +
2015 +/*     PCI_OUR_STATUS          32 bit  Adapter Status Register (Yukon-2) */
2016 +#define PCI_OS_PCI64B  BIT_31          /* Conventional PCI 64 bits Bus */
2017 +#define PCI_OS_PCIX            BIT_30          /* PCI-X Bus */
2018 +#define PCI_OS_MODE_MSK        (3L<<28)        /* Bit 29..28:  PCI-X Bus Mode Mask */
2019 +#define PCI_OS_PCI66M  BIT_27          /* PCI 66 MHz Bus */
2020 +#define PCI_OS_PCI_X   BIT_26          /* PCI/PCI-X Bus (0 = PEX) */
2021 +#define PCI_OS_DLLE_MSK        (3L<<24)        /* Bit 25..24:  DLL Status Indication */
2022 +#define PCI_OS_DLLR_MSK        (0xfL<<20)      /* Bit 23..20:  DLL Row Counters Values */
2023 +#define PCI_OS_DLLC_MSK        (0xfL<<16)      /* Bit 19..16:  DLL Col. Counters Values */
2024 +                                                               /* Bit 15.. 8:  reserved */
2025 +
2026 +#define PCI_OS_SPEED(val)      ((val & PCI_OS_MODE_MSK) >> 28) /* PCI-X Speed */
2027 +/* possible values for the speed field of the register */
2028 +#define PCI_OS_SPD_PCI         0               /* PCI Conventional Bus */
2029 +#define PCI_OS_SPD_X66         1               /* PCI-X 66MHz Bus */
2030 +#define PCI_OS_SPD_X100                2               /* PCI-X 100MHz Bus */
2031 +#define PCI_OS_SPD_X133                3               /* PCI-X 133MHz Bus */
2032 +
2033 +/*     PCI_OUR_REG_3           32 bit  Our Register 3 (Yukon-ECU only) */
2034 +                                                               /* Bit 31..18:  reserved */
2035 +#define P_CLK_COR_REGS_D0_DIS  BIT_17  /* Disable Clock Core Regs in D0 */
2036 +#define P_CLK_PCI_REGS_D0_DIS  BIT_16  /* Disable Clock PCI  Regs in D0 */
2037 +#define P_CLK_COR_YTB_ARB_DIS  BIT_15  /* Disable Clock YTB  Arbiter */
2038 +#define P_CLK_MAC_LNK1_D3_DIS  BIT_14  /* Disable Clock MAC  Link1 in D3 */
2039 +#define P_CLK_COR_LNK1_D0_DIS  BIT_13  /* Disable Clock Core Link1 in D0 */
2040 +#define P_CLK_MAC_LNK1_D0_DIS  BIT_12  /* Disable Clock MAC  Link1 in D0 */
2041 +#define P_CLK_COR_LNK1_D3_DIS  BIT_11  /* Disable Clock Core Link1 in D3 */
2042 +#define P_CLK_PCI_MST_ARB_DIS  BIT_10  /* Disable Clock PCI  Master Arb. */
2043 +#define P_CLK_COR_REGS_D3_DIS  BIT_9   /* Disable Clock Core Regs in D3 */
2044 +#define P_CLK_PCI_REGS_D3_DIS  BIT_8   /* Disable Clock PCI  Regs in D3 */
2045 +#define P_CLK_REF_LNK1_GM_DIS  BIT_7   /* Disable Clock Ref. Link1 GMAC */
2046 +#define P_CLK_COR_LNK1_GM_DIS  BIT_6   /* Disable Clock Core Link1 GMAC */
2047 +#define P_CLK_PCI_COMMON_DIS   BIT_5   /* Disable Clock PCI  Common */
2048 +#define P_CLK_COR_COMMON_DIS   BIT_4   /* Disable Clock Core Common */
2049 +#define P_CLK_PCI_LNK1_BMU_DIS BIT_3   /* Disable Clock PCI  Link1 BMU */
2050 +#define P_CLK_COR_LNK1_BMU_DIS BIT_2   /* Disable Clock Core Link1 BMU */
2051 +#define P_CLK_PCI_LNK1_BIU_DIS BIT_1   /* Disable Clock PCI  Link1 BIU */
2052 +#define P_CLK_COR_LNK1_BIU_DIS BIT_0   /* Disable Clock Core Link1 BIU */
2053 +
2054 +/*     PCI_OUR_REG_4           32 bit  Our Register 4 (Yukon-ECU only) */
2055 +#define P_PEX_LTSSM_STAT_MSK   (0x7fL<<25)     /* Bit 31..25:  PEX LTSSM Mask */
2056 +                                                                       /* (Link Training & Status State Machine) */
2057 +                                                               /* Bit 24:      reserved */
2058 +#define P_TIMER_VALUE_MSK              (0xffL<<16)     /* Bit 23..16:  Timer Value Mask */
2059 +#define P_FORCE_ASPM_REQUEST   BIT_15  /* Force ASPM Request (A1 only) */
2060 +                                                                               /* (Active State Power Management) */
2061 +                                                                               /* Bit 14..12: Force ASPM on Event */
2062 +#define P_ASPM_GPHY_LINK_DOWN  BIT_14  /* GPHY Link Down (A1 only) */
2063 +#define P_ASPM_INT_FIFO_EMPTY  BIT_13  /* Internal FIFO Empty (A1 only) */
2064 +#define P_ASPM_CLKRUN_REQUEST  BIT_12  /* CLKRUN Request (A1 only) */
2065 +                                                               /* Bit 11.. 8:  reserved */
2066 +#define P_ASPM_FORCE_ASPM_L1   BIT_7   /* Force ASPM L1  Enable (A1b only) */
2067 +#define P_ASPM_FORCE_ASPM_L0S  BIT_6   /* Force ASPM L0s Enable (A1b only) */
2068 +#define P_ASPM_FORCE_CLKREQ_PIN        BIT_5   /* Force CLKREQn pin low (A1b only) */
2069 +#define P_ASPM_FORCE_CLKREQ_ENA        BIT_4   /* Force CLKREQ Enable (A1b only) */
2070 +#define P_ASPM_CLKREQ_PAD_CTL  BIT_3   /* CLKREQ PAD Control (A1 only) */
2071 +#define P_ASPM_A1_MODE_SELECT  BIT_2   /* A1 Mode Select (A1 only) */
2072 +#define P_CLK_GATE_PEX_UNIT_ENA        BIT_1   /* Enable Gate PEX Unit Clock */
2073 +#define P_CLK_GATE_ROOT_COR_ENA        BIT_0   /* Enable Gate Root Core Clock */
2074 +
2075 +#define P_PEX_LTSSM_STAT(x)            (SHIFT25(x) & P_PEX_LTSSM_STAT_MSK)
2076 +#define P_PEX_LTSSM_L1_STAT            0x34
2077 +#define P_PEX_LTSSM_DET_STAT   0x01
2078 +
2079 +#define P_ASPM_CONTROL_MSK     (P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN | \
2080 +                                                        P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY)
2081 +
2082 +/*     PCI_OUR_REG_5           32 bit  Our Register 5 (Yukon-ECU only) */
2083 +                                                               /* Bit 31..27:  reserved */
2084 +                                                                               /* Bit 26..16: Release Clock on Event */
2085 +#define P_REL_PCIE_RST_DE_ASS  BIT_26  /* PCIe Reset De-Asserted */
2086 +#define P_REL_GPHY_REC_PACKET  BIT_25  /* GPHY Received Packet */
2087 +#define P_REL_INT_FIFO_N_EMPTY BIT_24  /* Internal FIFO Not Empty */
2088 +#define P_REL_MAIN_PWR_AVAIL   BIT_23  /* Main Power Available */
2089 +#define P_REL_CLKRUN_REQ_REL   BIT_22  /* CLKRUN Request Release */
2090 +#define P_REL_PCIE_RESET_ASS   BIT_21  /* PCIe Reset Asserted */
2091 +#define P_REL_PME_ASSERTED             BIT_20  /* PME Asserted */
2092 +#define P_REL_PCIE_EXIT_L1_ST  BIT_19  /* PCIe Exit L1 State */
2093 +#define P_REL_LOADER_NOT_FIN   BIT_18  /* EPROM Loader Not Finished */
2094 +#define P_REL_PCIE_RX_EX_IDLE  BIT_17  /* PCIe Rx Exit Electrical Idle State */
2095 +#define P_REL_GPHY_LINK_UP             BIT_16  /* GPHY Link Up */
2096 +                                                               /* Bit 15..11:  reserved */
2097 +                                                                               /* Bit 10.. 0: Mask for Gate Clock */
2098 +#define P_GAT_PCIE_RST_DE_ASS  BIT_10  /* PCIe Reset De-Asserted */
2099 +#define P_GAT_GPHY_N_REC_PACKET        BIT_9   /* GPHY Not Received Packet */
2100 +#define P_GAT_INT_FIFO_EMPTY   BIT_8   /* Internal FIFO Empty */
2101 +#define P_GAT_MAIN_PWR_N_AVAIL BIT_7   /* Main Power Not Available */
2102 +#define P_GAT_CLKRUN_REQ_REL   BIT_6   /* CLKRUN Not Requested */
2103 +#define P_GAT_PCIE_RESET_ASS   BIT_5   /* PCIe Reset Asserted */
2104 +#define P_GAT_PME_DE_ASSERTED  BIT_4   /* PME De-Asserted */
2105 +#define P_GAT_PCIE_ENTER_L1_ST BIT_3   /* PCIe Enter L1 State */
2106 +#define P_GAT_LOADER_FINISHED  BIT_2   /* EPROM Loader Finished */
2107 +#define P_GAT_PCIE_RX_EL_IDLE  BIT_1   /* PCIe Rx Electrical Idle State */
2108 +#define P_GAT_GPHY_LINK_DOWN   BIT_0   /* GPHY Link Down */
2109 +
2110 +/*     PEX_DEV_CTRL                    16 bit  PEX Device Control (Yukon-2) */
2111 +                                                               /* Bit 15       reserved */
2112 +#define PEX_DC_MAX_RRS_MSK     (7<<12) /* Bit 14..12:  Max. Read Request Size */
2113 +#define PEX_DC_EN_NO_SNOOP     BIT_11S /* Enable No Snoop */
2114 +#define PEX_DC_EN_AUX_POW      BIT_10S /* Enable AUX Power */
2115 +#define PEX_DC_EN_PHANTOM      BIT_9S  /* Enable Phantom Functions */
2116 +#define PEX_DC_EN_EXT_TAG      BIT_8S  /* Enable Extended Tag Field */
2117 +#define PEX_DC_MAX_PLS_MSK     (7<<5)  /* Bit  7.. 5:  Max. Payload Size Mask */
2118 +#define PEX_DC_EN_REL_ORD      BIT_4S  /* Enable Relaxed Ordering */
2119 +#define PEX_DC_EN_UNS_RQ_RP    BIT_3S  /* Enable Unsupported Request Reporting */
2120 +#define PEX_DC_EN_FAT_ER_RP    BIT_2S  /* Enable Fatal Error Reporting */
2121 +#define PEX_DC_EN_NFA_ER_RP    BIT_1S  /* Enable Non-Fatal Error Reporting */
2122 +#define PEX_DC_EN_COR_ER_RP    BIT_0S  /* Enable Correctable Error Reporting */
2123 +
2124 +#define PEX_DC_MAX_RD_RQ_SIZE(x)       (SHIFT12(x) & PEX_DC_MAX_RRS_MSK)
2125 +
2126 +/*     PEX_LNK_CAP                     32 bit  PEX Link Capabilities */
2127 +#define PEX_CAP_MAX_WI_MSK     (0x3f<<4)       /* Bit  9.. 4:  Max. Link Width Mask */
2128 +#define PEX_CAP_MAX_SP_MSK     0x0f    /* Bit  3.. 0:  Max. Link Speed Mask */
2129 +
2130 +/*     PEX_LNK_CTRL                    16 bit  PEX Link Control (Yukon-2) */
2131 +#define PEX_LC_CLK_PM_ENA      BIT_8S  /* Enable Clock Power Management (CLKREQ) */
2132 +
2133 +/*     PEX_LNK_STAT                    16 bit  PEX Link Status (Yukon-2) */
2134 +                                                               /* Bit 15..13   reserved */
2135 +#define PEX_LS_SLOT_CLK_CFG    BIT_12S /* Slot Clock Config */
2136 +#define PEX_LS_LINK_TRAIN      BIT_11S /* Link Training */
2137 +#define PEX_LS_TRAIN_ERROR     BIT_10S /* Training Error */
2138 +#define PEX_LS_LINK_WI_MSK     (0x3f<<4)       /* Bit  9.. 4:  Neg. Link Width Mask */
2139 +#define PEX_LS_LINK_SP_MSK     0x0f    /* Bit  3.. 0:  Link Speed Mask */
2140 +
2141 +/*     PEX_UNC_ERR_STAT                16 bit  PEX Uncorrectable Errors Status (Yukon-2) */
2142 +                                                               /* Bit 31..21   reserved */
2143 +#define PEX_UNSUP_REQ  BIT_20          /* Unsupported Request Error */
2144 +                                                                       /* ECRC Error (not supported) */
2145 +#define PEX_MALFOR_TLP BIT_18          /* Malformed TLP */
2146 +#define PEX_RX_OV              BIT_17          /* Receiver Overflow (not supported) */
2147 +#define PEX_UNEXP_COMP BIT_16          /* Unexpected Completion */
2148 +                                                                       /* Completer Abort (not supported) */
2149 +#define PEX_COMP_TO            BIT_14          /* Completion Timeout */
2150 +#define PEX_FLOW_CTRL_P        BIT_13          /* Flow Control Protocol Error */
2151 +#define PEX_POIS_TLP   BIT_12          /* Poisoned TLP */
2152 +                                                               /* Bit 11.. 5:  reserved */
2153 +#define PEX_DATA_LINK_P BIT_4          /* Data Link Protocol Error */
2154 +                                                               /* Bit  3.. 1:  reserved */
2155 +                                                                       /* Training Error (not supported) */
2156 +
2157 +#define PEX_FATAL_ERRORS       (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P)
2158
2159  /*     Control Register File (Address Map) */
2160
2161 @@ -342,15 +561,21 @@
2162   */
2163  #define B0_RAP                 0x0000  /*  8 bit       Register Address Port */
2164         /* 0x0001 - 0x0003:     reserved */
2165 -#define B0_CTST                        0x0004  /* 16 bit       Control/Status register */
2166 -#define B0_LED                 0x0006  /*  8 Bit       LED register */
2167 +#define B0_CTST                        0x0004  /* 16 bit       Control/Status Register */
2168 +#define B0_LED                 0x0006  /*  8 Bit       LED Register */
2169  #define B0_POWER_CTRL  0x0007  /*  8 Bit       Power Control reg (YUKON only) */
2170  #define B0_ISRC                        0x0008  /* 32 bit       Interrupt Source Register */
2171  #define B0_IMSK                        0x000c  /* 32 bit       Interrupt Mask Register */
2172  #define B0_HWE_ISRC            0x0010  /* 32 bit       HW Error Interrupt Src Reg */
2173  #define B0_HWE_IMSK            0x0014  /* 32 bit       HW Error Interrupt Mask Reg */
2174 -#define B0_SP_ISRC             0x0018  /* 32 bit       Special Interrupt Source Reg */
2175 -       /* 0x001c:              reserved */
2176 +#define B0_SP_ISRC             0x0018  /* 32 bit       Special Interrupt Source Reg 1 */
2177 +
2178 +/* Special ISR registers (Yukon-2 only) */
2179 +#define B0_Y2_SP_ISRC2 0x001c  /* 32 bit       Special Interrupt Source Reg 2 */
2180 +#define B0_Y2_SP_ISRC3 0x0020  /* 32 bit       Special Interrupt Source Reg 3 */
2181 +#define B0_Y2_SP_EISR  0x0024  /* 32 bit       Enter ISR Register */
2182 +#define B0_Y2_SP_LISR  0x0028  /* 32 bit       Leave ISR Register */
2183 +#define B0_Y2_SP_ICR   0x002c  /* 32 bit       Interrupt Control Register */
2184
2185  /* B0 XMAC 1 registers (GENESIS only) */
2186  #define B0_XM1_IMSK            0x0020  /* 16 bit r/w   XMAC 1 Interrupt Mask Register*/
2187 @@ -372,7 +597,7 @@
2188  #define B0_XM2_PHY_DATA 0x0054 /* 16 bit r/w   XMAC 2 PHY Data Register */
2189         /* 0x0056 - 0x005f:     reserved */
2190
2191 -/* BMU Control Status Registers */
2192 +/* BMU Control Status Registers (Yukon and Genesis) */
2193  #define B0_R1_CSR              0x0060  /* 32 bit       BMU Ctrl/Stat Rx Queue 1 */
2194  #define B0_R2_CSR              0x0064  /* 32 bit       BMU Ctrl/Stat Rx Queue 2 */
2195  #define B0_XS1_CSR             0x0068  /* 32 bit       BMU Ctrl/Stat Sync Tx Queue 1 */
2196 @@ -390,7 +615,7 @@
2197  /*
2198   *     Bank 2
2199   */
2200 -/* NA reg = 48 bit Network Address Register, 3x16 or 8x8 bit readable */
2201 +/* NA reg = 48 bit Network Address Register, 3x16 or 6x8 bit readable */
2202  #define B2_MAC_1               0x0100  /* NA reg        MAC Address 1 */
2203         /* 0x0106 - 0x0107:     reserved */
2204  #define B2_MAC_2               0x0108  /* NA reg        MAC Address 2 */
2205 @@ -400,14 +625,23 @@
2206  #define B2_CONN_TYP            0x0118  /*  8 bit       Connector type */
2207  #define B2_PMD_TYP             0x0119  /*  8 bit       PMD type */
2208  #define B2_MAC_CFG             0x011a  /*  8 bit       MAC Configuration / Chip Revision */
2209 -#define B2_CHIP_ID             0x011b  /*  8 bit       Chip Identification Number */
2210 -       /* Eprom registers are currently of no use */
2211 +#define B2_CHIP_ID             0x011b  /*  8 bit       Chip Identification Number */
2212 +       /* Eprom registers */
2213  #define B2_E_0                 0x011c  /*  8 bit       EPROM Byte 0 (ext. SRAM size */
2214 +/* Yukon and Genesis */
2215  #define B2_E_1                 0x011d  /*  8 bit       EPROM Byte 1 (PHY type) */
2216  #define B2_E_2                 0x011e  /*  8 bit       EPROM Byte 2 */
2217 +/* Yukon-2 */
2218 +#define B2_Y2_CLK_GATE 0x011d  /*  8 bit       Clock Gating (Yukon-2) */
2219 +#define B2_Y2_HW_RES   0x011e  /*  8 bit       HW Resources (Yukon-2) */
2220 +
2221  #define B2_E_3                 0x011f  /*  8 bit       EPROM Byte 3 */
2222 +
2223 +/* Yukon and Genesis */
2224  #define B2_FAR                 0x0120  /* 32 bit       Flash-Prom Addr Reg/Cnt */
2225  #define B2_FDP                 0x0124  /*  8 bit       Flash-Prom Data Port */
2226 +/* Yukon-2 */
2227 +#define B2_Y2_CLK_CTRL 0x0120  /* 32 bit       Core Clock Frequency Control */
2228         /* 0x0125 - 0x0127:     reserved */
2229  #define B2_LD_CTRL             0x0128  /*  8 bit       EPROM loader control register */
2230  #define B2_LD_TEST             0x0129  /*  8 bit       EPROM loader test register */
2231 @@ -439,6 +673,10 @@
2232  #define B2_BSC_CTRL            0x0178  /*  8 bit       Blink Source Counter Control */
2233  #define B2_BSC_STAT            0x0179  /*  8 bit       Blink Source Counter Status */
2234  #define B2_BSC_TST             0x017a  /* 16 bit       Blink Source Counter Test Reg */
2235 +
2236 +/* Yukon-2 */
2237 +#define Y2_PEX_PHY_DATA        0x0170  /* 16 bit       PEX PHY Data Register */
2238 +#define Y2_PEX_PHY_ADDR        0x0172  /* 16 bit       PEX PHY Address Register */
2239         /* 0x017c - 0x017f:     reserved */
2240
2241  /*
2242 @@ -448,9 +686,14 @@
2243  #define B3_RAM_ADDR            0x0180  /* 32 bit       RAM Address, to read or write */
2244  #define B3_RAM_DATA_LO 0x0184  /* 32 bit       RAM Data Word (low dWord) */
2245  #define B3_RAM_DATA_HI 0x0188  /* 32 bit       RAM Data Word (high dWord) */
2246 +#define B3_RAM_PARITY  0x018c  /*  8 bit       RAM Parity (Yukon-ECU A1) */
2247 +
2248 +#define SELECT_RAM_BUFFER(rb, addr) (addr | (rb << 6)) /* Yukon-2 only */
2249 +
2250         /* 0x018c - 0x018f:     reserved */
2251
2252  /* RAM Interface Registers */
2253 +/* Yukon-2: use SELECT_RAM_BUFFER() to access the RAM buffer */
2254  /*
2255   * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
2256   * not usable in SW. Please notice these are NOT real timeouts, these are
2257 @@ -517,8 +760,8 @@
2258         /* 0x01ea - 0x01eb:     reserved */
2259  #define B3_PA_TOVAL_TX2        0x01ec  /* 16 bit       Timeout Val Tx Path MAC 2 */
2260         /* 0x01ee - 0x01ef:     reserved */
2261 -#define B3_PA_CTRL     0x01f0  /* 16 bit       Packet Arbiter Ctrl Register */
2262 -#define B3_PA_TEST     0x01f2  /* 16 bit       Packet Arbiter Test Register */
2263 +#define B3_PA_CTRL             0x01f0  /* 16 bit       Packet Arbiter Ctrl Register */
2264 +#define B3_PA_TEST             0x01f2  /* 16 bit       Packet Arbiter Test Register */
2265         /* 0x01f4 - 0x01ff:     reserved */
2266
2267  /*
2268 @@ -532,7 +775,16 @@
2269  #define TXA_CTRL               0x0210  /*  8 bit       Tx Arbiter Control Register */
2270  #define TXA_TEST               0x0211  /*  8 bit       Tx Arbiter Test Register */
2271  #define TXA_STAT               0x0212  /*  8 bit       Tx Arbiter Status Register */
2272 -       /* 0x0213 - 0x027f:     reserved */
2273 +       /* 0x0213 - 0x021f:     reserved */
2274 +
2275 +       /* RSS key registers for Yukon-2 Family */
2276 +#define B4_RSS_KEY             0x0220  /* 4x32 bit RSS Key register (Yukon-2) */
2277 +       /* RSS key register offsets */
2278 +#define KEY_IDX_0               0              /* offset for location of KEY 0 */
2279 +#define KEY_IDX_1               4              /* offset for location of KEY 1 */
2280 +#define KEY_IDX_2               8              /* offset for location of KEY 2 */
2281 +#define KEY_IDX_3              12              /* offset for location of KEY 3 */
2282 +
2283         /* 0x0280 - 0x0292:     MAC 2 */
2284         /* 0x0213 - 0x027f:     reserved */
2285
2286 @@ -556,10 +808,10 @@
2287
2288  /* Queue Register Offsets, use Q_ADDR() to access */
2289  #define Q_D            0x00    /* 8*32 bit     Current Descriptor */
2290 -#define Q_DA_L 0x20    /* 32 bit       Current Descriptor Address Low dWord */
2291 -#define Q_DA_H 0x24    /* 32 bit       Current Descriptor Address High dWord */
2292 -#define Q_AC_L 0x28    /* 32 bit       Current Address Counter Low dWord */
2293 -#define Q_AC_H 0x2c    /* 32 bit       Current Address Counter High dWord */
2294 +#define Q_DA_L 0x20    /* 32 bit       Current Descriptor Address Low DWord */
2295 +#define Q_DA_H 0x24    /* 32 bit       Current Descriptor Address High DWord */
2296 +#define Q_AC_L 0x28    /* 32 bit       Current Address Counter Low DWord */
2297 +#define Q_AC_H 0x2c    /* 32 bit       Current Address Counter High DWord */
2298  #define Q_BC   0x30    /* 32 bit       Current Byte Counter */
2299  #define Q_CSR  0x34    /* 32 bit       BMU Control/Status Register */
2300  #define Q_F            0x38    /* 32 bit       Flag Register */
2301 @@ -570,8 +822,56 @@
2302  #define Q_T1_SV        0x3f    /*  8 bit       Test Register 1 Supervisor SM */
2303  #define Q_T2   0x40    /* 32 bit       Test Register 2 */
2304  #define Q_T3   0x44    /* 32 bit       Test Register 3 */
2305 +
2306 +/* Yukon-2 */
2307 +#define Q_DONE         0x24    /* 16 bit       Done Index */
2308 +
2309 +#define Q_WM           0x40    /* 16 bit       FIFO Watermark */
2310 +#define Q_AL           0x42    /*  8 bit       FIFO Alignment */
2311 +       /* 0x43:        reserved */
2312 +/* RX Queue */
2313 +#define Q_RX_RSP       0x44    /* 16 bit       FIFO Read Shadow Pointer */
2314 +#define Q_RX_RSL       0x46    /*  8 bit       FIFO Read Shadow Level */
2315 +       /* 0x47:        reserved */
2316 +#define Q_RX_RP                0x48    /*  8 bit       FIFO Read Pointer */
2317 +       /* 0x49:        reserved */
2318 +#define Q_RX_RL                0x4a    /*  8 bit       FIFO Read Level */
2319 +       /* 0x4b:        reserved */
2320 +#define Q_RX_WP                0x4c    /*  8 bit       FIFO Write Pointer */
2321 +#define Q_RX_WSP       0x4d    /*  8 bit       FIFO Write Shadow Pointer */
2322 +#define Q_RX_WL                0x4e    /*  8 bit       FIFO Write Level */
2323 +#define Q_RX_WSL       0x4f    /*  8 bit       FIFO Write Shadow Level */
2324 +/* TX Queue */
2325 +#define Q_TX_WSP       0x44    /* 16 bit       FIFO Write Shadow Pointer */
2326 +#define Q_TX_WSL       0x46    /*  8 bit       FIFO Write Shadow Level */
2327 +       /* 0x47:        reserved */
2328 +#define Q_TX_WP                0x48    /*  8 bit       FIFO Write Pointer */
2329 +       /* 0x49:        reserved */
2330 +#define Q_TX_WL                0x4a    /*  8 bit       FIFO Write Level */
2331 +       /* 0x4b:        reserved */
2332 +#define Q_TX_RP                0x4c    /*  8 bit       FIFO Read Pointer */
2333 +       /* 0x4d:        reserved */
2334 +#define Q_TX_RL                0x4e    /*  8 bit       FIFO Read Level */
2335 +       /* 0x4f:        reserved */
2336 +
2337         /* 0x48 - 0x7f: reserved */
2338
2339 +/* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/
2340 +#define Y2_B8_PREF_REGS                        0x0450
2341 +
2342 +#define PREF_UNIT_CTRL_REG             0x00    /* 32 bit       Prefetch Control register */
2343 +#define PREF_UNIT_LAST_IDX_REG 0x04    /* 16 bit       Last Index */
2344 +#define PREF_UNIT_ADDR_LOW_REG 0x08    /* 32 bit       List start addr, low part */
2345 +#define PREF_UNIT_ADDR_HI_REG  0x0c    /* 32 bit       List start addr, high part*/
2346 +#define PREF_UNIT_GET_IDX_REG  0x10    /* 16 bit       Get Index */
2347 +#define PREF_UNIT_PUT_IDX_REG  0x14    /* 16 bit       Put Index */
2348 +#define PREF_UNIT_FIFO_WP_REG  0x20    /*  8 bit       FIFO write pointer */
2349 +#define PREF_UNIT_FIFO_RP_REG  0x24    /*  8 bit       FIFO read pointer */
2350 +#define PREF_UNIT_FIFO_WM_REG  0x28    /*  8 bit       FIFO watermark */
2351 +#define PREF_UNIT_FIFO_LEV_REG 0x2c    /*  8 bit       FIFO level */
2352 +
2353 +#define PREF_UNIT_MASK_IDX             0x0fff
2354 +
2355  /*
2356   *     Bank 16 - 23
2357   */
2358 @@ -583,17 +883,17 @@
2359  #define RB_END                 0x04    /* 32 bit       RAM Buffer End Address */
2360  #define RB_WP                  0x08    /* 32 bit       RAM Buffer Write Pointer */
2361  #define RB_RP                  0x0c    /* 32 bit       RAM Buffer Read Pointer */
2362 -#define RB_RX_UTPP             0x10    /* 32 bit       Rx Upper Threshold, Pause Pack */
2363 -#define RB_RX_LTPP             0x14    /* 32 bit       Rx Lower Threshold, Pause Pack */
2364 +#define RB_RX_UTPP             0x10    /* 32 bit       Rx Upper Threshold, Pause Packet */
2365 +#define RB_RX_LTPP             0x14    /* 32 bit       Rx Lower Threshold, Pause Packet */
2366  #define RB_RX_UTHP             0x18    /* 32 bit       Rx Upper Threshold, High Prio */
2367  #define RB_RX_LTHP             0x1c    /* 32 bit       Rx Lower Threshold, High Prio */
2368         /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
2369  #define RB_PC                  0x20    /* 32 bit       RAM Buffer Packet Counter */
2370  #define RB_LEV                 0x24    /* 32 bit       RAM Buffer Level Register */
2371 -#define RB_CTRL                        0x28    /*  8 bit       RAM Buffer Control Register */
2372 +#define RB_CTRL                        0x28    /* 32 bit       RAM Buffer Control Register */
2373  #define RB_TST1                        0x29    /*  8 bit       RAM Buffer Test Register 1 */
2374 -#define RB_TST2                        0x2A    /*  8 bit       RAM Buffer Test Register 2 */
2375 -       /* 0x2c - 0x7f: reserved */
2376 +#define RB_TST2                        0x2a    /*  8 bit       RAM Buffer Test Register 2 */
2377 +       /* 0x2b - 0x7f: reserved */
2378
2379  /*
2380   *     Bank 24
2381 @@ -603,7 +903,7 @@
2382   * use MR_ADDR() to access
2383   */
2384  #define RX_MFF_EA              0x0c00  /* 32 bit       Receive MAC FIFO End Address */
2385 -#define RX_MFF_WP              0x0c04  /* 32 bit       Receive MAC FIFO Write Pointer */
2386 +#define RX_MFF_WP              0x0c04  /* 32 bit       Receive MAC FIFO Write Pointer */
2387         /* 0x0c08 - 0x0c0b:     reserved */
2388  #define RX_MFF_RP              0x0c0c  /* 32 bit       Receive MAC FIFO Read Pointer */
2389  #define RX_MFF_PC              0x0c10  /* 32 bit       Receive MAC FIFO Packet Cnt */
2390 @@ -628,20 +928,23 @@
2391  #define LNK_LED_REG            0x0c3c  /*  8 bit       Link LED Register */
2392         /* 0x0c3d - 0x0c3f:     reserved */
2393
2394 -/* Receive GMAC FIFO (YUKON only), use MR_ADDR() to access */
2395 +/* Receive GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
2396  #define RX_GMF_EA              0x0c40  /* 32 bit       Rx GMAC FIFO End Address */
2397  #define RX_GMF_AF_THR  0x0c44  /* 32 bit       Rx GMAC FIFO Almost Full Thresh. */
2398  #define RX_GMF_CTRL_T  0x0c48  /* 32 bit       Rx GMAC FIFO Control/Test */
2399  #define RX_GMF_FL_MSK  0x0c4c  /* 32 bit       Rx GMAC FIFO Flush Mask */
2400  #define RX_GMF_FL_THR  0x0c50  /* 32 bit       Rx GMAC FIFO Flush Threshold */
2401 -       /* 0x0c54 - 0x0c5f:     reserved */
2402 -#define RX_GMF_WP              0x0c60  /* 32 bit       Rx GMAC FIFO Write Pointer */
2403 +#define RX_GMF_TR_THR  0x0c54  /* 32 bit       Rx Truncation Threshold (Yukon-2) */
2404 +#define RX_GMF_UP_THR  0x0c58  /* 16 bit       Rx Upper Pause Thr (Yukon-EC_U) */
2405 +#define RX_GMF_LP_THR  0x0c5a  /* 16 bit       Rx Lower Pause Thr (Yukon-EC_U) */
2406 +#define RX_GMF_VLAN            0x0c5c  /* 32 bit       Rx VLAN Type Register (Yukon-2) */
2407 +#define RX_GMF_WP              0x0c60  /* 32 bit       Rx GMAC FIFO Write Pointer */
2408         /* 0x0c64 - 0x0c67:     reserved */
2409 -#define RX_GMF_WLEV            0x0c68  /* 32 bit       Rx GMAC FIFO Write Level */
2410 +#define RX_GMF_WLEV            0x0c68  /* 32 bit       Rx GMAC FIFO Write Level */
2411         /* 0x0c6c - 0x0c6f:     reserved */
2412 -#define RX_GMF_RP              0x0c70  /* 32 bit       Rx GMAC FIFO Read Pointer */
2413 +#define RX_GMF_RP              0x0c70  /* 32 bit       Rx GMAC FIFO Read Pointer */
2414         /* 0x0c74 - 0x0c77:     reserved */
2415 -#define RX_GMF_RLEV            0x0c78  /* 32 bit       Rx GMAC FIFO Read Level */
2416 +#define RX_GMF_RLEV            0x0c78  /* 32 bit       Rx GMAC FIFO Read Level */
2417         /* 0x0c7c - 0x0c7f:     reserved */
2418
2419  /*
2420 @@ -658,7 +961,7 @@
2421   * use MR_ADDR() to access
2422   */
2423  #define TX_MFF_EA              0x0d00  /* 32 bit       Transmit MAC FIFO End Address */
2424 -#define TX_MFF_WP              0x0d04  /* 32 bit       Transmit MAC FIFO WR Pointer */
2425 +#define TX_MFF_WP              0x0d04  /* 32 bit       Transmit MAC FIFO WR Pointer */
2426  #define TX_MFF_WSP             0x0d08  /* 32 bit       Transmit MAC FIFO WR Shadow Ptr */
2427  #define TX_MFF_RP              0x0d0c  /* 32 bit       Transmit MAC FIFO RD Pointer */
2428  #define TX_MFF_PC              0x0d10  /* 32 bit       Transmit MAC FIFO Packet Cnt */
2429 @@ -676,18 +979,19 @@
2430  #define TX_LED_TST             0x0d29  /*  8 bit       Transmit LED Cnt Test Reg */
2431         /* 0x0d2a - 0x0d3f:     reserved */
2432
2433 -/* Transmit GMAC FIFO (YUKON only), use MR_ADDR() to access */
2434 +/* Transmit GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
2435  #define TX_GMF_EA              0x0d40  /* 32 bit       Tx GMAC FIFO End Address */
2436 -#define TX_GMF_AE_THR  0x0d44  /* 32 bit       Tx GMAC FIFO Almost Empty Thresh.*/
2437 +#define TX_GMF_AE_THR  0x0d44  /* 32 bit       Tx GMAC FIFO Almost Empty Thresh. */
2438  #define TX_GMF_CTRL_T  0x0d48  /* 32 bit       Tx GMAC FIFO Control/Test */
2439 -       /* 0x0d4c - 0x0d5f:     reserved */
2440 -#define TX_GMF_WP              0x0d60  /* 32 bit       Tx GMAC FIFO Write Pointer */
2441 -#define TX_GMF_WSP             0x0d64  /* 32 bit       Tx GMAC FIFO Write Shadow Ptr. */
2442 -#define TX_GMF_WLEV            0x0d68  /* 32 bit       Tx GMAC FIFO Write Level */
2443 +       /* 0x0d4c - 0x0d5b:     reserved */
2444 +#define TX_GMF_VLAN            0x0d5c  /* 32 bit       Tx VLAN Type Register (Yukon-2) */
2445 +#define TX_GMF_WP              0x0d60  /* 32 bit       Tx GMAC FIFO Write Pointer */
2446 +#define TX_GMF_WSP             0x0d64  /* 32 bit       Tx GMAC FIFO Write Shadow Pointer */
2447 +#define TX_GMF_WLEV            0x0d68  /* 32 bit       Tx GMAC FIFO Write Level */
2448         /* 0x0d6c - 0x0d6f:     reserved */
2449 -#define TX_GMF_RP              0x0d70  /* 32 bit       Tx GMAC FIFO Read Pointer */
2450 -#define TX_GMF_RSTP            0x0d74  /* 32 bit       Tx GMAC FIFO Restart Pointer */
2451 -#define TX_GMF_RLEV            0x0d78  /* 32 bit       Tx GMAC FIFO Read Level */
2452 +#define TX_GMF_RP              0x0d70  /* 32 bit       Tx GMAC FIFO Read Pointer */
2453 +#define TX_GMF_RSTP            0x0d74  /* 32 bit       Tx GMAC FIFO Restart Pointer */
2454 +#define TX_GMF_RLEV            0x0d78  /* 32 bit       Tx GMAC FIFO Read Level */
2455         /* 0x0d7c - 0x0d7f:     reserved */
2456
2457  /*
2458 @@ -713,12 +1017,84 @@
2459  #define GMAC_TI_ST_CTRL        0x0e18  /*  8 bit       Time Stamp Timer Ctrl Reg */
2460         /* 0x0e19:      reserved */
2461  #define GMAC_TI_ST_TST 0x0e1a  /*  8 bit       Time Stamp Timer Test Reg */
2462 -       /* 0x0e1b - 0x0e7f:     reserved */
2463 +       /* 0x0e1b - 0x0e1f:     reserved */
2464 +
2465 +/* Polling Unit Registers (Yukon-2 only) */
2466 +#define POLL_CTRL                      0x0e20  /* 32 bit       Polling Unit Control Reg */
2467 +#define POLL_LAST_IDX          0x0e24  /* 16 bit       Polling Unit List Last Index */
2468 +       /* 0x0e26 - 0x0e27:     reserved */
2469 +#define POLL_LIST_ADDR_LO      0x0e28  /* 32 bit       Poll. List Start Addr (low) */
2470 +#define POLL_LIST_ADDR_HI      0x0e2c  /* 32 bit       Poll. List Start Addr (high) */
2471 +       /* 0x0e30 - 0x0e3f:     reserved */
2472 +
2473 +/* ASF Subsystem Registers (Yukon-2 only) */
2474 +#define B28_Y2_SMB_CONFIG      0x0e40  /* 32 bit       ASF SMBus Config Register */
2475 +#define B28_Y2_SMB_CSD_REG     0x0e44  /* 32 bit       ASF SMB Control/Status/Data */
2476 +       /* 0x0e48 - 0x0e5f: reserved */
2477 +#define B28_Y2_ASF_IRQ_V_BASE  0x0e60  /* 32 bit       ASF IRQ Vector Base */
2478 +       /* 0x0e64 - 0x0e67: reserved */
2479 +#define B28_Y2_ASF_STAT_CMD    0x0e68  /* 32 bit       ASF Status and Command Reg */
2480 +#define B28_Y2_ASF_HOST_COM    0x0e6c  /* 32 bit       ASF Host Communication Reg */
2481 +#define B28_Y2_DATA_REG_1      0x0e70  /* 32 bit       ASF/Host Data Register 1 */
2482 +#define B28_Y2_DATA_REG_2      0x0e74  /* 32 bit       ASF/Host Data Register 2 */
2483 +#define B28_Y2_DATA_REG_3      0x0e78  /* 32 bit       ASF/Host Data Register 3 */
2484 +#define B28_Y2_DATA_REG_4      0x0e7c  /* 32 bit       ASF/Host Data Register 4 */
2485
2486  /*
2487   *     Bank 29
2488   */
2489 -       /* 0x0e80 - 0x0efc:     reserved */
2490 +
2491 +/* Status BMU Registers (Yukon-2 only)*/
2492 +#define STAT_CTRL                      0x0e80  /* 32 bit       Status BMU Control Reg */
2493 +#define STAT_LAST_IDX          0x0e84  /* 16 bit       Status BMU Last Index */
2494 +       /* 0x0e85 - 0x0e86:     reserved */
2495 +#define STAT_LIST_ADDR_LO      0x0e88  /* 32 bit       Status List Start Addr (low) */
2496 +#define STAT_LIST_ADDR_HI      0x0e8c  /* 32 bit       Status List Start Addr (high) */
2497 +#define STAT_TXA1_RIDX         0x0e90  /* 16 bit       Status TxA1 Report Index Reg */
2498 +#define STAT_TXS1_RIDX         0x0e92  /* 16 bit       Status TxS1 Report Index Reg */
2499 +#define STAT_TXA2_RIDX         0x0e94  /* 16 bit       Status TxA2 Report Index Reg */
2500 +#define STAT_TXS2_RIDX         0x0e96  /* 16 bit       Status TxS2 Report Index Reg */
2501 +#define STAT_TX_IDX_TH         0x0e98  /* 16 bit       Status Tx Index Threshold Reg */
2502 +       /* 0x0e9a - 0x0e9b:     reserved */
2503 +#define STAT_PUT_IDX           0x0e9c  /* 16 bit       Status Put Index Reg */
2504 +       /* 0x0e9e - 0x0e9f:     reserved */
2505 +
2506 +/* FIFO Control/Status Registers (Yukon-2 only) */
2507 +#define STAT_FIFO_WP           0x0ea0  /*  8 bit       Status FIFO Write Pointer Reg */
2508 +       /* 0x0ea1 - 0x0ea3:     reserved */
2509 +#define STAT_FIFO_RP           0x0ea4  /*  8 bit       Status FIFO Read Pointer Reg */
2510 +       /* 0x0ea5:      reserved */
2511 +#define STAT_FIFO_RSP          0x0ea6  /*  8 bit       Status FIFO Read Shadow Ptr */
2512 +       /* 0x0ea7:      reserved */
2513 +#define STAT_FIFO_LEVEL                0x0ea8  /*  8 bit       Status FIFO Level Reg */
2514 +       /* 0x0ea9:      reserved */
2515 +#define STAT_FIFO_SHLVL                0x0eaa  /*  8 bit       Status FIFO Shadow Level Reg */
2516 +       /* 0x0eab:      reserved */
2517 +#define STAT_FIFO_WM           0x0eac  /*  8 bit       Status FIFO Watermark Reg */
2518 +#define STAT_FIFO_ISR_WM       0x0ead  /*  8 bit       Status FIFO ISR Watermark Reg */
2519 +       /* 0x0eae - 0x0eaf:     reserved */
2520 +
2521 +/* Level and ISR Timer Registers (Yukon-2 only) */
2522 +#define STAT_LEV_TIMER_INI     0x0eb0  /* 32 bit       Level Timer Init. Value Reg */
2523 +#define STAT_LEV_TIMER_CNT     0x0eb4  /* 32 bit       Level Timer Counter Reg */
2524 +#define STAT_LEV_TIMER_CTRL    0x0eb8  /*  8 bit       Level Timer Control Reg */
2525 +#define STAT_LEV_TIMER_TEST    0x0eb9  /*  8 bit       Level Timer Test Reg */
2526 +       /* 0x0eba - 0x0ebf:     reserved */
2527 +#define STAT_TX_TIMER_INI      0x0ec0  /* 32 bit       Tx Timer Init. Value Reg */
2528 +#define STAT_TX_TIMER_CNT      0x0ec4  /* 32 bit       Tx Timer Counter Reg */
2529 +#define STAT_TX_TIMER_CTRL     0x0ec8  /*  8 bit       Tx Timer Control Reg */
2530 +#define STAT_TX_TIMER_TEST     0x0ec9  /*  8 bit       Tx Timer Test Reg */
2531 +       /* 0x0eca - 0x0ecf:     reserved */
2532 +#define STAT_ISR_TIMER_INI     0x0ed0  /* 32 bit       ISR Timer Init. Value Reg */
2533 +#define STAT_ISR_TIMER_CNT     0x0ed4  /* 32 bit       ISR Timer Counter Reg */
2534 +#define STAT_ISR_TIMER_CTRL    0x0ed8  /*  8 bit       ISR Timer Control Reg */
2535 +#define STAT_ISR_TIMER_TEST    0x0ed9  /*  8 bit       ISR Timer Test Reg */
2536 +       /* 0x0eda - 0x0eff:     reserved */
2537 +
2538 +#define ST_LAST_IDX_MASK       0x007f  /* Last Index Mask */
2539 +#define ST_TXRP_IDX_MASK       0x0fff  /* Tx Report Index Mask */
2540 +#define ST_TXTH_IDX_MASK       0x0fff  /* Tx Threshold Index Mask */
2541 +#define ST_WM_IDX_MASK         0x3f    /* FIFO Watermark Index Mask */
2542
2543  /*
2544   *     Bank 30
2545 @@ -742,11 +1118,9 @@
2546  #define WOL_MATCH_RES  0x0f23  /*  8 bit       WOL Match Result Reg */
2547  #define WOL_MAC_ADDR_LO        0x0f24  /* 32 bit       WOL MAC Address Low */
2548  #define WOL_MAC_ADDR_HI        0x0f28  /* 16 bit       WOL MAC Address High */
2549 -#define WOL_PATT_RPTR  0x0f2c  /*  8 bit       WOL Pattern Read Ptr */
2550 -
2551 -/* use this macro to access above registers */
2552 -#define WOL_REG(Reg)   ((Reg) + (pAC->GIni.GIWolOffs))
2553 -
2554 +#define WOL_PATT_PME   0x0f2a  /*  8 bit       WOL PME Match Enable (Yukon-2) */
2555 +#define WOL_PATT_ASFM  0x0f2b  /*  8 bit       WOL ASF Match Enable (Yukon-2) */
2556 +#define WOL_PATT_RPTR  0x0f2c  /*  8 bit       WOL Pattern Read Pointer */
2557
2558  /* WOL Pattern Length Registers (YUKON only) */
2559
2560 @@ -764,11 +1138,22 @@
2561   */
2562  /* 0x0f80 - 0x0fff:    reserved */
2563
2564 +/* WOL registers link 2 */
2565 +
2566 +/* use this macro to access WOL registers */
2567 +#define WOL_REG(Port, Reg)     ((Reg) + ((Port)*0x80) + (pAC->GIni.GIWolOffs))
2568 +
2569  /*
2570   *     Bank 32 - 33
2571   */
2572  #define WOL_PATT_RAM_1 0x1000  /*  WOL Pattern RAM Link 1 */
2573 +#define WOL_PATT_RAM_2 0x1400  /*  WOL Pattern RAM Link 2 */
2574 +
2575 +/* use this macro to retrieve the pattern ram base address */
2576 +#define WOL_PATT_RAM_BASE(Port) (WOL_PATT_RAM_1 + (Port)*0x400)
2577
2578 +/* offset to configuration space on Yukon-2 */
2579 +#define Y2_CFG_SPC             0x1c00
2580  /*
2581   *     Bank 0x22 - 0x3f
2582   */
2583 @@ -800,13 +1185,27 @@
2584   */
2585  /*     B0_RAP          8 bit   Register Address Port */
2586                                                                 /* Bit 7:       reserved */
2587 -#define RAP_RAP                        0x3f    /* Bit 6..0:    0 = block 0,..,6f = block 6f */
2588 +#define RAP_MSK                        0x7f    /* Bit 6..0:    0 = block 0,..,6f = block 6f */
2589 +
2590 +/*     B0_CTST                 24 bit  Control/Status register */
2591 +                                                               /* Bit 23..18:  reserved */
2592 +#define Y2_VMAIN_AVAIL BIT_17          /* VMAIN available (YUKON-2 only) */
2593 +#define Y2_VAUX_AVAIL  BIT_16          /* VAUX available (YUKON-2 only) */
2594 +#define Y2_HW_WOL_ON   BIT_15S         /* HW WOL On  (Yukon-EC Ultra A1 only) */
2595 +#define Y2_HW_WOL_OFF  BIT_14S         /* HW WOL Off (Yukon-EC Ultra A1 only) */
2596 +#define Y2_ASF_ENABLE  BIT_13S         /* ASF Unit Enable (YUKON-2 only) */
2597 +#define Y2_ASF_DISABLE BIT_12S         /* ASF Unit Disable (YUKON-2 only) */
2598 +#define Y2_CLK_RUN_ENA BIT_11S         /* CLK_RUN Enable  (YUKON-2 only) */
2599 +#define Y2_CLK_RUN_DIS BIT_10S         /* CLK_RUN Disable (YUKON-2 only) */
2600 +#define Y2_LED_STAT_ON BIT_9S          /* Status LED On  (YUKON-2 only) */
2601 +#define Y2_LED_STAT_OFF        BIT_8S          /* Status LED Off (YUKON-2 only) */
2602 +                                                               /* Bit  7.. 0:  same as below */
2603
2604  /*     B0_CTST                 16 bit  Control/Status register */
2605                                                                 /* Bit 15..14:  reserved */
2606 -#define CS_CLK_RUN_HOT BIT_13S         /* CLK_RUN hot m. (YUKON-Lite only) */
2607 -#define CS_CLK_RUN_RST BIT_12S         /* CLK_RUN reset  (YUKON-Lite only) */
2608 -#define CS_CLK_RUN_ENA BIT_11S         /* CLK_RUN enable (YUKON-Lite only) */
2609 +#define CS_CLK_RUN_HOT BIT_13S         /* CLK_RUN Hot m. (YUKON-Lite only) */
2610 +#define CS_CLK_RUN_RST BIT_12S         /* CLK_RUN Reset  (YUKON-Lite only) */
2611 +#define CS_CLK_RUN_ENA BIT_11S         /* CLK_RUN Enable (YUKON-Lite only) */
2612  #define CS_VAUX_AVAIL  BIT_10S         /* VAUX available (YUKON only) */
2613  #define CS_BUS_CLOCK   BIT_9S          /* Bus Clock 0/1 = 33/66 MHz */
2614  #define CS_BUS_SLOT_SZ BIT_8S          /* Slot Size 0/1 = 32/64 bit slot */
2615 @@ -814,26 +1213,27 @@
2616  #define CS_CL_SW_IRQ   BIT_6S          /* Clear IRQ SW Request */
2617  #define CS_STOP_DONE   BIT_5S          /* Stop Master is finished */
2618  #define CS_STOP_MAST   BIT_4S          /* Command Bit to stop the master */
2619 -#define CS_MRST_CLR            BIT_3S          /* Clear Master reset   */
2620 -#define CS_MRST_SET            BIT_2S          /* Set Master reset     */
2621 -#define CS_RST_CLR             BIT_1S          /* Clear Software reset */
2622 -#define CS_RST_SET             BIT_0S          /* Set   Software reset */
2623 +#define CS_MRST_CLR            BIT_3S          /* Clear Master Reset */
2624 +#define CS_MRST_SET            BIT_2S          /* Set   Master Reset */
2625 +#define CS_RST_CLR             BIT_1S          /* Clear Software Reset */
2626 +#define CS_RST_SET             BIT_0S          /* Set   Software Reset */
2627
2628 -/*     B0_LED                   8 Bit  LED register */
2629 +/*     B0_LED                   8 Bit  LED register (GENESIS only)*/
2630                                                                 /* Bit  7.. 2:  reserved */
2631 -#define LED_STAT_ON            BIT_1S          /* Status LED on        */
2632 -#define LED_STAT_OFF   BIT_0S          /* Status LED off       */
2633 +#define LED_STAT_ON            BIT_1S          /* Status LED On        */
2634 +#define LED_STAT_OFF   BIT_0S          /* Status LED Off       */
2635
2636  /*     B0_POWER_CTRL    8 Bit  Power Control reg (YUKON only) */
2637  #define PC_VAUX_ENA            BIT_7           /* Switch VAUX Enable  */
2638 -#define PC_VAUX_DIS            BIT_6       /* Switch VAUX Disable */
2639 -#define PC_VCC_ENA             BIT_5       /* Switch VCC Enable  */
2640 -#define PC_VCC_DIS             BIT_4       /* Switch VCC Disable */
2641 -#define PC_VAUX_ON             BIT_3       /* Switch VAUX On  */
2642 -#define PC_VAUX_OFF            BIT_2       /* Switch VAUX Off */
2643 -#define PC_VCC_ON              BIT_1       /* Switch VCC On  */
2644 -#define PC_VCC_OFF             BIT_0       /* Switch VCC Off */
2645 +#define PC_VAUX_DIS            BIT_6           /* Switch VAUX Disable */
2646 +#define PC_VCC_ENA             BIT_5           /* Switch VCC Enable  */
2647 +#define PC_VCC_DIS             BIT_4           /* Switch VCC Disable */
2648 +#define PC_VAUX_ON             BIT_3           /* Switch VAUX On  */
2649 +#define PC_VAUX_OFF            BIT_2           /* Switch VAUX Off */
2650 +#define PC_VCC_ON              BIT_1           /* Switch VCC On  */
2651 +#define PC_VCC_OFF             BIT_0           /* Switch VCC Off */
2652
2653 +/* Yukon and Genesis */
2654  /*     B0_ISRC                 32 bit  Interrupt Source Register */
2655  /*     B0_IMSK                 32 bit  Interrupt Mask Register */
2656  /*     B0_SP_ISRC              32 bit  Special Interrupt Source Reg */
2657 @@ -879,12 +1279,58 @@
2658  #define IS_XA2_F               BIT_1           /* Q_XA2 End of Frame */
2659  #define IS_XA2_C               BIT_0           /* Q_XA2 Encoding Error */
2660
2661 +/* Yukon-2 */
2662 +/*     B0_ISRC                 32 bit  Interrupt Source Register */
2663 +/*     B0_IMSK                 32 bit  Interrupt Mask Register */
2664 +/*     B0_SP_ISRC              32 bit  Special Interrupt Source Reg */
2665 +/*     B2_IRQM_MSK             32 bit  IRQ Moderation Mask */
2666 +/*     B0_Y2_SP_ISRC2  32 bit  Special Interrupt Source Reg 2 */
2667 +/*     B0_Y2_SP_ISRC3  32 bit  Special Interrupt Source Reg 3 */
2668 +/*     B0_Y2_SP_EISR   32 bit  Enter ISR Reg */
2669 +/*     B0_Y2_SP_LISR   32 bit  Leave ISR Reg */
2670 +#define Y2_IS_PORT_MASK(Port, Mask)    ((Mask) << (Port*8))
2671 +#define Y2_IS_HW_ERR   BIT_31          /* Interrupt HW Error */
2672 +#define Y2_IS_STAT_BMU BIT_30          /* Status BMU Interrupt */
2673 +#define Y2_IS_ASF              BIT_29          /* ASF subsystem Interrupt */
2674 +                                                       /* Bit 28: reserved */
2675 +#define Y2_IS_POLL_CHK BIT_27          /* Check IRQ from polling unit */
2676 +#define Y2_IS_TWSI_RDY BIT_26          /* IRQ on end of TWSI Tx */
2677 +#define Y2_IS_IRQ_SW   BIT_25          /* SW forced IRQ        */
2678 +#define Y2_IS_TIMINT   BIT_24          /* IRQ from Timer       */
2679 +                                                       /* Bit 23..16 reserved */
2680 +                                               /* Link 2 Interrupts */
2681 +#define Y2_IS_IRQ_PHY2 BIT_12          /* Interrupt from PHY 2 */
2682 +#define Y2_IS_IRQ_MAC2 BIT_11          /* Interrupt from MAC 2 */
2683 +#define Y2_IS_CHK_RX2  BIT_10          /* Descriptor error Rx 2 */
2684 +#define Y2_IS_CHK_TXS2 BIT_9           /* Descriptor error TXS 2 */
2685 +#define Y2_IS_CHK_TXA2 BIT_8           /* Descriptor error TXA 2 */
2686 +                                                       /* Bit  7.. 5 reserved */
2687 +                                               /* Link 1 interrupts */
2688 +#define Y2_IS_IRQ_PHY1 BIT_4           /* Interrupt from PHY 1 */
2689 +#define Y2_IS_IRQ_MAC1 BIT_3           /* Interrupt from MAC 1 */
2690 +#define Y2_IS_CHK_RX1  BIT_2           /* Descriptor error Rx 1 */
2691 +#define Y2_IS_CHK_TXS1 BIT_1           /* Descriptor error TXS 1 */
2692 +#define Y2_IS_CHK_TXA1 BIT_0           /* Descriptor error TXA 1 */
2693 +
2694 +#define Y2_IS_L1_MASK  0x0000001fUL    /* IRQ Mask for port 1 */
2695 +
2696 +#define Y2_IS_L2_MASK  0x00001f00UL    /* IRQ Mask for port 2 */
2697 +
2698 +#define Y2_IS_ALL_MSK  0xef001f1fUL    /* All Interrupt bits */
2699 +
2700 +/*     B0_Y2_SP_ICR    32 bit  Interrupt Control Register */
2701 +                                                       /* Bit 31.. 4:  reserved */
2702 +#define Y2_IC_ISR_MASK BIT_3           /* ISR mask flag */
2703 +#define Y2_IC_ISR_STAT BIT_2           /* ISR status flag */
2704 +#define Y2_IC_LEAVE_ISR        BIT_1           /* Leave ISR */
2705 +#define Y2_IC_ENTER_ISR        BIT_0           /* Enter ISR */
2706
2707 +/* Yukon and Genesis */
2708  /*     B0_HWE_ISRC             32 bit  HW Error Interrupt Src Reg */
2709  /*     B0_HWE_IMSK             32 bit  HW Error Interrupt Mask Reg */
2710  /*     B2_IRQM_HWE_MSK 32 bit  IRQ Moderation HW Error Mask */
2711  #define IS_ERR_MSK             0x00000fffL     /*              All Error bits */
2712 -                                                               /* Bit 31..14:  reserved */
2713 +                                                       /* Bit 31..14:  reserved */
2714  #define IS_IRQ_TIST_OV BIT_13  /* Time Stamp Timer Overflow (YUKON only) */
2715  #define IS_IRQ_SENSOR  BIT_12  /* IRQ from Sensor (YUKON only) */
2716  #define IS_IRQ_MST_ERR BIT_11  /* IRQ master error detected */
2717 @@ -900,6 +1346,43 @@
2718  #define IS_R1_PAR_ERR  BIT_1   /* Queue R1 Parity Error */
2719  #define IS_R2_PAR_ERR  BIT_0   /* Queue R2 Parity Error */
2720
2721 +/* Yukon-2 */
2722 +/*     B0_HWE_ISRC             32 bit  HW Error Interrupt Src Reg */
2723 +/*     B0_HWE_IMSK             32 bit  HW Error Interrupt Mask Reg */
2724 +/*     B2_IRQM_HWE_MSK 32 bit  IRQ Moderation HW Error Mask */
2725 +                                               /* Bit: 31..30 reserved */
2726 +#define Y2_IS_TIST_OV  BIT_29  /* Time Stamp Timer overflow interrupt */
2727 +#define Y2_IS_SENSOR   BIT_28  /* Sensor interrupt */
2728 +#define Y2_IS_MST_ERR  BIT_27  /* Master error interrupt */
2729 +#define Y2_IS_IRQ_STAT BIT_26  /* Status exception interrupt */
2730 +#define Y2_IS_PCI_EXP  BIT_25  /* PCI-Express interrupt */
2731 +#define Y2_IS_PCI_NEXP BIT_24  /* Bus Abort detected */
2732 +                                               /* Bit: 23..14 reserved */
2733 +                                               /* Link 2 */
2734 +#define Y2_IS_PAR_RD2  BIT_13  /* Read RAM parity error interrupt */
2735 +#define Y2_IS_PAR_WR2  BIT_12  /* Write RAM parity error interrupt */
2736 +#define Y2_IS_PAR_MAC2 BIT_11  /* MAC hardware fault interrupt */
2737 +#define Y2_IS_PAR_RX2  BIT_10  /* Parity Error Rx Queue 2 */
2738 +#define Y2_IS_TCP_TXS2 BIT_9   /* TCP length mismatch sync Tx queue IRQ */
2739 +#define Y2_IS_TCP_TXA2 BIT_8   /* TCP length mismatch async Tx queue IRQ */
2740 +                                               /* Bit:  9.. 6 reserved */
2741 +                                               /* Link 1 */
2742 +#define Y2_IS_PAR_RD1  BIT_5   /* Read RAM parity error interrupt */
2743 +#define Y2_IS_PAR_WR1  BIT_4   /* Write RAM parity error interrupt */
2744 +#define Y2_IS_PAR_MAC1 BIT_3   /* MAC hardware fault interrupt */
2745 +#define Y2_IS_PAR_RX1  BIT_2   /* Parity Error Rx Queue 1 */
2746 +#define Y2_IS_TCP_TXS1 BIT_1   /* TCP length mismatch sync Tx queue IRQ */
2747 +#define Y2_IS_TCP_TXA1 BIT_0   /* TCP length mismatch async Tx queue IRQ */
2748 +
2749 +#define Y2_HWE_L1_MASK (Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |\
2750 +                                                Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1)
2751 +#define Y2_HWE_L2_MASK (Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |\
2752 +                                                Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2)
2753 +
2754 +#define Y2_HWE_ALL_MSK (Y2_IS_TIST_OV | /* Y2_IS_SENSOR | */ Y2_IS_MST_ERR |\
2755 +                                                Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP |\
2756 +                                                Y2_HWE_L1_MASK | Y2_HWE_L2_MASK)
2757 +
2758  /*     B2_CONN_TYP              8 bit  Connector type */
2759  /*     B2_PMD_TYP               8 bit  PMD type */
2760  /*     Values of connector and PMD type comply to SysKonnect internal std */
2761 @@ -908,19 +1391,78 @@
2762  #define CFG_CHIP_R_MSK (0xf<<4)        /* Bit 7.. 4: Chip Revision */
2763                                                                         /* Bit 3.. 2:   reserved */
2764  #define CFG_DIS_M2_CLK BIT_1S          /* Disable Clock for 2nd MAC */
2765 -#define CFG_SNG_MAC            BIT_0S          /* MAC Config: 0=2 MACs / 1=1 MAC*/
2766 +#define CFG_SNG_MAC            BIT_0S          /* MAC Config: 0 = 2 MACs; 1 = 1 MAC */
2767
2768 -/*     B2_CHIP_ID               8 bit  Chip Identification Number */
2769 +/*     B2_CHIP_ID               8 bit  Chip Identification Number */
2770  #define CHIP_ID_GENESIS                0x0a    /* Chip ID for GENESIS */
2771  #define CHIP_ID_YUKON          0xb0    /* Chip ID for YUKON */
2772  #define CHIP_ID_YUKON_LITE     0xb1    /* Chip ID for YUKON-Lite (Rev. A1-A3) */
2773  #define CHIP_ID_YUKON_LP       0xb2    /* Chip ID for YUKON-LP */
2774 +#define CHIP_ID_YUKON_XL       0xb3    /* Chip ID for YUKON-2 XL */
2775 +#define CHIP_ID_YUKON_EC_U     0xb4    /* Chip ID for YUKON-2 EC Ultra */
2776 +#define CHIP_ID_YUKON_EC       0xb6    /* Chip ID for YUKON-2 EC */
2777 +#define CHIP_ID_YUKON_FE       0xb7    /* Chip ID for YUKON-2 FE */
2778
2779  #define CHIP_REV_YU_LITE_A1    3               /* Chip Rev. for YUKON-Lite A1,A2 */
2780  #define CHIP_REV_YU_LITE_A3    7               /* Chip Rev. for YUKON-Lite A3 */
2781
2782 +#define CHIP_REV_YU_XL_A0      0               /* Chip Rev. for Yukon-2 A0 */
2783 +#define CHIP_REV_YU_XL_A1      1               /* Chip Rev. for Yukon-2 A1 */
2784 +#define CHIP_REV_YU_XL_A2      2               /* Chip Rev. for Yukon-2 A2 */
2785 +#define CHIP_REV_YU_XL_A3      3               /* Chip Rev. for Yukon-2 A3 */
2786 +
2787 +#define CHIP_REV_YU_EC_A1      0               /* Chip Rev. for Yukon-EC A0,A1 */
2788 +#define CHIP_REV_YU_EC_A2      1               /* Chip Rev. for Yukon-EC A2 */
2789 +#define CHIP_REV_YU_EC_A3      2               /* Chip Rev. for Yukon-EC A3 */
2790 +
2791 +#define CHIP_REV_YU_EC_U_A0    1               /* Chip Rev. for Yukon-EC Ultra A0 */
2792 +#define CHIP_REV_YU_EC_U_A1    2               /* Chip Rev. for Yukon-EC Ultra A1 */
2793 +
2794 +#define CHIP_REV_YU_FE_A1      1               /* Chip Rev. for Yukon-FE A1 */
2795 +#define CHIP_REV_YU_FE_A2      3               /* Chip Rev. for Yukon-FE A2 */
2796 +
2797 +/*     B2_Y2_CLK_GATE   8 bit  Clock Gating (Yukon-2 only) */
2798 +#define Y2_STATUS_LNK2_INAC    BIT_7S  /* Status Link 2 inactiv (0 = activ) */
2799 +#define Y2_CLK_GAT_LNK2_DIS    BIT_6S  /* Disable PHY clock for Link 2 */
2800 +#define Y2_COR_CLK_LNK2_DIS    BIT_5S  /* Disable Core clock Link 2 */
2801 +#define Y2_PCI_CLK_LNK2_DIS    BIT_4S  /* Disable PCI clock Link 2 */
2802 +#define Y2_STATUS_LNK1_INAC    BIT_3S  /* Status Link 1 inactiv (0 = activ) */
2803 +#define Y2_CLK_GAT_LNK1_DIS    BIT_2S  /* Disable PHY clock for Link 1 */
2804 +#define Y2_COR_CLK_LNK1_DIS    BIT_1S  /* Disable Core clock Link 1 */
2805 +#define Y2_PCI_CLK_LNK1_DIS    BIT_0S  /* Disable PCI clock Link 1 */
2806 +
2807 +/*     B2_Y2_HW_RES    8 bit   HW Resources (Yukon-2 only) */
2808 +                                                               /* Bit 7.. 6:   reserved */
2809 +#define CFG_PEX_PME_NATIVE     BIT_5S  /* PCI-E PME native mode select */
2810 +#define CFG_LED_MODE_MSK       (7<<2)  /* Bit  4.. 2:  LED Mode Mask */
2811 +#define CFG_LINK_2_AVAIL       BIT_1S  /* Link 2 available */
2812 +#define CFG_LINK_1_AVAIL       BIT_0S  /* Link 1 available */
2813 +
2814 +#define CFG_LED_MODE(x)                (((x) & CFG_LED_MODE_MSK) >> 2)
2815 +#define CFG_DUAL_MAC_MSK       (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)
2816 +
2817 +#define CFG_LED_DUAL_ACT_LNK   1       /* Dual LED ACT/LNK mode */
2818 +#define CFG_LED_LINK_MUX_P60   2       /* Link LED on pin 60 (Yukon-EC Ultra) */
2819 +
2820 +/*     B2_E_3                   8 bit  lower 4 bits used for HW self test result */
2821 +#define B2_E3_RES_MASK 0x0f
2822 +
2823  /*     B2_FAR                  32 bit  Flash-Prom Addr Reg/Cnt */
2824 -#define FAR_ADDR               0x1ffffL        /* Bit 16.. 0:  FPROM Address mask */
2825 +#define FAR_ADDR               0x1ffffL        /* Bit 16.. 0:  FPROM Address Mask */
2826 +
2827 +/*     B2_Y2_CLK_CTRL  32 bit  Core Clock Frequency Control Register (Yukon-2/EC) */
2828 +                                                               /* Bit 31..24:  reserved */
2829 +/* Yukon-EC/FE */
2830 +#define Y2_CLK_DIV_VAL_MSK     (0xffL<<16)     /* Bit 23..16:  Clock Divisor Value */
2831 +#define Y2_CLK_DIV_VAL(x)      (SHIFT16(x) & Y2_CLK_DIV_VAL_MSK)
2832 +/* Yukon-2 */
2833 +#define Y2_CLK_DIV_VAL2_MSK    (7L<<21)        /* Bit 23..21:  Clock Divisor Value */
2834 +#define Y2_CLK_SELECT2_MSK     (0x1fL<<16)     /* Bit 20..16:  Clock Select */
2835 +#define Y2_CLK_DIV_VAL_2(x)    (SHIFT21(x) & Y2_CLK_DIV_VAL2_MSK)
2836 +#define Y2_CLK_SEL_VAL_2(x)    (SHIFT16(x) & Y2_CLK_SELECT2_MSK)
2837 +                                                               /* Bit 15.. 2:  reserved */
2838 +#define Y2_CLK_DIV_ENA         BIT_1S  /* Enable  Core Clock Division */
2839 +#define Y2_CLK_DIV_DIS         BIT_0S  /* Disable Core Clock Division */
2840
2841  /*     B2_LD_CTRL               8 bit  EPROM loader control register */
2842  /*     Bits are currently reserved */
2843 @@ -960,9 +1502,6 @@
2844  #define DPT_START              BIT_1S  /* Start Descriptor Poll Timer */
2845  #define DPT_STOP               BIT_0S  /* Stop  Descriptor Poll Timer */
2846
2847 -/*     B2_E_3                   8 bit  lower 4 bits used for HW self test result */
2848 -#define B2_E3_RES_MASK 0x0f
2849 -
2850  /*     B2_TST_CTRL1     8 bit  Test Control Register 1 */
2851  #define TST_FRC_DPERR_MR       BIT_7S  /* force DATAPERR on MST RD */
2852  #define TST_FRC_DPERR_MW       BIT_6S  /* force DATAPERR on MST WR */
2853 @@ -975,14 +1514,14 @@
2854
2855  /*     B2_TST_CTRL2     8 bit  Test Control Register 2 */
2856                                                                         /* Bit 7.. 4:   reserved */
2857 -                       /* force the following error on the next master read/write      */
2858 +                       /* force the following error on the next master read/write */
2859  #define TST_FRC_DPERR_MR64     BIT_3S  /* DataPERR RD 64       */
2860  #define TST_FRC_DPERR_MW64     BIT_2S  /* DataPERR WR 64       */
2861  #define TST_FRC_APERR_1M64     BIT_1S  /* AddrPERR on 1. phase */
2862  #define TST_FRC_APERR_2M64     BIT_0S  /* AddrPERR on 2. phase */
2863
2864  /*     B2_GP_IO                32 bit  General Purpose I/O Register */
2865 -                                                       /* Bit 31..26:  reserved */
2866 +                                               /* Bit 31..26:  reserved */
2867  #define GP_DIR_9       BIT_25  /* IO_9 direct, 0=In/1=Out */
2868  #define GP_DIR_8       BIT_24  /* IO_8 direct, 0=In/1=Out */
2869  #define GP_DIR_7       BIT_23  /* IO_7 direct, 0=In/1=Out */
2870 @@ -1009,15 +1548,15 @@
2871  #define I2C_FLAG               BIT_31          /* Start read/write if WR */
2872  #define I2C_ADDR               (0x7fffL<<16)   /* Bit 30..16:  Addr to be RD/WR */
2873  #define I2C_DEV_SEL            (0x7fL<<9)              /* Bit 15.. 9:  I2C Device Select */
2874 -                                                               /* Bit  8.. 5:  reserved        */
2875 +                                                               /* Bit  8.. 5:  reserved */
2876  #define I2C_BURST_LEN  BIT_4           /* Burst Len, 1/4 bytes */
2877 -#define I2C_DEV_SIZE   (7<<1)          /* Bit  3.. 1:  I2C Device Size */
2878 -#define I2C_025K_DEV   (0<<1)          /*              0: 256 Bytes or smal. */
2879 -#define I2C_05K_DEV            (1<<1)          /*              1: 512  Bytes   */
2880 -#define I2C_1K_DEV             (2<<1)          /*              2: 1024 Bytes   */
2881 -#define I2C_2K_DEV             (3<<1)          /*              3: 2048 Bytes   */
2882 -#define I2C_4K_DEV             (4<<1)          /*              4: 4096 Bytes   */
2883 -#define I2C_8K_DEV             (5<<1)          /*              5: 8192 Bytes   */
2884 +#define I2C_DEV_SIZE   (7<<1)          /* Bit  3.. 1:  I2C Device Size */
2885 +#define I2C_025K_DEV   (0<<1)          /*              0:   256 Bytes or smaller */
2886 +#define I2C_05K_DEV            (1<<1)          /*              1:   512 Bytes  */
2887 +#define I2C_1K_DEV             (2<<1)          /*              2:  1024 Bytes  */
2888 +#define I2C_2K_DEV             (3<<1)          /*              3:  2048 Bytes  */
2889 +#define I2C_4K_DEV             (4<<1)          /*              4:  4096 Bytes  */
2890 +#define I2C_8K_DEV             (5<<1)          /*              5:  8192 Bytes  */
2891  #define I2C_16K_DEV            (6<<1)          /*              6: 16384 Bytes  */
2892  #define I2C_32K_DEV            (7<<1)          /*              7: 32768 Bytes  */
2893  #define I2C_STOP               BIT_0           /* Interrupt I2C transfer */
2894 @@ -1026,16 +1565,14 @@
2895                                                                 /* Bit 31.. 1   reserved */
2896  #define I2C_CLR_IRQ            BIT_0   /* Clear I2C IRQ */
2897
2898 -/*     B2_I2C_SW               32 bit (8 bit access)   I2C HW SW Port Register */
2899 +/*     B2_I2C_SW               32 bit (8 bit access)   I2C SW Port Register */
2900                                                                 /* Bit  7.. 3:  reserved */
2901  #define I2C_DATA_DIR   BIT_2S          /* direction of I2C_DATA */
2902 -#define I2C_DATA               BIT_1S          /* I2C Data Port        */
2903 -#define I2C_CLK                        BIT_0S          /* I2C Clock Port       */
2904 +#define I2C_DATA               BIT_1S          /* I2C Data Port */
2905 +#define I2C_CLK                        BIT_0S          /* I2C Clock Port */
2906
2907 -/*
2908 - * I2C Address
2909 - */
2910 -#define I2C_SENS_ADDR  LM80_ADDR       /* I2C Sensor Address, (Volt and Temp)*/
2911 +/* I2C Address */
2912 +#define I2C_SENS_ADDR  LM80_ADDR       /* I2C Sensor Address (Volt and Temp) */
2913
2914
2915  /*     B2_BSC_CTRL              8 bit  Blink Source Counter Control */
2916 @@ -1052,16 +1589,20 @@
2917  #define BSC_T_OFF      BIT_1S          /* Test mode off */
2918  #define BSC_T_STEP     BIT_0S          /* Test step */
2919
2920 +/*     Y2_PEX_PHY_ADDR/DATA            PEX PHY address and data reg  (Yukon-2 only) */
2921 +#define PEX_RD_ACCESS  BIT_31  /* Access Mode Read = 1, Write = 0 */
2922 +#define PEX_DB_ACCESS  BIT_30  /* Access to debug register */
2923 +
2924
2925  /*     B3_RAM_ADDR             32 bit  RAM Address, to read or write */
2926                                         /* Bit 31..19:  reserved */
2927  #define RAM_ADR_RAN    0x0007ffffL     /* Bit 18.. 0:  RAM Address Range */
2928
2929  /* RAM Interface Registers */
2930 -/*     B3_RI_CTRL              16 bit  RAM Iface Control Register */
2931 +/*     B3_RI_CTRL              16 bit  RAM Interface Control Register */
2932                                                                 /* Bit 15..10:  reserved */
2933 -#define RI_CLR_RD_PERR BIT_9S  /* Clear IRQ RAM Read Parity Err */
2934 -#define RI_CLR_WR_PERR BIT_8S  /* Clear IRQ RAM Write Parity Err*/
2935 +#define RI_CLR_RD_PERR BIT_9S  /* Clear IRQ RAM Read  Parity Err */
2936 +#define RI_CLR_WR_PERR BIT_8S  /* Clear IRQ RAM Write Parity Err */
2937                                                                 /* Bit  7.. 2:  reserved */
2938  #define RI_RST_CLR             BIT_1S  /* Clear RAM Interface Reset */
2939  #define RI_RST_SET             BIT_0S  /* Set   RAM Interface Reset */
2940 @@ -1171,7 +1712,7 @@
2941                                                                 /* Bit 31..16:  reserved */
2942  #define BC_MAX                 0xffff  /* Bit 15.. 0:  Byte counter */
2943
2944 -/* BMU Control Status Registers */
2945 +/* BMU Control / Status Registers (Yukon and Genesis) */
2946  /*     B0_R1_CSR               32 bit  BMU Ctrl/Stat Rx Queue 1 */
2947  /*     B0_R2_CSR               32 bit  BMU Ctrl/Stat Rx Queue 2 */
2948  /*     B0_XA1_CSR              32 bit  BMU Ctrl/Stat Sync Tx Queue 1 */
2949 @@ -1212,13 +1753,48 @@
2950                                                 CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\
2951                                                 CSR_TRANS_RUN)
2952
2953 +/* Rx BMU Control / Status Registers (Yukon-2) */
2954 +#define BMU_IDLE                       BIT_31  /* BMU Idle State */
2955 +#define BMU_RX_TCP_PKT         BIT_30  /* Rx TCP Packet (when RSS Hash enabled) */
2956 +#define BMU_RX_IP_PKT          BIT_29  /* Rx IP  Packet (when RSS Hash enabled) */
2957 +                                                               /* Bit 28..16:  reserved */
2958 +#define BMU_ENA_RX_RSS_HASH    BIT_15  /* Enable  Rx RSS Hash */
2959 +#define BMU_DIS_RX_RSS_HASH    BIT_14  /* Disable Rx RSS Hash */
2960 +#define BMU_ENA_RX_CHKSUM      BIT_13  /* Enable  Rx TCP/IP Checksum Check */
2961 +#define BMU_DIS_RX_CHKSUM      BIT_12  /* Disable Rx TCP/IP Checksum Check */
2962 +#define BMU_CLR_IRQ_PAR                BIT_11  /* Clear IRQ on Parity errors (Rx) */
2963 +#define BMU_CLR_IRQ_TCP                BIT_11  /* Clear IRQ on TCP segmen. error (Tx) */
2964 +#define BMU_CLR_IRQ_CHK                BIT_10  /* Clear IRQ Check */
2965 +#define BMU_STOP                       BIT_9   /* Stop  Rx/Tx Queue */
2966 +#define BMU_START                      BIT_8   /* Start Rx/Tx Queue */
2967 +#define BMU_FIFO_OP_ON         BIT_7   /* FIFO Operational On */
2968 +#define BMU_FIFO_OP_OFF        BIT_6   /* FIFO Operational Off */
2969 +#define BMU_FIFO_ENA           BIT_5   /* Enable FIFO */
2970 +#define BMU_FIFO_RST           BIT_4   /* Reset  FIFO */
2971 +#define BMU_OP_ON                      BIT_3   /* BMU Operational On */
2972 +#define BMU_OP_OFF                     BIT_2   /* BMU Operational Off */
2973 +#define BMU_RST_CLR                    BIT_1   /* Clear BMU Reset (Enable) */
2974 +#define BMU_RST_SET                    BIT_0   /* Set   BMU Reset */
2975 +
2976 +#define BMU_CLR_RESET          (BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR)
2977 +#define BMU_OPER_INIT          (BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START | \
2978 +                                                       BMU_FIFO_ENA | BMU_OP_ON)
2979 +
2980 +/* Tx BMU Control / Status Registers (Yukon-2) */
2981 +                                                               /* Bit 31: same as for Rx */
2982 +                                                               /* Bit 30..14:  reserved */
2983 +#define BMU_TX_IPIDINCR_ON     BIT_13  /* Enable  IP ID Increment */
2984 +#define BMU_TX_IPIDINCR_OFF    BIT_12  /* Disable IP ID Increment */
2985 +#define BMU_TX_CLR_IRQ_TCP     BIT_11  /* Clear IRQ on TCP segm. length mism. */
2986 +                                                               /* Bit 10..0: same as for Rx */
2987 +
2988  /*     Q_F                             32 bit  Flag Register */
2989                                                                         /* Bit 31..28:  reserved */
2990  #define F_ALM_FULL             BIT_27          /* Rx FIFO: almost full */
2991  #define F_EMPTY                        BIT_27          /* Tx FIFO: empty flag */
2992  #define F_FIFO_EOF             BIT_26          /* Tag (EOF Flag) bit in FIFO */
2993  #define F_WM_REACHED   BIT_25          /* Watermark reached */
2994 -                                                                       /* reserved */
2995 +#define F_M_RX_RAM_DIS BIT_24          /* MAC Rx RAM Read Port disable */
2996  #define F_FIFO_LEVEL   (0x1fL<<16)     /* Bit 23..16:  # of Qwords in FIFO */
2997                                                                         /* Bit 15..11:  reserved */
2998  #define F_WATER_MARK   0x0007ffL       /* Bit 10.. 0:  Watermark */
2999 @@ -1260,6 +1836,13 @@
3000                                                                 /* Bit  3:      reserved */
3001  #define T3_VRAM_MSK            7               /* Bit  2.. 0:  Virtual RAM Buffer Address */
3002
3003 +/* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/
3004 +/* PREF_UNIT_CTRL_REG  32 bit  Prefetch Control register */
3005 +#define PREF_UNIT_OP_ON                BIT_3   /* prefetch unit operational */
3006 +#define PREF_UNIT_OP_OFF       BIT_2   /* prefetch unit not operational */
3007 +#define PREF_UNIT_RST_CLR      BIT_1   /* Clear Prefetch Unit Reset */
3008 +#define PREF_UNIT_RST_SET      BIT_0   /* Set   Prefetch Unit Reset */
3009 +
3010  /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
3011  /*     RB_START                32 bit  RAM Buffer Start Address */
3012  /*     RB_END                  32 bit  RAM Buffer End Address */
3013 @@ -1275,24 +1858,24 @@
3014  #define RB_MSK 0x0007ffff      /* Bit 18.. 0:  RAM Buffer Pointer Bits */
3015
3016  /*     RB_TST2                  8 bit  RAM Buffer Test Register 2 */
3017 -                                                               /* Bit 7.. 4:   reserved */
3018 -#define RB_PC_DEC              BIT_3S  /* Packet Counter Decrem */
3019 +                                                       /* Bit 7.. 4:   reserved */
3020 +#define RB_PC_DEC              BIT_3S  /* Packet Counter Decrement */
3021  #define RB_PC_T_ON             BIT_2S  /* Packet Counter Test On */
3022 -#define RB_PC_T_OFF            BIT_1S  /* Packet Counter Tst Off */
3023 -#define RB_PC_INC              BIT_0S  /* Packet Counter Increm */
3024 +#define RB_PC_T_OFF            BIT_1S  /* Packet Counter Test Off */
3025 +#define RB_PC_INC              BIT_0S  /* Packet Counter Increment */
3026
3027  /*     RB_TST1                  8 bit  RAM Buffer Test Register 1 */
3028                                                         /* Bit 7:       reserved */
3029  #define RB_WP_T_ON             BIT_6S  /* Write Pointer Test On */
3030  #define RB_WP_T_OFF            BIT_5S  /* Write Pointer Test Off */
3031 -#define RB_WP_INC              BIT_4S  /* Write Pointer Increm */
3032 +#define RB_WP_INC              BIT_4S  /* Write Pointer Increment */
3033                                                                 /* Bit 3:       reserved */
3034  #define RB_RP_T_ON             BIT_2S  /* Read Pointer Test On */
3035  #define RB_RP_T_OFF            BIT_1S  /* Read Pointer Test Off */
3036 -#define RB_RP_DEC              BIT_0S  /* Read Pointer Decrement */
3037 +#define RB_RP_INC              BIT_0S  /* Read Pointer Increment */
3038
3039  /*     RB_CTRL                  8 bit  RAM Buffer Control Register */
3040 -                                                               /* Bit 7.. 6:   reserved */
3041 +                                                       /* Bit 7.. 6:   reserved */
3042  #define RB_ENA_STFWD   BIT_5S  /* Enable  Store & Forward */
3043  #define RB_DIS_STFWD   BIT_4S  /* Disable Store & Forward */
3044  #define RB_ENA_OP_MD   BIT_3S  /* Enable  Operation Mode */
3045 @@ -1300,16 +1883,31 @@
3046  #define RB_RST_CLR             BIT_1S  /* Clear RAM Buf STM Reset */
3047  #define RB_RST_SET             BIT_0S  /* Set   RAM Buf STM Reset */
3048
3049 +/* Yukon-2 */
3050 +                                                       /* Bit 31..20:  reserved */
3051 +#define RB_CNT_DOWN            BIT_19  /* Packet Counter Decrement */
3052 +#define RB_CNT_TST_ON  BIT_18  /* Packet Counter Test On */
3053 +#define RB_CNT_TST_OFF BIT_17  /* Packet Counter Test Off */
3054 +#define RB_CNT_UP              BIT_16  /* Packet Counter Increment */
3055 +                                                       /* Bit 15:      reserved */
3056 +#define RB_WP_TST_ON   BIT_14  /* Write Pointer Test On */
3057 +#define RB_WP_TST_OFF  BIT_13  /* Write Pointer Test Off */
3058 +#define RB_WP_UP               BIT_12  /* Write Pointer Increment  */
3059 +                                                       /* Bit 11:      reserved */
3060 +#define RB_RP_TST_ON   BIT_10  /* Read Pointer Test On */
3061 +#define RB_RP_TST_OFF  BIT_9   /* Read Pointer Test Off */
3062 +#define RB_RP_UP               BIT_8   /* Read Pointer Increment */
3063 +
3064
3065  /* Receive and Transmit MAC FIFO Registers (GENESIS only) */
3066
3067  /*     RX_MFF_EA               32 bit  Receive MAC FIFO End Address */
3068 -/*     RX_MFF_WP               32 bit  Receive MAC FIFO Write Pointer */
3069 +/*     RX_MFF_WP               32 bit  Receive MAC FIFO Write Pointer */
3070  /*     RX_MFF_RP               32 bit  Receive MAC FIFO Read Pointer */
3071  /*     RX_MFF_PC               32 bit  Receive MAC FIFO Packet Counter */
3072  /*     RX_MFF_LEV              32 bit  Receive MAC FIFO Level */
3073  /*     TX_MFF_EA               32 bit  Transmit MAC FIFO End Address */
3074 -/*     TX_MFF_WP               32 bit  Transmit MAC FIFO Write Pointer */
3075 +/*     TX_MFF_WP               32 bit  Transmit MAC FIFO Write Pointer */
3076  /*     TX_MFF_WSP              32 bit  Transmit MAC FIFO WR Shadow Pointer */
3077  /*     TX_MFF_RP               32 bit  Transmit MAC FIFO Read Pointer */
3078  /*     TX_MFF_PC               32 bit  Transmit MAC FIFO Packet Cnt */
3079 @@ -1359,9 +1957,9 @@
3080  /*     RX_MFF_TST2              8 bit  Receive MAC FIFO Test Register 2 */
3081  /*     TX_MFF_TST2              8 bit  Transmit MAC FIFO Test Register 2 */
3082                                                                 /* Bit 7:       reserved */
3083 -#define MFF_WSP_T_ON   BIT_6S  /* Tx: Write Shadow Ptr TestOn */
3084 -#define MFF_WSP_T_OFF  BIT_5S  /* Tx: Write Shadow Ptr TstOff */
3085 -#define MFF_WSP_INC            BIT_4S  /* Tx: Write Shadow Ptr Increment */
3086 +#define MFF_WSP_T_ON   BIT_6S  /* Tx: Write Shadow Pointer Test On */
3087 +#define MFF_WSP_T_OFF  BIT_5S  /* Tx: Write Shadow Pointer Test Off */
3088 +#define MFF_WSP_INC            BIT_4S  /* Tx: Write Shadow Pointer Increment */
3089  #define MFF_PC_DEC             BIT_3S  /* Packet Counter Decrement */
3090  #define MFF_PC_T_ON            BIT_2S  /* Packet Counter Test On */
3091  #define MFF_PC_T_OFF   BIT_1S  /* Packet Counter Test Off */
3092 @@ -1372,7 +1970,7 @@
3093                                         /* Bit 7:       reserved */
3094  #define MFF_WP_T_ON            BIT_6S  /* Write Pointer Test On */
3095  #define MFF_WP_T_OFF   BIT_5S  /* Write Pointer Test Off */
3096 -#define MFF_WP_INC             BIT_4S  /* Write Pointer Increm */
3097 +#define MFF_WP_INC             BIT_4S  /* Write Pointer Increment */
3098                                                         /* Bit 3:       reserved */
3099  #define MFF_RP_T_ON            BIT_2S  /* Read Pointer Test On */
3100  #define MFF_RP_T_OFF   BIT_1S  /* Read Pointer Test Off */
3101 @@ -1391,12 +1989,16 @@
3102
3103  /*     RX_LED_CTRL              8 bit  Receive LED Cnt Control Reg */
3104  /*     TX_LED_CTRL              8 bit  Transmit LED Cnt Control Reg */
3105 +                                                       /* Bit 7.. 3:   reserved */
3106 +#define LED_START              BIT_2S  /* Start Counter */
3107 +#define LED_STOP               BIT_1S  /* Stop Counter */
3108 +#define LED_STATE              BIT_0S  /* Rx/Tx: LED State, 1=LED On */
3109 +
3110  /*     LNK_SYNC_CTRL    8 bit  Link Sync Cnt Control Register */
3111                                                         /* Bit 7.. 3:   reserved */
3112 -#define LED_START              BIT_2S  /* Start Timer */
3113 -#define LED_STOP               BIT_1S  /* Stop Timer */
3114 -#define LED_STATE              BIT_0S  /* Rx/Tx: LED State, 1=LED on */
3115 -#define LED_CLR_IRQ            BIT_0S  /* Lnk:         Clear Link IRQ */
3116 +#define LNK_START              BIT_2S  /* Start Counter */
3117 +#define LNK_STOP               BIT_1S  /* Stop Counter */
3118 +#define LNK_CLR_IRQ            BIT_0S  /* Clear Link IRQ */
3119
3120  /*     RX_LED_TST               8 bit  Receive LED Cnt Test Register */
3121  /*     TX_LED_TST               8 bit  Transmit LED Cnt Test Register */
3122 @@ -1407,86 +2009,142 @@
3123  #define LED_T_STEP             BIT_0S  /* LED Counter Step */
3124
3125  /*     LNK_LED_REG              8 bit  Link LED Register */
3126 -                                                               /* Bit 7.. 6:   reserved */
3127 +                                                       /* Bit 7.. 6:   reserved */
3128  #define LED_BLK_ON             BIT_5S  /* Link LED Blinking On */
3129  #define LED_BLK_OFF            BIT_4S  /* Link LED Blinking Off */
3130  #define LED_SYNC_ON            BIT_3S  /* Use Sync Wire to switch LED */
3131  #define LED_SYNC_OFF   BIT_2S  /* Disable Sync Wire Input */
3132 -#define LED_ON                 BIT_1S  /* switch LED on */
3133 -#define LED_OFF                        BIT_0S  /* switch LED off */
3134 +#define LED_ON                 BIT_1S  /* Switch LED On */
3135 +#define LED_OFF                        BIT_0S  /* Switch LED Off */
3136
3137  /*     Receive and Transmit GMAC FIFO Registers (YUKON only) */
3138
3139  /*     RX_GMF_EA               32 bit  Rx GMAC FIFO End Address */
3140  /*     RX_GMF_AF_THR   32 bit  Rx GMAC FIFO Almost Full Thresh. */
3141 -/*     RX_GMF_WP               32 bit  Rx GMAC FIFO Write Pointer */
3142 -/*     RX_GMF_WLEV             32 bit  Rx GMAC FIFO Write Level */
3143 -/*     RX_GMF_RP               32 bit  Rx GMAC FIFO Read Pointer */
3144 -/*     RX_GMF_RLEV             32 bit  Rx GMAC FIFO Read Level */
3145 +/*     RX_GMF_WP               32 bit  Rx GMAC FIFO Write Pointer */
3146 +/*     RX_GMF_WLEV             32 bit  Rx GMAC FIFO Write Level */
3147 +/*     RX_GMF_RP               32 bit  Rx GMAC FIFO Read Pointer */
3148 +/*     RX_GMF_RLEV             32 bit  Rx GMAC FIFO Read Level */
3149  /*     TX_GMF_EA               32 bit  Tx GMAC FIFO End Address */
3150  /*     TX_GMF_AE_THR   32 bit  Tx GMAC FIFO Almost Empty Thresh.*/
3151 -/*     TX_GMF_WP               32 bit  Tx GMAC FIFO Write Pointer */
3152 -/*     TX_GMF_WSP              32 bit  Tx GMAC FIFO Write Shadow Ptr. */
3153 -/*     TX_GMF_WLEV             32 bit  Tx GMAC FIFO Write Level */
3154 -/*     TX_GMF_RP               32 bit  Tx GMAC FIFO Read Pointer */
3155 -/*     TX_GMF_RSTP             32 bit  Tx GMAC FIFO Restart Pointer */
3156 -/*     TX_GMF_RLEV             32 bit  Tx GMAC FIFO Read Level */
3157 +/*     TX_GMF_WP               32 bit  Tx GMAC FIFO Write Pointer */
3158 +/*     TX_GMF_WSP              32 bit  Tx GMAC FIFO Write Shadow Pointer */
3159 +/*     TX_GMF_WLEV             32 bit  Tx GMAC FIFO Write Level */
3160 +/*     TX_GMF_RP               32 bit  Tx GMAC FIFO Read Pointer */
3161 +/*     TX_GMF_RSTP             32 bit  Tx GMAC FIFO Restart Pointer */
3162 +/*     TX_GMF_RLEV             32 bit  Tx GMAC FIFO Read Level */
3163
3164  /*     RX_GMF_CTRL_T   32 bit  Rx GMAC FIFO Control/Test */
3165 -                                               /* Bits 31..15: reserved */
3166 -#define GMF_WP_TST_ON  BIT_14          /* Write Pointer Test On */
3167 -#define GMF_WP_TST_OFF BIT_13          /* Write Pointer Test Off */
3168 -#define GMF_WP_STEP            BIT_12          /* Write Pointer Step/Increment */
3169 +                                               /* Bit 31..28 reserved */
3170 +#define RX_TRUNC_ON            BIT_27  /* Enable  Packet Truncation */
3171 +#define RX_TRUNC_OFF   BIT_26  /* Disable Packet Truncation */
3172 +#define RX_VLAN_STRIP_ON       BIT_25  /* Enable  VLAN Stripping */
3173 +#define RX_VLAN_STRIP_OFF      BIT_24  /* Disable VLAN Stripping */
3174 +                                               /* Bit 23..15 reserved */
3175 +#define GMF_WP_TST_ON  BIT_14  /* Write Pointer Test On */
3176 +#define GMF_WP_TST_OFF BIT_13  /* Write Pointer Test Off */
3177 +#define GMF_WP_STEP            BIT_12  /* Write Pointer Step/Increment */
3178                                                 /* Bit 11:      reserved */
3179 -#define GMF_RP_TST_ON  BIT_10          /* Read Pointer Test On */
3180 -#define GMF_RP_TST_OFF BIT_9           /* Read Pointer Test Off */
3181 -#define GMF_RP_STEP            BIT_8           /* Read Pointer Step/Increment */
3182 -#define GMF_RX_F_FL_ON BIT_7           /* Rx FIFO Flush Mode On */
3183 -#define GMF_RX_F_FL_OFF        BIT_6           /* Rx FIFO Flush Mode Off */
3184 -#define GMF_CLI_RX_FO  BIT_5           /* Clear IRQ Rx FIFO Overrun */
3185 -#define GMF_CLI_RX_FC  BIT_4           /* Clear IRQ Rx Frame Complete */
3186 -#define GMF_OPER_ON            BIT_3           /* Operational Mode On */
3187 -#define GMF_OPER_OFF   BIT_2           /* Operational Mode Off */
3188 -#define GMF_RST_CLR            BIT_1           /* Clear GMAC FIFO Reset */
3189 -#define GMF_RST_SET            BIT_0           /* Set   GMAC FIFO Reset */
3190 -
3191 -/*     TX_GMF_CTRL_T   32 bit  Tx GMAC FIFO Control/Test */
3192 -                                               /* Bits 31..19: reserved */
3193 -#define GMF_WSP_TST_ON BIT_18          /* Write Shadow Pointer Test On */
3194 -#define GMF_WSP_TST_OFF        BIT_17          /* Write Shadow Pointer Test Off */
3195 -#define GMF_WSP_STEP   BIT_16          /* Write Shadow Pointer Step/Increment */
3196 -                                               /* Bits 15..7: same as for RX_GMF_CTRL_T */
3197 -#define GMF_CLI_TX_FU  BIT_6           /* Clear IRQ Tx FIFO Underrun */
3198 -#define GMF_CLI_TX_FC  BIT_5           /* Clear IRQ Tx Frame Complete */
3199 -#define GMF_CLI_TX_PE  BIT_4           /* Clear IRQ Tx Parity Error */
3200 +#define GMF_RP_TST_ON  BIT_10  /* Read Pointer Test On */
3201 +#define GMF_RP_TST_OFF BIT_9   /* Read Pointer Test Off */
3202 +#define GMF_RP_STEP            BIT_8   /* Read Pointer Step/Increment */
3203 +#define GMF_RX_F_FL_ON BIT_7   /* Rx FIFO Flush Mode On */
3204 +#define GMF_RX_F_FL_OFF        BIT_6   /* Rx FIFO Flush Mode Off */
3205 +#define GMF_CLI_RX_FO  BIT_5   /* Clear IRQ Rx FIFO Overrun */
3206 +#define GMF_CLI_RX_FC  BIT_4   /* Clear IRQ Rx Frame Complete */
3207 +#define GMF_OPER_ON            BIT_3   /* Operational Mode On */
3208 +#define GMF_OPER_OFF   BIT_2   /* Operational Mode Off */
3209 +#define GMF_RST_CLR            BIT_1   /* Clear GMAC FIFO Reset */
3210 +#define GMF_RST_SET            BIT_0   /* Set   GMAC FIFO Reset */
3211 +
3212 +/*     TX_GMF_CTRL_T   32 bit  Tx GMAC FIFO Control/Test (YUKON and Yukon-2) */
3213 +#define TX_STFW_DIS            BIT_31  /* Disable Store & Forward (Yukon-EC Ultra) */
3214 +#define TX_STFW_ENA            BIT_30  /* Enable  Store & Forward (Yukon-EC Ultra) */
3215 +                                               /* Bits 29..26: reserved */
3216 +#define TX_VLAN_TAG_ON BIT_25  /* Enable  VLAN tagging */
3217 +#define TX_VLAN_TAG_OFF        BIT_24  /* Disable VLAN tagging */
3218 +#define TX_PCI_JUM_ENA BIT_23  /* Enable  PCI Jumbo Mode (Yukon-EC Ultra) */
3219 +#define TX_PCI_JUM_DIS BIT_22  /* Disable PCI Jumbo Mode (Yukon-EC Ultra) */
3220 +                                               /* Bits 21..19: reserved */
3221 +#define GMF_WSP_TST_ON BIT_18  /* Write Shadow Pointer Test On */
3222 +#define GMF_WSP_TST_OFF        BIT_17  /* Write Shadow Pointer Test Off */
3223 +#define GMF_WSP_STEP   BIT_16  /* Write Shadow Pointer Step/Increment */
3224 +                                               /* Bits 15..8: same as for RX_GMF_CTRL_T */
3225 +                                               /* Bit 7:       reserved */
3226 +#define GMF_CLI_TX_FU  BIT_6   /* Clear IRQ Tx FIFO Underrun */
3227 +#define GMF_CLI_TX_FC  BIT_5   /* Clear IRQ Tx Frame Complete */
3228 +#define GMF_CLI_TX_PE  BIT_4   /* Clear IRQ Tx Parity Error */
3229                                                 /* Bits 3..0: same as for RX_GMF_CTRL_T */
3230
3231  #define GMF_RX_CTRL_DEF                (GMF_OPER_ON | GMF_RX_F_FL_ON)
3232  #define GMF_TX_CTRL_DEF                GMF_OPER_ON
3233
3234 +#define RX_GMF_AF_THR_MIN      0x0c    /* Rx GMAC FIFO Almost Full Thresh. min. */
3235  #define RX_GMF_FL_THR_DEF      0x0a    /* Rx GMAC FIFO Flush Threshold default */
3236
3237  /*     GMAC_TI_ST_CTRL  8 bit  Time Stamp Timer Ctrl Reg (YUKON only) */
3238 -                                                               /* Bit 7.. 3:   reserved */
3239 -#define GMT_ST_START   BIT_2S          /* Start Time Stamp Timer */
3240 -#define GMT_ST_STOP            BIT_1S          /* Stop  Time Stamp Timer */
3241 -#define GMT_ST_CLR_IRQ BIT_0S          /* Clear Time Stamp Timer IRQ */
3242 -
3243 +                                                       /* Bit 7.. 3:   reserved */
3244 +#define GMT_ST_START   BIT_2S  /* Start Time Stamp Timer */
3245 +#define GMT_ST_STOP            BIT_1S  /* Stop  Time Stamp Timer */
3246 +#define GMT_ST_CLR_IRQ BIT_0S  /* Clear Time Stamp Timer IRQ */
3247 +
3248 +/*     POLL_CTRL               32 bit  Polling Unit control register (Yukon-2 only) */
3249 +                                                       /* Bit 31.. 6:  reserved */
3250 +#define PC_CLR_IRQ_CHK BIT_5   /* Clear IRQ Check */
3251 +#define PC_POLL_RQ             BIT_4   /* Poll Request Start */
3252 +#define PC_POLL_OP_ON  BIT_3   /* Operational Mode On */
3253 +#define PC_POLL_OP_OFF BIT_2   /* Operational Mode Off */
3254 +#define PC_POLL_RST_CLR        BIT_1   /* Clear Polling Unit Reset (Enable) */
3255 +#define PC_POLL_RST_SET        BIT_0   /* Set   Polling Unit Reset */
3256 +
3257 +
3258 +/* The bit definition of the following registers is still missing! */
3259 +/* B28_Y2_SMB_CONFIG           32 bit  ASF SMBus Config Register */
3260 +/* B28_Y2_SMB_CSD_REG          32 bit  ASF SMB Control/Status/Data */
3261 +/* B28_Y2_ASF_IRQ_V_BASE       32 bit  ASF IRQ Vector Base */
3262 +
3263 +/* B28_Y2_ASF_STAT_CMD         32 bit  ASF Status and Command Reg */
3264 +/* This register is used by the host driver software */
3265 +                                                       /* Bit 31.. 5   reserved */
3266 +#define Y2_ASF_OS_PRES BIT_4S  /* ASF operation system present */
3267 +#define Y2_ASF_RESET   BIT_3S  /* ASF system in reset state */
3268 +#define Y2_ASF_RUNNING BIT_2S  /* ASF system operational */
3269 +#define Y2_ASF_CLR_HSTI        BIT_1S  /* Clear ASF IRQ */
3270 +#define Y2_ASF_IRQ             BIT_0S  /* Issue an IRQ to ASF system */
3271 +
3272 +#define Y2_ASF_UC_STATE        (3<<2)  /* ASF uC State */
3273 +#define Y2_ASF_CLK_HALT        0               /* ASF system clock stopped */
3274 +
3275 +/* B28_Y2_ASF_HOST_COM 32 bit  ASF Host Communication Reg */
3276 +/* This register is used by the ASF firmware */
3277 +                                                       /* Bit 31.. 2   reserved */
3278 +#define Y2_ASF_CLR_ASFI        BIT_1   /* Clear host IRQ */
3279 +#define Y2_ASF_HOST_IRQ        BIT_0   /* Issue an IRQ to HOST system */
3280 +
3281 +
3282 +/*     STAT_CTRL               32 bit  Status BMU control register (Yukon-2 only) */
3283 +                                                       /* Bit  7.. 5:  reserved */
3284 +#define SC_STAT_CLR_IRQ        BIT_4   /* Status Burst IRQ clear */
3285 +#define SC_STAT_OP_ON  BIT_3   /* Operational Mode On */
3286 +#define SC_STAT_OP_OFF BIT_2   /* Operational Mode Off */
3287 +#define SC_STAT_RST_CLR        BIT_1   /* Clear Status Unit Reset (Enable) */
3288 +#define SC_STAT_RST_SET        BIT_0   /* Set   Status Unit Reset */
3289 +
3290  /*     GMAC_CTRL               32 bit  GMAC Control Reg (YUKON only) */
3291                                                 /* Bits 31.. 8: reserved */
3292 -#define GMC_H_BURST_ON BIT_7           /* Half Duplex Burst Mode On */
3293 -#define GMC_H_BURST_OFF        BIT_6           /* Half Duplex Burst Mode Off */
3294 -#define GMC_F_LOOPB_ON BIT_5           /* FIFO Loopback On */
3295 -#define GMC_F_LOOPB_OFF        BIT_4           /* FIFO Loopback Off */
3296 -#define GMC_PAUSE_ON   BIT_3           /* Pause On */
3297 -#define GMC_PAUSE_OFF  BIT_2           /* Pause Off */
3298 -#define GMC_RST_CLR            BIT_1           /* Clear GMAC Reset */
3299 -#define GMC_RST_SET            BIT_0           /* Set   GMAC Reset */
3300 +#define GMC_H_BURST_ON BIT_7   /* Half Duplex Burst Mode On */
3301 +#define GMC_H_BURST_OFF        BIT_6   /* Half Duplex Burst Mode Off */
3302 +#define GMC_F_LOOPB_ON BIT_5   /* FIFO Loopback On */
3303 +#define GMC_F_LOOPB_OFF        BIT_4   /* FIFO Loopback Off */
3304 +#define GMC_PAUSE_ON   BIT_3   /* Pause On */
3305 +#define GMC_PAUSE_OFF  BIT_2   /* Pause Off */
3306 +#define GMC_RST_CLR            BIT_1   /* Clear GMAC Reset */
3307 +#define GMC_RST_SET            BIT_0   /* Set   GMAC Reset */
3308
3309  /*     GPHY_CTRL               32 bit  GPHY Control Reg (YUKON only) */
3310                                                 /* Bits 31..29: reserved */
3311  #define GPC_SEL_BDT            BIT_28  /* Select Bi-Dir. Transfer for MDC/MDIO */
3312 -#define GPC_INT_POL_HI BIT_27  /* IRQ Polarity is Active HIGH */
3313 +#define GPC_INT_POL            BIT_27  /* IRQ Polarity is Active Low */
3314  #define GPC_75_OHM             BIT_26  /* Use 75 Ohm Termination instead of 50 */
3315  #define GPC_DIS_FC             BIT_25  /* Disable Automatic Fiber/Copper Detection */
3316  #define GPC_DIS_SLEEP  BIT_24  /* Disable Energy Detect */
3317 @@ -1501,15 +2159,24 @@
3318  #define GPC_ANEG_2             BIT_15  /* ANEG[2] */
3319  #define GPC_ANEG_1             BIT_14  /* ANEG[1] */
3320  #define GPC_ENA_PAUSE  BIT_13  /* Enable Pause (SYM_OR_REM) */
3321 -#define GPC_PHYADDR_4  BIT_12  /* Bit 4 of Phy Addr */
3322 -#define GPC_PHYADDR_3  BIT_11  /* Bit 3 of Phy Addr */
3323 -#define GPC_PHYADDR_2  BIT_10  /* Bit 2 of Phy Addr */
3324 -#define GPC_PHYADDR_1  BIT_9   /* Bit 1 of Phy Addr */
3325 -#define GPC_PHYADDR_0  BIT_8   /* Bit 0 of Phy Addr */
3326 +#define GPC_PHYADDR_4  BIT_12  /* Bit 4 of PHY Addr */
3327 +#define GPC_PHYADDR_3  BIT_11  /* Bit 3 of PHY Addr */
3328 +#define GPC_PHYADDR_2  BIT_10  /* Bit 2 of PHY Addr */
3329 +#define GPC_PHYADDR_1  BIT_9   /* Bit 1 of PHY Addr */
3330 +#define GPC_PHYADDR_0  BIT_8   /* Bit 0 of PHY Addr */
3331                                                 /* Bits  7..2:  reserved */
3332  #define GPC_RST_CLR            BIT_1   /* Clear GPHY Reset */
3333  #define GPC_RST_SET            BIT_0   /* Set   GPHY Reset */
3334
3335 +/* Yukon-EC Ultra only */
3336 +#define GPC_LED_CONF_MSK       (7<<6)  /* Bit 8.. 6:   GPHY LED Config */
3337 +#define GPC_PD_125M_CLK_OFF    BIT_5   /* Disable Power Down Clock 125 MHz */
3338 +#define GPC_PD_125M_CLK_ON     BIT_4   /* Enable  Power Down Clock 125 MHz */
3339 +#define GPC_DPLL_RST_SET       BIT_3   /* Set   GPHY's DPLL Reset */
3340 +#define GPC_DPLL_RST_CLR       BIT_2   /* Clear GPHY's DPLL Reset */
3341 +                                                                       /* (DPLL = Digital Phase Lock Loop) */
3342 +#define GPC_LED_CONF_VAL(x)    (SHIFT6(x) & GPC_LED_CONF_MSK)
3343 +
3344  #define GPC_HWCFG_GMII_COP     (GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | \
3345                                                          GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
3346
3347 @@ -1540,20 +2207,20 @@
3348
3349  /*     GMAC_IRQ_SRC     8 bit  GMAC Interrupt Source Reg (YUKON only) */
3350  /*     GMAC_IRQ_MSK     8 bit  GMAC Interrupt Mask   Reg (YUKON only) */
3351 -#define GM_IS_TX_CO_OV BIT_5           /* Transmit Counter Overflow IRQ */
3352 -#define GM_IS_RX_CO_OV BIT_4           /* Receive Counter Overflow IRQ */
3353 -#define GM_IS_TX_FF_UR BIT_3           /* Transmit FIFO Underrun */
3354 -#define GM_IS_TX_COMPL BIT_2           /* Frame Transmission Complete */
3355 -#define GM_IS_RX_FF_OR BIT_1           /* Receive FIFO Overrun */
3356 -#define GM_IS_RX_COMPL BIT_0           /* Frame Reception Complete */
3357 +#define GM_IS_RX_CO_OV BIT_5S          /* Receive Counter Overflow IRQ */
3358 +#define GM_IS_TX_CO_OV BIT_4S          /* Transmit Counter Overflow IRQ */
3359 +#define GM_IS_TX_FF_UR BIT_3S          /* Transmit FIFO Underrun */
3360 +#define GM_IS_TX_COMPL BIT_2S          /* Frame Transmission Complete */
3361 +#define GM_IS_RX_FF_OR BIT_1S          /* Receive FIFO Overrun */
3362 +#define GM_IS_RX_COMPL BIT_0S          /* Frame Reception Complete */
3363
3364 -#define GMAC_DEF_MSK   (GM_IS_TX_CO_OV | GM_IS_RX_CO_OV | \
3365 +#define GMAC_DEF_MSK   (GM_IS_RX_CO_OV | GM_IS_TX_CO_OV | \
3366                                                 GM_IS_TX_FF_UR)
3367
3368 -/*     GMAC_LINK_CTRL  16 bit  GMAC Link Control Reg (YUKON only) */
3369 +/*     GMAC_LINK_CTRL  16 bit  Link Control Reg (YUKON only) */
3370                                                 /* Bits 15.. 2: reserved */
3371 -#define GMLC_RST_CLR   BIT_1S          /* Clear GMAC Link Reset */
3372 -#define GMLC_RST_SET   BIT_0S          /* Set   GMAC Link Reset */
3373 +#define GMLC_RST_CLR   BIT_1S          /* Clear Link Reset */
3374 +#define GMLC_RST_SET   BIT_0S          /* Set   Link Reset */
3375
3376
3377  /*     WOL_CTRL_STAT   16 bit  WOL Control/Status Reg */
3378 @@ -1579,15 +2246,19 @@
3379
3380  #define WOL_CTL_DEFAULT                                \
3381         (WOL_CTL_DIS_PME_ON_LINK_CHG |  \
3382 -       WOL_CTL_DIS_PME_ON_PATTERN |    \
3383 -       WOL_CTL_DIS_PME_ON_MAGIC_PKT |  \
3384 -       WOL_CTL_DIS_LINK_CHG_UNIT |             \
3385 -       WOL_CTL_DIS_PATTERN_UNIT |              \
3386 -       WOL_CTL_DIS_MAGIC_PKT_UNIT)
3387 +        WOL_CTL_DIS_PME_ON_PATTERN |   \
3388 +        WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
3389 +        WOL_CTL_DIS_LINK_CHG_UNIT |    \
3390 +        WOL_CTL_DIS_PATTERN_UNIT |             \
3391 +        WOL_CTL_DIS_MAGIC_PKT_UNIT)
3392
3393  /*     WOL_MATCH_CTL    8 bit  WOL Match Control Reg */
3394  #define WOL_CTL_PATT_ENA(x)                            (BIT_0 << (x))
3395
3396 +/*     WOL_PATT_PME    8 bit   WOL PME Match Enable (Yukon-2) */
3397 +#define WOL_PATT_FORCE_PME                             BIT_7   /* Generates a PME */
3398 +#define WOL_PATT_MATCH_PME_ALL                 0x7f
3399 +
3400  #define SK_NUM_WOL_PATTERN             7
3401  #define SK_PATTERN_PER_WORD            4
3402  #define SK_BITMASK_PATTERN             7
3403 @@ -1597,26 +2268,28 @@
3404  #define WOL_LENGTH_SHIFT       8
3405
3406
3407 +/* typedefs ******************************************************************/
3408 +
3409  /* Receive and Transmit Descriptors ******************************************/
3410
3411  /* Transmit Descriptor struct */
3412  typedef        struct s_HwTxd {
3413         SK_U32 volatile TxCtrl; /* Transmit Buffer Control Field */
3414         SK_U32  TxNext;                 /* Physical Address Pointer to the next TxD */
3415 -       SK_U32  TxAdrLo;                /* Physical Tx Buffer Address lower dword */
3416 -       SK_U32  TxAdrHi;                /* Physical Tx Buffer Address upper dword */
3417 +       SK_U32  TxAdrLo;                /* Physical Tx Buffer Address lower DWord */
3418 +       SK_U32  TxAdrHi;                /* Physical Tx Buffer Address upper DWord */
3419         SK_U32  TxStat;                 /* Transmit Frame Status Word */
3420 -#ifndef        SK_USE_REV_DESC
3421 +#ifndef SK_USE_REV_DESC
3422         SK_U16  TxTcpOffs;              /* TCP Checksum Calculation Start Value */
3423         SK_U16  TxRes1;                 /* 16 bit reserved field */
3424         SK_U16  TxTcpWp;                /* TCP Checksum Write Position */
3425         SK_U16  TxTcpSp;                /* TCP Checksum Calculation Start Position */
3426 -#else  /* SK_USE_REV_DESC */
3427 +#else  /* SK_USE_REV_DESC */
3428         SK_U16  TxRes1;                 /* 16 bit reserved field */
3429         SK_U16  TxTcpOffs;              /* TCP Checksum Calculation Start Value */
3430         SK_U16  TxTcpSp;                /* TCP Checksum Calculation Start Position */
3431         SK_U16  TxTcpWp;                /* TCP Checksum Write Position */
3432 -#endif /* SK_USE_REV_DESC */
3433 +#endif /* SK_USE_REV_DESC */
3434         SK_U32  TxRes2;                 /* 32 bit reserved field */
3435  } SK_HWTXD;
3436
3437 @@ -1624,33 +2297,266 @@
3438  typedef        struct s_HwRxd {
3439         SK_U32 volatile RxCtrl; /* Receive Buffer Control Field */
3440         SK_U32  RxNext;                 /* Physical Address Pointer to the next RxD */
3441 -       SK_U32  RxAdrLo;                /* Physical Rx Buffer Address lower dword */
3442 -       SK_U32  RxAdrHi;                /* Physical Rx Buffer Address upper dword */
3443 +       SK_U32  RxAdrLo;                /* Physical Rx Buffer Address lower DWord */
3444 +       SK_U32  RxAdrHi;                /* Physical Rx Buffer Address upper DWord */
3445         SK_U32  RxStat;                 /* Receive Frame Status Word */
3446         SK_U32  RxTiSt;                 /* Receive Time Stamp (from XMAC on GENESIS) */
3447 -#ifndef        SK_USE_REV_DESC
3448 -       SK_U16  RxTcpSum1;              /* TCP Checksum 1 */
3449 -       SK_U16  RxTcpSum2;              /* TCP Checksum 2 */
3450 +#ifndef SK_USE_REV_DESC
3451 +       SK_U16  RxTcpSum1;              /* Rx TCP Checksum 1 */
3452 +       SK_U16  RxTcpSum2;              /* Rx TCP Checksum 2 */
3453         SK_U16  RxTcpSp1;               /* TCP Checksum Calculation Start Position 1 */
3454         SK_U16  RxTcpSp2;               /* TCP Checksum Calculation Start Position 2 */
3455 -#else  /* SK_USE_REV_DESC */
3456 -       SK_U16  RxTcpSum2;              /* TCP Checksum 2 */
3457 -       SK_U16  RxTcpSum1;              /* TCP Checksum 1 */
3458 +#else  /* SK_USE_REV_DESC */
3459 +       SK_U16  RxTcpSum2;              /* Rx TCP Checksum 2 */
3460 +       SK_U16  RxTcpSum1;              /* Rx TCP Checksum 1 */
3461         SK_U16  RxTcpSp2;               /* TCP Checksum Calculation Start Position 2 */
3462         SK_U16  RxTcpSp1;               /* TCP Checksum Calculation Start Position 1 */
3463 -#endif /* SK_USE_REV_DESC */
3464 +#endif /* SK_USE_REV_DESC */
3465  } SK_HWRXD;
3466
3467  /*
3468   * Drivers which use the reverse descriptor feature (PCI_OUR_REG_2)
3469   * should set the define SK_USE_REV_DESC.
3470 - * Structures are 'normaly' not endianess dependent. But in
3471 - * this case the SK_U16 fields are bound to bit positions inside the
3472 - * descriptor. RxTcpSum1 e.g. must start at bit 0 within the 6.th DWord.
3473 + * Structures are 'normally' not endianess dependent. But in this case
3474 + * the SK_U16 fields are bound to bit positions inside the descriptor.
3475 + * RxTcpSum1 e.g. must start at bit 0 within the 7.th DWord.
3476   * The bit positions inside a DWord are of course endianess dependent and
3477 - * swaps if the DWord is swapped by the hardware.
3478 + * swap if the DWord is swapped by the hardware.
3479   */
3480
3481 +/* YUKON-2 descriptors ******************************************************/
3482 +
3483 +typedef struct _TxChksum {
3484 +#ifndef SK_USE_REV_DESC
3485 +       SK_U16  TxTcpWp;                /* TCP Checksum Write Position */
3486 +       SK_U16  TxTcpSp;                /* TCP Checksum Calculation Start Position */
3487 +#else  /* SK_USE_REV_DESC */
3488 +       SK_U16  TxTcpSp;                /* TCP Checksum Calculation Start Position */
3489 +       SK_U16  TxTcpWp;                /* TCP Checksum Write Position */
3490 +#endif /* SK_USE_REV_DESC */
3491 +} SK_HWTXCS;
3492 +
3493 +typedef struct _LargeSend {
3494 +#ifndef SK_USE_REV_DESC
3495 +       SK_U16 Length;          /* Large Send Segment Length */
3496 +       SK_U16 Reserved;        /* reserved */
3497 +#else  /* SK_USE_REV_DESC */
3498 +       SK_U16 Reserved;        /* reserved */
3499 +       SK_U16 Length;          /* Large Send Segment Length */
3500 +#endif /* SK_USE_REV_DESC */
3501 +} SK_HWTXLS;
3502 +
3503 +typedef union u_HwTxBuf {
3504 +       SK_U16  BufLen;         /* Tx Buffer Length */
3505 +       SK_U16  VlanTag;        /* VLAN Tag */
3506 +       SK_U16  InitCsum;       /* Init. Checksum */
3507 +} SK_HWTXBUF;
3508 +
3509 +/* Tx List Element structure */
3510 +typedef struct s_HwLeTx {
3511 +       union {
3512 +               SK_U32  BufAddr;        /* Tx LE Buffer Address high/low */
3513 +               SK_HWTXCS ChkSum;       /* Tx LE TCP Checksum parameters */
3514 +               SK_HWTXLS LargeSend;/* Large Send length */
3515 +       } TxUn;
3516 +#ifndef SK_USE_REV_DESC
3517 +       SK_HWTXBUF      Send;
3518 +       SK_U8   ControlFlags;   /* Tx LE Control field or Lock Number */
3519 +       SK_U8   Opcode;                 /* Tx LE Opcode field */
3520 +#else  /* SK_USE_REV_DESC */
3521 +       SK_U8   Opcode;                 /* Tx LE Opcode field */
3522 +       SK_U8   ControlFlags;   /* Tx LE Control field or Lock Number */
3523 +       SK_HWTXBUF      Send;
3524 +#endif /* SK_USE_REV_DESC */
3525 +} SK_HWLETX;
3526 +
3527 +typedef struct _RxChkSum{
3528 +#ifndef SK_USE_REV_DESC
3529 +       SK_U16  RxTcpSp1;               /* TCP Checksum Calculation Start Position 1 */
3530 +       SK_U16  RxTcpSp2;               /* TCP Checksum Calculation Start Position 2 */
3531 +#else  /* SK_USE_REV_DESC */
3532 +       SK_U16  RxTcpSp2;               /* TCP Checksum Calculation Start Position 2 */
3533 +       SK_U16  RxTcpSp1;               /* TCP Checksum Calculation Start Position 1 */
3534 +#endif /* SK_USE_REV_DESC */
3535 +} SK_HWRXCS;
3536 +
3537 +/* Rx List Element structure */
3538 +typedef struct s_HwLeRx {
3539 +       union {
3540 +               SK_U32  BufAddr;        /* Rx LE Buffer Address high/low */
3541 +               SK_HWRXCS ChkSum;       /* Rx LE TCP Checksum parameters */
3542 +       } RxUn;
3543 +#ifndef SK_USE_REV_DESC
3544 +       SK_U16  BufferLength;   /* Rx LE Buffer Length field */
3545 +       SK_U8   ControlFlags;   /* Rx LE Control field */
3546 +       SK_U8   Opcode;                 /* Rx LE Opcode field */
3547 +#else  /* SK_USE_REV_DESC */
3548 +       SK_U8   Opcode;                 /* Rx LE Opcode field */
3549 +       SK_U8   ControlFlags;   /* Rx LE Control field */
3550 +       SK_U16  BufferLength;   /* Rx LE Buffer Length field */
3551 +#endif /* SK_USE_REV_DESC */
3552 +} SK_HWLERX;
3553 +
3554 +typedef struct s_StRxTCPChkSum {
3555 +#ifndef SK_USE_REV_DESC
3556 +       SK_U16  RxTCPSum1;              /* Rx TCP Checksum 1 */
3557 +       SK_U16  RxTCPSum2;              /* Rx TCP Checksum 2 */
3558 +#else  /* SK_USE_REV_DESC */
3559 +       SK_U16  RxTCPSum2;              /* Rx TCP Checksum 2 */
3560 +       SK_U16  RxTCPSum1;              /* Rx TCP Checksum 1 */
3561 +#endif /* SK_USE_REV_DESC */
3562 +} SK_HWSTCS;
3563 +
3564 +typedef struct s_StRxRssFlags {
3565 +#ifndef SK_USE_REV_DESC
3566 +       SK_U8   FlagField;              /* contains TCP and IP flags */
3567 +       SK_U8   reserved;               /* reserved */
3568 +#else  /* SK_USE_REV_DESC */
3569 +       SK_U8   reserved;               /* reserved */
3570 +       SK_U8   FlagField;              /* contains TCP and IP flags */
3571 +#endif /* SK_USE_REV_DESC */
3572 +} SK_HWSTRSS;
3573 +
3574 +/* bit definition of RSS LE bit 32/33 (SK_HWSTRSS.FlagField) */
3575 +                                                               /* bit 7..2 reserved */
3576 +#define RSS_TCP_FLAG   BIT_1S  /* RSS value related to TCP area */
3577 +#define RSS_IP_FLAG            BIT_0S  /* RSS value related to IP area */
3578 +/* StRxRssValue is valid if at least RSS_IP_FLAG is set */
3579 +/* For protocol errors or other protocols an empty RSS LE is generated */
3580 +
3581 +typedef union u_HwStBuf {
3582 +       SK_U16  BufLen;         /* Rx Buffer Length */
3583 +       SK_U16  VlanTag;        /* VLAN Tag */
3584 +       SK_U16  StTxStatHi;     /* Tx Queue Status (high) */
3585 +       SK_HWSTRSS      Rss;    /* Flag Field for TCP and IP protocol */
3586 +} SK_HWSTBUF;
3587 +
3588 +/* Status List Element structure */
3589 +typedef struct s_HwLeSt {
3590 +       union {
3591 +               SK_U32  StRxStatWord;   /* Rx Status Dword */
3592 +               SK_U32  StRxTimeStamp;  /* Rx Timestamp */
3593 +               SK_HWSTCS StRxTCPCSum;  /* Rx TCP Checksum */
3594 +               SK_U32  StTxStatLow;    /* Tx Queue Status (low) */
3595 +               SK_U32  StRxRssValue;   /* Rx RSS value */
3596 +       } StUn;
3597 +#ifndef SK_USE_REV_DESC
3598 +       SK_HWSTBUF      Stat;
3599 +       SK_U8   Link;                   /* Status LE Link field */
3600 +       SK_U8   Opcode;                 /* Status LE Opcode field */
3601 +#else  /* SK_USE_REV_DESC */
3602 +       SK_U8   Opcode;                 /* Status LE Opcode field */
3603 +       SK_U8   Link;                   /* Status LE Link field */
3604 +       SK_HWSTBUF      Stat;
3605 +#endif /* SK_USE_REV_DESC */
3606 +} SK_HWLEST;
3607 +
3608 +/* Special Action List Element */
3609 +typedef struct s_HwLeSa {
3610 +#ifndef SK_USE_REV_DESC
3611 +       SK_U16  TxAIdxVld;              /* Special Action LE TxA Put Index field */
3612 +       SK_U16  TxSIdxVld;              /* Special Action LE TxS Put Index field */
3613 +       SK_U16  RxIdxVld;               /* Special Action LE Rx Put Index field */
3614 +       SK_U8   Link;                   /* Special Action LE Link field */
3615 +       SK_U8   Opcode;                 /* Special Action LE Opcode field */
3616 +#else  /* SK_USE_REV_DESC */
3617 +       SK_U16  TxSIdxVld;              /* Special Action LE TxS Put Index field */
3618 +       SK_U16  TxAIdxVld;              /* Special Action LE TxA Put Index field */
3619 +       SK_U8   Opcode;                 /* Special Action LE Opcode field */
3620 +       SK_U8   Link;                   /* Special Action LE Link field */
3621 +       SK_U16  RxIdxVld;               /* Special Action LE Rx Put Index field */
3622 +#endif /* SK_USE_REV_DESC */
3623 +} SK_HWLESA;
3624 +
3625 +/* Common List Element union */
3626 +typedef union u_HwLeTxRxSt {
3627 +       /* Transmit List Element Structure */
3628 +       SK_HWLETX Tx;
3629 +       /* Receive List Element Structure */
3630 +       SK_HWLERX Rx;
3631 +       /* Status List Element Structure */
3632 +       SK_HWLEST St;
3633 +       /* Special Action List Element Structure */
3634 +       SK_HWLESA Sa;
3635 +       /* Full List Element */
3636 +       SK_U64 Full;
3637 +} SK_HWLE;
3638 +
3639 +/* mask and shift value to get Tx async queue status for port 1 */
3640 +#define STLE_TXA1_MSKL         0x00000fff
3641 +#define STLE_TXA1_SHIFTL       0
3642 +
3643 +/* mask and shift value to get Tx sync queue status for port 1 */
3644 +#define STLE_TXS1_MSKL         0x00fff000
3645 +#define STLE_TXS1_SHIFTL       12
3646 +
3647 +/* mask and shift value to get Tx async queue status for port 2 */
3648 +#define STLE_TXA2_MSKL         0xff000000
3649 +#define STLE_TXA2_SHIFTL       24
3650 +#define STLE_TXA2_MSKH         0x000f
3651 +/* this one shifts up */
3652 +#define STLE_TXA2_SHIFTH       8
3653 +
3654 +/* mask and shift value to get Tx sync queue status for port 2 */
3655 +#define STLE_TXS2_MSKL         0x00000000
3656 +#define STLE_TXS2_SHIFTL       0
3657 +#define STLE_TXS2_MSKH         0xfff0
3658 +#define STLE_TXS2_SHIFTH       4
3659 +
3660 +/* YUKON-2 bit values */
3661 +#define HW_OWNER               BIT_7
3662 +#define SW_OWNER               0
3663 +
3664 +#define PU_PUTIDX_VALID                BIT_12
3665 +
3666 +/* YUKON-2 Control flags */
3667 +#define UDPTCP                 BIT_0S
3668 +#define CALSUM                 BIT_1S
3669 +#define WR_SUM                 BIT_2S
3670 +#define INIT_SUM               BIT_3S
3671 +#define LOCK_SUM               BIT_4S
3672 +#define INS_VLAN               BIT_5S
3673 +#define FRC_STAT               BIT_6S
3674 +#define EOP                            BIT_7S
3675 +
3676 +#define TX_LOCK                        BIT_8S
3677 +#define BUF_SEND               BIT_9S
3678 +#define PACKET_SEND            BIT_10S
3679 +
3680 +#define NO_WARNING             BIT_14S
3681 +#define NO_UPDATE              BIT_15S
3682 +
3683 +/* YUKON-2 Rx/Tx opcodes defines */
3684 +#define OP_TCPWRITE            0x11
3685 +#define OP_TCPSTART            0x12
3686 +#define OP_TCPINIT             0x14
3687 +#define OP_TCPLCK              0x18
3688 +#define OP_TCPCHKSUM   OP_TCPSTART
3689 +#define OP_TCPIS               (OP_TCPINIT | OP_TCPSTART)
3690 +#define OP_TCPLW               (OP_TCPLCK | OP_TCPWRITE)
3691 +#define OP_TCPLSW              (OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE)
3692 +#define OP_TCPLISW             (OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE)
3693 +#define OP_ADDR64              0x21
3694 +#define OP_VLAN                0x22
3695 +#define OP_ADDR64VLAN  (OP_ADDR64 | OP_VLAN)
3696 +#define OP_LRGLEN              0x24
3697 +#define OP_LRGLENVLAN  (OP_LRGLEN | OP_VLAN)
3698 +#define OP_BUFFER              0x40
3699 +#define OP_PACKET              0x41
3700 +#define OP_LARGESEND   0x43
3701 +
3702 +/* YUKON-2 STATUS opcodes defines */
3703 +#define OP_RXSTAT              0x60
3704 +#define OP_RXTIMESTAMP 0x61
3705 +#define OP_RXVLAN              0x62
3706 +#define OP_RXCHKS              0x64
3707 +#define OP_RXCHKSVLAN  (OP_RXCHKS | OP_RXVLAN)
3708 +#define OP_RXTIMEVLAN  (OP_RXTIMESTAMP | OP_RXVLAN)
3709 +#define OP_RSS_HASH            0x65
3710 +#define OP_TXINDEXLE   0x68
3711 +
3712 +/* YUKON-2 SPECIAL opcodes defines */
3713 +#define OP_PUTIDX      0x70
3714
3715  /* Descriptor Bit Definition */
3716  /*     TxCtrl          Transmit Buffer Control Field */
3717 @@ -1685,6 +2591,10 @@
3718
3719  /* macros ********************************************************************/
3720
3721 +/* Macro for accessing the key registers */
3722 +#define RSS_KEY_ADDR(Port, KeyIndex)   \
3723 +               ((B4_RSS_KEY | ( ((Port) == 0) ? 0 : 0x80)) + (KeyIndex))
3724 +
3725  /* Receive and Transmit Queues */
3726  #define Q_R1   0x0000          /* Receive Queue 1 */
3727  #define Q_R2   0x0080          /* Receive Queue 2 */
3728 @@ -1693,6 +2603,10 @@
3729  #define Q_XS2  0x0300          /* Synchronous Transmit Queue 2 */
3730  #define Q_XA2  0x0380          /* Asynchronous Transmit Queue 2 */
3731
3732 +#define Q_ASF_R1       0x100   /* ASF Rx Queue 1 */
3733 +#define Q_ASF_R2       0x180   /* ASF Rx Queue 2 */
3734 +#define Q_ASF_T1       0x140   /* ASF Tx Queue 1 */
3735 +#define Q_ASF_T2       0x1c0   /* ASF Tx Queue 2 */
3736  /*
3737   *     Macro Q_ADDR()
3738   *
3739 @@ -1704,11 +2618,27 @@
3740   *     Offs    Queue register offset.
3741   *                             Values: Q_D, Q_DA_L ... Q_T2, Q_T3
3742   *
3743 - * usage       SK_IN32(pAC, Q_ADDR(Q_R2, Q_BC), pVal)
3744 + * usage       SK_IN32(IoC, Q_ADDR(Q_R2, Q_BC), pVal)
3745   */
3746  #define Q_ADDR(Queue, Offs)    (B8_Q_REGS + (Queue) + (Offs))
3747
3748  /*
3749 + *     Macro Y2_PREF_Q_ADDR()
3750 + *
3751 + *     Use this macro to access the Prefetch Units of the receive and
3752 + *     transmit queues of Yukon-2.
3753 + *
3754 + * para:
3755 + *     Queue   Queue to access.
3756 + *                             Values: Q_R1, Q_R2, Q_XS1, Q_XA1, Q_XS2, Q_XA2,
3757 + *     Offs    Queue register offset.
3758 + *                             Values: PREF_UNIT_CTRL_REG ... PREF_UNIT_FIFO_LEV_REG
3759 + *
3760 + * usage       SK_IN16(IoC, Y2_Q_ADDR(Q_R2, PREF_UNIT_GET_IDX_REG), pVal)
3761 + */
3762 +#define Y2_PREF_Q_ADDR(Queue, Offs)    (Y2_B8_PREF_REGS + (Queue) + (Offs))
3763 +
3764 +/*
3765   *     Macro RB_ADDR()
3766   *
3767   *     Use this macro to access the RAM Buffer Registers.
3768 @@ -1719,14 +2649,14 @@
3769   *     Offs    Queue register offset.
3770   *                             Values: RB_START, RB_END ... RB_LEV, RB_CTRL
3771   *
3772 - * usage       SK_IN32(pAC, RB_ADDR(Q_R2, RB_RP), pVal)
3773 + * usage       SK_IN32(IoC, RB_ADDR(Q_R2, RB_RP), pVal)
3774   */
3775  #define RB_ADDR(Queue, Offs)   (B16_RAM_REGS + (Queue) + (Offs))
3776
3777
3778  /* MAC Related Registers */
3779 -#define MAC_1          0       /* belongs to the port near the slot */
3780 -#define MAC_2          1       /* belongs to the port far away from the slot */
3781 +#define MAC_1          0       /* 1st port */
3782 +#define MAC_2          1       /* 2nd port */
3783
3784  /*
3785   *     Macro MR_ADDR()
3786 @@ -1740,19 +2670,10 @@
3787   *                             Values: RX_MFF_EA, RX_MFF_WP ... LNK_LED_REG,
3788   *                                             TX_MFF_EA, TX_MFF_WP ... TX_LED_TST
3789   *
3790 - * usage       SK_IN32(pAC, MR_ADDR(MAC_1, TX_MFF_EA), pVal)
3791 + * usage       SK_IN32(IoC, MR_ADDR(MAC_1, TX_MFF_EA), pVal)
3792   */
3793  #define MR_ADDR(Mac, Offs)     (((Mac) << 7) + (Offs))
3794
3795 -#ifdef SK_LITTLE_ENDIAN
3796 -#define XM_WORD_LO     0
3797 -#define XM_WORD_HI     1
3798 -#else  /* !SK_LITTLE_ENDIAN */
3799 -#define XM_WORD_LO     1
3800 -#define XM_WORD_HI     0
3801 -#endif /* !SK_LITTLE_ENDIAN */
3802 -
3803 -
3804  /*
3805   * macros to access the XMAC (GENESIS only)
3806   *
3807 @@ -1777,22 +2698,31 @@
3808  #define XMA(Mac, Reg)                                                                  \
3809         ((BASE_XMAC_1 + (Mac) * (BASE_XMAC_2 - BASE_XMAC_1)) | ((Reg) << 1))
3810
3811 -#define XM_IN16(IoC, Mac, Reg, pVal)                                   \
3812 -       SK_IN16((IoC), XMA((Mac), (Reg)), (pVal))
3813 +#define XM_IN16(IoC, Mac, Reg, pVal)   \
3814 +       SK_IN16(IoC, XMA(Mac, Reg), pVal)
3815
3816 -#define XM_OUT16(IoC, Mac, Reg, Val)                                   \
3817 -       SK_OUT16((IoC), XMA((Mac), (Reg)), (Val))
3818 +#define XM_OUT16(IoC, Mac, Reg, Val)   \
3819 +       SK_OUT16(IoC, XMA(Mac, Reg), Val)
3820
3821 -#define XM_IN32(IoC, Mac, Reg, pVal) {                                 \
3822 -       SK_IN16((IoC), XMA((Mac), (Reg)),                                       \
3823 -               (SK_U16 SK_FAR*)&((SK_U16 SK_FAR*)(pVal))[XM_WORD_LO]);         \
3824 -       SK_IN16((IoC), XMA((Mac), (Reg+2)),                                     \
3825 -               (SK_U16 SK_FAR*)&((SK_U16 SK_FAR*)(pVal))[XM_WORD_HI]);         \
3826 +#ifdef SK_LITTLE_ENDIAN
3827 +
3828 +#define XM_IN32(IoC, Mac, Reg, pVal) {                                                         \
3829 +       SK_IN16(IoC, XMA(Mac, Reg), (SK_U16 SK_FAR *)(pVal));                   \
3830 +       SK_IN16(IoC, XMA(Mac, (Reg) + 2), (SK_U16 SK_FAR *)(pVal) + 1); \
3831  }
3832
3833 +#else  /* !SK_LITTLE_ENDIAN */
3834 +
3835 +#define XM_IN32(IoC, Mac, Reg, pVal) {                                                 \
3836 +       SK_IN16(IoC, XMA(Mac, Reg), (SK_U16 SK_FAR *)(pVal) + 1);       \
3837 +       SK_IN16(IoC, XMA(Mac, (Reg) + 2), (SK_U16 SK_FAR *)(pVal));     \
3838 +}
3839 +
3840 +#endif /* !SK_LITTLE_ENDIAN */
3841 +
3842  #define XM_OUT32(IoC, Mac, Reg, Val) {                                                                         \
3843 -       SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16)((Val) & 0xffffL));                  \
3844 -       SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16)(((Val) >> 16) & 0xffffL));\
3845 +       SK_OUT16(IoC, XMA(Mac, Reg), (SK_U16)((Val) & 0xffffL));                                \
3846 +       SK_OUT16(IoC, XMA(Mac, (Reg) + 2), (SK_U16)(((Val) >> 16) & 0xffffL));  \
3847  }
3848
3849  /* Remember: we are always writing to / reading from LITTLE ENDIAN memory */
3850 @@ -1802,13 +2732,13 @@
3851         SK_U8   *pByte;                                                                         \
3852         pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0];                         \
3853         SK_IN16((IoC), XMA((Mac), (Reg)), &Word);                       \
3854 -       pByte[0] = (SK_U8)(Word  & 0x00ff);                                     \
3855 +       pByte[0] = (SK_U8)(Word & 0x00ff);                                      \
3856         pByte[1] = (SK_U8)((Word >> 8) & 0x00ff);                       \
3857 -       SK_IN16((IoC), XMA((Mac), (Reg+2)), &Word);                     \
3858 -       pByte[2] = (SK_U8)(Word  & 0x00ff);                                     \
3859 +       SK_IN16((IoC), XMA((Mac), (Reg) + 2), &Word);           \
3860 +       pByte[2] = (SK_U8)(Word & 0x00ff);                                      \
3861         pByte[3] = (SK_U8)((Word >> 8) & 0x00ff);                       \
3862 -       SK_IN16((IoC), XMA((Mac), (Reg+4)), &Word);                     \
3863 -       pByte[4] = (SK_U8)(Word  & 0x00ff);                                     \
3864 +       SK_IN16((IoC), XMA((Mac), (Reg) + 4), &Word);           \
3865 +       pByte[4] = (SK_U8)(Word & 0x00ff);                                      \
3866         pByte[5] = (SK_U8)((Word >> 8) & 0x00ff);                       \
3867  }
3868
3869 @@ -1818,10 +2748,10 @@
3870         SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16)                     \
3871                 (((SK_U16)(pByte[0]) & 0x00ff) |                                \
3872                 (((SK_U16)(pByte[1]) << 8) & 0xff00)));                 \
3873 -       SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16)           \
3874 +       SK_OUT16((IoC), XMA((Mac), (Reg) + 2), (SK_U16)         \
3875                 (((SK_U16)(pByte[2]) & 0x00ff) |                                \
3876                 (((SK_U16)(pByte[3]) << 8) & 0xff00)));                 \
3877 -       SK_OUT16((IoC), XMA((Mac), (Reg+4)), (SK_U16)           \
3878 +       SK_OUT16((IoC), XMA((Mac), (Reg) + 4), (SK_U16)         \
3879                 (((SK_U16)(pByte[4]) & 0x00ff) |                                \
3880                 (((SK_U16)(pByte[5]) << 8) & 0xff00)));                 \
3881  }
3882 @@ -1831,16 +2761,16 @@
3883         SK_U8   SK_FAR *pByte;                                                          \
3884         pByte = (SK_U8 SK_FAR *)&((SK_U8 SK_FAR *)(pVal))[0];   \
3885         SK_IN16((IoC), XMA((Mac), (Reg)), &Word);                       \
3886 -       pByte[0] = (SK_U8)(Word  & 0x00ff);                                     \
3887 +       pByte[0] = (SK_U8)(Word & 0x00ff);                                      \
3888         pByte[1] = (SK_U8)((Word >> 8) & 0x00ff);                       \
3889 -       SK_IN16((IoC), XMA((Mac), (Reg+2)), &Word);                     \
3890 -       pByte[2] = (SK_U8)(Word  & 0x00ff);                                     \
3891 +       SK_IN16((IoC), XMA((Mac), (Reg) + 2), &Word);           \
3892 +       pByte[2] = (SK_U8)(Word & 0x00ff);                                      \
3893         pByte[3] = (SK_U8)((Word >> 8) & 0x00ff);                       \
3894 -       SK_IN16((IoC), XMA((Mac), (Reg+4)), &Word);                     \
3895 -       pByte[4] = (SK_U8)(Word  & 0x00ff);                                     \
3896 +       SK_IN16((IoC), XMA((Mac), (Reg) + 4), &Word);           \
3897 +       pByte[4] = (SK_U8)(Word & 0x00ff);                                      \
3898         pByte[5] = (SK_U8)((Word >> 8) & 0x00ff);                       \
3899 -       SK_IN16((IoC), XMA((Mac), (Reg+6)), &Word);                     \
3900 -       pByte[6] = (SK_U8)(Word  & 0x00ff);                                     \
3901 +       SK_IN16((IoC), XMA((Mac), (Reg) + 6), &Word);           \
3902 +       pByte[6] = (SK_U8)(Word & 0x00ff);                                      \
3903         pByte[7] = (SK_U8)((Word >> 8) & 0x00ff);                       \
3904  }
3905
3906 @@ -1850,13 +2780,13 @@
3907         SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16)                     \
3908                 (((SK_U16)(pByte[0]) & 0x00ff)|                                 \
3909                 (((SK_U16)(pByte[1]) << 8) & 0xff00)));                 \
3910 -       SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16)           \
3911 +       SK_OUT16((IoC), XMA((Mac), (Reg) + 2), (SK_U16)         \
3912                 (((SK_U16)(pByte[2]) & 0x00ff)|                                 \
3913                 (((SK_U16)(pByte[3]) << 8) & 0xff00)));                 \
3914 -       SK_OUT16((IoC), XMA((Mac), (Reg+4)), (SK_U16)           \
3915 +       SK_OUT16((IoC), XMA((Mac), (Reg) + 4), (SK_U16)         \
3916                 (((SK_U16)(pByte[4]) & 0x00ff)|                                 \
3917                 (((SK_U16)(pByte[5]) << 8) & 0xff00)));                 \
3918 -       SK_OUT16((IoC), XMA((Mac), (Reg+6)), (SK_U16)           \
3919 +       SK_OUT16((IoC), XMA((Mac), (Reg) + 6), (SK_U16)         \
3920                 (((SK_U16)(pByte[6]) & 0x00ff)|                                 \
3921                 (((SK_U16)(pByte[7]) << 8) & 0xff00)));                 \
3922  }
3923 @@ -1866,12 +2796,12 @@
3924   *
3925   * GM_IN16(),          to read  a 16 bit register (e.g. GM_GP_STAT)
3926   * GM_OUT16(),         to write a 16 bit register (e.g. GM_GP_CTRL)
3927 - * GM_IN32(),          to read  a 32 bit register (e.g. GM_)
3928 - * GM_OUT32(),         to write a 32 bit register (e.g. GM_)
3929 + * GM_IN32(),          to read  a 32 bit register (e.g. GM_RXF_UC_OK)
3930 + * GM_OUT32(),         to write a 32 bit register
3931   * GM_INADDR(),                to read  a network address register (e.g. GM_SRC_ADDR_1L)
3932   * GM_OUTADDR(),       to write a network address register (e.g. GM_SRC_ADDR_2L)
3933 - * GM_INHASH(),                to read  the GM_MC_ADDR_H1 register
3934 - * GM_OUTHASH()                to write the GM_MC_ADDR_H1 register
3935 + * GM_INHASH(),                to read  the hash registers (e.g. GM_MC_ADDR_H1..4)
3936 + * GM_OUTHASH()                to write the hash registers (e.g. GM_MC_ADDR_H1..4)
3937   *
3938   * para:
3939   *     Mac             GMAC to access          values: MAC_1 or MAC_2
3940 @@ -1885,22 +2815,31 @@
3941  #define GMA(Mac, Reg)                                                                  \
3942         ((BASE_GMAC_1 + (Mac) * (BASE_GMAC_2 - BASE_GMAC_1)) | (Reg))
3943
3944 -#define GM_IN16(IoC, Mac, Reg, pVal)                                   \
3945 -       SK_IN16((IoC), GMA((Mac), (Reg)), (pVal))
3946 +#define GM_IN16(IoC, Mac, Reg, pVal)   \
3947 +       SK_IN16(IoC, GMA(Mac, Reg), pVal)
3948
3949 -#define GM_OUT16(IoC, Mac, Reg, Val)                                   \
3950 -       SK_OUT16((IoC), GMA((Mac), (Reg)), (Val))
3951 +#define GM_OUT16(IoC, Mac, Reg, Val)   \
3952 +       SK_OUT16(IoC, GMA(Mac, Reg), Val)
3953
3954 -#define GM_IN32(IoC, Mac, Reg, pVal) {                                 \
3955 -       SK_IN16((IoC), GMA((Mac), (Reg)),                                       \
3956 -               (SK_U16 SK_FAR*)&((SK_U16 SK_FAR*)(pVal))[XM_WORD_LO]);         \
3957 -       SK_IN16((IoC), GMA((Mac), (Reg+4)),                                     \
3958 -               (SK_U16 SK_FAR*)&((SK_U16 SK_FAR*)(pVal))[XM_WORD_HI]);         \
3959 +#ifdef SK_LITTLE_ENDIAN
3960 +
3961 +#define GM_IN32(IoC, Mac, Reg, pVal) {                                                                 \
3962 +       SK_IN16(IoC, GMA(Mac, Reg), (SK_U16 SK_FAR *)(pVal));                           \
3963 +       SK_IN16((IoC), GMA(Mac, (Reg) + 4), (SK_U16 SK_FAR *)(pVal) + 1);       \
3964  }
3965
3966 +#else  /* !SK_LITTLE_ENDIAN */
3967 +
3968 +#define GM_IN32(IoC, Mac, Reg, pVal) {                                                 \
3969 +       SK_IN16(IoC, GMA(Mac, Reg), (SK_U16 SK_FAR *)(pVal) + 1);       \
3970 +       SK_IN16(IoC, GMA(Mac, (Reg) + 4), (SK_U16 SK_FAR *)(pVal));     \
3971 +}
3972 +
3973 +#endif /* !SK_LITTLE_ENDIAN */
3974 +
3975  #define GM_OUT32(IoC, Mac, Reg, Val) {                                                                         \
3976 -       SK_OUT16((IoC), GMA((Mac), (Reg)), (SK_U16)((Val) & 0xffffL));                  \
3977 -       SK_OUT16((IoC), GMA((Mac), (Reg+4)), (SK_U16)(((Val) >> 16) & 0xffffL));\
3978 +       SK_OUT16(IoC, GMA(Mac, Reg), (SK_U16)((Val) & 0xffffL));                                \
3979 +       SK_OUT16(IoC, GMA(Mac, (Reg) + 4), (SK_U16)(((Val) >> 16) & 0xffffL));  \
3980  }
3981
3982  #define GM_INADDR(IoC, Mac, Reg, pVal) {                               \
3983 @@ -1908,13 +2847,13 @@
3984         SK_U8   *pByte;                                                                         \
3985         pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0];                         \
3986         SK_IN16((IoC), GMA((Mac), (Reg)), &Word);                       \
3987 -       pByte[0] = (SK_U8)(Word  & 0x00ff);                                     \
3988 +       pByte[0] = (SK_U8)(Word & 0x00ff);                                      \
3989         pByte[1] = (SK_U8)((Word >> 8) & 0x00ff);                       \
3990 -       SK_IN16((IoC), GMA((Mac), (Reg+4)), &Word);                     \
3991 -       pByte[2] = (SK_U8)(Word  & 0x00ff);                                     \
3992 +       SK_IN16((IoC), GMA((Mac), (Reg) + 4), &Word);           \
3993 +       pByte[2] = (SK_U8)(Word & 0x00ff);                                      \
3994         pByte[3] = (SK_U8)((Word >> 8) & 0x00ff);                       \
3995 -       SK_IN16((IoC), GMA((Mac), (Reg+8)), &Word);                     \
3996 -       pByte[4] = (SK_U8)(Word  & 0x00ff);                                     \
3997 +       SK_IN16((IoC), GMA((Mac), (Reg) + 8), &Word);           \
3998 +       pByte[4] = (SK_U8)(Word & 0x00ff);                                      \
3999         pByte[5] = (SK_U8)((Word >> 8) & 0x00ff);                       \
4000  }
4001
4002 @@ -1924,10 +2863,10 @@
4003         SK_OUT16((IoC), GMA((Mac), (Reg)), (SK_U16)                     \
4004                 (((SK_U16)(pByte[0]) & 0x00ff) |                                \
4005                 (((SK_U16)(pByte[1]) << 8) & 0xff00)));                 \
4006 -       SK_OUT16((IoC), GMA((Mac), (Reg+4)), (SK_U16)           \
4007 +       SK_OUT16((IoC), GMA((Mac), (Reg) + 4), (SK_U16)         \
4008                 (((SK_U16)(pByte[2]) & 0x00ff) |                                \
4009                 (((SK_U16)(pByte[3]) << 8) & 0xff00)));                 \
4010 -       SK_OUT16((IoC), GMA((Mac), (Reg+8)), (SK_U16)           \
4011 +       SK_OUT16((IoC), GMA((Mac), (Reg) + 8), (SK_U16)         \
4012                 (((SK_U16)(pByte[4]) & 0x00ff) |                                \
4013                 (((SK_U16)(pByte[5]) << 8) & 0xff00)));                 \
4014  }
4015 @@ -1937,16 +2876,16 @@
4016         SK_U8   *pByte;                                                                         \
4017         pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0];                         \
4018         SK_IN16((IoC), GMA((Mac), (Reg)), &Word);                       \
4019 -       pByte[0] = (SK_U8)(Word  & 0x00ff);                                     \
4020 +       pByte[0] = (SK_U8)(Word & 0x00ff);                                      \
4021         pByte[1] = (SK_U8)((Word >> 8) & 0x00ff);                       \
4022 -       SK_IN16((IoC), GMA((Mac), (Reg+4)), &Word);                     \
4023 -       pByte[2] = (SK_U8)(Word  & 0x00ff);                                     \
4024 +       SK_IN16((IoC), GMA((Mac), (Reg) + 4), &Word);           \
4025 +       pByte[2] = (SK_U8)(Word & 0x00ff);                                      \
4026         pByte[3] = (SK_U8)((Word >> 8) & 0x00ff);                       \
4027 -       SK_IN16((IoC), GMA((Mac), (Reg+8)), &Word);                     \
4028 -       pByte[4] = (SK_U8)(Word  & 0x00ff);                                     \
4029 +       SK_IN16((IoC), GMA((Mac), (Reg) + 8), &Word);           \
4030 +       pByte[4] = (SK_U8)(Word & 0x00ff);                                      \
4031         pByte[5] = (SK_U8)((Word >> 8) & 0x00ff);                       \
4032 -       SK_IN16((IoC), GMA((Mac), (Reg+12)), &Word);            \
4033 -       pByte[6] = (SK_U8)(Word  & 0x00ff);                                     \
4034 +       SK_IN16((IoC), GMA((Mac), (Reg) + 12), &Word);          \
4035 +       pByte[6] = (SK_U8)(Word & 0x00ff);                                      \
4036         pByte[7] = (SK_U8)((Word >> 8) & 0x00ff);                       \
4037  }
4038
4039 @@ -1956,13 +2895,13 @@
4040         SK_OUT16((IoC), GMA((Mac), (Reg)), (SK_U16)                     \
4041                 (((SK_U16)(pByte[0]) & 0x00ff)|                                 \
4042                 (((SK_U16)(pByte[1]) << 8) & 0xff00)));                 \
4043 -       SK_OUT16((IoC), GMA((Mac), (Reg+4)), (SK_U16)           \
4044 +       SK_OUT16((IoC), GMA((Mac), (Reg) + 4), (SK_U16)         \
4045                 (((SK_U16)(pByte[2]) & 0x00ff)|                                 \
4046                 (((SK_U16)(pByte[3]) << 8) & 0xff00)));                 \
4047 -       SK_OUT16((IoC), GMA((Mac), (Reg+8)), (SK_U16)           \
4048 +       SK_OUT16((IoC), GMA((Mac), (Reg) + 8), (SK_U16)         \
4049                 (((SK_U16)(pByte[4]) & 0x00ff)|                                 \
4050                 (((SK_U16)(pByte[5]) << 8) & 0xff00)));                 \
4051 -       SK_OUT16((IoC), GMA((Mac), (Reg+12)), (SK_U16)          \
4052 +       SK_OUT16((IoC), GMA((Mac), (Reg) + 12), (SK_U16)        \
4053                 (((SK_U16)(pByte[6]) & 0x00ff)|                                 \
4054                 (((SK_U16)(pByte[7]) << 8) & 0xff00)));                 \
4055  }
4056 @@ -1980,8 +2919,8 @@
4057  #define SK_PHY_BCOM                    1       /* Broadcom BCM5400 */
4058  #define SK_PHY_LONE                    2       /* Level One LXT1000 */
4059  #define SK_PHY_NAT                     3       /* National DP83891 */
4060 -#define SK_PHY_MARV_COPPER     4       /* Marvell 88E1011S */
4061 -#define SK_PHY_MARV_FIBER      5       /* Marvell 88E1011S working on fiber */
4062 +#define SK_PHY_MARV_COPPER     4       /* Marvell 88E1040S */
4063 +#define SK_PHY_MARV_FIBER      5       /* Marvell 88E1040S working on fiber */
4064
4065  /*
4066   * PHY addresses (bits 12..8 of PHY address reg)
4067 @@ -2010,30 +2949,30 @@
4068   *
4069   * usage:      PHY_READ(IoC, pPort, MAC_1, PHY_CTRL, Value);
4070   * Warning: a PHY_READ on an uninitialized PHY (PHY still in reset) never
4071 - *          comes back. This is checked in DEBUG mode.
4072 + *     comes back. This is checked in DEBUG mode.
4073   */
4074  #ifndef DEBUG
4075  #define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) {                                              \
4076 -       SK_U16 Mmu;                                                                                                             \
4077 +       SK_U16 Mmu;                                                                                                                     \
4078                                                                                                                                                 \
4079         XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr);       \
4080         XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal));                                                     \
4081         if ((pPort)->PhyType != SK_PHY_XMAC) {                                                          \
4082 -               do {                                                                                                                    \
4083 +               do {                                                                                                                    \
4084                         XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu);                                        \
4085                 } while ((Mmu & XM_MMU_PHY_RDY) == 0);                                                  \
4086                 XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal));                                             \
4087 -       }                                                                                                                                       \
4088 +       }                                                                                                                                       \
4089  }
4090  #else
4091  #define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) {                                              \
4092 -       SK_U16 Mmu;                                                                                                             \
4093 +       SK_U16 Mmu;                                                                                                                     \
4094         int __i = 0;                                                                                                            \
4095                                                                                                                                                 \
4096         XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr);       \
4097         XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal));                                                     \
4098         if ((pPort)->PhyType != SK_PHY_XMAC) {                                                          \
4099 -               do {                                                                                                                    \
4100 +               do {                                                                                                                    \
4101                         XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu);                                        \
4102                         __i++;                                                                                                          \
4103                         if (__i > 100000) {                                                                                     \
4104 @@ -2044,7 +2983,7 @@
4105                         }                                                                                                                       \
4106                 } while ((Mmu & XM_MMU_PHY_RDY) == 0);                                                  \
4107                 XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal));                                             \
4108 -       }                                                                                                                                       \
4109 +       }                                                                                                                                       \
4110  }
4111  #endif /* DEBUG */
4112
4113 @@ -2052,17 +2991,17 @@
4114         SK_U16 Mmu;                                                                                                                     \
4115                                                                                                                                                 \
4116         if ((pPort)->PhyType != SK_PHY_XMAC) {                                                          \
4117 -               do {                                                                                                                    \
4118 +               do {                                                                                                                    \
4119                         XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu);                                        \
4120                 } while ((Mmu & XM_MMU_PHY_BUSY) != 0);                                                 \
4121 -       }                                                                                                                                       \
4122 +       }                                                                                                                                       \
4123         XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr);       \
4124         XM_OUT16((IoC), (Mac), XM_PHY_DATA, (Val));                                                     \
4125         if ((pPort)->PhyType != SK_PHY_XMAC) {                                                          \
4126 -               do {                                                                                                                    \
4127 +               do {                                                                                                                    \
4128                         XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu);                                        \
4129                 } while ((Mmu & XM_MMU_PHY_BUSY) != 0);                                                 \
4130 -       }                                                                                                                                       \
4131 +       }                                                                                                                                       \
4132  }
4133
4134  /*
4135 @@ -2071,12 +3010,14 @@
4136   *     Use this macro to access PCI config register from the I/O space.
4137   *
4138   * para:
4139 + *     pAC             Pointer to adapter context
4140   *     Addr    PCI configuration register to access.
4141   *                     Values: PCI_VENDOR_ID ... PCI_VPD_ADR_REG,
4142   *
4143 - * usage       SK_IN16(pAC, PCI_C(PCI_VENDOR_ID), pVal);
4144 + * usage       SK_IN16(IoC, PCI_C(pAC, PCI_VENDOR_ID), pVal);
4145   */
4146 -#define PCI_C(Addr)    (B7_CFG_SPC + (Addr))   /* PCI Config Space */
4147 +#define PCI_C(p, Addr)         \
4148 +       (((CHIP_ID_YUKON_2(p)) ? Y2_CFG_SPC : B7_CFG_SPC) + (Addr))
4149
4150  /*
4151   *     Macro SK_HW_ADDR(Base, Addr)
4152 @@ -2088,7 +3029,7 @@
4153   *     Addr    Address offset
4154   *
4155   * usage:      May be used in SK_INxx and SK_OUTxx macros
4156 - *             #define SK_IN8(pAC, Addr, pVal) ...\
4157 + *             #define SK_IN8(IoC, Addr, pVal) ...\
4158   *                     *pVal = (SK_U8)inp(SK_HW_ADDR(pAC->Hw.Iop, Addr)))
4159   */
4160  #ifdef SK_MEM_MAPPED_IO
4161 @@ -2107,20 +3048,31 @@
4162   * para:
4163   *     pAC             Pointer to adapter context struct
4164   *     IoC             I/O context needed for SK I/O macros
4165 - *  Port       Port number
4166 + *     Port    Port number
4167   *     Mode    Mode to set for this LED
4168   */
4169  #define SK_HWAC_LINK_LED(pAC, IoC, Port, Mode) \
4170         SK_OUT8(IoC, MR_ADDR(Port, LNK_LED_REG), Mode);
4171
4172 +#define SK_SET_GP_IO(IoC, Bit) {       \
4173 +       SK_U32  DWord;                                  \
4174 +       SK_IN32(IoC, B2_GP_IO, &DWord); \
4175 +       DWord |= ((GP_DIR_0 | GP_IO_0) << (Bit));\
4176 +       SK_OUT32(IoC, B2_GP_IO, DWord); \
4177 +}
4178
4179 -/* typedefs *******************************************************************/
4180 -
4181 +#define SK_CLR_GP_IO(IoC, Bit) {       \
4182 +       SK_U32  DWord;                                  \
4183 +       SK_IN32(IoC, B2_GP_IO, &DWord); \
4184 +       DWord &= ~((GP_DIR_0 | GP_IO_0) << (Bit));\
4185 +       SK_OUT32(IoC, B2_GP_IO, DWord); \
4186 +}
4187
4188 -/* function prototypes ********************************************************/
4189 +#define SK_GE_PCI_FIFO_SIZE            1600    /* PCI FIFO Size */
4190
4191  #ifdef __cplusplus
4192  }
4193  #endif /* __cplusplus */
4194
4195  #endif /* __INC_SKGEHW_H */
4196 +
4197 diff -ruN linux/drivers/net/sk98lin/h/skgehwt.h linux-new/drivers/net/sk98lin/h/skgehwt.h
4198 --- linux/drivers/net/sk98lin/h/skgehwt.h       2006-09-20 05:42:06.000000000 +0200
4199 +++ linux-new/drivers/net/sk98lin/h/skgehwt.h   2006-07-28 14:13:54.000000000 +0200
4200 @@ -2,14 +2,15 @@
4201   *
4202   * Name:       skhwt.h
4203   * Project:    Gigabit Ethernet Adapters, Event Scheduler Module
4204 - * Version:    $Revision$
4205 - * Date:       $Date$
4206 + * Version:    $Revision$
4207 + * Date:       $Date$
4208   * Purpose:    Defines for the hardware timer functions
4209   *
4210   ******************************************************************************/
4211
4212  /******************************************************************************
4213   *
4214 + *     LICENSE:
4215   *     (C)Copyright 1998-2002 SysKonnect GmbH.
4216   *     (C)Copyright 2002-2003 Marvell.
4217   *
4218 @@ -19,6 +20,7 @@
4219   *     (at your option) any later version.
4220   *
4221   *     The information in this file is provided "AS IS" without warranty.
4222 + *     /LICENSE
4223   *
4224   ******************************************************************************/
4225
4226 diff -ruN linux/drivers/net/sk98lin/h/skgei2c.h linux-new/drivers/net/sk98lin/h/skgei2c.h
4227 --- linux/drivers/net/sk98lin/h/skgei2c.h       2006-09-20 05:42:06.000000000 +0200
4228 +++ linux-new/drivers/net/sk98lin/h/skgei2c.h   1970-01-01 01:00:00.000000000 +0100
4229 @@ -1,210 +0,0 @@
4230 -/******************************************************************************
4231 - *
4232 - * Name:       skgei2c.h
4233 - * Project:    Gigabit Ethernet Adapters, TWSI-Module
4234 - * Version:    $Revision$
4235 - * Date:       $Date$
4236 - * Purpose:    Special defines for TWSI
4237 - *
4238 - ******************************************************************************/
4239 -
4240 -/******************************************************************************
4241 - *
4242 - *     (C)Copyright 1998-2002 SysKonnect.
4243 - *     (C)Copyright 2002-2003 Marvell.
4244 - *
4245 - *     This program is free software; you can redistribute it and/or modify
4246 - *     it under the terms of the GNU General Public License as published by
4247 - *     the Free Software Foundation; either version 2 of the License, or
4248 - *     (at your option) any later version.
4249 - *
4250 - *     The information in this file is provided "AS IS" without warranty.
4251 - *
4252 - ******************************************************************************/
4253 -
4254 -/*
4255 - * SKGEI2C.H   contains all SK-98xx specific defines for the TWSI handling
4256 - */
4257 -
4258 -#ifndef _INC_SKGEI2C_H_
4259 -#define _INC_SKGEI2C_H_
4260 -
4261 -/*
4262 - * Macros to access the B2_I2C_CTRL
4263 - */
4264 -#define SK_I2C_CTL(IoC, flag, dev, dev_size, reg, burst) \
4265 -       SK_OUT32(IoC, B2_I2C_CTRL,\
4266 -               (flag ? 0x80000000UL : 0x0L) | \
4267 -               (((SK_U32)reg << 16) & I2C_ADDR) | \
4268 -               (((SK_U32)dev << 9) & I2C_DEV_SEL) | \
4269 -               (dev_size & I2C_DEV_SIZE) | \
4270 -               ((burst << 4) & I2C_BURST_LEN))
4271 -
4272 -#define SK_I2C_STOP(IoC) {                             \
4273 -       SK_U32  I2cCtrl;                                \
4274 -       SK_IN32(IoC, B2_I2C_CTRL, &I2cCtrl);            \
4275 -       SK_OUT32(IoC, B2_I2C_CTRL, I2cCtrl | I2C_STOP); \
4276 -}
4277 -
4278 -#define SK_I2C_GET_CTL(IoC, pI2cCtrl)  SK_IN32(IoC, B2_I2C_CTRL, pI2cCtrl)
4279 -
4280 -/*
4281 - * Macros to access the TWSI SW Registers
4282 - */
4283 -#define SK_I2C_SET_BIT(IoC, SetBits) {                 \
4284 -       SK_U8   OrgBits;                                \
4285 -       SK_IN8(IoC, B2_I2C_SW, &OrgBits);               \
4286 -       SK_OUT8(IoC, B2_I2C_SW, OrgBits | (SK_U8)(SetBits));    \
4287 -}
4288 -
4289 -#define SK_I2C_CLR_BIT(IoC, ClrBits) {                 \
4290 -       SK_U8   OrgBits;                                \
4291 -       SK_IN8(IoC, B2_I2C_SW, &OrgBits);               \
4292 -       SK_OUT8(IoC, B2_I2C_SW, OrgBits & ~((SK_U8)(ClrBits))); \
4293 -}
4294 -
4295 -#define SK_I2C_GET_SW(IoC, pI2cSw)     SK_IN8(IoC, B2_I2C_SW, pI2cSw)
4296 -
4297 -/*
4298 - * define the possible sensor states
4299 - */
4300 -#define        SK_SEN_IDLE             0       /* Idle: sensor not read */
4301 -#define        SK_SEN_VALUE    1       /* Value Read cycle */
4302 -#define        SK_SEN_VALEXT   2       /* Extended Value Read cycle */
4303 -
4304 -/*
4305 - * Conversion factor to convert read Voltage sensor to milli Volt
4306 - * Conversion factor to convert read Temperature sensor to 10th degree Celsius
4307 - */
4308 -#define        SK_LM80_VT_LSB          22      /* 22mV LSB resolution */
4309 -#define        SK_LM80_TEMP_LSB        10      /* 1 degree LSB resolution */
4310 -#define        SK_LM80_TEMPEXT_LSB      5      /* 0.5 degree LSB resolution for ext. val. */
4311 -
4312 -/*
4313 - * formula: counter = (22500*60)/(rpm * divisor * pulses/2)
4314 - * assuming: 6500rpm, 4 pulses, divisor 1
4315 - */
4316 -#define SK_LM80_FAN_FAKTOR     ((22500L*60)/(1*2))
4317 -
4318 -/*
4319 - * Define sensor management data
4320 - * Maximum is reached on Genesis copper dual port and Yukon-64
4321 - * Board specific maximum is in pAC->I2c.MaxSens
4322 - */
4323 -#define        SK_MAX_SENSORS  8       /* maximal no. of installed sensors */
4324 -#define        SK_MIN_SENSORS  5       /* minimal no. of installed sensors */
4325 -
4326 -/*
4327 - * To watch the state machine (SM) use the timer in two ways
4328 - * instead of one as hitherto
4329 - */
4330 -#define        SK_TIMER_WATCH_SM               0       /* Watch the SM to finish in a spec. time */
4331 -#define        SK_TIMER_NEW_GAUGING    1       /* Start a new gauging when timer expires */
4332 -
4333 -/*
4334 - * Defines for the individual thresholds
4335 - */
4336 -
4337 -/* Temperature sensor */
4338 -#define        SK_SEN_TEMP_HIGH_ERR    800     /* Temperature High Err  Threshold */
4339 -#define        SK_SEN_TEMP_HIGH_WARN   700     /* Temperature High Warn Threshold */
4340 -#define        SK_SEN_TEMP_LOW_WARN    100     /* Temperature Low  Warn Threshold */
4341 -#define        SK_SEN_TEMP_LOW_ERR               0     /* Temperature Low  Err  Threshold */
4342 -
4343 -/* VCC which should be 5 V */
4344 -#define        SK_SEN_PCI_5V_HIGH_ERR          5588    /* Voltage PCI High Err  Threshold */
4345 -#define        SK_SEN_PCI_5V_HIGH_WARN         5346    /* Voltage PCI High Warn Threshold */
4346 -#define        SK_SEN_PCI_5V_LOW_WARN          4664    /* Voltage PCI Low  Warn Threshold */
4347 -#define        SK_SEN_PCI_5V_LOW_ERR           4422    /* Voltage PCI Low  Err  Threshold */
4348 -
4349 -/*
4350 - * VIO may be 5 V or 3.3 V. Initialization takes two parts:
4351 - * 1. Initialize lowest lower limit and highest higher limit.
4352 - * 2. After the first value is read correct the upper or the lower limit to
4353 - *    the appropriate C constant.
4354 - *
4355 - * Warning limits are +-5% of the exepected voltage.
4356 - * Error limits are +-10% of the expected voltage.
4357 - */
4358 -
4359 -/* Bug fix AF: 16.Aug.2001: Correct the init base of LM80 sensor */
4360 -
4361 -#define        SK_SEN_PCI_IO_5V_HIGH_ERR       5566    /* + 10% V PCI-IO High Err Threshold */
4362 -#define        SK_SEN_PCI_IO_5V_HIGH_WARN      5324    /* +  5% V PCI-IO High Warn Threshold */
4363 -                                       /*              5000    mVolt */
4364 -#define        SK_SEN_PCI_IO_5V_LOW_WARN       4686    /* -  5% V PCI-IO Low Warn Threshold */
4365 -#define        SK_SEN_PCI_IO_5V_LOW_ERR        4444    /* - 10% V PCI-IO Low Err Threshold */
4366 -
4367 -#define        SK_SEN_PCI_IO_RANGE_LIMITER     4000    /* 4000 mV range delimiter */
4368 -
4369 -/* correction values for the second pass */
4370 -#define        SK_SEN_PCI_IO_3V3_HIGH_ERR      3850    /* + 15% V PCI-IO High Err Threshold */
4371 -#define        SK_SEN_PCI_IO_3V3_HIGH_WARN     3674    /* + 10% V PCI-IO High Warn Threshold */
4372 -                                       /*              3300    mVolt */
4373 -#define        SK_SEN_PCI_IO_3V3_LOW_WARN      2926    /* - 10% V PCI-IO Low Warn Threshold */
4374 -#define        SK_SEN_PCI_IO_3V3_LOW_ERR       2772    /* - 15% V PCI-IO Low Err  Threshold */
4375 -
4376 -/*
4377 - * VDD voltage
4378 - */
4379 -#define        SK_SEN_VDD_HIGH_ERR             3630    /* Voltage ASIC High Err  Threshold */
4380 -#define        SK_SEN_VDD_HIGH_WARN    3476    /* Voltage ASIC High Warn Threshold */
4381 -#define        SK_SEN_VDD_LOW_WARN             3146    /* Voltage ASIC Low  Warn Threshold */
4382 -#define        SK_SEN_VDD_LOW_ERR              2970    /* Voltage ASIC Low  Err  Threshold */
4383 -
4384 -/*
4385 - * PHY PLL 3V3 voltage
4386 - */
4387 -#define        SK_SEN_PLL_3V3_HIGH_ERR         3630    /* Voltage PMA High Err  Threshold */
4388 -#define        SK_SEN_PLL_3V3_HIGH_WARN        3476    /* Voltage PMA High Warn Threshold */
4389 -#define        SK_SEN_PLL_3V3_LOW_WARN         3146    /* Voltage PMA Low  Warn Threshold */
4390 -#define        SK_SEN_PLL_3V3_LOW_ERR          2970    /* Voltage PMA Low  Err  Threshold */
4391 -
4392 -/*
4393 - * VAUX (YUKON only)
4394 - */
4395 -#define        SK_SEN_VAUX_3V3_HIGH_ERR        3630    /* Voltage VAUX High Err Threshold */
4396 -#define        SK_SEN_VAUX_3V3_HIGH_WARN       3476    /* Voltage VAUX High Warn Threshold */
4397 -#define        SK_SEN_VAUX_3V3_LOW_WARN        3146    /* Voltage VAUX Low Warn Threshold */
4398 -#define        SK_SEN_VAUX_3V3_LOW_ERR         2970    /* Voltage VAUX Low Err Threshold */
4399 -#define        SK_SEN_VAUX_0V_WARN_ERR            0    /* if VAUX not present */
4400 -#define        SK_SEN_VAUX_RANGE_LIMITER       1000    /* 1000 mV range delimiter */
4401 -
4402 -/*
4403 - * PHY 2V5 voltage
4404 - */
4405 -#define        SK_SEN_PHY_2V5_HIGH_ERR         2750    /* Voltage PHY High Err Threshold */
4406 -#define        SK_SEN_PHY_2V5_HIGH_WARN        2640    /* Voltage PHY High Warn Threshold */
4407 -#define        SK_SEN_PHY_2V5_LOW_WARN         2376    /* Voltage PHY Low Warn Threshold */
4408 -#define        SK_SEN_PHY_2V5_LOW_ERR          2222    /* Voltage PHY Low Err Threshold */
4409 -
4410 -/*
4411 - * ASIC Core 1V5 voltage (YUKON only)
4412 - */
4413 -#define        SK_SEN_CORE_1V5_HIGH_ERR        1650    /* Voltage ASIC Core High Err Threshold */
4414 -#define        SK_SEN_CORE_1V5_HIGH_WARN       1575    /* Voltage ASIC Core High Warn Threshold */
4415 -#define        SK_SEN_CORE_1V5_LOW_WARN        1425    /* Voltage ASIC Core Low Warn Threshold */
4416 -#define        SK_SEN_CORE_1V5_LOW_ERR         1350    /* Voltage ASIC Core Low Err Threshold */
4417 -
4418 -/*
4419 - * FAN 1 speed
4420 - */
4421 -/* assuming: 6500rpm +-15%, 4 pulses,
4422 - * warning at: 80 %
4423 - * error at:   70 %
4424 - * no upper limit
4425 - */
4426 -#define        SK_SEN_FAN_HIGH_ERR             20000   /* FAN Speed High Err Threshold */
4427 -#define        SK_SEN_FAN_HIGH_WARN    20000   /* FAN Speed High Warn Threshold */
4428 -#define        SK_SEN_FAN_LOW_WARN              5200   /* FAN Speed Low Warn Threshold */
4429 -#define        SK_SEN_FAN_LOW_ERR               4550   /* FAN Speed Low Err Threshold */
4430 -
4431 -/*
4432 - * Some Voltages need dynamic thresholds
4433 - */
4434 -#define        SK_SEN_DYN_INIT_NONE             0  /* No dynamic init of thresholds */
4435 -#define        SK_SEN_DYN_INIT_PCI_IO          10  /* Init PCI-IO with new thresholds */
4436 -#define        SK_SEN_DYN_INIT_VAUX            11  /* Init VAUX with new thresholds */
4437 -
4438 -extern int SkLm80ReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen);
4439 -#endif /* n_INC_SKGEI2C_H */
4440 diff -ruN linux/drivers/net/sk98lin/h/skgeinit.h linux-new/drivers/net/sk98lin/h/skgeinit.h
4441 --- linux/drivers/net/sk98lin/h/skgeinit.h      2006-09-20 05:42:06.000000000 +0200
4442 +++ linux-new/drivers/net/sk98lin/h/skgeinit.h  2006-07-28 14:13:54.000000000 +0200
4443 @@ -2,23 +2,24 @@
4444   *
4445   * Name:       skgeinit.h
4446   * Project:    Gigabit Ethernet Adapters, Common Modules
4447 - * Version:    $Revision$
4448 - * Date:       $Date$
4449 + * Version:    $Revision$
4450 + * Date:       $Date$
4451   * Purpose:    Structures and prototypes for the GE Init Module
4452   *
4453   ******************************************************************************/
4454
4455  /******************************************************************************
4456   *
4457 + *     LICENSE:
4458   *     (C)Copyright 1998-2002 SysKonnect.
4459 - *     (C)Copyright 2002-2003 Marvell.
4460 + *     (C)Copyright 2002-2006 Marvell.
4461   *
4462   *     This program is free software; you can redistribute it and/or modify
4463   *     it under the terms of the GNU General Public License as published by
4464   *     the Free Software Foundation; either version 2 of the License, or
4465   *     (at your option) any later version.
4466 - *
4467   *     The information in this file is provided "AS IS" without warranty.
4468 + *     /LICENSE
4469   *
4470   ******************************************************************************/
4471
4472 @@ -60,14 +61,17 @@
4473  #define SK_XMIT_DUR            0x002faf08UL    /*  50 ms */
4474  #define SK_BLK_DUR             0x01dcd650UL    /* 500 ms */
4475
4476 -#define SK_DPOLL_DEF   0x00ee6b28UL    /* 250 ms at 62.5 MHz */
4477 +#define SK_DPOLL_DEF   0x00ee6b28UL    /* 250 ms at 62.5 MHz (Genesis) */
4478 +#define SK_DPOLL_DEF_Y2        0x0000124fUL    /*  75 us (Yukon-2) */
4479
4480  #define SK_DPOLL_MAX   0x00ffffffUL    /* 268 ms at 62.5 MHz */
4481 -                                                                               /* 215 ms at 78.12 MHz */
4482 +                                                                               /* 215 ms at 78.12 MHz (Yukon) */
4483
4484  #define SK_FACT_62             100                     /* is given in percent */
4485 -#define SK_FACT_53              85         /* on GENESIS:      53.12 MHz */
4486 +#define SK_FACT_53              85                     /* on GENESIS:  53.12 MHz */
4487  #define SK_FACT_78             125                     /* on YUKON:    78.12 MHz */
4488 +#define SK_FACT_100            161                     /* on YUKON-FE: 100 MHz */
4489 +#define SK_FACT_125            202                     /* on YUKON-EC: 125 MHz */
4490
4491  /* Timeout values */
4492  #define SK_MAC_TO_53   72                      /* MAC arbiter timeout */
4493 @@ -82,11 +86,23 @@
4494  #define SK_RB_LLPP_S   (10 * 1024)     /* Lower Level for small Queues */
4495  #define SK_RB_LLPP_B   (16 * 1024)     /* Lower Level for big Queues */
4496
4497 +/* Threshold values for Yukon-EC Ultra */
4498 +#define SK_ECU_ULPP            0x0080  /* Upper Pause Threshold (multiples of 8) */
4499 +#define SK_ECU_LLPP            0x0060  /* Lower Pause Threshold (multiples of 8) */
4500 +#define SK_ECU_AE_THR  0x0180  /* Almost Empty Threshold */
4501 +#define SK_ECU_TXFF_LEV        0x01a0  /* Tx BMU FIFO Level */
4502 +
4503  #ifndef SK_BMU_RX_WM
4504 -#define SK_BMU_RX_WM   0x600           /* BMU Rx Watermark */
4505 +#define SK_BMU_RX_WM           0x600   /* BMU Rx Watermark */
4506  #endif
4507 +
4508  #ifndef SK_BMU_TX_WM
4509 -#define SK_BMU_TX_WM   0x600           /* BMU Tx Watermark */
4510 +#define SK_BMU_TX_WM           0x600   /* BMU Tx Watermark */
4511 +#endif
4512 +
4513 +/* performance sensitive drivers should set this define to 0x80 */
4514 +#ifndef SK_BMU_RX_WM_PEX
4515 +#define SK_BMU_RX_WM_PEX       0x600   /* BMU Rx Watermark for PEX */
4516  #endif
4517
4518  /* XMAC II Rx High Watermark */
4519 @@ -98,37 +114,31 @@
4520  #define SK_XM_THR_MULL 0x01fb          /* .. for multiple link usage */
4521  #define SK_XM_THR_JUMBO        0x03fc          /* .. for jumbo frame usage */
4522
4523 -/* values for GIPortUsage */
4524 +/* values for PortUsage */
4525  #define SK_RED_LINK            1               /* redundant link usage */
4526  #define SK_MUL_LINK            2               /* multiple link usage */
4527  #define SK_JUMBO_LINK  3               /* driver uses jumbo frames */
4528
4529  /* Minimum RAM Buffer Rx Queue Size */
4530 -#define SK_MIN_RXQ_SIZE        16              /* 16 kB */
4531 +#define SK_MIN_RXQ_SIZE        (((pAC)->GIni.GIYukon2) ? 10 : 16)              /* 10/16 kB */
4532
4533  /* Minimum RAM Buffer Tx Queue Size */
4534 -#define SK_MIN_TXQ_SIZE        16              /* 16 kB */
4535 +#define SK_MIN_TXQ_SIZE        (((pAC)->GIni.GIYukon2) ? 10 : 16)              /* 10/16 kB */
4536
4537 -/* Queue Size units */
4538 -#define QZ_UNITS               0x7
4539 +/* Queue Size units (Genesis/Yukon) */
4540 +#define QZ_UNITS               7
4541  #define QZ_STEP                        8
4542
4543 +/* Queue Size units (Yukon-2) */
4544 +#define QZ_STEP_Y2             1
4545 +
4546  /* Percentage of queue size from whole memory */
4547  /* 80 % for receive */
4548 -#define RAM_QUOTA_RX   80L
4549 -/* 0% for sync transfer */
4550 -#define        RAM_QUOTA_SYNC  0L
4551 +#define RAM_QUOTA_RX   80
4552 +/*  0 % for sync transfer */
4553 +#define RAM_QUOTA_SYNC 0
4554  /* the rest (20%) is taken for async transfer */
4555
4556 -/* Get the rounded queue size in Bytes in 8k steps */
4557 -#define ROUND_QUEUE_SIZE(SizeInBytes)                                  \
4558 -       ((((unsigned long) (SizeInBytes) + (QZ_STEP*1024L)-1) / 1024) & \
4559 -       ~(QZ_STEP-1))
4560 -
4561 -/* Get the rounded queue size in KBytes in 8k steps */
4562 -#define ROUND_QUEUE_SIZE_KB(Kilobytes) \
4563 -       ROUND_QUEUE_SIZE((Kilobytes) * 1024L)
4564 -
4565  /* Types of RAM Buffer Queues */
4566  #define SK_RX_SRAM_Q   1       /* small receive queue */
4567  #define SK_RX_BRAM_Q   2       /* big receive queue */
4568 @@ -167,11 +177,11 @@
4569
4570
4571  /* Link Speed Capabilities */
4572 -#define SK_LSPEED_CAP_AUTO                     (1<<0)  /* Automatic resolution */
4573 -#define SK_LSPEED_CAP_10MBPS           (1<<1)  /* 10 Mbps */
4574 -#define SK_LSPEED_CAP_100MBPS          (1<<2)  /* 100 Mbps */
4575 -#define SK_LSPEED_CAP_1000MBPS         (1<<3)  /* 1000 Mbps */
4576 -#define SK_LSPEED_CAP_INDETERMINATED (1<<4) /* indeterminated */
4577 +#define SK_LSPEED_CAP_AUTO                     BIT_0S  /* Automatic resolution */
4578 +#define SK_LSPEED_CAP_10MBPS           BIT_1S  /* 10 Mbps */
4579 +#define SK_LSPEED_CAP_100MBPS          BIT_2S  /* 100 Mbps */
4580 +#define SK_LSPEED_CAP_1000MBPS         BIT_3S  /* 1000 Mbps */
4581 +#define SK_LSPEED_CAP_INDETERMINATED BIT_4S /* indeterminated */
4582
4583  /* Link Speed Parameter */
4584  #define SK_LSPEED_AUTO                         1       /* Automatic resolution */
4585 @@ -189,11 +199,11 @@
4586
4587
4588  /* Link Capability Parameter */
4589 -#define SK_LMODE_CAP_HALF              (1<<0)  /* Half Duplex Mode */
4590 -#define SK_LMODE_CAP_FULL              (1<<1)  /* Full Duplex Mode */
4591 -#define SK_LMODE_CAP_AUTOHALF  (1<<2)  /* AutoHalf Duplex Mode */
4592 -#define SK_LMODE_CAP_AUTOFULL  (1<<3)  /* AutoFull Duplex Mode */
4593 -#define SK_LMODE_CAP_INDETERMINATED (1<<4) /* indeterminated */
4594 +#define SK_LMODE_CAP_HALF              BIT_0S  /* Half Duplex Mode */
4595 +#define SK_LMODE_CAP_FULL              BIT_1S  /* Full Duplex Mode */
4596 +#define SK_LMODE_CAP_AUTOHALF  BIT_2S  /* AutoHalf Duplex Mode */
4597 +#define SK_LMODE_CAP_AUTOFULL  BIT_3S  /* AutoFull Duplex Mode */
4598 +#define SK_LMODE_CAP_INDETERMINATED BIT_4S /* indeterminated */
4599
4600  /* Link Mode Current State */
4601  #define SK_LMODE_STAT_UNKNOWN  1       /* Unknown Duplex Mode */
4602 @@ -204,7 +214,7 @@
4603  #define SK_LMODE_STAT_INDETERMINATED 6 /* indeterminated */
4604
4605  /* Flow Control Mode Parameter (and capabilities) */
4606 -#define SK_FLOW_MODE_NONE              1       /* No Flow-Control */
4607 +#define SK_FLOW_MODE_NONE              1       /* No Flow Control */
4608  #define SK_FLOW_MODE_LOC_SEND  2       /* Local station sends PAUSE */
4609  #define SK_FLOW_MODE_SYMMETRIC 3       /* Both stations may send PAUSE */
4610  #define SK_FLOW_MODE_SYM_OR_REM        4       /* Both stations may send PAUSE or
4611 @@ -220,10 +230,10 @@
4612  #define SK_FLOW_STAT_INDETERMINATED 5  /* indeterminated */
4613
4614  /* Master/Slave Mode Capabilities */
4615 -#define SK_MS_CAP_AUTO         (1<<0)  /* Automatic resolution */
4616 -#define SK_MS_CAP_MASTER       (1<<1)  /* This station is master */
4617 -#define SK_MS_CAP_SLAVE                (1<<2)  /* This station is slave */
4618 -#define SK_MS_CAP_INDETERMINATED (1<<3)        /* indeterminated */
4619 +#define SK_MS_CAP_AUTO         BIT_0S  /* Automatic resolution */
4620 +#define SK_MS_CAP_MASTER       BIT_1S  /* This station is master */
4621 +#define SK_MS_CAP_SLAVE                BIT_2S  /* This station is slave */
4622 +#define SK_MS_CAP_INDETERMINATED BIT_3S        /* indeterminated */
4623
4624  /* Set Master/Slave Mode Parameter (and capabilities) */
4625  #define SK_MS_MODE_AUTO                1       /* Automatic resolution */
4626 @@ -238,25 +248,25 @@
4627  #define SK_MS_STAT_FAULT       4       /* M/S resolution failed */
4628  #define SK_MS_STAT_INDETERMINATED 5    /* indeterminated */
4629
4630 -/* parameter 'Mode' when calling SkXmSetRxCmd() */
4631 -#define SK_STRIP_FCS_ON                (1<<0)  /* Enable  FCS stripping of Rx frames */
4632 -#define SK_STRIP_FCS_OFF       (1<<1)  /* Disable FCS stripping of Rx frames */
4633 -#define SK_STRIP_PAD_ON                (1<<2)  /* Enable  pad byte stripping of Rx fr */
4634 -#define SK_STRIP_PAD_OFF       (1<<3)  /* Disable pad byte stripping of Rx fr */
4635 -#define SK_LENERR_OK_ON                (1<<4)  /* Don't chk fr for in range len error */
4636 -#define SK_LENERR_OK_OFF       (1<<5)  /* Check frames for in range len error */
4637 -#define SK_BIG_PK_OK_ON                (1<<6)  /* Don't set Rx Error bit for big frames */
4638 -#define SK_BIG_PK_OK_OFF       (1<<7)  /* Set Rx Error bit for big frames */
4639 -#define SK_SELF_RX_ON          (1<<8)  /* Enable  Rx of own packets */
4640 -#define SK_SELF_RX_OFF         (1<<9)  /* Disable Rx of own packets */
4641 +/* parameter 'Mode' when calling SkMacSetRxCmd() */
4642 +#define SK_STRIP_FCS_ON                BIT_0S  /* Enable  FCS stripping of Rx frames */
4643 +#define SK_STRIP_FCS_OFF       BIT_1S  /* Disable FCS stripping of Rx frames */
4644 +#define SK_STRIP_PAD_ON                BIT_2S  /* Enable  pad byte stripping of Rx fr */
4645 +#define SK_STRIP_PAD_OFF       BIT_3S  /* Disable pad byte stripping of Rx fr */
4646 +#define SK_LENERR_OK_ON                BIT_4S  /* Don't chk fr for in range len error */
4647 +#define SK_LENERR_OK_OFF       BIT_5S  /* Check frames for in range len error */
4648 +#define SK_BIG_PK_OK_ON                BIT_6S  /* Don't set Rx Error bit for big frames */
4649 +#define SK_BIG_PK_OK_OFF       BIT_7S  /* Set Rx Error bit for big frames */
4650 +#define SK_SELF_RX_ON          BIT_8S  /* Enable  Rx of own packets */
4651 +#define SK_SELF_RX_OFF         BIT_9S  /* Disable Rx of own packets */
4652
4653  /* parameter 'Para' when calling SkMacSetRxTxEn() */
4654 -#define SK_MAC_LOOPB_ON                (1<<0)  /* Enable  MAC Loopback Mode */
4655 -#define SK_MAC_LOOPB_OFF       (1<<1)  /* Disable MAC Loopback Mode */
4656 -#define SK_PHY_LOOPB_ON                (1<<2)  /* Enable  PHY Loopback Mode */
4657 -#define SK_PHY_LOOPB_OFF       (1<<3)  /* Disable PHY Loopback Mode */
4658 -#define SK_PHY_FULLD_ON                (1<<4)  /* Enable  GMII Full Duplex */
4659 -#define SK_PHY_FULLD_OFF       (1<<5)  /* Disable GMII Full Duplex */
4660 +#define SK_MAC_LOOPB_ON                BIT_0S  /* Enable  MAC Loopback Mode */
4661 +#define SK_MAC_LOOPB_OFF       BIT_1S  /* Disable MAC Loopback Mode */
4662 +#define SK_PHY_LOOPB_ON                BIT_2S  /* Enable  PHY Loopback Mode */
4663 +#define SK_PHY_LOOPB_OFF       BIT_3S  /* Disable PHY Loopback Mode */
4664 +#define SK_PHY_FULLD_ON                BIT_4S  /* Enable  GMII Full Duplex */
4665 +#define SK_PHY_FULLD_OFF       BIT_5S  /* Disable GMII Full Duplex */
4666
4667  /* States of PState */
4668  #define SK_PRT_RESET   0       /* the port is reset */
4669 @@ -266,18 +276,25 @@
4670
4671  /* PHY power down modes */
4672  #define PHY_PM_OPERATIONAL_MODE                0       /* PHY operational mode */
4673 -#define PHY_PM_DEEP_SLEEP                      1       /* coma mode --> minimal power */
4674 +#define PHY_PM_DEEP_SLEEP                      1       /* Coma mode --> minimal power */
4675  #define PHY_PM_IEEE_POWER_DOWN         2       /* IEEE 22.2.4.1.5 compl. power down */
4676 -#define PHY_PM_ENERGY_DETECT           3       /* energy detect */
4677 -#define PHY_PM_ENERGY_DETECT_PLUS      4       /* energy detect plus */
4678 +#define PHY_PM_ENERGY_DETECT           3       /* Energy detect */
4679 +#define PHY_PM_ENERGY_DETECT_PLUS      4       /* Energy detect plus */
4680 +
4681 +/* PCI Bus Types */
4682 +#define SK_PCI_BUS             BIT_0S          /* normal PCI bus */
4683 +#define SK_PCIX_BUS            BIT_1S          /* PCI-X bus */
4684 +#define SK_PEX_BUS             BIT_2S          /* PCI-Express bus */
4685
4686  /* Default receive frame limit for Workaround of XMAC Errata */
4687  #define SK_DEF_RX_WA_LIM       SK_CONSTU64(100)
4688
4689  /* values for GILedBlinkCtrl (LED Blink Control) */
4690 -#define SK_ACT_LED_BLINK       (1<<0)  /* Active LED blinking */
4691 -#define SK_DUP_LED_NORMAL      (1<<1)  /* Duplex LED normal */
4692 -#define SK_LED_LINK100_ON      (1<<2)  /* Link 100M LED on */
4693 +#define SK_ACT_LED_BLINK       BIT_0S  /* Active LED blinking */
4694 +#define SK_DUP_LED_NORMAL      BIT_1S  /* Duplex LED normal */
4695 +#define SK_LED_LINK100_ON      BIT_2S  /* Link 100M LED on */
4696 +#define SK_DUAL_LED_ACT_LNK    BIT_3S  /* Dual LED ACT/LNK configuration */
4697 +#define SK_LED_LINK_MUX_P60    BIT_4S  /* Link LED muxed to pin 60 */
4698
4699  /* Link Partner Status */
4700  #define SK_LIPA_UNKNOWN        0       /* Link partner is in unknown state */
4701 @@ -290,18 +307,187 @@
4702  /* Max. Auto-neg. timeouts before link detection in sense mode is reset */
4703  #define SK_MAX_ANEG_TO 10      /* Max. 10 times the sense mode is reset */
4704
4705 +
4706 +/******************************************************************************
4707 + *
4708 + * HW_FEATURE() macro
4709 + */
4710 +
4711 +/* DWORD 0: Features */
4712 +#define HWF_FORCE_AUTO_NEG             0x04000000UL    /* Force Auto-Negotiation */
4713 +#define HWF_CLK_GATING_ENABLE  0x02000000UL    /* Enable Clock Gating */
4714 +#define HWF_RED_CORE_CLK_SUP   0x01000000UL    /* Reduced Core Clock supp. */
4715 +#define HWF_RESTORE_LOST_BARS  0x00800000UL    /* save and restore PCI bars */
4716 +#define HWF_ASPM_SWITCHING             0x00400000UL    /* activate ASPM feature */
4717 +
4718 +/*-RMV- DWORD 1: Deviations */
4719 +#define HWF_WA_DEV_4200                        0x10200000UL    /*-RMV- 4.200 (D3 Blue Screen)*/
4720 +#define HWF_WA_DEV_4185CS              0x10100000UL    /*-RMV- 4.185 (ECU 100 CS cal)*/
4721 +#define HWF_WA_DEV_4185                        0x10080000UL    /*-RMV- 4.185 (ECU Tx h check)*/
4722 +#define HWF_WA_DEV_4167                        0x10040000UL    /*-RMV- 4.167 (Rx OvSize Hang)*/
4723 +#define HWF_WA_DEV_4152                        0x10020000UL    /*-RMV- 4.152 (RSS issue) */
4724 +#define HWF_WA_DEV_4115                        0x10010000UL    /*-RMV- 4.115 (Rx MAC FIFO) */
4725 +#define HWF_WA_DEV_4109                        0x10008000UL    /*-RMV- 4.109 (BIU hang) */
4726 +#define HWF_WA_DEV_483                 0x10004000UL    /*-RMV- 4.83 (Rx TCP wrong) */
4727 +#define HWF_WA_DEV_479                 0x10002000UL    /*-RMV- 4.79 (Rx BMU hang II) */
4728 +#define HWF_WA_DEV_472                 0x10001000UL    /*-RMV- 4.72 (GPHY2 MDC clk) */
4729 +#define HWF_WA_DEV_463                 0x10000800UL    /*-RMV- 4.63 (Rx BMU hang I) */
4730 +#define HWF_WA_DEV_427                 0x10000400UL    /*-RMV- 4.27 (Tx Done Rep) */
4731 +#define HWF_WA_DEV_42                  0x10000200UL    /*-RMV- 4.2 (pref unit burst) */
4732 +#define HWF_WA_DEV_46                  0x10000100UL    /*-RMV- 4.6 (CPU crash II) */
4733 +#define HWF_WA_DEV_43_418              0x10000080UL    /*-RMV- 4.3 & 4.18 (PCI unexp */
4734 +                                                                                               /*-RMV- compl&Stat BMU deadl) */
4735 +#define HWF_WA_DEV_420                 0x10000040UL    /*-RMV- 4.20 (Status BMU ov) */
4736 +#define HWF_WA_DEV_423                 0x10000020UL    /*-RMV- 4.23 (TCP Segm Hang) */
4737 +#define HWF_WA_DEV_424                 0x10000010UL    /*-RMV- 4.24 (MAC reg overwr) */
4738 +#define HWF_WA_DEV_425                 0x10000008UL    /*-RMV- 4.25 (Magic packet */
4739 +                                                                                               /*-RMV- with odd offset) */
4740 +#define HWF_WA_DEV_428                 0x10000004UL    /*-RMV- 4.28 (Poll-U &BigEndi)*/
4741 +#define HWF_WA_FIFO_FLUSH_YLA0 0x10000002UL    /*-RMV- dis Rx GMAC FIFO Flush*/
4742 +                                                                                               /*-RMV- for Yu-L Rev. A0 only */
4743 +#define HWF_WA_COMA_MODE               0x10000001UL    /*-RMV- Coma Mode WA req */
4744 +
4745 +/* DWORD 2: Real HW features not settable from outside */
4746 +/* not yet used */
4747 +#if 0
4748 +#define HWF_SYNC_TX_SUP                        0x20800000UL    /* Synch. Tx Queue available */
4749 +#define HWF_SINGLE_PORT_DEVICE 0x20400000UL    /* Device has only one LAN IF */
4750 +#define HWF_JUMBO_FRAMES_SUP   0x20200000UL    /* Jumbo Frames supported */
4751 +#define HWF_TX_TCP_CSUM_SUP            0x20100000UL    /* TCP Tx checksum supported */
4752 +#define HWF_TX_UDP_CSUM_SUP            0x20080000UL    /* UDP Tx checksum supported */
4753 +#define HWF_RX_CSUM_SUP                        0x20040000UL    /* RX checksum supported */
4754 +#define HWF_TCP_SEGM_SUP               0x20020000UL    /* TCP segmentation supported */
4755 +#define HWF_RSS_HASH_SUP               0x20010000UL    /* RSS Hash supported */
4756 +#define HWF_PORT_VLAN_SUP              0x20008000UL    /* VLAN can be config per port*/
4757 +#define HWF_ROLE_PARAM_SUP             0x20004000UL    /* Role parameter supported */
4758 +#define HWF_LOW_PMODE_SUP              0x20002000UL    /* Low Power Mode supported */
4759 +#define HWF_ENERGIE_DEMO_SUP   0x20001000UL    /* Energy Detect mode supp. */
4760 +#define HWF_SPEED1000_SUP              0x20000800UL    /* Line Speed 1000 supported */
4761 +#define HWF_SPEED100_SUP               0x20000400UL    /* Line Speed 100 supported */
4762 +#define HWF_SPEED10_SUP                        0x20000200UL    /* Line Speed 10 supported */
4763 +#define HWF_AUTONEGSENSE_SUP   0x20000100UL    /* Autoneg Sense supported */
4764 +#define HWF_PHY_LOOPB_MD_SUP   0x20000080UL    /* PHY loopback mode supp. */
4765 +#define HWF_ASF_SUP                            0x20000040UL    /* ASF support possible */
4766 +#define HWF_QS_STEPS_1KB               0x20000020UL    /* The Rx/Tx queues can be */
4767 +                                                                                               /* configured with 1 kB res. */
4768 +#define HWF_OWN_RAM_PER_PORT   0x20000010UL    /* Each port has a separate */
4769 +                                                                                               /* RAM buffer */
4770 +#define HWF_MIN_LED_IF                 0x20000008UL    /* Minimal LED interface */
4771 +                                                                                               /* (e.g. for Yukon-EC) */
4772 +#define HWF_LIST_ELEMENTS_USED 0x20000004UL    /* HW uses list elements */
4773 +                                                                                               /* (otherwise desc. are used) */
4774 +#define HWF_GMAC_INSIDE                        0x20000002UL    /* Device contains GMAC */
4775 +#define HWF_TWSI_PRESENT               0x20000001UL    /* TWSI sensor bus present */
4776 +#endif
4777 +
4778 +/* DWORD 3: still unused */
4779 +
4780 +
4781 +/*
4782 + * HW_FEATURE()        -       returns whether the feature is serviced or not
4783 + */
4784 +#define HW_FEATURE(pAC, ReqFeature) \
4785 +       (((pAC)->GIni.HwF.Features[((ReqFeature) & 0x30000000UL) >> 28] &\
4786 +        ((ReqFeature) & 0x0fffffffUL)) != 0)
4787 +
4788 +#define HW_FEAT_LIST   0
4789 +#define HW_DEV_LIST            1
4790 +#define HW_FEAT_LIST_2 2
4791 +
4792 +#define SET_HW_FEATURE_MASK(pAC, List, OffMaskValue, OnMaskValue) {    \
4793 +       if ((List) == HW_FEAT_LIST || (List) == HW_DEV_LIST) {                  \
4794 +               (pAC)->GIni.HwF.OffMask[List] = (OffMaskValue);                         \
4795 +               (pAC)->GIni.HwF.OnMask[List] = (OnMaskValue);                           \
4796 +       }                                                                                                                               \
4797 +}
4798 +
4799 +/* driver access macros for GIni structure ***********************************/
4800 +
4801 +#define CHIP_ID_YUKON_2(pAC)           ((pAC)->GIni.GIYukon2)
4802 +
4803 +#define HW_SYNC_TX_SUPPORTED(pAC)                                              \
4804 +               ((pAC)->GIni.GIChipId != CHIP_ID_YUKON_EC &&    \
4805 +                (pAC)->GIni.GIChipId != CHIP_ID_YUKON_FE &&    \
4806 +                (pAC)->GIni.GIChipId != CHIP_ID_YUKON_EC_U)
4807 +
4808 +#define HW_MS_TO_TICKS(pAC, MsTime) \
4809 +       ((MsTime) * (62500L/100) * (pAC)->GIni.GIHstClkFact)
4810 +
4811 +#define HW_IS_8056(pAC)                                                                        \
4812 +       ((pAC)->GIni.GIChipId == CHIP_ID_YUKON_EC_U &&          \
4813 +         (pAC)->GIni.GIChipRev == CHIP_REV_YU_EC_U_A1 &&       \
4814 +         (pAC)->GIni.GIChipCap == 2 &&                                         \
4815 +       !HW_FEATURE(pAC, HWF_WA_DEV_4200))
4816 +
4817 +#ifdef XXX
4818 +/* still under construction */
4819 +#define HW_IS_SINGLE_PORT(pAC)         ((pAC)->GIni.GIMacsFound == 1)
4820 +#define HW_NUMBER_OF_PORTS(pAC)                ((pAC)->GIni.GIMacsFound)
4821 +
4822 +#define HW_TX_UDP_CSUM_SUPPORTED(pAC) \
4823 +       ((((pAC)->GIni.GIChipId >= CHIP_ID_YUKON) && ((pAC)->GIni.GIChipRev != 0))
4824 +
4825 +#define HW_DEFAULT_LINESPEED(pAC)      \
4826 +       ((!(pAC)->GIni.GIGenesis && (pAC)->GIni.GICopperType) ? \
4827 +       SK_LSPEED_AUTO : SK_LSPEED_1000MBPS)
4828 +
4829 +#define HW_ROLE_PARAM_SUPPORTED(pAC)   ((pAC)->GIni.GICopperType)
4830 +
4831 +#define HW_SPEED1000_SUPPORTED(pAC, Port)              \
4832 +        ((pAC)->GIni.GP[Port].PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS)
4833 +
4834 +#define HW_SPEED100_SUPPORTED(pAC, Port)               \
4835 +        ((pAC)->GIni.GP[Port].PLinkSpeedCap & SK_LSPEED_CAP_100MBPS)
4836 +
4837 +#define HW_SPEED10_SUPPORTED(pAC, Port)                \
4838 +        ((pAC)->GIni.GP[Port].PLinkSpeedCap & SK_LSPEED_CAP_10MBPS)
4839 +
4840 +#define HW_AUTONEGSENSE_SUPPORTED(pAC) ((pAC)->GIni.GP[0].PhyType==SK_PHY_XMAC)
4841 +
4842 +#define HW_FREQ_TO_CARD_TICKS(pAC, AdapterClkSpeed, Freq) \
4843 +       (((AdapterClkSpeed / 100) * (pAC)->GIni.GIHstClkFact) / Freq)
4844 +
4845 +#define HW_IS_LINK_UP(pAC, Port)               ((pAC)->GIni.GP[Port].PHWLinkUp)
4846 +#define HW_LINK_SPEED_USED(pAC, Port)  ((pAC)->GIni.GP[Port].PLinkSpeedUsed)
4847 +#define HW_RAM_SIZE(pAC)                               ((pAC)->GIni.GIRamSize)
4848 +
4849 +#define HW_PHY_LP_MODE_SUPPORTED(pAC)  (pAC0->???
4850 +#define HW_ASF_ACTIVE(pAC)                             ???
4851 +#define RAWIO_OUT32(pAC, pAC->RegIrqMask, pAC->GIni.GIValIrqMask)...
4852 +
4853 +/* macro to check whether Tx checksum is supported */
4854 +#define HW_TX_CSUM_SUPPORTED(pAC)      ((pAC)->GIni.GIChipId != CHIP_ID_GENESIS)
4855 +
4856 +BMU_UDP_CHECK : BMU_TCP_CHECK;
4857 +
4858 +/* macro for - Own Bit mirrored to DWORD7 (Yukon LP receive descriptor) */
4859 +#endif /* 0 */
4860 +
4861 +
4862  /* structures *****************************************************************/
4863
4864  /*
4865 + * HW Feature structure
4866 + */
4867 +typedef struct s_HwFeatures {
4868 +       SK_U32  Features[4];    /* Feature list */
4869 +       SK_U32  OffMask[4];             /* Off Mask */
4870 +       SK_U32  OnMask[4];              /* On Mask */
4871 +} SK_HW_FEATURES;
4872 +
4873 +/*
4874   * MAC specific functions
4875   */
4876  typedef struct s_GeMacFunc {
4877 -       int  (*pFnMacUpdateStats)(SK_AC *pAC, SK_IOC IoC, unsigned int Port);
4878 -       int  (*pFnMacStatistic)(SK_AC *pAC, SK_IOC IoC, unsigned int Port,
4879 -                                                       SK_U16 StatAddr, SK_U32 SK_FAR *pVal);
4880 -       int  (*pFnMacResetCounter)(SK_AC *pAC, SK_IOC IoC, unsigned int Port);
4881 -       int  (*pFnMacOverflow)(SK_AC *pAC, SK_IOC IoC, unsigned int Port,
4882 -                                                  SK_U16 IStatus, SK_U64 SK_FAR *pVal);
4883 +       int     (*pFnMacUpdateStats)(SK_AC *, SK_IOC, unsigned int);
4884 +       int     (*pFnMacStatistic)(SK_AC *, SK_IOC, unsigned int, SK_U16, SK_U32 SK_FAR *);
4885 +       int     (*pFnMacResetCounter)(SK_AC *, SK_IOC, unsigned int);
4886 +       int     (*pFnMacOverflow)(SK_AC *, SK_IOC, unsigned int, SK_U16, SK_U64 SK_FAR *);
4887 +       void (*pSkGeSirqIsr)(SK_AC *, SK_IOC, SK_U32);
4888 +#ifdef SK_DIAG
4889 +       int     (*pFnMacPhyRead)(SK_AC *, SK_IOC, int, int, SK_U16 SK_FAR *);
4890 +       int     (*pFnMacPhyWrite)(SK_AC *, SK_IOC, int, int, SK_U16);
4891 +#endif /* SK_DIAG */
4892  } SK_GEMACFUNC;
4893
4894  /*
4895 @@ -311,7 +497,7 @@
4896  #ifndef SK_DIAG
4897         SK_TIMER        PWaTimer;       /* Workaround Timer */
4898         SK_TIMER        HalfDupChkTimer;
4899 -#endif /* SK_DIAG */
4900 +#endif /* !SK_DIAG */
4901         SK_U32  PPrevShorts;    /* Previous Short Counter checking */
4902         SK_U32  PPrevFcs;               /* Previous FCS Error Counter checking */
4903         SK_U64  PPrevRx;                /* Previous RxOk Counter checking */
4904 @@ -335,6 +521,7 @@
4905         int             PXaQOff;                /* Asynchronous Tx Queue Address Offset */
4906         int             PhyType;                /* PHY used on this port */
4907         int             PState;                 /* Port status (reset, stop, init, run) */
4908 +       int             PPortUsage;             /* Driver Port Usage */
4909         SK_U16  PhyId1;                 /* PHY Id1 on this port */
4910         SK_U16  PhyAddr;                /* MDIO/MDC PHY address */
4911         SK_U16  PIsave;                 /* Saved Interrupt status word */
4912 @@ -348,7 +535,7 @@
4913         SK_U8   PLinkModeConf;  /* Link Mode configured */
4914         SK_U8   PLinkMode;              /* Link Mode currently used */
4915         SK_U8   PLinkModeStatus;/* Link Mode Status */
4916 -       SK_U8   PLinkSpeedCap;  /* Link Speed Capabilities(10/100/1000 Mbps) */
4917 +       SK_U8   PLinkSpeedCap;  /* Link Speed Capabilities (10/100/1000 Mbps) */
4918         SK_U8   PLinkSpeed;             /* configured Link Speed (10/100/1000 Mbps) */
4919         SK_U8   PLinkSpeedUsed; /* current Link Speed (10/100/1000 Mbps) */
4920         SK_U8   PFlowCtrlCap;   /* Flow Control Capabilities */
4921 @@ -367,7 +554,10 @@
4922         int             PMacJamLen;             /* MAC Jam length */
4923         int             PMacJamIpgVal;  /* MAC Jam IPG */
4924         int             PMacJamIpgData; /* MAC IPG Jam to Data */
4925 +       int             PMacBackOffLim; /* MAC Back-off Limit */
4926 +       int             PMacDataBlind;  /* MAC Data Blinder */
4927         int             PMacIpgData;    /* MAC Data IPG */
4928 +       SK_U16  PMacAddr[3];    /* MAC address */
4929         SK_BOOL PMacLimit4;             /* reset collision counter and backoff algorithm */
4930  } SK_GEPORT;
4931
4932 @@ -379,27 +569,38 @@
4933         int                     GIChipId;               /* Chip Identification Number */
4934         int                     GIChipRev;              /* Chip Revision Number */
4935         SK_U8           GIPciHwRev;             /* PCI HW Revision Number */
4936 +       SK_U8           GIPciBus;               /* PCI Bus Type (PCI / PCI-X / PCI-Express) */
4937 +       SK_U8           GIPciMode;              /* PCI / PCI-X Mode @ Clock */
4938 +       SK_U8           GIPexWidth;             /* PCI-Express Negotiated Link Width */
4939         SK_BOOL         GIGenesis;              /* Genesis adapter ? */
4940 -       SK_BOOL         GIYukon;                /* YUKON-A1/Bx chip */
4941 +       SK_BOOL         GIYukon;                /* YUKON family (1 and 2) */
4942         SK_BOOL         GIYukonLite;    /* YUKON-Lite chip */
4943 +       SK_BOOL         GIYukon2;               /* YUKON-2 chip (-XL, -EC or -FE) */
4944 +       SK_U8           GIConTyp;               /* Connector Type */
4945 +       SK_U8           GIPmdTyp;               /* PMD Type */
4946         SK_BOOL         GICopperType;   /* Copper Type adapter ? */
4947         SK_BOOL         GIPciSlot64;    /* 64-bit PCI Slot */
4948         SK_BOOL         GIPciClock66;   /* 66 MHz PCI Clock */
4949         SK_BOOL         GIVauxAvail;    /* VAUX available (YUKON) */
4950         SK_BOOL         GIYukon32Bit;   /* 32-Bit YUKON adapter */
4951 +       SK_BOOL         GIAsfEnabled;   /* ASF subsystem enabled */
4952 +       SK_BOOL         GIAsfRunning;   /* ASF subsystem running */
4953         SK_U16          GILedBlinkCtrl; /* LED Blink Control */
4954         int                     GIMacsFound;    /* Number of MACs found on this adapter */
4955         int                     GIMacType;              /* MAC Type used on this adapter */
4956 -       int                     GIHstClkFact;   /* Host Clock Factor (62.5 / HstClk * 100) */
4957 -       int                     GIPortUsage;    /* Driver Port Usage */
4958 +       int                     GIChipCap;              /* Adapter's Capabilities */
4959 +       int                     GIHwResInfo;    /* HW Resources / Application Information */
4960 +       int                     GIHstClkFact;   /* Host Clock Factor (HstClk / 62.5 * 100) */
4961         int                     GILevel;                /* Initialization Level completed */
4962         int                     GIRamSize;              /* The RAM size of the adapter in kB */
4963         int                     GIWolOffs;              /* WOL Register Offset (HW-Bug in Rev. A) */
4964         SK_U32          GIRamOffs;              /* RAM Address Offset for addr calculation */
4965         SK_U32          GIPollTimerVal; /* Descr. Poll Timer Init Val (HstClk ticks) */
4966         SK_U32          GIValIrqMask;   /* Value for Interrupt Mask */
4967 +       SK_U32          GIValHwIrqMask; /* Value for HWE Interrupt Mask */
4968         SK_U32          GITimeStampCnt; /* Time Stamp High Counter (YUKON only) */
4969         SK_GEPORT       GP[SK_MAX_MACS];/* Port Dependent Information */
4970 +       SK_HW_FEATURES HwF;                     /* HW Features struct */
4971         SK_GEMACFUNC GIFunc;            /* MAC depedent functions */
4972  } SK_GEINIT;
4973
4974 @@ -417,7 +618,7 @@
4975  #define SKERR_HWI_E005         (SKERR_HWI_E004+1)
4976  #define SKERR_HWI_E005MSG      "SkGeInitPort(): cannot init running ports"
4977  #define SKERR_HWI_E006         (SKERR_HWI_E005+1)
4978 -#define SKERR_HWI_E006MSG      "SkGeMacInit(): PState does not match HW state"
4979 +#define SKERR_HWI_E006MSG      "SkGeInit() called with illegal Chip Id"
4980  #define SKERR_HWI_E007         (SKERR_HWI_E006+1)
4981  #define SKERR_HWI_E007MSG      "SkXmInitDupMd() called with invalid Dup Mode"
4982  #define SKERR_HWI_E008         (SKERR_HWI_E007+1)
4983 @@ -433,11 +634,11 @@
4984  #define SKERR_HWI_E013         (SKERR_HWI_E012+1)
4985  #define SKERR_HWI_E013MSG      "SkGeInitPort(): cfg changed for running queue"
4986  #define SKERR_HWI_E014         (SKERR_HWI_E013+1)
4987 -#define SKERR_HWI_E014MSG      "SkGeInitPort(): unknown GIPortUsage specified"
4988 +#define SKERR_HWI_E014MSG      "SkGeInitPort(): unknown PortUsage specified"
4989  #define SKERR_HWI_E015         (SKERR_HWI_E014+1)
4990 -#define SKERR_HWI_E015MSG      "Illegal Link mode parameter"
4991 +#define SKERR_HWI_E015MSG      "Illegal Link Mode parameter"
4992  #define SKERR_HWI_E016         (SKERR_HWI_E015+1)
4993 -#define SKERR_HWI_E016MSG      "Illegal Flow control mode parameter"
4994 +#define SKERR_HWI_E016MSG      "Illegal Flow Control Mode parameter"
4995  #define SKERR_HWI_E017         (SKERR_HWI_E016+1)
4996  #define SKERR_HWI_E017MSG      "Illegal value specified for GIPollTimerVal"
4997  #define SKERR_HWI_E018         (SKERR_HWI_E017+1)
4998 @@ -447,15 +648,19 @@
4999  #define SKERR_HWI_E020         (SKERR_HWI_E019+1)
5000  #define SKERR_HWI_E020MSG      "Illegal Master/Slave parameter"
5001  #define SKERR_HWI_E021         (SKERR_HWI_E020+1)
5002 -#define        SKERR_HWI_E021MSG       "MacUpdateStats(): cannot update statistic counter"
5003 -#define        SKERR_HWI_E022          (SKERR_HWI_E021+1)
5004 -#define        SKERR_HWI_E022MSG       "MacStatistic(): illegal statistic base address"
5005 +#define SKERR_HWI_E021MSG      "MacUpdateStats(): cannot update statistic counter"
5006 +#define SKERR_HWI_E022         (SKERR_HWI_E021+1)
5007 +#define SKERR_HWI_E022MSG      "MacStatistic(): illegal statistic base address"
5008  #define SKERR_HWI_E023         (SKERR_HWI_E022+1)
5009  #define SKERR_HWI_E023MSG      "SkGeInitPort(): Transmit Queue Size too small"
5010  #define SKERR_HWI_E024         (SKERR_HWI_E023+1)
5011  #define SKERR_HWI_E024MSG      "FATAL: SkGeStopPort() does not terminate (Rx)"
5012  #define SKERR_HWI_E025         (SKERR_HWI_E024+1)
5013 -#define SKERR_HWI_E025MSG      ""
5014 +#define SKERR_HWI_E025MSG      "Link Partner not Auto-Neg. able"
5015 +#define SKERR_HWI_E026         (SKERR_HWI_E025+1)
5016 +#define SKERR_HWI_E026MSG      "PEX negotiated Link width not max."
5017 +#define SKERR_HWI_E027         (SKERR_HWI_E026+1)
5018 +#define SKERR_HWI_E027MSG      ""
5019
5020  /* function prototypes ********************************************************/
5021
5022 @@ -464,6 +669,30 @@
5023  /*
5024   * public functions in skgeinit.c
5025   */
5026 +extern void SkGePortVlan(
5027 +       SK_AC   *pAC,
5028 +       SK_IOC  IoC,
5029 +       int             Port,
5030 +       SK_BOOL Enable);
5031 +
5032 +extern void SkGeRxRss(
5033 +       SK_AC   *pAC,
5034 +       SK_IOC  IoC,
5035 +       int             Port,
5036 +       SK_BOOL Enable);
5037 +
5038 +extern void SkGeRxCsum(
5039 +       SK_AC   *pAC,
5040 +       SK_IOC  IoC,
5041 +       int             Port,
5042 +       SK_BOOL Enable);
5043 +
5044 +extern void    SkGePollRxD(
5045 +       SK_AC   *pAC,
5046 +       SK_IOC  IoC,
5047 +       int             Port,
5048 +       SK_BOOL PollRxD);
5049 +
5050  extern void    SkGePollTxD(
5051         SK_AC   *pAC,
5052         SK_IOC  IoC,
5053 @@ -516,11 +745,28 @@
5054         int             Led,
5055         int             Mode);
5056
5057 +extern void    SkGeInitRamIface(
5058 +       SK_AC   *pAC,
5059 +       SK_IOC  IoC);
5060 +
5061  extern int     SkGeInitAssignRamToQueues(
5062         SK_AC   *pAC,
5063 -       int             ActivePort,
5064 +       int             Port,
5065         SK_BOOL DualNet);
5066
5067 +extern void    DoInitRamQueue(
5068 +       SK_AC   *pAC,
5069 +       SK_IOC  IoC,
5070 +       int             QuIoOffs,
5071 +       SK_U32  QuStartAddr,
5072 +       SK_U32  QuEndAddr,
5073 +       int             QuType);
5074 +
5075 +extern int     SkYuk2RestartRxBmu(
5076 +       SK_AC   *pAC,
5077 +       SK_IOC  IoC,
5078 +       int             Port);
5079 +
5080  /*
5081   * public functions in skxmac2.c
5082   */
5083 @@ -539,6 +785,11 @@
5084         SK_IOC  IoC,
5085         int             Port);
5086
5087 +extern void    SkMacClearRst(
5088 +       SK_AC   *pAC,
5089 +       SK_IOC  IoC,
5090 +       int             Port);
5091 +
5092  extern void    SkXmInitMac(
5093         SK_AC   *pAC,
5094         SK_IOC  IoC,
5095 @@ -565,6 +816,11 @@
5096         SK_IOC  IoC,
5097         int             Port);
5098
5099 +extern void    SkMacFlushRxFifo(
5100 +       SK_AC   *pAC,
5101 +       SK_IOC  IoC,
5102 +       int             Port);
5103 +
5104  extern void    SkMacIrq(
5105         SK_AC   *pAC,
5106         SK_IOC  IoC,
5107 @@ -581,7 +837,13 @@
5108         int             Port,
5109         SK_U16  IStatus);
5110
5111 -extern int  SkMacRxTxEnable(
5112 +extern void    SkMacSetRxTxEn(
5113 +       SK_AC   *pAC,
5114 +       SK_IOC  IoC,
5115 +       int             Port,
5116 +       int             Para);
5117 +
5118 +extern int     SkMacRxTxEnable(
5119         SK_AC   *pAC,
5120         SK_IOC  IoC,
5121         int             Port);
5122 @@ -598,28 +860,28 @@
5123         int             Port,
5124         SK_BOOL Enable);
5125
5126 -extern void    SkXmPhyRead(
5127 +extern int     SkXmPhyRead(
5128         SK_AC   *pAC,
5129         SK_IOC  IoC,
5130         int             Port,
5131         int             Addr,
5132         SK_U16  SK_FAR *pVal);
5133
5134 -extern void    SkXmPhyWrite(
5135 +extern int     SkXmPhyWrite(
5136         SK_AC   *pAC,
5137         SK_IOC  IoC,
5138         int             Port,
5139         int             Addr,
5140         SK_U16  Val);
5141
5142 -extern void    SkGmPhyRead(
5143 +extern int     SkGmPhyRead(
5144         SK_AC   *pAC,
5145         SK_IOC  IoC,
5146         int             Port,
5147         int             Addr,
5148         SK_U16  SK_FAR *pVal);
5149
5150 -extern void    SkGmPhyWrite(
5151 +extern int     SkGmPhyWrite(
5152         SK_AC   *pAC,
5153         SK_IOC  IoC,
5154         int             Port,
5155 @@ -633,6 +895,16 @@
5156         int             StartNum,
5157         int             StopNum);
5158
5159 +extern void    SkXmInitDupMd(
5160 +       SK_AC   *pAC,
5161 +       SK_IOC  IoC,
5162 +       int             Port);
5163 +
5164 +extern void    SkXmInitPauseMd(
5165 +       SK_AC   *pAC,
5166 +       SK_IOC  IoC,
5167 +       int             Port);
5168 +
5169  extern void    SkXmAutoNegLipaXmac(
5170         SK_AC   *pAC,
5171         SK_IOC  IoC,
5172 @@ -677,7 +949,7 @@
5173         SK_AC   *pAC,
5174         SK_IOC  IoC,
5175         unsigned int Port,
5176 -       SK_U16  IStatus,
5177 +       SK_U16  IStatus,
5178         SK_U64  SK_FAR *pStatus);
5179
5180  extern int SkGmOverflowStatus(
5181 @@ -693,6 +965,19 @@
5182         int             Port,
5183         SK_BOOL StartTest);
5184
5185 +#ifdef SK_PHY_LP_MODE
5186 +extern int SkGmEnterLowPowerMode(
5187 +       SK_AC   *pAC,
5188 +       SK_IOC  IoC,
5189 +       int             Port,
5190 +       SK_U8   Mode);
5191 +
5192 +extern int SkGmLeaveLowPowerMode(
5193 +       SK_AC   *pAC,
5194 +       SK_IOC  IoC,
5195 +       int             Port);
5196 +#endif /* SK_PHY_LP_MODE */
5197 +
5198  #ifdef SK_DIAG
5199  extern void    SkGePhyRead(
5200         SK_AC   *pAC,
5201 @@ -735,6 +1020,7 @@
5202  /*
5203   * public functions in skgeinit.c
5204   */
5205 +extern void    SkGePollRxD();
5206  extern void    SkGePollTxD();
5207  extern void    SkGeYellowLED();
5208  extern int     SkGeCfgSync();
5209 @@ -744,30 +1030,41 @@
5210  extern void    SkGeDeInit();
5211  extern int     SkGeInitPort();
5212  extern void    SkGeXmitLED();
5213 +extern void    SkGeInitRamIface();
5214  extern int     SkGeInitAssignRamToQueues();
5215 +extern void    SkGePortVlan();
5216 +extern void    SkGeRxCsum();
5217 +extern void    SkGeRxRss();
5218 +extern void    DoInitRamQueue();
5219 +extern int     SkYuk2RestartRxBmu();
5220
5221  /*
5222   * public functions in skxmac2.c
5223   */
5224 -extern void SkMacRxTxDisable();
5225 +extern void    SkMacRxTxDisable();
5226  extern void    SkMacSoftRst();
5227  extern void    SkMacHardRst();
5228 -extern void SkMacInitPhy();
5229 -extern int  SkMacRxTxEnable();
5230 -extern void SkMacPromiscMode();
5231 -extern void SkMacHashing();
5232 -extern void SkMacIrqDisable();
5233 +extern void    SkMacClearRst();
5234 +extern void    SkMacInitPhy();
5235 +extern int     SkMacRxTxEnable();
5236 +extern void    SkMacPromiscMode();
5237 +extern void    SkMacHashing();
5238 +extern void    SkMacIrqDisable();
5239  extern void    SkMacFlushTxFifo();
5240 +extern void    SkMacFlushRxFifo();
5241  extern void    SkMacIrq();
5242  extern int     SkMacAutoNegDone();
5243  extern void    SkMacAutoNegLipaPhy();
5244 +extern void    SkMacSetRxTxEn();
5245  extern void    SkXmInitMac();
5246 -extern void    SkXmPhyRead();
5247 -extern void    SkXmPhyWrite();
5248 +extern int     SkXmPhyRead();
5249 +extern int     SkXmPhyWrite();
5250  extern void    SkGmInitMac();
5251 -extern void    SkGmPhyRead();
5252 -extern void    SkGmPhyWrite();
5253 +extern int     SkGmPhyRead();
5254 +extern int     SkGmPhyWrite();
5255  extern void    SkXmClrExactAddr();
5256 +extern void    SkXmInitDupMd();
5257 +extern void    SkXmInitPauseMd();
5258  extern void    SkXmAutoNegLipaXmac();
5259  extern int     SkXmUpdateStats();
5260  extern int     SkGmUpdateStats();
5261 @@ -778,6 +1075,10 @@
5262  extern int     SkXmOverflowStatus();
5263  extern int     SkGmOverflowStatus();
5264  extern int     SkGmCableDiagStatus();
5265 +#ifdef SK_PHY_LP_MODE
5266 +extern int     SkGmEnterLowPowerMode();
5267 +extern int     SkGmLeaveLowPowerMode();
5268 +#endif /* SK_PHY_LP_MODE */
5269
5270  #ifdef SK_DIAG
5271  extern void    SkGePhyRead();
5272 @@ -788,10 +1089,11 @@
5273  extern void    SkXmSendCont();
5274  #endif /* SK_DIAG */
5275
5276 -#endif /* SK_KR_PROTO */
5277 +#endif /* SK_KR_PROTO */
5278
5279  #ifdef __cplusplus
5280  }
5281 -#endif /* __cplusplus */
5282 +#endif /* __cplusplus */
5283 +
5284 +#endif /* __INC_SKGEINIT_H_ */
5285
5286 -#endif /* __INC_SKGEINIT_H_ */
5287 diff -ruN linux/drivers/net/sk98lin/h/skgepnm2.h linux-new/drivers/net/sk98lin/h/skgepnm2.h
5288 --- linux/drivers/net/sk98lin/h/skgepnm2.h      2006-09-20 05:42:06.000000000 +0200
5289 +++ linux-new/drivers/net/sk98lin/h/skgepnm2.h  2006-07-28 14:13:54.000000000 +0200
5290 @@ -2,14 +2,15 @@
5291   *
5292   * Name:       skgepnm2.h
5293   * Project:    GEnesis, PCI Gigabit Ethernet Adapter
5294 - * Version:    $Revision$
5295 - * Date:       $Date$
5296 + * Version:    $Revision$
5297 + * Date:       $Date$
5298   * Purpose:    Defines for Private Network Management Interface
5299   *
5300   ****************************************************************************/
5301
5302  /******************************************************************************
5303   *
5304 + *     LICENSE:
5305   *     (C)Copyright 1998-2002 SysKonnect GmbH.
5306   *     (C)Copyright 2002-2003 Marvell.
5307   *
5308 @@ -19,6 +20,7 @@
5309   *     (at your option) any later version.
5310   *
5311   *     The information in this file is provided "AS IS" without warranty.
5312 + *     /LICENSE
5313   *
5314   ******************************************************************************/
5315
5316 @@ -28,8 +30,13 @@
5317  /*
5318   * General definitions
5319   */
5320 -#define SK_PNMI_CHIPSET_XMAC   1       /* XMAC11800FP */
5321 -#define SK_PNMI_CHIPSET_YUKON  2       /* YUKON */
5322 +#define SK_PNMI_CHIPSET_XMAC           1       /* XMAC11800FP */
5323 +#define SK_PNMI_CHIPSET_YUKON          2       /* YUKON */
5324 +#define SK_PNMI_CHIPSET_YUKON_LITE     3       /* YUKON-Lite (Rev. A1-A3) */
5325 +#define SK_PNMI_CHIPSET_YUKON_LP       4       /* YUKON-LP */
5326 +#define SK_PNMI_CHIPSET_YUKON_XL       5       /* YUKON-2 XL */
5327 +#define SK_PNMI_CHIPSET_YUKON_EC       6       /* YUKON-2 EC */
5328 +#define SK_PNMI_CHIPSET_YUKON_FE       7       /* YUKON-2 FE */
5329
5330  #define        SK_PNMI_BUS_PCI         1       /* PCI bus*/
5331
5332 @@ -70,9 +77,9 @@
5333  /*
5334   * VCT internal status values
5335   */
5336 -#define SK_PNMI_VCT_PENDING    32
5337 -#define SK_PNMI_VCT_TEST_DONE  64
5338 -#define SK_PNMI_VCT_LINK       128
5339 +#define SK_PNMI_VCT_PENDING            0x20
5340 +#define SK_PNMI_VCT_TEST_DONE  0x40
5341 +#define SK_PNMI_VCT_LINK               0x80
5342
5343  /*
5344   * Internal table definitions
5345 @@ -323,7 +330,7 @@
5346                                                 vSt, \
5347                                                 pAC->Pnmi.MacUpdatedFlag, \
5348                                                 pAC->Pnmi.RlmtUpdatedFlag, \
5349 -                                               pAC->Pnmi.SirqUpdatedFlag))}}
5350 +                                               pAC->Pnmi.SirqUpdatedFlag));}}
5351
5352  #else  /* !DEBUG */
5353
5354 diff -ruN linux/drivers/net/sk98lin/h/skgepnmi.h linux-new/drivers/net/sk98lin/h/skgepnmi.h
5355 --- linux/drivers/net/sk98lin/h/skgepnmi.h      2006-09-20 05:42:06.000000000 +0200
5356 +++ linux-new/drivers/net/sk98lin/h/skgepnmi.h  2006-07-28 14:13:54.000000000 +0200
5357 @@ -1,15 +1,16 @@
5358  /*****************************************************************************
5359   *
5360   * Name:       skgepnmi.h
5361 - * Project:    GEnesis, PCI Gigabit Ethernet Adapter
5362 - * Version:    $Revision$
5363 - * Date:       $Date$
5364 + * Project:    Gigabit Ethernet Adapters, PNMI-Module
5365 + * Version:    $Revision$
5366 + * Date:       $Date$
5367   * Purpose:    Defines for Private Network Management Interface
5368   *
5369   ****************************************************************************/
5370
5371  /******************************************************************************
5372   *
5373 + *     LICENSE:
5374   *     (C)Copyright 1998-2002 SysKonnect GmbH.
5375   *     (C)Copyright 2002-2003 Marvell.
5376   *
5377 @@ -19,6 +20,7 @@
5378   *     (at your option) any later version.
5379   *
5380   *     The information in this file is provided "AS IS" without warranty.
5381 + *     /LICENSE
5382   *
5383   ******************************************************************************/
5384
5385 @@ -31,7 +33,7 @@
5386  #include "h/sktypes.h"
5387  #include "h/skerror.h"
5388  #include "h/sktimer.h"
5389 -#include "h/ski2c.h"
5390 +#include "h/sktwsi.h"
5391  #include "h/skaddr.h"
5392  #include "h/skrlmt.h"
5393  #include "h/skvpd.h"
5394 @@ -41,7 +43,6 @@
5395   */
5396  #define SK_PNMI_MDB_VERSION            0x00030001      /* 3.1 */
5397
5398 -
5399  /*
5400   * Event definitions
5401   */
5402 @@ -54,16 +55,13 @@
5403  #define SK_PNMI_EVT_UTILIZATION_TIMER  7       /* Timer event for Utiliza. */
5404  #define SK_PNMI_EVT_CLEAR_COUNTER              8       /* Clear statistic counters */
5405  #define SK_PNMI_EVT_XMAC_RESET                 9       /* XMAC will be reset */
5406 -
5407  #define SK_PNMI_EVT_RLMT_PORT_UP               10      /* Port came logically up */
5408  #define SK_PNMI_EVT_RLMT_PORT_DOWN             11      /* Port went logically down */
5409  #define SK_PNMI_EVT_RLMT_SEGMENTATION  13      /* Two SP root bridges found */
5410  #define SK_PNMI_EVT_RLMT_ACTIVE_DOWN   14      /* Port went logically down */
5411  #define SK_PNMI_EVT_RLMT_ACTIVE_UP             15      /* Port came logically up */
5412 -#define SK_PNMI_EVT_RLMT_SET_NETS              16      /* 1. Parameter is number of nets
5413 -                                                                                               1 = single net; 2 = dual net */
5414 -#define SK_PNMI_EVT_VCT_RESET          17      /* VCT port reset timer event started with SET. */
5415 -
5416 +#define SK_PNMI_EVT_RLMT_SET_NETS              16      /* Number of nets (1 or 2). */
5417 +#define SK_PNMI_EVT_VCT_RESET                  17      /* VCT port reset timer event started with SET. */
5418
5419  /*
5420   * Return values
5421 @@ -78,7 +76,6 @@
5422  #define SK_PNMI_ERR_UNKNOWN_NET        7
5423  #define SK_PNMI_ERR_NOT_SUPPORTED      10
5424
5425 -
5426  /*
5427   * Return values of driver reset function SK_DRIVER_RESET() and
5428   * driver event function SK_DRIVER_EVENT()
5429 @@ -86,19 +83,17 @@
5430  #define SK_PNMI_ERR_OK                 0
5431  #define SK_PNMI_ERR_FAIL               1
5432
5433 -
5434  /*
5435   * Return values of driver test function SK_DRIVER_SELFTEST()
5436   */
5437  #define SK_PNMI_TST_UNKNOWN            (1 << 0)
5438 -#define SK_PNMI_TST_TRANCEIVER         (1 << 1)
5439 +#define SK_PNMI_TST_TRANCEIVER (1 << 1)
5440  #define SK_PNMI_TST_ASIC               (1 << 2)
5441  #define SK_PNMI_TST_SENSOR             (1 << 3)
5442 -#define SK_PNMI_TST_POWERMGMT          (1 << 4)
5443 +#define SK_PNMI_TST_POWERMGMT  (1 << 4)
5444  #define SK_PNMI_TST_PCI                        (1 << 5)
5445  #define SK_PNMI_TST_MAC                        (1 << 6)
5446
5447 -
5448  /*
5449   * RLMT specific definitions
5450   */
5451 @@ -223,7 +218,17 @@
5452  #define OID_SKGE_RLMT_PORT_NUMBER              0xFF010141
5453  #define OID_SKGE_RLMT_PORT_ACTIVE              0xFF010142
5454  #define OID_SKGE_RLMT_PORT_PREFERRED   0xFF010143
5455 -#define OID_SKGE_INTERMEDIATE_SUPPORT  0xFF010160
5456 +
5457 +#define OID_SKGE_RLMT_MONITOR_NUMBER   0xFF010150
5458 +#define OID_SKGE_RLMT_MONITOR_INDEX            0xFF010151
5459 +#define OID_SKGE_RLMT_MONITOR_ADDR             0xFF010152
5460 +#define OID_SKGE_RLMT_MONITOR_ERRS             0xFF010153
5461 +#define OID_SKGE_RLMT_MONITOR_TIMESTAMP        0xFF010154
5462 +#define OID_SKGE_RLMT_MONITOR_ADMIN            0xFF010155
5463 +
5464 +#define OID_SKGE_INTERMEDIATE_SUPPORT          0xFF010160
5465 +#define OID_SKGE_SET_TEAM_MAC_ADDRESS          0xFF010161
5466 +#define OID_SKGE_DEVICE_INFORMATION            0xFF010162
5467
5468  #define OID_SKGE_SPEED_CAP                             0xFF010170
5469  #define OID_SKGE_SPEED_MODE                            0xFF010171
5470 @@ -322,13 +327,6 @@
5471  #define OID_SKGE_RLMT_TX_SP_REQ_CTS            0xFF020168
5472  #define OID_SKGE_RLMT_RX_SP_CTS                        0xFF020169
5473
5474 -#define OID_SKGE_RLMT_MONITOR_NUMBER   0xFF010150
5475 -#define OID_SKGE_RLMT_MONITOR_INDEX            0xFF010151
5476 -#define OID_SKGE_RLMT_MONITOR_ADDR             0xFF010152
5477 -#define OID_SKGE_RLMT_MONITOR_ERRS             0xFF010153
5478 -#define OID_SKGE_RLMT_MONITOR_TIMESTAMP        0xFF010154
5479 -#define OID_SKGE_RLMT_MONITOR_ADMIN            0xFF010155
5480 -
5481  #define OID_SKGE_TX_SW_QUEUE_LEN               0xFF020170
5482  #define OID_SKGE_TX_SW_QUEUE_MAX               0xFF020171
5483  #define OID_SKGE_TX_RETRY                              0xFF020172
5484 @@ -352,6 +350,7 @@
5485  #define OID_SKGE_VCT_GET                               0xFF020200
5486  #define OID_SKGE_VCT_SET                               0xFF020201
5487  #define OID_SKGE_VCT_STATUS                            0xFF020202
5488 +#define OID_SKGE_VCT_CAPABILITIES              0xFF020203
5489
5490  #ifdef SK_DIAG_SUPPORT
5491  /* Defines for driver DIAG mode. */
5492 @@ -367,22 +366,79 @@
5493  #define OID_SKGE_PHY_TYPE                              0xFF020215
5494  #define OID_SKGE_PHY_LP_MODE                   0xFF020216
5495
5496 +/*
5497 + * Added for new DualNet IM driver V2
5498 + * these OIDs should later  be in pnmi.h
5499 + */
5500 +#define OID_SKGE_MAC_COUNT             0xFF020217
5501 +#define OID_SKGE_DUALNET_MODE          0xFF020218
5502 +#define OID_SKGE_SET_TAGHEADER 0xFF020219
5503 +
5504 +#ifdef SK_ASF
5505 +/* Defines for ASF */
5506 +#define OID_SKGE_ASF                    0xFF02021a
5507 +#define OID_SKGE_ASF_STORE_CONFIG       0xFF02021b
5508 +#define OID_SKGE_ASF_ENA                0xFF02021c
5509 +#define OID_SKGE_ASF_RETRANS            0xFF02021d
5510 +#define OID_SKGE_ASF_RETRANS_INT        0xFF02021e
5511 +#define OID_SKGE_ASF_HB_ENA             0xFF02021f
5512 +#define OID_SKGE_ASF_HB_INT             0xFF020220
5513 +#define OID_SKGE_ASF_WD_ENA             0xFF020221
5514 +#define OID_SKGE_ASF_WD_TIME            0xFF020222
5515 +#define OID_SKGE_ASF_IP_SOURCE          0xFF020223
5516 +#define OID_SKGE_ASF_MAC_SOURCE                        0xFF020224
5517 +#define OID_SKGE_ASF_IP_DEST            0xFF020225
5518 +#define OID_SKGE_ASF_MAC_DEST           0xFF020226
5519 +#define OID_SKGE_ASF_COMMUNITY_NAME     0xFF020227
5520 +#define OID_SKGE_ASF_RSP_ENA            0xFF020228
5521 +#define OID_SKGE_ASF_RETRANS_COUNT_MIN 0xFF020229
5522 +#define OID_SKGE_ASF_RETRANS_COUNT_MAX 0xFF02022a
5523 +#define OID_SKGE_ASF_RETRANS_INT_MIN   0xFF02022b
5524 +#define OID_SKGE_ASF_RETRANS_INT_MAX   0xFF02022c
5525 +#define OID_SKGE_ASF_HB_INT_MIN                        0xFF02022d
5526 +#define OID_SKGE_ASF_HB_INT_MAX                        0xFF02022e
5527 +#define OID_SKGE_ASF_WD_TIME_MIN               0xFF02022f
5528 +#define OID_SKGE_ASF_WD_TIME_MAX               0xFF020230
5529 +#define OID_SKGE_ASF_HB_CAP                            0xFF020231
5530 +#define OID_SKGE_ASF_WD_TIMER_RES              0xFF020232
5531 +#define OID_SKGE_ASF_GUID                              0xFF020233
5532 +#define OID_SKGE_ASF_KEY_OP                            0xFF020234
5533 +#define OID_SKGE_ASF_KEY_ADM                   0xFF020235
5534 +#define OID_SKGE_ASF_KEY_GEN                   0xFF020236
5535 +#define OID_SKGE_ASF_CAP                               0xFF020237
5536 +#define OID_SKGE_ASF_PAR_1                             0xFF020238
5537 +#define OID_SKGE_ASF_OVERALL_OID        0xFF020239
5538 +#endif /* SK_ASF */
5539 +
5540 +
5541 +// Defined for yukon2 path only
5542 +#define OID_SKGE_UPPER_MINIPORT                0xFF02023D
5543 +
5544 +
5545 +#ifdef SK_ASF
5546 +/* Defines for ASF */
5547 +#define OID_SKGE_ASF_FWVER_OID          0xFF020240
5548 +#define OID_SKGE_ASF_ACPI_OID           0xFF020241
5549 +#define OID_SKGE_ASF_SMBUS_OID          0xFF020242
5550 +#endif /* SK_ASF */
5551 +
5552 +
5553  /* VCT struct to store a backup copy of VCT data after a port reset. */
5554  typedef struct s_PnmiVct {
5555         SK_U8                   VctStatus;
5556 -       SK_U8                   PCableLen;
5557 -       SK_U32                  PMdiPairLen[4];
5558 -       SK_U8                   PMdiPairSts[4];
5559 +       SK_U8                   CableLen;
5560 +       SK_U32                  MdiPairLen[4];
5561 +       SK_U8                   MdiPairSts[4];
5562  } SK_PNMI_VCT;
5563
5564
5565  /* VCT status values (to be given to CPA via OID_SKGE_VCT_STATUS). */
5566 -#define SK_PNMI_VCT_NONE               0
5567 -#define SK_PNMI_VCT_OLD_VCT_DATA       1
5568 -#define SK_PNMI_VCT_NEW_VCT_DATA       2
5569 -#define SK_PNMI_VCT_OLD_DSP_DATA       4
5570 -#define SK_PNMI_VCT_NEW_DSP_DATA       8
5571 -#define SK_PNMI_VCT_RUNNING            16
5572 +#define SK_PNMI_VCT_NONE                       0x00
5573 +#define SK_PNMI_VCT_OLD_VCT_DATA       0x01
5574 +#define SK_PNMI_VCT_NEW_VCT_DATA       0x02
5575 +#define SK_PNMI_VCT_OLD_DSP_DATA       0x04
5576 +#define SK_PNMI_VCT_NEW_DSP_DATA       0x08
5577 +#define SK_PNMI_VCT_RUNNING                    0x10
5578
5579
5580  /* VCT cable test status. */
5581 @@ -390,7 +446,12 @@
5582  #define SK_PNMI_VCT_SHORT_CABLE                        1
5583  #define SK_PNMI_VCT_OPEN_CABLE                 2
5584  #define SK_PNMI_VCT_TEST_FAIL                  3
5585 -#define SK_PNMI_VCT_IMPEDANCE_MISMATCH         4
5586 +#define SK_PNMI_VCT_IMPEDANCE_MISMATCH 4
5587 +#define SK_PNMI_VCT_NOT_PRESENT                        5
5588 +
5589 +/* VCT capabilities (needed for OID_SKGE_VCT_CAPABILITIES. */
5590 +#define SK_PNMI_VCT_SUPPORTED                  1
5591 +#define SK_PNMI_VCT_NOT_SUPPORTED              0
5592
5593  #define        OID_SKGE_TRAP_SEN_WAR_LOW               500
5594  #define OID_SKGE_TRAP_SEN_WAR_UPP              501
5595 @@ -419,7 +480,6 @@
5596  #define        SK_SET_FULL_MIB                 5
5597  #define        SK_PRESET_FULL_MIB              6
5598
5599 -
5600  /*
5601   * Define error numbers and messages for syslog
5602   */
5603 @@ -452,7 +512,7 @@
5604  #define SK_PNMI_ERR014         (SK_ERRBASE_PNMI + 14)
5605  #define SK_PNMI_ERR014MSG      "Vpd: Cannot read VPD keys"
5606  #define SK_PNMI_ERR015         (SK_ERRBASE_PNMI + 15)
5607 -#define SK_PNMI_ERR015MSG      "Vpd: Internal array for VPD keys to small"
5608 +#define SK_PNMI_ERR015MSG      "Vpd: Internal array for VPD keys too small"
5609  #define SK_PNMI_ERR016         (SK_ERRBASE_PNMI + 16)
5610  #define SK_PNMI_ERR016MSG      "Vpd: Key string too long"
5611  #define SK_PNMI_ERR017         (SK_ERRBASE_PNMI + 17)
5612 @@ -494,9 +554,9 @@
5613  #define SK_PNMI_ERR036         (SK_ERRBASE_PNMI + 36)
5614  #define SK_PNMI_ERR036MSG      ""
5615  #define SK_PNMI_ERR037         (SK_ERRBASE_PNMI + 37)
5616 -#define SK_PNMI_ERR037MSG      "Rlmt: SK_RLMT_MODE_CHANGE event return not 0"
5617 +#define SK_PNMI_ERR037MSG      "Rlmt: SK_RLMT_MODE_CHANGE event returned not 0"
5618  #define SK_PNMI_ERR038         (SK_ERRBASE_PNMI + 38)
5619 -#define SK_PNMI_ERR038MSG      "Rlmt: SK_RLMT_PREFPORT_CHANGE event return not 0"
5620 +#define SK_PNMI_ERR038MSG      "Rlmt: SK_RLMT_PREFPORT_CHANGE event returned not 0"
5621  #define SK_PNMI_ERR039         (SK_ERRBASE_PNMI + 39)
5622  #define SK_PNMI_ERR039MSG      "RlmtStat: Unknown OID"
5623  #define SK_PNMI_ERR040         (SK_ERRBASE_PNMI + 40)
5624 @@ -514,9 +574,9 @@
5625  #define SK_PNMI_ERR046         (SK_ERRBASE_PNMI + 46)
5626  #define SK_PNMI_ERR046MSG      "Monitor: Unknown OID"
5627  #define SK_PNMI_ERR047         (SK_ERRBASE_PNMI + 47)
5628 -#define SK_PNMI_ERR047MSG      "SirqUpdate: Event function returns not 0"
5629 +#define SK_PNMI_ERR047MSG      "SirqUpdate: Event function returned not 0"
5630  #define SK_PNMI_ERR048         (SK_ERRBASE_PNMI + 48)
5631 -#define SK_PNMI_ERR048MSG      "RlmtUpdate: Event function returns not 0"
5632 +#define SK_PNMI_ERR048MSG      "RlmtUpdate: Event function returned not 0"
5633  #define SK_PNMI_ERR049         (SK_ERRBASE_PNMI + 49)
5634  #define SK_PNMI_ERR049MSG      "SkPnmiInit: Invalid size of 'CounterOffset' struct!!"
5635  #define SK_PNMI_ERR050         (SK_ERRBASE_PNMI + 50)
5636 @@ -826,23 +886,25 @@
5637  } SK_PNMI_STRUCT_DATA;
5638
5639  #define SK_PNMI_STRUCT_SIZE    (sizeof(SK_PNMI_STRUCT_DATA))
5640 +
5641 +/* The ReturnStatus field must be located before VpdFreeBytes! */
5642  #define SK_PNMI_MIN_STRUCT_SIZE        ((unsigned int)(SK_UPTR)\
5643                                  &(((SK_PNMI_STRUCT_DATA *)0)->VpdFreeBytes))
5644 -                                                                                                               /*
5645 -                                                                                                                * ReturnStatus field
5646 -                                                                                                                * must be located
5647 -                                                                                                                * before VpdFreeBytes
5648 -                                                                                                                */
5649
5650  /*
5651   * Various definitions
5652   */
5653 +#define SK_PNMI_EVT_TIMER_CHECK                28125000L       /* 28125 ms */
5654 +
5655 +#define SK_PNMI_VCT_TIMER_CHECK                 4000000L       /* 4 sec. */
5656 +
5657  #define SK_PNMI_MAX_PROTOS             3
5658
5659 -#define SK_PNMI_CNT_NO                 66      /* Must have the value of the enum
5660 -                                                                        * SK_PNMI_MAX_IDX. Define SK_PNMI_CHECK
5661 -                                                                        * for check while init phase 1
5662 -                                                                        */
5663 +/*
5664 + * SK_PNMI_CNT_NO must have the value of the enum SK_PNMI_MAX_IDX.
5665 + * Define SK_PNMI_CHECK to check this during init level SK_INIT_IO.
5666 + */
5667 +#define SK_PNMI_CNT_NO                 66
5668
5669  /*
5670   * Estimate data structure
5671 @@ -856,14 +918,6 @@
5672
5673
5674  /*
5675 - * VCT timer data structure
5676 - */
5677 -typedef struct s_VctTimer {
5678 -       SK_TIMER                VctTimer;
5679 -} SK_PNMI_VCT_TIMER;
5680 -
5681 -
5682 -/*
5683   * PNMI specific adapter context structure
5684   */
5685  typedef struct s_PnmiPort {
5686 @@ -933,12 +987,13 @@
5687         unsigned int    TrapQueueEnd;
5688         unsigned int    TrapBufPad;
5689         unsigned int    TrapUnique;
5690 -       SK_U8           VctStatus[SK_MAX_MACS];
5691 -       SK_PNMI_VCT     VctBackup[SK_MAX_MACS];
5692 -       SK_PNMI_VCT_TIMER VctTimeout[SK_MAX_MACS];
5693 +       SK_U8                   VctStatus[SK_MAX_MACS];
5694 +       SK_PNMI_VCT             VctBackup[SK_MAX_MACS];
5695 +       SK_TIMER                VctTimeout[SK_MAX_MACS];
5696  #ifdef SK_DIAG_SUPPORT
5697         SK_U32                  DiagAttached;
5698  #endif /* SK_DIAG_SUPPORT */
5699 +       SK_BOOL         VpdKeyReadError;
5700  } SK_PNMI;
5701
5702
5703 @@ -946,6 +1001,10 @@
5704   * Function prototypes
5705   */
5706  extern int SkPnmiInit(SK_AC *pAC, SK_IOC IoC, int Level);
5707 +extern int SkPnmiGetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void* pBuf,
5708 +       unsigned int* pLen, SK_U32 Instance, SK_U32 NetIndex);
5709 +extern int SkPnmiPreSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id,
5710 +       void* pBuf, unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex);
5711  extern int SkPnmiSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void* pBuf,
5712         unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex);
5713  extern int SkPnmiGetStruct(SK_AC *pAC, SK_IOC IoC, void* pBuf,
5714 diff -ruN linux/drivers/net/sk98lin/h/skgesirq.h linux-new/drivers/net/sk98lin/h/skgesirq.h
5715 --- linux/drivers/net/sk98lin/h/skgesirq.h      2006-09-20 05:42:06.000000000 +0200
5716 +++ linux-new/drivers/net/sk98lin/h/skgesirq.h  2006-07-28 14:13:54.000000000 +0200
5717 @@ -2,23 +2,24 @@
5718   *
5719   * Name:       skgesirq.h
5720   * Project:    Gigabit Ethernet Adapters, Common Modules
5721 - * Version:    $Revision$
5722 - * Date:       $Date$
5723 - * Purpose:    SK specific Gigabit Ethernet special IRQ functions
5724 + * Version:    $Revision$
5725 + * Date:       $Date$
5726 + * Purpose:    Gigabit Ethernet special IRQ functions
5727   *
5728   ******************************************************************************/
5729
5730  /******************************************************************************
5731   *
5732 + *     LICENSE:
5733   *     (C)Copyright 1998-2002 SysKonnect.
5734 - *     (C)Copyright 2002-2003 Marvell.
5735 + *     (C)Copyright 2002-2005 Marvell.
5736   *
5737   *     This program is free software; you can redistribute it and/or modify
5738   *     it under the terms of the GNU General Public License as published by
5739   *     the Free Software Foundation; either version 2 of the License, or
5740   *     (at your option) any later version.
5741 - *
5742   *     The information in this file is provided "AS IS" without warranty.
5743 + *     /LICENSE
5744   *
5745   ******************************************************************************/
5746
5747 @@ -26,9 +27,9 @@
5748  #define _INC_SKGESIRQ_H_
5749
5750  /* Define return codes of SkGePortCheckUp and CheckShort */
5751 -#define        SK_HW_PS_NONE           0       /* No action needed */
5752 -#define        SK_HW_PS_RESTART        1       /* Restart needed */
5753 -#define        SK_HW_PS_LINK           2       /* Link Up actions needed */
5754 +#define SK_HW_PS_NONE          0       /* No action needed */
5755 +#define SK_HW_PS_RESTART       1       /* Restart needed */
5756 +#define SK_HW_PS_LINK          2       /* Link Up actions needed */
5757
5758  /*
5759   * Define the Event the special IRQ/INI module can handle
5760 @@ -44,10 +45,10 @@
5761  #define SK_HWEV_SET_SPEED              9       /* Set Link Speed by PNMI */
5762  #define SK_HWEV_HALFDUP_CHK            10      /* Half Duplex Hangup Workaround */
5763
5764 -#define SK_WA_ACT_TIME         (5000000UL)     /* 5 sec */
5765 -#define SK_WA_INA_TIME         (100000UL)      /* 100 msec */
5766 +#define SK_WA_ACT_TIME         1000000UL       /* 1000 msec (1 sec) */
5767 +#define SK_WA_INA_TIME          100000UL       /*  100 msec */
5768
5769 -#define SK_HALFDUP_CHK_TIME    (10000UL)       /* 10 msec */
5770 +#define SK_HALFDUP_CHK_TIME      10000UL       /*   10 msec */
5771
5772  /*
5773   * Define the error numbers and messages
5774 @@ -75,9 +76,9 @@
5775  #define SKERR_SIRQ_E011                (SKERR_SIRQ_E010+1)
5776  #define SKERR_SIRQ_E011MSG     "CHECK failure XA2"
5777  #define SKERR_SIRQ_E012                (SKERR_SIRQ_E011+1)
5778 -#define SKERR_SIRQ_E012MSG     "unexpected IRQ Master error"
5779 +#define SKERR_SIRQ_E012MSG     "Unexpected IRQ Master error"
5780  #define SKERR_SIRQ_E013                (SKERR_SIRQ_E012+1)
5781 -#define SKERR_SIRQ_E013MSG     "unexpected IRQ Status error"
5782 +#define SKERR_SIRQ_E013MSG     "Unexpected IRQ Status error"
5783  #define SKERR_SIRQ_E014                (SKERR_SIRQ_E013+1)
5784  #define SKERR_SIRQ_E014MSG     "Parity error on RAM (read)"
5785  #define SKERR_SIRQ_E015                (SKERR_SIRQ_E014+1)
5786 @@ -102,9 +103,35 @@
5787  #define SKERR_SIRQ_E024MSG     "FIFO overflow error"
5788  #define SKERR_SIRQ_E025                (SKERR_SIRQ_E024+1)
5789  #define SKERR_SIRQ_E025MSG     "2 Pair Downshift detected"
5790 +#define SKERR_SIRQ_E026                (SKERR_SIRQ_E025+1)
5791 +#define SKERR_SIRQ_E026MSG     "Uncorrectable PCI Express error"
5792 +#define SKERR_SIRQ_E027                (SKERR_SIRQ_E026+1)
5793 +#define SKERR_SIRQ_E027MSG     "PCI Bus Abort detected"
5794 +#define SKERR_SIRQ_E028                (SKERR_SIRQ_E027+1)
5795 +#define SKERR_SIRQ_E028MSG     "Parity error on RAM 1 (read)"
5796 +#define SKERR_SIRQ_E029                (SKERR_SIRQ_E028+1)
5797 +#define SKERR_SIRQ_E029MSG     "Parity error on RAM 1 (write)"
5798 +#define SKERR_SIRQ_E030                (SKERR_SIRQ_E029+1)
5799 +#define SKERR_SIRQ_E030MSG     "Parity error on RAM 2 (read)"
5800 +#define SKERR_SIRQ_E031                (SKERR_SIRQ_E030+1)
5801 +#define SKERR_SIRQ_E031MSG     "Parity error on RAM 2 (write)"
5802 +#define SKERR_SIRQ_E032                (SKERR_SIRQ_E031+1)
5803 +#define SKERR_SIRQ_E032MSG     "TCP segmentation error async. queue 1"
5804 +#define SKERR_SIRQ_E033                (SKERR_SIRQ_E032+1)
5805 +#define SKERR_SIRQ_E033MSG     "TCP segmentation error sync. queue 1"
5806 +#define SKERR_SIRQ_E034                (SKERR_SIRQ_E033+1)
5807 +#define SKERR_SIRQ_E034MSG     "TCP segmentation error async. queue 2"
5808 +#define SKERR_SIRQ_E035                (SKERR_SIRQ_E034+1)
5809 +#define SKERR_SIRQ_E035MSG     "TCP segmentation error sync. queue 2"
5810 +#define SKERR_SIRQ_E036                (SKERR_SIRQ_E035+1)
5811 +#define SKERR_SIRQ_E036MSG     "CHECK failure polling unit"
5812
5813  extern void SkGeSirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus);
5814  extern int  SkGeSirqEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Para);
5815 +extern void SkHWLinkUp(SK_AC *pAC, SK_IOC IoC, int Port);
5816  extern void SkHWLinkDown(SK_AC *pAC, SK_IOC IoC, int Port);
5817 +extern void SkGeYuSirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus);
5818 +extern void SkYuk2SirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus);
5819
5820  #endif /* _INC_SKGESIRQ_H_ */
5821 +
5822 diff -ruN linux/drivers/net/sk98lin/h/skgetwsi.h linux-new/drivers/net/sk98lin/h/skgetwsi.h
5823 --- linux/drivers/net/sk98lin/h/skgetwsi.h      1970-01-01 01:00:00.000000000 +0100
5824 +++ linux-new/drivers/net/sk98lin/h/skgetwsi.h  2006-07-28 14:13:54.000000000 +0200
5825 @@ -0,0 +1,243 @@
5826 +/******************************************************************************
5827 + *
5828 + * Name:       skgetwsi.h
5829 + * Project:    Gigabit Ethernet Adapters, TWSI-Module
5830 + * Version:    $Revision$
5831 + * Date:       $Date$
5832 + * Purpose:    Special defines for TWSI
5833 + *
5834 + ******************************************************************************/
5835 +
5836 +/******************************************************************************
5837 + *
5838 + *     LICENSE:
5839 + *     (C)Copyright 1998-2002 SysKonnect.
5840 + *     (C)Copyright 2002-2004 Marvell.
5841 + *
5842 + *     This program is free software; you can redistribute it and/or modify
5843 + *     it under the terms of the GNU General Public License as published by
5844 + *     the Free Software Foundation; either version 2 of the License, or
5845 + *     (at your option) any later version.
5846 + *     The information in this file is provided "AS IS" without warranty.
5847 + *     /LICENSE
5848 + *
5849 + ******************************************************************************/
5850 +
5851 +/*
5852 + * SKGETWSI.H  contains all SK-98xx specific defines for the TWSI handling
5853 + */
5854 +
5855 +#ifndef _INC_SKGETWSI_H_
5856 +#define _INC_SKGETWSI_H_
5857 +
5858 +/*
5859 + * Macros to access the B2_I2C_CTRL
5860 + */
5861 +#define SK_I2C_CTL(IoC, flag, dev, dev_size, reg, burst) \
5862 +       SK_OUT32(IoC, B2_I2C_CTRL,\
5863 +               (flag ? 0x80000000UL : 0x0L) | \
5864 +               (((SK_U32)reg << 16) & I2C_ADDR) | \
5865 +               (((SK_U32)dev << 9) & I2C_DEV_SEL) | \
5866 +               (dev_size & I2C_DEV_SIZE) | \
5867 +               ((burst << 4) & I2C_BURST_LEN))
5868 +
5869 +#define SK_I2C_STOP(IoC) {                     \
5870 +       SK_U32  I2cCtrl;                                \
5871 +       SK_IN32(IoC, B2_I2C_CTRL, &I2cCtrl);            \
5872 +       SK_OUT32(IoC, B2_I2C_CTRL, I2cCtrl | I2C_STOP); \
5873 +}
5874 +
5875 +#define SK_I2C_GET_CTL(IoC, pI2cCtrl)  SK_IN32(IoC, B2_I2C_CTRL, pI2cCtrl)
5876 +
5877 +/*
5878 + * Macros to access the TWSI SW Registers
5879 + */
5880 +#define SK_I2C_SET_BIT(IoC, SetBits) {                 \
5881 +       SK_U8   OrgBits;                                \
5882 +       SK_IN8(IoC, B2_I2C_SW, &OrgBits);               \
5883 +       SK_OUT8(IoC, B2_I2C_SW, OrgBits | (SK_U8)(SetBits));    \
5884 +}
5885 +
5886 +#define SK_I2C_CLR_BIT(IoC, ClrBits) {                 \
5887 +       SK_U8   OrgBits;                                \
5888 +       SK_IN8(IoC, B2_I2C_SW, &OrgBits);               \
5889 +       SK_OUT8(IoC, B2_I2C_SW, OrgBits & ~((SK_U8)(ClrBits))); \
5890 +}
5891 +
5892 +#define SK_I2C_GET_SW(IoC, pI2cSw)     SK_IN8(IoC, B2_I2C_SW, pI2cSw)
5893 +
5894 +/*
5895 + * define the possible sensor states
5896 + */
5897 +#define SK_SEN_IDLE            0       /* Idle: sensor not read */
5898 +#define SK_SEN_VALUE   1       /* Value Read cycle */
5899 +#define SK_SEN_VALEXT  2       /* Extended Value Read cycle */
5900 +
5901 +/*
5902 + * Conversion factor to convert read Voltage sensor to milli Volt
5903 + * Conversion factor to convert read Temperature sensor to 10th degree Celsius
5904 + */
5905 +#define SK_LM80_VT_LSB         22      /* 22mV LSB resolution */
5906 +#define SK_LM80_TEMP_LSB       10      /* 1 degree LSB resolution */
5907 +#define SK_LM80_TEMPEXT_LSB     5      /* 0.5 degree LSB resolution for ext. val. */
5908 +
5909 +/*
5910 + * formula: counter = (22500*60)/(rpm * divisor * pulses/2)
5911 + * assuming: 6500rpm, 4 pulses, divisor 1
5912 + */
5913 +#define SK_LM80_FAN_FAKTOR     ((22500L*60)/(1*2))
5914 +
5915 +/*
5916 + * Define sensor management data
5917 + * Maximum is reached on Genesis copper dual port and Yukon-64
5918 + * Board specific maximum is in pAC->I2c.MaxSens
5919 + */
5920 +#define SK_MAX_SENSORS 8       /* maximal no. of installed sensors */
5921 +#define SK_MIN_SENSORS 5       /* minimal no. of installed sensors */
5922 +
5923 +/*
5924 + * To watch the state machine (SM) use the timer in two ways
5925 + * instead of one as hitherto
5926 + */
5927 +#define SK_TIMER_WATCH_SM              0       /* Watch the SM to finish in a spec. time */
5928 +#define SK_TIMER_NEW_GAUGING   1       /* Start a new gauging when timer expires */
5929 +
5930 +/*
5931 + * Defines for the individual thresholds
5932 + */
5933 +
5934 +#define C_PLUS_20              120 / 100
5935 +#define C_PLUS_15              115 / 100
5936 +#define C_PLUS_10              110 / 100
5937 +#define C_PLUS_5               105 / 100
5938 +#define C_MINUS_5               95 / 100
5939 +#define C_MINUS_10              90 / 100
5940 +#define C_MINUS_15              85 / 100
5941 +
5942 +/* Temperature sensor */
5943 +#define SK_SEN_TEMP_HIGH_ERR   800     /* Temperature High Err  Threshold */
5944 +#define SK_SEN_TEMP_HIGH_WARN  700     /* Temperature High Warn Threshold */
5945 +#define SK_SEN_TEMP_LOW_WARN   100     /* Temperature Low  Warn Threshold */
5946 +#define SK_SEN_TEMP_LOW_ERR              0     /* Temperature Low  Err  Threshold */
5947 +
5948 +/* VCC which should be 5 V */
5949 +#define SK_SEN_PCI_5V_HIGH_ERR         5588    /* Voltage PCI High Err  Threshold */
5950 +#define SK_SEN_PCI_5V_HIGH_WARN                5346    /* Voltage PCI High Warn Threshold */
5951 +#define SK_SEN_PCI_5V_LOW_WARN         4664    /* Voltage PCI Low  Warn Threshold */
5952 +#define SK_SEN_PCI_5V_LOW_ERR          4422    /* Voltage PCI Low  Err  Threshold */
5953 +
5954 +/*
5955 + * VIO may be 5 V or 3.3 V. Initialization takes two parts:
5956 + * 1. Initialize lowest lower limit and highest higher limit.
5957 + * 2. After the first value is read correct the upper or the lower limit to
5958 + *    the appropriate C constant.
5959 + *
5960 + * Warning limits are +-5% of the exepected voltage.
5961 + * Error limits are +-10% of the expected voltage.
5962 + */
5963 +
5964 +/* Bug fix AF: 16.Aug.2001: Correct the init base of LM80 sensor */
5965 +
5966 +#define SK_SEN_PCI_IO_5V_HIGH_ERR      5566    /* + 10% V PCI-IO High Err Threshold */
5967 +#define SK_SEN_PCI_IO_5V_HIGH_WARN     5324    /* +  5% V PCI-IO High Warn Threshold */
5968 +                                       /*              5000    mVolt */
5969 +#define SK_SEN_PCI_IO_5V_LOW_WARN      4686    /* -  5% V PCI-IO Low Warn Threshold */
5970 +#define SK_SEN_PCI_IO_5V_LOW_ERR       4444    /* - 10% V PCI-IO Low Err Threshold */
5971 +
5972 +#define SK_SEN_PCI_IO_RANGE_LIMITER    4000    /* 4000 mV range delimiter */
5973 +
5974 +/* correction values for the second pass */
5975 +#define SK_SEN_PCI_IO_3V3_HIGH_ERR     3850    /* + 15% V PCI-IO High Err Threshold */
5976 +#define SK_SEN_PCI_IO_3V3_HIGH_WARN    3674    /* + 10% V PCI-IO High Warn Threshold */
5977 +                                       /*              3300    mVolt */
5978 +#define SK_SEN_PCI_IO_3V3_LOW_WARN     2926    /* - 10% V PCI-IO Low Warn Threshold */
5979 +#define SK_SEN_PCI_IO_3V3_LOW_ERR      2772    /* - 15% V PCI-IO Low Err  Threshold */
5980 +
5981 +/*
5982 + * VDD voltage
5983 + */
5984 +#define SK_SEN_VDD_HIGH_ERR            3630    /* Voltage ASIC High Err  Threshold */
5985 +#define SK_SEN_VDD_HIGH_WARN   3476    /* Voltage ASIC High Warn Threshold */
5986 +#define SK_SEN_VDD_LOW_WARN            3146    /* Voltage ASIC Low  Warn Threshold */
5987 +#define SK_SEN_VDD_LOW_ERR             2970    /* Voltage ASIC Low  Err  Threshold */
5988 +
5989 +/*
5990 + * PHY PLL 3V3 voltage
5991 + */
5992 +#define SK_SEN_PLL_3V3_HIGH_ERR                3630    /* Voltage PMA High Err  Threshold */
5993 +#define SK_SEN_PLL_3V3_HIGH_WARN       3476    /* Voltage PMA High Warn Threshold */
5994 +#define SK_SEN_PLL_3V3_LOW_WARN                3146    /* Voltage PMA Low  Warn Threshold */
5995 +#define SK_SEN_PLL_3V3_LOW_ERR         2970    /* Voltage PMA Low  Err  Threshold */
5996 +
5997 +/*
5998 + * VAUX (YUKON only)
5999 + */
6000 +#define SK_SEN_VAUX_3V3_VAL            3300    /* Voltage VAUX 3.3 Volt */
6001 +
6002 +#define SK_SEN_VAUX_3V3_HIGH_ERR       (SK_I32)(SK_SEN_VAUX_3V3_VAL * C_PLUS_10)
6003 +#define SK_SEN_VAUX_3V3_HIGH_WARN      (SK_I32)(SK_SEN_VAUX_3V3_VAL * C_PLUS_5)
6004 +#define SK_SEN_VAUX_3V3_LOW_WARN       (SK_I32)(SK_SEN_VAUX_3V3_VAL * C_MINUS_5)
6005 +#define SK_SEN_VAUX_3V3_LOW_ERR                (SK_I32)(SK_SEN_VAUX_3V3_VAL * C_MINUS_10)
6006 +
6007 +#define SK_SEN_VAUX_RANGE_LIMITER      1000    /* 1000 mV range delimiter */
6008 +
6009 +/*
6010 + * PHY 2V5 voltage
6011 + */
6012 +#define SK_SEN_PHY_2V5_VAL             2500    /* Voltage PHY 2.5 Volt */
6013 +
6014 +#define SK_SEN_PHY_2V5_HIGH_ERR                (SK_I32)(SK_SEN_PHY_2V5_VAL * C_PLUS_10)
6015 +#define SK_SEN_PHY_2V5_HIGH_WARN       (SK_I32)(SK_SEN_PHY_2V5_VAL * C_PLUS_5)
6016 +#define SK_SEN_PHY_2V5_LOW_WARN                (SK_I32)(SK_SEN_PHY_2V5_VAL * C_MINUS_5)
6017 +#define SK_SEN_PHY_2V5_LOW_ERR         (SK_I32)(SK_SEN_PHY_2V5_VAL * C_MINUS_10)
6018 +
6019 +/*
6020 + * ASIC Core 1V5 voltage (YUKON only)
6021 + */
6022 +#define SK_SEN_CORE_1V5_VAL            1500    /* Voltage ASIC Core 1.5 Volt */
6023 +
6024 +#define SK_SEN_CORE_1V5_HIGH_ERR       (SK_I32)(SK_SEN_CORE_1V5_VAL * C_PLUS_10)
6025 +#define SK_SEN_CORE_1V5_HIGH_WARN      (SK_I32)(SK_SEN_CORE_1V5_VAL * C_PLUS_5)
6026 +#define SK_SEN_CORE_1V5_LOW_WARN       (SK_I32)(SK_SEN_CORE_1V5_VAL * C_MINUS_5)
6027 +#define SK_SEN_CORE_1V5_LOW_ERR        (SK_I32)(SK_SEN_CORE_1V5_VAL * C_MINUS_10)
6028 +
6029 +/*
6030 + * ASIC Core 1V2 (1V3) voltage (YUKON-2 only)
6031 + */
6032 +#define SK_SEN_CORE_1V2_VAL            1200    /* Voltage ASIC Core 1.2 Volt */
6033 +
6034 +#define SK_SEN_CORE_1V2_HIGH_ERR       (SK_I32)(SK_SEN_CORE_1V2_VAL * C_PLUS_20)
6035 +#define SK_SEN_CORE_1V2_HIGH_WARN      (SK_I32)(SK_SEN_CORE_1V2_VAL * C_PLUS_15)
6036 +#define SK_SEN_CORE_1V2_LOW_WARN       (SK_I32)(SK_SEN_CORE_1V2_VAL * C_MINUS_5)
6037 +#define SK_SEN_CORE_1V2_LOW_ERR        (SK_I32)(SK_SEN_CORE_1V2_VAL * C_MINUS_10)
6038 +
6039 +#define SK_SEN_CORE_1V3_VAL            1300    /* Voltage ASIC Core 1.3 Volt */
6040 +
6041 +#define SK_SEN_CORE_1V3_HIGH_ERR       (SK_I32)(SK_SEN_CORE_1V3_VAL * C_PLUS_15)
6042 +#define SK_SEN_CORE_1V3_HIGH_WARN      (SK_I32)(SK_SEN_CORE_1V3_VAL * C_PLUS_10)
6043 +#define SK_SEN_CORE_1V3_LOW_WARN       (SK_I32)(SK_SEN_CORE_1V3_VAL * C_MINUS_5)
6044 +#define SK_SEN_CORE_1V3_LOW_ERR        (SK_I32)(SK_SEN_CORE_1V3_VAL * C_MINUS_10)
6045 +
6046 +/*
6047 + * FAN 1 speed
6048 + */
6049 +/* assuming: 6500rpm +-15%, 4 pulses,
6050 + * warning at: 80 %
6051 + * error at:   70 %
6052 + * no upper limit
6053 + */
6054 +#define SK_SEN_FAN_HIGH_ERR            20000   /* FAN Speed High Err Threshold */
6055 +#define SK_SEN_FAN_HIGH_WARN   20000   /* FAN Speed High Warn Threshold */
6056 +#define SK_SEN_FAN_LOW_WARN             5200   /* FAN Speed Low Warn Threshold */
6057 +#define SK_SEN_FAN_LOW_ERR              4550   /* FAN Speed Low Err Threshold */
6058 +
6059 +/*
6060 + * Some Voltages need dynamic thresholds
6061 + */
6062 +#define SK_SEN_DYN_INIT_NONE            0  /* No dynamic init of thresholds */
6063 +#define SK_SEN_DYN_INIT_PCI_IO         10  /* Init PCI-IO with new thresholds */
6064 +#define SK_SEN_DYN_INIT_VAUX           11  /* Init VAUX with new thresholds */
6065 +
6066 +extern int SkLm80ReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen);
6067 +#endif /* n_INC_SKGETWSI_H */
6068 +
6069 diff -ruN linux/drivers/net/sk98lin/h/ski2c.h linux-new/drivers/net/sk98lin/h/ski2c.h
6070 --- linux/drivers/net/sk98lin/h/ski2c.h 2006-09-20 05:42:06.000000000 +0200
6071 +++ linux-new/drivers/net/sk98lin/h/ski2c.h     1970-01-01 01:00:00.000000000 +0100
6072 @@ -1,174 +0,0 @@
6073 -/******************************************************************************
6074 - *
6075 - * Name:       ski2c.h
6076 - * Project:    Gigabit Ethernet Adapters, TWSI-Module
6077 - * Version:    $Revision$
6078 - * Date:       $Date$
6079 - * Purpose:    Defines to access Voltage and Temperature Sensor
6080 - *
6081 - ******************************************************************************/
6082 -
6083 -/******************************************************************************
6084 - *
6085 - *     (C)Copyright 1998-2002 SysKonnect.
6086 - *     (C)Copyright 2002-2003 Marvell.
6087 - *
6088 - *     This program is free software; you can redistribute it and/or modify
6089 - *     it under the terms of the GNU General Public License as published by
6090 - *     the Free Software Foundation; either version 2 of the License, or
6091 - *     (at your option) any later version.
6092 - *
6093 - *     The information in this file is provided "AS IS" without warranty.
6094 - *
6095 - ******************************************************************************/
6096 -
6097 -/*
6098 - * SKI2C.H     contains all I2C specific defines
6099 - */
6100 -
6101 -#ifndef _SKI2C_H_
6102 -#define _SKI2C_H_
6103 -
6104 -typedef struct  s_Sensor SK_SENSOR;
6105 -
6106 -#include "h/skgei2c.h"
6107 -
6108 -/*
6109 - * Define the I2C events.
6110 - */
6111 -#define SK_I2CEV_IRQ   1       /* IRQ happened Event */
6112 -#define SK_I2CEV_TIM   2       /* Timeout event */
6113 -#define SK_I2CEV_CLEAR 3       /* Clear MIB Values */
6114 -
6115 -/*
6116 - * Define READ and WRITE Constants.
6117 - */
6118 -#define I2C_READ       0
6119 -#define I2C_WRITE      1
6120 -#define I2C_BURST      1
6121 -#define I2C_SINGLE     0
6122 -
6123 -#define SKERR_I2C_E001         (SK_ERRBASE_I2C+0)
6124 -#define SKERR_I2C_E001MSG      "Sensor index unknown"
6125 -#define SKERR_I2C_E002         (SKERR_I2C_E001+1)
6126 -#define SKERR_I2C_E002MSG      "TWSI: transfer does not complete"
6127 -#define SKERR_I2C_E003         (SKERR_I2C_E002+1)
6128 -#define SKERR_I2C_E003MSG      "LM80: NAK on device send"
6129 -#define SKERR_I2C_E004         (SKERR_I2C_E003+1)
6130 -#define SKERR_I2C_E004MSG      "LM80: NAK on register send"
6131 -#define SKERR_I2C_E005         (SKERR_I2C_E004+1)
6132 -#define SKERR_I2C_E005MSG      "LM80: NAK on device (2) send"
6133 -#define SKERR_I2C_E006         (SKERR_I2C_E005+1)
6134 -#define SKERR_I2C_E006MSG      "Unknown event"
6135 -#define SKERR_I2C_E007         (SKERR_I2C_E006+1)
6136 -#define SKERR_I2C_E007MSG      "LM80 read out of state"
6137 -#define SKERR_I2C_E008         (SKERR_I2C_E007+1)
6138 -#define SKERR_I2C_E008MSG      "Unexpected sensor read completed"
6139 -#define SKERR_I2C_E009         (SKERR_I2C_E008+1)
6140 -#define SKERR_I2C_E009MSG      "WARNING: temperature sensor out of range"
6141 -#define SKERR_I2C_E010         (SKERR_I2C_E009+1)
6142 -#define SKERR_I2C_E010MSG      "WARNING: voltage sensor out of range"
6143 -#define SKERR_I2C_E011         (SKERR_I2C_E010+1)
6144 -#define SKERR_I2C_E011MSG      "ERROR: temperature sensor out of range"
6145 -#define SKERR_I2C_E012         (SKERR_I2C_E011+1)
6146 -#define SKERR_I2C_E012MSG      "ERROR: voltage sensor out of range"
6147 -#define SKERR_I2C_E013         (SKERR_I2C_E012+1)
6148 -#define SKERR_I2C_E013MSG      "ERROR: couldn't init sensor"
6149 -#define SKERR_I2C_E014         (SKERR_I2C_E013+1)
6150 -#define SKERR_I2C_E014MSG      "WARNING: fan sensor out of range"
6151 -#define SKERR_I2C_E015         (SKERR_I2C_E014+1)
6152 -#define SKERR_I2C_E015MSG      "ERROR: fan sensor out of range"
6153 -#define SKERR_I2C_E016         (SKERR_I2C_E015+1)
6154 -#define SKERR_I2C_E016MSG      "TWSI: active transfer does not complete"
6155 -
6156 -/*
6157 - * Define Timeout values
6158 - */
6159 -#define SK_I2C_TIM_LONG                2000000L        /* 2 seconds */
6160 -#define SK_I2C_TIM_SHORT        100000L        /* 100 milliseconds */
6161 -#define SK_I2C_TIM_WATCH       1000000L        /* 1 second */
6162 -
6163 -/*
6164 - * Define trap and error log hold times
6165 - */
6166 -#ifndef        SK_SEN_ERR_TR_HOLD
6167 -#define SK_SEN_ERR_TR_HOLD             (4*SK_TICKS_PER_SEC)
6168 -#endif
6169 -#ifndef        SK_SEN_ERR_LOG_HOLD
6170 -#define SK_SEN_ERR_LOG_HOLD            (60*SK_TICKS_PER_SEC)
6171 -#endif
6172 -#ifndef        SK_SEN_WARN_TR_HOLD
6173 -#define SK_SEN_WARN_TR_HOLD            (15*SK_TICKS_PER_SEC)
6174 -#endif
6175 -#ifndef        SK_SEN_WARN_LOG_HOLD
6176 -#define SK_SEN_WARN_LOG_HOLD   (15*60*SK_TICKS_PER_SEC)
6177 -#endif
6178 -
6179 -/*
6180 - * Defines for SenType
6181 - */
6182 -#define SK_SEN_UNKNOWN 0
6183 -#define SK_SEN_TEMP            1
6184 -#define SK_SEN_VOLT            2
6185 -#define SK_SEN_FAN             3
6186 -
6187 -/*
6188 - * Define for the SenErrorFlag
6189 - */
6190 -#define SK_SEN_ERR_NOT_PRESENT 0       /* Error Flag: Sensor not present */
6191 -#define SK_SEN_ERR_OK                  1       /* Error Flag: O.K. */
6192 -#define SK_SEN_ERR_WARN                        2       /* Error Flag: Warning */
6193 -#define SK_SEN_ERR_ERR                 3       /* Error Flag: Error */
6194 -#define SK_SEN_ERR_FAULTY              4       /* Error Flag: Faulty */
6195 -
6196 -/*
6197 - * Define the Sensor struct
6198 - */
6199 -struct s_Sensor {
6200 -       char    *SenDesc;                       /* Description */
6201 -       int             SenType;                        /* Voltage or Temperature */
6202 -       SK_I32  SenValue;                       /* Current value of the sensor */
6203 -       SK_I32  SenThreErrHigh;         /* High error Threshhold of this sensor */
6204 -       SK_I32  SenThreWarnHigh;        /* High warning Threshhold of this sensor */
6205 -       SK_I32  SenThreErrLow;          /* Lower error Threshold of the sensor */
6206 -       SK_I32  SenThreWarnLow;         /* Lower warning Threshold of the sensor */
6207 -       int             SenErrFlag;                     /* Sensor indicated an error */
6208 -       SK_BOOL SenInit;                        /* Is sensor initialized ? */
6209 -       SK_U64  SenErrCts;                      /* Error trap counter */
6210 -       SK_U64  SenWarnCts;                     /* Warning trap counter */
6211 -       SK_U64  SenBegErrTS;            /* Begin error timestamp */
6212 -       SK_U64  SenBegWarnTS;           /* Begin warning timestamp */
6213 -       SK_U64  SenLastErrTrapTS;       /* Last error trap timestamp */
6214 -       SK_U64  SenLastErrLogTS;        /* Last error log timestamp */
6215 -       SK_U64  SenLastWarnTrapTS;      /* Last warning trap timestamp */
6216 -       SK_U64  SenLastWarnLogTS;       /* Last warning log timestamp */
6217 -       int             SenState;                       /* Sensor State (see HW specific include) */
6218 -       int             (*SenRead)(SK_AC *pAC, SK_IOC IoC, struct s_Sensor *pSen);
6219 -                                                               /* Sensors read function */
6220 -       SK_U16  SenReg;                         /* Register Address for this sensor */
6221 -       SK_U8   SenDev;                         /* Device Selection for this sensor */
6222 -};
6223 -
6224 -typedef        struct  s_I2c {
6225 -       SK_SENSOR       SenTable[SK_MAX_SENSORS];       /* Sensor Table */
6226 -       int                     CurrSens;       /* Which sensor is currently queried */
6227 -       int                     MaxSens;        /* Max. number of sensors */
6228 -       int                     TimerMode;      /* Use the timer also to watch the state machine */
6229 -       int                     InitLevel;      /* Initialized Level */
6230 -#ifndef SK_DIAG
6231 -       int                     DummyReads;     /* Number of non-checked dummy reads */
6232 -       SK_TIMER        SenTimer;       /* Sensors timer */
6233 -#endif /* !SK_DIAG */
6234 -} SK_I2C;
6235 -
6236 -extern int SkI2cInit(SK_AC *pAC, SK_IOC IoC, int Level);
6237 -#ifdef SK_DIAG
6238 -extern SK_U32 SkI2cRead(SK_AC *pAC, SK_IOC IoC, int Dev, int Size, int Reg,
6239 -                                                int Burst);
6240 -#else /* !SK_DIAG */
6241 -extern int SkI2cEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Para);
6242 -extern void SkI2cWaitIrq(SK_AC *pAC, SK_IOC IoC);
6243 -extern void SkI2cIsr(SK_AC *pAC, SK_IOC IoC);
6244 -#endif /* !SK_DIAG */
6245 -#endif /* n_SKI2C_H */
6246 -
6247 diff -ruN linux/drivers/net/sk98lin/h/skqueue.h linux-new/drivers/net/sk98lin/h/skqueue.h
6248 --- linux/drivers/net/sk98lin/h/skqueue.h       2006-09-20 05:42:06.000000000 +0200
6249 +++ linux-new/drivers/net/sk98lin/h/skqueue.h   2006-07-28 14:13:54.000000000 +0200
6250 @@ -2,14 +2,15 @@
6251   *
6252   * Name:       skqueue.h
6253   * Project:    Gigabit Ethernet Adapters, Event Scheduler Module
6254 - * Version:    $Revision$
6255 - * Date:       $Date$
6256 + * Version:    $Revision$
6257 + * Date:       $Date$
6258   * Purpose:    Defines for the Event queue
6259   *
6260   ******************************************************************************/
6261
6262  /******************************************************************************
6263   *
6264 + *     LICENSE:
6265   *     (C)Copyright 1998-2002 SysKonnect GmbH.
6266   *     (C)Copyright 2002-2003 Marvell.
6267   *
6268 @@ -19,6 +20,7 @@
6269   *     (at your option) any later version.
6270   *
6271   *     The information in this file is provided "AS IS" without warranty.
6272 + *     /LICENSE
6273   *
6274   ******************************************************************************/
6275
6276 @@ -45,6 +47,9 @@
6277  #define        SKGE_RSF        11      /* RSF Aggregation Event Class */
6278  #define        SKGE_MARKER     12      /* MARKER Aggregation Event Class */
6279  #define        SKGE_FD         13      /* FD Distributor Event Class */
6280 +#ifdef SK_ASF
6281 +#define        SKGE_ASF        14      /* ASF Event Class */
6282 +#endif
6283
6284  /*
6285   * define event queue as circular buffer
6286 @@ -90,5 +95,11 @@
6287  #define        SKERR_Q_E001MSG "Event queue overflow"
6288  #define        SKERR_Q_E002    (SKERR_Q_E001+1)
6289  #define        SKERR_Q_E002MSG "Undefined event class"
6290 +#define        SKERR_Q_E003    (SKERR_Q_E001+2)
6291 +#define        SKERR_Q_E003MSG "Event queued in Init Level 0"
6292 +#define        SKERR_Q_E004    (SKERR_Q_E001+3)
6293 +#define        SKERR_Q_E004MSG "Error Reported from Event Fuction (Queue Blocked)"
6294 +#define        SKERR_Q_E005    (SKERR_Q_E001+4)
6295 +#define        SKERR_Q_E005MSG "Event scheduler called in Init Level 0 or 1"
6296  #endif /* _SKQUEUE_H_ */
6297
6298 diff -ruN linux/drivers/net/sk98lin/h/skrlmt.h linux-new/drivers/net/sk98lin/h/skrlmt.h
6299 --- linux/drivers/net/sk98lin/h/skrlmt.h        2006-09-20 05:42:06.000000000 +0200
6300 +++ linux-new/drivers/net/sk98lin/h/skrlmt.h    2006-07-28 14:13:54.000000000 +0200
6301 @@ -2,14 +2,15 @@
6302   *
6303   * Name:       skrlmt.h
6304   * Project:    GEnesis, PCI Gigabit Ethernet Adapter
6305 - * Version:    $Revision$
6306 - * Date:       $Date$
6307 + * Version:    $Revision$
6308 + * Date:       $Date$
6309   * Purpose:    Header file for Redundant Link ManagemenT.
6310   *
6311   ******************************************************************************/
6312
6313  /******************************************************************************
6314   *
6315 + *     LICENSE:
6316   *     (C)Copyright 1998-2002 SysKonnect GmbH.
6317   *     (C)Copyright 2002-2003 Marvell.
6318   *
6319 @@ -19,6 +20,7 @@
6320   *     (at your option) any later version.
6321   *
6322   *     The information in this file is provided "AS IS" without warranty.
6323 + *     /LICENSE
6324   *
6325   ******************************************************************************/
6326
6327 diff -ruN linux/drivers/net/sk98lin/h/sktimer.h linux-new/drivers/net/sk98lin/h/sktimer.h
6328 --- linux/drivers/net/sk98lin/h/sktimer.h       2006-09-20 05:42:06.000000000 +0200
6329 +++ linux-new/drivers/net/sk98lin/h/sktimer.h   2006-07-28 14:13:54.000000000 +0200
6330 @@ -2,14 +2,15 @@
6331   *
6332   * Name:       sktimer.h
6333   * Project:    Gigabit Ethernet Adapters, Event Scheduler Module
6334 - * Version:    $Revision$
6335 - * Date:       $Date$
6336 + * Version:    $Revision$
6337 + * Date:       $Date$
6338   * Purpose:    Defines for the timer functions
6339   *
6340   ******************************************************************************/
6341
6342  /******************************************************************************
6343   *
6344 + *     LICENSE:
6345   *     (C)Copyright 1998-2002 SysKonnect GmbH.
6346   *     (C)Copyright 2002-2003 Marvell.
6347   *
6348 @@ -19,6 +20,7 @@
6349   *     (at your option) any later version.
6350   *
6351   *     The information in this file is provided "AS IS" without warranty.
6352 + *     /LICENSE
6353   *
6354   ******************************************************************************/
6355
6356 diff -ruN linux/drivers/net/sk98lin/h/sktwsi.h linux-new/drivers/net/sk98lin/h/sktwsi.h
6357 --- linux/drivers/net/sk98lin/h/sktwsi.h        1970-01-01 01:00:00.000000000 +0100
6358 +++ linux-new/drivers/net/sk98lin/h/sktwsi.h    2006-07-28 14:13:54.000000000 +0200
6359 @@ -0,0 +1,179 @@
6360 +/******************************************************************************
6361 + *
6362 + * Name:       sktwsi.h
6363 + * Project:    Gigabit Ethernet Adapters, TWSI-Module
6364 + * Version:    $Revision$
6365 + * Date:       $Date$
6366 + * Purpose:    Defines to access Voltage and Temperature Sensor
6367 + *
6368 + ******************************************************************************/
6369 +
6370 +/******************************************************************************
6371 + *
6372 + *     LICENSE:
6373 + *     (C)Copyright 1998-2002 SysKonnect.
6374 + *     (C)Copyright 2002-2003 Marvell.
6375 + *
6376 + *     This program is free software; you can redistribute it and/or modify
6377 + *     it under the terms of the GNU General Public License as published by
6378 + *     the Free Software Foundation; either version 2 of the License, or
6379 + *     (at your option) any later version.
6380 + *
6381 + *     The information in this file is provided "AS IS" without warranty.
6382 + *     /LICENSE
6383 + *
6384 + ******************************************************************************/
6385 +
6386 +/*
6387 + * SKTWSI.H    contains all TWSI specific defines
6388 + */
6389 +
6390 +#ifndef _SKTWSI_H_
6391 +#define _SKTWSI_H_
6392 +
6393 +typedef struct  s_Sensor SK_SENSOR;
6394 +
6395 +#include "h/skgetwsi.h"
6396 +
6397 +/*
6398 + * Define the TWSI events.
6399 + */
6400 +#define SK_I2CEV_IRQ   1       /* IRQ happened Event */
6401 +#define SK_I2CEV_TIM   2       /* Timeout event */
6402 +#define SK_I2CEV_CLEAR 3       /* Clear MIB Values */
6403 +
6404 +/*
6405 + * Define READ and WRITE Constants.
6406 + */
6407 +#define I2C_READ       0
6408 +#define I2C_WRITE      1
6409 +#define I2C_BURST      1
6410 +#define I2C_SINGLE     0
6411 +
6412 +#define SKERR_I2C_E001         (SK_ERRBASE_I2C+0)
6413 +#define SKERR_I2C_E001MSG      "Sensor index unknown"
6414 +#define SKERR_I2C_E002         (SKERR_I2C_E001+1)
6415 +#define SKERR_I2C_E002MSG      "TWSI: transfer does not complete"
6416 +#define SKERR_I2C_E003         (SKERR_I2C_E002+1)
6417 +#define SKERR_I2C_E003MSG      "LM80: NAK on device send"
6418 +#define SKERR_I2C_E004         (SKERR_I2C_E003+1)
6419 +#define SKERR_I2C_E004MSG      "LM80: NAK on register send"
6420 +#define SKERR_I2C_E005         (SKERR_I2C_E004+1)
6421 +#define SKERR_I2C_E005MSG      "LM80: NAK on device (2) send"
6422 +#define SKERR_I2C_E006         (SKERR_I2C_E005+1)
6423 +#define SKERR_I2C_E006MSG      "Unknown event"
6424 +#define SKERR_I2C_E007         (SKERR_I2C_E006+1)
6425 +#define SKERR_I2C_E007MSG      "LM80 read out of state"
6426 +#define SKERR_I2C_E008         (SKERR_I2C_E007+1)
6427 +#define SKERR_I2C_E008MSG      "Unexpected sensor read completed"
6428 +#define SKERR_I2C_E009         (SKERR_I2C_E008+1)
6429 +#define SKERR_I2C_E009MSG      "WARNING: temperature sensor out of range"
6430 +#define SKERR_I2C_E010         (SKERR_I2C_E009+1)
6431 +#define SKERR_I2C_E010MSG      "WARNING: voltage sensor out of range"
6432 +#define SKERR_I2C_E011         (SKERR_I2C_E010+1)
6433 +#define SKERR_I2C_E011MSG      "ERROR: temperature sensor out of range"
6434 +#define SKERR_I2C_E012         (SKERR_I2C_E011+1)
6435 +#define SKERR_I2C_E012MSG      "ERROR: voltage sensor out of range"
6436 +#define SKERR_I2C_E013         (SKERR_I2C_E012+1)
6437 +#define SKERR_I2C_E013MSG      "ERROR: couldn't init sensor"
6438 +#define SKERR_I2C_E014         (SKERR_I2C_E013+1)
6439 +#define SKERR_I2C_E014MSG      "WARNING: fan sensor out of range"
6440 +#define SKERR_I2C_E015         (SKERR_I2C_E014+1)
6441 +#define SKERR_I2C_E015MSG      "ERROR: fan sensor out of range"
6442 +#define SKERR_I2C_E016         (SKERR_I2C_E015+1)
6443 +#define SKERR_I2C_E016MSG      "TWSI: active transfer does not complete"
6444 +
6445 +/*
6446 + * Define Timeout values
6447 + */
6448 +#define SK_I2C_TIM_LONG                2000000L        /* 2 seconds */
6449 +#define SK_I2C_TIM_SHORT        100000L        /* 100 milliseconds */
6450 +#define SK_I2C_TIM_WATCH       1000000L        /* 1 second */
6451 +
6452 +/*
6453 + * Define trap and error log hold times
6454 + */
6455 +#ifndef        SK_SEN_ERR_TR_HOLD
6456 +#define SK_SEN_ERR_TR_HOLD             (4*SK_TICKS_PER_SEC)
6457 +#endif
6458 +#ifndef        SK_SEN_ERR_LOG_HOLD
6459 +#define SK_SEN_ERR_LOG_HOLD            (60*SK_TICKS_PER_SEC)
6460 +#endif
6461 +#ifndef        SK_SEN_WARN_TR_HOLD
6462 +#define SK_SEN_WARN_TR_HOLD            (15*SK_TICKS_PER_SEC)
6463 +#endif
6464 +#ifndef        SK_SEN_WARN_LOG_HOLD
6465 +#define SK_SEN_WARN_LOG_HOLD   (15*60*SK_TICKS_PER_SEC)
6466 +#endif
6467 +
6468 +/*
6469 + * Defines for SenType
6470 + */
6471 +#define SK_SEN_UNKNOWN 0
6472 +#define SK_SEN_TEMP            1
6473 +#define SK_SEN_VOLT            2
6474 +#define SK_SEN_FAN             3
6475 +
6476 +/*
6477 + * Define for the SenErrorFlag
6478 + */
6479 +#define SK_SEN_ERR_NOT_PRESENT 0       /* Error Flag: Sensor not present */
6480 +#define SK_SEN_ERR_OK                  1       /* Error Flag: O.K. */
6481 +#define SK_SEN_ERR_WARN                        2       /* Error Flag: Warning */
6482 +#define SK_SEN_ERR_ERR                 3       /* Error Flag: Error */
6483 +#define SK_SEN_ERR_FAULTY              4       /* Error Flag: Faulty */
6484 +
6485 +/*
6486 + * Define the Sensor struct
6487 + */
6488 +struct s_Sensor {
6489 +       char    *SenDesc;                       /* Description */
6490 +       int             SenType;                        /* Voltage or Temperature */
6491 +       SK_I32  SenValue;                       /* Current value of the sensor */
6492 +       SK_I32  SenThreErrHigh;         /* High error Threshhold of this sensor */
6493 +       SK_I32  SenThreWarnHigh;        /* High warning Threshhold of this sensor */
6494 +       SK_I32  SenThreErrLow;          /* Lower error Threshold of the sensor */
6495 +       SK_I32  SenThreWarnLow;         /* Lower warning Threshold of the sensor */
6496 +       int             SenErrFlag;                     /* Sensor indicated an error */
6497 +       SK_BOOL SenInit;                        /* Is sensor initialized ? */
6498 +       SK_U64  SenErrCts;                      /* Error trap counter */
6499 +       SK_U64  SenWarnCts;                     /* Warning trap counter */
6500 +       SK_U64  SenBegErrTS;            /* Begin error timestamp */
6501 +       SK_U64  SenBegWarnTS;           /* Begin warning timestamp */
6502 +       SK_U64  SenLastErrTrapTS;       /* Last error trap timestamp */
6503 +       SK_U64  SenLastErrLogTS;        /* Last error log timestamp */
6504 +       SK_U64  SenLastWarnTrapTS;      /* Last warning trap timestamp */
6505 +       SK_U64  SenLastWarnLogTS;       /* Last warning log timestamp */
6506 +       int             SenState;                       /* Sensor State (see HW specific include) */
6507 +       int             (*SenRead)(SK_AC *pAC, SK_IOC IoC, struct s_Sensor *pSen);
6508 +                                                               /* Sensors read function */
6509 +       SK_U16  SenReg;                         /* Register Address for this sensor */
6510 +       SK_U8   SenDev;                         /* Device Selection for this sensor */
6511 +};
6512 +
6513 +typedef        struct  s_I2c {
6514 +       SK_SENSOR       SenTable[SK_MAX_SENSORS];       /* Sensor Table */
6515 +       int                     CurrSens;       /* Which sensor is currently queried */
6516 +       int                     MaxSens;        /* Max. number of sensors */
6517 +       int                     TimerMode;      /* Use the timer also to watch the state machine */
6518 +       int                     InitLevel;      /* Initialized Level */
6519 +#ifndef SK_DIAG
6520 +       int                     DummyReads;     /* Number of non-checked dummy reads */
6521 +       SK_TIMER        SenTimer;       /* Sensors timer */
6522 +#endif /* !SK_DIAG */
6523 +} SK_I2C;
6524 +
6525 +extern int SkI2cInit(SK_AC *pAC, SK_IOC IoC, int Level);
6526 +extern int SkI2cWrite(SK_AC *pAC, SK_IOC IoC, SK_U32 Data, int Dev, int Size,
6527 +                                          int Reg, int Burst);
6528 +extern int SkI2cReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen);
6529 +#ifdef SK_DIAG
6530 +extern SK_U32 SkI2cRead(SK_AC *pAC, SK_IOC IoC, int Dev, int Size, int Reg,
6531 +                                                int Burst);
6532 +#else /* !SK_DIAG */
6533 +extern int SkI2cEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Para);
6534 +extern void SkI2cWaitIrq(SK_AC *pAC, SK_IOC IoC);
6535 +extern void SkI2cIsr(SK_AC *pAC, SK_IOC IoC);
6536 +#endif /* !SK_DIAG */
6537 +#endif /* n_SKTWSI_H */
6538 +
6539 diff -ruN linux/drivers/net/sk98lin/h/sktypes.h linux-new/drivers/net/sk98lin/h/sktypes.h
6540 --- linux/drivers/net/sk98lin/h/sktypes.h       2006-09-20 05:42:06.000000000 +0200
6541 +++ linux-new/drivers/net/sk98lin/h/sktypes.h   2006-07-28 14:13:54.000000000 +0200
6542 @@ -2,8 +2,8 @@
6543   *
6544   * Name:       sktypes.h
6545   * Project:    GEnesis, PCI Gigabit Ethernet Adapter
6546 - * Version:    $Revision$
6547 - * Date:       $Date$
6548 + * Version:    $Revision$
6549 + * Date:       $Date$
6550   * Purpose:    Define data types for Linux
6551   *
6552   ******************************************************************************/
6553 @@ -11,7 +11,7 @@
6554  /******************************************************************************
6555   *
6556   *     (C)Copyright 1998-2002 SysKonnect GmbH.
6557 - *     (C)Copyright 2002-2003 Marvell.
6558 + *     (C)Copyright 2002-2005 Marvell.
6559   *
6560   *     This program is free software; you can redistribute it and/or modify
6561   *     it under the terms of the GNU General Public License as published by
6562 @@ -22,48 +22,28 @@
6563   *
6564   ******************************************************************************/
6565
6566 -/******************************************************************************
6567 - *
6568 - * Description:
6569 - *
6570 - * In this file, all data types that are needed by the common modules
6571 - * are mapped to Linux data types.
6572 - *
6573 - *
6574 - * Include File Hierarchy:
6575 - *
6576 - *
6577 - ******************************************************************************/
6578 -
6579  #ifndef __INC_SKTYPES_H
6580  #define __INC_SKTYPES_H
6581
6582 -
6583 -/* defines *******************************************************************/
6584 -
6585 -/*
6586 - * Data types with a specific size. 'I' = signed, 'U' = unsigned.
6587 - */
6588 -#define SK_I8  s8
6589 -#define SK_U8  u8
6590 -#define SK_I16 s16
6591 -#define SK_U16 u16
6592 -#define SK_I32 s32
6593 -#define SK_U32 u32
6594 -#define SK_I64 s64
6595 -#define SK_U64 u64
6596 -
6597 -#define SK_UPTR        ulong           /* casting pointer <-> integral */
6598 -
6599 -/*
6600 -* Boolean type.
6601 -*/
6602 -#define SK_BOOL                SK_U8
6603 -#define SK_FALSE       0
6604 -#define SK_TRUE                (!SK_FALSE)
6605 -
6606 -/* typedefs *******************************************************************/
6607 -
6608 -/* function prototypes ********************************************************/
6609 +#define SK_I8    s8    /* 8 bits (1 byte) signed       */
6610 +#define SK_U8    u8    /* 8 bits (1 byte) unsigned     */
6611 +#define SK_I16  s16    /* 16 bits (2 bytes) signed     */
6612 +#define SK_U16  u16    /* 16 bits (2 bytes) unsigned   */
6613 +#define SK_I32  s32    /* 32 bits (4 bytes) signed     */
6614 +#define SK_U32  u32    /* 32 bits (4 bytes) unsigned   */
6615 +#define SK_I64  s64    /* 64 bits (8 bytes) signed     */
6616 +#define SK_U64  u64    /* 64 bits (8 bytes) unsigned   */
6617 +
6618 +#define SK_UPTR        ulong  /* casting pointer <-> integral */
6619 +
6620 +#define SK_BOOL   SK_U8
6621 +#define SK_FALSE  0
6622 +#define SK_TRUE   (!SK_FALSE)
6623
6624  #endif /* __INC_SKTYPES_H */
6625 +
6626 +/*******************************************************************************
6627 + *
6628 + * End of file
6629 + *
6630 + ******************************************************************************/
6631 diff -ruN linux/drivers/net/sk98lin/h/skversion.h linux-new/drivers/net/sk98lin/h/skversion.h
6632 --- linux/drivers/net/sk98lin/h/skversion.h     2006-09-20 05:42:06.000000000 +0200
6633 +++ linux-new/drivers/net/sk98lin/h/skversion.h 2006-07-28 14:13:54.000000000 +0200
6634 @@ -1,17 +1,17 @@
6635  /******************************************************************************
6636   *
6637 - * Name:       version.h
6638 + * Name:       skversion.h
6639   * Project:    GEnesis, PCI Gigabit Ethernet Adapter
6640 - * Version:    $Revision$
6641 - * Date:       $Date$
6642 - * Purpose:    SK specific Error log support
6643 + * Version:    $Revision$
6644 + * Date:       $Date$
6645 + * Purpose:    specific version strings and numbers
6646   *
6647   ******************************************************************************/
6648
6649  /******************************************************************************
6650   *
6651   *     (C)Copyright 1998-2002 SysKonnect GmbH.
6652 - *     (C)Copyright 2002-2003 Marvell.
6653 + *     (C)Copyright 2002-2005 Marvell.
6654   *
6655   *     This program is free software; you can redistribute it and/or modify
6656   *     it under the terms of the GNU General Public License as published by
6657 @@ -22,17 +22,15 @@
6658   *
6659   ******************************************************************************/
6660
6661 -#ifdef lint
6662 -static const char SysKonnectFileId[] = "@(#) (C) SysKonnect GmbH.";
6663 -static const char SysKonnectBuildNumber[] =
6664 -       "@(#)SK-BUILD: 6.23 PL: 01";
6665 -#endif /* !defined(lint) */
6666 -
6667 -#define BOOT_STRING    "sk98lin: Network Device Driver v6.23\n" \
6668 -                       "(C)Copyright 1999-2004 Marvell(R)."
6669 -
6670 -#define VER_STRING     "6.23"
6671 -#define DRIVER_FILE_NAME       "sk98lin"
6672 -#define DRIVER_REL_DATE                "Feb-13-2004"
6673 -
6674 +#define BOOT_STRING  "sk98lin: Network Device Driver v8.36.1.3\n" \
6675 +                     "(C)Copyright 1999-2006 Marvell(R)."
6676 +#define VER_STRING   "8.36.1.3"
6677 +#define PATCHLEVEL   "01"
6678 +#define DRIVER_FILE_NAME   "sk98lin"
6679 +#define DRIVER_REL_DATE    "Jul-28-2006"
6680
6681 +/*******************************************************************************
6682 + *
6683 + * End of file
6684 + *
6685 + ******************************************************************************/
6686 diff -ruN linux/drivers/net/sk98lin/h/skvpd.h linux-new/drivers/net/sk98lin/h/skvpd.h
6687 --- linux/drivers/net/sk98lin/h/skvpd.h 2006-09-20 05:42:06.000000000 +0200
6688 +++ linux-new/drivers/net/sk98lin/h/skvpd.h     2006-07-28 14:13:54.000000000 +0200
6689 @@ -1,23 +1,25 @@
6690  /******************************************************************************
6691   *
6692   * Name:       skvpd.h
6693 - * Project:    GEnesis, PCI Gigabit Ethernet Adapter
6694 - * Version:    $Revision$
6695 - * Date:       $Date$
6696 + * Project:    Gigabit Ethernet Adapters, VPD-Module
6697 + * Version:    $Revision$
6698 + * Date:       $Date$
6699   * Purpose:    Defines and Macros for VPD handling
6700   *
6701   ******************************************************************************/
6702
6703  /******************************************************************************
6704   *
6705 - *     (C)Copyright 1998-2003 SysKonnect GmbH.
6706 + *     LICENSE:
6707 + *     (C)Copyright 1998-2002 SysKonnect.
6708 + *     (C)Copyright 2002-2004 Marvell.
6709   *
6710   *     This program is free software; you can redistribute it and/or modify
6711   *     it under the terms of the GNU General Public License as published by
6712   *     the Free Software Foundation; either version 2 of the License, or
6713   *     (at your option) any later version.
6714 - *
6715   *     The information in this file is provided "AS IS" without warranty.
6716 + *     /LICENSE
6717   *
6718   ******************************************************************************/
6719
6720 @@ -31,7 +33,7 @@
6721  /*
6722   * Define Resource Type Identifiers and VPD keywords
6723   */
6724 -#define        RES_ID          0x82    /* Resource Type ID String (Product Name) */
6725 +#define RES_ID         0x82    /* Resource Type ID String (Product Name) */
6726  #define RES_VPD_R      0x90    /* start of VPD read only area */
6727  #define RES_VPD_W      0x91    /* start of VPD read/write area */
6728  #define RES_END                0x78    /* Resource Type End Tag */
6729 @@ -40,14 +42,16 @@
6730  #define VPD_NAME       "Name"  /* Product Name, VPD name of RES_ID */
6731  #endif /* VPD_NAME */
6732  #define VPD_PN         "PN"    /* Adapter Part Number */
6733 -#define        VPD_EC          "EC"    /* Adapter Engineering Level */
6734 +#define VPD_EC         "EC"    /* Adapter Engineering Level */
6735  #define VPD_MN         "MN"    /* Manufacture ID */
6736  #define VPD_SN         "SN"    /* Serial Number */
6737  #define VPD_CP         "CP"    /* Extended Capability */
6738  #define VPD_RV         "RV"    /* Checksum and Reserved */
6739 -#define        VPD_YA          "YA"    /* Asset Tag Identifier */
6740 +#define VPD_YA         "YA"    /* Asset Tag Identifier */
6741  #define VPD_VL         "VL"    /* First Error Log Message (SK specific) */
6742  #define VPD_VF         "VF"    /* Second Error Log Message (SK specific) */
6743 +#define VPD_VB         "VB"    /* Boot Agent ROM Configuration (SK specific) */
6744 +#define VPD_VE         "VE"    /* EFI UNDI Configuration (SK specific) */
6745  #define VPD_RW         "RW"    /* Remaining Read / Write Area */
6746
6747  /* 'type' values for vpd_setup_para() */
6748 @@ -55,7 +59,7 @@
6749  #define VPD_RW_KEY     2       /* RW keys are "Yx", "Vx", and "RW" */
6750
6751  /* 'op' values for vpd_setup_para() */
6752 -#define        ADD_KEY         1       /* add the key at the pos "RV" or "RW" */
6753 +#define ADD_KEY                1       /* add the key at the pos "RV" or "RW" */
6754  #define OWR_KEY                2       /* overwrite key if already exists */
6755
6756  /*
6757 @@ -64,18 +68,18 @@
6758
6759  #define VPD_DEV_ID_GENESIS     0x4300
6760
6761 -#define        VPD_SIZE_YUKON          256
6762 -#define        VPD_SIZE_GENESIS        512
6763 -#define        VPD_SIZE                        512
6764 +#define VPD_SIZE_YUKON         256
6765 +#define VPD_SIZE_GENESIS       512
6766 +#define VPD_SIZE                       512
6767  #define VPD_READ       0x0000
6768  #define VPD_WRITE      0x8000
6769
6770  #define VPD_STOP(pAC,IoC)      VPD_OUT16(pAC,IoC,PCI_VPD_ADR_REG,VPD_WRITE)
6771
6772 -#define VPD_GET_RES_LEN(p)     ((unsigned int) \
6773 -                                       (* (SK_U8 *)&(p)[1]) |\
6774 -                                       ((* (SK_U8 *)&(p)[2]) << 8))
6775 -#define VPD_GET_VPD_LEN(p)     ((unsigned int)(* (SK_U8 *)&(p)[2]))
6776 +#define VPD_GET_RES_LEN(p)     ((unsigned int)\
6777 +                                       (*(SK_U8 *)&(p)[1]) |\
6778 +                                       ((*(SK_U8 *)&(p)[2]) << 8))
6779 +#define VPD_GET_VPD_LEN(p)     ((unsigned int)(*(SK_U8 *)&(p)[2]))
6780  #define VPD_GET_VAL(p)         ((char *)&(p)[3])
6781
6782  #define VPD_MAX_LEN    50
6783 @@ -126,62 +130,78 @@
6784  /*
6785   * System specific VPD macros
6786   */
6787 -#ifndef SKDIAG
6788 +#ifndef SK_DIAG
6789  #ifndef VPD_DO_IO
6790  #define VPD_OUT8(pAC,IoC,Addr,Val)     (void)SkPciWriteCfgByte(pAC,Addr,Val)
6791  #define VPD_OUT16(pAC,IoC,Addr,Val)    (void)SkPciWriteCfgWord(pAC,Addr,Val)
6792 +#define VPD_OUT32(pAC,IoC,Addr,Val)    (void)SkPciWriteCfgDWord(pAC,Addr,Val)
6793  #define VPD_IN8(pAC,IoC,Addr,pVal)     (void)SkPciReadCfgByte(pAC,Addr,pVal)
6794  #define VPD_IN16(pAC,IoC,Addr,pVal)    (void)SkPciReadCfgWord(pAC,Addr,pVal)
6795  #define VPD_IN32(pAC,IoC,Addr,pVal)    (void)SkPciReadCfgDWord(pAC,Addr,pVal)
6796  #else  /* VPD_DO_IO */
6797 -#define VPD_OUT8(pAC,IoC,Addr,Val)     SK_OUT8(IoC,PCI_C(Addr),Val)
6798 -#define VPD_OUT16(pAC,IoC,Addr,Val)    SK_OUT16(IoC,PCI_C(Addr),Val)
6799 -#define VPD_IN8(pAC,IoC,Addr,pVal)     SK_IN8(IoC,PCI_C(Addr),pVal)
6800 -#define VPD_IN16(pAC,IoC,Addr,pVal)    SK_IN16(IoC,PCI_C(Addr),pVal)
6801 -#define VPD_IN32(pAC,IoC,Addr,pVal)    SK_IN32(IoC,PCI_C(Addr),pVal)
6802 +#define VPD_OUT8(pAC,IoC,Addr,Val)     SK_OUT8(IoC,PCI_C(pAC,Addr),Val)
6803 +#define VPD_OUT16(pAC,IoC,Addr,Val)    SK_OUT16(IoC,PCI_C(pAC,Addr),Val)
6804 +#define VPD_OUT32(pAC,IoC,Addr,Val)    SK_OUT32(IoC,PCI_C(pAC,Addr),Val)
6805 +#define VPD_IN8(pAC,IoC,Addr,pVal)     SK_IN8(IoC,PCI_C(pAC,Addr),pVal)
6806 +#define VPD_IN16(pAC,IoC,Addr,pVal)    SK_IN16(IoC,PCI_C(pAC,Addr),pVal)
6807 +#define VPD_IN32(pAC,IoC,Addr,pVal)    SK_IN32(IoC,PCI_C(pAC,Addr),pVal)
6808  #endif /* VPD_DO_IO */
6809 -#else  /* SKDIAG */
6810 +#else  /* SK_DIAG */
6811  #define VPD_OUT8(pAC,Ioc,Addr,Val) {                   \
6812                 if ((pAC)->DgT.DgUseCfgCycle)                   \
6813                         SkPciWriteCfgByte(pAC,Addr,Val);        \
6814                 else                                                                    \
6815 -                       SK_OUT8(pAC,PCI_C(Addr),Val);           \
6816 +                       SK_OUT8(pAC,PCI_C(pAC,Addr),Val);       \
6817                 }
6818  #define VPD_OUT16(pAC,Ioc,Addr,Val) {                  \
6819                 if ((pAC)->DgT.DgUseCfgCycle)                   \
6820                         SkPciWriteCfgWord(pAC,Addr,Val);        \
6821                 else                                            \
6822 -                       SK_OUT16(pAC,PCI_C(Addr),Val);          \
6823 +                       SK_OUT16(pAC,PCI_C(pAC,Addr),Val);      \
6824 +               }
6825 +#define VPD_OUT32(pAC,Ioc,Addr,Val) {                  \
6826 +               if ((pAC)->DgT.DgUseCfgCycle)                   \
6827 +                       SkPciWriteCfgDWord(pAC,Addr,Val);       \
6828 +               else                                            \
6829 +                       SK_OUT32(pAC,PCI_C(pAC,Addr),Val);      \
6830                 }
6831  #define VPD_IN8(pAC,Ioc,Addr,pVal) {                   \
6832 -               if ((pAC)->DgT.DgUseCfgCycle)                   \
6833 +               if ((pAC)->DgT.DgUseCfgCycle)                   \
6834                         SkPciReadCfgByte(pAC,Addr,pVal);        \
6835                 else                                            \
6836 -                       SK_IN8(pAC,PCI_C(Addr),pVal);           \
6837 +                       SK_IN8(pAC,PCI_C(pAC,Addr),pVal);       \
6838                 }
6839  #define VPD_IN16(pAC,Ioc,Addr,pVal) {                  \
6840 -               if ((pAC)->DgT.DgUseCfgCycle)                   \
6841 +               if ((pAC)->DgT.DgUseCfgCycle)                   \
6842                         SkPciReadCfgWord(pAC,Addr,pVal);        \
6843                 else                                            \
6844 -                       SK_IN16(pAC,PCI_C(Addr),pVal);          \
6845 +                       SK_IN16(pAC,PCI_C(pAC,Addr),pVal);      \
6846                 }
6847  #define VPD_IN32(pAC,Ioc,Addr,pVal) {                  \
6848                 if ((pAC)->DgT.DgUseCfgCycle)                   \
6849                         SkPciReadCfgDWord(pAC,Addr,pVal);       \
6850                 else                                            \
6851 -                       SK_IN32(pAC,PCI_C(Addr),pVal);          \
6852 +                       SK_IN32(pAC,PCI_C(pAC,Addr),pVal);      \
6853                 }
6854 -#endif /* nSKDIAG */
6855 +#endif /* SK_DIAG */
6856
6857  /* function prototypes ********************************************************/
6858
6859  #ifndef        SK_KR_PROTO
6860 -#ifdef SKDIAG
6861 +#ifdef SK_DIAG
6862  extern SK_U32  VpdReadDWord(
6863         SK_AC           *pAC,
6864         SK_IOC          IoC,
6865         int                     addr);
6866 -#endif /* SKDIAG */
6867 +#endif /* SK_DIAG */
6868 +
6869 +extern int     VpdSetupPara(
6870 +       SK_AC           *pAC,
6871 +       const char      *key,
6872 +       const char      *buf,
6873 +       int                     len,
6874 +       int                     type,
6875 +       int                     op);
6876
6877  extern SK_VPD_STATUS   *VpdStat(
6878         SK_AC           *pAC,
6879 @@ -219,7 +239,17 @@
6880         SK_AC           *pAC,
6881         SK_IOC          IoC);
6882
6883 -#ifdef SKDIAG
6884 +extern void    VpdErrLog(
6885 +       SK_AC           *pAC,
6886 +       SK_IOC          IoC,
6887 +       char            *msg);
6888 +
6889 +int VpdInit(
6890 +       SK_AC           *pAC,
6891 +       SK_IOC          IoC);
6892 +
6893 +#if defined(SK_DIAG) || defined(SK_ASF)
6894 +
6895  extern int     VpdReadBlock(
6896         SK_AC           *pAC,
6897         SK_IOC          IoC,
6898 @@ -233,9 +263,12 @@
6899         char            *buf,
6900         int                     addr,
6901         int                     len);
6902 -#endif /* SKDIAG */
6903 +
6904 +#endif /* SK_DIAG || SK_ASF */
6905 +
6906  #else  /* SK_KR_PROTO */
6907  extern SK_U32  VpdReadDWord();
6908 +extern int     VpdSetupPara();
6909  extern SK_VPD_STATUS   *VpdStat();
6910  extern int     VpdKeys();
6911  extern int     VpdRead();
6912 @@ -243,6 +276,8 @@
6913  extern int     VpdWrite();
6914  extern int     VpdDelete();
6915  extern int     VpdUpdate();
6916 +extern void    VpdErrLog();
6917  #endif /* SK_KR_PROTO */
6918
6919  #endif /* __INC_SKVPD_H_ */
6920 +
6921 diff -ruN linux/drivers/net/sk98lin/h/sky2le.h linux-new/drivers/net/sk98lin/h/sky2le.h
6922 --- linux/drivers/net/sk98lin/h/sky2le.h        1970-01-01 01:00:00.000000000 +0100
6923 +++ linux-new/drivers/net/sk98lin/h/sky2le.h    2006-07-28 14:13:54.000000000 +0200
6924 @@ -0,0 +1,890 @@
6925 +/******************************************************************************
6926 + *
6927 + * Name:       sky2le.h
6928 + * Project:    Gigabit Ethernet Adapters, Common Modules
6929 + * Version:    $Revision$
6930 + * Date:       $Date$
6931 + * Purpose:    Common list element definitions and access macros.
6932 + *
6933 + ******************************************************************************/
6934 +
6935 +/******************************************************************************
6936 + *
6937 + *     LICENSE:
6938 + *     (C)Copyright 2002-2006 Marvell.
6939 + *
6940 + *     This program is free software; you can redistribute it and/or modify
6941 + *     it under the terms of the GNU General Public License as published by
6942 + *     the Free Software Foundation; either version 2 of the License, or
6943 + *     (at your option) any later version.
6944 + *     The information in this file is provided "AS IS" without warranty.
6945 + *     /LICENSE
6946 + *
6947 + ******************************************************************************/
6948 +
6949 +#ifndef __INC_SKY2LE_H
6950 +#define __INC_SKY2LE_H
6951 +
6952 +#ifdef __cplusplus
6953 +extern "C" {
6954 +#endif /* __cplusplus */
6955 +
6956 +/* defines ********************************************************************/
6957 +
6958 +#define MIN_LEN_OF_LE_TAB      128
6959 +#define MAX_LEN_OF_LE_TAB      4096
6960 +#ifdef USE_POLLING_UNIT
6961 +#define NUM_LE_POLLING_UNIT    2
6962 +#endif
6963 +#define MAX_FRAG_OVERHEAD      10
6964 +
6965 +/* Macro for aligning a given value */
6966 +#define SK_ALIGN_SIZE(Value, Alignment, AlignedVal) {                                  \
6967 +       (AlignedVal) = (((Value) + (Alignment) - 1) & (~((Alignment) - 1)));\
6968 +}
6969 +
6970 +/******************************************************************************
6971 + *
6972 + * LE2DWord() - Converts the given Little Endian value to machine order value
6973 + *
6974 + * Description:
6975 + *     This function converts the Little Endian value received as an argument to
6976 + *     the machine order value.
6977 + *
6978 + * Returns:
6979 + *     The converted value
6980 + *
6981 + */
6982 +
6983 +#ifdef SK_LITTLE_ENDIAN
6984 +
6985 +#ifndef        SK_USE_REV_DESC
6986 +#define LE2DWord(value)        (value)
6987 +#else  /* SK_USE_REV_DESC */
6988 +#define LE2DWord(value)                                        \
6989 +       ((((value)<<24L) & 0xff000000L) +       \
6990 +        (((value)<< 8L) & 0x00ff0000L) +       \
6991 +        (((value)>> 8L) & 0x0000ff00L) +       \
6992 +        (((value)>>24L) & 0x000000ffL))
6993 +#endif /* SK_USE_REV_DESC */
6994 +
6995 +#else  /* !SK_LITTLE_ENDIAN */
6996 +
6997 +#ifndef        SK_USE_REV_DESC
6998 +#define LE2DWord(value)                                        \
6999 +       ((((value)<<24L) & 0xff000000L) +       \
7000 +        (((value)<< 8L) & 0x00ff0000L) +       \
7001 +        (((value)>> 8L) & 0x0000ff00L) +       \
7002 +        (((value)>>24L) & 0x000000ffL))
7003 +#else  /* SK_USE_REV_DESC */
7004 +#define LE2DWord(value)        (value)
7005 +#endif /* SK_USE_REV_DESC */
7006 +
7007 +#endif /* !SK_LITTLE_ENDIAN */
7008 +
7009 +/******************************************************************************
7010 + *
7011 + * DWord2LE() - Converts the given value to a Little Endian value
7012 + *
7013 + * Description:
7014 + *     This function converts the value received as an argument to a Little Endian
7015 + *     value on Big Endian machines. If the machine running the code is Little
7016 + *     Endian, then no conversion is done.
7017 + *
7018 + * Returns:
7019 + *     The converted value
7020 + *
7021 + */
7022 +
7023 +#ifdef SK_LITTLE_ENDIAN
7024 +
7025 +#ifndef        SK_USE_REV_DESC
7026 +#define DWord2LE(value) (value)
7027 +#else  /* SK_USE_REV_DESC */
7028 +#define DWord2LE(value)                                        \
7029 +       ((((value)<<24L) & 0xff000000L) +       \
7030 +        (((value)<< 8L) & 0x00ff0000L) +       \
7031 +        (((value)>> 8L) & 0x0000ff00L) +       \
7032 +        (((value)>>24L) & 0x000000ffL))
7033 +#endif /* SK_USE_REV_DESC */
7034 +
7035 +#else  /* !SK_LITTLE_ENDIAN */
7036 +
7037 +#ifndef        SK_USE_REV_DESC
7038 +#define DWord2LE(value)                                        \
7039 +       ((((value)<<24L) & 0xff000000L) +       \
7040 +        (((value)<< 8L) & 0x00ff0000L) +       \
7041 +        (((value)>> 8L) & 0x0000ff00L) +       \
7042 +        (((value)>>24L) & 0x000000ffL))
7043 +#else  /* SK_USE_REV_DESC */
7044 +#define DWord2LE(value) (value)
7045 +#endif /* SK_USE_REV_DESC */
7046 +#endif /* !SK_LITTLE_ENDIAN */
7047 +
7048 +/******************************************************************************
7049 + *
7050 + * LE2Word() - Converts the given Little Endian value to machine order value
7051 + *
7052 + * Description:
7053 + *     This function converts the Little Endian value received as an argument to
7054 + *     the machine order value.
7055 + *
7056 + * Returns:
7057 + *     The converted value
7058 + *
7059 + */
7060 +
7061 +#ifdef SK_LITTLE_ENDIAN
7062 +#ifndef        SK_USE_REV_DESC
7063 +#define LE2Word(value) (value)
7064 +#else  /* SK_USE_REV_DESC */
7065 +#define LE2Word(value)                         \
7066 +       ((((value)<< 8L) & 0xff00) +    \
7067 +        (((value)>> 8L) & 0x00ff))
7068 +#endif /* SK_USE_REV_DESC */
7069 +
7070 +#else  /* !SK_LITTLE_ENDIAN */
7071 +#ifndef        SK_USE_REV_DESC
7072 +#define LE2Word(value)                         \
7073 +       ((((value)<< 8L) & 0xff00) +    \
7074 +        (((value)>> 8L) & 0x00ff))
7075 +#else  /* SK_USE_REV_DESC */
7076 +#define LE2Word(value) (value)
7077 +#endif /* SK_USE_REV_DESC */
7078 +#endif /* !SK_LITTLE_ENDIAN */
7079 +
7080 +/******************************************************************************
7081 + *
7082 + * Word2LE() - Converts the given value to a Little Endian value
7083 + *
7084 + * Description:
7085 + *     This function converts the value received as an argument to a Little Endian
7086 + *     value on Big Endian machines. If the machine running the code is Little
7087 + *     Endian, then no conversion is done.
7088 + *
7089 + * Returns:
7090 + *     The converted value
7091 + *
7092 + */
7093 +
7094 +#ifdef SK_LITTLE_ENDIAN
7095 +#ifndef        SK_USE_REV_DESC
7096 +#define Word2LE(value) (value)
7097 +#else  /* SK_USE_REV_DESC */
7098 +#define Word2LE(value)                         \
7099 +       ((((value)<< 8L) & 0xff00) +    \
7100 +        (((value)>> 8L) & 0x00ff))
7101 +#endif /* SK_USE_REV_DESC */
7102 +
7103 +#else  /* !SK_LITTLE_ENDIAN */
7104 +#ifndef        SK_USE_REV_DESC
7105 +#define Word2LE(value)                         \
7106 +       ((((value)<< 8L) & 0xff00) +    \
7107 +        (((value)>> 8L) & 0x00ff))
7108 +#else  /* SK_USE_REV_DESC */
7109 +#define Word2LE(value) (value)
7110 +#endif /* SK_USE_REV_DESC */
7111 +#endif /* !SK_LITTLE_ENDIAN */
7112 +
7113 +/******************************************************************************
7114 + *
7115 + * Transmit list element macros
7116 + *
7117 + */
7118 +
7119 +#define TXLE_SET_ADDR(pLE, Addr)       \
7120 +       ((pLE)->Tx.TxUn.BufAddr = DWord2LE(Addr))
7121 +#define TXLE_SET_LSLEN(pLE, Len)       \
7122 +       ((pLE)->Tx.TxUn.LargeSend.Length = Word2LE(Len))
7123 +#define TXLE_SET_STACS(pLE, Start)     \
7124 +       ((pLE)->Tx.TxUn.ChkSum.TxTcpSp = Word2LE(Start))
7125 +#define TXLE_SET_WRICS(pLE, Write)     \
7126 +       ((pLE)->Tx.TxUn.ChkSum.TxTcpWp = Word2LE(Write))
7127 +#define TXLE_SET_INICS(pLE, Ini)       ((pLE)->Tx.Send.InitCsum = Word2LE(Ini))
7128 +#define TXLE_SET_LEN(pLE, Len)         ((pLE)->Tx.Send.BufLen = Word2LE(Len))
7129 +#define TXLE_SET_VLAN(pLE, Vlan)       ((pLE)->Tx.Send.VlanTag = Word2LE(Vlan))
7130 +#define TXLE_SET_LCKCS(pLE, Lock)      ((pLE)->Tx.ControlFlags = (Lock))
7131 +#define TXLE_SET_CTRL(pLE, Ctrl)       ((pLE)->Tx.ControlFlags = (Ctrl))
7132 +#define TXLE_SET_OPC(pLE, Opc)         ((pLE)->Tx.Opcode = (Opc))
7133 +
7134 +#define TXLE_GET_ADDR(pLE)             LE2DWord((pLE)->Tx.TxUn.BufAddr)
7135 +#define TXLE_GET_LSLEN(pLE)            LE2Word((pLE)->Tx.TxUn.LargeSend.Length)
7136 +#define TXLE_GET_STACS(pLE)            LE2Word((pLE)->Tx.TxUn.ChkSum.TxTcpSp)
7137 +#define TXLE_GET_WRICS(pLE)            LE2Word((pLE)->Tx.TxUn.ChkSum.TxTcpWp)
7138 +#define TXLE_GET_INICS(pLE)            LE2Word((pLE)->Tx.Send.InitCsum)
7139 +#define TXLE_GET_LEN(pLE)              LE2Word((pLE)->Tx.Send.BufLen)
7140 +#define TXLE_GET_VLAN(pLE)             LE2Word((pLE)->Tx.Send.VlanTag)
7141 +#define TXLE_GET_LCKCS(pLE)            ((pLE)->Tx.ControlFlags)
7142 +#define TXLE_GET_CTRL(pLE)             ((pLE)->Tx.ControlFlags)
7143 +#define TXLE_GET_OPC(pLE)              ((pLE)->Tx.Opcode)
7144 +
7145 +/******************************************************************************
7146 + *
7147 + * Receive list element macros
7148 + *
7149 + */
7150 +
7151 +#define RXLE_SET_ADDR(pLE, Addr)       \
7152 +       ((pLE)->Rx.RxUn.BufAddr = (SK_U32)DWord2LE(Addr))
7153 +#define RXLE_SET_STACS2(pLE, Offs)     \
7154 +       ((pLE)->Rx.RxUn.ChkSum.RxTcpSp2 = Word2LE(Offs))
7155 +#define RXLE_SET_STACS1(pLE, Offs)     \
7156 +       ((pLE)->Rx.RxUn.ChkSum.RxTcpSp1 = Word2LE(Offs))
7157 +#define RXLE_SET_LEN(pLE, Len)         ((pLE)->Rx.BufferLength = Word2LE(Len))
7158 +#define RXLE_SET_CTRL(pLE, Ctrl)       ((pLE)->Rx.ControlFlags = (Ctrl))
7159 +#define RXLE_SET_OPC(pLE, Opc)         ((pLE)->Rx.Opcode = (Opc))
7160 +
7161 +#define RXLE_GET_ADDR(pLE)             LE2DWord((pLE)->Rx.RxUn.BufAddr)
7162 +#define RXLE_GET_STACS2(pLE)   LE2Word((pLE)->Rx.RxUn.ChkSum.RxTcpSp2)
7163 +#define RXLE_GET_STACS1(pLE)   LE2Word((pLE)->Rx.RxUn.ChkSum.RxTcpSp1)
7164 +#define RXLE_GET_LEN(pLE)              LE2Word((pLE)->Rx.BufferLength)
7165 +#define RXLE_GET_CTRL(pLE)             ((pLE)->Rx.ControlFlags)
7166 +#define RXLE_GET_OPC(pLE)              ((pLE)->Rx.Opcode)
7167 +
7168 +/******************************************************************************
7169 + *
7170 + * Status list element macros
7171 + *
7172 + */
7173 +
7174 +#define STLE_SET_OPC(pLE, Opc)         ((pLE)->St.Opcode = (Opc))
7175 +
7176 +#define STLE_GET_FRSTATUS(pLE) LE2DWord((pLE)->St.StUn.StRxStatWord)
7177 +#define STLE_GET_TIST(pLE)             LE2DWord((pLE)->St.StUn.StRxTimeStamp)
7178 +#define STLE_GET_TCP1(pLE)             LE2Word((pLE)->St.StUn.StRxTCPCSum.RxTCPSum1)
7179 +#define STLE_GET_TCP2(pLE)             LE2Word((pLE)->St.StUn.StRxTCPCSum.RxTCPSum2)
7180 +#define STLE_GET_LEN(pLE)              LE2Word((pLE)->St.Stat.BufLen)
7181 +#define STLE_GET_VLAN(pLE)             LE2Word((pLE)->St.Stat.VlanTag)
7182 +#define STLE_GET_LINK(pLE)             ((pLE)->St.Link)
7183 +#define STLE_GET_OPC(pLE)              ((pLE)->St.Opcode)
7184 +#define STLE_GET_DONE_IDX(pLE,LowVal,HighVal) {                        \
7185 +       (LowVal) = LE2DWord((pLE)->St.StUn.StTxStatLow);        \
7186 +       (HighVal) = LE2Word((pLE)->St.Stat.StTxStatHi);         \
7187 +}
7188 +
7189 +#define STLE_GET_RSS(pLE)              LE2DWord((pLE)->St.StUn.StRxRssValue)
7190 +#define STLE_GET_IPBIT(pLE)            ((pLE)->St.Stat.Rss.FlagField & RSS_IP_FLAG)
7191 +#define STLE_GET_TCPBIT(pLE)   ((pLE)->St.Stat.Rss.FlagField & RSS_TCP_FLAG)
7192 +
7193 +
7194 +/* always take both values as a parameter to avoid typos */
7195 +#define STLE_GET_DONE_IDX_TXA1(LowVal,HighVal)                 \
7196 +       (((LowVal) & STLE_TXA1_MSKL) >> STLE_TXA1_SHIFTL)
7197 +#define STLE_GET_DONE_IDX_TXS1(LowVal,HighVal)                 \
7198 +       ((LowVal & STLE_TXS1_MSKL) >> STLE_TXS1_SHIFTL)
7199 +#define STLE_GET_DONE_IDX_TXA2(LowVal,HighVal)                 \
7200 +       (((LowVal & STLE_TXA2_MSKL) >> STLE_TXA2_SHIFTL) +      \
7201 +       ((HighVal & STLE_TXA2_MSKH) << STLE_TXA2_SHIFTH))
7202 +#define STLE_GET_DONE_IDX_TXS2(LowVal,HighVal)                 \
7203 +       ((HighVal & STLE_TXS2_MSKH) >> STLE_TXS2_SHIFTH)
7204 +
7205 +
7206 +#define SK_Y2_RXSTAT_CHECK_PKT(Len, RxStat, IsOk) {                    \
7207 +       (IsOk) = (((RxStat) & GMR_FS_RX_OK) != 0) &&                    \
7208 +                        (((RxStat) & GMR_FS_ANY_ERR) == 0);                    \
7209 +                                                                                                                       \
7210 +       if ((IsOk) && ((SK_U16)(((RxStat) & GMR_FS_LEN_MSK) >>  \
7211 +               GMR_FS_LEN_SHIFT) != (Len))) {                                          \
7212 +               /* length in MAC status differs from length in LE */\
7213 +               (IsOk) = SK_FALSE;                                                                      \
7214 +       }                                                                                                               \
7215 +}
7216 +
7217 +
7218 +/******************************************************************************
7219 + *
7220 + * Polling unit list element macros
7221 + *
7222 + * NOTE: the Idx must be <= 0xfff and PU_PUTIDX_VALID makes them valid
7223 + *
7224 + */
7225 +
7226 +#ifdef USE_POLLING_UNIT
7227 +
7228 +#define POLE_SET_OPC(pLE, Opc)         ((pLE)->Sa.Opcode = (Opc))
7229 +#define POLE_SET_LINK(pLE, Port)       ((pLE)->Sa.Link = (Port))
7230 +#define POLE_SET_RXIDX(pLE, Idx)       ((pLE)->Sa.RxIdxVld = Word2LE(Idx))
7231 +#define POLE_SET_TXAIDX(pLE, Idx)      ((pLE)->Sa.TxAIdxVld = Word2LE(Idx))
7232 +#define POLE_SET_TXSIDX(pLE, Idx)      ((pLE)->Sa.TxSIdxVld = Word2LE(Idx))
7233 +
7234 +#define POLE_GET_OPC(pLE)              ((pLE)->Sa.Opcode)
7235 +#define POLE_GET_LINK(pLE)             ((pLE)->Sa.Link)
7236 +#define POLE_GET_RXIDX(pLE)            LE2Word((pLE)->Sa.RxIdxVld)
7237 +#define POLE_GET_TXAIDX(pLE)   LE2Word((pLE)->Sa.TxAIdxVld)
7238 +#define POLE_GET_TXSIDX(pLE)   LE2Word((pLE)->Sa.TxSIdxVld)
7239 +
7240 +#endif /* USE_POLLING_UNIT */
7241 +
7242 +/******************************************************************************
7243 + *
7244 + * Debug macros for list elements
7245 + *
7246 + */
7247 +
7248 +#ifdef DEBUG
7249 +
7250 +#define SK_DBG_DUMP_RX_LE(pLE) {                                                                               \
7251 +       SK_U8   Opcode;                                                                                                         \
7252 +       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                          \
7253 +               ("=== RX_LIST_ELEMENT @addr: %p cont: %02x %02x %02x %02x %02x %02x %02x %02x\n",       \
7254 +               pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\
7255 +               ((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5],             \
7256 +               ((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7]));                                               \
7257 +       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                          \
7258 +               ("\t (16bit) %04x %04x %04x %04x\n",                                                    \
7259 +               ((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2],  \
7260 +               ((SK_U16 *) pLE)[3]));                                                                                  \
7261 +       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                          \
7262 +               ("\t (32bit) %08x %08x\n",                                                                              \
7263 +               ((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1]));                                     \
7264 +       Opcode = RXLE_GET_OPC(pLE);                                                                                     \
7265 +       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                          \
7266 +               ("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == HW_OWNER) ?   \
7267 +                "Hardware" : "Software"));                                                                             \
7268 +       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                          \
7269 +               ("\tOpc: 0x%x ",Opcode));                                                                               \
7270 +       switch (Opcode & (~HW_OWNER)) {                                                                         \
7271 +       case OP_BUFFER:                                                                                                         \
7272 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7273 +                       ("\tOP_BUFFER\n"));                                                                                     \
7274 +               break;                                                                                                                  \
7275 +       case OP_PACKET:                                                                                                         \
7276 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7277 +                       ("\tOP_PACKET\n"));                                                                                     \
7278 +               break;                                                                                                                  \
7279 +       case OP_ADDR64:                                                                                                         \
7280 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7281 +                       ("\tOP_ADDR64\n"));                                                                                     \
7282 +               break;                                                                                                                  \
7283 +       case OP_TCPSTART:                                                                                                       \
7284 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7285 +                       ("\tOP_TCPPAR\n"));                                                                                     \
7286 +               break;                                                                                                                  \
7287 +       case SW_OWNER:                                                                                                          \
7288 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7289 +                       ("\tunused LE\n"));                                                                                     \
7290 +               break;                                                                                                                  \
7291 +       default:                                                                                                                        \
7292 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7293 +                       ("\tunknown Opcode!!!\n"));                                                                     \
7294 +       }                                                                                                                                       \
7295 +       if ((Opcode & OP_BUFFER) == OP_BUFFER) {                                                        \
7296 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7297 +                       ("\tControl: 0x%x\n", RXLE_GET_CTRL(pLE)));                                     \
7298 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7299 +                       ("\tBufLen: 0x%x\n", RXLE_GET_LEN(pLE)));                                       \
7300 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7301 +                       ("\tLowAddr: 0x%x\n", RXLE_GET_ADDR(pLE)));                                     \
7302 +       }                                                                                                                                       \
7303 +       if ((Opcode & OP_ADDR64) == OP_ADDR64) {                                                        \
7304 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7305 +                       ("\tHighAddr: 0x%x\n", RXLE_GET_ADDR(pLE)));                            \
7306 +       }                                                                                                                                       \
7307 +       if ((Opcode & OP_TCPSTART) == OP_TCPSTART) {                                            \
7308 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7309 +                       ("\tTCP Sum Start 1 : 0x%x\n", RXLE_GET_STACS1(pLE)));          \
7310 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7311 +                       ("\tTCP Sum Start 2 : 0x%x\n", RXLE_GET_STACS2(pLE)));          \
7312 +       }                                                                                                                                       \
7313 +       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                          \
7314 +               ("=====================\n"));                                                                   \
7315 +}
7316 +
7317 +#define SK_DBG_DUMP_TX_LE(pLE) {                                                                               \
7318 +       SK_U8   Opcode;                                                                                                         \
7319 +       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                          \
7320 +               ("=== TX_LIST_ELEMENT @addr: %p cont: %02x %02x %02x %02x %02x %02x %02x %02x\n",       \
7321 +               pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\
7322 +               ((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5],             \
7323 +               ((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7]));                                               \
7324 +       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                          \
7325 +               ("\t (16bit) %04x %04x %04x %04x\n",                                                    \
7326 +               ((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2],  \
7327 +               ((SK_U16 *) pLE)[3]));                                                                                  \
7328 +       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                          \
7329 +               ("\t (32bit) %08x %08x\n",                                                                              \
7330 +               ((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1]));                                     \
7331 +       Opcode = TXLE_GET_OPC(pLE);                                                                                     \
7332 +       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                          \
7333 +               ("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == HW_OWNER) ?   \
7334 +               "Hardware" : "Software"));                                                                              \
7335 +       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                          \
7336 +               ("\tOpc: 0x%x ",Opcode));                                                                               \
7337 +       switch (Opcode & (~HW_OWNER)) {                                                                         \
7338 +       case OP_TCPCHKSUM:                                                                                                      \
7339 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7340 +                       ("\tOP_TCPCHKSUM\n"));                                                                          \
7341 +               break;                                                                                                                  \
7342 +       case OP_TCPIS:                                                                                                          \
7343 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7344 +                       ("\tOP_TCPIS\n"));                                                                                      \
7345 +               break;                                                                                                                  \
7346 +       case OP_TCPLCK:                                                                                                         \
7347 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7348 +                       ("\tOP_TCPLCK\n"));                                                                                     \
7349 +               break;                                                                                                                  \
7350 +       case OP_TCPLW:                                                                                                          \
7351 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7352 +                       ("\tOP_TCPLW\n"));                                                                                      \
7353 +               break;                                                                                                                  \
7354 +       case OP_TCPLSW:                                                                                                         \
7355 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7356 +                       ("\tOP_TCPLSW\n"));                                                                                     \
7357 +               break;                                                                                                                  \
7358 +       case OP_TCPLISW:                                                                                                        \
7359 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7360 +                       ("\tOP_TCPLISW\n"));                                                                            \
7361 +               break;                                                                                                                  \
7362 +       case OP_ADDR64:                                                                                                         \
7363 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7364 +                       ("\tOP_ADDR64\n"));                                                                                     \
7365 +               break;                                                                                                                  \
7366 +       case OP_VLAN:                                                                                                           \
7367 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7368 +                       ("\tOP_VLAN\n"));                                                                                       \
7369 +               break;                                                                                                                  \
7370 +       case OP_ADDR64VLAN:                                                                                                     \
7371 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7372 +                       ("\tOP_ADDR64VLAN\n"));                                                                         \
7373 +               break;                                                                                                                  \
7374 +       case OP_LRGLEN:                                                                                                         \
7375 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7376 +                       ("\tOP_LRGLEN\n"));                                                                                     \
7377 +               break;                                                                                                                  \
7378 +       case OP_LRGLENVLAN:                                                                                                     \
7379 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7380 +                       ("\tOP_LRGLENVLAN\n"));                                                                         \
7381 +               break;                                                                                                                  \
7382 +       case OP_BUFFER:                                                                                                         \
7383 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7384 +                       ("\tOP_BUFFER\n"));                                                                                     \
7385 +               break;                                                                                                                  \
7386 +       case OP_PACKET:                                                                                                         \
7387 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7388 +                       ("\tOP_PACKET\n"));                                                                                     \
7389 +               break;                                                                                                                  \
7390 +       case OP_LARGESEND:                                                                                                      \
7391 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7392 +                       ("\tOP_LARGESEND\n"));                                                                          \
7393 +               break;                                                                                                                  \
7394 +       case SW_OWNER:                                                                                                          \
7395 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7396 +                       ("\tunused LE\n"));                                                                                     \
7397 +               break;                                                                                                                  \
7398 +       default:                                                                                                                        \
7399 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7400 +                       ("\tunknown Opcode!!!\n"));                                                                     \
7401 +       }                                                                                                                                       \
7402 +       if ((Opcode & OP_BUFFER) == OP_BUFFER) {                                                        \
7403 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7404 +                       ("\tControl: 0x%x\n", TXLE_GET_CTRL(pLE)));                                     \
7405 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7406 +                       ("\tBufLen: 0x%x\n", TXLE_GET_LEN(pLE)));                                       \
7407 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7408 +                       ("\tLowAddr: 0x%x\n", TXLE_GET_ADDR(pLE)));                                     \
7409 +       }                                                                                                                                       \
7410 +       if ((Opcode & OP_ADDR64) == OP_ADDR64) {                                                        \
7411 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7412 +                       ("\tHighAddr: 0x%x\n", TXLE_GET_ADDR(pLE)));                            \
7413 +       }                                                                                                                                       \
7414 +       if ((Opcode & OP_VLAN) == OP_VLAN) {                                                            \
7415 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7416 +                       ("\tVLAN Id: 0x%x\n", TXLE_GET_VLAN(pLE)));                                     \
7417 +       }                                                                                                                                       \
7418 +       if ((Opcode & OP_LRGLEN) == OP_LRGLEN) {                                                        \
7419 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7420 +                       ("\tLarge send length: 0x%x\n", TXLE_GET_LSLEN(pLE)));          \
7421 +       }                                                                                                                                       \
7422 +       if ((Opcode &(~HW_OWNER)) <= OP_ADDR64) {                                                       \
7423 +               if ((Opcode & OP_TCPWRITE) == OP_TCPWRITE) {                                    \
7424 +                       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                          \
7425 +                               ("\tTCP Sum Write: 0x%x\n", TXLE_GET_WRICS(pLE)));              \
7426 +               }                                                                                                                               \
7427 +               if ((Opcode & OP_TCPSTART) == OP_TCPSTART) {                                    \
7428 +                       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                          \
7429 +                               ("\tTCP Sum Start: 0x%x\n", TXLE_GET_STACS(pLE)));              \
7430 +               }                                                                                                                               \
7431 +               if ((Opcode & OP_TCPINIT) == OP_TCPINIT) {                                              \
7432 +                       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                          \
7433 +                               ("\tTCP Sum Init: 0x%x\n", TXLE_GET_INICS(pLE)));               \
7434 +               }                                                                                                                               \
7435 +               if ((Opcode & OP_TCPLCK) == OP_TCPLCK) {                                                \
7436 +                       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                          \
7437 +                               ("\tTCP Sum Lock: 0x%x\n", TXLE_GET_LCKCS(pLE)));               \
7438 +               }                                                                                                                               \
7439 +       }                                                                                                                                       \
7440 +       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                          \
7441 +               ("=====================\n"));                                                                   \
7442 +}
7443 +
7444 +#define SK_DBG_DUMP_ST_LE(pLE) {                                                                               \
7445 +       SK_U8   Opcode;                                                                                                         \
7446 +       SK_U16  HighVal;                                                                                                        \
7447 +       SK_U32  LowVal;                                                                                                         \
7448 +       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                          \
7449 +               ("=== ST_LIST_ELEMENT @addr: %p contains: %02x %02x %02x %02x %02x %02x %02x %02x\n",\
7450 +               pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\
7451 +               ((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5],             \
7452 +               ((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7]));                                               \
7453 +       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                          \
7454 +               ("\t (16bit) %04x %04x %04x %04x\n",                                                    \
7455 +               ((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2],  \
7456 +               ((SK_U16 *) pLE)[3]));                                                                                  \
7457 +       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                          \
7458 +               ("\t (32bit) %08x %08x\n",                                                                              \
7459 +               ((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1]));                                             \
7460 +       Opcode = STLE_GET_OPC(pLE);                                                                                     \
7461 +       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                          \
7462 +               ("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == SW_OWNER) ?   \
7463 +               "Hardware" : "Software"));                                                                              \
7464 +       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                          \
7465 +               ("\tOpc: 0x%x", Opcode));                                                                               \
7466 +       Opcode &= (~HW_OWNER);                                                                                          \
7467 +       switch (Opcode) {                                                                                                       \
7468 +       case OP_RXSTAT:                                                                                                         \
7469 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7470 +                       ("\tOP_RXSTAT\n"));                                                                                     \
7471 +               break;                                                                                                                  \
7472 +       case OP_RXTIMESTAMP:                                                                                            \
7473 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7474 +                       ("\tOP_RXTIMESTAMP\n"));                                                                        \
7475 +               break;                                                                                                                  \
7476 +       case OP_RXVLAN:                                                                                                         \
7477 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7478 +                       ("\tOP_RXVLAN\n"));                                                                                     \
7479 +               break;                                                                                                                  \
7480 +       case OP_RXCHKS:                                                                                                         \
7481 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7482 +                       ("\tOP_RXCHKS\n"));                                                                                     \
7483 +               break;                                                                                                                  \
7484 +       case OP_RXCHKSVLAN:                                                                                                     \
7485 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7486 +                       ("\tOP_RXCHKSVLAN\n"));                                                                         \
7487 +               break;                                                                                                                  \
7488 +       case OP_RXTIMEVLAN:                                                                                                     \
7489 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7490 +                       ("\tOP_RXTIMEVLAN\n"));                                                                         \
7491 +               break;                                                                                                                  \
7492 +       case OP_RSS_HASH:                                                                                                       \
7493 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7494 +                       ("\tOP_RSS_HASH\n"));                                                                           \
7495 +               break;                                                                                                                  \
7496 +       case OP_TXINDEXLE:                                                                                                      \
7497 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7498 +                       ("\tOP_TXINDEXLE\n"));                                                                          \
7499 +               break;                                                                                                                  \
7500 +       case HW_OWNER:                                                                                                          \
7501 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7502 +                       ("\tunused LE\n"));                                                                                     \
7503 +               break;                                                                                                                  \
7504 +       default:                                                                                                                        \
7505 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7506 +                       ("\tunknown status list element!!!\n"));                                        \
7507 +       }                                                                                                                                       \
7508 +       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                          \
7509 +               ("\tPort: %c\n", 'A' + STLE_GET_LINK(pLE)));                                    \
7510 +       if (Opcode == OP_RXSTAT) {                                                                                      \
7511 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7512 +                       ("\tFrameLen: 0x%x\n", STLE_GET_LEN(pLE)));                                     \
7513 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7514 +                       ("\tFrameStat: 0x%x\n", STLE_GET_FRSTATUS(pLE)));                       \
7515 +       }                                                                                                                                       \
7516 +       if ((Opcode & OP_RXVLAN) == OP_RXVLAN) {                                                        \
7517 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7518 +                       ("\tVLAN Id: 0x%x\n", STLE_GET_VLAN(pLE)));                                     \
7519 +       }                                                                                                                                       \
7520 +       if ((Opcode & OP_RXTIMESTAMP) == OP_RXTIMESTAMP) {                                      \
7521 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7522 +                       ("\tTimestamp: 0x%x\n", STLE_GET_TIST(pLE)));                           \
7523 +       }                                                                                                                                       \
7524 +       if ((Opcode & OP_RXCHKS) == OP_RXCHKS) {                                                        \
7525 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7526 +                       ("\tTCP: 0x%x 0x%x\n", STLE_GET_TCP1(pLE),                                      \
7527 +                       STLE_GET_TCP2(pLE)));                                                                           \
7528 +       }                                                                                                                                       \
7529 +       if (Opcode == OP_TXINDEXLE) {                                                                           \
7530 +               STLE_GET_DONE_IDX(pLE, LowVal, HighVal);                                                \
7531 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7532 +                       ("\tTx Index TxA1: 0x%x\n",                                                                     \
7533 +                       STLE_GET_DONE_IDX_TXA1(LowVal,HighVal)));                                       \
7534 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7535 +                       ("\tTx Index TxS1: 0x%x\n",                                                                     \
7536 +                       STLE_GET_DONE_IDX_TXS1(LowVal,HighVal)));                                       \
7537 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7538 +                       ("\tTx Index TxA2: 0x%x\n",                                                                     \
7539 +                       STLE_GET_DONE_IDX_TXA2(LowVal,HighVal)));                                       \
7540 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7541 +                       ("\tTx Index TxS2: 0x%x\n",                                                                     \
7542 +                       STLE_GET_DONE_IDX_TXS2(LowVal,HighVal)));                                       \
7543 +       }                                                                                                                                       \
7544 +       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                          \
7545 +               ("=====================\n"));                                                                   \
7546 +}
7547 +
7548 +#ifdef USE_POLLING_UNIT
7549 +#define SK_DBG_DUMP_PO_LE(pLE) {                                                                               \
7550 +       SK_U8   Opcode;                                                                                                         \
7551 +       SK_U16  Idx;                                                                                                            \
7552 +       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                          \
7553 +               ("=== PO_LIST_ELEMENT @addr: %p cont: %02x %02x %02x %02x %02x %02x %02x %02x\n",       \
7554 +               pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\
7555 +               ((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5],             \
7556 +               ((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7]));                                               \
7557 +       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                          \
7558 +               ("\t (16bit) %04x %04x %04x %04x\n",                                                    \
7559 +               ((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2],  \
7560 +               ((SK_U16 *) pLE)[3]));                                                                                  \
7561 +       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                          \
7562 +               ("\t (32bit) %08x %08x\n",                                                                              \
7563 +               ((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1]));                                             \
7564 +       Opcode = POLE_GET_OPC(pLE);                                                                                     \
7565 +       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                          \
7566 +                ("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == HW_OWNER) ?  \
7567 +                 "Hardware" : "Software"));                                                                    \
7568 +       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                          \
7569 +                ("\tOpc: 0x%x ",Opcode));                                                                              \
7570 +       if ((Opcode & ~HW_OWNER) == OP_PUTIDX) {                                                        \
7571 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7572 +                       ("\tOP_PUTIDX\n"));                                                                                     \
7573 +       }                                                                                                                                       \
7574 +       else {                                                                                                                          \
7575 +               SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                  \
7576 +                       ("\tunknown Opcode!!!\n"));                                                                     \
7577 +       }                                                                                                                                       \
7578 +       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                          \
7579 +               ("\tPort %c\n", 'A' + POLE_GET_LINK(pLE)));                                             \
7580 +       Idx = POLE_GET_TXAIDX(pLE);                                                                                     \
7581 +       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                          \
7582 +               ("\tTxA Index is 0x%X and %svalid\n", Idx,                                              \
7583 +               (Idx & PU_PUTIDX_VALID) ? "" : "not "));                                                \
7584 +       Idx = POLE_GET_TXSIDX(pLE);                                                                                     \
7585 +       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                          \
7586 +               ("\tTxS Index is 0x%X and %svalid\n", Idx,                                              \
7587 +               (Idx & PU_PUTIDX_VALID) ? "" : "not "));                                                \
7588 +       Idx = POLE_GET_RXIDX(pLE);                                                                                      \
7589 +       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                          \
7590 +               ("\tRx Index is 0x%X and %svalid\n", Idx,                                               \
7591 +               (Idx & PU_PUTIDX_VALID) ? "" : "not "));                                                \
7592 +       SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT,                                          \
7593 +               ("=====================\n"));                                                                   \
7594 +}
7595 +#endif /* USE_POLLING_UNIT */
7596 +
7597 +#else  /* !DEBUG */
7598 +
7599 +#define SK_DBG_DUMP_RX_LE(pLE)
7600 +#define SK_DBG_DUMP_TX_LE(pLE)
7601 +#define SK_DBG_DUMP_ST_LE(pLE)
7602 +#define SK_DBG_DUMP_PO_LE(pLE)
7603 +
7604 +#endif /* !DEBUG */
7605 +
7606 +/******************************************************************************
7607 + *
7608 + * Macros for listelement tables
7609 + *
7610 + *
7611 + */
7612 +
7613 +#define LE_SIZE sizeof(SK_HWLE)
7614 +#define LE_TAB_SIZE(NumElements)       ((NumElements) * LE_SIZE)
7615 +
7616 +/* Number of unused list elements in table
7617 + * this macro always returns the number of free listelements - 1
7618 + * this way we want to guarantee that always one LE remains unused
7619 + */
7620 +#define NUM_FREE_LE_IN_TABLE(pTable)                                                           \
7621 +       ( ((pTable)->Put >= (pTable)->Done) ?                                                   \
7622 +       (NUM_LE_IN_TABLE(pTable) - (pTable)->Put + (pTable)->Done - 1) :\
7623 +       ((pTable)->Done - (pTable)->Put - 1) )
7624 +
7625 +/* total number of list elements in table */
7626 +#define NUM_LE_IN_TABLE(pTable)                ((pTable)->Num)
7627 +
7628 +/* get next unused Rx list element */
7629 +#define GET_RX_LE(pLE, pTable) {                                                                       \
7630 +       pLE = &(pTable)->pLETab[(pTable)->Put];                                                 \
7631 +       (pTable)->Put = ((pTable)->Put + 1) & (NUM_LE_IN_TABLE(pTable) - 1);\
7632 +}
7633 +
7634 +/* get next unused Tx list element */
7635 +#define GET_TX_LE(pLE, pTable) GET_RX_LE(pLE, pTable)
7636 +
7637 +/* get next status list element expected to be finished by hw */
7638 +#define GET_ST_LE(pLE, pTable) {                                                                       \
7639 +       pLE = &(pTable)->pLETab[(pTable)->Done];                                                \
7640 +               (pTable)->Done = ((pTable)->Done +1) & (NUM_LE_IN_TABLE(pTable) - 1);\
7641 +}
7642 +
7643 +#ifdef USE_POLLING_UNIT
7644 +/* get next polling unit list element for port */
7645 +#define GET_PO_LE(pLE, pTable, Port) {                                                         \
7646 +       pLE = &(pTable)->pLETab[(Port)];                                                                \
7647 +}
7648 +#endif /* USE_POLLING_UNIT */
7649 +
7650 +#define GET_PUT_IDX(pTable)                    ((pTable)->Put)
7651 +
7652 +#define UPDATE_HWPUT_IDX(pTable)       {(pTable)->HwPut = (pTable)->Put; }
7653 +
7654 +/*
7655 + * get own bit of next status LE
7656 + * if the result is != 0 there has been at least one status LE finished
7657 + */
7658 +#define OWN_OF_FIRST_LE(pTable)                                                                        \
7659 +       (STLE_GET_OPC(&(pTable)->pLETab[(pTable)->Done]) & HW_OWNER)
7660 +
7661 +#define SET_DONE_INDEX(pTable, Idx)    (pTable)->Done = (Idx);
7662 +
7663 +#define GET_DONE_INDEX(pTable) ((pTable)->Done)
7664 +
7665 +#ifdef SAFE_BUT_SLOW
7666 +
7667 +/* check own bit of LE before current done idx */
7668 +#define CHECK_STLE_OVERFLOW(pTable, IsOk) {                                            \
7669 +               unsigned i;                                                                                             \
7670 +               if ((i = (pTable)->Done) == 0) {                                                \
7671 +                       i = NUM_LE_IN_TABLE(pTable);                                            \
7672 +               }                                                                                                               \
7673 +               else {                                                                                                  \
7674 +                       i = i - 1;                                                                                      \
7675 +               }                                                                                                               \
7676 +               if (STLE_GET_OPC(&(pTable)->pLETab[i]) == HW_OWNER) {   \
7677 +                       (IsOk) = SK_TRUE;                                                                       \
7678 +               }                                                                                                               \
7679 +               else {                                                                                                  \
7680 +                       (IsOk) = SK_FALSE;                                                                      \
7681 +               }                                                                                                               \
7682 +       }
7683 +
7684 +
7685 +/*
7686 + * for Yukon-2 the hardware is not polling the list elements, so it
7687 + * is not necessary to change the own-bit of Rx or Tx LEs before
7688 + * reusing them
7689 + * but it might make debugging easier if one simply can see whether
7690 + * a LE has been worked on
7691 + */
7692 +
7693 +#define CLEAR_LE_OWN(pTable, Idx)                                                              \
7694 +       STLE_SET_OPC(&(pTable)->pLETab[(Idx)], SW_OWNER)
7695 +
7696 +/*
7697 + * clear all own bits starting from old done index up to the LE before
7698 + * the new done index
7699 + */
7700 +#define CLEAR_LE_OWN_FROM_DONE_TO(pTable, To) {                                        \
7701 +               int i;                                                                                                  \
7702 +               i = (pTable)->Done;                                                                             \
7703 +               while (i != To) {                                                                               \
7704 +                       CLEAR_LE_OWN(pTable, i);                                                        \
7705 +                       i = (i + 1) & (NUM_LE_IN_TABLE(pTable) - 1);            \
7706 +               }                                                                                                               \
7707 +       }
7708 +
7709 +#else  /* !SAFE_BUT_SLOW */
7710 +
7711 +#define CHECK_STLE_OVERFLOW(pTable, IsOk)
7712 +#define CLEAR_LE_OWN(pTable, Idx)
7713 +#define CLEAR_LE_OWN_FROM_DONE_TO(pTable, To)
7714 +
7715 +#endif /* !SAFE_BUT_SLOW */
7716 +
7717 +
7718 +/* typedefs *******************************************************************/
7719 +
7720 +typedef struct s_LetRxTx {
7721 +       SK_U16  VlanId;                 /* VLAN Id given down last time */
7722 +       SK_U16  TcpWp;                  /* TCP Checksum Write Position */
7723 +       SK_U16  TcpSp1;                 /* TCP Checksum Calculation Start Position 1 */
7724 +       SK_U16  TcpSp2;                 /* TCP Checksum Calculation Start Position 2 */
7725 +       SK_U16  MssValue;               /* Maximum Segment Size */
7726 +       SK_U16  Reserved1;              /* reserved word for furture extensions */
7727 +       SK_U16  Reserved2;              /* reserved word for furture extensions */
7728 +       SK_U16  Reserved3;              /* reserved word for furture extensions */
7729 +} SK_LET_RX_TX;
7730 +
7731 +typedef struct s_LetStat {
7732 +       SK_U32  RxTimeStamp;    /* Receive Timestamp */
7733 +       SK_U32  RssHashValue;   /* RSS Hash Value */
7734 +       SK_BOOL RssIsIp;                /* RSS Hash Value: IP packet detected */
7735 +       SK_BOOL RssIsTcp;               /* RSS Hash Value: IP+TCP packet detected */
7736 +       SK_U16  VlanId;                 /* VLAN Id given received by Status BMU */
7737 +       SK_U16  TcpSum1;                /* TCP checksum 1 (status BMU) */
7738 +       SK_U16  TcpSum2;                /* TCP checksum 2 (status BMU) */
7739 +} SK_LET_STAT;
7740 +
7741 +typedef union s_LetBmuSpec {
7742 +       SK_LET_RX_TX    RxTx;   /* Rx/Tx BMU specific variables */
7743 +       SK_LET_STAT             Stat;   /* Status BMU specific variables */
7744 +} SK_LET_BMU_S;
7745 +
7746 +typedef        struct s_le_table {
7747 +       /* all LE's between Done and HWPut are owned by the hardware */
7748 +       /* all LE's between Put and Done can be used from software */
7749 +       /* all LE's between HWPut and Put are currently processed in DriverSend */
7750 +       unsigned Done;                  /* done index - consumed from HW and available */
7751 +       unsigned Put;                   /* put index - to be given to hardware */
7752 +       unsigned HwPut;                 /* put index actually given to hardware */
7753 +       unsigned Num;                   /* total number of list elements */
7754 +       SK_HWLE *pLETab;                /* virtual address of list element table */
7755 +       SK_U32  pPhyLETABLow;   /* physical address of list element table */
7756 +       SK_U32  pPhyLETABHigh;  /* physical address of list element table */
7757 +       /* values to remember in order to save some LEs */
7758 +       SK_U32  BufHighAddr;    /* high address given down last time */
7759 +       SK_LET_BMU_S Bmu;               /* contains BMU specific information */
7760 +       SK_U32  Private;                /* driver private variable free usable */
7761 +       SK_U16  TcpInitCsum;    /* init checksum */
7762 +} SK_LE_TABLE;
7763 +
7764 +/* function prototypes ********************************************************/
7765 +
7766 +#ifndef        SK_KR_PROTO
7767 +
7768 +/*
7769 + * public functions in sky2le.c
7770 + */
7771 +extern void SkGeY2SetPutIndex(
7772 +       SK_AC   *pAC,
7773 +       SK_IOC  IoC,
7774 +       SK_U32  StartAddrPrefetchUnit,
7775 +       SK_LE_TABLE *pLETab);
7776 +
7777 +extern void SkGeY2InitPrefetchUnit(
7778 +       SK_AC   *pAC,
7779 +       SK_IOC  IoC,
7780 +       unsigned int Queue,
7781 +       SK_LE_TABLE *pLETab);
7782 +
7783 +extern void SkGeY2InitStatBmu(
7784 +       SK_AC   *pAC,
7785 +       SK_IOC  IoC,
7786 +       SK_LE_TABLE *pLETab);
7787 +
7788 +extern void SkGeY2InitPollUnit(
7789 +       SK_AC   *pAC,
7790 +       SK_IOC  IoC,
7791 +       SK_LE_TABLE *pLETab);
7792 +
7793 +extern void SkGeY2InitSingleLETable(
7794 +       SK_AC   *pAC,
7795 +       SK_LE_TABLE *pLETab,
7796 +       unsigned int NumLE,
7797 +       void    *pVMem,
7798 +       SK_U32  PMemLowAddr,
7799 +       SK_U32  PMemHighAddr);
7800 +
7801 +#else  /* SK_KR_PROTO */
7802 +extern void SkGeY2SetPutIndex();
7803 +extern void SkGeY2InitPrefetchUnit();
7804 +extern void SkGeY2InitStatBmu();
7805 +extern void SkGeY2InitPollUnit();
7806 +extern void SkGeY2InitSingleLETable();
7807 +#endif /* SK_KR_PROTO */
7808 +
7809 +#ifdef __cplusplus
7810 +}
7811 +#endif /* __cplusplus */
7812 +
7813 +#endif /* __INC_SKY2LE_H */
7814 +
7815 diff -ruN linux/drivers/net/sk98lin/h/xmac_ii.h linux-new/drivers/net/sk98lin/h/xmac_ii.h
7816 --- linux/drivers/net/sk98lin/h/xmac_ii.h       2006-09-20 05:42:06.000000000 +0200
7817 +++ linux-new/drivers/net/sk98lin/h/xmac_ii.h   2006-07-28 14:13:54.000000000 +0200
7818 @@ -2,23 +2,24 @@
7819   *
7820   * Name:       xmac_ii.h
7821   * Project:    Gigabit Ethernet Adapters, Common Modules
7822 - * Version:    $Revision$
7823 - * Date:       $Date$
7824 + * Version:    $Revision$
7825 + * Date:       $Date$
7826   * Purpose:    Defines and Macros for Gigabit Ethernet Controller
7827   *
7828   ******************************************************************************/
7829
7830  /******************************************************************************
7831   *
7832 + *     LICENSE:
7833   *     (C)Copyright 1998-2002 SysKonnect.
7834 - *     (C)Copyright 2002-2003 Marvell.
7835 + *     (C)Copyright 2002-2006 Marvell.
7836   *
7837   *     This program is free software; you can redistribute it and/or modify
7838   *     it under the terms of the GNU General Public License as published by
7839   *     the Free Software Foundation; either version 2 of the License, or
7840   *     (at your option) any later version.
7841 - *
7842   *     The information in this file is provided "AS IS" without warranty.
7843 + *     /LICENSE
7844   *
7845   ******************************************************************************/
7846
7847 @@ -371,18 +372,18 @@
7848                                                                 /* Bit 16..6:   reserved */
7849  #define XM_SC_SNP_RXC  (1<<5)  /* Bit  5: (sc) Snap Rx Counters */
7850  #define XM_SC_SNP_TXC  (1<<4)  /* Bit  4: (sc) Snap Tx Counters */
7851 -#define XM_SC_CP_RXC   (1<<3)  /* Bit  3:      Copy Rx Counters Continuously */
7852 +#define XM_SC_CP_RXC   (1<<3)  /* Bit  3:      Copy Rx Counters Continuously */
7853  #define XM_SC_CP_TXC   (1<<2)  /* Bit  2:      Copy Tx Counters Continuously */
7854  #define XM_SC_CLR_RXC  (1<<1)  /* Bit  1: (sc) Clear Rx Counters */
7855 -#define XM_SC_CLR_TXC  (1<<0)  /* Bit  0: (sc) Clear Tx Counters */
7856 +#define XM_SC_CLR_TXC  (1<<0)  /* Bit  0: (sc) Clear Tx Counters */
7857
7858
7859  /*     XM_RX_CNT_EV    32 bit r/o      Rx Counter Event Register */
7860  /*     XM_RX_EV_MSK    32 bit r/w      Rx Counter Event Mask */
7861 -#define XMR_MAX_SZ_OV  (1UL<<31)       /* Bit 31:      1024-MaxSize Rx Cnt Ov*/
7862 -#define XMR_1023B_OV   (1L<<30)        /* Bit 30:      512-1023Byte Rx Cnt Ov*/
7863 -#define XMR_511B_OV            (1L<<29)        /* Bit 29:      256-511 Byte Rx Cnt Ov*/
7864 -#define XMR_255B_OV            (1L<<28)        /* Bit 28:      128-255 Byte Rx Cnt Ov*/
7865 +#define XMR_MAX_SZ_OV  (1UL<<31)       /* Bit 31:      1024-MaxSize Rx Cnt Ov */
7866 +#define XMR_1023B_OV   (1L<<30)        /* Bit 30:      512-1023Byte Rx Cnt Ov */
7867 +#define XMR_511B_OV            (1L<<29)        /* Bit 29:      256-511 Byte Rx Cnt Ov */
7868 +#define XMR_255B_OV            (1L<<28)        /* Bit 28:      128-255 Byte Rx Cnt Ov */
7869  #define XMR_127B_OV            (1L<<27)        /* Bit 27:      65-127 Byte Rx Cnt Ov */
7870  #define XMR_64B_OV             (1L<<26)        /* Bit 26:      64 Byte Rx Cnt Ov */
7871  #define XMR_UTIL_OV            (1L<<25)        /* Bit 25:      Rx Util Cnt Overflow */
7872 @@ -390,9 +391,9 @@
7873  #define XMR_CEX_ERR_OV (1L<<23)        /* Bit 23:      CEXT Err Cnt Ov */
7874                                                                         /* Bit 22:      reserved */
7875  #define XMR_FCS_ERR_OV (1L<<21)        /* Bit 21:      Rx FCS Error Cnt Ov */
7876 -#define XMR_LNG_ERR_OV (1L<<20)        /* Bit 20:      Rx too Long Err Cnt Ov*/
7877 +#define XMR_LNG_ERR_OV (1L<<20)        /* Bit 20:      Rx too Long Err Cnt Ov */
7878  #define XMR_RUNT_OV            (1L<<19)        /* Bit 19:      Runt Event Cnt Ov */
7879 -#define XMR_SHT_ERR_OV (1L<<18)        /* Bit 18:      Rx Short Ev Err Cnt Ov*/
7880 +#define XMR_SHT_ERR_OV (1L<<18)        /* Bit 18:      Rx Short Ev Err Cnt Ov */
7881  #define XMR_SYM_ERR_OV (1L<<17)        /* Bit 17:      Rx Sym Err Cnt Ov */
7882                                                                         /* Bit 16:      reserved */
7883  #define XMR_CAR_ERR_OV (1L<<15)        /* Bit 15:      Rx Carr Ev Err Cnt Ov */
7884 @@ -401,57 +402,57 @@
7885  #define XMR_FRA_ERR_OV (1L<<12)        /* Bit 12:      Rx Framing Err Cnt Ov */
7886  #define XMR_FMISS_OV   (1L<<11)        /* Bit 11:      Rx Missed Ev Cnt Ov */
7887  #define XMR_BURST              (1L<<10)        /* Bit 10:      Rx Burst Event Cnt Ov */
7888 -#define XMR_INV_MOC            (1L<<9)         /* Bit  9:      Rx with inv. MAC OC Ov*/
7889 +#define XMR_INV_MOC            (1L<<9)         /* Bit  9:      Rx with inv. MAC OC Ov */
7890  #define XMR_INV_MP             (1L<<8)         /* Bit  8:      Rx inv Pause Frame Ov */
7891  #define XMR_MCTRL_OV   (1L<<7)         /* Bit  7:      Rx MAC Ctrl-F Cnt Ov */
7892 -#define XMR_MPAUSE_OV  (1L<<6)         /* Bit  6:      Rx Pause MAC Ctrl-F Ov*/
7893 -#define XMR_UC_OK_OV   (1L<<5)         /* Bit  5:      Rx Unicast Frame CntOv*/
7894 +#define XMR_MPAUSE_OV  (1L<<6)         /* Bit  6:      Rx Pause MAC Ctrl-F Ov */
7895 +#define XMR_UC_OK_OV   (1L<<5)         /* Bit  5:      Rx Unicast Frame Cnt Ov */
7896  #define XMR_MC_OK_OV   (1L<<4)         /* Bit  4:      Rx Multicast Cnt Ov */
7897  #define XMR_BC_OK_OV   (1L<<3)         /* Bit  3:      Rx Broadcast Cnt Ov */
7898 -#define XMR_OK_LO_OV   (1L<<2)         /* Bit  2:      Octets Rx OK Low CntOv*/
7899 -#define XMR_OK_HI_OV   (1L<<1)         /* Bit  1:      Octets Rx OK Hi Cnt Ov*/
7900 -#define XMR_OK_OV              (1L<<0)         /* Bit  0:      Frames Received Ok Ov */
7901 +#define XMR_OK_LO_OV   (1L<<2)         /* Bit  2:      Octets Rx OK Low Cnt Ov */
7902 +#define XMR_OK_HI_OV   (1L<<1)         /* Bit  1:      Octets Rx OK High Cnt Ov */
7903 +#define XMR_OK_OV              (1L<<0)         /* Bit  0:      Frames Received OK Ov */
7904
7905  #define XMR_DEF_MSK            (XMR_OK_LO_OV | XMR_OK_HI_OV)
7906
7907  /*     XM_TX_CNT_EV    32 bit r/o      Tx Counter Event Register */
7908  /*     XM_TX_EV_MSK    32 bit r/w      Tx Counter Event Mask */
7909                                                                         /* Bit 31..26:  reserved */
7910 -#define XMT_MAX_SZ_OV  (1L<<25)        /* Bit 25:      1024-MaxSize Tx Cnt Ov*/
7911 -#define XMT_1023B_OV   (1L<<24)        /* Bit 24:      512-1023Byte Tx Cnt Ov*/
7912 -#define XMT_511B_OV            (1L<<23)        /* Bit 23:      256-511 Byte Tx Cnt Ov*/
7913 -#define XMT_255B_OV            (1L<<22)        /* Bit 22:      128-255 Byte Tx Cnt Ov*/
7914 +#define XMT_MAX_SZ_OV  (1L<<25)        /* Bit 25:      1024-MaxSize Tx Cnt Ov */
7915 +#define XMT_1023B_OV   (1L<<24)        /* Bit 24:      512-1023Byte Tx Cnt Ov */
7916 +#define XMT_511B_OV            (1L<<23)        /* Bit 23:      256-511 Byte Tx Cnt Ov */
7917 +#define XMT_255B_OV            (1L<<22)        /* Bit 22:      128-255 Byte Tx Cnt Ov */
7918  #define XMT_127B_OV            (1L<<21)        /* Bit 21:      65-127 Byte Tx Cnt Ov */
7919  #define XMT_64B_OV             (1L<<20)        /* Bit 20:      64 Byte Tx Cnt Ov */
7920  #define XMT_UTIL_OV            (1L<<19)        /* Bit 19:      Tx Util Cnt Overflow */
7921  #define XMT_UTIL_UR            (1L<<18)        /* Bit 18:      Tx Util Cnt Underrun */
7922 -#define XMT_CS_ERR_OV  (1L<<17)        /* Bit 17:      Tx Carr Sen Err Cnt Ov*/
7923 +#define XMT_CS_ERR_OV  (1L<<17)        /* Bit 17:      Tx Carr Sen Err Cnt Ov */
7924  #define XMT_FIFO_UR_OV (1L<<16)        /* Bit 16:      Tx FIFO Ur Ev Cnt Ov */
7925  #define XMT_EX_DEF_OV  (1L<<15)        /* Bit 15:      Tx Ex Deferall Cnt Ov */
7926  #define XMT_DEF                        (1L<<14)        /* Bit 14:      Tx Deferred Cnt Ov */
7927  #define XMT_LAT_COL_OV (1L<<13)        /* Bit 13:      Tx Late Col Cnt Ov */
7928 -#define XMT_ABO_COL_OV (1L<<12)        /* Bit 12:      Tx abo dueto Ex Col Ov*/
7929 +#define XMT_ABO_COL_OV (1L<<12)        /* Bit 12:      Tx abo dueto Ex Col Ov */
7930  #define XMT_MUL_COL_OV (1L<<11)        /* Bit 11:      Tx Mult Col Cnt Ov */
7931  #define XMT_SNG_COL            (1L<<10)        /* Bit 10:      Tx Single Col Cnt Ov */
7932 -#define XMT_MCTRL_OV   (1L<<9)         /* Bit  9:      Tx MAC Ctrl Counter Ov*/
7933 -#define XMT_MPAUSE             (1L<<8)         /* Bit  8:      Tx Pause MAC Ctrl-F Ov*/
7934 +#define XMT_MCTRL_OV   (1L<<9)         /* Bit  9:      Tx MAC Ctrl Counter Ov */
7935 +#define XMT_MPAUSE             (1L<<8)         /* Bit  8:      Tx Pause MAC Ctrl-F Ov */
7936  #define XMT_BURST              (1L<<7)         /* Bit  7:      Tx Burst Event Cnt Ov */
7937  #define XMT_LONG               (1L<<6)         /* Bit  6:      Tx Long Frame Cnt Ov */
7938  #define XMT_UC_OK_OV   (1L<<5)         /* Bit  5:      Tx Unicast Cnt Ov */
7939  #define XMT_MC_OK_OV   (1L<<4)         /* Bit  4:      Tx Multicast Cnt Ov */
7940  #define XMT_BC_OK_OV   (1L<<3)         /* Bit  3:      Tx Broadcast Cnt Ov */
7941 -#define XMT_OK_LO_OV   (1L<<2)         /* Bit  2:      Octets Tx OK Low CntOv*/
7942 -#define XMT_OK_HI_OV   (1L<<1)         /* Bit  1:      Octets Tx OK Hi Cnt Ov*/
7943 -#define XMT_OK_OV              (1L<<0)         /* Bit  0:      Frames Tx Ok Ov */
7944 +#define XMT_OK_LO_OV   (1L<<2)         /* Bit  2:      Octets Tx OK Low Cnt Ov */
7945 +#define XMT_OK_HI_OV   (1L<<1)         /* Bit  1:      Octets Tx OK High Cnt Ov */
7946 +#define XMT_OK_OV              (1L<<0)         /* Bit  0:      Frames Tx OK Ov */
7947
7948  #define XMT_DEF_MSK            (XMT_OK_LO_OV | XMT_OK_HI_OV)
7949
7950  /*
7951   * Receive Frame Status Encoding
7952   */
7953 -#define XMR_FS_LEN     (0x3fffUL<<18)  /* Bit 31..18:  Rx Frame Length */
7954 -#define XMR_FS_2L_VLAN (1L<<17)        /* Bit 17:      tagged wh 2Lev VLAN ID*/
7955 -#define XMR_FS_1L_VLAN (1L<<16)        /* Bit 16:      tagged wh 1Lev VLAN ID*/
7956 +#define XMR_FS_LEN_MSK (0x3fffUL<<18)  /* Bit 31..18:  Rx Frame Length */
7957 +#define XMR_FS_2L_VLAN (1L<<17)        /* Bit 17:      Tagged wh 2Lev VLAN ID */
7958 +#define XMR_FS_1L_VLAN (1L<<16)        /* Bit 16:      Tagged wh 1Lev VLAN ID */
7959  #define XMR_FS_BC              (1L<<15)        /* Bit 15:      Broadcast Frame */
7960  #define XMR_FS_MC              (1L<<14)        /* Bit 14:      Multicast Frame */
7961  #define XMR_FS_UC              (1L<<13)        /* Bit 13:      Unicast Frame */
7962 @@ -469,6 +470,8 @@
7963  #define XMR_FS_ERR             (1L<<1)         /* Bit  1:      Frame Error */
7964  #define XMR_FS_MCTRL   (1L<<0)         /* Bit  0:      MAC Control Packet */
7965
7966 +#define XMR_FS_LEN_SHIFT       18
7967 +
7968  /*
7969   * XMR_FS_ERR will be set if
7970   *     XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT,
7971 @@ -488,7 +491,7 @@
7972  #define PHY_XMAC_ID0           0x02    /* 16 bit r/o   PHY ID0 Register */
7973  #define PHY_XMAC_ID1           0x03    /* 16 bit r/o   PHY ID1 Register */
7974  #define PHY_XMAC_AUNE_ADV      0x04    /* 16 bit r/w   Auto-Neg. Advertisement */
7975 -#define PHY_XMAC_AUNE_LP       0x05    /* 16 bit r/o   Link Partner Abi Reg */
7976 +#define PHY_XMAC_AUNE_LP       0x05    /* 16 bit r/o   Link Partner Ability Reg */
7977  #define PHY_XMAC_AUNE_EXP      0x06    /* 16 bit r/o   Auto-Neg. Expansion Reg */
7978  #define PHY_XMAC_NEPG          0x07    /* 16 bit r/w   Next Page Register */
7979  #define PHY_XMAC_NEPG_LP       0x08    /* 16 bit r/o   Next Page Link Partner */
7980 @@ -505,12 +508,12 @@
7981  #define PHY_BCOM_ID0           0x02    /* 16 bit r/o   PHY ID0 Register */
7982  #define PHY_BCOM_ID1           0x03    /* 16 bit r/o   PHY ID1 Register */
7983  #define PHY_BCOM_AUNE_ADV      0x04    /* 16 bit r/w   Auto-Neg. Advertisement */
7984 -#define PHY_BCOM_AUNE_LP       0x05    /* 16 bit r/o   Link Part Ability Reg */
7985 +#define PHY_BCOM_AUNE_LP       0x05    /* 16 bit r/o   Link Partner Ability Reg */
7986  #define PHY_BCOM_AUNE_EXP      0x06    /* 16 bit r/o   Auto-Neg. Expansion Reg */
7987  #define PHY_BCOM_NEPG          0x07    /* 16 bit r/w   Next Page Register */
7988  #define PHY_BCOM_NEPG_LP       0x08    /* 16 bit r/o   Next Page Link Partner */
7989         /* Broadcom-specific registers */
7990 -#define PHY_BCOM_1000T_CTRL    0x09    /* 16 bit r/w   1000Base-T Ctrl Reg */
7991 +#define PHY_BCOM_1000T_CTRL    0x09    /* 16 bit r/w   1000Base-T Control Reg */
7992  #define PHY_BCOM_1000T_STAT    0x0a    /* 16 bit r/o   1000Base-T Status Reg */
7993         /* 0x0b - 0x0e:         reserved */
7994  #define PHY_BCOM_EXT_STAT      0x0f    /* 16 bit r/o   Extended Status Reg */
7995 @@ -536,29 +539,37 @@
7996  #define PHY_MARV_ID0           0x02    /* 16 bit r/o   PHY ID0 Register */
7997  #define PHY_MARV_ID1           0x03    /* 16 bit r/o   PHY ID1 Register */
7998  #define PHY_MARV_AUNE_ADV      0x04    /* 16 bit r/w   Auto-Neg. Advertisement */
7999 -#define PHY_MARV_AUNE_LP       0x05    /* 16 bit r/o   Link Part Ability Reg */
8000 +#define PHY_MARV_AUNE_LP       0x05    /* 16 bit r/o   Link Partner Ability Reg */
8001  #define PHY_MARV_AUNE_EXP      0x06    /* 16 bit r/o   Auto-Neg. Expansion Reg */
8002  #define PHY_MARV_NEPG          0x07    /* 16 bit r/w   Next Page Register */
8003  #define PHY_MARV_NEPG_LP       0x08    /* 16 bit r/o   Next Page Link Partner */
8004         /* Marvel-specific registers */
8005 -#define PHY_MARV_1000T_CTRL    0x09    /* 16 bit r/w   1000Base-T Ctrl Reg */
8006 +#define PHY_MARV_1000T_CTRL    0x09    /* 16 bit r/w   1000Base-T Control Reg */
8007  #define PHY_MARV_1000T_STAT    0x0a    /* 16 bit r/o   1000Base-T Status Reg */
8008         /* 0x0b - 0x0e:         reserved */
8009  #define PHY_MARV_EXT_STAT      0x0f    /* 16 bit r/o   Extended Status Reg */
8010 -#define PHY_MARV_PHY_CTRL      0x10    /* 16 bit r/w   PHY Specific Ctrl Reg */
8011 -#define PHY_MARV_PHY_STAT      0x11    /* 16 bit r/o   PHY Specific Stat Reg */
8012 +#define PHY_MARV_PHY_CTRL      0x10    /* 16 bit r/w   PHY Specific Control Reg */
8013 +#define PHY_MARV_PHY_STAT      0x11    /* 16 bit r/o   PHY Specific Status Reg */
8014  #define PHY_MARV_INT_MASK      0x12    /* 16 bit r/w   Interrupt Mask Reg */
8015  #define PHY_MARV_INT_STAT      0x13    /* 16 bit r/o   Interrupt Status Reg */
8016  #define PHY_MARV_EXT_CTRL      0x14    /* 16 bit r/w   Ext. PHY Specific Ctrl */
8017  #define PHY_MARV_RXE_CNT       0x15    /* 16 bit r/w   Receive Error Counter */
8018  #define PHY_MARV_EXT_ADR       0x16    /* 16 bit r/w   Ext. Ad. for Cable Diag. */
8019 -       /* 0x17:                reserved */
8020 +#define PHY_MARV_PORT_IRQ      0x17    /* 16 bit r/o   Port 0 IRQ (88E1111 only) */
8021  #define PHY_MARV_LED_CTRL      0x18    /* 16 bit r/w   LED Control Reg */
8022  #define PHY_MARV_LED_OVER      0x19    /* 16 bit r/w   Manual LED Override Reg */
8023  #define PHY_MARV_EXT_CTRL_2    0x1a    /* 16 bit r/w   Ext. PHY Specific Ctrl 2 */
8024  #define PHY_MARV_EXT_P_STAT    0x1b    /* 16 bit r/w   Ext. PHY Spec. Stat Reg */
8025  #define PHY_MARV_CABLE_DIAG    0x1c    /* 16 bit r/o   Cable Diagnostic Reg */
8026 -       /* 0x1d - 0x1f:         reserved */
8027 +#define PHY_MARV_PAGE_ADDR     0x1d    /* 16 bit r/w   Extended Page Address Reg */
8028 +#define PHY_MARV_PAGE_DATA     0x1e    /* 16 bit r/w   Extended Page Data Reg */
8029 +
8030 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
8031 +#define PHY_MARV_FE_LED_PAR    0x16    /* 16 bit r/w   LED Parallel Select Reg. */
8032 +#define PHY_MARV_FE_LED_SER    0x17    /* 16 bit r/w   LED Stream Select S. LED */
8033 +#define PHY_MARV_FE_VCT_TX     0x1a    /* 16 bit r/w   VCT Reg. for TXP/N Pins */
8034 +#define PHY_MARV_FE_VCT_RX     0x1b    /* 16 bit r/o   VCT Reg. for RXP/N Pins */
8035 +#define PHY_MARV_FE_SPEC_2     0x1c    /* 16 bit r/w   Specific Control Reg. 2 */
8036
8037  /*----------------------------------------------------------------------------*/
8038  /*
8039 @@ -569,14 +580,14 @@
8040  #define PHY_LONE_ID0           0x02    /* 16 bit r/o   PHY ID0 Register */
8041  #define PHY_LONE_ID1           0x03    /* 16 bit r/o   PHY ID1 Register */
8042  #define PHY_LONE_AUNE_ADV      0x04    /* 16 bit r/w   Auto-Neg. Advertisement */
8043 -#define PHY_LONE_AUNE_LP       0x05    /* 16 bit r/o   Link Part Ability Reg */
8044 +#define PHY_LONE_AUNE_LP       0x05    /* 16 bit r/o   Link Partner Ability Reg */
8045  #define PHY_LONE_AUNE_EXP      0x06    /* 16 bit r/o   Auto-Neg. Expansion Reg */
8046  #define PHY_LONE_NEPG          0x07    /* 16 bit r/w   Next Page Register */
8047  #define PHY_LONE_NEPG_LP       0x08    /* 16 bit r/o   Next Page Link Partner */
8048         /* Level One-specific registers */
8049 -#define PHY_LONE_1000T_CTRL    0x09    /* 16 bit r/w   1000Base-T Control Reg*/
8050 +#define PHY_LONE_1000T_CTRL    0x09    /* 16 bit r/w   1000Base-T Control Reg */
8051  #define PHY_LONE_1000T_STAT    0x0a    /* 16 bit r/o   1000Base-T Status Reg */
8052 -       /* 0x0b -0x0e:          reserved */
8053 +       /* 0x0b - 0x0e:         reserved */
8054  #define PHY_LONE_EXT_STAT      0x0f    /* 16 bit r/o   Extended Status Reg */
8055  #define PHY_LONE_PORT_CFG      0x10    /* 16 bit r/w   Port Configuration Reg*/
8056  #define PHY_LONE_Q_STAT                0x11    /* 16 bit r/o   Quick Status Reg */
8057 @@ -585,7 +596,7 @@
8058  #define PHY_LONE_LED_CFG       0x14    /* 16 bit r/w   LED Configuration Reg */
8059  #define PHY_LONE_PORT_CTRL     0x15    /* 16 bit r/w   Port Control Reg */
8060  #define PHY_LONE_CIM           0x16    /* 16 bit r/o   CIM Reg */
8061 -       /* 0x17 -0x1c:          reserved */
8062 +       /* 0x17 - 0x1c:         reserved */
8063
8064  /*----------------------------------------------------------------------------*/
8065  /*
8066 @@ -603,14 +614,14 @@
8067         /* National-specific registers */
8068  #define PHY_NAT_1000T_CTRL     0x09    /* 16 bit r/w   1000Base-T Control Reg */
8069  #define PHY_NAT_1000T_STAT     0x0a    /* 16 bit r/o   1000Base-T Status Reg */
8070 -       /* 0x0b -0x0e:          reserved */
8071 +       /* 0x0b - 0x0e:         reserved */
8072  #define PHY_NAT_EXT_STAT       0x0f    /* 16 bit r/o   Extended Status Register */
8073  #define PHY_NAT_EXT_CTRL1      0x10    /* 16 bit r/o   Extended Control Reg1 */
8074  #define PHY_NAT_Q_STAT1                0x11    /* 16 bit r/o   Quick Status Reg1 */
8075  #define PHY_NAT_10B_OP         0x12    /* 16 bit r/o   10Base-T Operations Reg */
8076  #define PHY_NAT_EXT_CTRL2      0x13    /* 16 bit r/o   Extended Control Reg1 */
8077  #define PHY_NAT_Q_STAT2                0x14    /* 16 bit r/o   Quick Status Reg2 */
8078 -       /* 0x15 -0x18:          reserved */
8079 +       /* 0x15 - 0x18:         reserved */
8080  #define PHY_NAT_PHY_ADDR       0x19    /* 16 bit r/o   PHY Address Register */
8081
8082
8083 @@ -618,7 +629,7 @@
8084
8085  /*
8086   * PHY bit definitions
8087 - * Bits defined as PHY_X_..., PHY_B_..., PHY_L_... or PHY_N_... are
8088 + * Bits defined as PHY_X_..., PHY_B_..., PHY_L_..., PHY_N_... or PHY_M_... are
8089   * XMAC/Broadcom/LevelOne/National/Marvell-specific.
8090   * All other are general.
8091   */
8092 @@ -629,14 +640,14 @@
8093  /*****  PHY_LONE_CTRL  16 bit r/w      PHY Control Register *****/
8094  #define PHY_CT_RESET   (1<<15) /* Bit 15: (sc) clear all PHY related regs */
8095  #define PHY_CT_LOOP            (1<<14) /* Bit 14:      enable Loopback over PHY */
8096 -#define PHY_CT_SPS_LSB (1<<13) /* Bit 13: (BC,L1) Speed select, lower bit */
8097 +#define PHY_CT_SPS_LSB (1<<13) /* Bit 13:      Speed select, lower bit */
8098  #define PHY_CT_ANE             (1<<12) /* Bit 12:      Auto-Negotiation Enabled */
8099 -#define PHY_CT_PDOWN   (1<<11) /* Bit 11: (BC,L1) Power Down Mode */
8100 -#define PHY_CT_ISOL            (1<<10) /* Bit 10: (BC,L1) Isolate Mode */
8101 -#define PHY_CT_RE_CFG  (1<<9)  /* Bit  9: (sc) Restart Auto-Negotiation */
8102 +#define PHY_CT_PDOWN   (1<<11) /* Bit 11:      Power Down Mode */
8103 +#define PHY_CT_ISOL            (1<<10) /* Bit 10:      Isolate Mode */
8104 +#define PHY_CT_RE_CFG  (1<<9)  /* Bit  9:      (sc) Restart Auto-Negotiation */
8105  #define PHY_CT_DUP_MD  (1<<8)  /* Bit  8:      Duplex Mode */
8106 -#define PHY_CT_COL_TST (1<<7)  /* Bit  7: (BC,L1) Collision Test enabled */
8107 -#define PHY_CT_SPS_MSB (1<<6)  /* Bit  6: (BC,L1) Speed select, upper bit */
8108 +#define PHY_CT_COL_TST (1<<7)  /* Bit  7:      Collision Test enabled */
8109 +#define PHY_CT_SPS_MSB (1<<6)  /* Bit  6:      Speed select, upper bit */
8110                                                                 /* Bit  5..0:   reserved */
8111
8112  #define PHY_CT_SP1000  PHY_CT_SPS_MSB  /* enable speed of 1000 Mbps */
8113 @@ -649,25 +660,25 @@
8114  /*****  PHY_MARV_STAT  16 bit r/w      PHY Status Register *****/
8115  /*****  PHY_LONE_STAT  16 bit r/w      PHY Status Register *****/
8116                                                                 /* Bit 15..9:   reserved */
8117 -                               /*      (BC/L1) 100/10 Mbps cap bits ignored*/
8118 +                               /*      (BC/L1) 100/10 Mbps cap bits ignored */
8119  #define PHY_ST_EXT_ST  (1<<8)  /* Bit  8:      Extended Status Present */
8120                                                                 /* Bit  7:      reserved */
8121 -#define PHY_ST_PRE_SUP (1<<6)  /* Bit  6: (BC/L1) preamble suppression */
8122 +#define PHY_ST_PRE_SUP (1<<6)  /* Bit  6:      Preamble Suppression */
8123  #define PHY_ST_AN_OVER (1<<5)  /* Bit  5:      Auto-Negotiation Over */
8124  #define PHY_ST_REM_FLT (1<<4)  /* Bit  4:      Remote Fault Condition Occured */
8125  #define PHY_ST_AN_CAP  (1<<3)  /* Bit  3:      Auto-Negotiation Capability */
8126  #define PHY_ST_LSYNC   (1<<2)  /* Bit  2:      Link Synchronized */
8127 -#define PHY_ST_JAB_DET (1<<1)  /* Bit  1: (BC/L1) Jabber Detected */
8128 +#define PHY_ST_JAB_DET (1<<1)  /* Bit  1:      Jabber Detected */
8129  #define PHY_ST_EXT_REG (1<<0)  /* Bit  0:      Extended Register available */
8130
8131
8132 -/***** PHY_XMAC_ID1            16 bit r/o      PHY ID1 Register */
8133 -/***** PHY_BCOM_ID1            16 bit r/o      PHY ID1 Register */
8134 -/***** PHY_MARV_ID1            16 bit r/o      PHY ID1 Register */
8135 -/***** PHY_LONE_ID1            16 bit r/o      PHY ID1 Register */
8136 +/*****  PHY_XMAC_ID1           16 bit r/o      PHY ID1 Register */
8137 +/*****  PHY_BCOM_ID1           16 bit r/o      PHY ID1 Register */
8138 +/*****  PHY_MARV_ID1           16 bit r/o      PHY ID1 Register */
8139 +/*****  PHY_LONE_ID1           16 bit r/o      PHY ID1 Register */
8140  #define PHY_I1_OUI_MSK (0x3f<<10)      /* Bit 15..10:  Organization Unique ID */
8141  #define PHY_I1_MOD_NUM (0x3f<<4)       /* Bit  9.. 4:  Model Number */
8142 -#define PHY_I1_REV_MSK 0x0f            /* Bit  3.. 0:  Revision Number */
8143 +#define PHY_I1_REV_MSK 0xf                     /* Bit  3.. 0:  Revision Number */
8144
8145  /* different Broadcom PHY Ids */
8146  #define PHY_BCOM_ID1_A1                0x6041
8147 @@ -675,11 +686,21 @@
8148  #define PHY_BCOM_ID1_C0                0x6044
8149  #define PHY_BCOM_ID1_C5                0x6047
8150
8151 +/* different Marvell PHY Ids */
8152 +#define PHY_MARV_ID0_VAL       0x0141          /* Marvell Unique Identifier */
8153 +
8154 +#define PHY_MARV_ID1_B0                0x0C23          /* Yukon      (PHY 88E1040 Rev.C0) */
8155 +#define PHY_MARV_ID1_B2                0x0C25          /* Yukon-Plus (PHY 88E1040 Rev.D0) */
8156 +#define PHY_MARV_ID1_C2                0x0CC2          /* Yukon-EC   (PHY 88E1111 Rev.B1) */
8157 +#define PHY_MARV_ID1_Y2                0x0C91          /* Yukon-XL   (PHY 88E1112 Rev.B0) */
8158 +#define PHY_MARV_ID1_FE                0x0C83          /* Yukon-FE   (PHY 88E3082 Rev.A1) */
8159 +#define PHY_MARV_ID1_ECU       0x0CB0          /* Yukon-ECU  (PHY 88E1149 Rev.B2?) */
8160 +
8161
8162  /*****  PHY_XMAC_AUNE_ADV      16 bit r/w      Auto-Negotiation Advertisement *****/
8163  /*****  PHY_XMAC_AUNE_LP       16 bit r/o      Link Partner Ability Reg *****/
8164  #define PHY_AN_NXT_PG  (1<<15) /* Bit 15:      Request Next Page */
8165 -#define PHY_X_AN_ACK   (1<<14) /* Bit 14: (ro) Acknowledge Received */
8166 +#define PHY_X_AN_ACK   (1<<14) /* Bit 14:      (ro) Acknowledge Received */
8167  #define PHY_X_AN_RFB   (3<<12) /* Bit 13..12:  Remote Fault Bits */
8168                                                                 /* Bit 11.. 9:  reserved */
8169  #define PHY_X_AN_PAUSE (3<<7)  /* Bit  8.. 7:  Pause Bits */
8170 @@ -738,7 +759,7 @@
8171  /*     PHY_ANE_LP_NP           (see XMAC) Bit  3:      Link Partner can Next Page */
8172  /*     PHY_ANE_LOC_NP          (see XMAC) Bit  2:      Local PHY can Next Page */
8173  /*     PHY_ANE_RX_PG           (see XMAC) Bit  1:      Page Received */
8174 -#define PHY_ANE_LP_CAP (1<<0)  /* Bit  0:      Link Partner Auto-Neg. Cap. */
8175 +#define PHY_ANE_LP_CAP (1<<0)  /* Bit  0:      Link Partner Auto-Neg. Able */
8176
8177  /*****  PHY_XMAC_NEPG          16 bit r/w      Next Page Register *****/
8178  /*****  PHY_BCOM_NEPG          16 bit r/w      Next Page Register *****/
8179 @@ -827,7 +848,7 @@
8180  #define PHY_B_PEC_BY_MLT3      (1<<8)  /* Bit  8:      Bypass MLT3 Encoder */
8181  #define PHY_B_PEC_BY_RXA       (1<<7)  /* Bit  7:      Bypass Rx Alignm. */
8182  #define PHY_B_PEC_RES_SCR      (1<<6)  /* Bit  6:      Reset Scrambler */
8183 -#define PHY_B_PEC_EN_LTR       (1<<5)  /* Bit  5:      Ena LED Traffic Mode */
8184 +#define PHY_B_PEC_EN_LTR       (1<<5)  /* Bit  5:      Enable LED Traffic Mode */
8185  #define PHY_B_PEC_LED_ON       (1<<4)  /* Bit  4:      Force LED's on */
8186  #define PHY_B_PEC_LED_OFF      (1<<3)  /* Bit  3:      Force LED's off */
8187  #define PHY_B_PEC_EX_IPG       (1<<2)  /* Bit  2:      Extend Tx IPG Mode */
8188 @@ -981,7 +1002,7 @@
8189  #define PHY_L_QS_DUP_MOD       (1<<9)  /* Bit  9:      Full/Half Duplex */
8190  #define PHY_L_QS_AN                    (1<<8)  /* Bit  8:      AutoNeg is On */
8191  #define PHY_L_QS_AN_C          (1<<7)  /* Bit  7:      AN is Complete */
8192 -#define PHY_L_QS_LLE           (7<<4)  /* Bit  6:      Line Length Estim. */
8193 +#define PHY_L_QS_LLE           (7<<4)  /* Bit  6..4:   Line Length Estim. */
8194  #define PHY_L_QS_PAUSE         (1<<3)  /* Bit  3:      LP advertised Pause */
8195  #define PHY_L_QS_AS_PAUSE      (1<<2)  /* Bit  2:      LP adv. asym. Pause */
8196  #define PHY_L_QS_ISOLATE       (1<<1)  /* Bit  1:      CIM Isolated */
8197 @@ -1029,9 +1050,8 @@
8198                                                                         /* Bit  9..0:   not described */
8199
8200  /*****  PHY_LONE_CIM           16 bit r/o      CIM Reg *****/
8201 -#define PHY_L_CIM_ISOL         (255<<8)/* Bit 15..8:   Isolate Count */
8202 -#define PHY_L_CIM_FALSE_CAR    (255<<0)/* Bit  7..0:   False Carrier Count */
8203 -
8204 +#define PHY_L_CIM_ISOL         (0xff<<8)       /* Bit 15..8:   Isolate Count */
8205 +#define PHY_L_CIM_FALSE_CAR    0xff            /* Bit  7..0:   False Carrier Count */
8206
8207  /*
8208   * Pause Bits (PHY_L_AN_ASP and PHY_L_AN_PC) encoding
8209 @@ -1041,7 +1061,6 @@
8210  #define PHY_L_P_ASYM_MD                (2<<10) /* Bit 11..10:  asymmetric Pause Mode */
8211  #define PHY_L_P_BOTH_MD                (3<<10) /* Bit 11..10:  both Pause Mode */
8212
8213 -
8214  /*
8215   * National-Specific
8216   */
8217 @@ -1085,23 +1104,25 @@
8218   * Marvell-Specific
8219   */
8220  /*****  PHY_MARV_AUNE_ADV      16 bit r/w      Auto-Negotiation Advertisement *****/
8221 -/*****  PHY_MARV_AUNE_LP       16 bit r/w      Link Part Ability Reg *****/
8222 -#define PHY_M_AN_NXT_PG                BIT_15  /* Request Next Page */
8223 -#define PHY_M_AN_ACK           BIT_14  /* (ro) Acknowledge Received */
8224 -#define PHY_M_AN_RF                    BIT_13  /* Remote Fault */
8225 -                                                                       /* Bit 12:      reserved */
8226 -#define PHY_M_AN_ASP           BIT_11  /* Asymmetric Pause */
8227 -#define PHY_M_AN_PC                    BIT_10  /* MAC Pause implemented */
8228 -#define PHY_M_AN_100_FD                BIT_8   /* Advertise 100Base-TX Full Duplex */
8229 -#define PHY_M_AN_100_HD                BIT_7   /* Advertise 100Base-TX Half Duplex */
8230 -#define PHY_M_AN_10_FD         BIT_6   /* Advertise 10Base-TX Full Duplex */
8231 -#define PHY_M_AN_10_HD         BIT_5   /* Advertise 10Base-TX Half Duplex */
8232 -
8233 -/* special defines for FIBER (88E1011S only) */
8234 -#define PHY_M_AN_ASP_X         BIT_8   /* Asymmetric Pause */
8235 -#define PHY_M_AN_PC_X          BIT_7   /* MAC Pause implemented */
8236 -#define PHY_M_AN_1000X_AHD     BIT_6   /* Advertise 10000Base-X Half Duplex */
8237 -#define PHY_M_AN_1000X_AFD     BIT_5   /* Advertise 10000Base-X Full Duplex */
8238 +/*****  PHY_MARV_AUNE_LP       16 bit r/w      Link Partner Ability Reg *****/
8239 +#define PHY_M_AN_NXT_PG                BIT_15S /* Request Next Page */
8240 +#define PHY_M_AN_ACK           BIT_14S /* (ro) Acknowledge Received */
8241 +#define PHY_M_AN_RF                    BIT_13S /* Remote Fault */
8242 +                                                               /* Bit 12:      reserved */
8243 +#define PHY_M_AN_ASP           BIT_11S /* Asymmetric Pause */
8244 +#define PHY_M_AN_PC                    BIT_10S /* MAC Pause implemented */
8245 +#define PHY_M_AN_100_T4                BIT_9S  /* Not cap. 100Base-T4 (always 0) */
8246 +#define PHY_M_AN_100_FD                BIT_8S  /* Advertise 100Base-TX Full Duplex */
8247 +#define PHY_M_AN_100_HD                BIT_7S  /* Advertise 100Base-TX Half Duplex */
8248 +#define PHY_M_AN_10_FD         BIT_6S  /* Advertise 10Base-TX Full Duplex */
8249 +#define PHY_M_AN_10_HD         BIT_5S  /* Advertise 10Base-TX Half Duplex */
8250 +#define PHY_M_AN_SEL_MSK       (0x1f<<4)       /* Bit  4.. 0: Selector Field Mask */
8251 +
8252 +/* special defines for FIBER (88E1040S only) */
8253 +#define PHY_M_AN_ASP_X         BIT_8S  /* Asymmetric Pause */
8254 +#define PHY_M_AN_PC_X          BIT_7S  /* MAC Pause implemented */
8255 +#define PHY_M_AN_1000X_AHD     BIT_6S  /* Advertise 10000Base-X Half Duplex */
8256 +#define PHY_M_AN_1000X_AFD     BIT_5S  /* Advertise 10000Base-X Full Duplex */
8257
8258  /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
8259  #define PHY_M_P_NO_PAUSE_X     (0<<7)  /* Bit  8.. 7:  no Pause Mode */
8260 @@ -1111,105 +1132,168 @@
8261
8262  /*****  PHY_MARV_1000T_CTRL    16 bit r/w      1000Base-T Control Reg *****/
8263  #define PHY_M_1000C_TEST       (7<<13) /* Bit 15..13:  Test Modes */
8264 -#define PHY_M_1000C_MSE                (1<<12) /* Bit 12:      Manual Master/Slave Enable */
8265 -#define PHY_M_1000C_MSC                (1<<11) /* Bit 11:      M/S Configuration (1=Master) */
8266 -#define PHY_M_1000C_MPD                (1<<10) /* Bit 10:      Multi-Port Device */
8267 -#define PHY_M_1000C_AFD                (1<<9)  /* Bit  9:      Advertise Full Duplex */
8268 -#define PHY_M_1000C_AHD                (1<<8)  /* Bit  8:      Advertise Half Duplex */
8269 +#define PHY_M_1000C_MSE                BIT_12S /* Manual Master/Slave Enable */
8270 +#define PHY_M_1000C_MSC                BIT_11S /* M/S Configuration (1=Master) */
8271 +#define PHY_M_1000C_MPD                BIT_10S /* Multi-Port Device */
8272 +#define PHY_M_1000C_AFD                BIT_9S  /* Advertise Full Duplex */
8273 +#define PHY_M_1000C_AHD                BIT_8S  /* Advertise Half Duplex */
8274                                                                         /* Bit  7..0:   reserved */
8275
8276  /*****  PHY_MARV_PHY_CTRL      16 bit r/w      PHY Specific Ctrl Reg *****/
8277 -#define PHY_M_PC_TX_FFD_MSK    (3<<14) /* Bit 15..14:  Tx FIFO Depth Mask */
8278 -#define PHY_M_PC_RX_FFD_MSK    (3<<12) /* Bit 13..12:  Rx FIFO Depth Mask */
8279 -#define PHY_M_PC_ASS_CRS_TX    (1<<11) /* Bit 11:      Assert CRS on Transmit */
8280 -#define PHY_M_PC_FL_GOOD       (1<<10) /* Bit 10:      Force Link Good */
8281 -#define PHY_M_PC_EN_DET_MSK    (3<<8)  /* Bit  9.. 8:  Energy Detect Mask */
8282 -#define PHY_M_PC_ENA_EXT_D     (1<<7)  /* Bit  7:      Enable Ext. Distance (10BT) */
8283 -#define PHY_M_PC_MDIX_MSK      (3<<5)  /* Bit  6.. 5:  MDI/MDIX Config. Mask */
8284 -#define PHY_M_PC_DIS_125CLK    (1<<4)  /* Bit  4:      Disable 125 CLK */
8285 -#define PHY_M_PC_MAC_POW_UP    (1<<3)  /* Bit  3:      MAC Power up */
8286 -#define PHY_M_PC_SQE_T_ENA     (1<<2)  /* Bit  2:      SQE Test Enabled */
8287 -#define PHY_M_PC_POL_R_DIS     (1<<1)  /* Bit  1:      Polarity Reversal Disabled */
8288 -#define PHY_M_PC_DIS_JABBER    (1<<0)  /* Bit  0:      Disable Jabber */
8289 +#define PHY_M_PC_TX_FFD_MSK    (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */
8290 +#define PHY_M_PC_RX_FFD_MSK    (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */
8291 +#define PHY_M_PC_ASS_CRS_TX    BIT_11S /* Assert CRS on Transmit */
8292 +#define PHY_M_PC_FL_GOOD       BIT_10S /* Force Link Good */
8293 +#define PHY_M_PC_EN_DET_MSK    (3<<8)  /* Bit  9.. 8: Energy Detect Mask */
8294 +#define PHY_M_PC_ENA_EXT_D     BIT_7S  /* Enable Ext. Distance (10BT) */
8295 +#define PHY_M_PC_MDIX_MSK      (3<<5)  /* Bit  6.. 5: MDI/MDIX Config. Mask */
8296 +#define PHY_M_PC_DIS_125CLK    BIT_4S  /* Disable 125 CLK */
8297 +#define PHY_M_PC_MAC_POW_UP    BIT_3S  /* MAC Power up */
8298 +#define PHY_M_PC_SQE_T_ENA     BIT_2S  /* SQE Test Enabled */
8299 +#define PHY_M_PC_POL_R_DIS     BIT_1S  /* Polarity Reversal Disabled */
8300 +#define PHY_M_PC_DIS_JABBER    BIT_0S  /* Disable Jabber */
8301
8302  #define PHY_M_PC_EN_DET                        SHIFT8(2)       /* Energy Detect (Mode 1) */
8303  #define PHY_M_PC_EN_DET_PLUS   SHIFT8(3)       /* Energy Detect Plus (Mode 2) */
8304
8305 -#define PHY_M_PC_MDI_XMODE(x)  SHIFT5(x)
8306 -#define PHY_M_PC_MAN_MDI       0       /* 00 = Manual MDI configuration */
8307 +#define PHY_M_PC_MDI_XMODE(x)  (SHIFT5(x) & PHY_M_PC_MDIX_MSK)
8308 +
8309 +#define PHY_M_PC_MAN_MDI       0               /* 00 = Manual MDI configuration */
8310  #define PHY_M_PC_MAN_MDIX      1               /* 01 = Manual MDIX configuration */
8311  #define PHY_M_PC_ENA_AUTO      3               /* 11 = Enable Automatic Crossover */
8312
8313 +/* for Yukon-2/-EC Ultra Gigabit Ethernet PHY (88E1112/88E1149 only) */
8314 +#define PHY_M_PC_DIS_LINK_P    BIT_15S /* Disable Link Pulses */
8315 +#define PHY_M_PC_DSC_MSK       (7<<12) /* Bit 14..12:  Downshift Counter */
8316 +#define PHY_M_PC_DOWN_S_ENA    BIT_11S /* Downshift Enable */
8317 +                                                                       /* !!! Errata in spec. (1 = disable) */
8318 +
8319 +#define PHY_M_PC_DSC(x)                        (SHIFT12(x) & PHY_M_PC_DSC_MSK)
8320 +                                                                               /* 000=1x; 001=2x; 010=3x; 011=4x */
8321 +                                                                               /* 100=5x; 101=6x; 110=7x; 111=8x */
8322 +
8323 +/* for Yukon-EC Ultra Gigabit Ethernet PHY (88E1149 only) */
8324 +                                                               /* Bit  4:      reserved */
8325 +#define PHY_M_PC_COP_TX_DIS    BIT_3S  /* Copper Transmitter Disable */
8326 +#define PHY_M_PC_POW_D_ENA     BIT_2S  /* Power Down Enable */
8327 +
8328 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
8329 +#define PHY_M_PC_ENA_DTE_DT    BIT_15S /* Enable Data Terminal Equ. (DTE) Detect */
8330 +#define PHY_M_PC_ENA_ENE_DT    BIT_14S /* Enable Energy Detect (sense & pulse) */
8331 +#define PHY_M_PC_DIS_NLP_CK    BIT_13S /* Disable Normal Link Puls (NLP) Check */
8332 +#define PHY_M_PC_ENA_LIP_NP    BIT_12S /* Enable Link Partner Next Page Reg. */
8333 +#define PHY_M_PC_DIS_NLP_GN    BIT_11S /* Disable Normal Link Puls Generation */
8334 +
8335 +#define PHY_M_PC_DIS_SCRAMB    BIT_9S  /* Disable Scrambler */
8336 +#define PHY_M_PC_DIS_FEFI      BIT_8S  /* Disable Far End Fault Indic. (FEFI) */
8337 +
8338 +#define PHY_M_PC_SH_TP_SEL     BIT_6S  /* Shielded Twisted Pair Select */
8339 +#define PHY_M_PC_RX_FD_MSK     (3<<2)  /* Bit  3.. 2: Rx FIFO Depth Mask */
8340 +
8341  /*****  PHY_MARV_PHY_STAT      16 bit r/o      PHY Specific Status Reg *****/
8342 -#define PHY_M_PS_SPEED_MSK     (3<<14) /* Bit 15..14:  Speed Mask */
8343 -#define PHY_M_PS_SPEED_1000    (1<<15) /*       10 = 1000 Mbps */
8344 -#define PHY_M_PS_SPEED_100     (1<<14) /*       01 =  100 Mbps */
8345 -#define PHY_M_PS_SPEED_10      0               /*       00 =   10 Mbps */
8346 -#define PHY_M_PS_FULL_DUP      (1<<13) /* Bit 13:      Full Duplex */
8347 -#define PHY_M_PS_PAGE_REC      (1<<12) /* Bit 12:      Page Received */
8348 -#define PHY_M_PS_SPDUP_RES     (1<<11) /* Bit 11:      Speed & Duplex Resolved */
8349 -#define PHY_M_PS_LINK_UP       (1<<10) /* Bit 10:      Link Up */
8350 -#define PHY_M_PS_CABLE_MSK     (3<<7)  /* Bit  9.. 7:  Cable Length Mask */
8351 -#define PHY_M_PS_MDI_X_STAT    (1<<6)  /* Bit  6:      MDI Crossover Stat (1=MDIX) */
8352 -#define PHY_M_PS_DOWNS_STAT    (1<<5)  /* Bit  5:      Downshift Status (1=downsh.) */
8353 -#define PHY_M_PS_ENDET_STAT    (1<<4)  /* Bit  4:      Energy Detect Status (1=act) */
8354 -#define PHY_M_PS_TX_P_EN       (1<<3)  /* Bit  3:      Tx Pause Enabled */
8355 -#define PHY_M_PS_RX_P_EN       (1<<2)  /* Bit  2:      Rx Pause Enabled */
8356 -#define PHY_M_PS_POL_REV       (1<<1)  /* Bit  1:      Polarity Reversed */
8357 -#define PHY_M_PC_JABBER                (1<<0)  /* Bit  0:      Jabber */
8358 +#define PHY_M_PS_SPEED_MSK     (3<<14) /* Bit 15..14: Speed Mask */
8359 +#define PHY_M_PS_SPEED_1000    BIT_15S /*              10 = 1000 Mbps */
8360 +#define PHY_M_PS_SPEED_100     BIT_14S /*              01 =  100 Mbps */
8361 +#define PHY_M_PS_SPEED_10      0               /*              00 =   10 Mbps */
8362 +#define PHY_M_PS_FULL_DUP      BIT_13S /* Full Duplex */
8363 +#define PHY_M_PS_PAGE_REC      BIT_12S /* Page Received */
8364 +#define PHY_M_PS_SPDUP_RES     BIT_11S /* Speed & Duplex Resolved */
8365 +#define PHY_M_PS_LINK_UP       BIT_10S /* Link Up */
8366 +#define PHY_M_PS_CABLE_MSK     (7<<7)  /* Bit  9.. 7: Cable Length Mask */
8367 +#define PHY_M_PS_MDI_X_STAT    BIT_6S  /* MDI Crossover Stat (1=MDIX) */
8368 +#define PHY_M_PS_DOWNS_STAT    BIT_5S  /* Downshift Status (1=downsh.) */
8369 +#define PHY_M_PS_ENDET_STAT    BIT_4S  /* Energy Detect Status (1=act) */
8370 +#define PHY_M_PS_TX_P_EN       BIT_3S  /* Tx Pause Enabled */
8371 +#define PHY_M_PS_RX_P_EN       BIT_2S  /* Rx Pause Enabled */
8372 +#define PHY_M_PS_POL_REV       BIT_1S  /* Polarity Reversed */
8373 +#define PHY_M_PS_JABBER                BIT_0S  /* Jabber */
8374
8375  #define PHY_M_PS_PAUSE_MSK     (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
8376
8377 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
8378 +#define PHY_M_PS_DTE_DETECT    BIT_15S /* Data Terminal Equipment (DTE) Detected */
8379 +#define PHY_M_PS_RES_SPEED     BIT_14S /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
8380 +
8381  /*****  PHY_MARV_INT_MASK      16 bit r/w      Interrupt Mask Reg *****/
8382  /*****  PHY_MARV_INT_STAT      16 bit r/o      Interrupt Status Reg *****/
8383 -#define PHY_M_IS_AN_ERROR      (1<<15) /* Bit 15:      Auto-Negotiation Error */
8384 -#define PHY_M_IS_LSP_CHANGE    (1<<14) /* Bit 14:      Link Speed Changed */
8385 -#define PHY_M_IS_DUP_CHANGE    (1<<13) /* Bit 13:      Duplex Mode Changed */
8386 -#define PHY_M_IS_AN_PR         (1<<12) /* Bit 12:      Page Received */
8387 -#define PHY_M_IS_AN_COMPL      (1<<11) /* Bit 11:      Auto-Negotiation Completed */
8388 -#define PHY_M_IS_LST_CHANGE    (1<<10) /* Bit 10:      Link Status Changed */
8389 -#define PHY_M_IS_SYMB_ERROR    (1<<9)  /* Bit  9:      Symbol Error */
8390 -#define PHY_M_IS_FALSE_CARR    (1<<8)  /* Bit  8:      False Carrier */
8391 -#define PHY_M_IS_FIFO_ERROR    (1<<7)  /* Bit  7:      FIFO Overflow/Underrun Error */
8392 -#define PHY_M_IS_MDI_CHANGE    (1<<6)  /* Bit  6:      MDI Crossover Changed */
8393 -#define PHY_M_IS_DOWNSH_DET    (1<<5)  /* Bit  5:      Downshift Detected */
8394 -#define PHY_M_IS_END_CHANGE    (1<<4)  /* Bit  4:      Energy Detect Changed */
8395 -                                                                       /* Bit  3..2:   reserved */
8396 -#define PHY_M_IS_POL_CHANGE    (1<<1)  /* Bit  1:      Polarity Changed */
8397 -#define PHY_M_IS_JABBER                (1<<0)  /* Bit  0:      Jabber */
8398 +#define PHY_M_IS_AN_ERROR      BIT_15S /* Auto-Negotiation Error */
8399 +#define PHY_M_IS_LSP_CHANGE    BIT_14S /* Link Speed Changed */
8400 +#define PHY_M_IS_DUP_CHANGE    BIT_13S /* Duplex Mode Changed */
8401 +#define PHY_M_IS_AN_PR         BIT_12S /* Page Received */
8402 +#define PHY_M_IS_AN_COMPL      BIT_11S /* Auto-Negotiation Completed */
8403 +#define PHY_M_IS_LST_CHANGE    BIT_10S /* Link Status Changed */
8404 +#define PHY_M_IS_SYMB_ERROR    BIT_9S  /* Symbol Error */
8405 +#define PHY_M_IS_FALSE_CARR    BIT_8S  /* False Carrier */
8406 +#define PHY_M_IS_FIFO_ERROR    BIT_7S  /* FIFO Overflow/Underrun Error */
8407 +#define PHY_M_IS_MDI_CHANGE    BIT_6S  /* MDI Crossover Changed */
8408 +#define PHY_M_IS_DOWNSH_DET    BIT_5S  /* Downshift Detected */
8409 +#define PHY_M_IS_END_CHANGE    BIT_4S  /* Energy Detect Changed */
8410 +                                                               /* Bit   3:     reserved */
8411 +#define PHY_M_IS_DTE_CHANGE    BIT_2S  /* DTE Power Det. Status Changed */
8412 +                                                                       /* (88E1111 only) */
8413 +#define PHY_M_IS_POL_CHANGE    BIT_1S  /* Polarity Changed */
8414 +#define PHY_M_IS_JABBER                BIT_0S  /* Jabber */
8415
8416  #define PHY_M_DEF_MSK          (PHY_M_IS_AN_ERROR | PHY_M_IS_AN_PR | \
8417 -                                                       PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR)
8418 +                                                       PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR | \
8419 +                                                       PHY_M_IS_END_CHANGE)
8420
8421  /*****  PHY_MARV_EXT_CTRL      16 bit r/w      Ext. PHY Specific Ctrl *****/
8422 -#define PHY_M_EC_M_DSC_MSK     (3<<10) /* Bit 11..10:  Master downshift counter */
8423 -#define PHY_M_EC_S_DSC_MSK     (3<<8)  /* Bit  9.. 8:  Slave  downshift counter */
8424 +#define PHY_M_EC_ENA_BC_EXT    BIT_15S /* Enable Block Carr. Ext. (88E1111 only) */
8425 +#define PHY_M_EC_ENA_LIN_LB    BIT_14S /* Enable Line Loopback (88E1111 only) */
8426 +                                                               /* Bit 13:      reserved */
8427 +#define PHY_M_EC_DIS_LINK_P    BIT_12S /* Disable Link Pulses (88E1111 only) */
8428 +#define PHY_M_EC_M_DSC_MSK     (3<<10) /* Bit 11..10:  Master Downshift Counter */
8429 +                                                                       /* (88E1040 Rev.C0 only) */
8430 +#define PHY_M_EC_S_DSC_MSK     (3<<8)  /* Bit  9.. 8:  Slave  Downshift Counter */
8431 +                                                                       /* (88E1040 Rev.C0 only) */
8432 +#define PHY_M_EC_DSC_MSK_2     (7<<9)  /* Bit 11.. 9:  Downshift Counter */
8433 +                                                                       /* (88E1040 Rev.D0 and higher) */
8434 +#define PHY_M_EC_DOWN_S_ENA    BIT_8S  /* Downshift Enable (88E1040 Rev.D0 and */
8435 +                                                                       /* 88E1111 !!! Errata in spec. (1=dis.) */
8436 +#define PHY_M_EC_RX_TIM_CT     BIT_7S  /* RGMII Rx Timing Control*/
8437  #define PHY_M_EC_MAC_S_MSK     (7<<4)  /* Bit  6.. 4:  Def. MAC interface speed */
8438 -#define PHY_M_EC_FIB_AN_ENA    (1<<3)  /* Bit  3:      Fiber Auto-Neg. Enable */
8439 -
8440 -#define PHY_M_EC_M_DSC(x)              SHIFT10(x)      /* 00=1x; 01=2x; 10=3x; 11=4x */
8441 -#define PHY_M_EC_S_DSC(x)              SHIFT8(x)       /* 00=dis; 01=1x; 10=2x; 11=3x */
8442 -#define PHY_M_EC_MAC_S(x)              SHIFT4(x)       /* 01X=0; 110=2.5; 111=25 (MHz) */
8443 -
8444 +#define PHY_M_EC_FIB_AN_ENA    BIT_3S  /* Fiber Auto-Neg. Enable 88E1040S only) */
8445 +#define PHY_M_EC_DTE_D_ENA     BIT_2S  /* DTE Detect Enable (88E1111 only) */
8446 +#define PHY_M_EC_TX_TIM_CT     BIT_1S  /* RGMII Tx Timing Control */
8447 +#define PHY_M_EC_TRANS_DIS     BIT_0S  /* Transmitter Disable (88E1111 only) */
8448 +
8449 +#define PHY_M_EC_M_DSC(x)              (SHIFT10(x) & PHY_M_EC_M_DSC_MSK)
8450 +                                                                       /* 00=1x; 01=2x; 10=3x; 11=4x */
8451 +#define PHY_M_EC_S_DSC(x)              (SHIFT8(x) & PHY_M_EC_S_DSC_MSK)
8452 +                                                                       /* 00=dis; 01=1x; 10=2x; 11=3x */
8453 +#define PHY_M_EC_MAC_S(x)              (SHIFT4(x) & PHY_M_EC_MAC_S_MSK)
8454 +                                                                       /* 01X=0; 110=2.5; 111=25 (MHz) */
8455 +
8456 +#define PHY_M_EC_DSC_2(x)              (SHIFT9(x) & PHY_M_EC_DSC_MSK_2)
8457 +                                                                       /* 000=1x; 001=2x; 010=3x; 011=4x */
8458 +                                                                       /* 100=5x; 101=6x; 110=7x; 111=8x */
8459  #define MAC_TX_CLK_0_MHZ       2
8460  #define MAC_TX_CLK_2_5_MHZ     6
8461  #define MAC_TX_CLK_25_MHZ      7
8462
8463  /*****  PHY_MARV_LED_CTRL      16 bit r/w      LED Control Reg *****/
8464 -#define PHY_M_LEDC_DIS_LED     (1<<15) /* Bit 15:      Disable LED */
8465 -#define PHY_M_LEDC_PULS_MSK    (7<<12) /* Bit 14..12:  Pulse Stretch Mask */
8466 -#define PHY_M_LEDC_F_INT       (1<<11) /* Bit 11:      Force Interrupt */
8467 -#define PHY_M_LEDC_BL_R_MSK    (7<<8)  /* Bit 10.. 8:  Blink Rate Mask */
8468 -                                                                       /* Bit  7.. 5:  reserved */
8469 -#define PHY_M_LEDC_LINK_MSK    (3<<3)  /* Bit  4.. 3:  Link Control Mask */
8470 -#define PHY_M_LEDC_DP_CTRL     (1<<2)  /* Bit  2:      Duplex Control */
8471 -#define PHY_M_LEDC_RX_CTRL     (1<<1)  /* Bit  1:      Rx activity / Link */
8472 -#define PHY_M_LEDC_TX_CTRL     (1<<0)  /* Bit  0:      Tx activity / Link */
8473 +#define PHY_M_LEDC_DIS_LED     BIT_15S /* Disable LED */
8474 +#define PHY_M_LEDC_PULS_MSK    (7<<12) /* Bit 14..12: Pulse Stretch Mask */
8475 +#define PHY_M_LEDC_F_INT       BIT_11S /* Force Interrupt */
8476 +#define PHY_M_LEDC_BL_R_MSK    (7<<8)  /* Bit 10.. 8: Blink Rate Mask */
8477 +#define PHY_M_LEDC_DP_C_LSB    BIT_7S  /* Duplex Control (LSB, 88E1111 only) */
8478 +#define PHY_M_LEDC_TX_C_LSB    BIT_6S  /* Tx Control (LSB, 88E1111 only) */
8479 +#define PHY_M_LEDC_LK_C_MSK    (7<<3)  /* Bit  5.. 3: Link Control Mask */
8480 +                                                                       /* (88E1111 only) */
8481 +                                                               /* Bit  7.. 5:  reserved (88E1040 only) */
8482 +#define PHY_M_LEDC_LINK_MSK    (3<<3)  /* Bit  4.. 3: Link Control Mask */
8483 +                                                                       /* (88E1040 only) */
8484 +#define PHY_M_LEDC_DP_CTRL     BIT_2S  /* Duplex Control */
8485 +#define PHY_M_LEDC_DP_C_MSB    BIT_2S  /* Duplex Control (MSB, 88E1111 only) */
8486 +#define PHY_M_LEDC_RX_CTRL     BIT_1S  /* Rx Activity / Link */
8487 +#define PHY_M_LEDC_TX_CTRL     BIT_0S  /* Tx Activity / Link */
8488 +#define PHY_M_LEDC_TX_C_MSB    BIT_0S  /* Tx Control (MSB, 88E1111 only) */
8489
8490 -#define PHY_M_LED_PULS_DUR(x)  SHIFT12(x)      /* Pulse Stretch Duration */
8491 +#define PHY_M_LED_PULS_DUR(x)  (SHIFT12(x) & PHY_M_LEDC_PULS_MSK)
8492
8493 -#define        PULS_NO_STR             0               /* no pulse stretching */
8494 -#define        PULS_21MS               1               /* 21 ms to 42 ms */
8495 +#define PULS_NO_STR            0               /* no pulse stretching */
8496 +#define PULS_21MS              1               /* 21 ms to 42 ms */
8497  #define PULS_42MS              2               /* 42 ms to 84 ms */
8498  #define PULS_84MS              3               /* 84 ms to 170 ms */
8499  #define PULS_170MS             4               /* 170 ms to 340 ms */
8500 @@ -1217,7 +1301,7 @@
8501  #define PULS_670MS             6               /* 670 ms to 1.3 s */
8502  #define PULS_1300MS            7               /* 1.3 s to 2.7 s */
8503
8504 -#define PHY_M_LED_BLINK_RT(x)  SHIFT8(x)       /* Blink Rate */
8505 +#define PHY_M_LED_BLINK_RT(x)  (SHIFT8(x) & PHY_M_LEDC_BL_R_MSK)
8506
8507  #define BLINK_42MS             0               /* 42 ms */
8508  #define BLINK_84MS             1               /* 84 ms */
8509 @@ -1227,6 +1311,8 @@
8510                                                                 /* values 5 - 7: reserved */
8511
8512  /*****  PHY_MARV_LED_OVER      16 bit r/w      Manual LED Override Reg *****/
8513 +#define PHY_M_LED_MO_SGMII(x)  SHIFT14(x)      /* Bit 15..14:  SGMII AN Timer */
8514 +                                                                               /* Bit 13..12:  reserved */
8515  #define PHY_M_LED_MO_DUP(x)            SHIFT10(x)      /* Bit 11..10:  Duplex */
8516  #define PHY_M_LED_MO_10(x)             SHIFT8(x)       /* Bit  9.. 8:  Link 10 */
8517  #define PHY_M_LED_MO_100(x)            SHIFT6(x)       /* Bit  7.. 6:  Link 100 */
8518 @@ -1240,30 +1326,35 @@
8519  #define MO_LED_ON                      3
8520
8521  /*****  PHY_MARV_EXT_CTRL_2    16 bit r/w      Ext. PHY Specific Ctrl 2 *****/
8522 -                                                                       /* Bit 15.. 7:  reserved */
8523 -#define PHY_M_EC2_FI_IMPED     (1<<6)  /* Bit  6:      Fiber Input  Impedance */
8524 -#define PHY_M_EC2_FO_IMPED     (1<<5)  /* Bit  5:      Fiber Output Impedance */
8525 -#define PHY_M_EC2_FO_M_CLK     (1<<4)  /* Bit  4:      Fiber Mode Clock Enable */
8526 -#define PHY_M_EC2_FO_BOOST     (1<<3)  /* Bit  3:      Fiber Output Boost */
8527 +                                                               /* Bit 15.. 7:  reserved */
8528 +#define PHY_M_EC2_FI_IMPED     BIT_6S  /* Fiber Input  Impedance */
8529 +#define PHY_M_EC2_FO_IMPED     BIT_5S  /* Fiber Output Impedance */
8530 +#define PHY_M_EC2_FO_M_CLK     BIT_4S  /* Fiber Mode Clock Enable */
8531 +#define PHY_M_EC2_FO_BOOST     BIT_3S  /* Fiber Output Boost */
8532  #define PHY_M_EC2_FO_AM_MSK    7               /* Bit  2.. 0:  Fiber Output Amplitude */
8533
8534 -/***** PHY_MARV_EXT_P_STAT 16 bit r/w  Ext. PHY Specific Status *****/
8535 -#define PHY_M_FC_AUTO_SEL      (1<<15) /* Bit 15:      Fiber/Copper Auto Sel. dis. */
8536 -#define PHY_M_FC_AN_REG_ACC (1<<14) /* Bit 14: Fiber/Copper Autoneg. reg acc */
8537 -#define PHY_M_FC_RESULUTION (1<<13)    /* Bit 13:      Fiber/Copper Resulution */
8538 -#define PHY_M_SER_IF_AN_BP  (1<<12) /* Bit 12: Ser IF autoneg. bypass enable */
8539 -#define PHY_M_SER_IF_BP_ST     (1<<11) /* Bit 11:      Ser IF autoneg. bypass status */
8540 -#define PHY_M_IRQ_POLARITY     (1<<10) /* Bit 10:      IRQ polarity */
8541 -                                                                       /* Bit 9..4: reserved */
8542 -#define PHY_M_UNDOC1           (1<< 7) /* undocumented bit !! */
8543 -#define PHY_M_MODE_MASK                (0xf<<0)/* Bit 3..0: copy of HWCFG MODE[3:0] */
8544 -
8545 +/*****  PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
8546 +#define PHY_M_FC_AUTO_SEL      BIT_15S /* Fiber/Copper Auto Sel. Dis. */
8547 +#define PHY_M_FC_AN_REG_ACC    BIT_14S /* Fiber/Copper AN Reg. Access */
8548 +#define PHY_M_FC_RESOLUTION    BIT_13S /* Fiber/Copper Resolution */
8549 +#define PHY_M_SER_IF_AN_BP     BIT_12S /* Ser. IF AN Bypass Enable */
8550 +#define PHY_M_SER_IF_BP_ST     BIT_11S /* Ser. IF AN Bypass Status */
8551 +#define PHY_M_IRQ_POLARITY     BIT_10S /* IRQ polarity */
8552 +#define PHY_M_DIS_AUT_MED      BIT_9S  /* Disable Aut. Medium Reg. Selection */
8553 +                                                                       /* (88E1111 only) */
8554 +                                                               /* Bit  9.. 4: reserved (88E1040 only) */
8555 +#define PHY_M_UNDOC1           BIT_7S  /* undocumented bit !! */
8556 +#define PHY_M_DTE_POW_STAT     BIT_4S  /* DTE Power Status (88E1111 only) */
8557 +#define PHY_M_MODE_MASK                0xf             /* Bit  3.. 0: copy of HWCFG MODE[3:0] */
8558
8559  /*****  PHY_MARV_CABLE_DIAG    16 bit r/o      Cable Diagnostic Reg *****/
8560 -#define PHY_M_CABD_ENA_TEST    (1<<15) /* Bit 15:      Enable Test */
8561 -#define PHY_M_CABD_STAT_MSK    (3<<13) /* Bit 14..13:  Status */
8562 -                                                                       /* Bit 12.. 8:  reserved */
8563 -#define PHY_M_CABD_DIST_MSK    0xff    /* Bit  7.. 0:  Distance */
8564 +#define PHY_M_CABD_ENA_TEST    BIT_15S         /* Enable Test (Page 0) */
8565 +#define PHY_M_CABD_DIS_WAIT    BIT_15S         /* Disable Waiting Period (Page 1) */
8566 +                                                                               /* (88E1111 only) */
8567 +#define PHY_M_CABD_STAT_MSK    (3<<13)         /* Bit 14..13: Status Mask */
8568 +#define PHY_M_CABD_AMPL_MSK    (0x1f<<8)       /* Bit 12.. 8: Amplitude Mask */
8569 +                                                                               /* (88E1111 only) */
8570 +#define PHY_M_CABD_DIST_MSK    0xff            /* Bit  7.. 0: Distance Mask */
8571
8572  /* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */
8573  #define CABD_STAT_NORMAL       0
8574 @@ -1271,6 +1362,79 @@
8575  #define CABD_STAT_OPEN         2
8576  #define CABD_STAT_FAIL         3
8577
8578 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
8579 +/*****  PHY_MARV_FE_LED_PAR            16 bit r/w      LED Parallel Select Reg. *****/
8580 +                                                                       /* Bit 15..12: reserved (used internally) */
8581 +#define PHY_M_FELP_LED2_MSK    (0xf<<8)        /* Bit 11.. 8: LED2 Mask (LINK) */
8582 +#define PHY_M_FELP_LED1_MSK    (0xf<<4)        /* Bit  7.. 4: LED1 Mask (ACT) */
8583 +#define PHY_M_FELP_LED0_MSK    0xf                     /* Bit  3.. 0: LED0 Mask (SPEED) */
8584 +
8585 +#define PHY_M_FELP_LED2_CTRL(x)        (SHIFT8(x) & PHY_M_FELP_LED2_MSK)
8586 +#define PHY_M_FELP_LED1_CTRL(x)        (SHIFT4(x) & PHY_M_FELP_LED1_MSK)
8587 +#define PHY_M_FELP_LED0_CTRL(x)        (SHIFT0(x) & PHY_M_FELP_LED0_MSK)
8588 +
8589 +#define LED_PAR_CTRL_COLX      0x00
8590 +#define LED_PAR_CTRL_ERROR     0x01
8591 +#define LED_PAR_CTRL_DUPLEX    0x02
8592 +#define LED_PAR_CTRL_DP_COL    0x03
8593 +#define LED_PAR_CTRL_SPEED     0x04
8594 +#define LED_PAR_CTRL_LINK      0x05
8595 +#define LED_PAR_CTRL_TX                0x06
8596 +#define LED_PAR_CTRL_RX                0x07
8597 +#define LED_PAR_CTRL_ACT       0x08
8598 +#define LED_PAR_CTRL_LNK_RX    0x09
8599 +#define LED_PAR_CTRL_LNK_AC    0x0a
8600 +#define LED_PAR_CTRL_ACT_BL    0x0b
8601 +#define LED_PAR_CTRL_TX_BL     0x0c
8602 +#define LED_PAR_CTRL_RX_BL     0x0d
8603 +#define LED_PAR_CTRL_COL_BL    0x0e
8604 +#define LED_PAR_CTRL_INACT     0x0f
8605 +
8606 +/*****  PHY_MARV_FE_SPEC_2             16 bit r/w      Specific Control Reg. 2 *****/
8607 +#define PHY_M_FESC_DIS_WAIT    BIT_2S  /* Disable TDR Waiting Period */
8608 +#define PHY_M_FESC_ENA_MCLK    BIT_1S  /* Enable MAC Rx Clock in sleep mode */
8609 +#define PHY_M_FESC_SEL_CL_A    BIT_0S  /* Select Class A driver (100B-TX) */
8610 +
8611 +/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
8612 +/*****  PHY_MARV_PHY_CTRL (page 1)             16 bit r/w      Fiber Specific Ctrl *****/
8613 +#define PHY_M_FIB_FORCE_LNK    BIT_10S /* Force Link Good */
8614 +#define PHY_M_FIB_SIGD_POL     BIT_9S  /* SIGDET Polarity */
8615 +#define PHY_M_FIB_TX_DIS       BIT_3S  /* Transmitter Disable */
8616 +
8617 +/*****  PHY_MARV_PHY_CTRL (page 2)             16 bit r/w      MAC Specific Ctrl *****/
8618 +#define PHY_M_MAC_MD_MSK       (7<<7)  /* Bit  9.. 7: Mode Select Mask */
8619 +#define PHY_M_MAC_GMIF_PUP     BIT_3S  /* GMII Power Up (88E1149 only) */
8620 +
8621 +#define PHY_M_MAC_MD_AUTO              3       /* Auto Copper/1000Base-X */
8622 +#define PHY_M_MAC_MD_COPPER            5       /* Copper only */
8623 +#define PHY_M_MAC_MD_1000BX            7       /* 1000Base-X only */
8624 +#define PHY_M_MAC_MODE_SEL(x)  (SHIFT7(x) & PHY_M_MAC_MD_MSK)
8625 +
8626 +/*****  PHY_MARV_PHY_CTRL (page 3)             16 bit r/w      LED Control Reg. *****/
8627 +#define PHY_M_LEDC_LOS_MSK     (0xf<<12)       /* Bit 15..12: LOS LED Ctrl. Mask */
8628 +#define PHY_M_LEDC_INIT_MSK    (0xf<<8)        /* Bit 11.. 8: INIT LED Ctrl. Mask */
8629 +#define PHY_M_LEDC_STA1_MSK    (0xf<<4)        /* Bit  7.. 4: STAT1 LED Ctrl. Mask */
8630 +#define PHY_M_LEDC_STA0_MSK    0xf                     /* Bit  3.. 0: STAT0 LED Ctrl. Mask */
8631 +
8632 +#define PHY_M_LEDC_LOS_CTRL(x) (SHIFT12(x) & PHY_M_LEDC_LOS_MSK)
8633 +#define PHY_M_LEDC_INIT_CTRL(x)        (SHIFT8(x) & PHY_M_LEDC_INIT_MSK)
8634 +#define PHY_M_LEDC_STA1_CTRL(x)        (SHIFT4(x) & PHY_M_LEDC_STA1_MSK)
8635 +#define PHY_M_LEDC_STA0_CTRL(x)        (SHIFT0(x) & PHY_M_LEDC_STA0_MSK)
8636 +
8637 +/*****  PHY_MARV_PHY_STAT (page 3)             16 bit r/w      Polarity Control Reg. *****/
8638 +#define PHY_M_POLC_LS1M_MSK    (0xf<<12)       /* Bit 15..12: LOS,STAT1 Mix % Mask */
8639 +#define PHY_M_POLC_IS0M_MSK    (0xf<<8)        /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
8640 +#define PHY_M_POLC_LOS_MSK     (0x3<<6)        /* Bit  7.. 6: LOS Pol. Ctrl. Mask */
8641 +#define PHY_M_POLC_INIT_MSK    (0x3<<4)        /* Bit  5.. 4: INIT Pol. Ctrl. Mask */
8642 +#define PHY_M_POLC_STA1_MSK    (0x3<<2)        /* Bit  3.. 2: STAT1 Pol. Ctrl. Mask */
8643 +#define PHY_M_POLC_STA0_MSK    0x3                     /* Bit  1.. 0: STAT0 Pol. Ctrl. Mask */
8644 +
8645 +#define PHY_M_POLC_LS1_P_MIX(x)        (SHIFT12(x) & PHY_M_POLC_LS1M_MSK)
8646 +#define PHY_M_POLC_IS0_P_MIX(x)        (SHIFT8(x) & PHY_M_POLC_IS0M_MSK)
8647 +#define PHY_M_POLC_LOS_CTRL(x) (SHIFT6(x) & PHY_M_POLC_LOS_MSK)
8648 +#define PHY_M_POLC_INIT_CTRL(x)        (SHIFT4(x) & PHY_M_POLC_INIT_MSK)
8649 +#define PHY_M_POLC_STA1_CTRL(x)        (SHIFT2(x) & PHY_M_POLC_STA1_MSK)
8650 +#define PHY_M_POLC_STA0_CTRL(x)        (SHIFT0(x) & PHY_M_POLC_STA0_MSK)
8651
8652  /*
8653   * GMAC registers
8654 @@ -1431,141 +1595,159 @@
8655   */
8656
8657  /*     GM_GP_STAT      16 bit r/o      General Purpose Status Register */
8658 -#define GM_GPSR_SPEED          (1<<15) /* Bit 15:      Port Speed (1 = 100 Mbps) */
8659 -#define GM_GPSR_DUPLEX         (1<<14) /* Bit 14:      Duplex Mode (1 = Full) */
8660 -#define GM_GPSR_FC_TX_DIS      (1<<13) /* Bit 13:      Tx Flow-Control Mode Disabled */
8661 -#define GM_GPSR_LINK_UP                (1<<12) /* Bit 12:      Link Up Status */
8662 -#define GM_GPSR_PAUSE          (1<<11) /* Bit 11:      Pause State */
8663 -#define GM_GPSR_TX_ACTIVE      (1<<10) /* Bit 10:      Tx in Progress */
8664 -#define GM_GPSR_EXC_COL                (1<<9)  /* Bit  9:      Excessive Collisions Occured */
8665 -#define GM_GPSR_LAT_COL                (1<<8)  /* Bit  8:      Late Collisions Occured */
8666 -                                                               /* Bit  7..6:   reserved */
8667 -#define GM_GPSR_PHY_ST_CH      (1<<5)  /* Bit  5:      PHY Status Change */
8668 -#define GM_GPSR_GIG_SPEED      (1<<4)  /* Bit  4:      Gigabit Speed (1 = 1000 Mbps) */
8669 -#define GM_GPSR_PART_MODE      (1<<3)  /* Bit  3:      Partition mode */
8670 -#define GM_GPSR_FC_RX_DIS      (1<<2)  /* Bit  2:      Rx Flow-Control Mode Disabled */
8671 -#define GM_GPSR_PROM_EN                (1<<1)  /* Bit  1:      Promiscuous Mode Enabled */
8672 -                                                               /* Bit  0:      reserved */
8673 -
8674 +#define GM_GPSR_SPEED          BIT_15S /* Port Speed (1 = 100 Mbps) */
8675 +#define GM_GPSR_DUPLEX         BIT_14S /* Duplex Mode (1 = Full) */
8676 +#define GM_GPSR_FC_TX_DIS      BIT_13S /* Tx Flow-Control Mode Disabled */
8677 +#define GM_GPSR_LINK_UP                BIT_12S /* Link Up Status */
8678 +#define GM_GPSR_PAUSE          BIT_11S /* Pause State */
8679 +#define GM_GPSR_TX_ACTIVE      BIT_10S /* Tx in Progress */
8680 +#define GM_GPSR_EXC_COL                BIT_9S  /* Excessive Collisions Occured */
8681 +#define GM_GPSR_LAT_COL                BIT_8S  /* Late Collisions Occured */
8682 +                                                               /* Bit   7.. 6: reserved */
8683 +#define GM_GPSR_PHY_ST_CH      BIT_5S  /* PHY Status Change */
8684 +#define GM_GPSR_GIG_SPEED      BIT_4S  /* Gigabit Speed (1 = 1000 Mbps) */
8685 +#define GM_GPSR_PART_MODE      BIT_3S  /* Partition mode */
8686 +#define GM_GPSR_FC_RX_DIS      BIT_2S  /* Rx Flow-Control Mode Disabled */
8687 +                                                               /* Bit   2.. 0: reserved */
8688 +
8689  /*     GM_GP_CTRL      16 bit r/w      General Purpose Control Register */
8690 -                                                               /* Bit 15:      reserved */
8691 -#define GM_GPCR_PROM_ENA       (1<<14) /* Bit 14:      Enable Promiscuous Mode */
8692 -#define GM_GPCR_FC_TX_DIS      (1<<13) /* Bit 13:      Disable Tx Flow-Control Mode */
8693 -#define GM_GPCR_TX_ENA         (1<<12) /* Bit 12:      Enable Transmit */
8694 -#define GM_GPCR_RX_ENA         (1<<11) /* Bit 11:      Enable Receive */
8695 -#define GM_GPCR_BURST_ENA      (1<<10) /* Bit 10:      Enable Burst Mode */
8696 -#define GM_GPCR_LOOP_ENA       (1<<9)  /* Bit  9:      Enable MAC Loopback Mode */
8697 -#define GM_GPCR_PART_ENA       (1<<8)  /* Bit  8:      Enable Partition Mode */
8698 -#define GM_GPCR_GIGS_ENA       (1<<7)  /* Bit  7:      Gigabit Speed (1000 Mbps) */
8699 -#define GM_GPCR_FL_PASS                (1<<6)  /* Bit  6:      Force Link Pass */
8700 -#define GM_GPCR_DUP_FULL       (1<<5)  /* Bit  5:      Full Duplex Mode */
8701 -#define GM_GPCR_FC_RX_DIS      (1<<4)  /* Bit  4:      Disable Rx Flow-Control Mode */
8702 -#define GM_GPCR_SPEED_100      (1<<3)  /* Bit  3:      Port Speed 100 Mbps */
8703 -#define GM_GPCR_AU_DUP_DIS     (1<<2)  /* Bit  2:      Disable Auto-Update Duplex */
8704 -#define GM_GPCR_AU_FCT_DIS     (1<<1)  /* Bit  1:      Disable Auto-Update Flow-C. */
8705 -#define GM_GPCR_AU_SPD_DIS     (1<<0)  /* Bit  0:      Disable Auto-Update Speed */
8706 +#define GM_GPCR_RMII_PH_ENA    BIT_15S /* Enable RMII for PHY (Yukon-FE only) */
8707 +#define GM_GPCR_RMII_LB_ENA    BIT_14S /* Enable RMII Loopback (Yukon-FE only) */
8708 +#define GM_GPCR_FC_TX_DIS      BIT_13S /* Disable Tx Flow-Control Mode */
8709 +#define GM_GPCR_TX_ENA         BIT_12S /* Enable Transmit */
8710 +#define GM_GPCR_RX_ENA         BIT_11S /* Enable Receive */
8711 +                                                               /* Bit 10:      reserved */
8712 +#define GM_GPCR_LOOP_ENA       BIT_9S  /* Enable MAC Loopback Mode */
8713 +#define GM_GPCR_PART_ENA       BIT_8S  /* Enable Partition Mode */
8714 +#define GM_GPCR_GIGS_ENA       BIT_7S  /* Gigabit Speed (1000 Mbps) */
8715 +#define GM_GPCR_FL_PASS                BIT_6S  /* Force Link Pass */
8716 +#define GM_GPCR_DUP_FULL       BIT_5S  /* Full Duplex Mode */
8717 +#define GM_GPCR_FC_RX_DIS      BIT_4S  /* Disable Rx Flow-Control Mode */
8718 +#define GM_GPCR_SPEED_100      BIT_3S  /* Port Speed 100 Mbps */
8719 +#define GM_GPCR_AU_DUP_DIS     BIT_2S  /* Disable Auto-Update Duplex */
8720 +#define GM_GPCR_AU_FCT_DIS     BIT_1S  /* Disable Auto-Update Flow-C. */
8721 +#define GM_GPCR_AU_SPD_DIS     BIT_0S  /* Disable Auto-Update Speed */
8722
8723  #define GM_GPCR_SPEED_1000     (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
8724  #define GM_GPCR_AU_ALL_DIS     (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |\
8725                                                          GM_GPCR_AU_SPD_DIS)
8726 -
8727 +
8728  /*     GM_TX_CTRL                              16 bit r/w      Transmit Control Register */
8729 -#define GM_TXCR_FORCE_JAM      (1<<15) /* Bit 15:      Force Jam / Flow-Control */
8730 -#define GM_TXCR_CRC_DIS                (1<<14) /* Bit 14:      Disable insertion of CRC */
8731 -#define GM_TXCR_PAD_DIS                (1<<13) /* Bit 13:      Disable padding of packets */
8732 -#define GM_TXCR_COL_THR_MSK    (7<<10) /* Bit 12..10:  Collision Threshold */
8733 +#define GM_TXCR_FORCE_JAM      BIT_15S /* Force Jam / Flow-Control */
8734 +#define GM_TXCR_CRC_DIS                BIT_14S /* Disable insertion of CRC */
8735 +#define GM_TXCR_PAD_DIS                BIT_13S /* Disable padding of packets */
8736 +#define GM_TXCR_COL_THR_MSK    (7<<10) /* Bit 12..10: Collision Threshold Mask */
8737 +                                                               /* Bit   9.. 8: reserved */
8738 +#define GM_TXCR_PAD_PAT_MSK    0xff    /* Bit  7.. 0: Padding Pattern Mask */
8739 +                                                                       /* (Yukon-2 only) */
8740
8741  #define TX_COL_THR(x)          (SHIFT10(x) & GM_TXCR_COL_THR_MSK)
8742
8743  #define TX_COL_DEF                     0x04
8744 -
8745 +
8746  /*     GM_RX_CTRL                              16 bit r/w      Receive Control Register */
8747 -#define GM_RXCR_UCF_ENA                (1<<15) /* Bit 15:      Enable Unicast filtering */
8748 -#define GM_RXCR_MCF_ENA                (1<<14) /* Bit 14:      Enable Multicast filtering */
8749 -#define GM_RXCR_CRC_DIS                (1<<13) /* Bit 13:      Remove 4-byte CRC */
8750 -#define GM_RXCR_PASS_FC                (1<<12) /* Bit 12:      Pass FC packets to FIFO */
8751 -
8752 +#define GM_RXCR_UCF_ENA                BIT_15S /* Enable Unicast filtering */
8753 +#define GM_RXCR_MCF_ENA                BIT_14S /* Enable Multicast filtering */
8754 +#define GM_RXCR_CRC_DIS                BIT_13S /* Remove 4-byte CRC */
8755 +#define GM_RXCR_PASS_FC                BIT_12S /* Pass FC packets to FIFO (Yukon-1 only) */
8756 +                                                               /* Bit  11.. 0: reserved */
8757 +
8758  /*     GM_TX_PARAM                             16 bit r/w      Transmit Parameter Register */
8759 -#define GM_TXPA_JAMLEN_MSK     (0x03<<14)      /* Bit 15..14:  Jam Length */
8760 -#define GM_TXPA_JAMIPG_MSK     (0x1f<<9)       /* Bit 13..9:   Jam IPG */
8761 -#define GM_TXPA_JAMDAT_MSK     (0x1f<<4)       /* Bit  8..4:   IPG Jam to Data */
8762 -                                                               /* Bit  3..0:   reserved */
8763 +#define GM_TXPA_JAMLEN_MSK     (3<<14)         /* Bit 15..14: Jam Length Mask */
8764 +#define GM_TXPA_JAMIPG_MSK     (0x1f<<9)       /* Bit 13.. 9: Jam IPG Mask */
8765 +#define GM_TXPA_JAMDAT_MSK     (0x1f<<4)       /* Bit  8.. 4: IPG Jam to Data Mask */
8766 +#define GM_TXPA_BO_LIM_MSK     0x0f            /* Bit  3.. 0: Backoff Limit Mask */
8767 +                                                                               /* (Yukon-2 only) */
8768
8769  #define TX_JAM_LEN_VAL(x)      (SHIFT14(x) & GM_TXPA_JAMLEN_MSK)
8770  #define TX_JAM_IPG_VAL(x)      (SHIFT9(x) & GM_TXPA_JAMIPG_MSK)
8771  #define TX_IPG_JAM_DATA(x)     (SHIFT4(x) & GM_TXPA_JAMDAT_MSK)
8772 +#define TX_BACK_OFF_LIM(x)     ((x) & GM_TXPA_BO_LIM_MSK)
8773
8774  #define TX_JAM_LEN_DEF         0x03
8775  #define TX_JAM_IPG_DEF         0x0b
8776  #define TX_IPG_JAM_DEF         0x1c
8777 +#define TX_BOF_LIM_DEF         0x04
8778
8779  /*     GM_SERIAL_MODE                  16 bit r/w      Serial Mode Register */
8780 -#define GM_SMOD_DATABL_MSK     (0x1f<<11)      /* Bit 15..11:  Data Blinder (r/o) */
8781 -#define GM_SMOD_LIMIT_4                (1<<10) /* Bit 10:      4 consecutive Tx trials */
8782 -#define GM_SMOD_VLAN_ENA       (1<<9)  /* Bit  9:      Enable VLAN  (Max. Frame Len) */
8783 -#define GM_SMOD_JUMBO_ENA      (1<<8)  /* Bit  8:      Enable Jumbo (Max. Frame Len) */
8784 -                                                               /* Bit  7..5:   reserved */
8785 -#define GM_SMOD_IPG_MSK                0x1f    /* Bit 4..0:    Inter-Packet Gap (IPG) */
8786 -
8787 +#define GM_SMOD_DATABL_MSK     (0x1f<<11)      /* Bit 15..11:  Data Blinder */
8788 +                                                                               /* r/o on Yukon, r/w on Yukon-EC */
8789 +#define GM_SMOD_LIMIT_4                BIT_10S /* 4 consecutive Tx trials */
8790 +#define GM_SMOD_VLAN_ENA       BIT_9S  /* Enable VLAN  (Max. Frame Len) */
8791 +#define GM_SMOD_JUMBO_ENA      BIT_8S  /* Enable Jumbo (Max. Frame Len) */
8792 +                                                               /* Bit   7.. 5: reserved */
8793 +#define GM_SMOD_IPG_MSK                0x1f    /* Bit  4.. 0:  Inter-Packet Gap (IPG) */
8794 +
8795  #define DATA_BLIND_VAL(x)      (SHIFT11(x) & GM_SMOD_DATABL_MSK)
8796 -#define DATA_BLIND_DEF         0x04
8797 +#define IPG_DATA_VAL(x)                ((x) & GM_SMOD_IPG_MSK)
8798
8799 -#define IPG_DATA_VAL(x)                (x & GM_SMOD_IPG_MSK)
8800 +#define DATA_BLIND_DEF         0x04
8801  #define IPG_DATA_DEF           0x1e
8802
8803  /*     GM_SMI_CTRL                             16 bit r/w      SMI Control Register */
8804  #define GM_SMI_CT_PHY_A_MSK    (0x1f<<11)      /* Bit 15..11:  PHY Device Address */
8805  #define GM_SMI_CT_REG_A_MSK    (0x1f<<6)       /* Bit 10.. 6:  PHY Register Address */
8806 -#define GM_SMI_CT_OP_RD                (1<<5)  /* Bit  5:      OpCode Read (0=Write)*/
8807 -#define GM_SMI_CT_RD_VAL       (1<<4)  /* Bit  4:      Read Valid (Read completed) */
8808 -#define GM_SMI_CT_BUSY         (1<<3)  /* Bit  3:      Busy (Operation in progress) */
8809 -                                                               /* Bit   2..0:  reserved */
8810 -
8811 +#define GM_SMI_CT_OP_RD                BIT_5S  /* OpCode Read (0=Write)*/
8812 +#define GM_SMI_CT_RD_VAL       BIT_4S  /* Read Valid (Read completed) */
8813 +#define GM_SMI_CT_BUSY         BIT_3S  /* Busy (Operation in progress) */
8814 +                                                               /* Bit   2.. 0: reserved */
8815 +
8816  #define GM_SMI_CT_PHY_AD(x)    (SHIFT11(x) & GM_SMI_CT_PHY_A_MSK)
8817  #define GM_SMI_CT_REG_AD(x)    (SHIFT6(x) & GM_SMI_CT_REG_A_MSK)
8818
8819 -       /*      GM_PHY_ADDR                             16 bit r/w      GPHY Address Register */
8820 -                                                               /* Bit  15..6:  reserved */
8821 -#define GM_PAR_MIB_CLR         (1<<5)  /* Bit  5:      Set MIB Clear Counter Mode */
8822 -#define GM_PAR_MIB_TST         (1<<4)  /* Bit  4:      MIB Load Counter (Test Mode) */
8823 -                                                               /* Bit   3..0:  reserved */
8824 -
8825 +/*     GM_PHY_ADDR                             16 bit r/w      GPHY Address Register */
8826 +                                                               /* Bit  15.. 6: reserved */
8827 +#define GM_PAR_MIB_CLR         BIT_5S  /* Set MIB Clear Counter Mode */
8828 +#define GM_PAR_MIB_TST         BIT_4S  /* MIB Load Counter (Test Mode) */
8829 +                                                               /* Bit   3.. 0: reserved */
8830 +
8831  /* Receive Frame Status Encoding */
8832 -#define GMR_FS_LEN     (0xffffUL<<16)  /* Bit 31..16:  Rx Frame Length */
8833 +#define GMR_FS_LEN_MSK (0xffffUL<<16)  /* Bit 31..16:  Rx Frame Length */
8834                                                                 /* Bit  15..14: reserved */
8835 -#define GMR_FS_VLAN            (1L<<13)        /* Bit 13:      VLAN Packet */
8836 -#define GMR_FS_JABBER  (1L<<12)        /* Bit 12:      Jabber Packet */
8837 -#define GMR_FS_UN_SIZE (1L<<11)        /* Bit 11:      Undersize Packet */
8838 -#define GMR_FS_MC              (1L<<10)        /* Bit 10:      Multicast Packet */
8839 -#define GMR_FS_BC              (1L<<9)         /* Bit  9:      Broadcast Packet */
8840 -#define GMR_FS_RX_OK   (1L<<8)         /* Bit  8:      Receive OK (Good Packet) */
8841 -#define GMR_FS_GOOD_FC (1L<<7)         /* Bit  7:      Good Flow-Control Packet */
8842 -#define GMR_FS_BAD_FC  (1L<<6)         /* Bit  6:      Bad  Flow-Control Packet */
8843 -#define GMR_FS_MII_ERR (1L<<5)         /* Bit  5:      MII Error */
8844 -#define GMR_FS_LONG_ERR        (1L<<4)         /* Bit  4:      Too Long Packet */
8845 -#define GMR_FS_FRAGMENT        (1L<<3)         /* Bit  3:      Fragment */
8846 +#define GMR_FS_VLAN                    BIT_13  /* VLAN Packet */
8847 +#define GMR_FS_JABBER          BIT_12  /* Jabber Packet */
8848 +#define GMR_FS_UN_SIZE         BIT_11  /* Undersize Packet */
8849 +#define GMR_FS_MC                      BIT_10  /* Multicast Packet */
8850 +#define GMR_FS_BC                      BIT_9   /* Broadcast Packet */
8851 +#define GMR_FS_RX_OK           BIT_8   /* Receive OK (Good Packet) */
8852 +#define GMR_FS_GOOD_FC         BIT_7   /* Good Flow-Control Packet */
8853 +#define GMR_FS_BAD_FC          BIT_6   /* Bad  Flow-Control Packet */
8854 +#define GMR_FS_MII_ERR         BIT_5   /* MII Error */
8855 +#define GMR_FS_LONG_ERR                BIT_4   /* Too Long Packet */
8856 +#define GMR_FS_FRAGMENT                BIT_3   /* Fragment */
8857                                                                 /* Bit  2:      reserved */
8858 -#define GMR_FS_CRC_ERR (1L<<1)         /* Bit  1:      CRC Error */
8859 -#define GMR_FS_RX_FF_OV        (1L<<0)         /* Bit  0:      Rx FIFO Overflow */
8860 +#define GMR_FS_CRC_ERR         BIT_1   /* CRC Error */
8861 +#define GMR_FS_RX_FF_OV                BIT_0   /* Rx FIFO Overflow */
8862 +
8863 +#define GMR_FS_LEN_SHIFT       16
8864
8865  /*
8866   * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR)
8867   */
8868 -#define GMR_FS_ANY_ERR (GMR_FS_CRC_ERR | \
8869 -                       GMR_FS_LONG_ERR | \
8870 +#ifdef SK_DIAG
8871 +#define GMR_FS_ANY_ERR         ( \
8872 +                       GMR_FS_RX_FF_OV | \
8873 +                       GMR_FS_CRC_ERR | \
8874 +                       GMR_FS_FRAGMENT | \
8875                         GMR_FS_MII_ERR | \
8876                         GMR_FS_BAD_FC | \
8877                         GMR_FS_GOOD_FC | \
8878                         GMR_FS_JABBER)
8879 -
8880 -/* Rx GMAC FIFO Flush Mask (default) */
8881 -#define RX_FF_FL_DEF_MSK       (GMR_FS_CRC_ERR | \
8882 +#else
8883 +#define GMR_FS_ANY_ERR         ( \
8884                         GMR_FS_RX_FF_OV | \
8885 +                       GMR_FS_CRC_ERR | \
8886 +                       GMR_FS_FRAGMENT | \
8887 +                       GMR_FS_LONG_ERR | \
8888                         GMR_FS_MII_ERR | \
8889                         GMR_FS_BAD_FC | \
8890                         GMR_FS_GOOD_FC | \
8891                         GMR_FS_UN_SIZE | \
8892                         GMR_FS_JABBER)
8893 +#endif
8894 +
8895 +/* Rx GMAC FIFO Flush Mask (default) */
8896 +#define RX_FF_FL_DEF_MSK       GMR_FS_ANY_ERR
8897
8898  /* typedefs *******************************************************************/
8899
8900 @@ -1577,3 +1759,4 @@
8901  #endif /* __cplusplus */
8902
8903  #endif /* __INC_XMAC_H */
8904 +
8905 diff -ruN linux/drivers/net/sk98lin/skaddr.c linux-new/drivers/net/sk98lin/skaddr.c
8906 --- linux/drivers/net/sk98lin/skaddr.c  2006-09-20 05:42:06.000000000 +0200
8907 +++ linux-new/drivers/net/sk98lin/skaddr.c      2006-07-28 14:13:54.000000000 +0200
8908 @@ -2,16 +2,17 @@
8909   *
8910   * Name:       skaddr.c
8911   * Project:    Gigabit Ethernet Adapters, ADDR-Module
8912 - * Version:    $Revision$
8913 - * Date:       $Date$
8914 + * Version:    $Revision$
8915 + * Date:       $Date$
8916   * Purpose:    Manage Addresses (Multicast and Unicast) and Promiscuous Mode.
8917   *
8918   ******************************************************************************/
8919
8920  /******************************************************************************
8921   *
8922 + *     LICENSE:
8923   *     (C)Copyright 1998-2002 SysKonnect GmbH.
8924 - *     (C)Copyright 2002-2003 Marvell.
8925 + *     (C)Copyright 2002-2005 Marvell.
8926   *
8927   *     This program is free software; you can redistribute it and/or modify
8928   *     it under the terms of the GNU General Public License as published by
8929 @@ -19,6 +20,7 @@
8930   *     (at your option) any later version.
8931   *
8932   *     The information in this file is provided "AS IS" without warranty.
8933 + *     /LICENSE
8934   *
8935   ******************************************************************************/
8936
8937 @@ -44,7 +46,7 @@
8938
8939  #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
8940  static const char SysKonnectFileId[] =
8941 -       "@(#) $Id$ (C) Marvell.";
8942 +       "@(#) $Id$ (C) Marvell.";
8943  #endif /* DEBUG ||!LINT || !SK_SLIM */
8944
8945  #define __SKADDR_C
8946 @@ -58,11 +60,10 @@
8947
8948  /* defines ********************************************************************/
8949
8950 -
8951  #define XMAC_POLY      0xEDB88320UL    /* CRC32-Poly - XMAC: Little Endian */
8952  #define GMAC_POLY      0x04C11DB7L     /* CRC16-Poly - GMAC: Little Endian */
8953  #define HASH_BITS      6                               /* #bits in hash */
8954 -#define        SK_MC_BIT       0x01
8955 +#define SK_MC_BIT      0x01
8956
8957  /* Error numbers and messages. */
8958
8959 @@ -79,7 +80,7 @@
8960
8961  /* 64-bit hash values with all bits set. */
8962
8963 -static const SK_U16    OnesHash[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
8964 +SK_U16 OnesHash[4] = {0xffff, 0xffff, 0xffff, 0xffff};
8965
8966  /* local variables ************************************************************/
8967
8968 @@ -87,21 +88,6 @@
8969  static int     Next0[SK_MAX_MACS] = {0};
8970  #endif /* DEBUG */
8971
8972 -static int SkAddrGmacMcAdd(SK_AC *pAC, SK_IOC IoC, SK_U32 PortNumber,
8973 -                          SK_MAC_ADDR *pMc, int Flags);
8974 -static int SkAddrGmacMcClear(SK_AC *pAC, SK_IOC IoC, SK_U32 PortNumber,
8975 -                            int Flags);
8976 -static int SkAddrGmacMcUpdate(SK_AC *pAC, SK_IOC IoC, SK_U32 PortNumber);
8977 -static int SkAddrGmacPromiscuousChange(SK_AC *pAC, SK_IOC IoC,
8978 -                                      SK_U32 PortNumber, int NewPromMode);
8979 -static int SkAddrXmacMcAdd(SK_AC *pAC, SK_IOC IoC, SK_U32 PortNumber,
8980 -                          SK_MAC_ADDR *pMc, int Flags);
8981 -static int SkAddrXmacMcClear(SK_AC *pAC, SK_IOC IoC, SK_U32 PortNumber,
8982 -                            int Flags);
8983 -static int SkAddrXmacMcUpdate(SK_AC *pAC, SK_IOC IoC, SK_U32 PortNumber);
8984 -static int SkAddrXmacPromiscuousChange(SK_AC *pAC, SK_IOC IoC,
8985 -                                      SK_U32 PortNumber, int NewPromMode);
8986 -
8987  /* functions ******************************************************************/
8988
8989  /******************************************************************************
8990 @@ -151,13 +137,12 @@
8991
8992         switch (Level) {
8993         case SK_INIT_DATA:
8994 -               SK_MEMSET((char *) &pAC->Addr, (SK_U8) 0,
8995 -            (SK_U16) sizeof(SK_ADDR));
8996 +               SK_MEMSET((char *)&pAC->Addr, (SK_U8)0, (SK_U16)sizeof(SK_ADDR));
8997
8998                 for (i = 0; i < SK_MAX_MACS; i++) {
8999                         pAPort = &pAC->Addr.Port[i];
9000                         pAPort->PromMode = SK_PROM_MODE_NONE;
9001 -
9002 +
9003                         pAPort->FirstExactMatchRlmt = SK_ADDR_FIRST_MATCH_RLMT;
9004                         pAPort->FirstExactMatchDrv = SK_ADDR_FIRST_MATCH_DRV;
9005                         pAPort->NextExactMatchRlmt = SK_ADDR_FIRST_MATCH_RLMT;
9006 @@ -174,7 +159,7 @@
9007                 /* pAC->Addr.InitDone = SK_INIT_DATA; */
9008                 break;
9009
9010 -    case SK_INIT_IO:
9011 +       case SK_INIT_IO:
9012  #ifndef SK_NO_RLMT
9013                 for (i = 0; i < SK_MAX_NETS; i++) {
9014                         pAC->Addr.Net[i].ActivePort = pAC->Rlmt.Net[i].ActivePort;
9015 @@ -188,7 +173,7 @@
9016                         }
9017                 }
9018  #endif /* DEBUG */
9019 -
9020 +
9021                 /* Read permanent logical MAC address from Control Register File. */
9022                 for (j = 0; j < SK_MAC_ADDR_LEN; j++) {
9023                         InAddr = (SK_U8 *) &pAC->Addr.Net[0].PermanentMacAddress.a[j];
9024 @@ -206,11 +191,11 @@
9025                 pAC->Addr.Port[pAC->Addr.Net[0].ActivePort].Exact[0] =
9026                         pAC->Addr.Net[0].CurrentMacAddress;
9027  #if SK_MAX_NETS > 1
9028 -               /* Set logical MAC address for net 2 to (log | 3). */
9029 +               /* Set logical MAC address for net 2 to. */
9030                 if (!pAC->Addr.Net[1].CurrentMacAddressSet) {
9031                         pAC->Addr.Net[1].PermanentMacAddress =
9032                                 pAC->Addr.Net[0].PermanentMacAddress;
9033 -                       pAC->Addr.Net[1].PermanentMacAddress.a[5] |= 3;
9034 +                       pAC->Addr.Net[1].PermanentMacAddress.a[5] += 1;
9035                         /* Set the current logical MAC address to the permanent one. */
9036                         pAC->Addr.Net[1].CurrentMacAddress =
9037                                 pAC->Addr.Net[1].PermanentMacAddress;
9038 @@ -228,8 +213,8 @@
9039                                         pAC->Addr.Net[i].PermanentMacAddress.a[2],
9040                                         pAC->Addr.Net[i].PermanentMacAddress.a[3],
9041                                         pAC->Addr.Net[i].PermanentMacAddress.a[4],
9042 -                                       pAC->Addr.Net[i].PermanentMacAddress.a[5]))
9043 -
9044 +                                       pAC->Addr.Net[i].PermanentMacAddress.a[5]));
9045 +
9046                         SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_INIT,
9047                                 ("Logical MAC Address (Net%d): %02X %02X %02X %02X %02X %02X\n",
9048                                         i,
9049 @@ -238,7 +223,7 @@
9050                                         pAC->Addr.Net[i].CurrentMacAddress.a[2],
9051                                         pAC->Addr.Net[i].CurrentMacAddress.a[3],
9052                                         pAC->Addr.Net[i].CurrentMacAddress.a[4],
9053 -                                       pAC->Addr.Net[i].CurrentMacAddress.a[5]))
9054 +                                       pAC->Addr.Net[i].CurrentMacAddress.a[5]));
9055                 }
9056  #endif /* DEBUG */
9057
9058 @@ -281,8 +266,8 @@
9059                                         pAPort->PermanentMacAddress.a[2],
9060                                         pAPort->PermanentMacAddress.a[3],
9061                                         pAPort->PermanentMacAddress.a[4],
9062 -                                       pAPort->PermanentMacAddress.a[5]))
9063 -
9064 +                                       pAPort->PermanentMacAddress.a[5]));
9065 +
9066                         SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_INIT,
9067                                 ("SkAddrInit: Physical MAC Address: %02X %02X %02X %02X %02X %02X\n",
9068                                         pAPort->CurrentMacAddress.a[0],
9069 @@ -290,7 +275,7 @@
9070                                         pAPort->CurrentMacAddress.a[2],
9071                                         pAPort->CurrentMacAddress.a[3],
9072                                         pAPort->CurrentMacAddress.a[4],
9073 -                                       pAPort->CurrentMacAddress.a[5]))
9074 +                                       pAPort->CurrentMacAddress.a[5]));
9075  #endif /* DEBUG */
9076                 }
9077                 /* pAC->Addr.InitDone = SK_INIT_IO; */
9078 @@ -314,7 +299,7 @@
9079         }
9080
9081         return (SK_ADDR_SUCCESS);
9082 -
9083 +
9084  }      /* SkAddrInit */
9085
9086  #ifndef SK_SLIM
9087 @@ -348,16 +333,20 @@
9088  int            Flags)          /* permanent/non-perm, sw-only */
9089  {
9090         int ReturnCode;
9091 -
9092 +
9093         if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
9094                 return (SK_ADDR_ILLEGAL_PORT);
9095         }
9096 -
9097 +
9098         if (pAC->GIni.GIGenesis) {
9099 +#ifdef GENESIS
9100                 ReturnCode = SkAddrXmacMcClear(pAC, IoC, PortNumber, Flags);
9101 +#endif
9102         }
9103         else {
9104 +#ifdef YUKON
9105                 ReturnCode = SkAddrGmacMcClear(pAC, IoC, PortNumber, Flags);
9106 +#endif
9107         }
9108
9109         return (ReturnCode);
9110 @@ -367,7 +356,7 @@
9111  #endif /* !SK_SLIM */
9112
9113  #ifndef SK_SLIM
9114 -
9115 +#ifdef GENESIS
9116  /******************************************************************************
9117   *
9118   *     SkAddrXmacMcClear - clear the multicast table
9119 @@ -387,7 +376,7 @@
9120   *     SK_ADDR_SUCCESS
9121   *     SK_ADDR_ILLEGAL_PORT
9122   */
9123 -static int     SkAddrXmacMcClear(
9124 +int    SkAddrXmacMcClear(
9125  SK_AC  *pAC,           /* adapter context */
9126  SK_IOC IoC,            /* I/O context */
9127  SK_U32 PortNumber,     /* Index of affected port */
9128 @@ -417,13 +406,13 @@
9129         }
9130
9131         return (SK_ADDR_SUCCESS);
9132 -
9133 -}      /* SkAddrXmacMcClear */
9134
9135 +}      /* SkAddrXmacMcClear */
9136 +#endif /* GENESIS */
9137  #endif /* !SK_SLIM */
9138
9139  #ifndef SK_SLIM
9140 -
9141 +#ifdef YUKON
9142  /******************************************************************************
9143   *
9144   *     SkAddrGmacMcClear - clear the multicast table
9145 @@ -444,7 +433,7 @@
9146   *     SK_ADDR_SUCCESS
9147   *     SK_ADDR_ILLEGAL_PORT
9148   */
9149 -static int     SkAddrGmacMcClear(
9150 +int    SkAddrGmacMcClear(
9151  SK_AC  *pAC,           /* adapter context */
9152  SK_IOC IoC,            /* I/O context */
9153  SK_U32 PortNumber,     /* Index of affected port */
9154 @@ -462,38 +451,37 @@
9155                         pAC->Addr.Port[PortNumber].InexactFilter.Bytes[4],
9156                         pAC->Addr.Port[PortNumber].InexactFilter.Bytes[5],
9157                         pAC->Addr.Port[PortNumber].InexactFilter.Bytes[6],
9158 -                       pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7]))
9159 +                       pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7]));
9160  #endif /* DEBUG */
9161
9162         /* Clear InexactFilter */
9163         for (i = 0; i < 8; i++) {
9164                 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] = 0;
9165         }
9166 -
9167 +
9168         if (Flags & SK_ADDR_PERMANENT) {        /* permanent => RLMT */
9169 -
9170 +
9171                 /* Copy DRV bits to InexactFilter. */
9172                 for (i = 0; i < 8; i++) {
9173                         pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |=
9174                                 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[i];
9175 -
9176 +
9177                         /* Clear InexactRlmtFilter. */
9178                         pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[i] = 0;
9179 -
9180 -               }
9181 +               }
9182         }
9183         else {  /* not permanent => DRV */
9184 -
9185 +
9186                 /* Copy RLMT bits to InexactFilter. */
9187                 for (i = 0; i < 8; i++) {
9188                         pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |=
9189                                 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[i];
9190 -
9191 +
9192                         /* Clear InexactDrvFilter. */
9193                         pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[i] = 0;
9194                 }
9195         }
9196 -
9197 +
9198  #ifdef DEBUG
9199         SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
9200                 ("GMAC InexactFilter (cleared): %02X %02X %02X %02X %02X %02X %02X %02X\n",
9201 @@ -504,19 +492,20 @@
9202                         pAC->Addr.Port[PortNumber].InexactFilter.Bytes[4],
9203                         pAC->Addr.Port[PortNumber].InexactFilter.Bytes[5],
9204                         pAC->Addr.Port[PortNumber].InexactFilter.Bytes[6],
9205 -                       pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7]))
9206 +                       pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7]));
9207  #endif /* DEBUG */
9208 -
9209 +
9210         if (!(Flags & SK_MC_SW_ONLY)) {
9211                 (void) SkAddrGmacMcUpdate(pAC, IoC, PortNumber);
9212         }
9213 -
9214 +
9215         return (SK_ADDR_SUCCESS);
9216
9217  }      /* SkAddrGmacMcClear */
9218 +#endif /* YUKON */
9219
9220  #ifndef SK_ADDR_CHEAT
9221 -
9222 +#ifdef GENESIS
9223  /******************************************************************************
9224   *
9225   *     SkXmacMcHash - hash multicast address
9226 @@ -534,7 +523,7 @@
9227   * Returns:
9228   *     Hash value of multicast address.
9229   */
9230 -static SK_U32 SkXmacMcHash(
9231 +SK_U32 SkXmacMcHash(
9232  unsigned char *pMc)    /* Multicast address */
9233  {
9234         SK_U32 Idx;
9235 @@ -553,8 +542,9 @@
9236         return (Crc & ((1 << HASH_BITS) - 1));
9237
9238  }      /* SkXmacMcHash */
9239 +#endif /* GENESIS */
9240
9241 -
9242 +#ifdef YUKON
9243  /******************************************************************************
9244   *
9245   *     SkGmacMcHash - hash multicast address
9246 @@ -572,7 +562,7 @@
9247   * Returns:
9248   *     Hash value of multicast address.
9249   */
9250 -static SK_U32 SkGmacMcHash(
9251 +SK_U32 SkGmacMcHash(
9252  unsigned char *pMc)    /* Multicast address */
9253  {
9254         SK_U32 Data;
9255 @@ -585,7 +575,7 @@
9256         for (Byte = 0; Byte < 6; Byte++) {
9257                 /* Get next byte. */
9258                 Data = (SK_U32) pMc[Byte];
9259 -
9260 +
9261                 /* Change bit order in byte. */
9262                 TmpData = Data;
9263                 for (Bit = 0; Bit < 8; Bit++) {
9264 @@ -597,7 +587,7 @@
9265                         }
9266                         TmpData >>= 1;
9267                 }
9268 -
9269 +
9270                 Crc ^= (Data << 24);
9271                 for (Bit = 0; Bit < 8; Bit++) {
9272                         if (Crc & 0x80000000) {
9273 @@ -608,11 +598,11 @@
9274                         }
9275                 }
9276         }
9277 -
9278 +
9279         return (Crc & ((1 << HASH_BITS) - 1));
9280
9281  }      /* SkGmacMcHash */
9282 -
9283 +#endif /* YUKON */
9284  #endif /* !SK_ADDR_CHEAT */
9285
9286  /******************************************************************************
9287 @@ -647,23 +637,27 @@
9288  int                    Flags)          /* permanent/non-permanent */
9289  {
9290         int ReturnCode;
9291 -
9292 +
9293         if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
9294                 return (SK_ADDR_ILLEGAL_PORT);
9295         }
9296 -
9297 +
9298         if (pAC->GIni.GIGenesis) {
9299 +#ifdef GENESIS
9300                 ReturnCode = SkAddrXmacMcAdd(pAC, IoC, PortNumber, pMc, Flags);
9301 +#endif
9302         }
9303         else {
9304 +#ifdef YUKON
9305                 ReturnCode = SkAddrGmacMcAdd(pAC, IoC, PortNumber, pMc, Flags);
9306 +#endif
9307         }
9308
9309         return (ReturnCode);
9310
9311  }      /* SkAddrMcAdd */
9312
9313 -
9314 +#ifdef GENESIS
9315  /******************************************************************************
9316   *
9317   *     SkAddrXmacMcAdd - add a multicast address to a port
9318 @@ -687,7 +681,7 @@
9319   *     SK_MC_ILLEGAL_ADDRESS
9320   *     SK_MC_RLMT_OVERFLOW
9321   */
9322 -static int     SkAddrXmacMcAdd(
9323 +int    SkAddrXmacMcAdd(
9324  SK_AC          *pAC,           /* adapter context */
9325  SK_IOC         IoC,            /* I/O context */
9326  SK_U32         PortNumber,     /* Port Number */
9327 @@ -708,7 +702,7 @@
9328                         return (SK_MC_RLMT_OVERFLOW);
9329                 }
9330  #endif /* DEBUG */
9331 -
9332 +
9333                 if (pAC->Addr.Port[PortNumber].NextExactMatchRlmt >
9334                         SK_ADDR_LAST_MATCH_RLMT) {
9335                         return (SK_MC_RLMT_OVERFLOW);
9336 @@ -729,7 +723,7 @@
9337                 return (SK_MC_RLMT_OVERFLOW);
9338         }
9339  #endif /* DEBUG */
9340 -
9341 +
9342         if (pAC->Addr.Port[PortNumber].NextExactMatchDrv <= SK_ADDR_LAST_MATCH_DRV) {
9343
9344                 /* Set exact match entry. */
9345 @@ -773,8 +767,9 @@
9346         }
9347
9348  }      /* SkAddrXmacMcAdd */
9349 +#endif /* GENESIS */
9350
9351 -
9352 +#ifdef YUKON
9353  /******************************************************************************
9354   *
9355   *     SkAddrGmacMcAdd - add a multicast address to a port
9356 @@ -793,7 +788,7 @@
9357   *     SK_MC_FILTERING_INEXACT
9358   *     SK_MC_ILLEGAL_ADDRESS
9359   */
9360 -static int     SkAddrGmacMcAdd(
9361 +int    SkAddrGmacMcAdd(
9362  SK_AC          *pAC,           /* adapter context */
9363  SK_IOC         IoC,            /* I/O context */
9364  SK_U32         PortNumber,     /* Port Number */
9365 @@ -804,28 +799,29 @@
9366  #ifndef SK_ADDR_CHEAT
9367         SK_U32 HashBit;
9368  #endif /* !defined(SK_ADDR_CHEAT) */
9369 -
9370 +
9371         if (!(pMc->a[0] & SK_MC_BIT)) {
9372                 /* Hashing only possible with multicast addresses */
9373                 return (SK_MC_ILLEGAL_ADDRESS);
9374         }
9375 -
9376 +
9377  #ifndef SK_ADDR_CHEAT
9378 -
9379 +
9380         /* Compute hash value of address. */
9381         HashBit = SkGmacMcHash(&pMc->a[0]);
9382 -
9383 +
9384         if (Flags & SK_ADDR_PERMANENT) {        /* permanent => RLMT */
9385 -
9386 +
9387                 /* Add bit to InexactRlmtFilter. */
9388                 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[HashBit / 8] |=
9389                         1 << (HashBit % 8);
9390 -
9391 +
9392                 /* Copy bit to InexactFilter. */
9393                 for (i = 0; i < 8; i++) {
9394                         pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |=
9395                                 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[i];
9396                 }
9397 +
9398  #ifdef DEBUG
9399                 SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
9400                 ("GMAC InexactRlmtFilter: %02X %02X %02X %02X %02X %02X %02X %02X\n",
9401 @@ -836,20 +832,21 @@
9402                         pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[4],
9403                         pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[5],
9404                         pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[6],
9405 -                       pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[7]))
9406 +                       pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[7]));
9407  #endif /* DEBUG */
9408         }
9409         else {  /* not permanent => DRV */
9410 -
9411 +
9412                 /* Add bit to InexactDrvFilter. */
9413                 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[HashBit / 8] |=
9414                         1 << (HashBit % 8);
9415 -
9416 +
9417                 /* Copy bit to InexactFilter. */
9418                 for (i = 0; i < 8; i++) {
9419                         pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |=
9420                                 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[i];
9421                 }
9422 +
9423  #ifdef DEBUG
9424                 SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
9425                 ("GMAC InexactDrvFilter: %02X %02X %02X %02X %02X %02X %02X %02X\n",
9426 @@ -860,22 +857,22 @@
9427                         pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[4],
9428                         pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[5],
9429                         pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[6],
9430 -                       pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[7]))
9431 +                       pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[7]));
9432  #endif /* DEBUG */
9433         }
9434 -
9435 +
9436  #else  /* SK_ADDR_CHEAT */
9437 -
9438 +
9439         /* Set all bits in InexactFilter. */
9440         for (i = 0; i < 8; i++) {
9441                 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] = 0xFF;
9442         }
9443  #endif /* SK_ADDR_CHEAT */
9444 -
9445 +
9446         return (SK_MC_FILTERING_INEXACT);
9447 -
9448 -}      /* SkAddrGmacMcAdd */
9449
9450 +}      /* SkAddrGmacMcAdd */
9451 +#endif /* YUKON */
9452  #endif /* !SK_SLIM */
9453
9454  /******************************************************************************
9455 @@ -907,7 +904,8 @@
9456  SK_IOC IoC,            /* I/O context */
9457  SK_U32 PortNumber)     /* Port Number */
9458  {
9459 -       int ReturnCode = 0;
9460 +       int ReturnCode = SK_ADDR_ILLEGAL_PORT;
9461 +
9462  #if (!defined(SK_SLIM) || defined(DEBUG))
9463         if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
9464                 return (SK_ADDR_ILLEGAL_PORT);
9465 @@ -952,7 +950,7 @@
9466   *     SK_MC_FILTERING_INEXACT
9467   *     SK_ADDR_ILLEGAL_PORT
9468   */
9469 -static int     SkAddrXmacMcUpdate(
9470 +int    SkAddrXmacMcUpdate(
9471  SK_AC  *pAC,           /* adapter context */
9472  SK_IOC IoC,            /* I/O context */
9473  SK_U32 PortNumber)     /* Port Number */
9474 @@ -963,13 +961,13 @@
9475         SK_ADDR_PORT    *pAPort;
9476
9477         SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
9478 -               ("SkAddrXmacMcUpdate on Port %u.\n", PortNumber))
9479 -
9480 +               ("SkAddrXmacMcUpdate on Port %u.\n", PortNumber));
9481 +
9482         pAPort = &pAC->Addr.Port[PortNumber];
9483
9484  #ifdef DEBUG
9485         SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
9486 -               ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber]))
9487 +               ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber]));
9488  #endif /* DEBUG */
9489
9490         /* Start with 0 to also program the logical MAC address. */
9491 @@ -981,7 +979,7 @@
9492
9493         /* Clear other permanent exact match addresses on XMAC */
9494         if (pAPort->NextExactMatchRlmt <= SK_ADDR_LAST_MATCH_RLMT) {
9495 -
9496 +
9497                 SkXmClrExactAddr(pAC, IoC, PortNumber, pAPort->NextExactMatchRlmt,
9498                         SK_ADDR_LAST_MATCH_RLMT);
9499         }
9500 @@ -993,7 +991,7 @@
9501
9502         /* Clear other non-permanent exact match addresses on XMAC */
9503         if (pAPort->NextExactMatchDrv <= SK_ADDR_LAST_MATCH_DRV) {
9504 -
9505 +
9506                 SkXmClrExactAddr(pAC, IoC, PortNumber, pAPort->NextExactMatchDrv,
9507                         SK_ADDR_LAST_MATCH_DRV);
9508         }
9509 @@ -1003,18 +1001,18 @@
9510         }
9511
9512         if (pAPort->PromMode & SK_PROM_MODE_ALL_MC) {
9513 -
9514 +
9515                 /* Set all bits in 64-bit hash register. */
9516                 XM_OUTHASH(IoC, PortNumber, XM_HSM, &OnesHash);
9517 -
9518 +
9519                 /* Enable Hashing */
9520                 SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
9521         }
9522         else if (Inexact != 0) {
9523 -
9524 +
9525                 /* Set 64-bit hash register to InexactFilter. */
9526                 XM_OUTHASH(IoC, PortNumber, XM_HSM, &pAPort->InexactFilter.Bytes[0]);
9527 -
9528 +
9529                 /* Enable Hashing */
9530                 SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
9531         }
9532 @@ -1029,7 +1027,7 @@
9533
9534         /* Set port's current physical MAC address. */
9535         OutAddr = (SK_U16 *) &pAPort->CurrentMacAddress.a[0];
9536 -
9537 +
9538         XM_OUTADDR(IoC, PortNumber, XM_SA, OutAddr);
9539
9540  #ifdef xDEBUG
9541 @@ -1039,9 +1037,9 @@
9542
9543                 /* Get exact match address i from port PortNumber. */
9544                 InAddr = (SK_U16 *) &InAddr8[0];
9545 -
9546 +
9547                 XM_INADDR(IoC, PortNumber, XM_EXM(i), InAddr);
9548 -
9549 +
9550                 SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
9551                         ("SkAddrXmacMcUpdate: MC address %d on Port %u: ",
9552                          "%02x %02x %02x %02x %02x %02x -- %02x %02x %02x %02x %02x %02x\n",
9553 @@ -1058,7 +1056,7 @@
9554                                 pAPort->Exact[i].a[2],
9555                                 pAPort->Exact[i].a[3],
9556                                 pAPort->Exact[i].a[4],
9557 -                               pAPort->Exact[i].a[5]))
9558 +                               pAPort->Exact[i].a[5]));
9559         }
9560  #endif /* DEBUG */
9561
9562 @@ -1069,7 +1067,7 @@
9563         else {
9564                 return (SK_MC_FILTERING_INEXACT);
9565         }
9566 -
9567 +
9568  }      /* SkAddrXmacMcUpdate */
9569
9570  #endif  /* GENESIS */
9571 @@ -1097,7 +1095,7 @@
9572   *     SK_MC_FILTERING_INEXACT
9573   *     SK_ADDR_ILLEGAL_PORT
9574   */
9575 -static int     SkAddrGmacMcUpdate(
9576 +int    SkAddrGmacMcUpdate(
9577  SK_AC  *pAC,           /* adapter context */
9578  SK_IOC IoC,            /* I/O context */
9579  SK_U32 PortNumber)     /* Port Number */
9580 @@ -1110,37 +1108,37 @@
9581         SK_ADDR_PORT    *pAPort;
9582
9583         SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
9584 -               ("SkAddrGmacMcUpdate on Port %u.\n", PortNumber))
9585 -
9586 +               ("SkAddrGmacMcUpdate on Port %u.\n", PortNumber));
9587 +
9588         pAPort = &pAC->Addr.Port[PortNumber];
9589
9590  #ifdef DEBUG
9591         SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
9592 -               ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber]))
9593 +               ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber]));
9594  #endif /* DEBUG */
9595 -
9596 +
9597  #ifndef SK_SLIM
9598         for (Inexact = 0, i = 0; i < 8; i++) {
9599                 Inexact |= pAPort->InexactFilter.Bytes[i];
9600         }
9601 -
9602 +
9603         /* Set 64-bit hash register to InexactFilter. */
9604         GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1,
9605                 &pAPort->InexactFilter.Bytes[0]);
9606 -
9607 -       if (pAPort->PromMode & SK_PROM_MODE_ALL_MC) {
9608 -
9609 +
9610 +       if (pAPort->PromMode & SK_PROM_MODE_ALL_MC) {
9611 +
9612                 /* Set all bits in 64-bit hash register. */
9613                 GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1, &OnesHash);
9614 -
9615 +
9616                 /* Enable Hashing */
9617                 SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
9618         }
9619 -       else {
9620 +       else {
9621                 /* Enable Hashing. */
9622                 SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
9623         }
9624 -
9625 +
9626         if (pAPort->PromMode != SK_PROM_MODE_NONE) {
9627                 (void) SkAddrGmacPromiscuousChange(pAC, IoC, PortNumber, pAPort->PromMode);
9628         }
9629 @@ -1151,19 +1149,19 @@
9630
9631         /* Enable Hashing */
9632         SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
9633 -
9634 +
9635         (void) SkAddrGmacPromiscuousChange(pAC, IoC, PortNumber, pAPort->PromMode);
9636 -
9637 +
9638  #endif /* SK_SLIM */
9639 -
9640 +
9641         /* Set port's current physical MAC address. */
9642         OutAddr = (SK_U16 *) &pAPort->CurrentMacAddress.a[0];
9643         GM_OUTADDR(IoC, PortNumber, GM_SRC_ADDR_1L, OutAddr);
9644 -
9645 +
9646         /* Set port's current logical MAC address. */
9647         OutAddr = (SK_U16 *) &pAPort->Exact[0].a[0];
9648         GM_OUTADDR(IoC, PortNumber, GM_SRC_ADDR_2L, OutAddr);
9649 -
9650 +
9651  #ifdef DEBUG
9652         SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
9653                 ("SkAddrGmacMcUpdate: Permanent Physical MAC Address: %02X %02X %02X %02X %02X %02X\n",
9654 @@ -1172,8 +1170,8 @@
9655                         pAPort->Exact[0].a[2],
9656                         pAPort->Exact[0].a[3],
9657                         pAPort->Exact[0].a[4],
9658 -                       pAPort->Exact[0].a[5]))
9659 -
9660 +                       pAPort->Exact[0].a[5]));
9661 +
9662         SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
9663                 ("SkAddrGmacMcUpdate: Physical MAC Address: %02X %02X %02X %02X %02X %02X\n",
9664                         pAPort->CurrentMacAddress.a[0],
9665 @@ -1181,9 +1179,9 @@
9666                         pAPort->CurrentMacAddress.a[2],
9667                         pAPort->CurrentMacAddress.a[3],
9668                         pAPort->CurrentMacAddress.a[4],
9669 -                       pAPort->CurrentMacAddress.a[5]))
9670 +                       pAPort->CurrentMacAddress.a[5]));
9671  #endif /* DEBUG */
9672 -
9673 +
9674  #ifndef SK_SLIM
9675         /* Determine return value. */
9676         if (Inexact == 0 && pAPort->PromMode == 0) {
9677 @@ -1195,7 +1193,7 @@
9678  #else /* SK_SLIM */
9679         return (SK_MC_FILTERING_INEXACT);
9680  #endif /* SK_SLIM */
9681 -
9682 +
9683  }      /* SkAddrGmacMcUpdate */
9684
9685  #endif /* YUKON */
9686 @@ -1243,6 +1241,11 @@
9687                 return (SK_ADDR_ILLEGAL_PORT);
9688         }
9689  #endif /* !SK_SLIM || DEBUG */
9690 +
9691 +       if (pNewAddr == NULL) {
9692 +               return (3);
9693 +       }
9694 +
9695         if (pNewAddr != NULL && (pNewAddr->a[0] & SK_MC_BIT) != 0) {
9696                 return (SK_ADDR_MULTICAST_ADDRESS);
9697         }
9698 @@ -1290,26 +1293,46 @@
9699                 (void) SkAddrMcUpdate(pAC, IoC, PortNumber);
9700         }
9701         else if (Flags & SK_ADDR_PHYSICAL_ADDRESS) {    /* Physical MAC address. */
9702 -               if (SK_ADDR_EQUAL(pNewAddr->a,
9703 -                       pAC->Addr.Net[NetNumber].CurrentMacAddress.a)) {
9704 -                       return (SK_ADDR_DUPLICATE_ADDRESS);
9705 -               }
9706 -
9707                 for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) {
9708                         if (!pAC->Addr.Port[i].CurrentMacAddressSet) {
9709                                 return (SK_ADDR_TOO_EARLY);
9710                         }
9711 +               }
9712
9713 +               /*
9714 +                * In dual net mode it should be possible to set all MAC
9715 +                * addresses independently. Therefore the equality checks
9716 +                * against the locical address of the same port and the
9717 +                * physical address of the other port are suppressed here.
9718 +                */
9719 +#ifndef SK_NO_RLMT
9720 +               if (pAC->Rlmt.NumNets == 1) {
9721 +#endif /* SK_NO_RLMT */
9722                         if (SK_ADDR_EQUAL(pNewAddr->a,
9723 -                               pAC->Addr.Port[i].CurrentMacAddress.a)) {
9724 -                               if (i == PortNumber) {
9725 -                                       return (SK_ADDR_SUCCESS);
9726 -                               }
9727 -                               else {
9728 -                                       return (SK_ADDR_DUPLICATE_ADDRESS);
9729 +                               pAC->Addr.Net[NetNumber].CurrentMacAddress.a)) {
9730 +                               return (SK_ADDR_DUPLICATE_ADDRESS);
9731 +                       }
9732 +
9733 +                       for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) {
9734 +                               if (SK_ADDR_EQUAL(pNewAddr->a,
9735 +                                       pAC->Addr.Port[i].CurrentMacAddress.a)) {
9736 +                                       if (i == PortNumber) {
9737 +                                               return (SK_ADDR_SUCCESS);
9738 +                                       }
9739 +                                       else {
9740 +                                               return (SK_ADDR_DUPLICATE_ADDRESS);
9741 +                                       }
9742                                 }
9743                         }
9744 +#ifndef SK_NO_RLMT
9745                 }
9746 +               else {
9747 +                       if (SK_ADDR_EQUAL(pNewAddr->a,
9748 +                               pAC->Addr.Port[PortNumber].CurrentMacAddress.a)) {
9749 +                               return (SK_ADDR_SUCCESS);
9750 +                       }
9751 +               }
9752 +#endif /* SK_NO_RLMT */
9753
9754                 pAC->Addr.Port[PortNumber].PreviousMacAddress =
9755                         pAC->Addr.Port[PortNumber].CurrentMacAddress;
9756 @@ -1340,18 +1363,32 @@
9757                         pAC->Addr.Net[NetNumber].CurrentMacAddress.a)) {
9758                         return (SK_ADDR_SUCCESS);
9759                 }
9760 -
9761 +
9762                 for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) {
9763                         if (!pAC->Addr.Port[i].CurrentMacAddressSet) {
9764                                 return (SK_ADDR_TOO_EARLY);
9765                         }
9766 +               }
9767
9768 -                       if (SK_ADDR_EQUAL(pNewAddr->a,
9769 -                               pAC->Addr.Port[i].CurrentMacAddress.a)) {
9770 -                               return (SK_ADDR_DUPLICATE_ADDRESS);
9771 +               /*
9772 +                * In dual net mode on Yukon-2 adapters the physical address
9773 +                * of port 0 and the logical address of port 1 are equal - in
9774 +                * this case the equality check of the physical address leads
9775 +                * to an error and is suppressed here.
9776 +                */
9777 +#ifndef SK_NO_RLMT
9778 +               if (pAC->Rlmt.NumNets == 1) {
9779 +#endif /* SK_NO_RLMT */
9780 +                       for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) {
9781 +                               if (SK_ADDR_EQUAL(pNewAddr->a,
9782 +                                       pAC->Addr.Port[i].CurrentMacAddress.a)) {
9783 +                                       return (SK_ADDR_DUPLICATE_ADDRESS);
9784 +                               }
9785                         }
9786 +#ifndef SK_NO_RLMT
9787                 }
9788 -
9789 +#endif /* SK_NO_RLMT */
9790 +
9791                 /*
9792                  * In case that the physical and the logical MAC addresses are equal
9793                  * we must also change the physical MAC address here.
9794 @@ -1360,11 +1397,11 @@
9795                  */
9796                 if (SK_ADDR_EQUAL(pAC->Addr.Port[PortNumber].CurrentMacAddress.a,
9797                                 pAC->Addr.Port[PortNumber].Exact[0].a)) {
9798 -
9799 +
9800                         pAC->Addr.Port[PortNumber].PreviousMacAddress =
9801                                 pAC->Addr.Port[PortNumber].CurrentMacAddress;
9802                         pAC->Addr.Port[PortNumber].CurrentMacAddress = *pNewAddr;
9803 -
9804 +
9805  #ifndef SK_NO_RLMT
9806                         /* Report address change to RLMT. */
9807                         Para.Para32[0] = PortNumber;
9808 @@ -1372,7 +1409,7 @@
9809                         SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_PORT_ADDR, Para);
9810  #endif /* !SK_NO_RLMT */
9811                 }
9812 -
9813 +
9814  #ifndef SK_NO_RLMT
9815                 /* Set PortNumber to number of net's active port. */
9816                 PortNumber = pAC->Rlmt.Net[NetNumber].
9817 @@ -1388,8 +1425,8 @@
9818                                 pAC->Addr.Net[NetNumber].PermanentMacAddress.a[2],
9819                                 pAC->Addr.Net[NetNumber].PermanentMacAddress.a[3],
9820                                 pAC->Addr.Net[NetNumber].PermanentMacAddress.a[4],
9821 -                               pAC->Addr.Net[NetNumber].PermanentMacAddress.a[5]))
9822 -
9823 +                               pAC->Addr.Net[NetNumber].PermanentMacAddress.a[5]));
9824 +
9825                 SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
9826                         ("SkAddrOverride: New logical MAC Address: %02X %02X %02X %02X %02X %02X\n",
9827                                 pAC->Addr.Net[NetNumber].CurrentMacAddress.a[0],
9828 @@ -1397,17 +1434,16 @@
9829                                 pAC->Addr.Net[NetNumber].CurrentMacAddress.a[2],
9830                                 pAC->Addr.Net[NetNumber].CurrentMacAddress.a[3],
9831                                 pAC->Addr.Net[NetNumber].CurrentMacAddress.a[4],
9832 -                               pAC->Addr.Net[NetNumber].CurrentMacAddress.a[5]))
9833 +                               pAC->Addr.Net[NetNumber].CurrentMacAddress.a[5]));
9834  #endif /* DEBUG */
9835
9836 -        /* Write address to first exact match entry of active port. */
9837 -               (void) SkAddrMcUpdate(pAC, IoC, PortNumber);
9838 +               /* Write address to first exact match entry of active port. */
9839 +               (void)SkAddrMcUpdate(pAC, IoC, PortNumber);
9840         }
9841
9842         return (SK_ADDR_SUCCESS);
9843 -
9844 -}      /* SkAddrOverride */
9845
9846 +}      /* SkAddrOverride */
9847
9848  #endif /* SK_NO_MAO */
9849
9850 @@ -1439,7 +1475,8 @@
9851  SK_U32 PortNumber,             /* port whose promiscuous mode changes */
9852  int            NewPromMode)    /* new promiscuous mode */
9853  {
9854 -       int ReturnCode = 0;
9855 +       int ReturnCode = SK_ADDR_ILLEGAL_PORT;
9856 +
9857  #if (!defined(SK_SLIM) || defined(DEBUG))
9858         if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
9859                 return (SK_ADDR_ILLEGAL_PORT);
9860 @@ -1483,7 +1520,7 @@
9861   *     SK_ADDR_SUCCESS
9862   *     SK_ADDR_ILLEGAL_PORT
9863   */
9864 -static int     SkAddrXmacPromiscuousChange(
9865 +int    SkAddrXmacPromiscuousChange(
9866  SK_AC  *pAC,                   /* adapter context */
9867  SK_IOC IoC,                    /* I/O context */
9868  SK_U32 PortNumber,             /* port whose promiscuous mode changes */
9869 @@ -1504,17 +1541,18 @@
9870                 /* Promiscuous mode! */
9871                 CurPromMode |= SK_PROM_MODE_LLC;
9872         }
9873 -
9874 +
9875         for (Inexact = 0xFF, i = 0; i < 8; i++) {
9876                 Inexact &= pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i];
9877         }
9878 +
9879         if (Inexact == 0xFF) {
9880                 CurPromMode |= (pAC->Addr.Port[PortNumber].PromMode & SK_PROM_MODE_ALL_MC);
9881         }
9882         else {
9883                 /* Get InexactModeBit (bit XM_MD_ENA_HASH in mode register) */
9884                 XM_IN16(IoC, PortNumber, XM_MODE, &LoMode);
9885 -
9886 +
9887                 InexactModeBit = (LoMode & XM_MD_ENA_HASH) != 0;
9888
9889                 /* Read 64-bit hash register from XMAC */
9890 @@ -1537,7 +1575,7 @@
9891
9892         if ((NewPromMode & SK_PROM_MODE_ALL_MC) &&
9893                 !(CurPromMode & SK_PROM_MODE_ALL_MC)) { /* All MC. */
9894 -
9895 +
9896                 /* Set all bits in 64-bit hash register. */
9897                 XM_OUTHASH(IoC, PortNumber, XM_HSM, &OnesHash);
9898
9899 @@ -1573,9 +1611,9 @@
9900                 /* Clear Promiscuous Mode */
9901                 SkMacPromiscMode(pAC, IoC, (int) PortNumber, SK_FALSE);
9902         }
9903 -
9904 +
9905         return (SK_ADDR_SUCCESS);
9906 -
9907 +
9908  }      /* SkAddrXmacPromiscuousChange */
9909
9910  #endif /* GENESIS */
9911 @@ -1600,70 +1638,42 @@
9912   *     SK_ADDR_SUCCESS
9913   *     SK_ADDR_ILLEGAL_PORT
9914   */
9915 -static int     SkAddrGmacPromiscuousChange(
9916 +int    SkAddrGmacPromiscuousChange(
9917  SK_AC  *pAC,                   /* adapter context */
9918  SK_IOC IoC,                    /* I/O context */
9919  SK_U32 PortNumber,             /* port whose promiscuous mode changes */
9920  int            NewPromMode)    /* new promiscuous mode */
9921  {
9922 -       SK_U16          ReceiveControl; /* GMAC Receive Control Register */
9923 -       int             CurPromMode = SK_PROM_MODE_NONE;
9924 -
9925 -       /* Read CurPromMode from Hardware. */
9926 -       GM_IN16(IoC, PortNumber, GM_RX_CTRL, &ReceiveControl);
9927 -
9928 -       if ((ReceiveControl & (GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA)) == 0) {
9929 -               /* Promiscuous mode! */
9930 -               CurPromMode |= SK_PROM_MODE_LLC;
9931 +       if (PortNumber >= (SK_U32)pAC->GIni.GIMacsFound) {
9932 +               return (SK_ADDR_ILLEGAL_PORT);
9933         }
9934
9935 -       if ((ReceiveControl & GM_RXCR_MCF_ENA) == 0) {
9936 -               /* All Multicast mode! */
9937 -               CurPromMode |= (pAC->Addr.Port[PortNumber].PromMode & SK_PROM_MODE_ALL_MC);
9938 -       }
9939 +       switch(NewPromMode) {
9940 +       case (SK_PROM_MODE_NONE):                                                       /* 0 */
9941
9942 -       pAC->Addr.Port[PortNumber].PromMode = NewPromMode;
9943 +               /* Normal receive mode */
9944 +               SkMacPromiscMode(pAC, IoC, (int) PortNumber, SK_FALSE);
9945 +               break;
9946
9947 -       if (NewPromMode == CurPromMode) {
9948 -               return (SK_ADDR_SUCCESS);
9949 -       }
9950 -
9951 -       if ((NewPromMode & SK_PROM_MODE_ALL_MC) &&
9952 -               !(CurPromMode & SK_PROM_MODE_ALL_MC)) { /* All MC */
9953 -
9954 -               /* Set all bits in 64-bit hash register. */
9955 -               GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1, &OnesHash);
9956 -
9957 -               /* Enable Hashing */
9958 -               SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
9959 -       }
9960 -
9961 -       if ((CurPromMode & SK_PROM_MODE_ALL_MC) &&
9962 -               !(NewPromMode & SK_PROM_MODE_ALL_MC)) { /* Norm. MC */
9963 +       case (SK_PROM_MODE_LLC):                                                        /* 1 */
9964 +               /* This mode is ignored and mapped to prom. mode */
9965 +       case (SK_PROM_MODE_LLC | SK_PROM_MODE_ALL_MC):          /* 3 */
9966
9967 -               /* Set 64-bit hash register to InexactFilter. */
9968 -               GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1,
9969 -                       &pAC->Addr.Port[PortNumber].InexactFilter.Bytes[0]);
9970 +               /* Set the MAC to promiscuous mode. */
9971 +               SkMacPromiscMode(pAC, IoC, (int) PortNumber, SK_TRUE);
9972 +               break;
9973
9974 -               /* Enable Hashing. */
9975 -               SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
9976 -       }
9977 +       case (SK_PROM_MODE_ALL_MC):                                                     /* 2 */
9978
9979 -       if ((NewPromMode & SK_PROM_MODE_LLC) &&
9980 -               !(CurPromMode & SK_PROM_MODE_LLC)) {    /* Prom. LLC */
9981 -
9982 -               /* Set the MAC to Promiscuous Mode. */
9983 -               SkMacPromiscMode(pAC, IoC, (int) PortNumber, SK_TRUE);
9984 -       }
9985 -       else if ((CurPromMode & SK_PROM_MODE_LLC) &&
9986 -               !(NewPromMode & SK_PROM_MODE_LLC)) {    /* Norm. LLC */
9987 -
9988 -               /* Clear Promiscuous Mode. */
9989 -               SkMacPromiscMode(pAC, IoC, (int) PortNumber, SK_FALSE);
9990 +               /* Disable MC hashing */
9991 +               SkMacHashing(pAC, IoC, (int) PortNumber, SK_FALSE);
9992 +               break;
9993 +
9994 +       default:
9995 +               break;
9996         }
9997
9998         return (SK_ADDR_SUCCESS);
9999 -
10000  }      /* SkAddrGmacPromiscuousChange */
10001
10002  #endif /* YUKON */
10003 @@ -1735,33 +1745,33 @@
10004                         pAC->Addr.Port[ToPortNumber].InexactFilter.Bytes[i];
10005                 pAC->Addr.Port[ToPortNumber].InexactFilter.Bytes[i] = Byte;
10006         }
10007 -
10008 +
10009         i = pAC->Addr.Port[FromPortNumber].PromMode;
10010         pAC->Addr.Port[FromPortNumber].PromMode = pAC->Addr.Port[ToPortNumber].PromMode;
10011         pAC->Addr.Port[ToPortNumber].PromMode = i;
10012 -
10013 +
10014         if (pAC->GIni.GIGenesis) {
10015                 DWord = pAC->Addr.Port[FromPortNumber].FirstExactMatchRlmt;
10016                 pAC->Addr.Port[FromPortNumber].FirstExactMatchRlmt =
10017                         pAC->Addr.Port[ToPortNumber].FirstExactMatchRlmt;
10018                 pAC->Addr.Port[ToPortNumber].FirstExactMatchRlmt = DWord;
10019 -
10020 +
10021                 DWord = pAC->Addr.Port[FromPortNumber].NextExactMatchRlmt;
10022                 pAC->Addr.Port[FromPortNumber].NextExactMatchRlmt =
10023                         pAC->Addr.Port[ToPortNumber].NextExactMatchRlmt;
10024                 pAC->Addr.Port[ToPortNumber].NextExactMatchRlmt = DWord;
10025 -
10026 +
10027                 DWord = pAC->Addr.Port[FromPortNumber].FirstExactMatchDrv;
10028                 pAC->Addr.Port[FromPortNumber].FirstExactMatchDrv =
10029                         pAC->Addr.Port[ToPortNumber].FirstExactMatchDrv;
10030                 pAC->Addr.Port[ToPortNumber].FirstExactMatchDrv = DWord;
10031 -
10032 +
10033                 DWord = pAC->Addr.Port[FromPortNumber].NextExactMatchDrv;
10034                 pAC->Addr.Port[FromPortNumber].NextExactMatchDrv =
10035                         pAC->Addr.Port[ToPortNumber].NextExactMatchDrv;
10036                 pAC->Addr.Port[ToPortNumber].NextExactMatchDrv = DWord;
10037         }
10038 -
10039 +
10040         /* CAUTION: Solution works if only ports of one adapter are in use. */
10041         for (i = 0; (SK_U32) i < pAC->Rlmt.Net[pAC->Rlmt.Port[ToPortNumber].
10042                 Net->NetNumber].NumPorts; i++) {
10043 @@ -1772,12 +1782,12 @@
10044                         /* 20001207 RA: Was "ToPortNumber;". */
10045                 }
10046         }
10047 -
10048 +
10049         (void) SkAddrMcUpdate(pAC, IoC, FromPortNumber);
10050         (void) SkAddrMcUpdate(pAC, IoC, ToPortNumber);
10051
10052         return (SK_ADDR_SUCCESS);
10053 -
10054 +
10055  }      /* SkAddrSwap */
10056
10057  #endif /* !SK_SLIM */
10058 diff -ruN linux/drivers/net/sk98lin/skcsum.c linux-new/drivers/net/sk98lin/skcsum.c
10059 --- linux/drivers/net/sk98lin/skcsum.c  1970-01-01 01:00:00.000000000 +0100
10060 +++ linux-new/drivers/net/sk98lin/skcsum.c      2006-07-28 14:13:54.000000000 +0200
10061 @@ -0,0 +1,873 @@
10062 +/******************************************************************************
10063 + *
10064 + * Name:       skcsum.c
10065 + * Project:    GEnesis, PCI Gigabit Ethernet Adapter
10066 + * Version:    $Revision$
10067 + * Date:       $Date$
10068 + * Purpose:    Store/verify Internet checksum in send/receive packets.
10069 + *
10070 + ******************************************************************************/
10071 +
10072 +/******************************************************************************
10073 + *
10074 + *     LICENSE:
10075 + *     (C)Copyright 1998-2003 SysKonnect GmbH.
10076 + *
10077 + *     This program is free software; you can redistribute it and/or modify
10078 + *     it under the terms of the GNU General Public License as published by
10079 + *     the Free Software Foundation; either version 2 of the License, or
10080 + *     (at your option) any later version.
10081 + *
10082 + *     The information in this file is provided "AS IS" without warranty.
10083 + *     /LICENSE
10084 + *
10085 + ******************************************************************************/
10086 +
10087 +#ifdef SK_USE_CSUM     /* Check if CSUM is to be used. */
10088 +
10089 +#ifndef lint
10090 +static const char SysKonnectFileId[] =
10091 +       "@(#) $Id$ (C) SysKonnect.";
10092 +#endif /* !lint */
10093 +
10094 +/******************************************************************************
10095 + *
10096 + * Description:
10097 + *
10098 + * This is the "GEnesis" common module "CSUM".
10099 + *
10100 + * This module contains the code necessary to calculate, store, and verify the
10101 + * Internet Checksum of IP, TCP, and UDP frames.
10102 + *
10103 + * "GEnesis" is an abbreviation of "Gigabit Ethernet Network System in Silicon"
10104 + * and is the code name of this SysKonnect project.
10105 + *
10106 + * Compilation Options:
10107 + *
10108 + *     SK_USE_CSUM - Define if CSUM is to be used. Otherwise, CSUM will be an
10109 + *     empty module.
10110 + *
10111 + *     SKCS_OVERWRITE_PROTO - Define to overwrite the default protocol id
10112 + *     definitions. In this case, all SKCS_PROTO_xxx definitions must be made
10113 + *     external.
10114 + *
10115 + *     SKCS_OVERWRITE_STATUS - Define to overwrite the default return status
10116 + *     definitions. In this case, all SKCS_STATUS_xxx definitions must be made
10117 + *     external.
10118 + *
10119 + * Include File Hierarchy:
10120 + *
10121 + *     "h/skdrv1st.h"
10122 + *     "h/skcsum.h"
10123 + *     "h/sktypes.h"
10124 + *     "h/skqueue.h"
10125 + *     "h/skdrv2nd.h"
10126 + *
10127 + ******************************************************************************/
10128 +
10129 +#include "h/skdrv1st.h"
10130 +#include "h/skcsum.h"
10131 +#include "h/skdrv2nd.h"
10132 +
10133 +/* defines ********************************************************************/
10134 +
10135 +/* The size of an Ethernet MAC header. */
10136 +#define SKCS_ETHERNET_MAC_HEADER_SIZE                  (6+6+2)
10137 +
10138 +/* The size of the used topology's MAC header. */
10139 +#define        SKCS_MAC_HEADER_SIZE    SKCS_ETHERNET_MAC_HEADER_SIZE
10140 +
10141 +/* The size of the IP header without any option fields. */
10142 +#define SKCS_IP_HEADER_SIZE                                            20
10143 +
10144 +/*
10145 + * Field offsets within the IP header.
10146 + */
10147 +
10148 +/* "Internet Header Version" and "Length". */
10149 +#define SKCS_OFS_IP_HEADER_VERSION_AND_LENGTH  0
10150 +
10151 +/* "Total Length". */
10152 +#define SKCS_OFS_IP_TOTAL_LENGTH                               2
10153 +
10154 +/* "Flags" "Fragment Offset". */
10155 +#define SKCS_OFS_IP_FLAGS_AND_FRAGMENT_OFFSET  6
10156 +
10157 +/* "Next Level Protocol" identifier. */
10158 +#define SKCS_OFS_IP_NEXT_LEVEL_PROTOCOL                        9
10159 +
10160 +/* Source IP address. */
10161 +#define SKCS_OFS_IP_SOURCE_ADDRESS                             12
10162 +
10163 +/* Destination IP address. */
10164 +#define SKCS_OFS_IP_DESTINATION_ADDRESS                        16
10165 +
10166 +
10167 +/*
10168 + * Field offsets within the UDP header.
10169 + */
10170 +
10171 +/* UDP checksum. */
10172 +#define SKCS_OFS_UDP_CHECKSUM                                  6
10173 +
10174 +/* IP "Next Level Protocol" identifiers (see RFC 790). */
10175 +#define SKCS_PROTO_ID_TCP              6       /* Transport Control Protocol */
10176 +#define SKCS_PROTO_ID_UDP              17      /* User Datagram Protocol */
10177 +
10178 +/* IP "Don't Fragment" bit. */
10179 +#define SKCS_IP_DONT_FRAGMENT  SKCS_HTON16(0x4000)
10180 +
10181 +/* Add a byte offset to a pointer. */
10182 +#define SKCS_IDX(pPtr, Ofs)    ((void *) ((char *) (pPtr) + (Ofs)))
10183 +
10184 +/*
10185 + * Macros that convert host to network representation and vice versa, i.e.
10186 + * little/big endian conversion on little endian machines only.
10187 + */
10188 +#ifdef SK_LITTLE_ENDIAN
10189 +#define SKCS_HTON16(Val16)     (((unsigned) (Val16) >> 8) | (((Val16) & 0xff) << 8))
10190 +#endif /* SK_LITTLE_ENDIAN */
10191 +#ifdef SK_BIG_ENDIAN
10192 +#define SKCS_HTON16(Val16)     (Val16)
10193 +#endif /* SK_BIG_ENDIAN */
10194 +#define SKCS_NTOH16(Val16)     SKCS_HTON16(Val16)
10195 +
10196 +/* typedefs *******************************************************************/
10197 +
10198 +/* function prototypes ********************************************************/
10199 +
10200 +/******************************************************************************
10201 + *
10202 + *     SkCsGetSendInfo - get checksum information for a send packet
10203 + *
10204 + * Description:
10205 + *     Get all checksum information necessary to send a TCP or UDP packet. The
10206 + *     function checks the IP header passed to it. If the high-level protocol
10207 + *     is either TCP or UDP the pseudo header checksum is calculated and
10208 + *     returned.
10209 + *
10210 + *     The function returns the total length of the IP header (including any
10211 + *     IP option fields), which is the same as the start offset of the IP data
10212 + *     which in turn is the start offset of the TCP or UDP header.
10213 + *
10214 + *     The function also returns the TCP or UDP pseudo header checksum, which
10215 + *     should be used as the start value for the hardware checksum calculation.
10216 + *     (Note that any actual pseudo header checksum can never calculate to
10217 + *     zero.)
10218 + *
10219 + * Note:
10220 + *     There is a bug in the GENESIS ASIC which may lead to wrong checksums.
10221 + *
10222 + * Arguments:
10223 + *     pAc - A pointer to the adapter context struct.
10224 + *
10225 + *     pIpHeader - Pointer to IP header. Must be at least the IP header *not*
10226 + *     including any option fields, i.e. at least 20 bytes.
10227 + *
10228 + *     Note: This pointer will be used to address 8-, 16-, and 32-bit
10229 + *     variables with the respective alignment offsets relative to the pointer.
10230 + *     Thus, the pointer should point to a 32-bit aligned address. If the
10231 + *     target system cannot address 32-bit variables on non 32-bit aligned
10232 + *     addresses, then the pointer *must* point to a 32-bit aligned address.
10233 + *
10234 + *     pPacketInfo - A pointer to the packet information structure for this
10235 + *     packet. Before calling this SkCsGetSendInfo(), the following field must
10236 + *     be initialized:
10237 + *
10238 + *             ProtocolFlags - Initialize with any combination of
10239 + *             SKCS_PROTO_XXX bit flags. SkCsGetSendInfo() will only work on
10240 + *             the protocols specified here. Any protocol(s) not specified
10241 + *             here will be ignored.
10242 + *
10243 + *             Note: Only one checksum can be calculated in hardware. Thus, if
10244 + *             SKCS_PROTO_IP is specified in the 'ProtocolFlags',
10245 + *             SkCsGetSendInfo() must calculate the IP header checksum in
10246 + *             software. It might be a better idea to have the calling
10247 + *             protocol stack calculate the IP header checksum.
10248 + *
10249 + * Returns: N/A
10250 + *     On return, the following fields in 'pPacketInfo' may or may not have
10251 + *     been filled with information, depending on the protocol(s) found in the
10252 + *     packet:
10253 + *
10254 + *     ProtocolFlags - Returns the SKCS_PROTO_XXX bit flags of the protocol(s)
10255 + *     that were both requested by the caller and actually found in the packet.
10256 + *     Protocol(s) not specified by the caller and/or not found in the packet
10257 + *     will have their respective SKCS_PROTO_XXX bit flags reset.
10258 + *
10259 + *     Note: For IP fragments, TCP and UDP packet information is ignored.
10260 + *
10261 + *     IpHeaderLength - The total length in bytes of the complete IP header
10262 + *     including any option fields is returned here. This is the start offset
10263 + *     of the IP data, i.e. the TCP or UDP header if present.
10264 + *
10265 + *     IpHeaderChecksum - If IP has been specified in the 'ProtocolFlags', the
10266 + *     16-bit Internet Checksum of the IP header is returned here. This value
10267 + *     is to be stored into the packet's 'IP Header Checksum' field.
10268 + *
10269 + *     PseudoHeaderChecksum - If this is a TCP or UDP packet and if TCP or UDP
10270 + *     has been specified in the 'ProtocolFlags', the 16-bit Internet Checksum
10271 + *     of the TCP or UDP pseudo header is returned here.
10272 + */
10273 +void SkCsGetSendInfo(
10274 +SK_AC                          *pAc,                   /* Adapter context struct. */
10275 +void                           *pIpHeader,             /* IP header. */
10276 +SKCS_PACKET_INFO       *pPacketInfo,   /* Packet information struct. */
10277 +int                                    NetNumber)              /* Net number */
10278 +{
10279 +       /* Internet Header Version found in IP header. */
10280 +       unsigned InternetHeaderVersion;
10281 +
10282 +       /* Length of the IP header as found in IP header. */
10283 +       unsigned IpHeaderLength;
10284 +
10285 +       /* Bit field specifiying the desired/found protocols. */
10286 +       unsigned ProtocolFlags;
10287 +
10288 +       /* Next level protocol identifier found in IP header. */
10289 +       unsigned NextLevelProtocol;
10290 +
10291 +       /* Length of IP data portion. */
10292 +       unsigned IpDataLength;
10293 +
10294 +       /* TCP/UDP pseudo header checksum. */
10295 +       unsigned long PseudoHeaderChecksum;
10296 +
10297 +       /* Pointer to next level protocol statistics structure. */
10298 +       SKCS_PROTO_STATS *NextLevelProtoStats;
10299 +
10300 +       /* Temporary variable. */
10301 +       unsigned Tmp;
10302 +
10303 +       Tmp = *(SK_U8 *)
10304 +               SKCS_IDX(pIpHeader, SKCS_OFS_IP_HEADER_VERSION_AND_LENGTH);
10305 +
10306 +       /* Get the Internet Header Version (IHV). */
10307 +       /* Note: The IHV is stored in the upper four bits. */
10308 +
10309 +       InternetHeaderVersion = Tmp >> 4;
10310 +
10311 +       /* Check the Internet Header Version. */
10312 +       /* Note: We currently only support IP version 4. */
10313 +
10314 +       if (InternetHeaderVersion != 4) {       /* IPv4? */
10315 +               SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_TX,
10316 +                       ("Tx: Unknown Internet Header Version %u.\n",
10317 +                       InternetHeaderVersion));
10318 +               pPacketInfo->ProtocolFlags = 0;
10319 +               pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].TxUnableCts++;
10320 +               return;
10321 +       }
10322 +
10323 +       /* Get the IP header length (IHL). */
10324 +       /*
10325 +        * Note: The IHL is stored in the lower four bits as the number of
10326 +        * 4-byte words.
10327 +        */
10328 +
10329 +       IpHeaderLength = (Tmp & 0xf) * 4;
10330 +       pPacketInfo->IpHeaderLength = IpHeaderLength;
10331 +
10332 +       /* Check the IP header length. */
10333 +
10334 +       /* 04-Aug-1998 sw - Really check the IHL? Necessary? */
10335 +
10336 +       if (IpHeaderLength < 5*4) {
10337 +               SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_TX,
10338 +                       ("Tx: Invalid IP Header Length %u.\n", IpHeaderLength));
10339 +               pPacketInfo->ProtocolFlags = 0;
10340 +               pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].TxUnableCts++;
10341 +               return;
10342 +       }
10343 +
10344 +       /* This is an IPv4 frame with a header of valid length. */
10345 +
10346 +       pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].TxOkCts++;
10347 +
10348 +       /* Check if we should calculate the IP header checksum. */
10349 +
10350 +       ProtocolFlags = pPacketInfo->ProtocolFlags;
10351 +
10352 +       if (ProtocolFlags & SKCS_PROTO_IP) {
10353 +               pPacketInfo->IpHeaderChecksum =
10354 +                       SkCsCalculateChecksum(pIpHeader, IpHeaderLength);
10355 +       }
10356 +
10357 +       /* Get the next level protocol identifier. */
10358 +
10359 +       NextLevelProtocol =
10360 +               *(SK_U8 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_NEXT_LEVEL_PROTOCOL);
10361 +
10362 +       /*
10363 +        * Check if this is a TCP or UDP frame and if we should calculate the
10364 +        * TCP/UDP pseudo header checksum.
10365 +        *
10366 +        * Also clear all protocol bit flags of protocols not present in the
10367 +        * frame.
10368 +        */
10369 +
10370 +       if ((ProtocolFlags & SKCS_PROTO_TCP) != 0 &&
10371 +               NextLevelProtocol == SKCS_PROTO_ID_TCP) {
10372 +               /* TCP/IP frame. */
10373 +               ProtocolFlags &= SKCS_PROTO_TCP | SKCS_PROTO_IP;
10374 +               NextLevelProtoStats =
10375 +                       &pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_TCP];
10376 +       }
10377 +       else if ((ProtocolFlags & SKCS_PROTO_UDP) != 0 &&
10378 +               NextLevelProtocol == SKCS_PROTO_ID_UDP) {
10379 +               /* UDP/IP frame. */
10380 +               ProtocolFlags &= SKCS_PROTO_UDP | SKCS_PROTO_IP;
10381 +               NextLevelProtoStats =
10382 +                       &pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_UDP];
10383 +       }
10384 +       else {
10385 +               /*
10386 +                * Either not a TCP or UDP frame and/or TCP/UDP processing not
10387 +                * specified.
10388 +                */
10389 +               pPacketInfo->ProtocolFlags = ProtocolFlags & SKCS_PROTO_IP;
10390 +               return;
10391 +       }
10392 +
10393 +       /* Check if this is an IP fragment. */
10394 +
10395 +       /*
10396 +        * Note: An IP fragment has a non-zero "Fragment Offset" field and/or
10397 +        * the "More Fragments" bit set. Thus, if both the "Fragment Offset"
10398 +        * and the "More Fragments" are zero, it is *not* a fragment. We can
10399 +        * easily check both at the same time since they are in the same 16-bit
10400 +        * word.
10401 +        */
10402 +
10403 +       if ((*(SK_U16 *)
10404 +               SKCS_IDX(pIpHeader, SKCS_OFS_IP_FLAGS_AND_FRAGMENT_OFFSET) &
10405 +               ~SKCS_IP_DONT_FRAGMENT) != 0) {
10406 +               /* IP fragment; ignore all other protocols. */
10407 +               pPacketInfo->ProtocolFlags = ProtocolFlags & SKCS_PROTO_IP;
10408 +               NextLevelProtoStats->TxUnableCts++;
10409 +               return;
10410 +       }
10411 +
10412 +       /*
10413 +        * Calculate the TCP/UDP pseudo header checksum.
10414 +        */
10415 +
10416 +       /* Get total length of IP header and data. */
10417 +
10418 +       IpDataLength =
10419 +               *(SK_U16 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_TOTAL_LENGTH);
10420 +
10421 +       /* Get length of IP data portion. */
10422 +
10423 +       IpDataLength = SKCS_NTOH16(IpDataLength) - IpHeaderLength;
10424 +
10425 +       /* Calculate the sum of all pseudo header fields (16-bit). */
10426 +
10427 +       PseudoHeaderChecksum =
10428 +               (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
10429 +                       SKCS_OFS_IP_SOURCE_ADDRESS + 0) +
10430 +               (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
10431 +                       SKCS_OFS_IP_SOURCE_ADDRESS + 2) +
10432 +               (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
10433 +                       SKCS_OFS_IP_DESTINATION_ADDRESS + 0) +
10434 +               (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
10435 +                       SKCS_OFS_IP_DESTINATION_ADDRESS + 2) +
10436 +               (unsigned long) SKCS_HTON16(NextLevelProtocol) +
10437 +               (unsigned long) SKCS_HTON16(IpDataLength);
10438 +
10439 +       /* Add-in any carries. */
10440 +
10441 +       SKCS_OC_ADD(PseudoHeaderChecksum, PseudoHeaderChecksum, 0);
10442 +
10443 +       /* Add-in any new carry. */
10444 +
10445 +       SKCS_OC_ADD(pPacketInfo->PseudoHeaderChecksum, PseudoHeaderChecksum, 0);
10446 +
10447 +       pPacketInfo->ProtocolFlags = ProtocolFlags;
10448 +       NextLevelProtoStats->TxOkCts++; /* Success. */
10449 +}      /* SkCsGetSendInfo */
10450 +
10451 +
10452 +/******************************************************************************
10453 + *
10454 + *     SkCsGetReceiveInfo - verify checksum information for a received packet
10455 + *
10456 + * Description:
10457 + *     Verify a received frame's checksum. The function returns a status code
10458 + *     reflecting the result of the verification.
10459 + *
10460 + * Note:
10461 + *     Before calling this function you have to verify that the frame is
10462 + *     not padded and Checksum1 and Checksum2 are bigger than 1.
10463 + *
10464 + * Arguments:
10465 + *     pAc - Pointer to adapter context struct.
10466 + *
10467 + *     pIpHeader - Pointer to IP header. Must be at least the length in bytes
10468 + *     of the received IP header including any option fields. For UDP packets,
10469 + *     8 additional bytes are needed to access the UDP checksum.
10470 + *
10471 + *     Note: The actual length of the IP header is stored in the lower four
10472 + *     bits of the first octet of the IP header as the number of 4-byte words,
10473 + *     so it must be multiplied by four to get the length in bytes. Thus, the
10474 + *     maximum IP header length is 15 * 4 = 60 bytes.
10475 + *
10476 + *     Checksum1 - The first 16-bit Internet Checksum calculated by the
10477 + *     hardware starting at the offset returned by SkCsSetReceiveFlags().
10478 + *
10479 + *     Checksum2 - The second 16-bit Internet Checksum calculated by the
10480 + *     hardware starting at the offset returned by SkCsSetReceiveFlags().
10481 + *
10482 + * Returns:
10483 + *     SKCS_STATUS_UNKNOWN_IP_VERSION - Not an IP v4 frame.
10484 + *     SKCS_STATUS_IP_CSUM_ERROR - IP checksum error.
10485 + *     SKCS_STATUS_IP_CSUM_ERROR_TCP - IP checksum error in TCP frame.
10486 + *     SKCS_STATUS_IP_CSUM_ERROR_UDP - IP checksum error in UDP frame
10487 + *     SKCS_STATUS_IP_FRAGMENT - IP fragment (IP checksum ok).
10488 + *     SKCS_STATUS_IP_CSUM_OK - IP checksum ok (not a TCP or UDP frame).
10489 + *     SKCS_STATUS_TCP_CSUM_ERROR - TCP checksum error (IP checksum ok).
10490 + *     SKCS_STATUS_UDP_CSUM_ERROR - UDP checksum error (IP checksum ok).
10491 + *     SKCS_STATUS_TCP_CSUM_OK - IP and TCP checksum ok.
10492 + *     SKCS_STATUS_UDP_CSUM_OK - IP and UDP checksum ok.
10493 + *     SKCS_STATUS_IP_CSUM_OK_NO_UDP - IP checksum OK and no UDP checksum.
10494 + *
10495 + *     Note: If SKCS_OVERWRITE_STATUS is defined, the SKCS_STATUS_XXX values
10496 + *     returned here can be defined in some header file by the module using CSUM.
10497 + *     In this way, the calling module can assign return values for its own needs,
10498 + *     e.g. by assigning bit flags to the individual protocols.
10499 + */
10500 +SKCS_STATUS SkCsGetReceiveInfo(
10501 +SK_AC          *pAc,           /* Adapter context struct. */
10502 +void           *pIpHeader,     /* IP header. */
10503 +unsigned       Checksum1,      /* Hardware checksum 1. */
10504 +unsigned       Checksum2,      /* Hardware checksum 2. */
10505 +int                    NetNumber)      /* Net number */
10506 +{
10507 +       /* Internet Header Version found in IP header. */
10508 +       unsigned InternetHeaderVersion;
10509 +
10510 +       /* Length of the IP header as found in IP header. */
10511 +       unsigned IpHeaderLength;
10512 +
10513 +       /* Length of IP data portion. */
10514 +       unsigned IpDataLength;
10515 +
10516 +       /* IP header checksum. */
10517 +       unsigned IpHeaderChecksum;
10518 +
10519 +       /* IP header options checksum, if any. */
10520 +       unsigned IpOptionsChecksum;
10521 +
10522 +       /* IP data checksum, i.e. TCP/UDP checksum. */
10523 +       unsigned IpDataChecksum;
10524 +
10525 +       /* Next level protocol identifier found in IP header. */
10526 +       unsigned NextLevelProtocol;
10527 +
10528 +       /* The checksum of the "next level protocol", i.e. TCP or UDP. */
10529 +       unsigned long NextLevelProtocolChecksum;
10530 +
10531 +       /* Pointer to next level protocol statistics structure. */
10532 +       SKCS_PROTO_STATS *NextLevelProtoStats;
10533 +
10534 +       /* Temporary variable. */
10535 +       unsigned Tmp;
10536 +
10537 +       Tmp = *(SK_U8 *)
10538 +               SKCS_IDX(pIpHeader, SKCS_OFS_IP_HEADER_VERSION_AND_LENGTH);
10539 +
10540 +       /* Get the Internet Header Version (IHV). */
10541 +       /* Note: The IHV is stored in the upper four bits. */
10542 +
10543 +       InternetHeaderVersion = Tmp >> 4;
10544 +
10545 +       /* Check the Internet Header Version. */
10546 +       /* Note: We currently only support IP version 4. */
10547 +
10548 +       if (InternetHeaderVersion != 4) {       /* IPv4? */
10549 +               SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_RX,
10550 +                       ("Rx: Unknown Internet Header Version %u.\n",
10551 +                       InternetHeaderVersion));
10552 +               pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxUnableCts++;
10553 +               return (SKCS_STATUS_UNKNOWN_IP_VERSION);
10554 +       }
10555 +
10556 +       /* Get the IP header length (IHL). */
10557 +       /*
10558 +        * Note: The IHL is stored in the lower four bits as the number of
10559 +        * 4-byte words.
10560 +        */
10561 +
10562 +       IpHeaderLength = (Tmp & 0xf) * 4;
10563 +
10564 +       /* Check the IP header length. */
10565 +
10566 +       /* 04-Aug-1998 sw - Really check the IHL? Necessary? */
10567 +
10568 +       if (IpHeaderLength < 5*4) {
10569 +               SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_RX,
10570 +                       ("Rx: Invalid IP Header Length %u.\n", IpHeaderLength));
10571 +               pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxErrCts++;
10572 +               return (SKCS_STATUS_IP_CSUM_ERROR);
10573 +       }
10574 +
10575 +       /* This is an IPv4 frame with a header of valid length. */
10576 +
10577 +       /* Get the IP header and data checksum. */
10578 +
10579 +       IpDataChecksum = Checksum2;
10580 +
10581 +       /*
10582 +        * The IP header checksum is calculated as follows:
10583 +        *
10584 +        *      IpHeaderChecksum = Checksum1 - Checksum2
10585 +        */
10586 +
10587 +       SKCS_OC_SUB(IpHeaderChecksum, Checksum1, Checksum2);
10588 +
10589 +       /* Check if any IP header options. */
10590 +
10591 +       if (IpHeaderLength > SKCS_IP_HEADER_SIZE) {
10592 +
10593 +               /* Get the IP options checksum. */
10594 +
10595 +               IpOptionsChecksum = SkCsCalculateChecksum(
10596 +                       SKCS_IDX(pIpHeader, SKCS_IP_HEADER_SIZE),
10597 +                       IpHeaderLength - SKCS_IP_HEADER_SIZE);
10598 +
10599 +               /* Adjust the IP header and IP data checksums. */
10600 +
10601 +               SKCS_OC_ADD(IpHeaderChecksum, IpHeaderChecksum, IpOptionsChecksum);
10602 +
10603 +               SKCS_OC_SUB(IpDataChecksum, IpDataChecksum, IpOptionsChecksum);
10604 +       }
10605 +
10606 +       /*
10607 +        * Check if the IP header checksum is ok.
10608 +        *
10609 +        * NOTE: We must check the IP header checksum even if the caller just wants
10610 +        * us to check upper-layer checksums, because we cannot do any further
10611 +        * processing of the packet without a valid IP checksum.
10612 +        */
10613 +
10614 +       /* Get the next level protocol identifier. */
10615 +
10616 +       NextLevelProtocol = *(SK_U8 *)
10617 +               SKCS_IDX(pIpHeader, SKCS_OFS_IP_NEXT_LEVEL_PROTOCOL);
10618 +
10619 +       if (IpHeaderChecksum != 0xffff) {
10620 +               pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxErrCts++;
10621 +               /* the NDIS tester wants to know the upper level protocol too */
10622 +               if (NextLevelProtocol == SKCS_PROTO_ID_TCP) {
10623 +                       return(SKCS_STATUS_IP_CSUM_ERROR_TCP);
10624 +               }
10625 +               else if (NextLevelProtocol == SKCS_PROTO_ID_UDP) {
10626 +                       return(SKCS_STATUS_IP_CSUM_ERROR_UDP);
10627 +               }
10628 +               return (SKCS_STATUS_IP_CSUM_ERROR);
10629 +       }
10630 +
10631 +       /*
10632 +        * Check if this is a TCP or UDP frame and if we should calculate the
10633 +        * TCP/UDP pseudo header checksum.
10634 +        *
10635 +        * Also clear all protocol bit flags of protocols not present in the
10636 +        * frame.
10637 +        */
10638 +
10639 +       if ((pAc->Csum.ReceiveFlags[NetNumber] & SKCS_PROTO_TCP) != 0 &&
10640 +               NextLevelProtocol == SKCS_PROTO_ID_TCP) {
10641 +               /* TCP/IP frame. */
10642 +               NextLevelProtoStats =
10643 +                       &pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_TCP];
10644 +       }
10645 +       else if ((pAc->Csum.ReceiveFlags[NetNumber] & SKCS_PROTO_UDP) != 0 &&
10646 +               NextLevelProtocol == SKCS_PROTO_ID_UDP) {
10647 +               /* UDP/IP frame. */
10648 +               NextLevelProtoStats =
10649 +                       &pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_UDP];
10650 +       }
10651 +       else {
10652 +               /*
10653 +                * Either not a TCP or UDP frame and/or TCP/UDP processing not
10654 +                * specified.
10655 +                */
10656 +               return (SKCS_STATUS_IP_CSUM_OK);
10657 +       }
10658 +
10659 +       /* Check if this is an IP fragment. */
10660 +
10661 +       /*
10662 +        * Note: An IP fragment has a non-zero "Fragment Offset" field and/or
10663 +        * the "More Fragments" bit set. Thus, if both the "Fragment Offset"
10664 +        * and the "More Fragments" are zero, it is *not* a fragment. We can
10665 +        * easily check both at the same time since they are in the same 16-bit
10666 +        * word.
10667 +        */
10668 +
10669 +       if ((*(SK_U16 *)
10670 +               SKCS_IDX(pIpHeader, SKCS_OFS_IP_FLAGS_AND_FRAGMENT_OFFSET) &
10671 +               ~SKCS_IP_DONT_FRAGMENT) != 0) {
10672 +               /* IP fragment; ignore all other protocols. */
10673 +               NextLevelProtoStats->RxUnableCts++;
10674 +               return (SKCS_STATUS_IP_FRAGMENT);
10675 +       }
10676 +
10677 +       /*
10678 +        * 08-May-2000 ra
10679 +        *
10680 +        * From RFC 768 (UDP)
10681 +        * If the computed checksum is zero, it is transmitted as all ones (the
10682 +        * equivalent in one's complement arithmetic).  An all zero transmitted
10683 +        * checksum value means that the transmitter generated no checksum (for
10684 +        * debugging or for higher level protocols that don't care).
10685 +        */
10686 +
10687 +       if (NextLevelProtocol == SKCS_PROTO_ID_UDP &&
10688 +               *(SK_U16*)SKCS_IDX(pIpHeader, IpHeaderLength + 6) == 0x0000) {
10689 +
10690 +               NextLevelProtoStats->RxOkCts++;
10691 +
10692 +               return (SKCS_STATUS_IP_CSUM_OK_NO_UDP);
10693 +       }
10694 +
10695 +       /*
10696 +        * Calculate the TCP/UDP checksum.
10697 +        */
10698 +
10699 +       /* Get total length of IP header and data. */
10700 +
10701 +       IpDataLength =
10702 +               *(SK_U16 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_TOTAL_LENGTH);
10703 +
10704 +       /* Get length of IP data portion. */
10705 +
10706 +       IpDataLength = SKCS_NTOH16(IpDataLength) - IpHeaderLength;
10707 +
10708 +       NextLevelProtocolChecksum =
10709 +
10710 +               /* Calculate the pseudo header checksum. */
10711 +
10712 +               (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
10713 +                       SKCS_OFS_IP_SOURCE_ADDRESS + 0) +
10714 +               (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
10715 +                       SKCS_OFS_IP_SOURCE_ADDRESS + 2) +
10716 +               (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
10717 +                       SKCS_OFS_IP_DESTINATION_ADDRESS + 0) +
10718 +               (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
10719 +                       SKCS_OFS_IP_DESTINATION_ADDRESS + 2) +
10720 +               (unsigned long) SKCS_HTON16(NextLevelProtocol) +
10721 +               (unsigned long) SKCS_HTON16(IpDataLength) +
10722 +
10723 +               /* Add the TCP/UDP header checksum. */
10724 +
10725 +               (unsigned long) IpDataChecksum;
10726 +
10727 +       /* Add-in any carries. */
10728 +
10729 +       SKCS_OC_ADD(NextLevelProtocolChecksum, NextLevelProtocolChecksum, 0);
10730 +
10731 +       /* Add-in any new carry. */
10732 +
10733 +       SKCS_OC_ADD(NextLevelProtocolChecksum, NextLevelProtocolChecksum, 0);
10734 +
10735 +       /* Check if the TCP/UDP checksum is ok. */
10736 +
10737 +       if ((unsigned) NextLevelProtocolChecksum == 0xffff) {
10738 +
10739 +               /* TCP/UDP checksum ok. */
10740 +
10741 +               NextLevelProtoStats->RxOkCts++;
10742 +
10743 +               return (NextLevelProtocol == SKCS_PROTO_ID_TCP ?
10744 +                       SKCS_STATUS_TCP_CSUM_OK : SKCS_STATUS_UDP_CSUM_OK);
10745 +       }
10746 +
10747 +       /* TCP/UDP checksum error. */
10748 +
10749 +       NextLevelProtoStats->RxErrCts++;
10750 +
10751 +       return (NextLevelProtocol == SKCS_PROTO_ID_TCP ?
10752 +               SKCS_STATUS_TCP_CSUM_ERROR : SKCS_STATUS_UDP_CSUM_ERROR);
10753 +}      /* SkCsGetReceiveInfo */
10754 +
10755 +
10756 +/******************************************************************************
10757 + *
10758 + *     SkCsSetReceiveFlags - set checksum receive flags
10759 + *
10760 + * Description:
10761 + *     Use this function to set the various receive flags. According to the
10762 + *     protocol flags set by the caller, the start offsets within received
10763 + *     packets of the two hardware checksums are returned. These offsets must
10764 + *     be stored in all receive descriptors.
10765 + *
10766 + * Arguments:
10767 + *     pAc - Pointer to adapter context struct.
10768 + *
10769 + *     ReceiveFlags - Any combination of SK_PROTO_XXX flags of the protocols
10770 + *     for which the caller wants checksum information on received frames.
10771 + *
10772 + *     pChecksum1Offset - The start offset of the first receive descriptor
10773 + *     hardware checksum to be calculated for received frames is returned
10774 + *     here.
10775 + *
10776 + *     pChecksum2Offset - The start offset of the second receive descriptor
10777 + *     hardware checksum to be calculated for received frames is returned
10778 + *     here.
10779 + *
10780 + * Returns: N/A
10781 + *     Returns the two hardware checksum start offsets.
10782 + */
10783 +void SkCsSetReceiveFlags(
10784 +SK_AC          *pAc,                           /* Adapter context struct. */
10785 +unsigned       ReceiveFlags,           /* New receive flags. */
10786 +unsigned       *pChecksum1Offset,      /* Offset for hardware checksum 1. */
10787 +unsigned       *pChecksum2Offset,      /* Offset for hardware checksum 2. */
10788 +int                    NetNumber)
10789 +{
10790 +       /* Save the receive flags. */
10791 +
10792 +       pAc->Csum.ReceiveFlags[NetNumber] = ReceiveFlags;
10793 +
10794 +       /* First checksum start offset is the IP header. */
10795 +       *pChecksum1Offset = SKCS_MAC_HEADER_SIZE;
10796 +
10797 +       /*
10798 +        * Second checksum start offset is the IP data. Note that this may vary
10799 +        * if there are any IP header options in the actual packet.
10800 +        */
10801 +       *pChecksum2Offset = SKCS_MAC_HEADER_SIZE + SKCS_IP_HEADER_SIZE;
10802 +}      /* SkCsSetReceiveFlags */
10803 +
10804 +#ifndef SK_CS_CALCULATE_CHECKSUM
10805 +
10806 +/******************************************************************************
10807 + *
10808 + *     SkCsCalculateChecksum - calculate checksum for specified data
10809 + *
10810 + * Description:
10811 + *     Calculate and return the 16-bit Internet Checksum for the specified
10812 + *     data.
10813 + *
10814 + * Arguments:
10815 + *     pData - Pointer to data for which the checksum shall be calculated.
10816 + *     Note: The pointer should be aligned on a 16-bit boundary.
10817 + *
10818 + *     Length - Length in bytes of data to checksum.
10819 + *
10820 + * Returns:
10821 + *     The 16-bit Internet Checksum for the specified data.
10822 + *
10823 + *     Note: The checksum is calculated in the machine's natural byte order,
10824 + *     i.e. little vs. big endian. Thus, the resulting checksum is different
10825 + *     for the same input data on little and big endian machines.
10826 + *
10827 + *     However, when written back to the network packet, the byte order is
10828 + *     always in correct network order.
10829 + */
10830 +unsigned SkCsCalculateChecksum(
10831 +void           *pData,         /* Data to checksum. */
10832 +unsigned       Length)         /* Length of data. */
10833 +{
10834 +       SK_U16 *pU16;           /* Pointer to the data as 16-bit words. */
10835 +       unsigned long Checksum; /* Checksum; must be at least 32 bits. */
10836 +
10837 +       /* Sum up all 16-bit words. */
10838 +
10839 +       pU16 = (SK_U16 *) pData;
10840 +       for (Checksum = 0; Length > 1; Length -= 2) {
10841 +               Checksum += *pU16++;
10842 +       }
10843 +
10844 +       /* If this is an odd number of bytes, add-in the last byte. */
10845 +
10846 +       if (Length > 0) {
10847 +#ifdef SK_BIG_ENDIAN
10848 +               /* Add the last byte as the high byte. */
10849 +               Checksum += ((unsigned) *(SK_U8 *) pU16) << 8;
10850 +#else  /* !SK_BIG_ENDIAN */
10851 +               /* Add the last byte as the low byte. */
10852 +               Checksum += *(SK_U8 *) pU16;
10853 +#endif /* !SK_BIG_ENDIAN */
10854 +       }
10855 +
10856 +       /* Add-in any carries. */
10857 +
10858 +       SKCS_OC_ADD(Checksum, Checksum, 0);
10859 +
10860 +       /* Add-in any new carry. */
10861 +
10862 +       SKCS_OC_ADD(Checksum, Checksum, 0);
10863 +
10864 +       /* Note: All bits beyond the 16-bit limit are now zero. */
10865 +
10866 +       return ((unsigned) Checksum);
10867 +}      /* SkCsCalculateChecksum */
10868 +
10869 +#endif /* SK_CS_CALCULATE_CHECKSUM */
10870 +
10871 +/******************************************************************************
10872 + *
10873 + *     SkCsEvent - the CSUM event dispatcher
10874 + *
10875 + * Description:
10876 + *     This is the event handler for the CSUM module.
10877 + *
10878 + * Arguments:
10879 + *     pAc - Pointer to adapter context.
10880 + *
10881 + *     Ioc - I/O context.
10882 + *
10883 + *     Event -  Event id.
10884 + *
10885 + *     Param - Event dependent parameter.
10886 + *
10887 + * Returns:
10888 + *     The 16-bit Internet Checksum for the specified data.
10889 + *
10890 + *     Note: The checksum is calculated in the machine's natural byte order,
10891 + *     i.e. little vs. big endian. Thus, the resulting checksum is different
10892 + *     for the same input data on little and big endian machines.
10893 + *
10894 + *     However, when written back to the network packet, the byte order is
10895 + *     always in correct network order.
10896 + */
10897 +int SkCsEvent(
10898 +SK_AC          *pAc,   /* Pointer to adapter context. */
10899 +SK_IOC         Ioc,    /* I/O context. */
10900 +SK_U32         Event,  /* Event id. */
10901 +SK_EVPARA      Param)  /* Event dependent parameter. */
10902 +{
10903 +       int ProtoIndex;
10904 +       int     NetNumber;
10905 +
10906 +       switch (Event) {
10907 +       /*
10908 +        * Clear protocol statistics.
10909 +        *
10910 +        * Param - Protocol index, or -1 for all protocols.
10911 +        *               - Net number.
10912 +        */
10913 +       case SK_CSUM_EVENT_CLEAR_PROTO_STATS:
10914 +
10915 +               ProtoIndex = (int)Param.Para32[1];
10916 +               NetNumber = (int)Param.Para32[0];
10917 +               if (ProtoIndex < 0) {   /* Clear for all protocols. */
10918 +                       if (NetNumber >= 0) {
10919 +                               SK_MEMSET(&pAc->Csum.ProtoStats[NetNumber][0], 0,
10920 +                                       sizeof(pAc->Csum.ProtoStats[NetNumber]));
10921 +                       }
10922 +               }
10923 +               else {                                  /* Clear for individual protocol. */
10924 +                       SK_MEMSET(&pAc->Csum.ProtoStats[NetNumber][ProtoIndex], 0,
10925 +                               sizeof(pAc->Csum.ProtoStats[NetNumber][ProtoIndex]));
10926 +               }
10927 +               break;
10928 +       default:
10929 +               break;
10930 +       }
10931 +       return (0);     /* Success. */
10932 +}      /* SkCsEvent */
10933 +
10934 +#endif /* SK_USE_CSUM */
10935 diff -ruN linux/drivers/net/sk98lin/skdim.c linux-new/drivers/net/sk98lin/skdim.c
10936 --- linux/drivers/net/sk98lin/skdim.c   2006-09-20 05:42:06.000000000 +0200
10937 +++ linux-new/drivers/net/sk98lin/skdim.c       2006-07-28 14:13:56.000000000 +0200
10938 @@ -1,17 +1,25 @@
10939  /******************************************************************************
10940   *
10941 - * Name:       skdim.c
10942 - * Project:    GEnesis, PCI Gigabit Ethernet Adapter
10943 - * Version:    $Revision$
10944 - * Date:       $Date$
10945 - * Purpose:    All functions to maintain interrupt moderation
10946 + * Name:        skdim.c
10947 + * Project:     GEnesis, PCI Gigabit Ethernet Adapter
10948 + * Version:     $Revision$
10949 + * Date:        $Date$
10950 + * Purpose:     All functions regardig interrupt moderation
10951   *
10952   ******************************************************************************/
10953
10954  /******************************************************************************
10955   *
10956   *     (C)Copyright 1998-2002 SysKonnect GmbH.
10957 - *     (C)Copyright 2002-2003 Marvell.
10958 + *     (C)Copyright 2002-2005 Marvell.
10959 + *
10960 + *     Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet
10961 + *      Server Adapters.
10962 + *
10963 + *     Author: Ralph Roesler (rroesler@syskonnect.de)
10964 + *             Mirko Lindner (mlindner@syskonnect.de)
10965 + *
10966 + *     Address all question to: linux@syskonnect.de
10967   *
10968   *     This program is free software; you can redistribute it and/or modify
10969   *     it under the terms of the GNU General Public License as published by
10970 @@ -20,723 +28,367 @@
10971   *
10972   *     The information in this file is provided "AS IS" without warranty.
10973   *
10974 - ******************************************************************************/
10975 + *****************************************************************************/
10976
10977 -/******************************************************************************
10978 - *
10979 - * Description:
10980 - *
10981 - * This module is intended to manage the dynamic interrupt moderation on both
10982 - * GEnesis and Yukon adapters.
10983 - *
10984 - * Include File Hierarchy:
10985 - *
10986 - *     "skdrv1st.h"
10987 - *     "skdrv2nd.h"
10988 - *
10989 - ******************************************************************************/
10990 -
10991 -#ifndef        lint
10992 -static const char SysKonnectFileId[] =
10993 -       "@(#) $Id$ (C) SysKonnect.";
10994 -#endif
10995 -
10996 -#define __SKADDR_C
10997 -
10998 -#ifdef __cplusplus
10999 -#error C++ is not yet supported.
11000 -extern "C" {
11001 -#endif
11002 -
11003 -/*******************************************************************************
11004 -**
11005 -** Includes
11006 -**
11007 -*******************************************************************************/
11008 -
11009 -#ifndef __INC_SKDRV1ST_H
11010  #include "h/skdrv1st.h"
11011 -#endif
11012 -
11013 -#ifndef __INC_SKDRV2ND_H
11014  #include "h/skdrv2nd.h"
11015 -#endif
11016
11017 -#include       <linux/kernel_stat.h>
11018 -
11019 -/*******************************************************************************
11020 -**
11021 -** Defines
11022 -**
11023 -*******************************************************************************/
11024 -
11025 -/*******************************************************************************
11026 -**
11027 -** Typedefs
11028 -**
11029 -*******************************************************************************/
11030 +/******************************************************************************
11031 + *
11032 + * Local Function Prototypes
11033 + *
11034 + *****************************************************************************/
11035
11036 -/*******************************************************************************
11037 -**
11038 -** Local function prototypes
11039 -**
11040 -*******************************************************************************/
11041 -
11042 -static unsigned int GetCurrentSystemLoad(SK_AC *pAC);
11043 -static SK_U64       GetIsrCalls(SK_AC *pAC);
11044 -static SK_BOOL      IsIntModEnabled(SK_AC *pAC);
11045 -static void         SetCurrIntCtr(SK_AC *pAC);
11046 -static void         EnableIntMod(SK_AC *pAC);
11047 -static void         DisableIntMod(SK_AC *pAC);
11048 -static void         ResizeDimTimerDuration(SK_AC *pAC);
11049 -static void         DisplaySelectedModerationType(SK_AC *pAC);
11050 -static void         DisplaySelectedModerationMask(SK_AC *pAC);
11051 -static void         DisplayDescrRatio(SK_AC *pAC);
11052 +static SK_U64 getIsrCalls(SK_AC *pAC);
11053 +static SK_BOOL isIntModEnabled(SK_AC *pAC);
11054 +static void setCurrIntCtr(SK_AC *pAC);
11055 +static void enableIntMod(SK_AC *pAC);
11056 +static void disableIntMod(SK_AC *pAC);
11057
11058 -/*******************************************************************************
11059 -**
11060 -** Global variables
11061 -**
11062 -*******************************************************************************/
11063 +#define M_DIMINFO pAC->DynIrqModInfo
11064
11065 -/*******************************************************************************
11066 -**
11067 -** Local variables
11068 -**
11069 -*******************************************************************************/
11070 +/******************************************************************************
11071 + *
11072 + * Global Functions
11073 + *
11074 + *****************************************************************************/
11075
11076 -/*******************************************************************************
11077 -**
11078 -** Global functions
11079 -**
11080 -*******************************************************************************/
11081 +/*****************************************************************************
11082 + *
11083 + *     SkDimModerate - Moderates the IRQs depending on the current needs
11084 + *
11085 + * Description:
11086 + *     Moderation of IRQs depends on the number of occurred IRQs with
11087 + *     respect to the previous moderation cycle.
11088 + *
11089 + * Returns:    N/A
11090 + *
11091 + */
11092 +void SkDimModerate(
11093 +SK_AC *pAC)  /* pointer to adapter control context */
11094 +{
11095 +       SK_U64  IsrCalls = getIsrCalls(pAC);
11096 +
11097 +       SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==> SkDimModerate\n"));
11098 +
11099 +       if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
11100 +               if (isIntModEnabled(pAC)) {
11101 +                       if (IsrCalls < M_DIMINFO.MaxModIntsPerSecLowerLimit) {
11102 +                               disableIntMod(pAC);
11103 +                       }
11104 +               } else {
11105 +                       if (IsrCalls > M_DIMINFO.MaxModIntsPerSecUpperLimit) {
11106 +                               enableIntMod(pAC);
11107 +                       }
11108 +               }
11109 +       }
11110 +       setCurrIntCtr(pAC);
11111
11112 -/*******************************************************************************
11113 -** Function     : SkDimModerate
11114 -** Description  : Called in every ISR to check if moderation is to be applied
11115 -**                or not for the current number of interrupts
11116 -** Programmer   : Ralph Roesler
11117 -** Last Modified: 22-mar-03
11118 -** Returns      : void (!)
11119 -** Notes        : -
11120 -*******************************************************************************/
11121 -
11122 -void
11123 -SkDimModerate(SK_AC *pAC) {
11124 -    unsigned int CurrSysLoad    = 0;  /* expressed in percent */
11125 -    unsigned int LoadIncrease   = 0;  /* expressed in percent */
11126 -    SK_U64       ThresholdInts  = 0;
11127 -    SK_U64       IsrCallsPerSec = 0;
11128 +       SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("<== SkDimModerate\n"));
11129 +}
11130
11131 -#define M_DIMINFO pAC->DynIrqModInfo
11132 +/*****************************************************************************
11133 + *
11134 + *     SkDimStartModerationTimer - Starts the moderation timer
11135 + *
11136 + * Description:
11137 + *     Dynamic interrupt moderation is regularly checked using the
11138 + *     so-called moderation timer. This timer is started with this function.
11139 + *
11140 + * Returns:    N/A
11141 + */
11142 +void SkDimStartModerationTimer(
11143 +SK_AC *pAC) /* pointer to adapter control context */
11144 +{
11145 +       SK_EVPARA   EventParam;   /* Event struct for timer event */
11146 +
11147 +       SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11148 +                       ("==> SkDimStartModerationTimer\n"));
11149
11150 -    if (!IsIntModEnabled(pAC)) {
11151 -        if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
11152 -            CurrSysLoad = GetCurrentSystemLoad(pAC);
11153 -            if (CurrSysLoad > 75) {
11154 -                    /*
11155 -                    ** More than 75% total system load! Enable the moderation
11156 -                    ** to shield the system against too many interrupts.
11157 -                    */
11158 -                    EnableIntMod(pAC);
11159 -            } else if (CurrSysLoad > M_DIMINFO.PrevSysLoad) {
11160 -                LoadIncrease = (CurrSysLoad - M_DIMINFO.PrevSysLoad);
11161 -                if (LoadIncrease > ((M_DIMINFO.PrevSysLoad *
11162 -                                         C_INT_MOD_ENABLE_PERCENTAGE) / 100)) {
11163 -                    if (CurrSysLoad > 10) {
11164 -                        /*
11165 -                        ** More than 50% increase with respect to the
11166 -                        ** previous load of the system. Most likely this
11167 -                        ** is due to our ISR-proc...
11168 -                        */
11169 -                        EnableIntMod(pAC);
11170 -                    }
11171 -                }
11172 -            } else {
11173 -                /*
11174 -                ** Neither too much system load at all nor too much increase
11175 -                ** with respect to the previous system load. Hence, we can leave
11176 -                ** the ISR-handling like it is without enabling moderation.
11177 -                */
11178 -            }
11179 -            M_DIMINFO.PrevSysLoad = CurrSysLoad;
11180 -        }
11181 -    } else {
11182 -        if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
11183 -            ThresholdInts  = ((M_DIMINFO.MaxModIntsPerSec *
11184 -                                   C_INT_MOD_DISABLE_PERCENTAGE) / 100);
11185 -            IsrCallsPerSec = GetIsrCalls(pAC);
11186 -            if (IsrCallsPerSec <= ThresholdInts) {
11187 -                /*
11188 -                ** The number of interrupts within the last second is
11189 -                ** lower than the disable_percentage of the desried
11190 -                ** maxrate. Therefore we can disable the moderation.
11191 -                */
11192 -                DisableIntMod(pAC);
11193 -                M_DIMINFO.MaxModIntsPerSec =
11194 -                   (M_DIMINFO.MaxModIntsPerSecUpperLimit +
11195 -                    M_DIMINFO.MaxModIntsPerSecLowerLimit) / 2;
11196 -            } else {
11197 -                /*
11198 -                ** The number of interrupts per sec is the same as expected.
11199 -                ** Evalulate the descriptor-ratio. If it has changed, a resize
11200 -                ** in the moderation timer might be useful
11201 -                */
11202 -                if (M_DIMINFO.AutoSizing) {
11203 -                    ResizeDimTimerDuration(pAC);
11204 -                }
11205 -            }
11206 -        }
11207 -    }
11208 -
11209 -    /*
11210 -    ** Some information to the log...
11211 -    */
11212 -    if (M_DIMINFO.DisplayStats) {
11213 -        DisplaySelectedModerationType(pAC);
11214 -        DisplaySelectedModerationMask(pAC);
11215 -        DisplayDescrRatio(pAC);
11216 -    }
11217 +       if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
11218 +               SK_MEMSET((char *) &EventParam, 0, sizeof(EventParam));
11219 +               EventParam.Para32[0] = SK_DRV_MODERATION_TIMER;
11220 +               SkTimerStart(pAC, pAC->IoBase,
11221 +                       &pAC->DynIrqModInfo.ModTimer,
11222 +                       pAC->DynIrqModInfo.DynIrqModSampleInterval * 1000000,
11223 +                       SKGE_DRV, SK_DRV_TIMER, EventParam);
11224 +       }
11225
11226 -    M_DIMINFO.NbrProcessedDescr = 0;
11227 -    SetCurrIntCtr(pAC);
11228 +       SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11229 +                       ("<== SkDimStartModerationTimer\n"));
11230  }
11231
11232 -/*******************************************************************************
11233 -** Function     : SkDimStartModerationTimer
11234 -** Description  : Starts the audit-timer for the dynamic interrupt moderation
11235 -** Programmer   : Ralph Roesler
11236 -** Last Modified: 22-mar-03
11237 -** Returns      : void (!)
11238 -** Notes        : -
11239 -*******************************************************************************/
11240 -
11241 -void
11242 -SkDimStartModerationTimer(SK_AC *pAC) {
11243 -    SK_EVPARA    EventParam;   /* Event struct for timer event */
11244 -
11245 -    SK_MEMSET((char *) &EventParam, 0, sizeof(EventParam));
11246 -    EventParam.Para32[0] = SK_DRV_MODERATION_TIMER;
11247 -    SkTimerStart(pAC, pAC->IoBase, &pAC->DynIrqModInfo.ModTimer,
11248 -                 SK_DRV_MODERATION_TIMER_LENGTH,
11249 -                 SKGE_DRV, SK_DRV_TIMER, EventParam);
11250 -}
11251 +/*****************************************************************************
11252 + *
11253 + *     SkDimEnableModerationIfNeeded - Enables or disables any moderationtype
11254 + *
11255 + * Description:
11256 + *     This function effectively initializes the IRQ moderation of a network
11257 + *     adapter. Depending on the configuration, this might be either static
11258 + *     or dynamic. If no moderation is configured, this function will do
11259 + *     nothing.
11260 + *
11261 + * Returns:    N/A
11262 + */
11263 +void SkDimEnableModerationIfNeeded(
11264 +SK_AC *pAC)  /* pointer to adapter control context */
11265 +{
11266 +       SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11267 +                       ("==> SkDimEnableModerationIfNeeded\n"));
11268 +
11269 +       if (M_DIMINFO.IntModTypeSelect != C_INT_MOD_NONE) {
11270 +               if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_STATIC) {
11271 +                       enableIntMod(pAC);
11272 +               } else { /* must be C_INT_MOD_DYNAMIC */
11273 +                       SkDimStartModerationTimer(pAC);
11274 +               }
11275 +       }
11276
11277 -/*******************************************************************************
11278 -** Function     : SkDimEnableModerationIfNeeded
11279 -** Description  : Either enables or disables moderation
11280 -** Programmer   : Ralph Roesler
11281 -** Last Modified: 22-mar-03
11282 -** Returns      : void (!)
11283 -** Notes        : This function is called when a particular adapter is opened
11284 -**                There is no Disable function, because when all interrupts
11285 -**                might be disable, the moderation timer has no meaning at all
11286 -******************************************************************************/
11287 -
11288 -void
11289 -SkDimEnableModerationIfNeeded(SK_AC *pAC) {
11290 -
11291 -    if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_STATIC) {
11292 -        EnableIntMod(pAC);   /* notification print in this function */
11293 -    } else if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
11294 -        SkDimStartModerationTimer(pAC);
11295 -        if (M_DIMINFO.DisplayStats) {
11296 -            printk("Dynamic moderation has been enabled\n");
11297 -        }
11298 -    } else {
11299 -        if (M_DIMINFO.DisplayStats) {
11300 -            printk("No moderation has been enabled\n");
11301 -        }
11302 -    }
11303 +       SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11304 +                       ("<== SkDimEnableModerationIfNeeded\n"));
11305  }
11306
11307 -/*******************************************************************************
11308 -** Function     : SkDimDisplayModerationSettings
11309 -** Description  : Displays the current settings regaring interrupt moderation
11310 -** Programmer   : Ralph Roesler
11311 -** Last Modified: 22-mar-03
11312 -** Returns      : void (!)
11313 -** Notes        : -
11314 -*******************************************************************************/
11315 -
11316 -void
11317 -SkDimDisplayModerationSettings(SK_AC *pAC) {
11318 -    DisplaySelectedModerationType(pAC);
11319 -    DisplaySelectedModerationMask(pAC);
11320 -}
11321 +/*****************************************************************************
11322 + *
11323 + *     SkDimDisableModeration - disables moderation if it is enabled
11324 + *
11325 + * Description:
11326 + *     Disabling of the moderation requires that is enabled already.
11327 + *
11328 + * Returns:    N/A
11329 + */
11330 +void SkDimDisableModeration(
11331 +SK_AC  *pAC,                /* pointer to adapter control context */
11332 +int     CurrentModeration)  /* type of current moderation         */
11333 +{
11334 +       SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11335 +                       ("==> SkDimDisableModeration\n"));
11336 +
11337 +       if (M_DIMINFO.IntModTypeSelect != C_INT_MOD_NONE) {
11338 +               if (CurrentModeration == C_INT_MOD_STATIC) {
11339 +                       disableIntMod(pAC);
11340 +               } else { /* must be C_INT_MOD_DYNAMIC */
11341 +                       SkTimerStop(pAC, pAC->IoBase, &M_DIMINFO.ModTimer);
11342 +                       disableIntMod(pAC);
11343 +               }
11344 +       }
11345
11346 -/*******************************************************************************
11347 -**
11348 -** Local functions
11349 -**
11350 -*******************************************************************************/
11351 +       SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11352 +                       ("<== SkDimDisableModeration\n"));
11353 +}
11354
11355 -/*******************************************************************************
11356 -** Function     : GetCurrentSystemLoad
11357 -** Description  : Retrieves the current system load of the system. This load
11358 -**                is evaluated for all processors within the system.
11359 -** Programmer   : Ralph Roesler
11360 -** Last Modified: 22-mar-03
11361 -** Returns      : unsigned int: load expressed in percentage
11362 -** Notes        : The possible range being returned is from 0 up to 100.
11363 -**                Whereas 0 means 'no load at all' and 100 'system fully loaded'
11364 -**                It is impossible to determine what actually causes the system
11365 -**                to be in 100%, but maybe that is due to too much interrupts.
11366 -*******************************************************************************/
11367 -
11368 -static unsigned int
11369 -GetCurrentSystemLoad(SK_AC *pAC) {
11370 -       unsigned long jif         = jiffies;
11371 -       unsigned int  UserTime    = 0;
11372 -       unsigned int  SystemTime  = 0;
11373 -       unsigned int  NiceTime    = 0;
11374 -       unsigned int  IdleTime    = 0;
11375 -       unsigned int  TotalTime   = 0;
11376 -       unsigned int  UsedTime    = 0;
11377 -       unsigned int  SystemLoad  = 0;
11378 +/******************************************************************************
11379 + *
11380 + * Local Functions
11381 + *
11382 + *****************************************************************************/
11383
11384 -       /* unsigned int  NbrCpu      = 0; */
11385 +/*****************************************************************************
11386 + *
11387 + *     getIsrCalls - evaluate the number of IRQs handled in mod interval
11388 + *
11389 + * Description:
11390 + *     Depending on the selected moderation mask, this function will return
11391 + *     the number of interrupts handled in the previous moderation interval.
11392 + *     This evaluated number is based on the current number of interrupts
11393 + *     stored in PNMI-context and the previous stored interrupts.
11394 + *
11395 + * Returns:
11396 + *     the number of IRQs handled
11397 + */
11398 +static SK_U64 getIsrCalls(
11399 +SK_AC *pAC)  /* pointer to adapter control context */
11400 +{
11401 +       SK_U64   RxPort0IntDiff = 0, RxPort1IntDiff = 0;
11402 +       SK_U64   TxPort0IntDiff = 0, TxPort1IntDiff = 0;
11403 +       SK_U64   StatusPort0IntDiff = 0, StatusPort1IntDiff = 0;
11404 +
11405 +        SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==>getIsrCalls\n"));
11406 +
11407 +       if (!CHIP_ID_YUKON_2(pAC)) {
11408 +               if ((M_DIMINFO.MaskIrqModeration == IRQ_MASK_TX_ONLY) ||
11409 +                   (M_DIMINFO.MaskIrqModeration == IRQ_MASK_SP_TX)) {
11410 +                       if (pAC->GIni.GIMacsFound == 2) {
11411 +                               TxPort1IntDiff =
11412 +                                       pAC->Pnmi.Port[1].TxIntrCts -
11413 +                                       M_DIMINFO.PrevPort1TxIntrCts;
11414 +                       }
11415 +                       TxPort0IntDiff = pAC->Pnmi.Port[0].TxIntrCts -
11416 +                                       M_DIMINFO.PrevPort0TxIntrCts;
11417 +               } else if ((M_DIMINFO.MaskIrqModeration == IRQ_MASK_RX_ONLY) ||
11418 +                          (M_DIMINFO.MaskIrqModeration == IRQ_MASK_SP_RX)) {
11419 +                       if (pAC->GIni.GIMacsFound == 2) {
11420 +                               RxPort1IntDiff =
11421 +                                       pAC->Pnmi.Port[1].RxIntrCts -
11422 +                                       M_DIMINFO.PrevPort1RxIntrCts;
11423 +                       }
11424 +                       RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts -
11425 +                                       M_DIMINFO.PrevPort0RxIntrCts;
11426 +               } else {
11427 +                       if (pAC->GIni.GIMacsFound == 2) {
11428 +                               RxPort1IntDiff =
11429 +                                       pAC->Pnmi.Port[1].RxIntrCts -
11430 +                                       M_DIMINFO.PrevPort1RxIntrCts;
11431 +                               TxPort1IntDiff =
11432 +                                       pAC->Pnmi.Port[1].TxIntrCts -
11433 +                                       M_DIMINFO.PrevPort1TxIntrCts;
11434 +                       }
11435 +                       RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts -
11436 +                                       M_DIMINFO.PrevPort0RxIntrCts;
11437 +                       TxPort0IntDiff = pAC->Pnmi.Port[0].TxIntrCts -
11438 +                                       M_DIMINFO.PrevPort0TxIntrCts;
11439 +               }
11440 +               SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11441 +                               ("==>getIsrCalls (!CHIP_ID_YUKON_2)\n"));
11442 +               return (RxPort0IntDiff + RxPort1IntDiff +
11443 +                       TxPort0IntDiff + TxPort1IntDiff);
11444 +       }
11445
11446         /*
11447 -       ** The following lines have been commented out, because
11448 -       ** from kernel 2.5.44 onwards, the kernel-owned structure
11449 -       **
11450 -       **      struct kernel_stat kstat
11451 -       **
11452 -       ** is not marked as an exported symbol in the file
11453 +       ** We have a Yukon2 compliant chipset if we come up to here
11454         **
11455 -       **      kernel/ksyms.c
11456 -       **
11457 -       ** As a consequence, using this driver as KLM is not possible
11458 -       ** and any access of the structure kernel_stat via the
11459 -       ** dedicated macros kstat_cpu(i).cpustat.xxx is to be avoided.
11460 -       **
11461 -       ** The kstat-information might be added again in future
11462 -       ** versions of the 2.5.xx kernel, but for the time being,
11463 -       ** number of interrupts will serve as indication how much
11464 -       ** load we currently have...
11465 -       **
11466 -       ** for (NbrCpu = 0; NbrCpu < num_online_cpus(); NbrCpu++) {
11467 -       **      UserTime   = UserTime   + kstat_cpu(NbrCpu).cpustat.user;
11468 -       **      NiceTime   = NiceTime   + kstat_cpu(NbrCpu).cpustat.nice;
11469 -       **      SystemTime = SystemTime + kstat_cpu(NbrCpu).cpustat.system;
11470 -       ** }
11471 +       if (pAC->GIni.GIMacsFound == 2) {
11472 +               StatusPort1IntDiff = pAC->Pnmi.Port[1].StatusLeIntrCts -
11473 +                                       M_DIMINFO.PrevPort1StatusIntrCts;
11474 +       }
11475 +       StatusPort0IntDiff = pAC->Pnmi.Port[0].StatusLeIntrCts -
11476 +                               M_DIMINFO.PrevPort0StatusIntrCts;
11477         */
11478 -       SK_U64 ThresholdInts  = 0;
11479 -       SK_U64 IsrCallsPerSec = 0;
11480 -
11481 -       ThresholdInts  = ((M_DIMINFO.MaxModIntsPerSec *
11482 -                          C_INT_MOD_ENABLE_PERCENTAGE) + 100);
11483 -       IsrCallsPerSec = GetIsrCalls(pAC);
11484 -       if (IsrCallsPerSec >= ThresholdInts) {
11485 -           /*
11486 -           ** We do not know how much the real CPU-load is!
11487 -           ** Return 80% as a default in order to activate DIM
11488 -           */
11489 -           SystemLoad = 80;
11490 -           return (SystemLoad);
11491 -       }
11492 -
11493 -       UsedTime  = UserTime + NiceTime + SystemTime;
11494 -
11495 -       IdleTime  = jif * num_online_cpus() - UsedTime;
11496 -       TotalTime = UsedTime + IdleTime;
11497 -
11498 -       SystemLoad = ( 100 * (UsedTime  - M_DIMINFO.PrevUsedTime) ) /
11499 -                                               (TotalTime - M_DIMINFO.PrevTotalTime);
11500 +        SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11501 +                       ("==>getIsrCalls (CHIP_ID_YUKON_2)\n"));
11502 +       return (StatusPort0IntDiff + StatusPort1IntDiff);
11503 +}
11504
11505 -       if (M_DIMINFO.DisplayStats) {
11506 -               printk("Current system load is: %u\n", SystemLoad);
11507 +/*****************************************************************************
11508 + *
11509 + *     setCurrIntCtr - stores the current number of interrupts
11510 + *
11511 + * Description:
11512 + *     Stores the current number of occurred interrupts in the adapter
11513 + *     context. This is needed to evaluate the  umber of interrupts within
11514 + *     the moderation interval.
11515 + *
11516 + * Returns:    N/A
11517 + *
11518 + */
11519 +static void setCurrIntCtr(
11520 +SK_AC *pAC)  /* pointer to adapter control context */
11521 +{
11522 +        SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==>setCurrIntCtr\n"));
11523 +
11524 +       if (!CHIP_ID_YUKON_2(pAC)) {
11525 +               if (pAC->GIni.GIMacsFound == 2) {
11526 +                       M_DIMINFO.PrevPort1RxIntrCts = pAC->Pnmi.Port[1].RxIntrCts;
11527 +                       M_DIMINFO.PrevPort1TxIntrCts = pAC->Pnmi.Port[1].TxIntrCts;
11528 +               }
11529 +               M_DIMINFO.PrevPort0RxIntrCts = pAC->Pnmi.Port[0].RxIntrCts;
11530 +               M_DIMINFO.PrevPort0TxIntrCts = pAC->Pnmi.Port[0].TxIntrCts;
11531 +               SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11532 +                               ("<== setCurrIntCtr (!CHIP_ID_YUKON_2)\n"));
11533 +               return;
11534         }
11535
11536 -       M_DIMINFO.PrevTotalTime = TotalTime;
11537 -       M_DIMINFO.PrevUsedTime  = UsedTime;
11538 -
11539 -       return (SystemLoad);
11540 +       /*
11541 +       ** We have a Yukon2 compliant chipset if we come up to here
11542 +       **
11543 +       if (pAC->GIni.GIMacsFound == 2) {
11544 +               M_DIMINFO.PrevPort1StatusIntrCts = pAC->Pnmi.Port[1].StatusLeIntrCts;
11545 +       }
11546 +       M_DIMINFO.PrevPort0StatusIntrCts = pAC->Pnmi.Port[0].StatusLeIntrCts;
11547 +       */
11548 +        SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11549 +                       ("<== setCurrIntCtr (CHIP_ID_YUKON_2)\n"));
11550  }
11551
11552 -/*******************************************************************************
11553 -** Function     : GetIsrCalls
11554 -** Description  : Depending on the selected moderation mask, this function will
11555 -**                return the number of interrupts handled in the previous time-
11556 -**                frame. This evaluated number is based on the current number
11557 -**                of interrupts stored in PNMI-context and the previous stored
11558 -**                interrupts.
11559 -** Programmer   : Ralph Roesler
11560 -** Last Modified: 23-mar-03
11561 -** Returns      : int:   the number of interrupts being executed in the last
11562 -**                       timeframe
11563 -** Notes        : It makes only sense to call this function, when dynamic
11564 -**                interrupt moderation is applied
11565 -*******************************************************************************/
11566 -
11567 -static SK_U64
11568 -GetIsrCalls(SK_AC *pAC) {
11569 -    SK_U64   RxPort0IntDiff = 0;
11570 -    SK_U64   RxPort1IntDiff = 0;
11571 -    SK_U64   TxPort0IntDiff = 0;
11572 -    SK_U64   TxPort1IntDiff = 0;
11573 -
11574 -    if (pAC->DynIrqModInfo.MaskIrqModeration == IRQ_MASK_TX_ONLY) {
11575 -        if (pAC->GIni.GIMacsFound == 2) {
11576 -            TxPort1IntDiff = pAC->Pnmi.Port[1].TxIntrCts -
11577 -                             pAC->DynIrqModInfo.PrevPort1TxIntrCts;
11578 -        }
11579 -        TxPort0IntDiff = pAC->Pnmi.Port[0].TxIntrCts -
11580 -                         pAC->DynIrqModInfo.PrevPort0TxIntrCts;
11581 -    } else if (pAC->DynIrqModInfo.MaskIrqModeration == IRQ_MASK_RX_ONLY) {
11582 -        if (pAC->GIni.GIMacsFound == 2) {
11583 -            RxPort1IntDiff = pAC->Pnmi.Port[1].RxIntrCts -
11584 -                             pAC->DynIrqModInfo.PrevPort1RxIntrCts;
11585 -        }
11586 -        RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts -
11587 -                         pAC->DynIrqModInfo.PrevPort0RxIntrCts;
11588 -    } else {
11589 -        if (pAC->GIni.GIMacsFound == 2) {
11590 -            RxPort1IntDiff = pAC->Pnmi.Port[1].RxIntrCts -
11591 -                             pAC->DynIrqModInfo.PrevPort1RxIntrCts;
11592 -            TxPort1IntDiff = pAC->Pnmi.Port[1].TxIntrCts -
11593 -                             pAC->DynIrqModInfo.PrevPort1TxIntrCts;
11594 -        }
11595 -        RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts -
11596 -                         pAC->DynIrqModInfo.PrevPort0RxIntrCts;
11597 -        TxPort0IntDiff = pAC->Pnmi.Port[0].TxIntrCts -
11598 -                         pAC->DynIrqModInfo.PrevPort0TxIntrCts;
11599 -    }
11600 -
11601 -    return (RxPort0IntDiff + RxPort1IntDiff + TxPort0IntDiff + TxPort1IntDiff);
11602 +/*****************************************************************************
11603 + *
11604 + *     isIntModEnabled - returns the current state of interrupt moderation
11605 + *
11606 + * Description:
11607 + *     This function retrieves the current value of the interrupt moderation
11608 + *     command register. Its content determines whether any moderation is
11609 + *     running or not.
11610 + *
11611 + * Returns:
11612 + *     SK_TRUE : IRQ moderation is currently active
11613 + *     SK_FALSE: No IRQ moderation is active
11614 + */
11615 +static SK_BOOL isIntModEnabled(
11616 +SK_AC *pAC)  /* pointer to adapter control context */
11617 +{
11618 +       unsigned long CtrCmd;
11619 +
11620 +        SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==>isIntModEnabled\n"));
11621 +
11622 +       SK_IN32(pAC->IoBase, B2_IRQM_CTRL, &CtrCmd);
11623 +       if ((CtrCmd & TIM_START) == TIM_START) {
11624 +               SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11625 +                       ("<== isIntModEnabled (SK_TRUE)\n"));
11626 +               return SK_TRUE;
11627 +       }
11628 +        SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11629 +                       ("<== isIntModEnabled (SK_FALSE)\n"));
11630 +       return SK_FALSE;
11631  }
11632
11633 -/*******************************************************************************
11634 -** Function     : GetRxCalls
11635 -** Description  : This function will return the number of times a receive inter-
11636 -**                rupt was processed. This is needed to evaluate any resizing
11637 -**                factor.
11638 -** Programmer   : Ralph Roesler
11639 -** Last Modified: 23-mar-03
11640 -** Returns      : SK_U64: the number of RX-ints being processed
11641 -** Notes        : It makes only sense to call this function, when dynamic
11642 -**                interrupt moderation is applied
11643 -*******************************************************************************/
11644 -
11645 -static SK_U64
11646 -GetRxCalls(SK_AC *pAC) {
11647 -    SK_U64   RxPort0IntDiff = 0;
11648 -    SK_U64   RxPort1IntDiff = 0;
11649 -
11650 -    if (pAC->GIni.GIMacsFound == 2) {
11651 -        RxPort1IntDiff = pAC->Pnmi.Port[1].RxIntrCts -
11652 -                         pAC->DynIrqModInfo.PrevPort1RxIntrCts;
11653 -    }
11654 -    RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts -
11655 -                     pAC->DynIrqModInfo.PrevPort0RxIntrCts;
11656 -
11657 -    return (RxPort0IntDiff + RxPort1IntDiff);
11658 -}
11659 +/*****************************************************************************
11660 + *
11661 + *     enableIntMod - enables the interrupt moderation
11662 + *
11663 + * Description:
11664 + *     Enabling the interrupt moderation is done by putting the desired
11665 + *     moderation interval in the B2_IRQM_INI register, specifying the
11666 + *     desired maks in the B2_IRQM_MSK register and finally starting the
11667 + *     IRQ moderation timer using the B2_IRQM_CTRL register.
11668 + *
11669 + * Returns:    N/A
11670 + *
11671 + */
11672 +static void enableIntMod(
11673 +SK_AC *pAC)  /* pointer to adapter control context */
11674 +{
11675 +       unsigned long ModBase;
11676 +
11677 +        SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==> enableIntMod\n"));
11678 +
11679 +       if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
11680 +               ModBase = C_CLK_FREQ_GENESIS / M_DIMINFO.MaxModIntsPerSec;
11681 +       } else if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) {
11682 +               ModBase = C_CLK_FREQ_YUKON_EC / M_DIMINFO.MaxModIntsPerSec;
11683 +       } else {
11684 +               ModBase = C_CLK_FREQ_YUKON / M_DIMINFO.MaxModIntsPerSec;
11685 +       }
11686
11687 -/*******************************************************************************
11688 -** Function     : SetCurrIntCtr
11689 -** Description  : Will store the current number orf occured interrupts in the
11690 -**                adapter context. This is needed to evaluated the number of
11691 -**                interrupts within a current timeframe.
11692 -** Programmer   : Ralph Roesler
11693 -** Last Modified: 23-mar-03
11694 -** Returns      : void (!)
11695 -** Notes        : -
11696 -*******************************************************************************/
11697 -
11698 -static void
11699 -SetCurrIntCtr(SK_AC *pAC) {
11700 -    if (pAC->GIni.GIMacsFound == 2) {
11701 -        pAC->DynIrqModInfo.PrevPort1RxIntrCts = pAC->Pnmi.Port[1].RxIntrCts;
11702 -        pAC->DynIrqModInfo.PrevPort1TxIntrCts = pAC->Pnmi.Port[1].TxIntrCts;
11703 -    }
11704 -    pAC->DynIrqModInfo.PrevPort0RxIntrCts = pAC->Pnmi.Port[0].RxIntrCts;
11705 -    pAC->DynIrqModInfo.PrevPort0TxIntrCts = pAC->Pnmi.Port[0].TxIntrCts;
11706 -}
11707 +       SK_OUT32(pAC->IoBase, B2_IRQM_INI, ModBase);
11708 +       SK_OUT32(pAC->IoBase, B2_IRQM_MSK, M_DIMINFO.MaskIrqModeration);
11709 +       SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_START);
11710
11711 -/*******************************************************************************
11712 -** Function     : IsIntModEnabled()
11713 -** Description  : Retrieves the current value of the interrupts moderation
11714 -**                command register. Its content determines whether any
11715 -**                moderation is running or not.
11716 -** Programmer   : Ralph Roesler
11717 -** Last Modified: 23-mar-03
11718 -** Returns      : SK_TRUE  : if mod timer running
11719 -**                SK_FALSE : if no moderation is being performed
11720 -** Notes        : -
11721 -*******************************************************************************/
11722 -
11723 -static SK_BOOL
11724 -IsIntModEnabled(SK_AC *pAC) {
11725 -    unsigned long CtrCmd;
11726 -
11727 -    SK_IN32(pAC->IoBase, B2_IRQM_CTRL, &CtrCmd);
11728 -    if ((CtrCmd & TIM_START) == TIM_START) {
11729 -       return SK_TRUE;
11730 -    } else {
11731 -       return SK_FALSE;
11732 -    }
11733 +        SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("<== enableIntMod\n"));
11734  }
11735
11736 -/*******************************************************************************
11737 -** Function     : EnableIntMod()
11738 -** Description  : Enables the interrupt moderation using the values stored in
11739 -**                in the pAC->DynIntMod data structure
11740 -** Programmer   : Ralph Roesler
11741 -** Last Modified: 22-mar-03
11742 -** Returns      : -
11743 -** Notes        : -
11744 -*******************************************************************************/
11745 -
11746 -static void
11747 -EnableIntMod(SK_AC *pAC) {
11748 -    unsigned long ModBase;
11749 -
11750 -    if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
11751 -       ModBase = C_CLK_FREQ_GENESIS / pAC->DynIrqModInfo.MaxModIntsPerSec;
11752 -    } else {
11753 -       ModBase = C_CLK_FREQ_YUKON / pAC->DynIrqModInfo.MaxModIntsPerSec;
11754 -    }
11755 -
11756 -    SK_OUT32(pAC->IoBase, B2_IRQM_INI,  ModBase);
11757 -    SK_OUT32(pAC->IoBase, B2_IRQM_MSK,  pAC->DynIrqModInfo.MaskIrqModeration);
11758 -    SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_START);
11759 -    if (M_DIMINFO.DisplayStats) {
11760 -        printk("Enabled interrupt moderation (%i ints/sec)\n",
11761 -               M_DIMINFO.MaxModIntsPerSec);
11762 -    }
11763 -}
11764 +/*****************************************************************************
11765 + *
11766 + *     disableIntMod - disables the interrupt moderation
11767 + *
11768 + * Description:
11769 + *     Disabling the interrupt moderation is done by stopping the
11770 + *     IRQ moderation timer using the B2_IRQM_CTRL register.
11771 + *
11772 + * Returns:    N/A
11773 + *
11774 + */
11775 +static void disableIntMod(
11776 +SK_AC *pAC)  /* pointer to adapter control context */
11777 +{
11778 +        SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==> disableIntMod\n"));
11779
11780 -/*******************************************************************************
11781 -** Function     : DisableIntMod()
11782 -** Description  : Disbles the interrupt moderation independent of what inter-
11783 -**                rupts are running or not
11784 -** Programmer   : Ralph Roesler
11785 -** Last Modified: 23-mar-03
11786 -** Returns      : -
11787 -** Notes        : -
11788 -*******************************************************************************/
11789 -
11790 -static void
11791 -DisableIntMod(SK_AC *pAC) {
11792 -
11793 -    SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_STOP);
11794 -    if (M_DIMINFO.DisplayStats) {
11795 -        printk("Disabled interrupt moderation\n");
11796 -    }
11797 -}
11798 +       SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_STOP);
11799
11800 -/*******************************************************************************
11801 -** Function     : ResizeDimTimerDuration();
11802 -** Description  : Checks the current used descriptor ratio and resizes the
11803 -**                duration timer (longer/smaller) if possible.
11804 -** Programmer   : Ralph Roesler
11805 -** Last Modified: 23-mar-03
11806 -** Returns      : -
11807 -** Notes        : There are both maximum and minimum timer duration value.
11808 -**                This function assumes that interrupt moderation is already
11809 -**                enabled!
11810 -*******************************************************************************/
11811 -
11812 -static void
11813 -ResizeDimTimerDuration(SK_AC *pAC) {
11814 -    SK_BOOL IncreaseTimerDuration;
11815 -    int     TotalMaxNbrDescr;
11816 -    int     UsedDescrRatio;
11817 -    int     RatioDiffAbs;
11818 -    int     RatioDiffRel;
11819 -    int     NewMaxModIntsPerSec;
11820 -    int     ModAdjValue;
11821 -    long    ModBase;
11822 -
11823 -    /*
11824 -    ** Check first if we are allowed to perform any modification
11825 -    */
11826 -    if (IsIntModEnabled(pAC)) {
11827 -        if (M_DIMINFO.IntModTypeSelect != C_INT_MOD_DYNAMIC) {
11828 -            return;
11829 -        } else {
11830 -            if (M_DIMINFO.ModJustEnabled) {
11831 -                M_DIMINFO.ModJustEnabled = SK_FALSE;
11832 -                return;
11833 -            }
11834 -        }
11835 -    }
11836 -
11837 -    /*
11838 -    ** If we got until here, we have to evaluate the amount of the
11839 -    ** descriptor ratio change...
11840 -    */
11841 -    TotalMaxNbrDescr = pAC->RxDescrPerRing * GetRxCalls(pAC);
11842 -    UsedDescrRatio   = (M_DIMINFO.NbrProcessedDescr * 100) / TotalMaxNbrDescr;
11843 -
11844 -    if (UsedDescrRatio > M_DIMINFO.PrevUsedDescrRatio) {
11845 -        RatioDiffAbs = (UsedDescrRatio - M_DIMINFO.PrevUsedDescrRatio);
11846 -        RatioDiffRel = (RatioDiffAbs * 100) / UsedDescrRatio;
11847 -        M_DIMINFO.PrevUsedDescrRatio = UsedDescrRatio;
11848 -        IncreaseTimerDuration = SK_FALSE;  /* in other words: DECREASE */
11849 -    } else if (UsedDescrRatio < M_DIMINFO.PrevUsedDescrRatio) {
11850 -        RatioDiffAbs = (M_DIMINFO.PrevUsedDescrRatio - UsedDescrRatio);
11851 -        RatioDiffRel = (RatioDiffAbs * 100) / M_DIMINFO.PrevUsedDescrRatio;
11852 -        M_DIMINFO.PrevUsedDescrRatio = UsedDescrRatio;
11853 -        IncreaseTimerDuration = SK_TRUE;   /* in other words: INCREASE */
11854 -    } else {
11855 -        RatioDiffAbs = (M_DIMINFO.PrevUsedDescrRatio - UsedDescrRatio);
11856 -        RatioDiffRel = (RatioDiffAbs * 100) / M_DIMINFO.PrevUsedDescrRatio;
11857 -        M_DIMINFO.PrevUsedDescrRatio = UsedDescrRatio;
11858 -        IncreaseTimerDuration = SK_TRUE;   /* in other words: INCREASE */
11859 -    }
11860 -
11861 -    /*
11862 -    ** Now we can determine the change in percent
11863 -    */
11864 -    if ((RatioDiffRel >= 0) && (RatioDiffRel <= 5) ) {
11865 -       ModAdjValue = 1;  /*  1% change - maybe some other value in future */
11866 -    } else if ((RatioDiffRel > 5) && (RatioDiffRel <= 10) ) {
11867 -       ModAdjValue = 1;  /*  1% change - maybe some other value in future */
11868 -    } else if ((RatioDiffRel > 10) && (RatioDiffRel <= 15) ) {
11869 -       ModAdjValue = 1;  /*  1% change - maybe some other value in future */
11870 -    } else {
11871 -       ModAdjValue = 1;  /*  1% change - maybe some other value in future */
11872 -    }
11873 -
11874 -    if (IncreaseTimerDuration) {
11875 -       NewMaxModIntsPerSec =  M_DIMINFO.MaxModIntsPerSec +
11876 -                             (M_DIMINFO.MaxModIntsPerSec * ModAdjValue) / 100;
11877 -    } else {
11878 -       NewMaxModIntsPerSec =  M_DIMINFO.MaxModIntsPerSec -
11879 -                             (M_DIMINFO.MaxModIntsPerSec * ModAdjValue) / 100;
11880 -    }
11881 -
11882 -    /*
11883 -    ** Check if we exceed boundaries...
11884 -    */
11885 -    if ( (NewMaxModIntsPerSec > M_DIMINFO.MaxModIntsPerSecUpperLimit) ||
11886 -         (NewMaxModIntsPerSec < M_DIMINFO.MaxModIntsPerSecLowerLimit)) {
11887 -        if (M_DIMINFO.DisplayStats) {
11888 -            printk("Cannot change ModTim from %i to %i ints/sec\n",
11889 -                   M_DIMINFO.MaxModIntsPerSec, NewMaxModIntsPerSec);
11890 -        }
11891 -        return;
11892 -    } else {
11893 -        if (M_DIMINFO.DisplayStats) {
11894 -            printk("Resized ModTim from %i to %i ints/sec\n",
11895 -                   M_DIMINFO.MaxModIntsPerSec, NewMaxModIntsPerSec);
11896 -        }
11897 -    }
11898 -
11899 -    M_DIMINFO.MaxModIntsPerSec = NewMaxModIntsPerSec;
11900 -
11901 -    if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
11902 -        ModBase = C_CLK_FREQ_GENESIS / pAC->DynIrqModInfo.MaxModIntsPerSec;
11903 -    } else {
11904 -        ModBase = C_CLK_FREQ_YUKON / pAC->DynIrqModInfo.MaxModIntsPerSec;
11905 -    }
11906 -
11907 -    /*
11908 -    ** We do not need to touch any other registers
11909 -    */
11910 -    SK_OUT32(pAC->IoBase, B2_IRQM_INI, ModBase);
11911 +        SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("<== disableIntMod\n"));
11912  }
11913
11914  /*******************************************************************************
11915 -** Function     : DisplaySelectedModerationType()
11916 -** Description  : Displays what type of moderation we have
11917 -** Programmer   : Ralph Roesler
11918 -** Last Modified: 23-mar-03
11919 -** Returns      : void!
11920 -** Notes        : -
11921 -*******************************************************************************/
11922 -
11923 -static void
11924 -DisplaySelectedModerationType(SK_AC *pAC) {
11925 -
11926 -    if (pAC->DynIrqModInfo.DisplayStats) {
11927 -        if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_STATIC) {
11928 -             printk("Static int moderation runs with %i INTS/sec\n",
11929 -                    pAC->DynIrqModInfo.MaxModIntsPerSec);
11930 -        } else if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
11931 -             if (IsIntModEnabled(pAC)) {
11932 -                printk("Dynamic int moderation runs with %i INTS/sec\n",
11933 -                       pAC->DynIrqModInfo.MaxModIntsPerSec);
11934 -             } else {
11935 -                printk("Dynamic int moderation currently not applied\n");
11936 -             }
11937 -        } else {
11938 -             printk("No interrupt moderation selected!\n");
11939 -        }
11940 -    }
11941 -}
11942 -
11943 -/*******************************************************************************
11944 -** Function     : DisplaySelectedModerationMask()
11945 -** Description  : Displays what interrupts are moderated
11946 -** Programmer   : Ralph Roesler
11947 -** Last Modified: 23-mar-03
11948 -** Returns      : void!
11949 -** Notes        : -
11950 -*******************************************************************************/
11951 -
11952 -static void
11953 -DisplaySelectedModerationMask(SK_AC *pAC) {
11954 -
11955 -    if (pAC->DynIrqModInfo.DisplayStats) {
11956 -        if (pAC->DynIrqModInfo.IntModTypeSelect != C_INT_MOD_NONE) {
11957 -            switch (pAC->DynIrqModInfo.MaskIrqModeration) {
11958 -                case IRQ_MASK_TX_ONLY:
11959 -                   printk("Only Tx-interrupts are moderated\n");
11960 -                   break;
11961 -                case IRQ_MASK_RX_ONLY:
11962 -                   printk("Only Rx-interrupts are moderated\n");
11963 -                   break;
11964 -                case IRQ_MASK_SP_ONLY:
11965 -                   printk("Only special-interrupts are moderated\n");
11966 -                   break;
11967 -                case IRQ_MASK_TX_RX:
11968 -                   printk("Tx- and Rx-interrupts are moderated\n");
11969 -                   break;
11970 -                case IRQ_MASK_SP_RX:
11971 -                   printk("Special- and Rx-interrupts are moderated\n");
11972 -                   break;
11973 -                case IRQ_MASK_SP_TX:
11974 -                   printk("Special- and Tx-interrupts are moderated\n");
11975 -                   break;
11976 -                case IRQ_MASK_RX_TX_SP:
11977 -                   printk("All Rx-, Tx and special-interrupts are moderated\n");
11978 -                   break;
11979 -                default:
11980 -                   printk("Don't know what is moderated\n");
11981 -                   break;
11982 -            }
11983 -        } else {
11984 -            printk("No specific interrupts masked for moderation\n");
11985 -        }
11986 -    }
11987 -}
11988 -
11989 -/*******************************************************************************
11990 -** Function     : DisplayDescrRatio
11991 -** Description  : Like the name states...
11992 -** Programmer   : Ralph Roesler
11993 -** Last Modified: 23-mar-03
11994 -** Returns      : void!
11995 -** Notes        : -
11996 -*******************************************************************************/
11997 -
11998 -static void
11999 -DisplayDescrRatio(SK_AC *pAC) {
12000 -    int TotalMaxNbrDescr = 0;
12001 -
12002 -    if (pAC->DynIrqModInfo.DisplayStats) {
12003 -        TotalMaxNbrDescr = pAC->RxDescrPerRing * GetRxCalls(pAC);
12004 -        printk("Ratio descriptors: %i/%i\n",
12005 -               M_DIMINFO.NbrProcessedDescr, TotalMaxNbrDescr);
12006 -    }
12007 -}
12008 -
12009 -/*******************************************************************************
12010 -**
12011 -** End of file
12012 -**
12013 -*******************************************************************************/
12014 + *
12015 + * End of file
12016 + *
12017 + ******************************************************************************/
12018 diff -ruN linux/drivers/net/sk98lin/skethtool.c linux-new/drivers/net/sk98lin/skethtool.c
12019 --- linux/drivers/net/sk98lin/skethtool.c       2006-09-20 05:42:06.000000000 +0200
12020 +++ linux-new/drivers/net/sk98lin/skethtool.c   2006-07-28 14:13:56.000000000 +0200
12021 @@ -2,8 +2,8 @@
12022   *
12023   * Name:        skethtool.c
12024   * Project:     GEnesis, PCI Gigabit Ethernet Adapter
12025 - * Version:     $Revision$
12026 - * Date:        $Date$
12027 + * Version:     $Revision$
12028 + * Date:        $Date$
12029   * Purpose:     All functions regarding ethtool handling
12030   *
12031   ******************************************************************************/
12032 @@ -11,7 +11,7 @@
12033  /******************************************************************************
12034   *
12035   *     (C)Copyright 1998-2002 SysKonnect GmbH.
12036 - *     (C)Copyright 2002-2004 Marvell.
12037 + *     (C)Copyright 2002-2005 Marvell.
12038   *
12039   *     Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet
12040   *      Server Adapters.
12041 @@ -21,9 +21,6 @@
12042   *
12043   *     Address all question to: linux@syskonnect.de
12044   *
12045 - *     The technical manual for the adapters is available from SysKonnect's
12046 - *     web pages: www.syskonnect.com
12047 - *
12048   *     This program is free software; you can redistribute it and/or modify
12049   *     it under the terms of the GNU General Public License as published by
12050   *     the Free Software Foundation; either version 2 of the License, or
12051 @@ -36,10 +33,18 @@
12052  #include "h/skdrv1st.h"
12053  #include "h/skdrv2nd.h"
12054  #include "h/skversion.h"
12055 -
12056  #include <linux/ethtool.h>
12057 +#include <linux/module.h>
12058  #include <linux/timer.h>
12059 -#include <linux/delay.h>
12060 +
12061 +/******************************************************************************
12062 + *
12063 + * External Functions and Data
12064 + *
12065 + *****************************************************************************/
12066 +
12067 +extern void SkDimDisableModeration(SK_AC *pAC, int CurrentModeration);
12068 +extern void SkDimEnableModerationIfNeeded(SK_AC *pAC);
12069
12070  /******************************************************************************
12071   *
12072 @@ -47,6 +52,12 @@
12073   *
12074   *****************************************************************************/
12075
12076 +#ifndef ETHT_STATSTRING_LEN
12077 +#define ETHT_STATSTRING_LEN 32
12078 +#endif
12079 +
12080 +#define SK98LIN_STAT(m)        sizeof(((SK_AC *)0)->m),offsetof(SK_AC, m)
12081 +
12082  #define SUPP_COPPER_ALL (SUPPORTED_10baseT_Half  | SUPPORTED_10baseT_Full  | \
12083                           SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
12084                           SUPPORTED_1000baseT_Half| SUPPORTED_1000baseT_Full| \
12085 @@ -65,6 +76,454 @@
12086                           ADVERTISED_FIBRE          | \
12087                           ADVERTISED_Autoneg)
12088
12089 +/******************************************************************************
12090 + *
12091 + * Local Function Prototypes
12092 + *
12093 + *****************************************************************************/
12094 +
12095 +#ifdef ETHTOOL_GSET
12096 +static void getSettings(SK_AC *pAC, int port, struct ethtool_cmd *ecmd);
12097 +#endif
12098 +#ifdef ETHTOOL_SSET
12099 +static int setSettings(SK_AC *pAC, int port, struct ethtool_cmd *ecmd);
12100 +#endif
12101 +#ifdef ETHTOOL_GPAUSEPARAM
12102 +static void getPauseParams(SK_AC *pAC, int port, struct ethtool_pauseparam *epause);
12103 +#endif
12104 +#ifdef ETHTOOL_SPAUSEPARAM
12105 +static int setPauseParams(SK_AC *pAC, int port, struct ethtool_pauseparam *epause);
12106 +#endif
12107 +#ifdef ETHTOOL_GDRVINFO
12108 +static void getDriverInfo(SK_AC *pAC, int port, struct ethtool_drvinfo *edrvinfo);
12109 +#endif
12110 +#ifdef ETHTOOL_PHYS_ID
12111 +static int startLocateNIC(SK_AC *pAC, int port, struct ethtool_value *blinkSecs);
12112 +static void toggleLeds(unsigned long ptr);
12113 +#endif
12114 +#ifdef ETHTOOL_GCOALESCE
12115 +static void getModerationParams(SK_AC *pAC, int port, struct ethtool_coalesce *ecoalesc);
12116 +#endif
12117 +#ifdef ETHTOOL_SCOALESCE
12118 +static int setModerationParams(SK_AC *pAC, int port, struct ethtool_coalesce *ecoalesc);
12119 +#endif
12120 +#ifdef ETHTOOL_GWOL
12121 +static void getWOLsettings(SK_AC *pAC, int port, struct ethtool_wolinfo *ewol);
12122 +#endif
12123 +#ifdef ETHTOOL_SWOL
12124 +static int setWOLsettings(SK_AC *pAC, int port, struct ethtool_wolinfo *ewol);
12125 +#endif
12126 +
12127 +static int getPortNumber(struct net_device *netdev, struct ifreq *ifr);
12128 +
12129 +/******************************************************************************
12130 + *
12131 + * Local Variables
12132 + *
12133 + *****************************************************************************/
12134 +
12135 +struct sk98lin_stats {
12136 +       char stat_string[ETHT_STATSTRING_LEN];
12137 +       int  sizeof_stat;
12138 +       int  stat_offset;
12139 +};
12140 +
12141 +static struct sk98lin_stats sk98lin_etht_stats_port0[] = {
12142 +       { "rx_packets" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxOkCts) },
12143 +       { "tx_packets" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxOkCts) },
12144 +       { "rx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxOctetsOkCts) },
12145 +       { "tx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxOctetsOkCts) },
12146 +       { "rx_errors" , SK98LIN_STAT(PnmiStruct.InErrorsCts) },
12147 +       { "tx_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxSingleCollisionCts) },
12148 +       { "rx_dropped" , SK98LIN_STAT(PnmiStruct.RxNoBufCts) },
12149 +       { "tx_dropped" , SK98LIN_STAT(PnmiStruct.TxNoBufCts) },
12150 +       { "multicasts" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxMulticastOkCts) },
12151 +       { "collisions" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxSingleCollisionCts) },
12152 +       { "rx_length_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxRuntCts) },
12153 +       { "rx_buffer_overflow_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxFifoOverflowCts) },
12154 +       { "rx_crc_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxFcsCts) },
12155 +       { "rx_frame_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxFramingCts) },
12156 +       { "rx_too_short_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxShortsCts) },
12157 +       { "rx_too_long_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxTooLongCts) },
12158 +       { "rx_carrier_extension_errors", SK98LIN_STAT(PnmiStruct.Stat[0].StatRxCextCts) },
12159 +       { "rx_symbol_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxSymbolCts) },
12160 +       { "rx_llc_mac_size_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxIRLengthCts) },
12161 +       { "rx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxCarrierCts) },
12162 +       { "rx_jabber_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxJabberCts) },
12163 +       { "rx_missed_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxMissedCts) },
12164 +       { "tx_abort_collision_errors" , SK98LIN_STAT(stats.tx_aborted_errors) },
12165 +       { "tx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxCarrierCts) },
12166 +       { "tx_buffer_underrun_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxFifoUnderrunCts) },
12167 +       { "tx_heartbeat_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxCarrierCts) } ,
12168 +       { "tx_window_errors" , SK98LIN_STAT(stats.tx_window_errors) }
12169 +};
12170 +
12171 +static struct sk98lin_stats sk98lin_etht_stats_port1[] = {
12172 +       { "rx_packets" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxOkCts) },
12173 +       { "tx_packets" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxOkCts) },
12174 +       { "rx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxOctetsOkCts) },
12175 +       { "tx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxOctetsOkCts) },
12176 +       { "rx_errors" , SK98LIN_STAT(PnmiStruct.InErrorsCts) },
12177 +       { "tx_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxSingleCollisionCts) },
12178 +       { "rx_dropped" , SK98LIN_STAT(PnmiStruct.RxNoBufCts) },
12179 +       { "tx_dropped" , SK98LIN_STAT(PnmiStruct.TxNoBufCts) },
12180 +       { "multicasts" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxMulticastOkCts) },
12181 +       { "collisions" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxSingleCollisionCts) },
12182 +       { "rx_length_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxRuntCts) },
12183 +       { "rx_buffer_overflow_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxFifoOverflowCts) },
12184 +       { "rx_crc_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxFcsCts) },
12185 +       { "rx_frame_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxFramingCts) },
12186 +       { "rx_too_short_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxShortsCts) },
12187 +       { "rx_too_long_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxTooLongCts) },
12188 +       { "rx_carrier_extension_errors", SK98LIN_STAT(PnmiStruct.Stat[1].StatRxCextCts) },
12189 +       { "rx_symbol_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxSymbolCts) },
12190 +       { "rx_llc_mac_size_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxIRLengthCts) },
12191 +       { "rx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxCarrierCts) },
12192 +       { "rx_jabber_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxJabberCts) },
12193 +       { "rx_missed_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxMissedCts) },
12194 +       { "tx_abort_collision_errors" , SK98LIN_STAT(stats.tx_aborted_errors) },
12195 +       { "tx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxCarrierCts) },
12196 +       { "tx_buffer_underrun_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxFifoUnderrunCts) },
12197 +       { "tx_heartbeat_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxCarrierCts) } ,
12198 +       { "tx_window_errors" , SK98LIN_STAT(stats.tx_window_errors) }
12199 +};
12200 +
12201 +#define SK98LIN_STATS_LEN sizeof(sk98lin_etht_stats_port0) / sizeof(struct sk98lin_stats)
12202 +
12203 +static int nbrBlinkQuarterSeconds;
12204 +static int currentPortIndex;
12205 +static SK_BOOL isLocateNICrunning   = SK_FALSE;
12206 +static SK_BOOL isDualNetCard        = SK_FALSE;
12207 +static SK_BOOL doSwitchLEDsOn       = SK_FALSE;
12208 +static SK_BOOL boardWasDown[2]      = { SK_FALSE, SK_FALSE };
12209 +static struct timer_list locateNICtimer;
12210 +
12211 +/******************************************************************************
12212 + *
12213 + * Global Functions
12214 + *
12215 + *****************************************************************************/
12216 +
12217 +/*****************************************************************************
12218 + *
12219 + *     SkEthIoctl - IOCTL entry point for all ethtool queries
12220 + *
12221 + * Description:
12222 + *     Any IOCTL request that has to deal with the ethtool command tool is
12223 + *     dispatched via this function.
12224 + *
12225 + * Returns:
12226 + *     ==0:    everything fine, no error
12227 + *     !=0:    the return value is the error code of the failure
12228 + */
12229 +int SkEthIoctl(
12230 +struct net_device *netdev,  /* the pointer to netdev structure       */
12231 +struct ifreq      *ifr)     /* what interface the request refers to? */
12232 +{
12233 +       DEV_NET             *pNet        = (DEV_NET*) netdev->priv;
12234 +       SK_AC               *pAC         = pNet->pAC;
12235 +       void                *pAddr       = ifr->ifr_data;
12236 +       int                  port        = getPortNumber(netdev, ifr);
12237 +       SK_PNMI_STRUCT_DATA *pPnmiStruct = &pAC->PnmiStruct;
12238 +       SK_U32               Size        = sizeof(SK_PNMI_STRUCT_DATA);
12239 +       SK_U32               cmd;
12240 +       struct sk98lin_stats *sk98lin_etht_stats =
12241 +               (port == 0) ? sk98lin_etht_stats_port0 : sk98lin_etht_stats_port1;
12242 +
12243 +        if (get_user(cmd, (uint32_t *) pAddr)) {
12244 +                return -EFAULT;
12245 +       }
12246 +
12247 +       switch(cmd) {
12248 +#ifdef ETHTOOL_GSET
12249 +       case ETHTOOL_GSET: {
12250 +               struct ethtool_cmd ecmd = { ETHTOOL_GSET };
12251 +               getSettings(pAC, port, &ecmd);
12252 +               if(copy_to_user(pAddr, &ecmd, sizeof(ecmd))) {
12253 +                       return -EFAULT;
12254 +               }
12255 +               return 0;
12256 +       }
12257 +       break;
12258 +#endif
12259 +#ifdef ETHTOOL_SSET
12260 +       case ETHTOOL_SSET: {
12261 +               struct ethtool_cmd ecmd;
12262 +               if(copy_from_user(&ecmd, pAddr, sizeof(ecmd))) {
12263 +                       return -EFAULT;
12264 +               }
12265 +               return setSettings(pAC, port, &ecmd);
12266 +       }
12267 +       break;
12268 +#endif
12269 +#ifdef ETHTOOL_GLINK
12270 +       case ETHTOOL_GLINK: {
12271 +               struct ethtool_value edata = { ETHTOOL_GLINK };
12272 +               edata.data = netif_carrier_ok(netdev);
12273 +               if (copy_to_user(pAddr, &edata, sizeof(edata)))
12274 +                       return -EFAULT;
12275 +               return 0;
12276 +       }
12277 +#endif
12278 +#ifdef ETHTOOL_GDRVINFO
12279 +       case ETHTOOL_GDRVINFO: {
12280 +               struct ethtool_drvinfo drvinfo = { ETHTOOL_GDRVINFO };
12281 +               getDriverInfo(pAC, port, &drvinfo);
12282 +               if(copy_to_user(pAddr, &drvinfo, sizeof(drvinfo))) {
12283 +                       return -EFAULT;
12284 +               }
12285 +               return 0;
12286 +       }
12287 +       break;
12288 +#endif
12289 +#ifdef ETHTOOL_GSTRINGS
12290 +       case ETHTOOL_GSTRINGS: {
12291 +               struct ethtool_gstrings gstrings = { ETHTOOL_GSTRINGS };
12292 +               char *strings = NULL;
12293 +               int err = 0;
12294 +               if(copy_from_user(&gstrings, pAddr, sizeof(gstrings))) {
12295 +                       return -EFAULT;
12296 +               }
12297 +               switch(gstrings.string_set) {
12298 +#ifdef ETHTOOL_GSTATS
12299 +                       case ETH_SS_STATS: {
12300 +                               int i;
12301 +                               gstrings.len = SK98LIN_STATS_LEN;
12302 +                               if ((strings = kmalloc(SK98LIN_STATS_LEN*ETHT_STATSTRING_LEN,GFP_KERNEL)) == NULL) {
12303 +                                       return -ENOMEM;
12304 +                               }
12305 +                               for(i=0; i < SK98LIN_STATS_LEN; i++) {
12306 +                                       memcpy(&strings[i * ETHT_STATSTRING_LEN],
12307 +                                               &(sk98lin_etht_stats[i].stat_string),
12308 +                                               ETHT_STATSTRING_LEN);
12309 +                               }
12310 +                       }
12311 +                       break;
12312 +#endif
12313 +                       default:
12314 +                               return -EOPNOTSUPP;
12315 +               }
12316 +               if(copy_to_user(pAddr, &gstrings, sizeof(gstrings))) {
12317 +                       err = -EFAULT;
12318 +               }
12319 +               pAddr = (void *) ((unsigned long int) pAddr + offsetof(struct ethtool_gstrings, data));
12320 +               if(!err && copy_to_user(pAddr, strings, gstrings.len * ETH_GSTRING_LEN)) {
12321 +                       err = -EFAULT;
12322 +               }
12323 +               kfree(strings);
12324 +               return err;
12325 +       }
12326 +#endif
12327 +#ifdef ETHTOOL_GSTATS
12328 +       case ETHTOOL_GSTATS: {
12329 +               struct {
12330 +                       struct ethtool_stats eth_stats;
12331 +                       uint64_t data[SK98LIN_STATS_LEN];
12332 +               } stats = { {ETHTOOL_GSTATS, SK98LIN_STATS_LEN} };
12333 +               int i;
12334 +
12335 +               if (netif_running(pAC->dev[port])) {
12336 +                       SkPnmiGetStruct(pAC, pAC->IoBase, pPnmiStruct, &Size, port);
12337 +               }
12338 +               for(i = 0; i < SK98LIN_STATS_LEN; i++) {
12339 +                       if (netif_running(pAC->dev[port])) {
12340 +                               stats.data[i] = (sk98lin_etht_stats[i].sizeof_stat ==
12341 +                                       sizeof(uint64_t)) ?
12342 +                                       *(uint64_t *)((char *)pAC +
12343 +                                               sk98lin_etht_stats[i].stat_offset) :
12344 +                                       *(uint32_t *)((char *)pAC +
12345 +                                               sk98lin_etht_stats[i].stat_offset);
12346 +                       } else {
12347 +                               stats.data[i] = (sk98lin_etht_stats[i].sizeof_stat ==
12348 +                                       sizeof(uint64_t)) ? (uint64_t) 0 : (uint32_t) 0;
12349 +                       }
12350 +               }
12351 +               if(copy_to_user(pAddr, &stats, sizeof(stats))) {
12352 +                       return -EFAULT;
12353 +               }
12354 +               return 0;
12355 +       }
12356 +#endif
12357 +#ifdef ETHTOOL_PHYS_ID
12358 +       case ETHTOOL_PHYS_ID: {
12359 +               struct ethtool_value blinkSecs;
12360 +               if(copy_from_user(&blinkSecs, pAddr, sizeof(blinkSecs))) {
12361 +                       return -EFAULT;
12362 +               }
12363 +               return startLocateNIC(pAC, port, &blinkSecs);
12364 +       }
12365 +#endif
12366 +#ifdef ETHTOOL_GPAUSEPARAM
12367 +       case ETHTOOL_GPAUSEPARAM: {
12368 +               struct ethtool_pauseparam epause = { ETHTOOL_GPAUSEPARAM };
12369 +               getPauseParams(pAC, port, &epause);
12370 +               if(copy_to_user(pAddr, &epause, sizeof(epause))) {
12371 +                       return -EFAULT;
12372 +               }
12373 +               return 0;
12374 +       }
12375 +#endif
12376 +#ifdef ETHTOOL_SPAUSEPARAM
12377 +       case ETHTOOL_SPAUSEPARAM: {
12378 +               struct ethtool_pauseparam epause;
12379 +               if(copy_from_user(&epause, pAddr, sizeof(epause))) {
12380 +                       return -EFAULT;
12381 +               }
12382 +               return setPauseParams(pAC, port, &epause);
12383 +       }
12384 +#endif
12385 +#ifdef ETHTOOL_GSG
12386 +       case ETHTOOL_GSG: {
12387 +               struct ethtool_value edata = { ETHTOOL_GSG };
12388 +               edata.data = (netdev->features & NETIF_F_SG) != 0;
12389 +               if (copy_to_user(pAddr, &edata, sizeof(edata))) {
12390 +                       return -EFAULT;
12391 +               }
12392 +               return 0;
12393 +       }
12394 +#endif
12395 +#ifdef ETHTOOL_SSG
12396 +       case ETHTOOL_SSG: {
12397 +               struct ethtool_value edata;
12398 +               if (copy_from_user(&edata, pAddr, sizeof(edata))) {
12399 +                        return -EFAULT;
12400 +               }
12401 +               if (pAC->ChipsetType) { /* Don't handle if Genesis */
12402 +                       if (edata.data) {
12403 +                               netdev->features |= NETIF_F_SG;
12404 +                       } else {
12405 +                               netdev->features &= ~NETIF_F_SG;
12406 +                       }
12407 +               }
12408 +               return 0;
12409 +       }
12410 +#endif
12411 +#ifdef ETHTOOL_GRXCSUM
12412 +       case ETHTOOL_GRXCSUM: {
12413 +               struct ethtool_value edata = { ETHTOOL_GRXCSUM };
12414 +               edata.data = pAC->RxPort[port].UseRxCsum;
12415 +               if (copy_to_user(pAddr, &edata, sizeof(edata))) {
12416 +                       return -EFAULT;
12417 +               }
12418 +               return 0;
12419 +       }
12420 +#endif
12421 +#ifdef ETHTOOL_SRXCSUM
12422 +       case ETHTOOL_SRXCSUM: {
12423 +               struct ethtool_value edata;
12424 +               if (copy_from_user(&edata, pAddr, sizeof(edata))) {
12425 +                       return -EFAULT;
12426 +               }
12427 +               pAC->RxPort[port].UseRxCsum = edata.data;
12428 +                return 0;
12429 +       }
12430 +#endif
12431 +#ifdef ETHTOOL_GTXCSUM
12432 +       case ETHTOOL_GTXCSUM: {
12433 +               struct ethtool_value edata = { ETHTOOL_GTXCSUM };
12434 +               edata.data = ((netdev->features & NETIF_F_IP_CSUM) != 0);
12435 +               if (copy_to_user(pAddr, &edata, sizeof(edata))) {
12436 +                       return -EFAULT;
12437 +               }
12438 +               return 0;
12439 +       }
12440 +#endif
12441 +#ifdef ETHTOOL_STXCSUM
12442 +       case ETHTOOL_STXCSUM: {
12443 +               struct ethtool_value edata;
12444 +               if (copy_from_user(&edata, pAddr, sizeof(edata))) {
12445 +                       return -EFAULT;
12446 +               }
12447 +               if (pAC->ChipsetType) { /* Don't handle if Genesis */
12448 +                       if (edata.data) {
12449 +                               netdev->features |= NETIF_F_IP_CSUM;
12450 +                       } else {
12451 +                               netdev->features &= ~NETIF_F_IP_CSUM;
12452 +                       }
12453 +               }
12454 +               return 0;
12455 +       }
12456 +#endif
12457 +#ifdef ETHTOOL_NWAY_RST
12458 +       case ETHTOOL_NWAY_RST: {
12459 +               if(netif_running(netdev)) {
12460 +                       (*netdev->stop)(netdev);
12461 +                       (*netdev->open)(netdev);
12462 +               }
12463 +               return 0;
12464 +       }
12465 +#endif
12466 +#ifdef NETIF_F_TSO
12467 +#ifdef ETHTOOL_GTSO
12468 +       case ETHTOOL_GTSO: {
12469 +               struct ethtool_value edata = { ETHTOOL_GTSO };
12470 +               edata.data = (netdev->features & NETIF_F_TSO) != 0;
12471 +               if (copy_to_user(pAddr, &edata, sizeof(edata))) {
12472 +                       return -EFAULT;
12473 +               }
12474 +               return 0;
12475 +       }
12476 +#endif
12477 +#ifdef ETHTOOL_STSO
12478 +       case ETHTOOL_STSO: {
12479 +               struct ethtool_value edata;
12480 +               if (CHIP_ID_YUKON_2(pAC)) {
12481 +                       if (copy_from_user(&edata, pAddr, sizeof(edata))) {
12482 +                               return -EFAULT;
12483 +                       }
12484 +                       if (edata.data) {
12485 +                               netdev->features |= NETIF_F_TSO;
12486 +                       } else {
12487 +                               netdev->features &= ~NETIF_F_TSO;
12488 +                       }
12489 +                       return 0;
12490 +               }
12491 +                return -EOPNOTSUPP;
12492 +       }
12493 +#endif
12494 +#endif
12495 +#ifdef ETHTOOL_GCOALESCE
12496 +       case ETHTOOL_GCOALESCE: {
12497 +               struct ethtool_coalesce ecoalesc = { ETHTOOL_GCOALESCE };
12498 +               getModerationParams(pAC, port, &ecoalesc);
12499 +               if(copy_to_user(pAddr, &ecoalesc, sizeof(ecoalesc))) {
12500 +                       return -EFAULT;
12501 +               }
12502 +               return 0;
12503 +       }
12504 +#endif
12505 +#ifdef ETHTOOL_SCOALESCE
12506 +       case ETHTOOL_SCOALESCE: {
12507 +               struct ethtool_coalesce ecoalesc;
12508 +               if(copy_from_user(&ecoalesc, pAddr, sizeof(ecoalesc))) {
12509 +                       return -EFAULT;
12510 +               }
12511 +               return setModerationParams(pAC, port, &ecoalesc);
12512 +       }
12513 +#endif
12514 +#ifdef ETHTOOL_GWOL
12515 +       case ETHTOOL_GWOL: {
12516 +               struct ethtool_wolinfo ewol = { ETHTOOL_GWOL };
12517 +               getWOLsettings(pAC, port, &ewol);
12518 +               if(copy_to_user(pAddr, &ewol, sizeof(ewol))) {
12519 +                       return -EFAULT;
12520 +               }
12521 +               return 0;
12522 +       }
12523 +#endif
12524 +#ifdef ETHTOOL_SWOL
12525 +       case ETHTOOL_SWOL: {
12526 +               struct ethtool_wolinfo ewol;
12527 +               if(copy_from_user(&ewol, pAddr, sizeof(ewol))) {
12528 +                       return -EFAULT;
12529 +               }
12530 +               return setWOLsettings(pAC, port, &ewol);
12531 +       }
12532 +#endif
12533 +        default:
12534 +                return -EOPNOTSUPP;
12535 +        }
12536 +} /* SkEthIoctl() */
12537
12538  /******************************************************************************
12539   *
12540 @@ -72,6 +531,7 @@
12541   *
12542   *****************************************************************************/
12543
12544 +#ifdef ETHTOOL_GSET
12545  /*****************************************************************************
12546   *
12547   *     getSettings - retrieves the current settings of the selected adapter
12548 @@ -81,15 +541,15 @@
12549   *     This configuration involves a)speed, b)duplex and c)autoneg plus
12550   *     a number of other variables.
12551   *
12552 - * Returns:    always 0
12553 + * Returns:    N/A
12554   *
12555   */
12556 -static int getSettings(struct net_device *dev, struct ethtool_cmd *ecmd)
12557 +static void getSettings(
12558 +SK_AC              *pAC,  /* pointer to adapter control context      */
12559 +int                 port, /* the port of the selected adapter        */
12560 +struct ethtool_cmd *ecmd) /* mandatory command structure for results */
12561  {
12562 -       const DEV_NET *pNet = netdev_priv(dev);
12563 -       int port = pNet->PortNr;
12564 -       const SK_AC *pAC = pNet->pAC;
12565 -       const SK_GEPORT *pPort = &pAC->GIni.GP[port];
12566 +       SK_GEPORT *pPort = &pAC->GIni.GP[port];
12567
12568         static int DuplexAutoNegConfMap[9][3]= {
12569                 { -1                     , -1         , -1              },
12570 @@ -102,6 +562,7 @@
12571                 { SK_LMODE_AUTOSENSE     , -1         , -1              },
12572                 { SK_LMODE_INDETERMINATED, -1         , -1              }
12573         };
12574 +
12575         static int SpeedConfMap[6][2] = {
12576                 { 0                       , -1         },
12577                 { SK_LSPEED_AUTO          , -1         },
12578 @@ -110,6 +571,7 @@
12579                 { SK_LSPEED_1000MBPS      , SPEED_1000 },
12580                 { SK_LSPEED_INDETERMINATED, -1         }
12581         };
12582 +
12583         static int AdvSpeedMap[6][2] = {
12584                 { 0                       , -1         },
12585                 { SK_LSPEED_AUTO          , -1         },
12586 @@ -137,12 +599,10 @@
12587                         if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {
12588                                 ecmd->supported &= ~(SUPPORTED_1000baseT_Half);
12589                         }
12590 -#ifdef CHIP_ID_YUKON_FE
12591                         if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) {
12592                                 ecmd->supported &= ~(SUPPORTED_1000baseT_Half);
12593                                 ecmd->supported &= ~(SUPPORTED_1000baseT_Full);
12594                         }
12595 -#endif
12596                 }
12597                 if (pAC->GIni.GP[0].PLinkSpeed != SK_LSPEED_AUTO) {
12598                         ecmd->advertising = AdvSpeedMap[pPort->PLinkSpeed][1];
12599 @@ -152,26 +612,20 @@
12600                 } else {
12601                         ecmd->advertising = ecmd->supported;
12602                 }
12603 -
12604 -               if (ecmd->autoneg == AUTONEG_ENABLE)
12605 +               if (ecmd->autoneg == AUTONEG_ENABLE) {
12606                         ecmd->advertising |= ADVERTISED_Autoneg;
12607 +               } else {
12608 +                       ecmd->advertising = ADVERTISED_TP;
12609 +               }
12610         } else {
12611                 ecmd->port        = PORT_FIBRE;
12612 -               ecmd->supported   = SUPP_FIBRE_ALL;
12613 -               ecmd->advertising = ADV_FIBRE_ALL;
12614 +               ecmd->supported   = (SUPP_FIBRE_ALL);
12615 +               ecmd->advertising = (ADV_FIBRE_ALL);
12616         }
12617 -       return 0;
12618 -}
12619 -
12620 -/*
12621 - * MIB infrastructure uses instance value starting at 1
12622 - * based on board and port.
12623 - */
12624 -static inline u32 pnmiInstance(const DEV_NET *pNet)
12625 -{
12626 -       return 1 + (pNet->pAC->RlmtNets == 2) + pNet->PortNr;
12627  }
12628 +#endif
12629
12630 +#ifdef ETHTOOL_SSET
12631  /*****************************************************************************
12632   *
12633   *     setSettings - configures the settings of a selected adapter
12634 @@ -181,422 +635,719 @@
12635   *     c)autonegotiation.
12636   *
12637   * Returns:
12638 - *     0:      everything fine, no error
12639 - *     <0:     the return value is the error code of the failure
12640 + *     ==0:    everything fine, no error
12641 + *     !=0:    the return value is the error code of the failure
12642   */
12643 -static int setSettings(struct net_device *dev, struct ethtool_cmd *ecmd)
12644 +static int setSettings(
12645 +SK_AC              *pAC,  /* pointer to adapter control context    */
12646 +int                 port, /* the port of the selected adapter      */
12647 +struct ethtool_cmd *ecmd) /* command structure containing settings */
12648  {
12649 -       DEV_NET *pNet = netdev_priv(dev);
12650 -       SK_AC *pAC = pNet->pAC;
12651 -       u32 instance;
12652 -       char buf[4];
12653 -       int len = 1;
12654 +       DEV_NET     *pNet  = (DEV_NET *) pAC->dev[port]->priv;
12655 +       SK_U32       Instance;
12656 +       char         Buf[4];
12657 +       unsigned int Len = 1;
12658 +       int Ret;
12659
12660 -       if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100
12661 -           && ecmd->speed != SPEED_1000)
12662 -               return -EINVAL;
12663 -
12664 -       if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
12665 -               return -EINVAL;
12666 +       if (port == 0) {
12667 +               Instance = (pAC->RlmtNets == 2) ? 1 : 2;
12668 +       } else {
12669 +               Instance = (pAC->RlmtNets == 2) ? 2 : 3;
12670 +       }
12671
12672 -       if (ecmd->autoneg != AUTONEG_DISABLE && ecmd->autoneg != AUTONEG_ENABLE)
12673 -               return -EINVAL;
12674 +       if (((ecmd->autoneg == AUTONEG_DISABLE) || (ecmd->autoneg == AUTONEG_ENABLE)) &&
12675 +           ((ecmd->duplex == DUPLEX_FULL) || (ecmd->duplex == DUPLEX_HALF))) {
12676 +               if (ecmd->autoneg == AUTONEG_DISABLE) {
12677 +                       if (ecmd->duplex == DUPLEX_FULL) {
12678 +                               *Buf = (char) SK_LMODE_FULL;
12679 +                       } else {
12680 +                               *Buf = (char) SK_LMODE_HALF;
12681 +                       }
12682 +               } else {
12683 +               /* Autoneg on. Enable autoparam */
12684 +                       *Buf = (char) SK_LMODE_AUTOBOTH;
12685 +               }
12686
12687 -       if (ecmd->autoneg == AUTONEG_DISABLE)
12688 -               *buf = (ecmd->duplex == DUPLEX_FULL)
12689 -                       ? SK_LMODE_FULL : SK_LMODE_HALF;
12690 -       else
12691 -               *buf = (ecmd->duplex == DUPLEX_FULL)
12692 -                       ? SK_LMODE_AUTOFULL : SK_LMODE_AUTOHALF;
12693 -
12694 -       instance = pnmiInstance(pNet);
12695 -       if (SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_LINK_MODE,
12696 -                          &buf, &len, instance, pNet->NetNr) != SK_PNMI_ERR_OK)
12697 -               return -EINVAL;
12698 +               Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_LINK_MODE,
12699 +                                       &Buf, &Len, Instance, pNet->NetNr);
12700
12701 -       switch(ecmd->speed) {
12702 -       case SPEED_1000:
12703 -               *buf = SK_LSPEED_1000MBPS;
12704 -               break;
12705 -       case SPEED_100:
12706 -               *buf = SK_LSPEED_100MBPS;
12707 -               break;
12708 -       case SPEED_10:
12709 -               *buf = SK_LSPEED_10MBPS;
12710 +               if (Ret != SK_PNMI_ERR_OK) {
12711 +                       return -EINVAL;
12712 +               }
12713 +       } else if (ecmd->autoneg == AUTONEG_ENABLE) {
12714 +       /* Set default values */
12715 +               *Buf = (char) SK_LMODE_AUTOBOTH;
12716 +               Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_LINK_MODE,
12717 +                                       &Buf, &Len, Instance, pNet->NetNr);
12718         }
12719
12720 -       if (SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE,
12721 -                        &buf, &len, instance, pNet->NetNr) != SK_PNMI_ERR_OK)
12722 +       if ((ecmd->speed == SPEED_1000) ||
12723 +           (ecmd->speed == SPEED_100)  ||
12724 +           (ecmd->speed == SPEED_10)) {
12725 +               if (ecmd->autoneg == AUTONEG_ENABLE) {
12726 +                       *Buf = (char) SK_LSPEED_AUTO;
12727 +               } else if (ecmd->speed == SPEED_1000) {
12728 +                       *Buf = (char) SK_LSPEED_1000MBPS;
12729 +               } else if (ecmd->speed == SPEED_100) {
12730 +                       *Buf = (char) SK_LSPEED_100MBPS;
12731 +               } else {
12732 +                       *Buf = (char) SK_LSPEED_10MBPS;
12733 +               }
12734 +
12735 +               Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE,
12736 +                                       &Buf, &Len, Instance, pNet->NetNr);
12737 +
12738 +               if (Ret != SK_PNMI_ERR_OK) {
12739 +                       return -EINVAL;
12740 +               }
12741 +       } else if (ecmd->autoneg == AUTONEG_ENABLE) {
12742 +               *Buf = (char) SK_LSPEED_AUTO;
12743 +               Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE,
12744 +                                       &Buf, &Len, Instance, pNet->NetNr);
12745 +       } else {
12746                 return -EINVAL;
12747 +       }
12748
12749         return 0;
12750  }
12751 +#endif
12752
12753 +#ifdef ETHTOOL_GPAUSEPARAM
12754  /*****************************************************************************
12755   *
12756 - *     getDriverInfo - returns generic driver and adapter information
12757 + *     getPauseParams - retrieves the pause parameters
12758   *
12759   * Description:
12760 - *     Generic driver information is returned via this function, such as
12761 - *     the name of the driver, its version and and firmware version.
12762 - *     In addition to this, the location of the selected adapter is
12763 - *     returned as a bus info string (e.g. '01:05.0').
12764 - *
12765 + *     All current pause parameters of a selected adapter are placed
12766 + *     in the passed ethtool_pauseparam structure and are returned.
12767 + *
12768   * Returns:    N/A
12769   *
12770   */
12771 -static void getDriverInfo(struct net_device *dev, struct ethtool_drvinfo *info)
12772 +static void getPauseParams(
12773 +SK_AC                     *pAC,    /* pointer to adapter control context */
12774 +int                        port,   /* the port of the selected adapter   */
12775 +struct ethtool_pauseparam *epause) /* pause parameter struct for result  */
12776  {
12777 -       const DEV_NET   *pNet = netdev_priv(dev);
12778 -       const SK_AC *pAC = pNet->pAC;
12779 -       char vers[32];
12780 -
12781 -       snprintf(vers, sizeof(vers)-1, VER_STRING "(v%d.%d)",
12782 -               (pAC->GIni.GIPciHwRev >> 4) & 0xf, pAC->GIni.GIPciHwRev & 0xf);
12783 -
12784 -       strlcpy(info->driver, DRIVER_FILE_NAME, sizeof(info->driver));
12785 -       strcpy(info->version, vers);
12786 -       strcpy(info->fw_version, "N/A");
12787 -       strlcpy(info->bus_info, pci_name(pAC->PciDev), ETHTOOL_BUSINFO_LEN);
12788 -}
12789 -
12790 -/*
12791 - * Ethtool statistics support.
12792 - */
12793 -static const char StringsStats[][ETH_GSTRING_LEN] = {
12794 -       "rx_packets",   "tx_packets",
12795 -       "rx_bytes",     "tx_bytes",
12796 -       "rx_errors",    "tx_errors",
12797 -       "rx_dropped",   "tx_dropped",
12798 -       "multicasts",   "collisions",
12799 -       "rx_length_errors",             "rx_buffer_overflow_errors",
12800 -       "rx_crc_errors",                "rx_frame_errors",
12801 -       "rx_too_short_errors",          "rx_too_long_errors",
12802 -       "rx_carrier_extension_errors",  "rx_symbol_errors",
12803 -       "rx_llc_mac_size_errors",       "rx_carrier_errors",
12804 -       "rx_jabber_errors",             "rx_missed_errors",
12805 -       "tx_abort_collision_errors",    "tx_carrier_errors",
12806 -       "tx_buffer_underrun_errors",    "tx_heartbeat_errors",
12807 -       "tx_window_errors",
12808 -};
12809 +       SK_GEPORT *pPort            = &pAC->GIni.GP[port];
12810
12811 -static int getStatsCount(struct net_device *dev)
12812 -{
12813 -       return ARRAY_SIZE(StringsStats);
12814 -}
12815 +       epause->rx_pause = 0;
12816 +       epause->tx_pause = 0;
12817
12818 -static void getStrings(struct net_device *dev, u32 stringset, u8 *data)
12819 -{
12820 -       switch(stringset) {
12821 -       case ETH_SS_STATS:
12822 -               memcpy(data, *StringsStats, sizeof(StringsStats));
12823 -               break;
12824 +       if (pPort->PFlowCtrlMode == SK_FLOW_MODE_LOC_SEND) {
12825 +               epause->tx_pause = 1;
12826 +       }
12827 +       if ((pPort->PFlowCtrlMode == SK_FLOW_MODE_SYMMETRIC) ||
12828 +           (pPort->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM)) {
12829 +               epause->tx_pause = 1;
12830 +               epause->rx_pause = 1;
12831         }
12832 -}
12833
12834 -static void getEthtoolStats(struct net_device *dev,
12835 -                           struct ethtool_stats *stats, u64 *data)
12836 -{
12837 -       const DEV_NET   *pNet = netdev_priv(dev);
12838 -       const SK_AC *pAC = pNet->pAC;
12839 -       const SK_PNMI_STRUCT_DATA *pPnmiStruct = &pAC->PnmiStruct;
12840 -
12841 -       *data++ = pPnmiStruct->Stat[0].StatRxOkCts;
12842 -       *data++ = pPnmiStruct->Stat[0].StatTxOkCts;
12843 -       *data++ = pPnmiStruct->Stat[0].StatRxOctetsOkCts;
12844 -       *data++ = pPnmiStruct->Stat[0].StatTxOctetsOkCts;
12845 -       *data++ = pPnmiStruct->InErrorsCts;
12846 -       *data++ = pPnmiStruct->Stat[0].StatTxSingleCollisionCts;
12847 -       *data++ = pPnmiStruct->RxNoBufCts;
12848 -       *data++ = pPnmiStruct->TxNoBufCts;
12849 -       *data++ = pPnmiStruct->Stat[0].StatRxMulticastOkCts;
12850 -       *data++ = pPnmiStruct->Stat[0].StatTxSingleCollisionCts;
12851 -       *data++ = pPnmiStruct->Stat[0].StatRxRuntCts;
12852 -       *data++ = pPnmiStruct->Stat[0].StatRxFifoOverflowCts;
12853 -       *data++ = pPnmiStruct->Stat[0].StatRxFcsCts;
12854 -       *data++ = pPnmiStruct->Stat[0].StatRxFramingCts;
12855 -       *data++ = pPnmiStruct->Stat[0].StatRxShortsCts;
12856 -       *data++ = pPnmiStruct->Stat[0].StatRxTooLongCts;
12857 -       *data++ = pPnmiStruct->Stat[0].StatRxCextCts;
12858 -       *data++ = pPnmiStruct->Stat[0].StatRxSymbolCts;
12859 -       *data++ = pPnmiStruct->Stat[0].StatRxIRLengthCts;
12860 -       *data++ = pPnmiStruct->Stat[0].StatRxCarrierCts;
12861 -       *data++ = pPnmiStruct->Stat[0].StatRxJabberCts;
12862 -       *data++ = pPnmiStruct->Stat[0].StatRxMissedCts;
12863 -       *data++ = pAC->stats.tx_aborted_errors;
12864 -       *data++ = pPnmiStruct->Stat[0].StatTxCarrierCts;
12865 -       *data++ = pPnmiStruct->Stat[0].StatTxFifoUnderrunCts;
12866 -       *data++ = pPnmiStruct->Stat[0].StatTxCarrierCts;
12867 -       *data++ = pAC->stats.tx_window_errors;
12868 +       if ((epause->rx_pause == 0) && (epause->tx_pause == 0)) {
12869 +               epause->autoneg = SK_FALSE;
12870 +       } else {
12871 +               epause->autoneg = SK_TRUE;
12872 +       }
12873  }
12874 +#endif
12875
12876 -
12877 +#ifdef ETHTOOL_SPAUSEPARAM
12878  /*****************************************************************************
12879   *
12880 - *     toggleLeds - Changes the LED state of an adapter
12881 + *     setPauseParams - configures the pause parameters of an adapter
12882   *
12883   * Description:
12884 - *     This function changes the current state of all LEDs of an adapter so
12885 - *     that it can be located by a user.
12886 - *
12887 - * Returns:    N/A
12888 + *     This function sets the Rx or Tx pause parameters
12889   *
12890 + * Returns:
12891 + *     ==0:    everything fine, no error
12892 + *     !=0:    the return value is the error code of the failure
12893   */
12894 -static void toggleLeds(DEV_NET *pNet, int on)
12895 +static int setPauseParams(
12896 +SK_AC                     *pAC,    /* pointer to adapter control context */
12897 +int                        port,   /* the port of the selected adapter   */
12898 +struct ethtool_pauseparam *epause) /* pause parameter struct with params */
12899  {
12900 -       SK_AC *pAC = pNet->pAC;
12901 -       int port = pNet->PortNr;
12902 -       void __iomem *io = pAC->IoBase;
12903 -
12904 -       if (pAC->GIni.GIGenesis) {
12905 -               SK_OUT8(io, MR_ADDR(port,LNK_LED_REG),
12906 -                       on ? SK_LNK_ON : SK_LNK_OFF);
12907 -               SkGeYellowLED(pAC, io,
12908 -                             on ? (LED_ON >> 1) : (LED_OFF >> 1));
12909 -               SkGeXmitLED(pAC, io, MR_ADDR(port,RX_LED_INI),
12910 -                           on ? SK_LED_TST : SK_LED_DIS);
12911 -
12912 -               if (pAC->GIni.GP[port].PhyType == SK_PHY_BCOM)
12913 -                       SkXmPhyWrite(pAC, io, port, PHY_BCOM_P_EXT_CTRL,
12914 -                                    on ? PHY_B_PEC_LED_ON : PHY_B_PEC_LED_OFF);
12915 -               else if (pAC->GIni.GP[port].PhyType == SK_PHY_LONE)
12916 -                       SkXmPhyWrite(pAC, io, port, PHY_LONE_LED_CFG,
12917 -                                    on ? 0x0800 : PHY_L_LC_LEDT);
12918 -               else
12919 -                       SkGeXmitLED(pAC, io, MR_ADDR(port,TX_LED_INI),
12920 -                                   on ? SK_LED_TST : SK_LED_DIS);
12921 +       SK_GEPORT *pPort            = &pAC->GIni.GP[port];
12922 +       DEV_NET   *pNet             = (DEV_NET *) pAC->dev[port]->priv;
12923 +       int        PrevSpeedVal     = pPort->PLinkSpeedUsed;
12924 +
12925 +       SK_U32         Instance;
12926 +       char           Buf[4];
12927 +       int            Ret;
12928 +       SK_BOOL        prevAutonegValue = SK_TRUE;
12929 +       int            prevTxPause      = 0;
12930 +       int            prevRxPause      = 0;
12931 +       unsigned int   Len              = 1;
12932 +
12933 +        if (port == 0) {
12934 +                Instance = (pAC->RlmtNets == 2) ? 1 : 2;
12935 +        } else {
12936 +                Instance = (pAC->RlmtNets == 2) ? 2 : 3;
12937 +        }
12938 +
12939 +       /*
12940 +       ** we have to determine the current settings to see if
12941 +       ** the operator requested any modification of the flow
12942 +       ** control parameters...
12943 +       */
12944 +       if (pPort->PFlowCtrlMode == SK_FLOW_MODE_LOC_SEND) {
12945 +               prevTxPause = 1;
12946 +       }
12947 +       if ((pPort->PFlowCtrlMode == SK_FLOW_MODE_SYMMETRIC) ||
12948 +           (pPort->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM)) {
12949 +               prevTxPause = 1;
12950 +               prevRxPause = 1;
12951 +       }
12952 +
12953 +       if ((prevRxPause == 0) && (prevTxPause == 0)) {
12954 +               prevAutonegValue = SK_FALSE;
12955 +       }
12956 +
12957 +
12958 +       /*
12959 +       ** perform modifications regarding the changes
12960 +       ** requested by the operator
12961 +       */
12962 +       if (epause->autoneg != prevAutonegValue) {
12963 +               if (epause->autoneg == AUTONEG_DISABLE) {
12964 +                       *Buf = (char) SK_FLOW_MODE_NONE;
12965 +               } else {
12966 +                       *Buf = (char) SK_FLOW_MODE_SYMMETRIC;
12967 +               }
12968         } else {
12969 -               const u16 YukLedOn = (PHY_M_LED_MO_DUP(MO_LED_ON)  |
12970 -                                     PHY_M_LED_MO_10(MO_LED_ON)   |
12971 -                                     PHY_M_LED_MO_100(MO_LED_ON)  |
12972 -                                     PHY_M_LED_MO_1000(MO_LED_ON) |
12973 -                                     PHY_M_LED_MO_RX(MO_LED_ON));
12974 -               const u16  YukLedOff = (PHY_M_LED_MO_DUP(MO_LED_OFF)  |
12975 -                                       PHY_M_LED_MO_10(MO_LED_OFF)   |
12976 -                                       PHY_M_LED_MO_100(MO_LED_OFF)  |
12977 -                                       PHY_M_LED_MO_1000(MO_LED_OFF) |
12978 -                                       PHY_M_LED_MO_RX(MO_LED_OFF));
12979 -
12980 +               if(epause->rx_pause && epause->tx_pause) {
12981 +                       *Buf = (char) SK_FLOW_MODE_SYMMETRIC;
12982 +               } else if (epause->rx_pause && !epause->tx_pause) {
12983 +                       *Buf = (char) SK_FLOW_MODE_SYM_OR_REM;
12984 +               } else if(!epause->rx_pause && epause->tx_pause) {
12985 +                       *Buf = (char) SK_FLOW_MODE_LOC_SEND;
12986 +               } else {
12987 +                       *Buf = (char) SK_FLOW_MODE_NONE;
12988 +               }
12989 +       }
12990 +
12991 +       Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_FLOWCTRL_MODE,
12992 +                       &Buf, &Len, Instance, pNet->NetNr);
12993 +
12994 +       if (Ret != SK_PNMI_ERR_OK) {
12995 +               SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_CTRL,
12996 +               ("ethtool (sk98lin): error changing rx/tx pause (%i)\n", Ret));
12997 +       }  else {
12998 +               Len = 1; /* set buffer length to correct value */
12999 +       }
13000 +
13001 +       /*
13002 +       ** It may be that autoneg has been disabled! Therefore
13003 +       ** set the speed to the previously used value...
13004 +       */
13005 +       *Buf = (char) PrevSpeedVal;
13006 +
13007 +       Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE,
13008 +                       &Buf, &Len, Instance, pNet->NetNr);
13009
13010 -               SkGmPhyWrite(pAC,io,port,PHY_MARV_LED_CTRL,0);
13011 -               SkGmPhyWrite(pAC,io,port,PHY_MARV_LED_OVER,
13012 -                            on ? YukLedOn : YukLedOff);
13013 +       if (Ret != SK_PNMI_ERR_OK) {
13014 +               SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_CTRL,
13015 +               ("ethtool (sk98lin): error setting speed (%i)\n", Ret));
13016         }
13017 +        return 0;
13018  }
13019 +#endif
13020
13021 +#ifdef ETHTOOL_GCOALESCE
13022  /*****************************************************************************
13023   *
13024 - *     skGeBlinkTimer - Changes the LED state of an adapter
13025 + *     getModerationParams - retrieves the IRQ moderation settings
13026   *
13027   * Description:
13028 - *     This function changes the current state of all LEDs of an adapter so
13029 - *     that it can be located by a user. If the requested time interval for
13030 - *     this test has elapsed, this function cleans up everything that was
13031 - *     temporarily setup during the locate NIC test. This involves of course
13032 - *     also closing or opening any adapter so that the initial board state
13033 - *     is recovered.
13034 + *     All current IRQ moderation settings of a selected adapter are placed
13035 + *     in the passed ethtool_coalesce structure and are returned.
13036   *
13037   * Returns:    N/A
13038   *
13039   */
13040 -void SkGeBlinkTimer(unsigned long data)
13041 +static void getModerationParams(
13042 +SK_AC                   *pAC,      /* pointer to adapter control context */
13043 +int                      port,     /* the port of the selected adapter   */
13044 +struct ethtool_coalesce *ecoalesc) /* IRQ moderation struct for results  */
13045  {
13046 -       struct net_device *dev = (struct net_device *) data;
13047 -       DEV_NET *pNet = netdev_priv(dev);
13048 -       SK_AC *pAC = pNet->pAC;
13049 -
13050 -       toggleLeds(pNet, pAC->LedsOn);
13051 +       DIM_INFO *Info = &pAC->DynIrqModInfo;
13052 +       SK_BOOL UseTxIrqModeration = SK_FALSE;
13053 +       SK_BOOL UseRxIrqModeration = SK_FALSE;
13054 +
13055 +       if (Info->IntModTypeSelect != C_INT_MOD_NONE) {
13056 +               if (CHIP_ID_YUKON_2(pAC)) {
13057 +                       UseRxIrqModeration = SK_TRUE;
13058 +                       UseTxIrqModeration = SK_TRUE;
13059 +               } else {
13060 +                       if ((Info->MaskIrqModeration == IRQ_MASK_RX_ONLY) ||
13061 +                           (Info->MaskIrqModeration == IRQ_MASK_SP_RX)   ||
13062 +                           (Info->MaskIrqModeration == IRQ_MASK_RX_TX_SP)) {
13063 +                               UseRxIrqModeration = SK_TRUE;
13064 +                       }
13065 +                       if ((Info->MaskIrqModeration == IRQ_MASK_TX_ONLY) ||
13066 +                           (Info->MaskIrqModeration == IRQ_MASK_SP_TX)   ||
13067 +                           (Info->MaskIrqModeration == IRQ_MASK_RX_TX_SP)) {
13068 +                               UseTxIrqModeration = SK_TRUE;
13069 +                       }
13070 +               }
13071
13072 -       pAC->LedsOn = !pAC->LedsOn;
13073 -       mod_timer(&pAC->BlinkTimer, jiffies + HZ/4);
13074 +               if (UseRxIrqModeration) {
13075 +                       ecoalesc->rx_coalesce_usecs = 1000000 / Info->MaxModIntsPerSec;
13076 +               }
13077 +               if (UseTxIrqModeration) {
13078 +                       ecoalesc->tx_coalesce_usecs = 1000000 / Info->MaxModIntsPerSec;
13079 +               }
13080 +               if (Info->IntModTypeSelect == C_INT_MOD_DYNAMIC) {
13081 +                       ecoalesc->rate_sample_interval = Info->DynIrqModSampleInterval;
13082 +                       if (UseRxIrqModeration) {
13083 +                               ecoalesc->use_adaptive_rx_coalesce = 1;
13084 +                               ecoalesc->rx_coalesce_usecs_low =
13085 +                                       1000000 / Info->MaxModIntsPerSecLowerLimit;
13086 +                               ecoalesc->rx_coalesce_usecs_high =
13087 +                                       1000000 / Info->MaxModIntsPerSecUpperLimit;
13088 +                       }
13089 +                       if (UseTxIrqModeration) {
13090 +                               ecoalesc->use_adaptive_tx_coalesce = 1;
13091 +                               ecoalesc->tx_coalesce_usecs_low =
13092 +                                       1000000 / Info->MaxModIntsPerSecLowerLimit;
13093 +                               ecoalesc->tx_coalesce_usecs_high =
13094 +                                       1000000 / Info->MaxModIntsPerSecUpperLimit;
13095 +                       }
13096 +               }
13097 +       }
13098  }
13099 +#endif
13100
13101 +#ifdef ETHTOOL_SCOALESCE
13102  /*****************************************************************************
13103   *
13104 - *     locateDevice - start the locate NIC feature of the elected adapter
13105 + *     setModerationParams - configures the IRQ moderation of an adapter
13106   *
13107   * Description:
13108 - *     This function is used if the user want to locate a particular NIC.
13109 - *     All LEDs are regularly switched on and off, so the NIC can easily
13110 - *     be identified.
13111 + *     Depending on the desired IRQ moderation parameters, either a) static,
13112 + *     b) dynamic or c) no moderation is configured.
13113   *
13114 - * Returns:
13115 - *     ==0:    everything fine, no error, locateNIC test was started
13116 - *     !=0:    one locateNIC test runs already
13117 + * Returns:
13118 + *     ==0:    everything fine, no error
13119 + *     !=0:    the return value is the error code of the failure
13120   *
13121 + * Notes:
13122 + *     The supported timeframe for the coalesced interrupts ranges from
13123 + *     33.333us (30 IntsPerSec) down to 25us (40.000 IntsPerSec).
13124 + *     Any requested value that is not in this range will abort the request!
13125   */
13126 -static int locateDevice(struct net_device *dev, u32 data)
13127 +static int setModerationParams(
13128 +SK_AC                   *pAC,      /* pointer to adapter control context */
13129 +int                      port,     /* the port of the selected adapter   */
13130 +struct ethtool_coalesce *ecoalesc) /* IRQ moderation struct with params  */
13131  {
13132 -       DEV_NET *pNet = netdev_priv(dev);
13133 -       SK_AC *pAC = pNet->pAC;
13134 +       DIM_INFO  *Info             = &pAC->DynIrqModInfo;
13135 +       int        PrevModeration   = Info->IntModTypeSelect;
13136
13137 -       if(!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
13138 -               data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
13139 +       Info->IntModTypeSelect = C_INT_MOD_NONE; /* initial default */
13140
13141 -       /* start blinking */
13142 -       pAC->LedsOn = 0;
13143 -       mod_timer(&pAC->BlinkTimer, jiffies);
13144 -       msleep_interruptible(data * 1000);
13145 -       del_timer_sync(&pAC->BlinkTimer);
13146 -       toggleLeds(pNet, 0);
13147 +       if ((ecoalesc->rx_coalesce_usecs) || (ecoalesc->tx_coalesce_usecs)) {
13148 +               if (ecoalesc->rx_coalesce_usecs) {
13149 +                       if ((ecoalesc->rx_coalesce_usecs < 25) ||
13150 +                           (ecoalesc->rx_coalesce_usecs > 33333)) {
13151 +                               return -EINVAL;
13152 +                       }
13153 +               }
13154 +               if (ecoalesc->tx_coalesce_usecs) {
13155 +                       if ((ecoalesc->tx_coalesce_usecs < 25) ||
13156 +                           (ecoalesc->tx_coalesce_usecs > 33333)) {
13157 +                               return -EINVAL;
13158 +                       }
13159 +               }
13160 +               if (!CHIP_ID_YUKON_2(pAC)) {
13161 +                       if ((Info->MaskIrqModeration == IRQ_MASK_SP_RX) ||
13162 +                           (Info->MaskIrqModeration == IRQ_MASK_SP_TX) ||
13163 +                           (Info->MaskIrqModeration == IRQ_MASK_RX_TX_SP)) {
13164 +                               Info->MaskIrqModeration = IRQ_MASK_SP_ONLY;
13165 +                       }
13166 +               }
13167 +               Info->IntModTypeSelect = C_INT_MOD_STATIC;
13168 +               if (ecoalesc->rx_coalesce_usecs) {
13169 +                       Info->MaxModIntsPerSec =
13170 +                               1000000 / ecoalesc->rx_coalesce_usecs;
13171 +                       if (!CHIP_ID_YUKON_2(pAC)) {
13172 +                               if (Info->MaskIrqModeration == IRQ_MASK_TX_ONLY) {
13173 +                                       Info->MaskIrqModeration = IRQ_MASK_TX_RX;
13174 +                               }
13175 +                               if (Info->MaskIrqModeration == IRQ_MASK_SP_ONLY) {
13176 +                                       Info->MaskIrqModeration = IRQ_MASK_SP_RX;
13177 +                               }
13178 +                               if (Info->MaskIrqModeration == IRQ_MASK_SP_TX) {
13179 +                                       Info->MaskIrqModeration = IRQ_MASK_RX_TX_SP;
13180 +                               }
13181 +                       } else {
13182 +                               Info->MaskIrqModeration = Y2_IRQ_MASK;
13183 +                       }
13184 +               }
13185 +               if (ecoalesc->tx_coalesce_usecs) {
13186 +                       Info->MaxModIntsPerSec =
13187 +                               1000000 / ecoalesc->tx_coalesce_usecs;
13188 +                       if (!CHIP_ID_YUKON_2(pAC)) {
13189 +                               if (Info->MaskIrqModeration == IRQ_MASK_RX_ONLY) {
13190 +                                       Info->MaskIrqModeration = IRQ_MASK_TX_RX;
13191 +                               }
13192 +                               if (Info->MaskIrqModeration == IRQ_MASK_SP_ONLY) {
13193 +                                       Info->MaskIrqModeration = IRQ_MASK_SP_TX;
13194 +                               }
13195 +                               if (Info->MaskIrqModeration == IRQ_MASK_SP_RX) {
13196 +                                       Info->MaskIrqModeration = IRQ_MASK_RX_TX_SP;
13197 +                               }
13198 +                       } else {
13199 +                               Info->MaskIrqModeration = Y2_IRQ_MASK;
13200 +                       }
13201 +               }
13202 +       }
13203 +       if ((ecoalesc->rate_sample_interval)  ||
13204 +           (ecoalesc->rx_coalesce_usecs_low) ||
13205 +           (ecoalesc->tx_coalesce_usecs_low) ||
13206 +           (ecoalesc->rx_coalesce_usecs_high)||
13207 +           (ecoalesc->tx_coalesce_usecs_high)) {
13208 +               if (ecoalesc->rate_sample_interval) {
13209 +                       if ((ecoalesc->rate_sample_interval < 1) ||
13210 +                           (ecoalesc->rate_sample_interval > 10)) {
13211 +                               return -EINVAL;
13212 +                       }
13213 +               }
13214 +               if (ecoalesc->rx_coalesce_usecs_low) {
13215 +                       if ((ecoalesc->rx_coalesce_usecs_low < 25) ||
13216 +                           (ecoalesc->rx_coalesce_usecs_low > 33333)) {
13217 +                               return -EINVAL;
13218 +                       }
13219 +               }
13220 +               if (ecoalesc->rx_coalesce_usecs_high) {
13221 +                       if ((ecoalesc->rx_coalesce_usecs_high < 25) ||
13222 +                           (ecoalesc->rx_coalesce_usecs_high > 33333)) {
13223 +                               return -EINVAL;
13224 +                       }
13225 +               }
13226 +               if (ecoalesc->tx_coalesce_usecs_low) {
13227 +                       if ((ecoalesc->tx_coalesce_usecs_low < 25) ||
13228 +                           (ecoalesc->tx_coalesce_usecs_low > 33333)) {
13229 +                               return -EINVAL;
13230 +                       }
13231 +               }
13232 +               if (ecoalesc->tx_coalesce_usecs_high) {
13233 +                       if ((ecoalesc->tx_coalesce_usecs_high < 25) ||
13234 +                           (ecoalesc->tx_coalesce_usecs_high > 33333)) {
13235 +                               return -EINVAL;
13236 +                       }
13237 +               }
13238
13239 -       return 0;
13240 +               Info->IntModTypeSelect = C_INT_MOD_DYNAMIC;
13241 +               if (ecoalesc->rate_sample_interval) {
13242 +                       Info->DynIrqModSampleInterval =
13243 +                               ecoalesc->rate_sample_interval;
13244 +               }
13245 +               if (ecoalesc->rx_coalesce_usecs_low) {
13246 +                       Info->MaxModIntsPerSecLowerLimit =
13247 +                               1000000 / ecoalesc->rx_coalesce_usecs_low;
13248 +               }
13249 +               if (ecoalesc->tx_coalesce_usecs_low) {
13250 +                       Info->MaxModIntsPerSecLowerLimit =
13251 +                               1000000 / ecoalesc->tx_coalesce_usecs_low;
13252 +               }
13253 +               if (ecoalesc->rx_coalesce_usecs_high) {
13254 +                       Info->MaxModIntsPerSecUpperLimit =
13255 +                               1000000 / ecoalesc->rx_coalesce_usecs_high;
13256 +               }
13257 +               if (ecoalesc->tx_coalesce_usecs_high) {
13258 +                       Info->MaxModIntsPerSecUpperLimit =
13259 +                               1000000 / ecoalesc->tx_coalesce_usecs_high;
13260 +               }
13261 +       }
13262 +
13263 +       if ((PrevModeration         == C_INT_MOD_NONE) &&
13264 +           (Info->IntModTypeSelect != C_INT_MOD_NONE)) {
13265 +               SkDimEnableModerationIfNeeded(pAC);
13266 +       }
13267 +       if (PrevModeration != C_INT_MOD_NONE) {
13268 +               SkDimDisableModeration(pAC, PrevModeration);
13269 +               if (Info->IntModTypeSelect != C_INT_MOD_NONE) {
13270 +                       SkDimEnableModerationIfNeeded(pAC);
13271 +               }
13272 +       }
13273 +
13274 +        return 0;
13275  }
13276 +#endif
13277
13278 +#ifdef ETHTOOL_GWOL
13279  /*****************************************************************************
13280   *
13281 - *     getPauseParams - retrieves the pause parameters
13282 + *     getWOLsettings - retrieves the WOL settings of the selected adapter
13283   *
13284   * Description:
13285 - *     All current pause parameters of a selected adapter are placed
13286 - *     in the passed ethtool_pauseparam structure and are returned.
13287 + *     All current WOL settings of a selected adapter are placed in the
13288 + *     passed ethtool_wolinfo structure and are returned to the caller.
13289   *
13290   * Returns:    N/A
13291   *
13292   */
13293 -static void getPauseParams(struct net_device *dev, struct ethtool_pauseparam *epause)
13294 +static void getWOLsettings(
13295 +SK_AC                  *pAC,  /* pointer to adapter control context  */
13296 +int                     port, /* the port of the selected adapter    */
13297 +struct ethtool_wolinfo *ewol) /* mandatory WOL structure for results */
13298  {
13299 -       DEV_NET *pNet = netdev_priv(dev);
13300 -       SK_AC *pAC = pNet->pAC;
13301 -       SK_GEPORT *pPort = &pAC->GIni.GP[pNet->PortNr];
13302 +       ewol->supported = pAC->WolInfo.SupportedWolOptions;
13303 +       ewol->wolopts   = pAC->WolInfo.ConfiguredWolOptions;
13304
13305 -       epause->rx_pause = (pPort->PFlowCtrlMode == SK_FLOW_MODE_SYMMETRIC) ||
13306 -                 (pPort->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM);
13307 -
13308 -       epause->tx_pause = epause->rx_pause || (pPort->PFlowCtrlMode == SK_FLOW_MODE_LOC_SEND);
13309 -       epause->autoneg = epause->rx_pause || epause->tx_pause;
13310 +       return;
13311  }
13312 +#endif
13313
13314 +#ifdef ETHTOOL_SWOL
13315  /*****************************************************************************
13316   *
13317 - *     setPauseParams - configures the pause parameters of an adapter
13318 + *     setWOLsettings - configures the WOL settings of a selected adapter
13319   *
13320   * Description:
13321 - *     This function sets the Rx or Tx pause parameters
13322 + *     The WOL settings of a selected adapter are configured regarding
13323 + *     the parameters in the passed ethtool_wolinfo structure.
13324 + *     Note that currently only wake on magic packet is supported!
13325   *
13326   * Returns:
13327   *     ==0:    everything fine, no error
13328   *     !=0:    the return value is the error code of the failure
13329   */
13330 -static int setPauseParams(struct net_device *dev , struct ethtool_pauseparam *epause)
13331 +static int setWOLsettings(
13332 +SK_AC                  *pAC,  /* pointer to adapter control context */
13333 +int                     port, /* the port of the selected adapter   */
13334 +struct ethtool_wolinfo *ewol) /* WOL structure containing settings  */
13335  {
13336 -       DEV_NET *pNet = netdev_priv(dev);
13337 -       SK_AC *pAC = pNet->pAC;
13338 -       SK_GEPORT *pPort = &pAC->GIni.GP[pNet->PortNr];
13339 -       u32     instance = pnmiInstance(pNet);
13340 -       struct ethtool_pauseparam old;
13341 -       u8      oldspeed = pPort->PLinkSpeedUsed;
13342 -       char    buf[4];
13343 -       int     len = 1;
13344 -       int ret;
13345 +       if (((ewol->wolopts & WAKE_MAGIC) == WAKE_MAGIC) || (ewol->wolopts == 0)) {
13346 +               pAC->WolInfo.ConfiguredWolOptions = ewol->wolopts;
13347 +               return 0;
13348 +       }
13349 +       return -EFAULT;
13350 +}
13351 +#endif
13352
13353 -       /*
13354 -       ** we have to determine the current settings to see if
13355 -       ** the operator requested any modification of the flow
13356 -       ** control parameters...
13357 -       */
13358 -       getPauseParams(dev, &old);
13359 +#ifdef ETHTOOL_GDRVINFO
13360 +/*****************************************************************************
13361 + *
13362 + *     getDriverInfo - returns generic driver and adapter information
13363 + *
13364 + * Description:
13365 + *     Generic driver information is returned via this function, such as
13366 + *     the name of the driver, its version and and firmware version.
13367 + *     In addition to this, the location of the selected adapter is
13368 + *     returned as a bus info string (e.g. '01:05.0').
13369 + *
13370 + * Returns:    N/A
13371 + *
13372 + */
13373 +static void getDriverInfo(
13374 +SK_AC                  *pAC,      /* pointer to adapter control context   */
13375 +int                     port,     /* the port of the selected adapter     */
13376 +struct ethtool_drvinfo *edrvinfo) /* mandatory info structure for results */
13377 +{
13378 +       char versionString[32];
13379
13380 -       /*
13381 -       ** perform modifications regarding the changes
13382 -       ** requested by the operator
13383 -       */
13384 -       if (epause->autoneg != old.autoneg)
13385 -               *buf = epause->autoneg ? SK_FLOW_MODE_NONE : SK_FLOW_MODE_SYMMETRIC;
13386 -       else {
13387 -               if (epause->rx_pause && epause->tx_pause)
13388 -                       *buf = SK_FLOW_MODE_SYMMETRIC;
13389 -               else if (epause->rx_pause && !epause->tx_pause)
13390 -                       *buf =  SK_FLOW_MODE_SYM_OR_REM;
13391 -               else if (!epause->rx_pause && epause->tx_pause)
13392 -                       *buf =  SK_FLOW_MODE_LOC_SEND;
13393 -               else
13394 -                       *buf = SK_FLOW_MODE_NONE;
13395 +       snprintf(versionString, 32, "%s (%s)", VER_STRING, PATCHLEVEL);
13396 +       strncpy(edrvinfo->driver, DRIVER_FILE_NAME , 32);
13397 +       strncpy(edrvinfo->version, versionString , 32);
13398 +       strncpy(edrvinfo->fw_version, "N/A", 32);
13399 +       strncpy(edrvinfo->bus_info, pci_name(pAC->PciDev), 32);
13400 +
13401 +#ifdef  ETHTOOL_GSTATS
13402 +       edrvinfo->n_stats = SK98LIN_STATS_LEN;
13403 +#endif
13404 +}
13405 +#endif
13406 +
13407 +#ifdef ETHTOOL_PHYS_ID
13408 +/*****************************************************************************
13409 + *
13410 + *     startLocateNIC - start the locate NIC feature of the elected adapter
13411 + *
13412 + * Description:
13413 + *     This function is used if the user want to locate a particular NIC.
13414 + *     All LEDs are regularly switched on and off, so the NIC can easily
13415 + *     be identified.
13416 + *
13417 + * Returns:
13418 + *     ==0:    everything fine, no error, locateNIC test was started
13419 + *     !=0:    one locateNIC test runs already
13420 + *
13421 + */
13422 +static int startLocateNIC(
13423 +SK_AC                *pAC,        /* pointer to adapter control context        */
13424 +int                   port,       /* the port of the selected adapter          */
13425 +struct ethtool_value *blinkSecs)  /* how long the LEDs should blink in seconds */
13426 +{
13427 +       struct SK_NET_DEVICE *pDev      = pAC->dev[port];
13428 +       int                   OtherPort = (port) ? 0 : 1;
13429 +       struct SK_NET_DEVICE *pOtherDev = pAC->dev[OtherPort];
13430 +
13431 +       if (isLocateNICrunning) {
13432 +               return -EFAULT;
13433         }
13434 +       isLocateNICrunning = SK_TRUE;
13435 +       currentPortIndex = port;
13436 +       isDualNetCard = (pDev != pOtherDev) ? SK_TRUE : SK_FALSE;
13437
13438 -       ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_FLOWCTRL_MODE,
13439 -                        &buf, &len, instance, pNet->NetNr);
13440 +       if (netif_running(pAC->dev[port])) {
13441 +               boardWasDown[0] = SK_FALSE;
13442 +       } else {
13443 +               (*pDev->open)(pDev);
13444 +               boardWasDown[0] = SK_TRUE;
13445 +       }
13446
13447 -       if (ret != SK_PNMI_ERR_OK) {
13448 -               SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_CTRL,
13449 -                          ("ethtool (sk98lin): error changing rx/tx pause (%i)\n", ret));
13450 -               goto err;
13451 +       if (isDualNetCard) {
13452 +               if (netif_running(pAC->dev[OtherPort])) {
13453 +                       boardWasDown[1] = SK_FALSE;
13454 +               } else {
13455 +                       (*pOtherDev->open)(pOtherDev);
13456 +                       boardWasDown[1] = SK_TRUE;
13457 +               }
13458         }
13459
13460 -       /*
13461 -       ** It may be that autoneg has been disabled! Therefore
13462 -       ** set the speed to the previously used value...
13463 -       */
13464 -       if (!epause->autoneg) {
13465 -               len = 1;
13466 -               ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE,
13467 -                                  &oldspeed, &len, instance, pNet->NetNr);
13468 -               if (ret != SK_PNMI_ERR_OK)
13469 -                       SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_CTRL,
13470 -                                  ("ethtool (sk98lin): error setting speed (%i)\n", ret));
13471 +       if ((blinkSecs->data < 1) || (blinkSecs->data > 30)) {
13472 +               blinkSecs->data = 3; /* three seconds default */
13473         }
13474 - err:
13475 -        return ret ? -EIO : 0;
13476 -}
13477 +       nbrBlinkQuarterSeconds = 4*blinkSecs->data;
13478
13479 -/* Only Yukon supports checksum offload. */
13480 -static int setScatterGather(struct net_device *dev, u32 data)
13481 -{
13482 -       DEV_NET *pNet = netdev_priv(dev);
13483 -       SK_AC *pAC = pNet->pAC;
13484 +       init_timer(&locateNICtimer);
13485 +       locateNICtimer.function = toggleLeds;
13486 +       locateNICtimer.data     = (unsigned long) pAC;
13487 +       locateNICtimer.expires  = jiffies + HZ; /* initially 1sec */
13488 +       add_timer(&locateNICtimer);
13489
13490 -       if (pAC->GIni.GIChipId == CHIP_ID_GENESIS)
13491 -               return -EOPNOTSUPP;
13492 -       return ethtool_op_set_sg(dev, data);
13493 +       return 0;
13494  }
13495
13496 -static int setTxCsum(struct net_device *dev, u32 data)
13497 +/*****************************************************************************
13498 + *
13499 + *     toggleLeds - Changes the LED state of an adapter
13500 + *
13501 + * Description:
13502 + *     This function changes the current state of all LEDs of an adapter so
13503 + *     that it can be located by a user. If the requested time interval for
13504 + *     this test has elapsed, this function cleans up everything that was
13505 + *     temporarily setup during the locate NIC test. This involves of course
13506 + *     also closing or opening any adapter so that the initial board state
13507 + *     is recovered.
13508 + *
13509 + * Returns:    N/A
13510 + *
13511 + */
13512 +static void toggleLeds(
13513 +unsigned long ptr)  /* holds the pointer to adapter control context */
13514  {
13515 -       DEV_NET *pNet = netdev_priv(dev);
13516 -       SK_AC *pAC = pNet->pAC;
13517 -
13518 -       if (pAC->GIni.GIChipId == CHIP_ID_GENESIS)
13519 -               return -EOPNOTSUPP;
13520 +       SK_AC                *pAC       = (SK_AC *) ptr;
13521 +       int                   port      = currentPortIndex;
13522 +       SK_IOC                IoC       = pAC->IoBase;
13523 +       struct SK_NET_DEVICE *pDev      = pAC->dev[port];
13524 +       int                   OtherPort = (port) ? 0 : 1;
13525 +       struct SK_NET_DEVICE *pOtherDev = pAC->dev[OtherPort];
13526 +
13527 +       SK_U16  YukLedOn = (PHY_M_LED_MO_DUP(MO_LED_ON)  |
13528 +                           PHY_M_LED_MO_10(MO_LED_ON)   |
13529 +                           PHY_M_LED_MO_100(MO_LED_ON)  |
13530 +                           PHY_M_LED_MO_1000(MO_LED_ON) |
13531 +                           PHY_M_LED_MO_RX(MO_LED_ON));
13532 +       SK_U16  YukLedOff = (PHY_M_LED_MO_DUP(MO_LED_OFF)  |
13533 +                            PHY_M_LED_MO_10(MO_LED_OFF)   |
13534 +                            PHY_M_LED_MO_100(MO_LED_OFF)  |
13535 +                            PHY_M_LED_MO_1000(MO_LED_OFF) |
13536 +                            PHY_M_LED_MO_RX(MO_LED_OFF));
13537 +
13538 +       nbrBlinkQuarterSeconds--;
13539 +       if (nbrBlinkQuarterSeconds <= 0) {
13540 +               (*pDev->stop)(pDev);
13541 +               if (isDualNetCard) {
13542 +                       (*pOtherDev->stop)(pOtherDev);
13543 +               }
13544
13545 -       return ethtool_op_set_tx_csum(dev, data);
13546 -}
13547 +               if (!boardWasDown[0]) {
13548 +                       (*pDev->open)(pDev);
13549 +               }
13550 +               if (isDualNetCard) {
13551 +                       (*pOtherDev->open)(pOtherDev);
13552 +               }
13553 +               isDualNetCard      = SK_FALSE;
13554 +               isLocateNICrunning = SK_FALSE;
13555 +               return;
13556 +       }
13557
13558 -static u32 getRxCsum(struct net_device *dev)
13559 -{
13560 -       DEV_NET *pNet = netdev_priv(dev);
13561 -       SK_AC *pAC = pNet->pAC;
13562 +       doSwitchLEDsOn = (doSwitchLEDsOn) ? SK_FALSE : SK_TRUE;
13563 +       if (doSwitchLEDsOn) {
13564 +               if (pAC->GIni.GIGenesis) {
13565 +                       SK_OUT8(IoC,MR_ADDR(port,LNK_LED_REG),(SK_U8)SK_LNK_ON);
13566 +                       SkGeYellowLED(pAC,IoC,LED_ON >> 1);
13567 +                       SkGeXmitLED(pAC,IoC,MR_ADDR(port,RX_LED_INI),SK_LED_TST);
13568 +                       if (pAC->GIni.GP[port].PhyType == SK_PHY_BCOM) {
13569 +                               SkXmPhyWrite(pAC,IoC,port,PHY_BCOM_P_EXT_CTRL,PHY_B_PEC_LED_ON);
13570 +                       } else if (pAC->GIni.GP[port].PhyType == SK_PHY_LONE) {
13571 +                               SkXmPhyWrite(pAC,IoC,port,PHY_LONE_LED_CFG,0x0800);
13572 +                       } else {
13573 +                               SkGeXmitLED(pAC,IoC,MR_ADDR(port,TX_LED_INI),SK_LED_TST);
13574 +                       }
13575 +               } else {
13576 +                       SkGmPhyWrite(pAC,IoC,port,PHY_MARV_LED_CTRL,0);
13577 +                       SkGmPhyWrite(pAC,IoC,port,PHY_MARV_LED_OVER,YukLedOn);
13578 +               }
13579 +       } else {
13580 +               if (pAC->GIni.GIGenesis) {
13581 +                       SK_OUT8(IoC,MR_ADDR(port,LNK_LED_REG),(SK_U8)SK_LNK_OFF);
13582 +                       SkGeYellowLED(pAC,IoC,LED_OFF >> 1);
13583 +                       SkGeXmitLED(pAC,IoC,MR_ADDR(port,RX_LED_INI),SK_LED_DIS);
13584 +                       if (pAC->GIni.GP[port].PhyType == SK_PHY_BCOM) {
13585 +                               SkXmPhyWrite(pAC,IoC,port,PHY_BCOM_P_EXT_CTRL,PHY_B_PEC_LED_OFF);
13586 +                       } else if (pAC->GIni.GP[port].PhyType == SK_PHY_LONE) {
13587 +                               SkXmPhyWrite(pAC,IoC,port,PHY_LONE_LED_CFG,PHY_L_LC_LEDT);
13588 +                       } else {
13589 +                               SkGeXmitLED(pAC,IoC,MR_ADDR(port,TX_LED_INI),SK_LED_DIS);
13590 +                       }
13591 +               } else {
13592 +                       SkGmPhyWrite(pAC,IoC,port,PHY_MARV_LED_CTRL,0);
13593 +                       SkGmPhyWrite(pAC,IoC,port,PHY_MARV_LED_OVER,YukLedOff);
13594 +               }
13595 +       }
13596
13597 -       return pAC->RxPort[pNet->PortNr].RxCsum;
13598 -}
13599 +       locateNICtimer.function = toggleLeds;
13600 +       locateNICtimer.data     = (unsigned long) pAC;
13601 +       locateNICtimer.expires  = jiffies + (HZ/4); /* 250ms */
13602 +       add_timer(&locateNICtimer);
13603 +}
13604 +#endif
13605
13606 -static int setRxCsum(struct net_device *dev, u32 data)
13607 +/*****************************************************************************
13608 + *
13609 + *     getPortNumber - evaluates the port number of an interface
13610 + *
13611 + * Description:
13612 + *     It may be that the current interface refers to one which is located
13613 + *     on a dual net adapter. Hence, this function will return the correct
13614 + *     port for further use.
13615 + *
13616 + * Returns:
13617 + *     the port number that corresponds to the selected adapter
13618 + *
13619 + */
13620 +static int getPortNumber(
13621 +struct net_device *netdev,  /* the pointer to netdev structure       */
13622 +struct ifreq      *ifr)     /* what interface the request refers to? */
13623  {
13624 -       DEV_NET *pNet = netdev_priv(dev);
13625 -       SK_AC *pAC = pNet->pAC;
13626 -
13627 -       if (pAC->GIni.GIChipId == CHIP_ID_GENESIS)
13628 -               return -EOPNOTSUPP;
13629 +       DEV_NET *pNet = (DEV_NET*) netdev->priv;
13630 +       SK_AC   *pAC  = pNet->pAC;
13631
13632 -       pAC->RxPort[pNet->PortNr].RxCsum = data != 0;
13633 +       if (pAC->dev[1] != pAC->dev[0]) {
13634 +               if (!strcmp(pAC->dev[1]->name, ifr->ifr_name)) {
13635 +                       return 1; /* port index 1 */
13636 +               }
13637 +       }
13638         return 0;
13639  }
13640
13641 -const struct ethtool_ops SkGeEthtoolOps = {
13642 -       .get_settings           = getSettings,
13643 -       .set_settings           = setSettings,
13644 -       .get_drvinfo            = getDriverInfo,
13645 -       .get_strings            = getStrings,
13646 -       .get_stats_count        = getStatsCount,
13647 -       .get_ethtool_stats      = getEthtoolStats,
13648 -       .phys_id                = locateDevice,
13649 -       .get_pauseparam         = getPauseParams,
13650 -       .set_pauseparam         = setPauseParams,
13651 -       .get_link               = ethtool_op_get_link,
13652 -       .get_perm_addr          = ethtool_op_get_perm_addr,
13653 -       .get_sg                 = ethtool_op_get_sg,
13654 -       .set_sg                 = setScatterGather,
13655 -       .get_tx_csum            = ethtool_op_get_tx_csum,
13656 -       .set_tx_csum            = setTxCsum,
13657 -       .get_rx_csum            = getRxCsum,
13658 -       .set_rx_csum            = setRxCsum,
13659 -};
13660 +/*******************************************************************************
13661 + *
13662 + * End of file
13663 + *
13664 + ******************************************************************************/
13665 diff -ruN linux/drivers/net/sk98lin/skge.c linux-new/drivers/net/sk98lin/skge.c
13666 --- linux/drivers/net/sk98lin/skge.c    2006-09-20 05:42:06.000000000 +0200
13667 +++ linux-new/drivers/net/sk98lin/skge.c        2006-07-28 14:13:56.000000000 +0200
13668 @@ -1,32 +1,26 @@
13669  /******************************************************************************
13670   *
13671 - * Name:       skge.c
13672 - * Project:    GEnesis, PCI Gigabit Ethernet Adapter
13673 - * Version:    $Revision$
13674 - * Date:               $Date$
13675 - * Purpose:    The main driver source module
13676 + * Name:        skge.c
13677 + * Project:     GEnesis, PCI Gigabit Ethernet Adapter
13678 + * Version:     $Revision$
13679 + * Date:        $Date$
13680 + * Purpose:     The main driver source module
13681   *
13682   ******************************************************************************/
13683
13684  /******************************************************************************
13685   *
13686   *     (C)Copyright 1998-2002 SysKonnect GmbH.
13687 - *     (C)Copyright 2002-2003 Marvell.
13688 + *     (C)Copyright 2002-2005 Marvell.
13689   *
13690   *     Driver for Marvell Yukon chipset and SysKonnect Gigabit Ethernet
13691   *      Server Adapters.
13692   *
13693 - *     Created 10-Feb-1999, based on Linux' acenic.c, 3c59x.c and
13694 - *     SysKonnects GEnesis Solaris driver
13695 - *     Author: Christoph Goos (cgoos@syskonnect.de)
13696 - *             Mirko Lindner (mlindner@syskonnect.de)
13697 + *     Author: Mirko Lindner (mlindner@syskonnect.de)
13698 + *             Ralph Roesler (rroesler@syskonnect.de)
13699   *
13700   *     Address all question to: linux@syskonnect.de
13701   *
13702 - *     The technical manual for the adapters is available from SysKonnect's
13703 - *     web pages: www.syskonnect.com
13704 - *     Goto "Support" and search Knowledge Base for "manual".
13705 - *
13706   *     This program is free software; you can redistribute it and/or modify
13707   *     it under the terms of the GNU General Public License as published by
13708   *     the Free Software Foundation; either version 2 of the License, or
13709 @@ -38,85 +32,53 @@
13710
13711  /******************************************************************************
13712   *
13713 - * Possible compiler options (#define xxx / -Dxxx):
13714 - *
13715 - *     debugging can be enable by changing SK_DEBUG_CHKMOD and
13716 - *     SK_DEBUG_CHKCAT in makefile (described there).
13717 - *
13718 - ******************************************************************************/
13719 -
13720 -/******************************************************************************
13721 - *
13722   * Description:
13723   *
13724 - *     This is the main module of the Linux GE driver.
13725 - *
13726 - *     All source files except skge.c, skdrv1st.h, skdrv2nd.h and sktypes.h
13727 - *     are part of SysKonnect's COMMON MODULES for the SK-98xx adapters.
13728 - *     Those are used for drivers on multiple OS', so some thing may seem
13729 - *     unnecessary complicated on Linux. Please do not try to 'clean up'
13730 - *     them without VERY good reasons, because this will make it more
13731 - *     difficult to keep the Linux driver in synchronisation with the
13732 - *     other versions.
13733 - *
13734 - * Include file hierarchy:
13735 - *
13736 - *     <linux/module.h>
13737 - *
13738 - *     "h/skdrv1st.h"
13739 - *             <linux/types.h>
13740 - *             <linux/kernel.h>
13741 - *             <linux/string.h>
13742 - *             <linux/errno.h>
13743 - *             <linux/ioport.h>
13744 - *             <linux/slab.h>
13745 - *             <linux/interrupt.h>
13746 - *             <linux/pci.h>
13747 - *             <linux/bitops.h>
13748 - *             <asm/byteorder.h>
13749 - *             <asm/io.h>
13750 - *             <linux/netdevice.h>
13751 - *             <linux/etherdevice.h>
13752 - *             <linux/skbuff.h>
13753 - *         those three depending on kernel version used:
13754 - *             <linux/bios32.h>
13755 - *             <linux/init.h>
13756 - *             <asm/uaccess.h>
13757 - *             <net/checksum.h>
13758 - *
13759 - *             "h/skerror.h"
13760 - *             "h/skdebug.h"
13761 - *             "h/sktypes.h"
13762 - *             "h/lm80.h"
13763 - *             "h/xmac_ii.h"
13764 - *
13765 - *      "h/skdrv2nd.h"
13766 - *             "h/skqueue.h"
13767 - *             "h/skgehwt.h"
13768 - *             "h/sktimer.h"
13769 - *             "h/ski2c.h"
13770 - *             "h/skgepnmi.h"
13771 - *             "h/skvpd.h"
13772 - *             "h/skgehw.h"
13773 - *             "h/skgeinit.h"
13774 - *             "h/skaddr.h"
13775 - *             "h/skgesirq.h"
13776 - *             "h/skrlmt.h"
13777 + *     All source files in this sk98lin directory except of the sk98lin
13778 + *     Linux specific files
13779 + *
13780 + *             - skdim.c
13781 + *             - skethtool.c
13782 + *             - skge.c
13783 + *             - skproc.c
13784 + *             - sky2.c
13785 + *             - Makefile
13786 + *             - h/skdrv1st.h
13787 + *             - h/skdrv2nd.h
13788 + *             - h/sktypes.h
13789 + *             - h/skversion.h
13790 + *
13791 + *     are part of SysKonnect's common modules for the SK-9xxx adapters.
13792 + *
13793 + *     Those common module files which are not Linux specific are used to
13794 + *     build drivers on different OS' (e.g. Windows, MAC OS) so that those
13795 + *     drivers are based on the same set of files
13796 + *
13797 + *     At a first glance, this seems to complicate things unnescessarily on
13798 + *     Linux, but please do not try to 'clean up' them without VERY good
13799 + *     reasons, because this will make it more difficult to keep the sk98lin
13800 + *     driver for Linux in synchronisation with the other drivers running on
13801 + *     other operating systems.
13802   *
13803   ******************************************************************************/
13804
13805  #include       "h/skversion.h"
13806
13807 -#include       <linux/in.h>
13808  #include       <linux/module.h>
13809 -#include       <linux/moduleparam.h>
13810  #include       <linux/init.h>
13811 -#include       <linux/dma-mapping.h>
13812 -#include       <linux/ip.h>
13813 +#include       <linux/ethtool.h>
13814 +
13815 +#ifdef CONFIG_PROC_FS
13816 +#include       <linux/proc_fs.h>
13817 +#endif
13818
13819  #include       "h/skdrv1st.h"
13820  #include       "h/skdrv2nd.h"
13821
13822 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
13823 +#include       <linux/moduleparam.h>
13824 +#endif
13825 +
13826  /*******************************************************************************
13827   *
13828   * Defines
13829 @@ -126,62 +88,15 @@
13830  /* for debuging on x86 only */
13831  /* #define BREAKPOINT() asm(" int $3"); */
13832
13833 -/* use the transmit hw checksum driver functionality */
13834 -#define USE_SK_TX_CHECKSUM
13835 -
13836 -/* use the receive hw checksum driver functionality */
13837 -#define USE_SK_RX_CHECKSUM
13838 -
13839 -/* use the scatter-gather functionality with sendfile() */
13840 -#define SK_ZEROCOPY
13841 -
13842 -/* use of a transmit complete interrupt */
13843 -#define USE_TX_COMPLETE
13844 -
13845 -/*
13846 - * threshold for copying small receive frames
13847 - * set to 0 to avoid copying, set to 9001 to copy all frames
13848 - */
13849 -#define SK_COPY_THRESHOLD      50
13850 -
13851 -/* number of adapters that can be configured via command line params */
13852 -#define SK_MAX_CARD_PARAM      16
13853 -
13854 -
13855 -
13856 -/*
13857 - * use those defines for a compile-in version of the driver instead
13858 - * of command line parameters
13859 - */
13860 -// #define LINK_SPEED_A        {"Auto", }
13861 -// #define LINK_SPEED_B        {"Auto", }
13862 -// #define AUTO_NEG_A  {"Sense", }
13863 -// #define AUTO_NEG_B  {"Sense", }
13864 -// #define DUP_CAP_A   {"Both", }
13865 -// #define DUP_CAP_B   {"Both", }
13866 -// #define FLOW_CTRL_A {"SymOrRem", }
13867 -// #define FLOW_CTRL_B {"SymOrRem", }
13868 -// #define ROLE_A      {"Auto", }
13869 -// #define ROLE_B      {"Auto", }
13870 -// #define PREF_PORT   {"A", }
13871 -// #define CON_TYPE    {"Auto", }
13872 -// #define RLMT_MODE   {"CheckLinkState", }
13873 -
13874 -#define DEV_KFREE_SKB(skb) dev_kfree_skb(skb)
13875 -#define DEV_KFREE_SKB_IRQ(skb) dev_kfree_skb_irq(skb)
13876 -#define DEV_KFREE_SKB_ANY(skb) dev_kfree_skb_any(skb)
13877 -
13878
13879  /* Set blink mode*/
13880  #define OEM_CONFIG_VALUE (     SK_ACT_LED_BLINK | \
13881                                 SK_DUP_LED_NORMAL | \
13882                                 SK_LED_LINK100_ON)
13883
13884 -
13885 -/* Isr return value */
13886 -#define SkIsrRetVar    irqreturn_t
13887 -#define SkIsrRetNone   IRQ_NONE
13888 -#define SkIsrRetHandled        IRQ_HANDLED
13889 +#define CLEAR_AND_START_RX(Port) SK_OUT8(pAC->IoBase, RxQueueAddr[(Port)]+Q_CSR, CSR_START | CSR_IRQ_CL_F)
13890 +#define START_RX(Port) SK_OUT8(pAC->IoBase, RxQueueAddr[(Port)]+Q_CSR, CSR_START)
13891 +#define CLEAR_TX_IRQ(Port,Prio) SK_OUT8(pAC->IoBase, TxQueueAddr[(Port)][(Prio)]+Q_CSR, CSR_IRQ_CL_F)
13892
13893
13894  /*******************************************************************************
13895 @@ -190,12 +105,25 @@
13896   *
13897   ******************************************************************************/
13898
13899 +static int     __devinit sk98lin_init_device(struct pci_dev *pdev, const struct pci_device_id *ent);
13900 +static void    sk98lin_remove_device(struct pci_dev *pdev);
13901 +#ifdef CONFIG_PM
13902 +static int     sk98lin_suspend(struct pci_dev *pdev, u32 state);
13903 +static int     sk98lin_resume(struct pci_dev *pdev);
13904 +static void    SkEnableWOMagicPacket(SK_AC *pAC, SK_IOC IoC, SK_MAC_ADDR MacAddr);
13905 +#endif
13906 +#ifdef Y2_RECOVERY
13907 +static void    SkGeHandleKernelTimer(unsigned long ptr);
13908 +void           SkGeCheckTimer(DEV_NET *pNet);
13909 +static SK_BOOL  CheckRXCounters(DEV_NET *pNet);
13910 +static void    CheckRxPath(DEV_NET *pNet);
13911 +#endif
13912  static void    FreeResources(struct SK_NET_DEVICE *dev);
13913  static int     SkGeBoardInit(struct SK_NET_DEVICE *dev, SK_AC *pAC);
13914  static SK_BOOL BoardAllocMem(SK_AC *pAC);
13915  static void    BoardFreeMem(SK_AC *pAC);
13916  static void    BoardInitMem(SK_AC *pAC);
13917 -static void    SetupRing(SK_AC*, void*, uintptr_t, RXD**, RXD**, RXD**, int*, SK_BOOL);
13918 +static void    SetupRing(SK_AC*, void*, uintptr_t, RXD**, RXD**, RXD**, int*, int*, SK_BOOL);
13919  static SkIsrRetVar     SkGeIsr(int irq, void *dev_id);
13920  static SkIsrRetVar     SkGeIsrOnePort(int irq, void *dev_id);
13921  static int     SkGeOpen(struct SK_NET_DEVICE *dev);
13922 @@ -206,39 +134,76 @@
13923  static struct  net_device_stats *SkGeStats(struct SK_NET_DEVICE *dev);
13924  static int     SkGeIoctl(struct SK_NET_DEVICE *dev, struct ifreq *rq, int cmd);
13925  static void    GetConfiguration(SK_AC*);
13926 +static void    ProductStr(SK_AC*);
13927  static int     XmitFrame(SK_AC*, TX_PORT*, struct sk_buff*);
13928  static void    FreeTxDescriptors(SK_AC*pAC, TX_PORT*);
13929  static void    FillRxRing(SK_AC*, RX_PORT*);
13930  static SK_BOOL FillRxDescriptor(SK_AC*, RX_PORT*);
13931 +#ifdef CONFIG_SK98LIN_NAPI
13932 +static int     SkGePoll(struct net_device *dev, int *budget);
13933 +static void    ReceiveIrq(SK_AC*, RX_PORT*, SK_BOOL, int*, int);
13934 +#else
13935  static void    ReceiveIrq(SK_AC*, RX_PORT*, SK_BOOL);
13936 -static void    ClearAndStartRx(SK_AC*, int);
13937 -static void    ClearTxIrq(SK_AC*, int, int);
13938 +#endif
13939 +#ifdef SK_POLL_CONTROLLER
13940 +static void    SkGeNetPoll(struct SK_NET_DEVICE *dev);
13941 +#endif
13942  static void    ClearRxRing(SK_AC*, RX_PORT*);
13943  static void    ClearTxRing(SK_AC*, TX_PORT*);
13944  static int     SkGeChangeMtu(struct SK_NET_DEVICE *dev, int new_mtu);
13945  static void    PortReInitBmu(SK_AC*, int);
13946  static int     SkGeIocMib(DEV_NET*, unsigned int, int);
13947  static int     SkGeInitPCI(SK_AC *pAC);
13948 -static void    StartDrvCleanupTimer(SK_AC *pAC);
13949 -static void    StopDrvCleanupTimer(SK_AC *pAC);
13950 -static int     XmitFrameSG(SK_AC*, TX_PORT*, struct sk_buff*);
13951 -
13952 -#ifdef SK_DIAG_SUPPORT
13953  static SK_U32   ParseDeviceNbrFromSlotName(const char *SlotName);
13954  static int      SkDrvInitAdapter(SK_AC *pAC, int devNbr);
13955  static int      SkDrvDeInitAdapter(SK_AC *pAC, int devNbr);
13956 -#endif
13957 +extern void    SkLocalEventQueue(      SK_AC *pAC,
13958 +                                       SK_U32 Class,
13959 +                                       SK_U32 Event,
13960 +                                       SK_U32 Param1,
13961 +                                       SK_U32 Param2,
13962 +                                       SK_BOOL Flag);
13963 +extern void    SkLocalEventQueue64(    SK_AC *pAC,
13964 +                                       SK_U32 Class,
13965 +                                       SK_U32 Event,
13966 +                                       SK_U64 Param,
13967 +                                       SK_BOOL Flag);
13968 +
13969 +static int     XmitFrameSG(SK_AC*, TX_PORT*, struct sk_buff*);
13970
13971  /*******************************************************************************
13972   *
13973   * Extern Function Prototypes
13974   *
13975   ******************************************************************************/
13976 +
13977 +extern SK_BOOL SkY2AllocateResources(SK_AC *pAC);
13978 +extern void SkY2FreeResources(SK_AC *pAC);
13979 +extern void SkY2AllocateRxBuffers(SK_AC *pAC,SK_IOC IoC,int Port);
13980 +extern void SkY2FreeRxBuffers(SK_AC *pAC,SK_IOC IoC,int Port);
13981 +extern void SkY2FreeTxBuffers(SK_AC *pAC,SK_IOC IoC,int Port);
13982 +extern SkIsrRetVar SkY2Isr(int irq,void *dev_id /*,struct pt_regs *ptregs*/ );
13983 +extern int SkY2Xmit(struct sk_buff *skb,struct SK_NET_DEVICE *dev);
13984 +extern void SkY2PortStop(SK_AC *pAC,SK_IOC IoC,int Port,int Dir,int RstMode);
13985 +extern void SkY2PortStart(SK_AC *pAC,SK_IOC IoC,int Port);
13986 +extern int SkY2RlmtSend(SK_AC *pAC,int PortNr,struct sk_buff *pMessage);
13987 +extern void SkY2RestartStatusUnit(SK_AC *pAC);
13988 +extern void FillReceiveTableYukon2(SK_AC *pAC,SK_IOC IoC,int Port);
13989 +#ifdef CONFIG_SK98LIN_NAPI
13990 +extern int SkY2Poll(struct net_device *dev, int *budget);
13991 +#endif
13992 +
13993  extern void SkDimEnableModerationIfNeeded(SK_AC *pAC);
13994 -extern void SkDimDisplayModerationSettings(SK_AC *pAC);
13995  extern void SkDimStartModerationTimer(SK_AC *pAC);
13996  extern void SkDimModerate(SK_AC *pAC);
13997 -extern void SkGeBlinkTimer(unsigned long data);
13998 +
13999 +extern int SkEthIoctl(struct net_device *netdev, struct ifreq *ifr);
14000 +
14001 +#ifdef CONFIG_PROC_FS
14002 +static const char      SK_Root_Dir_entry[] = "sk98lin";
14003 +static struct          proc_dir_entry *pSkRootDir;
14004 +extern struct  file_operations sk_proc_fops;
14005 +#endif
14006
14007  #ifdef DEBUG
14008  static void    DumpMsg(struct sk_buff*, char*);
14009 @@ -247,33 +212,454 @@
14010  #endif
14011
14012  /* global variables *********************************************************/
14013 +static const char *BootString = BOOT_STRING;
14014 +struct SK_NET_DEVICE *SkGeRootDev = NULL;
14015  static SK_BOOL DoPrintInterfaceChange = SK_TRUE;
14016 -extern const struct ethtool_ops SkGeEthtoolOps;
14017
14018  /* local variables **********************************************************/
14019  static uintptr_t TxQueueAddr[SK_MAX_MACS][2] = {{0x680, 0x600},{0x780, 0x700}};
14020  static uintptr_t RxQueueAddr[SK_MAX_MACS] = {0x400, 0x480};
14021 +static int sk98lin_max_boards_found = 0;
14022 +
14023 +#ifdef CONFIG_PROC_FS
14024 +static struct proc_dir_entry   *pSkRootDir;
14025 +#endif
14026 +
14027 +
14028 +
14029 +static struct pci_device_id sk98lin_pci_tbl[] __devinitdata = {
14030 +/*     { pci_vendor_id, pci_device_id, * SAMPLE ENTRY! *
14031 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, */
14032 +       { 0x10b7, 0x1700, /* 3Com (10b7), Gigabit Ethernet Adapter */
14033 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14034 +       { 0x10b7, 0x80eb, /* 3Com (10b7), 3Com 3C940B Gigabit LOM Ethernet Adapter */
14035 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14036 +       { 0x1148, 0x4300, /* SysKonnect (1148), SK-98xx Gigabit Ethernet Server Adapter */
14037 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14038 +       { 0x1148, 0x4320, /* SysKonnect (1148), SK-98xx V2.0 Gigabit Ethernet Adapter */
14039 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14040 +       { 0x1148, 0x9000, /* SysKonnect (1148), SK-9Sxx 10/100/1000Base-T Server Adapter  */
14041 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14042 +       { 0x1148, 0x9E00, /* SysKonnect (1148), SK-9Exx 10/100/1000Base-T Adapter */
14043 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14044 +       { 0x1186, 0x4001, /* D-Link (1186), Gigabit Ethernet Adapter */
14045 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14046 +       { 0x1186, 0x4b00, /* D-Link (1186), Gigabit Ethernet Adapter */
14047 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14048 +       { 0x1186, 0x4b01, /* D-Link (1186), Gigabit Ethernet Adapter */
14049 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14050 +       { 0x1186, 0x4b02, /* D-Link (1186), Gigabit Ethernet Adapter */
14051 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14052 +       { 0x1186, 0x4c00, /* D-Link (1186), Gigabit Ethernet Adapter */
14053 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14054 +       { 0x11ab, 0x4320, /* Marvell (11ab), Gigabit Ethernet Controller */
14055 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14056 +       { 0x11ab, 0x4340, /* Marvell (11ab), Gigabit Ethernet Controller  */
14057 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14058 +       { 0x11ab, 0x4341, /* Marvell (11ab), Gigabit Ethernet Controller  */
14059 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14060 +       { 0x11ab, 0x4342, /* Marvell (11ab), Gigabit Ethernet Controller  */
14061 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14062 +       { 0x11ab, 0x4343, /* Marvell (11ab), Gigabit Ethernet Controller  */
14063 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14064 +       { 0x11ab, 0x4344, /* Marvell (11ab), Gigabit Ethernet Controller  */
14065 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14066 +       { 0x11ab, 0x4345, /* Marvell (11ab), Gigabit Ethernet Controller  */
14067 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14068 +       { 0x11ab, 0x4346, /* Marvell (11ab), Gigabit Ethernet Controller  */
14069 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14070 +       { 0x11ab, 0x4347, /* Marvell (11ab), Gigabit Ethernet Controller  */
14071 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14072 +       { 0x11ab, 0x4350, /* Marvell (11ab), Fast Ethernet Controller */
14073 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14074 +       { 0x11ab, 0x4351, /* Marvell (11ab), Fast Ethernet Controller */
14075 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14076 +       { 0x11ab, 0x4352, /* Marvell (11ab), Fast Ethernet Controller */
14077 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14078 +       { 0x11ab, 0x4353, /* Marvell (11ab), Fast Ethernet Controller */
14079 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14080 +       { 0x11ab, 0x4356, /* Marvell (11ab), Gigabit Ethernet Controller */
14081 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14082 +       { 0x11ab, 0x4360, /* Marvell (11ab), Gigabit Ethernet Controller */
14083 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14084 +       { 0x11ab, 0x4361, /* Marvell (11ab), Gigabit Ethernet Controller */
14085 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14086 +       { 0x11ab, 0x4362, /* Marvell (11ab), Gigabit Ethernet Controller */
14087 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14088 +       { 0x11ab, 0x4363, /* Marvell (11ab), Marvell */
14089 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14090 +       { 0x11ab, 0x4364, /* Marvell (11ab), Gigabit Ethernet Controller */
14091 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14092 +       { 0x11ab, 0x4366, /* Marvell (11ab), Gigabit Ethernet Controller */
14093 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14094 +       { 0x11ab, 0x4367, /* Marvell (11ab), Gigabit Ethernet Controller */
14095 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14096 +       { 0x11ab, 0x4368, /* Marvell (11ab), Gigabit Ethernet Controller */
14097 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14098 +       { 0x11ab, 0x4369, /* Marvell (11ab), Gigabit Ethernet Controller */
14099 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14100 +       { 0x11ab, 0x5005, /* Marvell (11ab), Belkin */
14101 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14102 +       { 0x1371, 0x434e, /* CNet (1371), GigaCard Network Adapter */
14103 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14104 +       { 0x1737, 0x1032, /* Linksys (1737), Gigabit Network Adapter */
14105 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14106 +       { 0x1737, 0x1064, /* Linksys (1737), Gigabit Network Adapter */
14107 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14108 +       { 0, }
14109 +};
14110 +
14111 +MODULE_DEVICE_TABLE(pci, sk98lin_pci_tbl);
14112 +
14113 +static struct pci_driver sk98lin_driver = {
14114 +       .name           = DRIVER_FILE_NAME,
14115 +       .id_table       = sk98lin_pci_tbl,
14116 +       .probe          = sk98lin_init_device,
14117 +       .remove         = __devexit_p(sk98lin_remove_device),
14118 +#ifdef CONFIG_PM
14119 +       .suspend        = sk98lin_suspend,
14120 +       .resume         = sk98lin_resume
14121 +#endif
14122 +};
14123 +
14124
14125  /*****************************************************************************
14126   *
14127 - *     SkPciWriteCfgDWord - write a 32 bit value to pci config space
14128 + *     sk98lin_init_device - initialize the adapter
14129   *
14130   * Description:
14131 - *     This routine writes a 32 bit value to the pci configuration
14132 - *     space.
14133 + *     This function initializes the adapter. Resources for
14134 + *     the adapter are allocated and the adapter is brought into Init 1
14135 + *     state.
14136   *
14137   * Returns:
14138 - *     0 - indicate everything worked ok.
14139 - *     != 0 - error indication
14140 + *     0, if everything is ok
14141 + *     !=0, on error
14142   */
14143 -static inline int SkPciWriteCfgDWord(
14144 -SK_AC *pAC,    /* Adapter Control structure pointer */
14145 -int PciAddr,           /* PCI register address */
14146 -SK_U32 Val)            /* pointer to store the read value */
14147 +static int __devinit sk98lin_init_device(struct pci_dev *pdev,
14148 +                                 const struct pci_device_id *ent)
14149 +
14150  {
14151 -       pci_write_config_dword(pAC->PciDev, PciAddr, Val);
14152 -       return(0);
14153 -} /* SkPciWriteCfgDWord */
14154 +       static SK_BOOL          sk98lin_boot_string = SK_FALSE;
14155 +       static SK_BOOL          sk98lin_proc_entry = SK_FALSE;
14156 +       static int              sk98lin_boards_found = 0;
14157 +       SK_AC                   *pAC;
14158 +       DEV_NET                 *pNet = NULL;
14159 +       struct SK_NET_DEVICE *dev = NULL;
14160 +       int                     retval;
14161 +#ifdef CONFIG_PROC_FS
14162 +       struct proc_dir_entry   *pProcFile;
14163 +#endif
14164 +       int                     pci_using_dac;
14165 +
14166 +       retval = pci_enable_device(pdev);
14167 +       if (retval) {
14168 +               printk(KERN_ERR "Cannot enable PCI device, "
14169 +                       "aborting.\n");
14170 +               return retval;
14171 +       }
14172 +
14173 +       dev = NULL;
14174 +       pNet = NULL;
14175 +
14176 +
14177 +       /* INSERT * We have to find the power-management capabilities */
14178 +       /* Find power-management capability. */
14179 +
14180 +       pci_using_dac = 0;              /* Set 32 bit DMA per default */
14181 +       /* Configure DMA attributes. */
14182 +       retval = pci_set_dma_mask(pdev, (u64) 0xffffffffffffffffULL);
14183 +       if (!retval) {
14184 +               pci_using_dac = 1;
14185 +       } else {
14186 +               retval = pci_set_dma_mask(pdev, (u64) 0xffffffff);
14187 +               if (retval) {
14188 +                       printk(KERN_ERR "No usable DMA configuration, "
14189 +                              "aborting.\n");
14190 +                       return retval;
14191 +               }
14192 +       }
14193 +
14194 +
14195 +       if ((dev = alloc_etherdev(sizeof(DEV_NET))) == NULL) {
14196 +               printk(KERN_ERR "Unable to allocate etherdev "
14197 +                       "structure!\n");
14198 +               return -ENODEV;
14199 +       }
14200 +
14201 +       pNet = dev->priv;
14202 +       pNet->pAC = kmalloc(sizeof(SK_AC), GFP_KERNEL);
14203 +       if (pNet->pAC == NULL){
14204 +               free_netdev(dev);
14205 +               printk(KERN_ERR "Unable to allocate adapter "
14206 +                       "structure!\n");
14207 +               return -ENODEV;
14208 +       }
14209 +
14210 +
14211 +       /* Print message */
14212 +       if (!sk98lin_boot_string) {
14213 +               /* set display flag to TRUE so that */
14214 +               /* we only display this string ONCE */
14215 +               sk98lin_boot_string = SK_TRUE;
14216 +               printk("%s\n", BootString);
14217 +       }
14218 +
14219 +       memset(pNet->pAC, 0, sizeof(SK_AC));
14220 +       pAC = pNet->pAC;
14221 +       pAC->PciDev = pdev;
14222 +       pAC->PciDevId = pdev->device;
14223 +       pAC->dev[0] = dev;
14224 +       pAC->dev[1] = dev;
14225 +       sprintf(pAC->Name, "SysKonnect SK-98xx");
14226 +       pAC->CheckQueue = SK_FALSE;
14227 +
14228 +       dev->irq = pdev->irq;
14229 +       retval = SkGeInitPCI(pAC);
14230 +       if (retval) {
14231 +               printk("SKGE: PCI setup failed: %i\n", retval);
14232 +               free_netdev(dev);
14233 +               return -ENODEV;
14234 +       }
14235 +
14236 +       SET_MODULE_OWNER(dev);
14237 +
14238 +       dev->open               =  &SkGeOpen;
14239 +       dev->stop               =  &SkGeClose;
14240 +       dev->get_stats          =  &SkGeStats;
14241 +       dev->set_multicast_list =  &SkGeSetRxMode;
14242 +       dev->set_mac_address    =  &SkGeSetMacAddr;
14243 +       dev->do_ioctl           =  &SkGeIoctl;
14244 +       dev->change_mtu         =  &SkGeChangeMtu;
14245 +       dev->flags              &= ~IFF_RUNNING;
14246 +#ifdef SK_POLL_CONTROLLER
14247 +       dev->poll_controller    =  SkGeNetPoll;
14248 +#endif
14249 +       SET_NETDEV_DEV(dev, &pdev->dev);
14250 +
14251 +       pAC->Index = sk98lin_boards_found;
14252 +
14253 +       if (SkGeBoardInit(dev, pAC)) {
14254 +               free_netdev(dev);
14255 +               return -ENODEV;
14256 +       } else {
14257 +               ProductStr(pAC);
14258 +       }
14259 +
14260 +       if (pci_using_dac)
14261 +               dev->features |= NETIF_F_HIGHDMA;
14262 +
14263 +       /* shifter to later moment in time... */
14264 +       if (CHIP_ID_YUKON_2(pAC)) {
14265 +               dev->hard_start_xmit =  &SkY2Xmit;
14266 +#ifdef CONFIG_SK98LIN_NAPI
14267 +               dev->poll =  &SkY2Poll;
14268 +               dev->weight = 64;
14269 +#endif
14270 +       } else {
14271 +               dev->hard_start_xmit =  &SkGeXmit;
14272 +#ifdef CONFIG_SK98LIN_NAPI
14273 +               dev->poll =  &SkGePoll;
14274 +               dev->weight = 64;
14275 +#endif
14276 +       }
14277 +
14278 +#ifdef NETIF_F_TSO
14279 +#ifdef USE_SK_TSO_FEATURE
14280 +       if ((CHIP_ID_YUKON_2(pAC)) &&
14281 +               (pAC->GIni.GIChipId != CHIP_ID_YUKON_EC_U)) {
14282 +               dev->features |= NETIF_F_TSO;
14283 +       }
14284 +#endif
14285 +#endif
14286 +#ifdef CONFIG_SK98LIN_ZEROCOPY
14287 +       if (pAC->GIni.GIChipId != CHIP_ID_GENESIS)
14288 +               dev->features |= NETIF_F_SG;
14289 +#endif
14290 +#ifdef USE_SK_TX_CHECKSUM
14291 +       if (pAC->GIni.GIChipId != CHIP_ID_GENESIS)
14292 +               dev->features |= NETIF_F_IP_CSUM;
14293 +#endif
14294 +#ifdef USE_SK_RX_CHECKSUM
14295 +       pAC->RxPort[0].UseRxCsum = SK_TRUE;
14296 +       if (pAC->GIni.GIMacsFound == 2 ) {
14297 +               pAC->RxPort[1].UseRxCsum = SK_TRUE;
14298 +       }
14299 +#endif
14300 +
14301 +       /* Save the hardware revision */
14302 +       pAC->HWRevision = (((pAC->GIni.GIPciHwRev >> 4) & 0x0F)*10) +
14303 +               (pAC->GIni.GIPciHwRev & 0x0F);
14304 +
14305 +       /* Set driver globals */
14306 +       pAC->Pnmi.pDriverFileName    = DRIVER_FILE_NAME;
14307 +       pAC->Pnmi.pDriverReleaseDate = DRIVER_REL_DATE;
14308 +
14309 +       SK_MEMSET(&(pAC->PnmiBackup), 0, sizeof(SK_PNMI_STRUCT_DATA));
14310 +       SK_MEMCPY(&(pAC->PnmiBackup), &(pAC->PnmiStruct),
14311 +                       sizeof(SK_PNMI_STRUCT_DATA));
14312 +
14313 +       /* Register net device */
14314 +       retval = register_netdev(dev);
14315 +       if (retval) {
14316 +               printk(KERN_ERR "SKGE: Could not register device.\n");
14317 +               FreeResources(dev);
14318 +               free_netdev(dev);
14319 +               return retval;
14320 +       }
14321 +
14322 +       /* Save initial device name */
14323 +       strcpy(pNet->InitialDevName, dev->name);
14324 +
14325 +       /* Set network to off */
14326 +       netif_stop_queue(dev);
14327 +       netif_carrier_off(dev);
14328 +
14329 +       /* Print adapter specific string from vpd and config settings */
14330 +       printk("%s: %s\n", pNet->InitialDevName, pAC->DeviceStr);
14331 +       printk("      PrefPort:%c  RlmtMode:%s\n",
14332 +               'A' + pAC->Rlmt.Net[0].Port[pAC->Rlmt.Net[0].PrefPort]->PortNumber,
14333 +               (pAC->RlmtMode==0)  ? "Check Link State" :
14334 +               ((pAC->RlmtMode==1) ? "Check Link State" :
14335 +               ((pAC->RlmtMode==3) ? "Check Local Port" :
14336 +               ((pAC->RlmtMode==7) ? "Check Segmentation" :
14337 +               ((pAC->RlmtMode==17) ? "Dual Check Link State" :"Error")))));
14338 +
14339 +       SkGeYellowLED(pAC, pAC->IoBase, 1);
14340 +
14341 +       memcpy((caddr_t) &dev->dev_addr,
14342 +               (caddr_t) &pAC->Addr.Net[0].CurrentMacAddress, 6);
14343 +
14344 +       /* First adapter... Create proc and print message */
14345 +#ifdef CONFIG_PROC_FS
14346 +       if (!sk98lin_proc_entry) {
14347 +               sk98lin_proc_entry = SK_TRUE;
14348 +               SK_MEMCPY(&SK_Root_Dir_entry, BootString,
14349 +                       sizeof(SK_Root_Dir_entry) - 1);
14350 +
14351 +               /*Create proc (directory)*/
14352 +               if(!pSkRootDir) {
14353 +                       pSkRootDir = proc_mkdir(SK_Root_Dir_entry, proc_net);
14354 +                       if (!pSkRootDir) {
14355 +                               printk(KERN_WARNING "%s: Unable to create /proc/net/%s",
14356 +                                       dev->name, SK_Root_Dir_entry);
14357 +                       } else {
14358 +                               pSkRootDir->owner = THIS_MODULE;
14359 +                       }
14360 +               }
14361 +       }
14362 +
14363 +       /* Create proc file */
14364 +       if (pSkRootDir &&
14365 +               (pProcFile = create_proc_entry(pNet->InitialDevName, S_IRUGO,
14366 +                       pSkRootDir))) {
14367 +               pProcFile->proc_fops = &sk_proc_fops;
14368 +               pProcFile->data      = dev;
14369 +       }
14370 +
14371 +#endif
14372 +
14373 +       pNet->PortNr = 0;
14374 +       pNet->NetNr  = 0;
14375 +
14376 +       sk98lin_boards_found++;
14377 +       pci_set_drvdata(pdev, dev);
14378 +
14379 +       /* More then one port found */
14380 +       if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
14381 +               if ((dev = alloc_etherdev(sizeof(DEV_NET))) == 0) {
14382 +                       printk(KERN_ERR "Unable to allocate etherdev "
14383 +                               "structure!\n");
14384 +                       return -ENODEV;
14385 +               }
14386 +
14387 +               pAC->dev[1]   = dev;
14388 +               pNet          = dev->priv;
14389 +               pNet->PortNr  = 1;
14390 +               pNet->NetNr   = 1;
14391 +               pNet->pAC     = pAC;
14392 +
14393 +               if (CHIP_ID_YUKON_2(pAC)) {
14394 +                       dev->hard_start_xmit = &SkY2Xmit;
14395 +#ifdef CONFIG_SK98LIN_NAPI
14396 +                       dev->poll =  &SkY2Poll;
14397 +                       dev->weight = 64;
14398 +#endif
14399 +               } else {
14400 +                       dev->hard_start_xmit = &SkGeXmit;
14401 +#ifdef CONFIG_SK98LIN_NAPI
14402 +                       dev->poll =  &SkGePoll;
14403 +                       dev->weight = 64;
14404 +#endif
14405 +               }
14406 +               dev->open               = &SkGeOpen;
14407 +               dev->stop               = &SkGeClose;
14408 +               dev->get_stats          = &SkGeStats;
14409 +               dev->set_multicast_list = &SkGeSetRxMode;
14410 +               dev->set_mac_address    = &SkGeSetMacAddr;
14411 +               dev->do_ioctl           = &SkGeIoctl;
14412 +               dev->change_mtu         = &SkGeChangeMtu;
14413 +               dev->flags             &= ~IFF_RUNNING;
14414 +#ifdef SK_POLL_CONTROLLER
14415 +               dev->poll_controller    = SkGeNetPoll;
14416 +#endif
14417 +
14418 +#ifdef NETIF_F_TSO
14419 +#ifdef USE_SK_TSO_FEATURE
14420 +               if ((CHIP_ID_YUKON_2(pAC)) &&
14421 +                       (pAC->GIni.GIChipId != CHIP_ID_YUKON_EC_U)) {
14422 +                       dev->features |= NETIF_F_TSO;
14423 +               }
14424 +#endif
14425 +#endif
14426 +#ifdef CONFIG_SK98LIN_ZEROCOPY
14427 +               /* Don't handle if Genesis chipset */
14428 +               if (pAC->GIni.GIChipId != CHIP_ID_GENESIS)
14429 +                       dev->features |= NETIF_F_SG;
14430 +#endif
14431 +#ifdef USE_SK_TX_CHECKSUM
14432 +               /* Don't handle if Genesis chipset */
14433 +               if (pAC->GIni.GIChipId != CHIP_ID_GENESIS)
14434 +                       dev->features |= NETIF_F_IP_CSUM;
14435 +#endif
14436 +
14437 +               if (register_netdev(dev)) {
14438 +                       printk(KERN_ERR "SKGE: Could not register device.\n");
14439 +                       free_netdev(dev);
14440 +                       pAC->dev[1] = pAC->dev[0];
14441 +               } else {
14442 +
14443 +               /* Save initial device name */
14444 +               strcpy(pNet->InitialDevName, dev->name);
14445 +
14446 +               /* Set network to off */
14447 +               netif_stop_queue(dev);
14448 +               netif_carrier_off(dev);
14449 +
14450 +
14451 +#ifdef CONFIG_PROC_FS
14452 +               if (pSkRootDir
14453 +                   && (pProcFile = create_proc_entry(pNet->InitialDevName,
14454 +                                               S_IRUGO, pSkRootDir))) {
14455 +                       pProcFile->proc_fops = &sk_proc_fops;
14456 +                       pProcFile->data      = dev;
14457 +               }
14458 +#endif
14459 +
14460 +               memcpy((caddr_t) &dev->dev_addr,
14461 +               (caddr_t) &pAC->Addr.Net[1].CurrentMacAddress, 6);
14462 +
14463 +               printk("%s: %s\n", pNet->InitialDevName, pAC->DeviceStr);
14464 +               printk("      PrefPort:B  RlmtMode:Dual Check Link State\n");
14465 +               }
14466 +       }
14467 +
14468 +       pAC->Index = sk98lin_boards_found;
14469 +       sk98lin_max_boards_found = sk98lin_boards_found;
14470 +       return 0;
14471 +}
14472 +
14473 +
14474
14475  /*****************************************************************************
14476   *
14477 @@ -282,22 +668,26 @@
14478   * Description:
14479   *     This function initialize the PCI resources and IO
14480   *
14481 - * Returns:
14482 - *     0 - indicate everything worked ok.
14483 - *     != 0 - error indication
14484 + * Returns: N/A
14485 + *
14486   */
14487 -static __devinit int SkGeInitPCI(SK_AC *pAC)
14488 +static int SkGeInitPCI(SK_AC *pAC)
14489  {
14490         struct SK_NET_DEVICE *dev = pAC->dev[0];
14491         struct pci_dev *pdev = pAC->PciDev;
14492         int retval;
14493
14494 +       if (pci_enable_device(pdev) != 0) {
14495 +               return 1;
14496 +       }
14497 +
14498         dev->mem_start = pci_resource_start (pdev, 0);
14499         pci_set_master(pdev);
14500
14501 -       retval = pci_request_regions(pdev, "sk98lin");
14502 -       if (retval)
14503 -               goto out;
14504 +       if (pci_request_regions(pdev, DRIVER_FILE_NAME) != 0) {
14505 +               retval = 2;
14506 +               goto out_disable;
14507 +       }
14508
14509  #ifdef SK_BIG_ENDIAN
14510         /*
14511 @@ -315,9 +705,10 @@
14512         /*
14513          * Remap the regs into kernel space.
14514          */
14515 -       pAC->IoBase = ioremap_nocache(dev->mem_start, 0x4000);
14516 -       if (!pAC->IoBase) {
14517 -               retval = -EIO;
14518 +       pAC->IoBase = (char*)ioremap_nocache(dev->mem_start, 0x4000);
14519 +
14520 +       if (!pAC->IoBase){
14521 +               retval = 3;
14522                 goto out_release;
14523         }
14524
14525 @@ -325,10 +716,476 @@
14526
14527   out_release:
14528         pci_release_regions(pdev);
14529 - out:
14530 + out_disable:
14531 +       pci_disable_device(pdev);
14532         return retval;
14533  }
14534
14535 +#ifdef Y2_RECOVERY
14536 +/*****************************************************************************
14537 + *
14538 + *     SkGeHandleKernelTimer - Handle the kernel timer requests
14539 + *
14540 + * Description:
14541 + *     If the requested time interval for the timer has elapsed,
14542 + *     this function checks the link state.
14543 + *
14544 + * Returns:    N/A
14545 + *
14546 + */
14547 +static void SkGeHandleKernelTimer(
14548 +unsigned long ptr)  /* holds the pointer to adapter control context */
14549 +{
14550 +       DEV_NET         *pNet = (DEV_NET*) ptr;
14551 +       SkGeCheckTimer(pNet);
14552 +}
14553 +
14554 +/*****************************************************************************
14555 + *
14556 + *     sk98lin_check_timer - Resume the the card
14557 + *
14558 + * Description:
14559 + *     This function checks the kernel timer
14560 + *
14561 + * Returns: N/A
14562 + *
14563 + */
14564 +void SkGeCheckTimer(
14565 +DEV_NET *pNet)  /* holds the pointer to adapter control context */
14566 +{
14567 +       SK_AC           *pAC = pNet->pAC;
14568 +       SK_BOOL         StartTimer = SK_TRUE;
14569 +
14570 +       if (pNet->InRecover)
14571 +               return;
14572 +       if (pNet->TimerExpired)
14573 +               return;
14574 +       pNet->TimerExpired = SK_TRUE;
14575 +
14576 +#define TXPORT pAC->TxPort[pNet->PortNr][TX_PRIO_LOW]
14577 +#define RXPORT pAC->RxPort[pNet->PortNr]
14578 +
14579 +       if (    (CHIP_ID_YUKON_2(pAC)) &&
14580 +               (netif_running(pAC->dev[pNet->PortNr]))) {
14581 +
14582 +#ifdef Y2_RX_CHECK
14583 +               if (HW_FEATURE(pAC, HWF_WA_DEV_4167)) {
14584 +               /* Checks the RX path */
14585 +                       CheckRxPath(pNet);
14586 +               }
14587 +#endif
14588 +
14589 +               /* Checkthe transmitter */
14590 +               if (!(IS_Q_EMPTY(&TXPORT.TxAQ_working))) {
14591 +                       if (TXPORT.LastDone != TXPORT.TxALET.Done) {
14592 +                               TXPORT.LastDone = TXPORT.TxALET.Done;
14593 +                               pNet->TransmitTimeoutTimer = 0;
14594 +                       } else {
14595 +                               pNet->TransmitTimeoutTimer++;
14596 +                               if (pNet->TransmitTimeoutTimer >= 10) {
14597 +                                       pNet->TransmitTimeoutTimer = 0;
14598 +#ifdef CHECK_TRANSMIT_TIMEOUT
14599 +                                       StartTimer =  SK_FALSE;
14600 +                                       SkLocalEventQueue(pAC, SKGE_DRV,
14601 +                                               SK_DRV_RECOVER,pNet->PortNr,-1,SK_FALSE);
14602 +#endif
14603 +                               }
14604 +                       }
14605 +               }
14606 +
14607 +#ifdef CHECK_TRANSMIT_TIMEOUT
14608 +//             if (!timer_pending(&pNet->KernelTimer)) {
14609 +                       pNet->KernelTimer.expires = jiffies + (HZ/4); /* 100ms */
14610 +                       add_timer(&pNet->KernelTimer);
14611 +                       pNet->TimerExpired = SK_FALSE;
14612 +//             }
14613 +#endif
14614 +       }
14615 +}
14616 +
14617 +
14618 +/*****************************************************************************
14619 +*
14620 +* CheckRXCounters - Checks the the statistics for RX path hang
14621 +*
14622 +* Description:
14623 +*      This function is called periodical by a timer.
14624 +*
14625 +* Notes:
14626 +*
14627 +* Function Parameters:
14628 +*
14629 +* Returns:
14630 +*      Traffic status
14631 +*
14632 +*/
14633 +static SK_BOOL CheckRXCounters(
14634 +DEV_NET *pNet)  /* holds the pointer to adapter control context */
14635 +{
14636 +       SK_AC                   *pAC = pNet->pAC;
14637 +       SK_BOOL bStatus         = SK_FALSE;
14638 +
14639 +       /* Variable used to store the MAC RX FIFO RP, RPLev*/
14640 +       SK_U32                  MACFifoRP = 0;
14641 +       SK_U32                  MACFifoRLev = 0;
14642 +
14643 +       /* Variable used to store the PCI RX FIFO RP, RPLev*/
14644 +       SK_U32                  RXFifoRP = 0;
14645 +       SK_U8                   RXFifoRLev = 0;
14646 +
14647 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
14648 +               ("==> CheckRXCounters()\n"));
14649 +
14650 +       /*Check if statistic counters hangs*/
14651 +       if (pNet->LastJiffies == pAC->dev[pNet->PortNr]->last_rx) {
14652 +               /* Now read the values of read pointer/level from MAC RX FIFO again */
14653 +               SK_IN32(pAC->IoBase, MR_ADDR(pNet->PortNr, RX_GMF_RP), &MACFifoRP);
14654 +               SK_IN32(pAC->IoBase, MR_ADDR(pNet->PortNr, RX_GMF_RLEV), &MACFifoRLev);
14655 +
14656 +               /* Now read the values of read pointer/level from RX FIFO again */
14657 +               SK_IN8(pAC->IoBase, Q_ADDR(pAC->GIni.GP[pNet->PortNr].PRxQOff, Q_RX_RP), &RXFifoRP);
14658 +               SK_IN8(pAC->IoBase, Q_ADDR(pAC->GIni.GP[pNet->PortNr].PRxQOff, Q_RX_RL), &RXFifoRLev);
14659 +
14660 +               /* Check if the MAC RX hang */
14661 +               if ((MACFifoRP == pNet->PreviousMACFifoRP) &&
14662 +                       (pNet->PreviousMACFifoRP != 0) &&
14663 +                       (MACFifoRLev >= pNet->PreviousMACFifoRLev)){
14664 +                       bStatus = SK_TRUE;
14665 +               }
14666 +
14667 +               /* Check if the PCI RX hang */
14668 +               if ((RXFifoRP == pNet->PreviousRXFifoRP) &&
14669 +                       (pNet->PreviousRXFifoRP != 0) &&
14670 +                       (RXFifoRLev >= pNet->PreviousRXFifoRLev)){
14671 +                       /*Set the flag to indicate that the RX FIFO hangs*/
14672 +                       bStatus = SK_TRUE;
14673 +               }
14674 +       }
14675 +
14676 +       /* Store now the values of counters for next check */
14677 +       pNet->LastJiffies = pAC->dev[pNet->PortNr]->last_rx;
14678 +
14679 +       /* Store the values of  read pointer/level from MAC RX FIFO for next test */
14680 +       pNet->PreviousMACFifoRP = MACFifoRP;
14681 +       pNet->PreviousMACFifoRLev = MACFifoRLev;
14682 +
14683 +       /* Store the values of  read pointer/level from RX FIFO for next test */
14684 +       pNet->PreviousRXFifoRP = RXFifoRP;
14685 +       pNet->PreviousRXFifoRLev = RXFifoRLev;
14686 +
14687 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
14688 +               ("<== CheckRXCounters()\n"));
14689 +
14690 +       return bStatus;
14691 +}
14692 +
14693 +/*****************************************************************************
14694 +*
14695 +* CheckRxPath - Checks if the RX path
14696 +*
14697 +* Description:
14698 +*      This function is called periodical by a timer.
14699 +*
14700 +* Notes:
14701 +*
14702 +* Function Parameters:
14703 +*
14704 +* Returns:
14705 +*      None.
14706 +*
14707 +*/
14708 +static void  CheckRxPath(
14709 +DEV_NET *pNet)  /* holds the pointer to adapter control context */
14710 +{
14711 +       unsigned long           Flags;    /* for the spin locks    */
14712 +       /* Initialize the pAC structure.*/
14713 +       SK_AC                   *pAC = pNet->pAC;
14714 +
14715 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
14716 +               ("==> CheckRxPath()\n"));
14717 +
14718 +       /*If the statistics are not changed then could be an RX problem */
14719 +       if (CheckRXCounters(pNet)){
14720 +               /*
14721 +                * First we try the simple solution by resetting the Level Timer
14722 +                */
14723 +
14724 +               /* Stop Level Timer of Status BMU */
14725 +               SK_OUT8(pAC->IoBase, STAT_LEV_TIMER_CTRL, TIM_STOP);
14726 +
14727 +               /* Start Level Timer of Status BMU */
14728 +               SK_OUT8(pAC->IoBase, STAT_LEV_TIMER_CTRL, TIM_START);
14729 +
14730 +               if (!CheckRXCounters(pNet)) {
14731 +                       return;
14732 +               }
14733 +
14734 +               spin_lock_irqsave(&pAC->SlowPathLock, Flags);
14735 +               SkLocalEventQueue(pAC, SKGE_DRV,
14736 +                       SK_DRV_RECOVER,pNet->PortNr,-1,SK_TRUE);
14737 +
14738 +               /* Reset the fifo counters */
14739 +               pNet->PreviousMACFifoRP = 0;
14740 +               pNet->PreviousMACFifoRLev = 0;
14741 +               pNet->PreviousRXFifoRP = 0;
14742 +               pNet->PreviousRXFifoRLev = 0;
14743 +
14744 +               spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
14745 +       }
14746 +
14747 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
14748 +               ("<== CheckRxPath()\n"));
14749 +}
14750 +
14751 +
14752 +
14753 +#endif
14754 +
14755 +
14756 +#ifdef CONFIG_PM
14757 +/*****************************************************************************
14758 + *
14759 + *     sk98lin_resume - Resume the the card
14760 + *
14761 + * Description:
14762 + *     This function resumes the card into the D0 state
14763 + *
14764 + * Returns: N/A
14765 + *
14766 + */
14767 +static int sk98lin_resume(
14768 +struct pci_dev *pdev)   /* the device that is to resume */
14769 +{
14770 +       struct net_device   *dev  = pci_get_drvdata(pdev);
14771 +       DEV_NET             *pNet = (DEV_NET*) dev->priv;
14772 +       SK_AC               *pAC  = pNet->pAC;
14773 +       SK_U16               PmCtlSts;
14774 +
14775 +       /* Set the power state to D0 */
14776 +       pci_set_power_state(pdev, 0);
14777 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
14778 +       pci_restore_state(pdev);
14779 +#else
14780 +       pci_restore_state(pdev, pAC->PciState);
14781 +#endif
14782 +
14783 +       pci_enable_device(pdev);
14784 +       pci_set_master(pdev);
14785 +
14786 +       pci_enable_wake(pdev, 3, 0);
14787 +       pci_enable_wake(pdev, 4, 0);
14788 +
14789 +       SK_OUT8(pAC->IoBase, RX_GMF_CTRL_T, (SK_U8)GMF_RST_CLR);
14790 +
14791 +       /* Set the adapter power state to D0 */
14792 +       SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);
14793 +       PmCtlSts &= ~(PCI_PM_STATE_D3); /* reset all DState bits */
14794 +       PmCtlSts |= PCI_PM_STATE_D0;
14795 +       SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PmCtlSts);
14796 +
14797 +       /* Reinit the adapter and start the port again */
14798 +       pAC->BoardLevel = SK_INIT_DATA;
14799 +       SkDrvLeaveDiagMode(pAC);
14800 +
14801 +       if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) ||
14802 +               (CHIP_ID_YUKON_2(pAC)) ) {
14803 +               pAC->StatusLETable.Done  = 0;
14804 +               pAC->StatusLETable.Put   = 0;
14805 +               pAC->StatusLETable.HwPut = 0;
14806 +               SkGeY2InitStatBmu(pAC, pAC->IoBase, &pAC->StatusLETable);
14807 +       }
14808 +
14809 +       return 0;
14810 +}
14811 +
14812 +/*****************************************************************************
14813 + *
14814 + *     sk98lin_suspend - Suspend the card
14815 + *
14816 + * Description:
14817 + *     This function suspends the card into a defined state
14818 + *
14819 + * Returns: N/A
14820 + *
14821 + */
14822 +static int sk98lin_suspend(
14823 +struct pci_dev *pdev,   /* pointer to the device that is to suspend */
14824 +u32            state)  /* what power state is desired by Linux?    */
14825 +{
14826 +       struct net_device   *dev  = pci_get_drvdata(pdev);
14827 +       DEV_NET             *pNet = (DEV_NET*) dev->priv;
14828 +       SK_AC               *pAC  = pNet->pAC;
14829 +       SK_U16               PciPMControlStatus;
14830 +       SK_U16               PciPMCapabilities;
14831 +       SK_MAC_ADDR          MacAddr;
14832 +       int                  i;
14833 +
14834 +       /* GEnesis and first yukon revs do not support power management */
14835 +       if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {
14836 +               if (pAC->GIni.GIChipRev == 0) {
14837 +                       return 0; /* power management not supported */
14838 +               }
14839 +       }
14840 +
14841 +       if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
14842 +               return 0; /* not supported for this chipset */
14843 +       }
14844 +
14845 +       if (pAC->WolInfo.ConfiguredWolOptions == 0) {
14846 +               return 0; /* WOL possible, but disabled via ethtool */
14847 +       }
14848 +
14849 +       if(netif_running(dev)) {
14850 +               netif_stop_queue(dev); /* stop device if running */
14851 +       }
14852 +
14853 +       /* read the PM control/status register from the PCI config space */
14854 +       SK_IN16(pAC->IoBase, PCI_C(pAC, PCI_PM_CTL_STS), &PciPMControlStatus);
14855 +
14856 +       /* read the power management capabilities from the config space */
14857 +       SK_IN16(pAC->IoBase, PCI_C(pAC, PCI_PM_CAP_REG), &PciPMCapabilities);
14858 +
14859 +       /* Enable WakeUp with Magic Packet - get MAC address from adapter */
14860 +       for (i = 0; i < SK_MAC_ADDR_LEN; i++) {
14861 +               /* virtual address: will be used for data */
14862 +               SK_IN8(pAC->IoBase, (B2_MAC_1 + i), &MacAddr.a[i]);
14863 +       }
14864 +
14865 +       SkDrvEnterDiagMode(pAC);
14866 +       SkEnableWOMagicPacket(pAC, pAC->IoBase, MacAddr);
14867 +
14868 +       pci_enable_wake(pdev, 3, 1);
14869 +       pci_enable_wake(pdev, 4, 1);    /* 4 == D3 cold */
14870 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
14871 +       pci_save_state(pdev);
14872 +#else
14873 +       pci_save_state(pdev, pAC->PciState);
14874 +#endif
14875 +       pci_disable_device(pdev); // NEW
14876 +       pci_set_power_state(pdev, state); /* set the state */
14877 +
14878 +       return 0;
14879 +}
14880 +
14881 +
14882 +/******************************************************************************
14883 + *
14884 + *     SkEnableWOMagicPacket - Enable Wake on Magic Packet on the adapter
14885 + *
14886 + * Context:
14887 + *     init, pageable
14888 + *     the adapter should be de-initialized before calling this function
14889 + *
14890 + * Returns:
14891 + *     nothing
14892 + */
14893 +
14894 +static void SkEnableWOMagicPacket(
14895 +SK_AC         *pAC,      /* Adapter Control Context          */
14896 +SK_IOC         IoC,      /* I/O control context              */
14897 +SK_MAC_ADDR    MacAddr)  /* MacAddr expected in magic packet */
14898 +{
14899 +       SK_U16  Word;
14900 +       SK_U32  DWord;
14901 +       int     i;
14902 +       int     HwPortIndex;
14903 +       int     Port = 0;
14904 +
14905 +       /* use Port 0 as long as we do not have any dual port cards which support WOL */
14906 +       HwPortIndex = 0;
14907 +       DWord = 0;
14908 +
14909 +       SK_OUT16(IoC, 0x0004, 0x0002);  /* clear S/W Reset */
14910 +       SK_OUT16(IoC, 0x0f10, 0x0002);  /* clear Link Reset */
14911 +
14912 +       /*
14913 +        * PHY Configuration:
14914 +        * Autonegotioation is enalbed, advertise 10 HD, 10 FD,
14915 +        * 100 HD, and 100 FD.
14916 +        */
14917 +       if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) ||
14918 +               (pAC->GIni.GIChipId == CHIP_ID_YUKON) ||
14919 +               (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) ||
14920 +               (CHIP_ID_YUKON_2(pAC)) ) {
14921 +
14922 +               SK_OUT8(IoC, 0x0007, 0xa9);                     /* enable VAUX */
14923 +
14924 +               /* WA code for COMA mode */
14925 +               /* Only for yukon plus based chipsets rev A3 */
14926 +               if (pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3) {
14927 +                       SK_IN32(IoC, B2_GP_IO, &DWord);
14928 +                       DWord |= GP_DIR_9;                      /* set to output */
14929 +                       DWord &= ~GP_IO_9;                      /* clear PHY reset (active high) */
14930 +                       SK_OUT32(IoC, B2_GP_IO, DWord);         /* clear PHY reset */
14931 +               }
14932 +
14933 +               if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) ||
14934 +                       (pAC->GIni.GIChipId == CHIP_ID_YUKON)) {
14935 +                       SK_OUT32(IoC, 0x0f04, 0x01f04001);      /* set PHY reset */
14936 +                       SK_OUT32(IoC, 0x0f04, 0x01f04002);      /* clear PHY reset */
14937 +               } else {
14938 +                       SK_OUT8(IoC, 0x0f04, 0x02);             /* clear PHY reset */
14939 +               }
14940 +
14941 +               SK_OUT8(IoC, 0x0f00, 0x02);                     /* clear MAC reset */
14942 +               SkGmPhyWrite(pAC, IoC, Port, 4, 0x01e1);        /* advertise 10/100 HD/FD */
14943 +               SkGmPhyWrite(pAC, IoC, Port, 9, 0x0000);        /* do not advertise 1000 HD/FD */
14944 +               SkGmPhyWrite(pAC, IoC, Port, 00, 0xB300);       /* 100 MBit, disable Autoneg */
14945 +       } else if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) {
14946 +               SK_OUT8(IoC, 0x0007, 0xa9);                     /* enable VAUX */
14947 +               SK_OUT8(IoC, 0x0f04, 0x02);                     /* clear PHY reset */
14948 +               SK_OUT8(IoC, 0x0f00, 0x02);                     /* clear MAC reset */
14949 +               SkGmPhyWrite(pAC, IoC, Port, 16, 0x0130);       /* Enable Automatic Crossover */
14950 +               SkGmPhyWrite(pAC, IoC, Port, 00, 0xB300);       /* 100 MBit, disable Autoneg */
14951 +       }
14952 +
14953 +
14954 +       /*
14955 +        * MAC Configuration:
14956 +        * Set the MAC to 100 HD and enable the auto update features
14957 +        * for Speed, Flow Control and Duplex Mode.
14958 +        * If autonegotiation completes successfully the
14959 +        * MAC takes the link parameters from the PHY.
14960 +        * If the link partner doesn't support autonegotiation
14961 +        * the MAC can receive magic packets if the link partner
14962 +        * uses 100 HD.
14963 +        */
14964 +       SK_OUT16(IoC, 0x2804, 0x3832);
14965 +
14966 +
14967 +       /*
14968 +        * Set Up Magic Packet parameters
14969 +        */
14970 +       for (i = 0; i < 6; i+=2) {              /* set up magic packet MAC address */
14971 +               SK_IN16(IoC, 0x100 + i, &Word);
14972 +               SK_OUT16(IoC, 0xf24 + i, Word);
14973 +       }
14974 +
14975 +       SK_OUT16(IoC, 0x0f20, 0x0208);          /* enable PME on magic packet */
14976 +                                               /* and on wake up frame */
14977 +
14978 +       /*
14979 +        * Set up PME generation
14980 +        */
14981 +       /* set PME legacy mode */
14982 +       /* Only for PCI express based chipsets */
14983 +       if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) ||
14984 +               (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) ||
14985 +               (CHIP_ID_YUKON_2(pAC))) {
14986 +               SkPciReadCfgDWord(pAC, 0x40, &DWord);
14987 +               DWord |= 0x8000;
14988 +               SkPciWriteCfgDWord(pAC, 0x40, DWord);
14989 +       }
14990 +
14991 +       SK_OUT8(IoC, RX_GMF_CTRL_T, (SK_U8)GMF_RST_SET);
14992 +
14993 +       /* clear PME status and switch adapter to DState */
14994 +       SkPciReadCfgWord(pAC, 0x4c, &Word);
14995 +       Word |= 0x103;
14996 +       SkPciWriteCfgWord(pAC, 0x4c, Word);
14997 +}      /* SkEnableWOMagicPacket */
14998 +#endif
14999 +
15000
15001  /*****************************************************************************
15002   *
15003 @@ -347,20 +1204,24 @@
15004  DEV_NET                *pNet;
15005  SK_AC          *pAC;
15006
15007 -       pNet = netdev_priv(dev);
15008 -       pAC = pNet->pAC;
15009 -       AllocFlag = pAC->AllocFlag;
15010 -       if (pAC->PciDev) {
15011 -               pci_release_regions(pAC->PciDev);
15012 -       }
15013 -       if (AllocFlag & SK_ALLOC_IRQ) {
15014 -               free_irq(dev->irq, dev);
15015 -       }
15016 -       if (pAC->IoBase) {
15017 -               iounmap(pAC->IoBase);
15018 -       }
15019 -       if (pAC->pDescrMem) {
15020 -               BoardFreeMem(pAC);
15021 +       if (dev->priv) {
15022 +               pNet = (DEV_NET*) dev->priv;
15023 +               pAC = pNet->pAC;
15024 +               AllocFlag = pAC->AllocFlag;
15025 +               if (pAC->PciDev) {
15026 +                       pci_release_regions(pAC->PciDev);
15027 +               }
15028 +               if (AllocFlag & SK_ALLOC_IRQ) {
15029 +                       free_irq(dev->irq, dev);
15030 +               }
15031 +               if (pAC->IoBase) {
15032 +                       iounmap(pAC->IoBase);
15033 +               }
15034 +               if (CHIP_ID_YUKON_2(pAC)) {
15035 +                       SkY2FreeResources(pAC);
15036 +               } else {
15037 +                       BoardFreeMem(pAC);
15038 +               }
15039         }
15040
15041  } /* FreeResources */
15042 @@ -369,6 +1230,7 @@
15043  MODULE_DESCRIPTION("SysKonnect SK-NET Gigabit Ethernet SK-98xx driver");
15044  MODULE_LICENSE("GPL");
15045
15046 +
15047  #ifdef LINK_SPEED_A
15048  static char *Speed_A[SK_MAX_CARD_PARAM] = LINK_SPEED;
15049  #else
15050 @@ -450,9 +1312,11 @@
15051  static int   IntsPerSec[SK_MAX_CARD_PARAM];
15052  static char *Moderation[SK_MAX_CARD_PARAM];
15053  static char *ModerationMask[SK_MAX_CARD_PARAM];
15054 -static char *AutoSizing[SK_MAX_CARD_PARAM];
15055 -static char *Stats[SK_MAX_CARD_PARAM];
15056
15057 +static char *LowLatency[SK_MAX_CARD_PARAM];
15058 +static char *BroadcastPrio[SK_MAX_CARD_PARAM];
15059 +
15060 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
15061  module_param_array(Speed_A, charp, NULL, 0);
15062  module_param_array(Speed_B, charp, NULL, 0);
15063  module_param_array(AutoNeg_A, charp, NULL, 0);
15064 @@ -469,9 +1333,119 @@
15065  /* used for interrupt moderation */
15066  module_param_array(IntsPerSec, int, NULL, 0);
15067  module_param_array(Moderation, charp, NULL, 0);
15068 -module_param_array(Stats, charp, NULL, 0);
15069  module_param_array(ModerationMask, charp, NULL, 0);
15070 -module_param_array(AutoSizing, charp, NULL, 0);
15071 +module_param_array(LowLatency, charp, NULL, 0);
15072 +module_param_array(BroadcastPrio, charp, NULL, 0);
15073 +#else
15074 +MODULE_PARM(Speed_A,    "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15075 +MODULE_PARM(Speed_B,    "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15076 +MODULE_PARM(AutoNeg_A,  "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15077 +MODULE_PARM(AutoNeg_B,  "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15078 +MODULE_PARM(DupCap_A,   "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15079 +MODULE_PARM(DupCap_B,   "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15080 +MODULE_PARM(FlowCtrl_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15081 +MODULE_PARM(FlowCtrl_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15082 +MODULE_PARM(Role_A,    "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15083 +MODULE_PARM(Role_B,    "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15084 +MODULE_PARM(ConType,   "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15085 +MODULE_PARM(PrefPort,   "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15086 +MODULE_PARM(RlmtMode,   "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15087 +MODULE_PARM(IntsPerSec,     "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "i");
15088 +MODULE_PARM(Moderation,     "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15089 +MODULE_PARM(ModerationMask, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15090 +MODULE_PARM(LowLatency, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15091 +MODULE_PARM(BroadcastPrio, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15092 +#endif
15093 +
15094 +
15095 +/*****************************************************************************
15096 + *
15097 + *     sk98lin_remove_device - device deinit function
15098 + *
15099 + * Description:
15100 + *     Disable adapter if it is still running, free resources,
15101 + *     free device struct.
15102 + *
15103 + * Returns: N/A
15104 + */
15105 +
15106 +static void sk98lin_remove_device(struct pci_dev *pdev)
15107 +{
15108 +DEV_NET                *pNet;
15109 +SK_AC          *pAC;
15110 +struct SK_NET_DEVICE *next;
15111 +unsigned long Flags;
15112 +struct net_device *dev = pci_get_drvdata(pdev);
15113 +
15114 +
15115 +       /* Device not available. Return. */
15116 +       if (!dev)
15117 +               return;
15118 +
15119 +       pNet = (DEV_NET*) dev->priv;
15120 +       pAC = pNet->pAC;
15121 +       next = pAC->Next;
15122 +
15123 +       netif_stop_queue(dev);
15124 +       SkGeYellowLED(pAC, pAC->IoBase, 0);
15125 +
15126 +       if(pAC->BoardLevel == SK_INIT_RUN) {
15127 +               /* board is still alive */
15128 +               spin_lock_irqsave(&pAC->SlowPathLock, Flags);
15129 +               SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP,
15130 +                                       0, -1, SK_FALSE);
15131 +               SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP,
15132 +                                       1, -1, SK_TRUE);
15133 +
15134 +               /* disable interrupts */
15135 +               SK_OUT32(pAC->IoBase, B0_IMSK, 0);
15136 +               SkGeDeInit(pAC, pAC->IoBase);
15137 +               spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
15138 +               pAC->BoardLevel = SK_INIT_DATA;
15139 +               /* We do NOT check here, if IRQ was pending, of course*/
15140 +       }
15141 +
15142 +       if(pAC->BoardLevel == SK_INIT_IO) {
15143 +               /* board is still alive */
15144 +               SkGeDeInit(pAC, pAC->IoBase);
15145 +               pAC->BoardLevel = SK_INIT_DATA;
15146 +       }
15147 +
15148 +       if ((pAC->GIni.GIMacsFound == 2) && pAC->RlmtNets == 2){
15149 +               unregister_netdev(pAC->dev[1]);
15150 +               free_netdev(pAC->dev[1]);
15151 +       }
15152 +
15153 +       FreeResources(dev);
15154 +
15155 +#ifdef CONFIG_PROC_FS
15156 +       /* Remove the sk98lin procfs device entries */
15157 +       if ((pAC->GIni.GIMacsFound == 2) && pAC->RlmtNets == 2){
15158 +               remove_proc_entry(pAC->dev[1]->name, pSkRootDir);
15159 +       }
15160 +       remove_proc_entry(pNet->InitialDevName, pSkRootDir);
15161 +#endif
15162 +
15163 +       dev->get_stats = NULL;
15164 +       /*
15165 +        * otherwise unregister_netdev calls get_stats with
15166 +        * invalid IO ...  :-(
15167 +        */
15168 +       unregister_netdev(dev);
15169 +       free_netdev(dev);
15170 +       kfree(pAC);
15171 +       sk98lin_max_boards_found--;
15172 +
15173 +#ifdef CONFIG_PROC_FS
15174 +       /* Remove all Proc entries if last device */
15175 +       if (sk98lin_max_boards_found == 0) {
15176 +               /* clear proc-dir */
15177 +               remove_proc_entry(pSkRootDir->name, proc_net);
15178 +       }
15179 +#endif
15180 +
15181 +}
15182 +
15183
15184  /*****************************************************************************
15185   *
15186 @@ -509,12 +1483,11 @@
15187                 spin_lock_init(&pAC->TxPort[i][0].TxDesRingLock);
15188                 spin_lock_init(&pAC->RxPort[i].RxDesRingLock);
15189         }
15190 -       spin_lock_init(&pAC->SlowPathLock);
15191
15192 -       /* setup phy_id blink timer */
15193 -       pAC->BlinkTimer.function = SkGeBlinkTimer;
15194 -       pAC->BlinkTimer.data = (unsigned long) dev;
15195 -       init_timer(&pAC->BlinkTimer);
15196 +       spin_lock_init(&pAC->InitLock);         /* Init lock */
15197 +       spin_lock_init(&pAC->SlowPathLock);
15198 +       spin_lock_init(&pAC->TxQueueLock);      /* for Yukon2 chipsets */
15199 +       spin_lock_init(&pAC->SetPutIndexLock);  /* for Yukon2 chipsets */
15200
15201         /* level 0 init common modules here */
15202
15203 @@ -523,7 +1496,7 @@
15204         if (SkGeInit(pAC, pAC->IoBase, SK_INIT_DATA) != 0) {
15205                 printk("HWInit (0) failed.\n");
15206                 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
15207 -               return -EIO;
15208 +               return(-EAGAIN);
15209         }
15210         SkI2cInit(  pAC, pAC->IoBase, SK_INIT_DATA);
15211         SkEventInit(pAC, pAC->IoBase, SK_INIT_DATA);
15212 @@ -533,19 +1506,17 @@
15213         SkTimerInit(pAC, pAC->IoBase, SK_INIT_DATA);
15214
15215         pAC->BoardLevel = SK_INIT_DATA;
15216 -       pAC->RxBufSize  = ETH_BUF_SIZE;
15217 +       pAC->RxPort[0].RxBufSize = ETH_BUF_SIZE;
15218 +       pAC->RxPort[1].RxBufSize = ETH_BUF_SIZE;
15219
15220         SK_PNMI_SET_DRIVER_DESCR(pAC, DescrString);
15221         SK_PNMI_SET_DRIVER_VER(pAC, VerStr);
15222
15223 -       spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
15224 -
15225         /* level 1 init common modules here (HW init) */
15226 -       spin_lock_irqsave(&pAC->SlowPathLock, Flags);
15227         if (SkGeInit(pAC, pAC->IoBase, SK_INIT_IO) != 0) {
15228                 printk("sk98lin: HWInit (1) failed.\n");
15229                 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
15230 -               return -EIO;
15231 +               return(-EAGAIN);
15232         }
15233         SkI2cInit(  pAC, pAC->IoBase, SK_INIT_IO);
15234         SkEventInit(pAC, pAC->IoBase, SK_INIT_IO);
15235 @@ -553,46 +1524,93 @@
15236         SkAddrInit( pAC, pAC->IoBase, SK_INIT_IO);
15237         SkRlmtInit( pAC, pAC->IoBase, SK_INIT_IO);
15238         SkTimerInit(pAC, pAC->IoBase, SK_INIT_IO);
15239 +#ifdef Y2_RECOVERY
15240 +       /* mark entries invalid */
15241 +       pAC->LastPort = 3;
15242 +       pAC->LastOpc = 0xFF;
15243 +#endif
15244
15245         /* Set chipset type support */
15246 -       pAC->ChipsetType = 0;
15247         if ((pAC->GIni.GIChipId == CHIP_ID_YUKON) ||
15248 -               (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE)) {
15249 -               pAC->ChipsetType = 1;
15250 +               (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) ||
15251 +               (pAC->GIni.GIChipId == CHIP_ID_YUKON_LP)) {
15252 +               pAC->ChipsetType = 1;   /* Yukon chipset (descriptor logic) */
15253 +       } else if (CHIP_ID_YUKON_2(pAC)) {
15254 +               pAC->ChipsetType = 2;   /* Yukon2 chipset (list logic) */
15255 +       } else {
15256 +               pAC->ChipsetType = 0;   /* Genesis chipset (descriptor logic) */
15257 +       }
15258 +
15259 +       /* wake on lan support */
15260 +       pAC->WolInfo.SupportedWolOptions = 0;
15261 +#if defined (ETHTOOL_GWOL) && defined (ETHTOOL_SWOL)
15262 +       if (pAC->GIni.GIChipId != CHIP_ID_GENESIS) {
15263 +               pAC->WolInfo.SupportedWolOptions  = WAKE_MAGIC;
15264 +               if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {
15265 +                       if (pAC->GIni.GIChipRev == 0) {
15266 +                               pAC->WolInfo.SupportedWolOptions = 0;
15267 +                       }
15268 +               }
15269         }
15270 +#endif
15271 +       pAC->WolInfo.ConfiguredWolOptions = pAC->WolInfo.SupportedWolOptions;
15272
15273         GetConfiguration(pAC);
15274         if (pAC->RlmtNets == 2) {
15275 -               pAC->GIni.GIPortUsage = SK_MUL_LINK;
15276 +               pAC->GIni.GP[0].PPortUsage = SK_MUL_LINK;
15277 +               pAC->GIni.GP[1].PPortUsage = SK_MUL_LINK;
15278         }
15279
15280         pAC->BoardLevel = SK_INIT_IO;
15281         spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
15282
15283 -       if (pAC->GIni.GIMacsFound == 2) {
15284 -                Ret = request_irq(dev->irq, SkGeIsr, IRQF_SHARED, "sk98lin", dev);
15285 -       } else if (pAC->GIni.GIMacsFound == 1) {
15286 -               Ret = request_irq(dev->irq, SkGeIsrOnePort, IRQF_SHARED,
15287 -                       "sk98lin", dev);
15288 -       } else {
15289 -               printk(KERN_WARNING "sk98lin: Illegal number of ports: %d\n",
15290 -                      pAC->GIni.GIMacsFound);
15291 -               return -EIO;
15292 +       if (!CHIP_ID_YUKON_2(pAC)) {
15293 +               if (pAC->GIni.GIMacsFound == 2) {
15294 +                       Ret = request_irq(dev->irq, SkGeIsr, SA_SHIRQ, dev->name, dev);
15295 +               } else if (pAC->GIni.GIMacsFound == 1) {
15296 +                       Ret = request_irq(dev->irq, SkGeIsrOnePort, SA_SHIRQ, dev->name, dev);
15297 +               } else {
15298 +                       printk(KERN_WARNING "sk98lin: Illegal number of ports: %d\n",
15299 +                               pAC->GIni.GIMacsFound);
15300 +                       return -EAGAIN;
15301 +               }
15302 +       }
15303 +       else {
15304 +               Ret = request_irq(dev->irq, SkY2Isr, SA_SHIRQ, dev->name, dev);
15305         }
15306
15307         if (Ret) {
15308                 printk(KERN_WARNING "sk98lin: Requested IRQ %d is busy.\n",
15309 -                      dev->irq);
15310 -               return Ret;
15311 +                       dev->irq);
15312 +               return -EAGAIN;
15313         }
15314         pAC->AllocFlag |= SK_ALLOC_IRQ;
15315
15316 -       /* Alloc memory for this board (Mem for RxD/TxD) : */
15317 -       if(!BoardAllocMem(pAC)) {
15318 -               printk("No memory for descriptor rings.\n");
15319 -               return -ENOMEM;
15320 +       /*
15321 +       ** Alloc descriptor/LETable memory for this board (both RxD/TxD)
15322 +       */
15323 +       if (CHIP_ID_YUKON_2(pAC)) {
15324 +               if (!SkY2AllocateResources(pAC)) {
15325 +                       printk("No memory for Yukon2 settings\n");
15326 +                       return(-EAGAIN);
15327 +               }
15328 +       } else {
15329 +               if(!BoardAllocMem(pAC)) {
15330 +                       printk("No memory for descriptor rings.\n");
15331 +                       return(-EAGAIN);
15332 +               }
15333         }
15334
15335 +#ifdef SK_USE_CSUM
15336 +       SkCsSetReceiveFlags(pAC,
15337 +               SKCS_PROTO_IP | SKCS_PROTO_TCP | SKCS_PROTO_UDP,
15338 +               &pAC->CsOfs1, &pAC->CsOfs2, 0);
15339 +       pAC->CsOfs = (pAC->CsOfs2 << 16) | pAC->CsOfs1;
15340 +#endif
15341 +
15342 +       /*
15343 +       ** Function BoardInitMem() for Yukon dependent settings...
15344 +       */
15345         BoardInitMem(pAC);
15346         /* tschilling: New common function with minimum size check. */
15347         DualNet = SK_FALSE;
15348 @@ -604,11 +1622,22 @@
15349                 pAC,
15350                 pAC->ActivePort,
15351                 DualNet)) {
15352 -               BoardFreeMem(pAC);
15353 +               if (CHIP_ID_YUKON_2(pAC)) {
15354 +                       SkY2FreeResources(pAC);
15355 +               } else {
15356 +                       BoardFreeMem(pAC);
15357 +               }
15358 +
15359                 printk("sk98lin: SkGeInitAssignRamToQueues failed.\n");
15360 -               return -EIO;
15361 +               return(-EAGAIN);
15362         }
15363
15364 +       /*
15365 +        * Register the device here
15366 +        */
15367 +       pAC->Next = SkGeRootDev;
15368 +       SkGeRootDev = dev;
15369 +
15370         return (0);
15371  } /* SkGeBoardInit */
15372
15373 @@ -627,7 +1656,8 @@
15374   *     SK_TRUE, if all memory could be allocated
15375   *     SK_FALSE, if not
15376   */
15377 -static __devinit SK_BOOL BoardAllocMem(SK_AC   *pAC)
15378 +static SK_BOOL BoardAllocMem(
15379 +SK_AC  *pAC)
15380  {
15381  caddr_t                pDescrMem;      /* pointer to descriptor memory area */
15382  size_t         AllocLength;    /* length of complete descriptor area */
15383 @@ -697,16 +1727,20 @@
15384
15385         SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
15386                 ("BoardFreeMem\n"));
15387 +
15388 +       if (pAC->pDescrMem) {
15389 +
15390  #if (BITS_PER_LONG == 32)
15391 -       AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound + 8;
15392 +               AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound + 8;
15393  #else
15394 -       AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound
15395 -               + RX_RING_SIZE + 8;
15396 +               AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound
15397 +                       + RX_RING_SIZE + 8;
15398  #endif
15399
15400 -       pci_free_consistent(pAC->PciDev, AllocLength,
15401 +               pci_free_consistent(pAC->PciDev, AllocLength,
15402                             pAC->pDescrMem, pAC->pDescrMemDMA);
15403 -       pAC->pDescrMem = NULL;
15404 +               pAC->pDescrMem = NULL;
15405 +       }
15406  } /* BoardFreeMem */
15407
15408
15409 @@ -715,12 +1749,13 @@
15410   *     BoardInitMem - initiate the descriptor rings
15411   *
15412   * Description:
15413 - *     This function sets the descriptor rings up in memory.
15414 + *     This function sets the descriptor rings or LETables up in memory.
15415   *     The adapter is initialized with the descriptor start addresses.
15416   *
15417   * Returns:    N/A
15418   */
15419 -static __devinit void BoardInitMem(SK_AC *pAC)
15420 +static void BoardInitMem(
15421 +SK_AC  *pAC)   /* pointer to adapter context */
15422  {
15423  int    i;              /* loop counter */
15424  int    RxDescrSize;    /* the size of a rx descriptor rounded up to alignment*/
15425 @@ -729,34 +1764,37 @@
15426         SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
15427                 ("BoardInitMem\n"));
15428
15429 -       RxDescrSize = (((sizeof(RXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN;
15430 -       pAC->RxDescrPerRing = RX_RING_SIZE / RxDescrSize;
15431 -       TxDescrSize = (((sizeof(TXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN;
15432 -       pAC->TxDescrPerRing = TX_RING_SIZE / RxDescrSize;
15433 +       if (!pAC->GIni.GIYukon2) {
15434 +               RxDescrSize = (((sizeof(RXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN;
15435 +               pAC->RxDescrPerRing = RX_RING_SIZE / RxDescrSize;
15436 +               TxDescrSize = (((sizeof(TXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN;
15437 +               pAC->TxDescrPerRing = TX_RING_SIZE / RxDescrSize;
15438
15439 -       for (i=0; i<pAC->GIni.GIMacsFound; i++) {
15440 -               SetupRing(
15441 -                       pAC,
15442 -                       pAC->TxPort[i][0].pTxDescrRing,
15443 -                       pAC->TxPort[i][0].VTxDescrRing,
15444 -                       (RXD**)&pAC->TxPort[i][0].pTxdRingHead,
15445 -                       (RXD**)&pAC->TxPort[i][0].pTxdRingTail,
15446 -                       (RXD**)&pAC->TxPort[i][0].pTxdRingPrev,
15447 -                       &pAC->TxPort[i][0].TxdRingFree,
15448 -                       SK_TRUE);
15449 -               SetupRing(
15450 -                       pAC,
15451 -                       pAC->RxPort[i].pRxDescrRing,
15452 -                       pAC->RxPort[i].VRxDescrRing,
15453 -                       &pAC->RxPort[i].pRxdRingHead,
15454 -                       &pAC->RxPort[i].pRxdRingTail,
15455 -                       &pAC->RxPort[i].pRxdRingPrev,
15456 -                       &pAC->RxPort[i].RxdRingFree,
15457 -                       SK_FALSE);
15458 +               for (i=0; i<pAC->GIni.GIMacsFound; i++) {
15459 +                       SetupRing(
15460 +                               pAC,
15461 +                               pAC->TxPort[i][0].pTxDescrRing,
15462 +                               pAC->TxPort[i][0].VTxDescrRing,
15463 +                               (RXD**)&pAC->TxPort[i][0].pTxdRingHead,
15464 +                               (RXD**)&pAC->TxPort[i][0].pTxdRingTail,
15465 +                               (RXD**)&pAC->TxPort[i][0].pTxdRingPrev,
15466 +                               &pAC->TxPort[i][0].TxdRingFree,
15467 +                               &pAC->TxPort[i][0].TxdRingPrevFree,
15468 +                               SK_TRUE);
15469 +                       SetupRing(
15470 +                               pAC,
15471 +                               pAC->RxPort[i].pRxDescrRing,
15472 +                               pAC->RxPort[i].VRxDescrRing,
15473 +                               &pAC->RxPort[i].pRxdRingHead,
15474 +                               &pAC->RxPort[i].pRxdRingTail,
15475 +                               &pAC->RxPort[i].pRxdRingPrev,
15476 +                               &pAC->RxPort[i].RxdRingFree,
15477 +                               &pAC->RxPort[i].RxdRingFree,
15478 +                               SK_FALSE);
15479 +               }
15480         }
15481  } /* BoardInitMem */
15482
15483 -
15484  /*****************************************************************************
15485   *
15486   *     SetupRing - create one descriptor ring
15487 @@ -776,6 +1814,7 @@
15488  RXD            **ppRingTail,   /* address where the tail should be written */
15489  RXD            **ppRingPrev,   /* address where the tail should be written */
15490  int            *pRingFree,     /* address where the # of free descr. goes */
15491 +int            *pRingPrevFree, /* address where the # of free descr. goes */
15492  SK_BOOL                IsTx)           /* flag: is this a tx ring */
15493  {
15494  int    i;              /* loop counter */
15495 @@ -808,7 +1847,7 @@
15496                 /* set the pointers right */
15497                 pDescr->VNextRxd = VNextDescr & 0xffffffffULL;
15498                 pDescr->pNextRxd = pNextDescr;
15499 -               if (!IsTx) pDescr->TcpSumStarts = ETH_HLEN << 16 | ETH_HLEN;
15500 +               pDescr->TcpSumStarts = pAC->CsOfs;
15501
15502                 /* advance one step */
15503                 pPrevDescr = pDescr;
15504 @@ -818,11 +1857,12 @@
15505         }
15506         pPrevDescr->pNextRxd = (RXD*) pMemArea;
15507         pPrevDescr->VNextRxd = VMemArea;
15508 -       pDescr = (RXD*) pMemArea;
15509 -       *ppRingHead = (RXD*) pMemArea;
15510 -       *ppRingTail = *ppRingHead;
15511 -       *ppRingPrev = pPrevDescr;
15512 -       *pRingFree = DescrNum;
15513 +       pDescr               = (RXD*) pMemArea;
15514 +       *ppRingHead          = (RXD*) pMemArea;
15515 +       *ppRingTail          = *ppRingHead;
15516 +       *ppRingPrev          = pPrevDescr;
15517 +       *pRingFree           = DescrNum;
15518 +       *pRingPrevFree       = DescrNum;
15519  } /* SetupRing */
15520
15521
15522 @@ -887,17 +1927,35 @@
15523  SK_AC          *pAC;
15524  SK_U32         IntSrc;         /* interrupts source register contents */
15525
15526 -       pNet = netdev_priv(dev);
15527 +       pNet = (DEV_NET*) dev->priv;
15528         pAC = pNet->pAC;
15529
15530         /*
15531          * Check and process if its our interrupt
15532          */
15533         SK_IN32(pAC->IoBase, B0_SP_ISRC, &IntSrc);
15534 -       if (IntSrc == 0) {
15535 +       if ((IntSrc == 0) && (!pNet->NetConsoleMode)) {
15536                 return SkIsrRetNone;
15537         }
15538
15539 +#ifdef CONFIG_SK98LIN_NAPI
15540 +       if (netif_rx_schedule_prep(dev)) {
15541 +               pAC->GIni.GIValIrqMask &= ~(NAPI_DRV_IRQS);
15542 +               SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
15543 +               __netif_rx_schedule(dev);
15544 +       }
15545 +
15546 +#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
15547 +       if (IntSrc & IS_XA1_F) {
15548 +               CLEAR_TX_IRQ(0, TX_PRIO_LOW);
15549 +       }
15550 +       if (IntSrc & IS_XA2_F) {
15551 +               CLEAR_TX_IRQ(1, TX_PRIO_LOW);
15552 +       }
15553 +#endif
15554 +
15555 +
15556 +#else
15557         while (((IntSrc & IRQ_MASK) & ~SPECIAL_IRQS) != 0) {
15558  #if 0 /* software irq currently not used */
15559                 if (IntSrc & IS_IRQ_SW) {
15560 @@ -911,6 +1969,7 @@
15561                                 SK_DBGCAT_DRV_INT_SRC,
15562                                 ("EOF RX1 IRQ\n"));
15563                         ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE);
15564 +                       CLEAR_AND_START_RX(0);
15565                         SK_PNMI_CNT_RX_INTR(pAC, 0);
15566                 }
15567                 if (IntSrc & IS_R2_F) {
15568 @@ -918,6 +1977,7 @@
15569                                 SK_DBGCAT_DRV_INT_SRC,
15570                                 ("EOF RX2 IRQ\n"));
15571                         ReceiveIrq(pAC, &pAC->RxPort[1], SK_TRUE);
15572 +                       CLEAR_AND_START_RX(1);
15573                         SK_PNMI_CNT_RX_INTR(pAC, 1);
15574                 }
15575  #ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
15576 @@ -925,6 +1985,7 @@
15577                         SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
15578                                 SK_DBGCAT_DRV_INT_SRC,
15579                                 ("EOF AS TX1 IRQ\n"));
15580 +                       CLEAR_TX_IRQ(0, TX_PRIO_LOW);
15581                         SK_PNMI_CNT_TX_INTR(pAC, 0);
15582                         spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
15583                         FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]);
15584 @@ -934,6 +1995,7 @@
15585                         SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
15586                                 SK_DBGCAT_DRV_INT_SRC,
15587                                 ("EOF AS TX2 IRQ\n"));
15588 +                       CLEAR_TX_IRQ(1, TX_PRIO_LOW);
15589                         SK_PNMI_CNT_TX_INTR(pAC, 1);
15590                         spin_lock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock);
15591                         FreeTxDescriptors(pAC, &pAC->TxPort[1][TX_PRIO_LOW]);
15592 @@ -944,38 +2006,42 @@
15593                         SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
15594                                 SK_DBGCAT_DRV_INT_SRC,
15595                                 ("EOF SY TX1 IRQ\n"));
15596 +                       CLEAR_TX_IRQ(0, TX_PRIO_HIGH);
15597                         SK_PNMI_CNT_TX_INTR(pAC, 1);
15598                         spin_lock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock);
15599                         FreeTxDescriptors(pAC, 0, TX_PRIO_HIGH);
15600                         spin_unlock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock);
15601 -                       ClearTxIrq(pAC, 0, TX_PRIO_HIGH);
15602                 }
15603                 if (IntSrc & IS_XS2_F) {
15604                         SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
15605                                 SK_DBGCAT_DRV_INT_SRC,
15606                                 ("EOF SY TX2 IRQ\n"));
15607 +                       CLEAR_TX_IRQ(1, TX_PRIO_HIGH);
15608                         SK_PNMI_CNT_TX_INTR(pAC, 1);
15609                         spin_lock(&pAC->TxPort[1][TX_PRIO_HIGH].TxDesRingLock);
15610                         FreeTxDescriptors(pAC, 1, TX_PRIO_HIGH);
15611                         spin_unlock(&pAC->TxPort[1][TX_PRIO_HIGH].TxDesRingLock);
15612 -                       ClearTxIrq(pAC, 1, TX_PRIO_HIGH);
15613                 }
15614  #endif
15615  #endif
15616
15617 -               /* do all IO at once */
15618 -               if (IntSrc & IS_R1_F)
15619 -                       ClearAndStartRx(pAC, 0);
15620 -               if (IntSrc & IS_R2_F)
15621 -                       ClearAndStartRx(pAC, 1);
15622 -#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
15623 -               if (IntSrc & IS_XA1_F)
15624 -                       ClearTxIrq(pAC, 0, TX_PRIO_LOW);
15625 -               if (IntSrc & IS_XA2_F)
15626 -                       ClearTxIrq(pAC, 1, TX_PRIO_LOW);
15627 -#endif
15628                 SK_IN32(pAC->IoBase, B0_ISRC, &IntSrc);
15629         } /* while (IntSrc & IRQ_MASK != 0) */
15630 +#endif
15631 +
15632 +#ifndef CONFIG_SK98LIN_NAPI
15633 +       /* Handle interrupts */
15634 +       spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
15635 +       FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]);
15636 +       spin_unlock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
15637 +       ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE);
15638 +       START_RX(0);
15639 +       spin_lock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock);
15640 +       FreeTxDescriptors(pAC, &pAC->TxPort[1][TX_PRIO_LOW]);
15641 +       spin_unlock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock);
15642 +       ReceiveIrq(pAC, &pAC->RxPort[1], SK_TRUE);
15643 +       START_RX(1);
15644 +#endif
15645
15646         IntSrc &= pAC->GIni.GIValIrqMask;
15647         if ((IntSrc & SPECIAL_IRQS) || pAC->CheckQueue) {
15648 @@ -988,19 +2054,9 @@
15649
15650                 SkEventDispatcher(pAC, pAC->IoBase);
15651                 spin_unlock(&pAC->SlowPathLock);
15652 +               START_RX(0);
15653 +               START_RX(1);
15654         }
15655 -       /*
15656 -        * do it all again is case we cleared an interrupt that
15657 -        * came in after handling the ring (OUTs may be delayed
15658 -        * in hardware buffers, but are through after IN)
15659 -        *
15660 -        * rroesler: has been commented out and shifted to
15661 -        *           SkGeDrvEvent(), because it is timer
15662 -        *           guarded now
15663 -        *
15664 -       ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE);
15665 -       ReceiveIrq(pAC, &pAC->RxPort[1], SK_TRUE);
15666 -        */
15667
15668         if (pAC->CheckQueue) {
15669                 pAC->CheckQueue = SK_FALSE;
15670 @@ -1012,7 +2068,7 @@
15671         /* IRQ is processed - Enable IRQs again*/
15672         SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
15673
15674 -               return SkIsrRetHandled;
15675 +       return SkIsrRetHandled;
15676  } /* SkGeIsr */
15677
15678
15679 @@ -1036,17 +2092,32 @@
15680  SK_AC          *pAC;
15681  SK_U32         IntSrc;         /* interrupts source register contents */
15682
15683 -       pNet = netdev_priv(dev);
15684 +       pNet = (DEV_NET*) dev->priv;
15685         pAC = pNet->pAC;
15686
15687         /*
15688          * Check and process if its our interrupt
15689          */
15690         SK_IN32(pAC->IoBase, B0_SP_ISRC, &IntSrc);
15691 -       if (IntSrc == 0) {
15692 +       if ((IntSrc == 0) && (!pNet->NetConsoleMode)) {
15693                 return SkIsrRetNone;
15694         }
15695
15696 +#ifdef CONFIG_SK98LIN_NAPI
15697 +       if (netif_rx_schedule_prep(dev)) {
15698 +               CLEAR_AND_START_RX(0);
15699 +               CLEAR_TX_IRQ(0, TX_PRIO_LOW);
15700 +               pAC->GIni.GIValIrqMask &= ~(NAPI_DRV_IRQS);
15701 +               SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
15702 +               __netif_rx_schedule(dev);
15703 +       }
15704 +
15705 +#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
15706 +       if (IntSrc & IS_XA1_F) {
15707 +               CLEAR_TX_IRQ(0, TX_PRIO_LOW);
15708 +       }
15709 +#endif
15710 +#else
15711         while (((IntSrc & IRQ_MASK) & ~SPECIAL_IRQS) != 0) {
15712  #if 0 /* software irq currently not used */
15713                 if (IntSrc & IS_IRQ_SW) {
15714 @@ -1060,6 +2131,7 @@
15715                                 SK_DBGCAT_DRV_INT_SRC,
15716                                 ("EOF RX1 IRQ\n"));
15717                         ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE);
15718 +                       CLEAR_AND_START_RX(0);
15719                         SK_PNMI_CNT_RX_INTR(pAC, 0);
15720                 }
15721  #ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
15722 @@ -1067,6 +2139,7 @@
15723                         SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
15724                                 SK_DBGCAT_DRV_INT_SRC,
15725                                 ("EOF AS TX1 IRQ\n"));
15726 +                       CLEAR_TX_IRQ(0, TX_PRIO_LOW);
15727                         SK_PNMI_CNT_TX_INTR(pAC, 0);
15728                         spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
15729                         FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]);
15730 @@ -1077,25 +2150,27 @@
15731                         SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
15732                                 SK_DBGCAT_DRV_INT_SRC,
15733                                 ("EOF SY TX1 IRQ\n"));
15734 +                       CLEAR_TX_IRQ(0, TX_PRIO_HIGH);
15735                         SK_PNMI_CNT_TX_INTR(pAC, 0);
15736                         spin_lock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock);
15737                         FreeTxDescriptors(pAC, 0, TX_PRIO_HIGH);
15738                         spin_unlock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock);
15739 -                       ClearTxIrq(pAC, 0, TX_PRIO_HIGH);
15740                 }
15741  #endif
15742  #endif
15743
15744 -               /* do all IO at once */
15745 -               if (IntSrc & IS_R1_F)
15746 -                       ClearAndStartRx(pAC, 0);
15747 -#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
15748 -               if (IntSrc & IS_XA1_F)
15749 -                       ClearTxIrq(pAC, 0, TX_PRIO_LOW);
15750 -#endif
15751                 SK_IN32(pAC->IoBase, B0_ISRC, &IntSrc);
15752         } /* while (IntSrc & IRQ_MASK != 0) */
15753 +#endif
15754
15755 +#ifndef CONFIG_SK98LIN_NAPI
15756 +       spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
15757 +       FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]);
15758 +       spin_unlock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
15759 +       ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE);
15760 +       START_RX(0);
15761 +#endif
15762 +
15763         IntSrc &= pAC->GIni.GIValIrqMask;
15764         if ((IntSrc & SPECIAL_IRQS) || pAC->CheckQueue) {
15765                 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
15766 @@ -1107,44 +2182,15 @@
15767
15768                 SkEventDispatcher(pAC, pAC->IoBase);
15769                 spin_unlock(&pAC->SlowPathLock);
15770 +               START_RX(0);
15771         }
15772 -       /*
15773 -        * do it all again is case we cleared an interrupt that
15774 -        * came in after handling the ring (OUTs may be delayed
15775 -        * in hardware buffers, but are through after IN)
15776 -        *
15777 -        * rroesler: has been commented out and shifted to
15778 -        *           SkGeDrvEvent(), because it is timer
15779 -        *           guarded now
15780 -        *
15781 -       ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE);
15782 -        */
15783
15784         /* IRQ is processed - Enable IRQs again*/
15785         SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
15786
15787 -               return SkIsrRetHandled;
15788 +       return SkIsrRetHandled;
15789  } /* SkGeIsrOnePort */
15790
15791 -#ifdef CONFIG_NET_POLL_CONTROLLER
15792 -/****************************************************************************
15793 - *
15794 - *     SkGePollController - polling receive, for netconsole
15795 - *
15796 - * Description:
15797 - *     Polling receive - used by netconsole and other diagnostic tools
15798 - *     to allow network i/o with interrupts disabled.
15799 - *
15800 - * Returns: N/A
15801 - */
15802 -static void SkGePollController(struct net_device *dev)
15803 -{
15804 -       disable_irq(dev->irq);
15805 -       SkGeIsr(dev->irq, dev);
15806 -       enable_irq(dev->irq);
15807 -}
15808 -#endif
15809 -
15810  /****************************************************************************
15811   *
15812   *     SkGeOpen - handle start of initialized adapter
15813 @@ -1162,27 +2208,27 @@
15814   *     != 0 on error
15815   */
15816  static int SkGeOpen(
15817 -struct SK_NET_DEVICE   *dev)
15818 +struct SK_NET_DEVICE *dev)  /* the device that is to be opened */
15819  {
15820 -       DEV_NET                 *pNet;
15821 -       SK_AC                   *pAC;
15822 -       unsigned long   Flags;          /* for spin lock */
15823 -       int                             i;
15824 -       SK_EVPARA               EvPara;         /* an event parameter union */
15825 +       DEV_NET        *pNet = (DEV_NET*) dev->priv;
15826 +       SK_AC          *pAC  = pNet->pAC;
15827 +       unsigned long   Flags;          /* for the spin locks   */
15828 +       unsigned long   InitFlags;      /* for the spin locks   */
15829 +       int             CurrMac;        /* loop ctr for ports   */
15830
15831 -       pNet = netdev_priv(dev);
15832 -       pAC = pNet->pAC;
15833 -
15834         SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
15835                 ("SkGeOpen: pAC=0x%lX:\n", (unsigned long)pAC));
15836 +       spin_lock_irqsave(&pAC->InitLock, InitFlags);
15837
15838 -#ifdef SK_DIAG_SUPPORT
15839         if (pAC->DiagModeActive == DIAG_ACTIVE) {
15840                 if (pAC->Pnmi.DiagAttached == SK_DIAG_RUNNING) {
15841                         return (-1);   /* still in use by diag; deny actions */
15842                 }
15843         }
15844 -#endif
15845 +
15846 +       if (!try_module_get(THIS_MODULE)) {
15847 +               return (-1);    /* increase of usage count not possible */
15848 +       }
15849
15850         /* Set blink mode */
15851         if ((pAC->PciDev->vendor == 0x1186) || (pAC->PciDev->vendor == 0x11ab ))
15852 @@ -1191,6 +2237,7 @@
15853         if (pAC->BoardLevel == SK_INIT_DATA) {
15854                 /* level 1 init common modules here */
15855                 if (SkGeInit(pAC, pAC->IoBase, SK_INIT_IO) != 0) {
15856 +                       module_put(THIS_MODULE); /* decrease usage count */
15857                         printk("%s: HWInit (1) failed.\n", pAC->dev[pNet->PortNr]->name);
15858                         return (-1);
15859                 }
15860 @@ -1201,11 +2248,17 @@
15861                 SkRlmtInit      (pAC, pAC->IoBase, SK_INIT_IO);
15862                 SkTimerInit     (pAC, pAC->IoBase, SK_INIT_IO);
15863                 pAC->BoardLevel = SK_INIT_IO;
15864 +#ifdef Y2_RECOVERY
15865 +               /* mark entries invalid */
15866 +               pAC->LastPort = 3;
15867 +               pAC->LastOpc = 0xFF;
15868 +#endif
15869         }
15870
15871         if (pAC->BoardLevel != SK_INIT_RUN) {
15872                 /* tschilling: Level 2 init modules here, check return value. */
15873                 if (SkGeInit(pAC, pAC->IoBase, SK_INIT_RUN) != 0) {
15874 +                       module_put(THIS_MODULE); /* decrease usage count */
15875                         printk("%s: HWInit (2) failed.\n", pAC->dev[pNet->PortNr]->name);
15876                         return (-1);
15877                 }
15878 @@ -1218,44 +2271,62 @@
15879                 pAC->BoardLevel = SK_INIT_RUN;
15880         }
15881
15882 -       for (i=0; i<pAC->GIni.GIMacsFound; i++) {
15883 -               /* Enable transmit descriptor polling. */
15884 -               SkGePollTxD(pAC, pAC->IoBase, i, SK_TRUE);
15885 -               FillRxRing(pAC, &pAC->RxPort[i]);
15886 +       for (CurrMac=0; CurrMac<pAC->GIni.GIMacsFound; CurrMac++) {
15887 +               if (!CHIP_ID_YUKON_2(pAC)) {
15888 +                       /* Enable transmit descriptor polling. */
15889 +                       SkGePollTxD(pAC, pAC->IoBase, CurrMac, SK_TRUE);
15890 +                       FillRxRing(pAC, &pAC->RxPort[CurrMac]);
15891 +                       SkMacRxTxEnable(pAC, pAC->IoBase, pNet->PortNr);
15892 +               }
15893         }
15894 -       SkGeYellowLED(pAC, pAC->IoBase, 1);
15895
15896 -       StartDrvCleanupTimer(pAC);
15897 +       SkGeYellowLED(pAC, pAC->IoBase, 1);
15898         SkDimEnableModerationIfNeeded(pAC);
15899 -       SkDimDisplayModerationSettings(pAC);
15900 -
15901 -       pAC->GIni.GIValIrqMask &= IRQ_MASK;
15902
15903 -       /* enable Interrupts */
15904 -       SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
15905 -       SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK);
15906 +       if (!CHIP_ID_YUKON_2(pAC)) {
15907 +               /*
15908 +               ** Has been setup already at SkGeInit(SK_INIT_IO),
15909 +               ** but additional masking added for Genesis & Yukon
15910 +               ** chipsets -> modify it...
15911 +               */
15912 +               pAC->GIni.GIValIrqMask &= IRQ_MASK;
15913 +#ifndef USE_TX_COMPLETE
15914 +               pAC->GIni.GIValIrqMask &= ~(TX_COMPL_IRQS);
15915 +#endif
15916 +       }
15917
15918         spin_lock_irqsave(&pAC->SlowPathLock, Flags);
15919
15920         if ((pAC->RlmtMode != 0) && (pAC->MaxPorts == 0)) {
15921 -               EvPara.Para32[0] = pAC->RlmtNets;
15922 -               EvPara.Para32[1] = -1;
15923 -               SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_SET_NETS,
15924 -                       EvPara);
15925 -               EvPara.Para32[0] = pAC->RlmtMode;
15926 -               EvPara.Para32[1] = 0;
15927 -               SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_MODE_CHANGE,
15928 -                       EvPara);
15929 +               SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_SET_NETS,
15930 +                                       pAC->RlmtNets, -1, SK_FALSE);
15931 +               SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_MODE_CHANGE,
15932 +                                       pAC->RlmtMode, 0, SK_FALSE);
15933         }
15934
15935 -       EvPara.Para32[0] = pNet->NetNr;
15936 -       EvPara.Para32[1] = -1;
15937 -       SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara);
15938 -       SkEventDispatcher(pAC, pAC->IoBase);
15939 +       SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_START,
15940 +                               pNet->NetNr, -1, SK_TRUE);
15941         spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
15942
15943 -       pAC->MaxPorts++;
15944 +#ifdef Y2_RECOVERY
15945 +       pNet->TimerExpired = SK_FALSE;
15946 +       pNet->InRecover = SK_FALSE;
15947 +       pNet->NetConsoleMode = SK_FALSE;
15948 +
15949 +       /* Initialize the kernel timer */
15950 +       init_timer(&pNet->KernelTimer);
15951 +       pNet->KernelTimer.function      = SkGeHandleKernelTimer;
15952 +       pNet->KernelTimer.data          = (unsigned long) pNet;
15953 +       pNet->KernelTimer.expires       = jiffies + (HZ/4); /* initially 250ms */
15954 +       add_timer(&pNet->KernelTimer);
15955 +#endif
15956 +
15957 +       /* enable Interrupts */
15958 +       SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
15959 +       SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK);
15960
15961 +       pAC->MaxPorts++;
15962 +       spin_unlock_irqrestore(&pAC->InitLock, InitFlags);
15963
15964         SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
15965                 ("SkGeOpen suceeded\n"));
15966 @@ -1276,32 +2347,37 @@
15967   *     error code - on error
15968   */
15969  static int SkGeClose(
15970 -struct SK_NET_DEVICE   *dev)
15971 +struct SK_NET_DEVICE *dev)  /* the device that is to be closed */
15972  {
15973 -       DEV_NET         *pNet;
15974 -       DEV_NET         *newPtrNet;
15975 -       SK_AC           *pAC;
15976 -
15977 -       unsigned long   Flags;          /* for spin lock */
15978 -       int             i;
15979 -       int             PortIdx;
15980 -       SK_EVPARA       EvPara;
15981 -
15982 +       DEV_NET         *pNet = (DEV_NET*) dev->priv;
15983 +       SK_AC           *pAC  = pNet->pAC;
15984 +       DEV_NET         *newPtrNet;
15985 +       unsigned long    Flags;         /* for the spin locks           */
15986 +       unsigned long    InitFlags;     /* for the spin locks           */
15987 +       int              CurrMac;       /* loop ctr for the current MAC */
15988 +       int              PortIdx;
15989 +#ifdef CONFIG_SK98LIN_NAPI
15990 +       int              WorkToDo = 1; /* min(*budget, dev->quota);    */
15991 +       int              WorkDone = 0;
15992 +#endif
15993         SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
15994                 ("SkGeClose: pAC=0x%lX ", (unsigned long)pAC));
15995 +       spin_lock_irqsave(&pAC->InitLock, InitFlags);
15996
15997 -       pNet = netdev_priv(dev);
15998 -       pAC = pNet->pAC;
15999 +#ifdef Y2_RECOVERY
16000 +       pNet->InRecover = SK_TRUE;
16001 +       del_timer(&pNet->KernelTimer);
16002 +#endif
16003
16004 -#ifdef SK_DIAG_SUPPORT
16005         if (pAC->DiagModeActive == DIAG_ACTIVE) {
16006                 if (pAC->DiagFlowCtrl == SK_FALSE) {
16007 +                       module_put(THIS_MODULE);
16008                         /*
16009                         ** notify that the interface which has been closed
16010                         ** by operator interaction must not be started up
16011                         ** again when the DIAG has finished.
16012                         */
16013 -                       newPtrNet = netdev_priv(pAC->dev[0]);
16014 +                       newPtrNet = (DEV_NET *) pAC->dev[0]->priv;
16015                         if (newPtrNet == pNet) {
16016                                 pAC->WasIfUp[0] = SK_FALSE;
16017                         } else {
16018 @@ -1312,7 +2388,6 @@
16019                         pAC->DiagFlowCtrl = SK_FALSE;
16020                 }
16021         }
16022 -#endif
16023
16024         netif_stop_queue(dev);
16025
16026 @@ -1321,8 +2396,6 @@
16027         else
16028                 PortIdx = pNet->NetNr;
16029
16030 -        StopDrvCleanupTimer(pAC);
16031 -
16032         /*
16033          * Clear multicast table, promiscuous mode ....
16034          */
16035 @@ -1334,46 +2407,101 @@
16036                 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
16037                 /* disable interrupts */
16038                 SK_OUT32(pAC->IoBase, B0_IMSK, 0);
16039 -               EvPara.Para32[0] = pNet->NetNr;
16040 -               EvPara.Para32[1] = -1;
16041 -               SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
16042 -               SkEventDispatcher(pAC, pAC->IoBase);
16043 +               SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP,
16044 +                                       pNet->NetNr, -1, SK_TRUE);
16045                 SK_OUT32(pAC->IoBase, B0_IMSK, 0);
16046                 /* stop the hardware */
16047 -               SkGeDeInit(pAC, pAC->IoBase);
16048 -               pAC->BoardLevel = SK_INIT_DATA;
16049 +
16050 +
16051 +               if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 1)) {
16052 +               /* RLMT check link state mode */
16053 +                       for (CurrMac=0; CurrMac<pAC->GIni.GIMacsFound; CurrMac++) {
16054 +                               if (CHIP_ID_YUKON_2(pAC))
16055 +                                       SkY2PortStop(   pAC,
16056 +                                                       pAC->IoBase,
16057 +                                                       CurrMac,
16058 +                                                       SK_STOP_ALL,
16059 +                                                       SK_HARD_RST);
16060 +                               else
16061 +                                       SkGeStopPort(   pAC,
16062 +                                                       pAC->IoBase,
16063 +                                                       CurrMac,
16064 +                                                       SK_STOP_ALL,
16065 +                                                       SK_HARD_RST);
16066 +                       } /* for */
16067 +               } else {
16068 +               /* Single link or single port */
16069 +                       if (CHIP_ID_YUKON_2(pAC))
16070 +                               SkY2PortStop(   pAC,
16071 +                                               pAC->IoBase,
16072 +                                               PortIdx,
16073 +                                               SK_STOP_ALL,
16074 +                                               SK_HARD_RST);
16075 +                       else
16076 +                               SkGeStopPort(   pAC,
16077 +                                               pAC->IoBase,
16078 +                                               PortIdx,
16079 +                                               SK_STOP_ALL,
16080 +                                               SK_HARD_RST);
16081 +               }
16082                 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
16083         } else {
16084 -
16085                 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
16086 -               EvPara.Para32[0] = pNet->NetNr;
16087 -               EvPara.Para32[1] = -1;
16088 -               SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
16089 -               SkPnmiEvent(pAC, pAC->IoBase, SK_PNMI_EVT_XMAC_RESET, EvPara);
16090 -               SkEventDispatcher(pAC, pAC->IoBase);
16091 +               SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP,
16092 +                                       pNet->NetNr, -1, SK_FALSE);
16093 +               SkLocalEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET,
16094 +                                       pNet->NetNr, -1, SK_TRUE);
16095                 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
16096
16097                 /* Stop port */
16098                 spin_lock_irqsave(&pAC->TxPort[pNet->PortNr]
16099                         [TX_PRIO_LOW].TxDesRingLock, Flags);
16100 -               SkGeStopPort(pAC, pAC->IoBase, pNet->PortNr,
16101 -                       SK_STOP_ALL, SK_HARD_RST);
16102 +               if (CHIP_ID_YUKON_2(pAC)) {
16103 +                       SkY2PortStop(pAC, pAC->IoBase, pNet->PortNr,
16104 +                               SK_STOP_ALL, SK_HARD_RST);
16105 +               }
16106 +               else {
16107 +                       SkGeStopPort(pAC, pAC->IoBase, pNet->PortNr,
16108 +                               SK_STOP_ALL, SK_HARD_RST);
16109 +               }
16110                 spin_unlock_irqrestore(&pAC->TxPort[pNet->PortNr]
16111                         [TX_PRIO_LOW].TxDesRingLock, Flags);
16112         }
16113
16114         if (pAC->RlmtNets == 1) {
16115                 /* clear all descriptor rings */
16116 -               for (i=0; i<pAC->GIni.GIMacsFound; i++) {
16117 -                       ReceiveIrq(pAC, &pAC->RxPort[i], SK_TRUE);
16118 -                       ClearRxRing(pAC, &pAC->RxPort[i]);
16119 -                       ClearTxRing(pAC, &pAC->TxPort[i][TX_PRIO_LOW]);
16120 +               for (CurrMac=0; CurrMac<pAC->GIni.GIMacsFound; CurrMac++) {
16121 +                       if (!CHIP_ID_YUKON_2(pAC)) {
16122 +#ifdef CONFIG_SK98LIN_NAPI
16123 +                               WorkToDo = 1;
16124 +                               ReceiveIrq(pAC,&pAC->RxPort[CurrMac],
16125 +                                               SK_TRUE,&WorkDone,WorkToDo);
16126 +#else
16127 +                               ReceiveIrq(pAC,&pAC->RxPort[CurrMac],SK_TRUE);
16128 +#endif
16129 +                               ClearRxRing(pAC, &pAC->RxPort[CurrMac]);
16130 +                               ClearTxRing(pAC, &pAC->TxPort[CurrMac][TX_PRIO_LOW]);
16131 +                       } else {
16132 +                               SkY2FreeRxBuffers(pAC, pAC->IoBase, CurrMac);
16133 +                               SkY2FreeTxBuffers(pAC, pAC->IoBase, CurrMac);
16134 +                       }
16135                 }
16136         } else {
16137                 /* clear port descriptor rings */
16138 -               ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE);
16139 -               ClearRxRing(pAC, &pAC->RxPort[pNet->PortNr]);
16140 -               ClearTxRing(pAC, &pAC->TxPort[pNet->PortNr][TX_PRIO_LOW]);
16141 +               if (!CHIP_ID_YUKON_2(pAC)) {
16142 +#ifdef CONFIG_SK98LIN_NAPI
16143 +                       WorkToDo = 1;
16144 +                       ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE, &WorkDone, WorkToDo);
16145 +#else
16146 +                       ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE);
16147 +#endif
16148 +                       ClearRxRing(pAC, &pAC->RxPort[pNet->PortNr]);
16149 +                       ClearTxRing(pAC, &pAC->TxPort[pNet->PortNr][TX_PRIO_LOW]);
16150 +               }
16151 +               else {
16152 +                       SkY2FreeRxBuffers(pAC, pAC->IoBase, pNet->PortNr);
16153 +                       SkY2FreeTxBuffers(pAC, pAC->IoBase, pNet->PortNr);
16154 +               }
16155         }
16156
16157         SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
16158 @@ -1384,6 +2512,12 @@
16159                         sizeof(SK_PNMI_STRUCT_DATA));
16160
16161         pAC->MaxPorts--;
16162 +       module_put(THIS_MODULE);
16163 +
16164 +#ifdef Y2_RECOVERY
16165 +       pNet->InRecover = SK_FALSE;
16166 +#endif
16167 +       spin_unlock_irqrestore(&pAC->InitLock, InitFlags);
16168
16169         return (0);
16170  } /* SkGeClose */
16171 @@ -1410,7 +2544,7 @@
16172  SK_AC          *pAC;
16173  int                    Rc;     /* return code of XmitFrame */
16174
16175 -       pNet = netdev_priv(dev);
16176 +       pNet = (DEV_NET*) dev->priv;
16177         pAC = pNet->pAC;
16178
16179         if ((!skb_shinfo(skb)->nr_frags) ||
16180 @@ -1456,6 +2590,96 @@
16181         return (0);
16182  } /* SkGeXmit */
16183
16184 +#ifdef CONFIG_SK98LIN_NAPI
16185 +/*****************************************************************************
16186 + *
16187 + *     SkGePoll - NAPI Rx polling callback for GEnesis and Yukon chipsets
16188 + *
16189 + * Description:
16190 + *     Called by the Linux system in case NAPI polling is activated
16191 + *
16192 + * Returns:
16193 + *     The number of work data still to be handled
16194 + */
16195 +static int SkGePoll(struct net_device *dev, int *budget)
16196 +{
16197 +       SK_AC           *pAC = ((DEV_NET*)(dev->priv))->pAC; /* pointer to adapter context */
16198 +       int             WorkToDo = min(*budget, dev->quota);
16199 +       int             WorkDone = 0;
16200 +       unsigned long   Flags;
16201 +
16202 +
16203 +       if (pAC->dev[0] != pAC->dev[1]) {
16204 +               spin_lock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock);
16205 +               FreeTxDescriptors(pAC, &pAC->TxPort[1][TX_PRIO_LOW]);
16206 +               spin_unlock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock);
16207 +
16208 +               ReceiveIrq(pAC, &pAC->RxPort[1], SK_TRUE, &WorkDone, WorkToDo);
16209 +               CLEAR_AND_START_RX(1);
16210 +       }
16211 +       spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
16212 +       FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]);
16213 +       spin_unlock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
16214 +
16215 +       ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE, &WorkDone, WorkToDo);
16216 +       CLEAR_AND_START_RX(0);
16217 +
16218 +       *budget -= WorkDone;
16219 +       dev->quota -= WorkDone;
16220 +
16221 +       if(WorkDone < WorkToDo) {
16222 +               spin_lock_irqsave(&pAC->SlowPathLock, Flags);
16223 +               netif_rx_complete(dev);
16224 +               pAC->GIni.GIValIrqMask |= (NAPI_DRV_IRQS);
16225 +#ifndef USE_TX_COMPLETE
16226 +               pAC->GIni.GIValIrqMask &= ~(TX_COMPL_IRQS);
16227 +#endif
16228 +               /* enable interrupts again */
16229 +               SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
16230 +               spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
16231 +       }
16232 +       return (WorkDone >= WorkToDo);
16233 +} /* SkGePoll */
16234 +#endif
16235 +
16236 +#ifdef SK_POLL_CONTROLLER
16237 +/*****************************************************************************
16238 + *
16239 + *     SkGeNetPoll - Polling "interrupt"
16240 + *
16241 + * Description:
16242 + *     Polling 'interrupt' - used by things like netconsole and netdump
16243 + *     to send skbs without having to re-enable interrupts.
16244 + *     It's not called while the interrupt routine is executing.
16245 + */
16246 +static void SkGeNetPoll(
16247 +struct SK_NET_DEVICE *dev)
16248 +{
16249 +DEV_NET                *pNet;
16250 +SK_AC          *pAC;
16251 +
16252 +       pNet = (DEV_NET*) dev->priv;
16253 +       pAC = pNet->pAC;
16254 +       pNet->NetConsoleMode = SK_TRUE;
16255 +
16256 +               /*  Prevent any reconfiguration while handling
16257 +                   the 'interrupt' */
16258 +               SK_OUT32(pAC->IoBase, B0_IMSK, 0);
16259 +
16260 +               if (!CHIP_ID_YUKON_2(pAC)) {
16261 +               /* Handle the GENESIS Isr */
16262 +                       if (pAC->GIni.GIMacsFound == 2)
16263 +                               SkGeIsr(dev->irq, dev);
16264 +                       else
16265 +                               SkGeIsrOnePort(dev->irq, dev);
16266 +               } else {
16267 +               /* Handle the Yukon2 Isr */
16268 +                       SkY2Isr(dev->irq, dev);
16269 +               }
16270 +
16271 +}
16272 +#endif
16273 +
16274
16275  /*****************************************************************************
16276   *
16277 @@ -1480,7 +2704,7 @@
16278   *     < 0 - on failure: other problems ( -> return failure to upper layers)
16279   */
16280  static int XmitFrame(
16281 -SK_AC          *pAC,           /* pointer to adapter context           */
16282 +SK_AC          *pAC,           /* pointer to adapter context           */
16283  TX_PORT                *pTxPort,       /* pointer to struct of port to send to */
16284  struct sk_buff *pMessage)      /* pointer to send-message              */
16285  {
16286 @@ -1488,17 +2712,22 @@
16287         TXD             *pOldTxd;
16288         unsigned long    Flags;
16289         SK_U64           PhysAddr;
16290 +       int              Protocol;
16291 +       int              IpHeaderLength;
16292         int              BytesSend = pMessage->len;
16293
16294         SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, ("X"));
16295
16296         spin_lock_irqsave(&pTxPort->TxDesRingLock, Flags);
16297  #ifndef USE_TX_COMPLETE
16298 -       FreeTxDescriptors(pAC, pTxPort);
16299 +       if ((pTxPort->TxdRingPrevFree - pTxPort->TxdRingFree) > 6)  {
16300 +               FreeTxDescriptors(pAC, pTxPort);
16301 +               pTxPort->TxdRingPrevFree = pTxPort->TxdRingFree;
16302 +       }
16303  #endif
16304         if (pTxPort->TxdRingFree == 0) {
16305                 /*
16306 -               ** no enough free descriptors in ring at the moment.
16307 +               ** not enough free descriptors in ring at the moment.
16308                 ** Maybe free'ing some old one help?
16309                 */
16310                 FreeTxDescriptors(pAC, pTxPort);
16311 @@ -1525,7 +2754,7 @@
16312         ** This is to resolve faulty padding by the HW with 0xaa bytes.
16313         */
16314         if (BytesSend < C_LEN_ETHERNET_MINSIZE) {
16315 -               if (skb_padto(pMessage, C_LEN_ETHERNET_MINSIZE)) {
16316 +               if ((pMessage = skb_padto(pMessage, C_LEN_ETHERNET_MINSIZE)) == NULL) {
16317                         spin_unlock_irqrestore(&pTxPort->TxDesRingLock, Flags);
16318                         return 0;
16319                 }
16320 @@ -1560,10 +2789,8 @@
16321         pTxd->pMBuf     = pMessage;
16322
16323         if (pMessage->ip_summed == CHECKSUM_PARTIAL) {
16324 -               u16 hdrlen = pMessage->h.raw - pMessage->data;
16325 -               u16 offset = hdrlen + pMessage->csum;
16326 -
16327 -               if ((pMessage->h.ipiph->protocol == IPPROTO_UDP ) &&
16328 +               Protocol = ((SK_U8)pMessage->data[C_OFFSET_IPPROTO] & 0xff);
16329 +               if ((Protocol == C_PROTO_ID_UDP) &&
16330                         (pAC->GIni.GIChipRev == 0) &&
16331                         (pAC->GIni.GIChipId == CHIP_ID_YUKON)) {
16332                         pTxd->TBControl = BMU_TCP_CHECK;
16333 @@ -1571,9 +2798,14 @@
16334                         pTxd->TBControl = BMU_UDP_CHECK;
16335                 }
16336
16337 -               pTxd->TcpSumOfs = 0;
16338 -               pTxd->TcpSumSt  = hdrlen;
16339 -               pTxd->TcpSumWr  = offset;
16340 +               IpHeaderLength  = (SK_U8)pMessage->data[C_OFFSET_IPHEADER];
16341 +               IpHeaderLength  = (IpHeaderLength & 0xf) * 4;
16342 +               pTxd->TcpSumOfs = 0; /* PH-Checksum already calculated */
16343 +               pTxd->TcpSumSt  = C_LEN_ETHERMAC_HEADER + IpHeaderLength +
16344 +                                                       (Protocol == C_PROTO_ID_UDP ?
16345 +                                                       C_OFFSET_UDPHEADER_UDPCS :
16346 +                                                       C_OFFSET_TCPHEADER_TCPCS);
16347 +               pTxd->TcpSumWr  = C_LEN_ETHERMAC_HEADER + IpHeaderLength;
16348
16349                 pTxd->TBControl |= BMU_OWN | BMU_STF |
16350                                    BMU_SW  | BMU_EOF |
16351 @@ -1581,7 +2813,7 @@
16352                                    BMU_IRQ_EOF |
16353  #endif
16354                                    pMessage->len;
16355 -        } else {
16356 +       } else {
16357                 pTxd->TBControl = BMU_OWN | BMU_STF | BMU_CHECK |
16358                                   BMU_SW  | BMU_EOF |
16359  #ifdef USE_TX_COMPLETE
16360 @@ -1636,10 +2868,11 @@
16361         TXD             *pTxdLst;
16362         int              CurrFrag;
16363         int              BytesSend;
16364 +       int              IpHeaderLength;
16365 +       int              Protocol;
16366         skb_frag_t      *sk_frag;
16367         SK_U64           PhysAddr;
16368         unsigned long    Flags;
16369 -       SK_U32           Control;
16370
16371         spin_lock_irqsave(&pTxPort->TxDesRingLock, Flags);
16372  #ifndef USE_TX_COMPLETE
16373 @@ -1662,6 +2895,7 @@
16374         pTxdFst   = pTxd;
16375         pTxdLst   = pTxd;
16376         BytesSend = 0;
16377 +       Protocol  = 0;
16378
16379         /*
16380         ** Map the first fragment (header) into the DMA-space
16381 @@ -1679,31 +2913,32 @@
16382         ** Does the HW need to evaluate checksum for TCP or UDP packets?
16383         */
16384         if (pMessage->ip_summed == CHECKSUM_PARTIAL) {
16385 -               u16 hdrlen = pMessage->h.raw - pMessage->data;
16386 -               u16 offset = hdrlen + pMessage->csum;
16387 -
16388 -               Control = BMU_STFWD;
16389 -
16390 +               pTxd->TBControl = BMU_STF | BMU_STFWD | skb_headlen(pMessage);
16391                 /*
16392                 ** We have to use the opcode for tcp here,  because the
16393                 ** opcode for udp is not working in the hardware yet
16394                 ** (Revision 2.0)
16395                 */
16396 -               if ((pMessage->h.ipiph->protocol == IPPROTO_UDP ) &&
16397 +               Protocol = ((SK_U8)pMessage->data[C_OFFSET_IPPROTO] & 0xff);
16398 +               if ((Protocol == C_PROTO_ID_UDP) &&
16399                         (pAC->GIni.GIChipRev == 0) &&
16400                         (pAC->GIni.GIChipId == CHIP_ID_YUKON)) {
16401 -                       Control |= BMU_TCP_CHECK;
16402 +                       pTxd->TBControl |= BMU_TCP_CHECK;
16403                 } else {
16404 -                       Control |= BMU_UDP_CHECK;
16405 +                       pTxd->TBControl |= BMU_UDP_CHECK;
16406                 }
16407
16408 -               pTxd->TcpSumOfs = 0;
16409 -               pTxd->TcpSumSt  = hdrlen;
16410 -               pTxd->TcpSumWr  = offset;
16411 -       } else
16412 -               Control = BMU_CHECK | BMU_SW;
16413 -
16414 -       pTxd->TBControl = BMU_STF | Control | skb_headlen(pMessage);
16415 +               IpHeaderLength  = ((SK_U8)pMessage->data[C_OFFSET_IPHEADER] & 0xf)*4;
16416 +               pTxd->TcpSumOfs = 0; /* PH-Checksum already claculated */
16417 +               pTxd->TcpSumSt  = C_LEN_ETHERMAC_HEADER + IpHeaderLength +
16418 +                                               (Protocol == C_PROTO_ID_UDP ?
16419 +                                               C_OFFSET_UDPHEADER_UDPCS :
16420 +                                               C_OFFSET_TCPHEADER_TCPCS);
16421 +               pTxd->TcpSumWr  = C_LEN_ETHERMAC_HEADER + IpHeaderLength;
16422 +       } else {
16423 +               pTxd->TBControl = BMU_CHECK | BMU_SW | BMU_STF |
16424 +                                       skb_headlen(pMessage);
16425 +       }
16426
16427         pTxd = pTxd->pNextTxd;
16428         pTxPort->TxdRingFree--;
16429 @@ -1727,18 +2962,40 @@
16430                 pTxd->VDataHigh = (SK_U32) (PhysAddr >> 32);
16431                 pTxd->pMBuf     = pMessage;
16432
16433 -               pTxd->TBControl = Control | BMU_OWN | sk_frag->size;
16434 +               /*
16435 +               ** Does the HW need to evaluate checksum for TCP or UDP packets?
16436 +               */
16437 +               if (pMessage->ip_summed == CHECKSUM_PARTIAL) {
16438 +                       pTxd->TBControl = BMU_OWN | BMU_SW | BMU_STFWD;
16439 +                       /*
16440 +                       ** We have to use the opcode for tcp here because the
16441 +                       ** opcode for udp is not working in the hardware yet
16442 +                       ** (revision 2.0)
16443 +                       */
16444 +                       if ((Protocol == C_PROTO_ID_UDP) &&
16445 +                               (pAC->GIni.GIChipRev == 0) &&
16446 +                               (pAC->GIni.GIChipId == CHIP_ID_YUKON)) {
16447 +                               pTxd->TBControl |= BMU_TCP_CHECK;
16448 +                       } else {
16449 +                               pTxd->TBControl |= BMU_UDP_CHECK;
16450 +                       }
16451 +               } else {
16452 +                       pTxd->TBControl = BMU_CHECK | BMU_SW | BMU_OWN;
16453 +               }
16454
16455                 /*
16456                 ** Do we have the last fragment?
16457                 */
16458                 if( (CurrFrag+1) == skb_shinfo(pMessage)->nr_frags )  {
16459  #ifdef USE_TX_COMPLETE
16460 -                       pTxd->TBControl |= BMU_EOF | BMU_IRQ_EOF;
16461 +                       pTxd->TBControl |= BMU_EOF | BMU_IRQ_EOF | sk_frag->size;
16462  #else
16463 -                       pTxd->TBControl |= BMU_EOF;
16464 +                       pTxd->TBControl |= BMU_EOF | sk_frag->size;
16465  #endif
16466                         pTxdFst->TBControl |= BMU_OWN | BMU_SW;
16467 +
16468 +               } else {
16469 +                       pTxd->TBControl |= sk_frag->size;
16470                 }
16471                 pTxdLst = pTxd;
16472                 pTxd    = pTxd->pNextTxd;
16473 @@ -1892,7 +3149,7 @@
16474  SK_U16         Length;         /* data fragment length */
16475  SK_U64         PhysAddr;       /* physical address of a rx buffer */
16476
16477 -       pMsgBlock = alloc_skb(pAC->RxBufSize, GFP_ATOMIC);
16478 +       pMsgBlock = alloc_skb(pRxPort->RxBufSize, GFP_ATOMIC);
16479         if (pMsgBlock == NULL) {
16480                 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
16481                         SK_DBGCAT_DRV_ENTRY,
16482 @@ -1906,12 +3163,12 @@
16483         pRxd = pRxPort->pRxdRingTail;
16484         pRxPort->pRxdRingTail = pRxd->pNextRxd;
16485         pRxPort->RxdRingFree--;
16486 -       Length = pAC->RxBufSize;
16487 +       Length = pRxPort->RxBufSize;
16488         PhysAddr = (SK_U64) pci_map_page(pAC->PciDev,
16489                 virt_to_page(pMsgBlock->data),
16490                 ((unsigned long) pMsgBlock->data &
16491                 ~PAGE_MASK),
16492 -               pAC->RxBufSize - 2,
16493 +               pRxPort->RxBufSize - 2,
16494                 PCI_DMA_FROMDEVICE);
16495
16496         pRxd->VDataLow  = (SK_U32) (PhysAddr & 0xffffffff);
16497 @@ -1951,7 +3208,7 @@
16498         pRxd = pRxPort->pRxdRingTail;
16499         pRxPort->pRxdRingTail = pRxd->pNextRxd;
16500         pRxPort->RxdRingFree--;
16501 -       Length = pAC->RxBufSize;
16502 +       Length = pRxPort->RxBufSize;
16503
16504         pRxd->VDataLow  = PhysLow;
16505         pRxd->VDataHigh = PhysHigh;
16506 @@ -1976,28 +3233,40 @@
16507   * Returns:    N/A
16508   */
16509  static void ReceiveIrq(
16510 -       SK_AC           *pAC,                   /* pointer to adapter context */
16511 -       RX_PORT         *pRxPort,               /* pointer to receive port struct */
16512 -       SK_BOOL         SlowPathLock)   /* indicates if SlowPathLock is needed */
16513 -{
16514 -RXD                            *pRxd;                  /* pointer to receive descriptors */
16515 -SK_U32                 Control;                /* control field of descriptor */
16516 -struct sk_buff *pMsg;                  /* pointer to message holding frame */
16517 -struct sk_buff *pNewMsg;               /* pointer to a new message for copying frame */
16518 -int                            FrameLength;    /* total length of received frame */
16519 -SK_MBUF                        *pRlmtMbuf;             /* ptr to a buffer for giving a frame to rlmt */
16520 -SK_EVPARA              EvPara;                 /* an event parameter union */
16521 -unsigned long  Flags;                  /* for spin lock */
16522 -int                            PortIndex = pRxPort->PortIndex;
16523 -unsigned int   Offset;
16524 -unsigned int   NumBytes;
16525 -unsigned int   ForRlmt;
16526 -SK_BOOL                        IsBc;
16527 -SK_BOOL                        IsMc;
16528 -SK_BOOL  IsBadFrame;                   /* Bad frame */
16529 -
16530 -SK_U32                 FrameStat;
16531 -SK_U64                 PhysAddr;
16532 +#ifdef CONFIG_SK98LIN_NAPI
16533 +SK_AC    *pAC,          /* pointer to adapter context          */
16534 +RX_PORT  *pRxPort,      /* pointer to receive port struct      */
16535 +SK_BOOL   SlowPathLock, /* indicates if SlowPathLock is needed */
16536 +int      *WorkDone,
16537 +int       WorkToDo)
16538 +#else
16539 +SK_AC    *pAC,          /* pointer to adapter context          */
16540 +RX_PORT  *pRxPort,      /* pointer to receive port struct      */
16541 +SK_BOOL   SlowPathLock) /* indicates if SlowPathLock is needed */
16542 +#endif
16543 +{
16544 +       RXD             *pRxd;          /* pointer to receive descriptors         */
16545 +       struct sk_buff  *pMsg;          /* pointer to message holding frame       */
16546 +       struct sk_buff  *pNewMsg;       /* pointer to new message for frame copy  */
16547 +       SK_MBUF         *pRlmtMbuf;     /* ptr to buffer for giving frame to RLMT */
16548 +       SK_EVPARA        EvPara;        /* an event parameter union        */
16549 +       SK_U32           Control;       /* control field of descriptor     */
16550 +       unsigned long    Flags;         /* for spin lock handling          */
16551 +       int              PortIndex = pRxPort->PortIndex;
16552 +       int              FrameLength;   /* total length of received frame  */
16553 +       int              IpFrameLength; /* IP length of the received frame */
16554 +       unsigned int     Offset;
16555 +       unsigned int     NumBytes;
16556 +       unsigned int     RlmtNotifier;
16557 +       SK_BOOL          IsBc;          /* we received a broadcast packet  */
16558 +       SK_BOOL          IsMc;          /* we received a multicast packet  */
16559 +       SK_BOOL          IsBadFrame;    /* the frame received is bad!      */
16560 +       SK_U32           FrameStat;
16561 +       unsigned short   Csum1;
16562 +       unsigned short   Csum2;
16563 +       unsigned short   Type;
16564 +       int              Result;
16565 +       SK_U64           PhysAddr;
16566
16567  rx_start:
16568         /* do forever; exit if BMU_OWN found */
16569 @@ -2019,6 +3288,13 @@
16570
16571                 Control = pRxd->RBControl;
16572
16573 +#ifdef CONFIG_SK98LIN_NAPI
16574 +               if (*WorkDone >= WorkToDo) {
16575 +                       break;
16576 +               }
16577 +               (*WorkDone)++;
16578 +#endif
16579 +
16580                 /* check if this descriptor is ready */
16581                 if ((Control & BMU_OWN) != 0) {
16582                         /* this descriptor is not yet ready */
16583 @@ -2027,11 +3303,10 @@
16584                         FillRxRing(pAC, pRxPort);
16585                         return;
16586                 }
16587 -                pAC->DynIrqModInfo.NbrProcessedDescr++;
16588
16589                 /* get length of frame and check it */
16590                 FrameLength = Control & BMU_BBC;
16591 -               if (FrameLength > pAC->RxBufSize) {
16592 +               if (FrameLength > pRxPort->RxBufSize) {
16593                         goto rx_failed;
16594                 }
16595
16596 @@ -2046,8 +3321,8 @@
16597                 FrameStat = pRxd->FrameStat;
16598
16599                 /* check for frame length mismatch */
16600 -#define XMR_FS_LEN_SHIFT        18
16601 -#define GMR_FS_LEN_SHIFT        16
16602 +#define XMR_FS_LEN_SHIFT       18
16603 +#define GMR_FS_LEN_SHIFT       16
16604                 if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
16605                         if (FrameLength != (SK_U32) (FrameStat >> XMR_FS_LEN_SHIFT)) {
16606                                 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
16607 @@ -2057,8 +3332,7 @@
16608                                         (SK_U32) (FrameStat >> XMR_FS_LEN_SHIFT)));
16609                                 goto rx_failed;
16610                         }
16611 -               }
16612 -               else {
16613 +               } else {
16614                         if (FrameLength != (SK_U32) (FrameStat >> GMR_FS_LEN_SHIFT)) {
16615                                 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
16616                                         SK_DBGCAT_DRV_RX_PROGRESS,
16617 @@ -2091,9 +3365,6 @@
16618  /* DumpMsg(pMsg, "Rx");        */
16619
16620                 if ((Control & BMU_STAT_VAL) != BMU_STAT_VAL || (IsBadFrame)) {
16621 -#if 0
16622 -                       (FrameStat & (XMR_FS_ANY_ERR | XMR_FS_2L_VLAN)) != 0) {
16623 -#endif
16624                         /* there is a receive error in this frame */
16625                         SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
16626                                 SK_DBGCAT_DRV_RX_PROGRESS,
16627 @@ -2101,6 +3372,20 @@
16628                                 "Control: %x\nRxStat: %x\n",
16629                                 Control, FrameStat));
16630
16631 +                       PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32;
16632 +                       PhysAddr |= (SK_U64) pRxd->VDataLow;
16633 +
16634 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5)
16635 +                       pci_dma_sync_single(pAC->PciDev,
16636 +                                               (dma_addr_t) PhysAddr,
16637 +                                               FrameLength,
16638 +                                               PCI_DMA_FROMDEVICE);
16639 +#else
16640 +                       pci_dma_sync_single_for_cpu(pAC->PciDev,
16641 +                                               (dma_addr_t) PhysAddr,
16642 +                                               FrameLength,
16643 +                                               PCI_DMA_FROMDEVICE);
16644 +#endif
16645                         ReQueueRxBuffer(pAC, pRxPort, pMsg,
16646                                 pRxd->VDataHigh, pRxd->VDataLow);
16647
16648 @@ -2120,96 +3405,107 @@
16649                         skb_put(pNewMsg, FrameLength);
16650                         PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32;
16651                         PhysAddr |= (SK_U64) pRxd->VDataLow;
16652 -
16653 -                       pci_dma_sync_single_for_cpu(pAC->PciDev,
16654 -                                                   (dma_addr_t) PhysAddr,
16655 -                                                   FrameLength,
16656 -                                                   PCI_DMA_FROMDEVICE);
16657 -                       memcpy(pNewMsg->data, pMsg, FrameLength);
16658 -
16659 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5)
16660 +                       pci_dma_sync_single(pAC->PciDev,
16661 +                                               (dma_addr_t) PhysAddr,
16662 +                                               FrameLength,
16663 +                                               PCI_DMA_FROMDEVICE);
16664 +#else
16665                         pci_dma_sync_single_for_device(pAC->PciDev,
16666 -                                                      (dma_addr_t) PhysAddr,
16667 -                                                      FrameLength,
16668 -                                                      PCI_DMA_FROMDEVICE);
16669 +                                               (dma_addr_t) PhysAddr,
16670 +                                               FrameLength,
16671 +                                               PCI_DMA_FROMDEVICE);
16672 +#endif
16673 +
16674 +                       eth_copy_and_sum(pNewMsg, pMsg->data,
16675 +                               FrameLength, 0);
16676                         ReQueueRxBuffer(pAC, pRxPort, pMsg,
16677                                 pRxd->VDataHigh, pRxd->VDataLow);
16678
16679                         pMsg = pNewMsg;
16680
16681 -               }
16682 -               else {
16683 +               } else {
16684                         /*
16685                          * if large frame, or SKB allocation failed, pass
16686                          * the SKB directly to the networking
16687                          */
16688 -
16689                         PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32;
16690                         PhysAddr |= (SK_U64) pRxd->VDataLow;
16691
16692                         /* release the DMA mapping */
16693                         pci_unmap_single(pAC->PciDev,
16694                                          PhysAddr,
16695 -                                        pAC->RxBufSize - 2,
16696 +                                        pRxPort->RxBufSize - 2,
16697                                          PCI_DMA_FROMDEVICE);
16698 +                       skb_put(pMsg, FrameLength); /* set message len */
16699 +                       pMsg->ip_summed = CHECKSUM_NONE; /* initial default */
16700
16701 -                       /* set length in message */
16702 -                       skb_put(pMsg, FrameLength);
16703 +                       if (pRxPort->UseRxCsum) {
16704 +                               Type = ntohs(*((short*)&pMsg->data[12]));
16705 +                               if (Type == 0x800) {
16706 +                                       IpFrameLength = (int) ntohs((unsigned short)
16707 +                                                       ((unsigned short *) pMsg->data)[8]);
16708 +                                       if ((FrameLength - IpFrameLength) == 0xe) {
16709 +                                               Csum1=le16_to_cpu(pRxd->TcpSums & 0xffff);
16710 +                                               Csum2=le16_to_cpu((pRxd->TcpSums >> 16) & 0xffff);
16711 +                                               if ((((Csum1 & 0xfffe) && (Csum2 & 0xfffe)) &&
16712 +                                                       (pAC->GIni.GIChipId == CHIP_ID_GENESIS)) ||
16713 +                                                       (pAC->ChipsetType)) {
16714 +                                                       Result = SkCsGetReceiveInfo(pAC, &pMsg->data[14],
16715 +                                                               Csum1, Csum2, PortIndex);
16716 +                                                       if ((Result == SKCS_STATUS_IP_FRAGMENT) ||
16717 +                                                           (Result == SKCS_STATUS_IP_CSUM_OK)  ||
16718 +                                                           (Result == SKCS_STATUS_TCP_CSUM_OK) ||
16719 +                                                           (Result == SKCS_STATUS_UDP_CSUM_OK)) {
16720 +                                                               pMsg->ip_summed = CHECKSUM_UNNECESSARY;
16721 +                                                       } else if ((Result == SKCS_STATUS_TCP_CSUM_ERROR)    ||
16722 +                                                                  (Result == SKCS_STATUS_UDP_CSUM_ERROR)    ||
16723 +                                                                  (Result == SKCS_STATUS_IP_CSUM_ERROR_UDP) ||
16724 +                                                                  (Result == SKCS_STATUS_IP_CSUM_ERROR_TCP) ||
16725 +                                                                  (Result == SKCS_STATUS_IP_CSUM_ERROR)) {
16726 +                                                               /* HW Checksum error */
16727 +                                                               SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
16728 +                                                               SK_DBGCAT_DRV_RX_PROGRESS,
16729 +                                                               ("skge: CRC error. Frame dropped!\n"));
16730 +                                                               goto rx_failed;
16731 +                                                       } else {
16732 +                                                               pMsg->ip_summed = CHECKSUM_NONE;
16733 +                                                       }
16734 +                                               }/* checksumControl calculation valid */
16735 +                                       } /* Frame length check */
16736 +                               } /* IP frame */
16737 +                       } /* pRxPort->UseRxCsum */
16738                 } /* frame > SK_COPY_TRESHOLD */
16739 -
16740 -#ifdef USE_SK_RX_CHECKSUM
16741 -               pMsg->csum = pRxd->TcpSums & 0xffff;
16742 -               pMsg->ip_summed = CHECKSUM_COMPLETE;
16743 -#else
16744 -               pMsg->ip_summed = CHECKSUM_NONE;
16745 -#endif
16746 -
16747 +
16748                 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("V"));
16749 -               ForRlmt = SK_RLMT_RX_PROTOCOL;
16750 -#if 0
16751 -               IsBc = (FrameStat & XMR_FS_BC)==XMR_FS_BC;
16752 -#endif
16753 +               RlmtNotifier = SK_RLMT_RX_PROTOCOL;
16754                 SK_RLMT_PRE_LOOKAHEAD(pAC, PortIndex, FrameLength,
16755 -                       IsBc, &Offset, &NumBytes);
16756 +                                       IsBc, &Offset, &NumBytes);
16757                 if (NumBytes != 0) {
16758 -#if 0
16759 -                       IsMc = (FrameStat & XMR_FS_MC)==XMR_FS_MC;
16760 -#endif
16761 -                       SK_RLMT_LOOKAHEAD(pAC, PortIndex,
16762 -                               &pMsg->data[Offset],
16763 -                               IsBc, IsMc, &ForRlmt);
16764 +                       SK_RLMT_LOOKAHEAD(pAC,PortIndex,&pMsg->data[Offset],
16765 +                                               IsBc,IsMc,&RlmtNotifier);
16766                 }
16767 -               if (ForRlmt == SK_RLMT_RX_PROTOCOL) {
16768 -                                       SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("W"));
16769 +               if (RlmtNotifier == SK_RLMT_RX_PROTOCOL) {
16770 +                       SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("W"));
16771                         /* send up only frames from active port */
16772 -                       if ((PortIndex == pAC->ActivePort) ||
16773 -                               (pAC->RlmtNets == 2)) {
16774 -                               /* frame for upper layer */
16775 +                       if ((PortIndex == pAC->ActivePort)||(pAC->RlmtNets == 2)) {
16776                                 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("U"));
16777  #ifdef xDEBUG
16778                                 DumpMsg(pMsg, "Rx");
16779  #endif
16780 -                               SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC,
16781 -                                       FrameLength, pRxPort->PortIndex);
16782 -
16783 -                               pMsg->dev = pAC->dev[pRxPort->PortIndex];
16784 -                               pMsg->protocol = eth_type_trans(pMsg,
16785 -                                       pAC->dev[pRxPort->PortIndex]);
16786 -                               netif_rx(pMsg);
16787 -                               pAC->dev[pRxPort->PortIndex]->last_rx = jiffies;
16788 -                       }
16789 -                       else {
16790 -                               /* drop frame */
16791 +                               SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC,FrameLength,PortIndex);
16792 +                               pMsg->dev = pAC->dev[PortIndex];
16793 +                               pMsg->protocol = eth_type_trans(pMsg,pAC->dev[PortIndex]);
16794 +                               netif_rx(pMsg); /* frame for upper layer */
16795 +                               pAC->dev[PortIndex]->last_rx = jiffies;
16796 +                       } else {
16797                                 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
16798 -                                       SK_DBGCAT_DRV_RX_PROGRESS,
16799 -                                       ("D"));
16800 -                               DEV_KFREE_SKB(pMsg);
16801 +                                       SK_DBGCAT_DRV_RX_PROGRESS,("D"));
16802 +                               DEV_KFREE_SKB(pMsg); /* drop frame */
16803                         }
16804 -
16805 -               } /* if not for rlmt */
16806 -               else {
16807 -                       /* packet for rlmt */
16808 +               } else { /* packet for RLMT stack */
16809                         SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
16810 -                               SK_DBGCAT_DRV_RX_PROGRESS, ("R"));
16811 +                               SK_DBGCAT_DRV_RX_PROGRESS,("R"));
16812                         pRlmtMbuf = SkDrvAllocRlmtMbuf(pAC,
16813                                 pAC->IoBase, FrameLength);
16814                         if (pRlmtMbuf != NULL) {
16815 @@ -2237,32 +3533,26 @@
16816                                 }
16817
16818                                 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
16819 -                                       SK_DBGCAT_DRV_RX_PROGRESS,
16820 -                                       ("Q"));
16821 +                                       SK_DBGCAT_DRV_RX_PROGRESS,("Q"));
16822                         }
16823 -                       if ((pAC->dev[pRxPort->PortIndex]->flags &
16824 -                               (IFF_PROMISC | IFF_ALLMULTI)) != 0 ||
16825 -                               (ForRlmt & SK_RLMT_RX_PROTOCOL) ==
16826 -                               SK_RLMT_RX_PROTOCOL) {
16827 -                               pMsg->dev = pAC->dev[pRxPort->PortIndex];
16828 -                               pMsg->protocol = eth_type_trans(pMsg,
16829 -                                       pAC->dev[pRxPort->PortIndex]);
16830 +                       if ((pAC->dev[PortIndex]->flags & (IFF_PROMISC | IFF_ALLMULTI)) ||
16831 +                           (RlmtNotifier & SK_RLMT_RX_PROTOCOL)) {
16832 +                               pMsg->dev = pAC->dev[PortIndex];
16833 +                               pMsg->protocol = eth_type_trans(pMsg,pAC->dev[PortIndex]);
16834 +#ifdef CONFIG_SK98LIN_NAPI
16835 +                               netif_receive_skb(pMsg);
16836 +#else
16837                                 netif_rx(pMsg);
16838 -                               pAC->dev[pRxPort->PortIndex]->last_rx = jiffies;
16839 -                       }
16840 -                       else {
16841 +#endif
16842 +                               pAC->dev[PortIndex]->last_rx = jiffies;
16843 +                       } else {
16844                                 DEV_KFREE_SKB(pMsg);
16845                         }
16846 -
16847 -               } /* if packet for rlmt */
16848 +               } /* if packet for RLMT stack */
16849         } /* for ... scanning the RXD ring */
16850
16851         /* RXD ring is empty -> fill and restart */
16852         FillRxRing(pAC, pRxPort);
16853 -       /* do not start if called from Close */
16854 -       if (pAC->BoardLevel > SK_INIT_DATA) {
16855 -               ClearAndStartRx(pAC, PortIndex);
16856 -       }
16857         return;
16858
16859  rx_failed:
16860 @@ -2276,7 +3566,7 @@
16861         PhysAddr |= (SK_U64) pRxd->VDataLow;
16862         pci_unmap_page(pAC->PciDev,
16863                          PhysAddr,
16864 -                        pAC->RxBufSize - 2,
16865 +                        pRxPort->RxBufSize - 2,
16866                          PCI_DMA_FROMDEVICE);
16867         DEV_KFREE_SKB_IRQ(pRxd->pMBuf);
16868         pRxd->pMBuf = NULL;
16869 @@ -2286,49 +3576,6 @@
16870
16871  } /* ReceiveIrq */
16872
16873 -
16874 -/*****************************************************************************
16875 - *
16876 - *     ClearAndStartRx - give a start receive command to BMU, clear IRQ
16877 - *
16878 - * Description:
16879 - *     This function sends a start command and a clear interrupt
16880 - *     command for one receive queue to the BMU.
16881 - *
16882 - * Returns: N/A
16883 - *     none
16884 - */
16885 -static void ClearAndStartRx(
16886 -SK_AC  *pAC,           /* pointer to the adapter context */
16887 -int    PortIndex)      /* index of the receive port (XMAC) */
16888 -{
16889 -       SK_OUT8(pAC->IoBase,
16890 -               RxQueueAddr[PortIndex]+Q_CSR,
16891 -               CSR_START | CSR_IRQ_CL_F);
16892 -} /* ClearAndStartRx */
16893 -
16894 -
16895 -/*****************************************************************************
16896 - *
16897 - *     ClearTxIrq - give a clear transmit IRQ command to BMU
16898 - *
16899 - * Description:
16900 - *     This function sends a clear tx IRQ command for one
16901 - *     transmit queue to the BMU.
16902 - *
16903 - * Returns: N/A
16904 - */
16905 -static void ClearTxIrq(
16906 -SK_AC  *pAC,           /* pointer to the adapter context */
16907 -int    PortIndex,      /* index of the transmit port (XMAC) */
16908 -int    Prio)           /* priority or normal queue */
16909 -{
16910 -       SK_OUT8(pAC->IoBase,
16911 -               TxQueueAddr[PortIndex][Prio]+Q_CSR,
16912 -               CSR_IRQ_CL_F);
16913 -} /* ClearTxIrq */
16914 -
16915 -
16916  /*****************************************************************************
16917   *
16918   *     ClearRxRing - remove all buffers from the receive ring
16919 @@ -2359,7 +3606,7 @@
16920                         PhysAddr |= (SK_U64) pRxd->VDataLow;
16921                         pci_unmap_page(pAC->PciDev,
16922                                          PhysAddr,
16923 -                                        pAC->RxBufSize - 2,
16924 +                                        pRxPort->RxBufSize - 2,
16925                                          PCI_DMA_FROMDEVICE);
16926                         DEV_KFREE_SKB(pRxd->pMBuf);
16927                         pRxd->pMBuf = NULL;
16928 @@ -2417,31 +3664,32 @@
16929  static int SkGeSetMacAddr(struct SK_NET_DEVICE *dev, void *p)
16930  {
16931
16932 -DEV_NET *pNet = netdev_priv(dev);
16933 +DEV_NET *pNet = (DEV_NET*) dev->priv;
16934  SK_AC  *pAC = pNet->pAC;
16935 +int    Ret;
16936
16937  struct sockaddr        *addr = p;
16938  unsigned long  Flags;
16939
16940         SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
16941                 ("SkGeSetMacAddr starts now...\n"));
16942 -       if(netif_running(dev))
16943 -               return -EBUSY;
16944
16945         memcpy(dev->dev_addr, addr->sa_data,dev->addr_len);
16946
16947         spin_lock_irqsave(&pAC->SlowPathLock, Flags);
16948
16949         if (pAC->RlmtNets == 2)
16950 -               SkAddrOverride(pAC, pAC->IoBase, pNet->NetNr,
16951 +               Ret = SkAddrOverride(pAC, pAC->IoBase, pNet->NetNr,
16952                         (SK_MAC_ADDR*)dev->dev_addr, SK_ADDR_VIRTUAL_ADDRESS);
16953         else
16954 -               SkAddrOverride(pAC, pAC->IoBase, pAC->ActivePort,
16955 +               Ret = SkAddrOverride(pAC, pAC->IoBase, pAC->ActivePort,
16956                         (SK_MAC_ADDR*)dev->dev_addr, SK_ADDR_VIRTUAL_ADDRESS);
16957 -
16958 -
16959
16960         spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
16961 +
16962 +       if (Ret != SK_ADDR_OVERRIDE_SUCCESS)
16963 +               return -EBUSY;
16964 +
16965         return 0;
16966  } /* SkGeSetMacAddr */
16967
16968 @@ -2474,7 +3722,7 @@
16969         SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
16970                 ("SkGeSetRxMode starts now... "));
16971
16972 -       pNet = netdev_priv(dev);
16973 +       pNet = (DEV_NET*) dev->priv;
16974         pAC = pNet->pAC;
16975         if (pAC->RlmtNets == 1)
16976                 PortIdx = pAC->ActivePort;
16977 @@ -2523,6 +3771,45 @@
16978
16979  /*****************************************************************************
16980   *
16981 + *     SkSetMtuBufferSize - set the MTU buffer to another value
16982 + *
16983 + * Description:
16984 + *     This function sets the new buffers and is called whenever the MTU
16985 + *      size is changed
16986 + *
16987 + * Returns:
16988 + *     N/A
16989 + */
16990 +
16991 +static void SkSetMtuBufferSize(
16992 +SK_AC  *pAC,           /* pointer to adapter context */
16993 +int    PortNr,         /* Port number */
16994 +int    Mtu)            /* pointer to tx prt struct */
16995 +{
16996 +       pAC->RxPort[PortNr].RxBufSize = Mtu + 32;
16997 +
16998 +       /* RxBufSize must be a multiple of 8 */
16999 +       while (pAC->RxPort[PortNr].RxBufSize % 8) {
17000 +               pAC->RxPort[PortNr].RxBufSize =
17001 +                       pAC->RxPort[PortNr].RxBufSize + 1;
17002 +       }
17003 +
17004 +       if (Mtu > 1500) {
17005 +               pAC->GIni.GP[PortNr].PPortUsage = SK_JUMBO_LINK;
17006 +       } else {
17007 +               if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
17008 +                       pAC->GIni.GP[PortNr].PPortUsage = SK_MUL_LINK;
17009 +               } else {
17010 +                       pAC->GIni.GP[PortNr].PPortUsage = SK_RED_LINK;
17011 +               }
17012 +       }
17013 +
17014 +       return;
17015 +}
17016 +
17017 +
17018 +/*****************************************************************************
17019 + *
17020   *     SkGeChangeMtu - set the MTU to another value
17021   *
17022   * Description:
17023 @@ -2536,28 +3823,32 @@
17024   */
17025  static int SkGeChangeMtu(struct SK_NET_DEVICE *dev, int NewMtu)
17026  {
17027 -DEV_NET                *pNet;
17028 -struct net_device *pOtherDev;
17029 -SK_AC          *pAC;
17030 -unsigned long  Flags;
17031 -int            i;
17032 -SK_EVPARA      EvPara;
17033 +DEV_NET                        *pNet;
17034 +SK_AC                  *pAC;
17035 +unsigned long          Flags;
17036 +#ifdef CONFIG_SK98LIN_NAPI
17037 +int                    WorkToDo = 1; // min(*budget, dev->quota);
17038 +int                    WorkDone = 0;
17039 +#endif
17040
17041         SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
17042                 ("SkGeChangeMtu starts now...\n"));
17043
17044 -       pNet = netdev_priv(dev);
17045 +       pNet = (DEV_NET*) dev->priv;
17046         pAC  = pNet->pAC;
17047
17048 +       /* MTU size outside the spec */
17049         if ((NewMtu < 68) || (NewMtu > SK_JUMBO_MTU)) {
17050                 return -EINVAL;
17051         }
17052
17053 -       if(pAC->BoardLevel != SK_INIT_RUN) {
17054 +       /* MTU > 1500 on yukon FE not allowed */
17055 +       if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_FE)
17056 +               && (NewMtu > 1500)){
17057                 return -EINVAL;
17058         }
17059
17060 -#ifdef SK_DIAG_SUPPORT
17061 +       /* Diag access active */
17062         if (pAC->DiagModeActive == DIAG_ACTIVE) {
17063                 if (pAC->DiagFlowCtrl == SK_FALSE) {
17064                         return -1; /* still in use, deny any actions of MTU */
17065 @@ -2565,201 +3856,74 @@
17066                         pAC->DiagFlowCtrl = SK_FALSE;
17067                 }
17068         }
17069 -#endif
17070 -
17071 -       pOtherDev = pAC->dev[1 - pNet->NetNr];
17072 -
17073 -       if ( netif_running(pOtherDev) && (pOtherDev->mtu > 1500)
17074 -            && (NewMtu <= 1500))
17075 -               return 0;
17076
17077 -       pAC->RxBufSize = NewMtu + 32;
17078         dev->mtu = NewMtu;
17079 +       SkSetMtuBufferSize(pAC, pNet->PortNr, NewMtu);
17080
17081 -       SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
17082 -               ("New MTU: %d\n", NewMtu));
17083 +       if(!netif_running(dev)) {
17084 +       /* Preset MTU size if device not ready/running */
17085 +               return 0;
17086 +       }
17087
17088 -       /*
17089 -       ** Prevent any reconfiguration while changing the MTU
17090 -       ** by disabling any interrupts
17091 -       */
17092 +       /*  Prevent any reconfiguration while changing the MTU
17093 +           by disabling any interrupts */
17094         SK_OUT32(pAC->IoBase, B0_IMSK, 0);
17095         spin_lock_irqsave(&pAC->SlowPathLock, Flags);
17096
17097 -       /*
17098 -       ** Notify RLMT that any ports are to be stopped
17099 -       */
17100 -       EvPara.Para32[0] =  0;
17101 -       EvPara.Para32[1] = -1;
17102 -       if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
17103 -               SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
17104 -               EvPara.Para32[0] =  1;
17105 -               SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
17106 -       } else {
17107 -               SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
17108 -       }
17109 -
17110 -       /*
17111 -       ** After calling the SkEventDispatcher(), RLMT is aware about
17112 -       ** the stopped ports -> configuration can take place!
17113 -       */
17114 -       SkEventDispatcher(pAC, pAC->IoBase);
17115 -
17116 -       for (i=0; i<pAC->GIni.GIMacsFound; i++) {
17117 -               spin_lock(&pAC->TxPort[i][TX_PRIO_LOW].TxDesRingLock);
17118 -               netif_stop_queue(pAC->dev[i]);
17119 +       /* Notify RLMT that the port has to be stopped */
17120 +       netif_stop_queue(dev);
17121 +       SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP,
17122 +                               pNet->PortNr, -1, SK_TRUE);
17123 +       spin_lock(&pAC->TxPort[pNet->PortNr][TX_PRIO_LOW].TxDesRingLock);
17124
17125 -       }
17126
17127 -       /*
17128 -       ** Depending on the desired MTU size change, a different number of
17129 -       ** RX buffers need to be allocated
17130 -       */
17131 -       if (NewMtu > 1500) {
17132 -           /*
17133 -           ** Use less rx buffers
17134 -           */
17135 -           for (i=0; i<pAC->GIni.GIMacsFound; i++) {
17136 -               if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
17137 -                   pAC->RxPort[i].RxFillLimit =  pAC->RxDescrPerRing -
17138 -                                                (pAC->RxDescrPerRing / 4);
17139 -               } else {
17140 -                   if (i == pAC->ActivePort) {
17141 -                       pAC->RxPort[i].RxFillLimit = pAC->RxDescrPerRing -
17142 -                                                   (pAC->RxDescrPerRing / 4);
17143 -                   } else {
17144 -                       pAC->RxPort[i].RxFillLimit = pAC->RxDescrPerRing -
17145 -                                                   (pAC->RxDescrPerRing / 10);
17146 -                   }
17147 -               }
17148 -           }
17149 +       /* Change RxFillLimit to 1 */
17150 +       if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
17151 +               pAC->RxPort[pNet->PortNr].RxFillLimit = 1;
17152         } else {
17153 -           /*
17154 -           ** Use the normal amount of rx buffers
17155 -           */
17156 -           for (i=0; i<pAC->GIni.GIMacsFound; i++) {
17157 -               if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
17158 -                   pAC->RxPort[i].RxFillLimit = 1;
17159 -               } else {
17160 -                   if (i == pAC->ActivePort) {
17161 -                       pAC->RxPort[i].RxFillLimit = 1;
17162 -                   } else {
17163 -                       pAC->RxPort[i].RxFillLimit = pAC->RxDescrPerRing -
17164 -                                                   (pAC->RxDescrPerRing / 4);
17165 -                   }
17166 -               }
17167 -           }
17168 +               pAC->RxPort[1 - pNet->PortNr].RxFillLimit = 1;
17169 +               pAC->RxPort[pNet->PortNr].RxFillLimit = pAC->RxDescrPerRing -
17170 +                                       (pAC->RxDescrPerRing / 4);
17171         }
17172 -
17173 -       SkGeDeInit(pAC, pAC->IoBase);
17174
17175 -       /*
17176 -       ** enable/disable hardware support for long frames
17177 -       */
17178 -       if (NewMtu > 1500) {
17179 -// pAC->JumboActivated = SK_TRUE; /* is never set back !!! */
17180 -               pAC->GIni.GIPortUsage = SK_JUMBO_LINK;
17181 +       /* clear and reinit the rx rings here, because of new MTU size */
17182 +       if (CHIP_ID_YUKON_2(pAC)) {
17183 +               SkY2PortStop(pAC, pAC->IoBase, pNet->PortNr, SK_STOP_ALL, SK_SOFT_RST);
17184 +               SkY2AllocateRxBuffers(pAC, pAC->IoBase, pNet->PortNr);
17185 +               SkY2PortStart(pAC, pAC->IoBase, pNet->PortNr);
17186         } else {
17187 -           if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
17188 -               pAC->GIni.GIPortUsage = SK_MUL_LINK;
17189 -           } else {
17190 -               pAC->GIni.GIPortUsage = SK_RED_LINK;
17191 -           }
17192 -       }
17193 +//             SkGeStopPort(pAC, pAC->IoBase, pNet->PortNr, SK_STOP_ALL, SK_SOFT_RST);
17194 +#ifdef CONFIG_SK98LIN_NAPI
17195 +               WorkToDo = 1;
17196 +               ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE, &WorkDone, WorkToDo);
17197 +#else
17198 +               ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE);
17199 +#endif
17200 +               ClearRxRing(pAC, &pAC->RxPort[pNet->PortNr]);
17201 +               FillRxRing(pAC, &pAC->RxPort[pNet->PortNr]);
17202
17203 -       SkGeInit(   pAC, pAC->IoBase, SK_INIT_IO);
17204 -       SkI2cInit(  pAC, pAC->IoBase, SK_INIT_IO);
17205 -       SkEventInit(pAC, pAC->IoBase, SK_INIT_IO);
17206 -       SkPnmiInit( pAC, pAC->IoBase, SK_INIT_IO);
17207 -       SkAddrInit( pAC, pAC->IoBase, SK_INIT_IO);
17208 -       SkRlmtInit( pAC, pAC->IoBase, SK_INIT_IO);
17209 -       SkTimerInit(pAC, pAC->IoBase, SK_INIT_IO);
17210 -
17211 -       /*
17212 -       ** tschilling:
17213 -       ** Speed and others are set back to default in level 1 init!
17214 -       */
17215 -       GetConfiguration(pAC);
17216 -
17217 -       SkGeInit(   pAC, pAC->IoBase, SK_INIT_RUN);
17218 -       SkI2cInit(  pAC, pAC->IoBase, SK_INIT_RUN);
17219 -       SkEventInit(pAC, pAC->IoBase, SK_INIT_RUN);
17220 -       SkPnmiInit( pAC, pAC->IoBase, SK_INIT_RUN);
17221 -       SkAddrInit( pAC, pAC->IoBase, SK_INIT_RUN);
17222 -       SkRlmtInit( pAC, pAC->IoBase, SK_INIT_RUN);
17223 -       SkTimerInit(pAC, pAC->IoBase, SK_INIT_RUN);
17224 +               /* Enable transmit descriptor polling */
17225 +               SkGePollTxD(pAC, pAC->IoBase, pNet->PortNr, SK_TRUE);
17226 +               FillRxRing(pAC, &pAC->RxPort[pNet->PortNr]);
17227 +       }
17228
17229 -       /*
17230 -       ** clear and reinit the rx rings here
17231 -       */
17232 -       for (i=0; i<pAC->GIni.GIMacsFound; i++) {
17233 -               ReceiveIrq(pAC, &pAC->RxPort[i], SK_TRUE);
17234 -               ClearRxRing(pAC, &pAC->RxPort[i]);
17235 -               FillRxRing(pAC, &pAC->RxPort[i]);
17236 +       netif_start_queue(pAC->dev[pNet->PortNr]);
17237
17238 -               /*
17239 -               ** Enable transmit descriptor polling
17240 -               */
17241 -               SkGePollTxD(pAC, pAC->IoBase, i, SK_TRUE);
17242 -               FillRxRing(pAC, &pAC->RxPort[i]);
17243 -       };
17244 +       spin_unlock(&pAC->TxPort[pNet->PortNr][TX_PRIO_LOW].TxDesRingLock);
17245
17246 -       SkGeYellowLED(pAC, pAC->IoBase, 1);
17247 -       SkDimEnableModerationIfNeeded(pAC);
17248 -       SkDimDisplayModerationSettings(pAC);
17249
17250 -       netif_start_queue(pAC->dev[pNet->PortNr]);
17251 -       for (i=pAC->GIni.GIMacsFound-1; i>=0; i--) {
17252 -               spin_unlock(&pAC->TxPort[i][TX_PRIO_LOW].TxDesRingLock);
17253 -       }
17254 +       /* Notify RLMT about the changing and restarting one (or more) ports */
17255 +       SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_START,
17256 +                                       pNet->PortNr, -1, SK_TRUE);
17257
17258 -       /*
17259 -       ** Enable Interrupts again
17260 -       */
17261 +       /* Enable Interrupts again */
17262         SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
17263         SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK);
17264
17265 -       SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara);
17266 -       SkEventDispatcher(pAC, pAC->IoBase);
17267 -
17268 -       /*
17269 -       ** Notify RLMT about the changing and restarting one (or more) ports
17270 -       */
17271 -       if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
17272 -               EvPara.Para32[0] = pAC->RlmtNets;
17273 -               EvPara.Para32[1] = -1;
17274 -               SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_SET_NETS, EvPara);
17275 -               EvPara.Para32[0] = pNet->PortNr;
17276 -               EvPara.Para32[1] = -1;
17277 -               SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara);
17278 -
17279 -               if (netif_running(pOtherDev)) {
17280 -                       DEV_NET *pOtherNet = netdev_priv(pOtherDev);
17281 -                       EvPara.Para32[0] = pOtherNet->PortNr;
17282 -                       SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara);
17283 -               }
17284 -       } else {
17285 -               SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara);
17286 -       }
17287 -
17288 -       SkEventDispatcher(pAC, pAC->IoBase);
17289         spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
17290 -
17291 -       /*
17292 -       ** While testing this driver with latest kernel 2.5 (2.5.70), it
17293 -       ** seems as if upper layers have a problem to handle a successful
17294 -       ** return value of '0'. If such a zero is returned, the complete
17295 -       ** system hangs for several minutes (!), which is in acceptable.
17296 -       **
17297 -       ** Currently it is not clear, what the exact reason for this problem
17298 -       ** is. The implemented workaround for 2.5 is to return the desired
17299 -       ** new MTU size if all needed changes for the new MTU size where
17300 -       ** performed. In kernels 2.2 and 2.4, a zero value is returned,
17301 -       ** which indicates the successful change of the mtu-size.
17302 -       */
17303 -       return NewMtu;
17304 +       return 0;
17305
17306 -} /* SkGeChangeMtu */
17307 +}
17308
17309
17310  /*****************************************************************************
17311 @@ -2775,75 +3939,67 @@
17312   */
17313  static struct net_device_stats *SkGeStats(struct SK_NET_DEVICE *dev)
17314  {
17315 -DEV_NET *pNet = netdev_priv(dev);
17316 -SK_AC  *pAC = pNet->pAC;
17317 -SK_PNMI_STRUCT_DATA *pPnmiStruct;       /* structure for all Pnmi-Data */
17318 -SK_PNMI_STAT    *pPnmiStat;             /* pointer to virtual XMAC stat. data */
17319 -SK_PNMI_CONF    *pPnmiConf;             /* pointer to virtual link config. */
17320 -unsigned int    Size;                   /* size of pnmi struct */
17321 -unsigned long  Flags;                  /* for spin lock */
17322 -
17323 -       SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
17324 -               ("SkGeStats starts now...\n"));
17325 -       pPnmiStruct = &pAC->PnmiStruct;
17326 +       DEV_NET         *pNet = (DEV_NET*) dev->priv;
17327 +       SK_AC           *pAC = pNet->pAC;
17328 +       unsigned long   LateCollisions, ExcessiveCollisions, RxTooLong;
17329 +       unsigned long   Flags; /* for spin lock */
17330 +       SK_U32          MaxNumOidEntries, Oid, Len;
17331 +       char            Buf[8];
17332 +       struct {
17333 +               SK_U32         Oid;
17334 +               unsigned long *pVar;
17335 +       } Vars[] = {
17336 +               { OID_SKGE_STAT_TX_LATE_COL,   &LateCollisions               },
17337 +               { OID_SKGE_STAT_TX_EXCESS_COL, &ExcessiveCollisions          },
17338 +               { OID_SKGE_STAT_RX_TOO_LONG,   &RxTooLong                    },
17339 +               { OID_SKGE_STAT_RX,            &pAC->stats.rx_packets        },
17340 +               { OID_SKGE_STAT_TX,            &pAC->stats.tx_packets        },
17341 +               { OID_SKGE_STAT_RX_OCTETS,     &pAC->stats.rx_bytes          },
17342 +               { OID_SKGE_STAT_TX_OCTETS,     &pAC->stats.tx_bytes          },
17343 +               { OID_SKGE_RX_NO_BUF_CTS,      &pAC->stats.rx_dropped        },
17344 +               { OID_SKGE_TX_NO_BUF_CTS,      &pAC->stats.tx_dropped        },
17345 +               { OID_SKGE_STAT_RX_MULTICAST,  &pAC->stats.multicast         },
17346 +               { OID_SKGE_STAT_RX_RUNT,       &pAC->stats.rx_length_errors  },
17347 +               { OID_SKGE_STAT_RX_FCS,        &pAC->stats.rx_crc_errors     },
17348 +               { OID_SKGE_STAT_RX_FRAMING,    &pAC->stats.rx_frame_errors   },
17349 +               { OID_SKGE_STAT_RX_OVERFLOW,   &pAC->stats.rx_over_errors    },
17350 +               { OID_SKGE_STAT_RX_MISSED,     &pAC->stats.rx_missed_errors  },
17351 +               { OID_SKGE_STAT_TX_CARRIER,    &pAC->stats.tx_carrier_errors },
17352 +               { OID_SKGE_STAT_TX_UNDERRUN,   &pAC->stats.tx_fifo_errors    },
17353 +       };
17354 +
17355 +       if ((pAC->DiagModeActive == DIAG_NOTACTIVE) &&
17356 +           (pAC->BoardLevel     == SK_INIT_RUN)) {
17357 +               memset(&pAC->stats, 0x00, sizeof(pAC->stats)); /* clean first */
17358 +               spin_lock_irqsave(&pAC->SlowPathLock, Flags);
17359
17360 -#ifdef SK_DIAG_SUPPORT
17361 -        if ((pAC->DiagModeActive == DIAG_NOTACTIVE) &&
17362 -                (pAC->BoardLevel == SK_INIT_RUN)) {
17363 -#endif
17364 -        SK_MEMSET(pPnmiStruct, 0, sizeof(SK_PNMI_STRUCT_DATA));
17365 -        spin_lock_irqsave(&pAC->SlowPathLock, Flags);
17366 -        Size = SK_PNMI_STRUCT_SIZE;
17367 -               SkPnmiGetStruct(pAC, pAC->IoBase, pPnmiStruct, &Size, pNet->NetNr);
17368 -        spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
17369 -#ifdef SK_DIAG_SUPPORT
17370 -       }
17371 -#endif
17372 +               MaxNumOidEntries = sizeof(Vars) / sizeof(Vars[0]);
17373 +               for (Oid = 0; Oid < MaxNumOidEntries; Oid++) {
17374 +                       if (SkPnmiGetVar(pAC,pAC->IoBase, Vars[Oid].Oid,
17375 +                               &Buf, &Len, 1, pNet->NetNr) != SK_PNMI_ERR_OK) {
17376 +                               memset(Buf, 0x00, sizeof(Buf));
17377 +                       }
17378 +                       *Vars[Oid].pVar = (unsigned long) (*((SK_U64 *) Buf));
17379 +               }
17380 +               spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
17381
17382 -        pPnmiStat = &pPnmiStruct->Stat[0];
17383 -        pPnmiConf = &pPnmiStruct->Conf[0];
17384 +               pAC->stats.collisions = LateCollisions + ExcessiveCollisions;
17385 +               pAC->stats.tx_errors =  pAC->stats.tx_carrier_errors +
17386 +                                       pAC->stats.tx_fifo_errors;
17387 +               pAC->stats.rx_errors =  pAC->stats.rx_length_errors +
17388 +                                       pAC->stats.rx_crc_errors +
17389 +                                       pAC->stats.rx_frame_errors +
17390 +                                       pAC->stats.rx_over_errors +
17391 +                                       pAC->stats.rx_missed_errors;
17392
17393 -       pAC->stats.rx_packets = (SK_U32) pPnmiStruct->RxDeliveredCts & 0xFFFFFFFF;
17394 -       pAC->stats.tx_packets = (SK_U32) pPnmiStat->StatTxOkCts & 0xFFFFFFFF;
17395 -       pAC->stats.rx_bytes = (SK_U32) pPnmiStruct->RxOctetsDeliveredCts;
17396 -       pAC->stats.tx_bytes = (SK_U32) pPnmiStat->StatTxOctetsOkCts;
17397 -
17398 -        if (dev->mtu <= 1500) {
17399 -                pAC->stats.rx_errors = (SK_U32) pPnmiStruct->InErrorsCts & 0xFFFFFFFF;
17400 -        } else {
17401 -                pAC->stats.rx_errors = (SK_U32) ((pPnmiStruct->InErrorsCts -
17402 -                        pPnmiStat->StatRxTooLongCts) & 0xFFFFFFFF);
17403 +               if (dev->mtu > 1500) {
17404 +                       pAC->stats.rx_errors = pAC->stats.rx_errors - RxTooLong;
17405 +               }
17406         }
17407
17408 -
17409 -       if (pAC->GIni.GP[0].PhyType == SK_PHY_XMAC && pAC->HWRevision < 12)
17410 -               pAC->stats.rx_errors = pAC->stats.rx_errors - pPnmiStat->StatRxShortsCts;
17411 -
17412 -       pAC->stats.tx_errors = (SK_U32) pPnmiStat->StatTxSingleCollisionCts & 0xFFFFFFFF;
17413 -       pAC->stats.rx_dropped = (SK_U32) pPnmiStruct->RxNoBufCts & 0xFFFFFFFF;
17414 -       pAC->stats.tx_dropped = (SK_U32) pPnmiStruct->TxNoBufCts & 0xFFFFFFFF;
17415 -       pAC->stats.multicast = (SK_U32) pPnmiStat->StatRxMulticastOkCts & 0xFFFFFFFF;
17416 -       pAC->stats.collisions = (SK_U32) pPnmiStat->StatTxSingleCollisionCts & 0xFFFFFFFF;
17417 -
17418 -       /* detailed rx_errors: */
17419 -       pAC->stats.rx_length_errors = (SK_U32) pPnmiStat->StatRxRuntCts & 0xFFFFFFFF;
17420 -       pAC->stats.rx_over_errors = (SK_U32) pPnmiStat->StatRxFifoOverflowCts & 0xFFFFFFFF;
17421 -       pAC->stats.rx_crc_errors = (SK_U32) pPnmiStat->StatRxFcsCts & 0xFFFFFFFF;
17422 -       pAC->stats.rx_frame_errors = (SK_U32) pPnmiStat->StatRxFramingCts & 0xFFFFFFFF;
17423 -       pAC->stats.rx_fifo_errors = (SK_U32) pPnmiStat->StatRxFifoOverflowCts & 0xFFFFFFFF;
17424 -       pAC->stats.rx_missed_errors = (SK_U32) pPnmiStat->StatRxMissedCts & 0xFFFFFFFF;
17425 -
17426 -       /* detailed tx_errors */
17427 -       pAC->stats.tx_aborted_errors = (SK_U32) 0;
17428 -       pAC->stats.tx_carrier_errors = (SK_U32) pPnmiStat->StatTxCarrierCts & 0xFFFFFFFF;
17429 -       pAC->stats.tx_fifo_errors = (SK_U32) pPnmiStat->StatTxFifoUnderrunCts & 0xFFFFFFFF;
17430 -       pAC->stats.tx_heartbeat_errors = (SK_U32) pPnmiStat->StatTxCarrierCts & 0xFFFFFFFF;
17431 -       pAC->stats.tx_window_errors = (SK_U32) 0;
17432 -
17433         return(&pAC->stats);
17434  } /* SkGeStats */
17435
17436 -
17437  /*****************************************************************************
17438   *
17439   *     SkGeIoctl - IO-control function
17440 @@ -2851,38 +4007,41 @@
17441   * Description:
17442   *     This function is called if an ioctl is issued on the device.
17443   *     There are three subfunction for reading, writing and test-writing
17444 - *     the private MIB data structure (useful for SysKonnect-internal tools).
17445 + *     the private MIB data structure (usefull for SysKonnect-internal tools).
17446   *
17447   * Returns:
17448   *     0, if everything is ok
17449   *     !=0, on error
17450   */
17451 -static int SkGeIoctl(struct SK_NET_DEVICE *dev, struct ifreq *rq, int cmd)
17452 -{
17453 -DEV_NET                *pNet;
17454 -SK_AC          *pAC;
17455 -void           *pMemBuf;
17456 -struct pci_dev  *pdev = NULL;
17457 -SK_GE_IOCTL    Ioctl;
17458 -unsigned int   Err = 0;
17459 -int            Size = 0;
17460 -int             Ret = 0;
17461 -unsigned int   Length = 0;
17462 -int            HeaderLength = sizeof(SK_U32) + sizeof(SK_U32);
17463 +static int SkGeIoctl(
17464 +struct SK_NET_DEVICE *dev,  /* the device the IOCTL is to be performed on   */
17465 +struct ifreq         *rq,   /* additional request structure containing data */
17466 +int                   cmd)  /* requested IOCTL command number               */
17467 +{
17468 +       DEV_NET          *pNet = (DEV_NET*) dev->priv;
17469 +       SK_AC            *pAC  = pNet->pAC;
17470 +       struct pci_dev   *pdev = NULL;
17471 +       void             *pMemBuf;
17472 +       SK_GE_IOCTL       Ioctl;
17473 +       unsigned long     Flags; /* for spin lock */
17474 +       unsigned int      Err = 0;
17475 +       unsigned int      Length = 0;
17476 +       int               HeaderLength = sizeof(SK_U32) + sizeof(SK_U32);
17477 +       int               Size = 0;
17478 +       int               Ret = 0;
17479
17480         SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
17481                 ("SkGeIoctl starts now...\n"));
17482
17483 -       pNet = netdev_priv(dev);
17484 -       pAC = pNet->pAC;
17485 -
17486         if(copy_from_user(&Ioctl, rq->ifr_data, sizeof(SK_GE_IOCTL))) {
17487                 return -EFAULT;
17488         }
17489
17490         switch(cmd) {
17491 -       case SK_IOCTL_SETMIB:
17492 -       case SK_IOCTL_PRESETMIB:
17493 +       case SIOCETHTOOL:
17494 +               return SkEthIoctl(dev, rq);
17495 +       case SK_IOCTL_SETMIB:     /* FALL THRU */
17496 +       case SK_IOCTL_PRESETMIB:  /* FALL THRU (if capable!) */
17497                 if (!capable(CAP_NET_ADMIN)) return -EPERM;
17498         case SK_IOCTL_GETMIB:
17499                 if(copy_from_user(&pAC->PnmiStruct, Ioctl.pData,
17500 @@ -2909,6 +4068,7 @@
17501                 if (NULL == (pMemBuf = kmalloc(Length, GFP_KERNEL))) {
17502                         return -ENOMEM;
17503                 }
17504 +               spin_lock_irqsave(&pAC->SlowPathLock, Flags);
17505                 if(copy_from_user(pMemBuf, Ioctl.pData, Length)) {
17506                         Err = -EFAULT;
17507                         goto fault_gen;
17508 @@ -2927,10 +4087,10 @@
17509                         goto fault_gen;
17510                 }
17511  fault_gen:
17512 +               spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
17513                 kfree(pMemBuf); /* cleanup everything */
17514                 break;
17515 -#ifdef SK_DIAG_SUPPORT
17516 -       case SK_IOCTL_DIAG:
17517 +       case SK_IOCTL_DIAG:
17518                 if (!capable(CAP_NET_ADMIN)) return -EPERM;
17519                 if (Ioctl.Len < (sizeof(pAC->PnmiStruct) + HeaderLength)) {
17520                         Length = Ioctl.Len;
17521 @@ -2967,7 +4127,6 @@
17522  fault_diag:
17523                 kfree(pMemBuf); /* cleanup everything */
17524                 break;
17525 -#endif
17526         default:
17527                 Err = -EOPNOTSUPP;
17528         }
17529 @@ -2999,12 +4158,12 @@
17530  unsigned int   Size,   /* length of ioctl data */
17531  int            mode)   /* flag for set/preset */
17532  {
17533 -unsigned long  Flags;  /* for spin lock */
17534 -SK_AC          *pAC;
17535 +       SK_AC           *pAC = pNet->pAC;
17536 +       unsigned long   Flags;  /* for spin lock */
17537
17538         SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
17539                 ("SkGeIocMib starts now...\n"));
17540 -       pAC = pNet->pAC;
17541 +
17542         /* access MIB */
17543         spin_lock_irqsave(&pAC->SlowPathLock, Flags);
17544         switch(mode) {
17545 @@ -3047,17 +4206,18 @@
17546  SK_I32 Port;           /* preferred port */
17547  SK_BOOL        AutoSet;
17548  SK_BOOL DupSet;
17549 -int    LinkSpeed          = SK_LSPEED_AUTO;    /* Link speed */
17550 -int    AutoNeg            = 1;                 /* autoneg off (0) or on (1) */
17551 -int    DuplexCap          = 0;                 /* 0=both,1=full,2=half */
17552 -int    FlowCtrl           = SK_FLOW_MODE_SYM_OR_REM;   /* FlowControl  */
17553 -int    MSMode             = SK_MS_MODE_AUTO;   /* master/slave mode    */
17554 -
17555 -SK_BOOL IsConTypeDefined   = SK_TRUE;
17556 -SK_BOOL IsLinkSpeedDefined = SK_TRUE;
17557 -SK_BOOL IsFlowCtrlDefined  = SK_TRUE;
17558 -SK_BOOL IsRoleDefined      = SK_TRUE;
17559 -SK_BOOL IsModeDefined      = SK_TRUE;
17560 +int    LinkSpeed               = SK_LSPEED_AUTO;       /* Link speed */
17561 +int    AutoNeg                 = 1;                    /* autoneg off (0) or on (1) */
17562 +int    DuplexCap               = 0;                    /* 0=both,1=full,2=half */
17563 +int    FlowCtrl                = SK_FLOW_MODE_SYM_OR_REM;      /* FlowControl  */
17564 +int    MSMode                  = SK_MS_MODE_AUTO;      /* master/slave mode    */
17565 +int    IrqModMaskOffset        = 6;                    /* all ints moderated=default */
17566 +
17567 +SK_BOOL IsConTypeDefined       = SK_TRUE;
17568 +SK_BOOL IsLinkSpeedDefined     = SK_TRUE;
17569 +SK_BOOL IsFlowCtrlDefined      = SK_TRUE;
17570 +SK_BOOL IsRoleDefined          = SK_TRUE;
17571 +SK_BOOL IsModeDefined          = SK_TRUE;
17572  /*
17573   *     The two parameters AutoNeg. and DuplexCap. map to one configuration
17574   *     parameter. The mapping is described by this table:
17575 @@ -3075,6 +4235,15 @@
17576                   {SK_LMODE_AUTOBOTH , SK_LMODE_AUTOFULL , SK_LMODE_AUTOHALF },
17577                   {SK_LMODE_AUTOSENSE, SK_LMODE_AUTOSENSE, SK_LMODE_AUTOSENSE} };
17578
17579 +SK_U32 IrqModMask[7][2] =
17580 +               { { IRQ_MASK_RX_ONLY , Y2_DRIVER_IRQS  },
17581 +                 { IRQ_MASK_TX_ONLY , Y2_DRIVER_IRQS  },
17582 +                 { IRQ_MASK_SP_ONLY , Y2_SPECIAL_IRQS },
17583 +                 { IRQ_MASK_SP_RX   , Y2_IRQ_MASK     },
17584 +                 { IRQ_MASK_TX_RX   , Y2_DRIVER_IRQS  },
17585 +                 { IRQ_MASK_SP_TX   , Y2_IRQ_MASK     },
17586 +                 { IRQ_MASK_RX_TX_SP, Y2_IRQ_MASK     } };
17587 +
17588  #define DC_BOTH        0
17589  #define DC_FULL 1
17590  #define DC_HALF 2
17591 @@ -3107,6 +4276,7 @@
17592         ** ConType   DupCap   AutoNeg   FlowCtrl      Role      Speed
17593         ** -------   ------   -------   --------   ----------   -----
17594         **  Auto      Both      On      SymOrRem      Auto       Auto
17595 +       **  1000FD    Full      Off       None      <ignored>    1000
17596         **  100FD     Full      Off       None      <ignored>    100
17597         **  100HD     Half      Off       None      <ignored>    100
17598         **  10FD      Full      Off       None      <ignored>    10
17599 @@ -3114,66 +4284,86 @@
17600         **
17601         ** This ConType parameter is used for all ports of the adapter!
17602         */
17603 -        if ( (ConType != NULL)                &&
17604 +       if ( (ConType != NULL)                &&
17605              (pAC->Index < SK_MAX_CARD_PARAM) &&
17606              (ConType[pAC->Index] != NULL) ) {
17607
17608 -                       /* Check chipset family */
17609 -                       if ((!pAC->ChipsetType) &&
17610 -                               (strcmp(ConType[pAC->Index],"Auto")!=0) &&
17611 -                               (strcmp(ConType[pAC->Index],"")!=0)) {
17612 -                               /* Set the speed parameter back */
17613 -                                       printk("sk98lin: Illegal value \"%s\" "
17614 -                                                       "for ConType."
17615 -                                                       " Using Auto.\n",
17616 -                                                       ConType[pAC->Index]);
17617 -
17618 -                                       sprintf(ConType[pAC->Index], "Auto");
17619 -                       }
17620 +               /* Check chipset family */
17621 +               if ((!pAC->ChipsetType) &&
17622 +                       (strcmp(ConType[pAC->Index],"Auto")!=0) &&
17623 +                       (strcmp(ConType[pAC->Index],"")!=0)) {
17624 +                       /* Set the speed parameter back */
17625 +                       printk("sk98lin: Illegal value \"%s\" "
17626 +                               "for ConType."
17627 +                               " Using Auto.\n",
17628 +                               ConType[pAC->Index]);
17629 +
17630 +                       ConType[pAC->Index] = "Auto";
17631 +               }
17632 +
17633 +               if ((pAC->ChipsetType) &&
17634 +                       (pAC->GIni.GICopperType != SK_TRUE) &&
17635 +                       (strcmp(ConType[pAC->Index],"") != 0) &&
17636 +                       (strcmp(ConType[pAC->Index],"1000FD") != 0)) {
17637 +                       /* Set the speed parameter back */
17638 +                       printk("sk98lin: Illegal value \"%s\" "
17639 +                               "for ConType."
17640 +                               " Using Auto.\n",
17641 +                               ConType[pAC->Index]);
17642 +                       IsConTypeDefined = SK_FALSE;
17643 +                       ConType[pAC->Index] = "Auto";
17644 +               }
17645
17646 -                               if (strcmp(ConType[pAC->Index],"")==0) {
17647 +               if (strcmp(ConType[pAC->Index],"")==0) {
17648                         IsConTypeDefined = SK_FALSE; /* No ConType defined */
17649 -                               } else if (strcmp(ConType[pAC->Index],"Auto")==0) {
17650 +               } else if (strcmp(ConType[pAC->Index],"Auto")==0) {
17651                     for (Port = 0; Port < SK_MAX_MACS; Port++) {
17652                         M_CurrPort.PLinkModeConf = Capabilities[AN_ON][DC_BOTH];
17653                         M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_SYM_OR_REM;
17654                         M_CurrPort.PMSMode       = SK_MS_MODE_AUTO;
17655                         M_CurrPort.PLinkSpeed    = SK_LSPEED_AUTO;
17656                     }
17657 -                } else if (strcmp(ConType[pAC->Index],"100FD")==0) {
17658 +               } else if (strcmp(ConType[pAC->Index],"1000FD")==0) {
17659 +                   for (Port = 0; Port < SK_MAX_MACS; Port++) {
17660 +                       M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_FULL];
17661 +                       M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE;
17662 +                       M_CurrPort.PMSMode       = SK_MS_MODE_AUTO;
17663 +                       M_CurrPort.PLinkSpeed    = SK_LSPEED_1000MBPS;
17664 +                   }
17665 +               } else if (strcmp(ConType[pAC->Index],"100FD")==0) {
17666                     for (Port = 0; Port < SK_MAX_MACS; Port++) {
17667                         M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_FULL];
17668                         M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE;
17669                         M_CurrPort.PMSMode       = SK_MS_MODE_AUTO;
17670                         M_CurrPort.PLinkSpeed    = SK_LSPEED_100MBPS;
17671                     }
17672 -                } else if (strcmp(ConType[pAC->Index],"100HD")==0) {
17673 +               } else if (strcmp(ConType[pAC->Index],"100HD")==0) {
17674                     for (Port = 0; Port < SK_MAX_MACS; Port++) {
17675                         M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_HALF];
17676                         M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE;
17677                         M_CurrPort.PMSMode       = SK_MS_MODE_AUTO;
17678                         M_CurrPort.PLinkSpeed    = SK_LSPEED_100MBPS;
17679                     }
17680 -                } else if (strcmp(ConType[pAC->Index],"10FD")==0) {
17681 +               } else if (strcmp(ConType[pAC->Index],"10FD")==0) {
17682                     for (Port = 0; Port < SK_MAX_MACS; Port++) {
17683                         M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_FULL];
17684                         M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE;
17685                         M_CurrPort.PMSMode       = SK_MS_MODE_AUTO;
17686                         M_CurrPort.PLinkSpeed    = SK_LSPEED_10MBPS;
17687                     }
17688 -                } else if (strcmp(ConType[pAC->Index],"10HD")==0) {
17689 +               } else if (strcmp(ConType[pAC->Index],"10HD")==0) {
17690                     for (Port = 0; Port < SK_MAX_MACS; Port++) {
17691                         M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_HALF];
17692                         M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE;
17693                         M_CurrPort.PMSMode       = SK_MS_MODE_AUTO;
17694                         M_CurrPort.PLinkSpeed    = SK_LSPEED_10MBPS;
17695                     }
17696 -                } else {
17697 +               } else {
17698                     printk("sk98lin: Illegal value \"%s\" for ConType\n",
17699                         ConType[pAC->Index]);
17700                     IsConTypeDefined = SK_FALSE; /* Wrong ConType defined */
17701                 }
17702 -        } else {
17703 +       } else {
17704             IsConTypeDefined = SK_FALSE; /* No ConType defined */
17705         }
17706
17707 @@ -3192,14 +4382,30 @@
17708                 } else if (strcmp(Speed_A[pAC->Index],"100")==0) {
17709                     LinkSpeed = SK_LSPEED_100MBPS;
17710                 } else if (strcmp(Speed_A[pAC->Index],"1000")==0) {
17711 -                   LinkSpeed = SK_LSPEED_1000MBPS;
17712 +                   if ((pAC->PciDev->vendor == 0x11ab ) &&
17713 +                       (pAC->PciDev->device == 0x4350)) {
17714 +                               LinkSpeed = SK_LSPEED_100MBPS;
17715 +                               printk("sk98lin: Illegal value \"%s\" for Speed_A.\n"
17716 +                                       "Gigabit speed not possible with this chip revision!",
17717 +                                       Speed_A[pAC->Index]);
17718 +                       } else {
17719 +                               LinkSpeed = SK_LSPEED_1000MBPS;
17720 +                   }
17721                 } else {
17722                     printk("sk98lin: Illegal value \"%s\" for Speed_A\n",
17723                         Speed_A[pAC->Index]);
17724                     IsLinkSpeedDefined = SK_FALSE;
17725                 }
17726         } else {
17727 -           IsLinkSpeedDefined = SK_FALSE;
17728 +               if ((pAC->PciDev->vendor == 0x11ab ) &&
17729 +                       (pAC->PciDev->device == 0x4350)) {
17730 +                       /* Gigabit speed not supported
17731 +                        * Swith to speed 100
17732 +                        */
17733 +                       LinkSpeed = SK_LSPEED_100MBPS;
17734 +               } else {
17735 +                       IsLinkSpeedDefined = SK_FALSE;
17736 +               }
17737         }
17738
17739         /*
17740 @@ -3294,9 +4500,6 @@
17741         }
17742
17743         if (!AutoSet && DupSet) {
17744 -               printk("sk98lin: Port A: Duplex setting not"
17745 -                       " possible in\n    default AutoNegotiation mode"
17746 -                       " (Sense).\n    Using AutoNegotiation On\n");
17747                 AutoNeg = AN_ON;
17748         }
17749
17750 @@ -3324,7 +4527,7 @@
17751                     FlowCtrl = SK_FLOW_MODE_NONE;
17752                 } else {
17753                     printk("sk98lin: Illegal value \"%s\" for FlowCtrl_A\n",
17754 -                        FlowCtrl_A[pAC->Index]);
17755 +                       FlowCtrl_A[pAC->Index]);
17756                     IsFlowCtrlDefined = SK_FALSE;
17757                 }
17758         } else {
17759 @@ -3416,7 +4619,7 @@
17760         ** Decide whether to set new config value if somethig valid has
17761         ** been received.
17762         */
17763 -        if (IsLinkSpeedDefined) {
17764 +       if (IsLinkSpeedDefined) {
17765             pAC->GIni.GP[1].PLinkSpeed = LinkSpeed;
17766         }
17767
17768 @@ -3492,9 +4695,6 @@
17769         }
17770
17771         if (!AutoSet && DupSet) {
17772 -               printk("sk98lin: Port B: Duplex setting not"
17773 -                       " possible in\n    default AutoNegotiation mode"
17774 -                       " (Sense).\n    Using AutoNegotiation On\n");
17775                 AutoNeg = AN_ON;
17776         }
17777
17778 @@ -3607,11 +4807,15 @@
17779         }
17780
17781         pAC->RlmtNets = 1;
17782 +       pAC->RlmtMode = 0;
17783
17784         if (RlmtMode != NULL && pAC->Index<SK_MAX_CARD_PARAM &&
17785                 RlmtMode[pAC->Index] != NULL) {
17786                 if (strcmp(RlmtMode[pAC->Index], "") == 0) {
17787 -                       pAC->RlmtMode = 0;
17788 +                       if (pAC->GIni.GIMacsFound == 2) {
17789 +                               pAC->RlmtMode = SK_RLMT_CHECK_LINK;
17790 +                               pAC->RlmtNets = 2;
17791 +                       }
17792                 } else if (strcmp(RlmtMode[pAC->Index], "CheckLinkState") == 0) {
17793                         pAC->RlmtMode = SK_RLMT_CHECK_LINK;
17794                 } else if (strcmp(RlmtMode[pAC->Index], "CheckLocalPort") == 0) {
17795 @@ -3632,12 +4836,46 @@
17796                         pAC->RlmtMode = 0;
17797                 }
17798         } else {
17799 -               pAC->RlmtMode = 0;
17800 +               if (pAC->GIni.GIMacsFound == 2) {
17801 +                       pAC->RlmtMode = SK_RLMT_CHECK_LINK;
17802 +                       pAC->RlmtNets = 2;
17803 +               }
17804         }
17805 -
17806 +
17807 +#ifdef SK_YUKON2
17808 +       /*
17809 +       ** use dualnet config per default
17810 +       *
17811 +       pAC->RlmtMode = SK_RLMT_CHECK_LINK;
17812 +       pAC->RlmtNets = 2;
17813 +       */
17814 +#endif
17815 +
17816 +
17817 +       /*
17818 +       ** Check the LowLatance parameters
17819 +       */
17820 +       pAC->LowLatency = SK_FALSE;
17821 +       if (LowLatency[pAC->Index] != NULL) {
17822 +               if (strcmp(LowLatency[pAC->Index], "On") == 0) {
17823 +                       pAC->LowLatency = SK_TRUE;
17824 +               }
17825 +       }
17826 +
17827 +       /*
17828 +       ** Check the BroadcastPrio parameters
17829 +       */
17830 +       pAC->Rlmt.Net[0].ChgBcPrio = SK_FALSE;
17831 +       if (BroadcastPrio[pAC->Index] != NULL) {
17832 +               if (strcmp(BroadcastPrio[pAC->Index], "On") == 0) {
17833 +                       pAC->Rlmt.Net[0].ChgBcPrio = SK_TRUE;
17834 +               }
17835 +       }
17836 +
17837         /*
17838         ** Check the interrupt moderation parameters
17839         */
17840 +       pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_NONE;
17841         if (Moderation[pAC->Index] != NULL) {
17842                 if (strcmp(Moderation[pAC->Index], "") == 0) {
17843                         pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_NONE;
17844 @@ -3651,70 +4889,49 @@
17845                         printk("sk98lin: Illegal value \"%s\" for Moderation.\n"
17846                                 "      Disable interrupt moderation.\n",
17847                                 Moderation[pAC->Index]);
17848 -                       pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_NONE;
17849 -               }
17850 -       } else {
17851 -               pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_NONE;
17852 -       }
17853 -
17854 -       if (Stats[pAC->Index] != NULL) {
17855 -               if (strcmp(Stats[pAC->Index], "Yes") == 0) {
17856 -                       pAC->DynIrqModInfo.DisplayStats = SK_TRUE;
17857 -               } else {
17858 -                       pAC->DynIrqModInfo.DisplayStats = SK_FALSE;
17859                 }
17860         } else {
17861 -               pAC->DynIrqModInfo.DisplayStats = SK_FALSE;
17862 +/* Set interrupt moderation if wished */
17863 +#ifdef CONFIG_SK98LIN_STATINT
17864 +               pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_STATIC;
17865 +#endif
17866         }
17867
17868         if (ModerationMask[pAC->Index] != NULL) {
17869                 if (strcmp(ModerationMask[pAC->Index], "Rx") == 0) {
17870 -                       pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_ONLY;
17871 +                       IrqModMaskOffset = 0;
17872                 } else if (strcmp(ModerationMask[pAC->Index], "Tx") == 0) {
17873 -                       pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_TX_ONLY;
17874 +                       IrqModMaskOffset = 1;
17875                 } else if (strcmp(ModerationMask[pAC->Index], "Sp") == 0) {
17876 -                       pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_SP_ONLY;
17877 +                       IrqModMaskOffset = 2;
17878                 } else if (strcmp(ModerationMask[pAC->Index], "RxSp") == 0) {
17879 -                       pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_SP_RX;
17880 +                       IrqModMaskOffset = 3;
17881                 } else if (strcmp(ModerationMask[pAC->Index], "SpRx") == 0) {
17882 -                       pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_SP_RX;
17883 +                       IrqModMaskOffset = 3;
17884                 } else if (strcmp(ModerationMask[pAC->Index], "RxTx") == 0) {
17885 -                       pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_TX_RX;
17886 +                       IrqModMaskOffset = 4;
17887                 } else if (strcmp(ModerationMask[pAC->Index], "TxRx") == 0) {
17888 -                       pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_TX_RX;
17889 +                       IrqModMaskOffset = 4;
17890                 } else if (strcmp(ModerationMask[pAC->Index], "TxSp") == 0) {
17891 -                       pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_SP_TX;
17892 +                       IrqModMaskOffset = 5;
17893                 } else if (strcmp(ModerationMask[pAC->Index], "SpTx") == 0) {
17894 -                       pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_SP_TX;
17895 -               } else if (strcmp(ModerationMask[pAC->Index], "RxTxSp") == 0) {
17896 -                       pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP;
17897 -               } else if (strcmp(ModerationMask[pAC->Index], "RxSpTx") == 0) {
17898 -                       pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP;
17899 -               } else if (strcmp(ModerationMask[pAC->Index], "TxRxSp") == 0) {
17900 -                       pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP;
17901 -               } else if (strcmp(ModerationMask[pAC->Index], "TxSpRx") == 0) {
17902 -                       pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP;
17903 -               } else if (strcmp(ModerationMask[pAC->Index], "SpTxRx") == 0) {
17904 -                       pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP;
17905 -               } else if (strcmp(ModerationMask[pAC->Index], "SpRxTx") == 0) {
17906 -                       pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP;
17907 -               } else { /* some rubbish */
17908 -                       pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_ONLY;
17909 -               }
17910 -       } else {  /* operator has stated nothing */
17911 -               pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_TX_RX;
17912 -       }
17913 -
17914 -       if (AutoSizing[pAC->Index] != NULL) {
17915 -               if (strcmp(AutoSizing[pAC->Index], "On") == 0) {
17916 -                       pAC->DynIrqModInfo.AutoSizing = SK_FALSE;
17917 -               } else {
17918 -                       pAC->DynIrqModInfo.AutoSizing = SK_FALSE;
17919 +                       IrqModMaskOffset = 5;
17920 +               } else { /* some rubbish stated */
17921 +                       // IrqModMaskOffset = 6; ->has been initialized
17922 +                       // already at the begin of this function...
17923                 }
17924 -       } else {  /* operator has stated nothing */
17925 -               pAC->DynIrqModInfo.AutoSizing = SK_FALSE;
17926 +       }
17927 +       if (!CHIP_ID_YUKON_2(pAC)) {
17928 +               pAC->DynIrqModInfo.MaskIrqModeration = IrqModMask[IrqModMaskOffset][0];
17929 +       } else {
17930 +               pAC->DynIrqModInfo.MaskIrqModeration = IrqModMask[IrqModMaskOffset][1];
17931         }
17932
17933 +       if (!CHIP_ID_YUKON_2(pAC)) {
17934 +               pAC->DynIrqModInfo.MaxModIntsPerSec = C_INTS_PER_SEC_DEFAULT;
17935 +       } else {
17936 +               pAC->DynIrqModInfo.MaxModIntsPerSec = C_Y2_INTS_PER_SEC_DEFAULT;
17937 +       }
17938         if (IntsPerSec[pAC->Index] != 0) {
17939                 if ((IntsPerSec[pAC->Index]< C_INT_MOD_IPS_LOWER_RANGE) ||
17940                         (IntsPerSec[pAC->Index] > C_INT_MOD_IPS_UPPER_RANGE)) {
17941 @@ -3723,97 +4940,54 @@
17942                                 IntsPerSec[pAC->Index],
17943                                 C_INT_MOD_IPS_LOWER_RANGE,
17944                                 C_INT_MOD_IPS_UPPER_RANGE,
17945 -                               C_INTS_PER_SEC_DEFAULT);
17946 -                       pAC->DynIrqModInfo.MaxModIntsPerSec = C_INTS_PER_SEC_DEFAULT;
17947 +                               pAC->DynIrqModInfo.MaxModIntsPerSec);
17948                 } else {
17949                         pAC->DynIrqModInfo.MaxModIntsPerSec = IntsPerSec[pAC->Index];
17950                 }
17951 -       } else {
17952 -               pAC->DynIrqModInfo.MaxModIntsPerSec = C_INTS_PER_SEC_DEFAULT;
17953 -       }
17954 +       }
17955
17956         /*
17957         ** Evaluate upper and lower moderation threshold
17958         */
17959         pAC->DynIrqModInfo.MaxModIntsPerSecUpperLimit =
17960                 pAC->DynIrqModInfo.MaxModIntsPerSec +
17961 -               (pAC->DynIrqModInfo.MaxModIntsPerSec / 2);
17962 +               (pAC->DynIrqModInfo.MaxModIntsPerSec / 5);
17963
17964         pAC->DynIrqModInfo.MaxModIntsPerSecLowerLimit =
17965                 pAC->DynIrqModInfo.MaxModIntsPerSec -
17966 -               (pAC->DynIrqModInfo.MaxModIntsPerSec / 2);
17967 -
17968 -       pAC->DynIrqModInfo.PrevTimeVal = jiffies;  /* initial value */
17969 -
17970 -
17971 -} /* GetConfiguration */
17972 -
17973 +               (pAC->DynIrqModInfo.MaxModIntsPerSec / 5);
17974
17975 -/*****************************************************************************
17976 - *
17977 - *     ProductStr - return a adapter identification string from vpd
17978 - *
17979 - * Description:
17980 - *     This function reads the product name string from the vpd area
17981 - *     and puts it the field pAC->DeviceString.
17982 - *
17983 - * Returns: N/A
17984 - */
17985 -static inline int ProductStr(
17986 -       SK_AC   *pAC,           /* pointer to adapter context */
17987 -       char    *DeviceStr,     /* result string */
17988 -       int      StrLen         /* length of the string */
17989 -)
17990 -{
17991 -char   Keyword[] = VPD_NAME;   /* vpd productname identifier */
17992 -int    ReturnCode;             /* return code from vpd_read */
17993 -unsigned long Flags;
17994 +       pAC->DynIrqModInfo.DynIrqModSampleInterval =
17995 +               SK_DRV_MODERATION_TIMER_LENGTH;
17996
17997 -       spin_lock_irqsave(&pAC->SlowPathLock, Flags);
17998 -       ReturnCode = VpdRead(pAC, pAC->IoBase, Keyword, DeviceStr, &StrLen);
17999 -       spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
18000 +} /* GetConfiguration */
18001
18002 -       return ReturnCode;
18003 -} /* ProductStr */
18004
18005  /*****************************************************************************
18006   *
18007 - *      StartDrvCleanupTimer - Start timer to check for descriptors which
18008 - *                             might be placed in descriptor ring, but
18009 - *                             havent been handled up to now
18010 + *     ProductStr - return a adapter identification string from vpd
18011   *
18012   * Description:
18013 - *      This function requests a HW-timer fo the Yukon card. The actions to
18014 - *      perform when this timer expires, are located in the SkDrvEvent().
18015 + *     This function reads the product name string from the vpd area
18016 + *     and puts it the field pAC->DeviceString.
18017   *
18018   * Returns: N/A
18019   */
18020 -static void
18021 -StartDrvCleanupTimer(SK_AC *pAC) {
18022 -    SK_EVPARA    EventParam;   /* Event struct for timer event */
18023 -
18024 -    SK_MEMSET((char *) &EventParam, 0, sizeof(EventParam));
18025 -    EventParam.Para32[0] = SK_DRV_RX_CLEANUP_TIMER;
18026 -    SkTimerStart(pAC, pAC->IoBase, &pAC->DrvCleanupTimer,
18027 -                 SK_DRV_RX_CLEANUP_TIMER_LENGTH,
18028 -                 SKGE_DRV, SK_DRV_TIMER, EventParam);
18029 -}
18030 +static void ProductStr(SK_AC *pAC)
18031 +{
18032 +       char Default[] = "Generic Marvell Yukon chipset Ethernet device";
18033 +       char Key[] = VPD_NAME; /* VPD productname key */
18034 +       int StrLen = 80;       /* stringlen           */
18035 +       unsigned long Flags;
18036
18037 -/*****************************************************************************
18038 - *
18039 - *      StopDrvCleanupTimer - Stop timer to check for descriptors
18040 - *
18041 - * Description:
18042 - *      This function requests a HW-timer fo the Yukon card. The actions to
18043 - *      perform when this timer expires, are located in the SkDrvEvent().
18044 - *
18045 - * Returns: N/A
18046 - */
18047 -static void
18048 -StopDrvCleanupTimer(SK_AC *pAC) {
18049 -    SkTimerStop(pAC, pAC->IoBase, &pAC->DrvCleanupTimer);
18050 -    SK_MEMSET((char *) &pAC->DrvCleanupTimer, 0, sizeof(SK_TIMER));
18051 -}
18052 +       spin_lock_irqsave(&pAC->SlowPathLock, Flags);
18053 +       if (VpdRead(pAC, pAC->IoBase, Key, pAC->DeviceStr, &StrLen)) {
18054 +               SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ERROR,
18055 +                       ("Error reading VPD data: %d\n", ReturnCode));
18056 +               strcpy(pAC->DeviceStr, Default);
18057 +       }
18058 +       spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
18059 +} /* ProductStr */
18060
18061  /****************************************************************************/
18062  /* functions for common modules *********************************************/
18063 @@ -3903,7 +5077,9 @@
18064  SK_U64 SkOsGetTime(SK_AC *pAC)
18065  {
18066         SK_U64  PrivateJiffies;
18067 +
18068         SkOsGetTimeCurrent(pAC, &PrivateJiffies);
18069 +
18070         return PrivateJiffies;
18071  } /* SkOsGetTime */
18072
18073 @@ -3976,6 +5152,28 @@
18074
18075  /*****************************************************************************
18076   *
18077 + *     SkPciWriteCfgDWord - write a 32 bit value to pci config space
18078 + *
18079 + * Description:
18080 + *     This routine writes a 32 bit value to the pci configuration
18081 + *     space.
18082 + *
18083 + * Returns:
18084 + *     0 - indicate everything worked ok.
18085 + *     != 0 - error indication
18086 + */
18087 +int SkPciWriteCfgDWord(
18088 +SK_AC *pAC,    /* Adapter Control structure pointer */
18089 +int PciAddr,           /* PCI register address */
18090 +SK_U32 Val)            /* pointer to store the read value */
18091 +{
18092 +       pci_write_config_dword(pAC->PciDev, PciAddr, Val);
18093 +       return(0);
18094 +} /* SkPciWriteCfgDWord */
18095 +
18096 +
18097 +/*****************************************************************************
18098 + *
18099   *     SkPciWriteCfgWord - write a 16 bit value to pci config space
18100   *
18101   * Description:
18102 @@ -4036,29 +5234,27 @@
18103   *
18104   */
18105  int SkDrvEvent(
18106 -SK_AC *pAC,            /* pointer to adapter context */
18107 -SK_IOC IoC,            /* io-context */
18108 -SK_U32 Event,          /* event-id */
18109 -SK_EVPARA Param)       /* event-parameter */
18110 -{
18111 -SK_MBUF                *pRlmtMbuf;     /* pointer to a rlmt-mbuf structure */
18112 -struct sk_buff *pMsg;          /* pointer to a message block */
18113 -int            FromPort;       /* the port from which we switch away */
18114 -int            ToPort;         /* the port we switch to */
18115 -SK_EVPARA      NewPara;        /* parameter for further events */
18116 -int            Stat;
18117 -unsigned long  Flags;
18118 -SK_BOOL                DualNet;
18119 +SK_AC     *pAC,    /* pointer to adapter context */
18120 +SK_IOC     IoC,    /* IO control context         */
18121 +SK_U32     Event,  /* event-id                   */
18122 +SK_EVPARA  Param)  /* event-parameter            */
18123 +{
18124 +       SK_MBUF         *pRlmtMbuf;   /* pointer to a rlmt-mbuf structure   */
18125 +       struct sk_buff  *pMsg;        /* pointer to a message block         */
18126 +       SK_BOOL          DualNet;
18127 +       SK_U32           Reason;
18128 +       unsigned long    Flags;
18129 +       unsigned long    InitFlags;
18130 +       int              FromPort;    /* the port from which we switch away */
18131 +       int              ToPort;      /* the port we switch to              */
18132 +       int              Stat;
18133 +       DEV_NET         *pNet = NULL;
18134 +#ifdef CONFIG_SK98LIN_NAPI
18135 +       int              WorkToDo = 1; /* min(*budget, dev->quota); */
18136 +       int              WorkDone = 0;
18137 +#endif
18138
18139         switch (Event) {
18140 -       case SK_DRV_ADAP_FAIL:
18141 -               SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18142 -                       ("ADAPTER FAIL EVENT\n"));
18143 -               printk("%s: Adapter failed.\n", pAC->dev[0]->name);
18144 -               /* disable interrupts */
18145 -               SK_OUT32(pAC->IoBase, B0_IMSK, 0);
18146 -               /* cgoos */
18147 -               break;
18148         case SK_DRV_PORT_FAIL:
18149                 FromPort = Param.Para32[0];
18150                 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18151 @@ -4068,210 +5264,300 @@
18152                 } else {
18153                         printk("%s: Port B failed.\n", pAC->dev[1]->name);
18154                 }
18155 -               /* cgoos */
18156                 break;
18157 -       case SK_DRV_PORT_RESET:  /* SK_U32 PortIdx */
18158 -               /* action list 4 */
18159 +       case SK_DRV_PORT_RESET:
18160                 FromPort = Param.Para32[0];
18161                 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18162                         ("PORT RESET EVENT, Port: %d ", FromPort));
18163 -               NewPara.Para64 = FromPort;
18164 -               SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_XMAC_RESET, NewPara);
18165 +               SkLocalEventQueue64(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET,
18166 +                                       FromPort, SK_FALSE);
18167                 spin_lock_irqsave(
18168                         &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18169                         Flags);
18170 -
18171 -               SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_HARD_RST);
18172 -               netif_carrier_off(pAC->dev[Param.Para32[0]]);
18173 +               if (CHIP_ID_YUKON_2(pAC)) {
18174 +                       SkY2PortStop(pAC, IoC, FromPort, SK_STOP_ALL, SK_HARD_RST);
18175 +               } else {
18176 +                       SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_HARD_RST);
18177 +               }
18178 +               pAC->dev[Param.Para32[0]]->flags &= ~IFF_RUNNING;
18179                 spin_unlock_irqrestore(
18180                         &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18181                         Flags);
18182
18183 -               /* clear rx ring from received frames */
18184 -               ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE);
18185 -
18186 -               ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
18187 +               if (!CHIP_ID_YUKON_2(pAC)) {
18188 +#ifdef CONFIG_SK98LIN_NAPI
18189 +                       WorkToDo = 1;
18190 +                       ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE, &WorkDone, WorkToDo);
18191 +#else
18192 +                       ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE);
18193 +#endif
18194 +                       ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
18195 +               }
18196                 spin_lock_irqsave(
18197                         &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18198                         Flags);
18199 -
18200 -               /* tschilling: Handling of return value inserted. */
18201 -               if (SkGeInitPort(pAC, IoC, FromPort)) {
18202 -                       if (FromPort == 0) {
18203 -                               printk("%s: SkGeInitPort A failed.\n", pAC->dev[0]->name);
18204 +
18205 +#ifdef USE_TIST_FOR_RESET
18206 +                if (pAC->GIni.GIYukon2) {
18207 +#ifdef Y2_RECOVERY
18208 +                       /* for Yukon II we want to have tist enabled all the time */
18209 +                       if (!SK_ADAPTER_WAITING_FOR_TIST(pAC)) {
18210 +                               Y2_ENABLE_TIST(pAC->IoBase);
18211 +                       }
18212 +#else
18213 +                       /* make sure that we do not accept any status LEs from now on */
18214 +                       if (SK_ADAPTER_WAITING_FOR_TIST(pAC)) {
18215 +#endif
18216 +                               /* port already waiting for tist */
18217 +                               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
18218 +                                       ("Port %c is now waiting for specific Tist\n",
18219 +                                       'A' +  FromPort));
18220 +                               SK_SET_WAIT_BIT_FOR_PORT(
18221 +                                       pAC,
18222 +                                       SK_PSTATE_WAITING_FOR_SPECIFIC_TIST,
18223 +                                       FromPort);
18224 +                               /* get current timestamp */
18225 +                               Y2_GET_TIST_LOW_VAL(pAC->IoBase, &pAC->MinTistLo);
18226 +                               pAC->MinTistHi = pAC->GIni.GITimeStampCnt;
18227 +#ifndef Y2_RECOVERY
18228                         } else {
18229 -                               printk("%s: SkGeInitPort B failed.\n", pAC->dev[1]->name);
18230 +                               /* nobody is waiting yet */
18231 +                               SK_SET_WAIT_BIT_FOR_PORT(
18232 +                                       pAC,
18233 +                                       SK_PSTATE_WAITING_FOR_ANY_TIST,
18234 +                                       FromPort);
18235 +                               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
18236 +                                       ("Port %c is now waiting for any Tist (0x%X)\n",
18237 +                                       'A' +  FromPort, pAC->AdapterResetState));
18238 +                               /* start tist */
18239 +                               Y2_ENABLE_TIST(pAC-IoBase);
18240 +                       }
18241 +#endif
18242 +               }
18243 +#endif
18244 +
18245 +#ifdef Y2_LE_CHECK
18246 +               /* mark entries invalid */
18247 +               pAC->LastPort = 3;
18248 +               pAC->LastOpc = 0xFF;
18249 +#endif
18250 +               if (CHIP_ID_YUKON_2(pAC)) {
18251 +                       SkY2PortStart(pAC, IoC, FromPort);
18252 +               } else {
18253 +                       /* tschilling: Handling of return value inserted. */
18254 +                       if (SkGeInitPort(pAC, IoC, FromPort)) {
18255 +                               if (FromPort == 0) {
18256 +                                       printk("%s: SkGeInitPort A failed.\n", pAC->dev[0]->name);
18257 +                               } else {
18258 +                                       printk("%s: SkGeInitPort B failed.\n", pAC->dev[1]->name);
18259 +                               }
18260                         }
18261 +                       SkAddrMcUpdate(pAC,IoC, FromPort);
18262 +                       PortReInitBmu(pAC, FromPort);
18263 +                       SkGePollTxD(pAC, IoC, FromPort, SK_TRUE);
18264 +                       CLEAR_AND_START_RX(FromPort);
18265                 }
18266 -               SkAddrMcUpdate(pAC,IoC, FromPort);
18267 -               PortReInitBmu(pAC, FromPort);
18268 -               SkGePollTxD(pAC, IoC, FromPort, SK_TRUE);
18269 -               ClearAndStartRx(pAC, FromPort);
18270                 spin_unlock_irqrestore(
18271                         &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18272                         Flags);
18273                 break;
18274 -       case SK_DRV_NET_UP:      /* SK_U32 PortIdx */
18275 -       {       struct net_device *dev = pAC->dev[Param.Para32[0]];
18276 -               /* action list 5 */
18277 +       case SK_DRV_NET_UP:
18278 +               spin_lock_irqsave(&pAC->InitLock, InitFlags);
18279                 FromPort = Param.Para32[0];
18280                 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18281 -                       ("NET UP EVENT, Port: %d ", Param.Para32[0]));
18282 -               /* Mac update */
18283 -               SkAddrMcUpdate(pAC,IoC, FromPort);
18284 -
18285 +                       ("NET UP EVENT, Port: %d ", FromPort));
18286 +               SkAddrMcUpdate(pAC,IoC, FromPort); /* Mac update */
18287                 if (DoPrintInterfaceChange) {
18288 -               printk("%s: network connection up using"
18289 -                       " port %c\n", pAC->dev[Param.Para32[0]]->name, 'A'+Param.Para32[0]);
18290 +                       printk("%s: network connection up using port %c\n",
18291 +                               pAC->dev[FromPort]->name, 'A'+FromPort);
18292
18293 -               /* tschilling: Values changed according to LinkSpeedUsed. */
18294 -               Stat = pAC->GIni.GP[FromPort].PLinkSpeedUsed;
18295 -               if (Stat == SK_LSPEED_STAT_10MBPS) {
18296 -                       printk("    speed:           10\n");
18297 -               } else if (Stat == SK_LSPEED_STAT_100MBPS) {
18298 -                       printk("    speed:           100\n");
18299 -               } else if (Stat == SK_LSPEED_STAT_1000MBPS) {
18300 -                       printk("    speed:           1000\n");
18301 -               } else {
18302 -                       printk("    speed:           unknown\n");
18303 -               }
18304 +                       /* tschilling: Values changed according to LinkSpeedUsed. */
18305 +                       Stat = pAC->GIni.GP[FromPort].PLinkSpeedUsed;
18306 +                       if (Stat == SK_LSPEED_STAT_10MBPS) {
18307 +                               printk("    speed:           10\n");
18308 +                       } else if (Stat == SK_LSPEED_STAT_100MBPS) {
18309 +                               printk("    speed:           100\n");
18310 +                       } else if (Stat == SK_LSPEED_STAT_1000MBPS) {
18311 +                               printk("    speed:           1000\n");
18312 +                       } else {
18313 +                               printk("    speed:           unknown\n");
18314 +                       }
18315
18316 +                       Stat = pAC->GIni.GP[FromPort].PLinkModeStatus;
18317 +                       if ((Stat == SK_LMODE_STAT_AUTOHALF) ||
18318 +                           (Stat == SK_LMODE_STAT_AUTOFULL)) {
18319 +                               printk("    autonegotiation: yes\n");
18320 +                       } else {
18321 +                               printk("    autonegotiation: no\n");
18322 +                       }
18323
18324 -               Stat = pAC->GIni.GP[FromPort].PLinkModeStatus;
18325 -               if (Stat == SK_LMODE_STAT_AUTOHALF ||
18326 -                       Stat == SK_LMODE_STAT_AUTOFULL) {
18327 -                       printk("    autonegotiation: yes\n");
18328 -               }
18329 -               else {
18330 -                       printk("    autonegotiation: no\n");
18331 -               }
18332 -               if (Stat == SK_LMODE_STAT_AUTOHALF ||
18333 -                       Stat == SK_LMODE_STAT_HALF) {
18334 -                       printk("    duplex mode:     half\n");
18335 -               }
18336 -               else {
18337 -                       printk("    duplex mode:     full\n");
18338 -               }
18339 -               Stat = pAC->GIni.GP[FromPort].PFlowCtrlStatus;
18340 -               if (Stat == SK_FLOW_STAT_REM_SEND ) {
18341 -                       printk("    flowctrl:        remote send\n");
18342 -               }
18343 -               else if (Stat == SK_FLOW_STAT_LOC_SEND ){
18344 -                       printk("    flowctrl:        local send\n");
18345 -               }
18346 -               else if (Stat == SK_FLOW_STAT_SYMMETRIC ){
18347 -                       printk("    flowctrl:        symmetric\n");
18348 -               }
18349 -               else {
18350 -                       printk("    flowctrl:        none\n");
18351 -               }
18352 -
18353 -               /* tschilling: Check against CopperType now. */
18354 -               if ((pAC->GIni.GICopperType == SK_TRUE) &&
18355 -                       (pAC->GIni.GP[FromPort].PLinkSpeedUsed ==
18356 -                       SK_LSPEED_STAT_1000MBPS)) {
18357 -                       Stat = pAC->GIni.GP[FromPort].PMSStatus;
18358 -                       if (Stat == SK_MS_STAT_MASTER ) {
18359 -                               printk("    role:            master\n");
18360 +                       if ((Stat == SK_LMODE_STAT_AUTOHALF) ||
18361 +                           (Stat == SK_LMODE_STAT_HALF)) {
18362 +                               printk("    duplex mode:     half\n");
18363 +                       } else {
18364 +                               printk("    duplex mode:     full\n");
18365                         }
18366 -                       else if (Stat == SK_MS_STAT_SLAVE ) {
18367 -                               printk("    role:            slave\n");
18368 +
18369 +                       Stat = pAC->GIni.GP[FromPort].PFlowCtrlStatus;
18370 +                       if (Stat == SK_FLOW_STAT_REM_SEND ) {
18371 +                               printk("    flowctrl:        remote send\n");
18372 +                       } else if (Stat == SK_FLOW_STAT_LOC_SEND ) {
18373 +                               printk("    flowctrl:        local send\n");
18374 +                       } else if (Stat == SK_FLOW_STAT_SYMMETRIC ) {
18375 +                               printk("    flowctrl:        symmetric\n");
18376 +                       } else {
18377 +                               printk("    flowctrl:        none\n");
18378                         }
18379 -                       else {
18380 -                               printk("    role:            ???\n");
18381 +
18382 +                       /* tschilling: Check against CopperType now. */
18383 +                       if ((pAC->GIni.GICopperType == SK_TRUE) &&
18384 +                               (pAC->GIni.GP[FromPort].PLinkSpeedUsed ==
18385 +                               SK_LSPEED_STAT_1000MBPS)) {
18386 +                               Stat = pAC->GIni.GP[FromPort].PMSStatus;
18387 +                               if (Stat == SK_MS_STAT_MASTER ) {
18388 +                                       printk("    role:            master\n");
18389 +                               } else if (Stat == SK_MS_STAT_SLAVE ) {
18390 +                                       printk("    role:            slave\n");
18391 +                               } else {
18392 +                                       printk("    role:            ???\n");
18393 +                               }
18394                         }
18395 -               }
18396
18397 -               /*
18398 -                  Display dim (dynamic interrupt moderation)
18399 -                  informations
18400 -                */
18401 -               if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_STATIC)
18402 -                       printk("    irq moderation:  static (%d ints/sec)\n",
18403 +                       /* Display interrupt moderation informations */
18404 +                       if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_STATIC) {
18405 +                               printk("    irq moderation:  static (%d ints/sec)\n",
18406                                         pAC->DynIrqModInfo.MaxModIntsPerSec);
18407 -               else if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_DYNAMIC)
18408 -                       printk("    irq moderation:  dynamic (%d ints/sec)\n",
18409 +                       } else if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
18410 +                               printk("    irq moderation:  dynamic (%d ints/sec)\n",
18411                                         pAC->DynIrqModInfo.MaxModIntsPerSec);
18412 -               else
18413 -                       printk("    irq moderation:  disabled\n");
18414 +                       } else {
18415 +                               printk("    irq moderation:  disabled\n");
18416 +                       }
18417 +
18418 +#ifdef NETIF_F_TSO
18419 +                       if (CHIP_ID_YUKON_2(pAC)) {
18420 +                               if (pAC->dev[FromPort]->features & NETIF_F_TSO) {
18421 +                                       printk("    tcp offload:     enabled\n");
18422 +                               } else {
18423 +                                       printk("    tcp offload:     disabled\n");
18424 +                               }
18425 +                       }
18426 +#endif
18427 +
18428 +                       if (pAC->dev[FromPort]->features & NETIF_F_SG) {
18429 +                               printk("    scatter-gather:  enabled\n");
18430 +                       } else {
18431 +                               printk("    scatter-gather:  disabled\n");
18432 +                       }
18433
18434 +                       if (pAC->dev[FromPort]->features & NETIF_F_IP_CSUM) {
18435 +                               printk("    tx-checksum:     enabled\n");
18436 +                       } else {
18437 +                               printk("    tx-checksum:     disabled\n");
18438 +                       }
18439
18440 -               printk("    scatter-gather:  %s\n",
18441 -                      (dev->features & NETIF_F_SG) ? "enabled" : "disabled");
18442 -               printk("    tx-checksum:     %s\n",
18443 -                      (dev->features & NETIF_F_IP_CSUM) ? "enabled" : "disabled");
18444 -               printk("    rx-checksum:     %s\n",
18445 -                      pAC->RxPort[Param.Para32[0]].RxCsum ? "enabled" : "disabled");
18446 +                       if (pAC->RxPort[FromPort].UseRxCsum) {
18447 +                               printk("    rx-checksum:     enabled\n");
18448 +                       } else {
18449 +                               printk("    rx-checksum:     disabled\n");
18450 +                       }
18451 +#ifdef CONFIG_SK98LIN_NAPI
18452 +                               printk("    rx-polling:      enabled\n");
18453 +#endif
18454 +                       if (pAC->LowLatency) {
18455 +                               printk("    low latency:     enabled\n");
18456 +                       }
18457
18458 +                       if (pAC->Rlmt.Net[0].ChgBcPrio) {
18459 +                               printk("    broadcast prio:  enabled\n");
18460 +                       }
18461                 } else {
18462 -                        DoPrintInterfaceChange = SK_TRUE;
18463 -                }
18464 +                       DoPrintInterfaceChange = SK_TRUE;
18465 +               }
18466
18467 -               if ((Param.Para32[0] != pAC->ActivePort) &&
18468 -                       (pAC->RlmtNets == 1)) {
18469 -                       NewPara.Para32[0] = pAC->ActivePort;
18470 -                       NewPara.Para32[1] = Param.Para32[0];
18471 -                       SkEventQueue(pAC, SKGE_DRV, SK_DRV_SWITCH_INTERN,
18472 -                               NewPara);
18473 +               if ((FromPort != pAC->ActivePort)&&(pAC->RlmtNets == 1)) {
18474 +                       SkLocalEventQueue(pAC, SKGE_DRV, SK_DRV_SWITCH_INTERN,
18475 +                                               pAC->ActivePort, FromPort, SK_FALSE);
18476                 }
18477
18478                 /* Inform the world that link protocol is up. */
18479 -               netif_carrier_on(dev);
18480 +               netif_wake_queue(pAC->dev[FromPort]);
18481 +               netif_carrier_on(pAC->dev[FromPort]);
18482 +               pAC->dev[FromPort]->flags |= IFF_RUNNING;
18483 +               spin_unlock_irqrestore(&pAC->InitLock, InitFlags);
18484                 break;
18485 -       }
18486 -       case SK_DRV_NET_DOWN:    /* SK_U32 Reason */
18487 -               /* action list 7 */
18488 +       case SK_DRV_NET_DOWN:
18489 +               Reason   = Param.Para32[0];
18490 +               FromPort = Param.Para32[1];
18491                 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18492                         ("NET DOWN EVENT "));
18493 +
18494 +               /* Stop queue and carrier */
18495 +               netif_stop_queue(pAC->dev[FromPort]);
18496 +               netif_carrier_off(pAC->dev[FromPort]);
18497 +
18498 +               /* Print link change */
18499                 if (DoPrintInterfaceChange) {
18500 -                       printk("%s: network connection down\n",
18501 -                               pAC->dev[Param.Para32[1]]->name);
18502 +                       if (pAC->dev[FromPort]->flags & IFF_RUNNING) {
18503 +                               printk("%s: network connection down\n",
18504 +                                       pAC->dev[FromPort]->name);
18505 +                       }
18506                 } else {
18507                         DoPrintInterfaceChange = SK_TRUE;
18508                 }
18509 -               netif_carrier_off(pAC->dev[Param.Para32[1]]);
18510 +               pAC->dev[FromPort]->flags &= ~IFF_RUNNING;
18511                 break;
18512 -       case SK_DRV_SWITCH_HARD: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */
18513 -               SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18514 -                       ("PORT SWITCH HARD "));
18515 -       case SK_DRV_SWITCH_SOFT: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */
18516 -       /* action list 6 */
18517 -               printk("%s: switching to port %c\n", pAC->dev[0]->name,
18518 -                       'A'+Param.Para32[1]);
18519 -       case SK_DRV_SWITCH_INTERN: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */
18520 +       case SK_DRV_SWITCH_HARD:   /* FALL THRU */
18521 +       case SK_DRV_SWITCH_SOFT:   /* FALL THRU */
18522 +       case SK_DRV_SWITCH_INTERN:
18523                 FromPort = Param.Para32[0];
18524 -               ToPort = Param.Para32[1];
18525 +               ToPort   = Param.Para32[1];
18526 +               printk("%s: switching from port %c to port %c\n",
18527 +                       pAC->dev[0]->name, 'A'+FromPort, 'A'+ToPort);
18528                 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18529                         ("PORT SWITCH EVENT, From: %d  To: %d (Pref %d) ",
18530                         FromPort, ToPort, pAC->Rlmt.Net[0].PrefPort));
18531 -               NewPara.Para64 = FromPort;
18532 -               SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_XMAC_RESET, NewPara);
18533 -               NewPara.Para64 = ToPort;
18534 -               SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_XMAC_RESET, NewPara);
18535 +               SkLocalEventQueue64(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET,
18536 +                                       FromPort, SK_FALSE);
18537 +               SkLocalEventQueue64(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET,
18538 +                                       ToPort, SK_FALSE);
18539                 spin_lock_irqsave(
18540                         &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18541                         Flags);
18542                 spin_lock(&pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock);
18543 -               SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST);
18544 -               SkGeStopPort(pAC, IoC, ToPort, SK_STOP_ALL, SK_SOFT_RST);
18545 +               if (CHIP_ID_YUKON_2(pAC)) {
18546 +                       SkY2PortStop(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST);
18547 +                       SkY2PortStop(pAC, IoC, ToPort, SK_STOP_ALL, SK_SOFT_RST);
18548 +               }
18549 +               else {
18550 +                       SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST);
18551 +                       SkGeStopPort(pAC, IoC, ToPort, SK_STOP_ALL, SK_SOFT_RST);
18552 +               }
18553                 spin_unlock(&pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock);
18554                 spin_unlock_irqrestore(
18555                         &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18556                         Flags);
18557
18558 -               ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE); /* clears rx ring */
18559 -               ReceiveIrq(pAC, &pAC->RxPort[ToPort], SK_FALSE); /* clears rx ring */
18560
18561 -               ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
18562 -               ClearTxRing(pAC, &pAC->TxPort[ToPort][TX_PRIO_LOW]);
18563 +               if (!CHIP_ID_YUKON_2(pAC)) {
18564 +#ifdef CONFIG_SK98LIN_NAPI
18565 +                       WorkToDo = 1;
18566 +                       ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE, &WorkDone, WorkToDo);
18567 +                       ReceiveIrq(pAC, &pAC->RxPort[ToPort], SK_FALSE, &WorkDone, WorkToDo);
18568 +#else
18569 +                       ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE); /* clears rx ring */
18570 +                       ReceiveIrq(pAC, &pAC->RxPort[ToPort], SK_FALSE); /* clears rx ring */
18571 +#endif
18572 +                       ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
18573 +                       ClearTxRing(pAC, &pAC->TxPort[ToPort][TX_PRIO_LOW]);
18574 +               }
18575 +
18576                 spin_lock_irqsave(
18577                         &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18578                         Flags);
18579                 spin_lock(&pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock);
18580                 pAC->ActivePort = ToPort;
18581 -#if 0
18582 -               SetQueueSizes(pAC);
18583 -#else
18584 +
18585                 /* tschilling: New common function with minimum size check. */
18586                 DualNet = SK_FALSE;
18587                 if (pAC->RlmtNets == 2) {
18588 @@ -4289,74 +5575,316 @@
18589                         printk("SkGeInitAssignRamToQueues failed.\n");
18590                         break;
18591                 }
18592 -#endif
18593 -               /* tschilling: Handling of return values inserted. */
18594 -               if (SkGeInitPort(pAC, IoC, FromPort) ||
18595 -                       SkGeInitPort(pAC, IoC, ToPort)) {
18596 -                       printk("%s: SkGeInitPort failed.\n", pAC->dev[0]->name);
18597 +
18598 +               if (!CHIP_ID_YUKON_2(pAC)) {
18599 +                       /* tschilling: Handling of return values inserted. */
18600 +                       if (SkGeInitPort(pAC, IoC, FromPort) ||
18601 +                               SkGeInitPort(pAC, IoC, ToPort)) {
18602 +                               printk("%s: SkGeInitPort failed.\n", pAC->dev[0]->name);
18603 +                       }
18604                 }
18605 -               if (Event == SK_DRV_SWITCH_SOFT) {
18606 -                       SkMacRxTxEnable(pAC, IoC, FromPort);
18607 +               if (!CHIP_ID_YUKON_2(pAC)) {
18608 +                       if (Event == SK_DRV_SWITCH_SOFT) {
18609 +                               SkMacRxTxEnable(pAC, IoC, FromPort);
18610 +                       }
18611 +                       SkMacRxTxEnable(pAC, IoC, ToPort);
18612                 }
18613 -               SkMacRxTxEnable(pAC, IoC, ToPort);
18614 +
18615                 SkAddrSwap(pAC, IoC, FromPort, ToPort);
18616                 SkAddrMcUpdate(pAC, IoC, FromPort);
18617                 SkAddrMcUpdate(pAC, IoC, ToPort);
18618 -               PortReInitBmu(pAC, FromPort);
18619 -               PortReInitBmu(pAC, ToPort);
18620 -               SkGePollTxD(pAC, IoC, FromPort, SK_TRUE);
18621 -               SkGePollTxD(pAC, IoC, ToPort, SK_TRUE);
18622 -               ClearAndStartRx(pAC, FromPort);
18623 -               ClearAndStartRx(pAC, ToPort);
18624 +
18625 +#ifdef USE_TIST_FOR_RESET
18626 +                if (pAC->GIni.GIYukon2) {
18627 +                       /* make sure that we do not accept any status LEs from now on */
18628 +                       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
18629 +                               ("both Ports now waiting for specific Tist\n"));
18630 +                       SK_SET_WAIT_BIT_FOR_PORT(
18631 +                               pAC,
18632 +                               SK_PSTATE_WAITING_FOR_ANY_TIST,
18633 +                               0);
18634 +                       SK_SET_WAIT_BIT_FOR_PORT(
18635 +                               pAC,
18636 +                               SK_PSTATE_WAITING_FOR_ANY_TIST,
18637 +                               1);
18638 +
18639 +                       /* start tist */
18640 +                       Y2_ENABLE_TIST(pAC->IoBase);
18641 +               }
18642 +#endif
18643 +               if (!CHIP_ID_YUKON_2(pAC)) {
18644 +                       PortReInitBmu(pAC, FromPort);
18645 +                       PortReInitBmu(pAC, ToPort);
18646 +                       SkGePollTxD(pAC, IoC, FromPort, SK_TRUE);
18647 +                       SkGePollTxD(pAC, IoC, ToPort, SK_TRUE);
18648 +                       CLEAR_AND_START_RX(FromPort);
18649 +                       CLEAR_AND_START_RX(ToPort);
18650 +               } else {
18651 +                       SkY2PortStart(pAC, IoC, FromPort);
18652 +                       SkY2PortStart(pAC, IoC, ToPort);
18653 +#ifdef SK_YUKON2
18654 +                       /* in yukon-II always port 0 has to be started first */
18655 +                       // SkY2PortStart(pAC, IoC, 0);
18656 +                       // SkY2PortStart(pAC, IoC, 1);
18657 +#endif
18658 +               }
18659                 spin_unlock(&pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock);
18660                 spin_unlock_irqrestore(
18661                         &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18662                         Flags);
18663                 break;
18664         case SK_DRV_RLMT_SEND:   /* SK_MBUF *pMb */
18665 -               SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18666 -                       ("RLS "));
18667 +               SK_DBG_MSG(NULL,SK_DBGMOD_DRV,SK_DBGCAT_DRV_EVENT,("RLS "));
18668                 pRlmtMbuf = (SK_MBUF*) Param.pParaPtr;
18669                 pMsg = (struct sk_buff*) pRlmtMbuf->pOs;
18670                 skb_put(pMsg, pRlmtMbuf->Length);
18671 -               if (XmitFrame(pAC, &pAC->TxPort[pRlmtMbuf->PortIdx][TX_PRIO_LOW],
18672 -                       pMsg) < 0)
18673 +               if (!CHIP_ID_YUKON_2(pAC)) {
18674 +                       if (XmitFrame(pAC, &pAC->TxPort[pRlmtMbuf->PortIdx][TX_PRIO_LOW],
18675 +                               pMsg) < 0) {
18676 +                               DEV_KFREE_SKB_ANY(pMsg);
18677 +                       }
18678 +               } else {
18679 +                       if (SkY2RlmtSend(pAC, pRlmtMbuf->PortIdx, pMsg) < 0) {
18680 +                               DEV_KFREE_SKB_ANY(pMsg);
18681 +                       }
18682 +               }
18683 +               break;
18684 +       case SK_DRV_TIMER:
18685 +               if (Param.Para32[0] == SK_DRV_MODERATION_TIMER) {
18686 +                       /* check what IRQs are to be moderated */
18687 +                       SkDimStartModerationTimer(pAC);
18688 +                       SkDimModerate(pAC);
18689 +               } else {
18690 +                       printk("Expiration of unknown timer\n");
18691 +               }
18692 +               break;
18693 +       case SK_DRV_ADAP_FAIL:
18694 +#if (!defined (Y2_RECOVERY) && !defined (Y2_LE_CHECK))
18695 +               SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18696 +                       ("ADAPTER FAIL EVENT\n"));
18697 +               printk("%s: Adapter failed.\n", pAC->dev[0]->name);
18698 +               SK_OUT32(pAC->IoBase, B0_IMSK, 0); /* disable interrupts */
18699 +               break;
18700 +#endif
18701 +
18702 +#if (defined (Y2_RECOVERY) || defined (Y2_LE_CHECK))
18703 +       case SK_DRV_RECOVER:
18704 +               spin_lock_irqsave(&pAC->InitLock, InitFlags);
18705 +               pNet = (DEV_NET *) pAC->dev[Param.Para32[0]]->priv;
18706 +
18707 +               /* Recover already in progress */
18708 +               if (pNet->InRecover) {
18709 +                       break;
18710 +               }
18711 +
18712 +               netif_stop_queue(pAC->dev[Param.Para32[0]]); /* stop device if running */
18713 +               pNet->InRecover = SK_TRUE;
18714 +
18715 +               FromPort = Param.Para32[0];
18716 +               SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18717 +                       ("PORT RESET EVENT, Port: %d ", FromPort));
18718 +
18719 +               /* Disable interrupts */
18720 +               SK_OUT32(pAC->IoBase, B0_IMSK, 0);
18721 +               SK_OUT32(pAC->IoBase, B0_HWE_IMSK, 0);
18722 +
18723 +               SkLocalEventQueue64(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET,
18724 +                                       FromPort, SK_FALSE);
18725 +               spin_lock_irqsave(
18726 +                       &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18727 +                       Flags);
18728 +               if (CHIP_ID_YUKON_2(pAC)) {
18729 +                       SkY2PortStop(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST);
18730 +               } else {
18731 +                       SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST);
18732 +               }
18733 +               pAC->dev[Param.Para32[0]]->flags &= ~IFF_RUNNING;
18734 +               spin_unlock_irqrestore(
18735 +                       &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18736 +                       Flags);
18737 +
18738 +               if (!CHIP_ID_YUKON_2(pAC)) {
18739 +#ifdef CONFIG_SK98LIN_NAPI
18740 +                       WorkToDo = 1;
18741 +                       ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE, &WorkDone, WorkToDo);
18742 +#else
18743 +                       ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE);
18744 +#endif
18745 +                       ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
18746 +               }
18747 +               spin_lock_irqsave(
18748 +                       &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18749 +                       Flags);
18750 +
18751 +#ifdef USE_TIST_FOR_RESET
18752 +               if (pAC->GIni.GIYukon2) {
18753 +#if 0
18754 +                       /* make sure that we do not accept any status LEs from now on */
18755 +                       Y2_ENABLE_TIST(pAC->IoBase);
18756 +
18757 +                       /* get current timestamp */
18758 +                       Y2_GET_TIST_LOW_VAL(pAC->IoBase, &pAC->MinTistLo);
18759 +                       pAC->MinTistHi = pAC->GIni.GITimeStampCnt;
18760 +
18761 +                       SK_SET_WAIT_BIT_FOR_PORT(
18762 +                               pAC,
18763 +                               SK_PSTATE_WAITING_FOR_SPECIFIC_TIST,
18764 +                               FromPort);
18765 +#endif
18766 +                       SK_SET_WAIT_BIT_FOR_PORT(
18767 +                               pAC,
18768 +                               SK_PSTATE_WAITING_FOR_ANY_TIST,
18769 +                               FromPort);
18770 +
18771 +                       /* start tist */
18772 +                        Y2_ENABLE_TIST(pAC->IoBase);
18773 +               }
18774 +#endif
18775 +
18776 +               /* Restart Receive BMU on Yukon-2 */
18777 +               if (HW_FEATURE(pAC, HWF_WA_DEV_4167)) {
18778 +                       SkYuk2RestartRxBmu(pAC, IoC, FromPort);
18779 +               }
18780 +
18781 +#ifdef Y2_LE_CHECK
18782 +               /* mark entries invalid */
18783 +               pAC->LastPort = 3;
18784 +               pAC->LastOpc = 0xFF;
18785 +#endif
18786 +
18787 +#endif
18788 +               /* Restart ports but do not initialize PHY. */
18789 +               if (CHIP_ID_YUKON_2(pAC)) {
18790 +                       SkY2PortStart(pAC, IoC, FromPort);
18791 +               } else {
18792 +                       /* tschilling: Handling of return value inserted. */
18793 +                       if (SkGeInitPort(pAC, IoC, FromPort)) {
18794 +                               if (FromPort == 0) {
18795 +                                       printk("%s: SkGeInitPort A failed.\n", pAC->dev[0]->name);
18796 +                               } else {
18797 +                                       printk("%s: SkGeInitPort B failed.\n", pAC->dev[1]->name);
18798 +                               }
18799 +                       }
18800 +                       SkAddrMcUpdate(pAC,IoC, FromPort);
18801 +                       PortReInitBmu(pAC, FromPort);
18802 +                       SkGePollTxD(pAC, IoC, FromPort, SK_TRUE);
18803 +                       CLEAR_AND_START_RX(FromPort);
18804 +               }
18805 +               spin_unlock_irqrestore(
18806 +                       &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18807 +                       Flags);
18808 +
18809 +               /* Map any waiting RX buffers to HW */
18810 +               FillReceiveTableYukon2(pAC, pAC->IoBase, FromPort);
18811 +
18812 +               pNet->InRecover = SK_FALSE;
18813 +               /* enable Interrupts */
18814 +               SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
18815 +               SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK);
18816 +               netif_wake_queue(pAC->dev[FromPort]);
18817 +               spin_unlock_irqrestore(&pAC->InitLock, InitFlags);
18818 +               break;
18819 +       default:
18820 +               break;
18821 +       }
18822 +       SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18823 +               ("END EVENT "));
18824 +
18825 +       return (0);
18826 +} /* SkDrvEvent */
18827 +
18828 +
18829 +/******************************************************************************
18830 + *
18831 + *     SkLocalEventQueue()     -       add event to queue
18832 + *
18833 + * Description:
18834 + *     This function adds an event to the event queue and run the
18835 + *     SkEventDispatcher. At least Init Level 1 is required to queue events,
18836 + *     but will be scheduled add Init Level 2.
18837 + *
18838 + * returns:
18839 + *     nothing
18840 + */
18841 +void SkLocalEventQueue(
18842 +SK_AC *pAC,            /* Adapters context */
18843 +SK_U32 Class,          /* Event Class */
18844 +SK_U32 Event,          /* Event to be queued */
18845 +SK_U32 Param1,         /* Event parameter 1 */
18846 +SK_U32 Param2,         /* Event parameter 2 */
18847 +SK_BOOL Dispatcher)    /* Dispatcher flag:
18848 +                        *      TRUE == Call SkEventDispatcher
18849 +                        *      FALSE == Don't execute SkEventDispatcher
18850 +                        */
18851 +{
18852 +       SK_EVPARA       EvPara;
18853 +       EvPara.Para32[0] = Param1;
18854 +       EvPara.Para32[1] = Param2;
18855 +
18856 +
18857 +       if (Class == SKGE_PNMI) {
18858 +               SkPnmiEvent(    pAC,
18859 +                               pAC->IoBase,
18860 +                               Event,
18861 +                               EvPara);
18862 +       } else {
18863 +               SkEventQueue(   pAC,
18864 +                               Class,
18865 +                               Event,
18866 +                               EvPara);
18867 +       }
18868 +
18869 +       /* Run the dispatcher */
18870 +       if (Dispatcher) {
18871 +               SkEventDispatcher(pAC, pAC->IoBase);
18872 +       }
18873 +
18874 +}
18875 +
18876 +/******************************************************************************
18877 + *
18878 + *     SkLocalEventQueue64()   -       add event to queue (64bit version)
18879 + *
18880 + * Description:
18881 + *     This function adds an event to the event queue and run the
18882 + *     SkEventDispatcher. At least Init Level 1 is required to queue events,
18883 + *     but will be scheduled add Init Level 2.
18884 + *
18885 + * returns:
18886 + *     nothing
18887 + */
18888 +void SkLocalEventQueue64(
18889 +SK_AC *pAC,            /* Adapters context */
18890 +SK_U32 Class,          /* Event Class */
18891 +SK_U32 Event,          /* Event to be queued */
18892 +SK_U64 Param,          /* Event parameter */
18893 +SK_BOOL Dispatcher)    /* Dispatcher flag:
18894 +                        *      TRUE == Call SkEventDispatcher
18895 +                        *      FALSE == Don't execute SkEventDispatcher
18896 +                        */
18897 +{
18898 +       SK_EVPARA       EvPara;
18899 +       EvPara.Para64 = Param;
18900 +
18901 +
18902 +       if (Class == SKGE_PNMI) {
18903 +               SkPnmiEvent(    pAC,
18904 +                               pAC->IoBase,
18905 +                               Event,
18906 +                               EvPara);
18907 +       } else {
18908 +               SkEventQueue(   pAC,
18909 +                               Class,
18910 +                               Event,
18911 +                               EvPara);
18912 +       }
18913
18914 -                       DEV_KFREE_SKB_ANY(pMsg);
18915 -               break;
18916 -       case SK_DRV_TIMER:
18917 -               if (Param.Para32[0] == SK_DRV_MODERATION_TIMER) {
18918 -                       /*
18919 -                       ** expiration of the moderation timer implies that
18920 -                       ** dynamic moderation is to be applied
18921 -                       */
18922 -                       SkDimStartModerationTimer(pAC);
18923 -                       SkDimModerate(pAC);
18924 -                        if (pAC->DynIrqModInfo.DisplayStats) {
18925 -                           SkDimDisplayModerationSettings(pAC);
18926 -                        }
18927 -                } else if (Param.Para32[0] == SK_DRV_RX_CLEANUP_TIMER) {
18928 -                       /*
18929 -                       ** check if we need to check for descriptors which
18930 -                       ** haven't been handled the last millisecs
18931 -                       */
18932 -                       StartDrvCleanupTimer(pAC);
18933 -                       if (pAC->GIni.GIMacsFound == 2) {
18934 -                               ReceiveIrq(pAC, &pAC->RxPort[1], SK_FALSE);
18935 -                       }
18936 -                       ReceiveIrq(pAC, &pAC->RxPort[0], SK_FALSE);
18937 -               } else {
18938 -                       printk("Expiration of unknown timer\n");
18939 -               }
18940 -               break;
18941 -       default:
18942 -               break;
18943 +       /* Run the dispatcher */
18944 +       if (Dispatcher) {
18945 +               SkEventDispatcher(pAC, pAC->IoBase);
18946         }
18947 -       SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18948 -               ("END EVENT "));
18949 -
18950 -       return (0);
18951 -} /* SkDrvEvent */
18952 +
18953 +}
18954
18955
18956  /*****************************************************************************
18957 @@ -4408,8 +5936,6 @@
18958
18959  } /* SkErrorLog */
18960
18961 -#ifdef SK_DIAG_SUPPORT
18962 -
18963  /*****************************************************************************
18964   *
18965   *     SkDrvEnterDiagMode - handles DIAG attach request
18966 @@ -4424,8 +5950,11 @@
18967  int SkDrvEnterDiagMode(
18968  SK_AC   *pAc)   /* pointer to adapter context */
18969  {
18970 -       DEV_NET *pNet = netdev_priv(pAc->dev[0]);
18971 -       SK_AC   *pAC  = pNet->pAC;
18972 +       SK_AC   *pAC  = NULL;
18973 +       DEV_NET *pNet = NULL;
18974 +
18975 +       pNet = (DEV_NET *) pAc->dev[0]->priv;
18976 +       pAC = pNet->pAC;
18977
18978         SK_MEMCPY(&(pAc->PnmiBackup), &(pAc->PnmiStruct),
18979                         sizeof(SK_PNMI_STRUCT_DATA));
18980 @@ -4440,8 +5969,9 @@
18981                 } else {
18982                         pAC->WasIfUp[0] = SK_FALSE;
18983                 }
18984 -               if (pNet != netdev_priv(pAC->dev[1])) {
18985 -                       pNet = netdev_priv(pAC->dev[1]);
18986 +
18987 +               if (pNet != (DEV_NET *) pAc->dev[1]->priv) {
18988 +                       pNet = (DEV_NET *) pAc->dev[1]->priv;
18989                         if (netif_running(pAC->dev[1])) {
18990                                 pAC->WasIfUp[1] = SK_TRUE;
18991                                 pAC->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */
18992 @@ -4474,16 +6004,16 @@
18993                         sizeof(SK_PNMI_STRUCT_DATA));
18994         pAc->DiagModeActive    = DIAG_NOTACTIVE;
18995         pAc->Pnmi.DiagAttached = SK_DIAG_IDLE;
18996 -        if (pAc->WasIfUp[0] == SK_TRUE) {
18997 -                pAc->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */
18998 +       if (pAc->WasIfUp[0] == SK_TRUE) {
18999 +               pAc->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */
19000                 DoPrintInterfaceChange = SK_FALSE;
19001 -                SkDrvInitAdapter(pAc, 0);    /* first device  */
19002 -        }
19003 -        if (pAc->WasIfUp[1] == SK_TRUE) {
19004 -                pAc->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */
19005 +               SkDrvInitAdapter(pAc, 0);    /* first device  */
19006 +       }
19007 +       if (pAc->WasIfUp[1] == SK_TRUE) {
19008 +               pAc->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */
19009                 DoPrintInterfaceChange = SK_FALSE;
19010 -                SkDrvInitAdapter(pAc, 1);    /* second device */
19011 -        }
19012 +               SkDrvInitAdapter(pAc, 1);    /* second device */
19013 +       }
19014         return(0);
19015  }
19016
19017 @@ -4563,11 +6093,20 @@
19018
19019         dev = pAC->dev[devNbr];
19020
19021 -       /* On Linux 2.6 the network driver does NOT mess with reference
19022 -       ** counts.  The driver MUST be able to be unloaded at any time
19023 -       ** due to the possibility of hotplug.
19024 +       /*
19025 +       ** Function SkGeClose() uses MOD_DEC_USE_COUNT (2.2/2.4)
19026 +       ** or module_put() (2.6) to decrease the number of users for
19027 +       ** a device, but if a device is to be put under control of
19028 +       ** the DIAG, that count is OK already and does not need to
19029 +       ** be adapted! Hence the opposite MOD_INC_USE_COUNT or
19030 +       ** try_module_get() needs to be used again to correct that.
19031         */
19032 +       if (!try_module_get(THIS_MODULE)) {
19033 +               return (-1);
19034 +       }
19035 +
19036         if (SkGeClose(dev) != 0) {
19037 +               module_put(THIS_MODULE);
19038                 return (-1);
19039         }
19040         return (0);
19041 @@ -4596,6 +6135,17 @@
19042
19043         if (SkGeOpen(dev) != 0) {
19044                 return (-1);
19045 +       } else {
19046 +               /*
19047 +               ** Function SkGeOpen() uses MOD_INC_USE_COUNT (2.2/2.4)
19048 +               ** or try_module_get() (2.6) to increase the number of
19049 +               ** users for a device, but if a device was just under
19050 +               ** control of the DIAG, that count is OK already and
19051 +               ** does not need to be adapted! Hence the opposite
19052 +               ** MOD_DEC_USE_COUNT or module_put() needs to be used
19053 +               ** again to correct that.
19054 +               */
19055 +               module_put(THIS_MODULE);
19056         }
19057
19058         /*
19059 @@ -4608,14 +6158,25 @@
19060
19061  } /* SkDrvInitAdapter */
19062
19063 -#endif
19064 +static int __init sk98lin_init(void)
19065 +{
19066 +       return pci_module_init(&sk98lin_driver);
19067 +}
19068 +
19069 +static void __exit sk98lin_cleanup(void)
19070 +{
19071 +       pci_unregister_driver(&sk98lin_driver);
19072 +}
19073 +
19074 +module_init(sk98lin_init);
19075 +module_exit(sk98lin_cleanup);
19076 +
19077
19078  #ifdef DEBUG
19079  /****************************************************************************/
19080  /* "debug only" section *****************************************************/
19081  /****************************************************************************/
19082
19083 -
19084  /*****************************************************************************
19085   *
19086   *     DumpMsg - print a frame
19087 @@ -4626,9 +6187,11 @@
19088   * Returns: N/A
19089   *
19090   */
19091 -static void DumpMsg(struct sk_buff *skb, char *str)
19092 +static void DumpMsg(
19093 +struct sk_buff *skb,  /* linux' socket buffer  */
19094 +char           *str)  /* additional msg string */
19095  {
19096 -       int     msglen;
19097 +       int msglen = (skb->len > 64) ? 64 : skb->len;
19098
19099         if (skb == NULL) {
19100                 printk("DumpMsg(): NULL-Message\n");
19101 @@ -4640,19 +6203,14 @@
19102                 return;
19103         }
19104
19105 -       msglen = skb->len;
19106 -       if (msglen > 64)
19107 -               msglen = 64;
19108 -
19109 -       printk("--- Begin of message from %s , len %d (from %d) ----\n", str, msglen, skb->len);
19110 -
19111 +       printk("DumpMsg: PhysPage: %p\n",
19112 +               page_address(virt_to_page(skb->data)));
19113 +       printk("--- Begin of message from %s , len %d (from %d) ----\n",
19114 +               str, msglen, skb->len);
19115         DumpData((char *)skb->data, msglen);
19116 -
19117         printk("------- End of message ---------\n");
19118  } /* DumpMsg */
19119
19120 -
19121 -
19122  /*****************************************************************************
19123   *
19124   *     DumpData - print a data area
19125 @@ -4664,23 +6222,22 @@
19126   * Returns: N/A
19127   *
19128   */
19129 -static void DumpData(char *p, int size)
19130 -{
19131 -register int    i;
19132 -int    haddr, addr;
19133 -char   hex_buffer[180];
19134 -char   asc_buffer[180];
19135 -char   HEXCHAR[] = "0123456789ABCDEF";
19136 -
19137 -       addr = 0;
19138 -       haddr = 0;
19139 -       hex_buffer[0] = 0;
19140 -       asc_buffer[0] = 0;
19141 +static void DumpData(
19142 +char  *p,     /* pointer to area containing the data */
19143 +int    size)  /* the size of that data area in bytes */
19144 +{
19145 +       register int  i;
19146 +       int           haddr = 0, addr = 0;
19147 +       char          hex_buffer[180] = { '\0' };
19148 +       char          asc_buffer[180] = { '\0' };
19149 +       char          HEXCHAR[] = "0123456789ABCDEF";
19150 +
19151         for (i=0; i < size; ) {
19152 -               if (*p >= '0' && *p <='z')
19153 +               if (*p >= '0' && *p <='z') {
19154                         asc_buffer[addr] = *p;
19155 -               else
19156 +               } else {
19157                         asc_buffer[addr] = '.';
19158 +               }
19159                 addr++;
19160                 asc_buffer[addr] = 0;
19161                 hex_buffer[haddr] = HEXCHAR[(*p & 0xf0) >> 4];
19162 @@ -4706,27 +6263,24 @@
19163   *     DumpLong - print a data area as long values
19164   *
19165   * Description:
19166 - *     This function prints a area of data to the system logfile/to the
19167 + *     This function prints a long variable to the system logfile/to the
19168   *     console.
19169   *
19170   * Returns: N/A
19171   *
19172   */
19173 -static void DumpLong(char *pc, int size)
19174 -{
19175 -register int    i;
19176 -int    haddr, addr;
19177 -char   hex_buffer[180];
19178 -char   asc_buffer[180];
19179 -char   HEXCHAR[] = "0123456789ABCDEF";
19180 -long   *p;
19181 -int    l;
19182 -
19183 -       addr = 0;
19184 -       haddr = 0;
19185 -       hex_buffer[0] = 0;
19186 -       asc_buffer[0] = 0;
19187 -       p = (long*) pc;
19188 +static void DumpLong(
19189 +char  *pc,    /* location of the variable to print */
19190 +int    size)  /* how large is the variable?        */
19191 +{
19192 +       register int   i;
19193 +       int            haddr = 0, addr = 0;
19194 +       char           hex_buffer[180] = { '\0' };
19195 +       char           asc_buffer[180] = { '\0' };
19196 +       char           HEXCHAR[] = "0123456789ABCDEF";
19197 +       long          *p = (long*) pc;
19198 +       int            l;
19199 +
19200         for (i=0; i < size; ) {
19201                 l = (long) *p;
19202                 hex_buffer[haddr] = HEXCHAR[(l >> 28) & 0xf];
19203 @@ -4760,386 +6314,9 @@
19204
19205  #endif
19206
19207 -static int __devinit skge_probe_one(struct pci_dev *pdev,
19208 -               const struct pci_device_id *ent)
19209 -{
19210 -       SK_AC                   *pAC;
19211 -       DEV_NET                 *pNet = NULL;
19212 -       struct net_device       *dev = NULL;
19213 -       static int boards_found = 0;
19214 -       int error = -ENODEV;
19215 -       int using_dac = 0;
19216 -       char DeviceStr[80];
19217 -
19218 -       if (pci_enable_device(pdev))
19219 -               goto out;
19220 -
19221 -       /* Configure DMA attributes. */
19222 -       if (sizeof(dma_addr_t) > sizeof(u32) &&
19223 -           !(error = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
19224 -               using_dac = 1;
19225 -               error = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
19226 -               if (error < 0) {
19227 -                       printk(KERN_ERR "sk98lin %s unable to obtain 64 bit DMA "
19228 -                              "for consistent allocations\n", pci_name(pdev));
19229 -                       goto out_disable_device;
19230 -               }
19231 -       } else {
19232 -               error = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
19233 -               if (error) {
19234 -                       printk(KERN_ERR "sk98lin %s no usable DMA configuration\n",
19235 -                              pci_name(pdev));
19236 -                       goto out_disable_device;
19237 -               }
19238 -       }
19239 -
19240 -       error = -ENOMEM;
19241 -       dev = alloc_etherdev(sizeof(DEV_NET));
19242 -       if (!dev) {
19243 -               printk(KERN_ERR "sk98lin: unable to allocate etherdev "
19244 -                      "structure!\n");
19245 -               goto out_disable_device;
19246 -       }
19247 -
19248 -       pNet = netdev_priv(dev);
19249 -       pNet->pAC = kzalloc(sizeof(SK_AC), GFP_KERNEL);
19250 -       if (!pNet->pAC) {
19251 -               printk(KERN_ERR "sk98lin: unable to allocate adapter "
19252 -                      "structure!\n");
19253 -               goto out_free_netdev;
19254 -       }
19255 -
19256 -       pAC = pNet->pAC;
19257 -       pAC->PciDev = pdev;
19258 -
19259 -       pAC->dev[0] = dev;
19260 -       pAC->dev[1] = dev;
19261 -       pAC->CheckQueue = SK_FALSE;
19262 -
19263 -       dev->irq = pdev->irq;
19264 -
19265 -       error = SkGeInitPCI(pAC);
19266 -       if (error) {
19267 -               printk(KERN_ERR "sk98lin: PCI setup failed: %i\n", error);
19268 -               goto out_free_netdev;
19269 -       }
19270 -
19271 -       SET_MODULE_OWNER(dev);
19272 -       dev->open =             &SkGeOpen;
19273 -       dev->stop =             &SkGeClose;
19274 -       dev->hard_start_xmit =  &SkGeXmit;
19275 -       dev->get_stats =        &SkGeStats;
19276 -       dev->set_multicast_list = &SkGeSetRxMode;
19277 -       dev->set_mac_address =  &SkGeSetMacAddr;
19278 -       dev->do_ioctl =         &SkGeIoctl;
19279 -       dev->change_mtu =       &SkGeChangeMtu;
19280 -#ifdef CONFIG_NET_POLL_CONTROLLER
19281 -       dev->poll_controller =  &SkGePollController;
19282 -#endif
19283 -       SET_NETDEV_DEV(dev, &pdev->dev);
19284 -       SET_ETHTOOL_OPS(dev, &SkGeEthtoolOps);
19285 -
19286 -       /* Use only if yukon hardware */
19287 -       if (pAC->ChipsetType) {
19288 -#ifdef USE_SK_TX_CHECKSUM
19289 -               dev->features |= NETIF_F_IP_CSUM;
19290 -#endif
19291 -#ifdef SK_ZEROCOPY
19292 -               dev->features |= NETIF_F_SG;
19293 -#endif
19294 -#ifdef USE_SK_RX_CHECKSUM
19295 -               pAC->RxPort[0].RxCsum = 1;
19296 -#endif
19297 -       }
19298 -
19299 -       if (using_dac)
19300 -               dev->features |= NETIF_F_HIGHDMA;
19301 -
19302 -       pAC->Index = boards_found++;
19303 -
19304 -       error = SkGeBoardInit(dev, pAC);
19305 -       if (error)
19306 -               goto out_free_netdev;
19307 -
19308 -       /* Read Adapter name from VPD */
19309 -       if (ProductStr(pAC, DeviceStr, sizeof(DeviceStr)) != 0) {
19310 -               error = -EIO;
19311 -               printk(KERN_ERR "sk98lin: Could not read VPD data.\n");
19312 -               goto out_free_resources;
19313 -       }
19314 -
19315 -       /* Register net device */
19316 -       error = register_netdev(dev);
19317 -       if (error) {
19318 -               printk(KERN_ERR "sk98lin: Could not register device.\n");
19319 -               goto out_free_resources;
19320 -       }
19321 -
19322 -       /* Print adapter specific string from vpd */
19323 -       printk("%s: %s\n", dev->name, DeviceStr);
19324 -
19325 -       /* Print configuration settings */
19326 -       printk("      PrefPort:%c  RlmtMode:%s\n",
19327 -               'A' + pAC->Rlmt.Net[0].Port[pAC->Rlmt.Net[0].PrefPort]->PortNumber,
19328 -               (pAC->RlmtMode==0)  ? "Check Link State" :
19329 -               ((pAC->RlmtMode==1) ? "Check Link State" :
19330 -               ((pAC->RlmtMode==3) ? "Check Local Port" :
19331 -               ((pAC->RlmtMode==7) ? "Check Segmentation" :
19332 -               ((pAC->RlmtMode==17) ? "Dual Check Link State" :"Error")))));
19333 -
19334 -       SkGeYellowLED(pAC, pAC->IoBase, 1);
19335 -
19336 -       memcpy(&dev->dev_addr, &pAC->Addr.Net[0].CurrentMacAddress, 6);
19337 -       memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
19338 -
19339 -       pNet->PortNr = 0;
19340 -       pNet->NetNr  = 0;
19341 -
19342 -       boards_found++;
19343 -
19344 -       pci_set_drvdata(pdev, dev);
19345 -
19346 -       /* More then one port found */
19347 -       if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
19348 -               dev = alloc_etherdev(sizeof(DEV_NET));
19349 -               if (!dev) {
19350 -                       printk(KERN_ERR "sk98lin: unable to allocate etherdev "
19351 -                               "structure!\n");
19352 -                       goto single_port;
19353 -               }
19354 -
19355 -               pNet          = netdev_priv(dev);
19356 -               pNet->PortNr  = 1;
19357 -               pNet->NetNr   = 1;
19358 -               pNet->pAC     = pAC;
19359 -
19360 -               dev->open               = &SkGeOpen;
19361 -               dev->stop               = &SkGeClose;
19362 -               dev->hard_start_xmit    = &SkGeXmit;
19363 -               dev->get_stats          = &SkGeStats;
19364 -               dev->set_multicast_list = &SkGeSetRxMode;
19365 -               dev->set_mac_address    = &SkGeSetMacAddr;
19366 -               dev->do_ioctl           = &SkGeIoctl;
19367 -               dev->change_mtu         = &SkGeChangeMtu;
19368 -               SET_NETDEV_DEV(dev, &pdev->dev);
19369 -               SET_ETHTOOL_OPS(dev, &SkGeEthtoolOps);
19370 -
19371 -               if (pAC->ChipsetType) {
19372 -#ifdef USE_SK_TX_CHECKSUM
19373 -                       dev->features |= NETIF_F_IP_CSUM;
19374 -#endif
19375 -#ifdef SK_ZEROCOPY
19376 -                       dev->features |= NETIF_F_SG;
19377 -#endif
19378 -#ifdef USE_SK_RX_CHECKSUM
19379 -                       pAC->RxPort[1].RxCsum = 1;
19380 -#endif
19381 -               }
19382 -
19383 -               if (using_dac)
19384 -                       dev->features |= NETIF_F_HIGHDMA;
19385 -
19386 -               error = register_netdev(dev);
19387 -               if (error) {
19388 -                       printk(KERN_ERR "sk98lin: Could not register device"
19389 -                              " for second port. (%d)\n", error);
19390 -                       free_netdev(dev);
19391 -                       goto single_port;
19392 -               }
19393 -
19394 -               pAC->dev[1]   = dev;
19395 -               memcpy(&dev->dev_addr,
19396 -                      &pAC->Addr.Net[1].CurrentMacAddress, 6);
19397 -               memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
19398 -
19399 -               printk("%s: %s\n", dev->name, DeviceStr);
19400 -               printk("      PrefPort:B  RlmtMode:Dual Check Link State\n");
19401 -       }
19402 -
19403 -single_port:
19404 -
19405 -       /* Save the hardware revision */
19406 -       pAC->HWRevision = (((pAC->GIni.GIPciHwRev >> 4) & 0x0F)*10) +
19407 -               (pAC->GIni.GIPciHwRev & 0x0F);
19408 -
19409 -       /* Set driver globals */
19410 -       pAC->Pnmi.pDriverFileName    = DRIVER_FILE_NAME;
19411 -       pAC->Pnmi.pDriverReleaseDate = DRIVER_REL_DATE;
19412 -
19413 -       memset(&pAC->PnmiBackup, 0, sizeof(SK_PNMI_STRUCT_DATA));
19414 -       memcpy(&pAC->PnmiBackup, &pAC->PnmiStruct, sizeof(SK_PNMI_STRUCT_DATA));
19415 -
19416 -       return 0;
19417 -
19418 - out_free_resources:
19419 -       FreeResources(dev);
19420 - out_free_netdev:
19421 -       free_netdev(dev);
19422 - out_disable_device:
19423 -       pci_disable_device(pdev);
19424 - out:
19425 -       return error;
19426 -}
19427 -
19428 -static void __devexit skge_remove_one(struct pci_dev *pdev)
19429 -{
19430 -       struct net_device *dev = pci_get_drvdata(pdev);
19431 -       DEV_NET *pNet = netdev_priv(dev);
19432 -       SK_AC *pAC = pNet->pAC;
19433 -       struct net_device *otherdev = pAC->dev[1];
19434 -
19435 -       unregister_netdev(dev);
19436 -
19437 -       SkGeYellowLED(pAC, pAC->IoBase, 0);
19438 -
19439 -       if (pAC->BoardLevel == SK_INIT_RUN) {
19440 -               SK_EVPARA EvPara;
19441 -               unsigned long Flags;
19442 -
19443 -               /* board is still alive */
19444 -               spin_lock_irqsave(&pAC->SlowPathLock, Flags);
19445 -               EvPara.Para32[0] = 0;
19446 -               EvPara.Para32[1] = -1;
19447 -               SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
19448 -               EvPara.Para32[0] = 1;
19449 -               EvPara.Para32[1] = -1;
19450 -               SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
19451 -               SkEventDispatcher(pAC, pAC->IoBase);
19452 -               /* disable interrupts */
19453 -               SK_OUT32(pAC->IoBase, B0_IMSK, 0);
19454 -               SkGeDeInit(pAC, pAC->IoBase);
19455 -               spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
19456 -               pAC->BoardLevel = SK_INIT_DATA;
19457 -               /* We do NOT check here, if IRQ was pending, of course*/
19458 -       }
19459 -
19460 -       if (pAC->BoardLevel == SK_INIT_IO) {
19461 -               /* board is still alive */
19462 -               SkGeDeInit(pAC, pAC->IoBase);
19463 -               pAC->BoardLevel = SK_INIT_DATA;
19464 -       }
19465 -
19466 -       FreeResources(dev);
19467 -       free_netdev(dev);
19468 -       if (otherdev != dev)
19469 -               free_netdev(otherdev);
19470 -       kfree(pAC);
19471 -}
19472 -
19473 -#ifdef CONFIG_PM
19474 -static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
19475 -{
19476 -       struct net_device *dev = pci_get_drvdata(pdev);
19477 -       DEV_NET *pNet = netdev_priv(dev);
19478 -       SK_AC *pAC = pNet->pAC;
19479 -       struct net_device *otherdev = pAC->dev[1];
19480 -
19481 -       if (netif_running(dev)) {
19482 -               netif_carrier_off(dev);
19483 -               DoPrintInterfaceChange = SK_FALSE;
19484 -               SkDrvDeInitAdapter(pAC, 0);  /* performs SkGeClose */
19485 -               netif_device_detach(dev);
19486 -       }
19487 -       if (otherdev != dev) {
19488 -               if (netif_running(otherdev)) {
19489 -                       netif_carrier_off(otherdev);
19490 -                       DoPrintInterfaceChange = SK_FALSE;
19491 -                       SkDrvDeInitAdapter(pAC, 1);  /* performs SkGeClose */
19492 -                       netif_device_detach(otherdev);
19493 -               }
19494 -       }
19495 -
19496 -       pci_save_state(pdev);
19497 -       pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
19498 -       if (pAC->AllocFlag & SK_ALLOC_IRQ) {
19499 -               free_irq(dev->irq, dev);
19500 -       }
19501 -       pci_disable_device(pdev);
19502 -       pci_set_power_state(pdev, pci_choose_state(pdev, state));
19503 -
19504 -       return 0;
19505 -}
19506 -
19507 -static int skge_resume(struct pci_dev *pdev)
19508 -{
19509 -       struct net_device *dev = pci_get_drvdata(pdev);
19510 -       DEV_NET *pNet = netdev_priv(dev);
19511 -       SK_AC *pAC = pNet->pAC;
19512 -       struct net_device *otherdev = pAC->dev[1];
19513 -       int ret;
19514 -
19515 -       pci_set_power_state(pdev, PCI_D0);
19516 -       pci_restore_state(pdev);
19517 -       pci_enable_device(pdev);
19518 -       pci_set_master(pdev);
19519 -       if (pAC->GIni.GIMacsFound == 2)
19520 -               ret = request_irq(dev->irq, SkGeIsr, IRQF_SHARED, "sk98lin", dev);
19521 -       else
19522 -               ret = request_irq(dev->irq, SkGeIsrOnePort, IRQF_SHARED, "sk98lin", dev);
19523 -       if (ret) {
19524 -               printk(KERN_WARNING "sk98lin: unable to acquire IRQ %d\n", dev->irq);
19525 -               pAC->AllocFlag &= ~SK_ALLOC_IRQ;
19526 -               dev->irq = 0;
19527 -               pci_disable_device(pdev);
19528 -               return -EBUSY;
19529 -       }
19530 -
19531 -       netif_device_attach(dev);
19532 -       if (netif_running(dev)) {
19533 -               DoPrintInterfaceChange = SK_FALSE;
19534 -               SkDrvInitAdapter(pAC, 0);    /* first device  */
19535 -       }
19536 -       if (otherdev != dev) {
19537 -               netif_device_attach(otherdev);
19538 -               if (netif_running(otherdev)) {
19539 -                       DoPrintInterfaceChange = SK_FALSE;
19540 -                       SkDrvInitAdapter(pAC, 1);    /* second device  */
19541 -               }
19542 -       }
19543 -
19544 -       return 0;
19545 -}
19546 -#else
19547 -#define skge_suspend NULL
19548 -#define skge_resume NULL
19549 -#endif
19550 -
19551 -static struct pci_device_id skge_pci_tbl[] = {
19552 -       { PCI_VENDOR_ID_3COM, 0x1700, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
19553 -       { PCI_VENDOR_ID_3COM, 0x80eb, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
19554 -       { PCI_VENDOR_ID_SYSKONNECT, 0x4300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
19555 -       { PCI_VENDOR_ID_SYSKONNECT, 0x4320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
19556 -/* DLink card does not have valid VPD so this driver gags
19557 - *     { PCI_VENDOR_ID_DLINK, 0x4c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
19558 - */
19559 -       { PCI_VENDOR_ID_MARVELL, 0x4320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
19560 -       { PCI_VENDOR_ID_MARVELL, 0x5005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
19561 -       { PCI_VENDOR_ID_CNET, 0x434e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
19562 -       { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
19563 -       { PCI_VENDOR_ID_LINKSYS, 0x1064, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
19564 -       { 0 }
19565 -};
19566 -
19567 -MODULE_DEVICE_TABLE(pci, skge_pci_tbl);
19568 -
19569 -static struct pci_driver skge_driver = {
19570 -       .name           = "sk98lin",
19571 -       .id_table       = skge_pci_tbl,
19572 -       .probe          = skge_probe_one,
19573 -       .remove         = __devexit_p(skge_remove_one),
19574 -       .suspend        = skge_suspend,
19575 -       .resume         = skge_resume,
19576 -};
19577 -
19578 -static int __init skge_init(void)
19579 -{
19580 -       return pci_register_driver(&skge_driver);
19581 -}
19582 -
19583 -static void __exit skge_exit(void)
19584 -{
19585 -       pci_unregister_driver(&skge_driver);
19586 -}
19587 +/*******************************************************************************
19588 + *
19589 + * End of file
19590 + *
19591 + ******************************************************************************/
19592
19593 -module_init(skge_init);
19594 -module_exit(skge_exit);
19595 diff -ruN linux/drivers/net/sk98lin/skgehwt.c linux-new/drivers/net/sk98lin/skgehwt.c
19596 --- linux/drivers/net/sk98lin/skgehwt.c 2006-09-20 05:42:06.000000000 +0200
19597 +++ linux-new/drivers/net/sk98lin/skgehwt.c     2006-07-28 14:13:54.000000000 +0200
19598 @@ -2,16 +2,17 @@
19599   *
19600   * Name:       skgehwt.c
19601   * Project:    Gigabit Ethernet Adapters, Event Scheduler Module
19602 - * Version:    $Revision$
19603 - * Date:       $Date$
19604 + * Version:    $Revision$
19605 + * Date:       $Date$
19606   * Purpose:    Hardware Timer
19607   *
19608   ******************************************************************************/
19609
19610  /******************************************************************************
19611   *
19612 + *     LICENSE:
19613   *     (C)Copyright 1998-2002 SysKonnect GmbH.
19614 - *     (C)Copyright 2002-2003 Marvell.
19615 + *     (C)Copyright 2002-2004 Marvell.
19616   *
19617   *     This program is free software; you can redistribute it and/or modify
19618   *     it under the terms of the GNU General Public License as published by
19619 @@ -19,6 +20,7 @@
19620   *     (at your option) any later version.
19621   *
19622   *     The information in this file is provided "AS IS" without warranty.
19623 + *     /LICENSE
19624   *
19625   ******************************************************************************/
19626
19627 @@ -27,7 +29,7 @@
19628   */
19629  #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
19630  static const char SysKonnectFileId[] =
19631 -       "@(#) $Id$ (C) Marvell.";
19632 +       "@(#) $Id$ (C) Marvell.";
19633  #endif
19634
19635  #include "h/skdrv1st.h"                /* Driver Specific Definitions */
19636 @@ -44,10 +46,10 @@
19637  /*
19638   * Prototypes of local functions.
19639   */
19640 -#define        SK_HWT_MAX      (65000)
19641 +#define        SK_HWT_MAX      65000UL * 160           /* ca. 10 sec. */
19642
19643  /* correction factor */
19644 -#define        SK_HWT_FAC      (1000 * (SK_U32)pAC->GIni.GIHstClkFact / 100)
19645 +#define        SK_HWT_FAC      (10 * (SK_U32)pAC->GIni.GIHstClkFact / 16)
19646
19647  /*
19648   * Initialize hardware timer.
19649 @@ -73,29 +75,21 @@
19650  void   SkHwtStart(
19651  SK_AC  *pAC,   /* Adapters context */
19652  SK_IOC Ioc,    /* IoContext */
19653 -SK_U32 Time)   /* Time in units of 16us to load the timer with. */
19654 +SK_U32 Time)   /* Time in usec to load the timer */
19655  {
19656 -       SK_U32  Cnt;
19657 -
19658         if (Time > SK_HWT_MAX)
19659                 Time = SK_HWT_MAX;
19660
19661         pAC->Hwt.TStart = Time;
19662         pAC->Hwt.TStop = 0L;
19663
19664 -       Cnt = Time;
19665 -
19666 -       /*
19667 -        * if time < 16 us
19668 -        *      time = 16 us
19669 -        */
19670 -       if (!Cnt) {
19671 -               Cnt++;
19672 +       if (!Time) {
19673 +               Time = 1L;
19674         }
19675
19676 -       SK_OUT32(Ioc, B2_TI_INI, Cnt * SK_HWT_FAC);
19677 -
19678 -       SK_OUT16(Ioc, B2_TI_CTRL, TIM_START);   /* Start timer. */
19679 +       SK_OUT32(Ioc, B2_TI_INI, Time * SK_HWT_FAC);
19680 +
19681 +       SK_OUT16(Ioc, B2_TI_CTRL, TIM_START);   /* Start timer */
19682
19683         pAC->Hwt.TActive = SK_TRUE;
19684  }
19685 @@ -109,13 +103,12 @@
19686  SK_IOC Ioc)    /* IoContext */
19687  {
19688         SK_OUT16(Ioc, B2_TI_CTRL, TIM_STOP);
19689 -
19690 +
19691         SK_OUT16(Ioc, B2_TI_CTRL, TIM_CLR_IRQ);
19692
19693         pAC->Hwt.TActive = SK_FALSE;
19694  }
19695
19696 -
19697  /*
19698   *     Stop hardware timer and read time elapsed since last start.
19699   *
19700 @@ -129,6 +122,9 @@
19701  {
19702         SK_U32  TRead;
19703         SK_U32  IStatus;
19704 +       SK_U32  TimerInt;
19705 +
19706 +       TimerInt = CHIP_ID_YUKON_2(pAC) ? Y2_IS_TIMINT : IS_TIMINT;
19707
19708         if (pAC->Hwt.TActive) {
19709
19710 @@ -139,15 +135,15 @@
19711
19712                 SK_IN32(Ioc, B0_ISRC, &IStatus);
19713
19714 -               /* Check if timer expired (or wraped around) */
19715 -               if ((TRead > pAC->Hwt.TStart) || (IStatus & IS_TIMINT)) {
19716 -
19717 +               /* Check if timer expired (or wrapped around) */
19718 +               if ((TRead > pAC->Hwt.TStart) || ((IStatus & TimerInt) != 0)) {
19719 +
19720                         SkHwtStop(pAC, Ioc);
19721 -
19722 +
19723                         pAC->Hwt.TStop = pAC->Hwt.TStart;
19724                 }
19725                 else {
19726 -
19727 +
19728                         pAC->Hwt.TStop = pAC->Hwt.TStart - TRead;
19729                 }
19730         }
19731 @@ -162,9 +158,9 @@
19732  SK_IOC Ioc)    /* IoContext */
19733  {
19734         SkHwtStop(pAC, Ioc);
19735 -
19736 +
19737         pAC->Hwt.TStop = pAC->Hwt.TStart;
19738 -
19739 +
19740         SkTimerDone(pAC, Ioc);
19741  }
19742
19743 diff -ruN linux/drivers/net/sk98lin/skgeinit.c linux-new/drivers/net/sk98lin/skgeinit.c
19744 --- linux/drivers/net/sk98lin/skgeinit.c        2006-09-20 05:42:06.000000000 +0200
19745 +++ linux-new/drivers/net/sk98lin/skgeinit.c    2006-07-28 14:13:54.000000000 +0200
19746 @@ -2,23 +2,24 @@
19747   *
19748   * Name:       skgeinit.c
19749   * Project:    Gigabit Ethernet Adapters, Common Modules
19750 - * Version:    $Revision$
19751 - * Date:       $Date$
19752 + * Version:    $Revision$
19753 + * Date:       $Date$
19754   * Purpose:    Contains functions to initialize the adapter
19755   *
19756   ******************************************************************************/
19757
19758  /******************************************************************************
19759   *
19760 + *     LICENSE:
19761   *     (C)Copyright 1998-2002 SysKonnect.
19762 - *     (C)Copyright 2002-2003 Marvell.
19763 + *     (C)Copyright 2002-2006 Marvell.
19764   *
19765   *     This program is free software; you can redistribute it and/or modify
19766   *     it under the terms of the GNU General Public License as published by
19767   *     the Free Software Foundation; either version 2 of the License, or
19768   *     (at your option) any later version.
19769 - *
19770   *     The information in this file is provided "AS IS" without warranty.
19771 + *     /LICENSE
19772   *
19773   ******************************************************************************/
19774
19775 @@ -31,7 +32,7 @@
19776
19777  #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
19778  static const char SysKonnectFileId[] =
19779 -       "@(#) $Id$ (C) Marvell.";
19780 +       "@(#) $Id$ (C) Marvell.";
19781  #endif
19782
19783  struct s_QOffTab {
19784 @@ -39,6 +40,7 @@
19785         int     XsQOff;         /* Sync Tx Queue Address Offset */
19786         int     XaQOff;         /* Async Tx Queue Address Offset */
19787  };
19788 +
19789  static struct s_QOffTab QOffTab[] = {
19790         {Q_R1, Q_XS1, Q_XA1}, {Q_R2, Q_XS2, Q_XA2}
19791  };
19792 @@ -57,6 +59,126 @@
19793  #endif
19794  };
19795
19796 +#ifndef SK_SLIM
19797 +/******************************************************************************
19798 + *
19799 + *     SkGePortVlan() - Enable / Disable VLAN support
19800 + *
19801 + * Description:
19802 + *     Enable or disable the VLAN support of the selected port.
19803 + *     The new configuration is *not* saved over any SkGeStopPort() and
19804 + *     SkGeInitPort() calls.
19805 + *     Currently this function is only supported on Yukon-2/EC adapters.
19806 + *
19807 + * Returns:
19808 + *     nothing
19809 + */
19810 +void SkGePortVlan(
19811 +SK_AC  *pAC,   /* Adapter Context */
19812 +SK_IOC IoC,    /* I/O Context */
19813 +int            Port,   /* Port number */
19814 +SK_BOOL        Enable) /* Flag */
19815 +{
19816 +       SK_U32  RxCtrl;
19817 +       SK_U32  TxCtrl;
19818 +
19819 +       if (CHIP_ID_YUKON_2(pAC)) {
19820 +               if (Enable) {
19821 +                       RxCtrl = RX_VLAN_STRIP_ON;
19822 +                       TxCtrl = TX_VLAN_TAG_ON;
19823 +               }
19824 +               else {
19825 +                       RxCtrl = RX_VLAN_STRIP_OFF;
19826 +                       TxCtrl = TX_VLAN_TAG_OFF;
19827 +               }
19828 +
19829 +               SK_OUT32(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), RxCtrl);
19830 +
19831 +               SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), TxCtrl);
19832 +       }
19833 +}      /* SkGePortVlan */
19834 +
19835 +
19836 +/******************************************************************************
19837 + *
19838 + *     SkGeRxRss() - Enable / Disable RSS Hash Calculation
19839 + *
19840 + * Description:
19841 + *     Enable or disable the RSS hash calculation of the selected port.
19842 + *     The new configuration is *not* saved over any SkGeStopPort() and
19843 + *     SkGeInitPort() calls.
19844 + *     Currently this function is only supported on Yukon-2/EC adapters.
19845 + *
19846 + * Returns:
19847 + *     nothing
19848 + */
19849 +void SkGeRxRss(
19850 +SK_AC  *pAC,   /* Adapter Context */
19851 +SK_IOC IoC,    /* I/O Context */
19852 +int            Port,   /* Port number */
19853 +SK_BOOL        Enable) /* Flag */
19854 +{
19855 +       if (CHIP_ID_YUKON_2(pAC)) {
19856 +               SK_OUT32(IoC, Q_ADDR(pAC->GIni.GP[Port].PRxQOff, Q_CSR),
19857 +                       Enable ? BMU_ENA_RX_RSS_HASH : BMU_DIS_RX_RSS_HASH);
19858 +       }
19859 +}      /* SkGeRxRss */
19860 +
19861 +
19862 +/******************************************************************************
19863 + *
19864 + *     SkGeRxCsum() - Enable / Disable Receive Checksum
19865 + *
19866 + * Description:
19867 + *     Enable or disable the checksum of the selected port.
19868 + *     The new configuration is *not* saved over any SkGeStopPort() and
19869 + *     SkGeInitPort() calls.
19870 + *     Currently this function is only supported on Yukon-2/EC adapters.
19871 + *
19872 + * Returns:
19873 + *     nothing
19874 + */
19875 +void SkGeRxCsum(
19876 +SK_AC  *pAC,   /* Adapter Context */
19877 +SK_IOC IoC,    /* I/O Context */
19878 +int            Port,   /* Port number */
19879 +SK_BOOL        Enable) /* Flag */
19880 +{
19881 +       if (CHIP_ID_YUKON_2(pAC)) {
19882 +               SK_OUT32(IoC, Q_ADDR(pAC->GIni.GP[Port].PRxQOff, Q_CSR),
19883 +                       Enable ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
19884 +       }
19885 +}      /* SkGeRxCsum */
19886 +#endif /* !SK_SLIM */
19887 +
19888 +/******************************************************************************
19889 + *
19890 + *     SkGePollRxD() - Enable / Disable Descriptor Polling of RxD Ring
19891 + *
19892 + * Description:
19893 + *     Enable or disable the descriptor polling of the receive descriptor
19894 + *     ring (RxD) for port 'Port'.
19895 + *     The new configuration is *not* saved over any SkGeStopPort() and
19896 + *     SkGeInitPort() calls.
19897 + *
19898 + * Returns:
19899 + *     nothing
19900 + */
19901 +void SkGePollRxD(
19902 +SK_AC  *pAC,           /* Adapter Context */
19903 +SK_IOC IoC,            /* I/O Context */
19904 +int            Port,           /* Port Index (MAC_1 + n) */
19905 +SK_BOOL PollRxD)       /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */
19906 +{
19907 +       SK_GEPORT *pPrt;
19908 +
19909 +       pPrt = &pAC->GIni.GP[Port];
19910 +
19911 +       SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), (SK_U32)((PollRxD) ?
19912 +               CSR_ENA_POL : CSR_DIS_POL));
19913 +}      /* SkGePollRxD */
19914 +
19915 +
19916  /******************************************************************************
19917   *
19918   *     SkGePollTxD() - Enable / Disable Descriptor Polling of TxD Rings
19919 @@ -71,8 +193,8 @@
19920   *     nothing
19921   */
19922  void SkGePollTxD(
19923 -SK_AC  *pAC,           /* adapter context */
19924 -SK_IOC IoC,            /* IO context */
19925 +SK_AC  *pAC,           /* Adapter Context */
19926 +SK_IOC IoC,            /* I/O Context */
19927  int            Port,           /* Port Index (MAC_1 + n) */
19928  SK_BOOL PollTxD)       /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */
19929  {
19930 @@ -86,13 +208,13 @@
19931         if (pPrt->PXSQSize != 0) {
19932                 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), DWord);
19933         }
19934 -
19935 +
19936         if (pPrt->PXAQSize != 0) {
19937                 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), DWord);
19938         }
19939  }      /* SkGePollTxD */
19940
19941 -
19942 +#ifndef SK_SLIM
19943  /******************************************************************************
19944   *
19945   *     SkGeYellowLED() - Switch the yellow LED on or off.
19946 @@ -107,20 +229,30 @@
19947   *     nothing
19948   */
19949  void SkGeYellowLED(
19950 -SK_AC  *pAC,           /* adapter context */
19951 -SK_IOC IoC,            /* IO context */
19952 +SK_AC  *pAC,           /* Adapter Context */
19953 +SK_IOC IoC,            /* I/O Context */
19954  int            State)          /* yellow LED state, 0 = OFF, 0 != ON */
19955  {
19956 +       int     LedReg;
19957 +
19958 +       if (CHIP_ID_YUKON_2(pAC)) {
19959 +               /* different mapping on Yukon-2 */
19960 +               LedReg = B0_CTST + 1;
19961 +       }
19962 +       else {
19963 +               LedReg = B0_LED;
19964 +       }
19965 +
19966         if (State == 0) {
19967 -               /* Switch yellow LED OFF */
19968 -               SK_OUT8(IoC, B0_LED, LED_STAT_OFF);
19969 +               /* Switch state LED OFF */
19970 +               SK_OUT8(IoC, LedReg, LED_STAT_OFF);
19971         }
19972         else {
19973 -               /* Switch yellow LED ON */
19974 -               SK_OUT8(IoC, B0_LED, LED_STAT_ON);
19975 +               /* Switch state LED ON */
19976 +               SK_OUT8(IoC, LedReg, LED_STAT_ON);
19977         }
19978  }      /* SkGeYellowLED */
19979 -
19980 +#endif /* !SK_SLIM */
19981
19982  #if (!defined(SK_SLIM) || defined(GENESIS))
19983  /******************************************************************************
19984 @@ -141,8 +273,8 @@
19985   *     nothing
19986   */
19987  void SkGeXmitLED(
19988 -SK_AC  *pAC,           /* adapter context */
19989 -SK_IOC IoC,            /* IO context */
19990 +SK_AC  *pAC,           /* Adapter Context */
19991 +SK_IOC IoC,            /* I/O Context */
19992  int            Led,            /* offset to the LED Init Value register */
19993  int            Mode)           /* Mode may be SK_LED_DIS, SK_LED_ENA, SK_LED_TST */
19994  {
19995 @@ -167,18 +299,17 @@
19996                  */
19997                 SK_OUT32(IoC, Led + XMIT_LED_CNT, 0);
19998                 SK_OUT8(IoC, Led + XMIT_LED_TST, LED_T_OFF);
19999 -               break;
20000         }
20001 -
20002 +
20003         /*
20004 -        * 1000BT: The Transmit LED is driven by the PHY.
20005 +        * 1000BT: the Transmit LED is driven by the PHY.
20006          * But the default LED configuration is used for
20007          * Level One and Broadcom PHYs.
20008 -        * (Broadcom: It may be that PHY_B_PEC_EN_LTR has to be set.)
20009 -        * (In this case it has to be added here. But we will see. XXX)
20010 +        * (Broadcom: It may be that PHY_B_PEC_EN_LTR has to be set.
20011 +        * In this case it has to be added here.)
20012          */
20013  }      /* SkGeXmitLED */
20014 -#endif /* !SK_SLIM || GENESIS */
20015 +#endif /* !SK_SLIM || GENESIS */
20016
20017
20018  /******************************************************************************
20019 @@ -199,7 +330,7 @@
20020   *     1:      configuration error
20021   */
20022  static int DoCalcAddr(
20023 -SK_AC          *pAC,                           /* adapter context */
20024 +SK_AC          *pAC,                           /* Adapter Context */
20025  SK_GEPORT      SK_FAR *pPrt,           /* port index */
20026  int                    QuSize,                         /* size of the queue to configure in kB */
20027  SK_U32         SK_FAR *StartVal,       /* start value for address calculation */
20028 @@ -236,12 +367,35 @@
20029
20030  /******************************************************************************
20031   *
20032 + *     SkGeRoundQueueSize() - Round the given queue size to the adpaters QZ units
20033 + *
20034 + * Description:
20035 + *     This function rounds the given queue size in kBs to adapter specific
20036 + *     queue size units (Genesis and Yukon: 8 kB, Yukon-2/EC: 1 kB).
20037 + *
20038 + * Returns:
20039 + *     the rounded queue size in kB
20040 + */
20041 +static int SkGeRoundQueueSize(
20042 +SK_AC  *pAC,           /* Adapter Context */
20043 +int    QueueSizeKB)    /* Queue size in kB */
20044 +{
20045 +       int QueueSizeSteps;
20046 +
20047 +       QueueSizeSteps = (CHIP_ID_YUKON_2(pAC)) ? QZ_STEP_Y2 : QZ_STEP;
20048 +
20049 +       return((QueueSizeKB + QueueSizeSteps - 1) & ~(QueueSizeSteps - 1));
20050 +}      /* SkGeRoundQueueSize */
20051 +
20052 +
20053 +/******************************************************************************
20054 + *
20055   *     SkGeInitAssignRamToQueues() - allocate default queue sizes
20056   *
20057   * Description:
20058   *     This function assigns the memory to the different queues and ports.
20059   *     When DualNet is set to SK_TRUE all ports get the same amount of memory.
20060 - *  Otherwise the first port gets most of the memory and all the
20061 + *     Otherwise the first port gets most of the memory and all the
20062   *     other ports just the required minimum.
20063   *     This function can only be called when pAC->GIni.GIRamSize and
20064   *     pAC->GIni.GIMacsFound have been initialized, usually this happens
20065 @@ -254,102 +408,146 @@
20066   */
20067
20068  int SkGeInitAssignRamToQueues(
20069 -SK_AC  *pAC,                   /* Adapter context */
20070 +SK_AC  *pAC,                   /* Adapter Context */
20071  int            ActivePort,             /* Active Port in RLMT mode */
20072 -SK_BOOL        DualNet)                /* adapter context */
20073 +SK_BOOL        DualNet)                /* Dual Net active */
20074  {
20075         int     i;
20076         int     UsedKilobytes;                  /* memory already assigned */
20077         int     ActivePortKilobytes;    /* memory available for active port */
20078 -       SK_GEPORT *pGePort;
20079 -
20080 -       UsedKilobytes = 0;
20081 +       int     MinQueueSize;                   /* min. memory for queues */
20082 +       int     TotalRamSize;                   /* total memory for queues */
20083 +       SK_BOOL DualPortYukon2;
20084 +       SK_GEPORT *pPrt;
20085
20086         if (ActivePort >= pAC->GIni.GIMacsFound) {
20087 +
20088                 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
20089                         ("SkGeInitAssignRamToQueues: ActivePort (%d) invalid\n",
20090                         ActivePort));
20091                 return(1);
20092         }
20093 -       if (((pAC->GIni.GIMacsFound * (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE)) +
20094 -               ((RAM_QUOTA_SYNC == 0) ? 0 : SK_MIN_TXQ_SIZE)) > pAC->GIni.GIRamSize) {
20095 +
20096 +       DualPortYukon2 = (CHIP_ID_YUKON_2(pAC) && pAC->GIni.GIMacsFound == 2);
20097 +
20098 +       TotalRamSize = pAC->GIni.GIRamSize;
20099 +
20100 +       if (DualPortYukon2) {
20101 +               TotalRamSize *= 2;
20102 +       }
20103 +
20104 +       MinQueueSize = SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE;
20105 +
20106 +       if (MinQueueSize > pAC->GIni.GIRamSize) {
20107 +               MinQueueSize = pAC->GIni.GIRamSize;
20108 +       }
20109 +
20110 +       if ((pAC->GIni.GIMacsFound * MinQueueSize +
20111 +                RAM_QUOTA_SYNC * SK_MIN_TXQ_SIZE) > TotalRamSize) {
20112 +
20113                 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
20114                         ("SkGeInitAssignRamToQueues: Not enough memory (%d)\n",
20115 -                        pAC->GIni.GIRamSize));
20116 +                       TotalRamSize));
20117                 return(2);
20118         }
20119
20120         if (DualNet) {
20121                 /* every port gets the same amount of memory */
20122 -               ActivePortKilobytes = pAC->GIni.GIRamSize / pAC->GIni.GIMacsFound;
20123 +               ActivePortKilobytes = TotalRamSize / pAC->GIni.GIMacsFound;
20124 +
20125                 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
20126
20127 -                       pGePort = &pAC->GIni.GP[i];
20128 -
20129 +                       pPrt = &pAC->GIni.GP[i];
20130 +
20131 +                       if (DualPortYukon2) {
20132 +                               ActivePortKilobytes = pAC->GIni.GIRamSize;
20133 +                       }
20134                         /* take away the minimum memory for active queues */
20135 -                       ActivePortKilobytes -= (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE);
20136 +                       ActivePortKilobytes -= MinQueueSize;
20137
20138                         /* receive queue gets the minimum + 80% of the rest */
20139 -                       pGePort->PRxQSize = (int) (ROUND_QUEUE_SIZE_KB((
20140 -                               ActivePortKilobytes * (unsigned long) RAM_QUOTA_RX) / 100))
20141 +                       pPrt->PRxQSize = SkGeRoundQueueSize(pAC,
20142 +                               (int)((long)ActivePortKilobytes * RAM_QUOTA_RX) / 100)
20143                                 + SK_MIN_RXQ_SIZE;
20144
20145 -                       ActivePortKilobytes -= (pGePort->PRxQSize - SK_MIN_RXQ_SIZE);
20146 +                       ActivePortKilobytes -= (pPrt->PRxQSize - SK_MIN_RXQ_SIZE);
20147
20148                         /* synchronous transmit queue */
20149 -                       pGePort->PXSQSize = 0;
20150 +                       pPrt->PXSQSize = 0;
20151
20152                         /* asynchronous transmit queue */
20153 -                       pGePort->PXAQSize = (int) ROUND_QUEUE_SIZE_KB(ActivePortKilobytes +
20154 -                               SK_MIN_TXQ_SIZE);
20155 +                       pPrt->PXAQSize = SkGeRoundQueueSize(pAC,
20156 +                               ActivePortKilobytes + SK_MIN_TXQ_SIZE);
20157                 }
20158         }
20159 -       else {
20160 -               /* Rlmt Mode or single link adapter */
20161 +       else {  /* RLMT Mode or single link adapter */
20162 +
20163 +               UsedKilobytes = 0;
20164
20165 -               /* Set standby queue size defaults for all standby ports */
20166 +               /* set standby queue size defaults for all standby ports */
20167                 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
20168
20169                         if (i != ActivePort) {
20170 -                               pGePort = &pAC->GIni.GP[i];
20171 +                               pPrt = &pAC->GIni.GP[i];
20172
20173 -                               pGePort->PRxQSize = SK_MIN_RXQ_SIZE;
20174 -                               pGePort->PXAQSize = SK_MIN_TXQ_SIZE;
20175 -                               pGePort->PXSQSize = 0;
20176 +                               if (DualPortYukon2) {
20177 +                                       pPrt->PRxQSize = SkGeRoundQueueSize(pAC,
20178 +                                               (int)((long)(pAC->GIni.GIRamSize - MinQueueSize) *
20179 +                                               RAM_QUOTA_RX) / 100) + SK_MIN_RXQ_SIZE;
20180 +
20181 +                                       pPrt->PXAQSize = pAC->GIni.GIRamSize - pPrt->PRxQSize;
20182 +                               }
20183 +                               else {
20184 +                                       pPrt->PRxQSize = SK_MIN_RXQ_SIZE;
20185 +                                       pPrt->PXAQSize = SK_MIN_TXQ_SIZE;
20186 +                               }
20187 +                               pPrt->PXSQSize = 0;
20188
20189                                 /* Count used RAM */
20190 -                               UsedKilobytes += pGePort->PRxQSize + pGePort->PXAQSize;
20191 +                               UsedKilobytes += pPrt->PRxQSize + pPrt->PXAQSize;
20192                         }
20193                 }
20194                 /* what's left? */
20195 -               ActivePortKilobytes = pAC->GIni.GIRamSize - UsedKilobytes;
20196 +               ActivePortKilobytes = TotalRamSize - UsedKilobytes;
20197
20198                 /* assign it to the active port */
20199                 /* first take away the minimum memory */
20200 -               ActivePortKilobytes -= (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE);
20201 -               pGePort = &pAC->GIni.GP[ActivePort];
20202 +               ActivePortKilobytes -= MinQueueSize;
20203 +               pPrt = &pAC->GIni.GP[ActivePort];
20204 +
20205 +               /* receive queue gets 80% of the rest */
20206 +               pPrt->PRxQSize = SkGeRoundQueueSize(pAC,
20207 +                       (int)((long)ActivePortKilobytes * RAM_QUOTA_RX) / 100);
20208
20209 -               /* receive queue get's the minimum + 80% of the rest */
20210 -               pGePort->PRxQSize = (int) (ROUND_QUEUE_SIZE_KB((ActivePortKilobytes *
20211 -                       (unsigned long) RAM_QUOTA_RX) / 100)) + SK_MIN_RXQ_SIZE;
20212 +               ActivePortKilobytes -= pPrt->PRxQSize;
20213
20214 -               ActivePortKilobytes -= (pGePort->PRxQSize - SK_MIN_RXQ_SIZE);
20215 +               /* add the minimum memory for Rx queue */
20216 +               pPrt->PRxQSize += MinQueueSize/2;
20217
20218                 /* synchronous transmit queue */
20219 -               pGePort->PXSQSize = 0;
20220 +               pPrt->PXSQSize = 0;
20221
20222 -               /* asynchronous transmit queue */
20223 -               pGePort->PXAQSize = (int) ROUND_QUEUE_SIZE_KB(ActivePortKilobytes) +
20224 -                       SK_MIN_TXQ_SIZE;
20225 +               /* asynchronous transmit queue gets 20% of the rest */
20226 +               pPrt->PXAQSize = SkGeRoundQueueSize(pAC, ActivePortKilobytes) +
20227 +                       /* add the minimum memory for Tx queue */
20228 +                       MinQueueSize/2;
20229         }
20230 -#ifdef VCPU
20231 -       VCPUprintf(0, "PRxQSize=%u, PXSQSize=%u, PXAQSize=%u\n",
20232 -               pGePort->PRxQSize, pGePort->PXSQSize, pGePort->PXAQSize);
20233 -#endif /* VCPU */
20234 +
20235 +#ifdef DEBUG
20236 +       for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
20237 +
20238 +               pPrt = &pAC->GIni.GP[i];
20239 +
20240 +               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
20241 +                       ("Port %d: RxQSize=%u, TxAQSize=%u, TxSQSize=%u\n",
20242 +                       i, pPrt->PRxQSize, pPrt->PXAQSize, pPrt->PXSQSize));
20243 +       }
20244 +#endif /* DEBUG */
20245
20246         return(0);
20247  }      /* SkGeInitAssignRamToQueues */
20248
20249 +
20250  /******************************************************************************
20251   *
20252   *     SkGeCheckQSize() - Checks the Adapters Queue Size Configuration
20253 @@ -360,12 +558,12 @@
20254   *     used ports.
20255   *     This requirements must be fullfilled to have a valid configuration:
20256   *             - The size of all queues must not exceed GIRamSize.
20257 - *             - The queue sizes must be specified in units of 8 kB.
20258 + *             - The queue sizes must be specified in units of 8 kB (Genesis & Yukon).
20259   *             - The size of Rx queues of available ports must not be
20260 - *               smaller than 16 kB.
20261 + *               smaller than 16 kB (Genesis & Yukon) resp. 10 kB (Yukon-2).
20262   *             - The size of at least one Tx queue (synch. or asynch.)
20263 - *        of available ports must not be smaller than 16 kB
20264 - *        when Jumbo Frames are used.
20265 + *               of available ports must not be smaller than 16 kB (Genesis & Yukon),
20266 + *               resp. 10 kB (Yukon-2) when Jumbo Frames are used.
20267   *             - The RAM start and end addresses must not be changed
20268   *               for ports which are already initialized.
20269   *     Furthermore SkGeCheckQSize() defines the Start and End Addresses
20270 @@ -376,7 +574,7 @@
20271   *     1:      Queue Size Configuration invalid
20272   */
20273  static int SkGeCheckQSize(
20274 -SK_AC   *pAC,          /* adapter context */
20275 +SK_AC   *pAC,          /* Adapter Context */
20276  int             Port)          /* port index */
20277  {
20278         SK_GEPORT *pPrt;
20279 @@ -386,55 +584,68 @@
20280         SK_U32  StartAddr;
20281  #ifndef SK_SLIM
20282         int     UsedMem;        /* total memory used (max. found ports) */
20283 -#endif
20284 +#endif
20285
20286         Rtv = 0;
20287 -
20288 +
20289  #ifndef SK_SLIM
20290
20291         UsedMem = 0;
20292 +
20293         for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
20294                 pPrt = &pAC->GIni.GP[i];
20295
20296 -               if ((pPrt->PRxQSize & QZ_UNITS) != 0 ||
20297 -                       (pPrt->PXSQSize & QZ_UNITS) != 0 ||
20298 -                       (pPrt->PXAQSize & QZ_UNITS) != 0) {
20299 +               if (CHIP_ID_YUKON_2(pAC)) {
20300 +                       UsedMem = 0;
20301 +               }
20302 +               else if (((pPrt->PRxQSize & QZ_UNITS) != 0 ||
20303 +                                 (pPrt->PXSQSize & QZ_UNITS) != 0 ||
20304 +                                 (pPrt->PXAQSize & QZ_UNITS) != 0)) {
20305
20306                         SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG);
20307                         return(1);
20308                 }
20309
20310 -               if (i == Port && pPrt->PRxQSize < SK_MIN_RXQ_SIZE) {
20311 +#ifndef SK_DIAG
20312 +               if (i == Port && pAC->GIni.GIRamSize > SK_MIN_RXQ_SIZE &&
20313 +                       pPrt->PRxQSize < SK_MIN_RXQ_SIZE) {
20314                         SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E011, SKERR_HWI_E011MSG);
20315                         return(1);
20316                 }
20317 -
20318 +
20319                 /*
20320                  * the size of at least one Tx queue (synch. or asynch.) has to be > 0.
20321                  * if Jumbo Frames are used, this size has to be >= 16 kB.
20322                  */
20323                 if ((i == Port && pPrt->PXSQSize == 0 && pPrt->PXAQSize == 0) ||
20324 -                       (pAC->GIni.GIPortUsage == SK_JUMBO_LINK &&
20325 -            ((pPrt->PXSQSize > 0 && pPrt->PXSQSize < SK_MIN_TXQ_SIZE) ||
20326 +                       (pPrt->PPortUsage == SK_JUMBO_LINK &&
20327 +                       ((pPrt->PXSQSize > 0 && pPrt->PXSQSize < SK_MIN_TXQ_SIZE) ||
20328                          (pPrt->PXAQSize > 0 && pPrt->PXAQSize < SK_MIN_TXQ_SIZE)))) {
20329                                 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E023, SKERR_HWI_E023MSG);
20330                                 return(1);
20331                 }
20332 -
20333 +#endif /* !SK_DIAG */
20334 +
20335                 UsedMem += pPrt->PRxQSize + pPrt->PXSQSize + pPrt->PXAQSize;
20336 +
20337 +               if (UsedMem > pAC->GIni.GIRamSize) {
20338 +                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG);
20339 +                       return(1);
20340 +               }
20341         }
20342 -
20343 -       if (UsedMem > pAC->GIni.GIRamSize) {
20344 -               SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG);
20345 -               return(1);
20346 -       }
20347 -#endif /* !SK_SLIM */
20348 +
20349 +#endif /* !SK_SLIM */
20350
20351         /* Now start address calculation */
20352         StartAddr = pAC->GIni.GIRamOffs;
20353         for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
20354 +
20355                 pPrt = &pAC->GIni.GP[i];
20356
20357 +               if (CHIP_ID_YUKON_2(pAC)) {
20358 +                       StartAddr = 0;
20359 +               }
20360 +
20361                 /* Calculate/Check values for the receive queue */
20362                 Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PRxQSize, &StartAddr,
20363                         &pPrt->PRxQRamStart, &pPrt->PRxQRamEnd);
20364 @@ -474,8 +685,8 @@
20365   *     nothing
20366   */
20367  static void SkGeInitMacArb(
20368 -SK_AC  *pAC,           /* adapter context */
20369 -SK_IOC IoC)            /* IO context */
20370 +SK_AC  *pAC,           /* Adapter Context */
20371 +SK_IOC IoC)            /* I/O Context */
20372  {
20373         /* release local reset */
20374         SK_OUT16(IoC, B3_MA_TO_CTRL, MA_RST_CLR);
20375 @@ -514,8 +725,8 @@
20376   *     nothing
20377   */
20378  static void SkGeInitPktArb(
20379 -SK_AC  *pAC,           /* adapter context */
20380 -SK_IOC IoC)            /* IO context */
20381 +SK_AC  *pAC,           /* Adapter Context */
20382 +SK_IOC IoC)            /* I/O Context */
20383  {
20384         /* release local reset */
20385         SK_OUT16(IoC, B3_PA_CTRL, PA_RST_CLR);
20386 @@ -531,7 +742,8 @@
20387          * NOTE: the packet arbiter timeout interrupt is needed for
20388          * half duplex hangup workaround
20389          */
20390 -       if (pAC->GIni.GIPortUsage != SK_JUMBO_LINK) {
20391 +       if (pAC->GIni.GP[MAC_1].PPortUsage != SK_JUMBO_LINK &&
20392 +               pAC->GIni.GP[MAC_2].PPortUsage != SK_JUMBO_LINK) {
20393                 if (pAC->GIni.GIMacsFound == 1) {
20394                         SK_OUT16(IoC, B3_PA_CTRL, PA_ENA_TO_TX1);
20395                 }
20396 @@ -554,14 +766,11 @@
20397   *     nothing
20398   */
20399  static void SkGeInitMacFifo(
20400 -SK_AC  *pAC,           /* adapter context */
20401 -SK_IOC IoC,            /* IO context */
20402 +SK_AC  *pAC,           /* Adapter Context */
20403 +SK_IOC IoC,            /* I/O Context */
20404  int            Port)           /* Port Index (MAC_1 + n) */
20405  {
20406         SK_U16  Word;
20407 -#ifdef VCPU
20408 -       SK_U32  DWord;
20409 -#endif /* VCPU */
20410         /*
20411          * For each FIFO:
20412          *      - release local reset
20413 @@ -569,63 +778,107 @@
20414          *      - setup defaults for the control register
20415          *      - enable the FIFO
20416          */
20417 -
20418 +
20419  #ifdef GENESIS
20420         if (pAC->GIni.GIGenesis) {
20421 -               /* Configure Rx MAC FIFO */
20422 +               /* configure Rx MAC FIFO */
20423                 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_CLR);
20424                 SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_RX_CTRL_DEF);
20425                 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
20426 -
20427 -               /* Configure Tx MAC FIFO */
20428 +
20429 +               /* configure Tx MAC FIFO */
20430                 SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_RST_CLR);
20431                 SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
20432                 SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
20433 -
20434 -               /* Enable frame flushing if jumbo frames used */
20435 -               if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
20436 +
20437 +               /* enable frame flushing if jumbo frames used */
20438 +               if (pAC->GIni.GP[Port].PPortUsage == SK_JUMBO_LINK) {
20439                         SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
20440                 }
20441         }
20442  #endif /* GENESIS */
20443 -
20444 +
20445  #ifdef YUKON
20446         if (pAC->GIni.GIYukon) {
20447 -               /* set Rx GMAC FIFO Flush Mask */
20448 -               SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), (SK_U16)RX_FF_FL_DEF_MSK);
20449 -
20450 +
20451                 Word = (SK_U16)GMF_RX_CTRL_DEF;
20452
20453                 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
20454 -               if (pAC->GIni.GIYukonLite && pAC->GIni.GIChipId == CHIP_ID_YUKON) {
20455 +               if (pAC->GIni.GIYukonLite /* && pAC->GIni.GIChipId == CHIP_ID_YUKON */) {
20456
20457                         Word &= ~GMF_RX_F_FL_ON;
20458                 }
20459 -
20460 -               /* Configure Rx MAC FIFO */
20461 +
20462 +               /* configure Rx GMAC FIFO */
20463                 SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR);
20464                 SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), Word);
20465 -
20466 -               /* set Rx GMAC FIFO Flush Threshold (default: 0x0a -> 56 bytes) */
20467 -               SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
20468 -
20469 -               /* Configure Tx MAC FIFO */
20470 +
20471 +               Word = RX_FF_FL_DEF_MSK;
20472 +
20473 +#ifndef SK_DIAG
20474 +               if (HW_FEATURE(pAC, HWF_WA_DEV_4115)) {
20475 +                       /*
20476 +                        * Flushing must be enabled (needed for ASF see dev. #4.29),
20477 +                        * but the flushing mask should be disabled (see dev. #4.115)
20478 +                        */
20479 +                       Word = 0;
20480 +               }
20481 +#endif /* !SK_DIAG */
20482 +
20483 +               /* set Rx GMAC FIFO Flush Mask (after clearing reset) */
20484 +               SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), Word);
20485 +
20486 +               /* default: 0x0a -> 56 bytes on Yukon-1 and 64 bytes on Yukon-2 */
20487 +               Word = (SK_U16)RX_GMF_FL_THR_DEF;
20488 +
20489 +               if (CHIP_ID_YUKON_2(pAC)) {
20490 +                       if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC &&
20491 +                               pAC->GIni.GIAsfEnabled) {
20492 +                               /* WA for dev. #4.30 (reduce to 0x08 -> 48 bytes) */
20493 +                               Word -= 2;
20494 +                       }
20495 +               }
20496 +               else {
20497 +                       /*
20498 +                       * because Pause Packet Truncation in GMAC is not working
20499 +                       * we have to increase the Flush Threshold to 64 bytes
20500 +                       * in order to flush pause packets in Rx FIFO on Yukon-1
20501 +                       */
20502 +                       Word++;
20503 +               }
20504 +
20505 +               /* set Rx GMAC FIFO Flush Threshold (after clearing reset) */
20506 +               SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), Word);
20507 +
20508 +               /* configure Tx GMAC FIFO */
20509                 SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR);
20510                 SK_OUT16(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U16)GMF_TX_CTRL_DEF);
20511 -
20512 -#ifdef VCPU
20513 -               SK_IN32(IoC, MR_ADDR(Port, RX_GMF_AF_THR), &DWord);
20514 -               SK_IN32(IoC, MR_ADDR(Port, TX_GMF_AE_THR), &DWord);
20515 -#endif /* VCPU */
20516 -
20517 -               /* set Tx GMAC FIFO Almost Empty Threshold */
20518 -/*             SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_AE_THR), 0); */
20519 +
20520 +               if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) {
20521 +                       /* set Rx Pause Threshold */
20522 +                       SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_LP_THR), (SK_U16)SK_ECU_LLPP);
20523 +                       SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_UP_THR), (SK_U16)SK_ECU_ULPP);
20524 +
20525 +                       if (pAC->GIni.GP[Port].PPortUsage == SK_JUMBO_LINK) {
20526 +                               /* set Tx GMAC FIFO Almost Empty Threshold */
20527 +                               SK_OUT16(IoC, MR_ADDR(Port, TX_GMF_AE_THR),
20528 +                                       (SK_U16)SK_ECU_AE_THR);
20529 +                               /* disable Store & Forward mode for TX */
20530 +                               SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), TX_STFW_DIS);
20531 +                       }
20532 +#ifdef TEST_ONLY
20533 +                       else {
20534 +                               /* enable Store & Forward mode for TX */
20535 +                               SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), TX_STFW_ENA);
20536 +                       }
20537 +#endif /* TEST_ONLY */
20538 +               }
20539         }
20540  #endif /* YUKON */
20541
20542  }      /* SkGeInitMacFifo */
20543
20544 -#ifdef SK_LNK_SYNC_CNT
20545 +#ifdef SK_LNK_SYNC_CNT
20546  /******************************************************************************
20547   *
20548   *     SkGeLoadLnkSyncCnt() - Load the Link Sync Counter and starts counting
20549 @@ -646,8 +899,8 @@
20550   *     nothing
20551   */
20552  void SkGeLoadLnkSyncCnt(
20553 -SK_AC  *pAC,           /* adapter context */
20554 -SK_IOC IoC,            /* IO context */
20555 +SK_AC  *pAC,           /* Adapter Context */
20556 +SK_IOC IoC,            /* I/O Context */
20557  int            Port,           /* Port Index (MAC_1 + n) */
20558  SK_U32 CntVal)         /* Counter value */
20559  {
20560 @@ -657,7 +910,7 @@
20561         SK_BOOL IrqPend;
20562
20563         /* stop counter */
20564 -       SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_STOP);
20565 +       SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LNK_STOP);
20566
20567         /*
20568          * ASIC problem:
20569 @@ -670,6 +923,7 @@
20570         IrqPend = SK_FALSE;
20571         SK_IN32(IoC, B0_ISRC, &ISrc);
20572         SK_IN32(IoC, B0_IMSK, &OrgIMsk);
20573 +
20574         if (Port == MAC_1) {
20575                 NewIMsk = OrgIMsk & ~IS_LNK_SYNC_M1;
20576                 if ((ISrc & IS_LNK_SYNC_M1) != 0) {
20577 @@ -682,6 +936,7 @@
20578                         IrqPend = SK_TRUE;
20579                 }
20580         }
20581 +
20582         if (!IrqPend) {
20583                 SK_OUT32(IoC, B0_IMSK, NewIMsk);
20584         }
20585 @@ -690,15 +945,17 @@
20586         SK_OUT32(IoC, MR_ADDR(Port, LNK_SYNC_INI), CntVal);
20587
20588         /* start counter */
20589 -       SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_START);
20590 +       SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LNK_START);
20591
20592         if (!IrqPend) {
20593 -               /* clear the unexpected IRQ, and restore the interrupt mask */
20594 -               SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_CLR_IRQ);
20595 +               /* clear the unexpected IRQ */
20596 +               SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LNK_CLR_IRQ);
20597 +
20598 +               /* restore the interrupt mask */
20599                 SK_OUT32(IoC, B0_IMSK, OrgIMsk);
20600         }
20601  }      /* SkGeLoadLnkSyncCnt*/
20602 -#endif /* SK_LNK_SYNC_CNT */
20603 +#endif /* SK_LNK_SYNC_CNT */
20604
20605  #if defined(SK_DIAG) || defined(SK_CFG_SYNC)
20606  /******************************************************************************
20607 @@ -730,8 +987,8 @@
20608   *             synchronous queue is configured
20609   */
20610  int SkGeCfgSync(
20611 -SK_AC  *pAC,           /* adapter context */
20612 -SK_IOC IoC,            /* IO context */
20613 +SK_AC  *pAC,           /* Adapter Context */
20614 +SK_IOC IoC,            /* I/O Context */
20615  int            Port,           /* Port Index (MAC_1 + n) */
20616  SK_U32 IntTime,        /* Interval Timer Value in units of 8ns */
20617  SK_U32 LimCount,       /* Number of bytes to transfer during IntTime */
20618 @@ -749,16 +1006,16 @@
20619                 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG);
20620                 return(1);
20621         }
20622 -
20623 +
20624         if (pAC->GIni.GP[Port].PXSQSize == 0) {
20625                 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E009, SKERR_HWI_E009MSG);
20626                 return(2);
20627         }
20628 -
20629 +
20630         /* calculate register values */
20631         IntTime = (IntTime / 2) * pAC->GIni.GIHstClkFact / 100;
20632         LimCount = LimCount / 8;
20633 -
20634 +
20635         if (IntTime > TXA_MAX_VAL || LimCount > TXA_MAX_VAL) {
20636                 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG);
20637                 return(1);
20638 @@ -776,13 +1033,13 @@
20639          */
20640         SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
20641                 TXA_ENA_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
20642 -
20643 +
20644         SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), IntTime);
20645         SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), LimCount);
20646 -
20647 +
20648         SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
20649                 (SK_U8)(SyncMode & (TXA_ENA_ALLOC | TXA_DIS_ALLOC)));
20650 -
20651 +
20652         if (IntTime != 0 || LimCount != 0) {
20653                 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_DIS_FSYNC | TXA_START_RC);
20654         }
20655 @@ -803,10 +1060,10 @@
20656   * Returns:
20657   *     nothing
20658   */
20659 -static void DoInitRamQueue(
20660 -SK_AC  *pAC,                   /* adapter context */
20661 -SK_IOC IoC,                    /* IO context */
20662 -int            QuIoOffs,               /* Queue IO Address Offset */
20663 +void DoInitRamQueue(
20664 +SK_AC  *pAC,                   /* Adapter Context */
20665 +SK_IOC IoC,                    /* I/O Context */
20666 +int            QuIoOffs,               /* Queue I/O Address Offset */
20667  SK_U32 QuStartAddr,    /* Queue Start Address */
20668  SK_U32 QuEndAddr,              /* Queue End Address */
20669  int            QuType)                 /* Queue Type (SK_RX_SRAM_Q|SK_RX_BRAM_Q|SK_TX_RAM_Q) */
20670 @@ -839,8 +1096,7 @@
20671
20672                         /* continue with SK_RX_BRAM_Q */
20673                 case SK_RX_BRAM_Q:
20674 -                       /* write threshold for Rx Queue */
20675 -
20676 +                       /* write threshold for Rx Queue (Pause packets) */
20677                         SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RX_UTPP), RxUpThresVal);
20678                         SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RX_LTPP), RxLoThresVal);
20679
20680 @@ -854,7 +1110,8 @@
20681                          * or YUKON is used ((GMAC Tx FIFO is only 1 kB)
20682                          * we NEED Store & Forward of the RAM buffer.
20683                          */
20684 -                       if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK ||
20685 +                       if (pAC->GIni.GP[MAC_1].PPortUsage == SK_JUMBO_LINK ||
20686 +                               pAC->GIni.GP[MAC_2].PPortUsage == SK_JUMBO_LINK ||
20687                                 pAC->GIni.GIYukon) {
20688                                 /* enable Store & Forward Mode for the Tx Side */
20689                                 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_ENA_STFWD);
20690 @@ -883,8 +1140,8 @@
20691   *     nothing
20692   */
20693  static void SkGeInitRamBufs(
20694 -SK_AC  *pAC,           /* adapter context */
20695 -SK_IOC IoC,            /* IO context */
20696 +SK_AC  *pAC,           /* Adapter Context */
20697 +SK_IOC IoC,            /* I/O Context */
20698  int            Port)           /* Port Index (MAC_1 + n) */
20699  {
20700         SK_GEPORT *pPrt;
20701 @@ -892,8 +1149,8 @@
20702
20703         pPrt = &pAC->GIni.GP[Port];
20704
20705 -       if (pPrt->PRxQSize == SK_MIN_RXQ_SIZE) {
20706 -               RxQType = SK_RX_SRAM_Q;         /* small Rx Queue */
20707 +       if (pPrt->PRxQSize <= SK_MIN_RXQ_SIZE) {
20708 +               RxQType = SK_RX_SRAM_Q;         /* small Rx Queue */
20709         }
20710         else {
20711                 RxQType = SK_RX_BRAM_Q;         /* big Rx Queue */
20712 @@ -901,10 +1158,10 @@
20713
20714         DoInitRamQueue(pAC, IoC, pPrt->PRxQOff, pPrt->PRxQRamStart,
20715                 pPrt->PRxQRamEnd, RxQType);
20716 -
20717 +
20718         DoInitRamQueue(pAC, IoC, pPrt->PXsQOff, pPrt->PXsQRamStart,
20719                 pPrt->PXsQRamEnd, SK_TX_RAM_Q);
20720 -
20721 +
20722         DoInitRamQueue(pAC, IoC, pPrt->PXaQOff, pPrt->PXaQRamStart,
20723                 pPrt->PXaQRamEnd, SK_TX_RAM_Q);
20724
20725 @@ -924,27 +1181,38 @@
20726   * Returns:
20727   *     nothing
20728   */
20729 -static void SkGeInitRamIface(
20730 -SK_AC  *pAC,           /* adapter context */
20731 -SK_IOC IoC)            /* IO context */
20732 +void SkGeInitRamIface(
20733 +SK_AC  *pAC,           /* Adapter Context */
20734 +SK_IOC IoC)            /* I/O Context */
20735  {
20736 -       /* release local reset */
20737 -       SK_OUT16(IoC, B3_RI_CTRL, RI_RST_CLR);
20738 +       int i;
20739 +       int RamBuffers;
20740
20741 -       /* configure timeout values */
20742 -       SK_OUT8(IoC, B3_RI_WTO_R1, SK_RI_TO_53);
20743 -       SK_OUT8(IoC, B3_RI_WTO_XA1, SK_RI_TO_53);
20744 -       SK_OUT8(IoC, B3_RI_WTO_XS1, SK_RI_TO_53);
20745 -       SK_OUT8(IoC, B3_RI_RTO_R1, SK_RI_TO_53);
20746 -       SK_OUT8(IoC, B3_RI_RTO_XA1, SK_RI_TO_53);
20747 -       SK_OUT8(IoC, B3_RI_RTO_XS1, SK_RI_TO_53);
20748 -       SK_OUT8(IoC, B3_RI_WTO_R2, SK_RI_TO_53);
20749 -       SK_OUT8(IoC, B3_RI_WTO_XA2, SK_RI_TO_53);
20750 -       SK_OUT8(IoC, B3_RI_WTO_XS2, SK_RI_TO_53);
20751 -       SK_OUT8(IoC, B3_RI_RTO_R2, SK_RI_TO_53);
20752 -       SK_OUT8(IoC, B3_RI_RTO_XA2, SK_RI_TO_53);
20753 -       SK_OUT8(IoC, B3_RI_RTO_XS2, SK_RI_TO_53);
20754 +       if (CHIP_ID_YUKON_2(pAC)) {
20755 +               RamBuffers = pAC->GIni.GIMacsFound;
20756 +       }
20757 +       else {
20758 +               RamBuffers = 1;
20759 +       }
20760
20761 +       for (i = 0; i < RamBuffers; i++) {
20762 +               /* release local reset */
20763 +               SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_CTRL), (SK_U8)RI_RST_CLR);
20764 +
20765 +               /* configure timeout values */
20766 +               SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
20767 +               SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
20768 +               SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
20769 +               SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
20770 +               SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
20771 +               SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
20772 +               SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
20773 +               SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
20774 +               SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
20775 +               SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
20776 +               SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
20777 +               SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
20778 +       }
20779  }      /* SkGeInitRamIface */
20780
20781
20782 @@ -959,41 +1227,91 @@
20783   *     nothing
20784   */
20785  static void SkGeInitBmu(
20786 -SK_AC  *pAC,           /* adapter context */
20787 -SK_IOC IoC,            /* IO context */
20788 +SK_AC  *pAC,           /* Adapter Context */
20789 +SK_IOC IoC,            /* I/O Context */
20790  int            Port)           /* Port Index (MAC_1 + n) */
20791  {
20792         SK_GEPORT       *pPrt;
20793 -       SK_U32          RxWm;
20794 -       SK_U32          TxWm;
20795 +       SK_U16          RxWm;
20796 +       SK_U16          TxWm;
20797
20798         pPrt = &pAC->GIni.GP[Port];
20799
20800         RxWm = SK_BMU_RX_WM;
20801         TxWm = SK_BMU_TX_WM;
20802 -
20803 -       if (!pAC->GIni.GIPciSlot64 && !pAC->GIni.GIPciClock66) {
20804 -               /* for better performance */
20805 -               RxWm /= 2;
20806 -               TxWm /= 2;
20807 -       }
20808
20809 -       /* Rx Queue: Release all local resets and set the watermark */
20810 -       SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_CLR_RESET);
20811 -       SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_F), RxWm);
20812 +       if (CHIP_ID_YUKON_2(pAC)) {
20813
20814 -       /*
20815 -        * Tx Queue: Release all local resets if the queue is used !
20816 -        *              set watermark
20817 -        */
20818 -       if (pPrt->PXSQSize != 0) {
20819 -               SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_CLR_RESET);
20820 -               SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_F), TxWm);
20821 +               if (pAC->GIni.GIPciBus == SK_PEX_BUS) {
20822 +                       /* for better performance set it to 128 */
20823 +                       RxWm = SK_BMU_RX_WM_PEX;
20824 +               }
20825 +
20826 +               /* Rx Queue: Release all local resets and set the watermark */
20827 +               SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), BMU_CLR_RESET);
20828 +               SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), BMU_OPER_INIT);
20829 +               SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), BMU_FIFO_OP_ON);
20830 +
20831 +               SK_OUT16(IoC, Q_ADDR(pPrt->PRxQOff, Q_WM), RxWm);
20832 +
20833 +               if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U &&
20834 +                       pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A1) {
20835 +                       /* MAC Rx RAM Read is controlled by hardware */
20836 +                       SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_F), F_M_RX_RAM_DIS);
20837 +               }
20838 +
20839 +               /*
20840 +                * Tx Queue: Release all local resets if the queue is used !
20841 +                *              set watermark
20842 +                */
20843 +               if (pPrt->PXSQSize != 0 && HW_SYNC_TX_SUPPORTED(pAC)) {
20844 +                       /* Yukon-EC doesn't have a synchronous Tx queue */
20845 +                       SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), BMU_CLR_RESET);
20846 +                       SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), BMU_OPER_INIT);
20847 +                       SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), BMU_FIFO_OP_ON);
20848 +
20849 +                       SK_OUT16(IoC, Q_ADDR(pPrt->PXsQOff, Q_WM), TxWm);
20850 +               }
20851 +
20852 +               if (pPrt->PXAQSize != 0) {
20853 +
20854 +                       SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), BMU_CLR_RESET);
20855 +                       SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), BMU_OPER_INIT);
20856 +                       SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), BMU_FIFO_OP_ON);
20857 +
20858 +                       SK_OUT16(IoC, Q_ADDR(pPrt->PXaQOff, Q_WM), TxWm);
20859 +
20860 +                       if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U &&
20861 +                               pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A0) {
20862 +                               /* fix for Yukon-EC Ultra: set BMU FIFO level */
20863 +                               SK_OUT16(IoC, Q_ADDR(pPrt->PXaQOff, Q_AL), SK_ECU_TXFF_LEV);
20864 +                       }
20865 +               }
20866         }
20867 -
20868 -       if (pPrt->PXAQSize != 0) {
20869 -               SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_CLR_RESET);
20870 -               SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_F), TxWm);
20871 +       else {
20872 +               if (!pAC->GIni.GIPciSlot64 && !pAC->GIni.GIPciClock66) {
20873 +                       /* for better performance */
20874 +                       RxWm /= 2;
20875 +                       TxWm /= 2;
20876 +               }
20877 +
20878 +               /* Rx Queue: Release all local resets and set the watermark */
20879 +               SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_CLR_RESET);
20880 +               SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_F), RxWm);
20881 +
20882 +               /*
20883 +                * Tx Queue: Release all local resets if the queue is used !
20884 +                *              set watermark
20885 +                */
20886 +               if (pPrt->PXSQSize != 0) {
20887 +                       SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_CLR_RESET);
20888 +                       SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_F), TxWm);
20889 +               }
20890 +
20891 +               if (pPrt->PXAQSize != 0) {
20892 +                       SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_CLR_RESET);
20893 +                       SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_F), TxWm);
20894 +               }
20895         }
20896         /*
20897          * Do NOT enable the descriptor poll timers here, because
20898 @@ -1017,20 +1335,29 @@
20899   */
20900  static SK_U32 TestStopBit(
20901  SK_AC  *pAC,           /* Adapter Context */
20902 -SK_IOC IoC,            /* IO Context */
20903 -int            QuIoOffs)       /* Queue IO Address Offset */
20904 +SK_IOC IoC,            /* I/O Context */
20905 +int            QuIoOffs)       /* Queue I/O Address Offset */
20906  {
20907         SK_U32  QuCsr;  /* CSR contents */
20908
20909         SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
20910 -
20911 -       if ((QuCsr & (CSR_STOP | CSR_SV_IDLE)) == 0) {
20912 -               /* Stop Descriptor overridden by start command */
20913 -               SK_OUT32(IoC, Q_ADDR(QuIoOffs, Q_CSR), CSR_STOP);
20914
20915 -               SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
20916 +       if (CHIP_ID_YUKON_2(pAC)) {
20917 +               if ((QuCsr & (BMU_STOP | BMU_IDLE)) == 0) {
20918 +                       /* Stop Descriptor overridden by start command */
20919 +                       SK_OUT32(IoC, Q_ADDR(QuIoOffs, Q_CSR), BMU_STOP);
20920 +
20921 +                       SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
20922 +               }
20923 +       }
20924 +       else {
20925 +               if ((QuCsr & (CSR_STOP | CSR_SV_IDLE)) == 0) {
20926 +                       /* Stop Descriptor overridden by start command */
20927 +                       SK_OUT32(IoC, Q_ADDR(QuIoOffs, Q_CSR), CSR_STOP);
20928 +
20929 +                       SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
20930 +               }
20931         }
20932 -
20933         return(QuCsr);
20934  }      /* TestStopBit */
20935
20936 @@ -1054,8 +1381,8 @@
20937   *                             has to be stopped once before.
20938   *             SK_STOP_ALL     SK_STOP_TX + SK_STOP_RX
20939   *
20940 - *     RstMode = SK_SOFT_RST   Resets the MAC. The PHY is still alive.
20941 - *                     SK_HARD_RST     Resets the MAC and the PHY.
20942 + *     RstMode =       SK_SOFT_RST     Resets the MAC, the PHY is still alive.
20943 + *                             SK_HARD_RST     Resets the MAC and the PHY.
20944   *
20945   * Example:
20946   *     1) A Link Down event was signaled for a port. Therefore the activity
20947 @@ -1114,56 +1441,82 @@
20948   *       SWITCH_PORT.
20949   */
20950  void SkGeStopPort(
20951 -SK_AC  *pAC,   /* adapter context */
20952 -SK_IOC IoC,    /* I/O context */
20953 -int            Port,   /* port to stop (MAC_1 + n) */
20954 +SK_AC  *pAC,   /* Adapter Context */
20955 +SK_IOC IoC,    /* I/O Context */
20956 +int            Port,   /* Port to stop (MAC_1 + n) */
20957  int            Dir,    /* Direction to Stop (SK_STOP_RX, SK_STOP_TX, SK_STOP_ALL) */
20958  int            RstMode)/* Reset Mode (SK_SOFT_RST, SK_HARD_RST) */
20959  {
20960 -#ifndef SK_DIAG
20961 -       SK_EVPARA Para;
20962 -#endif /* !SK_DIAG */
20963         SK_GEPORT *pPrt;
20964 -       SK_U32  DWord;
20965 +       SK_U32  RxCsr;
20966         SK_U32  XsCsr;
20967         SK_U32  XaCsr;
20968         SK_U64  ToutStart;
20969 +       SK_U32  CsrStart;
20970 +       SK_U32  CsrStop;
20971 +       SK_U32  CsrIdle;
20972 +       SK_U32  CsrTest;
20973 +       SK_U8   rsl;    /* FIFO read shadow level */
20974 +       SK_U8   rl;             /* FIFO read level */
20975         int             i;
20976         int             ToutCnt;
20977
20978         pPrt = &pAC->GIni.GP[Port];
20979
20980 +       /* set the proper values of Q_CSR register layout depending on the chip */
20981 +       if (CHIP_ID_YUKON_2(pAC)) {
20982 +               CsrStart = BMU_START;
20983 +               CsrStop = BMU_STOP;
20984 +               CsrIdle = BMU_IDLE;
20985 +               CsrTest = BMU_IDLE;
20986 +       }
20987 +       else {
20988 +               CsrStart = CSR_START;
20989 +               CsrStop = CSR_STOP;
20990 +               CsrIdle = CSR_SV_IDLE;
20991 +               CsrTest = CSR_SV_IDLE | CSR_STOP;
20992 +       }
20993 +
20994         if ((Dir & SK_STOP_TX) != 0) {
20995 -               /* disable receiver and transmitter */
20996 -               SkMacRxTxDisable(pAC, IoC, Port);
20997 -
20998 +
20999 +               if (!pAC->GIni.GIAsfEnabled) {
21000 +                       /* disable receiver and transmitter */
21001 +                       SkMacRxTxDisable(pAC, IoC, Port);
21002 +               }
21003 +
21004                 /* stop both transmit queues */
21005 +               SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CsrStop);
21006 +               SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CsrStop);
21007                 /*
21008                  * If the BMU is in the reset state CSR_STOP will terminate
21009                  * immediately.
21010                  */
21011 -               SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_STOP);
21012 -               SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_STOP);
21013
21014                 ToutStart = SkOsGetTime(pAC);
21015                 ToutCnt = 0;
21016                 do {
21017 -                       /*
21018 -                        * Clear packet arbiter timeout to make sure
21019 -                        * this loop will terminate.
21020 -                        */
21021 -                       SK_OUT16(IoC, B3_PA_CTRL, (SK_U16)((Port == MAC_1) ?
21022 -                               PA_CLR_TO_TX1 : PA_CLR_TO_TX2));
21023 -
21024 -                       /*
21025 -                        * If the transfer stucks at the MAC the STOP command will not
21026 -                        * terminate if we don't flush the XMAC's transmit FIFO !
21027 -                        */
21028 -                       SkMacFlushTxFifo(pAC, IoC, Port);
21029 -
21030 -                       XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff);
21031 +#ifdef GENESIS
21032 +                       if (pAC->GIni.GIGenesis) {
21033 +                               /* clear Tx packet arbiter timeout IRQ */
21034 +                               SK_OUT16(IoC, B3_PA_CTRL, (SK_U16)((Port == MAC_1) ?
21035 +                                       PA_CLR_TO_TX1 : PA_CLR_TO_TX2));
21036 +                               /*
21037 +                                * If the transfer stucks at the XMAC the STOP command will not
21038 +                                * terminate if we don't flush the XMAC's transmit FIFO !
21039 +                                */
21040 +                               SkMacFlushTxFifo(pAC, IoC, Port);
21041 +                       }
21042 +#endif /* GENESIS */
21043 +
21044                         XaCsr = TestStopBit(pAC, IoC, pPrt->PXaQOff);
21045
21046 +                       if (HW_SYNC_TX_SUPPORTED(pAC)) {
21047 +                               XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff);
21048 +                       }
21049 +                       else {
21050 +                               XsCsr = XaCsr;
21051 +                       }
21052 +
21053                         if (SkOsGetTime(pAC) - ToutStart > (SK_TICKS_PER_SEC / 18)) {
21054                                 /*
21055                                  * Timeout of 1/18 second reached.
21056 @@ -1171,67 +1524,115 @@
21057                                  */
21058                                 ToutCnt++;
21059                                 if (ToutCnt > 1) {
21060 -                                       /* Might be a problem when the driver event handler
21061 -                                        * calls StopPort again. XXX.
21062 +                                       /*
21063 +                                        * If BMU stop doesn't terminate, we assume that
21064 +                                        * we have a stable state and can reset the BMU,
21065 +                                        * the Prefetch Unit, and RAM buffer now.
21066                                          */
21067 -
21068 -                                       /* Fatal Error, Loop aborted */
21069 -                                       SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E018,
21070 -                                               SKERR_HWI_E018MSG);
21071 -#ifndef SK_DIAG
21072 -                                       Para.Para64 = Port;
21073 -                                       SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
21074 -#endif /* !SK_DIAG */
21075 -                                       return;
21076 +                                       break;                  /* ===> leave do/while loop here */
21077                                 }
21078                                 /*
21079 -                                * Cache incoherency workaround: Assume a start command
21080 +                                * Cache incoherency workaround: assume a start command
21081                                  * has been lost while sending the frame.
21082                                  */
21083                                 ToutStart = SkOsGetTime(pAC);
21084
21085 -                               if ((XsCsr & CSR_STOP) != 0) {
21086 -                                       SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_START);
21087 +                               if ((XsCsr & CsrStop) != 0) {
21088 +                                       SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CsrStart);
21089                                 }
21090 -                               if ((XaCsr & CSR_STOP) != 0) {
21091 -                                       SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_START);
21092 +
21093 +                               if ((XaCsr & CsrStop) != 0) {
21094 +                                       SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CsrStart);
21095                                 }
21096 -                       }
21097
21098 +                               /*
21099 +                                * After the previous operations the X(s|a)Csr does no
21100 +                                * longer contain the proper values
21101 +                                */
21102 +                               XaCsr = TestStopBit(pAC, IoC, pPrt->PXaQOff);
21103 +
21104 +                               if (HW_SYNC_TX_SUPPORTED(pAC)) {
21105 +                                       XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff);
21106 +                               }
21107 +                               else {
21108 +                                       XsCsr = XaCsr;
21109 +                               }
21110 +                       }
21111                         /*
21112                          * Because of the ASIC problem report entry from 21.08.1998 it is
21113                          * required to wait until CSR_STOP is reset and CSR_SV_IDLE is set.
21114 +                        * (valid for GENESIS only)
21115                          */
21116 -               } while ((XsCsr & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE ||
21117 -                                (XaCsr & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE);
21118 +               } while (((XsCsr & CsrTest) != CsrIdle ||
21119 +                                 (XaCsr & CsrTest) != CsrIdle));
21120 +
21121 +               if (pAC->GIni.GIAsfEnabled) {
21122
21123 -               /* Reset the MAC depending on the RstMode */
21124 -               if (RstMode == SK_SOFT_RST) {
21125 -                       SkMacSoftRst(pAC, IoC, Port);
21126 +                       pPrt->PState = (RstMode == SK_SOFT_RST) ? SK_PRT_STOP :
21127 +                               SK_PRT_RESET;
21128                 }
21129                 else {
21130 -                       SkMacHardRst(pAC, IoC, Port);
21131 +                       /* Reset the MAC depending on the RstMode */
21132 +                       if (RstMode == SK_SOFT_RST) {
21133 +
21134 +                               SkMacSoftRst(pAC, IoC, Port);
21135 +                       }
21136 +                       else {
21137 +#ifdef SK_DIAG
21138 +                               if (HW_FEATURE(pAC, HWF_WA_DEV_472) && Port == MAC_1 &&
21139 +                                       pAC->GIni.GP[MAC_2].PState == SK_PRT_RUN) {
21140 +
21141 +                                       pAC->GIni.GP[MAC_1].PState = SK_PRT_RESET;
21142 +
21143 +                                       /* set GPHY Control reset */
21144 +                                       SK_OUT8(IoC, MR_ADDR(MAC_1, GPHY_CTRL), (SK_U8)GPC_RST_SET);
21145 +                               }
21146 +                               else {
21147 +
21148 +                                       SkMacHardRst(pAC, IoC, Port);
21149 +                               }
21150 +#else /* !SK_DIAG */
21151 +                               SkMacHardRst(pAC, IoC, Port);
21152 +#endif /* !SK_DIAG */
21153 +                       }
21154                 }
21155 -
21156 -               /* Disable Force Sync bit and Enable Alloc bit */
21157 +
21158 +               /* disable Force Sync bit and Enable Alloc bit */
21159                 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
21160                         TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
21161 -
21162 +
21163                 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
21164                 SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), 0L);
21165                 SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), 0L);
21166
21167                 /* Perform a local reset of the port's Tx path */
21168 +               if (CHIP_ID_YUKON_2(pAC)) {
21169 +                       /* Reset the PCI FIFO of the async Tx queue */
21170 +                       SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR),
21171 +                               BMU_RST_SET | BMU_FIFO_RST);
21172 +
21173 +                       /* Reset the PCI FIFO of the sync Tx queue */
21174 +                       SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR),
21175 +                               BMU_RST_SET | BMU_FIFO_RST);
21176 +
21177 +                       /* Reset the Tx prefetch units */
21178 +                       SK_OUT32(IoC, Y2_PREF_Q_ADDR(pPrt->PXaQOff, PREF_UNIT_CTRL_REG),
21179 +                               PREF_UNIT_RST_SET);
21180 +                       SK_OUT32(IoC, Y2_PREF_Q_ADDR(pPrt->PXsQOff, PREF_UNIT_CTRL_REG),
21181 +                               PREF_UNIT_RST_SET);
21182 +               }
21183 +               else {
21184 +                       /* Reset the PCI FIFO of the async Tx queue */
21185 +                       SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_SET_RESET);
21186 +                       /* Reset the PCI FIFO of the sync Tx queue */
21187 +                       SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_SET_RESET);
21188 +               }
21189
21190 -               /* Reset the PCI FIFO of the async Tx queue */
21191 -               SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_SET_RESET);
21192 -               /* Reset the PCI FIFO of the sync Tx queue */
21193 -               SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_SET_RESET);
21194                 /* Reset the RAM Buffer async Tx queue */
21195                 SK_OUT8(IoC, RB_ADDR(pPrt->PXaQOff, RB_CTRL), RB_RST_SET);
21196                 /* Reset the RAM Buffer sync Tx queue */
21197                 SK_OUT8(IoC, RB_ADDR(pPrt->PXsQOff, RB_CTRL), RB_RST_SET);
21198 -
21199 +
21200                 /* Reset Tx MAC FIFO */
21201  #ifdef GENESIS
21202                 if (pAC->GIni.GIGenesis) {
21203 @@ -1243,74 +1644,132 @@
21204                         SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_DIS);
21205                 }
21206  #endif /* GENESIS */
21207 -
21208 +
21209  #ifdef YUKON
21210                 if (pAC->GIni.GIYukon) {
21211 -                       /* Reset TX MAC FIFO */
21212 -                       SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_SET);
21213 +                       /* do the reset only if ASF is not enabled */
21214 +                       if (!pAC->GIni.GIAsfEnabled) {
21215 +                               /* Reset Tx MAC FIFO */
21216 +                               SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_SET);
21217 +                       }
21218 +
21219 +                       /* set Pause Off */
21220 +                       SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_PAUSE_OFF);
21221                 }
21222  #endif /* YUKON */
21223         }
21224
21225         if ((Dir & SK_STOP_RX) != 0) {
21226 -               /*
21227 -                * The RX Stop Command will not terminate if no buffers
21228 -                * are queued in the RxD ring. But it will always reach
21229 -                * the Idle state. Therefore we can use this feature to
21230 -                * stop the transfer of received packets.
21231 -                */
21232 -               /* stop the port's receive queue */
21233 -               SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_STOP);
21234 -
21235 -               i = 100;
21236 -               do {
21237 +
21238 +               if (CHIP_ID_YUKON_2(pAC)) {
21239                         /*
21240 -                        * Clear packet arbiter timeout to make sure
21241 -                        * this loop will terminate
21242 +                        * The RX Stop command will not work for Yukon-2 if the BMU does not
21243 +                        * reach the end of packet and since we can't make sure that we have
21244 +                        * incoming data, we must reset the BMU while it is not during a DMA
21245 +                        * transfer. Since it is possible that the RX path is still active,
21246 +                        * the RX RAM buffer will be stopped first, so any possible incoming
21247 +                        * data will not trigger a DMA. After the RAM buffer is stopped, the
21248 +                        * BMU is polled until any DMA in progress is ended and only then it
21249 +                        * will be reset.
21250                          */
21251 -                       SK_OUT16(IoC, B3_PA_CTRL, (SK_U16)((Port == MAC_1) ?
21252 -                               PA_CLR_TO_RX1 : PA_CLR_TO_RX2));
21253
21254 -                       DWord = TestStopBit(pAC, IoC, pPrt->PRxQOff);
21255 +                       /* disable the RAM Buffer receive queue */
21256 +                       SK_OUT8(IoC, RB_ADDR(pPrt->PRxQOff, RB_CTRL), RB_DIS_OP_MD);
21257
21258 -                       /* timeout if i==0 (bug fix for #10748) */
21259 -                       if (--i == 0) {
21260 -                               SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E024,
21261 -                                       SKERR_HWI_E024MSG);
21262 -                               break;
21263 +                       i = 0xffff;
21264 +                       while (--i) {
21265 +                               SK_IN8(IoC, RB_ADDR(pPrt->PRxQOff, Q_RX_RSL), &rsl);
21266 +                               SK_IN8(IoC, RB_ADDR(pPrt->PRxQOff, Q_RX_RL), &rl);
21267 +
21268 +                               if (rsl == rl) {
21269 +                                       break;
21270 +                               }
21271                         }
21272 +
21273 +                       /*
21274 +                        * If the Rx side is blocked, the above loop cannot terminate.
21275 +                        * But, if there was any traffic it should be terminated, now.
21276 +                        * However, stop the Rx BMU and the Prefetch Unit !
21277 +                        */
21278 +                       SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR),
21279 +                               BMU_RST_SET | BMU_FIFO_RST);
21280 +                       /* reset the Rx prefetch unit */
21281 +                       SK_OUT32(IoC, Y2_PREF_Q_ADDR(pPrt->PRxQOff, PREF_UNIT_CTRL_REG),
21282 +                               PREF_UNIT_RST_SET);
21283 +               }
21284 +               else {
21285                         /*
21286 -                        * because of the ASIC problem report entry from 21.08.98
21287 -                        * it is required to wait until CSR_STOP is reset and
21288 -                        * CSR_SV_IDLE is set.
21289 +                        * The RX Stop Command will not terminate if no buffers
21290 +                        * are queued in the RxD ring. But it will always reach
21291 +                        * the Idle state. Therefore we can use this feature to
21292 +                        * stop the transfer of received packets.
21293                          */
21294 -               } while ((DWord & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE);
21295 +                       /* stop the port's receive queue */
21296 +                       SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CsrStop);
21297
21298 -               /* The path data transfer activity is fully stopped now */
21299 +                       i = 100;
21300 +                       do {
21301 +#ifdef GENESIS
21302 +                               if (pAC->GIni.GIGenesis) {
21303 +                                       /* clear Rx packet arbiter timeout IRQ */
21304 +                                       SK_OUT16(IoC, B3_PA_CTRL, (SK_U16)((Port == MAC_1) ?
21305 +                                               PA_CLR_TO_RX1 : PA_CLR_TO_RX2));
21306 +                               }
21307 +#endif /* GENESIS */
21308
21309 -               /* Perform a local reset of the port's Rx path */
21310 +                               RxCsr = TestStopBit(pAC, IoC, pPrt->PRxQOff);
21311 +
21312 +                               /* timeout if i==0 (bug fix for #10748) */
21313 +                               if (--i == 0) {
21314 +                                       SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E024,
21315 +                                               SKERR_HWI_E024MSG);
21316 +                                       break;
21317 +                               }
21318 +                       /*
21319 +                        * Because of the ASIC problem report entry from 21.08.1998 it is
21320 +                        * required to wait until CSR_STOP is reset and CSR_SV_IDLE is set.
21321 +                        * (valid for GENESIS only)
21322 +                        */
21323 +                       } while ((RxCsr & CsrTest) != CsrIdle);
21324 +                       /* The path data transfer activity is fully stopped now */
21325 +
21326 +                       /* Perform a local reset of the port's Rx path */
21327 +                       /* Reset the PCI FIFO of the Rx queue */
21328 +                       SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_SET_RESET);
21329 +               }
21330
21331 -                /*     Reset the PCI FIFO of the Rx queue */
21332 -               SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_SET_RESET);
21333                 /* Reset the RAM Buffer receive queue */
21334                 SK_OUT8(IoC, RB_ADDR(pPrt->PRxQOff, RB_CTRL), RB_RST_SET);
21335
21336 -               /* Reset Rx MAC FIFO */
21337  #ifdef GENESIS
21338                 if (pAC->GIni.GIGenesis) {
21339 -
21340 +
21341 +                       /* Reset Rx MAC FIFO */
21342                         SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_SET);
21343
21344                         /* switch Rx LED off, stop the LED counter */
21345                         SkGeXmitLED(pAC, IoC, MR_ADDR(Port, RX_LED_INI), SK_LED_DIS);
21346                 }
21347  #endif /* GENESIS */
21348 -
21349 +
21350  #ifdef YUKON
21351 -               if (pAC->GIni.GIYukon) {
21352 +               if (pAC->GIni.GIYukon && !pAC->GIni.GIAsfEnabled) {
21353                         /* Reset Rx MAC FIFO */
21354                         SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_RST_SET);
21355                 }
21356 +
21357 +#ifndef NDIS_MINIPORT_DRIVER   /* temp. ifndef, remove after PM module rework*/
21358 +               /* WA for Dev. #4.169 */
21359 +               if ((pAC->GIni.GIChipId == CHIP_ID_YUKON ||
21360 +                        pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) &&
21361 +                       RstMode == SK_HARD_RST) {
21362 +                       /* set Link Control reset */
21363 +                       SK_OUT8(IoC, MR_ADDR(Port, GMAC_LINK_CTRL), (SK_U8)GMLC_RST_SET);
21364 +
21365 +                       /* clear Link Control reset */
21366 +                       SK_OUT8(IoC, MR_ADDR(Port, GMAC_LINK_CTRL), (SK_U8)GMLC_RST_CLR);
21367 +               }
21368 +#endif /* !NDIS_MINIPORT */
21369  #endif /* YUKON */
21370         }
21371  }      /* SkGeStopPort */
21372 @@ -1327,8 +1786,8 @@
21373   *     nothing
21374   */
21375  static void SkGeInit0(
21376 -SK_AC  *pAC,           /* adapter context */
21377 -SK_IOC IoC)            /* IO context */
21378 +SK_AC  *pAC,           /* Adapter Context */
21379 +SK_IOC IoC)            /* I/O Context */
21380  {
21381         int i;
21382         SK_GEPORT *pPrt;
21383 @@ -1337,6 +1796,7 @@
21384                 pPrt = &pAC->GIni.GP[i];
21385
21386                 pPrt->PState = SK_PRT_RESET;
21387 +               pPrt->PPortUsage = SK_RED_LINK;
21388                 pPrt->PRxQOff = QOffTab[i].RxQOff;
21389                 pPrt->PXsQOff = QOffTab[i].XsQOff;
21390                 pPrt->PXaQOff = QOffTab[i].XaQOff;
21391 @@ -1365,22 +1825,226 @@
21392                 pPrt->PLipaAutoNeg = (SK_U8)SK_LIPA_UNKNOWN;
21393                 pPrt->PAutoNegFail = SK_FALSE;
21394                 pPrt->PHWLinkUp = SK_FALSE;
21395 -               pPrt->PLinkBroken = SK_TRUE; /* See WA code */
21396 +               pPrt->PLinkBroken = SK_TRUE;    /* See WA code */
21397                 pPrt->PPhyPowerState = PHY_PM_OPERATIONAL_MODE;
21398                 pPrt->PMacColThres = TX_COL_DEF;
21399                 pPrt->PMacJamLen = TX_JAM_LEN_DEF;
21400                 pPrt->PMacJamIpgVal     = TX_JAM_IPG_DEF;
21401                 pPrt->PMacJamIpgData = TX_IPG_JAM_DEF;
21402 +               pPrt->PMacBackOffLim = TX_BOF_LIM_DEF;
21403 +               pPrt->PMacDataBlind = DATA_BLIND_DEF;
21404                 pPrt->PMacIpgData = IPG_DATA_DEF;
21405                 pPrt->PMacLimit4 = SK_FALSE;
21406         }
21407
21408 -       pAC->GIni.GIPortUsage = SK_RED_LINK;
21409         pAC->GIni.GILedBlinkCtrl = (SK_U16)OemConfig.Value;
21410 -       pAC->GIni.GIValIrqMask = IS_ALL_MSK;
21411 +       pAC->GIni.GIChipCap = 0;
21412 +
21413 +       for (i = 0; i < 4; i++) {
21414 +               pAC->GIni.HwF.Features[i]= 0x00000000;
21415 +               pAC->GIni.HwF.OnMask[i]  = 0x00000000;
21416 +               pAC->GIni.HwF.OffMask[i] = 0x00000000;
21417 +       }
21418
21419  }      /* SkGeInit0*/
21420
21421 +#ifdef SK_PCI_RESET
21422 +/******************************************************************************
21423 + *
21424 + *     SkGePciReset() - Reset PCI interface
21425 + *
21426 + * Description:
21427 + *     o Read PCI configuration.
21428 + *     o Change power state to 3.
21429 + *     o Change power state to 0.
21430 + *     o Restore PCI configuration.
21431 + *
21432 + * Returns:
21433 + *     0:      Success.
21434 + *     1:      Power state could not be changed to 3.
21435 + */
21436 +static int SkGePciReset(
21437 +SK_AC  *pAC,           /* Adapter Context */
21438 +SK_IOC IoC)            /* I/O Context */
21439 +{
21440 +       int             i;
21441 +       SK_U16  PmCtlSts;
21442 +       SK_U32  Bp1;
21443 +       SK_U32  Bp2;
21444 +       SK_U16  PciCmd;
21445 +       SK_U8   Cls;
21446 +       SK_U8   Lat;
21447 +       SK_U8   ConfigSpace[PCI_CFG_SIZE];
21448 +
21449 +       /*
21450 +        * Note: Switching to D3 state is like a software reset.
21451 +        *               Switching from D3 to D0 is a hardware reset.
21452 +        *               We have to save and restore the configuration space.
21453 +        */
21454 +       for (i = 0; i < PCI_CFG_SIZE; i++) {
21455 +               SkPciReadCfgDWord(pAC, i*4, &ConfigSpace[i]);
21456 +       }
21457 +
21458 +       /* We know the RAM Interface Arbiter is enabled. */
21459 +       SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D3);
21460 +
21461 +       SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);
21462 +
21463 +       if ((PmCtlSts & PCI_PM_STATE_MSK) != PCI_PM_STATE_D3) {
21464 +               return(1);
21465 +       }
21466 +
21467 +       /* Return to D0 state. */
21468 +       SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D0);
21469 +
21470 +       /* Check for D0 state. */
21471 +       SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);
21472 +
21473 +       if ((PmCtlSts & PCI_PM_STATE_MSK) != PCI_PM_STATE_D0) {
21474 +               return(1);
21475 +       }
21476 +
21477 +       /* Check PCI Config Registers. */
21478 +       SkPciReadCfgWord(pAC, PCI_COMMAND, &PciCmd);
21479 +       SkPciReadCfgByte(pAC, PCI_CACHE_LSZ, &Cls);
21480 +       SkPciReadCfgDWord(pAC, PCI_BASE_1ST, &Bp1);
21481 +
21482 +       /*
21483 +        * Compute the location in PCI config space of BAR2
21484 +        * relativ to the location of BAR1
21485 +        */
21486 +       if ((Bp1 & PCI_MEM_TYP_MSK) == PCI_MEM64BIT) {
21487 +               /* BAR1 is 64 bits wide */
21488 +               i = 8;
21489 +       }
21490 +       else {
21491 +               i = 4;
21492 +       }
21493 +
21494 +       SkPciReadCfgDWord(pAC, PCI_BASE_1ST + i, &Bp2);
21495 +       SkPciReadCfgByte(pAC, PCI_LAT_TIM, &Lat);
21496 +
21497 +       if (PciCmd != 0 || Cls != 0 || (Bp1 & 0xfffffff0L) != 0 || Bp2 != 1 ||
21498 +               Lat != 0) {
21499 +               return(1);
21500 +       }
21501 +
21502 +       /* Restore PCI Config Space. */
21503 +       for (i = 0; i < PCI_CFG_SIZE; i++) {
21504 +               SkPciWriteCfgDWord(pAC, i*4, ConfigSpace[i]);
21505 +       }
21506 +
21507 +       return(0);
21508 +}      /* SkGePciReset */
21509 +#endif /* SK_PCI_RESET */
21510 +
21511 +
21512 +#ifndef SK_SLIM
21513 +/******************************************************************************
21514 + *
21515 + *     SkGeSetUpSupFeatures() - Collect Feature List for HW_FEATURE Macro
21516 + *
21517 + * Description:
21518 + *     This function collects the available features and required
21519 + *     deviation services of the Adapter and provides these
21520 + *     information in the GIHwF struct. This information is used as
21521 + *     default value and may be overritten by the driver using the
21522 + *     SET_HW_FEATURE_MASK() macro in its Init0 phase.
21523 + *
21524 + * Notice:
21525 + *     Using the On and Off mask: Never switch on the same bit in both
21526 + *     masks simultaneously. However, if doing the Off mask will win.
21527 + *
21528 + * Returns:
21529 + *     nothing
21530 + */
21531 +static void SkGeSetUpSupFeatures(
21532 +SK_AC  *pAC,           /* Adapter Context */
21533 +SK_IOC IoC)            /* I/O Context */
21534 +{
21535 +       int i;
21536 +       SK_U16 Word;
21537 +
21538 +       switch (pAC->GIni.GIChipId) {
21539 +       case CHIP_ID_YUKON_EC:
21540 +               if (pAC->GIni.GIChipRev == CHIP_REV_YU_EC_A1) {
21541 +                       /* A0/A1 */
21542 +                       pAC->GIni.HwF.Features[HW_DEV_LIST] =
21543 +                               HWF_WA_DEV_42  | HWF_WA_DEV_46 | HWF_WA_DEV_43_418 |
21544 +                               HWF_WA_DEV_420 | HWF_WA_DEV_423 |
21545 +                               HWF_WA_DEV_424 | HWF_WA_DEV_425 | HWF_WA_DEV_427 |
21546 +                               HWF_WA_DEV_428 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
21547 +                               HWF_WA_DEV_4152| HWF_WA_DEV_4167;
21548 +               }
21549 +               else {
21550 +                       /* A2/A3 */
21551 +                       pAC->GIni.HwF.Features[HW_DEV_LIST] =
21552 +                               HWF_WA_DEV_424 | HWF_WA_DEV_425 | HWF_WA_DEV_427 |
21553 +                               HWF_WA_DEV_428 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
21554 +                               HWF_WA_DEV_4152| HWF_WA_DEV_4167;
21555 +               }
21556 +               break;
21557 +       case CHIP_ID_YUKON_FE:
21558 +               pAC->GIni.HwF.Features[HW_DEV_LIST] =
21559 +                       HWF_WA_DEV_427 | HWF_WA_DEV_4109 |
21560 +                       HWF_WA_DEV_4152| HWF_WA_DEV_4167;
21561 +               break;
21562 +       case CHIP_ID_YUKON_XL:
21563 +               switch (pAC->GIni.GIChipRev) {
21564 +               case CHIP_REV_YU_XL_A0:         /* still needed for Diag */
21565 +                       pAC->GIni.HwF.Features[HW_DEV_LIST] =
21566 +                               HWF_WA_DEV_427 | HWF_WA_DEV_463 | HWF_WA_DEV_472 |
21567 +                               HWF_WA_DEV_479 | HWF_WA_DEV_483 | HWF_WA_DEV_4115 |
21568 +                               HWF_WA_DEV_4152| HWF_WA_DEV_4167;
21569 +                       break;
21570 +
21571 +               case CHIP_REV_YU_XL_A1:
21572 +                       pAC->GIni.HwF.Features[HW_DEV_LIST] =
21573 +                               HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
21574 +                               HWF_WA_DEV_4115| HWF_WA_DEV_4152| HWF_WA_DEV_4167;
21575 +                       break;
21576 +
21577 +               case CHIP_REV_YU_XL_A2:
21578 +                       pAC->GIni.HwF.Features[HW_DEV_LIST] =
21579 +                               HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
21580 +                               HWF_WA_DEV_4115 | HWF_WA_DEV_4167;
21581 +                       break;
21582 +
21583 +               case CHIP_REV_YU_XL_A3:
21584 +                       pAC->GIni.HwF.Features[HW_DEV_LIST] =
21585 +                               HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
21586 +                               HWF_WA_DEV_4115;
21587 +                       break;
21588 +               }
21589 +               break;
21590 +       case CHIP_ID_YUKON_EC_U:
21591 +               if (pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A0) {
21592 +                       pAC->GIni.HwF.Features[HW_DEV_LIST] =
21593 +                               HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109;
21594 +               }
21595 +               else if (pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A1) {
21596 +                       pAC->GIni.HwF.Features[HW_DEV_LIST] =
21597 +                               HWF_WA_DEV_427 | HWF_WA_DEV_4109 | HWF_WA_DEV_4185;
21598 +
21599 +                       /* check for Rev. A1 */
21600 +                       SK_IN16(IoC, Q_ADDR(Q_XA1, Q_WM), &Word);
21601 +
21602 +                       if (Word == 0) {
21603 +                               pAC->GIni.HwF.Features[HW_DEV_LIST] |=
21604 +                                       HWF_WA_DEV_4185CS | HWF_WA_DEV_4200;
21605 +                       }
21606 +               }
21607 +               break;
21608 +       }
21609 +
21610 +       for (i = 0; i < 4; i++) {
21611 +               pAC->GIni.HwF.Features[i] =
21612 +                       (pAC->GIni.HwF.Features[i] | pAC->GIni.HwF.OnMask[i]) &
21613 +                               ~pAC->GIni.HwF.OffMask[i];
21614 +       }
21615 +}      /* SkGeSetUpSupFeatures */
21616 +#endif /* !SK_SLIM */
21617 +
21618
21619  /******************************************************************************
21620   *
21621 @@ -1404,76 +2068,253 @@
21622   *     6:      HW self test failed
21623   */
21624  static int SkGeInit1(
21625 -SK_AC  *pAC,           /* adapter context */
21626 -SK_IOC IoC)            /* IO context */
21627 +SK_AC  *pAC,           /* Adapter Context */
21628 +SK_IOC IoC)            /* I/O Context */
21629  {
21630         SK_U8   Byte;
21631         SK_U16  Word;
21632 -       SK_U16  CtrlStat;
21633 +       SK_U32  CtrlStat;
21634 +       SK_U32  VauxAvail;
21635         SK_U32  DWord;
21636 +       SK_U32  Our1;
21637 +       SK_U32  PowerDownBit;
21638 +       SK_BOOL FiberType;
21639 +       SK_GEPORT *pPrt;
21640         int     RetVal;
21641 -       int     i;
21642 +       int     i, j;
21643
21644         RetVal = 0;
21645
21646 -       /* save CLK_RUN bits (YUKON-Lite) */
21647 -       SK_IN16(IoC, B0_CTST, &CtrlStat);
21648 +       /* save CLK_RUN & ASF_ENABLE bits (YUKON-Lite, YUKON-EC) */
21649 +       SK_IN32(IoC, B0_CTST, &CtrlStat);
21650
21651 -       /* do the SW-reset */
21652 -       SK_OUT8(IoC, B0_CTST, CS_RST_SET);
21653 +#ifdef SK_PCI_RESET
21654 +       (void)SkGePciReset(pAC, IoC);
21655 +#endif /* SK_PCI_RESET */
21656
21657         /* release the SW-reset */
21658 +       /* Important: SW-reset has to be cleared here, to ensure
21659 +        * the CHIP_ID can be read IO-mapped based, too -
21660 +        * remember the RAP register can only be written if
21661 +        * SW-reset is cleared.
21662 +        */
21663         SK_OUT8(IoC, B0_CTST, CS_RST_CLR);
21664
21665 +       /* read Chip Identification Number */
21666 +       SK_IN8(IoC, B2_CHIP_ID, &Byte);
21667 +       pAC->GIni.GIChipId = Byte;
21668 +
21669 +       pAC->GIni.GIAsfEnabled = SK_FALSE;
21670 +
21671 +       /* ASF support only for Yukon-2 */
21672 +       if ((pAC->GIni.GIChipId >= CHIP_ID_YUKON_XL) &&
21673 +               (pAC->GIni.GIChipId <= CHIP_ID_YUKON_EC)) {
21674 +#ifdef SK_ASF
21675 +               if ((CtrlStat & Y2_ASF_ENABLE) != 0) {
21676 +                       /* do the SW-reset only if ASF is not enabled */
21677 +                       pAC->GIni.GIAsfEnabled = SK_TRUE;
21678 +               }
21679 +#else /* !SK_ASF */
21680 +
21681 +               SK_IN8(IoC, B28_Y2_ASF_STAT_CMD, &Byte);
21682 +
21683 +               pAC->GIni.GIAsfRunning = Byte & Y2_ASF_RUNNING;
21684 +
21685 +               /* put ASF system in reset state */
21686 +               SK_OUT8(IoC, B28_Y2_ASF_STAT_CMD, (SK_U8)Y2_ASF_RESET);
21687 +
21688 +               /* disable ASF Unit */
21689 +               SK_OUT16(IoC, B0_CTST, Y2_ASF_DISABLE);
21690 +#endif /* !SK_ASF */
21691 +       }
21692 +
21693 +       if (!pAC->GIni.GIAsfEnabled) {
21694 +               /* Yukon-2: required for Diag and Power Management */
21695 +               /* set the SW-reset */
21696 +               SK_OUT8(IoC, B0_CTST, CS_RST_SET);
21697 +
21698 +               /* release the SW-reset */
21699 +               SK_OUT8(IoC, B0_CTST, CS_RST_CLR);
21700 +       }
21701 +
21702 +       /* enable Config Write */
21703 +       SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
21704 +
21705         /* reset all error bits in the PCI STATUS register */
21706         /*
21707          * Note: PCI Cfg cycles cannot be used, because they are not
21708          *               available on some platforms after 'boot time'.
21709          */
21710 -       SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);
21711 -
21712 -       SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
21713 -       SK_OUT16(IoC, PCI_C(PCI_STATUS), (SK_U16)(Word | PCI_ERRBITS));
21714 -       SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
21715 +       SK_IN16(IoC, PCI_C(pAC, PCI_STATUS), &Word);
21716 +
21717 +       SK_OUT16(IoC, PCI_C(pAC, PCI_STATUS), Word | (SK_U16)PCI_ERRBITS);
21718
21719         /* release Master Reset */
21720         SK_OUT8(IoC, B0_CTST, CS_MRST_CLR);
21721
21722  #ifdef CLK_RUN
21723         CtrlStat |= CS_CLK_RUN_ENA;
21724 -#endif /* CLK_RUN */
21725
21726         /* restore CLK_RUN bits */
21727         SK_OUT16(IoC, B0_CTST, (SK_U16)(CtrlStat &
21728                 (CS_CLK_RUN_HOT | CS_CLK_RUN_RST | CS_CLK_RUN_ENA)));
21729 +#endif /* CLK_RUN */
21730 +
21731 +       if ((pAC->GIni.GIChipId >= CHIP_ID_YUKON_XL) &&
21732 +               (pAC->GIni.GIChipId <= CHIP_ID_YUKON_FE)) {
21733 +
21734 +               pAC->GIni.GIYukon2 = SK_TRUE;
21735 +               pAC->GIni.GIValIrqMask = Y2_IS_ALL_MSK;
21736 +               pAC->GIni.GIValHwIrqMask = Y2_HWE_ALL_MSK;
21737 +
21738 +               VauxAvail = Y2_VAUX_AVAIL;
21739 +
21740 +               SK_IN32(IoC, PCI_C(pAC, PCI_OUR_STATUS), &DWord);
21741 +
21742 +               if ((DWord & PCI_OS_PCI_X) != 0) {
21743 +#ifndef SK_SLIM
21744 +                       /* this is a PCI / PCI-X bus */
21745 +                       if ((DWord & PCI_OS_PCIX) != 0) {
21746 +                               /* this is a PCI-X bus */
21747 +                               pAC->GIni.GIPciBus = SK_PCIX_BUS;
21748 +
21749 +                               /* PCI-X is always 64-bit wide */
21750 +                               pAC->GIni.GIPciSlot64 = SK_TRUE;
21751 +
21752 +                               pAC->GIni.GIPciMode = (SK_U8)(PCI_OS_SPEED(DWord));
21753 +                       }
21754 +                       else {
21755 +                               /* this is a conventional PCI bus */
21756 +                               pAC->GIni.GIPciBus = SK_PCI_BUS;
21757 +
21758 +                               SK_IN16(IoC, PCI_C(pAC, PCI_OUR_REG_2), &Word);
21759 +
21760 +                               /* check if 64-bit width is used */
21761 +                               pAC->GIni.GIPciSlot64 = (SK_BOOL)
21762 +                                       (((DWord & PCI_OS_PCI64B) != 0) &&
21763 +                                       ((Word & PCI_USEDATA64) != 0));
21764 +
21765 +                               /* check if 66 MHz PCI Clock is active */
21766 +                               pAC->GIni.GIPciClock66 = (SK_BOOL)((DWord & PCI_OS_PCI66M) != 0);
21767 +                       }
21768 +#endif /* !SK_SLIM */
21769 +               }
21770 +               else {
21771 +                       /* this is a PEX bus */
21772 +                       pAC->GIni.GIPciBus = SK_PEX_BUS;
21773 +
21774 +                       /* clear any PEX errors */
21775 +                       SK_OUT32(IoC, PCI_C(pAC, PEX_UNC_ERR_STAT), 0xffffffffUL);
21776 +
21777 +                       SK_IN32(IoC, PCI_C(pAC, PEX_UNC_ERR_STAT), &DWord);
21778 +
21779 +                       if ((DWord & PEX_RX_OV) != 0) {
21780 +                               /* Dev #4.205 occured */
21781 +                               pAC->GIni.GIValHwIrqMask &= ~Y2_IS_PCI_EXP;
21782 +                               pAC->GIni.GIValIrqMask &= ~Y2_IS_HW_ERR;
21783 +                       }
21784 +
21785 +                       SK_IN16(IoC, PCI_C(pAC, PEX_LNK_STAT), &Word);
21786 +
21787 +                       pAC->GIni.GIPexWidth = (SK_U8)((Word & PEX_LS_LINK_WI_MSK) >> 4);
21788 +               }
21789 +               /*
21790 +                * Yukon-2 chips family has a different way of providing
21791 +                * the number of MACs available
21792 +                */
21793 +               pAC->GIni.GIMacsFound = 1;
21794 +
21795 +               /* get HW Resources */
21796 +               SK_IN8(IoC, B2_Y2_HW_RES, &Byte);
21797 +
21798 +               if (CHIP_ID_YUKON_2(pAC)) {
21799 +                       /*
21800 +                        * OEM config value is overwritten and should not
21801 +                        * be used for Yukon-2
21802 +                        */
21803 +                       pAC->GIni.GILedBlinkCtrl |= SK_ACT_LED_BLINK;
21804 +
21805 +#ifndef SK_SLIM
21806 +                       if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) {
21807 +                               /* LED Configuration is stored in GPIO */
21808 +                               SK_IN8(IoC, B2_GP_IO, &Byte);
21809 +
21810 +                               if (CFG_LED_MODE(Byte) == CFG_LED_LINK_MUX_P60) {
21811 +
21812 +                                       pAC->GIni.GILedBlinkCtrl |= SK_LED_LINK_MUX_P60;
21813 +                               }
21814 +                       }
21815 +#endif /* !SK_SLIM */
21816 +
21817 +                       if (CFG_LED_MODE(Byte) == CFG_LED_DUAL_ACT_LNK) {
21818 +
21819 +                               pAC->GIni.GILedBlinkCtrl |= SK_DUAL_LED_ACT_LNK;
21820 +                       }
21821 +               }
21822 +
21823 +               /* save HW Resources / Application Information */
21824 +               pAC->GIni.GIHwResInfo = Byte;
21825 +
21826 +               if ((Byte & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
21827 +
21828 +                       SK_IN8(IoC, B2_Y2_CLK_GATE, &Byte);
21829 +
21830 +                       if (!(Byte & Y2_STATUS_LNK2_INAC)) {
21831 +                               /* Link 2 activ */
21832 +                               pAC->GIni.GIMacsFound++;
21833 +                       }
21834 +               }
21835 +
21836 +#ifdef VCPU
21837 +               if (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL) {
21838 +                       /* temporary WA for reported number of links */
21839 +                       pAC->GIni.GIMacsFound = 2;
21840 +               }
21841 +#endif /* VCPU */
21842 +
21843 +               /* read Chip Revision */
21844 +               SK_IN8(IoC, B2_MAC_CFG, &Byte);
21845 +
21846 +               pAC->GIni.GIChipCap = Byte & 0x0f;
21847 +       }
21848 +       else {
21849 +               pAC->GIni.GIYukon2 = SK_FALSE;
21850 +               pAC->GIni.GIValIrqMask = IS_ALL_MSK;
21851 +               pAC->GIni.GIValHwIrqMask = 0;   /* not activated */
21852 +
21853 +               VauxAvail = CS_VAUX_AVAIL;
21854 +
21855 +               /* read number of MACs and Chip Revision */
21856 +               SK_IN8(IoC, B2_MAC_CFG, &Byte);
21857 +
21858 +               pAC->GIni.GIMacsFound = (Byte & CFG_SNG_MAC) ? 1 : 2;
21859 +       }
21860
21861 -       /* read Chip Identification Number */
21862 -       SK_IN8(IoC, B2_CHIP_ID, &Byte);
21863 -       pAC->GIni.GIChipId = Byte;
21864 -
21865 -       /* read number of MACs */
21866 -       SK_IN8(IoC, B2_MAC_CFG, &Byte);
21867 -       pAC->GIni.GIMacsFound = (Byte & CFG_SNG_MAC) ? 1 : 2;
21868 -
21869         /* get Chip Revision Number */
21870         pAC->GIni.GIChipRev = (SK_U8)((Byte & CFG_CHIP_R_MSK) >> 4);
21871
21872 -       /* get diff. PCI parameters */
21873 -       SK_IN16(IoC, B0_CTST, &CtrlStat);
21874 -
21875 +#ifndef SK_DIAG
21876 +       if (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL &&
21877 +               pAC->GIni.GIChipRev == CHIP_REV_YU_XL_A0) {
21878 +               /* Yukon-2 Chip Rev. A0 */
21879 +               return(6);
21880 +       }
21881 +#endif /* !SK_DIAG */
21882 +
21883         /* read the adapters RAM size */
21884         SK_IN8(IoC, B2_E_0, &Byte);
21885 -
21886 +
21887         pAC->GIni.GIGenesis = SK_FALSE;
21888         pAC->GIni.GIYukon = SK_FALSE;
21889         pAC->GIni.GIYukonLite = SK_FALSE;
21890 +       pAC->GIni.GIVauxAvail = SK_FALSE;
21891
21892  #ifdef GENESIS
21893         if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
21894
21895                 pAC->GIni.GIGenesis = SK_TRUE;
21896
21897 -               if (Byte == (SK_U8)3) {
21898 +               if (Byte == (SK_U8)3) {
21899                         /* special case: 4 x 64k x 36, offset = 0x80000 */
21900                         pAC->GIni.GIRamSize = 1024;
21901                         pAC->GIni.GIRamOffs = (SK_U32)512 * 1024;
21902 @@ -1482,57 +2323,83 @@
21903                         pAC->GIni.GIRamSize = (int)Byte * 512;
21904                         pAC->GIni.GIRamOffs = 0;
21905                 }
21906 -               /* all GE adapters work with 53.125 MHz host clock */
21907 +               /* all GENESIS adapters work with 53.125 MHz host clock */
21908                 pAC->GIni.GIHstClkFact = SK_FACT_53;
21909 -
21910 +
21911                 /* set Descr. Poll Timer Init Value to 250 ms */
21912                 pAC->GIni.GIPollTimerVal =
21913                         SK_DPOLL_DEF * (SK_U32)pAC->GIni.GIHstClkFact / 100;
21914         }
21915  #endif /* GENESIS */
21916 -
21917 +
21918  #ifdef YUKON
21919         if (pAC->GIni.GIChipId != CHIP_ID_GENESIS) {
21920 -
21921 +
21922                 pAC->GIni.GIYukon = SK_TRUE;
21923 -
21924 +
21925                 pAC->GIni.GIRamSize = (Byte == (SK_U8)0) ? 128 : (int)Byte * 4;
21926 -
21927 +
21928 +#ifndef SK_SLIM
21929                 pAC->GIni.GIRamOffs = 0;
21930 -
21931 -               /* WA for chip Rev. A */
21932 +
21933 +               /* WA for Yukon chip Rev. A */
21934                 pAC->GIni.GIWolOffs = (pAC->GIni.GIChipId == CHIP_ID_YUKON &&
21935                         pAC->GIni.GIChipRev == 0) ? WOL_REG_OFFS : 0;
21936 -
21937 +
21938                 /* get PM Capabilities of PCI config space */
21939 -               SK_IN16(IoC, PCI_C(PCI_PM_CAP_REG), &Word);
21940 +               SK_IN16(IoC, PCI_C(pAC, PCI_PM_CAP_REG), &Word);
21941
21942                 /* check if VAUX is available */
21943 -               if (((CtrlStat & CS_VAUX_AVAIL) != 0) &&
21944 +               if (((CtrlStat & VauxAvail) != 0) &&
21945                         /* check also if PME from D3cold is set */
21946                         ((Word & PCI_PME_D3C_SUP) != 0)) {
21947                         /* set entry in GE init struct */
21948                         pAC->GIni.GIVauxAvail = SK_TRUE;
21949                 }
21950 -
21951 -               if (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) {
21952 -                       /* this is Rev. A1 */
21953 -                       pAC->GIni.GIYukonLite = SK_TRUE;
21954 -               }
21955 -               else {
21956 -                       /* save Flash-Address Register */
21957 -                       SK_IN32(IoC, B2_FAR, &DWord);
21958 +#endif /* !SK_SLIM */
21959
21960 -                       /* test Flash-Address Register */
21961 -                       SK_OUT8(IoC, B2_FAR + 3, 0xff);
21962 -                       SK_IN8(IoC, B2_FAR + 3, &Byte);
21963 +               if (!CHIP_ID_YUKON_2(pAC)) {
21964
21965 -                       if (Byte != 0) {
21966 -                               /* this is Rev. A0 */
21967 +                       if (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) {
21968 +                               /* this is Rev. A1 */
21969                                 pAC->GIni.GIYukonLite = SK_TRUE;
21970 +                       }
21971 +#ifndef SK_SLIM
21972 +                       else {
21973 +                               /* save Flash-Address Register */
21974 +                               SK_IN32(IoC, B2_FAR, &DWord);
21975 +
21976 +                               /* test Flash-Address Register */
21977 +                               SK_OUT8(IoC, B2_FAR + 3, 0xff);
21978 +                               SK_IN8(IoC, B2_FAR + 3, &Byte);
21979 +
21980 +                               if (Byte != 0) {
21981 +                                       /* this is Rev. A0 */
21982 +                                       pAC->GIni.GIYukonLite = SK_TRUE;
21983 +
21984 +                                       /* restore Flash-Address Register */
21985 +                                       SK_OUT32(IoC, B2_FAR, DWord);
21986 +                               }
21987 +                       }
21988 +#endif /* !SK_SLIM */
21989 +               }
21990 +               else {
21991 +                       /* Check for CLS = 0 (dev. #4.55) */
21992 +                       if (pAC->GIni.GIPciBus != SK_PEX_BUS) {
21993 +                               /* PCI and PCI-X */
21994 +                               SK_IN8(IoC, PCI_C(pAC, PCI_CACHE_LSZ), &Byte);
21995 +
21996 +                               if (Byte == 0) {
21997 +                                       /* set CLS to 2 if configured to 0 */
21998 +                                       SK_OUT8(IoC, PCI_C(pAC, PCI_CACHE_LSZ), 2);
21999 +                               }
22000
22001 -                               /* restore Flash-Address Register */
22002 -                               SK_OUT32(IoC, B2_FAR, DWord);
22003 +                               if (pAC->GIni.GIPciBus == SK_PCIX_BUS) {
22004 +                                       /* set Cache Line Size opt. */
22005 +                                       SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_1), &DWord);
22006 +                                       DWord |= PCI_CLS_OPT;
22007 +                                       SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_1), DWord);
22008 +                               }
22009                         }
22010                 }
22011
22012 @@ -1540,138 +2407,282 @@
22013                 SK_OUT8(IoC, B0_POWER_CTRL, (SK_U8)(PC_VAUX_ENA | PC_VCC_ENA |
22014                         PC_VAUX_OFF | PC_VCC_ON));
22015
22016 -               /* read the Interrupt source */
22017 -               SK_IN32(IoC, B0_ISRC, &DWord);
22018 -
22019 -               if ((DWord & IS_HW_ERR) != 0) {
22020 -                       /* read the HW Error Interrupt source */
22021 -                       SK_IN32(IoC, B0_HWE_ISRC, &DWord);
22022 -
22023 -                       if ((DWord & IS_IRQ_SENSOR) != 0) {
22024 -                               /* disable HW Error IRQ */
22025 -                               pAC->GIni.GIValIrqMask &= ~IS_HW_ERR;
22026 +               Byte = 0;
22027 +
22028 +               if (CHIP_ID_YUKON_2(pAC)) {
22029 +                       switch (pAC->GIni.GIChipId) {
22030 +                       /* PEX adapters work with different host clock */
22031 +                       case CHIP_ID_YUKON_EC:
22032 +                       case CHIP_ID_YUKON_EC_U:
22033 +                               /* Yukon-EC works with 125 MHz host clock */
22034 +                               pAC->GIni.GIHstClkFact = SK_FACT_125;
22035 +                               break;
22036 +                       case CHIP_ID_YUKON_FE:
22037 +                               /* Yukon-FE works with 100 MHz host clock */
22038 +                               pAC->GIni.GIHstClkFact = SK_FACT_100;
22039 +                               break;
22040 +                       case CHIP_ID_YUKON_XL:
22041 +                               /* all Yukon-2 adapters work with 156 MHz host clock */
22042 +                               pAC->GIni.GIHstClkFact = 2 * SK_FACT_78;
22043 +
22044 +                               if (pAC->GIni.GIChipRev > CHIP_REV_YU_XL_A1) {
22045 +                                       /* enable bits are inverted */
22046 +                                       Byte = (SK_U8)(Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
22047 +                                               Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
22048 +                                               Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
22049 +                               }
22050 +                               break;
22051 +                       default:
22052 +                               SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E006,
22053 +                                       SKERR_HWI_E006MSG);
22054                         }
22055 +
22056 +                       pAC->GIni.GIPollTimerVal =
22057 +                               SK_DPOLL_DEF_Y2 * (SK_U32)pAC->GIni.GIHstClkFact / 100;
22058 +
22059 +                       /* set power down bit */
22060 +                       PowerDownBit = PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD;
22061 +
22062 +                       /* disable Core Clock Division, set Clock Select to 0 (Yukon-2) */
22063 +                       SK_OUT32(IoC, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
22064 +
22065 +                       /* enable MAC/PHY, PCI and Core Clock for both Links */
22066 +                       SK_OUT8(IoC, B2_Y2_CLK_GATE, Byte);
22067                 }
22068 -
22069 -               for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
22070 -                       /* set GMAC Link Control reset */
22071 -                       SK_OUT16(IoC, MR_ADDR(i, GMAC_LINK_CTRL), GMLC_RST_SET);
22072 +               else {
22073 +                       /* YUKON adapters work with 78 MHz host clock */
22074 +                       pAC->GIni.GIHstClkFact = SK_FACT_78;
22075
22076 -                       /* clear GMAC Link Control reset */
22077 -                       SK_OUT16(IoC, MR_ADDR(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
22078 +                       pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX;        /* 215 ms */
22079 +
22080 +                       /* read the Interrupt source */
22081 +                       SK_IN32(IoC, B0_ISRC, &DWord);
22082 +
22083 +                       if ((DWord & IS_HW_ERR) != 0) {
22084 +                               /* read the HW Error Interrupt source */
22085 +                               SK_IN32(IoC, B0_HWE_ISRC, &DWord);
22086 +
22087 +                               if ((DWord & IS_IRQ_SENSOR) != 0) {
22088 +                                       /* disable HW Error IRQ */
22089 +                                       pAC->GIni.GIValIrqMask &= ~IS_HW_ERR;
22090 +                               }
22091 +                       }
22092 +                       /* set power down bit */
22093 +                       PowerDownBit = PCI_PHY_COMA;
22094 +               }
22095 +
22096 +               SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_1), &Our1);
22097 +
22098 +               Our1 &= ~PowerDownBit;
22099 +
22100 +               if (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL &&
22101 +                       pAC->GIni.GIChipRev > CHIP_REV_YU_XL_A1) {
22102 +                       /* deassert Low Power for 1st PHY */
22103 +                       Our1 |= PCI_Y2_PHY1_COMA;
22104 +
22105 +                       if (pAC->GIni.GIMacsFound > 1) {
22106 +                               /* deassert Low Power for 2nd PHY */
22107 +                               Our1 |= PCI_Y2_PHY2_COMA;
22108 +                       }
22109 +               }
22110 +               else if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) {
22111 +                       /* enable HW WOL */
22112 +                       SK_OUT16(IoC, B0_CTST, (SK_U16)Y2_HW_WOL_ON);
22113 +
22114 +                       /* enable all clocks */
22115 +                       SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_3), 0);
22116 +
22117 +                       SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_4), &DWord);
22118 +
22119 +                       DWord &= P_ASPM_CONTROL_MSK;
22120 +                       /* set all bits to 0 except bits 15..12 */
22121 +                       SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_4), DWord);
22122 +
22123 +                       /* set to default value */
22124 +                       SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_5), 0);
22125 +               }
22126 +
22127 +               /* release PHY from PowerDown/COMA Mode */
22128 +               SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_1), Our1);
22129 +
22130 +               if (!pAC->GIni.GIAsfEnabled) {
22131 +
22132 +                       for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
22133 +                               /* set Link Control reset */
22134 +                               SK_OUT8(IoC, MR_ADDR(i, GMAC_LINK_CTRL), (SK_U8)GMLC_RST_SET);
22135 +
22136 +                               /* clear Link Control reset */
22137 +                               SK_OUT8(IoC, MR_ADDR(i, GMAC_LINK_CTRL), (SK_U8)GMLC_RST_CLR);
22138 +                       }
22139                 }
22140 -               /* all YU chips work with 78.125 MHz host clock */
22141 -               pAC->GIni.GIHstClkFact = SK_FACT_78;
22142 -
22143 -               pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX;        /* 215 ms */
22144         }
22145  #endif /* YUKON */
22146
22147 -       /* check if 64-bit PCI Slot is present */
22148 -       pAC->GIni.GIPciSlot64 = (SK_BOOL)((CtrlStat & CS_BUS_SLOT_SZ) != 0);
22149 -
22150 -       /* check if 66 MHz PCI Clock is active */
22151 -       pAC->GIni.GIPciClock66 = (SK_BOOL)((CtrlStat & CS_BUS_CLOCK) != 0);
22152 +       SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
22153 +
22154 +#ifndef SK_SLIM
22155 +       if (!CHIP_ID_YUKON_2(pAC)) {
22156 +               /* this is a conventional PCI bus */
22157 +               pAC->GIni.GIPciBus = SK_PCI_BUS;
22158 +
22159 +               /* check if 64-bit PCI Slot is present */
22160 +               pAC->GIni.GIPciSlot64 = (SK_BOOL)((CtrlStat & CS_BUS_SLOT_SZ) != 0);
22161 +
22162 +               /* check if 66 MHz PCI Clock is active */
22163 +               pAC->GIni.GIPciClock66 = (SK_BOOL)((CtrlStat & CS_BUS_CLOCK) != 0);
22164 +       }
22165
22166         /* read PCI HW Revision Id. */
22167 -       SK_IN8(IoC, PCI_C(PCI_REV_ID), &Byte);
22168 +       SK_IN8(IoC, PCI_C(pAC, PCI_REV_ID), &Byte);
22169         pAC->GIni.GIPciHwRev = Byte;
22170
22171 +       /* read connector type */
22172 +       SK_IN8(IoC, B2_CONN_TYP, &pAC->GIni.GIConTyp);
22173 +#endif /* !SK_SLIM */
22174 +
22175         /* read the PMD type */
22176         SK_IN8(IoC, B2_PMD_TYP, &Byte);
22177 -       pAC->GIni.GICopperType = (SK_U8)(Byte == 'T');
22178
22179 -       /* read the PHY type */
22180 +       pAC->GIni.GIPmdTyp = Byte;
22181 +
22182 +       FiberType = (Byte == 'L' || Byte == 'S' || Byte == 'P');
22183 +
22184 +       pAC->GIni.GICopperType = (SK_BOOL)(Byte == 'T' || Byte == '1' ||
22185 +               (pAC->GIni.GIYukon2 && !FiberType));
22186 +
22187 +       /* read the PHY type (Yukon and Genesis) */
22188         SK_IN8(IoC, B2_E_1, &Byte);
22189
22190         Byte &= 0x0f;   /* the PHY type is stored in the lower nibble */
22191         for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
22192 -
22193 +
22194 +               pPrt = &pAC->GIni.GP[i];
22195 +
22196 +               /* get the MAC addresses */
22197 +               for (j = 0; j < 3; j++) {
22198 +                       SK_IN16(IoC, B2_MAC_1 + i * 8 + j * 2, &pPrt->PMacAddr[j]);
22199 +               }
22200 +
22201  #ifdef GENESIS
22202                 if (pAC->GIni.GIGenesis) {
22203                         switch (Byte) {
22204                         case SK_PHY_XMAC:
22205 -                               pAC->GIni.GP[i].PhyAddr = PHY_ADDR_XMAC;
22206 +                               pPrt->PhyAddr = PHY_ADDR_XMAC;
22207                                 break;
22208                         case SK_PHY_BCOM:
22209 -                               pAC->GIni.GP[i].PhyAddr = PHY_ADDR_BCOM;
22210 -                               pAC->GIni.GP[i].PMSCap = (SK_U8)(SK_MS_CAP_AUTO |
22211 +                               pPrt->PhyAddr = PHY_ADDR_BCOM;
22212 +                               pPrt->PMSCap = (SK_U8)(SK_MS_CAP_AUTO |
22213                                         SK_MS_CAP_MASTER | SK_MS_CAP_SLAVE);
22214                                 break;
22215  #ifdef OTHER_PHY
22216                         case SK_PHY_LONE:
22217 -                               pAC->GIni.GP[i].PhyAddr = PHY_ADDR_LONE;
22218 +                               pPrt->PhyAddr = PHY_ADDR_LONE;
22219                                 break;
22220                         case SK_PHY_NAT:
22221 -                               pAC->GIni.GP[i].PhyAddr = PHY_ADDR_NAT;
22222 +                               pPrt->PhyAddr = PHY_ADDR_NAT;
22223                                 break;
22224  #endif /* OTHER_PHY */
22225                         default:
22226                                 /* ERROR: unexpected PHY type detected */
22227                                 RetVal = 5;
22228 -                               break;
22229                         }
22230                 }
22231  #endif /* GENESIS */
22232 -
22233 +
22234  #ifdef YUKON
22235                 if (pAC->GIni.GIYukon) {
22236 -
22237 -                       if (Byte < (SK_U8)SK_PHY_MARV_COPPER) {
22238 +
22239 +                       if (((Byte < (SK_U8)SK_PHY_MARV_COPPER) || pAC->GIni.GIYukon2) &&
22240 +                               !FiberType) {
22241                                 /* if this field is not initialized */
22242                                 Byte = (SK_U8)SK_PHY_MARV_COPPER;
22243 -
22244 +
22245                                 pAC->GIni.GICopperType = SK_TRUE;
22246                         }
22247 -
22248 -                       pAC->GIni.GP[i].PhyAddr = PHY_ADDR_MARV;
22249 -
22250 +
22251 +                       pPrt->PhyAddr = PHY_ADDR_MARV;
22252 +
22253                         if (pAC->GIni.GICopperType) {
22254
22255 -                               pAC->GIni.GP[i].PLinkSpeedCap = (SK_U8)(SK_LSPEED_CAP_AUTO |
22256 -                                       SK_LSPEED_CAP_10MBPS | SK_LSPEED_CAP_100MBPS |
22257 -                                       SK_LSPEED_CAP_1000MBPS);
22258 -
22259 -                               pAC->GIni.GP[i].PLinkSpeed = (SK_U8)SK_LSPEED_AUTO;
22260 -
22261 -                               pAC->GIni.GP[i].PMSCap = (SK_U8)(SK_MS_CAP_AUTO |
22262 +                               if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE ||
22263 +                                       (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC &&
22264 +                                       pAC->GIni.GIChipCap == 2)) {
22265 +
22266 +                                       pPrt->PLinkSpeedCap = (SK_U8)(SK_LSPEED_CAP_100MBPS |
22267 +                                               SK_LSPEED_CAP_10MBPS);
22268 +
22269 +                                       pAC->GIni.GIRamSize = 4;
22270 +                               }
22271 +                               else {
22272 +                                       pPrt->PLinkSpeedCap = (SK_U8)(SK_LSPEED_CAP_1000MBPS |
22273 +                                               SK_LSPEED_CAP_100MBPS | SK_LSPEED_CAP_10MBPS |
22274 +                                               SK_LSPEED_CAP_AUTO);
22275 +                               }
22276 +
22277 +                               pPrt->PLinkSpeed = (SK_U8)SK_LSPEED_AUTO;
22278 +
22279 +                               pPrt->PMSCap = (SK_U8)(SK_MS_CAP_AUTO |
22280                                         SK_MS_CAP_MASTER | SK_MS_CAP_SLAVE);
22281                         }
22282                         else {
22283                                 Byte = (SK_U8)SK_PHY_MARV_FIBER;
22284                         }
22285                 }
22286 +
22287 +               /* clear TWSI IRQ */
22288 +               SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
22289 +
22290  #endif /* YUKON */
22291 -
22292 -               pAC->GIni.GP[i].PhyType = (int)Byte;
22293 -
22294 +
22295 +               pPrt->PhyType = (int)Byte;
22296 +
22297                 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
22298 -                       ("PHY type: %d  PHY addr: %04x\n", Byte,
22299 -                       pAC->GIni.GP[i].PhyAddr));
22300 +                       ("PHY type: %d  PHY addr: %04x\n",
22301 +                       Byte, pPrt->PhyAddr));
22302         }
22303 -
22304 +
22305         /* get MAC Type & set function pointers dependent on */
22306  #ifdef GENESIS
22307         if (pAC->GIni.GIGenesis) {
22308 -
22309 +
22310                 pAC->GIni.GIMacType = SK_MAC_XMAC;
22311
22312                 pAC->GIni.GIFunc.pFnMacUpdateStats      = SkXmUpdateStats;
22313                 pAC->GIni.GIFunc.pFnMacStatistic        = SkXmMacStatistic;
22314                 pAC->GIni.GIFunc.pFnMacResetCounter     = SkXmResetCounter;
22315                 pAC->GIni.GIFunc.pFnMacOverflow         = SkXmOverflowStatus;
22316 +#ifdef SK_DIAG
22317 +               pAC->GIni.GIFunc.pFnMacPhyRead          = SkXmPhyRead;
22318 +               pAC->GIni.GIFunc.pFnMacPhyWrite         = SkXmPhyWrite;
22319 +#else  /* SK_DIAG */
22320 +               pAC->GIni.GIFunc.pSkGeSirqIsr           = SkGeYuSirqIsr;
22321 +#endif /* !SK_DIAG */
22322         }
22323  #endif /* GENESIS */
22324 -
22325 +
22326  #ifdef YUKON
22327         if (pAC->GIni.GIYukon) {
22328 -
22329 +
22330 +#ifndef SK_SLIM
22331                 pAC->GIni.GIMacType = SK_MAC_GMAC;
22332
22333                 pAC->GIni.GIFunc.pFnMacUpdateStats      = SkGmUpdateStats;
22334                 pAC->GIni.GIFunc.pFnMacStatistic        = SkGmMacStatistic;
22335                 pAC->GIni.GIFunc.pFnMacResetCounter     = SkGmResetCounter;
22336                 pAC->GIni.GIFunc.pFnMacOverflow         = SkGmOverflowStatus;
22337 +#endif /* !SK_SLIM */
22338 +
22339 +#ifdef SK_DIAG
22340 +               pAC->GIni.GIFunc.pFnMacPhyRead          = SkGmPhyRead;
22341 +               pAC->GIni.GIFunc.pFnMacPhyWrite         = SkGmPhyWrite;
22342 +#else  /* SK_DIAG */
22343 +               if (CHIP_ID_YUKON_2(pAC)) {
22344 +                       pAC->GIni.GIFunc.pSkGeSirqIsr   = SkYuk2SirqIsr;
22345 +               }
22346 +               else {
22347 +                       pAC->GIni.GIFunc.pSkGeSirqIsr   = SkGeYuSirqIsr;
22348 +               }
22349 +#endif /* !SK_DIAG */
22350
22351  #ifdef SPECIAL_HANDLING
22352                 if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {
22353 @@ -1684,7 +2695,13 @@
22354  #endif
22355         }
22356  #endif /* YUKON */
22357 -
22358 +
22359 +#ifndef SK_SLIM
22360 +
22361 +       SkGeSetUpSupFeatures(pAC, IoC);
22362 +
22363 +#endif /* !SK_SLIM */
22364 +
22365         return(RetVal);
22366  }      /* SkGeInit1 */
22367
22368 @@ -1705,9 +2722,15 @@
22369   *     nothing
22370   */
22371  static void SkGeInit2(
22372 -SK_AC  *pAC,           /* adapter context */
22373 -SK_IOC IoC)            /* IO context */
22374 +SK_AC  *pAC,           /* Adapter Context */
22375 +SK_IOC IoC)            /* I/O Context */
22376  {
22377 +#ifdef YUKON
22378 +       SK_U16  Word;
22379 +#if (!defined(SK_SLIM) && !defined(SK_DIAG))
22380 +       SK_EVPARA       Para;
22381 +#endif /* !SK_SLIM && !SK_DIAG */
22382 +#endif /* YUKON */
22383  #ifdef GENESIS
22384         SK_U32  DWord;
22385  #endif /* GENESIS */
22386 @@ -1720,7 +2743,9 @@
22387
22388                         SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E017, SKERR_HWI_E017MSG);
22389                 }
22390 +
22391                 SK_OUT32(IoC, B28_DPT_INI, pAC->GIni.GIPollTimerVal);
22392 +
22393                 SK_OUT8(IoC, B28_DPT_CTRL, DPT_START);
22394         }
22395
22396 @@ -1730,6 +2755,7 @@
22397                 DWord = SK_BLK_DUR * (SK_U32)pAC->GIni.GIHstClkFact / 100;
22398
22399                 SK_OUT32(IoC, B2_BSC_INI, DWord);
22400 +
22401                 SK_OUT8(IoC, B2_BSC_CTRL, BSC_START);
22402
22403                 /*
22404 @@ -1741,13 +2767,13 @@
22405                 SkGeInitPktArb(pAC, IoC);
22406         }
22407  #endif /* GENESIS */
22408 -
22409 -#ifdef YUKON
22410 +
22411 +#ifdef xSK_DIAG
22412         if (pAC->GIni.GIYukon) {
22413                 /* start Time Stamp Timer */
22414                 SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8)GMT_ST_START);
22415         }
22416 -#endif /* YUKON */
22417 +#endif /* SK_DIAG */
22418
22419         /* enable the Tx Arbiters */
22420         for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
22421 @@ -1757,8 +2783,62 @@
22422         /* enable the RAM Interface Arbiter */
22423         SkGeInitRamIface(pAC, IoC);
22424
22425 +#ifdef YUKON
22426 +       if (CHIP_ID_YUKON_2(pAC)) {
22427 +
22428 +               if (pAC->GIni.GIPciBus == SK_PEX_BUS) {
22429 +
22430 +                       SK_IN16(IoC, PCI_C(pAC, PEX_DEV_CTRL), &Word);
22431 +
22432 +                       /* change Max. Read Request Size to 2048 bytes */
22433 +                       Word &= ~PEX_DC_MAX_RRS_MSK;
22434 +                       Word |= PEX_DC_MAX_RD_RQ_SIZE(4);
22435 +
22436 +                       SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
22437 +
22438 +                       SK_OUT16(IoC, PCI_C(pAC, PEX_DEV_CTRL), Word);
22439 +
22440 +#ifdef REPLAY_TIMER
22441 +                       if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) {
22442 +                               /* PEX Ack Reply Timeout to 40 us */
22443 +                               SK_OUT16(IoC, PCI_C(pAC, PEX_ACK_RPLY_TOX1), 0x2710);
22444 +                       }
22445 +#endif
22446 +
22447 +                       SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
22448 +
22449 +#if (!defined(SK_SLIM) && !defined(SK_DIAG))
22450 +                       SK_IN16(IoC, PCI_C(pAC, PEX_LNK_CAP), &Word);
22451 +
22452 +                       Word = (Word & PEX_CAP_MAX_WI_MSK) >> 4;
22453 +
22454 +                       /* compare PEX Negotiated Link Width against max. capabil */
22455 +                       if (pAC->GIni.GIPexWidth != (SK_U8)Word) {
22456 +
22457 +                               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
22458 +                                       ("PEX negotiated Link width is: %d, exp.: %d\n",
22459 +                                        pAC->GIni.GIPexWidth, Word));
22460 +
22461 +#ifndef NDIS_MINIPORT_DRIVER
22462 +                               SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E026,
22463 +                                       SKERR_HWI_E026MSG);
22464 +#endif
22465 +                               Para.Para64 = 0;
22466 +                               SkEventQueue(pAC, SKGE_DRV, SK_DRV_PEX_LINK_WIDTH, Para);
22467 +                       }
22468 +#endif /* !SK_SLIM && !SK_DIAG */
22469 +               }
22470 +
22471 +               /*
22472 +                * Writing the HW Error Mask Reg. will not generate an IRQ
22473 +                * as long as the B0_IMSK is not set by the driver.
22474 +                */
22475 +               SK_OUT32(IoC, B0_HWE_IMSK, pAC->GIni.GIValHwIrqMask);
22476 +       }
22477 +#endif /* YUKON */
22478  }      /* SkGeInit2 */
22479
22480 +
22481  /******************************************************************************
22482   *
22483   *     SkGeInit() - Initialize the GE Adapter with the specified level.
22484 @@ -1780,7 +2860,7 @@
22485   *                             if Number of MACs > SK_MAX_MACS
22486   *
22487   *                     After returning from Level 0 the adapter
22488 - *                     may be accessed with IO operations.
22489 + *                     may be accessed with I/O operations.
22490   *
22491   *     Level   2:      start the Blink Source Counter
22492   *
22493 @@ -1789,14 +2869,14 @@
22494   *     1:      Number of MACs exceeds SK_MAX_MACS      (after level 1)
22495   *     2:      Adapter not present or not accessible
22496   *     3:      Illegal initialization level
22497 - *     4:      Initialization Level 1 Call missing
22498 + *     4:      Initialization level 1 call missing
22499   *     5:      Unexpected PHY type detected
22500   *     6:      HW self test failed
22501   */
22502  int    SkGeInit(
22503 -SK_AC  *pAC,           /* adapter context */
22504 -SK_IOC IoC,            /* IO context */
22505 -int            Level)          /* initialization level */
22506 +SK_AC  *pAC,           /* Adapter Context */
22507 +SK_IOC IoC,            /* I/O Context */
22508 +int            Level)          /* Initialization Level */
22509  {
22510         int             RetVal;         /* return value */
22511         SK_U32  DWord;
22512 @@ -1811,7 +2891,7 @@
22513                 SkGeInit0(pAC, IoC);
22514                 pAC->GIni.GILevel = SK_INIT_DATA;
22515                 break;
22516 -
22517 +
22518         case SK_INIT_IO:
22519                 /* Initialization Level 1 */
22520                 RetVal = SkGeInit1(pAC, IoC);
22521 @@ -1823,22 +2903,24 @@
22522                 SK_OUT32(IoC, B2_IRQM_INI, SK_TEST_VAL);
22523                 SK_IN32(IoC, B2_IRQM_INI, &DWord);
22524                 SK_OUT32(IoC, B2_IRQM_INI, 0L);
22525 -
22526 +
22527                 if (DWord != SK_TEST_VAL) {
22528                         RetVal = 2;
22529                         break;
22530                 }
22531
22532 +#ifdef DEBUG
22533                 /* check if the number of GIMacsFound matches SK_MAX_MACS */
22534                 if (pAC->GIni.GIMacsFound > SK_MAX_MACS) {
22535                         RetVal = 1;
22536                         break;
22537                 }
22538 +#endif /* DEBUG */
22539
22540                 /* Level 1 successfully passed */
22541                 pAC->GIni.GILevel = SK_INIT_IO;
22542                 break;
22543 -
22544 +
22545         case SK_INIT_RUN:
22546                 /* Initialization Level 2 */
22547                 if (pAC->GIni.GILevel != SK_INIT_IO) {
22548 @@ -1848,12 +2930,13 @@
22549                         RetVal = 4;
22550                         break;
22551                 }
22552 +
22553                 SkGeInit2(pAC, IoC);
22554
22555                 /* Level 2 successfully passed */
22556                 pAC->GIni.GILevel = SK_INIT_RUN;
22557                 break;
22558 -
22559 +
22560         default:
22561                 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E003, SKERR_HWI_E003MSG);
22562                 RetVal = 3;
22563 @@ -1876,40 +2959,88 @@
22564   *     nothing
22565   */
22566  void SkGeDeInit(
22567 -SK_AC  *pAC,           /* adapter context */
22568 -SK_IOC IoC)            /* IO context */
22569 +SK_AC  *pAC,           /* Adapter Context */
22570 +SK_IOC IoC)            /* I/O Context */
22571  {
22572         int     i;
22573         SK_U16  Word;
22574
22575 +#ifdef SK_PHY_LP_MODE_DEEP_SLEEP
22576 +       SK_U16  PmCtlSts;
22577 +#endif
22578 +
22579  #if (!defined(SK_SLIM) && !defined(VCPU))
22580         /* ensure I2C is ready */
22581         SkI2cWaitIrq(pAC, IoC);
22582 -#endif
22583 +#endif
22584
22585 -       /* stop all current transfer activity */
22586 -       for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
22587 -               if (pAC->GIni.GP[i].PState != SK_PRT_STOP &&
22588 -                       pAC->GIni.GP[i].PState != SK_PRT_RESET) {
22589 +#ifdef SK_PHY_LP_MODE_DEEP_SLEEP
22590 +       /*
22591 +        * for power saving purposes within mobile environments
22592 +        * we set the PHY to coma mode.
22593 +        */
22594 +#ifdef XXX
22595 +       if (pAC->GIni.GIVauxAvail) {
22596 +               /* switch power to VAUX */
22597 +               SK_OUT8(IoC, B0_POWER_CTRL, (SK_U8)(PC_VAUX_ENA | PC_VCC_ENA |
22598 +                       PC_VAUX_ON | PC_VCC_OFF));
22599 +       }
22600 +#endif /* XXX */
22601 +
22602 +       if (CHIP_ID_YUKON_2(pAC) && !pAC->GIni.GIAsfEnabled
22603 +#ifdef XXX
22604 +               || (pAC->GIni.GIYukonLite && pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3)
22605 +#endif /* XXX */
22606 +               ) {
22607 +
22608 +               /* flag for SkGmEnterLowPowerMode() that the call was from here */
22609 +               pAC->GIni.GILevel = SK_INIT_IO;
22610 +
22611 +               /* for all ports switch PHY to coma mode */
22612 +               for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
22613 +
22614 +                       /* Reset Rx MAC FIFO */
22615 +                       SK_OUT8(IoC, MR_ADDR(i, RX_GMF_CTRL_T), (SK_U8)GMF_RST_SET);
22616
22617 -                       SkGeStopPort(pAC, IoC, i, SK_STOP_ALL, SK_HARD_RST);
22618 +                       (void)SkGmEnterLowPowerMode(pAC, IoC, i, PHY_PM_DEEP_SLEEP);
22619 +               }
22620 +       }
22621 +       else if (pAC->GIni.GIYukonLite) {
22622 +               /* switch PHY to IEEE Power Down mode */
22623 +               (void)SkGmEnterLowPowerMode(pAC, IoC, 0, PHY_PM_IEEE_POWER_DOWN);
22624 +       }
22625 +#else /* !SK_PHY_LP_MODE_DEEP_SLEEP */
22626 +
22627 +       if (!pAC->GIni.GIAsfEnabled) {
22628 +               /* stop all current transfer activity */
22629 +               for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
22630 +                       if (pAC->GIni.GP[i].PState != SK_PRT_STOP &&
22631 +                               pAC->GIni.GP[i].PState != SK_PRT_RESET) {
22632 +
22633 +                               SkGeStopPort(pAC, IoC, i, SK_STOP_ALL, SK_HARD_RST);
22634 +                       }
22635                 }
22636         }
22637
22638 -       /* Reset all bits in the PCI STATUS register */
22639 +       /* reset all bits in the PCI STATUS register */
22640         /*
22641          * Note: PCI Cfg cycles cannot be used, because they are not
22642          *       available on some platforms after 'boot time'.
22643          */
22644 -       SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);
22645 -
22646 +       SK_IN16(IoC, PCI_C(pAC, PCI_STATUS), &Word);
22647 +
22648         SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
22649 -       SK_OUT16(IoC, PCI_C(PCI_STATUS), (SK_U16)(Word | PCI_ERRBITS));
22650 +
22651 +       SK_OUT16(IoC, PCI_C(pAC, PCI_STATUS), Word | (SK_U16)PCI_ERRBITS);
22652 +
22653         SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
22654
22655 -       /* do the reset, all LEDs are switched off now */
22656 -       SK_OUT8(IoC, B0_CTST, CS_RST_SET);
22657 -
22658 +       if (!pAC->GIni.GIAsfEnabled) {
22659 +               /* set the SW-reset */
22660 +               SK_OUT8(IoC, B0_CTST, CS_RST_SET);
22661 +       }
22662 +#endif /* !SK_PHY_LP_MODE_DEEP_SLEEP */
22663 +
22664         pAC->GIni.GILevel = SK_INIT_DATA;
22665  }      /* SkGeDeInit */
22666
22667 @@ -1943,8 +3074,8 @@
22668   *     2:      The port has to be stopped before it can be initialized again.
22669   */
22670  int SkGeInitPort(
22671 -SK_AC  *pAC,           /* adapter context */
22672 -SK_IOC IoC,            /* IO context */
22673 +SK_AC  *pAC,           /* Adapter Context */
22674 +SK_IOC IoC,            /* I/O Context */
22675  int            Port)           /* Port to configure */
22676  {
22677         SK_GEPORT *pPrt;
22678 @@ -1955,8 +3086,8 @@
22679                 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E004, SKERR_HWI_E004MSG);
22680                 return(1);
22681         }
22682 -
22683 -       if (pPrt->PState == SK_PRT_INIT || pPrt->PState == SK_PRT_RUN) {
22684 +
22685 +       if (pPrt->PState >= SK_PRT_INIT) {
22686                 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E005, SKERR_HWI_E005MSG);
22687                 return(2);
22688         }
22689 @@ -1967,35 +3098,35 @@
22690         if (pAC->GIni.GIGenesis) {
22691                 /* initialize Rx, Tx and Link LED */
22692                 /*
22693 -                * If 1000BT Phy needs LED initialization than swap
22694 +                * If 1000BT PHY needs LED initialization than swap
22695                  * LED and XMAC initialization order
22696                  */
22697                 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_ENA);
22698                 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, RX_LED_INI), SK_LED_ENA);
22699                 /* The Link LED is initialized by RLMT or Diagnostics itself */
22700 -
22701 +
22702                 SkXmInitMac(pAC, IoC, Port);
22703         }
22704  #endif /* GENESIS */
22705 -
22706 +
22707  #ifdef YUKON
22708         if (pAC->GIni.GIYukon) {
22709
22710                 SkGmInitMac(pAC, IoC, Port);
22711         }
22712  #endif /* YUKON */
22713 -
22714 +
22715         /* do NOT initialize the Link Sync Counter */
22716
22717         SkGeInitMacFifo(pAC, IoC, Port);
22718 -
22719 +
22720         SkGeInitRamBufs(pAC, IoC, Port);
22721 -
22722 +
22723         if (pPrt->PXSQSize != 0) {
22724                 /* enable Force Sync bit if synchronous queue available */
22725                 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_ENA_FSYNC);
22726         }
22727 -
22728 +
22729         SkGeInitBmu(pAC, IoC, Port);
22730
22731         /* mark port as initialized */
22732 @@ -2003,3 +3134,219 @@
22733
22734         return(0);
22735  }      /* SkGeInitPort */
22736 +
22737 +
22738 +#if (defined(YUK2) && !defined(SK_SLIM))
22739 +/******************************************************************************
22740 + *
22741 + *     SkGeRamWrite() - Writes One quadword to RAM
22742 + *
22743 + * Returns:
22744 + *     0
22745 + */
22746 +static void SkGeRamWrite(
22747 +SK_AC  *pAC,           /* Adapter Context */
22748 +SK_IOC IoC,            /* I/O Context */
22749 +SK_U32 Addr,           /* Address to be written to (in quadwords) */
22750 +SK_U32 LowDword,       /* Lower Dword to be written */
22751 +SK_U32 HighDword,      /* Upper Dword to be written */
22752 +int            Port)           /* Select RAM buffer (Yukon-2 has 2 RAM buffers) */
22753 +{
22754 +       SK_OUT32(IoC, SELECT_RAM_BUFFER(Port, B3_RAM_ADDR), Addr);
22755 +
22756 +       /* Write Access is initiated by writing the upper Dword */
22757 +       SK_OUT32(IoC, SELECT_RAM_BUFFER(Port, B3_RAM_DATA_LO), LowDword);
22758 +
22759 +       SK_OUT32(IoC, SELECT_RAM_BUFFER(Port, B3_RAM_DATA_HI), HighDword);
22760 +}
22761 +
22762 +/******************************************************************************
22763 + *
22764 + * SkYuk2RestartRxBmu() - Restart Receive BMU on Yukon-2
22765 + *
22766 + * return:
22767 + *     0       o.k.
22768 + *     1       timeout
22769 + */
22770 +int SkYuk2RestartRxBmu(
22771 +SK_AC  *pAC,           /* Adapter Context */
22772 +SK_IOC IoC,            /* I/O Context */
22773 +int            Port)           /* Port Index (MAC_1 + n) */
22774 +{
22775 +       SK_U16          Word;
22776 +       SK_U16          MacCtrl;
22777 +       SK_U16          RxCtrl;
22778 +       SK_U16          FlushMask;
22779 +       SK_U16          FlushTrsh;
22780 +       SK_U32          RamAdr;
22781 +       SK_U32          StartTime;
22782 +       SK_U32          CurrTime;
22783 +       SK_U32          Delta;
22784 +       SK_U32          TimeOut;
22785 +       SK_GEPORT       *pPrt;                  /* GIni Port struct pointer */
22786 +       SK_U16          WordBuffer[4];  /* Buffer to handle MAC address */
22787 +       int                     i;
22788 +       int                     Rtv;
22789 +
22790 +       Rtv = 0;
22791 +
22792 +       pPrt = &pAC->GIni.GP[Port];
22793 +
22794 +/*
22795 + 1. save Rx MAC FIFO Flush Mask and Rx MAC FIFO Flush Threshold
22796 + 2. save GMAC Rx Control Register
22797 + 3. re-initialize MAC Rx FIFO, Rx RAM Buffer Queue, PCI Rx FIFO,
22798 +       Rx BMU and Rx Prefetch Unit of the link.
22799 + 4. set Rx MAC FIFO Flush Mask to 0xffff
22800 +       set Rx MAC FIFO Flush Threshold to a high value, e.g. 0x20
22801 + 5. set GMAC to loopback mode and switch GMAC back to Rx/Tx enable
22802 + 6. clear Rx/Tx Frame Complete IRQ in Rx/T MAC FIFO Control Register
22803 + 7. send one packet with a size of 64bytes (size below flush threshold)
22804 +       from TXA RAM Buffer Queue to set the rx_sop flop:
22805 +       - set TxAQ Write Pointer to (packet size in qwords + 2)
22806 +       - set TxAQ Level to (packet size in qwords + 2)
22807 +       - write Internal Status Word 1 and 2 to TxAQ RAM Buffer Queue QWord 0,1
22808 +         according to figure 61 on page 330 of Yukon-2 Spec.
22809 +       - write MAC header with Destination Address = own MAC address to
22810 +         TxAQ RAM Buffer Queue QWords 2 and 3
22811 +       - set TxAQ Packet Counter to 1 -> packet is transmitted immediately
22812 + 8. poll GMAC IRQ Source Register for IRQ Rx/Tx Frame Complete
22813 + 9. restore GMAC Rx Control Register
22814 +10. restore Rx MAC FIFO Flush Mask and Rx MAC FIFO Flush Threshold
22815 +11. set GMAC back to GMII mode
22816 +*/
22817 +
22818 +       /* save Rx GMAC FIFO Flush Mask */
22819 +       SK_IN16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), &FlushMask);
22820 +
22821 +       /* save Rx GMAC FIFO Flush Threshold */
22822 +       SK_IN16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), &FlushTrsh);
22823 +
22824 +       /* save GMAC Rx Control Register */
22825 +       GM_IN16(IoC, Port, GM_RX_CTRL, &RxCtrl);
22826 +
22827 +       /* configure the GMAC FIFOs */
22828 +       SkGeInitMacFifo(pAC, IoC, Port);
22829 +
22830 +       SkGeInitRamBufs(pAC, IoC, Port);
22831 +
22832 +       SkGeInitBmu(pAC, IoC, Port);
22833 +
22834 +       /* configure Rx GMAC FIFO */
22835 +       SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), GMF_RX_CTRL_DEF);
22836 +
22837 +       /* set Rx GMAC FIFO Flush Mask */
22838 +       SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), 0xffff);
22839 +
22840 +       /* set Rx GMAC FIFO Flush Threshold */
22841 +       SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), 0x20);
22842 +
22843 +       /* set to promiscuous mode */
22844 +       Word = RxCtrl & ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
22845 +
22846 +       /* set GMAC Rx Control Register */
22847 +       GM_OUT16(IoC, Port, GM_RX_CTRL, Word);
22848 +
22849 +       /* get General Purpose Control */
22850 +       GM_IN16(IoC, Port, GM_GP_CTRL, &MacCtrl);
22851 +
22852 +       /* enable MAC Loopback Mode */
22853 +       GM_OUT16(IoC, Port, GM_GP_CTRL, MacCtrl | GM_GPCR_LOOP_ENA);
22854 +
22855 +       /* enable MAC Loopback Mode and Rx/Tx */
22856 +       GM_OUT16(IoC, Port, GM_GP_CTRL, MacCtrl | GM_GPCR_LOOP_ENA |
22857 +               GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
22858 +
22859 +       /* clear GMAC IRQ Rx Frame Complete */
22860 +       SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_CLI_RX_FC);
22861 +
22862 +       /* clear GMAC IRQ Tx Frame Complete */
22863 +       SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_CLI_TX_FC);
22864 +
22865 +       /* send one packet with a size of 64bytes from RAM buffer*/
22866 +
22867 +       RamAdr = pPrt->PXaQRamStart / 8;
22868 +
22869 +       SK_OUT32(IoC, RB_ADDR(pPrt->PXaQOff, RB_WP), RamAdr + 10);
22870 +
22871 +       SK_OUT32(IoC, RB_ADDR(pPrt->PXaQOff, RB_LEV), 10);
22872 +
22873 +       /* write 1st status quad word (packet end address in RAM, packet length */
22874 +       SkGeRamWrite(pAC, IoC, RamAdr, (RamAdr + 9) << 16, 64, Port);
22875 +
22876 +       /* write 2nd status quad word */
22877 +       SkGeRamWrite(pAC, IoC, RamAdr + 1, 0, 0, Port);
22878 +
22879 +       for (i = 0; i < 3; i++) {
22880 +               /* set MAC Destination Address */
22881 +               WordBuffer[i] = pPrt->PMacAddr[i];
22882 +       }
22883 +
22884 +       WordBuffer[3] = WordBuffer[0];
22885 +
22886 +       /* write DA to MAC header */
22887 +       SkGeRamWrite(pAC, IoC, RamAdr + 2, *(SK_U32 *)&WordBuffer[0],
22888 +               *(SK_U32 *)&WordBuffer[2], Port);
22889 +
22890 +       WordBuffer[0] = WordBuffer[1];
22891 +       WordBuffer[1] = WordBuffer[2];
22892 +       WordBuffer[2] = 0x3200;         /* len / type field (big endian) */
22893 +       WordBuffer[3] = 0;
22894 +
22895 +       /* write SA and type field to MAC header */
22896 +       SkGeRamWrite(pAC, IoC, RamAdr + 3, *(SK_U32 *)&WordBuffer[0],
22897 +               *(SK_U32 *)&WordBuffer[2], Port);
22898 +
22899 +       SkGeRamWrite(pAC, IoC, RamAdr + 4, 0x4c56524d,  /* "MRVL" */
22900 +               0x00464d2d, Port);                                                      /* "-MF"  */
22901 +
22902 +       for (i = 0; i < 5; i++) {
22903 +               /* fill packet with zeroes */
22904 +               SkGeRamWrite(pAC, IoC, RamAdr + 5 + i, 0, 0, Port);
22905 +       }
22906 +
22907 +       SK_OUT32(IoC, RB_ADDR(pPrt->PXaQOff, RB_PC), 1);
22908 +
22909 +       SK_IN32(IoC, GMAC_TI_ST_VAL, &StartTime);
22910 +
22911 +       /* set timeout to 10 ms */
22912 +       TimeOut = HW_MS_TO_TICKS(pAC, 10);
22913 +
22914 +       do {
22915 +               SK_IN32(IoC, GMAC_TI_ST_VAL, &CurrTime);
22916 +
22917 +               if (CurrTime >= StartTime) {
22918 +                       Delta = CurrTime - StartTime;
22919 +               }
22920 +               else {
22921 +                       Delta = CurrTime + ~StartTime + 1;
22922 +               }
22923 +
22924 +               if (Delta > TimeOut) {
22925 +                       Rtv = 1;
22926 +                       break;
22927 +               }
22928 +
22929 +               /* read the GMAC Interrupt source register */
22930 +               SK_IN16(IoC, MR_ADDR(Port, GMAC_IRQ_SRC), &Word);
22931 +
22932 +       } while ((Word & (GM_IS_TX_COMPL | GM_IS_RX_COMPL)) !=
22933 +                        (GM_IS_TX_COMPL | GM_IS_RX_COMPL));
22934 +
22935 +       /* disable MAC Loopback Mode and Rx/Tx */
22936 +       GM_OUT16(IoC, Port, GM_GP_CTRL, MacCtrl);
22937 +
22938 +       /* restore GMAC Rx Control Register */
22939 +       GM_OUT16(IoC, Port, GM_RX_CTRL, RxCtrl);
22940 +
22941 +       /* restore Rx GMAC FIFO Flush Mask */
22942 +       SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), FlushMask);
22943 +
22944 +       /* restore Rx GMAC FIFO Flush Threshold */
22945 +       SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), FlushTrsh);
22946 +
22947 +       return(Rtv);
22948 +
22949 +}      /* SkYuk2RestartRxBmu */
22950 +#endif /* YUK2 && !SK_SLIM */
22951 +
22952 diff -ruN linux/drivers/net/sk98lin/skgemib.c linux-new/drivers/net/sk98lin/skgemib.c
22953 --- linux/drivers/net/sk98lin/skgemib.c 2006-09-20 05:42:06.000000000 +0200
22954 +++ linux-new/drivers/net/sk98lin/skgemib.c     2006-07-28 14:13:54.000000000 +0200
22955 @@ -2,14 +2,15 @@
22956   *
22957   * Name:       skgemib.c
22958   * Project:    GEnesis, PCI Gigabit Ethernet Adapter
22959 - * Version:    $Revision$
22960 - * Date:       $Date$
22961 + * Version:    $Revision$
22962 + * Date:       $Date$
22963   * Purpose:    Private Network Management Interface Management Database
22964   *
22965   ****************************************************************************/
22966
22967  /******************************************************************************
22968   *
22969 + *     LICENSE:
22970   *     (C)Copyright 1998-2002 SysKonnect GmbH.
22971   *     (C)Copyright 2002-2003 Marvell.
22972   *
22973 @@ -19,6 +20,7 @@
22974   *     (at your option) any later version.
22975   *
22976   *     The information in this file is provided "AS IS" without warranty.
22977 + *     /LICENSE
22978   *
22979   ******************************************************************************/
22980
22981 @@ -80,6 +82,12 @@
22982         unsigned int TableIndex, SK_U32 NetIndex);
22983  #endif /* SK_DIAG_SUPPORT */
22984
22985 +#ifdef SK_ASF
22986 +PNMI_STATIC int Asf(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
22987 +    char *pBuf, unsigned int *pLen, SK_U32 Instance,
22988 +    unsigned int TableIndex, SK_U32 NetIndex);
22989 +#endif /* SK_ASF */
22990 +
22991
22992  /* defines *******************************************************************/
22993  #define ID_TABLE_SIZE (sizeof(IdTable)/sizeof(IdTable[0]))
22994 @@ -251,6 +259,183 @@
22995                 0,
22996                 SK_PNMI_RW, DiagActions, 0},
22997  #endif /* SK_DIAG_SUPPORT */
22998 +#ifdef SK_ASF
22999 +    {OID_SKGE_ASF,
23000 +        0,
23001 +        0,
23002 +        0,
23003 +        SK_PNMI_RW, Asf, 0},
23004 +    {OID_SKGE_ASF_STORE_CONFIG,
23005 +        0,
23006 +        0,
23007 +        0,
23008 +        SK_PNMI_RW, Asf, 0},
23009 +    {OID_SKGE_ASF_ENA,
23010 +        0,
23011 +        0,
23012 +        0,
23013 +        SK_PNMI_RW, Asf, 0},
23014 +    {OID_SKGE_ASF_RETRANS,
23015 +        0,
23016 +        0,
23017 +        0,
23018 +        SK_PNMI_RW, Asf, 0},
23019 +    {OID_SKGE_ASF_RETRANS_INT,
23020 +        0,
23021 +        0,
23022 +        0,
23023 +        SK_PNMI_RW, Asf, 0},
23024 +    {OID_SKGE_ASF_HB_ENA,
23025 +        0,
23026 +        0,
23027 +        0,
23028 +        SK_PNMI_RW, Asf, 0},
23029 +    {OID_SKGE_ASF_HB_INT,
23030 +        0,
23031 +        0,
23032 +        0,
23033 +        SK_PNMI_RW, Asf, 0},
23034 +    {OID_SKGE_ASF_WD_ENA,
23035 +        0,
23036 +        0,
23037 +        0,
23038 +        SK_PNMI_RW, Asf, 0},
23039 +    {OID_SKGE_ASF_WD_TIME,
23040 +        0,
23041 +        0,
23042 +        0,
23043 +        SK_PNMI_RW, Asf, 0},
23044 +    {OID_SKGE_ASF_IP_SOURCE,
23045 +        0,
23046 +        0,
23047 +        0,
23048 +        SK_PNMI_RW, Asf, 0},
23049 +    {OID_SKGE_ASF_MAC_SOURCE,
23050 +        0,
23051 +        0,
23052 +        0,
23053 +        SK_PNMI_RW, Asf, 0},
23054 +    {OID_SKGE_ASF_IP_DEST,
23055 +        0,
23056 +        0,
23057 +        0,
23058 +        SK_PNMI_RW, Asf, 0},
23059 +    {OID_SKGE_ASF_MAC_DEST,
23060 +        0,
23061 +        0,
23062 +        0,
23063 +        SK_PNMI_RW, Asf, 0},
23064 +    {OID_SKGE_ASF_COMMUNITY_NAME,
23065 +        0,
23066 +        0,
23067 +        0,
23068 +        SK_PNMI_RW, Asf, 0},
23069 +    {OID_SKGE_ASF_RSP_ENA,
23070 +        0,
23071 +        0,
23072 +        0,
23073 +        SK_PNMI_RW, Asf, 0},
23074 +    {OID_SKGE_ASF_RETRANS_COUNT_MIN,
23075 +        0,
23076 +        0,
23077 +        0,
23078 +        SK_PNMI_RW, Asf, 0},
23079 +    {OID_SKGE_ASF_RETRANS_COUNT_MAX,
23080 +        0,
23081 +        0,
23082 +        0,
23083 +        SK_PNMI_RW, Asf, 0},
23084 +    {OID_SKGE_ASF_RETRANS_INT_MIN,
23085 +        0,
23086 +        0,
23087 +        0,
23088 +        SK_PNMI_RW, Asf, 0},
23089 +    {OID_SKGE_ASF_RETRANS_INT_MAX,
23090 +        0,
23091 +        0,
23092 +        0,
23093 +        SK_PNMI_RW, Asf, 0},
23094 +    {OID_SKGE_ASF_HB_INT_MIN,
23095 +        0,
23096 +        0,
23097 +        0,
23098 +        SK_PNMI_RW, Asf, 0},
23099 +    {OID_SKGE_ASF_HB_INT_MAX,
23100 +        0,
23101 +        0,
23102 +        0,
23103 +        SK_PNMI_RW, Asf, 0},
23104 +    {OID_SKGE_ASF_WD_TIME_MIN,
23105 +        0,
23106 +        0,
23107 +        0,
23108 +        SK_PNMI_RW, Asf, 0},
23109 +    {OID_SKGE_ASF_WD_TIME_MAX,
23110 +        0,
23111 +        0,
23112 +        0,
23113 +        SK_PNMI_RW, Asf, 0},
23114 +    {OID_SKGE_ASF_HB_CAP,
23115 +        0,
23116 +        0,
23117 +        0,
23118 +        SK_PNMI_RW, Asf, 0},
23119 +    {OID_SKGE_ASF_WD_TIMER_RES,
23120 +        0,
23121 +        0,
23122 +        0,
23123 +        SK_PNMI_RW, Asf, 0},
23124 +    {OID_SKGE_ASF_GUID,
23125 +        0,
23126 +        0,
23127 +        0,
23128 +        SK_PNMI_RW, Asf, 0},
23129 +    {OID_SKGE_ASF_KEY_OP,
23130 +        0,
23131 +        0,
23132 +        0,
23133 +        SK_PNMI_RW, Asf, 0},
23134 +    {OID_SKGE_ASF_KEY_ADM,
23135 +        0,
23136 +        0,
23137 +        0,
23138 +        SK_PNMI_RW, Asf, 0},
23139 +    {OID_SKGE_ASF_KEY_GEN,
23140 +        0,
23141 +        0,
23142 +        0,
23143 +        SK_PNMI_RW, Asf, 0},
23144 +    {OID_SKGE_ASF_CAP,
23145 +        0,
23146 +        0,
23147 +        0,
23148 +        SK_PNMI_RW, Asf, 0},
23149 +    {OID_SKGE_ASF_PAR_1,
23150 +        0,
23151 +        0,
23152 +        0,
23153 +        SK_PNMI_RW, Asf, 0},
23154 +    {OID_SKGE_ASF_OVERALL_OID,
23155 +        0,
23156 +        0,
23157 +        0,
23158 +        SK_PNMI_RW, Asf, 0},
23159 +    {OID_SKGE_ASF_FWVER_OID,
23160 +        0,
23161 +        0,
23162 +        0,
23163 +        SK_PNMI_RO, Asf, 0},
23164 +    {OID_SKGE_ASF_ACPI_OID,
23165 +        0,
23166 +        0,
23167 +        0,
23168 +        SK_PNMI_RO, Asf, 0},
23169 +    {OID_SKGE_ASF_SMBUS_OID,
23170 +        0,
23171 +        0,
23172 +        0,
23173 +        SK_PNMI_RO, Asf, 0},
23174 +#endif /* SK_ASF */
23175         {OID_SKGE_MDB_VERSION,
23176                 1,
23177                 0,
23178 @@ -871,6 +1056,13 @@
23179                 sizeof(SK_PNMI_CONF),
23180                 SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyType),
23181                 SK_PNMI_RO, MacPrivateConf, 0},
23182 +#ifdef SK_PHY_LP_MODE
23183 +               {OID_SKGE_PHY_LP_MODE,
23184 +               SK_PNMI_MAC_ENTRIES,
23185 +               sizeof(SK_PNMI_CONF),
23186 +               SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyMode),
23187 +               SK_PNMI_RW, MacPrivateConf, 0},
23188 +#endif
23189         {OID_SKGE_LINK_CAP,
23190                 SK_PNMI_MAC_ENTRIES,
23191                 sizeof(SK_PNMI_CONF),
23192 @@ -1066,6 +1258,11 @@
23193                 0,
23194                 0,
23195                 SK_PNMI_RO, Vct, 0},
23196 +       {OID_SKGE_VCT_CAPABILITIES,
23197 +               0,
23198 +               0,
23199 +               0,
23200 +               SK_PNMI_RO, Vct, 0},
23201         {OID_SKGE_BOARDLEVEL,
23202                 0,
23203                 0,
23204 diff -ruN linux/drivers/net/sk98lin/skgepnmi.c linux-new/drivers/net/sk98lin/skgepnmi.c
23205 --- linux/drivers/net/sk98lin/skgepnmi.c        2006-09-20 05:42:06.000000000 +0200
23206 +++ linux-new/drivers/net/sk98lin/skgepnmi.c    2006-07-28 14:13:54.000000000 +0200
23207 @@ -1,15 +1,16 @@
23208  /*****************************************************************************
23209   *
23210   * Name:       skgepnmi.c
23211 - * Project:    GEnesis, PCI Gigabit Ethernet Adapter
23212 - * Version:    $Revision$
23213 - * Date:       $Date$
23214 + * Project:    Gigabit Ethernet Adapters, PNMI-Module
23215 + * Version:    $Revision$
23216 + * Date:       $Date$
23217   * Purpose:    Private Network Management Interface
23218   *
23219   ****************************************************************************/
23220
23221  /******************************************************************************
23222   *
23223 + *     LICENSE:
23224   *     (C)Copyright 1998-2002 SysKonnect GmbH.
23225   *     (C)Copyright 2002-2003 Marvell.
23226   *
23227 @@ -19,14 +20,14 @@
23228   *     (at your option) any later version.
23229   *
23230   *     The information in this file is provided "AS IS" without warranty.
23231 + *     /LICENSE
23232   *
23233   ******************************************************************************/
23234
23235 -
23236 -#ifndef _lint
23237 +#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
23238  static const char SysKonnectFileId[] =
23239 -       "@(#) $Id$ (C) Marvell.";
23240 -#endif /* !_lint */
23241 +       "@(#) $Id$ (C) Marvell.";
23242 +#endif
23243
23244  #include "h/skdrv1st.h"
23245  #include "h/sktypes.h"
23246 @@ -38,12 +39,14 @@
23247  #include "h/skcsum.h"
23248  #include "h/skvpd.h"
23249  #include "h/skgehw.h"
23250 +#include "h/sky2le.h"
23251  #include "h/skgeinit.h"
23252  #include "h/skdrv2nd.h"
23253  #include "h/skgepnm2.h"
23254  #ifdef SK_POWER_MGMT
23255  #include "h/skgepmgt.h"
23256 -#endif
23257 +#endif /* SK_POWER_MGMT */
23258 +
23259  /* defines *******************************************************************/
23260
23261  #ifndef DEBUG
23262 @@ -53,23 +56,6 @@
23263  #endif /* DEBUG */
23264
23265  /*
23266 - * Public Function prototypes
23267 - */
23268 -int SkPnmiInit(SK_AC *pAC, SK_IOC IoC, int level);
23269 -int SkPnmiSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void *pBuf,
23270 -       unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex);
23271 -int SkPnmiGetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf,
23272 -       unsigned int *pLen, SK_U32 NetIndex);
23273 -int SkPnmiPreSetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf,
23274 -       unsigned int *pLen, SK_U32 NetIndex);
23275 -int SkPnmiSetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf,
23276 -       unsigned int *pLen, SK_U32 NetIndex);
23277 -int SkPnmiEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Param);
23278 -int SkPnmiGenIoctl(SK_AC *pAC, SK_IOC IoC, void * pBuf,
23279 -       unsigned int * pLen, SK_U32 NetIndex);
23280 -
23281 -
23282 -/*
23283   * Private Function prototypes
23284   */
23285
23286 @@ -105,9 +91,8 @@
23287  PNMI_STATIC int RlmtUpdate(SK_AC *pAC, SK_IOC IoC, SK_U32 NetIndex);
23288  PNMI_STATIC int SirqUpdate(SK_AC *pAC, SK_IOC IoC);
23289  PNMI_STATIC void VirtualConf(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, char *pBuf);
23290 -PNMI_STATIC int Vct(SK_AC *pAC, SK_IOC IoC, int Action, SK_U32 Id, char *pBuf,
23291 -       unsigned int *pLen, SK_U32 Instance, unsigned int TableIndex, SK_U32 NetIndex);
23292  PNMI_STATIC void CheckVctStatus(SK_AC *, SK_IOC, char *, SK_U32, SK_U32);
23293 +PNMI_STATIC void VctGetResults(SK_AC *, SK_IOC, SK_U32);
23294
23295  /*
23296   * Table to correlate OID with handler function and index to
23297 @@ -349,17 +334,13 @@
23298   *     Always 0
23299   */
23300  int SkPnmiInit(
23301 -SK_AC *pAC,            /* Pointer to adapter context */
23302 -SK_IOC IoC,            /* IO context handle */
23303 -int Level)             /* Initialization level */
23304 +SK_AC  *pAC,           /* Pointer to adapter context */
23305 +SK_IOC IoC,            /* IO context handle */
23306 +int            Level)          /* Initialization level */
23307  {
23308         unsigned int    PortMax;        /* Number of ports */
23309         unsigned int    PortIndex;      /* Current port index in loop */
23310 -       SK_U16          Val16;          /* Multiple purpose 16 bit variable */
23311 -       SK_U8           Val8;           /* Mulitple purpose 8 bit variable */
23312 -       SK_EVPARA       EventParam;     /* Event struct for timer event */
23313 -       SK_PNMI_VCT     *pVctBackupData;
23314 -
23315 +       SK_EVPARA               EventParam;     /* Event struct for timer event */
23316
23317         SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
23318                 ("PNMI: SkPnmiInit: Called, level=%d\n", Level));
23319 @@ -368,13 +349,19 @@
23320
23321         case SK_INIT_DATA:
23322                 SK_MEMSET((char *)&pAC->Pnmi, 0, sizeof(pAC->Pnmi));
23323 +
23324                 pAC->Pnmi.TrapBufFree = SK_PNMI_TRAP_QUEUE_LEN;
23325                 pAC->Pnmi.StartUpTime = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC));
23326                 pAC->Pnmi.RlmtChangeThreshold = SK_PNMI_DEF_RLMT_CHG_THRES;
23327 +
23328                 for (PortIndex = 0; PortIndex < SK_MAX_MACS; PortIndex ++) {
23329
23330                         pAC->Pnmi.Port[PortIndex].ActiveFlag = SK_FALSE;
23331                         pAC->Pnmi.DualNetActiveFlag = SK_FALSE;
23332 +
23333 +                       /* Initialize DSP variables for Vct() to 0xff => Never written! */
23334 +                       pAC->GIni.GP[PortIndex].PCableLen = 0xff;
23335 +                       pAC->Pnmi.VctBackup[PortIndex].CableLen = 0xff;
23336                 }
23337
23338  #ifdef SK_PNMI_CHECK
23339 @@ -404,51 +391,36 @@
23340                 break;
23341
23342         case SK_INIT_IO:
23343 -               /*
23344 -                * Reset MAC counters
23345 -                */
23346 +
23347 +               /* Reset MAC counters. */
23348                 PortMax = pAC->GIni.GIMacsFound;
23349
23350                 for (PortIndex = 0; PortIndex < PortMax; PortIndex ++) {
23351
23352                         pAC->GIni.GIFunc.pFnMacResetCounter(pAC, IoC, PortIndex);
23353                 }
23354 -
23355 -               /* Initialize DSP variables for Vct() to 0xff => Never written! */
23356 -               for (PortIndex = 0; PortIndex < PortMax; PortIndex ++) {
23357 -                       pAC->GIni.GP[PortIndex].PCableLen = 0xff;
23358 -                       pVctBackupData = &pAC->Pnmi.VctBackup[PortIndex];
23359 -                       pVctBackupData->PCableLen = 0xff;
23360 -               }
23361 -
23362 -               /*
23363 -                * Get pci bus speed
23364 -                */
23365 -               SK_IN16(IoC, B0_CTST, &Val16);
23366 -               if ((Val16 & CS_BUS_CLOCK) == 0) {
23367
23368 -                       pAC->Pnmi.PciBusSpeed = 33;
23369 +               /* Get PCI bus speed. */
23370 +               if (pAC->GIni.GIPciClock66) {
23371 +
23372 +                       pAC->Pnmi.PciBusSpeed = 66;
23373                 }
23374                 else {
23375 -                       pAC->Pnmi.PciBusSpeed = 66;
23376 +                       pAC->Pnmi.PciBusSpeed = 33;
23377                 }
23378
23379 -               /*
23380 -                * Get pci bus width
23381 -                */
23382 -               SK_IN16(IoC, B0_CTST, &Val16);
23383 -               if ((Val16 & CS_BUS_SLOT_SZ) == 0) {
23384 +               /* Get PCI bus width. */
23385 +               if (pAC->GIni.GIPciSlot64) {
23386
23387 -                       pAC->Pnmi.PciBusWidth = 32;
23388 +                       pAC->Pnmi.PciBusWidth = 64;
23389                 }
23390                 else {
23391 -                       pAC->Pnmi.PciBusWidth = 64;
23392 +                       pAC->Pnmi.PciBusWidth = 32;
23393                 }
23394
23395 -               /*
23396 -                * Get chipset
23397 -                */
23398 +               /* Get chipset. */
23399                 switch (pAC->GIni.GIChipId) {
23400 +
23401                 case CHIP_ID_GENESIS:
23402                         pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_XMAC;
23403                         break;
23404 @@ -457,57 +429,51 @@
23405                         pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON;
23406                         break;
23407
23408 +               case CHIP_ID_YUKON_LITE:
23409 +                       pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_LITE;
23410 +                       break;
23411 +
23412 +               case CHIP_ID_YUKON_LP:
23413 +                       pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_LP;
23414 +                       break;
23415 +
23416 +               case CHIP_ID_YUKON_XL:
23417 +                       pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_XL;
23418 +                       break;
23419 +
23420 +               case CHIP_ID_YUKON_EC:
23421 +                       pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_EC;
23422 +                       break;
23423 +
23424 +               case CHIP_ID_YUKON_FE:
23425 +                       pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_FE;
23426 +                       break;
23427 +
23428                 default:
23429                         break;
23430                 }
23431
23432 -               /*
23433 -                * Get PMD and DeviceType
23434 -                */
23435 -               SK_IN8(IoC, B2_PMD_TYP, &Val8);
23436 -               switch (Val8) {
23437 +               /* Get PMD and Device Type. */
23438 +               switch (pAC->GIni.GIPmdTyp) {
23439 +
23440                 case 'S':
23441                         pAC->Pnmi.PMD = 3;
23442 -                       if (pAC->GIni.GIMacsFound > 1) {
23443 -
23444 -                               pAC->Pnmi.DeviceType = 0x00020002;
23445 -                       }
23446 -                       else {
23447 -                               pAC->Pnmi.DeviceType = 0x00020001;
23448 -                       }
23449 +                       pAC->Pnmi.DeviceType = 0x00020001;
23450                         break;
23451
23452                 case 'L':
23453                         pAC->Pnmi.PMD = 2;
23454 -                       if (pAC->GIni.GIMacsFound > 1) {
23455 -
23456 -                               pAC->Pnmi.DeviceType = 0x00020004;
23457 -                       }
23458 -                       else {
23459 -                               pAC->Pnmi.DeviceType = 0x00020003;
23460 -                       }
23461 +                       pAC->Pnmi.DeviceType = 0x00020003;
23462                         break;
23463
23464                 case 'C':
23465                         pAC->Pnmi.PMD = 4;
23466 -                       if (pAC->GIni.GIMacsFound > 1) {
23467 -
23468 -                               pAC->Pnmi.DeviceType = 0x00020006;
23469 -                       }
23470 -                       else {
23471 -                               pAC->Pnmi.DeviceType = 0x00020005;
23472 -                       }
23473 +                       pAC->Pnmi.DeviceType = 0x00020005;
23474                         break;
23475
23476                 case 'T':
23477                         pAC->Pnmi.PMD = 5;
23478 -                       if (pAC->GIni.GIMacsFound > 1) {
23479 -
23480 -                               pAC->Pnmi.DeviceType = 0x00020008;
23481 -                       }
23482 -                       else {
23483 -                               pAC->Pnmi.DeviceType = 0x00020007;
23484 -                       }
23485 +                       pAC->Pnmi.DeviceType = 0x00020007;
23486                         break;
23487
23488                 default :
23489 @@ -516,11 +482,14 @@
23490                         break;
23491                 }
23492
23493 -               /*
23494 -                * Get connector
23495 -                */
23496 -               SK_IN8(IoC, B2_CONN_TYP, &Val8);
23497 -               switch (Val8) {
23498 +               if (pAC->GIni.GIMacsFound > 1) {
23499 +
23500 +                       pAC->Pnmi.DeviceType++;
23501 +               }
23502 +
23503 +               /* Get connector type. */
23504 +               switch (pAC->GIni.GIConTyp) {
23505 +
23506                 case 'C':
23507                         pAC->Pnmi.Connector = 2;
23508                         break;
23509 @@ -548,17 +517,17 @@
23510                 break;
23511
23512         case SK_INIT_RUN:
23513 -               /*
23514 -                * Start timer for RLMT change counter
23515 -                */
23516 +
23517 +               /* Start timer for RLMT change counter. */
23518                 SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
23519 +
23520                 SkTimerStart(pAC, IoC, &pAC->Pnmi.RlmtChangeEstimate.EstTimer,
23521 -                       28125000, SKGE_PNMI, SK_PNMI_EVT_CHG_EST_TIMER,
23522 +                       SK_PNMI_EVT_TIMER_CHECK, SKGE_PNMI, SK_PNMI_EVT_CHG_EST_TIMER,
23523                         EventParam);
23524                 break;
23525
23526         default:
23527 -               break; /* Nothing todo */
23528 +               break; /* Nothing to do. */
23529         }
23530
23531         return (0);
23532 @@ -583,7 +552,7 @@
23533   *                           exist (e.g. port instance 3 on a two port
23534   *                              adapter.
23535   */
23536 -static int SkPnmiGetVar(
23537 +int SkPnmiGetVar(
23538  SK_AC *pAC,            /* Pointer to adapter context */
23539  SK_IOC IoC,            /* IO context handle */
23540  SK_U32 Id,             /* Object ID that is to be processed */
23541 @@ -607,7 +576,7 @@
23542   * Description:
23543   *     Calls a general sub-function for all this stuff. The preset does
23544   *     the same as a set, but returns just before finally setting the
23545 - *     new value. This is useful to check if a set might be successfull.
23546 + *     new value. This is usefull to check if a set might be successfull.
23547   *     If the instance -1 is passed, an array of values is supposed and
23548   *     all instances of the OID will be set.
23549   *
23550 @@ -625,7 +594,7 @@
23551   *                           exist (e.g. port instance 3 on a two port
23552   *                              adapter.
23553   */
23554 -static int SkPnmiPreSetVar(
23555 +int SkPnmiPreSetVar(
23556  SK_AC *pAC,            /* Pointer to adapter context */
23557  SK_IOC IoC,            /* IO context handle */
23558  SK_U32 Id,             /* Object ID that is to be processed */
23559 @@ -638,7 +607,6 @@
23560                 ("PNMI: SkPnmiPreSetVar: Called, Id=0x%x, BufLen=%d, Instance=%d, NetIndex=%d\n",
23561                         Id, *pLen, Instance, NetIndex));
23562
23563 -
23564         return (PnmiVar(pAC, IoC, SK_PNMI_PRESET, Id, (char *)pBuf, pLen,
23565                 Instance, NetIndex));
23566  }
23567 @@ -650,7 +618,7 @@
23568   * Description:
23569   *     Calls a general sub-function for all this stuff. The preset does
23570   *     the same as a set, but returns just before finally setting the
23571 - *     new value. This is useful to check if a set might be successfull.
23572 + *     new value. This is usefull to check if a set might be successfull.
23573   *     If the instance -1 is passed, an array of values is supposed and
23574   *     all instances of the OID will be set.
23575   *
23576 @@ -720,7 +688,6 @@
23577         unsigned int    TmpLen;
23578         char            KeyArr[SK_PNMI_VPD_ENTRIES][SK_PNMI_VPD_KEY_SIZE];
23579
23580 -
23581         SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
23582                 ("PNMI: SkPnmiGetStruct: Called, BufLen=%d, NetIndex=%d\n",
23583                         *pLen, NetIndex));
23584 @@ -729,22 +696,19 @@
23585
23586                 if (*pLen >= SK_PNMI_MIN_STRUCT_SIZE) {
23587
23588 -                       SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_TOO_SHORT,
23589 -                               (SK_U32)(-1));
23590 +                       SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_TOO_SHORT, (SK_U32)(-1));
23591                 }
23592
23593                 *pLen = SK_PNMI_STRUCT_SIZE;
23594                 return (SK_PNMI_ERR_TOO_SHORT);
23595         }
23596
23597 -    /*
23598 -     * Check NetIndex
23599 -     */
23600 +       /* Check NetIndex. */
23601         if (NetIndex >= pAC->Rlmt.NumNets) {
23602                 return (SK_PNMI_ERR_UNKNOWN_NET);
23603         }
23604
23605 -       /* Update statistic */
23606 +       /* Update statistics. */
23607         SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On call");
23608
23609         if ((Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1)) !=
23610 @@ -769,35 +733,37 @@
23611                 return (Ret);
23612         }
23613
23614 -       /*
23615 -        * Increment semaphores to indicate that an update was
23616 -        * already done
23617 -        */
23618 +       /* Increment semaphores to indicate that an update was already done. */
23619         pAC->Pnmi.MacUpdatedFlag ++;
23620         pAC->Pnmi.RlmtUpdatedFlag ++;
23621         pAC->Pnmi.SirqUpdatedFlag ++;
23622
23623 -       /* Get vpd keys for instance calculation */
23624 -       Ret = GetVpdKeyArr(pAC, IoC, &KeyArr[0][0], sizeof(KeyArr), &TmpLen);
23625 -       if (Ret != SK_PNMI_ERR_OK) {
23626 +       /*
23627 +        * Get VPD keys for instance calculation.
23628 +        * Please read comment in Vpd().
23629 +        */
23630 +       if (pAC->Pnmi.VpdKeyReadError == SK_FALSE) {
23631 +               Ret = GetVpdKeyArr(pAC, IoC, &KeyArr[0][0], sizeof(KeyArr), &TmpLen);
23632 +               if (Ret != SK_PNMI_ERR_OK) {
23633
23634 -               pAC->Pnmi.MacUpdatedFlag --;
23635 -               pAC->Pnmi.RlmtUpdatedFlag --;
23636 -               pAC->Pnmi.SirqUpdatedFlag --;
23637 +                       pAC->Pnmi.MacUpdatedFlag --;
23638 +                       pAC->Pnmi.RlmtUpdatedFlag --;
23639 +                       pAC->Pnmi.SirqUpdatedFlag --;
23640
23641 -               SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On return");
23642 -               SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1));
23643 -               *pLen = SK_PNMI_MIN_STRUCT_SIZE;
23644 -               return (SK_PNMI_ERR_GENERAL);
23645 +                       SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On return");
23646 +                       SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1));
23647 +                       *pLen = SK_PNMI_MIN_STRUCT_SIZE;
23648 +                       return (SK_PNMI_ERR_GENERAL);
23649 +               }
23650         }
23651
23652 -       /* Retrieve values */
23653 +       /* Retrieve values. */
23654         SK_MEMSET((char *)pBuf, 0, SK_PNMI_STRUCT_SIZE);
23655 +
23656         for (TableIndex = 0; TableIndex < ID_TABLE_SIZE; TableIndex ++) {
23657
23658                 InstanceNo = IdTable[TableIndex].InstanceNo;
23659 -               for (InstanceCnt = 1; InstanceCnt <= InstanceNo;
23660 -                       InstanceCnt ++) {
23661 +               for (InstanceCnt = 1; InstanceCnt <= InstanceNo; InstanceCnt ++) {
23662
23663                         DstOffset = IdTable[TableIndex].Offset +
23664                                 (InstanceCnt - 1) *
23665 @@ -866,7 +832,7 @@
23666   * Description:
23667   *     Calls a general sub-function for all this set stuff. The preset does
23668   *     the same as a set, but returns just before finally setting the
23669 - *     new value. This is useful to check if a set might be successfull.
23670 + *     new value. This is usefull to check if a set might be successfull.
23671   *     The sub-function runs through the IdTable, checks which OIDs are able
23672   *     to set, and calls the handler function of the OID to perform the
23673   *     preset. The return value of the function will also be stored in
23674 @@ -994,7 +960,6 @@
23675         unsigned int    PhysPortIndex;
23676      unsigned int       MaxNetNumber;
23677         int                     CounterIndex;
23678 -       int                     Ret;
23679         SK_U16          MacStatus;
23680         SK_U64          OverflowStatus;
23681         SK_U64          Mask;
23682 @@ -1008,12 +973,7 @@
23683         SK_U64          Delta;
23684         SK_PNMI_ESTIMATE *pEst;
23685         SK_U32          NetIndex;
23686 -       SK_GEPORT       *pPrt;
23687 -       SK_PNMI_VCT     *pVctBackupData;
23688         SK_U32          RetCode;
23689 -       int             i;
23690 -       SK_U32          CableLength;
23691 -
23692
23693  #ifdef DEBUG
23694         if (Event != SK_PNMI_EVT_XMAC_RESET) {
23695 @@ -1044,9 +1004,7 @@
23696  #endif /* DEBUG */
23697                 OverflowStatus = 0;
23698
23699 -               /*
23700 -                * Check which source caused an overflow interrupt.
23701 -                */
23702 +               /* Check which source caused an overflow interrupt. */
23703                 if ((pAC->GIni.GIFunc.pFnMacOverflow(pAC, IoC, PhysPortIndex,
23704                                 MacStatus, &OverflowStatus) != 0) ||
23705                         (OverflowStatus == 0)) {
23706 @@ -1064,7 +1022,6 @@
23707
23708                         Mask = (SK_U64)1 << CounterIndex;
23709                         if ((OverflowStatus & Mask) == 0) {
23710 -
23711                                 continue;
23712                         }
23713
23714 @@ -1096,9 +1053,7 @@
23715                         case SK_PNMI_HRX_IRLENGTH:
23716                         case SK_PNMI_HRX_RESERVED:
23717
23718 -                       /*
23719 -                        * the following counters aren't be handled (id > 63)
23720 -                        */
23721 +                       /* The following counters aren't be handled (id > 63). */
23722                         case SK_PNMI_HTX_SYNC:
23723                         case SK_PNMI_HTX_SYNC_OCTET:
23724                                 break;
23725 @@ -1185,7 +1140,7 @@
23726                 if ((unsigned int)Param.Para64 >= (unsigned int)pAC->I2c.MaxSens) {
23727
23728                         SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
23729 -                               ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_SEN_ERR_UPP parameter wrong, SensorIndex=%d\n",
23730 +                               ("PNMI: ERR: SK_PNMI_EVT_SEN_ERR_UPP parameter wrong, SensorIndex=%d\n",
23731                                 (unsigned int)Param.Para64));
23732                         return (0);
23733                 }
23734 @@ -1204,16 +1159,14 @@
23735         case SK_PNMI_EVT_CHG_EST_TIMER:
23736                 /*
23737                  * Calculate port switch average on a per hour basis
23738 -                *   Time interval for check       : 28125 ms
23739 +                *   Time interval for check       : 28125 ms (SK_PNMI_EVT_TIMER_CHECK)
23740                  *   Number of values for average  : 8
23741                  *
23742                  * Be careful in changing these values, on change check
23743                  *   - typedef of SK_PNMI_ESTIMATE (Size of EstValue
23744                  *     array one less than value number)
23745                  *   - Timer initialization SkTimerStart() in SkPnmiInit
23746 -                *   - Delta value below must be multiplicated with
23747 -                *     power of 2
23748 -                *
23749 +                *   - Delta value below must be multiplicated with power of 2
23750                  */
23751                 pEst = &pAC->Pnmi.RlmtChangeEstimate;
23752                 CounterIndex = pEst->EstValueIndex + 1;
23753 @@ -1236,7 +1189,7 @@
23754                         Delta = NewestValue - OldestValue;
23755                 }
23756                 else {
23757 -                       /* Overflow situation */
23758 +                       /* Overflow situation. */
23759                         Delta = (SK_U64)(0 - OldestValue) + NewestValue;
23760                 }
23761
23762 @@ -1262,8 +1215,9 @@
23763                 }
23764
23765                 SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
23766 +
23767                 SkTimerStart(pAC, IoC, &pAC->Pnmi.RlmtChangeEstimate.EstTimer,
23768 -                       28125000, SKGE_PNMI, SK_PNMI_EVT_CHG_EST_TIMER,
23769 +                       SK_PNMI_EVT_TIMER_CHECK, SKGE_PNMI, SK_PNMI_EVT_CHG_EST_TIMER,
23770                         EventParam);
23771                 break;
23772
23773 @@ -1307,29 +1261,25 @@
23774                                 (unsigned int)Param.Para64));
23775                         return (0);
23776                 }
23777 -#endif
23778 +#endif /* DEBUG */
23779 +
23780                 PhysPortIndex = (unsigned int)Param.Para64;
23781
23782 -               /*
23783 -                * Update XMAC statistic to get fresh values
23784 -                */
23785 -               Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1);
23786 -               if (Ret != SK_PNMI_ERR_OK) {
23787 +               /* Update XMAC statistic to get fresh values. */
23788 +               if (MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1) !=
23789 +                       SK_PNMI_ERR_OK) {
23790
23791                         SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return");
23792                         return (0);
23793                 }
23794 -               /*
23795 -                * Increment semaphore to indicate that an update was
23796 -                * already done
23797 -                */
23798 +
23799 +               /* Increment semaphore to indicate that an update was already done. */
23800                 pAC->Pnmi.MacUpdatedFlag ++;
23801
23802                 for (CounterIndex = 0; CounterIndex < SK_PNMI_MAX_IDX;
23803                         CounterIndex ++) {
23804
23805                         if (!StatAddr[CounterIndex][MacType].GetOffset) {
23806 -
23807                                 continue;
23808                         }
23809
23810 @@ -1362,14 +1312,15 @@
23811                 QueueRlmtPortTrap(pAC, OID_SKGE_TRAP_RLMT_PORT_UP, PhysPortIndex);
23812                 (void)SK_DRIVER_SENDEVENT(pAC, IoC);
23813
23814 -               /* Bugfix for XMAC errata (#10620)*/
23815 +               /* Bugfix for XMAC errata (#10620). */
23816                 if (MacType == SK_MAC_XMAC) {
23817 -                       /* Add incremental difference to offset (#10620)*/
23818 +                       /* Add incremental difference to offset (#10620). */
23819                         (void)pAC->GIni.GIFunc.pFnMacStatistic(pAC, IoC, PhysPortIndex,
23820                                 XM_RXE_SHT_ERR, &Val32);
23821
23822                         Value = (((SK_U64)pAC->Pnmi.Port[PhysPortIndex].
23823                                  CounterHigh[SK_PNMI_HRX_SHORTS] << 32) | (SK_U64)Val32);
23824 +
23825                         pAC->Pnmi.Port[PhysPortIndex].CounterOffset[SK_PNMI_HRX_SHORTS] +=
23826                                 Value - pAC->Pnmi.Port[PhysPortIndex].RxShortZeroMark;
23827                 }
23828 @@ -1399,7 +1350,7 @@
23829                 QueueRlmtPortTrap(pAC, OID_SKGE_TRAP_RLMT_PORT_DOWN, PhysPortIndex);
23830                 (void)SK_DRIVER_SENDEVENT(pAC, IoC);
23831
23832 -               /* Bugfix #10620 - get zero level for incremental difference */
23833 +               /* Bugfix #10620 - get zero level for incremental difference. */
23834                 if (MacType == SK_MAC_XMAC) {
23835
23836                         (void)pAC->GIni.GIFunc.pFnMacStatistic(pAC, IoC, PhysPortIndex,
23837 @@ -1431,17 +1382,13 @@
23838                 }
23839  #endif /* DEBUG */
23840
23841 -               /*
23842 -                * For now, ignore event if NetIndex != 0.
23843 -                */
23844 +               /* For now, ignore event if NetIndex != 0. */
23845                 if (Param.Para32[1] != 0) {
23846
23847                         return (0);
23848                 }
23849
23850 -               /*
23851 -                * Nothing to do if port is already inactive
23852 -                */
23853 +               /* Nothing to do if port is already inactive. */
23854                 if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
23855
23856                         return (0);
23857 @@ -1472,7 +1419,6 @@
23858                         CounterIndex ++) {
23859
23860                         if (!StatAddr[CounterIndex][MacType].GetOffset) {
23861 -
23862                                 continue;
23863                         }
23864
23865 @@ -1481,9 +1427,7 @@
23866                         pAC->Pnmi.VirtualCounterOffset[CounterIndex] += Value;
23867                 }
23868
23869 -               /*
23870 -                * Set port to inactive
23871 -                */
23872 +               /* Set port to inactive. */
23873                 pAC->Pnmi.Port[PhysPortIndex].ActiveFlag = SK_FALSE;
23874
23875                 pAC->Pnmi.MacUpdatedFlag --;
23876 @@ -1509,25 +1453,19 @@
23877                 }
23878  #endif /* DEBUG */
23879
23880 -               /*
23881 -                * For now, ignore event if NetIndex != 0.
23882 -                */
23883 +               /* For now, ignore event if NetIndex != 0. */
23884                 if (Param.Para32[1] != 0) {
23885
23886                         return (0);
23887                 }
23888
23889 -               /*
23890 -                * Nothing to do if port is already active
23891 -                */
23892 +               /* Nothing to do if port is already inactive. */
23893                 if (pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
23894
23895                         return (0);
23896                 }
23897
23898 -               /*
23899 -                * Statistic maintenance
23900 -                */
23901 +               /* Statistic maintenance. */
23902                 pAC->Pnmi.RlmtChangeCts ++;
23903                 pAC->Pnmi.RlmtChangeTime = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC));
23904
23905 @@ -1561,7 +1499,6 @@
23906                         CounterIndex ++) {
23907
23908                         if (!StatAddr[CounterIndex][MacType].GetOffset) {
23909 -
23910                                 continue;
23911                         }
23912
23913 @@ -1570,16 +1507,14 @@
23914                         pAC->Pnmi.VirtualCounterOffset[CounterIndex] -= Value;
23915                 }
23916
23917 -               /* Set port to active */
23918 +               /* Set port to active. */
23919                 pAC->Pnmi.Port[PhysPortIndex].ActiveFlag = SK_TRUE;
23920
23921                 pAC->Pnmi.MacUpdatedFlag --;
23922                 break;
23923
23924         case SK_PNMI_EVT_RLMT_SEGMENTATION:
23925 -               /*
23926 -                * Para.Para32[0] contains the NetIndex.
23927 -                */
23928 +               /* Para.Para32[0] contains the NetIndex. */
23929
23930                 /*
23931                  * Store a trap message in the trap buffer and generate an event for
23932 @@ -1594,71 +1529,53 @@
23933                  *  Param.Para32[0] contains the number of Nets.
23934                  *  Param.Para32[1] is reserved, contains -1.
23935                  */
23936 -           /*
23937 -        * Check number of nets
23938 -                */
23939 +           /* Check number of nets. */
23940                 MaxNetNumber = pAC->GIni.GIMacsFound;
23941 -               if (((unsigned int)Param.Para32[0] < 1)
23942 -                       || ((unsigned int)Param.Para32[0] > MaxNetNumber)) {
23943 +
23944 +               if (((unsigned int)Param.Para32[0] < 1) ||
23945 +                       ((unsigned int)Param.Para32[0] > MaxNetNumber)) {
23946 +
23947                         return (SK_PNMI_ERR_UNKNOWN_NET);
23948                 }
23949
23950 -        if ((unsigned int)Param.Para32[0] == 1) { /* single net mode */
23951 +        if ((unsigned int)Param.Para32[0] == 1) { /* SingleNet mode. */
23952                 pAC->Pnmi.DualNetActiveFlag = SK_FALSE;
23953          }
23954 -        else { /* dual net mode */
23955 +        else { /* DualNet mode. */
23956                 pAC->Pnmi.DualNetActiveFlag = SK_TRUE;
23957          }
23958          break;
23959
23960      case SK_PNMI_EVT_VCT_RESET:
23961                 PhysPortIndex = Param.Para32[0];
23962 -               pPrt = &pAC->GIni.GP[PhysPortIndex];
23963 -               pVctBackupData = &pAC->Pnmi.VctBackup[PhysPortIndex];
23964
23965                 if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_PENDING) {
23966 +
23967                         RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_FALSE);
23968 +
23969                         if (RetCode == 2) {
23970                                 /*
23971                                  * VCT test is still running.
23972                                  * Start VCT timer counter again.
23973                                  */
23974 -                               SK_MEMSET((char *) &Param, 0, sizeof(Param));
23975 +                               SK_MEMSET((char *)&Param, 0, sizeof(Param));
23976 +
23977                                 Param.Para32[0] = PhysPortIndex;
23978                                 Param.Para32[1] = -1;
23979 -                               SkTimerStart(pAC, IoC,
23980 -                                       &pAC->Pnmi.VctTimeout[PhysPortIndex].VctTimer,
23981 -                               4000000, SKGE_PNMI, SK_PNMI_EVT_VCT_RESET, Param);
23982 +
23983 +                               SkTimerStart(pAC, IoC, &pAC->Pnmi.VctTimeout[PhysPortIndex],
23984 +                                       SK_PNMI_VCT_TIMER_CHECK, SKGE_PNMI, SK_PNMI_EVT_VCT_RESET, Param);
23985 +
23986                                 break;
23987                         }
23988 -                       pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_PENDING;
23989 -                       pAC->Pnmi.VctStatus[PhysPortIndex] |=
23990 -                               (SK_PNMI_VCT_NEW_VCT_DATA | SK_PNMI_VCT_TEST_DONE);
23991
23992 -                       /* Copy results for later use to PNMI struct. */
23993 -                       for (i = 0; i < 4; i++)  {
23994 -                               if (pPrt->PMdiPairSts[i] == SK_PNMI_VCT_NORMAL_CABLE) {
23995 -                                       if ((pPrt->PMdiPairLen[i] > 35) &&
23996 -                                               (pPrt->PMdiPairLen[i] < 0xff)) {
23997 -                                               pPrt->PMdiPairSts[i] = SK_PNMI_VCT_IMPEDANCE_MISMATCH;
23998 -                                       }
23999 -                               }
24000 -                               if ((pPrt->PMdiPairLen[i] > 35) &&
24001 -                                       (pPrt->PMdiPairLen[i] != 0xff)) {
24002 -                                       CableLength = 1000 *
24003 -                                               (((175 * pPrt->PMdiPairLen[i]) / 210) - 28);
24004 -                               }
24005 -                               else {
24006 -                                       CableLength = 0;
24007 -                               }
24008 -                               pVctBackupData->PMdiPairLen[i] = CableLength;
24009 -                               pVctBackupData->PMdiPairSts[i] = pPrt->PMdiPairSts[i];
24010 -                       }
24011 +                       VctGetResults(pAC, IoC, PhysPortIndex);
24012
24013 -                       Param.Para32[0] = PhysPortIndex;
24014 -                       Param.Para32[1] = -1;
24015 -                       SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Param);
24016 -                       SkEventDispatcher(pAC, IoC);
24017 +                       EventParam.Para32[0] = PhysPortIndex;
24018 +                       EventParam.Para32[1] = -1;
24019 +                       SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, EventParam);
24020 +
24021 +                       /* SkEventDispatcher(pAC, IoC); */
24022                 }
24023
24024                 break;
24025 @@ -1706,14 +1623,13 @@
24026         unsigned int    TableIndex;
24027         int             Ret;
24028
24029 -
24030         if ((TableIndex = LookupId(Id)) == (unsigned int)(-1)) {
24031
24032                 *pLen = 0;
24033                 return (SK_PNMI_ERR_UNKNOWN_OID);
24034         }
24035
24036 -    /* Check NetIndex */
24037 +    /* Check NetIndex. */
24038         if (NetIndex >= pAC->Rlmt.NumNets) {
24039                 return (SK_PNMI_ERR_UNKNOWN_NET);
24040         }
24041 @@ -1763,22 +1679,20 @@
24042         SK_U32          Instance;
24043         SK_U32          Id;
24044
24045 -
24046 -       /* Check if the passed buffer has the right size */
24047 +       /* Check if the passed buffer has the right size. */
24048         if (*pLen < SK_PNMI_STRUCT_SIZE) {
24049
24050 -               /* Check if we can return the error within the buffer */
24051 +               /* Check if we can return the error within the buffer. */
24052                 if (*pLen >= SK_PNMI_MIN_STRUCT_SIZE) {
24053
24054 -                       SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_TOO_SHORT,
24055 -                               (SK_U32)(-1));
24056 +                       SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_TOO_SHORT, (SK_U32)(-1));
24057                 }
24058
24059                 *pLen = SK_PNMI_STRUCT_SIZE;
24060                 return (SK_PNMI_ERR_TOO_SHORT);
24061         }
24062
24063 -    /* Check NetIndex */
24064 +    /* Check NetIndex. */
24065         if (NetIndex >= pAC->Rlmt.NumNets) {
24066                 return (SK_PNMI_ERR_UNKNOWN_NET);
24067         }
24068 @@ -1806,12 +1720,11 @@
24069         pAC->Pnmi.RlmtUpdatedFlag ++;
24070         pAC->Pnmi.SirqUpdatedFlag ++;
24071
24072 -       /* Preset/Set values */
24073 +       /* PRESET/SET values. */
24074         for (TableIndex = 0; TableIndex < ID_TABLE_SIZE; TableIndex ++) {
24075
24076                 if ((IdTable[TableIndex].Access != SK_PNMI_RW) &&
24077                         (IdTable[TableIndex].Access != SK_PNMI_WO)) {
24078 -
24079                         continue;
24080                 }
24081
24082 @@ -1822,8 +1735,7 @@
24083                         InstanceCnt ++) {
24084
24085                         DstOffset = IdTable[TableIndex].Offset +
24086 -                               (InstanceCnt - 1) *
24087 -                               IdTable[TableIndex].StructSize;
24088 +                               (InstanceCnt - 1) * IdTable[TableIndex].StructSize;
24089
24090                         /*
24091                          * Because VPD multiple instance variables are
24092 @@ -1833,9 +1745,7 @@
24093                          */
24094                         Instance = (SK_U32)InstanceCnt;
24095
24096 -                       /*
24097 -                        * Evaluate needed buffer length
24098 -                        */
24099 +                       /* Evaluate needed buffer length. */
24100                         Len = 0;
24101                         Ret = IdTable[TableIndex].Func(pAC, IoC,
24102                                 SK_PNMI_GET, IdTable[TableIndex].Id,
24103 @@ -1851,8 +1761,7 @@
24104                                 pAC->Pnmi.SirqUpdatedFlag --;
24105
24106                                 SK_PNMI_CHECKFLAGS("PnmiStruct: On return");
24107 -                               SK_PNMI_SET_STAT(pBuf,
24108 -                                       SK_PNMI_ERR_GENERAL, DstOffset);
24109 +                               SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_GENERAL, DstOffset);
24110                                 *pLen = SK_PNMI_MIN_STRUCT_SIZE;
24111                                 return (SK_PNMI_ERR_GENERAL);
24112                         }
24113 @@ -1874,7 +1783,7 @@
24114                                 }
24115                         }
24116
24117 -                       /* Call the OID handler function */
24118 +                       /* Call the OID handler function. */
24119                         Ret = IdTable[TableIndex].Func(pAC, IoC, Action,
24120                                 IdTable[TableIndex].Id, pBuf + DstOffset,
24121                                 &Len, Instance, TableIndex, NetIndex);
24122 @@ -1885,8 +1794,7 @@
24123                                 pAC->Pnmi.SirqUpdatedFlag --;
24124
24125                                 SK_PNMI_CHECKFLAGS("PnmiStruct: On return");
24126 -                               SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_BAD_VALUE,
24127 -                                       DstOffset);
24128 +                               SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_BAD_VALUE, DstOffset);
24129                                 *pLen = SK_PNMI_MIN_STRUCT_SIZE;
24130                                 return (SK_PNMI_ERR_BAD_VALUE);
24131                         }
24132 @@ -1920,7 +1828,7 @@
24133
24134                 if (IdTable[i].Id == Id) {
24135
24136 -                       return i;
24137 +                       return (i);
24138                 }
24139         }
24140
24141 @@ -1961,16 +1869,13 @@
24142  {
24143         if (Id != OID_SKGE_ALL_DATA) {
24144
24145 -               SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR003,
24146 -                       SK_PNMI_ERR003MSG);
24147 +               SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR003, SK_PNMI_ERR003MSG);
24148
24149                 *pLen = 0;
24150                 return (SK_PNMI_ERR_GENERAL);
24151         }
24152
24153 -       /*
24154 -        * Check instance. We only handle single instance variables
24155 -        */
24156 +       /* Check instance. We only handle single instance variables. */
24157         if (Instance != (SK_U32)(-1) && Instance != 1) {
24158
24159                 *pLen = 0;
24160 @@ -2029,10 +1934,7 @@
24161         int     Ret;
24162         SK_U32  ActionOp;
24163
24164 -
24165 -       /*
24166 -        * Check instance. We only handle single instance variables
24167 -        */
24168 +       /* Check instance. We only handle single instance variables. */
24169         if (Instance != (SK_U32)(-1) && Instance != 1) {
24170
24171                 *pLen = 0;
24172 @@ -2045,10 +1947,10 @@
24173                 return (SK_PNMI_ERR_TOO_SHORT);
24174         }
24175
24176 -       /* Check if a get should be performed */
24177 +       /* Check if a GET should be performed. */
24178         if (Action == SK_PNMI_GET) {
24179
24180 -               /* A get is easy. We always return the same value */
24181 +               /* A GET is easy. We always return the same value. */
24182                 ActionOp = (SK_U32)SK_PNMI_ACT_IDLE;
24183                 SK_PNMI_STORE_U32(pBuf, ActionOp);
24184                 *pLen = sizeof(SK_U32);
24185 @@ -2056,13 +1958,13 @@
24186                 return (SK_PNMI_ERR_OK);
24187         }
24188
24189 -       /* Continue with PRESET/SET action */
24190 +       /* Continue with PRESET/SET action. */
24191         if (*pLen > sizeof(SK_U32)) {
24192
24193                 return (SK_PNMI_ERR_BAD_VALUE);
24194         }
24195
24196 -       /* Check if the command is a known one */
24197 +       /* Check if the command is a known one. */
24198         SK_PNMI_READ_U32(pBuf, ActionOp);
24199         if (*pLen > sizeof(SK_U32) ||
24200                 (ActionOp != SK_PNMI_ACT_IDLE &&
24201 @@ -2074,7 +1976,7 @@
24202                 return (SK_PNMI_ERR_BAD_VALUE);
24203         }
24204
24205 -       /* A preset ends here */
24206 +       /* A PRESET ends here. */
24207         if (Action == SK_PNMI_PRESET) {
24208
24209                 return (SK_PNMI_ERR_OK);
24210 @@ -2083,19 +1985,15 @@
24211         switch (ActionOp) {
24212
24213         case SK_PNMI_ACT_IDLE:
24214 -               /* Nothing to do */
24215 +               /* Nothing to do. */
24216                 break;
24217
24218         case SK_PNMI_ACT_RESET:
24219 -               /*
24220 -                * Perform a driver reset or something that comes near
24221 -                * to this.
24222 -                */
24223 +               /* Perform a driver reset or something that comes near to this. */
24224                 Ret = SK_DRIVER_RESET(pAC, IoC);
24225                 if (Ret != 0) {
24226
24227 -                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR005,
24228 -                               SK_PNMI_ERR005MSG);
24229 +                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR005, SK_PNMI_ERR005MSG);
24230
24231                         return (SK_PNMI_ERR_GENERAL);
24232                 }
24233 @@ -2112,13 +2010,12 @@
24234                 break;
24235
24236         case SK_PNMI_ACT_RESETCNT:
24237 -               /* Set all counters and timestamps to zero */
24238 +               /* Set all counters and timestamps to zero. */
24239                 ResetCounter(pAC, IoC, NetIndex);
24240                 break;
24241
24242         default:
24243 -               SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR006,
24244 -                       SK_PNMI_ERR006MSG);
24245 +               SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR006, SK_PNMI_ERR006MSG);
24246
24247                 return (SK_PNMI_ERR_GENERAL);
24248         }
24249 @@ -2162,25 +2059,21 @@
24250         SK_U32  StatVal32;
24251         SK_BOOL Is64BitReq = SK_FALSE;
24252
24253 -       /*
24254 -        * Only the active Mac is returned
24255 -        */
24256 +       /* Only the active MAC is returned. */
24257         if (Instance != (SK_U32)(-1) && Instance != 1) {
24258
24259                 *pLen = 0;
24260                 return (SK_PNMI_ERR_UNKNOWN_INST);
24261         }
24262
24263 -       /*
24264 -        * Check action type
24265 -        */
24266 +       /* Check action type. */
24267         if (Action != SK_PNMI_GET) {
24268
24269                 *pLen = 0;
24270                 return (SK_PNMI_ERR_READ_ONLY);
24271         }
24272
24273 -       /* Check length */
24274 +       /* Check length. */
24275         switch (Id) {
24276
24277         case OID_802_3_PERMANENT_ADDRESS:
24278 @@ -2201,12 +2094,12 @@
24279
24280  #else /* SK_NDIS_64BIT_CTR */
24281
24282 -               /* for compatibility, at least 32bit are required for OID */
24283 +               /* For compatibility, at least 32 bits are required for OID. */
24284                 if (*pLen < sizeof(SK_U32)) {
24285                         /*
24286 -                       * but indicate handling for 64bit values,
24287 -                       * if insufficient space is provided
24288 -                       */
24289 +                        * Indicate handling for 64 bit values,
24290 +                        * if insufficient space is provided.
24291 +                        */
24292                         *pLen = sizeof(SK_U64);
24293                         return (SK_PNMI_ERR_TOO_SHORT);
24294                 }
24295 @@ -2222,16 +2115,14 @@
24296          * to indicate that an update was already done.
24297          */
24298         Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1);
24299 -       if ( Ret != SK_PNMI_ERR_OK) {
24300 +       if (Ret != SK_PNMI_ERR_OK) {
24301
24302                 *pLen = 0;
24303                 return (Ret);
24304         }
24305         pAC->Pnmi.MacUpdatedFlag ++;
24306
24307 -       /*
24308 -        * Get value (MAC Index 0 identifies the virtual MAC)
24309 -        */
24310 +       /* Get value (MAC index 0 identifies the virtual MAC). */
24311         switch (Id) {
24312
24313         case OID_802_3_PERMANENT_ADDRESS:
24314 @@ -2247,7 +2138,7 @@
24315         default:
24316                 StatVal = GetStatVal(pAC, IoC, 0, IdTable[TableIndex].Param, NetIndex);
24317
24318 -               /* by default 32bit values are evaluated */
24319 +               /* By default 32 bit values are evaluated. */
24320                 if (!Is64BitReq) {
24321                         StatVal32 = (SK_U32)StatVal;
24322                         SK_PNMI_STORE_U32(pBuf, StatVal32);
24323 @@ -2301,21 +2192,19 @@
24324         int                             MacType;
24325         int                             Ret;
24326         SK_U64                  StatVal;
24327 -
24328 -
24329
24330 -       /* Calculate instance if wished. MAC index 0 is the virtual MAC */
24331 +       /* Calculate instance if wished. MAC index 0 is the virtual MAC. */
24332         PhysPortMax = pAC->GIni.GIMacsFound;
24333         LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax);
24334
24335         MacType = pAC->GIni.GIMacType;
24336
24337 -       if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* Dual net mode */
24338 +       if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* DualNet mode. */
24339                 LogPortMax--;
24340         }
24341
24342 -       if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried */
24343 -               /* Check instance range */
24344 +       if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried. */
24345 +               /* Check instance range. */
24346                 if ((Instance < 1) || (Instance > LogPortMax)) {
24347
24348                         *pLen = 0;
24349 @@ -2325,20 +2214,20 @@
24350                 Limit = LogPortIndex + 1;
24351         }
24352
24353 -       else { /* Instance == (SK_U32)(-1), get all Instances of that OID */
24354 +       else { /* Instance == (SK_U32)(-1), get all Instances of that OID. */
24355
24356                 LogPortIndex = 0;
24357                 Limit = LogPortMax;
24358         }
24359
24360 -       /* Check action */
24361 +       /* Check action. */
24362         if (Action != SK_PNMI_GET) {
24363
24364                 *pLen = 0;
24365                 return (SK_PNMI_ERR_READ_ONLY);
24366         }
24367
24368 -       /* Check length */
24369 +       /* Check length. */
24370         if (*pLen < (Limit - LogPortIndex) * sizeof(SK_U64)) {
24371
24372                 *pLen = (Limit - LogPortIndex) * sizeof(SK_U64);
24373 @@ -2357,7 +2246,7 @@
24374         }
24375         pAC->Pnmi.MacUpdatedFlag ++;
24376
24377 -       /* Get value */
24378 +       /* Get value. */
24379         Offset = 0;
24380         for (; LogPortIndex < Limit; LogPortIndex ++) {
24381
24382 @@ -2463,19 +2352,16 @@
24383         unsigned int    Limit;
24384         unsigned int    Offset = 0;
24385
24386 -       /*
24387 -        * Calculate instance if wished. MAC index 0 is the virtual
24388 -        * MAC.
24389 -        */
24390 +       /* Calculate instance if wished. MAC index 0 is the virtual MAC. */
24391         PhysPortMax = pAC->GIni.GIMacsFound;
24392         LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax);
24393
24394 -       if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* Dual net mode */
24395 +       if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* DualNet mode. */
24396                 LogPortMax--;
24397         }
24398
24399 -       if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried */
24400 -               /* Check instance range */
24401 +       if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried. */
24402 +               /* Check instance range. */
24403                 if ((Instance < 1) || (Instance > LogPortMax)) {
24404
24405                         *pLen = 0;
24406 @@ -2484,27 +2370,23 @@
24407                 LogPortIndex = SK_PNMI_PORT_INST2LOG(Instance);
24408                 Limit = LogPortIndex + 1;
24409         }
24410 -       else { /* Instance == (SK_U32)(-1), get all Instances of that OID */
24411 +       else { /* Instance == (SK_U32)(-1), get all Instances of that OID. */
24412
24413                 LogPortIndex = 0;
24414                 Limit = LogPortMax;
24415         }
24416
24417 -       /*
24418 -        * Perform Action
24419 -        */
24420 +       /* Perform action. */
24421         if (Action == SK_PNMI_GET) {
24422
24423 -               /* Check length */
24424 +               /* Check length. */
24425                 if (*pLen < (Limit - LogPortIndex) * 6) {
24426
24427                         *pLen = (Limit - LogPortIndex) * 6;
24428                         return (SK_PNMI_ERR_TOO_SHORT);
24429                 }
24430
24431 -               /*
24432 -                * Get value
24433 -                */
24434 +               /* Get value. */
24435                 for (; LogPortIndex < Limit; LogPortIndex ++) {
24436
24437                         switch (Id) {
24438 @@ -2528,8 +2410,7 @@
24439                                                 &pAC->Addr.Net[NetIndex].PermanentMacAddress);
24440                                 }
24441                                 else {
24442 -                                       PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
24443 -                                               pAC, LogPortIndex);
24444 +                                       PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);
24445
24446                                         CopyMac(pBuf + Offset,
24447                                                 &pAC->Addr.Port[PhysPortIndex].PermanentMacAddress);
24448 @@ -2538,8 +2419,7 @@
24449                                 break;
24450
24451                         default:
24452 -                               SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR008,
24453 -                                       SK_PNMI_ERR008MSG);
24454 +                               SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR008, SK_PNMI_ERR008MSG);
24455
24456                                 *pLen = 0;
24457                                 return (SK_PNMI_ERR_GENERAL);
24458 @@ -2550,8 +2430,8 @@
24459         }
24460         else {
24461                 /*
24462 -                * The logical MAC address may not be changed only
24463 -                * the physical ones
24464 +                * The logical MAC address may not be changed,
24465 +                * only the physical ones.
24466                  */
24467                 if (Id == OID_SKGE_PHYS_FAC_ADDR) {
24468
24469 @@ -2559,19 +2439,16 @@
24470                         return (SK_PNMI_ERR_READ_ONLY);
24471                 }
24472
24473 -               /*
24474 -                * Only the current address may be changed
24475 -                */
24476 +               /* Only the current address may be changed. */
24477                 if (Id != OID_SKGE_PHYS_CUR_ADDR) {
24478
24479 -                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR009,
24480 -                               SK_PNMI_ERR009MSG);
24481 +                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR009, SK_PNMI_ERR009MSG);
24482
24483                         *pLen = 0;
24484                         return (SK_PNMI_ERR_GENERAL);
24485                 }
24486
24487 -               /* Check length */
24488 +               /* Check length. */
24489                 if (*pLen < (Limit - LogPortIndex) * 6) {
24490
24491                         *pLen = (Limit - LogPortIndex) * 6;
24492 @@ -2583,32 +2460,26 @@
24493                         return (SK_PNMI_ERR_BAD_VALUE);
24494                 }
24495
24496 -               /*
24497 -                * Check Action
24498 -                */
24499 +               /* Check action. */
24500                 if (Action == SK_PNMI_PRESET) {
24501
24502                         *pLen = 0;
24503                         return (SK_PNMI_ERR_OK);
24504                 }
24505
24506 -               /*
24507 -                * Set OID_SKGE_MAC_CUR_ADDR
24508 -                */
24509 +               /* Set OID_SKGE_MAC_CUR_ADDR.  */
24510                 for (; LogPortIndex < Limit; LogPortIndex ++, Offset += 6) {
24511
24512                         /*
24513                          * A set to virtual port and set of broadcast
24514 -                        * address will be ignored
24515 +                        * address will be ignored.
24516                          */
24517                         if (LogPortIndex == 0 || SK_MEMCMP(pBuf + Offset,
24518                                 "\xff\xff\xff\xff\xff\xff", 6) == 0) {
24519 -
24520                                 continue;
24521                         }
24522
24523 -                       PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC,
24524 -                               LogPortIndex);
24525 +                       PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);
24526
24527                         Ret = SkAddrOverride(pAC, IoC, PhysPortIndex,
24528                                 (SK_MAC_ADDR *)(pBuf + Offset),
24529 @@ -2661,10 +2532,7 @@
24530         unsigned int    Offset = 0;
24531         SK_U64          StatVal;
24532
24533 -
24534 -       /*
24535 -        * Calculate instance if wished
24536 -        */
24537 +       /* Calculate instance if wished. */
24538         if (Instance != (SK_U32)(-1)) {
24539
24540                 if ((Instance < 1) || (Instance > SKCS_NUM_PROTOCOLS)) {
24541 @@ -2680,25 +2548,21 @@
24542                 Limit = SKCS_NUM_PROTOCOLS;
24543         }
24544
24545 -       /*
24546 -        * Check action
24547 -        */
24548 +       /* Check action. */
24549         if (Action != SK_PNMI_GET) {
24550
24551                 *pLen = 0;
24552                 return (SK_PNMI_ERR_READ_ONLY);
24553         }
24554
24555 -       /* Check length */
24556 +       /* Check length. */
24557         if (*pLen < (Limit - Index) * sizeof(SK_U64)) {
24558
24559                 *pLen = (Limit - Index) * sizeof(SK_U64);
24560                 return (SK_PNMI_ERR_TOO_SHORT);
24561         }
24562
24563 -       /*
24564 -        * Get value
24565 -        */
24566 +       /* Get value. */
24567         for (; Index < Limit; Index ++) {
24568
24569                 switch (Id) {
24570 @@ -2724,8 +2588,7 @@
24571                         break;
24572
24573                 default:
24574 -                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR010,
24575 -                               SK_PNMI_ERR010MSG);
24576 +                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR010, SK_PNMI_ERR010MSG);
24577
24578                         *pLen = 0;
24579                         return (SK_PNMI_ERR_GENERAL);
24580 @@ -2735,9 +2598,7 @@
24581                 Offset += sizeof(SK_U64);
24582         }
24583
24584 -       /*
24585 -        * Store used buffer space
24586 -        */
24587 +       /* Store used buffer space. */
24588         *pLen = Offset;
24589
24590         return (SK_PNMI_ERR_OK);
24591 @@ -2780,10 +2641,7 @@
24592         SK_U32          Val32;
24593         SK_U64          Val64;
24594
24595 -
24596 -       /*
24597 -        * Calculate instance if wished
24598 -        */
24599 +       /* Calculate instance if wished. */
24600         if ((Instance != (SK_U32)(-1))) {
24601
24602                 if ((Instance < 1) || (Instance > (SK_U32)pAC->I2c.MaxSens)) {
24603 @@ -2800,16 +2658,14 @@
24604                 Limit = (unsigned int) pAC->I2c.MaxSens;
24605         }
24606
24607 -       /*
24608 -        * Check action
24609 -        */
24610 +       /* Check action. */
24611         if (Action != SK_PNMI_GET) {
24612
24613                 *pLen = 0;
24614                 return (SK_PNMI_ERR_READ_ONLY);
24615         }
24616
24617 -       /* Check length */
24618 +       /* Check length. */
24619         switch (Id) {
24620
24621         case OID_SKGE_SENSOR_VALUE:
24622 @@ -2868,38 +2724,33 @@
24623                 break;
24624
24625         default:
24626 -               SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR012,
24627 -                       SK_PNMI_ERR012MSG);
24628 +               SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR012, SK_PNMI_ERR012MSG);
24629
24630                 *pLen = 0;
24631                 return (SK_PNMI_ERR_GENERAL);
24632
24633         }
24634
24635 -       /*
24636 -        * Get value
24637 -        */
24638 +       /* Get value. */
24639         for (Offset = 0; Index < Limit; Index ++) {
24640
24641                 switch (Id) {
24642
24643                 case OID_SKGE_SENSOR_INDEX:
24644                         *(pBuf + Offset) = (char)Index;
24645 -                       Offset += sizeof(char);
24646 +                       Offset ++;
24647                         break;
24648
24649                 case OID_SKGE_SENSOR_DESCR:
24650                         Len = SK_STRLEN(pAC->I2c.SenTable[Index].SenDesc);
24651 -                       SK_MEMCPY(pBuf + Offset + 1,
24652 -                               pAC->I2c.SenTable[Index].SenDesc, Len);
24653 +                       SK_MEMCPY(pBuf + Offset + 1, pAC->I2c.SenTable[Index].SenDesc, Len);
24654                         *(pBuf + Offset) = (char)Len;
24655                         Offset += Len + 1;
24656                         break;
24657
24658                 case OID_SKGE_SENSOR_TYPE:
24659 -                       *(pBuf + Offset) =
24660 -                               (char)pAC->I2c.SenTable[Index].SenType;
24661 -                       Offset += sizeof(char);
24662 +                       *(pBuf + Offset) = (char)pAC->I2c.SenTable[Index].SenType;
24663 +                       Offset ++;
24664                         break;
24665
24666                 case OID_SKGE_SENSOR_VALUE:
24667 @@ -2936,9 +2787,8 @@
24668                         break;
24669
24670                 case OID_SKGE_SENSOR_STATUS:
24671 -                       *(pBuf + Offset) =
24672 -                               (char)pAC->I2c.SenTable[Index].SenErrFlag;
24673 -                       Offset += sizeof(char);
24674 +                       *(pBuf + Offset) = (char)pAC->I2c.SenTable[Index].SenErrFlag;
24675 +                       Offset ++;
24676                         break;
24677
24678                 case OID_SKGE_SENSOR_WAR_CTS:
24679 @@ -2975,9 +2825,7 @@
24680                 }
24681         }
24682
24683 -       /*
24684 -        * Store used buffer space
24685 -        */
24686 +       /* Store used buffer space. */
24687         *pLen = Offset;
24688
24689         return (SK_PNMI_ERR_OK);
24690 @@ -3032,8 +2880,29 @@
24691         SK_U32          Val32;
24692
24693         /*
24694 -        * Get array of all currently stored VPD keys
24695 -        */
24696 +        * VpdKeyReadError will be set in GetVpdKeyArr() if an error occurs.
24697 +        * Due to the fact that some drivers use SkPnmiGetStruct() to retrieve
24698 +        * all statistical data, an error in GetVpdKeyArr() will generate a PNMI
24699 +        * error and terminate SkPnmiGetStruct() without filling in statistical
24700 +        * data into the PNMI struct. In this case the driver will get no values
24701 +        * for statistical purposes (netstat, ifconfig etc.). GetVpdKeyArr() is
24702 +        * the first function to be called in SkPnmiGetStruct(), so any error
24703 +        * will terminate SkPnmiGetStruct() immediately. Hence, VpdKeyReadError will
24704 +        * be set during the first call to GetVpdKeyArr() to make successful calls
24705 +        * to SkPnmiGetStruct() possible. But there is another point to consider:
24706 +        * When filling in the statistical data into the PNMI struct, the VPD
24707 +        * handler Vpd() will also be called. If GetVpdKeyArr() in Vpd() would
24708 +        * return with SK_PNMI_ERR_GENERAL, SkPnmiGetStruct() would fail again.
24709 +        * For this reason VpdKeyReadError is checked here and, if set, Vpd()
24710 +        * will return without doing anything and the return value SK_PNMI_ERR_OK.
24711 +        * Therefore SkPnmiGetStruct() is able to continue and fill in all other
24712 +        * statistical data.
24713 +        */
24714 +       if (pAC->Pnmi.VpdKeyReadError == SK_TRUE) {
24715 +               return (SK_PNMI_ERR_OK);
24716 +       }
24717 +
24718 +       /* Get array of all currently stored VPD keys. */
24719         Ret = GetVpdKeyArr(pAC, IoC, &KeyArr[0][0], sizeof(KeyArr), &KeyNo);
24720         if (Ret != SK_PNMI_ERR_OK) {
24721                 *pLen = 0;
24722 @@ -3078,34 +2947,32 @@
24723                 }
24724         }
24725
24726 -       /*
24727 -        * Get value, if a query should be performed
24728 -        */
24729 +       /* Get value, if a query should be performed. */
24730         if (Action == SK_PNMI_GET) {
24731
24732                 switch (Id) {
24733
24734                 case OID_SKGE_VPD_FREE_BYTES:
24735 -                       /* Check length of buffer */
24736 +                       /* Check length of buffer. */
24737                         if (*pLen < sizeof(SK_U32)) {
24738
24739                                 *pLen = sizeof(SK_U32);
24740                                 return (SK_PNMI_ERR_TOO_SHORT);
24741                         }
24742 -                       /* Get number of free bytes */
24743 +                       /* Get number of free bytes. */
24744                         pVpdStatus = VpdStat(pAC, IoC);
24745                         if (pVpdStatus == NULL) {
24746
24747 -                               SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR017,
24748 -                                       SK_PNMI_ERR017MSG);
24749 +                               SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
24750 +                                       (SK_PNMI_ERR017MSG));
24751
24752                                 *pLen = 0;
24753                                 return (SK_PNMI_ERR_GENERAL);
24754                         }
24755                         if ((pVpdStatus->vpd_status & VPD_VALID) == 0) {
24756
24757 -                               SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR018,
24758 -                                       SK_PNMI_ERR018MSG);
24759 +                               SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
24760 +                                       (SK_PNMI_ERR018MSG));
24761
24762                                 *pLen = 0;
24763                                 return (SK_PNMI_ERR_GENERAL);
24764 @@ -3117,7 +2984,7 @@
24765                         break;
24766
24767                 case OID_SKGE_VPD_ENTRIES_LIST:
24768 -                       /* Check length */
24769 +                       /* Check length. */
24770                         for (Len = 0, Index = 0; Index < KeyNo; Index ++) {
24771
24772                                 Len += SK_STRLEN(KeyArr[Index]) + 1;
24773 @@ -3128,7 +2995,7 @@
24774                                 return (SK_PNMI_ERR_TOO_SHORT);
24775                         }
24776
24777 -                       /* Get value */
24778 +                       /* Get value. */
24779                         *(pBuf) = (char)Len - 1;
24780                         for (Offset = 1, Index = 0; Index < KeyNo; Index ++) {
24781
24782 @@ -3147,7 +3014,7 @@
24783                         break;
24784
24785                 case OID_SKGE_VPD_ENTRIES_NUMBER:
24786 -                       /* Check length */
24787 +                       /* Check length. */
24788                         if (*pLen < sizeof(SK_U32)) {
24789
24790                                 *pLen = sizeof(SK_U32);
24791 @@ -3160,7 +3027,7 @@
24792                         break;
24793
24794                 case OID_SKGE_VPD_KEY:
24795 -                       /* Check buffer length, if it is large enough */
24796 +                       /* Check buffer length, if it is large enough. */
24797                         for (Len = 0, Index = FirstIndex;
24798                                 Index < LastIndex; Index ++) {
24799
24800 @@ -3176,32 +3043,28 @@
24801                          * Get the key to an intermediate buffer, because
24802                          * we have to prepend a length byte.
24803                          */
24804 -                       for (Offset = 0, Index = FirstIndex;
24805 -                               Index < LastIndex; Index ++) {
24806 +                       for (Offset = 0, Index = FirstIndex; Index < LastIndex; Index ++) {
24807
24808                                 Len = SK_STRLEN(KeyArr[Index]);
24809
24810                                 *(pBuf + Offset) = (char)Len;
24811 -                               SK_MEMCPY(pBuf + Offset + 1, KeyArr[Index],
24812 -                                       Len);
24813 +                               SK_MEMCPY(pBuf + Offset + 1, KeyArr[Index], Len);
24814                                 Offset += Len + 1;
24815                         }
24816                         *pLen = Offset;
24817                         break;
24818
24819                 case OID_SKGE_VPD_VALUE:
24820 -                       /* Check the buffer length if it is large enough */
24821 -                       for (Offset = 0, Index = FirstIndex;
24822 -                               Index < LastIndex; Index ++) {
24823 +                       /* Check the buffer length if it is large enough. */
24824 +                       for (Offset = 0, Index = FirstIndex; Index < LastIndex; Index ++) {
24825
24826                                 BufLen = 256;
24827                                 if (VpdRead(pAC, IoC, KeyArr[Index], Buf,
24828                                         (int *)&BufLen) > 0 ||
24829                                         BufLen >= SK_PNMI_VPD_DATALEN) {
24830
24831 -                                       SK_ERR_LOG(pAC, SK_ERRCL_SW,
24832 -                                               SK_PNMI_ERR021,
24833 -                                               SK_PNMI_ERR021MSG);
24834 +                                       SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
24835 +                                               (SK_PNMI_ERR021MSG));
24836
24837                                         return (SK_PNMI_ERR_GENERAL);
24838                                 }
24839 @@ -3217,17 +3080,15 @@
24840                          * Get the value to an intermediate buffer, because
24841                          * we have to prepend a length byte.
24842                          */
24843 -                       for (Offset = 0, Index = FirstIndex;
24844 -                               Index < LastIndex; Index ++) {
24845 +                       for (Offset = 0, Index = FirstIndex; Index < LastIndex; Index ++) {
24846
24847                                 BufLen = 256;
24848                                 if (VpdRead(pAC, IoC, KeyArr[Index], Buf,
24849                                         (int *)&BufLen) > 0 ||
24850                                         BufLen >= SK_PNMI_VPD_DATALEN) {
24851
24852 -                                       SK_ERR_LOG(pAC, SK_ERRCL_SW,
24853 -                                               SK_PNMI_ERR022,
24854 -                                               SK_PNMI_ERR022MSG);
24855 +                                       SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
24856 +                                               (SK_PNMI_ERR022MSG));
24857
24858                                         *pLen = 0;
24859                                         return (SK_PNMI_ERR_GENERAL);
24860 @@ -3247,8 +3108,7 @@
24861                                 return (SK_PNMI_ERR_TOO_SHORT);
24862                         }
24863
24864 -                       for (Offset = 0, Index = FirstIndex;
24865 -                               Index < LastIndex; Index ++) {
24866 +                       for (Offset = 0, Index = FirstIndex; Index < LastIndex; Index ++) {
24867
24868                                 if (VpdMayWrite(KeyArr[Index])) {
24869
24870 @@ -3274,15 +3134,15 @@
24871                         break;
24872
24873                 default:
24874 -                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR023,
24875 -                               SK_PNMI_ERR023MSG);
24876 +                       SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
24877 +                               (SK_PNMI_ERR023MSG));
24878
24879                         *pLen = 0;
24880                         return (SK_PNMI_ERR_GENERAL);
24881                 }
24882         }
24883         else {
24884 -               /* The only OID which can be set is VPD_ACTION */
24885 +               /* The only OID which can be set is VPD_ACTION. */
24886                 if (Id != OID_SKGE_VPD_ACTION) {
24887
24888                         if (Id == OID_SKGE_VPD_FREE_BYTES ||
24889 @@ -3296,8 +3156,8 @@
24890                                 return (SK_PNMI_ERR_READ_ONLY);
24891                         }
24892
24893 -                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR024,
24894 -                               SK_PNMI_ERR024MSG);
24895 +                       SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
24896 +                               (SK_PNMI_ERR024MSG));
24897
24898                         *pLen = 0;
24899                         return (SK_PNMI_ERR_GENERAL);
24900 @@ -3313,14 +3173,11 @@
24901                         return (SK_PNMI_ERR_TOO_SHORT);
24902                 }
24903
24904 -               /*
24905 -                * The first byte contains the VPD action type we should
24906 -                * perform.
24907 -                */
24908 +               /* The first byte contains the VPD action type we should perform. */
24909                 switch (*pBuf) {
24910
24911                 case SK_PNMI_VPD_IGNORE:
24912 -                       /* Nothing to do */
24913 +                       /* Nothing to do. */
24914                         break;
24915
24916                 case SK_PNMI_VPD_CREATE:
24917 @@ -3352,13 +3209,13 @@
24918                         SK_MEMCPY(Buf, pBuf + 4, Offset);
24919                         Buf[Offset] = 0;
24920
24921 -                       /* A preset ends here */
24922 +                       /* A PRESET ends here. */
24923                         if (Action == SK_PNMI_PRESET) {
24924
24925                                 return (SK_PNMI_ERR_OK);
24926                         }
24927
24928 -                       /* Write the new entry or modify an existing one */
24929 +                       /* Write the new entry or modify an existing one .*/
24930                         Ret = VpdWrite(pAC, IoC, KeyStr, Buf);
24931                         if (Ret == SK_PNMI_VPD_NOWRITE ) {
24932
24933 @@ -3367,8 +3224,8 @@
24934                         }
24935                         else if (Ret != SK_PNMI_VPD_OK) {
24936
24937 -                               SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR025,
24938 -                                       SK_PNMI_ERR025MSG);
24939 +                               SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
24940 +                                       (SK_PNMI_ERR025MSG));
24941
24942                                 *pLen = 0;
24943                                 return (SK_PNMI_ERR_GENERAL);
24944 @@ -3381,8 +3238,8 @@
24945                         Ret = VpdUpdate(pAC, IoC);
24946                         if (Ret != SK_PNMI_VPD_OK) {
24947
24948 -                               SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR026,
24949 -                                       SK_PNMI_ERR026MSG);
24950 +                               SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
24951 +                                       (SK_PNMI_ERR026MSG));
24952
24953                                 *pLen = 0;
24954                                 return (SK_PNMI_ERR_GENERAL);
24955 @@ -3390,7 +3247,7 @@
24956                         break;
24957
24958                 case SK_PNMI_VPD_DELETE:
24959 -                       /* Check if the buffer size is plausible */
24960 +                       /* Check if the buffer size is plausible. */
24961                         if (*pLen < 3) {
24962
24963                                 *pLen = 3;
24964 @@ -3405,7 +3262,7 @@
24965                         KeyStr[1] = pBuf[2];
24966                         KeyStr[2] = 0;
24967
24968 -                       /* Find the passed key in the array */
24969 +                       /* Find the passed key in the array. */
24970                         for (Index = 0; Index < KeyNo; Index ++) {
24971
24972                                 if (SK_STRCMP(KeyStr, KeyArr[Index]) == 0) {
24973 @@ -3413,6 +3270,7 @@
24974                                         break;
24975                                 }
24976                         }
24977 +
24978                         /*
24979                          * If we cannot find the key it is wrong, so we
24980                          * return an appropriate error value.
24981 @@ -3428,12 +3286,12 @@
24982                                 return (SK_PNMI_ERR_OK);
24983                         }
24984
24985 -                       /* Ok, you wanted it and you will get it */
24986 +                       /* Ok, you wanted it and you will get it. */
24987                         Ret = VpdDelete(pAC, IoC, KeyStr);
24988                         if (Ret != SK_PNMI_VPD_OK) {
24989
24990 -                               SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR027,
24991 -                                       SK_PNMI_ERR027MSG);
24992 +                               SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
24993 +                                       (SK_PNMI_ERR027MSG));
24994
24995                                 *pLen = 0;
24996                                 return (SK_PNMI_ERR_GENERAL);
24997 @@ -3446,8 +3304,8 @@
24998                         Ret = VpdUpdate(pAC, IoC);
24999                         if (Ret != SK_PNMI_VPD_OK) {
25000
25001 -                               SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR028,
25002 -                                       SK_PNMI_ERR028MSG);
25003 +                               SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
25004 +                                       (SK_PNMI_ERR028MSG));
25005
25006                                 *pLen = 0;
25007                                 return (SK_PNMI_ERR_GENERAL);
25008 @@ -3501,23 +3359,21 @@
25009         SK_U32          Val32;
25010         SK_U64          Val64;
25011         SK_U64          Val64RxHwErrs = 0;
25012 +       SK_U64          Val64RxRunt = 0;
25013 +       SK_U64          Val64RxFcs = 0;
25014         SK_U64          Val64TxHwErrs = 0;
25015         SK_BOOL         Is64BitReq = SK_FALSE;
25016         char            Buf[256];
25017         int                     MacType;
25018
25019 -       /*
25020 -        * Check instance. We only handle single instance variables.
25021 -        */
25022 +       /* Check instance. We only handle single instance variables. */
25023         if (Instance != (SK_U32)(-1) && Instance != 1) {
25024
25025                 *pLen = 0;
25026                 return (SK_PNMI_ERR_UNKNOWN_INST);
25027         }
25028
25029 -       /*
25030 -        * Check action. We only allow get requests.
25031 -        */
25032 +       /* Check action. We only allow get requests. */
25033         if (Action != SK_PNMI_GET) {
25034
25035                 *pLen = 0;
25036 @@ -3526,9 +3382,7 @@
25037
25038         MacType = pAC->GIni.GIMacType;
25039
25040 -       /*
25041 -        * Check length for the various supported OIDs
25042 -        */
25043 +       /* Check length for the various supported OIDs. */
25044         switch (Id) {
25045
25046         case OID_GEN_XMIT_ERROR:
25047 @@ -3542,14 +3396,12 @@
25048
25049  #else /* SK_NDIS_64BIT_CTR */
25050
25051 -               /*
25052 -                * for compatibility, at least 32bit are required for oid
25053 -                */
25054 +               /* For compatibility, at least 32bit are required for OID. */
25055                 if (*pLen < sizeof(SK_U32)) {
25056                         /*
25057 -                       * but indicate handling for 64bit values,
25058 -                       * if insufficient space is provided
25059 -                       */
25060 +                        * Indicate handling for 64bit values,
25061 +                        * if insufficient space is provided.
25062 +                        */
25063                         *pLen = sizeof(SK_U64);
25064                         return (SK_PNMI_ERR_TOO_SHORT);
25065                 }
25066 @@ -3620,11 +3472,11 @@
25067                 break;
25068
25069         default:
25070 -               /* Checked later */
25071 +               /* Checked later. */
25072                 break;
25073         }
25074
25075 -       /* Update statistic */
25076 +       /* Update statistics. */
25077         if (Id == OID_SKGE_RX_HW_ERROR_CTS ||
25078                 Id == OID_SKGE_TX_HW_ERROR_CTS ||
25079                 Id == OID_SKGE_IN_ERRORS_CTS ||
25080 @@ -3632,7 +3484,8 @@
25081                 Id == OID_GEN_XMIT_ERROR ||
25082                 Id == OID_GEN_RCV_ERROR) {
25083
25084 -               /* Force the XMAC to update its statistic counters and
25085 +               /*
25086 +                * Force the XMAC to update its statistic counters and
25087                  * Increment semaphore to indicate that an update was
25088                  * already done.
25089                  */
25090 @@ -3663,14 +3516,29 @@
25091                                 GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_IRLENGTH, NetIndex) +
25092                                 GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_SYMBOL, NetIndex) +
25093                                 GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_SHORTS, NetIndex) +
25094 -                               GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_RUNT, NetIndex) +
25095                                 GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_TOO_LONG, NetIndex) +
25096 -                               GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_FCS, NetIndex) +
25097                                 GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_CEXT, NetIndex);
25098 -               break;
25099
25100 -               case OID_SKGE_TX_HW_ERROR_CTS:
25101 -               case OID_SKGE_OUT_ERROR_CTS:
25102 +
25103 +                       /*
25104 +                       * In some cases the runt and fcs counters are incremented when collisions
25105 +                       * occur. We have to correct those counters here.
25106 +                       */
25107 +                       Val64RxRunt = GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_RUNT, NetIndex);
25108 +                       Val64RxFcs = GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_FCS, NetIndex);
25109 +
25110 +                       if (Val64RxRunt > Val64RxFcs) {
25111 +                               Val64RxRunt -= Val64RxFcs;
25112 +                               Val64RxHwErrs += Val64RxRunt;
25113 +                       }
25114 +                       else {
25115 +                               Val64RxFcs -= Val64RxRunt;
25116 +                               Val64RxHwErrs += Val64RxFcs;
25117 +                       }
25118 +                       break;
25119 +
25120 +               case OID_SKGE_TX_HW_ERROR_CTS:
25121 +               case OID_SKGE_OUT_ERROR_CTS:
25122                 case OID_GEN_XMIT_ERROR:
25123                         Val64TxHwErrs =
25124                                 GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_EXCESS_COL, NetIndex) +
25125 @@ -3681,9 +3549,7 @@
25126                 }
25127         }
25128
25129 -       /*
25130 -        * Retrieve value
25131 -        */
25132 +       /* Retrieve value. */
25133         switch (Id) {
25134
25135         case OID_SKGE_SUPPORTED_LIST:
25136 @@ -3693,11 +3559,11 @@
25137                         *pLen = Len;
25138                         return (SK_PNMI_ERR_TOO_SHORT);
25139                 }
25140 -               for (Offset = 0, Index = 0; Offset < Len;
25141 -                       Offset += sizeof(SK_U32), Index ++) {
25142 +               for (Offset = 0, Index = 0; Offset < Len; Index ++) {
25143
25144                         Val32 = (SK_U32)IdTable[Index].Id;
25145                         SK_PNMI_STORE_U32(pBuf + Offset, Val32);
25146 +                       Offset += sizeof(SK_U32);
25147                 }
25148                 *pLen = Len;
25149                 break;
25150 @@ -3723,8 +3589,7 @@
25151         case OID_SKGE_DRIVER_DESCR:
25152                 if (pAC->Pnmi.pDriverDescription == NULL) {
25153
25154 -                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR007,
25155 -                               SK_PNMI_ERR007MSG);
25156 +                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR007, SK_PNMI_ERR007MSG);
25157
25158                         *pLen = 0;
25159                         return (SK_PNMI_ERR_GENERAL);
25160 @@ -3733,8 +3598,7 @@
25161                 Len = SK_STRLEN(pAC->Pnmi.pDriverDescription) + 1;
25162                 if (Len > SK_PNMI_STRINGLEN1) {
25163
25164 -                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR029,
25165 -                               SK_PNMI_ERR029MSG);
25166 +                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR029, SK_PNMI_ERR029MSG);
25167
25168                         *pLen = 0;
25169                         return (SK_PNMI_ERR_GENERAL);
25170 @@ -3753,8 +3617,7 @@
25171         case OID_SKGE_DRIVER_VERSION:
25172                 if (pAC->Pnmi.pDriverVersion == NULL) {
25173
25174 -                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR030,
25175 -                               SK_PNMI_ERR030MSG);
25176 +                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR030, SK_PNMI_ERR030MSG);
25177
25178                         *pLen = 0;
25179                         return (SK_PNMI_ERR_GENERAL);
25180 @@ -3763,8 +3626,7 @@
25181                 Len = SK_STRLEN(pAC->Pnmi.pDriverVersion) + 1;
25182                 if (Len > SK_PNMI_STRINGLEN1) {
25183
25184 -                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR031,
25185 -                               SK_PNMI_ERR031MSG);
25186 +                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR031, SK_PNMI_ERR031MSG);
25187
25188                         *pLen = 0;
25189                         return (SK_PNMI_ERR_GENERAL);
25190 @@ -3783,8 +3645,7 @@
25191         case OID_SKGE_DRIVER_RELDATE:
25192                 if (pAC->Pnmi.pDriverReleaseDate == NULL) {
25193
25194 -                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR030,
25195 -                               SK_PNMI_ERR053MSG);
25196 +                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR053, SK_PNMI_ERR053MSG);
25197
25198                         *pLen = 0;
25199                         return (SK_PNMI_ERR_GENERAL);
25200 @@ -3793,8 +3654,7 @@
25201                 Len = SK_STRLEN(pAC->Pnmi.pDriverReleaseDate) + 1;
25202                 if (Len > SK_PNMI_STRINGLEN1) {
25203
25204 -                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR031,
25205 -                               SK_PNMI_ERR054MSG);
25206 +                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR054, SK_PNMI_ERR054MSG);
25207
25208                         *pLen = 0;
25209                         return (SK_PNMI_ERR_GENERAL);
25210 @@ -3813,8 +3673,7 @@
25211         case OID_SKGE_DRIVER_FILENAME:
25212                 if (pAC->Pnmi.pDriverFileName == NULL) {
25213
25214 -                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR030,
25215 -                               SK_PNMI_ERR055MSG);
25216 +                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR055, SK_PNMI_ERR055MSG);
25217
25218                         *pLen = 0;
25219                         return (SK_PNMI_ERR_GENERAL);
25220 @@ -3823,8 +3682,7 @@
25221                 Len = SK_STRLEN(pAC->Pnmi.pDriverFileName) + 1;
25222                 if (Len > SK_PNMI_STRINGLEN1) {
25223
25224 -                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR031,
25225 -                               SK_PNMI_ERR056MSG);
25226 +                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR056, SK_PNMI_ERR056MSG);
25227
25228                         *pLen = 0;
25229                         return (SK_PNMI_ERR_GENERAL);
25230 @@ -3846,12 +3704,16 @@
25231                  * query may move to the initialisation routine. But
25232                  * the VPD data is cached and therefore a call here
25233                  * will not make much difference.
25234 +                * Please read comment in Vpd().
25235                  */
25236 +               if (pAC->Pnmi.VpdKeyReadError == SK_TRUE) {
25237 +                       return (SK_PNMI_ERR_OK);
25238 +               }
25239 +
25240                 Len = 256;
25241                 if (VpdRead(pAC, IoC, VPD_NAME, Buf, (int *)&Len) > 0) {
25242
25243 -                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR032,
25244 -                               SK_PNMI_ERR032MSG);
25245 +                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR032, SK_PNMI_ERR032MSG);
25246
25247                         *pLen = 0;
25248                         return (SK_PNMI_ERR_GENERAL);
25249 @@ -3859,8 +3721,7 @@
25250                 Len ++;
25251                 if (Len > SK_PNMI_STRINGLEN1) {
25252
25253 -                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR033,
25254 -                               SK_PNMI_ERR033MSG);
25255 +                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR033, SK_PNMI_ERR033MSG);
25256
25257                         *pLen = 0;
25258                         return (SK_PNMI_ERR_GENERAL);
25259 @@ -3876,7 +3737,6 @@
25260                 break;
25261
25262         case OID_SKGE_HW_VERSION:
25263 -               /* Oh, I love to do some string manipulation */
25264                 if (*pLen < 5) {
25265
25266                         *pLen = 5;
25267 @@ -3885,9 +3745,9 @@
25268                 Val8 = (SK_U8)pAC->GIni.GIPciHwRev;
25269                 pBuf[0] = 4;
25270                 pBuf[1] = 'v';
25271 -               pBuf[2] = (char)(0x30 | ((Val8 >> 4) & 0x0F));
25272 +               pBuf[2] = (char)('0' | ((Val8 >> 4) & 0x0f));
25273                 pBuf[3] = '.';
25274 -               pBuf[4] = (char)(0x30 | (Val8 & 0x0F));
25275 +               pBuf[4] = (char)('0' | (Val8 & 0x0f));
25276                 *pLen = 5;
25277                 break;
25278
25279 @@ -3910,12 +3770,12 @@
25280                 break;
25281
25282         case OID_SKGE_VAUXAVAIL:
25283 -               *pBuf = (char) pAC->GIni.GIVauxAvail;
25284 +               *pBuf = (char)pAC->GIni.GIVauxAvail;
25285                 *pLen = sizeof(char);
25286                 break;
25287
25288         case OID_SKGE_BUS_TYPE:
25289 -               *pBuf = (char) SK_PNMI_BUS_PCI;
25290 +               *pBuf = (char)SK_PNMI_BUS_PCI;
25291                 *pLen = sizeof(char);
25292                 break;
25293
25294 @@ -3964,31 +3824,31 @@
25295                 break;
25296
25297         case OID_SKGE_RLMT_MONITOR_NUMBER:
25298 -/* XXX Not yet implemented by RLMT therefore we return zero elements */
25299 +               /* Not yet implemented by RLMT, therefore we return zero elements. */
25300                 Val32 = 0;
25301                 SK_PNMI_STORE_U32(pBuf, Val32);
25302                 *pLen = sizeof(SK_U32);
25303                 break;
25304
25305         case OID_SKGE_TX_SW_QUEUE_LEN:
25306 -               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25307 +               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25308                 if (MacType == SK_MAC_XMAC) {
25309 -                       /* Dual net mode */
25310 +                       /* DualNet mode. */
25311                         if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25312                                 Val64 = pAC->Pnmi.BufPort[NetIndex].TxSwQueueLen;
25313                         }
25314 -                       /* Single net mode */
25315 +                       /* SingleNet mode. */
25316                         else {
25317                                 Val64 = pAC->Pnmi.BufPort[0].TxSwQueueLen +
25318                                         pAC->Pnmi.BufPort[1].TxSwQueueLen;
25319                         }
25320                 }
25321                 else {
25322 -                       /* Dual net mode */
25323 +                       /* DualNet mode. */
25324                         if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25325                                 Val64 = pAC->Pnmi.Port[NetIndex].TxSwQueueLen;
25326                         }
25327 -                       /* Single net mode */
25328 +                       /* SingleNet mode. */
25329                         else {
25330                                 Val64 = pAC->Pnmi.Port[0].TxSwQueueLen +
25331                                         pAC->Pnmi.Port[1].TxSwQueueLen;
25332 @@ -4000,24 +3860,24 @@
25333
25334
25335         case OID_SKGE_TX_SW_QUEUE_MAX:
25336 -               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25337 +               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25338                 if (MacType == SK_MAC_XMAC) {
25339 -                       /* Dual net mode */
25340 +                       /* DualNet mode. */
25341                         if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25342                                 Val64 = pAC->Pnmi.BufPort[NetIndex].TxSwQueueMax;
25343                         }
25344 -                       /* Single net mode */
25345 +                       /* SingleNet mode. */
25346                         else {
25347                                 Val64 = pAC->Pnmi.BufPort[0].TxSwQueueMax +
25348                                         pAC->Pnmi.BufPort[1].TxSwQueueMax;
25349                         }
25350                 }
25351                 else {
25352 -                       /* Dual net mode */
25353 +                       /* DualNet mode. */
25354                         if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25355                                 Val64 = pAC->Pnmi.Port[NetIndex].TxSwQueueMax;
25356                         }
25357 -                       /* Single net mode */
25358 +                       /* SingleNet mode. */
25359                         else {
25360                                 Val64 = pAC->Pnmi.Port[0].TxSwQueueMax +
25361                                         pAC->Pnmi.Port[1].TxSwQueueMax;
25362 @@ -4028,24 +3888,24 @@
25363                 break;
25364
25365         case OID_SKGE_TX_RETRY:
25366 -               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25367 +               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25368                 if (MacType == SK_MAC_XMAC) {
25369 -                       /* Dual net mode */
25370 +                       /* DualNet mode. */
25371                         if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25372                                 Val64 = pAC->Pnmi.BufPort[NetIndex].TxRetryCts;
25373                         }
25374 -                       /* Single net mode */
25375 +                       /* SingleNet mode. */
25376                         else {
25377                                 Val64 = pAC->Pnmi.BufPort[0].TxRetryCts +
25378                                         pAC->Pnmi.BufPort[1].TxRetryCts;
25379                         }
25380                 }
25381                 else {
25382 -                       /* Dual net mode */
25383 +                       /* DualNet mode. */
25384                         if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25385                                 Val64 = pAC->Pnmi.Port[NetIndex].TxRetryCts;
25386                         }
25387 -                       /* Single net mode */
25388 +                       /* SingleNet mode. */
25389                         else {
25390                                 Val64 = pAC->Pnmi.Port[0].TxRetryCts +
25391                                         pAC->Pnmi.Port[1].TxRetryCts;
25392 @@ -4056,24 +3916,24 @@
25393                 break;
25394
25395         case OID_SKGE_RX_INTR_CTS:
25396 -               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25397 +               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25398                 if (MacType == SK_MAC_XMAC) {
25399 -                       /* Dual net mode */
25400 +                       /* DualNet mode. */
25401                         if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25402                                 Val64 = pAC->Pnmi.BufPort[NetIndex].RxIntrCts;
25403                         }
25404 -                       /* Single net mode */
25405 +                       /* SingleNet mode. */
25406                         else {
25407                                 Val64 = pAC->Pnmi.BufPort[0].RxIntrCts +
25408                                         pAC->Pnmi.BufPort[1].RxIntrCts;
25409                         }
25410                 }
25411                 else {
25412 -                       /* Dual net mode */
25413 +                       /* DualNet mode. */
25414                         if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25415                                 Val64 = pAC->Pnmi.Port[NetIndex].RxIntrCts;
25416                         }
25417 -                       /* Single net mode */
25418 +                       /* SingleNet mode. */
25419                         else {
25420                                 Val64 = pAC->Pnmi.Port[0].RxIntrCts +
25421                                         pAC->Pnmi.Port[1].RxIntrCts;
25422 @@ -4084,24 +3944,24 @@
25423                 break;
25424
25425         case OID_SKGE_TX_INTR_CTS:
25426 -               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25427 +               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25428                 if (MacType == SK_MAC_XMAC) {
25429 -                       /* Dual net mode */
25430 +                       /* DualNet mode. */
25431                         if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25432                                 Val64 = pAC->Pnmi.BufPort[NetIndex].TxIntrCts;
25433                         }
25434 -                       /* Single net mode */
25435 +                       /* SingleNet mode. */
25436                         else {
25437                                 Val64 = pAC->Pnmi.BufPort[0].TxIntrCts +
25438                                         pAC->Pnmi.BufPort[1].TxIntrCts;
25439                         }
25440                 }
25441                 else {
25442 -                       /* Dual net mode */
25443 +                       /* DualNet mode. */
25444                         if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25445                                 Val64 = pAC->Pnmi.Port[NetIndex].TxIntrCts;
25446                         }
25447 -                       /* Single net mode */
25448 +                       /* SingleNet mode. */
25449                         else {
25450                                 Val64 = pAC->Pnmi.Port[0].TxIntrCts +
25451                                         pAC->Pnmi.Port[1].TxIntrCts;
25452 @@ -4112,24 +3972,24 @@
25453                 break;
25454
25455         case OID_SKGE_RX_NO_BUF_CTS:
25456 -               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25457 +               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25458                 if (MacType == SK_MAC_XMAC) {
25459 -                       /* Dual net mode */
25460 +                       /* DualNet mode. */
25461                         if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25462                                 Val64 = pAC->Pnmi.BufPort[NetIndex].RxNoBufCts;
25463                         }
25464 -                       /* Single net mode */
25465 +                       /* SingleNet mode. */
25466                         else {
25467                                 Val64 = pAC->Pnmi.BufPort[0].RxNoBufCts +
25468                                         pAC->Pnmi.BufPort[1].RxNoBufCts;
25469                         }
25470                 }
25471                 else {
25472 -                       /* Dual net mode */
25473 +                       /* DualNet mode. */
25474                         if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25475                                 Val64 = pAC->Pnmi.Port[NetIndex].RxNoBufCts;
25476                         }
25477 -                       /* Single net mode */
25478 +                       /* SingleNet mode. */
25479                         else {
25480                                 Val64 = pAC->Pnmi.Port[0].RxNoBufCts +
25481                                         pAC->Pnmi.Port[1].RxNoBufCts;
25482 @@ -4140,24 +4000,24 @@
25483                 break;
25484
25485         case OID_SKGE_TX_NO_BUF_CTS:
25486 -               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25487 +               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25488                 if (MacType == SK_MAC_XMAC) {
25489 -                       /* Dual net mode */
25490 +                       /* DualNet mode. */
25491                         if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25492                                 Val64 = pAC->Pnmi.BufPort[NetIndex].TxNoBufCts;
25493                         }
25494 -                       /* Single net mode */
25495 +                       /* SingleNet mode. */
25496                         else {
25497                                 Val64 = pAC->Pnmi.BufPort[0].TxNoBufCts +
25498                                         pAC->Pnmi.BufPort[1].TxNoBufCts;
25499                         }
25500                 }
25501                 else {
25502 -                       /* Dual net mode */
25503 +                       /* DualNet mode. */
25504                         if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25505                                 Val64 = pAC->Pnmi.Port[NetIndex].TxNoBufCts;
25506                         }
25507 -                       /* Single net mode */
25508 +                       /* SingleNet mode. */
25509                         else {
25510                                 Val64 = pAC->Pnmi.Port[0].TxNoBufCts +
25511                                         pAC->Pnmi.Port[1].TxNoBufCts;
25512 @@ -4168,24 +4028,24 @@
25513                 break;
25514
25515         case OID_SKGE_TX_USED_DESCR_NO:
25516 -               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25517 +               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25518                 if (MacType == SK_MAC_XMAC) {
25519 -                       /* Dual net mode */
25520 +                       /* DualNet mode. */
25521                         if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25522                                 Val64 = pAC->Pnmi.BufPort[NetIndex].TxUsedDescrNo;
25523                         }
25524 -                       /* Single net mode */
25525 +                       /* SingleNet mode. */
25526                         else {
25527                                 Val64 = pAC->Pnmi.BufPort[0].TxUsedDescrNo +
25528                                         pAC->Pnmi.BufPort[1].TxUsedDescrNo;
25529                         }
25530                 }
25531                 else {
25532 -                       /* Dual net mode */
25533 +                       /* DualNet mode. */
25534                         if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25535                                 Val64 = pAC->Pnmi.Port[NetIndex].TxUsedDescrNo;
25536                         }
25537 -                       /* Single net mode */
25538 +                       /* SingleNet mode. */
25539                         else {
25540                                 Val64 = pAC->Pnmi.Port[0].TxUsedDescrNo +
25541                                         pAC->Pnmi.Port[1].TxUsedDescrNo;
25542 @@ -4196,24 +4056,24 @@
25543                 break;
25544
25545         case OID_SKGE_RX_DELIVERED_CTS:
25546 -               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25547 +               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25548                 if (MacType == SK_MAC_XMAC) {
25549 -                       /* Dual net mode */
25550 +                       /* DualNet mode. */
25551                         if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25552                                 Val64 = pAC->Pnmi.BufPort[NetIndex].RxDeliveredCts;
25553                         }
25554 -                       /* Single net mode */
25555 +                       /* SingleNet mode. */
25556                         else {
25557                                 Val64 = pAC->Pnmi.BufPort[0].RxDeliveredCts +
25558                                         pAC->Pnmi.BufPort[1].RxDeliveredCts;
25559                         }
25560                 }
25561                 else {
25562 -                       /* Dual net mode */
25563 +                       /* DualNet mode. */
25564                         if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25565                                 Val64 = pAC->Pnmi.Port[NetIndex].RxDeliveredCts;
25566                         }
25567 -                       /* Single net mode */
25568 +                       /* SingleNet mode. */
25569                         else {
25570                                 Val64 = pAC->Pnmi.Port[0].RxDeliveredCts +
25571                                         pAC->Pnmi.Port[1].RxDeliveredCts;
25572 @@ -4224,24 +4084,24 @@
25573                 break;
25574
25575         case OID_SKGE_RX_OCTETS_DELIV_CTS:
25576 -               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25577 +               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25578                 if (MacType == SK_MAC_XMAC) {
25579 -                       /* Dual net mode */
25580 +                       /* DualNet mode. */
25581                         if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25582                                 Val64 = pAC->Pnmi.BufPort[NetIndex].RxOctetsDeliveredCts;
25583                         }
25584 -                       /* Single net mode */
25585 +                       /* SingleNet mode. */
25586                         else {
25587                                 Val64 = pAC->Pnmi.BufPort[0].RxOctetsDeliveredCts +
25588                                         pAC->Pnmi.BufPort[1].RxOctetsDeliveredCts;
25589                         }
25590                 }
25591                 else {
25592 -                       /* Dual net mode */
25593 +                       /* DualNet mode. */
25594                         if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25595                                 Val64 = pAC->Pnmi.Port[NetIndex].RxOctetsDeliveredCts;
25596                         }
25597 -                       /* Single net mode */
25598 +                       /* SingleNet mode. */
25599                         else {
25600                                 Val64 = pAC->Pnmi.Port[0].RxOctetsDeliveredCts +
25601                                         pAC->Pnmi.Port[1].RxOctetsDeliveredCts;
25602 @@ -4262,13 +4122,13 @@
25603                 break;
25604
25605         case OID_SKGE_IN_ERRORS_CTS:
25606 -               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25607 +               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25608                 if (MacType == SK_MAC_XMAC) {
25609 -                       /* Dual net mode */
25610 +                       /* DualNet mode. */
25611                         if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25612                                 Val64 = Val64RxHwErrs + pAC->Pnmi.BufPort[NetIndex].RxNoBufCts;
25613                         }
25614 -                       /* Single net mode */
25615 +                       /* SingleNet mode. */
25616                         else {
25617                                 Val64 = Val64RxHwErrs +
25618                                         pAC->Pnmi.BufPort[0].RxNoBufCts +
25619 @@ -4276,11 +4136,11 @@
25620                         }
25621                 }
25622                 else {
25623 -                       /* Dual net mode */
25624 +                       /* DualNet mode. */
25625                         if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25626                                 Val64 = Val64RxHwErrs + pAC->Pnmi.Port[NetIndex].RxNoBufCts;
25627                         }
25628 -                       /* Single net mode */
25629 +                       /* SingleNet mode. */
25630                         else {
25631                                 Val64 = Val64RxHwErrs +
25632                                         pAC->Pnmi.Port[0].RxNoBufCts +
25633 @@ -4292,13 +4152,13 @@
25634                 break;
25635
25636         case OID_SKGE_OUT_ERROR_CTS:
25637 -               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25638 +               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25639                 if (MacType == SK_MAC_XMAC) {
25640 -                       /* Dual net mode */
25641 +                       /* DualNet mode. */
25642                         if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25643                                 Val64 = Val64TxHwErrs + pAC->Pnmi.BufPort[NetIndex].TxNoBufCts;
25644                         }
25645 -                       /* Single net mode */
25646 +                       /* SingleNet mode. */
25647                         else {
25648                                 Val64 = Val64TxHwErrs +
25649                                         pAC->Pnmi.BufPort[0].TxNoBufCts +
25650 @@ -4306,11 +4166,11 @@
25651                         }
25652                 }
25653                 else {
25654 -                       /* Dual net mode */
25655 +                       /* DualNet mode. */
25656                         if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25657                                 Val64 = Val64TxHwErrs + pAC->Pnmi.Port[NetIndex].TxNoBufCts;
25658                         }
25659 -                       /* Single net mode */
25660 +                       /* SingleNet mode. */
25661                         else {
25662                                 Val64 = Val64TxHwErrs +
25663                                         pAC->Pnmi.Port[0].TxNoBufCts +
25664 @@ -4322,24 +4182,24 @@
25665                 break;
25666
25667         case OID_SKGE_ERR_RECOVERY_CTS:
25668 -               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25669 +               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25670                 if (MacType == SK_MAC_XMAC) {
25671 -                       /* Dual net mode */
25672 +                       /* DualNet mode. */
25673                         if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25674                                 Val64 = pAC->Pnmi.BufPort[NetIndex].ErrRecoveryCts;
25675                         }
25676 -                       /* Single net mode */
25677 +                       /* SingleNet mode. */
25678                         else {
25679                                 Val64 = pAC->Pnmi.BufPort[0].ErrRecoveryCts +
25680                                         pAC->Pnmi.BufPort[1].ErrRecoveryCts;
25681                         }
25682                 }
25683                 else {
25684 -                       /* Dual net mode */
25685 +                       /* DualNet mode. */
25686                         if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25687                                 Val64 = pAC->Pnmi.Port[NetIndex].ErrRecoveryCts;
25688                         }
25689 -                       /* Single net mode */
25690 +                       /* SingleNet mode. */
25691                         else {
25692                                 Val64 = pAC->Pnmi.Port[0].ErrRecoveryCts +
25693                                         pAC->Pnmi.Port[1].ErrRecoveryCts;
25694 @@ -4363,7 +4223,7 @@
25695                 break;
25696
25697         case OID_GEN_RCV_ERROR:
25698 -               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25699 +               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25700                 if (MacType == SK_MAC_XMAC) {
25701                         Val64 = Val64RxHwErrs + pAC->Pnmi.BufPort[NetIndex].RxNoBufCts;
25702                 }
25703 @@ -4372,7 +4232,7 @@
25704                 }
25705
25706                 /*
25707 -                * by default 32bit values are evaluated
25708 +                * By default 32bit values are evaluated.
25709                  */
25710                 if (!Is64BitReq) {
25711                         Val32 = (SK_U32)Val64;
25712 @@ -4386,7 +4246,7 @@
25713                 break;
25714
25715         case OID_GEN_XMIT_ERROR:
25716 -               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25717 +               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25718                 if (MacType == SK_MAC_XMAC) {
25719                         Val64 = Val64TxHwErrs + pAC->Pnmi.BufPort[NetIndex].TxNoBufCts;
25720                 }
25721 @@ -4395,7 +4255,7 @@
25722                 }
25723
25724                 /*
25725 -                * by default 32bit values are evaluated
25726 +                * By default 32bit values are evaluated.
25727                  */
25728                 if (!Is64BitReq) {
25729                         Val32 = (SK_U32)Val64;
25730 @@ -4409,16 +4269,19 @@
25731                 break;
25732
25733         case OID_GEN_RCV_NO_BUFFER:
25734 -               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25735 +               /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25736                 if (MacType == SK_MAC_XMAC) {
25737 -                       Val64 = pAC->Pnmi.BufPort[NetIndex].RxNoBufCts;
25738 +                       Val64 = pAC->Pnmi.BufPort[NetIndex].RxNoBufCts +
25739 +                               GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_OVERFLOW, NetIndex);
25740 +
25741                 }
25742                 else {
25743 -                       Val64 = pAC->Pnmi.Port[NetIndex].RxNoBufCts;
25744 +                       Val64 = pAC->Pnmi.Port[NetIndex].RxNoBufCts +
25745 +                               GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_OVERFLOW, NetIndex);
25746                 }
25747
25748                 /*
25749 -                * by default 32bit values are evaluated
25750 +                * By default 32bit values are evaluated.
25751                  */
25752                 if (!Is64BitReq) {
25753                         Val32 = (SK_U32)Val64;
25754 @@ -4438,8 +4301,7 @@
25755                 break;
25756
25757         default:
25758 -               SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR034,
25759 -                       SK_PNMI_ERR034MSG);
25760 +               SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR034, SK_PNMI_ERR034MSG);
25761
25762                 *pLen = 0;
25763                 return (SK_PNMI_ERR_GENERAL);
25764 @@ -4496,25 +4358,17 @@
25765         SK_U32          Val32;
25766         SK_U64          Val64;
25767
25768 -
25769 -       /*
25770 -        * Check instance. Only single instance OIDs are allowed here.
25771 -        */
25772 +       /* Check instance. Only single instance OIDs are allowed here. */
25773         if (Instance != (SK_U32)(-1) && Instance != 1) {
25774
25775                 *pLen = 0;
25776                 return (SK_PNMI_ERR_UNKNOWN_INST);
25777         }
25778
25779 -       /*
25780 -        * Perform the requested action.
25781 -        */
25782 +       /* Perform the requested action. */
25783         if (Action == SK_PNMI_GET) {
25784
25785 -               /*
25786 -                * Check if the buffer length is large enough.
25787 -                */
25788 -
25789 +               /* Check if the buffer length is large enough. */
25790                 switch (Id) {
25791
25792                 case OID_SKGE_RLMT_MODE:
25793 @@ -4547,8 +4401,7 @@
25794                         break;
25795
25796                 default:
25797 -                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR035,
25798 -                               SK_PNMI_ERR035MSG);
25799 +                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR035, SK_PNMI_ERR035MSG);
25800
25801                         *pLen = 0;
25802                         return (SK_PNMI_ERR_GENERAL);
25803 @@ -4567,9 +4420,7 @@
25804                 }
25805                 pAC->Pnmi.RlmtUpdatedFlag ++;
25806
25807 -               /*
25808 -                * Retrieve Value
25809 -               */
25810 +               /* Retrieve value. */
25811                 switch (Id) {
25812
25813                 case OID_SKGE_RLMT_MODE:
25814 @@ -4647,17 +4498,17 @@
25815                 pAC->Pnmi.RlmtUpdatedFlag --;
25816         }
25817         else {
25818 -               /* Perform a preset or set */
25819 +               /* Perform a PRESET or SET. */
25820                 switch (Id) {
25821
25822                 case OID_SKGE_RLMT_MODE:
25823 -                       /* Check if the buffer length is plausible */
25824 +                       /* Check if the buffer length is plausible. */
25825                         if (*pLen < sizeof(char)) {
25826
25827                                 *pLen = sizeof(char);
25828                                 return (SK_PNMI_ERR_TOO_SHORT);
25829                         }
25830 -                       /* Check if the value range is correct */
25831 +                       /* Check if the value range is correct. */
25832                         if (*pLen != sizeof(char) ||
25833                                 (*pBuf & SK_PNMI_RLMT_MODE_CHK_LINK) == 0 ||
25834                                 *(SK_U8 *)pBuf > 15) {
25835 @@ -4665,21 +4516,21 @@
25836                                 *pLen = 0;
25837                                 return (SK_PNMI_ERR_BAD_VALUE);
25838                         }
25839 -                       /* The preset ends here */
25840 +                       /* The PRESET ends here. */
25841                         if (Action == SK_PNMI_PRESET) {
25842
25843                                 *pLen = 0;
25844                                 return (SK_PNMI_ERR_OK);
25845                         }
25846 -                       /* Send an event to RLMT to change the mode */
25847 +                       /* Send an event to RLMT to change the mode. */
25848                         SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
25849 +
25850                         EventParam.Para32[0] |= (SK_U32)(*pBuf);
25851                         EventParam.Para32[1] = 0;
25852                         if (SkRlmtEvent(pAC, IoC, SK_RLMT_MODE_CHANGE,
25853                                 EventParam) > 0) {
25854
25855 -                               SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR037,
25856 -                                       SK_PNMI_ERR037MSG);
25857 +                               SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR037, SK_PNMI_ERR037MSG);
25858
25859                                 *pLen = 0;
25860                                 return (SK_PNMI_ERR_GENERAL);
25861 @@ -4687,20 +4538,25 @@
25862                         break;
25863
25864                 case OID_SKGE_RLMT_PORT_PREFERRED:
25865 -                       /* Check if the buffer length is plausible */
25866 +                       /* PRESET/SET action makes no sense in Dual Net mode. */
25867 +                       if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25868 +                               break;
25869 +                       }
25870 +
25871 +                       /* Check if the buffer length is plausible. */
25872                         if (*pLen < sizeof(char)) {
25873
25874                                 *pLen = sizeof(char);
25875                                 return (SK_PNMI_ERR_TOO_SHORT);
25876                         }
25877 -                       /* Check if the value range is correct */
25878 +                       /* Check if the value range is correct. */
25879                         if (*pLen != sizeof(char) || *(SK_U8 *)pBuf >
25880                                 (SK_U8)pAC->GIni.GIMacsFound) {
25881
25882                                 *pLen = 0;
25883                                 return (SK_PNMI_ERR_BAD_VALUE);
25884                         }
25885 -                       /* The preset ends here */
25886 +                       /* The PRESET ends here. */
25887                         if (Action == SK_PNMI_PRESET) {
25888
25889                                 *pLen = 0;
25890 @@ -4713,13 +4569,13 @@
25891                          * make the decision which is the preferred port.
25892                          */
25893                         SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
25894 +
25895                         EventParam.Para32[0] = (SK_U32)(*pBuf) - 1;
25896                         EventParam.Para32[1] = NetIndex;
25897                         if (SkRlmtEvent(pAC, IoC, SK_RLMT_PREFPORT_CHANGE,
25898                                 EventParam) > 0) {
25899
25900 -                               SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR038,
25901 -                                       SK_PNMI_ERR038MSG);
25902 +                               SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR038, SK_PNMI_ERR038MSG);
25903
25904                                 *pLen = 0;
25905                                 return (SK_PNMI_ERR_GENERAL);
25906 @@ -4727,22 +4583,20 @@
25907                         break;
25908
25909                 case OID_SKGE_RLMT_CHANGE_THRES:
25910 -                       /* Check if the buffer length is plausible */
25911 +                       /* Check if the buffer length is plausible. */
25912                         if (*pLen < sizeof(SK_U64)) {
25913
25914                                 *pLen = sizeof(SK_U64);
25915                                 return (SK_PNMI_ERR_TOO_SHORT);
25916                         }
25917 -                       /*
25918 -                        * There are not many restrictions to the
25919 -                        * value range.
25920 -                        */
25921 +
25922 +                       /* There are not many restrictions to the value range. */
25923                         if (*pLen != sizeof(SK_U64)) {
25924
25925                                 *pLen = 0;
25926                                 return (SK_PNMI_ERR_BAD_VALUE);
25927                         }
25928 -                       /* A preset ends here */
25929 +                       /* The PRESET ends here. */
25930                         if (Action == SK_PNMI_PRESET) {
25931
25932                                 *pLen = 0;
25933 @@ -4757,7 +4611,7 @@
25934                         break;
25935
25936                 default:
25937 -                       /* The other OIDs are not be able for set */
25938 +                       /* The other OIDs are not be able for set. */
25939                         *pLen = 0;
25940                         return (SK_PNMI_ERR_READ_ONLY);
25941                 }
25942 @@ -4802,54 +4656,49 @@
25943         SK_U32          Val32;
25944         SK_U64          Val64;
25945
25946 -       /*
25947 -        * Calculate the port indexes from the instance.
25948 -        */
25949 +
25950 +       /* Calculate the port indexes from the instance. */
25951         PhysPortMax = pAC->GIni.GIMacsFound;
25952
25953         if ((Instance != (SK_U32)(-1))) {
25954 -               /* Check instance range */
25955 +               /* Check instance range. */
25956                 if ((Instance < 1) || (Instance > PhysPortMax)) {
25957
25958                         *pLen = 0;
25959                         return (SK_PNMI_ERR_UNKNOWN_INST);
25960                 }
25961
25962 -               /* Single net mode */
25963 +               /* SingleNet mode. */
25964                 PhysPortIndex = Instance - 1;
25965
25966 -               /* Dual net mode */
25967 +               /* DualNet mode. */
25968                 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25969                         PhysPortIndex = NetIndex;
25970                 }
25971
25972 -               /* Both net modes */
25973 +               /* Both net modes. */
25974                 Limit = PhysPortIndex + 1;
25975         }
25976         else {
25977 -               /* Single net mode */
25978 +               /* SingleNet mode. */
25979                 PhysPortIndex = 0;
25980                 Limit = PhysPortMax;
25981
25982 -               /* Dual net mode */
25983 +               /* DualNet mode. */
25984                 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25985                         PhysPortIndex = NetIndex;
25986                         Limit = PhysPortIndex + 1;
25987                 }
25988         }
25989
25990 -       /*
25991 -        * Currently only get requests are allowed.
25992 -        */
25993 +       /* Currently only GET requests are allowed. */
25994         if (Action != SK_PNMI_GET) {
25995
25996                 *pLen = 0;
25997                 return (SK_PNMI_ERR_READ_ONLY);
25998         }
25999
26000 -       /*
26001 -        * Check if the buffer length is large enough.
26002 -        */
26003 +       /* Check if the buffer length is large enough. */
26004         switch (Id) {
26005
26006         case OID_SKGE_RLMT_PORT_INDEX:
26007 @@ -4873,8 +4722,7 @@
26008                 break;
26009
26010         default:
26011 -               SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR039,
26012 -                       SK_PNMI_ERR039MSG);
26013 +               SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR039, SK_PNMI_ERR039MSG);
26014
26015                 *pLen = 0;
26016                 return (SK_PNMI_ERR_GENERAL);
26017 @@ -4892,9 +4740,7 @@
26018         }
26019         pAC->Pnmi.RlmtUpdatedFlag ++;
26020
26021 -       /*
26022 -        * Get value
26023 -        */
26024 +       /* Get value. */
26025         Offset = 0;
26026         for (; PhysPortIndex < Limit; PhysPortIndex ++) {
26027
26028 @@ -5007,19 +4853,21 @@
26029         int                     Ret;
26030         SK_EVPARA       EventParam;
26031         SK_U32          Val32;
26032 +#ifdef SK_PHY_LP_MODE
26033 +       SK_U8   CurrentPhyPowerState;
26034 +#endif /* SK_PHY_LP_MODE */
26035
26036 -       /*
26037 -        * Calculate instance if wished. MAC index 0 is the virtual MAC.
26038 -        */
26039 +
26040 +       /* Calculate instance if wished. MAC index 0 is the virtual MAC. */
26041         PhysPortMax = pAC->GIni.GIMacsFound;
26042         LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax);
26043
26044 -       if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* Dual net mode */
26045 +       if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* DualNet mode. */
26046                 LogPortMax--;
26047         }
26048
26049 -       if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried */
26050 -               /* Check instance range */
26051 +       if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried. */
26052 +               /* Check instance range. */
26053                 if ((Instance < 1) || (Instance > LogPortMax)) {
26054
26055                         *pLen = 0;
26056 @@ -5029,18 +4877,16 @@
26057                 Limit = LogPortIndex + 1;
26058         }
26059
26060 -       else { /* Instance == (SK_U32)(-1), get all Instances of that OID */
26061 +       else { /* Instance == (SK_U32)(-1), get all Instances of that OID. */
26062
26063                 LogPortIndex = 0;
26064                 Limit = LogPortMax;
26065         }
26066
26067 -       /*
26068 -        * Perform action
26069 -        */
26070 +       /* Perform action. */
26071         if (Action == SK_PNMI_GET) {
26072
26073 -               /* Check length */
26074 +               /* Check length. */
26075                 switch (Id) {
26076
26077                 case OID_SKGE_PMD:
26078 @@ -5058,6 +4904,9 @@
26079                 case OID_SKGE_SPEED_CAP:
26080                 case OID_SKGE_SPEED_MODE:
26081                 case OID_SKGE_SPEED_STATUS:
26082 +#ifdef SK_PHY_LP_MODE
26083 +               case OID_SKGE_PHY_LP_MODE:
26084 +#endif
26085                         if (*pLen < (Limit - LogPortIndex) * sizeof(SK_U8)) {
26086
26087                                 *pLen = (Limit - LogPortIndex) * sizeof(SK_U8);
26088 @@ -5075,8 +4924,7 @@
26089                         break;
26090
26091                 default:
26092 -                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR041,
26093 -                               SK_PNMI_ERR041MSG);
26094 +                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR041, SK_PNMI_ERR041MSG);
26095                         *pLen = 0;
26096                         return (SK_PNMI_ERR_GENERAL);
26097                 }
26098 @@ -5092,9 +4940,7 @@
26099                 }
26100                 pAC->Pnmi.SirqUpdatedFlag ++;
26101
26102 -               /*
26103 -                * Get value
26104 -                */
26105 +               /* Get value. */
26106                 Offset = 0;
26107                 for (; LogPortIndex < Limit; LogPortIndex ++) {
26108
26109 @@ -5104,85 +4950,99 @@
26110
26111                         case OID_SKGE_PMD:
26112                                 *pBufPtr = pAC->Pnmi.PMD;
26113 -                               Offset += sizeof(char);
26114 +                               Offset ++;
26115                                 break;
26116
26117                         case OID_SKGE_CONNECTOR:
26118                                 *pBufPtr = pAC->Pnmi.Connector;
26119 -                               Offset += sizeof(char);
26120 +                               Offset ++;
26121                                 break;
26122
26123                         case OID_SKGE_PHY_TYPE:
26124 -                               if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26125 +                               if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26126                                         if (LogPortIndex == 0) {
26127                                                 continue;
26128                                         }
26129 -                                       else {
26130 -                                               /* Get value for physical ports */
26131 -                                               PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26132 -                                                       pAC, LogPortIndex);
26133 -                                               Val32 = pAC->GIni.GP[PhysPortIndex].PhyType;
26134 -                                               SK_PNMI_STORE_U32(pBufPtr, Val32);
26135 -                                       }
26136 +                                       /* Get value for physical port. */
26137 +                                       PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);
26138 +                                       Val32 = pAC->GIni.GP[PhysPortIndex].PhyType;
26139                                 }
26140 -                               else { /* DualNetMode */
26141 +                               else { /* DualNet mode. */
26142
26143                                         Val32 = pAC->GIni.GP[NetIndex].PhyType;
26144 -                                       SK_PNMI_STORE_U32(pBufPtr, Val32);
26145                                 }
26146 +                               SK_PNMI_STORE_U32(pBufPtr, Val32);
26147                                 Offset += sizeof(SK_U32);
26148                                 break;
26149
26150 +#ifdef SK_PHY_LP_MODE
26151 +                       case OID_SKGE_PHY_LP_MODE:
26152 +                               if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26153 +                                       if (LogPortIndex == 0) {
26154 +                                               continue;
26155 +                                       }
26156 +                                       /* Get value for physical port. */
26157 +                                       PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);
26158 +                                       *pBufPtr = (SK_U8)pAC->GIni.GP[PhysPortIndex].PPhyPowerState;
26159 +                               }
26160 +                               else { /* DualNet mode. */
26161 +
26162 +                                       *pBufPtr = (SK_U8)pAC->GIni.GP[NetIndex].PPhyPowerState;
26163 +                               }
26164 +                               Offset += sizeof(SK_U8);
26165 +                               break;
26166 +#endif
26167 +
26168                         case OID_SKGE_LINK_CAP:
26169 -                               if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26170 +                               if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26171                                         if (LogPortIndex == 0) {
26172 -                                               /* Get value for virtual port */
26173 +                                               /* Get value for virtual port. */
26174                                                 VirtualConf(pAC, IoC, Id, pBufPtr);
26175                                         }
26176                                         else {
26177 -                                               /* Get value for physical ports */
26178 +                                               /* Get value for physical port. */
26179                                                 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26180                                                         pAC, LogPortIndex);
26181
26182                                                 *pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkCap;
26183                                         }
26184                                 }
26185 -                               else { /* DualNetMode */
26186 +                               else { /* DualNet mode. */
26187
26188                                         *pBufPtr = pAC->GIni.GP[NetIndex].PLinkCap;
26189                                 }
26190 -                               Offset += sizeof(char);
26191 +                               Offset ++;
26192                                 break;
26193
26194                         case OID_SKGE_LINK_MODE:
26195 -                               if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26196 +                               if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26197                                         if (LogPortIndex == 0) {
26198 -                                               /* Get value for virtual port */
26199 +                                               /* Get value for virtual port. */
26200                                                 VirtualConf(pAC, IoC, Id, pBufPtr);
26201                                         }
26202                                         else {
26203 -                                               /* Get value for physical ports */
26204 +                                               /* Get value for physical port. */
26205                                                 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26206                                                         pAC, LogPortIndex);
26207
26208                                                 *pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkModeConf;
26209                                         }
26210                                 }
26211 -                               else { /* DualNetMode */
26212 +                               else { /* DualNet mode. */
26213
26214                                         *pBufPtr = pAC->GIni.GP[NetIndex].PLinkModeConf;
26215                                 }
26216 -                               Offset += sizeof(char);
26217 +                               Offset ++;
26218                                 break;
26219
26220                         case OID_SKGE_LINK_MODE_STATUS:
26221 -                               if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26222 +                               if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26223                                         if (LogPortIndex == 0) {
26224 -                                               /* Get value for virtual port */
26225 +                                               /* Get value for virtual port. */
26226                                                 VirtualConf(pAC, IoC, Id, pBufPtr);
26227                                         }
26228                                         else {
26229 -                                               /* Get value for physical port */
26230 +                                               /* Get value for physical port. */
26231                                                 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26232                                                         pAC, LogPortIndex);
26233
26234 @@ -5190,147 +5050,147 @@
26235                                                         CalculateLinkModeStatus(pAC, IoC, PhysPortIndex);
26236                                         }
26237                                 }
26238 -                               else { /* DualNetMode */
26239 +                               else { /* DualNet mode. */
26240
26241                                         *pBufPtr = CalculateLinkModeStatus(pAC, IoC, NetIndex);
26242                                 }
26243 -                               Offset += sizeof(char);
26244 +                               Offset ++;
26245                                 break;
26246
26247                         case OID_SKGE_LINK_STATUS:
26248 -                               if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26249 +                               if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26250                                         if (LogPortIndex == 0) {
26251 -                                               /* Get value for virtual port */
26252 +                                               /* Get value for virtual port. */
26253                                                 VirtualConf(pAC, IoC, Id, pBufPtr);
26254                                         }
26255                                         else {
26256 -                                               /* Get value for physical ports */
26257 +                                               /* Get value for physical port. */
26258                                                 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26259                                                         pAC, LogPortIndex);
26260
26261                                                 *pBufPtr = CalculateLinkStatus(pAC, IoC, PhysPortIndex);
26262                                         }
26263                                 }
26264 -                               else { /* DualNetMode */
26265 +                               else { /* DualNet mode. */
26266
26267                                         *pBufPtr = CalculateLinkStatus(pAC, IoC, NetIndex);
26268                                 }
26269 -                               Offset += sizeof(char);
26270 +                               Offset ++;
26271                                 break;
26272
26273                         case OID_SKGE_FLOWCTRL_CAP:
26274 -                               if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26275 +                               if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26276                                         if (LogPortIndex == 0) {
26277 -                                               /* Get value for virtual port */
26278 +                                               /* Get value for virtual port. */
26279                                                 VirtualConf(pAC, IoC, Id, pBufPtr);
26280                                         }
26281                                         else {
26282 -                                               /* Get value for physical ports */
26283 +                                               /* Get value for physical port. */
26284                                                 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26285                                                         pAC, LogPortIndex);
26286
26287                                                 *pBufPtr = pAC->GIni.GP[PhysPortIndex].PFlowCtrlCap;
26288                                         }
26289                                 }
26290 -                               else { /* DualNetMode */
26291 +                               else { /* DualNet mode. */
26292
26293                                         *pBufPtr = pAC->GIni.GP[NetIndex].PFlowCtrlCap;
26294                                 }
26295 -                               Offset += sizeof(char);
26296 +                               Offset ++;
26297                                 break;
26298
26299                         case OID_SKGE_FLOWCTRL_MODE:
26300 -                               if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26301 +                               if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26302                                         if (LogPortIndex == 0) {
26303 -                                               /* Get value for virtual port */
26304 +                                               /* Get value for virtual port. */
26305                                                 VirtualConf(pAC, IoC, Id, pBufPtr);
26306                                         }
26307                                         else {
26308 -                                               /* Get value for physical port */
26309 +                                               /* Get value for physical port. */
26310                                                 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26311                                                         pAC, LogPortIndex);
26312
26313                                                 *pBufPtr = pAC->GIni.GP[PhysPortIndex].PFlowCtrlMode;
26314                                         }
26315                                 }
26316 -                               else { /* DualNetMode */
26317 +                               else { /* DualNet mode. */
26318
26319                                         *pBufPtr = pAC->GIni.GP[NetIndex].PFlowCtrlMode;
26320                                 }
26321 -                               Offset += sizeof(char);
26322 +                               Offset ++;
26323                                 break;
26324
26325                         case OID_SKGE_FLOWCTRL_STATUS:
26326 -                               if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26327 +                               if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26328                                         if (LogPortIndex == 0) {
26329 -                                               /* Get value for virtual port */
26330 +                                               /* Get value for virtual port. */
26331                                                 VirtualConf(pAC, IoC, Id, pBufPtr);
26332                                         }
26333                                         else {
26334 -                                               /* Get value for physical port */
26335 +                                               /* Get value for physical port. */
26336                                                 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26337                                                         pAC, LogPortIndex);
26338
26339                                                 *pBufPtr = pAC->GIni.GP[PhysPortIndex].PFlowCtrlStatus;
26340                                         }
26341                                 }
26342 -                               else { /* DualNetMode */
26343 +                               else { /* DualNet mode. */
26344
26345                                         *pBufPtr = pAC->GIni.GP[NetIndex].PFlowCtrlStatus;
26346                                 }
26347 -                               Offset += sizeof(char);
26348 +                               Offset ++;
26349                                 break;
26350
26351                         case OID_SKGE_PHY_OPERATION_CAP:
26352 -                               if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26353 +                               if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet Mode. */
26354                                         if (LogPortIndex == 0) {
26355 -                                               /* Get value for virtual port */
26356 +                                               /* Get value for virtual port. */
26357                                                 VirtualConf(pAC, IoC, Id, pBufPtr);
26358                                         }
26359                                         else {
26360 -                                               /* Get value for physical ports */
26361 +                                               /* Get value for physical port. */
26362                                                 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26363                                                         pAC, LogPortIndex);
26364
26365                                                 *pBufPtr = pAC->GIni.GP[PhysPortIndex].PMSCap;
26366                                         }
26367                                 }
26368 -                               else { /* DualNetMode */
26369 +                               else { /* DualNet mode. */
26370
26371                                         *pBufPtr = pAC->GIni.GP[NetIndex].PMSCap;
26372                                 }
26373 -                               Offset += sizeof(char);
26374 +                               Offset ++;
26375                                 break;
26376
26377                         case OID_SKGE_PHY_OPERATION_MODE:
26378 -                               if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26379 +                               if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26380                                         if (LogPortIndex == 0) {
26381 -                                               /* Get value for virtual port */
26382 +                                               /* Get value for virtual port. */
26383                                                 VirtualConf(pAC, IoC, Id, pBufPtr);
26384                                         }
26385                                         else {
26386 -                                               /* Get value for physical port */
26387 +                                               /* Get value for physical port. */
26388                                                 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26389                                                         pAC, LogPortIndex);
26390
26391                                                 *pBufPtr = pAC->GIni.GP[PhysPortIndex].PMSMode;
26392                                         }
26393                                 }
26394 -                               else { /* DualNetMode */
26395 +                               else { /* DualNet mode. */
26396
26397                                         *pBufPtr = pAC->GIni.GP[NetIndex].PMSMode;
26398                                 }
26399 -                               Offset += sizeof(char);
26400 +                               Offset ++;
26401                                 break;
26402
26403                         case OID_SKGE_PHY_OPERATION_STATUS:
26404 -                               if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26405 +                               if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26406                                         if (LogPortIndex == 0) {
26407 -                                               /* Get value for virtual port */
26408 +                                               /* Get value for virtual port. */
26409                                                 VirtualConf(pAC, IoC, Id, pBufPtr);
26410                                         }
26411                                         else {
26412 -                                               /* Get value for physical port */
26413 +                                               /* Get value for physical port. */
26414                                                 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26415                                                         pAC, LogPortIndex);
26416
26417 @@ -5341,70 +5201,70 @@
26418
26419                                         *pBufPtr = pAC->GIni.GP[NetIndex].PMSStatus;
26420                                 }
26421 -                               Offset += sizeof(char);
26422 +                               Offset ++;
26423                                 break;
26424
26425                         case OID_SKGE_SPEED_CAP:
26426 -                               if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26427 +                               if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26428                                         if (LogPortIndex == 0) {
26429 -                                               /* Get value for virtual port */
26430 +                                               /* Get value for virtual port. */
26431                                                 VirtualConf(pAC, IoC, Id, pBufPtr);
26432                                         }
26433                                         else {
26434 -                                               /* Get value for physical ports */
26435 +                                               /* Get value for physical port. */
26436                                                 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26437                                                         pAC, LogPortIndex);
26438
26439                                                 *pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkSpeedCap;
26440                                         }
26441                                 }
26442 -                               else { /* DualNetMode */
26443 +                               else { /* DualNet mode. */
26444
26445                                         *pBufPtr = pAC->GIni.GP[NetIndex].PLinkSpeedCap;
26446                                 }
26447 -                               Offset += sizeof(char);
26448 +                               Offset ++;
26449                                 break;
26450
26451                         case OID_SKGE_SPEED_MODE:
26452 -                               if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26453 +                               if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26454                                         if (LogPortIndex == 0) {
26455 -                                               /* Get value for virtual port */
26456 +                                               /* Get value for virtual port. */
26457                                                 VirtualConf(pAC, IoC, Id, pBufPtr);
26458                                         }
26459                                         else {
26460 -                                               /* Get value for physical port */
26461 +                                               /* Get value for physical port. */
26462                                                 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26463                                                         pAC, LogPortIndex);
26464
26465                                                 *pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkSpeed;
26466                                         }
26467                                 }
26468 -                               else { /* DualNetMode */
26469 +                               else { /* DualNet mode. */
26470
26471                                         *pBufPtr = pAC->GIni.GP[NetIndex].PLinkSpeed;
26472                                 }
26473 -                               Offset += sizeof(char);
26474 +                               Offset ++;
26475                                 break;
26476
26477                         case OID_SKGE_SPEED_STATUS:
26478 -                               if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26479 +                               if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26480                                         if (LogPortIndex == 0) {
26481 -                                               /* Get value for virtual port */
26482 +                                               /* Get value for virtual port. */
26483                                                 VirtualConf(pAC, IoC, Id, pBufPtr);
26484                                         }
26485                                         else {
26486 -                                               /* Get value for physical port */
26487 +                                               /* Get value for physical port. */
26488                                                 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26489                                                         pAC, LogPortIndex);
26490
26491                                                 *pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkSpeedUsed;
26492                                         }
26493                                 }
26494 -                               else { /* DualNetMode */
26495 +                               else { /* DualNet mode. */
26496
26497                                         *pBufPtr = pAC->GIni.GP[NetIndex].PLinkSpeedUsed;
26498                                 }
26499 -                               Offset += sizeof(char);
26500 +                               Offset ++;
26501                                 break;
26502
26503                         case OID_SKGE_MTU:
26504 @@ -5449,38 +5309,41 @@
26505                 }
26506                 break;
26507
26508 -       case OID_SKGE_MTU:
26509 -               if (*pLen < sizeof(SK_U32)) {
26510 +#ifdef SK_PHY_LP_MODE
26511 +       case OID_SKGE_PHY_LP_MODE:
26512 +               if (*pLen < Limit - LogPortIndex) {
26513
26514 -                       *pLen = sizeof(SK_U32);
26515 +                       *pLen = Limit - LogPortIndex;
26516                         return (SK_PNMI_ERR_TOO_SHORT);
26517                 }
26518 -               if (*pLen != sizeof(SK_U32)) {
26519 +               break;
26520 +#endif /* SK_PHY_LP_MODE */
26521
26522 -                       *pLen = 0;
26523 -                       return (SK_PNMI_ERR_BAD_VALUE);
26524 +       case OID_SKGE_MTU:
26525 +               if (*pLen < (Limit - LogPortIndex) * sizeof(SK_U32)) {
26526 +
26527 +                       *pLen = (Limit - LogPortIndex) * sizeof(SK_U32);
26528 +                       return (SK_PNMI_ERR_TOO_SHORT);
26529                 }
26530                 break;
26531 -
26532 +
26533      default:
26534                 *pLen = 0;
26535                 return (SK_PNMI_ERR_READ_ONLY);
26536         }
26537
26538 -       /*
26539 -        * Perform preset or set
26540 -        */
26541 +       /* Perform PRESET or SET. */
26542         Offset = 0;
26543         for (; LogPortIndex < Limit; LogPortIndex ++) {
26544
26545 +               Val8 = *(pBuf + Offset);
26546 +
26547                 switch (Id) {
26548
26549                 case OID_SKGE_LINK_MODE:
26550 -                       /* Check the value range */
26551 -                       Val8 = *(pBuf + Offset);
26552 +                       /* Check the value range. */
26553                         if (Val8 == 0) {
26554 -
26555 -                               Offset += sizeof(char);
26556 +                               Offset++;
26557                                 break;
26558                         }
26559                         if (Val8 < SK_LMODE_HALF ||
26560 @@ -5491,51 +5354,68 @@
26561                                 return (SK_PNMI_ERR_BAD_VALUE);
26562                         }
26563
26564 -                       /* The preset ends here */
26565 +                       /* The PRESET ends here. */
26566                         if (Action == SK_PNMI_PRESET) {
26567
26568                                 return (SK_PNMI_ERR_OK);
26569                         }
26570
26571 -                       if (LogPortIndex == 0) {
26572 -
26573 -                               /*
26574 -                                * The virtual port consists of all currently
26575 -                                * active ports. Find them and send an event
26576 -                                * with the new link mode to SIRQ.
26577 -                                */
26578 -                               for (PhysPortIndex = 0;
26579 -                                       PhysPortIndex < PhysPortMax;
26580 -                                       PhysPortIndex ++) {
26581 -
26582 -                                       if (!pAC->Pnmi.Port[PhysPortIndex].
26583 -                                               ActiveFlag) {
26584 -
26585 -                                               continue;
26586 -                                       }
26587 +                       if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26588 +                               if (LogPortIndex == 0) {
26589 +                                       /*
26590 +                                        * The virtual port consists of all currently
26591 +                                        * active ports. Find them and send an event
26592 +                                        * with the new link mode to SIRQ.
26593 +                                        */
26594 +                                       for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;
26595 +                                               PhysPortIndex ++) {
26596
26597 -                                       EventParam.Para32[0] = PhysPortIndex;
26598 +                                               if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
26599 +                                                       continue;
26600 +                                               }
26601 +
26602 +                                               EventParam.Para32[0] = PhysPortIndex;
26603 +                                               EventParam.Para32[1] = (SK_U32)Val8;
26604 +                                               if (SkGeSirqEvent(pAC, IoC,
26605 +                                                       SK_HWEV_SET_LMODE,
26606 +                                                       EventParam) > 0) {
26607 +
26608 +                                                       SK_ERR_LOG(pAC, SK_ERRCL_SW,
26609 +                                                               SK_PNMI_ERR043,
26610 +                                                               SK_PNMI_ERR043MSG);
26611 +
26612 +                                                       *pLen = 0;
26613 +                                                       return (SK_PNMI_ERR_GENERAL);
26614 +                                               }
26615 +                                       } /* for */
26616 +                               }
26617 +                               else {
26618 +                                       /*
26619 +                                        * Send an event with the new link mode to
26620 +                                        * the SIRQ module.
26621 +                                        */
26622 +                                       EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
26623 +                                               pAC, LogPortIndex);
26624                                         EventParam.Para32[1] = (SK_U32)Val8;
26625 -                                       if (SkGeSirqEvent(pAC, IoC,
26626 -                                               SK_HWEV_SET_LMODE,
26627 +                                       if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_LMODE,
26628                                                 EventParam) > 0) {
26629 -
26630 +
26631                                                 SK_ERR_LOG(pAC, SK_ERRCL_SW,
26632                                                         SK_PNMI_ERR043,
26633                                                         SK_PNMI_ERR043MSG);
26634 -
26635 +
26636                                                 *pLen = 0;
26637                                                 return (SK_PNMI_ERR_GENERAL);
26638                                         }
26639                                 }
26640                         }
26641 -                       else {
26642 +                       else { /* DualNet mode. */
26643 +
26644                                 /*
26645                                  * Send an event with the new link mode to
26646                                  * the SIRQ module.
26647                                  */
26648 -                               EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
26649 -                                       pAC, LogPortIndex);
26650 +                               EventParam.Para32[0] = NetIndex;
26651                                 EventParam.Para32[1] = (SK_U32)Val8;
26652                                 if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_LMODE,
26653                                         EventParam) > 0) {
26654 @@ -5548,15 +5428,13 @@
26655                                         return (SK_PNMI_ERR_GENERAL);
26656                                 }
26657                         }
26658 -                       Offset += sizeof(char);
26659 +                       Offset++;
26660                         break;
26661
26662                 case OID_SKGE_FLOWCTRL_MODE:
26663 -                       /* Check the value range */
26664 -                       Val8 = *(pBuf + Offset);
26665 +                       /* Check the value range. */
26666                         if (Val8 == 0) {
26667 -
26668 -                               Offset += sizeof(char);
26669 +                               Offset++;
26670                                 break;
26671                         }
26672                         if (Val8 < SK_FLOW_MODE_NONE ||
26673 @@ -5567,30 +5445,48 @@
26674                                 return (SK_PNMI_ERR_BAD_VALUE);
26675                         }
26676
26677 -                       /* The preset ends here */
26678 +                       /* The PRESET ends here. */
26679                         if (Action == SK_PNMI_PRESET) {
26680
26681                                 return (SK_PNMI_ERR_OK);
26682                         }
26683
26684 -                       if (LogPortIndex == 0) {
26685 +                       if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26686 +                               if (LogPortIndex == 0) {
26687 +                                       /*
26688 +                                        * The virtual port consists of all currently
26689 +                                        * active ports. Find them and send an event
26690 +                                        * with the new flow control mode to SIRQ.
26691 +                                        */
26692 +                                       for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;
26693 +                                               PhysPortIndex ++) {
26694
26695 -                               /*
26696 -                                * The virtual port consists of all currently
26697 -                                * active ports. Find them and send an event
26698 -                                * with the new flow control mode to SIRQ.
26699 -                                */
26700 -                               for (PhysPortIndex = 0;
26701 -                                       PhysPortIndex < PhysPortMax;
26702 -                                       PhysPortIndex ++) {
26703 +                                               if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
26704 +                                                       continue;
26705 +                                               }
26706
26707 -                                       if (!pAC->Pnmi.Port[PhysPortIndex].
26708 -                                               ActiveFlag) {
26709 +                                               EventParam.Para32[0] = PhysPortIndex;
26710 +                                               EventParam.Para32[1] = (SK_U32)Val8;
26711 +                                               if (SkGeSirqEvent(pAC, IoC,
26712 +                                                       SK_HWEV_SET_FLOWMODE,
26713 +                                                       EventParam) > 0) {
26714 +
26715 +                                                       SK_ERR_LOG(pAC, SK_ERRCL_SW,
26716 +                                                               SK_PNMI_ERR044,
26717 +                                                               SK_PNMI_ERR044MSG);
26718
26719 -                                               continue;
26720 +                                                       *pLen = 0;
26721 +                                                       return (SK_PNMI_ERR_GENERAL);
26722 +                                               }
26723                                         }
26724 -
26725 -                                       EventParam.Para32[0] = PhysPortIndex;
26726 +                               }
26727 +                               else {
26728 +                                       /*
26729 +                                        * Send an event with the new flow control
26730 +                                        * mode to the SIRQ module.
26731 +                                        */
26732 +                                       EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
26733 +                                               pAC, LogPortIndex);
26734                                         EventParam.Para32[1] = (SK_U32)Val8;
26735                                         if (SkGeSirqEvent(pAC, IoC,
26736                                                 SK_HWEV_SET_FLOWMODE,
26737 @@ -5605,17 +5501,16 @@
26738                                         }
26739                                 }
26740                         }
26741 -                       else {
26742 +                       else { /* DualNet mode. */
26743 +
26744                                 /*
26745 -                                * Send an event with the new flow control
26746 -                                * mode to the SIRQ module.
26747 +                                * Send an event with the new link mode to
26748 +                                * the SIRQ module.
26749                                  */
26750 -                               EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
26751 -                                       pAC, LogPortIndex);
26752 +                               EventParam.Para32[0] = NetIndex;
26753                                 EventParam.Para32[1] = (SK_U32)Val8;
26754 -                               if (SkGeSirqEvent(pAC, IoC,
26755 -                                       SK_HWEV_SET_FLOWMODE, EventParam)
26756 -                                       > 0) {
26757 +                               if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_FLOWMODE,
26758 +                                       EventParam) > 0) {
26759
26760                                         SK_ERR_LOG(pAC, SK_ERRCL_SW,
26761                                                 SK_PNMI_ERR044,
26762 @@ -5625,15 +5520,14 @@
26763                                         return (SK_PNMI_ERR_GENERAL);
26764                                 }
26765                         }
26766 -                       Offset += sizeof(char);
26767 +                       Offset++;
26768                         break;
26769
26770                 case OID_SKGE_PHY_OPERATION_MODE :
26771 -                       /* Check the value range */
26772 -                       Val8 = *(pBuf + Offset);
26773 +                       /* Check the value range. */
26774                         if (Val8 == 0) {
26775 -                               /* mode of this port remains unchanged */
26776 -                               Offset += sizeof(char);
26777 +                               /* Mode of this port remains unchanged. */
26778 +                               Offset++;
26779                                 break;
26780                         }
26781                         if (Val8 < SK_MS_MODE_AUTO ||
26782 @@ -5644,34 +5538,51 @@
26783                                 return (SK_PNMI_ERR_BAD_VALUE);
26784                         }
26785
26786 -                       /* The preset ends here */
26787 +                       /* The PRESET ends here. */
26788                         if (Action == SK_PNMI_PRESET) {
26789
26790                                 return (SK_PNMI_ERR_OK);
26791                         }
26792
26793 -                       if (LogPortIndex == 0) {
26794 +                       if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26795 +                               if (LogPortIndex == 0) {
26796 +                                       /*
26797 +                                        * The virtual port consists of all currently
26798 +                                        * active ports. Find them and send an event
26799 +                                        * with new master/slave (role) mode to SIRQ.
26800 +                                        */
26801 +                                       for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;
26802 +                                               PhysPortIndex ++) {
26803
26804 -                               /*
26805 -                                * The virtual port consists of all currently
26806 -                                * active ports. Find them and send an event
26807 -                                * with new master/slave (role) mode to SIRQ.
26808 -                                */
26809 -                               for (PhysPortIndex = 0;
26810 -                                       PhysPortIndex < PhysPortMax;
26811 -                                       PhysPortIndex ++) {
26812 +                                               if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
26813 +                                                       continue;
26814 +                                               }
26815
26816 -                                       if (!pAC->Pnmi.Port[PhysPortIndex].
26817 -                                               ActiveFlag) {
26818 +                                               EventParam.Para32[0] = PhysPortIndex;
26819 +                                               EventParam.Para32[1] = (SK_U32)Val8;
26820 +                                               if (SkGeSirqEvent(pAC, IoC,
26821 +                                                       SK_HWEV_SET_ROLE,
26822 +                                                       EventParam) > 0) {
26823 +
26824 +                                                       SK_ERR_LOG(pAC, SK_ERRCL_SW,
26825 +                                                               SK_PNMI_ERR042,
26826 +                                                               SK_PNMI_ERR042MSG);
26827
26828 -                                               continue;
26829 +                                                       *pLen = 0;
26830 +                                                       return (SK_PNMI_ERR_GENERAL);
26831 +                                               }
26832                                         }
26833 -
26834 -                                       EventParam.Para32[0] = PhysPortIndex;
26835 +                               }
26836 +                               else {
26837 +                                       /*
26838 +                                        * Send an event with the new master/slave
26839 +                                        * (role) mode to the SIRQ module.
26840 +                                        */
26841 +                                       EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
26842 +                                               pAC, LogPortIndex);
26843                                         EventParam.Para32[1] = (SK_U32)Val8;
26844                                         if (SkGeSirqEvent(pAC, IoC,
26845 -                                               SK_HWEV_SET_ROLE,
26846 -                                               EventParam) > 0) {
26847 +                                               SK_HWEV_SET_ROLE, EventParam) > 0) {
26848
26849                                                 SK_ERR_LOG(pAC, SK_ERRCL_SW,
26850                                                         SK_PNMI_ERR042,
26851 @@ -5682,16 +5593,16 @@
26852                                         }
26853                                 }
26854                         }
26855 -                       else {
26856 +                       else { /* DualNet mode. */
26857 +
26858                                 /*
26859 -                                * Send an event with the new master/slave
26860 -                                * (role) mode to the SIRQ module.
26861 +                                * Send an event with the new link mode to
26862 +                                * the SIRQ module.
26863                                  */
26864 -                               EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
26865 -                                       pAC, LogPortIndex);
26866 +                               EventParam.Para32[0] = NetIndex;
26867                                 EventParam.Para32[1] = (SK_U32)Val8;
26868 -                               if (SkGeSirqEvent(pAC, IoC,
26869 -                                       SK_HWEV_SET_ROLE, EventParam) > 0) {
26870 +                               if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_ROLE,
26871 +                                       EventParam) > 0) {
26872
26873                                         SK_ERR_LOG(pAC, SK_ERRCL_SW,
26874                                                 SK_PNMI_ERR042,
26875 @@ -5701,16 +5612,13 @@
26876                                         return (SK_PNMI_ERR_GENERAL);
26877                                 }
26878                         }
26879 -
26880 -                       Offset += sizeof(char);
26881 +                       Offset++;
26882                         break;
26883
26884                 case OID_SKGE_SPEED_MODE:
26885 -                       /* Check the value range */
26886 -                       Val8 = *(pBuf + Offset);
26887 +                       /* Check the value range. */
26888                         if (Val8 == 0) {
26889 -
26890 -                               Offset += sizeof(char);
26891 +                               Offset++;
26892                                 break;
26893                         }
26894                         if (Val8 < (SK_LSPEED_AUTO) ||
26895 @@ -5721,29 +5629,49 @@
26896                                 return (SK_PNMI_ERR_BAD_VALUE);
26897                         }
26898
26899 -                       /* The preset ends here */
26900 +                       /* The PRESET ends here. */
26901                         if (Action == SK_PNMI_PRESET) {
26902
26903                                 return (SK_PNMI_ERR_OK);
26904                         }
26905
26906 -                       if (LogPortIndex == 0) {
26907 +                       if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26908 +                               if (LogPortIndex == 0) {
26909
26910 -                               /*
26911 -                                * The virtual port consists of all currently
26912 -                                * active ports. Find them and send an event
26913 -                                * with the new flow control mode to SIRQ.
26914 -                                */
26915 -                               for (PhysPortIndex = 0;
26916 -                                       PhysPortIndex < PhysPortMax;
26917 -                                       PhysPortIndex ++) {
26918 +                                       /*
26919 +                                        * The virtual port consists of all currently
26920 +                                        * active ports. Find them and send an event
26921 +                                        * with the new flow control mode to SIRQ.
26922 +                                        */
26923 +                                       for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;
26924 +                                               PhysPortIndex ++) {
26925
26926 -                                       if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
26927 +                                               if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
26928 +                                                       continue;
26929 +                                               }
26930
26931 -                                               continue;
26932 -                                       }
26933 +                                               EventParam.Para32[0] = PhysPortIndex;
26934 +                                               EventParam.Para32[1] = (SK_U32)Val8;
26935 +                                               if (SkGeSirqEvent(pAC, IoC,
26936 +                                                       SK_HWEV_SET_SPEED,
26937 +                                                       EventParam) > 0) {
26938 +
26939 +                                                       SK_ERR_LOG(pAC, SK_ERRCL_SW,
26940 +                                                               SK_PNMI_ERR045,
26941 +                                                               SK_PNMI_ERR045MSG);
26942
26943 -                                       EventParam.Para32[0] = PhysPortIndex;
26944 +                                                       *pLen = 0;
26945 +                                                       return (SK_PNMI_ERR_GENERAL);
26946 +                                               }
26947 +                                       }
26948 +                               }
26949 +                               else {
26950 +                                       /*
26951 +                                        * Send an event with the new flow control
26952 +                                        * mode to the SIRQ module.
26953 +                                        */
26954 +                                       EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
26955 +                                               pAC, LogPortIndex);
26956                                         EventParam.Para32[1] = (SK_U32)Val8;
26957                                         if (SkGeSirqEvent(pAC, IoC,
26958                                                 SK_HWEV_SET_SPEED,
26959 @@ -5758,16 +5686,15 @@
26960                                         }
26961                                 }
26962                         }
26963 -                       else {
26964 +                       else { /* DualNet mode. */
26965 +
26966                                 /*
26967 -                                * Send an event with the new flow control
26968 -                                * mode to the SIRQ module.
26969 +                                * Send an event with the new link mode to
26970 +                                * the SIRQ module.
26971                                  */
26972 -                               EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
26973 -                                       pAC, LogPortIndex);
26974 +                               EventParam.Para32[0] = NetIndex;
26975                                 EventParam.Para32[1] = (SK_U32)Val8;
26976 -                               if (SkGeSirqEvent(pAC, IoC,
26977 -                                       SK_HWEV_SET_SPEED,
26978 +                               if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_SPEED,
26979                                         EventParam) > 0) {
26980
26981                                         SK_ERR_LOG(pAC, SK_ERRCL_SW,
26982 @@ -5778,23 +5705,25 @@
26983                                         return (SK_PNMI_ERR_GENERAL);
26984                                 }
26985                         }
26986 -                       Offset += sizeof(char);
26987 +                       Offset++;
26988                         break;
26989
26990 -               case OID_SKGE_MTU :
26991 -                       /* Check the value range */
26992 -                       Val32 = *(SK_U32*)(pBuf + Offset);
26993 +               case OID_SKGE_MTU:
26994 +                       /* Check the value range. */
26995 +                       SK_PNMI_READ_U32((pBuf + Offset), Val32);
26996 +
26997                         if (Val32 == 0) {
26998 -                               /* mtu of this port remains unchanged */
26999 +                               /* MTU of this port remains unchanged. */
27000                                 Offset += sizeof(SK_U32);
27001                                 break;
27002                         }
27003 +
27004                         if (SK_DRIVER_PRESET_MTU(pAC, IoC, NetIndex, Val32) != 0) {
27005                                 *pLen = 0;
27006                                 return (SK_PNMI_ERR_BAD_VALUE);
27007                         }
27008
27009 -                       /* The preset ends here */
27010 +                       /* The PRESET ends here. */
27011                         if (Action == SK_PNMI_PRESET) {
27012                                 return (SK_PNMI_ERR_OK);
27013                         }
27014 @@ -5805,7 +5734,70 @@
27015
27016                         Offset += sizeof(SK_U32);
27017                         break;
27018 -
27019 +
27020 +#ifdef SK_PHY_LP_MODE
27021 +               case OID_SKGE_PHY_LP_MODE:
27022 +                       /* The PRESET ends here. */
27023 +                       if (Action == SK_PNMI_PRESET) {
27024 +
27025 +                               return (SK_PNMI_ERR_OK);
27026 +                       }
27027 +
27028 +                       if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
27029 +                               if (LogPortIndex == 0) {
27030 +                                       Offset = 0;
27031 +                                       continue;
27032 +                               }
27033 +                       }
27034 +                       /* Set value for physical port. */
27035 +                       PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);
27036 +                       CurrentPhyPowerState = pAC->GIni.GP[PhysPortIndex].PPhyPowerState;
27037 +
27038 +                       switch (Val8) {
27039 +                               case PHY_PM_OPERATIONAL_MODE:
27040 +                                       /* If LowPowerMode is active, we can leave it. */
27041 +                                       if (CurrentPhyPowerState) {
27042 +
27043 +                                               Val32 = SkGmLeaveLowPowerMode(pAC, IoC, PhysPortIndex);
27044 +
27045 +                                               if ((CurrentPhyPowerState == PHY_PM_DEEP_SLEEP) ||
27046 +                                                       (CurrentPhyPowerState == PHY_PM_IEEE_POWER_DOWN)) {
27047 +
27048 +                                                       SkDrvInitAdapter(pAC);
27049 +                                               }
27050 +                                               break;
27051 +                                       }
27052 +                                       else {
27053 +                                               *pLen = 0;
27054 +                                               return (SK_PNMI_ERR_GENERAL);
27055 +                                       }
27056 +                               case PHY_PM_DEEP_SLEEP:
27057 +                               case PHY_PM_IEEE_POWER_DOWN:
27058 +                                       /* If no LowPowerMode is active, we can enter it. */
27059 +                                       if (!CurrentPhyPowerState) {
27060 +                                               SkDrvDeInitAdapter(pAC);
27061 +                                       }
27062 +
27063 +                               case PHY_PM_ENERGY_DETECT:
27064 +                               case PHY_PM_ENERGY_DETECT_PLUS:
27065 +                                       /* If no LowPowerMode is active, we can enter it. */
27066 +                                       if (!CurrentPhyPowerState) {
27067 +
27068 +                                               Val32 = SkGmEnterLowPowerMode(pAC, IoC, PhysPortIndex, *pBuf);
27069 +                                               break;
27070 +                                       }
27071 +                                       else {
27072 +                                               *pLen = 0;
27073 +                                               return (SK_PNMI_ERR_GENERAL);
27074 +                                       }
27075 +                               default:
27076 +                                       *pLen = 0;
27077 +                                       return (SK_PNMI_ERR_BAD_VALUE);
27078 +                       }
27079 +                       Offset++;
27080 +                       break;
27081 +#endif /* SK_PHY_LP_MODE */
27082 +
27083                 default:
27084              SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR,
27085                  ("MacPrivateConf: Unknown OID should be handled before set"));
27086 @@ -5854,14 +5846,11 @@
27087         unsigned int    Limit;
27088         unsigned int    Offset;
27089         unsigned int    Entries;
27090 -
27091
27092 -       /*
27093 -        * Calculate instance if wished.
27094 -        */
27095 -       /* XXX Not yet implemented. Return always an empty table. */
27096 +       /* Not implemented yet. Return always an empty table. */
27097         Entries = 0;
27098
27099 +       /* Calculate instance if wished. */
27100         if ((Instance != (SK_U32)(-1))) {
27101
27102                 if ((Instance < 1) || (Instance > Entries)) {
27103 @@ -5878,12 +5867,10 @@
27104                 Limit = Entries;
27105         }
27106
27107 -       /*
27108 -        * Get/Set value
27109 -       */
27110 +       /* GET/SET value. */
27111         if (Action == SK_PNMI_GET) {
27112
27113 -               for (Offset=0; Index < Limit; Index ++) {
27114 +               for (Offset = 0; Index < Limit; Index ++) {
27115
27116                         switch (Id) {
27117
27118 @@ -5905,32 +5892,29 @@
27119                 *pLen = Offset;
27120         }
27121         else {
27122 -               /* Only MONITOR_ADMIN can be set */
27123 +               /* Only MONITOR_ADMIN can be set. */
27124                 if (Id != OID_SKGE_RLMT_MONITOR_ADMIN) {
27125
27126                         *pLen = 0;
27127                         return (SK_PNMI_ERR_READ_ONLY);
27128                 }
27129
27130 -               /* Check if the length is plausible */
27131 +               /* Check if the length is plausible. */
27132                 if (*pLen < (Limit - Index)) {
27133
27134                         return (SK_PNMI_ERR_TOO_SHORT);
27135                 }
27136 -               /* Okay, we have a wide value range */
27137 +               /* Okay, we have a wide value range. */
27138                 if (*pLen != (Limit - Index)) {
27139
27140                         *pLen = 0;
27141                         return (SK_PNMI_ERR_BAD_VALUE);
27142                 }
27143 -/*
27144 -               for (Offset=0; Index < Limit; Index ++) {
27145 -               }
27146 -*/
27147 -/*
27148 - * XXX Not yet implemented. Return always BAD_VALUE, because the table
27149 - * is empty.
27150 - */
27151 +
27152 +               /*
27153 +                * Not yet implemented. Return always BAD_VALUE,
27154 +                * because the table is empty.
27155 +                */
27156                 *pLen = 0;
27157                 return (SK_PNMI_ERR_BAD_VALUE);
27158         }
27159 @@ -5971,14 +5955,12 @@
27160         PortActiveFlag = SK_FALSE;
27161         PhysPortMax = pAC->GIni.GIMacsFound;
27162
27163 -       for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;
27164 -               PhysPortIndex ++) {
27165 +       for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax; PhysPortIndex ++) {
27166
27167                 pPrt = &pAC->GIni.GP[PhysPortIndex];
27168
27169 -               /* Check if the physical port is active */
27170 +               /* Check if the physical port is active. */
27171                 if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
27172 -
27173                         continue;
27174                 }
27175
27176 @@ -5987,12 +5969,13 @@
27177                 switch (Id) {
27178
27179                 case OID_SKGE_PHY_TYPE:
27180 -                       /* Check if it is the first active port */
27181 +                       /* Check if it is the first active port. */
27182                         if (*pBuf == 0) {
27183                                 Val32 = pPrt->PhyType;
27184                                 SK_PNMI_STORE_U32(pBuf, Val32);
27185                                 continue;
27186                         }
27187 +                       break;
27188
27189                 case OID_SKGE_LINK_CAP:
27190
27191 @@ -6006,7 +5989,7 @@
27192                         break;
27193
27194                 case OID_SKGE_LINK_MODE:
27195 -                       /* Check if it is the first active port */
27196 +                       /* Check if it is the first active port. */
27197                         if (*pBuf == 0) {
27198
27199                                 *pBuf = pPrt->PLinkModeConf;
27200 @@ -6014,9 +5997,8 @@
27201                         }
27202
27203                         /*
27204 -                        * If we find an active port with a different link
27205 -                        * mode than the first one we return a value that
27206 -                        * indicates that the link mode is indeterminated.
27207 +                        * If we find an active port with a different link mode
27208 +                        * than the first one we return indeterminated.
27209                          */
27210                         if (*pBuf != pPrt->PLinkModeConf) {
27211
27212 @@ -6025,10 +6007,10 @@
27213                         break;
27214
27215                 case OID_SKGE_LINK_MODE_STATUS:
27216 -                       /* Get the link mode of the physical port */
27217 +                       /* Get the link mode of the physical port. */
27218                         Val8 = CalculateLinkModeStatus(pAC, IoC, PhysPortIndex);
27219
27220 -                       /* Check if it is the first active port */
27221 +                       /* Check if it is the first active port. */
27222                         if (*pBuf == 0) {
27223
27224                                 *pBuf = Val8;
27225 @@ -6036,10 +6018,8 @@
27226                         }
27227
27228                         /*
27229 -                        * If we find an active port with a different link
27230 -                        * mode status than the first one we return a value
27231 -                        * that indicates that the link mode status is
27232 -                        * indeterminated.
27233 +                        * If we find an active port with a different link mode status
27234 +                        * than the first one we return indeterminated.
27235                          */
27236                         if (*pBuf != Val8) {
27237
27238 @@ -6048,10 +6028,10 @@
27239                         break;
27240
27241                 case OID_SKGE_LINK_STATUS:
27242 -                       /* Get the link status of the physical port */
27243 +                       /* Get the link status of the physical port. */
27244                         Val8 = CalculateLinkStatus(pAC, IoC, PhysPortIndex);
27245
27246 -                       /* Check if it is the first active port */
27247 +                       /* Check if it is the first active port. */
27248                         if (*pBuf == 0) {
27249
27250                                 *pBuf = Val8;
27251 @@ -6059,10 +6039,8 @@
27252                         }
27253
27254                         /*
27255 -                        * If we find an active port with a different link
27256 -                        * status than the first one, we return a value
27257 -                        * that indicates that the link status is
27258 -                        * indeterminated.
27259 +                        * If we find an active port with a different link status
27260 +                        * than the first one we return indeterminated.
27261                          */
27262                         if (*pBuf != Val8) {
27263
27264 @@ -6071,7 +6049,7 @@
27265                         break;
27266
27267                 case OID_SKGE_FLOWCTRL_CAP:
27268 -                       /* Check if it is the first active port */
27269 +                       /* Check if it is the first active port. */
27270                         if (*pBuf == 0) {
27271
27272                                 *pBuf = pPrt->PFlowCtrlCap;
27273 @@ -6086,7 +6064,7 @@
27274                         break;
27275
27276                 case OID_SKGE_FLOWCTRL_MODE:
27277 -                       /* Check if it is the first active port */
27278 +                       /* Check if it is the first active port. */
27279                         if (*pBuf == 0) {
27280
27281                                 *pBuf = pPrt->PFlowCtrlMode;
27282 @@ -6094,9 +6072,8 @@
27283                         }
27284
27285                         /*
27286 -                        * If we find an active port with a different flow
27287 -                        * control mode than the first one, we return a value
27288 -                        * that indicates that the mode is indeterminated.
27289 +                        * If we find an active port with a different flow-control mode
27290 +                        * than the first one we return indeterminated.
27291                          */
27292                         if (*pBuf != pPrt->PFlowCtrlMode) {
27293
27294 @@ -6105,7 +6082,7 @@
27295                         break;
27296
27297                 case OID_SKGE_FLOWCTRL_STATUS:
27298 -                       /* Check if it is the first active port */
27299 +                       /* Check if it is the first active port. */
27300                         if (*pBuf == 0) {
27301
27302                                 *pBuf = pPrt->PFlowCtrlStatus;
27303 @@ -6113,10 +6090,8 @@
27304                         }
27305
27306                         /*
27307 -                        * If we find an active port with a different flow
27308 -                        * control status than the first one, we return a
27309 -                        * value that indicates that the status is
27310 -                        * indeterminated.
27311 +                        * If we find an active port with a different flow-control status
27312 +                        * than the first one we return indeterminated.
27313                          */
27314                         if (*pBuf != pPrt->PFlowCtrlStatus) {
27315
27316 @@ -6125,7 +6100,7 @@
27317                         break;
27318
27319                 case OID_SKGE_PHY_OPERATION_CAP:
27320 -                       /* Check if it is the first active port */
27321 +                       /* Check if it is the first active port. */
27322                         if (*pBuf == 0) {
27323
27324                                 *pBuf = pPrt->PMSCap;
27325 @@ -6140,7 +6115,7 @@
27326                         break;
27327
27328                 case OID_SKGE_PHY_OPERATION_MODE:
27329 -                       /* Check if it is the first active port */
27330 +                       /* Check if it is the first active port. */
27331                         if (*pBuf == 0) {
27332
27333                                 *pBuf = pPrt->PMSMode;
27334 @@ -6148,9 +6123,8 @@
27335                         }
27336
27337                         /*
27338 -                        * If we find an active port with a different master/
27339 -                        * slave mode than the first one, we return a value
27340 -                        * that indicates that the mode is indeterminated.
27341 +                        * If we find an active port with a different master/slave mode
27342 +                        * than the first one we return indeterminated.
27343                          */
27344                         if (*pBuf != pPrt->PMSMode) {
27345
27346 @@ -6159,7 +6133,7 @@
27347                         break;
27348
27349                 case OID_SKGE_PHY_OPERATION_STATUS:
27350 -                       /* Check if it is the first active port */
27351 +                       /* Check if it is the first active port. */
27352                         if (*pBuf == 0) {
27353
27354                                 *pBuf = pPrt->PMSStatus;
27355 @@ -6167,10 +6141,8 @@
27356                         }
27357
27358                         /*
27359 -                        * If we find an active port with a different master/
27360 -                        * slave status than the first one, we return a
27361 -                        * value that indicates that the status is
27362 -                        * indeterminated.
27363 +                        * If we find an active port with a different master/slave status
27364 +                        * than the first one we return indeterminated.
27365                          */
27366                         if (*pBuf != pPrt->PMSStatus) {
27367
27368 @@ -6179,7 +6151,7 @@
27369                         break;
27370
27371                 case OID_SKGE_SPEED_MODE:
27372 -                       /* Check if it is the first active port */
27373 +                       /* Check if it is the first active port. */
27374                         if (*pBuf == 0) {
27375
27376                                 *pBuf = pPrt->PLinkSpeed;
27377 @@ -6187,9 +6159,8 @@
27378                         }
27379
27380                         /*
27381 -                        * If we find an active port with a different flow
27382 -                        * control mode than the first one, we return a value
27383 -                        * that indicates that the mode is indeterminated.
27384 +                        * If we find an active port with a different link speed
27385 +                        * than the first one we return indeterminated.
27386                          */
27387                         if (*pBuf != pPrt->PLinkSpeed) {
27388
27389 @@ -6198,7 +6169,7 @@
27390                         break;
27391
27392                 case OID_SKGE_SPEED_STATUS:
27393 -                       /* Check if it is the first active port */
27394 +                       /* Check if it is the first active port. */
27395                         if (*pBuf == 0) {
27396
27397                                 *pBuf = pPrt->PLinkSpeedUsed;
27398 @@ -6206,10 +6177,8 @@
27399                         }
27400
27401                         /*
27402 -                        * If we find an active port with a different flow
27403 -                        * control status than the first one, we return a
27404 -                        * value that indicates that the status is
27405 -                        * indeterminated.
27406 +                        * If we find an active port with a different link speed used
27407 +                        * than the first one we return indeterminated.
27408                          */
27409                         if (*pBuf != pPrt->PLinkSpeedUsed) {
27410
27411 @@ -6219,9 +6188,7 @@
27412                 }
27413         }
27414
27415 -       /*
27416 -        * If no port is active return an indeterminated answer
27417 -        */
27418 +       /* If no port is active return an indeterminated answer. */
27419         if (!PortActiveFlag) {
27420
27421                 switch (Id) {
27422 @@ -6324,7 +6291,7 @@
27423   *
27424   * Description:
27425   *     The COMMON module only tells us if the mode is half or full duplex.
27426 - *     But in the decade of auto sensing it is useful for the user to
27427 + *     But in the decade of auto sensing it is usefull for the user to
27428   *     know if the mode was negotiated or forced. Therefore we have a
27429   *     look to the mode, which was last used by the negotiation process.
27430   *
27431 @@ -6338,16 +6305,15 @@
27432  {
27433         SK_U8   Result;
27434
27435 -       /* Get the current mode, which can be full or half duplex */
27436 +       /* Get the current mode, which can be full or half duplex. */
27437         Result = pAC->GIni.GP[PhysPortIndex].PLinkModeStatus;
27438
27439 -       /* Check if no valid mode could be found (link is down) */
27440 +       /* Check if no valid mode could be found (link is down). */
27441         if (Result < SK_LMODE_STAT_HALF) {
27442
27443                 Result = SK_LMODE_STAT_UNKNOWN;
27444         }
27445         else if (pAC->GIni.GP[PhysPortIndex].PLinkMode >= SK_LMODE_AUTOHALF) {
27446 -
27447                 /*
27448                  * Auto-negotiation was used to bring up the link. Change
27449                  * the already found duplex status that it indicates
27450 @@ -6392,22 +6358,22 @@
27451         int                     Index;
27452         int                     Ret;
27453
27454 -
27455         SK_MEMSET(pKeyArr, 0, KeyArrLen);
27456
27457 -       /*
27458 -        * Get VPD key list
27459 -        */
27460 -       Ret = VpdKeys(pAC, IoC, (char *)&BufKeys, (int *)&BufKeysLen,
27461 +       /* Get VPD key list. */
27462 +       Ret = VpdKeys(pAC, IoC, BufKeys, (int *)&BufKeysLen,
27463                 (int *)pKeyNo);
27464 +
27465         if (Ret > 0) {
27466
27467 -               SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR014,
27468 -                       SK_PNMI_ERR014MSG);
27469 +               SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
27470 +                       (SK_PNMI_ERR014MSG));
27471
27472 +               /* Please read comment in Vpd(). */
27473 +               pAC->Pnmi.VpdKeyReadError = SK_TRUE;
27474                 return (SK_PNMI_ERR_GENERAL);
27475         }
27476 -       /* If no keys are available return now */
27477 +       /* If no keys are available return now. */
27478         if (*pKeyNo == 0 || BufKeysLen == 0) {
27479
27480                 return (SK_PNMI_ERR_OK);
27481 @@ -6415,12 +6381,12 @@
27482         /*
27483          * If the key list is too long for us trunc it and give a
27484          * errorlog notification. This case should not happen because
27485 -        * the maximum number of keys is limited due to RAM limitations
27486 +        * the maximum number of keys is limited due to RAM limitations.
27487          */
27488         if (*pKeyNo > SK_PNMI_VPD_ENTRIES) {
27489
27490 -               SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR015,
27491 -                       SK_PNMI_ERR015MSG);
27492 +               SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
27493 +                       (SK_PNMI_ERR015MSG));
27494
27495                 *pKeyNo = SK_PNMI_VPD_ENTRIES;
27496         }
27497 @@ -6433,14 +6399,14 @@
27498                 Offset ++) {
27499
27500                 if (BufKeys[Offset] != 0) {
27501 -
27502                         continue;
27503                 }
27504
27505                 if (Offset - StartOffset > SK_PNMI_VPD_KEY_SIZE) {
27506
27507 -                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR016,
27508 -                               SK_PNMI_ERR016MSG);
27509 +                       SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
27510 +                                          (SK_PNMI_ERR016MSG));
27511 +
27512                         return (SK_PNMI_ERR_GENERAL);
27513                 }
27514
27515 @@ -6451,7 +6417,7 @@
27516                 StartOffset = Offset + 1;
27517         }
27518
27519 -       /* Last key not zero terminated? Get it anyway */
27520 +       /* Last key not zero terminated? Get it anyway. */
27521         if (StartOffset < Offset) {
27522
27523                 SK_STRNCPY(pKeyArr + Index * SK_PNMI_VPD_KEY_SIZE,
27524 @@ -6480,19 +6446,18 @@
27525  {
27526         SK_EVPARA       EventParam;
27527
27528 -
27529         /* Was the module already updated during the current PNMI call? */
27530         if (pAC->Pnmi.SirqUpdatedFlag > 0) {
27531
27532                 return (SK_PNMI_ERR_OK);
27533         }
27534
27535 -       /* Send an synchronuous update event to the module */
27536 +       /* Send an synchronuous update event to the module. */
27537         SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
27538 -       if (SkGeSirqEvent(pAC, IoC, SK_HWEV_UPDATE_STAT, EventParam) > 0) {
27539 +
27540 +       if (SkGeSirqEvent(pAC, IoC, SK_HWEV_UPDATE_STAT, EventParam)) {
27541
27542 -               SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR047,
27543 -                       SK_PNMI_ERR047MSG);
27544 +               SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR047, SK_PNMI_ERR047MSG);
27545
27546                 return (SK_PNMI_ERR_GENERAL);
27547         }
27548 @@ -6520,21 +6485,19 @@
27549  {
27550         SK_EVPARA       EventParam;
27551
27552 -
27553         /* Was the module already updated during the current PNMI call? */
27554         if (pAC->Pnmi.RlmtUpdatedFlag > 0) {
27555
27556                 return (SK_PNMI_ERR_OK);
27557         }
27558
27559 -       /* Send an synchronuous update event to the module */
27560 +       /* Send an synchronuous update event to the module. */
27561         SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
27562         EventParam.Para32[0] = NetIndex;
27563         EventParam.Para32[1] = (SK_U32)-1;
27564         if (SkRlmtEvent(pAC, IoC, SK_RLMT_STATS_UPDATE, EventParam) > 0) {
27565
27566 -               SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR048,
27567 -                       SK_PNMI_ERR048MSG);
27568 +               SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR048, SK_PNMI_ERR048MSG);
27569
27570                 return (SK_PNMI_ERR_GENERAL);
27571         }
27572 @@ -6572,20 +6535,20 @@
27573                 return (SK_PNMI_ERR_OK);
27574         }
27575
27576 -       /* Send an update command to all MACs specified */
27577 +       /* Send an update command to all MACs specified. */
27578         for (MacIndex = FirstMac; MacIndex <= LastMac; MacIndex ++) {
27579
27580                 /*
27581                  * 2002-09-13 pweber:   Freeze the current SW counters.
27582                  *                      (That should be done as close as
27583                  *                      possible to the update of the
27584 -                *                      HW counters)
27585 +                *                      HW counters).
27586                  */
27587                 if (pAC->GIni.GIMacType == SK_MAC_XMAC) {
27588                         pAC->Pnmi.BufPort[MacIndex] = pAC->Pnmi.Port[MacIndex];
27589                 }
27590
27591 -               /* 2002-09-13 pweber:  Update the HW counter  */
27592 +               /* 2002-09-13 pweber:  Update the HW counter.  */
27593                 if (pAC->GIni.GIFunc.pFnMacUpdateStats(pAC, IoC, MacIndex) != 0) {
27594
27595                         return (SK_PNMI_ERR_GENERAL);
27596 @@ -6623,19 +6586,19 @@
27597         SK_U64                  Val = 0;
27598
27599
27600 -       if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {   /* Dual net mode */
27601 +       if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {   /* DualNet mode. */
27602
27603                 PhysPortIndex = NetIndex;
27604
27605                 Val = GetPhysStatVal(pAC, IoC, PhysPortIndex, StatIndex);
27606         }
27607 -       else {  /* Single Net mode */
27608 +       else {  /* SingleNet mode. */
27609
27610                 if (LogPortIndex == 0) {
27611
27612                         PhysPortMax = pAC->GIni.GIMacsFound;
27613
27614 -                       /* Add counter of all active ports */
27615 +                       /* Add counter of all active ports. */
27616                         for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;
27617                                 PhysPortIndex ++) {
27618
27619 @@ -6645,11 +6608,11 @@
27620                                 }
27621                         }
27622
27623 -                       /* Correct value because of port switches */
27624 +                       /* Correct value because of port switches. */
27625                         Val += pAC->Pnmi.VirtualCounterOffset[StatIndex];
27626                 }
27627                 else {
27628 -                       /* Get counter value of physical port */
27629 +                       /* Get counter value of physical port. */
27630                         PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);
27631
27632                         Val = GetPhysStatVal(pAC, IoC, PhysPortIndex, StatIndex);
27633 @@ -6695,7 +6658,7 @@
27634
27635         MacType = pAC->GIni.GIMacType;
27636
27637 -       /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
27638 +       /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
27639         if (MacType == SK_MAC_XMAC) {
27640                 pPnmiPrt = &pAC->Pnmi.BufPort[PhysPortIndex];
27641         }
27642 @@ -6763,7 +6726,7 @@
27643         case SK_PNMI_HTX_BURST:
27644         case SK_PNMI_HTX_EXCESS_DEF:
27645         case SK_PNMI_HTX_CARRIER:
27646 -               /* Not supported by GMAC */
27647 +               /* Not supported by GMAC. */
27648                 if (MacType == SK_MAC_GMAC) {
27649                         return (Val);
27650                 }
27651 @@ -6775,7 +6738,7 @@
27652                 break;
27653
27654         case SK_PNMI_HTX_MACC:
27655 -               /* GMAC only supports PAUSE MAC control frames */
27656 +               /* GMAC only supports PAUSE MAC control frames. */
27657                 if (MacType == SK_MAC_GMAC) {
27658                         HelpIndex = SK_PNMI_HTX_PMACC;
27659                 }
27660 @@ -6792,7 +6755,7 @@
27661
27662         case SK_PNMI_HTX_COL:
27663         case SK_PNMI_HRX_UNDERSIZE:
27664 -               /* Not supported by XMAC */
27665 +               /* Not supported by XMAC. */
27666                 if (MacType == SK_MAC_XMAC) {
27667                         return (Val);
27668                 }
27669 @@ -6804,7 +6767,7 @@
27670                 break;
27671
27672         case SK_PNMI_HTX_DEFFERAL:
27673 -               /* Not supported by GMAC */
27674 +               /* Not supported by GMAC. */
27675                 if (MacType == SK_MAC_GMAC) {
27676                         return (Val);
27677                 }
27678 @@ -6822,7 +6785,7 @@
27679                         HighVal = 0;
27680                 }
27681                 else {
27682 -                       /* Otherwise get contents of hardware register */
27683 +                       /* Otherwise get contents of hardware register. */
27684                         (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
27685                                                                                   StatAddr[StatIndex][MacType].Reg,
27686                                                                                   &LowVal);
27687 @@ -6831,7 +6794,7 @@
27688                 break;
27689
27690         case SK_PNMI_HRX_BADOCTET:
27691 -               /* Not supported by XMAC */
27692 +               /* Not supported by XMAC. */
27693                 if (MacType == SK_MAC_XMAC) {
27694                         return (Val);
27695                 }
27696 @@ -6850,7 +6813,7 @@
27697                 return (Val);
27698
27699         case SK_PNMI_HRX_LONGFRAMES:
27700 -               /* For XMAC the SW counter is managed by PNMI */
27701 +               /* For XMAC the SW counter is managed by PNMI. */
27702                 if (MacType == SK_MAC_XMAC) {
27703                         return (pPnmiPrt->StatRxLongFrameCts);
27704                 }
27705 @@ -6870,7 +6833,7 @@
27706                 Val = (((SK_U64)HighVal << 32) | (SK_U64)LowVal);
27707
27708                 if (MacType == SK_MAC_GMAC) {
27709 -                       /* For GMAC the SW counter is additionally managed by PNMI */
27710 +                       /* For GMAC the SW counter is additionally managed by PNMI. */
27711                         Val += pPnmiPrt->StatRxFrameTooLongCts;
27712                 }
27713                 else {
27714 @@ -6888,20 +6851,19 @@
27715                 break;
27716
27717         case SK_PNMI_HRX_SHORTS:
27718 -               /* Not supported by GMAC */
27719 +               /* Not supported by GMAC. */
27720                 if (MacType == SK_MAC_GMAC) {
27721                         /* GM_RXE_FRAG?? */
27722                         return (Val);
27723                 }
27724
27725                 /*
27726 -                * XMAC counts short frame errors even if link down (#10620)
27727 -                *
27728 -                * If link-down the counter remains constant
27729 +                * XMAC counts short frame errors even if link down (#10620).
27730 +                * If the link is down, the counter remains constant.
27731                  */
27732                 if (pPrt->PLinkModeStatus != SK_LMODE_STAT_UNKNOWN) {
27733
27734 -                       /* Otherwise get incremental difference */
27735 +                       /* Otherwise get incremental difference. */
27736                         (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
27737                                                                                   StatAddr[StatIndex][MacType].Reg,
27738                                                                                   &LowVal);
27739 @@ -6924,7 +6886,7 @@
27740         case SK_PNMI_HRX_IRLENGTH:
27741         case SK_PNMI_HRX_SYMBOL:
27742         case SK_PNMI_HRX_CEXT:
27743 -               /* Not supported by GMAC */
27744 +               /* Not supported by GMAC. */
27745                 if (MacType == SK_MAC_GMAC) {
27746                         return (Val);
27747                 }
27748 @@ -6936,7 +6898,7 @@
27749                 break;
27750
27751         case SK_PNMI_HRX_PMACC_ERR:
27752 -               /* For GMAC the SW counter is managed by PNMI */
27753 +               /* For GMAC the SW counter is managed by PNMI. */
27754                 if (MacType == SK_MAC_GMAC) {
27755                         return (pPnmiPrt->StatRxPMaccErr);
27756                 }
27757 @@ -6947,13 +6909,13 @@
27758                 HighVal = pPnmiPrt->CounterHigh[StatIndex];
27759                 break;
27760
27761 -       /* SW counter managed by PNMI */
27762 +       /* SW counter managed by PNMI. */
27763         case SK_PNMI_HTX_SYNC:
27764                 LowVal = (SK_U32)pPnmiPrt->StatSyncCts;
27765                 HighVal = (SK_U32)(pPnmiPrt->StatSyncCts >> 32);
27766                 break;
27767
27768 -       /* SW counter managed by PNMI */
27769 +       /* SW counter managed by PNMI. */
27770         case SK_PNMI_HTX_SYNC_OCTET:
27771                 LowVal = (SK_U32)pPnmiPrt->StatSyncOctetsCts;
27772                 HighVal = (SK_U32)(pPnmiPrt->StatSyncOctetsCts >> 32);
27773 @@ -6961,17 +6923,19 @@
27774
27775         case SK_PNMI_HRX_FCS:
27776                 /*
27777 -                * Broadcom filters FCS errors and counts it in
27778 -                * Receive Error Counter register
27779 +                * Broadcom filters FCS errors and counts them in
27780 +                * Receive Error Counter register.
27781                  */
27782                 if (pPrt->PhyType == SK_PHY_BCOM) {
27783 -                       /* do not read while not initialized (PHY_READ hangs!)*/
27784 +#ifdef GENESIS
27785 +                       /* Do not read while not initialized (PHY_READ hangs!). */
27786                         if (pPrt->PState != SK_PRT_RESET) {
27787                                 SkXmPhyRead(pAC, IoC, PhysPortIndex, PHY_BCOM_RE_CTR, &Word);
27788
27789                                 LowVal = Word;
27790                         }
27791                         HighVal = pPnmiPrt->CounterHigh[StatIndex];
27792 +#endif /* GENESIS */
27793                 }
27794                 else {
27795                         (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
27796 @@ -6991,7 +6955,7 @@
27797
27798         Val = (((SK_U64)HighVal << 32) | (SK_U64)LowVal);
27799
27800 -       /* Correct value because of possible XMAC reset. XMAC Errata #2 */
27801 +       /* Correct value because of possible XMAC reset (XMAC Errata #2). */
27802         Val += pPnmiPrt->CounterOffset[StatIndex];
27803
27804         return (Val);
27805 @@ -7016,22 +6980,21 @@
27806         unsigned int    PhysPortIndex;
27807         SK_EVPARA       EventParam;
27808
27809 -
27810         SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
27811
27812 -       /* Notify sensor module */
27813 +       /* Notify sensor module. */
27814         SkEventQueue(pAC, SKGE_I2C, SK_I2CEV_CLEAR, EventParam);
27815
27816 -       /* Notify RLMT module */
27817 +       /* Notify RLMT module. */
27818         EventParam.Para32[0] = NetIndex;
27819         EventParam.Para32[1] = (SK_U32)-1;
27820         SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STATS_CLEAR, EventParam);
27821         EventParam.Para32[1] = 0;
27822
27823 -       /* Notify SIRQ module */
27824 +       /* Notify SIRQ module. */
27825         SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_CLEAR_STAT, EventParam);
27826
27827 -       /* Notify CSUM module */
27828 +       /* Notify CSUM module. */
27829  #ifdef SK_USE_CSUM
27830         EventParam.Para32[0] = NetIndex;
27831         EventParam.Para32[1] = (SK_U32)-1;
27832 @@ -7039,7 +7002,7 @@
27833                 EventParam);
27834  #endif /* SK_USE_CSUM */
27835
27836 -       /* Clear XMAC statistic */
27837 +       /* Clear XMAC statistics. */
27838         for (PhysPortIndex = 0; PhysPortIndex <
27839                 (unsigned int)pAC->GIni.GIMacsFound; PhysPortIndex ++) {
27840
27841 @@ -7066,13 +7029,13 @@
27842                         PhysPortIndex].StatRxPMaccErr));
27843         }
27844
27845 -       /*
27846 -        * Clear local statistics
27847 -        */
27848 +       /* Clear local statistics. */
27849         SK_MEMSET((char *)&pAC->Pnmi.VirtualCounterOffset, 0,
27850                   sizeof(pAC->Pnmi.VirtualCounterOffset));
27851 +
27852         pAC->Pnmi.RlmtChangeCts = 0;
27853         pAC->Pnmi.RlmtChangeTime = 0;
27854 +
27855         SK_MEMSET((char *)&pAC->Pnmi.RlmtChangeEstimate.EstValue[0], 0,
27856                 sizeof(pAC->Pnmi.RlmtChangeEstimate.EstValue));
27857         pAC->Pnmi.RlmtChangeEstimate.EstValueIndex = 0;
27858 @@ -7109,23 +7072,21 @@
27859  SK_U32 TrapId,         /* SNMP ID of the trap */
27860  unsigned int Size)     /* Space needed for trap entry */
27861  {
27862 -       unsigned int            BufPad = pAC->Pnmi.TrapBufPad;
27863 -       unsigned int            BufFree = pAC->Pnmi.TrapBufFree;
27864 -       unsigned int            Beg = pAC->Pnmi.TrapQueueBeg;
27865 -       unsigned int            End = pAC->Pnmi.TrapQueueEnd;
27866 +       unsigned int    BufPad = pAC->Pnmi.TrapBufPad;
27867 +       unsigned int    BufFree = pAC->Pnmi.TrapBufFree;
27868 +       unsigned int    Beg = pAC->Pnmi.TrapQueueBeg;
27869 +       unsigned int    End = pAC->Pnmi.TrapQueueEnd;
27870         char                    *pBuf = &pAC->Pnmi.TrapBuf[0];
27871         int                     Wrap;
27872 -       unsigned int            NeededSpace;
27873 -       unsigned int            EntrySize;
27874 +       unsigned int    NeededSpace;
27875 +       unsigned int    EntrySize;
27876         SK_U32                  Val32;
27877         SK_U64                  Val64;
27878
27879 -
27880 -       /* Last byte of entry will get a copy of the entry length */
27881 +       /* Last byte of entry will get a copy of the entry length. */
27882         Size ++;
27883
27884 -       /*
27885 -        * Calculate needed buffer space */
27886 +       /* Calculate needed buffer space. */
27887         if (Beg >= Size) {
27888
27889                 NeededSpace = Size;
27890 @@ -7140,7 +7101,7 @@
27891          * Check if enough buffer space is provided. Otherwise
27892          * free some entries. Leave one byte space between begin
27893          * and end of buffer to make it possible to detect whether
27894 -        * the buffer is full or empty
27895 +        * the buffer is full or empty.
27896          */
27897         while (BufFree < NeededSpace + 1) {
27898
27899 @@ -7179,13 +7140,13 @@
27900         }
27901         BufFree -= NeededSpace;
27902
27903 -       /* Save the current offsets */
27904 +       /* Save the current offsets. */
27905         pAC->Pnmi.TrapQueueBeg = Beg;
27906         pAC->Pnmi.TrapQueueEnd = End;
27907         pAC->Pnmi.TrapBufPad = BufPad;
27908         pAC->Pnmi.TrapBufFree = BufFree;
27909
27910 -       /* Initialize the trap entry */
27911 +       /* Initialize the trap entry. */
27912         *(pBuf + Beg + Size - 1) = (char)Size;
27913         *(pBuf + Beg) = (char)Size;
27914         Val32 = (pAC->Pnmi.TrapUnique) ++;
27915 @@ -7220,7 +7181,6 @@
27916         unsigned int    Len;
27917         unsigned int    DstOff = 0;
27918
27919 -
27920         while (Trap != End) {
27921
27922                 Len = (unsigned int)*(pBuf + Trap);
27923 @@ -7265,7 +7225,6 @@
27924         unsigned int    Entries = 0;
27925         unsigned int    TotalLen = 0;
27926
27927 -
27928         while (Trap != End) {
27929
27930                 Len = (unsigned int)*(pBuf + Trap);
27931 @@ -7322,14 +7281,14 @@
27932         unsigned int    DescrLen;
27933         SK_U32          Val32;
27934
27935 -
27936 -       /* Get trap buffer entry */
27937 +       /* Get trap buffer entry. */
27938         DescrLen = SK_STRLEN(pAC->I2c.SenTable[SensorIndex].SenDesc);
27939 +
27940         pBuf = GetTrapEntry(pAC, TrapId,
27941                 SK_PNMI_TRAP_SENSOR_LEN_BASE + DescrLen);
27942         Offset = SK_PNMI_TRAP_SIMPLE_LEN;
27943
27944 -       /* Store additionally sensor trap related data */
27945 +       /* Store additionally sensor trap related data. */
27946         Val32 = OID_SKGE_SENSOR_INDEX;
27947         SK_PNMI_STORE_U32(pBuf + Offset, Val32);
27948         *(pBuf + Offset + 4) = 4;
27949 @@ -7374,7 +7333,6 @@
27950         char    *pBuf;
27951         SK_U32  Val32;
27952
27953 -
27954         pBuf = GetTrapEntry(pAC, OID_SKGE_TRAP_RLMT_CHANGE_PORT,
27955                 SK_PNMI_TRAP_RLMT_CHANGE_LEN);
27956
27957 @@ -7402,7 +7360,6 @@
27958         char    *pBuf;
27959         SK_U32  Val32;
27960
27961 -
27962         pBuf = GetTrapEntry(pAC, TrapId, SK_PNMI_TRAP_RLMT_PORT_LEN);
27963
27964         Val32 = OID_SKGE_RLMT_PORT_INDEX;
27965 @@ -7422,12 +7379,11 @@
27966   *     Nothing
27967   */
27968  PNMI_STATIC void CopyMac(
27969 -char *pDst,            /* Pointer to destination buffer */
27970 +char           *pDst,  /* Pointer to destination buffer */
27971  SK_MAC_ADDR *pMac)     /* Pointer of Source */
27972  {
27973         int     i;
27974
27975 -
27976         for (i = 0; i < sizeof(SK_MAC_ADDR); i ++) {
27977
27978                 *(pDst + i) = pMac->a[i];
27979 @@ -7465,19 +7421,22 @@
27980  SK_U32 NetIndex)       /* NetIndex (0..n), in single net mode allways zero */
27981  {
27982
27983 +       int i;
27984 +       unsigned int HwPortIndex;
27985 +
27986         SK_U32  RetCode = SK_PNMI_ERR_GENERAL;
27987
27988 -       /*
27989 -        * Check instance. We only handle single instance variables
27990 -        */
27991 -       if (Instance != (SK_U32)(-1) && Instance != 1) {
27992 +       /* Check instance. We only handle single instance variables. */
27993 +       if ((Instance != (SK_U32)(-1))) {
27994
27995                 *pLen = 0;
27996                 return (SK_PNMI_ERR_UNKNOWN_INST);
27997         }
27998 +
27999 +       /* Get hardware port index */
28000 +       HwPortIndex = NetIndex;
28001
28002 -
28003 -    /* Check length */
28004 +    /* Check length. */
28005      switch (Id) {
28006
28007      case OID_PNP_CAPABILITIES:
28008 @@ -7515,14 +7474,10 @@
28009          break;
28010      }
28011
28012 -    /*
28013 -        * Perform action
28014 -        */
28015 +       /* Perform action. */
28016         if (Action == SK_PNMI_GET) {
28017
28018 -               /*
28019 -                * Get value
28020 -                */
28021 +               /* Get value. */
28022                 switch (Id) {
28023
28024                 case OID_PNP_CAPABILITIES:
28025 @@ -7530,18 +7485,21 @@
28026                         break;
28027
28028                 case OID_PNP_QUERY_POWER:
28029 -                       /* The Windows DDK describes: An OID_PNP_QUERY_POWER requests
28030 -                        the miniport to indicate whether it can transition its NIC
28031 -                        to the low-power state.
28032 -                        A miniport driver must always return NDIS_STATUS_SUCCESS
28033 -                        to a query of OID_PNP_QUERY_POWER. */
28034 +                       /*
28035 +                        * The Windows DDK describes: An OID_PNP_QUERY_POWER requests
28036 +                        * the miniport to indicate whether it can transition its NIC
28037 +                        * to the low-power state.
28038 +                        * A miniport driver must always return NDIS_STATUS_SUCCESS
28039 +                        * to a query of OID_PNP_QUERY_POWER.
28040 +                        */
28041                         *pLen = sizeof(SK_DEVICE_POWER_STATE);
28042              RetCode = SK_PNMI_ERR_OK;
28043                         break;
28044
28045 -                       /* NDIS handles these OIDs as write-only.
28046 +                       /*
28047 +                        * NDIS handles these OIDs as write-only.
28048                          * So in case of get action the buffer with written length = 0
28049 -                        * is returned
28050 +                        * is returned.
28051                          */
28052                 case OID_PNP_SET_POWER:
28053                 case OID_PNP_ADD_WAKE_UP_PATTERN:
28054 @@ -7551,7 +7509,7 @@
28055                         break;
28056
28057                 case OID_PNP_ENABLE_WAKE_UP:
28058 -                       RetCode = SkPowerGetEnableWakeUp(pAC, IoC, pBuf, pLen);
28059 +                       RetCode = SkPowerGetEnableWakeUp(pAC, IoC, HwPortIndex, pBuf, pLen);
28060                         break;
28061
28062                 default:
28063 @@ -7562,31 +7520,49 @@
28064                 return (RetCode);
28065         }
28066
28067 -
28068 -       /*
28069 -        * Perform preset or set
28070 -        */
28071 +       /* Perform PRESET or SET. */
28072
28073 -       /* POWER module does not support PRESET action */
28074 +       /* The POWER module does not support PRESET action. */
28075         if (Action == SK_PNMI_PRESET) {
28076 +
28077                 return (SK_PNMI_ERR_OK);
28078         }
28079
28080 +       /* */
28081 +       i= HwPortIndex;
28082 +
28083         switch (Id) {
28084         case OID_PNP_SET_POWER:
28085 -               RetCode = SkPowerSetPower(pAC, IoC, pBuf, pLen);
28086 +               /* Dual net mode? */
28087 +               for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
28088 +                       if (RetCode = SkPowerSetPower(pAC, IoC, i, pBuf, pLen)) {
28089 +                               break;
28090 +                       }
28091 +               }
28092                 break;
28093
28094         case OID_PNP_ADD_WAKE_UP_PATTERN:
28095 -               RetCode = SkPowerAddWakeUpPattern(pAC, IoC, pBuf, pLen);
28096 +               for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
28097 +                       if (RetCode = SkPowerAddWakeUpPattern(pAC, IoC, i, pBuf, pLen)) {
28098 +                               break;
28099 +                       }
28100 +               }
28101                 break;
28102
28103         case OID_PNP_REMOVE_WAKE_UP_PATTERN:
28104 -               RetCode = SkPowerRemoveWakeUpPattern(pAC, IoC, pBuf, pLen);
28105 +               for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
28106 +                       if (RetCode = SkPowerRemoveWakeUpPattern(pAC, IoC, i, pBuf, pLen)) {
28107 +                               break;
28108 +                       }
28109 +               }
28110                 break;
28111
28112         case OID_PNP_ENABLE_WAKE_UP:
28113 -               RetCode = SkPowerSetEnableWakeUp(pAC, IoC, pBuf, pLen);
28114 +               for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
28115 +                       if (RetCode = SkPowerSetEnableWakeUp(pAC, IoC, i, pBuf, pLen)) {
28116 +                               break;
28117 +                       }
28118 +               }
28119                 break;
28120
28121         default:
28122 @@ -7600,7 +7576,7 @@
28123  #ifdef SK_DIAG_SUPPORT
28124  /*****************************************************************************
28125   *
28126 - * DiagActions - OID handler function of Diagnostic driver
28127 + * DiagActions - OID handler function of Diagnostic driver
28128   *
28129   * Description:
28130   *     The code is simple. No description necessary.
28131 @@ -7627,22 +7603,17 @@
28132  unsigned int TableIndex, /* Index to the Id table */
28133  SK_U32 NetIndex)       /* NetIndex (0..n), in single net mode always zero */
28134  {
28135 -
28136         SK_U32  DiagStatus;
28137         SK_U32  RetCode = SK_PNMI_ERR_GENERAL;
28138
28139 -       /*
28140 -        * Check instance. We only handle single instance variables.
28141 -        */
28142 +       /* Check instance. We only handle single instance variables. */
28143         if (Instance != (SK_U32)(-1) && Instance != 1) {
28144
28145                 *pLen = 0;
28146                 return (SK_PNMI_ERR_UNKNOWN_INST);
28147         }
28148
28149 -       /*
28150 -        * Check length.
28151 -        */
28152 +    /* Check length. */
28153         switch (Id) {
28154
28155         case OID_SKGE_DIAG_MODE:
28156 @@ -7660,10 +7631,9 @@
28157         }
28158
28159         /* Perform action. */
28160 -
28161 -       /* GET value. */
28162         if (Action == SK_PNMI_GET) {
28163
28164 +               /* Get value. */
28165                 switch (Id) {
28166
28167                 case OID_SKGE_DIAG_MODE:
28168 @@ -7678,14 +7648,15 @@
28169                         RetCode = SK_PNMI_ERR_GENERAL;
28170                         break;
28171                 }
28172 -               return (RetCode);
28173 +               return (RetCode);
28174         }
28175
28176         /* From here SET or PRESET value. */
28177
28178         /* PRESET value is not supported. */
28179         if (Action == SK_PNMI_PRESET) {
28180 -               return (SK_PNMI_ERR_OK);
28181 +
28182 +               return (SK_PNMI_ERR_OK);
28183         }
28184
28185         /* SET value. */
28186 @@ -7697,7 +7668,7 @@
28187
28188                                 /* Attach the DIAG to this adapter. */
28189                                 case SK_DIAG_ATTACHED:
28190 -                                       /* Check if we come from running */
28191 +                                       /* Check if we come from running. */
28192                                         if (pAC->Pnmi.DiagAttached == SK_DIAG_RUNNING) {
28193
28194                                                 RetCode = SkDrvLeaveDiagMode(pAC);
28195 @@ -7732,7 +7703,7 @@
28196                                                 /* If DiagMode is not active, we can enter it. */
28197                                                 if (!pAC->DiagModeActive) {
28198
28199 -                                                       RetCode = SkDrvEnterDiagMode(pAC);
28200 +                                                       RetCode = SkDrvEnterDiagMode(pAC);
28201                                                 }
28202                                                 else {
28203
28204 @@ -7751,7 +7722,7 @@
28205                                         break;
28206
28207                                 case SK_DIAG_IDLE:
28208 -                                       /* Check if we come from running */
28209 +                                       /* Check if we come from running. */
28210                                         if (pAC->Pnmi.DiagAttached == SK_DIAG_RUNNING) {
28211
28212                                                 RetCode = SkDrvLeaveDiagMode(pAC);
28213 @@ -7797,7 +7768,7 @@
28214
28215  /*****************************************************************************
28216   *
28217 - * Vct - OID handler function of  OIDs
28218 + * Vct - OID handler function of OIDs for Virtual Cable Tester (VCT)
28219   *
28220   * Description:
28221   *     The code is simple. No description necessary.
28222 @@ -7833,153 +7804,150 @@
28223         SK_U32          PhysPortIndex;
28224         SK_U32          Limit;
28225         SK_U32          Offset;
28226 -       SK_BOOL         Link;
28227 -       SK_U32          RetCode = SK_PNMI_ERR_GENERAL;
28228 -       int             i;
28229 +       SK_U32          RetCode;
28230 +       int                     i;
28231         SK_EVPARA       Para;
28232 -       SK_U32          CableLength;
28233 -
28234 -       /*
28235 -        * Calculate the port indexes from the instance.
28236 -        */
28237 +
28238 +       RetCode = SK_PNMI_ERR_GENERAL;
28239 +
28240 +       /* Calculate the port indexes from the instance. */
28241         PhysPortMax = pAC->GIni.GIMacsFound;
28242         LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax);
28243 -
28244 +
28245         /* Dual net mode? */
28246         if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
28247                 LogPortMax--;
28248         }
28249 -
28250 +
28251         if ((Instance != (SK_U32) (-1))) {
28252 -               /* Check instance range. */
28253 -               if ((Instance < 2) || (Instance > LogPortMax)) {
28254 -                       *pLen = 0;
28255 -                       return (SK_PNMI_ERR_UNKNOWN_INST);
28256 -               }
28257 -
28258 +               /*
28259 +                * Get one instance of that OID, so check the instance range:
28260 +                * There is no virtual port with an Instance == 1, so we get
28261 +                * the values from one physical port only.
28262 +                */
28263                 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
28264                         PhysPortIndex = NetIndex;
28265                 }
28266                 else {
28267 +                       if ((Instance < 2) || (Instance > LogPortMax)) {
28268 +                               *pLen = 0;
28269 +                               return (SK_PNMI_ERR_UNKNOWN_INST);
28270 +                       }
28271                         PhysPortIndex = Instance - 2;
28272                 }
28273                 Limit = PhysPortIndex + 1;
28274         }
28275         else {
28276                 /*
28277 -                * Instance == (SK_U32) (-1), get all Instances of that OID.
28278 -                *
28279 -                * Not implemented yet. May be used in future releases.
28280 +                * Instance == (SK_U32) (-1), so get all instances of that OID.
28281 +                * There is no virtual port with an Instance == 1, so we get
28282 +                * the values from all physical ports.
28283                  */
28284                 PhysPortIndex = 0;
28285                 Limit = PhysPortMax;
28286         }
28287 -
28288 -       pPrt = &pAC->GIni.GP[PhysPortIndex];
28289 -       if (pPrt->PHWLinkUp) {
28290 -               Link = SK_TRUE;
28291 -       }
28292 -       else {
28293 -               Link = SK_FALSE;
28294 -       }
28295 -
28296 -       /* Check MAC type */
28297 -       if (pPrt->PhyType != SK_PHY_MARV_COPPER) {
28298 +
28299 +       /* Check MAC type. */
28300 +       if ((Id != OID_SKGE_VCT_CAPABILITIES) &&
28301 +               (pAC->GIni.GP[PhysPortIndex].PhyType != SK_PHY_MARV_COPPER)) {
28302                 *pLen = 0;
28303 -               return (SK_PNMI_ERR_GENERAL);
28304 +               return (SK_PNMI_ERR_NOT_SUPPORTED);
28305         }
28306 -
28307 -       /* Initialize backup data pointer. */
28308 -       pVctBackupData = &pAC->Pnmi.VctBackup[PhysPortIndex];
28309 -
28310 -       /* Check action type */
28311 +
28312 +       /* Check action type. */
28313         if (Action == SK_PNMI_GET) {
28314 -               /* Check length */
28315 +               /* Check length. */
28316                 switch (Id) {
28317 -
28318 +
28319                 case OID_SKGE_VCT_GET:
28320                         if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_PNMI_VCT)) {
28321                                 *pLen = (Limit - PhysPortIndex) * sizeof(SK_PNMI_VCT);
28322                                 return (SK_PNMI_ERR_TOO_SHORT);
28323                         }
28324                         break;
28325 -
28326 +
28327                 case OID_SKGE_VCT_STATUS:
28328 +               case OID_SKGE_VCT_CAPABILITIES:
28329                         if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U8)) {
28330                                 *pLen = (Limit - PhysPortIndex) * sizeof(SK_U8);
28331                                 return (SK_PNMI_ERR_TOO_SHORT);
28332                         }
28333                         break;
28334 -
28335 +
28336                 default:
28337                         *pLen = 0;
28338                         return (SK_PNMI_ERR_GENERAL);
28339                 }
28340 -
28341 -               /* Get value */
28342 +
28343 +               /* Get value. */
28344                 Offset = 0;
28345                 for (; PhysPortIndex < Limit; PhysPortIndex++) {
28346 +
28347 +                       pPrt = &pAC->GIni.GP[PhysPortIndex];
28348 +
28349                         switch (Id) {
28350 -
28351 +
28352                         case OID_SKGE_VCT_GET:
28353 -                               if ((Link == SK_FALSE) &&
28354 +                               if (!pPrt->PHWLinkUp &&
28355                                         (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_PENDING)) {
28356 +
28357                                         RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_FALSE);
28358 +
28359                                         if (RetCode == 0) {
28360 -                                               pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_PENDING;
28361 -                                               pAC->Pnmi.VctStatus[PhysPortIndex] |=
28362 -                                                       (SK_PNMI_VCT_NEW_VCT_DATA | SK_PNMI_VCT_TEST_DONE);
28363 -
28364 -                                               /* Copy results for later use to PNMI struct. */
28365 -                                               for (i = 0; i < 4; i++)  {
28366 -                                                       if (pPrt->PMdiPairSts[i] == SK_PNMI_VCT_NORMAL_CABLE) {
28367 -                                                               if ((pPrt->PMdiPairLen[i] > 35) && (pPrt->PMdiPairLen[i] < 0xff)) {
28368 -                                                                       pPrt->PMdiPairSts[i] = SK_PNMI_VCT_IMPEDANCE_MISMATCH;
28369 -                                                               }
28370 -                                                       }
28371 -                                                       if ((pPrt->PMdiPairLen[i] > 35) && (pPrt->PMdiPairLen[i] != 0xff)) {
28372 -                                                               CableLength = 1000 * (((175 * pPrt->PMdiPairLen[i]) / 210) - 28);
28373 -                                                       }
28374 -                                                       else {
28375 -                                                               CableLength = 0;
28376 -                                                       }
28377 -                                                       pVctBackupData->PMdiPairLen[i] = CableLength;
28378 -                                                       pVctBackupData->PMdiPairSts[i] = pPrt->PMdiPairSts[i];
28379 -                                               }
28380 +
28381 +                                               /* VCT test is finished, so save the data. */
28382 +                                               VctGetResults(pAC, IoC, PhysPortIndex);
28383
28384                                                 Para.Para32[0] = PhysPortIndex;
28385                                                 Para.Para32[1] = -1;
28386                                                 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Para);
28387 -                                               SkEventDispatcher(pAC, IoC);
28388 -                                       }
28389 -                                       else {
28390 -                                               ; /* VCT test is running. */
28391 +
28392 +                                               /* SkEventDispatcher(pAC, IoC); */
28393                                         }
28394                                 }
28395 -
28396 +
28397 +                               /* Initialize backup data pointer. */
28398 +                               pVctBackupData = &pAC->Pnmi.VctBackup[PhysPortIndex];
28399 +
28400                                 /* Get all results. */
28401                                 CheckVctStatus(pAC, IoC, pBuf, Offset, PhysPortIndex);
28402 -                               Offset += sizeof(SK_U8);
28403 +
28404 +                               Offset++;
28405                                 *(pBuf + Offset) = pPrt->PCableLen;
28406 -                               Offset += sizeof(SK_U8);
28407 +                               Offset++;
28408                                 for (i = 0; i < 4; i++)  {
28409 -                                       SK_PNMI_STORE_U32((pBuf + Offset), pVctBackupData->PMdiPairLen[i]);
28410 +
28411 +                                       SK_PNMI_STORE_U32((pBuf + Offset), pVctBackupData->MdiPairLen[i]);
28412                                         Offset += sizeof(SK_U32);
28413                                 }
28414                                 for (i = 0; i < 4; i++)  {
28415 -                                       *(pBuf + Offset) = pVctBackupData->PMdiPairSts[i];
28416 -                                       Offset += sizeof(SK_U8);
28417 +
28418 +                                       *(pBuf + Offset) = pVctBackupData->MdiPairSts[i];
28419 +                                       Offset++;
28420                                 }
28421 -
28422 +
28423                                 RetCode = SK_PNMI_ERR_OK;
28424                                 break;
28425 -
28426 +
28427                         case OID_SKGE_VCT_STATUS:
28428                                 CheckVctStatus(pAC, IoC, pBuf, Offset, PhysPortIndex);
28429 -                               Offset += sizeof(SK_U8);
28430 +
28431 +                               Offset++;
28432                                 RetCode = SK_PNMI_ERR_OK;
28433                                 break;
28434 -
28435 +
28436 +                       case OID_SKGE_VCT_CAPABILITIES:
28437 +                               if (pPrt->PhyType != SK_PHY_MARV_COPPER) {
28438 +                                       *(pBuf + Offset) = SK_PNMI_VCT_NOT_SUPPORTED;
28439 +                               }
28440 +                               else {
28441 +                                       *(pBuf + Offset) = SK_PNMI_VCT_SUPPORTED;
28442 +                               }
28443 +                               Offset++;
28444 +
28445 +                               RetCode = SK_PNMI_ERR_OK;
28446 +                               break;
28447 +
28448                         default:
28449                                 *pLen = 0;
28450                                 return (SK_PNMI_ERR_GENERAL);
28451 @@ -7987,15 +7955,15 @@
28452                 } /* for */
28453                 *pLen = Offset;
28454                 return (RetCode);
28455 -
28456 +
28457         } /* if SK_PNMI_GET */
28458 -
28459 +
28460         /*
28461          * From here SET or PRESET action. Check if the passed
28462          * buffer length is plausible.
28463          */
28464 -
28465 -       /* Check length */
28466 +
28467 +       /* Check length. */
28468         switch (Id) {
28469         case OID_SKGE_VCT_SET:
28470                 if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U32)) {
28471 @@ -8003,42 +7971,45 @@
28472                         return (SK_PNMI_ERR_TOO_SHORT);
28473                 }
28474                 break;
28475 -
28476 +
28477         default:
28478                 *pLen = 0;
28479                 return (SK_PNMI_ERR_GENERAL);
28480         }
28481 -
28482 -       /*
28483 -        * Perform preset or set.
28484 -        */
28485 -
28486 +
28487 +       /* Perform PRESET or SET. */
28488 +
28489         /* VCT does not support PRESET action. */
28490         if (Action == SK_PNMI_PRESET) {
28491 +
28492                 return (SK_PNMI_ERR_OK);
28493         }
28494 -
28495 +
28496         Offset = 0;
28497         for (; PhysPortIndex < Limit; PhysPortIndex++) {
28498 +
28499 +               pPrt = &pAC->GIni.GP[PhysPortIndex];
28500 +
28501                 switch (Id) {
28502                 case OID_SKGE_VCT_SET: /* Start VCT test. */
28503 -                       if (Link == SK_FALSE) {
28504 +                       if (!pPrt->PHWLinkUp) {
28505                                 SkGeStopPort(pAC, IoC, PhysPortIndex, SK_STOP_ALL, SK_SOFT_RST);
28506 -
28507 +
28508                                 RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_TRUE);
28509 +
28510                                 if (RetCode == 0) { /* RetCode: 0 => Start! */
28511                                         pAC->Pnmi.VctStatus[PhysPortIndex] |= SK_PNMI_VCT_PENDING;
28512 -                                       pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_NEW_VCT_DATA;
28513 -                                       pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_LINK;
28514 -
28515 -                                       /*
28516 -                                        * Start VCT timer counter.
28517 -                                        */
28518 -                                       SK_MEMSET((char *) &Para, 0, sizeof(Para));
28519 +                                       pAC->Pnmi.VctStatus[PhysPortIndex] &=
28520 +                                               ~(SK_PNMI_VCT_NEW_VCT_DATA | SK_PNMI_VCT_LINK);
28521 +
28522 +                                       /* Start VCT timer counter. */
28523 +                                       SK_MEMSET((char *)&Para, 0, sizeof(Para));
28524                                         Para.Para32[0] = PhysPortIndex;
28525                                         Para.Para32[1] = -1;
28526 -                                       SkTimerStart(pAC, IoC, &pAC->Pnmi.VctTimeout[PhysPortIndex].VctTimer,
28527 -                                               4000000, SKGE_PNMI, SK_PNMI_EVT_VCT_RESET, Para);
28528 +
28529 +                                       SkTimerStart(pAC, IoC, &pAC->Pnmi.VctTimeout[PhysPortIndex],
28530 +                                               SK_PNMI_VCT_TIMER_CHECK, SKGE_PNMI, SK_PNMI_EVT_VCT_RESET, Para);
28531 +
28532                                         SK_PNMI_STORE_U32((pBuf + Offset), RetCode);
28533                                         RetCode = SK_PNMI_ERR_OK;
28534                                 }
28535 @@ -8054,7 +8025,7 @@
28536                         }
28537                         Offset += sizeof(SK_U32);
28538                         break;
28539 -
28540 +
28541                 default:
28542                         *pLen = 0;
28543                         return (SK_PNMI_ERR_GENERAL);
28544 @@ -8066,6 +8037,65 @@
28545  } /* Vct */
28546
28547
28548 +PNMI_STATIC void VctGetResults(
28549 +SK_AC          *pAC,
28550 +SK_IOC         IoC,
28551 +SK_U32         Port)
28552 +{
28553 +       SK_GEPORT       *pPrt;
28554 +       int                     i;
28555 +       SK_U8           PairLen;
28556 +       SK_U8           PairSts;
28557 +       SK_U32          MinLength;
28558 +       SK_U32          CableLength;
28559 +
28560 +       pPrt = &pAC->GIni.GP[Port];
28561 +
28562 +       if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) {
28563 +               MinLength = 25;
28564 +       }
28565 +       else {
28566 +               MinLength = 35;
28567 +       }
28568 +
28569 +       /* Copy results for later use to PNMI struct. */
28570 +       for (i = 0; i < 4; i++)  {
28571 +
28572 +               PairLen = pPrt->PMdiPairLen[i];
28573 +
28574 +               if (((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) == 0) && (i > 1)) {
28575 +                       PairSts = SK_PNMI_VCT_NOT_PRESENT;
28576 +               }
28577 +               else {
28578 +                       PairSts = pPrt->PMdiPairSts[i];
28579 +               }
28580 +
28581 +               if ((PairSts == SK_PNMI_VCT_NORMAL_CABLE) &&
28582 +                       (PairLen > 28) && (PairLen < 0xff)) {
28583 +
28584 +                       PairSts = SK_PNMI_VCT_IMPEDANCE_MISMATCH;
28585 +               }
28586 +
28587 +               /* Ignore values <= MinLength, the linear factor is 4/5. */
28588 +               if ((PairLen > MinLength) && (PairLen < 0xff)) {
28589 +
28590 +                       CableLength = 1000UL * (PairLen - MinLength) * 4 / 5;
28591 +               }
28592 +               else {
28593 +                       /* No cable or short cable. */
28594 +                       CableLength = 0;
28595 +               }
28596 +
28597 +               pAC->Pnmi.VctBackup[Port].MdiPairLen[i] = CableLength;
28598 +               pAC->Pnmi.VctBackup[Port].MdiPairSts[i] = PairSts;
28599 +       }
28600 +
28601 +       pAC->Pnmi.VctStatus[Port] &= ~SK_PNMI_VCT_PENDING;
28602 +       pAC->Pnmi.VctStatus[Port] |= (SK_PNMI_VCT_NEW_VCT_DATA |
28603 +               SK_PNMI_VCT_TEST_DONE);
28604 +
28605 +} /* GetVctResults */
28606 +
28607  PNMI_STATIC void CheckVctStatus(
28608  SK_AC          *pAC,
28609  SK_IOC         IoC,
28610 @@ -8075,54 +8105,57 @@
28611  {
28612         SK_GEPORT       *pPrt;
28613         SK_PNMI_VCT     *pVctData;
28614 +       SK_U8           VctStatus;
28615         SK_U32          RetCode;
28616 -
28617 +
28618         pPrt = &pAC->GIni.GP[PhysPortIndex];
28619 -
28620 +
28621         pVctData = (SK_PNMI_VCT *) (pBuf + Offset);
28622         pVctData->VctStatus = SK_PNMI_VCT_NONE;
28623 -
28624 +
28625 +       VctStatus = pAC->Pnmi.VctStatus[PhysPortIndex];
28626 +
28627         if (!pPrt->PHWLinkUp) {
28628 -
28629 +
28630                 /* Was a VCT test ever made before? */
28631 -               if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_TEST_DONE) {
28632 -                       if ((pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_LINK)) {
28633 +               if (VctStatus & SK_PNMI_VCT_TEST_DONE) {
28634 +                       if (VctStatus & SK_PNMI_VCT_LINK) {
28635                                 pVctData->VctStatus |= SK_PNMI_VCT_OLD_VCT_DATA;
28636                         }
28637                         else {
28638                                 pVctData->VctStatus |= SK_PNMI_VCT_NEW_VCT_DATA;
28639                         }
28640                 }
28641 -
28642 +
28643                 /* Check VCT test status. */
28644                 RetCode = SkGmCableDiagStatus(pAC,IoC, PhysPortIndex, SK_FALSE);
28645 +
28646                 if (RetCode == 2) { /* VCT test is running. */
28647                         pVctData->VctStatus |= SK_PNMI_VCT_RUNNING;
28648                 }
28649                 else { /* VCT data was copied to pAC here. Check PENDING state. */
28650 -                       if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_PENDING) {
28651 +                       if (VctStatus & SK_PNMI_VCT_PENDING) {
28652                                 pVctData->VctStatus |= SK_PNMI_VCT_NEW_VCT_DATA;
28653                         }
28654                 }
28655 -
28656 +
28657                 if (pPrt->PCableLen != 0xff) { /* Old DSP value. */
28658                         pVctData->VctStatus |= SK_PNMI_VCT_OLD_DSP_DATA;
28659                 }
28660         }
28661         else {
28662 -
28663                 /* Was a VCT test ever made before? */
28664 -               if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_TEST_DONE) {
28665 +               if (VctStatus & SK_PNMI_VCT_TEST_DONE) {
28666                         pVctData->VctStatus &= ~SK_PNMI_VCT_NEW_VCT_DATA;
28667                         pVctData->VctStatus |= SK_PNMI_VCT_OLD_VCT_DATA;
28668                 }
28669 -
28670 +
28671                 /* DSP only valid in 100/1000 modes. */
28672 -               if (pAC->GIni.GP[PhysPortIndex].PLinkSpeedUsed !=
28673 -                       SK_LSPEED_STAT_10MBPS) {
28674 +               if (pPrt->PLinkSpeedUsed != SK_LSPEED_STAT_10MBPS) {
28675                         pVctData->VctStatus |= SK_PNMI_VCT_NEW_DSP_DATA;
28676                 }
28677         }
28678 +
28679  } /* CheckVctStatus */
28680
28681
28682 @@ -8165,29 +8198,29 @@
28683         ReturnCode = SK_PNMI_ERR_GENERAL;
28684
28685         SK_MEMCPY(&Mode, pBuf, sizeof(SK_I32));
28686 -       SK_MEMCPY(&Oid, (char *) pBuf + sizeof(SK_I32), sizeof(SK_U32));
28687 +       SK_MEMCPY(&Oid, (char *)pBuf + sizeof(SK_I32), sizeof(SK_U32));
28688         HeaderLength = sizeof(SK_I32) + sizeof(SK_U32);
28689         *pLen = *pLen - HeaderLength;
28690 -       SK_MEMCPY((char *) pBuf + sizeof(SK_I32), (char *) pBuf + HeaderLength, *pLen);
28691 +       SK_MEMCPY((char *)pBuf + sizeof(SK_I32), (char *)pBuf + HeaderLength, *pLen);
28692
28693         switch(Mode) {
28694         case SK_GET_SINGLE_VAR:
28695 -               ReturnCode = SkPnmiGetVar(pAC, IoC, Oid,
28696 -                               (char *) pBuf + sizeof(SK_I32), pLen,
28697 +               ReturnCode = SkPnmiGetVar(pAC, IoC, Oid,
28698 +                               (char *)pBuf + sizeof(SK_I32), pLen,
28699                                 ((SK_U32) (-1)), NetIndex);
28700                 SK_PNMI_STORE_U32(pBuf, ReturnCode);
28701                 *pLen = *pLen + sizeof(SK_I32);
28702                 break;
28703         case SK_PRESET_SINGLE_VAR:
28704 -               ReturnCode = SkPnmiPreSetVar(pAC, IoC, Oid,
28705 -                               (char *) pBuf + sizeof(SK_I32), pLen,
28706 +               ReturnCode = SkPnmiPreSetVar(pAC, IoC, Oid,
28707 +                               (char *)pBuf + sizeof(SK_I32), pLen,
28708                                 ((SK_U32) (-1)), NetIndex);
28709                 SK_PNMI_STORE_U32(pBuf, ReturnCode);
28710                 *pLen = *pLen + sizeof(SK_I32);
28711                 break;
28712         case SK_SET_SINGLE_VAR:
28713 -               ReturnCode = SkPnmiSetVar(pAC, IoC, Oid,
28714 -                               (char *) pBuf + sizeof(SK_I32), pLen,
28715 +               ReturnCode = SkPnmiSetVar(pAC, IoC, Oid,
28716 +                               (char *)pBuf + sizeof(SK_I32), pLen,
28717                                 ((SK_U32) (-1)), NetIndex);
28718                 SK_PNMI_STORE_U32(pBuf, ReturnCode);
28719                 *pLen = *pLen + sizeof(SK_I32);
28720 @@ -8208,3 +8241,86 @@
28721         return (ReturnCode);
28722
28723  } /* SkGeIocGen */
28724 +
28725 +#ifdef SK_ASF
28726 +/*****************************************************************************
28727 + *
28728 + * Asf
28729 + *
28730 + * Description:
28731 + *  The code is simple. No description necessary.
28732 + *
28733 + * Returns:
28734 + *  SK_PNMI_ERR_OK           The request was successfully performed.
28735 + *  SK_PNMI_ERR_GENERAL      A general severe internal error occured.
28736 + *  SK_PNMI_ERR_TOO_SHORT    The passed buffer is too short to contain
28737 + *                           the correct data (e.g. a 32bit value is
28738 + *                           needed, but a 16 bit value was passed).
28739 + *  SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
28740 + *                           exist (e.g. port instance 3 on a two port
28741 + *                           adapter.
28742 + */
28743 +
28744 +PNMI_STATIC int Asf(
28745 +SK_AC *pAC,     /* Pointer to adapter context */
28746 +SK_IOC IoC,     /* IO context handle */
28747 +int Action,     /* GET/PRESET/SET action */
28748 +SK_U32 Id,      /* Object ID that is to be processed */
28749 +char *pBuf,     /* Buffer used for the management data transfer */
28750 +unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */
28751 +SK_U32 Instance,    /* Instance (1..n) that is to be queried or -1 */
28752 +unsigned int TableIndex, /* Index to the Id table */
28753 +SK_U32 NetIndex)    /* NetIndex (0..n), in single net mode always zero */
28754 +{
28755 +    SK_U32  RetCode = SK_PNMI_ERR_GENERAL;
28756 +
28757 +    /*
28758 +     * Check instance. We only handle single instance variables.
28759 +     */
28760 +    if (Instance != (SK_U32)(-1) && Instance != 1) {
28761 +
28762 +        *pLen = 0;
28763 +        return (SK_PNMI_ERR_UNKNOWN_INST);
28764 +    }
28765 +
28766 +    /* Perform action. */
28767 +    /* GET value. */
28768 +    if (Action == SK_PNMI_GET) {
28769 +        switch (Id) {
28770 +            case OID_SKGE_ASF:
28771 +                RetCode = SkAsfGet(pAC, IoC, (SK_U8 *) pBuf, pLen);
28772 +                break;
28773 +            default:
28774 +                RetCode = SkAsfGetOid( pAC, IoC, Id, Instance, (SK_U8 *) pBuf, pLen );
28775 +                break;
28776 +        }
28777 +
28778 +        return (RetCode);
28779 +    }
28780 +
28781 +    /* PRESET value. */
28782 +    if (Action == SK_PNMI_PRESET) {
28783 +        switch (Id) {
28784 +            case OID_SKGE_ASF:
28785 +                RetCode = SkAsfPreSet(pAC, IoC, (SK_U8 *) pBuf, pLen);
28786 +                break;
28787 +            default:
28788 +                RetCode = SkAsfPreSetOid( pAC, IoC, Id, Instance, (SK_U8 *) pBuf, pLen );
28789 +                break;
28790 +        }
28791 +    }
28792 +
28793 +    /* SET value. */
28794 +    if (Action == SK_PNMI_SET) {
28795 +        switch (Id) {
28796 +            case OID_SKGE_ASF:
28797 +                RetCode = SkAsfSet(pAC, IoC, (SK_U8 *) pBuf, pLen);
28798 +                break;
28799 +            default:
28800 +                RetCode = SkAsfSetOid( pAC, IoC, Id, Instance, (SK_U8 *) pBuf, pLen );
28801 +                break;
28802 +        }
28803 +    }
28804 +    return (RetCode);
28805 +}
28806 +#endif /* SK_ASF */
28807 diff -ruN linux/drivers/net/sk98lin/skgesirq.c linux-new/drivers/net/sk98lin/skgesirq.c
28808 --- linux/drivers/net/sk98lin/skgesirq.c        2006-09-20 05:42:06.000000000 +0200
28809 +++ linux-new/drivers/net/sk98lin/skgesirq.c    2006-07-28 14:13:54.000000000 +0200
28810 @@ -2,23 +2,24 @@
28811   *
28812   * Name:       skgesirq.c
28813   * Project:    Gigabit Ethernet Adapters, Common Modules
28814 - * Version:    $Revision$
28815 - * Date:       $Date$
28816 + * Version:    $Revision$
28817 + * Date:       $Date$
28818   * Purpose:    Special IRQ module
28819   *
28820   ******************************************************************************/
28821
28822  /******************************************************************************
28823   *
28824 + *     LICENSE:
28825   *     (C)Copyright 1998-2002 SysKonnect.
28826 - *     (C)Copyright 2002-2003 Marvell.
28827 + *     (C)Copyright 2002-2006 Marvell.
28828   *
28829   *     This program is free software; you can redistribute it and/or modify
28830   *     it under the terms of the GNU General Public License as published by
28831   *     the Free Software Foundation; either version 2 of the License, or
28832   *     (at your option) any later version.
28833 - *
28834   *     The information in this file is provided "AS IS" without warranty.
28835 + *     /LICENSE
28836   *
28837   ******************************************************************************/
28838
28839 @@ -38,7 +39,7 @@
28840   *     right after this ISR.
28841   *
28842   *     The Interrupt source register of the adapter is NOT read by this module.
28843 - *  SO if the drivers implementor needs a while loop around the
28844 + *     SO if the drivers implementor needs a while loop around the
28845   *     slow data paths interrupt bits, he needs to call the SkGeSirqIsr() for
28846   *     each loop entered.
28847   *
28848 @@ -46,11 +47,6 @@
28849   *
28850   */
28851
28852 -#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
28853 -static const char SysKonnectFileId[] =
28854 -       "@(#) $Id$ (C) Marvell.";
28855 -#endif
28856 -
28857  #include "h/skdrv1st.h"                /* Driver Specific Definitions */
28858  #ifndef SK_SLIM
28859  #include "h/skgepnmi.h"                /* PNMI Definitions */
28860 @@ -58,6 +54,13 @@
28861  #endif
28862  #include "h/skdrv2nd.h"                /* Adapter Control and Driver specific Def. */
28863
28864 +/* local variables ************************************************************/
28865 +
28866 +#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
28867 +static const char SysKonnectFileId[] =
28868 +       "@(#) $Id$ (C) Marvell.";
28869 +#endif
28870 +
28871  /* local function prototypes */
28872  #ifdef GENESIS
28873  static int     SkGePortCheckUpXmac(SK_AC*, SK_IOC, int, SK_BOOL);
28874 @@ -86,7 +89,7 @@
28875         XM_RXF_511B,
28876         XM_RXF_1023B,
28877         XM_RXF_MAX_SZ
28878 -} ;
28879 +};
28880  #endif /* GENESIS */
28881
28882  #ifdef __C2MAN__
28883 @@ -109,8 +112,8 @@
28884   * Returns: N/A
28885   */
28886  static void SkHWInitDefSense(
28887 -SK_AC  *pAC,   /* adapter context */
28888 -SK_IOC IoC,    /* IO context */
28889 +SK_AC  *pAC,   /* Adapter Context */
28890 +SK_IOC IoC,    /* I/O context */
28891  int            Port)   /* Port Index (MAC_1 + n) */
28892  {
28893         SK_GEPORT       *pPrt;          /* GIni Port struct pointer */
28894 @@ -119,7 +122,7 @@
28895
28896         pPrt->PAutoNegTimeOut = 0;
28897
28898 -       if (pPrt->PLinkModeConf != SK_LMODE_AUTOSENSE) {
28899 +       if (pPrt->PLinkModeConf != (SK_U8)SK_LMODE_AUTOSENSE) {
28900                 pPrt->PLinkMode = pPrt->PLinkModeConf;
28901                 return;
28902         }
28903 @@ -145,8 +148,8 @@
28904   *
28905   */
28906  static SK_U8 SkHWSenseGetNext(
28907 -SK_AC  *pAC,   /* adapter context */
28908 -SK_IOC IoC,    /* IO context */
28909 +SK_AC  *pAC,   /* Adapter Context */
28910 +SK_IOC IoC,    /* I/O context */
28911  int            Port)   /* Port Index (MAC_1 + n) */
28912  {
28913         SK_GEPORT       *pPrt;          /* GIni Port struct pointer */
28914 @@ -155,18 +158,18 @@
28915
28916         pPrt->PAutoNegTimeOut = 0;
28917
28918 -    if (pPrt->PLinkModeConf != (SK_U8)SK_LMODE_AUTOSENSE) {
28919 +       if (pPrt->PLinkModeConf != (SK_U8)SK_LMODE_AUTOSENSE) {
28920                 /* Leave all as configured */
28921                 return(pPrt->PLinkModeConf);
28922         }
28923
28924 -    if (pPrt->PLinkMode == (SK_U8)SK_LMODE_AUTOFULL) {
28925 +       if (pPrt->PLinkMode == (SK_U8)SK_LMODE_AUTOFULL) {
28926                 /* Return next mode AUTOBOTH */
28927 -        return ((SK_U8)SK_LMODE_AUTOBOTH);
28928 +               return((SK_U8)SK_LMODE_AUTOBOTH);
28929         }
28930
28931         /* Return default autofull */
28932 -    return ((SK_U8)SK_LMODE_AUTOFULL);
28933 +       return((SK_U8)SK_LMODE_AUTOFULL);
28934  }      /* SkHWSenseGetNext */
28935
28936
28937 @@ -179,8 +182,8 @@
28938   * Returns: N/A
28939   */
28940  static void SkHWSenseSetNext(
28941 -SK_AC  *pAC,           /* adapter context */
28942 -SK_IOC IoC,            /* IO context */
28943 +SK_AC  *pAC,           /* Adapter Context */
28944 +SK_IOC IoC,            /* I/O context */
28945  int            Port,           /* Port Index (MAC_1 + n) */
28946  SK_U8  NewMode)        /* New Mode to be written in sense mode */
28947  {
28948 @@ -190,7 +193,7 @@
28949
28950         pPrt->PAutoNegTimeOut = 0;
28951
28952 -    if (pPrt->PLinkModeConf != (SK_U8)SK_LMODE_AUTOSENSE) {
28953 +       if (pPrt->PLinkModeConf != (SK_U8)SK_LMODE_AUTOSENSE) {
28954                 return;
28955         }
28956
28957 @@ -214,8 +217,8 @@
28958   * Returns: N/A
28959   */
28960  void SkHWLinkDown(
28961 -SK_AC  *pAC,           /* adapter context */
28962 -SK_IOC IoC,            /* IO context */
28963 +SK_AC  *pAC,           /* Adapter Context */
28964 +SK_IOC IoC,            /* I/O context */
28965  int            Port)           /* Port Index (MAC_1 + n) */
28966  {
28967         SK_GEPORT       *pPrt;          /* GIni Port struct pointer */
28968 @@ -227,26 +230,28 @@
28969
28970         /* Disable Receiver and Transmitter */
28971         SkMacRxTxDisable(pAC, IoC, Port);
28972 -
28973 +
28974         /* Init default sense mode */
28975         SkHWInitDefSense(pAC, IoC, Port);
28976
28977 -       if (pPrt->PHWLinkUp == SK_FALSE) {
28978 +       if (!pPrt->PHWLinkUp) {
28979                 return;
28980         }
28981
28982 -       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
28983 +       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
28984                 ("Link down Port %d\n", Port));
28985
28986         /* Set Link to DOWN */
28987         pPrt->PHWLinkUp = SK_FALSE;
28988
28989 +#ifndef SK_SLIM
28990         /* Reset Port stati */
28991 -    pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN;
28992 -    pPrt->PFlowCtrlStatus = (SK_U8)SK_FLOW_STAT_NONE;
28993 +       pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN;
28994 +       pPrt->PFlowCtrlStatus = (SK_U8)SK_FLOW_STAT_NONE;
28995         pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_INDETERMINATED;
28996 +#endif /* !SK_SLIM */
28997
28998 -       /* Re-init Phy especially when the AutoSense default is set now */
28999 +       /* Re-init PHY especially when the AutoSense default is set now */
29000         SkMacInitPhy(pAC, IoC, Port, SK_FALSE);
29001
29002         /* GP0: used for workaround of Rev. C Errata 2 */
29003 @@ -265,9 +270,9 @@
29004   *
29005   * Returns: N/A
29006   */
29007 -static void SkHWLinkUp(
29008 -SK_AC  *pAC,   /* adapter context */
29009 -SK_IOC IoC,    /* IO context */
29010 +void SkHWLinkUp(
29011 +SK_AC  *pAC,   /* Adapter Context */
29012 +SK_IOC IoC,    /* I/O context */
29013  int            Port)   /* Port Index (MAC_1 + n) */
29014  {
29015         SK_GEPORT       *pPrt;          /* GIni Port struct pointer */
29016 @@ -280,12 +285,14 @@
29017         }
29018
29019         pPrt->PHWLinkUp = SK_TRUE;
29020 +
29021 +#ifndef SK_SLIM
29022         pPrt->PAutoNegFail = SK_FALSE;
29023 -    pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN;
29024 +       pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN;
29025
29026 -    if (pPrt->PLinkMode != (SK_U8)SK_LMODE_AUTOHALF &&
29027 -        pPrt->PLinkMode != (SK_U8)SK_LMODE_AUTOFULL &&
29028 -        pPrt->PLinkMode != (SK_U8)SK_LMODE_AUTOBOTH) {
29029 +       if (pPrt->PLinkMode != (SK_U8)SK_LMODE_AUTOHALF &&
29030 +               pPrt->PLinkMode != (SK_U8)SK_LMODE_AUTOFULL &&
29031 +               pPrt->PLinkMode != (SK_U8)SK_LMODE_AUTOBOTH) {
29032                 /* Link is up and no Auto-negotiation should be done */
29033
29034                 /* Link speed should be the configured one */
29035 @@ -293,7 +300,9 @@
29036                 case SK_LSPEED_AUTO:
29037                         /* default is 1000 Mbps */
29038                 case SK_LSPEED_1000MBPS:
29039 -                       pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_1000MBPS;
29040 +                       pPrt->PLinkSpeedUsed = (SK_U8)
29041 +                               ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) ?
29042 +                                SK_LSPEED_STAT_1000MBPS : SK_LSPEED_STAT_100MBPS;
29043                         break;
29044                 case SK_LSPEED_100MBPS:
29045                         pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_100MBPS;
29046 @@ -304,19 +313,19 @@
29047                 }
29048
29049                 /* Set Link Mode Status */
29050 -               if (pPrt->PLinkMode == SK_LMODE_FULL) {
29051 -                       pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_FULL;
29052 -               }
29053 -               else {
29054 -            pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_HALF;
29055 -               }
29056 +               pPrt->PLinkModeStatus = (SK_U8)
29057 +                       ((pPrt->PLinkMode == (SK_U8)SK_LMODE_FULL) ?
29058 +                        SK_LMODE_STAT_FULL : SK_LMODE_STAT_HALF);
29059
29060                 /* No flow control without auto-negotiation */
29061 -        pPrt->PFlowCtrlStatus = (SK_U8)SK_FLOW_STAT_NONE;
29062 +               pPrt->PFlowCtrlStatus = (SK_U8)SK_FLOW_STAT_NONE;
29063 +#endif /* !SK_SLIM */
29064
29065                 /* enable Rx/Tx */
29066 -        (void)SkMacRxTxEnable(pAC, IoC, Port);
29067 +               (void)SkMacRxTxEnable(pAC, IoC, Port);
29068 +#ifndef SK_SLIM
29069         }
29070 +#endif /* !SK_SLIM */
29071  }      /* SkHWLinkUp */
29072
29073
29074 @@ -329,14 +338,16 @@
29075   * Returns: N/A
29076   */
29077  static void SkMacParity(
29078 -SK_AC  *pAC,   /* adapter context */
29079 -SK_IOC IoC,    /* IO context */
29080 -int            Port)   /* Port Index of the port failed */
29081 +SK_AC  *pAC,   /* Adapter Context */
29082 +SK_IOC IoC,    /* I/O context */
29083 +int            Port)   /* Port Index (MAC_1 + n) */
29084  {
29085         SK_EVPARA       Para;
29086         SK_GEPORT       *pPrt;          /* GIni Port struct pointer */
29087         SK_U32          TxMax;          /* Tx Max Size Counter */
29088
29089 +       TxMax = 0;
29090 +
29091         pPrt = &pAC->GIni.GP[Port];
29092
29093         /* Clear IRQ Tx Parity Error */
29094 @@ -346,7 +357,7 @@
29095                 SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_CLR_PERR);
29096         }
29097  #endif /* GENESIS */
29098 -
29099 +
29100  #ifdef YUKON
29101         if (pAC->GIni.GIYukon) {
29102                 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
29103 @@ -355,7 +366,7 @@
29104                         pAC->GIni.GIChipRev == 0) ? GMF_CLI_TX_FC : GMF_CLI_TX_PE));
29105         }
29106  #endif /* YUKON */
29107 -
29108 +
29109         if (pPrt->PCheckPar) {
29110
29111                 if (Port == MAC_1) {
29112 @@ -366,7 +377,7 @@
29113                 }
29114                 Para.Para64 = Port;
29115                 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
29116 -
29117 +
29118                 Para.Para32[0] = Port;
29119                 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
29120
29121 @@ -378,18 +389,18 @@
29122         if (pAC->GIni.GIGenesis) {
29123                 /* Snap statistic counters */
29124                 (void)SkXmUpdateStats(pAC, IoC, Port);
29125 -
29126 +
29127                 (void)SkXmMacStatistic(pAC, IoC, Port, XM_TXF_MAX_SZ, &TxMax);
29128         }
29129  #endif /* GENESIS */
29130 -
29131 +
29132  #ifdef YUKON
29133         if (pAC->GIni.GIYukon) {
29134
29135                 (void)SkGmMacStatistic(pAC, IoC, Port, GM_TXF_1518B, &TxMax);
29136         }
29137  #endif /* YUKON */
29138 -
29139 +
29140         if (TxMax > 0) {
29141                 /* From now on check the parity */
29142                 pPrt->PCheckPar = SK_TRUE;
29143 @@ -399,15 +410,15 @@
29144
29145  /******************************************************************************
29146   *
29147 - *     SkGeHwErr() - Hardware Error service routine
29148 + *     SkGeYuHwErr() - Hardware Error service routine (Genesis and Yukon)
29149   *
29150   * Description: handles all HW Error interrupts
29151   *
29152   * Returns: N/A
29153   */
29154 -static void SkGeHwErr(
29155 -SK_AC  *pAC,           /* adapter context */
29156 -SK_IOC IoC,            /* IO context */
29157 +static void SkGeYuHwErr(
29158 +SK_AC  *pAC,           /* Adapter Context */
29159 +SK_IOC IoC,            /* I/O context */
29160  SK_U32 HwStatus)       /* Interrupt status word */
29161  {
29162         SK_EVPARA       Para;
29163 @@ -423,10 +434,10 @@
29164                 }
29165
29166                 /* Reset all bits in the PCI STATUS register */
29167 -               SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);
29168 -
29169 +               SK_IN16(IoC, PCI_C(pAC, PCI_STATUS), &Word);
29170 +
29171                 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
29172 -        SK_OUT16(IoC, PCI_C(PCI_STATUS), (SK_U16)(Word | PCI_ERRBITS));
29173 +               SK_OUT16(IoC, PCI_C(pAC, PCI_STATUS), (SK_U16)(Word | PCI_ERRBITS));
29174                 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
29175
29176                 Para.Para64 = 0;
29177 @@ -461,7 +472,7 @@
29178                 }
29179         }
29180  #endif /* GENESIS */
29181 -
29182 +
29183  #ifdef YUKON
29184         if (pAC->GIni.GIYukon) {
29185                 /* This is necessary only for Rx timing measurements */
29186 @@ -484,14 +495,18 @@
29187  #endif /* YUKON */
29188
29189         if ((HwStatus & IS_RAM_RD_PAR) != 0) {
29190 +
29191                 SK_OUT16(IoC, B3_RI_CTRL, RI_CLR_RD_PERR);
29192 +
29193                 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E014, SKERR_SIRQ_E014MSG);
29194                 Para.Para64 = 0;
29195                 SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
29196         }
29197
29198         if ((HwStatus & IS_RAM_WR_PAR) != 0) {
29199 +
29200                 SK_OUT16(IoC, B3_RI_CTRL, RI_CLR_WR_PERR);
29201 +
29202                 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E015, SKERR_SIRQ_E015MSG);
29203                 Para.Para64 = 0;
29204                 SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
29205 @@ -512,7 +527,7 @@
29206                 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E018, SKERR_SIRQ_E018MSG);
29207                 Para.Para64 = MAC_1;
29208                 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
29209 -
29210 +
29211                 Para.Para32[0] = MAC_1;
29212                 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
29213         }
29214 @@ -524,37 +539,297 @@
29215                 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E019, SKERR_SIRQ_E019MSG);
29216                 Para.Para64 = MAC_2;
29217                 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
29218 -
29219 +
29220                 Para.Para32[0] = MAC_2;
29221                 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
29222         }
29223 -}      /* SkGeHwErr */
29224 +}      /* SkGeYuHwErr */
29225 +
29226 +#ifdef YUK2
29227 +/******************************************************************************
29228 + *
29229 + *     SkYuk2HwPortErr() - Service HW Errors for specified port (Yukon-2 only)
29230 + *
29231 + * Description: handles the HW Error interrupts for a specific port.
29232 + *
29233 + * Returns: N/A
29234 + */
29235 +static void SkYuk2HwPortErr(
29236 +SK_AC  *pAC,           /* Adapter Context */
29237 +SK_IOC IoC,            /* I/O Context */
29238 +SK_U32 HwStatus,       /* Interrupt status word */
29239 +int            Port)           /* Port Index (MAC_1 + n) */
29240 +{
29241 +       SK_EVPARA       Para;
29242 +       int                     Queue;
29243 +
29244 +       if (Port == MAC_2) {
29245 +               HwStatus >>= 8;
29246 +       }
29247 +
29248 +       if ((HwStatus & Y2_HWE_L1_MASK) == 0) {
29249 +               return;
29250 +       }
29251 +
29252 +       if ((HwStatus & Y2_IS_PAR_RD1) != 0) {
29253 +               /* Clear IRQ */
29254 +               SK_OUT16(IoC, SELECT_RAM_BUFFER(Port, B3_RI_CTRL), RI_CLR_RD_PERR);
29255 +
29256 +               if (Port == MAC_1) {
29257 +                       SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E028, SKERR_SIRQ_E028MSG);
29258 +               }
29259 +               else {
29260 +                       SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E030, SKERR_SIRQ_E030MSG);
29261 +               }
29262 +       }
29263
29264 +       if ((HwStatus & Y2_IS_PAR_WR1) != 0) {
29265 +               /* Clear IRQ */
29266 +               SK_OUT16(IoC, SELECT_RAM_BUFFER(Port, B3_RI_CTRL), RI_CLR_WR_PERR);
29267 +
29268 +               if (Port == MAC_1) {
29269 +                       SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E029, SKERR_SIRQ_E029MSG);
29270 +               }
29271 +               else {
29272 +                       SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E031, SKERR_SIRQ_E031MSG);
29273 +               }
29274 +       }
29275 +
29276 +       if ((HwStatus & Y2_IS_PAR_MAC1) != 0) {
29277 +               /* Clear IRQ */
29278 +               SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
29279 +
29280 +               if (Port == MAC_1) {
29281 +                       SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E016, SKERR_SIRQ_E016MSG);
29282 +               }
29283 +               else {
29284 +                       SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E017, SKERR_SIRQ_E017MSG);
29285 +               }
29286 +       }
29287 +
29288 +       if ((HwStatus & Y2_IS_PAR_RX1) != 0) {
29289 +               if (Port == MAC_1) {
29290 +                       Queue = Q_R1;
29291 +                       SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E018, SKERR_SIRQ_E018MSG);
29292 +               }
29293 +               else {
29294 +                       Queue = Q_R2;
29295 +                       SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E019, SKERR_SIRQ_E019MSG);
29296 +               }
29297 +               /* Clear IRQ */
29298 +               SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_PAR);
29299 +       }
29300 +
29301 +       if ((HwStatus & Y2_IS_TCP_TXS1) != 0) {
29302 +               if (Port == MAC_1) {
29303 +                       Queue = Q_XS1;
29304 +                       SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E033, SKERR_SIRQ_E033MSG);
29305 +               }
29306 +               else {
29307 +                       Queue = Q_XS2;
29308 +                       SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E035, SKERR_SIRQ_E035MSG);
29309 +               }
29310 +               /* Clear IRQ */
29311 +               SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_TCP);
29312 +       }
29313 +
29314 +       if ((HwStatus & Y2_IS_TCP_TXA1) != 0) {
29315 +               if (Port == MAC_1) {
29316 +                       Queue = Q_XA1;
29317 +                       SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E032, SKERR_SIRQ_E032MSG);
29318 +               }
29319 +               else {
29320 +                       Queue = Q_XA2;
29321 +                       SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E034, SKERR_SIRQ_E034MSG);
29322 +               }
29323 +               /* Clear IRQ */
29324 +               SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_TCP);
29325 +       }
29326 +
29327 +       Para.Para64 = Port;
29328 +       SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
29329 +
29330 +       Para.Para32[0] = Port;
29331 +       SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
29332 +
29333 +}      /* SkYuk2HwPortErr */
29334
29335  /******************************************************************************
29336   *
29337 - *     SkGeSirqIsr() - Special Interrupt Service Routine
29338 + *     SkYuk2HwErr() - Hardware Error service routine (Yukon-2 only)
29339   *
29340 - * Description: handles all non data transfer specific interrupts (slow path)
29341 + * Description: handles all HW Error interrupts
29342 + *
29343 + * Returns: N/A
29344 + */
29345 +static void SkYuk2HwErr(
29346 +SK_AC  *pAC,           /* Adapter Context */
29347 +SK_IOC IoC,            /* I/O Context */
29348 +SK_U32 HwStatus)       /* Interrupt status word */
29349 +{
29350 +       SK_EVPARA       Para;
29351 +       SK_U16          Word;
29352 +       SK_U32          DWord;
29353 +       SK_U32          TlpHead[4];
29354 +       int                     i;
29355 +
29356 +       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
29357 +               ("HW-Error Status: 0x%08lX\n", HwStatus));
29358 +
29359 +       /* This is necessary only for Rx timing measurements */
29360 +       if ((HwStatus & Y2_IS_TIST_OV) != 0) {
29361 +               /* increment Time Stamp Timer counter (high) */
29362 +               pAC->GIni.GITimeStampCnt++;
29363 +
29364 +               /* Clear Time Stamp Timer IRQ */
29365 +               SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8)GMT_ST_CLR_IRQ);
29366 +       }
29367 +
29368 +       /* Evaluate Y2_IS_PCI_NEXP before Y2_IS_MST_ERR or Y2_IS_IRQ_STAT */
29369 +       if ((HwStatus & Y2_IS_PCI_NEXP) != 0) {
29370 +               /*
29371 +                * This error is also mapped either to Master Abort (Y2_IS_MST_ERR)
29372 +                * or Target Abort (Y2_IS_IRQ_STAT) bit and can only be cleared there.
29373 +                * Therefore handle this event just by printing an error log entry.
29374 +                */
29375 +               SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E027, SKERR_SIRQ_E027MSG);
29376 +       }
29377 +
29378 +       if ((HwStatus & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) {
29379 +               /* PCI Errors occured */
29380 +               if ((HwStatus & Y2_IS_IRQ_STAT) != 0) {
29381 +                       SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E013, SKERR_SIRQ_E013MSG);
29382 +               }
29383 +               else {
29384 +                       SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E012, SKERR_SIRQ_E012MSG);
29385 +               }
29386 +
29387 +               /* Reset all bits in the PCI STATUS register */
29388 +               SK_IN16(IoC, PCI_C(pAC, PCI_STATUS), &Word);
29389 +
29390 +               SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
29391 +               SK_OUT16(IoC, PCI_C(pAC, PCI_STATUS), (SK_U16)(Word | PCI_ERRBITS));
29392 +               SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
29393 +
29394 +               Para.Para64 = 0;
29395 +               SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
29396 +       }
29397 +
29398 +       /* check for PCI-Express Uncorrectable Error */
29399 +       if ((HwStatus & Y2_IS_PCI_EXP) != 0) {
29400 +               /*
29401 +                * On PCI-Express bus bridges are called root complexes (RC).
29402 +                * PCI-Express errors are recognized by the root complex too,
29403 +                * which requests the system to handle the problem. After error
29404 +                * occurence it may be that no access to the adapter may be performed
29405 +                * any longer.
29406 +                */
29407 +
29408 +               /* Get uncorrectable error status */
29409 +               SK_IN32(IoC, PCI_C(pAC, PEX_UNC_ERR_STAT), &DWord);
29410 +
29411 +               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
29412 +                       ("PEX Uncorr.Error Status: 0x%08lX\n", DWord));
29413 +
29414 +               if (DWord != PEX_UNSUP_REQ) {
29415 +                       /* ignore Unsupported Request Errors */
29416 +                       SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E026, SKERR_SIRQ_E026MSG);
29417 +               }
29418 +
29419 +               if ((DWord & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) {
29420 +                       /*
29421 +                        * Stop only, if the uncorrectable error is fatal or
29422 +                        * Poisoned TLP occured
29423 +                        */
29424 +                       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, ("Header Log:"));
29425 +
29426 +                       for (i = 0; i < 4; i++) {
29427 +                               /* get TLP Header from Log Registers */
29428 +                               SK_IN32(IoC, PCI_C(pAC, PEX_HEADER_LOG + i*4), &TlpHead[i]);
29429 +
29430 +                               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
29431 +                                       (" 0x%08lX", TlpHead[i]));
29432 +                       }
29433 +                       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, ("\n"));
29434 +
29435 +                       /* check for vendor defined broadcast message */
29436 +                       if (TlpHead[0] == 0x73004001 && (SK_U8)TlpHead[1] == 0x7f) {
29437 +
29438 +                               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
29439 +                                       ("Vendor defined broadcast message\n"));
29440 +                       }
29441 +                       else {
29442 +                               Para.Para64 = 0;
29443 +                               SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
29444 +
29445 +                               pAC->GIni.GIValHwIrqMask &= ~Y2_IS_PCI_EXP;
29446 +                               /* Rewrite HW IRQ mask */
29447 +                               SK_OUT32(IoC, B0_HWE_IMSK, pAC->GIni.GIValHwIrqMask);
29448 +                       }
29449 +               }
29450 +
29451 +               /* clear any PEX errors */
29452 +               SK_OUT32(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
29453 +               SK_OUT32(IoC, PCI_C(pAC, PEX_UNC_ERR_STAT), 0xffffffffUL);
29454 +               SK_OUT32(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
29455 +
29456 +               SK_IN32(IoC, PCI_C(pAC, PEX_UNC_ERR_STAT), &DWord);
29457 +
29458 +               if ((DWord & PEX_RX_OV) != 0) {
29459 +                       /* Dev #4.205 occured */
29460 +                       pAC->GIni.GIValHwIrqMask &= ~Y2_IS_PCI_EXP;
29461 +                       pAC->GIni.GIValIrqMask &= ~Y2_IS_HW_ERR;
29462 +               }
29463 +       }
29464 +
29465 +       for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
29466 +
29467 +               SkYuk2HwPortErr(pAC, IoC, HwStatus, i);
29468 +       }
29469 +
29470 +}      /* SkYuk2HwErr */
29471 +#endif /* YUK2 */
29472 +
29473 +/******************************************************************************
29474 + *
29475 + *     SkGeSirqIsr() - Wrapper for Special Interrupt Service Routine
29476 + *
29477 + * Description: calls the preselected special ISR (slow path)
29478   *
29479   * Returns: N/A
29480   */
29481  void SkGeSirqIsr(
29482 -SK_AC  *pAC,           /* adapter context */
29483 -SK_IOC IoC,            /* IO context */
29484 +SK_AC  *pAC,           /* Adapter Context */
29485 +SK_IOC IoC,            /* I/O context */
29486 +SK_U32 Istatus)        /* Interrupt status word */
29487 +{
29488 +       pAC->GIni.GIFunc.pSkGeSirqIsr(pAC, IoC, Istatus);
29489 +}
29490 +
29491 +/******************************************************************************
29492 + *
29493 + *     SkGeYuSirqIsr() - Special Interrupt Service Routine
29494 + *
29495 + * Description: handles all non data transfer specific interrupts (slow path)
29496 + *
29497 + * Returns: N/A
29498 + */
29499 +void SkGeYuSirqIsr(
29500 +SK_AC  *pAC,           /* Adapter Context */
29501 +SK_IOC IoC,            /* I/O Context */
29502  SK_U32 Istatus)        /* Interrupt status word */
29503  {
29504         SK_EVPARA       Para;
29505         SK_U32          RegVal32;       /* Read register value */
29506         SK_GEPORT       *pPrt;          /* GIni Port struct pointer */
29507 -       SK_U16          PhyInt;
29508 +       SK_U16          PhyInt;
29509         int                     i;
29510
29511         if (((Istatus & IS_HW_ERR) & pAC->GIni.GIValIrqMask) != 0) {
29512                 /* read the HW Error Interrupt source */
29513                 SK_IN32(IoC, B0_HWE_ISRC, &RegVal32);
29514 -
29515 -               SkGeHwErr(pAC, IoC, RegVal32);
29516 +
29517 +               SkGeYuHwErr(pAC, IoC, RegVal32);
29518         }
29519
29520         /*
29521 @@ -569,7 +844,7 @@
29522         }
29523
29524         if (((Istatus & (IS_PA_TO_RX2 | IS_PA_TO_TX2)) != 0) &&
29525 -           pAC->GIni.GP[MAC_2].PState == SK_PRT_RESET) {
29526 +               pAC->GIni.GP[MAC_2].PState == SK_PRT_RESET) {
29527                 /* MAC 2 was not initialized but Packet timeout occured */
29528                 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E005,
29529                         SKERR_SIRQ_E005MSG);
29530 @@ -590,8 +865,8 @@
29531         }
29532
29533         if ((Istatus & IS_PA_TO_TX1) != 0) {
29534 -
29535 -               pPrt = &pAC->GIni.GP[0];
29536 +
29537 +               pPrt = &pAC->GIni.GP[MAC_1];
29538
29539                 /* May be a normal situation in a server with a slow network */
29540                 SK_OUT16(IoC, B3_PA_CTRL, PA_CLR_TO_TX1);
29541 @@ -612,17 +887,18 @@
29542                                  * we ignore those
29543                                  */
29544                                 pPrt->HalfDupTimerActive = SK_TRUE;
29545 +
29546                                 /* Snap statistic counters */
29547                                 (void)SkXmUpdateStats(pAC, IoC, 0);
29548
29549                                 (void)SkXmMacStatistic(pAC, IoC, 0, XM_TXO_OK_HI, &RegVal32);
29550
29551                                 pPrt->LastOctets = (SK_U64)RegVal32 << 32;
29552 -
29553 +
29554                                 (void)SkXmMacStatistic(pAC, IoC, 0, XM_TXO_OK_LO, &RegVal32);
29555
29556                                 pPrt->LastOctets += RegVal32;
29557 -
29558 +
29559                                 Para.Para32[0] = 0;
29560                                 SkTimerStart(pAC, IoC, &pPrt->HalfDupChkTimer, SK_HALFDUP_CHK_TIME,
29561                                         SKGE_HWAC, SK_HWEV_HALFDUP_CHK, Para);
29562 @@ -632,8 +908,8 @@
29563         }
29564
29565         if ((Istatus & IS_PA_TO_TX2) != 0) {
29566 -
29567 -               pPrt = &pAC->GIni.GP[1];
29568 +
29569 +               pPrt = &pAC->GIni.GP[MAC_2];
29570
29571                 /* May be a normal situation in a server with a slow network */
29572                 SK_OUT16(IoC, B3_PA_CTRL, PA_CLR_TO_TX2);
29573 @@ -645,17 +921,18 @@
29574                                  pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOHALF) &&
29575                                 !pPrt->HalfDupTimerActive) {
29576                                 pPrt->HalfDupTimerActive = SK_TRUE;
29577 +
29578                                 /* Snap statistic counters */
29579                                 (void)SkXmUpdateStats(pAC, IoC, 1);
29580
29581                                 (void)SkXmMacStatistic(pAC, IoC, 1, XM_TXO_OK_HI, &RegVal32);
29582
29583                                 pPrt->LastOctets = (SK_U64)RegVal32 << 32;
29584 -
29585 +
29586                                 (void)SkXmMacStatistic(pAC, IoC, 1, XM_TXO_OK_LO, &RegVal32);
29587
29588                                 pPrt->LastOctets += RegVal32;
29589 -
29590 +
29591                                 Para.Para32[0] = 1;
29592                                 SkTimerStart(pAC, IoC, &pPrt->HalfDupChkTimer, SK_HALFDUP_CHK_TIME,
29593                                         SKGE_HWAC, SK_HWEV_HALFDUP_CHK, Para);
29594 @@ -668,6 +945,7 @@
29595         if ((Istatus & IS_R1_C) != 0) {
29596                 /* Clear IRQ */
29597                 SK_OUT32(IoC, B0_R1_CSR, CSR_IRQ_CL_C);
29598 +
29599                 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E006,
29600                         SKERR_SIRQ_E006MSG);
29601                 Para.Para64 = MAC_1;
29602 @@ -679,6 +957,7 @@
29603         if ((Istatus & IS_R2_C) != 0) {
29604                 /* Clear IRQ */
29605                 SK_OUT32(IoC, B0_R2_CSR, CSR_IRQ_CL_C);
29606 +
29607                 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E007,
29608                         SKERR_SIRQ_E007MSG);
29609                 Para.Para64 = MAC_2;
29610 @@ -690,6 +969,7 @@
29611         if ((Istatus & IS_XS1_C) != 0) {
29612                 /* Clear IRQ */
29613                 SK_OUT32(IoC, B0_XS1_CSR, CSR_IRQ_CL_C);
29614 +
29615                 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E008,
29616                         SKERR_SIRQ_E008MSG);
29617                 Para.Para64 = MAC_1;
29618 @@ -701,6 +981,7 @@
29619         if ((Istatus & IS_XA1_C) != 0) {
29620                 /* Clear IRQ */
29621                 SK_OUT32(IoC, B0_XA1_CSR, CSR_IRQ_CL_C);
29622 +
29623                 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E009,
29624                         SKERR_SIRQ_E009MSG);
29625                 Para.Para64 = MAC_1;
29626 @@ -712,6 +993,7 @@
29627         if ((Istatus & IS_XS2_C) != 0) {
29628                 /* Clear IRQ */
29629                 SK_OUT32(IoC, B0_XS2_CSR, CSR_IRQ_CL_C);
29630 +
29631                 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E010,
29632                         SKERR_SIRQ_E010MSG);
29633                 Para.Para64 = MAC_2;
29634 @@ -723,6 +1005,7 @@
29635         if ((Istatus & IS_XA2_C) != 0) {
29636                 /* Clear IRQ */
29637                 SK_OUT32(IoC, B0_XA2_CSR, CSR_IRQ_CL_C);
29638 +
29639                 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E011,
29640                         SKERR_SIRQ_E011MSG);
29641                 Para.Para64 = MAC_2;
29642 @@ -735,39 +1018,37 @@
29643         if ((Istatus & IS_EXT_REG) != 0) {
29644                 /* Test IRQs from PHY */
29645                 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
29646 -
29647 +
29648                         pPrt = &pAC->GIni.GP[i];
29649 -
29650 +
29651                         if (pPrt->PState == SK_PRT_RESET) {
29652                                 continue;
29653                         }
29654 -
29655 +
29656  #ifdef GENESIS
29657                         if (pAC->GIni.GIGenesis) {
29658 -
29659 +
29660                                 switch (pPrt->PhyType) {
29661 -
29662 +
29663                                 case SK_PHY_XMAC:
29664                                         break;
29665 -
29666 +
29667                                 case SK_PHY_BCOM:
29668                                         SkXmPhyRead(pAC, IoC, i, PHY_BCOM_INT_STAT, &PhyInt);
29669 -
29670 +
29671                                         if ((PhyInt & ~PHY_B_DEF_MSK) != 0) {
29672                                                 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
29673 -                                                       ("Port %d Bcom Int: 0x%04X\n",
29674 -                                                       i, PhyInt));
29675 +                                                       ("Port %d PHY Int: 0x%04X\n", i, PhyInt));
29676                                                 SkPhyIsrBcom(pAC, IoC, i, PhyInt);
29677                                         }
29678                                         break;
29679  #ifdef OTHER_PHY
29680                                 case SK_PHY_LONE:
29681                                         SkXmPhyRead(pAC, IoC, i, PHY_LONE_INT_STAT, &PhyInt);
29682 -
29683 +
29684                                         if ((PhyInt & PHY_L_DEF_MSK) != 0) {
29685                                                 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
29686 -                                                       ("Port %d Lone Int: %x\n",
29687 -                                                       i, PhyInt));
29688 +                                                       ("Port %d PHY Int: 0x%04X\n", i, PhyInt));
29689                                                 SkPhyIsrLone(pAC, IoC, i, PhyInt);
29690                                         }
29691                                         break;
29692 @@ -775,7 +1056,7 @@
29693                                 }
29694                         }
29695  #endif /* GENESIS */
29696 -
29697 +
29698  #ifdef YUKON
29699                         if (pAC->GIni.GIYukon) {
29700                                 /* Read PHY Interrupt Status */
29701 @@ -783,8 +1064,7 @@
29702
29703                                 if ((PhyInt & PHY_M_DEF_MSK) != 0) {
29704                                         SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
29705 -                                               ("Port %d Marv Int: 0x%04X\n",
29706 -                                               i, PhyInt));
29707 +                                               ("Port %d PHY Int: 0x%04X\n", i, PhyInt));
29708                                         SkPhyIsrGmac(pAC, IoC, i, PhyInt);
29709                                 }
29710                         }
29711 @@ -792,13 +1072,13 @@
29712                 }
29713         }
29714
29715 -       /* I2C Ready interrupt */
29716 +       /* TWSI Ready interrupt */
29717         if ((Istatus & IS_I2C_READY) != 0) {
29718  #ifdef SK_SLIM
29719 -        SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
29720 -#else
29721 +               SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
29722 +#else
29723                 SkI2cIsr(pAC, IoC);
29724 -#endif
29725 +#endif
29726         }
29727
29728         /* SW forced interrupt */
29729 @@ -813,7 +1093,7 @@
29730                  * us only a link going down.
29731                  */
29732                 /* clear interrupt */
29733 -               SK_OUT8(IoC, MR_ADDR(MAC_1, LNK_SYNC_CTRL), LED_CLR_IRQ);
29734 +               SK_OUT8(IoC, MR_ADDR(MAC_1, LNK_SYNC_CTRL), LNK_CLR_IRQ);
29735         }
29736
29737         /* Check MAC after link sync counter */
29738 @@ -828,7 +1108,7 @@
29739                  * us only a link going down.
29740                  */
29741                 /* clear interrupt */
29742 -               SK_OUT8(IoC, MR_ADDR(MAC_2, LNK_SYNC_CTRL), LED_CLR_IRQ);
29743 +               SK_OUT8(IoC, MR_ADDR(MAC_2, LNK_SYNC_CTRL), LNK_CLR_IRQ);
29744         }
29745
29746         /* Check MAC after link sync counter */
29747 @@ -844,13 +1124,201 @@
29748                         /* read the HW Error Interrupt source */
29749                         SK_IN32(IoC, B0_HWE_ISRC, &RegVal32);
29750
29751 -                       SkGeHwErr(pAC, IoC, RegVal32);
29752 +                       SkGeYuHwErr(pAC, IoC, RegVal32);
29753                 }
29754
29755                 SkHwtIsr(pAC, IoC);
29756         }
29757
29758 -}      /* SkGeSirqIsr */
29759 +}      /* SkGeYuSirqIsr */
29760 +
29761 +#ifdef YUK2
29762 +/******************************************************************************
29763 + *
29764 + *     SkYuk2PortSirq() - Service HW Errors for specified port (Yukon-2 only)
29765 + *
29766 + * Description: handles the HW Error interrupts for a specific port.
29767 + *
29768 + * Returns: N/A
29769 + */
29770 +static void SkYuk2PortSirq(
29771 +SK_AC  *pAC,           /* Adapter Context */
29772 +SK_IOC IoC,            /* I/O Context */
29773 +SK_U32 IStatus,        /* Interrupt status word */
29774 +int            Port)           /* Port Index (MAC_1 + n) */
29775 +{
29776 +       SK_EVPARA       Para;
29777 +       int                     Queue;
29778 +       SK_U16          PhyInt;
29779 +
29780 +       if (Port == MAC_2) {
29781 +               IStatus >>= 8;
29782 +       }
29783 +
29784 +       /* Interrupt from PHY */
29785 +       if ((IStatus & Y2_IS_IRQ_PHY1) != 0) {
29786 +               /* Read PHY Interrupt Status */
29787 +               SkGmPhyRead(pAC, IoC, Port, PHY_MARV_INT_STAT, &PhyInt);
29788 +
29789 +               if ((PhyInt & PHY_M_DEF_MSK) != 0) {
29790 +                       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
29791 +                               ("Port %d PHY Int: 0x%04X\n", Port, PhyInt));
29792 +                       SkPhyIsrGmac(pAC, IoC, Port, PhyInt);
29793 +               }
29794 +       }
29795 +
29796 +       /* Interrupt from MAC */
29797 +       if ((IStatus & Y2_IS_IRQ_MAC1) != 0) {
29798 +               SkMacIrq(pAC, IoC, Port);
29799 +       }
29800 +
29801 +       if ((IStatus & (Y2_IS_CHK_RX1 | Y2_IS_CHK_TXS1 | Y2_IS_CHK_TXA1)) != 0) {
29802 +               if ((IStatus & Y2_IS_CHK_RX1) != 0) {
29803 +                       if (Port == MAC_1) {
29804 +                               Queue = Q_R1;
29805 +                               SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E006,
29806 +                                       SKERR_SIRQ_E006MSG);
29807 +                       }
29808 +                       else {
29809 +                               Queue = Q_R2;
29810 +                               SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E007,
29811 +                                       SKERR_SIRQ_E007MSG);
29812 +                       }
29813 +                       /* Clear IRQ */
29814 +                       SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_CHK);
29815 +               }
29816 +
29817 +               if ((IStatus & Y2_IS_CHK_TXS1) != 0) {
29818 +                       if (Port == MAC_1) {
29819 +                               Queue = Q_XS1;
29820 +                               SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E008,
29821 +                                       SKERR_SIRQ_E008MSG);
29822 +                       }
29823 +                       else {
29824 +                               Queue = Q_XS2;
29825 +                               SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E010,
29826 +                                       SKERR_SIRQ_E010MSG);
29827 +                       }
29828 +                       /* Clear IRQ */
29829 +                       SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_CHK);
29830 +               }
29831 +
29832 +               if ((IStatus & Y2_IS_CHK_TXA1) != 0) {
29833 +                       if (Port == MAC_1) {
29834 +                               Queue = Q_XA1;
29835 +                               SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E009,
29836 +                                       SKERR_SIRQ_E009MSG);
29837 +                       }
29838 +                       else {
29839 +                               Queue = Q_XA2;
29840 +                               SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E011,
29841 +                                       SKERR_SIRQ_E011MSG);
29842 +                       }
29843 +                       /* Clear IRQ */
29844 +                       SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_CHK);
29845 +               }
29846 +
29847 +               Para.Para64 = Port;
29848 +               SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
29849 +
29850 +               Para.Para32[0] = Port;
29851 +               SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
29852 +       }
29853 +}      /* SkYuk2PortSirq */
29854 +#endif /* YUK2 */
29855 +
29856 +/******************************************************************************
29857 + *
29858 + *     SkYuk2SirqIsr() - Special Interrupt Service Routine     (Yukon-2 only)
29859 + *
29860 + * Description: handles all non data transfer specific interrupts (slow path)
29861 + *
29862 + * Returns: N/A
29863 + */
29864 +void SkYuk2SirqIsr(
29865 +SK_AC  *pAC,           /* Adapter Context */
29866 +SK_IOC IoC,            /* I/O Context */
29867 +SK_U32 Istatus)        /* Interrupt status word */
29868 +{
29869 +#ifdef YUK2
29870 +       SK_EVPARA       Para;
29871 +       SK_U32          RegVal32;       /* Read register value */
29872 +       SK_U8           Value;
29873 +
29874 +       /* HW Error indicated ? */
29875 +       if (((Istatus & Y2_IS_HW_ERR) & pAC->GIni.GIValIrqMask) != 0) {
29876 +               /* read the HW Error Interrupt source */
29877 +               SK_IN32(IoC, B0_HWE_ISRC, &RegVal32);
29878 +
29879 +               SkYuk2HwErr(pAC, IoC, RegVal32);
29880 +       }
29881 +
29882 +       /* Interrupt from ASF Subsystem */
29883 +       if ((Istatus & Y2_IS_ASF) != 0) {
29884 +               /* clear IRQ */
29885 +               /* later on clearing should be done in ASF ISR handler */
29886 +               SK_IN8(IoC, B28_Y2_ASF_STAT_CMD, &Value);
29887 +               Value |= Y2_ASF_CLR_HSTI;
29888 +               SK_OUT8(IoC, B28_Y2_ASF_STAT_CMD, Value);
29889 +               /* Call IRQ handler in ASF Module */
29890 +               /* TBD */
29891 +       }
29892 +
29893 +       /* Check IRQ from polling unit */
29894 +       if ((Istatus & Y2_IS_POLL_CHK) != 0) {
29895 +               /* Clear IRQ */
29896 +               SK_OUT32(IoC, POLL_CTRL, PC_CLR_IRQ_CHK);
29897 +
29898 +               SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E036,
29899 +                       SKERR_SIRQ_E036MSG);
29900 +               Para.Para64 = 0;
29901 +               SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
29902 +       }
29903 +
29904 +       /* TWSI Ready interrupt */
29905 +       if ((Istatus & Y2_IS_TWSI_RDY) != 0) {
29906 +#ifdef SK_SLIM
29907 +               SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
29908 +#else
29909 +               SkI2cIsr(pAC, IoC);
29910 +#endif
29911 +       }
29912 +
29913 +       /* SW forced interrupt */
29914 +       if ((Istatus & Y2_IS_IRQ_SW) != 0) {
29915 +               /* clear the software IRQ */
29916 +               SK_OUT8(IoC, B0_CTST, CS_CL_SW_IRQ);
29917 +       }
29918 +
29919 +       if ((Istatus & Y2_IS_L1_MASK) != 0) {
29920 +               SkYuk2PortSirq(pAC, IoC, Istatus, MAC_1);
29921 +       }
29922 +
29923 +       if ((Istatus & Y2_IS_L2_MASK) != 0) {
29924 +               SkYuk2PortSirq(pAC, IoC, Istatus, MAC_2);
29925 +       }
29926 +
29927 +       /* Timer interrupt (served last) */
29928 +       if ((Istatus & Y2_IS_TIMINT) != 0) {
29929 +
29930 +               if (((Istatus & Y2_IS_HW_ERR) & ~pAC->GIni.GIValIrqMask) != 0) {
29931 +                       /* read the HW Error Interrupt source */
29932 +                       SK_IN32(IoC, B0_HWE_ISRC, &RegVal32);
29933 +
29934 +                       /* otherwise we would generate error log entries periodically */
29935 +                       RegVal32 &= pAC->GIni.GIValHwIrqMask;
29936 +                       if (RegVal32 != 0) {
29937 +                               SkYuk2HwErr(pAC, IoC, RegVal32);
29938 +                       }
29939 +               }
29940 +
29941 +               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
29942 +                       ("Timer Int: 0x%08lX\n", Istatus));
29943 +               SkHwtIsr(pAC, IoC);
29944 +       }
29945 +#endif /* YUK2 */
29946 +
29947 +}      /* SkYuk2SirqIsr */
29948
29949
29950  #ifdef GENESIS
29951 @@ -864,8 +1332,8 @@
29952   */
29953  static int SkGePortCheckShorts(
29954  SK_AC  *pAC,           /* Adapter Context */
29955 -SK_IOC IoC,            /* IO Context */
29956 -int            Port)           /* Which port should be checked */
29957 +SK_IOC IoC,            /* I/O Context */
29958 +int            Port)           /* Port Index (MAC_1 + n) */
29959  {
29960         SK_U32          Shorts;                 /* Short Event Counter */
29961         SK_U32          CheckShorts;    /* Check value for Short Event Counter */
29962 @@ -893,9 +1361,9 @@
29963         RxCts = 0;
29964
29965         for (i = 0; i < sizeof(SkGeRxRegs)/sizeof(SkGeRxRegs[0]); i++) {
29966 -
29967 +
29968                 (void)SkXmMacStatistic(pAC, IoC, Port, SkGeRxRegs[i], &RxTmp);
29969 -
29970 +
29971                 RxCts += (SK_U64)RxTmp;
29972         }
29973
29974 @@ -912,11 +1380,11 @@
29975                 CheckShorts = 2;
29976
29977                 (void)SkXmMacStatistic(pAC, IoC, Port, XM_RXF_FCS_ERR, &FcsErrCts);
29978 -
29979 -               if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE &&
29980 -                   pPrt->PLipaAutoNeg == SK_LIPA_UNKNOWN &&
29981 -                   (pPrt->PLinkMode == SK_LMODE_HALF ||
29982 -                        pPrt->PLinkMode == SK_LMODE_FULL)) {
29983 +
29984 +               if (pPrt->PLinkModeConf == (SK_U8)SK_LMODE_AUTOSENSE &&
29985 +                       pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_UNKNOWN &&
29986 +                       (pPrt->PLinkMode == (SK_U8)SK_LMODE_HALF ||
29987 +                        pPrt->PLinkMode == (SK_U8)SK_LMODE_FULL)) {
29988                         /*
29989                          * This is autosensing and we are in the fallback
29990                          * manual full/half duplex mode.
29991 @@ -925,16 +1393,16 @@
29992                                 /* Nothing received, restart link */
29993                                 pPrt->PPrevFcs = FcsErrCts;
29994                                 pPrt->PPrevShorts = Shorts;
29995 -
29996 +
29997                                 return(SK_HW_PS_RESTART);
29998                         }
29999                         else {
30000 -                               pPrt->PLipaAutoNeg = SK_LIPA_MANUAL;
30001 +                               pPrt->PLipaAutoNeg = (SK_U8)SK_LIPA_MANUAL;
30002                         }
30003                 }
30004
30005                 if (((RxCts - pPrt->PPrevRx) > pPrt->PRxLim) ||
30006 -                   (!(FcsErrCts - pPrt->PPrevFcs))) {
30007 +                       (!(FcsErrCts - pPrt->PPrevFcs))) {
30008                         /*
30009                          * Note: The compare with zero above has to be done the way shown,
30010                          * otherwise the Linux driver will have a problem.
30011 @@ -979,29 +1447,25 @@
30012   */
30013  static int SkGePortCheckUp(
30014  SK_AC  *pAC,           /* Adapter Context */
30015 -SK_IOC IoC,            /* IO Context */
30016 -int            Port)           /* Which port should be checked */
30017 +SK_IOC IoC,            /* I/O Context */
30018 +int            Port)           /* Port Index (MAC_1 + n) */
30019  {
30020         SK_GEPORT       *pPrt;          /* GIni Port struct pointer */
30021         SK_BOOL         AutoNeg;        /* Is Auto-negotiation used ? */
30022         int                     Rtv;            /* Return value */
30023
30024         Rtv = SK_HW_PS_NONE;
30025 -
30026 +
30027         pPrt = &pAC->GIni.GP[Port];
30028
30029 -       if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
30030 -               AutoNeg = SK_FALSE;
30031 -       }
30032 -       else {
30033 -               AutoNeg = SK_TRUE;
30034 -       }
30035 +       AutoNeg = pPrt->PLinkMode != SK_LMODE_HALF &&
30036 +                         pPrt->PLinkMode != SK_LMODE_FULL;
30037
30038  #ifdef GENESIS
30039         if (pAC->GIni.GIGenesis) {
30040
30041                 switch (pPrt->PhyType) {
30042 -
30043 +
30044                 case SK_PHY_XMAC:
30045                         Rtv = SkGePortCheckUpXmac(pAC, IoC, Port, AutoNeg);
30046                         break;
30047 @@ -1019,15 +1483,15 @@
30048                 }
30049         }
30050  #endif /* GENESIS */
30051 -
30052 +
30053  #ifdef YUKON
30054         if (pAC->GIni.GIYukon) {
30055 -
30056 +
30057                 Rtv = SkGePortCheckUpGmac(pAC, IoC, Port, AutoNeg);
30058         }
30059  #endif /* YUKON */
30060
30061 -       return(Rtv);
30062 +       return(Rtv);
30063  }      /* SkGePortCheckUp */
30064
30065
30066 @@ -1043,8 +1507,8 @@
30067   */
30068  static int SkGePortCheckUpXmac(
30069  SK_AC  *pAC,           /* Adapter Context */
30070 -SK_IOC IoC,            /* IO Context */
30071 -int            Port,           /* Which port should be checked */
30072 +SK_IOC IoC,            /* I/O Context */
30073 +int            Port,           /* Port Index (MAC_1 + n) */
30074  SK_BOOL        AutoNeg)        /* Is Auto-negotiation used ? */
30075  {
30076         SK_U32          Shorts;         /* Short Event Counter */
30077 @@ -1082,7 +1546,7 @@
30078                         XM_IN16(IoC, Port, XM_ISRC, &Isrc);
30079                         IsrcSum |= Isrc;
30080                         SkXmAutoNegLipaXmac(pAC, IoC, Port, IsrcSum);
30081 -
30082 +
30083                         if ((Isrc & XM_IS_INP_ASS) == 0) {
30084                                 /* It has been in sync since last time */
30085                                 /* Restart the PORT */
30086 @@ -1101,14 +1565,14 @@
30087                                  * Link Restart Workaround:
30088                                  *  it may be possible that the other Link side
30089                                  *  restarts its link as well an we detect
30090 -                                *  another LinkBroken. To prevent this
30091 +                                *  another PLinkBroken. To prevent this
30092                                  *  happening we check for a maximum number
30093                                  *  of consecutive restart. If those happens,
30094                                  *  we do NOT restart the active link and
30095                                  *  check whether the link is now o.k.
30096                                  */
30097                                 pPrt->PLinkResCt++;
30098 -
30099 +
30100                                 pPrt->PAutoNegTimeOut = 0;
30101
30102                                 if (pPrt->PLinkResCt < SK_MAX_LRESTART) {
30103 @@ -1116,13 +1580,13 @@
30104                                 }
30105
30106                                 pPrt->PLinkResCt = 0;
30107 -
30108 +
30109                                 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30110                                         ("Do NOT restart on Port %d %x %x\n", Port, Isrc, IsrcSum));
30111                         }
30112                         else {
30113                                 pPrt->PIsave = (SK_U16)(IsrcSum & XM_IS_AND);
30114 -
30115 +
30116                                 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30117                                         ("Save Sync/nosync Port %d %x %x\n", Port, Isrc, IsrcSum));
30118
30119 @@ -1149,7 +1613,7 @@
30120                                 if ((Isrc & XM_IS_INP_ASS) != 0) {
30121                                         pPrt->PLinkBroken = SK_TRUE;
30122                                         /* Re-Init Link partner Autoneg flag */
30123 -                                       pPrt->PLipaAutoNeg = SK_LIPA_UNKNOWN;
30124 +                                       pPrt->PLipaAutoNeg = (SK_U8)SK_LIPA_UNKNOWN;
30125                                         SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
30126                                                 ("Link broken Port %d\n", Port));
30127
30128 @@ -1162,7 +1626,7 @@
30129                 }
30130                 else {
30131                         SkXmAutoNegLipaXmac(pAC, IoC, Port, Isrc);
30132 -
30133 +
30134                         if (SkGePortCheckShorts(pAC, IoC, Port) == SK_HW_PS_RESTART) {
30135                                 return(SK_HW_PS_RESTART);
30136                         }
30137 @@ -1178,7 +1642,7 @@
30138         IsrcSum |= Isrc;
30139
30140         SkXmAutoNegLipaXmac(pAC, IoC, Port, IsrcSum);
30141 -
30142 +
30143         if ((GpReg & XM_GP_INP_ASS) != 0 || (IsrcSum & XM_IS_INP_ASS) != 0) {
30144                 if ((GpReg & XM_GP_INP_ASS) == 0) {
30145                         /* Save Auto-negotiation Done interrupt only if link is in sync */
30146 @@ -1194,20 +1658,26 @@
30147         }
30148
30149         if (AutoNeg) {
30150 +               /* Auto-Negotiation Done ? */
30151                 if ((IsrcSum & XM_IS_AND) != 0) {
30152 +
30153                         SkHWLinkUp(pAC, IoC, Port);
30154 +
30155                         Done = SkMacAutoNegDone(pAC, IoC, Port);
30156 +
30157                         if (Done != SK_AND_OK) {
30158                                 /* Get PHY parameters, for debugging only */
30159                                 SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_AUNE_LP, &LpAb);
30160                                 SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_RES_ABI, &ResAb);
30161 -                               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30162 +                               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
30163                                         ("AutoNeg FAIL Port %d (LpAb %x, ResAb %x)\n",
30164 -                                        Port, LpAb, ResAb));
30165 -
30166 +                                       Port, LpAb, ResAb));
30167 +
30168                                 /* Try next possible mode */
30169                                 NextMode = SkHWSenseGetNext(pAC, IoC, Port);
30170 +
30171                                 SkHWLinkDown(pAC, IoC, Port);
30172 +
30173                                 if (Done == SK_AND_DUP_CAP) {
30174                                         /* GoTo next mode */
30175                                         SkHWSenseSetNext(pAC, IoC, Port, NextMode);
30176 @@ -1220,42 +1690,41 @@
30177                          * (clear Page Received bit if set)
30178                          */
30179                         SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_AUNE_EXP, &ExtStat);
30180 -
30181 +
30182                         return(SK_HW_PS_LINK);
30183                 }
30184 -
30185 +
30186                 /* AutoNeg not done, but HW link is up. Check for timeouts */
30187 -               pPrt->PAutoNegTimeOut++;
30188 -               if (pPrt->PAutoNegTimeOut >= SK_AND_MAX_TO) {
30189 +               if (pPrt->PAutoNegTimeOut++ >= SK_AND_MAX_TO) {
30190                         /* Increase the Timeout counter */
30191                         pPrt->PAutoNegTOCt++;
30192
30193                         /* Timeout occured */
30194                         SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
30195                                 ("AutoNeg timeout Port %d\n", Port));
30196 -                       if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE &&
30197 -                               pPrt->PLipaAutoNeg != SK_LIPA_AUTO) {
30198 +                       if (pPrt->PLinkModeConf == (SK_U8)SK_LMODE_AUTOSENSE &&
30199 +                               pPrt->PLipaAutoNeg != (SK_U8)SK_LIPA_AUTO) {
30200                                 /* Set Link manually up */
30201                                 SkHWSenseSetNext(pAC, IoC, Port, SK_LMODE_FULL);
30202                                 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
30203                                         ("Set manual full duplex Port %d\n", Port));
30204                         }
30205
30206 -                       if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE &&
30207 -                               pPrt->PLipaAutoNeg == SK_LIPA_AUTO &&
30208 +                       if (pPrt->PLinkModeConf == (SK_U8)SK_LMODE_AUTOSENSE &&
30209 +                               pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_AUTO &&
30210                                 pPrt->PAutoNegTOCt >= SK_MAX_ANEG_TO) {
30211                                 /*
30212                                  * This is rather complicated.
30213                                  * we need to check here whether the LIPA_AUTO
30214                                  * we saw before is false alert. We saw at one
30215 -                                * switch ( SR8800) that on boot time it sends
30216 +                                * switch (SR8800) that on boot time it sends
30217                                  * just one auto-neg packet and does no further
30218                                  * auto-negotiation.
30219                                  * Solution: we restart the autosensing after
30220                                  * a few timeouts.
30221                                  */
30222                                 pPrt->PAutoNegTOCt = 0;
30223 -                               pPrt->PLipaAutoNeg = SK_LIPA_UNKNOWN;
30224 +                               pPrt->PLipaAutoNeg = (SK_U8)SK_LIPA_UNKNOWN;
30225                                 SkHWInitDefSense(pAC, IoC, Port);
30226                         }
30227
30228 @@ -1266,18 +1735,18 @@
30229         else {
30230                 /* Link is up and we don't need more */
30231  #ifdef DEBUG
30232 -               if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) {
30233 -                       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30234 +               if (pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_AUTO) {
30235 +                       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
30236                                 ("ERROR: Lipa auto detected on port %d\n", Port));
30237                 }
30238  #endif /* DEBUG */
30239                 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
30240                         ("Link sync(GP), Port %d\n", Port));
30241                 SkHWLinkUp(pAC, IoC, Port);
30242 -
30243 +
30244                 /*
30245 -                * Link sync (GP) and so assume a good connection. But if not received
30246 -                * a bunch of frames received in a time slot (maybe broken tx cable)
30247 +                * Link sync (GP) and so assume a good connection. But if no
30248 +                * bunch of frames received in a time slot (maybe broken Tx cable)
30249                  * the port is restart.
30250                  */
30251                 return(SK_HW_PS_LINK);
30252 @@ -1298,14 +1767,14 @@
30253   */
30254  static int SkGePortCheckUpBcom(
30255  SK_AC  *pAC,           /* Adapter Context */
30256 -SK_IOC IoC,            /* IO Context */
30257 -int            Port,           /* Which port should be checked */
30258 +SK_IOC IoC,            /* I/O Context */
30259 +int            Port,           /* Port Index (MAC_1 + n) */
30260  SK_BOOL        AutoNeg)        /* Is Auto-negotiation used ? */
30261  {
30262         SK_GEPORT       *pPrt;          /* GIni Port struct pointer */
30263         int                     Done;
30264         SK_U16          Isrc;           /* Interrupt source register */
30265 -       SK_U16          PhyStat;        /* Phy Status Register */
30266 +       SK_U16          PhyStat;        /* PHY Status Register */
30267         SK_U16          ResAb;          /* Master/Slave resolution */
30268         SK_U16          Ctrl;           /* Broadcom control flags */
30269  #ifdef DEBUG
30270 @@ -1318,74 +1787,6 @@
30271         /* Check for No HCD Link events (#10523) */
30272         SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_STAT, &Isrc);
30273
30274 -#ifdef xDEBUG
30275 -       if ((Isrc & ~(PHY_B_IS_HCT | PHY_B_IS_LCT) ==
30276 -               (PHY_B_IS_SCR_S_ER | PHY_B_IS_RRS_CHANGE | PHY_B_IS_LRS_CHANGE)) {
30277 -
30278 -               SK_U32  Stat1, Stat2, Stat3;
30279 -
30280 -               Stat1 = 0;
30281 -               SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_MASK, &Stat1);
30282 -               CMSMPrintString(
30283 -                       pAC->pConfigTable,
30284 -                       MSG_TYPE_RUNTIME_INFO,
30285 -                       "CheckUp1 - Stat: %x, Mask: %x",
30286 -                       (void *)Isrc,
30287 -                       (void *)Stat1);
30288 -
30289 -               Stat1 = 0;
30290 -               SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_CTRL, &Stat1);
30291 -               Stat2 = 0;
30292 -               SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_STAT, &Stat2);
30293 -               Stat1 = Stat1 << 16 | Stat2;
30294 -               Stat2 = 0;
30295 -               SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_ADV, &Stat2);
30296 -               Stat3 = 0;
30297 -               SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &Stat3);
30298 -               Stat2 = Stat2 << 16 | Stat3;
30299 -               CMSMPrintString(
30300 -                       pAC->pConfigTable,
30301 -                       MSG_TYPE_RUNTIME_INFO,
30302 -                       "Ctrl/Stat: %x, AN Adv/LP: %x",
30303 -                       (void *)Stat1,
30304 -                       (void *)Stat2);
30305 -
30306 -               Stat1 = 0;
30307 -               SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_EXP, &Stat1);
30308 -               Stat2 = 0;
30309 -               SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_EXT_STAT, &Stat2);
30310 -               Stat1 = Stat1 << 16 | Stat2;
30311 -               Stat2 = 0;
30312 -               SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_CTRL, &Stat2);
30313 -               Stat3 = 0;
30314 -               SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &Stat3);
30315 -               Stat2 = Stat2 << 16 | Stat3;
30316 -               CMSMPrintString(
30317 -                       pAC->pConfigTable,
30318 -                       MSG_TYPE_RUNTIME_INFO,
30319 -                       "AN Exp/IEEE Ext: %x, 1000T Ctrl/Stat: %x",
30320 -                       (void *)Stat1,
30321 -                       (void *)Stat2);
30322 -
30323 -               Stat1 = 0;
30324 -               SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_CTRL, &Stat1);
30325 -               Stat2 = 0;
30326 -               SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_STAT, &Stat2);
30327 -               Stat1 = Stat1 << 16 | Stat2;
30328 -               Stat2 = 0;
30329 -               SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &Stat2);
30330 -               Stat3 = 0;
30331 -               SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_STAT, &Stat3);
30332 -               Stat2 = Stat2 << 16 | Stat3;
30333 -               CMSMPrintString(
30334 -                       pAC->pConfigTable,
30335 -                       MSG_TYPE_RUNTIME_INFO,
30336 -                       "PHY Ext Ctrl/Stat: %x, Aux Ctrl/Stat: %x",
30337 -                       (void *)Stat1,
30338 -                       (void *)Stat2);
30339 -       }
30340 -#endif /* DEBUG */
30341 -
30342         if ((Isrc & (PHY_B_IS_NO_HDCL /* | PHY_B_IS_NO_HDC */)) != 0) {
30343                 /*
30344                  * Workaround BCom Errata:
30345 @@ -1398,14 +1799,6 @@
30346                         (SK_U16)(Ctrl & ~PHY_CT_LOOP));
30347                 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30348                         ("No HCD Link event, Port %d\n", Port));
30349 -#ifdef xDEBUG
30350 -               CMSMPrintString(
30351 -                       pAC->pConfigTable,
30352 -                       MSG_TYPE_RUNTIME_INFO,
30353 -                       "No HCD link event, port %d.",
30354 -                       (void *)Port,
30355 -                       (void *)NULL);
30356 -#endif /* DEBUG */
30357         }
30358
30359         /* Not obsolete: link status bit is latched to 0 and autoclearing! */
30360 @@ -1415,72 +1808,6 @@
30361                 return(SK_HW_PS_NONE);
30362         }
30363
30364 -#ifdef xDEBUG
30365 -       {
30366 -               SK_U32  Stat1, Stat2, Stat3;
30367 -
30368 -               Stat1 = 0;
30369 -               SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_MASK, &Stat1);
30370 -               CMSMPrintString(
30371 -                       pAC->pConfigTable,
30372 -                       MSG_TYPE_RUNTIME_INFO,
30373 -                       "CheckUp1a - Stat: %x, Mask: %x",
30374 -                       (void *)Isrc,
30375 -                       (void *)Stat1);
30376 -
30377 -               Stat1 = 0;
30378 -               SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_CTRL, &Stat1);
30379 -               Stat2 = 0;
30380 -               SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_STAT, &PhyStat);
30381 -               Stat1 = Stat1 << 16 | PhyStat;
30382 -               Stat2 = 0;
30383 -               SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_ADV, &Stat2);
30384 -               Stat3 = 0;
30385 -               SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &Stat3);
30386 -               Stat2 = Stat2 << 16 | Stat3;
30387 -               CMSMPrintString(
30388 -                       pAC->pConfigTable,
30389 -                       MSG_TYPE_RUNTIME_INFO,
30390 -                       "Ctrl/Stat: %x, AN Adv/LP: %x",
30391 -                       (void *)Stat1,
30392 -                       (void *)Stat2);
30393 -
30394 -               Stat1 = 0;
30395 -               SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_EXP, &Stat1);
30396 -               Stat2 = 0;
30397 -               SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_EXT_STAT, &Stat2);
30398 -               Stat1 = Stat1 << 16 | Stat2;
30399 -               Stat2 = 0;
30400 -               SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_CTRL, &Stat2);
30401 -               Stat3 = 0;
30402 -               SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &ResAb);
30403 -               Stat2 = Stat2 << 16 | ResAb;
30404 -               CMSMPrintString(
30405 -                       pAC->pConfigTable,
30406 -                       MSG_TYPE_RUNTIME_INFO,
30407 -                       "AN Exp/IEEE Ext: %x, 1000T Ctrl/Stat: %x",
30408 -                       (void *)Stat1,
30409 -                       (void *)Stat2);
30410 -
30411 -               Stat1 = 0;
30412 -               SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_CTRL, &Stat1);
30413 -               Stat2 = 0;
30414 -               SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_STAT, &Stat2);
30415 -               Stat1 = Stat1 << 16 | Stat2;
30416 -               Stat2 = 0;
30417 -               SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &Stat2);
30418 -               Stat3 = 0;
30419 -               SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_STAT, &Stat3);
30420 -               Stat2 = Stat2 << 16 | Stat3;
30421 -               CMSMPrintString(
30422 -                       pAC->pConfigTable,
30423 -                       MSG_TYPE_RUNTIME_INFO,
30424 -                       "PHY Ext Ctrl/Stat: %x, Aux Ctrl/Stat: %x",
30425 -                       (void *)Stat1,
30426 -                       (void *)Stat2);
30427 -       }
30428 -#endif /* DEBUG */
30429 -
30430         /*
30431          * Here we usually can check whether the link is in sync and
30432          * auto-negotiation is done.
30433 @@ -1489,7 +1816,7 @@
30434         SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_STAT, &PhyStat);
30435
30436         SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat);
30437 -
30438 +
30439         SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30440                 ("CheckUp Port %d, PhyStat: 0x%04X\n", Port, PhyStat));
30441
30442 @@ -1497,88 +1824,62 @@
30443
30444         if ((ResAb & PHY_B_1000S_MSF) != 0) {
30445                 /* Error */
30446 -               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30447 -                       ("Master/Slave Fault port %d\n", Port));
30448 -
30449 +               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
30450 +                       ("Master/Slave Fault, ResAb: 0x%04X\n", ResAb));
30451 +
30452                 pPrt->PAutoNegFail = SK_TRUE;
30453                 pPrt->PMSStatus = SK_MS_STAT_FAULT;
30454 -
30455 +
30456                 return(SK_HW_PS_RESTART);
30457         }
30458
30459         if ((PhyStat & PHY_ST_LSYNC) == 0) {
30460                 return(SK_HW_PS_NONE);
30461         }
30462 -
30463 +
30464         pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
30465                 SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE;
30466 -
30467 +
30468         SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30469                 ("Port %d, ResAb: 0x%04X\n", Port, ResAb));
30470
30471         if (AutoNeg) {
30472 +               /* Auto-Negotiation Over ? */
30473                 if ((PhyStat & PHY_ST_AN_OVER) != 0) {
30474 -
30475 +
30476                         SkHWLinkUp(pAC, IoC, Port);
30477 -
30478 +
30479                         Done = SkMacAutoNegDone(pAC, IoC, Port);
30480 -
30481 +
30482                         if (Done != SK_AND_OK) {
30483  #ifdef DEBUG
30484                                 /* Get PHY parameters, for debugging only */
30485                                 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &LpAb);
30486                                 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &ExtStat);
30487 -                               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30488 +                               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
30489                                         ("AutoNeg FAIL Port %d (LpAb %x, 1000TStat %x)\n",
30490                                         Port, LpAb, ExtStat));
30491  #endif /* DEBUG */
30492                                 return(SK_HW_PS_RESTART);
30493                         }
30494                         else {
30495 -#ifdef xDEBUG
30496 -                               /* Dummy read ISR to prevent extra link downs/ups */
30497 -                               SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_STAT, &ExtStat);
30498 -
30499 -                               if ((ExtStat & ~(PHY_B_IS_HCT | PHY_B_IS_LCT)) != 0) {
30500 -                                       CMSMPrintString(
30501 -                                               pAC->pConfigTable,
30502 -                                               MSG_TYPE_RUNTIME_INFO,
30503 -                                               "CheckUp2 - Stat: %x",
30504 -                                               (void *)ExtStat,
30505 -                                               (void *)NULL);
30506 -                               }
30507 -#endif /* DEBUG */
30508                                 return(SK_HW_PS_LINK);
30509                         }
30510                 }
30511         }
30512         else {  /* !AutoNeg */
30513 -               /* Link is up and we don't need more. */
30514 +               /* Link is up and we don't need more */
30515  #ifdef DEBUG
30516 -               if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) {
30517 -                       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30518 +               if (pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_AUTO) {
30519 +                       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
30520                                 ("ERROR: Lipa auto detected on port %d\n", Port));
30521                 }
30522  #endif /* DEBUG */
30523
30524 -#ifdef xDEBUG
30525 -               /* Dummy read ISR to prevent extra link downs/ups */
30526 -               SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_STAT, &ExtStat);
30527 -
30528 -               if ((ExtStat & ~(PHY_B_IS_HCT | PHY_B_IS_LCT)) != 0) {
30529 -                       CMSMPrintString(
30530 -                               pAC->pConfigTable,
30531 -                               MSG_TYPE_RUNTIME_INFO,
30532 -                               "CheckUp3 - Stat: %x",
30533 -                               (void *)ExtStat,
30534 -                               (void *)NULL);
30535 -               }
30536 -#endif /* DEBUG */
30537 -
30538                 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
30539                         ("Link sync(GP), Port %d\n", Port));
30540                 SkHWLinkUp(pAC, IoC, Port);
30541 -
30542 +
30543                 return(SK_HW_PS_LINK);
30544         }
30545
30546 @@ -1599,17 +1900,18 @@
30547   */
30548  static int SkGePortCheckUpGmac(
30549  SK_AC  *pAC,           /* Adapter Context */
30550 -SK_IOC IoC,            /* IO Context */
30551 -int            Port,           /* Which port should be checked */
30552 +SK_IOC IoC,            /* I/O Context */
30553 +int            Port,           /* Port Index (MAC_1 + n) */
30554  SK_BOOL        AutoNeg)        /* Is Auto-negotiation used ? */
30555  {
30556         SK_GEPORT       *pPrt;          /* GIni Port struct pointer */
30557         int                     Done;
30558 -       SK_U16          PhyIsrc;        /* PHY Interrupt source */
30559 -       SK_U16          PhyStat;        /* PPY Status */
30560 +       SK_U16          PhyStat;        /* PHY Status */
30561         SK_U16          PhySpecStat;/* PHY Specific Status */
30562         SK_U16          ResAb;          /* Master/Slave resolution */
30563 +#ifndef SK_SLIM
30564         SK_EVPARA       Para;
30565 +#endif /* !SK_SLIM */
30566  #ifdef DEBUG
30567         SK_U16          Word;           /* I/O helper */
30568  #endif /* DEBUG */
30569 @@ -1626,107 +1928,145 @@
30570         SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30571                 ("CheckUp Port %d, PhyStat: 0x%04X\n", Port, PhyStat));
30572
30573 -       /* Read PHY Interrupt Status */
30574 -       SkGmPhyRead(pAC, IoC, Port, PHY_MARV_INT_STAT, &PhyIsrc);
30575 +       SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat);
30576
30577 -       if ((PhyIsrc & PHY_M_IS_AN_COMPL) != 0) {
30578 -               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30579 -                       ("Auto-Negotiation Completed, PhyIsrc: 0x%04X\n", PhyIsrc));
30580 -       }
30581 +       if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
30582
30583 -       if ((PhyIsrc & PHY_M_IS_LSP_CHANGE) != 0) {
30584 -               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30585 -                       ("Link Speed Changed, PhyIsrc: 0x%04X\n", PhyIsrc));
30586 -       }
30587 +               SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_STAT, &ResAb);
30588
30589 -       SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat);
30590 -
30591 -       SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_STAT, &ResAb);
30592 +               if ((ResAb & PHY_B_1000S_MSF) != 0) {
30593 +                       /* Error */
30594 +                       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
30595 +                               ("Master/Slave Fault, ResAb: 0x%04X\n", ResAb));
30596
30597 -       if ((ResAb & PHY_B_1000S_MSF) != 0) {
30598 -               /* Error */
30599 -               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30600 -                       ("Master/Slave Fault port %d\n", Port));
30601 -
30602 -               pPrt->PAutoNegFail = SK_TRUE;
30603 -               pPrt->PMSStatus = SK_MS_STAT_FAULT;
30604 -
30605 -               return(SK_HW_PS_RESTART);
30606 +                       pPrt->PAutoNegFail = SK_TRUE;
30607 +                       pPrt->PMSStatus = SK_MS_STAT_FAULT;
30608 +
30609 +                       return(SK_HW_PS_RESTART);
30610 +               }
30611         }
30612
30613         /* Read PHY Specific Status */
30614         SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &PhySpecStat);
30615 -
30616 +
30617         SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30618                 ("Phy1000BT: 0x%04X, PhySpecStat: 0x%04X\n", ResAb, PhySpecStat));
30619
30620 -#ifdef DEBUG
30621 +#if (defined(DEBUG) && !defined(SK_SLIM))
30622 +       /* Read PHY Auto-Negotiation Expansion */
30623         SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_EXP, &Word);
30624
30625 -       if ((PhyIsrc & PHY_M_IS_AN_PR) != 0 || (Word & PHY_ANE_RX_PG) != 0 ||
30626 -               (PhySpecStat & PHY_M_PS_PAGE_REC) != 0)  {
30627 +       if (pAC->GIni.GICopperType && (Word & PHY_ANE_LP_CAP) == 0) {
30628 +
30629 +               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30630 +                       ("Link Partner not Auto-Neg. able, AN Exp.: 0x%04X\n", Word));
30631 +       }
30632 +
30633 +       if ((Word & PHY_ANE_RX_PG) != 0 ||
30634 +               (PhySpecStat & PHY_M_PS_PAGE_REC) != 0) {
30635                 /* Read PHY Next Page Link Partner */
30636                 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_NEPG_LP, &Word);
30637
30638                 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30639 -                       ("Page Received, NextPage: 0x%04X\n", Word));
30640 +                       ("Page received, NextPage: 0x%04X\n", Word));
30641         }
30642 -#endif /* DEBUG */
30643 +#endif /* DEBUG && !SK_SLIM */
30644
30645         if ((PhySpecStat & PHY_M_PS_LINK_UP) == 0) {
30646 +               /* Link down */
30647                 return(SK_HW_PS_NONE);
30648         }
30649 -
30650 -       if ((PhySpecStat & PHY_M_PS_DOWNS_STAT) != 0 ||
30651 -               (PhyIsrc & PHY_M_IS_DOWNSH_DET) != 0) {
30652 -               /* Downshift detected */
30653 -               SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E025, SKERR_SIRQ_E025MSG);
30654 -
30655 -               Para.Para64 = Port;
30656 -               SkEventQueue(pAC, SKGE_DRV, SK_DRV_DOWNSHIFT_DET, Para);
30657 -
30658 -               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30659 -                       ("Downshift detected, PhyIsrc: 0x%04X\n", PhyIsrc));
30660 +
30661 +#ifdef XXX
30662 +       SK_U16          PhyInt;
30663 +       /* Read PHY Interrupt Status */
30664 +       SkGmPhyRead(pAC, IoC, Port, PHY_MARV_INT_STAT, &PhyInt);
30665 +
30666 +       /* cross check that the link is really up */
30667 +       if ((PhyInt & PHY_M_IS_LST_CHANGE) == 0) {
30668 +               /* Link Status unchanged */
30669 +               return(SK_HW_PS_NONE);
30670         }
30671 +#endif /* XXX */
30672 +
30673 +#ifndef SK_SLIM
30674 +       if (pAC->GIni.GICopperType) {
30675 +
30676 +               if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
30677 +
30678 +                       if ((PhySpecStat & PHY_M_PS_DOWNS_STAT) != 0) {
30679 +                               /* Downshift detected */
30680 +                               Para.Para64 = Port;
30681 +                               SkEventQueue(pAC, SKGE_DRV, SK_DRV_DOWNSHIFT_DET, Para);
30682 +
30683 +                               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30684 +                                       ("Downshift detected, PhySpecStat: 0x%04X\n", PhySpecStat));
30685 +
30686 +                               SK_ERR_LOG(pAC, SK_ERRCL_CONFIG, SKERR_SIRQ_E025,
30687 +                                       SKERR_SIRQ_E025MSG);
30688 +                       }
30689 +
30690 +                       pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
30691 +                               SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE;
30692 +               }
30693 +
30694 +               if ((PhySpecStat & PHY_M_PS_MDI_X_STAT) != 0) {
30695 +                       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30696 +                               ("MDI Xover detected, PhyStat: 0x%04X\n", PhySpecStat));
30697 +               }
30698 +
30699 +               /* on PHY 88E1112 & 88E1145 cable length is in Reg. 26, Page 5 */
30700 +               if (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL ||
30701 +                       pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) {
30702 +                       /* select page 5 to access VCT DSP distance register */
30703 +                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 5);
30704 +
30705 +                       /* get VCT DSP distance */
30706 +                       SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL_2, &PhySpecStat);
30707 +
30708 +                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0);
30709 +
30710 +                       pPrt->PCableLen = (SK_U8)(PhySpecStat & PHY_M_EC2_FO_AM_MSK);
30711 +               }
30712 +               else {
30713 +                       pPrt->PCableLen = (SK_U8)((PhySpecStat & PHY_M_PS_CABLE_MSK) >> 7);
30714 +               }
30715 +       }
30716 +#endif /* !SK_SLIM */
30717
30718 -       pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
30719 -               SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE;
30720 -
30721 -       pPrt->PCableLen = (SK_U8)((PhySpecStat & PHY_M_PS_CABLE_MSK) >> 7);
30722 -
30723         if (AutoNeg) {
30724 -               /* Auto-Negotiation Over ? */
30725 +               /* Auto-Negotiation Complete ? */
30726                 if ((PhyStat & PHY_ST_AN_OVER) != 0) {
30727 -
30728 +
30729                         SkHWLinkUp(pAC, IoC, Port);
30730 -
30731 +
30732                         Done = SkMacAutoNegDone(pAC, IoC, Port);
30733 -
30734 +
30735                         if (Done != SK_AND_OK) {
30736                                 return(SK_HW_PS_RESTART);
30737                         }
30738 -
30739 +
30740                         return(SK_HW_PS_LINK);
30741                 }
30742         }
30743         else {  /* !AutoNeg */
30744 -               /* Link is up and we don't need more */
30745 -#ifdef DEBUG
30746 -               if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) {
30747 -                       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30748 +#if (defined(DEBUG) && !defined(SK_SLIM))
30749 +               if (pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_AUTO) {
30750 +                       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
30751                                 ("ERROR: Lipa auto detected on port %d\n", Port));
30752                 }
30753 -#endif /* DEBUG */
30754 +#endif /* DEBUG && !SK_SLIM */
30755
30756                 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
30757                         ("Link sync, Port %d\n", Port));
30758                 SkHWLinkUp(pAC, IoC, Port);
30759 -
30760 +
30761                 return(SK_HW_PS_LINK);
30762         }
30763
30764         return(SK_HW_PS_NONE);
30765  }      /* SkGePortCheckUpGmac */
30766 +
30767  #endif /* YUKON */
30768
30769
30770 @@ -1742,8 +2082,8 @@
30771   */
30772  static int SkGePortCheckUpLone(
30773  SK_AC  *pAC,           /* Adapter Context */
30774 -SK_IOC IoC,            /* IO Context */
30775 -int            Port,           /* Which port should be checked */
30776 +SK_IOC IoC,            /* I/O Context */
30777 +int            Port,           /* Port Index (MAC_1 + n) */
30778  SK_BOOL        AutoNeg)        /* Is Auto-negotiation used ? */
30779  {
30780         SK_GEPORT       *pPrt;          /* GIni Port struct pointer */
30781 @@ -1751,7 +2091,7 @@
30782         SK_U16          Isrc;           /* Interrupt source register */
30783         SK_U16          LpAb;           /* Link Partner Ability */
30784         SK_U16          ExtStat;        /* Extended Status Register */
30785 -       SK_U16          PhyStat;        /* Phy Status Register */
30786 +       SK_U16          PhyStat;        /* PHY Status Register */
30787         SK_U16          StatSum;
30788         SK_U8           NextMode;       /* Next AutoSensing Mode */
30789
30790 @@ -1772,7 +2112,7 @@
30791         StatSum |= PhyStat;
30792
30793         SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat);
30794 -
30795 +
30796         if ((PhyStat & PHY_ST_LSYNC) == 0) {
30797                 /* Save Auto-negotiation Done bit */
30798                 pPrt->PIsave = (SK_U16)(StatSum & PHY_ST_AN_OVER);
30799 @@ -1786,20 +2126,26 @@
30800         }
30801
30802         if (AutoNeg) {
30803 +               /* Auto-Negotiation Over ? */
30804                 if ((StatSum & PHY_ST_AN_OVER) != 0) {
30805 +
30806                         SkHWLinkUp(pAC, IoC, Port);
30807 +
30808                         Done = SkMacAutoNegDone(pAC, IoC, Port);
30809 +
30810                         if (Done != SK_AND_OK) {
30811                                 /* Get PHY parameters, for debugging only */
30812                                 SkXmPhyRead(pAC, IoC, Port, PHY_LONE_AUNE_LP, &LpAb);
30813                                 SkXmPhyRead(pAC, IoC, Port, PHY_LONE_1000T_STAT, &ExtStat);
30814 -                               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30815 +                               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
30816                                         ("AutoNeg FAIL Port %d (LpAb %x, 1000TStat %x)\n",
30817                                          Port, LpAb, ExtStat));
30818 -
30819 +
30820                                 /* Try next possible mode */
30821                                 NextMode = SkHWSenseGetNext(pAC, IoC, Port);
30822 +
30823                                 SkHWLinkDown(pAC, IoC, Port);
30824 +
30825                                 if (Done == SK_AND_DUP_CAP) {
30826                                         /* GoTo next mode */
30827                                         SkHWSenseSetNext(pAC, IoC, Port, NextMode);
30828 @@ -1817,15 +2163,14 @@
30829                                 return(SK_HW_PS_LINK);
30830                         }
30831                 }
30832 -
30833 +
30834                 /* AutoNeg not done, but HW link is up. Check for timeouts */
30835 -               pPrt->PAutoNegTimeOut++;
30836 -               if (pPrt->PAutoNegTimeOut >= SK_AND_MAX_TO) {
30837 +               if (pPrt->PAutoNegTimeOut++ >= SK_AND_MAX_TO) {
30838                         /* Timeout occured */
30839                         SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
30840                                 ("AutoNeg timeout Port %d\n", Port));
30841 -                       if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE &&
30842 -                               pPrt->PLipaAutoNeg != SK_LIPA_AUTO) {
30843 +                       if (pPrt->PLinkModeConf == (SK_U8)SK_LMODE_AUTOSENSE &&
30844 +                               pPrt->PLipaAutoNeg != (SK_U8)SK_LIPA_AUTO) {
30845                                 /* Set Link manually up */
30846                                 SkHWSenseSetNext(pAC, IoC, Port, SK_LMODE_FULL);
30847                                 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
30848 @@ -1839,8 +2184,8 @@
30849         else {
30850                 /* Link is up and we don't need more */
30851  #ifdef DEBUG
30852 -               if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) {
30853 -                       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30854 +               if (pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_AUTO) {
30855 +                       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
30856                                 ("ERROR: Lipa auto detected on port %d\n", Port));
30857                 }
30858  #endif /* DEBUG */
30859 @@ -1850,11 +2195,12 @@
30860                  * extra link down/ups
30861                  */
30862                 SkXmPhyRead(pAC, IoC, Port, PHY_LONE_INT_STAT, &ExtStat);
30863 -
30864 +
30865                 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
30866                         ("Link sync(GP), Port %d\n", Port));
30867 +
30868                 SkHWLinkUp(pAC, IoC, Port);
30869 -
30870 +
30871                 return(SK_HW_PS_LINK);
30872         }
30873
30874 @@ -1873,8 +2219,8 @@
30875   */
30876  static int SkGePortCheckUpNat(
30877  SK_AC  *pAC,           /* Adapter Context */
30878 -SK_IOC IoC,            /* IO Context */
30879 -int            Port,           /* Which port should be checked */
30880 +SK_IOC IoC,            /* I/O Context */
30881 +int            Port,           /* Port Index (MAC_1 + n) */
30882  SK_BOOL        AutoNeg)        /* Is Auto-negotiation used ? */
30883  {
30884         /* todo: National */
30885 @@ -1893,38 +2239,40 @@
30886   */
30887  int    SkGeSirqEvent(
30888  SK_AC          *pAC,           /* Adapter Context */
30889 -SK_IOC         IoC,            /* Io Context */
30890 +SK_IOC         IoC,            /* I/O Context */
30891  SK_U32         Event,          /* Module specific Event */
30892  SK_EVPARA      Para)           /* Event specific Parameter */
30893  {
30894         SK_GEPORT       *pPrt;          /* GIni Port struct pointer */
30895 -       SK_U32          Port;
30896 +       int                     Port;
30897         SK_U32          Val32;
30898         int                     PortStat;
30899 +#ifndef SK_SLIM
30900         SK_U8           Val8;
30901 +#endif
30902  #ifdef GENESIS
30903         SK_U64          Octets;
30904  #endif /* GENESIS */
30905
30906 -       Port = Para.Para32[0];
30907 +       Port = (int)Para.Para32[0];
30908         pPrt = &pAC->GIni.GP[Port];
30909
30910         switch (Event) {
30911         case SK_HWEV_WATIM:
30912                 if (pPrt->PState == SK_PRT_RESET) {
30913 -
30914 +
30915                         PortStat = SK_HW_PS_NONE;
30916                 }
30917                 else {
30918                         /* Check whether port came up */
30919 -                       PortStat = SkGePortCheckUp(pAC, IoC, (int)Port);
30920 +                       PortStat = SkGePortCheckUp(pAC, IoC, Port);
30921                 }
30922
30923                 switch (PortStat) {
30924                 case SK_HW_PS_RESTART:
30925                         if (pPrt->PHWLinkUp) {
30926                                 /* Set Link to down */
30927 -                               SkHWLinkDown(pAC, IoC, (int)Port);
30928 +                               SkHWLinkDown(pAC, IoC, Port);
30929
30930                                 /*
30931                                  * Signal directly to RLMT to ensure correct
30932 @@ -1942,22 +2290,28 @@
30933                         SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_UP, Para);
30934                         break;
30935                 }
30936 -
30937 +
30938                 /* Start again the check Timer */
30939                 if (pPrt->PHWLinkUp) {
30940 +
30941                         Val32 = SK_WA_ACT_TIME;
30942                 }
30943                 else {
30944                         Val32 = SK_WA_INA_TIME;
30945 -               }
30946
30947 -               /* Todo: still needed for non-XMAC PHYs??? */
30948 +                       if (pAC->GIni.GIYukon) {
30949 +                               Val32 *= 5;
30950 +                       }
30951 +               }
30952                 /* Start workaround Errata #2 timer */
30953                 SkTimerStart(pAC, IoC, &pPrt->PWaTimer, Val32,
30954                         SKGE_HWAC, SK_HWEV_WATIM, Para);
30955 +
30956                 break;
30957
30958         case SK_HWEV_PORT_START:
30959 +
30960 +#ifndef SK_SLIM
30961                 if (pPrt->PHWLinkUp) {
30962                         /*
30963                          * Signal directly to RLMT to ensure correct
30964 @@ -1965,8 +2319,9 @@
30965                          */
30966                         SkRlmtEvent(pAC, IoC, SK_RLMT_LINK_DOWN, Para);
30967                 }
30968 +#endif /* !SK_SLIM */
30969
30970 -               SkHWLinkDown(pAC, IoC, (int)Port);
30971 +               SkHWLinkDown(pAC, IoC, Port);
30972
30973                 /* Schedule Port RESET */
30974                 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Para);
30975 @@ -1974,9 +2329,11 @@
30976                 /* Start workaround Errata #2 timer */
30977                 SkTimerStart(pAC, IoC, &pPrt->PWaTimer, SK_WA_INA_TIME,
30978                         SKGE_HWAC, SK_HWEV_WATIM, Para);
30979 +
30980                 break;
30981
30982         case SK_HWEV_PORT_STOP:
30983 +#ifndef SK_SLIM
30984                 if (pPrt->PHWLinkUp) {
30985                         /*
30986                          * Signal directly to RLMT to ensure correct
30987 @@ -1984,20 +2341,22 @@
30988                          */
30989                         SkRlmtEvent(pAC, IoC, SK_RLMT_LINK_DOWN, Para);
30990                 }
30991 +#endif /* !SK_SLIM */
30992
30993                 /* Stop Workaround Timer */
30994                 SkTimerStop(pAC, IoC, &pPrt->PWaTimer);
30995
30996 -               SkHWLinkDown(pAC, IoC, (int)Port);
30997 +               SkHWLinkDown(pAC, IoC, Port);
30998                 break;
30999
31000 +#ifndef SK_SLIM
31001         case SK_HWEV_UPDATE_STAT:
31002                 /* We do NOT need to update any statistics */
31003                 break;
31004
31005         case SK_HWEV_CLEAR_STAT:
31006                 /* We do NOT need to clear any statistics */
31007 -               for (Port = 0; Port < (SK_U32)pAC->GIni.GIMacsFound; Port++) {
31008 +               for (Port = 0; Port < pAC->GIni.GIMacsFound; Port++) {
31009                         pPrt->PPrevRx = 0;
31010                         pPrt->PPrevFcs = 0;
31011                         pPrt->PPrevShorts = 0;
31012 @@ -2058,6 +2417,7 @@
31013                         SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_START, Para);
31014                 }
31015                 break;
31016 +#endif /* !SK_SLIM */
31017
31018  #ifdef GENESIS
31019         case SK_HWEV_HALFDUP_CHK:
31020 @@ -2069,17 +2429,18 @@
31021                         pPrt->HalfDupTimerActive = SK_FALSE;
31022                         if (pPrt->PLinkModeStatus == SK_LMODE_STAT_HALF ||
31023                                 pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOHALF) {
31024 +
31025                                 /* Snap statistic counters */
31026                                 (void)SkXmUpdateStats(pAC, IoC, Port);
31027
31028                                 (void)SkXmMacStatistic(pAC, IoC, Port, XM_TXO_OK_HI, &Val32);
31029
31030                                 Octets = (SK_U64)Val32 << 32;
31031 -
31032 +
31033                                 (void)SkXmMacStatistic(pAC, IoC, Port, XM_TXO_OK_LO, &Val32);
31034
31035                                 Octets += Val32;
31036 -
31037 +
31038                                 if (pPrt->LastOctets == Octets) {
31039                                         /* Tx hanging, a FIFO flush restarts it */
31040                                         SkMacFlushTxFifo(pAC, IoC, Port);
31041 @@ -2088,7 +2449,7 @@
31042                 }
31043                 break;
31044  #endif /* GENESIS */
31045 -
31046 +
31047         default:
31048                 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_SIRQ_E001, SKERR_SIRQ_E001MSG);
31049                 break;
31050 @@ -2109,8 +2470,8 @@
31051   */
31052  static void SkPhyIsrBcom(
31053  SK_AC          *pAC,           /* Adapter Context */
31054 -SK_IOC         IoC,            /* Io Context */
31055 -int                    Port,           /* Port Num = PHY Num */
31056 +SK_IOC         IoC,            /* I/O Context */
31057 +int                    Port,           /* Port Index (MAC_1 + n) */
31058  SK_U16         IStatus)        /* Interrupt Status */
31059  {
31060         SK_GEPORT       *pPrt;          /* GIni Port struct pointer */
31061 @@ -2123,7 +2484,7 @@
31062                 SK_ERR_LOG(pAC, SK_ERRCL_HW | SK_ERRCL_INIT, SKERR_SIRQ_E022,
31063                         SKERR_SIRQ_E022MSG);
31064         }
31065 -
31066 +
31067         if ((IStatus & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) != 0) {
31068
31069                 SkHWLinkDown(pAC, IoC, Port);
31070 @@ -2152,47 +2513,83 @@
31071   */
31072  static void SkPhyIsrGmac(
31073  SK_AC          *pAC,           /* Adapter Context */
31074 -SK_IOC         IoC,            /* Io Context */
31075 -int                    Port,           /* Port Num = PHY Num */
31076 +SK_IOC         IoC,            /* I/O Context */
31077 +int                    Port,           /* Port Index (MAC_1 + n) */
31078  SK_U16         IStatus)        /* Interrupt Status */
31079  {
31080 -       SK_GEPORT       *pPrt;          /* GIni Port struct pointer */
31081 +       SK_GEPORT       *pPrt;  /* GIni Port struct pointer */
31082         SK_EVPARA       Para;
31083 +#ifdef XXX
31084         SK_U16          Word;
31085 +#endif /* XXX */
31086
31087         pPrt = &pAC->GIni.GP[Port];
31088
31089 -       if ((IStatus & (PHY_M_IS_AN_PR | PHY_M_IS_LST_CHANGE)) != 0) {
31090 -
31091 -               SkHWLinkDown(pAC, IoC, Port);
31092 +       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
31093 +               ("Port %d PHY IRQ, PhyIsrc: 0x%04X\n", Port, IStatus));
31094
31095 -               SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_ADV, &Word);
31096 +       if ((IStatus & PHY_M_IS_LST_CHANGE) != 0) {
31097
31098                 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
31099 -                       ("AutoNeg.Adv: 0x%04X\n", Word));
31100 -
31101 -               /* Set Auto-negotiation advertisement */
31102 -               if (pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM) {
31103 -                       /* restore Asymmetric Pause bit */
31104 -                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_AUNE_ADV,
31105 -                               (SK_U16)(Word | PHY_M_AN_ASP));
31106 -               }
31107 -
31108 +                       ("Link Status changed\n"));
31109 +
31110                 Para.Para32[0] = (SK_U32)Port;
31111 -               /* Signal to RLMT */
31112 -               SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
31113 +
31114 +               if (pPrt->PHWLinkUp) {
31115 +
31116 +                       SkHWLinkDown(pAC, IoC, Port);
31117 +
31118 +#ifdef XXX
31119 +                       SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_ADV, &Word);
31120 +
31121 +                       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
31122 +                               ("AutoNeg.Adv: 0x%04X\n", Word));
31123 +
31124 +                       /* Set Auto-negotiation advertisement */
31125 +                       if (pAC->GIni.GIChipId != CHIP_ID_YUKON_FE &&
31126 +                               pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM) {
31127 +                               /* restore Asymmetric Pause bit */
31128 +                               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_AUNE_ADV,
31129 +                                       (SK_U16)(Word | PHY_M_AN_ASP));
31130 +                       }
31131 +#endif /* XXX */
31132 +
31133 +                       /* Signal to RLMT */
31134 +                       SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
31135 +               }
31136 +               else {
31137 +                       if ((IStatus & PHY_M_IS_AN_COMPL) != 0) {
31138 +                               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
31139 +                                       ("Auto-Negotiation completed\n"));
31140 +                       }
31141 +
31142 +                       if ((IStatus & PHY_M_IS_LSP_CHANGE) != 0) {
31143 +                               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
31144 +                                       ("Link Speed changed\n"));
31145 +                       }
31146 +
31147 +                       SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_WATIM, Para);
31148 +               }
31149         }
31150 -
31151 +
31152         if ((IStatus & PHY_M_IS_AN_ERROR) != 0) {
31153 -               /* Auto-Negotiation Error */
31154 -               SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E023, SKERR_SIRQ_E023MSG);
31155 +               /* the copper PHY makes 1 retry */
31156 +               if (pAC->GIni.GICopperType) {
31157 +                       /* not logged as error, it might be the first attempt */
31158 +                       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
31159 +                               ("Auto-Negotiation Error\n"));
31160 +               }
31161 +               else {
31162 +                       /* Auto-Negotiation Error */
31163 +                       SK_ERR_LOG(pAC, SK_ERRCL_CONFIG, SKERR_SIRQ_E023, SKERR_SIRQ_E023MSG);
31164 +               }
31165         }
31166 -
31167 +
31168         if ((IStatus & PHY_M_IS_FIFO_ERROR) != 0) {
31169                 /* FIFO Overflow/Underrun Error */
31170                 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E024, SKERR_SIRQ_E024MSG);
31171         }
31172 -
31173 +
31174  }      /* SkPhyIsrGmac */
31175  #endif /* YUKON */
31176
31177 @@ -2208,14 +2605,14 @@
31178   */
31179  static void SkPhyIsrLone(
31180  SK_AC  *pAC,           /* Adapter Context */
31181 -SK_IOC IoC,            /* Io Context */
31182 -int            Port,           /* Port Num = PHY Num */
31183 +SK_IOC IoC,            /* I/O Context */
31184 +int            Port,           /* Port Index (MAC_1 + n) */
31185  SK_U16 IStatus)        /* Interrupt Status */
31186  {
31187         SK_EVPARA       Para;
31188
31189         if (IStatus & (PHY_L_IS_DUP | PHY_L_IS_ISOL)) {
31190 -
31191 +
31192                 SkHWLinkDown(pAC, IoC, Port);
31193
31194                 Para.Para32[0] = (SK_U32)Port;
31195 @@ -2227,3 +2624,4 @@
31196  #endif /* OTHER_PHY */
31197
31198  /* End of File */
31199 +
31200 diff -ruN linux/drivers/net/sk98lin/ski2c.c linux-new/drivers/net/sk98lin/ski2c.c
31201 --- linux/drivers/net/sk98lin/ski2c.c   2006-09-20 05:42:06.000000000 +0200
31202 +++ linux-new/drivers/net/sk98lin/ski2c.c       1970-01-01 01:00:00.000000000 +0100
31203 @@ -1,1296 +0,0 @@
31204 -/******************************************************************************
31205 - *
31206 - * Name:       ski2c.c
31207 - * Project:    Gigabit Ethernet Adapters, TWSI-Module
31208 - * Version:    $Revision$
31209 - * Date:       $Date$
31210 - * Purpose:    Functions to access Voltage and Temperature Sensor
31211 - *
31212 - ******************************************************************************/
31213 -
31214 -/******************************************************************************
31215 - *
31216 - *     (C)Copyright 1998-2002 SysKonnect.
31217 - *     (C)Copyright 2002-2003 Marvell.
31218 - *
31219 - *     This program is free software; you can redistribute it and/or modify
31220 - *     it under the terms of the GNU General Public License as published by
31221 - *     the Free Software Foundation; either version 2 of the License, or
31222 - *     (at your option) any later version.
31223 - *
31224 - *     The information in this file is provided "AS IS" without warranty.
31225 - *
31226 - ******************************************************************************/
31227 -
31228 -/*
31229 - *     I2C Protocol
31230 - */
31231 -#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
31232 -static const char SysKonnectFileId[] =
31233 -       "@(#) $Id$ (C) Marvell. ";
31234 -#endif
31235 -
31236 -#include "h/skdrv1st.h"                /* Driver Specific Definitions */
31237 -#include "h/lm80.h"
31238 -#include "h/skdrv2nd.h"                /* Adapter Control- and Driver specific Def. */
31239 -
31240 -#ifdef __C2MAN__
31241 -/*
31242 -       I2C protocol implementation.
31243 -
31244 -       General Description:
31245 -
31246 -       The I2C protocol is used for the temperature sensors and for
31247 -       the serial EEPROM which hold the configuration.
31248 -
31249 -       This file covers functions that allow to read write and do
31250 -       some bulk requests a specified I2C address.
31251 -
31252 -       The Genesis has 2 I2C buses. One for the EEPROM which holds
31253 -       the VPD Data and one for temperature and voltage sensor.
31254 -       The following picture shows the I2C buses, I2C devices and
31255 -       their control registers.
31256 -
31257 -       Note: The VPD functions are in skvpd.c
31258 -.
31259 -.      PCI Config I2C Bus for VPD Data:
31260 -.
31261 -.                    +------------+
31262 -.                    | VPD EEPROM |
31263 -.                    +------------+
31264 -.                           |
31265 -.                           | <-- I2C
31266 -.                           |
31267 -.               +-----------+-----------+
31268 -.               |                       |
31269 -.      +-----------------+     +-----------------+
31270 -.      | PCI_VPD_ADR_REG |     | PCI_VPD_DAT_REG |
31271 -.      +-----------------+     +-----------------+
31272 -.
31273 -.
31274 -.      I2C Bus for LM80 sensor:
31275 -.
31276 -.                      +-----------------+
31277 -.                      | Temperature and |
31278 -.                      | Voltage Sensor  |
31279 -.                      |       LM80      |
31280 -.                      +-----------------+
31281 -.                              |
31282 -.                              |
31283 -.                      I2C --> |
31284 -.                              |
31285 -.                           +----+
31286 -.           +-------------->| OR |<--+
31287 -.           |               +----+   |
31288 -.     +------+------+                |
31289 -.     |                    |                 |
31290 -. +--------+   +--------+      +----------+
31291 -. | B2_I2C |   | B2_I2C |      |  B2_I2C  |
31292 -. | _CTRL  |   | _DATA  |      |   _SW    |
31293 -. +--------+   +--------+      +----------+
31294 -.
31295 -       The I2C bus may be driven by the B2_I2C_SW or by the B2_I2C_CTRL
31296 -       and B2_I2C_DATA registers.
31297 -       For driver software it is recommended to use the I2C control and
31298 -       data register, because I2C bus timing is done by the ASIC and
31299 -       an interrupt may be received when the I2C request is completed.
31300 -
31301 -       Clock Rate Timing:                      MIN     MAX     generated by
31302 -               VPD EEPROM:                     50 kHz  100 kHz         HW
31303 -               LM80 over I2C Ctrl/Data reg.    50 kHz  100 kHz         HW
31304 -               LM80 over B2_I2C_SW register    0       400 kHz         SW
31305 -
31306 -       Note:   The clock generated by the hardware is dependend on the
31307 -               PCI clock. If the PCI bus clock is 33 MHz, the I2C/VPD
31308 -               clock is 50 kHz.
31309 - */
31310 -intro()
31311 -{}
31312 -#endif
31313 -
31314 -#ifdef SK_DIAG
31315 -/*
31316 - * I2C Fast Mode timing values used by the LM80.
31317 - * If new devices are added to the I2C bus the timing values have to be checked.
31318 - */
31319 -#ifndef I2C_SLOW_TIMING
31320 -#define        T_CLK_LOW                       1300L   /* clock low time in ns */
31321 -#define        T_CLK_HIGH                       600L   /* clock high time in ns */
31322 -#define T_DATA_IN_SETUP                 100L   /* data in Set-up Time */
31323 -#define T_START_HOLD            600L   /* start condition hold time */
31324 -#define T_START_SETUP           600L   /* start condition Set-up time */
31325 -#define        T_STOP_SETUP             600L   /* stop condition Set-up time */
31326 -#define T_BUS_IDLE                     1300L   /* time the bus must free after Tx */
31327 -#define        T_CLK_2_DATA_OUT         900L   /* max. clock low to data output valid */
31328 -#else  /* I2C_SLOW_TIMING */
31329 -/* I2C Standard Mode Timing */
31330 -#define        T_CLK_LOW                       4700L   /* clock low time in ns */
31331 -#define        T_CLK_HIGH                      4000L   /* clock high time in ns */
31332 -#define T_DATA_IN_SETUP                 250L   /* data in Set-up Time */
31333 -#define T_START_HOLD           4000L   /* start condition hold time */
31334 -#define T_START_SETUP          4700L   /* start condition Set-up time */
31335 -#define        T_STOP_SETUP            4000L   /* stop condition Set-up time */
31336 -#define T_BUS_IDLE                     4700L   /* time the bus must free after Tx */
31337 -#endif /* !I2C_SLOW_TIMING */
31338 -
31339 -#define NS2BCLK(x)     (((x)*125)/10000)
31340 -
31341 -/*
31342 - * I2C Wire Operations
31343 - *
31344 - * About I2C_CLK_LOW():
31345 - *
31346 - * The Data Direction bit (I2C_DATA_DIR) has to be set to input when setting
31347 - * clock to low, to prevent the ASIC and the I2C data client from driving the
31348 - * serial data line simultaneously (ASIC: last bit of a byte = '1', I2C client
31349 - * send an 'ACK'). See also Concentrator Bugreport No. 10192.
31350 - */
31351 -#define I2C_DATA_HIGH(IoC)     SK_I2C_SET_BIT(IoC, I2C_DATA)
31352 -#define        I2C_DATA_LOW(IoC)       SK_I2C_CLR_BIT(IoC, I2C_DATA)
31353 -#define        I2C_DATA_OUT(IoC)       SK_I2C_SET_BIT(IoC, I2C_DATA_DIR)
31354 -#define        I2C_DATA_IN(IoC)        SK_I2C_CLR_BIT(IoC, I2C_DATA_DIR | I2C_DATA)
31355 -#define        I2C_CLK_HIGH(IoC)       SK_I2C_SET_BIT(IoC, I2C_CLK)
31356 -#define        I2C_CLK_LOW(IoC)        SK_I2C_CLR_BIT(IoC, I2C_CLK | I2C_DATA_DIR)
31357 -#define        I2C_START_COND(IoC)     SK_I2C_CLR_BIT(IoC, I2C_CLK)
31358 -
31359 -#define NS2CLKT(x)     ((x*125L)/10000)
31360 -
31361 -/*--------------- I2C Interface Register Functions --------------- */
31362 -
31363 -/*
31364 - * sending one bit
31365 - */
31366 -void SkI2cSndBit(
31367 -SK_IOC IoC,    /* I/O Context */
31368 -SK_U8  Bit)    /* Bit to send */
31369 -{
31370 -       I2C_DATA_OUT(IoC);
31371 -       if (Bit) {
31372 -               I2C_DATA_HIGH(IoC);
31373 -       }
31374 -       else {
31375 -               I2C_DATA_LOW(IoC);
31376 -       }
31377 -       SkDgWaitTime(IoC, NS2BCLK(T_DATA_IN_SETUP));
31378 -       I2C_CLK_HIGH(IoC);
31379 -       SkDgWaitTime(IoC, NS2BCLK(T_CLK_HIGH));
31380 -       I2C_CLK_LOW(IoC);
31381 -}      /* SkI2cSndBit*/
31382 -
31383 -
31384 -/*
31385 - * Signal a start to the I2C Bus.
31386 - *
31387 - * A start is signaled when data goes to low in a high clock cycle.
31388 - *
31389 - * Ends with Clock Low.
31390 - *
31391 - * Status: not tested
31392 - */
31393 -void SkI2cStart(
31394 -SK_IOC IoC)    /* I/O Context */
31395 -{
31396 -       /* Init data and Clock to output lines */
31397 -       /* Set Data high */
31398 -       I2C_DATA_OUT(IoC);
31399 -       I2C_DATA_HIGH(IoC);
31400 -       /* Set Clock high */
31401 -       I2C_CLK_HIGH(IoC);
31402 -
31403 -       SkDgWaitTime(IoC, NS2BCLK(T_START_SETUP));
31404 -
31405 -       /* Set Data Low */
31406 -       I2C_DATA_LOW(IoC);
31407 -
31408 -       SkDgWaitTime(IoC, NS2BCLK(T_START_HOLD));
31409 -
31410 -       /* Clock low without Data to Input */
31411 -       I2C_START_COND(IoC);
31412 -
31413 -       SkDgWaitTime(IoC, NS2BCLK(T_CLK_LOW));
31414 -}      /* SkI2cStart */
31415 -
31416 -
31417 -void SkI2cStop(
31418 -SK_IOC IoC)    /* I/O Context */
31419 -{
31420 -       /* Init data and Clock to output lines */
31421 -       /* Set Data low */
31422 -       I2C_DATA_OUT(IoC);
31423 -       I2C_DATA_LOW(IoC);
31424 -
31425 -       SkDgWaitTime(IoC, NS2BCLK(T_CLK_2_DATA_OUT));
31426 -
31427 -       /* Set Clock high */
31428 -       I2C_CLK_HIGH(IoC);
31429 -
31430 -       SkDgWaitTime(IoC, NS2BCLK(T_STOP_SETUP));
31431 -
31432 -       /*
31433 -        * Set Data High:       Do it by setting the Data Line to Input.
31434 -        *                      Because of a pull up resistor the Data Line
31435 -        *                      floods to high.
31436 -        */
31437 -       I2C_DATA_IN(IoC);
31438 -
31439 -       /*
31440 -        *      When I2C activity is stopped
31441 -        *       o      DATA should be set to input and
31442 -        *       o      CLOCK should be set to high!
31443 -        */
31444 -       SkDgWaitTime(IoC, NS2BCLK(T_BUS_IDLE));
31445 -}      /* SkI2cStop */
31446 -
31447 -
31448 -/*
31449 - * Receive just one bit via the I2C bus.
31450 - *
31451 - * Note:       Clock must be set to LOW before calling this function.
31452 - *
31453 - * Returns The received bit.
31454 - */
31455 -int SkI2cRcvBit(
31456 -SK_IOC IoC)    /* I/O Context */
31457 -{
31458 -       int     Bit;
31459 -       SK_U8   I2cSwCtrl;
31460 -
31461 -       /* Init data as input line */
31462 -       I2C_DATA_IN(IoC);
31463 -
31464 -       SkDgWaitTime(IoC, NS2BCLK(T_CLK_2_DATA_OUT));
31465 -
31466 -       I2C_CLK_HIGH(IoC);
31467 -
31468 -       SkDgWaitTime(IoC, NS2BCLK(T_CLK_HIGH));
31469 -
31470 -       SK_I2C_GET_SW(IoC, &I2cSwCtrl);
31471 -
31472 -       Bit = (I2cSwCtrl & I2C_DATA) ? 1 : 0;
31473 -
31474 -       I2C_CLK_LOW(IoC);
31475 -       SkDgWaitTime(IoC, NS2BCLK(T_CLK_LOW-T_CLK_2_DATA_OUT));
31476 -
31477 -       return(Bit);
31478 -}      /* SkI2cRcvBit */
31479 -
31480 -
31481 -/*
31482 - * Receive an ACK.
31483 - *
31484 - * returns     0 If acknowledged
31485 - *             1 in case of an error
31486 - */
31487 -int SkI2cRcvAck(
31488 -SK_IOC IoC)    /* I/O Context */
31489 -{
31490 -       /*
31491 -        * Received bit must be zero.
31492 -        */
31493 -       return(SkI2cRcvBit(IoC) != 0);
31494 -}      /* SkI2cRcvAck */
31495 -
31496 -
31497 -/*
31498 - * Send an NACK.
31499 - */
31500 -void SkI2cSndNAck(
31501 -SK_IOC IoC)    /* I/O Context */
31502 -{
31503 -       /*
31504 -        * Received bit must be zero.
31505 -        */
31506 -       SkI2cSndBit(IoC, 1);
31507 -}      /* SkI2cSndNAck */
31508 -
31509 -
31510 -/*
31511 - * Send an ACK.
31512 - */
31513 -void SkI2cSndAck(
31514 -SK_IOC IoC)    /* I/O Context */
31515 -{
31516 -       /*
31517 -        * Received bit must be zero.
31518 -        */
31519 -       SkI2cSndBit(IoC, 0);
31520 -}      /* SkI2cSndAck */
31521 -
31522 -
31523 -/*
31524 - * Send one byte to the I2C device and wait for ACK.
31525 - *
31526 - * Return acknowleged status.
31527 - */
31528 -int SkI2cSndByte(
31529 -SK_IOC IoC,    /* I/O Context */
31530 -int            Byte)   /* byte to send */
31531 -{
31532 -       int     i;
31533 -
31534 -       for (i = 0; i < 8; i++) {
31535 -               if (Byte & (1<<(7-i))) {
31536 -                       SkI2cSndBit(IoC, 1);
31537 -               }
31538 -               else {
31539 -                       SkI2cSndBit(IoC, 0);
31540 -               }
31541 -       }
31542 -
31543 -       return(SkI2cRcvAck(IoC));
31544 -}      /* SkI2cSndByte */
31545 -
31546 -
31547 -/*
31548 - * Receive one byte and ack it.
31549 - *
31550 - * Return byte.
31551 - */
31552 -int SkI2cRcvByte(
31553 -SK_IOC IoC,    /* I/O Context */
31554 -int            Last)   /* Last Byte Flag */
31555 -{
31556 -       int     i;
31557 -       int     Byte = 0;
31558 -
31559 -       for (i = 0; i < 8; i++) {
31560 -               Byte <<= 1;
31561 -               Byte |= SkI2cRcvBit(IoC);
31562 -       }
31563 -
31564 -       if (Last) {
31565 -               SkI2cSndNAck(IoC);
31566 -       }
31567 -       else {
31568 -               SkI2cSndAck(IoC);
31569 -       }
31570 -
31571 -       return(Byte);
31572 -}      /* SkI2cRcvByte */
31573 -
31574 -
31575 -/*
31576 - * Start dialog and send device address
31577 - *
31578 - * Return 0 if acknowleged, 1 in case of an error
31579 - */
31580 -int    SkI2cSndDev(
31581 -SK_IOC IoC,    /* I/O Context */
31582 -int            Addr,   /* Device Address */
31583 -int            Rw)             /* Read / Write Flag */
31584 -{
31585 -       SkI2cStart(IoC);
31586 -       Rw = ~Rw;
31587 -       Rw &= I2C_WRITE;
31588 -       return(SkI2cSndByte(IoC, (Addr<<1) | Rw));
31589 -}      /* SkI2cSndDev */
31590 -
31591 -#endif /* SK_DIAG */
31592 -
31593 -/*----------------- I2C CTRL Register Functions ----------*/
31594 -
31595 -/*
31596 - * waits for a completion of an I2C transfer
31597 - *
31598 - * returns     0:      success, transfer completes
31599 - *                     1:      error,   transfer does not complete, I2C transfer
31600 - *                                              killed, wait loop terminated.
31601 - */
31602 -static int     SkI2cWait(
31603 -SK_AC  *pAC,   /* Adapter Context */
31604 -SK_IOC IoC,    /* I/O Context */
31605 -int            Event)  /* complete event to wait for (I2C_READ or I2C_WRITE) */
31606 -{
31607 -       SK_U64  StartTime;
31608 -       SK_U64  CurrentTime;
31609 -       SK_U32  I2cCtrl;
31610 -
31611 -       StartTime = SkOsGetTime(pAC);
31612 -
31613 -       do {
31614 -               CurrentTime = SkOsGetTime(pAC);
31615 -
31616 -               if (CurrentTime - StartTime > SK_TICKS_PER_SEC / 8) {
31617 -
31618 -                       SK_I2C_STOP(IoC);
31619 -#ifndef SK_DIAG
31620 -                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E002, SKERR_I2C_E002MSG);
31621 -#endif /* !SK_DIAG */
31622 -                       return(1);
31623 -               }
31624 -
31625 -               SK_I2C_GET_CTL(IoC, &I2cCtrl);
31626 -
31627 -#ifdef xYUKON_DBG
31628 -               printf("StartTime=%lu, CurrentTime=%lu\n",
31629 -                       StartTime, CurrentTime);
31630 -               if (kbhit()) {
31631 -                       return(1);
31632 -               }
31633 -#endif /* YUKON_DBG */
31634 -
31635 -       } while ((I2cCtrl & I2C_FLAG) == (SK_U32)Event << 31);
31636 -
31637 -       return(0);
31638 -}      /* SkI2cWait */
31639 -
31640 -
31641 -/*
31642 - * waits for a completion of an I2C transfer
31643 - *
31644 - * Returns
31645 - *     Nothing
31646 - */
31647 -void SkI2cWaitIrq(
31648 -SK_AC  *pAC,   /* Adapter Context */
31649 -SK_IOC IoC)    /* I/O Context */
31650 -{
31651 -       SK_SENSOR       *pSen;
31652 -       SK_U64          StartTime;
31653 -       SK_U32          IrqSrc;
31654 -
31655 -       pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
31656 -
31657 -       if (pSen->SenState == SK_SEN_IDLE) {
31658 -               return;
31659 -       }
31660 -
31661 -       StartTime = SkOsGetTime(pAC);
31662 -
31663 -       do {
31664 -               if (SkOsGetTime(pAC) - StartTime > SK_TICKS_PER_SEC / 8) {
31665 -
31666 -                       SK_I2C_STOP(IoC);
31667 -#ifndef SK_DIAG
31668 -                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E016, SKERR_I2C_E016MSG);
31669 -#endif /* !SK_DIAG */
31670 -                       return;
31671 -               }
31672 -
31673 -               SK_IN32(IoC, B0_ISRC, &IrqSrc);
31674 -
31675 -       } while ((IrqSrc & IS_I2C_READY) == 0);
31676 -
31677 -       pSen->SenState = SK_SEN_IDLE;
31678 -       return;
31679 -}      /* SkI2cWaitIrq */
31680 -
31681 -/*
31682 - * writes a single byte or 4 bytes into the I2C device
31683 - *
31684 - * returns     0:      success
31685 - *                     1:      error
31686 - */
31687 -static int SkI2cWrite(
31688 -SK_AC  *pAC,           /* Adapter Context */
31689 -SK_IOC IoC,            /* I/O Context */
31690 -SK_U32 I2cData,        /* I2C Data to write */
31691 -int            I2cDev,         /* I2C Device Address */
31692 -int            I2cDevSize, /* I2C Device Size (e.g. I2C_025K_DEV or I2C_2K_DEV) */
31693 -int            I2cReg,         /* I2C Device Register Address */
31694 -int            I2cBurst)       /* I2C Burst Flag */
31695 -{
31696 -       SK_OUT32(IoC, B2_I2C_DATA, I2cData);
31697 -
31698 -       SK_I2C_CTL(IoC, I2C_WRITE, I2cDev, I2cDevSize, I2cReg, I2cBurst);
31699 -
31700 -       return(SkI2cWait(pAC, IoC, I2C_WRITE));
31701 -}      /* SkI2cWrite*/
31702 -
31703 -
31704 -#ifdef SK_DIAG
31705 -/*
31706 - * reads a single byte or 4 bytes from the I2C device
31707 - *
31708 - * returns     the word read
31709 - */
31710 -SK_U32 SkI2cRead(
31711 -SK_AC  *pAC,           /* Adapter Context */
31712 -SK_IOC IoC,            /* I/O Context */
31713 -int            I2cDev,         /* I2C Device Address */
31714 -int            I2cDevSize, /* I2C Device Size (e.g. I2C_025K_DEV or I2C_2K_DEV) */
31715 -int            I2cReg,         /* I2C Device Register Address */
31716 -int            I2cBurst)       /* I2C Burst Flag */
31717 -{
31718 -       SK_U32  Data;
31719 -
31720 -       SK_OUT32(IoC, B2_I2C_DATA, 0);
31721 -       SK_I2C_CTL(IoC, I2C_READ, I2cDev, I2cDevSize, I2cReg, I2cBurst);
31722 -
31723 -       if (SkI2cWait(pAC, IoC, I2C_READ) != 0) {
31724 -               w_print("%s\n", SKERR_I2C_E002MSG);
31725 -       }
31726 -
31727 -       SK_IN32(IoC, B2_I2C_DATA, &Data);
31728 -
31729 -       return(Data);
31730 -}      /* SkI2cRead */
31731 -#endif /* SK_DIAG */
31732 -
31733 -
31734 -/*
31735 - * read a sensor's value
31736 - *
31737 - * This function reads a sensor's value from the I2C sensor chip. The sensor
31738 - * is defined by its index into the sensors database in the struct pAC points
31739 - * to.
31740 - * Returns
31741 - *             1 if the read is completed
31742 - *             0 if the read must be continued (I2C Bus still allocated)
31743 - */
31744 -static int     SkI2cReadSensor(
31745 -SK_AC          *pAC,   /* Adapter Context */
31746 -SK_IOC         IoC,    /* I/O Context */
31747 -SK_SENSOR      *pSen)  /* Sensor to be read */
31748 -{
31749 -    if (pSen->SenRead != NULL) {
31750 -        return((*pSen->SenRead)(pAC, IoC, pSen));
31751 -    }
31752 -       else {
31753 -        return(0); /* no success */
31754 -       }
31755 -}      /* SkI2cReadSensor */
31756 -
31757 -/*
31758 - * Do the Init state 0 initialization
31759 - */
31760 -static int SkI2cInit0(
31761 -SK_AC  *pAC)   /* Adapter Context */
31762 -{
31763 -       int     i;
31764 -
31765 -       /* Begin with first sensor */
31766 -       pAC->I2c.CurrSens = 0;
31767 -
31768 -       /* Begin with timeout control for state machine */
31769 -       pAC->I2c.TimerMode = SK_TIMER_WATCH_SM;
31770 -
31771 -       /* Set sensor number to zero */
31772 -       pAC->I2c.MaxSens = 0;
31773 -
31774 -#ifndef SK_DIAG
31775 -       /* Initialize Number of Dummy Reads */
31776 -       pAC->I2c.DummyReads = SK_MAX_SENSORS;
31777 -#endif
31778 -
31779 -       for (i = 0; i < SK_MAX_SENSORS; i++) {
31780 -               pAC->I2c.SenTable[i].SenDesc = "unknown";
31781 -               pAC->I2c.SenTable[i].SenType = SK_SEN_UNKNOWN;
31782 -               pAC->I2c.SenTable[i].SenThreErrHigh = 0;
31783 -               pAC->I2c.SenTable[i].SenThreErrLow = 0;
31784 -               pAC->I2c.SenTable[i].SenThreWarnHigh = 0;
31785 -               pAC->I2c.SenTable[i].SenThreWarnLow = 0;
31786 -               pAC->I2c.SenTable[i].SenReg = LM80_FAN2_IN;
31787 -               pAC->I2c.SenTable[i].SenInit = SK_SEN_DYN_INIT_NONE;
31788 -               pAC->I2c.SenTable[i].SenValue = 0;
31789 -               pAC->I2c.SenTable[i].SenErrFlag = SK_SEN_ERR_NOT_PRESENT;
31790 -               pAC->I2c.SenTable[i].SenErrCts = 0;
31791 -               pAC->I2c.SenTable[i].SenBegErrTS = 0;
31792 -               pAC->I2c.SenTable[i].SenState = SK_SEN_IDLE;
31793 -               pAC->I2c.SenTable[i].SenRead = NULL;
31794 -               pAC->I2c.SenTable[i].SenDev = 0;
31795 -       }
31796 -
31797 -       /* Now we are "INIT data"ed */
31798 -       pAC->I2c.InitLevel = SK_INIT_DATA;
31799 -       return(0);
31800 -}      /* SkI2cInit0*/
31801 -
31802 -
31803 -/*
31804 - * Do the init state 1 initialization
31805 - *
31806 - * initialize the following register of the LM80:
31807 - * Configuration register:
31808 - * - START, noINT, activeLOW, noINT#Clear, noRESET, noCI, noGPO#, noINIT
31809 - *
31810 - * Interrupt Mask Register 1:
31811 - * - all interrupts are Disabled (0xff)
31812 - *
31813 - * Interrupt Mask Register 2:
31814 - * - all interrupts are Disabled (0xff) Interrupt modi doesn't matter.
31815 - *
31816 - * Fan Divisor/RST_OUT register:
31817 - * - Divisors set to 1 (bits 00), all others 0s.
31818 - *
31819 - * OS# Configuration/Temperature resolution Register:
31820 - * - all 0s
31821 - *
31822 - */
31823 -static int SkI2cInit1(
31824 -SK_AC  *pAC,   /* Adapter Context */
31825 -SK_IOC IoC)    /* I/O Context */
31826 -{
31827 -    int i;
31828 -    SK_U8 I2cSwCtrl;
31829 -       SK_GEPORT *pPrt;        /* GIni Port struct pointer */
31830 -
31831 -       if (pAC->I2c.InitLevel != SK_INIT_DATA) {
31832 -               /* ReInit not needed in I2C module */
31833 -               return(0);
31834 -       }
31835 -
31836 -    /* Set the Direction of I2C-Data Pin to IN */
31837 -    SK_I2C_CLR_BIT(IoC, I2C_DATA_DIR | I2C_DATA);
31838 -    /* Check for 32-Bit Yukon with Low at I2C-Data Pin */
31839 -       SK_I2C_GET_SW(IoC, &I2cSwCtrl);
31840 -
31841 -       if ((I2cSwCtrl & I2C_DATA) == 0) {
31842 -               /* this is a 32-Bit board */
31843 -               pAC->GIni.GIYukon32Bit = SK_TRUE;
31844 -        return(0);
31845 -    }
31846 -
31847 -       /* Check for 64 Bit Yukon without sensors */
31848 -       if (SkI2cWrite(pAC, IoC, 0, LM80_ADDR, I2C_025K_DEV, LM80_CFG, 0) != 0) {
31849 -        return(0);
31850 -    }
31851 -
31852 -       (void)SkI2cWrite(pAC, IoC, 0xffUL, LM80_ADDR, I2C_025K_DEV, LM80_IMSK_1, 0);
31853 -
31854 -       (void)SkI2cWrite(pAC, IoC, 0xffUL, LM80_ADDR, I2C_025K_DEV, LM80_IMSK_2, 0);
31855 -
31856 -       (void)SkI2cWrite(pAC, IoC, 0, LM80_ADDR, I2C_025K_DEV, LM80_FAN_CTRL, 0);
31857 -
31858 -       (void)SkI2cWrite(pAC, IoC, 0, LM80_ADDR, I2C_025K_DEV, LM80_TEMP_CTRL, 0);
31859 -
31860 -       (void)SkI2cWrite(pAC, IoC, (SK_U32)LM80_CFG_START, LM80_ADDR, I2C_025K_DEV,
31861 -               LM80_CFG, 0);
31862 -
31863 -       /*
31864 -        * MaxSens has to be updated here, because PhyType is not
31865 -        * set when performing Init Level 0
31866 -        */
31867 -    pAC->I2c.MaxSens = 5;
31868 -
31869 -       pPrt = &pAC->GIni.GP[0];
31870 -
31871 -       if (pAC->GIni.GIGenesis) {
31872 -               if (pPrt->PhyType == SK_PHY_BCOM) {
31873 -                       if (pAC->GIni.GIMacsFound == 1) {
31874 -                               pAC->I2c.MaxSens += 1;
31875 -                       }
31876 -                       else {
31877 -                               pAC->I2c.MaxSens += 3;
31878 -                       }
31879 -               }
31880 -       }
31881 -       else {
31882 -               pAC->I2c.MaxSens += 3;
31883 -       }
31884 -
31885 -       for (i = 0; i < pAC->I2c.MaxSens; i++) {
31886 -               switch (i) {
31887 -               case 0:
31888 -                       pAC->I2c.SenTable[i].SenDesc = "Temperature";
31889 -                       pAC->I2c.SenTable[i].SenType = SK_SEN_TEMP;
31890 -                       pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_TEMP_HIGH_ERR;
31891 -                       pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_TEMP_HIGH_WARN;
31892 -                       pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_TEMP_LOW_WARN;
31893 -                       pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_TEMP_LOW_ERR;
31894 -                       pAC->I2c.SenTable[i].SenReg = LM80_TEMP_IN;
31895 -                       break;
31896 -               case 1:
31897 -                       pAC->I2c.SenTable[i].SenDesc = "Voltage PCI";
31898 -                       pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
31899 -                       pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PCI_5V_HIGH_ERR;
31900 -                       pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PCI_5V_HIGH_WARN;
31901 -                       pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PCI_5V_LOW_WARN;
31902 -                       pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PCI_5V_LOW_ERR;
31903 -                       pAC->I2c.SenTable[i].SenReg = LM80_VT0_IN;
31904 -                       break;
31905 -               case 2:
31906 -                       pAC->I2c.SenTable[i].SenDesc = "Voltage PCI-IO";
31907 -                       pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
31908 -                       pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PCI_IO_5V_HIGH_ERR;
31909 -                       pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PCI_IO_5V_HIGH_WARN;
31910 -                       pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PCI_IO_3V3_LOW_WARN;
31911 -                       pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PCI_IO_3V3_LOW_ERR;
31912 -                       pAC->I2c.SenTable[i].SenReg = LM80_VT1_IN;
31913 -                       pAC->I2c.SenTable[i].SenInit = SK_SEN_DYN_INIT_PCI_IO;
31914 -                       break;
31915 -               case 3:
31916 -                       pAC->I2c.SenTable[i].SenDesc = "Voltage ASIC";
31917 -                       pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
31918 -                       pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_VDD_HIGH_ERR;
31919 -                       pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_VDD_HIGH_WARN;
31920 -                       pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_VDD_LOW_WARN;
31921 -                       pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_VDD_LOW_ERR;
31922 -                       pAC->I2c.SenTable[i].SenReg = LM80_VT2_IN;
31923 -                       break;
31924 -               case 4:
31925 -                       if (pAC->GIni.GIGenesis) {
31926 -                               if (pPrt->PhyType == SK_PHY_BCOM) {
31927 -                                       pAC->I2c.SenTable[i].SenDesc = "Voltage PHY A PLL";
31928 -                                       pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR;
31929 -                                       pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN;
31930 -                                       pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN;
31931 -                                       pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR;
31932 -                               }
31933 -                               else {
31934 -                                       pAC->I2c.SenTable[i].SenDesc = "Voltage PMA";
31935 -                                       pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR;
31936 -                                       pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN;
31937 -                                       pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN;
31938 -                                       pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR;
31939 -                               }
31940 -                       }
31941 -                       else {
31942 -                               pAC->I2c.SenTable[i].SenDesc = "Voltage VAUX";
31943 -                               pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_VAUX_3V3_HIGH_ERR;
31944 -                               pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_VAUX_3V3_HIGH_WARN;
31945 -                               if (pAC->GIni.GIVauxAvail) {
31946 -                                       pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_VAUX_3V3_LOW_WARN;
31947 -                                       pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_VAUX_3V3_LOW_ERR;
31948 -                               }
31949 -                               else {
31950 -                                       pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_VAUX_0V_WARN_ERR;
31951 -                                       pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_VAUX_0V_WARN_ERR;
31952 -                               }
31953 -                       }
31954 -                       pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
31955 -                       pAC->I2c.SenTable[i].SenReg = LM80_VT3_IN;
31956 -                       break;
31957 -               case 5:
31958 -                       if (pAC->GIni.GIGenesis) {
31959 -                               pAC->I2c.SenTable[i].SenDesc = "Voltage PHY 2V5";
31960 -                               pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PHY_2V5_HIGH_ERR;
31961 -                               pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PHY_2V5_HIGH_WARN;
31962 -                               pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PHY_2V5_LOW_WARN;
31963 -                               pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PHY_2V5_LOW_ERR;
31964 -                       }
31965 -                       else {
31966 -                               pAC->I2c.SenTable[i].SenDesc = "Voltage Core 1V5";
31967 -                               pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_CORE_1V5_HIGH_ERR;
31968 -                               pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_CORE_1V5_HIGH_WARN;
31969 -                               pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_CORE_1V5_LOW_WARN;
31970 -                               pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_CORE_1V5_LOW_ERR;
31971 -                       }
31972 -                       pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
31973 -                       pAC->I2c.SenTable[i].SenReg = LM80_VT4_IN;
31974 -                       break;
31975 -               case 6:
31976 -                       if (pAC->GIni.GIGenesis) {
31977 -                               pAC->I2c.SenTable[i].SenDesc = "Voltage PHY B PLL";
31978 -                       }
31979 -                       else {
31980 -                               pAC->I2c.SenTable[i].SenDesc = "Voltage PHY 3V3";
31981 -                       }
31982 -                       pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
31983 -                       pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR;
31984 -                       pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN;
31985 -                       pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN;
31986 -                       pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR;
31987 -                       pAC->I2c.SenTable[i].SenReg = LM80_VT5_IN;
31988 -                       break;
31989 -               case 7:
31990 -                       if (pAC->GIni.GIGenesis) {
31991 -                               pAC->I2c.SenTable[i].SenDesc = "Speed Fan";
31992 -                               pAC->I2c.SenTable[i].SenType = SK_SEN_FAN;
31993 -                               pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_FAN_HIGH_ERR;
31994 -                               pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_FAN_HIGH_WARN;
31995 -                               pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_FAN_LOW_WARN;
31996 -                               pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_FAN_LOW_ERR;
31997 -                               pAC->I2c.SenTable[i].SenReg = LM80_FAN2_IN;
31998 -                       }
31999 -                       else {
32000 -                               pAC->I2c.SenTable[i].SenDesc = "Voltage PHY 2V5";
32001 -                               pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
32002 -                               pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PHY_2V5_HIGH_ERR;
32003 -                               pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PHY_2V5_HIGH_WARN;
32004 -                               pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PHY_2V5_LOW_WARN;
32005 -                               pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PHY_2V5_LOW_ERR;
32006 -                               pAC->I2c.SenTable[i].SenReg = LM80_VT6_IN;
32007 -                       }
32008 -                       break;
32009 -               default:
32010 -                       SK_ERR_LOG(pAC, SK_ERRCL_INIT | SK_ERRCL_SW,
32011 -                               SKERR_I2C_E001, SKERR_I2C_E001MSG);
32012 -                       break;
32013 -               }
32014 -
32015 -               pAC->I2c.SenTable[i].SenValue = 0;
32016 -               pAC->I2c.SenTable[i].SenErrFlag = SK_SEN_ERR_OK;
32017 -               pAC->I2c.SenTable[i].SenErrCts = 0;
32018 -               pAC->I2c.SenTable[i].SenBegErrTS = 0;
32019 -               pAC->I2c.SenTable[i].SenState = SK_SEN_IDLE;
32020 -               pAC->I2c.SenTable[i].SenRead = SkLm80ReadSensor;
32021 -               pAC->I2c.SenTable[i].SenDev = LM80_ADDR;
32022 -       }
32023 -
32024 -#ifndef SK_DIAG
32025 -       pAC->I2c.DummyReads = pAC->I2c.MaxSens;
32026 -#endif /* !SK_DIAG */
32027 -
32028 -       /* Clear I2C IRQ */
32029 -       SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
32030 -
32031 -       /* Now we are I/O initialized */
32032 -       pAC->I2c.InitLevel = SK_INIT_IO;
32033 -       return(0);
32034 -}      /* SkI2cInit1 */
32035 -
32036 -
32037 -/*
32038 - * Init level 2: Start first sensor read.
32039 - */
32040 -static int SkI2cInit2(
32041 -SK_AC  *pAC,   /* Adapter Context */
32042 -SK_IOC IoC)    /* I/O Context */
32043 -{
32044 -       int             ReadComplete;
32045 -       SK_SENSOR       *pSen;
32046 -
32047 -       if (pAC->I2c.InitLevel != SK_INIT_IO) {
32048 -               /* ReInit not needed in I2C module */
32049 -               /* Init0 and Init2 not permitted */
32050 -               return(0);
32051 -       }
32052 -
32053 -       pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
32054 -       ReadComplete = SkI2cReadSensor(pAC, IoC, pSen);
32055 -
32056 -       if (ReadComplete) {
32057 -               SK_ERR_LOG(pAC, SK_ERRCL_INIT, SKERR_I2C_E008, SKERR_I2C_E008MSG);
32058 -       }
32059 -
32060 -       /* Now we are correctly initialized */
32061 -       pAC->I2c.InitLevel = SK_INIT_RUN;
32062 -
32063 -       return(0);
32064 -}      /* SkI2cInit2*/
32065 -
32066 -
32067 -/*
32068 - * Initialize I2C devices
32069 - *
32070 - * Get the first voltage value and discard it.
32071 - * Go into temperature read mode. A default pointer is not set.
32072 - *
32073 - * The things to be done depend on the init level in the parameter list:
32074 - * Level 0:
32075 - *     Initialize only the data structures. Do NOT access hardware.
32076 - * Level 1:
32077 - *     Initialize hardware through SK_IN / SK_OUT commands. Do NOT use interrupts.
32078 - * Level 2:
32079 - *     Everything is possible. Interrupts may be used from now on.
32080 - *
32081 - * return:
32082 - *     0 = success
32083 - *     other = error.
32084 - */
32085 -int    SkI2cInit(
32086 -SK_AC  *pAC,   /* Adapter Context */
32087 -SK_IOC IoC,    /* I/O Context needed in levels 1 and 2 */
32088 -int            Level)  /* Init Level */
32089 -{
32090 -
32091 -       switch (Level) {
32092 -       case SK_INIT_DATA:
32093 -               return(SkI2cInit0(pAC));
32094 -       case SK_INIT_IO:
32095 -               return(SkI2cInit1(pAC, IoC));
32096 -       case SK_INIT_RUN:
32097 -               return(SkI2cInit2(pAC, IoC));
32098 -       default:
32099 -               break;
32100 -       }
32101 -
32102 -       return(0);
32103 -}      /* SkI2cInit */
32104 -
32105 -
32106 -#ifndef SK_DIAG
32107 -
32108 -/*
32109 - * Interrupt service function for the I2C Interface
32110 - *
32111 - * Clears the Interrupt source
32112 - *
32113 - * Reads the register and check it for sending a trap.
32114 - *
32115 - * Starts the timer if necessary.
32116 - */
32117 -void SkI2cIsr(
32118 -SK_AC  *pAC,   /* Adapter Context */
32119 -SK_IOC IoC)    /* I/O Context */
32120 -{
32121 -       SK_EVPARA       Para;
32122 -
32123 -       /* Clear I2C IRQ */
32124 -       SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
32125 -
32126 -       Para.Para64 = 0;
32127 -       SkEventQueue(pAC, SKGE_I2C, SK_I2CEV_IRQ, Para);
32128 -}      /* SkI2cIsr */
32129 -
32130 -
32131 -/*
32132 - * Check this sensors Value against the threshold and send events.
32133 - */
32134 -static void SkI2cCheckSensor(
32135 -SK_AC          *pAC,   /* Adapter Context */
32136 -SK_SENSOR      *pSen)
32137 -{
32138 -       SK_EVPARA       ParaLocal;
32139 -       SK_BOOL         TooHigh;        /* Is sensor too high? */
32140 -       SK_BOOL         TooLow;         /* Is sensor too low? */
32141 -       SK_U64          CurrTime;       /* Current Time */
32142 -       SK_BOOL         DoTrapSend;     /* We need to send a trap */
32143 -       SK_BOOL         DoErrLog;       /* We need to log the error */
32144 -       SK_BOOL         IsError;        /* We need to log the error */
32145 -
32146 -       /* Check Dummy Reads first */
32147 -       if (pAC->I2c.DummyReads > 0) {
32148 -               pAC->I2c.DummyReads--;
32149 -               return;
32150 -       }
32151 -
32152 -       /* Get the current time */
32153 -       CurrTime = SkOsGetTime(pAC);
32154 -
32155 -       /* Set para to the most useful setting: The current sensor. */
32156 -       ParaLocal.Para64 = (SK_U64)pAC->I2c.CurrSens;
32157 -
32158 -       /* Check the Value against the thresholds. First: Error Thresholds */
32159 -       TooHigh = (pSen->SenValue > pSen->SenThreErrHigh);
32160 -       TooLow = (pSen->SenValue < pSen->SenThreErrLow);
32161 -
32162 -       IsError = SK_FALSE;
32163 -       if (TooHigh || TooLow) {
32164 -               /* Error condition is satisfied */
32165 -               DoTrapSend = SK_TRUE;
32166 -               DoErrLog = SK_TRUE;
32167 -
32168 -               /* Now error condition is satisfied */
32169 -               IsError = SK_TRUE;
32170 -
32171 -               if (pSen->SenErrFlag == SK_SEN_ERR_ERR) {
32172 -                       /* This state is the former one */
32173 -
32174 -                       /* So check first whether we have to send a trap */
32175 -                       if (pSen->SenLastErrTrapTS + SK_SEN_ERR_TR_HOLD >
32176 -                           CurrTime) {
32177 -                               /*
32178 -                                * Do NOT send the Trap. The hold back time
32179 -                                * has to run out first.
32180 -                                */
32181 -                               DoTrapSend = SK_FALSE;
32182 -                       }
32183 -
32184 -                       /* Check now whether we have to log an Error */
32185 -                       if (pSen->SenLastErrLogTS + SK_SEN_ERR_LOG_HOLD >
32186 -                           CurrTime) {
32187 -                               /*
32188 -                                * Do NOT log the error. The hold back time
32189 -                                * has to run out first.
32190 -                                */
32191 -                               DoErrLog = SK_FALSE;
32192 -                       }
32193 -               }
32194 -               else {
32195 -                       /* We came from a different state -> Set Begin Time Stamp */
32196 -                       pSen->SenBegErrTS = CurrTime;
32197 -                       pSen->SenErrFlag = SK_SEN_ERR_ERR;
32198 -               }
32199 -
32200 -               if (DoTrapSend) {
32201 -                       /* Set current Time */
32202 -                       pSen->SenLastErrTrapTS = CurrTime;
32203 -                       pSen->SenErrCts++;
32204 -
32205 -                       /* Queue PNMI Event */
32206 -                       SkEventQueue(pAC, SKGE_PNMI, (TooHigh ?
32207 -                               SK_PNMI_EVT_SEN_ERR_UPP :
32208 -                               SK_PNMI_EVT_SEN_ERR_LOW),
32209 -                               ParaLocal);
32210 -               }
32211 -
32212 -               if (DoErrLog) {
32213 -                       /* Set current Time */
32214 -                       pSen->SenLastErrLogTS = CurrTime;
32215 -
32216 -                       if (pSen->SenType == SK_SEN_TEMP) {
32217 -                               SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E011, SKERR_I2C_E011MSG);
32218 -                       }
32219 -                       else if (pSen->SenType == SK_SEN_VOLT) {
32220 -                               SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E012, SKERR_I2C_E012MSG);
32221 -                       }
32222 -                       else {
32223 -                               SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E015, SKERR_I2C_E015MSG);
32224 -                       }
32225 -               }
32226 -       }
32227 -
32228 -       /* Check the Value against the thresholds */
32229 -       /* 2nd: Warning thresholds */
32230 -       TooHigh = (pSen->SenValue > pSen->SenThreWarnHigh);
32231 -       TooLow = (pSen->SenValue < pSen->SenThreWarnLow);
32232 -
32233 -       if (!IsError && (TooHigh || TooLow)) {
32234 -               /* Error condition is satisfied */
32235 -               DoTrapSend = SK_TRUE;
32236 -               DoErrLog = SK_TRUE;
32237 -
32238 -               if (pSen->SenErrFlag == SK_SEN_ERR_WARN) {
32239 -                       /* This state is the former one */
32240 -
32241 -                       /* So check first whether we have to send a trap */
32242 -                       if (pSen->SenLastWarnTrapTS + SK_SEN_WARN_TR_HOLD > CurrTime) {
32243 -                               /*
32244 -                                * Do NOT send the Trap. The hold back time
32245 -                                * has to run out first.
32246 -                                */
32247 -                               DoTrapSend = SK_FALSE;
32248 -                       }
32249 -
32250 -                       /* Check now whether we have to log an Error */
32251 -                       if (pSen->SenLastWarnLogTS + SK_SEN_WARN_LOG_HOLD > CurrTime) {
32252 -                               /*
32253 -                                * Do NOT log the error. The hold back time
32254 -                                * has to run out first.
32255 -                                */
32256 -                               DoErrLog = SK_FALSE;
32257 -                       }
32258 -               }
32259 -               else {
32260 -                       /* We came from a different state -> Set Begin Time Stamp */
32261 -                       pSen->SenBegWarnTS = CurrTime;
32262 -                       pSen->SenErrFlag = SK_SEN_ERR_WARN;
32263 -               }
32264 -
32265 -               if (DoTrapSend) {
32266 -                       /* Set current Time */
32267 -                       pSen->SenLastWarnTrapTS = CurrTime;
32268 -                       pSen->SenWarnCts++;
32269 -
32270 -                       /* Queue PNMI Event */
32271 -                       SkEventQueue(pAC, SKGE_PNMI, (TooHigh ?
32272 -                               SK_PNMI_EVT_SEN_WAR_UPP :
32273 -                               SK_PNMI_EVT_SEN_WAR_LOW),
32274 -                               ParaLocal);
32275 -               }
32276 -
32277 -               if (DoErrLog) {
32278 -                       /* Set current Time */
32279 -                       pSen->SenLastWarnLogTS = CurrTime;
32280 -
32281 -                       if (pSen->SenType == SK_SEN_TEMP) {
32282 -                               SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E009, SKERR_I2C_E009MSG);
32283 -                       }
32284 -                       else if (pSen->SenType == SK_SEN_VOLT) {
32285 -                               SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E010, SKERR_I2C_E010MSG);
32286 -                       }
32287 -                       else {
32288 -                               SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E014, SKERR_I2C_E014MSG);
32289 -                       }
32290 -               }
32291 -       }
32292 -
32293 -       /* Check for NO error at all */
32294 -       if (!IsError && !TooHigh && !TooLow) {
32295 -               /* Set o.k. Status if no error and no warning condition */
32296 -               pSen->SenErrFlag = SK_SEN_ERR_OK;
32297 -       }
32298 -
32299 -       /* End of check against the thresholds */
32300 -
32301 -       /* Bug fix AF: 16.Aug.2001: Correct the init base
32302 -        * of LM80 sensor.
32303 -        */
32304 -       if (pSen->SenInit == SK_SEN_DYN_INIT_PCI_IO) {
32305 -
32306 -        pSen->SenInit = SK_SEN_DYN_INIT_NONE;
32307 -
32308 -               if (pSen->SenValue > SK_SEN_PCI_IO_RANGE_LIMITER) {
32309 -                       /* 5V PCI-IO Voltage */
32310 -                       pSen->SenThreWarnLow = SK_SEN_PCI_IO_5V_LOW_WARN;
32311 -                       pSen->SenThreErrLow = SK_SEN_PCI_IO_5V_LOW_ERR;
32312 -               }
32313 -               else {
32314 -                       /* 3.3V PCI-IO Voltage */
32315 -                       pSen->SenThreWarnHigh = SK_SEN_PCI_IO_3V3_HIGH_WARN;
32316 -                       pSen->SenThreErrHigh = SK_SEN_PCI_IO_3V3_HIGH_ERR;
32317 -               }
32318 -       }
32319 -
32320 -#ifdef TEST_ONLY
32321 -    /* Dynamic thresholds also for VAUX of LM80 sensor */
32322 -       if (pSen->SenInit == SK_SEN_DYN_INIT_VAUX) {
32323 -
32324 -        pSen->SenInit = SK_SEN_DYN_INIT_NONE;
32325 -
32326 -               /* 3.3V VAUX Voltage */
32327 -               if (pSen->SenValue > SK_SEN_VAUX_RANGE_LIMITER) {
32328 -                       pSen->SenThreWarnLow = SK_SEN_VAUX_3V3_LOW_WARN;
32329 -                       pSen->SenThreErrLow = SK_SEN_VAUX_3V3_LOW_ERR;
32330 -               }
32331 -               /* 0V VAUX Voltage */
32332 -               else {
32333 -                       pSen->SenThreWarnHigh = SK_SEN_VAUX_0V_WARN_ERR;
32334 -                       pSen->SenThreErrHigh = SK_SEN_VAUX_0V_WARN_ERR;
32335 -               }
32336 -       }
32337 -
32338 -       /*
32339 -        * Check initialization state:
32340 -        * The VIO Thresholds need adaption
32341 -        */
32342 -       if (!pSen->SenInit && pSen->SenReg == LM80_VT1_IN &&
32343 -            pSen->SenValue > SK_SEN_WARNLOW2C &&
32344 -            pSen->SenValue < SK_SEN_WARNHIGH2) {
32345 -               pSen->SenThreErrLow = SK_SEN_ERRLOW2C;
32346 -               pSen->SenThreWarnLow = SK_SEN_WARNLOW2C;
32347 -               pSen->SenInit = SK_TRUE;
32348 -       }
32349 -
32350 -       if (!pSen->SenInit && pSen->SenReg == LM80_VT1_IN &&
32351 -            pSen->SenValue > SK_SEN_WARNLOW2 &&
32352 -            pSen->SenValue < SK_SEN_WARNHIGH2C) {
32353 -               pSen->SenThreErrHigh = SK_SEN_ERRHIGH2C;
32354 -               pSen->SenThreWarnHigh = SK_SEN_WARNHIGH2C;
32355 -               pSen->SenInit = SK_TRUE;
32356 -       }
32357 -#endif
32358 -
32359 -       if (pSen->SenInit != SK_SEN_DYN_INIT_NONE) {
32360 -               SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E013, SKERR_I2C_E013MSG);
32361 -       }
32362 -}      /* SkI2cCheckSensor */
32363 -
32364 -
32365 -/*
32366 - * The only Event to be served is the timeout event
32367 - *
32368 - */
32369 -int    SkI2cEvent(
32370 -SK_AC          *pAC,   /* Adapter Context */
32371 -SK_IOC         IoC,    /* I/O Context */
32372 -SK_U32         Event,  /* Module specific Event */
32373 -SK_EVPARA      Para)   /* Event specific Parameter */
32374 -{
32375 -       int                     ReadComplete;
32376 -       SK_SENSOR       *pSen;
32377 -       SK_U32          Time;
32378 -       SK_EVPARA       ParaLocal;
32379 -       int                     i;
32380 -
32381 -       /* New case: no sensors */
32382 -       if (pAC->I2c.MaxSens == 0) {
32383 -               return(0);
32384 -       }
32385 -
32386 -       switch (Event) {
32387 -       case SK_I2CEV_IRQ:
32388 -               pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
32389 -               ReadComplete = SkI2cReadSensor(pAC, IoC, pSen);
32390 -
32391 -               if (ReadComplete) {
32392 -                       /* Check sensor against defined thresholds */
32393 -                       SkI2cCheckSensor(pAC, pSen);
32394 -
32395 -                       /* Increment Current sensor and set appropriate Timeout */
32396 -                       pAC->I2c.CurrSens++;
32397 -                       if (pAC->I2c.CurrSens >= pAC->I2c.MaxSens) {
32398 -                               pAC->I2c.CurrSens = 0;
32399 -                               Time = SK_I2C_TIM_LONG;
32400 -                       }
32401 -                       else {
32402 -                               Time = SK_I2C_TIM_SHORT;
32403 -                       }
32404 -
32405 -                       /* Start Timer */
32406 -                       ParaLocal.Para64 = (SK_U64)0;
32407 -
32408 -                       pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING;
32409 -
32410 -                       SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time,
32411 -                               SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
32412 -               }
32413 -        else {
32414 -                       /* Start Timer */
32415 -                       ParaLocal.Para64 = (SK_U64)0;
32416 -
32417 -                       pAC->I2c.TimerMode = SK_TIMER_WATCH_SM;
32418 -
32419 -            SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, SK_I2C_TIM_WATCH,
32420 -                               SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
32421 -               }
32422 -               break;
32423 -       case SK_I2CEV_TIM:
32424 -               if (pAC->I2c.TimerMode == SK_TIMER_NEW_GAUGING) {
32425 -
32426 -                       ParaLocal.Para64 = (SK_U64)0;
32427 -                       SkTimerStop(pAC, IoC, &pAC->I2c.SenTimer);
32428 -
32429 -                       pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
32430 -                       ReadComplete = SkI2cReadSensor(pAC, IoC, pSen);
32431 -
32432 -                       if (ReadComplete) {
32433 -                               /* Check sensor against defined thresholds */
32434 -                               SkI2cCheckSensor(pAC, pSen);
32435 -
32436 -                               /* Increment Current sensor and set appropriate Timeout */
32437 -                               pAC->I2c.CurrSens++;
32438 -                               if (pAC->I2c.CurrSens == pAC->I2c.MaxSens) {
32439 -                                       pAC->I2c.CurrSens = 0;
32440 -                                       Time = SK_I2C_TIM_LONG;
32441 -                               }
32442 -                               else {
32443 -                                       Time = SK_I2C_TIM_SHORT;
32444 -                               }
32445 -
32446 -                               /* Start Timer */
32447 -                               ParaLocal.Para64 = (SK_U64)0;
32448 -
32449 -                               pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING;
32450 -
32451 -                               SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time,
32452 -                                       SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
32453 -                       }
32454 -               }
32455 -               else {
32456 -                       pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
32457 -                       pSen->SenErrFlag = SK_SEN_ERR_FAULTY;
32458 -                       SK_I2C_STOP(IoC);
32459 -
32460 -                       /* Increment Current sensor and set appropriate Timeout */
32461 -                       pAC->I2c.CurrSens++;
32462 -                       if (pAC->I2c.CurrSens == pAC->I2c.MaxSens) {
32463 -                               pAC->I2c.CurrSens = 0;
32464 -                               Time = SK_I2C_TIM_LONG;
32465 -                       }
32466 -                       else {
32467 -                               Time = SK_I2C_TIM_SHORT;
32468 -                       }
32469 -
32470 -                       /* Start Timer */
32471 -                       ParaLocal.Para64 = (SK_U64)0;
32472 -
32473 -                       pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING;
32474 -
32475 -                       SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time,
32476 -                               SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
32477 -               }
32478 -               break;
32479 -       case SK_I2CEV_CLEAR:
32480 -               for (i = 0; i < SK_MAX_SENSORS; i++) {
32481 -                       pAC->I2c.SenTable[i].SenErrFlag = SK_SEN_ERR_OK;
32482 -                       pAC->I2c.SenTable[i].SenErrCts = 0;
32483 -                       pAC->I2c.SenTable[i].SenWarnCts = 0;
32484 -                       pAC->I2c.SenTable[i].SenBegErrTS = 0;
32485 -                       pAC->I2c.SenTable[i].SenBegWarnTS = 0;
32486 -                       pAC->I2c.SenTable[i].SenLastErrTrapTS = (SK_U64)0;
32487 -                       pAC->I2c.SenTable[i].SenLastErrLogTS = (SK_U64)0;
32488 -                       pAC->I2c.SenTable[i].SenLastWarnTrapTS = (SK_U64)0;
32489 -                       pAC->I2c.SenTable[i].SenLastWarnLogTS = (SK_U64)0;
32490 -               }
32491 -               break;
32492 -       default:
32493 -               SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E006, SKERR_I2C_E006MSG);
32494 -       }
32495 -
32496 -       return(0);
32497 -}      /* SkI2cEvent*/
32498 -
32499 -#endif /* !SK_DIAG */
32500 diff -ruN linux/drivers/net/sk98lin/sklm80.c linux-new/drivers/net/sk98lin/sklm80.c
32501 --- linux/drivers/net/sk98lin/sklm80.c  2006-09-20 05:42:06.000000000 +0200
32502 +++ linux-new/drivers/net/sk98lin/sklm80.c      2006-07-28 14:13:54.000000000 +0200
32503 @@ -2,14 +2,15 @@
32504   *
32505   * Name:       sklm80.c
32506   * Project:    Gigabit Ethernet Adapters, TWSI-Module
32507 - * Version:    $Revision$
32508 - * Date:       $Date$
32509 + * Version:    $Revision$
32510 + * Date:       $Date$
32511   * Purpose:    Functions to access Voltage and Temperature Sensor (LM80)
32512   *
32513   ******************************************************************************/
32514
32515  /******************************************************************************
32516   *
32517 + *     LICENSE:
32518   *     (C)Copyright 1998-2002 SysKonnect.
32519   *     (C)Copyright 2002-2003 Marvell.
32520   *
32521 @@ -19,6 +20,7 @@
32522   *     (at your option) any later version.
32523   *
32524   *     The information in this file is provided "AS IS" without warranty.
32525 + *     /LICENSE
32526   *
32527   ******************************************************************************/
32528
32529 @@ -27,24 +29,96 @@
32530  */
32531  #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
32532  static const char SysKonnectFileId[] =
32533 -       "@(#) $Id$ (C) Marvell. ";
32534 +       "@(#) $Id$ (C) Marvell. ";
32535  #endif
32536
32537  #include "h/skdrv1st.h"                /* Driver Specific Definitions */
32538  #include "h/lm80.h"
32539  #include "h/skdrv2nd.h"                /* Adapter Control- and Driver specific Def. */
32540
32541 +#ifdef SK_DIAG
32542 +#define        BREAK_OR_WAIT(pAC,IoC,Event)    SkI2cWait(pAC,IoC,Event)
32543 +#else  /* nSK_DIAG */
32544  #define        BREAK_OR_WAIT(pAC,IoC,Event)    break
32545 +#endif /* nSK_DIAG */
32546 +
32547 +#ifdef SK_DIAG
32548 +/*
32549 + * read the register 'Reg' from the device 'Dev'
32550 + *
32551 + * return      read error      -1
32552 + *             success         the read value
32553 + */
32554 +int    SkLm80RcvReg(
32555 +SK_IOC IoC,            /* Adapter Context */
32556 +int            Dev,            /* I2C device address */
32557 +int            Reg)            /* register to read */
32558 +{
32559 +       int     Val = 0;
32560 +       int     TempExt;
32561 +
32562 +       /* Signal device number */
32563 +       if (SkI2cSndDev(IoC, Dev, I2C_WRITE)) {
32564 +               return(-1);
32565 +       }
32566 +
32567 +       if (SkI2cSndByte(IoC, Reg)) {
32568 +               return(-1);
32569 +       }
32570 +
32571 +       /* repeat start */
32572 +       if (SkI2cSndDev(IoC, Dev, I2C_READ)) {
32573 +               return(-1);
32574 +       }
32575 +
32576 +       switch (Reg) {
32577 +       case LM80_TEMP_IN:
32578 +               Val = (int)SkI2cRcvByte(IoC, 1);
32579 +
32580 +               /* First: correct the value: it might be negative */
32581 +               if ((Val & 0x80) != 0) {
32582 +                       /* Value is negative */
32583 +                       Val = Val - 256;
32584 +               }
32585 +               Val = Val * SK_LM80_TEMP_LSB;
32586 +               SkI2cStop(IoC);
32587 +
32588 +               TempExt = (int)SkLm80RcvReg(IoC, LM80_ADDR, LM80_TEMP_CTRL);
32589 +
32590 +               if (Val > 0) {
32591 +                       Val += ((TempExt >> 7) * SK_LM80_TEMPEXT_LSB);
32592 +               }
32593 +               else {
32594 +                       Val -= ((TempExt >> 7) * SK_LM80_TEMPEXT_LSB);
32595 +               }
32596 +               return(Val);
32597 +               break;
32598 +       case LM80_VT0_IN:
32599 +       case LM80_VT1_IN:
32600 +       case LM80_VT2_IN:
32601 +       case LM80_VT3_IN:
32602 +               Val = (int)SkI2cRcvByte(IoC, 1) * SK_LM80_VT_LSB;
32603 +               break;
32604 +
32605 +       default:
32606 +               Val = (int)SkI2cRcvByte(IoC, 1);
32607 +               break;
32608 +       }
32609 +
32610 +       SkI2cStop(IoC);
32611 +       return(Val);
32612 +}
32613 +#endif /* SK_DIAG */
32614
32615  /*
32616   * read a sensors value (LM80 specific)
32617   *
32618 - * This function reads a sensors value from the I2C sensor chip LM80.
32619 + * This function reads a sensors value from the TWSI sensor chip LM80.
32620   * The sensor is defined by its index into the sensors database in the struct
32621   * pAC points to.
32622   *
32623   * Returns     1 if the read is completed
32624 - *             0 if the read must be continued (I2C Bus still allocated)
32625 + *             0 if the read must be continued (TWSI Bus still allocated)
32626   */
32627  int SkLm80ReadSensor(
32628  SK_AC          *pAC,   /* Adapter Context */
32629 diff -ruN linux/drivers/net/sk98lin/skproc.c linux-new/drivers/net/sk98lin/skproc.c
32630 --- linux/drivers/net/sk98lin/skproc.c  1970-01-01 01:00:00.000000000 +0100
32631 +++ linux-new/drivers/net/sk98lin/skproc.c      2006-07-28 14:13:56.000000000 +0200
32632 @@ -0,0 +1,477 @@
32633 +/******************************************************************************
32634 + *
32635 + * Name:       skproc.c
32636 + * Project:    GEnesis, PCI Gigabit Ethernet Adapter
32637 + * Version:    $Revision$
32638 + * Date:       $Date$
32639 + * Purpose:    Functions to display statictic data
32640 + *
32641 + ******************************************************************************/
32642 +
32643 +/******************************************************************************
32644 + *
32645 + *     (C)Copyright 1998-2002 SysKonnect GmbH.
32646 + *     (C)Copyright 2002-2005 Marvell.
32647 + *
32648 + *     Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet
32649 + *      Server Adapters.
32650 + *
32651 + *     Author: Ralph Roesler (rroesler@syskonnect.de)
32652 + *             Mirko Lindner (mlindner@syskonnect.de)
32653 + *
32654 + *     Address all question to: linux@syskonnect.de
32655 + *
32656 + *     This program is free software; you can redistribute it and/or modify
32657 + *     it under the terms of the GNU General Public License as published by
32658 + *     the Free Software Foundation; either version 2 of the License, or
32659 + *     (at your option) any later version.
32660 + *
32661 + *     The information in this file is provided "AS IS" without warranty.
32662 + *
32663 + *****************************************************************************/
32664 +
32665 +#include <linux/proc_fs.h>
32666 +#include <linux/seq_file.h>
32667 +
32668 +#include "h/skdrv1st.h"
32669 +#include "h/skdrv2nd.h"
32670 +#include "h/skversion.h"
32671 +
32672 +extern struct SK_NET_DEVICE *SkGeRootDev;
32673 +
32674 +/******************************************************************************
32675 + *
32676 + * Local Function Prototypes and Local Variables
32677 + *
32678 + *****************************************************************************/
32679 +
32680 +static int sk_proc_print(void *writePtr, char *format, ...);
32681 +static void sk_gen_browse(void *buffer);
32682 +static int len;
32683 +
32684 +static int sk_seq_show(struct seq_file *seq, void *v);
32685 +static int sk_proc_open(struct inode *inode, struct file *file);
32686 +struct file_operations sk_proc_fops = {
32687 +       .owner          = THIS_MODULE,
32688 +       .open           = sk_proc_open,
32689 +       .read           = seq_read,
32690 +       .llseek         = seq_lseek,
32691 +       .release        = single_release,
32692 +};
32693 +struct net_device *currDev = NULL;
32694 +
32695 +/*****************************************************************************
32696 + *
32697 + *     sk_gen_browse -generic  print "summaries" entry
32698 + *
32699 + * Description:
32700 + *     This function fills the proc entry with statistic data about
32701 + *     the ethernet device.
32702 + *
32703 + * Returns:    N/A
32704 + *
32705 + */
32706 +static void sk_gen_browse(
32707 +void *buffer)  /* buffer where the statistics will be stored in */
32708 +{
32709 +       struct SK_NET_DEVICE    *SkgeProcDev = SkGeRootDev;
32710 +       struct SK_NET_DEVICE    *next;
32711 +       SK_BOOL                 DisableStatistic = 0;
32712 +       SK_PNMI_STRUCT_DATA     *pPnmiStruct;
32713 +       SK_PNMI_STAT            *pPnmiStat;
32714 +       unsigned long           Flags;
32715 +       unsigned int            Size;
32716 +       DEV_NET                 *pNet;
32717 +       SK_AC                   *pAC;
32718 +       char                    sens_msg[50];
32719 +       int                     card_type;
32720 +       int                     MaxSecurityCount = 0;
32721 +       int                     t;
32722 +       int                     i;
32723 +
32724 +       while (SkgeProcDev) {
32725 +               MaxSecurityCount++;
32726 +               if (MaxSecurityCount > 100) {
32727 +                       printk("Max limit for sk_proc_read security counter!\n");
32728 +                       return;
32729 +               }
32730 +               pNet = (DEV_NET*) SkgeProcDev->priv;
32731 +               pAC = pNet->pAC;
32732 +               next = pAC->Next;
32733 +               pPnmiStruct = &pAC->PnmiStruct;
32734 +               /* NetIndex in GetStruct is now required, zero is only dummy */
32735 +
32736 +               for (t=pAC->GIni.GIMacsFound; t > 0; t--) {
32737 +                       if ((pAC->GIni.GIMacsFound == 2) && pAC->RlmtNets == 1)
32738 +                               t--;
32739 +
32740 +                       spin_lock_irqsave(&pAC->SlowPathLock, Flags);
32741 +                       Size = SK_PNMI_STRUCT_SIZE;
32742 +                       DisableStatistic = 0;
32743 +                       if (pAC->BoardLevel == SK_INIT_DATA) {
32744 +                               SK_MEMCPY(&(pAC->PnmiStruct), &(pAC->PnmiBackup), sizeof(SK_PNMI_STRUCT_DATA));
32745 +                               if (pAC->DiagModeActive == DIAG_NOTACTIVE) {
32746 +                                       pAC->Pnmi.DiagAttached = SK_DIAG_IDLE;
32747 +                               }
32748 +                       } else {
32749 +                               SkPnmiGetStruct(pAC, pAC->IoBase, pPnmiStruct, &Size, t-1);
32750 +                       }
32751 +                       spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
32752 +                       if (strcmp(pAC->dev[t-1]->name, currDev->name) == 0) {
32753 +                               if (!pAC->GIni.GIYukon32Bit)
32754 +                                       card_type = 64;
32755 +                               else
32756 +                                       card_type = 32;
32757 +
32758 +                               pPnmiStat = &pPnmiStruct->Stat[0];
32759 +                               len = sk_proc_print(buffer,
32760 +                                       "\nDetailed statistic for device %s\n",
32761 +                                       pAC->dev[t-1]->name);
32762 +                               len += sk_proc_print(buffer,
32763 +                                       "=======================================\n");
32764 +
32765 +                               /* Board statistics */
32766 +                               len += sk_proc_print(buffer,
32767 +                                       "\nBoard statistics\n\n");
32768 +                               len += sk_proc_print(buffer,
32769 +                                       "Card name                      %s\n",
32770 +                                       pAC->DeviceStr);
32771 +                               len += sk_proc_print(buffer,
32772 +                                       "Vendor/Device ID               %x/%x\n",
32773 +                                       pAC->PciDev->vendor,
32774 +                                       pAC->PciDev->device);
32775 +                               len += sk_proc_print(buffer,
32776 +                                       "Card type (Bit)                %d\n",
32777 +                                       card_type);
32778 +
32779 +                               len += sk_proc_print(buffer,
32780 +                                       "Active Port                    %c\n",
32781 +                                       'A' + pAC->Rlmt.Net[t-1].Port[pAC->Rlmt.
32782 +                                       Net[t-1].PrefPort]->PortNumber);
32783 +                               len += sk_proc_print(buffer,
32784 +                                       "Preferred Port                 %c\n",
32785 +                                       'A' + pAC->Rlmt.Net[t-1].Port[pAC->Rlmt.
32786 +                                       Net[t-1].PrefPort]->PortNumber);
32787 +
32788 +                               if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_STATIC) {
32789 +                                       len += sk_proc_print(buffer,
32790 +                                       "Interrupt Moderation           static (%d ints/sec)\n",
32791 +                                       pAC->DynIrqModInfo.MaxModIntsPerSec);
32792 +                               } else if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
32793 +                                       len += sk_proc_print(buffer,
32794 +                                       "Interrupt Moderation           dynamic (%d ints/sec)\n",
32795 +                                       pAC->DynIrqModInfo.MaxModIntsPerSec);
32796 +                               } else {
32797 +                                       len += sk_proc_print(buffer,
32798 +                                       "Interrupt Moderation           disabled\n");
32799 +                               }
32800 +
32801 +                               if (pAC->GIni.GIPciBus == SK_PEX_BUS) {
32802 +                                       len += sk_proc_print(buffer,
32803 +                                               "Bus type                       PCI-Express\n");
32804 +                                       len += sk_proc_print(buffer,
32805 +                                               "Bus width (Lanes)              %d\n",
32806 +                                               pAC->GIni.GIPexWidth);
32807 +                               } else {
32808 +                                       if (pAC->GIni.GIPciBus == SK_PCIX_BUS) {
32809 +                                               len += sk_proc_print(buffer,
32810 +                                                       "Bus type                       PCI-X\n");
32811 +                                               if (pAC->GIni.GIPciMode == PCI_OS_SPD_X133) {
32812 +                                                       len += sk_proc_print(buffer,
32813 +                                                               "Bus speed (MHz)                133\n");
32814 +                                               } else if (pAC->GIni.GIPciMode == PCI_OS_SPD_X100) {
32815 +                                                       len += sk_proc_print(buffer,
32816 +                                                               "Bus speed (MHz)                100\n");
32817 +                                               } else if (pAC->GIni.GIPciMode == PCI_OS_SPD_X66) {
32818 +                                                       len += sk_proc_print(buffer,
32819 +                                                               "Bus speed (MHz)                66\n");
32820 +                                               } else {
32821 +                                                       len += sk_proc_print(buffer,
32822 +                                                               "Bus speed (MHz)                33\n");
32823 +                                               }
32824 +                                       } else {
32825 +                                               len += sk_proc_print(buffer,
32826 +                                                       "Bus type                       PCI\n");
32827 +                                               len += sk_proc_print(buffer,
32828 +                                                       "Bus speed (MHz)                %d\n",
32829 +                                                       pPnmiStruct->BusSpeed);
32830 +                                       }
32831 +                                       len += sk_proc_print(buffer,
32832 +                                               "Bus width (Bit)                %d\n",
32833 +                                               pPnmiStruct->BusWidth);
32834 +                               }
32835 +
32836 +                               len += sk_proc_print(buffer,
32837 +                                       "Driver version                 %s (%s)\n",
32838 +                                       VER_STRING, PATCHLEVEL);
32839 +                               len += sk_proc_print(buffer,
32840 +                                       "Driver release date            %s\n",
32841 +                                       pAC->Pnmi.pDriverReleaseDate);
32842 +                               len += sk_proc_print(buffer,
32843 +                                       "Hardware revision              v%d.%d\n",
32844 +                                       (pAC->GIni.GIPciHwRev >> 4) & 0x0F,
32845 +                                       pAC->GIni.GIPciHwRev & 0x0F);
32846 +
32847 +                               if (!netif_running(pAC->dev[t-1])) {
32848 +                                       len += sk_proc_print(buffer,
32849 +                                               "\n      Device %s is down.\n"
32850 +                                               "      Therefore no statistics are available.\n"
32851 +                                               "      After bringing the device up (ifconfig)"
32852 +                                               " statistics will\n"
32853 +                                               "      be displayed.\n",
32854 +                                               pAC->dev[t-1]->name);
32855 +                                       DisableStatistic = 1;
32856 +                               }
32857 +
32858 +                               /* Display only if statistic info available */
32859 +                               /* Print sensor informations */
32860 +                               if (!DisableStatistic) {
32861 +                                       for (i=0; i < pAC->I2c.MaxSens; i ++) {
32862 +                                               /* Check type */
32863 +                                               switch (pAC->I2c.SenTable[i].SenType) {
32864 +                                               case 1:
32865 +                                                       strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc);
32866 +                                                       strcat(sens_msg, " (C)");
32867 +                                                       len += sk_proc_print(buffer,
32868 +                                                               "%-25s      %d.%02d\n",
32869 +                                                               sens_msg,
32870 +                                                               pAC->I2c.SenTable[i].SenValue / 10,
32871 +                                                               pAC->I2c.SenTable[i].SenValue %
32872 +                                                               10);
32873 +
32874 +                                                       strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc);
32875 +                                                       strcat(sens_msg, " (F)");
32876 +                                                       len += sk_proc_print(buffer,
32877 +                                                               "%-25s      %d.%02d\n",
32878 +                                                               sens_msg,
32879 +                                                               ((((pAC->I2c.SenTable[i].SenValue)
32880 +                                                               *10)*9)/5 + 3200)/100,
32881 +                                                               ((((pAC->I2c.SenTable[i].SenValue)
32882 +                                                               *10)*9)/5 + 3200) % 10);
32883 +                                                       break;
32884 +                                               case 2:
32885 +                                                       strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc);
32886 +                                                       strcat(sens_msg, " (V)");
32887 +                                                       len += sk_proc_print(buffer,
32888 +                                                               "%-25s      %d.%03d\n",
32889 +                                                               sens_msg,
32890 +                                                               pAC->I2c.SenTable[i].SenValue / 1000,
32891 +                                                               pAC->I2c.SenTable[i].SenValue % 1000);
32892 +                                                       break;
32893 +                                               case 3:
32894 +                                                       strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc);
32895 +                                                       strcat(sens_msg, " (rpm)");
32896 +                                                       len += sk_proc_print(buffer,
32897 +                                                               "%-25s      %d\n",
32898 +                                                               sens_msg,
32899 +                                                               pAC->I2c.SenTable[i].SenValue);
32900 +                                                       break;
32901 +                                               default:
32902 +                                                       break;
32903 +                                               }
32904 +                                       }
32905 +
32906 +                                       /*Receive statistics */
32907 +                                       len += sk_proc_print(buffer,
32908 +                                       "\nReceive statistics\n\n");
32909 +
32910 +                                       len += sk_proc_print(buffer,
32911 +                                               "Received bytes                 %Lu\n",
32912 +                                               (unsigned long long) pPnmiStat->StatRxOctetsOkCts);
32913 +                                       len += sk_proc_print(buffer,
32914 +                                               "Received packets               %Lu\n",
32915 +                                               (unsigned long long) pPnmiStat->StatRxOkCts);
32916 +#if 0
32917 +                                       if (pAC->GIni.GP[0].PhyType == SK_PHY_XMAC &&
32918 +                                               pAC->HWRevision < 12) {
32919 +                                               pPnmiStruct->InErrorsCts = pPnmiStruct->InErrorsCts -
32920 +                                                       pPnmiStat->StatRxShortsCts;
32921 +                                               pPnmiStat->StatRxShortsCts = 0;
32922 +                                       }
32923 +#endif
32924 +                                       if (pAC->dev[t-1]->mtu > 1500)
32925 +                                               pPnmiStruct->InErrorsCts = pPnmiStruct->InErrorsCts -
32926 +                                                       pPnmiStat->StatRxTooLongCts;
32927 +
32928 +                                       len += sk_proc_print(buffer,
32929 +                                               "Receive errors                 %Lu\n",
32930 +                                               (unsigned long long) pPnmiStruct->InErrorsCts);
32931 +                                       len += sk_proc_print(buffer,
32932 +                                               "Receive dropped                %Lu\n",
32933 +                                               (unsigned long long) pPnmiStruct->RxNoBufCts);
32934 +                                       len += sk_proc_print(buffer,
32935 +                                               "Received multicast             %Lu\n",
32936 +                                               (unsigned long long) pPnmiStat->StatRxMulticastOkCts);
32937 +#ifdef ADVANCED_STATISTIC_OUTPUT
32938 +                                       len += sk_proc_print(buffer,
32939 +                                               "Receive error types\n");
32940 +                                       len += sk_proc_print(buffer,
32941 +                                               "   length                      %Lu\n",
32942 +                                               (unsigned long long) pPnmiStat->StatRxRuntCts);
32943 +                                       len += sk_proc_print(buffer,
32944 +                                               "   buffer overflow             %Lu\n",
32945 +                                               (unsigned long long) pPnmiStat->StatRxFifoOverflowCts);
32946 +                                       len += sk_proc_print(buffer,
32947 +                                               "   bad crc                     %Lu\n",
32948 +                                               (unsigned long long) pPnmiStat->StatRxFcsCts);
32949 +                                       len += sk_proc_print(buffer,
32950 +                                               "   framing                     %Lu\n",
32951 +                                               (unsigned long long) pPnmiStat->StatRxFramingCts);
32952 +                                       len += sk_proc_print(buffer,
32953 +                                               "   missed frames               %Lu\n",
32954 +                                               (unsigned long long) pPnmiStat->StatRxMissedCts);
32955 +
32956 +                                       if (pAC->dev[t-1]->mtu > 1500)
32957 +                                               pPnmiStat->StatRxTooLongCts = 0;
32958 +
32959 +                                       len += sk_proc_print(buffer,
32960 +                                               "   too long                    %Lu\n",
32961 +                                               (unsigned long long) pPnmiStat->StatRxTooLongCts);
32962 +                                       len += sk_proc_print(buffer,
32963 +                                               "   carrier extension           %Lu\n",
32964 +                                               (unsigned long long) pPnmiStat->StatRxCextCts);
32965 +                                       len += sk_proc_print(buffer,
32966 +                                               "   too short                   %Lu\n",
32967 +                                               (unsigned long long) pPnmiStat->StatRxShortsCts);
32968 +                                       len += sk_proc_print(buffer,
32969 +                                               "   symbol                      %Lu\n",
32970 +                                               (unsigned long long) pPnmiStat->StatRxSymbolCts);
32971 +                                       len += sk_proc_print(buffer,
32972 +                                               "   LLC MAC size                %Lu\n",
32973 +                                               (unsigned long long) pPnmiStat->StatRxIRLengthCts);
32974 +                                       len += sk_proc_print(buffer,
32975 +                                               "   carrier event               %Lu\n",
32976 +                                               (unsigned long long) pPnmiStat->StatRxCarrierCts);
32977 +                                       len += sk_proc_print(buffer,
32978 +                                               "   jabber                      %Lu\n",
32979 +                                               (unsigned long long) pPnmiStat->StatRxJabberCts);
32980 +#endif
32981 +
32982 +                                       /*Transmit statistics */
32983 +                                       len += sk_proc_print(buffer,
32984 +                                       "\nTransmit statistics\n\n");
32985 +
32986 +                                       len += sk_proc_print(buffer,
32987 +                                               "Transmitted bytes              %Lu\n",
32988 +                                               (unsigned long long) pPnmiStat->StatTxOctetsOkCts);
32989 +                                       len += sk_proc_print(buffer,
32990 +                                               "Transmitted packets            %Lu\n",
32991 +                                               (unsigned long long) pPnmiStat->StatTxOkCts);
32992 +                                       len += sk_proc_print(buffer,
32993 +                                               "Transmit errors                %Lu\n",
32994 +                                               (unsigned long long) pPnmiStat->StatTxSingleCollisionCts);
32995 +                                       len += sk_proc_print(buffer,
32996 +                                               "Transmit dropped               %Lu\n",
32997 +                                               (unsigned long long) pPnmiStruct->TxNoBufCts);
32998 +                                       len += sk_proc_print(buffer,
32999 +                                               "Transmit collisions            %Lu\n",
33000 +                                               (unsigned long long) pPnmiStat->StatTxSingleCollisionCts);
33001 +#ifdef ADVANCED_STATISTIC_OUTPUT
33002 +                                       len += sk_proc_print(buffer,
33003 +                                               "Transmit error types\n");
33004 +                                       len += sk_proc_print(buffer,
33005 +                                               "   excessive collision         %ld\n",
33006 +                                               pAC->stats.tx_aborted_errors);
33007 +                                       len += sk_proc_print(buffer,
33008 +                                               "   carrier                     %Lu\n",
33009 +                                               (unsigned long long) pPnmiStat->StatTxCarrierCts);
33010 +                                       len += sk_proc_print(buffer,
33011 +                                               "   fifo underrun               %Lu\n",
33012 +                                               (unsigned long long) pPnmiStat->StatTxFifoUnderrunCts);
33013 +                                       len += sk_proc_print(buffer,
33014 +                                               "   heartbeat                   %Lu\n",
33015 +                                               (unsigned long long) pPnmiStat->StatTxCarrierCts);
33016 +                                       len += sk_proc_print(buffer,
33017 +                                               "   window                      %ld\n",
33018 +                                               pAC->stats.tx_window_errors);
33019 +#endif
33020 +                               } /* if (!DisableStatistic) */
33021 +
33022 +                       } /* if (strcmp(pACname, currDeviceName) == 0) */
33023 +               }
33024 +               SkgeProcDev = next;
33025 +       }
33026 +}
33027 +
33028 +/*****************************************************************************
33029 + *
33030 + *      sk_proc_print - generic line print
33031 + *
33032 + * Description:
33033 + *     This function fills the proc entry with statistic data about the
33034 + *     ethernet device.
33035 + *
33036 + * Returns:
33037 + *     the number of bytes written
33038 + *
33039 + */
33040 +static int sk_proc_print(
33041 +void *writePtr, /* the buffer pointer         */
33042 +char *format,   /* the format of the string   */
33043 +...)            /* variable list of arguments */
33044 +{
33045 +#define MAX_LEN_SINGLE_LINE 256
33046 +       char     str[MAX_LEN_SINGLE_LINE];
33047 +       va_list  a_start;
33048 +       int      lenght = 0;
33049 +
33050 +       struct seq_file *seq = (struct seq_file *) writePtr;
33051 +
33052 +       SK_MEMSET(str, 0, MAX_LEN_SINGLE_LINE);
33053 +
33054 +       va_start(a_start, format);
33055 +       vsprintf(str, format, a_start);
33056 +       va_end(a_start);
33057 +
33058 +       lenght = strlen(str);
33059 +
33060 +       seq_printf(seq, str);
33061 +       return lenght;
33062 +}
33063 +
33064 +/*****************************************************************************
33065 + *
33066 + *      sk_seq_show - show proc information of a particular adapter
33067 + *
33068 + * Description:
33069 + *     This function fills the proc entry with statistic data about the
33070 + *     ethernet device. It invokes the generic sk_gen_browse() to print
33071 + *     out all items one per one.
33072 + *
33073 + * Returns:
33074 + *     the number of bytes written
33075 + *
33076 + */
33077 +static int sk_seq_show(
33078 +struct seq_file *seq,  /* the sequence pointer */
33079 +void            *v)    /* additional pointer   */
33080 +{
33081 +       void *castedBuffer = (void *) seq;
33082 +       currDev = seq->private;
33083 +       sk_gen_browse(castedBuffer);
33084 +       return 0;
33085 +}
33086 +
33087 +/*****************************************************************************
33088 + *
33089 + *      sk_proc_open - register the show function when proc is open'ed
33090 + *
33091 + * Description:
33092 + *     This function is called whenever a sk98lin proc file is queried.
33093 + *
33094 + * Returns:
33095 + *     the return value of single_open()
33096 + *
33097 + */
33098 +static int sk_proc_open(
33099 +struct inode *inode,  /* the inode of the file   */
33100 +struct file  *file)   /* the file pointer itself */
33101 +{
33102 +       return single_open(file, sk_seq_show, PDE(inode)->data);
33103 +}
33104 +
33105 +/*******************************************************************************
33106 + *
33107 + * End of file
33108 + *
33109 + ******************************************************************************/
33110 diff -ruN linux/drivers/net/sk98lin/skqueue.c linux-new/drivers/net/sk98lin/skqueue.c
33111 --- linux/drivers/net/sk98lin/skqueue.c 2006-09-20 05:42:06.000000000 +0200
33112 +++ linux-new/drivers/net/sk98lin/skqueue.c     2006-07-28 14:13:54.000000000 +0200
33113 @@ -2,14 +2,15 @@
33114   *
33115   * Name:       skqueue.c
33116   * Project:    Gigabit Ethernet Adapters, Event Scheduler Module
33117 - * Version:    $Revision$
33118 - * Date:       $Date$
33119 + * Version:    $Revision$
33120 + * Date:       $Date$
33121   * Purpose:    Management of an event queue.
33122   *
33123   ******************************************************************************/
33124
33125  /******************************************************************************
33126   *
33127 + *     LICENSE:
33128   *     (C)Copyright 1998-2002 SysKonnect GmbH.
33129   *     (C)Copyright 2002-2003 Marvell.
33130   *
33131 @@ -19,6 +20,7 @@
33132   *     (at your option) any later version.
33133   *
33134   *     The information in this file is provided "AS IS" without warranty.
33135 + *     /LICENSE
33136   *
33137   ******************************************************************************/
33138
33139 @@ -28,7 +30,7 @@
33140   */
33141  #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
33142  static const char SysKonnectFileId[] =
33143 -       "@(#) $Id$ (C) Marvell.";
33144 +       "@(#) $Id$ (C) Marvell.";
33145  #endif
33146
33147  #include "h/skdrv1st.h"                /* Driver Specific Definitions */
33148 @@ -48,10 +50,16 @@
33149
33150  #define PRINTF(a,b,c)
33151
33152 -/*
33153 - * init event queue management
33154 +/******************************************************************************
33155 + *
33156 + *     SkEventInit() - init event queue management
33157   *
33158 - * Must be called during init level 0.
33159 + * Description:
33160 + *     This function initializes event queue management.
33161 + *     It must be called during init level 0.
33162 + *
33163 + * Returns:
33164 + *     nothing
33165   */
33166  void   SkEventInit(
33167  SK_AC  *pAC,   /* Adapter context */
33168 @@ -67,8 +75,17 @@
33169         }
33170  }
33171
33172 -/*
33173 - * add event to queue
33174 +/******************************************************************************
33175 + *
33176 + *     SkEventQueue()  -       add event to queue
33177 + *
33178 + * Description:
33179 + *     This function adds an event to the event queue.
33180 + *     At least Init Level 1 is required to queue events,
33181 + *     but will be scheduled add Init Level 2.
33182 + *
33183 + * returns:
33184 + *     nothing
33185   */
33186  void   SkEventQueue(
33187  SK_AC          *pAC,   /* Adapters context */
33188 @@ -76,26 +93,45 @@
33189  SK_U32         Event,  /* Event to be queued */
33190  SK_EVPARA      Para)   /* Event parameter */
33191  {
33192 -       pAC->Event.EvPut->Class = Class;
33193 -       pAC->Event.EvPut->Event = Event;
33194 -       pAC->Event.EvPut->Para = Para;
33195 +
33196 +       if (pAC->GIni.GILevel == SK_INIT_DATA) {
33197 +               SK_ERR_LOG(pAC, SK_ERRCL_NORES, SKERR_Q_E003, SKERR_Q_E003MSG);
33198 +       }
33199 +       else {
33200 +               pAC->Event.EvPut->Class = Class;
33201 +               pAC->Event.EvPut->Event = Event;
33202 +               pAC->Event.EvPut->Para = Para;
33203
33204 -       if (++pAC->Event.EvPut == &pAC->Event.EvQueue[SK_MAX_EVENT])
33205 -               pAC->Event.EvPut = pAC->Event.EvQueue;
33206 +               if (++pAC->Event.EvPut == &pAC->Event.EvQueue[SK_MAX_EVENT])
33207 +                       pAC->Event.EvPut = pAC->Event.EvQueue;
33208
33209 -       if (pAC->Event.EvPut == pAC->Event.EvGet) {
33210 -               SK_ERR_LOG(pAC, SK_ERRCL_NORES, SKERR_Q_E001, SKERR_Q_E001MSG);
33211 +               if (pAC->Event.EvPut == pAC->Event.EvGet) {
33212 +                       SK_ERR_LOG(pAC, SK_ERRCL_NORES, SKERR_Q_E001, SKERR_Q_E001MSG);
33213 +               }
33214         }
33215  }
33216
33217 -/*
33218 - * event dispatcher
33219 - *     while event queue is not empty
33220 - *             get event from queue
33221 - *             send command to state machine
33222 - *     end
33223 - *     return error reported by individual Event function
33224 - *             0 if no error occured.
33225 +/******************************************************************************
33226 + *
33227 + *     SkEventDispatcher() -    Event Dispatcher
33228 + *
33229 + * Description:
33230 + *     The event dispatcher performs the following operations:
33231 + *             o while event queue is not empty
33232 + *                     - get event from queue
33233 + *                     - send event to state machine
33234 + *               end
33235 + *
33236 + * CAUTION:
33237 + *     The event functions MUST report an error if performing a reinitialization
33238 + *     of the event queue, e.g. performing level Init 0..2 while in dispatcher
33239 + *     call!
33240 + *  ANY OTHER return value delays scheduling the other events in the
33241 + *     queue. In this case the event blocks the queue until
33242 + *  the error condition is cleared!
33243 + *
33244 + * Returns:
33245 + *     The return value error reported by individual event function
33246   */
33247  int    SkEventDispatcher(
33248  SK_AC  *pAC,   /* Adapters Context */
33249 @@ -105,6 +141,10 @@
33250         SK_U32                  Class;
33251         int                     Rtv;
33252
33253 +       if (pAC->GIni.GILevel != SK_INIT_RUN) {
33254 +               SK_ERR_LOG(pAC, SK_ERRCL_NORES, SKERR_Q_E005, SKERR_Q_E005MSG);
33255 +       }
33256 +
33257         pEv = pAC->Event.EvGet;
33258
33259         PRINTF("dispatch get %x put %x\n", pEv, pAC->Event.ev_put);
33260 @@ -138,7 +178,7 @@
33261                         Rtv = SkSwtEvent(pAC, Ioc, pEv->Event, pEv->Para);
33262                         break;
33263  #endif /* !SK_USE_SW_TIMER */
33264 -#ifdef SK_USE_LAC_EV
33265 +#if defined(SK_USE_LAC_EV) || defined(SK_LBFO)
33266                 case SKGE_LACP :
33267                         Rtv = SkLacpEvent(pAC, Ioc, pEv->Event, pEv->Para);
33268                         break;
33269 @@ -152,6 +192,11 @@
33270                         Rtv = SkFdEvent(pAC, Ioc, pEv->Event, pEv->Para);
33271                         break;
33272  #endif /* SK_USE_LAC_EV */
33273 +#ifdef SK_ASF
33274 +               case SKGE_ASF :
33275 +                       Rtv = SkAsfEvent(pAC,Ioc,pEv->Event,pEv->Para);
33276 +                       break ;
33277 +#endif
33278  #ifdef SK_USE_CSUM
33279                 case SKGE_CSUM :
33280                         Rtv = SkCsEvent(pAC, Ioc, pEv->Event, pEv->Para);
33281 @@ -163,6 +208,20 @@
33282                 }
33283
33284                 if (Rtv != 0) {
33285 +                       /*
33286 +                        * Special Case: See CAUTION statement above.
33287 +                        * We assume the event queue is reset.
33288 +                        */
33289 +                       if (pAC->Event.EvGet != pAC->Event.EvQueue &&
33290 +                               pAC->Event.EvGet != pEv) {
33291 +                               /*
33292 +                                * Create an error log entry if the
33293 +                                * event queue isn't reset.
33294 +                                * In this case it may be blocked.
33295 +                                */
33296 +                               SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_Q_E004, SKERR_Q_E004MSG);
33297 +                       }
33298 +
33299                         return(Rtv);
33300                 }
33301
33302 diff -ruN linux/drivers/net/sk98lin/skrlmt.c linux-new/drivers/net/sk98lin/skrlmt.c
33303 --- linux/drivers/net/sk98lin/skrlmt.c  2006-09-20 05:42:06.000000000 +0200
33304 +++ linux-new/drivers/net/sk98lin/skrlmt.c      2006-07-28 14:13:54.000000000 +0200
33305 @@ -2,14 +2,15 @@
33306   *
33307   * Name:       skrlmt.c
33308   * Project:    GEnesis, PCI Gigabit Ethernet Adapter
33309 - * Version:    $Revision$
33310 - * Date:       $Date$
33311 + * Version:    $Revision$
33312 + * Date:       $Date$
33313   * Purpose:    Manage links on SK-NET Adapters, esp. redundant ones.
33314   *
33315   ******************************************************************************/
33316
33317  /******************************************************************************
33318   *
33319 + *     LICENSE:
33320   *     (C)Copyright 1998-2002 SysKonnect GmbH.
33321   *     (C)Copyright 2002-2003 Marvell.
33322   *
33323 @@ -19,6 +20,7 @@
33324   *     (at your option) any later version.
33325   *
33326   *     The information in this file is provided "AS IS" without warranty.
33327 + *     /LICENSE
33328   *
33329   ******************************************************************************/
33330
33331 @@ -39,7 +41,7 @@
33332
33333  #ifndef        lint
33334  static const char SysKonnectFileId[] =
33335 -       "@(#) $Id$ (C) Marvell.";
33336 +       "@(#) $Id$ (C) Marvell.";
33337  #endif /* !defined(lint) */
33338
33339  #define __SKRLMT_C
33340 @@ -282,6 +284,7 @@
33341
33342  SK_MAC_ADDR    SkRlmtMcAddr =  {{0x01,  0x00,  0x5A,  0x52,  0x4C,  0x4D}};
33343  SK_MAC_ADDR    BridgeMcAddr =  {{0x01,  0x80,  0xC2,  0x00,  0x00,  0x00}};
33344 +SK_MAC_ADDR    BcAddr =                {{0xFF,  0xFF,  0xFF,  0xFF,  0xFF,  0xFF}};
33345
33346  /* local variables ************************************************************/
33347
33348 @@ -349,7 +352,7 @@
33349      SK_BOOL            PhysicalAMacAddressSet;
33350
33351         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_INIT,
33352 -               ("RLMT Init level %d.\n", Level))
33353 +               ("RLMT Init level %d.\n", Level));
33354
33355         switch (Level) {
33356         case SK_INIT_DATA:      /* Initialize data structures. */
33357 @@ -389,7 +392,7 @@
33358
33359         case SK_INIT_IO:        /* GIMacsFound first available here. */
33360                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_INIT,
33361 -                       ("RLMT: %d MACs were detected.\n", pAC->GIni.GIMacsFound))
33362 +                       ("RLMT: %d MACs were detected.\n", pAC->GIni.GIMacsFound));
33363
33364                 pAC->Rlmt.Net[0].NumPorts = pAC->GIni.GIMacsFound;
33365
33366 @@ -511,7 +514,7 @@
33367         }
33368
33369         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33370 -               ("SkRlmtBuildCheckChain.\n"))
33371 +               ("SkRlmtBuildCheckChain.\n"));
33372
33373         NumMacsUp = 0;
33374
33375 @@ -557,7 +560,7 @@
33376                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33377                         ("Port %d checks %d other ports: %2X.\n", i,
33378                                 pAC->Rlmt.Net[NetIdx].Port[i]->PortsChecked,
33379 -                               pAC->Rlmt.Net[NetIdx].Port[i]->PortCheck[0].CheckAddr.a[5]))
33380 +                               pAC->Rlmt.Net[NetIdx].Port[i]->PortCheck[0].CheckAddr.a[5]));
33381         }
33382  #endif /* DEBUG */
33383
33384 @@ -603,7 +606,7 @@
33385         if ((CheckSrc == 0) || (CheckDest == 0)) {
33386                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_ERR,
33387                         ("SkRlmtBuildPacket: Invalid %s%saddr.\n",
33388 -                        (CheckSrc == 0 ? "Src" : ""), (CheckDest == 0 ? "Dest" : "")))
33389 +                        (CheckSrc == 0 ? "Src" : ""), (CheckDest == 0 ? "Dest" : "")));
33390         }
33391  #endif
33392
33393 @@ -795,7 +798,7 @@
33394
33395                         SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para);
33396                         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_TX,
33397 -                               ("SkRlmtSend: BPDU Packet on Port %u.\n", PortNumber))
33398 +                               ("SkRlmtSend: BPDU Packet on Port %u.\n", PortNumber));
33399                 }
33400         }
33401         return;
33402 @@ -834,7 +837,7 @@
33403                  * Bring it up.
33404                  */
33405                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33406 -                       ("SkRlmtPacketReceive: Received on PortDown.\n"))
33407 +                       ("SkRlmtPacketReceive: Received on PortDown.\n"));
33408
33409                 pRPort->PortState = SK_RLMT_PS_GOING_UP;
33410                 pRPort->GuTimeStamp = SkOsGetTime(pAC);
33411 @@ -848,7 +851,7 @@
33412         }       /* PortDown && !SuspectTx */
33413         else if (pRPort->CheckingState & SK_RLMT_PCS_RX) {
33414                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33415 -                       ("SkRlmtPacketReceive: Stop bringing port down.\n"))
33416 +                       ("SkRlmtPacketReceive: Stop bringing port down.\n"));
33417                 SkTimerStop(pAC, IoC, &pRPort->DownRxTimer);
33418                 pRPort->CheckingState &= ~SK_RLMT_PCS_RX;
33419                 /* pAC->Rlmt.CheckSwitch = SK_TRUE; */
33420 @@ -895,7 +898,7 @@
33421         pRPort = &pAC->Rlmt.Port[PortNumber];
33422
33423         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33424 -               ("SkRlmtPacketReceive: PortNumber == %d.\n", PortNumber))
33425 +               ("SkRlmtPacketReceive: PortNumber == %d.\n", PortNumber));
33426
33427         pRPacket = (SK_RLMT_PACKET*)pMb->pData;
33428         pSPacket = (SK_SPTREE_PACKET*)pRPacket;
33429 @@ -916,7 +919,7 @@
33430
33431                 /* Not sent to current MAC or registered MC address => Trash it. */
33432                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33433 -                       ("SkRlmtPacketReceive: Not for me.\n"))
33434 +                       ("SkRlmtPacketReceive: Not for me.\n"));
33435
33436                 SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
33437                 return;
33438 @@ -954,7 +957,7 @@
33439                         pRPacket->Indicator[5] == SK_RLMT_INDICATOR5 &&
33440                         pRPacket->Indicator[6] == SK_RLMT_INDICATOR6) {
33441                         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33442 -                               ("SkRlmtPacketReceive: Duplicate MAC Address.\n"))
33443 +                               ("SkRlmtPacketReceive: Duplicate MAC Address.\n"));
33444
33445                         /* Error Log entry. */
33446                         SK_ERR_LOG(pAC, SK_ERRCL_COMM, SKERR_RLMT_E006, SKERR_RLMT_E006_MSG);
33447 @@ -962,7 +965,7 @@
33448                 else {
33449                         /* Simply trash it. */
33450                         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33451 -                               ("SkRlmtPacketReceive: Sent by me.\n"))
33452 +                               ("SkRlmtPacketReceive: Sent by me.\n"));
33453                 }
33454
33455                 SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
33456 @@ -1006,7 +1009,7 @@
33457  #endif /* 0 */
33458
33459                         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33460 -                               ("SkRlmtPacketReceive: Announce.\n"))
33461 +                               ("SkRlmtPacketReceive: Announce.\n"));
33462
33463                         SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
33464                         break;
33465 @@ -1014,7 +1017,7 @@
33466                 case SK_PACKET_ALIVE:
33467                         if (pRPacket->SSap & LLC_COMMAND_RESPONSE_BIT) {
33468                                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33469 -                                       ("SkRlmtPacketReceive: Alive Reply.\n"))
33470 +                                       ("SkRlmtPacketReceive: Alive Reply.\n"));
33471
33472                                 if (!(pAC->Addr.Port[PortNumber].PromMode & SK_PROM_MODE_LLC) ||
33473                                         SK_ADDR_EQUAL(
33474 @@ -1045,7 +1048,7 @@
33475                         }
33476                         else {  /* Alive Request Packet. */
33477                                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33478 -                                       ("SkRlmtPacketReceive: Alive Request.\n"))
33479 +                                       ("SkRlmtPacketReceive: Alive Request.\n"));
33480
33481                                 pRPort->RxHelloCts++;
33482
33483 @@ -1064,7 +1067,7 @@
33484
33485                 case SK_PACKET_CHECK_TX:
33486                         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33487 -                               ("SkRlmtPacketReceive: Check your tx line.\n"))
33488 +                               ("SkRlmtPacketReceive: Check your tx line.\n"));
33489
33490                         /* A port checking us requests us to check our tx line. */
33491                         pRPort->CheckingState |= SK_RLMT_PCS_TX;
33492 @@ -1087,7 +1090,7 @@
33493
33494                 case SK_PACKET_ADDR_CHANGED:
33495                         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33496 -                               ("SkRlmtPacketReceive: Address Change.\n"))
33497 +                               ("SkRlmtPacketReceive: Address Change.\n"));
33498
33499                         /* Build the check chain. */
33500                         SkRlmtBuildCheckChain(pAC, pRPort->Net->NetNumber);
33501 @@ -1096,7 +1099,7 @@
33502
33503                 default:
33504                         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33505 -                               ("SkRlmtPacketReceive: Unknown RLMT packet.\n"))
33506 +                               ("SkRlmtPacketReceive: Unknown RLMT packet.\n"));
33507
33508                         /* RA;:;: ??? */
33509                         SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
33510 @@ -1106,7 +1109,7 @@
33511                 pSPacket->Ctrl == SK_RLMT_SPT_CTRL &&
33512                 (pSPacket->SSap & ~LLC_COMMAND_RESPONSE_BIT) == SK_RLMT_SPT_SSAP) {
33513                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33514 -                       ("SkRlmtPacketReceive: BPDU Packet.\n"))
33515 +                       ("SkRlmtPacketReceive: BPDU Packet.\n"));
33516
33517                 /* Spanning Tree packet. */
33518                 pRPort->RxSpHelloCts++;
33519 @@ -1138,7 +1141,7 @@
33520                                         pRPort->Root.Id[0], pRPort->Root.Id[1],
33521                                         pRPort->Root.Id[2], pRPort->Root.Id[3],
33522                                         pRPort->Root.Id[4], pRPort->Root.Id[5],
33523 -                                       pRPort->Root.Id[6], pRPort->Root.Id[7]))
33524 +                                       pRPort->Root.Id[6], pRPort->Root.Id[7]));
33525                 }
33526
33527                 SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
33528 @@ -1149,7 +1152,7 @@
33529         }
33530         else {
33531                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33532 -                       ("SkRlmtPacketReceive: Unknown Packet Type.\n"))
33533 +                       ("SkRlmtPacketReceive: Unknown Packet Type.\n"));
33534
33535                 /* Unknown packet. */
33536                 SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
33537 @@ -1231,7 +1234,7 @@
33538         if ((pRPort->PacketsPerTimeSlot - pRPort->BpduPacketsPerTimeSlot) == 0) {
33539                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33540                         ("SkRlmtCheckPort %d: No (%d) receives in last time slot.\n",
33541 -                               PortNumber, pRPort->PacketsPerTimeSlot))
33542 +                               PortNumber, pRPort->PacketsPerTimeSlot));
33543
33544                 /*
33545                  * Check segmentation if there was no receive at least twice
33546 @@ -1248,7 +1251,7 @@
33547
33548                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33549                         ("SkRlmtCheckPort: PortsSuspect %d, PcsRx %d.\n",
33550 -                               pRPort->PortsSuspect, pRPort->CheckingState & SK_RLMT_PCS_RX))
33551 +                               pRPort->PortsSuspect, pRPort->CheckingState & SK_RLMT_PCS_RX));
33552
33553                 if (pRPort->PortState != SK_RLMT_PS_DOWN) {
33554                         NewTimeout = TO_SHORTEN(pAC->Rlmt.Port[PortNumber].Net->TimeoutValue);
33555 @@ -1294,7 +1297,7 @@
33556                         ("SkRlmtCheckPort %d: %d (%d) receives in last time slot.\n",
33557                                 PortNumber,
33558                                 pRPort->PacketsPerTimeSlot - pRPort->BpduPacketsPerTimeSlot,
33559 -                               pRPort->PacketsPerTimeSlot))
33560 +                               pRPort->PacketsPerTimeSlot));
33561
33562                 SkRlmtPortReceives(pAC, IoC, PortNumber);
33563                 if (pAC->Rlmt.CheckSwitch) {
33564 @@ -1344,7 +1347,7 @@
33565                                 i,
33566                                 pAC->Rlmt.Port[i].PortDown, pAC->Rlmt.Port[i].PortNoRx,
33567                                 *((SK_U32*)(&pAC->Rlmt.Port[i].BcTimeStamp) + OFFS_HI32),
33568 -                               *((SK_U32*)(&pAC->Rlmt.Port[i].BcTimeStamp) + OFFS_LO32)))
33569 +                               *((SK_U32*)(&pAC->Rlmt.Port[i].BcTimeStamp) + OFFS_LO32)));
33570
33571                 if (!pAC->Rlmt.Port[i].PortDown && !pAC->Rlmt.Port[i].PortNoRx) {
33572                         if (!PortFound || pAC->Rlmt.Port[i].BcTimeStamp > BcTimeStamp) {
33573 @@ -1357,7 +1360,7 @@
33574
33575         if (PortFound) {
33576                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33577 -                       ("Port %d received the last broadcast.\n", *pSelect))
33578 +                       ("Port %d received the last broadcast.\n", *pSelect));
33579
33580                 /* Look if another port's time stamp is similar. */
33581                 for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) {
33582 @@ -1372,7 +1375,7 @@
33583                                 PortFound = SK_FALSE;
33584
33585                                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33586 -                                       ("Port %d received a broadcast at a similar time.\n", i))
33587 +                                       ("Port %d received a broadcast at a similar time.\n", i));
33588                                 break;
33589                         }
33590                 }
33591 @@ -1384,7 +1387,7 @@
33592                         ("SK_RLMT_SELECT_BCRX found Port %d receiving the substantially "
33593                          "latest broadcast (%u).\n",
33594                                 *pSelect,
33595 -                               BcTimeStamp - pAC->Rlmt.Port[1 - *pSelect].BcTimeStamp))
33596 +                               BcTimeStamp - pAC->Rlmt.Port[1 - *pSelect].BcTimeStamp));
33597         }
33598  #endif /* DEBUG */
33599
33600 @@ -1433,7 +1436,7 @@
33601                         PortFound = SK_TRUE;
33602                         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33603                                 ("SK_RLMT_SELECT_NOTSUSPECT found Port %d up and not check RX.\n",
33604 -                                       *pSelect))
33605 +                                       *pSelect));
33606                         break;
33607                 }
33608         }
33609 @@ -1482,7 +1485,7 @@
33610                         }
33611                         PortFound = SK_TRUE;
33612                         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33613 -                               ("SK_RLMT_SELECT_UP found Port %d up.\n", *pSelect))
33614 +                               ("SK_RLMT_SELECT_UP found Port %d up.\n", *pSelect));
33615                         break;
33616                 }
33617         }
33618 @@ -1543,7 +1546,7 @@
33619         }
33620
33621         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33622 -               ("SK_RLMT_SELECT_GOINGUP found Port %d going up.\n", *pSelect))
33623 +               ("SK_RLMT_SELECT_GOINGUP found Port %d going up.\n", *pSelect));
33624         return (SK_TRUE);
33625  }      /* SkRlmtSelectGoingUp */
33626
33627 @@ -1589,7 +1592,7 @@
33628                         }
33629                         PortFound = SK_TRUE;
33630                         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33631 -                               ("SK_RLMT_SELECT_DOWN found Port %d down.\n", *pSelect))
33632 +                               ("SK_RLMT_SELECT_DOWN found Port %d down.\n", *pSelect));
33633                         break;
33634                 }
33635         }
33636 @@ -1679,16 +1682,19 @@
33637                         Para.Para32[1] = NetIdx;
33638                         SkEventQueue(pAC, SKGE_DRV, SK_DRV_NET_UP, Para);
33639
33640 -                       if ((pAC->Rlmt.Net[NetIdx].RlmtMode & SK_RLMT_TRANSPARENT) == 0 &&
33641 -                               (Para.pParaPtr = SkRlmtBuildPacket(pAC, IoC,
33642 -                               pAC->Rlmt.Net[NetIdx].Port[i]->PortNumber,
33643 -                               SK_PACKET_ANNOUNCE, &pAC->Addr.Net[NetIdx].
33644 -                               CurrentMacAddress, &SkRlmtMcAddr)) != NULL) {
33645 -                               /*
33646 -                                * Send announce packet to RLMT multicast address to force
33647 -                                * switches to learn the new location of the logical MAC address.
33648 -                                */
33649 -                               SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para);
33650 +                       if (pAC->Rlmt.NumNets == 1) {
33651 +                               if ((pAC->Rlmt.Net[NetIdx].RlmtMode & SK_RLMT_TRANSPARENT) == 0 &&
33652 +                                       (Para.pParaPtr = SkRlmtBuildPacket(pAC, IoC,
33653 +                                       pAC->Rlmt.Net[NetIdx].Port[i]->PortNumber,
33654 +                                       SK_PACKET_ANNOUNCE, &pAC->Addr.Net[NetIdx].
33655 +                                       CurrentMacAddress, &SkRlmtMcAddr)) != NULL) {
33656 +
33657 +                                       /*
33658 +                                        * Send announce packet to RLMT multicast address to force
33659 +                                        * switches to learn the new location of the logical MAC address.
33660 +                                        */
33661 +                                       SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para);
33662 +                               }
33663                         }
33664                 }
33665                 else {
33666 @@ -1787,7 +1793,7 @@
33667
33668                         if (Para.Para32[1] != Active) {
33669                                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33670 -                                       ("Active: %d, Para1: %d.\n", Active, Para.Para32[1]))
33671 +                                       ("Active: %d, Para1: %d.\n", Active, Para.Para32[1]));
33672                                 pAC->Rlmt.Net[NetIdx].ActivePort = Para.Para32[1];
33673                                 Para.Para32[0] = pAC->Rlmt.Net[NetIdx].
33674                                         Port[Para.Para32[0]]->PortNumber;
33675 @@ -1867,7 +1873,7 @@
33676                                 pNet->Port[i]->Root.Id[0], pNet->Port[i]->Root.Id[1],
33677                                 pNet->Port[i]->Root.Id[2], pNet->Port[i]->Root.Id[3],
33678                                 pNet->Port[i]->Root.Id[4], pNet->Port[i]->Root.Id[5],
33679 -                               pNet->Port[i]->Root.Id[6], pNet->Port[i]->Root.Id[7]))
33680 +                               pNet->Port[i]->Root.Id[6], pNet->Port[i]->Root.Id[7]));
33681
33682                 if (!pNet->RootIdSet) {
33683                         pNet->Root = pNet->Port[i]->Root;
33684 @@ -1962,13 +1968,13 @@
33685         SK_U32                  i;
33686
33687         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33688 -               ("SK_RLMT_PORTSTART_TIMEOUT Port %d Event BEGIN.\n", Para.Para32[0]))
33689 +               ("SK_RLMT_PORTSTART_TIMEOUT Port %d Event BEGIN.\n", Para.Para32[0]));
33690
33691                 if (Para.Para32[1] != (SK_U32)-1) {
33692                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33693 -                       ("Bad Parameter.\n"))
33694 +                       ("Bad Parameter.\n"));
33695                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33696 -                       ("SK_RLMT_PORTSTART_TIMEOUT Event EMPTY.\n"))
33697 +                       ("SK_RLMT_PORTSTART_TIMEOUT Event EMPTY.\n"));
33698                 return;
33699         }
33700
33701 @@ -1989,7 +1995,7 @@
33702         }
33703
33704         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33705 -               ("SK_RLMT_PORTSTART_TIMEOUT Event END.\n"))
33706 +               ("SK_RLMT_PORTSTART_TIMEOUT Event END.\n"));
33707  }      /* SkRlmtEvtPortStartTim */
33708
33709
33710 @@ -2017,21 +2023,21 @@
33711         SK_EVPARA               Para2;
33712
33713         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33714 -               ("SK_RLMT_LINK_UP Port %d Event BEGIN.\n", Para.Para32[0]))
33715 +               ("SK_RLMT_LINK_UP Port %d Event BEGIN.\n", Para.Para32[0]));
33716
33717         pRPort = &pAC->Rlmt.Port[Para.Para32[0]];
33718         if (!pRPort->PortStarted) {
33719                 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_RLMT_E008, SKERR_RLMT_E008_MSG);
33720
33721                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33722 -                               ("SK_RLMT_LINK_UP Event EMPTY.\n"))
33723 +                               ("SK_RLMT_LINK_UP Event EMPTY.\n"));
33724                 return;
33725         }
33726
33727         if (!pRPort->LinkDown) {
33728                 /* RA;:;: Any better solution? */
33729                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33730 -                       ("SK_RLMT_LINK_UP Event EMPTY.\n"))
33731 +                       ("SK_RLMT_LINK_UP Event EMPTY.\n"));
33732                 return;
33733         }
33734
33735 @@ -2081,16 +2087,19 @@
33736         Para2.Para32[1] = (SK_U32)-1;
33737         SkTimerStart(pAC, IoC, &pRPort->UpTimer, SK_RLMT_PORTUP_TIM_VAL,
33738                 SKGE_RLMT, SK_RLMT_PORTUP_TIM, Para2);
33739 -
33740 +
33741         /* Later: if (pAC->Rlmt.RlmtMode & SK_RLMT_CHECK_LOC_LINK) && */
33742 -       if ((pRPort->Net->RlmtMode & SK_RLMT_TRANSPARENT) == 0 &&
33743 -               (pRPort->Net->RlmtMode & SK_RLMT_CHECK_LINK) != 0 &&
33744 -               (Para2.pParaPtr =
33745 -                       SkRlmtBuildPacket(pAC, IoC, Para.Para32[0], SK_PACKET_ANNOUNCE,
33746 -                       &pAC->Addr.Port[Para.Para32[0]].CurrentMacAddress, &SkRlmtMcAddr)
33747 -               ) != NULL) {
33748 -               /* Send "new" packet to RLMT multicast address. */
33749 -               SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para2);
33750 +       if (pAC->Rlmt.NumNets == 1) {
33751 +               if ((pRPort->Net->RlmtMode & SK_RLMT_TRANSPARENT) == 0 &&
33752 +                       (pRPort->Net->RlmtMode & SK_RLMT_CHECK_LINK) != 0 &&
33753 +                       (Para2.pParaPtr =
33754 +                               SkRlmtBuildPacket(pAC, IoC, Para.Para32[0], SK_PACKET_ANNOUNCE,
33755 +                               &pAC->Addr.Port[Para.Para32[0]].CurrentMacAddress, &SkRlmtMcAddr)
33756 +                       ) != NULL) {
33757 +
33758 +                       /* Send "new" packet to RLMT multicast address. */
33759 +                       SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para2);
33760 +               }
33761         }
33762
33763         if (pRPort->Net->RlmtMode & SK_RLMT_CHECK_SEG) {
33764 @@ -2109,7 +2118,7 @@
33765         }
33766
33767         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33768 -               ("SK_RLMT_LINK_UP Event END.\n"))
33769 +               ("SK_RLMT_LINK_UP Event END.\n"));
33770  }      /* SkRlmtEvtLinkUp */
33771
33772
33773 @@ -2135,20 +2144,20 @@
33774         SK_RLMT_PORT    *pRPort;
33775
33776         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33777 -               ("SK_RLMT_PORTUP_TIM Port %d Event BEGIN.\n", Para.Para32[0]))
33778 +               ("SK_RLMT_PORTUP_TIM Port %d Event BEGIN.\n", Para.Para32[0]));
33779
33780         if (Para.Para32[1] != (SK_U32)-1) {
33781                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33782 -                       ("Bad Parameter.\n"))
33783 +                       ("Bad Parameter.\n"));
33784                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33785 -                       ("SK_RLMT_PORTUP_TIM Event EMPTY.\n"))
33786 +                       ("SK_RLMT_PORTUP_TIM Event EMPTY.\n"));
33787                 return;
33788         }
33789
33790         pRPort = &pAC->Rlmt.Port[Para.Para32[0]];
33791         if (pRPort->LinkDown || (pRPort->PortState == SK_RLMT_PS_UP)) {
33792                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33793 -                       ("SK_RLMT_PORTUP_TIM Port %d Event EMPTY.\n", Para.Para32[0]))
33794 +                       ("SK_RLMT_PORTUP_TIM Port %d Event EMPTY.\n", Para.Para32[0]));
33795                 return;
33796         }
33797
33798 @@ -2163,7 +2172,7 @@
33799         }
33800
33801         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33802 -               ("SK_RLMT_PORTUP_TIM Event END.\n"))
33803 +               ("SK_RLMT_PORTUP_TIM Event END.\n"));
33804  }      /* SkRlmtEvtPortUpTim */
33805
33806
33807 @@ -2191,13 +2200,13 @@
33808
33809         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33810                 ("SK_RLMT_PORTDOWN* Port %d Event (%d) BEGIN.\n",
33811 -                       Para.Para32[0], Event))
33812 +                       Para.Para32[0], Event));
33813
33814         if (Para.Para32[1] != (SK_U32)-1) {
33815                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33816 -                       ("Bad Parameter.\n"))
33817 +                       ("Bad Parameter.\n"));
33818                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33819 -                       ("SK_RLMT_PORTDOWN* Event EMPTY.\n"))
33820 +                       ("SK_RLMT_PORTDOWN* Event EMPTY.\n"));
33821                 return;
33822         }
33823
33824 @@ -2205,7 +2214,7 @@
33825         if (!pRPort->PortStarted || (Event == SK_RLMT_PORTDOWN_TX_TIM &&
33826                 !(pRPort->CheckingState & SK_RLMT_PCS_TX))) {
33827                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33828 -                       ("SK_RLMT_PORTDOWN* Event (%d) EMPTY.\n", Event))
33829 +                       ("SK_RLMT_PORTDOWN* Event (%d) EMPTY.\n", Event));
33830                 return;
33831         }
33832
33833 @@ -2242,7 +2251,7 @@
33834         }
33835
33836         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33837 -               ("SK_RLMT_PORTDOWN* Event (%d) END.\n", Event))
33838 +               ("SK_RLMT_PORTDOWN* Event (%d) END.\n", Event));
33839  }      /* SkRlmtEvtPortDownX */
33840
33841
33842 @@ -2269,7 +2278,7 @@
33843
33844         pRPort = &pAC->Rlmt.Port[Para.Para32[0]];
33845         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33846 -               ("SK_RLMT_LINK_DOWN Port %d Event BEGIN.\n", Para.Para32[0]))
33847 +               ("SK_RLMT_LINK_DOWN Port %d Event BEGIN.\n", Para.Para32[0]));
33848
33849         if (!pAC->Rlmt.Port[Para.Para32[0]].LinkDown) {
33850                 pRPort->Net->LinksUp--;
33851 @@ -2288,7 +2297,7 @@
33852         }
33853
33854         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33855 -               ("SK_RLMT_LINK_DOWN Event END.\n"))
33856 +               ("SK_RLMT_LINK_DOWN Event END.\n"));
33857  }      /* SkRlmtEvtLinkDown */
33858
33859
33860 @@ -2317,13 +2326,13 @@
33861         SK_MAC_ADDR             *pNewMacAddr;
33862
33863         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33864 -               ("SK_RLMT_PORT_ADDR Port %d Event BEGIN.\n", Para.Para32[0]))
33865 +               ("SK_RLMT_PORT_ADDR Port %d Event BEGIN.\n", Para.Para32[0]));
33866
33867         if (Para.Para32[1] != (SK_U32)-1) {
33868                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33869 -                       ("Bad Parameter.\n"))
33870 +                       ("Bad Parameter.\n"));
33871                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33872 -                       ("SK_RLMT_PORT_ADDR Event EMPTY.\n"))
33873 +                       ("SK_RLMT_PORT_ADDR Event EMPTY.\n"));
33874                 return;
33875         }
33876
33877 @@ -2347,7 +2356,7 @@
33878         }
33879
33880         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33881 -                       ("SK_RLMT_PORT_ADDR Event END.\n"))
33882 +                       ("SK_RLMT_PORT_ADDR Event END.\n"));
33883  }      /* SkRlmtEvtPortAddr */
33884
33885
33886 @@ -2375,35 +2384,35 @@
33887         SK_U32          PortNumber;
33888
33889         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33890 -               ("SK_RLMT_START Net %d Event BEGIN.\n", Para.Para32[0]))
33891 +               ("SK_RLMT_START Net %d Event BEGIN.\n", Para.Para32[0]));
33892
33893         if (Para.Para32[1] != (SK_U32)-1) {
33894                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33895 -                       ("Bad Parameter.\n"))
33896 +                       ("Bad Parameter.\n"));
33897                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33898 -                       ("SK_RLMT_START Event EMPTY.\n"))
33899 +                       ("SK_RLMT_START Event EMPTY.\n"));
33900                 return;
33901         }
33902
33903         if (Para.Para32[0] >= pAC->Rlmt.NumNets) {
33904                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33905 -                       ("Bad NetNumber %d.\n", Para.Para32[0]))
33906 +                       ("Bad NetNumber %d.\n", Para.Para32[0]));
33907                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33908 -                       ("SK_RLMT_START Event EMPTY.\n"))
33909 +                       ("SK_RLMT_START Event EMPTY.\n"));
33910                 return;
33911         }
33912
33913         if (pAC->Rlmt.Net[Para.Para32[0]].RlmtState != SK_RLMT_RS_INIT) {
33914                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33915 -                       ("SK_RLMT_START Event EMPTY.\n"))
33916 +                       ("SK_RLMT_START Event EMPTY.\n"));
33917                 return;
33918         }
33919
33920         if (pAC->Rlmt.NetsStarted >= pAC->Rlmt.NumNets) {
33921                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33922 -                       ("All nets should have been started.\n"))
33923 +                       ("All nets should have been started.\n"));
33924                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33925 -                       ("SK_RLMT_START Event EMPTY.\n"))
33926 +                       ("SK_RLMT_START Event EMPTY.\n"));
33927                 return;
33928         }
33929
33930 @@ -2437,7 +2446,7 @@
33931         pAC->Rlmt.NetsStarted++;
33932
33933         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33934 -                       ("SK_RLMT_START Event END.\n"))
33935 +                       ("SK_RLMT_START Event END.\n"));
33936  }      /* SkRlmtEvtStart */
33937
33938
33939 @@ -2465,35 +2474,35 @@
33940         SK_U32          i;
33941
33942         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33943 -               ("SK_RLMT_STOP Net %d Event BEGIN.\n", Para.Para32[0]))
33944 +               ("SK_RLMT_STOP Net %d Event BEGIN.\n", Para.Para32[0]));
33945
33946         if (Para.Para32[1] != (SK_U32)-1) {
33947                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33948 -                       ("Bad Parameter.\n"))
33949 +                       ("Bad Parameter.\n"));
33950                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33951 -                       ("SK_RLMT_STOP Event EMPTY.\n"))
33952 +                       ("SK_RLMT_STOP Event EMPTY.\n"));
33953                 return;
33954         }
33955
33956         if (Para.Para32[0] >= pAC->Rlmt.NumNets) {
33957                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33958 -                       ("Bad NetNumber %d.\n", Para.Para32[0]))
33959 +                       ("Bad NetNumber %d.\n", Para.Para32[0]));
33960                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33961 -                       ("SK_RLMT_STOP Event EMPTY.\n"))
33962 +                       ("SK_RLMT_STOP Event EMPTY.\n"));
33963                 return;
33964         }
33965
33966         if (pAC->Rlmt.Net[Para.Para32[0]].RlmtState == SK_RLMT_RS_INIT) {
33967                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33968 -                       ("SK_RLMT_STOP Event EMPTY.\n"))
33969 +                       ("SK_RLMT_STOP Event EMPTY.\n"));
33970                 return;
33971         }
33972
33973         if (pAC->Rlmt.NetsStarted == 0) {
33974                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33975 -                       ("All nets are stopped.\n"))
33976 +                       ("All nets are stopped.\n"));
33977                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33978 -                       ("SK_RLMT_STOP Event EMPTY.\n"))
33979 +                       ("SK_RLMT_STOP Event EMPTY.\n"));
33980                 return;
33981         }
33982
33983 @@ -2528,7 +2537,7 @@
33984         pAC->Rlmt.NetsStarted--;
33985
33986         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33987 -               ("SK_RLMT_STOP Event END.\n"))
33988 +               ("SK_RLMT_STOP Event END.\n"));
33989  }      /* SkRlmtEvtStop */
33990
33991
33992 @@ -2558,13 +2567,13 @@
33993         SK_U32                  i;
33994
33995         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33996 -               ("SK_RLMT_TIM Event BEGIN.\n"))
33997 +               ("SK_RLMT_TIM Event BEGIN.\n"));
33998
33999         if (Para.Para32[1] != (SK_U32)-1) {
34000                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34001 -                       ("Bad Parameter.\n"))
34002 +                       ("Bad Parameter.\n"));
34003                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34004 -                       ("SK_RLMT_TIM Event EMPTY.\n"))
34005 +                       ("SK_RLMT_TIM Event EMPTY.\n"));
34006                 return;
34007         }
34008
34009 @@ -2636,7 +2645,7 @@
34010         }
34011
34012         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34013 -                       ("SK_RLMT_TIM Event END.\n"))
34014 +                       ("SK_RLMT_TIM Event END.\n"));
34015  }      /* SkRlmtEvtTim */
34016
34017
34018 @@ -2664,13 +2673,13 @@
34019  #endif /* DEBUG */
34020
34021         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34022 -               ("SK_RLMT_SEG_TIM Event BEGIN.\n"))
34023 +               ("SK_RLMT_SEG_TIM Event BEGIN.\n"));
34024
34025         if (Para.Para32[1] != (SK_U32)-1) {
34026                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34027 -                       ("Bad Parameter.\n"))
34028 +                       ("Bad Parameter.\n"));
34029                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34030 -                       ("SK_RLMT_SEG_TIM Event EMPTY.\n"))
34031 +                       ("SK_RLMT_SEG_TIM Event EMPTY.\n"));
34032                 return;
34033         }
34034
34035 @@ -2694,7 +2703,7 @@
34036                                         InAddr8[3], InAddr8[4], InAddr8[5],
34037                                         pAPort->Exact[k].a[0], pAPort->Exact[k].a[1],
34038                                         pAPort->Exact[k].a[2], pAPort->Exact[k].a[3],
34039 -                                       pAPort->Exact[k].a[4], pAPort->Exact[k].a[5]))
34040 +                                       pAPort->Exact[k].a[4], pAPort->Exact[k].a[5]));
34041                 }
34042         }
34043  #endif /* xDEBUG */
34044 @@ -2702,7 +2711,7 @@
34045         SkRlmtCheckSeg(pAC, IoC, Para.Para32[0]);
34046
34047         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34048 -                       ("SK_RLMT_SEG_TIM Event END.\n"))
34049 +                       ("SK_RLMT_SEG_TIM Event END.\n"));
34050  }      /* SkRlmtEvtSegTim */
34051
34052
34053 @@ -2731,18 +2740,18 @@
34054
34055
34056         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34057 -               ("SK_RLMT_PACKET_RECEIVED Event BEGIN.\n"))
34058 +               ("SK_RLMT_PACKET_RECEIVED Event BEGIN.\n"));
34059
34060         /* Should we ignore frames during port switching? */
34061
34062  #ifdef DEBUG
34063         pMb = Para.pParaPtr;
34064         if (pMb == NULL) {
34065 -               SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, ("No mbuf.\n"))
34066 +               SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, ("No mbuf.\n"));
34067         }
34068         else if (pMb->pNext != NULL) {
34069                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34070 -                       ("More than one mbuf or pMb->pNext not set.\n"))
34071 +                       ("More than one mbuf or pMb->pNext not set.\n"));
34072         }
34073  #endif /* DEBUG */
34074
34075 @@ -2760,7 +2769,7 @@
34076         }
34077
34078         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34079 -               ("SK_RLMT_PACKET_RECEIVED Event END.\n"))
34080 +               ("SK_RLMT_PACKET_RECEIVED Event END.\n"));
34081  }      /* SkRlmtEvtPacketRx */
34082
34083
34084 @@ -2787,21 +2796,21 @@
34085         SK_RLMT_PORT    *pRPort;
34086
34087         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34088 -               ("SK_RLMT_STATS_CLEAR Event BEGIN.\n"))
34089 +               ("SK_RLMT_STATS_CLEAR Event BEGIN.\n"));
34090
34091         if (Para.Para32[1] != (SK_U32)-1) {
34092                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34093 -                       ("Bad Parameter.\n"))
34094 +                       ("Bad Parameter.\n"));
34095                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34096 -                       ("SK_RLMT_STATS_CLEAR Event EMPTY.\n"))
34097 +                       ("SK_RLMT_STATS_CLEAR Event EMPTY.\n"));
34098                 return;
34099         }
34100
34101         if (Para.Para32[0] >= pAC->Rlmt.NumNets) {
34102                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34103 -                       ("Bad NetNumber %d.\n", Para.Para32[0]))
34104 +                       ("Bad NetNumber %d.\n", Para.Para32[0]));
34105                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34106 -                       ("SK_RLMT_STATS_CLEAR Event EMPTY.\n"))
34107 +                       ("SK_RLMT_STATS_CLEAR Event EMPTY.\n"));
34108                 return;
34109         }
34110
34111 @@ -2816,7 +2825,7 @@
34112         }
34113
34114         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34115 -               ("SK_RLMT_STATS_CLEAR Event END.\n"))
34116 +               ("SK_RLMT_STATS_CLEAR Event END.\n"));
34117  }      /* SkRlmtEvtStatsClear */
34118
34119
34120 @@ -2840,28 +2849,28 @@
34121  SK_EVPARA      Para)   /* SK_U32 NetNumber; SK_U32 -1 */
34122  {
34123         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34124 -               ("SK_RLMT_STATS_UPDATE Event BEGIN.\n"))
34125 +               ("SK_RLMT_STATS_UPDATE Event BEGIN.\n"));
34126
34127         if (Para.Para32[1] != (SK_U32)-1) {
34128                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34129 -                       ("Bad Parameter.\n"))
34130 +                       ("Bad Parameter.\n"));
34131                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34132 -                       ("SK_RLMT_STATS_UPDATE Event EMPTY.\n"))
34133 +                       ("SK_RLMT_STATS_UPDATE Event EMPTY.\n"));
34134                 return;
34135         }
34136
34137         if (Para.Para32[0] >= pAC->Rlmt.NumNets) {
34138                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34139 -                       ("Bad NetNumber %d.\n", Para.Para32[0]))
34140 +                       ("Bad NetNumber %d.\n", Para.Para32[0]));
34141                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34142 -                       ("SK_RLMT_STATS_UPDATE Event EMPTY.\n"))
34143 +                       ("SK_RLMT_STATS_UPDATE Event EMPTY.\n"));
34144                 return;
34145         }
34146
34147         /* Update statistics - currently always up-to-date. */
34148
34149         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34150 -               ("SK_RLMT_STATS_UPDATE Event END.\n"))
34151 +               ("SK_RLMT_STATS_UPDATE Event END.\n"));
34152  }      /* SkRlmtEvtStatsUpdate */
34153
34154
34155 @@ -2885,13 +2894,13 @@
34156  SK_EVPARA      Para)   /* SK_U32 PortIndex; SK_U32 NetNumber */
34157  {
34158         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34159 -               ("SK_RLMT_PREFPORT_CHANGE to Port %d Event BEGIN.\n", Para.Para32[0]))
34160 +               ("SK_RLMT_PREFPORT_CHANGE to Port %d Event BEGIN.\n", Para.Para32[0]));
34161
34162         if (Para.Para32[1] >= pAC->Rlmt.NumNets) {
34163                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34164 -                       ("Bad NetNumber %d.\n", Para.Para32[1]))
34165 +                       ("Bad NetNumber %d.\n", Para.Para32[1]));
34166                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34167 -                       ("SK_RLMT_PREFPORT_CHANGE Event EMPTY.\n"))
34168 +                       ("SK_RLMT_PREFPORT_CHANGE Event EMPTY.\n"));
34169                 return;
34170         }
34171
34172 @@ -2904,7 +2913,7 @@
34173                         SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_RLMT_E010, SKERR_RLMT_E010_MSG);
34174
34175                         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34176 -                               ("SK_RLMT_PREFPORT_CHANGE Event EMPTY.\n"))
34177 +                               ("SK_RLMT_PREFPORT_CHANGE Event EMPTY.\n"));
34178                         return;
34179                 }
34180
34181 @@ -2918,7 +2927,7 @@
34182         }
34183
34184         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34185 -               ("SK_RLMT_PREFPORT_CHANGE Event END.\n"))
34186 +               ("SK_RLMT_PREFPORT_CHANGE Event END.\n"));
34187  }      /* SkRlmtEvtPrefportChange */
34188
34189
34190 @@ -2944,37 +2953,37 @@
34191         int i;
34192
34193         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34194 -               ("SK_RLMT_SET_NETS Event BEGIN.\n"))
34195 +               ("SK_RLMT_SET_NETS Event BEGIN.\n"));
34196
34197         if (Para.Para32[1] != (SK_U32)-1) {
34198                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34199 -                       ("Bad Parameter.\n"))
34200 +                       ("Bad Parameter.\n"));
34201                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34202 -                       ("SK_RLMT_SET_NETS Event EMPTY.\n"))
34203 +                       ("SK_RLMT_SET_NETS Event EMPTY.\n"));
34204                 return;
34205         }
34206
34207         if (Para.Para32[0] == 0 || Para.Para32[0] > SK_MAX_NETS ||
34208                 Para.Para32[0] > (SK_U32)pAC->GIni.GIMacsFound) {
34209                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34210 -                       ("Bad number of nets: %d.\n", Para.Para32[0]))
34211 +                       ("Bad number of nets: %d.\n", Para.Para32[0]));
34212                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34213 -                       ("SK_RLMT_SET_NETS Event EMPTY.\n"))
34214 +                       ("SK_RLMT_SET_NETS Event EMPTY.\n"));
34215                 return;
34216         }
34217
34218         if (Para.Para32[0] == pAC->Rlmt.NumNets) {      /* No change. */
34219                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34220 -                       ("SK_RLMT_SET_NETS Event EMPTY.\n"))
34221 +                       ("SK_RLMT_SET_NETS Event EMPTY.\n"));
34222                 return;
34223         }
34224
34225         /* Entering and leaving dual mode only allowed while nets are stopped. */
34226         if (pAC->Rlmt.NetsStarted > 0) {
34227                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34228 -                       ("Changing dual mode only allowed while all nets are stopped.\n"))
34229 +                       ("Changing dual mode only allowed while all nets are stopped.\n"));
34230                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34231 -                       ("SK_RLMT_SET_NETS Event EMPTY.\n"))
34232 +                       ("SK_RLMT_SET_NETS Event EMPTY.\n"));
34233                 return;
34234         }
34235
34236 @@ -3005,9 +3014,10 @@
34237                 SkEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_RLMT_SET_NETS, Para);
34238
34239                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34240 -                       ("RLMT: Changed to one net with two ports.\n"))
34241 +                       ("RLMT: Changed to one net with two ports.\n"));
34242         }
34243         else if (Para.Para32[0] == 2) {
34244 +               pAC->Rlmt.RlmtOff = SK_TRUE;
34245                 pAC->Rlmt.Port[1].Net= &pAC->Rlmt.Net[1];
34246                 pAC->Rlmt.Net[1].NumPorts = pAC->GIni.GIMacsFound - 1;
34247                 pAC->Rlmt.Net[0].NumPorts =
34248 @@ -3034,19 +3044,19 @@
34249                 SkEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_RLMT_SET_NETS, Para);
34250
34251                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34252 -                       ("RLMT: Changed to two nets with one port each.\n"))
34253 +                       ("RLMT: Changed to two nets with one port each.\n"));
34254         }
34255         else {
34256                 /* Not implemented for more than two nets. */
34257                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34258 -                       ("SetNets not implemented for more than two nets.\n"))
34259 +                       ("SetNets not implemented for more than two nets.\n"));
34260                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34261 -                       ("SK_RLMT_SET_NETS Event EMPTY.\n"))
34262 +                       ("SK_RLMT_SET_NETS Event EMPTY.\n"));
34263                 return;
34264         }
34265
34266         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34267 -               ("SK_RLMT_SET_NETS Event END.\n"))
34268 +               ("SK_RLMT_SET_NETS Event END.\n"));
34269  }      /* SkRlmtSetNets */
34270
34271
34272 @@ -3074,13 +3084,13 @@
34273         SK_U32          PrevRlmtMode;
34274
34275         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34276 -               ("SK_RLMT_MODE_CHANGE Event BEGIN.\n"))
34277 +               ("SK_RLMT_MODE_CHANGE Event BEGIN.\n"));
34278
34279         if (Para.Para32[1] >= pAC->Rlmt.NumNets) {
34280                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34281 -                       ("Bad NetNumber %d.\n", Para.Para32[1]))
34282 +                       ("Bad NetNumber %d.\n", Para.Para32[1]));
34283                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34284 -                       ("SK_RLMT_MODE_CHANGE Event EMPTY.\n"))
34285 +                       ("SK_RLMT_MODE_CHANGE Event EMPTY.\n"));
34286                 return;
34287         }
34288
34289 @@ -3090,9 +3100,9 @@
34290                 Para.Para32[0] != SK_RLMT_MODE_CLS) {
34291                 pAC->Rlmt.Net[Para.Para32[1]].RlmtMode = SK_RLMT_MODE_CLS;
34292                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34293 -                       ("Forced RLMT mode to CLS on single port net.\n"))
34294 +                       ("Forced RLMT mode to CLS on single port net.\n"));
34295                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34296 -                       ("SK_RLMT_MODE_CHANGE Event EMPTY.\n"))
34297 +                       ("SK_RLMT_MODE_CHANGE Event EMPTY.\n"));
34298                 return;
34299         }
34300
34301 @@ -3158,7 +3168,7 @@
34302         }       /* SK_RLMT_CHECK_SEG bit changed. */
34303
34304         SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34305 -                       ("SK_RLMT_MODE_CHANGE Event END.\n"))
34306 +                       ("SK_RLMT_MODE_CHANGE Event END.\n"));
34307  }      /* SkRlmtEvtModeChange */
34308
34309
34310 @@ -3244,7 +3254,7 @@
34311
34312         default:        /* Create error log entry. */
34313                 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34314 -                       ("Unknown RLMT Event %d.\n", Event))
34315 +                       ("Unknown RLMT Event %d.\n", Event));
34316                 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_RLMT_E003, SKERR_RLMT_E003_MSG);
34317                 break;
34318         }       /* switch() */
34319 diff -ruN linux/drivers/net/sk98lin/sktimer.c linux-new/drivers/net/sk98lin/sktimer.c
34320 --- linux/drivers/net/sk98lin/sktimer.c 2006-09-20 05:42:06.000000000 +0200
34321 +++ linux-new/drivers/net/sk98lin/sktimer.c     2006-07-28 14:13:54.000000000 +0200
34322 @@ -2,16 +2,17 @@
34323   *
34324   * Name:       sktimer.c
34325   * Project:    Gigabit Ethernet Adapters, Event Scheduler Module
34326 - * Version:    $Revision$
34327 - * Date:       $Date$
34328 + * Version:    $Revision$
34329 + * Date:       $Date$
34330   * Purpose:    High level timer functions.
34331   *
34332   ******************************************************************************/
34333
34334  /******************************************************************************
34335   *
34336 + *     LICENSE:
34337   *     (C)Copyright 1998-2002 SysKonnect GmbH.
34338 - *     (C)Copyright 2002-2003 Marvell.
34339 + *     (C)Copyright 2002-2004 Marvell.
34340   *
34341   *     This program is free software; you can redistribute it and/or modify
34342   *     it under the terms of the GNU General Public License as published by
34343 @@ -19,16 +20,16 @@
34344   *     (at your option) any later version.
34345   *
34346   *     The information in this file is provided "AS IS" without warranty.
34347 + *     /LICENSE
34348   *
34349   ******************************************************************************/
34350
34351 -
34352  /*
34353   *     Event queue and dispatcher
34354   */
34355  #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
34356  static const char SysKonnectFileId[] =
34357 -       "@(#) $Id$ (C) Marvell.";
34358 +       "@(#) $Id$ (C) Marvell.";
34359  #endif
34360
34361  #include "h/skdrv1st.h"                /* Driver Specific Definitions */
34362 @@ -62,7 +63,7 @@
34363  {
34364         switch (Level) {
34365         case SK_INIT_DATA:
34366 -               pAC->Tim.StQueue = NULL;
34367 +               pAC->Tim.StQueue = 0;
34368                 break;
34369         case SK_INIT_IO:
34370                 SkHwtInit(pAC, Ioc);
34371 @@ -85,22 +86,20 @@
34372         SK_TIMER        **ppTimPrev;
34373         SK_TIMER        *pTm;
34374
34375 -       /*
34376 -        * remove timer from queue
34377 -        */
34378 +       /* remove timer from queue */
34379         pTimer->TmActive = SK_FALSE;
34380 -
34381 +
34382         if (pAC->Tim.StQueue == pTimer && !pTimer->TmNext) {
34383                 SkHwtStop(pAC, Ioc);
34384         }
34385 -
34386 +
34387         for (ppTimPrev = &pAC->Tim.StQueue; (pTm = *ppTimPrev);
34388                 ppTimPrev = &pTm->TmNext ) {
34389 -
34390 +
34391                 if (pTm == pTimer) {
34392                         /*
34393                          * Timer found in queue
34394 -                        * - dequeue it and
34395 +                        * - dequeue it
34396                          * - correct delta of the next timer
34397                          */
34398                         *ppTimPrev = pTm->TmNext;
34399 @@ -121,7 +120,7 @@
34400  SK_AC          *pAC,           /* Adapters context */
34401  SK_IOC         Ioc,            /* IoContext */
34402  SK_TIMER       *pTimer,        /* Timer Pointer to be started */
34403 -SK_U32         Time,           /* Time value */
34404 +SK_U32         Time,           /* Time Value (in microsec.) */
34405  SK_U32         Class,          /* Event Class for this timer */
34406  SK_U32         Event,          /* Event Value for this timer */
34407  SK_EVPARA      Para)           /* Event Parameter for this timer */
34408 @@ -130,11 +129,6 @@
34409         SK_TIMER        *pTm;
34410         SK_U32          Delta;
34411
34412 -       Time /= 16;             /* input is uS, clock ticks are 16uS */
34413 -
34414 -       if (!Time)
34415 -               Time = 1;
34416 -
34417         SkTimerStop(pAC, Ioc, pTimer);
34418
34419         pTimer->TmClass = Class;
34420 @@ -143,31 +137,26 @@
34421         pTimer->TmActive = SK_TRUE;
34422
34423         if (!pAC->Tim.StQueue) {
34424 -               /* First Timer to be started */
34425 +               /* first Timer to be started */
34426                 pAC->Tim.StQueue = pTimer;
34427 -               pTimer->TmNext = NULL;
34428 +               pTimer->TmNext = 0;
34429                 pTimer->TmDelta = Time;
34430 -
34431 +
34432                 SkHwtStart(pAC, Ioc, Time);
34433 -
34434 +
34435                 return;
34436         }
34437
34438 -       /*
34439 -        * timer correction
34440 -        */
34441 +       /* timer correction */
34442         timer_done(pAC, Ioc, 0);
34443
34444 -       /*
34445 -        * find position in queue
34446 -        */
34447 +       /* find position in queue */
34448         Delta = 0;
34449         for (ppTimPrev = &pAC->Tim.StQueue; (pTm = *ppTimPrev);
34450                 ppTimPrev = &pTm->TmNext ) {
34451 -
34452 +
34453                 if (Delta + pTm->TmDelta > Time) {
34454 -                       /* Position found */
34455 -                       /* Here the timer needs to be inserted. */
34456 +                       /* the timer needs to be inserted here */
34457                         break;
34458                 }
34459                 Delta += pTm->TmDelta;
34460 @@ -179,9 +168,7 @@
34461         pTimer->TmDelta = Time - Delta;
34462
34463         if (pTm) {
34464 -               /* There is a next timer
34465 -                * -> correct its Delta value.
34466 -                */
34467 +               /* there is a next timer:  correct its Delta value */
34468                 pTm->TmDelta -= pTimer->TmDelta;
34469         }
34470
34471 @@ -210,7 +197,7 @@
34472         int             Done = 0;
34473
34474         Delta = SkHwtRead(pAC, Ioc);
34475 -
34476 +
34477         ppLast = &pAC->Tim.StQueue;
34478         pTm = pAC->Tim.StQueue;
34479         while (pTm && !Done) {
34480 @@ -228,13 +215,13 @@
34481                         Done = 1;
34482                 }
34483         }
34484 -       *ppLast = NULL;
34485 +       *ppLast = 0;
34486         /*
34487          * pTm points to the first Timer that did not run out.
34488          * StQueue points to the first Timer that run out.
34489          */
34490
34491 -       for ( pTComp = pAC->Tim.StQueue; pTComp; pTComp = pTComp->TmNext) {
34492 +       for (pTComp = pAC->Tim.StQueue; pTComp; pTComp = pTComp->TmNext) {
34493                 SkEventQueue(pAC,pTComp->TmClass, pTComp->TmEvent, pTComp->TmPara);
34494         }
34495
34496 diff -ruN linux/drivers/net/sk98lin/sktwsi.c linux-new/drivers/net/sk98lin/sktwsi.c
34497 --- linux/drivers/net/sk98lin/sktwsi.c  1970-01-01 01:00:00.000000000 +0100
34498 +++ linux-new/drivers/net/sk98lin/sktwsi.c      2006-07-28 14:13:54.000000000 +0200
34499 @@ -0,0 +1,1361 @@
34500 +/******************************************************************************
34501 + *
34502 + * Name:       sktwsi.c
34503 + * Project:    Gigabit Ethernet Adapters, TWSI-Module
34504 + * Version:    $Revision$
34505 + * Date:       $Date$
34506 + * Purpose:    Functions to access Voltage and Temperature Sensor
34507 + *
34508 + ******************************************************************************/
34509 +
34510 +/******************************************************************************
34511 + *
34512 + *     LICENSE:
34513 + *     (C)Copyright 1998-2002 SysKonnect.
34514 + *     (C)Copyright 2002-2005 Marvell.
34515 + *
34516 + *     This program is free software; you can redistribute it and/or modify
34517 + *     it under the terms of the GNU General Public License as published by
34518 + *     the Free Software Foundation; either version 2 of the License, or
34519 + *     (at your option) any later version.
34520 + *     The information in this file is provided "AS IS" without warranty.
34521 + *     /LICENSE
34522 + *
34523 + ******************************************************************************/
34524 +
34525 +/*
34526 + *     TWSI Protocol
34527 + */
34528 +#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
34529 +static const char SysKonnectFileId[] =
34530 +       "@(#) $Id$ (C) Marvell.";
34531 +#endif
34532 +
34533 +#include "h/skdrv1st.h"                /* Driver Specific Definitions */
34534 +#include "h/lm80.h"
34535 +#include "h/skdrv2nd.h"                /* Adapter Control- and Driver specific Def. */
34536 +
34537 +#ifdef __C2MAN__
34538 +/*
34539 +       TWSI protocol implementation.
34540 +
34541 +       General Description:
34542 +
34543 +       The TWSI protocol is used for the temperature sensors and for
34544 +       the serial EEPROM which hold the configuration.
34545 +
34546 +       This file covers functions that allow to read write and do
34547 +       some bulk requests a specified TWSI address.
34548 +
34549 +       The Genesis has 2 TWSI buses. One for the EEPROM which holds
34550 +       the VPD Data and one for temperature and voltage sensor.
34551 +       The following picture shows the TWSI buses, TWSI devices and
34552 +       their control registers.
34553 +
34554 +       Note: The VPD functions are in skvpd.c
34555 +.
34556 +.      PCI Config TWSI Bus for VPD Data:
34557 +.
34558 +.                    +------------+
34559 +.                    | VPD EEPROM |
34560 +.                    +------------+
34561 +.                           |
34562 +.                           | <-- TWSI
34563 +.                           |
34564 +.               +-----------+-----------+
34565 +.               |                       |
34566 +.      +-----------------+     +-----------------+
34567 +.      | PCI_VPD_ADR_REG |     | PCI_VPD_DAT_REG |
34568 +.      +-----------------+     +-----------------+
34569 +.
34570 +.
34571 +.      TWSI Bus for LM80 sensor:
34572 +.
34573 +.                      +-----------------+
34574 +.                      | Temperature and |
34575 +.                      | Voltage Sensor  |
34576 +.                      |       LM80      |
34577 +.                      +-----------------+
34578 +.                              |
34579 +.                              |
34580 +.                      TWSI --> |
34581 +.                              |
34582 +.                           +----+
34583 +.           +-------------->| OR |<--+
34584 +.           |               +----+   |
34585 +.     +------+------+                |
34586 +.     |                    |                 |
34587 +. +--------+   +--------+      +----------+
34588 +. | B2_I2C |   | B2_I2C |      |  B2_I2C  |
34589 +. | _CTRL  |   | _DATA  |      |   _SW    |
34590 +. +--------+   +--------+      +----------+
34591 +.
34592 +       The TWSI bus may be driven by the B2_I2C_SW or by the B2_I2C_CTRL
34593 +       and B2_I2C_DATA registers.
34594 +       For driver software it is recommended to use the TWSI control and
34595 +       data register, because TWSI bus timing is done by the ASIC and
34596 +       an interrupt may be received when the TWSI request is completed.
34597 +
34598 +       Clock Rate Timing:                      MIN     MAX     generated by
34599 +               VPD EEPROM:                     50 kHz  100 kHz         HW
34600 +               LM80 over TWSI Ctrl/Data reg.   50 kHz  100 kHz         HW
34601 +               LM80 over B2_I2C_SW register    0       400 kHz         SW
34602 +
34603 +       Note:   The clock generated by the hardware is dependend on the
34604 +               PCI clock. If the PCI bus clock is 33 MHz, the I2C/VPD
34605 +               clock is 50 kHz.
34606 + */
34607 +intro()
34608 +{}
34609 +#endif
34610 +
34611 +#ifdef SK_DIAG
34612 +/*
34613 + * TWSI Fast Mode timing values used by the LM80.
34614 + * If new devices are added to the TWSI bus the timing values have to be checked.
34615 + */
34616 +#ifndef I2C_SLOW_TIMING
34617 +#define T_CLK_LOW                      1300L   /* clock low time in ns */
34618 +#define T_CLK_HIGH                      600L   /* clock high time in ns */
34619 +#define T_DATA_IN_SETUP                 100L   /* data in Set-up Time */
34620 +#define T_START_HOLD            600L   /* start condition hold time */
34621 +#define T_START_SETUP           600L   /* start condition Set-up time */
34622 +#define T_STOP_SETUP            600L   /* stop condition Set-up time */
34623 +#define T_BUS_IDLE                     1300L   /* time the bus must free after Tx */
34624 +#define T_CLK_2_DATA_OUT        900L   /* max. clock low to data output valid */
34625 +#else  /* I2C_SLOW_TIMING */
34626 +/* TWSI Standard Mode Timing */
34627 +#define T_CLK_LOW                      4700L   /* clock low time in ns */
34628 +#define T_CLK_HIGH                     4000L   /* clock high time in ns */
34629 +#define T_DATA_IN_SETUP                 250L   /* data in Set-up Time */
34630 +#define T_START_HOLD           4000L   /* start condition hold time */
34631 +#define T_START_SETUP          4700L   /* start condition Set-up time */
34632 +#define T_STOP_SETUP           4000L   /* stop condition Set-up time */
34633 +#define T_BUS_IDLE                     4700L   /* time the bus must free after Tx */
34634 +#endif /* !I2C_SLOW_TIMING */
34635 +
34636 +#define NS2BCLK(x)     (((x)*125)/10000)
34637 +
34638 +/*
34639 + * TWSI Wire Operations
34640 + *
34641 + * About I2C_CLK_LOW():
34642 + *
34643 + * The Data Direction bit (I2C_DATA_DIR) has to be set to input when setting
34644 + * clock to low, to prevent the ASIC and the TWSI data client from driving the
34645 + * serial data line simultaneously (ASIC: last bit of a byte = '1', TWSI client
34646 + * send an 'ACK'). See also Concentrator Bugreport No. 10192.
34647 + */
34648 +#define I2C_DATA_HIGH(IoC)     SK_I2C_SET_BIT(IoC, I2C_DATA)
34649 +#define I2C_DATA_LOW(IoC)      SK_I2C_CLR_BIT(IoC, I2C_DATA)
34650 +#define I2C_DATA_OUT(IoC)      SK_I2C_SET_BIT(IoC, I2C_DATA_DIR)
34651 +#define I2C_DATA_IN(IoC)       SK_I2C_CLR_BIT(IoC, I2C_DATA_DIR | I2C_DATA)
34652 +#define I2C_CLK_HIGH(IoC)      SK_I2C_SET_BIT(IoC, I2C_CLK)
34653 +#define I2C_CLK_LOW(IoC)       SK_I2C_CLR_BIT(IoC, I2C_CLK | I2C_DATA_DIR)
34654 +#define I2C_START_COND(IoC)    SK_I2C_CLR_BIT(IoC, I2C_CLK)
34655 +
34656 +#define NS2CLKT(x)     ((x*125L)/10000)
34657 +
34658 +/*--------------- TWSI Interface Register Functions --------------- */
34659 +
34660 +/*
34661 + * sending one bit
34662 + */
34663 +void SkI2cSndBit(
34664 +SK_IOC IoC,    /* I/O Context */
34665 +SK_U8  Bit)    /* Bit to send */
34666 +{
34667 +       I2C_DATA_OUT(IoC);
34668 +       if (Bit) {
34669 +               I2C_DATA_HIGH(IoC);
34670 +       }
34671 +       else {
34672 +               I2C_DATA_LOW(IoC);
34673 +       }
34674 +       SkDgWaitTime(IoC, NS2BCLK(T_DATA_IN_SETUP));
34675 +       I2C_CLK_HIGH(IoC);
34676 +       SkDgWaitTime(IoC, NS2BCLK(T_CLK_HIGH));
34677 +       I2C_CLK_LOW(IoC);
34678 +}      /* SkI2cSndBit*/
34679 +
34680 +
34681 +/*
34682 + * Signal a start to the TWSI Bus.
34683 + *
34684 + * A start is signaled when data goes to low in a high clock cycle.
34685 + *
34686 + * Ends with Clock Low.
34687 + *
34688 + * Status: not tested
34689 + */
34690 +void SkI2cStart(
34691 +SK_IOC IoC)    /* I/O Context */
34692 +{
34693 +       /* Init data and Clock to output lines */
34694 +       /* Set Data high */
34695 +       I2C_DATA_OUT(IoC);
34696 +       I2C_DATA_HIGH(IoC);
34697 +       /* Set Clock high */
34698 +       I2C_CLK_HIGH(IoC);
34699 +
34700 +       SkDgWaitTime(IoC, NS2BCLK(T_START_SETUP));
34701 +
34702 +       /* Set Data Low */
34703 +       I2C_DATA_LOW(IoC);
34704 +
34705 +       SkDgWaitTime(IoC, NS2BCLK(T_START_HOLD));
34706 +
34707 +       /* Clock low without Data to Input */
34708 +       I2C_START_COND(IoC);
34709 +
34710 +       SkDgWaitTime(IoC, NS2BCLK(T_CLK_LOW));
34711 +}      /* SkI2cStart */
34712 +
34713 +
34714 +void SkI2cStop(
34715 +SK_IOC IoC)    /* I/O Context */
34716 +{
34717 +       /* Init data and Clock to output lines */
34718 +       /* Set Data low */
34719 +       I2C_DATA_OUT(IoC);
34720 +       I2C_DATA_LOW(IoC);
34721 +
34722 +       SkDgWaitTime(IoC, NS2BCLK(T_CLK_2_DATA_OUT));
34723 +
34724 +       /* Set Clock high */
34725 +       I2C_CLK_HIGH(IoC);
34726 +
34727 +       SkDgWaitTime(IoC, NS2BCLK(T_STOP_SETUP));
34728 +
34729 +       /*
34730 +        * Set Data High:       Do it by setting the Data Line to Input.
34731 +        *                      Because of a pull up resistor the Data Line
34732 +        *                      floods to high.
34733 +        */
34734 +       I2C_DATA_IN(IoC);
34735 +
34736 +       /*
34737 +        *      When TWSI activity is stopped
34738 +        *       o      DATA should be set to input and
34739 +        *       o      CLOCK should be set to high!
34740 +        */
34741 +       SkDgWaitTime(IoC, NS2BCLK(T_BUS_IDLE));
34742 +}      /* SkI2cStop */
34743 +
34744 +
34745 +/*
34746 + * Receive just one bit via the TWSI bus.
34747 + *
34748 + * Note:       Clock must be set to LOW before calling this function.
34749 + *
34750 + * Returns The received bit.
34751 + */
34752 +int SkI2cRcvBit(
34753 +SK_IOC IoC)    /* I/O Context */
34754 +{
34755 +       int     Bit;
34756 +       SK_U8   I2cSwCtrl;
34757 +
34758 +       /* Init data as input line */
34759 +       I2C_DATA_IN(IoC);
34760 +
34761 +       SkDgWaitTime(IoC, NS2BCLK(T_CLK_2_DATA_OUT));
34762 +
34763 +       I2C_CLK_HIGH(IoC);
34764 +
34765 +       SkDgWaitTime(IoC, NS2BCLK(T_CLK_HIGH));
34766 +
34767 +       SK_I2C_GET_SW(IoC, &I2cSwCtrl);
34768 +
34769 +       Bit = (I2cSwCtrl & I2C_DATA) ? 1 : 0;
34770 +
34771 +       I2C_CLK_LOW(IoC);
34772 +       SkDgWaitTime(IoC, NS2BCLK(T_CLK_LOW-T_CLK_2_DATA_OUT));
34773 +
34774 +       return(Bit);
34775 +}      /* SkI2cRcvBit */
34776 +
34777 +
34778 +/*
34779 + * Receive an ACK.
34780 + *
34781 + * returns     0 If acknowledged
34782 + *             1 in case of an error
34783 + */
34784 +int SkI2cRcvAck(
34785 +SK_IOC IoC)    /* I/O Context */
34786 +{
34787 +       /*
34788 +        * Received bit must be zero.
34789 +        */
34790 +       return(SkI2cRcvBit(IoC) != 0);
34791 +}      /* SkI2cRcvAck */
34792 +
34793 +
34794 +/*
34795 + * Send an NACK.
34796 + */
34797 +void SkI2cSndNAck(
34798 +SK_IOC IoC)    /* I/O Context */
34799 +{
34800 +       /*
34801 +        * Received bit must be zero.
34802 +        */
34803 +       SkI2cSndBit(IoC, 1);
34804 +}      /* SkI2cSndNAck */
34805 +
34806 +
34807 +/*
34808 + * Send an ACK.
34809 + */
34810 +void SkI2cSndAck(
34811 +SK_IOC IoC)    /* I/O Context */
34812 +{
34813 +       /*
34814 +        * Received bit must be zero.
34815 +        */
34816 +       SkI2cSndBit(IoC, 0);
34817 +}      /* SkI2cSndAck */
34818 +
34819 +
34820 +/*
34821 + * Send one byte to the TWSI device and wait for ACK.
34822 + *
34823 + * Return acknowleged status.
34824 + */
34825 +int SkI2cSndByte(
34826 +SK_IOC IoC,    /* I/O Context */
34827 +int            Byte)   /* byte to send */
34828 +{
34829 +       int     i;
34830 +
34831 +       for (i = 0; i < 8; i++) {
34832 +               if (Byte & (1<<(7-i))) {
34833 +                       SkI2cSndBit(IoC, 1);
34834 +               }
34835 +               else {
34836 +                       SkI2cSndBit(IoC, 0);
34837 +               }
34838 +       }
34839 +
34840 +       return(SkI2cRcvAck(IoC));
34841 +}      /* SkI2cSndByte */
34842 +
34843 +
34844 +/*
34845 + * Receive one byte and ack it.
34846 + *
34847 + * Return byte.
34848 + */
34849 +int SkI2cRcvByte(
34850 +SK_IOC IoC,    /* I/O Context */
34851 +int            Last)   /* Last Byte Flag */
34852 +{
34853 +       int     i;
34854 +       int     Byte = 0;
34855 +
34856 +       for (i = 0; i < 8; i++) {
34857 +               Byte <<= 1;
34858 +               Byte |= SkI2cRcvBit(IoC);
34859 +       }
34860 +
34861 +       if (Last) {
34862 +               SkI2cSndNAck(IoC);
34863 +       }
34864 +       else {
34865 +               SkI2cSndAck(IoC);
34866 +       }
34867 +
34868 +       return(Byte);
34869 +}      /* SkI2cRcvByte */
34870 +
34871 +
34872 +/*
34873 + * Start dialog and send device address
34874 + *
34875 + * Return 0 if acknowleged, 1 in case of an error
34876 + */
34877 +int SkI2cSndDev(
34878 +SK_IOC IoC,    /* I/O Context */
34879 +int            Addr,   /* Device Address */
34880 +int            Rw)             /* Read / Write Flag */
34881 +{
34882 +       SkI2cStart(IoC);
34883 +       Rw = ~Rw;
34884 +       Rw &= I2C_WRITE;
34885 +       return(SkI2cSndByte(IoC, (Addr << 1) | Rw));
34886 +}      /* SkI2cSndDev */
34887 +
34888 +#endif /* SK_DIAG */
34889 +
34890 +/*----------------- TWSI CTRL Register Functions ----------*/
34891 +
34892 +/*
34893 + * waits for a completion of a TWSI transfer
34894 + *
34895 + * returns     0:      success, transfer completes
34896 + *                     1:      error,   transfer does not complete, TWSI transfer
34897 + *                                              killed, wait loop terminated.
34898 + */
34899 +int SkI2cWait(
34900 +SK_AC  *pAC,   /* Adapter Context */
34901 +SK_IOC IoC,    /* I/O Context */
34902 +int            Event)  /* complete event to wait for (I2C_READ or I2C_WRITE) */
34903 +{
34904 +       SK_U64  StartTime;
34905 +       SK_U64  CurrentTime;
34906 +       SK_U32  I2cCtrl;
34907 +
34908 +       StartTime = SkOsGetTime(pAC);
34909 +
34910 +       do {
34911 +               CurrentTime = SkOsGetTime(pAC);
34912 +
34913 +               if (CurrentTime - StartTime > SK_TICKS_PER_SEC / 8) {
34914 +
34915 +                       SK_I2C_STOP(IoC);
34916 +#ifndef SK_DIAG
34917 +                       if (pAC->I2c.InitLevel > SK_INIT_DATA) {
34918 +                               SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E002, SKERR_I2C_E002MSG);
34919 +                       }
34920 +#endif /* !SK_DIAG */
34921 +                       return(1);
34922 +               }
34923 +
34924 +               SK_I2C_GET_CTL(IoC, &I2cCtrl);
34925 +
34926 +#ifdef xYUKON_DBG
34927 +               printf("StartTime=%lu, CurrentTime=%lu\n",
34928 +                       StartTime, CurrentTime);
34929 +               if (kbhit()) {
34930 +                       return(1);
34931 +               }
34932 +#endif /* YUKON_DBG */
34933 +
34934 +       } while ((I2cCtrl & I2C_FLAG) == (SK_U32)Event << 31);
34935 +
34936 +       return(0);
34937 +}      /* SkI2cWait */
34938 +
34939 +
34940 +/*
34941 + * waits for a completion of a TWSI transfer
34942 + *
34943 + * Returns
34944 + *     Nothing
34945 + */
34946 +void SkI2cWaitIrq(
34947 +SK_AC  *pAC,   /* Adapter Context */
34948 +SK_IOC IoC)    /* I/O Context */
34949 +{
34950 +       SK_SENSOR       *pSen;
34951 +       SK_U64          StartTime;
34952 +       SK_U32          IrqSrc;
34953 +       SK_U32          IsTwsiReadyBit;
34954 +
34955 +       pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
34956 +
34957 +       if (pSen->SenState == SK_SEN_IDLE) {
34958 +               return;
34959 +       }
34960 +
34961 +       IsTwsiReadyBit = CHIP_ID_YUKON_2(pAC) ? Y2_IS_TWSI_RDY : IS_I2C_READY;
34962 +
34963 +       StartTime = SkOsGetTime(pAC);
34964 +
34965 +       do {
34966 +               if (SkOsGetTime(pAC) - StartTime > SK_TICKS_PER_SEC / 8) {
34967 +
34968 +                       SK_I2C_STOP(IoC);
34969 +#ifndef SK_DIAG
34970 +                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E016, SKERR_I2C_E016MSG);
34971 +#endif /* !SK_DIAG */
34972 +                       return;
34973 +               }
34974 +
34975 +               SK_IN32(IoC, B0_ISRC, &IrqSrc);
34976 +
34977 +       } while ((IrqSrc & IsTwsiReadyBit) == 0);
34978 +
34979 +       pSen->SenState = SK_SEN_IDLE;
34980 +       return;
34981 +}      /* SkI2cWaitIrq */
34982 +
34983 +/*
34984 + * writes a single byte or 4 bytes into the TWSI device
34985 + *
34986 + * returns     0:      success
34987 + *                     1:      error
34988 + */
34989 +int SkI2cWrite(
34990 +SK_AC  *pAC,           /* Adapter Context */
34991 +SK_IOC IoC,            /* I/O Context */
34992 +SK_U32 I2cData,        /* TWSI Data to write */
34993 +int            I2cDev,         /* TWSI Device Address */
34994 +int            I2cDevSize,     /* TWSI Device Size (e.g. I2C_025K_DEV or I2C_2K_DEV) */
34995 +int            I2cReg,         /* TWSI Device Register Address */
34996 +int            I2cBurst)       /* TWSI Burst Flag */
34997 +{
34998 +       SK_OUT32(IoC, B2_I2C_DATA, I2cData);
34999 +
35000 +       SK_I2C_CTL(IoC, I2C_WRITE, I2cDev, I2cDevSize, I2cReg, I2cBurst);
35001 +
35002 +       return(SkI2cWait(pAC, IoC, I2C_WRITE));
35003 +}      /* SkI2cWrite*/
35004 +
35005 +
35006 +#ifdef SK_DIAG
35007 +/*
35008 + * reads a single byte or 4 bytes from the TWSI device
35009 + *
35010 + * returns     the word read
35011 + */
35012 +SK_U32 SkI2cRead(
35013 +SK_AC  *pAC,           /* Adapter Context */
35014 +SK_IOC IoC,            /* I/O Context */
35015 +int            I2cDev,         /* TWSI Device Address */
35016 +int            I2cDevSize,     /* TWSI Device Size (e.g. I2C_025K_DEV or I2C_2K_DEV) */
35017 +int            I2cReg,         /* TWSI Device Register Address */
35018 +int            I2cBurst)       /* TWSI Burst Flag */
35019 +{
35020 +       SK_U32  Data;
35021 +
35022 +       SK_OUT32(IoC, B2_I2C_DATA, 0);
35023 +
35024 +       SK_I2C_CTL(IoC, I2C_READ, I2cDev, I2cDevSize, I2cReg, I2cBurst);
35025 +
35026 +       if (SkI2cWait(pAC, IoC, I2C_READ) != 0) {
35027 +               w_print("%s\n", SKERR_I2C_E002MSG);
35028 +       }
35029 +
35030 +       SK_IN32(IoC, B2_I2C_DATA, &Data);
35031 +
35032 +       return(Data);
35033 +}      /* SkI2cRead */
35034 +#endif /* SK_DIAG */
35035 +
35036 +
35037 +/*
35038 + * read a sensor's value
35039 + *
35040 + * This function reads a sensor's value from the TWSI sensor chip. The sensor
35041 + * is defined by its index into the sensors database in the struct pAC points
35042 + * to.
35043 + * Returns
35044 + *             1 if the read is completed
35045 + *             0 if the read must be continued (TWSI Bus still allocated)
35046 + */
35047 +int SkI2cReadSensor(
35048 +SK_AC          *pAC,   /* Adapter Context */
35049 +SK_IOC         IoC,    /* I/O Context */
35050 +SK_SENSOR      *pSen)  /* Sensor to be read */
35051 +{
35052 +       if (pSen->SenRead != NULL) {
35053 +               return((*pSen->SenRead)(pAC, IoC, pSen));
35054 +       }
35055 +
35056 +       return(0); /* no success */
35057 +}      /* SkI2cReadSensor */
35058 +
35059 +/*
35060 + * Do the Init state 0 initialization
35061 + */
35062 +static int SkI2cInit0(
35063 +SK_AC  *pAC)   /* Adapter Context */
35064 +{
35065 +       int                     i;
35066 +       SK_SENSOR       *pSen;
35067 +
35068 +       /* Begin with first sensor */
35069 +       pAC->I2c.CurrSens = 0;
35070 +
35071 +       /* Begin with timeout control for state machine */
35072 +       pAC->I2c.TimerMode = SK_TIMER_WATCH_SM;
35073 +
35074 +       /* Set sensor number to zero */
35075 +       pAC->I2c.MaxSens = 0;
35076 +
35077 +#ifndef SK_DIAG
35078 +       /* Initialize Number of Dummy Reads */
35079 +       pAC->I2c.DummyReads = SK_MAX_SENSORS;
35080 +#endif /* !SK_DIAG */
35081 +
35082 +       for (i = 0; i < SK_MAX_SENSORS; i++) {
35083 +               pSen = &pAC->I2c.SenTable[i];
35084 +
35085 +               pSen->SenDesc = "unknown";
35086 +               pSen->SenType = SK_SEN_UNKNOWN;
35087 +               pSen->SenThreErrHigh = 0;
35088 +               pSen->SenThreErrLow = 0;
35089 +               pSen->SenThreWarnHigh = 0;
35090 +               pSen->SenThreWarnLow = 0;
35091 +               pSen->SenReg = LM80_FAN2_IN;
35092 +               pSen->SenInit = SK_SEN_DYN_INIT_NONE;
35093 +               pSen->SenValue = 0;
35094 +               pSen->SenErrFlag = SK_SEN_ERR_NOT_PRESENT;
35095 +               pSen->SenErrCts = 0;
35096 +               pSen->SenBegErrTS = 0;
35097 +               pSen->SenState = SK_SEN_IDLE;
35098 +               pSen->SenRead = NULL;
35099 +               pSen->SenDev = 0;
35100 +       }
35101 +
35102 +       /* Now we are "INIT data"ed */
35103 +       pAC->I2c.InitLevel = SK_INIT_DATA;
35104 +       return(0);
35105 +}      /* SkI2cInit0*/
35106 +
35107 +
35108 +/*
35109 + * Do the init state 1 initialization
35110 + *
35111 + * initialize the following register of the LM80:
35112 + * Configuration register:
35113 + * - START, noINT, activeLOW, noINT#Clear, noRESET, noCI, noGPO#, noINIT
35114 + *
35115 + * Interrupt Mask Register 1:
35116 + * - all interrupts are Disabled (0xff)
35117 + *
35118 + * Interrupt Mask Register 2:
35119 + * - all interrupts are Disabled (0xff) Interrupt modi doesn't matter.
35120 + *
35121 + * Fan Divisor/RST_OUT register:
35122 + * - Divisors set to 1 (bits 00), all others 0s.
35123 + *
35124 + * OS# Configuration/Temperature resolution Register:
35125 + * - all 0s
35126 + *
35127 + */
35128 +static int SkI2cInit1(
35129 +SK_AC  *pAC,   /* Adapter Context */
35130 +SK_IOC IoC)    /* I/O Context */
35131 +{
35132 +       int                     i;
35133 +       SK_U8           I2cSwCtrl;
35134 +       SK_GEPORT       *pPrt;  /* GIni Port struct pointer */
35135 +       SK_SENSOR       *pSen;
35136 +
35137 +       if (pAC->I2c.InitLevel != SK_INIT_DATA) {
35138 +               /* Re-init not needed in TWSI module */
35139 +               return(0);
35140 +       }
35141 +
35142 +       if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC ||
35143 +               pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) {
35144 +               /* No sensors on Yukon-EC and Yukon-FE */
35145 +               return(0);
35146 +       }
35147 +
35148 +       /* Set the Direction of TWSI-Data Pin to IN */
35149 +       SK_I2C_CLR_BIT(IoC, I2C_DATA_DIR | I2C_DATA);
35150 +
35151 +       /* Check for 32-Bit Yukon with Low at TWSI-Data Pin */
35152 +       SK_I2C_GET_SW(IoC, &I2cSwCtrl);
35153 +
35154 +       if ((I2cSwCtrl & I2C_DATA) == 0) {
35155 +               /* this is a 32-Bit board */
35156 +               pAC->GIni.GIYukon32Bit = SK_TRUE;
35157 +               return(0);
35158 +       }
35159 +
35160 +       /* Check for 64 Bit Yukon without sensors */
35161 +       if (SkI2cWrite(pAC, IoC, 0, LM80_ADDR, I2C_025K_DEV, LM80_CFG, 0) != 0) {
35162 +               return(0);
35163 +       }
35164 +
35165 +       (void)SkI2cWrite(pAC, IoC, 0xffUL, LM80_ADDR, I2C_025K_DEV, LM80_IMSK_1, 0);
35166 +
35167 +       (void)SkI2cWrite(pAC, IoC, 0xffUL, LM80_ADDR, I2C_025K_DEV, LM80_IMSK_2, 0);
35168 +
35169 +       (void)SkI2cWrite(pAC, IoC, 0, LM80_ADDR, I2C_025K_DEV, LM80_FAN_CTRL, 0);
35170 +
35171 +       (void)SkI2cWrite(pAC, IoC, 0, LM80_ADDR, I2C_025K_DEV, LM80_TEMP_CTRL, 0);
35172 +
35173 +       (void)SkI2cWrite(pAC, IoC, (SK_U32)LM80_CFG_START, LM80_ADDR, I2C_025K_DEV,
35174 +               LM80_CFG, 0);
35175 +
35176 +       /*
35177 +        * MaxSens has to be updated here, because PhyType is not
35178 +        * set when performing Init Level 0
35179 +        */
35180 +       pAC->I2c.MaxSens = 5;
35181 +
35182 +       pPrt = &pAC->GIni.GP[0];
35183 +
35184 +       if (pAC->GIni.GIGenesis) {
35185 +               if (pPrt->PhyType == SK_PHY_BCOM) {
35186 +                       if (pAC->GIni.GIMacsFound == 1) {
35187 +                               pAC->I2c.MaxSens += 1;
35188 +                       }
35189 +                       else {
35190 +                               pAC->I2c.MaxSens += 3;
35191 +                       }
35192 +               }
35193 +       }
35194 +       else {
35195 +               pAC->I2c.MaxSens += 3;
35196 +       }
35197 +
35198 +       for (i = 0; i < pAC->I2c.MaxSens; i++) {
35199 +               pSen = &pAC->I2c.SenTable[i];
35200 +               switch (i) {
35201 +               case 0:
35202 +                       pSen->SenDesc = "Temperature";
35203 +                       pSen->SenType = SK_SEN_TEMP;
35204 +                       pSen->SenThreErrHigh = SK_SEN_TEMP_HIGH_ERR;
35205 +                       pSen->SenThreWarnHigh = SK_SEN_TEMP_HIGH_WARN;
35206 +                       pSen->SenThreWarnLow = SK_SEN_TEMP_LOW_WARN;
35207 +                       pSen->SenThreErrLow = SK_SEN_TEMP_LOW_ERR;
35208 +                       pSen->SenReg = LM80_TEMP_IN;
35209 +                       break;
35210 +               case 1:
35211 +                       pSen->SenDesc = "Voltage PCI";
35212 +                       pSen->SenType = SK_SEN_VOLT;
35213 +                       pSen->SenThreErrHigh = SK_SEN_PCI_5V_HIGH_ERR;
35214 +                       pSen->SenThreWarnHigh = SK_SEN_PCI_5V_HIGH_WARN;
35215 +                       if (pAC->GIni.GIPciBus != SK_PEX_BUS) {
35216 +                               pSen->SenThreWarnLow = SK_SEN_PCI_5V_LOW_WARN;
35217 +                               pSen->SenThreErrLow = SK_SEN_PCI_5V_LOW_ERR;
35218 +                       }
35219 +                       else {
35220 +                               pSen->SenThreWarnLow = 0;
35221 +                               pSen->SenThreErrLow = 0;
35222 +                       }
35223 +                       pSen->SenReg = LM80_VT0_IN;
35224 +                       break;
35225 +               case 2:
35226 +                       pSen->SenDesc = "Voltage PCI-IO";
35227 +                       pSen->SenType = SK_SEN_VOLT;
35228 +                       pSen->SenThreErrHigh = SK_SEN_PCI_IO_5V_HIGH_ERR;
35229 +                       pSen->SenThreWarnHigh = SK_SEN_PCI_IO_5V_HIGH_WARN;
35230 +                       if (pAC->GIni.GIPciBus != SK_PEX_BUS) {
35231 +                               pSen->SenThreWarnLow = SK_SEN_PCI_IO_3V3_LOW_WARN;
35232 +                               pSen->SenThreErrLow = SK_SEN_PCI_IO_3V3_LOW_ERR;
35233 +                       }
35234 +                       else {
35235 +                               pSen->SenThreWarnLow = 0;
35236 +                               pSen->SenThreErrLow = 0;
35237 +                       }
35238 +                       pSen->SenReg = LM80_VT1_IN;
35239 +                       pSen->SenInit = SK_SEN_DYN_INIT_PCI_IO;
35240 +                       break;
35241 +               case 3:
35242 +                       if (pAC->GIni.GIGenesis) {
35243 +                               pSen->SenDesc = "Voltage ASIC";
35244 +                       }
35245 +                       else {
35246 +                               pSen->SenDesc = "Voltage VMAIN";
35247 +                       }
35248 +                       pSen->SenType = SK_SEN_VOLT;
35249 +                       pSen->SenThreErrHigh = SK_SEN_VDD_HIGH_ERR;
35250 +                       pSen->SenThreWarnHigh = SK_SEN_VDD_HIGH_WARN;
35251 +                       pSen->SenThreWarnLow = SK_SEN_VDD_LOW_WARN;
35252 +                       pSen->SenThreErrLow = SK_SEN_VDD_LOW_ERR;
35253 +                       pSen->SenReg = LM80_VT2_IN;
35254 +                       break;
35255 +               case 4:
35256 +                       if (pAC->GIni.GIGenesis) {
35257 +                               if (pPrt->PhyType == SK_PHY_BCOM) {
35258 +                                       pSen->SenDesc = "Voltage PHY A PLL";
35259 +                                       pSen->SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR;
35260 +                                       pSen->SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN;
35261 +                                       pSen->SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN;
35262 +                                       pSen->SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR;
35263 +                               }
35264 +                               else {
35265 +                                       pSen->SenDesc = "Voltage PMA";
35266 +                                       pSen->SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR;
35267 +                                       pSen->SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN;
35268 +                                       pSen->SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN;
35269 +                                       pSen->SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR;
35270 +                               }
35271 +                       }
35272 +                       else {
35273 +                               pSen->SenDesc = "Voltage VAUX";
35274 +                               pSen->SenThreErrHigh = SK_SEN_VAUX_3V3_HIGH_ERR;
35275 +                               pSen->SenThreWarnHigh = SK_SEN_VAUX_3V3_HIGH_WARN;
35276 +                               if (pAC->GIni.GIVauxAvail) {
35277 +                                       pSen->SenThreWarnLow = SK_SEN_VAUX_3V3_LOW_WARN;
35278 +                                       pSen->SenThreErrLow = SK_SEN_VAUX_3V3_LOW_ERR;
35279 +                               }
35280 +                               else {
35281 +                                       pSen->SenThreErrLow = 0;
35282 +                                       pSen->SenThreWarnLow = 0;
35283 +                               }
35284 +                       }
35285 +                       pSen->SenType = SK_SEN_VOLT;
35286 +                       pSen->SenReg = LM80_VT3_IN;
35287 +                       break;
35288 +               case 5:
35289 +                       if (CHIP_ID_YUKON_2(pAC)) {
35290 +                               if (pAC->GIni.GIChipRev == CHIP_REV_YU_XL_A0) {
35291 +                                       pSen->SenDesc = "Voltage Core 1V3";
35292 +                                       pSen->SenThreErrHigh = SK_SEN_CORE_1V3_HIGH_ERR;
35293 +                                       pSen->SenThreWarnHigh = SK_SEN_CORE_1V3_HIGH_WARN;
35294 +                                       pSen->SenThreWarnLow = SK_SEN_CORE_1V3_LOW_WARN;
35295 +                                       pSen->SenThreErrLow = SK_SEN_CORE_1V3_LOW_ERR;
35296 +                               }
35297 +                               else {
35298 +                                       pSen->SenDesc = "Voltage Core 1V2";
35299 +                                       pSen->SenThreErrHigh = SK_SEN_CORE_1V2_HIGH_ERR;
35300 +                                       pSen->SenThreWarnHigh = SK_SEN_CORE_1V2_HIGH_WARN;
35301 +                                       pSen->SenThreWarnLow = SK_SEN_CORE_1V2_LOW_WARN;
35302 +                                       pSen->SenThreErrLow = SK_SEN_CORE_1V2_LOW_ERR;
35303 +                               }
35304 +                       }
35305 +                       else {
35306 +                               if (pAC->GIni.GIGenesis) {
35307 +                                       pSen->SenDesc = "Voltage PHY 2V5";
35308 +                                       pSen->SenThreErrHigh = SK_SEN_PHY_2V5_HIGH_ERR;
35309 +                                       pSen->SenThreWarnHigh = SK_SEN_PHY_2V5_HIGH_WARN;
35310 +                                       pSen->SenThreWarnLow = SK_SEN_PHY_2V5_LOW_WARN;
35311 +                                       pSen->SenThreErrLow = SK_SEN_PHY_2V5_LOW_ERR;
35312 +                               }
35313 +                               else {
35314 +                                       pSen->SenDesc = "Voltage Core 1V5";
35315 +                                       pSen->SenThreErrHigh = SK_SEN_CORE_1V5_HIGH_ERR;
35316 +                                       pSen->SenThreWarnHigh = SK_SEN_CORE_1V5_HIGH_WARN;
35317 +                                       pSen->SenThreWarnLow = SK_SEN_CORE_1V5_LOW_WARN;
35318 +                                       pSen->SenThreErrLow = SK_SEN_CORE_1V5_LOW_ERR;
35319 +                               }
35320 +                       }
35321 +                       pSen->SenType = SK_SEN_VOLT;
35322 +                       pSen->SenReg = LM80_VT4_IN;
35323 +                       break;
35324 +               case 6:
35325 +                       if (CHIP_ID_YUKON_2(pAC)) {
35326 +                               pSen->SenDesc = "Voltage PHY 1V5";
35327 +                               pSen->SenThreErrHigh = SK_SEN_CORE_1V5_HIGH_ERR;
35328 +                               pSen->SenThreWarnHigh = SK_SEN_CORE_1V5_HIGH_WARN;
35329 +                               if (pAC->GIni.GIPciBus == SK_PEX_BUS) {
35330 +                                       pSen->SenThreWarnLow = SK_SEN_CORE_1V5_LOW_WARN;
35331 +                                       pSen->SenThreErrLow = SK_SEN_CORE_1V5_LOW_ERR;
35332 +                               }
35333 +                               else {
35334 +                                       pSen->SenThreWarnLow = 0;
35335 +                                       pSen->SenThreErrLow = 0;
35336 +                               }
35337 +                       }
35338 +                       else {
35339 +                               if (pAC->GIni.GIGenesis) {
35340 +                                       pSen->SenDesc = "Voltage PHY B PLL";
35341 +                               }
35342 +                               else {
35343 +                                       pSen->SenDesc = "Voltage PHY 3V3";
35344 +                               }
35345 +                               pSen->SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR;
35346 +                               pSen->SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN;
35347 +                               pSen->SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN;
35348 +                               pSen->SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR;
35349 +                       }
35350 +                       pSen->SenType = SK_SEN_VOLT;
35351 +                       pSen->SenReg = LM80_VT5_IN;
35352 +                       break;
35353 +               case 7:
35354 +                       if (pAC->GIni.GIGenesis) {
35355 +                               pSen->SenDesc = "Speed Fan";
35356 +                               pSen->SenType = SK_SEN_FAN;
35357 +                               pSen->SenThreErrHigh = SK_SEN_FAN_HIGH_ERR;
35358 +                               pSen->SenThreWarnHigh = SK_SEN_FAN_HIGH_WARN;
35359 +                               pSen->SenThreWarnLow = SK_SEN_FAN_LOW_WARN;
35360 +                               pSen->SenThreErrLow = SK_SEN_FAN_LOW_ERR;
35361 +                               pSen->SenReg = LM80_FAN2_IN;
35362 +                       }
35363 +                       else {
35364 +                               pSen->SenDesc = "Voltage PHY 2V5";
35365 +                               pSen->SenType = SK_SEN_VOLT;
35366 +                               pSen->SenThreErrHigh = SK_SEN_PHY_2V5_HIGH_ERR;
35367 +                               pSen->SenThreWarnHigh = SK_SEN_PHY_2V5_HIGH_WARN;
35368 +                               pSen->SenThreWarnLow = SK_SEN_PHY_2V5_LOW_WARN;
35369 +                               pSen->SenThreErrLow = SK_SEN_PHY_2V5_LOW_ERR;
35370 +                               pSen->SenReg = LM80_VT6_IN;
35371 +                       }
35372 +                       break;
35373 +               default:
35374 +                       SK_ERR_LOG(pAC, SK_ERRCL_INIT | SK_ERRCL_SW,
35375 +                               SKERR_I2C_E001, SKERR_I2C_E001MSG);
35376 +                       break;
35377 +               }
35378 +
35379 +               pSen->SenValue = 0;
35380 +               pSen->SenErrFlag = SK_SEN_ERR_OK;
35381 +               pSen->SenErrCts = 0;
35382 +               pSen->SenBegErrTS = 0;
35383 +               pSen->SenState = SK_SEN_IDLE;
35384 +               if (pSen->SenThreWarnLow != 0) {
35385 +                       pSen->SenRead = SkLm80ReadSensor;
35386 +               }
35387 +               pSen->SenDev = LM80_ADDR;
35388 +       }
35389 +
35390 +#ifndef SK_DIAG
35391 +       pAC->I2c.DummyReads = pAC->I2c.MaxSens;
35392 +#endif /* !SK_DIAG */
35393 +
35394 +       /* Clear TWSI IRQ */
35395 +       SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
35396 +
35397 +       /* Now we are I/O initialized */
35398 +       pAC->I2c.InitLevel = SK_INIT_IO;
35399 +       return(0);
35400 +}      /* SkI2cInit1 */
35401 +
35402 +
35403 +/*
35404 + * Init level 2: Start first sensor read.
35405 + */
35406 +static int SkI2cInit2(
35407 +SK_AC  *pAC,   /* Adapter Context */
35408 +SK_IOC IoC)    /* I/O Context */
35409 +{
35410 +       int                     ReadComplete;
35411 +       SK_SENSOR       *pSen;
35412 +
35413 +       if (pAC->I2c.InitLevel != SK_INIT_IO) {
35414 +               /* ReInit not needed in TWSI module */
35415 +               /* Init0 and Init2 not permitted */
35416 +               return(0);
35417 +       }
35418 +
35419 +       pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
35420 +
35421 +       ReadComplete = SkI2cReadSensor(pAC, IoC, pSen);
35422 +
35423 +       if (ReadComplete) {
35424 +               SK_ERR_LOG(pAC, SK_ERRCL_INIT, SKERR_I2C_E008, SKERR_I2C_E008MSG);
35425 +       }
35426 +
35427 +       /* Now we are correctly initialized */
35428 +       pAC->I2c.InitLevel = SK_INIT_RUN;
35429 +
35430 +       return(0);
35431 +}      /* SkI2cInit2*/
35432 +
35433 +
35434 +/*
35435 + * Initialize TWSI devices
35436 + *
35437 + * Get the first voltage value and discard it.
35438 + * Go into temperature read mode. A default pointer is not set.
35439 + *
35440 + * The things to be done depend on the init level in the parameter list:
35441 + * Level 0:
35442 + *     Initialize only the data structures. Do NOT access hardware.
35443 + * Level 1:
35444 + *     Initialize hardware through SK_IN / SK_OUT commands. Do NOT use interrupts.
35445 + * Level 2:
35446 + *     Everything is possible. Interrupts may be used from now on.
35447 + *
35448 + * return:
35449 + *     0 = success
35450 + *     other = error.
35451 + */
35452 +int SkI2cInit(
35453 +SK_AC  *pAC,   /* Adapter Context */
35454 +SK_IOC IoC,    /* I/O Context needed in levels 1 and 2 */
35455 +int            Level)  /* Init Level */
35456 +{
35457 +
35458 +       switch (Level) {
35459 +       case SK_INIT_DATA:
35460 +               return(SkI2cInit0(pAC));
35461 +       case SK_INIT_IO:
35462 +               return(SkI2cInit1(pAC, IoC));
35463 +       case SK_INIT_RUN:
35464 +               return(SkI2cInit2(pAC, IoC));
35465 +       default:
35466 +               break;
35467 +       }
35468 +
35469 +       return(0);
35470 +}      /* SkI2cInit */
35471 +
35472 +
35473 +#ifndef SK_DIAG
35474 +/*
35475 + * Interrupt service function for the TWSI Interface
35476 + *
35477 + * Clears the Interrupt source
35478 + *
35479 + * Reads the register and check it for sending a trap.
35480 + *
35481 + * Starts the timer if necessary.
35482 + */
35483 +void SkI2cIsr(
35484 +SK_AC  *pAC,   /* Adapter Context */
35485 +SK_IOC IoC)    /* I/O Context */
35486 +{
35487 +       SK_EVPARA       Para;
35488 +
35489 +       /* Clear TWSI IRQ */
35490 +       SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
35491 +
35492 +       Para.Para64 = 0;
35493 +       SkEventQueue(pAC, SKGE_I2C, SK_I2CEV_IRQ, Para);
35494 +}      /* SkI2cIsr */
35495 +
35496 +
35497 +/*
35498 + * Check this sensors Value against the threshold and send events.
35499 + */
35500 +static void SkI2cCheckSensor(
35501 +SK_AC          *pAC,   /* Adapter Context */
35502 +SK_SENSOR      *pSen)
35503 +{
35504 +       SK_EVPARA       ParaLocal;
35505 +       SK_BOOL         TooHigh;        /* Is sensor too high? */
35506 +       SK_BOOL         TooLow;         /* Is sensor too low? */
35507 +       SK_U64          CurrTime;       /* Current Time */
35508 +       SK_BOOL         DoTrapSend;     /* We need to send a trap */
35509 +       SK_BOOL         DoErrLog;       /* We need to log the error */
35510 +       SK_BOOL         IsError;        /* Error occured */
35511 +
35512 +       /* Check Dummy Reads first */
35513 +       if (pAC->I2c.DummyReads > 0) {
35514 +               pAC->I2c.DummyReads--;
35515 +               return;
35516 +       }
35517 +
35518 +       /* Get the current time */
35519 +       CurrTime = SkOsGetTime(pAC);
35520 +
35521 +       /* Set para to the most useful setting: The current sensor. */
35522 +       ParaLocal.Para64 = (SK_U64)pAC->I2c.CurrSens;
35523 +
35524 +       /* Check the Value against the thresholds. First: Error Thresholds */
35525 +       TooHigh = pSen->SenValue > pSen->SenThreErrHigh;
35526 +       TooLow  = pSen->SenValue < pSen->SenThreErrLow;
35527 +
35528 +       IsError = SK_FALSE;
35529 +
35530 +       if (TooHigh || TooLow) {
35531 +               /* Error condition is satisfied */
35532 +               DoTrapSend = SK_TRUE;
35533 +               DoErrLog = SK_TRUE;
35534 +
35535 +               /* Now error condition is satisfied */
35536 +               IsError = SK_TRUE;
35537 +
35538 +               if (pSen->SenErrFlag == SK_SEN_ERR_ERR) {
35539 +                       /* This state is the former one */
35540 +
35541 +                       /* So check first whether we have to send a trap */
35542 +                       if (pSen->SenLastErrTrapTS + SK_SEN_ERR_TR_HOLD > CurrTime) {
35543 +                               /*
35544 +                                * Do NOT send the Trap. The hold back time
35545 +                                * has to run out first.
35546 +                                */
35547 +                               DoTrapSend = SK_FALSE;
35548 +                       }
35549 +
35550 +                       /* Check now whether we have to log an Error */
35551 +                       if (pSen->SenLastErrLogTS + SK_SEN_ERR_LOG_HOLD > CurrTime) {
35552 +                               /*
35553 +                                * Do NOT log the error. The hold back time
35554 +                                * has to run out first.
35555 +                                */
35556 +                               DoErrLog = SK_FALSE;
35557 +                       }
35558 +               }
35559 +               else {
35560 +                       /* We came from a different state -> Set Begin Time Stamp */
35561 +                       pSen->SenBegErrTS = CurrTime;
35562 +                       pSen->SenErrFlag = SK_SEN_ERR_ERR;
35563 +               }
35564 +
35565 +               if (DoTrapSend) {
35566 +                       /* Set current Time */
35567 +                       pSen->SenLastErrTrapTS = CurrTime;
35568 +                       pSen->SenErrCts++;
35569 +
35570 +                       /* Queue PNMI Event */
35571 +                       SkEventQueue(pAC, SKGE_PNMI, TooHigh ?
35572 +                               SK_PNMI_EVT_SEN_ERR_UPP : SK_PNMI_EVT_SEN_ERR_LOW,
35573 +                               ParaLocal);
35574 +               }
35575 +
35576 +               if (DoErrLog) {
35577 +                       /* Set current Time */
35578 +                       pSen->SenLastErrLogTS = CurrTime;
35579 +
35580 +                       if (pSen->SenType == SK_SEN_TEMP) {
35581 +                               SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E011, SKERR_I2C_E011MSG);
35582 +                       }
35583 +                       else if (pSen->SenType == SK_SEN_VOLT) {
35584 +                               SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E012, SKERR_I2C_E012MSG);
35585 +                       }
35586 +                       else {
35587 +                               SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E015, SKERR_I2C_E015MSG);
35588 +                       }
35589 +               }
35590 +       }
35591 +
35592 +       /* Check the Value against the thresholds */
35593 +       /* 2nd: Warning thresholds */
35594 +       TooHigh = pSen->SenValue > pSen->SenThreWarnHigh;
35595 +       TooLow  = pSen->SenValue < pSen->SenThreWarnLow;
35596 +
35597 +       if (!IsError && (TooHigh || TooLow)) {
35598 +               /* Error condition is satisfied */
35599 +               DoTrapSend = SK_TRUE;
35600 +               DoErrLog = SK_TRUE;
35601 +
35602 +               if (pSen->SenErrFlag == SK_SEN_ERR_WARN) {
35603 +                       /* This state is the former one */
35604 +
35605 +                       /* So check first whether we have to send a trap */
35606 +                       if (pSen->SenLastWarnTrapTS + SK_SEN_WARN_TR_HOLD > CurrTime) {
35607 +                               /*
35608 +                                * Do NOT send the Trap. The hold back time
35609 +                                * has to run out first.
35610 +                                */
35611 +                               DoTrapSend = SK_FALSE;
35612 +                       }
35613 +
35614 +                       /* Check now whether we have to log an Error */
35615 +                       if (pSen->SenLastWarnLogTS + SK_SEN_WARN_LOG_HOLD > CurrTime) {
35616 +                               /*
35617 +                                * Do NOT log the error. The hold back time
35618 +                                * has to run out first.
35619 +                                */
35620 +                               DoErrLog = SK_FALSE;
35621 +                       }
35622 +               }
35623 +               else {
35624 +                       /* We came from a different state -> Set Begin Time Stamp */
35625 +                       pSen->SenBegWarnTS = CurrTime;
35626 +                       pSen->SenErrFlag = SK_SEN_ERR_WARN;
35627 +               }
35628 +
35629 +               if (DoTrapSend) {
35630 +                       /* Set current Time */
35631 +                       pSen->SenLastWarnTrapTS = CurrTime;
35632 +                       pSen->SenWarnCts++;
35633 +
35634 +                       /* Queue PNMI Event */
35635 +                       SkEventQueue(pAC, SKGE_PNMI, TooHigh ?
35636 +                               SK_PNMI_EVT_SEN_WAR_UPP : SK_PNMI_EVT_SEN_WAR_LOW, ParaLocal);
35637 +               }
35638 +
35639 +               if (DoErrLog) {
35640 +                       /* Set current Time */
35641 +                       pSen->SenLastWarnLogTS = CurrTime;
35642 +
35643 +                       if (pSen->SenType == SK_SEN_TEMP) {
35644 +                               SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E009, SKERR_I2C_E009MSG);
35645 +                       }
35646 +                       else if (pSen->SenType == SK_SEN_VOLT) {
35647 +                               SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E010, SKERR_I2C_E010MSG);
35648 +                       }
35649 +                       else {
35650 +                               SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E014, SKERR_I2C_E014MSG);
35651 +                       }
35652 +               }
35653 +       }
35654 +
35655 +       /* Check for NO error at all */
35656 +       if (!IsError && !TooHigh && !TooLow) {
35657 +               /* Set o.k. Status if no error and no warning condition */
35658 +               pSen->SenErrFlag = SK_SEN_ERR_OK;
35659 +       }
35660 +
35661 +       /* End of check against the thresholds */
35662 +
35663 +       if (pSen->SenInit == SK_SEN_DYN_INIT_PCI_IO) {
35664 +               /* Bug fix AF: 16.Aug.2001: Correct the init base of LM80 sensor */
35665 +               pSen->SenInit = SK_SEN_DYN_INIT_NONE;
35666 +
35667 +               if (pSen->SenValue > SK_SEN_PCI_IO_RANGE_LIMITER) {
35668 +                       /* 5V PCI-IO Voltage */
35669 +                       pSen->SenThreWarnLow = SK_SEN_PCI_IO_5V_LOW_WARN;
35670 +                       pSen->SenThreErrLow = SK_SEN_PCI_IO_5V_LOW_ERR;
35671 +               }
35672 +               else {
35673 +                       /* 3.3V PCI-IO Voltage */
35674 +                       pSen->SenThreWarnHigh = SK_SEN_PCI_IO_3V3_HIGH_WARN;
35675 +                       pSen->SenThreErrHigh = SK_SEN_PCI_IO_3V3_HIGH_ERR;
35676 +               }
35677 +       }
35678 +
35679 +#ifdef TEST_ONLY
35680 +       /* Dynamic thresholds also for VAUX of LM80 sensor */
35681 +       if (pSen->SenInit == SK_SEN_DYN_INIT_VAUX) {
35682 +
35683 +               pSen->SenInit = SK_SEN_DYN_INIT_NONE;
35684 +
35685 +               /* 3.3V VAUX Voltage */
35686 +               if (pSen->SenValue > SK_SEN_VAUX_RANGE_LIMITER) {
35687 +                       pSen->SenThreWarnLow = SK_SEN_VAUX_3V3_LOW_WARN;
35688 +                       pSen->SenThreErrLow = SK_SEN_VAUX_3V3_LOW_ERR;
35689 +               }
35690 +               /* 0V VAUX Voltage */
35691 +               else {
35692 +                       pSen->SenThreWarnHigh = SK_SEN_VAUX_0V_WARN_ERR;
35693 +                       pSen->SenThreErrHigh = SK_SEN_VAUX_0V_WARN_ERR;
35694 +               }
35695 +       }
35696 +
35697 +       /* Check initialization state: the VIO Thresholds need adaption */
35698 +       if (!pSen->SenInit && pSen->SenReg == LM80_VT1_IN &&
35699 +                pSen->SenValue > SK_SEN_WARNLOW2C &&
35700 +                pSen->SenValue < SK_SEN_WARNHIGH2) {
35701 +
35702 +               pSen->SenThreErrLow = SK_SEN_ERRLOW2C;
35703 +               pSen->SenThreWarnLow = SK_SEN_WARNLOW2C;
35704 +               pSen->SenInit = SK_TRUE;
35705 +       }
35706 +
35707 +       if (!pSen->SenInit && pSen->SenReg == LM80_VT1_IN &&
35708 +                pSen->SenValue > SK_SEN_WARNLOW2 &&
35709 +                pSen->SenValue < SK_SEN_WARNHIGH2C) {
35710 +
35711 +               pSen->SenThreErrHigh = SK_SEN_ERRHIGH2C;
35712 +               pSen->SenThreWarnHigh = SK_SEN_WARNHIGH2C;
35713 +               pSen->SenInit = SK_TRUE;
35714 +       }
35715 +#endif
35716 +
35717 +       if (pSen->SenInit != SK_SEN_DYN_INIT_NONE) {
35718 +               SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E013, SKERR_I2C_E013MSG);
35719 +       }
35720 +}      /* SkI2cCheckSensor */
35721 +
35722 +
35723 +/*
35724 + * The only Event to be served is the timeout event
35725 + *
35726 + */
35727 +int SkI2cEvent(
35728 +SK_AC          *pAC,   /* Adapter Context */
35729 +SK_IOC         IoC,    /* I/O Context */
35730 +SK_U32         Event,  /* Module specific Event */
35731 +SK_EVPARA      Para)   /* Event specific Parameter */
35732 +{
35733 +       int                     ReadComplete;
35734 +       SK_SENSOR       *pSen;
35735 +       SK_U32          Time;
35736 +       SK_EVPARA       ParaLocal;
35737 +       int                     i;
35738 +
35739 +       /* New case: no sensors */
35740 +       if (pAC->I2c.MaxSens == 0) {
35741 +               return(0);
35742 +       }
35743 +
35744 +       switch (Event) {
35745 +       case SK_I2CEV_IRQ:
35746 +               pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
35747 +               ReadComplete = SkI2cReadSensor(pAC, IoC, pSen);
35748 +
35749 +               if (ReadComplete) {
35750 +                       /* Check sensor against defined thresholds */
35751 +                       SkI2cCheckSensor(pAC, pSen);
35752 +
35753 +                       /* Increment Current sensor and set appropriate Timeout */
35754 +                       pAC->I2c.CurrSens++;
35755 +                       if (pAC->I2c.CurrSens >= pAC->I2c.MaxSens) {
35756 +                               pAC->I2c.CurrSens = 0;
35757 +                               Time = SK_I2C_TIM_LONG;
35758 +                       }
35759 +                       else {
35760 +                               Time = SK_I2C_TIM_SHORT;
35761 +                       }
35762 +
35763 +                       /* Start Timer */
35764 +                       ParaLocal.Para64 = (SK_U64)0;
35765 +
35766 +                       pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING;
35767 +
35768 +                       SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time,
35769 +                               SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
35770 +               }
35771 +               else {
35772 +                       /* Start Timer */
35773 +                       ParaLocal.Para64 = (SK_U64)0;
35774 +
35775 +                       pAC->I2c.TimerMode = SK_TIMER_WATCH_SM;
35776 +
35777 +                       SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, SK_I2C_TIM_WATCH,
35778 +                               SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
35779 +               }
35780 +               break;
35781 +       case SK_I2CEV_TIM:
35782 +               if (pAC->I2c.TimerMode == SK_TIMER_NEW_GAUGING) {
35783 +
35784 +                       ParaLocal.Para64 = (SK_U64)0;
35785 +                       SkTimerStop(pAC, IoC, &pAC->I2c.SenTimer);
35786 +
35787 +                       pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
35788 +                       ReadComplete = SkI2cReadSensor(pAC, IoC, pSen);
35789 +
35790 +                       if (ReadComplete) {
35791 +                               /* Check sensor against defined thresholds */
35792 +                               SkI2cCheckSensor(pAC, pSen);
35793 +
35794 +                               /* Increment Current sensor and set appropriate Timeout */
35795 +                               pAC->I2c.CurrSens++;
35796 +                               if (pAC->I2c.CurrSens == pAC->I2c.MaxSens) {
35797 +                                       pAC->I2c.CurrSens = 0;
35798 +                                       Time = SK_I2C_TIM_LONG;
35799 +                               }
35800 +                               else {
35801 +                                       Time = SK_I2C_TIM_SHORT;
35802 +                               }
35803 +
35804 +                               /* Start Timer */
35805 +                               ParaLocal.Para64 = (SK_U64)0;
35806 +
35807 +                               pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING;
35808 +
35809 +                               SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time,
35810 +                                       SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
35811 +                       }
35812 +               }
35813 +               else {
35814 +                       pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
35815 +                       pSen->SenErrFlag = SK_SEN_ERR_FAULTY;
35816 +                       SK_I2C_STOP(IoC);
35817 +
35818 +                       /* Increment Current sensor and set appropriate Timeout */
35819 +                       pAC->I2c.CurrSens++;
35820 +                       if (pAC->I2c.CurrSens == pAC->I2c.MaxSens) {
35821 +                               pAC->I2c.CurrSens = 0;
35822 +                               Time = SK_I2C_TIM_LONG;
35823 +                       }
35824 +                       else {
35825 +                               Time = SK_I2C_TIM_SHORT;
35826 +                       }
35827 +
35828 +                       /* Start Timer */
35829 +                       ParaLocal.Para64 = (SK_U64)0;
35830 +
35831 +                       pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING;
35832 +
35833 +                       SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time,
35834 +                               SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
35835 +               }
35836 +               break;
35837 +       case SK_I2CEV_CLEAR:
35838 +               for (i = 0; i < SK_MAX_SENSORS; i++) {
35839 +                       pSen = &pAC->I2c.SenTable[i];
35840 +
35841 +                       pSen->SenErrFlag = SK_SEN_ERR_OK;
35842 +                       pSen->SenErrCts = 0;
35843 +                       pSen->SenWarnCts = 0;
35844 +                       pSen->SenBegErrTS = 0;
35845 +                       pSen->SenBegWarnTS = 0;
35846 +                       pSen->SenLastErrTrapTS = (SK_U64)0;
35847 +                       pSen->SenLastErrLogTS = (SK_U64)0;
35848 +                       pSen->SenLastWarnTrapTS = (SK_U64)0;
35849 +                       pSen->SenLastWarnLogTS = (SK_U64)0;
35850 +               }
35851 +               break;
35852 +       default:
35853 +               SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E006, SKERR_I2C_E006MSG);
35854 +       }
35855 +
35856 +       return(0);
35857 +}      /* SkI2cEvent*/
35858 +
35859 +#endif /* !SK_DIAG */
35860 +
35861 diff -ruN linux/drivers/net/sk98lin/skvpd.c linux-new/drivers/net/sk98lin/skvpd.c
35862 --- linux/drivers/net/sk98lin/skvpd.c   2006-09-20 05:42:06.000000000 +0200
35863 +++ linux-new/drivers/net/sk98lin/skvpd.c       2006-07-28 14:13:54.000000000 +0200
35864 @@ -1,23 +1,25 @@
35865  /******************************************************************************
35866   *
35867   * Name:       skvpd.c
35868 - * Project:    GEnesis, PCI Gigabit Ethernet Adapter
35869 - * Version:    $Revision$
35870 - * Date:       $Date$
35871 - * Purpose:    Shared software to read and write VPD data
35872 + * Project:    Gigabit Ethernet Adapters, VPD-Module
35873 + * Version:    $Revision$
35874 + * Date:       $Date$
35875 + * Purpose:    Shared software to read and write VPD
35876   *
35877   ******************************************************************************/
35878
35879  /******************************************************************************
35880   *
35881 - *     (C)Copyright 1998-2003 SysKonnect GmbH.
35882 + *     LICENSE:
35883 + *     (C)Copyright 1998-2002 SysKonnect.
35884 + *     (C)Copyright 2002-2005 Marvell.
35885   *
35886   *     This program is free software; you can redistribute it and/or modify
35887   *     it under the terms of the GNU General Public License as published by
35888   *     the Free Software Foundation; either version 2 of the License, or
35889   *     (at your option) any later version.
35890 - *
35891   *     The information in this file is provided "AS IS" without warranty.
35892 + *     /LICENSE
35893   *
35894   ******************************************************************************/
35895
35896 @@ -25,7 +27,7 @@
35897         Please refer skvpd.txt for information how to include this module
35898   */
35899  static const char SysKonnectFileId[] =
35900 -       "@(#)$Id$ (C) SK";
35901 +       "@(#) $Id$ (C) Marvell.";
35902
35903  #include "h/skdrv1st.h"
35904  #include "h/sktypes.h"
35905 @@ -52,18 +54,23 @@
35906   *             error   exit(9) with a error message
35907   */
35908  static int VpdWait(
35909 -SK_AC  *pAC,   /* Adapters context */
35910 +SK_AC  *pAC,   /* Adapters Context */
35911  SK_IOC IoC,    /* IO Context */
35912  int            event)  /* event to wait for (VPD_READ / VPD_write) completion*/
35913  {
35914 -       SK_U64  start_time;
35915 +       SK_I64  start_time;
35916 +       SK_I64  curr_time;
35917         SK_U16  state;
35918
35919 -       SK_DBG_MSG(pAC,SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
35920 -               ("VPD wait for %s\n", event?"Write":"Read"));
35921 -       start_time = SkOsGetTime(pAC);
35922 +       SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
35923 +               ("VPD wait for %s\n", event ? "Write" : "Read"));
35924 +
35925 +       start_time = (SK_I64)SkOsGetTime(pAC);
35926 +
35927         do {
35928 -               if (SkOsGetTime(pAC) - start_time > SK_TICKS_PER_SEC) {
35929 +               curr_time = (SK_I64)SkOsGetTime(pAC);
35930 +
35931 +               if (curr_time - start_time > SK_TICKS_PER_SEC) {
35932
35933                         /* Bug fix AF: Thu Mar 28 2002
35934                          * Do not call: VPD_STOP(pAC, IoC);
35935 @@ -81,18 +88,19 @@
35936                                 ("ERROR:VPD wait timeout\n"));
35937                         return(1);
35938                 }
35939 -
35940 +
35941                 VPD_IN16(pAC, IoC, PCI_VPD_ADR_REG, &state);
35942 -
35943 +
35944                 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
35945 -                       ("state = %x, event %x\n",state,event));
35946 -       } while((int)(state & PCI_VPD_FLAG) == event);
35947 +                       ("state = %x, event %x\n", state, event));
35948 +
35949 +       } while ((int)(state & PCI_VPD_FLAG) == event);
35950
35951         return(0);
35952  }
35953
35954 -#ifdef SKDIAG
35955
35956 +#ifdef SK_DIAG
35957  /*
35958   * Read the dword at address 'addr' from the VPD EEPROM.
35959   *
35960 @@ -104,7 +112,7 @@
35961   * Returns the data read.
35962   */
35963  SK_U32 VpdReadDWord(
35964 -SK_AC  *pAC,   /* Adapters context */
35965 +SK_AC  *pAC,   /* Adapters Context */
35966  SK_IOC IoC,    /* IO Context */
35967  int            addr)   /* VPD address */
35968  {
35969 @@ -112,7 +120,7 @@
35970
35971         /* start VPD read */
35972         SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
35973 -               ("VPD read dword at 0x%x\n",addr));
35974 +               ("VPD read dword at 0x%x\n", addr));
35975         addr &= ~VPD_WRITE;             /* ensure the R/W bit is set to read */
35976
35977         VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, (SK_U16)addr);
35978 @@ -124,14 +132,73 @@
35979         Rtv = 0;
35980
35981         VPD_IN32(pAC, IoC, PCI_VPD_DAT_REG, &Rtv);
35982 -
35983 +
35984         SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
35985 -               ("VPD read dword data = 0x%x\n",Rtv));
35986 +               ("VPD read dword data = 0x%x\n", Rtv));
35987         return(Rtv);
35988  }
35989 +#endif /* SK_DIAG */
35990 +
35991 +
35992 +#ifdef XXX
35993 +/*
35994 +       Write the dword 'data' at address 'addr' into the VPD EEPROM, and
35995 +       verify that the data is written.
35996 +
35997 + Needed Time:
35998 +
35999 +.                              MIN             MAX
36000 +. -------------------------------------------------------------------
36001 +. write                                1.8 ms          3.6 ms
36002 +. internal write cyles         0.7 ms          7.0 ms
36003 +. -------------------------------------------------------------------
36004 +. over all program time                2.5 ms          10.6 ms
36005 +. read                         1.3 ms          2.6 ms
36006 +. -------------------------------------------------------------------
36007 +. over all                     3.8 ms          13.2 ms
36008 +.
36009 +
36010 + Returns       0:      success
36011 +                       1:      error,  I2C transfer does not terminate
36012 +                       2:      error,  data verify error
36013 +
36014 + */
36015 +static int VpdWriteDWord(
36016 +SK_AC  *pAC,   /* Adapters Context */
36017 +SK_IOC IoC,    /* IO Context */
36018 +int            addr,   /* VPD address */
36019 +SK_U32 data)   /* VPD data to write */
36020 +{
36021 +       /* start VPD write */
36022 +       /* Don't swap here, it's a data stream of bytes */
36023 +       SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
36024 +               ("VPD write dword at addr 0x%x, data = 0x%x\n", addr, data));
36025 +       VPD_OUT32(pAC, IoC, PCI_VPD_DAT_REG, (SK_U32)data);
36026 +       /* But do it here */
36027 +       addr |= VPD_WRITE;
36028 +
36029 +       VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, (SK_U16)(addr | VPD_WRITE));
36030 +
36031 +       /* this may take up to 10,6 ms */
36032 +       if (VpdWait(pAC, IoC, VPD_WRITE)) {
36033 +               SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36034 +                       ("Write Timed Out\n"));
36035 +               return(1);
36036 +       };
36037 +
36038 +       /* verify data */
36039 +       if (VpdReadDWord(pAC, IoC, addr) != data) {
36040 +               SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
36041 +                       ("Data Verify Error\n"));
36042 +               return(2);
36043 +       }
36044 +       return(0);
36045 +}      /* VpdWriteDWord */
36046
36047 -#endif /* SKDIAG */
36048 +#endif /* XXX */
36049
36050 +
36051 +#ifndef SK_SLIM
36052  /*
36053   *     Read one Stream of 'len' bytes of VPD data, starting at 'addr' from
36054   *     or to the I2C EEPROM.
36055 @@ -139,7 +206,7 @@
36056   * Returns number of bytes read / written.
36057   */
36058  static int VpdWriteStream(
36059 -SK_AC  *pAC,   /* Adapters context */
36060 +SK_AC  *pAC,   /* Adapters Context */
36061  SK_IOC IoC,    /* IO Context */
36062  char   *buf,   /* data buffer */
36063  int            Addr,   /* VPD start address */
36064 @@ -156,7 +223,7 @@
36065         pComp = (SK_U8 *) buf;
36066
36067         for (i = 0; i < Len; i++, buf++) {
36068 -               if ((i%sizeof(SK_U32)) == 0) {
36069 +               if ((i % SZ_LONG) == 0) {
36070                         /*
36071                          * At the begin of each cycle read the Data Reg
36072                          * So it is initialized even if only a few bytes
36073 @@ -174,14 +241,13 @@
36074                         }
36075                 }
36076
36077 -               /* Write current Byte */
36078 -               VPD_OUT8(pAC, IoC, PCI_VPD_DAT_REG + (i%sizeof(SK_U32)),
36079 -                               *(SK_U8*)buf);
36080 +               /* Write current byte */
36081 +               VPD_OUT8(pAC, IoC, PCI_VPD_DAT_REG + (i % SZ_LONG), *(SK_U8 *)buf);
36082
36083 -               if (((i%sizeof(SK_U32)) == 3) || (i == (Len - 1))) {
36084 +               if (((i % SZ_LONG) == 3) || (i == (Len - 1))) {
36085                         /* New Address needs to be written to VPD_ADDR reg */
36086                         AdrReg = (SK_U16) Addr;
36087 -                       Addr += sizeof(SK_U32);
36088 +                       Addr += SZ_LONG;
36089                         AdrReg |= VPD_WRITE;    /* WRITE operation */
36090
36091                         VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, AdrReg);
36092 @@ -191,7 +257,7 @@
36093                         if (Rtv != 0) {
36094                                 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36095                                         ("Write Timed Out\n"));
36096 -                               return(i - (i%sizeof(SK_U32)));
36097 +                               return(i - (i % SZ_LONG));
36098                         }
36099
36100                         /*
36101 @@ -206,18 +272,18 @@
36102                         if (Rtv != 0) {
36103                                 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36104                                         ("Verify Timed Out\n"));
36105 -                               return(i - (i%sizeof(SK_U32)));
36106 +                               return(i - (i % SZ_LONG));
36107                         }
36108
36109 -                       for (j = 0; j <= (int)(i%sizeof(SK_U32)); j++, pComp++) {
36110 -
36111 +                       for (j = 0; j <= (int)(i % SZ_LONG); j++, pComp++) {
36112 +
36113                                 VPD_IN8(pAC, IoC, PCI_VPD_DAT_REG + j, &Data);
36114 -
36115 +
36116                                 if (Data != *pComp) {
36117                                         /* Verify Error */
36118                                         SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36119                                                 ("WriteStream Verify Error\n"));
36120 -                                       return(i - (i%sizeof(SK_U32)) + j);
36121 +                                       return(i - (i % SZ_LONG) + j);
36122                                 }
36123                         }
36124                 }
36125 @@ -225,7 +291,7 @@
36126
36127         return(Len);
36128  }
36129 -
36130 +#endif /* !SK_SLIM */
36131
36132  /*
36133   *     Read one Stream of 'len' bytes of VPD data, starting at 'addr' from
36134 @@ -234,7 +300,7 @@
36135   * Returns number of bytes read / written.
36136   */
36137  static int VpdReadStream(
36138 -SK_AC  *pAC,   /* Adapters context */
36139 +SK_AC  *pAC,   /* Adapters Context */
36140  SK_IOC IoC,    /* IO Context */
36141  char   *buf,   /* data buffer */
36142  int            Addr,   /* VPD start address */
36143 @@ -245,10 +311,10 @@
36144         int             Rtv;
36145
36146         for (i = 0; i < Len; i++, buf++) {
36147 -               if ((i%sizeof(SK_U32)) == 0) {
36148 +               if ((i % SZ_LONG) == 0) {
36149                         /* New Address needs to be written to VPD_ADDR reg */
36150                         AdrReg = (SK_U16) Addr;
36151 -                       Addr += sizeof(SK_U32);
36152 +                       Addr += SZ_LONG;
36153                         AdrReg &= ~VPD_WRITE;   /* READ operation */
36154
36155                         VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, AdrReg);
36156 @@ -259,13 +325,13 @@
36157                                 return(i);
36158                         }
36159                 }
36160 -               VPD_IN8(pAC, IoC, PCI_VPD_DAT_REG + (i%sizeof(SK_U32)),
36161 -                       (SK_U8 *)buf);
36162 +               VPD_IN8(pAC, IoC, PCI_VPD_DAT_REG + (i % SZ_LONG), (SK_U8 *)buf);
36163         }
36164
36165         return(Len);
36166  }
36167
36168 +
36169  /*
36170   *     Read ore writes 'len' bytes of VPD data, starting at 'addr' from
36171   *     or to the I2C EEPROM.
36172 @@ -273,7 +339,7 @@
36173   * Returns number of bytes read / written.
36174   */
36175  static int VpdTransferBlock(
36176 -SK_AC  *pAC,   /* Adapters context */
36177 +SK_AC  *pAC,   /* Adapters Context */
36178  SK_IOC IoC,    /* IO Context */
36179  char   *buf,   /* data buffer */
36180  int            addr,   /* VPD start address */
36181 @@ -287,18 +353,19 @@
36182                 ("VPD %s block, addr = 0x%x, len = %d\n",
36183                 dir ? "write" : "read", addr, len));
36184
36185 -       if (len == 0)
36186 +       if (len == 0) {
36187                 return(0);
36188 +       }
36189
36190         vpd_rom_size = pAC->vpd.rom_size;
36191 -
36192 +
36193         if (addr > vpd_rom_size - 4) {
36194                 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
36195                         ("Address error: 0x%x, exp. < 0x%x\n",
36196                         addr, vpd_rom_size - 4));
36197                 return(0);
36198         }
36199 -
36200 +
36201         if (addr + len > vpd_rom_size) {
36202                 len = vpd_rom_size - addr;
36203                 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36204 @@ -308,22 +375,24 @@
36205         if (dir == VPD_READ) {
36206                 Rtv = VpdReadStream(pAC, IoC, buf, addr, len);
36207         }
36208 +#ifndef SK_SLIM
36209         else {
36210                 Rtv = VpdWriteStream(pAC, IoC, buf, addr, len);
36211         }
36212 +#endif /* !SK_SLIM */
36213
36214         return(Rtv);
36215  }
36216
36217 -#ifdef SKDIAG
36218
36219 +#if defined(SK_DIAG) || defined(SK_ASF)
36220  /*
36221   *     Read 'len' bytes of VPD data, starting at 'addr'.
36222   *
36223   * Returns number of bytes read.
36224   */
36225  int VpdReadBlock(
36226 -SK_AC  *pAC,   /* pAC pointer */
36227 +SK_AC  *pAC,   /* Adapters Context */
36228  SK_IOC IoC,    /* IO Context */
36229  char   *buf,   /* buffer were the data should be stored */
36230  int            addr,   /* start reading at the VPD address */
36231 @@ -332,13 +401,14 @@
36232         return(VpdTransferBlock(pAC, IoC, buf, addr, len, VPD_READ));
36233  }
36234
36235 +
36236  /*
36237   *     Write 'len' bytes of *but to the VPD EEPROM, starting at 'addr'.
36238   *
36239   * Returns number of bytes writes.
36240   */
36241  int VpdWriteBlock(
36242 -SK_AC  *pAC,   /* pAC pointer */
36243 +SK_AC  *pAC,   /* Adapters Context */
36244  SK_IOC IoC,    /* IO Context */
36245  char   *buf,   /* buffer, holds the data to write */
36246  int            addr,   /* start writing at the VPD address */
36247 @@ -346,19 +416,28 @@
36248  {
36249         return(VpdTransferBlock(pAC, IoC, buf, addr, len, VPD_WRITE));
36250  }
36251 -#endif /* SKDIAG */
36252 +#endif /* SK_DIAG || SK_ASF */
36253
36254 -/*
36255 - * (re)initialize the VPD buffer
36256 +
36257 +/******************************************************************************
36258   *
36259 - * Reads the VPD data from the EEPROM into the VPD buffer.
36260 - * Get the remaining read only and read / write space.
36261 + *     VpdInit() - (re)initialize the VPD buffer
36262   *
36263 - * return      0:      success
36264 - *             1:      fatal VPD error
36265 + * Description:
36266 + *     Reads the VPD data from the EEPROM into the VPD buffer.
36267 + *     Get the remaining read only and read / write space.
36268 + *
36269 + * Note:
36270 + *     This is a local function and should be used locally only.
36271 + *     However, the ASF module needs to use this function also.
36272 + *     Therfore it has been published.
36273 + *
36274 + * Returns:
36275 + *     0:      success
36276 + *     1:      fatal VPD error
36277   */
36278 -static int VpdInit(
36279 -SK_AC  *pAC,   /* Adapters context */
36280 +int VpdInit(
36281 +SK_AC  *pAC,   /* Adapters Context */
36282  SK_IOC IoC)    /* IO Context */
36283  {
36284         SK_VPD_PARA *r, rp;     /* RW or RV */
36285 @@ -368,14 +447,14 @@
36286         SK_U16  dev_id;
36287         SK_U32  our_reg2;
36288
36289 -       SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_INIT, ("VpdInit .. "));
36290 -
36291 +       SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_INIT, ("VpdInit ... "));
36292 +
36293         VPD_IN16(pAC, IoC, PCI_DEVICE_ID, &dev_id);
36294 -
36295 +
36296         VPD_IN32(pAC, IoC, PCI_OUR_REG_2, &our_reg2);
36297 -
36298 +
36299         pAC->vpd.rom_size = 256 << ((our_reg2 & PCI_VPD_ROM_SZ) >> 14);
36300 -
36301 +
36302         /*
36303          * this function might get used before the hardware is initialized
36304          * therefore we cannot always trust in GIChipId
36305 @@ -388,6 +467,7 @@
36306                 /* for Yukon the VPD size is always 256 */
36307                 vpd_size = VPD_SIZE_YUKON;
36308         }
36309 +#ifndef SK_SLIM
36310         else {
36311                 /* Genesis uses the maximum ROM size up to 512 for VPD */
36312                 if (pAC->vpd.rom_size > VPD_SIZE_GENESIS) {
36313 @@ -397,6 +477,7 @@
36314                         vpd_size = pAC->vpd.rom_size;
36315                 }
36316         }
36317 +#endif /* !SK_SLIM */
36318
36319         /* read the VPD data into the VPD buffer */
36320         if (VpdTransferBlock(pAC, IoC, pAC->vpd.vpd_buf, 0, vpd_size, VPD_READ)
36321 @@ -406,19 +487,17 @@
36322                         ("Block Read Error\n"));
36323                 return(1);
36324         }
36325 -
36326 +
36327         pAC->vpd.vpd_size = vpd_size;
36328
36329 +#ifndef SK_SLIM
36330         /* Asus K8V Se Deluxe bugfix. Correct VPD content */
36331 -       /* MBo April 2004 */
36332 -       if (((unsigned char)pAC->vpd.vpd_buf[0x3f] == 0x38) &&
36333 -           ((unsigned char)pAC->vpd.vpd_buf[0x40] == 0x3c) &&
36334 -           ((unsigned char)pAC->vpd.vpd_buf[0x41] == 0x45)) {
36335 -               printk("sk98lin: Asus mainboard with buggy VPD? "
36336 -                               "Correcting data.\n");
36337 -               pAC->vpd.vpd_buf[0x40] = 0x38;
36338 -       }
36339 +       i = 62;
36340 +       if (!SK_STRNCMP(pAC->vpd.vpd_buf + i, " 8<E", 4)) {
36341
36342 +               pAC->vpd.vpd_buf[i + 2] = '8';
36343 +       }
36344 +#endif /* !SK_SLIM */
36345
36346         /* find the end tag of the RO area */
36347         if (!(r = vpd_find_para(pAC, VPD_RV, &rp))) {
36348 @@ -426,9 +505,9 @@
36349                         ("Encoding Error: RV Tag not found\n"));
36350                 return(1);
36351         }
36352 -
36353 +
36354         if (r->p_val + r->p_len > pAC->vpd.vpd_buf + vpd_size/2) {
36355 -               SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
36356 +               SK_DBG_MSG(pAC, SK_DBGMOD_VPD,SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
36357                         ("Encoding Error: Invalid VPD struct size\n"));
36358                 return(1);
36359         }
36360 @@ -438,7 +517,7 @@
36361         for (i = 0, x = 0; (unsigned)i <= (unsigned)vpd_size/2 - r->p_len; i++) {
36362                 x += pAC->vpd.vpd_buf[i];
36363         }
36364 -
36365 +
36366         if (x != 0) {
36367                 /* checksum error */
36368                 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
36369 @@ -452,7 +531,7 @@
36370                         ("Encoding Error: RV Tag not found\n"));
36371                 return(1);
36372         }
36373 -
36374 +
36375         if (r->p_val < pAC->vpd.vpd_buf + vpd_size/2) {
36376                 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
36377                         ("Encoding Error: Invalid VPD struct size\n"));
36378 @@ -472,6 +551,7 @@
36379         return(0);
36380  }
36381
36382 +
36383  /*
36384   *     find the Keyword 'key' in the VPD buffer and fills the
36385   *     parameter struct 'p' with it's values
36386 @@ -480,58 +560,63 @@
36387   *             0:      parameter was not found or VPD encoding error
36388   */
36389  static SK_VPD_PARA *vpd_find_para(
36390 -SK_AC          *pAC,   /* common data base */
36391 +SK_AC          *pAC,   /* Adapters Context */
36392  const char     *key,   /* keyword to find (e.g. "MN") */
36393 -SK_VPD_PARA *p)                /* parameter description struct */
36394 +SK_VPD_PARA    *p)             /* parameter description struct */
36395  {
36396         char *v ;       /* points to VPD buffer */
36397         int max;        /* Maximum Number of Iterations */
36398 +       int len;
36399
36400         v = pAC->vpd.vpd_buf;
36401         max = 128;
36402
36403         SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
36404 -               ("VPD find para %s .. ",key));
36405 +               ("VPD find para %s .. ", key));
36406
36407         /* check mandatory resource type ID string (Product Name) */
36408         if (*v != (char)RES_ID) {
36409                 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
36410                         ("Error: 0x%x missing\n", RES_ID));
36411 -               return NULL;
36412 +               return(0);
36413         }
36414
36415 -       if (strcmp(key, VPD_NAME) == 0) {
36416 -               p->p_len = VPD_GET_RES_LEN(v);
36417 +       len = VPD_GET_RES_LEN(v);
36418 +
36419 +       if (SK_STRCMP(key, VPD_NAME) == 0) {
36420 +               p->p_len = len;
36421                 p->p_val = VPD_GET_VAL(v);
36422                 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
36423 -                       ("found, len = %d\n", p->p_len));
36424 +                       ("found, len = %d\n", len));
36425                 return(p);
36426         }
36427
36428 -       v += 3 + VPD_GET_RES_LEN(v) + 3;
36429 -       for (;; ) {
36430 -               if (SK_MEMCMP(key,v,2) == 0) {
36431 +       v += 3 + len + 3;
36432 +
36433 +       for ( ; ; ) {
36434 +               if (SK_MEMCMP(key, v, 2) == 0) {
36435                         p->p_len = VPD_GET_VPD_LEN(v);
36436                         p->p_val = VPD_GET_VAL(v);
36437                         SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
36438 -                               ("found, len = %d\n",p->p_len));
36439 +                               ("found, len = %d\n", p->p_len));
36440                         return(p);
36441                 }
36442
36443                 /* exit when reaching the "RW" Tag or the maximum of itera. */
36444                 max--;
36445 -               if (SK_MEMCMP(VPD_RW,v,2) == 0 || max == 0) {
36446 +               if (SK_MEMCMP(VPD_RW, v, 2) == 0 || max == 0) {
36447                         break;
36448                 }
36449
36450 -               if (SK_MEMCMP(VPD_RV,v,2) == 0) {
36451 -                       v += 3 + VPD_GET_VPD_LEN(v) + 3;        /* skip VPD-W */
36452 -               }
36453 -               else {
36454 -                       v += 3 + VPD_GET_VPD_LEN(v);
36455 +               len = 3 + VPD_GET_VPD_LEN(v);
36456 +
36457 +               if (SK_MEMCMP(VPD_RV, v, 2) == 0) {
36458 +                       len += 3;                                       /* skip VPD-W */
36459                 }
36460 +               v += len;
36461 +
36462                 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
36463 -                       ("scanning '%c%c' len = %d\n",v[0],v[1],v[2]));
36464 +                       ("scanning '%c%c' len = %d\n", v[0], v[1], v[2]));
36465         }
36466
36467  #ifdef DEBUG
36468 @@ -541,9 +626,10 @@
36469                         ("Key/Len Encoding error\n"));
36470         }
36471  #endif /* DEBUG */
36472 -       return NULL;
36473 +       return(0);
36474  }
36475
36476 +
36477  /*
36478   *     Move 'n' bytes. Begin with the last byte if 'n' is > 0,
36479   *     Start with the last byte if n is < 0.
36480 @@ -558,8 +644,9 @@
36481         char *p;
36482         int i;          /* number of byte copied */
36483
36484 -       if (n == 0)
36485 +       if (n == 0) {
36486                 return;
36487 +       }
36488
36489         i = (int) (end - start + 1);
36490         if (n < 0) {
36491 @@ -578,6 +665,7 @@
36492         }
36493  }
36494
36495 +
36496  /*
36497   *     setup the VPD keyword 'key' at 'ip'.
36498   *
36499 @@ -594,10 +682,11 @@
36500         p = (SK_VPD_KEY *) ip;
36501         p->p_key[0] = key[0];
36502         p->p_key[1] = key[1];
36503 -       p->p_len = (unsigned char) len;
36504 -       SK_MEMCPY(&p->p_val,buf,len);
36505 +       p->p_len = (unsigned char)len;
36506 +       SK_MEMCPY(&p->p_val, buf, len);
36507  }
36508
36509 +
36510  /*
36511   *     Setup the VPD end tag "RV" / "RW".
36512   *     Also correct the remaining space variables vpd_free_ro / vpd_free_rw.
36513 @@ -606,7 +695,7 @@
36514   *             1:      encoding error
36515   */
36516  static int vpd_mod_endtag(
36517 -SK_AC  *pAC,           /* common data base */
36518 +SK_AC  *pAC,           /* Adapters Context */
36519  char   *etp)           /* end pointer input position */
36520  {
36521         SK_VPD_KEY *p;
36522 @@ -615,7 +704,7 @@
36523         int     vpd_size;
36524
36525         SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
36526 -               ("VPD modify endtag at 0x%x = '%c%c'\n",etp,etp[0],etp[1]));
36527 +               ("VPD modify endtag at 0x%x = '%c%c'\n", etp, etp[0], etp[1]));
36528
36529         vpd_size = pAC->vpd.vpd_size;
36530
36531 @@ -623,7 +712,7 @@
36532
36533         if (p->p_key[0] != 'R' || (p->p_key[1] != 'V' && p->p_key[1] != 'W')) {
36534                 /* something wrong here, encoding error */
36535 -               SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
36536 +               SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
36537                         ("Encoding Error: invalid end tag\n"));
36538                 return(1);
36539         }
36540 @@ -655,6 +744,7 @@
36541         return(0);
36542  }
36543
36544 +
36545  /*
36546   *     Insert a VPD keyword into the VPD buffer.
36547   *
36548 @@ -669,8 +759,8 @@
36549   *             6:      fatal VPD error
36550   *
36551   */
36552 -static int     VpdSetupPara(
36553 -SK_AC  *pAC,           /* common data base */
36554 +int    VpdSetupPara(
36555 +SK_AC  *pAC,           /* Adapters Context */
36556  const char     *key,   /* keyword to insert */
36557  const char     *buf,   /* buffer with the keyword value */
36558  int            len,            /* length of the keyword value */
36559 @@ -687,12 +777,12 @@
36560         int vpd_size;
36561
36562         SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
36563 -               ("VPD setup para key = %s, val = %s\n",key,buf));
36564 -
36565 +               ("VPD setup para key = %s, val = %s\n", key, buf));
36566 +
36567         vpd_size = pAC->vpd.vpd_size;
36568
36569         rtv = 0;
36570 -       ip = NULL;
36571 +       ip = 0;
36572         if (type == VPD_RW_KEY) {
36573                 /* end tag is "RW" */
36574                 free = pAC->vpd.v.vpd_free_rw;
36575 @@ -743,7 +833,9 @@
36576         }
36577
36578         vpd_move_para(ip + vp.p_len + found, etp+2, len-vp.p_len+head);
36579 +
36580         vpd_insert_key(key, buf, len, ip);
36581 +
36582         if (vpd_mod_endtag(pAC, etp + len - vp.p_len + head)) {
36583                 pAC->vpd.v.vpd_status &= ~VPD_VALID;
36584                 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36585 @@ -754,7 +846,7 @@
36586         return(rtv);
36587  }
36588
36589 -
36590 +#ifndef SK_SLIM
36591  /*
36592   *     Read the contents of the VPD EEPROM and copy it to the
36593   *     VPD buffer if not already done.
36594 @@ -763,7 +855,7 @@
36595   *             this fields.
36596   */
36597  SK_VPD_STATUS *VpdStat(
36598 -SK_AC  *pAC,   /* Adapters context */
36599 +SK_AC  *pAC,   /* Adapters Context */
36600  SK_IOC IoC)    /* IO Context */
36601  {
36602         if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) {
36603 @@ -780,13 +872,14 @@
36604   *     keyword list by copying the keywords to 'buf', all after
36605   *     each other and terminated with a '\0'.
36606   *
36607 - * Exceptions: o The Resource Type ID String (product name) is called "Name"
36608 + * Exceptions:
36609 + *             o The Resource Type ID String (product name) is called "Name"
36610   *             o The VPD end tags 'RV' and 'RW' are not listed
36611   *
36612   *     The number of copied keywords is counted in 'elements'.
36613   *
36614   * returns     0:      success
36615 - *             2:      buffer overfull, one or more keywords are missing
36616 + *             2:      buffer overflow, one or more keywords are missing
36617   *             6:      fatal VPD error
36618   *
36619   *     example values after returning:
36620 @@ -796,7 +889,7 @@
36621   *             *elements =      9
36622   */
36623  int VpdKeys(
36624 -SK_AC  *pAC,           /* common data base */
36625 +SK_AC  *pAC,           /* Adapters Context */
36626  SK_IOC IoC,            /* IO Context */
36627  char   *buf,           /* buffer where to copy the keywords */
36628  int            *len,           /* buffer length */
36629 @@ -806,6 +899,7 @@
36630         int n;
36631
36632         SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX, ("list VPD keys .. "));
36633 +
36634         *elements = 0;
36635         if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) {
36636                 if (VpdInit(pAC, IoC) != 0) {
36637 @@ -816,43 +910,44 @@
36638                 }
36639         }
36640
36641 -       if ((signed)strlen(VPD_NAME) + 1 <= *len) {
36642 +       if ((signed)SK_STRLEN(VPD_NAME) + 1 <= *len) {
36643                 v = pAC->vpd.vpd_buf;
36644 -               strcpy(buf,VPD_NAME);
36645 -               n = strlen(VPD_NAME) + 1;
36646 +               SK_STRCPY(buf, VPD_NAME);
36647 +               n = SK_STRLEN(VPD_NAME) + 1;
36648                 buf += n;
36649                 *elements = 1;
36650                 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX,
36651 -                       ("'%c%c' ",v[0],v[1]));
36652 +                       ("'%c%c' ", v[0], v[1]));
36653         }
36654         else {
36655                 *len = 0;
36656 -               SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR,
36657 +               SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36658                         ("buffer overflow\n"));
36659                 return(2);
36660         }
36661
36662         v += 3 + VPD_GET_RES_LEN(v) + 3;
36663 -       for (;; ) {
36664 +
36665 +       for ( ; ; ) {
36666                 /* exit when reaching the "RW" Tag */
36667 -               if (SK_MEMCMP(VPD_RW,v,2) == 0) {
36668 +               if (SK_MEMCMP(VPD_RW, v, 2) == 0) {
36669                         break;
36670                 }
36671
36672 -               if (SK_MEMCMP(VPD_RV,v,2) == 0) {
36673 +               if (SK_MEMCMP(VPD_RV, v, 2) == 0) {
36674                         v += 3 + VPD_GET_VPD_LEN(v) + 3;        /* skip VPD-W */
36675                         continue;
36676                 }
36677
36678 -               if (n+3 <= *len) {
36679 -                       SK_MEMCPY(buf,v,2);
36680 +               if (n + 3 <= *len) {
36681 +                       SK_MEMCPY(buf, v, 2);
36682                         buf += 2;
36683                         *buf++ = '\0';
36684                         n += 3;
36685                         v += 3 + VPD_GET_VPD_LEN(v);
36686                         *elements += 1;
36687                         SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX,
36688 -                               ("'%c%c' ",v[0],v[1]));
36689 +                               ("'%c%c' ", v[0], v[1]));
36690                 }
36691                 else {
36692                         *len = n;
36693 @@ -867,6 +962,7 @@
36694         return(0);
36695  }
36696
36697 +#endif /* !SK_SLIM */
36698
36699  /*
36700   *     Read the contents of the VPD EEPROM and copy it to the
36701 @@ -882,7 +978,7 @@
36702   *             6:      fatal VPD error
36703   */
36704  int VpdRead(
36705 -SK_AC          *pAC,   /* common data base */
36706 +SK_AC          *pAC,   /* Adapters Context */
36707  SK_IOC         IoC,    /* IO Context */
36708  const char     *key,   /* keyword to read (e.g. "MN") */
36709  char           *buf,   /* buffer where to copy the keyword value */
36710 @@ -891,6 +987,7 @@
36711         SK_VPD_PARA *p, vp;
36712
36713         SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX, ("VPD read %s .. ", key));
36714 +
36715         if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) {
36716                 if (VpdInit(pAC, IoC) != 0) {
36717                         *len = 0;
36718 @@ -901,7 +998,7 @@
36719         }
36720
36721         if ((p = vpd_find_para(pAC, key, &vp)) != NULL) {
36722 -               if (p->p_len > (*(unsigned *)len)-1) {
36723 +               if (p->p_len > (*(unsigned *)len) - 1) {
36724                         p->p_len = *len - 1;
36725                 }
36726                 SK_MEMCPY(buf, p->p_val, p->p_len);
36727 @@ -909,7 +1006,7 @@
36728                 *len = p->p_len;
36729                 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX,
36730                         ("%c%c%c%c.., len = %d\n",
36731 -                       buf[0],buf[1],buf[2],buf[3],*len));
36732 +                       buf[0], buf[1], buf[2], buf[3], *len));
36733         }
36734         else {
36735                 *len = 0;
36736 @@ -919,7 +1016,7 @@
36737         return(0);
36738  }
36739
36740 -
36741 +#ifndef SK_SLIM
36742  /*
36743   *     Check whether a given key may be written
36744   *
36745 @@ -932,12 +1029,13 @@
36746  {
36747         if ((*key != 'Y' && *key != 'V') ||
36748                 key[1] < '0' || key[1] > 'Z' ||
36749 -               (key[1] > '9' && key[1] < 'A') || strlen(key) != 2) {
36750 +               (key[1] > '9' && key[1] < 'A') || SK_STRLEN(key) != 2) {
36751
36752                 return(SK_FALSE);
36753         }
36754         return(SK_TRUE);
36755  }
36756 +#endif /* !SK_SLIM */
36757
36758  /*
36759   *     Read the contents of the VPD EEPROM and copy it to the VPD
36760 @@ -953,7 +1051,7 @@
36761   *             6:      fatal VPD error
36762   */
36763  int VpdWrite(
36764 -SK_AC          *pAC,   /* common data base */
36765 +SK_AC          *pAC,   /* Adapters Context */
36766  SK_IOC         IoC,    /* IO Context */
36767  const char     *key,   /* keyword to write (allowed values "Yx", "Vx") */
36768  const char     *buf)   /* buffer where the keyword value can be read from */
36769 @@ -963,11 +1061,11 @@
36770         int rtv2;
36771
36772         SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX,
36773 -               ("VPD write %s = %s\n",key,buf));
36774 +               ("VPD write %s = %s\n", key, buf));
36775
36776         if ((*key != 'Y' && *key != 'V') ||
36777                 key[1] < '0' || key[1] > 'Z' ||
36778 -               (key[1] > '9' && key[1] < 'A') || strlen(key) != 2) {
36779 +               (key[1] > '9' && key[1] < 'A') || SK_STRLEN(key) != 2) {
36780
36781                 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36782                         ("illegal key tag, keyword not written\n"));
36783 @@ -983,13 +1081,13 @@
36784         }
36785
36786         rtv = 0;
36787 -       len = strlen(buf);
36788 +       len = SK_STRLEN(buf);
36789         if (len > VPD_MAX_LEN) {
36790                 /* cut it */
36791                 len = VPD_MAX_LEN;
36792                 rtv = 2;
36793                 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36794 -                       ("keyword too long, cut after %d bytes\n",VPD_MAX_LEN));
36795 +                       ("keyword too long, cut after %d bytes\n", VPD_MAX_LEN));
36796         }
36797         if ((rtv2 = VpdSetupPara(pAC, key, buf, len, VPD_RW_KEY, OWR_KEY)) != 0) {
36798                 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36799 @@ -1000,6 +1098,7 @@
36800         return(rtv);
36801  }
36802
36803 +#ifndef SK_SLIM
36804  /*
36805   *     Read the contents of the VPD EEPROM and copy it to the
36806   *     VPD buffer if not already done. Remove the VPD keyword
36807 @@ -1013,7 +1112,7 @@
36808   *             6:      fatal VPD error
36809   */
36810  int VpdDelete(
36811 -SK_AC  *pAC,   /* common data base */
36812 +SK_AC  *pAC,   /* Adapters Context */
36813  SK_IOC IoC,    /* IO Context */
36814  char   *key)   /* keyword to read (e.g. "MN") */
36815  {
36816 @@ -1023,7 +1122,7 @@
36817
36818         vpd_size = pAC->vpd.vpd_size;
36819
36820 -       SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_TX,("VPD delete key %s\n",key));
36821 +       SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX, ("VPD delete key %s\n", key));
36822         if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) {
36823                 if (VpdInit(pAC, IoC) != 0) {
36824                         SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36825 @@ -1042,7 +1141,7 @@
36826
36827                 etp = pAC->vpd.vpd_buf + (vpd_size-pAC->vpd.v.vpd_free_rw-1-3);
36828
36829 -               vpd_move_para(vp.p_val+vp.p_len, etp+2,
36830 +               vpd_move_para(vp.p_val + vp.p_len, etp + 2,
36831                         - ((int)(vp.p_len + 3)));
36832                 if (vpd_mod_endtag(pAC, etp - vp.p_len - 3)) {
36833                         pAC->vpd.v.vpd_status &= ~VPD_VALID;
36834 @@ -1059,6 +1158,7 @@
36835
36836         return(0);
36837  }
36838 +#endif /* !SK_SLIM */
36839
36840  /*
36841   *     If the VPD buffer contains valid data write the VPD
36842 @@ -1068,7 +1168,7 @@
36843   *             3:      VPD transfer timeout
36844   */
36845  int VpdUpdate(
36846 -SK_AC  *pAC,   /* Adapters context */
36847 +SK_AC  *pAC,   /* Adapters Context */
36848  SK_IOC IoC)    /* IO Context */
36849  {
36850         int vpd_size;
36851 @@ -1089,3 +1189,51 @@
36852         return(0);
36853  }
36854
36855 +#ifndef SK_SLIM
36856 +/*
36857 + *     Read the contents of the VPD EEPROM and copy it to the VPD buffer
36858 + *     if not already done. If the keyword "VF" is not present it will be
36859 + *     created and the error log message will be stored to this keyword.
36860 + *     If "VF" is not present the error log message will be stored to the
36861 + *     keyword "VL". "VL" will created or overwritten if "VF" is present.
36862 + *     The VPD read/write area is saved to the VPD EEPROM.
36863 + *
36864 + * returns nothing, errors will be ignored.
36865 + */
36866 +void VpdErrLog(
36867 +SK_AC  *pAC,   /* Adapters Context */
36868 +SK_IOC IoC,    /* IO Context */
36869 +char   *msg)   /* error log message */
36870 +{
36871 +       SK_VPD_PARA *v, vf;     /* VF */
36872 +       int len;
36873 +
36874 +       SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX,
36875 +               ("VPD error log msg %s\n", msg));
36876 +
36877 +       if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) {
36878 +               if (VpdInit(pAC, IoC) != 0) {
36879 +                       SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36880 +                               ("VPD init error\n"));
36881 +                       return;
36882 +               }
36883 +       }
36884 +
36885 +       len = SK_STRLEN(msg);
36886 +       if (len > VPD_MAX_LEN) {
36887 +               /* cut it */
36888 +               len = VPD_MAX_LEN;
36889 +       }
36890 +       if ((v = vpd_find_para(pAC, VPD_VF, &vf)) != NULL) {
36891 +               SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX, ("overwrite VL\n"));
36892 +               (void)VpdSetupPara(pAC, VPD_VL, msg, len, VPD_RW_KEY, OWR_KEY);
36893 +       }
36894 +       else {
36895 +               SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX, ("write VF\n"));
36896 +               (void)VpdSetupPara(pAC, VPD_VF, msg, len, VPD_RW_KEY, ADD_KEY);
36897 +       }
36898 +
36899 +       (void)VpdUpdate(pAC, IoC);
36900 +}
36901 +#endif /* !SK_SLIM */
36902 +
36903 diff -ruN linux/drivers/net/sk98lin/skxmac2.c linux-new/drivers/net/sk98lin/skxmac2.c
36904 --- linux/drivers/net/sk98lin/skxmac2.c 2006-09-20 05:42:06.000000000 +0200
36905 +++ linux-new/drivers/net/sk98lin/skxmac2.c     2006-07-28 14:13:54.000000000 +0200
36906 @@ -2,23 +2,24 @@
36907   *
36908   * Name:       skxmac2.c
36909   * Project:    Gigabit Ethernet Adapters, Common Modules
36910 - * Version:    $Revision$
36911 - * Date:       $Date$
36912 + * Version:    $Revision$
36913 + * Date:       $Date$
36914   * Purpose:    Contains functions to initialize the MACs and PHYs
36915   *
36916   ******************************************************************************/
36917
36918  /******************************************************************************
36919   *
36920 + *     LICENSE:
36921   *     (C)Copyright 1998-2002 SysKonnect.
36922 - *     (C)Copyright 2002-2003 Marvell.
36923 + *     (C)Copyright 2002-2006 Marvell.
36924   *
36925   *     This program is free software; you can redistribute it and/or modify
36926   *     it under the terms of the GNU General Public License as published by
36927   *     the Free Software Foundation; either version 2 of the License, or
36928   *     (at your option) any later version.
36929 - *
36930   *     The information in this file is provided "AS IS" without warranty.
36931 + *     /LICENSE
36932   *
36933   ******************************************************************************/
36934
36935 @@ -29,7 +30,7 @@
36936
36937  /* BCOM PHY magic pattern list */
36938  typedef struct s_PhyHack {
36939 -       int             PhyReg;         /* Phy register */
36940 +       int             PhyReg;         /* PHY register */
36941         SK_U16  PhyVal;         /* Value to write */
36942  } BCOM_HACK;
36943
36944 @@ -37,17 +38,17 @@
36945
36946  #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
36947  static const char SysKonnectFileId[] =
36948 -       "@(#) $Id$ (C) Marvell.";
36949 +       "@(#) $Id$ (C) Marvell.";
36950  #endif
36951
36952  #ifdef GENESIS
36953 -static BCOM_HACK BcomRegA1Hack[] = {
36954 +BCOM_HACK BcomRegA1Hack[] = {
36955   { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
36956   { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
36957   { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
36958   { 0, 0 }
36959  };
36960 -static BCOM_HACK BcomRegC0Hack[] = {
36961 +BCOM_HACK BcomRegC0Hack[] = {
36962   { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 }, { 0x17, 0x0013 },
36963   { 0x15, 0x0A04 }, { 0x18, 0x0420 },
36964   { 0, 0 }
36965 @@ -83,7 +84,7 @@
36966   * Returns:
36967   *     nothing
36968   */
36969 -void SkXmPhyRead(
36970 +int SkXmPhyRead(
36971  SK_AC  *pAC,                   /* Adapter Context */
36972  SK_IOC IoC,                    /* I/O Context */
36973  int            Port,                   /* Port Index (MAC_1 + n) */
36974 @@ -94,13 +95,13 @@
36975         SK_GEPORT       *pPrt;
36976
36977         pPrt = &pAC->GIni.GP[Port];
36978 -
36979 +
36980         /* write the PHY register's address */
36981         XM_OUT16(IoC, Port, XM_PHY_ADDR, PhyReg | pPrt->PhyAddr);
36982 -
36983 +
36984         /* get the PHY register's value */
36985         XM_IN16(IoC, Port, XM_PHY_DATA, pVal);
36986 -
36987 +
36988         if (pPrt->PhyType != SK_PHY_XMAC) {
36989                 do {
36990                         XM_IN16(IoC, Port, XM_MMU_CMD, &Mmu);
36991 @@ -110,6 +111,8 @@
36992                 /* get the PHY register's value */
36993                 XM_IN16(IoC, Port, XM_PHY_DATA, pVal);
36994         }
36995 +
36996 +       return(0);
36997  }      /* SkXmPhyRead */
36998
36999
37000 @@ -122,7 +125,7 @@
37001   * Returns:
37002   *     nothing
37003   */
37004 -void SkXmPhyWrite(
37005 +int SkXmPhyWrite(
37006  SK_AC  *pAC,           /* Adapter Context */
37007  SK_IOC IoC,            /* I/O Context */
37008  int            Port,           /* Port Index (MAC_1 + n) */
37009 @@ -133,26 +136,28 @@
37010         SK_GEPORT       *pPrt;
37011
37012         pPrt = &pAC->GIni.GP[Port];
37013 -
37014 +
37015         if (pPrt->PhyType != SK_PHY_XMAC) {
37016                 do {
37017                         XM_IN16(IoC, Port, XM_MMU_CMD, &Mmu);
37018                         /* wait until 'Busy' is cleared */
37019                 } while ((Mmu & XM_MMU_PHY_BUSY) != 0);
37020         }
37021 -
37022 +
37023         /* write the PHY register's address */
37024         XM_OUT16(IoC, Port, XM_PHY_ADDR, PhyReg | pPrt->PhyAddr);
37025 -
37026 +
37027         /* write the PHY register's value */
37028         XM_OUT16(IoC, Port, XM_PHY_DATA, Val);
37029 -
37030 +
37031         if (pPrt->PhyType != SK_PHY_XMAC) {
37032                 do {
37033                         XM_IN16(IoC, Port, XM_MMU_CMD, &Mmu);
37034                         /* wait until 'Busy' is cleared */
37035                 } while ((Mmu & XM_MMU_PHY_BUSY) != 0);
37036         }
37037 +
37038 +       return(0);
37039  }      /* SkXmPhyWrite */
37040  #endif /* GENESIS */
37041
37042 @@ -165,63 +170,97 @@
37043   * Description:        reads a 16-bit word from GPHY through MDIO
37044   *
37045   * Returns:
37046 - *     nothing
37047 + *     0       o.k.
37048 + *     1       error during MDIO read
37049 + *     2       timeout
37050   */
37051 -void SkGmPhyRead(
37052 +int SkGmPhyRead(
37053  SK_AC  *pAC,                   /* Adapter Context */
37054  SK_IOC IoC,                    /* I/O Context */
37055  int            Port,                   /* Port Index (MAC_1 + n) */
37056  int            PhyReg,                 /* Register Address (Offset) */
37057  SK_U16 SK_FAR *pVal)   /* Pointer to Value */
37058  {
37059 +       SK_U16  Word;
37060         SK_U16  Ctrl;
37061         SK_GEPORT       *pPrt;
37062 -#ifdef VCPU
37063 -       u_long SimCyle;
37064 -       u_long SimLowTime;
37065 -
37066 -       VCPUgetTime(&SimCyle, &SimLowTime);
37067 -       VCPUprintf(0, "SkGmPhyRead(%u), SimCyle=%u, SimLowTime=%u\n",
37068 -               PhyReg, SimCyle, SimLowTime);
37069 -#endif /* VCPU */
37070 -
37071 +       SK_U32  StartTime;
37072 +       SK_U32  CurrTime;
37073 +       SK_U32  Delta;
37074 +       SK_U32  TimeOut;
37075 +       int             Rtv;
37076 +
37077 +       Rtv = 0;
37078 +
37079 +       *pVal = 0xffff;
37080 +
37081         pPrt = &pAC->GIni.GP[Port];
37082 -
37083 +
37084         /* set PHY-Register offset and 'Read' OpCode (= 1) */
37085 -       *pVal = (SK_U16)(GM_SMI_CT_PHY_AD(pPrt->PhyAddr) |
37086 +       Word = (SK_U16)(GM_SMI_CT_PHY_AD(pPrt->PhyAddr) |
37087                 GM_SMI_CT_REG_AD(PhyReg) | GM_SMI_CT_OP_RD);
37088
37089 -       GM_OUT16(IoC, Port, GM_SMI_CTRL, *pVal);
37090 +       GM_OUT16(IoC, Port, GM_SMI_CTRL, Word);
37091
37092 -       GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);
37093 -
37094         /* additional check for MDC/MDIO activity */
37095 -       if ((Ctrl & GM_SMI_CT_BUSY) == 0) {
37096 -               *pVal = 0;
37097 -               return;
37098 +       GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);
37099 +
37100 +       if (Ctrl == 0xffff || (Ctrl & GM_SMI_CT_OP_RD) == 0) {
37101 +
37102 +               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
37103 +                       ("PHY read impossible on Port %d (Ctrl=0x%04x)\n", Port, Ctrl));
37104 +
37105 +               return(1);
37106         }
37107
37108 -       *pVal |= GM_SMI_CT_BUSY;
37109 -
37110 -       do {
37111 +       Word |= GM_SMI_CT_BUSY;
37112 +
37113 +       SK_IN32(IoC, GMAC_TI_ST_VAL, &StartTime);
37114 +
37115 +       /* set timeout to 10 ms */
37116 +       TimeOut = HW_MS_TO_TICKS(pAC, 10);
37117 +
37118 +       do {    /* wait until 'Busy' is cleared and 'ReadValid' is set */
37119  #ifdef VCPU
37120                 VCPUwaitTime(1000);
37121  #endif /* VCPU */
37122
37123 +               SK_IN32(IoC, GMAC_TI_ST_VAL, &CurrTime);
37124 +
37125 +               if (CurrTime >= StartTime) {
37126 +                       Delta = CurrTime - StartTime;
37127 +               }
37128 +               else {
37129 +                       Delta = CurrTime + ~StartTime + 1;
37130 +               }
37131 +
37132 +               if (Delta > TimeOut) {
37133 +
37134 +                       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
37135 +                               ("PHY read timeout on Port %d (Ctrl=0x%04x)\n", Port, Ctrl));
37136 +                       Rtv = 2;
37137 +                       break;
37138 +               }
37139 +
37140                 GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);
37141
37142 -       /* wait until 'ReadValid' is set */
37143 -       } while (Ctrl == *pVal);
37144 -
37145 -       /* get the PHY register's value */
37146 +               /* Error on reading SMI Control Register */
37147 +               if (Ctrl == 0xffff) {
37148 +                       return(1);
37149 +               }
37150 +
37151 +       } while ((Ctrl ^ Word) != (GM_SMI_CT_RD_VAL | GM_SMI_CT_BUSY));
37152 +
37153         GM_IN16(IoC, Port, GM_SMI_DATA, pVal);
37154
37155 -#ifdef VCPU
37156 -       VCPUgetTime(&SimCyle, &SimLowTime);
37157 -       VCPUprintf(0, "VCPUgetTime(), SimCyle=%u, SimLowTime=%u\n",
37158 -               SimCyle, SimLowTime);
37159 -#endif /* VCPU */
37160 +       /* dummy read after GM_IN16() */
37161 +       SK_IN32(IoC, GMAC_TI_ST_VAL, &CurrTime);
37162
37163 +       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
37164 +               ("SkGmPhyRead Port:%d, Reg=%d, Val = 0x%04X\n",
37165 +                Port, PhyReg, *pVal));
37166 +
37167 +       return(Rtv);
37168  }      /* SkGmPhyRead */
37169
37170
37171 @@ -232,9 +271,11 @@
37172   * Description:        writes a 16-bit word to GPHY through MDIO
37173   *
37174   * Returns:
37175 - *     nothing
37176 + *     0       o.k.
37177 + *     1       error during MDIO read
37178 + *     2       timeout
37179   */
37180 -void SkGmPhyWrite(
37181 +int SkGmPhyWrite(
37182  SK_AC  *pAC,           /* Adapter Context */
37183  SK_IOC IoC,            /* I/O Context */
37184  int            Port,           /* Port Index (MAC_1 + n) */
37185 @@ -243,54 +284,78 @@
37186  {
37187         SK_U16  Ctrl;
37188         SK_GEPORT       *pPrt;
37189 -#ifdef VCPU
37190 -       SK_U32  DWord;
37191 -       u_long  SimCyle;
37192 -       u_long  SimLowTime;
37193 -
37194 -       VCPUgetTime(&SimCyle, &SimLowTime);
37195 -       VCPUprintf(0, "SkGmPhyWrite(Reg=%u, Val=0x%04x), SimCyle=%u, SimLowTime=%u\n",
37196 -               PhyReg, Val, SimCyle, SimLowTime);
37197 -#endif /* VCPU */
37198 -
37199 +       SK_U32  StartTime;
37200 +       SK_U32  CurrTime;
37201 +       SK_U32  Delta;
37202 +       SK_U32  TimeOut;
37203 +
37204 +       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
37205 +               ("SkGmPhyWrite Port:%d, Reg=%d, Val = 0x%04X\n",
37206 +                Port, PhyReg, Val));
37207 +
37208         pPrt = &pAC->GIni.GP[Port];
37209 -
37210 +
37211         /* write the PHY register's value */
37212         GM_OUT16(IoC, Port, GM_SMI_DATA, Val);
37213 -
37214 -       /* set PHY-Register offset and 'Write' OpCode (= 0) */
37215 -       Val = GM_SMI_CT_PHY_AD(pPrt->PhyAddr) | GM_SMI_CT_REG_AD(PhyReg);
37216
37217 -       GM_OUT16(IoC, Port, GM_SMI_CTRL, Val);
37218 -
37219 -       GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);
37220 -
37221 +#ifdef DEBUG
37222         /* additional check for MDC/MDIO activity */
37223 -       if ((Ctrl & GM_SMI_CT_BUSY) == 0) {
37224 -               return;
37225 +       GM_IN16(IoC, Port, GM_SMI_DATA, &Ctrl);
37226 +
37227 +       if (Ctrl != Val) {
37228 +
37229 +               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
37230 +                       ("PHY write impossible on Port %d (Val=0x%04x)\n", Port, Ctrl));
37231 +
37232 +               return(1);
37233         }
37234 -
37235 -       Val |= GM_SMI_CT_BUSY;
37236 +#endif /* DEBUG */
37237
37238 -       do {
37239 -#ifdef VCPU
37240 -               /* read Timer value */
37241 -               SK_IN32(IoC, B2_TI_VAL, &DWord);
37242 +       /* set PHY-Register offset and 'Write' OpCode (= 0) */
37243 +       Ctrl = (SK_U16)(GM_SMI_CT_PHY_AD(pPrt->PhyAddr) |
37244 +               GM_SMI_CT_REG_AD(PhyReg));
37245
37246 +       GM_OUT16(IoC, Port, GM_SMI_CTRL, Ctrl);
37247 +
37248 +       SK_IN32(IoC, GMAC_TI_ST_VAL, &StartTime);
37249 +
37250 +       /* set timeout to 10 ms */
37251 +       TimeOut = HW_MS_TO_TICKS(pAC, 10);
37252 +
37253 +       do {    /* wait until 'Busy' is cleared */
37254 +#ifdef VCPU
37255                 VCPUwaitTime(1000);
37256  #endif /* VCPU */
37257
37258 +               SK_IN32(IoC, GMAC_TI_ST_VAL, &CurrTime);
37259 +
37260 +               if (CurrTime >= StartTime) {
37261 +                       Delta = CurrTime - StartTime;
37262 +               }
37263 +               else {
37264 +                       Delta = CurrTime + ~StartTime + 1;
37265 +               }
37266 +
37267 +               if (Delta > TimeOut) {
37268 +
37269 +                       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
37270 +                               ("PHY write timeout on Port %d (Ctrl=0x%04x)\n", Port, Ctrl));
37271 +                       return(2);
37272 +               }
37273 +
37274                 GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);
37275
37276 -       /* wait until 'Busy' is cleared */
37277 -       } while (Ctrl == Val);
37278 -
37279 -#ifdef VCPU
37280 -       VCPUgetTime(&SimCyle, &SimLowTime);
37281 -       VCPUprintf(0, "VCPUgetTime(), SimCyle=%u, SimLowTime=%u\n",
37282 -               SimCyle, SimLowTime);
37283 -#endif /* VCPU */
37284 +               /* Error on reading SMI Control Register */
37285 +               if (Ctrl == 0xffff) {
37286 +                       return(1);
37287 +               }
37288
37289 +       } while ((Ctrl & GM_SMI_CT_BUSY) != 0);
37290 +
37291 +       /* dummy read after GM_IN16() */
37292 +       SK_IN32(IoC, GMAC_TI_ST_VAL, &CurrTime);
37293 +
37294 +       return(0);
37295  }      /* SkGmPhyWrite */
37296  #endif /* YUKON */
37297
37298 @@ -312,16 +377,8 @@
37299  int            PhyReg,         /* Register Address (Offset) */
37300  SK_U16 *pVal)          /* Pointer to Value */
37301  {
37302 -       void (*r_func)(SK_AC *pAC, SK_IOC IoC, int Port, int Reg, SK_U16 *pVal);
37303
37304 -       if (pAC->GIni.GIGenesis) {
37305 -               r_func = SkXmPhyRead;
37306 -       }
37307 -       else {
37308 -               r_func = SkGmPhyRead;
37309 -       }
37310 -
37311 -       r_func(pAC, IoC, Port, PhyReg, pVal);
37312 +       pAC->GIni.GIFunc.pFnMacPhyRead(pAC, IoC, Port, PhyReg, pVal);
37313  }      /* SkGePhyRead */
37314
37315
37316 @@ -341,16 +398,8 @@
37317  int            PhyReg,         /* Register Address (Offset) */
37318  SK_U16 Val)            /* Value */
37319  {
37320 -       void (*w_func)(SK_AC *pAC, SK_IOC IoC, int Port, int Reg, SK_U16 Val);
37321
37322 -       if (pAC->GIni.GIGenesis) {
37323 -               w_func = SkXmPhyWrite;
37324 -       }
37325 -       else {
37326 -               w_func = SkGmPhyWrite;
37327 -       }
37328 -
37329 -       w_func(pAC, IoC, Port, PhyReg, Val);
37330 +       pAC->GIni.GIFunc.pFnMacPhyWrite(pAC, IoC, Port, PhyReg, Val);
37331  }      /* SkGePhyWrite */
37332  #endif /* SK_DIAG */
37333
37334 @@ -360,15 +409,15 @@
37335   *     SkMacPromiscMode() - Enable / Disable Promiscuous Mode
37336   *
37337   * Description:
37338 - *   enables / disables promiscuous mode by setting Mode Register (XMAC) or
37339 - *   Receive Control Register (GMAC) dep. on board type
37340 + *     enables / disables promiscuous mode by setting Mode Register (XMAC) or
37341 + *     Receive Control Register (GMAC) dep. on board type
37342   *
37343   * Returns:
37344   *     nothing
37345   */
37346  void SkMacPromiscMode(
37347 -SK_AC  *pAC,   /* adapter context */
37348 -SK_IOC IoC,    /* IO context */
37349 +SK_AC  *pAC,   /* Adapter Context */
37350 +SK_IOC IoC,    /* I/O Context */
37351  int            Port,   /* Port Index (MAC_1 + n) */
37352  SK_BOOL        Enable) /* Enable / Disable */
37353  {
37354 @@ -377,11 +426,11 @@
37355  #endif
37356  #ifdef GENESIS
37357         SK_U32  MdReg;
37358 -#endif
37359 +#endif
37360
37361  #ifdef GENESIS
37362         if (pAC->GIni.GIGenesis) {
37363 -
37364 +
37365                 XM_IN32(IoC, Port, XM_MODE, &MdReg);
37366                 /* enable or disable promiscuous mode */
37367                 if (Enable) {
37368 @@ -394,12 +443,12 @@
37369                 XM_OUT32(IoC, Port, XM_MODE, MdReg);
37370         }
37371  #endif /* GENESIS */
37372 -
37373 +
37374  #ifdef YUKON
37375         if (pAC->GIni.GIYukon) {
37376 -
37377 +
37378                 GM_IN16(IoC, Port, GM_RX_CTRL, &RcReg);
37379 -
37380 +
37381                 /* enable or disable unicast and multicast filtering */
37382                 if (Enable) {
37383                         RcReg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
37384 @@ -420,28 +469,28 @@
37385   *     SkMacHashing() - Enable / Disable Hashing
37386   *
37387   * Description:
37388 - *   enables / disables hashing by setting Mode Register (XMAC) or
37389 - *   Receive Control Register (GMAC) dep. on board type
37390 + *     enables / disables hashing by setting Mode Register (XMAC) or
37391 + *     Receive Control Register (GMAC) dep. on board type
37392   *
37393   * Returns:
37394   *     nothing
37395   */
37396  void SkMacHashing(
37397 -SK_AC  *pAC,   /* adapter context */
37398 -SK_IOC IoC,    /* IO context */
37399 +SK_AC  *pAC,   /* Adapter Context */
37400 +SK_IOC IoC,    /* I/O Context */
37401  int            Port,   /* Port Index (MAC_1 + n) */
37402  SK_BOOL        Enable) /* Enable / Disable */
37403  {
37404  #ifdef YUKON
37405         SK_U16  RcReg;
37406 -#endif
37407 +#endif
37408  #ifdef GENESIS
37409         SK_U32  MdReg;
37410  #endif
37411
37412  #ifdef GENESIS
37413         if (pAC->GIni.GIGenesis) {
37414 -
37415 +
37416                 XM_IN32(IoC, Port, XM_MODE, &MdReg);
37417                 /* enable or disable hashing */
37418                 if (Enable) {
37419 @@ -454,12 +503,12 @@
37420                 XM_OUT32(IoC, Port, XM_MODE, MdReg);
37421         }
37422  #endif /* GENESIS */
37423 -
37424 +
37425  #ifdef YUKON
37426         if (pAC->GIni.GIYukon) {
37427 -
37428 +
37429                 GM_IN16(IoC, Port, GM_RX_CTRL, &RcReg);
37430 -
37431 +
37432                 /* enable or disable multicast filtering */
37433                 if (Enable) {
37434                         RcReg |= GM_RXCR_MCF_ENA;
37435 @@ -487,8 +536,8 @@
37436   *      - don't set XMR_FS_ERR in status       SK_LENERR_OK_ON/OFF
37437   *        for inrange length error frames
37438   *      - don't set XMR_FS_ERR in status       SK_BIG_PK_OK_ON/OFF
37439 - *        for frames > 1514 bytes
37440 - *   - enable Rx of own packets         SK_SELF_RX_ON/OFF
37441 + *             for frames > 1514 bytes
37442 + *     - enable Rx of own packets                      SK_SELF_RX_ON/OFF
37443   *
37444   *     for incoming packets may be enabled/disabled by this function.
37445   *     Additional modes may be added later.
37446 @@ -499,11 +548,11 @@
37447   *     nothing
37448   */
37449  static void SkXmSetRxCmd(
37450 -SK_AC  *pAC,           /* adapter context */
37451 -SK_IOC IoC,            /* IO context */
37452 +SK_AC  *pAC,           /* Adapter Context */
37453 +SK_IOC IoC,            /* I/O Context */
37454  int            Port,           /* Port Index (MAC_1 + n) */
37455  int            Mode)           /* Mode is SK_STRIP_FCS_ON/OFF, SK_STRIP_PAD_ON/OFF,
37456 -                                          SK_LENERR_OK_ON/OFF, or SK_BIG_PK_OK_ON/OFF */
37457 +                                               SK_LENERR_OK_ON/OFF, or SK_BIG_PK_OK_ON/OFF */
37458  {
37459         SK_U16  OldRxCmd;
37460         SK_U16  RxCmd;
37461 @@ -511,7 +560,7 @@
37462         XM_IN16(IoC, Port, XM_RX_CMD, &OldRxCmd);
37463
37464         RxCmd = OldRxCmd;
37465 -
37466 +
37467         switch (Mode & (SK_STRIP_FCS_ON | SK_STRIP_FCS_OFF)) {
37468         case SK_STRIP_FCS_ON:
37469                 RxCmd |= XM_RX_STRIP_FCS;
37470 @@ -572,8 +621,8 @@
37471   *     The features
37472   *      - FCS (CRC) stripping,                         SK_STRIP_FCS_ON/OFF
37473   *      - don't set GMR_FS_LONG_ERR            SK_BIG_PK_OK_ON/OFF
37474 - *        for frames > 1514 bytes
37475 - *   - enable Rx of own packets         SK_SELF_RX_ON/OFF
37476 + *             for frames > 1514 bytes
37477 + *     - enable Rx of own packets                      SK_SELF_RX_ON/OFF
37478   *
37479   *     for incoming packets may be enabled/disabled by this function.
37480   *     Additional modes may be added later.
37481 @@ -584,20 +633,17 @@
37482   *     nothing
37483   */
37484  static void SkGmSetRxCmd(
37485 -SK_AC  *pAC,           /* adapter context */
37486 -SK_IOC IoC,            /* IO context */
37487 +SK_AC  *pAC,           /* Adapter Context */
37488 +SK_IOC IoC,            /* I/O Context */
37489  int            Port,           /* Port Index (MAC_1 + n) */
37490  int            Mode)           /* Mode is SK_STRIP_FCS_ON/OFF, SK_STRIP_PAD_ON/OFF,
37491 -                                          SK_LENERR_OK_ON/OFF, or SK_BIG_PK_OK_ON/OFF */
37492 +                                               SK_LENERR_OK_ON/OFF, or SK_BIG_PK_OK_ON/OFF */
37493  {
37494 -       SK_U16  OldRxCmd;
37495         SK_U16  RxCmd;
37496
37497         if ((Mode & (SK_STRIP_FCS_ON | SK_STRIP_FCS_OFF)) != 0) {
37498 -
37499 -               GM_IN16(IoC, Port, GM_RX_CTRL, &OldRxCmd);
37500
37501 -               RxCmd = OldRxCmd;
37502 +               GM_IN16(IoC, Port, GM_RX_CTRL, &RxCmd);
37503
37504                 if ((Mode & SK_STRIP_FCS_ON) != 0) {
37505                         RxCmd |= GM_RXCR_CRC_DIS;
37506 @@ -605,17 +651,13 @@
37507                 else {
37508                         RxCmd &= ~GM_RXCR_CRC_DIS;
37509                 }
37510 -               /* Write the new mode to the Rx control register if required */
37511 -               if (OldRxCmd != RxCmd) {
37512 -                       GM_OUT16(IoC, Port, GM_RX_CTRL, RxCmd);
37513 -               }
37514 +               /* Write the new mode to the Rx Control register */
37515 +               GM_OUT16(IoC, Port, GM_RX_CTRL, RxCmd);
37516         }
37517
37518         if ((Mode & (SK_BIG_PK_OK_ON | SK_BIG_PK_OK_OFF)) != 0) {
37519 -
37520 -               GM_IN16(IoC, Port, GM_SERIAL_MODE, &OldRxCmd);
37521
37522 -               RxCmd = OldRxCmd;
37523 +               GM_IN16(IoC, Port, GM_SERIAL_MODE, &RxCmd);
37524
37525                 if ((Mode & SK_BIG_PK_OK_ON) != 0) {
37526                         RxCmd |= GM_SMOD_JUMBO_ENA;
37527 @@ -623,10 +665,8 @@
37528                 else {
37529                         RxCmd &= ~GM_SMOD_JUMBO_ENA;
37530                 }
37531 -               /* Write the new mode to the Rx control register if required */
37532 -               if (OldRxCmd != RxCmd) {
37533 -                       GM_OUT16(IoC, Port, GM_SERIAL_MODE, RxCmd);
37534 -               }
37535 +               /* Write the new mode to the Serial Mode register */
37536 +               GM_OUT16(IoC, Port, GM_SERIAL_MODE, RxCmd);
37537         }
37538  }      /* SkGmSetRxCmd */
37539
37540 @@ -641,17 +681,17 @@
37541   *     nothing
37542   */
37543  void SkMacSetRxCmd(
37544 -SK_AC  *pAC,           /* adapter context */
37545 -SK_IOC IoC,            /* IO context */
37546 +SK_AC  *pAC,           /* Adapter Context */
37547 +SK_IOC IoC,            /* I/O Context */
37548  int            Port,           /* Port Index (MAC_1 + n) */
37549  int            Mode)           /* Rx Mode */
37550  {
37551         if (pAC->GIni.GIGenesis) {
37552 -
37553 +
37554                 SkXmSetRxCmd(pAC, IoC, Port, Mode);
37555         }
37556         else {
37557 -
37558 +
37559                 SkGmSetRxCmd(pAC, IoC, Port, Mode);
37560         }
37561
37562 @@ -668,15 +708,15 @@
37563   *     nothing
37564   */
37565  void SkMacCrcGener(
37566 -SK_AC  *pAC,   /* adapter context */
37567 -SK_IOC IoC,    /* IO context */
37568 +SK_AC  *pAC,   /* Adapter Context */
37569 +SK_IOC IoC,    /* I/O Context */
37570  int            Port,   /* Port Index (MAC_1 + n) */
37571  SK_BOOL        Enable) /* Enable / Disable */
37572  {
37573         SK_U16  Word;
37574
37575         if (pAC->GIni.GIGenesis) {
37576 -
37577 +
37578                 XM_IN16(IoC, Port, XM_TX_CMD, &Word);
37579
37580                 if (Enable) {
37581 @@ -689,9 +729,9 @@
37582                 XM_OUT16(IoC, Port, XM_TX_CMD, Word);
37583         }
37584         else {
37585 -
37586 +
37587                 GM_IN16(IoC, Port, GM_TX_CTRL, &Word);
37588 -
37589 +
37590                 if (Enable) {
37591                         Word &= ~GM_TXCR_CRC_DIS;
37592                 }
37593 @@ -721,14 +761,14 @@
37594   *     nothing
37595   */
37596  void SkXmClrExactAddr(
37597 -SK_AC  *pAC,           /* adapter context */
37598 -SK_IOC IoC,            /* IO context */
37599 +SK_AC  *pAC,           /* Adapter Context */
37600 +SK_IOC IoC,            /* I/O Context */
37601  int            Port,           /* Port Index (MAC_1 + n) */
37602  int            StartNum,       /* Begin with this Address Register Index (0..15) */
37603  int            StopNum)        /* Stop after finished with this Register Idx (0..15) */
37604  {
37605         int             i;
37606 -       SK_U16  ZeroAddr[3] = {0x0000, 0x0000, 0x0000};
37607 +       SK_U16  ZeroAddr[3] = {0, 0, 0};
37608
37609         if ((unsigned)StartNum > 15 || (unsigned)StopNum > 15 ||
37610                 StartNum > StopNum) {
37611 @@ -738,7 +778,7 @@
37612         }
37613
37614         for (i = StartNum; i <= StopNum; i++) {
37615 -               XM_OUTADDR(IoC, Port, XM_EXM(i), &ZeroAddr[0]);
37616 +               XM_OUTADDR(IoC, Port, XM_EXM(i), ZeroAddr);
37617         }
37618  }      /* SkXmClrExactAddr */
37619  #endif /* GENESIS */
37620 @@ -755,21 +795,21 @@
37621   *     nothing
37622   */
37623  void SkMacFlushTxFifo(
37624 -SK_AC  *pAC,   /* adapter context */
37625 -SK_IOC IoC,    /* IO context */
37626 +SK_AC  *pAC,   /* Adapter Context */
37627 +SK_IOC IoC,    /* I/O Context */
37628  int            Port)   /* Port Index (MAC_1 + n) */
37629  {
37630  #ifdef GENESIS
37631         SK_U32  MdReg;
37632
37633         if (pAC->GIni.GIGenesis) {
37634 -
37635 +
37636                 XM_IN32(IoC, Port, XM_MODE, &MdReg);
37637
37638                 XM_OUT32(IoC, Port, XM_MODE, MdReg | XM_MD_FTF);
37639         }
37640  #endif /* GENESIS */
37641 -
37642 +
37643  #ifdef YUKON
37644         if (pAC->GIni.GIYukon) {
37645                 /* no way to flush the FIFO we have to issue a reset */
37646 @@ -790,9 +830,9 @@
37647   * Returns:
37648   *     nothing
37649   */
37650 -static void SkMacFlushRxFifo(
37651 -SK_AC  *pAC,   /* adapter context */
37652 -SK_IOC IoC,    /* IO context */
37653 +void SkMacFlushRxFifo(
37654 +SK_AC  *pAC,   /* Adapter Context */
37655 +SK_IOC IoC,    /* I/O Context */
37656  int            Port)   /* Port Index (MAC_1 + n) */
37657  {
37658  #ifdef GENESIS
37659 @@ -805,7 +845,7 @@
37660                 XM_OUT32(IoC, Port, XM_MODE, MdReg | XM_MD_FRF);
37661         }
37662  #endif /* GENESIS */
37663 -
37664 +
37665  #ifdef YUKON
37666         if (pAC->GIni.GIYukon) {
37667                 /* no way to flush the FIFO we have to issue a reset */
37668 @@ -853,23 +893,23 @@
37669   *     nothing
37670   */
37671  static void SkXmSoftRst(
37672 -SK_AC  *pAC,   /* adapter context */
37673 -SK_IOC IoC,    /* IO context */
37674 +SK_AC  *pAC,   /* Adapter Context */
37675 +SK_IOC IoC,    /* I/O Context */
37676  int            Port)   /* Port Index (MAC_1 + n) */
37677  {
37678 -       SK_U16  ZeroAddr[4] = {0x0000, 0x0000, 0x0000, 0x0000};
37679 -
37680 +       SK_U16  ZeroAddr[4] = {0, 0, 0, 0};
37681 +
37682         /* reset the statistics module */
37683         XM_OUT32(IoC, Port, XM_GP_PORT, XM_GP_RES_STAT);
37684
37685         /* disable all XMAC IRQs */
37686         XM_OUT16(IoC, Port, XM_IMSK, 0xffff);
37687 -
37688 +
37689         XM_OUT32(IoC, Port, XM_MODE, 0);                /* clear Mode Reg */
37690 -
37691 +
37692         XM_OUT16(IoC, Port, XM_TX_CMD, 0);              /* reset TX CMD Reg */
37693         XM_OUT16(IoC, Port, XM_RX_CMD, 0);              /* reset RX CMD Reg */
37694 -
37695 +
37696         /* disable all PHY IRQs */
37697         switch (pAC->GIni.GP[Port].PhyType) {
37698         case SK_PHY_BCOM:
37699 @@ -887,13 +927,13 @@
37700         }
37701
37702         /* clear the Hash Register */
37703 -       XM_OUTHASH(IoC, Port, XM_HSM, &ZeroAddr);
37704 +       XM_OUTHASH(IoC, Port, XM_HSM, ZeroAddr);
37705
37706         /* clear the Exact Match Address registers */
37707         SkXmClrExactAddr(pAC, IoC, Port, 0, 15);
37708 -
37709 +
37710         /* clear the Source Check Address registers */
37711 -       XM_OUTHASH(IoC, Port, XM_SRC_CHK, &ZeroAddr);
37712 +       XM_OUTHASH(IoC, Port, XM_SRC_CHK, ZeroAddr);
37713
37714  }      /* SkXmSoftRst */
37715
37716 @@ -916,8 +956,8 @@
37717   *     nothing
37718   */
37719  static void SkXmHardRst(
37720 -SK_AC  *pAC,   /* adapter context */
37721 -SK_IOC IoC,    /* IO context */
37722 +SK_AC  *pAC,   /* Adapter Context */
37723 +SK_IOC IoC,    /* I/O Context */
37724  int            Port)   /* Port Index (MAC_1 + n) */
37725  {
37726         SK_U32  Reg;
37727 @@ -940,19 +980,19 @@
37728                         }
37729
37730                         SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
37731 -
37732 +
37733                         SK_IN16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), &Word);
37734 -
37735 +
37736                 } while ((Word & MFF_SET_MAC_RST) == 0);
37737         }
37738
37739         /* For external PHYs there must be special handling */
37740         if (pAC->GIni.GP[Port].PhyType != SK_PHY_XMAC) {
37741 -
37742 +
37743                 SK_IN32(IoC, B2_GP_IO, &Reg);
37744 -
37745 +
37746                 if (Port == 0) {
37747 -                       Reg |= GP_DIR_0;        /* set to output */
37748 +                       Reg |= GP_DIR_0;        /* set to output */
37749                         Reg &= ~GP_IO_0;        /* set PHY reset (active low) */
37750                 }
37751                 else {
37752 @@ -978,12 +1018,12 @@
37753   *     nothing
37754   */
37755  static void SkXmClearRst(
37756 -SK_AC  *pAC,   /* adapter context */
37757 -SK_IOC IoC,    /* IO context */
37758 +SK_AC  *pAC,   /* Adapter Context */
37759 +SK_IOC IoC,    /* I/O Context */
37760  int            Port)   /* Port Index (MAC_1 + n) */
37761  {
37762         SK_U32  DWord;
37763 -
37764 +
37765         /* clear HW reset */
37766         SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
37767
37768 @@ -1000,7 +1040,7 @@
37769                 /* Clear PHY reset */
37770                 SK_OUT32(IoC, B2_GP_IO, DWord);
37771
37772 -               /* Enable GMII interface */
37773 +               /* enable GMII interface */
37774                 XM_OUT16(IoC, Port, XM_HW_CFG, XM_HW_GMII_MD);
37775         }
37776  }      /* SkXmClearRst */
37777 @@ -1020,29 +1060,28 @@
37778   *     nothing
37779   */
37780  static void SkGmSoftRst(
37781 -SK_AC  *pAC,   /* adapter context */
37782 -SK_IOC IoC,    /* IO context */
37783 +SK_AC  *pAC,   /* Adapter Context */
37784 +SK_IOC IoC,    /* I/O Context */
37785  int            Port)   /* Port Index (MAC_1 + n) */
37786  {
37787 -       SK_U16  EmptyHash[4] = {0x0000, 0x0000, 0x0000, 0x0000};
37788 -       SK_U16  RxCtrl;
37789 +       SK_U16  EmptyHash[4] = { 0x0000, 0x0000, 0x0000, 0x0000 };
37790 +       SK_U16  RxCtrl;
37791
37792         /* reset the statistics module */
37793
37794         /* disable all GMAC IRQs */
37795 -       SK_OUT8(IoC, GMAC_IRQ_MSK, 0);
37796 -
37797 +       SK_OUT8(IoC, MR_ADDR(Port, GMAC_IRQ_MSK), 0);
37798 +
37799         /* disable all PHY IRQs */
37800         SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, 0);
37801 -
37802 +
37803         /* clear the Hash Register */
37804         GM_OUTHASH(IoC, Port, GM_MC_ADDR_H1, EmptyHash);
37805
37806 -       /* Enable Unicast and Multicast filtering */
37807 +       /* enable Unicast and Multicast filtering */
37808         GM_IN16(IoC, Port, GM_RX_CTRL, &RxCtrl);
37809 -
37810 -       GM_OUT16(IoC, Port, GM_RX_CTRL,
37811 -               (SK_U16)(RxCtrl | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA));
37812 +
37813 +       GM_OUT16(IoC, Port, GM_RX_CTRL, RxCtrl | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
37814
37815  }      /* SkGmSoftRst */
37816
37817 @@ -1057,16 +1096,16 @@
37818   *     nothing
37819   */
37820  static void SkGmHardRst(
37821 -SK_AC  *pAC,   /* adapter context */
37822 -SK_IOC IoC,    /* IO context */
37823 +SK_AC  *pAC,   /* Adapter Context */
37824 +SK_IOC IoC,    /* I/O Context */
37825  int            Port)   /* Port Index (MAC_1 + n) */
37826  {
37827         SK_U32  DWord;
37828 -
37829 +
37830         /* WA code for COMA mode */
37831         if (pAC->GIni.GIYukonLite &&
37832                 pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3) {
37833 -
37834 +
37835                 SK_IN32(IoC, B2_GP_IO, &DWord);
37836
37837                 DWord |= (GP_DIR_9 | GP_IO_9);
37838 @@ -1076,10 +1115,10 @@
37839         }
37840
37841         /* set GPHY Control reset */
37842 -       SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), GPC_RST_SET);
37843 +       SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_SET);
37844
37845         /* set GMAC Control reset */
37846 -       SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_RST_SET);
37847 +       SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_SET);
37848
37849  }      /* SkGmHardRst */
37850
37851 @@ -1094,24 +1133,24 @@
37852   *     nothing
37853   */
37854  static void SkGmClearRst(
37855 -SK_AC  *pAC,   /* adapter context */
37856 -SK_IOC IoC,    /* IO context */
37857 +SK_AC  *pAC,   /* Adapter Context */
37858 +SK_IOC IoC,    /* I/O Context */
37859  int            Port)   /* Port Index (MAC_1 + n) */
37860  {
37861         SK_U32  DWord;
37862 -
37863 -#ifdef XXX
37864 -               /* clear GMAC Control reset */
37865 -               SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_RST_CLR);
37866 +#ifdef SK_DIAG
37867 +       SK_U16  PhyId0;
37868 +       SK_U16  PhyId1;
37869 +#endif /* SK_DIAG */
37870
37871 -               /* set GMAC Control reset */
37872 -               SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_RST_SET);
37873 -#endif /* XXX */
37874 +#if defined(SK_DIAG) || defined(DEBUG)
37875 +       SK_U16  Word;
37876 +#endif /* SK_DIAG || DEBUG */
37877
37878         /* WA code for COMA mode */
37879         if (pAC->GIni.GIYukonLite &&
37880                 pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3) {
37881 -
37882 +
37883                 SK_IN32(IoC, B2_GP_IO, &DWord);
37884
37885                 DWord |= GP_DIR_9;              /* set to output */
37886 @@ -1121,30 +1160,87 @@
37887                 SK_OUT32(IoC, B2_GP_IO, DWord);
37888         }
37889
37890 -       /* set HWCFG_MODE */
37891 -       DWord = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
37892 -               GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE |
37893 -               (pAC->GIni.GICopperType ? GPC_HWCFG_GMII_COP :
37894 -               GPC_HWCFG_GMII_FIB);
37895 +#ifdef VCPU
37896 +       /* set MAC Reset before PHY reset is set */
37897 +       SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_SET);
37898 +#endif /* VCPU */
37899
37900 -       /* set GPHY Control reset */
37901 -       SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), DWord | GPC_RST_SET);
37902 +       if (CHIP_ID_YUKON_2(pAC)) {
37903 +               /* set GPHY Control reset */
37904 +               SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_SET);
37905
37906 -       /* release GPHY Control reset */
37907 -       SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), DWord | GPC_RST_CLR);
37908 +               /* release GPHY Control reset */
37909 +               SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_CLR);
37910 +
37911 +#ifdef DEBUG
37912 +               /* additional check for PEX */
37913 +               SK_IN16(IoC, GPHY_CTRL, &Word);
37914 +
37915 +               if (pAC->GIni.GIPciBus == SK_PEX_BUS && Word != GPC_RST_CLR) {
37916 +
37917 +                       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
37918 +                               ("Error on PEX-bus after GPHY reset\n"));
37919 +               }
37920 +#endif /* DEBUG */
37921 +       }
37922 +       else {
37923 +               /* set HWCFG_MODE */
37924 +               DWord = GPC_INT_POL | GPC_DIS_FC | GPC_DIS_SLEEP |
37925 +                       GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE |
37926 +                       (pAC->GIni.GICopperType ? GPC_HWCFG_GMII_COP :
37927 +                       GPC_HWCFG_GMII_FIB);
37928 +
37929 +               /* set GPHY Control reset */
37930 +               SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), DWord | GPC_RST_SET);
37931 +
37932 +               /* release GPHY Control reset */
37933 +               SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), DWord | GPC_RST_CLR);
37934 +       }
37935
37936  #ifdef VCPU
37937 +       /* wait for internal initialization of GPHY */
37938 +       VCPUprintf(0, "Waiting until PHY %d is ready to initialize\n", Port);
37939 +       VCpuWait(10000);
37940 +
37941 +       /* release GMAC reset */
37942 +       SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_CLR);
37943 +
37944 +       /* wait for stable GMAC clock */
37945         VCpuWait(9000);
37946  #endif /* VCPU */
37947
37948         /* clear GMAC Control reset */
37949 -       SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
37950 +       SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_CLR);
37951 +
37952 +#ifdef SK_DIAG
37953 +       if (HW_FEATURE(pAC, HWF_WA_DEV_472) && Port == MAC_2) {
37954 +
37955 +               /* clear GMAC 1 Control reset */
37956 +               SK_OUT8(IoC, MR_ADDR(MAC_1, GMAC_CTRL), (SK_U8)GMC_RST_CLR);
37957 +
37958 +               do {
37959 +                       /* set GMAC 2 Control reset */
37960 +                       SK_OUT8(IoC, MR_ADDR(MAC_2, GMAC_CTRL), (SK_U8)GMC_RST_SET);
37961 +
37962 +                       /* clear GMAC 2 Control reset */
37963 +                       SK_OUT8(IoC, MR_ADDR(MAC_2, GMAC_CTRL), (SK_U8)GMC_RST_CLR);
37964 +
37965 +                       SkGmPhyRead(pAC, IoC, MAC_2, PHY_MARV_ID0, &PhyId0);
37966 +
37967 +                       SkGmPhyRead(pAC, IoC, MAC_2, PHY_MARV_ID1, &PhyId1);
37968 +
37969 +                       SkGmPhyRead(pAC, IoC, MAC_2, PHY_MARV_INT_MASK, &Word);
37970 +
37971 +               } while (Word != 0 || PhyId0 != PHY_MARV_ID0_VAL ||
37972 +                                PhyId1 != PHY_MARV_ID1_Y2);
37973 +       }
37974 +#endif /* SK_DIAG */
37975
37976  #ifdef VCPU
37977         VCpuWait(2000);
37978 -
37979 +
37980         SK_IN32(IoC, MR_ADDR(Port, GPHY_CTRL), &DWord);
37981 -
37982 +
37983         SK_IN32(IoC, B0_ISRC, &DWord);
37984  #endif /* VCPU */
37985
37986 @@ -1162,37 +1258,33 @@
37987   *     nothing
37988   */
37989  void SkMacSoftRst(
37990 -SK_AC  *pAC,   /* adapter context */
37991 -SK_IOC IoC,    /* IO context */
37992 +SK_AC  *pAC,   /* Adapter Context */
37993 +SK_IOC IoC,    /* I/O Context */
37994  int            Port)   /* Port Index (MAC_1 + n) */
37995  {
37996 -       SK_GEPORT       *pPrt;
37997 -
37998 -       pPrt = &pAC->GIni.GP[Port];
37999 -
38000         /* disable receiver and transmitter */
38001         SkMacRxTxDisable(pAC, IoC, Port);
38002
38003  #ifdef GENESIS
38004         if (pAC->GIni.GIGenesis) {
38005 -
38006 +
38007                 SkXmSoftRst(pAC, IoC, Port);
38008         }
38009  #endif /* GENESIS */
38010 -
38011 +
38012  #ifdef YUKON
38013         if (pAC->GIni.GIYukon) {
38014 -
38015 +
38016                 SkGmSoftRst(pAC, IoC, Port);
38017         }
38018  #endif /* YUKON */
38019
38020         /* flush the MAC's Rx and Tx FIFOs */
38021         SkMacFlushTxFifo(pAC, IoC, Port);
38022 -
38023 +
38024         SkMacFlushRxFifo(pAC, IoC, Port);
38025
38026 -       pPrt->PState = SK_PRT_STOP;
38027 +       pAC->GIni.GP[Port].PState = SK_PRT_STOP;
38028
38029  }      /* SkMacSoftRst */
38030
38031 @@ -1207,29 +1299,63 @@
38032   *     nothing
38033   */
38034  void SkMacHardRst(
38035 -SK_AC  *pAC,   /* adapter context */
38036 -SK_IOC IoC,    /* IO context */
38037 +SK_AC  *pAC,   /* Adapter Context */
38038 +SK_IOC IoC,    /* I/O Context */
38039  int            Port)   /* Port Index (MAC_1 + n) */
38040  {
38041 -
38042 +
38043  #ifdef GENESIS
38044         if (pAC->GIni.GIGenesis) {
38045 -
38046 +
38047                 SkXmHardRst(pAC, IoC, Port);
38048         }
38049  #endif /* GENESIS */
38050 -
38051 +
38052  #ifdef YUKON
38053         if (pAC->GIni.GIYukon) {
38054 -
38055 +
38056                 SkGmHardRst(pAC, IoC, Port);
38057         }
38058  #endif /* YUKON */
38059
38060 +       pAC->GIni.GP[Port].PHWLinkUp = SK_FALSE;
38061 +
38062         pAC->GIni.GP[Port].PState = SK_PRT_RESET;
38063
38064  }      /* SkMacHardRst */
38065
38066 +#ifndef SK_SLIM
38067 +/******************************************************************************
38068 + *
38069 + *     SkMacClearRst() - Clear the MAC reset
38070 + *
38071 + * Description:        calls a clear MAC reset routine dep. on board type
38072 + *
38073 + * Returns:
38074 + *     nothing
38075 + */
38076 +void SkMacClearRst(
38077 +SK_AC  *pAC,   /* Adapter Context */
38078 +SK_IOC IoC,    /* I/O Context */
38079 +int            Port)   /* Port Index (MAC_1 + n) */
38080 +{
38081 +
38082 +#ifdef GENESIS
38083 +       if (pAC->GIni.GIGenesis) {
38084 +
38085 +               SkXmClearRst(pAC, IoC, Port);
38086 +       }
38087 +#endif /* GENESIS */
38088 +
38089 +#ifdef YUKON
38090 +       if (pAC->GIni.GIYukon) {
38091 +
38092 +               SkGmClearRst(pAC, IoC, Port);
38093 +       }
38094 +#endif /* YUKON */
38095 +
38096 +}      /* SkMacClearRst */
38097 +#endif /* !SK_SLIM */
38098
38099  #ifdef GENESIS
38100  /******************************************************************************
38101 @@ -1247,8 +1373,8 @@
38102   *     nothing
38103   */
38104  void SkXmInitMac(
38105 -SK_AC  *pAC,           /* adapter context */
38106 -SK_IOC IoC,            /* IO context */
38107 +SK_AC  *pAC,           /* Adapter Context */
38108 +SK_IOC IoC,            /* I/O Context */
38109  int            Port)           /* Port Index (MAC_1 + n) */
38110  {
38111         SK_GEPORT       *pPrt;
38112 @@ -1258,13 +1384,13 @@
38113         pPrt = &pAC->GIni.GP[Port];
38114
38115         if (pPrt->PState == SK_PRT_STOP) {
38116 -               /* Port State: SK_PRT_STOP */
38117                 /* Verify that the reset bit is cleared */
38118                 SK_IN16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), &SWord);
38119
38120                 if ((SWord & MFF_SET_MAC_RST) != 0) {
38121                         /* PState does not match HW state */
38122 -                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E006, SKERR_HWI_E006MSG);
38123 +                       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
38124 +                               ("SkXmInitMac: PState does not match HW state"));
38125                         /* Correct it */
38126                         pPrt->PState = SK_PRT_RESET;
38127                 }
38128 @@ -1283,7 +1409,7 @@
38129                          * Must be done AFTER first access to BCOM chip.
38130                          */
38131                         XM_IN16(IoC, Port, XM_MMU_CMD, &SWord);
38132 -
38133 +
38134                         XM_OUT16(IoC, Port, XM_MMU_CMD, SWord | XM_MMU_NO_PRE);
38135
38136                         if (pPrt->PhyId1 == PHY_BCOM_ID1_C0) {
38137 @@ -1316,7 +1442,7 @@
38138                          * Disable Power Management after reset.
38139                          */
38140                         SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &SWord);
38141 -
38142 +
38143                         SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUX_CTRL,
38144                                 (SK_U16)(SWord | PHY_B_AC_DIS_PM));
38145
38146 @@ -1325,19 +1451,13 @@
38147
38148                 /* Dummy read the Interrupt source register */
38149                 XM_IN16(IoC, Port, XM_ISRC, &SWord);
38150 -
38151 +
38152                 /*
38153                  * The auto-negotiation process starts immediately after
38154                  * clearing the reset. The auto-negotiation process should be
38155                  * started by the SIRQ, therefore stop it here immediately.
38156                  */
38157                 SkMacInitPhy(pAC, IoC, Port, SK_FALSE);
38158 -
38159 -#ifdef TEST_ONLY
38160 -               /* temp. code: enable signal detect */
38161 -               /* WARNING: do not override GMII setting above */
38162 -               XM_OUT16(IoC, Port, XM_HW_CFG, XM_HW_COM4SIG);
38163 -#endif
38164         }
38165
38166         /*
38167 @@ -1351,7 +1471,7 @@
38168                  * independent. Remember this when changing.
38169                  */
38170                 SK_IN16(IoC, (B2_MAC_2 + Port * 8 + i * 2), &SWord);
38171 -
38172 +
38173                 XM_OUT16(IoC, Port, (XM_SA + i * 2), SWord);
38174         }
38175
38176 @@ -1369,7 +1489,7 @@
38177         SWord = SK_XM_THR_SL;                           /* for single port */
38178
38179         if (pAC->GIni.GIMacsFound > 1) {
38180 -               switch (pAC->GIni.GIPortUsage) {
38181 +               switch (pPrt->PPortUsage) {
38182                 case SK_RED_LINK:
38183                         SWord = SK_XM_THR_REDL;         /* redundant link */
38184                         break;
38185 @@ -1392,7 +1512,7 @@
38186         /* setup register defaults for the Rx Command Register */
38187         SWord = XM_RX_STRIP_FCS | XM_RX_LENERR_OK;
38188
38189 -       if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
38190 +       if (pPrt->PPortUsage == SK_JUMBO_LINK) {
38191                 SWord |= XM_RX_BIG_PK_OK;
38192         }
38193
38194 @@ -1404,7 +1524,7 @@
38195                  */
38196                 SWord |= XM_RX_DIS_CEXT;
38197         }
38198 -
38199 +
38200         XM_OUT16(IoC, Port, XM_RX_CMD, SWord);
38201
38202         /*
38203 @@ -1461,8 +1581,8 @@
38204   *     nothing
38205   */
38206  void SkGmInitMac(
38207 -SK_AC  *pAC,           /* adapter context */
38208 -SK_IOC IoC,            /* IO context */
38209 +SK_AC  *pAC,           /* Adapter Context */
38210 +SK_IOC IoC,            /* I/O Context */
38211  int            Port)           /* Port Index (MAC_1 + n) */
38212  {
38213         SK_GEPORT       *pPrt;
38214 @@ -1473,26 +1593,41 @@
38215         pPrt = &pAC->GIni.GP[Port];
38216
38217         if (pPrt->PState == SK_PRT_STOP) {
38218 -               /* Port State: SK_PRT_STOP */
38219                 /* Verify that the reset bit is cleared */
38220                 SK_IN32(IoC, MR_ADDR(Port, GMAC_CTRL), &DWord);
38221 -
38222 +
38223                 if ((DWord & GMC_RST_SET) != 0) {
38224                         /* PState does not match HW state */
38225 -                       SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E006, SKERR_HWI_E006MSG);
38226 +                       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38227 +                               ("SkGmInitMac: PState does not match HW state"));
38228                         /* Correct it */
38229                         pPrt->PState = SK_PRT_RESET;
38230                 }
38231 +               else {
38232 +                       /* enable PHY interrupts */
38233 +                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK,
38234 +                               (SK_U16)PHY_M_DEF_MSK);
38235 +               }
38236         }
38237
38238         if (pPrt->PState == SK_PRT_RESET) {
38239 -
38240 +
38241                 SkGmHardRst(pAC, IoC, Port);
38242
38243                 SkGmClearRst(pAC, IoC, Port);
38244 -
38245 +
38246 +#ifndef SK_SLIM
38247 +               if (HW_FEATURE(pAC, HWF_FORCE_AUTO_NEG) &&
38248 +                       pPrt->PLinkModeConf < SK_LMODE_AUTOHALF) {
38249 +                       /* Force Auto-Negotiation */
38250 +                       pPrt->PLinkMode = (pPrt->PLinkModeConf == SK_LMODE_FULL) ?
38251 +                               SK_LMODE_AUTOBOTH : SK_LMODE_AUTOHALF;
38252 +               }
38253 +#endif /* !SK_SLIM */
38254 +
38255                 /* Auto-negotiation ? */
38256 -               if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
38257 +               if (pPrt->PLinkMode == SK_LMODE_HALF ||
38258 +                        pPrt->PLinkMode == SK_LMODE_FULL) {
38259                         /* Auto-negotiation disabled */
38260
38261                         /* get General Purpose Control */
38262 @@ -1500,10 +1635,10 @@
38263
38264                         /* disable auto-update for speed, duplex and flow-control */
38265                         SWord |= GM_GPCR_AU_ALL_DIS;
38266 -
38267 +
38268                         /* setup General Purpose Control Register */
38269                         GM_OUT16(IoC, Port, GM_GP_CTRL, SWord);
38270 -
38271 +
38272                         SWord = GM_GPCR_AU_ALL_DIS;
38273                 }
38274                 else {
38275 @@ -1514,7 +1649,10 @@
38276                 switch (pPrt->PLinkSpeed) {
38277                 case SK_LSPEED_AUTO:
38278                 case SK_LSPEED_1000MBPS:
38279 -                       SWord |= GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100;
38280 +                       if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
38281 +
38282 +                               SWord |= GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100;
38283 +                       }
38284                         break;
38285                 case SK_LSPEED_100MBPS:
38286                         SWord |= GM_GPCR_SPEED_100;
38287 @@ -1532,8 +1670,6 @@
38288                 /* flow-control settings */
38289                 switch (pPrt->PFlowCtrlMode) {
38290                 case SK_FLOW_MODE_NONE:
38291 -                       /* set Pause Off */
38292 -                       SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_PAUSE_OFF);
38293                         /* disable Tx & Rx flow-control */
38294                         SWord |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
38295                         break;
38296 @@ -1551,24 +1687,22 @@
38297                 GM_OUT16(IoC, Port, GM_GP_CTRL, SWord);
38298
38299                 /* dummy read the Interrupt Source Register */
38300 -               SK_IN16(IoC, GMAC_IRQ_SRC, &SWord);
38301 -
38302 +               SK_IN16(IoC, MR_ADDR(Port, GMAC_IRQ_SRC), &SWord);
38303 +
38304  #ifndef VCPU
38305 -               /* read Id from PHY */
38306 -               SkGmPhyRead(pAC, IoC, Port, PHY_MARV_ID1, &pPrt->PhyId1);
38307 -
38308                 SkGmInitPhyMarv(pAC, IoC, Port, SK_FALSE);
38309 -#endif /* VCPU */
38310 +#endif /* !VCPU */
38311         }
38312
38313         (void)SkGmResetCounter(pAC, IoC, Port);
38314
38315         /* setup Transmit Control Register */
38316 -       GM_OUT16(IoC, Port, GM_TX_CTRL, TX_COL_THR(pPrt->PMacColThres));
38317 +       GM_OUT16(IoC, Port, GM_TX_CTRL, (SK_U16)TX_COL_THR(pPrt->PMacColThres));
38318
38319         /* setup Receive Control Register */
38320 -       GM_OUT16(IoC, Port, GM_RX_CTRL, GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA |
38321 -               GM_RXCR_CRC_DIS);
38322 +       SWord = GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA | GM_RXCR_CRC_DIS;
38323 +
38324 +       GM_OUT16(IoC, Port, GM_RX_CTRL, SWord);
38325
38326         /* setup Transmit Flow Control Register */
38327         GM_OUT16(IoC, Port, GM_TX_FLOW_CTRL, 0xffff);
38328 @@ -1578,31 +1712,29 @@
38329         GM_IN16(IoC, Port, GM_TX_PARAM, &SWord);
38330  #endif /* VCPU */
38331
38332 -    SWord = TX_JAM_LEN_VAL(pPrt->PMacJamLen) |
38333 -                       TX_JAM_IPG_VAL(pPrt->PMacJamIpgVal) |
38334 -                       TX_IPG_JAM_DATA(pPrt->PMacJamIpgData);
38335 -
38336 +       SWord = (SK_U16)(TX_JAM_LEN_VAL(pPrt->PMacJamLen) |
38337 +               TX_JAM_IPG_VAL(pPrt->PMacJamIpgVal) |
38338 +               TX_IPG_JAM_DATA(pPrt->PMacJamIpgData) |
38339 +               TX_BACK_OFF_LIM(pPrt->PMacBackOffLim));
38340 +
38341         GM_OUT16(IoC, Port, GM_TX_PARAM, SWord);
38342
38343         /* configure the Serial Mode Register */
38344 -#ifdef VCPU
38345 -       GM_IN16(IoC, Port, GM_SERIAL_MODE, &SWord);
38346 -#endif /* VCPU */
38347 -
38348 -       SWord = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(pPrt->PMacIpgData);
38349 +       SWord = (SK_U16)(DATA_BLIND_VAL(pPrt->PMacDataBlind) |
38350 +               GM_SMOD_VLAN_ENA | IPG_DATA_VAL(pPrt->PMacIpgData));
38351
38352         if (pPrt->PMacLimit4) {
38353                 /* reset of collision counter after 4 consecutive collisions */
38354                 SWord |= GM_SMOD_LIMIT_4;
38355         }
38356
38357 -       if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
38358 +       if (pPrt->PPortUsage == SK_JUMBO_LINK) {
38359                 /* enable jumbo mode (Max. Frame Length = 9018) */
38360                 SWord |= GM_SMOD_JUMBO_ENA;
38361         }
38362 -
38363 +
38364         GM_OUT16(IoC, Port, GM_SERIAL_MODE, SWord);
38365 -
38366 +
38367         /*
38368          * configure the GMACs Station Addresses
38369          * in PROM you can find our addresses at:
38370 @@ -1631,17 +1763,17 @@
38371                 else {
38372                         GM_OUT16(IoC, Port, (GM_SRC_ADDR_1L + i * 4), SWord);
38373                 }
38374 -#else
38375 +#else
38376                 GM_OUT16(IoC, Port, (GM_SRC_ADDR_1L + i * 4), SWord);
38377  #endif /* WA_DEV_16 */
38378 -
38379 +
38380                 /* virtual address: will be used for data */
38381                 SK_IN16(IoC, (B2_MAC_1 + Port * 8 + i * 2), &SWord);
38382
38383                 GM_OUT16(IoC, Port, (GM_SRC_ADDR_2L + i * 4), SWord);
38384 -
38385 +
38386                 /* reset Multicast filtering Hash registers 1-3 */
38387 -               GM_OUT16(IoC, Port, GM_MC_ADDR_H1 + 4*i, 0);
38388 +               GM_OUT16(IoC, Port, GM_MC_ADDR_H1 + i * 4, 0);
38389         }
38390
38391         /* reset Multicast filtering Hash register 4 */
38392 @@ -1652,18 +1784,6 @@
38393         GM_OUT16(IoC, Port, GM_RX_IRQ_MSK, 0);
38394         GM_OUT16(IoC, Port, GM_TR_IRQ_MSK, 0);
38395
38396 -#if defined(SK_DIAG) || defined(DEBUG)
38397 -       /* read General Purpose Status */
38398 -       GM_IN16(IoC, Port, GM_GP_STAT, &SWord);
38399 -
38400 -       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38401 -               ("MAC Stat Reg.=0x%04X\n", SWord));
38402 -#endif /* SK_DIAG || DEBUG */
38403 -
38404 -#ifdef SK_DIAG
38405 -       c_print("MAC Stat Reg=0x%04X\n", SWord);
38406 -#endif /* SK_DIAG */
38407 -
38408  }      /* SkGmInitMac */
38409  #endif /* YUKON */
38410
38411 @@ -1681,9 +1801,9 @@
38412   * Returns:
38413   *     nothing
38414   */
38415 -static void SkXmInitDupMd(
38416 -SK_AC  *pAC,           /* adapter context */
38417 -SK_IOC IoC,            /* IO context */
38418 +void SkXmInitDupMd(
38419 +SK_AC  *pAC,           /* Adapter Context */
38420 +SK_IOC IoC,            /* I/O Context */
38421  int            Port)           /* Port Index (MAC_1 + n) */
38422  {
38423         switch (pAC->GIni.GP[Port].PLinkModeStatus) {
38424 @@ -1729,9 +1849,9 @@
38425   * Returns:
38426   *     nothing
38427   */
38428 -static void SkXmInitPauseMd(
38429 -SK_AC  *pAC,           /* adapter context */
38430 -SK_IOC IoC,            /* IO context */
38431 +void SkXmInitPauseMd(
38432 +SK_AC  *pAC,           /* Adapter Context */
38433 +SK_IOC IoC,            /* I/O Context */
38434  int            Port)           /* Port Index (MAC_1 + n) */
38435  {
38436         SK_GEPORT       *pPrt;
38437 @@ -1741,11 +1861,11 @@
38438         pPrt = &pAC->GIni.GP[Port];
38439
38440         XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
38441 -
38442 +
38443         if (pPrt->PFlowCtrlStatus == SK_FLOW_STAT_NONE ||
38444                 pPrt->PFlowCtrlStatus == SK_FLOW_STAT_LOC_SEND) {
38445
38446 -               /* Disable Pause Frame Reception */
38447 +               /* disable Pause Frame Reception */
38448                 Word |= XM_MMU_IGN_PF;
38449         }
38450         else {
38451 @@ -1753,10 +1873,10 @@
38452                  * enabling pause frame reception is required for 1000BT
38453                  * because the XMAC is not reset if the link is going down
38454                  */
38455 -               /* Enable Pause Frame Reception */
38456 +               /* enable Pause Frame Reception */
38457                 Word &= ~XM_MMU_IGN_PF;
38458 -       }
38459 -
38460 +       }
38461 +
38462         XM_OUT16(IoC, Port, XM_MMU_CMD, Word);
38463
38464         XM_IN32(IoC, Port, XM_MODE, &DWord);
38465 @@ -1779,10 +1899,10 @@
38466                 /* remember this value is defined in big endian (!) */
38467                 XM_OUT16(IoC, Port, XM_MAC_PTIME, 0xffff);
38468
38469 -               /* Set Pause Mode in Mode Register */
38470 +               /* set Pause Mode in Mode Register */
38471                 DWord |= XM_PAUSE_MODE;
38472
38473 -               /* Set Pause Mode in MAC Rx FIFO */
38474 +               /* set Pause Mode in MAC Rx FIFO */
38475                 SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
38476         }
38477         else {
38478 @@ -1790,22 +1910,22 @@
38479                  * disable pause frame generation is required for 1000BT
38480                  * because the XMAC is not reset if the link is going down
38481                  */
38482 -               /* Disable Pause Mode in Mode Register */
38483 +               /* disable Pause Mode in Mode Register */
38484                 DWord &= ~XM_PAUSE_MODE;
38485
38486 -               /* Disable Pause Mode in MAC Rx FIFO */
38487 +               /* disable Pause Mode in MAC Rx FIFO */
38488                 SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
38489         }
38490 -
38491 +
38492         XM_OUT32(IoC, Port, XM_MODE, DWord);
38493  }      /* SkXmInitPauseMd*/
38494
38495
38496  /******************************************************************************
38497   *
38498 - *     SkXmInitPhyXmac() - Initialize the XMAC Phy registers
38499 + *     SkXmInitPhyXmac() - Initialize the XMAC PHY registers
38500   *
38501 - * Description:        initializes all the XMACs Phy registers
38502 + * Description:        initializes all the XMACs PHY registers
38503   *
38504   * Note:
38505   *
38506 @@ -1813,22 +1933,22 @@
38507   *     nothing
38508   */
38509  static void SkXmInitPhyXmac(
38510 -SK_AC  *pAC,           /* adapter context */
38511 -SK_IOC IoC,            /* IO context */
38512 +SK_AC  *pAC,           /* Adapter Context */
38513 +SK_IOC IoC,            /* I/O Context */
38514  int            Port,           /* Port Index (MAC_1 + n) */
38515 -SK_BOOL        DoLoop)         /* Should a Phy LoopBack be set-up? */
38516 +SK_BOOL        DoLoop)         /* Should a PHY LoopBack be set-up? */
38517  {
38518         SK_GEPORT       *pPrt;
38519         SK_U16          Ctrl;
38520
38521         pPrt = &pAC->GIni.GP[Port];
38522         Ctrl = 0;
38523 -
38524 +
38525         /* Auto-negotiation ? */
38526         if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
38527                 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38528                         ("InitPhyXmac: no auto-negotiation Port %d\n", Port));
38529 -               /* Set DuplexMode in Config register */
38530 +               /* set DuplexMode in Config register */
38531                 if (pPrt->PLinkMode == SK_LMODE_FULL) {
38532                         Ctrl |= PHY_CT_DUP_MD;
38533                 }
38534 @@ -1841,9 +1961,9 @@
38535         else {
38536                 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38537                         ("InitPhyXmac: with auto-negotiation Port %d\n", Port));
38538 -               /* Set Auto-negotiation advertisement */
38539 +               /* set Auto-negotiation advertisement */
38540
38541 -               /* Set Full/half duplex capabilities */
38542 +               /* set Full/half duplex capabilities */
38543                 switch (pPrt->PLinkMode) {
38544                 case SK_LMODE_AUTOHALF:
38545                         Ctrl |= PHY_X_AN_HD;
38546 @@ -1859,7 +1979,7 @@
38547                                 SKERR_HWI_E015MSG);
38548                 }
38549
38550 -               /* Set Flow-control capabilities */
38551 +               /* set Flow-control capabilities */
38552                 switch (pPrt->PFlowCtrlMode) {
38553                 case SK_FLOW_MODE_NONE:
38554                         Ctrl |= PHY_X_P_NO_PAUSE;
38555 @@ -1886,20 +2006,20 @@
38556         }
38557
38558         if (DoLoop) {
38559 -               /* Set the Phy Loopback bit, too */
38560 +               /* set the PHY Loopback bit, too */
38561                 Ctrl |= PHY_CT_LOOP;
38562         }
38563
38564 -       /* Write to the Phy control register */
38565 +       /* Write to the PHY control register */
38566         SkXmPhyWrite(pAC, IoC, Port, PHY_XMAC_CTRL, Ctrl);
38567  }      /* SkXmInitPhyXmac */
38568
38569
38570  /******************************************************************************
38571   *
38572 - *     SkXmInitPhyBcom() - Initialize the Broadcom Phy registers
38573 + *     SkXmInitPhyBcom() - Initialize the Broadcom PHY registers
38574   *
38575 - * Description:        initializes all the Broadcom Phy registers
38576 + * Description:        initializes all the Broadcom PHY registers
38577   *
38578   * Note:
38579   *
38580 @@ -1907,10 +2027,10 @@
38581   *     nothing
38582   */
38583  static void SkXmInitPhyBcom(
38584 -SK_AC  *pAC,           /* adapter context */
38585 -SK_IOC IoC,            /* IO context */
38586 +SK_AC  *pAC,           /* Adapter Context */
38587 +SK_IOC IoC,            /* I/O Context */
38588  int            Port,           /* Port Index (MAC_1 + n) */
38589 -SK_BOOL        DoLoop)         /* Should a Phy LoopBack be set-up? */
38590 +SK_BOOL        DoLoop)         /* Should a PHY LoopBack be set-up? */
38591  {
38592         SK_GEPORT       *pPrt;
38593         SK_U16          Ctrl1;
38594 @@ -1930,16 +2050,17 @@
38595         /* manually Master/Slave ? */
38596         if (pPrt->PMSMode != SK_MS_MODE_AUTO) {
38597                 Ctrl2 |= PHY_B_1000C_MSE;
38598 -
38599 +
38600                 if (pPrt->PMSMode == SK_MS_MODE_MASTER) {
38601                         Ctrl2 |= PHY_B_1000C_MSC;
38602                 }
38603         }
38604 +
38605         /* Auto-negotiation ? */
38606         if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
38607                 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38608                         ("InitPhyBcom: no auto-negotiation Port %d\n", Port));
38609 -               /* Set DuplexMode in Config register */
38610 +               /* set DuplexMode in Config register */
38611                 if (pPrt->PLinkMode == SK_LMODE_FULL) {
38612                         Ctrl1 |= PHY_CT_DUP_MD;
38613                 }
38614 @@ -1957,7 +2078,7 @@
38615         else {
38616                 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38617                         ("InitPhyBcom: with auto-negotiation Port %d\n", Port));
38618 -               /* Set Auto-negotiation advertisement */
38619 +               /* set Auto-negotiation advertisement */
38620
38621                 /*
38622                  * Workaround BCOM Errata #1 for the C5 type.
38623 @@ -1965,8 +2086,8 @@
38624                  * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
38625                  */
38626                 Ctrl2 |= PHY_B_1000C_RD;
38627 -
38628 -                /* Set Full/half duplex capabilities */
38629 +
38630 +                /* set Full/half duplex capabilities */
38631                 switch (pPrt->PLinkMode) {
38632                 case SK_LMODE_AUTOHALF:
38633                         Ctrl2 |= PHY_B_1000C_AHD;
38634 @@ -1982,7 +2103,7 @@
38635                                 SKERR_HWI_E015MSG);
38636                 }
38637
38638 -               /* Set Flow-control capabilities */
38639 +               /* set Flow-control capabilities */
38640                 switch (pPrt->PFlowCtrlMode) {
38641                 case SK_FLOW_MODE_NONE:
38642                         Ctrl3 |= PHY_B_P_NO_PAUSE;
38643 @@ -2004,27 +2125,27 @@
38644                 /* Restart Auto-negotiation */
38645                 Ctrl1 |= PHY_CT_ANE | PHY_CT_RE_CFG;
38646         }
38647 -
38648 +
38649         /* Initialize LED register here? */
38650         /* No. Please do it in SkDgXmitLed() (if required) and swap
38651 -          init order of LEDs and XMAC. (MAl) */
38652 -
38653 +               init order of LEDs and XMAC. (MAl) */
38654 +
38655         /* Write 1000Base-T Control Register */
38656         SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_1000T_CTRL, Ctrl2);
38657         SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38658 -               ("Set 1000B-T Ctrl Reg=0x%04X\n", Ctrl2));
38659 -
38660 +               ("Set 1000B-T Ctrl Reg = 0x%04X\n", Ctrl2));
38661 +
38662         /* Write AutoNeg Advertisement Register */
38663         SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUNE_ADV, Ctrl3);
38664         SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38665 -               ("Set Auto-Neg.Adv.Reg=0x%04X\n", Ctrl3));
38666 -
38667 +               ("Set Auto-Neg.Adv.Reg = 0x%04X\n", Ctrl3));
38668 +
38669         if (DoLoop) {
38670 -               /* Set the Phy Loopback bit, too */
38671 +               /* set the PHY Loopback bit, too */
38672                 Ctrl1 |= PHY_CT_LOOP;
38673         }
38674
38675 -       if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
38676 +       if (pPrt->PPortUsage == SK_JUMBO_LINK) {
38677                 /* configure FIFO to high latency for transmission of ext. packets */
38678                 Ctrl4 |= PHY_B_PEC_HIGH_LA;
38679
38680 @@ -2036,20 +2157,553 @@
38681
38682         /* Configure LED Traffic Mode and Jumbo Frame usage if specified */
38683         SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_P_EXT_CTRL, Ctrl4);
38684 -
38685 -       /* Write to the Phy control register */
38686 +
38687 +       /* Write to the PHY control register */
38688         SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_CTRL, Ctrl1);
38689         SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38690 -               ("PHY Control Reg=0x%04X\n", Ctrl1));
38691 +               ("PHY Control Reg = 0x%04X\n", Ctrl1));
38692  }      /* SkXmInitPhyBcom */
38693  #endif /* GENESIS */
38694
38695 +
38696  #ifdef YUKON
38697 +#ifdef SK_PHY_LP_MODE
38698 +/******************************************************************************
38699 + *
38700 + *     SkGmEnterLowPowerMode()
38701 + *
38702 + * Description:
38703 + *     This function sets the Marvell Alaska PHY to the low power mode
38704 + *     given by parameter mode.
38705 + *     The following low power modes are available:
38706 + *
38707 + *             - COMA Mode (Deep Sleep):
38708 + *                     The PHY cannot wake up on its own.
38709 + *
38710 + *             - IEEE 22.2.4.1.5 compatible power down mode
38711 + *                     The PHY cannot wake up on its own.
38712 + *
38713 + *             - energy detect mode
38714 + *                     The PHY can wake up on its own by detecting activity
38715 + *                     on the CAT 5 cable.
38716 + *
38717 + *             - energy detect plus mode
38718 + *                     The PHY can wake up on its own by detecting activity
38719 + *                     on the CAT 5 cable.
38720 + *                     Connected devices can be woken up by sending normal link
38721 + *                     pulses every second.
38722 + *
38723 + * Note:
38724 + *
38725 + * Returns:
38726 + *             0: ok
38727 + *             1: error
38728 + */
38729 +int SkGmEnterLowPowerMode(
38730 +SK_AC  *pAC,           /* Adapter Context */
38731 +SK_IOC IoC,            /* I/O Context */
38732 +int            Port,           /* Port Index (e.g. MAC_1) */
38733 +SK_U8  Mode)           /* low power mode */
38734 +{
38735 +       SK_U8   LastMode;
38736 +       SK_U8   Byte;
38737 +       SK_U16  Word;
38738 +       SK_U16  ClkDiv;
38739 +       SK_U32  DWord;
38740 +       SK_U32  PowerDownBit;
38741 +       int             ChipId;
38742 +       int             Ret = 0;
38743 +
38744 +       if (!(CHIP_ID_YUKON_2(pAC) || (pAC->GIni.GIYukonLite &&
38745 +               pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3))) {
38746 +
38747 +               return(1);
38748 +       }
38749 +
38750 +       /* save current power mode */
38751 +       LastMode = pAC->GIni.GP[Port].PPhyPowerState;
38752 +       pAC->GIni.GP[Port].PPhyPowerState = Mode;
38753 +
38754 +       ChipId = pAC->GIni.GIChipId;
38755 +
38756 +       SK_DBG_MSG(pAC, SK_DBGMOD_POWM, SK_DBGCAT_CTRL,
38757 +               ("SkGmEnterLowPowerMode: %u\n", Mode));
38758 +
38759 +       /* release GPHY Control reset */
38760 +       SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_CLR);
38761 +
38762 +       /* release GMAC reset */
38763 +       SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_CLR);
38764 +
38765 +       if (ChipId == CHIP_ID_YUKON_EC_U) {
38766 +               /* select page 2 to access MAC control register */
38767 +               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 2);
38768 +
38769 +               SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
38770 +               /* allow GMII Power Down */
38771 +               Word &= ~PHY_M_MAC_GMIF_PUP;
38772 +               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
38773 +
38774 +               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0);
38775 +       }
38776 +
38777 +       switch (Mode) {
38778 +       /* COMA mode (deep sleep) */
38779 +       case PHY_PM_DEEP_SLEEP:
38780 +               /* setup General Purpose Control Register */
38781 +               GM_OUT16(IoC, Port, GM_GP_CTRL, GM_GPCR_FL_PASS |
38782 +                       GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
38783 +
38784 +               if (CHIP_ID_YUKON_2(pAC)) {
38785 +                       /* set power down bit */
38786 +                       PowerDownBit = (Port == MAC_1) ? PCI_Y2_PHY1_POWD :
38787 +                               PCI_Y2_PHY2_POWD;
38788 +
38789 +                       if (ChipId != CHIP_ID_YUKON_EC) {
38790 +
38791 +                               if (ChipId == CHIP_ID_YUKON_EC_U) {
38792 +
38793 +                                       SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
38794 +                                       /* enable Power Down */
38795 +                                       Word |= PHY_M_PC_POW_D_ENA;
38796 +                                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
38797 +                               }
38798 +
38799 +                               /* set IEEE compatible Power Down Mode (dev. #4.99) */
38800 +                               Ret = SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PHY_CT_PDOWN);
38801 +                       }
38802 +               }
38803 +               else {
38804 +                       /* apply COMA mode workaround for Yukon-Plus*/
38805 +                       (void)SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_ADDR, 0x001f);
38806 +
38807 +                       Ret = SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xfff3);
38808 +
38809 +                       PowerDownBit = PCI_PHY_COMA;
38810 +               }
38811 +
38812 +               SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
38813 +
38814 +               SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_1), &DWord);
38815 +
38816 +               /* set PHY to PowerDown/COMA Mode */
38817 +               SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_1), DWord | PowerDownBit);
38818 +
38819 +               /* check if this routine was called from a for() loop */
38820 +               if (CHIP_ID_YUKON_2(pAC) &&
38821 +                       (pAC->GIni.GIMacsFound == 1 || Port == MAC_2)) {
38822 +
38823 +                       /* ASF system clock stopped */
38824 +                       SK_OUT8(IoC, B28_Y2_ASF_STAT_CMD, (SK_U8)Y2_ASF_CLK_HALT);
38825 +
38826 +                       if (ChipId == CHIP_ID_YUKON_EC_U) {
38827 +                               /* set GPHY Control reset */
38828 +                               SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_SET);
38829 +
38830 +                               /* additional power saving measurements */
38831 +                               SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_4), &DWord);
38832 +
38833 +                               /* set gating core clock for LTSSM in L1 state */
38834 +                               DWord |= (P_PEX_LTSSM_STAT(P_PEX_LTSSM_L1_STAT) |
38835 +                                       /* auto clock gated scheme controlled by CLKREQ */
38836 +                                       P_ASPM_A1_MODE_SELECT |
38837 +                                       /* enable Gate Root Core Clock */
38838 +                                       P_CLK_GATE_ROOT_COR_ENA);
38839 +
38840 +                               if (HW_FEATURE(pAC, HWF_WA_DEV_4200)) {
38841 +                                       /* enable Clock Power Management (CLKREQ) */
38842 +                                       SK_IN16(IoC, PCI_C(pAC, PEX_LNK_CTRL), &Word);
38843 +                                       Word |= PEX_LC_CLK_PM_ENA;
38844 +                                       SK_OUT16(IoC, PCI_C(pAC, PEX_LNK_CTRL), Word);
38845 +                               }
38846 +                               else {
38847 +                                       /* force CLKREQ Enable in Our4 (A1b only) */
38848 +                                       DWord |= P_ASPM_FORCE_CLKREQ_ENA;
38849 +                               }
38850 +
38851 +                               SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_4), DWord);
38852 +
38853 +                               /* set Mask Register for Release/Gate Clock */
38854 +                               SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_5),
38855 +                                       P_REL_PCIE_EXIT_L1_ST | P_GAT_PCIE_ENTER_L1_ST |
38856 +                                       P_REL_PCIE_RX_EX_IDLE | P_GAT_PCIE_RX_EL_IDLE |
38857 +                                       P_REL_GPHY_LINK_UP | P_GAT_GPHY_LINK_DOWN);
38858 +                       }
38859 +
38860 +                       if (HW_FEATURE(pAC, HWF_RED_CORE_CLK_SUP)) {
38861 +                               /* divide clock by 4 only for Yukon-EC */
38862 +                               ClkDiv = (ChipId == CHIP_ID_YUKON_EC) ? 1 : 0;
38863 +
38864 +                               /* on Yukon-2 clock select value is 31 */
38865 +                               DWord = (ChipId == CHIP_ID_YUKON_XL) ?
38866 +                                       (Y2_CLK_DIV_VAL_2(0) | Y2_CLK_SEL_VAL_2(31)) :
38867 +                                        Y2_CLK_DIV_VAL(ClkDiv);
38868 +
38869 +                               /* check for Yukon-2 dual port PCI-Express adapter */
38870 +                               if (!(pAC->GIni.GIMacsFound == 2 &&
38871 +                                         pAC->GIni.GIPciBus == SK_PEX_BUS)) {
38872 +                                       /* enable Core Clock Division */
38873 +                                       DWord |= Y2_CLK_DIV_ENA;
38874 +                               }
38875 +
38876 +                               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38877 +                                       ("Set Core Clock: 0x%08X\n", DWord));
38878 +
38879 +                               /* reduce Core Clock Frequency */
38880 +                               SK_OUT32(IoC, B2_Y2_CLK_CTRL, DWord);
38881 +                       }
38882 +
38883 +                       if (HW_FEATURE(pAC, HWF_CLK_GATING_ENABLE)) {
38884 +                               /* check for Yukon-2 Rev. A2 */
38885 +                               if (ChipId == CHIP_ID_YUKON_XL &&
38886 +                                       pAC->GIni.GIChipRev > CHIP_REV_YU_XL_A1) {
38887 +                                       /* enable bits are inverted */
38888 +                                       Byte = 0;
38889 +                               }
38890 +                               else {
38891 +                                       Byte = (SK_U8)(Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
38892 +                                               Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
38893 +                                               Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
38894 +                               }
38895 +
38896 +                               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38897 +                                       ("Set Clock Gating: 0x%02X\n", Byte));
38898 +
38899 +                               /* disable MAC/PHY, PCI and Core Clock for both Links */
38900 +                               SK_OUT8(IoC, B2_Y2_CLK_GATE, Byte);
38901 +                       }
38902 +
38903 +                       if (pAC->GIni.GIVauxAvail) {
38904 +                               /* switch power to VAUX */
38905 +                               SK_OUT8(IoC, B0_POWER_CTRL, (SK_U8)(PC_VAUX_ENA | PC_VCC_ENA |
38906 +                                       PC_VAUX_ON | PC_VCC_OFF));
38907 +                       }
38908 +#ifdef DEBUG
38909 +                       SK_IN32(IoC, B0_CTST, &DWord);
38910 +
38911 +                       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38912 +                               ("Ctrl/Stat & Switch: 0x%08x\n", DWord));
38913 +#endif /* DEBUG */
38914 +
38915 +                       if (pAC->GIni.GILevel != SK_INIT_IO &&
38916 +                               pAC->GIni.GIMacsFound == 1 &&
38917 +                               pAC->GIni.GIPciBus == SK_PEX_BUS) {
38918 +
38919 +                               if (ChipId == CHIP_ID_YUKON_EC_U) {
38920 +
38921 +#ifdef PCI_E_L1_STATE
38922 +                                       SK_IN16(IoC, PCI_C(pAC, PCI_OUR_REG_1), &Word);
38923 +                                       /* force to PCIe L1 */
38924 +                                       Word |= (SK_U16)PCI_FORCE_PEX_L1;
38925 +                                       SK_OUT16(IoC, PCI_C(pAC, PCI_OUR_REG_1), Word);
38926 +#endif /* PCI_E_L1_STATE */
38927 +                               }
38928 +                               else {
38929 +                                       /* switch to D1 state */
38930 +                                       SK_OUT8(IoC, PCI_C(pAC, PCI_PM_CTL_STS), PCI_PM_STATE_D1);
38931 +                               }
38932 +                       }
38933 +               }
38934 +
38935 +               break;
38936 +
38937 +       /* IEEE 22.2.4.1.5 compatible power down mode */
38938 +       case PHY_PM_IEEE_POWER_DOWN:
38939 +
38940 +               if (!CHIP_ID_YUKON_2(pAC) && !pAC->GIni.GIYukonLite) {
38941 +
38942 +                       Ret = SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
38943 +
38944 +                       /* disable MAC 125 MHz clock */
38945 +                       Word |= PHY_M_PC_DIS_125CLK;
38946 +                       Word &= ~PHY_M_PC_MAC_POW_UP;
38947 +
38948 +                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
38949 +
38950 +                       /* these register changes must be followed by a software reset */
38951 +                       SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word);
38952 +
38953 +                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word | PHY_CT_RESET);
38954 +               }
38955 +
38956 +               /* switch IEEE compatible power down mode on */
38957 +               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PHY_CT_PDOWN);
38958 +
38959 +               break;
38960 +
38961 +       /* energy detect and energy detect plus mode */
38962 +       case PHY_PM_ENERGY_DETECT:
38963 +       case PHY_PM_ENERGY_DETECT_PLUS:
38964 +
38965 +               Ret = SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
38966 +
38967 +#ifdef XXX
38968 +               /* disable Polarity Reversal */
38969 +               Word |= PHY_M_PC_POL_R_DIS;
38970 +#endif /* XXX */
38971 +
38972 +               if (!CHIP_ID_YUKON_2(pAC)) {
38973 +                       /* disable MAC 125 MHz clock */
38974 +                       Word |= PHY_M_PC_DIS_125CLK;
38975 +               }
38976 +
38977 +               if (ChipId == CHIP_ID_YUKON_FE) {
38978 +                       /* enable Energy Detect (sense & pulse) */
38979 +                       Word |= PHY_M_PC_ENA_ENE_DT;
38980 +               }
38981 +               else {
38982 +                       /* clear energy detect mode bits */
38983 +                       Word &= ~PHY_M_PC_EN_DET_MSK;
38984 +
38985 +                       Word |= (Mode == PHY_PM_ENERGY_DETECT) ? PHY_M_PC_EN_DET :
38986 +                               PHY_M_PC_EN_DET_PLUS;
38987 +               }
38988 +
38989 +               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
38990 +
38991 +               /* these register changes must be followed by a software reset */
38992 +               SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word);
38993 +               Word |= PHY_CT_RESET;
38994 +               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word);
38995 +
38996 +               if (ChipId == CHIP_ID_YUKON_EC_U) {
38997 +                       /* additional power saving measurements */
38998 +                       SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_4), &DWord);
38999 +
39000 +                       /* set gating core clock for LTSSM in L1 state */
39001 +                       DWord |= (P_PEX_LTSSM_STAT(P_PEX_LTSSM_L1_STAT) |
39002 +                               /* auto clock gated scheme controlled by CLKREQ */
39003 +                               P_ASPM_A1_MODE_SELECT |
39004 +                               /* Enable Gate Root Core Clock */
39005 +                               P_CLK_GATE_ROOT_COR_ENA);
39006 +
39007 +                       if (HW_FEATURE(pAC, HWF_WA_DEV_4200)) {
39008 +                               /* enable Clock Power Management (CLKREQ) */
39009 +                               SK_IN16(IoC, PCI_C(pAC, PEX_LNK_CTRL), &Word);
39010 +                               Word |= PEX_LC_CLK_PM_ENA;
39011 +                               SK_OUT16(IoC, PCI_C(pAC, PEX_LNK_CTRL), Word);
39012 +                       }
39013 +                       else {
39014 +                               /* force CLKREQ Enable in Our4 (A1b only) */
39015 +                               DWord |= P_ASPM_FORCE_CLKREQ_ENA;
39016 +                       }
39017 +
39018 +                       SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_4), DWord);
39019 +
39020 +                       /* set Mask Register for Release/Gate Clock */
39021 +                       SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_5),
39022 +                               P_REL_PCIE_EXIT_L1_ST | P_GAT_PCIE_ENTER_L1_ST |
39023 +                               P_REL_PCIE_RX_EX_IDLE | P_GAT_PCIE_RX_EL_IDLE |
39024 +                               P_REL_GPHY_LINK_UP | P_GAT_GPHY_LINK_DOWN);
39025 +
39026 +#ifdef PCI_E_L1_STATE
39027 +                       SK_IN16(IoC, PCI_C(pAC, PCI_OUR_REG_1), &Word);
39028 +                       /* enable PCIe L1 on GPHY link down */
39029 +                       Word |= (SK_U16)PCI_ENA_GPHY_LNK;
39030 +                       SK_OUT16(IoC, PCI_C(pAC, PCI_OUR_REG_1), Word);
39031 +#endif /* PCI_E_L1_STATE */
39032 +               }
39033 +
39034 +               break;
39035 +
39036 +       /* don't change current power mode */
39037 +       default:
39038 +               pAC->GIni.GP[Port].PPhyPowerState = LastMode;
39039 +               Ret = 1;
39040 +       }
39041 +
39042 +       return(Ret);
39043 +
39044 +}      /* SkGmEnterLowPowerMode */
39045 +
39046 +/******************************************************************************
39047 + *
39048 + *     SkGmLeaveLowPowerMode()
39049 + *
39050 + * Description:
39051 + *     Leave the current low power mode and switch to normal mode
39052 + *
39053 + * Note:
39054 + *
39055 + * Returns:
39056 + *             0:      ok
39057 + *             1:      error
39058 + */
39059 +int SkGmLeaveLowPowerMode(
39060 +SK_AC  *pAC,           /* Adapter Context */
39061 +SK_IOC IoC,            /* I/O Context */
39062 +int            Port)           /* Port Index (e.g. MAC_1) */
39063 +{
39064 +       SK_U32  DWord;
39065 +       SK_U32  PowerDownBit;
39066 +       SK_U16  Word;
39067 +       SK_U8   LastMode;
39068 +       int             ChipId;
39069 +       int             Ret = 0;
39070 +
39071 +       if (!(CHIP_ID_YUKON_2(pAC) || (pAC->GIni.GIYukonLite &&
39072 +               pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3))) {
39073 +
39074 +               return(1);
39075 +       }
39076 +
39077 +       /* save current power mode */
39078 +       LastMode = pAC->GIni.GP[Port].PPhyPowerState;
39079 +       pAC->GIni.GP[Port].PPhyPowerState = PHY_PM_OPERATIONAL_MODE;
39080 +
39081 +       ChipId = pAC->GIni.GIChipId;
39082 +
39083 +       SK_DBG_MSG(pAC, SK_DBGMOD_POWM, SK_DBGCAT_CTRL,
39084 +               ("SkGmLeaveLowPowerMode: %u\n", LastMode));
39085 +
39086 +       switch (LastMode) {
39087 +       /* COMA mode (deep sleep) */
39088 +       case PHY_PM_DEEP_SLEEP:
39089 +
39090 +               if (ChipId == CHIP_ID_YUKON_EC_U) {
39091 +#ifdef PCI_E_L1_STATE
39092 +                       /* set to default value (leave PCIe L1) */
39093 +                       SkPciWriteCfgWord(pAC, PCI_OUR_REG_1, 0);
39094 +#endif /* PCI_E_L1_STATE */
39095 +
39096 +                       SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_4), &DWord);
39097 +
39098 +                       DWord &= P_ASPM_CONTROL_MSK;
39099 +                       /* set all bits to 0 except bits 15..12 */
39100 +                       SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_4), DWord);
39101 +
39102 +                       /* set to default value */
39103 +                       SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_5), 0);
39104 +               }
39105 +               else {
39106 +                       SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &Word);
39107 +
39108 +                       /* reset all DState bits */
39109 +                       Word &= ~PCI_PM_STATE_MSK;
39110 +
39111 +                       /* switch to D0 state */
39112 +                       SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, Word);
39113 +               }
39114 +
39115 +               SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
39116 +
39117 +               if (CHIP_ID_YUKON_2(pAC)) {
39118 +                       /* disable Core Clock Division */
39119 +                       SK_OUT32(IoC, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
39120 +
39121 +                       /* set power down bit */
39122 +                       PowerDownBit = (Port == MAC_1) ? PCI_Y2_PHY1_POWD :
39123 +                               PCI_Y2_PHY2_POWD;
39124 +               }
39125 +               else {
39126 +                       PowerDownBit = PCI_PHY_COMA;
39127 +               }
39128 +
39129 +               SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_1), &DWord);
39130 +
39131 +               /* Release PHY from PowerDown/COMA Mode */
39132 +               SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_1), DWord & ~PowerDownBit);
39133 +
39134 +               SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
39135 +
39136 +               if (CHIP_ID_YUKON_2(pAC)) {
39137 +
39138 +                       if (ChipId == CHIP_ID_YUKON_FE) {
39139 +                               /* release IEEE compatible Power Down Mode */
39140 +                               Ret = SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PHY_CT_ANE);
39141 +                       }
39142 +                       else if (ChipId == CHIP_ID_YUKON_EC_U) {
39143 +                               /* release GPHY Control reset */
39144 +                               SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_CLR);
39145 +                       }
39146 +               }
39147 +               else {
39148 +                       SK_IN32(IoC, B2_GP_IO, &DWord);
39149 +
39150 +                       /* set to output */
39151 +                       DWord |= (GP_DIR_9 | GP_IO_9);
39152 +
39153 +                       /* set PHY reset */
39154 +                       SK_OUT32(IoC, B2_GP_IO, DWord);
39155 +
39156 +                       DWord &= ~GP_IO_9;      /* clear PHY reset (active high) */
39157 +
39158 +                       /* clear PHY reset */
39159 +                       SK_OUT32(IoC, B2_GP_IO, DWord);
39160 +               }
39161 +
39162 +               break;
39163 +
39164 +       /* IEEE 22.2.4.1.5 compatible power down mode */
39165 +       case PHY_PM_IEEE_POWER_DOWN:
39166 +
39167 +               if (ChipId != CHIP_ID_YUKON_XL) {
39168 +
39169 +                       Ret = SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
39170 +                       Word &= ~PHY_M_PC_DIS_125CLK;   /* enable MAC 125 MHz clock */
39171 +                       Word |= PHY_M_PC_MAC_POW_UP;    /* set MAC power up */
39172 +                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
39173 +
39174 +                       /* these register changes must be followed by a software reset */
39175 +                       SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word);
39176 +                       Word |= PHY_CT_RESET;
39177 +                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word);
39178 +               }
39179 +
39180 +               /* switch IEEE compatible power down mode off */
39181 +               SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word);
39182 +               Word &= ~PHY_CT_PDOWN;
39183 +               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word);
39184 +
39185 +               break;
39186 +
39187 +       /* energy detect and energy detect plus mode */
39188 +       case PHY_PM_ENERGY_DETECT:
39189 +       case PHY_PM_ENERGY_DETECT_PLUS:
39190 +
39191 +               if (ChipId != CHIP_ID_YUKON_XL) {
39192 +
39193 +                       Ret = SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
39194 +
39195 +                       if (ChipId == CHIP_ID_YUKON_FE) {
39196 +                               /* disable Energy Detect */
39197 +                               Word &= ~PHY_M_PC_ENA_ENE_DT;
39198 +                       }
39199 +                       else {
39200 +                               /* disable energy detect mode & enable MAC 125 MHz clock */
39201 +                               Word &= ~(PHY_M_PC_EN_DET_MSK | PHY_M_PC_DIS_125CLK);
39202 +                       }
39203 +
39204 +#ifdef XXX
39205 +                       /* enable Polarity Reversal */
39206 +                       Word &= ~PHY_M_PC_POL_R_DIS;
39207 +#endif /* XXX */
39208 +
39209 +                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
39210 +
39211 +                       /* these register changes must be followed by a software reset */
39212 +                       SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word);
39213 +                       Word |= PHY_CT_RESET;
39214 +                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word);
39215 +               }
39216 +               break;
39217 +
39218 +       /* don't change current power mode */
39219 +       default:
39220 +               pAC->GIni.GP[Port].PPhyPowerState = LastMode;
39221 +               Ret = 1;
39222 +       }
39223 +
39224 +       return(Ret);
39225 +
39226 +}      /* SkGmLeaveLowPowerMode */
39227 +#endif /* SK_PHY_LP_MODE */
39228 +
39229  /******************************************************************************
39230   *
39231 - *     SkGmInitPhyMarv() - Initialize the Marvell Phy registers
39232 + *     SkGmInitPhyMarv() - Initialize the Marvell PHY registers
39233   *
39234 - * Description:        initializes all the Marvell Phy registers
39235 + * Description:        initializes all the Marvell PHY registers
39236   *
39237   * Note:
39238   *
39239 @@ -2057,107 +2711,246 @@
39240   *     nothing
39241   */
39242  static void SkGmInitPhyMarv(
39243 -SK_AC  *pAC,           /* adapter context */
39244 -SK_IOC IoC,            /* IO context */
39245 +SK_AC  *pAC,           /* Adapter Context */
39246 +SK_IOC IoC,            /* I/O Context */
39247  int            Port,           /* Port Index (MAC_1 + n) */
39248 -SK_BOOL        DoLoop)         /* Should a Phy LoopBack be set-up? */
39249 +SK_BOOL        DoLoop)         /* Should a PHY LoopBack be set-up? */
39250  {
39251         SK_GEPORT       *pPrt;
39252 +       SK_BOOL         AutoNeg;
39253         SK_U16          PhyCtrl;
39254         SK_U16          C1000BaseT;
39255         SK_U16          AutoNegAdv;
39256 +       SK_U8           PauseMode;
39257 +       int                     ChipId;
39258 +       int                     Mode;
39259 +#ifndef VCPU
39260 +       SK_U16          Word;
39261 +       SK_U16          PageReg;
39262 +#ifndef SK_SLIM
39263 +       SK_U16          LoopSpeed;
39264 +#endif /* !SK_SLIM */
39265         SK_U16          ExtPhyCtrl;
39266 +       SK_U16          BlinkCtrl;
39267         SK_U16          LedCtrl;
39268 -       SK_BOOL         AutoNeg;
39269 +       SK_U16          LedConf;
39270 +       SK_U16          LedOver;
39271 +#ifndef SK_DIAG
39272 +       SK_EVPARA       Para;
39273 +#endif /* !SK_DIAG */
39274  #if defined(SK_DIAG) || defined(DEBUG)
39275         SK_U16          PhyStat;
39276         SK_U16          PhyStat1;
39277         SK_U16          PhySpecStat;
39278  #endif /* SK_DIAG || DEBUG */
39279 +#endif /* !VCPU */
39280 +
39281 +       /* set Pause On */
39282 +       PauseMode = (SK_U8)GMC_PAUSE_ON;
39283
39284         pPrt = &pAC->GIni.GP[Port];
39285
39286 +       ChipId = pAC->GIni.GIChipId;
39287 +
39288         /* Auto-negotiation ? */
39289 -       if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
39290 -               AutoNeg = SK_FALSE;
39291 +       AutoNeg = pPrt->PLinkMode != SK_LMODE_HALF &&
39292 +                         pPrt->PLinkMode != SK_LMODE_FULL;
39293 +
39294 +       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39295 +               ("InitPhyMarv: Port %d, Auto-neg. %s, LMode %d, LSpeed %d, FlowC %d\n",
39296 +                Port, AutoNeg ? "ON" : "OFF",
39297 +                pPrt->PLinkMode, pPrt->PLinkSpeed, pPrt->PFlowCtrlMode));
39298 +
39299 +#ifndef VCPU
39300 +       /* read Id from PHY */
39301 +       if (SkGmPhyRead(pAC, IoC, Port, PHY_MARV_ID1, &pPrt->PhyId1) != 0) {
39302 +
39303 +#ifndef SK_DIAG
39304 +               Para.Para64 = Port;
39305 +               SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
39306 +#endif /* !SK_DIAG */
39307 +
39308 +               return;
39309         }
39310 -       else {
39311 -               AutoNeg = SK_TRUE;
39312 +
39313 +       if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
39314 +
39315 +#ifndef SK_SLIM
39316 +               if (DoLoop) {
39317 +                       /* special setup for PHY 88E1112 */
39318 +                       if (ChipId == CHIP_ID_YUKON_XL) {
39319 +
39320 +                               LoopSpeed = pPrt->PLinkSpeed;
39321 +
39322 +                               if (LoopSpeed == SK_LSPEED_AUTO) {
39323 +                                       /* force 1000 Mbps */
39324 +                                       LoopSpeed = SK_LSPEED_1000MBPS;
39325 +                               }
39326 +                               LoopSpeed += 2;
39327 +
39328 +                               /* save page register */
39329 +                               SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_ADR, &PageReg);
39330 +
39331 +                               /* select page 2 to access MAC control register */
39332 +                               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 2);
39333 +
39334 +                               /* set MAC interface speed */
39335 +                               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, LoopSpeed << 4);
39336 +
39337 +                               /* restore page register */
39338 +                               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, PageReg);
39339 +
39340 +                               /* disable link pulses */
39341 +                               Word = PHY_M_PC_DIS_LINK_P;
39342 +                       }
39343 +                       else {
39344 +                               /* set 'MAC Power up'-bit, set Manual MDI configuration */
39345 +                               Word = PHY_M_PC_MAC_POW_UP;
39346 +                       }
39347 +
39348 +                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
39349 +               }
39350 +               else
39351 +#endif /* !SK_SLIM */
39352 +               if (AutoNeg && pPrt->PLinkSpeed == SK_LSPEED_AUTO &&
39353 +                               !(ChipId == CHIP_ID_YUKON_XL || ChipId == CHIP_ID_YUKON_EC_U)) {
39354 +                       /* Read Ext. PHY Specific Control */
39355 +                       SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl);
39356 +
39357 +                       ExtPhyCtrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
39358 +                               PHY_M_EC_MAC_S_MSK);
39359 +
39360 +                       ExtPhyCtrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
39361 +
39362 +                       /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
39363 +                       if (pAC->GIni.GIYukonLite || ChipId == CHIP_ID_YUKON_EC) {
39364 +                               /* set downshift counter to 3x and enable downshift */
39365 +                               ExtPhyCtrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
39366 +                       }
39367 +                       else {
39368 +                               /* set master & slave downshift counter to 1x */
39369 +                               ExtPhyCtrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
39370 +                       }
39371 +
39372 +                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_CTRL, ExtPhyCtrl);
39373 +                       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39374 +                               ("Set Ext. PHY Ctrl = 0x%04X\n", ExtPhyCtrl));
39375 +               }
39376         }
39377 -
39378 -       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39379 -               ("InitPhyMarv: Port %d, auto-negotiation %s\n",
39380 -                Port, AutoNeg ? "ON" : "OFF"));
39381
39382 -#ifdef VCPU
39383 -       VCPUprintf(0, "SkGmInitPhyMarv(), Port=%u, DoLoop=%u\n",
39384 -               Port, DoLoop);
39385 -#else /* VCPU */
39386 -       if (DoLoop) {
39387 -               /* Set 'MAC Power up'-bit, set Manual MDI configuration */
39388 -               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL,
39389 -                       PHY_M_PC_MAC_POW_UP);
39390 +       if (CHIP_ID_YUKON_2(pAC)) {
39391 +               /* Read PHY Specific Control */
39392 +               SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &PhyCtrl);
39393 +
39394 +               if (!DoLoop && pAC->GIni.GICopperType) {
39395 +
39396 +                       if (ChipId == CHIP_ID_YUKON_FE) {
39397 +                               /* enable Automatic Crossover (!!! Bits 5..4) */
39398 +                               PhyCtrl |= (SK_U16)(PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1);
39399 +                       }
39400 +                       else {
39401 +#ifndef SK_DIAG
39402 +                               /* disable Energy Detect Mode */
39403 +                               PhyCtrl &= ~PHY_M_PC_EN_DET_MSK;
39404 +#endif /* !SK_DIAG */
39405 +
39406 +                               /* enable Automatic Crossover */
39407 +                               PhyCtrl |= (SK_U16)PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
39408 +
39409 +                               /* downshift on PHY 88E1112 and 88E1149 is changed */
39410 +                               if (AutoNeg && pPrt->PLinkSpeed == SK_LSPEED_AUTO &&
39411 +                                       (ChipId == CHIP_ID_YUKON_XL ||
39412 +                                        ChipId == CHIP_ID_YUKON_EC_U)) {
39413 +                                       /* set downshift counter to 3x and enable downshift */
39414 +                                       PhyCtrl &= ~PHY_M_PC_DSC_MSK;
39415 +                                       PhyCtrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
39416 +                               }
39417 +                       }
39418 +               }
39419 +               /* workaround for deviation #4.88 (CRC errors) */
39420 +               else {
39421 +                       /* disable Automatic Crossover */
39422 +                       PhyCtrl &= ~PHY_M_PC_MDIX_MSK;
39423 +               }
39424 +
39425 +               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, PhyCtrl);
39426         }
39427 -       else if (AutoNeg && pPrt->PLinkSpeed == SK_LSPEED_AUTO) {
39428 -               /* Read Ext. PHY Specific Control */
39429 -               SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl);
39430 -
39431 -               ExtPhyCtrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
39432 -                       PHY_M_EC_MAC_S_MSK);
39433 -
39434 -               ExtPhyCtrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ) |
39435 -                       PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
39436 -
39437 -               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_CTRL, ExtPhyCtrl);
39438 -               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39439 -                       ("Set Ext. PHY Ctrl=0x%04X\n", ExtPhyCtrl));
39440 +
39441 +       /* special setup for PHY 88E1112 Fiber */
39442 +       if (ChipId == CHIP_ID_YUKON_XL && !pAC->GIni.GICopperType) {
39443 +               /* select 1000BASE-X only mode in MAC Specific Ctrl Reg. */
39444 +               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 2);
39445 +
39446 +               SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
39447 +
39448 +               Word &= ~PHY_M_MAC_MD_MSK;
39449 +               Word |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
39450 +
39451 +               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
39452 +
39453 +               /* select page 1 to access Fiber registers */
39454 +               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 1);
39455 +
39456 +               if (pAC->GIni.GIPmdTyp == 'P') {
39457 +                       /* for SFP-module set SIGDET polarity to low */
39458 +                       SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
39459 +
39460 +                       Word |= PHY_M_FIB_SIGD_POL;
39461 +
39462 +                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
39463 +               }
39464         }
39465
39466         /* Read PHY Control */
39467         SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &PhyCtrl);
39468
39469         if (!AutoNeg) {
39470 -               /* Disable Auto-negotiation */
39471 +               /* disable Auto-negotiation */
39472                 PhyCtrl &= ~PHY_CT_ANE;
39473         }
39474
39475         PhyCtrl |= PHY_CT_RESET;
39476 -       /* Assert software reset */
39477 +       /* assert software reset */
39478         SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PhyCtrl);
39479 -#endif /* VCPU */
39480 +#endif /* !VCPU */
39481
39482         PhyCtrl = 0 /* PHY_CT_COL_TST */;
39483         C1000BaseT = 0;
39484         AutoNegAdv = PHY_SEL_TYPE;
39485
39486 +#ifndef SK_SLIM
39487         /* manually Master/Slave ? */
39488         if (pPrt->PMSMode != SK_MS_MODE_AUTO) {
39489                 /* enable Manual Master/Slave */
39490                 C1000BaseT |= PHY_M_1000C_MSE;
39491 -
39492 +
39493                 if (pPrt->PMSMode == SK_MS_MODE_MASTER) {
39494                         C1000BaseT |= PHY_M_1000C_MSC;  /* set it to Master */
39495                 }
39496         }
39497 -
39498 +#endif /* !SK_SLIM */
39499 +
39500         /* Auto-negotiation ? */
39501         if (!AutoNeg) {
39502 -
39503 +
39504                 if (pPrt->PLinkMode == SK_LMODE_FULL) {
39505 -                       /* Set Full Duplex Mode */
39506 +                       /* set Full Duplex Mode */
39507                         PhyCtrl |= PHY_CT_DUP_MD;
39508                 }
39509
39510 -               /* Set Master/Slave manually if not already done */
39511 +#ifndef SK_SLIM
39512 +               /* set Master/Slave manually if not already done */
39513                 if (pPrt->PMSMode == SK_MS_MODE_AUTO) {
39514                         C1000BaseT |= PHY_M_1000C_MSE;  /* set it to Slave */
39515                 }
39516 +#endif /* !SK_SLIM */
39517
39518 -               /* Set Speed */
39519 +               /* set Speed */
39520                 switch (pPrt->PLinkSpeed) {
39521                 case SK_LSPEED_AUTO:
39522                 case SK_LSPEED_1000MBPS:
39523 -                       PhyCtrl |= PHY_CT_SP1000;
39524 +                       PhyCtrl |= (((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) ?
39525 +                                               PHY_CT_SP1000 : PHY_CT_SP100);
39526                         break;
39527                 case SK_LSPEED_100MBPS:
39528                         PhyCtrl |= PHY_CT_SP100;
39529 @@ -2169,38 +2962,66 @@
39530                                 SKERR_HWI_E019MSG);
39531                 }
39532
39533 +               if ((pPrt->PFlowCtrlMode == SK_FLOW_STAT_NONE) ||
39534 +                       /* disable Pause also for 10/100 Mbps in half duplex mode */
39535 +                       ((ChipId != CHIP_ID_YUKON_EC_U) &&
39536 +                       (pPrt->PLinkMode == SK_LMODE_HALF) &&
39537 +                        ((pPrt->PLinkSpeed == SK_LSPEED_STAT_100MBPS) ||
39538 +                         (pPrt->PLinkSpeed == SK_LSPEED_STAT_10MBPS)))) {
39539 +
39540 +                       /* set Pause Off */
39541 +                       PauseMode = (SK_U8)GMC_PAUSE_OFF;
39542 +               }
39543 +
39544 +               SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), PauseMode);
39545 +
39546                 if (!DoLoop) {
39547 +                       /* assert software reset */
39548                         PhyCtrl |= PHY_CT_RESET;
39549                 }
39550         }
39551         else {
39552 -               /* Set Auto-negotiation advertisement */
39553 -
39554 +               /* set Auto-negotiation advertisement */
39555 +
39556                 if (pAC->GIni.GICopperType) {
39557 -                       /* Set Speed capabilities */
39558 +                       /* set Speed capabilities */
39559                         switch (pPrt->PLinkSpeed) {
39560                         case SK_LSPEED_AUTO:
39561 -                               C1000BaseT |= PHY_M_1000C_AHD | PHY_M_1000C_AFD;
39562 +                               if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
39563 +                                       C1000BaseT |= PHY_M_1000C_AFD;
39564 +#ifdef xSK_DIAG
39565 +                                       C1000BaseT |= PHY_M_1000C_AHD;
39566 +#endif /* SK_DIAG */
39567 +                               }
39568                                 AutoNegAdv |= PHY_M_AN_100_FD | PHY_M_AN_100_HD |
39569                                         PHY_M_AN_10_FD | PHY_M_AN_10_HD;
39570                                 break;
39571                         case SK_LSPEED_1000MBPS:
39572 -                               C1000BaseT |= PHY_M_1000C_AHD | PHY_M_1000C_AFD;
39573 +                               if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
39574 +                                       C1000BaseT |= PHY_M_1000C_AFD;
39575 +#ifdef xSK_DIAG
39576 +                                       C1000BaseT |= PHY_M_1000C_AHD;
39577 +#endif /* SK_DIAG */
39578 +                               }
39579                                 break;
39580                         case SK_LSPEED_100MBPS:
39581 -                               AutoNegAdv |= PHY_M_AN_100_FD | PHY_M_AN_100_HD |
39582 -                                       /* advertise 10Base-T also */
39583 -                                       PHY_M_AN_10_FD | PHY_M_AN_10_HD;
39584 +                               if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_100MBPS) != 0) {
39585 +                                       AutoNegAdv |= PHY_M_AN_100_FD | PHY_M_AN_100_HD |
39586 +                                               /* advertise 10Base-T also */
39587 +                                               PHY_M_AN_10_FD | PHY_M_AN_10_HD;
39588 +                               }
39589                                 break;
39590                         case SK_LSPEED_10MBPS:
39591 -                               AutoNegAdv |= PHY_M_AN_10_FD | PHY_M_AN_10_HD;
39592 +                               if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_10MBPS) != 0) {
39593 +                                       AutoNegAdv |= PHY_M_AN_10_FD | PHY_M_AN_10_HD;
39594 +                               }
39595                                 break;
39596                         default:
39597                                 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E019,
39598                                         SKERR_HWI_E019MSG);
39599                         }
39600
39601 -                       /* Set Full/half duplex capabilities */
39602 +                       /* set Full/half duplex capabilities */
39603                         switch (pPrt->PLinkMode) {
39604                         case SK_LMODE_AUTOHALF:
39605                                 C1000BaseT &= ~PHY_M_1000C_AFD;
39606 @@ -2216,8 +3037,8 @@
39607                                 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E015,
39608                                         SKERR_HWI_E015MSG);
39609                         }
39610 -
39611 -                       /* Set Flow-control capabilities */
39612 +
39613 +                       /* set Flow-control capabilities */
39614                         switch (pPrt->PFlowCtrlMode) {
39615                         case SK_FLOW_MODE_NONE:
39616                                 AutoNegAdv |= PHY_B_P_NO_PAUSE;
39617 @@ -2236,9 +3057,9 @@
39618                                         SKERR_HWI_E016MSG);
39619                         }
39620                 }
39621 -               else {  /* special defines for FIBER (88E1011S only) */
39622 -
39623 -                       /* Set Full/half duplex capabilities */
39624 +               else {  /* special defines for FIBER (88E1040S only) */
39625 +
39626 +                       /* set Full/half duplex capabilities */
39627                         switch (pPrt->PLinkMode) {
39628                         case SK_LMODE_AUTOHALF:
39629                                 AutoNegAdv |= PHY_M_AN_1000X_AHD;
39630 @@ -2253,8 +3074,8 @@
39631                                 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E015,
39632                                         SKERR_HWI_E015MSG);
39633                         }
39634 -
39635 -                       /* Set Flow-control capabilities */
39636 +
39637 +                       /* set Flow-control capabilities */
39638                         switch (pPrt->PFlowCtrlMode) {
39639                         case SK_FLOW_MODE_NONE:
39640                                 AutoNegAdv |= PHY_M_P_NO_PAUSE_X;
39641 @@ -2279,138 +3100,247 @@
39642                         PhyCtrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
39643                 }
39644         }
39645 -
39646 +
39647  #ifdef VCPU
39648         /*
39649          * E-mail from Gu Lin (08-03-2002):
39650          */
39651 -
39652 +
39653         /* Program PHY register 30 as 16'h0708 for simulation speed up */
39654         SkGmPhyWrite(pAC, IoC, Port, 30, 0x0700 /* 0x0708 */);
39655 -
39656 +
39657         VCpuWait(2000);
39658
39659 -#else /* VCPU */
39660 -
39661 -       /* Write 1000Base-T Control Register */
39662 -       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_1000T_CTRL, C1000BaseT);
39663 -       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39664 -               ("Set 1000B-T Ctrl =0x%04X\n", C1000BaseT));
39665 -
39666 +#else /* !VCPU */
39667 +
39668 +       if (ChipId != CHIP_ID_YUKON_FE) {
39669 +               /* Write 1000Base-T Control Register */
39670 +               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_1000T_CTRL, C1000BaseT);
39671 +               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39672 +                       ("Set 1000B-T Ctrl  = 0x%04X\n", C1000BaseT));
39673 +       }
39674 +
39675         /* Write AutoNeg Advertisement Register */
39676         SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_AUNE_ADV, AutoNegAdv);
39677         SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39678 -               ("Set Auto-Neg.Adv.=0x%04X\n", AutoNegAdv));
39679 -#endif /* VCPU */
39680 -
39681 +               ("Set Auto-Neg.Adv. = 0x%04X\n", AutoNegAdv));
39682 +#endif /* !VCPU */
39683 +
39684 +#ifndef SK_SLIM
39685         if (DoLoop) {
39686 -               /* Set the PHY Loopback bit */
39687 +               /* set the PHY Loopback bit */
39688                 PhyCtrl |= PHY_CT_LOOP;
39689 -
39690 -#ifdef XXX
39691 -               /* Program PHY register 16 as 16'h0400 to force link good */
39692 -               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, PHY_M_PC_FL_GOOD);
39693 -#endif /* XXX */
39694 -
39695 -#ifndef VCPU
39696 -               if (pPrt->PLinkSpeed != SK_LSPEED_AUTO) {
39697 -                       /* Write Ext. PHY Specific Control */
39698 -                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_CTRL,
39699 -                               (SK_U16)((pPrt->PLinkSpeed + 2) << 4));
39700 -               }
39701 -#endif /* VCPU */
39702 -       }
39703 -#ifdef TEST_ONLY
39704 -       else if (pPrt->PLinkSpeed == SK_LSPEED_10MBPS) {
39705 -                       /* Write PHY Specific Control */
39706 -                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL,
39707 -                               PHY_M_PC_EN_DET_MSK);
39708         }
39709 -#endif
39710 +#endif /* !SK_SLIM */
39711
39712         /* Write to the PHY Control register */
39713         SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PhyCtrl);
39714         SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39715 -               ("Set PHY Ctrl Reg.=0x%04X\n", PhyCtrl));
39716 +               ("Set PHY Ctrl Reg. = 0x%04X\n", PhyCtrl));
39717
39718  #ifdef VCPU
39719         VCpuWait(2000);
39720 -#else
39721 +#else /* !VCPU */
39722 +
39723 +       LedCtrl = PHY_M_LED_PULS_DUR(PULS_170MS);
39724 +
39725 +       LedOver = 0;
39726 +
39727 +       BlinkCtrl = pAC->GIni.GILedBlinkCtrl;
39728 +
39729 +       if ((BlinkCtrl & SK_ACT_LED_BLINK) != 0) {
39730 +
39731 +               if (ChipId == CHIP_ID_YUKON_FE) {
39732 +                       /* on 88E3082 these bits are at 11..9 (shifted left) */
39733 +                       LedCtrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
39734 +
39735 +                       SkGmPhyRead(pAC, IoC, Port, PHY_MARV_FE_LED_PAR, &Word);
39736 +
39737 +                       /* delete ACT LED control bits */
39738 +                       Word &= ~PHY_M_FELP_LED1_MSK;
39739 +                       /* change ACT LED control to blink mode */
39740 +                       Word |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
39741 +
39742 +                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_FE_LED_PAR, Word);
39743 +               }
39744 +               else if (ChipId == CHIP_ID_YUKON_XL || ChipId == CHIP_ID_YUKON_EC_U) {
39745 +                       /* save page register */
39746 +                       SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_ADR, &PageReg);
39747 +
39748 +                       /* select page 3 to access LED control register */
39749 +                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 3);
39750 +
39751 +                       LedConf = PHY_M_LEDC_LOS_CTRL(1) |              /* LINK/ACT (Yukon-2 only) */
39752 +                                         PHY_M_LEDC_STA1_CTRL(7) |             /* 100 Mbps */
39753 +                                         PHY_M_LEDC_STA0_CTRL(7);              /* 1000 Mbps */
39754
39755 -       LedCtrl = PHY_M_LED_PULS_DUR(PULS_170MS) | PHY_M_LED_BLINK_RT(BLINK_84MS);
39756 +                       Mode = 7;               /* 10 Mbps: On */
39757
39758 -       if ((pAC->GIni.GILedBlinkCtrl & SK_ACT_LED_BLINK) != 0) {
39759 -               LedCtrl |= PHY_M_LEDC_RX_CTRL | PHY_M_LEDC_TX_CTRL;
39760 +                       if (ChipId == CHIP_ID_YUKON_XL) {
39761 +                               /* set Polarity Control register */
39762 +                               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_STAT, (SK_U16)
39763 +                                       (PHY_M_POLC_LS1_P_MIX(4) | PHY_M_POLC_IS0_P_MIX(4) |
39764 +                                        PHY_M_POLC_LOS_CTRL(2) | PHY_M_POLC_INIT_CTRL(2) |
39765 +                                        PHY_M_POLC_STA1_CTRL(2) | PHY_M_POLC_STA0_CTRL(2)));
39766 +                       }
39767 +                       else if (ChipId == CHIP_ID_YUKON_EC_U) {
39768 +                               /* check for LINK_LED mux */
39769 +                               if ((BlinkCtrl & SK_LED_LINK_MUX_P60) != 0) {
39770 +
39771 +                                       SK_IN16(pAC, GPHY_CTRL, &Word);
39772 +
39773 +                                       Word |= GPC_LED_CONF_VAL(4);
39774 +
39775 +                                       /* set GPHY LED Config */
39776 +                                       SK_OUT16(pAC, GPHY_CTRL, Word);
39777 +                               }
39778 +                               else {
39779 +                                       Mode = 8;       /* Forced Off */
39780 +
39781 +                                       /* set LED[5:4] Function Control and Polarity register */
39782 +                                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_STAT, (SK_U16)
39783 +                                               (PHY_M_LEDC_STA1_CTRL(1) |      /* LED_ACT to Link/Act. */
39784 +                                                PHY_M_LEDC_STA0_CTRL(6)));     /* LED_DUP to Duplex */
39785 +                               }
39786 +
39787 +                               /* set Blink Rate in LED Timer Control Register */
39788 +                               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK,
39789 +                                       LedCtrl | (SK_U16)PHY_M_LED_BLINK_RT(BLINK_84MS));
39790 +                       }
39791 +
39792 +                       LedConf |= PHY_M_LEDC_INIT_CTRL(Mode);
39793 +
39794 +                       /* set LED Function Control register */
39795 +                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, LedConf);
39796 +
39797 +#if (defined(SK_DIAG) || (defined(DEBUG) && !defined(SK_SLIM)))
39798 +                       /* select page 6 to access Packet Generation register */
39799 +                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 6);
39800 +
39801 +                       SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &PhyCtrl);
39802 +
39803 +                       PhyCtrl |= BIT_4S;                      /* enable CRC checker */
39804 +
39805 +                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, PhyCtrl);
39806 +#endif /* SK_DIAG || (DEBUG && !SK_SLIM) */
39807 +
39808 +                       /* restore page register */
39809 +                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, PageReg);
39810 +               }
39811 +               else {
39812 +                       /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
39813 +                       LedCtrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
39814 +
39815 +                       /* on PHY 88E1111 there is a change for LED control */
39816 +                       if (ChipId == CHIP_ID_YUKON_EC &&
39817 +                               (BlinkCtrl & SK_DUAL_LED_ACT_LNK) != 0) {
39818 +                               /* Yukon-EC needs setting of 2 bits: 0,6=11) */
39819 +                               LedCtrl |= PHY_M_LEDC_TX_C_LSB;
39820 +                       }
39821 +                       /* turn off the Rx LED (LED_RX) */
39822 +                       LedOver |= PHY_M_LED_MO_RX(MO_LED_OFF);
39823 +               }
39824         }
39825
39826 -       if ((pAC->GIni.GILedBlinkCtrl & SK_DUP_LED_NORMAL) != 0) {
39827 +       if ((BlinkCtrl & SK_DUP_LED_NORMAL) != 0) {
39828 +               /* disable blink mode (LED_DUPLEX) on collisions */
39829                 LedCtrl |= PHY_M_LEDC_DP_CTRL;
39830         }
39831 -
39832 -       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_LED_CTRL, LedCtrl);
39833
39834 -       if ((pAC->GIni.GILedBlinkCtrl & SK_LED_LINK100_ON) != 0) {
39835 -               /* only in forced 100 Mbps mode */
39836 -               if (!AutoNeg && pPrt->PLinkSpeed == SK_LSPEED_100MBPS) {
39837 +       if (ChipId == CHIP_ID_YUKON_EC_U) {
39838 +               if (pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A1) {
39839 +                       /* apply fixes in PHY AFE */
39840 +                       SkGmPhyWrite(pAC, IoC, Port, 22, 255);
39841 +                       /* increase differential signal amplitude in 10BASE-T */
39842 +                       SkGmPhyWrite(pAC, IoC, Port, 24, 0xaa99);
39843 +                       SkGmPhyWrite(pAC, IoC, Port, 23, 0x2011);
39844 +
39845 +                       /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
39846 +                       SkGmPhyWrite(pAC, IoC, Port, 24, 0xa204);
39847 +                       SkGmPhyWrite(pAC, IoC, Port, 23, 0x2002);
39848 +
39849 +                       /* set page register to 0 */
39850 +                       SkGmPhyWrite(pAC, IoC, Port, 22, 0);
39851 +               }
39852 +       }
39853 +       else {
39854 +               /* no effect on Yukon-XL */
39855 +               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_LED_CTRL, LedCtrl);
39856 +
39857 +#ifndef SK_SLIM
39858 +               if ((BlinkCtrl & SK_LED_LINK100_ON) != 0) {
39859 +                       /* only in forced 100 Mbps mode */
39860 +                       if (!AutoNeg && pPrt->PLinkSpeed == SK_LSPEED_100MBPS) {
39861 +                               /* turn on 100 Mbps LED (LED_LINK100) */
39862 +                               LedOver |= PHY_M_LED_MO_100(MO_LED_ON);
39863 +                       }
39864 +               }
39865 +#endif /* !SK_SLIM */
39866
39867 -                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_LED_OVER,
39868 -                               PHY_M_LED_MO_100(MO_LED_ON));
39869 +               if (LedOver != 0) {
39870 +                       /* set Manual LED Override */
39871 +                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_LED_OVER, LedOver);
39872                 }
39873         }
39874
39875  #ifdef SK_DIAG
39876 -       c_print("Set PHY Ctrl=0x%04X\n", PhyCtrl);
39877 -       c_print("Set 1000 B-T=0x%04X\n", C1000BaseT);
39878 -       c_print("Set Auto-Neg=0x%04X\n", AutoNegAdv);
39879 -       c_print("Set Ext Ctrl=0x%04X\n", ExtPhyCtrl);
39880 +       c_print("Set PHY Ctrl = 0x%04X\n", PhyCtrl);
39881 +       c_print("Set 1000 B-T = 0x%04X\n", C1000BaseT);
39882 +       c_print("Set Auto-Neg = 0x%04X\n", AutoNegAdv);
39883 +       c_print("Set Ext Ctrl = 0x%04X\n", ExtPhyCtrl);
39884  #endif /* SK_DIAG */
39885
39886 -#if defined(SK_DIAG) || defined(DEBUG)
39887 +#if (defined(SK_DIAG) || (defined(DEBUG) && !defined(SK_SLIM)))
39888         /* Read PHY Control */
39889         SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &PhyCtrl);
39890         SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39891 -               ("PHY Ctrl Reg.=0x%04X\n", PhyCtrl));
39892 -
39893 -       /* Read 1000Base-T Control Register */
39894 -       SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_CTRL, &C1000BaseT);
39895 -       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39896 -               ("1000B-T Ctrl =0x%04X\n", C1000BaseT));
39897 -
39898 +               ("PHY Ctrl Reg. = 0x%04X\n", PhyCtrl));
39899 +
39900         /* Read AutoNeg Advertisement Register */
39901         SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_ADV, &AutoNegAdv);
39902         SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39903 -               ("Auto-Neg.Adv.=0x%04X\n", AutoNegAdv));
39904 -
39905 -       /* Read Ext. PHY Specific Control */
39906 -       SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl);
39907 -       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39908 -               ("Ext. PHY Ctrl=0x%04X\n", ExtPhyCtrl));
39909 -
39910 +               ("Auto-Neg.Adv. = 0x%04X\n", AutoNegAdv));
39911 +
39912 +       if (ChipId != CHIP_ID_YUKON_FE) {
39913 +               /* Read 1000Base-T Control Register */
39914 +               SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_CTRL, &C1000BaseT);
39915 +               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39916 +                       ("1000B-T Ctrl  = 0x%04X\n", C1000BaseT));
39917 +
39918 +               /* Read Ext. PHY Specific Control */
39919 +               SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl);
39920 +               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39921 +                       ("Ext. PHY Ctrl = 0x%04X\n", ExtPhyCtrl));
39922 +       }
39923 +
39924         /* Read PHY Status */
39925         SkGmPhyRead(pAC, IoC, Port, PHY_MARV_STAT, &PhyStat);
39926         SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39927 -               ("PHY Stat Reg.=0x%04X\n", PhyStat));
39928 +               ("PHY Stat Reg. = 0x%04X\n", PhyStat));
39929 +
39930         SkGmPhyRead(pAC, IoC, Port, PHY_MARV_STAT, &PhyStat1);
39931         SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39932 -               ("PHY Stat Reg.=0x%04X\n", PhyStat1));
39933 -
39934 +               ("PHY Stat Reg. = 0x%04X\n", PhyStat1));
39935 +
39936         /* Read PHY Specific Status */
39937         SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &PhySpecStat);
39938         SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39939 -               ("PHY Spec Stat=0x%04X\n", PhySpecStat));
39940 -#endif /* SK_DIAG || DEBUG */
39941 +               ("PHY Spec Stat = 0x%04X\n", PhySpecStat));
39942 +#endif /* SK_DIAG || (DEBUG && !SK_SLIM) */
39943
39944  #ifdef SK_DIAG
39945 -       c_print("PHY Ctrl Reg=0x%04X\n", PhyCtrl);
39946 -       c_print("PHY 1000 Reg=0x%04X\n", C1000BaseT);
39947 -       c_print("PHY AnAd Reg=0x%04X\n", AutoNegAdv);
39948 -       c_print("Ext Ctrl Reg=0x%04X\n", ExtPhyCtrl);
39949 -       c_print("PHY Stat Reg=0x%04X\n", PhyStat);
39950 -       c_print("PHY Stat Reg=0x%04X\n", PhyStat1);
39951 -       c_print("PHY Spec Reg=0x%04X\n", PhySpecStat);
39952 +       c_print("PHY Ctrl Reg = 0x%04X\n", PhyCtrl);
39953 +       c_print("PHY 1000 Reg = 0x%04X\n", C1000BaseT);
39954 +       c_print("PHY AnAd Reg = 0x%04X\n", AutoNegAdv);
39955 +       c_print("Ext Ctrl Reg = 0x%04X\n", ExtPhyCtrl);
39956 +       c_print("PHY Stat Reg = 0x%04X\n", PhyStat);
39957 +       c_print("PHY Stat Reg = 0x%04X\n", PhyStat1);
39958 +       c_print("PHY Spec Reg = 0x%04X\n", PhySpecStat);
39959  #endif /* SK_DIAG */
39960
39961 -#endif /* VCPU */
39962 +       /* enable PHY interrupts */
39963 +       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, (SK_U16)PHY_M_DEF_MSK);
39964 +#endif /* !VCPU */
39965
39966  }      /* SkGmInitPhyMarv */
39967  #endif /* YUKON */
39968 @@ -2419,9 +3349,9 @@
39969  #ifdef OTHER_PHY
39970  /******************************************************************************
39971   *
39972 - *     SkXmInitPhyLone() - Initialize the Level One Phy registers
39973 + *     SkXmInitPhyLone() - Initialize the Level One PHY registers
39974   *
39975 - * Description:        initializes all the Level One Phy registers
39976 + * Description:        initializes all the Level One PHY registers
39977   *
39978   * Note:
39979   *
39980 @@ -2429,10 +3359,10 @@
39981   *     nothing
39982   */
39983  static void SkXmInitPhyLone(
39984 -SK_AC  *pAC,           /* adapter context */
39985 -SK_IOC IoC,            /* IO context */
39986 +SK_AC  *pAC,           /* Adapter Context */
39987 +SK_IOC IoC,            /* I/O Context */
39988  int            Port,           /* Port Index (MAC_1 + n) */
39989 -SK_BOOL        DoLoop)         /* Should a Phy LoopBack be set-up? */
39990 +SK_BOOL        DoLoop)         /* Should a PHY LoopBack be set-up? */
39991  {
39992         SK_GEPORT       *pPrt;
39993         SK_U16          Ctrl1;
39994 @@ -2448,11 +3378,12 @@
39995         /* manually Master/Slave ? */
39996         if (pPrt->PMSMode != SK_MS_MODE_AUTO) {
39997                 Ctrl2 |= PHY_L_1000C_MSE;
39998 -
39999 +
40000                 if (pPrt->PMSMode == SK_MS_MODE_MASTER) {
40001                         Ctrl2 |= PHY_L_1000C_MSC;
40002                 }
40003         }
40004 +
40005         /* Auto-negotiation ? */
40006         if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
40007                 /*
40008 @@ -2461,7 +3392,7 @@
40009                  */
40010                 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40011                         ("InitPhyLone: no auto-negotiation Port %d\n", Port));
40012 -               /* Set DuplexMode in Config register */
40013 +               /* set DuplexMode in Config register */
40014                 if (pPrt->PLinkMode == SK_LMODE_FULL) {
40015                         Ctrl1 |= PHY_CT_DUP_MD;
40016                 }
40017 @@ -2470,7 +3401,6 @@
40018                 if (pPrt->PMSMode == SK_MS_MODE_AUTO) {
40019                         Ctrl2 |= PHY_L_1000C_MSE;       /* set it to Slave */
40020                 }
40021 -
40022                 /*
40023                  * Do NOT enable Auto-negotiation here. This would hold
40024                  * the link down because no IDLES are transmitted
40025 @@ -2479,9 +3409,9 @@
40026         else {
40027                 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40028                         ("InitPhyLone: with auto-negotiation Port %d\n", Port));
40029 -               /* Set Auto-negotiation advertisement */
40030 +               /* set Auto-negotiation advertisement */
40031
40032 -               /* Set Full/half duplex capabilities */
40033 +               /* set Full/half duplex capabilities */
40034                 switch (pPrt->PLinkMode) {
40035                 case SK_LMODE_AUTOHALF:
40036                         Ctrl2 |= PHY_L_1000C_AHD;
40037 @@ -2497,7 +3427,7 @@
40038                                 SKERR_HWI_E015MSG);
40039                 }
40040
40041 -               /* Set Flow-control capabilities */
40042 +               /* set Flow-control capabilities */
40043                 switch (pPrt->PFlowCtrlMode) {
40044                 case SK_FLOW_MODE_NONE:
40045                         Ctrl3 |= PHY_L_P_NO_PAUSE;
40046 @@ -2519,34 +3449,34 @@
40047                 /* Restart Auto-negotiation */
40048                 Ctrl1 = PHY_CT_ANE | PHY_CT_RE_CFG;
40049         }
40050 -
40051 +
40052         /* Write 1000Base-T Control Register */
40053         SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_1000T_CTRL, Ctrl2);
40054         SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40055 -               ("1000B-T Ctrl Reg=0x%04X\n", Ctrl2));
40056 -
40057 +               ("1000B-T Ctrl Reg = 0x%04X\n", Ctrl2));
40058 +
40059         /* Write AutoNeg Advertisement Register */
40060         SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_AUNE_ADV, Ctrl3);
40061         SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40062 -               ("Auto-Neg.Adv.Reg=0x%04X\n", Ctrl3));
40063 +               ("Auto-Neg.Adv.Reg = 0x%04X\n", Ctrl3));
40064
40065         if (DoLoop) {
40066 -               /* Set the Phy Loopback bit, too */
40067 +               /* set the PHY Loopback bit, too */
40068                 Ctrl1 |= PHY_CT_LOOP;
40069         }
40070
40071 -       /* Write to the Phy control register */
40072 +       /* Write to the PHY control register */
40073         SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_CTRL, Ctrl1);
40074         SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40075 -               ("PHY Control Reg=0x%04X\n", Ctrl1));
40076 +               ("PHY Control Reg = 0x%04X\n", Ctrl1));
40077  }      /* SkXmInitPhyLone */
40078
40079
40080  /******************************************************************************
40081   *
40082 - *     SkXmInitPhyNat() - Initialize the National Phy registers
40083 + *     SkXmInitPhyNat() - Initialize the National PHY registers
40084   *
40085 - * Description:        initializes all the National Phy registers
40086 + * Description:        initializes all the National PHY registers
40087   *
40088   * Note:
40089   *
40090 @@ -2554,10 +3484,10 @@
40091   *     nothing
40092   */
40093  static void SkXmInitPhyNat(
40094 -SK_AC  *pAC,           /* adapter context */
40095 -SK_IOC IoC,            /* IO context */
40096 +SK_AC  *pAC,           /* Adapter Context */
40097 +SK_IOC IoC,            /* I/O Context */
40098  int            Port,           /* Port Index (MAC_1 + n) */
40099 -SK_BOOL        DoLoop)         /* Should a Phy LoopBack be set-up? */
40100 +SK_BOOL        DoLoop)         /* Should a PHY LoopBack be set-up? */
40101  {
40102  /* todo: National */
40103  }      /* SkXmInitPhyNat */
40104 @@ -2576,10 +3506,10 @@
40105   *     nothing
40106   */
40107  void SkMacInitPhy(
40108 -SK_AC  *pAC,           /* adapter context */
40109 -SK_IOC IoC,            /* IO context */
40110 +SK_AC  *pAC,           /* Adapter Context */
40111 +SK_IOC IoC,            /* I/O Context */
40112  int            Port,           /* Port Index (MAC_1 + n) */
40113 -SK_BOOL        DoLoop)         /* Should a Phy LoopBack be set-up? */
40114 +SK_BOOL        DoLoop)         /* Should a PHY LoopBack be set-up? */
40115  {
40116         SK_GEPORT       *pPrt;
40117
40118 @@ -2587,7 +3517,7 @@
40119
40120  #ifdef GENESIS
40121         if (pAC->GIni.GIGenesis) {
40122 -
40123 +
40124                 switch (pPrt->PhyType) {
40125                 case SK_PHY_XMAC:
40126                         SkXmInitPhyXmac(pAC, IoC, Port, DoLoop);
40127 @@ -2606,10 +3536,10 @@
40128                 }
40129         }
40130  #endif /* GENESIS */
40131 -
40132 +
40133  #ifdef YUKON
40134         if (pAC->GIni.GIYukon) {
40135 -
40136 +
40137                 SkGmInitPhyMarv(pAC, IoC, Port, DoLoop);
40138         }
40139  #endif /* YUKON */
40140 @@ -2627,17 +3557,17 @@
40141   *
40142   * Returns:
40143   *     SK_AND_OK       o.k.
40144 - *     SK_AND_DUP_CAP  Duplex capability error happened
40145 - *     SK_AND_OTHER    Other error happened
40146 + *     SK_AND_DUP_CAP  Duplex capability error happened
40147 + *     SK_AND_OTHER    Other error happened
40148   */
40149  static int SkXmAutoNegDoneXmac(
40150 -SK_AC  *pAC,           /* adapter context */
40151 -SK_IOC IoC,            /* IO context */
40152 +SK_AC  *pAC,           /* Adapter Context */
40153 +SK_IOC IoC,            /* I/O Context */
40154  int            Port)           /* Port Index (MAC_1 + n) */
40155  {
40156         SK_GEPORT       *pPrt;
40157         SK_U16          ResAb;          /* Resolved Ability */
40158 -       SK_U16          LPAb;           /* Link Partner Ability */
40159 +       SK_U16          LinkPartAb;     /* Link Partner Ability */
40160
40161         SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40162                 ("AutoNegDoneXmac, Port %d\n", Port));
40163 @@ -2645,15 +3575,15 @@
40164         pPrt = &pAC->GIni.GP[Port];
40165
40166         /* Get PHY parameters */
40167 -       SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_AUNE_LP, &LPAb);
40168 +       SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_AUNE_LP, &LinkPartAb);
40169         SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_RES_ABI, &ResAb);
40170
40171 -       if ((LPAb & PHY_X_AN_RFB) != 0) {
40172 +       if ((LinkPartAb & PHY_X_AN_RFB) != 0) {
40173                 /* At least one of the remote fault bit is set */
40174 -               /* Error */
40175 -               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40176 +               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
40177                         ("AutoNegFail: Remote fault bit set Port %d\n", Port));
40178                 pPrt->PAutoNegFail = SK_TRUE;
40179 +
40180                 return(SK_AND_OTHER);
40181         }
40182
40183 @@ -2666,9 +3596,10 @@
40184         }
40185         else {
40186                 /* Error */
40187 -               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40188 +               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
40189                         ("AutoNegFail: Duplex mode mismatch Port %d\n", Port));
40190                 pPrt->PAutoNegFail = SK_TRUE;
40191 +
40192                 return(SK_AND_DUP_CAP);
40193         }
40194
40195 @@ -2676,25 +3607,26 @@
40196         /* We are NOT using chapter 4.23 of the Xaqti manual */
40197         /* We are using IEEE 802.3z/D5.0 Table 37-4 */
40198         if ((pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYMMETRIC ||
40199 -            pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM) &&
40200 -           (LPAb & PHY_X_P_SYM_MD) != 0) {
40201 +                pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM) &&
40202 +               (LinkPartAb & PHY_X_P_SYM_MD) != 0) {
40203                 /* Symmetric PAUSE */
40204                 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC;
40205         }
40206         else if (pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM &&
40207 -                  (LPAb & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD) {
40208 -               /* Enable PAUSE receive, disable PAUSE transmit */
40209 +                        (LinkPartAb & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD) {
40210 +               /* enable PAUSE receive, disable PAUSE transmit */
40211                 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND;
40212         }
40213         else if (pPrt->PFlowCtrlMode == SK_FLOW_MODE_LOC_SEND &&
40214 -                  (LPAb & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD) {
40215 -               /* Disable PAUSE receive, enable PAUSE transmit */
40216 +                        (LinkPartAb & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD) {
40217 +               /* disable PAUSE receive, enable PAUSE transmit */
40218                 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND;
40219         }
40220         else {
40221                 /* PAUSE mismatch -> no PAUSE */
40222                 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
40223         }
40224 +
40225         pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_1000MBPS;
40226
40227         return(SK_AND_OK);
40228 @@ -2710,41 +3642,39 @@
40229   *
40230   * Returns:
40231   *     SK_AND_OK       o.k.
40232 - *     SK_AND_DUP_CAP  Duplex capability error happened
40233 - *     SK_AND_OTHER    Other error happened
40234 + *     SK_AND_DUP_CAP  Duplex capability error happened
40235 + *     SK_AND_OTHER    Other error happened
40236   */
40237  static int SkXmAutoNegDoneBcom(
40238 -SK_AC  *pAC,           /* adapter context */
40239 -SK_IOC IoC,            /* IO context */
40240 +SK_AC  *pAC,           /* Adapter Context */
40241 +SK_IOC IoC,            /* I/O Context */
40242  int            Port)           /* Port Index (MAC_1 + n) */
40243  {
40244         SK_GEPORT       *pPrt;
40245 -       SK_U16          LPAb;           /* Link Partner Ability */
40246 -       SK_U16          AuxStat;        /* Auxiliary Status */
40247 -
40248  #ifdef TEST_ONLY
40249 -01-Sep-2000 RA;:;:
40250         SK_U16          ResAb;          /* Resolved Ability */
40251 -#endif /* 0 */
40252 +#endif
40253 +       SK_U16          LinkPartAb;     /* Link Partner Ability */
40254 +       SK_U16          AuxStat;        /* Auxiliary Status */
40255
40256         SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40257                 ("AutoNegDoneBcom, Port %d\n", Port));
40258         pPrt = &pAC->GIni.GP[Port];
40259
40260         /* Get PHY parameters */
40261 -       SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &LPAb);
40262 +       SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &LinkPartAb);
40263  #ifdef TEST_ONLY
40264 -01-Sep-2000 RA;:;:
40265         SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &ResAb);
40266 -#endif /* 0 */
40267 -
40268 +#endif
40269 +
40270         SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_STAT, &AuxStat);
40271
40272 -       if ((LPAb & PHY_B_AN_RF) != 0) {
40273 +       if ((LinkPartAb & PHY_B_AN_RF) != 0) {
40274                 /* Remote fault bit is set: Error */
40275 -               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40276 +               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
40277                         ("AutoNegFail: Remote fault bit set Port %d\n", Port));
40278                 pPrt->PAutoNegFail = SK_TRUE;
40279 +
40280                 return(SK_AND_OTHER);
40281         }
40282
40283 @@ -2757,26 +3687,26 @@
40284         }
40285         else {
40286                 /* Error */
40287 -               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40288 +               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
40289                         ("AutoNegFail: Duplex mode mismatch Port %d\n", Port));
40290                 pPrt->PAutoNegFail = SK_TRUE;
40291 +
40292                 return(SK_AND_DUP_CAP);
40293         }
40294 -
40295 +
40296  #ifdef TEST_ONLY
40297 -01-Sep-2000 RA;:;:
40298         /* Check Master/Slave resolution */
40299         if ((ResAb & PHY_B_1000S_MSF) != 0) {
40300 -               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40301 +               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
40302                         ("Master/Slave Fault Port %d\n", Port));
40303                 pPrt->PAutoNegFail = SK_TRUE;
40304                 pPrt->PMSStatus = SK_MS_STAT_FAULT;
40305                 return(SK_AND_OTHER);
40306         }
40307 -
40308 +
40309         pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
40310                 SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE;
40311 -#endif /* 0 */
40312 +#endif
40313
40314         /* Check PAUSE mismatch ??? */
40315         /* We are using IEEE 802.3z/D5.0 Table 37-4 */
40316 @@ -2785,17 +3715,18 @@
40317                 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC;
40318         }
40319         else if ((AuxStat & PHY_B_AS_PAUSE_MSK) == PHY_B_AS_PRR) {
40320 -               /* Enable PAUSE receive, disable PAUSE transmit */
40321 +               /* enable PAUSE receive, disable PAUSE transmit */
40322                 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND;
40323         }
40324         else if ((AuxStat & PHY_B_AS_PAUSE_MSK) == PHY_B_AS_PRT) {
40325 -               /* Disable PAUSE receive, enable PAUSE transmit */
40326 +               /* disable PAUSE receive, enable PAUSE transmit */
40327                 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND;
40328         }
40329         else {
40330                 /* PAUSE mismatch -> no PAUSE */
40331                 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
40332         }
40333 +
40334         pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_1000MBPS;
40335
40336         return(SK_AND_OK);
40337 @@ -2813,99 +3744,182 @@
40338   *
40339   * Returns:
40340   *     SK_AND_OK       o.k.
40341 - *     SK_AND_DUP_CAP  Duplex capability error happened
40342 - *     SK_AND_OTHER    Other error happened
40343 + *     SK_AND_DUP_CAP  Duplex capability error happened
40344 + *     SK_AND_OTHER    Other error happened
40345   */
40346  static int SkGmAutoNegDoneMarv(
40347 -SK_AC  *pAC,           /* adapter context */
40348 -SK_IOC IoC,            /* IO context */
40349 +SK_AC  *pAC,           /* Adapter Context */
40350 +SK_IOC IoC,            /* I/O Context */
40351  int            Port)           /* Port Index (MAC_1 + n) */
40352  {
40353         SK_GEPORT       *pPrt;
40354 -       SK_U16          LPAb;           /* Link Partner Ability */
40355         SK_U16          ResAb;          /* Resolved Ability */
40356         SK_U16          AuxStat;        /* Auxiliary Status */
40357 +       SK_U8           PauseMode;      /* Pause Mode */
40358 +#ifndef SK_SLIM
40359 +       SK_U16          LinkPartAb;     /* Link Partner Ability */
40360 +#ifndef SK_DIAG
40361 +       SK_EVPARA       Para;
40362 +#endif /* !SK_DIAG */
40363 +#endif /* !SK_SLIM */
40364 +
40365 +       /* set Pause On */
40366 +       PauseMode = (SK_U8)GMC_PAUSE_ON;
40367
40368         SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40369                 ("AutoNegDoneMarv, Port %d\n", Port));
40370 +
40371         pPrt = &pAC->GIni.GP[Port];
40372
40373 +#ifndef SK_SLIM
40374         /* Get PHY parameters */
40375 -       SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_LP, &LPAb);
40376 +       SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_LP, &LinkPartAb);
40377 +
40378         SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40379 -               ("Link P.Abil.=0x%04X\n", LPAb));
40380 -
40381 -       if ((LPAb & PHY_M_AN_RF) != 0) {
40382 -               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40383 +               ("Link P.Abil. = 0x%04X\n", LinkPartAb));
40384 +
40385 +       if ((LinkPartAb & PHY_M_AN_RF) != 0) {
40386 +               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
40387                         ("AutoNegFail: Remote fault bit set Port %d\n", Port));
40388                 pPrt->PAutoNegFail = SK_TRUE;
40389 +
40390                 return(SK_AND_OTHER);
40391         }
40392
40393 -       SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_STAT, &ResAb);
40394 -
40395 -       /* Check Master/Slave resolution */
40396 -       if ((ResAb & PHY_B_1000S_MSF) != 0) {
40397 -               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40398 -                       ("Master/Slave Fault Port %d\n", Port));
40399 -               pPrt->PAutoNegFail = SK_TRUE;
40400 -               pPrt->PMSStatus = SK_MS_STAT_FAULT;
40401 -               return(SK_AND_OTHER);
40402 +       if (pAC->GIni.GICopperType) {
40403 +               /* Read PHY Auto-Negotiation Expansion */
40404 +               SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_EXP, &LinkPartAb);
40405 +
40406 +               if ((LinkPartAb & PHY_ANE_LP_CAP) == 0) {
40407 +
40408 +#ifndef SK_DIAG
40409 +                       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40410 +                               ("Link Partner not Auto-Neg. able, AN Exp.: 0x%04X\n",
40411 +                               LinkPartAb));
40412 +
40413 +#ifndef NDIS_MINIPORT_DRIVER
40414 +                       SK_ERR_LOG(pAC, SK_ERRCL_CONFIG, SKERR_HWI_E025, SKERR_HWI_E025MSG);
40415 +#endif
40416 +
40417 +                       Para.Para64 = Port;
40418 +                       SkEventQueue(pAC, SKGE_DRV, SK_DRV_LIPA_NOT_AN_ABLE, Para);
40419 +#else
40420 +                       c_print("Link Partner not Auto-Neg. able, AN Exp.: 0x%04X\n",
40421 +                               LinkPartAb);
40422 +#endif /* !SK_DIAG */
40423 +
40424 +                       if (HW_FEATURE(pAC, HWF_FORCE_AUTO_NEG) &&
40425 +                               pPrt->PLinkModeConf < SK_LMODE_AUTOHALF) {
40426 +                               /* set used link speed */
40427 +                               pPrt->PLinkSpeedUsed = pPrt->PLinkSpeed;
40428 +
40429 +                               /* Set Link Mode Status */
40430 +                               pPrt->PLinkModeStatus = (pPrt->PLinkModeConf == SK_LMODE_FULL) ?
40431 +                                       SK_LMODE_STAT_FULL : SK_LMODE_STAT_HALF;
40432 +
40433 +                               return(SK_AND_OK);
40434 +                       }
40435 +               }
40436         }
40437 -
40438 -       pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
40439 -               (SK_U8)SK_MS_STAT_MASTER : (SK_U8)SK_MS_STAT_SLAVE;
40440 -
40441 +#endif /* !SK_SLIM */
40442 +
40443 +       if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
40444 +
40445 +               SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_STAT, &ResAb);
40446 +
40447 +               /* Check Master/Slave resolution */
40448 +               if ((ResAb & PHY_B_1000S_MSF) != 0) {
40449 +                       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
40450 +                               ("Master/Slave Fault Port %d\n", Port));
40451 +                       pPrt->PAutoNegFail = SK_TRUE;
40452 +                       pPrt->PMSStatus = SK_MS_STAT_FAULT;
40453 +                       return(SK_AND_OTHER);
40454 +               }
40455 +
40456 +               pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
40457 +                       (SK_U8)SK_MS_STAT_MASTER : (SK_U8)SK_MS_STAT_SLAVE;
40458 +       }
40459 +
40460         /* Read PHY Specific Status */
40461         SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &AuxStat);
40462 -
40463 +
40464         /* Check Speed & Duplex resolved */
40465         if ((AuxStat & PHY_M_PS_SPDUP_RES) == 0) {
40466 -               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40467 +               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
40468                         ("AutoNegFail: Speed & Duplex not resolved, Port %d\n", Port));
40469                 pPrt->PAutoNegFail = SK_TRUE;
40470                 pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN;
40471 +
40472                 return(SK_AND_DUP_CAP);
40473         }
40474 -
40475 -       if ((AuxStat & PHY_M_PS_FULL_DUP) != 0) {
40476 -               pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_AUTOFULL;
40477 -       }
40478 -       else {
40479 -               pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_AUTOHALF;
40480 -       }
40481 -
40482 -       /* Check PAUSE mismatch ??? */
40483 -       /* We are using IEEE 802.3z/D5.0 Table 37-4 */
40484 -       if ((AuxStat & PHY_M_PS_PAUSE_MSK) == PHY_M_PS_PAUSE_MSK) {
40485 -               /* Symmetric PAUSE */
40486 -               pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC;
40487 -       }
40488 -       else if ((AuxStat & PHY_M_PS_PAUSE_MSK) == PHY_M_PS_RX_P_EN) {
40489 -               /* Enable PAUSE receive, disable PAUSE transmit */
40490 -               pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND;
40491 -       }
40492 -       else if ((AuxStat & PHY_M_PS_PAUSE_MSK) == PHY_M_PS_TX_P_EN) {
40493 -               /* Disable PAUSE receive, enable PAUSE transmit */
40494 -               pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND;
40495 +
40496 +       pPrt->PLinkModeStatus = (SK_U8)(((AuxStat & PHY_M_PS_FULL_DUP) != 0) ?
40497 +               SK_LMODE_STAT_AUTOFULL : SK_LMODE_STAT_AUTOHALF);
40498 +
40499 +       if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) {
40500 +               /* set used link speed */
40501 +               pPrt->PLinkSpeedUsed = (SK_U8)(((AuxStat & PHY_M_PS_SPEED_100) != 0) ?
40502 +                       SK_LSPEED_STAT_100MBPS : SK_LSPEED_STAT_10MBPS);
40503         }
40504         else {
40505 -               /* PAUSE mismatch -> no PAUSE */
40506 -               pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
40507 +               /* set used link speed */
40508 +               switch ((unsigned)(AuxStat & PHY_M_PS_SPEED_MSK)) {
40509 +               case (unsigned)PHY_M_PS_SPEED_1000:
40510 +                       pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_1000MBPS;
40511 +                       break;
40512 +               case PHY_M_PS_SPEED_100:
40513 +                       pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_100MBPS;
40514 +                       break;
40515 +               default:
40516 +                       pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_10MBPS;
40517 +               }
40518 +
40519 +               if (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL ||
40520 +                       pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) {
40521 +                       /* Tx & Rx Pause Enabled bits are at 9..8 */
40522 +                       AuxStat >>= 6;
40523 +
40524 +                       if (!pAC->GIni.GICopperType) {
40525 +                               /* always 1000 Mbps on fiber */
40526 +                               pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_1000MBPS;
40527 +                       }
40528 +               }
40529 +
40530 +               AuxStat &= PHY_M_PS_PAUSE_MSK;
40531 +               /* We are using IEEE 802.3z/D5.0 Table 37-4 */
40532 +               if (AuxStat == PHY_M_PS_PAUSE_MSK) {
40533 +                       /* Symmetric PAUSE */
40534 +                       pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC;
40535 +               }
40536 +               else if (AuxStat == PHY_M_PS_RX_P_EN) {
40537 +                       /* enable PAUSE receive, disable PAUSE transmit */
40538 +                       pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND;
40539 +               }
40540 +               else if (AuxStat == PHY_M_PS_TX_P_EN) {
40541 +                       /* disable PAUSE receive, enable PAUSE transmit */
40542 +                       pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND;
40543 +               }
40544 +               else {
40545 +                       /* PAUSE mismatch -> no PAUSE */
40546 +                       pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
40547 +               }
40548         }
40549 -
40550 -       /* set used link speed */
40551 -       switch ((unsigned)(AuxStat & PHY_M_PS_SPEED_MSK)) {
40552 -       case (unsigned)PHY_M_PS_SPEED_1000:
40553 -               pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_1000MBPS;
40554 -               break;
40555 -       case PHY_M_PS_SPEED_100:
40556 -               pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_100MBPS;
40557 -               break;
40558 -       default:
40559 -               pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_10MBPS;
40560 +
40561 +       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40562 +               ("LinkSpeedUsed = %d\n", pPrt->PLinkSpeedUsed));
40563 +
40564 +       if ((pPrt->PFlowCtrlStatus == SK_FLOW_STAT_NONE) ||
40565 +               /* disable Pause also for 10/100 Mbps in half duplex mode */
40566 +               ((pAC->GIni.GIChipId != CHIP_ID_YUKON_EC_U) &&
40567 +               (pPrt->PLinkSpeedUsed < (SK_U8)SK_LSPEED_STAT_1000MBPS) &&
40568 +                pPrt->PLinkModeStatus == (SK_U8)SK_LMODE_STAT_AUTOHALF)) {
40569 +
40570 +               /* set Pause Off */
40571 +               PauseMode = (SK_U8)GMC_PAUSE_OFF;
40572         }
40573
40574 +       SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), PauseMode);
40575 +
40576         return(SK_AND_OK);
40577  }      /* SkGmAutoNegDoneMarv */
40578  #endif /* YUKON */
40579 @@ -2921,17 +3935,17 @@
40580   *
40581   * Returns:
40582   *     SK_AND_OK       o.k.
40583 - *     SK_AND_DUP_CAP  Duplex capability error happened
40584 - *     SK_AND_OTHER    Other error happened
40585 + *     SK_AND_DUP_CAP  Duplex capability error happened
40586 + *     SK_AND_OTHER    Other error happened
40587   */
40588  static int SkXmAutoNegDoneLone(
40589 -SK_AC  *pAC,           /* adapter context */
40590 -SK_IOC IoC,            /* IO context */
40591 +SK_AC  *pAC,           /* Adapter Context */
40592 +SK_IOC IoC,            /* I/O Context */
40593  int            Port)           /* Port Index (MAC_1 + n) */
40594  {
40595         SK_GEPORT       *pPrt;
40596         SK_U16          ResAb;          /* Resolved Ability */
40597 -       SK_U16          LPAb;           /* Link Partner Ability */
40598 +       SK_U16          LinkPartAb;     /* Link Partner Ability */
40599         SK_U16          QuickStat;      /* Auxiliary Status */
40600
40601         SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40602 @@ -2939,16 +3953,16 @@
40603         pPrt = &pAC->GIni.GP[Port];
40604
40605         /* Get PHY parameters */
40606 -       SkXmPhyRead(pAC, IoC, Port, PHY_LONE_AUNE_LP, &LPAb);
40607 +       SkXmPhyRead(pAC, IoC, Port, PHY_LONE_AUNE_LP, &LinkPartAb);
40608         SkXmPhyRead(pAC, IoC, Port, PHY_LONE_1000T_STAT, &ResAb);
40609         SkXmPhyRead(pAC, IoC, Port, PHY_LONE_Q_STAT, &QuickStat);
40610
40611 -       if ((LPAb & PHY_L_AN_RF) != 0) {
40612 +       if ((LinkPartAb & PHY_L_AN_RF) != 0) {
40613                 /* Remote fault bit is set */
40614 -               /* Error */
40615 -               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40616 +               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
40617                         ("AutoNegFail: Remote fault bit set Port %d\n", Port));
40618                 pPrt->PAutoNegFail = SK_TRUE;
40619 +
40620                 return(SK_AND_OTHER);
40621         }
40622
40623 @@ -2959,28 +3973,25 @@
40624         else {
40625                 pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_AUTOHALF;
40626         }
40627 -
40628 +
40629         /* Check Master/Slave resolution */
40630         if ((ResAb & PHY_L_1000S_MSF) != 0) {
40631                 /* Error */
40632 -               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40633 +               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
40634                         ("Master/Slave Fault Port %d\n", Port));
40635                 pPrt->PAutoNegFail = SK_TRUE;
40636                 pPrt->PMSStatus = SK_MS_STAT_FAULT;
40637                 return(SK_AND_OTHER);
40638         }
40639 -       else if (ResAb & PHY_L_1000S_MSR) {
40640 -               pPrt->PMSStatus = SK_MS_STAT_MASTER;
40641 -       }
40642 -       else {
40643 -               pPrt->PMSStatus = SK_MS_STAT_SLAVE;
40644 -       }
40645 +
40646 +       pPrt->PMSStatus = ((ResAb & PHY_L_1000S_MSR) != 0) ?
40647 +               (SK_U8)SK_MS_STAT_MASTER : (SK_U8)SK_MS_STAT_SLAVE;
40648
40649         /* Check PAUSE mismatch */
40650         /* We are using IEEE 802.3z/D5.0 Table 37-4 */
40651         /* we must manually resolve the abilities here */
40652         pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
40653 -
40654 +
40655         switch (pPrt->PFlowCtrlMode) {
40656         case SK_FLOW_MODE_NONE:
40657                 /* default */
40658 @@ -2988,7 +3999,7 @@
40659         case SK_FLOW_MODE_LOC_SEND:
40660                 if ((QuickStat & (PHY_L_QS_PAUSE | PHY_L_QS_AS_PAUSE)) ==
40661                         (PHY_L_QS_PAUSE | PHY_L_QS_AS_PAUSE)) {
40662 -                       /* Disable PAUSE receive, enable PAUSE transmit */
40663 +                       /* disable PAUSE receive, enable PAUSE transmit */
40664                         pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND;
40665                 }
40666                 break;
40667 @@ -3001,7 +4012,7 @@
40668         case SK_FLOW_MODE_SYM_OR_REM:
40669                 if ((QuickStat & (PHY_L_QS_PAUSE | PHY_L_QS_AS_PAUSE)) ==
40670                         PHY_L_QS_AS_PAUSE) {
40671 -                       /* Enable PAUSE receive, disable PAUSE transmit */
40672 +                       /* enable PAUSE receive, disable PAUSE transmit */
40673                         pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND;
40674                 }
40675                 else if ((QuickStat & PHY_L_QS_PAUSE) != 0) {
40676 @@ -3013,103 +4024,238 @@
40677                 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E016,
40678                         SKERR_HWI_E016MSG);
40679         }
40680 -
40681 -       return(SK_AND_OK);
40682 -}      /* SkXmAutoNegDoneLone */
40683 +
40684 +       return(SK_AND_OK);
40685 +}      /* SkXmAutoNegDoneLone */
40686 +
40687 +
40688 +/******************************************************************************
40689 + *
40690 + *     SkXmAutoNegDoneNat() - Auto-negotiation handling
40691 + *
40692 + * Description:
40693 + *     This function handles the auto-negotiation if the Done bit is set.
40694 + *
40695 + * Returns:
40696 + *     SK_AND_OK       o.k.
40697 + *     SK_AND_DUP_CAP  Duplex capability error happened
40698 + *     SK_AND_OTHER    Other error happened
40699 + */
40700 +static int SkXmAutoNegDoneNat(
40701 +SK_AC  *pAC,           /* Adapter Context */
40702 +SK_IOC IoC,            /* I/O Context */
40703 +int            Port)           /* Port Index (MAC_1 + n) */
40704 +{
40705 +/* todo: National */
40706 +       return(SK_AND_OK);
40707 +}      /* SkXmAutoNegDoneNat */
40708 +#endif /* OTHER_PHY */
40709 +
40710 +
40711 +/******************************************************************************
40712 + *
40713 + *     SkMacAutoNegDone() - Auto-negotiation handling
40714 + *
40715 + * Description:        calls the auto-negotiation done routines dep. on board type
40716 + *
40717 + * Returns:
40718 + *     SK_AND_OK       o.k.
40719 + *     SK_AND_DUP_CAP  Duplex capability error happened
40720 + *     SK_AND_OTHER    Other error happened
40721 + */
40722 +int SkMacAutoNegDone(
40723 +SK_AC  *pAC,           /* Adapter Context */
40724 +SK_IOC IoC,            /* I/O Context */
40725 +int            Port)           /* Port Index (MAC_1 + n) */
40726 +{
40727 +       SK_GEPORT       *pPrt;
40728 +       int     Rtv;
40729 +
40730 +       Rtv = SK_AND_OK;
40731 +
40732 +       pPrt = &pAC->GIni.GP[Port];
40733 +
40734 +#ifdef GENESIS
40735 +       if (pAC->GIni.GIGenesis) {
40736 +
40737 +               switch (pPrt->PhyType) {
40738 +
40739 +               case SK_PHY_XMAC:
40740 +                       Rtv = SkXmAutoNegDoneXmac(pAC, IoC, Port);
40741 +                       break;
40742 +               case SK_PHY_BCOM:
40743 +                       Rtv = SkXmAutoNegDoneBcom(pAC, IoC, Port);
40744 +                       break;
40745 +#ifdef OTHER_PHY
40746 +               case SK_PHY_LONE:
40747 +                       Rtv = SkXmAutoNegDoneLone(pAC, IoC, Port);
40748 +                       break;
40749 +               case SK_PHY_NAT:
40750 +                       Rtv = SkXmAutoNegDoneNat(pAC, IoC, Port);
40751 +                       break;
40752 +#endif /* OTHER_PHY */
40753 +               default:
40754 +                       return(SK_AND_OTHER);
40755 +               }
40756 +       }
40757 +#endif /* GENESIS */
40758 +
40759 +#ifdef YUKON
40760 +       if (pAC->GIni.GIYukon) {
40761 +
40762 +               Rtv = SkGmAutoNegDoneMarv(pAC, IoC, Port);
40763 +       }
40764 +#endif /* YUKON */
40765 +
40766 +       if (Rtv != SK_AND_OK) {
40767 +               return(Rtv);
40768 +       }
40769 +
40770 +       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40771 +               ("AutoNeg done Port %d\n", Port));
40772 +
40773 +       /* We checked everything and may now enable the link */
40774 +       pPrt->PAutoNegFail = SK_FALSE;
40775 +
40776 +       SkMacRxTxEnable(pAC, IoC, Port);
40777 +
40778 +       return(SK_AND_OK);
40779 +}      /* SkMacAutoNegDone */
40780 +
40781 +
40782 +#ifndef SK_SLIM
40783 +#ifdef GENESIS
40784 +/******************************************************************************
40785 + *
40786 + *     SkXmSetRxTxEn() - Special Set Rx/Tx Enable and some features in XMAC
40787 + *
40788 + * Description:
40789 + *  sets MAC or PHY LoopBack and Duplex Mode in the MMU Command Reg.
40790 + *  enables Rx/Tx
40791 + *
40792 + * Returns: N/A
40793 + */
40794 +static void SkXmSetRxTxEn(
40795 +SK_AC  *pAC,           /* Adapter Context */
40796 +SK_IOC IoC,            /* I/O Context */
40797 +int            Port,           /* Port Index (MAC_1 + n) */
40798 +int            Para)           /* Parameter to set: MAC or PHY LoopBack, Duplex Mode */
40799 +{
40800 +       SK_U16  Word;
40801 +
40802 +       XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
40803 +
40804 +       switch (Para & (SK_MAC_LOOPB_ON | SK_MAC_LOOPB_OFF)) {
40805 +       case SK_MAC_LOOPB_ON:
40806 +               Word |= XM_MMU_MAC_LB;
40807 +               break;
40808 +       case SK_MAC_LOOPB_OFF:
40809 +               Word &= ~XM_MMU_MAC_LB;
40810 +               break;
40811 +       }
40812 +
40813 +       switch (Para & (SK_PHY_LOOPB_ON | SK_PHY_LOOPB_OFF)) {
40814 +       case SK_PHY_LOOPB_ON:
40815 +               Word |= XM_MMU_GMII_LOOP;
40816 +               break;
40817 +       case SK_PHY_LOOPB_OFF:
40818 +               Word &= ~XM_MMU_GMII_LOOP;
40819 +               break;
40820 +       }
40821 +
40822 +       switch (Para & (SK_PHY_FULLD_ON | SK_PHY_FULLD_OFF)) {
40823 +       case SK_PHY_FULLD_ON:
40824 +               Word |= XM_MMU_GMII_FD;
40825 +               break;
40826 +       case SK_PHY_FULLD_OFF:
40827 +               Word &= ~XM_MMU_GMII_FD;
40828 +               break;
40829 +       }
40830 +
40831 +       XM_OUT16(IoC, Port, XM_MMU_CMD, Word | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
40832 +
40833 +       /* dummy read to ensure writing */
40834 +       XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
40835 +
40836 +}      /* SkXmSetRxTxEn */
40837 +#endif /* GENESIS */
40838
40839
40840 +#ifdef YUKON
40841  /******************************************************************************
40842   *
40843 - *     SkXmAutoNegDoneNat() - Auto-negotiation handling
40844 + *     SkGmSetRxTxEn() - Special Set Rx/Tx Enable and some features in GMAC
40845   *
40846   * Description:
40847 - *     This function handles the auto-negotiation if the Done bit is set.
40848 + *  sets MAC LoopBack and Duplex Mode in the General Purpose Control Reg.
40849 + *  enables Rx/Tx
40850   *
40851 - * Returns:
40852 - *     SK_AND_OK       o.k.
40853 - *     SK_AND_DUP_CAP  Duplex capability error happened
40854 - *     SK_AND_OTHER    Other error happened
40855 + * Returns: N/A
40856   */
40857 -static int SkXmAutoNegDoneNat(
40858 -SK_AC  *pAC,           /* adapter context */
40859 -SK_IOC IoC,            /* IO context */
40860 -int            Port)           /* Port Index (MAC_1 + n) */
40861 +static void SkGmSetRxTxEn(
40862 +SK_AC  *pAC,           /* Adapter Context */
40863 +SK_IOC IoC,            /* I/O Context */
40864 +int            Port,           /* Port Index (MAC_1 + n) */
40865 +int            Para)           /* Parameter to set: MAC LoopBack, Duplex Mode */
40866  {
40867 -/* todo: National */
40868 -       return(SK_AND_OK);
40869 -}      /* SkXmAutoNegDoneNat */
40870 -#endif /* OTHER_PHY */
40871 +       SK_U16  Ctrl;
40872 +
40873 +       GM_IN16(IoC, Port, GM_GP_CTRL, &Ctrl);
40874 +
40875 +       switch (Para & (SK_MAC_LOOPB_ON | SK_MAC_LOOPB_OFF)) {
40876 +       case SK_MAC_LOOPB_ON:
40877 +               Ctrl |= GM_GPCR_LOOP_ENA;
40878 +               break;
40879 +       case SK_MAC_LOOPB_OFF:
40880 +               Ctrl &= ~GM_GPCR_LOOP_ENA;
40881 +               break;
40882 +       }
40883 +
40884 +       switch (Para & (SK_PHY_FULLD_ON | SK_PHY_FULLD_OFF)) {
40885 +       case SK_PHY_FULLD_ON:
40886 +               Ctrl |= GM_GPCR_DUP_FULL;
40887 +               break;
40888 +       case SK_PHY_FULLD_OFF:
40889 +               Ctrl &= ~GM_GPCR_DUP_FULL;
40890 +               break;
40891 +       }
40892 +
40893 +       GM_OUT16(IoC, Port, GM_GP_CTRL, Ctrl | GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
40894 +
40895 +}      /* SkGmSetRxTxEn */
40896 +#endif /* YUKON */
40897
40898
40899  /******************************************************************************
40900   *
40901 - *     SkMacAutoNegDone() - Auto-negotiation handling
40902 + *     SkMacSetRxTxEn() - Special Set Rx/Tx Enable and parameters
40903   *
40904 - * Description:        calls the auto-negotiation done routines dep. on board type
40905 + * Description:        calls the Special Set Rx/Tx Enable routines dep. on board type
40906   *
40907 - * Returns:
40908 - *     SK_AND_OK       o.k.
40909 - *     SK_AND_DUP_CAP  Duplex capability error happened
40910 - *     SK_AND_OTHER    Other error happened
40911 + * Returns: N/A
40912   */
40913 -int    SkMacAutoNegDone(
40914 -SK_AC  *pAC,           /* adapter context */
40915 -SK_IOC IoC,            /* IO context */
40916 -int            Port)           /* Port Index (MAC_1 + n) */
40917 +void SkMacSetRxTxEn(
40918 +SK_AC  *pAC,           /* Adapter Context */
40919 +SK_IOC IoC,            /* I/O Context */
40920 +int            Port,           /* Port Index (MAC_1 + n) */
40921 +int            Para)
40922  {
40923 -       SK_GEPORT       *pPrt;
40924 -       int     Rtv;
40925 -
40926 -       Rtv = SK_AND_OK;
40927 -
40928 -       pPrt = &pAC->GIni.GP[Port];
40929 -
40930  #ifdef GENESIS
40931         if (pAC->GIni.GIGenesis) {
40932 -
40933 -               switch (pPrt->PhyType) {
40934 -
40935 -               case SK_PHY_XMAC:
40936 -                       Rtv = SkXmAutoNegDoneXmac(pAC, IoC, Port);
40937 -                       break;
40938 -               case SK_PHY_BCOM:
40939 -                       Rtv = SkXmAutoNegDoneBcom(pAC, IoC, Port);
40940 -                       break;
40941 -#ifdef OTHER_PHY
40942 -               case SK_PHY_LONE:
40943 -                       Rtv = SkXmAutoNegDoneLone(pAC, IoC, Port);
40944 -                       break;
40945 -               case SK_PHY_NAT:
40946 -                       Rtv = SkXmAutoNegDoneNat(pAC, IoC, Port);
40947 -                       break;
40948 -#endif /* OTHER_PHY */
40949 -               default:
40950 -                       return(SK_AND_OTHER);
40951 -               }
40952 +
40953 +               SkXmSetRxTxEn(pAC, IoC, Port, Para);
40954         }
40955  #endif /* GENESIS */
40956 -
40957 +
40958  #ifdef YUKON
40959         if (pAC->GIni.GIYukon) {
40960 -
40961 -               Rtv = SkGmAutoNegDoneMarv(pAC, IoC, Port);
40962 +
40963 +               SkGmSetRxTxEn(pAC, IoC, Port, Para);
40964         }
40965  #endif /* YUKON */
40966 -
40967 -       if (Rtv != SK_AND_OK) {
40968 -               return(Rtv);
40969 -       }
40970 -
40971 -       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40972 -               ("AutoNeg done Port %d\n", Port));
40973 -
40974 -       /* We checked everything and may now enable the link */
40975 -       pPrt->PAutoNegFail = SK_FALSE;
40976
40977 -       SkMacRxTxEnable(pAC, IoC, Port);
40978 -
40979 -       return(SK_AND_OK);
40980 -}      /* SkMacAutoNegDone */
40981 +}      /* SkMacSetRxTxEn */
40982 +#endif /* !SK_SLIM */
40983
40984
40985  /******************************************************************************
40986 @@ -3123,8 +4269,8 @@
40987   *     != 0    Error happened
40988   */
40989  int SkMacRxTxEnable(
40990 -SK_AC  *pAC,           /* adapter context */
40991 -SK_IOC IoC,            /* IO context */
40992 +SK_AC  *pAC,           /* Adapter Context */
40993 +SK_IOC IoC,            /* I/O Context */
40994  int            Port)           /* Port Index (MAC_1 + n) */
40995  {
40996         SK_GEPORT       *pPrt;
40997 @@ -3142,9 +4288,9 @@
40998         }
40999
41000         if ((pPrt->PLinkMode == SK_LMODE_AUTOHALF ||
41001 -            pPrt->PLinkMode == SK_LMODE_AUTOFULL ||
41002 -            pPrt->PLinkMode == SK_LMODE_AUTOBOTH) &&
41003 -            pPrt->PAutoNegFail) {
41004 +                pPrt->PLinkMode == SK_LMODE_AUTOFULL ||
41005 +                pPrt->PLinkMode == SK_LMODE_AUTOBOTH) &&
41006 +                pPrt->PAutoNegFail) {
41007                 /* Auto-negotiation is not done or failed */
41008                 return(0);
41009         }
41010 @@ -3153,9 +4299,9 @@
41011         if (pAC->GIni.GIGenesis) {
41012                 /* set Duplex Mode and Pause Mode */
41013                 SkXmInitDupMd(pAC, IoC, Port);
41014 -
41015 +
41016                 SkXmInitPauseMd(pAC, IoC, Port);
41017 -
41018 +
41019                 /*
41020                  * Initialize the Interrupt Mask Register. Default IRQs are...
41021                  *      - Link Asynchronous Event
41022 @@ -3171,23 +4317,24 @@
41023                 /* add IRQ for Receive FIFO Overflow */
41024                 IntMask &= ~XM_IS_RXF_OV;
41025  #endif /* DEBUG */
41026 -
41027 +
41028                 if (pPrt->PhyType != SK_PHY_XMAC) {
41029                         /* disable GP0 interrupt bit */
41030                         IntMask |= XM_IS_INP_ASS;
41031                 }
41032 +
41033                 XM_OUT16(IoC, Port, XM_IMSK, IntMask);
41034 -
41035 +
41036                 /* get MMU Command Reg. */
41037                 XM_IN16(IoC, Port, XM_MMU_CMD, &Reg);
41038 -
41039 +
41040                 if (pPrt->PhyType != SK_PHY_XMAC &&
41041                         (pPrt->PLinkModeStatus == SK_LMODE_STAT_FULL ||
41042                          pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOFULL)) {
41043                         /* set to Full Duplex */
41044                         Reg |= XM_MMU_GMII_FD;
41045                 }
41046 -
41047 +
41048                 switch (pPrt->PhyType) {
41049                 case SK_PHY_BCOM:
41050                         /*
41051 @@ -3197,7 +4344,7 @@
41052                         SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &SWord);
41053                         SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUX_CTRL,
41054                                 (SK_U16)(SWord & ~PHY_B_AC_DIS_PM));
41055 -            SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_INT_MASK,
41056 +                       SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_INT_MASK,
41057                                 (SK_U16)PHY_B_DEF_MSK);
41058                         break;
41059  #ifdef OTHER_PHY
41060 @@ -3211,12 +4358,12 @@
41061                         break;
41062  #endif /* OTHER_PHY */
41063                 }
41064 -
41065 +
41066                 /* enable Rx/Tx */
41067                 XM_OUT16(IoC, Port, XM_MMU_CMD, Reg | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
41068         }
41069  #endif /* GENESIS */
41070 -
41071 +
41072  #ifdef YUKON
41073         if (pAC->GIni.GIYukon) {
41074                 /*
41075 @@ -3227,34 +4374,46 @@
41076                  */
41077                 IntMask = GMAC_DEF_MSK;
41078
41079 -#ifdef DEBUG
41080 +#if (defined(DEBUG) || defined(YUK2)) && (!defined(SK_SLIM))
41081                 /* add IRQ for Receive FIFO Overrun */
41082                 IntMask |= GM_IS_RX_FF_OR;
41083 -#endif /* DEBUG */
41084 -
41085 -               SK_OUT8(IoC, GMAC_IRQ_MSK, (SK_U8)IntMask);
41086 -
41087 +#endif
41088 +
41089 +               SK_OUT8(IoC, MR_ADDR(Port, GMAC_IRQ_MSK), (SK_U8)IntMask);
41090 +
41091                 /* get General Purpose Control */
41092                 GM_IN16(IoC, Port, GM_GP_CTRL, &Reg);
41093 -
41094 +
41095                 if (pPrt->PLinkModeStatus == SK_LMODE_STAT_FULL ||
41096                         pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOFULL) {
41097                         /* set to Full Duplex */
41098                         Reg |= GM_GPCR_DUP_FULL;
41099 +
41100 +#ifndef SK_SLIM
41101 +                       if (HW_FEATURE(pAC, HWF_FORCE_AUTO_NEG) &&
41102 +                               pPrt->PLinkModeConf < SK_LMODE_AUTOHALF) {
41103 +                               /* disable auto-update for speed, duplex and flow-control */
41104 +                               Reg |= GM_GPCR_AU_ALL_DIS;
41105 +                       }
41106 +#endif /* !SK_SLIM */
41107                 }
41108 -
41109 -               /* enable Rx/Tx */
41110 -        GM_OUT16(IoC, Port, GM_GP_CTRL, (SK_U16)(Reg | GM_GPCR_RX_ENA |
41111 -                       GM_GPCR_TX_ENA));
41112
41113 -#ifndef VCPU
41114 -               /* Enable all PHY interrupts */
41115 -        SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK,
41116 -                       (SK_U16)PHY_M_DEF_MSK);
41117 -#endif /* VCPU */
41118 +               /* WA for dev. #4.209 */
41119 +               if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U &&
41120 +                       pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A1) {
41121 +                       /* enable/disable Store & Forward mode for TX */
41122 +                       SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_CTRL_T),
41123 +                               pPrt->PLinkSpeedUsed != (SK_U8)SK_LSPEED_STAT_1000MBPS ?
41124 +                               TX_STFW_ENA : TX_STFW_DIS);
41125 +               }
41126 +
41127 +               /* enable Rx/Tx */
41128 +               GM_OUT16(IoC, Port, GM_GP_CTRL, Reg | GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
41129         }
41130  #endif /* YUKON */
41131 -
41132 +
41133 +       pAC->GIni.GP[Port].PState = SK_PRT_RUN;
41134 +
41135         return(0);
41136
41137  }      /* SkMacRxTxEnable */
41138 @@ -3270,33 +4429,33 @@
41139   */
41140  void SkMacRxTxDisable(
41141  SK_AC  *pAC,           /* Adapter Context */
41142 -SK_IOC IoC,            /* IO context */
41143 +SK_IOC IoC,            /* I/O Context */
41144  int            Port)           /* Port Index (MAC_1 + n) */
41145  {
41146         SK_U16  Word;
41147
41148  #ifdef GENESIS
41149         if (pAC->GIni.GIGenesis) {
41150 -
41151 +
41152                 XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
41153 -
41154 -               XM_OUT16(IoC, Port, XM_MMU_CMD, Word & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
41155 -
41156 +
41157 +               Word &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
41158 +
41159 +               XM_OUT16(IoC, Port, XM_MMU_CMD, Word);
41160 +
41161                 /* dummy read to ensure writing */
41162                 XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
41163         }
41164  #endif /* GENESIS */
41165 -
41166 +
41167  #ifdef YUKON
41168         if (pAC->GIni.GIYukon) {
41169 -
41170 +
41171                 GM_IN16(IoC, Port, GM_GP_CTRL, &Word);
41172
41173 -        GM_OUT16(IoC, Port, GM_GP_CTRL, (SK_U16)(Word & ~(GM_GPCR_RX_ENA |
41174 -                       GM_GPCR_TX_ENA)));
41175 +               Word &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
41176
41177 -               /* dummy read to ensure writing */
41178 -               GM_IN16(IoC, Port, GM_GP_CTRL, &Word);
41179 +               GM_OUT16(IoC, Port, GM_GP_CTRL, Word);
41180         }
41181  #endif /* YUKON */
41182
41183 @@ -3313,7 +4472,7 @@
41184   */
41185  void SkMacIrqDisable(
41186  SK_AC  *pAC,           /* Adapter Context */
41187 -SK_IOC IoC,            /* IO context */
41188 +SK_IOC IoC,            /* I/O Context */
41189  int            Port)           /* Port Index (MAC_1 + n) */
41190  {
41191         SK_GEPORT       *pPrt;
41192 @@ -3325,18 +4484,18 @@
41193
41194  #ifdef GENESIS
41195         if (pAC->GIni.GIGenesis) {
41196 -
41197 +
41198                 /* disable all XMAC IRQs */
41199 -               XM_OUT16(IoC, Port, XM_IMSK, 0xffff);
41200 -
41201 -               /* Disable all PHY interrupts */
41202 +               XM_OUT16(IoC, Port, XM_IMSK, 0xffff);
41203 +
41204 +               /* disable all PHY interrupts */
41205                 switch (pPrt->PhyType) {
41206                         case SK_PHY_BCOM:
41207                                 /* Make sure that PHY is initialized */
41208                                 if (pPrt->PState != SK_PRT_RESET) {
41209                                         /* NOT allowed if BCOM is in RESET state */
41210                                         /* Workaround BCOM Errata (#10523) all BCom */
41211 -                                       /* Disable Power Management if link is down */
41212 +                                       /* disable Power Management if link is down */
41213                                         SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &Word);
41214                                         SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUX_CTRL,
41215                                                 (SK_U16)(Word | PHY_B_AC_DIS_PM));
41216 @@ -3355,16 +4514,16 @@
41217                 }
41218         }
41219  #endif /* GENESIS */
41220 -
41221 +
41222  #ifdef YUKON
41223         if (pAC->GIni.GIYukon) {
41224                 /* disable all GMAC IRQs */
41225 -               SK_OUT8(IoC, GMAC_IRQ_MSK, 0);
41226 -
41227 +               SK_OUT8(IoC, MR_ADDR(Port, GMAC_IRQ_MSK), 0);
41228 +
41229  #ifndef VCPU
41230 -               /* Disable all PHY interrupts */
41231 +               /* disable all PHY interrupts */
41232                 SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, 0);
41233 -#endif /* VCPU */
41234 +#endif /* !VCPU */
41235         }
41236  #endif /* YUKON */
41237
41238 @@ -3376,29 +4535,72 @@
41239   *
41240   *     SkXmSendCont() - Enable / Disable Send Continuous Mode
41241   *
41242 - * Description:        enable / disable Send Continuous Mode on XMAC
41243 + * Description:        enable / disable Send Continuous Mode on XMAC resp.
41244 + *                                                             Packet Generation on GPHY
41245   *
41246   * Returns:
41247   *     nothing
41248   */
41249  void SkXmSendCont(
41250 -SK_AC  *pAC,   /* adapter context */
41251 -SK_IOC IoC,    /* IO context */
41252 +SK_AC  *pAC,   /* Adapter Context */
41253 +SK_IOC IoC,    /* I/O Context */
41254  int            Port,   /* Port Index (MAC_1 + n) */
41255  SK_BOOL        Enable) /* Enable / Disable */
41256  {
41257 +       SK_U16  Reg;
41258 +       SK_U16  Save;
41259         SK_U32  MdReg;
41260
41261 -       XM_IN32(IoC, Port, XM_MODE, &MdReg);
41262 +       if (pAC->GIni.GIGenesis) {
41263 +               XM_IN32(IoC, Port, XM_MODE, &MdReg);
41264
41265 -       if (Enable) {
41266 -               MdReg |= XM_MD_TX_CONT;
41267 +               if (Enable) {
41268 +                       MdReg |= XM_MD_TX_CONT;
41269 +               }
41270 +               else {
41271 +                       MdReg &= ~XM_MD_TX_CONT;
41272 +               }
41273 +               /* setup Mode Register */
41274 +               XM_OUT32(IoC, Port, XM_MODE, MdReg);
41275         }
41276         else {
41277 -               MdReg &= ~XM_MD_TX_CONT;
41278 +               if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) {
41279 +                       /* select page 18 */
41280 +                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_ADDR, 18);
41281 +
41282 +                       SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PAGE_DATA, &Reg);
41283 +
41284 +                       Reg &= ~0x003c;                 /* clear bits 5..2 */
41285 +
41286 +                       if (Enable) {
41287 +                               /* enable packet generation, 1518 byte length */
41288 +                               Reg |= (BIT_5S | BIT_3S);
41289 +                       }
41290 +
41291 +                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, Reg);
41292 +               }
41293 +               else if (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL) {
41294 +                       /* save page register */
41295 +                       SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_ADR, &Save);
41296 +
41297 +                       /* select page 6 to access Packet Generation register */
41298 +                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 6);
41299 +
41300 +                       SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Reg);
41301 +
41302 +                       Reg &= ~0x003f;                 /* clear bits 5..0 */
41303 +
41304 +                       if (Enable) {
41305 +                               /* enable packet generation, 1518 byte length */
41306 +                               Reg |= (BIT_3S | BIT_1S);
41307 +                       }
41308 +
41309 +                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Reg);
41310 +
41311 +                       /* restore page register */
41312 +                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, Save);
41313 +               }
41314         }
41315 -       /* setup Mode Register */
41316 -       XM_OUT32(IoC, Port, XM_MODE, MdReg);
41317
41318  }      /* SkXmSendCont */
41319
41320 @@ -3413,8 +4615,8 @@
41321   *     nothing
41322   */
41323  void SkMacTimeStamp(
41324 -SK_AC  *pAC,   /* adapter context */
41325 -SK_IOC IoC,    /* IO context */
41326 +SK_AC  *pAC,   /* Adapter Context */
41327 +SK_IOC IoC,    /* I/O Context */
41328  int            Port,   /* Port Index (MAC_1 + n) */
41329  SK_BOOL        Enable) /* Enable / Disable */
41330  {
41331 @@ -3459,8 +4661,8 @@
41332   *     is set true.
41333   */
41334  void SkXmAutoNegLipaXmac(
41335 -SK_AC  *pAC,           /* adapter context */
41336 -SK_IOC IoC,            /* IO context */
41337 +SK_AC  *pAC,           /* Adapter Context */
41338 +SK_IOC IoC,            /* I/O Context */
41339  int            Port,           /* Port Index (MAC_1 + n) */
41340  SK_U16 IStatus)        /* Interrupt Status word to analyse */
41341  {
41342 @@ -3472,8 +4674,9 @@
41343                 (IStatus & (XM_IS_LIPA_RC | XM_IS_RX_PAGE | XM_IS_AND)) != 0) {
41344
41345                 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
41346 -                       ("AutoNegLipa: AutoNeg detected on Port %d, IStatus=0x%04X\n",
41347 +                       ("AutoNegLipa: AutoNeg detected on Port %d, IStatus = 0x%04X\n",
41348                         Port, IStatus));
41349 +
41350                 pPrt->PLipaAutoNeg = SK_LIPA_AUTO;
41351         }
41352  }      /* SkXmAutoNegLipaXmac */
41353 @@ -3489,8 +4692,8 @@
41354   *     is set true.
41355   */
41356  void SkMacAutoNegLipaPhy(
41357 -SK_AC  *pAC,           /* adapter context */
41358 -SK_IOC IoC,            /* IO context */
41359 +SK_AC  *pAC,           /* Adapter Context */
41360 +SK_IOC IoC,            /* I/O Context */
41361  int            Port,           /* Port Index (MAC_1 + n) */
41362  SK_U16 PhyStat)        /* PHY Status word to analyse */
41363  {
41364 @@ -3502,8 +4705,9 @@
41365                 (PhyStat & PHY_ST_AN_OVER) != 0) {
41366
41367                 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
41368 -                       ("AutoNegLipa: AutoNeg detected on Port %d, PhyStat=0x%04X\n",
41369 +                       ("AutoNegLipa: AutoNeg detected on Port %d, PhyStat = 0x%04X\n",
41370                         Port, PhyStat));
41371 +
41372                 pPrt->PLipaAutoNeg = SK_LIPA_AUTO;
41373         }
41374  }      /* SkMacAutoNegLipaPhy */
41375 @@ -3518,7 +4722,7 @@
41376   *
41377   * Note:
41378   *     With an external PHY, some interrupt bits are not meaningfull any more:
41379 - *     - LinkAsyncEvent (bit #14)              XM_IS_LNK_AE
41380 + *     - LinkAsyncEvent (bit #14)              XM_IS_LNK_AE
41381   *     - LinkPartnerReqConfig (bit #10)        XM_IS_LIPA_RC
41382   *     - Page Received (bit #9)                XM_IS_RX_PAGE
41383   *     - NextPageLoadedForXmt (bit #8)         XM_IS_TX_PAGE
41384 @@ -3530,22 +4734,23 @@
41385   *     nothing
41386   */
41387  static void SkXmIrq(
41388 -SK_AC  *pAC,           /* adapter context */
41389 -SK_IOC IoC,            /* IO context */
41390 +SK_AC  *pAC,           /* Adapter Context */
41391 +SK_IOC IoC,            /* I/O Context */
41392  int            Port)           /* Port Index (MAC_1 + n) */
41393  {
41394         SK_GEPORT       *pPrt;
41395 -       SK_EVPARA       Para;
41396         SK_U16          IStatus;        /* Interrupt status read from the XMAC */
41397         SK_U16          IStatus2;
41398  #ifdef SK_SLIM
41399 -    SK_U64      OverflowStatus;
41400 -#endif
41401 +       SK_U64          OverflowStatus;
41402 +#else
41403 +       SK_EVPARA       Para;
41404 +#endif /* SK_SLIM */
41405
41406         pPrt = &pAC->GIni.GP[Port];
41407 -
41408 +
41409         XM_IN16(IoC, Port, XM_ISRC, &IStatus);
41410 -
41411 +
41412         /* LinkPartner Auto-negable? */
41413         if (pPrt->PhyType == SK_PHY_XMAC) {
41414                 SkXmAutoNegLipaXmac(pAC, IoC, Port, IStatus);
41415 @@ -3556,7 +4761,7 @@
41416                         XM_IS_RX_PAGE | XM_IS_TX_PAGE |
41417                         XM_IS_AND | XM_IS_INP_ASS);
41418         }
41419 -
41420 +
41421         SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
41422                 ("XmacIrq Port %d Isr 0x%04X\n", Port, IStatus));
41423
41424 @@ -3666,49 +4871,55 @@
41425   *     nothing
41426   */
41427  static void SkGmIrq(
41428 -SK_AC  *pAC,           /* adapter context */
41429 -SK_IOC IoC,            /* IO context */
41430 +SK_AC  *pAC,           /* Adapter Context */
41431 +SK_IOC IoC,            /* I/O Context */
41432  int            Port)           /* Port Index (MAC_1 + n) */
41433  {
41434         SK_GEPORT       *pPrt;
41435         SK_U8           IStatus;        /* Interrupt status */
41436  #ifdef SK_SLIM
41437 -    SK_U64      OverflowStatus;
41438 +       SK_U64          OverflowStatus;
41439  #else
41440         SK_EVPARA       Para;
41441 -#endif
41442 +#endif /* SK_SLIM */
41443
41444         pPrt = &pAC->GIni.GP[Port];
41445 -
41446 -       SK_IN8(IoC, GMAC_IRQ_SRC, &IStatus);
41447 -
41448 +
41449 +       SK_IN8(IoC, MR_ADDR(Port, GMAC_IRQ_SRC), &IStatus);
41450 +
41451  #ifdef XXX
41452         /* LinkPartner Auto-negable? */
41453         SkMacAutoNegLipaPhy(pAC, IoC, Port, IStatus);
41454  #endif /* XXX */
41455 -
41456 +
41457         SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
41458 -               ("GmacIrq Port %d Isr 0x%04X\n", Port, IStatus));
41459 +               ("GmacIrq Port %d Isr 0x%02X\n", Port, IStatus));
41460
41461         /* Combined Tx & Rx Counter Overflow SIRQ Event */
41462         if (IStatus & (GM_IS_RX_CO_OV | GM_IS_TX_CO_OV)) {
41463                 /* these IRQs will be cleared by reading GMACs register */
41464  #ifdef SK_SLIM
41465 -        SkGmOverflowStatus(pAC, IoC, Port, IStatus, &OverflowStatus);
41466 +               SkGmOverflowStatus(pAC, IoC, Port, (SK_U16)IStatus, &OverflowStatus);
41467  #else
41468                 Para.Para32[0] = (SK_U32)Port;
41469                 Para.Para32[1] = (SK_U32)IStatus;
41470                 SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_SIRQ_OVERFLOW, Para);
41471 -#endif
41472 +#endif /* SK_SLIM */
41473         }
41474
41475 +#ifndef SK_SLIM
41476         if (IStatus & GM_IS_RX_FF_OR) {
41477                 /* clear GMAC Rx FIFO Overrun IRQ */
41478                 SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_CLI_RX_FO);
41479 +
41480 +               Para.Para64 = Port;
41481 +               SkEventQueue(pAC, SKGE_DRV, SK_DRV_RX_OVERFLOW, Para);
41482 +
41483  #ifdef DEBUG
41484                 pPrt->PRxOverCnt++;
41485  #endif /* DEBUG */
41486         }
41487 +#endif /* !SK_SLIM */
41488
41489         if (IStatus & GM_IS_TX_FF_UR) {
41490                 /* clear GMAC Tx FIFO Underrun IRQ */
41491 @@ -3738,8 +4949,8 @@
41492   *     nothing
41493   */
41494  void SkMacIrq(
41495 -SK_AC  *pAC,           /* adapter context */
41496 -SK_IOC IoC,            /* IO context */
41497 +SK_AC  *pAC,           /* Adapter Context */
41498 +SK_IOC IoC,            /* I/O Context */
41499  int            Port)           /* Port Index (MAC_1 + n) */
41500  {
41501  #ifdef GENESIS
41502 @@ -3748,7 +4959,7 @@
41503                 SkXmIrq(pAC, IoC, Port);
41504         }
41505  #endif /* GENESIS */
41506 -
41507 +
41508  #ifdef YUKON
41509         if (pAC->GIni.GIYukon) {
41510                 /* IRQ from GMAC */
41511 @@ -3775,8 +4986,8 @@
41512   *     1:  something went wrong
41513   */
41514  int SkXmUpdateStats(
41515 -SK_AC  *pAC,           /* adapter context */
41516 -SK_IOC IoC,            /* IO context */
41517 +SK_AC  *pAC,           /* Adapter Context */
41518 +SK_IOC IoC,            /* I/O Context */
41519  unsigned int Port)     /* Port Index (MAC_1 + n) */
41520  {
41521         SK_GEPORT       *pPrt;
41522 @@ -3798,7 +5009,7 @@
41523         do {
41524
41525                 XM_IN16(IoC, Port, XM_STAT_CMD, &StatReg);
41526 -
41527 +
41528                 if (++WaitIndex > 10) {
41529
41530                         SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E021, SKERR_HWI_E021MSG);
41531 @@ -3806,7 +5017,7 @@
41532                         return(1);
41533                 }
41534         } while ((StatReg & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) != 0);
41535 -
41536 +
41537         return(0);
41538  }      /* SkXmUpdateStats */
41539
41540 @@ -3825,19 +5036,19 @@
41541   *     1:  something went wrong
41542   */
41543  int SkXmMacStatistic(
41544 -SK_AC  *pAC,                   /* adapter context */
41545 -SK_IOC IoC,                    /* IO context */
41546 +SK_AC  *pAC,                   /* Adapter Context */
41547 +SK_IOC IoC,                    /* I/O Context */
41548  unsigned int Port,             /* Port Index (MAC_1 + n) */
41549  SK_U16 StatAddr,               /* MIB counter base address */
41550 -SK_U32 SK_FAR *pVal)   /* ptr to return statistic value */
41551 +SK_U32 SK_FAR *pVal)   /* Pointer to return statistic value */
41552  {
41553         if ((StatAddr < XM_TXF_OK) || (StatAddr > XM_RXF_MAX_SZ)) {
41554 -
41555 +
41556                 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E022, SKERR_HWI_E022MSG);
41557 -
41558 +
41559                 return(1);
41560         }
41561 -
41562 +
41563         XM_IN32(IoC, Port, StatAddr, pVal);
41564
41565         return(0);
41566 @@ -3856,12 +5067,12 @@
41567   *     1:  something went wrong
41568   */
41569  int SkXmResetCounter(
41570 -SK_AC  *pAC,           /* adapter context */
41571 -SK_IOC IoC,            /* IO context */
41572 +SK_AC  *pAC,           /* Adapter Context */
41573 +SK_IOC IoC,            /* I/O Context */
41574  unsigned int Port)     /* Port Index (MAC_1 + n) */
41575  {
41576         XM_OUT16(IoC, Port, XM_STAT_CMD, XM_SC_CLR_RXC | XM_SC_CLR_TXC);
41577 -       /* Clear two times according to Errata #3 */
41578 +       /* Clear two times according to XMAC Errata #3 */
41579         XM_OUT16(IoC, Port, XM_STAT_CMD, XM_SC_CLR_RXC | XM_SC_CLR_TXC);
41580
41581         return(0);
41582 @@ -3888,11 +5099,11 @@
41583   *     1:  something went wrong
41584   */
41585  int SkXmOverflowStatus(
41586 -SK_AC  *pAC,                           /* adapter context */
41587 -SK_IOC IoC,                            /* IO context */
41588 +SK_AC  *pAC,                           /* Adapter Context */
41589 +SK_IOC IoC,                            /* I/O Context */
41590  unsigned int Port,                     /* Port Index (MAC_1 + n) */
41591 -SK_U16 IStatus,                        /* Interupt Status from MAC */
41592 -SK_U64 SK_FAR *pStatus)        /* ptr for return overflow status value */
41593 +SK_U16 IStatus,                        /* Interrupt Status from MAC */
41594 +SK_U64 SK_FAR *pStatus)        /* Pointer for return overflow status value */
41595  {
41596         SK_U64  Status; /* Overflow status */
41597         SK_U32  RegVal;
41598 @@ -3904,7 +5115,7 @@
41599                 XM_IN32(IoC, Port, XM_RX_CNT_EV, &RegVal);
41600                 Status |= (SK_U64)RegVal << 32;
41601         }
41602 -
41603 +
41604         if ((IStatus & XM_IS_TXC_OV) != 0) {
41605
41606                 XM_IN32(IoC, Port, XM_TX_CNT_EV, &RegVal);
41607 @@ -3931,8 +5142,8 @@
41608   *     1:  something went wrong
41609   */
41610  int SkGmUpdateStats(
41611 -SK_AC  *pAC,           /* adapter context */
41612 -SK_IOC IoC,            /* IO context */
41613 +SK_AC  *pAC,           /* Adapter Context */
41614 +SK_IOC IoC,            /* I/O Context */
41615  unsigned int Port)     /* Port Index (MAC_1 + n) */
41616  {
41617         return(0);
41618 @@ -3953,24 +5164,27 @@
41619   *     1:  something went wrong
41620   */
41621  int SkGmMacStatistic(
41622 -SK_AC  *pAC,                   /* adapter context */
41623 -SK_IOC IoC,                    /* IO context */
41624 +SK_AC  *pAC,                   /* Adapter Context */
41625 +SK_IOC IoC,                    /* I/O Context */
41626  unsigned int Port,             /* Port Index (MAC_1 + n) */
41627  SK_U16 StatAddr,               /* MIB counter base address */
41628 -SK_U32 SK_FAR *pVal)   /* ptr to return statistic value */
41629 +SK_U32 SK_FAR *pVal)   /* Pointer to return statistic value */
41630  {
41631
41632         if ((StatAddr < GM_RXF_UC_OK) || (StatAddr > GM_TXE_FIFO_UR)) {
41633 -
41634 +
41635                 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E022, SKERR_HWI_E022MSG);
41636 -
41637 -               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
41638 +
41639 +               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
41640                         ("SkGmMacStat: wrong MIB counter 0x%04X\n", StatAddr));
41641                 return(1);
41642         }
41643 -
41644 +
41645         GM_IN32(IoC, Port, StatAddr, pVal);
41646
41647 +       /* dummy read after GM_IN32() */
41648 +       SK_IN16(IoC, B0_RAP, &StatAddr);
41649 +
41650         return(0);
41651  }      /* SkGmMacStatistic */
41652
41653 @@ -3987,11 +5201,11 @@
41654   *     1:  something went wrong
41655   */
41656  int SkGmResetCounter(
41657 -SK_AC  *pAC,           /* adapter context */
41658 -SK_IOC IoC,            /* IO context */
41659 +SK_AC  *pAC,           /* Adapter Context */
41660 +SK_IOC IoC,            /* I/O Context */
41661  unsigned int Port)     /* Port Index (MAC_1 + n) */
41662  {
41663 -       SK_U16  Reg;    /* Phy Address Register */
41664 +       SK_U16  Reg;    /* PHY Address Register */
41665         SK_U16  Word;
41666         int             i;
41667
41668 @@ -3999,16 +5213,16 @@
41669
41670         /* set MIB Clear Counter Mode */
41671         GM_OUT16(IoC, Port, GM_PHY_ADDR, Reg | GM_PAR_MIB_CLR);
41672 -
41673 +
41674         /* read all MIB Counters with Clear Mode set */
41675         for (i = 0; i < GM_MIB_CNT_SIZE; i++) {
41676                 /* the reset is performed only when the lower 16 bits are read */
41677                 GM_IN16(IoC, Port, GM_MIB_CNT_BASE + 8*i, &Word);
41678         }
41679 -
41680 +
41681         /* clear MIB Clear Counter Mode */
41682         GM_OUT16(IoC, Port, GM_PHY_ADDR, Reg);
41683 -
41684 +
41685         return(0);
41686  }      /* SkGmResetCounter */
41687
41688 @@ -4022,48 +5236,62 @@
41689   *     resulting counter overflow status is written to <pStatus>, whereas the
41690   *     the following bit coding is used:
41691   *     63:56 - unused
41692 - *     55:48 - TxRx interrupt register bit7:0
41693 - *     32:47 - Rx interrupt register
41694 + *     55:48 - TxRx interrupt register bit 7:0
41695 + *     47:32 - Rx interrupt register
41696   *     31:24 - unused
41697 - *     23:16 - TxRx interrupt register bit15:8
41698 - *     15:0  - Tx interrupt register
41699 + *     23:16 - TxRx interrupt register bit 15:8
41700 + *     15: 0 - Tx interrupt register
41701   *
41702   * Returns:
41703   *     0:  success
41704   *     1:  something went wrong
41705   */
41706  int SkGmOverflowStatus(
41707 -SK_AC  *pAC,                           /* adapter context */
41708 -SK_IOC IoC,                            /* IO context */
41709 +SK_AC  *pAC,                           /* Adapter Context */
41710 +SK_IOC IoC,                            /* I/O Context */
41711  unsigned int Port,                     /* Port Index (MAC_1 + n) */
41712 -SK_U16 IStatus,                        /* Interupt Status from MAC */
41713 -SK_U64 SK_FAR *pStatus)        /* ptr for return overflow status value */
41714 +SK_U16 IStatus,                        /* Interrupt Status from MAC */
41715 +SK_U64 SK_FAR *pStatus)        /* Pointer for return overflow status value */
41716  {
41717 -       SK_U64  Status;         /* Overflow status */
41718         SK_U16  RegVal;
41719 +#ifndef SK_SLIM
41720 +       SK_U64  Status;         /* Overflow status */
41721
41722         Status = 0;
41723 +#endif /* !SK_SLIM */
41724
41725         if ((IStatus & GM_IS_RX_CO_OV) != 0) {
41726                 /* this register is self-clearing after read */
41727                 GM_IN16(IoC, Port, GM_RX_IRQ_SRC, &RegVal);
41728 +
41729 +#ifndef SK_SLIM
41730                 Status |= (SK_U64)RegVal << 32;
41731 +#endif /* !SK_SLIM */
41732         }
41733 -
41734 +
41735         if ((IStatus & GM_IS_TX_CO_OV) != 0) {
41736                 /* this register is self-clearing after read */
41737                 GM_IN16(IoC, Port, GM_TX_IRQ_SRC, &RegVal);
41738 +
41739 +#ifndef SK_SLIM
41740                 Status |= (SK_U64)RegVal;
41741 +#endif /* !SK_SLIM */
41742         }
41743 -
41744 +
41745         /* this register is self-clearing after read */
41746         GM_IN16(IoC, Port, GM_TR_IRQ_SRC, &RegVal);
41747 +
41748 +#ifndef SK_SLIM
41749         /* Rx overflow interrupt register bits (LoByte)*/
41750         Status |= (SK_U64)((SK_U8)RegVal) << 48;
41751         /* Tx overflow interrupt register bits (HiByte)*/
41752         Status |= (SK_U64)(RegVal >> 8) << 16;
41753
41754         *pStatus = Status;
41755 +#endif /* !SK_SLIM */
41756 +
41757 +       /* dummy read after GM_IN16() */
41758 +       SK_IN16(IoC, B0_RAP, &RegVal);
41759
41760         return(0);
41761  }      /* SkGmOverflowStatus */
41762 @@ -4079,60 +5307,124 @@
41763   *  gets the results if 'StartTest' is true
41764   *
41765   * NOTE:       this test is meaningful only when link is down
41766 - *
41767 + *
41768   * Returns:
41769   *     0:  success
41770   *     1:      no YUKON copper
41771   *     2:      test in progress
41772   */
41773  int SkGmCableDiagStatus(
41774 -SK_AC  *pAC,           /* adapter context */
41775 -SK_IOC IoC,            /* IO context */
41776 +SK_AC  *pAC,           /* Adapter Context */
41777 +SK_IOC IoC,            /* I/O Context */
41778  int            Port,           /* Port Index (MAC_1 + n) */
41779  SK_BOOL        StartTest)      /* flag for start / get result */
41780  {
41781         int             i;
41782 +       int             CableDiagOffs;
41783 +       int             MdiPairs;
41784 +       int             Rtv;
41785 +       SK_BOOL FastEthernet;
41786 +       SK_BOOL Yukon2;
41787         SK_U16  RegVal;
41788         SK_GEPORT       *pPrt;
41789
41790         pPrt = &pAC->GIni.GP[Port];
41791
41792         if (pPrt->PhyType != SK_PHY_MARV_COPPER) {
41793 -
41794 +
41795                 return(1);
41796         }
41797
41798 +       Yukon2 = pAC->GIni.GIChipId == CHIP_ID_YUKON_XL ||
41799 +                        pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U;
41800 +
41801 +       if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) {
41802 +
41803 +               CableDiagOffs = PHY_MARV_FE_VCT_TX;
41804 +               FastEthernet = SK_TRUE;
41805 +               MdiPairs = 2;
41806 +       }
41807 +       else {
41808 +               CableDiagOffs = Yukon2 ? PHY_MARV_PHY_CTRL : PHY_MARV_CABLE_DIAG;
41809 +               FastEthernet = SK_FALSE;
41810 +               MdiPairs = 4;
41811 +       }
41812 +
41813         if (StartTest) {
41814 +
41815 +               /* set to RESET to avoid PortCheckUp */
41816 +               pPrt->PState = SK_PRT_RESET;
41817 +
41818                 /* only start the cable test */
41819 -               if ((pPrt->PhyId1 & PHY_I1_REV_MSK) < 4) {
41820 -                       /* apply TDR workaround from Marvell */
41821 -                       SkGmPhyWrite(pAC, IoC, Port, 29, 0x001e);
41822 -
41823 -                       SkGmPhyWrite(pAC, IoC, Port, 30, 0xcc00);
41824 -                       SkGmPhyWrite(pAC, IoC, Port, 30, 0xc800);
41825 -                       SkGmPhyWrite(pAC, IoC, Port, 30, 0xc400);
41826 -                       SkGmPhyWrite(pAC, IoC, Port, 30, 0xc000);
41827 -                       SkGmPhyWrite(pAC, IoC, Port, 30, 0xc100);
41828 +               if (!FastEthernet) {
41829 +
41830 +                       if ((((pPrt->PhyId1 & PHY_I1_MOD_NUM) >> 4) == 2) &&
41831 +                                ((pPrt->PhyId1 & PHY_I1_REV_MSK) < 4)) {
41832 +                               /* apply TDR workaround for model 2, rev. < 4 */
41833 +                               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_ADDR, 0x001e);
41834 +
41835 +                               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xcc00);
41836 +                               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xc800);
41837 +                               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xc400);
41838 +                               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xc000);
41839 +                               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xc100);
41840 +                       }
41841 +
41842 +#ifdef YUKON_DBG
41843 +                       if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) {
41844 +                               /* set address to 1 for page 1 */
41845 +                               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 1);
41846 +
41847 +                               /* disable waiting period */
41848 +                               SkGmPhyWrite(pAC, IoC, Port, CableDiagOffs,
41849 +                                       PHY_M_CABD_DIS_WAIT);
41850 +                       }
41851 +#endif
41852 +                       if (Yukon2) {
41853 +                               /* set address to 5 for page 5 */
41854 +                               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 5);
41855 +
41856 +#ifdef YUKON_DBG
41857 +                               /* disable waiting period */
41858 +                               SkGmPhyWrite(pAC, IoC, Port, CableDiagOffs + 1,
41859 +                                       PHY_M_CABD_DIS_WAIT);
41860 +#endif
41861 +                       }
41862 +                       else {
41863 +                               /* set address to 0 for MDI[0] (Page 0) */
41864 +                               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0);
41865 +                       }
41866                 }
41867 +               else {
41868 +                       RegVal = PHY_CT_RESET | PHY_CT_SP100;
41869
41870 -               /* set address to 0 for MDI[0] */
41871 -               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0);
41872 +                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, RegVal);
41873
41874 -               /* Read Cable Diagnostic Reg */
41875 -               SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CABLE_DIAG, &RegVal);
41876 +#ifdef xYUKON_DBG
41877 +                       SkGmPhyRead(pAC, IoC, Port, PHY_MARV_FE_SPEC_2, &RegVal);
41878 +                       /* disable waiting period */
41879 +                       RegVal |= PHY_M_FESC_DIS_WAIT;
41880 +
41881 +                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_FE_SPEC_2, RegVal);
41882 +#endif
41883 +               }
41884
41885                 /* start Cable Diagnostic Test */
41886 -               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CABLE_DIAG,
41887 -                       (SK_U16)(RegVal | PHY_M_CABD_ENA_TEST));
41888 -
41889 +               SkGmPhyWrite(pAC, IoC, Port, CableDiagOffs, PHY_M_CABD_ENA_TEST);
41890 +
41891                 return(0);
41892         }
41893 -
41894 +
41895         /* Read Cable Diagnostic Reg */
41896 -       SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CABLE_DIAG, &RegVal);
41897 +       Rtv = SkGmPhyRead(pAC, IoC, Port, CableDiagOffs, &RegVal);
41898 +
41899 +       if (Rtv == 2) {
41900 +               /* PHY read timeout */
41901 +               return(3);
41902 +       }
41903
41904         SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
41905 -               ("PHY Cable Diag.=0x%04X\n", RegVal));
41906 +               ("PHY Cable Diag. = 0x%04X\n", RegVal));
41907
41908         if ((RegVal & PHY_M_CABD_ENA_TEST) != 0) {
41909                 /* test is running */
41910 @@ -4140,16 +5432,24 @@
41911         }
41912
41913         /* get the test results */
41914 -       for (i = 0; i < 4; i++)  {
41915 -               /* set address to i for MDI[i] */
41916 -               SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, (SK_U16)i);
41917 +       for (i = 0; i < MdiPairs; i++) {
41918 +
41919 +               if (!FastEthernet && !Yukon2) {
41920 +                       /* set address to i for MDI[i] */
41921 +                       SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, (SK_U16)i);
41922 +               }
41923
41924                 /* get Cable Diagnostic values */
41925 -               SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CABLE_DIAG, &RegVal);
41926 +               SkGmPhyRead(pAC, IoC, Port, CableDiagOffs, &RegVal);
41927
41928                 pPrt->PMdiPairLen[i] = (SK_U8)(RegVal & PHY_M_CABD_DIST_MSK);
41929
41930                 pPrt->PMdiPairSts[i] = (SK_U8)((RegVal & PHY_M_CABD_STAT_MSK) >> 13);
41931 +
41932 +               if (FastEthernet || Yukon2) {
41933 +                       /* get next register */
41934 +                       CableDiagOffs++;
41935 +               }
41936         }
41937
41938         return(0);
41939 @@ -4158,3 +5458,4 @@
41940  #endif /* YUKON */
41941
41942  /* End of file */
41943 +
41944 diff -ruN linux/drivers/net/sk98lin/sky2.c linux-new/drivers/net/sk98lin/sky2.c
41945 --- linux/drivers/net/sk98lin/sky2.c    1970-01-01 01:00:00.000000000 +0100
41946 +++ linux-new/drivers/net/sk98lin/sky2.c        2006-07-28 14:13:56.000000000 +0200
41947 @@ -0,0 +1,2733 @@
41948 +/******************************************************************************
41949 + *
41950 + * Name:        sky2.c
41951 + * Project:     Yukon2 specific functions and implementations
41952 + * Version:     $Revision$
41953 + * Date:        $Date$
41954 + * Purpose:     The main driver source module
41955 + *
41956 + *****************************************************************************/
41957 +
41958 +/******************************************************************************
41959 + *
41960 + *     (C)Copyright 1998-2002 SysKonnect GmbH.
41961 + *     (C)Copyright 2002-2005 Marvell.
41962 + *
41963 + *     Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet
41964 + *      Server Adapters.
41965 + *
41966 + *     Author: Ralph Roesler (rroesler@syskonnect.de)
41967 + *             Mirko Lindner (mlindner@syskonnect.de)
41968 + *
41969 + *     Address all question to: linux@syskonnect.de
41970 + *
41971 + *     This program is free software; you can redistribute it and/or modify
41972 + *     it under the terms of the GNU General Public License as published by
41973 + *     the Free Software Foundation; either version 2 of the License, or
41974 + *     (at your option) any later version.
41975 + *
41976 + *     The information in this file is provided "AS IS" without warranty.
41977 + *
41978 + *****************************************************************************/
41979 +
41980 +#include "h/skdrv1st.h"
41981 +#include "h/skdrv2nd.h"
41982 +#include <linux/tcp.h>
41983 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,14)
41984 +#include <linux/ip.h>
41985 +#endif
41986 +/******************************************************************************
41987 + *
41988 + * Local Function Prototypes
41989 + *
41990 + *****************************************************************************/
41991 +
41992 +static void InitPacketQueues(SK_AC *pAC,int Port);
41993 +static void GiveTxBufferToHw(SK_AC *pAC,SK_IOC IoC,int Port);
41994 +static void GiveRxBufferToHw(SK_AC *pAC,SK_IOC IoC,int Port,SK_PACKET *pPacket);
41995 +static SK_BOOL HandleReceives(SK_AC *pAC,int Port,SK_U16 Len,SK_U32 FrameStatus,SK_U16 Tcp1,SK_U16 Tcp2,SK_U32 Tist,SK_U16 Vlan);
41996 +static void CheckForSendComplete(SK_AC *pAC,SK_IOC IoC,int Port,SK_PKT_QUEUE *pPQ,SK_LE_TABLE *pLETab,unsigned int Done);
41997 +static void UnmapAndFreeTxPktBuffer(SK_AC *pAC,SK_PACKET *pSkPacket,int TxPort);
41998 +static SK_BOOL AllocateAndInitLETables(SK_AC *pAC);
41999 +static SK_BOOL AllocatePacketBuffersYukon2(SK_AC *pAC);
42000 +static void FreeLETables(SK_AC *pAC);
42001 +static void FreePacketBuffers(SK_AC *pAC);
42002 +static SK_BOOL AllocAndMapRxBuffer(SK_AC *pAC,SK_PACKET *pSkPacket,int Port);
42003 +#ifdef CONFIG_SK98LIN_NAPI
42004 +static SK_BOOL HandleStatusLEs(SK_AC *pAC,int *WorkDone,int WorkToDo);
42005 +#else
42006 +static SK_BOOL HandleStatusLEs(SK_AC *pAC);
42007 +#endif
42008 +
42009 +extern void    SkGeCheckTimer          (DEV_NET *pNet);
42010 +extern void    SkLocalEventQueue(      SK_AC *pAC,
42011 +                                       SK_U32 Class,
42012 +                                       SK_U32 Event,
42013 +                                       SK_U32 Param1,
42014 +                                       SK_U32 Param2,
42015 +                                       SK_BOOL Flag);
42016 +extern void    SkLocalEventQueue64(    SK_AC *pAC,
42017 +                                       SK_U32 Class,
42018 +                                       SK_U32 Event,
42019 +                                       SK_U64 Param,
42020 +                                       SK_BOOL Flag);
42021 +
42022 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,15)
42023 +/* Need way to schedule device 0 even when it's offline. */
42024 +static inline int __netif_rx_schedule_prep(struct net_device *dev)
42025 +{
42026 +       return !test_and_set_bit(__LINK_STATE_RX_SCHED, &dev->state);
42027 +}
42028 +#endif
42029 +
42030 +
42031 +/******************************************************************************
42032 + *
42033 + * Local Variables
42034 + *
42035 + *****************************************************************************/
42036 +
42037 +#define MAX_NBR_RX_BUFFERS_IN_HW       0x15
42038 +static SK_U8 NbrRxBuffersInHW;
42039 +#define FLUSH_OPC(le)
42040 +
42041 +/******************************************************************************
42042 + *
42043 + * Global Functions
42044 + *
42045 + *****************************************************************************/
42046 +
42047 +int SkY2Xmit( struct sk_buff *skb, struct SK_NET_DEVICE *dev);
42048 +void FillReceiveTableYukon2(SK_AC *pAC,SK_IOC IoC,int Port);
42049 +
42050 +/*****************************************************************************
42051 + *
42052 + *     SkY2RestartStatusUnit - restarts teh status unit
42053 + *
42054 + * Description:
42055 + *     Reenables the status unit after any De-Init (e.g. when altering
42056 + *     the sie of the MTU via 'ifconfig a.b.c.d mtu xxx')
42057 + *
42058 + * Returns:    N/A
42059 + */
42060 +void SkY2RestartStatusUnit(
42061 +SK_AC  *pAC)  /* pointer to adapter control context */
42062 +{
42063 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42064 +               ("==> SkY2RestartStatusUnit\n"));
42065 +
42066 +       /*
42067 +       ** It might be that the TX timer is not started. Therefore
42068 +       ** it is initialized here -> to be more investigated!
42069 +       */
42070 +       SK_OUT32(pAC->IoBase, STAT_TX_TIMER_INI, HW_MS_TO_TICKS(pAC,10));
42071 +
42072 +       pAC->StatusLETable.Done  = 0;
42073 +       pAC->StatusLETable.Put   = 0;
42074 +       pAC->StatusLETable.HwPut = 0;
42075 +       SkGeY2InitStatBmu(pAC, pAC->IoBase, &pAC->StatusLETable);
42076 +
42077 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42078 +               ("<== SkY2RestartStatusUnit\n"));
42079 +}
42080 +
42081 +/*****************************************************************************
42082 + *
42083 + *     SkY2RlmtSend - sends out a single RLMT notification
42084 + *
42085 + * Description:
42086 + *     This function sends out an RLMT frame
42087 + *
42088 + * Returns:
42089 + *     > 0 - on succes: the number of bytes in the message
42090 + *     = 0 - on resource shortage: this frame sent or dropped, now
42091 + *           the ring is full ( -> set tbusy)
42092 + *     < 0 - on failure: other problems ( -> return failure to upper layers)
42093 + */
42094 +int SkY2RlmtSend (
42095 +SK_AC          *pAC,       /* pointer to adapter control context           */
42096 +int             PortNr,    /* index of port the packet(s) shall be send to */
42097 +struct sk_buff *pMessage)  /* pointer to send-message                      */
42098 +{
42099 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42100 +               ("=== SkY2RlmtSend\n"));
42101 +#if 0
42102 +       return -1;   // temporarily do not send out RLMT frames
42103 +#endif
42104 +       skb_shinfo(pMessage)->nr_frags = (2*MAX_SKB_FRAGS) + PortNr;
42105 +       return(SkY2Xmit(pMessage, pAC->dev[PortNr])); // SkY2Xmit needs device
42106 +}
42107 +
42108 +/*****************************************************************************
42109 + *
42110 + *     SkY2AllocateResources - Allocates all required resources for Yukon2
42111 + *
42112 + * Description:
42113 + *     This function allocates all memory needed for the Yukon2.
42114 + *     It maps also RX buffers to the LETables and initializes the
42115 + *     status list element table.
42116 + *
42117 + * Returns:
42118 + *     SK_TRUE, if all resources could be allocated and setup succeeded
42119 + *     SK_FALSE, if an error
42120 + */
42121 +SK_BOOL SkY2AllocateResources (
42122 +SK_AC  *pAC)  /* pointer to adapter control context */
42123 +{
42124 +       int CurrMac;
42125 +
42126 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
42127 +               ("==> SkY2AllocateResources\n"));
42128 +
42129 +       /*
42130 +       ** Initialize the packet queue variables first
42131 +       */
42132 +       for (CurrMac = 0; CurrMac < pAC->GIni.GIMacsFound; CurrMac++) {
42133 +               InitPacketQueues(pAC, CurrMac);
42134 +       }
42135 +
42136 +       /*
42137 +       ** Get sufficient memory for the LETables
42138 +       */
42139 +       if (!AllocateAndInitLETables(pAC)) {
42140 +               SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
42141 +                       SK_DBGCAT_INIT | SK_DBGCAT_DRV_ERROR,
42142 +                       ("No memory for LETable.\n"));
42143 +               return(SK_FALSE);
42144 +       }
42145 +
42146 +       /*
42147 +       ** Allocate and intialize memory for both RX and TX
42148 +       ** packet and fragment buffers. On an error, free
42149 +       ** previously allocated LETable memory and quit.
42150 +       */
42151 +       if (!AllocatePacketBuffersYukon2(pAC)) {
42152 +               FreeLETables(pAC);
42153 +               SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
42154 +                       SK_DBGCAT_INIT | SK_DBGCAT_DRV_ERROR,
42155 +                       ("No memory for Packetbuffers.\n"));
42156 +               return(SK_FALSE);
42157 +       }
42158 +
42159 +       /*
42160 +       ** Rx and Tx LE tables will be initialized in SkGeOpen()
42161 +       **
42162 +       ** It might be that the TX timer is not started. Therefore
42163 +       ** it is initialized here -> to be more investigated!
42164 +       */
42165 +       SK_OUT32(pAC->IoBase, STAT_TX_TIMER_INI, HW_MS_TO_TICKS(pAC,10));
42166 +       SkGeY2InitStatBmu(pAC, pAC->IoBase, &pAC->StatusLETable);
42167 +
42168 +       pAC->MaxUnusedRxLeWorking = MAX_UNUSED_RX_LE_WORKING;
42169 +
42170 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
42171 +               ("<== SkY2AllocateResources\n"));
42172 +
42173 +       return (SK_TRUE);
42174 +}
42175 +
42176 +/*****************************************************************************
42177 + *
42178 + *     SkY2FreeResources - Frees previously allocated resources of Yukon2
42179 + *
42180 + * Description:
42181 + *     This function frees all previously allocated memory of the Yukon2.
42182 + *
42183 + * Returns: N/A
42184 + */
42185 +void SkY2FreeResources (
42186 +SK_AC  *pAC)  /* pointer to adapter control context */
42187 +{
42188 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42189 +               ("==> SkY2FreeResources\n"));
42190 +
42191 +       FreeLETables(pAC);
42192 +       FreePacketBuffers(pAC);
42193 +
42194 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42195 +               ("<== SkY2FreeResources\n"));
42196 +}
42197 +
42198 +/*****************************************************************************
42199 + *
42200 + *     SkY2AllocateRxBuffers - Allocates the receive buffers for a port
42201 + *
42202 + * Description:
42203 + *     This function allocated all the RX buffers of the Yukon2.
42204 + *
42205 + * Returns: N/A
42206 + */
42207 +void SkY2AllocateRxBuffers (
42208 +SK_AC    *pAC,   /* pointer to adapter control context */
42209 +SK_IOC    IoC,  /* I/O control context                */
42210 +int       Port)         /* port index of RX                   */
42211 +{
42212 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
42213 +               ("==> SkY2AllocateRxBuffers (Port %c)\n", Port));
42214 +
42215 +       FillReceiveTableYukon2(pAC, IoC, Port);
42216 +
42217 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
42218 +               ("<== SkY2AllocateRxBuffers\n"));
42219 +}
42220 +
42221 +/*****************************************************************************
42222 + *
42223 + *     SkY2FreeRxBuffers - Free's all allocates RX buffers of
42224 + *
42225 + * Description:
42226 + *     This function frees all RX buffers of the Yukon2 for a single port
42227 + *
42228 + * Returns: N/A
42229 + */
42230 +void SkY2FreeRxBuffers (
42231 +SK_AC    *pAC,   /* pointer to adapter control context */
42232 +SK_IOC    IoC,  /* I/O control context                */
42233 +int       Port)         /* port index of RX                   */
42234 +{
42235 +       SK_PACKET     *pSkPacket;
42236 +       unsigned long  Flags;   /* for POP/PUSH macros */
42237 +
42238 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42239 +               ("==> SkY2FreeRxBuffers (Port %c)\n", Port));
42240 +
42241 +       if (pAC->RxPort[Port].ReceivePacketTable   != NULL) {
42242 +               POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_working, pSkPacket);
42243 +               while (pSkPacket != NULL) {
42244 +                       if ((pSkPacket->pFrag) != NULL) {
42245 +                               pci_unmap_page(pAC->PciDev,
42246 +                               (dma_addr_t) pSkPacket->pFrag->pPhys,
42247 +                               pSkPacket->pFrag->FragLen - 2,
42248 +                               PCI_DMA_FROMDEVICE);
42249 +
42250 +                               /* wipe out any rubbish data that may interfere */
42251 +                               skb_shinfo(pSkPacket->pMBuf)->nr_frags = 0;
42252 +                               skb_shinfo(pSkPacket->pMBuf)->frag_list = NULL;
42253 +                               DEV_KFREE_SKB_ANY(pSkPacket->pMBuf);
42254 +                               pSkPacket->pMBuf        = NULL;
42255 +                               pSkPacket->pFrag->pPhys = (SK_U64) 0;
42256 +                               pSkPacket->pFrag->pVirt = NULL;
42257 +                       }
42258 +                       PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pSkPacket);
42259 +                       POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_working, pSkPacket);
42260 +               }
42261 +       }
42262 +
42263 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42264 +               ("<== SkY2FreeRxBuffers\n"));
42265 +}
42266 +
42267 +/*****************************************************************************
42268 + *
42269 + *     SkY2FreeTxBuffers - Free's any currently maintained Tx buffer
42270 + *
42271 + * Description:
42272 + *     This function frees the TX buffers of the Yukon2 for a single port
42273 + *     which might be in use by a transmit action
42274 + *
42275 + * Returns: N/A
42276 + */
42277 +void SkY2FreeTxBuffers (
42278 +SK_AC    *pAC,   /* pointer to adapter control context */
42279 +SK_IOC    IoC,  /* I/O control context                */
42280 +int       Port)         /* port index of TX                   */
42281 +{
42282 +       SK_PACKET      *pSkPacket;
42283 +       SK_FRAG        *pSkFrag;
42284 +       unsigned long   Flags;
42285 +
42286 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42287 +               ("==> SkY2FreeTxBuffers (Port %c)\n", Port));
42288 +
42289 +       if (pAC->TxPort[Port][0].TransmitPacketTable != NULL) {
42290 +               POP_FIRST_PKT_FROM_QUEUE(&pAC->TxPort[Port][0].TxAQ_working, pSkPacket);
42291 +               while (pSkPacket != NULL) {
42292 +                       if ((pSkFrag = pSkPacket->pFrag) != NULL) {
42293 +                               UnmapAndFreeTxPktBuffer(pAC, pSkPacket, Port);
42294 +                       }
42295 +                       PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->TxPort[Port][0].TxQ_free, pSkPacket);
42296 +                       POP_FIRST_PKT_FROM_QUEUE(&pAC->TxPort[Port][0].TxAQ_working, pSkPacket);
42297 +               }
42298 +#ifdef USE_SYNC_TX_QUEUE
42299 +               POP_FIRST_PKT_FROM_QUEUE(&pAC->TxPort[Port][0].TxSQ_working, pSkPacket);
42300 +               while (pSkPacket != NULL) {
42301 +                       if ((pSkFrag = pSkPacket->pFrag) != NULL) {
42302 +                               UnmapAndFreeTxPktBuffer(pAC, pSkPacket, Port);
42303 +                       }
42304 +                       PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->TxPort[Port][0].TxQ_free, pSkPacket);
42305 +                       POP_FIRST_PKT_FROM_QUEUE(&pAC->TxPort[Port][0].TxSQ_working, pSkPacket);
42306 +               }
42307 +#endif
42308 +       }
42309 +
42310 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42311 +               ("<== SkY2FreeTxBuffers\n"));
42312 +}
42313 +
42314 +/*****************************************************************************
42315 + *
42316 + *     SkY2Isr - handle a receive IRQ for all yukon2 cards
42317 + *
42318 + * Description:
42319 + *     This function is called when a receive IRQ is set. (only for yukon2)
42320 + *     HandleReceives does the deferred processing of all outstanding
42321 + *     interrupt operations.
42322 + *
42323 + * Returns:    N/A
42324 + */
42325 +SkIsrRetVar SkY2Isr (
42326 +int              irq,     /* the irq we have received (might be shared!) */
42327 +void            *dev_id  /* current device id                           */
42328 +) /*  */
42329 +{
42330 +       struct SK_NET_DEVICE  *dev  = (struct SK_NET_DEVICE *)dev_id;
42331 +       DEV_NET               *pNet = (DEV_NET*) dev->priv;
42332 +       SK_AC                 *pAC  = pNet->pAC;
42333 +       SK_U32                 IntSrc;
42334 +#ifdef CONFIG_SK98LIN_NAPI
42335 +       SK_BOOL                SetIntMask       = SK_FALSE;
42336 +#else
42337 +       SK_BOOL                handledStatLE    = SK_FALSE;
42338 +       unsigned long          Flags;
42339 +#endif
42340 +
42341 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
42342 +               ("==> SkY2Isr\n"));
42343 +
42344 +       SK_IN32(pAC->IoBase, B0_Y2_SP_ISRC2, &IntSrc);
42345 +
42346 +       if ((IntSrc == 0) && (!pNet->NetConsoleMode)){
42347 +               SK_OUT32(pAC->IoBase, B0_Y2_SP_ICR, 2);
42348 +               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
42349 +                       ("No Interrupt\n ==> SkY2Isr\n"));
42350 +               return SkIsrRetNone;
42351 +
42352 +       }
42353 +
42354 +#ifdef Y2_RECOVERY
42355 +       if (pNet->InRecover) {
42356 +               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
42357 +                       ("Already in recover\n ==> SkY2Isr\n"));
42358 +               SK_OUT32(pAC->IoBase, B0_Y2_SP_ICR, 2);
42359 +               return SkIsrRetNone;
42360 +       }
42361 +#endif
42362 +
42363 +#ifdef CONFIG_SK98LIN_NAPI
42364 +       /* Since both boards share one irq, they share one poll routine */
42365 +       if (__netif_rx_schedule_prep(pAC->dev[0])) {
42366 +               pAC->GIni.GIValIrqMask &= ~(Y2_IS_STAT_BMU);
42367 +               SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
42368 +               SetIntMask = SK_TRUE;
42369 +               __netif_rx_schedule(pAC->dev[0]);
42370 +       }
42371 +#else
42372 +       handledStatLE = HandleStatusLEs(pAC);
42373 +#endif
42374 +
42375 +       /*
42376 +       ** Check for Special Interrupts
42377 +       */
42378 +       if ((IntSrc & ~Y2_IS_STAT_BMU) || pAC->CheckQueue || pNet->TimerExpired) {
42379 +               pAC->CheckQueue = SK_FALSE;
42380 +#ifdef CONFIG_SK98LIN_NAPI
42381 +               spin_lock(&pAC->SlowPathLock);
42382 +#else
42383 +               spin_lock_irqsave(&pAC->SetPutIndexLock, Flags);
42384 +#endif
42385 +               SkGeSirqIsr(pAC, pAC->IoBase, IntSrc);
42386 +               SkEventDispatcher(pAC, pAC->IoBase);
42387 +#ifdef CONFIG_SK98LIN_NAPI
42388 +               spin_unlock(&pAC->SlowPathLock);
42389 +#else
42390 +               spin_unlock_irqrestore(&pAC->SetPutIndexLock, Flags);
42391 +#endif
42392 +       }
42393 +
42394 +       /* Speed enhancement for a2 chipsets */
42395 +       if (HW_FEATURE(pAC, HWF_WA_DEV_42)) {
42396 +#ifdef CONFIG_SK98LIN_NAPI
42397 +               spin_lock(&pAC->SlowPathLock);
42398 +#else
42399 +               spin_lock_irqsave(&pAC->SetPutIndexLock, Flags);
42400 +#endif
42401 +               SkGeY2SetPutIndex(pAC, pAC->IoBase, Y2_PREF_Q_ADDR(Q_XA1,0), &pAC->TxPort[0][0].TxALET);
42402 +               SkGeY2SetPutIndex(pAC, pAC->IoBase, Y2_PREF_Q_ADDR(Q_R1,0), &pAC->RxPort[0].RxLET);
42403 +#ifdef CONFIG_SK98LIN_NAPI
42404 +               spin_unlock(&pAC->SlowPathLock);
42405 +#else
42406 +               spin_unlock_irqrestore(&pAC->SetPutIndexLock, Flags);
42407 +#endif
42408 +       }
42409 +
42410 +       /*
42411 +       ** Reenable interrupts and signal end of ISR
42412 +       */
42413 +       SK_OUT32(pAC->IoBase, B0_Y2_SP_ICR, 2);
42414 +
42415 +       /*
42416 +       ** Stop and restart TX timer in case a Status LE was handled
42417 +       */
42418 +#ifndef CONFIG_SK98LIN_NAPI
42419 +       if ((HW_FEATURE(pAC, HWF_WA_DEV_43_418)) && (handledStatLE)) {
42420 +               SK_OUT8(pAC->IoBase, STAT_TX_TIMER_CTRL, TIM_STOP);
42421 +               SK_OUT8(pAC->IoBase, STAT_TX_TIMER_CTRL, TIM_START);
42422 +       }
42423 +#endif
42424 +
42425 +       if (!(IS_Q_EMPTY(&(pAC->TxPort[0][TX_PRIO_LOW].TxAQ_waiting)))) {
42426 +               GiveTxBufferToHw(pAC, pAC->IoBase, 0);
42427 +       }
42428 +       if (!(IS_Q_EMPTY(&(pAC->TxPort[1][TX_PRIO_LOW].TxAQ_waiting)))) {
42429 +               GiveTxBufferToHw(pAC, pAC->IoBase, 1);
42430 +       }
42431 +
42432 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
42433 +               ("<== SkY2Isr\n"));
42434 +
42435 +       return SkIsrRetHandled;
42436 +}      /* SkY2Isr */
42437 +
42438 +/*****************************************************************************
42439 + *
42440 + *     SkY2Xmit - Linux frame transmit function for Yukon2
42441 + *
42442 + * Description:
42443 + *     The system calls this function to send frames onto the wire.
42444 + *     It puts the frame in the tx descriptor ring. If the ring is
42445 + *     full then, the 'tbusy' flag is set.
42446 + *
42447 + * Returns:
42448 + *     0, if everything is ok
42449 + *     !=0, on error
42450 + *
42451 + * WARNING:
42452 + *     returning 1 in 'tbusy' case caused system crashes (double
42453 + *     allocated skb's) !!!
42454 + */
42455 +int SkY2Xmit(
42456 +struct sk_buff       *skb,  /* socket buffer to be sent */
42457 +struct SK_NET_DEVICE *dev)  /* via which device?        */
42458 +{
42459 +       DEV_NET         *pNet    = (DEV_NET*) dev->priv;
42460 +       SK_AC           *pAC     = pNet->pAC;
42461 +       SK_U8            FragIdx = 0;
42462 +       SK_PACKET       *pSkPacket;
42463 +       SK_FRAG         *PrevFrag;
42464 +       SK_FRAG         *CurrFrag;
42465 +       SK_PKT_QUEUE    *pWorkQueue;  /* corresponding TX queue */
42466 +       SK_PKT_QUEUE    *pWaitQueue;
42467 +       SK_PKT_QUEUE    *pFreeQueue;
42468 +       SK_LE_TABLE     *pLETab;      /* corresponding LETable  */
42469 +       skb_frag_t      *sk_frag;
42470 +       SK_U64           PhysAddr;
42471 +       unsigned long    Flags;
42472 +       unsigned int     Port;
42473 +       int              CurrFragCtr;
42474 +
42475 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
42476 +               ("==> SkY2Xmit\n"));
42477 +
42478 +       /*
42479 +       ** Get port and return if no free packet is available
42480 +       */
42481 +       if (skb_shinfo(skb)->nr_frags > MAX_SKB_FRAGS) {
42482 +               Port = skb_shinfo(skb)->nr_frags - (2*MAX_SKB_FRAGS);
42483 +               skb_shinfo(skb)->nr_frags = 0;
42484 +       } else {
42485 +               Port = (pAC->RlmtNets == 2) ? pNet->PortNr : pAC->ActivePort;
42486 +       }
42487 +
42488 +       if (IS_Q_EMPTY(&(pAC->TxPort[Port][TX_PRIO_LOW].TxQ_free))) {
42489 +               SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
42490 +                       SK_DBGCAT_DRV_TX_PROGRESS | SK_DBGCAT_DRV_ERROR,
42491 +                       ("Not free packets available for send\n"));
42492 +               return 1; /* zero bytes sent! */
42493 +       }
42494 +
42495 +       /*
42496 +       ** Put any new packet to be sent in the waiting queue and
42497 +       ** handle also any possible fragment of that packet.
42498 +       */
42499 +       pWorkQueue = &(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_working);
42500 +       pWaitQueue = &(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting);
42501 +       pFreeQueue = &(pAC->TxPort[Port][TX_PRIO_LOW].TxQ_free);
42502 +       pLETab     = &(pAC->TxPort[Port][TX_PRIO_LOW].TxALET);
42503 +
42504 +       /*
42505 +       ** Normal send operations require only one fragment, because
42506 +       ** only one sk_buff data area is passed.
42507 +       ** In contradiction to this, scatter-gather (zerocopy) send
42508 +       ** operations might pass one or more additional fragments
42509 +       ** where each fragment needs a separate fragment info packet.
42510 +       */
42511 +       if (((skb_shinfo(skb)->nr_frags + 1) * MAX_FRAG_OVERHEAD) >
42512 +                                       NUM_FREE_LE_IN_TABLE(pLETab)) {
42513 +               SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
42514 +                       SK_DBGCAT_DRV_TX_PROGRESS | SK_DBGCAT_DRV_ERROR,
42515 +                       ("Not enough LE available for send\n"));
42516 +               return 1; /* zero bytes sent! */
42517 +       }
42518 +
42519 +       if ((skb_shinfo(skb)->nr_frags + 1) > MAX_NUM_FRAGS) {
42520 +               SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
42521 +                       SK_DBGCAT_DRV_TX_PROGRESS | SK_DBGCAT_DRV_ERROR,
42522 +                       ("Not even one fragment available for send\n"));
42523 +               return 1; /* zero bytes sent! */
42524 +       }
42525 +
42526 +       /*
42527 +       ** Get first packet from free packet queue
42528 +       */
42529 +       POP_FIRST_PKT_FROM_QUEUE(pFreeQueue, pSkPacket);
42530 +       if(pSkPacket == NULL) {
42531 +               SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
42532 +                       SK_DBGCAT_DRV_TX_PROGRESS | SK_DBGCAT_DRV_ERROR,
42533 +                       ("Could not obtain free packet used for xmit\n"));
42534 +               return 1; /* zero bytes sent! */
42535 +       }
42536 +
42537 +       pSkPacket->pFrag = &(pSkPacket->FragArray[FragIdx]);
42538 +
42539 +       /*
42540 +       ** map the sk_buff to be available for the adapter
42541 +       */
42542 +       PhysAddr = (SK_U64) pci_map_page(pAC->PciDev,
42543 +                       virt_to_page(skb->data),
42544 +                       ((unsigned long) skb->data & ~PAGE_MASK),
42545 +                       skb_headlen(skb),
42546 +                       PCI_DMA_TODEVICE);
42547 +       pSkPacket->pMBuf          = skb;
42548 +       pSkPacket->pFrag->pPhys   = PhysAddr;
42549 +       pSkPacket->pFrag->FragLen = skb_headlen(skb);
42550 +       pSkPacket->pFrag->pNext   = NULL; /* initial has no next default */
42551 +       pSkPacket->NumFrags       = skb_shinfo(skb)->nr_frags + 1;
42552 +
42553 +       PrevFrag = pSkPacket->pFrag;
42554 +
42555 +       /*
42556 +       ** Each scatter-gather fragment need to be mapped...
42557 +       */
42558 +        for (  CurrFragCtr = 0;
42559 +               CurrFragCtr < skb_shinfo(skb)->nr_frags;
42560 +               CurrFragCtr++) {
42561 +               FragIdx++;
42562 +               sk_frag = &skb_shinfo(skb)->frags[CurrFragCtr];
42563 +               CurrFrag = &(pSkPacket->FragArray[FragIdx]);
42564 +
42565 +               /*
42566 +               ** map the sk_buff to be available for the adapter
42567 +               */
42568 +               PhysAddr = (SK_U64) pci_map_page(pAC->PciDev,
42569 +                               sk_frag->page,
42570 +                               sk_frag->page_offset,
42571 +                               sk_frag->size,
42572 +                               PCI_DMA_TODEVICE);
42573 +
42574 +               CurrFrag->pPhys   = PhysAddr;
42575 +               CurrFrag->FragLen = sk_frag->size;
42576 +               CurrFrag->pNext   = NULL;
42577 +
42578 +               /*
42579 +               ** Add the new fragment to the list of fragments
42580 +               */
42581 +               PrevFrag->pNext = CurrFrag;
42582 +               PrevFrag = CurrFrag;
42583 +       }
42584 +
42585 +       /*
42586 +       ** Add packet to waiting packets queue
42587 +       */
42588 +       PUSH_PKT_AS_LAST_IN_QUEUE(pWaitQueue, pSkPacket);
42589 +       GiveTxBufferToHw(pAC, pAC->IoBase, Port);
42590 +       dev->trans_start = jiffies;
42591 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
42592 +               ("<== SkY2Xmit(return 0)\n"));
42593 +       return (0);
42594 +}      /* SkY2Xmit */
42595 +
42596 +#ifdef CONFIG_SK98LIN_NAPI
42597 +/*****************************************************************************
42598 + *
42599 + *     SkY2Poll - NAPI Rx polling callback for Yukon2 chipsets
42600 + *
42601 + * Description:
42602 + *     Called by the Linux system in case NAPI polling is activated
42603 + *
42604 + * Returns
42605 + *     The number of work data still to be handled
42606 + *
42607 + * Notes
42608 + *     The slowpath lock needs to be set because HW accesses may
42609 + *     interfere with slowpath events (e.g. TWSI)
42610 + */
42611 +int SkY2Poll(
42612 +struct net_device *dev,     /* device that needs to be polled */
42613 +int               *budget)  /* how many budget do we have?    */
42614 +{
42615 +       SK_AC          *pAC           = ((DEV_NET*)(dev->priv))->pAC;
42616 +       int             WorkToDo      = min(*budget, dev->quota);
42617 +       int             WorkDone      = 0;
42618 +       SK_BOOL         handledStatLE = SK_FALSE;
42619 +
42620 +       handledStatLE = HandleStatusLEs(pAC, &WorkDone, WorkToDo);
42621 +
42622 +       *budget -= WorkDone;
42623 +       dev->quota -= WorkDone;
42624 +
42625 +       if(WorkDone < WorkToDo) {
42626 +               netif_rx_complete(dev);
42627 +               pAC->GIni.GIValIrqMask |= (Y2_IS_STAT_BMU);
42628 +               SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
42629 +               if ((HW_FEATURE(pAC, HWF_WA_DEV_43_418)) && (handledStatLE)) {
42630 +                       SK_OUT8(pAC->IoBase, STAT_TX_TIMER_CTRL, TIM_STOP);
42631 +                       SK_OUT8(pAC->IoBase, STAT_TX_TIMER_CTRL, TIM_START);
42632 +               }
42633 +       }
42634 +       return (WorkDone >= WorkToDo);
42635 +}      /* SkY2Poll */
42636 +#endif
42637 +
42638 +/******************************************************************************
42639 + *
42640 + *     SkY2PortStop - stop a port on Yukon2
42641 + *
42642 + * Description:
42643 + *     This function stops a port of the Yukon2 chip. This stop
42644 + *     stop needs to be performed in a specific order:
42645 + *
42646 + *     a) Stop the Prefetch unit
42647 + *     b) Stop the Port (MAC, PHY etc.)
42648 + *
42649 + * Returns: N/A
42650 + */
42651 +void SkY2PortStop(
42652 +SK_AC   *pAC,      /* adapter control context                             */
42653 +SK_IOC   IoC,      /* I/O control context (address of adapter registers)  */
42654 +int      Port,     /* port to stop (MAC_1 + n)                            */
42655 +int      Dir,      /* StopDirection (SK_STOP_RX, SK_STOP_TX, SK_STOP_ALL) */
42656 +int      RstMode)  /* Reset Mode (SK_SOFT_RST, SK_HARD_RST)               */
42657 +{
42658 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42659 +               ("==> SkY2PortStop (Port %c)\n", 'A' + Port));
42660 +
42661 +       /*
42662 +       ** Stop the HW
42663 +       */
42664 +       SkGeStopPort(pAC, IoC, Port, Dir, RstMode);
42665 +
42666 +       /*
42667 +       ** Move any TX packet from work queues into the free queue again
42668 +       ** and initialize the TX LETable variables
42669 +       */
42670 +       SkY2FreeTxBuffers(pAC, pAC->IoBase, Port);
42671 +       pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Bmu.RxTx.TcpWp    = 0;
42672 +       pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Bmu.RxTx.MssValue = 0;
42673 +       pAC->TxPort[Port][TX_PRIO_LOW].TxALET.BufHighAddr       = 0;
42674 +       pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Done              = 0;
42675 +       pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Put               = 0;
42676 +       // pAC->GIni.GP[Port].PState = SK_PRT_STOP;
42677 +
42678 +       /*
42679 +       ** Move any RX packet from work queue into the waiting queue
42680 +       ** and initialize the RX LETable variables
42681 +       */
42682 +       SkY2FreeRxBuffers(pAC, pAC->IoBase, Port);
42683 +       pAC->RxPort[Port].RxLET.BufHighAddr = 0;
42684 +
42685 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42686 +               ("<== SkY2PortStop()\n"));
42687 +}
42688 +
42689 +/******************************************************************************
42690 + *
42691 + *     SkY2PortStart - start a port on Yukon2
42692 + *
42693 + * Description:
42694 + *     This function starts a port of the Yukon2 chip. This start
42695 + *     action needs to be performed in a specific order:
42696 + *
42697 + *     a) Initialize the LET indices (PUT/GET to 0)
42698 + *     b) Initialize the LET in HW (enables also prefetch unit)
42699 + *     c) Move all RX buffers from waiting queue to working queue
42700 + *        which involves also setting up of RX list elements
42701 + *     d) Initialize the FIFO settings of Yukon2 (Watermark etc.)
42702 + *     e) Initialize the Port (MAC, PHY etc.)
42703 + *     f) Initialize the MC addresses
42704 + *
42705 + * Returns:    N/A
42706 + */
42707 +void SkY2PortStart(
42708 +SK_AC   *pAC,   /* adapter control context                            */
42709 +SK_IOC   IoC,   /* I/O control context (address of adapter registers) */
42710 +int      Port)  /* port to start                                      */
42711 +{
42712 +       // SK_GEPORT *pPrt = &pAC->GIni.GP[Port];
42713 +       SK_HWLE   *pLE;
42714 +       SK_U32     DWord;
42715 +       SK_U32     PrefetchReg; /* register for Put index */
42716 +
42717 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42718 +               ("==> SkY2PortStart (Port %c)\n", 'A' + Port));
42719 +
42720 +       /*
42721 +       ** Initialize the LET indices
42722 +       */
42723 +       pAC->RxPort[Port].RxLET.Done                = 0;
42724 +       pAC->RxPort[Port].RxLET.Put                 = 0;
42725 +       pAC->RxPort[Port].RxLET.HwPut               = 0;
42726 +       pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Done  = 0;
42727 +       pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Put   = 0;
42728 +       pAC->TxPort[Port][TX_PRIO_LOW].TxALET.HwPut = 0;
42729 +       if (HW_SYNC_TX_SUPPORTED(pAC)) {
42730 +               pAC->TxPort[Port][TX_PRIO_LOW].TxSLET.Done  = 0;
42731 +               pAC->TxPort[Port][TX_PRIO_LOW].TxSLET.Put   = 0;
42732 +               pAC->TxPort[Port][TX_PRIO_LOW].TxSLET.HwPut = 0;
42733 +       }
42734 +
42735 +       if (HW_FEATURE(pAC, HWF_WA_DEV_420)) {
42736 +               /*
42737 +               ** It might be that we have to limit the RX buffers
42738 +               ** effectively passed to HW. Initialize the start
42739 +               ** value in that case...
42740 +               */
42741 +               NbrRxBuffersInHW = 0;
42742 +       }
42743 +
42744 +       /*
42745 +       ** TODO on dual net adapters we need to check if
42746 +       ** StatusLETable need to be set...
42747 +       **
42748 +       ** pAC->StatusLETable.Done  = 0;
42749 +       ** pAC->StatusLETable.Put   = 0;
42750 +       ** pAC->StatusLETable.HwPut = 0;
42751 +       ** SkGeY2InitPrefetchUnit(pAC, pAC->IoBase, Q_ST, &pAC->StatusLETable);
42752 +       */
42753 +
42754 +       /*
42755 +       ** Initialize the LET in HW (enables also prefetch unit)
42756 +       */
42757 +       SkGeY2InitPrefetchUnit(pAC, IoC,(Port == 0) ? Q_R1 : Q_R2,
42758 +                       &pAC->RxPort[Port].RxLET);
42759 +       SkGeY2InitPrefetchUnit( pAC, IoC,(Port == 0) ? Q_XA1 : Q_XA2,
42760 +                       &pAC->TxPort[Port][TX_PRIO_LOW].TxALET);
42761 +       if (HW_SYNC_TX_SUPPORTED(pAC)) {
42762 +               SkGeY2InitPrefetchUnit( pAC, IoC, (Port == 0) ? Q_XS1 : Q_XS2,
42763 +                               &pAC->TxPort[Port][TX_PRIO_HIGH].TxSLET);
42764 +       }
42765 +
42766 +
42767 +       /*
42768 +       ** Using new values for the watermarks and the timer for
42769 +       ** low latency optimization
42770 +       */
42771 +       if (pAC->LowLatency) {
42772 +               SK_OUT8(IoC, STAT_FIFO_WM, 1);
42773 +               SK_OUT8(IoC, STAT_FIFO_ISR_WM, 1);
42774 +               SK_OUT32(IoC, STAT_LEV_TIMER_INI, 50);
42775 +               SK_OUT32(IoC, STAT_ISR_TIMER_INI, 10);
42776 +       }
42777 +
42778 +
42779 +       /*
42780 +       ** Initialize the Port (MAC, PHY etc.)
42781 +       */
42782 +       if (SkGeInitPort(pAC, IoC, Port)) {
42783 +               if (Port == 0) {
42784 +                       printk("%s: SkGeInitPort A failed.\n",pAC->dev[0]->name);
42785 +               } else {
42786 +                       printk("%s: SkGeInitPort B failed.\n",pAC->dev[1]->name);
42787 +               }
42788 +       }
42789 +
42790 +       if (IS_GMAC(pAC)) {
42791 +               /* disable Rx GMAC FIFO Flush Mode */
42792 +               SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8) GMF_RX_F_FL_OFF);
42793 +       }
42794 +
42795 +       /*
42796 +       ** Initialize the MC addresses
42797 +       */
42798 +       SkAddrMcUpdate(pAC,IoC, Port);
42799 +
42800 +       SkMacRxTxEnable(pAC, IoC,Port);
42801 +
42802 +       if (pAC->RxPort[Port].UseRxCsum) {
42803 +               SkGeRxCsum(pAC, IoC, Port, SK_TRUE);
42804 +
42805 +               GET_RX_LE(pLE, &pAC->RxPort[Port].RxLET);
42806 +               RXLE_SET_STACS1(pLE, pAC->CsOfs1);
42807 +               RXLE_SET_STACS2(pLE, pAC->CsOfs2);
42808 +               RXLE_SET_CTRL(pLE, 0);
42809 +
42810 +               RXLE_SET_OPC(pLE, OP_TCPSTART | HW_OWNER);
42811 +               FLUSH_OPC(pLE);
42812 +               if (Port == 0) {
42813 +                       PrefetchReg=Y2_PREF_Q_ADDR(Q_R1,PREF_UNIT_PUT_IDX_REG);
42814 +               } else {
42815 +                       PrefetchReg=Y2_PREF_Q_ADDR(Q_R2,PREF_UNIT_PUT_IDX_REG);
42816 +               }
42817 +               DWord = GET_PUT_IDX(&pAC->RxPort[Port].RxLET);
42818 +               SK_OUT32(IoC, PrefetchReg, DWord);
42819 +               UPDATE_HWPUT_IDX(&pAC->RxPort[Port].RxLET);
42820 +       }
42821 +
42822 +       pAC->GIni.GP[Port].PState = SK_PRT_RUN;
42823 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42824 +               ("<== SkY2PortStart()\n"));
42825 +}
42826 +
42827 +/******************************************************************************
42828 + *
42829 + * Local Functions
42830 + *
42831 + *****************************************************************************/
42832 +
42833 +/*****************************************************************************
42834 + *
42835 + *     InitPacketQueues - initialize SW settings of packet queues
42836 + *
42837 + * Description:
42838 + *     This function will initialize the packet queues for a port.
42839 + *
42840 + * Returns: N/A
42841 + */
42842 +static void InitPacketQueues(
42843 +SK_AC  *pAC,   /* pointer to adapter control context */
42844 +int     Port)  /* index of port to be initialized    */
42845 +{
42846 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
42847 +               ("==> InitPacketQueues(Port %c)\n", 'A' + Port));
42848 +
42849 +       pAC->RxPort[Port].RxQ_working.pHead = NULL;
42850 +       pAC->RxPort[Port].RxQ_working.pTail = NULL;
42851 +       spin_lock_init(&pAC->RxPort[Port].RxQ_working.QueueLock);
42852 +
42853 +       pAC->RxPort[Port].RxQ_waiting.pHead = NULL;
42854 +       pAC->RxPort[Port].RxQ_waiting.pTail = NULL;
42855 +       spin_lock_init(&pAC->RxPort[Port].RxQ_waiting.QueueLock);
42856 +
42857 +       pAC->TxPort[Port][TX_PRIO_LOW].TxQ_free.pHead = NULL;
42858 +       pAC->TxPort[Port][TX_PRIO_LOW].TxQ_free.pTail = NULL;
42859 +       spin_lock_init(&pAC->TxPort[Port][TX_PRIO_LOW].TxQ_free.QueueLock);
42860 +
42861 +       pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_working.pHead = NULL;
42862 +       pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_working.pTail = NULL;
42863 +       spin_lock_init(&pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_working.QueueLock);
42864 +
42865 +       pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting.pHead = NULL;
42866 +       pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting.pTail = NULL;
42867 +       spin_lock_init(&pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting.QueueLock);
42868 +
42869 +#ifdef USE_SYNC_TX_QUEUE
42870 +       pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_working.pHead = NULL;
42871 +       pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_working.pTail = NULL;
42872 +       spin_lock_init(&pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_working.QueueLock);
42873 +
42874 +       pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_waiting.pHead = NULL;
42875 +       pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_waiting.pTail = NULL;
42876 +       spin_lock_init(&pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_waiting.QueueLock);
42877 +#endif
42878 +
42879 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
42880 +               ("<== InitPacketQueues(Port %c)\n", 'A' + Port));
42881 +}      /* InitPacketQueues */
42882 +
42883 +/*****************************************************************************
42884 + *
42885 + *     GiveTxBufferToHw - commits a previously allocated DMA area to HW
42886 + *
42887 + * Description:
42888 + *     This functions gives transmit buffers to HW. If no list elements
42889 + *     are available the buffers will be queued.
42890 + *
42891 + * Notes:
42892 + *       This function can run only once in a system at one time.
42893 + *
42894 + * Returns: N/A
42895 + */
42896 +static void GiveTxBufferToHw(
42897 +SK_AC   *pAC,   /* pointer to adapter control context         */
42898 +SK_IOC   IoC,   /* I/O control context (address of registers) */
42899 +int      Port)  /* port index for which the buffer is used    */
42900 +{
42901 +       SK_HWLE         *pLE;
42902 +       SK_PACKET       *pSkPacket;
42903 +       SK_FRAG         *pFrag;
42904 +       SK_PKT_QUEUE    *pWorkQueue;   /* corresponding TX queue */
42905 +       SK_PKT_QUEUE    *pWaitQueue;
42906 +       SK_LE_TABLE     *pLETab;       /* corresponding LETable  */
42907 +       SK_BOOL          SetOpcodePacketFlag;
42908 +       SK_U32           HighAddress;
42909 +       SK_U32           LowAddress;
42910 +       SK_U16           TcpSumStart;
42911 +       SK_U16           TcpSumWrite;
42912 +       SK_U8            OpCode;
42913 +       SK_U8            Ctrl;
42914 +       unsigned long    Flags;
42915 +       unsigned long    LockFlag;
42916 +       int              Protocol;
42917 +#ifdef NETIF_F_TSO
42918 +       SK_U16           Mss;
42919 +       int              TcpOptLen;
42920 +       int              IpTcpLen;
42921 +#endif
42922 +
42923 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
42924 +               ("==> GiveTxBufferToHw\n"));
42925 +
42926 +       if (IS_Q_EMPTY(&(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting))) {
42927 +               return;
42928 +       }
42929 +
42930 +       spin_lock_irqsave(&pAC->TxQueueLock, LockFlag);
42931 +
42932 +       /*
42933 +       ** Initialize queue settings
42934 +       */
42935 +       pWorkQueue = &(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_working);
42936 +       pWaitQueue = &(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting);
42937 +       pLETab     = &(pAC->TxPort[Port][TX_PRIO_LOW].TxALET);
42938 +
42939 +       POP_FIRST_PKT_FROM_QUEUE(pWaitQueue, pSkPacket);
42940 +       while (pSkPacket != NULL) {
42941 +               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
42942 +                       ("\tWe have a packet to send %p\n", pSkPacket));
42943 +
42944 +               /*
42945 +               ** the first frag of a packet gets opcode OP_PACKET
42946 +               */
42947 +               SetOpcodePacketFlag     = SK_TRUE;
42948 +               pFrag                   = pSkPacket->pFrag;
42949 +
42950 +               /*
42951 +               ** fill list elements with data from fragments
42952 +               */
42953 +               while (pFrag != NULL) {
42954 +                       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
42955 +                               ("\tGet LE\n"));
42956 +#ifdef NETIF_F_TSO
42957 +                       Mss = skb_shinfo(pSkPacket->pMBuf)->gso_size;
42958 +                       if (Mss) {
42959 +                               TcpOptLen = ((pSkPacket->pMBuf->h.th->doff - 5) * 4);
42960 +                               IpTcpLen  = ((pSkPacket->pMBuf->nh.iph->ihl * 4) +
42961 +                                               sizeof(struct tcphdr));
42962 +                               Mss += (TcpOptLen + IpTcpLen + C_LEN_ETHERMAC_HEADER);
42963 +                       }
42964 +                       if (pLETab->Bmu.RxTx.MssValue != Mss) {
42965 +                               pLETab->Bmu.RxTx.MssValue = Mss;
42966 +                               /* Take a new LE for TSO from the table */
42967 +                               GET_TX_LE(pLE, pLETab);
42968 +
42969 +#if 0
42970 +                               if(pSkPacket->VlanId) {
42971 +                                       TXLE_SET_OPC(pLE, OP_LRGLENVLAN | HW_OWNER);
42972 +                                       TXLE_SET_VLAN(pLE, pSkPacket->VlanId);
42973 +                                       pSkPacket->VlanId = 0;
42974 +                                       Ctrl |= INS_VLAN;
42975 +                               } else {
42976 +#endif
42977 +                                       TXLE_SET_OPC(pLE, OP_LRGLEN | HW_OWNER);
42978 +#if 0
42979 +                               }
42980 +#endif
42981 +                               /* set maximum segment size for new packet */
42982 +                               TXLE_SET_LSLEN(pLE, pLETab->Bmu.RxTx.MssValue);
42983 +                               FLUSH_OPC(pLE) ;
42984 +                       }
42985 +#endif
42986 +                       GET_TX_LE(pLE, pLETab);
42987 +                       Ctrl = 0;
42988 +
42989 +                       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
42990 +                               ("\tGot empty LE %p idx %d\n", pLE, GET_PUT_IDX(pLETab)));
42991 +
42992 +                       SK_DBG_DUMP_TX_LE(pLE);
42993 +
42994 +                       LowAddress  = (SK_U32) (pFrag->pPhys & 0xffffffff);
42995 +                       HighAddress = (SK_U32) (pFrag->pPhys >> 32);
42996 +
42997 +                       if (HighAddress != pLETab->BufHighAddr) {
42998 +                               /* set opcode high part of the address in one LE */
42999 +                               OpCode = OP_ADDR64 | HW_OWNER;
43000 +
43001 +                               /* Set now the 32 high bits of the address */
43002 +                               TXLE_SET_ADDR( pLE, HighAddress);
43003 +
43004 +                               /* Set the opcode into the LE */
43005 +                               TXLE_SET_OPC(pLE, OpCode);
43006 +
43007 +                               /* Flush the LE to memory */
43008 +                               FLUSH_OPC(pLE);
43009 +
43010 +                               /* remember the HighAddress we gave to the Hardware */
43011 +                               pLETab->BufHighAddr = HighAddress;
43012 +
43013 +                               /* get a new LE because we filled one with high address */
43014 +                               GET_TX_LE(pLE, pLETab);
43015 +                       }
43016 +
43017 +                       /*
43018 +                       ** TCP checksum offload
43019 +                       */
43020 +                       if ((pSkPacket->pMBuf->ip_summed == CHECKSUM_PARTIAL) &&
43021 +                           (SetOpcodePacketFlag         == SK_TRUE)) {
43022 +                               Protocol = ((SK_U8)pSkPacket->pMBuf->data[C_OFFSET_IPPROTO] & 0xff);
43023 +                               /* if (Protocol & C_PROTO_ID_IP) { Ctrl = 0; } */
43024 +                               if (Protocol & C_PROTO_ID_TCP) {
43025 +                                       Ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
43026 +                                       /* TCP Checksum Calculation Start Position */
43027 +                                       TcpSumStart = C_LEN_ETHERMAC_HEADER + IP_HDR_LEN;
43028 +                                       /* TCP Checksum Write Position */
43029 +                                       TcpSumWrite = TcpSumStart + TCP_CSUM_OFFS;
43030 +                               } else {
43031 +                                       Ctrl = UDPTCP | CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
43032 +                                       /* TCP Checksum Calculation Start Position */
43033 +                                       TcpSumStart = ETHER_MAC_HDR_LEN + IP_HDR_LEN;
43034 +                                       /* UDP Checksum Write Position */
43035 +                                       TcpSumWrite = TcpSumStart + UDP_CSUM_OFFS;
43036 +                               }
43037 +
43038 +                               if ((Ctrl) && (pLETab->Bmu.RxTx.TcpWp != TcpSumWrite)) {
43039 +                                       /* Update the last value of the write position */
43040 +                                       pLETab->Bmu.RxTx.TcpWp = TcpSumWrite;
43041 +
43042 +                                       /* Set the Lock field for this LE: */
43043 +                                       /* Checksum calculation for one packet only */
43044 +                                       TXLE_SET_LCKCS(pLE, 1);
43045 +
43046 +                                       /* Set the start position for checksum. */
43047 +                                       TXLE_SET_STACS(pLE, TcpSumStart);
43048 +
43049 +                                       /* Set the position where the checksum will be writen */
43050 +                                       TXLE_SET_WRICS(pLE, TcpSumWrite);
43051 +
43052 +                                       /* Set the initial value for checksum */
43053 +                                       /* PseudoHeader CS passed from Linux -> 0! */
43054 +                                       TXLE_SET_INICS(pLE, 0);
43055 +
43056 +                                       /* Set the opcode for tcp checksum */
43057 +                                       TXLE_SET_OPC(pLE, OP_TCPLISW | HW_OWNER);
43058 +
43059 +                                       /* Flush the LE to memory */
43060 +                                       FLUSH_OPC(pLE);
43061 +
43062 +                                       /* get a new LE because we filled one with data for checksum */
43063 +                                       GET_TX_LE(pLE, pLETab);
43064 +                               }
43065 +                       } /* end TCP offload handling */
43066 +
43067 +                       TXLE_SET_ADDR(pLE, LowAddress);
43068 +                       TXLE_SET_LEN(pLE, pFrag->FragLen);
43069 +
43070 +                       if (SetOpcodePacketFlag){
43071 +#ifdef NETIF_F_TSO
43072 +                               if (Mss) {
43073 +                                       OpCode = OP_LARGESEND | HW_OWNER;
43074 +                               } else {
43075 +#endif
43076 +                                       OpCode = OP_PACKET| HW_OWNER;
43077 +#ifdef NETIF_F_TSO
43078 +                               }
43079 +#endif
43080 +                               SetOpcodePacketFlag = SK_FALSE;
43081 +                       } else {
43082 +                               /* Follow packet in a sequence has always OP_BUFFER */
43083 +                               OpCode = OP_BUFFER | HW_OWNER;
43084 +                       }
43085 +
43086 +                       /* Check if the low address is near the upper limit. */
43087 +                       CHECK_LOW_ADDRESS(pLETab->BufHighAddr, LowAddress, pFrag->FragLen);
43088 +
43089 +                       pFrag = pFrag->pNext;
43090 +                       if (pFrag == NULL) {
43091 +                               /* mark last fragment */
43092 +                               Ctrl |= EOP;
43093 +                       }
43094 +                       TXLE_SET_CTRL(pLE, Ctrl);
43095 +                       TXLE_SET_OPC(pLE, OpCode);
43096 +                       FLUSH_OPC(pLE);
43097 +
43098 +                       SK_DBG_DUMP_TX_LE(pLE);
43099 +               }
43100 +
43101 +               /*
43102 +               ** Remember next LE for tx complete
43103 +               */
43104 +               pSkPacket->NextLE = GET_PUT_IDX(pLETab);
43105 +               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43106 +                       ("\tNext LE for pkt %p is %d\n", pSkPacket, pSkPacket->NextLE));
43107 +
43108 +               /*
43109 +               ** Add packet to working packets queue
43110 +               */
43111 +               PUSH_PKT_AS_LAST_IN_QUEUE(pWorkQueue, pSkPacket);
43112 +
43113 +               /*
43114 +               ** give transmit start command
43115 +               */
43116 +               if (HW_FEATURE(pAC, HWF_WA_DEV_42)) {
43117 +                       spin_lock(&pAC->SetPutIndexLock);
43118 +                       SkGeY2SetPutIndex(pAC, pAC->IoBase, Y2_PREF_Q_ADDR(Q_XA1,0), &pAC->TxPort[0][0].TxALET);
43119 +                       spin_unlock(&pAC->SetPutIndexLock);
43120 +               } else {
43121 +                       /* write put index */
43122 +                       if (Port == 0) {
43123 +                               SK_OUT32(pAC->IoBase,
43124 +                                       Y2_PREF_Q_ADDR(Q_XA1,PREF_UNIT_PUT_IDX_REG),
43125 +                                       GET_PUT_IDX(&pAC->TxPort[0][0].TxALET));
43126 +                               UPDATE_HWPUT_IDX(&pAC->TxPort[0][0].TxALET);
43127 +                       } else {
43128 +                               SK_OUT32(pAC->IoBase,
43129 +                                       Y2_PREF_Q_ADDR(Q_XA2, PREF_UNIT_PUT_IDX_REG),
43130 +                                       GET_PUT_IDX(&pAC->TxPort[1][0].TxALET));
43131 +                               UPDATE_HWPUT_IDX(&pAC->TxPort[1][0].TxALET);
43132 +                       }
43133 +               }
43134 +
43135 +               if (IS_Q_EMPTY(&(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting))) {
43136 +                       break; /* get out of while */
43137 +               }
43138 +               POP_FIRST_PKT_FROM_QUEUE(pWaitQueue, pSkPacket);
43139 +       } /* while (pSkPacket != NULL) */
43140 +
43141 +       spin_unlock_irqrestore(&pAC->TxQueueLock, LockFlag);
43142 +
43143 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43144 +               ("<== GiveTxBufferToHw\n"));
43145 +       return;
43146 +}      /* GiveTxBufferToHw */
43147 +
43148 +/***********************************************************************
43149 + *
43150 + *     GiveRxBufferToHw - commits a previously allocated DMA area to HW
43151 + *
43152 + * Description:
43153 + *     This functions gives receive buffers to HW. If no list elements
43154 + *     are available the buffers will be queued.
43155 + *
43156 + * Notes:
43157 + *       This function can run only once in a system at one time.
43158 + *
43159 + * Returns: N/A
43160 + */
43161 +static void GiveRxBufferToHw(
43162 +SK_AC      *pAC,      /* pointer to adapter control context         */
43163 +SK_IOC      IoC,      /* I/O control context (address of registers) */
43164 +int         Port,     /* port index for which the buffer is used    */
43165 +SK_PACKET  *pPacket)  /* receive buffer(s)                          */
43166 +{
43167 +       SK_HWLE         *pLE;
43168 +       SK_LE_TABLE     *pLETab;
43169 +       SK_BOOL         Done = SK_FALSE;  /* at least on LE changed? */
43170 +       SK_U32          LowAddress;
43171 +       SK_U32          HighAddress;
43172 +       SK_U32          PrefetchReg;      /* register for Put index  */
43173 +       unsigned        NumFree;
43174 +       unsigned        Required;
43175 +       unsigned long   Flags;
43176 +
43177 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43178 +       ("==> GiveRxBufferToHw(Port %c, Packet %p)\n", 'A' + Port, pPacket));
43179 +
43180 +       pLETab  = &pAC->RxPort[Port].RxLET;
43181 +
43182 +       if (Port == 0) {
43183 +               PrefetchReg = Y2_PREF_Q_ADDR(Q_R1, PREF_UNIT_PUT_IDX_REG);
43184 +       } else {
43185 +               PrefetchReg = Y2_PREF_Q_ADDR(Q_R2, PREF_UNIT_PUT_IDX_REG);
43186 +       }
43187 +
43188 +       if (pPacket != NULL) {
43189 +               /*
43190 +               ** For the time being, we have only one packet passed
43191 +               ** to this function which might be changed in future!
43192 +               */
43193 +               PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket);
43194 +       }
43195 +
43196 +       /*
43197 +       ** now pPacket contains the very first waiting packet
43198 +       */
43199 +       POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket);
43200 +       while (pPacket != NULL) {
43201 +               if (HW_FEATURE(pAC, HWF_WA_DEV_420)) {
43202 +                       if (NbrRxBuffersInHW >= MAX_NBR_RX_BUFFERS_IN_HW) {
43203 +                               PUSH_PKT_AS_FIRST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket);
43204 +                               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43205 +                                       ("<== GiveRxBufferToHw()\n"));
43206 +                               return;
43207 +                       }
43208 +                       NbrRxBuffersInHW++;
43209 +               }
43210 +
43211 +               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43212 +                       ("Try to add packet %p\n", pPacket));
43213 +
43214 +               /*
43215 +               ** Check whether we have enough listelements:
43216 +               **
43217 +               ** we have to take into account that each fragment
43218 +               ** may need an additional list element for the high
43219 +               ** part of the address here I simplified it by
43220 +               ** using MAX_FRAG_OVERHEAD maybe it's worth to split
43221 +               ** this constant for Rx and Tx or to calculate the
43222 +               ** real number of needed LE's
43223 +               */
43224 +               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43225 +                       ("\tNum %d Put %d Done %d Free %d %d\n",
43226 +                       pLETab->Num, pLETab->Put, pLETab->Done,
43227 +                       NUM_FREE_LE_IN_TABLE(pLETab),
43228 +                       (NUM_FREE_LE_IN_TABLE(pLETab))));
43229 +
43230 +               Required = pPacket->NumFrags + MAX_FRAG_OVERHEAD;
43231 +               NumFree = NUM_FREE_LE_IN_TABLE(pLETab);
43232 +               if (NumFree) {
43233 +                       NumFree--;
43234 +               }
43235 +
43236 +               if (Required > NumFree ) {
43237 +                       SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
43238 +                               SK_DBGCAT_DRV_RX_PROGRESS | SK_DBGCAT_DRV_ERROR,
43239 +                               ("\tOut of LEs have %d need %d\n",
43240 +                               NumFree, Required));
43241 +
43242 +                       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43243 +                               ("\tWaitQueue starts with packet %p\n", pPacket));
43244 +                       PUSH_PKT_AS_FIRST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket);
43245 +                       if (Done) {
43246 +                               /*
43247 +                               ** write Put index to BMU or Polling Unit and make the LE's
43248 +                               ** available for the hardware
43249 +                               */
43250 +                               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43251 +                                       ("\tWrite new Put Idx\n"));
43252 +
43253 +                               SK_OUT32(IoC, PrefetchReg, GET_PUT_IDX(pLETab));
43254 +                               UPDATE_HWPUT_IDX(pLETab);
43255 +                       }
43256 +                       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43257 +                               ("<== GiveRxBufferToHw()\n"));
43258 +                       return;
43259 +               } else {
43260 +                       if (!AllocAndMapRxBuffer(pAC, pPacket, Port)) {
43261 +                               /*
43262 +                               ** Failure while allocating sk_buff might
43263 +                               ** be due to temporary short of resources
43264 +                               ** Maybe next time buffers are available.
43265 +                               ** Until this, the packet remains in the
43266 +                               ** RX waiting queue...
43267 +                               */
43268 +                               SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
43269 +                                       SK_DBGCAT_DRV_RX_PROGRESS | SK_DBGCAT_DRV_ERROR,
43270 +                                       ("Failed to allocate Rx buffer\n"));
43271 +
43272 +                               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43273 +                                       ("WaitQueue starts with packet %p\n", pPacket));
43274 +                               PUSH_PKT_AS_FIRST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket);
43275 +                               if (Done) {
43276 +                                       /*
43277 +                                       ** write Put index to BMU or Polling
43278 +                                       ** Unit and make the LE's
43279 +                                       ** available for the hardware
43280 +                                       */
43281 +                                       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43282 +                                               ("\tWrite new Put Idx\n"));
43283 +
43284 +                                       SK_OUT32(IoC, PrefetchReg, GET_PUT_IDX(pLETab));
43285 +                                       UPDATE_HWPUT_IDX(pLETab);
43286 +                               }
43287 +                               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43288 +                                       ("<== GiveRxBufferToHw()\n"));
43289 +                               return;
43290 +                       }
43291 +               }
43292 +               Done = SK_TRUE;
43293 +
43294 +               LowAddress = (SK_U32) (pPacket->pFrag->pPhys & 0xffffffff);
43295 +               HighAddress = (SK_U32) (pPacket->pFrag->pPhys >> 32);
43296 +               if (HighAddress != pLETab->BufHighAddr) {
43297 +                       /* get a new LE for high address */
43298 +                       GET_RX_LE(pLE, pLETab);
43299 +
43300 +                       /* Set now the 32 high bits of the address */
43301 +                       RXLE_SET_ADDR(pLE, HighAddress);
43302 +
43303 +                       /* Set the control bits of the address */
43304 +                       RXLE_SET_CTRL(pLE, 0);
43305 +
43306 +                       /* Set the opcode into the LE */
43307 +                       RXLE_SET_OPC(pLE, (OP_ADDR64 | HW_OWNER));
43308 +
43309 +                       /* Flush the LE to memory */
43310 +                       FLUSH_OPC(pLE);
43311 +
43312 +                       /* remember the HighAddress we gave to the Hardware */
43313 +                       pLETab->BufHighAddr = HighAddress;
43314 +               }
43315 +
43316 +               /*
43317 +               ** Fill data into listelement
43318 +               */
43319 +               GET_RX_LE(pLE, pLETab);
43320 +               RXLE_SET_ADDR(pLE, LowAddress);
43321 +               RXLE_SET_LEN(pLE, pPacket->pFrag->FragLen);
43322 +               RXLE_SET_CTRL(pLE, 0);
43323 +               RXLE_SET_OPC(pLE, (OP_PACKET | HW_OWNER));
43324 +               FLUSH_OPC(pLE);
43325 +
43326 +               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43327 +                       ("=== LE filled\n"));
43328 +
43329 +               SK_DBG_DUMP_RX_LE(pLE);
43330 +
43331 +               /*
43332 +               ** Remember next LE for rx complete
43333 +               */
43334 +               pPacket->NextLE = GET_PUT_IDX(pLETab);
43335 +
43336 +               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43337 +                       ("\tPackets Next LE is %d\n", pPacket->NextLE));
43338 +
43339 +               /*
43340 +               ** Add packet to working receive buffer queue and get
43341 +               ** any next packet out of the waiting queue
43342 +               */
43343 +               PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_working, pPacket);
43344 +               if (IS_Q_EMPTY(&(pAC->RxPort[Port].RxQ_waiting))) {
43345 +                       break; /* get out of while processing */
43346 +               }
43347 +               POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket);
43348 +       }
43349 +
43350 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43351 +               ("\tWaitQueue is empty\n"));
43352 +
43353 +       if (Done) {
43354 +               /*
43355 +               ** write Put index to BMU or Polling Unit and make the LE's
43356 +               ** available for the hardware
43357 +               */
43358 +               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43359 +                       ("\tWrite new Put Idx\n"));
43360 +
43361 +               /* Speed enhancement for a2 chipsets */
43362 +               if (HW_FEATURE(pAC, HWF_WA_DEV_42)) {
43363 +                       spin_lock_irqsave(&pAC->SetPutIndexLock, Flags);
43364 +                       SkGeY2SetPutIndex(pAC, pAC->IoBase, Y2_PREF_Q_ADDR(Q_R1,0), pLETab);
43365 +                       spin_unlock_irqrestore(&pAC->SetPutIndexLock, Flags);
43366 +               } else {
43367 +                       /* write put index */
43368 +                       if (Port == 0) {
43369 +                               SK_OUT32(IoC,
43370 +                                       Y2_PREF_Q_ADDR(Q_R1, PREF_UNIT_PUT_IDX_REG),
43371 +                                       GET_PUT_IDX(pLETab));
43372 +                       } else {
43373 +                               SK_OUT32(IoC,
43374 +                                       Y2_PREF_Q_ADDR(Q_R2, PREF_UNIT_PUT_IDX_REG),
43375 +                                       GET_PUT_IDX(pLETab));
43376 +                       }
43377 +
43378 +                       /* Update put index */
43379 +                       UPDATE_HWPUT_IDX(pLETab);
43380 +               }
43381 +       }
43382 +
43383 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43384 +               ("<== GiveRxBufferToHw()\n"));
43385 +}       /* GiveRxBufferToHw */
43386 +
43387 +/***********************************************************************
43388 + *
43389 + *     FillReceiveTableYukon2 - map any waiting RX buffers to HW
43390 + *
43391 + * Description:
43392 + *     If the list element table contains more empty elements than
43393 + *     specified this function tries to refill them.
43394 + *
43395 + * Notes:
43396 + *       This function can run only once per port in a system at one time.
43397 + *
43398 + * Returns: N/A
43399 + */
43400 +void FillReceiveTableYukon2(
43401 +SK_AC   *pAC,   /* pointer to adapter control context */
43402 +SK_IOC   IoC,   /* I/O control context                */
43403 +int      Port)  /* port index of RX                   */
43404 +{
43405 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43406 +               ("==> FillReceiveTableYukon2 (Port %c)\n", 'A' + Port));
43407 +
43408 +       if (NUM_FREE_LE_IN_TABLE(&pAC->RxPort[Port].RxLET) >
43409 +               pAC->MaxUnusedRxLeWorking) {
43410 +
43411 +               /*
43412 +               ** Give alle waiting receive buffers down
43413 +               ** The queue holds all RX packets that
43414 +               ** need a fresh allocation of the sk_buff.
43415 +               */
43416 +               if (pAC->RxPort[Port].RxQ_waiting.pHead != NULL) {
43417 +                       SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43418 +                       ("Waiting queue is not empty -> give it to HW"));
43419 +                       GiveRxBufferToHw(pAC, IoC, Port, NULL);
43420 +               }
43421 +       }
43422 +
43423 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43424 +               ("<== FillReceiveTableYukon2 ()\n"));
43425 +}      /* FillReceiveTableYukon2 */
43426 +
43427 +/******************************************************************************
43428 + *
43429 + *
43430 + *     HandleReceives - will pass any ready RX packet to kernel
43431 + *
43432 + * Description:
43433 + *     This functions handles a received packet. It checks wether it is
43434 + *     valid, updates the receive list element table and gives the receive
43435 + *     buffer to Linux
43436 + *
43437 + * Notes:
43438 + *     This function can run only once per port at one time in the system.
43439 + *
43440 + * Returns: N/A
43441 + */
43442 +static SK_BOOL HandleReceives(
43443 +SK_AC  *pAC,          /* adapter control context                     */
43444 +int     Port,         /* port on which a packet has been received    */
43445 +SK_U16  Len,          /* number of bytes which was actually received */
43446 +SK_U32  FrameStatus,  /* MAC frame status word                       */
43447 +SK_U16  Tcp1,         /* first hw checksum                           */
43448 +SK_U16  Tcp2,         /* second hw checksum                          */
43449 +SK_U32  Tist,         /* timestamp                                   */
43450 +SK_U16  Vlan)         /* Vlan Id                                     */
43451 +{
43452 +
43453 +       SK_PACKET       *pSkPacket;
43454 +       SK_LE_TABLE     *pLETab;
43455 +       SK_MBUF         *pRlmtMbuf;  /* buffer for giving RLMT frame */
43456 +       struct sk_buff  *pMsg;       /* ptr to message holding frame */
43457 +#ifdef __ia64__
43458 +       struct sk_buff  *pNewMsg;    /* used when IP aligning        */
43459 +#endif
43460 +
43461 +       SK_BOOL         IsGoodPkt;
43462 +       SK_BOOL         IsBc;
43463 +       SK_BOOL         IsMc;
43464 +       SK_EVPARA       EvPara;      /* an event parameter union     */
43465 +       SK_I16          LenToFree;   /* must be signed integer       */
43466 +
43467 +       unsigned long   Flags;       /* for spin lock                */
43468 +       unsigned int    RlmtNotifier;
43469 +       unsigned short  Type;
43470 +       int             IpFrameLength;
43471 +       int             FrameLength; /* total length of recvd frame  */
43472 +       int             HeaderLength;
43473 +       int             NumBytes;
43474 +       int             Result;
43475 +       int             Offset = 0;
43476 +
43477 +#ifdef Y2_SYNC_CHECK
43478 +       SK_U16          MyTcp;
43479 +#endif
43480 +
43481 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43482 +               ("==> HandleReceives (Port %c)\n", 'A' + Port));
43483 +
43484 +       /*
43485 +       ** initialize vars for selected port
43486 +       */
43487 +       pLETab = &pAC->RxPort[Port].RxLET;
43488 +
43489 +       /*
43490 +       ** check whether we want to receive this packet
43491 +       */
43492 +       SK_Y2_RXSTAT_CHECK_PKT(Len, FrameStatus, IsGoodPkt);
43493 +
43494 +       /*
43495 +       ** Remember length to free (in case of RxBuffer overruns;
43496 +       ** unlikely, but might happen once in a while)
43497 +       */
43498 +       LenToFree = (SK_I16) Len;
43499 +
43500 +       /*
43501 +       ** maybe we put these two checks into the SK_RXDESC_CHECK_PKT macro too
43502 +       */
43503 +       if (Len > pAC->RxPort[Port].RxBufSize) {
43504 +               IsGoodPkt = SK_FALSE;
43505 +       }
43506 +
43507 +       /*
43508 +       ** take first receive buffer out of working queue
43509 +       */
43510 +       POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_working, pSkPacket);
43511 +       if (pSkPacket == NULL) {
43512 +               SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
43513 +                       SK_DBGCAT_DRV_ERROR,
43514 +                       ("Packet not available. NULL pointer.\n"));
43515 +               return(SK_TRUE);
43516 +       }
43517 +
43518 +       if (HW_FEATURE(pAC, HWF_WA_DEV_420)) {
43519 +               NbrRxBuffersInHW--;
43520 +       }
43521 +
43522 +       /*
43523 +       ** Verify the received length of the frame! Note that having
43524 +       ** multiple RxBuffers being aware of one single receive packet
43525 +       ** (one packet spread over multiple RxBuffers) is not supported
43526 +       ** by this driver!
43527 +       */
43528 +       if ((Len > pAC->RxPort[Port].RxBufSize) ||
43529 +               (Len > (SK_U16) pSkPacket->PacketLen)) {
43530 +               IsGoodPkt = SK_FALSE;
43531 +       }
43532 +
43533 +       /*
43534 +       ** Reset own bit in LE's between old and new Done index
43535 +       ** This is not really necessary but makes debugging easier
43536 +       */
43537 +       CLEAR_LE_OWN_FROM_DONE_TO(pLETab, pSkPacket->NextLE);
43538 +
43539 +       /*
43540 +       ** Free the list elements for new Rx buffers
43541 +       */
43542 +       SET_DONE_INDEX(pLETab, pSkPacket->NextLE);
43543 +       pMsg = pSkPacket->pMBuf;
43544 +       FrameLength = Len;
43545 +
43546 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43547 +               ("Received frame of length %d on port %d\n",FrameLength, Port));
43548 +
43549 +       if (!IsGoodPkt) {
43550 +               /*
43551 +               ** release the DMA mapping
43552 +               */
43553 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5)
43554 +               pci_dma_sync_single(pAC->PciDev,
43555 +                               (dma_addr_t) pSkPacket->pFrag->pPhys,
43556 +                               pSkPacket->pFrag->FragLen,
43557 +                               PCI_DMA_FROMDEVICE);
43558 +
43559 +#else
43560 +               pci_dma_sync_single_for_cpu(pAC->PciDev,
43561 +                               (dma_addr_t) pSkPacket->pFrag->pPhys,
43562 +                               pSkPacket->pFrag->FragLen,
43563 +                               PCI_DMA_FROMDEVICE);
43564 +#endif
43565 +
43566 +               DEV_KFREE_SKB_ANY(pSkPacket->pMBuf);
43567 +               PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pSkPacket);
43568 +               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43569 +                       ("<== HandleReceives (Port %c)\n", 'A' + Port));
43570 +
43571 +               /*
43572 +               ** Sanity check for RxBuffer overruns...
43573 +               */
43574 +               LenToFree = LenToFree - (pSkPacket->pFrag->FragLen);
43575 +               while (LenToFree > 0) {
43576 +                       POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_working, pSkPacket);
43577 +                       if (HW_FEATURE(pAC, HWF_WA_DEV_420)) {
43578 +                               NbrRxBuffersInHW--;
43579 +                       }
43580 +                       CLEAR_LE_OWN_FROM_DONE_TO(pLETab, pSkPacket->NextLE);
43581 +                       SET_DONE_INDEX(pLETab, pSkPacket->NextLE);
43582 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5)
43583 +                       pci_dma_sync_single(pAC->PciDev,
43584 +                                       (dma_addr_t) pSkPacket->pFrag->pPhys,
43585 +                                       pSkPacket->pFrag->FragLen,
43586 +                                       PCI_DMA_FROMDEVICE);
43587 +#else
43588 +                       pci_dma_sync_single_for_device(pAC->PciDev,
43589 +                                       (dma_addr_t) pSkPacket->pFrag->pPhys,
43590 +                                       pSkPacket->pFrag->FragLen,
43591 +                                       PCI_DMA_FROMDEVICE);
43592 +#endif
43593 +
43594 +                       DEV_KFREE_SKB_ANY(pSkPacket->pMBuf);
43595 +                       PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pSkPacket);
43596 +                       LenToFree = LenToFree - ((SK_I16)(pSkPacket->pFrag->FragLen));
43597 +
43598 +                       SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
43599 +                               SK_DBGCAT_DRV_RX_PROGRESS | SK_DBGCAT_DRV_ERROR,
43600 +                               ("<==HandleReceives (Port %c) drop faulty len pkt(2)\n",'A'+Port));
43601 +               }
43602 +               return(SK_TRUE);
43603 +       } else {
43604 +               /*
43605 +               ** Release the DMA mapping
43606 +               */
43607 +               pci_unmap_single(pAC->PciDev,
43608 +                                pSkPacket->pFrag->pPhys,
43609 +                                pAC->RxPort[Port].RxBufSize,
43610 +                                PCI_DMA_FROMDEVICE);
43611 +
43612 +               skb_put(pMsg, FrameLength);             /* set message len */
43613 +               pMsg->ip_summed = CHECKSUM_NONE;        /* initial default */
43614 +
43615 +#ifdef Y2_SYNC_CHECK
43616 +               pAC->FramesWithoutSyncCheck++;
43617 +               if (pAC->FramesWithoutSyncCheck > Y2_RESYNC_WATERMARK) {
43618 +                       if ((Tcp1 != 1) || (Tcp2 != 0)) {
43619 +                               pAC->FramesWithoutSyncCheck = 0;
43620 +                               MyTcp = (SK_U16) SkCsCalculateChecksum(
43621 +                                               &pMsg->data[14],
43622 +                                               FrameLength - 14);
43623 +                               if (MyTcp != Tcp1) {
43624 +                                       /* Queue port reset event */
43625 +                                       SkLocalEventQueue(pAC, SKGE_DRV,
43626 +                                       SK_DRV_RECOVER,Port,-1,SK_FALSE);
43627 +                               }
43628 +                       }
43629 +               }
43630 +#endif
43631 +
43632 +               if (pAC->RxPort[Port].UseRxCsum) {
43633 +                       Type = ntohs(*((short*)&pMsg->data[12]));
43634 +                       if (Type == 0x800) {
43635 +                               *((char *)&(IpFrameLength)) = pMsg->data[16];
43636 +                               *(((char *)&(IpFrameLength))+1) = pMsg->data[17];
43637 +                               IpFrameLength = ntohs(IpFrameLength);
43638 +                               HeaderLength  = FrameLength - IpFrameLength;
43639 +                               if (HeaderLength == 0xe) {
43640 +                                       Result =
43641 +                                           SkCsGetReceiveInfo(pAC,&pMsg->data[14],Tcp1,Tcp2, Port);
43642 +                                       if ((Result == SKCS_STATUS_IP_FRAGMENT) ||
43643 +                                           (Result == SKCS_STATUS_IP_CSUM_OK)  ||
43644 +                                           (Result == SKCS_STATUS_TCP_CSUM_OK) ||
43645 +                                           (Result == SKCS_STATUS_UDP_CSUM_OK)) {
43646 +                                               pMsg->ip_summed = CHECKSUM_UNNECESSARY;
43647 +                                       } else if ((Result == SKCS_STATUS_TCP_CSUM_ERROR)    ||
43648 +                                                  (Result == SKCS_STATUS_UDP_CSUM_ERROR)    ||
43649 +                                                  (Result == SKCS_STATUS_IP_CSUM_ERROR_UDP) ||
43650 +                                                  (Result == SKCS_STATUS_IP_CSUM_ERROR_TCP) ||
43651 +                                                  (Result == SKCS_STATUS_IP_CSUM_ERROR)) {
43652 +                                               SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
43653 +                                                       SK_DBGCAT_DRV_RX_PROGRESS | SK_DBGCAT_DRV_ERROR,
43654 +                                                       ("skge: CRC error. Frame dropped!\n"));
43655 +                                               DEV_KFREE_SKB_ANY(pMsg);
43656 +                                               PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pSkPacket);
43657 +                                               SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_RX_PROGRESS,
43658 +                                                       ("<==HandleReceives(Port %c)\n",'A'+Port));
43659 +                                               return(SK_TRUE);
43660 +                                       } else {
43661 +                                               pMsg->ip_summed = CHECKSUM_NONE;
43662 +                                       }
43663 +                               } /* end if (HeaderLength == valid) */
43664 +                       } /* end if (Type == 0x800) -> IP frame */
43665 +               } /* end if (pRxPort->UseRxCsum) */
43666 +
43667 +               SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
43668 +                       SK_DBGCAT_DRV_RX_PROGRESS,("V"));
43669 +               RlmtNotifier = SK_RLMT_RX_PROTOCOL;
43670 +
43671 +               IsBc = (FrameStatus & GMR_FS_BC) ? SK_TRUE : SK_FALSE;
43672 +               SK_RLMT_PRE_LOOKAHEAD(pAC,Port,FrameLength,
43673 +                                       IsBc,&Offset,&NumBytes);
43674 +               if (NumBytes != 0) {
43675 +                       IsMc = (FrameStatus & GMR_FS_MC) ? SK_TRUE : SK_FALSE;
43676 +                       SK_RLMT_LOOKAHEAD(pAC,Port,&pMsg->data[Offset],
43677 +                                               IsBc,IsMc,&RlmtNotifier);
43678 +               }
43679 +
43680 +               if (RlmtNotifier == SK_RLMT_RX_PROTOCOL) {
43681 +                       SK_DBG_MSG(NULL,SK_DBGMOD_DRV,
43682 +                               SK_DBGCAT_DRV_RX_PROGRESS,("W"));
43683 +                       if ((Port == pAC->ActivePort)||(pAC->RlmtNets == 2)) {
43684 +                               /* send up only frames from active port */
43685 +                               SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
43686 +                                       SK_DBGCAT_DRV_RX_PROGRESS,("U"));
43687 +#ifdef xDEBUG
43688 +                               DumpMsg(pMsg, "Rx");
43689 +#endif
43690 +                               SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC,
43691 +                                       FrameLength, Port);
43692 +#ifdef __ia64__
43693 +                               pNewMsg = alloc_skb(pMsg->len, GFP_ATOMIC);
43694 +                               skb_reserve(pNewMsg, 2); /* to align IP */
43695 +                               SK_MEMCPY(pNewMsg->data,pMsg->data,pMsg->len);
43696 +                               pNewMsg->ip_summed = pMsg->ip_summed;
43697 +                               skb_put(pNewMsg, pMsg->len);
43698 +                               DEV_KFREE_SKB_ANY(pMsg);
43699 +                               pMsg = pNewMsg;
43700 +#endif
43701 +                               pMsg->dev = pAC->dev[Port];
43702 +                               pMsg->protocol = eth_type_trans(pMsg,
43703 +                                       pAC->dev[Port]);
43704 +#ifdef CONFIG_SK98LIN_NAPI
43705 +                               netif_receive_skb(pMsg);
43706 +#else
43707 +                               netif_rx(pMsg);
43708 +#endif
43709 +                               pAC->dev[Port]->last_rx = jiffies;
43710 +                       } else { /* drop frame */
43711 +                               SK_DBG_MSG(NULL,SK_DBGMOD_DRV,
43712 +                                       SK_DBGCAT_DRV_RX_PROGRESS,("D"));
43713 +                               DEV_KFREE_SKB_ANY(pMsg);
43714 +                       }
43715 +               } else { /* This is an RLMT-packet! */
43716 +                       SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
43717 +                               SK_DBGCAT_DRV_RX_PROGRESS,("R"));
43718 +                       pRlmtMbuf = SkDrvAllocRlmtMbuf(pAC,
43719 +                               pAC->IoBase, FrameLength);
43720 +                       if (pRlmtMbuf != NULL) {
43721 +                               pRlmtMbuf->pNext = NULL;
43722 +                               pRlmtMbuf->Length = FrameLength;
43723 +                               pRlmtMbuf->PortIdx = Port;
43724 +                               EvPara.pParaPtr = pRlmtMbuf;
43725 +                               SK_MEMCPY((char*)(pRlmtMbuf->pData),
43726 +                                         (char*)(pMsg->data),FrameLength);
43727 +
43728 +#ifdef CONFIG_SK98LIN_NAPI
43729 +                               spin_lock_irqsave(&pAC->SlowPathLock, Flags);
43730 +#endif
43731 +                               SkEventQueue(pAC, SKGE_RLMT,
43732 +                                               SK_RLMT_PACKET_RECEIVED,
43733 +                                               EvPara);
43734 +                               pAC->CheckQueue = SK_TRUE;
43735 +#ifdef CONFIG_SK98LIN_NAPI
43736 +                               spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
43737 +#endif
43738 +                               SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
43739 +                                       SK_DBGCAT_DRV_RX_PROGRESS,("Q"));
43740 +                       }
43741 +                       if (pAC->dev[Port]->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
43742 +#ifdef __ia64__
43743 +                               pNewMsg = alloc_skb(pMsg->len, GFP_ATOMIC);
43744 +                               skb_reserve(pNewMsg, 2); /* to align IP */
43745 +                               SK_MEMCPY(pNewMsg->data,pMsg->data,pMsg->len);
43746 +                               pNewMsg->ip_summed = pMsg->ip_summed;
43747 +                               pNewMsg->len = pMsg->len;
43748 +                               DEV_KFREE_SKB_ANY(pMsg);
43749 +                               pMsg = pNewMsg;
43750 +#endif
43751 +                               pMsg->dev = pAC->dev[Port];
43752 +                               pMsg->protocol = eth_type_trans(pMsg,pAC->dev[Port]);
43753 +                               netif_rx(pMsg);
43754 +                               pAC->dev[Port]->last_rx = jiffies;
43755 +                       } else {
43756 +                               DEV_KFREE_SKB_ANY(pMsg);
43757 +                       }
43758 +               } /* if packet for rlmt */
43759 +               PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pSkPacket);
43760 +       } /* end if-else (IsGoodPkt) */
43761 +
43762 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43763 +               ("<== HandleReceives (Port %c)\n", 'A' + Port));
43764 +       return(SK_TRUE);
43765 +
43766 +}      /* HandleReceives */
43767 +
43768 +/***********************************************************************
43769 + *
43770 + *     CheckForSendComplete - Frees any freeable Tx bufffer
43771 + *
43772 + * Description:
43773 + *     This function checks the queues of a port for completed send
43774 + *     packets and returns these packets back to the OS.
43775 + *
43776 + * Notes:
43777 + *     This function can run simultaneously for both ports if
43778 + *     the OS function OSReturnPacket() can handle this,
43779 + *
43780 + *     Such a send complete does not mean, that the packet is really
43781 + *     out on the wire. We just know that the adapter has copied it
43782 + *     into its internal memory and the buffer in the systems memory
43783 + *     is no longer needed.
43784 + *
43785 + * Returns: N/A
43786 + */
43787 +static void CheckForSendComplete(
43788 +SK_AC         *pAC,     /* pointer to adapter control context  */
43789 +SK_IOC         IoC,     /* I/O control context                 */
43790 +int            Port,    /* port index                          */
43791 +SK_PKT_QUEUE  *pPQ,     /* tx working packet queue to check    */
43792 +SK_LE_TABLE   *pLETab,  /* corresponding list element table    */
43793 +unsigned int   Done)    /* done index reported for this LET    */
43794 +{
43795 +       SK_PACKET       *pSkPacket;
43796 +       SK_PKT_QUEUE     SendCmplPktQ = { NULL, NULL, SPIN_LOCK_UNLOCKED };
43797 +       SK_BOOL          DoWakeQueue  = SK_FALSE;
43798 +       unsigned long    Flags;
43799 +       unsigned         Put;
43800 +
43801 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43802 +               ("==> CheckForSendComplete(Port %c)\n", 'A' + Port));
43803 +
43804 +       /*
43805 +       ** Reset own bit in LE's between old and new Done index
43806 +       ** This is not really necessairy but makes debugging easier
43807 +       */
43808 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43809 +               ("Clear Own Bits in TxTable from %d to %d\n",
43810 +               pLETab->Done, (Done == 0) ?
43811 +               NUM_LE_IN_TABLE(pLETab) :
43812 +               (Done - 1)));
43813 +
43814 +       spin_lock_irqsave(&(pPQ->QueueLock), Flags);
43815 +
43816 +       CLEAR_LE_OWN_FROM_DONE_TO(pLETab, Done);
43817 +
43818 +       Put = GET_PUT_IDX(pLETab);
43819 +
43820 +       /*
43821 +       ** Check whether some packets have been completed
43822 +       */
43823 +       PLAIN_POP_FIRST_PKT_FROM_QUEUE(pPQ, pSkPacket);
43824 +       while (pSkPacket != NULL) {
43825 +
43826 +               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43827 +                       ("Check Completion of Tx packet %p\n", pSkPacket));
43828 +               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43829 +                       ("Put %d NewDone %d NextLe of Packet %d\n", Put, Done,
43830 +                       pSkPacket->NextLE));
43831 +
43832 +               if ((Put > Done) &&
43833 +                       ((pSkPacket->NextLE > Put) || (pSkPacket->NextLE <= Done))) {
43834 +                       PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(&SendCmplPktQ, pSkPacket);
43835 +                       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43836 +                               ("Packet finished (a)\n"));
43837 +               } else if ((Done > Put) &&
43838 +                       (pSkPacket->NextLE > Put) && (pSkPacket->NextLE <= Done)) {
43839 +                       PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(&SendCmplPktQ, pSkPacket);
43840 +                       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43841 +                               ("Packet finished (b)\n"));
43842 +               } else if ((Done == TXA_MAX_LE-1) && (Put == 0) && (pSkPacket->NextLE == 0)) {
43843 +                       PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(&SendCmplPktQ, pSkPacket);
43844 +                       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43845 +                               ("Packet finished (b)\n"));
43846 +                       DoWakeQueue = SK_TRUE;
43847 +               } else if (Done == Put) {
43848 +                       /* all packets have been sent */
43849 +                       PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(&SendCmplPktQ, pSkPacket);
43850 +                       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43851 +                               ("Packet finished (c)\n"));
43852 +               } else {
43853 +                       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43854 +                               ("Packet not yet finished\n"));
43855 +                       PLAIN_PUSH_PKT_AS_FIRST_IN_QUEUE(pPQ, pSkPacket);
43856 +                       break;
43857 +               }
43858 +               PLAIN_POP_FIRST_PKT_FROM_QUEUE(pPQ, pSkPacket);
43859 +       }
43860 +       spin_unlock_irqrestore(&(pPQ->QueueLock), Flags);
43861 +
43862 +       /*
43863 +       ** Set new done index in list element table
43864 +       */
43865 +       SET_DONE_INDEX(pLETab, Done);
43866 +
43867 +       /*
43868 +       ** All TX packets that are send complete should be added to
43869 +       ** the free queue again for new sents to come
43870 +       */
43871 +       pSkPacket = SendCmplPktQ.pHead;
43872 +       while (pSkPacket != NULL) {
43873 +               while (pSkPacket->pFrag != NULL) {
43874 +                       pci_unmap_page(pAC->PciDev,
43875 +                                       (dma_addr_t) pSkPacket->pFrag->pPhys,
43876 +                                       pSkPacket->pFrag->FragLen,
43877 +                                       PCI_DMA_FROMDEVICE);
43878 +                       pSkPacket->pFrag = pSkPacket->pFrag->pNext;
43879 +               }
43880 +
43881 +               DEV_KFREE_SKB_ANY(pSkPacket->pMBuf);
43882 +               pSkPacket->pMBuf        = NULL;
43883 +               pSkPacket = pSkPacket->pNext; /* get next packet */
43884 +       }
43885 +
43886 +       /*
43887 +       ** Append the available TX packets back to free queue
43888 +       */
43889 +       if (SendCmplPktQ.pHead != NULL) {
43890 +               spin_lock_irqsave(&(pAC->TxPort[Port][0].TxQ_free.QueueLock), Flags);
43891 +               if (pAC->TxPort[Port][0].TxQ_free.pTail != NULL) {
43892 +                       pAC->TxPort[Port][0].TxQ_free.pTail->pNext = SendCmplPktQ.pHead;
43893 +                       pAC->TxPort[Port][0].TxQ_free.pTail        = SendCmplPktQ.pTail;
43894 +                       if (pAC->TxPort[Port][0].TxQ_free.pHead->pNext == NULL) {
43895 +                               netif_wake_queue(pAC->dev[Port]);
43896 +                       }
43897 +               } else {
43898 +                       pAC->TxPort[Port][0].TxQ_free.pHead = SendCmplPktQ.pHead;
43899 +                       pAC->TxPort[Port][0].TxQ_free.pTail = SendCmplPktQ.pTail;
43900 +                       netif_wake_queue(pAC->dev[Port]);
43901 +               }
43902 +               if (Done == Put) {
43903 +                       netif_wake_queue(pAC->dev[Port]);
43904 +               }
43905 +               if (DoWakeQueue) {
43906 +                       netif_wake_queue(pAC->dev[Port]);
43907 +                       DoWakeQueue = SK_FALSE;
43908 +               }
43909 +               spin_unlock_irqrestore(&pAC->TxPort[Port][0].TxQ_free.QueueLock, Flags);
43910 +       }
43911 +
43912 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43913 +               ("<== CheckForSendComplete()\n"));
43914 +
43915 +       return;
43916 +}      /* CheckForSendComplete */
43917 +
43918 +/*****************************************************************************
43919 + *
43920 + *     UnmapAndFreeTxPktBuffer
43921 + *
43922 + * Description:
43923 + *      This function free any allocated space of receive buffers
43924 + *
43925 + * Arguments:
43926 + *      pAC - A pointer to the adapter context struct.
43927 + *
43928 + */
43929 +static void UnmapAndFreeTxPktBuffer(
43930 +SK_AC       *pAC,       /* pointer to adapter context             */
43931 +SK_PACKET   *pSkPacket,        /* pointer to port struct of ring to fill */
43932 +int          TxPort)    /* TX port index                          */
43933 +{
43934 +       SK_FRAG  *pFrag = pSkPacket->pFrag;
43935 +
43936 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43937 +               ("--> UnmapAndFreeTxPktBuffer\n"));
43938 +
43939 +       while (pFrag != NULL) {
43940 +               pci_unmap_page(pAC->PciDev,
43941 +                               (dma_addr_t) pFrag->pPhys,
43942 +                               pFrag->FragLen,
43943 +                               PCI_DMA_FROMDEVICE);
43944 +               pFrag = pFrag->pNext;
43945 +       }
43946 +
43947 +       DEV_KFREE_SKB_ANY(pSkPacket->pMBuf);
43948 +       pSkPacket->pMBuf        = NULL;
43949 +
43950 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43951 +               ("<-- UnmapAndFreeTxPktBuffer\n"));
43952 +}
43953 +
43954 +/*****************************************************************************
43955 + *
43956 + *     HandleStatusLEs
43957 + *
43958 + * Description:
43959 + *     This function checks for any new status LEs that may have been
43960 +  *    received. Those status LEs may either be Rx or Tx ones.
43961 + *
43962 + * Returns:    N/A
43963 + */
43964 +static SK_BOOL HandleStatusLEs(
43965 +#ifdef CONFIG_SK98LIN_NAPI
43966 +SK_AC *pAC,       /* pointer to adapter context   */
43967 +int   *WorkDone,  /* Done counter needed for NAPI */
43968 +int    WorkToDo)  /* ToDo counter for NAPI        */
43969 +#else
43970 +SK_AC *pAC)       /* pointer to adapter context   */
43971 +#endif
43972 +{
43973 +       int       DoneTxA[SK_MAX_MACS];
43974 +       int       DoneTxS[SK_MAX_MACS];
43975 +       int       Port;
43976 +       SK_BOOL   handledStatLE = SK_FALSE;
43977 +       SK_BOOL   NewDone       = SK_FALSE;
43978 +       SK_HWLE  *pLE;
43979 +       SK_U16    HighVal;
43980 +       SK_U32    LowVal;
43981 +       SK_U8     OpCode;
43982 +       int       i;
43983 +
43984 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
43985 +               ("==> HandleStatusLEs\n"));
43986 +
43987 +       do {
43988 +               if (OWN_OF_FIRST_LE(&pAC->StatusLETable) != HW_OWNER)
43989 +                       break;
43990 +
43991 +               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
43992 +                       ("Check next Own Bit of ST-LE[%d]: 0x%li \n",
43993 +                       (pAC->StatusLETable.Done + 1) % NUM_LE_IN_TABLE(&pAC->StatusLETable),
43994 +                        OWN_OF_FIRST_LE(&pAC->StatusLETable)));
43995 +
43996 +               while (OWN_OF_FIRST_LE(&pAC->StatusLETable) == HW_OWNER) {
43997 +                       GET_ST_LE(pLE, &pAC->StatusLETable);
43998 +                       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
43999 +                               ("Working on finished status LE[%d]:\n",
44000 +                               GET_DONE_INDEX(&pAC->StatusLETable)));
44001 +                       SK_DBG_DUMP_ST_LE(pLE);
44002 +                       handledStatLE = SK_TRUE;
44003 +                       OpCode = STLE_GET_OPC(pLE) & ~HW_OWNER;
44004 +                       Port = STLE_GET_LINK(pLE);
44005 +
44006 +#ifdef USE_TIST_FOR_RESET
44007 +                       if (SK_ADAPTER_WAITING_FOR_TIST(pAC)) {
44008 +                               /* do we just have a tist LE ? */
44009 +                               if ((OpCode & OP_RXTIMESTAMP) == OP_RXTIMESTAMP) {
44010 +                                       for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
44011 +                                               if (SK_PORT_WAITING_FOR_ANY_TIST(pAC, i)) {
44012 +                                                       /* if a port is waiting for any tist it is done */
44013 +                                                       SK_CLR_STATE_FOR_PORT(pAC, i);
44014 +                                                       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
44015 +                                                               ("Got any Tist on port %c (now 0x%X!!!)\n",
44016 +                                                               'A' + i, pAC->AdapterResetState));
44017 +                                               }
44018 +                                               if (SK_PORT_WAITING_FOR_SPECIFIC_TIST(pAC, i)) {
44019 +                                                       Y2_GET_TIST_LOW_VAL(pAC->IoBase, &LowVal);
44020 +                                                       if ((pAC->MinTistHi != pAC->GIni.GITimeStampCnt) ||
44021 +                                                               (pAC->MinTistLo < LowVal)) {
44022 +                                                               /* time is up now */
44023 +                                                               SK_CLR_STATE_FOR_PORT(pAC, i);
44024 +                                                               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
44025 +                                                                       ("Got expected Tist on Port %c (now 0x%X)!!!\n",
44026 +                                                                       'A' + i, pAC->AdapterResetState));
44027 +#ifdef Y2_SYNC_CHECK
44028 +                                                               pAC->FramesWithoutSyncCheck =
44029 +                                                               Y2_RESYNC_WATERMARK;
44030 +#endif
44031 +                                                       } else {
44032 +                                                               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
44033 +                                                                       ("Got Tist %l:%l on Port %c but still waiting\n",
44034 +                                                                       pAC->GIni.GITimeStampCnt, pAC->MinTistLo,
44035 +                                                                       'A' + i));
44036 +                                                       }
44037 +                                               }
44038 +                                       }
44039 +#ifndef Y2_RECOVERY
44040 +                                       if (!SK_ADAPTER_WAITING_FOR_TIST(pAC)) {
44041 +                                               /* nobody needs tist anymore - turn it off */
44042 +                                               Y2_DISABLE_TIST(pAC->IoBase);
44043 +                                               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
44044 +                                               ("Turn off Tist !!!\n"));
44045 +                                       }
44046 +#endif
44047 +                               } else if (OpCode == OP_TXINDEXLE) {
44048 +                                       /*
44049 +                                        * change OpCode to notify the folowing code
44050 +                                        * to ignore the done index from this LE
44051 +                                        * unfortunately tist LEs will be generated only
44052 +                                        * for RxStat LEs
44053 +                                        * so in order to get a safe Done index for a
44054 +                                        * port currently waiting for a tist we have to
44055 +                                        * get the done index directly from the BMU
44056 +                                        */
44057 +                                       OpCode = OP_MOD_TXINDEX;
44058 +                                       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
44059 +                                               ("Mark unusable TX_INDEX LE!!!\n"));
44060 +                               } else {
44061 +                                       if (SK_PORT_WAITING_FOR_TIST(pAC, Port)) {
44062 +                                               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
44063 +                                                       ("Ignore LE 0x%X on Port %c!!!\n",
44064 +                                                       OpCode, 'A' + Port));
44065 +                                               OpCode = OP_MOD_LE;
44066 +#ifdef Y2_LE_CHECK
44067 +                                               /* mark entries invalid */
44068 +                                               pAC->LastOpc = 0xFF;
44069 +                                               pAC->LastPort = 3;
44070 +#endif
44071 +                                       }
44072 +                               }
44073 +                       } /* if (SK_ADAPTER_WAITING_FOR_TIST(pAC)) */
44074 +#endif
44075 +
44076 +
44077 +
44078 +
44079 +
44080 +#ifdef Y2_LE_CHECK
44081 +                       if (pAC->LastOpc != 0xFF) {
44082 +                               /* last opc is valid
44083 +                                * check if current opcode follows last opcode
44084 +                                */
44085 +                               if ((((OpCode & OP_RXTIMESTAMP) == OP_RXTIMESTAMP) && (pAC->LastOpc != OP_RXSTAT)) ||
44086 +                                   (((OpCode & OP_RXCHKS) == OP_RXCHKS) && (pAC->LastOpc != OP_RXTIMESTAMP)) ||
44087 +                                   ((OpCode == OP_RXSTAT) && (pAC->LastOpc != OP_RXCHKS))) {
44088 +
44089 +                                       /* opcode sequence broken
44090 +                                        * current LE is invalid
44091 +                                        */
44092 +
44093 +                                       if (pAC->LastOpc == OP_RXTIMESTAMP) {
44094 +                                               /* force invalid checksum */
44095 +                                               pLE->St.StUn.StRxTCPCSum.RxTCPSum1 = 1;
44096 +                                               pLE->St.StUn.StRxTCPCSum.RxTCPSum2 = 0;
44097 +                                               OpCode = pAC->LastOpc = OP_RXCHKS;
44098 +                                               Port = pAC->LastPort;
44099 +                                       } else if (pAC->LastOpc == OP_RXCHKS) {
44100 +                                               /* force invalid frame */
44101 +                                               Port = pAC->LastPort;
44102 +                                               pLE->St.Stat.BufLen = 64;
44103 +                                               pLE->St.StUn.StRxStatWord = GMR_FS_CRC_ERR;
44104 +                                               OpCode = pAC->LastOpc = OP_RXSTAT;
44105 +#ifdef Y2_SYNC_CHECK
44106 +                                               /* force rx sync check */
44107 +                                               pAC->FramesWithoutSyncCheck = Y2_RESYNC_WATERMARK;
44108 +#endif
44109 +                                       } else if (pAC->LastOpc == OP_RXSTAT) {
44110 +                                               /* create dont care tist */
44111 +                                               pLE->St.StUn.StRxTimeStamp = 0;
44112 +                                               OpCode = pAC->LastOpc = OP_RXTIMESTAMP;
44113 +                                               /* dont know the port yet */
44114 +                                       } else {
44115 +#ifdef DEBUG
44116 +                                               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
44117 +                                                       ("Unknown LastOpc %X for Timestamp on port %c.\n",
44118 +                                                       pAC->LastOpc, Port));
44119 +#endif
44120 +                                       }
44121 +                               }
44122 +                       }
44123 +#endif
44124 +
44125 +                       switch (OpCode) {
44126 +                       case OP_RXSTAT:
44127 +#ifdef Y2_RECOVERY
44128 +                               pAC->LastOpc = OP_RXSTAT;
44129 +#endif
44130 +                               /*
44131 +                               ** This is always the last Status LE belonging
44132 +                               ** to a received packet -> handle it...
44133 +                               */
44134 +                               if ((Port != 0) && (Port != 1)) {
44135 +                               /* Unknown port */
44136 +                                       panic("sk98lin: Unknown port %d\n",
44137 +                                       Port);
44138 +                               }
44139 +
44140 +                               HandleReceives(
44141 +                                       pAC,
44142 +                                       Port,
44143 +                                       STLE_GET_LEN(pLE),
44144 +                                       STLE_GET_FRSTATUS(pLE),
44145 +                                       pAC->StatusLETable.Bmu.Stat.TcpSum1,
44146 +                                       pAC->StatusLETable.Bmu.Stat.TcpSum2,
44147 +                                       pAC->StatusLETable.Bmu.Stat.RxTimeStamp,
44148 +                                       pAC->StatusLETable.Bmu.Stat.VlanId);
44149 +#ifdef CONFIG_SK98LIN_NAPI
44150 +                               if (*WorkDone >= WorkToDo) {
44151 +                                       break;
44152 +                               }
44153 +                               (*WorkDone)++;
44154 +#endif
44155 +                               break;
44156 +                       case OP_RXVLAN:
44157 +                               /* this value will be used for next RXSTAT */
44158 +                               pAC->StatusLETable.Bmu.Stat.VlanId = STLE_GET_VLAN(pLE);
44159 +                               break;
44160 +                       case OP_RXTIMEVLAN:
44161 +                               /* this value will be used for next RXSTAT */
44162 +                               pAC->StatusLETable.Bmu.Stat.VlanId = STLE_GET_VLAN(pLE);
44163 +                               /* fall through */
44164 +                       case OP_RXTIMESTAMP:
44165 +                               /* this value will be used for next RXSTAT */
44166 +                               pAC->StatusLETable.Bmu.Stat.RxTimeStamp = STLE_GET_TIST(pLE);
44167 +#ifdef Y2_RECOVERY
44168 +                               pAC->LastOpc = OP_RXTIMESTAMP;
44169 +                               pAC->LastPort = Port;
44170 +#endif
44171 +                               break;
44172 +                       case OP_RXCHKSVLAN:
44173 +                               /* this value will be used for next RXSTAT */
44174 +                               pAC->StatusLETable.Bmu.Stat.VlanId = STLE_GET_VLAN(pLE);
44175 +                               /* fall through */
44176 +                       case OP_RXCHKS:
44177 +                               /* this value will be used for next RXSTAT */
44178 +                               pAC->StatusLETable.Bmu.Stat.TcpSum1 = STLE_GET_TCP1(pLE);
44179 +                               pAC->StatusLETable.Bmu.Stat.TcpSum2 = STLE_GET_TCP2(pLE);
44180 +#ifdef Y2_RECOVERY
44181 +                               pAC->LastPort = Port;
44182 +                               pAC->LastOpc = OP_RXCHKS;
44183 +#endif
44184 +                               break;
44185 +                       case OP_RSS_HASH:
44186 +                               /* this value will be used for next RXSTAT */
44187 +#if 0
44188 +                               pAC->StatusLETable.Bmu.Stat.RssHashValue = STLE_GET_RSS(pLE);
44189 +#endif
44190 +                               break;
44191 +                       case OP_TXINDEXLE:
44192 +                               /*
44193 +                               ** :;:; TODO
44194 +                               ** it would be possible to check for which queues
44195 +                               ** the index has been changed and call
44196 +                               ** CheckForSendComplete() only for such queues
44197 +                               */
44198 +                               STLE_GET_DONE_IDX(pLE,LowVal,HighVal);
44199 +                               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
44200 +                                       ("LowVal: 0x%x HighVal: 0x%x\n", LowVal, HighVal));
44201 +
44202 +                               /*
44203 +                               ** It would be possible to check whether we really
44204 +                               ** need the values for second port or sync queue,
44205 +                               ** but I think checking whether we need them is
44206 +                               ** more expensive than the calculation
44207 +                               */
44208 +                               DoneTxA[0] = STLE_GET_DONE_IDX_TXA1(LowVal,HighVal);
44209 +                               DoneTxS[0] = STLE_GET_DONE_IDX_TXS1(LowVal,HighVal);
44210 +                               DoneTxA[1] = STLE_GET_DONE_IDX_TXA2(LowVal,HighVal);
44211 +                               DoneTxS[1] = STLE_GET_DONE_IDX_TXS2(LowVal,HighVal);
44212 +
44213 +                               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
44214 +                                       ("DoneTxa1 0x%x DoneTxS1: 0x%x DoneTxa2 0x%x DoneTxS2: 0x%x\n",
44215 +                                       DoneTxA[0], DoneTxS[0], DoneTxA[1], DoneTxS[1]));
44216 +
44217 +                               NewDone = SK_TRUE;
44218 +                               break;
44219 +#ifdef USE_TIST_FOR_RESET
44220 +                       case OP_MOD_TXINDEX:
44221 +                               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
44222 +                                       ("OP_MOD_TXINDEX\n"));
44223 +                               SK_IN16(pAC->IoBase, Q_ADDR(Q_XA1, Q_DONE), &DoneTxA[0]);
44224 +                               if (pAC->GIni.GIMacsFound > 1) {
44225 +                                       SK_IN16(pAC->IoBase, Q_ADDR(Q_XA2, Q_DONE), &DoneTxA[1]);
44226 +                               }
44227 +                               NewDone = SK_TRUE;
44228 +                               break;
44229 +                       case OP_MOD_LE:
44230 +                               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
44231 +                               ("Ignore marked LE on port in Reset\n"));
44232 +                               break;
44233 +#endif
44234 +
44235 +                       default:
44236 +                               /*
44237 +                               ** Have to handle the illegal Opcode in Status LE
44238 +                               */
44239 +                               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
44240 +                                       ("Unexpected OpCode\n"));
44241 +                               break;
44242 +                       }
44243 +
44244 +#ifdef Y2_RECOVERY
44245 +                       OpCode = STLE_GET_OPC(pLE) & ~HW_OWNER;
44246 +                       STLE_SET_OPC(pLE, OpCode);
44247 +#else
44248 +                       /*
44249 +                       ** Reset own bit we have to do this in order to detect a overflow
44250 +                       */
44251 +                       STLE_SET_OPC(pLE, SW_OWNER);
44252 +#endif
44253 +               } /* while (OWN_OF_FIRST_LE(&pAC->StatusLETable) == HW_OWNER) */
44254 +
44255 +               /*
44256 +               ** Now handle any new transmit complete
44257 +               */
44258 +               if (NewDone) {
44259 +                       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
44260 +                               ("Done Index for Tx BMU has been changed\n"));
44261 +                       for (Port = 0; Port < pAC->GIni.GIMacsFound; Port++) {
44262 +                               /*
44263 +                               ** Do we have a new Done idx ?
44264 +                               */
44265 +                               if (DoneTxA[Port] != GET_DONE_INDEX(&pAC->TxPort[Port][0].TxALET)) {
44266 +                                       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
44267 +                                               ("Check TxA%d\n", Port + 1));
44268 +                                       CheckForSendComplete(pAC, pAC->IoBase, Port,
44269 +                                               &(pAC->TxPort[Port][0].TxAQ_working),
44270 +                                               &pAC->TxPort[Port][0].TxALET,
44271 +                                               DoneTxA[Port]);
44272 +                               } else {
44273 +                                       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
44274 +                                               ("No changes for TxA%d\n", Port + 1));
44275 +                               }
44276 +#ifdef USE_SYNC_TX_QUEUE
44277 +                               if (HW_SYNC_TX_SUPPORTED(pAC)) {
44278 +                                       /*
44279 +                                       ** Do we have a new Done idx ?
44280 +                                       */
44281 +                                       if (DoneTxS[Port] !=
44282 +                                               GET_DONE_INDEX(&pAC->TxPort[Port][0].TxSLET)) {
44283 +                                               SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
44284 +                                                       SK_DBGCAT_DRV_INT_SRC,
44285 +                                                       ("Check TxS%d\n", Port));
44286 +                                               CheckForSendComplete(pAC, pAC->IoBase, Port,
44287 +                                                       &(pAC->TxPort[Port][0].TxSQ_working),
44288 +                                                       &pAC->TxPort[Port][0].TxSLET,
44289 +                                                       DoneTxS[Port]);
44290 +                                       } else {
44291 +                                               SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
44292 +                                                       SK_DBGCAT_DRV_INT_SRC,
44293 +                                                       ("No changes for TxS%d\n", Port));
44294 +                                       }
44295 +                               }
44296 +#endif
44297 +                       }
44298 +               }
44299 +               NewDone = SK_FALSE;
44300 +
44301 +               /*
44302 +               ** Check whether we have to refill our RX table
44303 +               */
44304 +               if (HW_FEATURE(pAC, HWF_WA_DEV_420)) {
44305 +                       if (NbrRxBuffersInHW < MAX_NBR_RX_BUFFERS_IN_HW) {
44306 +                               for (Port = 0; Port < pAC->GIni.GIMacsFound; Port++) {
44307 +                                       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
44308 +                                               ("Check for refill of RxBuffers on Port %c\n", 'A' + Port));
44309 +                                       FillReceiveTableYukon2(pAC, pAC->IoBase, Port);
44310 +                               }
44311 +                       }
44312 +               } else {
44313 +                       for (Port = 0; Port < pAC->GIni.GIMacsFound; Port++) {
44314 +                               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
44315 +                                       ("Check for refill of RxBuffers on Port %c\n", 'A' + Port));
44316 +                               if (NUM_FREE_LE_IN_TABLE(&pAC->RxPort[Port].RxLET) >= 64) {
44317 +                                       FillReceiveTableYukon2(pAC, pAC->IoBase, Port);
44318 +                               }
44319 +                       }
44320 +               }
44321 +#ifdef CONFIG_SK98LIN_NAPI
44322 +               if (*WorkDone >= WorkToDo) {
44323 +                       break;
44324 +               }
44325 +#endif
44326 +       } while (OWN_OF_FIRST_LE(&pAC->StatusLETable) == HW_OWNER);
44327 +
44328 +       /*
44329 +       ** Clear status BMU
44330 +       */
44331 +       if (handledStatLE)
44332 +               SK_OUT32(pAC->IoBase, STAT_CTRL, SC_STAT_CLR_IRQ);
44333 +
44334 +       return(handledStatLE);
44335 +}      /* HandleStatusLEs */
44336 +
44337 +/*****************************************************************************
44338 + *
44339 + *     AllocateAndInitLETables - allocate memory for the LETable and init
44340 + *
44341 + * Description:
44342 + *     This function will allocate space for the LETable and will also
44343 + *     initialize them. The size of the tables must have been specified
44344 + *     before.
44345 + *
44346 + * Arguments:
44347 + *     pAC - A pointer to the adapter context struct.
44348 + *
44349 + * Returns:
44350 + *     SK_TRUE  - all LETables initialized
44351 + *     SK_FALSE - failed
44352 + */
44353 +static SK_BOOL AllocateAndInitLETables(
44354 +SK_AC *pAC)  /* pointer to adapter context */
44355 +{
44356 +       char           *pVirtMemAddr;
44357 +       dma_addr_t     pPhysMemAddr = 0;
44358 +       SK_U32         CurrMac;
44359 +       unsigned       Size;
44360 +       unsigned       Aligned;
44361 +       unsigned       Alignment;
44362 +
44363 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
44364 +               ("==> AllocateAndInitLETables()\n"));
44365 +
44366 +       /*
44367 +       ** Determine how much memory we need with respect to alignment
44368 +       */
44369 +       Alignment = MAX_LEN_OF_LE_TAB;
44370 +       Size = 0;
44371 +       for (CurrMac = 0; CurrMac < pAC->GIni.GIMacsFound; CurrMac++) {
44372 +               SK_ALIGN_SIZE(LE_TAB_SIZE(RX_MAX_LE), Alignment, Aligned);
44373 +               Size += Aligned;
44374 +               SK_ALIGN_SIZE(LE_TAB_SIZE(TXA_MAX_LE), Alignment, Aligned);
44375 +               Size += Aligned;
44376 +               SK_ALIGN_SIZE(LE_TAB_SIZE(TXS_MAX_LE), Alignment, Aligned);
44377 +               Size += Aligned;
44378 +       }
44379 +       SK_ALIGN_SIZE(LE_TAB_SIZE(ST_MAX_LE), Alignment, Aligned);
44380 +       Size += Aligned;
44381 +       Size += Alignment;
44382 +       pAC->SizeOfAlignedLETables = Size;
44383 +
44384 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
44385 +                       ("Need %08x bytes in total\n", Size));
44386 +
44387 +       /*
44388 +       ** Allocate the memory
44389 +       */
44390 +       pVirtMemAddr = pci_alloc_consistent(pAC->PciDev, Size, &pPhysMemAddr);
44391 +       if (pVirtMemAddr == NULL) {
44392 +               SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
44393 +                       SK_DBGCAT_INIT | SK_DBGCAT_DRV_ERROR,
44394 +                       ("AllocateAndInitLETables: kernel malloc failed!\n"));
44395 +               return (SK_FALSE);
44396 +       }
44397 +
44398 +       /*
44399 +       ** Initialize the memory
44400 +       */
44401 +       SK_MEMSET(pVirtMemAddr, 0, Size);
44402 +       ALIGN_ADDR(pVirtMemAddr, Alignment); /* Macro defined in skgew.h */
44403 +
44404 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
44405 +               ("Virtual address of LETab is %8p!\n", pVirtMemAddr));
44406 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
44407 +               ("Phys address of LETab is %8p!\n", (void *) pPhysMemAddr));
44408 +
44409 +       for (CurrMac = 0; CurrMac < pAC->GIni.GIMacsFound; CurrMac++) {
44410 +               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
44411 +                       ("RxLeTable for Port %c", 'A' + CurrMac));
44412 +               SkGeY2InitSingleLETable(
44413 +                       pAC,
44414 +                       &pAC->RxPort[CurrMac].RxLET,
44415 +                       RX_MAX_LE,
44416 +                       pVirtMemAddr,
44417 +                       (SK_U32) (pPhysMemAddr & 0xffffffff),
44418 +                       (SK_U32) (((SK_U64) pPhysMemAddr) >> 32));
44419 +
44420 +               SK_ALIGN_SIZE(LE_TAB_SIZE(RX_MAX_LE), Alignment, Aligned);
44421 +               pVirtMemAddr += Aligned;
44422 +               pPhysMemAddr += Aligned;
44423 +
44424 +               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
44425 +                       ("TxALeTable for Port %c", 'A' + CurrMac));
44426 +               SkGeY2InitSingleLETable(
44427 +                       pAC,
44428 +                       &pAC->TxPort[CurrMac][0].TxALET,
44429 +                       TXA_MAX_LE,
44430 +                       pVirtMemAddr,
44431 +                       (SK_U32) (pPhysMemAddr & 0xffffffff),
44432 +                       (SK_U32) (((SK_U64) pPhysMemAddr) >> 32));
44433 +
44434 +               SK_ALIGN_SIZE(LE_TAB_SIZE(TXA_MAX_LE), Alignment, Aligned);
44435 +               pVirtMemAddr += Aligned;
44436 +               pPhysMemAddr += Aligned;
44437 +
44438 +               SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
44439 +                       ("TxSLeTable for Port %c", 'A' + CurrMac));
44440 +               SkGeY2InitSingleLETable(
44441 +                       pAC,
44442 +                       &pAC->TxPort[CurrMac][0].TxSLET,
44443 +                       TXS_MAX_LE,
44444 +                       pVirtMemAddr,
44445 +                       (SK_U32) (pPhysMemAddr & 0xffffffff),
44446 +                       (SK_U32) (((SK_U64) pPhysMemAddr) >> 32));
44447 +
44448 +               SK_ALIGN_SIZE(LE_TAB_SIZE(TXS_MAX_LE), Alignment, Aligned);
44449 +               pVirtMemAddr += Aligned;
44450 +               pPhysMemAddr += Aligned;
44451 +       }
44452 +
44453 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,("StLeTable"));
44454 +
44455 +       SkGeY2InitSingleLETable(
44456 +               pAC,
44457 +               &pAC->StatusLETable,
44458 +               ST_MAX_LE,
44459 +               pVirtMemAddr,
44460 +               (SK_U32) (pPhysMemAddr & 0xffffffff),
44461 +               (SK_U32) (((SK_U64) pPhysMemAddr) >> 32));
44462 +
44463 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
44464 +               ("<== AllocateAndInitLETables(OK)\n"));
44465 +       return(SK_TRUE);
44466 +}      /* AllocateAndInitLETables */
44467 +
44468 +/*****************************************************************************
44469 + *
44470 + *     AllocatePacketBuffersYukon2 - allocate packet and fragment buffers
44471 + *
44472 + * Description:
44473 + *      This function will allocate space for the packets and fragments
44474 + *
44475 + * Arguments:
44476 + *      pAC - A pointer to the adapter context struct.
44477 + *
44478 + * Returns:
44479 + *      SK_TRUE  - Memory was allocated correctly
44480 + *      SK_FALSE - An error occured
44481 + */
44482 +static SK_BOOL AllocatePacketBuffersYukon2(
44483 +SK_AC *pAC)  /* pointer to adapter context */
44484 +{
44485 +       SK_PACKET       *pRxPacket;
44486 +       SK_PACKET       *pTxPacket;
44487 +       SK_U32           CurrBuff;
44488 +       SK_U32           CurrMac;
44489 +       unsigned long    Flags; /* needed for POP/PUSH functions */
44490 +
44491 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
44492 +               ("==> AllocatePacketBuffersYukon2()"));
44493 +
44494 +       for (CurrMac = 0; CurrMac < pAC->GIni.GIMacsFound; CurrMac++) {
44495 +               /*
44496 +               ** Allocate RX packet space, initialize the packets and
44497 +               ** add them to the RX waiting queue. Waiting queue means
44498 +               ** that packet and fragment are initialized, but no sk_buff
44499 +               ** has been assigned to it yet.
44500 +               */
44501 +               pAC->RxPort[CurrMac].ReceivePacketTable =
44502 +                       kmalloc((RX_MAX_NBR_BUFFERS * sizeof(SK_PACKET)), GFP_KERNEL);
44503 +
44504 +               if (pAC->RxPort[CurrMac].ReceivePacketTable == NULL) {
44505 +                       SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_INIT | SK_DBGCAT_DRV_ERROR,
44506 +                               ("AllocatePacketBuffersYukon2: no mem RxPkts (port %i)",CurrMac));
44507 +                       break;
44508 +               } else {
44509 +                       SK_MEMSET(pAC->RxPort[CurrMac].ReceivePacketTable, 0,
44510 +                               (RX_MAX_NBR_BUFFERS * sizeof(SK_PACKET)));
44511 +
44512 +                       pRxPacket = pAC->RxPort[CurrMac].ReceivePacketTable;
44513 +
44514 +                       for (CurrBuff=0;CurrBuff<RX_MAX_NBR_BUFFERS;CurrBuff++) {
44515 +                               pRxPacket->pFrag = &(pRxPacket->FragArray[0]);
44516 +                               pRxPacket->NumFrags = 1;
44517 +                               PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[CurrMac].RxQ_waiting, pRxPacket);
44518 +                               pRxPacket++;
44519 +                       }
44520 +               }
44521 +
44522 +               /*
44523 +               ** Allocate TX packet space, initialize the packets and
44524 +               ** add them to the TX free queue. Free queue means that
44525 +               ** packet is available and initialized, but no fragment
44526 +               ** has been assigned to it. (Must be done at TX side)
44527 +               */
44528 +               pAC->TxPort[CurrMac][0].TransmitPacketTable =
44529 +                       kmalloc((TX_MAX_NBR_BUFFERS * sizeof(SK_PACKET)), GFP_KERNEL);
44530 +
44531 +               if (pAC->TxPort[CurrMac][0].TransmitPacketTable == NULL) {
44532 +                       SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_INIT | SK_DBGCAT_DRV_ERROR,
44533 +                               ("AllocatePacketBuffersYukon2: no mem TxPkts (port %i)",CurrMac));
44534 +                       kfree(pAC->RxPort[CurrMac].ReceivePacketTable);
44535 +                       return(SK_FALSE);
44536 +               } else {
44537 +                       SK_MEMSET(pAC->TxPort[CurrMac][0].TransmitPacketTable, 0,
44538 +                               (TX_MAX_NBR_BUFFERS * sizeof(SK_PACKET)));
44539 +
44540 +                       pTxPacket = pAC->TxPort[CurrMac][0].TransmitPacketTable;
44541 +
44542 +                       for (CurrBuff=0;CurrBuff<TX_MAX_NBR_BUFFERS;CurrBuff++) {
44543 +                               PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->TxPort[CurrMac][0].TxQ_free, pTxPacket);
44544 +                               pTxPacket++;
44545 +                       }
44546 +               }
44547 +       } /* end for (CurrMac = 0; CurrMac < pAC->GIni.GIMacsFound; CurrMac++) */
44548 +
44549 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
44550 +               ("<== AllocatePacketBuffersYukon2 (OK)\n"));
44551 +       return(SK_TRUE);
44552 +
44553 +}      /* AllocatePacketBuffersYukon2 */
44554 +
44555 +/*****************************************************************************
44556 + *
44557 + *     FreeLETables - release allocated memory of LETables
44558 + *
44559 + * Description:
44560 + *      This function will free all resources of the LETables
44561 + *
44562 + * Arguments:
44563 + *      pAC - A pointer to the adapter context struct.
44564 + *
44565 + * Returns: N/A
44566 + */
44567 +static void FreeLETables(
44568 +SK_AC *pAC)  /* pointer to adapter control context */
44569 +{
44570 +       dma_addr_t      pPhysMemAddr;
44571 +       char            *pVirtMemAddr;
44572 +
44573 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
44574 +               ("==> FreeLETables()\n"));
44575 +
44576 +       /*
44577 +       ** The RxLETable is the first of all LET.
44578 +       ** Therefore we can use its address for the input
44579 +       ** of the free function.
44580 +       */
44581 +       pVirtMemAddr = (char *) pAC->RxPort[0].RxLET.pLETab;
44582 +       pPhysMemAddr = (((SK_U64) pAC->RxPort[0].RxLET.pPhyLETABHigh << (SK_U64) 32) |
44583 +                       ((SK_U64) pAC->RxPort[0].RxLET.pPhyLETABLow));
44584 +
44585 +       /* free continuous memory */
44586 +       pci_free_consistent(pAC->PciDev, pAC->SizeOfAlignedLETables,
44587 +                           pVirtMemAddr, pPhysMemAddr);
44588 +
44589 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
44590 +               ("<== FreeLETables()\n"));
44591 +}      /* FreeLETables */
44592 +
44593 +/*****************************************************************************
44594 + *
44595 + *     FreePacketBuffers - free's all packet buffers of an adapter
44596 + *
44597 + * Description:
44598 + *      This function will free all previously allocated memory of the
44599 + *     packet buffers.
44600 + *
44601 + * Arguments:
44602 + *      pAC - A pointer to the adapter context struct.
44603 + *
44604 + * Returns: N/A
44605 + */
44606 +static void FreePacketBuffers(
44607 +SK_AC *pAC)  /* pointer to adapter control context */
44608 +{
44609 +       int Port;
44610 +
44611 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
44612 +               ("==> FreePacketBuffers()\n"));
44613 +
44614 +       for (Port = 0; Port < pAC->GIni.GIMacsFound; Port++) {
44615 +               kfree(pAC->RxPort[Port].ReceivePacketTable);
44616 +               kfree(pAC->TxPort[Port][0].TransmitPacketTable);
44617 +       }
44618 +
44619 +       SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
44620 +               ("<== FreePacketBuffers()\n"));
44621 +}      /* FreePacketBuffers */
44622 +
44623 +/*****************************************************************************
44624 + *
44625 + *     AllocAndMapRxBuffer - fill one buffer into the receive packet/fragment
44626 + *
44627 + * Description:
44628 + *     The function allocates a new receive buffer and assigns it to the
44629 + *     the passsed receive packet/fragment
44630 + *
44631 + * Returns:
44632 + *     SK_TRUE - a buffer was allocated and assigned
44633 + *     SK_FALSE - a buffer could not be added
44634 + */
44635 +static SK_BOOL AllocAndMapRxBuffer(
44636 +SK_AC      *pAC,        /* pointer to the adapter control context */
44637 +SK_PACKET  *pSkPacket,  /* pointer to packet that is to fill      */
44638 +int         Port)       /* port the packet belongs to             */
44639 +{
44640 +       struct sk_buff *pMsgBlock;  /* pointer to a new message block  */
44641 +       SK_U64          PhysAddr;   /* physical address of a rx buffer */
44642 +
44643 +       SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
44644 +               ("--> AllocAndMapRxBuffer (Port: %i)\n", Port));
44645 +
44646 +       pMsgBlock = alloc_skb(pAC->RxPort[Port].RxBufSize, GFP_ATOMIC);
44647 +       if (pMsgBlock == NULL) {
44648 +               SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
44649 +                       SK_DBGCAT_DRV_RX_PROGRESS | SK_DBGCAT_DRV_ERROR,
44650 +                       ("%s: Allocation of rx buffer failed !\n",
44651 +                       pAC->dev[Port]->name));
44652 +               SK_PNMI_CNT_NO_RX_BUF(pAC, pAC->RxPort[Port].PortIndex);
44653 +               return(SK_FALSE);
44654 +       }
44655 +       skb_reserve(pMsgBlock, 8);
44656 +
44657 +       PhysAddr = (SK_U64) pci_map_page(pAC->PciDev,
44658 +               virt_to_page(pMsgBlock->data),
44659 +               ((unsigned long) pMsgBlock->data &
44660 +               ~PAGE_MASK),
44661 +               pAC->RxPort[Port].RxBufSize,
44662 +               PCI_DMA_FROMDEVICE);
44663 +
44664 +       pSkPacket->pFrag->pVirt   = pMsgBlock->data;
44665 +       pSkPacket->pFrag->pPhys   = PhysAddr;
44666 +       pSkPacket->pFrag->FragLen = pAC->RxPort[Port].RxBufSize; /* for correct unmap */
44667 +       pSkPacket->pMBuf          = pMsgBlock;
44668 +       pSkPacket->PacketLen      = pAC->RxPort[Port].RxBufSize;
44669 +
44670 +       SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
44671 +               ("<-- AllocAndMapRxBuffer\n"));
44672 +
44673 +       return (SK_TRUE);
44674 +}      /* AllocAndMapRxBuffer */
44675 +
44676 +/*******************************************************************************
44677 + *
44678 + * End of file
44679 + *
44680 + ******************************************************************************/
44681 diff -ruN linux/drivers/net/sk98lin/sky2le.c linux-new/drivers/net/sk98lin/sky2le.c
44682 --- linux/drivers/net/sk98lin/sky2le.c  1970-01-01 01:00:00.000000000 +0100
44683 +++ linux-new/drivers/net/sk98lin/sky2le.c      2006-07-28 14:13:54.000000000 +0200
44684 @@ -0,0 +1,507 @@
44685 +/*****************************************************************************
44686 + *
44687 + *     Name:           sky2le.c
44688 + *     Project:        Gigabit Ethernet Adapters, Common Modules
44689 + *     Version:        $Revision$
44690 + *     Date:           $Date$
44691 + *     Purpose:        Functions for handling List Element Tables
44692 + *
44693 + *****************************************************************************/
44694 +
44695 +/******************************************************************************
44696 + *
44697 + *     LICENSE:
44698 + *     (C)Copyright 2002-2006 Marvell.
44699 + *
44700 + *     This program is free software; you can redistribute it and/or modify
44701 + *     it under the terms of the GNU General Public License as published by
44702 + *     the Free Software Foundation; either version 2 of the License, or
44703 + *     (at your option) any later version.
44704 + *     The information in this file is provided "AS IS" without warranty.
44705 + *     /LICENSE
44706 + *
44707 + ******************************************************************************/
44708 +
44709 +/*****************************************************************************
44710 + *
44711 + * Description:
44712 + *
44713 + * This module contains the code necessary for handling List Elements.
44714 + *
44715 + * Supported Gigabit Ethernet Chipsets:
44716 + *     Yukon-2 (PCI, PCI-X, PCI-Express)
44717 + *
44718 + * Include File Hierarchy:
44719 + *
44720 + *
44721 + *****************************************************************************/
44722 +#include "h/skdrv1st.h"
44723 +#include "h/skdrv2nd.h"
44724 +
44725 +/* defines *******************************************************************/
44726 +/* typedefs ******************************************************************/
44727 +/* global variables **********************************************************/
44728 +/* local variables ***********************************************************/
44729 +
44730 +#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
44731 +static const char SysKonnectFileId[] =
44732 +       "@(#) $Id$ (C) Marvell.";
44733 +#endif /* DEBUG || (!LINT && !SK_SLIM) */
44734 +
44735 +/* function prototypes *******************************************************/
44736 +
44737 +/*****************************************************************************
44738 + *
44739 + * SkGeY2InitSingleLETable() - initializes a list element table
44740 + *
44741 + * Description:
44742 + *     This function will initialize the selected list element table.
44743 + *     Should be called once during DriverInit. No InitLevel required.
44744 + *
44745 + * Arguments:
44746 + *     pAC                     - pointer to the adapter context struct.
44747 + *     pLETab          - pointer to list element table structure
44748 + *     NumLE           - number of list elements in this table
44749 + *     pVMem           - virtual address of memory allocated for this LE table
44750 + *     PMemLowAddr - physical address of memory to be used for the LE table
44751 + *     PMemHighAddr
44752 + *
44753 + * Returns:
44754 + *     nothing
44755 + */
44756 +void SkGeY2InitSingleLETable(
44757 +SK_AC  *pAC,                   /* pointer to adapter context */
44758 +SK_LE_TABLE    *pLETab,        /* pointer to list element table to be initialized */
44759 +unsigned int NumLE,            /* number of list elements to be filled in tab */
44760 +void   *pVMem,                 /* virtual address of memory used for list elements */
44761 +SK_U32 PMemLowAddr,    /* physical addr of mem used for LE */
44762 +SK_U32 PMemHighAddr)
44763 +{
44764 +       unsigned int i;
44765 +
44766 +       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44767 +               ("==> SkGeY2InitSingleLETable()\n"));
44768 +
44769 +#ifdef DEBUG
44770 +       if (NumLE != 2) {       /* not table for polling unit */
44771 +               if ((NumLE % MIN_LEN_OF_LE_TAB) != 0 || NumLE > MAX_LEN_OF_LE_TAB) {
44772 +                       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
44773 +                               ("ERROR: Illegal number of list elements %d\n", NumLE));
44774 +               }
44775 +       }
44776 +#endif /* DEBUG */
44777 +
44778 +       /* special case: unused list element table */
44779 +       if (NumLE == 0) {
44780 +               PMemLowAddr = 0;
44781 +               PMemHighAddr = 0;
44782 +               pVMem = 0;
44783 +       }
44784 +
44785 +       /*
44786 +        * in order to get the best possible performance the macros to access
44787 +        * list elements use & instead of %
44788 +        * this requires the length of LE tables to be a power of 2
44789 +        */
44790 +
44791 +       /*
44792 +        * this code guarantees that we use the next power of 2 below the
44793 +        * value specified for NumLe - this way some LEs in the table may
44794 +        * not be used but the macros work correctly
44795 +        * this code does not check for bad values below 128 because in such a
44796 +        * case we cannot do anything here
44797 +        */
44798 +
44799 +       if ((NumLE != 2) && (NumLE != 0)) {
44800 +               /* no check for polling unit and unused sync Tx */
44801 +               i = MIN_LEN_OF_LE_TAB;
44802 +               while (NumLE > i) {
44803 +                       i *= 2;
44804 +                       if (i > MAX_LEN_OF_LE_TAB) {
44805 +                               break;
44806 +                       }
44807 +               }
44808 +               if (NumLE != i) {
44809 +                       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
44810 +                               ("ERROR: Illegal number of list elements %d adjusted to %d\n",
44811 +                               NumLE, (i / 2)));
44812 +                       NumLE = i / 2;
44813 +               }
44814 +       }
44815 +
44816 +       /* set addresses */
44817 +       pLETab->pPhyLETABLow = PMemLowAddr;
44818 +       pLETab->pPhyLETABHigh = PMemHighAddr;
44819 +       pLETab->pLETab = pVMem;
44820 +
44821 +       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44822 +               ("contains %d LEs", NumLE));
44823 +       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44824 +               (" and starts at virt %08lx and phys %08lx:%08lx\n",
44825 +               pVMem, PMemHighAddr, PMemLowAddr));
44826 +
44827 +       /* initialize indexes */
44828 +       pLETab->Done = 0;
44829 +       pLETab->Put = 0;
44830 +       pLETab->HwPut = 0;
44831 +       /* initialize size */
44832 +       pLETab->Num = NumLE;
44833 +
44834 +       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44835 +               ("<== SkGeY2InitSingleLETable()\n"));
44836 +}      /* SkGeY2InitSingleLETable */
44837 +
44838 +/*****************************************************************************
44839 + *
44840 + * SkGeY2InitPrefetchUnit() - Initialize a Prefetch Unit
44841 + *
44842 + * Description:
44843 + *     Calling this function requires an already configured list element
44844 + *     table. The prefetch unit to be configured is specified in the parameter
44845 + *     'Queue'. The function is able to initialze the prefetch units of
44846 + *     the following queues: Q_R1, Q_R2, Q_XS1, Q_XS2, Q_XA1, Q_XA2.
44847 + *     The funcution should be called before SkGeInitPort().
44848 + *
44849 + * Arguments:
44850 + *     pAC - pointer to the adapter context struct.
44851 + *     IoC - I/O context.
44852 + *     Queue - I/O offset of queue e.g. Q_XA1.
44853 + *     pLETab - pointer to list element table to be initialized
44854 + *
44855 + * Returns: N/A
44856 + */
44857 +void SkGeY2InitPrefetchUnit(
44858 +SK_AC  *pAC,                   /* pointer to adapter context */
44859 +SK_IOC IoC,                    /* I/O context */
44860 +unsigned int Queue,            /* Queue offset for finding the right registers */
44861 +SK_LE_TABLE    *pLETab)        /* pointer to list element table to be initialized */
44862 +{
44863 +       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44864 +               ("==> SkGeY2InitPrefetchUnit()\n"));
44865 +
44866 +#ifdef DEBUG
44867 +       if (Queue != Q_R1 && Queue != Q_R2 && Queue != Q_XS1 &&
44868 +               Queue != Q_XS2 && Queue != Q_XA1 && Queue != Q_XA2) {
44869 +               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
44870 +                       ("ERROR: Illegal queue identifier %x\n", Queue));
44871 +       }
44872 +#endif /* DEBUG */
44873 +
44874 +       /* disable the prefetch unit */
44875 +       SK_OUT32(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_CTRL_REG), PREF_UNIT_RST_SET);
44876 +       SK_OUT32(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_CTRL_REG), PREF_UNIT_RST_CLR);
44877 +
44878 +       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44879 +               ("Base address: %08lx:%08lx\n", pLETab->pPhyLETABHigh,
44880 +               pLETab->pPhyLETABLow));
44881 +
44882 +       /* Set the list base address  high part*/
44883 +       SK_OUT32(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_ADDR_HI_REG),
44884 +               pLETab->pPhyLETABHigh);
44885 +
44886 +       /* Set the list base address low part */
44887 +       SK_OUT32(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_ADDR_LOW_REG),
44888 +               pLETab->pPhyLETABLow);
44889 +
44890 +       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44891 +               ("Last index: %d\n", pLETab->Num-1));
44892 +
44893 +       /* Set the list last index */
44894 +       SK_OUT16(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_LAST_IDX_REG),
44895 +               (SK_U16)(pLETab->Num - 1));
44896 +
44897 +       /* turn on prefetch unit */
44898 +       SK_OUT32(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_CTRL_REG), PREF_UNIT_OP_ON);
44899 +
44900 +       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44901 +               ("<== SkGeY2InitPrefetchUnit()\n"));
44902 +}      /* SkGeY2InitPrefetchUnit */
44903 +
44904 +
44905 +/*****************************************************************************
44906 + *
44907 + * SkGeY2InitStatBmu() -       Initialize the Status BMU
44908 + *
44909 + * Description:
44910 + *     Calling this function requires an already configured list element
44911 + *     table. Ensure the status BMU is only initialized once during
44912 + *  DriverInit - InitLevel2 required.
44913 + *
44914 + * Arguments:
44915 + *     pAC - pointer to the adapter context struct.
44916 + *     IoC - I/O context.
44917 + *     pLETab - pointer to status LE table to be initialized
44918 + *
44919 + * Returns: N/A
44920 + */
44921 +void SkGeY2InitStatBmu(
44922 +SK_AC  *pAC,                   /* pointer to adapter context */
44923 +SK_IOC IoC,                    /* I/O context */
44924 +SK_LE_TABLE    *pLETab)        /* pointer to status LE table */
44925 +{
44926 +       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44927 +               ("==> SkGeY2InitStatBmu()\n"));
44928 +
44929 +       /* disable the prefetch unit */
44930 +       SK_OUT32(IoC, STAT_CTRL, SC_STAT_RST_SET);
44931 +       SK_OUT32(IoC, STAT_CTRL, SC_STAT_RST_CLR);
44932 +
44933 +       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44934 +               ("Base address Low: %08lX\n", pLETab->pPhyLETABLow));
44935 +
44936 +       /* Set the list base address */
44937 +       SK_OUT32(IoC, STAT_LIST_ADDR_LO, pLETab->pPhyLETABLow);
44938 +
44939 +       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44940 +               ("Base address High: %08lX\n", pLETab->pPhyLETABHigh));
44941 +
44942 +       SK_OUT32(IoC, STAT_LIST_ADDR_HI, pLETab->pPhyLETABHigh);
44943 +
44944 +       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44945 +               ("Last index: %d\n", pLETab->Num - 1));
44946 +
44947 +       /* Set the list last index */
44948 +       SK_OUT16(IoC, STAT_LAST_IDX, (SK_U16)(pLETab->Num - 1));
44949 +
44950 +       if (HW_FEATURE(pAC, HWF_WA_DEV_43_418)) {
44951 +
44952 +               SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44953 +                       ("Set Tx index threshold\n"));
44954 +               /* WA for dev. #4.3 */
44955 +               SK_OUT16(IoC, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK);
44956 +
44957 +               /* set Status-FIFO watermark */
44958 +               SK_OUT8(IoC, STAT_FIFO_WM, 0x21);               /* WA for dev. #4.18 */
44959 +
44960 +               /* set Status-FIFO ISR watermark */
44961 +               SK_OUT8(IoC, STAT_FIFO_ISR_WM, 0x07);   /* WA for dev. #4.18 */
44962 +
44963 +               /* WA for dev. #4.3 and #4.18 */
44964 +               /* set Status-FIFO Tx timer init value */
44965 +               SK_OUT32(IoC, STAT_TX_TIMER_INI, HW_MS_TO_TICKS(pAC, 10));
44966 +       }
44967 +       else {
44968 +               /*
44969 +                * Further settings may be added if required...
44970 +                * 1) Status-FIFO watermark (STAT_FIFO_WM, STAT_FIFO_ISR_WM)
44971 +                * 2) Status-FIFO timer values (STAT_TX_TIMER_INI,
44972 +                *              STAT_LEV_TIMER_INI and STAT_ISR_TIMER_INI)
44973 +                * but tests shows that the default values give the best results,
44974 +                * therefore the defaults are used.
44975 +                */
44976 +
44977 +               /*
44978 +                * Theses settings should avoid the temporary hang of the status BMU.
44979 +                * May be not all required... still under investigation...
44980 +                */
44981 +               SK_OUT16(IoC, STAT_TX_IDX_TH, 0x000a);
44982 +
44983 +               /* set Status-FIFO watermark */
44984 +               SK_OUT8(IoC, STAT_FIFO_WM, 0x10);
44985 +
44986 +               /* set Status-FIFO ISR watermark */
44987 +               SK_OUT8(IoC, STAT_FIFO_ISR_WM,
44988 +                       HW_FEATURE(pAC, HWF_WA_DEV_4109) ? 0x10 : 0x04);
44989 +
44990 +               /* set ISR Timer Init Value to 400 (3.2 us on Yukon-EC) */
44991 +               SK_OUT32(IoC, STAT_ISR_TIMER_INI, 0x0190);
44992 +       }
44993 +
44994 +       /* start Status-FIFO timer */
44995 +       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44996 +               ("Start Status FiFo timer\n"));
44997 +
44998 +       /* enable the prefetch unit */
44999 +       /* operational bit not functional for Yukon-EC, but fixed in Yukon-2 */
45000 +       SK_OUT32(IoC, STAT_CTRL, SC_STAT_OP_ON);
45001 +
45002 +       /* start Status-FIFO timer */
45003 +       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
45004 +               ("Start Status FiFo timer\n"));
45005 +
45006 +       SK_OUT8(IoC, STAT_TX_TIMER_CTRL, TIM_START);
45007 +       SK_OUT8(IoC, STAT_LEV_TIMER_CTRL, TIM_START);
45008 +       SK_OUT8(IoC, STAT_ISR_TIMER_CTRL, TIM_START);
45009 +
45010 +       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
45011 +               ("<== SkGeY2InitStatBmu()\n"));
45012 +}      /* SkGeY2InitStatBmu */
45013 +
45014 +#ifdef USE_POLLING_UNIT
45015 +/*****************************************************************************
45016 + *
45017 + * SkGeY2InitPollUnit() -      Initialize the Polling Unit
45018 + *
45019 + * Description:
45020 + *     This function will write the data of one polling LE table into the
45021 + *  adapter.
45022 + *
45023 + * Arguments:
45024 + *     pAC - pointer to the adapter context struct.
45025 + *     IoC - I/O context.
45026 + *     pLETab - pointer to polling LE table to be initialized
45027 + *
45028 + * Returns: N/A
45029 + */
45030 +void SkGeY2InitPollUnit(
45031 +SK_AC  *pAC,                   /* pointer to adapter context */
45032 +SK_IOC IoC,                    /* I/O context */
45033 +SK_LE_TABLE    *pLETab)        /* pointer to polling LE table */
45034 +{
45035 +       SK_HWLE *pLE;
45036 +       int     i;
45037 +#ifdef VCPU
45038 +       VCPU_VARS();
45039 +#endif /* VCPU */
45040 +
45041 +       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
45042 +               ("==> SkGeY2InitPollUnit()\n"));
45043 +
45044 +#ifdef VCPU
45045 +       for (i = 0; i < SK_MAX_MACS; i++) {
45046 +               GET_PO_LE(pLE, pLETab, i);
45047 +               VCPU_START_AND_COPY_LE();
45048 +               /* initialize polling LE but leave indexes invalid */
45049 +               POLE_SET_OPC(pLE, OP_PUTIDX | HW_OWNER);
45050 +               POLE_SET_LINK(pLE, i);
45051 +               POLE_SET_RXIDX(pLE, 0);
45052 +               POLE_SET_TXAIDX(pLE, 0);
45053 +               POLE_SET_TXSIDX(pLE, 0);
45054 +               VCPU_WRITE_LE();
45055 +               SK_DBG_DUMP_PO_LE(pLE);
45056 +       }
45057 +#endif /* VCPU */
45058 +
45059 +       /* disable the polling unit */
45060 +       SK_OUT32(IoC, POLL_CTRL, PC_POLL_RST_SET);
45061 +       SK_OUT32(IoC, POLL_CTRL, PC_POLL_RST_CLR);
45062 +
45063 +       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
45064 +               ("Base address Low: %08lX\n", pLETab->pPhyLETABLow));
45065 +
45066 +       /* Set the list base address */
45067 +       SK_OUT32(IoC, POLL_LIST_ADDR_LO, pLETab->pPhyLETABLow);
45068 +
45069 +       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
45070 +               ("Base address High: %08lX\n", pLETab->pPhyLETABHigh));
45071 +
45072 +       SK_OUT32(IoC, POLL_LIST_ADDR_HI, pLETab->pPhyLETABHigh);
45073 +
45074 +       /* we don't need to write the last index - it is hardwired to 1 */
45075 +
45076 +       /* enable the prefetch unit */
45077 +       SK_OUT32(IoC, POLL_CTRL, PC_POLL_OP_ON);
45078 +
45079 +       /*
45080 +        * now we have to start the descriptor poll timer because it triggers
45081 +        * the polling unit
45082 +        */
45083 +
45084 +       /*
45085 +        * still playing with the value (timer runs at 125 MHz)
45086 +        * descriptor poll timer is enabled by GeInit
45087 +        */
45088 +       SK_OUT32(IoC, B28_DPT_INI,
45089 +               (SK_DPOLL_DEF_Y2 * (SK_U32)pAC->GIni.GIHstClkFact / 100));
45090 +
45091 +       SK_OUT8(IoC, B28_DPT_CTRL, TIM_START);
45092 +
45093 +       SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
45094 +               ("<== SkGeY2InitPollUnit()\n"));
45095 +}      /* SkGeY2InitPollUnit */
45096 +#endif /* USE_POLLING_UNIT */
45097 +
45098 +
45099 +/******************************************************************************
45100 + *
45101 + * SkGeY2SetPutIndex
45102 + *
45103 + * Description:
45104 + *   This function is writing the Done index of a transmit
45105 + *   list element table.
45106 + *
45107 + * Notes:
45108 + *     Dev. Issue 4.2
45109 + *
45110 + * Returns: N/A
45111 + */
45112 +void SkGeY2SetPutIndex(
45113 +SK_AC  *pAC,                                   /* pointer to adapter context */
45114 +SK_IOC IoC,                                    /* pointer to the IO context */
45115 +SK_U32 StartAddrPrefetchUnit,  /* start address of the prefetch unit */
45116 +SK_LE_TABLE    *pLETab)                        /* list element table to work with */
45117 +{
45118 +       unsigned int Put;
45119 +       SK_U16 EndOfListIndex;
45120 +       SK_U16 HwGetIndex;
45121 +       SK_U16 HwPutIndex;
45122 +
45123 +       /* set put index we would like to write */
45124 +       Put = GET_PUT_IDX(pLETab);
45125 +
45126 +       /*
45127 +        * in this case we wrap around
45128 +        * new put is lower than last put given to HW
45129 +        */
45130 +       if (Put < pLETab->HwPut) {
45131 +
45132 +               /* set put index = last index of list */
45133 +               EndOfListIndex = (NUM_LE_IN_TABLE(pLETab)-1);
45134 +
45135 +               /* read get index of hw prefetch unit */
45136 +               SK_IN16(IoC, (StartAddrPrefetchUnit + PREF_UNIT_GET_IDX_REG),
45137 +                       &HwGetIndex);
45138 +
45139 +               /* read put index of hw prefetch unit */
45140 +               SK_IN16(IoC, (StartAddrPrefetchUnit + PREF_UNIT_PUT_IDX_REG),
45141 +                       &HwPutIndex);
45142 +
45143 +               /* prefetch unit reached end of list */
45144 +               /* prefetch unit reached first list element */
45145 +               if (HwGetIndex == 0) {
45146 +                       /* restore watermark */
45147 +                       SK_OUT8(IoC, StartAddrPrefetchUnit + PREF_UNIT_FIFO_WM_REG, 0xe0U);
45148 +                       /* write put index */
45149 +                       SK_OUT16(IoC, StartAddrPrefetchUnit + PREF_UNIT_PUT_IDX_REG,
45150 +                               (SK_U16)Put);
45151 +
45152 +                       /* remember put index  we wrote to hw */
45153 +                       pLETab->HwPut = Put;
45154 +               }
45155 +               else if (HwGetIndex == EndOfListIndex) {
45156 +                       /* set watermark to one list element */
45157 +                       SK_OUT8(IoC, StartAddrPrefetchUnit + PREF_UNIT_FIFO_WM_REG, 8);
45158 +                       /* set put index to first list element */
45159 +                       SK_OUT16(IoC, StartAddrPrefetchUnit + PREF_UNIT_PUT_IDX_REG, 0);
45160 +               }
45161 +               /* prefetch unit did not reach end of list yet */
45162 +               /* and we did not write put index to end of list yet */
45163 +               else if ((HwPutIndex != EndOfListIndex) &&
45164 +                                (HwGetIndex != EndOfListIndex)) {
45165 +                       /* write put index */
45166 +                       SK_OUT16(IoC, StartAddrPrefetchUnit + PREF_UNIT_PUT_IDX_REG,
45167 +                               EndOfListIndex);
45168 +               }
45169 +               else {
45170 +                       /* do nothing */
45171 +               }
45172 +       }
45173 +       else {
45174 +#ifdef XXX             /* leads in to problems in the Windows Driver */
45175 +               if (Put != pLETab->HwPut) {
45176 +                       /* write put index */
45177 +                       SK_OUT16(IoC, StartAddrPrefetchUnit + PREF_UNIT_PUT_IDX_REG,
45178 +                               (SK_U16)Put);
45179 +                       /* update put index */
45180 +                       UPDATE_HWPUT_IDX(pLETab);
45181 +               }
45182 +#else
45183 +               /* write put index */
45184 +               SK_OUT16(IoC, StartAddrPrefetchUnit + PREF_UNIT_PUT_IDX_REG,
45185 +                       (SK_U16)Put);
45186 +               /* update put index */
45187 +               UPDATE_HWPUT_IDX(pLETab);
45188 +#endif
45189 +       }
45190 +}      /* SkGeY2SetPutIndex */
45191 +
45192 diff -ruN linux/Documentation/networking/sk98lin.txt linux-new/Documentation/networking/sk98lin.txt
45193 --- linux/Documentation/networking/sk98lin.txt  2006-09-20 05:42:06.000000000 +0200
45194 +++ linux-new/drivers/net/sk98lin/sk98lin.txt   2006-07-28 14:13:54.000000000 +0200
45195 @@ -1,38 +1,56 @@
45196 -(C)Copyright 1999-2004 Marvell(R).
45197 -All rights reserved
45198 -===========================================================================
45199 +(C)Copyright 1999-2006 Marvell(R).
45200 +All rights reserved.
45201 +================================================================================
45202
45203 -sk98lin.txt created 13-Feb-2004
45204 +sk98lin.txt created 28-Jul-2006
45205
45206 -Readme File for sk98lin v6.23
45207 -Marvell Yukon/SysKonnect SK-98xx Gigabit Ethernet Adapter family driver for LINUX
45208 +Readme File for sk98lin v8.36.1.3
45209 +Marvell Yukon/SysKonnect SK-98xx Gigabit Ethernet Adapter driver for LINUX
45210
45211  This file contains
45212   1  Overview
45213 - 2  Required Files
45214 - 3  Installation
45215 -    3.1  Driver Installation
45216 -    3.2  Inclusion of adapter at system start
45217 - 4  Driver Parameters
45218 -    4.1  Per-Port Parameters
45219 -    4.2  Adapter Parameters
45220 - 5  Large Frame Support
45221 - 6  VLAN and Link Aggregation Support (IEEE 802.1, 802.1q, 802.3ad)
45222 - 7  Troubleshooting
45223 + 2  Supported Functions
45224 + 3  Required Files
45225 + 4  Installation
45226 +    4.1  Driver Installation
45227 +    4.2  Inclusion of adapter at system start
45228 + 5  Driver Parameters
45229 +    5.1  Per-Port Parameters
45230 +    5.2  Adapter Parameters
45231 + 6  Ethtool Support
45232 + 7  Large Frame Support
45233 + 8  VLAN and Link Aggregation Support (IEEE 802.1, 802.1q, 802.3ad)
45234 + 9  Wake on Lan support
45235 +10  Troubleshooting
45236
45237 -===========================================================================
45238 +================================================================================
45239
45240
45241  1  Overview
45242  ===========
45243
45244 -The sk98lin driver supports the Marvell Yukon and SysKonnect
45245 -SK-98xx/SK-95xx compliant Gigabit Ethernet Adapter on Linux. It has
45246 -been tested with Linux on Intel/x86 machines.
45247 +The sk98lin driver supports the Marvell Yukon, Yukon EC/FE, Yukon 2
45248 +and SysKonnect SK-98xx/SK-95xx compliant Gigabit Ethernet Adapter on Linux.
45249 +It has been tested with Linux on Intel/x86, x86_64 and IA64 machines.
45250  ***
45251
45252 +2  Supported Functions
45253 +======================
45254 +
45255 +The following functions are supported by the driver:
45256
45257 -2  Required Files
45258 +   NOTE 1: The hardware support depends on the used card
45259 +
45260 +   - RX/TX HW Checksum
45261 +   - Hardware interrupt moderation (static/dynamic)
45262 +   - Transmit poll
45263 +   - Zerocopy/Scatter-Gather
45264 +   - Ethtool support
45265 +   - Wake on Lan (Magic Packet only)
45266 +   - DualNet
45267 +
45268 +
45269 +3  Required Files
45270  =================
45271
45272  The linux kernel source.
45273 @@ -40,16 +58,14 @@
45274  ***
45275
45276
45277 -3  Installation
45278 +4  Installation
45279  ===============
45280
45281  It is recommended to download the latest version of the driver from the
45282 -SysKonnect web site www.syskonnect.com. If you have downloaded the latest
45283 -driver, the Linux kernel has to be patched before the driver can be
45284 -installed. For details on how to patch a Linux kernel, refer to the
45285 -patch.txt file.
45286 +SysKonnect web site www.syskonnect.com. For details on Installation
45287 +Instructions for sk98lin Driver, please refer to the README.txt file.
45288
45289 -3.1  Driver Installation
45290 +4.1  Driver Installation
45291  ------------------------
45292
45293  The following steps describe the actions that are required to install
45294 @@ -91,7 +107,7 @@
45295     with (M)
45296  5. Execute the command "make modules".
45297  6. Execute the command "make modules_install".
45298 -   The appropriate modules will be installed.
45299 +   The appropiate modules will be installed.
45300  7. Reboot your system.
45301
45302
45303 @@ -110,13 +126,13 @@
45304
45305     NOTE 1: If you have more than one Marvell Yukon or SysKonnect SK-98xx
45306             adapter installed, the adapters will be listed as 'eth0',
45307 -                   'eth1', 'eth2', etc.
45308 -                   For each adapter, repeat steps 3 and 4 below.
45309 +           'eth1', 'eth2', etc.
45310 +           For each adapter, repeat steps 3 and 4 below.
45311
45312     NOTE 2: If you have other Ethernet adapters installed, your Marvell
45313             Yukon or SysKonnect SK-98xx adapter will be mapped to the
45314 -                   next available number, e.g. 'eth1'. The mapping is executed
45315 -                   automatically.
45316 +           next available number, e.g. 'eth1'. The mapping is executed
45317 +           automatically.
45318             The module installation message (displayed either in a system
45319             log file or on the console) prints a line for each adapter
45320             found containing the corresponding 'ethX'.
45321 @@ -153,7 +169,7 @@
45322  1. Execute the command "ifconfig eth0 down".
45323  2. Execute the command "rmmod sk98lin".
45324
45325 -3.2  Inclusion of adapter at system start
45326 +4.2  Inclusion of adapter at system start
45327  -----------------------------------------
45328
45329  Since a large number of different Linux distributions are
45330 @@ -165,7 +181,8 @@
45331
45332  ***
45333
45334 -4  Driver Parameters
45335 +
45336 +5  Driver Parameters
45337  ====================
45338
45339  Parameters can be set at the command line after the module has been
45340 @@ -174,7 +191,7 @@
45341  to the driver module.
45342
45343  If you use the kernel module loader, you can set driver parameters
45344 -in the file /etc/modprobe.conf (or /etc/modules.conf in 2.4 or earlier).
45345 +in the file /etc/modules.conf (or old name: /etc/conf.modules).
45346  To set the driver parameters in this file, proceed as follows:
45347
45348  1. Insert a line of the form :
45349 @@ -208,7 +225,7 @@
45350        more adapters, adjust this and recompile.
45351
45352
45353 -4.1  Per-Port Parameters
45354 +5.1  Per-Port Parameters
45355  ------------------------
45356
45357  These settings are available for each port on the adapter.
45358 @@ -245,7 +262,7 @@
45359  This parameters is only relevant if auto-negotiation for this port is
45360  not set to "Sense". If auto-negotiation is set to "On", all three values
45361  are possible. If it is set to "Off", only "Full" and "Half" are allowed.
45362 -This parameter is useful if your link partner does not support all
45363 +This parameter is usefull if your link partner does not support all
45364  possible combinations.
45365
45366  Flow Control
45367 @@ -268,6 +285,18 @@
45368
45369  NOTE: This parameter is ignored if auto-negotiation is set to "Off".
45370
45371 +Broadcast Priority
45372 +-------------------
45373 +Parameter:    BroadcastPrio
45374 +Values:       On, Off
45375 +Default:      Off
45376 +
45377 +This parameter specifies whether received broadcast packets have the
45378 +highest priority for the port switch decision ("Off") or not ("On").
45379 +
45380 +NOTE: This parameter is only valid for dual port adapters.
45381 +
45382 +
45383  Role in Master-Slave-Negotiation (1000Base-T only)
45384  --------------------------------------------------
45385  Parameter:    Role_?
45386 @@ -282,13 +311,13 @@
45387  with this parameter.
45388
45389
45390 -4.2  Adapter Parameters
45391 +5.2  Adapter Parameters
45392  -----------------------
45393
45394 -Connection Type (SK-98xx V2.0 copper adapters only)
45395 +Connection Type (for copper adapters only)
45396  ---------------
45397  Parameter:    ConType
45398 -Values:       Auto, 100FD, 100HD, 10FD, 10HD
45399 +Values:       Auto, 1000FD, 100FD, 100HD, 10FD, 10HD
45400  Default:      Auto
45401
45402  The parameter 'ConType' is a combination of all five per-port parameters
45403 @@ -302,6 +331,7 @@
45404      ConType   |  DupCap   AutoNeg   FlowCtrl   Role             Speed
45405      ----------+------------------------------------------------------
45406      Auto      |  Both     On        SymOrRem   Auto             Auto
45407 +    1000FD    |  Full     Off       None       Auto (ignored)   1000
45408      100FD     |  Full     Off       None       Auto (ignored)   100
45409      100HD     |  Half     Off       None       Auto (ignored)   100
45410      10FD      |  Full     Off       None       Auto (ignored)   10
45411 @@ -379,7 +409,6 @@
45412  is tremendous. On the other hand, selecting a very short moderation time might
45413  compensate the use of any moderation being applied.
45414
45415 -
45416  Preferred Port
45417  --------------
45418  Parameter:    PrefPort
45419 @@ -394,7 +423,7 @@
45420  ------------------------------------------------
45421  Parameter:    RlmtMode
45422  Values:       CheckLinkState,CheckLocalPort, CheckSeg, DualNet
45423 -Default:      CheckLinkState
45424 +Default:      CheckLinkState (DualNet on dual port adapters)
45425
45426  RLMT monitors the status of the port. If the link of the active port
45427  fails, RLMT switches immediately to the standby link. The virtual link is
45428 @@ -429,10 +458,100 @@
45429        where a network path between the ports on one adapter exists.
45430        Moreover, they are not designed to work where adapters are connected
45431        back-to-back.
45432 +
45433 +LowLatency
45434 +----------
45435 +Parameter:    LowLatency
45436 +Values:       On, Off
45437 +Default:      Off
45438 +
45439 +This is used to reduce the packet latency time of the adapter. Setting the
45440 +LowLatency parameter to 'On' forces the adapter to pass any received packet
45441 +immediately to upper network layers and to send out any transmit packet as
45442 +fast as possible.
45443 +
45444 +NOTE 1: The system load increases if LowLatency is set to 'On' and a lot
45445 +        of data packets are transmitted and received.
45446 +
45447 +NOTE 2: This parameter is only used on adapters which are based on
45448 +        PCI Express compatible chipsets.
45449 +***
45450 +
45451 +
45452 +6  Ethtool Support
45453 +==================
45454 +
45455 +The sk98lin driver provides built-in ethtool support. The ethtool
45456 +can be used to display or modify interface specific configurations.
45457 +
45458 +Ethtool commands are invoked using a single parameter which reflects
45459 +the requested ethtool command plus an optional number of parameters
45460 +which belong to the desired command.
45461 +
45462 +It is not the intention of this section to explain the ethtool command
45463 +line tool and all its options. For further information refer to the
45464 +manpage of the ethtool.  This sections describes only the sk98lin
45465 +driver supported ethtool commands.
45466 +
45467 +Pause Parameters
45468 +----------------
45469 +Query command:  -a
45470 +Set command:    -A [autoneg on|off] [rx on|off] [tx on|off]
45471 +Sample:         ethtool -A eth0 rx off tx off
45472 +
45473 +Coalescing Parameters
45474 +---------------------
45475 +Query command:  -c
45476 +Set command:    -C [sample-interval I]
45477 +                   [rx-usecs N] [tx-usecs N]
45478 +                   [rx-usecs-low N] [tx-usecs-low N]
45479 +                   [rx-usecs-high N] [tx-usecs-high N]
45480 +Parameter:      I = Length of sample interval, in seconds
45481 +                    (supported values range from 1...10)
45482 +                N = Length of coalescing interval, in microseconds
45483 +                    (supported values range from 25...33,333)
45484 +Sample:         ethtool -C eth2 rx-usecs 500 tx-usecs 500
45485 +
45486 +NOTE: The sk98lin driver does not support different settings
45487 +      for the rx and tx interrupt coalescing parameters.
45488 +
45489 +Driver Information
45490 +------------------
45491 +Query command:  -i
45492 +Sample:         ethtool -i eth1
45493 +
45494 +Checksumming Parameters
45495 +-----------------------
45496 +Query command:  -k
45497 +Set command:    -K [rx on|off] [tx on|off] [sg on|off]
45498 +Sample:         ethtool -K eth0 sg off
45499 +
45500 +Locate NIC Command
45501 +------------------
45502 +Query command:  -p [N]
45503 +Parameter:      N = Amount of time to perform locate NIC command, in seconds
45504 +Sample:         ethtool -p 10 eth1
45505 +
45506 +Driver-specific Statistics
45507 +--------------------------
45508 +Query command:  -S
45509 +Sample:         ethtool -S eth0
45510 +
45511 +Setting Parameters
45512 +------------------
45513 +Set command:    -s [speed 10|100|1000] [duplex half|full]
45514 +                   [autoneg on|off] [wol gd]
45515 +Sample:         ethtool -s eth2 wol d
45516 +
45517 +NOTE: If cable is disconnected, please set the speed and duplex mode
45518 +      if you disable/enable autonegotiation
45519 +
45520 +NOTE: To set back to the default values use the "autoneg on" command.
45521 +      Sample:    ethtool -s eth2 autoneg on
45522  ***
45523
45524
45525 -5  Large Frame Support
45526 +7  Large Frame Support
45527  ======================
45528
45529  The driver supports large frames (also called jumbo frames). Using large
45530 @@ -444,10 +563,10 @@
45531        ifconfig eth0 mtu 9000
45532  This will only work if you have two adapters connected back-to-back
45533  or if you use a switch that supports large frames. When using a switch,
45534 -it should be configured to allow large frames and auto-negotiation should
45535 -be set to OFF. The setting must be configured on all adapters that can be
45536 -reached by the large frames. If one adapter is not set to receive large
45537 -frames, it will simply drop them.
45538 +it should be configured to allow large frames. The setting must be
45539 +configured on all adapters that can be reached by the large frames.
45540 +If one adapter is not set to receive large frames, it will simply drop
45541 +them.
45542
45543  You can switch back to the standard ethernet frame size by executing the
45544  following command:
45545 @@ -459,7 +578,7 @@
45546  ***
45547
45548
45549 -6  VLAN and Link Aggregation Support (IEEE 802.1, 802.1q, 802.3ad)
45550 +8  VLAN and Link Aggregation Support (IEEE 802.1, 802.1q, 802.3ad)
45551  ==================================================================
45552
45553  The Marvell Yukon/SysKonnect Linux drivers are able to support VLAN and
45554 @@ -477,8 +596,21 @@
45555        cause problems when unloading the driver.
45556
45557
45558 -7  Troubleshooting
45559 -==================
45560 +9  Wake on Lan support
45561 +======================
45562 +
45563 +The sk98lin driver supports wake up from suspend mode with MagicPacket
45564 +on APM systems. Wake on Lan support is enabled by default. To disable it
45565 +please use the ethtool.
45566 +
45567 +NOTE 1: APM support has to be enabled in BIOS and in the kernel.
45568 +
45569 +NOTE 2: Refer to the kernel documentation for additional requirements
45570 +        regarding APM support.
45571 +
45572 +
45573 +10  Troubleshooting
45574 +===================
45575
45576  If any problems occur during the installation process, check the
45577  following list:
45578 diff -ruN linux/drivers/net/Kconfig linux-new/drivers/net/Kconfig
45579 --- linux/drivers/net/Kconfig   2006-09-20 05:42:06.000000000 +0200
45580 +++ linux-new/drivers/net/Kconfig       2006-09-20 18:58:02.475331500 +0200
45581 @@ -2096,22 +2096,33 @@
45582           To compile this driver as a module, choose M here: the module
45583           will be called sky2.  This is recommended.
45584
45585 +
45586  config SK98LIN
45587         tristate "Marvell Yukon Chipset / SysKonnect SK-98xx Support"
45588         depends on PCI
45589         ---help---
45590           Say Y here if you have a Marvell Yukon or SysKonnect SK-98xx/SK-95xx
45591 -         compliant Gigabit Ethernet Adapter.
45592 -
45593 -         This driver supports the original Yukon chipset. A cleaner driver is
45594 -         also available (skge) which seems to work better than this one.
45595 -
45596 -         This driver does not support the newer Yukon2 chipset. A seperate
45597 -         driver, sky2, is provided to support Yukon2-based adapters.
45598 -
45599 -         The following adapters are supported by this driver:
45600 +         compliant Gigabit Ethernet Adapter. The following adapters are supported
45601 +         by this driver:
45602             - 3Com 3C940 Gigabit LOM Ethernet Adapter
45603             - 3Com 3C941 Gigabit LOM Ethernet Adapter
45604 +           - 88E8021 Marvell 1000 Mbit PCI-X, single Port Copper
45605 +           - 88E8021 Marvell 1000 Mbit PCI-X, single Port Fiber LX
45606 +           - 88E8021 Marvell 1000 Mbit PCI-X, single Port Fiber SX
45607 +           - 88E8022 Marvell 1000 Mbit PCI-X, dual Port Copper
45608 +           - 88E8022 Marvell 1000 Mbit PCI-X, dual Port Copper (Gateway)
45609 +           - 88E8022 Marvell 1000 Mbit PCI-X, dual Port Fiber LX
45610 +           - 88E8022 Marvell 1000 Mbit PCI-X, dual Port Fiber SX
45611 +           - 88E8061 Marvell 1000 Mbit PCI-E, single Port Copper
45612 +           - 88E8061 Marvell 1000 Mbit PCI-E, single Port Fiber LX
45613 +           - 88E8061 Marvell 1000 Mbit PCI-E, single Port Fiber SX
45614 +           - 88E8062 Marvell 1000 Mbit PCI-E, dual Port Copper
45615 +           - 88E8062 Marvell 1000 Mbit PCI-E, dual Port Copper (Gateway)
45616 +           - 88E8062 Marvell 1000 Mbit PCI-E, dual Port Fiber LX
45617 +           - 88E8062 Marvell 1000 Mbit PCI-E, dual Port Fiber SX
45618 +           - Abocom EFE3K - 10/100 Ethernet Expresscard
45619 +           - Abocom EGE5K - Giga Ethernet Expresscard
45620 +           - Acer 88EC042
45621             - Allied Telesyn AT-2970LX Gigabit Ethernet Adapter
45622             - Allied Telesyn AT-2970LX/2SC Gigabit Ethernet Adapter
45623             - Allied Telesyn AT-2970SX Gigabit Ethernet Adapter
45624 @@ -2121,31 +2132,85 @@
45625             - Allied Telesyn AT-2971SX Gigabit Ethernet Adapter
45626             - Allied Telesyn AT-2971T Gigabit Ethernet Adapter
45627             - Belkin Gigabit Desktop Card 10/100/1000Base-T Adapter, Copper RJ-45
45628 +           - DGE-530T Gigabit Ethernet Adapter
45629 +           - DGE-550SX Gigabit Ethernet Adapter
45630 +           - DGE-560SX Single fiber Gigabit Ethernet Adapter
45631 +           - DGE-560T Gigabit Ethernet Adapter
45632             - EG1032 v2 Instant Gigabit Network Adapter
45633             - EG1064 v2 Instant Gigabit Network Adapter
45634 -           - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Abit)
45635 -           - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Albatron)
45636 -           - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Asus)
45637 -           - Marvell 88E8001 Gigabit LOM Ethernet Adapter (ECS)
45638 -           - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Epox)
45639 -           - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Foxconn)
45640 -           - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Gigabyte)
45641 -           - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Iwill)
45642 -           - Marvell 88E8050 Gigabit LOM Ethernet Adapter (Intel)
45643 +           - Marvell 88E8001 Gigabit Ethernet Controller (Abit)
45644 +           - Marvell 88E8001 Gigabit Ethernet Controller (Albatron)
45645 +           - Marvell 88E8001 Gigabit Ethernet Controller (Asus)
45646 +           - Marvell 88E8001 Gigabit Ethernet Controller (Chaintech)
45647 +           - Marvell 88E8001 Gigabit Ethernet Controller (ECS)
45648 +           - Marvell 88E8001 Gigabit Ethernet Controller (Epox)
45649 +           - Marvell 88E8001 Gigabit Ethernet Controller (Foxconn)
45650 +           - Marvell 88E8001 Gigabit Ethernet Controller (Gigabyte)
45651 +           - Marvell 88E8001 Gigabit Ethernet Controller (Iwill)
45652 +           - Marvell 88E8035 Fast Ethernet Controller (LGE)
45653 +           - Marvell 88E8035 Fast Ethernet Controller (Toshiba)
45654 +           - Marvell 88E8036 Fast Ethernet Controller (Arima)
45655 +           - Marvell 88E8036 Fast Ethernet Controller (Compal)
45656 +           - Marvell 88E8036 Fast Ethernet Controller (Inventec)
45657 +           - Marvell 88E8036 Fast Ethernet Controller (LGE)
45658 +           - Marvell 88E8036 Fast Ethernet Controller (Mitac)
45659 +           - Marvell 88E8036 Fast Ethernet Controller (Panasonic)
45660 +           - Marvell 88E8036 Fast Ethernet Controller (Quanta)
45661 +           - Marvell 88E8036 Fast Ethernet Controller (Toshiba)
45662 +           - Marvell 88E8036 Fast Ethernet Controller (Wistron)
45663 +           - Marvell 88E8050 Gigabit Ethernet Controller (Gateway)
45664 +           - Marvell 88E8050 Gigabit Ethernet Controller (Intel)
45665 +           - Marvell 88E8052 Gigabit Ethernet Controller (ASRock)
45666 +           - Marvell 88E8052 Gigabit Ethernet Controller (Aopen)
45667 +           - Marvell 88E8052 Gigabit Ethernet Controller (Asus)
45668 +           - Marvell 88E8052 Gigabit Ethernet Controller (Gateway)
45669 +           - Marvell 88E8052 Gigabit Ethernet Controller (Gigabyte)
45670 +           - Marvell 88E8052 Gigabit Ethernet Controller (MSI)
45671 +           - Marvell 88E8052 Gigabit Ethernet Controller (Wistron)
45672 +           - Marvell 88E8053 Gigabit Ethernet Controller (ASRock)
45673 +           - Marvell 88E8053 Gigabit Ethernet Controller (Albatron)
45674 +           - Marvell 88E8053 Gigabit Ethernet Controller (Aopen)
45675 +           - Marvell 88E8053 Gigabit Ethernet Controller (Arima)
45676 +           - Marvell 88E8053 Gigabit Ethernet Controller (Asus)
45677 +           - Marvell 88E8053 Gigabit Ethernet Controller (Chaintech)
45678 +           - Marvell 88E8053 Gigabit Ethernet Controller (Clevo)
45679 +           - Marvell 88E8053 Gigabit Ethernet Controller (Compal)
45680 +           - Marvell 88E8053 Gigabit Ethernet Controller (DFI)
45681 +           - Marvell 88E8053 Gigabit Ethernet Controller (ECS)
45682 +           - Marvell 88E8053 Gigabit Ethernet Controller (Epox)
45683 +           - Marvell 88E8053 Gigabit Ethernet Controller (Gigabyte)
45684 +           - Marvell 88E8053 Gigabit Ethernet Controller (Inventec)
45685 +           - Marvell 88E8053 Gigabit Ethernet Controller (LGE)
45686 +           - Marvell 88E8053 Gigabit Ethernet Controller (MSI)
45687 +           - Marvell 88E8053 Gigabit Ethernet Controller (Mitac)
45688 +           - Marvell 88E8053 Gigabit Ethernet Controller (Panasonic)
45689 +           - Marvell 88E8053 Gigabit Ethernet Controller (Quanta)
45690 +           - Marvell 88E8053 Gigabit Ethernet Controller (SOYO)
45691 +           - Marvell 88E8053 Gigabit Ethernet Controller (Shuttle)
45692 +           - Marvell 88E8053 Gigabit Ethernet Controller (Toshiba)
45693 +           - Marvell 88E8053 Gigabit Ethernet Controller (Trigem)
45694 +           - Marvell RDK-8001
45695             - Marvell RDK-8001 Adapter
45696             - Marvell RDK-8002 Adapter
45697 +           - Marvell RDK-8003
45698             - Marvell RDK-8003 Adapter
45699             - Marvell RDK-8004 Adapter
45700             - Marvell RDK-8006 Adapter
45701             - Marvell RDK-8007 Adapter
45702             - Marvell RDK-8008 Adapter
45703             - Marvell RDK-8009 Adapter
45704 -           - Marvell RDK-8010 Adapter
45705 +           - Marvell RDK-8010
45706             - Marvell RDK-8011 Adapter
45707             - Marvell RDK-8012 Adapter
45708 -           - Marvell RDK-8052 Adapter
45709 -           - Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Adapter (32 bit)
45710 -           - Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Adapter (64 bit)
45711 +           - Marvell RDK-8035
45712 +           - Marvell RDK-8036
45713 +           - Marvell RDK-8052
45714 +           - Marvell RDK-8053
45715 +           - Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Controller (32 bit)
45716 +           - Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Controller (64 bit)
45717 +           - Marvell Yukon PCI-E Fast Ethernet
45718 +           - Marvell Yukon-EC Ultra, no ASF (Battery Power Service Support)
45719 +           - Marvell Yukon-FE Fast Ethernet, Reduced Battery Power Service Support)
45720             - N-Way PCI-Bus Giga-Card 1000/100/10Mbps(L)
45721             - SK-9521 10/100/1000Base-T Adapter
45722             - SK-9521 V2.0 10/100/1000Base-T Adapter
45723 @@ -2165,21 +2230,37 @@
45724             - SK-9871 Gigabit Ethernet Server Adapter (SK-NET GE-ZX)
45725             - SK-9871 V2.0 Gigabit Ethernet 1000Base-ZX Adapter
45726             - SK-9872 Gigabit Ethernet Server Adapter (SK-NET GE-ZX dual link)
45727 +           - SK-9S21 Server Adapter
45728 +           - SK-9S22 Server Adapter
45729 +           - SK-9S24 Server Adapter
45730 +           - SK-9S34 Server Adapter
45731 +           - SK-9S81 Server Adapter
45732 +           - SK-9S82 Server Adapter
45733 +           - SK-9S91 Server Adapter
45734 +           - SK-9S92 Server Adapter
45735             - SMC EZ Card 1000 (SMC9452TXV.2)
45736
45737           The adapters support Jumbo Frames.
45738           The dual link adapters support link-failover and dual port features.
45739           Both Marvell Yukon and SysKonnect SK-98xx/SK-95xx adapters support
45740           the scatter-gather functionality with sendfile(). Please refer to
45741 -         <file:Documentation/networking/sk98lin.txt> for more information about
45742 +         Documentation/networking/sk98lin.txt for more information about
45743           optional driver parameters.
45744           Questions concerning this driver may be addressed to:
45745 -             <linux@syskonnect.de>
45746 +             linux@syskonnect.de
45747
45748           If you want to compile this driver as a module ( = code which can be
45749           inserted in and removed from the running kernel whenever you want),
45750 -         say M here and read <file:Documentation/kbuild/modules.txt>. The module will
45751 -         be called sk98lin. This is recommended.
45752 +         say M here and read Documentation/modules.txt. This is recommended.
45753 +         The module will be called sk98lin. This is recommended.
45754 +
45755 +config SK98LIN_NAPI
45756 +       bool "Use Rx polling (NAPI)"
45757 +       depends on SK98LIN
45758 +       help
45759 +         NAPI is a new driver API designed to reduce CPU and interrupt load
45760 +         when the driver is receiving lots of packets from the card.
45761 +
45762
45763  config VIA_VELOCITY
45764         tristate "VIA Velocity support"