1 diff -ruN linux/drivers/net/sk98lin/Makefile linux-new/drivers/net/sk98lin/Makefile
2 --- linux/drivers/net/sk98lin/Makefile 2006-09-20 05:42:06.000000000 +0200
3 +++ linux-new/drivers/net/sk98lin/Makefile 2006-09-20 18:58:01.423265750 +0200
5 +#******************************************************************************
7 -# Makefile for the SysKonnect SK-98xx device driver.
9 +# Project: GEnesis, PCI Gigabit Ethernet Adapter
10 +# Version: $Revision$
12 +# Purpose: The main driver source module
14 +#******************************************************************************
16 +#******************************************************************************
18 +# (C)Copyright 1998-2002 SysKonnect GmbH.
19 +# (C)Copyright 2002-2005 Marvell.
21 +# Makefile for Marvell Yukon chipset and SysKonnect Gigabit Ethernet
22 +# Server Adapter driver. (Kernel 2.6)
24 +# Author: Mirko Lindner (mlindner@syskonnect.de)
25 +# Ralph Roesler (rroesler@syskonnect.de)
27 +# Address all question to: linux@syskonnect.de
29 +# This program is free software; you can redistribute it and/or modify
30 +# it under the terms of the GNU General Public License as published by
31 +# the Free Software Foundation; either version 2 of the License, or
32 +# (at your option) any later version.
34 +# The information in this file is provided "AS IS" without warranty.
36 +#******************************************************************************
38 +#******************************************************************************
43 +# Revision 1.9.2.1 2005/04/11 09:01:18 mlindner
44 +# Fix: Copyright year changed
46 +# Revision 1.9 2004/07/13 15:54:50 rroesler
47 +# Add: file skethtool.c
48 +# Fix: corrected header regarding copyright
49 +# Fix: minor typos corrected
51 +# Revision 1.8 2004/06/08 08:39:38 mlindner
52 +# Fix: Add CONFIG_SK98LIN_ZEROCOPY as default
54 +# Revision 1.7 2004/06/03 16:06:56 mlindner
55 +# Fix: Added compile flag SK_DIAG_SUPPORT
57 +# Revision 1.6 2004/06/02 08:02:59 mlindner
58 +# Add: Changed header information and inserted a GPL statement
61 +#******************************************************************************
66 obj-$(CONFIG_SK98LIN) += sk98lin.o
93 # SK_DBGCAT_DRV_INT_SRC 0x04000000 interrupts sources
94 # SK_DBGCAT_DRV_EVENT 0x08000000 driver events
96 -EXTRA_CFLAGS += -Idrivers/net/sk98lin -DSK_DIAG_SUPPORT -DGENESIS -DYUKON $(DBGDEF) $(SKPARAM)
97 +EXTRA_CFLAGS += -Idrivers/net/sk98lin -DSK_USE_CSUM -DSK_DIAG_SUPPORT \
98 + -DGENESIS -DYUKON -DYUK2 -DCONFIG_SK98LIN_ZEROCOPY \
99 + $(DBGDEF) $(SKPARAM)
102 rm -f core *.o *.a *.s
109 diff -ruN linux/drivers/net/sk98lin/h/lm80.h linux-new/drivers/net/sk98lin/h/lm80.h
110 --- linux/drivers/net/sk98lin/h/lm80.h 2006-09-20 05:42:06.000000000 +0200
111 +++ linux-new/drivers/net/sk98lin/h/lm80.h 2006-07-28 14:13:54.000000000 +0200
115 * Project: Gigabit Ethernet Adapters, Common Modules
116 - * Version: $Revision$
118 + * Version: $Revision$
120 * Purpose: Contains all defines for the LM80 Chip
121 * (National Semiconductor).
125 /******************************************************************************
128 * (C)Copyright 1998-2002 SysKonnect.
129 * (C)Copyright 2002-2003 Marvell.
132 * (at your option) any later version.
134 * The information in this file is provided "AS IS" without warranty.
137 ******************************************************************************/
139 diff -ruN linux/drivers/net/sk98lin/h/skaddr.h linux-new/drivers/net/sk98lin/h/skaddr.h
140 --- linux/drivers/net/sk98lin/h/skaddr.h 2006-09-20 05:42:06.000000000 +0200
141 +++ linux-new/drivers/net/sk98lin/h/skaddr.h 2006-07-28 14:13:54.000000000 +0200
145 * Project: Gigabit Ethernet Adapters, ADDR-Modul
146 - * Version: $Revision$
148 + * Version: $Revision$
150 * Purpose: Header file for Address Management (MC, UC, Prom).
152 ******************************************************************************/
154 /******************************************************************************
157 * (C)Copyright 1998-2002 SysKonnect GmbH.
158 * (C)Copyright 2002-2003 Marvell.
161 * (at your option) any later version.
163 * The information in this file is provided "AS IS" without warranty.
166 ******************************************************************************/
172 +extern int SkAddrXmacMcClear(
178 +extern int SkAddrGmacMcClear(
184 extern int SkAddrMcAdd(
187 @@ -243,11 +257,41 @@
191 +extern int SkAddrXmacMcAdd(
198 +extern SK_U32 SkXmacMcHash(
199 + unsigned char *pMc);
201 +extern int SkAddrGmacMcAdd(
208 +extern SK_U32 SkGmacMcHash(
209 + unsigned char *pMc);
211 extern int SkAddrMcUpdate(
216 +extern int SkAddrXmacMcUpdate(
219 + SK_U32 PortNumber);
221 +extern int SkAddrGmacMcUpdate(
224 + SK_U32 PortNumber);
226 extern int SkAddrOverride(
233 +extern int SkAddrXmacPromiscuousChange(
239 +extern int SkAddrGmacPromiscuousChange(
246 extern int SkAddrSwap(
248 diff -ruN linux/drivers/net/sk98lin/h/skcsum.h linux-new/drivers/net/sk98lin/h/skcsum.h
249 --- linux/drivers/net/sk98lin/h/skcsum.h 2006-09-20 05:42:06.000000000 +0200
250 +++ linux-new/drivers/net/sk98lin/h/skcsum.h 2006-07-28 14:13:54.000000000 +0200
254 * Project: GEnesis - SysKonnect SK-NET Gigabit Ethernet (SK-98xx)
255 - * Version: $Revision$
257 + * Version: $Revision$
259 * Purpose: Store/verify Internet checksum in send/receive packets.
261 ******************************************************************************/
263 /******************************************************************************
266 * (C)Copyright 1998-2001 SysKonnect GmbH.
268 * This program is free software; you can redistribute it and/or modify
270 * (at your option) any later version.
272 * The information in this file is provided "AS IS" without warranty.
275 ******************************************************************************/
278 typedef struct s_Csum {
279 /* Enabled receive SK_PROTO_XXX bit flags. */
280 unsigned ReceiveFlags[SK_MAX_NETS];
282 unsigned TransmitFlags[SK_MAX_NETS];
283 -#endif /* TX_CSUM */
285 /* The protocol statistics structure; one per supported protocol. */
286 SKCS_PROTO_STATS ProtoStats[SK_MAX_NETS][SKCS_NUM_PROTOCOLS];
291 +extern void SkCsGetSendInfo(
294 + SKCS_PACKET_INFO *pPacketInfo,
297 extern void SkCsSetReceiveFlags(
299 unsigned ReceiveFlags,
300 diff -ruN linux/drivers/net/sk98lin/h/skdebug.h linux-new/drivers/net/sk98lin/h/skdebug.h
301 --- linux/drivers/net/sk98lin/h/skdebug.h 2006-09-20 05:42:06.000000000 +0200
302 +++ linux-new/drivers/net/sk98lin/h/skdebug.h 2006-07-28 14:13:54.000000000 +0200
306 * Project: Gigabit Ethernet Adapters, Common Modules
307 - * Version: $Revision$
309 + * Version: $Revision$
311 * Purpose: SK specific DEBUG support
313 ******************************************************************************/
315 /******************************************************************************
318 * (C)Copyright 1998-2002 SysKonnect.
319 - * (C)Copyright 2002-2003 Marvell.
320 + * (C)Copyright 2002-2005 Marvell.
322 * This program is free software; you can redistribute it and/or modify
323 * it under the terms of the GNU General Public License as published by
324 * the Free Software Foundation; either version 2 of the License, or
325 * (at your option) any later version.
327 * The information in this file is provided "AS IS" without warranty.
330 ******************************************************************************/
335 #define SK_DBG_MSG(pAC,comp,cat,arg) \
336 - if ( ((comp) & SK_DBG_CHKMOD(pAC)) && \
337 - ((cat) & SK_DBG_CHKCAT(pAC)) ) { \
338 - SK_DBG_PRINTF arg ; \
339 + if ( ((comp) & SK_DBG_CHKMOD(pAC)) && \
340 + ((cat) & SK_DBG_CHKCAT(pAC)) ) { \
341 + SK_DBG_PRINTF arg; \
346 #define SK_DBGMOD_ADDR 0x00000080L /* ADDR module */
347 #define SK_DBGMOD_PECP 0x00000100L /* PECP module */
348 #define SK_DBGMOD_POWM 0x00000200L /* Power Management module */
350 +#define SK_DBGMOD_ASF 0x00000400L /* ASF module */
353 +#define SK_DBGMOD_LACP 0x00000800L /* link aggregation control protocol */
354 +#define SK_DBGMOD_FD 0x00001000L /* frame distributor (link aggregation) */
355 +#endif /* SK_LBFO */
359 diff -ruN linux/drivers/net/sk98lin/h/skdrv1st.h linux-new/drivers/net/sk98lin/h/skdrv1st.h
360 --- linux/drivers/net/sk98lin/h/skdrv1st.h 2006-09-20 05:42:06.000000000 +0200
361 +++ linux-new/drivers/net/sk98lin/h/skdrv1st.h 2006-07-28 14:13:56.000000000 +0200
365 * Project: GEnesis, PCI Gigabit Ethernet Adapter
366 - * Version: $Revision$
368 + * Version: $Revision$
370 * Purpose: First header file for driver and all other modules
372 ******************************************************************************/
374 /******************************************************************************
376 * (C)Copyright 1998-2002 SysKonnect GmbH.
377 - * (C)Copyright 2002-2003 Marvell.
378 + * (C)Copyright 2002-2005 Marvell.
380 * This program is free software; you can redistribute it and/or modify
381 * it under the terms of the GNU General Public License as published by
384 ******************************************************************************/
386 -/******************************************************************************
390 - * This is the first include file of the driver, which includes all
391 - * neccessary system header files and some of the GEnesis header files.
392 - * It also defines some basic items.
394 - * Include File Hierarchy:
398 - ******************************************************************************/
400 #ifndef __INC_SKDRV1ST_H
401 #define __INC_SKDRV1ST_H
403 +/* Check kernel version */
404 +#include <linux/version.h>
406 typedef struct s_AC SK_AC;
408 /* Set card versions */
411 #define SK_ADDR_EQUAL(a1,a2) (!memcmp(a1,a2,6))
413 +#define SK_STRNCMP(s1,s2,len) strncmp(s1,s2,len)
414 +#define SK_STRCPY(dest,src) strcpy(dest,src)
416 #include <linux/types.h>
417 #include <linux/kernel.h>
418 #include <linux/string.h>
420 #include <linux/slab.h>
421 #include <linux/interrupt.h>
422 #include <linux/pci.h>
423 -#include <linux/bitops.h>
424 #include <asm/byteorder.h>
425 +#include <asm/bitops.h>
427 -#include <asm/irq.h>
428 #include <linux/netdevice.h>
429 #include <linux/etherdevice.h>
430 #include <linux/skbuff.h>
432 #include <net/checksum.h>
434 #define SK_CS_CALCULATE_CHECKSUM
435 -#ifndef CONFIG_X86_64
436 -#define SkCsCalculateChecksum(p,l) ((~ip_compute_csum(p, l)) & 0xffff)
438 -#define SkCsCalculateChecksum(p,l) ((~ip_fast_csum(p, l)) & 0xffff)
440 +#define SkCsCalculateChecksum(p,l) (~csum_fold(csum_partial(p, l, 0)))
442 #include "h/sktypes.h"
443 #include "h/skerror.h"
446 #include "h/xmac_ii.h"
448 +#ifndef SK_BMU_RX_WM_PEX
449 +#define SK_BMU_RX_WM_PEX 0x80
452 #ifdef __LITTLE_ENDIAN
453 #define SK_LITTLE_ENDIAN
455 #define SK_BIG_ENDIAN
456 +#define SK_USE_REV_DESC
459 #define SK_NET_DEVICE net_device
461 #define SK_MAX_MACS 2
462 #define SK_MAX_NETS 2
464 -#define SK_IOC char __iomem *
465 +#define SK_IOC char*
467 typedef struct s_DrvRlmtMbuf SK_MBUF;
473 +/*******************************************************************************
477 + ******************************************************************************/
478 diff -ruN linux/drivers/net/sk98lin/h/skdrv2nd.h linux-new/drivers/net/sk98lin/h/skdrv2nd.h
479 --- linux/drivers/net/sk98lin/h/skdrv2nd.h 2006-09-20 05:42:06.000000000 +0200
480 +++ linux-new/drivers/net/sk98lin/h/skdrv2nd.h 2006-07-28 14:13:56.000000000 +0200
482 /******************************************************************************
485 - * Project: GEnesis, PCI Gigabit Ethernet Adapter
486 - * Version: $Revision$
488 - * Purpose: Second header file for driver and all other modules
490 + * Project: GEnesis, PCI Gigabit Ethernet Adapter
491 + * Version: $Revision$
493 + * Purpose: Second header file for driver and all other modules
495 ******************************************************************************/
497 /******************************************************************************
499 * (C)Copyright 1998-2002 SysKonnect GmbH.
500 - * (C)Copyright 2002-2003 Marvell.
501 + * (C)Copyright 2002-2005 Marvell.
503 * This program is free software; you can redistribute it and/or modify
504 * it under the terms of the GNU General Public License as published by
506 #include "h/skqueue.h"
507 #include "h/skgehwt.h"
508 #include "h/sktimer.h"
509 -#include "h/ski2c.h"
510 +#include "h/sktwsi.h"
511 #include "h/skgepnmi.h"
513 #include "h/skgehw.h"
514 +#include "h/sky2le.h"
515 #include "h/skgeinit.h"
516 #include "h/skaddr.h"
517 #include "h/skgesirq.h"
518 @@ -53,103 +54,191 @@
519 #include "h/skrlmt.h"
520 #include "h/skgedrv.h"
522 +/* Defines for the poll cotroller */
523 +#define SK_NETDUMP_POLL
525 -extern SK_MBUF *SkDrvAllocRlmtMbuf(SK_AC*, SK_IOC, unsigned);
526 -extern void SkDrvFreeRlmtMbuf(SK_AC*, SK_IOC, SK_MBUF*);
527 -extern SK_U64 SkOsGetTime(SK_AC*);
528 -extern int SkPciReadCfgDWord(SK_AC*, int, SK_U32*);
529 -extern int SkPciReadCfgWord(SK_AC*, int, SK_U16*);
530 -extern int SkPciReadCfgByte(SK_AC*, int, SK_U8*);
531 -extern int SkPciWriteCfgWord(SK_AC*, int, SK_U16);
532 -extern int SkPciWriteCfgByte(SK_AC*, int, SK_U8);
533 -extern int SkDrvEvent(SK_AC*, SK_IOC IoC, SK_U32, SK_EVPARA);
535 -#ifdef SK_DIAG_SUPPORT
536 -extern int SkDrvEnterDiagMode(SK_AC *pAc);
537 -extern int SkDrvLeaveDiagMode(SK_AC *pAc);
538 +#ifdef SK_NETDUMP_POLL
539 +#ifdef HAVE_POLL_CONTROLLER
540 +#define SK_POLL_CONTROLLER
541 +#define CONFIG_SK98LIN_NAPI
542 +#elif CONFIG_NET_POLL_CONTROLLER
543 +#define SK_POLL_CONTROLLER
544 +#define CONFIG_SK98LIN_NAPI
549 +/******************************************************************************
551 + * Generic driver defines
553 + ******************************************************************************/
555 +#define USE_TIST_FOR_RESET /* Use timestamp for reset */
556 +#define Y2_RECOVERY /* use specific recovery yukon2 functions */
557 +#define Y2_LE_CHECK /* activate check for LE order */
558 +#define Y2_SYNC_CHECK /* activate check for receiver in sync */
559 +#define SK_YUKON2 /* Enable Yukon2 dual net support */
560 +#define USE_SK_TX_CHECKSUM /* use the tx hw checksum driver functionality */
561 +#define USE_SK_RX_CHECKSUM /* use the rx hw checksum driver functionality */
562 +#define USE_SK_TSO_FEATURE /* use TCP segmentation offload if possible */
563 +#define SK_COPY_THRESHOLD 50 /* threshold for copying small RX frames;
564 + * 0 avoids copying, 9001 copies all */
565 +#define SK_MAX_CARD_PARAM 16 /* number of adapters that can be configured via
566 + * command line params */
567 +//#define USE_TX_COMPLETE /* use of a transmit complete interrupt */
568 +#define Y2_RX_CHECK /* RX Check timestamp */
571 + * use those defines for a compile-in version of the driver instead
572 + * of command line parameters
574 +// #define LINK_SPEED_A {"Auto",}
575 +// #define LINK_SPEED_B {"Auto",}
576 +// #define AUTO_NEG_A {"Sense",}
577 +// #define AUTO_NEG_B {"Sense"}
578 +// #define DUP_CAP_A {"Both",}
579 +// #define DUP_CAP_B {"Both",}
580 +// #define FLOW_CTRL_A {"SymOrRem",}
581 +// #define FLOW_CTRL_B {"SymOrRem",}
582 +// #define ROLE_A {"Auto",}
583 +// #define ROLE_B {"Auto",}
584 +// #define PREF_PORT {"A",}
585 +// #define CON_TYPE {"Auto",}
586 +// #define RLMT_MODE {"CheckLinkState",}
589 +#define CHECK_TRANSMIT_TIMEOUT
590 +#define Y2_RESYNC_WATERMARK 1000000L
594 +/******************************************************************************
596 + * Generic ISR defines
598 + ******************************************************************************/
600 +#define SkIsrRetVar irqreturn_t
601 +#define SkIsrRetNone IRQ_NONE
602 +#define SkIsrRetHandled IRQ_HANDLED
604 +#define DEV_KFREE_SKB(skb) dev_kfree_skb(skb)
605 +#define DEV_KFREE_SKB_IRQ(skb) dev_kfree_skb_irq(skb)
606 +#define DEV_KFREE_SKB_ANY(skb) dev_kfree_skb_any(skb)
608 +/******************************************************************************
610 + * Global function prototypes
612 + ******************************************************************************/
614 +extern SK_MBUF *SkDrvAllocRlmtMbuf(SK_AC*, SK_IOC, unsigned);
615 +extern void SkDrvFreeRlmtMbuf(SK_AC*, SK_IOC, SK_MBUF*);
616 +extern SK_U64 SkOsGetTime(SK_AC*);
617 +extern int SkPciReadCfgDWord(SK_AC*, int, SK_U32*);
618 +extern int SkPciReadCfgWord(SK_AC*, int, SK_U16*);
619 +extern int SkPciReadCfgByte(SK_AC*, int, SK_U8*);
620 +extern int SkPciWriteCfgDWord(SK_AC*, int, SK_U32);
621 +extern int SkPciWriteCfgWord(SK_AC*, int, SK_U16);
622 +extern int SkPciWriteCfgByte(SK_AC*, int, SK_U8);
623 +extern int SkDrvEvent(SK_AC*, SK_IOC IoC, SK_U32, SK_EVPARA);
624 +extern int SkDrvEnterDiagMode(SK_AC *pAc);
625 +extern int SkDrvLeaveDiagMode(SK_AC *pAc);
627 +/******************************************************************************
629 + * Linux specific RLMT buffer structure (SK_MBUF typedef in skdrv1st)!
631 + ******************************************************************************/
633 struct s_DrvRlmtMbuf {
634 - SK_MBUF *pNext; /* Pointer to next RLMT Mbuf. */
635 - SK_U8 *pData; /* Data buffer (virtually contig.). */
636 - unsigned Size; /* Data buffer size. */
637 - unsigned Length; /* Length of packet (<= Size). */
638 - SK_U32 PortIdx; /* Receiving/transmitting port. */
639 + SK_MBUF *pNext; /* Pointer to next RLMT Mbuf. */
640 + SK_U8 *pData; /* Data buffer (virtually contig.). */
641 + unsigned Size; /* Data buffer size. */
642 + unsigned Length; /* Length of packet (<= Size). */
643 + SK_U32 PortIdx; /* Receiving/transmitting port. */
644 #ifdef SK_RLMT_MBUF_PRIVATE
645 - SK_RLMT_MBUF Rlmt; /* Private part for RLMT. */
646 -#endif /* SK_RLMT_MBUF_PRIVATE */
647 - struct sk_buff *pOs; /* Pointer to message block */
648 + SK_RLMT_MBUF Rlmt; /* Private part for RLMT. */
650 + struct sk_buff *pOs; /* Pointer to message block */
653 +/******************************************************************************
655 + * Linux specific TIME defines
657 + ******************************************************************************/
662 #if SK_TICKS_PER_SEC == 100
663 #define SK_PNMI_HUNDREDS_SEC(t) (t)
665 -#define SK_PNMI_HUNDREDS_SEC(t) ((((unsigned long)t) * 100) / \
666 - (SK_TICKS_PER_SEC))
667 +#define SK_PNMI_HUNDREDS_SEC(t) ((((unsigned long)t)*100)/(SK_TICKS_PER_SEC))
673 #define SkOsGetTimeCurrent(pAC, pUsec) {\
674 + static struct timeval prev_t; \
676 do_gettimeofday(&t);\
677 - *pUsec = ((((t.tv_sec) * 1000000L)+t.tv_usec)/10000);\
678 + if (prev_t.tv_sec == t.tv_sec) { \
679 + if (prev_t.tv_usec > t.tv_usec) { \
680 + t.tv_usec = prev_t.tv_usec; \
682 + prev_t.tv_usec = t.tv_usec; \
687 + *pUsec = ((t.tv_sec*100L)+(t.tv_usec/10000));\
690 +/******************************************************************************
692 + * Linux specific IOCTL defines and typedefs
694 + ******************************************************************************/
697 - * ioctl definitions
699 -#define SK_IOCTL_BASE (SIOCDEVPRIVATE)
700 -#define SK_IOCTL_GETMIB (SK_IOCTL_BASE + 0)
701 -#define SK_IOCTL_SETMIB (SK_IOCTL_BASE + 1)
702 -#define SK_IOCTL_PRESETMIB (SK_IOCTL_BASE + 2)
703 -#define SK_IOCTL_GEN (SK_IOCTL_BASE + 3)
704 -#define SK_IOCTL_DIAG (SK_IOCTL_BASE + 4)
706 -typedef struct s_IOCTL SK_GE_IOCTL;
707 +#define SK_IOCTL_BASE (SIOCDEVPRIVATE)
708 +#define SK_IOCTL_GETMIB (SK_IOCTL_BASE + 0)
709 +#define SK_IOCTL_SETMIB (SK_IOCTL_BASE + 1)
710 +#define SK_IOCTL_PRESETMIB (SK_IOCTL_BASE + 2)
711 +#define SK_IOCTL_GEN (SK_IOCTL_BASE + 3)
712 +#define SK_IOCTL_DIAG (SK_IOCTL_BASE + 4)
714 +typedef struct s_IOCTL SK_GE_IOCTL;
720 +/******************************************************************************
722 + * Generic sizes and length definitions
724 + ******************************************************************************/
727 - * define sizes of descriptor rings in bytes
730 -#define TX_RING_SIZE (8*1024)
731 -#define RX_RING_SIZE (24*1024)
734 - * Buffer size for ethernet packets
736 -#define ETH_BUF_SIZE 1540
737 -#define ETH_MAX_MTU 1514
738 -#define ETH_MIN_MTU 60
739 -#define ETH_MULTICAST_BIT 0x01
740 -#define SK_JUMBO_MTU 9000
743 - * transmit priority selects the queue: LOW=asynchron, HIGH=synchron
745 -#define TX_PRIO_LOW 0
746 -#define TX_PRIO_HIGH 1
747 +#define TX_RING_SIZE (24*1024) /* GEnesis/Yukon */
748 +#define RX_RING_SIZE (24*1024) /* GEnesis/Yukon */
749 +#define RX_MAX_NBR_BUFFERS 128 /* Yukon-EC/-II */
750 +#define TX_MAX_NBR_BUFFERS 128 /* Yukon-EC/-II */
751 +#define MAXIMUM_LOW_ADDRESS 0xFFFFFFFF /* Max. low address */
753 +#define ETH_BUF_SIZE 1560 /* multiples of 8 bytes */
754 +#define ETH_MAX_MTU 1514
755 +#define ETH_MIN_MTU 60
756 +#define ETH_MULTICAST_BIT 0x01
757 +#define SK_JUMBO_MTU 9000
759 +#define TX_PRIO_LOW 0 /* asynchronous queue */
760 +#define TX_PRIO_HIGH 1 /* synchronous queue */
761 +#define DESCR_ALIGN 64 /* alignment of Rx/Tx descriptors */
764 - * alignment of rx/tx descriptors
766 -#define DESCR_ALIGN 64
767 +/******************************************************************************
769 + * PNMI related definitions
771 + ******************************************************************************/
774 - * definitions for pnmi. TODO
776 #define SK_DRIVER_RESET(pAC, IoC) 0
777 #define SK_DRIVER_SENDEVENT(pAC, IoC) 0
778 #define SK_DRIVER_SELFTEST(pAC, IoC) 0
779 @@ -158,20 +247,16 @@
780 #define SK_DRIVER_SET_MTU(pAc,IoC,i,v) 0
781 #define SK_DRIVER_PRESET_MTU(pAc,IoC,i,v) 0
784 -** Interim definition of SK_DRV_TIMER placed in this file until
785 -** common modules have boon finallized
787 -#define SK_DRV_TIMER 11
788 -#define SK_DRV_MODERATION_TIMER 1
789 -#define SK_DRV_MODERATION_TIMER_LENGTH 1000000 /* 1 second */
790 -#define SK_DRV_RX_CLEANUP_TIMER 2
791 -#define SK_DRV_RX_CLEANUP_TIMER_LENGTH 1000000 /* 100 millisecs */
794 -** Definitions regarding transmitting frames
795 -** any calculating any checksum.
797 +/******************************************************************************
799 + * Various offsets and sizes
801 + ******************************************************************************/
803 +#define SK_DRV_MODERATION_TIMER 1 /* id */
804 +#define SK_DRV_MODERATION_TIMER_LENGTH 1 /* 1 second */
806 #define C_LEN_ETHERMAC_HEADER_DEST_ADDR 6
807 #define C_LEN_ETHERMAC_HEADER_SRC_ADDR 6
808 #define C_LEN_ETHERMAC_HEADER_LENTYPE 2
809 @@ -197,112 +282,445 @@
810 #define C_PROTO_ID_UDP 17 /* refer to RFC 790 or Stevens' */
811 #define C_PROTO_ID_TCP 6 /* TCP/IP illustrated for details */
813 -/* TX and RX descriptors *****************************************************/
814 +/******************************************************************************
816 + * Tx and Rx descriptor definitions
818 + ******************************************************************************/
820 typedef struct s_RxD RXD; /* the receive descriptor */
823 - volatile SK_U32 RBControl; /* Receive Buffer Control */
824 - SK_U32 VNextRxd; /* Next receive descriptor,low dword */
825 - SK_U32 VDataLow; /* Receive buffer Addr, low dword */
826 - SK_U32 VDataHigh; /* Receive buffer Addr, high dword */
827 - SK_U32 FrameStat; /* Receive Frame Status word */
828 - SK_U32 TimeStamp; /* Time stamp from XMAC */
829 - SK_U32 TcpSums; /* TCP Sum 2 / TCP Sum 1 */
830 - SK_U32 TcpSumStarts; /* TCP Sum Start 2 / TCP Sum Start 1 */
831 - RXD *pNextRxd; /* Pointer to next Rxd */
832 - struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */
833 + volatile SK_U32 RBControl; /* Receive Buffer Control */
834 + SK_U32 VNextRxd; /* Next receive descriptor,low dword */
835 + SK_U32 VDataLow; /* Receive buffer Addr, low dword */
836 + SK_U32 VDataHigh; /* Receive buffer Addr, high dword */
837 + SK_U32 FrameStat; /* Receive Frame Status word */
838 + SK_U32 TimeStamp; /* Time stamp from XMAC */
839 + SK_U32 TcpSums; /* TCP Sum 2 / TCP Sum 1 */
840 + SK_U32 TcpSumStarts; /* TCP Sum Start 2 / TCP Sum Start 1 */
841 + RXD *pNextRxd; /* Pointer to next Rxd */
842 + struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */
845 typedef struct s_TxD TXD; /* the transmit descriptor */
848 - volatile SK_U32 TBControl; /* Transmit Buffer Control */
849 - SK_U32 VNextTxd; /* Next transmit descriptor,low dword */
850 - SK_U32 VDataLow; /* Transmit Buffer Addr, low dword */
851 - SK_U32 VDataHigh; /* Transmit Buffer Addr, high dword */
852 - SK_U32 FrameStat; /* Transmit Frame Status Word */
853 - SK_U32 TcpSumOfs; /* Reserved / TCP Sum Offset */
854 - SK_U16 TcpSumSt; /* TCP Sum Start */
855 - SK_U16 TcpSumWr; /* TCP Sum Write */
856 - SK_U32 TcpReserved; /* not used */
857 - TXD *pNextTxd; /* Pointer to next Txd */
858 - struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */
859 + volatile SK_U32 TBControl; /* Transmit Buffer Control */
860 + SK_U32 VNextTxd; /* Next transmit descriptor,low dword */
861 + SK_U32 VDataLow; /* Transmit Buffer Addr, low dword */
862 + SK_U32 VDataHigh; /* Transmit Buffer Addr, high dword */
863 + SK_U32 FrameStat; /* Transmit Frame Status Word */
864 + SK_U32 TcpSumOfs; /* Reserved / TCP Sum Offset */
865 + SK_U16 TcpSumSt; /* TCP Sum Start */
866 + SK_U16 TcpSumWr; /* TCP Sum Write */
867 + SK_U32 TcpReserved; /* not used */
868 + TXD *pNextTxd; /* Pointer to next Txd */
869 + struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */
872 +/******************************************************************************
874 + * Generic Yukon-II defines
876 + ******************************************************************************/
878 +#define LE_SIZE sizeof(SK_HWLE)
879 +#define MAX_NUM_FRAGS (MAX_SKB_FRAGS + 1)
880 +#define MIN_LEN_OF_LE_TAB 128
881 +#define MAX_LEN_OF_LE_TAB 4096
882 +#define MAX_UNUSED_RX_LE_WORKING 8
883 +#ifdef MAX_FRAG_OVERHEAD
884 +#undef MAX_FRAG_OVERHEAD
885 +#define MAX_FRAG_OVERHEAD 4
887 +// as we have a maximum of 16 physical fragments,
888 +// maximum 1 ADDR64 per physical fragment
889 +// maximum 4 LEs for VLAN, Csum, LargeSend, Packet
890 +#define MIN_LE_FREE_REQUIRED ((16*2) + 4)
891 +#define IS_GMAC(pAc) (!pAc->GIni.GIGenesis)
892 +#ifdef USE_SYNC_TX_QUEUE
893 +#define TXS_MAX_LE 256
894 +#else /* !USE_SYNC_TX_QUEUE */
895 +#define TXS_MAX_LE 0
898 +#define ETHER_MAC_HDR_LEN (6+6+2) // MAC SRC ADDR, MAC DST ADDR, TYPE
899 +#define IP_HDR_LEN 20
900 +#define TCP_CSUM_OFFS 0x10
901 +#define UDP_CSUM_OFFS 0x06
902 +#define TXA_MAX_LE 256
903 +#define RX_MAX_LE 256
904 +#define ST_MAX_LE (SK_MAX_MACS)*((3*RX_MAX_LE)+(TXA_MAX_LE)+(TXS_MAX_LE))
906 +#if (defined (Y2_RECOVERY) || defined (Y2_LE_CHECK))
907 +/* event for recovery from tx hang or rx out of sync */
908 +#define SK_DRV_RECOVER 17
910 +/******************************************************************************
912 + * Structures specific for Yukon-II
914 + ******************************************************************************/
916 +typedef struct s_frag SK_FRAG;
921 + unsigned int FragLen;
924 -/* Used interrupt bits in the interrupts source register *********************/
925 +typedef struct s_packet SK_PACKET;
927 + /* Common infos: */
928 + SK_PACKET *pNext; /* pointer for packet queues */
929 + unsigned int PacketLen; /* length of packet */
930 + unsigned int NumFrags; /* nbr of fragments (for Rx always 1) */
931 + SK_FRAG *pFrag; /* fragment list */
932 + SK_FRAG FragArray[MAX_NUM_FRAGS]; /* TX fragment array */
933 + unsigned int NextLE; /* next LE to use for the next packet */
935 + /* Private infos: */
936 + struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */
939 +typedef struct s_queue SK_PKT_QUEUE;
943 + spinlock_t QueueLock; /* serialize packet accesses */
946 +/*******************************************************************************
948 + * Macros specific for Yukon-II queues
950 + ******************************************************************************/
952 +#define IS_Q_EMPTY(pQueue) ((pQueue)->pHead != NULL) ? SK_FALSE : SK_TRUE
953 +#define IS_Q_LOCKED(pQueue) spin_is_locked(&((pQueue)->QueueLock))
955 +#define PLAIN_POP_FIRST_PKT_FROM_QUEUE(pQueue, pPacket) { \
956 + if ((pQueue)->pHead != NULL) { \
957 + (pPacket) = (pQueue)->pHead; \
958 + (pQueue)->pHead = (pPacket)->pNext; \
959 + if ((pQueue)->pHead == NULL) { \
960 + (pQueue)->pTail = NULL; \
962 + (pPacket)->pNext = NULL; \
964 + (pPacket) = NULL; \
968 +#define PLAIN_PUSH_PKT_AS_FIRST_IN_QUEUE(pQueue, pPacket) { \
969 + if ((pQueue)->pHead != NULL) { \
970 + (pPacket)->pNext = (pQueue)->pHead; \
972 + (pPacket)->pNext = NULL; \
973 + (pQueue)->pTail = (pPacket); \
975 + (pQueue)->pHead = (pPacket); \
978 +#define PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(pQueue, pPacket) { \
979 + (pPacket)->pNext = NULL; \
980 + if ((pQueue)->pTail != NULL) { \
981 + (pQueue)->pTail->pNext = (pPacket); \
983 + (pQueue)->pHead = (pPacket); \
985 + (pQueue)->pTail = (pPacket); \
988 +#define PLAIN_PUSH_MULTIPLE_PKT_AS_LAST_IN_QUEUE(pQueue,pPktGrpStart,pPktGrpEnd) { \
989 + if ((pPktGrpStart) != NULL) { \
990 + if ((pQueue)->pTail != NULL) { \
991 + (pQueue)->pTail->pNext = (pPktGrpStart); \
993 + (pQueue)->pHead = (pPktGrpStart); \
995 + (pQueue)->pTail = (pPktGrpEnd); \
999 +/* Required: 'Flags' */
1000 +#define POP_FIRST_PKT_FROM_QUEUE(pQueue, pPacket) { \
1001 + spin_lock_irqsave(&((pQueue)->QueueLock), Flags); \
1002 + if ((pQueue)->pHead != NULL) { \
1003 + (pPacket) = (pQueue)->pHead; \
1004 + (pQueue)->pHead = (pPacket)->pNext; \
1005 + if ((pQueue)->pHead == NULL) { \
1006 + (pQueue)->pTail = NULL; \
1008 + (pPacket)->pNext = NULL; \
1010 + (pPacket) = NULL; \
1012 + spin_unlock_irqrestore(&((pQueue)->QueueLock), Flags); \
1015 +/* Required: 'Flags' */
1016 +#define PUSH_PKT_AS_FIRST_IN_QUEUE(pQueue, pPacket) { \
1017 + spin_lock_irqsave(&(pQueue)->QueueLock, Flags); \
1018 + if ((pQueue)->pHead != NULL) { \
1019 + (pPacket)->pNext = (pQueue)->pHead; \
1021 + (pPacket)->pNext = NULL; \
1022 + (pQueue)->pTail = (pPacket); \
1024 + (pQueue)->pHead = (pPacket); \
1025 + spin_unlock_irqrestore(&(pQueue)->QueueLock, Flags); \
1028 +/* Required: 'Flags' */
1029 +#define PUSH_PKT_AS_LAST_IN_QUEUE(pQueue, pPacket) { \
1030 + (pPacket)->pNext = NULL; \
1031 + spin_lock_irqsave(&(pQueue)->QueueLock, Flags); \
1032 + if ((pQueue)->pTail != NULL) { \
1033 + (pQueue)->pTail->pNext = (pPacket); \
1035 + (pQueue)->pHead = (pPacket); \
1037 + (pQueue)->pTail = (pPacket); \
1038 + spin_unlock_irqrestore(&(pQueue)->QueueLock, Flags); \
1041 +/* Required: 'Flags' */
1042 +#define PUSH_MULTIPLE_PKT_AS_LAST_IN_QUEUE(pQueue,pPktGrpStart,pPktGrpEnd) { \
1043 + if ((pPktGrpStart) != NULL) { \
1044 + spin_lock_irqsave(&(pQueue)->QueueLock, Flags); \
1045 + if ((pQueue)->pTail != NULL) { \
1046 + (pQueue)->pTail->pNext = (pPktGrpStart); \
1048 + (pQueue)->pHead = (pPktGrpStart); \
1050 + (pQueue)->pTail = (pPktGrpEnd); \
1051 + spin_unlock_irqrestore(&(pQueue)->QueueLock, Flags); \
1056 + *Check if the low address (32 bit) is near the 4G limit or over it.
1057 + * Set the high address to a wrong value.
1058 + * Doing so we force to write the ADDR64 LE.
1060 +#define CHECK_LOW_ADDRESS( _HighAddress, _LowAddress , _Length) { \
1061 + if ((~0-_LowAddress) <_Length) { \
1062 + _HighAddress= MAXIMUM_LOW_ADDRESS; \
1063 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, \
1064 + ("High Address must be set for HW. LowAddr = %d Length = %d\n", \
1065 + _LowAddress, _Length)); \
1069 +/*******************************************************************************
1071 + * Macros specific for Yukon-II queues (tist)
1073 + ******************************************************************************/
1075 +#ifdef USE_TIST_FOR_RESET
1076 +/* port is fully operational */
1077 +#define SK_PSTATE_NOT_WAITING_FOR_TIST 0
1078 +/* port in reset until any tist LE */
1079 +#define SK_PSTATE_WAITING_FOR_ANY_TIST BIT_0
1080 +/* port in reset until timer reaches pAC->MinTistLo */
1081 +#define SK_PSTATE_WAITING_FOR_SPECIFIC_TIST BIT_1
1082 +#define SK_PSTATE_PORT_SHIFT 4
1083 +#define SK_PSTATE_PORT_MASK ((1 << SK_PSTATE_PORT_SHIFT) - 1)
1085 +/* use this + Port to build OP_MOD_TXINDEX_NO_PORT_A|B */
1086 +#define OP_MOD_TXINDEX 0x71
1087 +/* opcode for a TX_INDEX LE in which Port A has to be ignored */
1088 +#define OP_MOD_TXINDEX_NO_PORT_A 0x71
1089 +/* opcode for a TX_INDEX LE in which Port B has to be ignored */
1090 +#define OP_MOD_TXINDEX_NO_PORT_B 0x72
1091 +/* opcode for LE to be ignored because port is still in reset */
1092 +#define OP_MOD_LE 0x7F
1094 +/* set tist wait mode Bit for port */
1095 +#define SK_SET_WAIT_BIT_FOR_PORT(pAC, Bit, Port) \
1097 + (pAC)->AdapterResetState |= ((Bit) << (SK_PSTATE_PORT_SHIFT * Port)); \
1100 +/* reset tist waiting for specified port */
1101 +#define SK_CLR_STATE_FOR_PORT(pAC, Port) \
1103 + (pAC)->AdapterResetState &= \
1104 + ~(SK_PSTATE_PORT_MASK << (SK_PSTATE_PORT_SHIFT * Port)); \
1107 +/* return SK_TRUE when port is in reset waiting for tist */
1108 +#define SK_PORT_WAITING_FOR_TIST(pAC, Port) \
1109 + ((((pAC)->AdapterResetState >> (SK_PSTATE_PORT_SHIFT * Port)) & \
1110 + SK_PSTATE_PORT_MASK) != SK_PSTATE_NOT_WAITING_FOR_TIST)
1112 +/* return SK_TRUE when port is in reset waiting for any tist */
1113 +#define SK_PORT_WAITING_FOR_ANY_TIST(pAC, Port) \
1114 + ((((pAC)->AdapterResetState >> (SK_PSTATE_PORT_SHIFT * Port)) & \
1115 + SK_PSTATE_WAITING_FOR_ANY_TIST) == SK_PSTATE_WAITING_FOR_ANY_TIST)
1117 +/* return SK_TRUE when port is in reset waiting for a specific tist */
1118 +#define SK_PORT_WAITING_FOR_SPECIFIC_TIST(pAC, Port) \
1119 + ((((pAC)->AdapterResetState >> (SK_PSTATE_PORT_SHIFT * Port)) & \
1120 + SK_PSTATE_WAITING_FOR_SPECIFIC_TIST) == \
1121 + SK_PSTATE_WAITING_FOR_SPECIFIC_TIST)
1123 +/* return whether adapter is expecting a tist LE */
1124 +#define SK_ADAPTER_WAITING_FOR_TIST(pAC) ((pAC)->AdapterResetState != 0)
1126 +/* enable timestamp timer and force creation of tist LEs */
1127 +#define Y2_ENABLE_TIST(IoC) \
1128 + SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8) GMT_ST_START)
1130 +/* disable timestamp timer and stop creation of tist LEs */
1131 +#define Y2_DISABLE_TIST(IoC) \
1132 + SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8) GMT_ST_STOP)
1134 +/* get current value of timestamp timer */
1135 +#define Y2_GET_TIST_LOW_VAL(IoC, pVal) \
1136 + SK_IN32(IoC, GMAC_TI_ST_VAL, pVal)
1138 -#define DRIVER_IRQS ((IS_IRQ_SW) | \
1139 - (IS_R1_F) |(IS_R2_F) | \
1140 - (IS_XS1_F) |(IS_XA1_F) | \
1141 - (IS_XS2_F) |(IS_XA2_F))
1143 -#define SPECIAL_IRQS ((IS_HW_ERR) |(IS_I2C_READY) | \
1144 - (IS_EXT_REG) |(IS_TIMINT) | \
1145 - (IS_PA_TO_RX1) |(IS_PA_TO_RX2) | \
1146 - (IS_PA_TO_TX1) |(IS_PA_TO_TX2) | \
1147 - (IS_MAC1) |(IS_LNK_SYNC_M1)| \
1148 - (IS_MAC2) |(IS_LNK_SYNC_M2)| \
1149 - (IS_R1_C) |(IS_R2_C) | \
1150 - (IS_XS1_C) |(IS_XA1_C) | \
1151 - (IS_XS2_C) |(IS_XA2_C))
1153 -#define IRQ_MASK ((IS_IRQ_SW) | \
1154 - (IS_R1_B) |(IS_R1_F) |(IS_R2_B) |(IS_R2_F) | \
1155 - (IS_XS1_B) |(IS_XS1_F) |(IS_XA1_B)|(IS_XA1_F)| \
1156 - (IS_XS2_B) |(IS_XS2_F) |(IS_XA2_B)|(IS_XA2_F)| \
1157 - (IS_HW_ERR) |(IS_I2C_READY)| \
1158 - (IS_EXT_REG) |(IS_TIMINT) | \
1159 - (IS_PA_TO_RX1) |(IS_PA_TO_RX2)| \
1160 - (IS_PA_TO_TX1) |(IS_PA_TO_TX2)| \
1161 - (IS_MAC1) |(IS_MAC2) | \
1162 - (IS_R1_C) |(IS_R2_C) | \
1163 - (IS_XS1_C) |(IS_XA1_C) | \
1164 - (IS_XS2_C) |(IS_XA2_C))
1167 -#define IRQ_HWE_MASK (IS_ERR_MSK) /* enable all HW irqs */
1169 +/*******************************************************************************
1171 + * Used interrupt bits in the interrupts source register
1173 + ******************************************************************************/
1175 +#define DRIVER_IRQS ((IS_IRQ_SW) | \
1176 + (IS_R1_F) | (IS_R2_F) | \
1177 + (IS_XS1_F) | (IS_XA1_F) | \
1178 + (IS_XS2_F) | (IS_XA2_F))
1180 +#define TX_COMPL_IRQS ((IS_XS1_B) | (IS_XS1_F) | \
1181 + (IS_XA1_B) | (IS_XA1_F) | \
1182 + (IS_XS2_B) | (IS_XS2_F) | \
1183 + (IS_XA2_B) | (IS_XA2_F))
1185 +#define NAPI_DRV_IRQS ((IS_R1_F) | (IS_R2_F) | \
1186 + (IS_XS1_F) | (IS_XA1_F)| \
1187 + (IS_XS2_F) | (IS_XA2_F))
1189 +#define Y2_DRIVER_IRQS ((Y2_IS_STAT_BMU) | (Y2_IS_IRQ_SW) | (Y2_IS_POLL_CHK))
1191 +#define SPECIAL_IRQS ((IS_HW_ERR) |(IS_I2C_READY) | \
1192 + (IS_EXT_REG) |(IS_TIMINT) | \
1193 + (IS_PA_TO_RX1) |(IS_PA_TO_RX2) | \
1194 + (IS_PA_TO_TX1) |(IS_PA_TO_TX2) | \
1195 + (IS_MAC1) |(IS_LNK_SYNC_M1)| \
1196 + (IS_MAC2) |(IS_LNK_SYNC_M2)| \
1197 + (IS_R1_C) |(IS_R2_C) | \
1198 + (IS_XS1_C) |(IS_XA1_C) | \
1199 + (IS_XS2_C) |(IS_XA2_C))
1201 +#define Y2_SPECIAL_IRQS ((Y2_IS_HW_ERR) |(Y2_IS_ASF) | \
1202 + (Y2_IS_TWSI_RDY) |(Y2_IS_TIMINT) | \
1203 + (Y2_IS_IRQ_PHY2) |(Y2_IS_IRQ_MAC2) | \
1204 + (Y2_IS_CHK_RX2) |(Y2_IS_CHK_TXS2) | \
1205 + (Y2_IS_CHK_TXA2) |(Y2_IS_IRQ_PHY1) | \
1206 + (Y2_IS_IRQ_MAC1) |(Y2_IS_CHK_RX1) | \
1207 + (Y2_IS_CHK_TXS1) |(Y2_IS_CHK_TXA1))
1209 +#define IRQ_MASK ((IS_IRQ_SW) | \
1210 + (IS_R1_F) |(IS_R2_F) | \
1211 + (IS_XS1_F) |(IS_XA1_F) | \
1212 + (IS_XS2_F) |(IS_XA2_F) | \
1213 + (IS_HW_ERR) |(IS_I2C_READY)| \
1214 + (IS_EXT_REG) |(IS_TIMINT) | \
1215 + (IS_PA_TO_RX1) |(IS_PA_TO_RX2)| \
1216 + (IS_PA_TO_TX1) |(IS_PA_TO_TX2)| \
1217 + (IS_MAC1) |(IS_MAC2) | \
1218 + (IS_R1_C) |(IS_R2_C) | \
1219 + (IS_XS1_C) |(IS_XA1_C) | \
1220 + (IS_XS2_C) |(IS_XA2_C))
1222 +#define Y2_IRQ_MASK ((Y2_DRIVER_IRQS) | (Y2_SPECIAL_IRQS))
1224 +#define IRQ_HWE_MASK (IS_ERR_MSK) /* enable all HW irqs */
1225 +#define Y2_IRQ_HWE_MASK (Y2_HWE_ALL_MSK) /* enable all HW irqs */
1227 typedef struct s_DevNet DEV_NET;
1233 + struct proc_dir_entry *proc;
1236 + char InitialDevName[20];
1237 + SK_BOOL NetConsoleMode;
1239 + struct timer_list KernelTimer; /* Kernel timer struct */
1240 + int TransmitTimeoutTimer; /* Transmit timer */
1241 + SK_BOOL TimerExpired; /* Transmit timer */
1242 + SK_BOOL InRecover; /* Recover flag */
1244 + SK_U32 PreviousMACFifoRP; /* Backup of the FRP */
1245 + SK_U32 PreviousMACFifoRLev; /* Backup of the FRL */
1246 + SK_U32 PreviousRXFifoRP; /* Backup of the RX FRP */
1247 + SK_U8 PreviousRXFifoRLev; /* Backup of the RX FRL */
1248 + SK_U32 LastJiffies; /* Backup of the jiffies*/
1254 -typedef struct s_TxPort TX_PORT;
1255 +/*******************************************************************************
1257 + * Rx/Tx Port structures
1259 + ******************************************************************************/
1262 - /* the transmit descriptor rings */
1263 - caddr_t pTxDescrRing; /* descriptor area memory */
1264 - SK_U64 VTxDescrRing; /* descr. area bus virt. addr. */
1265 - TXD *pTxdRingHead; /* Head of Tx rings */
1266 - TXD *pTxdRingTail; /* Tail of Tx rings */
1267 - TXD *pTxdRingPrev; /* descriptor sent previously */
1268 - int TxdRingFree; /* # of free entrys */
1269 - spinlock_t TxDesRingLock; /* serialize descriptor accesses */
1270 - SK_IOC HwAddr; /* bmu registers address */
1271 - int PortIndex; /* index number of port (0 or 1) */
1272 +typedef struct s_TxPort TX_PORT;
1273 +struct s_TxPort { /* the transmit descriptor rings */
1274 + caddr_t pTxDescrRing; /* descriptor area memory */
1275 + SK_U64 VTxDescrRing; /* descr. area bus virt. addr. */
1276 + TXD *pTxdRingHead; /* Head of Tx rings */
1277 + TXD *pTxdRingTail; /* Tail of Tx rings */
1278 + TXD *pTxdRingPrev; /* descriptor sent previously */
1279 + int TxdRingPrevFree;/* previously # of free entrys */
1280 + int TxdRingFree; /* # of free entrys */
1281 + spinlock_t TxDesRingLock; /* serialize descriptor accesses */
1282 + caddr_t HwAddr; /* bmu registers address */
1283 + int PortIndex; /* index number of port (0 or 1) */
1284 + SK_PACKET *TransmitPacketTable;
1285 + SK_LE_TABLE TxALET; /* tx (async) list element table */
1286 + SK_LE_TABLE TxSLET; /* tx (sync) list element table */
1287 + SK_PKT_QUEUE TxQ_free;
1288 + SK_PKT_QUEUE TxAQ_waiting;
1289 + SK_PKT_QUEUE TxSQ_waiting;
1290 + SK_PKT_QUEUE TxAQ_working;
1291 + SK_PKT_QUEUE TxSQ_working;
1292 + unsigned LastDone;
1295 -typedef struct s_RxPort RX_PORT;
1298 - /* the receive descriptor rings */
1299 - caddr_t pRxDescrRing; /* descriptor area memory */
1300 - SK_U64 VRxDescrRing; /* descr. area bus virt. addr. */
1301 - RXD *pRxdRingHead; /* Head of Rx rings */
1302 - RXD *pRxdRingTail; /* Tail of Rx rings */
1303 - RXD *pRxdRingPrev; /* descriptor given to BMU previously */
1304 - int RxdRingFree; /* # of free entrys */
1305 - int RxCsum; /* use receive checksum hardware */
1306 - spinlock_t RxDesRingLock; /* serialize descriptor accesses */
1307 - int RxFillLimit; /* limit for buffers in ring */
1308 - SK_IOC HwAddr; /* bmu registers address */
1309 - int PortIndex; /* index number of port (0 or 1) */
1310 +typedef struct s_RxPort RX_PORT;
1311 +struct s_RxPort { /* the receive descriptor rings */
1312 + caddr_t pRxDescrRing; /* descriptor area memory */
1313 + SK_U64 VRxDescrRing; /* descr. area bus virt. addr. */
1314 + RXD *pRxdRingHead; /* Head of Rx rings */
1315 + RXD *pRxdRingTail; /* Tail of Rx rings */
1316 + RXD *pRxdRingPrev; /* descr given to BMU previously */
1317 + int RxdRingFree; /* # of free entrys */
1318 + spinlock_t RxDesRingLock; /* serialize descriptor accesses */
1319 + int RxFillLimit; /* limit for buffers in ring */
1320 + caddr_t HwAddr; /* bmu registers address */
1321 + int PortIndex; /* index number of port (0 or 1) */
1322 + SK_BOOL UseRxCsum; /* use Rx checksumming (yes/no) */
1323 + SK_PACKET *ReceivePacketTable;
1324 + SK_LE_TABLE RxLET; /* rx list element table */
1325 + SK_PKT_QUEUE RxQ_working;
1326 + SK_PKT_QUEUE RxQ_waiting;
1330 -/* Definitions needed for interrupt moderation *******************************/
1331 +/*******************************************************************************
1333 + * Interrupt masks used in combination with interrupt moderation
1335 + ******************************************************************************/
1337 #define IRQ_EOF_AS_TX ((IS_XA1_F) | (IS_XA2_F))
1338 #define IRQ_EOF_SY_TX ((IS_XS1_F) | (IS_XS2_F))
1339 @@ -314,134 +732,151 @@
1340 #define IRQ_MASK_SP_TX ((SPECIAL_IRQS) | (IRQ_MASK_TX_ONLY))
1341 #define IRQ_MASK_RX_TX_SP ((SPECIAL_IRQS) | (IRQ_MASK_TX_RX))
1343 -#define C_INT_MOD_NONE 1
1344 -#define C_INT_MOD_STATIC 2
1345 -#define C_INT_MOD_DYNAMIC 4
1347 -#define C_CLK_FREQ_GENESIS 53215000 /* shorter: 53.125 MHz */
1348 -#define C_CLK_FREQ_YUKON 78215000 /* shorter: 78.125 MHz */
1350 -#define C_INTS_PER_SEC_DEFAULT 2000
1351 -#define C_INT_MOD_ENABLE_PERCENTAGE 50 /* if higher 50% enable */
1352 -#define C_INT_MOD_DISABLE_PERCENTAGE 50 /* if lower 50% disable */
1353 -#define C_INT_MOD_IPS_LOWER_RANGE 30
1354 -#define C_INT_MOD_IPS_UPPER_RANGE 40000
1357 -typedef struct s_DynIrqModInfo DIM_INFO;
1358 -struct s_DynIrqModInfo {
1359 - unsigned long PrevTimeVal;
1360 - unsigned int PrevSysLoad;
1361 - unsigned int PrevUsedTime;
1362 - unsigned int PrevTotalTime;
1363 - int PrevUsedDescrRatio;
1364 - int NbrProcessedDescr;
1365 - SK_U64 PrevPort0RxIntrCts;
1366 - SK_U64 PrevPort1RxIntrCts;
1367 - SK_U64 PrevPort0TxIntrCts;
1368 - SK_U64 PrevPort1TxIntrCts;
1369 - SK_BOOL ModJustEnabled; /* Moderation just enabled yes/no */
1371 - int MaxModIntsPerSec; /* Moderation Threshold */
1372 - int MaxModIntsPerSecUpperLimit; /* Upper limit for DIM */
1373 - int MaxModIntsPerSecLowerLimit; /* Lower limit for DIM */
1375 - long MaskIrqModeration; /* ModIrqType (eg. 'TxRx') */
1376 - SK_BOOL DisplayStats; /* Stats yes/no */
1377 - SK_BOOL AutoSizing; /* Resize DIM-timer on/off */
1378 - int IntModTypeSelect; /* EnableIntMod (eg. 'dynamic') */
1379 +#define IRQ_MASK_Y2_TX_ONLY (Y2_IS_STAT_BMU)
1380 +#define IRQ_MASK_Y2_RX_ONLY (Y2_IS_STAT_BMU)
1381 +#define IRQ_MASK_Y2_SP_ONLY (SPECIAL_IRQS)
1382 +#define IRQ_MASK_Y2_TX_RX ((IRQ_MASK_TX_ONLY)| (IRQ_MASK_RX_ONLY))
1383 +#define IRQ_MASK_Y2_SP_RX ((SPECIAL_IRQS) | (IRQ_MASK_RX_ONLY))
1384 +#define IRQ_MASK_Y2_SP_TX ((SPECIAL_IRQS) | (IRQ_MASK_TX_ONLY))
1385 +#define IRQ_MASK_Y2_RX_TX_SP ((SPECIAL_IRQS) | (IRQ_MASK_TX_RX))
1387 - SK_TIMER ModTimer; /* just some timer */
1389 +/*******************************************************************************
1391 + * Defines and typedefs regarding interrupt moderation
1393 + ******************************************************************************/
1395 -typedef struct s_PerStrm PER_STRM;
1396 +#define C_INT_MOD_NONE 1
1397 +#define C_INT_MOD_STATIC 2
1398 +#define C_INT_MOD_DYNAMIC 4
1400 +#define C_CLK_FREQ_GENESIS 53215000 /* or: 53.125 MHz */
1401 +#define C_CLK_FREQ_YUKON 78215000 /* or: 78.125 MHz */
1402 +#define C_CLK_FREQ_YUKON_EC 125000000 /* or: 125.000 MHz */
1404 +#define C_Y2_INTS_PER_SEC_DEFAULT 5000
1405 +#define C_INTS_PER_SEC_DEFAULT 2000
1406 +#define C_INT_MOD_IPS_LOWER_RANGE 30 /* in IRQs/second */
1407 +#define C_INT_MOD_IPS_UPPER_RANGE 40000 /* in IRQs/second */
1409 +typedef struct s_DynIrqModInfo {
1410 + SK_U64 PrevPort0RxIntrCts;
1411 + SK_U64 PrevPort1RxIntrCts;
1412 + SK_U64 PrevPort0TxIntrCts;
1413 + SK_U64 PrevPort1TxIntrCts;
1414 + SK_U64 PrevPort0StatusLeIntrCts;
1415 + SK_U64 PrevPort1StatusLeIntrCts;
1416 + int MaxModIntsPerSec; /* Moderation Threshold */
1417 + int MaxModIntsPerSecUpperLimit; /* Upper limit for DIM */
1418 + int MaxModIntsPerSecLowerLimit; /* Lower limit for DIM */
1419 + long MaskIrqModeration; /* IRQ Mask (eg. 'TxRx') */
1420 + int IntModTypeSelect; /* Type (eg. 'dynamic') */
1421 + int DynIrqModSampleInterval; /* expressed in seconds! */
1422 + SK_TIMER ModTimer; /* Timer for dynamic mod. */
1425 -#define SK_ALLOC_IRQ 0x00000001
1426 +/*******************************************************************************
1428 + * Defines and typedefs regarding wake-on-lan
1430 + ******************************************************************************/
1432 +typedef struct s_WakeOnLanInfo {
1433 + SK_U32 SupportedWolOptions; /* e.g. WAKE_PHY... */
1434 + SK_U32 ConfiguredWolOptions; /* e.g. WAKE_PHY... */
1437 -#ifdef SK_DIAG_SUPPORT
1438 +#define SK_ALLOC_IRQ 0x00000001
1439 #define DIAG_ACTIVE 1
1440 #define DIAG_NOTACTIVE 0
1443 /****************************************************************************
1445 * Per board structure / Adapter Context structure:
1446 - * Allocated within attach(9e) and freed within detach(9e).
1447 - * Contains all 'per device' necessary handles, flags, locks etc.:
1449 + * Contains all 'per device' necessary handles, flags, locks etc.:
1451 + ******************************************************************************/
1454 - SK_GEINIT GIni; /* GE init struct */
1455 - SK_PNMI Pnmi; /* PNMI data struct */
1456 - SK_VPD vpd; /* vpd data struct */
1457 - SK_QUEUE Event; /* Event queue */
1458 - SK_HWT Hwt; /* Hardware Timer control struct */
1459 - SK_TIMCTRL Tim; /* Software Timer control struct */
1460 - SK_I2C I2c; /* I2C relevant data structure */
1461 - SK_ADDR Addr; /* for Address module */
1462 - SK_CSUM Csum; /* for checksum module */
1463 - SK_RLMT Rlmt; /* for rlmt module */
1464 - spinlock_t SlowPathLock; /* Normal IRQ lock */
1465 - struct timer_list BlinkTimer; /* for LED blinking */
1467 - SK_PNMI_STRUCT_DATA PnmiStruct; /* structure to get all Pnmi-Data */
1468 - int RlmtMode; /* link check mode to set */
1469 - int RlmtNets; /* Number of nets */
1471 - SK_IOC IoBase; /* register set of adapter */
1472 - int BoardLevel; /* level of active hw init (0-2) */
1474 - SK_U32 AllocFlag; /* flag allocation of resources */
1475 - struct pci_dev *PciDev; /* for access to pci config space */
1476 - struct SK_NET_DEVICE *dev[2]; /* pointer to device struct */
1478 - int RxBufSize; /* length of receive buffers */
1479 - struct net_device_stats stats; /* linux 'netstat -i' statistics */
1480 - int Index; /* internal board index number */
1482 - /* adapter RAM sizes for queues of active port */
1483 - int RxQueueSize; /* memory used for receive queue */
1484 - int TxSQueueSize; /* memory used for sync. tx queue */
1485 - int TxAQueueSize; /* memory used for async. tx queue */
1487 - int PromiscCount; /* promiscuous mode counter */
1488 - int AllMultiCount; /* allmulticast mode counter */
1489 - int MulticCount; /* number of different MC */
1490 - /* addresses for this board */
1491 - /* (may be more than HW can)*/
1493 - int HWRevision; /* Hardware revision */
1494 - int ActivePort; /* the active XMAC port */
1495 - int MaxPorts; /* number of activated ports */
1496 - int TxDescrPerRing; /* # of descriptors per tx ring */
1497 - int RxDescrPerRing; /* # of descriptors per rx ring */
1499 - caddr_t pDescrMem; /* Pointer to the descriptor area */
1500 - dma_addr_t pDescrMemDMA; /* PCI DMA address of area */
1502 - /* the port structures with descriptor rings */
1503 - TX_PORT TxPort[SK_MAX_MACS][2];
1504 - RX_PORT RxPort[SK_MAX_MACS];
1506 - SK_BOOL CheckQueue; /* check event queue soon */
1507 - SK_TIMER DrvCleanupTimer;/* to check for pending descriptors */
1508 - DIM_INFO DynIrqModInfo; /* all data related to DIM */
1510 - /* Only for tests */
1512 - int ChipsetType; /* Chipset family type
1513 - * 0 == Genesis family support
1514 - * 1 == Yukon family support
1516 -#ifdef SK_DIAG_SUPPORT
1517 - SK_U32 DiagModeActive; /* is diag active? */
1518 - SK_BOOL DiagFlowCtrl; /* for control purposes */
1519 - SK_PNMI_STRUCT_DATA PnmiBackup; /* backup structure for all Pnmi-Data */
1520 - SK_BOOL WasIfUp[SK_MAX_MACS]; /* for OpenClose while
1521 - * DIAG is busy with NIC
1523 + SK_GEINIT GIni; /* GE init struct */
1524 + SK_PNMI Pnmi; /* PNMI data struct */
1525 + SK_VPD vpd; /* vpd data struct */
1526 + SK_QUEUE Event; /* Event queue */
1527 + SK_HWT Hwt; /* Hardware Timer ctrl struct */
1528 + SK_TIMCTRL Tim; /* Software Timer ctrl struct */
1529 + SK_I2C I2c; /* I2C relevant data structure*/
1530 + SK_ADDR Addr; /* for Address module */
1531 + SK_CSUM Csum; /* for checksum module */
1532 + SK_RLMT Rlmt; /* for rlmt module */
1533 + spinlock_t SlowPathLock; /* Normal IRQ lock */
1534 + spinlock_t InitLock; /* Init lock */
1535 + spinlock_t TxQueueLock; /* TX Queue lock */
1536 + SK_PNMI_STRUCT_DATA PnmiStruct; /* struct for all Pnmi-Data */
1537 + int RlmtMode; /* link check mode to set */
1538 + int RlmtNets; /* Number of nets */
1539 + SK_IOC IoBase; /* register set of adapter */
1540 + int BoardLevel; /* level of hw init (0-2) */
1541 + char DeviceStr[80]; /* adapter string from vpd */
1542 + SK_U32 AllocFlag; /* alloc flag of resources */
1543 + struct pci_dev *PciDev; /* for access to pci cfg space*/
1544 + SK_U32 PciDevId; /* pci device id */
1545 + struct SK_NET_DEVICE *dev[2]; /* pointer to device struct */
1546 + char Name[30]; /* driver name */
1547 + struct SK_NET_DEVICE *Next; /* link all devs for cleanup */
1548 + struct net_device_stats stats; /* linux 'netstat -i' stats */
1549 + int Index; /* internal board idx number */
1550 + int RxQueueSize; /* memory used for RX queue */
1551 + int TxSQueueSize; /* memory used for TXS queue */
1552 + int TxAQueueSize; /* memory used for TXA queue */
1553 + int PromiscCount; /* promiscuous mode counter */
1554 + int AllMultiCount; /* allmulticast mode counter */
1555 + int MulticCount; /* number of MC addresses used*/
1556 + int HWRevision; /* Hardware revision */
1557 + int ActivePort; /* the active XMAC port */
1558 + int MaxPorts; /* number of activated ports */
1559 + int TxDescrPerRing;/* # of descriptors TX ring */
1560 + int RxDescrPerRing;/* # of descriptors RX ring */
1561 + caddr_t pDescrMem; /* Ptr to the descriptor area */
1562 + dma_addr_t pDescrMemDMA; /* PCI DMA address of area */
1563 + SK_U32 PciState[16]; /* PCI state */
1564 + TX_PORT TxPort[SK_MAX_MACS][2];
1565 + RX_PORT RxPort[SK_MAX_MACS];
1566 + SK_LE_TABLE StatusLETable;
1567 + unsigned SizeOfAlignedLETables;
1568 + spinlock_t SetPutIndexLock;
1569 + int MaxUnusedRxLeWorking;
1570 + unsigned int CsOfs1; /* for checksum calculation */
1571 + unsigned int CsOfs2; /* for checksum calculation */
1572 + SK_U32 CsOfs; /* for checksum calculation */
1573 + SK_BOOL CheckQueue; /* check event queue soon */
1574 + DIM_INFO DynIrqModInfo; /* all data related to IntMod */
1575 + WOL_INFO WolInfo; /* all info regarding WOL */
1576 + int ChipsetType; /* 0=GENESIS; 1=Yukon */
1577 + SK_BOOL LowLatency; /* LowLatency optimization on?*/
1578 + SK_U32 DiagModeActive;/* is diag active? */
1579 + SK_BOOL DiagFlowCtrl; /* for control purposes */
1580 + SK_PNMI_STRUCT_DATA PnmiBackup; /* backup structure for PNMI */
1581 + SK_BOOL WasIfUp[SK_MAX_MACS];
1582 +#ifdef USE_TIST_FOR_RESET
1583 + int AdapterResetState;
1588 + int LastPort; /* port for curr. handled rx */
1589 + int LastOpc; /* last rx LEs opcode */
1591 +#ifdef Y2_SYNC_CHECK
1592 + unsigned long FramesWithoutSyncCheck; /* since last check */
1598 -#endif /* __INC_SKDRV2ND_H */
1602 +/*******************************************************************************
1606 + ******************************************************************************/
1607 diff -ruN linux/drivers/net/sk98lin/h/skerror.h linux-new/drivers/net/sk98lin/h/skerror.h
1608 --- linux/drivers/net/sk98lin/h/skerror.h 2006-09-20 05:42:06.000000000 +0200
1609 +++ linux-new/drivers/net/sk98lin/h/skerror.h 2006-07-28 14:13:54.000000000 +0200
1613 * Project: Gigabit Ethernet Adapters, Common Modules
1614 - * Version: $Revision$
1616 + * Version: $Revision$
1618 * Purpose: SK specific Error log support
1620 ******************************************************************************/
1622 /******************************************************************************
1625 * (C)Copyright 1998-2002 SysKonnect.
1626 - * (C)Copyright 2002-2003 Marvell.
1627 + * (C)Copyright 2002-2004 Marvell.
1629 * This program is free software; you can redistribute it and/or modify
1630 * it under the terms of the GNU General Public License as published by
1631 * the Free Software Foundation; either version 2 of the License, or
1632 * (at your option) any later version.
1634 * The information in this file is provided "AS IS" without warranty.
1637 ******************************************************************************/
1640 #define SK_ERRCL_HW (1L<<4) /* Hardware Failure */
1641 #define SK_ERRCL_COMM (1L<<5) /* Communication error */
1645 * Define Error Code Bases
1648 #define SK_ERRBASE_I2C 700 /* Base Error number for I2C module */
1649 #define SK_ERRBASE_QUEUE 800 /* Base Error number for Scheduler */
1650 #define SK_ERRBASE_ADDR 900 /* Base Error number for Address module */
1651 -#define SK_ERRBASE_PECP 1000 /* Base Error number for PECP */
1652 +#define SK_ERRBASE_PECP 1000 /* Base Error number for PECP */
1653 #define SK_ERRBASE_DRV 1100 /* Base Error number for Driver */
1654 +#define SK_ERRBASE_ASF 1200 /* Base Error number for ASF */
1656 #endif /* _INC_SKERROR_H_ */
1658 diff -ruN linux/drivers/net/sk98lin/h/skgedrv.h linux-new/drivers/net/sk98lin/h/skgedrv.h
1659 --- linux/drivers/net/sk98lin/h/skgedrv.h 2006-09-20 05:42:06.000000000 +0200
1660 +++ linux-new/drivers/net/sk98lin/h/skgedrv.h 2006-07-28 14:13:54.000000000 +0200
1664 * Project: Gigabit Ethernet Adapters, Common Modules
1665 - * Version: $Revision$
1667 + * Version: $Revision$
1669 * Purpose: Interface with the driver
1671 ******************************************************************************/
1673 /******************************************************************************
1676 * (C)Copyright 1998-2002 SysKonnect.
1677 - * (C)Copyright 2002-2003 Marvell.
1678 + * (C)Copyright 2002-2006 Marvell.
1680 * This program is free software; you can redistribute it and/or modify
1681 * it under the terms of the GNU General Public License as published by
1682 * the Free Software Foundation; either version 2 of the License, or
1683 * (at your option) any later version.
1685 * The information in this file is provided "AS IS" without warranty.
1688 ******************************************************************************/
1691 * In case of the driver we put the definition of the events here.
1693 #define SK_DRV_PORT_RESET 1 /* The port needs to be reset */
1694 -#define SK_DRV_NET_UP 2 /* The net is operational */
1695 +#define SK_DRV_NET_UP 2 /* The net is operational */
1696 #define SK_DRV_NET_DOWN 3 /* The net is down */
1697 #define SK_DRV_SWITCH_SOFT 4 /* Ports switch with both links connected */
1698 #define SK_DRV_SWITCH_HARD 5 /* Port switch due to link failure */
1700 #define SK_DRV_POWER_DOWN 10 /* Power down mode */
1701 #define SK_DRV_TIMER 11 /* Timer for free use */
1703 -#define SK_DRV_LINK_UP 12 /* Link Up event for driver */
1704 +#define SK_DRV_LINK_UP 12 /* Link Up event for driver */
1705 #define SK_DRV_LINK_DOWN 13 /* Link Down event for driver */
1707 #define SK_DRV_DOWNSHIFT_DET 14 /* Downshift 4-Pair / 2-Pair (YUKON only) */
1708 +#define SK_DRV_RX_OVERFLOW 15 /* Receive Overflow */
1709 +#define SK_DRV_LIPA_NOT_AN_ABLE 16 /* Link Partner not Auto-Negotiation able */
1710 +#define SK_DRV_PEX_LINK_WIDTH 17 /* PEX negotiated Link width not maximum */
1711 #endif /* __INC_SKGEDRV_H_ */
1712 diff -ruN linux/drivers/net/sk98lin/h/skgehw.h linux-new/drivers/net/sk98lin/h/skgehw.h
1713 --- linux/drivers/net/sk98lin/h/skgehw.h 2006-09-20 05:42:06.000000000 +0200
1714 +++ linux-new/drivers/net/sk98lin/h/skgehw.h 2006-07-28 14:13:54.000000000 +0200
1718 * Project: Gigabit Ethernet Adapters, Common Modules
1719 - * Version: $Revision$
1721 + * Version: $Revision$
1723 * Purpose: Defines and Macros for the Gigabit Ethernet Adapter Product Family
1725 ******************************************************************************/
1727 /******************************************************************************
1730 * (C)Copyright 1998-2002 SysKonnect.
1731 - * (C)Copyright 2002-2003 Marvell.
1732 + * (C)Copyright 2002-2006 Marvell.
1734 * This program is free software; you can redistribute it and/or modify
1735 * it under the terms of the GNU General Public License as published by
1736 * the Free Software Foundation; either version 2 of the License, or
1737 * (at your option) any later version.
1739 * The information in this file is provided "AS IS" without warranty.
1742 ******************************************************************************/
1744 @@ -114,6 +115,16 @@
1745 #define SHIFT1(x) ((x) << 1)
1746 #define SHIFT0(x) ((x) << 0)
1748 +/* Macro for arbitrary alignment of a given pointer */
1749 +#define ALIGN_ADDR( ADDRESS, GRANULARITY ) { \
1750 + SK_UPTR addr = (SK_UPTR)(ADDRESS); \
1751 + if (addr & ((GRANULARITY)-1)) { \
1752 + addr += (GRANULARITY); \
1753 + addr &= ~(SK_UPTR)((GRANULARITY)-1); \
1754 + ADDRESS = (void *)addr; \
1759 * Configuration Space header
1760 * Since this module is used for different OS', those may be
1761 @@ -132,34 +143,81 @@
1762 #define PCI_BIST 0x0f /* 8 bit Built-in selftest */
1763 #define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */
1764 #define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */
1765 - /* Byte 0x18..0x2b: reserved */
1766 + /* Bytes 0x18..0x2b: reserved */
1767 #define PCI_SUB_VID 0x2c /* 16 bit Subsystem Vendor ID */
1768 #define PCI_SUB_ID 0x2e /* 16 bit Subsystem ID */
1769 #define PCI_BASE_ROM 0x30 /* 32 bit Expansion ROM Base Address */
1770 -#define PCI_CAP_PTR 0x34 /* 8 bit Capabilities Ptr */
1771 - /* Byte 0x35..0x3b: reserved */
1772 +#define PCI_CAP_PTR 0x34 /* 8 bit Capabilities Pointer */
1773 + /* Bytes 0x35..0x3b: reserved */
1774 #define PCI_IRQ_LINE 0x3c /* 8 bit Interrupt Line */
1775 #define PCI_IRQ_PIN 0x3d /* 8 bit Interrupt Pin */
1776 #define PCI_MIN_GNT 0x3e /* 8 bit Min_Gnt */
1777 #define PCI_MAX_LAT 0x3f /* 8 bit Max_Lat */
1778 /* Device Dependent Region */
1779 -#define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */
1780 -#define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */
1781 +#define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */
1782 +#define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */
1783 /* Power Management Region */
1784 -#define PCI_PM_CAP_ID 0x48 /* 8 bit Power Management Cap. ID */
1785 -#define PCI_PM_NITEM 0x49 /* 8 bit Next Item Ptr */
1786 -#define PCI_PM_CAP_REG 0x4a /* 16 bit Power Management Capabilities */
1787 -#define PCI_PM_CTL_STS 0x4c /* 16 bit Power Manag. Control/Status */
1788 +#define PCI_PM_CAP_ID 0x48 /* 8 bit Power Management Cap. ID */
1789 +#define PCI_PM_NITEM 0x49 /* 8 bit PM Next Item Pointer */
1790 +#define PCI_PM_CAP_REG 0x4a /* 16 bit Power Management Capabilities */
1791 +#define PCI_PM_CTL_STS 0x4c /* 16 bit Power Manag. Control/Status */
1792 /* Byte 0x4e: reserved */
1793 -#define PCI_PM_DAT_REG 0x4f /* 8 bit Power Manag. Data Register */
1794 +#define PCI_PM_DAT_REG 0x4f /* 8 bit Power Manag. Data Register */
1796 -#define PCI_VPD_CAP_ID 0x50 /* 8 bit VPD Cap. ID */
1797 -#define PCI_VPD_NITEM 0x51 /* 8 bit Next Item Ptr */
1798 -#define PCI_VPD_ADR_REG 0x52 /* 16 bit VPD Address Register */
1799 -#define PCI_VPD_DAT_REG 0x54 /* 32 bit VPD Data Register */
1800 - /* Byte 0x58..0x59: reserved */
1801 -#define PCI_SER_LD_CTRL 0x5a /* 16 bit SEEPROM Loader Ctrl (YUKON only) */
1802 - /* Byte 0x5c..0xff: reserved */
1803 +#define PCI_VPD_CAP_ID 0x50 /* 8 bit VPD Cap. ID */
1804 +#define PCI_VPD_NITEM 0x51 /* 8 bit VPD Next Item Pointer */
1805 +#define PCI_VPD_ADR_REG 0x52 /* 16 bit VPD Address Register */
1806 +#define PCI_VPD_DAT_REG 0x54 /* 32 bit VPD Data Register */
1807 + /* Bytes 0x58..0x59: reserved */
1808 +#define PCI_SER_LD_CTRL 0x5a /* 16 bit SEEPROM Loader Ctrl (YUKON only) */
1809 + /* Bytes 0x5c..0xfc: used by Yukon-2 */
1810 +#define PCI_MSI_CAP_ID 0x5c /* 8 bit MSI Capability ID Register */
1811 +#define PCI_MSI_NITEM 0x5d /* 8 bit MSI Next Item Pointer */
1812 +#define PCI_MSI_CTRL 0x5e /* 16 bit MSI Message Control */
1813 +#define PCI_MSI_ADR_LO 0x60 /* 32 bit MSI Message Address (Lower) */
1814 +#define PCI_MSI_ADR_HI 0x64 /* 32 bit MSI Message Address (Upper) */
1815 +#define PCI_MSI_DATA 0x68 /* 16 bit MSI Message Data */
1816 + /* Bytes 0x6a..0x6b: reserved */
1817 +#define PCI_X_CAP_ID 0x6c /* 8 bit PCI-X Capability ID Register */
1818 +#define PCI_X_NITEM 0x6d /* 8 bit PCI-X Next Item Pointer */
1819 +#define PCI_X_COMMAND 0x6e /* 16 bit PCI-X Command */
1820 +#define PCI_X_PE_STAT 0x70 /* 32 bit PCI-X / PE Status */
1821 +#define PCI_CAL_CTRL 0x74 /* 16 bit PCI Calibration Control Register */
1822 +#define PCI_CAL_STAT 0x76 /* 16 bit PCI Calibration Status Register */
1823 +#define PCI_DISC_CNT 0x78 /* 16 bit PCI Discard Counter */
1824 +#define PCI_RETRY_CNT 0x7a /* 8 bit PCI Retry Counter */
1825 + /* Byte 0x7b: reserved */
1826 +#define PCI_OUR_STATUS 0x7c /* 32 bit Adapter Status Register */
1827 +#define PCI_OUR_REG_3 0x80 /* 32 bit Our Register 3 (Yukon-ECU only) */
1828 +#define PCI_OUR_REG_4 0x84 /* 32 bit Our Register 4 (Yukon-ECU only) */
1829 +#define PCI_OUR_REG_5 0x88 /* 32 bit Our Register 5 (Yukon-ECU only) */
1830 + /* Bytes 0x8c..0xdf: reserved */
1832 +/* PCI Express Capability */
1833 +#define PEX_CAP_ID 0xe0 /* 8 bit PEX Capability ID */
1834 +#define PEX_NITEM 0xe1 /* 8 bit PEX Next Item Pointer */
1835 +#define PEX_CAP_REG 0xe2 /* 16 bit PEX Capability Register */
1836 +#define PEX_DEV_CAP 0xe4 /* 32 bit PEX Device Capabilities */
1837 +#define PEX_DEV_CTRL 0xe8 /* 16 bit PEX Device Control */
1838 +#define PEX_DEV_STAT 0xea /* 16 bit PEX Device Status */
1839 +#define PEX_LNK_CAP 0xec /* 32 bit PEX Link Capabilities */
1840 +#define PEX_LNK_CTRL 0xf0 /* 16 bit PEX Link Control */
1841 +#define PEX_LNK_STAT 0xf2 /* 16 bit PEX Link Status */
1842 + /* Bytes 0xf4..0xff: reserved */
1844 +/* PCI Express Extended Capabilities */
1845 +#define PEX_ADV_ERR_REP 0x100 /* 32 bit PEX Advanced Error Reporting */
1846 +#define PEX_UNC_ERR_STAT 0x104 /* 32 bit PEX Uncorr. Errors Status */
1847 +#define PEX_UNC_ERR_MASK 0x108 /* 32 bit PEX Uncorr. Errors Mask */
1848 +#define PEX_UNC_ERR_SEV 0x10c /* 32 bit PEX Uncorr. Errors Severity */
1849 +#define PEX_COR_ERR_STAT 0x110 /* 32 bit PEX Correc. Errors Status */
1850 +#define PEX_COR_ERR_MASK 0x114 /* 32 bit PEX Correc. Errors Mask */
1851 +#define PEX_ADV_ERR_CAP_C 0x118 /* 32 bit PEX Advanced Error Cap./Ctrl */
1852 +#define PEX_HEADER_LOG 0x11c /* 4x32 bit PEX Header Log Register */
1854 +/* PCI Express Ack Timer for 1x Link */
1855 +#define PEX_ACK_LAT_TOX1 0x228 /* 16 bit PEX Ack Latency Timeout x1 */
1856 +#define PEX_ACK_RPLY_TOX1 0x22a /* 16 bit PEX Ack Reply Timeout val x1 */
1859 * I2C Address (PCI Config)
1860 @@ -180,13 +238,13 @@
1861 #define PCI_ADSTEP BIT_7S /* Address Stepping */
1862 #define PCI_PERREN BIT_6S /* Parity Report Response enable */
1863 #define PCI_VGA_SNOOP BIT_5S /* VGA palette snoop */
1864 -#define PCI_MWIEN BIT_4S /* Memory write an inv cycl ena */
1865 +#define PCI_MWIEN BIT_4S /* Memory write an inv cycl enable */
1866 #define PCI_SCYCEN BIT_3S /* Special Cycle enable */
1867 #define PCI_BMEN BIT_2S /* Bus Master enable */
1868 #define PCI_MEMEN BIT_1S /* Memory Space Access enable */
1869 #define PCI_IOEN BIT_0S /* I/O Space Access enable */
1871 -#define PCI_COMMAND_VAL (PCI_FBTEN | PCI_SERREN | PCI_PERREN | PCI_MWIEN |\
1872 +#define PCI_COMMAND_VAL (PCI_INT_DIS | PCI_SERREN | PCI_PERREN | \
1873 PCI_BMEN | PCI_MEMEN | PCI_IOEN)
1875 /* PCI_STATUS 16 bit Status */
1878 /* PCI_HEADER_T 8 bit Header Type */
1879 #define PCI_HD_MF_DEV BIT_7S /* 0= single, 1= multi-func dev */
1880 -#define PCI_HD_TYPE 0x7f /* Bit 6..0: Header Layout 0= normal */
1881 +#define PCI_HD_TYPE 0x7f /* Bit 6..0: Header Layout (0=normal) */
1883 /* PCI_BIST 8 bit Built-in selftest */
1884 /* Built-in Self test not supported (optional) */
1885 @@ -229,33 +287,42 @@
1886 #define PCI_MEMSIZE 0x4000L /* use 16 kB Memory Base */
1887 #define PCI_MEMBASE_MSK 0xffffc000L /* Bit 31..14: Memory Base Address */
1888 #define PCI_MEMSIZE_MSK 0x00003ff0L /* Bit 13.. 4: Memory Size Req. */
1889 -#define PCI_PREFEN BIT_3 /* Prefetchable */
1890 -#define PCI_MEM_TYP (3L<<2) /* Bit 2.. 1: Memory Type */
1891 +#define PCI_PREFEN BIT_3 /* Prefetch enable */
1892 +#define PCI_MEM_TYP_MSK (3L<<1) /* Bit 2.. 1: Memory Type Mask */
1893 +#define PCI_MEMSPACE BIT_0 /* Memory Space Indicator */
1895 #define PCI_MEM32BIT (0L<<1) /* Base addr anywhere in 32 Bit range */
1896 #define PCI_MEM1M (1L<<1) /* Base addr below 1 MegaByte */
1897 #define PCI_MEM64BIT (2L<<1) /* Base addr anywhere in 64 Bit range */
1898 -#define PCI_MEMSPACE BIT_0 /* Memory Space Indicator */
1900 /* PCI_BASE_2ND 32 bit 2nd Base address */
1901 #define PCI_IOBASE 0xffffff00L /* Bit 31.. 8: I/O Base address */
1902 #define PCI_IOSIZE 0x000000fcL /* Bit 7.. 2: I/O Size Requirements */
1903 - /* Bit 1: reserved */
1904 + /* Bit 1: reserved */
1905 #define PCI_IOSPACE BIT_0 /* I/O Space Indicator */
1907 /* PCI_BASE_ROM 32 bit Expansion ROM Base Address */
1908 #define PCI_ROMBASE_MSK 0xfffe0000L /* Bit 31..17: ROM Base address */
1909 #define PCI_ROMBASE_SIZ (0x1cL<<14) /* Bit 16..14: Treat as Base or Size */
1910 #define PCI_ROMSIZE (0x38L<<11) /* Bit 13..11: ROM Size Requirements */
1911 - /* Bit 10.. 1: reserved */
1912 + /* Bit 10.. 1: reserved */
1913 #define PCI_ROMEN BIT_0 /* Address Decode enable */
1915 /* Device Dependent Region */
1916 /* PCI_OUR_REG_1 32 bit Our Register 1 */
1917 - /* Bit 31..29: reserved */
1918 + /* Bit 31..29: reserved */
1919 #define PCI_PHY_COMA BIT_28 /* Set PHY to Coma Mode (YUKON only) */
1920 #define PCI_TEST_CAL BIT_27 /* Test PCI buffer calib. (YUKON only) */
1921 #define PCI_EN_CAL BIT_26 /* Enable PCI buffer calib. (YUKON only) */
1922 #define PCI_VIO BIT_25 /* PCI I/O Voltage, 0 = 3.3V, 1 = 5V */
1924 +#define PCI_Y2_PIG_ENA BIT_31 /* Enable Plug-in-Go (YUKON-2) */
1925 +#define PCI_Y2_DLL_DIS BIT_30 /* Disable PCI DLL (YUKON-2) */
1926 +#define PCI_Y2_PHY2_COMA BIT_29 /* Set PHY 2 to Coma Mode (YUKON-2) */
1927 +#define PCI_Y2_PHY1_COMA BIT_28 /* Set PHY 1 to Coma Mode (YUKON-2) */
1928 +#define PCI_Y2_PHY2_POWD BIT_27 /* Set PHY 2 to Power Down (YUKON-2) */
1929 +#define PCI_Y2_PHY1_POWD BIT_26 /* Set PHY 1 to Power Down (YUKON-2) */
1930 + /* Bit 25: reserved */
1931 #define PCI_DIS_BOOT BIT_24 /* Disable BOOT via ROM */
1932 #define PCI_EN_IO BIT_23 /* Mapping to I/O space */
1933 #define PCI_EN_FPROM BIT_22 /* Enable FLASH mapping to memory */
1934 @@ -266,9 +333,10 @@
1935 #define PCI_PAGE_32K (1L<<20) /* 32 k pages */
1936 #define PCI_PAGE_64K (2L<<20) /* 64 k pages */
1937 #define PCI_PAGE_128K (3L<<20) /* 128 k pages */
1938 - /* Bit 19: reserved */
1939 -#define PCI_PAGEREG (7L<<16) /* Bit 18..16: Page Register */
1940 + /* Bit 19: reserved */
1941 +#define PCI_PAGEREG (7L<<16) /* Bit 18..16: Page Register */
1942 #define PCI_NOTAR BIT_15 /* No turnaround cycle */
1943 +#define PCI_PEX_LEGNAT BIT_15 /* PEX PM legacy/native mode (YUKON-2) */
1944 #define PCI_FORCE_BE BIT_14 /* Assert all BEs on MR */
1945 #define PCI_DIS_MRL BIT_13 /* Disable Mem Read Line */
1946 #define PCI_DIS_MRM BIT_12 /* Disable Mem Read Multiple */
1947 @@ -278,13 +346,21 @@
1948 #define PCI_DIS_PCI_CLK BIT_8 /* Disable PCI clock driving */
1949 #define PCI_SKEW_DAS (0xfL<<4) /* Bit 7.. 4: Skew Ctrl, DAS Ext */
1950 #define PCI_SKEW_BASE 0xfL /* Bit 3.. 0: Skew Ctrl, Base */
1951 +#define PCI_CLS_OPT BIT_3 /* Cache Line Size opt. PCI-X (YUKON-2) */
1953 +/* Yukon-EC Ultra only */
1954 + /* Bit 14..10: reserved */
1955 +#define PCI_PHY_LNK_TIM_MSK (3L<<8) /* Bit 9.. 8: GPHY Link Trigger Timer */
1956 +#define PCI_ENA_L1_EVENT BIT_7 /* Enable PEX L1 Event */
1957 +#define PCI_ENA_GPHY_LNK BIT_6 /* Enable PEX L1 on GPHY Link down */
1958 +#define PCI_FORCE_PEX_L1 BIT_5 /* Force to PEX L1 */
1959 + /* Bit 4.. 0: reserved */
1961 /* PCI_OUR_REG_2 32 bit Our Register 2 */
1962 #define PCI_VPD_WR_THR (0xffL<<24) /* Bit 31..24: VPD Write Threshold */
1963 #define PCI_DEV_SEL (0x7fL<<17) /* Bit 23..17: EEPROM Device Select */
1964 #define PCI_VPD_ROM_SZ (7L<<14) /* Bit 16..14: VPD ROM Size */
1965 - /* Bit 13..12: reserved */
1966 + /* Bit 13..12: reserved */
1967 #define PCI_PATCH_DIR (0xfL<<8) /* Bit 11.. 8: Ext Patches dir 3..0 */
1968 #define PCI_PATCH_DIR_3 BIT_11
1969 #define PCI_PATCH_DIR_2 BIT_10
1970 @@ -296,22 +372,21 @@
1971 #define PCI_EXT_PATCH_1 BIT_5
1972 #define PCI_EXT_PATCH_0 BIT_4
1973 #define PCI_EN_DUMMY_RD BIT_3 /* Enable Dummy Read */
1974 -#define PCI_REV_DESC BIT_2 /* Reverse Desc. Bytes */
1975 - /* Bit 1: reserved */
1976 +#define PCI_REV_DESC BIT_2 /* Reverse Descriptor Bytes */
1977 + /* Bit 1: reserved */
1978 #define PCI_USEDATA64 BIT_0 /* Use 64Bit Data bus ext */
1981 -/* Power Management Region */
1982 +/* Power Management (PM) Region */
1983 /* PCI_PM_CAP_REG 16 bit Power Management Capabilities */
1984 -#define PCI_PME_SUP_MSK (0x1f<<11) /* Bit 15..11: PM Event Support Mask */
1985 -#define PCI_PME_D3C_SUP BIT_15S /* PME from D3cold Support (if Vaux) */
1986 +#define PCI_PME_SUP_MSK (0x1f<<11) /* Bit 15..11: PM Event (PME) Supp. Mask */
1987 +#define PCI_PME_D3C_SUP BIT_15S /* PME from D3cold Support (if VAUX) */
1988 #define PCI_PME_D3H_SUP BIT_14S /* PME from D3hot Support */
1989 #define PCI_PME_D2_SUP BIT_13S /* PME from D2 Support */
1990 #define PCI_PME_D1_SUP BIT_12S /* PME from D1 Support */
1991 #define PCI_PME_D0_SUP BIT_11S /* PME from D0 Support */
1992 #define PCI_PM_D2_SUP BIT_10S /* D2 Support in 33 MHz mode */
1993 #define PCI_PM_D1_SUP BIT_9S /* D1 Support */
1994 - /* Bit 8.. 6: reserved */
1995 + /* Bit 8.. 6: reserved */
1996 #define PCI_PM_DSI BIT_5S /* Device Specific Initialization */
1997 #define PCI_PM_APS BIT_4S /* Auxialiary Power Source */
1998 #define PCI_PME_CLOCK BIT_3S /* PM Event Clock */
2000 #define PCI_PM_DAT_SCL (3<<13) /* Bit 14..13: Data Reg. scaling factor */
2001 #define PCI_PM_DAT_SEL (0xf<<9) /* Bit 12.. 9: PM data selector field */
2002 #define PCI_PME_EN BIT_8S /* Enable PME# generation (YUKON only) */
2003 - /* Bit 7.. 2: reserved */
2004 + /* Bit 7.. 2: reserved */
2005 #define PCI_PM_STATE_MSK 3 /* Bit 1.. 0: Power Management State */
2007 #define PCI_PM_STATE_D0 0 /* D0: Operational (default) */
2008 @@ -333,7 +408,151 @@
2010 /* PCI_VPD_ADR_REG 16 bit VPD Address Register */
2011 #define PCI_VPD_FLAG BIT_15S /* starts VPD rd/wr cycle */
2012 -#define PCI_VPD_ADR_MSK 0x7fffL /* Bit 14.. 0: VPD address mask */
2013 +#define PCI_VPD_ADR_MSK 0x7fffL /* Bit 14.. 0: VPD Address Mask */
2015 +/* PCI_OUR_STATUS 32 bit Adapter Status Register (Yukon-2) */
2016 +#define PCI_OS_PCI64B BIT_31 /* Conventional PCI 64 bits Bus */
2017 +#define PCI_OS_PCIX BIT_30 /* PCI-X Bus */
2018 +#define PCI_OS_MODE_MSK (3L<<28) /* Bit 29..28: PCI-X Bus Mode Mask */
2019 +#define PCI_OS_PCI66M BIT_27 /* PCI 66 MHz Bus */
2020 +#define PCI_OS_PCI_X BIT_26 /* PCI/PCI-X Bus (0 = PEX) */
2021 +#define PCI_OS_DLLE_MSK (3L<<24) /* Bit 25..24: DLL Status Indication */
2022 +#define PCI_OS_DLLR_MSK (0xfL<<20) /* Bit 23..20: DLL Row Counters Values */
2023 +#define PCI_OS_DLLC_MSK (0xfL<<16) /* Bit 19..16: DLL Col. Counters Values */
2024 + /* Bit 15.. 8: reserved */
2026 +#define PCI_OS_SPEED(val) ((val & PCI_OS_MODE_MSK) >> 28) /* PCI-X Speed */
2027 +/* possible values for the speed field of the register */
2028 +#define PCI_OS_SPD_PCI 0 /* PCI Conventional Bus */
2029 +#define PCI_OS_SPD_X66 1 /* PCI-X 66MHz Bus */
2030 +#define PCI_OS_SPD_X100 2 /* PCI-X 100MHz Bus */
2031 +#define PCI_OS_SPD_X133 3 /* PCI-X 133MHz Bus */
2033 +/* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */
2034 + /* Bit 31..18: reserved */
2035 +#define P_CLK_COR_REGS_D0_DIS BIT_17 /* Disable Clock Core Regs in D0 */
2036 +#define P_CLK_PCI_REGS_D0_DIS BIT_16 /* Disable Clock PCI Regs in D0 */
2037 +#define P_CLK_COR_YTB_ARB_DIS BIT_15 /* Disable Clock YTB Arbiter */
2038 +#define P_CLK_MAC_LNK1_D3_DIS BIT_14 /* Disable Clock MAC Link1 in D3 */
2039 +#define P_CLK_COR_LNK1_D0_DIS BIT_13 /* Disable Clock Core Link1 in D0 */
2040 +#define P_CLK_MAC_LNK1_D0_DIS BIT_12 /* Disable Clock MAC Link1 in D0 */
2041 +#define P_CLK_COR_LNK1_D3_DIS BIT_11 /* Disable Clock Core Link1 in D3 */
2042 +#define P_CLK_PCI_MST_ARB_DIS BIT_10 /* Disable Clock PCI Master Arb. */
2043 +#define P_CLK_COR_REGS_D3_DIS BIT_9 /* Disable Clock Core Regs in D3 */
2044 +#define P_CLK_PCI_REGS_D3_DIS BIT_8 /* Disable Clock PCI Regs in D3 */
2045 +#define P_CLK_REF_LNK1_GM_DIS BIT_7 /* Disable Clock Ref. Link1 GMAC */
2046 +#define P_CLK_COR_LNK1_GM_DIS BIT_6 /* Disable Clock Core Link1 GMAC */
2047 +#define P_CLK_PCI_COMMON_DIS BIT_5 /* Disable Clock PCI Common */
2048 +#define P_CLK_COR_COMMON_DIS BIT_4 /* Disable Clock Core Common */
2049 +#define P_CLK_PCI_LNK1_BMU_DIS BIT_3 /* Disable Clock PCI Link1 BMU */
2050 +#define P_CLK_COR_LNK1_BMU_DIS BIT_2 /* Disable Clock Core Link1 BMU */
2051 +#define P_CLK_PCI_LNK1_BIU_DIS BIT_1 /* Disable Clock PCI Link1 BIU */
2052 +#define P_CLK_COR_LNK1_BIU_DIS BIT_0 /* Disable Clock Core Link1 BIU */
2054 +/* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
2055 +#define P_PEX_LTSSM_STAT_MSK (0x7fL<<25) /* Bit 31..25: PEX LTSSM Mask */
2056 + /* (Link Training & Status State Machine) */
2057 + /* Bit 24: reserved */
2058 +#define P_TIMER_VALUE_MSK (0xffL<<16) /* Bit 23..16: Timer Value Mask */
2059 +#define P_FORCE_ASPM_REQUEST BIT_15 /* Force ASPM Request (A1 only) */
2060 + /* (Active State Power Management) */
2061 + /* Bit 14..12: Force ASPM on Event */
2062 +#define P_ASPM_GPHY_LINK_DOWN BIT_14 /* GPHY Link Down (A1 only) */
2063 +#define P_ASPM_INT_FIFO_EMPTY BIT_13 /* Internal FIFO Empty (A1 only) */
2064 +#define P_ASPM_CLKRUN_REQUEST BIT_12 /* CLKRUN Request (A1 only) */
2065 + /* Bit 11.. 8: reserved */
2066 +#define P_ASPM_FORCE_ASPM_L1 BIT_7 /* Force ASPM L1 Enable (A1b only) */
2067 +#define P_ASPM_FORCE_ASPM_L0S BIT_6 /* Force ASPM L0s Enable (A1b only) */
2068 +#define P_ASPM_FORCE_CLKREQ_PIN BIT_5 /* Force CLKREQn pin low (A1b only) */
2069 +#define P_ASPM_FORCE_CLKREQ_ENA BIT_4 /* Force CLKREQ Enable (A1b only) */
2070 +#define P_ASPM_CLKREQ_PAD_CTL BIT_3 /* CLKREQ PAD Control (A1 only) */
2071 +#define P_ASPM_A1_MODE_SELECT BIT_2 /* A1 Mode Select (A1 only) */
2072 +#define P_CLK_GATE_PEX_UNIT_ENA BIT_1 /* Enable Gate PEX Unit Clock */
2073 +#define P_CLK_GATE_ROOT_COR_ENA BIT_0 /* Enable Gate Root Core Clock */
2075 +#define P_PEX_LTSSM_STAT(x) (SHIFT25(x) & P_PEX_LTSSM_STAT_MSK)
2076 +#define P_PEX_LTSSM_L1_STAT 0x34
2077 +#define P_PEX_LTSSM_DET_STAT 0x01
2079 +#define P_ASPM_CONTROL_MSK (P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN | \
2080 + P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY)
2082 +/* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */
2083 + /* Bit 31..27: reserved */
2084 + /* Bit 26..16: Release Clock on Event */
2085 +#define P_REL_PCIE_RST_DE_ASS BIT_26 /* PCIe Reset De-Asserted */
2086 +#define P_REL_GPHY_REC_PACKET BIT_25 /* GPHY Received Packet */
2087 +#define P_REL_INT_FIFO_N_EMPTY BIT_24 /* Internal FIFO Not Empty */
2088 +#define P_REL_MAIN_PWR_AVAIL BIT_23 /* Main Power Available */
2089 +#define P_REL_CLKRUN_REQ_REL BIT_22 /* CLKRUN Request Release */
2090 +#define P_REL_PCIE_RESET_ASS BIT_21 /* PCIe Reset Asserted */
2091 +#define P_REL_PME_ASSERTED BIT_20 /* PME Asserted */
2092 +#define P_REL_PCIE_EXIT_L1_ST BIT_19 /* PCIe Exit L1 State */
2093 +#define P_REL_LOADER_NOT_FIN BIT_18 /* EPROM Loader Not Finished */
2094 +#define P_REL_PCIE_RX_EX_IDLE BIT_17 /* PCIe Rx Exit Electrical Idle State */
2095 +#define P_REL_GPHY_LINK_UP BIT_16 /* GPHY Link Up */
2096 + /* Bit 15..11: reserved */
2097 + /* Bit 10.. 0: Mask for Gate Clock */
2098 +#define P_GAT_PCIE_RST_DE_ASS BIT_10 /* PCIe Reset De-Asserted */
2099 +#define P_GAT_GPHY_N_REC_PACKET BIT_9 /* GPHY Not Received Packet */
2100 +#define P_GAT_INT_FIFO_EMPTY BIT_8 /* Internal FIFO Empty */
2101 +#define P_GAT_MAIN_PWR_N_AVAIL BIT_7 /* Main Power Not Available */
2102 +#define P_GAT_CLKRUN_REQ_REL BIT_6 /* CLKRUN Not Requested */
2103 +#define P_GAT_PCIE_RESET_ASS BIT_5 /* PCIe Reset Asserted */
2104 +#define P_GAT_PME_DE_ASSERTED BIT_4 /* PME De-Asserted */
2105 +#define P_GAT_PCIE_ENTER_L1_ST BIT_3 /* PCIe Enter L1 State */
2106 +#define P_GAT_LOADER_FINISHED BIT_2 /* EPROM Loader Finished */
2107 +#define P_GAT_PCIE_RX_EL_IDLE BIT_1 /* PCIe Rx Electrical Idle State */
2108 +#define P_GAT_GPHY_LINK_DOWN BIT_0 /* GPHY Link Down */
2110 +/* PEX_DEV_CTRL 16 bit PEX Device Control (Yukon-2) */
2111 + /* Bit 15 reserved */
2112 +#define PEX_DC_MAX_RRS_MSK (7<<12) /* Bit 14..12: Max. Read Request Size */
2113 +#define PEX_DC_EN_NO_SNOOP BIT_11S /* Enable No Snoop */
2114 +#define PEX_DC_EN_AUX_POW BIT_10S /* Enable AUX Power */
2115 +#define PEX_DC_EN_PHANTOM BIT_9S /* Enable Phantom Functions */
2116 +#define PEX_DC_EN_EXT_TAG BIT_8S /* Enable Extended Tag Field */
2117 +#define PEX_DC_MAX_PLS_MSK (7<<5) /* Bit 7.. 5: Max. Payload Size Mask */
2118 +#define PEX_DC_EN_REL_ORD BIT_4S /* Enable Relaxed Ordering */
2119 +#define PEX_DC_EN_UNS_RQ_RP BIT_3S /* Enable Unsupported Request Reporting */
2120 +#define PEX_DC_EN_FAT_ER_RP BIT_2S /* Enable Fatal Error Reporting */
2121 +#define PEX_DC_EN_NFA_ER_RP BIT_1S /* Enable Non-Fatal Error Reporting */
2122 +#define PEX_DC_EN_COR_ER_RP BIT_0S /* Enable Correctable Error Reporting */
2124 +#define PEX_DC_MAX_RD_RQ_SIZE(x) (SHIFT12(x) & PEX_DC_MAX_RRS_MSK)
2126 +/* PEX_LNK_CAP 32 bit PEX Link Capabilities */
2127 +#define PEX_CAP_MAX_WI_MSK (0x3f<<4) /* Bit 9.. 4: Max. Link Width Mask */
2128 +#define PEX_CAP_MAX_SP_MSK 0x0f /* Bit 3.. 0: Max. Link Speed Mask */
2130 +/* PEX_LNK_CTRL 16 bit PEX Link Control (Yukon-2) */
2131 +#define PEX_LC_CLK_PM_ENA BIT_8S /* Enable Clock Power Management (CLKREQ) */
2133 +/* PEX_LNK_STAT 16 bit PEX Link Status (Yukon-2) */
2134 + /* Bit 15..13 reserved */
2135 +#define PEX_LS_SLOT_CLK_CFG BIT_12S /* Slot Clock Config */
2136 +#define PEX_LS_LINK_TRAIN BIT_11S /* Link Training */
2137 +#define PEX_LS_TRAIN_ERROR BIT_10S /* Training Error */
2138 +#define PEX_LS_LINK_WI_MSK (0x3f<<4) /* Bit 9.. 4: Neg. Link Width Mask */
2139 +#define PEX_LS_LINK_SP_MSK 0x0f /* Bit 3.. 0: Link Speed Mask */
2141 +/* PEX_UNC_ERR_STAT 16 bit PEX Uncorrectable Errors Status (Yukon-2) */
2142 + /* Bit 31..21 reserved */
2143 +#define PEX_UNSUP_REQ BIT_20 /* Unsupported Request Error */
2144 + /* ECRC Error (not supported) */
2145 +#define PEX_MALFOR_TLP BIT_18 /* Malformed TLP */
2146 +#define PEX_RX_OV BIT_17 /* Receiver Overflow (not supported) */
2147 +#define PEX_UNEXP_COMP BIT_16 /* Unexpected Completion */
2148 + /* Completer Abort (not supported) */
2149 +#define PEX_COMP_TO BIT_14 /* Completion Timeout */
2150 +#define PEX_FLOW_CTRL_P BIT_13 /* Flow Control Protocol Error */
2151 +#define PEX_POIS_TLP BIT_12 /* Poisoned TLP */
2152 + /* Bit 11.. 5: reserved */
2153 +#define PEX_DATA_LINK_P BIT_4 /* Data Link Protocol Error */
2154 + /* Bit 3.. 1: reserved */
2155 + /* Training Error (not supported) */
2157 +#define PEX_FATAL_ERRORS (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P)
2159 /* Control Register File (Address Map) */
2161 @@ -342,15 +561,21 @@
2163 #define B0_RAP 0x0000 /* 8 bit Register Address Port */
2164 /* 0x0001 - 0x0003: reserved */
2165 -#define B0_CTST 0x0004 /* 16 bit Control/Status register */
2166 -#define B0_LED 0x0006 /* 8 Bit LED register */
2167 +#define B0_CTST 0x0004 /* 16 bit Control/Status Register */
2168 +#define B0_LED 0x0006 /* 8 Bit LED Register */
2169 #define B0_POWER_CTRL 0x0007 /* 8 Bit Power Control reg (YUKON only) */
2170 #define B0_ISRC 0x0008 /* 32 bit Interrupt Source Register */
2171 #define B0_IMSK 0x000c /* 32 bit Interrupt Mask Register */
2172 #define B0_HWE_ISRC 0x0010 /* 32 bit HW Error Interrupt Src Reg */
2173 #define B0_HWE_IMSK 0x0014 /* 32 bit HW Error Interrupt Mask Reg */
2174 -#define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg */
2175 - /* 0x001c: reserved */
2176 +#define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg 1 */
2178 +/* Special ISR registers (Yukon-2 only) */
2179 +#define B0_Y2_SP_ISRC2 0x001c /* 32 bit Special Interrupt Source Reg 2 */
2180 +#define B0_Y2_SP_ISRC3 0x0020 /* 32 bit Special Interrupt Source Reg 3 */
2181 +#define B0_Y2_SP_EISR 0x0024 /* 32 bit Enter ISR Register */
2182 +#define B0_Y2_SP_LISR 0x0028 /* 32 bit Leave ISR Register */
2183 +#define B0_Y2_SP_ICR 0x002c /* 32 bit Interrupt Control Register */
2185 /* B0 XMAC 1 registers (GENESIS only) */
2186 #define B0_XM1_IMSK 0x0020 /* 16 bit r/w XMAC 1 Interrupt Mask Register*/
2188 #define B0_XM2_PHY_DATA 0x0054 /* 16 bit r/w XMAC 2 PHY Data Register */
2189 /* 0x0056 - 0x005f: reserved */
2191 -/* BMU Control Status Registers */
2192 +/* BMU Control Status Registers (Yukon and Genesis) */
2193 #define B0_R1_CSR 0x0060 /* 32 bit BMU Ctrl/Stat Rx Queue 1 */
2194 #define B0_R2_CSR 0x0064 /* 32 bit BMU Ctrl/Stat Rx Queue 2 */
2195 #define B0_XS1_CSR 0x0068 /* 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
2200 -/* NA reg = 48 bit Network Address Register, 3x16 or 8x8 bit readable */
2201 +/* NA reg = 48 bit Network Address Register, 3x16 or 6x8 bit readable */
2202 #define B2_MAC_1 0x0100 /* NA reg MAC Address 1 */
2203 /* 0x0106 - 0x0107: reserved */
2204 #define B2_MAC_2 0x0108 /* NA reg MAC Address 2 */
2205 @@ -400,14 +625,23 @@
2206 #define B2_CONN_TYP 0x0118 /* 8 bit Connector type */
2207 #define B2_PMD_TYP 0x0119 /* 8 bit PMD type */
2208 #define B2_MAC_CFG 0x011a /* 8 bit MAC Configuration / Chip Revision */
2209 -#define B2_CHIP_ID 0x011b /* 8 bit Chip Identification Number */
2210 - /* Eprom registers are currently of no use */
2211 +#define B2_CHIP_ID 0x011b /* 8 bit Chip Identification Number */
2212 + /* Eprom registers */
2213 #define B2_E_0 0x011c /* 8 bit EPROM Byte 0 (ext. SRAM size */
2214 +/* Yukon and Genesis */
2215 #define B2_E_1 0x011d /* 8 bit EPROM Byte 1 (PHY type) */
2216 #define B2_E_2 0x011e /* 8 bit EPROM Byte 2 */
2218 +#define B2_Y2_CLK_GATE 0x011d /* 8 bit Clock Gating (Yukon-2) */
2219 +#define B2_Y2_HW_RES 0x011e /* 8 bit HW Resources (Yukon-2) */
2221 #define B2_E_3 0x011f /* 8 bit EPROM Byte 3 */
2223 +/* Yukon and Genesis */
2224 #define B2_FAR 0x0120 /* 32 bit Flash-Prom Addr Reg/Cnt */
2225 #define B2_FDP 0x0124 /* 8 bit Flash-Prom Data Port */
2227 +#define B2_Y2_CLK_CTRL 0x0120 /* 32 bit Core Clock Frequency Control */
2228 /* 0x0125 - 0x0127: reserved */
2229 #define B2_LD_CTRL 0x0128 /* 8 bit EPROM loader control register */
2230 #define B2_LD_TEST 0x0129 /* 8 bit EPROM loader test register */
2231 @@ -439,6 +673,10 @@
2232 #define B2_BSC_CTRL 0x0178 /* 8 bit Blink Source Counter Control */
2233 #define B2_BSC_STAT 0x0179 /* 8 bit Blink Source Counter Status */
2234 #define B2_BSC_TST 0x017a /* 16 bit Blink Source Counter Test Reg */
2237 +#define Y2_PEX_PHY_DATA 0x0170 /* 16 bit PEX PHY Data Register */
2238 +#define Y2_PEX_PHY_ADDR 0x0172 /* 16 bit PEX PHY Address Register */
2239 /* 0x017c - 0x017f: reserved */
2242 @@ -448,9 +686,14 @@
2243 #define B3_RAM_ADDR 0x0180 /* 32 bit RAM Address, to read or write */
2244 #define B3_RAM_DATA_LO 0x0184 /* 32 bit RAM Data Word (low dWord) */
2245 #define B3_RAM_DATA_HI 0x0188 /* 32 bit RAM Data Word (high dWord) */
2246 +#define B3_RAM_PARITY 0x018c /* 8 bit RAM Parity (Yukon-ECU A1) */
2248 +#define SELECT_RAM_BUFFER(rb, addr) (addr | (rb << 6)) /* Yukon-2 only */
2250 /* 0x018c - 0x018f: reserved */
2252 /* RAM Interface Registers */
2253 +/* Yukon-2: use SELECT_RAM_BUFFER() to access the RAM buffer */
2255 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
2256 * not usable in SW. Please notice these are NOT real timeouts, these are
2258 /* 0x01ea - 0x01eb: reserved */
2259 #define B3_PA_TOVAL_TX2 0x01ec /* 16 bit Timeout Val Tx Path MAC 2 */
2260 /* 0x01ee - 0x01ef: reserved */
2261 -#define B3_PA_CTRL 0x01f0 /* 16 bit Packet Arbiter Ctrl Register */
2262 -#define B3_PA_TEST 0x01f2 /* 16 bit Packet Arbiter Test Register */
2263 +#define B3_PA_CTRL 0x01f0 /* 16 bit Packet Arbiter Ctrl Register */
2264 +#define B3_PA_TEST 0x01f2 /* 16 bit Packet Arbiter Test Register */
2265 /* 0x01f4 - 0x01ff: reserved */
2268 @@ -532,7 +775,16 @@
2269 #define TXA_CTRL 0x0210 /* 8 bit Tx Arbiter Control Register */
2270 #define TXA_TEST 0x0211 /* 8 bit Tx Arbiter Test Register */
2271 #define TXA_STAT 0x0212 /* 8 bit Tx Arbiter Status Register */
2272 - /* 0x0213 - 0x027f: reserved */
2273 + /* 0x0213 - 0x021f: reserved */
2275 + /* RSS key registers for Yukon-2 Family */
2276 +#define B4_RSS_KEY 0x0220 /* 4x32 bit RSS Key register (Yukon-2) */
2277 + /* RSS key register offsets */
2278 +#define KEY_IDX_0 0 /* offset for location of KEY 0 */
2279 +#define KEY_IDX_1 4 /* offset for location of KEY 1 */
2280 +#define KEY_IDX_2 8 /* offset for location of KEY 2 */
2281 +#define KEY_IDX_3 12 /* offset for location of KEY 3 */
2283 /* 0x0280 - 0x0292: MAC 2 */
2284 /* 0x0213 - 0x027f: reserved */
2286 @@ -556,10 +808,10 @@
2288 /* Queue Register Offsets, use Q_ADDR() to access */
2289 #define Q_D 0x00 /* 8*32 bit Current Descriptor */
2290 -#define Q_DA_L 0x20 /* 32 bit Current Descriptor Address Low dWord */
2291 -#define Q_DA_H 0x24 /* 32 bit Current Descriptor Address High dWord */
2292 -#define Q_AC_L 0x28 /* 32 bit Current Address Counter Low dWord */
2293 -#define Q_AC_H 0x2c /* 32 bit Current Address Counter High dWord */
2294 +#define Q_DA_L 0x20 /* 32 bit Current Descriptor Address Low DWord */
2295 +#define Q_DA_H 0x24 /* 32 bit Current Descriptor Address High DWord */
2296 +#define Q_AC_L 0x28 /* 32 bit Current Address Counter Low DWord */
2297 +#define Q_AC_H 0x2c /* 32 bit Current Address Counter High DWord */
2298 #define Q_BC 0x30 /* 32 bit Current Byte Counter */
2299 #define Q_CSR 0x34 /* 32 bit BMU Control/Status Register */
2300 #define Q_F 0x38 /* 32 bit Flag Register */
2301 @@ -570,8 +822,56 @@
2302 #define Q_T1_SV 0x3f /* 8 bit Test Register 1 Supervisor SM */
2303 #define Q_T2 0x40 /* 32 bit Test Register 2 */
2304 #define Q_T3 0x44 /* 32 bit Test Register 3 */
2307 +#define Q_DONE 0x24 /* 16 bit Done Index */
2309 +#define Q_WM 0x40 /* 16 bit FIFO Watermark */
2310 +#define Q_AL 0x42 /* 8 bit FIFO Alignment */
2311 + /* 0x43: reserved */
2313 +#define Q_RX_RSP 0x44 /* 16 bit FIFO Read Shadow Pointer */
2314 +#define Q_RX_RSL 0x46 /* 8 bit FIFO Read Shadow Level */
2315 + /* 0x47: reserved */
2316 +#define Q_RX_RP 0x48 /* 8 bit FIFO Read Pointer */
2317 + /* 0x49: reserved */
2318 +#define Q_RX_RL 0x4a /* 8 bit FIFO Read Level */
2319 + /* 0x4b: reserved */
2320 +#define Q_RX_WP 0x4c /* 8 bit FIFO Write Pointer */
2321 +#define Q_RX_WSP 0x4d /* 8 bit FIFO Write Shadow Pointer */
2322 +#define Q_RX_WL 0x4e /* 8 bit FIFO Write Level */
2323 +#define Q_RX_WSL 0x4f /* 8 bit FIFO Write Shadow Level */
2325 +#define Q_TX_WSP 0x44 /* 16 bit FIFO Write Shadow Pointer */
2326 +#define Q_TX_WSL 0x46 /* 8 bit FIFO Write Shadow Level */
2327 + /* 0x47: reserved */
2328 +#define Q_TX_WP 0x48 /* 8 bit FIFO Write Pointer */
2329 + /* 0x49: reserved */
2330 +#define Q_TX_WL 0x4a /* 8 bit FIFO Write Level */
2331 + /* 0x4b: reserved */
2332 +#define Q_TX_RP 0x4c /* 8 bit FIFO Read Pointer */
2333 + /* 0x4d: reserved */
2334 +#define Q_TX_RL 0x4e /* 8 bit FIFO Read Level */
2335 + /* 0x4f: reserved */
2337 /* 0x48 - 0x7f: reserved */
2339 +/* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/
2340 +#define Y2_B8_PREF_REGS 0x0450
2342 +#define PREF_UNIT_CTRL_REG 0x00 /* 32 bit Prefetch Control register */
2343 +#define PREF_UNIT_LAST_IDX_REG 0x04 /* 16 bit Last Index */
2344 +#define PREF_UNIT_ADDR_LOW_REG 0x08 /* 32 bit List start addr, low part */
2345 +#define PREF_UNIT_ADDR_HI_REG 0x0c /* 32 bit List start addr, high part*/
2346 +#define PREF_UNIT_GET_IDX_REG 0x10 /* 16 bit Get Index */
2347 +#define PREF_UNIT_PUT_IDX_REG 0x14 /* 16 bit Put Index */
2348 +#define PREF_UNIT_FIFO_WP_REG 0x20 /* 8 bit FIFO write pointer */
2349 +#define PREF_UNIT_FIFO_RP_REG 0x24 /* 8 bit FIFO read pointer */
2350 +#define PREF_UNIT_FIFO_WM_REG 0x28 /* 8 bit FIFO watermark */
2351 +#define PREF_UNIT_FIFO_LEV_REG 0x2c /* 8 bit FIFO level */
2353 +#define PREF_UNIT_MASK_IDX 0x0fff
2358 @@ -583,17 +883,17 @@
2359 #define RB_END 0x04 /* 32 bit RAM Buffer End Address */
2360 #define RB_WP 0x08 /* 32 bit RAM Buffer Write Pointer */
2361 #define RB_RP 0x0c /* 32 bit RAM Buffer Read Pointer */
2362 -#define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Pack */
2363 -#define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Pack */
2364 +#define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Packet */
2365 +#define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Packet */
2366 #define RB_RX_UTHP 0x18 /* 32 bit Rx Upper Threshold, High Prio */
2367 #define RB_RX_LTHP 0x1c /* 32 bit Rx Lower Threshold, High Prio */
2368 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
2369 #define RB_PC 0x20 /* 32 bit RAM Buffer Packet Counter */
2370 #define RB_LEV 0x24 /* 32 bit RAM Buffer Level Register */
2371 -#define RB_CTRL 0x28 /* 8 bit RAM Buffer Control Register */
2372 +#define RB_CTRL 0x28 /* 32 bit RAM Buffer Control Register */
2373 #define RB_TST1 0x29 /* 8 bit RAM Buffer Test Register 1 */
2374 -#define RB_TST2 0x2A /* 8 bit RAM Buffer Test Register 2 */
2375 - /* 0x2c - 0x7f: reserved */
2376 +#define RB_TST2 0x2a /* 8 bit RAM Buffer Test Register 2 */
2377 + /* 0x2b - 0x7f: reserved */
2382 * use MR_ADDR() to access
2384 #define RX_MFF_EA 0x0c00 /* 32 bit Receive MAC FIFO End Address */
2385 -#define RX_MFF_WP 0x0c04 /* 32 bit Receive MAC FIFO Write Pointer */
2386 +#define RX_MFF_WP 0x0c04 /* 32 bit Receive MAC FIFO Write Pointer */
2387 /* 0x0c08 - 0x0c0b: reserved */
2388 #define RX_MFF_RP 0x0c0c /* 32 bit Receive MAC FIFO Read Pointer */
2389 #define RX_MFF_PC 0x0c10 /* 32 bit Receive MAC FIFO Packet Cnt */
2390 @@ -628,20 +928,23 @@
2391 #define LNK_LED_REG 0x0c3c /* 8 bit Link LED Register */
2392 /* 0x0c3d - 0x0c3f: reserved */
2394 -/* Receive GMAC FIFO (YUKON only), use MR_ADDR() to access */
2395 +/* Receive GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
2396 #define RX_GMF_EA 0x0c40 /* 32 bit Rx GMAC FIFO End Address */
2397 #define RX_GMF_AF_THR 0x0c44 /* 32 bit Rx GMAC FIFO Almost Full Thresh. */
2398 #define RX_GMF_CTRL_T 0x0c48 /* 32 bit Rx GMAC FIFO Control/Test */
2399 #define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */
2400 #define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */
2401 - /* 0x0c54 - 0x0c5f: reserved */
2402 -#define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */
2403 +#define RX_GMF_TR_THR 0x0c54 /* 32 bit Rx Truncation Threshold (Yukon-2) */
2404 +#define RX_GMF_UP_THR 0x0c58 /* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */
2405 +#define RX_GMF_LP_THR 0x0c5a /* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */
2406 +#define RX_GMF_VLAN 0x0c5c /* 32 bit Rx VLAN Type Register (Yukon-2) */
2407 +#define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */
2408 /* 0x0c64 - 0x0c67: reserved */
2409 -#define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */
2410 +#define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */
2411 /* 0x0c6c - 0x0c6f: reserved */
2412 -#define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */
2413 +#define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */
2414 /* 0x0c74 - 0x0c77: reserved */
2415 -#define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */
2416 +#define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */
2417 /* 0x0c7c - 0x0c7f: reserved */
2421 * use MR_ADDR() to access
2423 #define TX_MFF_EA 0x0d00 /* 32 bit Transmit MAC FIFO End Address */
2424 -#define TX_MFF_WP 0x0d04 /* 32 bit Transmit MAC FIFO WR Pointer */
2425 +#define TX_MFF_WP 0x0d04 /* 32 bit Transmit MAC FIFO WR Pointer */
2426 #define TX_MFF_WSP 0x0d08 /* 32 bit Transmit MAC FIFO WR Shadow Ptr */
2427 #define TX_MFF_RP 0x0d0c /* 32 bit Transmit MAC FIFO RD Pointer */
2428 #define TX_MFF_PC 0x0d10 /* 32 bit Transmit MAC FIFO Packet Cnt */
2429 @@ -676,18 +979,19 @@
2430 #define TX_LED_TST 0x0d29 /* 8 bit Transmit LED Cnt Test Reg */
2431 /* 0x0d2a - 0x0d3f: reserved */
2433 -/* Transmit GMAC FIFO (YUKON only), use MR_ADDR() to access */
2434 +/* Transmit GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
2435 #define TX_GMF_EA 0x0d40 /* 32 bit Tx GMAC FIFO End Address */
2436 -#define TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
2437 +#define TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh. */
2438 #define TX_GMF_CTRL_T 0x0d48 /* 32 bit Tx GMAC FIFO Control/Test */
2439 - /* 0x0d4c - 0x0d5f: reserved */
2440 -#define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */
2441 -#define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
2442 -#define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */
2443 + /* 0x0d4c - 0x0d5b: reserved */
2444 +#define TX_GMF_VLAN 0x0d5c /* 32 bit Tx VLAN Type Register (Yukon-2) */
2445 +#define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */
2446 +#define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Pointer */
2447 +#define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */
2448 /* 0x0d6c - 0x0d6f: reserved */
2449 -#define TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */
2450 -#define TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */
2451 -#define TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */
2452 +#define TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */
2453 +#define TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */
2454 +#define TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */
2455 /* 0x0d7c - 0x0d7f: reserved */
2458 @@ -713,12 +1017,84 @@
2459 #define GMAC_TI_ST_CTRL 0x0e18 /* 8 bit Time Stamp Timer Ctrl Reg */
2460 /* 0x0e19: reserved */
2461 #define GMAC_TI_ST_TST 0x0e1a /* 8 bit Time Stamp Timer Test Reg */
2462 - /* 0x0e1b - 0x0e7f: reserved */
2463 + /* 0x0e1b - 0x0e1f: reserved */
2465 +/* Polling Unit Registers (Yukon-2 only) */
2466 +#define POLL_CTRL 0x0e20 /* 32 bit Polling Unit Control Reg */
2467 +#define POLL_LAST_IDX 0x0e24 /* 16 bit Polling Unit List Last Index */
2468 + /* 0x0e26 - 0x0e27: reserved */
2469 +#define POLL_LIST_ADDR_LO 0x0e28 /* 32 bit Poll. List Start Addr (low) */
2470 +#define POLL_LIST_ADDR_HI 0x0e2c /* 32 bit Poll. List Start Addr (high) */
2471 + /* 0x0e30 - 0x0e3f: reserved */
2473 +/* ASF Subsystem Registers (Yukon-2 only) */
2474 +#define B28_Y2_SMB_CONFIG 0x0e40 /* 32 bit ASF SMBus Config Register */
2475 +#define B28_Y2_SMB_CSD_REG 0x0e44 /* 32 bit ASF SMB Control/Status/Data */
2476 + /* 0x0e48 - 0x0e5f: reserved */
2477 +#define B28_Y2_ASF_IRQ_V_BASE 0x0e60 /* 32 bit ASF IRQ Vector Base */
2478 + /* 0x0e64 - 0x0e67: reserved */
2479 +#define B28_Y2_ASF_STAT_CMD 0x0e68 /* 32 bit ASF Status and Command Reg */
2480 +#define B28_Y2_ASF_HOST_COM 0x0e6c /* 32 bit ASF Host Communication Reg */
2481 +#define B28_Y2_DATA_REG_1 0x0e70 /* 32 bit ASF/Host Data Register 1 */
2482 +#define B28_Y2_DATA_REG_2 0x0e74 /* 32 bit ASF/Host Data Register 2 */
2483 +#define B28_Y2_DATA_REG_3 0x0e78 /* 32 bit ASF/Host Data Register 3 */
2484 +#define B28_Y2_DATA_REG_4 0x0e7c /* 32 bit ASF/Host Data Register 4 */
2489 - /* 0x0e80 - 0x0efc: reserved */
2491 +/* Status BMU Registers (Yukon-2 only)*/
2492 +#define STAT_CTRL 0x0e80 /* 32 bit Status BMU Control Reg */
2493 +#define STAT_LAST_IDX 0x0e84 /* 16 bit Status BMU Last Index */
2494 + /* 0x0e85 - 0x0e86: reserved */
2495 +#define STAT_LIST_ADDR_LO 0x0e88 /* 32 bit Status List Start Addr (low) */
2496 +#define STAT_LIST_ADDR_HI 0x0e8c /* 32 bit Status List Start Addr (high) */
2497 +#define STAT_TXA1_RIDX 0x0e90 /* 16 bit Status TxA1 Report Index Reg */
2498 +#define STAT_TXS1_RIDX 0x0e92 /* 16 bit Status TxS1 Report Index Reg */
2499 +#define STAT_TXA2_RIDX 0x0e94 /* 16 bit Status TxA2 Report Index Reg */
2500 +#define STAT_TXS2_RIDX 0x0e96 /* 16 bit Status TxS2 Report Index Reg */
2501 +#define STAT_TX_IDX_TH 0x0e98 /* 16 bit Status Tx Index Threshold Reg */
2502 + /* 0x0e9a - 0x0e9b: reserved */
2503 +#define STAT_PUT_IDX 0x0e9c /* 16 bit Status Put Index Reg */
2504 + /* 0x0e9e - 0x0e9f: reserved */
2506 +/* FIFO Control/Status Registers (Yukon-2 only) */
2507 +#define STAT_FIFO_WP 0x0ea0 /* 8 bit Status FIFO Write Pointer Reg */
2508 + /* 0x0ea1 - 0x0ea3: reserved */
2509 +#define STAT_FIFO_RP 0x0ea4 /* 8 bit Status FIFO Read Pointer Reg */
2510 + /* 0x0ea5: reserved */
2511 +#define STAT_FIFO_RSP 0x0ea6 /* 8 bit Status FIFO Read Shadow Ptr */
2512 + /* 0x0ea7: reserved */
2513 +#define STAT_FIFO_LEVEL 0x0ea8 /* 8 bit Status FIFO Level Reg */
2514 + /* 0x0ea9: reserved */
2515 +#define STAT_FIFO_SHLVL 0x0eaa /* 8 bit Status FIFO Shadow Level Reg */
2516 + /* 0x0eab: reserved */
2517 +#define STAT_FIFO_WM 0x0eac /* 8 bit Status FIFO Watermark Reg */
2518 +#define STAT_FIFO_ISR_WM 0x0ead /* 8 bit Status FIFO ISR Watermark Reg */
2519 + /* 0x0eae - 0x0eaf: reserved */
2521 +/* Level and ISR Timer Registers (Yukon-2 only) */
2522 +#define STAT_LEV_TIMER_INI 0x0eb0 /* 32 bit Level Timer Init. Value Reg */
2523 +#define STAT_LEV_TIMER_CNT 0x0eb4 /* 32 bit Level Timer Counter Reg */
2524 +#define STAT_LEV_TIMER_CTRL 0x0eb8 /* 8 bit Level Timer Control Reg */
2525 +#define STAT_LEV_TIMER_TEST 0x0eb9 /* 8 bit Level Timer Test Reg */
2526 + /* 0x0eba - 0x0ebf: reserved */
2527 +#define STAT_TX_TIMER_INI 0x0ec0 /* 32 bit Tx Timer Init. Value Reg */
2528 +#define STAT_TX_TIMER_CNT 0x0ec4 /* 32 bit Tx Timer Counter Reg */
2529 +#define STAT_TX_TIMER_CTRL 0x0ec8 /* 8 bit Tx Timer Control Reg */
2530 +#define STAT_TX_TIMER_TEST 0x0ec9 /* 8 bit Tx Timer Test Reg */
2531 + /* 0x0eca - 0x0ecf: reserved */
2532 +#define STAT_ISR_TIMER_INI 0x0ed0 /* 32 bit ISR Timer Init. Value Reg */
2533 +#define STAT_ISR_TIMER_CNT 0x0ed4 /* 32 bit ISR Timer Counter Reg */
2534 +#define STAT_ISR_TIMER_CTRL 0x0ed8 /* 8 bit ISR Timer Control Reg */
2535 +#define STAT_ISR_TIMER_TEST 0x0ed9 /* 8 bit ISR Timer Test Reg */
2536 + /* 0x0eda - 0x0eff: reserved */
2538 +#define ST_LAST_IDX_MASK 0x007f /* Last Index Mask */
2539 +#define ST_TXRP_IDX_MASK 0x0fff /* Tx Report Index Mask */
2540 +#define ST_TXTH_IDX_MASK 0x0fff /* Tx Threshold Index Mask */
2541 +#define ST_WM_IDX_MASK 0x3f /* FIFO Watermark Index Mask */
2545 @@ -742,11 +1118,9 @@
2546 #define WOL_MATCH_RES 0x0f23 /* 8 bit WOL Match Result Reg */
2547 #define WOL_MAC_ADDR_LO 0x0f24 /* 32 bit WOL MAC Address Low */
2548 #define WOL_MAC_ADDR_HI 0x0f28 /* 16 bit WOL MAC Address High */
2549 -#define WOL_PATT_RPTR 0x0f2c /* 8 bit WOL Pattern Read Ptr */
2551 -/* use this macro to access above registers */
2552 -#define WOL_REG(Reg) ((Reg) + (pAC->GIni.GIWolOffs))
2554 +#define WOL_PATT_PME 0x0f2a /* 8 bit WOL PME Match Enable (Yukon-2) */
2555 +#define WOL_PATT_ASFM 0x0f2b /* 8 bit WOL ASF Match Enable (Yukon-2) */
2556 +#define WOL_PATT_RPTR 0x0f2c /* 8 bit WOL Pattern Read Pointer */
2558 /* WOL Pattern Length Registers (YUKON only) */
2560 @@ -764,11 +1138,22 @@
2562 /* 0x0f80 - 0x0fff: reserved */
2564 +/* WOL registers link 2 */
2566 +/* use this macro to access WOL registers */
2567 +#define WOL_REG(Port, Reg) ((Reg) + ((Port)*0x80) + (pAC->GIni.GIWolOffs))
2572 #define WOL_PATT_RAM_1 0x1000 /* WOL Pattern RAM Link 1 */
2573 +#define WOL_PATT_RAM_2 0x1400 /* WOL Pattern RAM Link 2 */
2575 +/* use this macro to retrieve the pattern ram base address */
2576 +#define WOL_PATT_RAM_BASE(Port) (WOL_PATT_RAM_1 + (Port)*0x400)
2578 +/* offset to configuration space on Yukon-2 */
2579 +#define Y2_CFG_SPC 0x1c00
2583 @@ -800,13 +1185,27 @@
2585 /* B0_RAP 8 bit Register Address Port */
2586 /* Bit 7: reserved */
2587 -#define RAP_RAP 0x3f /* Bit 6..0: 0 = block 0,..,6f = block 6f */
2588 +#define RAP_MSK 0x7f /* Bit 6..0: 0 = block 0,..,6f = block 6f */
2590 +/* B0_CTST 24 bit Control/Status register */
2591 + /* Bit 23..18: reserved */
2592 +#define Y2_VMAIN_AVAIL BIT_17 /* VMAIN available (YUKON-2 only) */
2593 +#define Y2_VAUX_AVAIL BIT_16 /* VAUX available (YUKON-2 only) */
2594 +#define Y2_HW_WOL_ON BIT_15S /* HW WOL On (Yukon-EC Ultra A1 only) */
2595 +#define Y2_HW_WOL_OFF BIT_14S /* HW WOL Off (Yukon-EC Ultra A1 only) */
2596 +#define Y2_ASF_ENABLE BIT_13S /* ASF Unit Enable (YUKON-2 only) */
2597 +#define Y2_ASF_DISABLE BIT_12S /* ASF Unit Disable (YUKON-2 only) */
2598 +#define Y2_CLK_RUN_ENA BIT_11S /* CLK_RUN Enable (YUKON-2 only) */
2599 +#define Y2_CLK_RUN_DIS BIT_10S /* CLK_RUN Disable (YUKON-2 only) */
2600 +#define Y2_LED_STAT_ON BIT_9S /* Status LED On (YUKON-2 only) */
2601 +#define Y2_LED_STAT_OFF BIT_8S /* Status LED Off (YUKON-2 only) */
2602 + /* Bit 7.. 0: same as below */
2604 /* B0_CTST 16 bit Control/Status register */
2605 /* Bit 15..14: reserved */
2606 -#define CS_CLK_RUN_HOT BIT_13S /* CLK_RUN hot m. (YUKON-Lite only) */
2607 -#define CS_CLK_RUN_RST BIT_12S /* CLK_RUN reset (YUKON-Lite only) */
2608 -#define CS_CLK_RUN_ENA BIT_11S /* CLK_RUN enable (YUKON-Lite only) */
2609 +#define CS_CLK_RUN_HOT BIT_13S /* CLK_RUN Hot m. (YUKON-Lite only) */
2610 +#define CS_CLK_RUN_RST BIT_12S /* CLK_RUN Reset (YUKON-Lite only) */
2611 +#define CS_CLK_RUN_ENA BIT_11S /* CLK_RUN Enable (YUKON-Lite only) */
2612 #define CS_VAUX_AVAIL BIT_10S /* VAUX available (YUKON only) */
2613 #define CS_BUS_CLOCK BIT_9S /* Bus Clock 0/1 = 33/66 MHz */
2614 #define CS_BUS_SLOT_SZ BIT_8S /* Slot Size 0/1 = 32/64 bit slot */
2615 @@ -814,26 +1213,27 @@
2616 #define CS_CL_SW_IRQ BIT_6S /* Clear IRQ SW Request */
2617 #define CS_STOP_DONE BIT_5S /* Stop Master is finished */
2618 #define CS_STOP_MAST BIT_4S /* Command Bit to stop the master */
2619 -#define CS_MRST_CLR BIT_3S /* Clear Master reset */
2620 -#define CS_MRST_SET BIT_2S /* Set Master reset */
2621 -#define CS_RST_CLR BIT_1S /* Clear Software reset */
2622 -#define CS_RST_SET BIT_0S /* Set Software reset */
2623 +#define CS_MRST_CLR BIT_3S /* Clear Master Reset */
2624 +#define CS_MRST_SET BIT_2S /* Set Master Reset */
2625 +#define CS_RST_CLR BIT_1S /* Clear Software Reset */
2626 +#define CS_RST_SET BIT_0S /* Set Software Reset */
2628 -/* B0_LED 8 Bit LED register */
2629 +/* B0_LED 8 Bit LED register (GENESIS only)*/
2630 /* Bit 7.. 2: reserved */
2631 -#define LED_STAT_ON BIT_1S /* Status LED on */
2632 -#define LED_STAT_OFF BIT_0S /* Status LED off */
2633 +#define LED_STAT_ON BIT_1S /* Status LED On */
2634 +#define LED_STAT_OFF BIT_0S /* Status LED Off */
2636 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
2637 #define PC_VAUX_ENA BIT_7 /* Switch VAUX Enable */
2638 -#define PC_VAUX_DIS BIT_6 /* Switch VAUX Disable */
2639 -#define PC_VCC_ENA BIT_5 /* Switch VCC Enable */
2640 -#define PC_VCC_DIS BIT_4 /* Switch VCC Disable */
2641 -#define PC_VAUX_ON BIT_3 /* Switch VAUX On */
2642 -#define PC_VAUX_OFF BIT_2 /* Switch VAUX Off */
2643 -#define PC_VCC_ON BIT_1 /* Switch VCC On */
2644 -#define PC_VCC_OFF BIT_0 /* Switch VCC Off */
2645 +#define PC_VAUX_DIS BIT_6 /* Switch VAUX Disable */
2646 +#define PC_VCC_ENA BIT_5 /* Switch VCC Enable */
2647 +#define PC_VCC_DIS BIT_4 /* Switch VCC Disable */
2648 +#define PC_VAUX_ON BIT_3 /* Switch VAUX On */
2649 +#define PC_VAUX_OFF BIT_2 /* Switch VAUX Off */
2650 +#define PC_VCC_ON BIT_1 /* Switch VCC On */
2651 +#define PC_VCC_OFF BIT_0 /* Switch VCC Off */
2653 +/* Yukon and Genesis */
2654 /* B0_ISRC 32 bit Interrupt Source Register */
2655 /* B0_IMSK 32 bit Interrupt Mask Register */
2656 /* B0_SP_ISRC 32 bit Special Interrupt Source Reg */
2657 @@ -879,12 +1279,58 @@
2658 #define IS_XA2_F BIT_1 /* Q_XA2 End of Frame */
2659 #define IS_XA2_C BIT_0 /* Q_XA2 Encoding Error */
2662 +/* B0_ISRC 32 bit Interrupt Source Register */
2663 +/* B0_IMSK 32 bit Interrupt Mask Register */
2664 +/* B0_SP_ISRC 32 bit Special Interrupt Source Reg */
2665 +/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
2666 +/* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */
2667 +/* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */
2668 +/* B0_Y2_SP_EISR 32 bit Enter ISR Reg */
2669 +/* B0_Y2_SP_LISR 32 bit Leave ISR Reg */
2670 +#define Y2_IS_PORT_MASK(Port, Mask) ((Mask) << (Port*8))
2671 +#define Y2_IS_HW_ERR BIT_31 /* Interrupt HW Error */
2672 +#define Y2_IS_STAT_BMU BIT_30 /* Status BMU Interrupt */
2673 +#define Y2_IS_ASF BIT_29 /* ASF subsystem Interrupt */
2674 + /* Bit 28: reserved */
2675 +#define Y2_IS_POLL_CHK BIT_27 /* Check IRQ from polling unit */
2676 +#define Y2_IS_TWSI_RDY BIT_26 /* IRQ on end of TWSI Tx */
2677 +#define Y2_IS_IRQ_SW BIT_25 /* SW forced IRQ */
2678 +#define Y2_IS_TIMINT BIT_24 /* IRQ from Timer */
2679 + /* Bit 23..16 reserved */
2680 + /* Link 2 Interrupts */
2681 +#define Y2_IS_IRQ_PHY2 BIT_12 /* Interrupt from PHY 2 */
2682 +#define Y2_IS_IRQ_MAC2 BIT_11 /* Interrupt from MAC 2 */
2683 +#define Y2_IS_CHK_RX2 BIT_10 /* Descriptor error Rx 2 */
2684 +#define Y2_IS_CHK_TXS2 BIT_9 /* Descriptor error TXS 2 */
2685 +#define Y2_IS_CHK_TXA2 BIT_8 /* Descriptor error TXA 2 */
2686 + /* Bit 7.. 5 reserved */
2687 + /* Link 1 interrupts */
2688 +#define Y2_IS_IRQ_PHY1 BIT_4 /* Interrupt from PHY 1 */
2689 +#define Y2_IS_IRQ_MAC1 BIT_3 /* Interrupt from MAC 1 */
2690 +#define Y2_IS_CHK_RX1 BIT_2 /* Descriptor error Rx 1 */
2691 +#define Y2_IS_CHK_TXS1 BIT_1 /* Descriptor error TXS 1 */
2692 +#define Y2_IS_CHK_TXA1 BIT_0 /* Descriptor error TXA 1 */
2694 +#define Y2_IS_L1_MASK 0x0000001fUL /* IRQ Mask for port 1 */
2696 +#define Y2_IS_L2_MASK 0x00001f00UL /* IRQ Mask for port 2 */
2698 +#define Y2_IS_ALL_MSK 0xef001f1fUL /* All Interrupt bits */
2700 +/* B0_Y2_SP_ICR 32 bit Interrupt Control Register */
2701 + /* Bit 31.. 4: reserved */
2702 +#define Y2_IC_ISR_MASK BIT_3 /* ISR mask flag */
2703 +#define Y2_IC_ISR_STAT BIT_2 /* ISR status flag */
2704 +#define Y2_IC_LEAVE_ISR BIT_1 /* Leave ISR */
2705 +#define Y2_IC_ENTER_ISR BIT_0 /* Enter ISR */
2707 +/* Yukon and Genesis */
2708 /* B0_HWE_ISRC 32 bit HW Error Interrupt Src Reg */
2709 /* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */
2710 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
2711 #define IS_ERR_MSK 0x00000fffL /* All Error bits */
2712 - /* Bit 31..14: reserved */
2713 + /* Bit 31..14: reserved */
2714 #define IS_IRQ_TIST_OV BIT_13 /* Time Stamp Timer Overflow (YUKON only) */
2715 #define IS_IRQ_SENSOR BIT_12 /* IRQ from Sensor (YUKON only) */
2716 #define IS_IRQ_MST_ERR BIT_11 /* IRQ master error detected */
2717 @@ -900,6 +1346,43 @@
2718 #define IS_R1_PAR_ERR BIT_1 /* Queue R1 Parity Error */
2719 #define IS_R2_PAR_ERR BIT_0 /* Queue R2 Parity Error */
2722 +/* B0_HWE_ISRC 32 bit HW Error Interrupt Src Reg */
2723 +/* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */
2724 +/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
2725 + /* Bit: 31..30 reserved */
2726 +#define Y2_IS_TIST_OV BIT_29 /* Time Stamp Timer overflow interrupt */
2727 +#define Y2_IS_SENSOR BIT_28 /* Sensor interrupt */
2728 +#define Y2_IS_MST_ERR BIT_27 /* Master error interrupt */
2729 +#define Y2_IS_IRQ_STAT BIT_26 /* Status exception interrupt */
2730 +#define Y2_IS_PCI_EXP BIT_25 /* PCI-Express interrupt */
2731 +#define Y2_IS_PCI_NEXP BIT_24 /* Bus Abort detected */
2732 + /* Bit: 23..14 reserved */
2734 +#define Y2_IS_PAR_RD2 BIT_13 /* Read RAM parity error interrupt */
2735 +#define Y2_IS_PAR_WR2 BIT_12 /* Write RAM parity error interrupt */
2736 +#define Y2_IS_PAR_MAC2 BIT_11 /* MAC hardware fault interrupt */
2737 +#define Y2_IS_PAR_RX2 BIT_10 /* Parity Error Rx Queue 2 */
2738 +#define Y2_IS_TCP_TXS2 BIT_9 /* TCP length mismatch sync Tx queue IRQ */
2739 +#define Y2_IS_TCP_TXA2 BIT_8 /* TCP length mismatch async Tx queue IRQ */
2740 + /* Bit: 9.. 6 reserved */
2742 +#define Y2_IS_PAR_RD1 BIT_5 /* Read RAM parity error interrupt */
2743 +#define Y2_IS_PAR_WR1 BIT_4 /* Write RAM parity error interrupt */
2744 +#define Y2_IS_PAR_MAC1 BIT_3 /* MAC hardware fault interrupt */
2745 +#define Y2_IS_PAR_RX1 BIT_2 /* Parity Error Rx Queue 1 */
2746 +#define Y2_IS_TCP_TXS1 BIT_1 /* TCP length mismatch sync Tx queue IRQ */
2747 +#define Y2_IS_TCP_TXA1 BIT_0 /* TCP length mismatch async Tx queue IRQ */
2749 +#define Y2_HWE_L1_MASK (Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |\
2750 + Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1)
2751 +#define Y2_HWE_L2_MASK (Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |\
2752 + Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2)
2754 +#define Y2_HWE_ALL_MSK (Y2_IS_TIST_OV | /* Y2_IS_SENSOR | */ Y2_IS_MST_ERR |\
2755 + Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP |\
2756 + Y2_HWE_L1_MASK | Y2_HWE_L2_MASK)
2758 /* B2_CONN_TYP 8 bit Connector type */
2759 /* B2_PMD_TYP 8 bit PMD type */
2760 /* Values of connector and PMD type comply to SysKonnect internal std */
2761 @@ -908,19 +1391,78 @@
2762 #define CFG_CHIP_R_MSK (0xf<<4) /* Bit 7.. 4: Chip Revision */
2763 /* Bit 3.. 2: reserved */
2764 #define CFG_DIS_M2_CLK BIT_1S /* Disable Clock for 2nd MAC */
2765 -#define CFG_SNG_MAC BIT_0S /* MAC Config: 0=2 MACs / 1=1 MAC*/
2766 +#define CFG_SNG_MAC BIT_0S /* MAC Config: 0 = 2 MACs; 1 = 1 MAC */
2768 -/* B2_CHIP_ID 8 bit Chip Identification Number */
2769 +/* B2_CHIP_ID 8 bit Chip Identification Number */
2770 #define CHIP_ID_GENESIS 0x0a /* Chip ID for GENESIS */
2771 #define CHIP_ID_YUKON 0xb0 /* Chip ID for YUKON */
2772 #define CHIP_ID_YUKON_LITE 0xb1 /* Chip ID for YUKON-Lite (Rev. A1-A3) */
2773 #define CHIP_ID_YUKON_LP 0xb2 /* Chip ID for YUKON-LP */
2774 +#define CHIP_ID_YUKON_XL 0xb3 /* Chip ID for YUKON-2 XL */
2775 +#define CHIP_ID_YUKON_EC_U 0xb4 /* Chip ID for YUKON-2 EC Ultra */
2776 +#define CHIP_ID_YUKON_EC 0xb6 /* Chip ID for YUKON-2 EC */
2777 +#define CHIP_ID_YUKON_FE 0xb7 /* Chip ID for YUKON-2 FE */
2779 #define CHIP_REV_YU_LITE_A1 3 /* Chip Rev. for YUKON-Lite A1,A2 */
2780 #define CHIP_REV_YU_LITE_A3 7 /* Chip Rev. for YUKON-Lite A3 */
2782 +#define CHIP_REV_YU_XL_A0 0 /* Chip Rev. for Yukon-2 A0 */
2783 +#define CHIP_REV_YU_XL_A1 1 /* Chip Rev. for Yukon-2 A1 */
2784 +#define CHIP_REV_YU_XL_A2 2 /* Chip Rev. for Yukon-2 A2 */
2785 +#define CHIP_REV_YU_XL_A3 3 /* Chip Rev. for Yukon-2 A3 */
2787 +#define CHIP_REV_YU_EC_A1 0 /* Chip Rev. for Yukon-EC A0,A1 */
2788 +#define CHIP_REV_YU_EC_A2 1 /* Chip Rev. for Yukon-EC A2 */
2789 +#define CHIP_REV_YU_EC_A3 2 /* Chip Rev. for Yukon-EC A3 */
2791 +#define CHIP_REV_YU_EC_U_A0 1 /* Chip Rev. for Yukon-EC Ultra A0 */
2792 +#define CHIP_REV_YU_EC_U_A1 2 /* Chip Rev. for Yukon-EC Ultra A1 */
2794 +#define CHIP_REV_YU_FE_A1 1 /* Chip Rev. for Yukon-FE A1 */
2795 +#define CHIP_REV_YU_FE_A2 3 /* Chip Rev. for Yukon-FE A2 */
2797 +/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
2798 +#define Y2_STATUS_LNK2_INAC BIT_7S /* Status Link 2 inactiv (0 = activ) */
2799 +#define Y2_CLK_GAT_LNK2_DIS BIT_6S /* Disable PHY clock for Link 2 */
2800 +#define Y2_COR_CLK_LNK2_DIS BIT_5S /* Disable Core clock Link 2 */
2801 +#define Y2_PCI_CLK_LNK2_DIS BIT_4S /* Disable PCI clock Link 2 */
2802 +#define Y2_STATUS_LNK1_INAC BIT_3S /* Status Link 1 inactiv (0 = activ) */
2803 +#define Y2_CLK_GAT_LNK1_DIS BIT_2S /* Disable PHY clock for Link 1 */
2804 +#define Y2_COR_CLK_LNK1_DIS BIT_1S /* Disable Core clock Link 1 */
2805 +#define Y2_PCI_CLK_LNK1_DIS BIT_0S /* Disable PCI clock Link 1 */
2807 +/* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
2808 + /* Bit 7.. 6: reserved */
2809 +#define CFG_PEX_PME_NATIVE BIT_5S /* PCI-E PME native mode select */
2810 +#define CFG_LED_MODE_MSK (7<<2) /* Bit 4.. 2: LED Mode Mask */
2811 +#define CFG_LINK_2_AVAIL BIT_1S /* Link 2 available */
2812 +#define CFG_LINK_1_AVAIL BIT_0S /* Link 1 available */
2814 +#define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2)
2815 +#define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)
2817 +#define CFG_LED_DUAL_ACT_LNK 1 /* Dual LED ACT/LNK mode */
2818 +#define CFG_LED_LINK_MUX_P60 2 /* Link LED on pin 60 (Yukon-EC Ultra) */
2820 +/* B2_E_3 8 bit lower 4 bits used for HW self test result */
2821 +#define B2_E3_RES_MASK 0x0f
2823 /* B2_FAR 32 bit Flash-Prom Addr Reg/Cnt */
2824 -#define FAR_ADDR 0x1ffffL /* Bit 16.. 0: FPROM Address mask */
2825 +#define FAR_ADDR 0x1ffffL /* Bit 16.. 0: FPROM Address Mask */
2827 +/* B2_Y2_CLK_CTRL 32 bit Core Clock Frequency Control Register (Yukon-2/EC) */
2828 + /* Bit 31..24: reserved */
2830 +#define Y2_CLK_DIV_VAL_MSK (0xffL<<16) /* Bit 23..16: Clock Divisor Value */
2831 +#define Y2_CLK_DIV_VAL(x) (SHIFT16(x) & Y2_CLK_DIV_VAL_MSK)
2833 +#define Y2_CLK_DIV_VAL2_MSK (7L<<21) /* Bit 23..21: Clock Divisor Value */
2834 +#define Y2_CLK_SELECT2_MSK (0x1fL<<16) /* Bit 20..16: Clock Select */
2835 +#define Y2_CLK_DIV_VAL_2(x) (SHIFT21(x) & Y2_CLK_DIV_VAL2_MSK)
2836 +#define Y2_CLK_SEL_VAL_2(x) (SHIFT16(x) & Y2_CLK_SELECT2_MSK)
2837 + /* Bit 15.. 2: reserved */
2838 +#define Y2_CLK_DIV_ENA BIT_1S /* Enable Core Clock Division */
2839 +#define Y2_CLK_DIV_DIS BIT_0S /* Disable Core Clock Division */
2841 /* B2_LD_CTRL 8 bit EPROM loader control register */
2842 /* Bits are currently reserved */
2843 @@ -960,9 +1502,6 @@
2844 #define DPT_START BIT_1S /* Start Descriptor Poll Timer */
2845 #define DPT_STOP BIT_0S /* Stop Descriptor Poll Timer */
2847 -/* B2_E_3 8 bit lower 4 bits used for HW self test result */
2848 -#define B2_E3_RES_MASK 0x0f
2850 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
2851 #define TST_FRC_DPERR_MR BIT_7S /* force DATAPERR on MST RD */
2852 #define TST_FRC_DPERR_MW BIT_6S /* force DATAPERR on MST WR */
2853 @@ -975,14 +1514,14 @@
2855 /* B2_TST_CTRL2 8 bit Test Control Register 2 */
2856 /* Bit 7.. 4: reserved */
2857 - /* force the following error on the next master read/write */
2858 + /* force the following error on the next master read/write */
2859 #define TST_FRC_DPERR_MR64 BIT_3S /* DataPERR RD 64 */
2860 #define TST_FRC_DPERR_MW64 BIT_2S /* DataPERR WR 64 */
2861 #define TST_FRC_APERR_1M64 BIT_1S /* AddrPERR on 1. phase */
2862 #define TST_FRC_APERR_2M64 BIT_0S /* AddrPERR on 2. phase */
2864 /* B2_GP_IO 32 bit General Purpose I/O Register */
2865 - /* Bit 31..26: reserved */
2866 + /* Bit 31..26: reserved */
2867 #define GP_DIR_9 BIT_25 /* IO_9 direct, 0=In/1=Out */
2868 #define GP_DIR_8 BIT_24 /* IO_8 direct, 0=In/1=Out */
2869 #define GP_DIR_7 BIT_23 /* IO_7 direct, 0=In/1=Out */
2870 @@ -1009,15 +1548,15 @@
2871 #define I2C_FLAG BIT_31 /* Start read/write if WR */
2872 #define I2C_ADDR (0x7fffL<<16) /* Bit 30..16: Addr to be RD/WR */
2873 #define I2C_DEV_SEL (0x7fL<<9) /* Bit 15.. 9: I2C Device Select */
2874 - /* Bit 8.. 5: reserved */
2875 + /* Bit 8.. 5: reserved */
2876 #define I2C_BURST_LEN BIT_4 /* Burst Len, 1/4 bytes */
2877 -#define I2C_DEV_SIZE (7<<1) /* Bit 3.. 1: I2C Device Size */
2878 -#define I2C_025K_DEV (0<<1) /* 0: 256 Bytes or smal. */
2879 -#define I2C_05K_DEV (1<<1) /* 1: 512 Bytes */
2880 -#define I2C_1K_DEV (2<<1) /* 2: 1024 Bytes */
2881 -#define I2C_2K_DEV (3<<1) /* 3: 2048 Bytes */
2882 -#define I2C_4K_DEV (4<<1) /* 4: 4096 Bytes */
2883 -#define I2C_8K_DEV (5<<1) /* 5: 8192 Bytes */
2884 +#define I2C_DEV_SIZE (7<<1) /* Bit 3.. 1: I2C Device Size */
2885 +#define I2C_025K_DEV (0<<1) /* 0: 256 Bytes or smaller */
2886 +#define I2C_05K_DEV (1<<1) /* 1: 512 Bytes */
2887 +#define I2C_1K_DEV (2<<1) /* 2: 1024 Bytes */
2888 +#define I2C_2K_DEV (3<<1) /* 3: 2048 Bytes */
2889 +#define I2C_4K_DEV (4<<1) /* 4: 4096 Bytes */
2890 +#define I2C_8K_DEV (5<<1) /* 5: 8192 Bytes */
2891 #define I2C_16K_DEV (6<<1) /* 6: 16384 Bytes */
2892 #define I2C_32K_DEV (7<<1) /* 7: 32768 Bytes */
2893 #define I2C_STOP BIT_0 /* Interrupt I2C transfer */
2894 @@ -1026,16 +1565,14 @@
2895 /* Bit 31.. 1 reserved */
2896 #define I2C_CLR_IRQ BIT_0 /* Clear I2C IRQ */
2898 -/* B2_I2C_SW 32 bit (8 bit access) I2C HW SW Port Register */
2899 +/* B2_I2C_SW 32 bit (8 bit access) I2C SW Port Register */
2900 /* Bit 7.. 3: reserved */
2901 #define I2C_DATA_DIR BIT_2S /* direction of I2C_DATA */
2902 -#define I2C_DATA BIT_1S /* I2C Data Port */
2903 -#define I2C_CLK BIT_0S /* I2C Clock Port */
2904 +#define I2C_DATA BIT_1S /* I2C Data Port */
2905 +#define I2C_CLK BIT_0S /* I2C Clock Port */
2910 -#define I2C_SENS_ADDR LM80_ADDR /* I2C Sensor Address, (Volt and Temp)*/
2912 +#define I2C_SENS_ADDR LM80_ADDR /* I2C Sensor Address (Volt and Temp) */
2915 /* B2_BSC_CTRL 8 bit Blink Source Counter Control */
2916 @@ -1052,16 +1589,20 @@
2917 #define BSC_T_OFF BIT_1S /* Test mode off */
2918 #define BSC_T_STEP BIT_0S /* Test step */
2920 +/* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */
2921 +#define PEX_RD_ACCESS BIT_31 /* Access Mode Read = 1, Write = 0 */
2922 +#define PEX_DB_ACCESS BIT_30 /* Access to debug register */
2925 /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
2926 /* Bit 31..19: reserved */
2927 #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
2929 /* RAM Interface Registers */
2930 -/* B3_RI_CTRL 16 bit RAM Iface Control Register */
2931 +/* B3_RI_CTRL 16 bit RAM Interface Control Register */
2932 /* Bit 15..10: reserved */
2933 -#define RI_CLR_RD_PERR BIT_9S /* Clear IRQ RAM Read Parity Err */
2934 -#define RI_CLR_WR_PERR BIT_8S /* Clear IRQ RAM Write Parity Err*/
2935 +#define RI_CLR_RD_PERR BIT_9S /* Clear IRQ RAM Read Parity Err */
2936 +#define RI_CLR_WR_PERR BIT_8S /* Clear IRQ RAM Write Parity Err */
2937 /* Bit 7.. 2: reserved */
2938 #define RI_RST_CLR BIT_1S /* Clear RAM Interface Reset */
2939 #define RI_RST_SET BIT_0S /* Set RAM Interface Reset */
2940 @@ -1171,7 +1712,7 @@
2941 /* Bit 31..16: reserved */
2942 #define BC_MAX 0xffff /* Bit 15.. 0: Byte counter */
2944 -/* BMU Control Status Registers */
2945 +/* BMU Control / Status Registers (Yukon and Genesis) */
2946 /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
2947 /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
2948 /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
2949 @@ -1212,13 +1753,48 @@
2950 CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\
2953 +/* Rx BMU Control / Status Registers (Yukon-2) */
2954 +#define BMU_IDLE BIT_31 /* BMU Idle State */
2955 +#define BMU_RX_TCP_PKT BIT_30 /* Rx TCP Packet (when RSS Hash enabled) */
2956 +#define BMU_RX_IP_PKT BIT_29 /* Rx IP Packet (when RSS Hash enabled) */
2957 + /* Bit 28..16: reserved */
2958 +#define BMU_ENA_RX_RSS_HASH BIT_15 /* Enable Rx RSS Hash */
2959 +#define BMU_DIS_RX_RSS_HASH BIT_14 /* Disable Rx RSS Hash */
2960 +#define BMU_ENA_RX_CHKSUM BIT_13 /* Enable Rx TCP/IP Checksum Check */
2961 +#define BMU_DIS_RX_CHKSUM BIT_12 /* Disable Rx TCP/IP Checksum Check */
2962 +#define BMU_CLR_IRQ_PAR BIT_11 /* Clear IRQ on Parity errors (Rx) */
2963 +#define BMU_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segmen. error (Tx) */
2964 +#define BMU_CLR_IRQ_CHK BIT_10 /* Clear IRQ Check */
2965 +#define BMU_STOP BIT_9 /* Stop Rx/Tx Queue */
2966 +#define BMU_START BIT_8 /* Start Rx/Tx Queue */
2967 +#define BMU_FIFO_OP_ON BIT_7 /* FIFO Operational On */
2968 +#define BMU_FIFO_OP_OFF BIT_6 /* FIFO Operational Off */
2969 +#define BMU_FIFO_ENA BIT_5 /* Enable FIFO */
2970 +#define BMU_FIFO_RST BIT_4 /* Reset FIFO */
2971 +#define BMU_OP_ON BIT_3 /* BMU Operational On */
2972 +#define BMU_OP_OFF BIT_2 /* BMU Operational Off */
2973 +#define BMU_RST_CLR BIT_1 /* Clear BMU Reset (Enable) */
2974 +#define BMU_RST_SET BIT_0 /* Set BMU Reset */
2976 +#define BMU_CLR_RESET (BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR)
2977 +#define BMU_OPER_INIT (BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START | \
2978 + BMU_FIFO_ENA | BMU_OP_ON)
2980 +/* Tx BMU Control / Status Registers (Yukon-2) */
2981 + /* Bit 31: same as for Rx */
2982 + /* Bit 30..14: reserved */
2983 +#define BMU_TX_IPIDINCR_ON BIT_13 /* Enable IP ID Increment */
2984 +#define BMU_TX_IPIDINCR_OFF BIT_12 /* Disable IP ID Increment */
2985 +#define BMU_TX_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segm. length mism. */
2986 + /* Bit 10..0: same as for Rx */
2988 /* Q_F 32 bit Flag Register */
2989 /* Bit 31..28: reserved */
2990 #define F_ALM_FULL BIT_27 /* Rx FIFO: almost full */
2991 #define F_EMPTY BIT_27 /* Tx FIFO: empty flag */
2992 #define F_FIFO_EOF BIT_26 /* Tag (EOF Flag) bit in FIFO */
2993 #define F_WM_REACHED BIT_25 /* Watermark reached */
2995 +#define F_M_RX_RAM_DIS BIT_24 /* MAC Rx RAM Read Port disable */
2996 #define F_FIFO_LEVEL (0x1fL<<16) /* Bit 23..16: # of Qwords in FIFO */
2997 /* Bit 15..11: reserved */
2998 #define F_WATER_MARK 0x0007ffL /* Bit 10.. 0: Watermark */
2999 @@ -1260,6 +1836,13 @@
3000 /* Bit 3: reserved */
3001 #define T3_VRAM_MSK 7 /* Bit 2.. 0: Virtual RAM Buffer Address */
3003 +/* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/
3004 +/* PREF_UNIT_CTRL_REG 32 bit Prefetch Control register */
3005 +#define PREF_UNIT_OP_ON BIT_3 /* prefetch unit operational */
3006 +#define PREF_UNIT_OP_OFF BIT_2 /* prefetch unit not operational */
3007 +#define PREF_UNIT_RST_CLR BIT_1 /* Clear Prefetch Unit Reset */
3008 +#define PREF_UNIT_RST_SET BIT_0 /* Set Prefetch Unit Reset */
3010 /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
3011 /* RB_START 32 bit RAM Buffer Start Address */
3012 /* RB_END 32 bit RAM Buffer End Address */
3013 @@ -1275,24 +1858,24 @@
3014 #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
3016 /* RB_TST2 8 bit RAM Buffer Test Register 2 */
3017 - /* Bit 7.. 4: reserved */
3018 -#define RB_PC_DEC BIT_3S /* Packet Counter Decrem */
3019 + /* Bit 7.. 4: reserved */
3020 +#define RB_PC_DEC BIT_3S /* Packet Counter Decrement */
3021 #define RB_PC_T_ON BIT_2S /* Packet Counter Test On */
3022 -#define RB_PC_T_OFF BIT_1S /* Packet Counter Tst Off */
3023 -#define RB_PC_INC BIT_0S /* Packet Counter Increm */
3024 +#define RB_PC_T_OFF BIT_1S /* Packet Counter Test Off */
3025 +#define RB_PC_INC BIT_0S /* Packet Counter Increment */
3027 /* RB_TST1 8 bit RAM Buffer Test Register 1 */
3028 /* Bit 7: reserved */
3029 #define RB_WP_T_ON BIT_6S /* Write Pointer Test On */
3030 #define RB_WP_T_OFF BIT_5S /* Write Pointer Test Off */
3031 -#define RB_WP_INC BIT_4S /* Write Pointer Increm */
3032 +#define RB_WP_INC BIT_4S /* Write Pointer Increment */
3033 /* Bit 3: reserved */
3034 #define RB_RP_T_ON BIT_2S /* Read Pointer Test On */
3035 #define RB_RP_T_OFF BIT_1S /* Read Pointer Test Off */
3036 -#define RB_RP_DEC BIT_0S /* Read Pointer Decrement */
3037 +#define RB_RP_INC BIT_0S /* Read Pointer Increment */
3039 /* RB_CTRL 8 bit RAM Buffer Control Register */
3040 - /* Bit 7.. 6: reserved */
3041 + /* Bit 7.. 6: reserved */
3042 #define RB_ENA_STFWD BIT_5S /* Enable Store & Forward */
3043 #define RB_DIS_STFWD BIT_4S /* Disable Store & Forward */
3044 #define RB_ENA_OP_MD BIT_3S /* Enable Operation Mode */
3045 @@ -1300,16 +1883,31 @@
3046 #define RB_RST_CLR BIT_1S /* Clear RAM Buf STM Reset */
3047 #define RB_RST_SET BIT_0S /* Set RAM Buf STM Reset */
3050 + /* Bit 31..20: reserved */
3051 +#define RB_CNT_DOWN BIT_19 /* Packet Counter Decrement */
3052 +#define RB_CNT_TST_ON BIT_18 /* Packet Counter Test On */
3053 +#define RB_CNT_TST_OFF BIT_17 /* Packet Counter Test Off */
3054 +#define RB_CNT_UP BIT_16 /* Packet Counter Increment */
3055 + /* Bit 15: reserved */
3056 +#define RB_WP_TST_ON BIT_14 /* Write Pointer Test On */
3057 +#define RB_WP_TST_OFF BIT_13 /* Write Pointer Test Off */
3058 +#define RB_WP_UP BIT_12 /* Write Pointer Increment */
3059 + /* Bit 11: reserved */
3060 +#define RB_RP_TST_ON BIT_10 /* Read Pointer Test On */
3061 +#define RB_RP_TST_OFF BIT_9 /* Read Pointer Test Off */
3062 +#define RB_RP_UP BIT_8 /* Read Pointer Increment */
3065 /* Receive and Transmit MAC FIFO Registers (GENESIS only) */
3067 /* RX_MFF_EA 32 bit Receive MAC FIFO End Address */
3068 -/* RX_MFF_WP 32 bit Receive MAC FIFO Write Pointer */
3069 +/* RX_MFF_WP 32 bit Receive MAC FIFO Write Pointer */
3070 /* RX_MFF_RP 32 bit Receive MAC FIFO Read Pointer */
3071 /* RX_MFF_PC 32 bit Receive MAC FIFO Packet Counter */
3072 /* RX_MFF_LEV 32 bit Receive MAC FIFO Level */
3073 /* TX_MFF_EA 32 bit Transmit MAC FIFO End Address */
3074 -/* TX_MFF_WP 32 bit Transmit MAC FIFO Write Pointer */
3075 +/* TX_MFF_WP 32 bit Transmit MAC FIFO Write Pointer */
3076 /* TX_MFF_WSP 32 bit Transmit MAC FIFO WR Shadow Pointer */
3077 /* TX_MFF_RP 32 bit Transmit MAC FIFO Read Pointer */
3078 /* TX_MFF_PC 32 bit Transmit MAC FIFO Packet Cnt */
3079 @@ -1359,9 +1957,9 @@
3080 /* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */
3081 /* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */
3082 /* Bit 7: reserved */
3083 -#define MFF_WSP_T_ON BIT_6S /* Tx: Write Shadow Ptr TestOn */
3084 -#define MFF_WSP_T_OFF BIT_5S /* Tx: Write Shadow Ptr TstOff */
3085 -#define MFF_WSP_INC BIT_4S /* Tx: Write Shadow Ptr Increment */
3086 +#define MFF_WSP_T_ON BIT_6S /* Tx: Write Shadow Pointer Test On */
3087 +#define MFF_WSP_T_OFF BIT_5S /* Tx: Write Shadow Pointer Test Off */
3088 +#define MFF_WSP_INC BIT_4S /* Tx: Write Shadow Pointer Increment */
3089 #define MFF_PC_DEC BIT_3S /* Packet Counter Decrement */
3090 #define MFF_PC_T_ON BIT_2S /* Packet Counter Test On */
3091 #define MFF_PC_T_OFF BIT_1S /* Packet Counter Test Off */
3092 @@ -1372,7 +1970,7 @@
3093 /* Bit 7: reserved */
3094 #define MFF_WP_T_ON BIT_6S /* Write Pointer Test On */
3095 #define MFF_WP_T_OFF BIT_5S /* Write Pointer Test Off */
3096 -#define MFF_WP_INC BIT_4S /* Write Pointer Increm */
3097 +#define MFF_WP_INC BIT_4S /* Write Pointer Increment */
3098 /* Bit 3: reserved */
3099 #define MFF_RP_T_ON BIT_2S /* Read Pointer Test On */
3100 #define MFF_RP_T_OFF BIT_1S /* Read Pointer Test Off */
3101 @@ -1391,12 +1989,16 @@
3103 /* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */
3104 /* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */
3105 + /* Bit 7.. 3: reserved */
3106 +#define LED_START BIT_2S /* Start Counter */
3107 +#define LED_STOP BIT_1S /* Stop Counter */
3108 +#define LED_STATE BIT_0S /* Rx/Tx: LED State, 1=LED On */
3110 /* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */
3111 /* Bit 7.. 3: reserved */
3112 -#define LED_START BIT_2S /* Start Timer */
3113 -#define LED_STOP BIT_1S /* Stop Timer */
3114 -#define LED_STATE BIT_0S /* Rx/Tx: LED State, 1=LED on */
3115 -#define LED_CLR_IRQ BIT_0S /* Lnk: Clear Link IRQ */
3116 +#define LNK_START BIT_2S /* Start Counter */
3117 +#define LNK_STOP BIT_1S /* Stop Counter */
3118 +#define LNK_CLR_IRQ BIT_0S /* Clear Link IRQ */
3120 /* RX_LED_TST 8 bit Receive LED Cnt Test Register */
3121 /* TX_LED_TST 8 bit Transmit LED Cnt Test Register */
3122 @@ -1407,86 +2009,142 @@
3123 #define LED_T_STEP BIT_0S /* LED Counter Step */
3125 /* LNK_LED_REG 8 bit Link LED Register */
3126 - /* Bit 7.. 6: reserved */
3127 + /* Bit 7.. 6: reserved */
3128 #define LED_BLK_ON BIT_5S /* Link LED Blinking On */
3129 #define LED_BLK_OFF BIT_4S /* Link LED Blinking Off */
3130 #define LED_SYNC_ON BIT_3S /* Use Sync Wire to switch LED */
3131 #define LED_SYNC_OFF BIT_2S /* Disable Sync Wire Input */
3132 -#define LED_ON BIT_1S /* switch LED on */
3133 -#define LED_OFF BIT_0S /* switch LED off */
3134 +#define LED_ON BIT_1S /* Switch LED On */
3135 +#define LED_OFF BIT_0S /* Switch LED Off */
3137 /* Receive and Transmit GMAC FIFO Registers (YUKON only) */
3139 /* RX_GMF_EA 32 bit Rx GMAC FIFO End Address */
3140 /* RX_GMF_AF_THR 32 bit Rx GMAC FIFO Almost Full Thresh. */
3141 -/* RX_GMF_WP 32 bit Rx GMAC FIFO Write Pointer */
3142 -/* RX_GMF_WLEV 32 bit Rx GMAC FIFO Write Level */
3143 -/* RX_GMF_RP 32 bit Rx GMAC FIFO Read Pointer */
3144 -/* RX_GMF_RLEV 32 bit Rx GMAC FIFO Read Level */
3145 +/* RX_GMF_WP 32 bit Rx GMAC FIFO Write Pointer */
3146 +/* RX_GMF_WLEV 32 bit Rx GMAC FIFO Write Level */
3147 +/* RX_GMF_RP 32 bit Rx GMAC FIFO Read Pointer */
3148 +/* RX_GMF_RLEV 32 bit Rx GMAC FIFO Read Level */
3149 /* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */
3150 /* TX_GMF_AE_THR 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
3151 -/* TX_GMF_WP 32 bit Tx GMAC FIFO Write Pointer */
3152 -/* TX_GMF_WSP 32 bit Tx GMAC FIFO Write Shadow Ptr. */
3153 -/* TX_GMF_WLEV 32 bit Tx GMAC FIFO Write Level */
3154 -/* TX_GMF_RP 32 bit Tx GMAC FIFO Read Pointer */
3155 -/* TX_GMF_RSTP 32 bit Tx GMAC FIFO Restart Pointer */
3156 -/* TX_GMF_RLEV 32 bit Tx GMAC FIFO Read Level */
3157 +/* TX_GMF_WP 32 bit Tx GMAC FIFO Write Pointer */
3158 +/* TX_GMF_WSP 32 bit Tx GMAC FIFO Write Shadow Pointer */
3159 +/* TX_GMF_WLEV 32 bit Tx GMAC FIFO Write Level */
3160 +/* TX_GMF_RP 32 bit Tx GMAC FIFO Read Pointer */
3161 +/* TX_GMF_RSTP 32 bit Tx GMAC FIFO Restart Pointer */
3162 +/* TX_GMF_RLEV 32 bit Tx GMAC FIFO Read Level */
3164 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
3165 - /* Bits 31..15: reserved */
3166 -#define GMF_WP_TST_ON BIT_14 /* Write Pointer Test On */
3167 -#define GMF_WP_TST_OFF BIT_13 /* Write Pointer Test Off */
3168 -#define GMF_WP_STEP BIT_12 /* Write Pointer Step/Increment */
3169 + /* Bit 31..28 reserved */
3170 +#define RX_TRUNC_ON BIT_27 /* Enable Packet Truncation */
3171 +#define RX_TRUNC_OFF BIT_26 /* Disable Packet Truncation */
3172 +#define RX_VLAN_STRIP_ON BIT_25 /* Enable VLAN Stripping */
3173 +#define RX_VLAN_STRIP_OFF BIT_24 /* Disable VLAN Stripping */
3174 + /* Bit 23..15 reserved */
3175 +#define GMF_WP_TST_ON BIT_14 /* Write Pointer Test On */
3176 +#define GMF_WP_TST_OFF BIT_13 /* Write Pointer Test Off */
3177 +#define GMF_WP_STEP BIT_12 /* Write Pointer Step/Increment */
3178 /* Bit 11: reserved */
3179 -#define GMF_RP_TST_ON BIT_10 /* Read Pointer Test On */
3180 -#define GMF_RP_TST_OFF BIT_9 /* Read Pointer Test Off */
3181 -#define GMF_RP_STEP BIT_8 /* Read Pointer Step/Increment */
3182 -#define GMF_RX_F_FL_ON BIT_7 /* Rx FIFO Flush Mode On */
3183 -#define GMF_RX_F_FL_OFF BIT_6 /* Rx FIFO Flush Mode Off */
3184 -#define GMF_CLI_RX_FO BIT_5 /* Clear IRQ Rx FIFO Overrun */
3185 -#define GMF_CLI_RX_FC BIT_4 /* Clear IRQ Rx Frame Complete */
3186 -#define GMF_OPER_ON BIT_3 /* Operational Mode On */
3187 -#define GMF_OPER_OFF BIT_2 /* Operational Mode Off */
3188 -#define GMF_RST_CLR BIT_1 /* Clear GMAC FIFO Reset */
3189 -#define GMF_RST_SET BIT_0 /* Set GMAC FIFO Reset */
3191 -/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
3192 - /* Bits 31..19: reserved */
3193 -#define GMF_WSP_TST_ON BIT_18 /* Write Shadow Pointer Test On */
3194 -#define GMF_WSP_TST_OFF BIT_17 /* Write Shadow Pointer Test Off */
3195 -#define GMF_WSP_STEP BIT_16 /* Write Shadow Pointer Step/Increment */
3196 - /* Bits 15..7: same as for RX_GMF_CTRL_T */
3197 -#define GMF_CLI_TX_FU BIT_6 /* Clear IRQ Tx FIFO Underrun */
3198 -#define GMF_CLI_TX_FC BIT_5 /* Clear IRQ Tx Frame Complete */
3199 -#define GMF_CLI_TX_PE BIT_4 /* Clear IRQ Tx Parity Error */
3200 +#define GMF_RP_TST_ON BIT_10 /* Read Pointer Test On */
3201 +#define GMF_RP_TST_OFF BIT_9 /* Read Pointer Test Off */
3202 +#define GMF_RP_STEP BIT_8 /* Read Pointer Step/Increment */
3203 +#define GMF_RX_F_FL_ON BIT_7 /* Rx FIFO Flush Mode On */
3204 +#define GMF_RX_F_FL_OFF BIT_6 /* Rx FIFO Flush Mode Off */
3205 +#define GMF_CLI_RX_FO BIT_5 /* Clear IRQ Rx FIFO Overrun */
3206 +#define GMF_CLI_RX_FC BIT_4 /* Clear IRQ Rx Frame Complete */
3207 +#define GMF_OPER_ON BIT_3 /* Operational Mode On */
3208 +#define GMF_OPER_OFF BIT_2 /* Operational Mode Off */
3209 +#define GMF_RST_CLR BIT_1 /* Clear GMAC FIFO Reset */
3210 +#define GMF_RST_SET BIT_0 /* Set GMAC FIFO Reset */
3212 +/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test (YUKON and Yukon-2) */
3213 +#define TX_STFW_DIS BIT_31 /* Disable Store & Forward (Yukon-EC Ultra) */
3214 +#define TX_STFW_ENA BIT_30 /* Enable Store & Forward (Yukon-EC Ultra) */
3215 + /* Bits 29..26: reserved */
3216 +#define TX_VLAN_TAG_ON BIT_25 /* Enable VLAN tagging */
3217 +#define TX_VLAN_TAG_OFF BIT_24 /* Disable VLAN tagging */
3218 +#define TX_PCI_JUM_ENA BIT_23 /* Enable PCI Jumbo Mode (Yukon-EC Ultra) */
3219 +#define TX_PCI_JUM_DIS BIT_22 /* Disable PCI Jumbo Mode (Yukon-EC Ultra) */
3220 + /* Bits 21..19: reserved */
3221 +#define GMF_WSP_TST_ON BIT_18 /* Write Shadow Pointer Test On */
3222 +#define GMF_WSP_TST_OFF BIT_17 /* Write Shadow Pointer Test Off */
3223 +#define GMF_WSP_STEP BIT_16 /* Write Shadow Pointer Step/Increment */
3224 + /* Bits 15..8: same as for RX_GMF_CTRL_T */
3225 + /* Bit 7: reserved */
3226 +#define GMF_CLI_TX_FU BIT_6 /* Clear IRQ Tx FIFO Underrun */
3227 +#define GMF_CLI_TX_FC BIT_5 /* Clear IRQ Tx Frame Complete */
3228 +#define GMF_CLI_TX_PE BIT_4 /* Clear IRQ Tx Parity Error */
3229 /* Bits 3..0: same as for RX_GMF_CTRL_T */
3231 #define GMF_RX_CTRL_DEF (GMF_OPER_ON | GMF_RX_F_FL_ON)
3232 #define GMF_TX_CTRL_DEF GMF_OPER_ON
3234 +#define RX_GMF_AF_THR_MIN 0x0c /* Rx GMAC FIFO Almost Full Thresh. min. */
3235 #define RX_GMF_FL_THR_DEF 0x0a /* Rx GMAC FIFO Flush Threshold default */
3237 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
3238 - /* Bit 7.. 3: reserved */
3239 -#define GMT_ST_START BIT_2S /* Start Time Stamp Timer */
3240 -#define GMT_ST_STOP BIT_1S /* Stop Time Stamp Timer */
3241 -#define GMT_ST_CLR_IRQ BIT_0S /* Clear Time Stamp Timer IRQ */
3243 + /* Bit 7.. 3: reserved */
3244 +#define GMT_ST_START BIT_2S /* Start Time Stamp Timer */
3245 +#define GMT_ST_STOP BIT_1S /* Stop Time Stamp Timer */
3246 +#define GMT_ST_CLR_IRQ BIT_0S /* Clear Time Stamp Timer IRQ */
3248 +/* POLL_CTRL 32 bit Polling Unit control register (Yukon-2 only) */
3249 + /* Bit 31.. 6: reserved */
3250 +#define PC_CLR_IRQ_CHK BIT_5 /* Clear IRQ Check */
3251 +#define PC_POLL_RQ BIT_4 /* Poll Request Start */
3252 +#define PC_POLL_OP_ON BIT_3 /* Operational Mode On */
3253 +#define PC_POLL_OP_OFF BIT_2 /* Operational Mode Off */
3254 +#define PC_POLL_RST_CLR BIT_1 /* Clear Polling Unit Reset (Enable) */
3255 +#define PC_POLL_RST_SET BIT_0 /* Set Polling Unit Reset */
3258 +/* The bit definition of the following registers is still missing! */
3259 +/* B28_Y2_SMB_CONFIG 32 bit ASF SMBus Config Register */
3260 +/* B28_Y2_SMB_CSD_REG 32 bit ASF SMB Control/Status/Data */
3261 +/* B28_Y2_ASF_IRQ_V_BASE 32 bit ASF IRQ Vector Base */
3263 +/* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */
3264 +/* This register is used by the host driver software */
3265 + /* Bit 31.. 5 reserved */
3266 +#define Y2_ASF_OS_PRES BIT_4S /* ASF operation system present */
3267 +#define Y2_ASF_RESET BIT_3S /* ASF system in reset state */
3268 +#define Y2_ASF_RUNNING BIT_2S /* ASF system operational */
3269 +#define Y2_ASF_CLR_HSTI BIT_1S /* Clear ASF IRQ */
3270 +#define Y2_ASF_IRQ BIT_0S /* Issue an IRQ to ASF system */
3272 +#define Y2_ASF_UC_STATE (3<<2) /* ASF uC State */
3273 +#define Y2_ASF_CLK_HALT 0 /* ASF system clock stopped */
3275 +/* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */
3276 +/* This register is used by the ASF firmware */
3277 + /* Bit 31.. 2 reserved */
3278 +#define Y2_ASF_CLR_ASFI BIT_1 /* Clear host IRQ */
3279 +#define Y2_ASF_HOST_IRQ BIT_0 /* Issue an IRQ to HOST system */
3282 +/* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
3283 + /* Bit 7.. 5: reserved */
3284 +#define SC_STAT_CLR_IRQ BIT_4 /* Status Burst IRQ clear */
3285 +#define SC_STAT_OP_ON BIT_3 /* Operational Mode On */
3286 +#define SC_STAT_OP_OFF BIT_2 /* Operational Mode Off */
3287 +#define SC_STAT_RST_CLR BIT_1 /* Clear Status Unit Reset (Enable) */
3288 +#define SC_STAT_RST_SET BIT_0 /* Set Status Unit Reset */
3290 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
3291 /* Bits 31.. 8: reserved */
3292 -#define GMC_H_BURST_ON BIT_7 /* Half Duplex Burst Mode On */
3293 -#define GMC_H_BURST_OFF BIT_6 /* Half Duplex Burst Mode Off */
3294 -#define GMC_F_LOOPB_ON BIT_5 /* FIFO Loopback On */
3295 -#define GMC_F_LOOPB_OFF BIT_4 /* FIFO Loopback Off */
3296 -#define GMC_PAUSE_ON BIT_3 /* Pause On */
3297 -#define GMC_PAUSE_OFF BIT_2 /* Pause Off */
3298 -#define GMC_RST_CLR BIT_1 /* Clear GMAC Reset */
3299 -#define GMC_RST_SET BIT_0 /* Set GMAC Reset */
3300 +#define GMC_H_BURST_ON BIT_7 /* Half Duplex Burst Mode On */
3301 +#define GMC_H_BURST_OFF BIT_6 /* Half Duplex Burst Mode Off */
3302 +#define GMC_F_LOOPB_ON BIT_5 /* FIFO Loopback On */
3303 +#define GMC_F_LOOPB_OFF BIT_4 /* FIFO Loopback Off */
3304 +#define GMC_PAUSE_ON BIT_3 /* Pause On */
3305 +#define GMC_PAUSE_OFF BIT_2 /* Pause Off */
3306 +#define GMC_RST_CLR BIT_1 /* Clear GMAC Reset */
3307 +#define GMC_RST_SET BIT_0 /* Set GMAC Reset */
3309 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
3310 /* Bits 31..29: reserved */
3311 #define GPC_SEL_BDT BIT_28 /* Select Bi-Dir. Transfer for MDC/MDIO */
3312 -#define GPC_INT_POL_HI BIT_27 /* IRQ Polarity is Active HIGH */
3313 +#define GPC_INT_POL BIT_27 /* IRQ Polarity is Active Low */
3314 #define GPC_75_OHM BIT_26 /* Use 75 Ohm Termination instead of 50 */
3315 #define GPC_DIS_FC BIT_25 /* Disable Automatic Fiber/Copper Detection */
3316 #define GPC_DIS_SLEEP BIT_24 /* Disable Energy Detect */
3317 @@ -1501,15 +2159,24 @@
3318 #define GPC_ANEG_2 BIT_15 /* ANEG[2] */
3319 #define GPC_ANEG_1 BIT_14 /* ANEG[1] */
3320 #define GPC_ENA_PAUSE BIT_13 /* Enable Pause (SYM_OR_REM) */
3321 -#define GPC_PHYADDR_4 BIT_12 /* Bit 4 of Phy Addr */
3322 -#define GPC_PHYADDR_3 BIT_11 /* Bit 3 of Phy Addr */
3323 -#define GPC_PHYADDR_2 BIT_10 /* Bit 2 of Phy Addr */
3324 -#define GPC_PHYADDR_1 BIT_9 /* Bit 1 of Phy Addr */
3325 -#define GPC_PHYADDR_0 BIT_8 /* Bit 0 of Phy Addr */
3326 +#define GPC_PHYADDR_4 BIT_12 /* Bit 4 of PHY Addr */
3327 +#define GPC_PHYADDR_3 BIT_11 /* Bit 3 of PHY Addr */
3328 +#define GPC_PHYADDR_2 BIT_10 /* Bit 2 of PHY Addr */
3329 +#define GPC_PHYADDR_1 BIT_9 /* Bit 1 of PHY Addr */
3330 +#define GPC_PHYADDR_0 BIT_8 /* Bit 0 of PHY Addr */
3331 /* Bits 7..2: reserved */
3332 #define GPC_RST_CLR BIT_1 /* Clear GPHY Reset */
3333 #define GPC_RST_SET BIT_0 /* Set GPHY Reset */
3335 +/* Yukon-EC Ultra only */
3336 +#define GPC_LED_CONF_MSK (7<<6) /* Bit 8.. 6: GPHY LED Config */
3337 +#define GPC_PD_125M_CLK_OFF BIT_5 /* Disable Power Down Clock 125 MHz */
3338 +#define GPC_PD_125M_CLK_ON BIT_4 /* Enable Power Down Clock 125 MHz */
3339 +#define GPC_DPLL_RST_SET BIT_3 /* Set GPHY's DPLL Reset */
3340 +#define GPC_DPLL_RST_CLR BIT_2 /* Clear GPHY's DPLL Reset */
3341 + /* (DPLL = Digital Phase Lock Loop) */
3342 +#define GPC_LED_CONF_VAL(x) (SHIFT6(x) & GPC_LED_CONF_MSK)
3344 #define GPC_HWCFG_GMII_COP (GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | \
3345 GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
3347 @@ -1540,20 +2207,20 @@
3349 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
3350 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
3351 -#define GM_IS_TX_CO_OV BIT_5 /* Transmit Counter Overflow IRQ */
3352 -#define GM_IS_RX_CO_OV BIT_4 /* Receive Counter Overflow IRQ */
3353 -#define GM_IS_TX_FF_UR BIT_3 /* Transmit FIFO Underrun */
3354 -#define GM_IS_TX_COMPL BIT_2 /* Frame Transmission Complete */
3355 -#define GM_IS_RX_FF_OR BIT_1 /* Receive FIFO Overrun */
3356 -#define GM_IS_RX_COMPL BIT_0 /* Frame Reception Complete */
3357 +#define GM_IS_RX_CO_OV BIT_5S /* Receive Counter Overflow IRQ */
3358 +#define GM_IS_TX_CO_OV BIT_4S /* Transmit Counter Overflow IRQ */
3359 +#define GM_IS_TX_FF_UR BIT_3S /* Transmit FIFO Underrun */
3360 +#define GM_IS_TX_COMPL BIT_2S /* Frame Transmission Complete */
3361 +#define GM_IS_RX_FF_OR BIT_1S /* Receive FIFO Overrun */
3362 +#define GM_IS_RX_COMPL BIT_0S /* Frame Reception Complete */
3364 -#define GMAC_DEF_MSK (GM_IS_TX_CO_OV | GM_IS_RX_CO_OV | \
3365 +#define GMAC_DEF_MSK (GM_IS_RX_CO_OV | GM_IS_TX_CO_OV | \
3368 -/* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
3369 +/* GMAC_LINK_CTRL 16 bit Link Control Reg (YUKON only) */
3370 /* Bits 15.. 2: reserved */
3371 -#define GMLC_RST_CLR BIT_1S /* Clear GMAC Link Reset */
3372 -#define GMLC_RST_SET BIT_0S /* Set GMAC Link Reset */
3373 +#define GMLC_RST_CLR BIT_1S /* Clear Link Reset */
3374 +#define GMLC_RST_SET BIT_0S /* Set Link Reset */
3377 /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
3378 @@ -1579,15 +2246,19 @@
3380 #define WOL_CTL_DEFAULT \
3381 (WOL_CTL_DIS_PME_ON_LINK_CHG | \
3382 - WOL_CTL_DIS_PME_ON_PATTERN | \
3383 - WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
3384 - WOL_CTL_DIS_LINK_CHG_UNIT | \
3385 - WOL_CTL_DIS_PATTERN_UNIT | \
3386 - WOL_CTL_DIS_MAGIC_PKT_UNIT)
3387 + WOL_CTL_DIS_PME_ON_PATTERN | \
3388 + WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
3389 + WOL_CTL_DIS_LINK_CHG_UNIT | \
3390 + WOL_CTL_DIS_PATTERN_UNIT | \
3391 + WOL_CTL_DIS_MAGIC_PKT_UNIT)
3393 /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
3394 #define WOL_CTL_PATT_ENA(x) (BIT_0 << (x))
3396 +/* WOL_PATT_PME 8 bit WOL PME Match Enable (Yukon-2) */
3397 +#define WOL_PATT_FORCE_PME BIT_7 /* Generates a PME */
3398 +#define WOL_PATT_MATCH_PME_ALL 0x7f
3400 #define SK_NUM_WOL_PATTERN 7
3401 #define SK_PATTERN_PER_WORD 4
3402 #define SK_BITMASK_PATTERN 7
3403 @@ -1597,26 +2268,28 @@
3404 #define WOL_LENGTH_SHIFT 8
3407 +/* typedefs ******************************************************************/
3409 /* Receive and Transmit Descriptors ******************************************/
3411 /* Transmit Descriptor struct */
3412 typedef struct s_HwTxd {
3413 SK_U32 volatile TxCtrl; /* Transmit Buffer Control Field */
3414 SK_U32 TxNext; /* Physical Address Pointer to the next TxD */
3415 - SK_U32 TxAdrLo; /* Physical Tx Buffer Address lower dword */
3416 - SK_U32 TxAdrHi; /* Physical Tx Buffer Address upper dword */
3417 + SK_U32 TxAdrLo; /* Physical Tx Buffer Address lower DWord */
3418 + SK_U32 TxAdrHi; /* Physical Tx Buffer Address upper DWord */
3419 SK_U32 TxStat; /* Transmit Frame Status Word */
3420 -#ifndef SK_USE_REV_DESC
3421 +#ifndef SK_USE_REV_DESC
3422 SK_U16 TxTcpOffs; /* TCP Checksum Calculation Start Value */
3423 SK_U16 TxRes1; /* 16 bit reserved field */
3424 SK_U16 TxTcpWp; /* TCP Checksum Write Position */
3425 SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */
3426 -#else /* SK_USE_REV_DESC */
3427 +#else /* SK_USE_REV_DESC */
3428 SK_U16 TxRes1; /* 16 bit reserved field */
3429 SK_U16 TxTcpOffs; /* TCP Checksum Calculation Start Value */
3430 SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */
3431 SK_U16 TxTcpWp; /* TCP Checksum Write Position */
3432 -#endif /* SK_USE_REV_DESC */
3433 +#endif /* SK_USE_REV_DESC */
3434 SK_U32 TxRes2; /* 32 bit reserved field */
3437 @@ -1624,33 +2297,266 @@
3438 typedef struct s_HwRxd {
3439 SK_U32 volatile RxCtrl; /* Receive Buffer Control Field */
3440 SK_U32 RxNext; /* Physical Address Pointer to the next RxD */
3441 - SK_U32 RxAdrLo; /* Physical Rx Buffer Address lower dword */
3442 - SK_U32 RxAdrHi; /* Physical Rx Buffer Address upper dword */
3443 + SK_U32 RxAdrLo; /* Physical Rx Buffer Address lower DWord */
3444 + SK_U32 RxAdrHi; /* Physical Rx Buffer Address upper DWord */
3445 SK_U32 RxStat; /* Receive Frame Status Word */
3446 SK_U32 RxTiSt; /* Receive Time Stamp (from XMAC on GENESIS) */
3447 -#ifndef SK_USE_REV_DESC
3448 - SK_U16 RxTcpSum1; /* TCP Checksum 1 */
3449 - SK_U16 RxTcpSum2; /* TCP Checksum 2 */
3450 +#ifndef SK_USE_REV_DESC
3451 + SK_U16 RxTcpSum1; /* Rx TCP Checksum 1 */
3452 + SK_U16 RxTcpSum2; /* Rx TCP Checksum 2 */
3453 SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */
3454 SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */
3455 -#else /* SK_USE_REV_DESC */
3456 - SK_U16 RxTcpSum2; /* TCP Checksum 2 */
3457 - SK_U16 RxTcpSum1; /* TCP Checksum 1 */
3458 +#else /* SK_USE_REV_DESC */
3459 + SK_U16 RxTcpSum2; /* Rx TCP Checksum 2 */
3460 + SK_U16 RxTcpSum1; /* Rx TCP Checksum 1 */
3461 SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */
3462 SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */
3463 -#endif /* SK_USE_REV_DESC */
3464 +#endif /* SK_USE_REV_DESC */
3468 * Drivers which use the reverse descriptor feature (PCI_OUR_REG_2)
3469 * should set the define SK_USE_REV_DESC.
3470 - * Structures are 'normaly' not endianess dependent. But in
3471 - * this case the SK_U16 fields are bound to bit positions inside the
3472 - * descriptor. RxTcpSum1 e.g. must start at bit 0 within the 6.th DWord.
3473 + * Structures are 'normally' not endianess dependent. But in this case
3474 + * the SK_U16 fields are bound to bit positions inside the descriptor.
3475 + * RxTcpSum1 e.g. must start at bit 0 within the 7.th DWord.
3476 * The bit positions inside a DWord are of course endianess dependent and
3477 - * swaps if the DWord is swapped by the hardware.
3478 + * swap if the DWord is swapped by the hardware.
3481 +/* YUKON-2 descriptors ******************************************************/
3483 +typedef struct _TxChksum {
3484 +#ifndef SK_USE_REV_DESC
3485 + SK_U16 TxTcpWp; /* TCP Checksum Write Position */
3486 + SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */
3487 +#else /* SK_USE_REV_DESC */
3488 + SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */
3489 + SK_U16 TxTcpWp; /* TCP Checksum Write Position */
3490 +#endif /* SK_USE_REV_DESC */
3493 +typedef struct _LargeSend {
3494 +#ifndef SK_USE_REV_DESC
3495 + SK_U16 Length; /* Large Send Segment Length */
3496 + SK_U16 Reserved; /* reserved */
3497 +#else /* SK_USE_REV_DESC */
3498 + SK_U16 Reserved; /* reserved */
3499 + SK_U16 Length; /* Large Send Segment Length */
3500 +#endif /* SK_USE_REV_DESC */
3503 +typedef union u_HwTxBuf {
3504 + SK_U16 BufLen; /* Tx Buffer Length */
3505 + SK_U16 VlanTag; /* VLAN Tag */
3506 + SK_U16 InitCsum; /* Init. Checksum */
3509 +/* Tx List Element structure */
3510 +typedef struct s_HwLeTx {
3512 + SK_U32 BufAddr; /* Tx LE Buffer Address high/low */
3513 + SK_HWTXCS ChkSum; /* Tx LE TCP Checksum parameters */
3514 + SK_HWTXLS LargeSend;/* Large Send length */
3516 +#ifndef SK_USE_REV_DESC
3518 + SK_U8 ControlFlags; /* Tx LE Control field or Lock Number */
3519 + SK_U8 Opcode; /* Tx LE Opcode field */
3520 +#else /* SK_USE_REV_DESC */
3521 + SK_U8 Opcode; /* Tx LE Opcode field */
3522 + SK_U8 ControlFlags; /* Tx LE Control field or Lock Number */
3524 +#endif /* SK_USE_REV_DESC */
3527 +typedef struct _RxChkSum{
3528 +#ifndef SK_USE_REV_DESC
3529 + SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */
3530 + SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */
3531 +#else /* SK_USE_REV_DESC */
3532 + SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */
3533 + SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */
3534 +#endif /* SK_USE_REV_DESC */
3537 +/* Rx List Element structure */
3538 +typedef struct s_HwLeRx {
3540 + SK_U32 BufAddr; /* Rx LE Buffer Address high/low */
3541 + SK_HWRXCS ChkSum; /* Rx LE TCP Checksum parameters */
3543 +#ifndef SK_USE_REV_DESC
3544 + SK_U16 BufferLength; /* Rx LE Buffer Length field */
3545 + SK_U8 ControlFlags; /* Rx LE Control field */
3546 + SK_U8 Opcode; /* Rx LE Opcode field */
3547 +#else /* SK_USE_REV_DESC */
3548 + SK_U8 Opcode; /* Rx LE Opcode field */
3549 + SK_U8 ControlFlags; /* Rx LE Control field */
3550 + SK_U16 BufferLength; /* Rx LE Buffer Length field */
3551 +#endif /* SK_USE_REV_DESC */
3554 +typedef struct s_StRxTCPChkSum {
3555 +#ifndef SK_USE_REV_DESC
3556 + SK_U16 RxTCPSum1; /* Rx TCP Checksum 1 */
3557 + SK_U16 RxTCPSum2; /* Rx TCP Checksum 2 */
3558 +#else /* SK_USE_REV_DESC */
3559 + SK_U16 RxTCPSum2; /* Rx TCP Checksum 2 */
3560 + SK_U16 RxTCPSum1; /* Rx TCP Checksum 1 */
3561 +#endif /* SK_USE_REV_DESC */
3564 +typedef struct s_StRxRssFlags {
3565 +#ifndef SK_USE_REV_DESC
3566 + SK_U8 FlagField; /* contains TCP and IP flags */
3567 + SK_U8 reserved; /* reserved */
3568 +#else /* SK_USE_REV_DESC */
3569 + SK_U8 reserved; /* reserved */
3570 + SK_U8 FlagField; /* contains TCP and IP flags */
3571 +#endif /* SK_USE_REV_DESC */
3574 +/* bit definition of RSS LE bit 32/33 (SK_HWSTRSS.FlagField) */
3575 + /* bit 7..2 reserved */
3576 +#define RSS_TCP_FLAG BIT_1S /* RSS value related to TCP area */
3577 +#define RSS_IP_FLAG BIT_0S /* RSS value related to IP area */
3578 +/* StRxRssValue is valid if at least RSS_IP_FLAG is set */
3579 +/* For protocol errors or other protocols an empty RSS LE is generated */
3581 +typedef union u_HwStBuf {
3582 + SK_U16 BufLen; /* Rx Buffer Length */
3583 + SK_U16 VlanTag; /* VLAN Tag */
3584 + SK_U16 StTxStatHi; /* Tx Queue Status (high) */
3585 + SK_HWSTRSS Rss; /* Flag Field for TCP and IP protocol */
3588 +/* Status List Element structure */
3589 +typedef struct s_HwLeSt {
3591 + SK_U32 StRxStatWord; /* Rx Status Dword */
3592 + SK_U32 StRxTimeStamp; /* Rx Timestamp */
3593 + SK_HWSTCS StRxTCPCSum; /* Rx TCP Checksum */
3594 + SK_U32 StTxStatLow; /* Tx Queue Status (low) */
3595 + SK_U32 StRxRssValue; /* Rx RSS value */
3597 +#ifndef SK_USE_REV_DESC
3599 + SK_U8 Link; /* Status LE Link field */
3600 + SK_U8 Opcode; /* Status LE Opcode field */
3601 +#else /* SK_USE_REV_DESC */
3602 + SK_U8 Opcode; /* Status LE Opcode field */
3603 + SK_U8 Link; /* Status LE Link field */
3605 +#endif /* SK_USE_REV_DESC */
3608 +/* Special Action List Element */
3609 +typedef struct s_HwLeSa {
3610 +#ifndef SK_USE_REV_DESC
3611 + SK_U16 TxAIdxVld; /* Special Action LE TxA Put Index field */
3612 + SK_U16 TxSIdxVld; /* Special Action LE TxS Put Index field */
3613 + SK_U16 RxIdxVld; /* Special Action LE Rx Put Index field */
3614 + SK_U8 Link; /* Special Action LE Link field */
3615 + SK_U8 Opcode; /* Special Action LE Opcode field */
3616 +#else /* SK_USE_REV_DESC */
3617 + SK_U16 TxSIdxVld; /* Special Action LE TxS Put Index field */
3618 + SK_U16 TxAIdxVld; /* Special Action LE TxA Put Index field */
3619 + SK_U8 Opcode; /* Special Action LE Opcode field */
3620 + SK_U8 Link; /* Special Action LE Link field */
3621 + SK_U16 RxIdxVld; /* Special Action LE Rx Put Index field */
3622 +#endif /* SK_USE_REV_DESC */
3625 +/* Common List Element union */
3626 +typedef union u_HwLeTxRxSt {
3627 + /* Transmit List Element Structure */
3629 + /* Receive List Element Structure */
3631 + /* Status List Element Structure */
3633 + /* Special Action List Element Structure */
3635 + /* Full List Element */
3639 +/* mask and shift value to get Tx async queue status for port 1 */
3640 +#define STLE_TXA1_MSKL 0x00000fff
3641 +#define STLE_TXA1_SHIFTL 0
3643 +/* mask and shift value to get Tx sync queue status for port 1 */
3644 +#define STLE_TXS1_MSKL 0x00fff000
3645 +#define STLE_TXS1_SHIFTL 12
3647 +/* mask and shift value to get Tx async queue status for port 2 */
3648 +#define STLE_TXA2_MSKL 0xff000000
3649 +#define STLE_TXA2_SHIFTL 24
3650 +#define STLE_TXA2_MSKH 0x000f
3651 +/* this one shifts up */
3652 +#define STLE_TXA2_SHIFTH 8
3654 +/* mask and shift value to get Tx sync queue status for port 2 */
3655 +#define STLE_TXS2_MSKL 0x00000000
3656 +#define STLE_TXS2_SHIFTL 0
3657 +#define STLE_TXS2_MSKH 0xfff0
3658 +#define STLE_TXS2_SHIFTH 4
3660 +/* YUKON-2 bit values */
3661 +#define HW_OWNER BIT_7
3664 +#define PU_PUTIDX_VALID BIT_12
3666 +/* YUKON-2 Control flags */
3667 +#define UDPTCP BIT_0S
3668 +#define CALSUM BIT_1S
3669 +#define WR_SUM BIT_2S
3670 +#define INIT_SUM BIT_3S
3671 +#define LOCK_SUM BIT_4S
3672 +#define INS_VLAN BIT_5S
3673 +#define FRC_STAT BIT_6S
3676 +#define TX_LOCK BIT_8S
3677 +#define BUF_SEND BIT_9S
3678 +#define PACKET_SEND BIT_10S
3680 +#define NO_WARNING BIT_14S
3681 +#define NO_UPDATE BIT_15S
3683 +/* YUKON-2 Rx/Tx opcodes defines */
3684 +#define OP_TCPWRITE 0x11
3685 +#define OP_TCPSTART 0x12
3686 +#define OP_TCPINIT 0x14
3687 +#define OP_TCPLCK 0x18
3688 +#define OP_TCPCHKSUM OP_TCPSTART
3689 +#define OP_TCPIS (OP_TCPINIT | OP_TCPSTART)
3690 +#define OP_TCPLW (OP_TCPLCK | OP_TCPWRITE)
3691 +#define OP_TCPLSW (OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE)
3692 +#define OP_TCPLISW (OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE)
3693 +#define OP_ADDR64 0x21
3694 +#define OP_VLAN 0x22
3695 +#define OP_ADDR64VLAN (OP_ADDR64 | OP_VLAN)
3696 +#define OP_LRGLEN 0x24
3697 +#define OP_LRGLENVLAN (OP_LRGLEN | OP_VLAN)
3698 +#define OP_BUFFER 0x40
3699 +#define OP_PACKET 0x41
3700 +#define OP_LARGESEND 0x43
3702 +/* YUKON-2 STATUS opcodes defines */
3703 +#define OP_RXSTAT 0x60
3704 +#define OP_RXTIMESTAMP 0x61
3705 +#define OP_RXVLAN 0x62
3706 +#define OP_RXCHKS 0x64
3707 +#define OP_RXCHKSVLAN (OP_RXCHKS | OP_RXVLAN)
3708 +#define OP_RXTIMEVLAN (OP_RXTIMESTAMP | OP_RXVLAN)
3709 +#define OP_RSS_HASH 0x65
3710 +#define OP_TXINDEXLE 0x68
3712 +/* YUKON-2 SPECIAL opcodes defines */
3713 +#define OP_PUTIDX 0x70
3715 /* Descriptor Bit Definition */
3716 /* TxCtrl Transmit Buffer Control Field */
3717 @@ -1685,6 +2591,10 @@
3719 /* macros ********************************************************************/
3721 +/* Macro for accessing the key registers */
3722 +#define RSS_KEY_ADDR(Port, KeyIndex) \
3723 + ((B4_RSS_KEY | ( ((Port) == 0) ? 0 : 0x80)) + (KeyIndex))
3725 /* Receive and Transmit Queues */
3726 #define Q_R1 0x0000 /* Receive Queue 1 */
3727 #define Q_R2 0x0080 /* Receive Queue 2 */
3728 @@ -1693,6 +2603,10 @@
3729 #define Q_XS2 0x0300 /* Synchronous Transmit Queue 2 */
3730 #define Q_XA2 0x0380 /* Asynchronous Transmit Queue 2 */
3732 +#define Q_ASF_R1 0x100 /* ASF Rx Queue 1 */
3733 +#define Q_ASF_R2 0x180 /* ASF Rx Queue 2 */
3734 +#define Q_ASF_T1 0x140 /* ASF Tx Queue 1 */
3735 +#define Q_ASF_T2 0x1c0 /* ASF Tx Queue 2 */
3739 @@ -1704,11 +2618,27 @@
3740 * Offs Queue register offset.
3741 * Values: Q_D, Q_DA_L ... Q_T2, Q_T3
3743 - * usage SK_IN32(pAC, Q_ADDR(Q_R2, Q_BC), pVal)
3744 + * usage SK_IN32(IoC, Q_ADDR(Q_R2, Q_BC), pVal)
3746 #define Q_ADDR(Queue, Offs) (B8_Q_REGS + (Queue) + (Offs))
3749 + * Macro Y2_PREF_Q_ADDR()
3751 + * Use this macro to access the Prefetch Units of the receive and
3752 + * transmit queues of Yukon-2.
3755 + * Queue Queue to access.
3756 + * Values: Q_R1, Q_R2, Q_XS1, Q_XA1, Q_XS2, Q_XA2,
3757 + * Offs Queue register offset.
3758 + * Values: PREF_UNIT_CTRL_REG ... PREF_UNIT_FIFO_LEV_REG
3760 + * usage SK_IN16(IoC, Y2_Q_ADDR(Q_R2, PREF_UNIT_GET_IDX_REG), pVal)
3762 +#define Y2_PREF_Q_ADDR(Queue, Offs) (Y2_B8_PREF_REGS + (Queue) + (Offs))
3767 * Use this macro to access the RAM Buffer Registers.
3768 @@ -1719,14 +2649,14 @@
3769 * Offs Queue register offset.
3770 * Values: RB_START, RB_END ... RB_LEV, RB_CTRL
3772 - * usage SK_IN32(pAC, RB_ADDR(Q_R2, RB_RP), pVal)
3773 + * usage SK_IN32(IoC, RB_ADDR(Q_R2, RB_RP), pVal)
3775 #define RB_ADDR(Queue, Offs) (B16_RAM_REGS + (Queue) + (Offs))
3778 /* MAC Related Registers */
3779 -#define MAC_1 0 /* belongs to the port near the slot */
3780 -#define MAC_2 1 /* belongs to the port far away from the slot */
3781 +#define MAC_1 0 /* 1st port */
3782 +#define MAC_2 1 /* 2nd port */
3786 @@ -1740,19 +2670,10 @@
3787 * Values: RX_MFF_EA, RX_MFF_WP ... LNK_LED_REG,
3788 * TX_MFF_EA, TX_MFF_WP ... TX_LED_TST
3790 - * usage SK_IN32(pAC, MR_ADDR(MAC_1, TX_MFF_EA), pVal)
3791 + * usage SK_IN32(IoC, MR_ADDR(MAC_1, TX_MFF_EA), pVal)
3793 #define MR_ADDR(Mac, Offs) (((Mac) << 7) + (Offs))
3795 -#ifdef SK_LITTLE_ENDIAN
3796 -#define XM_WORD_LO 0
3797 -#define XM_WORD_HI 1
3798 -#else /* !SK_LITTLE_ENDIAN */
3799 -#define XM_WORD_LO 1
3800 -#define XM_WORD_HI 0
3801 -#endif /* !SK_LITTLE_ENDIAN */
3805 * macros to access the XMAC (GENESIS only)
3807 @@ -1777,22 +2698,31 @@
3808 #define XMA(Mac, Reg) \
3809 ((BASE_XMAC_1 + (Mac) * (BASE_XMAC_2 - BASE_XMAC_1)) | ((Reg) << 1))
3811 -#define XM_IN16(IoC, Mac, Reg, pVal) \
3812 - SK_IN16((IoC), XMA((Mac), (Reg)), (pVal))
3813 +#define XM_IN16(IoC, Mac, Reg, pVal) \
3814 + SK_IN16(IoC, XMA(Mac, Reg), pVal)
3816 -#define XM_OUT16(IoC, Mac, Reg, Val) \
3817 - SK_OUT16((IoC), XMA((Mac), (Reg)), (Val))
3818 +#define XM_OUT16(IoC, Mac, Reg, Val) \
3819 + SK_OUT16(IoC, XMA(Mac, Reg), Val)
3821 -#define XM_IN32(IoC, Mac, Reg, pVal) { \
3822 - SK_IN16((IoC), XMA((Mac), (Reg)), \
3823 - (SK_U16 SK_FAR*)&((SK_U16 SK_FAR*)(pVal))[XM_WORD_LO]); \
3824 - SK_IN16((IoC), XMA((Mac), (Reg+2)), \
3825 - (SK_U16 SK_FAR*)&((SK_U16 SK_FAR*)(pVal))[XM_WORD_HI]); \
3826 +#ifdef SK_LITTLE_ENDIAN
3828 +#define XM_IN32(IoC, Mac, Reg, pVal) { \
3829 + SK_IN16(IoC, XMA(Mac, Reg), (SK_U16 SK_FAR *)(pVal)); \
3830 + SK_IN16(IoC, XMA(Mac, (Reg) + 2), (SK_U16 SK_FAR *)(pVal) + 1); \
3833 +#else /* !SK_LITTLE_ENDIAN */
3835 +#define XM_IN32(IoC, Mac, Reg, pVal) { \
3836 + SK_IN16(IoC, XMA(Mac, Reg), (SK_U16 SK_FAR *)(pVal) + 1); \
3837 + SK_IN16(IoC, XMA(Mac, (Reg) + 2), (SK_U16 SK_FAR *)(pVal)); \
3840 +#endif /* !SK_LITTLE_ENDIAN */
3842 #define XM_OUT32(IoC, Mac, Reg, Val) { \
3843 - SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16)((Val) & 0xffffL)); \
3844 - SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16)(((Val) >> 16) & 0xffffL));\
3845 + SK_OUT16(IoC, XMA(Mac, Reg), (SK_U16)((Val) & 0xffffL)); \
3846 + SK_OUT16(IoC, XMA(Mac, (Reg) + 2), (SK_U16)(((Val) >> 16) & 0xffffL)); \
3849 /* Remember: we are always writing to / reading from LITTLE ENDIAN memory */
3850 @@ -1802,13 +2732,13 @@
3852 pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \
3853 SK_IN16((IoC), XMA((Mac), (Reg)), &Word); \
3854 - pByte[0] = (SK_U8)(Word & 0x00ff); \
3855 + pByte[0] = (SK_U8)(Word & 0x00ff); \
3856 pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \
3857 - SK_IN16((IoC), XMA((Mac), (Reg+2)), &Word); \
3858 - pByte[2] = (SK_U8)(Word & 0x00ff); \
3859 + SK_IN16((IoC), XMA((Mac), (Reg) + 2), &Word); \
3860 + pByte[2] = (SK_U8)(Word & 0x00ff); \
3861 pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \
3862 - SK_IN16((IoC), XMA((Mac), (Reg+4)), &Word); \
3863 - pByte[4] = (SK_U8)(Word & 0x00ff); \
3864 + SK_IN16((IoC), XMA((Mac), (Reg) + 4), &Word); \
3865 + pByte[4] = (SK_U8)(Word & 0x00ff); \
3866 pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \
3869 @@ -1818,10 +2748,10 @@
3870 SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16) \
3871 (((SK_U16)(pByte[0]) & 0x00ff) | \
3872 (((SK_U16)(pByte[1]) << 8) & 0xff00))); \
3873 - SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16) \
3874 + SK_OUT16((IoC), XMA((Mac), (Reg) + 2), (SK_U16) \
3875 (((SK_U16)(pByte[2]) & 0x00ff) | \
3876 (((SK_U16)(pByte[3]) << 8) & 0xff00))); \
3877 - SK_OUT16((IoC), XMA((Mac), (Reg+4)), (SK_U16) \
3878 + SK_OUT16((IoC), XMA((Mac), (Reg) + 4), (SK_U16) \
3879 (((SK_U16)(pByte[4]) & 0x00ff) | \
3880 (((SK_U16)(pByte[5]) << 8) & 0xff00))); \
3882 @@ -1831,16 +2761,16 @@
3883 SK_U8 SK_FAR *pByte; \
3884 pByte = (SK_U8 SK_FAR *)&((SK_U8 SK_FAR *)(pVal))[0]; \
3885 SK_IN16((IoC), XMA((Mac), (Reg)), &Word); \
3886 - pByte[0] = (SK_U8)(Word & 0x00ff); \
3887 + pByte[0] = (SK_U8)(Word & 0x00ff); \
3888 pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \
3889 - SK_IN16((IoC), XMA((Mac), (Reg+2)), &Word); \
3890 - pByte[2] = (SK_U8)(Word & 0x00ff); \
3891 + SK_IN16((IoC), XMA((Mac), (Reg) + 2), &Word); \
3892 + pByte[2] = (SK_U8)(Word & 0x00ff); \
3893 pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \
3894 - SK_IN16((IoC), XMA((Mac), (Reg+4)), &Word); \
3895 - pByte[4] = (SK_U8)(Word & 0x00ff); \
3896 + SK_IN16((IoC), XMA((Mac), (Reg) + 4), &Word); \
3897 + pByte[4] = (SK_U8)(Word & 0x00ff); \
3898 pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \
3899 - SK_IN16((IoC), XMA((Mac), (Reg+6)), &Word); \
3900 - pByte[6] = (SK_U8)(Word & 0x00ff); \
3901 + SK_IN16((IoC), XMA((Mac), (Reg) + 6), &Word); \
3902 + pByte[6] = (SK_U8)(Word & 0x00ff); \
3903 pByte[7] = (SK_U8)((Word >> 8) & 0x00ff); \
3906 @@ -1850,13 +2780,13 @@
3907 SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16) \
3908 (((SK_U16)(pByte[0]) & 0x00ff)| \
3909 (((SK_U16)(pByte[1]) << 8) & 0xff00))); \
3910 - SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16) \
3911 + SK_OUT16((IoC), XMA((Mac), (Reg) + 2), (SK_U16) \
3912 (((SK_U16)(pByte[2]) & 0x00ff)| \
3913 (((SK_U16)(pByte[3]) << 8) & 0xff00))); \
3914 - SK_OUT16((IoC), XMA((Mac), (Reg+4)), (SK_U16) \
3915 + SK_OUT16((IoC), XMA((Mac), (Reg) + 4), (SK_U16) \
3916 (((SK_U16)(pByte[4]) & 0x00ff)| \
3917 (((SK_U16)(pByte[5]) << 8) & 0xff00))); \
3918 - SK_OUT16((IoC), XMA((Mac), (Reg+6)), (SK_U16) \
3919 + SK_OUT16((IoC), XMA((Mac), (Reg) + 6), (SK_U16) \
3920 (((SK_U16)(pByte[6]) & 0x00ff)| \
3921 (((SK_U16)(pByte[7]) << 8) & 0xff00))); \
3923 @@ -1866,12 +2796,12 @@
3925 * GM_IN16(), to read a 16 bit register (e.g. GM_GP_STAT)
3926 * GM_OUT16(), to write a 16 bit register (e.g. GM_GP_CTRL)
3927 - * GM_IN32(), to read a 32 bit register (e.g. GM_)
3928 - * GM_OUT32(), to write a 32 bit register (e.g. GM_)
3929 + * GM_IN32(), to read a 32 bit register (e.g. GM_RXF_UC_OK)
3930 + * GM_OUT32(), to write a 32 bit register
3931 * GM_INADDR(), to read a network address register (e.g. GM_SRC_ADDR_1L)
3932 * GM_OUTADDR(), to write a network address register (e.g. GM_SRC_ADDR_2L)
3933 - * GM_INHASH(), to read the GM_MC_ADDR_H1 register
3934 - * GM_OUTHASH() to write the GM_MC_ADDR_H1 register
3935 + * GM_INHASH(), to read the hash registers (e.g. GM_MC_ADDR_H1..4)
3936 + * GM_OUTHASH() to write the hash registers (e.g. GM_MC_ADDR_H1..4)
3939 * Mac GMAC to access values: MAC_1 or MAC_2
3940 @@ -1885,22 +2815,31 @@
3941 #define GMA(Mac, Reg) \
3942 ((BASE_GMAC_1 + (Mac) * (BASE_GMAC_2 - BASE_GMAC_1)) | (Reg))
3944 -#define GM_IN16(IoC, Mac, Reg, pVal) \
3945 - SK_IN16((IoC), GMA((Mac), (Reg)), (pVal))
3946 +#define GM_IN16(IoC, Mac, Reg, pVal) \
3947 + SK_IN16(IoC, GMA(Mac, Reg), pVal)
3949 -#define GM_OUT16(IoC, Mac, Reg, Val) \
3950 - SK_OUT16((IoC), GMA((Mac), (Reg)), (Val))
3951 +#define GM_OUT16(IoC, Mac, Reg, Val) \
3952 + SK_OUT16(IoC, GMA(Mac, Reg), Val)
3954 -#define GM_IN32(IoC, Mac, Reg, pVal) { \
3955 - SK_IN16((IoC), GMA((Mac), (Reg)), \
3956 - (SK_U16 SK_FAR*)&((SK_U16 SK_FAR*)(pVal))[XM_WORD_LO]); \
3957 - SK_IN16((IoC), GMA((Mac), (Reg+4)), \
3958 - (SK_U16 SK_FAR*)&((SK_U16 SK_FAR*)(pVal))[XM_WORD_HI]); \
3959 +#ifdef SK_LITTLE_ENDIAN
3961 +#define GM_IN32(IoC, Mac, Reg, pVal) { \
3962 + SK_IN16(IoC, GMA(Mac, Reg), (SK_U16 SK_FAR *)(pVal)); \
3963 + SK_IN16((IoC), GMA(Mac, (Reg) + 4), (SK_U16 SK_FAR *)(pVal) + 1); \
3966 +#else /* !SK_LITTLE_ENDIAN */
3968 +#define GM_IN32(IoC, Mac, Reg, pVal) { \
3969 + SK_IN16(IoC, GMA(Mac, Reg), (SK_U16 SK_FAR *)(pVal) + 1); \
3970 + SK_IN16(IoC, GMA(Mac, (Reg) + 4), (SK_U16 SK_FAR *)(pVal)); \
3973 +#endif /* !SK_LITTLE_ENDIAN */
3975 #define GM_OUT32(IoC, Mac, Reg, Val) { \
3976 - SK_OUT16((IoC), GMA((Mac), (Reg)), (SK_U16)((Val) & 0xffffL)); \
3977 - SK_OUT16((IoC), GMA((Mac), (Reg+4)), (SK_U16)(((Val) >> 16) & 0xffffL));\
3978 + SK_OUT16(IoC, GMA(Mac, Reg), (SK_U16)((Val) & 0xffffL)); \
3979 + SK_OUT16(IoC, GMA(Mac, (Reg) + 4), (SK_U16)(((Val) >> 16) & 0xffffL)); \
3982 #define GM_INADDR(IoC, Mac, Reg, pVal) { \
3983 @@ -1908,13 +2847,13 @@
3985 pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \
3986 SK_IN16((IoC), GMA((Mac), (Reg)), &Word); \
3987 - pByte[0] = (SK_U8)(Word & 0x00ff); \
3988 + pByte[0] = (SK_U8)(Word & 0x00ff); \
3989 pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \
3990 - SK_IN16((IoC), GMA((Mac), (Reg+4)), &Word); \
3991 - pByte[2] = (SK_U8)(Word & 0x00ff); \
3992 + SK_IN16((IoC), GMA((Mac), (Reg) + 4), &Word); \
3993 + pByte[2] = (SK_U8)(Word & 0x00ff); \
3994 pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \
3995 - SK_IN16((IoC), GMA((Mac), (Reg+8)), &Word); \
3996 - pByte[4] = (SK_U8)(Word & 0x00ff); \
3997 + SK_IN16((IoC), GMA((Mac), (Reg) + 8), &Word); \
3998 + pByte[4] = (SK_U8)(Word & 0x00ff); \
3999 pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \
4002 @@ -1924,10 +2863,10 @@
4003 SK_OUT16((IoC), GMA((Mac), (Reg)), (SK_U16) \
4004 (((SK_U16)(pByte[0]) & 0x00ff) | \
4005 (((SK_U16)(pByte[1]) << 8) & 0xff00))); \
4006 - SK_OUT16((IoC), GMA((Mac), (Reg+4)), (SK_U16) \
4007 + SK_OUT16((IoC), GMA((Mac), (Reg) + 4), (SK_U16) \
4008 (((SK_U16)(pByte[2]) & 0x00ff) | \
4009 (((SK_U16)(pByte[3]) << 8) & 0xff00))); \
4010 - SK_OUT16((IoC), GMA((Mac), (Reg+8)), (SK_U16) \
4011 + SK_OUT16((IoC), GMA((Mac), (Reg) + 8), (SK_U16) \
4012 (((SK_U16)(pByte[4]) & 0x00ff) | \
4013 (((SK_U16)(pByte[5]) << 8) & 0xff00))); \
4015 @@ -1937,16 +2876,16 @@
4017 pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \
4018 SK_IN16((IoC), GMA((Mac), (Reg)), &Word); \
4019 - pByte[0] = (SK_U8)(Word & 0x00ff); \
4020 + pByte[0] = (SK_U8)(Word & 0x00ff); \
4021 pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \
4022 - SK_IN16((IoC), GMA((Mac), (Reg+4)), &Word); \
4023 - pByte[2] = (SK_U8)(Word & 0x00ff); \
4024 + SK_IN16((IoC), GMA((Mac), (Reg) + 4), &Word); \
4025 + pByte[2] = (SK_U8)(Word & 0x00ff); \
4026 pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \
4027 - SK_IN16((IoC), GMA((Mac), (Reg+8)), &Word); \
4028 - pByte[4] = (SK_U8)(Word & 0x00ff); \
4029 + SK_IN16((IoC), GMA((Mac), (Reg) + 8), &Word); \
4030 + pByte[4] = (SK_U8)(Word & 0x00ff); \
4031 pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \
4032 - SK_IN16((IoC), GMA((Mac), (Reg+12)), &Word); \
4033 - pByte[6] = (SK_U8)(Word & 0x00ff); \
4034 + SK_IN16((IoC), GMA((Mac), (Reg) + 12), &Word); \
4035 + pByte[6] = (SK_U8)(Word & 0x00ff); \
4036 pByte[7] = (SK_U8)((Word >> 8) & 0x00ff); \
4039 @@ -1956,13 +2895,13 @@
4040 SK_OUT16((IoC), GMA((Mac), (Reg)), (SK_U16) \
4041 (((SK_U16)(pByte[0]) & 0x00ff)| \
4042 (((SK_U16)(pByte[1]) << 8) & 0xff00))); \
4043 - SK_OUT16((IoC), GMA((Mac), (Reg+4)), (SK_U16) \
4044 + SK_OUT16((IoC), GMA((Mac), (Reg) + 4), (SK_U16) \
4045 (((SK_U16)(pByte[2]) & 0x00ff)| \
4046 (((SK_U16)(pByte[3]) << 8) & 0xff00))); \
4047 - SK_OUT16((IoC), GMA((Mac), (Reg+8)), (SK_U16) \
4048 + SK_OUT16((IoC), GMA((Mac), (Reg) + 8), (SK_U16) \
4049 (((SK_U16)(pByte[4]) & 0x00ff)| \
4050 (((SK_U16)(pByte[5]) << 8) & 0xff00))); \
4051 - SK_OUT16((IoC), GMA((Mac), (Reg+12)), (SK_U16) \
4052 + SK_OUT16((IoC), GMA((Mac), (Reg) + 12), (SK_U16) \
4053 (((SK_U16)(pByte[6]) & 0x00ff)| \
4054 (((SK_U16)(pByte[7]) << 8) & 0xff00))); \
4056 @@ -1980,8 +2919,8 @@
4057 #define SK_PHY_BCOM 1 /* Broadcom BCM5400 */
4058 #define SK_PHY_LONE 2 /* Level One LXT1000 */
4059 #define SK_PHY_NAT 3 /* National DP83891 */
4060 -#define SK_PHY_MARV_COPPER 4 /* Marvell 88E1011S */
4061 -#define SK_PHY_MARV_FIBER 5 /* Marvell 88E1011S working on fiber */
4062 +#define SK_PHY_MARV_COPPER 4 /* Marvell 88E1040S */
4063 +#define SK_PHY_MARV_FIBER 5 /* Marvell 88E1040S working on fiber */
4066 * PHY addresses (bits 12..8 of PHY address reg)
4067 @@ -2010,30 +2949,30 @@
4069 * usage: PHY_READ(IoC, pPort, MAC_1, PHY_CTRL, Value);
4070 * Warning: a PHY_READ on an uninitialized PHY (PHY still in reset) never
4071 - * comes back. This is checked in DEBUG mode.
4072 + * comes back. This is checked in DEBUG mode.
4075 #define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) { \
4079 XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \
4080 XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
4081 if ((pPort)->PhyType != SK_PHY_XMAC) { \
4084 XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
4085 } while ((Mmu & XM_MMU_PHY_RDY) == 0); \
4086 XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
4091 #define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) { \
4096 XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \
4097 XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
4098 if ((pPort)->PhyType != SK_PHY_XMAC) { \
4101 XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
4103 if (__i > 100000) { \
4104 @@ -2044,7 +2983,7 @@
4106 } while ((Mmu & XM_MMU_PHY_RDY) == 0); \
4107 XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
4113 @@ -2052,17 +2991,17 @@
4116 if ((pPort)->PhyType != SK_PHY_XMAC) { \
4119 XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
4120 } while ((Mmu & XM_MMU_PHY_BUSY) != 0); \
4123 XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \
4124 XM_OUT16((IoC), (Mac), XM_PHY_DATA, (Val)); \
4125 if ((pPort)->PhyType != SK_PHY_XMAC) { \
4128 XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
4129 } while ((Mmu & XM_MMU_PHY_BUSY) != 0); \
4135 @@ -2071,12 +3010,14 @@
4136 * Use this macro to access PCI config register from the I/O space.
4139 + * pAC Pointer to adapter context
4140 * Addr PCI configuration register to access.
4141 * Values: PCI_VENDOR_ID ... PCI_VPD_ADR_REG,
4143 - * usage SK_IN16(pAC, PCI_C(PCI_VENDOR_ID), pVal);
4144 + * usage SK_IN16(IoC, PCI_C(pAC, PCI_VENDOR_ID), pVal);
4146 -#define PCI_C(Addr) (B7_CFG_SPC + (Addr)) /* PCI Config Space */
4147 +#define PCI_C(p, Addr) \
4148 + (((CHIP_ID_YUKON_2(p)) ? Y2_CFG_SPC : B7_CFG_SPC) + (Addr))
4151 * Macro SK_HW_ADDR(Base, Addr)
4152 @@ -2088,7 +3029,7 @@
4153 * Addr Address offset
4155 * usage: May be used in SK_INxx and SK_OUTxx macros
4156 - * #define SK_IN8(pAC, Addr, pVal) ...\
4157 + * #define SK_IN8(IoC, Addr, pVal) ...\
4158 * *pVal = (SK_U8)inp(SK_HW_ADDR(pAC->Hw.Iop, Addr)))
4160 #ifdef SK_MEM_MAPPED_IO
4161 @@ -2107,20 +3048,31 @@
4163 * pAC Pointer to adapter context struct
4164 * IoC I/O context needed for SK I/O macros
4165 - * Port Port number
4166 + * Port Port number
4167 * Mode Mode to set for this LED
4169 #define SK_HWAC_LINK_LED(pAC, IoC, Port, Mode) \
4170 SK_OUT8(IoC, MR_ADDR(Port, LNK_LED_REG), Mode);
4172 +#define SK_SET_GP_IO(IoC, Bit) { \
4174 + SK_IN32(IoC, B2_GP_IO, &DWord); \
4175 + DWord |= ((GP_DIR_0 | GP_IO_0) << (Bit));\
4176 + SK_OUT32(IoC, B2_GP_IO, DWord); \
4179 -/* typedefs *******************************************************************/
4181 +#define SK_CLR_GP_IO(IoC, Bit) { \
4183 + SK_IN32(IoC, B2_GP_IO, &DWord); \
4184 + DWord &= ~((GP_DIR_0 | GP_IO_0) << (Bit));\
4185 + SK_OUT32(IoC, B2_GP_IO, DWord); \
4188 -/* function prototypes ********************************************************/
4189 +#define SK_GE_PCI_FIFO_SIZE 1600 /* PCI FIFO Size */
4193 #endif /* __cplusplus */
4195 #endif /* __INC_SKGEHW_H */
4197 diff -ruN linux/drivers/net/sk98lin/h/skgehwt.h linux-new/drivers/net/sk98lin/h/skgehwt.h
4198 --- linux/drivers/net/sk98lin/h/skgehwt.h 2006-09-20 05:42:06.000000000 +0200
4199 +++ linux-new/drivers/net/sk98lin/h/skgehwt.h 2006-07-28 14:13:54.000000000 +0200
4203 * Project: Gigabit Ethernet Adapters, Event Scheduler Module
4204 - * Version: $Revision$
4206 + * Version: $Revision$
4208 * Purpose: Defines for the hardware timer functions
4210 ******************************************************************************/
4212 /******************************************************************************
4215 * (C)Copyright 1998-2002 SysKonnect GmbH.
4216 * (C)Copyright 2002-2003 Marvell.
4219 * (at your option) any later version.
4221 * The information in this file is provided "AS IS" without warranty.
4224 ******************************************************************************/
4226 diff -ruN linux/drivers/net/sk98lin/h/skgei2c.h linux-new/drivers/net/sk98lin/h/skgei2c.h
4227 --- linux/drivers/net/sk98lin/h/skgei2c.h 2006-09-20 05:42:06.000000000 +0200
4228 +++ linux-new/drivers/net/sk98lin/h/skgei2c.h 1970-01-01 01:00:00.000000000 +0100
4230 -/******************************************************************************
4233 - * Project: Gigabit Ethernet Adapters, TWSI-Module
4234 - * Version: $Revision$
4236 - * Purpose: Special defines for TWSI
4238 - ******************************************************************************/
4240 -/******************************************************************************
4242 - * (C)Copyright 1998-2002 SysKonnect.
4243 - * (C)Copyright 2002-2003 Marvell.
4245 - * This program is free software; you can redistribute it and/or modify
4246 - * it under the terms of the GNU General Public License as published by
4247 - * the Free Software Foundation; either version 2 of the License, or
4248 - * (at your option) any later version.
4250 - * The information in this file is provided "AS IS" without warranty.
4252 - ******************************************************************************/
4255 - * SKGEI2C.H contains all SK-98xx specific defines for the TWSI handling
4258 -#ifndef _INC_SKGEI2C_H_
4259 -#define _INC_SKGEI2C_H_
4262 - * Macros to access the B2_I2C_CTRL
4264 -#define SK_I2C_CTL(IoC, flag, dev, dev_size, reg, burst) \
4265 - SK_OUT32(IoC, B2_I2C_CTRL,\
4266 - (flag ? 0x80000000UL : 0x0L) | \
4267 - (((SK_U32)reg << 16) & I2C_ADDR) | \
4268 - (((SK_U32)dev << 9) & I2C_DEV_SEL) | \
4269 - (dev_size & I2C_DEV_SIZE) | \
4270 - ((burst << 4) & I2C_BURST_LEN))
4272 -#define SK_I2C_STOP(IoC) { \
4274 - SK_IN32(IoC, B2_I2C_CTRL, &I2cCtrl); \
4275 - SK_OUT32(IoC, B2_I2C_CTRL, I2cCtrl | I2C_STOP); \
4278 -#define SK_I2C_GET_CTL(IoC, pI2cCtrl) SK_IN32(IoC, B2_I2C_CTRL, pI2cCtrl)
4281 - * Macros to access the TWSI SW Registers
4283 -#define SK_I2C_SET_BIT(IoC, SetBits) { \
4285 - SK_IN8(IoC, B2_I2C_SW, &OrgBits); \
4286 - SK_OUT8(IoC, B2_I2C_SW, OrgBits | (SK_U8)(SetBits)); \
4289 -#define SK_I2C_CLR_BIT(IoC, ClrBits) { \
4291 - SK_IN8(IoC, B2_I2C_SW, &OrgBits); \
4292 - SK_OUT8(IoC, B2_I2C_SW, OrgBits & ~((SK_U8)(ClrBits))); \
4295 -#define SK_I2C_GET_SW(IoC, pI2cSw) SK_IN8(IoC, B2_I2C_SW, pI2cSw)
4298 - * define the possible sensor states
4300 -#define SK_SEN_IDLE 0 /* Idle: sensor not read */
4301 -#define SK_SEN_VALUE 1 /* Value Read cycle */
4302 -#define SK_SEN_VALEXT 2 /* Extended Value Read cycle */
4305 - * Conversion factor to convert read Voltage sensor to milli Volt
4306 - * Conversion factor to convert read Temperature sensor to 10th degree Celsius
4308 -#define SK_LM80_VT_LSB 22 /* 22mV LSB resolution */
4309 -#define SK_LM80_TEMP_LSB 10 /* 1 degree LSB resolution */
4310 -#define SK_LM80_TEMPEXT_LSB 5 /* 0.5 degree LSB resolution for ext. val. */
4313 - * formula: counter = (22500*60)/(rpm * divisor * pulses/2)
4314 - * assuming: 6500rpm, 4 pulses, divisor 1
4316 -#define SK_LM80_FAN_FAKTOR ((22500L*60)/(1*2))
4319 - * Define sensor management data
4320 - * Maximum is reached on Genesis copper dual port and Yukon-64
4321 - * Board specific maximum is in pAC->I2c.MaxSens
4323 -#define SK_MAX_SENSORS 8 /* maximal no. of installed sensors */
4324 -#define SK_MIN_SENSORS 5 /* minimal no. of installed sensors */
4327 - * To watch the state machine (SM) use the timer in two ways
4328 - * instead of one as hitherto
4330 -#define SK_TIMER_WATCH_SM 0 /* Watch the SM to finish in a spec. time */
4331 -#define SK_TIMER_NEW_GAUGING 1 /* Start a new gauging when timer expires */
4334 - * Defines for the individual thresholds
4337 -/* Temperature sensor */
4338 -#define SK_SEN_TEMP_HIGH_ERR 800 /* Temperature High Err Threshold */
4339 -#define SK_SEN_TEMP_HIGH_WARN 700 /* Temperature High Warn Threshold */
4340 -#define SK_SEN_TEMP_LOW_WARN 100 /* Temperature Low Warn Threshold */
4341 -#define SK_SEN_TEMP_LOW_ERR 0 /* Temperature Low Err Threshold */
4343 -/* VCC which should be 5 V */
4344 -#define SK_SEN_PCI_5V_HIGH_ERR 5588 /* Voltage PCI High Err Threshold */
4345 -#define SK_SEN_PCI_5V_HIGH_WARN 5346 /* Voltage PCI High Warn Threshold */
4346 -#define SK_SEN_PCI_5V_LOW_WARN 4664 /* Voltage PCI Low Warn Threshold */
4347 -#define SK_SEN_PCI_5V_LOW_ERR 4422 /* Voltage PCI Low Err Threshold */
4350 - * VIO may be 5 V or 3.3 V. Initialization takes two parts:
4351 - * 1. Initialize lowest lower limit and highest higher limit.
4352 - * 2. After the first value is read correct the upper or the lower limit to
4353 - * the appropriate C constant.
4355 - * Warning limits are +-5% of the exepected voltage.
4356 - * Error limits are +-10% of the expected voltage.
4359 -/* Bug fix AF: 16.Aug.2001: Correct the init base of LM80 sensor */
4361 -#define SK_SEN_PCI_IO_5V_HIGH_ERR 5566 /* + 10% V PCI-IO High Err Threshold */
4362 -#define SK_SEN_PCI_IO_5V_HIGH_WARN 5324 /* + 5% V PCI-IO High Warn Threshold */
4364 -#define SK_SEN_PCI_IO_5V_LOW_WARN 4686 /* - 5% V PCI-IO Low Warn Threshold */
4365 -#define SK_SEN_PCI_IO_5V_LOW_ERR 4444 /* - 10% V PCI-IO Low Err Threshold */
4367 -#define SK_SEN_PCI_IO_RANGE_LIMITER 4000 /* 4000 mV range delimiter */
4369 -/* correction values for the second pass */
4370 -#define SK_SEN_PCI_IO_3V3_HIGH_ERR 3850 /* + 15% V PCI-IO High Err Threshold */
4371 -#define SK_SEN_PCI_IO_3V3_HIGH_WARN 3674 /* + 10% V PCI-IO High Warn Threshold */
4373 -#define SK_SEN_PCI_IO_3V3_LOW_WARN 2926 /* - 10% V PCI-IO Low Warn Threshold */
4374 -#define SK_SEN_PCI_IO_3V3_LOW_ERR 2772 /* - 15% V PCI-IO Low Err Threshold */
4379 -#define SK_SEN_VDD_HIGH_ERR 3630 /* Voltage ASIC High Err Threshold */
4380 -#define SK_SEN_VDD_HIGH_WARN 3476 /* Voltage ASIC High Warn Threshold */
4381 -#define SK_SEN_VDD_LOW_WARN 3146 /* Voltage ASIC Low Warn Threshold */
4382 -#define SK_SEN_VDD_LOW_ERR 2970 /* Voltage ASIC Low Err Threshold */
4385 - * PHY PLL 3V3 voltage
4387 -#define SK_SEN_PLL_3V3_HIGH_ERR 3630 /* Voltage PMA High Err Threshold */
4388 -#define SK_SEN_PLL_3V3_HIGH_WARN 3476 /* Voltage PMA High Warn Threshold */
4389 -#define SK_SEN_PLL_3V3_LOW_WARN 3146 /* Voltage PMA Low Warn Threshold */
4390 -#define SK_SEN_PLL_3V3_LOW_ERR 2970 /* Voltage PMA Low Err Threshold */
4393 - * VAUX (YUKON only)
4395 -#define SK_SEN_VAUX_3V3_HIGH_ERR 3630 /* Voltage VAUX High Err Threshold */
4396 -#define SK_SEN_VAUX_3V3_HIGH_WARN 3476 /* Voltage VAUX High Warn Threshold */
4397 -#define SK_SEN_VAUX_3V3_LOW_WARN 3146 /* Voltage VAUX Low Warn Threshold */
4398 -#define SK_SEN_VAUX_3V3_LOW_ERR 2970 /* Voltage VAUX Low Err Threshold */
4399 -#define SK_SEN_VAUX_0V_WARN_ERR 0 /* if VAUX not present */
4400 -#define SK_SEN_VAUX_RANGE_LIMITER 1000 /* 1000 mV range delimiter */
4405 -#define SK_SEN_PHY_2V5_HIGH_ERR 2750 /* Voltage PHY High Err Threshold */
4406 -#define SK_SEN_PHY_2V5_HIGH_WARN 2640 /* Voltage PHY High Warn Threshold */
4407 -#define SK_SEN_PHY_2V5_LOW_WARN 2376 /* Voltage PHY Low Warn Threshold */
4408 -#define SK_SEN_PHY_2V5_LOW_ERR 2222 /* Voltage PHY Low Err Threshold */
4411 - * ASIC Core 1V5 voltage (YUKON only)
4413 -#define SK_SEN_CORE_1V5_HIGH_ERR 1650 /* Voltage ASIC Core High Err Threshold */
4414 -#define SK_SEN_CORE_1V5_HIGH_WARN 1575 /* Voltage ASIC Core High Warn Threshold */
4415 -#define SK_SEN_CORE_1V5_LOW_WARN 1425 /* Voltage ASIC Core Low Warn Threshold */
4416 -#define SK_SEN_CORE_1V5_LOW_ERR 1350 /* Voltage ASIC Core Low Err Threshold */
4421 -/* assuming: 6500rpm +-15%, 4 pulses,
4422 - * warning at: 80 %
4426 -#define SK_SEN_FAN_HIGH_ERR 20000 /* FAN Speed High Err Threshold */
4427 -#define SK_SEN_FAN_HIGH_WARN 20000 /* FAN Speed High Warn Threshold */
4428 -#define SK_SEN_FAN_LOW_WARN 5200 /* FAN Speed Low Warn Threshold */
4429 -#define SK_SEN_FAN_LOW_ERR 4550 /* FAN Speed Low Err Threshold */
4432 - * Some Voltages need dynamic thresholds
4434 -#define SK_SEN_DYN_INIT_NONE 0 /* No dynamic init of thresholds */
4435 -#define SK_SEN_DYN_INIT_PCI_IO 10 /* Init PCI-IO with new thresholds */
4436 -#define SK_SEN_DYN_INIT_VAUX 11 /* Init VAUX with new thresholds */
4438 -extern int SkLm80ReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen);
4439 -#endif /* n_INC_SKGEI2C_H */
4440 diff -ruN linux/drivers/net/sk98lin/h/skgeinit.h linux-new/drivers/net/sk98lin/h/skgeinit.h
4441 --- linux/drivers/net/sk98lin/h/skgeinit.h 2006-09-20 05:42:06.000000000 +0200
4442 +++ linux-new/drivers/net/sk98lin/h/skgeinit.h 2006-07-28 14:13:54.000000000 +0200
4446 * Project: Gigabit Ethernet Adapters, Common Modules
4447 - * Version: $Revision$
4449 + * Version: $Revision$
4451 * Purpose: Structures and prototypes for the GE Init Module
4453 ******************************************************************************/
4455 /******************************************************************************
4458 * (C)Copyright 1998-2002 SysKonnect.
4459 - * (C)Copyright 2002-2003 Marvell.
4460 + * (C)Copyright 2002-2006 Marvell.
4462 * This program is free software; you can redistribute it and/or modify
4463 * it under the terms of the GNU General Public License as published by
4464 * the Free Software Foundation; either version 2 of the License, or
4465 * (at your option) any later version.
4467 * The information in this file is provided "AS IS" without warranty.
4470 ******************************************************************************/
4473 #define SK_XMIT_DUR 0x002faf08UL /* 50 ms */
4474 #define SK_BLK_DUR 0x01dcd650UL /* 500 ms */
4476 -#define SK_DPOLL_DEF 0x00ee6b28UL /* 250 ms at 62.5 MHz */
4477 +#define SK_DPOLL_DEF 0x00ee6b28UL /* 250 ms at 62.5 MHz (Genesis) */
4478 +#define SK_DPOLL_DEF_Y2 0x0000124fUL /* 75 us (Yukon-2) */
4480 #define SK_DPOLL_MAX 0x00ffffffUL /* 268 ms at 62.5 MHz */
4481 - /* 215 ms at 78.12 MHz */
4482 + /* 215 ms at 78.12 MHz (Yukon) */
4484 #define SK_FACT_62 100 /* is given in percent */
4485 -#define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */
4486 +#define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */
4487 #define SK_FACT_78 125 /* on YUKON: 78.12 MHz */
4488 +#define SK_FACT_100 161 /* on YUKON-FE: 100 MHz */
4489 +#define SK_FACT_125 202 /* on YUKON-EC: 125 MHz */
4491 /* Timeout values */
4492 #define SK_MAC_TO_53 72 /* MAC arbiter timeout */
4494 #define SK_RB_LLPP_S (10 * 1024) /* Lower Level for small Queues */
4495 #define SK_RB_LLPP_B (16 * 1024) /* Lower Level for big Queues */
4497 +/* Threshold values for Yukon-EC Ultra */
4498 +#define SK_ECU_ULPP 0x0080 /* Upper Pause Threshold (multiples of 8) */
4499 +#define SK_ECU_LLPP 0x0060 /* Lower Pause Threshold (multiples of 8) */
4500 +#define SK_ECU_AE_THR 0x0180 /* Almost Empty Threshold */
4501 +#define SK_ECU_TXFF_LEV 0x01a0 /* Tx BMU FIFO Level */
4503 #ifndef SK_BMU_RX_WM
4504 -#define SK_BMU_RX_WM 0x600 /* BMU Rx Watermark */
4505 +#define SK_BMU_RX_WM 0x600 /* BMU Rx Watermark */
4508 #ifndef SK_BMU_TX_WM
4509 -#define SK_BMU_TX_WM 0x600 /* BMU Tx Watermark */
4510 +#define SK_BMU_TX_WM 0x600 /* BMU Tx Watermark */
4513 +/* performance sensitive drivers should set this define to 0x80 */
4514 +#ifndef SK_BMU_RX_WM_PEX
4515 +#define SK_BMU_RX_WM_PEX 0x600 /* BMU Rx Watermark for PEX */
4518 /* XMAC II Rx High Watermark */
4519 @@ -98,37 +114,31 @@
4520 #define SK_XM_THR_MULL 0x01fb /* .. for multiple link usage */
4521 #define SK_XM_THR_JUMBO 0x03fc /* .. for jumbo frame usage */
4523 -/* values for GIPortUsage */
4524 +/* values for PortUsage */
4525 #define SK_RED_LINK 1 /* redundant link usage */
4526 #define SK_MUL_LINK 2 /* multiple link usage */
4527 #define SK_JUMBO_LINK 3 /* driver uses jumbo frames */
4529 /* Minimum RAM Buffer Rx Queue Size */
4530 -#define SK_MIN_RXQ_SIZE 16 /* 16 kB */
4531 +#define SK_MIN_RXQ_SIZE (((pAC)->GIni.GIYukon2) ? 10 : 16) /* 10/16 kB */
4533 /* Minimum RAM Buffer Tx Queue Size */
4534 -#define SK_MIN_TXQ_SIZE 16 /* 16 kB */
4535 +#define SK_MIN_TXQ_SIZE (((pAC)->GIni.GIYukon2) ? 10 : 16) /* 10/16 kB */
4537 -/* Queue Size units */
4538 -#define QZ_UNITS 0x7
4539 +/* Queue Size units (Genesis/Yukon) */
4543 +/* Queue Size units (Yukon-2) */
4544 +#define QZ_STEP_Y2 1
4546 /* Percentage of queue size from whole memory */
4547 /* 80 % for receive */
4548 -#define RAM_QUOTA_RX 80L
4549 -/* 0% for sync transfer */
4550 -#define RAM_QUOTA_SYNC 0L
4551 +#define RAM_QUOTA_RX 80
4552 +/* 0 % for sync transfer */
4553 +#define RAM_QUOTA_SYNC 0
4554 /* the rest (20%) is taken for async transfer */
4556 -/* Get the rounded queue size in Bytes in 8k steps */
4557 -#define ROUND_QUEUE_SIZE(SizeInBytes) \
4558 - ((((unsigned long) (SizeInBytes) + (QZ_STEP*1024L)-1) / 1024) & \
4561 -/* Get the rounded queue size in KBytes in 8k steps */
4562 -#define ROUND_QUEUE_SIZE_KB(Kilobytes) \
4563 - ROUND_QUEUE_SIZE((Kilobytes) * 1024L)
4565 /* Types of RAM Buffer Queues */
4566 #define SK_RX_SRAM_Q 1 /* small receive queue */
4567 #define SK_RX_BRAM_Q 2 /* big receive queue */
4568 @@ -167,11 +177,11 @@
4571 /* Link Speed Capabilities */
4572 -#define SK_LSPEED_CAP_AUTO (1<<0) /* Automatic resolution */
4573 -#define SK_LSPEED_CAP_10MBPS (1<<1) /* 10 Mbps */
4574 -#define SK_LSPEED_CAP_100MBPS (1<<2) /* 100 Mbps */
4575 -#define SK_LSPEED_CAP_1000MBPS (1<<3) /* 1000 Mbps */
4576 -#define SK_LSPEED_CAP_INDETERMINATED (1<<4) /* indeterminated */
4577 +#define SK_LSPEED_CAP_AUTO BIT_0S /* Automatic resolution */
4578 +#define SK_LSPEED_CAP_10MBPS BIT_1S /* 10 Mbps */
4579 +#define SK_LSPEED_CAP_100MBPS BIT_2S /* 100 Mbps */
4580 +#define SK_LSPEED_CAP_1000MBPS BIT_3S /* 1000 Mbps */
4581 +#define SK_LSPEED_CAP_INDETERMINATED BIT_4S /* indeterminated */
4583 /* Link Speed Parameter */
4584 #define SK_LSPEED_AUTO 1 /* Automatic resolution */
4585 @@ -189,11 +199,11 @@
4588 /* Link Capability Parameter */
4589 -#define SK_LMODE_CAP_HALF (1<<0) /* Half Duplex Mode */
4590 -#define SK_LMODE_CAP_FULL (1<<1) /* Full Duplex Mode */
4591 -#define SK_LMODE_CAP_AUTOHALF (1<<2) /* AutoHalf Duplex Mode */
4592 -#define SK_LMODE_CAP_AUTOFULL (1<<3) /* AutoFull Duplex Mode */
4593 -#define SK_LMODE_CAP_INDETERMINATED (1<<4) /* indeterminated */
4594 +#define SK_LMODE_CAP_HALF BIT_0S /* Half Duplex Mode */
4595 +#define SK_LMODE_CAP_FULL BIT_1S /* Full Duplex Mode */
4596 +#define SK_LMODE_CAP_AUTOHALF BIT_2S /* AutoHalf Duplex Mode */
4597 +#define SK_LMODE_CAP_AUTOFULL BIT_3S /* AutoFull Duplex Mode */
4598 +#define SK_LMODE_CAP_INDETERMINATED BIT_4S /* indeterminated */
4600 /* Link Mode Current State */
4601 #define SK_LMODE_STAT_UNKNOWN 1 /* Unknown Duplex Mode */
4603 #define SK_LMODE_STAT_INDETERMINATED 6 /* indeterminated */
4605 /* Flow Control Mode Parameter (and capabilities) */
4606 -#define SK_FLOW_MODE_NONE 1 /* No Flow-Control */
4607 +#define SK_FLOW_MODE_NONE 1 /* No Flow Control */
4608 #define SK_FLOW_MODE_LOC_SEND 2 /* Local station sends PAUSE */
4609 #define SK_FLOW_MODE_SYMMETRIC 3 /* Both stations may send PAUSE */
4610 #define SK_FLOW_MODE_SYM_OR_REM 4 /* Both stations may send PAUSE or
4611 @@ -220,10 +230,10 @@
4612 #define SK_FLOW_STAT_INDETERMINATED 5 /* indeterminated */
4614 /* Master/Slave Mode Capabilities */
4615 -#define SK_MS_CAP_AUTO (1<<0) /* Automatic resolution */
4616 -#define SK_MS_CAP_MASTER (1<<1) /* This station is master */
4617 -#define SK_MS_CAP_SLAVE (1<<2) /* This station is slave */
4618 -#define SK_MS_CAP_INDETERMINATED (1<<3) /* indeterminated */
4619 +#define SK_MS_CAP_AUTO BIT_0S /* Automatic resolution */
4620 +#define SK_MS_CAP_MASTER BIT_1S /* This station is master */
4621 +#define SK_MS_CAP_SLAVE BIT_2S /* This station is slave */
4622 +#define SK_MS_CAP_INDETERMINATED BIT_3S /* indeterminated */
4624 /* Set Master/Slave Mode Parameter (and capabilities) */
4625 #define SK_MS_MODE_AUTO 1 /* Automatic resolution */
4626 @@ -238,25 +248,25 @@
4627 #define SK_MS_STAT_FAULT 4 /* M/S resolution failed */
4628 #define SK_MS_STAT_INDETERMINATED 5 /* indeterminated */
4630 -/* parameter 'Mode' when calling SkXmSetRxCmd() */
4631 -#define SK_STRIP_FCS_ON (1<<0) /* Enable FCS stripping of Rx frames */
4632 -#define SK_STRIP_FCS_OFF (1<<1) /* Disable FCS stripping of Rx frames */
4633 -#define SK_STRIP_PAD_ON (1<<2) /* Enable pad byte stripping of Rx fr */
4634 -#define SK_STRIP_PAD_OFF (1<<3) /* Disable pad byte stripping of Rx fr */
4635 -#define SK_LENERR_OK_ON (1<<4) /* Don't chk fr for in range len error */
4636 -#define SK_LENERR_OK_OFF (1<<5) /* Check frames for in range len error */
4637 -#define SK_BIG_PK_OK_ON (1<<6) /* Don't set Rx Error bit for big frames */
4638 -#define SK_BIG_PK_OK_OFF (1<<7) /* Set Rx Error bit for big frames */
4639 -#define SK_SELF_RX_ON (1<<8) /* Enable Rx of own packets */
4640 -#define SK_SELF_RX_OFF (1<<9) /* Disable Rx of own packets */
4641 +/* parameter 'Mode' when calling SkMacSetRxCmd() */
4642 +#define SK_STRIP_FCS_ON BIT_0S /* Enable FCS stripping of Rx frames */
4643 +#define SK_STRIP_FCS_OFF BIT_1S /* Disable FCS stripping of Rx frames */
4644 +#define SK_STRIP_PAD_ON BIT_2S /* Enable pad byte stripping of Rx fr */
4645 +#define SK_STRIP_PAD_OFF BIT_3S /* Disable pad byte stripping of Rx fr */
4646 +#define SK_LENERR_OK_ON BIT_4S /* Don't chk fr for in range len error */
4647 +#define SK_LENERR_OK_OFF BIT_5S /* Check frames for in range len error */
4648 +#define SK_BIG_PK_OK_ON BIT_6S /* Don't set Rx Error bit for big frames */
4649 +#define SK_BIG_PK_OK_OFF BIT_7S /* Set Rx Error bit for big frames */
4650 +#define SK_SELF_RX_ON BIT_8S /* Enable Rx of own packets */
4651 +#define SK_SELF_RX_OFF BIT_9S /* Disable Rx of own packets */
4653 /* parameter 'Para' when calling SkMacSetRxTxEn() */
4654 -#define SK_MAC_LOOPB_ON (1<<0) /* Enable MAC Loopback Mode */
4655 -#define SK_MAC_LOOPB_OFF (1<<1) /* Disable MAC Loopback Mode */
4656 -#define SK_PHY_LOOPB_ON (1<<2) /* Enable PHY Loopback Mode */
4657 -#define SK_PHY_LOOPB_OFF (1<<3) /* Disable PHY Loopback Mode */
4658 -#define SK_PHY_FULLD_ON (1<<4) /* Enable GMII Full Duplex */
4659 -#define SK_PHY_FULLD_OFF (1<<5) /* Disable GMII Full Duplex */
4660 +#define SK_MAC_LOOPB_ON BIT_0S /* Enable MAC Loopback Mode */
4661 +#define SK_MAC_LOOPB_OFF BIT_1S /* Disable MAC Loopback Mode */
4662 +#define SK_PHY_LOOPB_ON BIT_2S /* Enable PHY Loopback Mode */
4663 +#define SK_PHY_LOOPB_OFF BIT_3S /* Disable PHY Loopback Mode */
4664 +#define SK_PHY_FULLD_ON BIT_4S /* Enable GMII Full Duplex */
4665 +#define SK_PHY_FULLD_OFF BIT_5S /* Disable GMII Full Duplex */
4667 /* States of PState */
4668 #define SK_PRT_RESET 0 /* the port is reset */
4669 @@ -266,18 +276,25 @@
4671 /* PHY power down modes */
4672 #define PHY_PM_OPERATIONAL_MODE 0 /* PHY operational mode */
4673 -#define PHY_PM_DEEP_SLEEP 1 /* coma mode --> minimal power */
4674 +#define PHY_PM_DEEP_SLEEP 1 /* Coma mode --> minimal power */
4675 #define PHY_PM_IEEE_POWER_DOWN 2 /* IEEE 22.2.4.1.5 compl. power down */
4676 -#define PHY_PM_ENERGY_DETECT 3 /* energy detect */
4677 -#define PHY_PM_ENERGY_DETECT_PLUS 4 /* energy detect plus */
4678 +#define PHY_PM_ENERGY_DETECT 3 /* Energy detect */
4679 +#define PHY_PM_ENERGY_DETECT_PLUS 4 /* Energy detect plus */
4681 +/* PCI Bus Types */
4682 +#define SK_PCI_BUS BIT_0S /* normal PCI bus */
4683 +#define SK_PCIX_BUS BIT_1S /* PCI-X bus */
4684 +#define SK_PEX_BUS BIT_2S /* PCI-Express bus */
4686 /* Default receive frame limit for Workaround of XMAC Errata */
4687 #define SK_DEF_RX_WA_LIM SK_CONSTU64(100)
4689 /* values for GILedBlinkCtrl (LED Blink Control) */
4690 -#define SK_ACT_LED_BLINK (1<<0) /* Active LED blinking */
4691 -#define SK_DUP_LED_NORMAL (1<<1) /* Duplex LED normal */
4692 -#define SK_LED_LINK100_ON (1<<2) /* Link 100M LED on */
4693 +#define SK_ACT_LED_BLINK BIT_0S /* Active LED blinking */
4694 +#define SK_DUP_LED_NORMAL BIT_1S /* Duplex LED normal */
4695 +#define SK_LED_LINK100_ON BIT_2S /* Link 100M LED on */
4696 +#define SK_DUAL_LED_ACT_LNK BIT_3S /* Dual LED ACT/LNK configuration */
4697 +#define SK_LED_LINK_MUX_P60 BIT_4S /* Link LED muxed to pin 60 */
4699 /* Link Partner Status */
4700 #define SK_LIPA_UNKNOWN 0 /* Link partner is in unknown state */
4701 @@ -290,18 +307,187 @@
4702 /* Max. Auto-neg. timeouts before link detection in sense mode is reset */
4703 #define SK_MAX_ANEG_TO 10 /* Max. 10 times the sense mode is reset */
4706 +/******************************************************************************
4708 + * HW_FEATURE() macro
4711 +/* DWORD 0: Features */
4712 +#define HWF_FORCE_AUTO_NEG 0x04000000UL /* Force Auto-Negotiation */
4713 +#define HWF_CLK_GATING_ENABLE 0x02000000UL /* Enable Clock Gating */
4714 +#define HWF_RED_CORE_CLK_SUP 0x01000000UL /* Reduced Core Clock supp. */
4715 +#define HWF_RESTORE_LOST_BARS 0x00800000UL /* save and restore PCI bars */
4716 +#define HWF_ASPM_SWITCHING 0x00400000UL /* activate ASPM feature */
4718 +/*-RMV- DWORD 1: Deviations */
4719 +#define HWF_WA_DEV_4200 0x10200000UL /*-RMV- 4.200 (D3 Blue Screen)*/
4720 +#define HWF_WA_DEV_4185CS 0x10100000UL /*-RMV- 4.185 (ECU 100 CS cal)*/
4721 +#define HWF_WA_DEV_4185 0x10080000UL /*-RMV- 4.185 (ECU Tx h check)*/
4722 +#define HWF_WA_DEV_4167 0x10040000UL /*-RMV- 4.167 (Rx OvSize Hang)*/
4723 +#define HWF_WA_DEV_4152 0x10020000UL /*-RMV- 4.152 (RSS issue) */
4724 +#define HWF_WA_DEV_4115 0x10010000UL /*-RMV- 4.115 (Rx MAC FIFO) */
4725 +#define HWF_WA_DEV_4109 0x10008000UL /*-RMV- 4.109 (BIU hang) */
4726 +#define HWF_WA_DEV_483 0x10004000UL /*-RMV- 4.83 (Rx TCP wrong) */
4727 +#define HWF_WA_DEV_479 0x10002000UL /*-RMV- 4.79 (Rx BMU hang II) */
4728 +#define HWF_WA_DEV_472 0x10001000UL /*-RMV- 4.72 (GPHY2 MDC clk) */
4729 +#define HWF_WA_DEV_463 0x10000800UL /*-RMV- 4.63 (Rx BMU hang I) */
4730 +#define HWF_WA_DEV_427 0x10000400UL /*-RMV- 4.27 (Tx Done Rep) */
4731 +#define HWF_WA_DEV_42 0x10000200UL /*-RMV- 4.2 (pref unit burst) */
4732 +#define HWF_WA_DEV_46 0x10000100UL /*-RMV- 4.6 (CPU crash II) */
4733 +#define HWF_WA_DEV_43_418 0x10000080UL /*-RMV- 4.3 & 4.18 (PCI unexp */
4734 + /*-RMV- compl&Stat BMU deadl) */
4735 +#define HWF_WA_DEV_420 0x10000040UL /*-RMV- 4.20 (Status BMU ov) */
4736 +#define HWF_WA_DEV_423 0x10000020UL /*-RMV- 4.23 (TCP Segm Hang) */
4737 +#define HWF_WA_DEV_424 0x10000010UL /*-RMV- 4.24 (MAC reg overwr) */
4738 +#define HWF_WA_DEV_425 0x10000008UL /*-RMV- 4.25 (Magic packet */
4739 + /*-RMV- with odd offset) */
4740 +#define HWF_WA_DEV_428 0x10000004UL /*-RMV- 4.28 (Poll-U &BigEndi)*/
4741 +#define HWF_WA_FIFO_FLUSH_YLA0 0x10000002UL /*-RMV- dis Rx GMAC FIFO Flush*/
4742 + /*-RMV- for Yu-L Rev. A0 only */
4743 +#define HWF_WA_COMA_MODE 0x10000001UL /*-RMV- Coma Mode WA req */
4745 +/* DWORD 2: Real HW features not settable from outside */
4748 +#define HWF_SYNC_TX_SUP 0x20800000UL /* Synch. Tx Queue available */
4749 +#define HWF_SINGLE_PORT_DEVICE 0x20400000UL /* Device has only one LAN IF */
4750 +#define HWF_JUMBO_FRAMES_SUP 0x20200000UL /* Jumbo Frames supported */
4751 +#define HWF_TX_TCP_CSUM_SUP 0x20100000UL /* TCP Tx checksum supported */
4752 +#define HWF_TX_UDP_CSUM_SUP 0x20080000UL /* UDP Tx checksum supported */
4753 +#define HWF_RX_CSUM_SUP 0x20040000UL /* RX checksum supported */
4754 +#define HWF_TCP_SEGM_SUP 0x20020000UL /* TCP segmentation supported */
4755 +#define HWF_RSS_HASH_SUP 0x20010000UL /* RSS Hash supported */
4756 +#define HWF_PORT_VLAN_SUP 0x20008000UL /* VLAN can be config per port*/
4757 +#define HWF_ROLE_PARAM_SUP 0x20004000UL /* Role parameter supported */
4758 +#define HWF_LOW_PMODE_SUP 0x20002000UL /* Low Power Mode supported */
4759 +#define HWF_ENERGIE_DEMO_SUP 0x20001000UL /* Energy Detect mode supp. */
4760 +#define HWF_SPEED1000_SUP 0x20000800UL /* Line Speed 1000 supported */
4761 +#define HWF_SPEED100_SUP 0x20000400UL /* Line Speed 100 supported */
4762 +#define HWF_SPEED10_SUP 0x20000200UL /* Line Speed 10 supported */
4763 +#define HWF_AUTONEGSENSE_SUP 0x20000100UL /* Autoneg Sense supported */
4764 +#define HWF_PHY_LOOPB_MD_SUP 0x20000080UL /* PHY loopback mode supp. */
4765 +#define HWF_ASF_SUP 0x20000040UL /* ASF support possible */
4766 +#define HWF_QS_STEPS_1KB 0x20000020UL /* The Rx/Tx queues can be */
4767 + /* configured with 1 kB res. */
4768 +#define HWF_OWN_RAM_PER_PORT 0x20000010UL /* Each port has a separate */
4770 +#define HWF_MIN_LED_IF 0x20000008UL /* Minimal LED interface */
4771 + /* (e.g. for Yukon-EC) */
4772 +#define HWF_LIST_ELEMENTS_USED 0x20000004UL /* HW uses list elements */
4773 + /* (otherwise desc. are used) */
4774 +#define HWF_GMAC_INSIDE 0x20000002UL /* Device contains GMAC */
4775 +#define HWF_TWSI_PRESENT 0x20000001UL /* TWSI sensor bus present */
4778 +/* DWORD 3: still unused */
4782 + * HW_FEATURE() - returns whether the feature is serviced or not
4784 +#define HW_FEATURE(pAC, ReqFeature) \
4785 + (((pAC)->GIni.HwF.Features[((ReqFeature) & 0x30000000UL) >> 28] &\
4786 + ((ReqFeature) & 0x0fffffffUL)) != 0)
4788 +#define HW_FEAT_LIST 0
4789 +#define HW_DEV_LIST 1
4790 +#define HW_FEAT_LIST_2 2
4792 +#define SET_HW_FEATURE_MASK(pAC, List, OffMaskValue, OnMaskValue) { \
4793 + if ((List) == HW_FEAT_LIST || (List) == HW_DEV_LIST) { \
4794 + (pAC)->GIni.HwF.OffMask[List] = (OffMaskValue); \
4795 + (pAC)->GIni.HwF.OnMask[List] = (OnMaskValue); \
4799 +/* driver access macros for GIni structure ***********************************/
4801 +#define CHIP_ID_YUKON_2(pAC) ((pAC)->GIni.GIYukon2)
4803 +#define HW_SYNC_TX_SUPPORTED(pAC) \
4804 + ((pAC)->GIni.GIChipId != CHIP_ID_YUKON_EC && \
4805 + (pAC)->GIni.GIChipId != CHIP_ID_YUKON_FE && \
4806 + (pAC)->GIni.GIChipId != CHIP_ID_YUKON_EC_U)
4808 +#define HW_MS_TO_TICKS(pAC, MsTime) \
4809 + ((MsTime) * (62500L/100) * (pAC)->GIni.GIHstClkFact)
4811 +#define HW_IS_8056(pAC) \
4812 + ((pAC)->GIni.GIChipId == CHIP_ID_YUKON_EC_U && \
4813 + (pAC)->GIni.GIChipRev == CHIP_REV_YU_EC_U_A1 && \
4814 + (pAC)->GIni.GIChipCap == 2 && \
4815 + !HW_FEATURE(pAC, HWF_WA_DEV_4200))
4818 +/* still under construction */
4819 +#define HW_IS_SINGLE_PORT(pAC) ((pAC)->GIni.GIMacsFound == 1)
4820 +#define HW_NUMBER_OF_PORTS(pAC) ((pAC)->GIni.GIMacsFound)
4822 +#define HW_TX_UDP_CSUM_SUPPORTED(pAC) \
4823 + ((((pAC)->GIni.GIChipId >= CHIP_ID_YUKON) && ((pAC)->GIni.GIChipRev != 0))
4825 +#define HW_DEFAULT_LINESPEED(pAC) \
4826 + ((!(pAC)->GIni.GIGenesis && (pAC)->GIni.GICopperType) ? \
4827 + SK_LSPEED_AUTO : SK_LSPEED_1000MBPS)
4829 +#define HW_ROLE_PARAM_SUPPORTED(pAC) ((pAC)->GIni.GICopperType)
4831 +#define HW_SPEED1000_SUPPORTED(pAC, Port) \
4832 + ((pAC)->GIni.GP[Port].PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS)
4834 +#define HW_SPEED100_SUPPORTED(pAC, Port) \
4835 + ((pAC)->GIni.GP[Port].PLinkSpeedCap & SK_LSPEED_CAP_100MBPS)
4837 +#define HW_SPEED10_SUPPORTED(pAC, Port) \
4838 + ((pAC)->GIni.GP[Port].PLinkSpeedCap & SK_LSPEED_CAP_10MBPS)
4840 +#define HW_AUTONEGSENSE_SUPPORTED(pAC) ((pAC)->GIni.GP[0].PhyType==SK_PHY_XMAC)
4842 +#define HW_FREQ_TO_CARD_TICKS(pAC, AdapterClkSpeed, Freq) \
4843 + (((AdapterClkSpeed / 100) * (pAC)->GIni.GIHstClkFact) / Freq)
4845 +#define HW_IS_LINK_UP(pAC, Port) ((pAC)->GIni.GP[Port].PHWLinkUp)
4846 +#define HW_LINK_SPEED_USED(pAC, Port) ((pAC)->GIni.GP[Port].PLinkSpeedUsed)
4847 +#define HW_RAM_SIZE(pAC) ((pAC)->GIni.GIRamSize)
4849 +#define HW_PHY_LP_MODE_SUPPORTED(pAC) (pAC0->???
4850 +#define HW_ASF_ACTIVE(pAC) ???
4851 +#define RAWIO_OUT32(pAC, pAC->RegIrqMask, pAC->GIni.GIValIrqMask)...
4853 +/* macro to check whether Tx checksum is supported */
4854 +#define HW_TX_CSUM_SUPPORTED(pAC) ((pAC)->GIni.GIChipId != CHIP_ID_GENESIS)
4856 +BMU_UDP_CHECK : BMU_TCP_CHECK;
4858 +/* macro for - Own Bit mirrored to DWORD7 (Yukon LP receive descriptor) */
4862 /* structures *****************************************************************/
4865 + * HW Feature structure
4867 +typedef struct s_HwFeatures {
4868 + SK_U32 Features[4]; /* Feature list */
4869 + SK_U32 OffMask[4]; /* Off Mask */
4870 + SK_U32 OnMask[4]; /* On Mask */
4874 * MAC specific functions
4876 typedef struct s_GeMacFunc {
4877 - int (*pFnMacUpdateStats)(SK_AC *pAC, SK_IOC IoC, unsigned int Port);
4878 - int (*pFnMacStatistic)(SK_AC *pAC, SK_IOC IoC, unsigned int Port,
4879 - SK_U16 StatAddr, SK_U32 SK_FAR *pVal);
4880 - int (*pFnMacResetCounter)(SK_AC *pAC, SK_IOC IoC, unsigned int Port);
4881 - int (*pFnMacOverflow)(SK_AC *pAC, SK_IOC IoC, unsigned int Port,
4882 - SK_U16 IStatus, SK_U64 SK_FAR *pVal);
4883 + int (*pFnMacUpdateStats)(SK_AC *, SK_IOC, unsigned int);
4884 + int (*pFnMacStatistic)(SK_AC *, SK_IOC, unsigned int, SK_U16, SK_U32 SK_FAR *);
4885 + int (*pFnMacResetCounter)(SK_AC *, SK_IOC, unsigned int);
4886 + int (*pFnMacOverflow)(SK_AC *, SK_IOC, unsigned int, SK_U16, SK_U64 SK_FAR *);
4887 + void (*pSkGeSirqIsr)(SK_AC *, SK_IOC, SK_U32);
4889 + int (*pFnMacPhyRead)(SK_AC *, SK_IOC, int, int, SK_U16 SK_FAR *);
4890 + int (*pFnMacPhyWrite)(SK_AC *, SK_IOC, int, int, SK_U16);
4891 +#endif /* SK_DIAG */
4897 SK_TIMER PWaTimer; /* Workaround Timer */
4898 SK_TIMER HalfDupChkTimer;
4899 -#endif /* SK_DIAG */
4900 +#endif /* !SK_DIAG */
4901 SK_U32 PPrevShorts; /* Previous Short Counter checking */
4902 SK_U32 PPrevFcs; /* Previous FCS Error Counter checking */
4903 SK_U64 PPrevRx; /* Previous RxOk Counter checking */
4905 int PXaQOff; /* Asynchronous Tx Queue Address Offset */
4906 int PhyType; /* PHY used on this port */
4907 int PState; /* Port status (reset, stop, init, run) */
4908 + int PPortUsage; /* Driver Port Usage */
4909 SK_U16 PhyId1; /* PHY Id1 on this port */
4910 SK_U16 PhyAddr; /* MDIO/MDC PHY address */
4911 SK_U16 PIsave; /* Saved Interrupt status word */
4913 SK_U8 PLinkModeConf; /* Link Mode configured */
4914 SK_U8 PLinkMode; /* Link Mode currently used */
4915 SK_U8 PLinkModeStatus;/* Link Mode Status */
4916 - SK_U8 PLinkSpeedCap; /* Link Speed Capabilities(10/100/1000 Mbps) */
4917 + SK_U8 PLinkSpeedCap; /* Link Speed Capabilities (10/100/1000 Mbps) */
4918 SK_U8 PLinkSpeed; /* configured Link Speed (10/100/1000 Mbps) */
4919 SK_U8 PLinkSpeedUsed; /* current Link Speed (10/100/1000 Mbps) */
4920 SK_U8 PFlowCtrlCap; /* Flow Control Capabilities */
4921 @@ -367,7 +554,10 @@
4922 int PMacJamLen; /* MAC Jam length */
4923 int PMacJamIpgVal; /* MAC Jam IPG */
4924 int PMacJamIpgData; /* MAC IPG Jam to Data */
4925 + int PMacBackOffLim; /* MAC Back-off Limit */
4926 + int PMacDataBlind; /* MAC Data Blinder */
4927 int PMacIpgData; /* MAC Data IPG */
4928 + SK_U16 PMacAddr[3]; /* MAC address */
4929 SK_BOOL PMacLimit4; /* reset collision counter and backoff algorithm */
4932 @@ -379,27 +569,38 @@
4933 int GIChipId; /* Chip Identification Number */
4934 int GIChipRev; /* Chip Revision Number */
4935 SK_U8 GIPciHwRev; /* PCI HW Revision Number */
4936 + SK_U8 GIPciBus; /* PCI Bus Type (PCI / PCI-X / PCI-Express) */
4937 + SK_U8 GIPciMode; /* PCI / PCI-X Mode @ Clock */
4938 + SK_U8 GIPexWidth; /* PCI-Express Negotiated Link Width */
4939 SK_BOOL GIGenesis; /* Genesis adapter ? */
4940 - SK_BOOL GIYukon; /* YUKON-A1/Bx chip */
4941 + SK_BOOL GIYukon; /* YUKON family (1 and 2) */
4942 SK_BOOL GIYukonLite; /* YUKON-Lite chip */
4943 + SK_BOOL GIYukon2; /* YUKON-2 chip (-XL, -EC or -FE) */
4944 + SK_U8 GIConTyp; /* Connector Type */
4945 + SK_U8 GIPmdTyp; /* PMD Type */
4946 SK_BOOL GICopperType; /* Copper Type adapter ? */
4947 SK_BOOL GIPciSlot64; /* 64-bit PCI Slot */
4948 SK_BOOL GIPciClock66; /* 66 MHz PCI Clock */
4949 SK_BOOL GIVauxAvail; /* VAUX available (YUKON) */
4950 SK_BOOL GIYukon32Bit; /* 32-Bit YUKON adapter */
4951 + SK_BOOL GIAsfEnabled; /* ASF subsystem enabled */
4952 + SK_BOOL GIAsfRunning; /* ASF subsystem running */
4953 SK_U16 GILedBlinkCtrl; /* LED Blink Control */
4954 int GIMacsFound; /* Number of MACs found on this adapter */
4955 int GIMacType; /* MAC Type used on this adapter */
4956 - int GIHstClkFact; /* Host Clock Factor (62.5 / HstClk * 100) */
4957 - int GIPortUsage; /* Driver Port Usage */
4958 + int GIChipCap; /* Adapter's Capabilities */
4959 + int GIHwResInfo; /* HW Resources / Application Information */
4960 + int GIHstClkFact; /* Host Clock Factor (HstClk / 62.5 * 100) */
4961 int GILevel; /* Initialization Level completed */
4962 int GIRamSize; /* The RAM size of the adapter in kB */
4963 int GIWolOffs; /* WOL Register Offset (HW-Bug in Rev. A) */
4964 SK_U32 GIRamOffs; /* RAM Address Offset for addr calculation */
4965 SK_U32 GIPollTimerVal; /* Descr. Poll Timer Init Val (HstClk ticks) */
4966 SK_U32 GIValIrqMask; /* Value for Interrupt Mask */
4967 + SK_U32 GIValHwIrqMask; /* Value for HWE Interrupt Mask */
4968 SK_U32 GITimeStampCnt; /* Time Stamp High Counter (YUKON only) */
4969 SK_GEPORT GP[SK_MAX_MACS];/* Port Dependent Information */
4970 + SK_HW_FEATURES HwF; /* HW Features struct */
4971 SK_GEMACFUNC GIFunc; /* MAC depedent functions */
4975 #define SKERR_HWI_E005 (SKERR_HWI_E004+1)
4976 #define SKERR_HWI_E005MSG "SkGeInitPort(): cannot init running ports"
4977 #define SKERR_HWI_E006 (SKERR_HWI_E005+1)
4978 -#define SKERR_HWI_E006MSG "SkGeMacInit(): PState does not match HW state"
4979 +#define SKERR_HWI_E006MSG "SkGeInit() called with illegal Chip Id"
4980 #define SKERR_HWI_E007 (SKERR_HWI_E006+1)
4981 #define SKERR_HWI_E007MSG "SkXmInitDupMd() called with invalid Dup Mode"
4982 #define SKERR_HWI_E008 (SKERR_HWI_E007+1)
4983 @@ -433,11 +634,11 @@
4984 #define SKERR_HWI_E013 (SKERR_HWI_E012+1)
4985 #define SKERR_HWI_E013MSG "SkGeInitPort(): cfg changed for running queue"
4986 #define SKERR_HWI_E014 (SKERR_HWI_E013+1)
4987 -#define SKERR_HWI_E014MSG "SkGeInitPort(): unknown GIPortUsage specified"
4988 +#define SKERR_HWI_E014MSG "SkGeInitPort(): unknown PortUsage specified"
4989 #define SKERR_HWI_E015 (SKERR_HWI_E014+1)
4990 -#define SKERR_HWI_E015MSG "Illegal Link mode parameter"
4991 +#define SKERR_HWI_E015MSG "Illegal Link Mode parameter"
4992 #define SKERR_HWI_E016 (SKERR_HWI_E015+1)
4993 -#define SKERR_HWI_E016MSG "Illegal Flow control mode parameter"
4994 +#define SKERR_HWI_E016MSG "Illegal Flow Control Mode parameter"
4995 #define SKERR_HWI_E017 (SKERR_HWI_E016+1)
4996 #define SKERR_HWI_E017MSG "Illegal value specified for GIPollTimerVal"
4997 #define SKERR_HWI_E018 (SKERR_HWI_E017+1)
4998 @@ -447,15 +648,19 @@
4999 #define SKERR_HWI_E020 (SKERR_HWI_E019+1)
5000 #define SKERR_HWI_E020MSG "Illegal Master/Slave parameter"
5001 #define SKERR_HWI_E021 (SKERR_HWI_E020+1)
5002 -#define SKERR_HWI_E021MSG "MacUpdateStats(): cannot update statistic counter"
5003 -#define SKERR_HWI_E022 (SKERR_HWI_E021+1)
5004 -#define SKERR_HWI_E022MSG "MacStatistic(): illegal statistic base address"
5005 +#define SKERR_HWI_E021MSG "MacUpdateStats(): cannot update statistic counter"
5006 +#define SKERR_HWI_E022 (SKERR_HWI_E021+1)
5007 +#define SKERR_HWI_E022MSG "MacStatistic(): illegal statistic base address"
5008 #define SKERR_HWI_E023 (SKERR_HWI_E022+1)
5009 #define SKERR_HWI_E023MSG "SkGeInitPort(): Transmit Queue Size too small"
5010 #define SKERR_HWI_E024 (SKERR_HWI_E023+1)
5011 #define SKERR_HWI_E024MSG "FATAL: SkGeStopPort() does not terminate (Rx)"
5012 #define SKERR_HWI_E025 (SKERR_HWI_E024+1)
5013 -#define SKERR_HWI_E025MSG ""
5014 +#define SKERR_HWI_E025MSG "Link Partner not Auto-Neg. able"
5015 +#define SKERR_HWI_E026 (SKERR_HWI_E025+1)
5016 +#define SKERR_HWI_E026MSG "PEX negotiated Link width not max."
5017 +#define SKERR_HWI_E027 (SKERR_HWI_E026+1)
5018 +#define SKERR_HWI_E027MSG ""
5020 /* function prototypes ********************************************************/
5022 @@ -464,6 +669,30 @@
5024 * public functions in skgeinit.c
5026 +extern void SkGePortVlan(
5032 +extern void SkGeRxRss(
5038 +extern void SkGeRxCsum(
5044 +extern void SkGePollRxD(
5050 extern void SkGePollTxD(
5053 @@ -516,11 +745,28 @@
5057 +extern void SkGeInitRamIface(
5061 extern int SkGeInitAssignRamToQueues(
5067 +extern void DoInitRamQueue(
5071 + SK_U32 QuStartAddr,
5075 +extern int SkYuk2RestartRxBmu(
5081 * public functions in skxmac2.c
5083 @@ -539,6 +785,11 @@
5087 +extern void SkMacClearRst(
5092 extern void SkXmInitMac(
5095 @@ -565,6 +816,11 @@
5099 +extern void SkMacFlushRxFifo(
5104 extern void SkMacIrq(
5107 @@ -581,7 +837,13 @@
5111 -extern int SkMacRxTxEnable(
5112 +extern void SkMacSetRxTxEn(
5118 +extern int SkMacRxTxEnable(
5122 @@ -598,28 +860,28 @@
5126 -extern void SkXmPhyRead(
5127 +extern int SkXmPhyRead(
5132 SK_U16 SK_FAR *pVal);
5134 -extern void SkXmPhyWrite(
5135 +extern int SkXmPhyWrite(
5142 -extern void SkGmPhyRead(
5143 +extern int SkGmPhyRead(
5148 SK_U16 SK_FAR *pVal);
5150 -extern void SkGmPhyWrite(
5151 +extern int SkGmPhyWrite(
5155 @@ -633,6 +895,16 @@
5159 +extern void SkXmInitDupMd(
5164 +extern void SkXmInitPauseMd(
5169 extern void SkXmAutoNegLipaXmac(
5178 SK_U64 SK_FAR *pStatus);
5180 extern int SkGmOverflowStatus(
5181 @@ -693,6 +965,19 @@
5185 +#ifdef SK_PHY_LP_MODE
5186 +extern int SkGmEnterLowPowerMode(
5192 +extern int SkGmLeaveLowPowerMode(
5196 +#endif /* SK_PHY_LP_MODE */
5199 extern void SkGePhyRead(
5201 @@ -735,6 +1020,7 @@
5203 * public functions in skgeinit.c
5205 +extern void SkGePollRxD();
5206 extern void SkGePollTxD();
5207 extern void SkGeYellowLED();
5208 extern int SkGeCfgSync();
5209 @@ -744,30 +1030,41 @@
5210 extern void SkGeDeInit();
5211 extern int SkGeInitPort();
5212 extern void SkGeXmitLED();
5213 +extern void SkGeInitRamIface();
5214 extern int SkGeInitAssignRamToQueues();
5215 +extern void SkGePortVlan();
5216 +extern void SkGeRxCsum();
5217 +extern void SkGeRxRss();
5218 +extern void DoInitRamQueue();
5219 +extern int SkYuk2RestartRxBmu();
5222 * public functions in skxmac2.c
5224 -extern void SkMacRxTxDisable();
5225 +extern void SkMacRxTxDisable();
5226 extern void SkMacSoftRst();
5227 extern void SkMacHardRst();
5228 -extern void SkMacInitPhy();
5229 -extern int SkMacRxTxEnable();
5230 -extern void SkMacPromiscMode();
5231 -extern void SkMacHashing();
5232 -extern void SkMacIrqDisable();
5233 +extern void SkMacClearRst();
5234 +extern void SkMacInitPhy();
5235 +extern int SkMacRxTxEnable();
5236 +extern void SkMacPromiscMode();
5237 +extern void SkMacHashing();
5238 +extern void SkMacIrqDisable();
5239 extern void SkMacFlushTxFifo();
5240 +extern void SkMacFlushRxFifo();
5241 extern void SkMacIrq();
5242 extern int SkMacAutoNegDone();
5243 extern void SkMacAutoNegLipaPhy();
5244 +extern void SkMacSetRxTxEn();
5245 extern void SkXmInitMac();
5246 -extern void SkXmPhyRead();
5247 -extern void SkXmPhyWrite();
5248 +extern int SkXmPhyRead();
5249 +extern int SkXmPhyWrite();
5250 extern void SkGmInitMac();
5251 -extern void SkGmPhyRead();
5252 -extern void SkGmPhyWrite();
5253 +extern int SkGmPhyRead();
5254 +extern int SkGmPhyWrite();
5255 extern void SkXmClrExactAddr();
5256 +extern void SkXmInitDupMd();
5257 +extern void SkXmInitPauseMd();
5258 extern void SkXmAutoNegLipaXmac();
5259 extern int SkXmUpdateStats();
5260 extern int SkGmUpdateStats();
5261 @@ -778,6 +1075,10 @@
5262 extern int SkXmOverflowStatus();
5263 extern int SkGmOverflowStatus();
5264 extern int SkGmCableDiagStatus();
5265 +#ifdef SK_PHY_LP_MODE
5266 +extern int SkGmEnterLowPowerMode();
5267 +extern int SkGmLeaveLowPowerMode();
5268 +#endif /* SK_PHY_LP_MODE */
5271 extern void SkGePhyRead();
5272 @@ -788,10 +1089,11 @@
5273 extern void SkXmSendCont();
5274 #endif /* SK_DIAG */
5276 -#endif /* SK_KR_PROTO */
5277 +#endif /* SK_KR_PROTO */
5281 -#endif /* __cplusplus */
5282 +#endif /* __cplusplus */
5284 +#endif /* __INC_SKGEINIT_H_ */
5286 -#endif /* __INC_SKGEINIT_H_ */
5287 diff -ruN linux/drivers/net/sk98lin/h/skgepnm2.h linux-new/drivers/net/sk98lin/h/skgepnm2.h
5288 --- linux/drivers/net/sk98lin/h/skgepnm2.h 2006-09-20 05:42:06.000000000 +0200
5289 +++ linux-new/drivers/net/sk98lin/h/skgepnm2.h 2006-07-28 14:13:54.000000000 +0200
5293 * Project: GEnesis, PCI Gigabit Ethernet Adapter
5294 - * Version: $Revision$
5296 + * Version: $Revision$
5298 * Purpose: Defines for Private Network Management Interface
5300 ****************************************************************************/
5302 /******************************************************************************
5305 * (C)Copyright 1998-2002 SysKonnect GmbH.
5306 * (C)Copyright 2002-2003 Marvell.
5309 * (at your option) any later version.
5311 * The information in this file is provided "AS IS" without warranty.
5314 ******************************************************************************/
5318 * General definitions
5320 -#define SK_PNMI_CHIPSET_XMAC 1 /* XMAC11800FP */
5321 -#define SK_PNMI_CHIPSET_YUKON 2 /* YUKON */
5322 +#define SK_PNMI_CHIPSET_XMAC 1 /* XMAC11800FP */
5323 +#define SK_PNMI_CHIPSET_YUKON 2 /* YUKON */
5324 +#define SK_PNMI_CHIPSET_YUKON_LITE 3 /* YUKON-Lite (Rev. A1-A3) */
5325 +#define SK_PNMI_CHIPSET_YUKON_LP 4 /* YUKON-LP */
5326 +#define SK_PNMI_CHIPSET_YUKON_XL 5 /* YUKON-2 XL */
5327 +#define SK_PNMI_CHIPSET_YUKON_EC 6 /* YUKON-2 EC */
5328 +#define SK_PNMI_CHIPSET_YUKON_FE 7 /* YUKON-2 FE */
5330 #define SK_PNMI_BUS_PCI 1 /* PCI bus*/
5334 * VCT internal status values
5336 -#define SK_PNMI_VCT_PENDING 32
5337 -#define SK_PNMI_VCT_TEST_DONE 64
5338 -#define SK_PNMI_VCT_LINK 128
5339 +#define SK_PNMI_VCT_PENDING 0x20
5340 +#define SK_PNMI_VCT_TEST_DONE 0x40
5341 +#define SK_PNMI_VCT_LINK 0x80
5344 * Internal table definitions
5347 pAC->Pnmi.MacUpdatedFlag, \
5348 pAC->Pnmi.RlmtUpdatedFlag, \
5349 - pAC->Pnmi.SirqUpdatedFlag))}}
5350 + pAC->Pnmi.SirqUpdatedFlag));}}
5354 diff -ruN linux/drivers/net/sk98lin/h/skgepnmi.h linux-new/drivers/net/sk98lin/h/skgepnmi.h
5355 --- linux/drivers/net/sk98lin/h/skgepnmi.h 2006-09-20 05:42:06.000000000 +0200
5356 +++ linux-new/drivers/net/sk98lin/h/skgepnmi.h 2006-07-28 14:13:54.000000000 +0200
5358 /*****************************************************************************
5361 - * Project: GEnesis, PCI Gigabit Ethernet Adapter
5362 - * Version: $Revision$
5364 + * Project: Gigabit Ethernet Adapters, PNMI-Module
5365 + * Version: $Revision$
5367 * Purpose: Defines for Private Network Management Interface
5369 ****************************************************************************/
5371 /******************************************************************************
5374 * (C)Copyright 1998-2002 SysKonnect GmbH.
5375 * (C)Copyright 2002-2003 Marvell.
5378 * (at your option) any later version.
5380 * The information in this file is provided "AS IS" without warranty.
5383 ******************************************************************************/
5386 #include "h/sktypes.h"
5387 #include "h/skerror.h"
5388 #include "h/sktimer.h"
5389 -#include "h/ski2c.h"
5390 +#include "h/sktwsi.h"
5391 #include "h/skaddr.h"
5392 #include "h/skrlmt.h"
5393 #include "h/skvpd.h"
5396 #define SK_PNMI_MDB_VERSION 0x00030001 /* 3.1 */
5403 #define SK_PNMI_EVT_UTILIZATION_TIMER 7 /* Timer event for Utiliza. */
5404 #define SK_PNMI_EVT_CLEAR_COUNTER 8 /* Clear statistic counters */
5405 #define SK_PNMI_EVT_XMAC_RESET 9 /* XMAC will be reset */
5407 #define SK_PNMI_EVT_RLMT_PORT_UP 10 /* Port came logically up */
5408 #define SK_PNMI_EVT_RLMT_PORT_DOWN 11 /* Port went logically down */
5409 #define SK_PNMI_EVT_RLMT_SEGMENTATION 13 /* Two SP root bridges found */
5410 #define SK_PNMI_EVT_RLMT_ACTIVE_DOWN 14 /* Port went logically down */
5411 #define SK_PNMI_EVT_RLMT_ACTIVE_UP 15 /* Port came logically up */
5412 -#define SK_PNMI_EVT_RLMT_SET_NETS 16 /* 1. Parameter is number of nets
5413 - 1 = single net; 2 = dual net */
5414 -#define SK_PNMI_EVT_VCT_RESET 17 /* VCT port reset timer event started with SET. */
5416 +#define SK_PNMI_EVT_RLMT_SET_NETS 16 /* Number of nets (1 or 2). */
5417 +#define SK_PNMI_EVT_VCT_RESET 17 /* VCT port reset timer event started with SET. */
5422 #define SK_PNMI_ERR_UNKNOWN_NET 7
5423 #define SK_PNMI_ERR_NOT_SUPPORTED 10
5427 * Return values of driver reset function SK_DRIVER_RESET() and
5428 * driver event function SK_DRIVER_EVENT()
5430 #define SK_PNMI_ERR_OK 0
5431 #define SK_PNMI_ERR_FAIL 1
5435 * Return values of driver test function SK_DRIVER_SELFTEST()
5437 #define SK_PNMI_TST_UNKNOWN (1 << 0)
5438 -#define SK_PNMI_TST_TRANCEIVER (1 << 1)
5439 +#define SK_PNMI_TST_TRANCEIVER (1 << 1)
5440 #define SK_PNMI_TST_ASIC (1 << 2)
5441 #define SK_PNMI_TST_SENSOR (1 << 3)
5442 -#define SK_PNMI_TST_POWERMGMT (1 << 4)
5443 +#define SK_PNMI_TST_POWERMGMT (1 << 4)
5444 #define SK_PNMI_TST_PCI (1 << 5)
5445 #define SK_PNMI_TST_MAC (1 << 6)
5449 * RLMT specific definitions
5451 @@ -223,7 +218,17 @@
5452 #define OID_SKGE_RLMT_PORT_NUMBER 0xFF010141
5453 #define OID_SKGE_RLMT_PORT_ACTIVE 0xFF010142
5454 #define OID_SKGE_RLMT_PORT_PREFERRED 0xFF010143
5455 -#define OID_SKGE_INTERMEDIATE_SUPPORT 0xFF010160
5457 +#define OID_SKGE_RLMT_MONITOR_NUMBER 0xFF010150
5458 +#define OID_SKGE_RLMT_MONITOR_INDEX 0xFF010151
5459 +#define OID_SKGE_RLMT_MONITOR_ADDR 0xFF010152
5460 +#define OID_SKGE_RLMT_MONITOR_ERRS 0xFF010153
5461 +#define OID_SKGE_RLMT_MONITOR_TIMESTAMP 0xFF010154
5462 +#define OID_SKGE_RLMT_MONITOR_ADMIN 0xFF010155
5464 +#define OID_SKGE_INTERMEDIATE_SUPPORT 0xFF010160
5465 +#define OID_SKGE_SET_TEAM_MAC_ADDRESS 0xFF010161
5466 +#define OID_SKGE_DEVICE_INFORMATION 0xFF010162
5468 #define OID_SKGE_SPEED_CAP 0xFF010170
5469 #define OID_SKGE_SPEED_MODE 0xFF010171
5470 @@ -322,13 +327,6 @@
5471 #define OID_SKGE_RLMT_TX_SP_REQ_CTS 0xFF020168
5472 #define OID_SKGE_RLMT_RX_SP_CTS 0xFF020169
5474 -#define OID_SKGE_RLMT_MONITOR_NUMBER 0xFF010150
5475 -#define OID_SKGE_RLMT_MONITOR_INDEX 0xFF010151
5476 -#define OID_SKGE_RLMT_MONITOR_ADDR 0xFF010152
5477 -#define OID_SKGE_RLMT_MONITOR_ERRS 0xFF010153
5478 -#define OID_SKGE_RLMT_MONITOR_TIMESTAMP 0xFF010154
5479 -#define OID_SKGE_RLMT_MONITOR_ADMIN 0xFF010155
5481 #define OID_SKGE_TX_SW_QUEUE_LEN 0xFF020170
5482 #define OID_SKGE_TX_SW_QUEUE_MAX 0xFF020171
5483 #define OID_SKGE_TX_RETRY 0xFF020172
5485 #define OID_SKGE_VCT_GET 0xFF020200
5486 #define OID_SKGE_VCT_SET 0xFF020201
5487 #define OID_SKGE_VCT_STATUS 0xFF020202
5488 +#define OID_SKGE_VCT_CAPABILITIES 0xFF020203
5490 #ifdef SK_DIAG_SUPPORT
5491 /* Defines for driver DIAG mode. */
5492 @@ -367,22 +366,79 @@
5493 #define OID_SKGE_PHY_TYPE 0xFF020215
5494 #define OID_SKGE_PHY_LP_MODE 0xFF020216
5497 + * Added for new DualNet IM driver V2
5498 + * these OIDs should later be in pnmi.h
5500 +#define OID_SKGE_MAC_COUNT 0xFF020217
5501 +#define OID_SKGE_DUALNET_MODE 0xFF020218
5502 +#define OID_SKGE_SET_TAGHEADER 0xFF020219
5505 +/* Defines for ASF */
5506 +#define OID_SKGE_ASF 0xFF02021a
5507 +#define OID_SKGE_ASF_STORE_CONFIG 0xFF02021b
5508 +#define OID_SKGE_ASF_ENA 0xFF02021c
5509 +#define OID_SKGE_ASF_RETRANS 0xFF02021d
5510 +#define OID_SKGE_ASF_RETRANS_INT 0xFF02021e
5511 +#define OID_SKGE_ASF_HB_ENA 0xFF02021f
5512 +#define OID_SKGE_ASF_HB_INT 0xFF020220
5513 +#define OID_SKGE_ASF_WD_ENA 0xFF020221
5514 +#define OID_SKGE_ASF_WD_TIME 0xFF020222
5515 +#define OID_SKGE_ASF_IP_SOURCE 0xFF020223
5516 +#define OID_SKGE_ASF_MAC_SOURCE 0xFF020224
5517 +#define OID_SKGE_ASF_IP_DEST 0xFF020225
5518 +#define OID_SKGE_ASF_MAC_DEST 0xFF020226
5519 +#define OID_SKGE_ASF_COMMUNITY_NAME 0xFF020227
5520 +#define OID_SKGE_ASF_RSP_ENA 0xFF020228
5521 +#define OID_SKGE_ASF_RETRANS_COUNT_MIN 0xFF020229
5522 +#define OID_SKGE_ASF_RETRANS_COUNT_MAX 0xFF02022a
5523 +#define OID_SKGE_ASF_RETRANS_INT_MIN 0xFF02022b
5524 +#define OID_SKGE_ASF_RETRANS_INT_MAX 0xFF02022c
5525 +#define OID_SKGE_ASF_HB_INT_MIN 0xFF02022d
5526 +#define OID_SKGE_ASF_HB_INT_MAX 0xFF02022e
5527 +#define OID_SKGE_ASF_WD_TIME_MIN 0xFF02022f
5528 +#define OID_SKGE_ASF_WD_TIME_MAX 0xFF020230
5529 +#define OID_SKGE_ASF_HB_CAP 0xFF020231
5530 +#define OID_SKGE_ASF_WD_TIMER_RES 0xFF020232
5531 +#define OID_SKGE_ASF_GUID 0xFF020233
5532 +#define OID_SKGE_ASF_KEY_OP 0xFF020234
5533 +#define OID_SKGE_ASF_KEY_ADM 0xFF020235
5534 +#define OID_SKGE_ASF_KEY_GEN 0xFF020236
5535 +#define OID_SKGE_ASF_CAP 0xFF020237
5536 +#define OID_SKGE_ASF_PAR_1 0xFF020238
5537 +#define OID_SKGE_ASF_OVERALL_OID 0xFF020239
5538 +#endif /* SK_ASF */
5541 +// Defined for yukon2 path only
5542 +#define OID_SKGE_UPPER_MINIPORT 0xFF02023D
5546 +/* Defines for ASF */
5547 +#define OID_SKGE_ASF_FWVER_OID 0xFF020240
5548 +#define OID_SKGE_ASF_ACPI_OID 0xFF020241
5549 +#define OID_SKGE_ASF_SMBUS_OID 0xFF020242
5550 +#endif /* SK_ASF */
5553 /* VCT struct to store a backup copy of VCT data after a port reset. */
5554 typedef struct s_PnmiVct {
5557 - SK_U32 PMdiPairLen[4];
5558 - SK_U8 PMdiPairSts[4];
5560 + SK_U32 MdiPairLen[4];
5561 + SK_U8 MdiPairSts[4];
5565 /* VCT status values (to be given to CPA via OID_SKGE_VCT_STATUS). */
5566 -#define SK_PNMI_VCT_NONE 0
5567 -#define SK_PNMI_VCT_OLD_VCT_DATA 1
5568 -#define SK_PNMI_VCT_NEW_VCT_DATA 2
5569 -#define SK_PNMI_VCT_OLD_DSP_DATA 4
5570 -#define SK_PNMI_VCT_NEW_DSP_DATA 8
5571 -#define SK_PNMI_VCT_RUNNING 16
5572 +#define SK_PNMI_VCT_NONE 0x00
5573 +#define SK_PNMI_VCT_OLD_VCT_DATA 0x01
5574 +#define SK_PNMI_VCT_NEW_VCT_DATA 0x02
5575 +#define SK_PNMI_VCT_OLD_DSP_DATA 0x04
5576 +#define SK_PNMI_VCT_NEW_DSP_DATA 0x08
5577 +#define SK_PNMI_VCT_RUNNING 0x10
5580 /* VCT cable test status. */
5581 @@ -390,7 +446,12 @@
5582 #define SK_PNMI_VCT_SHORT_CABLE 1
5583 #define SK_PNMI_VCT_OPEN_CABLE 2
5584 #define SK_PNMI_VCT_TEST_FAIL 3
5585 -#define SK_PNMI_VCT_IMPEDANCE_MISMATCH 4
5586 +#define SK_PNMI_VCT_IMPEDANCE_MISMATCH 4
5587 +#define SK_PNMI_VCT_NOT_PRESENT 5
5589 +/* VCT capabilities (needed for OID_SKGE_VCT_CAPABILITIES. */
5590 +#define SK_PNMI_VCT_SUPPORTED 1
5591 +#define SK_PNMI_VCT_NOT_SUPPORTED 0
5593 #define OID_SKGE_TRAP_SEN_WAR_LOW 500
5594 #define OID_SKGE_TRAP_SEN_WAR_UPP 501
5596 #define SK_SET_FULL_MIB 5
5597 #define SK_PRESET_FULL_MIB 6
5601 * Define error numbers and messages for syslog
5604 #define SK_PNMI_ERR014 (SK_ERRBASE_PNMI + 14)
5605 #define SK_PNMI_ERR014MSG "Vpd: Cannot read VPD keys"
5606 #define SK_PNMI_ERR015 (SK_ERRBASE_PNMI + 15)
5607 -#define SK_PNMI_ERR015MSG "Vpd: Internal array for VPD keys to small"
5608 +#define SK_PNMI_ERR015MSG "Vpd: Internal array for VPD keys too small"
5609 #define SK_PNMI_ERR016 (SK_ERRBASE_PNMI + 16)
5610 #define SK_PNMI_ERR016MSG "Vpd: Key string too long"
5611 #define SK_PNMI_ERR017 (SK_ERRBASE_PNMI + 17)
5613 #define SK_PNMI_ERR036 (SK_ERRBASE_PNMI + 36)
5614 #define SK_PNMI_ERR036MSG ""
5615 #define SK_PNMI_ERR037 (SK_ERRBASE_PNMI + 37)
5616 -#define SK_PNMI_ERR037MSG "Rlmt: SK_RLMT_MODE_CHANGE event return not 0"
5617 +#define SK_PNMI_ERR037MSG "Rlmt: SK_RLMT_MODE_CHANGE event returned not 0"
5618 #define SK_PNMI_ERR038 (SK_ERRBASE_PNMI + 38)
5619 -#define SK_PNMI_ERR038MSG "Rlmt: SK_RLMT_PREFPORT_CHANGE event return not 0"
5620 +#define SK_PNMI_ERR038MSG "Rlmt: SK_RLMT_PREFPORT_CHANGE event returned not 0"
5621 #define SK_PNMI_ERR039 (SK_ERRBASE_PNMI + 39)
5622 #define SK_PNMI_ERR039MSG "RlmtStat: Unknown OID"
5623 #define SK_PNMI_ERR040 (SK_ERRBASE_PNMI + 40)
5625 #define SK_PNMI_ERR046 (SK_ERRBASE_PNMI + 46)
5626 #define SK_PNMI_ERR046MSG "Monitor: Unknown OID"
5627 #define SK_PNMI_ERR047 (SK_ERRBASE_PNMI + 47)
5628 -#define SK_PNMI_ERR047MSG "SirqUpdate: Event function returns not 0"
5629 +#define SK_PNMI_ERR047MSG "SirqUpdate: Event function returned not 0"
5630 #define SK_PNMI_ERR048 (SK_ERRBASE_PNMI + 48)
5631 -#define SK_PNMI_ERR048MSG "RlmtUpdate: Event function returns not 0"
5632 +#define SK_PNMI_ERR048MSG "RlmtUpdate: Event function returned not 0"
5633 #define SK_PNMI_ERR049 (SK_ERRBASE_PNMI + 49)
5634 #define SK_PNMI_ERR049MSG "SkPnmiInit: Invalid size of 'CounterOffset' struct!!"
5635 #define SK_PNMI_ERR050 (SK_ERRBASE_PNMI + 50)
5636 @@ -826,23 +886,25 @@
5637 } SK_PNMI_STRUCT_DATA;
5639 #define SK_PNMI_STRUCT_SIZE (sizeof(SK_PNMI_STRUCT_DATA))
5641 +/* The ReturnStatus field must be located before VpdFreeBytes! */
5642 #define SK_PNMI_MIN_STRUCT_SIZE ((unsigned int)(SK_UPTR)\
5643 &(((SK_PNMI_STRUCT_DATA *)0)->VpdFreeBytes))
5645 - * ReturnStatus field
5647 - * before VpdFreeBytes
5651 * Various definitions
5653 +#define SK_PNMI_EVT_TIMER_CHECK 28125000L /* 28125 ms */
5655 +#define SK_PNMI_VCT_TIMER_CHECK 4000000L /* 4 sec. */
5657 #define SK_PNMI_MAX_PROTOS 3
5659 -#define SK_PNMI_CNT_NO 66 /* Must have the value of the enum
5660 - * SK_PNMI_MAX_IDX. Define SK_PNMI_CHECK
5661 - * for check while init phase 1
5664 + * SK_PNMI_CNT_NO must have the value of the enum SK_PNMI_MAX_IDX.
5665 + * Define SK_PNMI_CHECK to check this during init level SK_INIT_IO.
5667 +#define SK_PNMI_CNT_NO 66
5670 * Estimate data structure
5671 @@ -856,14 +918,6 @@
5675 - * VCT timer data structure
5677 -typedef struct s_VctTimer {
5678 - SK_TIMER VctTimer;
5679 -} SK_PNMI_VCT_TIMER;
5683 * PNMI specific adapter context structure
5685 typedef struct s_PnmiPort {
5686 @@ -933,12 +987,13 @@
5687 unsigned int TrapQueueEnd;
5688 unsigned int TrapBufPad;
5689 unsigned int TrapUnique;
5690 - SK_U8 VctStatus[SK_MAX_MACS];
5691 - SK_PNMI_VCT VctBackup[SK_MAX_MACS];
5692 - SK_PNMI_VCT_TIMER VctTimeout[SK_MAX_MACS];
5693 + SK_U8 VctStatus[SK_MAX_MACS];
5694 + SK_PNMI_VCT VctBackup[SK_MAX_MACS];
5695 + SK_TIMER VctTimeout[SK_MAX_MACS];
5696 #ifdef SK_DIAG_SUPPORT
5697 SK_U32 DiagAttached;
5698 #endif /* SK_DIAG_SUPPORT */
5699 + SK_BOOL VpdKeyReadError;
5703 @@ -946,6 +1001,10 @@
5704 * Function prototypes
5706 extern int SkPnmiInit(SK_AC *pAC, SK_IOC IoC, int Level);
5707 +extern int SkPnmiGetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void* pBuf,
5708 + unsigned int* pLen, SK_U32 Instance, SK_U32 NetIndex);
5709 +extern int SkPnmiPreSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id,
5710 + void* pBuf, unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex);
5711 extern int SkPnmiSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void* pBuf,
5712 unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex);
5713 extern int SkPnmiGetStruct(SK_AC *pAC, SK_IOC IoC, void* pBuf,
5714 diff -ruN linux/drivers/net/sk98lin/h/skgesirq.h linux-new/drivers/net/sk98lin/h/skgesirq.h
5715 --- linux/drivers/net/sk98lin/h/skgesirq.h 2006-09-20 05:42:06.000000000 +0200
5716 +++ linux-new/drivers/net/sk98lin/h/skgesirq.h 2006-07-28 14:13:54.000000000 +0200
5720 * Project: Gigabit Ethernet Adapters, Common Modules
5721 - * Version: $Revision$
5723 - * Purpose: SK specific Gigabit Ethernet special IRQ functions
5724 + * Version: $Revision$
5726 + * Purpose: Gigabit Ethernet special IRQ functions
5728 ******************************************************************************/
5730 /******************************************************************************
5733 * (C)Copyright 1998-2002 SysKonnect.
5734 - * (C)Copyright 2002-2003 Marvell.
5735 + * (C)Copyright 2002-2005 Marvell.
5737 * This program is free software; you can redistribute it and/or modify
5738 * it under the terms of the GNU General Public License as published by
5739 * the Free Software Foundation; either version 2 of the License, or
5740 * (at your option) any later version.
5742 * The information in this file is provided "AS IS" without warranty.
5745 ******************************************************************************/
5748 #define _INC_SKGESIRQ_H_
5750 /* Define return codes of SkGePortCheckUp and CheckShort */
5751 -#define SK_HW_PS_NONE 0 /* No action needed */
5752 -#define SK_HW_PS_RESTART 1 /* Restart needed */
5753 -#define SK_HW_PS_LINK 2 /* Link Up actions needed */
5754 +#define SK_HW_PS_NONE 0 /* No action needed */
5755 +#define SK_HW_PS_RESTART 1 /* Restart needed */
5756 +#define SK_HW_PS_LINK 2 /* Link Up actions needed */
5759 * Define the Event the special IRQ/INI module can handle
5761 #define SK_HWEV_SET_SPEED 9 /* Set Link Speed by PNMI */
5762 #define SK_HWEV_HALFDUP_CHK 10 /* Half Duplex Hangup Workaround */
5764 -#define SK_WA_ACT_TIME (5000000UL) /* 5 sec */
5765 -#define SK_WA_INA_TIME (100000UL) /* 100 msec */
5766 +#define SK_WA_ACT_TIME 1000000UL /* 1000 msec (1 sec) */
5767 +#define SK_WA_INA_TIME 100000UL /* 100 msec */
5769 -#define SK_HALFDUP_CHK_TIME (10000UL) /* 10 msec */
5770 +#define SK_HALFDUP_CHK_TIME 10000UL /* 10 msec */
5773 * Define the error numbers and messages
5775 #define SKERR_SIRQ_E011 (SKERR_SIRQ_E010+1)
5776 #define SKERR_SIRQ_E011MSG "CHECK failure XA2"
5777 #define SKERR_SIRQ_E012 (SKERR_SIRQ_E011+1)
5778 -#define SKERR_SIRQ_E012MSG "unexpected IRQ Master error"
5779 +#define SKERR_SIRQ_E012MSG "Unexpected IRQ Master error"
5780 #define SKERR_SIRQ_E013 (SKERR_SIRQ_E012+1)
5781 -#define SKERR_SIRQ_E013MSG "unexpected IRQ Status error"
5782 +#define SKERR_SIRQ_E013MSG "Unexpected IRQ Status error"
5783 #define SKERR_SIRQ_E014 (SKERR_SIRQ_E013+1)
5784 #define SKERR_SIRQ_E014MSG "Parity error on RAM (read)"
5785 #define SKERR_SIRQ_E015 (SKERR_SIRQ_E014+1)
5786 @@ -102,9 +103,35 @@
5787 #define SKERR_SIRQ_E024MSG "FIFO overflow error"
5788 #define SKERR_SIRQ_E025 (SKERR_SIRQ_E024+1)
5789 #define SKERR_SIRQ_E025MSG "2 Pair Downshift detected"
5790 +#define SKERR_SIRQ_E026 (SKERR_SIRQ_E025+1)
5791 +#define SKERR_SIRQ_E026MSG "Uncorrectable PCI Express error"
5792 +#define SKERR_SIRQ_E027 (SKERR_SIRQ_E026+1)
5793 +#define SKERR_SIRQ_E027MSG "PCI Bus Abort detected"
5794 +#define SKERR_SIRQ_E028 (SKERR_SIRQ_E027+1)
5795 +#define SKERR_SIRQ_E028MSG "Parity error on RAM 1 (read)"
5796 +#define SKERR_SIRQ_E029 (SKERR_SIRQ_E028+1)
5797 +#define SKERR_SIRQ_E029MSG "Parity error on RAM 1 (write)"
5798 +#define SKERR_SIRQ_E030 (SKERR_SIRQ_E029+1)
5799 +#define SKERR_SIRQ_E030MSG "Parity error on RAM 2 (read)"
5800 +#define SKERR_SIRQ_E031 (SKERR_SIRQ_E030+1)
5801 +#define SKERR_SIRQ_E031MSG "Parity error on RAM 2 (write)"
5802 +#define SKERR_SIRQ_E032 (SKERR_SIRQ_E031+1)
5803 +#define SKERR_SIRQ_E032MSG "TCP segmentation error async. queue 1"
5804 +#define SKERR_SIRQ_E033 (SKERR_SIRQ_E032+1)
5805 +#define SKERR_SIRQ_E033MSG "TCP segmentation error sync. queue 1"
5806 +#define SKERR_SIRQ_E034 (SKERR_SIRQ_E033+1)
5807 +#define SKERR_SIRQ_E034MSG "TCP segmentation error async. queue 2"
5808 +#define SKERR_SIRQ_E035 (SKERR_SIRQ_E034+1)
5809 +#define SKERR_SIRQ_E035MSG "TCP segmentation error sync. queue 2"
5810 +#define SKERR_SIRQ_E036 (SKERR_SIRQ_E035+1)
5811 +#define SKERR_SIRQ_E036MSG "CHECK failure polling unit"
5813 extern void SkGeSirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus);
5814 extern int SkGeSirqEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Para);
5815 +extern void SkHWLinkUp(SK_AC *pAC, SK_IOC IoC, int Port);
5816 extern void SkHWLinkDown(SK_AC *pAC, SK_IOC IoC, int Port);
5817 +extern void SkGeYuSirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus);
5818 +extern void SkYuk2SirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus);
5820 #endif /* _INC_SKGESIRQ_H_ */
5822 diff -ruN linux/drivers/net/sk98lin/h/skgetwsi.h linux-new/drivers/net/sk98lin/h/skgetwsi.h
5823 --- linux/drivers/net/sk98lin/h/skgetwsi.h 1970-01-01 01:00:00.000000000 +0100
5824 +++ linux-new/drivers/net/sk98lin/h/skgetwsi.h 2006-07-28 14:13:54.000000000 +0200
5826 +/******************************************************************************
5828 + * Name: skgetwsi.h
5829 + * Project: Gigabit Ethernet Adapters, TWSI-Module
5830 + * Version: $Revision$
5832 + * Purpose: Special defines for TWSI
5834 + ******************************************************************************/
5836 +/******************************************************************************
5839 + * (C)Copyright 1998-2002 SysKonnect.
5840 + * (C)Copyright 2002-2004 Marvell.
5842 + * This program is free software; you can redistribute it and/or modify
5843 + * it under the terms of the GNU General Public License as published by
5844 + * the Free Software Foundation; either version 2 of the License, or
5845 + * (at your option) any later version.
5846 + * The information in this file is provided "AS IS" without warranty.
5849 + ******************************************************************************/
5852 + * SKGETWSI.H contains all SK-98xx specific defines for the TWSI handling
5855 +#ifndef _INC_SKGETWSI_H_
5856 +#define _INC_SKGETWSI_H_
5859 + * Macros to access the B2_I2C_CTRL
5861 +#define SK_I2C_CTL(IoC, flag, dev, dev_size, reg, burst) \
5862 + SK_OUT32(IoC, B2_I2C_CTRL,\
5863 + (flag ? 0x80000000UL : 0x0L) | \
5864 + (((SK_U32)reg << 16) & I2C_ADDR) | \
5865 + (((SK_U32)dev << 9) & I2C_DEV_SEL) | \
5866 + (dev_size & I2C_DEV_SIZE) | \
5867 + ((burst << 4) & I2C_BURST_LEN))
5869 +#define SK_I2C_STOP(IoC) { \
5871 + SK_IN32(IoC, B2_I2C_CTRL, &I2cCtrl); \
5872 + SK_OUT32(IoC, B2_I2C_CTRL, I2cCtrl | I2C_STOP); \
5875 +#define SK_I2C_GET_CTL(IoC, pI2cCtrl) SK_IN32(IoC, B2_I2C_CTRL, pI2cCtrl)
5878 + * Macros to access the TWSI SW Registers
5880 +#define SK_I2C_SET_BIT(IoC, SetBits) { \
5882 + SK_IN8(IoC, B2_I2C_SW, &OrgBits); \
5883 + SK_OUT8(IoC, B2_I2C_SW, OrgBits | (SK_U8)(SetBits)); \
5886 +#define SK_I2C_CLR_BIT(IoC, ClrBits) { \
5888 + SK_IN8(IoC, B2_I2C_SW, &OrgBits); \
5889 + SK_OUT8(IoC, B2_I2C_SW, OrgBits & ~((SK_U8)(ClrBits))); \
5892 +#define SK_I2C_GET_SW(IoC, pI2cSw) SK_IN8(IoC, B2_I2C_SW, pI2cSw)
5895 + * define the possible sensor states
5897 +#define SK_SEN_IDLE 0 /* Idle: sensor not read */
5898 +#define SK_SEN_VALUE 1 /* Value Read cycle */
5899 +#define SK_SEN_VALEXT 2 /* Extended Value Read cycle */
5902 + * Conversion factor to convert read Voltage sensor to milli Volt
5903 + * Conversion factor to convert read Temperature sensor to 10th degree Celsius
5905 +#define SK_LM80_VT_LSB 22 /* 22mV LSB resolution */
5906 +#define SK_LM80_TEMP_LSB 10 /* 1 degree LSB resolution */
5907 +#define SK_LM80_TEMPEXT_LSB 5 /* 0.5 degree LSB resolution for ext. val. */
5910 + * formula: counter = (22500*60)/(rpm * divisor * pulses/2)
5911 + * assuming: 6500rpm, 4 pulses, divisor 1
5913 +#define SK_LM80_FAN_FAKTOR ((22500L*60)/(1*2))
5916 + * Define sensor management data
5917 + * Maximum is reached on Genesis copper dual port and Yukon-64
5918 + * Board specific maximum is in pAC->I2c.MaxSens
5920 +#define SK_MAX_SENSORS 8 /* maximal no. of installed sensors */
5921 +#define SK_MIN_SENSORS 5 /* minimal no. of installed sensors */
5924 + * To watch the state machine (SM) use the timer in two ways
5925 + * instead of one as hitherto
5927 +#define SK_TIMER_WATCH_SM 0 /* Watch the SM to finish in a spec. time */
5928 +#define SK_TIMER_NEW_GAUGING 1 /* Start a new gauging when timer expires */
5931 + * Defines for the individual thresholds
5934 +#define C_PLUS_20 120 / 100
5935 +#define C_PLUS_15 115 / 100
5936 +#define C_PLUS_10 110 / 100
5937 +#define C_PLUS_5 105 / 100
5938 +#define C_MINUS_5 95 / 100
5939 +#define C_MINUS_10 90 / 100
5940 +#define C_MINUS_15 85 / 100
5942 +/* Temperature sensor */
5943 +#define SK_SEN_TEMP_HIGH_ERR 800 /* Temperature High Err Threshold */
5944 +#define SK_SEN_TEMP_HIGH_WARN 700 /* Temperature High Warn Threshold */
5945 +#define SK_SEN_TEMP_LOW_WARN 100 /* Temperature Low Warn Threshold */
5946 +#define SK_SEN_TEMP_LOW_ERR 0 /* Temperature Low Err Threshold */
5948 +/* VCC which should be 5 V */
5949 +#define SK_SEN_PCI_5V_HIGH_ERR 5588 /* Voltage PCI High Err Threshold */
5950 +#define SK_SEN_PCI_5V_HIGH_WARN 5346 /* Voltage PCI High Warn Threshold */
5951 +#define SK_SEN_PCI_5V_LOW_WARN 4664 /* Voltage PCI Low Warn Threshold */
5952 +#define SK_SEN_PCI_5V_LOW_ERR 4422 /* Voltage PCI Low Err Threshold */
5955 + * VIO may be 5 V or 3.3 V. Initialization takes two parts:
5956 + * 1. Initialize lowest lower limit and highest higher limit.
5957 + * 2. After the first value is read correct the upper or the lower limit to
5958 + * the appropriate C constant.
5960 + * Warning limits are +-5% of the exepected voltage.
5961 + * Error limits are +-10% of the expected voltage.
5964 +/* Bug fix AF: 16.Aug.2001: Correct the init base of LM80 sensor */
5966 +#define SK_SEN_PCI_IO_5V_HIGH_ERR 5566 /* + 10% V PCI-IO High Err Threshold */
5967 +#define SK_SEN_PCI_IO_5V_HIGH_WARN 5324 /* + 5% V PCI-IO High Warn Threshold */
5969 +#define SK_SEN_PCI_IO_5V_LOW_WARN 4686 /* - 5% V PCI-IO Low Warn Threshold */
5970 +#define SK_SEN_PCI_IO_5V_LOW_ERR 4444 /* - 10% V PCI-IO Low Err Threshold */
5972 +#define SK_SEN_PCI_IO_RANGE_LIMITER 4000 /* 4000 mV range delimiter */
5974 +/* correction values for the second pass */
5975 +#define SK_SEN_PCI_IO_3V3_HIGH_ERR 3850 /* + 15% V PCI-IO High Err Threshold */
5976 +#define SK_SEN_PCI_IO_3V3_HIGH_WARN 3674 /* + 10% V PCI-IO High Warn Threshold */
5978 +#define SK_SEN_PCI_IO_3V3_LOW_WARN 2926 /* - 10% V PCI-IO Low Warn Threshold */
5979 +#define SK_SEN_PCI_IO_3V3_LOW_ERR 2772 /* - 15% V PCI-IO Low Err Threshold */
5984 +#define SK_SEN_VDD_HIGH_ERR 3630 /* Voltage ASIC High Err Threshold */
5985 +#define SK_SEN_VDD_HIGH_WARN 3476 /* Voltage ASIC High Warn Threshold */
5986 +#define SK_SEN_VDD_LOW_WARN 3146 /* Voltage ASIC Low Warn Threshold */
5987 +#define SK_SEN_VDD_LOW_ERR 2970 /* Voltage ASIC Low Err Threshold */
5990 + * PHY PLL 3V3 voltage
5992 +#define SK_SEN_PLL_3V3_HIGH_ERR 3630 /* Voltage PMA High Err Threshold */
5993 +#define SK_SEN_PLL_3V3_HIGH_WARN 3476 /* Voltage PMA High Warn Threshold */
5994 +#define SK_SEN_PLL_3V3_LOW_WARN 3146 /* Voltage PMA Low Warn Threshold */
5995 +#define SK_SEN_PLL_3V3_LOW_ERR 2970 /* Voltage PMA Low Err Threshold */
5998 + * VAUX (YUKON only)
6000 +#define SK_SEN_VAUX_3V3_VAL 3300 /* Voltage VAUX 3.3 Volt */
6002 +#define SK_SEN_VAUX_3V3_HIGH_ERR (SK_I32)(SK_SEN_VAUX_3V3_VAL * C_PLUS_10)
6003 +#define SK_SEN_VAUX_3V3_HIGH_WARN (SK_I32)(SK_SEN_VAUX_3V3_VAL * C_PLUS_5)
6004 +#define SK_SEN_VAUX_3V3_LOW_WARN (SK_I32)(SK_SEN_VAUX_3V3_VAL * C_MINUS_5)
6005 +#define SK_SEN_VAUX_3V3_LOW_ERR (SK_I32)(SK_SEN_VAUX_3V3_VAL * C_MINUS_10)
6007 +#define SK_SEN_VAUX_RANGE_LIMITER 1000 /* 1000 mV range delimiter */
6012 +#define SK_SEN_PHY_2V5_VAL 2500 /* Voltage PHY 2.5 Volt */
6014 +#define SK_SEN_PHY_2V5_HIGH_ERR (SK_I32)(SK_SEN_PHY_2V5_VAL * C_PLUS_10)
6015 +#define SK_SEN_PHY_2V5_HIGH_WARN (SK_I32)(SK_SEN_PHY_2V5_VAL * C_PLUS_5)
6016 +#define SK_SEN_PHY_2V5_LOW_WARN (SK_I32)(SK_SEN_PHY_2V5_VAL * C_MINUS_5)
6017 +#define SK_SEN_PHY_2V5_LOW_ERR (SK_I32)(SK_SEN_PHY_2V5_VAL * C_MINUS_10)
6020 + * ASIC Core 1V5 voltage (YUKON only)
6022 +#define SK_SEN_CORE_1V5_VAL 1500 /* Voltage ASIC Core 1.5 Volt */
6024 +#define SK_SEN_CORE_1V5_HIGH_ERR (SK_I32)(SK_SEN_CORE_1V5_VAL * C_PLUS_10)
6025 +#define SK_SEN_CORE_1V5_HIGH_WARN (SK_I32)(SK_SEN_CORE_1V5_VAL * C_PLUS_5)
6026 +#define SK_SEN_CORE_1V5_LOW_WARN (SK_I32)(SK_SEN_CORE_1V5_VAL * C_MINUS_5)
6027 +#define SK_SEN_CORE_1V5_LOW_ERR (SK_I32)(SK_SEN_CORE_1V5_VAL * C_MINUS_10)
6030 + * ASIC Core 1V2 (1V3) voltage (YUKON-2 only)
6032 +#define SK_SEN_CORE_1V2_VAL 1200 /* Voltage ASIC Core 1.2 Volt */
6034 +#define SK_SEN_CORE_1V2_HIGH_ERR (SK_I32)(SK_SEN_CORE_1V2_VAL * C_PLUS_20)
6035 +#define SK_SEN_CORE_1V2_HIGH_WARN (SK_I32)(SK_SEN_CORE_1V2_VAL * C_PLUS_15)
6036 +#define SK_SEN_CORE_1V2_LOW_WARN (SK_I32)(SK_SEN_CORE_1V2_VAL * C_MINUS_5)
6037 +#define SK_SEN_CORE_1V2_LOW_ERR (SK_I32)(SK_SEN_CORE_1V2_VAL * C_MINUS_10)
6039 +#define SK_SEN_CORE_1V3_VAL 1300 /* Voltage ASIC Core 1.3 Volt */
6041 +#define SK_SEN_CORE_1V3_HIGH_ERR (SK_I32)(SK_SEN_CORE_1V3_VAL * C_PLUS_15)
6042 +#define SK_SEN_CORE_1V3_HIGH_WARN (SK_I32)(SK_SEN_CORE_1V3_VAL * C_PLUS_10)
6043 +#define SK_SEN_CORE_1V3_LOW_WARN (SK_I32)(SK_SEN_CORE_1V3_VAL * C_MINUS_5)
6044 +#define SK_SEN_CORE_1V3_LOW_ERR (SK_I32)(SK_SEN_CORE_1V3_VAL * C_MINUS_10)
6049 +/* assuming: 6500rpm +-15%, 4 pulses,
6050 + * warning at: 80 %
6054 +#define SK_SEN_FAN_HIGH_ERR 20000 /* FAN Speed High Err Threshold */
6055 +#define SK_SEN_FAN_HIGH_WARN 20000 /* FAN Speed High Warn Threshold */
6056 +#define SK_SEN_FAN_LOW_WARN 5200 /* FAN Speed Low Warn Threshold */
6057 +#define SK_SEN_FAN_LOW_ERR 4550 /* FAN Speed Low Err Threshold */
6060 + * Some Voltages need dynamic thresholds
6062 +#define SK_SEN_DYN_INIT_NONE 0 /* No dynamic init of thresholds */
6063 +#define SK_SEN_DYN_INIT_PCI_IO 10 /* Init PCI-IO with new thresholds */
6064 +#define SK_SEN_DYN_INIT_VAUX 11 /* Init VAUX with new thresholds */
6066 +extern int SkLm80ReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen);
6067 +#endif /* n_INC_SKGETWSI_H */
6069 diff -ruN linux/drivers/net/sk98lin/h/ski2c.h linux-new/drivers/net/sk98lin/h/ski2c.h
6070 --- linux/drivers/net/sk98lin/h/ski2c.h 2006-09-20 05:42:06.000000000 +0200
6071 +++ linux-new/drivers/net/sk98lin/h/ski2c.h 1970-01-01 01:00:00.000000000 +0100
6073 -/******************************************************************************
6076 - * Project: Gigabit Ethernet Adapters, TWSI-Module
6077 - * Version: $Revision$
6079 - * Purpose: Defines to access Voltage and Temperature Sensor
6081 - ******************************************************************************/
6083 -/******************************************************************************
6085 - * (C)Copyright 1998-2002 SysKonnect.
6086 - * (C)Copyright 2002-2003 Marvell.
6088 - * This program is free software; you can redistribute it and/or modify
6089 - * it under the terms of the GNU General Public License as published by
6090 - * the Free Software Foundation; either version 2 of the License, or
6091 - * (at your option) any later version.
6093 - * The information in this file is provided "AS IS" without warranty.
6095 - ******************************************************************************/
6098 - * SKI2C.H contains all I2C specific defines
6104 -typedef struct s_Sensor SK_SENSOR;
6106 -#include "h/skgei2c.h"
6109 - * Define the I2C events.
6111 -#define SK_I2CEV_IRQ 1 /* IRQ happened Event */
6112 -#define SK_I2CEV_TIM 2 /* Timeout event */
6113 -#define SK_I2CEV_CLEAR 3 /* Clear MIB Values */
6116 - * Define READ and WRITE Constants.
6119 -#define I2C_WRITE 1
6120 -#define I2C_BURST 1
6121 -#define I2C_SINGLE 0
6123 -#define SKERR_I2C_E001 (SK_ERRBASE_I2C+0)
6124 -#define SKERR_I2C_E001MSG "Sensor index unknown"
6125 -#define SKERR_I2C_E002 (SKERR_I2C_E001+1)
6126 -#define SKERR_I2C_E002MSG "TWSI: transfer does not complete"
6127 -#define SKERR_I2C_E003 (SKERR_I2C_E002+1)
6128 -#define SKERR_I2C_E003MSG "LM80: NAK on device send"
6129 -#define SKERR_I2C_E004 (SKERR_I2C_E003+1)
6130 -#define SKERR_I2C_E004MSG "LM80: NAK on register send"
6131 -#define SKERR_I2C_E005 (SKERR_I2C_E004+1)
6132 -#define SKERR_I2C_E005MSG "LM80: NAK on device (2) send"
6133 -#define SKERR_I2C_E006 (SKERR_I2C_E005+1)
6134 -#define SKERR_I2C_E006MSG "Unknown event"
6135 -#define SKERR_I2C_E007 (SKERR_I2C_E006+1)
6136 -#define SKERR_I2C_E007MSG "LM80 read out of state"
6137 -#define SKERR_I2C_E008 (SKERR_I2C_E007+1)
6138 -#define SKERR_I2C_E008MSG "Unexpected sensor read completed"
6139 -#define SKERR_I2C_E009 (SKERR_I2C_E008+1)
6140 -#define SKERR_I2C_E009MSG "WARNING: temperature sensor out of range"
6141 -#define SKERR_I2C_E010 (SKERR_I2C_E009+1)
6142 -#define SKERR_I2C_E010MSG "WARNING: voltage sensor out of range"
6143 -#define SKERR_I2C_E011 (SKERR_I2C_E010+1)
6144 -#define SKERR_I2C_E011MSG "ERROR: temperature sensor out of range"
6145 -#define SKERR_I2C_E012 (SKERR_I2C_E011+1)
6146 -#define SKERR_I2C_E012MSG "ERROR: voltage sensor out of range"
6147 -#define SKERR_I2C_E013 (SKERR_I2C_E012+1)
6148 -#define SKERR_I2C_E013MSG "ERROR: couldn't init sensor"
6149 -#define SKERR_I2C_E014 (SKERR_I2C_E013+1)
6150 -#define SKERR_I2C_E014MSG "WARNING: fan sensor out of range"
6151 -#define SKERR_I2C_E015 (SKERR_I2C_E014+1)
6152 -#define SKERR_I2C_E015MSG "ERROR: fan sensor out of range"
6153 -#define SKERR_I2C_E016 (SKERR_I2C_E015+1)
6154 -#define SKERR_I2C_E016MSG "TWSI: active transfer does not complete"
6157 - * Define Timeout values
6159 -#define SK_I2C_TIM_LONG 2000000L /* 2 seconds */
6160 -#define SK_I2C_TIM_SHORT 100000L /* 100 milliseconds */
6161 -#define SK_I2C_TIM_WATCH 1000000L /* 1 second */
6164 - * Define trap and error log hold times
6166 -#ifndef SK_SEN_ERR_TR_HOLD
6167 -#define SK_SEN_ERR_TR_HOLD (4*SK_TICKS_PER_SEC)
6169 -#ifndef SK_SEN_ERR_LOG_HOLD
6170 -#define SK_SEN_ERR_LOG_HOLD (60*SK_TICKS_PER_SEC)
6172 -#ifndef SK_SEN_WARN_TR_HOLD
6173 -#define SK_SEN_WARN_TR_HOLD (15*SK_TICKS_PER_SEC)
6175 -#ifndef SK_SEN_WARN_LOG_HOLD
6176 -#define SK_SEN_WARN_LOG_HOLD (15*60*SK_TICKS_PER_SEC)
6180 - * Defines for SenType
6182 -#define SK_SEN_UNKNOWN 0
6183 -#define SK_SEN_TEMP 1
6184 -#define SK_SEN_VOLT 2
6185 -#define SK_SEN_FAN 3
6188 - * Define for the SenErrorFlag
6190 -#define SK_SEN_ERR_NOT_PRESENT 0 /* Error Flag: Sensor not present */
6191 -#define SK_SEN_ERR_OK 1 /* Error Flag: O.K. */
6192 -#define SK_SEN_ERR_WARN 2 /* Error Flag: Warning */
6193 -#define SK_SEN_ERR_ERR 3 /* Error Flag: Error */
6194 -#define SK_SEN_ERR_FAULTY 4 /* Error Flag: Faulty */
6197 - * Define the Sensor struct
6200 - char *SenDesc; /* Description */
6201 - int SenType; /* Voltage or Temperature */
6202 - SK_I32 SenValue; /* Current value of the sensor */
6203 - SK_I32 SenThreErrHigh; /* High error Threshhold of this sensor */
6204 - SK_I32 SenThreWarnHigh; /* High warning Threshhold of this sensor */
6205 - SK_I32 SenThreErrLow; /* Lower error Threshold of the sensor */
6206 - SK_I32 SenThreWarnLow; /* Lower warning Threshold of the sensor */
6207 - int SenErrFlag; /* Sensor indicated an error */
6208 - SK_BOOL SenInit; /* Is sensor initialized ? */
6209 - SK_U64 SenErrCts; /* Error trap counter */
6210 - SK_U64 SenWarnCts; /* Warning trap counter */
6211 - SK_U64 SenBegErrTS; /* Begin error timestamp */
6212 - SK_U64 SenBegWarnTS; /* Begin warning timestamp */
6213 - SK_U64 SenLastErrTrapTS; /* Last error trap timestamp */
6214 - SK_U64 SenLastErrLogTS; /* Last error log timestamp */
6215 - SK_U64 SenLastWarnTrapTS; /* Last warning trap timestamp */
6216 - SK_U64 SenLastWarnLogTS; /* Last warning log timestamp */
6217 - int SenState; /* Sensor State (see HW specific include) */
6218 - int (*SenRead)(SK_AC *pAC, SK_IOC IoC, struct s_Sensor *pSen);
6219 - /* Sensors read function */
6220 - SK_U16 SenReg; /* Register Address for this sensor */
6221 - SK_U8 SenDev; /* Device Selection for this sensor */
6224 -typedef struct s_I2c {
6225 - SK_SENSOR SenTable[SK_MAX_SENSORS]; /* Sensor Table */
6226 - int CurrSens; /* Which sensor is currently queried */
6227 - int MaxSens; /* Max. number of sensors */
6228 - int TimerMode; /* Use the timer also to watch the state machine */
6229 - int InitLevel; /* Initialized Level */
6231 - int DummyReads; /* Number of non-checked dummy reads */
6232 - SK_TIMER SenTimer; /* Sensors timer */
6233 -#endif /* !SK_DIAG */
6236 -extern int SkI2cInit(SK_AC *pAC, SK_IOC IoC, int Level);
6238 -extern SK_U32 SkI2cRead(SK_AC *pAC, SK_IOC IoC, int Dev, int Size, int Reg,
6240 -#else /* !SK_DIAG */
6241 -extern int SkI2cEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Para);
6242 -extern void SkI2cWaitIrq(SK_AC *pAC, SK_IOC IoC);
6243 -extern void SkI2cIsr(SK_AC *pAC, SK_IOC IoC);
6244 -#endif /* !SK_DIAG */
6245 -#endif /* n_SKI2C_H */
6247 diff -ruN linux/drivers/net/sk98lin/h/skqueue.h linux-new/drivers/net/sk98lin/h/skqueue.h
6248 --- linux/drivers/net/sk98lin/h/skqueue.h 2006-09-20 05:42:06.000000000 +0200
6249 +++ linux-new/drivers/net/sk98lin/h/skqueue.h 2006-07-28 14:13:54.000000000 +0200
6253 * Project: Gigabit Ethernet Adapters, Event Scheduler Module
6254 - * Version: $Revision$
6256 + * Version: $Revision$
6258 * Purpose: Defines for the Event queue
6260 ******************************************************************************/
6262 /******************************************************************************
6265 * (C)Copyright 1998-2002 SysKonnect GmbH.
6266 * (C)Copyright 2002-2003 Marvell.
6269 * (at your option) any later version.
6271 * The information in this file is provided "AS IS" without warranty.
6274 ******************************************************************************/
6277 #define SKGE_RSF 11 /* RSF Aggregation Event Class */
6278 #define SKGE_MARKER 12 /* MARKER Aggregation Event Class */
6279 #define SKGE_FD 13 /* FD Distributor Event Class */
6281 +#define SKGE_ASF 14 /* ASF Event Class */
6285 * define event queue as circular buffer
6287 #define SKERR_Q_E001MSG "Event queue overflow"
6288 #define SKERR_Q_E002 (SKERR_Q_E001+1)
6289 #define SKERR_Q_E002MSG "Undefined event class"
6290 +#define SKERR_Q_E003 (SKERR_Q_E001+2)
6291 +#define SKERR_Q_E003MSG "Event queued in Init Level 0"
6292 +#define SKERR_Q_E004 (SKERR_Q_E001+3)
6293 +#define SKERR_Q_E004MSG "Error Reported from Event Fuction (Queue Blocked)"
6294 +#define SKERR_Q_E005 (SKERR_Q_E001+4)
6295 +#define SKERR_Q_E005MSG "Event scheduler called in Init Level 0 or 1"
6296 #endif /* _SKQUEUE_H_ */
6298 diff -ruN linux/drivers/net/sk98lin/h/skrlmt.h linux-new/drivers/net/sk98lin/h/skrlmt.h
6299 --- linux/drivers/net/sk98lin/h/skrlmt.h 2006-09-20 05:42:06.000000000 +0200
6300 +++ linux-new/drivers/net/sk98lin/h/skrlmt.h 2006-07-28 14:13:54.000000000 +0200
6304 * Project: GEnesis, PCI Gigabit Ethernet Adapter
6305 - * Version: $Revision$
6307 + * Version: $Revision$
6309 * Purpose: Header file for Redundant Link ManagemenT.
6311 ******************************************************************************/
6313 /******************************************************************************
6316 * (C)Copyright 1998-2002 SysKonnect GmbH.
6317 * (C)Copyright 2002-2003 Marvell.
6320 * (at your option) any later version.
6322 * The information in this file is provided "AS IS" without warranty.
6325 ******************************************************************************/
6327 diff -ruN linux/drivers/net/sk98lin/h/sktimer.h linux-new/drivers/net/sk98lin/h/sktimer.h
6328 --- linux/drivers/net/sk98lin/h/sktimer.h 2006-09-20 05:42:06.000000000 +0200
6329 +++ linux-new/drivers/net/sk98lin/h/sktimer.h 2006-07-28 14:13:54.000000000 +0200
6333 * Project: Gigabit Ethernet Adapters, Event Scheduler Module
6334 - * Version: $Revision$
6336 + * Version: $Revision$
6338 * Purpose: Defines for the timer functions
6340 ******************************************************************************/
6342 /******************************************************************************
6345 * (C)Copyright 1998-2002 SysKonnect GmbH.
6346 * (C)Copyright 2002-2003 Marvell.
6349 * (at your option) any later version.
6351 * The information in this file is provided "AS IS" without warranty.
6354 ******************************************************************************/
6356 diff -ruN linux/drivers/net/sk98lin/h/sktwsi.h linux-new/drivers/net/sk98lin/h/sktwsi.h
6357 --- linux/drivers/net/sk98lin/h/sktwsi.h 1970-01-01 01:00:00.000000000 +0100
6358 +++ linux-new/drivers/net/sk98lin/h/sktwsi.h 2006-07-28 14:13:54.000000000 +0200
6360 +/******************************************************************************
6363 + * Project: Gigabit Ethernet Adapters, TWSI-Module
6364 + * Version: $Revision$
6366 + * Purpose: Defines to access Voltage and Temperature Sensor
6368 + ******************************************************************************/
6370 +/******************************************************************************
6373 + * (C)Copyright 1998-2002 SysKonnect.
6374 + * (C)Copyright 2002-2003 Marvell.
6376 + * This program is free software; you can redistribute it and/or modify
6377 + * it under the terms of the GNU General Public License as published by
6378 + * the Free Software Foundation; either version 2 of the License, or
6379 + * (at your option) any later version.
6381 + * The information in this file is provided "AS IS" without warranty.
6384 + ******************************************************************************/
6387 + * SKTWSI.H contains all TWSI specific defines
6393 +typedef struct s_Sensor SK_SENSOR;
6395 +#include "h/skgetwsi.h"
6398 + * Define the TWSI events.
6400 +#define SK_I2CEV_IRQ 1 /* IRQ happened Event */
6401 +#define SK_I2CEV_TIM 2 /* Timeout event */
6402 +#define SK_I2CEV_CLEAR 3 /* Clear MIB Values */
6405 + * Define READ and WRITE Constants.
6408 +#define I2C_WRITE 1
6409 +#define I2C_BURST 1
6410 +#define I2C_SINGLE 0
6412 +#define SKERR_I2C_E001 (SK_ERRBASE_I2C+0)
6413 +#define SKERR_I2C_E001MSG "Sensor index unknown"
6414 +#define SKERR_I2C_E002 (SKERR_I2C_E001+1)
6415 +#define SKERR_I2C_E002MSG "TWSI: transfer does not complete"
6416 +#define SKERR_I2C_E003 (SKERR_I2C_E002+1)
6417 +#define SKERR_I2C_E003MSG "LM80: NAK on device send"
6418 +#define SKERR_I2C_E004 (SKERR_I2C_E003+1)
6419 +#define SKERR_I2C_E004MSG "LM80: NAK on register send"
6420 +#define SKERR_I2C_E005 (SKERR_I2C_E004+1)
6421 +#define SKERR_I2C_E005MSG "LM80: NAK on device (2) send"
6422 +#define SKERR_I2C_E006 (SKERR_I2C_E005+1)
6423 +#define SKERR_I2C_E006MSG "Unknown event"
6424 +#define SKERR_I2C_E007 (SKERR_I2C_E006+1)
6425 +#define SKERR_I2C_E007MSG "LM80 read out of state"
6426 +#define SKERR_I2C_E008 (SKERR_I2C_E007+1)
6427 +#define SKERR_I2C_E008MSG "Unexpected sensor read completed"
6428 +#define SKERR_I2C_E009 (SKERR_I2C_E008+1)
6429 +#define SKERR_I2C_E009MSG "WARNING: temperature sensor out of range"
6430 +#define SKERR_I2C_E010 (SKERR_I2C_E009+1)
6431 +#define SKERR_I2C_E010MSG "WARNING: voltage sensor out of range"
6432 +#define SKERR_I2C_E011 (SKERR_I2C_E010+1)
6433 +#define SKERR_I2C_E011MSG "ERROR: temperature sensor out of range"
6434 +#define SKERR_I2C_E012 (SKERR_I2C_E011+1)
6435 +#define SKERR_I2C_E012MSG "ERROR: voltage sensor out of range"
6436 +#define SKERR_I2C_E013 (SKERR_I2C_E012+1)
6437 +#define SKERR_I2C_E013MSG "ERROR: couldn't init sensor"
6438 +#define SKERR_I2C_E014 (SKERR_I2C_E013+1)
6439 +#define SKERR_I2C_E014MSG "WARNING: fan sensor out of range"
6440 +#define SKERR_I2C_E015 (SKERR_I2C_E014+1)
6441 +#define SKERR_I2C_E015MSG "ERROR: fan sensor out of range"
6442 +#define SKERR_I2C_E016 (SKERR_I2C_E015+1)
6443 +#define SKERR_I2C_E016MSG "TWSI: active transfer does not complete"
6446 + * Define Timeout values
6448 +#define SK_I2C_TIM_LONG 2000000L /* 2 seconds */
6449 +#define SK_I2C_TIM_SHORT 100000L /* 100 milliseconds */
6450 +#define SK_I2C_TIM_WATCH 1000000L /* 1 second */
6453 + * Define trap and error log hold times
6455 +#ifndef SK_SEN_ERR_TR_HOLD
6456 +#define SK_SEN_ERR_TR_HOLD (4*SK_TICKS_PER_SEC)
6458 +#ifndef SK_SEN_ERR_LOG_HOLD
6459 +#define SK_SEN_ERR_LOG_HOLD (60*SK_TICKS_PER_SEC)
6461 +#ifndef SK_SEN_WARN_TR_HOLD
6462 +#define SK_SEN_WARN_TR_HOLD (15*SK_TICKS_PER_SEC)
6464 +#ifndef SK_SEN_WARN_LOG_HOLD
6465 +#define SK_SEN_WARN_LOG_HOLD (15*60*SK_TICKS_PER_SEC)
6469 + * Defines for SenType
6471 +#define SK_SEN_UNKNOWN 0
6472 +#define SK_SEN_TEMP 1
6473 +#define SK_SEN_VOLT 2
6474 +#define SK_SEN_FAN 3
6477 + * Define for the SenErrorFlag
6479 +#define SK_SEN_ERR_NOT_PRESENT 0 /* Error Flag: Sensor not present */
6480 +#define SK_SEN_ERR_OK 1 /* Error Flag: O.K. */
6481 +#define SK_SEN_ERR_WARN 2 /* Error Flag: Warning */
6482 +#define SK_SEN_ERR_ERR 3 /* Error Flag: Error */
6483 +#define SK_SEN_ERR_FAULTY 4 /* Error Flag: Faulty */
6486 + * Define the Sensor struct
6489 + char *SenDesc; /* Description */
6490 + int SenType; /* Voltage or Temperature */
6491 + SK_I32 SenValue; /* Current value of the sensor */
6492 + SK_I32 SenThreErrHigh; /* High error Threshhold of this sensor */
6493 + SK_I32 SenThreWarnHigh; /* High warning Threshhold of this sensor */
6494 + SK_I32 SenThreErrLow; /* Lower error Threshold of the sensor */
6495 + SK_I32 SenThreWarnLow; /* Lower warning Threshold of the sensor */
6496 + int SenErrFlag; /* Sensor indicated an error */
6497 + SK_BOOL SenInit; /* Is sensor initialized ? */
6498 + SK_U64 SenErrCts; /* Error trap counter */
6499 + SK_U64 SenWarnCts; /* Warning trap counter */
6500 + SK_U64 SenBegErrTS; /* Begin error timestamp */
6501 + SK_U64 SenBegWarnTS; /* Begin warning timestamp */
6502 + SK_U64 SenLastErrTrapTS; /* Last error trap timestamp */
6503 + SK_U64 SenLastErrLogTS; /* Last error log timestamp */
6504 + SK_U64 SenLastWarnTrapTS; /* Last warning trap timestamp */
6505 + SK_U64 SenLastWarnLogTS; /* Last warning log timestamp */
6506 + int SenState; /* Sensor State (see HW specific include) */
6507 + int (*SenRead)(SK_AC *pAC, SK_IOC IoC, struct s_Sensor *pSen);
6508 + /* Sensors read function */
6509 + SK_U16 SenReg; /* Register Address for this sensor */
6510 + SK_U8 SenDev; /* Device Selection for this sensor */
6513 +typedef struct s_I2c {
6514 + SK_SENSOR SenTable[SK_MAX_SENSORS]; /* Sensor Table */
6515 + int CurrSens; /* Which sensor is currently queried */
6516 + int MaxSens; /* Max. number of sensors */
6517 + int TimerMode; /* Use the timer also to watch the state machine */
6518 + int InitLevel; /* Initialized Level */
6520 + int DummyReads; /* Number of non-checked dummy reads */
6521 + SK_TIMER SenTimer; /* Sensors timer */
6522 +#endif /* !SK_DIAG */
6525 +extern int SkI2cInit(SK_AC *pAC, SK_IOC IoC, int Level);
6526 +extern int SkI2cWrite(SK_AC *pAC, SK_IOC IoC, SK_U32 Data, int Dev, int Size,
6527 + int Reg, int Burst);
6528 +extern int SkI2cReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen);
6530 +extern SK_U32 SkI2cRead(SK_AC *pAC, SK_IOC IoC, int Dev, int Size, int Reg,
6532 +#else /* !SK_DIAG */
6533 +extern int SkI2cEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Para);
6534 +extern void SkI2cWaitIrq(SK_AC *pAC, SK_IOC IoC);
6535 +extern void SkI2cIsr(SK_AC *pAC, SK_IOC IoC);
6536 +#endif /* !SK_DIAG */
6537 +#endif /* n_SKTWSI_H */
6539 diff -ruN linux/drivers/net/sk98lin/h/sktypes.h linux-new/drivers/net/sk98lin/h/sktypes.h
6540 --- linux/drivers/net/sk98lin/h/sktypes.h 2006-09-20 05:42:06.000000000 +0200
6541 +++ linux-new/drivers/net/sk98lin/h/sktypes.h 2006-07-28 14:13:54.000000000 +0200
6545 * Project: GEnesis, PCI Gigabit Ethernet Adapter
6546 - * Version: $Revision$
6548 + * Version: $Revision$
6550 * Purpose: Define data types for Linux
6552 ******************************************************************************/
6554 /******************************************************************************
6556 * (C)Copyright 1998-2002 SysKonnect GmbH.
6557 - * (C)Copyright 2002-2003 Marvell.
6558 + * (C)Copyright 2002-2005 Marvell.
6560 * This program is free software; you can redistribute it and/or modify
6561 * it under the terms of the GNU General Public License as published by
6564 ******************************************************************************/
6566 -/******************************************************************************
6570 - * In this file, all data types that are needed by the common modules
6571 - * are mapped to Linux data types.
6574 - * Include File Hierarchy:
6577 - ******************************************************************************/
6579 #ifndef __INC_SKTYPES_H
6580 #define __INC_SKTYPES_H
6583 -/* defines *******************************************************************/
6586 - * Data types with a specific size. 'I' = signed, 'U' = unsigned.
6597 -#define SK_UPTR ulong /* casting pointer <-> integral */
6602 -#define SK_BOOL SK_U8
6604 -#define SK_TRUE (!SK_FALSE)
6606 -/* typedefs *******************************************************************/
6608 -/* function prototypes ********************************************************/
6609 +#define SK_I8 s8 /* 8 bits (1 byte) signed */
6610 +#define SK_U8 u8 /* 8 bits (1 byte) unsigned */
6611 +#define SK_I16 s16 /* 16 bits (2 bytes) signed */
6612 +#define SK_U16 u16 /* 16 bits (2 bytes) unsigned */
6613 +#define SK_I32 s32 /* 32 bits (4 bytes) signed */
6614 +#define SK_U32 u32 /* 32 bits (4 bytes) unsigned */
6615 +#define SK_I64 s64 /* 64 bits (8 bytes) signed */
6616 +#define SK_U64 u64 /* 64 bits (8 bytes) unsigned */
6618 +#define SK_UPTR ulong /* casting pointer <-> integral */
6620 +#define SK_BOOL SK_U8
6622 +#define SK_TRUE (!SK_FALSE)
6624 #endif /* __INC_SKTYPES_H */
6626 +/*******************************************************************************
6630 + ******************************************************************************/
6631 diff -ruN linux/drivers/net/sk98lin/h/skversion.h linux-new/drivers/net/sk98lin/h/skversion.h
6632 --- linux/drivers/net/sk98lin/h/skversion.h 2006-09-20 05:42:06.000000000 +0200
6633 +++ linux-new/drivers/net/sk98lin/h/skversion.h 2006-07-28 14:13:54.000000000 +0200
6635 /******************************************************************************
6638 + * Name: skversion.h
6639 * Project: GEnesis, PCI Gigabit Ethernet Adapter
6640 - * Version: $Revision$
6642 - * Purpose: SK specific Error log support
6643 + * Version: $Revision$
6645 + * Purpose: specific version strings and numbers
6647 ******************************************************************************/
6649 /******************************************************************************
6651 * (C)Copyright 1998-2002 SysKonnect GmbH.
6652 - * (C)Copyright 2002-2003 Marvell.
6653 + * (C)Copyright 2002-2005 Marvell.
6655 * This program is free software; you can redistribute it and/or modify
6656 * it under the terms of the GNU General Public License as published by
6659 ******************************************************************************/
6662 -static const char SysKonnectFileId[] = "@(#) (C) SysKonnect GmbH.";
6663 -static const char SysKonnectBuildNumber[] =
6664 - "@(#)SK-BUILD: 6.23 PL: 01";
6665 -#endif /* !defined(lint) */
6667 -#define BOOT_STRING "sk98lin: Network Device Driver v6.23\n" \
6668 - "(C)Copyright 1999-2004 Marvell(R)."
6670 -#define VER_STRING "6.23"
6671 -#define DRIVER_FILE_NAME "sk98lin"
6672 -#define DRIVER_REL_DATE "Feb-13-2004"
6674 +#define BOOT_STRING "sk98lin: Network Device Driver v8.36.1.3\n" \
6675 + "(C)Copyright 1999-2006 Marvell(R)."
6676 +#define VER_STRING "8.36.1.3"
6677 +#define PATCHLEVEL "01"
6678 +#define DRIVER_FILE_NAME "sk98lin"
6679 +#define DRIVER_REL_DATE "Jul-28-2006"
6681 +/*******************************************************************************
6685 + ******************************************************************************/
6686 diff -ruN linux/drivers/net/sk98lin/h/skvpd.h linux-new/drivers/net/sk98lin/h/skvpd.h
6687 --- linux/drivers/net/sk98lin/h/skvpd.h 2006-09-20 05:42:06.000000000 +0200
6688 +++ linux-new/drivers/net/sk98lin/h/skvpd.h 2006-07-28 14:13:54.000000000 +0200
6690 /******************************************************************************
6693 - * Project: GEnesis, PCI Gigabit Ethernet Adapter
6694 - * Version: $Revision$
6696 + * Project: Gigabit Ethernet Adapters, VPD-Module
6697 + * Version: $Revision$
6699 * Purpose: Defines and Macros for VPD handling
6701 ******************************************************************************/
6703 /******************************************************************************
6705 - * (C)Copyright 1998-2003 SysKonnect GmbH.
6707 + * (C)Copyright 1998-2002 SysKonnect.
6708 + * (C)Copyright 2002-2004 Marvell.
6710 * This program is free software; you can redistribute it and/or modify
6711 * it under the terms of the GNU General Public License as published by
6712 * the Free Software Foundation; either version 2 of the License, or
6713 * (at your option) any later version.
6715 * The information in this file is provided "AS IS" without warranty.
6718 ******************************************************************************/
6722 * Define Resource Type Identifiers and VPD keywords
6724 -#define RES_ID 0x82 /* Resource Type ID String (Product Name) */
6725 +#define RES_ID 0x82 /* Resource Type ID String (Product Name) */
6726 #define RES_VPD_R 0x90 /* start of VPD read only area */
6727 #define RES_VPD_W 0x91 /* start of VPD read/write area */
6728 #define RES_END 0x78 /* Resource Type End Tag */
6730 #define VPD_NAME "Name" /* Product Name, VPD name of RES_ID */
6731 #endif /* VPD_NAME */
6732 #define VPD_PN "PN" /* Adapter Part Number */
6733 -#define VPD_EC "EC" /* Adapter Engineering Level */
6734 +#define VPD_EC "EC" /* Adapter Engineering Level */
6735 #define VPD_MN "MN" /* Manufacture ID */
6736 #define VPD_SN "SN" /* Serial Number */
6737 #define VPD_CP "CP" /* Extended Capability */
6738 #define VPD_RV "RV" /* Checksum and Reserved */
6739 -#define VPD_YA "YA" /* Asset Tag Identifier */
6740 +#define VPD_YA "YA" /* Asset Tag Identifier */
6741 #define VPD_VL "VL" /* First Error Log Message (SK specific) */
6742 #define VPD_VF "VF" /* Second Error Log Message (SK specific) */
6743 +#define VPD_VB "VB" /* Boot Agent ROM Configuration (SK specific) */
6744 +#define VPD_VE "VE" /* EFI UNDI Configuration (SK specific) */
6745 #define VPD_RW "RW" /* Remaining Read / Write Area */
6747 /* 'type' values for vpd_setup_para() */
6749 #define VPD_RW_KEY 2 /* RW keys are "Yx", "Vx", and "RW" */
6751 /* 'op' values for vpd_setup_para() */
6752 -#define ADD_KEY 1 /* add the key at the pos "RV" or "RW" */
6753 +#define ADD_KEY 1 /* add the key at the pos "RV" or "RW" */
6754 #define OWR_KEY 2 /* overwrite key if already exists */
6759 #define VPD_DEV_ID_GENESIS 0x4300
6761 -#define VPD_SIZE_YUKON 256
6762 -#define VPD_SIZE_GENESIS 512
6763 -#define VPD_SIZE 512
6764 +#define VPD_SIZE_YUKON 256
6765 +#define VPD_SIZE_GENESIS 512
6766 +#define VPD_SIZE 512
6767 #define VPD_READ 0x0000
6768 #define VPD_WRITE 0x8000
6770 #define VPD_STOP(pAC,IoC) VPD_OUT16(pAC,IoC,PCI_VPD_ADR_REG,VPD_WRITE)
6772 -#define VPD_GET_RES_LEN(p) ((unsigned int) \
6773 - (* (SK_U8 *)&(p)[1]) |\
6774 - ((* (SK_U8 *)&(p)[2]) << 8))
6775 -#define VPD_GET_VPD_LEN(p) ((unsigned int)(* (SK_U8 *)&(p)[2]))
6776 +#define VPD_GET_RES_LEN(p) ((unsigned int)\
6777 + (*(SK_U8 *)&(p)[1]) |\
6778 + ((*(SK_U8 *)&(p)[2]) << 8))
6779 +#define VPD_GET_VPD_LEN(p) ((unsigned int)(*(SK_U8 *)&(p)[2]))
6780 #define VPD_GET_VAL(p) ((char *)&(p)[3])
6782 #define VPD_MAX_LEN 50
6783 @@ -126,62 +130,78 @@
6785 * System specific VPD macros
6790 #define VPD_OUT8(pAC,IoC,Addr,Val) (void)SkPciWriteCfgByte(pAC,Addr,Val)
6791 #define VPD_OUT16(pAC,IoC,Addr,Val) (void)SkPciWriteCfgWord(pAC,Addr,Val)
6792 +#define VPD_OUT32(pAC,IoC,Addr,Val) (void)SkPciWriteCfgDWord(pAC,Addr,Val)
6793 #define VPD_IN8(pAC,IoC,Addr,pVal) (void)SkPciReadCfgByte(pAC,Addr,pVal)
6794 #define VPD_IN16(pAC,IoC,Addr,pVal) (void)SkPciReadCfgWord(pAC,Addr,pVal)
6795 #define VPD_IN32(pAC,IoC,Addr,pVal) (void)SkPciReadCfgDWord(pAC,Addr,pVal)
6796 #else /* VPD_DO_IO */
6797 -#define VPD_OUT8(pAC,IoC,Addr,Val) SK_OUT8(IoC,PCI_C(Addr),Val)
6798 -#define VPD_OUT16(pAC,IoC,Addr,Val) SK_OUT16(IoC,PCI_C(Addr),Val)
6799 -#define VPD_IN8(pAC,IoC,Addr,pVal) SK_IN8(IoC,PCI_C(Addr),pVal)
6800 -#define VPD_IN16(pAC,IoC,Addr,pVal) SK_IN16(IoC,PCI_C(Addr),pVal)
6801 -#define VPD_IN32(pAC,IoC,Addr,pVal) SK_IN32(IoC,PCI_C(Addr),pVal)
6802 +#define VPD_OUT8(pAC,IoC,Addr,Val) SK_OUT8(IoC,PCI_C(pAC,Addr),Val)
6803 +#define VPD_OUT16(pAC,IoC,Addr,Val) SK_OUT16(IoC,PCI_C(pAC,Addr),Val)
6804 +#define VPD_OUT32(pAC,IoC,Addr,Val) SK_OUT32(IoC,PCI_C(pAC,Addr),Val)
6805 +#define VPD_IN8(pAC,IoC,Addr,pVal) SK_IN8(IoC,PCI_C(pAC,Addr),pVal)
6806 +#define VPD_IN16(pAC,IoC,Addr,pVal) SK_IN16(IoC,PCI_C(pAC,Addr),pVal)
6807 +#define VPD_IN32(pAC,IoC,Addr,pVal) SK_IN32(IoC,PCI_C(pAC,Addr),pVal)
6808 #endif /* VPD_DO_IO */
6810 +#else /* SK_DIAG */
6811 #define VPD_OUT8(pAC,Ioc,Addr,Val) { \
6812 if ((pAC)->DgT.DgUseCfgCycle) \
6813 SkPciWriteCfgByte(pAC,Addr,Val); \
6815 - SK_OUT8(pAC,PCI_C(Addr),Val); \
6816 + SK_OUT8(pAC,PCI_C(pAC,Addr),Val); \
6818 #define VPD_OUT16(pAC,Ioc,Addr,Val) { \
6819 if ((pAC)->DgT.DgUseCfgCycle) \
6820 SkPciWriteCfgWord(pAC,Addr,Val); \
6822 - SK_OUT16(pAC,PCI_C(Addr),Val); \
6823 + SK_OUT16(pAC,PCI_C(pAC,Addr),Val); \
6825 +#define VPD_OUT32(pAC,Ioc,Addr,Val) { \
6826 + if ((pAC)->DgT.DgUseCfgCycle) \
6827 + SkPciWriteCfgDWord(pAC,Addr,Val); \
6829 + SK_OUT32(pAC,PCI_C(pAC,Addr),Val); \
6831 #define VPD_IN8(pAC,Ioc,Addr,pVal) { \
6832 - if ((pAC)->DgT.DgUseCfgCycle) \
6833 + if ((pAC)->DgT.DgUseCfgCycle) \
6834 SkPciReadCfgByte(pAC,Addr,pVal); \
6836 - SK_IN8(pAC,PCI_C(Addr),pVal); \
6837 + SK_IN8(pAC,PCI_C(pAC,Addr),pVal); \
6839 #define VPD_IN16(pAC,Ioc,Addr,pVal) { \
6840 - if ((pAC)->DgT.DgUseCfgCycle) \
6841 + if ((pAC)->DgT.DgUseCfgCycle) \
6842 SkPciReadCfgWord(pAC,Addr,pVal); \
6844 - SK_IN16(pAC,PCI_C(Addr),pVal); \
6845 + SK_IN16(pAC,PCI_C(pAC,Addr),pVal); \
6847 #define VPD_IN32(pAC,Ioc,Addr,pVal) { \
6848 if ((pAC)->DgT.DgUseCfgCycle) \
6849 SkPciReadCfgDWord(pAC,Addr,pVal); \
6851 - SK_IN32(pAC,PCI_C(Addr),pVal); \
6852 + SK_IN32(pAC,PCI_C(pAC,Addr),pVal); \
6854 -#endif /* nSKDIAG */
6855 +#endif /* SK_DIAG */
6857 /* function prototypes ********************************************************/
6862 extern SK_U32 VpdReadDWord(
6866 -#endif /* SKDIAG */
6867 +#endif /* SK_DIAG */
6869 +extern int VpdSetupPara(
6877 extern SK_VPD_STATUS *VpdStat(
6879 @@ -219,7 +239,17 @@
6884 +extern void VpdErrLog(
6893 +#if defined(SK_DIAG) || defined(SK_ASF)
6895 extern int VpdReadBlock(
6898 @@ -233,9 +263,12 @@
6902 -#endif /* SKDIAG */
6904 +#endif /* SK_DIAG || SK_ASF */
6906 #else /* SK_KR_PROTO */
6907 extern SK_U32 VpdReadDWord();
6908 +extern int VpdSetupPara();
6909 extern SK_VPD_STATUS *VpdStat();
6910 extern int VpdKeys();
6911 extern int VpdRead();
6913 extern int VpdWrite();
6914 extern int VpdDelete();
6915 extern int VpdUpdate();
6916 +extern void VpdErrLog();
6917 #endif /* SK_KR_PROTO */
6919 #endif /* __INC_SKVPD_H_ */
6921 diff -ruN linux/drivers/net/sk98lin/h/sky2le.h linux-new/drivers/net/sk98lin/h/sky2le.h
6922 --- linux/drivers/net/sk98lin/h/sky2le.h 1970-01-01 01:00:00.000000000 +0100
6923 +++ linux-new/drivers/net/sk98lin/h/sky2le.h 2006-07-28 14:13:54.000000000 +0200
6925 +/******************************************************************************
6928 + * Project: Gigabit Ethernet Adapters, Common Modules
6929 + * Version: $Revision$
6931 + * Purpose: Common list element definitions and access macros.
6933 + ******************************************************************************/
6935 +/******************************************************************************
6938 + * (C)Copyright 2002-2006 Marvell.
6940 + * This program is free software; you can redistribute it and/or modify
6941 + * it under the terms of the GNU General Public License as published by
6942 + * the Free Software Foundation; either version 2 of the License, or
6943 + * (at your option) any later version.
6944 + * The information in this file is provided "AS IS" without warranty.
6947 + ******************************************************************************/
6949 +#ifndef __INC_SKY2LE_H
6950 +#define __INC_SKY2LE_H
6954 +#endif /* __cplusplus */
6956 +/* defines ********************************************************************/
6958 +#define MIN_LEN_OF_LE_TAB 128
6959 +#define MAX_LEN_OF_LE_TAB 4096
6960 +#ifdef USE_POLLING_UNIT
6961 +#define NUM_LE_POLLING_UNIT 2
6963 +#define MAX_FRAG_OVERHEAD 10
6965 +/* Macro for aligning a given value */
6966 +#define SK_ALIGN_SIZE(Value, Alignment, AlignedVal) { \
6967 + (AlignedVal) = (((Value) + (Alignment) - 1) & (~((Alignment) - 1)));\
6970 +/******************************************************************************
6972 + * LE2DWord() - Converts the given Little Endian value to machine order value
6975 + * This function converts the Little Endian value received as an argument to
6976 + * the machine order value.
6979 + * The converted value
6983 +#ifdef SK_LITTLE_ENDIAN
6985 +#ifndef SK_USE_REV_DESC
6986 +#define LE2DWord(value) (value)
6987 +#else /* SK_USE_REV_DESC */
6988 +#define LE2DWord(value) \
6989 + ((((value)<<24L) & 0xff000000L) + \
6990 + (((value)<< 8L) & 0x00ff0000L) + \
6991 + (((value)>> 8L) & 0x0000ff00L) + \
6992 + (((value)>>24L) & 0x000000ffL))
6993 +#endif /* SK_USE_REV_DESC */
6995 +#else /* !SK_LITTLE_ENDIAN */
6997 +#ifndef SK_USE_REV_DESC
6998 +#define LE2DWord(value) \
6999 + ((((value)<<24L) & 0xff000000L) + \
7000 + (((value)<< 8L) & 0x00ff0000L) + \
7001 + (((value)>> 8L) & 0x0000ff00L) + \
7002 + (((value)>>24L) & 0x000000ffL))
7003 +#else /* SK_USE_REV_DESC */
7004 +#define LE2DWord(value) (value)
7005 +#endif /* SK_USE_REV_DESC */
7007 +#endif /* !SK_LITTLE_ENDIAN */
7009 +/******************************************************************************
7011 + * DWord2LE() - Converts the given value to a Little Endian value
7014 + * This function converts the value received as an argument to a Little Endian
7015 + * value on Big Endian machines. If the machine running the code is Little
7016 + * Endian, then no conversion is done.
7019 + * The converted value
7023 +#ifdef SK_LITTLE_ENDIAN
7025 +#ifndef SK_USE_REV_DESC
7026 +#define DWord2LE(value) (value)
7027 +#else /* SK_USE_REV_DESC */
7028 +#define DWord2LE(value) \
7029 + ((((value)<<24L) & 0xff000000L) + \
7030 + (((value)<< 8L) & 0x00ff0000L) + \
7031 + (((value)>> 8L) & 0x0000ff00L) + \
7032 + (((value)>>24L) & 0x000000ffL))
7033 +#endif /* SK_USE_REV_DESC */
7035 +#else /* !SK_LITTLE_ENDIAN */
7037 +#ifndef SK_USE_REV_DESC
7038 +#define DWord2LE(value) \
7039 + ((((value)<<24L) & 0xff000000L) + \
7040 + (((value)<< 8L) & 0x00ff0000L) + \
7041 + (((value)>> 8L) & 0x0000ff00L) + \
7042 + (((value)>>24L) & 0x000000ffL))
7043 +#else /* SK_USE_REV_DESC */
7044 +#define DWord2LE(value) (value)
7045 +#endif /* SK_USE_REV_DESC */
7046 +#endif /* !SK_LITTLE_ENDIAN */
7048 +/******************************************************************************
7050 + * LE2Word() - Converts the given Little Endian value to machine order value
7053 + * This function converts the Little Endian value received as an argument to
7054 + * the machine order value.
7057 + * The converted value
7061 +#ifdef SK_LITTLE_ENDIAN
7062 +#ifndef SK_USE_REV_DESC
7063 +#define LE2Word(value) (value)
7064 +#else /* SK_USE_REV_DESC */
7065 +#define LE2Word(value) \
7066 + ((((value)<< 8L) & 0xff00) + \
7067 + (((value)>> 8L) & 0x00ff))
7068 +#endif /* SK_USE_REV_DESC */
7070 +#else /* !SK_LITTLE_ENDIAN */
7071 +#ifndef SK_USE_REV_DESC
7072 +#define LE2Word(value) \
7073 + ((((value)<< 8L) & 0xff00) + \
7074 + (((value)>> 8L) & 0x00ff))
7075 +#else /* SK_USE_REV_DESC */
7076 +#define LE2Word(value) (value)
7077 +#endif /* SK_USE_REV_DESC */
7078 +#endif /* !SK_LITTLE_ENDIAN */
7080 +/******************************************************************************
7082 + * Word2LE() - Converts the given value to a Little Endian value
7085 + * This function converts the value received as an argument to a Little Endian
7086 + * value on Big Endian machines. If the machine running the code is Little
7087 + * Endian, then no conversion is done.
7090 + * The converted value
7094 +#ifdef SK_LITTLE_ENDIAN
7095 +#ifndef SK_USE_REV_DESC
7096 +#define Word2LE(value) (value)
7097 +#else /* SK_USE_REV_DESC */
7098 +#define Word2LE(value) \
7099 + ((((value)<< 8L) & 0xff00) + \
7100 + (((value)>> 8L) & 0x00ff))
7101 +#endif /* SK_USE_REV_DESC */
7103 +#else /* !SK_LITTLE_ENDIAN */
7104 +#ifndef SK_USE_REV_DESC
7105 +#define Word2LE(value) \
7106 + ((((value)<< 8L) & 0xff00) + \
7107 + (((value)>> 8L) & 0x00ff))
7108 +#else /* SK_USE_REV_DESC */
7109 +#define Word2LE(value) (value)
7110 +#endif /* SK_USE_REV_DESC */
7111 +#endif /* !SK_LITTLE_ENDIAN */
7113 +/******************************************************************************
7115 + * Transmit list element macros
7119 +#define TXLE_SET_ADDR(pLE, Addr) \
7120 + ((pLE)->Tx.TxUn.BufAddr = DWord2LE(Addr))
7121 +#define TXLE_SET_LSLEN(pLE, Len) \
7122 + ((pLE)->Tx.TxUn.LargeSend.Length = Word2LE(Len))
7123 +#define TXLE_SET_STACS(pLE, Start) \
7124 + ((pLE)->Tx.TxUn.ChkSum.TxTcpSp = Word2LE(Start))
7125 +#define TXLE_SET_WRICS(pLE, Write) \
7126 + ((pLE)->Tx.TxUn.ChkSum.TxTcpWp = Word2LE(Write))
7127 +#define TXLE_SET_INICS(pLE, Ini) ((pLE)->Tx.Send.InitCsum = Word2LE(Ini))
7128 +#define TXLE_SET_LEN(pLE, Len) ((pLE)->Tx.Send.BufLen = Word2LE(Len))
7129 +#define TXLE_SET_VLAN(pLE, Vlan) ((pLE)->Tx.Send.VlanTag = Word2LE(Vlan))
7130 +#define TXLE_SET_LCKCS(pLE, Lock) ((pLE)->Tx.ControlFlags = (Lock))
7131 +#define TXLE_SET_CTRL(pLE, Ctrl) ((pLE)->Tx.ControlFlags = (Ctrl))
7132 +#define TXLE_SET_OPC(pLE, Opc) ((pLE)->Tx.Opcode = (Opc))
7134 +#define TXLE_GET_ADDR(pLE) LE2DWord((pLE)->Tx.TxUn.BufAddr)
7135 +#define TXLE_GET_LSLEN(pLE) LE2Word((pLE)->Tx.TxUn.LargeSend.Length)
7136 +#define TXLE_GET_STACS(pLE) LE2Word((pLE)->Tx.TxUn.ChkSum.TxTcpSp)
7137 +#define TXLE_GET_WRICS(pLE) LE2Word((pLE)->Tx.TxUn.ChkSum.TxTcpWp)
7138 +#define TXLE_GET_INICS(pLE) LE2Word((pLE)->Tx.Send.InitCsum)
7139 +#define TXLE_GET_LEN(pLE) LE2Word((pLE)->Tx.Send.BufLen)
7140 +#define TXLE_GET_VLAN(pLE) LE2Word((pLE)->Tx.Send.VlanTag)
7141 +#define TXLE_GET_LCKCS(pLE) ((pLE)->Tx.ControlFlags)
7142 +#define TXLE_GET_CTRL(pLE) ((pLE)->Tx.ControlFlags)
7143 +#define TXLE_GET_OPC(pLE) ((pLE)->Tx.Opcode)
7145 +/******************************************************************************
7147 + * Receive list element macros
7151 +#define RXLE_SET_ADDR(pLE, Addr) \
7152 + ((pLE)->Rx.RxUn.BufAddr = (SK_U32)DWord2LE(Addr))
7153 +#define RXLE_SET_STACS2(pLE, Offs) \
7154 + ((pLE)->Rx.RxUn.ChkSum.RxTcpSp2 = Word2LE(Offs))
7155 +#define RXLE_SET_STACS1(pLE, Offs) \
7156 + ((pLE)->Rx.RxUn.ChkSum.RxTcpSp1 = Word2LE(Offs))
7157 +#define RXLE_SET_LEN(pLE, Len) ((pLE)->Rx.BufferLength = Word2LE(Len))
7158 +#define RXLE_SET_CTRL(pLE, Ctrl) ((pLE)->Rx.ControlFlags = (Ctrl))
7159 +#define RXLE_SET_OPC(pLE, Opc) ((pLE)->Rx.Opcode = (Opc))
7161 +#define RXLE_GET_ADDR(pLE) LE2DWord((pLE)->Rx.RxUn.BufAddr)
7162 +#define RXLE_GET_STACS2(pLE) LE2Word((pLE)->Rx.RxUn.ChkSum.RxTcpSp2)
7163 +#define RXLE_GET_STACS1(pLE) LE2Word((pLE)->Rx.RxUn.ChkSum.RxTcpSp1)
7164 +#define RXLE_GET_LEN(pLE) LE2Word((pLE)->Rx.BufferLength)
7165 +#define RXLE_GET_CTRL(pLE) ((pLE)->Rx.ControlFlags)
7166 +#define RXLE_GET_OPC(pLE) ((pLE)->Rx.Opcode)
7168 +/******************************************************************************
7170 + * Status list element macros
7174 +#define STLE_SET_OPC(pLE, Opc) ((pLE)->St.Opcode = (Opc))
7176 +#define STLE_GET_FRSTATUS(pLE) LE2DWord((pLE)->St.StUn.StRxStatWord)
7177 +#define STLE_GET_TIST(pLE) LE2DWord((pLE)->St.StUn.StRxTimeStamp)
7178 +#define STLE_GET_TCP1(pLE) LE2Word((pLE)->St.StUn.StRxTCPCSum.RxTCPSum1)
7179 +#define STLE_GET_TCP2(pLE) LE2Word((pLE)->St.StUn.StRxTCPCSum.RxTCPSum2)
7180 +#define STLE_GET_LEN(pLE) LE2Word((pLE)->St.Stat.BufLen)
7181 +#define STLE_GET_VLAN(pLE) LE2Word((pLE)->St.Stat.VlanTag)
7182 +#define STLE_GET_LINK(pLE) ((pLE)->St.Link)
7183 +#define STLE_GET_OPC(pLE) ((pLE)->St.Opcode)
7184 +#define STLE_GET_DONE_IDX(pLE,LowVal,HighVal) { \
7185 + (LowVal) = LE2DWord((pLE)->St.StUn.StTxStatLow); \
7186 + (HighVal) = LE2Word((pLE)->St.Stat.StTxStatHi); \
7189 +#define STLE_GET_RSS(pLE) LE2DWord((pLE)->St.StUn.StRxRssValue)
7190 +#define STLE_GET_IPBIT(pLE) ((pLE)->St.Stat.Rss.FlagField & RSS_IP_FLAG)
7191 +#define STLE_GET_TCPBIT(pLE) ((pLE)->St.Stat.Rss.FlagField & RSS_TCP_FLAG)
7194 +/* always take both values as a parameter to avoid typos */
7195 +#define STLE_GET_DONE_IDX_TXA1(LowVal,HighVal) \
7196 + (((LowVal) & STLE_TXA1_MSKL) >> STLE_TXA1_SHIFTL)
7197 +#define STLE_GET_DONE_IDX_TXS1(LowVal,HighVal) \
7198 + ((LowVal & STLE_TXS1_MSKL) >> STLE_TXS1_SHIFTL)
7199 +#define STLE_GET_DONE_IDX_TXA2(LowVal,HighVal) \
7200 + (((LowVal & STLE_TXA2_MSKL) >> STLE_TXA2_SHIFTL) + \
7201 + ((HighVal & STLE_TXA2_MSKH) << STLE_TXA2_SHIFTH))
7202 +#define STLE_GET_DONE_IDX_TXS2(LowVal,HighVal) \
7203 + ((HighVal & STLE_TXS2_MSKH) >> STLE_TXS2_SHIFTH)
7206 +#define SK_Y2_RXSTAT_CHECK_PKT(Len, RxStat, IsOk) { \
7207 + (IsOk) = (((RxStat) & GMR_FS_RX_OK) != 0) && \
7208 + (((RxStat) & GMR_FS_ANY_ERR) == 0); \
7210 + if ((IsOk) && ((SK_U16)(((RxStat) & GMR_FS_LEN_MSK) >> \
7211 + GMR_FS_LEN_SHIFT) != (Len))) { \
7212 + /* length in MAC status differs from length in LE */\
7213 + (IsOk) = SK_FALSE; \
7218 +/******************************************************************************
7220 + * Polling unit list element macros
7222 + * NOTE: the Idx must be <= 0xfff and PU_PUTIDX_VALID makes them valid
7226 +#ifdef USE_POLLING_UNIT
7228 +#define POLE_SET_OPC(pLE, Opc) ((pLE)->Sa.Opcode = (Opc))
7229 +#define POLE_SET_LINK(pLE, Port) ((pLE)->Sa.Link = (Port))
7230 +#define POLE_SET_RXIDX(pLE, Idx) ((pLE)->Sa.RxIdxVld = Word2LE(Idx))
7231 +#define POLE_SET_TXAIDX(pLE, Idx) ((pLE)->Sa.TxAIdxVld = Word2LE(Idx))
7232 +#define POLE_SET_TXSIDX(pLE, Idx) ((pLE)->Sa.TxSIdxVld = Word2LE(Idx))
7234 +#define POLE_GET_OPC(pLE) ((pLE)->Sa.Opcode)
7235 +#define POLE_GET_LINK(pLE) ((pLE)->Sa.Link)
7236 +#define POLE_GET_RXIDX(pLE) LE2Word((pLE)->Sa.RxIdxVld)
7237 +#define POLE_GET_TXAIDX(pLE) LE2Word((pLE)->Sa.TxAIdxVld)
7238 +#define POLE_GET_TXSIDX(pLE) LE2Word((pLE)->Sa.TxSIdxVld)
7240 +#endif /* USE_POLLING_UNIT */
7242 +/******************************************************************************
7244 + * Debug macros for list elements
7250 +#define SK_DBG_DUMP_RX_LE(pLE) { \
7252 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7253 + ("=== RX_LIST_ELEMENT @addr: %p cont: %02x %02x %02x %02x %02x %02x %02x %02x\n", \
7254 + pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\
7255 + ((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5], \
7256 + ((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7])); \
7257 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7258 + ("\t (16bit) %04x %04x %04x %04x\n", \
7259 + ((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2], \
7260 + ((SK_U16 *) pLE)[3])); \
7261 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7262 + ("\t (32bit) %08x %08x\n", \
7263 + ((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1])); \
7264 + Opcode = RXLE_GET_OPC(pLE); \
7265 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7266 + ("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == HW_OWNER) ? \
7267 + "Hardware" : "Software")); \
7268 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7269 + ("\tOpc: 0x%x ",Opcode)); \
7270 + switch (Opcode & (~HW_OWNER)) { \
7272 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7273 + ("\tOP_BUFFER\n")); \
7276 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7277 + ("\tOP_PACKET\n")); \
7280 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7281 + ("\tOP_ADDR64\n")); \
7283 + case OP_TCPSTART: \
7284 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7285 + ("\tOP_TCPPAR\n")); \
7288 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7289 + ("\tunused LE\n")); \
7292 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7293 + ("\tunknown Opcode!!!\n")); \
7295 + if ((Opcode & OP_BUFFER) == OP_BUFFER) { \
7296 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7297 + ("\tControl: 0x%x\n", RXLE_GET_CTRL(pLE))); \
7298 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7299 + ("\tBufLen: 0x%x\n", RXLE_GET_LEN(pLE))); \
7300 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7301 + ("\tLowAddr: 0x%x\n", RXLE_GET_ADDR(pLE))); \
7303 + if ((Opcode & OP_ADDR64) == OP_ADDR64) { \
7304 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7305 + ("\tHighAddr: 0x%x\n", RXLE_GET_ADDR(pLE))); \
7307 + if ((Opcode & OP_TCPSTART) == OP_TCPSTART) { \
7308 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7309 + ("\tTCP Sum Start 1 : 0x%x\n", RXLE_GET_STACS1(pLE))); \
7310 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7311 + ("\tTCP Sum Start 2 : 0x%x\n", RXLE_GET_STACS2(pLE))); \
7313 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7314 + ("=====================\n")); \
7317 +#define SK_DBG_DUMP_TX_LE(pLE) { \
7319 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7320 + ("=== TX_LIST_ELEMENT @addr: %p cont: %02x %02x %02x %02x %02x %02x %02x %02x\n", \
7321 + pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\
7322 + ((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5], \
7323 + ((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7])); \
7324 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7325 + ("\t (16bit) %04x %04x %04x %04x\n", \
7326 + ((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2], \
7327 + ((SK_U16 *) pLE)[3])); \
7328 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7329 + ("\t (32bit) %08x %08x\n", \
7330 + ((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1])); \
7331 + Opcode = TXLE_GET_OPC(pLE); \
7332 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7333 + ("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == HW_OWNER) ? \
7334 + "Hardware" : "Software")); \
7335 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7336 + ("\tOpc: 0x%x ",Opcode)); \
7337 + switch (Opcode & (~HW_OWNER)) { \
7338 + case OP_TCPCHKSUM: \
7339 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7340 + ("\tOP_TCPCHKSUM\n")); \
7343 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7344 + ("\tOP_TCPIS\n")); \
7347 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7348 + ("\tOP_TCPLCK\n")); \
7351 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7352 + ("\tOP_TCPLW\n")); \
7355 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7356 + ("\tOP_TCPLSW\n")); \
7358 + case OP_TCPLISW: \
7359 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7360 + ("\tOP_TCPLISW\n")); \
7363 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7364 + ("\tOP_ADDR64\n")); \
7367 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7368 + ("\tOP_VLAN\n")); \
7370 + case OP_ADDR64VLAN: \
7371 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7372 + ("\tOP_ADDR64VLAN\n")); \
7375 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7376 + ("\tOP_LRGLEN\n")); \
7378 + case OP_LRGLENVLAN: \
7379 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7380 + ("\tOP_LRGLENVLAN\n")); \
7383 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7384 + ("\tOP_BUFFER\n")); \
7387 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7388 + ("\tOP_PACKET\n")); \
7390 + case OP_LARGESEND: \
7391 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7392 + ("\tOP_LARGESEND\n")); \
7395 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7396 + ("\tunused LE\n")); \
7399 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7400 + ("\tunknown Opcode!!!\n")); \
7402 + if ((Opcode & OP_BUFFER) == OP_BUFFER) { \
7403 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7404 + ("\tControl: 0x%x\n", TXLE_GET_CTRL(pLE))); \
7405 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7406 + ("\tBufLen: 0x%x\n", TXLE_GET_LEN(pLE))); \
7407 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7408 + ("\tLowAddr: 0x%x\n", TXLE_GET_ADDR(pLE))); \
7410 + if ((Opcode & OP_ADDR64) == OP_ADDR64) { \
7411 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7412 + ("\tHighAddr: 0x%x\n", TXLE_GET_ADDR(pLE))); \
7414 + if ((Opcode & OP_VLAN) == OP_VLAN) { \
7415 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7416 + ("\tVLAN Id: 0x%x\n", TXLE_GET_VLAN(pLE))); \
7418 + if ((Opcode & OP_LRGLEN) == OP_LRGLEN) { \
7419 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7420 + ("\tLarge send length: 0x%x\n", TXLE_GET_LSLEN(pLE))); \
7422 + if ((Opcode &(~HW_OWNER)) <= OP_ADDR64) { \
7423 + if ((Opcode & OP_TCPWRITE) == OP_TCPWRITE) { \
7424 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7425 + ("\tTCP Sum Write: 0x%x\n", TXLE_GET_WRICS(pLE))); \
7427 + if ((Opcode & OP_TCPSTART) == OP_TCPSTART) { \
7428 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7429 + ("\tTCP Sum Start: 0x%x\n", TXLE_GET_STACS(pLE))); \
7431 + if ((Opcode & OP_TCPINIT) == OP_TCPINIT) { \
7432 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7433 + ("\tTCP Sum Init: 0x%x\n", TXLE_GET_INICS(pLE))); \
7435 + if ((Opcode & OP_TCPLCK) == OP_TCPLCK) { \
7436 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7437 + ("\tTCP Sum Lock: 0x%x\n", TXLE_GET_LCKCS(pLE))); \
7440 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7441 + ("=====================\n")); \
7444 +#define SK_DBG_DUMP_ST_LE(pLE) { \
7448 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7449 + ("=== ST_LIST_ELEMENT @addr: %p contains: %02x %02x %02x %02x %02x %02x %02x %02x\n",\
7450 + pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\
7451 + ((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5], \
7452 + ((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7])); \
7453 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7454 + ("\t (16bit) %04x %04x %04x %04x\n", \
7455 + ((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2], \
7456 + ((SK_U16 *) pLE)[3])); \
7457 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7458 + ("\t (32bit) %08x %08x\n", \
7459 + ((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1])); \
7460 + Opcode = STLE_GET_OPC(pLE); \
7461 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7462 + ("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == SW_OWNER) ? \
7463 + "Hardware" : "Software")); \
7464 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7465 + ("\tOpc: 0x%x", Opcode)); \
7466 + Opcode &= (~HW_OWNER); \
7467 + switch (Opcode) { \
7469 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7470 + ("\tOP_RXSTAT\n")); \
7472 + case OP_RXTIMESTAMP: \
7473 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7474 + ("\tOP_RXTIMESTAMP\n")); \
7477 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7478 + ("\tOP_RXVLAN\n")); \
7481 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7482 + ("\tOP_RXCHKS\n")); \
7484 + case OP_RXCHKSVLAN: \
7485 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7486 + ("\tOP_RXCHKSVLAN\n")); \
7488 + case OP_RXTIMEVLAN: \
7489 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7490 + ("\tOP_RXTIMEVLAN\n")); \
7492 + case OP_RSS_HASH: \
7493 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7494 + ("\tOP_RSS_HASH\n")); \
7496 + case OP_TXINDEXLE: \
7497 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7498 + ("\tOP_TXINDEXLE\n")); \
7501 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7502 + ("\tunused LE\n")); \
7505 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7506 + ("\tunknown status list element!!!\n")); \
7508 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7509 + ("\tPort: %c\n", 'A' + STLE_GET_LINK(pLE))); \
7510 + if (Opcode == OP_RXSTAT) { \
7511 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7512 + ("\tFrameLen: 0x%x\n", STLE_GET_LEN(pLE))); \
7513 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7514 + ("\tFrameStat: 0x%x\n", STLE_GET_FRSTATUS(pLE))); \
7516 + if ((Opcode & OP_RXVLAN) == OP_RXVLAN) { \
7517 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7518 + ("\tVLAN Id: 0x%x\n", STLE_GET_VLAN(pLE))); \
7520 + if ((Opcode & OP_RXTIMESTAMP) == OP_RXTIMESTAMP) { \
7521 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7522 + ("\tTimestamp: 0x%x\n", STLE_GET_TIST(pLE))); \
7524 + if ((Opcode & OP_RXCHKS) == OP_RXCHKS) { \
7525 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7526 + ("\tTCP: 0x%x 0x%x\n", STLE_GET_TCP1(pLE), \
7527 + STLE_GET_TCP2(pLE))); \
7529 + if (Opcode == OP_TXINDEXLE) { \
7530 + STLE_GET_DONE_IDX(pLE, LowVal, HighVal); \
7531 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7532 + ("\tTx Index TxA1: 0x%x\n", \
7533 + STLE_GET_DONE_IDX_TXA1(LowVal,HighVal))); \
7534 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7535 + ("\tTx Index TxS1: 0x%x\n", \
7536 + STLE_GET_DONE_IDX_TXS1(LowVal,HighVal))); \
7537 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7538 + ("\tTx Index TxA2: 0x%x\n", \
7539 + STLE_GET_DONE_IDX_TXA2(LowVal,HighVal))); \
7540 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7541 + ("\tTx Index TxS2: 0x%x\n", \
7542 + STLE_GET_DONE_IDX_TXS2(LowVal,HighVal))); \
7544 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7545 + ("=====================\n")); \
7548 +#ifdef USE_POLLING_UNIT
7549 +#define SK_DBG_DUMP_PO_LE(pLE) { \
7552 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7553 + ("=== PO_LIST_ELEMENT @addr: %p cont: %02x %02x %02x %02x %02x %02x %02x %02x\n", \
7554 + pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\
7555 + ((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5], \
7556 + ((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7])); \
7557 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7558 + ("\t (16bit) %04x %04x %04x %04x\n", \
7559 + ((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2], \
7560 + ((SK_U16 *) pLE)[3])); \
7561 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7562 + ("\t (32bit) %08x %08x\n", \
7563 + ((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1])); \
7564 + Opcode = POLE_GET_OPC(pLE); \
7565 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7566 + ("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == HW_OWNER) ? \
7567 + "Hardware" : "Software")); \
7568 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7569 + ("\tOpc: 0x%x ",Opcode)); \
7570 + if ((Opcode & ~HW_OWNER) == OP_PUTIDX) { \
7571 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7572 + ("\tOP_PUTIDX\n")); \
7575 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7576 + ("\tunknown Opcode!!!\n")); \
7578 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7579 + ("\tPort %c\n", 'A' + POLE_GET_LINK(pLE))); \
7580 + Idx = POLE_GET_TXAIDX(pLE); \
7581 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7582 + ("\tTxA Index is 0x%X and %svalid\n", Idx, \
7583 + (Idx & PU_PUTIDX_VALID) ? "" : "not ")); \
7584 + Idx = POLE_GET_TXSIDX(pLE); \
7585 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7586 + ("\tTxS Index is 0x%X and %svalid\n", Idx, \
7587 + (Idx & PU_PUTIDX_VALID) ? "" : "not ")); \
7588 + Idx = POLE_GET_RXIDX(pLE); \
7589 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7590 + ("\tRx Index is 0x%X and %svalid\n", Idx, \
7591 + (Idx & PU_PUTIDX_VALID) ? "" : "not ")); \
7592 + SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7593 + ("=====================\n")); \
7595 +#endif /* USE_POLLING_UNIT */
7599 +#define SK_DBG_DUMP_RX_LE(pLE)
7600 +#define SK_DBG_DUMP_TX_LE(pLE)
7601 +#define SK_DBG_DUMP_ST_LE(pLE)
7602 +#define SK_DBG_DUMP_PO_LE(pLE)
7604 +#endif /* !DEBUG */
7606 +/******************************************************************************
7608 + * Macros for listelement tables
7613 +#define LE_SIZE sizeof(SK_HWLE)
7614 +#define LE_TAB_SIZE(NumElements) ((NumElements) * LE_SIZE)
7616 +/* Number of unused list elements in table
7617 + * this macro always returns the number of free listelements - 1
7618 + * this way we want to guarantee that always one LE remains unused
7620 +#define NUM_FREE_LE_IN_TABLE(pTable) \
7621 + ( ((pTable)->Put >= (pTable)->Done) ? \
7622 + (NUM_LE_IN_TABLE(pTable) - (pTable)->Put + (pTable)->Done - 1) :\
7623 + ((pTable)->Done - (pTable)->Put - 1) )
7625 +/* total number of list elements in table */
7626 +#define NUM_LE_IN_TABLE(pTable) ((pTable)->Num)
7628 +/* get next unused Rx list element */
7629 +#define GET_RX_LE(pLE, pTable) { \
7630 + pLE = &(pTable)->pLETab[(pTable)->Put]; \
7631 + (pTable)->Put = ((pTable)->Put + 1) & (NUM_LE_IN_TABLE(pTable) - 1);\
7634 +/* get next unused Tx list element */
7635 +#define GET_TX_LE(pLE, pTable) GET_RX_LE(pLE, pTable)
7637 +/* get next status list element expected to be finished by hw */
7638 +#define GET_ST_LE(pLE, pTable) { \
7639 + pLE = &(pTable)->pLETab[(pTable)->Done]; \
7640 + (pTable)->Done = ((pTable)->Done +1) & (NUM_LE_IN_TABLE(pTable) - 1);\
7643 +#ifdef USE_POLLING_UNIT
7644 +/* get next polling unit list element for port */
7645 +#define GET_PO_LE(pLE, pTable, Port) { \
7646 + pLE = &(pTable)->pLETab[(Port)]; \
7648 +#endif /* USE_POLLING_UNIT */
7650 +#define GET_PUT_IDX(pTable) ((pTable)->Put)
7652 +#define UPDATE_HWPUT_IDX(pTable) {(pTable)->HwPut = (pTable)->Put; }
7655 + * get own bit of next status LE
7656 + * if the result is != 0 there has been at least one status LE finished
7658 +#define OWN_OF_FIRST_LE(pTable) \
7659 + (STLE_GET_OPC(&(pTable)->pLETab[(pTable)->Done]) & HW_OWNER)
7661 +#define SET_DONE_INDEX(pTable, Idx) (pTable)->Done = (Idx);
7663 +#define GET_DONE_INDEX(pTable) ((pTable)->Done)
7665 +#ifdef SAFE_BUT_SLOW
7667 +/* check own bit of LE before current done idx */
7668 +#define CHECK_STLE_OVERFLOW(pTable, IsOk) { \
7670 + if ((i = (pTable)->Done) == 0) { \
7671 + i = NUM_LE_IN_TABLE(pTable); \
7676 + if (STLE_GET_OPC(&(pTable)->pLETab[i]) == HW_OWNER) { \
7677 + (IsOk) = SK_TRUE; \
7680 + (IsOk) = SK_FALSE; \
7686 + * for Yukon-2 the hardware is not polling the list elements, so it
7687 + * is not necessary to change the own-bit of Rx or Tx LEs before
7689 + * but it might make debugging easier if one simply can see whether
7690 + * a LE has been worked on
7693 +#define CLEAR_LE_OWN(pTable, Idx) \
7694 + STLE_SET_OPC(&(pTable)->pLETab[(Idx)], SW_OWNER)
7697 + * clear all own bits starting from old done index up to the LE before
7698 + * the new done index
7700 +#define CLEAR_LE_OWN_FROM_DONE_TO(pTable, To) { \
7702 + i = (pTable)->Done; \
7703 + while (i != To) { \
7704 + CLEAR_LE_OWN(pTable, i); \
7705 + i = (i + 1) & (NUM_LE_IN_TABLE(pTable) - 1); \
7709 +#else /* !SAFE_BUT_SLOW */
7711 +#define CHECK_STLE_OVERFLOW(pTable, IsOk)
7712 +#define CLEAR_LE_OWN(pTable, Idx)
7713 +#define CLEAR_LE_OWN_FROM_DONE_TO(pTable, To)
7715 +#endif /* !SAFE_BUT_SLOW */
7718 +/* typedefs *******************************************************************/
7720 +typedef struct s_LetRxTx {
7721 + SK_U16 VlanId; /* VLAN Id given down last time */
7722 + SK_U16 TcpWp; /* TCP Checksum Write Position */
7723 + SK_U16 TcpSp1; /* TCP Checksum Calculation Start Position 1 */
7724 + SK_U16 TcpSp2; /* TCP Checksum Calculation Start Position 2 */
7725 + SK_U16 MssValue; /* Maximum Segment Size */
7726 + SK_U16 Reserved1; /* reserved word for furture extensions */
7727 + SK_U16 Reserved2; /* reserved word for furture extensions */
7728 + SK_U16 Reserved3; /* reserved word for furture extensions */
7731 +typedef struct s_LetStat {
7732 + SK_U32 RxTimeStamp; /* Receive Timestamp */
7733 + SK_U32 RssHashValue; /* RSS Hash Value */
7734 + SK_BOOL RssIsIp; /* RSS Hash Value: IP packet detected */
7735 + SK_BOOL RssIsTcp; /* RSS Hash Value: IP+TCP packet detected */
7736 + SK_U16 VlanId; /* VLAN Id given received by Status BMU */
7737 + SK_U16 TcpSum1; /* TCP checksum 1 (status BMU) */
7738 + SK_U16 TcpSum2; /* TCP checksum 2 (status BMU) */
7741 +typedef union s_LetBmuSpec {
7742 + SK_LET_RX_TX RxTx; /* Rx/Tx BMU specific variables */
7743 + SK_LET_STAT Stat; /* Status BMU specific variables */
7746 +typedef struct s_le_table {
7747 + /* all LE's between Done and HWPut are owned by the hardware */
7748 + /* all LE's between Put and Done can be used from software */
7749 + /* all LE's between HWPut and Put are currently processed in DriverSend */
7750 + unsigned Done; /* done index - consumed from HW and available */
7751 + unsigned Put; /* put index - to be given to hardware */
7752 + unsigned HwPut; /* put index actually given to hardware */
7753 + unsigned Num; /* total number of list elements */
7754 + SK_HWLE *pLETab; /* virtual address of list element table */
7755 + SK_U32 pPhyLETABLow; /* physical address of list element table */
7756 + SK_U32 pPhyLETABHigh; /* physical address of list element table */
7757 + /* values to remember in order to save some LEs */
7758 + SK_U32 BufHighAddr; /* high address given down last time */
7759 + SK_LET_BMU_S Bmu; /* contains BMU specific information */
7760 + SK_U32 Private; /* driver private variable free usable */
7761 + SK_U16 TcpInitCsum; /* init checksum */
7764 +/* function prototypes ********************************************************/
7766 +#ifndef SK_KR_PROTO
7769 + * public functions in sky2le.c
7771 +extern void SkGeY2SetPutIndex(
7774 + SK_U32 StartAddrPrefetchUnit,
7775 + SK_LE_TABLE *pLETab);
7777 +extern void SkGeY2InitPrefetchUnit(
7780 + unsigned int Queue,
7781 + SK_LE_TABLE *pLETab);
7783 +extern void SkGeY2InitStatBmu(
7786 + SK_LE_TABLE *pLETab);
7788 +extern void SkGeY2InitPollUnit(
7791 + SK_LE_TABLE *pLETab);
7793 +extern void SkGeY2InitSingleLETable(
7795 + SK_LE_TABLE *pLETab,
7796 + unsigned int NumLE,
7798 + SK_U32 PMemLowAddr,
7799 + SK_U32 PMemHighAddr);
7801 +#else /* SK_KR_PROTO */
7802 +extern void SkGeY2SetPutIndex();
7803 +extern void SkGeY2InitPrefetchUnit();
7804 +extern void SkGeY2InitStatBmu();
7805 +extern void SkGeY2InitPollUnit();
7806 +extern void SkGeY2InitSingleLETable();
7807 +#endif /* SK_KR_PROTO */
7811 +#endif /* __cplusplus */
7813 +#endif /* __INC_SKY2LE_H */
7815 diff -ruN linux/drivers/net/sk98lin/h/xmac_ii.h linux-new/drivers/net/sk98lin/h/xmac_ii.h
7816 --- linux/drivers/net/sk98lin/h/xmac_ii.h 2006-09-20 05:42:06.000000000 +0200
7817 +++ linux-new/drivers/net/sk98lin/h/xmac_ii.h 2006-07-28 14:13:54.000000000 +0200
7821 * Project: Gigabit Ethernet Adapters, Common Modules
7822 - * Version: $Revision$
7824 + * Version: $Revision$
7826 * Purpose: Defines and Macros for Gigabit Ethernet Controller
7828 ******************************************************************************/
7830 /******************************************************************************
7833 * (C)Copyright 1998-2002 SysKonnect.
7834 - * (C)Copyright 2002-2003 Marvell.
7835 + * (C)Copyright 2002-2006 Marvell.
7837 * This program is free software; you can redistribute it and/or modify
7838 * it under the terms of the GNU General Public License as published by
7839 * the Free Software Foundation; either version 2 of the License, or
7840 * (at your option) any later version.
7842 * The information in this file is provided "AS IS" without warranty.
7845 ******************************************************************************/
7847 @@ -371,18 +372,18 @@
7848 /* Bit 16..6: reserved */
7849 #define XM_SC_SNP_RXC (1<<5) /* Bit 5: (sc) Snap Rx Counters */
7850 #define XM_SC_SNP_TXC (1<<4) /* Bit 4: (sc) Snap Tx Counters */
7851 -#define XM_SC_CP_RXC (1<<3) /* Bit 3: Copy Rx Counters Continuously */
7852 +#define XM_SC_CP_RXC (1<<3) /* Bit 3: Copy Rx Counters Continuously */
7853 #define XM_SC_CP_TXC (1<<2) /* Bit 2: Copy Tx Counters Continuously */
7854 #define XM_SC_CLR_RXC (1<<1) /* Bit 1: (sc) Clear Rx Counters */
7855 -#define XM_SC_CLR_TXC (1<<0) /* Bit 0: (sc) Clear Tx Counters */
7856 +#define XM_SC_CLR_TXC (1<<0) /* Bit 0: (sc) Clear Tx Counters */
7859 /* XM_RX_CNT_EV 32 bit r/o Rx Counter Event Register */
7860 /* XM_RX_EV_MSK 32 bit r/w Rx Counter Event Mask */
7861 -#define XMR_MAX_SZ_OV (1UL<<31) /* Bit 31: 1024-MaxSize Rx Cnt Ov*/
7862 -#define XMR_1023B_OV (1L<<30) /* Bit 30: 512-1023Byte Rx Cnt Ov*/
7863 -#define XMR_511B_OV (1L<<29) /* Bit 29: 256-511 Byte Rx Cnt Ov*/
7864 -#define XMR_255B_OV (1L<<28) /* Bit 28: 128-255 Byte Rx Cnt Ov*/
7865 +#define XMR_MAX_SZ_OV (1UL<<31) /* Bit 31: 1024-MaxSize Rx Cnt Ov */
7866 +#define XMR_1023B_OV (1L<<30) /* Bit 30: 512-1023Byte Rx Cnt Ov */
7867 +#define XMR_511B_OV (1L<<29) /* Bit 29: 256-511 Byte Rx Cnt Ov */
7868 +#define XMR_255B_OV (1L<<28) /* Bit 28: 128-255 Byte Rx Cnt Ov */
7869 #define XMR_127B_OV (1L<<27) /* Bit 27: 65-127 Byte Rx Cnt Ov */
7870 #define XMR_64B_OV (1L<<26) /* Bit 26: 64 Byte Rx Cnt Ov */
7871 #define XMR_UTIL_OV (1L<<25) /* Bit 25: Rx Util Cnt Overflow */
7873 #define XMR_CEX_ERR_OV (1L<<23) /* Bit 23: CEXT Err Cnt Ov */
7874 /* Bit 22: reserved */
7875 #define XMR_FCS_ERR_OV (1L<<21) /* Bit 21: Rx FCS Error Cnt Ov */
7876 -#define XMR_LNG_ERR_OV (1L<<20) /* Bit 20: Rx too Long Err Cnt Ov*/
7877 +#define XMR_LNG_ERR_OV (1L<<20) /* Bit 20: Rx too Long Err Cnt Ov */
7878 #define XMR_RUNT_OV (1L<<19) /* Bit 19: Runt Event Cnt Ov */
7879 -#define XMR_SHT_ERR_OV (1L<<18) /* Bit 18: Rx Short Ev Err Cnt Ov*/
7880 +#define XMR_SHT_ERR_OV (1L<<18) /* Bit 18: Rx Short Ev Err Cnt Ov */
7881 #define XMR_SYM_ERR_OV (1L<<17) /* Bit 17: Rx Sym Err Cnt Ov */
7882 /* Bit 16: reserved */
7883 #define XMR_CAR_ERR_OV (1L<<15) /* Bit 15: Rx Carr Ev Err Cnt Ov */
7884 @@ -401,57 +402,57 @@
7885 #define XMR_FRA_ERR_OV (1L<<12) /* Bit 12: Rx Framing Err Cnt Ov */
7886 #define XMR_FMISS_OV (1L<<11) /* Bit 11: Rx Missed Ev Cnt Ov */
7887 #define XMR_BURST (1L<<10) /* Bit 10: Rx Burst Event Cnt Ov */
7888 -#define XMR_INV_MOC (1L<<9) /* Bit 9: Rx with inv. MAC OC Ov*/
7889 +#define XMR_INV_MOC (1L<<9) /* Bit 9: Rx with inv. MAC OC Ov */
7890 #define XMR_INV_MP (1L<<8) /* Bit 8: Rx inv Pause Frame Ov */
7891 #define XMR_MCTRL_OV (1L<<7) /* Bit 7: Rx MAC Ctrl-F Cnt Ov */
7892 -#define XMR_MPAUSE_OV (1L<<6) /* Bit 6: Rx Pause MAC Ctrl-F Ov*/
7893 -#define XMR_UC_OK_OV (1L<<5) /* Bit 5: Rx Unicast Frame CntOv*/
7894 +#define XMR_MPAUSE_OV (1L<<6) /* Bit 6: Rx Pause MAC Ctrl-F Ov */
7895 +#define XMR_UC_OK_OV (1L<<5) /* Bit 5: Rx Unicast Frame Cnt Ov */
7896 #define XMR_MC_OK_OV (1L<<4) /* Bit 4: Rx Multicast Cnt Ov */
7897 #define XMR_BC_OK_OV (1L<<3) /* Bit 3: Rx Broadcast Cnt Ov */
7898 -#define XMR_OK_LO_OV (1L<<2) /* Bit 2: Octets Rx OK Low CntOv*/
7899 -#define XMR_OK_HI_OV (1L<<1) /* Bit 1: Octets Rx OK Hi Cnt Ov*/
7900 -#define XMR_OK_OV (1L<<0) /* Bit 0: Frames Received Ok Ov */
7901 +#define XMR_OK_LO_OV (1L<<2) /* Bit 2: Octets Rx OK Low Cnt Ov */
7902 +#define XMR_OK_HI_OV (1L<<1) /* Bit 1: Octets Rx OK High Cnt Ov */
7903 +#define XMR_OK_OV (1L<<0) /* Bit 0: Frames Received OK Ov */
7905 #define XMR_DEF_MSK (XMR_OK_LO_OV | XMR_OK_HI_OV)
7907 /* XM_TX_CNT_EV 32 bit r/o Tx Counter Event Register */
7908 /* XM_TX_EV_MSK 32 bit r/w Tx Counter Event Mask */
7909 /* Bit 31..26: reserved */
7910 -#define XMT_MAX_SZ_OV (1L<<25) /* Bit 25: 1024-MaxSize Tx Cnt Ov*/
7911 -#define XMT_1023B_OV (1L<<24) /* Bit 24: 512-1023Byte Tx Cnt Ov*/
7912 -#define XMT_511B_OV (1L<<23) /* Bit 23: 256-511 Byte Tx Cnt Ov*/
7913 -#define XMT_255B_OV (1L<<22) /* Bit 22: 128-255 Byte Tx Cnt Ov*/
7914 +#define XMT_MAX_SZ_OV (1L<<25) /* Bit 25: 1024-MaxSize Tx Cnt Ov */
7915 +#define XMT_1023B_OV (1L<<24) /* Bit 24: 512-1023Byte Tx Cnt Ov */
7916 +#define XMT_511B_OV (1L<<23) /* Bit 23: 256-511 Byte Tx Cnt Ov */
7917 +#define XMT_255B_OV (1L<<22) /* Bit 22: 128-255 Byte Tx Cnt Ov */
7918 #define XMT_127B_OV (1L<<21) /* Bit 21: 65-127 Byte Tx Cnt Ov */
7919 #define XMT_64B_OV (1L<<20) /* Bit 20: 64 Byte Tx Cnt Ov */
7920 #define XMT_UTIL_OV (1L<<19) /* Bit 19: Tx Util Cnt Overflow */
7921 #define XMT_UTIL_UR (1L<<18) /* Bit 18: Tx Util Cnt Underrun */
7922 -#define XMT_CS_ERR_OV (1L<<17) /* Bit 17: Tx Carr Sen Err Cnt Ov*/
7923 +#define XMT_CS_ERR_OV (1L<<17) /* Bit 17: Tx Carr Sen Err Cnt Ov */
7924 #define XMT_FIFO_UR_OV (1L<<16) /* Bit 16: Tx FIFO Ur Ev Cnt Ov */
7925 #define XMT_EX_DEF_OV (1L<<15) /* Bit 15: Tx Ex Deferall Cnt Ov */
7926 #define XMT_DEF (1L<<14) /* Bit 14: Tx Deferred Cnt Ov */
7927 #define XMT_LAT_COL_OV (1L<<13) /* Bit 13: Tx Late Col Cnt Ov */
7928 -#define XMT_ABO_COL_OV (1L<<12) /* Bit 12: Tx abo dueto Ex Col Ov*/
7929 +#define XMT_ABO_COL_OV (1L<<12) /* Bit 12: Tx abo dueto Ex Col Ov */
7930 #define XMT_MUL_COL_OV (1L<<11) /* Bit 11: Tx Mult Col Cnt Ov */
7931 #define XMT_SNG_COL (1L<<10) /* Bit 10: Tx Single Col Cnt Ov */
7932 -#define XMT_MCTRL_OV (1L<<9) /* Bit 9: Tx MAC Ctrl Counter Ov*/
7933 -#define XMT_MPAUSE (1L<<8) /* Bit 8: Tx Pause MAC Ctrl-F Ov*/
7934 +#define XMT_MCTRL_OV (1L<<9) /* Bit 9: Tx MAC Ctrl Counter Ov */
7935 +#define XMT_MPAUSE (1L<<8) /* Bit 8: Tx Pause MAC Ctrl-F Ov */
7936 #define XMT_BURST (1L<<7) /* Bit 7: Tx Burst Event Cnt Ov */
7937 #define XMT_LONG (1L<<6) /* Bit 6: Tx Long Frame Cnt Ov */
7938 #define XMT_UC_OK_OV (1L<<5) /* Bit 5: Tx Unicast Cnt Ov */
7939 #define XMT_MC_OK_OV (1L<<4) /* Bit 4: Tx Multicast Cnt Ov */
7940 #define XMT_BC_OK_OV (1L<<3) /* Bit 3: Tx Broadcast Cnt Ov */
7941 -#define XMT_OK_LO_OV (1L<<2) /* Bit 2: Octets Tx OK Low CntOv*/
7942 -#define XMT_OK_HI_OV (1L<<1) /* Bit 1: Octets Tx OK Hi Cnt Ov*/
7943 -#define XMT_OK_OV (1L<<0) /* Bit 0: Frames Tx Ok Ov */
7944 +#define XMT_OK_LO_OV (1L<<2) /* Bit 2: Octets Tx OK Low Cnt Ov */
7945 +#define XMT_OK_HI_OV (1L<<1) /* Bit 1: Octets Tx OK High Cnt Ov */
7946 +#define XMT_OK_OV (1L<<0) /* Bit 0: Frames Tx OK Ov */
7948 #define XMT_DEF_MSK (XMT_OK_LO_OV | XMT_OK_HI_OV)
7951 * Receive Frame Status Encoding
7953 -#define XMR_FS_LEN (0x3fffUL<<18) /* Bit 31..18: Rx Frame Length */
7954 -#define XMR_FS_2L_VLAN (1L<<17) /* Bit 17: tagged wh 2Lev VLAN ID*/
7955 -#define XMR_FS_1L_VLAN (1L<<16) /* Bit 16: tagged wh 1Lev VLAN ID*/
7956 +#define XMR_FS_LEN_MSK (0x3fffUL<<18) /* Bit 31..18: Rx Frame Length */
7957 +#define XMR_FS_2L_VLAN (1L<<17) /* Bit 17: Tagged wh 2Lev VLAN ID */
7958 +#define XMR_FS_1L_VLAN (1L<<16) /* Bit 16: Tagged wh 1Lev VLAN ID */
7959 #define XMR_FS_BC (1L<<15) /* Bit 15: Broadcast Frame */
7960 #define XMR_FS_MC (1L<<14) /* Bit 14: Multicast Frame */
7961 #define XMR_FS_UC (1L<<13) /* Bit 13: Unicast Frame */
7963 #define XMR_FS_ERR (1L<<1) /* Bit 1: Frame Error */
7964 #define XMR_FS_MCTRL (1L<<0) /* Bit 0: MAC Control Packet */
7966 +#define XMR_FS_LEN_SHIFT 18
7969 * XMR_FS_ERR will be set if
7970 * XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT,
7972 #define PHY_XMAC_ID0 0x02 /* 16 bit r/o PHY ID0 Register */
7973 #define PHY_XMAC_ID1 0x03 /* 16 bit r/o PHY ID1 Register */
7974 #define PHY_XMAC_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */
7975 -#define PHY_XMAC_AUNE_LP 0x05 /* 16 bit r/o Link Partner Abi Reg */
7976 +#define PHY_XMAC_AUNE_LP 0x05 /* 16 bit r/o Link Partner Ability Reg */
7977 #define PHY_XMAC_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */
7978 #define PHY_XMAC_NEPG 0x07 /* 16 bit r/w Next Page Register */
7979 #define PHY_XMAC_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */
7980 @@ -505,12 +508,12 @@
7981 #define PHY_BCOM_ID0 0x02 /* 16 bit r/o PHY ID0 Register */
7982 #define PHY_BCOM_ID1 0x03 /* 16 bit r/o PHY ID1 Register */
7983 #define PHY_BCOM_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */
7984 -#define PHY_BCOM_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */
7985 +#define PHY_BCOM_AUNE_LP 0x05 /* 16 bit r/o Link Partner Ability Reg */
7986 #define PHY_BCOM_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */
7987 #define PHY_BCOM_NEPG 0x07 /* 16 bit r/w Next Page Register */
7988 #define PHY_BCOM_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */
7989 /* Broadcom-specific registers */
7990 -#define PHY_BCOM_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Ctrl Reg */
7991 +#define PHY_BCOM_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */
7992 #define PHY_BCOM_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */
7993 /* 0x0b - 0x0e: reserved */
7994 #define PHY_BCOM_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */
7995 @@ -536,29 +539,37 @@
7996 #define PHY_MARV_ID0 0x02 /* 16 bit r/o PHY ID0 Register */
7997 #define PHY_MARV_ID1 0x03 /* 16 bit r/o PHY ID1 Register */
7998 #define PHY_MARV_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */
7999 -#define PHY_MARV_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */
8000 +#define PHY_MARV_AUNE_LP 0x05 /* 16 bit r/o Link Partner Ability Reg */
8001 #define PHY_MARV_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */
8002 #define PHY_MARV_NEPG 0x07 /* 16 bit r/w Next Page Register */
8003 #define PHY_MARV_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */
8004 /* Marvel-specific registers */
8005 -#define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Ctrl Reg */
8006 +#define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */
8007 #define PHY_MARV_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */
8008 /* 0x0b - 0x0e: reserved */
8009 #define PHY_MARV_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */
8010 -#define PHY_MARV_PHY_CTRL 0x10 /* 16 bit r/w PHY Specific Ctrl Reg */
8011 -#define PHY_MARV_PHY_STAT 0x11 /* 16 bit r/o PHY Specific Stat Reg */
8012 +#define PHY_MARV_PHY_CTRL 0x10 /* 16 bit r/w PHY Specific Control Reg */
8013 +#define PHY_MARV_PHY_STAT 0x11 /* 16 bit r/o PHY Specific Status Reg */
8014 #define PHY_MARV_INT_MASK 0x12 /* 16 bit r/w Interrupt Mask Reg */
8015 #define PHY_MARV_INT_STAT 0x13 /* 16 bit r/o Interrupt Status Reg */
8016 #define PHY_MARV_EXT_CTRL 0x14 /* 16 bit r/w Ext. PHY Specific Ctrl */
8017 #define PHY_MARV_RXE_CNT 0x15 /* 16 bit r/w Receive Error Counter */
8018 #define PHY_MARV_EXT_ADR 0x16 /* 16 bit r/w Ext. Ad. for Cable Diag. */
8019 - /* 0x17: reserved */
8020 +#define PHY_MARV_PORT_IRQ 0x17 /* 16 bit r/o Port 0 IRQ (88E1111 only) */
8021 #define PHY_MARV_LED_CTRL 0x18 /* 16 bit r/w LED Control Reg */
8022 #define PHY_MARV_LED_OVER 0x19 /* 16 bit r/w Manual LED Override Reg */
8023 #define PHY_MARV_EXT_CTRL_2 0x1a /* 16 bit r/w Ext. PHY Specific Ctrl 2 */
8024 #define PHY_MARV_EXT_P_STAT 0x1b /* 16 bit r/w Ext. PHY Spec. Stat Reg */
8025 #define PHY_MARV_CABLE_DIAG 0x1c /* 16 bit r/o Cable Diagnostic Reg */
8026 - /* 0x1d - 0x1f: reserved */
8027 +#define PHY_MARV_PAGE_ADDR 0x1d /* 16 bit r/w Extended Page Address Reg */
8028 +#define PHY_MARV_PAGE_DATA 0x1e /* 16 bit r/w Extended Page Data Reg */
8030 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
8031 +#define PHY_MARV_FE_LED_PAR 0x16 /* 16 bit r/w LED Parallel Select Reg. */
8032 +#define PHY_MARV_FE_LED_SER 0x17 /* 16 bit r/w LED Stream Select S. LED */
8033 +#define PHY_MARV_FE_VCT_TX 0x1a /* 16 bit r/w VCT Reg. for TXP/N Pins */
8034 +#define PHY_MARV_FE_VCT_RX 0x1b /* 16 bit r/o VCT Reg. for RXP/N Pins */
8035 +#define PHY_MARV_FE_SPEC_2 0x1c /* 16 bit r/w Specific Control Reg. 2 */
8037 /*----------------------------------------------------------------------------*/
8039 @@ -569,14 +580,14 @@
8040 #define PHY_LONE_ID0 0x02 /* 16 bit r/o PHY ID0 Register */
8041 #define PHY_LONE_ID1 0x03 /* 16 bit r/o PHY ID1 Register */
8042 #define PHY_LONE_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */
8043 -#define PHY_LONE_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */
8044 +#define PHY_LONE_AUNE_LP 0x05 /* 16 bit r/o Link Partner Ability Reg */
8045 #define PHY_LONE_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */
8046 #define PHY_LONE_NEPG 0x07 /* 16 bit r/w Next Page Register */
8047 #define PHY_LONE_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */
8048 /* Level One-specific registers */
8049 -#define PHY_LONE_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg*/
8050 +#define PHY_LONE_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */
8051 #define PHY_LONE_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */
8052 - /* 0x0b -0x0e: reserved */
8053 + /* 0x0b - 0x0e: reserved */
8054 #define PHY_LONE_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */
8055 #define PHY_LONE_PORT_CFG 0x10 /* 16 bit r/w Port Configuration Reg*/
8056 #define PHY_LONE_Q_STAT 0x11 /* 16 bit r/o Quick Status Reg */
8058 #define PHY_LONE_LED_CFG 0x14 /* 16 bit r/w LED Configuration Reg */
8059 #define PHY_LONE_PORT_CTRL 0x15 /* 16 bit r/w Port Control Reg */
8060 #define PHY_LONE_CIM 0x16 /* 16 bit r/o CIM Reg */
8061 - /* 0x17 -0x1c: reserved */
8062 + /* 0x17 - 0x1c: reserved */
8064 /*----------------------------------------------------------------------------*/
8066 @@ -603,14 +614,14 @@
8067 /* National-specific registers */
8068 #define PHY_NAT_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */
8069 #define PHY_NAT_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */
8070 - /* 0x0b -0x0e: reserved */
8071 + /* 0x0b - 0x0e: reserved */
8072 #define PHY_NAT_EXT_STAT 0x0f /* 16 bit r/o Extended Status Register */
8073 #define PHY_NAT_EXT_CTRL1 0x10 /* 16 bit r/o Extended Control Reg1 */
8074 #define PHY_NAT_Q_STAT1 0x11 /* 16 bit r/o Quick Status Reg1 */
8075 #define PHY_NAT_10B_OP 0x12 /* 16 bit r/o 10Base-T Operations Reg */
8076 #define PHY_NAT_EXT_CTRL2 0x13 /* 16 bit r/o Extended Control Reg1 */
8077 #define PHY_NAT_Q_STAT2 0x14 /* 16 bit r/o Quick Status Reg2 */
8078 - /* 0x15 -0x18: reserved */
8079 + /* 0x15 - 0x18: reserved */
8080 #define PHY_NAT_PHY_ADDR 0x19 /* 16 bit r/o PHY Address Register */
8086 * PHY bit definitions
8087 - * Bits defined as PHY_X_..., PHY_B_..., PHY_L_... or PHY_N_... are
8088 + * Bits defined as PHY_X_..., PHY_B_..., PHY_L_..., PHY_N_... or PHY_M_... are
8089 * XMAC/Broadcom/LevelOne/National/Marvell-specific.
8090 * All other are general.
8092 @@ -629,14 +640,14 @@
8093 /***** PHY_LONE_CTRL 16 bit r/w PHY Control Register *****/
8094 #define PHY_CT_RESET (1<<15) /* Bit 15: (sc) clear all PHY related regs */
8095 #define PHY_CT_LOOP (1<<14) /* Bit 14: enable Loopback over PHY */
8096 -#define PHY_CT_SPS_LSB (1<<13) /* Bit 13: (BC,L1) Speed select, lower bit */
8097 +#define PHY_CT_SPS_LSB (1<<13) /* Bit 13: Speed select, lower bit */
8098 #define PHY_CT_ANE (1<<12) /* Bit 12: Auto-Negotiation Enabled */
8099 -#define PHY_CT_PDOWN (1<<11) /* Bit 11: (BC,L1) Power Down Mode */
8100 -#define PHY_CT_ISOL (1<<10) /* Bit 10: (BC,L1) Isolate Mode */
8101 -#define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Auto-Negotiation */
8102 +#define PHY_CT_PDOWN (1<<11) /* Bit 11: Power Down Mode */
8103 +#define PHY_CT_ISOL (1<<10) /* Bit 10: Isolate Mode */
8104 +#define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Auto-Negotiation */
8105 #define PHY_CT_DUP_MD (1<<8) /* Bit 8: Duplex Mode */
8106 -#define PHY_CT_COL_TST (1<<7) /* Bit 7: (BC,L1) Collision Test enabled */
8107 -#define PHY_CT_SPS_MSB (1<<6) /* Bit 6: (BC,L1) Speed select, upper bit */
8108 +#define PHY_CT_COL_TST (1<<7) /* Bit 7: Collision Test enabled */
8109 +#define PHY_CT_SPS_MSB (1<<6) /* Bit 6: Speed select, upper bit */
8110 /* Bit 5..0: reserved */
8112 #define PHY_CT_SP1000 PHY_CT_SPS_MSB /* enable speed of 1000 Mbps */
8113 @@ -649,25 +660,25 @@
8114 /***** PHY_MARV_STAT 16 bit r/w PHY Status Register *****/
8115 /***** PHY_LONE_STAT 16 bit r/w PHY Status Register *****/
8116 /* Bit 15..9: reserved */
8117 - /* (BC/L1) 100/10 Mbps cap bits ignored*/
8118 + /* (BC/L1) 100/10 Mbps cap bits ignored */
8119 #define PHY_ST_EXT_ST (1<<8) /* Bit 8: Extended Status Present */
8120 /* Bit 7: reserved */
8121 -#define PHY_ST_PRE_SUP (1<<6) /* Bit 6: (BC/L1) preamble suppression */
8122 +#define PHY_ST_PRE_SUP (1<<6) /* Bit 6: Preamble Suppression */
8123 #define PHY_ST_AN_OVER (1<<5) /* Bit 5: Auto-Negotiation Over */
8124 #define PHY_ST_REM_FLT (1<<4) /* Bit 4: Remote Fault Condition Occured */
8125 #define PHY_ST_AN_CAP (1<<3) /* Bit 3: Auto-Negotiation Capability */
8126 #define PHY_ST_LSYNC (1<<2) /* Bit 2: Link Synchronized */
8127 -#define PHY_ST_JAB_DET (1<<1) /* Bit 1: (BC/L1) Jabber Detected */
8128 +#define PHY_ST_JAB_DET (1<<1) /* Bit 1: Jabber Detected */
8129 #define PHY_ST_EXT_REG (1<<0) /* Bit 0: Extended Register available */
8132 -/***** PHY_XMAC_ID1 16 bit r/o PHY ID1 Register */
8133 -/***** PHY_BCOM_ID1 16 bit r/o PHY ID1 Register */
8134 -/***** PHY_MARV_ID1 16 bit r/o PHY ID1 Register */
8135 -/***** PHY_LONE_ID1 16 bit r/o PHY ID1 Register */
8136 +/***** PHY_XMAC_ID1 16 bit r/o PHY ID1 Register */
8137 +/***** PHY_BCOM_ID1 16 bit r/o PHY ID1 Register */
8138 +/***** PHY_MARV_ID1 16 bit r/o PHY ID1 Register */
8139 +/***** PHY_LONE_ID1 16 bit r/o PHY ID1 Register */
8140 #define PHY_I1_OUI_MSK (0x3f<<10) /* Bit 15..10: Organization Unique ID */
8141 #define PHY_I1_MOD_NUM (0x3f<<4) /* Bit 9.. 4: Model Number */
8142 -#define PHY_I1_REV_MSK 0x0f /* Bit 3.. 0: Revision Number */
8143 +#define PHY_I1_REV_MSK 0xf /* Bit 3.. 0: Revision Number */
8145 /* different Broadcom PHY Ids */
8146 #define PHY_BCOM_ID1_A1 0x6041
8147 @@ -675,11 +686,21 @@
8148 #define PHY_BCOM_ID1_C0 0x6044
8149 #define PHY_BCOM_ID1_C5 0x6047
8151 +/* different Marvell PHY Ids */
8152 +#define PHY_MARV_ID0_VAL 0x0141 /* Marvell Unique Identifier */
8154 +#define PHY_MARV_ID1_B0 0x0C23 /* Yukon (PHY 88E1040 Rev.C0) */
8155 +#define PHY_MARV_ID1_B2 0x0C25 /* Yukon-Plus (PHY 88E1040 Rev.D0) */
8156 +#define PHY_MARV_ID1_C2 0x0CC2 /* Yukon-EC (PHY 88E1111 Rev.B1) */
8157 +#define PHY_MARV_ID1_Y2 0x0C91 /* Yukon-XL (PHY 88E1112 Rev.B0) */
8158 +#define PHY_MARV_ID1_FE 0x0C83 /* Yukon-FE (PHY 88E3082 Rev.A1) */
8159 +#define PHY_MARV_ID1_ECU 0x0CB0 /* Yukon-ECU (PHY 88E1149 Rev.B2?) */
8162 /***** PHY_XMAC_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
8163 /***** PHY_XMAC_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/
8164 #define PHY_AN_NXT_PG (1<<15) /* Bit 15: Request Next Page */
8165 -#define PHY_X_AN_ACK (1<<14) /* Bit 14: (ro) Acknowledge Received */
8166 +#define PHY_X_AN_ACK (1<<14) /* Bit 14: (ro) Acknowledge Received */
8167 #define PHY_X_AN_RFB (3<<12) /* Bit 13..12: Remote Fault Bits */
8168 /* Bit 11.. 9: reserved */
8169 #define PHY_X_AN_PAUSE (3<<7) /* Bit 8.. 7: Pause Bits */
8171 /* PHY_ANE_LP_NP (see XMAC) Bit 3: Link Partner can Next Page */
8172 /* PHY_ANE_LOC_NP (see XMAC) Bit 2: Local PHY can Next Page */
8173 /* PHY_ANE_RX_PG (see XMAC) Bit 1: Page Received */
8174 -#define PHY_ANE_LP_CAP (1<<0) /* Bit 0: Link Partner Auto-Neg. Cap. */
8175 +#define PHY_ANE_LP_CAP (1<<0) /* Bit 0: Link Partner Auto-Neg. Able */
8177 /***** PHY_XMAC_NEPG 16 bit r/w Next Page Register *****/
8178 /***** PHY_BCOM_NEPG 16 bit r/w Next Page Register *****/
8180 #define PHY_B_PEC_BY_MLT3 (1<<8) /* Bit 8: Bypass MLT3 Encoder */
8181 #define PHY_B_PEC_BY_RXA (1<<7) /* Bit 7: Bypass Rx Alignm. */
8182 #define PHY_B_PEC_RES_SCR (1<<6) /* Bit 6: Reset Scrambler */
8183 -#define PHY_B_PEC_EN_LTR (1<<5) /* Bit 5: Ena LED Traffic Mode */
8184 +#define PHY_B_PEC_EN_LTR (1<<5) /* Bit 5: Enable LED Traffic Mode */
8185 #define PHY_B_PEC_LED_ON (1<<4) /* Bit 4: Force LED's on */
8186 #define PHY_B_PEC_LED_OFF (1<<3) /* Bit 3: Force LED's off */
8187 #define PHY_B_PEC_EX_IPG (1<<2) /* Bit 2: Extend Tx IPG Mode */
8188 @@ -981,7 +1002,7 @@
8189 #define PHY_L_QS_DUP_MOD (1<<9) /* Bit 9: Full/Half Duplex */
8190 #define PHY_L_QS_AN (1<<8) /* Bit 8: AutoNeg is On */
8191 #define PHY_L_QS_AN_C (1<<7) /* Bit 7: AN is Complete */
8192 -#define PHY_L_QS_LLE (7<<4) /* Bit 6: Line Length Estim. */
8193 +#define PHY_L_QS_LLE (7<<4) /* Bit 6..4: Line Length Estim. */
8194 #define PHY_L_QS_PAUSE (1<<3) /* Bit 3: LP advertised Pause */
8195 #define PHY_L_QS_AS_PAUSE (1<<2) /* Bit 2: LP adv. asym. Pause */
8196 #define PHY_L_QS_ISOLATE (1<<1) /* Bit 1: CIM Isolated */
8197 @@ -1029,9 +1050,8 @@
8198 /* Bit 9..0: not described */
8200 /***** PHY_LONE_CIM 16 bit r/o CIM Reg *****/
8201 -#define PHY_L_CIM_ISOL (255<<8)/* Bit 15..8: Isolate Count */
8202 -#define PHY_L_CIM_FALSE_CAR (255<<0)/* Bit 7..0: False Carrier Count */
8204 +#define PHY_L_CIM_ISOL (0xff<<8) /* Bit 15..8: Isolate Count */
8205 +#define PHY_L_CIM_FALSE_CAR 0xff /* Bit 7..0: False Carrier Count */
8208 * Pause Bits (PHY_L_AN_ASP and PHY_L_AN_PC) encoding
8209 @@ -1041,7 +1061,6 @@
8210 #define PHY_L_P_ASYM_MD (2<<10) /* Bit 11..10: asymmetric Pause Mode */
8211 #define PHY_L_P_BOTH_MD (3<<10) /* Bit 11..10: both Pause Mode */
8217 @@ -1085,23 +1104,25 @@
8220 /***** PHY_MARV_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
8221 -/***** PHY_MARV_AUNE_LP 16 bit r/w Link Part Ability Reg *****/
8222 -#define PHY_M_AN_NXT_PG BIT_15 /* Request Next Page */
8223 -#define PHY_M_AN_ACK BIT_14 /* (ro) Acknowledge Received */
8224 -#define PHY_M_AN_RF BIT_13 /* Remote Fault */
8225 - /* Bit 12: reserved */
8226 -#define PHY_M_AN_ASP BIT_11 /* Asymmetric Pause */
8227 -#define PHY_M_AN_PC BIT_10 /* MAC Pause implemented */
8228 -#define PHY_M_AN_100_FD BIT_8 /* Advertise 100Base-TX Full Duplex */
8229 -#define PHY_M_AN_100_HD BIT_7 /* Advertise 100Base-TX Half Duplex */
8230 -#define PHY_M_AN_10_FD BIT_6 /* Advertise 10Base-TX Full Duplex */
8231 -#define PHY_M_AN_10_HD BIT_5 /* Advertise 10Base-TX Half Duplex */
8233 -/* special defines for FIBER (88E1011S only) */
8234 -#define PHY_M_AN_ASP_X BIT_8 /* Asymmetric Pause */
8235 -#define PHY_M_AN_PC_X BIT_7 /* MAC Pause implemented */
8236 -#define PHY_M_AN_1000X_AHD BIT_6 /* Advertise 10000Base-X Half Duplex */
8237 -#define PHY_M_AN_1000X_AFD BIT_5 /* Advertise 10000Base-X Full Duplex */
8238 +/***** PHY_MARV_AUNE_LP 16 bit r/w Link Partner Ability Reg *****/
8239 +#define PHY_M_AN_NXT_PG BIT_15S /* Request Next Page */
8240 +#define PHY_M_AN_ACK BIT_14S /* (ro) Acknowledge Received */
8241 +#define PHY_M_AN_RF BIT_13S /* Remote Fault */
8242 + /* Bit 12: reserved */
8243 +#define PHY_M_AN_ASP BIT_11S /* Asymmetric Pause */
8244 +#define PHY_M_AN_PC BIT_10S /* MAC Pause implemented */
8245 +#define PHY_M_AN_100_T4 BIT_9S /* Not cap. 100Base-T4 (always 0) */
8246 +#define PHY_M_AN_100_FD BIT_8S /* Advertise 100Base-TX Full Duplex */
8247 +#define PHY_M_AN_100_HD BIT_7S /* Advertise 100Base-TX Half Duplex */
8248 +#define PHY_M_AN_10_FD BIT_6S /* Advertise 10Base-TX Full Duplex */
8249 +#define PHY_M_AN_10_HD BIT_5S /* Advertise 10Base-TX Half Duplex */
8250 +#define PHY_M_AN_SEL_MSK (0x1f<<4) /* Bit 4.. 0: Selector Field Mask */
8252 +/* special defines for FIBER (88E1040S only) */
8253 +#define PHY_M_AN_ASP_X BIT_8S /* Asymmetric Pause */
8254 +#define PHY_M_AN_PC_X BIT_7S /* MAC Pause implemented */
8255 +#define PHY_M_AN_1000X_AHD BIT_6S /* Advertise 10000Base-X Half Duplex */
8256 +#define PHY_M_AN_1000X_AFD BIT_5S /* Advertise 10000Base-X Full Duplex */
8258 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
8259 #define PHY_M_P_NO_PAUSE_X (0<<7) /* Bit 8.. 7: no Pause Mode */
8260 @@ -1111,105 +1132,168 @@
8262 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
8263 #define PHY_M_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */
8264 -#define PHY_M_1000C_MSE (1<<12) /* Bit 12: Manual Master/Slave Enable */
8265 -#define PHY_M_1000C_MSC (1<<11) /* Bit 11: M/S Configuration (1=Master) */
8266 -#define PHY_M_1000C_MPD (1<<10) /* Bit 10: Multi-Port Device */
8267 -#define PHY_M_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */
8268 -#define PHY_M_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */
8269 +#define PHY_M_1000C_MSE BIT_12S /* Manual Master/Slave Enable */
8270 +#define PHY_M_1000C_MSC BIT_11S /* M/S Configuration (1=Master) */
8271 +#define PHY_M_1000C_MPD BIT_10S /* Multi-Port Device */
8272 +#define PHY_M_1000C_AFD BIT_9S /* Advertise Full Duplex */
8273 +#define PHY_M_1000C_AHD BIT_8S /* Advertise Half Duplex */
8274 /* Bit 7..0: reserved */
8276 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
8277 -#define PHY_M_PC_TX_FFD_MSK (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */
8278 -#define PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */
8279 -#define PHY_M_PC_ASS_CRS_TX (1<<11) /* Bit 11: Assert CRS on Transmit */
8280 -#define PHY_M_PC_FL_GOOD (1<<10) /* Bit 10: Force Link Good */
8281 -#define PHY_M_PC_EN_DET_MSK (3<<8) /* Bit 9.. 8: Energy Detect Mask */
8282 -#define PHY_M_PC_ENA_EXT_D (1<<7) /* Bit 7: Enable Ext. Distance (10BT) */
8283 -#define PHY_M_PC_MDIX_MSK (3<<5) /* Bit 6.. 5: MDI/MDIX Config. Mask */
8284 -#define PHY_M_PC_DIS_125CLK (1<<4) /* Bit 4: Disable 125 CLK */
8285 -#define PHY_M_PC_MAC_POW_UP (1<<3) /* Bit 3: MAC Power up */
8286 -#define PHY_M_PC_SQE_T_ENA (1<<2) /* Bit 2: SQE Test Enabled */
8287 -#define PHY_M_PC_POL_R_DIS (1<<1) /* Bit 1: Polarity Reversal Disabled */
8288 -#define PHY_M_PC_DIS_JABBER (1<<0) /* Bit 0: Disable Jabber */
8289 +#define PHY_M_PC_TX_FFD_MSK (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */
8290 +#define PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */
8291 +#define PHY_M_PC_ASS_CRS_TX BIT_11S /* Assert CRS on Transmit */
8292 +#define PHY_M_PC_FL_GOOD BIT_10S /* Force Link Good */
8293 +#define PHY_M_PC_EN_DET_MSK (3<<8) /* Bit 9.. 8: Energy Detect Mask */
8294 +#define PHY_M_PC_ENA_EXT_D BIT_7S /* Enable Ext. Distance (10BT) */
8295 +#define PHY_M_PC_MDIX_MSK (3<<5) /* Bit 6.. 5: MDI/MDIX Config. Mask */
8296 +#define PHY_M_PC_DIS_125CLK BIT_4S /* Disable 125 CLK */
8297 +#define PHY_M_PC_MAC_POW_UP BIT_3S /* MAC Power up */
8298 +#define PHY_M_PC_SQE_T_ENA BIT_2S /* SQE Test Enabled */
8299 +#define PHY_M_PC_POL_R_DIS BIT_1S /* Polarity Reversal Disabled */
8300 +#define PHY_M_PC_DIS_JABBER BIT_0S /* Disable Jabber */
8302 #define PHY_M_PC_EN_DET SHIFT8(2) /* Energy Detect (Mode 1) */
8303 #define PHY_M_PC_EN_DET_PLUS SHIFT8(3) /* Energy Detect Plus (Mode 2) */
8305 -#define PHY_M_PC_MDI_XMODE(x) SHIFT5(x)
8306 -#define PHY_M_PC_MAN_MDI 0 /* 00 = Manual MDI configuration */
8307 +#define PHY_M_PC_MDI_XMODE(x) (SHIFT5(x) & PHY_M_PC_MDIX_MSK)
8309 +#define PHY_M_PC_MAN_MDI 0 /* 00 = Manual MDI configuration */
8310 #define PHY_M_PC_MAN_MDIX 1 /* 01 = Manual MDIX configuration */
8311 #define PHY_M_PC_ENA_AUTO 3 /* 11 = Enable Automatic Crossover */
8313 +/* for Yukon-2/-EC Ultra Gigabit Ethernet PHY (88E1112/88E1149 only) */
8314 +#define PHY_M_PC_DIS_LINK_P BIT_15S /* Disable Link Pulses */
8315 +#define PHY_M_PC_DSC_MSK (7<<12) /* Bit 14..12: Downshift Counter */
8316 +#define PHY_M_PC_DOWN_S_ENA BIT_11S /* Downshift Enable */
8317 + /* !!! Errata in spec. (1 = disable) */
8319 +#define PHY_M_PC_DSC(x) (SHIFT12(x) & PHY_M_PC_DSC_MSK)
8320 + /* 000=1x; 001=2x; 010=3x; 011=4x */
8321 + /* 100=5x; 101=6x; 110=7x; 111=8x */
8323 +/* for Yukon-EC Ultra Gigabit Ethernet PHY (88E1149 only) */
8324 + /* Bit 4: reserved */
8325 +#define PHY_M_PC_COP_TX_DIS BIT_3S /* Copper Transmitter Disable */
8326 +#define PHY_M_PC_POW_D_ENA BIT_2S /* Power Down Enable */
8328 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
8329 +#define PHY_M_PC_ENA_DTE_DT BIT_15S /* Enable Data Terminal Equ. (DTE) Detect */
8330 +#define PHY_M_PC_ENA_ENE_DT BIT_14S /* Enable Energy Detect (sense & pulse) */
8331 +#define PHY_M_PC_DIS_NLP_CK BIT_13S /* Disable Normal Link Puls (NLP) Check */
8332 +#define PHY_M_PC_ENA_LIP_NP BIT_12S /* Enable Link Partner Next Page Reg. */
8333 +#define PHY_M_PC_DIS_NLP_GN BIT_11S /* Disable Normal Link Puls Generation */
8335 +#define PHY_M_PC_DIS_SCRAMB BIT_9S /* Disable Scrambler */
8336 +#define PHY_M_PC_DIS_FEFI BIT_8S /* Disable Far End Fault Indic. (FEFI) */
8338 +#define PHY_M_PC_SH_TP_SEL BIT_6S /* Shielded Twisted Pair Select */
8339 +#define PHY_M_PC_RX_FD_MSK (3<<2) /* Bit 3.. 2: Rx FIFO Depth Mask */
8341 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
8342 -#define PHY_M_PS_SPEED_MSK (3<<14) /* Bit 15..14: Speed Mask */
8343 -#define PHY_M_PS_SPEED_1000 (1<<15) /* 10 = 1000 Mbps */
8344 -#define PHY_M_PS_SPEED_100 (1<<14) /* 01 = 100 Mbps */
8345 -#define PHY_M_PS_SPEED_10 0 /* 00 = 10 Mbps */
8346 -#define PHY_M_PS_FULL_DUP (1<<13) /* Bit 13: Full Duplex */
8347 -#define PHY_M_PS_PAGE_REC (1<<12) /* Bit 12: Page Received */
8348 -#define PHY_M_PS_SPDUP_RES (1<<11) /* Bit 11: Speed & Duplex Resolved */
8349 -#define PHY_M_PS_LINK_UP (1<<10) /* Bit 10: Link Up */
8350 -#define PHY_M_PS_CABLE_MSK (3<<7) /* Bit 9.. 7: Cable Length Mask */
8351 -#define PHY_M_PS_MDI_X_STAT (1<<6) /* Bit 6: MDI Crossover Stat (1=MDIX) */
8352 -#define PHY_M_PS_DOWNS_STAT (1<<5) /* Bit 5: Downshift Status (1=downsh.) */
8353 -#define PHY_M_PS_ENDET_STAT (1<<4) /* Bit 4: Energy Detect Status (1=act) */
8354 -#define PHY_M_PS_TX_P_EN (1<<3) /* Bit 3: Tx Pause Enabled */
8355 -#define PHY_M_PS_RX_P_EN (1<<2) /* Bit 2: Rx Pause Enabled */
8356 -#define PHY_M_PS_POL_REV (1<<1) /* Bit 1: Polarity Reversed */
8357 -#define PHY_M_PC_JABBER (1<<0) /* Bit 0: Jabber */
8358 +#define PHY_M_PS_SPEED_MSK (3<<14) /* Bit 15..14: Speed Mask */
8359 +#define PHY_M_PS_SPEED_1000 BIT_15S /* 10 = 1000 Mbps */
8360 +#define PHY_M_PS_SPEED_100 BIT_14S /* 01 = 100 Mbps */
8361 +#define PHY_M_PS_SPEED_10 0 /* 00 = 10 Mbps */
8362 +#define PHY_M_PS_FULL_DUP BIT_13S /* Full Duplex */
8363 +#define PHY_M_PS_PAGE_REC BIT_12S /* Page Received */
8364 +#define PHY_M_PS_SPDUP_RES BIT_11S /* Speed & Duplex Resolved */
8365 +#define PHY_M_PS_LINK_UP BIT_10S /* Link Up */
8366 +#define PHY_M_PS_CABLE_MSK (7<<7) /* Bit 9.. 7: Cable Length Mask */
8367 +#define PHY_M_PS_MDI_X_STAT BIT_6S /* MDI Crossover Stat (1=MDIX) */
8368 +#define PHY_M_PS_DOWNS_STAT BIT_5S /* Downshift Status (1=downsh.) */
8369 +#define PHY_M_PS_ENDET_STAT BIT_4S /* Energy Detect Status (1=act) */
8370 +#define PHY_M_PS_TX_P_EN BIT_3S /* Tx Pause Enabled */
8371 +#define PHY_M_PS_RX_P_EN BIT_2S /* Rx Pause Enabled */
8372 +#define PHY_M_PS_POL_REV BIT_1S /* Polarity Reversed */
8373 +#define PHY_M_PS_JABBER BIT_0S /* Jabber */
8375 #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
8377 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
8378 +#define PHY_M_PS_DTE_DETECT BIT_15S /* Data Terminal Equipment (DTE) Detected */
8379 +#define PHY_M_PS_RES_SPEED BIT_14S /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
8381 /***** PHY_MARV_INT_MASK 16 bit r/w Interrupt Mask Reg *****/
8382 /***** PHY_MARV_INT_STAT 16 bit r/o Interrupt Status Reg *****/
8383 -#define PHY_M_IS_AN_ERROR (1<<15) /* Bit 15: Auto-Negotiation Error */
8384 -#define PHY_M_IS_LSP_CHANGE (1<<14) /* Bit 14: Link Speed Changed */
8385 -#define PHY_M_IS_DUP_CHANGE (1<<13) /* Bit 13: Duplex Mode Changed */
8386 -#define PHY_M_IS_AN_PR (1<<12) /* Bit 12: Page Received */
8387 -#define PHY_M_IS_AN_COMPL (1<<11) /* Bit 11: Auto-Negotiation Completed */
8388 -#define PHY_M_IS_LST_CHANGE (1<<10) /* Bit 10: Link Status Changed */
8389 -#define PHY_M_IS_SYMB_ERROR (1<<9) /* Bit 9: Symbol Error */
8390 -#define PHY_M_IS_FALSE_CARR (1<<8) /* Bit 8: False Carrier */
8391 -#define PHY_M_IS_FIFO_ERROR (1<<7) /* Bit 7: FIFO Overflow/Underrun Error */
8392 -#define PHY_M_IS_MDI_CHANGE (1<<6) /* Bit 6: MDI Crossover Changed */
8393 -#define PHY_M_IS_DOWNSH_DET (1<<5) /* Bit 5: Downshift Detected */
8394 -#define PHY_M_IS_END_CHANGE (1<<4) /* Bit 4: Energy Detect Changed */
8395 - /* Bit 3..2: reserved */
8396 -#define PHY_M_IS_POL_CHANGE (1<<1) /* Bit 1: Polarity Changed */
8397 -#define PHY_M_IS_JABBER (1<<0) /* Bit 0: Jabber */
8398 +#define PHY_M_IS_AN_ERROR BIT_15S /* Auto-Negotiation Error */
8399 +#define PHY_M_IS_LSP_CHANGE BIT_14S /* Link Speed Changed */
8400 +#define PHY_M_IS_DUP_CHANGE BIT_13S /* Duplex Mode Changed */
8401 +#define PHY_M_IS_AN_PR BIT_12S /* Page Received */
8402 +#define PHY_M_IS_AN_COMPL BIT_11S /* Auto-Negotiation Completed */
8403 +#define PHY_M_IS_LST_CHANGE BIT_10S /* Link Status Changed */
8404 +#define PHY_M_IS_SYMB_ERROR BIT_9S /* Symbol Error */
8405 +#define PHY_M_IS_FALSE_CARR BIT_8S /* False Carrier */
8406 +#define PHY_M_IS_FIFO_ERROR BIT_7S /* FIFO Overflow/Underrun Error */
8407 +#define PHY_M_IS_MDI_CHANGE BIT_6S /* MDI Crossover Changed */
8408 +#define PHY_M_IS_DOWNSH_DET BIT_5S /* Downshift Detected */
8409 +#define PHY_M_IS_END_CHANGE BIT_4S /* Energy Detect Changed */
8410 + /* Bit 3: reserved */
8411 +#define PHY_M_IS_DTE_CHANGE BIT_2S /* DTE Power Det. Status Changed */
8412 + /* (88E1111 only) */
8413 +#define PHY_M_IS_POL_CHANGE BIT_1S /* Polarity Changed */
8414 +#define PHY_M_IS_JABBER BIT_0S /* Jabber */
8416 #define PHY_M_DEF_MSK (PHY_M_IS_AN_ERROR | PHY_M_IS_AN_PR | \
8417 - PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR)
8418 + PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR | \
8419 + PHY_M_IS_END_CHANGE)
8421 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
8422 -#define PHY_M_EC_M_DSC_MSK (3<<10) /* Bit 11..10: Master downshift counter */
8423 -#define PHY_M_EC_S_DSC_MSK (3<<8) /* Bit 9.. 8: Slave downshift counter */
8424 +#define PHY_M_EC_ENA_BC_EXT BIT_15S /* Enable Block Carr. Ext. (88E1111 only) */
8425 +#define PHY_M_EC_ENA_LIN_LB BIT_14S /* Enable Line Loopback (88E1111 only) */
8426 + /* Bit 13: reserved */
8427 +#define PHY_M_EC_DIS_LINK_P BIT_12S /* Disable Link Pulses (88E1111 only) */
8428 +#define PHY_M_EC_M_DSC_MSK (3<<10) /* Bit 11..10: Master Downshift Counter */
8429 + /* (88E1040 Rev.C0 only) */
8430 +#define PHY_M_EC_S_DSC_MSK (3<<8) /* Bit 9.. 8: Slave Downshift Counter */
8431 + /* (88E1040 Rev.C0 only) */
8432 +#define PHY_M_EC_DSC_MSK_2 (7<<9) /* Bit 11.. 9: Downshift Counter */
8433 + /* (88E1040 Rev.D0 and higher) */
8434 +#define PHY_M_EC_DOWN_S_ENA BIT_8S /* Downshift Enable (88E1040 Rev.D0 and */
8435 + /* 88E1111 !!! Errata in spec. (1=dis.) */
8436 +#define PHY_M_EC_RX_TIM_CT BIT_7S /* RGMII Rx Timing Control*/
8437 #define PHY_M_EC_MAC_S_MSK (7<<4) /* Bit 6.. 4: Def. MAC interface speed */
8438 -#define PHY_M_EC_FIB_AN_ENA (1<<3) /* Bit 3: Fiber Auto-Neg. Enable */
8440 -#define PHY_M_EC_M_DSC(x) SHIFT10(x) /* 00=1x; 01=2x; 10=3x; 11=4x */
8441 -#define PHY_M_EC_S_DSC(x) SHIFT8(x) /* 00=dis; 01=1x; 10=2x; 11=3x */
8442 -#define PHY_M_EC_MAC_S(x) SHIFT4(x) /* 01X=0; 110=2.5; 111=25 (MHz) */
8444 +#define PHY_M_EC_FIB_AN_ENA BIT_3S /* Fiber Auto-Neg. Enable 88E1040S only) */
8445 +#define PHY_M_EC_DTE_D_ENA BIT_2S /* DTE Detect Enable (88E1111 only) */
8446 +#define PHY_M_EC_TX_TIM_CT BIT_1S /* RGMII Tx Timing Control */
8447 +#define PHY_M_EC_TRANS_DIS BIT_0S /* Transmitter Disable (88E1111 only) */
8449 +#define PHY_M_EC_M_DSC(x) (SHIFT10(x) & PHY_M_EC_M_DSC_MSK)
8450 + /* 00=1x; 01=2x; 10=3x; 11=4x */
8451 +#define PHY_M_EC_S_DSC(x) (SHIFT8(x) & PHY_M_EC_S_DSC_MSK)
8452 + /* 00=dis; 01=1x; 10=2x; 11=3x */
8453 +#define PHY_M_EC_MAC_S(x) (SHIFT4(x) & PHY_M_EC_MAC_S_MSK)
8454 + /* 01X=0; 110=2.5; 111=25 (MHz) */
8456 +#define PHY_M_EC_DSC_2(x) (SHIFT9(x) & PHY_M_EC_DSC_MSK_2)
8457 + /* 000=1x; 001=2x; 010=3x; 011=4x */
8458 + /* 100=5x; 101=6x; 110=7x; 111=8x */
8459 #define MAC_TX_CLK_0_MHZ 2
8460 #define MAC_TX_CLK_2_5_MHZ 6
8461 #define MAC_TX_CLK_25_MHZ 7
8463 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
8464 -#define PHY_M_LEDC_DIS_LED (1<<15) /* Bit 15: Disable LED */
8465 -#define PHY_M_LEDC_PULS_MSK (7<<12) /* Bit 14..12: Pulse Stretch Mask */
8466 -#define PHY_M_LEDC_F_INT (1<<11) /* Bit 11: Force Interrupt */
8467 -#define PHY_M_LEDC_BL_R_MSK (7<<8) /* Bit 10.. 8: Blink Rate Mask */
8468 - /* Bit 7.. 5: reserved */
8469 -#define PHY_M_LEDC_LINK_MSK (3<<3) /* Bit 4.. 3: Link Control Mask */
8470 -#define PHY_M_LEDC_DP_CTRL (1<<2) /* Bit 2: Duplex Control */
8471 -#define PHY_M_LEDC_RX_CTRL (1<<1) /* Bit 1: Rx activity / Link */
8472 -#define PHY_M_LEDC_TX_CTRL (1<<0) /* Bit 0: Tx activity / Link */
8473 +#define PHY_M_LEDC_DIS_LED BIT_15S /* Disable LED */
8474 +#define PHY_M_LEDC_PULS_MSK (7<<12) /* Bit 14..12: Pulse Stretch Mask */
8475 +#define PHY_M_LEDC_F_INT BIT_11S /* Force Interrupt */
8476 +#define PHY_M_LEDC_BL_R_MSK (7<<8) /* Bit 10.. 8: Blink Rate Mask */
8477 +#define PHY_M_LEDC_DP_C_LSB BIT_7S /* Duplex Control (LSB, 88E1111 only) */
8478 +#define PHY_M_LEDC_TX_C_LSB BIT_6S /* Tx Control (LSB, 88E1111 only) */
8479 +#define PHY_M_LEDC_LK_C_MSK (7<<3) /* Bit 5.. 3: Link Control Mask */
8480 + /* (88E1111 only) */
8481 + /* Bit 7.. 5: reserved (88E1040 only) */
8482 +#define PHY_M_LEDC_LINK_MSK (3<<3) /* Bit 4.. 3: Link Control Mask */
8483 + /* (88E1040 only) */
8484 +#define PHY_M_LEDC_DP_CTRL BIT_2S /* Duplex Control */
8485 +#define PHY_M_LEDC_DP_C_MSB BIT_2S /* Duplex Control (MSB, 88E1111 only) */
8486 +#define PHY_M_LEDC_RX_CTRL BIT_1S /* Rx Activity / Link */
8487 +#define PHY_M_LEDC_TX_CTRL BIT_0S /* Tx Activity / Link */
8488 +#define PHY_M_LEDC_TX_C_MSB BIT_0S /* Tx Control (MSB, 88E1111 only) */
8490 -#define PHY_M_LED_PULS_DUR(x) SHIFT12(x) /* Pulse Stretch Duration */
8491 +#define PHY_M_LED_PULS_DUR(x) (SHIFT12(x) & PHY_M_LEDC_PULS_MSK)
8493 -#define PULS_NO_STR 0 /* no pulse stretching */
8494 -#define PULS_21MS 1 /* 21 ms to 42 ms */
8495 +#define PULS_NO_STR 0 /* no pulse stretching */
8496 +#define PULS_21MS 1 /* 21 ms to 42 ms */
8497 #define PULS_42MS 2 /* 42 ms to 84 ms */
8498 #define PULS_84MS 3 /* 84 ms to 170 ms */
8499 #define PULS_170MS 4 /* 170 ms to 340 ms */
8500 @@ -1217,7 +1301,7 @@
8501 #define PULS_670MS 6 /* 670 ms to 1.3 s */
8502 #define PULS_1300MS 7 /* 1.3 s to 2.7 s */
8504 -#define PHY_M_LED_BLINK_RT(x) SHIFT8(x) /* Blink Rate */
8505 +#define PHY_M_LED_BLINK_RT(x) (SHIFT8(x) & PHY_M_LEDC_BL_R_MSK)
8507 #define BLINK_42MS 0 /* 42 ms */
8508 #define BLINK_84MS 1 /* 84 ms */
8509 @@ -1227,6 +1311,8 @@
8510 /* values 5 - 7: reserved */
8512 /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
8513 +#define PHY_M_LED_MO_SGMII(x) SHIFT14(x) /* Bit 15..14: SGMII AN Timer */
8514 + /* Bit 13..12: reserved */
8515 #define PHY_M_LED_MO_DUP(x) SHIFT10(x) /* Bit 11..10: Duplex */
8516 #define PHY_M_LED_MO_10(x) SHIFT8(x) /* Bit 9.. 8: Link 10 */
8517 #define PHY_M_LED_MO_100(x) SHIFT6(x) /* Bit 7.. 6: Link 100 */
8518 @@ -1240,30 +1326,35 @@
8521 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
8522 - /* Bit 15.. 7: reserved */
8523 -#define PHY_M_EC2_FI_IMPED (1<<6) /* Bit 6: Fiber Input Impedance */
8524 -#define PHY_M_EC2_FO_IMPED (1<<5) /* Bit 5: Fiber Output Impedance */
8525 -#define PHY_M_EC2_FO_M_CLK (1<<4) /* Bit 4: Fiber Mode Clock Enable */
8526 -#define PHY_M_EC2_FO_BOOST (1<<3) /* Bit 3: Fiber Output Boost */
8527 + /* Bit 15.. 7: reserved */
8528 +#define PHY_M_EC2_FI_IMPED BIT_6S /* Fiber Input Impedance */
8529 +#define PHY_M_EC2_FO_IMPED BIT_5S /* Fiber Output Impedance */
8530 +#define PHY_M_EC2_FO_M_CLK BIT_4S /* Fiber Mode Clock Enable */
8531 +#define PHY_M_EC2_FO_BOOST BIT_3S /* Fiber Output Boost */
8532 #define PHY_M_EC2_FO_AM_MSK 7 /* Bit 2.. 0: Fiber Output Amplitude */
8534 -/***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
8535 -#define PHY_M_FC_AUTO_SEL (1<<15) /* Bit 15: Fiber/Copper Auto Sel. dis. */
8536 -#define PHY_M_FC_AN_REG_ACC (1<<14) /* Bit 14: Fiber/Copper Autoneg. reg acc */
8537 -#define PHY_M_FC_RESULUTION (1<<13) /* Bit 13: Fiber/Copper Resulution */
8538 -#define PHY_M_SER_IF_AN_BP (1<<12) /* Bit 12: Ser IF autoneg. bypass enable */
8539 -#define PHY_M_SER_IF_BP_ST (1<<11) /* Bit 11: Ser IF autoneg. bypass status */
8540 -#define PHY_M_IRQ_POLARITY (1<<10) /* Bit 10: IRQ polarity */
8541 - /* Bit 9..4: reserved */
8542 -#define PHY_M_UNDOC1 (1<< 7) /* undocumented bit !! */
8543 -#define PHY_M_MODE_MASK (0xf<<0)/* Bit 3..0: copy of HWCFG MODE[3:0] */
8545 +/***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
8546 +#define PHY_M_FC_AUTO_SEL BIT_15S /* Fiber/Copper Auto Sel. Dis. */
8547 +#define PHY_M_FC_AN_REG_ACC BIT_14S /* Fiber/Copper AN Reg. Access */
8548 +#define PHY_M_FC_RESOLUTION BIT_13S /* Fiber/Copper Resolution */
8549 +#define PHY_M_SER_IF_AN_BP BIT_12S /* Ser. IF AN Bypass Enable */
8550 +#define PHY_M_SER_IF_BP_ST BIT_11S /* Ser. IF AN Bypass Status */
8551 +#define PHY_M_IRQ_POLARITY BIT_10S /* IRQ polarity */
8552 +#define PHY_M_DIS_AUT_MED BIT_9S /* Disable Aut. Medium Reg. Selection */
8553 + /* (88E1111 only) */
8554 + /* Bit 9.. 4: reserved (88E1040 only) */
8555 +#define PHY_M_UNDOC1 BIT_7S /* undocumented bit !! */
8556 +#define PHY_M_DTE_POW_STAT BIT_4S /* DTE Power Status (88E1111 only) */
8557 +#define PHY_M_MODE_MASK 0xf /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
8559 /***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/
8560 -#define PHY_M_CABD_ENA_TEST (1<<15) /* Bit 15: Enable Test */
8561 -#define PHY_M_CABD_STAT_MSK (3<<13) /* Bit 14..13: Status */
8562 - /* Bit 12.. 8: reserved */
8563 -#define PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance */
8564 +#define PHY_M_CABD_ENA_TEST BIT_15S /* Enable Test (Page 0) */
8565 +#define PHY_M_CABD_DIS_WAIT BIT_15S /* Disable Waiting Period (Page 1) */
8566 + /* (88E1111 only) */
8567 +#define PHY_M_CABD_STAT_MSK (3<<13) /* Bit 14..13: Status Mask */
8568 +#define PHY_M_CABD_AMPL_MSK (0x1f<<8) /* Bit 12.. 8: Amplitude Mask */
8569 + /* (88E1111 only) */
8570 +#define PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance Mask */
8572 /* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */
8573 #define CABD_STAT_NORMAL 0
8574 @@ -1271,6 +1362,79 @@
8575 #define CABD_STAT_OPEN 2
8576 #define CABD_STAT_FAIL 3
8578 +/* for 10/100 Fast Ethernet PHY (88E3082 only) */
8579 +/***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
8580 + /* Bit 15..12: reserved (used internally) */
8581 +#define PHY_M_FELP_LED2_MSK (0xf<<8) /* Bit 11.. 8: LED2 Mask (LINK) */
8582 +#define PHY_M_FELP_LED1_MSK (0xf<<4) /* Bit 7.. 4: LED1 Mask (ACT) */
8583 +#define PHY_M_FELP_LED0_MSK 0xf /* Bit 3.. 0: LED0 Mask (SPEED) */
8585 +#define PHY_M_FELP_LED2_CTRL(x) (SHIFT8(x) & PHY_M_FELP_LED2_MSK)
8586 +#define PHY_M_FELP_LED1_CTRL(x) (SHIFT4(x) & PHY_M_FELP_LED1_MSK)
8587 +#define PHY_M_FELP_LED0_CTRL(x) (SHIFT0(x) & PHY_M_FELP_LED0_MSK)
8589 +#define LED_PAR_CTRL_COLX 0x00
8590 +#define LED_PAR_CTRL_ERROR 0x01
8591 +#define LED_PAR_CTRL_DUPLEX 0x02
8592 +#define LED_PAR_CTRL_DP_COL 0x03
8593 +#define LED_PAR_CTRL_SPEED 0x04
8594 +#define LED_PAR_CTRL_LINK 0x05
8595 +#define LED_PAR_CTRL_TX 0x06
8596 +#define LED_PAR_CTRL_RX 0x07
8597 +#define LED_PAR_CTRL_ACT 0x08
8598 +#define LED_PAR_CTRL_LNK_RX 0x09
8599 +#define LED_PAR_CTRL_LNK_AC 0x0a
8600 +#define LED_PAR_CTRL_ACT_BL 0x0b
8601 +#define LED_PAR_CTRL_TX_BL 0x0c
8602 +#define LED_PAR_CTRL_RX_BL 0x0d
8603 +#define LED_PAR_CTRL_COL_BL 0x0e
8604 +#define LED_PAR_CTRL_INACT 0x0f
8606 +/***** PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
8607 +#define PHY_M_FESC_DIS_WAIT BIT_2S /* Disable TDR Waiting Period */
8608 +#define PHY_M_FESC_ENA_MCLK BIT_1S /* Enable MAC Rx Clock in sleep mode */
8609 +#define PHY_M_FESC_SEL_CL_A BIT_0S /* Select Class A driver (100B-TX) */
8611 +/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
8612 +/***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/
8613 +#define PHY_M_FIB_FORCE_LNK BIT_10S /* Force Link Good */
8614 +#define PHY_M_FIB_SIGD_POL BIT_9S /* SIGDET Polarity */
8615 +#define PHY_M_FIB_TX_DIS BIT_3S /* Transmitter Disable */
8617 +/***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
8618 +#define PHY_M_MAC_MD_MSK (7<<7) /* Bit 9.. 7: Mode Select Mask */
8619 +#define PHY_M_MAC_GMIF_PUP BIT_3S /* GMII Power Up (88E1149 only) */
8621 +#define PHY_M_MAC_MD_AUTO 3 /* Auto Copper/1000Base-X */
8622 +#define PHY_M_MAC_MD_COPPER 5 /* Copper only */
8623 +#define PHY_M_MAC_MD_1000BX 7 /* 1000Base-X only */
8624 +#define PHY_M_MAC_MODE_SEL(x) (SHIFT7(x) & PHY_M_MAC_MD_MSK)
8626 +/***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
8627 +#define PHY_M_LEDC_LOS_MSK (0xf<<12) /* Bit 15..12: LOS LED Ctrl. Mask */
8628 +#define PHY_M_LEDC_INIT_MSK (0xf<<8) /* Bit 11.. 8: INIT LED Ctrl. Mask */
8629 +#define PHY_M_LEDC_STA1_MSK (0xf<<4) /* Bit 7.. 4: STAT1 LED Ctrl. Mask */
8630 +#define PHY_M_LEDC_STA0_MSK 0xf /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
8632 +#define PHY_M_LEDC_LOS_CTRL(x) (SHIFT12(x) & PHY_M_LEDC_LOS_MSK)
8633 +#define PHY_M_LEDC_INIT_CTRL(x) (SHIFT8(x) & PHY_M_LEDC_INIT_MSK)
8634 +#define PHY_M_LEDC_STA1_CTRL(x) (SHIFT4(x) & PHY_M_LEDC_STA1_MSK)
8635 +#define PHY_M_LEDC_STA0_CTRL(x) (SHIFT0(x) & PHY_M_LEDC_STA0_MSK)
8637 +/***** PHY_MARV_PHY_STAT (page 3) 16 bit r/w Polarity Control Reg. *****/
8638 +#define PHY_M_POLC_LS1M_MSK (0xf<<12) /* Bit 15..12: LOS,STAT1 Mix % Mask */
8639 +#define PHY_M_POLC_IS0M_MSK (0xf<<8) /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
8640 +#define PHY_M_POLC_LOS_MSK (0x3<<6) /* Bit 7.. 6: LOS Pol. Ctrl. Mask */
8641 +#define PHY_M_POLC_INIT_MSK (0x3<<4) /* Bit 5.. 4: INIT Pol. Ctrl. Mask */
8642 +#define PHY_M_POLC_STA1_MSK (0x3<<2) /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */
8643 +#define PHY_M_POLC_STA0_MSK 0x3 /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */
8645 +#define PHY_M_POLC_LS1_P_MIX(x) (SHIFT12(x) & PHY_M_POLC_LS1M_MSK)
8646 +#define PHY_M_POLC_IS0_P_MIX(x) (SHIFT8(x) & PHY_M_POLC_IS0M_MSK)
8647 +#define PHY_M_POLC_LOS_CTRL(x) (SHIFT6(x) & PHY_M_POLC_LOS_MSK)
8648 +#define PHY_M_POLC_INIT_CTRL(x) (SHIFT4(x) & PHY_M_POLC_INIT_MSK)
8649 +#define PHY_M_POLC_STA1_CTRL(x) (SHIFT2(x) & PHY_M_POLC_STA1_MSK)
8650 +#define PHY_M_POLC_STA0_CTRL(x) (SHIFT0(x) & PHY_M_POLC_STA0_MSK)
8654 @@ -1431,141 +1595,159 @@
8657 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
8658 -#define GM_GPSR_SPEED (1<<15) /* Bit 15: Port Speed (1 = 100 Mbps) */
8659 -#define GM_GPSR_DUPLEX (1<<14) /* Bit 14: Duplex Mode (1 = Full) */
8660 -#define GM_GPSR_FC_TX_DIS (1<<13) /* Bit 13: Tx Flow-Control Mode Disabled */
8661 -#define GM_GPSR_LINK_UP (1<<12) /* Bit 12: Link Up Status */
8662 -#define GM_GPSR_PAUSE (1<<11) /* Bit 11: Pause State */
8663 -#define GM_GPSR_TX_ACTIVE (1<<10) /* Bit 10: Tx in Progress */
8664 -#define GM_GPSR_EXC_COL (1<<9) /* Bit 9: Excessive Collisions Occured */
8665 -#define GM_GPSR_LAT_COL (1<<8) /* Bit 8: Late Collisions Occured */
8666 - /* Bit 7..6: reserved */
8667 -#define GM_GPSR_PHY_ST_CH (1<<5) /* Bit 5: PHY Status Change */
8668 -#define GM_GPSR_GIG_SPEED (1<<4) /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
8669 -#define GM_GPSR_PART_MODE (1<<3) /* Bit 3: Partition mode */
8670 -#define GM_GPSR_FC_RX_DIS (1<<2) /* Bit 2: Rx Flow-Control Mode Disabled */
8671 -#define GM_GPSR_PROM_EN (1<<1) /* Bit 1: Promiscuous Mode Enabled */
8672 - /* Bit 0: reserved */
8674 +#define GM_GPSR_SPEED BIT_15S /* Port Speed (1 = 100 Mbps) */
8675 +#define GM_GPSR_DUPLEX BIT_14S /* Duplex Mode (1 = Full) */
8676 +#define GM_GPSR_FC_TX_DIS BIT_13S /* Tx Flow-Control Mode Disabled */
8677 +#define GM_GPSR_LINK_UP BIT_12S /* Link Up Status */
8678 +#define GM_GPSR_PAUSE BIT_11S /* Pause State */
8679 +#define GM_GPSR_TX_ACTIVE BIT_10S /* Tx in Progress */
8680 +#define GM_GPSR_EXC_COL BIT_9S /* Excessive Collisions Occured */
8681 +#define GM_GPSR_LAT_COL BIT_8S /* Late Collisions Occured */
8682 + /* Bit 7.. 6: reserved */
8683 +#define GM_GPSR_PHY_ST_CH BIT_5S /* PHY Status Change */
8684 +#define GM_GPSR_GIG_SPEED BIT_4S /* Gigabit Speed (1 = 1000 Mbps) */
8685 +#define GM_GPSR_PART_MODE BIT_3S /* Partition mode */
8686 +#define GM_GPSR_FC_RX_DIS BIT_2S /* Rx Flow-Control Mode Disabled */
8687 + /* Bit 2.. 0: reserved */
8689 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
8690 - /* Bit 15: reserved */
8691 -#define GM_GPCR_PROM_ENA (1<<14) /* Bit 14: Enable Promiscuous Mode */
8692 -#define GM_GPCR_FC_TX_DIS (1<<13) /* Bit 13: Disable Tx Flow-Control Mode */
8693 -#define GM_GPCR_TX_ENA (1<<12) /* Bit 12: Enable Transmit */
8694 -#define GM_GPCR_RX_ENA (1<<11) /* Bit 11: Enable Receive */
8695 -#define GM_GPCR_BURST_ENA (1<<10) /* Bit 10: Enable Burst Mode */
8696 -#define GM_GPCR_LOOP_ENA (1<<9) /* Bit 9: Enable MAC Loopback Mode */
8697 -#define GM_GPCR_PART_ENA (1<<8) /* Bit 8: Enable Partition Mode */
8698 -#define GM_GPCR_GIGS_ENA (1<<7) /* Bit 7: Gigabit Speed (1000 Mbps) */
8699 -#define GM_GPCR_FL_PASS (1<<6) /* Bit 6: Force Link Pass */
8700 -#define GM_GPCR_DUP_FULL (1<<5) /* Bit 5: Full Duplex Mode */
8701 -#define GM_GPCR_FC_RX_DIS (1<<4) /* Bit 4: Disable Rx Flow-Control Mode */
8702 -#define GM_GPCR_SPEED_100 (1<<3) /* Bit 3: Port Speed 100 Mbps */
8703 -#define GM_GPCR_AU_DUP_DIS (1<<2) /* Bit 2: Disable Auto-Update Duplex */
8704 -#define GM_GPCR_AU_FCT_DIS (1<<1) /* Bit 1: Disable Auto-Update Flow-C. */
8705 -#define GM_GPCR_AU_SPD_DIS (1<<0) /* Bit 0: Disable Auto-Update Speed */
8706 +#define GM_GPCR_RMII_PH_ENA BIT_15S /* Enable RMII for PHY (Yukon-FE only) */
8707 +#define GM_GPCR_RMII_LB_ENA BIT_14S /* Enable RMII Loopback (Yukon-FE only) */
8708 +#define GM_GPCR_FC_TX_DIS BIT_13S /* Disable Tx Flow-Control Mode */
8709 +#define GM_GPCR_TX_ENA BIT_12S /* Enable Transmit */
8710 +#define GM_GPCR_RX_ENA BIT_11S /* Enable Receive */
8711 + /* Bit 10: reserved */
8712 +#define GM_GPCR_LOOP_ENA BIT_9S /* Enable MAC Loopback Mode */
8713 +#define GM_GPCR_PART_ENA BIT_8S /* Enable Partition Mode */
8714 +#define GM_GPCR_GIGS_ENA BIT_7S /* Gigabit Speed (1000 Mbps) */
8715 +#define GM_GPCR_FL_PASS BIT_6S /* Force Link Pass */
8716 +#define GM_GPCR_DUP_FULL BIT_5S /* Full Duplex Mode */
8717 +#define GM_GPCR_FC_RX_DIS BIT_4S /* Disable Rx Flow-Control Mode */
8718 +#define GM_GPCR_SPEED_100 BIT_3S /* Port Speed 100 Mbps */
8719 +#define GM_GPCR_AU_DUP_DIS BIT_2S /* Disable Auto-Update Duplex */
8720 +#define GM_GPCR_AU_FCT_DIS BIT_1S /* Disable Auto-Update Flow-C. */
8721 +#define GM_GPCR_AU_SPD_DIS BIT_0S /* Disable Auto-Update Speed */
8723 #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
8724 #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |\
8728 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
8729 -#define GM_TXCR_FORCE_JAM (1<<15) /* Bit 15: Force Jam / Flow-Control */
8730 -#define GM_TXCR_CRC_DIS (1<<14) /* Bit 14: Disable insertion of CRC */
8731 -#define GM_TXCR_PAD_DIS (1<<13) /* Bit 13: Disable padding of packets */
8732 -#define GM_TXCR_COL_THR_MSK (7<<10) /* Bit 12..10: Collision Threshold */
8733 +#define GM_TXCR_FORCE_JAM BIT_15S /* Force Jam / Flow-Control */
8734 +#define GM_TXCR_CRC_DIS BIT_14S /* Disable insertion of CRC */
8735 +#define GM_TXCR_PAD_DIS BIT_13S /* Disable padding of packets */
8736 +#define GM_TXCR_COL_THR_MSK (7<<10) /* Bit 12..10: Collision Threshold Mask */
8737 + /* Bit 9.. 8: reserved */
8738 +#define GM_TXCR_PAD_PAT_MSK 0xff /* Bit 7.. 0: Padding Pattern Mask */
8739 + /* (Yukon-2 only) */
8741 #define TX_COL_THR(x) (SHIFT10(x) & GM_TXCR_COL_THR_MSK)
8743 #define TX_COL_DEF 0x04
8746 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
8747 -#define GM_RXCR_UCF_ENA (1<<15) /* Bit 15: Enable Unicast filtering */
8748 -#define GM_RXCR_MCF_ENA (1<<14) /* Bit 14: Enable Multicast filtering */
8749 -#define GM_RXCR_CRC_DIS (1<<13) /* Bit 13: Remove 4-byte CRC */
8750 -#define GM_RXCR_PASS_FC (1<<12) /* Bit 12: Pass FC packets to FIFO */
8752 +#define GM_RXCR_UCF_ENA BIT_15S /* Enable Unicast filtering */
8753 +#define GM_RXCR_MCF_ENA BIT_14S /* Enable Multicast filtering */
8754 +#define GM_RXCR_CRC_DIS BIT_13S /* Remove 4-byte CRC */
8755 +#define GM_RXCR_PASS_FC BIT_12S /* Pass FC packets to FIFO (Yukon-1 only) */
8756 + /* Bit 11.. 0: reserved */
8758 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
8759 -#define GM_TXPA_JAMLEN_MSK (0x03<<14) /* Bit 15..14: Jam Length */
8760 -#define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13..9: Jam IPG */
8761 -#define GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8..4: IPG Jam to Data */
8762 - /* Bit 3..0: reserved */
8763 +#define GM_TXPA_JAMLEN_MSK (3<<14) /* Bit 15..14: Jam Length Mask */
8764 +#define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13.. 9: Jam IPG Mask */
8765 +#define GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8.. 4: IPG Jam to Data Mask */
8766 +#define GM_TXPA_BO_LIM_MSK 0x0f /* Bit 3.. 0: Backoff Limit Mask */
8767 + /* (Yukon-2 only) */
8769 #define TX_JAM_LEN_VAL(x) (SHIFT14(x) & GM_TXPA_JAMLEN_MSK)
8770 #define TX_JAM_IPG_VAL(x) (SHIFT9(x) & GM_TXPA_JAMIPG_MSK)
8771 #define TX_IPG_JAM_DATA(x) (SHIFT4(x) & GM_TXPA_JAMDAT_MSK)
8772 +#define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK)
8774 #define TX_JAM_LEN_DEF 0x03
8775 #define TX_JAM_IPG_DEF 0x0b
8776 #define TX_IPG_JAM_DEF 0x1c
8777 +#define TX_BOF_LIM_DEF 0x04
8779 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
8780 -#define GM_SMOD_DATABL_MSK (0x1f<<11) /* Bit 15..11: Data Blinder (r/o) */
8781 -#define GM_SMOD_LIMIT_4 (1<<10) /* Bit 10: 4 consecutive Tx trials */
8782 -#define GM_SMOD_VLAN_ENA (1<<9) /* Bit 9: Enable VLAN (Max. Frame Len) */
8783 -#define GM_SMOD_JUMBO_ENA (1<<8) /* Bit 8: Enable Jumbo (Max. Frame Len) */
8784 - /* Bit 7..5: reserved */
8785 -#define GM_SMOD_IPG_MSK 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
8787 +#define GM_SMOD_DATABL_MSK (0x1f<<11) /* Bit 15..11: Data Blinder */
8788 + /* r/o on Yukon, r/w on Yukon-EC */
8789 +#define GM_SMOD_LIMIT_4 BIT_10S /* 4 consecutive Tx trials */
8790 +#define GM_SMOD_VLAN_ENA BIT_9S /* Enable VLAN (Max. Frame Len) */
8791 +#define GM_SMOD_JUMBO_ENA BIT_8S /* Enable Jumbo (Max. Frame Len) */
8792 + /* Bit 7.. 5: reserved */
8793 +#define GM_SMOD_IPG_MSK 0x1f /* Bit 4.. 0: Inter-Packet Gap (IPG) */
8795 #define DATA_BLIND_VAL(x) (SHIFT11(x) & GM_SMOD_DATABL_MSK)
8796 -#define DATA_BLIND_DEF 0x04
8797 +#define IPG_DATA_VAL(x) ((x) & GM_SMOD_IPG_MSK)
8799 -#define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
8800 +#define DATA_BLIND_DEF 0x04
8801 #define IPG_DATA_DEF 0x1e
8803 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
8804 #define GM_SMI_CT_PHY_A_MSK (0x1f<<11) /* Bit 15..11: PHY Device Address */
8805 #define GM_SMI_CT_REG_A_MSK (0x1f<<6) /* Bit 10.. 6: PHY Register Address */
8806 -#define GM_SMI_CT_OP_RD (1<<5) /* Bit 5: OpCode Read (0=Write)*/
8807 -#define GM_SMI_CT_RD_VAL (1<<4) /* Bit 4: Read Valid (Read completed) */
8808 -#define GM_SMI_CT_BUSY (1<<3) /* Bit 3: Busy (Operation in progress) */
8809 - /* Bit 2..0: reserved */
8811 +#define GM_SMI_CT_OP_RD BIT_5S /* OpCode Read (0=Write)*/
8812 +#define GM_SMI_CT_RD_VAL BIT_4S /* Read Valid (Read completed) */
8813 +#define GM_SMI_CT_BUSY BIT_3S /* Busy (Operation in progress) */
8814 + /* Bit 2.. 0: reserved */
8816 #define GM_SMI_CT_PHY_AD(x) (SHIFT11(x) & GM_SMI_CT_PHY_A_MSK)
8817 #define GM_SMI_CT_REG_AD(x) (SHIFT6(x) & GM_SMI_CT_REG_A_MSK)
8819 - /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
8820 - /* Bit 15..6: reserved */
8821 -#define GM_PAR_MIB_CLR (1<<5) /* Bit 5: Set MIB Clear Counter Mode */
8822 -#define GM_PAR_MIB_TST (1<<4) /* Bit 4: MIB Load Counter (Test Mode) */
8823 - /* Bit 3..0: reserved */
8825 +/* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
8826 + /* Bit 15.. 6: reserved */
8827 +#define GM_PAR_MIB_CLR BIT_5S /* Set MIB Clear Counter Mode */
8828 +#define GM_PAR_MIB_TST BIT_4S /* MIB Load Counter (Test Mode) */
8829 + /* Bit 3.. 0: reserved */
8831 /* Receive Frame Status Encoding */
8832 -#define GMR_FS_LEN (0xffffUL<<16) /* Bit 31..16: Rx Frame Length */
8833 +#define GMR_FS_LEN_MSK (0xffffUL<<16) /* Bit 31..16: Rx Frame Length */
8834 /* Bit 15..14: reserved */
8835 -#define GMR_FS_VLAN (1L<<13) /* Bit 13: VLAN Packet */
8836 -#define GMR_FS_JABBER (1L<<12) /* Bit 12: Jabber Packet */
8837 -#define GMR_FS_UN_SIZE (1L<<11) /* Bit 11: Undersize Packet */
8838 -#define GMR_FS_MC (1L<<10) /* Bit 10: Multicast Packet */
8839 -#define GMR_FS_BC (1L<<9) /* Bit 9: Broadcast Packet */
8840 -#define GMR_FS_RX_OK (1L<<8) /* Bit 8: Receive OK (Good Packet) */
8841 -#define GMR_FS_GOOD_FC (1L<<7) /* Bit 7: Good Flow-Control Packet */
8842 -#define GMR_FS_BAD_FC (1L<<6) /* Bit 6: Bad Flow-Control Packet */
8843 -#define GMR_FS_MII_ERR (1L<<5) /* Bit 5: MII Error */
8844 -#define GMR_FS_LONG_ERR (1L<<4) /* Bit 4: Too Long Packet */
8845 -#define GMR_FS_FRAGMENT (1L<<3) /* Bit 3: Fragment */
8846 +#define GMR_FS_VLAN BIT_13 /* VLAN Packet */
8847 +#define GMR_FS_JABBER BIT_12 /* Jabber Packet */
8848 +#define GMR_FS_UN_SIZE BIT_11 /* Undersize Packet */
8849 +#define GMR_FS_MC BIT_10 /* Multicast Packet */
8850 +#define GMR_FS_BC BIT_9 /* Broadcast Packet */
8851 +#define GMR_FS_RX_OK BIT_8 /* Receive OK (Good Packet) */
8852 +#define GMR_FS_GOOD_FC BIT_7 /* Good Flow-Control Packet */
8853 +#define GMR_FS_BAD_FC BIT_6 /* Bad Flow-Control Packet */
8854 +#define GMR_FS_MII_ERR BIT_5 /* MII Error */
8855 +#define GMR_FS_LONG_ERR BIT_4 /* Too Long Packet */
8856 +#define GMR_FS_FRAGMENT BIT_3 /* Fragment */
8857 /* Bit 2: reserved */
8858 -#define GMR_FS_CRC_ERR (1L<<1) /* Bit 1: CRC Error */
8859 -#define GMR_FS_RX_FF_OV (1L<<0) /* Bit 0: Rx FIFO Overflow */
8860 +#define GMR_FS_CRC_ERR BIT_1 /* CRC Error */
8861 +#define GMR_FS_RX_FF_OV BIT_0 /* Rx FIFO Overflow */
8863 +#define GMR_FS_LEN_SHIFT 16
8866 * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR)
8868 -#define GMR_FS_ANY_ERR (GMR_FS_CRC_ERR | \
8869 - GMR_FS_LONG_ERR | \
8871 +#define GMR_FS_ANY_ERR ( \
8872 + GMR_FS_RX_FF_OV | \
8873 + GMR_FS_CRC_ERR | \
8874 + GMR_FS_FRAGMENT | \
8880 -/* Rx GMAC FIFO Flush Mask (default) */
8881 -#define RX_FF_FL_DEF_MSK (GMR_FS_CRC_ERR | \
8883 +#define GMR_FS_ANY_ERR ( \
8885 + GMR_FS_CRC_ERR | \
8886 + GMR_FS_FRAGMENT | \
8887 + GMR_FS_LONG_ERR | \
8895 +/* Rx GMAC FIFO Flush Mask (default) */
8896 +#define RX_FF_FL_DEF_MSK GMR_FS_ANY_ERR
8898 /* typedefs *******************************************************************/
8900 @@ -1577,3 +1759,4 @@
8901 #endif /* __cplusplus */
8903 #endif /* __INC_XMAC_H */
8905 diff -ruN linux/drivers/net/sk98lin/skaddr.c linux-new/drivers/net/sk98lin/skaddr.c
8906 --- linux/drivers/net/sk98lin/skaddr.c 2006-09-20 05:42:06.000000000 +0200
8907 +++ linux-new/drivers/net/sk98lin/skaddr.c 2006-07-28 14:13:54.000000000 +0200
8911 * Project: Gigabit Ethernet Adapters, ADDR-Module
8912 - * Version: $Revision$
8914 + * Version: $Revision$
8916 * Purpose: Manage Addresses (Multicast and Unicast) and Promiscuous Mode.
8918 ******************************************************************************/
8920 /******************************************************************************
8923 * (C)Copyright 1998-2002 SysKonnect GmbH.
8924 - * (C)Copyright 2002-2003 Marvell.
8925 + * (C)Copyright 2002-2005 Marvell.
8927 * This program is free software; you can redistribute it and/or modify
8928 * it under the terms of the GNU General Public License as published by
8930 * (at your option) any later version.
8932 * The information in this file is provided "AS IS" without warranty.
8935 ******************************************************************************/
8939 #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
8940 static const char SysKonnectFileId[] =
8941 - "@(#) $Id$ (C) Marvell.";
8942 + "@(#) $Id$ (C) Marvell.";
8943 #endif /* DEBUG ||!LINT || !SK_SLIM */
8948 /* defines ********************************************************************/
8951 #define XMAC_POLY 0xEDB88320UL /* CRC32-Poly - XMAC: Little Endian */
8952 #define GMAC_POLY 0x04C11DB7L /* CRC16-Poly - GMAC: Little Endian */
8953 #define HASH_BITS 6 /* #bits in hash */
8954 -#define SK_MC_BIT 0x01
8955 +#define SK_MC_BIT 0x01
8957 /* Error numbers and messages. */
8961 /* 64-bit hash values with all bits set. */
8963 -static const SK_U16 OnesHash[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
8964 +SK_U16 OnesHash[4] = {0xffff, 0xffff, 0xffff, 0xffff};
8966 /* local variables ************************************************************/
8969 static int Next0[SK_MAX_MACS] = {0};
8972 -static int SkAddrGmacMcAdd(SK_AC *pAC, SK_IOC IoC, SK_U32 PortNumber,
8973 - SK_MAC_ADDR *pMc, int Flags);
8974 -static int SkAddrGmacMcClear(SK_AC *pAC, SK_IOC IoC, SK_U32 PortNumber,
8976 -static int SkAddrGmacMcUpdate(SK_AC *pAC, SK_IOC IoC, SK_U32 PortNumber);
8977 -static int SkAddrGmacPromiscuousChange(SK_AC *pAC, SK_IOC IoC,
8978 - SK_U32 PortNumber, int NewPromMode);
8979 -static int SkAddrXmacMcAdd(SK_AC *pAC, SK_IOC IoC, SK_U32 PortNumber,
8980 - SK_MAC_ADDR *pMc, int Flags);
8981 -static int SkAddrXmacMcClear(SK_AC *pAC, SK_IOC IoC, SK_U32 PortNumber,
8983 -static int SkAddrXmacMcUpdate(SK_AC *pAC, SK_IOC IoC, SK_U32 PortNumber);
8984 -static int SkAddrXmacPromiscuousChange(SK_AC *pAC, SK_IOC IoC,
8985 - SK_U32 PortNumber, int NewPromMode);
8987 /* functions ******************************************************************/
8989 /******************************************************************************
8990 @@ -151,13 +137,12 @@
8994 - SK_MEMSET((char *) &pAC->Addr, (SK_U8) 0,
8995 - (SK_U16) sizeof(SK_ADDR));
8996 + SK_MEMSET((char *)&pAC->Addr, (SK_U8)0, (SK_U16)sizeof(SK_ADDR));
8998 for (i = 0; i < SK_MAX_MACS; i++) {
8999 pAPort = &pAC->Addr.Port[i];
9000 pAPort->PromMode = SK_PROM_MODE_NONE;
9003 pAPort->FirstExactMatchRlmt = SK_ADDR_FIRST_MATCH_RLMT;
9004 pAPort->FirstExactMatchDrv = SK_ADDR_FIRST_MATCH_DRV;
9005 pAPort->NextExactMatchRlmt = SK_ADDR_FIRST_MATCH_RLMT;
9007 /* pAC->Addr.InitDone = SK_INIT_DATA; */
9013 for (i = 0; i < SK_MAX_NETS; i++) {
9014 pAC->Addr.Net[i].ActivePort = pAC->Rlmt.Net[i].ActivePort;
9021 /* Read permanent logical MAC address from Control Register File. */
9022 for (j = 0; j < SK_MAC_ADDR_LEN; j++) {
9023 InAddr = (SK_U8 *) &pAC->Addr.Net[0].PermanentMacAddress.a[j];
9024 @@ -206,11 +191,11 @@
9025 pAC->Addr.Port[pAC->Addr.Net[0].ActivePort].Exact[0] =
9026 pAC->Addr.Net[0].CurrentMacAddress;
9028 - /* Set logical MAC address for net 2 to (log | 3). */
9029 + /* Set logical MAC address for net 2 to. */
9030 if (!pAC->Addr.Net[1].CurrentMacAddressSet) {
9031 pAC->Addr.Net[1].PermanentMacAddress =
9032 pAC->Addr.Net[0].PermanentMacAddress;
9033 - pAC->Addr.Net[1].PermanentMacAddress.a[5] |= 3;
9034 + pAC->Addr.Net[1].PermanentMacAddress.a[5] += 1;
9035 /* Set the current logical MAC address to the permanent one. */
9036 pAC->Addr.Net[1].CurrentMacAddress =
9037 pAC->Addr.Net[1].PermanentMacAddress;
9039 pAC->Addr.Net[i].PermanentMacAddress.a[2],
9040 pAC->Addr.Net[i].PermanentMacAddress.a[3],
9041 pAC->Addr.Net[i].PermanentMacAddress.a[4],
9042 - pAC->Addr.Net[i].PermanentMacAddress.a[5]))
9044 + pAC->Addr.Net[i].PermanentMacAddress.a[5]));
9046 SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_INIT,
9047 ("Logical MAC Address (Net%d): %02X %02X %02X %02X %02X %02X\n",
9050 pAC->Addr.Net[i].CurrentMacAddress.a[2],
9051 pAC->Addr.Net[i].CurrentMacAddress.a[3],
9052 pAC->Addr.Net[i].CurrentMacAddress.a[4],
9053 - pAC->Addr.Net[i].CurrentMacAddress.a[5]))
9054 + pAC->Addr.Net[i].CurrentMacAddress.a[5]));
9059 pAPort->PermanentMacAddress.a[2],
9060 pAPort->PermanentMacAddress.a[3],
9061 pAPort->PermanentMacAddress.a[4],
9062 - pAPort->PermanentMacAddress.a[5]))
9064 + pAPort->PermanentMacAddress.a[5]));
9066 SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_INIT,
9067 ("SkAddrInit: Physical MAC Address: %02X %02X %02X %02X %02X %02X\n",
9068 pAPort->CurrentMacAddress.a[0],
9070 pAPort->CurrentMacAddress.a[2],
9071 pAPort->CurrentMacAddress.a[3],
9072 pAPort->CurrentMacAddress.a[4],
9073 - pAPort->CurrentMacAddress.a[5]))
9074 + pAPort->CurrentMacAddress.a[5]));
9077 /* pAC->Addr.InitDone = SK_INIT_IO; */
9081 return (SK_ADDR_SUCCESS);
9087 @@ -348,16 +333,20 @@
9088 int Flags) /* permanent/non-perm, sw-only */
9093 if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
9094 return (SK_ADDR_ILLEGAL_PORT);
9098 if (pAC->GIni.GIGenesis) {
9100 ReturnCode = SkAddrXmacMcClear(pAC, IoC, PortNumber, Flags);
9105 ReturnCode = SkAddrGmacMcClear(pAC, IoC, PortNumber, Flags);
9109 return (ReturnCode);
9111 #endif /* !SK_SLIM */
9116 /******************************************************************************
9118 * SkAddrXmacMcClear - clear the multicast table
9121 * SK_ADDR_ILLEGAL_PORT
9123 -static int SkAddrXmacMcClear(
9124 +int SkAddrXmacMcClear(
9125 SK_AC *pAC, /* adapter context */
9126 SK_IOC IoC, /* I/O context */
9127 SK_U32 PortNumber, /* Index of affected port */
9128 @@ -417,13 +406,13 @@
9131 return (SK_ADDR_SUCCESS);
9133 -} /* SkAddrXmacMcClear */
9135 +} /* SkAddrXmacMcClear */
9136 +#endif /* GENESIS */
9137 #endif /* !SK_SLIM */
9142 /******************************************************************************
9144 * SkAddrGmacMcClear - clear the multicast table
9147 * SK_ADDR_ILLEGAL_PORT
9149 -static int SkAddrGmacMcClear(
9150 +int SkAddrGmacMcClear(
9151 SK_AC *pAC, /* adapter context */
9152 SK_IOC IoC, /* I/O context */
9153 SK_U32 PortNumber, /* Index of affected port */
9154 @@ -462,38 +451,37 @@
9155 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[4],
9156 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[5],
9157 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[6],
9158 - pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7]))
9159 + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7]));
9162 /* Clear InexactFilter */
9163 for (i = 0; i < 8; i++) {
9164 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] = 0;
9168 if (Flags & SK_ADDR_PERMANENT) { /* permanent => RLMT */
9171 /* Copy DRV bits to InexactFilter. */
9172 for (i = 0; i < 8; i++) {
9173 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |=
9174 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[i];
9177 /* Clear InexactRlmtFilter. */
9178 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[i] = 0;
9183 else { /* not permanent => DRV */
9186 /* Copy RLMT bits to InexactFilter. */
9187 for (i = 0; i < 8; i++) {
9188 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |=
9189 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[i];
9192 /* Clear InexactDrvFilter. */
9193 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[i] = 0;
9199 SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
9200 ("GMAC InexactFilter (cleared): %02X %02X %02X %02X %02X %02X %02X %02X\n",
9201 @@ -504,19 +492,20 @@
9202 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[4],
9203 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[5],
9204 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[6],
9205 - pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7]))
9206 + pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7]));
9210 if (!(Flags & SK_MC_SW_ONLY)) {
9211 (void) SkAddrGmacMcUpdate(pAC, IoC, PortNumber);
9215 return (SK_ADDR_SUCCESS);
9217 } /* SkAddrGmacMcClear */
9220 #ifndef SK_ADDR_CHEAT
9223 /******************************************************************************
9225 * SkXmacMcHash - hash multicast address
9228 * Hash value of multicast address.
9230 -static SK_U32 SkXmacMcHash(
9231 +SK_U32 SkXmacMcHash(
9232 unsigned char *pMc) /* Multicast address */
9236 return (Crc & ((1 << HASH_BITS) - 1));
9238 } /* SkXmacMcHash */
9239 +#endif /* GENESIS */
9243 /******************************************************************************
9245 * SkGmacMcHash - hash multicast address
9248 * Hash value of multicast address.
9250 -static SK_U32 SkGmacMcHash(
9251 +SK_U32 SkGmacMcHash(
9252 unsigned char *pMc) /* Multicast address */
9256 for (Byte = 0; Byte < 6; Byte++) {
9257 /* Get next byte. */
9258 Data = (SK_U32) pMc[Byte];
9261 /* Change bit order in byte. */
9263 for (Bit = 0; Bit < 8; Bit++) {
9270 Crc ^= (Data << 24);
9271 for (Bit = 0; Bit < 8; Bit++) {
9272 if (Crc & 0x80000000) {
9273 @@ -608,11 +598,11 @@
9279 return (Crc & ((1 << HASH_BITS) - 1));
9281 } /* SkGmacMcHash */
9284 #endif /* !SK_ADDR_CHEAT */
9286 /******************************************************************************
9287 @@ -647,23 +637,27 @@
9288 int Flags) /* permanent/non-permanent */
9293 if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
9294 return (SK_ADDR_ILLEGAL_PORT);
9298 if (pAC->GIni.GIGenesis) {
9300 ReturnCode = SkAddrXmacMcAdd(pAC, IoC, PortNumber, pMc, Flags);
9305 ReturnCode = SkAddrGmacMcAdd(pAC, IoC, PortNumber, pMc, Flags);
9309 return (ReturnCode);
9315 /******************************************************************************
9317 * SkAddrXmacMcAdd - add a multicast address to a port
9319 * SK_MC_ILLEGAL_ADDRESS
9320 * SK_MC_RLMT_OVERFLOW
9322 -static int SkAddrXmacMcAdd(
9323 +int SkAddrXmacMcAdd(
9324 SK_AC *pAC, /* adapter context */
9325 SK_IOC IoC, /* I/O context */
9326 SK_U32 PortNumber, /* Port Number */
9328 return (SK_MC_RLMT_OVERFLOW);
9333 if (pAC->Addr.Port[PortNumber].NextExactMatchRlmt >
9334 SK_ADDR_LAST_MATCH_RLMT) {
9335 return (SK_MC_RLMT_OVERFLOW);
9337 return (SK_MC_RLMT_OVERFLOW);
9342 if (pAC->Addr.Port[PortNumber].NextExactMatchDrv <= SK_ADDR_LAST_MATCH_DRV) {
9344 /* Set exact match entry. */
9348 } /* SkAddrXmacMcAdd */
9349 +#endif /* GENESIS */
9353 /******************************************************************************
9355 * SkAddrGmacMcAdd - add a multicast address to a port
9357 * SK_MC_FILTERING_INEXACT
9358 * SK_MC_ILLEGAL_ADDRESS
9360 -static int SkAddrGmacMcAdd(
9361 +int SkAddrGmacMcAdd(
9362 SK_AC *pAC, /* adapter context */
9363 SK_IOC IoC, /* I/O context */
9364 SK_U32 PortNumber, /* Port Number */
9365 @@ -804,28 +799,29 @@
9366 #ifndef SK_ADDR_CHEAT
9368 #endif /* !defined(SK_ADDR_CHEAT) */
9371 if (!(pMc->a[0] & SK_MC_BIT)) {
9372 /* Hashing only possible with multicast addresses */
9373 return (SK_MC_ILLEGAL_ADDRESS);
9377 #ifndef SK_ADDR_CHEAT
9380 /* Compute hash value of address. */
9381 HashBit = SkGmacMcHash(&pMc->a[0]);
9384 if (Flags & SK_ADDR_PERMANENT) { /* permanent => RLMT */
9387 /* Add bit to InexactRlmtFilter. */
9388 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[HashBit / 8] |=
9392 /* Copy bit to InexactFilter. */
9393 for (i = 0; i < 8; i++) {
9394 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |=
9395 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[i];
9399 SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
9400 ("GMAC InexactRlmtFilter: %02X %02X %02X %02X %02X %02X %02X %02X\n",
9401 @@ -836,20 +832,21 @@
9402 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[4],
9403 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[5],
9404 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[6],
9405 - pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[7]))
9406 + pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[7]));
9409 else { /* not permanent => DRV */
9412 /* Add bit to InexactDrvFilter. */
9413 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[HashBit / 8] |=
9417 /* Copy bit to InexactFilter. */
9418 for (i = 0; i < 8; i++) {
9419 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |=
9420 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[i];
9424 SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
9425 ("GMAC InexactDrvFilter: %02X %02X %02X %02X %02X %02X %02X %02X\n",
9426 @@ -860,22 +857,22 @@
9427 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[4],
9428 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[5],
9429 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[6],
9430 - pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[7]))
9431 + pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[7]));
9436 #else /* SK_ADDR_CHEAT */
9439 /* Set all bits in InexactFilter. */
9440 for (i = 0; i < 8; i++) {
9441 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] = 0xFF;
9443 #endif /* SK_ADDR_CHEAT */
9446 return (SK_MC_FILTERING_INEXACT);
9448 -} /* SkAddrGmacMcAdd */
9450 +} /* SkAddrGmacMcAdd */
9452 #endif /* !SK_SLIM */
9454 /******************************************************************************
9456 SK_IOC IoC, /* I/O context */
9457 SK_U32 PortNumber) /* Port Number */
9459 - int ReturnCode = 0;
9460 + int ReturnCode = SK_ADDR_ILLEGAL_PORT;
9462 #if (!defined(SK_SLIM) || defined(DEBUG))
9463 if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
9464 return (SK_ADDR_ILLEGAL_PORT);
9466 * SK_MC_FILTERING_INEXACT
9467 * SK_ADDR_ILLEGAL_PORT
9469 -static int SkAddrXmacMcUpdate(
9470 +int SkAddrXmacMcUpdate(
9471 SK_AC *pAC, /* adapter context */
9472 SK_IOC IoC, /* I/O context */
9473 SK_U32 PortNumber) /* Port Number */
9474 @@ -963,13 +961,13 @@
9475 SK_ADDR_PORT *pAPort;
9477 SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
9478 - ("SkAddrXmacMcUpdate on Port %u.\n", PortNumber))
9480 + ("SkAddrXmacMcUpdate on Port %u.\n", PortNumber));
9482 pAPort = &pAC->Addr.Port[PortNumber];
9485 SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
9486 - ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber]))
9487 + ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber]));
9490 /* Start with 0 to also program the logical MAC address. */
9493 /* Clear other permanent exact match addresses on XMAC */
9494 if (pAPort->NextExactMatchRlmt <= SK_ADDR_LAST_MATCH_RLMT) {
9497 SkXmClrExactAddr(pAC, IoC, PortNumber, pAPort->NextExactMatchRlmt,
9498 SK_ADDR_LAST_MATCH_RLMT);
9502 /* Clear other non-permanent exact match addresses on XMAC */
9503 if (pAPort->NextExactMatchDrv <= SK_ADDR_LAST_MATCH_DRV) {
9506 SkXmClrExactAddr(pAC, IoC, PortNumber, pAPort->NextExactMatchDrv,
9507 SK_ADDR_LAST_MATCH_DRV);
9509 @@ -1003,18 +1001,18 @@
9512 if (pAPort->PromMode & SK_PROM_MODE_ALL_MC) {
9515 /* Set all bits in 64-bit hash register. */
9516 XM_OUTHASH(IoC, PortNumber, XM_HSM, &OnesHash);
9519 /* Enable Hashing */
9520 SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
9522 else if (Inexact != 0) {
9525 /* Set 64-bit hash register to InexactFilter. */
9526 XM_OUTHASH(IoC, PortNumber, XM_HSM, &pAPort->InexactFilter.Bytes[0]);
9529 /* Enable Hashing */
9530 SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
9532 @@ -1029,7 +1027,7 @@
9534 /* Set port's current physical MAC address. */
9535 OutAddr = (SK_U16 *) &pAPort->CurrentMacAddress.a[0];
9538 XM_OUTADDR(IoC, PortNumber, XM_SA, OutAddr);
9541 @@ -1039,9 +1037,9 @@
9543 /* Get exact match address i from port PortNumber. */
9544 InAddr = (SK_U16 *) &InAddr8[0];
9547 XM_INADDR(IoC, PortNumber, XM_EXM(i), InAddr);
9550 SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
9551 ("SkAddrXmacMcUpdate: MC address %d on Port %u: ",
9552 "%02x %02x %02x %02x %02x %02x -- %02x %02x %02x %02x %02x %02x\n",
9553 @@ -1058,7 +1056,7 @@
9554 pAPort->Exact[i].a[2],
9555 pAPort->Exact[i].a[3],
9556 pAPort->Exact[i].a[4],
9557 - pAPort->Exact[i].a[5]))
9558 + pAPort->Exact[i].a[5]));
9562 @@ -1069,7 +1067,7 @@
9564 return (SK_MC_FILTERING_INEXACT);
9568 } /* SkAddrXmacMcUpdate */
9570 #endif /* GENESIS */
9571 @@ -1097,7 +1095,7 @@
9572 * SK_MC_FILTERING_INEXACT
9573 * SK_ADDR_ILLEGAL_PORT
9575 -static int SkAddrGmacMcUpdate(
9576 +int SkAddrGmacMcUpdate(
9577 SK_AC *pAC, /* adapter context */
9578 SK_IOC IoC, /* I/O context */
9579 SK_U32 PortNumber) /* Port Number */
9580 @@ -1110,37 +1108,37 @@
9581 SK_ADDR_PORT *pAPort;
9583 SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
9584 - ("SkAddrGmacMcUpdate on Port %u.\n", PortNumber))
9586 + ("SkAddrGmacMcUpdate on Port %u.\n", PortNumber));
9588 pAPort = &pAC->Addr.Port[PortNumber];
9591 SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
9592 - ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber]))
9593 + ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber]));
9598 for (Inexact = 0, i = 0; i < 8; i++) {
9599 Inexact |= pAPort->InexactFilter.Bytes[i];
9603 /* Set 64-bit hash register to InexactFilter. */
9604 GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1,
9605 &pAPort->InexactFilter.Bytes[0]);
9607 - if (pAPort->PromMode & SK_PROM_MODE_ALL_MC) {
9610 + if (pAPort->PromMode & SK_PROM_MODE_ALL_MC) {
9612 /* Set all bits in 64-bit hash register. */
9613 GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1, &OnesHash);
9616 /* Enable Hashing */
9617 SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
9621 /* Enable Hashing. */
9622 SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
9626 if (pAPort->PromMode != SK_PROM_MODE_NONE) {
9627 (void) SkAddrGmacPromiscuousChange(pAC, IoC, PortNumber, pAPort->PromMode);
9629 @@ -1151,19 +1149,19 @@
9631 /* Enable Hashing */
9632 SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
9635 (void) SkAddrGmacPromiscuousChange(pAC, IoC, PortNumber, pAPort->PromMode);
9638 #endif /* SK_SLIM */
9641 /* Set port's current physical MAC address. */
9642 OutAddr = (SK_U16 *) &pAPort->CurrentMacAddress.a[0];
9643 GM_OUTADDR(IoC, PortNumber, GM_SRC_ADDR_1L, OutAddr);
9646 /* Set port's current logical MAC address. */
9647 OutAddr = (SK_U16 *) &pAPort->Exact[0].a[0];
9648 GM_OUTADDR(IoC, PortNumber, GM_SRC_ADDR_2L, OutAddr);
9652 SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
9653 ("SkAddrGmacMcUpdate: Permanent Physical MAC Address: %02X %02X %02X %02X %02X %02X\n",
9654 @@ -1172,8 +1170,8 @@
9655 pAPort->Exact[0].a[2],
9656 pAPort->Exact[0].a[3],
9657 pAPort->Exact[0].a[4],
9658 - pAPort->Exact[0].a[5]))
9660 + pAPort->Exact[0].a[5]));
9662 SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
9663 ("SkAddrGmacMcUpdate: Physical MAC Address: %02X %02X %02X %02X %02X %02X\n",
9664 pAPort->CurrentMacAddress.a[0],
9665 @@ -1181,9 +1179,9 @@
9666 pAPort->CurrentMacAddress.a[2],
9667 pAPort->CurrentMacAddress.a[3],
9668 pAPort->CurrentMacAddress.a[4],
9669 - pAPort->CurrentMacAddress.a[5]))
9670 + pAPort->CurrentMacAddress.a[5]));
9675 /* Determine return value. */
9676 if (Inexact == 0 && pAPort->PromMode == 0) {
9677 @@ -1195,7 +1193,7 @@
9679 return (SK_MC_FILTERING_INEXACT);
9680 #endif /* SK_SLIM */
9683 } /* SkAddrGmacMcUpdate */
9686 @@ -1243,6 +1241,11 @@
9687 return (SK_ADDR_ILLEGAL_PORT);
9689 #endif /* !SK_SLIM || DEBUG */
9691 + if (pNewAddr == NULL) {
9695 if (pNewAddr != NULL && (pNewAddr->a[0] & SK_MC_BIT) != 0) {
9696 return (SK_ADDR_MULTICAST_ADDRESS);
9698 @@ -1290,26 +1293,46 @@
9699 (void) SkAddrMcUpdate(pAC, IoC, PortNumber);
9701 else if (Flags & SK_ADDR_PHYSICAL_ADDRESS) { /* Physical MAC address. */
9702 - if (SK_ADDR_EQUAL(pNewAddr->a,
9703 - pAC->Addr.Net[NetNumber].CurrentMacAddress.a)) {
9704 - return (SK_ADDR_DUPLICATE_ADDRESS);
9707 for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) {
9708 if (!pAC->Addr.Port[i].CurrentMacAddressSet) {
9709 return (SK_ADDR_TOO_EARLY);
9714 + * In dual net mode it should be possible to set all MAC
9715 + * addresses independently. Therefore the equality checks
9716 + * against the locical address of the same port and the
9717 + * physical address of the other port are suppressed here.
9720 + if (pAC->Rlmt.NumNets == 1) {
9721 +#endif /* SK_NO_RLMT */
9722 if (SK_ADDR_EQUAL(pNewAddr->a,
9723 - pAC->Addr.Port[i].CurrentMacAddress.a)) {
9724 - if (i == PortNumber) {
9725 - return (SK_ADDR_SUCCESS);
9728 - return (SK_ADDR_DUPLICATE_ADDRESS);
9729 + pAC->Addr.Net[NetNumber].CurrentMacAddress.a)) {
9730 + return (SK_ADDR_DUPLICATE_ADDRESS);
9733 + for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) {
9734 + if (SK_ADDR_EQUAL(pNewAddr->a,
9735 + pAC->Addr.Port[i].CurrentMacAddress.a)) {
9736 + if (i == PortNumber) {
9737 + return (SK_ADDR_SUCCESS);
9740 + return (SK_ADDR_DUPLICATE_ADDRESS);
9747 + if (SK_ADDR_EQUAL(pNewAddr->a,
9748 + pAC->Addr.Port[PortNumber].CurrentMacAddress.a)) {
9749 + return (SK_ADDR_SUCCESS);
9752 +#endif /* SK_NO_RLMT */
9754 pAC->Addr.Port[PortNumber].PreviousMacAddress =
9755 pAC->Addr.Port[PortNumber].CurrentMacAddress;
9756 @@ -1340,18 +1363,32 @@
9757 pAC->Addr.Net[NetNumber].CurrentMacAddress.a)) {
9758 return (SK_ADDR_SUCCESS);
9762 for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) {
9763 if (!pAC->Addr.Port[i].CurrentMacAddressSet) {
9764 return (SK_ADDR_TOO_EARLY);
9768 - if (SK_ADDR_EQUAL(pNewAddr->a,
9769 - pAC->Addr.Port[i].CurrentMacAddress.a)) {
9770 - return (SK_ADDR_DUPLICATE_ADDRESS);
9772 + * In dual net mode on Yukon-2 adapters the physical address
9773 + * of port 0 and the logical address of port 1 are equal - in
9774 + * this case the equality check of the physical address leads
9775 + * to an error and is suppressed here.
9778 + if (pAC->Rlmt.NumNets == 1) {
9779 +#endif /* SK_NO_RLMT */
9780 + for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) {
9781 + if (SK_ADDR_EQUAL(pNewAddr->a,
9782 + pAC->Addr.Port[i].CurrentMacAddress.a)) {
9783 + return (SK_ADDR_DUPLICATE_ADDRESS);
9789 +#endif /* SK_NO_RLMT */
9792 * In case that the physical and the logical MAC addresses are equal
9793 * we must also change the physical MAC address here.
9794 @@ -1360,11 +1397,11 @@
9796 if (SK_ADDR_EQUAL(pAC->Addr.Port[PortNumber].CurrentMacAddress.a,
9797 pAC->Addr.Port[PortNumber].Exact[0].a)) {
9800 pAC->Addr.Port[PortNumber].PreviousMacAddress =
9801 pAC->Addr.Port[PortNumber].CurrentMacAddress;
9802 pAC->Addr.Port[PortNumber].CurrentMacAddress = *pNewAddr;
9806 /* Report address change to RLMT. */
9807 Para.Para32[0] = PortNumber;
9808 @@ -1372,7 +1409,7 @@
9809 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_PORT_ADDR, Para);
9810 #endif /* !SK_NO_RLMT */
9815 /* Set PortNumber to number of net's active port. */
9816 PortNumber = pAC->Rlmt.Net[NetNumber].
9817 @@ -1388,8 +1425,8 @@
9818 pAC->Addr.Net[NetNumber].PermanentMacAddress.a[2],
9819 pAC->Addr.Net[NetNumber].PermanentMacAddress.a[3],
9820 pAC->Addr.Net[NetNumber].PermanentMacAddress.a[4],
9821 - pAC->Addr.Net[NetNumber].PermanentMacAddress.a[5]))
9823 + pAC->Addr.Net[NetNumber].PermanentMacAddress.a[5]));
9825 SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
9826 ("SkAddrOverride: New logical MAC Address: %02X %02X %02X %02X %02X %02X\n",
9827 pAC->Addr.Net[NetNumber].CurrentMacAddress.a[0],
9828 @@ -1397,17 +1434,16 @@
9829 pAC->Addr.Net[NetNumber].CurrentMacAddress.a[2],
9830 pAC->Addr.Net[NetNumber].CurrentMacAddress.a[3],
9831 pAC->Addr.Net[NetNumber].CurrentMacAddress.a[4],
9832 - pAC->Addr.Net[NetNumber].CurrentMacAddress.a[5]))
9833 + pAC->Addr.Net[NetNumber].CurrentMacAddress.a[5]));
9836 - /* Write address to first exact match entry of active port. */
9837 - (void) SkAddrMcUpdate(pAC, IoC, PortNumber);
9838 + /* Write address to first exact match entry of active port. */
9839 + (void)SkAddrMcUpdate(pAC, IoC, PortNumber);
9842 return (SK_ADDR_SUCCESS);
9844 -} /* SkAddrOverride */
9846 +} /* SkAddrOverride */
9848 #endif /* SK_NO_MAO */
9850 @@ -1439,7 +1475,8 @@
9851 SK_U32 PortNumber, /* port whose promiscuous mode changes */
9852 int NewPromMode) /* new promiscuous mode */
9854 - int ReturnCode = 0;
9855 + int ReturnCode = SK_ADDR_ILLEGAL_PORT;
9857 #if (!defined(SK_SLIM) || defined(DEBUG))
9858 if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
9859 return (SK_ADDR_ILLEGAL_PORT);
9860 @@ -1483,7 +1520,7 @@
9862 * SK_ADDR_ILLEGAL_PORT
9864 -static int SkAddrXmacPromiscuousChange(
9865 +int SkAddrXmacPromiscuousChange(
9866 SK_AC *pAC, /* adapter context */
9867 SK_IOC IoC, /* I/O context */
9868 SK_U32 PortNumber, /* port whose promiscuous mode changes */
9869 @@ -1504,17 +1541,18 @@
9870 /* Promiscuous mode! */
9871 CurPromMode |= SK_PROM_MODE_LLC;
9875 for (Inexact = 0xFF, i = 0; i < 8; i++) {
9876 Inexact &= pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i];
9879 if (Inexact == 0xFF) {
9880 CurPromMode |= (pAC->Addr.Port[PortNumber].PromMode & SK_PROM_MODE_ALL_MC);
9883 /* Get InexactModeBit (bit XM_MD_ENA_HASH in mode register) */
9884 XM_IN16(IoC, PortNumber, XM_MODE, &LoMode);
9887 InexactModeBit = (LoMode & XM_MD_ENA_HASH) != 0;
9889 /* Read 64-bit hash register from XMAC */
9890 @@ -1537,7 +1575,7 @@
9892 if ((NewPromMode & SK_PROM_MODE_ALL_MC) &&
9893 !(CurPromMode & SK_PROM_MODE_ALL_MC)) { /* All MC. */
9896 /* Set all bits in 64-bit hash register. */
9897 XM_OUTHASH(IoC, PortNumber, XM_HSM, &OnesHash);
9899 @@ -1573,9 +1611,9 @@
9900 /* Clear Promiscuous Mode */
9901 SkMacPromiscMode(pAC, IoC, (int) PortNumber, SK_FALSE);
9905 return (SK_ADDR_SUCCESS);
9908 } /* SkAddrXmacPromiscuousChange */
9910 #endif /* GENESIS */
9911 @@ -1600,70 +1638,42 @@
9913 * SK_ADDR_ILLEGAL_PORT
9915 -static int SkAddrGmacPromiscuousChange(
9916 +int SkAddrGmacPromiscuousChange(
9917 SK_AC *pAC, /* adapter context */
9918 SK_IOC IoC, /* I/O context */
9919 SK_U32 PortNumber, /* port whose promiscuous mode changes */
9920 int NewPromMode) /* new promiscuous mode */
9922 - SK_U16 ReceiveControl; /* GMAC Receive Control Register */
9923 - int CurPromMode = SK_PROM_MODE_NONE;
9925 - /* Read CurPromMode from Hardware. */
9926 - GM_IN16(IoC, PortNumber, GM_RX_CTRL, &ReceiveControl);
9928 - if ((ReceiveControl & (GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA)) == 0) {
9929 - /* Promiscuous mode! */
9930 - CurPromMode |= SK_PROM_MODE_LLC;
9931 + if (PortNumber >= (SK_U32)pAC->GIni.GIMacsFound) {
9932 + return (SK_ADDR_ILLEGAL_PORT);
9935 - if ((ReceiveControl & GM_RXCR_MCF_ENA) == 0) {
9936 - /* All Multicast mode! */
9937 - CurPromMode |= (pAC->Addr.Port[PortNumber].PromMode & SK_PROM_MODE_ALL_MC);
9939 + switch(NewPromMode) {
9940 + case (SK_PROM_MODE_NONE): /* 0 */
9942 - pAC->Addr.Port[PortNumber].PromMode = NewPromMode;
9943 + /* Normal receive mode */
9944 + SkMacPromiscMode(pAC, IoC, (int) PortNumber, SK_FALSE);
9947 - if (NewPromMode == CurPromMode) {
9948 - return (SK_ADDR_SUCCESS);
9951 - if ((NewPromMode & SK_PROM_MODE_ALL_MC) &&
9952 - !(CurPromMode & SK_PROM_MODE_ALL_MC)) { /* All MC */
9954 - /* Set all bits in 64-bit hash register. */
9955 - GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1, &OnesHash);
9957 - /* Enable Hashing */
9958 - SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
9961 - if ((CurPromMode & SK_PROM_MODE_ALL_MC) &&
9962 - !(NewPromMode & SK_PROM_MODE_ALL_MC)) { /* Norm. MC */
9963 + case (SK_PROM_MODE_LLC): /* 1 */
9964 + /* This mode is ignored and mapped to prom. mode */
9965 + case (SK_PROM_MODE_LLC | SK_PROM_MODE_ALL_MC): /* 3 */
9967 - /* Set 64-bit hash register to InexactFilter. */
9968 - GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1,
9969 - &pAC->Addr.Port[PortNumber].InexactFilter.Bytes[0]);
9970 + /* Set the MAC to promiscuous mode. */
9971 + SkMacPromiscMode(pAC, IoC, (int) PortNumber, SK_TRUE);
9974 - /* Enable Hashing. */
9975 - SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
9977 + case (SK_PROM_MODE_ALL_MC): /* 2 */
9979 - if ((NewPromMode & SK_PROM_MODE_LLC) &&
9980 - !(CurPromMode & SK_PROM_MODE_LLC)) { /* Prom. LLC */
9982 - /* Set the MAC to Promiscuous Mode. */
9983 - SkMacPromiscMode(pAC, IoC, (int) PortNumber, SK_TRUE);
9985 - else if ((CurPromMode & SK_PROM_MODE_LLC) &&
9986 - !(NewPromMode & SK_PROM_MODE_LLC)) { /* Norm. LLC */
9988 - /* Clear Promiscuous Mode. */
9989 - SkMacPromiscMode(pAC, IoC, (int) PortNumber, SK_FALSE);
9990 + /* Disable MC hashing */
9991 + SkMacHashing(pAC, IoC, (int) PortNumber, SK_FALSE);
9998 return (SK_ADDR_SUCCESS);
10000 } /* SkAddrGmacPromiscuousChange */
10003 @@ -1735,33 +1745,33 @@
10004 pAC->Addr.Port[ToPortNumber].InexactFilter.Bytes[i];
10005 pAC->Addr.Port[ToPortNumber].InexactFilter.Bytes[i] = Byte;
10009 i = pAC->Addr.Port[FromPortNumber].PromMode;
10010 pAC->Addr.Port[FromPortNumber].PromMode = pAC->Addr.Port[ToPortNumber].PromMode;
10011 pAC->Addr.Port[ToPortNumber].PromMode = i;
10014 if (pAC->GIni.GIGenesis) {
10015 DWord = pAC->Addr.Port[FromPortNumber].FirstExactMatchRlmt;
10016 pAC->Addr.Port[FromPortNumber].FirstExactMatchRlmt =
10017 pAC->Addr.Port[ToPortNumber].FirstExactMatchRlmt;
10018 pAC->Addr.Port[ToPortNumber].FirstExactMatchRlmt = DWord;
10021 DWord = pAC->Addr.Port[FromPortNumber].NextExactMatchRlmt;
10022 pAC->Addr.Port[FromPortNumber].NextExactMatchRlmt =
10023 pAC->Addr.Port[ToPortNumber].NextExactMatchRlmt;
10024 pAC->Addr.Port[ToPortNumber].NextExactMatchRlmt = DWord;
10027 DWord = pAC->Addr.Port[FromPortNumber].FirstExactMatchDrv;
10028 pAC->Addr.Port[FromPortNumber].FirstExactMatchDrv =
10029 pAC->Addr.Port[ToPortNumber].FirstExactMatchDrv;
10030 pAC->Addr.Port[ToPortNumber].FirstExactMatchDrv = DWord;
10033 DWord = pAC->Addr.Port[FromPortNumber].NextExactMatchDrv;
10034 pAC->Addr.Port[FromPortNumber].NextExactMatchDrv =
10035 pAC->Addr.Port[ToPortNumber].NextExactMatchDrv;
10036 pAC->Addr.Port[ToPortNumber].NextExactMatchDrv = DWord;
10040 /* CAUTION: Solution works if only ports of one adapter are in use. */
10041 for (i = 0; (SK_U32) i < pAC->Rlmt.Net[pAC->Rlmt.Port[ToPortNumber].
10042 Net->NetNumber].NumPorts; i++) {
10043 @@ -1772,12 +1782,12 @@
10044 /* 20001207 RA: Was "ToPortNumber;". */
10049 (void) SkAddrMcUpdate(pAC, IoC, FromPortNumber);
10050 (void) SkAddrMcUpdate(pAC, IoC, ToPortNumber);
10052 return (SK_ADDR_SUCCESS);
10057 #endif /* !SK_SLIM */
10058 diff -ruN linux/drivers/net/sk98lin/skcsum.c linux-new/drivers/net/sk98lin/skcsum.c
10059 --- linux/drivers/net/sk98lin/skcsum.c 1970-01-01 01:00:00.000000000 +0100
10060 +++ linux-new/drivers/net/sk98lin/skcsum.c 2006-07-28 14:13:54.000000000 +0200
10062 +/******************************************************************************
10065 + * Project: GEnesis, PCI Gigabit Ethernet Adapter
10066 + * Version: $Revision$
10068 + * Purpose: Store/verify Internet checksum in send/receive packets.
10070 + ******************************************************************************/
10072 +/******************************************************************************
10075 + * (C)Copyright 1998-2003 SysKonnect GmbH.
10077 + * This program is free software; you can redistribute it and/or modify
10078 + * it under the terms of the GNU General Public License as published by
10079 + * the Free Software Foundation; either version 2 of the License, or
10080 + * (at your option) any later version.
10082 + * The information in this file is provided "AS IS" without warranty.
10085 + ******************************************************************************/
10087 +#ifdef SK_USE_CSUM /* Check if CSUM is to be used. */
10090 +static const char SysKonnectFileId[] =
10091 + "@(#) $Id$ (C) SysKonnect.";
10092 +#endif /* !lint */
10094 +/******************************************************************************
10098 + * This is the "GEnesis" common module "CSUM".
10100 + * This module contains the code necessary to calculate, store, and verify the
10101 + * Internet Checksum of IP, TCP, and UDP frames.
10103 + * "GEnesis" is an abbreviation of "Gigabit Ethernet Network System in Silicon"
10104 + * and is the code name of this SysKonnect project.
10106 + * Compilation Options:
10108 + * SK_USE_CSUM - Define if CSUM is to be used. Otherwise, CSUM will be an
10111 + * SKCS_OVERWRITE_PROTO - Define to overwrite the default protocol id
10112 + * definitions. In this case, all SKCS_PROTO_xxx definitions must be made
10115 + * SKCS_OVERWRITE_STATUS - Define to overwrite the default return status
10116 + * definitions. In this case, all SKCS_STATUS_xxx definitions must be made
10119 + * Include File Hierarchy:
10127 + ******************************************************************************/
10129 +#include "h/skdrv1st.h"
10130 +#include "h/skcsum.h"
10131 +#include "h/skdrv2nd.h"
10133 +/* defines ********************************************************************/
10135 +/* The size of an Ethernet MAC header. */
10136 +#define SKCS_ETHERNET_MAC_HEADER_SIZE (6+6+2)
10138 +/* The size of the used topology's MAC header. */
10139 +#define SKCS_MAC_HEADER_SIZE SKCS_ETHERNET_MAC_HEADER_SIZE
10141 +/* The size of the IP header without any option fields. */
10142 +#define SKCS_IP_HEADER_SIZE 20
10145 + * Field offsets within the IP header.
10148 +/* "Internet Header Version" and "Length". */
10149 +#define SKCS_OFS_IP_HEADER_VERSION_AND_LENGTH 0
10151 +/* "Total Length". */
10152 +#define SKCS_OFS_IP_TOTAL_LENGTH 2
10154 +/* "Flags" "Fragment Offset". */
10155 +#define SKCS_OFS_IP_FLAGS_AND_FRAGMENT_OFFSET 6
10157 +/* "Next Level Protocol" identifier. */
10158 +#define SKCS_OFS_IP_NEXT_LEVEL_PROTOCOL 9
10160 +/* Source IP address. */
10161 +#define SKCS_OFS_IP_SOURCE_ADDRESS 12
10163 +/* Destination IP address. */
10164 +#define SKCS_OFS_IP_DESTINATION_ADDRESS 16
10168 + * Field offsets within the UDP header.
10171 +/* UDP checksum. */
10172 +#define SKCS_OFS_UDP_CHECKSUM 6
10174 +/* IP "Next Level Protocol" identifiers (see RFC 790). */
10175 +#define SKCS_PROTO_ID_TCP 6 /* Transport Control Protocol */
10176 +#define SKCS_PROTO_ID_UDP 17 /* User Datagram Protocol */
10178 +/* IP "Don't Fragment" bit. */
10179 +#define SKCS_IP_DONT_FRAGMENT SKCS_HTON16(0x4000)
10181 +/* Add a byte offset to a pointer. */
10182 +#define SKCS_IDX(pPtr, Ofs) ((void *) ((char *) (pPtr) + (Ofs)))
10185 + * Macros that convert host to network representation and vice versa, i.e.
10186 + * little/big endian conversion on little endian machines only.
10188 +#ifdef SK_LITTLE_ENDIAN
10189 +#define SKCS_HTON16(Val16) (((unsigned) (Val16) >> 8) | (((Val16) & 0xff) << 8))
10190 +#endif /* SK_LITTLE_ENDIAN */
10191 +#ifdef SK_BIG_ENDIAN
10192 +#define SKCS_HTON16(Val16) (Val16)
10193 +#endif /* SK_BIG_ENDIAN */
10194 +#define SKCS_NTOH16(Val16) SKCS_HTON16(Val16)
10196 +/* typedefs *******************************************************************/
10198 +/* function prototypes ********************************************************/
10200 +/******************************************************************************
10202 + * SkCsGetSendInfo - get checksum information for a send packet
10205 + * Get all checksum information necessary to send a TCP or UDP packet. The
10206 + * function checks the IP header passed to it. If the high-level protocol
10207 + * is either TCP or UDP the pseudo header checksum is calculated and
10210 + * The function returns the total length of the IP header (including any
10211 + * IP option fields), which is the same as the start offset of the IP data
10212 + * which in turn is the start offset of the TCP or UDP header.
10214 + * The function also returns the TCP or UDP pseudo header checksum, which
10215 + * should be used as the start value for the hardware checksum calculation.
10216 + * (Note that any actual pseudo header checksum can never calculate to
10220 + * There is a bug in the GENESIS ASIC which may lead to wrong checksums.
10223 + * pAc - A pointer to the adapter context struct.
10225 + * pIpHeader - Pointer to IP header. Must be at least the IP header *not*
10226 + * including any option fields, i.e. at least 20 bytes.
10228 + * Note: This pointer will be used to address 8-, 16-, and 32-bit
10229 + * variables with the respective alignment offsets relative to the pointer.
10230 + * Thus, the pointer should point to a 32-bit aligned address. If the
10231 + * target system cannot address 32-bit variables on non 32-bit aligned
10232 + * addresses, then the pointer *must* point to a 32-bit aligned address.
10234 + * pPacketInfo - A pointer to the packet information structure for this
10235 + * packet. Before calling this SkCsGetSendInfo(), the following field must
10236 + * be initialized:
10238 + * ProtocolFlags - Initialize with any combination of
10239 + * SKCS_PROTO_XXX bit flags. SkCsGetSendInfo() will only work on
10240 + * the protocols specified here. Any protocol(s) not specified
10241 + * here will be ignored.
10243 + * Note: Only one checksum can be calculated in hardware. Thus, if
10244 + * SKCS_PROTO_IP is specified in the 'ProtocolFlags',
10245 + * SkCsGetSendInfo() must calculate the IP header checksum in
10246 + * software. It might be a better idea to have the calling
10247 + * protocol stack calculate the IP header checksum.
10250 + * On return, the following fields in 'pPacketInfo' may or may not have
10251 + * been filled with information, depending on the protocol(s) found in the
10254 + * ProtocolFlags - Returns the SKCS_PROTO_XXX bit flags of the protocol(s)
10255 + * that were both requested by the caller and actually found in the packet.
10256 + * Protocol(s) not specified by the caller and/or not found in the packet
10257 + * will have their respective SKCS_PROTO_XXX bit flags reset.
10259 + * Note: For IP fragments, TCP and UDP packet information is ignored.
10261 + * IpHeaderLength - The total length in bytes of the complete IP header
10262 + * including any option fields is returned here. This is the start offset
10263 + * of the IP data, i.e. the TCP or UDP header if present.
10265 + * IpHeaderChecksum - If IP has been specified in the 'ProtocolFlags', the
10266 + * 16-bit Internet Checksum of the IP header is returned here. This value
10267 + * is to be stored into the packet's 'IP Header Checksum' field.
10269 + * PseudoHeaderChecksum - If this is a TCP or UDP packet and if TCP or UDP
10270 + * has been specified in the 'ProtocolFlags', the 16-bit Internet Checksum
10271 + * of the TCP or UDP pseudo header is returned here.
10273 +void SkCsGetSendInfo(
10274 +SK_AC *pAc, /* Adapter context struct. */
10275 +void *pIpHeader, /* IP header. */
10276 +SKCS_PACKET_INFO *pPacketInfo, /* Packet information struct. */
10277 +int NetNumber) /* Net number */
10279 + /* Internet Header Version found in IP header. */
10280 + unsigned InternetHeaderVersion;
10282 + /* Length of the IP header as found in IP header. */
10283 + unsigned IpHeaderLength;
10285 + /* Bit field specifiying the desired/found protocols. */
10286 + unsigned ProtocolFlags;
10288 + /* Next level protocol identifier found in IP header. */
10289 + unsigned NextLevelProtocol;
10291 + /* Length of IP data portion. */
10292 + unsigned IpDataLength;
10294 + /* TCP/UDP pseudo header checksum. */
10295 + unsigned long PseudoHeaderChecksum;
10297 + /* Pointer to next level protocol statistics structure. */
10298 + SKCS_PROTO_STATS *NextLevelProtoStats;
10300 + /* Temporary variable. */
10304 + SKCS_IDX(pIpHeader, SKCS_OFS_IP_HEADER_VERSION_AND_LENGTH);
10306 + /* Get the Internet Header Version (IHV). */
10307 + /* Note: The IHV is stored in the upper four bits. */
10309 + InternetHeaderVersion = Tmp >> 4;
10311 + /* Check the Internet Header Version. */
10312 + /* Note: We currently only support IP version 4. */
10314 + if (InternetHeaderVersion != 4) { /* IPv4? */
10315 + SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_TX,
10316 + ("Tx: Unknown Internet Header Version %u.\n",
10317 + InternetHeaderVersion));
10318 + pPacketInfo->ProtocolFlags = 0;
10319 + pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].TxUnableCts++;
10323 + /* Get the IP header length (IHL). */
10325 + * Note: The IHL is stored in the lower four bits as the number of
10329 + IpHeaderLength = (Tmp & 0xf) * 4;
10330 + pPacketInfo->IpHeaderLength = IpHeaderLength;
10332 + /* Check the IP header length. */
10334 + /* 04-Aug-1998 sw - Really check the IHL? Necessary? */
10336 + if (IpHeaderLength < 5*4) {
10337 + SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_TX,
10338 + ("Tx: Invalid IP Header Length %u.\n", IpHeaderLength));
10339 + pPacketInfo->ProtocolFlags = 0;
10340 + pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].TxUnableCts++;
10344 + /* This is an IPv4 frame with a header of valid length. */
10346 + pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].TxOkCts++;
10348 + /* Check if we should calculate the IP header checksum. */
10350 + ProtocolFlags = pPacketInfo->ProtocolFlags;
10352 + if (ProtocolFlags & SKCS_PROTO_IP) {
10353 + pPacketInfo->IpHeaderChecksum =
10354 + SkCsCalculateChecksum(pIpHeader, IpHeaderLength);
10357 + /* Get the next level protocol identifier. */
10359 + NextLevelProtocol =
10360 + *(SK_U8 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_NEXT_LEVEL_PROTOCOL);
10363 + * Check if this is a TCP or UDP frame and if we should calculate the
10364 + * TCP/UDP pseudo header checksum.
10366 + * Also clear all protocol bit flags of protocols not present in the
10370 + if ((ProtocolFlags & SKCS_PROTO_TCP) != 0 &&
10371 + NextLevelProtocol == SKCS_PROTO_ID_TCP) {
10372 + /* TCP/IP frame. */
10373 + ProtocolFlags &= SKCS_PROTO_TCP | SKCS_PROTO_IP;
10374 + NextLevelProtoStats =
10375 + &pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_TCP];
10377 + else if ((ProtocolFlags & SKCS_PROTO_UDP) != 0 &&
10378 + NextLevelProtocol == SKCS_PROTO_ID_UDP) {
10379 + /* UDP/IP frame. */
10380 + ProtocolFlags &= SKCS_PROTO_UDP | SKCS_PROTO_IP;
10381 + NextLevelProtoStats =
10382 + &pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_UDP];
10386 + * Either not a TCP or UDP frame and/or TCP/UDP processing not
10389 + pPacketInfo->ProtocolFlags = ProtocolFlags & SKCS_PROTO_IP;
10393 + /* Check if this is an IP fragment. */
10396 + * Note: An IP fragment has a non-zero "Fragment Offset" field and/or
10397 + * the "More Fragments" bit set. Thus, if both the "Fragment Offset"
10398 + * and the "More Fragments" are zero, it is *not* a fragment. We can
10399 + * easily check both at the same time since they are in the same 16-bit
10404 + SKCS_IDX(pIpHeader, SKCS_OFS_IP_FLAGS_AND_FRAGMENT_OFFSET) &
10405 + ~SKCS_IP_DONT_FRAGMENT) != 0) {
10406 + /* IP fragment; ignore all other protocols. */
10407 + pPacketInfo->ProtocolFlags = ProtocolFlags & SKCS_PROTO_IP;
10408 + NextLevelProtoStats->TxUnableCts++;
10413 + * Calculate the TCP/UDP pseudo header checksum.
10416 + /* Get total length of IP header and data. */
10419 + *(SK_U16 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_TOTAL_LENGTH);
10421 + /* Get length of IP data portion. */
10423 + IpDataLength = SKCS_NTOH16(IpDataLength) - IpHeaderLength;
10425 + /* Calculate the sum of all pseudo header fields (16-bit). */
10427 + PseudoHeaderChecksum =
10428 + (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
10429 + SKCS_OFS_IP_SOURCE_ADDRESS + 0) +
10430 + (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
10431 + SKCS_OFS_IP_SOURCE_ADDRESS + 2) +
10432 + (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
10433 + SKCS_OFS_IP_DESTINATION_ADDRESS + 0) +
10434 + (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
10435 + SKCS_OFS_IP_DESTINATION_ADDRESS + 2) +
10436 + (unsigned long) SKCS_HTON16(NextLevelProtocol) +
10437 + (unsigned long) SKCS_HTON16(IpDataLength);
10439 + /* Add-in any carries. */
10441 + SKCS_OC_ADD(PseudoHeaderChecksum, PseudoHeaderChecksum, 0);
10443 + /* Add-in any new carry. */
10445 + SKCS_OC_ADD(pPacketInfo->PseudoHeaderChecksum, PseudoHeaderChecksum, 0);
10447 + pPacketInfo->ProtocolFlags = ProtocolFlags;
10448 + NextLevelProtoStats->TxOkCts++; /* Success. */
10449 +} /* SkCsGetSendInfo */
10452 +/******************************************************************************
10454 + * SkCsGetReceiveInfo - verify checksum information for a received packet
10457 + * Verify a received frame's checksum. The function returns a status code
10458 + * reflecting the result of the verification.
10461 + * Before calling this function you have to verify that the frame is
10462 + * not padded and Checksum1 and Checksum2 are bigger than 1.
10465 + * pAc - Pointer to adapter context struct.
10467 + * pIpHeader - Pointer to IP header. Must be at least the length in bytes
10468 + * of the received IP header including any option fields. For UDP packets,
10469 + * 8 additional bytes are needed to access the UDP checksum.
10471 + * Note: The actual length of the IP header is stored in the lower four
10472 + * bits of the first octet of the IP header as the number of 4-byte words,
10473 + * so it must be multiplied by four to get the length in bytes. Thus, the
10474 + * maximum IP header length is 15 * 4 = 60 bytes.
10476 + * Checksum1 - The first 16-bit Internet Checksum calculated by the
10477 + * hardware starting at the offset returned by SkCsSetReceiveFlags().
10479 + * Checksum2 - The second 16-bit Internet Checksum calculated by the
10480 + * hardware starting at the offset returned by SkCsSetReceiveFlags().
10483 + * SKCS_STATUS_UNKNOWN_IP_VERSION - Not an IP v4 frame.
10484 + * SKCS_STATUS_IP_CSUM_ERROR - IP checksum error.
10485 + * SKCS_STATUS_IP_CSUM_ERROR_TCP - IP checksum error in TCP frame.
10486 + * SKCS_STATUS_IP_CSUM_ERROR_UDP - IP checksum error in UDP frame
10487 + * SKCS_STATUS_IP_FRAGMENT - IP fragment (IP checksum ok).
10488 + * SKCS_STATUS_IP_CSUM_OK - IP checksum ok (not a TCP or UDP frame).
10489 + * SKCS_STATUS_TCP_CSUM_ERROR - TCP checksum error (IP checksum ok).
10490 + * SKCS_STATUS_UDP_CSUM_ERROR - UDP checksum error (IP checksum ok).
10491 + * SKCS_STATUS_TCP_CSUM_OK - IP and TCP checksum ok.
10492 + * SKCS_STATUS_UDP_CSUM_OK - IP and UDP checksum ok.
10493 + * SKCS_STATUS_IP_CSUM_OK_NO_UDP - IP checksum OK and no UDP checksum.
10495 + * Note: If SKCS_OVERWRITE_STATUS is defined, the SKCS_STATUS_XXX values
10496 + * returned here can be defined in some header file by the module using CSUM.
10497 + * In this way, the calling module can assign return values for its own needs,
10498 + * e.g. by assigning bit flags to the individual protocols.
10500 +SKCS_STATUS SkCsGetReceiveInfo(
10501 +SK_AC *pAc, /* Adapter context struct. */
10502 +void *pIpHeader, /* IP header. */
10503 +unsigned Checksum1, /* Hardware checksum 1. */
10504 +unsigned Checksum2, /* Hardware checksum 2. */
10505 +int NetNumber) /* Net number */
10507 + /* Internet Header Version found in IP header. */
10508 + unsigned InternetHeaderVersion;
10510 + /* Length of the IP header as found in IP header. */
10511 + unsigned IpHeaderLength;
10513 + /* Length of IP data portion. */
10514 + unsigned IpDataLength;
10516 + /* IP header checksum. */
10517 + unsigned IpHeaderChecksum;
10519 + /* IP header options checksum, if any. */
10520 + unsigned IpOptionsChecksum;
10522 + /* IP data checksum, i.e. TCP/UDP checksum. */
10523 + unsigned IpDataChecksum;
10525 + /* Next level protocol identifier found in IP header. */
10526 + unsigned NextLevelProtocol;
10528 + /* The checksum of the "next level protocol", i.e. TCP or UDP. */
10529 + unsigned long NextLevelProtocolChecksum;
10531 + /* Pointer to next level protocol statistics structure. */
10532 + SKCS_PROTO_STATS *NextLevelProtoStats;
10534 + /* Temporary variable. */
10538 + SKCS_IDX(pIpHeader, SKCS_OFS_IP_HEADER_VERSION_AND_LENGTH);
10540 + /* Get the Internet Header Version (IHV). */
10541 + /* Note: The IHV is stored in the upper four bits. */
10543 + InternetHeaderVersion = Tmp >> 4;
10545 + /* Check the Internet Header Version. */
10546 + /* Note: We currently only support IP version 4. */
10548 + if (InternetHeaderVersion != 4) { /* IPv4? */
10549 + SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_RX,
10550 + ("Rx: Unknown Internet Header Version %u.\n",
10551 + InternetHeaderVersion));
10552 + pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxUnableCts++;
10553 + return (SKCS_STATUS_UNKNOWN_IP_VERSION);
10556 + /* Get the IP header length (IHL). */
10558 + * Note: The IHL is stored in the lower four bits as the number of
10562 + IpHeaderLength = (Tmp & 0xf) * 4;
10564 + /* Check the IP header length. */
10566 + /* 04-Aug-1998 sw - Really check the IHL? Necessary? */
10568 + if (IpHeaderLength < 5*4) {
10569 + SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_RX,
10570 + ("Rx: Invalid IP Header Length %u.\n", IpHeaderLength));
10571 + pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxErrCts++;
10572 + return (SKCS_STATUS_IP_CSUM_ERROR);
10575 + /* This is an IPv4 frame with a header of valid length. */
10577 + /* Get the IP header and data checksum. */
10579 + IpDataChecksum = Checksum2;
10582 + * The IP header checksum is calculated as follows:
10584 + * IpHeaderChecksum = Checksum1 - Checksum2
10587 + SKCS_OC_SUB(IpHeaderChecksum, Checksum1, Checksum2);
10589 + /* Check if any IP header options. */
10591 + if (IpHeaderLength > SKCS_IP_HEADER_SIZE) {
10593 + /* Get the IP options checksum. */
10595 + IpOptionsChecksum = SkCsCalculateChecksum(
10596 + SKCS_IDX(pIpHeader, SKCS_IP_HEADER_SIZE),
10597 + IpHeaderLength - SKCS_IP_HEADER_SIZE);
10599 + /* Adjust the IP header and IP data checksums. */
10601 + SKCS_OC_ADD(IpHeaderChecksum, IpHeaderChecksum, IpOptionsChecksum);
10603 + SKCS_OC_SUB(IpDataChecksum, IpDataChecksum, IpOptionsChecksum);
10607 + * Check if the IP header checksum is ok.
10609 + * NOTE: We must check the IP header checksum even if the caller just wants
10610 + * us to check upper-layer checksums, because we cannot do any further
10611 + * processing of the packet without a valid IP checksum.
10614 + /* Get the next level protocol identifier. */
10616 + NextLevelProtocol = *(SK_U8 *)
10617 + SKCS_IDX(pIpHeader, SKCS_OFS_IP_NEXT_LEVEL_PROTOCOL);
10619 + if (IpHeaderChecksum != 0xffff) {
10620 + pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxErrCts++;
10621 + /* the NDIS tester wants to know the upper level protocol too */
10622 + if (NextLevelProtocol == SKCS_PROTO_ID_TCP) {
10623 + return(SKCS_STATUS_IP_CSUM_ERROR_TCP);
10625 + else if (NextLevelProtocol == SKCS_PROTO_ID_UDP) {
10626 + return(SKCS_STATUS_IP_CSUM_ERROR_UDP);
10628 + return (SKCS_STATUS_IP_CSUM_ERROR);
10632 + * Check if this is a TCP or UDP frame and if we should calculate the
10633 + * TCP/UDP pseudo header checksum.
10635 + * Also clear all protocol bit flags of protocols not present in the
10639 + if ((pAc->Csum.ReceiveFlags[NetNumber] & SKCS_PROTO_TCP) != 0 &&
10640 + NextLevelProtocol == SKCS_PROTO_ID_TCP) {
10641 + /* TCP/IP frame. */
10642 + NextLevelProtoStats =
10643 + &pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_TCP];
10645 + else if ((pAc->Csum.ReceiveFlags[NetNumber] & SKCS_PROTO_UDP) != 0 &&
10646 + NextLevelProtocol == SKCS_PROTO_ID_UDP) {
10647 + /* UDP/IP frame. */
10648 + NextLevelProtoStats =
10649 + &pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_UDP];
10653 + * Either not a TCP or UDP frame and/or TCP/UDP processing not
10656 + return (SKCS_STATUS_IP_CSUM_OK);
10659 + /* Check if this is an IP fragment. */
10662 + * Note: An IP fragment has a non-zero "Fragment Offset" field and/or
10663 + * the "More Fragments" bit set. Thus, if both the "Fragment Offset"
10664 + * and the "More Fragments" are zero, it is *not* a fragment. We can
10665 + * easily check both at the same time since they are in the same 16-bit
10670 + SKCS_IDX(pIpHeader, SKCS_OFS_IP_FLAGS_AND_FRAGMENT_OFFSET) &
10671 + ~SKCS_IP_DONT_FRAGMENT) != 0) {
10672 + /* IP fragment; ignore all other protocols. */
10673 + NextLevelProtoStats->RxUnableCts++;
10674 + return (SKCS_STATUS_IP_FRAGMENT);
10680 + * From RFC 768 (UDP)
10681 + * If the computed checksum is zero, it is transmitted as all ones (the
10682 + * equivalent in one's complement arithmetic). An all zero transmitted
10683 + * checksum value means that the transmitter generated no checksum (for
10684 + * debugging or for higher level protocols that don't care).
10687 + if (NextLevelProtocol == SKCS_PROTO_ID_UDP &&
10688 + *(SK_U16*)SKCS_IDX(pIpHeader, IpHeaderLength + 6) == 0x0000) {
10690 + NextLevelProtoStats->RxOkCts++;
10692 + return (SKCS_STATUS_IP_CSUM_OK_NO_UDP);
10696 + * Calculate the TCP/UDP checksum.
10699 + /* Get total length of IP header and data. */
10702 + *(SK_U16 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_TOTAL_LENGTH);
10704 + /* Get length of IP data portion. */
10706 + IpDataLength = SKCS_NTOH16(IpDataLength) - IpHeaderLength;
10708 + NextLevelProtocolChecksum =
10710 + /* Calculate the pseudo header checksum. */
10712 + (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
10713 + SKCS_OFS_IP_SOURCE_ADDRESS + 0) +
10714 + (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
10715 + SKCS_OFS_IP_SOURCE_ADDRESS + 2) +
10716 + (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
10717 + SKCS_OFS_IP_DESTINATION_ADDRESS + 0) +
10718 + (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
10719 + SKCS_OFS_IP_DESTINATION_ADDRESS + 2) +
10720 + (unsigned long) SKCS_HTON16(NextLevelProtocol) +
10721 + (unsigned long) SKCS_HTON16(IpDataLength) +
10723 + /* Add the TCP/UDP header checksum. */
10725 + (unsigned long) IpDataChecksum;
10727 + /* Add-in any carries. */
10729 + SKCS_OC_ADD(NextLevelProtocolChecksum, NextLevelProtocolChecksum, 0);
10731 + /* Add-in any new carry. */
10733 + SKCS_OC_ADD(NextLevelProtocolChecksum, NextLevelProtocolChecksum, 0);
10735 + /* Check if the TCP/UDP checksum is ok. */
10737 + if ((unsigned) NextLevelProtocolChecksum == 0xffff) {
10739 + /* TCP/UDP checksum ok. */
10741 + NextLevelProtoStats->RxOkCts++;
10743 + return (NextLevelProtocol == SKCS_PROTO_ID_TCP ?
10744 + SKCS_STATUS_TCP_CSUM_OK : SKCS_STATUS_UDP_CSUM_OK);
10747 + /* TCP/UDP checksum error. */
10749 + NextLevelProtoStats->RxErrCts++;
10751 + return (NextLevelProtocol == SKCS_PROTO_ID_TCP ?
10752 + SKCS_STATUS_TCP_CSUM_ERROR : SKCS_STATUS_UDP_CSUM_ERROR);
10753 +} /* SkCsGetReceiveInfo */
10756 +/******************************************************************************
10758 + * SkCsSetReceiveFlags - set checksum receive flags
10761 + * Use this function to set the various receive flags. According to the
10762 + * protocol flags set by the caller, the start offsets within received
10763 + * packets of the two hardware checksums are returned. These offsets must
10764 + * be stored in all receive descriptors.
10767 + * pAc - Pointer to adapter context struct.
10769 + * ReceiveFlags - Any combination of SK_PROTO_XXX flags of the protocols
10770 + * for which the caller wants checksum information on received frames.
10772 + * pChecksum1Offset - The start offset of the first receive descriptor
10773 + * hardware checksum to be calculated for received frames is returned
10776 + * pChecksum2Offset - The start offset of the second receive descriptor
10777 + * hardware checksum to be calculated for received frames is returned
10781 + * Returns the two hardware checksum start offsets.
10783 +void SkCsSetReceiveFlags(
10784 +SK_AC *pAc, /* Adapter context struct. */
10785 +unsigned ReceiveFlags, /* New receive flags. */
10786 +unsigned *pChecksum1Offset, /* Offset for hardware checksum 1. */
10787 +unsigned *pChecksum2Offset, /* Offset for hardware checksum 2. */
10790 + /* Save the receive flags. */
10792 + pAc->Csum.ReceiveFlags[NetNumber] = ReceiveFlags;
10794 + /* First checksum start offset is the IP header. */
10795 + *pChecksum1Offset = SKCS_MAC_HEADER_SIZE;
10798 + * Second checksum start offset is the IP data. Note that this may vary
10799 + * if there are any IP header options in the actual packet.
10801 + *pChecksum2Offset = SKCS_MAC_HEADER_SIZE + SKCS_IP_HEADER_SIZE;
10802 +} /* SkCsSetReceiveFlags */
10804 +#ifndef SK_CS_CALCULATE_CHECKSUM
10806 +/******************************************************************************
10808 + * SkCsCalculateChecksum - calculate checksum for specified data
10811 + * Calculate and return the 16-bit Internet Checksum for the specified
10815 + * pData - Pointer to data for which the checksum shall be calculated.
10816 + * Note: The pointer should be aligned on a 16-bit boundary.
10818 + * Length - Length in bytes of data to checksum.
10821 + * The 16-bit Internet Checksum for the specified data.
10823 + * Note: The checksum is calculated in the machine's natural byte order,
10824 + * i.e. little vs. big endian. Thus, the resulting checksum is different
10825 + * for the same input data on little and big endian machines.
10827 + * However, when written back to the network packet, the byte order is
10828 + * always in correct network order.
10830 +unsigned SkCsCalculateChecksum(
10831 +void *pData, /* Data to checksum. */
10832 +unsigned Length) /* Length of data. */
10834 + SK_U16 *pU16; /* Pointer to the data as 16-bit words. */
10835 + unsigned long Checksum; /* Checksum; must be at least 32 bits. */
10837 + /* Sum up all 16-bit words. */
10839 + pU16 = (SK_U16 *) pData;
10840 + for (Checksum = 0; Length > 1; Length -= 2) {
10841 + Checksum += *pU16++;
10844 + /* If this is an odd number of bytes, add-in the last byte. */
10846 + if (Length > 0) {
10847 +#ifdef SK_BIG_ENDIAN
10848 + /* Add the last byte as the high byte. */
10849 + Checksum += ((unsigned) *(SK_U8 *) pU16) << 8;
10850 +#else /* !SK_BIG_ENDIAN */
10851 + /* Add the last byte as the low byte. */
10852 + Checksum += *(SK_U8 *) pU16;
10853 +#endif /* !SK_BIG_ENDIAN */
10856 + /* Add-in any carries. */
10858 + SKCS_OC_ADD(Checksum, Checksum, 0);
10860 + /* Add-in any new carry. */
10862 + SKCS_OC_ADD(Checksum, Checksum, 0);
10864 + /* Note: All bits beyond the 16-bit limit are now zero. */
10866 + return ((unsigned) Checksum);
10867 +} /* SkCsCalculateChecksum */
10869 +#endif /* SK_CS_CALCULATE_CHECKSUM */
10871 +/******************************************************************************
10873 + * SkCsEvent - the CSUM event dispatcher
10876 + * This is the event handler for the CSUM module.
10879 + * pAc - Pointer to adapter context.
10881 + * Ioc - I/O context.
10883 + * Event - Event id.
10885 + * Param - Event dependent parameter.
10888 + * The 16-bit Internet Checksum for the specified data.
10890 + * Note: The checksum is calculated in the machine's natural byte order,
10891 + * i.e. little vs. big endian. Thus, the resulting checksum is different
10892 + * for the same input data on little and big endian machines.
10894 + * However, when written back to the network packet, the byte order is
10895 + * always in correct network order.
10898 +SK_AC *pAc, /* Pointer to adapter context. */
10899 +SK_IOC Ioc, /* I/O context. */
10900 +SK_U32 Event, /* Event id. */
10901 +SK_EVPARA Param) /* Event dependent parameter. */
10908 + * Clear protocol statistics.
10910 + * Param - Protocol index, or -1 for all protocols.
10913 + case SK_CSUM_EVENT_CLEAR_PROTO_STATS:
10915 + ProtoIndex = (int)Param.Para32[1];
10916 + NetNumber = (int)Param.Para32[0];
10917 + if (ProtoIndex < 0) { /* Clear for all protocols. */
10918 + if (NetNumber >= 0) {
10919 + SK_MEMSET(&pAc->Csum.ProtoStats[NetNumber][0], 0,
10920 + sizeof(pAc->Csum.ProtoStats[NetNumber]));
10923 + else { /* Clear for individual protocol. */
10924 + SK_MEMSET(&pAc->Csum.ProtoStats[NetNumber][ProtoIndex], 0,
10925 + sizeof(pAc->Csum.ProtoStats[NetNumber][ProtoIndex]));
10931 + return (0); /* Success. */
10934 +#endif /* SK_USE_CSUM */
10935 diff -ruN linux/drivers/net/sk98lin/skdim.c linux-new/drivers/net/sk98lin/skdim.c
10936 --- linux/drivers/net/sk98lin/skdim.c 2006-09-20 05:42:06.000000000 +0200
10937 +++ linux-new/drivers/net/sk98lin/skdim.c 2006-07-28 14:13:56.000000000 +0200
10939 /******************************************************************************
10942 - * Project: GEnesis, PCI Gigabit Ethernet Adapter
10943 - * Version: $Revision$
10945 - * Purpose: All functions to maintain interrupt moderation
10947 + * Project: GEnesis, PCI Gigabit Ethernet Adapter
10948 + * Version: $Revision$
10950 + * Purpose: All functions regardig interrupt moderation
10952 ******************************************************************************/
10954 /******************************************************************************
10956 * (C)Copyright 1998-2002 SysKonnect GmbH.
10957 - * (C)Copyright 2002-2003 Marvell.
10958 + * (C)Copyright 2002-2005 Marvell.
10960 + * Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet
10961 + * Server Adapters.
10963 + * Author: Ralph Roesler (rroesler@syskonnect.de)
10964 + * Mirko Lindner (mlindner@syskonnect.de)
10966 + * Address all question to: linux@syskonnect.de
10968 * This program is free software; you can redistribute it and/or modify
10969 * it under the terms of the GNU General Public License as published by
10970 @@ -20,723 +28,367 @@
10972 * The information in this file is provided "AS IS" without warranty.
10974 - ******************************************************************************/
10975 + *****************************************************************************/
10977 -/******************************************************************************
10981 - * This module is intended to manage the dynamic interrupt moderation on both
10982 - * GEnesis and Yukon adapters.
10984 - * Include File Hierarchy:
10989 - ******************************************************************************/
10992 -static const char SysKonnectFileId[] =
10993 - "@(#) $Id$ (C) SysKonnect.";
10996 -#define __SKADDR_C
10998 -#ifdef __cplusplus
10999 -#error C++ is not yet supported.
11003 -/*******************************************************************************
11007 -*******************************************************************************/
11009 -#ifndef __INC_SKDRV1ST_H
11010 #include "h/skdrv1st.h"
11013 -#ifndef __INC_SKDRV2ND_H
11014 #include "h/skdrv2nd.h"
11017 -#include <linux/kernel_stat.h>
11019 -/*******************************************************************************
11023 -*******************************************************************************/
11025 -/*******************************************************************************
11029 -*******************************************************************************/
11030 +/******************************************************************************
11032 + * Local Function Prototypes
11034 + *****************************************************************************/
11036 -/*******************************************************************************
11038 -** Local function prototypes
11040 -*******************************************************************************/
11042 -static unsigned int GetCurrentSystemLoad(SK_AC *pAC);
11043 -static SK_U64 GetIsrCalls(SK_AC *pAC);
11044 -static SK_BOOL IsIntModEnabled(SK_AC *pAC);
11045 -static void SetCurrIntCtr(SK_AC *pAC);
11046 -static void EnableIntMod(SK_AC *pAC);
11047 -static void DisableIntMod(SK_AC *pAC);
11048 -static void ResizeDimTimerDuration(SK_AC *pAC);
11049 -static void DisplaySelectedModerationType(SK_AC *pAC);
11050 -static void DisplaySelectedModerationMask(SK_AC *pAC);
11051 -static void DisplayDescrRatio(SK_AC *pAC);
11052 +static SK_U64 getIsrCalls(SK_AC *pAC);
11053 +static SK_BOOL isIntModEnabled(SK_AC *pAC);
11054 +static void setCurrIntCtr(SK_AC *pAC);
11055 +static void enableIntMod(SK_AC *pAC);
11056 +static void disableIntMod(SK_AC *pAC);
11058 -/*******************************************************************************
11060 -** Global variables
11062 -*******************************************************************************/
11063 +#define M_DIMINFO pAC->DynIrqModInfo
11065 -/*******************************************************************************
11067 -** Local variables
11069 -*******************************************************************************/
11070 +/******************************************************************************
11072 + * Global Functions
11074 + *****************************************************************************/
11076 -/*******************************************************************************
11078 -** Global functions
11080 -*******************************************************************************/
11081 +/*****************************************************************************
11083 + * SkDimModerate - Moderates the IRQs depending on the current needs
11086 + * Moderation of IRQs depends on the number of occurred IRQs with
11087 + * respect to the previous moderation cycle.
11092 +void SkDimModerate(
11093 +SK_AC *pAC) /* pointer to adapter control context */
11095 + SK_U64 IsrCalls = getIsrCalls(pAC);
11097 + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==> SkDimModerate\n"));
11099 + if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
11100 + if (isIntModEnabled(pAC)) {
11101 + if (IsrCalls < M_DIMINFO.MaxModIntsPerSecLowerLimit) {
11102 + disableIntMod(pAC);
11105 + if (IsrCalls > M_DIMINFO.MaxModIntsPerSecUpperLimit) {
11106 + enableIntMod(pAC);
11110 + setCurrIntCtr(pAC);
11112 -/*******************************************************************************
11113 -** Function : SkDimModerate
11114 -** Description : Called in every ISR to check if moderation is to be applied
11115 -** or not for the current number of interrupts
11116 -** Programmer : Ralph Roesler
11117 -** Last Modified: 22-mar-03
11118 -** Returns : void (!)
11120 -*******************************************************************************/
11123 -SkDimModerate(SK_AC *pAC) {
11124 - unsigned int CurrSysLoad = 0; /* expressed in percent */
11125 - unsigned int LoadIncrease = 0; /* expressed in percent */
11126 - SK_U64 ThresholdInts = 0;
11127 - SK_U64 IsrCallsPerSec = 0;
11128 + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("<== SkDimModerate\n"));
11131 -#define M_DIMINFO pAC->DynIrqModInfo
11132 +/*****************************************************************************
11134 + * SkDimStartModerationTimer - Starts the moderation timer
11137 + * Dynamic interrupt moderation is regularly checked using the
11138 + * so-called moderation timer. This timer is started with this function.
11142 +void SkDimStartModerationTimer(
11143 +SK_AC *pAC) /* pointer to adapter control context */
11145 + SK_EVPARA EventParam; /* Event struct for timer event */
11147 + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11148 + ("==> SkDimStartModerationTimer\n"));
11150 - if (!IsIntModEnabled(pAC)) {
11151 - if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
11152 - CurrSysLoad = GetCurrentSystemLoad(pAC);
11153 - if (CurrSysLoad > 75) {
11155 - ** More than 75% total system load! Enable the moderation
11156 - ** to shield the system against too many interrupts.
11158 - EnableIntMod(pAC);
11159 - } else if (CurrSysLoad > M_DIMINFO.PrevSysLoad) {
11160 - LoadIncrease = (CurrSysLoad - M_DIMINFO.PrevSysLoad);
11161 - if (LoadIncrease > ((M_DIMINFO.PrevSysLoad *
11162 - C_INT_MOD_ENABLE_PERCENTAGE) / 100)) {
11163 - if (CurrSysLoad > 10) {
11165 - ** More than 50% increase with respect to the
11166 - ** previous load of the system. Most likely this
11167 - ** is due to our ISR-proc...
11169 - EnableIntMod(pAC);
11174 - ** Neither too much system load at all nor too much increase
11175 - ** with respect to the previous system load. Hence, we can leave
11176 - ** the ISR-handling like it is without enabling moderation.
11179 - M_DIMINFO.PrevSysLoad = CurrSysLoad;
11182 - if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
11183 - ThresholdInts = ((M_DIMINFO.MaxModIntsPerSec *
11184 - C_INT_MOD_DISABLE_PERCENTAGE) / 100);
11185 - IsrCallsPerSec = GetIsrCalls(pAC);
11186 - if (IsrCallsPerSec <= ThresholdInts) {
11188 - ** The number of interrupts within the last second is
11189 - ** lower than the disable_percentage of the desried
11190 - ** maxrate. Therefore we can disable the moderation.
11192 - DisableIntMod(pAC);
11193 - M_DIMINFO.MaxModIntsPerSec =
11194 - (M_DIMINFO.MaxModIntsPerSecUpperLimit +
11195 - M_DIMINFO.MaxModIntsPerSecLowerLimit) / 2;
11198 - ** The number of interrupts per sec is the same as expected.
11199 - ** Evalulate the descriptor-ratio. If it has changed, a resize
11200 - ** in the moderation timer might be useful
11202 - if (M_DIMINFO.AutoSizing) {
11203 - ResizeDimTimerDuration(pAC);
11210 - ** Some information to the log...
11212 - if (M_DIMINFO.DisplayStats) {
11213 - DisplaySelectedModerationType(pAC);
11214 - DisplaySelectedModerationMask(pAC);
11215 - DisplayDescrRatio(pAC);
11217 + if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
11218 + SK_MEMSET((char *) &EventParam, 0, sizeof(EventParam));
11219 + EventParam.Para32[0] = SK_DRV_MODERATION_TIMER;
11220 + SkTimerStart(pAC, pAC->IoBase,
11221 + &pAC->DynIrqModInfo.ModTimer,
11222 + pAC->DynIrqModInfo.DynIrqModSampleInterval * 1000000,
11223 + SKGE_DRV, SK_DRV_TIMER, EventParam);
11226 - M_DIMINFO.NbrProcessedDescr = 0;
11227 - SetCurrIntCtr(pAC);
11228 + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11229 + ("<== SkDimStartModerationTimer\n"));
11232 -/*******************************************************************************
11233 -** Function : SkDimStartModerationTimer
11234 -** Description : Starts the audit-timer for the dynamic interrupt moderation
11235 -** Programmer : Ralph Roesler
11236 -** Last Modified: 22-mar-03
11237 -** Returns : void (!)
11239 -*******************************************************************************/
11242 -SkDimStartModerationTimer(SK_AC *pAC) {
11243 - SK_EVPARA EventParam; /* Event struct for timer event */
11245 - SK_MEMSET((char *) &EventParam, 0, sizeof(EventParam));
11246 - EventParam.Para32[0] = SK_DRV_MODERATION_TIMER;
11247 - SkTimerStart(pAC, pAC->IoBase, &pAC->DynIrqModInfo.ModTimer,
11248 - SK_DRV_MODERATION_TIMER_LENGTH,
11249 - SKGE_DRV, SK_DRV_TIMER, EventParam);
11251 +/*****************************************************************************
11253 + * SkDimEnableModerationIfNeeded - Enables or disables any moderationtype
11256 + * This function effectively initializes the IRQ moderation of a network
11257 + * adapter. Depending on the configuration, this might be either static
11258 + * or dynamic. If no moderation is configured, this function will do
11263 +void SkDimEnableModerationIfNeeded(
11264 +SK_AC *pAC) /* pointer to adapter control context */
11266 + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11267 + ("==> SkDimEnableModerationIfNeeded\n"));
11269 + if (M_DIMINFO.IntModTypeSelect != C_INT_MOD_NONE) {
11270 + if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_STATIC) {
11271 + enableIntMod(pAC);
11272 + } else { /* must be C_INT_MOD_DYNAMIC */
11273 + SkDimStartModerationTimer(pAC);
11277 -/*******************************************************************************
11278 -** Function : SkDimEnableModerationIfNeeded
11279 -** Description : Either enables or disables moderation
11280 -** Programmer : Ralph Roesler
11281 -** Last Modified: 22-mar-03
11282 -** Returns : void (!)
11283 -** Notes : This function is called when a particular adapter is opened
11284 -** There is no Disable function, because when all interrupts
11285 -** might be disable, the moderation timer has no meaning at all
11286 -******************************************************************************/
11289 -SkDimEnableModerationIfNeeded(SK_AC *pAC) {
11291 - if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_STATIC) {
11292 - EnableIntMod(pAC); /* notification print in this function */
11293 - } else if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
11294 - SkDimStartModerationTimer(pAC);
11295 - if (M_DIMINFO.DisplayStats) {
11296 - printk("Dynamic moderation has been enabled\n");
11299 - if (M_DIMINFO.DisplayStats) {
11300 - printk("No moderation has been enabled\n");
11303 + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11304 + ("<== SkDimEnableModerationIfNeeded\n"));
11307 -/*******************************************************************************
11308 -** Function : SkDimDisplayModerationSettings
11309 -** Description : Displays the current settings regaring interrupt moderation
11310 -** Programmer : Ralph Roesler
11311 -** Last Modified: 22-mar-03
11312 -** Returns : void (!)
11314 -*******************************************************************************/
11317 -SkDimDisplayModerationSettings(SK_AC *pAC) {
11318 - DisplaySelectedModerationType(pAC);
11319 - DisplaySelectedModerationMask(pAC);
11321 +/*****************************************************************************
11323 + * SkDimDisableModeration - disables moderation if it is enabled
11326 + * Disabling of the moderation requires that is enabled already.
11330 +void SkDimDisableModeration(
11331 +SK_AC *pAC, /* pointer to adapter control context */
11332 +int CurrentModeration) /* type of current moderation */
11334 + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11335 + ("==> SkDimDisableModeration\n"));
11337 + if (M_DIMINFO.IntModTypeSelect != C_INT_MOD_NONE) {
11338 + if (CurrentModeration == C_INT_MOD_STATIC) {
11339 + disableIntMod(pAC);
11340 + } else { /* must be C_INT_MOD_DYNAMIC */
11341 + SkTimerStop(pAC, pAC->IoBase, &M_DIMINFO.ModTimer);
11342 + disableIntMod(pAC);
11346 -/*******************************************************************************
11348 -** Local functions
11350 -*******************************************************************************/
11351 + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11352 + ("<== SkDimDisableModeration\n"));
11355 -/*******************************************************************************
11356 -** Function : GetCurrentSystemLoad
11357 -** Description : Retrieves the current system load of the system. This load
11358 -** is evaluated for all processors within the system.
11359 -** Programmer : Ralph Roesler
11360 -** Last Modified: 22-mar-03
11361 -** Returns : unsigned int: load expressed in percentage
11362 -** Notes : The possible range being returned is from 0 up to 100.
11363 -** Whereas 0 means 'no load at all' and 100 'system fully loaded'
11364 -** It is impossible to determine what actually causes the system
11365 -** to be in 100%, but maybe that is due to too much interrupts.
11366 -*******************************************************************************/
11368 -static unsigned int
11369 -GetCurrentSystemLoad(SK_AC *pAC) {
11370 - unsigned long jif = jiffies;
11371 - unsigned int UserTime = 0;
11372 - unsigned int SystemTime = 0;
11373 - unsigned int NiceTime = 0;
11374 - unsigned int IdleTime = 0;
11375 - unsigned int TotalTime = 0;
11376 - unsigned int UsedTime = 0;
11377 - unsigned int SystemLoad = 0;
11378 +/******************************************************************************
11380 + * Local Functions
11382 + *****************************************************************************/
11384 - /* unsigned int NbrCpu = 0; */
11385 +/*****************************************************************************
11387 + * getIsrCalls - evaluate the number of IRQs handled in mod interval
11390 + * Depending on the selected moderation mask, this function will return
11391 + * the number of interrupts handled in the previous moderation interval.
11392 + * This evaluated number is based on the current number of interrupts
11393 + * stored in PNMI-context and the previous stored interrupts.
11396 + * the number of IRQs handled
11398 +static SK_U64 getIsrCalls(
11399 +SK_AC *pAC) /* pointer to adapter control context */
11401 + SK_U64 RxPort0IntDiff = 0, RxPort1IntDiff = 0;
11402 + SK_U64 TxPort0IntDiff = 0, TxPort1IntDiff = 0;
11403 + SK_U64 StatusPort0IntDiff = 0, StatusPort1IntDiff = 0;
11405 + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==>getIsrCalls\n"));
11407 + if (!CHIP_ID_YUKON_2(pAC)) {
11408 + if ((M_DIMINFO.MaskIrqModeration == IRQ_MASK_TX_ONLY) ||
11409 + (M_DIMINFO.MaskIrqModeration == IRQ_MASK_SP_TX)) {
11410 + if (pAC->GIni.GIMacsFound == 2) {
11412 + pAC->Pnmi.Port[1].TxIntrCts -
11413 + M_DIMINFO.PrevPort1TxIntrCts;
11415 + TxPort0IntDiff = pAC->Pnmi.Port[0].TxIntrCts -
11416 + M_DIMINFO.PrevPort0TxIntrCts;
11417 + } else if ((M_DIMINFO.MaskIrqModeration == IRQ_MASK_RX_ONLY) ||
11418 + (M_DIMINFO.MaskIrqModeration == IRQ_MASK_SP_RX)) {
11419 + if (pAC->GIni.GIMacsFound == 2) {
11421 + pAC->Pnmi.Port[1].RxIntrCts -
11422 + M_DIMINFO.PrevPort1RxIntrCts;
11424 + RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts -
11425 + M_DIMINFO.PrevPort0RxIntrCts;
11427 + if (pAC->GIni.GIMacsFound == 2) {
11429 + pAC->Pnmi.Port[1].RxIntrCts -
11430 + M_DIMINFO.PrevPort1RxIntrCts;
11432 + pAC->Pnmi.Port[1].TxIntrCts -
11433 + M_DIMINFO.PrevPort1TxIntrCts;
11435 + RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts -
11436 + M_DIMINFO.PrevPort0RxIntrCts;
11437 + TxPort0IntDiff = pAC->Pnmi.Port[0].TxIntrCts -
11438 + M_DIMINFO.PrevPort0TxIntrCts;
11440 + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11441 + ("==>getIsrCalls (!CHIP_ID_YUKON_2)\n"));
11442 + return (RxPort0IntDiff + RxPort1IntDiff +
11443 + TxPort0IntDiff + TxPort1IntDiff);
11447 - ** The following lines have been commented out, because
11448 - ** from kernel 2.5.44 onwards, the kernel-owned structure
11450 - ** struct kernel_stat kstat
11452 - ** is not marked as an exported symbol in the file
11453 + ** We have a Yukon2 compliant chipset if we come up to here
11455 - ** kernel/ksyms.c
11457 - ** As a consequence, using this driver as KLM is not possible
11458 - ** and any access of the structure kernel_stat via the
11459 - ** dedicated macros kstat_cpu(i).cpustat.xxx is to be avoided.
11461 - ** The kstat-information might be added again in future
11462 - ** versions of the 2.5.xx kernel, but for the time being,
11463 - ** number of interrupts will serve as indication how much
11464 - ** load we currently have...
11466 - ** for (NbrCpu = 0; NbrCpu < num_online_cpus(); NbrCpu++) {
11467 - ** UserTime = UserTime + kstat_cpu(NbrCpu).cpustat.user;
11468 - ** NiceTime = NiceTime + kstat_cpu(NbrCpu).cpustat.nice;
11469 - ** SystemTime = SystemTime + kstat_cpu(NbrCpu).cpustat.system;
11471 + if (pAC->GIni.GIMacsFound == 2) {
11472 + StatusPort1IntDiff = pAC->Pnmi.Port[1].StatusLeIntrCts -
11473 + M_DIMINFO.PrevPort1StatusIntrCts;
11475 + StatusPort0IntDiff = pAC->Pnmi.Port[0].StatusLeIntrCts -
11476 + M_DIMINFO.PrevPort0StatusIntrCts;
11478 - SK_U64 ThresholdInts = 0;
11479 - SK_U64 IsrCallsPerSec = 0;
11481 - ThresholdInts = ((M_DIMINFO.MaxModIntsPerSec *
11482 - C_INT_MOD_ENABLE_PERCENTAGE) + 100);
11483 - IsrCallsPerSec = GetIsrCalls(pAC);
11484 - if (IsrCallsPerSec >= ThresholdInts) {
11486 - ** We do not know how much the real CPU-load is!
11487 - ** Return 80% as a default in order to activate DIM
11490 - return (SystemLoad);
11493 - UsedTime = UserTime + NiceTime + SystemTime;
11495 - IdleTime = jif * num_online_cpus() - UsedTime;
11496 - TotalTime = UsedTime + IdleTime;
11498 - SystemLoad = ( 100 * (UsedTime - M_DIMINFO.PrevUsedTime) ) /
11499 - (TotalTime - M_DIMINFO.PrevTotalTime);
11500 + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11501 + ("==>getIsrCalls (CHIP_ID_YUKON_2)\n"));
11502 + return (StatusPort0IntDiff + StatusPort1IntDiff);
11505 - if (M_DIMINFO.DisplayStats) {
11506 - printk("Current system load is: %u\n", SystemLoad);
11507 +/*****************************************************************************
11509 + * setCurrIntCtr - stores the current number of interrupts
11512 + * Stores the current number of occurred interrupts in the adapter
11513 + * context. This is needed to evaluate the umber of interrupts within
11514 + * the moderation interval.
11519 +static void setCurrIntCtr(
11520 +SK_AC *pAC) /* pointer to adapter control context */
11522 + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==>setCurrIntCtr\n"));
11524 + if (!CHIP_ID_YUKON_2(pAC)) {
11525 + if (pAC->GIni.GIMacsFound == 2) {
11526 + M_DIMINFO.PrevPort1RxIntrCts = pAC->Pnmi.Port[1].RxIntrCts;
11527 + M_DIMINFO.PrevPort1TxIntrCts = pAC->Pnmi.Port[1].TxIntrCts;
11529 + M_DIMINFO.PrevPort0RxIntrCts = pAC->Pnmi.Port[0].RxIntrCts;
11530 + M_DIMINFO.PrevPort0TxIntrCts = pAC->Pnmi.Port[0].TxIntrCts;
11531 + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11532 + ("<== setCurrIntCtr (!CHIP_ID_YUKON_2)\n"));
11536 - M_DIMINFO.PrevTotalTime = TotalTime;
11537 - M_DIMINFO.PrevUsedTime = UsedTime;
11539 - return (SystemLoad);
11541 + ** We have a Yukon2 compliant chipset if we come up to here
11543 + if (pAC->GIni.GIMacsFound == 2) {
11544 + M_DIMINFO.PrevPort1StatusIntrCts = pAC->Pnmi.Port[1].StatusLeIntrCts;
11546 + M_DIMINFO.PrevPort0StatusIntrCts = pAC->Pnmi.Port[0].StatusLeIntrCts;
11548 + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11549 + ("<== setCurrIntCtr (CHIP_ID_YUKON_2)\n"));
11552 -/*******************************************************************************
11553 -** Function : GetIsrCalls
11554 -** Description : Depending on the selected moderation mask, this function will
11555 -** return the number of interrupts handled in the previous time-
11556 -** frame. This evaluated number is based on the current number
11557 -** of interrupts stored in PNMI-context and the previous stored
11559 -** Programmer : Ralph Roesler
11560 -** Last Modified: 23-mar-03
11561 -** Returns : int: the number of interrupts being executed in the last
11563 -** Notes : It makes only sense to call this function, when dynamic
11564 -** interrupt moderation is applied
11565 -*******************************************************************************/
11568 -GetIsrCalls(SK_AC *pAC) {
11569 - SK_U64 RxPort0IntDiff = 0;
11570 - SK_U64 RxPort1IntDiff = 0;
11571 - SK_U64 TxPort0IntDiff = 0;
11572 - SK_U64 TxPort1IntDiff = 0;
11574 - if (pAC->DynIrqModInfo.MaskIrqModeration == IRQ_MASK_TX_ONLY) {
11575 - if (pAC->GIni.GIMacsFound == 2) {
11576 - TxPort1IntDiff = pAC->Pnmi.Port[1].TxIntrCts -
11577 - pAC->DynIrqModInfo.PrevPort1TxIntrCts;
11579 - TxPort0IntDiff = pAC->Pnmi.Port[0].TxIntrCts -
11580 - pAC->DynIrqModInfo.PrevPort0TxIntrCts;
11581 - } else if (pAC->DynIrqModInfo.MaskIrqModeration == IRQ_MASK_RX_ONLY) {
11582 - if (pAC->GIni.GIMacsFound == 2) {
11583 - RxPort1IntDiff = pAC->Pnmi.Port[1].RxIntrCts -
11584 - pAC->DynIrqModInfo.PrevPort1RxIntrCts;
11586 - RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts -
11587 - pAC->DynIrqModInfo.PrevPort0RxIntrCts;
11589 - if (pAC->GIni.GIMacsFound == 2) {
11590 - RxPort1IntDiff = pAC->Pnmi.Port[1].RxIntrCts -
11591 - pAC->DynIrqModInfo.PrevPort1RxIntrCts;
11592 - TxPort1IntDiff = pAC->Pnmi.Port[1].TxIntrCts -
11593 - pAC->DynIrqModInfo.PrevPort1TxIntrCts;
11595 - RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts -
11596 - pAC->DynIrqModInfo.PrevPort0RxIntrCts;
11597 - TxPort0IntDiff = pAC->Pnmi.Port[0].TxIntrCts -
11598 - pAC->DynIrqModInfo.PrevPort0TxIntrCts;
11601 - return (RxPort0IntDiff + RxPort1IntDiff + TxPort0IntDiff + TxPort1IntDiff);
11602 +/*****************************************************************************
11604 + * isIntModEnabled - returns the current state of interrupt moderation
11607 + * This function retrieves the current value of the interrupt moderation
11608 + * command register. Its content determines whether any moderation is
11609 + * running or not.
11612 + * SK_TRUE : IRQ moderation is currently active
11613 + * SK_FALSE: No IRQ moderation is active
11615 +static SK_BOOL isIntModEnabled(
11616 +SK_AC *pAC) /* pointer to adapter control context */
11618 + unsigned long CtrCmd;
11620 + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==>isIntModEnabled\n"));
11622 + SK_IN32(pAC->IoBase, B2_IRQM_CTRL, &CtrCmd);
11623 + if ((CtrCmd & TIM_START) == TIM_START) {
11624 + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11625 + ("<== isIntModEnabled (SK_TRUE)\n"));
11628 + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11629 + ("<== isIntModEnabled (SK_FALSE)\n"));
11633 -/*******************************************************************************
11634 -** Function : GetRxCalls
11635 -** Description : This function will return the number of times a receive inter-
11636 -** rupt was processed. This is needed to evaluate any resizing
11638 -** Programmer : Ralph Roesler
11639 -** Last Modified: 23-mar-03
11640 -** Returns : SK_U64: the number of RX-ints being processed
11641 -** Notes : It makes only sense to call this function, when dynamic
11642 -** interrupt moderation is applied
11643 -*******************************************************************************/
11646 -GetRxCalls(SK_AC *pAC) {
11647 - SK_U64 RxPort0IntDiff = 0;
11648 - SK_U64 RxPort1IntDiff = 0;
11650 - if (pAC->GIni.GIMacsFound == 2) {
11651 - RxPort1IntDiff = pAC->Pnmi.Port[1].RxIntrCts -
11652 - pAC->DynIrqModInfo.PrevPort1RxIntrCts;
11654 - RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts -
11655 - pAC->DynIrqModInfo.PrevPort0RxIntrCts;
11657 - return (RxPort0IntDiff + RxPort1IntDiff);
11659 +/*****************************************************************************
11661 + * enableIntMod - enables the interrupt moderation
11664 + * Enabling the interrupt moderation is done by putting the desired
11665 + * moderation interval in the B2_IRQM_INI register, specifying the
11666 + * desired maks in the B2_IRQM_MSK register and finally starting the
11667 + * IRQ moderation timer using the B2_IRQM_CTRL register.
11672 +static void enableIntMod(
11673 +SK_AC *pAC) /* pointer to adapter control context */
11675 + unsigned long ModBase;
11677 + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==> enableIntMod\n"));
11679 + if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
11680 + ModBase = C_CLK_FREQ_GENESIS / M_DIMINFO.MaxModIntsPerSec;
11681 + } else if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) {
11682 + ModBase = C_CLK_FREQ_YUKON_EC / M_DIMINFO.MaxModIntsPerSec;
11684 + ModBase = C_CLK_FREQ_YUKON / M_DIMINFO.MaxModIntsPerSec;
11687 -/*******************************************************************************
11688 -** Function : SetCurrIntCtr
11689 -** Description : Will store the current number orf occured interrupts in the
11690 -** adapter context. This is needed to evaluated the number of
11691 -** interrupts within a current timeframe.
11692 -** Programmer : Ralph Roesler
11693 -** Last Modified: 23-mar-03
11694 -** Returns : void (!)
11696 -*******************************************************************************/
11699 -SetCurrIntCtr(SK_AC *pAC) {
11700 - if (pAC->GIni.GIMacsFound == 2) {
11701 - pAC->DynIrqModInfo.PrevPort1RxIntrCts = pAC->Pnmi.Port[1].RxIntrCts;
11702 - pAC->DynIrqModInfo.PrevPort1TxIntrCts = pAC->Pnmi.Port[1].TxIntrCts;
11704 - pAC->DynIrqModInfo.PrevPort0RxIntrCts = pAC->Pnmi.Port[0].RxIntrCts;
11705 - pAC->DynIrqModInfo.PrevPort0TxIntrCts = pAC->Pnmi.Port[0].TxIntrCts;
11707 + SK_OUT32(pAC->IoBase, B2_IRQM_INI, ModBase);
11708 + SK_OUT32(pAC->IoBase, B2_IRQM_MSK, M_DIMINFO.MaskIrqModeration);
11709 + SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_START);
11711 -/*******************************************************************************
11712 -** Function : IsIntModEnabled()
11713 -** Description : Retrieves the current value of the interrupts moderation
11714 -** command register. Its content determines whether any
11715 -** moderation is running or not.
11716 -** Programmer : Ralph Roesler
11717 -** Last Modified: 23-mar-03
11718 -** Returns : SK_TRUE : if mod timer running
11719 -** SK_FALSE : if no moderation is being performed
11721 -*******************************************************************************/
11724 -IsIntModEnabled(SK_AC *pAC) {
11725 - unsigned long CtrCmd;
11727 - SK_IN32(pAC->IoBase, B2_IRQM_CTRL, &CtrCmd);
11728 - if ((CtrCmd & TIM_START) == TIM_START) {
11733 + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("<== enableIntMod\n"));
11736 -/*******************************************************************************
11737 -** Function : EnableIntMod()
11738 -** Description : Enables the interrupt moderation using the values stored in
11739 -** in the pAC->DynIntMod data structure
11740 -** Programmer : Ralph Roesler
11741 -** Last Modified: 22-mar-03
11744 -*******************************************************************************/
11747 -EnableIntMod(SK_AC *pAC) {
11748 - unsigned long ModBase;
11750 - if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
11751 - ModBase = C_CLK_FREQ_GENESIS / pAC->DynIrqModInfo.MaxModIntsPerSec;
11753 - ModBase = C_CLK_FREQ_YUKON / pAC->DynIrqModInfo.MaxModIntsPerSec;
11756 - SK_OUT32(pAC->IoBase, B2_IRQM_INI, ModBase);
11757 - SK_OUT32(pAC->IoBase, B2_IRQM_MSK, pAC->DynIrqModInfo.MaskIrqModeration);
11758 - SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_START);
11759 - if (M_DIMINFO.DisplayStats) {
11760 - printk("Enabled interrupt moderation (%i ints/sec)\n",
11761 - M_DIMINFO.MaxModIntsPerSec);
11764 +/*****************************************************************************
11766 + * disableIntMod - disables the interrupt moderation
11769 + * Disabling the interrupt moderation is done by stopping the
11770 + * IRQ moderation timer using the B2_IRQM_CTRL register.
11775 +static void disableIntMod(
11776 +SK_AC *pAC) /* pointer to adapter control context */
11778 + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==> disableIntMod\n"));
11780 -/*******************************************************************************
11781 -** Function : DisableIntMod()
11782 -** Description : Disbles the interrupt moderation independent of what inter-
11783 -** rupts are running or not
11784 -** Programmer : Ralph Roesler
11785 -** Last Modified: 23-mar-03
11788 -*******************************************************************************/
11791 -DisableIntMod(SK_AC *pAC) {
11793 - SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_STOP);
11794 - if (M_DIMINFO.DisplayStats) {
11795 - printk("Disabled interrupt moderation\n");
11798 + SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_STOP);
11800 -/*******************************************************************************
11801 -** Function : ResizeDimTimerDuration();
11802 -** Description : Checks the current used descriptor ratio and resizes the
11803 -** duration timer (longer/smaller) if possible.
11804 -** Programmer : Ralph Roesler
11805 -** Last Modified: 23-mar-03
11807 -** Notes : There are both maximum and minimum timer duration value.
11808 -** This function assumes that interrupt moderation is already
11810 -*******************************************************************************/
11813 -ResizeDimTimerDuration(SK_AC *pAC) {
11814 - SK_BOOL IncreaseTimerDuration;
11815 - int TotalMaxNbrDescr;
11816 - int UsedDescrRatio;
11817 - int RatioDiffAbs;
11818 - int RatioDiffRel;
11819 - int NewMaxModIntsPerSec;
11824 - ** Check first if we are allowed to perform any modification
11826 - if (IsIntModEnabled(pAC)) {
11827 - if (M_DIMINFO.IntModTypeSelect != C_INT_MOD_DYNAMIC) {
11830 - if (M_DIMINFO.ModJustEnabled) {
11831 - M_DIMINFO.ModJustEnabled = SK_FALSE;
11838 - ** If we got until here, we have to evaluate the amount of the
11839 - ** descriptor ratio change...
11841 - TotalMaxNbrDescr = pAC->RxDescrPerRing * GetRxCalls(pAC);
11842 - UsedDescrRatio = (M_DIMINFO.NbrProcessedDescr * 100) / TotalMaxNbrDescr;
11844 - if (UsedDescrRatio > M_DIMINFO.PrevUsedDescrRatio) {
11845 - RatioDiffAbs = (UsedDescrRatio - M_DIMINFO.PrevUsedDescrRatio);
11846 - RatioDiffRel = (RatioDiffAbs * 100) / UsedDescrRatio;
11847 - M_DIMINFO.PrevUsedDescrRatio = UsedDescrRatio;
11848 - IncreaseTimerDuration = SK_FALSE; /* in other words: DECREASE */
11849 - } else if (UsedDescrRatio < M_DIMINFO.PrevUsedDescrRatio) {
11850 - RatioDiffAbs = (M_DIMINFO.PrevUsedDescrRatio - UsedDescrRatio);
11851 - RatioDiffRel = (RatioDiffAbs * 100) / M_DIMINFO.PrevUsedDescrRatio;
11852 - M_DIMINFO.PrevUsedDescrRatio = UsedDescrRatio;
11853 - IncreaseTimerDuration = SK_TRUE; /* in other words: INCREASE */
11855 - RatioDiffAbs = (M_DIMINFO.PrevUsedDescrRatio - UsedDescrRatio);
11856 - RatioDiffRel = (RatioDiffAbs * 100) / M_DIMINFO.PrevUsedDescrRatio;
11857 - M_DIMINFO.PrevUsedDescrRatio = UsedDescrRatio;
11858 - IncreaseTimerDuration = SK_TRUE; /* in other words: INCREASE */
11862 - ** Now we can determine the change in percent
11864 - if ((RatioDiffRel >= 0) && (RatioDiffRel <= 5) ) {
11865 - ModAdjValue = 1; /* 1% change - maybe some other value in future */
11866 - } else if ((RatioDiffRel > 5) && (RatioDiffRel <= 10) ) {
11867 - ModAdjValue = 1; /* 1% change - maybe some other value in future */
11868 - } else if ((RatioDiffRel > 10) && (RatioDiffRel <= 15) ) {
11869 - ModAdjValue = 1; /* 1% change - maybe some other value in future */
11871 - ModAdjValue = 1; /* 1% change - maybe some other value in future */
11874 - if (IncreaseTimerDuration) {
11875 - NewMaxModIntsPerSec = M_DIMINFO.MaxModIntsPerSec +
11876 - (M_DIMINFO.MaxModIntsPerSec * ModAdjValue) / 100;
11878 - NewMaxModIntsPerSec = M_DIMINFO.MaxModIntsPerSec -
11879 - (M_DIMINFO.MaxModIntsPerSec * ModAdjValue) / 100;
11883 - ** Check if we exceed boundaries...
11885 - if ( (NewMaxModIntsPerSec > M_DIMINFO.MaxModIntsPerSecUpperLimit) ||
11886 - (NewMaxModIntsPerSec < M_DIMINFO.MaxModIntsPerSecLowerLimit)) {
11887 - if (M_DIMINFO.DisplayStats) {
11888 - printk("Cannot change ModTim from %i to %i ints/sec\n",
11889 - M_DIMINFO.MaxModIntsPerSec, NewMaxModIntsPerSec);
11893 - if (M_DIMINFO.DisplayStats) {
11894 - printk("Resized ModTim from %i to %i ints/sec\n",
11895 - M_DIMINFO.MaxModIntsPerSec, NewMaxModIntsPerSec);
11899 - M_DIMINFO.MaxModIntsPerSec = NewMaxModIntsPerSec;
11901 - if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
11902 - ModBase = C_CLK_FREQ_GENESIS / pAC->DynIrqModInfo.MaxModIntsPerSec;
11904 - ModBase = C_CLK_FREQ_YUKON / pAC->DynIrqModInfo.MaxModIntsPerSec;
11908 - ** We do not need to touch any other registers
11910 - SK_OUT32(pAC->IoBase, B2_IRQM_INI, ModBase);
11911 + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("<== disableIntMod\n"));
11914 /*******************************************************************************
11915 -** Function : DisplaySelectedModerationType()
11916 -** Description : Displays what type of moderation we have
11917 -** Programmer : Ralph Roesler
11918 -** Last Modified: 23-mar-03
11919 -** Returns : void!
11921 -*******************************************************************************/
11924 -DisplaySelectedModerationType(SK_AC *pAC) {
11926 - if (pAC->DynIrqModInfo.DisplayStats) {
11927 - if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_STATIC) {
11928 - printk("Static int moderation runs with %i INTS/sec\n",
11929 - pAC->DynIrqModInfo.MaxModIntsPerSec);
11930 - } else if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
11931 - if (IsIntModEnabled(pAC)) {
11932 - printk("Dynamic int moderation runs with %i INTS/sec\n",
11933 - pAC->DynIrqModInfo.MaxModIntsPerSec);
11935 - printk("Dynamic int moderation currently not applied\n");
11938 - printk("No interrupt moderation selected!\n");
11943 -/*******************************************************************************
11944 -** Function : DisplaySelectedModerationMask()
11945 -** Description : Displays what interrupts are moderated
11946 -** Programmer : Ralph Roesler
11947 -** Last Modified: 23-mar-03
11948 -** Returns : void!
11950 -*******************************************************************************/
11953 -DisplaySelectedModerationMask(SK_AC *pAC) {
11955 - if (pAC->DynIrqModInfo.DisplayStats) {
11956 - if (pAC->DynIrqModInfo.IntModTypeSelect != C_INT_MOD_NONE) {
11957 - switch (pAC->DynIrqModInfo.MaskIrqModeration) {
11958 - case IRQ_MASK_TX_ONLY:
11959 - printk("Only Tx-interrupts are moderated\n");
11961 - case IRQ_MASK_RX_ONLY:
11962 - printk("Only Rx-interrupts are moderated\n");
11964 - case IRQ_MASK_SP_ONLY:
11965 - printk("Only special-interrupts are moderated\n");
11967 - case IRQ_MASK_TX_RX:
11968 - printk("Tx- and Rx-interrupts are moderated\n");
11970 - case IRQ_MASK_SP_RX:
11971 - printk("Special- and Rx-interrupts are moderated\n");
11973 - case IRQ_MASK_SP_TX:
11974 - printk("Special- and Tx-interrupts are moderated\n");
11976 - case IRQ_MASK_RX_TX_SP:
11977 - printk("All Rx-, Tx and special-interrupts are moderated\n");
11980 - printk("Don't know what is moderated\n");
11984 - printk("No specific interrupts masked for moderation\n");
11989 -/*******************************************************************************
11990 -** Function : DisplayDescrRatio
11991 -** Description : Like the name states...
11992 -** Programmer : Ralph Roesler
11993 -** Last Modified: 23-mar-03
11994 -** Returns : void!
11996 -*******************************************************************************/
11999 -DisplayDescrRatio(SK_AC *pAC) {
12000 - int TotalMaxNbrDescr = 0;
12002 - if (pAC->DynIrqModInfo.DisplayStats) {
12003 - TotalMaxNbrDescr = pAC->RxDescrPerRing * GetRxCalls(pAC);
12004 - printk("Ratio descriptors: %i/%i\n",
12005 - M_DIMINFO.NbrProcessedDescr, TotalMaxNbrDescr);
12009 -/*******************************************************************************
12013 -*******************************************************************************/
12017 + ******************************************************************************/
12018 diff -ruN linux/drivers/net/sk98lin/skethtool.c linux-new/drivers/net/sk98lin/skethtool.c
12019 --- linux/drivers/net/sk98lin/skethtool.c 2006-09-20 05:42:06.000000000 +0200
12020 +++ linux-new/drivers/net/sk98lin/skethtool.c 2006-07-28 14:13:56.000000000 +0200
12023 * Name: skethtool.c
12024 * Project: GEnesis, PCI Gigabit Ethernet Adapter
12025 - * Version: $Revision$
12027 + * Version: $Revision$
12029 * Purpose: All functions regarding ethtool handling
12031 ******************************************************************************/
12033 /******************************************************************************
12035 * (C)Copyright 1998-2002 SysKonnect GmbH.
12036 - * (C)Copyright 2002-2004 Marvell.
12037 + * (C)Copyright 2002-2005 Marvell.
12039 * Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet
12043 * Address all question to: linux@syskonnect.de
12045 - * The technical manual for the adapters is available from SysKonnect's
12046 - * web pages: www.syskonnect.com
12048 * This program is free software; you can redistribute it and/or modify
12049 * it under the terms of the GNU General Public License as published by
12050 * the Free Software Foundation; either version 2 of the License, or
12051 @@ -36,10 +33,18 @@
12052 #include "h/skdrv1st.h"
12053 #include "h/skdrv2nd.h"
12054 #include "h/skversion.h"
12056 #include <linux/ethtool.h>
12057 +#include <linux/module.h>
12058 #include <linux/timer.h>
12059 -#include <linux/delay.h>
12061 +/******************************************************************************
12063 + * External Functions and Data
12065 + *****************************************************************************/
12067 +extern void SkDimDisableModeration(SK_AC *pAC, int CurrentModeration);
12068 +extern void SkDimEnableModerationIfNeeded(SK_AC *pAC);
12070 /******************************************************************************
12074 *****************************************************************************/
12076 +#ifndef ETHT_STATSTRING_LEN
12077 +#define ETHT_STATSTRING_LEN 32
12080 +#define SK98LIN_STAT(m) sizeof(((SK_AC *)0)->m),offsetof(SK_AC, m)
12082 #define SUPP_COPPER_ALL (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
12083 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
12084 SUPPORTED_1000baseT_Half| SUPPORTED_1000baseT_Full| \
12085 @@ -65,6 +76,454 @@
12086 ADVERTISED_FIBRE | \
12087 ADVERTISED_Autoneg)
12089 +/******************************************************************************
12091 + * Local Function Prototypes
12093 + *****************************************************************************/
12095 +#ifdef ETHTOOL_GSET
12096 +static void getSettings(SK_AC *pAC, int port, struct ethtool_cmd *ecmd);
12098 +#ifdef ETHTOOL_SSET
12099 +static int setSettings(SK_AC *pAC, int port, struct ethtool_cmd *ecmd);
12101 +#ifdef ETHTOOL_GPAUSEPARAM
12102 +static void getPauseParams(SK_AC *pAC, int port, struct ethtool_pauseparam *epause);
12104 +#ifdef ETHTOOL_SPAUSEPARAM
12105 +static int setPauseParams(SK_AC *pAC, int port, struct ethtool_pauseparam *epause);
12107 +#ifdef ETHTOOL_GDRVINFO
12108 +static void getDriverInfo(SK_AC *pAC, int port, struct ethtool_drvinfo *edrvinfo);
12110 +#ifdef ETHTOOL_PHYS_ID
12111 +static int startLocateNIC(SK_AC *pAC, int port, struct ethtool_value *blinkSecs);
12112 +static void toggleLeds(unsigned long ptr);
12114 +#ifdef ETHTOOL_GCOALESCE
12115 +static void getModerationParams(SK_AC *pAC, int port, struct ethtool_coalesce *ecoalesc);
12117 +#ifdef ETHTOOL_SCOALESCE
12118 +static int setModerationParams(SK_AC *pAC, int port, struct ethtool_coalesce *ecoalesc);
12120 +#ifdef ETHTOOL_GWOL
12121 +static void getWOLsettings(SK_AC *pAC, int port, struct ethtool_wolinfo *ewol);
12123 +#ifdef ETHTOOL_SWOL
12124 +static int setWOLsettings(SK_AC *pAC, int port, struct ethtool_wolinfo *ewol);
12127 +static int getPortNumber(struct net_device *netdev, struct ifreq *ifr);
12129 +/******************************************************************************
12131 + * Local Variables
12133 + *****************************************************************************/
12135 +struct sk98lin_stats {
12136 + char stat_string[ETHT_STATSTRING_LEN];
12141 +static struct sk98lin_stats sk98lin_etht_stats_port0[] = {
12142 + { "rx_packets" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxOkCts) },
12143 + { "tx_packets" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxOkCts) },
12144 + { "rx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxOctetsOkCts) },
12145 + { "tx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxOctetsOkCts) },
12146 + { "rx_errors" , SK98LIN_STAT(PnmiStruct.InErrorsCts) },
12147 + { "tx_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxSingleCollisionCts) },
12148 + { "rx_dropped" , SK98LIN_STAT(PnmiStruct.RxNoBufCts) },
12149 + { "tx_dropped" , SK98LIN_STAT(PnmiStruct.TxNoBufCts) },
12150 + { "multicasts" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxMulticastOkCts) },
12151 + { "collisions" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxSingleCollisionCts) },
12152 + { "rx_length_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxRuntCts) },
12153 + { "rx_buffer_overflow_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxFifoOverflowCts) },
12154 + { "rx_crc_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxFcsCts) },
12155 + { "rx_frame_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxFramingCts) },
12156 + { "rx_too_short_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxShortsCts) },
12157 + { "rx_too_long_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxTooLongCts) },
12158 + { "rx_carrier_extension_errors", SK98LIN_STAT(PnmiStruct.Stat[0].StatRxCextCts) },
12159 + { "rx_symbol_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxSymbolCts) },
12160 + { "rx_llc_mac_size_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxIRLengthCts) },
12161 + { "rx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxCarrierCts) },
12162 + { "rx_jabber_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxJabberCts) },
12163 + { "rx_missed_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxMissedCts) },
12164 + { "tx_abort_collision_errors" , SK98LIN_STAT(stats.tx_aborted_errors) },
12165 + { "tx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxCarrierCts) },
12166 + { "tx_buffer_underrun_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxFifoUnderrunCts) },
12167 + { "tx_heartbeat_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxCarrierCts) } ,
12168 + { "tx_window_errors" , SK98LIN_STAT(stats.tx_window_errors) }
12171 +static struct sk98lin_stats sk98lin_etht_stats_port1[] = {
12172 + { "rx_packets" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxOkCts) },
12173 + { "tx_packets" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxOkCts) },
12174 + { "rx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxOctetsOkCts) },
12175 + { "tx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxOctetsOkCts) },
12176 + { "rx_errors" , SK98LIN_STAT(PnmiStruct.InErrorsCts) },
12177 + { "tx_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxSingleCollisionCts) },
12178 + { "rx_dropped" , SK98LIN_STAT(PnmiStruct.RxNoBufCts) },
12179 + { "tx_dropped" , SK98LIN_STAT(PnmiStruct.TxNoBufCts) },
12180 + { "multicasts" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxMulticastOkCts) },
12181 + { "collisions" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxSingleCollisionCts) },
12182 + { "rx_length_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxRuntCts) },
12183 + { "rx_buffer_overflow_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxFifoOverflowCts) },
12184 + { "rx_crc_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxFcsCts) },
12185 + { "rx_frame_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxFramingCts) },
12186 + { "rx_too_short_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxShortsCts) },
12187 + { "rx_too_long_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxTooLongCts) },
12188 + { "rx_carrier_extension_errors", SK98LIN_STAT(PnmiStruct.Stat[1].StatRxCextCts) },
12189 + { "rx_symbol_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxSymbolCts) },
12190 + { "rx_llc_mac_size_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxIRLengthCts) },
12191 + { "rx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxCarrierCts) },
12192 + { "rx_jabber_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxJabberCts) },
12193 + { "rx_missed_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxMissedCts) },
12194 + { "tx_abort_collision_errors" , SK98LIN_STAT(stats.tx_aborted_errors) },
12195 + { "tx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxCarrierCts) },
12196 + { "tx_buffer_underrun_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxFifoUnderrunCts) },
12197 + { "tx_heartbeat_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxCarrierCts) } ,
12198 + { "tx_window_errors" , SK98LIN_STAT(stats.tx_window_errors) }
12201 +#define SK98LIN_STATS_LEN sizeof(sk98lin_etht_stats_port0) / sizeof(struct sk98lin_stats)
12203 +static int nbrBlinkQuarterSeconds;
12204 +static int currentPortIndex;
12205 +static SK_BOOL isLocateNICrunning = SK_FALSE;
12206 +static SK_BOOL isDualNetCard = SK_FALSE;
12207 +static SK_BOOL doSwitchLEDsOn = SK_FALSE;
12208 +static SK_BOOL boardWasDown[2] = { SK_FALSE, SK_FALSE };
12209 +static struct timer_list locateNICtimer;
12211 +/******************************************************************************
12213 + * Global Functions
12215 + *****************************************************************************/
12217 +/*****************************************************************************
12219 + * SkEthIoctl - IOCTL entry point for all ethtool queries
12222 + * Any IOCTL request that has to deal with the ethtool command tool is
12223 + * dispatched via this function.
12226 + * ==0: everything fine, no error
12227 + * !=0: the return value is the error code of the failure
12230 +struct net_device *netdev, /* the pointer to netdev structure */
12231 +struct ifreq *ifr) /* what interface the request refers to? */
12233 + DEV_NET *pNet = (DEV_NET*) netdev->priv;
12234 + SK_AC *pAC = pNet->pAC;
12235 + void *pAddr = ifr->ifr_data;
12236 + int port = getPortNumber(netdev, ifr);
12237 + SK_PNMI_STRUCT_DATA *pPnmiStruct = &pAC->PnmiStruct;
12238 + SK_U32 Size = sizeof(SK_PNMI_STRUCT_DATA);
12240 + struct sk98lin_stats *sk98lin_etht_stats =
12241 + (port == 0) ? sk98lin_etht_stats_port0 : sk98lin_etht_stats_port1;
12243 + if (get_user(cmd, (uint32_t *) pAddr)) {
12248 +#ifdef ETHTOOL_GSET
12249 + case ETHTOOL_GSET: {
12250 + struct ethtool_cmd ecmd = { ETHTOOL_GSET };
12251 + getSettings(pAC, port, &ecmd);
12252 + if(copy_to_user(pAddr, &ecmd, sizeof(ecmd))) {
12259 +#ifdef ETHTOOL_SSET
12260 + case ETHTOOL_SSET: {
12261 + struct ethtool_cmd ecmd;
12262 + if(copy_from_user(&ecmd, pAddr, sizeof(ecmd))) {
12265 + return setSettings(pAC, port, &ecmd);
12269 +#ifdef ETHTOOL_GLINK
12270 + case ETHTOOL_GLINK: {
12271 + struct ethtool_value edata = { ETHTOOL_GLINK };
12272 + edata.data = netif_carrier_ok(netdev);
12273 + if (copy_to_user(pAddr, &edata, sizeof(edata)))
12278 +#ifdef ETHTOOL_GDRVINFO
12279 + case ETHTOOL_GDRVINFO: {
12280 + struct ethtool_drvinfo drvinfo = { ETHTOOL_GDRVINFO };
12281 + getDriverInfo(pAC, port, &drvinfo);
12282 + if(copy_to_user(pAddr, &drvinfo, sizeof(drvinfo))) {
12289 +#ifdef ETHTOOL_GSTRINGS
12290 + case ETHTOOL_GSTRINGS: {
12291 + struct ethtool_gstrings gstrings = { ETHTOOL_GSTRINGS };
12292 + char *strings = NULL;
12294 + if(copy_from_user(&gstrings, pAddr, sizeof(gstrings))) {
12297 + switch(gstrings.string_set) {
12298 +#ifdef ETHTOOL_GSTATS
12299 + case ETH_SS_STATS: {
12301 + gstrings.len = SK98LIN_STATS_LEN;
12302 + if ((strings = kmalloc(SK98LIN_STATS_LEN*ETHT_STATSTRING_LEN,GFP_KERNEL)) == NULL) {
12305 + for(i=0; i < SK98LIN_STATS_LEN; i++) {
12306 + memcpy(&strings[i * ETHT_STATSTRING_LEN],
12307 + &(sk98lin_etht_stats[i].stat_string),
12308 + ETHT_STATSTRING_LEN);
12314 + return -EOPNOTSUPP;
12316 + if(copy_to_user(pAddr, &gstrings, sizeof(gstrings))) {
12319 + pAddr = (void *) ((unsigned long int) pAddr + offsetof(struct ethtool_gstrings, data));
12320 + if(!err && copy_to_user(pAddr, strings, gstrings.len * ETH_GSTRING_LEN)) {
12327 +#ifdef ETHTOOL_GSTATS
12328 + case ETHTOOL_GSTATS: {
12330 + struct ethtool_stats eth_stats;
12331 + uint64_t data[SK98LIN_STATS_LEN];
12332 + } stats = { {ETHTOOL_GSTATS, SK98LIN_STATS_LEN} };
12335 + if (netif_running(pAC->dev[port])) {
12336 + SkPnmiGetStruct(pAC, pAC->IoBase, pPnmiStruct, &Size, port);
12338 + for(i = 0; i < SK98LIN_STATS_LEN; i++) {
12339 + if (netif_running(pAC->dev[port])) {
12340 + stats.data[i] = (sk98lin_etht_stats[i].sizeof_stat ==
12341 + sizeof(uint64_t)) ?
12342 + *(uint64_t *)((char *)pAC +
12343 + sk98lin_etht_stats[i].stat_offset) :
12344 + *(uint32_t *)((char *)pAC +
12345 + sk98lin_etht_stats[i].stat_offset);
12347 + stats.data[i] = (sk98lin_etht_stats[i].sizeof_stat ==
12348 + sizeof(uint64_t)) ? (uint64_t) 0 : (uint32_t) 0;
12351 + if(copy_to_user(pAddr, &stats, sizeof(stats))) {
12357 +#ifdef ETHTOOL_PHYS_ID
12358 + case ETHTOOL_PHYS_ID: {
12359 + struct ethtool_value blinkSecs;
12360 + if(copy_from_user(&blinkSecs, pAddr, sizeof(blinkSecs))) {
12363 + return startLocateNIC(pAC, port, &blinkSecs);
12366 +#ifdef ETHTOOL_GPAUSEPARAM
12367 + case ETHTOOL_GPAUSEPARAM: {
12368 + struct ethtool_pauseparam epause = { ETHTOOL_GPAUSEPARAM };
12369 + getPauseParams(pAC, port, &epause);
12370 + if(copy_to_user(pAddr, &epause, sizeof(epause))) {
12376 +#ifdef ETHTOOL_SPAUSEPARAM
12377 + case ETHTOOL_SPAUSEPARAM: {
12378 + struct ethtool_pauseparam epause;
12379 + if(copy_from_user(&epause, pAddr, sizeof(epause))) {
12382 + return setPauseParams(pAC, port, &epause);
12385 +#ifdef ETHTOOL_GSG
12386 + case ETHTOOL_GSG: {
12387 + struct ethtool_value edata = { ETHTOOL_GSG };
12388 + edata.data = (netdev->features & NETIF_F_SG) != 0;
12389 + if (copy_to_user(pAddr, &edata, sizeof(edata))) {
12395 +#ifdef ETHTOOL_SSG
12396 + case ETHTOOL_SSG: {
12397 + struct ethtool_value edata;
12398 + if (copy_from_user(&edata, pAddr, sizeof(edata))) {
12401 + if (pAC->ChipsetType) { /* Don't handle if Genesis */
12402 + if (edata.data) {
12403 + netdev->features |= NETIF_F_SG;
12405 + netdev->features &= ~NETIF_F_SG;
12411 +#ifdef ETHTOOL_GRXCSUM
12412 + case ETHTOOL_GRXCSUM: {
12413 + struct ethtool_value edata = { ETHTOOL_GRXCSUM };
12414 + edata.data = pAC->RxPort[port].UseRxCsum;
12415 + if (copy_to_user(pAddr, &edata, sizeof(edata))) {
12421 +#ifdef ETHTOOL_SRXCSUM
12422 + case ETHTOOL_SRXCSUM: {
12423 + struct ethtool_value edata;
12424 + if (copy_from_user(&edata, pAddr, sizeof(edata))) {
12427 + pAC->RxPort[port].UseRxCsum = edata.data;
12431 +#ifdef ETHTOOL_GTXCSUM
12432 + case ETHTOOL_GTXCSUM: {
12433 + struct ethtool_value edata = { ETHTOOL_GTXCSUM };
12434 + edata.data = ((netdev->features & NETIF_F_IP_CSUM) != 0);
12435 + if (copy_to_user(pAddr, &edata, sizeof(edata))) {
12441 +#ifdef ETHTOOL_STXCSUM
12442 + case ETHTOOL_STXCSUM: {
12443 + struct ethtool_value edata;
12444 + if (copy_from_user(&edata, pAddr, sizeof(edata))) {
12447 + if (pAC->ChipsetType) { /* Don't handle if Genesis */
12448 + if (edata.data) {
12449 + netdev->features |= NETIF_F_IP_CSUM;
12451 + netdev->features &= ~NETIF_F_IP_CSUM;
12457 +#ifdef ETHTOOL_NWAY_RST
12458 + case ETHTOOL_NWAY_RST: {
12459 + if(netif_running(netdev)) {
12460 + (*netdev->stop)(netdev);
12461 + (*netdev->open)(netdev);
12466 +#ifdef NETIF_F_TSO
12467 +#ifdef ETHTOOL_GTSO
12468 + case ETHTOOL_GTSO: {
12469 + struct ethtool_value edata = { ETHTOOL_GTSO };
12470 + edata.data = (netdev->features & NETIF_F_TSO) != 0;
12471 + if (copy_to_user(pAddr, &edata, sizeof(edata))) {
12477 +#ifdef ETHTOOL_STSO
12478 + case ETHTOOL_STSO: {
12479 + struct ethtool_value edata;
12480 + if (CHIP_ID_YUKON_2(pAC)) {
12481 + if (copy_from_user(&edata, pAddr, sizeof(edata))) {
12484 + if (edata.data) {
12485 + netdev->features |= NETIF_F_TSO;
12487 + netdev->features &= ~NETIF_F_TSO;
12491 + return -EOPNOTSUPP;
12495 +#ifdef ETHTOOL_GCOALESCE
12496 + case ETHTOOL_GCOALESCE: {
12497 + struct ethtool_coalesce ecoalesc = { ETHTOOL_GCOALESCE };
12498 + getModerationParams(pAC, port, &ecoalesc);
12499 + if(copy_to_user(pAddr, &ecoalesc, sizeof(ecoalesc))) {
12505 +#ifdef ETHTOOL_SCOALESCE
12506 + case ETHTOOL_SCOALESCE: {
12507 + struct ethtool_coalesce ecoalesc;
12508 + if(copy_from_user(&ecoalesc, pAddr, sizeof(ecoalesc))) {
12511 + return setModerationParams(pAC, port, &ecoalesc);
12514 +#ifdef ETHTOOL_GWOL
12515 + case ETHTOOL_GWOL: {
12516 + struct ethtool_wolinfo ewol = { ETHTOOL_GWOL };
12517 + getWOLsettings(pAC, port, &ewol);
12518 + if(copy_to_user(pAddr, &ewol, sizeof(ewol))) {
12524 +#ifdef ETHTOOL_SWOL
12525 + case ETHTOOL_SWOL: {
12526 + struct ethtool_wolinfo ewol;
12527 + if(copy_from_user(&ewol, pAddr, sizeof(ewol))) {
12530 + return setWOLsettings(pAC, port, &ewol);
12534 + return -EOPNOTSUPP;
12536 +} /* SkEthIoctl() */
12538 /******************************************************************************
12542 *****************************************************************************/
12544 +#ifdef ETHTOOL_GSET
12545 /*****************************************************************************
12547 * getSettings - retrieves the current settings of the selected adapter
12548 @@ -81,15 +541,15 @@
12549 * This configuration involves a)speed, b)duplex and c)autoneg plus
12550 * a number of other variables.
12552 - * Returns: always 0
12556 -static int getSettings(struct net_device *dev, struct ethtool_cmd *ecmd)
12557 +static void getSettings(
12558 +SK_AC *pAC, /* pointer to adapter control context */
12559 +int port, /* the port of the selected adapter */
12560 +struct ethtool_cmd *ecmd) /* mandatory command structure for results */
12562 - const DEV_NET *pNet = netdev_priv(dev);
12563 - int port = pNet->PortNr;
12564 - const SK_AC *pAC = pNet->pAC;
12565 - const SK_GEPORT *pPort = &pAC->GIni.GP[port];
12566 + SK_GEPORT *pPort = &pAC->GIni.GP[port];
12568 static int DuplexAutoNegConfMap[9][3]= {
12570 @@ -102,6 +562,7 @@
12571 { SK_LMODE_AUTOSENSE , -1 , -1 },
12572 { SK_LMODE_INDETERMINATED, -1 , -1 }
12575 static int SpeedConfMap[6][2] = {
12577 { SK_LSPEED_AUTO , -1 },
12578 @@ -110,6 +571,7 @@
12579 { SK_LSPEED_1000MBPS , SPEED_1000 },
12580 { SK_LSPEED_INDETERMINATED, -1 }
12583 static int AdvSpeedMap[6][2] = {
12585 { SK_LSPEED_AUTO , -1 },
12586 @@ -137,12 +599,10 @@
12587 if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {
12588 ecmd->supported &= ~(SUPPORTED_1000baseT_Half);
12590 -#ifdef CHIP_ID_YUKON_FE
12591 if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) {
12592 ecmd->supported &= ~(SUPPORTED_1000baseT_Half);
12593 ecmd->supported &= ~(SUPPORTED_1000baseT_Full);
12597 if (pAC->GIni.GP[0].PLinkSpeed != SK_LSPEED_AUTO) {
12598 ecmd->advertising = AdvSpeedMap[pPort->PLinkSpeed][1];
12599 @@ -152,26 +612,20 @@
12601 ecmd->advertising = ecmd->supported;
12604 - if (ecmd->autoneg == AUTONEG_ENABLE)
12605 + if (ecmd->autoneg == AUTONEG_ENABLE) {
12606 ecmd->advertising |= ADVERTISED_Autoneg;
12608 + ecmd->advertising = ADVERTISED_TP;
12611 ecmd->port = PORT_FIBRE;
12612 - ecmd->supported = SUPP_FIBRE_ALL;
12613 - ecmd->advertising = ADV_FIBRE_ALL;
12614 + ecmd->supported = (SUPP_FIBRE_ALL);
12615 + ecmd->advertising = (ADV_FIBRE_ALL);
12621 - * MIB infrastructure uses instance value starting at 1
12622 - * based on board and port.
12624 -static inline u32 pnmiInstance(const DEV_NET *pNet)
12626 - return 1 + (pNet->pAC->RlmtNets == 2) + pNet->PortNr;
12630 +#ifdef ETHTOOL_SSET
12631 /*****************************************************************************
12633 * setSettings - configures the settings of a selected adapter
12634 @@ -181,422 +635,719 @@
12635 * c)autonegotiation.
12638 - * 0: everything fine, no error
12639 - * <0: the return value is the error code of the failure
12640 + * ==0: everything fine, no error
12641 + * !=0: the return value is the error code of the failure
12643 -static int setSettings(struct net_device *dev, struct ethtool_cmd *ecmd)
12644 +static int setSettings(
12645 +SK_AC *pAC, /* pointer to adapter control context */
12646 +int port, /* the port of the selected adapter */
12647 +struct ethtool_cmd *ecmd) /* command structure containing settings */
12649 - DEV_NET *pNet = netdev_priv(dev);
12650 - SK_AC *pAC = pNet->pAC;
12654 + DEV_NET *pNet = (DEV_NET *) pAC->dev[port]->priv;
12657 + unsigned int Len = 1;
12660 - if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100
12661 - && ecmd->speed != SPEED_1000)
12664 - if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
12667 + Instance = (pAC->RlmtNets == 2) ? 1 : 2;
12669 + Instance = (pAC->RlmtNets == 2) ? 2 : 3;
12672 - if (ecmd->autoneg != AUTONEG_DISABLE && ecmd->autoneg != AUTONEG_ENABLE)
12674 + if (((ecmd->autoneg == AUTONEG_DISABLE) || (ecmd->autoneg == AUTONEG_ENABLE)) &&
12675 + ((ecmd->duplex == DUPLEX_FULL) || (ecmd->duplex == DUPLEX_HALF))) {
12676 + if (ecmd->autoneg == AUTONEG_DISABLE) {
12677 + if (ecmd->duplex == DUPLEX_FULL) {
12678 + *Buf = (char) SK_LMODE_FULL;
12680 + *Buf = (char) SK_LMODE_HALF;
12683 + /* Autoneg on. Enable autoparam */
12684 + *Buf = (char) SK_LMODE_AUTOBOTH;
12687 - if (ecmd->autoneg == AUTONEG_DISABLE)
12688 - *buf = (ecmd->duplex == DUPLEX_FULL)
12689 - ? SK_LMODE_FULL : SK_LMODE_HALF;
12691 - *buf = (ecmd->duplex == DUPLEX_FULL)
12692 - ? SK_LMODE_AUTOFULL : SK_LMODE_AUTOHALF;
12694 - instance = pnmiInstance(pNet);
12695 - if (SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_LINK_MODE,
12696 - &buf, &len, instance, pNet->NetNr) != SK_PNMI_ERR_OK)
12698 + Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_LINK_MODE,
12699 + &Buf, &Len, Instance, pNet->NetNr);
12701 - switch(ecmd->speed) {
12703 - *buf = SK_LSPEED_1000MBPS;
12706 - *buf = SK_LSPEED_100MBPS;
12709 - *buf = SK_LSPEED_10MBPS;
12710 + if (Ret != SK_PNMI_ERR_OK) {
12713 + } else if (ecmd->autoneg == AUTONEG_ENABLE) {
12714 + /* Set default values */
12715 + *Buf = (char) SK_LMODE_AUTOBOTH;
12716 + Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_LINK_MODE,
12717 + &Buf, &Len, Instance, pNet->NetNr);
12720 - if (SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE,
12721 - &buf, &len, instance, pNet->NetNr) != SK_PNMI_ERR_OK)
12722 + if ((ecmd->speed == SPEED_1000) ||
12723 + (ecmd->speed == SPEED_100) ||
12724 + (ecmd->speed == SPEED_10)) {
12725 + if (ecmd->autoneg == AUTONEG_ENABLE) {
12726 + *Buf = (char) SK_LSPEED_AUTO;
12727 + } else if (ecmd->speed == SPEED_1000) {
12728 + *Buf = (char) SK_LSPEED_1000MBPS;
12729 + } else if (ecmd->speed == SPEED_100) {
12730 + *Buf = (char) SK_LSPEED_100MBPS;
12732 + *Buf = (char) SK_LSPEED_10MBPS;
12735 + Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE,
12736 + &Buf, &Len, Instance, pNet->NetNr);
12738 + if (Ret != SK_PNMI_ERR_OK) {
12741 + } else if (ecmd->autoneg == AUTONEG_ENABLE) {
12742 + *Buf = (char) SK_LSPEED_AUTO;
12743 + Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE,
12744 + &Buf, &Len, Instance, pNet->NetNr);
12753 +#ifdef ETHTOOL_GPAUSEPARAM
12754 /*****************************************************************************
12756 - * getDriverInfo - returns generic driver and adapter information
12757 + * getPauseParams - retrieves the pause parameters
12760 - * Generic driver information is returned via this function, such as
12761 - * the name of the driver, its version and and firmware version.
12762 - * In addition to this, the location of the selected adapter is
12763 - * returned as a bus info string (e.g. '01:05.0').
12765 + * All current pause parameters of a selected adapter are placed
12766 + * in the passed ethtool_pauseparam structure and are returned.
12771 -static void getDriverInfo(struct net_device *dev, struct ethtool_drvinfo *info)
12772 +static void getPauseParams(
12773 +SK_AC *pAC, /* pointer to adapter control context */
12774 +int port, /* the port of the selected adapter */
12775 +struct ethtool_pauseparam *epause) /* pause parameter struct for result */
12777 - const DEV_NET *pNet = netdev_priv(dev);
12778 - const SK_AC *pAC = pNet->pAC;
12781 - snprintf(vers, sizeof(vers)-1, VER_STRING "(v%d.%d)",
12782 - (pAC->GIni.GIPciHwRev >> 4) & 0xf, pAC->GIni.GIPciHwRev & 0xf);
12784 - strlcpy(info->driver, DRIVER_FILE_NAME, sizeof(info->driver));
12785 - strcpy(info->version, vers);
12786 - strcpy(info->fw_version, "N/A");
12787 - strlcpy(info->bus_info, pci_name(pAC->PciDev), ETHTOOL_BUSINFO_LEN);
12791 - * Ethtool statistics support.
12793 -static const char StringsStats[][ETH_GSTRING_LEN] = {
12794 - "rx_packets", "tx_packets",
12795 - "rx_bytes", "tx_bytes",
12796 - "rx_errors", "tx_errors",
12797 - "rx_dropped", "tx_dropped",
12798 - "multicasts", "collisions",
12799 - "rx_length_errors", "rx_buffer_overflow_errors",
12800 - "rx_crc_errors", "rx_frame_errors",
12801 - "rx_too_short_errors", "rx_too_long_errors",
12802 - "rx_carrier_extension_errors", "rx_symbol_errors",
12803 - "rx_llc_mac_size_errors", "rx_carrier_errors",
12804 - "rx_jabber_errors", "rx_missed_errors",
12805 - "tx_abort_collision_errors", "tx_carrier_errors",
12806 - "tx_buffer_underrun_errors", "tx_heartbeat_errors",
12807 - "tx_window_errors",
12809 + SK_GEPORT *pPort = &pAC->GIni.GP[port];
12811 -static int getStatsCount(struct net_device *dev)
12813 - return ARRAY_SIZE(StringsStats);
12815 + epause->rx_pause = 0;
12816 + epause->tx_pause = 0;
12818 -static void getStrings(struct net_device *dev, u32 stringset, u8 *data)
12820 - switch(stringset) {
12821 - case ETH_SS_STATS:
12822 - memcpy(data, *StringsStats, sizeof(StringsStats));
12824 + if (pPort->PFlowCtrlMode == SK_FLOW_MODE_LOC_SEND) {
12825 + epause->tx_pause = 1;
12827 + if ((pPort->PFlowCtrlMode == SK_FLOW_MODE_SYMMETRIC) ||
12828 + (pPort->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM)) {
12829 + epause->tx_pause = 1;
12830 + epause->rx_pause = 1;
12834 -static void getEthtoolStats(struct net_device *dev,
12835 - struct ethtool_stats *stats, u64 *data)
12837 - const DEV_NET *pNet = netdev_priv(dev);
12838 - const SK_AC *pAC = pNet->pAC;
12839 - const SK_PNMI_STRUCT_DATA *pPnmiStruct = &pAC->PnmiStruct;
12841 - *data++ = pPnmiStruct->Stat[0].StatRxOkCts;
12842 - *data++ = pPnmiStruct->Stat[0].StatTxOkCts;
12843 - *data++ = pPnmiStruct->Stat[0].StatRxOctetsOkCts;
12844 - *data++ = pPnmiStruct->Stat[0].StatTxOctetsOkCts;
12845 - *data++ = pPnmiStruct->InErrorsCts;
12846 - *data++ = pPnmiStruct->Stat[0].StatTxSingleCollisionCts;
12847 - *data++ = pPnmiStruct->RxNoBufCts;
12848 - *data++ = pPnmiStruct->TxNoBufCts;
12849 - *data++ = pPnmiStruct->Stat[0].StatRxMulticastOkCts;
12850 - *data++ = pPnmiStruct->Stat[0].StatTxSingleCollisionCts;
12851 - *data++ = pPnmiStruct->Stat[0].StatRxRuntCts;
12852 - *data++ = pPnmiStruct->Stat[0].StatRxFifoOverflowCts;
12853 - *data++ = pPnmiStruct->Stat[0].StatRxFcsCts;
12854 - *data++ = pPnmiStruct->Stat[0].StatRxFramingCts;
12855 - *data++ = pPnmiStruct->Stat[0].StatRxShortsCts;
12856 - *data++ = pPnmiStruct->Stat[0].StatRxTooLongCts;
12857 - *data++ = pPnmiStruct->Stat[0].StatRxCextCts;
12858 - *data++ = pPnmiStruct->Stat[0].StatRxSymbolCts;
12859 - *data++ = pPnmiStruct->Stat[0].StatRxIRLengthCts;
12860 - *data++ = pPnmiStruct->Stat[0].StatRxCarrierCts;
12861 - *data++ = pPnmiStruct->Stat[0].StatRxJabberCts;
12862 - *data++ = pPnmiStruct->Stat[0].StatRxMissedCts;
12863 - *data++ = pAC->stats.tx_aborted_errors;
12864 - *data++ = pPnmiStruct->Stat[0].StatTxCarrierCts;
12865 - *data++ = pPnmiStruct->Stat[0].StatTxFifoUnderrunCts;
12866 - *data++ = pPnmiStruct->Stat[0].StatTxCarrierCts;
12867 - *data++ = pAC->stats.tx_window_errors;
12868 + if ((epause->rx_pause == 0) && (epause->tx_pause == 0)) {
12869 + epause->autoneg = SK_FALSE;
12871 + epause->autoneg = SK_TRUE;
12877 +#ifdef ETHTOOL_SPAUSEPARAM
12878 /*****************************************************************************
12880 - * toggleLeds - Changes the LED state of an adapter
12881 + * setPauseParams - configures the pause parameters of an adapter
12884 - * This function changes the current state of all LEDs of an adapter so
12885 - * that it can be located by a user.
12888 + * This function sets the Rx or Tx pause parameters
12891 + * ==0: everything fine, no error
12892 + * !=0: the return value is the error code of the failure
12894 -static void toggleLeds(DEV_NET *pNet, int on)
12895 +static int setPauseParams(
12896 +SK_AC *pAC, /* pointer to adapter control context */
12897 +int port, /* the port of the selected adapter */
12898 +struct ethtool_pauseparam *epause) /* pause parameter struct with params */
12900 - SK_AC *pAC = pNet->pAC;
12901 - int port = pNet->PortNr;
12902 - void __iomem *io = pAC->IoBase;
12904 - if (pAC->GIni.GIGenesis) {
12905 - SK_OUT8(io, MR_ADDR(port,LNK_LED_REG),
12906 - on ? SK_LNK_ON : SK_LNK_OFF);
12907 - SkGeYellowLED(pAC, io,
12908 - on ? (LED_ON >> 1) : (LED_OFF >> 1));
12909 - SkGeXmitLED(pAC, io, MR_ADDR(port,RX_LED_INI),
12910 - on ? SK_LED_TST : SK_LED_DIS);
12912 - if (pAC->GIni.GP[port].PhyType == SK_PHY_BCOM)
12913 - SkXmPhyWrite(pAC, io, port, PHY_BCOM_P_EXT_CTRL,
12914 - on ? PHY_B_PEC_LED_ON : PHY_B_PEC_LED_OFF);
12915 - else if (pAC->GIni.GP[port].PhyType == SK_PHY_LONE)
12916 - SkXmPhyWrite(pAC, io, port, PHY_LONE_LED_CFG,
12917 - on ? 0x0800 : PHY_L_LC_LEDT);
12919 - SkGeXmitLED(pAC, io, MR_ADDR(port,TX_LED_INI),
12920 - on ? SK_LED_TST : SK_LED_DIS);
12921 + SK_GEPORT *pPort = &pAC->GIni.GP[port];
12922 + DEV_NET *pNet = (DEV_NET *) pAC->dev[port]->priv;
12923 + int PrevSpeedVal = pPort->PLinkSpeedUsed;
12928 + SK_BOOL prevAutonegValue = SK_TRUE;
12929 + int prevTxPause = 0;
12930 + int prevRxPause = 0;
12931 + unsigned int Len = 1;
12934 + Instance = (pAC->RlmtNets == 2) ? 1 : 2;
12936 + Instance = (pAC->RlmtNets == 2) ? 2 : 3;
12940 + ** we have to determine the current settings to see if
12941 + ** the operator requested any modification of the flow
12942 + ** control parameters...
12944 + if (pPort->PFlowCtrlMode == SK_FLOW_MODE_LOC_SEND) {
12947 + if ((pPort->PFlowCtrlMode == SK_FLOW_MODE_SYMMETRIC) ||
12948 + (pPort->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM)) {
12953 + if ((prevRxPause == 0) && (prevTxPause == 0)) {
12954 + prevAutonegValue = SK_FALSE;
12959 + ** perform modifications regarding the changes
12960 + ** requested by the operator
12962 + if (epause->autoneg != prevAutonegValue) {
12963 + if (epause->autoneg == AUTONEG_DISABLE) {
12964 + *Buf = (char) SK_FLOW_MODE_NONE;
12966 + *Buf = (char) SK_FLOW_MODE_SYMMETRIC;
12969 - const u16 YukLedOn = (PHY_M_LED_MO_DUP(MO_LED_ON) |
12970 - PHY_M_LED_MO_10(MO_LED_ON) |
12971 - PHY_M_LED_MO_100(MO_LED_ON) |
12972 - PHY_M_LED_MO_1000(MO_LED_ON) |
12973 - PHY_M_LED_MO_RX(MO_LED_ON));
12974 - const u16 YukLedOff = (PHY_M_LED_MO_DUP(MO_LED_OFF) |
12975 - PHY_M_LED_MO_10(MO_LED_OFF) |
12976 - PHY_M_LED_MO_100(MO_LED_OFF) |
12977 - PHY_M_LED_MO_1000(MO_LED_OFF) |
12978 - PHY_M_LED_MO_RX(MO_LED_OFF));
12980 + if(epause->rx_pause && epause->tx_pause) {
12981 + *Buf = (char) SK_FLOW_MODE_SYMMETRIC;
12982 + } else if (epause->rx_pause && !epause->tx_pause) {
12983 + *Buf = (char) SK_FLOW_MODE_SYM_OR_REM;
12984 + } else if(!epause->rx_pause && epause->tx_pause) {
12985 + *Buf = (char) SK_FLOW_MODE_LOC_SEND;
12987 + *Buf = (char) SK_FLOW_MODE_NONE;
12991 + Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_FLOWCTRL_MODE,
12992 + &Buf, &Len, Instance, pNet->NetNr);
12994 + if (Ret != SK_PNMI_ERR_OK) {
12995 + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_CTRL,
12996 + ("ethtool (sk98lin): error changing rx/tx pause (%i)\n", Ret));
12998 + Len = 1; /* set buffer length to correct value */
13002 + ** It may be that autoneg has been disabled! Therefore
13003 + ** set the speed to the previously used value...
13005 + *Buf = (char) PrevSpeedVal;
13007 + Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE,
13008 + &Buf, &Len, Instance, pNet->NetNr);
13010 - SkGmPhyWrite(pAC,io,port,PHY_MARV_LED_CTRL,0);
13011 - SkGmPhyWrite(pAC,io,port,PHY_MARV_LED_OVER,
13012 - on ? YukLedOn : YukLedOff);
13013 + if (Ret != SK_PNMI_ERR_OK) {
13014 + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_CTRL,
13015 + ("ethtool (sk98lin): error setting speed (%i)\n", Ret));
13021 +#ifdef ETHTOOL_GCOALESCE
13022 /*****************************************************************************
13024 - * skGeBlinkTimer - Changes the LED state of an adapter
13025 + * getModerationParams - retrieves the IRQ moderation settings
13028 - * This function changes the current state of all LEDs of an adapter so
13029 - * that it can be located by a user. If the requested time interval for
13030 - * this test has elapsed, this function cleans up everything that was
13031 - * temporarily setup during the locate NIC test. This involves of course
13032 - * also closing or opening any adapter so that the initial board state
13034 + * All current IRQ moderation settings of a selected adapter are placed
13035 + * in the passed ethtool_coalesce structure and are returned.
13040 -void SkGeBlinkTimer(unsigned long data)
13041 +static void getModerationParams(
13042 +SK_AC *pAC, /* pointer to adapter control context */
13043 +int port, /* the port of the selected adapter */
13044 +struct ethtool_coalesce *ecoalesc) /* IRQ moderation struct for results */
13046 - struct net_device *dev = (struct net_device *) data;
13047 - DEV_NET *pNet = netdev_priv(dev);
13048 - SK_AC *pAC = pNet->pAC;
13050 - toggleLeds(pNet, pAC->LedsOn);
13051 + DIM_INFO *Info = &pAC->DynIrqModInfo;
13052 + SK_BOOL UseTxIrqModeration = SK_FALSE;
13053 + SK_BOOL UseRxIrqModeration = SK_FALSE;
13055 + if (Info->IntModTypeSelect != C_INT_MOD_NONE) {
13056 + if (CHIP_ID_YUKON_2(pAC)) {
13057 + UseRxIrqModeration = SK_TRUE;
13058 + UseTxIrqModeration = SK_TRUE;
13060 + if ((Info->MaskIrqModeration == IRQ_MASK_RX_ONLY) ||
13061 + (Info->MaskIrqModeration == IRQ_MASK_SP_RX) ||
13062 + (Info->MaskIrqModeration == IRQ_MASK_RX_TX_SP)) {
13063 + UseRxIrqModeration = SK_TRUE;
13065 + if ((Info->MaskIrqModeration == IRQ_MASK_TX_ONLY) ||
13066 + (Info->MaskIrqModeration == IRQ_MASK_SP_TX) ||
13067 + (Info->MaskIrqModeration == IRQ_MASK_RX_TX_SP)) {
13068 + UseTxIrqModeration = SK_TRUE;
13072 - pAC->LedsOn = !pAC->LedsOn;
13073 - mod_timer(&pAC->BlinkTimer, jiffies + HZ/4);
13074 + if (UseRxIrqModeration) {
13075 + ecoalesc->rx_coalesce_usecs = 1000000 / Info->MaxModIntsPerSec;
13077 + if (UseTxIrqModeration) {
13078 + ecoalesc->tx_coalesce_usecs = 1000000 / Info->MaxModIntsPerSec;
13080 + if (Info->IntModTypeSelect == C_INT_MOD_DYNAMIC) {
13081 + ecoalesc->rate_sample_interval = Info->DynIrqModSampleInterval;
13082 + if (UseRxIrqModeration) {
13083 + ecoalesc->use_adaptive_rx_coalesce = 1;
13084 + ecoalesc->rx_coalesce_usecs_low =
13085 + 1000000 / Info->MaxModIntsPerSecLowerLimit;
13086 + ecoalesc->rx_coalesce_usecs_high =
13087 + 1000000 / Info->MaxModIntsPerSecUpperLimit;
13089 + if (UseTxIrqModeration) {
13090 + ecoalesc->use_adaptive_tx_coalesce = 1;
13091 + ecoalesc->tx_coalesce_usecs_low =
13092 + 1000000 / Info->MaxModIntsPerSecLowerLimit;
13093 + ecoalesc->tx_coalesce_usecs_high =
13094 + 1000000 / Info->MaxModIntsPerSecUpperLimit;
13101 +#ifdef ETHTOOL_SCOALESCE
13102 /*****************************************************************************
13104 - * locateDevice - start the locate NIC feature of the elected adapter
13105 + * setModerationParams - configures the IRQ moderation of an adapter
13108 - * This function is used if the user want to locate a particular NIC.
13109 - * All LEDs are regularly switched on and off, so the NIC can easily
13111 + * Depending on the desired IRQ moderation parameters, either a) static,
13112 + * b) dynamic or c) no moderation is configured.
13115 - * ==0: everything fine, no error, locateNIC test was started
13116 - * !=0: one locateNIC test runs already
13118 + * ==0: everything fine, no error
13119 + * !=0: the return value is the error code of the failure
13122 + * The supported timeframe for the coalesced interrupts ranges from
13123 + * 33.333us (30 IntsPerSec) down to 25us (40.000 IntsPerSec).
13124 + * Any requested value that is not in this range will abort the request!
13126 -static int locateDevice(struct net_device *dev, u32 data)
13127 +static int setModerationParams(
13128 +SK_AC *pAC, /* pointer to adapter control context */
13129 +int port, /* the port of the selected adapter */
13130 +struct ethtool_coalesce *ecoalesc) /* IRQ moderation struct with params */
13132 - DEV_NET *pNet = netdev_priv(dev);
13133 - SK_AC *pAC = pNet->pAC;
13134 + DIM_INFO *Info = &pAC->DynIrqModInfo;
13135 + int PrevModeration = Info->IntModTypeSelect;
13137 - if(!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
13138 - data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
13139 + Info->IntModTypeSelect = C_INT_MOD_NONE; /* initial default */
13141 - /* start blinking */
13143 - mod_timer(&pAC->BlinkTimer, jiffies);
13144 - msleep_interruptible(data * 1000);
13145 - del_timer_sync(&pAC->BlinkTimer);
13146 - toggleLeds(pNet, 0);
13147 + if ((ecoalesc->rx_coalesce_usecs) || (ecoalesc->tx_coalesce_usecs)) {
13148 + if (ecoalesc->rx_coalesce_usecs) {
13149 + if ((ecoalesc->rx_coalesce_usecs < 25) ||
13150 + (ecoalesc->rx_coalesce_usecs > 33333)) {
13154 + if (ecoalesc->tx_coalesce_usecs) {
13155 + if ((ecoalesc->tx_coalesce_usecs < 25) ||
13156 + (ecoalesc->tx_coalesce_usecs > 33333)) {
13160 + if (!CHIP_ID_YUKON_2(pAC)) {
13161 + if ((Info->MaskIrqModeration == IRQ_MASK_SP_RX) ||
13162 + (Info->MaskIrqModeration == IRQ_MASK_SP_TX) ||
13163 + (Info->MaskIrqModeration == IRQ_MASK_RX_TX_SP)) {
13164 + Info->MaskIrqModeration = IRQ_MASK_SP_ONLY;
13167 + Info->IntModTypeSelect = C_INT_MOD_STATIC;
13168 + if (ecoalesc->rx_coalesce_usecs) {
13169 + Info->MaxModIntsPerSec =
13170 + 1000000 / ecoalesc->rx_coalesce_usecs;
13171 + if (!CHIP_ID_YUKON_2(pAC)) {
13172 + if (Info->MaskIrqModeration == IRQ_MASK_TX_ONLY) {
13173 + Info->MaskIrqModeration = IRQ_MASK_TX_RX;
13175 + if (Info->MaskIrqModeration == IRQ_MASK_SP_ONLY) {
13176 + Info->MaskIrqModeration = IRQ_MASK_SP_RX;
13178 + if (Info->MaskIrqModeration == IRQ_MASK_SP_TX) {
13179 + Info->MaskIrqModeration = IRQ_MASK_RX_TX_SP;
13182 + Info->MaskIrqModeration = Y2_IRQ_MASK;
13185 + if (ecoalesc->tx_coalesce_usecs) {
13186 + Info->MaxModIntsPerSec =
13187 + 1000000 / ecoalesc->tx_coalesce_usecs;
13188 + if (!CHIP_ID_YUKON_2(pAC)) {
13189 + if (Info->MaskIrqModeration == IRQ_MASK_RX_ONLY) {
13190 + Info->MaskIrqModeration = IRQ_MASK_TX_RX;
13192 + if (Info->MaskIrqModeration == IRQ_MASK_SP_ONLY) {
13193 + Info->MaskIrqModeration = IRQ_MASK_SP_TX;
13195 + if (Info->MaskIrqModeration == IRQ_MASK_SP_RX) {
13196 + Info->MaskIrqModeration = IRQ_MASK_RX_TX_SP;
13199 + Info->MaskIrqModeration = Y2_IRQ_MASK;
13203 + if ((ecoalesc->rate_sample_interval) ||
13204 + (ecoalesc->rx_coalesce_usecs_low) ||
13205 + (ecoalesc->tx_coalesce_usecs_low) ||
13206 + (ecoalesc->rx_coalesce_usecs_high)||
13207 + (ecoalesc->tx_coalesce_usecs_high)) {
13208 + if (ecoalesc->rate_sample_interval) {
13209 + if ((ecoalesc->rate_sample_interval < 1) ||
13210 + (ecoalesc->rate_sample_interval > 10)) {
13214 + if (ecoalesc->rx_coalesce_usecs_low) {
13215 + if ((ecoalesc->rx_coalesce_usecs_low < 25) ||
13216 + (ecoalesc->rx_coalesce_usecs_low > 33333)) {
13220 + if (ecoalesc->rx_coalesce_usecs_high) {
13221 + if ((ecoalesc->rx_coalesce_usecs_high < 25) ||
13222 + (ecoalesc->rx_coalesce_usecs_high > 33333)) {
13226 + if (ecoalesc->tx_coalesce_usecs_low) {
13227 + if ((ecoalesc->tx_coalesce_usecs_low < 25) ||
13228 + (ecoalesc->tx_coalesce_usecs_low > 33333)) {
13232 + if (ecoalesc->tx_coalesce_usecs_high) {
13233 + if ((ecoalesc->tx_coalesce_usecs_high < 25) ||
13234 + (ecoalesc->tx_coalesce_usecs_high > 33333)) {
13240 + Info->IntModTypeSelect = C_INT_MOD_DYNAMIC;
13241 + if (ecoalesc->rate_sample_interval) {
13242 + Info->DynIrqModSampleInterval =
13243 + ecoalesc->rate_sample_interval;
13245 + if (ecoalesc->rx_coalesce_usecs_low) {
13246 + Info->MaxModIntsPerSecLowerLimit =
13247 + 1000000 / ecoalesc->rx_coalesce_usecs_low;
13249 + if (ecoalesc->tx_coalesce_usecs_low) {
13250 + Info->MaxModIntsPerSecLowerLimit =
13251 + 1000000 / ecoalesc->tx_coalesce_usecs_low;
13253 + if (ecoalesc->rx_coalesce_usecs_high) {
13254 + Info->MaxModIntsPerSecUpperLimit =
13255 + 1000000 / ecoalesc->rx_coalesce_usecs_high;
13257 + if (ecoalesc->tx_coalesce_usecs_high) {
13258 + Info->MaxModIntsPerSecUpperLimit =
13259 + 1000000 / ecoalesc->tx_coalesce_usecs_high;
13263 + if ((PrevModeration == C_INT_MOD_NONE) &&
13264 + (Info->IntModTypeSelect != C_INT_MOD_NONE)) {
13265 + SkDimEnableModerationIfNeeded(pAC);
13267 + if (PrevModeration != C_INT_MOD_NONE) {
13268 + SkDimDisableModeration(pAC, PrevModeration);
13269 + if (Info->IntModTypeSelect != C_INT_MOD_NONE) {
13270 + SkDimEnableModerationIfNeeded(pAC);
13278 +#ifdef ETHTOOL_GWOL
13279 /*****************************************************************************
13281 - * getPauseParams - retrieves the pause parameters
13282 + * getWOLsettings - retrieves the WOL settings of the selected adapter
13285 - * All current pause parameters of a selected adapter are placed
13286 - * in the passed ethtool_pauseparam structure and are returned.
13287 + * All current WOL settings of a selected adapter are placed in the
13288 + * passed ethtool_wolinfo structure and are returned to the caller.
13293 -static void getPauseParams(struct net_device *dev, struct ethtool_pauseparam *epause)
13294 +static void getWOLsettings(
13295 +SK_AC *pAC, /* pointer to adapter control context */
13296 +int port, /* the port of the selected adapter */
13297 +struct ethtool_wolinfo *ewol) /* mandatory WOL structure for results */
13299 - DEV_NET *pNet = netdev_priv(dev);
13300 - SK_AC *pAC = pNet->pAC;
13301 - SK_GEPORT *pPort = &pAC->GIni.GP[pNet->PortNr];
13302 + ewol->supported = pAC->WolInfo.SupportedWolOptions;
13303 + ewol->wolopts = pAC->WolInfo.ConfiguredWolOptions;
13305 - epause->rx_pause = (pPort->PFlowCtrlMode == SK_FLOW_MODE_SYMMETRIC) ||
13306 - (pPort->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM);
13308 - epause->tx_pause = epause->rx_pause || (pPort->PFlowCtrlMode == SK_FLOW_MODE_LOC_SEND);
13309 - epause->autoneg = epause->rx_pause || epause->tx_pause;
13314 +#ifdef ETHTOOL_SWOL
13315 /*****************************************************************************
13317 - * setPauseParams - configures the pause parameters of an adapter
13318 + * setWOLsettings - configures the WOL settings of a selected adapter
13321 - * This function sets the Rx or Tx pause parameters
13322 + * The WOL settings of a selected adapter are configured regarding
13323 + * the parameters in the passed ethtool_wolinfo structure.
13324 + * Note that currently only wake on magic packet is supported!
13327 * ==0: everything fine, no error
13328 * !=0: the return value is the error code of the failure
13330 -static int setPauseParams(struct net_device *dev , struct ethtool_pauseparam *epause)
13331 +static int setWOLsettings(
13332 +SK_AC *pAC, /* pointer to adapter control context */
13333 +int port, /* the port of the selected adapter */
13334 +struct ethtool_wolinfo *ewol) /* WOL structure containing settings */
13336 - DEV_NET *pNet = netdev_priv(dev);
13337 - SK_AC *pAC = pNet->pAC;
13338 - SK_GEPORT *pPort = &pAC->GIni.GP[pNet->PortNr];
13339 - u32 instance = pnmiInstance(pNet);
13340 - struct ethtool_pauseparam old;
13341 - u8 oldspeed = pPort->PLinkSpeedUsed;
13345 + if (((ewol->wolopts & WAKE_MAGIC) == WAKE_MAGIC) || (ewol->wolopts == 0)) {
13346 + pAC->WolInfo.ConfiguredWolOptions = ewol->wolopts;
13354 - ** we have to determine the current settings to see if
13355 - ** the operator requested any modification of the flow
13356 - ** control parameters...
13358 - getPauseParams(dev, &old);
13359 +#ifdef ETHTOOL_GDRVINFO
13360 +/*****************************************************************************
13362 + * getDriverInfo - returns generic driver and adapter information
13365 + * Generic driver information is returned via this function, such as
13366 + * the name of the driver, its version and and firmware version.
13367 + * In addition to this, the location of the selected adapter is
13368 + * returned as a bus info string (e.g. '01:05.0').
13373 +static void getDriverInfo(
13374 +SK_AC *pAC, /* pointer to adapter control context */
13375 +int port, /* the port of the selected adapter */
13376 +struct ethtool_drvinfo *edrvinfo) /* mandatory info structure for results */
13378 + char versionString[32];
13381 - ** perform modifications regarding the changes
13382 - ** requested by the operator
13384 - if (epause->autoneg != old.autoneg)
13385 - *buf = epause->autoneg ? SK_FLOW_MODE_NONE : SK_FLOW_MODE_SYMMETRIC;
13387 - if (epause->rx_pause && epause->tx_pause)
13388 - *buf = SK_FLOW_MODE_SYMMETRIC;
13389 - else if (epause->rx_pause && !epause->tx_pause)
13390 - *buf = SK_FLOW_MODE_SYM_OR_REM;
13391 - else if (!epause->rx_pause && epause->tx_pause)
13392 - *buf = SK_FLOW_MODE_LOC_SEND;
13394 - *buf = SK_FLOW_MODE_NONE;
13395 + snprintf(versionString, 32, "%s (%s)", VER_STRING, PATCHLEVEL);
13396 + strncpy(edrvinfo->driver, DRIVER_FILE_NAME , 32);
13397 + strncpy(edrvinfo->version, versionString , 32);
13398 + strncpy(edrvinfo->fw_version, "N/A", 32);
13399 + strncpy(edrvinfo->bus_info, pci_name(pAC->PciDev), 32);
13401 +#ifdef ETHTOOL_GSTATS
13402 + edrvinfo->n_stats = SK98LIN_STATS_LEN;
13407 +#ifdef ETHTOOL_PHYS_ID
13408 +/*****************************************************************************
13410 + * startLocateNIC - start the locate NIC feature of the elected adapter
13413 + * This function is used if the user want to locate a particular NIC.
13414 + * All LEDs are regularly switched on and off, so the NIC can easily
13418 + * ==0: everything fine, no error, locateNIC test was started
13419 + * !=0: one locateNIC test runs already
13422 +static int startLocateNIC(
13423 +SK_AC *pAC, /* pointer to adapter control context */
13424 +int port, /* the port of the selected adapter */
13425 +struct ethtool_value *blinkSecs) /* how long the LEDs should blink in seconds */
13427 + struct SK_NET_DEVICE *pDev = pAC->dev[port];
13428 + int OtherPort = (port) ? 0 : 1;
13429 + struct SK_NET_DEVICE *pOtherDev = pAC->dev[OtherPort];
13431 + if (isLocateNICrunning) {
13434 + isLocateNICrunning = SK_TRUE;
13435 + currentPortIndex = port;
13436 + isDualNetCard = (pDev != pOtherDev) ? SK_TRUE : SK_FALSE;
13438 - ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_FLOWCTRL_MODE,
13439 - &buf, &len, instance, pNet->NetNr);
13440 + if (netif_running(pAC->dev[port])) {
13441 + boardWasDown[0] = SK_FALSE;
13443 + (*pDev->open)(pDev);
13444 + boardWasDown[0] = SK_TRUE;
13447 - if (ret != SK_PNMI_ERR_OK) {
13448 - SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_CTRL,
13449 - ("ethtool (sk98lin): error changing rx/tx pause (%i)\n", ret));
13451 + if (isDualNetCard) {
13452 + if (netif_running(pAC->dev[OtherPort])) {
13453 + boardWasDown[1] = SK_FALSE;
13455 + (*pOtherDev->open)(pOtherDev);
13456 + boardWasDown[1] = SK_TRUE;
13461 - ** It may be that autoneg has been disabled! Therefore
13462 - ** set the speed to the previously used value...
13464 - if (!epause->autoneg) {
13466 - ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE,
13467 - &oldspeed, &len, instance, pNet->NetNr);
13468 - if (ret != SK_PNMI_ERR_OK)
13469 - SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_CTRL,
13470 - ("ethtool (sk98lin): error setting speed (%i)\n", ret));
13471 + if ((blinkSecs->data < 1) || (blinkSecs->data > 30)) {
13472 + blinkSecs->data = 3; /* three seconds default */
13475 - return ret ? -EIO : 0;
13477 + nbrBlinkQuarterSeconds = 4*blinkSecs->data;
13479 -/* Only Yukon supports checksum offload. */
13480 -static int setScatterGather(struct net_device *dev, u32 data)
13482 - DEV_NET *pNet = netdev_priv(dev);
13483 - SK_AC *pAC = pNet->pAC;
13484 + init_timer(&locateNICtimer);
13485 + locateNICtimer.function = toggleLeds;
13486 + locateNICtimer.data = (unsigned long) pAC;
13487 + locateNICtimer.expires = jiffies + HZ; /* initially 1sec */
13488 + add_timer(&locateNICtimer);
13490 - if (pAC->GIni.GIChipId == CHIP_ID_GENESIS)
13491 - return -EOPNOTSUPP;
13492 - return ethtool_op_set_sg(dev, data);
13496 -static int setTxCsum(struct net_device *dev, u32 data)
13497 +/*****************************************************************************
13499 + * toggleLeds - Changes the LED state of an adapter
13502 + * This function changes the current state of all LEDs of an adapter so
13503 + * that it can be located by a user. If the requested time interval for
13504 + * this test has elapsed, this function cleans up everything that was
13505 + * temporarily setup during the locate NIC test. This involves of course
13506 + * also closing or opening any adapter so that the initial board state
13512 +static void toggleLeds(
13513 +unsigned long ptr) /* holds the pointer to adapter control context */
13515 - DEV_NET *pNet = netdev_priv(dev);
13516 - SK_AC *pAC = pNet->pAC;
13518 - if (pAC->GIni.GIChipId == CHIP_ID_GENESIS)
13519 - return -EOPNOTSUPP;
13520 + SK_AC *pAC = (SK_AC *) ptr;
13521 + int port = currentPortIndex;
13522 + SK_IOC IoC = pAC->IoBase;
13523 + struct SK_NET_DEVICE *pDev = pAC->dev[port];
13524 + int OtherPort = (port) ? 0 : 1;
13525 + struct SK_NET_DEVICE *pOtherDev = pAC->dev[OtherPort];
13527 + SK_U16 YukLedOn = (PHY_M_LED_MO_DUP(MO_LED_ON) |
13528 + PHY_M_LED_MO_10(MO_LED_ON) |
13529 + PHY_M_LED_MO_100(MO_LED_ON) |
13530 + PHY_M_LED_MO_1000(MO_LED_ON) |
13531 + PHY_M_LED_MO_RX(MO_LED_ON));
13532 + SK_U16 YukLedOff = (PHY_M_LED_MO_DUP(MO_LED_OFF) |
13533 + PHY_M_LED_MO_10(MO_LED_OFF) |
13534 + PHY_M_LED_MO_100(MO_LED_OFF) |
13535 + PHY_M_LED_MO_1000(MO_LED_OFF) |
13536 + PHY_M_LED_MO_RX(MO_LED_OFF));
13538 + nbrBlinkQuarterSeconds--;
13539 + if (nbrBlinkQuarterSeconds <= 0) {
13540 + (*pDev->stop)(pDev);
13541 + if (isDualNetCard) {
13542 + (*pOtherDev->stop)(pOtherDev);
13545 - return ethtool_op_set_tx_csum(dev, data);
13547 + if (!boardWasDown[0]) {
13548 + (*pDev->open)(pDev);
13550 + if (isDualNetCard) {
13551 + (*pOtherDev->open)(pOtherDev);
13553 + isDualNetCard = SK_FALSE;
13554 + isLocateNICrunning = SK_FALSE;
13558 -static u32 getRxCsum(struct net_device *dev)
13560 - DEV_NET *pNet = netdev_priv(dev);
13561 - SK_AC *pAC = pNet->pAC;
13562 + doSwitchLEDsOn = (doSwitchLEDsOn) ? SK_FALSE : SK_TRUE;
13563 + if (doSwitchLEDsOn) {
13564 + if (pAC->GIni.GIGenesis) {
13565 + SK_OUT8(IoC,MR_ADDR(port,LNK_LED_REG),(SK_U8)SK_LNK_ON);
13566 + SkGeYellowLED(pAC,IoC,LED_ON >> 1);
13567 + SkGeXmitLED(pAC,IoC,MR_ADDR(port,RX_LED_INI),SK_LED_TST);
13568 + if (pAC->GIni.GP[port].PhyType == SK_PHY_BCOM) {
13569 + SkXmPhyWrite(pAC,IoC,port,PHY_BCOM_P_EXT_CTRL,PHY_B_PEC_LED_ON);
13570 + } else if (pAC->GIni.GP[port].PhyType == SK_PHY_LONE) {
13571 + SkXmPhyWrite(pAC,IoC,port,PHY_LONE_LED_CFG,0x0800);
13573 + SkGeXmitLED(pAC,IoC,MR_ADDR(port,TX_LED_INI),SK_LED_TST);
13576 + SkGmPhyWrite(pAC,IoC,port,PHY_MARV_LED_CTRL,0);
13577 + SkGmPhyWrite(pAC,IoC,port,PHY_MARV_LED_OVER,YukLedOn);
13580 + if (pAC->GIni.GIGenesis) {
13581 + SK_OUT8(IoC,MR_ADDR(port,LNK_LED_REG),(SK_U8)SK_LNK_OFF);
13582 + SkGeYellowLED(pAC,IoC,LED_OFF >> 1);
13583 + SkGeXmitLED(pAC,IoC,MR_ADDR(port,RX_LED_INI),SK_LED_DIS);
13584 + if (pAC->GIni.GP[port].PhyType == SK_PHY_BCOM) {
13585 + SkXmPhyWrite(pAC,IoC,port,PHY_BCOM_P_EXT_CTRL,PHY_B_PEC_LED_OFF);
13586 + } else if (pAC->GIni.GP[port].PhyType == SK_PHY_LONE) {
13587 + SkXmPhyWrite(pAC,IoC,port,PHY_LONE_LED_CFG,PHY_L_LC_LEDT);
13589 + SkGeXmitLED(pAC,IoC,MR_ADDR(port,TX_LED_INI),SK_LED_DIS);
13592 + SkGmPhyWrite(pAC,IoC,port,PHY_MARV_LED_CTRL,0);
13593 + SkGmPhyWrite(pAC,IoC,port,PHY_MARV_LED_OVER,YukLedOff);
13597 - return pAC->RxPort[pNet->PortNr].RxCsum;
13599 + locateNICtimer.function = toggleLeds;
13600 + locateNICtimer.data = (unsigned long) pAC;
13601 + locateNICtimer.expires = jiffies + (HZ/4); /* 250ms */
13602 + add_timer(&locateNICtimer);
13606 -static int setRxCsum(struct net_device *dev, u32 data)
13607 +/*****************************************************************************
13609 + * getPortNumber - evaluates the port number of an interface
13612 + * It may be that the current interface refers to one which is located
13613 + * on a dual net adapter. Hence, this function will return the correct
13614 + * port for further use.
13617 + * the port number that corresponds to the selected adapter
13620 +static int getPortNumber(
13621 +struct net_device *netdev, /* the pointer to netdev structure */
13622 +struct ifreq *ifr) /* what interface the request refers to? */
13624 - DEV_NET *pNet = netdev_priv(dev);
13625 - SK_AC *pAC = pNet->pAC;
13627 - if (pAC->GIni.GIChipId == CHIP_ID_GENESIS)
13628 - return -EOPNOTSUPP;
13629 + DEV_NET *pNet = (DEV_NET*) netdev->priv;
13630 + SK_AC *pAC = pNet->pAC;
13632 - pAC->RxPort[pNet->PortNr].RxCsum = data != 0;
13633 + if (pAC->dev[1] != pAC->dev[0]) {
13634 + if (!strcmp(pAC->dev[1]->name, ifr->ifr_name)) {
13635 + return 1; /* port index 1 */
13641 -const struct ethtool_ops SkGeEthtoolOps = {
13642 - .get_settings = getSettings,
13643 - .set_settings = setSettings,
13644 - .get_drvinfo = getDriverInfo,
13645 - .get_strings = getStrings,
13646 - .get_stats_count = getStatsCount,
13647 - .get_ethtool_stats = getEthtoolStats,
13648 - .phys_id = locateDevice,
13649 - .get_pauseparam = getPauseParams,
13650 - .set_pauseparam = setPauseParams,
13651 - .get_link = ethtool_op_get_link,
13652 - .get_perm_addr = ethtool_op_get_perm_addr,
13653 - .get_sg = ethtool_op_get_sg,
13654 - .set_sg = setScatterGather,
13655 - .get_tx_csum = ethtool_op_get_tx_csum,
13656 - .set_tx_csum = setTxCsum,
13657 - .get_rx_csum = getRxCsum,
13658 - .set_rx_csum = setRxCsum,
13660 +/*******************************************************************************
13664 + ******************************************************************************/
13665 diff -ruN linux/drivers/net/sk98lin/skge.c linux-new/drivers/net/sk98lin/skge.c
13666 --- linux/drivers/net/sk98lin/skge.c 2006-09-20 05:42:06.000000000 +0200
13667 +++ linux-new/drivers/net/sk98lin/skge.c 2006-07-28 14:13:56.000000000 +0200
13669 /******************************************************************************
13672 - * Project: GEnesis, PCI Gigabit Ethernet Adapter
13673 - * Version: $Revision$
13675 - * Purpose: The main driver source module
13677 + * Project: GEnesis, PCI Gigabit Ethernet Adapter
13678 + * Version: $Revision$
13680 + * Purpose: The main driver source module
13682 ******************************************************************************/
13684 /******************************************************************************
13686 * (C)Copyright 1998-2002 SysKonnect GmbH.
13687 - * (C)Copyright 2002-2003 Marvell.
13688 + * (C)Copyright 2002-2005 Marvell.
13690 * Driver for Marvell Yukon chipset and SysKonnect Gigabit Ethernet
13693 - * Created 10-Feb-1999, based on Linux' acenic.c, 3c59x.c and
13694 - * SysKonnects GEnesis Solaris driver
13695 - * Author: Christoph Goos (cgoos@syskonnect.de)
13696 - * Mirko Lindner (mlindner@syskonnect.de)
13697 + * Author: Mirko Lindner (mlindner@syskonnect.de)
13698 + * Ralph Roesler (rroesler@syskonnect.de)
13700 * Address all question to: linux@syskonnect.de
13702 - * The technical manual for the adapters is available from SysKonnect's
13703 - * web pages: www.syskonnect.com
13704 - * Goto "Support" and search Knowledge Base for "manual".
13706 * This program is free software; you can redistribute it and/or modify
13707 * it under the terms of the GNU General Public License as published by
13708 * the Free Software Foundation; either version 2 of the License, or
13709 @@ -38,85 +32,53 @@
13711 /******************************************************************************
13713 - * Possible compiler options (#define xxx / -Dxxx):
13715 - * debugging can be enable by changing SK_DEBUG_CHKMOD and
13716 - * SK_DEBUG_CHKCAT in makefile (described there).
13718 - ******************************************************************************/
13720 -/******************************************************************************
13724 - * This is the main module of the Linux GE driver.
13726 - * All source files except skge.c, skdrv1st.h, skdrv2nd.h and sktypes.h
13727 - * are part of SysKonnect's COMMON MODULES for the SK-98xx adapters.
13728 - * Those are used for drivers on multiple OS', so some thing may seem
13729 - * unnecessary complicated on Linux. Please do not try to 'clean up'
13730 - * them without VERY good reasons, because this will make it more
13731 - * difficult to keep the Linux driver in synchronisation with the
13732 - * other versions.
13734 - * Include file hierarchy:
13736 - * <linux/module.h>
13739 - * <linux/types.h>
13740 - * <linux/kernel.h>
13741 - * <linux/string.h>
13742 - * <linux/errno.h>
13743 - * <linux/ioport.h>
13745 - * <linux/interrupt.h>
13747 - * <linux/bitops.h>
13748 - * <asm/byteorder.h>
13750 - * <linux/netdevice.h>
13751 - * <linux/etherdevice.h>
13752 - * <linux/skbuff.h>
13753 - * those three depending on kernel version used:
13754 - * <linux/bios32.h>
13756 - * <asm/uaccess.h>
13757 - * <net/checksum.h>
13777 + * All source files in this sk98lin directory except of the sk98lin
13778 + * Linux specific files
13789 + * - h/skversion.h
13791 + * are part of SysKonnect's common modules for the SK-9xxx adapters.
13793 + * Those common module files which are not Linux specific are used to
13794 + * build drivers on different OS' (e.g. Windows, MAC OS) so that those
13795 + * drivers are based on the same set of files
13797 + * At a first glance, this seems to complicate things unnescessarily on
13798 + * Linux, but please do not try to 'clean up' them without VERY good
13799 + * reasons, because this will make it more difficult to keep the sk98lin
13800 + * driver for Linux in synchronisation with the other drivers running on
13801 + * other operating systems.
13803 ******************************************************************************/
13805 #include "h/skversion.h"
13807 -#include <linux/in.h>
13808 #include <linux/module.h>
13809 -#include <linux/moduleparam.h>
13810 #include <linux/init.h>
13811 -#include <linux/dma-mapping.h>
13812 -#include <linux/ip.h>
13813 +#include <linux/ethtool.h>
13815 +#ifdef CONFIG_PROC_FS
13816 +#include <linux/proc_fs.h>
13819 #include "h/skdrv1st.h"
13820 #include "h/skdrv2nd.h"
13822 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
13823 +#include <linux/moduleparam.h>
13826 /*******************************************************************************
13829 @@ -126,62 +88,15 @@
13830 /* for debuging on x86 only */
13831 /* #define BREAKPOINT() asm(" int $3"); */
13833 -/* use the transmit hw checksum driver functionality */
13834 -#define USE_SK_TX_CHECKSUM
13836 -/* use the receive hw checksum driver functionality */
13837 -#define USE_SK_RX_CHECKSUM
13839 -/* use the scatter-gather functionality with sendfile() */
13840 -#define SK_ZEROCOPY
13842 -/* use of a transmit complete interrupt */
13843 -#define USE_TX_COMPLETE
13846 - * threshold for copying small receive frames
13847 - * set to 0 to avoid copying, set to 9001 to copy all frames
13849 -#define SK_COPY_THRESHOLD 50
13851 -/* number of adapters that can be configured via command line params */
13852 -#define SK_MAX_CARD_PARAM 16
13857 - * use those defines for a compile-in version of the driver instead
13858 - * of command line parameters
13860 -// #define LINK_SPEED_A {"Auto", }
13861 -// #define LINK_SPEED_B {"Auto", }
13862 -// #define AUTO_NEG_A {"Sense", }
13863 -// #define AUTO_NEG_B {"Sense", }
13864 -// #define DUP_CAP_A {"Both", }
13865 -// #define DUP_CAP_B {"Both", }
13866 -// #define FLOW_CTRL_A {"SymOrRem", }
13867 -// #define FLOW_CTRL_B {"SymOrRem", }
13868 -// #define ROLE_A {"Auto", }
13869 -// #define ROLE_B {"Auto", }
13870 -// #define PREF_PORT {"A", }
13871 -// #define CON_TYPE {"Auto", }
13872 -// #define RLMT_MODE {"CheckLinkState", }
13874 -#define DEV_KFREE_SKB(skb) dev_kfree_skb(skb)
13875 -#define DEV_KFREE_SKB_IRQ(skb) dev_kfree_skb_irq(skb)
13876 -#define DEV_KFREE_SKB_ANY(skb) dev_kfree_skb_any(skb)
13879 /* Set blink mode*/
13880 #define OEM_CONFIG_VALUE ( SK_ACT_LED_BLINK | \
13881 SK_DUP_LED_NORMAL | \
13885 -/* Isr return value */
13886 -#define SkIsrRetVar irqreturn_t
13887 -#define SkIsrRetNone IRQ_NONE
13888 -#define SkIsrRetHandled IRQ_HANDLED
13889 +#define CLEAR_AND_START_RX(Port) SK_OUT8(pAC->IoBase, RxQueueAddr[(Port)]+Q_CSR, CSR_START | CSR_IRQ_CL_F)
13890 +#define START_RX(Port) SK_OUT8(pAC->IoBase, RxQueueAddr[(Port)]+Q_CSR, CSR_START)
13891 +#define CLEAR_TX_IRQ(Port,Prio) SK_OUT8(pAC->IoBase, TxQueueAddr[(Port)][(Prio)]+Q_CSR, CSR_IRQ_CL_F)
13894 /*******************************************************************************
13895 @@ -190,12 +105,25 @@
13897 ******************************************************************************/
13899 +static int __devinit sk98lin_init_device(struct pci_dev *pdev, const struct pci_device_id *ent);
13900 +static void sk98lin_remove_device(struct pci_dev *pdev);
13902 +static int sk98lin_suspend(struct pci_dev *pdev, u32 state);
13903 +static int sk98lin_resume(struct pci_dev *pdev);
13904 +static void SkEnableWOMagicPacket(SK_AC *pAC, SK_IOC IoC, SK_MAC_ADDR MacAddr);
13906 +#ifdef Y2_RECOVERY
13907 +static void SkGeHandleKernelTimer(unsigned long ptr);
13908 +void SkGeCheckTimer(DEV_NET *pNet);
13909 +static SK_BOOL CheckRXCounters(DEV_NET *pNet);
13910 +static void CheckRxPath(DEV_NET *pNet);
13912 static void FreeResources(struct SK_NET_DEVICE *dev);
13913 static int SkGeBoardInit(struct SK_NET_DEVICE *dev, SK_AC *pAC);
13914 static SK_BOOL BoardAllocMem(SK_AC *pAC);
13915 static void BoardFreeMem(SK_AC *pAC);
13916 static void BoardInitMem(SK_AC *pAC);
13917 -static void SetupRing(SK_AC*, void*, uintptr_t, RXD**, RXD**, RXD**, int*, SK_BOOL);
13918 +static void SetupRing(SK_AC*, void*, uintptr_t, RXD**, RXD**, RXD**, int*, int*, SK_BOOL);
13919 static SkIsrRetVar SkGeIsr(int irq, void *dev_id);
13920 static SkIsrRetVar SkGeIsrOnePort(int irq, void *dev_id);
13921 static int SkGeOpen(struct SK_NET_DEVICE *dev);
13922 @@ -206,39 +134,76 @@
13923 static struct net_device_stats *SkGeStats(struct SK_NET_DEVICE *dev);
13924 static int SkGeIoctl(struct SK_NET_DEVICE *dev, struct ifreq *rq, int cmd);
13925 static void GetConfiguration(SK_AC*);
13926 +static void ProductStr(SK_AC*);
13927 static int XmitFrame(SK_AC*, TX_PORT*, struct sk_buff*);
13928 static void FreeTxDescriptors(SK_AC*pAC, TX_PORT*);
13929 static void FillRxRing(SK_AC*, RX_PORT*);
13930 static SK_BOOL FillRxDescriptor(SK_AC*, RX_PORT*);
13931 +#ifdef CONFIG_SK98LIN_NAPI
13932 +static int SkGePoll(struct net_device *dev, int *budget);
13933 +static void ReceiveIrq(SK_AC*, RX_PORT*, SK_BOOL, int*, int);
13935 static void ReceiveIrq(SK_AC*, RX_PORT*, SK_BOOL);
13936 -static void ClearAndStartRx(SK_AC*, int);
13937 -static void ClearTxIrq(SK_AC*, int, int);
13939 +#ifdef SK_POLL_CONTROLLER
13940 +static void SkGeNetPoll(struct SK_NET_DEVICE *dev);
13942 static void ClearRxRing(SK_AC*, RX_PORT*);
13943 static void ClearTxRing(SK_AC*, TX_PORT*);
13944 static int SkGeChangeMtu(struct SK_NET_DEVICE *dev, int new_mtu);
13945 static void PortReInitBmu(SK_AC*, int);
13946 static int SkGeIocMib(DEV_NET*, unsigned int, int);
13947 static int SkGeInitPCI(SK_AC *pAC);
13948 -static void StartDrvCleanupTimer(SK_AC *pAC);
13949 -static void StopDrvCleanupTimer(SK_AC *pAC);
13950 -static int XmitFrameSG(SK_AC*, TX_PORT*, struct sk_buff*);
13952 -#ifdef SK_DIAG_SUPPORT
13953 static SK_U32 ParseDeviceNbrFromSlotName(const char *SlotName);
13954 static int SkDrvInitAdapter(SK_AC *pAC, int devNbr);
13955 static int SkDrvDeInitAdapter(SK_AC *pAC, int devNbr);
13957 +extern void SkLocalEventQueue( SK_AC *pAC,
13963 +extern void SkLocalEventQueue64( SK_AC *pAC,
13969 +static int XmitFrameSG(SK_AC*, TX_PORT*, struct sk_buff*);
13971 /*******************************************************************************
13973 * Extern Function Prototypes
13975 ******************************************************************************/
13977 +extern SK_BOOL SkY2AllocateResources(SK_AC *pAC);
13978 +extern void SkY2FreeResources(SK_AC *pAC);
13979 +extern void SkY2AllocateRxBuffers(SK_AC *pAC,SK_IOC IoC,int Port);
13980 +extern void SkY2FreeRxBuffers(SK_AC *pAC,SK_IOC IoC,int Port);
13981 +extern void SkY2FreeTxBuffers(SK_AC *pAC,SK_IOC IoC,int Port);
13982 +extern SkIsrRetVar SkY2Isr(int irq,void *dev_id /*,struct pt_regs *ptregs*/ );
13983 +extern int SkY2Xmit(struct sk_buff *skb,struct SK_NET_DEVICE *dev);
13984 +extern void SkY2PortStop(SK_AC *pAC,SK_IOC IoC,int Port,int Dir,int RstMode);
13985 +extern void SkY2PortStart(SK_AC *pAC,SK_IOC IoC,int Port);
13986 +extern int SkY2RlmtSend(SK_AC *pAC,int PortNr,struct sk_buff *pMessage);
13987 +extern void SkY2RestartStatusUnit(SK_AC *pAC);
13988 +extern void FillReceiveTableYukon2(SK_AC *pAC,SK_IOC IoC,int Port);
13989 +#ifdef CONFIG_SK98LIN_NAPI
13990 +extern int SkY2Poll(struct net_device *dev, int *budget);
13993 extern void SkDimEnableModerationIfNeeded(SK_AC *pAC);
13994 -extern void SkDimDisplayModerationSettings(SK_AC *pAC);
13995 extern void SkDimStartModerationTimer(SK_AC *pAC);
13996 extern void SkDimModerate(SK_AC *pAC);
13997 -extern void SkGeBlinkTimer(unsigned long data);
13999 +extern int SkEthIoctl(struct net_device *netdev, struct ifreq *ifr);
14001 +#ifdef CONFIG_PROC_FS
14002 +static const char SK_Root_Dir_entry[] = "sk98lin";
14003 +static struct proc_dir_entry *pSkRootDir;
14004 +extern struct file_operations sk_proc_fops;
14008 static void DumpMsg(struct sk_buff*, char*);
14009 @@ -247,33 +212,454 @@
14012 /* global variables *********************************************************/
14013 +static const char *BootString = BOOT_STRING;
14014 +struct SK_NET_DEVICE *SkGeRootDev = NULL;
14015 static SK_BOOL DoPrintInterfaceChange = SK_TRUE;
14016 -extern const struct ethtool_ops SkGeEthtoolOps;
14018 /* local variables **********************************************************/
14019 static uintptr_t TxQueueAddr[SK_MAX_MACS][2] = {{0x680, 0x600},{0x780, 0x700}};
14020 static uintptr_t RxQueueAddr[SK_MAX_MACS] = {0x400, 0x480};
14021 +static int sk98lin_max_boards_found = 0;
14023 +#ifdef CONFIG_PROC_FS
14024 +static struct proc_dir_entry *pSkRootDir;
14029 +static struct pci_device_id sk98lin_pci_tbl[] __devinitdata = {
14030 +/* { pci_vendor_id, pci_device_id, * SAMPLE ENTRY! *
14031 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, */
14032 + { 0x10b7, 0x1700, /* 3Com (10b7), Gigabit Ethernet Adapter */
14033 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14034 + { 0x10b7, 0x80eb, /* 3Com (10b7), 3Com 3C940B Gigabit LOM Ethernet Adapter */
14035 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14036 + { 0x1148, 0x4300, /* SysKonnect (1148), SK-98xx Gigabit Ethernet Server Adapter */
14037 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14038 + { 0x1148, 0x4320, /* SysKonnect (1148), SK-98xx V2.0 Gigabit Ethernet Adapter */
14039 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14040 + { 0x1148, 0x9000, /* SysKonnect (1148), SK-9Sxx 10/100/1000Base-T Server Adapter */
14041 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14042 + { 0x1148, 0x9E00, /* SysKonnect (1148), SK-9Exx 10/100/1000Base-T Adapter */
14043 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14044 + { 0x1186, 0x4001, /* D-Link (1186), Gigabit Ethernet Adapter */
14045 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14046 + { 0x1186, 0x4b00, /* D-Link (1186), Gigabit Ethernet Adapter */
14047 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14048 + { 0x1186, 0x4b01, /* D-Link (1186), Gigabit Ethernet Adapter */
14049 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14050 + { 0x1186, 0x4b02, /* D-Link (1186), Gigabit Ethernet Adapter */
14051 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14052 + { 0x1186, 0x4c00, /* D-Link (1186), Gigabit Ethernet Adapter */
14053 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14054 + { 0x11ab, 0x4320, /* Marvell (11ab), Gigabit Ethernet Controller */
14055 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14056 + { 0x11ab, 0x4340, /* Marvell (11ab), Gigabit Ethernet Controller */
14057 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14058 + { 0x11ab, 0x4341, /* Marvell (11ab), Gigabit Ethernet Controller */
14059 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14060 + { 0x11ab, 0x4342, /* Marvell (11ab), Gigabit Ethernet Controller */
14061 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14062 + { 0x11ab, 0x4343, /* Marvell (11ab), Gigabit Ethernet Controller */
14063 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14064 + { 0x11ab, 0x4344, /* Marvell (11ab), Gigabit Ethernet Controller */
14065 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14066 + { 0x11ab, 0x4345, /* Marvell (11ab), Gigabit Ethernet Controller */
14067 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14068 + { 0x11ab, 0x4346, /* Marvell (11ab), Gigabit Ethernet Controller */
14069 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14070 + { 0x11ab, 0x4347, /* Marvell (11ab), Gigabit Ethernet Controller */
14071 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14072 + { 0x11ab, 0x4350, /* Marvell (11ab), Fast Ethernet Controller */
14073 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14074 + { 0x11ab, 0x4351, /* Marvell (11ab), Fast Ethernet Controller */
14075 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14076 + { 0x11ab, 0x4352, /* Marvell (11ab), Fast Ethernet Controller */
14077 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14078 + { 0x11ab, 0x4353, /* Marvell (11ab), Fast Ethernet Controller */
14079 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14080 + { 0x11ab, 0x4356, /* Marvell (11ab), Gigabit Ethernet Controller */
14081 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14082 + { 0x11ab, 0x4360, /* Marvell (11ab), Gigabit Ethernet Controller */
14083 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14084 + { 0x11ab, 0x4361, /* Marvell (11ab), Gigabit Ethernet Controller */
14085 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14086 + { 0x11ab, 0x4362, /* Marvell (11ab), Gigabit Ethernet Controller */
14087 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14088 + { 0x11ab, 0x4363, /* Marvell (11ab), Marvell */
14089 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14090 + { 0x11ab, 0x4364, /* Marvell (11ab), Gigabit Ethernet Controller */
14091 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14092 + { 0x11ab, 0x4366, /* Marvell (11ab), Gigabit Ethernet Controller */
14093 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14094 + { 0x11ab, 0x4367, /* Marvell (11ab), Gigabit Ethernet Controller */
14095 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14096 + { 0x11ab, 0x4368, /* Marvell (11ab), Gigabit Ethernet Controller */
14097 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14098 + { 0x11ab, 0x4369, /* Marvell (11ab), Gigabit Ethernet Controller */
14099 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14100 + { 0x11ab, 0x5005, /* Marvell (11ab), Belkin */
14101 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14102 + { 0x1371, 0x434e, /* CNet (1371), GigaCard Network Adapter */
14103 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14104 + { 0x1737, 0x1032, /* Linksys (1737), Gigabit Network Adapter */
14105 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14106 + { 0x1737, 0x1064, /* Linksys (1737), Gigabit Network Adapter */
14107 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14111 +MODULE_DEVICE_TABLE(pci, sk98lin_pci_tbl);
14113 +static struct pci_driver sk98lin_driver = {
14114 + .name = DRIVER_FILE_NAME,
14115 + .id_table = sk98lin_pci_tbl,
14116 + .probe = sk98lin_init_device,
14117 + .remove = __devexit_p(sk98lin_remove_device),
14119 + .suspend = sk98lin_suspend,
14120 + .resume = sk98lin_resume
14125 /*****************************************************************************
14127 - * SkPciWriteCfgDWord - write a 32 bit value to pci config space
14128 + * sk98lin_init_device - initialize the adapter
14131 - * This routine writes a 32 bit value to the pci configuration
14133 + * This function initializes the adapter. Resources for
14134 + * the adapter are allocated and the adapter is brought into Init 1
14138 - * 0 - indicate everything worked ok.
14139 - * != 0 - error indication
14140 + * 0, if everything is ok
14143 -static inline int SkPciWriteCfgDWord(
14144 -SK_AC *pAC, /* Adapter Control structure pointer */
14145 -int PciAddr, /* PCI register address */
14146 -SK_U32 Val) /* pointer to store the read value */
14147 +static int __devinit sk98lin_init_device(struct pci_dev *pdev,
14148 + const struct pci_device_id *ent)
14151 - pci_write_config_dword(pAC->PciDev, PciAddr, Val);
14153 -} /* SkPciWriteCfgDWord */
14154 + static SK_BOOL sk98lin_boot_string = SK_FALSE;
14155 + static SK_BOOL sk98lin_proc_entry = SK_FALSE;
14156 + static int sk98lin_boards_found = 0;
14158 + DEV_NET *pNet = NULL;
14159 + struct SK_NET_DEVICE *dev = NULL;
14161 +#ifdef CONFIG_PROC_FS
14162 + struct proc_dir_entry *pProcFile;
14164 + int pci_using_dac;
14166 + retval = pci_enable_device(pdev);
14168 + printk(KERN_ERR "Cannot enable PCI device, "
14177 + /* INSERT * We have to find the power-management capabilities */
14178 + /* Find power-management capability. */
14180 + pci_using_dac = 0; /* Set 32 bit DMA per default */
14181 + /* Configure DMA attributes. */
14182 + retval = pci_set_dma_mask(pdev, (u64) 0xffffffffffffffffULL);
14184 + pci_using_dac = 1;
14186 + retval = pci_set_dma_mask(pdev, (u64) 0xffffffff);
14188 + printk(KERN_ERR "No usable DMA configuration, "
14195 + if ((dev = alloc_etherdev(sizeof(DEV_NET))) == NULL) {
14196 + printk(KERN_ERR "Unable to allocate etherdev "
14201 + pNet = dev->priv;
14202 + pNet->pAC = kmalloc(sizeof(SK_AC), GFP_KERNEL);
14203 + if (pNet->pAC == NULL){
14204 + free_netdev(dev);
14205 + printk(KERN_ERR "Unable to allocate adapter "
14211 + /* Print message */
14212 + if (!sk98lin_boot_string) {
14213 + /* set display flag to TRUE so that */
14214 + /* we only display this string ONCE */
14215 + sk98lin_boot_string = SK_TRUE;
14216 + printk("%s\n", BootString);
14219 + memset(pNet->pAC, 0, sizeof(SK_AC));
14221 + pAC->PciDev = pdev;
14222 + pAC->PciDevId = pdev->device;
14223 + pAC->dev[0] = dev;
14224 + pAC->dev[1] = dev;
14225 + sprintf(pAC->Name, "SysKonnect SK-98xx");
14226 + pAC->CheckQueue = SK_FALSE;
14228 + dev->irq = pdev->irq;
14229 + retval = SkGeInitPCI(pAC);
14231 + printk("SKGE: PCI setup failed: %i\n", retval);
14232 + free_netdev(dev);
14236 + SET_MODULE_OWNER(dev);
14238 + dev->open = &SkGeOpen;
14239 + dev->stop = &SkGeClose;
14240 + dev->get_stats = &SkGeStats;
14241 + dev->set_multicast_list = &SkGeSetRxMode;
14242 + dev->set_mac_address = &SkGeSetMacAddr;
14243 + dev->do_ioctl = &SkGeIoctl;
14244 + dev->change_mtu = &SkGeChangeMtu;
14245 + dev->flags &= ~IFF_RUNNING;
14246 +#ifdef SK_POLL_CONTROLLER
14247 + dev->poll_controller = SkGeNetPoll;
14249 + SET_NETDEV_DEV(dev, &pdev->dev);
14251 + pAC->Index = sk98lin_boards_found;
14253 + if (SkGeBoardInit(dev, pAC)) {
14254 + free_netdev(dev);
14260 + if (pci_using_dac)
14261 + dev->features |= NETIF_F_HIGHDMA;
14263 + /* shifter to later moment in time... */
14264 + if (CHIP_ID_YUKON_2(pAC)) {
14265 + dev->hard_start_xmit = &SkY2Xmit;
14266 +#ifdef CONFIG_SK98LIN_NAPI
14267 + dev->poll = &SkY2Poll;
14268 + dev->weight = 64;
14271 + dev->hard_start_xmit = &SkGeXmit;
14272 +#ifdef CONFIG_SK98LIN_NAPI
14273 + dev->poll = &SkGePoll;
14274 + dev->weight = 64;
14278 +#ifdef NETIF_F_TSO
14279 +#ifdef USE_SK_TSO_FEATURE
14280 + if ((CHIP_ID_YUKON_2(pAC)) &&
14281 + (pAC->GIni.GIChipId != CHIP_ID_YUKON_EC_U)) {
14282 + dev->features |= NETIF_F_TSO;
14286 +#ifdef CONFIG_SK98LIN_ZEROCOPY
14287 + if (pAC->GIni.GIChipId != CHIP_ID_GENESIS)
14288 + dev->features |= NETIF_F_SG;
14290 +#ifdef USE_SK_TX_CHECKSUM
14291 + if (pAC->GIni.GIChipId != CHIP_ID_GENESIS)
14292 + dev->features |= NETIF_F_IP_CSUM;
14294 +#ifdef USE_SK_RX_CHECKSUM
14295 + pAC->RxPort[0].UseRxCsum = SK_TRUE;
14296 + if (pAC->GIni.GIMacsFound == 2 ) {
14297 + pAC->RxPort[1].UseRxCsum = SK_TRUE;
14301 + /* Save the hardware revision */
14302 + pAC->HWRevision = (((pAC->GIni.GIPciHwRev >> 4) & 0x0F)*10) +
14303 + (pAC->GIni.GIPciHwRev & 0x0F);
14305 + /* Set driver globals */
14306 + pAC->Pnmi.pDriverFileName = DRIVER_FILE_NAME;
14307 + pAC->Pnmi.pDriverReleaseDate = DRIVER_REL_DATE;
14309 + SK_MEMSET(&(pAC->PnmiBackup), 0, sizeof(SK_PNMI_STRUCT_DATA));
14310 + SK_MEMCPY(&(pAC->PnmiBackup), &(pAC->PnmiStruct),
14311 + sizeof(SK_PNMI_STRUCT_DATA));
14313 + /* Register net device */
14314 + retval = register_netdev(dev);
14316 + printk(KERN_ERR "SKGE: Could not register device.\n");
14317 + FreeResources(dev);
14318 + free_netdev(dev);
14322 + /* Save initial device name */
14323 + strcpy(pNet->InitialDevName, dev->name);
14325 + /* Set network to off */
14326 + netif_stop_queue(dev);
14327 + netif_carrier_off(dev);
14329 + /* Print adapter specific string from vpd and config settings */
14330 + printk("%s: %s\n", pNet->InitialDevName, pAC->DeviceStr);
14331 + printk(" PrefPort:%c RlmtMode:%s\n",
14332 + 'A' + pAC->Rlmt.Net[0].Port[pAC->Rlmt.Net[0].PrefPort]->PortNumber,
14333 + (pAC->RlmtMode==0) ? "Check Link State" :
14334 + ((pAC->RlmtMode==1) ? "Check Link State" :
14335 + ((pAC->RlmtMode==3) ? "Check Local Port" :
14336 + ((pAC->RlmtMode==7) ? "Check Segmentation" :
14337 + ((pAC->RlmtMode==17) ? "Dual Check Link State" :"Error")))));
14339 + SkGeYellowLED(pAC, pAC->IoBase, 1);
14341 + memcpy((caddr_t) &dev->dev_addr,
14342 + (caddr_t) &pAC->Addr.Net[0].CurrentMacAddress, 6);
14344 + /* First adapter... Create proc and print message */
14345 +#ifdef CONFIG_PROC_FS
14346 + if (!sk98lin_proc_entry) {
14347 + sk98lin_proc_entry = SK_TRUE;
14348 + SK_MEMCPY(&SK_Root_Dir_entry, BootString,
14349 + sizeof(SK_Root_Dir_entry) - 1);
14351 + /*Create proc (directory)*/
14352 + if(!pSkRootDir) {
14353 + pSkRootDir = proc_mkdir(SK_Root_Dir_entry, proc_net);
14354 + if (!pSkRootDir) {
14355 + printk(KERN_WARNING "%s: Unable to create /proc/net/%s",
14356 + dev->name, SK_Root_Dir_entry);
14358 + pSkRootDir->owner = THIS_MODULE;
14363 + /* Create proc file */
14364 + if (pSkRootDir &&
14365 + (pProcFile = create_proc_entry(pNet->InitialDevName, S_IRUGO,
14367 + pProcFile->proc_fops = &sk_proc_fops;
14368 + pProcFile->data = dev;
14373 + pNet->PortNr = 0;
14376 + sk98lin_boards_found++;
14377 + pci_set_drvdata(pdev, dev);
14379 + /* More then one port found */
14380 + if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
14381 + if ((dev = alloc_etherdev(sizeof(DEV_NET))) == 0) {
14382 + printk(KERN_ERR "Unable to allocate etherdev "
14387 + pAC->dev[1] = dev;
14388 + pNet = dev->priv;
14389 + pNet->PortNr = 1;
14393 + if (CHIP_ID_YUKON_2(pAC)) {
14394 + dev->hard_start_xmit = &SkY2Xmit;
14395 +#ifdef CONFIG_SK98LIN_NAPI
14396 + dev->poll = &SkY2Poll;
14397 + dev->weight = 64;
14400 + dev->hard_start_xmit = &SkGeXmit;
14401 +#ifdef CONFIG_SK98LIN_NAPI
14402 + dev->poll = &SkGePoll;
14403 + dev->weight = 64;
14406 + dev->open = &SkGeOpen;
14407 + dev->stop = &SkGeClose;
14408 + dev->get_stats = &SkGeStats;
14409 + dev->set_multicast_list = &SkGeSetRxMode;
14410 + dev->set_mac_address = &SkGeSetMacAddr;
14411 + dev->do_ioctl = &SkGeIoctl;
14412 + dev->change_mtu = &SkGeChangeMtu;
14413 + dev->flags &= ~IFF_RUNNING;
14414 +#ifdef SK_POLL_CONTROLLER
14415 + dev->poll_controller = SkGeNetPoll;
14418 +#ifdef NETIF_F_TSO
14419 +#ifdef USE_SK_TSO_FEATURE
14420 + if ((CHIP_ID_YUKON_2(pAC)) &&
14421 + (pAC->GIni.GIChipId != CHIP_ID_YUKON_EC_U)) {
14422 + dev->features |= NETIF_F_TSO;
14426 +#ifdef CONFIG_SK98LIN_ZEROCOPY
14427 + /* Don't handle if Genesis chipset */
14428 + if (pAC->GIni.GIChipId != CHIP_ID_GENESIS)
14429 + dev->features |= NETIF_F_SG;
14431 +#ifdef USE_SK_TX_CHECKSUM
14432 + /* Don't handle if Genesis chipset */
14433 + if (pAC->GIni.GIChipId != CHIP_ID_GENESIS)
14434 + dev->features |= NETIF_F_IP_CSUM;
14437 + if (register_netdev(dev)) {
14438 + printk(KERN_ERR "SKGE: Could not register device.\n");
14439 + free_netdev(dev);
14440 + pAC->dev[1] = pAC->dev[0];
14443 + /* Save initial device name */
14444 + strcpy(pNet->InitialDevName, dev->name);
14446 + /* Set network to off */
14447 + netif_stop_queue(dev);
14448 + netif_carrier_off(dev);
14451 +#ifdef CONFIG_PROC_FS
14453 + && (pProcFile = create_proc_entry(pNet->InitialDevName,
14454 + S_IRUGO, pSkRootDir))) {
14455 + pProcFile->proc_fops = &sk_proc_fops;
14456 + pProcFile->data = dev;
14460 + memcpy((caddr_t) &dev->dev_addr,
14461 + (caddr_t) &pAC->Addr.Net[1].CurrentMacAddress, 6);
14463 + printk("%s: %s\n", pNet->InitialDevName, pAC->DeviceStr);
14464 + printk(" PrefPort:B RlmtMode:Dual Check Link State\n");
14468 + pAC->Index = sk98lin_boards_found;
14469 + sk98lin_max_boards_found = sk98lin_boards_found;
14475 /*****************************************************************************
14477 @@ -282,22 +668,26 @@
14479 * This function initialize the PCI resources and IO
14482 - * 0 - indicate everything worked ok.
14483 - * != 0 - error indication
14487 -static __devinit int SkGeInitPCI(SK_AC *pAC)
14488 +static int SkGeInitPCI(SK_AC *pAC)
14490 struct SK_NET_DEVICE *dev = pAC->dev[0];
14491 struct pci_dev *pdev = pAC->PciDev;
14494 + if (pci_enable_device(pdev) != 0) {
14498 dev->mem_start = pci_resource_start (pdev, 0);
14499 pci_set_master(pdev);
14501 - retval = pci_request_regions(pdev, "sk98lin");
14504 + if (pci_request_regions(pdev, DRIVER_FILE_NAME) != 0) {
14506 + goto out_disable;
14509 #ifdef SK_BIG_ENDIAN
14511 @@ -315,9 +705,10 @@
14513 * Remap the regs into kernel space.
14515 - pAC->IoBase = ioremap_nocache(dev->mem_start, 0x4000);
14516 - if (!pAC->IoBase) {
14518 + pAC->IoBase = (char*)ioremap_nocache(dev->mem_start, 0x4000);
14520 + if (!pAC->IoBase){
14525 @@ -325,10 +716,476 @@
14528 pci_release_regions(pdev);
14531 + pci_disable_device(pdev);
14535 +#ifdef Y2_RECOVERY
14536 +/*****************************************************************************
14538 + * SkGeHandleKernelTimer - Handle the kernel timer requests
14541 + * If the requested time interval for the timer has elapsed,
14542 + * this function checks the link state.
14547 +static void SkGeHandleKernelTimer(
14548 +unsigned long ptr) /* holds the pointer to adapter control context */
14550 + DEV_NET *pNet = (DEV_NET*) ptr;
14551 + SkGeCheckTimer(pNet);
14554 +/*****************************************************************************
14556 + * sk98lin_check_timer - Resume the the card
14559 + * This function checks the kernel timer
14564 +void SkGeCheckTimer(
14565 +DEV_NET *pNet) /* holds the pointer to adapter control context */
14567 + SK_AC *pAC = pNet->pAC;
14568 + SK_BOOL StartTimer = SK_TRUE;
14570 + if (pNet->InRecover)
14572 + if (pNet->TimerExpired)
14574 + pNet->TimerExpired = SK_TRUE;
14576 +#define TXPORT pAC->TxPort[pNet->PortNr][TX_PRIO_LOW]
14577 +#define RXPORT pAC->RxPort[pNet->PortNr]
14579 + if ( (CHIP_ID_YUKON_2(pAC)) &&
14580 + (netif_running(pAC->dev[pNet->PortNr]))) {
14582 +#ifdef Y2_RX_CHECK
14583 + if (HW_FEATURE(pAC, HWF_WA_DEV_4167)) {
14584 + /* Checks the RX path */
14585 + CheckRxPath(pNet);
14589 + /* Checkthe transmitter */
14590 + if (!(IS_Q_EMPTY(&TXPORT.TxAQ_working))) {
14591 + if (TXPORT.LastDone != TXPORT.TxALET.Done) {
14592 + TXPORT.LastDone = TXPORT.TxALET.Done;
14593 + pNet->TransmitTimeoutTimer = 0;
14595 + pNet->TransmitTimeoutTimer++;
14596 + if (pNet->TransmitTimeoutTimer >= 10) {
14597 + pNet->TransmitTimeoutTimer = 0;
14598 +#ifdef CHECK_TRANSMIT_TIMEOUT
14599 + StartTimer = SK_FALSE;
14600 + SkLocalEventQueue(pAC, SKGE_DRV,
14601 + SK_DRV_RECOVER,pNet->PortNr,-1,SK_FALSE);
14607 +#ifdef CHECK_TRANSMIT_TIMEOUT
14608 +// if (!timer_pending(&pNet->KernelTimer)) {
14609 + pNet->KernelTimer.expires = jiffies + (HZ/4); /* 100ms */
14610 + add_timer(&pNet->KernelTimer);
14611 + pNet->TimerExpired = SK_FALSE;
14618 +/*****************************************************************************
14620 +* CheckRXCounters - Checks the the statistics for RX path hang
14623 +* This function is called periodical by a timer.
14627 +* Function Parameters:
14633 +static SK_BOOL CheckRXCounters(
14634 +DEV_NET *pNet) /* holds the pointer to adapter control context */
14636 + SK_AC *pAC = pNet->pAC;
14637 + SK_BOOL bStatus = SK_FALSE;
14639 + /* Variable used to store the MAC RX FIFO RP, RPLev*/
14640 + SK_U32 MACFifoRP = 0;
14641 + SK_U32 MACFifoRLev = 0;
14643 + /* Variable used to store the PCI RX FIFO RP, RPLev*/
14644 + SK_U32 RXFifoRP = 0;
14645 + SK_U8 RXFifoRLev = 0;
14647 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
14648 + ("==> CheckRXCounters()\n"));
14650 + /*Check if statistic counters hangs*/
14651 + if (pNet->LastJiffies == pAC->dev[pNet->PortNr]->last_rx) {
14652 + /* Now read the values of read pointer/level from MAC RX FIFO again */
14653 + SK_IN32(pAC->IoBase, MR_ADDR(pNet->PortNr, RX_GMF_RP), &MACFifoRP);
14654 + SK_IN32(pAC->IoBase, MR_ADDR(pNet->PortNr, RX_GMF_RLEV), &MACFifoRLev);
14656 + /* Now read the values of read pointer/level from RX FIFO again */
14657 + SK_IN8(pAC->IoBase, Q_ADDR(pAC->GIni.GP[pNet->PortNr].PRxQOff, Q_RX_RP), &RXFifoRP);
14658 + SK_IN8(pAC->IoBase, Q_ADDR(pAC->GIni.GP[pNet->PortNr].PRxQOff, Q_RX_RL), &RXFifoRLev);
14660 + /* Check if the MAC RX hang */
14661 + if ((MACFifoRP == pNet->PreviousMACFifoRP) &&
14662 + (pNet->PreviousMACFifoRP != 0) &&
14663 + (MACFifoRLev >= pNet->PreviousMACFifoRLev)){
14664 + bStatus = SK_TRUE;
14667 + /* Check if the PCI RX hang */
14668 + if ((RXFifoRP == pNet->PreviousRXFifoRP) &&
14669 + (pNet->PreviousRXFifoRP != 0) &&
14670 + (RXFifoRLev >= pNet->PreviousRXFifoRLev)){
14671 + /*Set the flag to indicate that the RX FIFO hangs*/
14672 + bStatus = SK_TRUE;
14676 + /* Store now the values of counters for next check */
14677 + pNet->LastJiffies = pAC->dev[pNet->PortNr]->last_rx;
14679 + /* Store the values of read pointer/level from MAC RX FIFO for next test */
14680 + pNet->PreviousMACFifoRP = MACFifoRP;
14681 + pNet->PreviousMACFifoRLev = MACFifoRLev;
14683 + /* Store the values of read pointer/level from RX FIFO for next test */
14684 + pNet->PreviousRXFifoRP = RXFifoRP;
14685 + pNet->PreviousRXFifoRLev = RXFifoRLev;
14687 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
14688 + ("<== CheckRXCounters()\n"));
14693 +/*****************************************************************************
14695 +* CheckRxPath - Checks if the RX path
14698 +* This function is called periodical by a timer.
14702 +* Function Parameters:
14708 +static void CheckRxPath(
14709 +DEV_NET *pNet) /* holds the pointer to adapter control context */
14711 + unsigned long Flags; /* for the spin locks */
14712 + /* Initialize the pAC structure.*/
14713 + SK_AC *pAC = pNet->pAC;
14715 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
14716 + ("==> CheckRxPath()\n"));
14718 + /*If the statistics are not changed then could be an RX problem */
14719 + if (CheckRXCounters(pNet)){
14721 + * First we try the simple solution by resetting the Level Timer
14724 + /* Stop Level Timer of Status BMU */
14725 + SK_OUT8(pAC->IoBase, STAT_LEV_TIMER_CTRL, TIM_STOP);
14727 + /* Start Level Timer of Status BMU */
14728 + SK_OUT8(pAC->IoBase, STAT_LEV_TIMER_CTRL, TIM_START);
14730 + if (!CheckRXCounters(pNet)) {
14734 + spin_lock_irqsave(&pAC->SlowPathLock, Flags);
14735 + SkLocalEventQueue(pAC, SKGE_DRV,
14736 + SK_DRV_RECOVER,pNet->PortNr,-1,SK_TRUE);
14738 + /* Reset the fifo counters */
14739 + pNet->PreviousMACFifoRP = 0;
14740 + pNet->PreviousMACFifoRLev = 0;
14741 + pNet->PreviousRXFifoRP = 0;
14742 + pNet->PreviousRXFifoRLev = 0;
14744 + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
14747 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
14748 + ("<== CheckRxPath()\n"));
14757 +/*****************************************************************************
14759 + * sk98lin_resume - Resume the the card
14762 + * This function resumes the card into the D0 state
14767 +static int sk98lin_resume(
14768 +struct pci_dev *pdev) /* the device that is to resume */
14770 + struct net_device *dev = pci_get_drvdata(pdev);
14771 + DEV_NET *pNet = (DEV_NET*) dev->priv;
14772 + SK_AC *pAC = pNet->pAC;
14775 + /* Set the power state to D0 */
14776 + pci_set_power_state(pdev, 0);
14777 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
14778 + pci_restore_state(pdev);
14780 + pci_restore_state(pdev, pAC->PciState);
14783 + pci_enable_device(pdev);
14784 + pci_set_master(pdev);
14786 + pci_enable_wake(pdev, 3, 0);
14787 + pci_enable_wake(pdev, 4, 0);
14789 + SK_OUT8(pAC->IoBase, RX_GMF_CTRL_T, (SK_U8)GMF_RST_CLR);
14791 + /* Set the adapter power state to D0 */
14792 + SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);
14793 + PmCtlSts &= ~(PCI_PM_STATE_D3); /* reset all DState bits */
14794 + PmCtlSts |= PCI_PM_STATE_D0;
14795 + SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PmCtlSts);
14797 + /* Reinit the adapter and start the port again */
14798 + pAC->BoardLevel = SK_INIT_DATA;
14799 + SkDrvLeaveDiagMode(pAC);
14801 + if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) ||
14802 + (CHIP_ID_YUKON_2(pAC)) ) {
14803 + pAC->StatusLETable.Done = 0;
14804 + pAC->StatusLETable.Put = 0;
14805 + pAC->StatusLETable.HwPut = 0;
14806 + SkGeY2InitStatBmu(pAC, pAC->IoBase, &pAC->StatusLETable);
14812 +/*****************************************************************************
14814 + * sk98lin_suspend - Suspend the card
14817 + * This function suspends the card into a defined state
14822 +static int sk98lin_suspend(
14823 +struct pci_dev *pdev, /* pointer to the device that is to suspend */
14824 +u32 state) /* what power state is desired by Linux? */
14826 + struct net_device *dev = pci_get_drvdata(pdev);
14827 + DEV_NET *pNet = (DEV_NET*) dev->priv;
14828 + SK_AC *pAC = pNet->pAC;
14829 + SK_U16 PciPMControlStatus;
14830 + SK_U16 PciPMCapabilities;
14831 + SK_MAC_ADDR MacAddr;
14834 + /* GEnesis and first yukon revs do not support power management */
14835 + if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {
14836 + if (pAC->GIni.GIChipRev == 0) {
14837 + return 0; /* power management not supported */
14841 + if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
14842 + return 0; /* not supported for this chipset */
14845 + if (pAC->WolInfo.ConfiguredWolOptions == 0) {
14846 + return 0; /* WOL possible, but disabled via ethtool */
14849 + if(netif_running(dev)) {
14850 + netif_stop_queue(dev); /* stop device if running */
14853 + /* read the PM control/status register from the PCI config space */
14854 + SK_IN16(pAC->IoBase, PCI_C(pAC, PCI_PM_CTL_STS), &PciPMControlStatus);
14856 + /* read the power management capabilities from the config space */
14857 + SK_IN16(pAC->IoBase, PCI_C(pAC, PCI_PM_CAP_REG), &PciPMCapabilities);
14859 + /* Enable WakeUp with Magic Packet - get MAC address from adapter */
14860 + for (i = 0; i < SK_MAC_ADDR_LEN; i++) {
14861 + /* virtual address: will be used for data */
14862 + SK_IN8(pAC->IoBase, (B2_MAC_1 + i), &MacAddr.a[i]);
14865 + SkDrvEnterDiagMode(pAC);
14866 + SkEnableWOMagicPacket(pAC, pAC->IoBase, MacAddr);
14868 + pci_enable_wake(pdev, 3, 1);
14869 + pci_enable_wake(pdev, 4, 1); /* 4 == D3 cold */
14870 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
14871 + pci_save_state(pdev);
14873 + pci_save_state(pdev, pAC->PciState);
14875 + pci_disable_device(pdev); // NEW
14876 + pci_set_power_state(pdev, state); /* set the state */
14882 +/******************************************************************************
14884 + * SkEnableWOMagicPacket - Enable Wake on Magic Packet on the adapter
14888 + * the adapter should be de-initialized before calling this function
14894 +static void SkEnableWOMagicPacket(
14895 +SK_AC *pAC, /* Adapter Control Context */
14896 +SK_IOC IoC, /* I/O control context */
14897 +SK_MAC_ADDR MacAddr) /* MacAddr expected in magic packet */
14905 + /* use Port 0 as long as we do not have any dual port cards which support WOL */
14909 + SK_OUT16(IoC, 0x0004, 0x0002); /* clear S/W Reset */
14910 + SK_OUT16(IoC, 0x0f10, 0x0002); /* clear Link Reset */
14913 + * PHY Configuration:
14914 + * Autonegotioation is enalbed, advertise 10 HD, 10 FD,
14915 + * 100 HD, and 100 FD.
14917 + if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) ||
14918 + (pAC->GIni.GIChipId == CHIP_ID_YUKON) ||
14919 + (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) ||
14920 + (CHIP_ID_YUKON_2(pAC)) ) {
14922 + SK_OUT8(IoC, 0x0007, 0xa9); /* enable VAUX */
14924 + /* WA code for COMA mode */
14925 + /* Only for yukon plus based chipsets rev A3 */
14926 + if (pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3) {
14927 + SK_IN32(IoC, B2_GP_IO, &DWord);
14928 + DWord |= GP_DIR_9; /* set to output */
14929 + DWord &= ~GP_IO_9; /* clear PHY reset (active high) */
14930 + SK_OUT32(IoC, B2_GP_IO, DWord); /* clear PHY reset */
14933 + if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) ||
14934 + (pAC->GIni.GIChipId == CHIP_ID_YUKON)) {
14935 + SK_OUT32(IoC, 0x0f04, 0x01f04001); /* set PHY reset */
14936 + SK_OUT32(IoC, 0x0f04, 0x01f04002); /* clear PHY reset */
14938 + SK_OUT8(IoC, 0x0f04, 0x02); /* clear PHY reset */
14941 + SK_OUT8(IoC, 0x0f00, 0x02); /* clear MAC reset */
14942 + SkGmPhyWrite(pAC, IoC, Port, 4, 0x01e1); /* advertise 10/100 HD/FD */
14943 + SkGmPhyWrite(pAC, IoC, Port, 9, 0x0000); /* do not advertise 1000 HD/FD */
14944 + SkGmPhyWrite(pAC, IoC, Port, 00, 0xB300); /* 100 MBit, disable Autoneg */
14945 + } else if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) {
14946 + SK_OUT8(IoC, 0x0007, 0xa9); /* enable VAUX */
14947 + SK_OUT8(IoC, 0x0f04, 0x02); /* clear PHY reset */
14948 + SK_OUT8(IoC, 0x0f00, 0x02); /* clear MAC reset */
14949 + SkGmPhyWrite(pAC, IoC, Port, 16, 0x0130); /* Enable Automatic Crossover */
14950 + SkGmPhyWrite(pAC, IoC, Port, 00, 0xB300); /* 100 MBit, disable Autoneg */
14955 + * MAC Configuration:
14956 + * Set the MAC to 100 HD and enable the auto update features
14957 + * for Speed, Flow Control and Duplex Mode.
14958 + * If autonegotiation completes successfully the
14959 + * MAC takes the link parameters from the PHY.
14960 + * If the link partner doesn't support autonegotiation
14961 + * the MAC can receive magic packets if the link partner
14964 + SK_OUT16(IoC, 0x2804, 0x3832);
14968 + * Set Up Magic Packet parameters
14970 + for (i = 0; i < 6; i+=2) { /* set up magic packet MAC address */
14971 + SK_IN16(IoC, 0x100 + i, &Word);
14972 + SK_OUT16(IoC, 0xf24 + i, Word);
14975 + SK_OUT16(IoC, 0x0f20, 0x0208); /* enable PME on magic packet */
14976 + /* and on wake up frame */
14979 + * Set up PME generation
14981 + /* set PME legacy mode */
14982 + /* Only for PCI express based chipsets */
14983 + if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) ||
14984 + (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) ||
14985 + (CHIP_ID_YUKON_2(pAC))) {
14986 + SkPciReadCfgDWord(pAC, 0x40, &DWord);
14988 + SkPciWriteCfgDWord(pAC, 0x40, DWord);
14991 + SK_OUT8(IoC, RX_GMF_CTRL_T, (SK_U8)GMF_RST_SET);
14993 + /* clear PME status and switch adapter to DState */
14994 + SkPciReadCfgWord(pAC, 0x4c, &Word);
14996 + SkPciWriteCfgWord(pAC, 0x4c, Word);
14997 +} /* SkEnableWOMagicPacket */
15001 /*****************************************************************************
15003 @@ -347,20 +1204,24 @@
15007 - pNet = netdev_priv(dev);
15009 - AllocFlag = pAC->AllocFlag;
15010 - if (pAC->PciDev) {
15011 - pci_release_regions(pAC->PciDev);
15013 - if (AllocFlag & SK_ALLOC_IRQ) {
15014 - free_irq(dev->irq, dev);
15016 - if (pAC->IoBase) {
15017 - iounmap(pAC->IoBase);
15019 - if (pAC->pDescrMem) {
15020 - BoardFreeMem(pAC);
15022 + pNet = (DEV_NET*) dev->priv;
15024 + AllocFlag = pAC->AllocFlag;
15025 + if (pAC->PciDev) {
15026 + pci_release_regions(pAC->PciDev);
15028 + if (AllocFlag & SK_ALLOC_IRQ) {
15029 + free_irq(dev->irq, dev);
15031 + if (pAC->IoBase) {
15032 + iounmap(pAC->IoBase);
15034 + if (CHIP_ID_YUKON_2(pAC)) {
15035 + SkY2FreeResources(pAC);
15037 + BoardFreeMem(pAC);
15041 } /* FreeResources */
15042 @@ -369,6 +1230,7 @@
15043 MODULE_DESCRIPTION("SysKonnect SK-NET Gigabit Ethernet SK-98xx driver");
15044 MODULE_LICENSE("GPL");
15047 #ifdef LINK_SPEED_A
15048 static char *Speed_A[SK_MAX_CARD_PARAM] = LINK_SPEED;
15050 @@ -450,9 +1312,11 @@
15051 static int IntsPerSec[SK_MAX_CARD_PARAM];
15052 static char *Moderation[SK_MAX_CARD_PARAM];
15053 static char *ModerationMask[SK_MAX_CARD_PARAM];
15054 -static char *AutoSizing[SK_MAX_CARD_PARAM];
15055 -static char *Stats[SK_MAX_CARD_PARAM];
15057 +static char *LowLatency[SK_MAX_CARD_PARAM];
15058 +static char *BroadcastPrio[SK_MAX_CARD_PARAM];
15060 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
15061 module_param_array(Speed_A, charp, NULL, 0);
15062 module_param_array(Speed_B, charp, NULL, 0);
15063 module_param_array(AutoNeg_A, charp, NULL, 0);
15064 @@ -469,9 +1333,119 @@
15065 /* used for interrupt moderation */
15066 module_param_array(IntsPerSec, int, NULL, 0);
15067 module_param_array(Moderation, charp, NULL, 0);
15068 -module_param_array(Stats, charp, NULL, 0);
15069 module_param_array(ModerationMask, charp, NULL, 0);
15070 -module_param_array(AutoSizing, charp, NULL, 0);
15071 +module_param_array(LowLatency, charp, NULL, 0);
15072 +module_param_array(BroadcastPrio, charp, NULL, 0);
15074 +MODULE_PARM(Speed_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15075 +MODULE_PARM(Speed_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15076 +MODULE_PARM(AutoNeg_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15077 +MODULE_PARM(AutoNeg_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15078 +MODULE_PARM(DupCap_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15079 +MODULE_PARM(DupCap_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15080 +MODULE_PARM(FlowCtrl_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15081 +MODULE_PARM(FlowCtrl_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15082 +MODULE_PARM(Role_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15083 +MODULE_PARM(Role_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15084 +MODULE_PARM(ConType, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15085 +MODULE_PARM(PrefPort, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15086 +MODULE_PARM(RlmtMode, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15087 +MODULE_PARM(IntsPerSec, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "i");
15088 +MODULE_PARM(Moderation, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15089 +MODULE_PARM(ModerationMask, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15090 +MODULE_PARM(LowLatency, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15091 +MODULE_PARM(BroadcastPrio, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15095 +/*****************************************************************************
15097 + * sk98lin_remove_device - device deinit function
15100 + * Disable adapter if it is still running, free resources,
15101 + * free device struct.
15106 +static void sk98lin_remove_device(struct pci_dev *pdev)
15110 +struct SK_NET_DEVICE *next;
15111 +unsigned long Flags;
15112 +struct net_device *dev = pci_get_drvdata(pdev);
15115 + /* Device not available. Return. */
15119 + pNet = (DEV_NET*) dev->priv;
15121 + next = pAC->Next;
15123 + netif_stop_queue(dev);
15124 + SkGeYellowLED(pAC, pAC->IoBase, 0);
15126 + if(pAC->BoardLevel == SK_INIT_RUN) {
15127 + /* board is still alive */
15128 + spin_lock_irqsave(&pAC->SlowPathLock, Flags);
15129 + SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP,
15130 + 0, -1, SK_FALSE);
15131 + SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP,
15134 + /* disable interrupts */
15135 + SK_OUT32(pAC->IoBase, B0_IMSK, 0);
15136 + SkGeDeInit(pAC, pAC->IoBase);
15137 + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
15138 + pAC->BoardLevel = SK_INIT_DATA;
15139 + /* We do NOT check here, if IRQ was pending, of course*/
15142 + if(pAC->BoardLevel == SK_INIT_IO) {
15143 + /* board is still alive */
15144 + SkGeDeInit(pAC, pAC->IoBase);
15145 + pAC->BoardLevel = SK_INIT_DATA;
15148 + if ((pAC->GIni.GIMacsFound == 2) && pAC->RlmtNets == 2){
15149 + unregister_netdev(pAC->dev[1]);
15150 + free_netdev(pAC->dev[1]);
15153 + FreeResources(dev);
15155 +#ifdef CONFIG_PROC_FS
15156 + /* Remove the sk98lin procfs device entries */
15157 + if ((pAC->GIni.GIMacsFound == 2) && pAC->RlmtNets == 2){
15158 + remove_proc_entry(pAC->dev[1]->name, pSkRootDir);
15160 + remove_proc_entry(pNet->InitialDevName, pSkRootDir);
15163 + dev->get_stats = NULL;
15165 + * otherwise unregister_netdev calls get_stats with
15166 + * invalid IO ... :-(
15168 + unregister_netdev(dev);
15169 + free_netdev(dev);
15171 + sk98lin_max_boards_found--;
15173 +#ifdef CONFIG_PROC_FS
15174 + /* Remove all Proc entries if last device */
15175 + if (sk98lin_max_boards_found == 0) {
15176 + /* clear proc-dir */
15177 + remove_proc_entry(pSkRootDir->name, proc_net);
15184 /*****************************************************************************
15186 @@ -509,12 +1483,11 @@
15187 spin_lock_init(&pAC->TxPort[i][0].TxDesRingLock);
15188 spin_lock_init(&pAC->RxPort[i].RxDesRingLock);
15190 - spin_lock_init(&pAC->SlowPathLock);
15192 - /* setup phy_id blink timer */
15193 - pAC->BlinkTimer.function = SkGeBlinkTimer;
15194 - pAC->BlinkTimer.data = (unsigned long) dev;
15195 - init_timer(&pAC->BlinkTimer);
15196 + spin_lock_init(&pAC->InitLock); /* Init lock */
15197 + spin_lock_init(&pAC->SlowPathLock);
15198 + spin_lock_init(&pAC->TxQueueLock); /* for Yukon2 chipsets */
15199 + spin_lock_init(&pAC->SetPutIndexLock); /* for Yukon2 chipsets */
15201 /* level 0 init common modules here */
15203 @@ -523,7 +1496,7 @@
15204 if (SkGeInit(pAC, pAC->IoBase, SK_INIT_DATA) != 0) {
15205 printk("HWInit (0) failed.\n");
15206 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
15210 SkI2cInit( pAC, pAC->IoBase, SK_INIT_DATA);
15211 SkEventInit(pAC, pAC->IoBase, SK_INIT_DATA);
15212 @@ -533,19 +1506,17 @@
15213 SkTimerInit(pAC, pAC->IoBase, SK_INIT_DATA);
15215 pAC->BoardLevel = SK_INIT_DATA;
15216 - pAC->RxBufSize = ETH_BUF_SIZE;
15217 + pAC->RxPort[0].RxBufSize = ETH_BUF_SIZE;
15218 + pAC->RxPort[1].RxBufSize = ETH_BUF_SIZE;
15220 SK_PNMI_SET_DRIVER_DESCR(pAC, DescrString);
15221 SK_PNMI_SET_DRIVER_VER(pAC, VerStr);
15223 - spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
15225 /* level 1 init common modules here (HW init) */
15226 - spin_lock_irqsave(&pAC->SlowPathLock, Flags);
15227 if (SkGeInit(pAC, pAC->IoBase, SK_INIT_IO) != 0) {
15228 printk("sk98lin: HWInit (1) failed.\n");
15229 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
15233 SkI2cInit( pAC, pAC->IoBase, SK_INIT_IO);
15234 SkEventInit(pAC, pAC->IoBase, SK_INIT_IO);
15235 @@ -553,46 +1524,93 @@
15236 SkAddrInit( pAC, pAC->IoBase, SK_INIT_IO);
15237 SkRlmtInit( pAC, pAC->IoBase, SK_INIT_IO);
15238 SkTimerInit(pAC, pAC->IoBase, SK_INIT_IO);
15239 +#ifdef Y2_RECOVERY
15240 + /* mark entries invalid */
15241 + pAC->LastPort = 3;
15242 + pAC->LastOpc = 0xFF;
15245 /* Set chipset type support */
15246 - pAC->ChipsetType = 0;
15247 if ((pAC->GIni.GIChipId == CHIP_ID_YUKON) ||
15248 - (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE)) {
15249 - pAC->ChipsetType = 1;
15250 + (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) ||
15251 + (pAC->GIni.GIChipId == CHIP_ID_YUKON_LP)) {
15252 + pAC->ChipsetType = 1; /* Yukon chipset (descriptor logic) */
15253 + } else if (CHIP_ID_YUKON_2(pAC)) {
15254 + pAC->ChipsetType = 2; /* Yukon2 chipset (list logic) */
15256 + pAC->ChipsetType = 0; /* Genesis chipset (descriptor logic) */
15259 + /* wake on lan support */
15260 + pAC->WolInfo.SupportedWolOptions = 0;
15261 +#if defined (ETHTOOL_GWOL) && defined (ETHTOOL_SWOL)
15262 + if (pAC->GIni.GIChipId != CHIP_ID_GENESIS) {
15263 + pAC->WolInfo.SupportedWolOptions = WAKE_MAGIC;
15264 + if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {
15265 + if (pAC->GIni.GIChipRev == 0) {
15266 + pAC->WolInfo.SupportedWolOptions = 0;
15271 + pAC->WolInfo.ConfiguredWolOptions = pAC->WolInfo.SupportedWolOptions;
15273 GetConfiguration(pAC);
15274 if (pAC->RlmtNets == 2) {
15275 - pAC->GIni.GIPortUsage = SK_MUL_LINK;
15276 + pAC->GIni.GP[0].PPortUsage = SK_MUL_LINK;
15277 + pAC->GIni.GP[1].PPortUsage = SK_MUL_LINK;
15280 pAC->BoardLevel = SK_INIT_IO;
15281 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
15283 - if (pAC->GIni.GIMacsFound == 2) {
15284 - Ret = request_irq(dev->irq, SkGeIsr, IRQF_SHARED, "sk98lin", dev);
15285 - } else if (pAC->GIni.GIMacsFound == 1) {
15286 - Ret = request_irq(dev->irq, SkGeIsrOnePort, IRQF_SHARED,
15289 - printk(KERN_WARNING "sk98lin: Illegal number of ports: %d\n",
15290 - pAC->GIni.GIMacsFound);
15292 + if (!CHIP_ID_YUKON_2(pAC)) {
15293 + if (pAC->GIni.GIMacsFound == 2) {
15294 + Ret = request_irq(dev->irq, SkGeIsr, SA_SHIRQ, dev->name, dev);
15295 + } else if (pAC->GIni.GIMacsFound == 1) {
15296 + Ret = request_irq(dev->irq, SkGeIsrOnePort, SA_SHIRQ, dev->name, dev);
15298 + printk(KERN_WARNING "sk98lin: Illegal number of ports: %d\n",
15299 + pAC->GIni.GIMacsFound);
15304 + Ret = request_irq(dev->irq, SkY2Isr, SA_SHIRQ, dev->name, dev);
15308 printk(KERN_WARNING "sk98lin: Requested IRQ %d is busy.\n",
15314 pAC->AllocFlag |= SK_ALLOC_IRQ;
15316 - /* Alloc memory for this board (Mem for RxD/TxD) : */
15317 - if(!BoardAllocMem(pAC)) {
15318 - printk("No memory for descriptor rings.\n");
15321 + ** Alloc descriptor/LETable memory for this board (both RxD/TxD)
15323 + if (CHIP_ID_YUKON_2(pAC)) {
15324 + if (!SkY2AllocateResources(pAC)) {
15325 + printk("No memory for Yukon2 settings\n");
15329 + if(!BoardAllocMem(pAC)) {
15330 + printk("No memory for descriptor rings.\n");
15335 +#ifdef SK_USE_CSUM
15336 + SkCsSetReceiveFlags(pAC,
15337 + SKCS_PROTO_IP | SKCS_PROTO_TCP | SKCS_PROTO_UDP,
15338 + &pAC->CsOfs1, &pAC->CsOfs2, 0);
15339 + pAC->CsOfs = (pAC->CsOfs2 << 16) | pAC->CsOfs1;
15343 + ** Function BoardInitMem() for Yukon dependent settings...
15346 /* tschilling: New common function with minimum size check. */
15347 DualNet = SK_FALSE;
15348 @@ -604,11 +1622,22 @@
15352 - BoardFreeMem(pAC);
15353 + if (CHIP_ID_YUKON_2(pAC)) {
15354 + SkY2FreeResources(pAC);
15356 + BoardFreeMem(pAC);
15359 printk("sk98lin: SkGeInitAssignRamToQueues failed.\n");
15365 + * Register the device here
15367 + pAC->Next = SkGeRootDev;
15368 + SkGeRootDev = dev;
15371 } /* SkGeBoardInit */
15373 @@ -627,7 +1656,8 @@
15374 * SK_TRUE, if all memory could be allocated
15377 -static __devinit SK_BOOL BoardAllocMem(SK_AC *pAC)
15378 +static SK_BOOL BoardAllocMem(
15381 caddr_t pDescrMem; /* pointer to descriptor memory area */
15382 size_t AllocLength; /* length of complete descriptor area */
15383 @@ -697,16 +1727,20 @@
15385 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
15386 ("BoardFreeMem\n"));
15388 + if (pAC->pDescrMem) {
15390 #if (BITS_PER_LONG == 32)
15391 - AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound + 8;
15392 + AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound + 8;
15394 - AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound
15395 - + RX_RING_SIZE + 8;
15396 + AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound
15397 + + RX_RING_SIZE + 8;
15400 - pci_free_consistent(pAC->PciDev, AllocLength,
15401 + pci_free_consistent(pAC->PciDev, AllocLength,
15402 pAC->pDescrMem, pAC->pDescrMemDMA);
15403 - pAC->pDescrMem = NULL;
15404 + pAC->pDescrMem = NULL;
15406 } /* BoardFreeMem */
15409 @@ -715,12 +1749,13 @@
15410 * BoardInitMem - initiate the descriptor rings
15413 - * This function sets the descriptor rings up in memory.
15414 + * This function sets the descriptor rings or LETables up in memory.
15415 * The adapter is initialized with the descriptor start addresses.
15419 -static __devinit void BoardInitMem(SK_AC *pAC)
15420 +static void BoardInitMem(
15421 +SK_AC *pAC) /* pointer to adapter context */
15423 int i; /* loop counter */
15424 int RxDescrSize; /* the size of a rx descriptor rounded up to alignment*/
15425 @@ -729,34 +1764,37 @@
15426 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
15427 ("BoardInitMem\n"));
15429 - RxDescrSize = (((sizeof(RXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN;
15430 - pAC->RxDescrPerRing = RX_RING_SIZE / RxDescrSize;
15431 - TxDescrSize = (((sizeof(TXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN;
15432 - pAC->TxDescrPerRing = TX_RING_SIZE / RxDescrSize;
15433 + if (!pAC->GIni.GIYukon2) {
15434 + RxDescrSize = (((sizeof(RXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN;
15435 + pAC->RxDescrPerRing = RX_RING_SIZE / RxDescrSize;
15436 + TxDescrSize = (((sizeof(TXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN;
15437 + pAC->TxDescrPerRing = TX_RING_SIZE / RxDescrSize;
15439 - for (i=0; i<pAC->GIni.GIMacsFound; i++) {
15442 - pAC->TxPort[i][0].pTxDescrRing,
15443 - pAC->TxPort[i][0].VTxDescrRing,
15444 - (RXD**)&pAC->TxPort[i][0].pTxdRingHead,
15445 - (RXD**)&pAC->TxPort[i][0].pTxdRingTail,
15446 - (RXD**)&pAC->TxPort[i][0].pTxdRingPrev,
15447 - &pAC->TxPort[i][0].TxdRingFree,
15451 - pAC->RxPort[i].pRxDescrRing,
15452 - pAC->RxPort[i].VRxDescrRing,
15453 - &pAC->RxPort[i].pRxdRingHead,
15454 - &pAC->RxPort[i].pRxdRingTail,
15455 - &pAC->RxPort[i].pRxdRingPrev,
15456 - &pAC->RxPort[i].RxdRingFree,
15458 + for (i=0; i<pAC->GIni.GIMacsFound; i++) {
15461 + pAC->TxPort[i][0].pTxDescrRing,
15462 + pAC->TxPort[i][0].VTxDescrRing,
15463 + (RXD**)&pAC->TxPort[i][0].pTxdRingHead,
15464 + (RXD**)&pAC->TxPort[i][0].pTxdRingTail,
15465 + (RXD**)&pAC->TxPort[i][0].pTxdRingPrev,
15466 + &pAC->TxPort[i][0].TxdRingFree,
15467 + &pAC->TxPort[i][0].TxdRingPrevFree,
15471 + pAC->RxPort[i].pRxDescrRing,
15472 + pAC->RxPort[i].VRxDescrRing,
15473 + &pAC->RxPort[i].pRxdRingHead,
15474 + &pAC->RxPort[i].pRxdRingTail,
15475 + &pAC->RxPort[i].pRxdRingPrev,
15476 + &pAC->RxPort[i].RxdRingFree,
15477 + &pAC->RxPort[i].RxdRingFree,
15481 } /* BoardInitMem */
15484 /*****************************************************************************
15486 * SetupRing - create one descriptor ring
15487 @@ -776,6 +1814,7 @@
15488 RXD **ppRingTail, /* address where the tail should be written */
15489 RXD **ppRingPrev, /* address where the tail should be written */
15490 int *pRingFree, /* address where the # of free descr. goes */
15491 +int *pRingPrevFree, /* address where the # of free descr. goes */
15492 SK_BOOL IsTx) /* flag: is this a tx ring */
15494 int i; /* loop counter */
15495 @@ -808,7 +1847,7 @@
15496 /* set the pointers right */
15497 pDescr->VNextRxd = VNextDescr & 0xffffffffULL;
15498 pDescr->pNextRxd = pNextDescr;
15499 - if (!IsTx) pDescr->TcpSumStarts = ETH_HLEN << 16 | ETH_HLEN;
15500 + pDescr->TcpSumStarts = pAC->CsOfs;
15502 /* advance one step */
15503 pPrevDescr = pDescr;
15504 @@ -818,11 +1857,12 @@
15506 pPrevDescr->pNextRxd = (RXD*) pMemArea;
15507 pPrevDescr->VNextRxd = VMemArea;
15508 - pDescr = (RXD*) pMemArea;
15509 - *ppRingHead = (RXD*) pMemArea;
15510 - *ppRingTail = *ppRingHead;
15511 - *ppRingPrev = pPrevDescr;
15512 - *pRingFree = DescrNum;
15513 + pDescr = (RXD*) pMemArea;
15514 + *ppRingHead = (RXD*) pMemArea;
15515 + *ppRingTail = *ppRingHead;
15516 + *ppRingPrev = pPrevDescr;
15517 + *pRingFree = DescrNum;
15518 + *pRingPrevFree = DescrNum;
15522 @@ -887,17 +1927,35 @@
15524 SK_U32 IntSrc; /* interrupts source register contents */
15526 - pNet = netdev_priv(dev);
15527 + pNet = (DEV_NET*) dev->priv;
15531 * Check and process if its our interrupt
15533 SK_IN32(pAC->IoBase, B0_SP_ISRC, &IntSrc);
15534 - if (IntSrc == 0) {
15535 + if ((IntSrc == 0) && (!pNet->NetConsoleMode)) {
15536 return SkIsrRetNone;
15539 +#ifdef CONFIG_SK98LIN_NAPI
15540 + if (netif_rx_schedule_prep(dev)) {
15541 + pAC->GIni.GIValIrqMask &= ~(NAPI_DRV_IRQS);
15542 + SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
15543 + __netif_rx_schedule(dev);
15546 +#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
15547 + if (IntSrc & IS_XA1_F) {
15548 + CLEAR_TX_IRQ(0, TX_PRIO_LOW);
15550 + if (IntSrc & IS_XA2_F) {
15551 + CLEAR_TX_IRQ(1, TX_PRIO_LOW);
15557 while (((IntSrc & IRQ_MASK) & ~SPECIAL_IRQS) != 0) {
15558 #if 0 /* software irq currently not used */
15559 if (IntSrc & IS_IRQ_SW) {
15560 @@ -911,6 +1969,7 @@
15561 SK_DBGCAT_DRV_INT_SRC,
15562 ("EOF RX1 IRQ\n"));
15563 ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE);
15564 + CLEAR_AND_START_RX(0);
15565 SK_PNMI_CNT_RX_INTR(pAC, 0);
15567 if (IntSrc & IS_R2_F) {
15568 @@ -918,6 +1977,7 @@
15569 SK_DBGCAT_DRV_INT_SRC,
15570 ("EOF RX2 IRQ\n"));
15571 ReceiveIrq(pAC, &pAC->RxPort[1], SK_TRUE);
15572 + CLEAR_AND_START_RX(1);
15573 SK_PNMI_CNT_RX_INTR(pAC, 1);
15575 #ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
15576 @@ -925,6 +1985,7 @@
15577 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
15578 SK_DBGCAT_DRV_INT_SRC,
15579 ("EOF AS TX1 IRQ\n"));
15580 + CLEAR_TX_IRQ(0, TX_PRIO_LOW);
15581 SK_PNMI_CNT_TX_INTR(pAC, 0);
15582 spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
15583 FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]);
15584 @@ -934,6 +1995,7 @@
15585 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
15586 SK_DBGCAT_DRV_INT_SRC,
15587 ("EOF AS TX2 IRQ\n"));
15588 + CLEAR_TX_IRQ(1, TX_PRIO_LOW);
15589 SK_PNMI_CNT_TX_INTR(pAC, 1);
15590 spin_lock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock);
15591 FreeTxDescriptors(pAC, &pAC->TxPort[1][TX_PRIO_LOW]);
15592 @@ -944,38 +2006,42 @@
15593 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
15594 SK_DBGCAT_DRV_INT_SRC,
15595 ("EOF SY TX1 IRQ\n"));
15596 + CLEAR_TX_IRQ(0, TX_PRIO_HIGH);
15597 SK_PNMI_CNT_TX_INTR(pAC, 1);
15598 spin_lock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock);
15599 FreeTxDescriptors(pAC, 0, TX_PRIO_HIGH);
15600 spin_unlock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock);
15601 - ClearTxIrq(pAC, 0, TX_PRIO_HIGH);
15603 if (IntSrc & IS_XS2_F) {
15604 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
15605 SK_DBGCAT_DRV_INT_SRC,
15606 ("EOF SY TX2 IRQ\n"));
15607 + CLEAR_TX_IRQ(1, TX_PRIO_HIGH);
15608 SK_PNMI_CNT_TX_INTR(pAC, 1);
15609 spin_lock(&pAC->TxPort[1][TX_PRIO_HIGH].TxDesRingLock);
15610 FreeTxDescriptors(pAC, 1, TX_PRIO_HIGH);
15611 spin_unlock(&pAC->TxPort[1][TX_PRIO_HIGH].TxDesRingLock);
15612 - ClearTxIrq(pAC, 1, TX_PRIO_HIGH);
15617 - /* do all IO at once */
15618 - if (IntSrc & IS_R1_F)
15619 - ClearAndStartRx(pAC, 0);
15620 - if (IntSrc & IS_R2_F)
15621 - ClearAndStartRx(pAC, 1);
15622 -#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
15623 - if (IntSrc & IS_XA1_F)
15624 - ClearTxIrq(pAC, 0, TX_PRIO_LOW);
15625 - if (IntSrc & IS_XA2_F)
15626 - ClearTxIrq(pAC, 1, TX_PRIO_LOW);
15628 SK_IN32(pAC->IoBase, B0_ISRC, &IntSrc);
15629 } /* while (IntSrc & IRQ_MASK != 0) */
15632 +#ifndef CONFIG_SK98LIN_NAPI
15633 + /* Handle interrupts */
15634 + spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
15635 + FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]);
15636 + spin_unlock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
15637 + ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE);
15639 + spin_lock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock);
15640 + FreeTxDescriptors(pAC, &pAC->TxPort[1][TX_PRIO_LOW]);
15641 + spin_unlock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock);
15642 + ReceiveIrq(pAC, &pAC->RxPort[1], SK_TRUE);
15646 IntSrc &= pAC->GIni.GIValIrqMask;
15647 if ((IntSrc & SPECIAL_IRQS) || pAC->CheckQueue) {
15648 @@ -988,19 +2054,9 @@
15650 SkEventDispatcher(pAC, pAC->IoBase);
15651 spin_unlock(&pAC->SlowPathLock);
15656 - * do it all again is case we cleared an interrupt that
15657 - * came in after handling the ring (OUTs may be delayed
15658 - * in hardware buffers, but are through after IN)
15660 - * rroesler: has been commented out and shifted to
15661 - * SkGeDrvEvent(), because it is timer
15664 - ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE);
15665 - ReceiveIrq(pAC, &pAC->RxPort[1], SK_TRUE);
15668 if (pAC->CheckQueue) {
15669 pAC->CheckQueue = SK_FALSE;
15670 @@ -1012,7 +2068,7 @@
15671 /* IRQ is processed - Enable IRQs again*/
15672 SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
15674 - return SkIsrRetHandled;
15675 + return SkIsrRetHandled;
15679 @@ -1036,17 +2092,32 @@
15681 SK_U32 IntSrc; /* interrupts source register contents */
15683 - pNet = netdev_priv(dev);
15684 + pNet = (DEV_NET*) dev->priv;
15688 * Check and process if its our interrupt
15690 SK_IN32(pAC->IoBase, B0_SP_ISRC, &IntSrc);
15691 - if (IntSrc == 0) {
15692 + if ((IntSrc == 0) && (!pNet->NetConsoleMode)) {
15693 return SkIsrRetNone;
15696 +#ifdef CONFIG_SK98LIN_NAPI
15697 + if (netif_rx_schedule_prep(dev)) {
15698 + CLEAR_AND_START_RX(0);
15699 + CLEAR_TX_IRQ(0, TX_PRIO_LOW);
15700 + pAC->GIni.GIValIrqMask &= ~(NAPI_DRV_IRQS);
15701 + SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
15702 + __netif_rx_schedule(dev);
15705 +#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
15706 + if (IntSrc & IS_XA1_F) {
15707 + CLEAR_TX_IRQ(0, TX_PRIO_LOW);
15711 while (((IntSrc & IRQ_MASK) & ~SPECIAL_IRQS) != 0) {
15712 #if 0 /* software irq currently not used */
15713 if (IntSrc & IS_IRQ_SW) {
15714 @@ -1060,6 +2131,7 @@
15715 SK_DBGCAT_DRV_INT_SRC,
15716 ("EOF RX1 IRQ\n"));
15717 ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE);
15718 + CLEAR_AND_START_RX(0);
15719 SK_PNMI_CNT_RX_INTR(pAC, 0);
15721 #ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
15722 @@ -1067,6 +2139,7 @@
15723 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
15724 SK_DBGCAT_DRV_INT_SRC,
15725 ("EOF AS TX1 IRQ\n"));
15726 + CLEAR_TX_IRQ(0, TX_PRIO_LOW);
15727 SK_PNMI_CNT_TX_INTR(pAC, 0);
15728 spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
15729 FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]);
15730 @@ -1077,25 +2150,27 @@
15731 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
15732 SK_DBGCAT_DRV_INT_SRC,
15733 ("EOF SY TX1 IRQ\n"));
15734 + CLEAR_TX_IRQ(0, TX_PRIO_HIGH);
15735 SK_PNMI_CNT_TX_INTR(pAC, 0);
15736 spin_lock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock);
15737 FreeTxDescriptors(pAC, 0, TX_PRIO_HIGH);
15738 spin_unlock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock);
15739 - ClearTxIrq(pAC, 0, TX_PRIO_HIGH);
15744 - /* do all IO at once */
15745 - if (IntSrc & IS_R1_F)
15746 - ClearAndStartRx(pAC, 0);
15747 -#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
15748 - if (IntSrc & IS_XA1_F)
15749 - ClearTxIrq(pAC, 0, TX_PRIO_LOW);
15751 SK_IN32(pAC->IoBase, B0_ISRC, &IntSrc);
15752 } /* while (IntSrc & IRQ_MASK != 0) */
15755 +#ifndef CONFIG_SK98LIN_NAPI
15756 + spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
15757 + FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]);
15758 + spin_unlock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
15759 + ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE);
15763 IntSrc &= pAC->GIni.GIValIrqMask;
15764 if ((IntSrc & SPECIAL_IRQS) || pAC->CheckQueue) {
15765 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
15766 @@ -1107,44 +2182,15 @@
15768 SkEventDispatcher(pAC, pAC->IoBase);
15769 spin_unlock(&pAC->SlowPathLock);
15773 - * do it all again is case we cleared an interrupt that
15774 - * came in after handling the ring (OUTs may be delayed
15775 - * in hardware buffers, but are through after IN)
15777 - * rroesler: has been commented out and shifted to
15778 - * SkGeDrvEvent(), because it is timer
15781 - ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE);
15784 /* IRQ is processed - Enable IRQs again*/
15785 SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
15787 - return SkIsrRetHandled;
15788 + return SkIsrRetHandled;
15789 } /* SkGeIsrOnePort */
15791 -#ifdef CONFIG_NET_POLL_CONTROLLER
15792 -/****************************************************************************
15794 - * SkGePollController - polling receive, for netconsole
15797 - * Polling receive - used by netconsole and other diagnostic tools
15798 - * to allow network i/o with interrupts disabled.
15802 -static void SkGePollController(struct net_device *dev)
15804 - disable_irq(dev->irq);
15805 - SkGeIsr(dev->irq, dev);
15806 - enable_irq(dev->irq);
15810 /****************************************************************************
15812 * SkGeOpen - handle start of initialized adapter
15813 @@ -1162,27 +2208,27 @@
15816 static int SkGeOpen(
15817 -struct SK_NET_DEVICE *dev)
15818 +struct SK_NET_DEVICE *dev) /* the device that is to be opened */
15822 - unsigned long Flags; /* for spin lock */
15824 - SK_EVPARA EvPara; /* an event parameter union */
15825 + DEV_NET *pNet = (DEV_NET*) dev->priv;
15826 + SK_AC *pAC = pNet->pAC;
15827 + unsigned long Flags; /* for the spin locks */
15828 + unsigned long InitFlags; /* for the spin locks */
15829 + int CurrMac; /* loop ctr for ports */
15831 - pNet = netdev_priv(dev);
15834 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
15835 ("SkGeOpen: pAC=0x%lX:\n", (unsigned long)pAC));
15836 + spin_lock_irqsave(&pAC->InitLock, InitFlags);
15838 -#ifdef SK_DIAG_SUPPORT
15839 if (pAC->DiagModeActive == DIAG_ACTIVE) {
15840 if (pAC->Pnmi.DiagAttached == SK_DIAG_RUNNING) {
15841 return (-1); /* still in use by diag; deny actions */
15846 + if (!try_module_get(THIS_MODULE)) {
15847 + return (-1); /* increase of usage count not possible */
15850 /* Set blink mode */
15851 if ((pAC->PciDev->vendor == 0x1186) || (pAC->PciDev->vendor == 0x11ab ))
15852 @@ -1191,6 +2237,7 @@
15853 if (pAC->BoardLevel == SK_INIT_DATA) {
15854 /* level 1 init common modules here */
15855 if (SkGeInit(pAC, pAC->IoBase, SK_INIT_IO) != 0) {
15856 + module_put(THIS_MODULE); /* decrease usage count */
15857 printk("%s: HWInit (1) failed.\n", pAC->dev[pNet->PortNr]->name);
15860 @@ -1201,11 +2248,17 @@
15861 SkRlmtInit (pAC, pAC->IoBase, SK_INIT_IO);
15862 SkTimerInit (pAC, pAC->IoBase, SK_INIT_IO);
15863 pAC->BoardLevel = SK_INIT_IO;
15864 +#ifdef Y2_RECOVERY
15865 + /* mark entries invalid */
15866 + pAC->LastPort = 3;
15867 + pAC->LastOpc = 0xFF;
15871 if (pAC->BoardLevel != SK_INIT_RUN) {
15872 /* tschilling: Level 2 init modules here, check return value. */
15873 if (SkGeInit(pAC, pAC->IoBase, SK_INIT_RUN) != 0) {
15874 + module_put(THIS_MODULE); /* decrease usage count */
15875 printk("%s: HWInit (2) failed.\n", pAC->dev[pNet->PortNr]->name);
15878 @@ -1218,44 +2271,62 @@
15879 pAC->BoardLevel = SK_INIT_RUN;
15882 - for (i=0; i<pAC->GIni.GIMacsFound; i++) {
15883 - /* Enable transmit descriptor polling. */
15884 - SkGePollTxD(pAC, pAC->IoBase, i, SK_TRUE);
15885 - FillRxRing(pAC, &pAC->RxPort[i]);
15886 + for (CurrMac=0; CurrMac<pAC->GIni.GIMacsFound; CurrMac++) {
15887 + if (!CHIP_ID_YUKON_2(pAC)) {
15888 + /* Enable transmit descriptor polling. */
15889 + SkGePollTxD(pAC, pAC->IoBase, CurrMac, SK_TRUE);
15890 + FillRxRing(pAC, &pAC->RxPort[CurrMac]);
15891 + SkMacRxTxEnable(pAC, pAC->IoBase, pNet->PortNr);
15894 - SkGeYellowLED(pAC, pAC->IoBase, 1);
15896 - StartDrvCleanupTimer(pAC);
15897 + SkGeYellowLED(pAC, pAC->IoBase, 1);
15898 SkDimEnableModerationIfNeeded(pAC);
15899 - SkDimDisplayModerationSettings(pAC);
15901 - pAC->GIni.GIValIrqMask &= IRQ_MASK;
15903 - /* enable Interrupts */
15904 - SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
15905 - SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK);
15906 + if (!CHIP_ID_YUKON_2(pAC)) {
15908 + ** Has been setup already at SkGeInit(SK_INIT_IO),
15909 + ** but additional masking added for Genesis & Yukon
15910 + ** chipsets -> modify it...
15912 + pAC->GIni.GIValIrqMask &= IRQ_MASK;
15913 +#ifndef USE_TX_COMPLETE
15914 + pAC->GIni.GIValIrqMask &= ~(TX_COMPL_IRQS);
15918 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
15920 if ((pAC->RlmtMode != 0) && (pAC->MaxPorts == 0)) {
15921 - EvPara.Para32[0] = pAC->RlmtNets;
15922 - EvPara.Para32[1] = -1;
15923 - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_SET_NETS,
15925 - EvPara.Para32[0] = pAC->RlmtMode;
15926 - EvPara.Para32[1] = 0;
15927 - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_MODE_CHANGE,
15929 + SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_SET_NETS,
15930 + pAC->RlmtNets, -1, SK_FALSE);
15931 + SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_MODE_CHANGE,
15932 + pAC->RlmtMode, 0, SK_FALSE);
15935 - EvPara.Para32[0] = pNet->NetNr;
15936 - EvPara.Para32[1] = -1;
15937 - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara);
15938 - SkEventDispatcher(pAC, pAC->IoBase);
15939 + SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_START,
15940 + pNet->NetNr, -1, SK_TRUE);
15941 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
15944 +#ifdef Y2_RECOVERY
15945 + pNet->TimerExpired = SK_FALSE;
15946 + pNet->InRecover = SK_FALSE;
15947 + pNet->NetConsoleMode = SK_FALSE;
15949 + /* Initialize the kernel timer */
15950 + init_timer(&pNet->KernelTimer);
15951 + pNet->KernelTimer.function = SkGeHandleKernelTimer;
15952 + pNet->KernelTimer.data = (unsigned long) pNet;
15953 + pNet->KernelTimer.expires = jiffies + (HZ/4); /* initially 250ms */
15954 + add_timer(&pNet->KernelTimer);
15957 + /* enable Interrupts */
15958 + SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
15959 + SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK);
15962 + spin_unlock_irqrestore(&pAC->InitLock, InitFlags);
15964 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
15965 ("SkGeOpen suceeded\n"));
15966 @@ -1276,32 +2347,37 @@
15967 * error code - on error
15969 static int SkGeClose(
15970 -struct SK_NET_DEVICE *dev)
15971 +struct SK_NET_DEVICE *dev) /* the device that is to be closed */
15974 - DEV_NET *newPtrNet;
15977 - unsigned long Flags; /* for spin lock */
15980 - SK_EVPARA EvPara;
15982 + DEV_NET *pNet = (DEV_NET*) dev->priv;
15983 + SK_AC *pAC = pNet->pAC;
15984 + DEV_NET *newPtrNet;
15985 + unsigned long Flags; /* for the spin locks */
15986 + unsigned long InitFlags; /* for the spin locks */
15987 + int CurrMac; /* loop ctr for the current MAC */
15989 +#ifdef CONFIG_SK98LIN_NAPI
15990 + int WorkToDo = 1; /* min(*budget, dev->quota); */
15991 + int WorkDone = 0;
15993 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
15994 ("SkGeClose: pAC=0x%lX ", (unsigned long)pAC));
15995 + spin_lock_irqsave(&pAC->InitLock, InitFlags);
15997 - pNet = netdev_priv(dev);
15999 +#ifdef Y2_RECOVERY
16000 + pNet->InRecover = SK_TRUE;
16001 + del_timer(&pNet->KernelTimer);
16004 -#ifdef SK_DIAG_SUPPORT
16005 if (pAC->DiagModeActive == DIAG_ACTIVE) {
16006 if (pAC->DiagFlowCtrl == SK_FALSE) {
16007 + module_put(THIS_MODULE);
16009 ** notify that the interface which has been closed
16010 ** by operator interaction must not be started up
16011 ** again when the DIAG has finished.
16013 - newPtrNet = netdev_priv(pAC->dev[0]);
16014 + newPtrNet = (DEV_NET *) pAC->dev[0]->priv;
16015 if (newPtrNet == pNet) {
16016 pAC->WasIfUp[0] = SK_FALSE;
16018 @@ -1312,7 +2388,6 @@
16019 pAC->DiagFlowCtrl = SK_FALSE;
16024 netif_stop_queue(dev);
16026 @@ -1321,8 +2396,6 @@
16028 PortIdx = pNet->NetNr;
16030 - StopDrvCleanupTimer(pAC);
16033 * Clear multicast table, promiscuous mode ....
16035 @@ -1334,46 +2407,101 @@
16036 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
16037 /* disable interrupts */
16038 SK_OUT32(pAC->IoBase, B0_IMSK, 0);
16039 - EvPara.Para32[0] = pNet->NetNr;
16040 - EvPara.Para32[1] = -1;
16041 - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
16042 - SkEventDispatcher(pAC, pAC->IoBase);
16043 + SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP,
16044 + pNet->NetNr, -1, SK_TRUE);
16045 SK_OUT32(pAC->IoBase, B0_IMSK, 0);
16046 /* stop the hardware */
16047 - SkGeDeInit(pAC, pAC->IoBase);
16048 - pAC->BoardLevel = SK_INIT_DATA;
16051 + if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 1)) {
16052 + /* RLMT check link state mode */
16053 + for (CurrMac=0; CurrMac<pAC->GIni.GIMacsFound; CurrMac++) {
16054 + if (CHIP_ID_YUKON_2(pAC))
16055 + SkY2PortStop( pAC,
16061 + SkGeStopPort( pAC,
16068 + /* Single link or single port */
16069 + if (CHIP_ID_YUKON_2(pAC))
16070 + SkY2PortStop( pAC,
16076 + SkGeStopPort( pAC,
16082 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
16085 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
16086 - EvPara.Para32[0] = pNet->NetNr;
16087 - EvPara.Para32[1] = -1;
16088 - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
16089 - SkPnmiEvent(pAC, pAC->IoBase, SK_PNMI_EVT_XMAC_RESET, EvPara);
16090 - SkEventDispatcher(pAC, pAC->IoBase);
16091 + SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP,
16092 + pNet->NetNr, -1, SK_FALSE);
16093 + SkLocalEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET,
16094 + pNet->NetNr, -1, SK_TRUE);
16095 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
16098 spin_lock_irqsave(&pAC->TxPort[pNet->PortNr]
16099 [TX_PRIO_LOW].TxDesRingLock, Flags);
16100 - SkGeStopPort(pAC, pAC->IoBase, pNet->PortNr,
16101 - SK_STOP_ALL, SK_HARD_RST);
16102 + if (CHIP_ID_YUKON_2(pAC)) {
16103 + SkY2PortStop(pAC, pAC->IoBase, pNet->PortNr,
16104 + SK_STOP_ALL, SK_HARD_RST);
16107 + SkGeStopPort(pAC, pAC->IoBase, pNet->PortNr,
16108 + SK_STOP_ALL, SK_HARD_RST);
16110 spin_unlock_irqrestore(&pAC->TxPort[pNet->PortNr]
16111 [TX_PRIO_LOW].TxDesRingLock, Flags);
16114 if (pAC->RlmtNets == 1) {
16115 /* clear all descriptor rings */
16116 - for (i=0; i<pAC->GIni.GIMacsFound; i++) {
16117 - ReceiveIrq(pAC, &pAC->RxPort[i], SK_TRUE);
16118 - ClearRxRing(pAC, &pAC->RxPort[i]);
16119 - ClearTxRing(pAC, &pAC->TxPort[i][TX_PRIO_LOW]);
16120 + for (CurrMac=0; CurrMac<pAC->GIni.GIMacsFound; CurrMac++) {
16121 + if (!CHIP_ID_YUKON_2(pAC)) {
16122 +#ifdef CONFIG_SK98LIN_NAPI
16124 + ReceiveIrq(pAC,&pAC->RxPort[CurrMac],
16125 + SK_TRUE,&WorkDone,WorkToDo);
16127 + ReceiveIrq(pAC,&pAC->RxPort[CurrMac],SK_TRUE);
16129 + ClearRxRing(pAC, &pAC->RxPort[CurrMac]);
16130 + ClearTxRing(pAC, &pAC->TxPort[CurrMac][TX_PRIO_LOW]);
16132 + SkY2FreeRxBuffers(pAC, pAC->IoBase, CurrMac);
16133 + SkY2FreeTxBuffers(pAC, pAC->IoBase, CurrMac);
16137 /* clear port descriptor rings */
16138 - ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE);
16139 - ClearRxRing(pAC, &pAC->RxPort[pNet->PortNr]);
16140 - ClearTxRing(pAC, &pAC->TxPort[pNet->PortNr][TX_PRIO_LOW]);
16141 + if (!CHIP_ID_YUKON_2(pAC)) {
16142 +#ifdef CONFIG_SK98LIN_NAPI
16144 + ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE, &WorkDone, WorkToDo);
16146 + ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE);
16148 + ClearRxRing(pAC, &pAC->RxPort[pNet->PortNr]);
16149 + ClearTxRing(pAC, &pAC->TxPort[pNet->PortNr][TX_PRIO_LOW]);
16152 + SkY2FreeRxBuffers(pAC, pAC->IoBase, pNet->PortNr);
16153 + SkY2FreeTxBuffers(pAC, pAC->IoBase, pNet->PortNr);
16157 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
16158 @@ -1384,6 +2512,12 @@
16159 sizeof(SK_PNMI_STRUCT_DATA));
16162 + module_put(THIS_MODULE);
16164 +#ifdef Y2_RECOVERY
16165 + pNet->InRecover = SK_FALSE;
16167 + spin_unlock_irqrestore(&pAC->InitLock, InitFlags);
16171 @@ -1410,7 +2544,7 @@
16173 int Rc; /* return code of XmitFrame */
16175 - pNet = netdev_priv(dev);
16176 + pNet = (DEV_NET*) dev->priv;
16179 if ((!skb_shinfo(skb)->nr_frags) ||
16180 @@ -1456,6 +2590,96 @@
16184 +#ifdef CONFIG_SK98LIN_NAPI
16185 +/*****************************************************************************
16187 + * SkGePoll - NAPI Rx polling callback for GEnesis and Yukon chipsets
16190 + * Called by the Linux system in case NAPI polling is activated
16193 + * The number of work data still to be handled
16195 +static int SkGePoll(struct net_device *dev, int *budget)
16197 + SK_AC *pAC = ((DEV_NET*)(dev->priv))->pAC; /* pointer to adapter context */
16198 + int WorkToDo = min(*budget, dev->quota);
16199 + int WorkDone = 0;
16200 + unsigned long Flags;
16203 + if (pAC->dev[0] != pAC->dev[1]) {
16204 + spin_lock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock);
16205 + FreeTxDescriptors(pAC, &pAC->TxPort[1][TX_PRIO_LOW]);
16206 + spin_unlock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock);
16208 + ReceiveIrq(pAC, &pAC->RxPort[1], SK_TRUE, &WorkDone, WorkToDo);
16209 + CLEAR_AND_START_RX(1);
16211 + spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
16212 + FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]);
16213 + spin_unlock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
16215 + ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE, &WorkDone, WorkToDo);
16216 + CLEAR_AND_START_RX(0);
16218 + *budget -= WorkDone;
16219 + dev->quota -= WorkDone;
16221 + if(WorkDone < WorkToDo) {
16222 + spin_lock_irqsave(&pAC->SlowPathLock, Flags);
16223 + netif_rx_complete(dev);
16224 + pAC->GIni.GIValIrqMask |= (NAPI_DRV_IRQS);
16225 +#ifndef USE_TX_COMPLETE
16226 + pAC->GIni.GIValIrqMask &= ~(TX_COMPL_IRQS);
16228 + /* enable interrupts again */
16229 + SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
16230 + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
16232 + return (WorkDone >= WorkToDo);
16236 +#ifdef SK_POLL_CONTROLLER
16237 +/*****************************************************************************
16239 + * SkGeNetPoll - Polling "interrupt"
16242 + * Polling 'interrupt' - used by things like netconsole and netdump
16243 + * to send skbs without having to re-enable interrupts.
16244 + * It's not called while the interrupt routine is executing.
16246 +static void SkGeNetPoll(
16247 +struct SK_NET_DEVICE *dev)
16252 + pNet = (DEV_NET*) dev->priv;
16254 + pNet->NetConsoleMode = SK_TRUE;
16256 + /* Prevent any reconfiguration while handling
16257 + the 'interrupt' */
16258 + SK_OUT32(pAC->IoBase, B0_IMSK, 0);
16260 + if (!CHIP_ID_YUKON_2(pAC)) {
16261 + /* Handle the GENESIS Isr */
16262 + if (pAC->GIni.GIMacsFound == 2)
16263 + SkGeIsr(dev->irq, dev);
16265 + SkGeIsrOnePort(dev->irq, dev);
16267 + /* Handle the Yukon2 Isr */
16268 + SkY2Isr(dev->irq, dev);
16275 /*****************************************************************************
16277 @@ -1480,7 +2704,7 @@
16278 * < 0 - on failure: other problems ( -> return failure to upper layers)
16280 static int XmitFrame(
16281 -SK_AC *pAC, /* pointer to adapter context */
16282 +SK_AC *pAC, /* pointer to adapter context */
16283 TX_PORT *pTxPort, /* pointer to struct of port to send to */
16284 struct sk_buff *pMessage) /* pointer to send-message */
16286 @@ -1488,17 +2712,22 @@
16288 unsigned long Flags;
16291 + int IpHeaderLength;
16292 int BytesSend = pMessage->len;
16294 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, ("X"));
16296 spin_lock_irqsave(&pTxPort->TxDesRingLock, Flags);
16297 #ifndef USE_TX_COMPLETE
16298 - FreeTxDescriptors(pAC, pTxPort);
16299 + if ((pTxPort->TxdRingPrevFree - pTxPort->TxdRingFree) > 6) {
16300 + FreeTxDescriptors(pAC, pTxPort);
16301 + pTxPort->TxdRingPrevFree = pTxPort->TxdRingFree;
16304 if (pTxPort->TxdRingFree == 0) {
16306 - ** no enough free descriptors in ring at the moment.
16307 + ** not enough free descriptors in ring at the moment.
16308 ** Maybe free'ing some old one help?
16310 FreeTxDescriptors(pAC, pTxPort);
16311 @@ -1525,7 +2754,7 @@
16312 ** This is to resolve faulty padding by the HW with 0xaa bytes.
16314 if (BytesSend < C_LEN_ETHERNET_MINSIZE) {
16315 - if (skb_padto(pMessage, C_LEN_ETHERNET_MINSIZE)) {
16316 + if ((pMessage = skb_padto(pMessage, C_LEN_ETHERNET_MINSIZE)) == NULL) {
16317 spin_unlock_irqrestore(&pTxPort->TxDesRingLock, Flags);
16320 @@ -1560,10 +2789,8 @@
16321 pTxd->pMBuf = pMessage;
16323 if (pMessage->ip_summed == CHECKSUM_PARTIAL) {
16324 - u16 hdrlen = pMessage->h.raw - pMessage->data;
16325 - u16 offset = hdrlen + pMessage->csum;
16327 - if ((pMessage->h.ipiph->protocol == IPPROTO_UDP ) &&
16328 + Protocol = ((SK_U8)pMessage->data[C_OFFSET_IPPROTO] & 0xff);
16329 + if ((Protocol == C_PROTO_ID_UDP) &&
16330 (pAC->GIni.GIChipRev == 0) &&
16331 (pAC->GIni.GIChipId == CHIP_ID_YUKON)) {
16332 pTxd->TBControl = BMU_TCP_CHECK;
16333 @@ -1571,9 +2798,14 @@
16334 pTxd->TBControl = BMU_UDP_CHECK;
16337 - pTxd->TcpSumOfs = 0;
16338 - pTxd->TcpSumSt = hdrlen;
16339 - pTxd->TcpSumWr = offset;
16340 + IpHeaderLength = (SK_U8)pMessage->data[C_OFFSET_IPHEADER];
16341 + IpHeaderLength = (IpHeaderLength & 0xf) * 4;
16342 + pTxd->TcpSumOfs = 0; /* PH-Checksum already calculated */
16343 + pTxd->TcpSumSt = C_LEN_ETHERMAC_HEADER + IpHeaderLength +
16344 + (Protocol == C_PROTO_ID_UDP ?
16345 + C_OFFSET_UDPHEADER_UDPCS :
16346 + C_OFFSET_TCPHEADER_TCPCS);
16347 + pTxd->TcpSumWr = C_LEN_ETHERMAC_HEADER + IpHeaderLength;
16349 pTxd->TBControl |= BMU_OWN | BMU_STF |
16351 @@ -1581,7 +2813,7 @@
16357 pTxd->TBControl = BMU_OWN | BMU_STF | BMU_CHECK |
16359 #ifdef USE_TX_COMPLETE
16360 @@ -1636,10 +2868,11 @@
16364 + int IpHeaderLength;
16366 skb_frag_t *sk_frag;
16368 unsigned long Flags;
16371 spin_lock_irqsave(&pTxPort->TxDesRingLock, Flags);
16372 #ifndef USE_TX_COMPLETE
16373 @@ -1662,6 +2895,7 @@
16380 ** Map the first fragment (header) into the DMA-space
16381 @@ -1679,31 +2913,32 @@
16382 ** Does the HW need to evaluate checksum for TCP or UDP packets?
16384 if (pMessage->ip_summed == CHECKSUM_PARTIAL) {
16385 - u16 hdrlen = pMessage->h.raw - pMessage->data;
16386 - u16 offset = hdrlen + pMessage->csum;
16388 - Control = BMU_STFWD;
16390 + pTxd->TBControl = BMU_STF | BMU_STFWD | skb_headlen(pMessage);
16392 ** We have to use the opcode for tcp here, because the
16393 ** opcode for udp is not working in the hardware yet
16396 - if ((pMessage->h.ipiph->protocol == IPPROTO_UDP ) &&
16397 + Protocol = ((SK_U8)pMessage->data[C_OFFSET_IPPROTO] & 0xff);
16398 + if ((Protocol == C_PROTO_ID_UDP) &&
16399 (pAC->GIni.GIChipRev == 0) &&
16400 (pAC->GIni.GIChipId == CHIP_ID_YUKON)) {
16401 - Control |= BMU_TCP_CHECK;
16402 + pTxd->TBControl |= BMU_TCP_CHECK;
16404 - Control |= BMU_UDP_CHECK;
16405 + pTxd->TBControl |= BMU_UDP_CHECK;
16408 - pTxd->TcpSumOfs = 0;
16409 - pTxd->TcpSumSt = hdrlen;
16410 - pTxd->TcpSumWr = offset;
16412 - Control = BMU_CHECK | BMU_SW;
16414 - pTxd->TBControl = BMU_STF | Control | skb_headlen(pMessage);
16415 + IpHeaderLength = ((SK_U8)pMessage->data[C_OFFSET_IPHEADER] & 0xf)*4;
16416 + pTxd->TcpSumOfs = 0; /* PH-Checksum already claculated */
16417 + pTxd->TcpSumSt = C_LEN_ETHERMAC_HEADER + IpHeaderLength +
16418 + (Protocol == C_PROTO_ID_UDP ?
16419 + C_OFFSET_UDPHEADER_UDPCS :
16420 + C_OFFSET_TCPHEADER_TCPCS);
16421 + pTxd->TcpSumWr = C_LEN_ETHERMAC_HEADER + IpHeaderLength;
16423 + pTxd->TBControl = BMU_CHECK | BMU_SW | BMU_STF |
16424 + skb_headlen(pMessage);
16427 pTxd = pTxd->pNextTxd;
16428 pTxPort->TxdRingFree--;
16429 @@ -1727,18 +2962,40 @@
16430 pTxd->VDataHigh = (SK_U32) (PhysAddr >> 32);
16431 pTxd->pMBuf = pMessage;
16433 - pTxd->TBControl = Control | BMU_OWN | sk_frag->size;
16435 + ** Does the HW need to evaluate checksum for TCP or UDP packets?
16437 + if (pMessage->ip_summed == CHECKSUM_PARTIAL) {
16438 + pTxd->TBControl = BMU_OWN | BMU_SW | BMU_STFWD;
16440 + ** We have to use the opcode for tcp here because the
16441 + ** opcode for udp is not working in the hardware yet
16442 + ** (revision 2.0)
16444 + if ((Protocol == C_PROTO_ID_UDP) &&
16445 + (pAC->GIni.GIChipRev == 0) &&
16446 + (pAC->GIni.GIChipId == CHIP_ID_YUKON)) {
16447 + pTxd->TBControl |= BMU_TCP_CHECK;
16449 + pTxd->TBControl |= BMU_UDP_CHECK;
16452 + pTxd->TBControl = BMU_CHECK | BMU_SW | BMU_OWN;
16456 ** Do we have the last fragment?
16458 if( (CurrFrag+1) == skb_shinfo(pMessage)->nr_frags ) {
16459 #ifdef USE_TX_COMPLETE
16460 - pTxd->TBControl |= BMU_EOF | BMU_IRQ_EOF;
16461 + pTxd->TBControl |= BMU_EOF | BMU_IRQ_EOF | sk_frag->size;
16463 - pTxd->TBControl |= BMU_EOF;
16464 + pTxd->TBControl |= BMU_EOF | sk_frag->size;
16466 pTxdFst->TBControl |= BMU_OWN | BMU_SW;
16469 + pTxd->TBControl |= sk_frag->size;
16472 pTxd = pTxd->pNextTxd;
16473 @@ -1892,7 +3149,7 @@
16474 SK_U16 Length; /* data fragment length */
16475 SK_U64 PhysAddr; /* physical address of a rx buffer */
16477 - pMsgBlock = alloc_skb(pAC->RxBufSize, GFP_ATOMIC);
16478 + pMsgBlock = alloc_skb(pRxPort->RxBufSize, GFP_ATOMIC);
16479 if (pMsgBlock == NULL) {
16480 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
16481 SK_DBGCAT_DRV_ENTRY,
16482 @@ -1906,12 +3163,12 @@
16483 pRxd = pRxPort->pRxdRingTail;
16484 pRxPort->pRxdRingTail = pRxd->pNextRxd;
16485 pRxPort->RxdRingFree--;
16486 - Length = pAC->RxBufSize;
16487 + Length = pRxPort->RxBufSize;
16488 PhysAddr = (SK_U64) pci_map_page(pAC->PciDev,
16489 virt_to_page(pMsgBlock->data),
16490 ((unsigned long) pMsgBlock->data &
16492 - pAC->RxBufSize - 2,
16493 + pRxPort->RxBufSize - 2,
16494 PCI_DMA_FROMDEVICE);
16496 pRxd->VDataLow = (SK_U32) (PhysAddr & 0xffffffff);
16497 @@ -1951,7 +3208,7 @@
16498 pRxd = pRxPort->pRxdRingTail;
16499 pRxPort->pRxdRingTail = pRxd->pNextRxd;
16500 pRxPort->RxdRingFree--;
16501 - Length = pAC->RxBufSize;
16502 + Length = pRxPort->RxBufSize;
16504 pRxd->VDataLow = PhysLow;
16505 pRxd->VDataHigh = PhysHigh;
16506 @@ -1976,28 +3233,40 @@
16509 static void ReceiveIrq(
16510 - SK_AC *pAC, /* pointer to adapter context */
16511 - RX_PORT *pRxPort, /* pointer to receive port struct */
16512 - SK_BOOL SlowPathLock) /* indicates if SlowPathLock is needed */
16514 -RXD *pRxd; /* pointer to receive descriptors */
16515 -SK_U32 Control; /* control field of descriptor */
16516 -struct sk_buff *pMsg; /* pointer to message holding frame */
16517 -struct sk_buff *pNewMsg; /* pointer to a new message for copying frame */
16518 -int FrameLength; /* total length of received frame */
16519 -SK_MBUF *pRlmtMbuf; /* ptr to a buffer for giving a frame to rlmt */
16520 -SK_EVPARA EvPara; /* an event parameter union */
16521 -unsigned long Flags; /* for spin lock */
16522 -int PortIndex = pRxPort->PortIndex;
16523 -unsigned int Offset;
16524 -unsigned int NumBytes;
16525 -unsigned int ForRlmt;
16528 -SK_BOOL IsBadFrame; /* Bad frame */
16532 +#ifdef CONFIG_SK98LIN_NAPI
16533 +SK_AC *pAC, /* pointer to adapter context */
16534 +RX_PORT *pRxPort, /* pointer to receive port struct */
16535 +SK_BOOL SlowPathLock, /* indicates if SlowPathLock is needed */
16539 +SK_AC *pAC, /* pointer to adapter context */
16540 +RX_PORT *pRxPort, /* pointer to receive port struct */
16541 +SK_BOOL SlowPathLock) /* indicates if SlowPathLock is needed */
16544 + RXD *pRxd; /* pointer to receive descriptors */
16545 + struct sk_buff *pMsg; /* pointer to message holding frame */
16546 + struct sk_buff *pNewMsg; /* pointer to new message for frame copy */
16547 + SK_MBUF *pRlmtMbuf; /* ptr to buffer for giving frame to RLMT */
16548 + SK_EVPARA EvPara; /* an event parameter union */
16549 + SK_U32 Control; /* control field of descriptor */
16550 + unsigned long Flags; /* for spin lock handling */
16551 + int PortIndex = pRxPort->PortIndex;
16552 + int FrameLength; /* total length of received frame */
16553 + int IpFrameLength; /* IP length of the received frame */
16554 + unsigned int Offset;
16555 + unsigned int NumBytes;
16556 + unsigned int RlmtNotifier;
16557 + SK_BOOL IsBc; /* we received a broadcast packet */
16558 + SK_BOOL IsMc; /* we received a multicast packet */
16559 + SK_BOOL IsBadFrame; /* the frame received is bad! */
16560 + SK_U32 FrameStat;
16561 + unsigned short Csum1;
16562 + unsigned short Csum2;
16563 + unsigned short Type;
16568 /* do forever; exit if BMU_OWN found */
16569 @@ -2019,6 +3288,13 @@
16571 Control = pRxd->RBControl;
16573 +#ifdef CONFIG_SK98LIN_NAPI
16574 + if (*WorkDone >= WorkToDo) {
16580 /* check if this descriptor is ready */
16581 if ((Control & BMU_OWN) != 0) {
16582 /* this descriptor is not yet ready */
16583 @@ -2027,11 +3303,10 @@
16584 FillRxRing(pAC, pRxPort);
16587 - pAC->DynIrqModInfo.NbrProcessedDescr++;
16589 /* get length of frame and check it */
16590 FrameLength = Control & BMU_BBC;
16591 - if (FrameLength > pAC->RxBufSize) {
16592 + if (FrameLength > pRxPort->RxBufSize) {
16596 @@ -2046,8 +3321,8 @@
16597 FrameStat = pRxd->FrameStat;
16599 /* check for frame length mismatch */
16600 -#define XMR_FS_LEN_SHIFT 18
16601 -#define GMR_FS_LEN_SHIFT 16
16602 +#define XMR_FS_LEN_SHIFT 18
16603 +#define GMR_FS_LEN_SHIFT 16
16604 if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
16605 if (FrameLength != (SK_U32) (FrameStat >> XMR_FS_LEN_SHIFT)) {
16606 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
16607 @@ -2057,8 +3332,7 @@
16608 (SK_U32) (FrameStat >> XMR_FS_LEN_SHIFT)));
16614 if (FrameLength != (SK_U32) (FrameStat >> GMR_FS_LEN_SHIFT)) {
16615 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
16616 SK_DBGCAT_DRV_RX_PROGRESS,
16617 @@ -2091,9 +3365,6 @@
16618 /* DumpMsg(pMsg, "Rx"); */
16620 if ((Control & BMU_STAT_VAL) != BMU_STAT_VAL || (IsBadFrame)) {
16622 - (FrameStat & (XMR_FS_ANY_ERR | XMR_FS_2L_VLAN)) != 0) {
16624 /* there is a receive error in this frame */
16625 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
16626 SK_DBGCAT_DRV_RX_PROGRESS,
16627 @@ -2101,6 +3372,20 @@
16628 "Control: %x\nRxStat: %x\n",
16629 Control, FrameStat));
16631 + PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32;
16632 + PhysAddr |= (SK_U64) pRxd->VDataLow;
16634 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5)
16635 + pci_dma_sync_single(pAC->PciDev,
16636 + (dma_addr_t) PhysAddr,
16638 + PCI_DMA_FROMDEVICE);
16640 + pci_dma_sync_single_for_cpu(pAC->PciDev,
16641 + (dma_addr_t) PhysAddr,
16643 + PCI_DMA_FROMDEVICE);
16645 ReQueueRxBuffer(pAC, pRxPort, pMsg,
16646 pRxd->VDataHigh, pRxd->VDataLow);
16648 @@ -2120,96 +3405,107 @@
16649 skb_put(pNewMsg, FrameLength);
16650 PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32;
16651 PhysAddr |= (SK_U64) pRxd->VDataLow;
16653 - pci_dma_sync_single_for_cpu(pAC->PciDev,
16654 - (dma_addr_t) PhysAddr,
16656 - PCI_DMA_FROMDEVICE);
16657 - memcpy(pNewMsg->data, pMsg, FrameLength);
16659 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5)
16660 + pci_dma_sync_single(pAC->PciDev,
16661 + (dma_addr_t) PhysAddr,
16663 + PCI_DMA_FROMDEVICE);
16665 pci_dma_sync_single_for_device(pAC->PciDev,
16666 - (dma_addr_t) PhysAddr,
16668 - PCI_DMA_FROMDEVICE);
16669 + (dma_addr_t) PhysAddr,
16671 + PCI_DMA_FROMDEVICE);
16674 + eth_copy_and_sum(pNewMsg, pMsg->data,
16676 ReQueueRxBuffer(pAC, pRxPort, pMsg,
16677 pRxd->VDataHigh, pRxd->VDataLow);
16685 * if large frame, or SKB allocation failed, pass
16686 * the SKB directly to the networking
16689 PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32;
16690 PhysAddr |= (SK_U64) pRxd->VDataLow;
16692 /* release the DMA mapping */
16693 pci_unmap_single(pAC->PciDev,
16695 - pAC->RxBufSize - 2,
16696 + pRxPort->RxBufSize - 2,
16697 PCI_DMA_FROMDEVICE);
16698 + skb_put(pMsg, FrameLength); /* set message len */
16699 + pMsg->ip_summed = CHECKSUM_NONE; /* initial default */
16701 - /* set length in message */
16702 - skb_put(pMsg, FrameLength);
16703 + if (pRxPort->UseRxCsum) {
16704 + Type = ntohs(*((short*)&pMsg->data[12]));
16705 + if (Type == 0x800) {
16706 + IpFrameLength = (int) ntohs((unsigned short)
16707 + ((unsigned short *) pMsg->data)[8]);
16708 + if ((FrameLength - IpFrameLength) == 0xe) {
16709 + Csum1=le16_to_cpu(pRxd->TcpSums & 0xffff);
16710 + Csum2=le16_to_cpu((pRxd->TcpSums >> 16) & 0xffff);
16711 + if ((((Csum1 & 0xfffe) && (Csum2 & 0xfffe)) &&
16712 + (pAC->GIni.GIChipId == CHIP_ID_GENESIS)) ||
16713 + (pAC->ChipsetType)) {
16714 + Result = SkCsGetReceiveInfo(pAC, &pMsg->data[14],
16715 + Csum1, Csum2, PortIndex);
16716 + if ((Result == SKCS_STATUS_IP_FRAGMENT) ||
16717 + (Result == SKCS_STATUS_IP_CSUM_OK) ||
16718 + (Result == SKCS_STATUS_TCP_CSUM_OK) ||
16719 + (Result == SKCS_STATUS_UDP_CSUM_OK)) {
16720 + pMsg->ip_summed = CHECKSUM_UNNECESSARY;
16721 + } else if ((Result == SKCS_STATUS_TCP_CSUM_ERROR) ||
16722 + (Result == SKCS_STATUS_UDP_CSUM_ERROR) ||
16723 + (Result == SKCS_STATUS_IP_CSUM_ERROR_UDP) ||
16724 + (Result == SKCS_STATUS_IP_CSUM_ERROR_TCP) ||
16725 + (Result == SKCS_STATUS_IP_CSUM_ERROR)) {
16726 + /* HW Checksum error */
16727 + SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
16728 + SK_DBGCAT_DRV_RX_PROGRESS,
16729 + ("skge: CRC error. Frame dropped!\n"));
16732 + pMsg->ip_summed = CHECKSUM_NONE;
16734 + }/* checksumControl calculation valid */
16735 + } /* Frame length check */
16737 + } /* pRxPort->UseRxCsum */
16738 } /* frame > SK_COPY_TRESHOLD */
16740 -#ifdef USE_SK_RX_CHECKSUM
16741 - pMsg->csum = pRxd->TcpSums & 0xffff;
16742 - pMsg->ip_summed = CHECKSUM_COMPLETE;
16744 - pMsg->ip_summed = CHECKSUM_NONE;
16748 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("V"));
16749 - ForRlmt = SK_RLMT_RX_PROTOCOL;
16751 - IsBc = (FrameStat & XMR_FS_BC)==XMR_FS_BC;
16753 + RlmtNotifier = SK_RLMT_RX_PROTOCOL;
16754 SK_RLMT_PRE_LOOKAHEAD(pAC, PortIndex, FrameLength,
16755 - IsBc, &Offset, &NumBytes);
16756 + IsBc, &Offset, &NumBytes);
16757 if (NumBytes != 0) {
16759 - IsMc = (FrameStat & XMR_FS_MC)==XMR_FS_MC;
16761 - SK_RLMT_LOOKAHEAD(pAC, PortIndex,
16762 - &pMsg->data[Offset],
16763 - IsBc, IsMc, &ForRlmt);
16764 + SK_RLMT_LOOKAHEAD(pAC,PortIndex,&pMsg->data[Offset],
16765 + IsBc,IsMc,&RlmtNotifier);
16767 - if (ForRlmt == SK_RLMT_RX_PROTOCOL) {
16768 - SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("W"));
16769 + if (RlmtNotifier == SK_RLMT_RX_PROTOCOL) {
16770 + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("W"));
16771 /* send up only frames from active port */
16772 - if ((PortIndex == pAC->ActivePort) ||
16773 - (pAC->RlmtNets == 2)) {
16774 - /* frame for upper layer */
16775 + if ((PortIndex == pAC->ActivePort)||(pAC->RlmtNets == 2)) {
16776 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("U"));
16778 DumpMsg(pMsg, "Rx");
16780 - SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC,
16781 - FrameLength, pRxPort->PortIndex);
16783 - pMsg->dev = pAC->dev[pRxPort->PortIndex];
16784 - pMsg->protocol = eth_type_trans(pMsg,
16785 - pAC->dev[pRxPort->PortIndex]);
16787 - pAC->dev[pRxPort->PortIndex]->last_rx = jiffies;
16791 + SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC,FrameLength,PortIndex);
16792 + pMsg->dev = pAC->dev[PortIndex];
16793 + pMsg->protocol = eth_type_trans(pMsg,pAC->dev[PortIndex]);
16794 + netif_rx(pMsg); /* frame for upper layer */
16795 + pAC->dev[PortIndex]->last_rx = jiffies;
16797 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
16798 - SK_DBGCAT_DRV_RX_PROGRESS,
16800 - DEV_KFREE_SKB(pMsg);
16801 + SK_DBGCAT_DRV_RX_PROGRESS,("D"));
16802 + DEV_KFREE_SKB(pMsg); /* drop frame */
16805 - } /* if not for rlmt */
16807 - /* packet for rlmt */
16808 + } else { /* packet for RLMT stack */
16809 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
16810 - SK_DBGCAT_DRV_RX_PROGRESS, ("R"));
16811 + SK_DBGCAT_DRV_RX_PROGRESS,("R"));
16812 pRlmtMbuf = SkDrvAllocRlmtMbuf(pAC,
16813 pAC->IoBase, FrameLength);
16814 if (pRlmtMbuf != NULL) {
16815 @@ -2237,32 +3533,26 @@
16818 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
16819 - SK_DBGCAT_DRV_RX_PROGRESS,
16821 + SK_DBGCAT_DRV_RX_PROGRESS,("Q"));
16823 - if ((pAC->dev[pRxPort->PortIndex]->flags &
16824 - (IFF_PROMISC | IFF_ALLMULTI)) != 0 ||
16825 - (ForRlmt & SK_RLMT_RX_PROTOCOL) ==
16826 - SK_RLMT_RX_PROTOCOL) {
16827 - pMsg->dev = pAC->dev[pRxPort->PortIndex];
16828 - pMsg->protocol = eth_type_trans(pMsg,
16829 - pAC->dev[pRxPort->PortIndex]);
16830 + if ((pAC->dev[PortIndex]->flags & (IFF_PROMISC | IFF_ALLMULTI)) ||
16831 + (RlmtNotifier & SK_RLMT_RX_PROTOCOL)) {
16832 + pMsg->dev = pAC->dev[PortIndex];
16833 + pMsg->protocol = eth_type_trans(pMsg,pAC->dev[PortIndex]);
16834 +#ifdef CONFIG_SK98LIN_NAPI
16835 + netif_receive_skb(pMsg);
16838 - pAC->dev[pRxPort->PortIndex]->last_rx = jiffies;
16842 + pAC->dev[PortIndex]->last_rx = jiffies;
16844 DEV_KFREE_SKB(pMsg);
16847 - } /* if packet for rlmt */
16848 + } /* if packet for RLMT stack */
16849 } /* for ... scanning the RXD ring */
16851 /* RXD ring is empty -> fill and restart */
16852 FillRxRing(pAC, pRxPort);
16853 - /* do not start if called from Close */
16854 - if (pAC->BoardLevel > SK_INIT_DATA) {
16855 - ClearAndStartRx(pAC, PortIndex);
16860 @@ -2276,7 +3566,7 @@
16861 PhysAddr |= (SK_U64) pRxd->VDataLow;
16862 pci_unmap_page(pAC->PciDev,
16864 - pAC->RxBufSize - 2,
16865 + pRxPort->RxBufSize - 2,
16866 PCI_DMA_FROMDEVICE);
16867 DEV_KFREE_SKB_IRQ(pRxd->pMBuf);
16868 pRxd->pMBuf = NULL;
16869 @@ -2286,49 +3576,6 @@
16874 -/*****************************************************************************
16876 - * ClearAndStartRx - give a start receive command to BMU, clear IRQ
16879 - * This function sends a start command and a clear interrupt
16880 - * command for one receive queue to the BMU.
16885 -static void ClearAndStartRx(
16886 -SK_AC *pAC, /* pointer to the adapter context */
16887 -int PortIndex) /* index of the receive port (XMAC) */
16889 - SK_OUT8(pAC->IoBase,
16890 - RxQueueAddr[PortIndex]+Q_CSR,
16891 - CSR_START | CSR_IRQ_CL_F);
16892 -} /* ClearAndStartRx */
16895 -/*****************************************************************************
16897 - * ClearTxIrq - give a clear transmit IRQ command to BMU
16900 - * This function sends a clear tx IRQ command for one
16901 - * transmit queue to the BMU.
16905 -static void ClearTxIrq(
16906 -SK_AC *pAC, /* pointer to the adapter context */
16907 -int PortIndex, /* index of the transmit port (XMAC) */
16908 -int Prio) /* priority or normal queue */
16910 - SK_OUT8(pAC->IoBase,
16911 - TxQueueAddr[PortIndex][Prio]+Q_CSR,
16913 -} /* ClearTxIrq */
16916 /*****************************************************************************
16918 * ClearRxRing - remove all buffers from the receive ring
16919 @@ -2359,7 +3606,7 @@
16920 PhysAddr |= (SK_U64) pRxd->VDataLow;
16921 pci_unmap_page(pAC->PciDev,
16923 - pAC->RxBufSize - 2,
16924 + pRxPort->RxBufSize - 2,
16925 PCI_DMA_FROMDEVICE);
16926 DEV_KFREE_SKB(pRxd->pMBuf);
16927 pRxd->pMBuf = NULL;
16928 @@ -2417,31 +3664,32 @@
16929 static int SkGeSetMacAddr(struct SK_NET_DEVICE *dev, void *p)
16932 -DEV_NET *pNet = netdev_priv(dev);
16933 +DEV_NET *pNet = (DEV_NET*) dev->priv;
16934 SK_AC *pAC = pNet->pAC;
16937 struct sockaddr *addr = p;
16938 unsigned long Flags;
16940 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
16941 ("SkGeSetMacAddr starts now...\n"));
16942 - if(netif_running(dev))
16945 memcpy(dev->dev_addr, addr->sa_data,dev->addr_len);
16947 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
16949 if (pAC->RlmtNets == 2)
16950 - SkAddrOverride(pAC, pAC->IoBase, pNet->NetNr,
16951 + Ret = SkAddrOverride(pAC, pAC->IoBase, pNet->NetNr,
16952 (SK_MAC_ADDR*)dev->dev_addr, SK_ADDR_VIRTUAL_ADDRESS);
16954 - SkAddrOverride(pAC, pAC->IoBase, pAC->ActivePort,
16955 + Ret = SkAddrOverride(pAC, pAC->IoBase, pAC->ActivePort,
16956 (SK_MAC_ADDR*)dev->dev_addr, SK_ADDR_VIRTUAL_ADDRESS);
16960 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
16962 + if (Ret != SK_ADDR_OVERRIDE_SUCCESS)
16966 } /* SkGeSetMacAddr */
16968 @@ -2474,7 +3722,7 @@
16969 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
16970 ("SkGeSetRxMode starts now... "));
16972 - pNet = netdev_priv(dev);
16973 + pNet = (DEV_NET*) dev->priv;
16975 if (pAC->RlmtNets == 1)
16976 PortIdx = pAC->ActivePort;
16977 @@ -2523,6 +3771,45 @@
16979 /*****************************************************************************
16981 + * SkSetMtuBufferSize - set the MTU buffer to another value
16984 + * This function sets the new buffers and is called whenever the MTU
16985 + * size is changed
16991 +static void SkSetMtuBufferSize(
16992 +SK_AC *pAC, /* pointer to adapter context */
16993 +int PortNr, /* Port number */
16994 +int Mtu) /* pointer to tx prt struct */
16996 + pAC->RxPort[PortNr].RxBufSize = Mtu + 32;
16998 + /* RxBufSize must be a multiple of 8 */
16999 + while (pAC->RxPort[PortNr].RxBufSize % 8) {
17000 + pAC->RxPort[PortNr].RxBufSize =
17001 + pAC->RxPort[PortNr].RxBufSize + 1;
17004 + if (Mtu > 1500) {
17005 + pAC->GIni.GP[PortNr].PPortUsage = SK_JUMBO_LINK;
17007 + if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
17008 + pAC->GIni.GP[PortNr].PPortUsage = SK_MUL_LINK;
17010 + pAC->GIni.GP[PortNr].PPortUsage = SK_RED_LINK;
17018 +/*****************************************************************************
17020 * SkGeChangeMtu - set the MTU to another value
17023 @@ -2536,28 +3823,32 @@
17025 static int SkGeChangeMtu(struct SK_NET_DEVICE *dev, int NewMtu)
17028 -struct net_device *pOtherDev;
17030 -unsigned long Flags;
17035 +unsigned long Flags;
17036 +#ifdef CONFIG_SK98LIN_NAPI
17037 +int WorkToDo = 1; // min(*budget, dev->quota);
17041 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
17042 ("SkGeChangeMtu starts now...\n"));
17044 - pNet = netdev_priv(dev);
17045 + pNet = (DEV_NET*) dev->priv;
17048 + /* MTU size outside the spec */
17049 if ((NewMtu < 68) || (NewMtu > SK_JUMBO_MTU)) {
17053 - if(pAC->BoardLevel != SK_INIT_RUN) {
17054 + /* MTU > 1500 on yukon FE not allowed */
17055 + if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_FE)
17056 + && (NewMtu > 1500)){
17060 -#ifdef SK_DIAG_SUPPORT
17061 + /* Diag access active */
17062 if (pAC->DiagModeActive == DIAG_ACTIVE) {
17063 if (pAC->DiagFlowCtrl == SK_FALSE) {
17064 return -1; /* still in use, deny any actions of MTU */
17065 @@ -2565,201 +3856,74 @@
17066 pAC->DiagFlowCtrl = SK_FALSE;
17071 - pOtherDev = pAC->dev[1 - pNet->NetNr];
17073 - if ( netif_running(pOtherDev) && (pOtherDev->mtu > 1500)
17074 - && (NewMtu <= 1500))
17077 - pAC->RxBufSize = NewMtu + 32;
17079 + SkSetMtuBufferSize(pAC, pNet->PortNr, NewMtu);
17081 - SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
17082 - ("New MTU: %d\n", NewMtu));
17083 + if(!netif_running(dev)) {
17084 + /* Preset MTU size if device not ready/running */
17089 - ** Prevent any reconfiguration while changing the MTU
17090 - ** by disabling any interrupts
17092 + /* Prevent any reconfiguration while changing the MTU
17093 + by disabling any interrupts */
17094 SK_OUT32(pAC->IoBase, B0_IMSK, 0);
17095 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
17098 - ** Notify RLMT that any ports are to be stopped
17100 - EvPara.Para32[0] = 0;
17101 - EvPara.Para32[1] = -1;
17102 - if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
17103 - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
17104 - EvPara.Para32[0] = 1;
17105 - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
17107 - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
17111 - ** After calling the SkEventDispatcher(), RLMT is aware about
17112 - ** the stopped ports -> configuration can take place!
17114 - SkEventDispatcher(pAC, pAC->IoBase);
17116 - for (i=0; i<pAC->GIni.GIMacsFound; i++) {
17117 - spin_lock(&pAC->TxPort[i][TX_PRIO_LOW].TxDesRingLock);
17118 - netif_stop_queue(pAC->dev[i]);
17119 + /* Notify RLMT that the port has to be stopped */
17120 + netif_stop_queue(dev);
17121 + SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP,
17122 + pNet->PortNr, -1, SK_TRUE);
17123 + spin_lock(&pAC->TxPort[pNet->PortNr][TX_PRIO_LOW].TxDesRingLock);
17128 - ** Depending on the desired MTU size change, a different number of
17129 - ** RX buffers need to be allocated
17131 - if (NewMtu > 1500) {
17133 - ** Use less rx buffers
17135 - for (i=0; i<pAC->GIni.GIMacsFound; i++) {
17136 - if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
17137 - pAC->RxPort[i].RxFillLimit = pAC->RxDescrPerRing -
17138 - (pAC->RxDescrPerRing / 4);
17140 - if (i == pAC->ActivePort) {
17141 - pAC->RxPort[i].RxFillLimit = pAC->RxDescrPerRing -
17142 - (pAC->RxDescrPerRing / 4);
17144 - pAC->RxPort[i].RxFillLimit = pAC->RxDescrPerRing -
17145 - (pAC->RxDescrPerRing / 10);
17149 + /* Change RxFillLimit to 1 */
17150 + if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
17151 + pAC->RxPort[pNet->PortNr].RxFillLimit = 1;
17154 - ** Use the normal amount of rx buffers
17156 - for (i=0; i<pAC->GIni.GIMacsFound; i++) {
17157 - if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
17158 - pAC->RxPort[i].RxFillLimit = 1;
17160 - if (i == pAC->ActivePort) {
17161 - pAC->RxPort[i].RxFillLimit = 1;
17163 - pAC->RxPort[i].RxFillLimit = pAC->RxDescrPerRing -
17164 - (pAC->RxDescrPerRing / 4);
17168 + pAC->RxPort[1 - pNet->PortNr].RxFillLimit = 1;
17169 + pAC->RxPort[pNet->PortNr].RxFillLimit = pAC->RxDescrPerRing -
17170 + (pAC->RxDescrPerRing / 4);
17173 - SkGeDeInit(pAC, pAC->IoBase);
17176 - ** enable/disable hardware support for long frames
17178 - if (NewMtu > 1500) {
17179 -// pAC->JumboActivated = SK_TRUE; /* is never set back !!! */
17180 - pAC->GIni.GIPortUsage = SK_JUMBO_LINK;
17181 + /* clear and reinit the rx rings here, because of new MTU size */
17182 + if (CHIP_ID_YUKON_2(pAC)) {
17183 + SkY2PortStop(pAC, pAC->IoBase, pNet->PortNr, SK_STOP_ALL, SK_SOFT_RST);
17184 + SkY2AllocateRxBuffers(pAC, pAC->IoBase, pNet->PortNr);
17185 + SkY2PortStart(pAC, pAC->IoBase, pNet->PortNr);
17187 - if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
17188 - pAC->GIni.GIPortUsage = SK_MUL_LINK;
17190 - pAC->GIni.GIPortUsage = SK_RED_LINK;
17193 +// SkGeStopPort(pAC, pAC->IoBase, pNet->PortNr, SK_STOP_ALL, SK_SOFT_RST);
17194 +#ifdef CONFIG_SK98LIN_NAPI
17196 + ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE, &WorkDone, WorkToDo);
17198 + ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE);
17200 + ClearRxRing(pAC, &pAC->RxPort[pNet->PortNr]);
17201 + FillRxRing(pAC, &pAC->RxPort[pNet->PortNr]);
17203 - SkGeInit( pAC, pAC->IoBase, SK_INIT_IO);
17204 - SkI2cInit( pAC, pAC->IoBase, SK_INIT_IO);
17205 - SkEventInit(pAC, pAC->IoBase, SK_INIT_IO);
17206 - SkPnmiInit( pAC, pAC->IoBase, SK_INIT_IO);
17207 - SkAddrInit( pAC, pAC->IoBase, SK_INIT_IO);
17208 - SkRlmtInit( pAC, pAC->IoBase, SK_INIT_IO);
17209 - SkTimerInit(pAC, pAC->IoBase, SK_INIT_IO);
17213 - ** Speed and others are set back to default in level 1 init!
17215 - GetConfiguration(pAC);
17217 - SkGeInit( pAC, pAC->IoBase, SK_INIT_RUN);
17218 - SkI2cInit( pAC, pAC->IoBase, SK_INIT_RUN);
17219 - SkEventInit(pAC, pAC->IoBase, SK_INIT_RUN);
17220 - SkPnmiInit( pAC, pAC->IoBase, SK_INIT_RUN);
17221 - SkAddrInit( pAC, pAC->IoBase, SK_INIT_RUN);
17222 - SkRlmtInit( pAC, pAC->IoBase, SK_INIT_RUN);
17223 - SkTimerInit(pAC, pAC->IoBase, SK_INIT_RUN);
17224 + /* Enable transmit descriptor polling */
17225 + SkGePollTxD(pAC, pAC->IoBase, pNet->PortNr, SK_TRUE);
17226 + FillRxRing(pAC, &pAC->RxPort[pNet->PortNr]);
17230 - ** clear and reinit the rx rings here
17232 - for (i=0; i<pAC->GIni.GIMacsFound; i++) {
17233 - ReceiveIrq(pAC, &pAC->RxPort[i], SK_TRUE);
17234 - ClearRxRing(pAC, &pAC->RxPort[i]);
17235 - FillRxRing(pAC, &pAC->RxPort[i]);
17236 + netif_start_queue(pAC->dev[pNet->PortNr]);
17239 - ** Enable transmit descriptor polling
17241 - SkGePollTxD(pAC, pAC->IoBase, i, SK_TRUE);
17242 - FillRxRing(pAC, &pAC->RxPort[i]);
17244 + spin_unlock(&pAC->TxPort[pNet->PortNr][TX_PRIO_LOW].TxDesRingLock);
17246 - SkGeYellowLED(pAC, pAC->IoBase, 1);
17247 - SkDimEnableModerationIfNeeded(pAC);
17248 - SkDimDisplayModerationSettings(pAC);
17250 - netif_start_queue(pAC->dev[pNet->PortNr]);
17251 - for (i=pAC->GIni.GIMacsFound-1; i>=0; i--) {
17252 - spin_unlock(&pAC->TxPort[i][TX_PRIO_LOW].TxDesRingLock);
17254 + /* Notify RLMT about the changing and restarting one (or more) ports */
17255 + SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_START,
17256 + pNet->PortNr, -1, SK_TRUE);
17259 - ** Enable Interrupts again
17261 + /* Enable Interrupts again */
17262 SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
17263 SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK);
17265 - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara);
17266 - SkEventDispatcher(pAC, pAC->IoBase);
17269 - ** Notify RLMT about the changing and restarting one (or more) ports
17271 - if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
17272 - EvPara.Para32[0] = pAC->RlmtNets;
17273 - EvPara.Para32[1] = -1;
17274 - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_SET_NETS, EvPara);
17275 - EvPara.Para32[0] = pNet->PortNr;
17276 - EvPara.Para32[1] = -1;
17277 - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara);
17279 - if (netif_running(pOtherDev)) {
17280 - DEV_NET *pOtherNet = netdev_priv(pOtherDev);
17281 - EvPara.Para32[0] = pOtherNet->PortNr;
17282 - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara);
17285 - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara);
17288 - SkEventDispatcher(pAC, pAC->IoBase);
17289 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
17292 - ** While testing this driver with latest kernel 2.5 (2.5.70), it
17293 - ** seems as if upper layers have a problem to handle a successful
17294 - ** return value of '0'. If such a zero is returned, the complete
17295 - ** system hangs for several minutes (!), which is in acceptable.
17297 - ** Currently it is not clear, what the exact reason for this problem
17298 - ** is. The implemented workaround for 2.5 is to return the desired
17299 - ** new MTU size if all needed changes for the new MTU size where
17300 - ** performed. In kernels 2.2 and 2.4, a zero value is returned,
17301 - ** which indicates the successful change of the mtu-size.
17306 -} /* SkGeChangeMtu */
17310 /*****************************************************************************
17311 @@ -2775,75 +3939,67 @@
17313 static struct net_device_stats *SkGeStats(struct SK_NET_DEVICE *dev)
17315 -DEV_NET *pNet = netdev_priv(dev);
17316 -SK_AC *pAC = pNet->pAC;
17317 -SK_PNMI_STRUCT_DATA *pPnmiStruct; /* structure for all Pnmi-Data */
17318 -SK_PNMI_STAT *pPnmiStat; /* pointer to virtual XMAC stat. data */
17319 -SK_PNMI_CONF *pPnmiConf; /* pointer to virtual link config. */
17320 -unsigned int Size; /* size of pnmi struct */
17321 -unsigned long Flags; /* for spin lock */
17323 - SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
17324 - ("SkGeStats starts now...\n"));
17325 - pPnmiStruct = &pAC->PnmiStruct;
17326 + DEV_NET *pNet = (DEV_NET*) dev->priv;
17327 + SK_AC *pAC = pNet->pAC;
17328 + unsigned long LateCollisions, ExcessiveCollisions, RxTooLong;
17329 + unsigned long Flags; /* for spin lock */
17330 + SK_U32 MaxNumOidEntries, Oid, Len;
17334 + unsigned long *pVar;
17336 + { OID_SKGE_STAT_TX_LATE_COL, &LateCollisions },
17337 + { OID_SKGE_STAT_TX_EXCESS_COL, &ExcessiveCollisions },
17338 + { OID_SKGE_STAT_RX_TOO_LONG, &RxTooLong },
17339 + { OID_SKGE_STAT_RX, &pAC->stats.rx_packets },
17340 + { OID_SKGE_STAT_TX, &pAC->stats.tx_packets },
17341 + { OID_SKGE_STAT_RX_OCTETS, &pAC->stats.rx_bytes },
17342 + { OID_SKGE_STAT_TX_OCTETS, &pAC->stats.tx_bytes },
17343 + { OID_SKGE_RX_NO_BUF_CTS, &pAC->stats.rx_dropped },
17344 + { OID_SKGE_TX_NO_BUF_CTS, &pAC->stats.tx_dropped },
17345 + { OID_SKGE_STAT_RX_MULTICAST, &pAC->stats.multicast },
17346 + { OID_SKGE_STAT_RX_RUNT, &pAC->stats.rx_length_errors },
17347 + { OID_SKGE_STAT_RX_FCS, &pAC->stats.rx_crc_errors },
17348 + { OID_SKGE_STAT_RX_FRAMING, &pAC->stats.rx_frame_errors },
17349 + { OID_SKGE_STAT_RX_OVERFLOW, &pAC->stats.rx_over_errors },
17350 + { OID_SKGE_STAT_RX_MISSED, &pAC->stats.rx_missed_errors },
17351 + { OID_SKGE_STAT_TX_CARRIER, &pAC->stats.tx_carrier_errors },
17352 + { OID_SKGE_STAT_TX_UNDERRUN, &pAC->stats.tx_fifo_errors },
17355 + if ((pAC->DiagModeActive == DIAG_NOTACTIVE) &&
17356 + (pAC->BoardLevel == SK_INIT_RUN)) {
17357 + memset(&pAC->stats, 0x00, sizeof(pAC->stats)); /* clean first */
17358 + spin_lock_irqsave(&pAC->SlowPathLock, Flags);
17360 -#ifdef SK_DIAG_SUPPORT
17361 - if ((pAC->DiagModeActive == DIAG_NOTACTIVE) &&
17362 - (pAC->BoardLevel == SK_INIT_RUN)) {
17364 - SK_MEMSET(pPnmiStruct, 0, sizeof(SK_PNMI_STRUCT_DATA));
17365 - spin_lock_irqsave(&pAC->SlowPathLock, Flags);
17366 - Size = SK_PNMI_STRUCT_SIZE;
17367 - SkPnmiGetStruct(pAC, pAC->IoBase, pPnmiStruct, &Size, pNet->NetNr);
17368 - spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
17369 -#ifdef SK_DIAG_SUPPORT
17372 + MaxNumOidEntries = sizeof(Vars) / sizeof(Vars[0]);
17373 + for (Oid = 0; Oid < MaxNumOidEntries; Oid++) {
17374 + if (SkPnmiGetVar(pAC,pAC->IoBase, Vars[Oid].Oid,
17375 + &Buf, &Len, 1, pNet->NetNr) != SK_PNMI_ERR_OK) {
17376 + memset(Buf, 0x00, sizeof(Buf));
17378 + *Vars[Oid].pVar = (unsigned long) (*((SK_U64 *) Buf));
17380 + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
17382 - pPnmiStat = &pPnmiStruct->Stat[0];
17383 - pPnmiConf = &pPnmiStruct->Conf[0];
17384 + pAC->stats.collisions = LateCollisions + ExcessiveCollisions;
17385 + pAC->stats.tx_errors = pAC->stats.tx_carrier_errors +
17386 + pAC->stats.tx_fifo_errors;
17387 + pAC->stats.rx_errors = pAC->stats.rx_length_errors +
17388 + pAC->stats.rx_crc_errors +
17389 + pAC->stats.rx_frame_errors +
17390 + pAC->stats.rx_over_errors +
17391 + pAC->stats.rx_missed_errors;
17393 - pAC->stats.rx_packets = (SK_U32) pPnmiStruct->RxDeliveredCts & 0xFFFFFFFF;
17394 - pAC->stats.tx_packets = (SK_U32) pPnmiStat->StatTxOkCts & 0xFFFFFFFF;
17395 - pAC->stats.rx_bytes = (SK_U32) pPnmiStruct->RxOctetsDeliveredCts;
17396 - pAC->stats.tx_bytes = (SK_U32) pPnmiStat->StatTxOctetsOkCts;
17398 - if (dev->mtu <= 1500) {
17399 - pAC->stats.rx_errors = (SK_U32) pPnmiStruct->InErrorsCts & 0xFFFFFFFF;
17401 - pAC->stats.rx_errors = (SK_U32) ((pPnmiStruct->InErrorsCts -
17402 - pPnmiStat->StatRxTooLongCts) & 0xFFFFFFFF);
17403 + if (dev->mtu > 1500) {
17404 + pAC->stats.rx_errors = pAC->stats.rx_errors - RxTooLong;
17409 - if (pAC->GIni.GP[0].PhyType == SK_PHY_XMAC && pAC->HWRevision < 12)
17410 - pAC->stats.rx_errors = pAC->stats.rx_errors - pPnmiStat->StatRxShortsCts;
17412 - pAC->stats.tx_errors = (SK_U32) pPnmiStat->StatTxSingleCollisionCts & 0xFFFFFFFF;
17413 - pAC->stats.rx_dropped = (SK_U32) pPnmiStruct->RxNoBufCts & 0xFFFFFFFF;
17414 - pAC->stats.tx_dropped = (SK_U32) pPnmiStruct->TxNoBufCts & 0xFFFFFFFF;
17415 - pAC->stats.multicast = (SK_U32) pPnmiStat->StatRxMulticastOkCts & 0xFFFFFFFF;
17416 - pAC->stats.collisions = (SK_U32) pPnmiStat->StatTxSingleCollisionCts & 0xFFFFFFFF;
17418 - /* detailed rx_errors: */
17419 - pAC->stats.rx_length_errors = (SK_U32) pPnmiStat->StatRxRuntCts & 0xFFFFFFFF;
17420 - pAC->stats.rx_over_errors = (SK_U32) pPnmiStat->StatRxFifoOverflowCts & 0xFFFFFFFF;
17421 - pAC->stats.rx_crc_errors = (SK_U32) pPnmiStat->StatRxFcsCts & 0xFFFFFFFF;
17422 - pAC->stats.rx_frame_errors = (SK_U32) pPnmiStat->StatRxFramingCts & 0xFFFFFFFF;
17423 - pAC->stats.rx_fifo_errors = (SK_U32) pPnmiStat->StatRxFifoOverflowCts & 0xFFFFFFFF;
17424 - pAC->stats.rx_missed_errors = (SK_U32) pPnmiStat->StatRxMissedCts & 0xFFFFFFFF;
17426 - /* detailed tx_errors */
17427 - pAC->stats.tx_aborted_errors = (SK_U32) 0;
17428 - pAC->stats.tx_carrier_errors = (SK_U32) pPnmiStat->StatTxCarrierCts & 0xFFFFFFFF;
17429 - pAC->stats.tx_fifo_errors = (SK_U32) pPnmiStat->StatTxFifoUnderrunCts & 0xFFFFFFFF;
17430 - pAC->stats.tx_heartbeat_errors = (SK_U32) pPnmiStat->StatTxCarrierCts & 0xFFFFFFFF;
17431 - pAC->stats.tx_window_errors = (SK_U32) 0;
17433 return(&pAC->stats);
17437 /*****************************************************************************
17439 * SkGeIoctl - IO-control function
17440 @@ -2851,38 +4007,41 @@
17442 * This function is called if an ioctl is issued on the device.
17443 * There are three subfunction for reading, writing and test-writing
17444 - * the private MIB data structure (useful for SysKonnect-internal tools).
17445 + * the private MIB data structure (usefull for SysKonnect-internal tools).
17448 * 0, if everything is ok
17451 -static int SkGeIoctl(struct SK_NET_DEVICE *dev, struct ifreq *rq, int cmd)
17456 -struct pci_dev *pdev = NULL;
17457 -SK_GE_IOCTL Ioctl;
17458 -unsigned int Err = 0;
17461 -unsigned int Length = 0;
17462 -int HeaderLength = sizeof(SK_U32) + sizeof(SK_U32);
17463 +static int SkGeIoctl(
17464 +struct SK_NET_DEVICE *dev, /* the device the IOCTL is to be performed on */
17465 +struct ifreq *rq, /* additional request structure containing data */
17466 +int cmd) /* requested IOCTL command number */
17468 + DEV_NET *pNet = (DEV_NET*) dev->priv;
17469 + SK_AC *pAC = pNet->pAC;
17470 + struct pci_dev *pdev = NULL;
17472 + SK_GE_IOCTL Ioctl;
17473 + unsigned long Flags; /* for spin lock */
17474 + unsigned int Err = 0;
17475 + unsigned int Length = 0;
17476 + int HeaderLength = sizeof(SK_U32) + sizeof(SK_U32);
17480 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
17481 ("SkGeIoctl starts now...\n"));
17483 - pNet = netdev_priv(dev);
17486 if(copy_from_user(&Ioctl, rq->ifr_data, sizeof(SK_GE_IOCTL))) {
17491 - case SK_IOCTL_SETMIB:
17492 - case SK_IOCTL_PRESETMIB:
17493 + case SIOCETHTOOL:
17494 + return SkEthIoctl(dev, rq);
17495 + case SK_IOCTL_SETMIB: /* FALL THRU */
17496 + case SK_IOCTL_PRESETMIB: /* FALL THRU (if capable!) */
17497 if (!capable(CAP_NET_ADMIN)) return -EPERM;
17498 case SK_IOCTL_GETMIB:
17499 if(copy_from_user(&pAC->PnmiStruct, Ioctl.pData,
17500 @@ -2909,6 +4068,7 @@
17501 if (NULL == (pMemBuf = kmalloc(Length, GFP_KERNEL))) {
17504 + spin_lock_irqsave(&pAC->SlowPathLock, Flags);
17505 if(copy_from_user(pMemBuf, Ioctl.pData, Length)) {
17508 @@ -2927,10 +4087,10 @@
17512 + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
17513 kfree(pMemBuf); /* cleanup everything */
17515 -#ifdef SK_DIAG_SUPPORT
17516 - case SK_IOCTL_DIAG:
17517 + case SK_IOCTL_DIAG:
17518 if (!capable(CAP_NET_ADMIN)) return -EPERM;
17519 if (Ioctl.Len < (sizeof(pAC->PnmiStruct) + HeaderLength)) {
17520 Length = Ioctl.Len;
17521 @@ -2967,7 +4127,6 @@
17523 kfree(pMemBuf); /* cleanup everything */
17529 @@ -2999,12 +4158,12 @@
17530 unsigned int Size, /* length of ioctl data */
17531 int mode) /* flag for set/preset */
17533 -unsigned long Flags; /* for spin lock */
17535 + SK_AC *pAC = pNet->pAC;
17536 + unsigned long Flags; /* for spin lock */
17538 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
17539 ("SkGeIocMib starts now...\n"));
17543 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
17545 @@ -3047,17 +4206,18 @@
17546 SK_I32 Port; /* preferred port */
17549 -int LinkSpeed = SK_LSPEED_AUTO; /* Link speed */
17550 -int AutoNeg = 1; /* autoneg off (0) or on (1) */
17551 -int DuplexCap = 0; /* 0=both,1=full,2=half */
17552 -int FlowCtrl = SK_FLOW_MODE_SYM_OR_REM; /* FlowControl */
17553 -int MSMode = SK_MS_MODE_AUTO; /* master/slave mode */
17555 -SK_BOOL IsConTypeDefined = SK_TRUE;
17556 -SK_BOOL IsLinkSpeedDefined = SK_TRUE;
17557 -SK_BOOL IsFlowCtrlDefined = SK_TRUE;
17558 -SK_BOOL IsRoleDefined = SK_TRUE;
17559 -SK_BOOL IsModeDefined = SK_TRUE;
17560 +int LinkSpeed = SK_LSPEED_AUTO; /* Link speed */
17561 +int AutoNeg = 1; /* autoneg off (0) or on (1) */
17562 +int DuplexCap = 0; /* 0=both,1=full,2=half */
17563 +int FlowCtrl = SK_FLOW_MODE_SYM_OR_REM; /* FlowControl */
17564 +int MSMode = SK_MS_MODE_AUTO; /* master/slave mode */
17565 +int IrqModMaskOffset = 6; /* all ints moderated=default */
17567 +SK_BOOL IsConTypeDefined = SK_TRUE;
17568 +SK_BOOL IsLinkSpeedDefined = SK_TRUE;
17569 +SK_BOOL IsFlowCtrlDefined = SK_TRUE;
17570 +SK_BOOL IsRoleDefined = SK_TRUE;
17571 +SK_BOOL IsModeDefined = SK_TRUE;
17573 * The two parameters AutoNeg. and DuplexCap. map to one configuration
17574 * parameter. The mapping is described by this table:
17575 @@ -3075,6 +4235,15 @@
17576 {SK_LMODE_AUTOBOTH , SK_LMODE_AUTOFULL , SK_LMODE_AUTOHALF },
17577 {SK_LMODE_AUTOSENSE, SK_LMODE_AUTOSENSE, SK_LMODE_AUTOSENSE} };
17579 +SK_U32 IrqModMask[7][2] =
17580 + { { IRQ_MASK_RX_ONLY , Y2_DRIVER_IRQS },
17581 + { IRQ_MASK_TX_ONLY , Y2_DRIVER_IRQS },
17582 + { IRQ_MASK_SP_ONLY , Y2_SPECIAL_IRQS },
17583 + { IRQ_MASK_SP_RX , Y2_IRQ_MASK },
17584 + { IRQ_MASK_TX_RX , Y2_DRIVER_IRQS },
17585 + { IRQ_MASK_SP_TX , Y2_IRQ_MASK },
17586 + { IRQ_MASK_RX_TX_SP, Y2_IRQ_MASK } };
17591 @@ -3107,6 +4276,7 @@
17592 ** ConType DupCap AutoNeg FlowCtrl Role Speed
17593 ** ------- ------ ------- -------- ---------- -----
17594 ** Auto Both On SymOrRem Auto Auto
17595 + ** 1000FD Full Off None <ignored> 1000
17596 ** 100FD Full Off None <ignored> 100
17597 ** 100HD Half Off None <ignored> 100
17598 ** 10FD Full Off None <ignored> 10
17599 @@ -3114,66 +4284,86 @@
17601 ** This ConType parameter is used for all ports of the adapter!
17603 - if ( (ConType != NULL) &&
17604 + if ( (ConType != NULL) &&
17605 (pAC->Index < SK_MAX_CARD_PARAM) &&
17606 (ConType[pAC->Index] != NULL) ) {
17608 - /* Check chipset family */
17609 - if ((!pAC->ChipsetType) &&
17610 - (strcmp(ConType[pAC->Index],"Auto")!=0) &&
17611 - (strcmp(ConType[pAC->Index],"")!=0)) {
17612 - /* Set the speed parameter back */
17613 - printk("sk98lin: Illegal value \"%s\" "
17615 - " Using Auto.\n",
17616 - ConType[pAC->Index]);
17618 - sprintf(ConType[pAC->Index], "Auto");
17620 + /* Check chipset family */
17621 + if ((!pAC->ChipsetType) &&
17622 + (strcmp(ConType[pAC->Index],"Auto")!=0) &&
17623 + (strcmp(ConType[pAC->Index],"")!=0)) {
17624 + /* Set the speed parameter back */
17625 + printk("sk98lin: Illegal value \"%s\" "
17627 + " Using Auto.\n",
17628 + ConType[pAC->Index]);
17630 + ConType[pAC->Index] = "Auto";
17633 + if ((pAC->ChipsetType) &&
17634 + (pAC->GIni.GICopperType != SK_TRUE) &&
17635 + (strcmp(ConType[pAC->Index],"") != 0) &&
17636 + (strcmp(ConType[pAC->Index],"1000FD") != 0)) {
17637 + /* Set the speed parameter back */
17638 + printk("sk98lin: Illegal value \"%s\" "
17640 + " Using Auto.\n",
17641 + ConType[pAC->Index]);
17642 + IsConTypeDefined = SK_FALSE;
17643 + ConType[pAC->Index] = "Auto";
17646 - if (strcmp(ConType[pAC->Index],"")==0) {
17647 + if (strcmp(ConType[pAC->Index],"")==0) {
17648 IsConTypeDefined = SK_FALSE; /* No ConType defined */
17649 - } else if (strcmp(ConType[pAC->Index],"Auto")==0) {
17650 + } else if (strcmp(ConType[pAC->Index],"Auto")==0) {
17651 for (Port = 0; Port < SK_MAX_MACS; Port++) {
17652 M_CurrPort.PLinkModeConf = Capabilities[AN_ON][DC_BOTH];
17653 M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_SYM_OR_REM;
17654 M_CurrPort.PMSMode = SK_MS_MODE_AUTO;
17655 M_CurrPort.PLinkSpeed = SK_LSPEED_AUTO;
17657 - } else if (strcmp(ConType[pAC->Index],"100FD")==0) {
17658 + } else if (strcmp(ConType[pAC->Index],"1000FD")==0) {
17659 + for (Port = 0; Port < SK_MAX_MACS; Port++) {
17660 + M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_FULL];
17661 + M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE;
17662 + M_CurrPort.PMSMode = SK_MS_MODE_AUTO;
17663 + M_CurrPort.PLinkSpeed = SK_LSPEED_1000MBPS;
17665 + } else if (strcmp(ConType[pAC->Index],"100FD")==0) {
17666 for (Port = 0; Port < SK_MAX_MACS; Port++) {
17667 M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_FULL];
17668 M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE;
17669 M_CurrPort.PMSMode = SK_MS_MODE_AUTO;
17670 M_CurrPort.PLinkSpeed = SK_LSPEED_100MBPS;
17672 - } else if (strcmp(ConType[pAC->Index],"100HD")==0) {
17673 + } else if (strcmp(ConType[pAC->Index],"100HD")==0) {
17674 for (Port = 0; Port < SK_MAX_MACS; Port++) {
17675 M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_HALF];
17676 M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE;
17677 M_CurrPort.PMSMode = SK_MS_MODE_AUTO;
17678 M_CurrPort.PLinkSpeed = SK_LSPEED_100MBPS;
17680 - } else if (strcmp(ConType[pAC->Index],"10FD")==0) {
17681 + } else if (strcmp(ConType[pAC->Index],"10FD")==0) {
17682 for (Port = 0; Port < SK_MAX_MACS; Port++) {
17683 M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_FULL];
17684 M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE;
17685 M_CurrPort.PMSMode = SK_MS_MODE_AUTO;
17686 M_CurrPort.PLinkSpeed = SK_LSPEED_10MBPS;
17688 - } else if (strcmp(ConType[pAC->Index],"10HD")==0) {
17689 + } else if (strcmp(ConType[pAC->Index],"10HD")==0) {
17690 for (Port = 0; Port < SK_MAX_MACS; Port++) {
17691 M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_HALF];
17692 M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE;
17693 M_CurrPort.PMSMode = SK_MS_MODE_AUTO;
17694 M_CurrPort.PLinkSpeed = SK_LSPEED_10MBPS;
17698 printk("sk98lin: Illegal value \"%s\" for ConType\n",
17699 ConType[pAC->Index]);
17700 IsConTypeDefined = SK_FALSE; /* Wrong ConType defined */
17704 IsConTypeDefined = SK_FALSE; /* No ConType defined */
17707 @@ -3192,14 +4382,30 @@
17708 } else if (strcmp(Speed_A[pAC->Index],"100")==0) {
17709 LinkSpeed = SK_LSPEED_100MBPS;
17710 } else if (strcmp(Speed_A[pAC->Index],"1000")==0) {
17711 - LinkSpeed = SK_LSPEED_1000MBPS;
17712 + if ((pAC->PciDev->vendor == 0x11ab ) &&
17713 + (pAC->PciDev->device == 0x4350)) {
17714 + LinkSpeed = SK_LSPEED_100MBPS;
17715 + printk("sk98lin: Illegal value \"%s\" for Speed_A.\n"
17716 + "Gigabit speed not possible with this chip revision!",
17717 + Speed_A[pAC->Index]);
17719 + LinkSpeed = SK_LSPEED_1000MBPS;
17722 printk("sk98lin: Illegal value \"%s\" for Speed_A\n",
17723 Speed_A[pAC->Index]);
17724 IsLinkSpeedDefined = SK_FALSE;
17727 - IsLinkSpeedDefined = SK_FALSE;
17728 + if ((pAC->PciDev->vendor == 0x11ab ) &&
17729 + (pAC->PciDev->device == 0x4350)) {
17730 + /* Gigabit speed not supported
17731 + * Swith to speed 100
17733 + LinkSpeed = SK_LSPEED_100MBPS;
17735 + IsLinkSpeedDefined = SK_FALSE;
17740 @@ -3294,9 +4500,6 @@
17743 if (!AutoSet && DupSet) {
17744 - printk("sk98lin: Port A: Duplex setting not"
17745 - " possible in\n default AutoNegotiation mode"
17746 - " (Sense).\n Using AutoNegotiation On\n");
17750 @@ -3324,7 +4527,7 @@
17751 FlowCtrl = SK_FLOW_MODE_NONE;
17753 printk("sk98lin: Illegal value \"%s\" for FlowCtrl_A\n",
17754 - FlowCtrl_A[pAC->Index]);
17755 + FlowCtrl_A[pAC->Index]);
17756 IsFlowCtrlDefined = SK_FALSE;
17759 @@ -3416,7 +4619,7 @@
17760 ** Decide whether to set new config value if somethig valid has
17763 - if (IsLinkSpeedDefined) {
17764 + if (IsLinkSpeedDefined) {
17765 pAC->GIni.GP[1].PLinkSpeed = LinkSpeed;
17768 @@ -3492,9 +4695,6 @@
17771 if (!AutoSet && DupSet) {
17772 - printk("sk98lin: Port B: Duplex setting not"
17773 - " possible in\n default AutoNegotiation mode"
17774 - " (Sense).\n Using AutoNegotiation On\n");
17778 @@ -3607,11 +4807,15 @@
17782 + pAC->RlmtMode = 0;
17784 if (RlmtMode != NULL && pAC->Index<SK_MAX_CARD_PARAM &&
17785 RlmtMode[pAC->Index] != NULL) {
17786 if (strcmp(RlmtMode[pAC->Index], "") == 0) {
17787 - pAC->RlmtMode = 0;
17788 + if (pAC->GIni.GIMacsFound == 2) {
17789 + pAC->RlmtMode = SK_RLMT_CHECK_LINK;
17790 + pAC->RlmtNets = 2;
17792 } else if (strcmp(RlmtMode[pAC->Index], "CheckLinkState") == 0) {
17793 pAC->RlmtMode = SK_RLMT_CHECK_LINK;
17794 } else if (strcmp(RlmtMode[pAC->Index], "CheckLocalPort") == 0) {
17795 @@ -3632,12 +4836,46 @@
17799 - pAC->RlmtMode = 0;
17800 + if (pAC->GIni.GIMacsFound == 2) {
17801 + pAC->RlmtMode = SK_RLMT_CHECK_LINK;
17802 + pAC->RlmtNets = 2;
17809 + ** use dualnet config per default
17811 + pAC->RlmtMode = SK_RLMT_CHECK_LINK;
17812 + pAC->RlmtNets = 2;
17818 + ** Check the LowLatance parameters
17820 + pAC->LowLatency = SK_FALSE;
17821 + if (LowLatency[pAC->Index] != NULL) {
17822 + if (strcmp(LowLatency[pAC->Index], "On") == 0) {
17823 + pAC->LowLatency = SK_TRUE;
17828 + ** Check the BroadcastPrio parameters
17830 + pAC->Rlmt.Net[0].ChgBcPrio = SK_FALSE;
17831 + if (BroadcastPrio[pAC->Index] != NULL) {
17832 + if (strcmp(BroadcastPrio[pAC->Index], "On") == 0) {
17833 + pAC->Rlmt.Net[0].ChgBcPrio = SK_TRUE;
17838 ** Check the interrupt moderation parameters
17840 + pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_NONE;
17841 if (Moderation[pAC->Index] != NULL) {
17842 if (strcmp(Moderation[pAC->Index], "") == 0) {
17843 pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_NONE;
17844 @@ -3651,70 +4889,49 @@
17845 printk("sk98lin: Illegal value \"%s\" for Moderation.\n"
17846 " Disable interrupt moderation.\n",
17847 Moderation[pAC->Index]);
17848 - pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_NONE;
17851 - pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_NONE;
17854 - if (Stats[pAC->Index] != NULL) {
17855 - if (strcmp(Stats[pAC->Index], "Yes") == 0) {
17856 - pAC->DynIrqModInfo.DisplayStats = SK_TRUE;
17858 - pAC->DynIrqModInfo.DisplayStats = SK_FALSE;
17861 - pAC->DynIrqModInfo.DisplayStats = SK_FALSE;
17862 +/* Set interrupt moderation if wished */
17863 +#ifdef CONFIG_SK98LIN_STATINT
17864 + pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_STATIC;
17868 if (ModerationMask[pAC->Index] != NULL) {
17869 if (strcmp(ModerationMask[pAC->Index], "Rx") == 0) {
17870 - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_ONLY;
17871 + IrqModMaskOffset = 0;
17872 } else if (strcmp(ModerationMask[pAC->Index], "Tx") == 0) {
17873 - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_TX_ONLY;
17874 + IrqModMaskOffset = 1;
17875 } else if (strcmp(ModerationMask[pAC->Index], "Sp") == 0) {
17876 - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_SP_ONLY;
17877 + IrqModMaskOffset = 2;
17878 } else if (strcmp(ModerationMask[pAC->Index], "RxSp") == 0) {
17879 - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_SP_RX;
17880 + IrqModMaskOffset = 3;
17881 } else if (strcmp(ModerationMask[pAC->Index], "SpRx") == 0) {
17882 - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_SP_RX;
17883 + IrqModMaskOffset = 3;
17884 } else if (strcmp(ModerationMask[pAC->Index], "RxTx") == 0) {
17885 - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_TX_RX;
17886 + IrqModMaskOffset = 4;
17887 } else if (strcmp(ModerationMask[pAC->Index], "TxRx") == 0) {
17888 - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_TX_RX;
17889 + IrqModMaskOffset = 4;
17890 } else if (strcmp(ModerationMask[pAC->Index], "TxSp") == 0) {
17891 - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_SP_TX;
17892 + IrqModMaskOffset = 5;
17893 } else if (strcmp(ModerationMask[pAC->Index], "SpTx") == 0) {
17894 - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_SP_TX;
17895 - } else if (strcmp(ModerationMask[pAC->Index], "RxTxSp") == 0) {
17896 - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP;
17897 - } else if (strcmp(ModerationMask[pAC->Index], "RxSpTx") == 0) {
17898 - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP;
17899 - } else if (strcmp(ModerationMask[pAC->Index], "TxRxSp") == 0) {
17900 - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP;
17901 - } else if (strcmp(ModerationMask[pAC->Index], "TxSpRx") == 0) {
17902 - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP;
17903 - } else if (strcmp(ModerationMask[pAC->Index], "SpTxRx") == 0) {
17904 - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP;
17905 - } else if (strcmp(ModerationMask[pAC->Index], "SpRxTx") == 0) {
17906 - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP;
17907 - } else { /* some rubbish */
17908 - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_ONLY;
17910 - } else { /* operator has stated nothing */
17911 - pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_TX_RX;
17914 - if (AutoSizing[pAC->Index] != NULL) {
17915 - if (strcmp(AutoSizing[pAC->Index], "On") == 0) {
17916 - pAC->DynIrqModInfo.AutoSizing = SK_FALSE;
17918 - pAC->DynIrqModInfo.AutoSizing = SK_FALSE;
17919 + IrqModMaskOffset = 5;
17920 + } else { /* some rubbish stated */
17921 + // IrqModMaskOffset = 6; ->has been initialized
17922 + // already at the begin of this function...
17924 - } else { /* operator has stated nothing */
17925 - pAC->DynIrqModInfo.AutoSizing = SK_FALSE;
17927 + if (!CHIP_ID_YUKON_2(pAC)) {
17928 + pAC->DynIrqModInfo.MaskIrqModeration = IrqModMask[IrqModMaskOffset][0];
17930 + pAC->DynIrqModInfo.MaskIrqModeration = IrqModMask[IrqModMaskOffset][1];
17933 + if (!CHIP_ID_YUKON_2(pAC)) {
17934 + pAC->DynIrqModInfo.MaxModIntsPerSec = C_INTS_PER_SEC_DEFAULT;
17936 + pAC->DynIrqModInfo.MaxModIntsPerSec = C_Y2_INTS_PER_SEC_DEFAULT;
17938 if (IntsPerSec[pAC->Index] != 0) {
17939 if ((IntsPerSec[pAC->Index]< C_INT_MOD_IPS_LOWER_RANGE) ||
17940 (IntsPerSec[pAC->Index] > C_INT_MOD_IPS_UPPER_RANGE)) {
17941 @@ -3723,97 +4940,54 @@
17942 IntsPerSec[pAC->Index],
17943 C_INT_MOD_IPS_LOWER_RANGE,
17944 C_INT_MOD_IPS_UPPER_RANGE,
17945 - C_INTS_PER_SEC_DEFAULT);
17946 - pAC->DynIrqModInfo.MaxModIntsPerSec = C_INTS_PER_SEC_DEFAULT;
17947 + pAC->DynIrqModInfo.MaxModIntsPerSec);
17949 pAC->DynIrqModInfo.MaxModIntsPerSec = IntsPerSec[pAC->Index];
17952 - pAC->DynIrqModInfo.MaxModIntsPerSec = C_INTS_PER_SEC_DEFAULT;
17957 ** Evaluate upper and lower moderation threshold
17959 pAC->DynIrqModInfo.MaxModIntsPerSecUpperLimit =
17960 pAC->DynIrqModInfo.MaxModIntsPerSec +
17961 - (pAC->DynIrqModInfo.MaxModIntsPerSec / 2);
17962 + (pAC->DynIrqModInfo.MaxModIntsPerSec / 5);
17964 pAC->DynIrqModInfo.MaxModIntsPerSecLowerLimit =
17965 pAC->DynIrqModInfo.MaxModIntsPerSec -
17966 - (pAC->DynIrqModInfo.MaxModIntsPerSec / 2);
17968 - pAC->DynIrqModInfo.PrevTimeVal = jiffies; /* initial value */
17971 -} /* GetConfiguration */
17973 + (pAC->DynIrqModInfo.MaxModIntsPerSec / 5);
17975 -/*****************************************************************************
17977 - * ProductStr - return a adapter identification string from vpd
17980 - * This function reads the product name string from the vpd area
17981 - * and puts it the field pAC->DeviceString.
17985 -static inline int ProductStr(
17986 - SK_AC *pAC, /* pointer to adapter context */
17987 - char *DeviceStr, /* result string */
17988 - int StrLen /* length of the string */
17991 -char Keyword[] = VPD_NAME; /* vpd productname identifier */
17992 -int ReturnCode; /* return code from vpd_read */
17993 -unsigned long Flags;
17994 + pAC->DynIrqModInfo.DynIrqModSampleInterval =
17995 + SK_DRV_MODERATION_TIMER_LENGTH;
17997 - spin_lock_irqsave(&pAC->SlowPathLock, Flags);
17998 - ReturnCode = VpdRead(pAC, pAC->IoBase, Keyword, DeviceStr, &StrLen);
17999 - spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
18000 +} /* GetConfiguration */
18002 - return ReturnCode;
18003 -} /* ProductStr */
18005 /*****************************************************************************
18007 - * StartDrvCleanupTimer - Start timer to check for descriptors which
18008 - * might be placed in descriptor ring, but
18009 - * havent been handled up to now
18010 + * ProductStr - return a adapter identification string from vpd
18013 - * This function requests a HW-timer fo the Yukon card. The actions to
18014 - * perform when this timer expires, are located in the SkDrvEvent().
18015 + * This function reads the product name string from the vpd area
18016 + * and puts it the field pAC->DeviceString.
18021 -StartDrvCleanupTimer(SK_AC *pAC) {
18022 - SK_EVPARA EventParam; /* Event struct for timer event */
18024 - SK_MEMSET((char *) &EventParam, 0, sizeof(EventParam));
18025 - EventParam.Para32[0] = SK_DRV_RX_CLEANUP_TIMER;
18026 - SkTimerStart(pAC, pAC->IoBase, &pAC->DrvCleanupTimer,
18027 - SK_DRV_RX_CLEANUP_TIMER_LENGTH,
18028 - SKGE_DRV, SK_DRV_TIMER, EventParam);
18030 +static void ProductStr(SK_AC *pAC)
18032 + char Default[] = "Generic Marvell Yukon chipset Ethernet device";
18033 + char Key[] = VPD_NAME; /* VPD productname key */
18034 + int StrLen = 80; /* stringlen */
18035 + unsigned long Flags;
18037 -/*****************************************************************************
18039 - * StopDrvCleanupTimer - Stop timer to check for descriptors
18042 - * This function requests a HW-timer fo the Yukon card. The actions to
18043 - * perform when this timer expires, are located in the SkDrvEvent().
18048 -StopDrvCleanupTimer(SK_AC *pAC) {
18049 - SkTimerStop(pAC, pAC->IoBase, &pAC->DrvCleanupTimer);
18050 - SK_MEMSET((char *) &pAC->DrvCleanupTimer, 0, sizeof(SK_TIMER));
18052 + spin_lock_irqsave(&pAC->SlowPathLock, Flags);
18053 + if (VpdRead(pAC, pAC->IoBase, Key, pAC->DeviceStr, &StrLen)) {
18054 + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ERROR,
18055 + ("Error reading VPD data: %d\n", ReturnCode));
18056 + strcpy(pAC->DeviceStr, Default);
18058 + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
18059 +} /* ProductStr */
18061 /****************************************************************************/
18062 /* functions for common modules *********************************************/
18063 @@ -3903,7 +5077,9 @@
18064 SK_U64 SkOsGetTime(SK_AC *pAC)
18066 SK_U64 PrivateJiffies;
18068 SkOsGetTimeCurrent(pAC, &PrivateJiffies);
18070 return PrivateJiffies;
18071 } /* SkOsGetTime */
18073 @@ -3976,6 +5152,28 @@
18075 /*****************************************************************************
18077 + * SkPciWriteCfgDWord - write a 32 bit value to pci config space
18080 + * This routine writes a 32 bit value to the pci configuration
18084 + * 0 - indicate everything worked ok.
18085 + * != 0 - error indication
18087 +int SkPciWriteCfgDWord(
18088 +SK_AC *pAC, /* Adapter Control structure pointer */
18089 +int PciAddr, /* PCI register address */
18090 +SK_U32 Val) /* pointer to store the read value */
18092 + pci_write_config_dword(pAC->PciDev, PciAddr, Val);
18094 +} /* SkPciWriteCfgDWord */
18097 +/*****************************************************************************
18099 * SkPciWriteCfgWord - write a 16 bit value to pci config space
18102 @@ -4036,29 +5234,27 @@
18106 -SK_AC *pAC, /* pointer to adapter context */
18107 -SK_IOC IoC, /* io-context */
18108 -SK_U32 Event, /* event-id */
18109 -SK_EVPARA Param) /* event-parameter */
18111 -SK_MBUF *pRlmtMbuf; /* pointer to a rlmt-mbuf structure */
18112 -struct sk_buff *pMsg; /* pointer to a message block */
18113 -int FromPort; /* the port from which we switch away */
18114 -int ToPort; /* the port we switch to */
18115 -SK_EVPARA NewPara; /* parameter for further events */
18117 -unsigned long Flags;
18119 +SK_AC *pAC, /* pointer to adapter context */
18120 +SK_IOC IoC, /* IO control context */
18121 +SK_U32 Event, /* event-id */
18122 +SK_EVPARA Param) /* event-parameter */
18124 + SK_MBUF *pRlmtMbuf; /* pointer to a rlmt-mbuf structure */
18125 + struct sk_buff *pMsg; /* pointer to a message block */
18128 + unsigned long Flags;
18129 + unsigned long InitFlags;
18130 + int FromPort; /* the port from which we switch away */
18131 + int ToPort; /* the port we switch to */
18133 + DEV_NET *pNet = NULL;
18134 +#ifdef CONFIG_SK98LIN_NAPI
18135 + int WorkToDo = 1; /* min(*budget, dev->quota); */
18136 + int WorkDone = 0;
18140 - case SK_DRV_ADAP_FAIL:
18141 - SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18142 - ("ADAPTER FAIL EVENT\n"));
18143 - printk("%s: Adapter failed.\n", pAC->dev[0]->name);
18144 - /* disable interrupts */
18145 - SK_OUT32(pAC->IoBase, B0_IMSK, 0);
18148 case SK_DRV_PORT_FAIL:
18149 FromPort = Param.Para32[0];
18150 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18151 @@ -4068,210 +5264,300 @@
18153 printk("%s: Port B failed.\n", pAC->dev[1]->name);
18157 - case SK_DRV_PORT_RESET: /* SK_U32 PortIdx */
18158 - /* action list 4 */
18159 + case SK_DRV_PORT_RESET:
18160 FromPort = Param.Para32[0];
18161 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18162 ("PORT RESET EVENT, Port: %d ", FromPort));
18163 - NewPara.Para64 = FromPort;
18164 - SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_XMAC_RESET, NewPara);
18165 + SkLocalEventQueue64(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET,
18166 + FromPort, SK_FALSE);
18168 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18171 - SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_HARD_RST);
18172 - netif_carrier_off(pAC->dev[Param.Para32[0]]);
18173 + if (CHIP_ID_YUKON_2(pAC)) {
18174 + SkY2PortStop(pAC, IoC, FromPort, SK_STOP_ALL, SK_HARD_RST);
18176 + SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_HARD_RST);
18178 + pAC->dev[Param.Para32[0]]->flags &= ~IFF_RUNNING;
18179 spin_unlock_irqrestore(
18180 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18183 - /* clear rx ring from received frames */
18184 - ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE);
18186 - ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
18187 + if (!CHIP_ID_YUKON_2(pAC)) {
18188 +#ifdef CONFIG_SK98LIN_NAPI
18190 + ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE, &WorkDone, WorkToDo);
18192 + ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE);
18194 + ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
18197 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18200 - /* tschilling: Handling of return value inserted. */
18201 - if (SkGeInitPort(pAC, IoC, FromPort)) {
18202 - if (FromPort == 0) {
18203 - printk("%s: SkGeInitPort A failed.\n", pAC->dev[0]->name);
18205 +#ifdef USE_TIST_FOR_RESET
18206 + if (pAC->GIni.GIYukon2) {
18207 +#ifdef Y2_RECOVERY
18208 + /* for Yukon II we want to have tist enabled all the time */
18209 + if (!SK_ADAPTER_WAITING_FOR_TIST(pAC)) {
18210 + Y2_ENABLE_TIST(pAC->IoBase);
18213 + /* make sure that we do not accept any status LEs from now on */
18214 + if (SK_ADAPTER_WAITING_FOR_TIST(pAC)) {
18216 + /* port already waiting for tist */
18217 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
18218 + ("Port %c is now waiting for specific Tist\n",
18219 + 'A' + FromPort));
18220 + SK_SET_WAIT_BIT_FOR_PORT(
18222 + SK_PSTATE_WAITING_FOR_SPECIFIC_TIST,
18224 + /* get current timestamp */
18225 + Y2_GET_TIST_LOW_VAL(pAC->IoBase, &pAC->MinTistLo);
18226 + pAC->MinTistHi = pAC->GIni.GITimeStampCnt;
18227 +#ifndef Y2_RECOVERY
18229 - printk("%s: SkGeInitPort B failed.\n", pAC->dev[1]->name);
18230 + /* nobody is waiting yet */
18231 + SK_SET_WAIT_BIT_FOR_PORT(
18233 + SK_PSTATE_WAITING_FOR_ANY_TIST,
18235 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
18236 + ("Port %c is now waiting for any Tist (0x%X)\n",
18237 + 'A' + FromPort, pAC->AdapterResetState));
18239 + Y2_ENABLE_TIST(pAC-IoBase);
18245 +#ifdef Y2_LE_CHECK
18246 + /* mark entries invalid */
18247 + pAC->LastPort = 3;
18248 + pAC->LastOpc = 0xFF;
18250 + if (CHIP_ID_YUKON_2(pAC)) {
18251 + SkY2PortStart(pAC, IoC, FromPort);
18253 + /* tschilling: Handling of return value inserted. */
18254 + if (SkGeInitPort(pAC, IoC, FromPort)) {
18255 + if (FromPort == 0) {
18256 + printk("%s: SkGeInitPort A failed.\n", pAC->dev[0]->name);
18258 + printk("%s: SkGeInitPort B failed.\n", pAC->dev[1]->name);
18261 + SkAddrMcUpdate(pAC,IoC, FromPort);
18262 + PortReInitBmu(pAC, FromPort);
18263 + SkGePollTxD(pAC, IoC, FromPort, SK_TRUE);
18264 + CLEAR_AND_START_RX(FromPort);
18266 - SkAddrMcUpdate(pAC,IoC, FromPort);
18267 - PortReInitBmu(pAC, FromPort);
18268 - SkGePollTxD(pAC, IoC, FromPort, SK_TRUE);
18269 - ClearAndStartRx(pAC, FromPort);
18270 spin_unlock_irqrestore(
18271 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18274 - case SK_DRV_NET_UP: /* SK_U32 PortIdx */
18275 - { struct net_device *dev = pAC->dev[Param.Para32[0]];
18276 - /* action list 5 */
18277 + case SK_DRV_NET_UP:
18278 + spin_lock_irqsave(&pAC->InitLock, InitFlags);
18279 FromPort = Param.Para32[0];
18280 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18281 - ("NET UP EVENT, Port: %d ", Param.Para32[0]));
18283 - SkAddrMcUpdate(pAC,IoC, FromPort);
18285 + ("NET UP EVENT, Port: %d ", FromPort));
18286 + SkAddrMcUpdate(pAC,IoC, FromPort); /* Mac update */
18287 if (DoPrintInterfaceChange) {
18288 - printk("%s: network connection up using"
18289 - " port %c\n", pAC->dev[Param.Para32[0]]->name, 'A'+Param.Para32[0]);
18290 + printk("%s: network connection up using port %c\n",
18291 + pAC->dev[FromPort]->name, 'A'+FromPort);
18293 - /* tschilling: Values changed according to LinkSpeedUsed. */
18294 - Stat = pAC->GIni.GP[FromPort].PLinkSpeedUsed;
18295 - if (Stat == SK_LSPEED_STAT_10MBPS) {
18296 - printk(" speed: 10\n");
18297 - } else if (Stat == SK_LSPEED_STAT_100MBPS) {
18298 - printk(" speed: 100\n");
18299 - } else if (Stat == SK_LSPEED_STAT_1000MBPS) {
18300 - printk(" speed: 1000\n");
18302 - printk(" speed: unknown\n");
18304 + /* tschilling: Values changed according to LinkSpeedUsed. */
18305 + Stat = pAC->GIni.GP[FromPort].PLinkSpeedUsed;
18306 + if (Stat == SK_LSPEED_STAT_10MBPS) {
18307 + printk(" speed: 10\n");
18308 + } else if (Stat == SK_LSPEED_STAT_100MBPS) {
18309 + printk(" speed: 100\n");
18310 + } else if (Stat == SK_LSPEED_STAT_1000MBPS) {
18311 + printk(" speed: 1000\n");
18313 + printk(" speed: unknown\n");
18316 + Stat = pAC->GIni.GP[FromPort].PLinkModeStatus;
18317 + if ((Stat == SK_LMODE_STAT_AUTOHALF) ||
18318 + (Stat == SK_LMODE_STAT_AUTOFULL)) {
18319 + printk(" autonegotiation: yes\n");
18321 + printk(" autonegotiation: no\n");
18324 - Stat = pAC->GIni.GP[FromPort].PLinkModeStatus;
18325 - if (Stat == SK_LMODE_STAT_AUTOHALF ||
18326 - Stat == SK_LMODE_STAT_AUTOFULL) {
18327 - printk(" autonegotiation: yes\n");
18330 - printk(" autonegotiation: no\n");
18332 - if (Stat == SK_LMODE_STAT_AUTOHALF ||
18333 - Stat == SK_LMODE_STAT_HALF) {
18334 - printk(" duplex mode: half\n");
18337 - printk(" duplex mode: full\n");
18339 - Stat = pAC->GIni.GP[FromPort].PFlowCtrlStatus;
18340 - if (Stat == SK_FLOW_STAT_REM_SEND ) {
18341 - printk(" flowctrl: remote send\n");
18343 - else if (Stat == SK_FLOW_STAT_LOC_SEND ){
18344 - printk(" flowctrl: local send\n");
18346 - else if (Stat == SK_FLOW_STAT_SYMMETRIC ){
18347 - printk(" flowctrl: symmetric\n");
18350 - printk(" flowctrl: none\n");
18353 - /* tschilling: Check against CopperType now. */
18354 - if ((pAC->GIni.GICopperType == SK_TRUE) &&
18355 - (pAC->GIni.GP[FromPort].PLinkSpeedUsed ==
18356 - SK_LSPEED_STAT_1000MBPS)) {
18357 - Stat = pAC->GIni.GP[FromPort].PMSStatus;
18358 - if (Stat == SK_MS_STAT_MASTER ) {
18359 - printk(" role: master\n");
18360 + if ((Stat == SK_LMODE_STAT_AUTOHALF) ||
18361 + (Stat == SK_LMODE_STAT_HALF)) {
18362 + printk(" duplex mode: half\n");
18364 + printk(" duplex mode: full\n");
18366 - else if (Stat == SK_MS_STAT_SLAVE ) {
18367 - printk(" role: slave\n");
18369 + Stat = pAC->GIni.GP[FromPort].PFlowCtrlStatus;
18370 + if (Stat == SK_FLOW_STAT_REM_SEND ) {
18371 + printk(" flowctrl: remote send\n");
18372 + } else if (Stat == SK_FLOW_STAT_LOC_SEND ) {
18373 + printk(" flowctrl: local send\n");
18374 + } else if (Stat == SK_FLOW_STAT_SYMMETRIC ) {
18375 + printk(" flowctrl: symmetric\n");
18377 + printk(" flowctrl: none\n");
18380 - printk(" role: ???\n");
18382 + /* tschilling: Check against CopperType now. */
18383 + if ((pAC->GIni.GICopperType == SK_TRUE) &&
18384 + (pAC->GIni.GP[FromPort].PLinkSpeedUsed ==
18385 + SK_LSPEED_STAT_1000MBPS)) {
18386 + Stat = pAC->GIni.GP[FromPort].PMSStatus;
18387 + if (Stat == SK_MS_STAT_MASTER ) {
18388 + printk(" role: master\n");
18389 + } else if (Stat == SK_MS_STAT_SLAVE ) {
18390 + printk(" role: slave\n");
18392 + printk(" role: ???\n");
18398 - Display dim (dynamic interrupt moderation)
18401 - if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_STATIC)
18402 - printk(" irq moderation: static (%d ints/sec)\n",
18403 + /* Display interrupt moderation informations */
18404 + if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_STATIC) {
18405 + printk(" irq moderation: static (%d ints/sec)\n",
18406 pAC->DynIrqModInfo.MaxModIntsPerSec);
18407 - else if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_DYNAMIC)
18408 - printk(" irq moderation: dynamic (%d ints/sec)\n",
18409 + } else if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
18410 + printk(" irq moderation: dynamic (%d ints/sec)\n",
18411 pAC->DynIrqModInfo.MaxModIntsPerSec);
18413 - printk(" irq moderation: disabled\n");
18415 + printk(" irq moderation: disabled\n");
18418 +#ifdef NETIF_F_TSO
18419 + if (CHIP_ID_YUKON_2(pAC)) {
18420 + if (pAC->dev[FromPort]->features & NETIF_F_TSO) {
18421 + printk(" tcp offload: enabled\n");
18423 + printk(" tcp offload: disabled\n");
18428 + if (pAC->dev[FromPort]->features & NETIF_F_SG) {
18429 + printk(" scatter-gather: enabled\n");
18431 + printk(" scatter-gather: disabled\n");
18434 + if (pAC->dev[FromPort]->features & NETIF_F_IP_CSUM) {
18435 + printk(" tx-checksum: enabled\n");
18437 + printk(" tx-checksum: disabled\n");
18440 - printk(" scatter-gather: %s\n",
18441 - (dev->features & NETIF_F_SG) ? "enabled" : "disabled");
18442 - printk(" tx-checksum: %s\n",
18443 - (dev->features & NETIF_F_IP_CSUM) ? "enabled" : "disabled");
18444 - printk(" rx-checksum: %s\n",
18445 - pAC->RxPort[Param.Para32[0]].RxCsum ? "enabled" : "disabled");
18446 + if (pAC->RxPort[FromPort].UseRxCsum) {
18447 + printk(" rx-checksum: enabled\n");
18449 + printk(" rx-checksum: disabled\n");
18451 +#ifdef CONFIG_SK98LIN_NAPI
18452 + printk(" rx-polling: enabled\n");
18454 + if (pAC->LowLatency) {
18455 + printk(" low latency: enabled\n");
18458 + if (pAC->Rlmt.Net[0].ChgBcPrio) {
18459 + printk(" broadcast prio: enabled\n");
18462 - DoPrintInterfaceChange = SK_TRUE;
18464 + DoPrintInterfaceChange = SK_TRUE;
18467 - if ((Param.Para32[0] != pAC->ActivePort) &&
18468 - (pAC->RlmtNets == 1)) {
18469 - NewPara.Para32[0] = pAC->ActivePort;
18470 - NewPara.Para32[1] = Param.Para32[0];
18471 - SkEventQueue(pAC, SKGE_DRV, SK_DRV_SWITCH_INTERN,
18473 + if ((FromPort != pAC->ActivePort)&&(pAC->RlmtNets == 1)) {
18474 + SkLocalEventQueue(pAC, SKGE_DRV, SK_DRV_SWITCH_INTERN,
18475 + pAC->ActivePort, FromPort, SK_FALSE);
18478 /* Inform the world that link protocol is up. */
18479 - netif_carrier_on(dev);
18480 + netif_wake_queue(pAC->dev[FromPort]);
18481 + netif_carrier_on(pAC->dev[FromPort]);
18482 + pAC->dev[FromPort]->flags |= IFF_RUNNING;
18483 + spin_unlock_irqrestore(&pAC->InitLock, InitFlags);
18486 - case SK_DRV_NET_DOWN: /* SK_U32 Reason */
18487 - /* action list 7 */
18488 + case SK_DRV_NET_DOWN:
18489 + Reason = Param.Para32[0];
18490 + FromPort = Param.Para32[1];
18491 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18492 ("NET DOWN EVENT "));
18494 + /* Stop queue and carrier */
18495 + netif_stop_queue(pAC->dev[FromPort]);
18496 + netif_carrier_off(pAC->dev[FromPort]);
18498 + /* Print link change */
18499 if (DoPrintInterfaceChange) {
18500 - printk("%s: network connection down\n",
18501 - pAC->dev[Param.Para32[1]]->name);
18502 + if (pAC->dev[FromPort]->flags & IFF_RUNNING) {
18503 + printk("%s: network connection down\n",
18504 + pAC->dev[FromPort]->name);
18507 DoPrintInterfaceChange = SK_TRUE;
18509 - netif_carrier_off(pAC->dev[Param.Para32[1]]);
18510 + pAC->dev[FromPort]->flags &= ~IFF_RUNNING;
18512 - case SK_DRV_SWITCH_HARD: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */
18513 - SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18514 - ("PORT SWITCH HARD "));
18515 - case SK_DRV_SWITCH_SOFT: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */
18516 - /* action list 6 */
18517 - printk("%s: switching to port %c\n", pAC->dev[0]->name,
18518 - 'A'+Param.Para32[1]);
18519 - case SK_DRV_SWITCH_INTERN: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */
18520 + case SK_DRV_SWITCH_HARD: /* FALL THRU */
18521 + case SK_DRV_SWITCH_SOFT: /* FALL THRU */
18522 + case SK_DRV_SWITCH_INTERN:
18523 FromPort = Param.Para32[0];
18524 - ToPort = Param.Para32[1];
18525 + ToPort = Param.Para32[1];
18526 + printk("%s: switching from port %c to port %c\n",
18527 + pAC->dev[0]->name, 'A'+FromPort, 'A'+ToPort);
18528 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18529 ("PORT SWITCH EVENT, From: %d To: %d (Pref %d) ",
18530 FromPort, ToPort, pAC->Rlmt.Net[0].PrefPort));
18531 - NewPara.Para64 = FromPort;
18532 - SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_XMAC_RESET, NewPara);
18533 - NewPara.Para64 = ToPort;
18534 - SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_XMAC_RESET, NewPara);
18535 + SkLocalEventQueue64(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET,
18536 + FromPort, SK_FALSE);
18537 + SkLocalEventQueue64(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET,
18538 + ToPort, SK_FALSE);
18540 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18542 spin_lock(&pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock);
18543 - SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST);
18544 - SkGeStopPort(pAC, IoC, ToPort, SK_STOP_ALL, SK_SOFT_RST);
18545 + if (CHIP_ID_YUKON_2(pAC)) {
18546 + SkY2PortStop(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST);
18547 + SkY2PortStop(pAC, IoC, ToPort, SK_STOP_ALL, SK_SOFT_RST);
18550 + SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST);
18551 + SkGeStopPort(pAC, IoC, ToPort, SK_STOP_ALL, SK_SOFT_RST);
18553 spin_unlock(&pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock);
18554 spin_unlock_irqrestore(
18555 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18558 - ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE); /* clears rx ring */
18559 - ReceiveIrq(pAC, &pAC->RxPort[ToPort], SK_FALSE); /* clears rx ring */
18561 - ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
18562 - ClearTxRing(pAC, &pAC->TxPort[ToPort][TX_PRIO_LOW]);
18563 + if (!CHIP_ID_YUKON_2(pAC)) {
18564 +#ifdef CONFIG_SK98LIN_NAPI
18566 + ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE, &WorkDone, WorkToDo);
18567 + ReceiveIrq(pAC, &pAC->RxPort[ToPort], SK_FALSE, &WorkDone, WorkToDo);
18569 + ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE); /* clears rx ring */
18570 + ReceiveIrq(pAC, &pAC->RxPort[ToPort], SK_FALSE); /* clears rx ring */
18572 + ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
18573 + ClearTxRing(pAC, &pAC->TxPort[ToPort][TX_PRIO_LOW]);
18577 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18579 spin_lock(&pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock);
18580 pAC->ActivePort = ToPort;
18582 - SetQueueSizes(pAC);
18585 /* tschilling: New common function with minimum size check. */
18586 DualNet = SK_FALSE;
18587 if (pAC->RlmtNets == 2) {
18588 @@ -4289,74 +5575,316 @@
18589 printk("SkGeInitAssignRamToQueues failed.\n");
18593 - /* tschilling: Handling of return values inserted. */
18594 - if (SkGeInitPort(pAC, IoC, FromPort) ||
18595 - SkGeInitPort(pAC, IoC, ToPort)) {
18596 - printk("%s: SkGeInitPort failed.\n", pAC->dev[0]->name);
18598 + if (!CHIP_ID_YUKON_2(pAC)) {
18599 + /* tschilling: Handling of return values inserted. */
18600 + if (SkGeInitPort(pAC, IoC, FromPort) ||
18601 + SkGeInitPort(pAC, IoC, ToPort)) {
18602 + printk("%s: SkGeInitPort failed.\n", pAC->dev[0]->name);
18605 - if (Event == SK_DRV_SWITCH_SOFT) {
18606 - SkMacRxTxEnable(pAC, IoC, FromPort);
18607 + if (!CHIP_ID_YUKON_2(pAC)) {
18608 + if (Event == SK_DRV_SWITCH_SOFT) {
18609 + SkMacRxTxEnable(pAC, IoC, FromPort);
18611 + SkMacRxTxEnable(pAC, IoC, ToPort);
18613 - SkMacRxTxEnable(pAC, IoC, ToPort);
18615 SkAddrSwap(pAC, IoC, FromPort, ToPort);
18616 SkAddrMcUpdate(pAC, IoC, FromPort);
18617 SkAddrMcUpdate(pAC, IoC, ToPort);
18618 - PortReInitBmu(pAC, FromPort);
18619 - PortReInitBmu(pAC, ToPort);
18620 - SkGePollTxD(pAC, IoC, FromPort, SK_TRUE);
18621 - SkGePollTxD(pAC, IoC, ToPort, SK_TRUE);
18622 - ClearAndStartRx(pAC, FromPort);
18623 - ClearAndStartRx(pAC, ToPort);
18625 +#ifdef USE_TIST_FOR_RESET
18626 + if (pAC->GIni.GIYukon2) {
18627 + /* make sure that we do not accept any status LEs from now on */
18628 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
18629 + ("both Ports now waiting for specific Tist\n"));
18630 + SK_SET_WAIT_BIT_FOR_PORT(
18632 + SK_PSTATE_WAITING_FOR_ANY_TIST,
18634 + SK_SET_WAIT_BIT_FOR_PORT(
18636 + SK_PSTATE_WAITING_FOR_ANY_TIST,
18640 + Y2_ENABLE_TIST(pAC->IoBase);
18643 + if (!CHIP_ID_YUKON_2(pAC)) {
18644 + PortReInitBmu(pAC, FromPort);
18645 + PortReInitBmu(pAC, ToPort);
18646 + SkGePollTxD(pAC, IoC, FromPort, SK_TRUE);
18647 + SkGePollTxD(pAC, IoC, ToPort, SK_TRUE);
18648 + CLEAR_AND_START_RX(FromPort);
18649 + CLEAR_AND_START_RX(ToPort);
18651 + SkY2PortStart(pAC, IoC, FromPort);
18652 + SkY2PortStart(pAC, IoC, ToPort);
18654 + /* in yukon-II always port 0 has to be started first */
18655 + // SkY2PortStart(pAC, IoC, 0);
18656 + // SkY2PortStart(pAC, IoC, 1);
18659 spin_unlock(&pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock);
18660 spin_unlock_irqrestore(
18661 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18664 case SK_DRV_RLMT_SEND: /* SK_MBUF *pMb */
18665 - SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18667 + SK_DBG_MSG(NULL,SK_DBGMOD_DRV,SK_DBGCAT_DRV_EVENT,("RLS "));
18668 pRlmtMbuf = (SK_MBUF*) Param.pParaPtr;
18669 pMsg = (struct sk_buff*) pRlmtMbuf->pOs;
18670 skb_put(pMsg, pRlmtMbuf->Length);
18671 - if (XmitFrame(pAC, &pAC->TxPort[pRlmtMbuf->PortIdx][TX_PRIO_LOW],
18673 + if (!CHIP_ID_YUKON_2(pAC)) {
18674 + if (XmitFrame(pAC, &pAC->TxPort[pRlmtMbuf->PortIdx][TX_PRIO_LOW],
18676 + DEV_KFREE_SKB_ANY(pMsg);
18679 + if (SkY2RlmtSend(pAC, pRlmtMbuf->PortIdx, pMsg) < 0) {
18680 + DEV_KFREE_SKB_ANY(pMsg);
18684 + case SK_DRV_TIMER:
18685 + if (Param.Para32[0] == SK_DRV_MODERATION_TIMER) {
18686 + /* check what IRQs are to be moderated */
18687 + SkDimStartModerationTimer(pAC);
18688 + SkDimModerate(pAC);
18690 + printk("Expiration of unknown timer\n");
18693 + case SK_DRV_ADAP_FAIL:
18694 +#if (!defined (Y2_RECOVERY) && !defined (Y2_LE_CHECK))
18695 + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18696 + ("ADAPTER FAIL EVENT\n"));
18697 + printk("%s: Adapter failed.\n", pAC->dev[0]->name);
18698 + SK_OUT32(pAC->IoBase, B0_IMSK, 0); /* disable interrupts */
18702 +#if (defined (Y2_RECOVERY) || defined (Y2_LE_CHECK))
18703 + case SK_DRV_RECOVER:
18704 + spin_lock_irqsave(&pAC->InitLock, InitFlags);
18705 + pNet = (DEV_NET *) pAC->dev[Param.Para32[0]]->priv;
18707 + /* Recover already in progress */
18708 + if (pNet->InRecover) {
18712 + netif_stop_queue(pAC->dev[Param.Para32[0]]); /* stop device if running */
18713 + pNet->InRecover = SK_TRUE;
18715 + FromPort = Param.Para32[0];
18716 + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18717 + ("PORT RESET EVENT, Port: %d ", FromPort));
18719 + /* Disable interrupts */
18720 + SK_OUT32(pAC->IoBase, B0_IMSK, 0);
18721 + SK_OUT32(pAC->IoBase, B0_HWE_IMSK, 0);
18723 + SkLocalEventQueue64(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET,
18724 + FromPort, SK_FALSE);
18725 + spin_lock_irqsave(
18726 + &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18728 + if (CHIP_ID_YUKON_2(pAC)) {
18729 + SkY2PortStop(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST);
18731 + SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST);
18733 + pAC->dev[Param.Para32[0]]->flags &= ~IFF_RUNNING;
18734 + spin_unlock_irqrestore(
18735 + &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18738 + if (!CHIP_ID_YUKON_2(pAC)) {
18739 +#ifdef CONFIG_SK98LIN_NAPI
18741 + ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE, &WorkDone, WorkToDo);
18743 + ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE);
18745 + ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
18747 + spin_lock_irqsave(
18748 + &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18751 +#ifdef USE_TIST_FOR_RESET
18752 + if (pAC->GIni.GIYukon2) {
18754 + /* make sure that we do not accept any status LEs from now on */
18755 + Y2_ENABLE_TIST(pAC->IoBase);
18757 + /* get current timestamp */
18758 + Y2_GET_TIST_LOW_VAL(pAC->IoBase, &pAC->MinTistLo);
18759 + pAC->MinTistHi = pAC->GIni.GITimeStampCnt;
18761 + SK_SET_WAIT_BIT_FOR_PORT(
18763 + SK_PSTATE_WAITING_FOR_SPECIFIC_TIST,
18766 + SK_SET_WAIT_BIT_FOR_PORT(
18768 + SK_PSTATE_WAITING_FOR_ANY_TIST,
18772 + Y2_ENABLE_TIST(pAC->IoBase);
18776 + /* Restart Receive BMU on Yukon-2 */
18777 + if (HW_FEATURE(pAC, HWF_WA_DEV_4167)) {
18778 + SkYuk2RestartRxBmu(pAC, IoC, FromPort);
18781 +#ifdef Y2_LE_CHECK
18782 + /* mark entries invalid */
18783 + pAC->LastPort = 3;
18784 + pAC->LastOpc = 0xFF;
18788 + /* Restart ports but do not initialize PHY. */
18789 + if (CHIP_ID_YUKON_2(pAC)) {
18790 + SkY2PortStart(pAC, IoC, FromPort);
18792 + /* tschilling: Handling of return value inserted. */
18793 + if (SkGeInitPort(pAC, IoC, FromPort)) {
18794 + if (FromPort == 0) {
18795 + printk("%s: SkGeInitPort A failed.\n", pAC->dev[0]->name);
18797 + printk("%s: SkGeInitPort B failed.\n", pAC->dev[1]->name);
18800 + SkAddrMcUpdate(pAC,IoC, FromPort);
18801 + PortReInitBmu(pAC, FromPort);
18802 + SkGePollTxD(pAC, IoC, FromPort, SK_TRUE);
18803 + CLEAR_AND_START_RX(FromPort);
18805 + spin_unlock_irqrestore(
18806 + &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18809 + /* Map any waiting RX buffers to HW */
18810 + FillReceiveTableYukon2(pAC, pAC->IoBase, FromPort);
18812 + pNet->InRecover = SK_FALSE;
18813 + /* enable Interrupts */
18814 + SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
18815 + SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK);
18816 + netif_wake_queue(pAC->dev[FromPort]);
18817 + spin_unlock_irqrestore(&pAC->InitLock, InitFlags);
18822 + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18826 +} /* SkDrvEvent */
18829 +/******************************************************************************
18831 + * SkLocalEventQueue() - add event to queue
18834 + * This function adds an event to the event queue and run the
18835 + * SkEventDispatcher. At least Init Level 1 is required to queue events,
18836 + * but will be scheduled add Init Level 2.
18841 +void SkLocalEventQueue(
18842 +SK_AC *pAC, /* Adapters context */
18843 +SK_U32 Class, /* Event Class */
18844 +SK_U32 Event, /* Event to be queued */
18845 +SK_U32 Param1, /* Event parameter 1 */
18846 +SK_U32 Param2, /* Event parameter 2 */
18847 +SK_BOOL Dispatcher) /* Dispatcher flag:
18848 + * TRUE == Call SkEventDispatcher
18849 + * FALSE == Don't execute SkEventDispatcher
18852 + SK_EVPARA EvPara;
18853 + EvPara.Para32[0] = Param1;
18854 + EvPara.Para32[1] = Param2;
18857 + if (Class == SKGE_PNMI) {
18858 + SkPnmiEvent( pAC,
18863 + SkEventQueue( pAC,
18869 + /* Run the dispatcher */
18870 + if (Dispatcher) {
18871 + SkEventDispatcher(pAC, pAC->IoBase);
18876 +/******************************************************************************
18878 + * SkLocalEventQueue64() - add event to queue (64bit version)
18881 + * This function adds an event to the event queue and run the
18882 + * SkEventDispatcher. At least Init Level 1 is required to queue events,
18883 + * but will be scheduled add Init Level 2.
18888 +void SkLocalEventQueue64(
18889 +SK_AC *pAC, /* Adapters context */
18890 +SK_U32 Class, /* Event Class */
18891 +SK_U32 Event, /* Event to be queued */
18892 +SK_U64 Param, /* Event parameter */
18893 +SK_BOOL Dispatcher) /* Dispatcher flag:
18894 + * TRUE == Call SkEventDispatcher
18895 + * FALSE == Don't execute SkEventDispatcher
18898 + SK_EVPARA EvPara;
18899 + EvPara.Para64 = Param;
18902 + if (Class == SKGE_PNMI) {
18903 + SkPnmiEvent( pAC,
18908 + SkEventQueue( pAC,
18914 - DEV_KFREE_SKB_ANY(pMsg);
18916 - case SK_DRV_TIMER:
18917 - if (Param.Para32[0] == SK_DRV_MODERATION_TIMER) {
18919 - ** expiration of the moderation timer implies that
18920 - ** dynamic moderation is to be applied
18922 - SkDimStartModerationTimer(pAC);
18923 - SkDimModerate(pAC);
18924 - if (pAC->DynIrqModInfo.DisplayStats) {
18925 - SkDimDisplayModerationSettings(pAC);
18927 - } else if (Param.Para32[0] == SK_DRV_RX_CLEANUP_TIMER) {
18929 - ** check if we need to check for descriptors which
18930 - ** haven't been handled the last millisecs
18932 - StartDrvCleanupTimer(pAC);
18933 - if (pAC->GIni.GIMacsFound == 2) {
18934 - ReceiveIrq(pAC, &pAC->RxPort[1], SK_FALSE);
18936 - ReceiveIrq(pAC, &pAC->RxPort[0], SK_FALSE);
18938 - printk("Expiration of unknown timer\n");
18943 + /* Run the dispatcher */
18944 + if (Dispatcher) {
18945 + SkEventDispatcher(pAC, pAC->IoBase);
18947 - SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18951 -} /* SkDrvEvent */
18956 /*****************************************************************************
18957 @@ -4408,8 +5936,6 @@
18961 -#ifdef SK_DIAG_SUPPORT
18963 /*****************************************************************************
18965 * SkDrvEnterDiagMode - handles DIAG attach request
18966 @@ -4424,8 +5950,11 @@
18967 int SkDrvEnterDiagMode(
18968 SK_AC *pAc) /* pointer to adapter context */
18970 - DEV_NET *pNet = netdev_priv(pAc->dev[0]);
18971 - SK_AC *pAC = pNet->pAC;
18972 + SK_AC *pAC = NULL;
18973 + DEV_NET *pNet = NULL;
18975 + pNet = (DEV_NET *) pAc->dev[0]->priv;
18978 SK_MEMCPY(&(pAc->PnmiBackup), &(pAc->PnmiStruct),
18979 sizeof(SK_PNMI_STRUCT_DATA));
18980 @@ -4440,8 +5969,9 @@
18982 pAC->WasIfUp[0] = SK_FALSE;
18984 - if (pNet != netdev_priv(pAC->dev[1])) {
18985 - pNet = netdev_priv(pAC->dev[1]);
18987 + if (pNet != (DEV_NET *) pAc->dev[1]->priv) {
18988 + pNet = (DEV_NET *) pAc->dev[1]->priv;
18989 if (netif_running(pAC->dev[1])) {
18990 pAC->WasIfUp[1] = SK_TRUE;
18991 pAC->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */
18992 @@ -4474,16 +6004,16 @@
18993 sizeof(SK_PNMI_STRUCT_DATA));
18994 pAc->DiagModeActive = DIAG_NOTACTIVE;
18995 pAc->Pnmi.DiagAttached = SK_DIAG_IDLE;
18996 - if (pAc->WasIfUp[0] == SK_TRUE) {
18997 - pAc->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */
18998 + if (pAc->WasIfUp[0] == SK_TRUE) {
18999 + pAc->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */
19000 DoPrintInterfaceChange = SK_FALSE;
19001 - SkDrvInitAdapter(pAc, 0); /* first device */
19003 - if (pAc->WasIfUp[1] == SK_TRUE) {
19004 - pAc->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */
19005 + SkDrvInitAdapter(pAc, 0); /* first device */
19007 + if (pAc->WasIfUp[1] == SK_TRUE) {
19008 + pAc->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */
19009 DoPrintInterfaceChange = SK_FALSE;
19010 - SkDrvInitAdapter(pAc, 1); /* second device */
19012 + SkDrvInitAdapter(pAc, 1); /* second device */
19017 @@ -4563,11 +6093,20 @@
19019 dev = pAC->dev[devNbr];
19021 - /* On Linux 2.6 the network driver does NOT mess with reference
19022 - ** counts. The driver MUST be able to be unloaded at any time
19023 - ** due to the possibility of hotplug.
19025 + ** Function SkGeClose() uses MOD_DEC_USE_COUNT (2.2/2.4)
19026 + ** or module_put() (2.6) to decrease the number of users for
19027 + ** a device, but if a device is to be put under control of
19028 + ** the DIAG, that count is OK already and does not need to
19029 + ** be adapted! Hence the opposite MOD_INC_USE_COUNT or
19030 + ** try_module_get() needs to be used again to correct that.
19032 + if (!try_module_get(THIS_MODULE)) {
19036 if (SkGeClose(dev) != 0) {
19037 + module_put(THIS_MODULE);
19041 @@ -4596,6 +6135,17 @@
19043 if (SkGeOpen(dev) != 0) {
19047 + ** Function SkGeOpen() uses MOD_INC_USE_COUNT (2.2/2.4)
19048 + ** or try_module_get() (2.6) to increase the number of
19049 + ** users for a device, but if a device was just under
19050 + ** control of the DIAG, that count is OK already and
19051 + ** does not need to be adapted! Hence the opposite
19052 + ** MOD_DEC_USE_COUNT or module_put() needs to be used
19053 + ** again to correct that.
19055 + module_put(THIS_MODULE);
19059 @@ -4608,14 +6158,25 @@
19061 } /* SkDrvInitAdapter */
19064 +static int __init sk98lin_init(void)
19066 + return pci_module_init(&sk98lin_driver);
19069 +static void __exit sk98lin_cleanup(void)
19071 + pci_unregister_driver(&sk98lin_driver);
19074 +module_init(sk98lin_init);
19075 +module_exit(sk98lin_cleanup);
19079 /****************************************************************************/
19080 /* "debug only" section *****************************************************/
19081 /****************************************************************************/
19084 /*****************************************************************************
19086 * DumpMsg - print a frame
19087 @@ -4626,9 +6187,11 @@
19091 -static void DumpMsg(struct sk_buff *skb, char *str)
19092 +static void DumpMsg(
19093 +struct sk_buff *skb, /* linux' socket buffer */
19094 +char *str) /* additional msg string */
19097 + int msglen = (skb->len > 64) ? 64 : skb->len;
19100 printk("DumpMsg(): NULL-Message\n");
19101 @@ -4640,19 +6203,14 @@
19105 - msglen = skb->len;
19109 - printk("--- Begin of message from %s , len %d (from %d) ----\n", str, msglen, skb->len);
19111 + printk("DumpMsg: PhysPage: %p\n",
19112 + page_address(virt_to_page(skb->data)));
19113 + printk("--- Begin of message from %s , len %d (from %d) ----\n",
19114 + str, msglen, skb->len);
19115 DumpData((char *)skb->data, msglen);
19117 printk("------- End of message ---------\n");
19122 /*****************************************************************************
19124 * DumpData - print a data area
19125 @@ -4664,23 +6222,22 @@
19129 -static void DumpData(char *p, int size)
19133 -char hex_buffer[180];
19134 -char asc_buffer[180];
19135 -char HEXCHAR[] = "0123456789ABCDEF";
19139 - hex_buffer[0] = 0;
19140 - asc_buffer[0] = 0;
19141 +static void DumpData(
19142 +char *p, /* pointer to area containing the data */
19143 +int size) /* the size of that data area in bytes */
19146 + int haddr = 0, addr = 0;
19147 + char hex_buffer[180] = { '\0' };
19148 + char asc_buffer[180] = { '\0' };
19149 + char HEXCHAR[] = "0123456789ABCDEF";
19151 for (i=0; i < size; ) {
19152 - if (*p >= '0' && *p <='z')
19153 + if (*p >= '0' && *p <='z') {
19154 asc_buffer[addr] = *p;
19157 asc_buffer[addr] = '.';
19160 asc_buffer[addr] = 0;
19161 hex_buffer[haddr] = HEXCHAR[(*p & 0xf0) >> 4];
19162 @@ -4706,27 +6263,24 @@
19163 * DumpLong - print a data area as long values
19166 - * This function prints a area of data to the system logfile/to the
19167 + * This function prints a long variable to the system logfile/to the
19173 -static void DumpLong(char *pc, int size)
19177 -char hex_buffer[180];
19178 -char asc_buffer[180];
19179 -char HEXCHAR[] = "0123456789ABCDEF";
19185 - hex_buffer[0] = 0;
19186 - asc_buffer[0] = 0;
19188 +static void DumpLong(
19189 +char *pc, /* location of the variable to print */
19190 +int size) /* how large is the variable? */
19193 + int haddr = 0, addr = 0;
19194 + char hex_buffer[180] = { '\0' };
19195 + char asc_buffer[180] = { '\0' };
19196 + char HEXCHAR[] = "0123456789ABCDEF";
19197 + long *p = (long*) pc;
19200 for (i=0; i < size; ) {
19202 hex_buffer[haddr] = HEXCHAR[(l >> 28) & 0xf];
19203 @@ -4760,386 +6314,9 @@
19207 -static int __devinit skge_probe_one(struct pci_dev *pdev,
19208 - const struct pci_device_id *ent)
19211 - DEV_NET *pNet = NULL;
19212 - struct net_device *dev = NULL;
19213 - static int boards_found = 0;
19214 - int error = -ENODEV;
19215 - int using_dac = 0;
19216 - char DeviceStr[80];
19218 - if (pci_enable_device(pdev))
19221 - /* Configure DMA attributes. */
19222 - if (sizeof(dma_addr_t) > sizeof(u32) &&
19223 - !(error = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
19225 - error = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
19227 - printk(KERN_ERR "sk98lin %s unable to obtain 64 bit DMA "
19228 - "for consistent allocations\n", pci_name(pdev));
19229 - goto out_disable_device;
19232 - error = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
19234 - printk(KERN_ERR "sk98lin %s no usable DMA configuration\n",
19236 - goto out_disable_device;
19241 - dev = alloc_etherdev(sizeof(DEV_NET));
19243 - printk(KERN_ERR "sk98lin: unable to allocate etherdev "
19245 - goto out_disable_device;
19248 - pNet = netdev_priv(dev);
19249 - pNet->pAC = kzalloc(sizeof(SK_AC), GFP_KERNEL);
19250 - if (!pNet->pAC) {
19251 - printk(KERN_ERR "sk98lin: unable to allocate adapter "
19253 - goto out_free_netdev;
19257 - pAC->PciDev = pdev;
19259 - pAC->dev[0] = dev;
19260 - pAC->dev[1] = dev;
19261 - pAC->CheckQueue = SK_FALSE;
19263 - dev->irq = pdev->irq;
19265 - error = SkGeInitPCI(pAC);
19267 - printk(KERN_ERR "sk98lin: PCI setup failed: %i\n", error);
19268 - goto out_free_netdev;
19271 - SET_MODULE_OWNER(dev);
19272 - dev->open = &SkGeOpen;
19273 - dev->stop = &SkGeClose;
19274 - dev->hard_start_xmit = &SkGeXmit;
19275 - dev->get_stats = &SkGeStats;
19276 - dev->set_multicast_list = &SkGeSetRxMode;
19277 - dev->set_mac_address = &SkGeSetMacAddr;
19278 - dev->do_ioctl = &SkGeIoctl;
19279 - dev->change_mtu = &SkGeChangeMtu;
19280 -#ifdef CONFIG_NET_POLL_CONTROLLER
19281 - dev->poll_controller = &SkGePollController;
19283 - SET_NETDEV_DEV(dev, &pdev->dev);
19284 - SET_ETHTOOL_OPS(dev, &SkGeEthtoolOps);
19286 - /* Use only if yukon hardware */
19287 - if (pAC->ChipsetType) {
19288 -#ifdef USE_SK_TX_CHECKSUM
19289 - dev->features |= NETIF_F_IP_CSUM;
19291 -#ifdef SK_ZEROCOPY
19292 - dev->features |= NETIF_F_SG;
19294 -#ifdef USE_SK_RX_CHECKSUM
19295 - pAC->RxPort[0].RxCsum = 1;
19300 - dev->features |= NETIF_F_HIGHDMA;
19302 - pAC->Index = boards_found++;
19304 - error = SkGeBoardInit(dev, pAC);
19306 - goto out_free_netdev;
19308 - /* Read Adapter name from VPD */
19309 - if (ProductStr(pAC, DeviceStr, sizeof(DeviceStr)) != 0) {
19311 - printk(KERN_ERR "sk98lin: Could not read VPD data.\n");
19312 - goto out_free_resources;
19315 - /* Register net device */
19316 - error = register_netdev(dev);
19318 - printk(KERN_ERR "sk98lin: Could not register device.\n");
19319 - goto out_free_resources;
19322 - /* Print adapter specific string from vpd */
19323 - printk("%s: %s\n", dev->name, DeviceStr);
19325 - /* Print configuration settings */
19326 - printk(" PrefPort:%c RlmtMode:%s\n",
19327 - 'A' + pAC->Rlmt.Net[0].Port[pAC->Rlmt.Net[0].PrefPort]->PortNumber,
19328 - (pAC->RlmtMode==0) ? "Check Link State" :
19329 - ((pAC->RlmtMode==1) ? "Check Link State" :
19330 - ((pAC->RlmtMode==3) ? "Check Local Port" :
19331 - ((pAC->RlmtMode==7) ? "Check Segmentation" :
19332 - ((pAC->RlmtMode==17) ? "Dual Check Link State" :"Error")))));
19334 - SkGeYellowLED(pAC, pAC->IoBase, 1);
19336 - memcpy(&dev->dev_addr, &pAC->Addr.Net[0].CurrentMacAddress, 6);
19337 - memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
19339 - pNet->PortNr = 0;
19344 - pci_set_drvdata(pdev, dev);
19346 - /* More then one port found */
19347 - if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
19348 - dev = alloc_etherdev(sizeof(DEV_NET));
19350 - printk(KERN_ERR "sk98lin: unable to allocate etherdev "
19352 - goto single_port;
19355 - pNet = netdev_priv(dev);
19356 - pNet->PortNr = 1;
19360 - dev->open = &SkGeOpen;
19361 - dev->stop = &SkGeClose;
19362 - dev->hard_start_xmit = &SkGeXmit;
19363 - dev->get_stats = &SkGeStats;
19364 - dev->set_multicast_list = &SkGeSetRxMode;
19365 - dev->set_mac_address = &SkGeSetMacAddr;
19366 - dev->do_ioctl = &SkGeIoctl;
19367 - dev->change_mtu = &SkGeChangeMtu;
19368 - SET_NETDEV_DEV(dev, &pdev->dev);
19369 - SET_ETHTOOL_OPS(dev, &SkGeEthtoolOps);
19371 - if (pAC->ChipsetType) {
19372 -#ifdef USE_SK_TX_CHECKSUM
19373 - dev->features |= NETIF_F_IP_CSUM;
19375 -#ifdef SK_ZEROCOPY
19376 - dev->features |= NETIF_F_SG;
19378 -#ifdef USE_SK_RX_CHECKSUM
19379 - pAC->RxPort[1].RxCsum = 1;
19384 - dev->features |= NETIF_F_HIGHDMA;
19386 - error = register_netdev(dev);
19388 - printk(KERN_ERR "sk98lin: Could not register device"
19389 - " for second port. (%d)\n", error);
19390 - free_netdev(dev);
19391 - goto single_port;
19394 - pAC->dev[1] = dev;
19395 - memcpy(&dev->dev_addr,
19396 - &pAC->Addr.Net[1].CurrentMacAddress, 6);
19397 - memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
19399 - printk("%s: %s\n", dev->name, DeviceStr);
19400 - printk(" PrefPort:B RlmtMode:Dual Check Link State\n");
19405 - /* Save the hardware revision */
19406 - pAC->HWRevision = (((pAC->GIni.GIPciHwRev >> 4) & 0x0F)*10) +
19407 - (pAC->GIni.GIPciHwRev & 0x0F);
19409 - /* Set driver globals */
19410 - pAC->Pnmi.pDriverFileName = DRIVER_FILE_NAME;
19411 - pAC->Pnmi.pDriverReleaseDate = DRIVER_REL_DATE;
19413 - memset(&pAC->PnmiBackup, 0, sizeof(SK_PNMI_STRUCT_DATA));
19414 - memcpy(&pAC->PnmiBackup, &pAC->PnmiStruct, sizeof(SK_PNMI_STRUCT_DATA));
19418 - out_free_resources:
19419 - FreeResources(dev);
19421 - free_netdev(dev);
19422 - out_disable_device:
19423 - pci_disable_device(pdev);
19428 -static void __devexit skge_remove_one(struct pci_dev *pdev)
19430 - struct net_device *dev = pci_get_drvdata(pdev);
19431 - DEV_NET *pNet = netdev_priv(dev);
19432 - SK_AC *pAC = pNet->pAC;
19433 - struct net_device *otherdev = pAC->dev[1];
19435 - unregister_netdev(dev);
19437 - SkGeYellowLED(pAC, pAC->IoBase, 0);
19439 - if (pAC->BoardLevel == SK_INIT_RUN) {
19440 - SK_EVPARA EvPara;
19441 - unsigned long Flags;
19443 - /* board is still alive */
19444 - spin_lock_irqsave(&pAC->SlowPathLock, Flags);
19445 - EvPara.Para32[0] = 0;
19446 - EvPara.Para32[1] = -1;
19447 - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
19448 - EvPara.Para32[0] = 1;
19449 - EvPara.Para32[1] = -1;
19450 - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
19451 - SkEventDispatcher(pAC, pAC->IoBase);
19452 - /* disable interrupts */
19453 - SK_OUT32(pAC->IoBase, B0_IMSK, 0);
19454 - SkGeDeInit(pAC, pAC->IoBase);
19455 - spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
19456 - pAC->BoardLevel = SK_INIT_DATA;
19457 - /* We do NOT check here, if IRQ was pending, of course*/
19460 - if (pAC->BoardLevel == SK_INIT_IO) {
19461 - /* board is still alive */
19462 - SkGeDeInit(pAC, pAC->IoBase);
19463 - pAC->BoardLevel = SK_INIT_DATA;
19466 - FreeResources(dev);
19467 - free_netdev(dev);
19468 - if (otherdev != dev)
19469 - free_netdev(otherdev);
19474 -static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
19476 - struct net_device *dev = pci_get_drvdata(pdev);
19477 - DEV_NET *pNet = netdev_priv(dev);
19478 - SK_AC *pAC = pNet->pAC;
19479 - struct net_device *otherdev = pAC->dev[1];
19481 - if (netif_running(dev)) {
19482 - netif_carrier_off(dev);
19483 - DoPrintInterfaceChange = SK_FALSE;
19484 - SkDrvDeInitAdapter(pAC, 0); /* performs SkGeClose */
19485 - netif_device_detach(dev);
19487 - if (otherdev != dev) {
19488 - if (netif_running(otherdev)) {
19489 - netif_carrier_off(otherdev);
19490 - DoPrintInterfaceChange = SK_FALSE;
19491 - SkDrvDeInitAdapter(pAC, 1); /* performs SkGeClose */
19492 - netif_device_detach(otherdev);
19496 - pci_save_state(pdev);
19497 - pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
19498 - if (pAC->AllocFlag & SK_ALLOC_IRQ) {
19499 - free_irq(dev->irq, dev);
19501 - pci_disable_device(pdev);
19502 - pci_set_power_state(pdev, pci_choose_state(pdev, state));
19507 -static int skge_resume(struct pci_dev *pdev)
19509 - struct net_device *dev = pci_get_drvdata(pdev);
19510 - DEV_NET *pNet = netdev_priv(dev);
19511 - SK_AC *pAC = pNet->pAC;
19512 - struct net_device *otherdev = pAC->dev[1];
19515 - pci_set_power_state(pdev, PCI_D0);
19516 - pci_restore_state(pdev);
19517 - pci_enable_device(pdev);
19518 - pci_set_master(pdev);
19519 - if (pAC->GIni.GIMacsFound == 2)
19520 - ret = request_irq(dev->irq, SkGeIsr, IRQF_SHARED, "sk98lin", dev);
19522 - ret = request_irq(dev->irq, SkGeIsrOnePort, IRQF_SHARED, "sk98lin", dev);
19524 - printk(KERN_WARNING "sk98lin: unable to acquire IRQ %d\n", dev->irq);
19525 - pAC->AllocFlag &= ~SK_ALLOC_IRQ;
19527 - pci_disable_device(pdev);
19531 - netif_device_attach(dev);
19532 - if (netif_running(dev)) {
19533 - DoPrintInterfaceChange = SK_FALSE;
19534 - SkDrvInitAdapter(pAC, 0); /* first device */
19536 - if (otherdev != dev) {
19537 - netif_device_attach(otherdev);
19538 - if (netif_running(otherdev)) {
19539 - DoPrintInterfaceChange = SK_FALSE;
19540 - SkDrvInitAdapter(pAC, 1); /* second device */
19547 -#define skge_suspend NULL
19548 -#define skge_resume NULL
19551 -static struct pci_device_id skge_pci_tbl[] = {
19552 - { PCI_VENDOR_ID_3COM, 0x1700, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
19553 - { PCI_VENDOR_ID_3COM, 0x80eb, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
19554 - { PCI_VENDOR_ID_SYSKONNECT, 0x4300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
19555 - { PCI_VENDOR_ID_SYSKONNECT, 0x4320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
19556 -/* DLink card does not have valid VPD so this driver gags
19557 - * { PCI_VENDOR_ID_DLINK, 0x4c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
19559 - { PCI_VENDOR_ID_MARVELL, 0x4320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
19560 - { PCI_VENDOR_ID_MARVELL, 0x5005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
19561 - { PCI_VENDOR_ID_CNET, 0x434e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
19562 - { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
19563 - { PCI_VENDOR_ID_LINKSYS, 0x1064, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
19567 -MODULE_DEVICE_TABLE(pci, skge_pci_tbl);
19569 -static struct pci_driver skge_driver = {
19570 - .name = "sk98lin",
19571 - .id_table = skge_pci_tbl,
19572 - .probe = skge_probe_one,
19573 - .remove = __devexit_p(skge_remove_one),
19574 - .suspend = skge_suspend,
19575 - .resume = skge_resume,
19578 -static int __init skge_init(void)
19580 - return pci_register_driver(&skge_driver);
19583 -static void __exit skge_exit(void)
19585 - pci_unregister_driver(&skge_driver);
19587 +/*******************************************************************************
19591 + ******************************************************************************/
19593 -module_init(skge_init);
19594 -module_exit(skge_exit);
19595 diff -ruN linux/drivers/net/sk98lin/skgehwt.c linux-new/drivers/net/sk98lin/skgehwt.c
19596 --- linux/drivers/net/sk98lin/skgehwt.c 2006-09-20 05:42:06.000000000 +0200
19597 +++ linux-new/drivers/net/sk98lin/skgehwt.c 2006-07-28 14:13:54.000000000 +0200
19601 * Project: Gigabit Ethernet Adapters, Event Scheduler Module
19602 - * Version: $Revision$
19604 + * Version: $Revision$
19606 * Purpose: Hardware Timer
19608 ******************************************************************************/
19610 /******************************************************************************
19613 * (C)Copyright 1998-2002 SysKonnect GmbH.
19614 - * (C)Copyright 2002-2003 Marvell.
19615 + * (C)Copyright 2002-2004 Marvell.
19617 * This program is free software; you can redistribute it and/or modify
19618 * it under the terms of the GNU General Public License as published by
19620 * (at your option) any later version.
19622 * The information in this file is provided "AS IS" without warranty.
19625 ******************************************************************************/
19629 #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
19630 static const char SysKonnectFileId[] =
19631 - "@(#) $Id$ (C) Marvell.";
19632 + "@(#) $Id$ (C) Marvell.";
19635 #include "h/skdrv1st.h" /* Driver Specific Definitions */
19636 @@ -44,10 +46,10 @@
19638 * Prototypes of local functions.
19640 -#define SK_HWT_MAX (65000)
19641 +#define SK_HWT_MAX 65000UL * 160 /* ca. 10 sec. */
19643 /* correction factor */
19644 -#define SK_HWT_FAC (1000 * (SK_U32)pAC->GIni.GIHstClkFact / 100)
19645 +#define SK_HWT_FAC (10 * (SK_U32)pAC->GIni.GIHstClkFact / 16)
19648 * Initialize hardware timer.
19649 @@ -73,29 +75,21 @@
19651 SK_AC *pAC, /* Adapters context */
19652 SK_IOC Ioc, /* IoContext */
19653 -SK_U32 Time) /* Time in units of 16us to load the timer with. */
19654 +SK_U32 Time) /* Time in usec to load the timer */
19658 if (Time > SK_HWT_MAX)
19661 pAC->Hwt.TStart = Time;
19662 pAC->Hwt.TStop = 0L;
19667 - * if time < 16 us
19676 - SK_OUT32(Ioc, B2_TI_INI, Cnt * SK_HWT_FAC);
19678 - SK_OUT16(Ioc, B2_TI_CTRL, TIM_START); /* Start timer. */
19679 + SK_OUT32(Ioc, B2_TI_INI, Time * SK_HWT_FAC);
19681 + SK_OUT16(Ioc, B2_TI_CTRL, TIM_START); /* Start timer */
19683 pAC->Hwt.TActive = SK_TRUE;
19685 @@ -109,13 +103,12 @@
19686 SK_IOC Ioc) /* IoContext */
19688 SK_OUT16(Ioc, B2_TI_CTRL, TIM_STOP);
19691 SK_OUT16(Ioc, B2_TI_CTRL, TIM_CLR_IRQ);
19693 pAC->Hwt.TActive = SK_FALSE;
19698 * Stop hardware timer and read time elapsed since last start.
19700 @@ -129,6 +122,9 @@
19706 + TimerInt = CHIP_ID_YUKON_2(pAC) ? Y2_IS_TIMINT : IS_TIMINT;
19708 if (pAC->Hwt.TActive) {
19710 @@ -139,15 +135,15 @@
19712 SK_IN32(Ioc, B0_ISRC, &IStatus);
19714 - /* Check if timer expired (or wraped around) */
19715 - if ((TRead > pAC->Hwt.TStart) || (IStatus & IS_TIMINT)) {
19717 + /* Check if timer expired (or wrapped around) */
19718 + if ((TRead > pAC->Hwt.TStart) || ((IStatus & TimerInt) != 0)) {
19720 SkHwtStop(pAC, Ioc);
19723 pAC->Hwt.TStop = pAC->Hwt.TStart;
19728 pAC->Hwt.TStop = pAC->Hwt.TStart - TRead;
19731 @@ -162,9 +158,9 @@
19732 SK_IOC Ioc) /* IoContext */
19734 SkHwtStop(pAC, Ioc);
19737 pAC->Hwt.TStop = pAC->Hwt.TStart;
19740 SkTimerDone(pAC, Ioc);
19743 diff -ruN linux/drivers/net/sk98lin/skgeinit.c linux-new/drivers/net/sk98lin/skgeinit.c
19744 --- linux/drivers/net/sk98lin/skgeinit.c 2006-09-20 05:42:06.000000000 +0200
19745 +++ linux-new/drivers/net/sk98lin/skgeinit.c 2006-07-28 14:13:54.000000000 +0200
19749 * Project: Gigabit Ethernet Adapters, Common Modules
19750 - * Version: $Revision$
19752 + * Version: $Revision$
19754 * Purpose: Contains functions to initialize the adapter
19756 ******************************************************************************/
19758 /******************************************************************************
19761 * (C)Copyright 1998-2002 SysKonnect.
19762 - * (C)Copyright 2002-2003 Marvell.
19763 + * (C)Copyright 2002-2006 Marvell.
19765 * This program is free software; you can redistribute it and/or modify
19766 * it under the terms of the GNU General Public License as published by
19767 * the Free Software Foundation; either version 2 of the License, or
19768 * (at your option) any later version.
19770 * The information in this file is provided "AS IS" without warranty.
19773 ******************************************************************************/
19777 #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
19778 static const char SysKonnectFileId[] =
19779 - "@(#) $Id$ (C) Marvell.";
19780 + "@(#) $Id$ (C) Marvell.";
19785 int XsQOff; /* Sync Tx Queue Address Offset */
19786 int XaQOff; /* Async Tx Queue Address Offset */
19789 static struct s_QOffTab QOffTab[] = {
19790 {Q_R1, Q_XS1, Q_XA1}, {Q_R2, Q_XS2, Q_XA2}
19792 @@ -57,6 +59,126 @@
19797 +/******************************************************************************
19799 + * SkGePortVlan() - Enable / Disable VLAN support
19802 + * Enable or disable the VLAN support of the selected port.
19803 + * The new configuration is *not* saved over any SkGeStopPort() and
19804 + * SkGeInitPort() calls.
19805 + * Currently this function is only supported on Yukon-2/EC adapters.
19810 +void SkGePortVlan(
19811 +SK_AC *pAC, /* Adapter Context */
19812 +SK_IOC IoC, /* I/O Context */
19813 +int Port, /* Port number */
19814 +SK_BOOL Enable) /* Flag */
19819 + if (CHIP_ID_YUKON_2(pAC)) {
19821 + RxCtrl = RX_VLAN_STRIP_ON;
19822 + TxCtrl = TX_VLAN_TAG_ON;
19825 + RxCtrl = RX_VLAN_STRIP_OFF;
19826 + TxCtrl = TX_VLAN_TAG_OFF;
19829 + SK_OUT32(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), RxCtrl);
19831 + SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), TxCtrl);
19833 +} /* SkGePortVlan */
19836 +/******************************************************************************
19838 + * SkGeRxRss() - Enable / Disable RSS Hash Calculation
19841 + * Enable or disable the RSS hash calculation of the selected port.
19842 + * The new configuration is *not* saved over any SkGeStopPort() and
19843 + * SkGeInitPort() calls.
19844 + * Currently this function is only supported on Yukon-2/EC adapters.
19850 +SK_AC *pAC, /* Adapter Context */
19851 +SK_IOC IoC, /* I/O Context */
19852 +int Port, /* Port number */
19853 +SK_BOOL Enable) /* Flag */
19855 + if (CHIP_ID_YUKON_2(pAC)) {
19856 + SK_OUT32(IoC, Q_ADDR(pAC->GIni.GP[Port].PRxQOff, Q_CSR),
19857 + Enable ? BMU_ENA_RX_RSS_HASH : BMU_DIS_RX_RSS_HASH);
19862 +/******************************************************************************
19864 + * SkGeRxCsum() - Enable / Disable Receive Checksum
19867 + * Enable or disable the checksum of the selected port.
19868 + * The new configuration is *not* saved over any SkGeStopPort() and
19869 + * SkGeInitPort() calls.
19870 + * Currently this function is only supported on Yukon-2/EC adapters.
19876 +SK_AC *pAC, /* Adapter Context */
19877 +SK_IOC IoC, /* I/O Context */
19878 +int Port, /* Port number */
19879 +SK_BOOL Enable) /* Flag */
19881 + if (CHIP_ID_YUKON_2(pAC)) {
19882 + SK_OUT32(IoC, Q_ADDR(pAC->GIni.GP[Port].PRxQOff, Q_CSR),
19883 + Enable ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
19885 +} /* SkGeRxCsum */
19886 +#endif /* !SK_SLIM */
19888 +/******************************************************************************
19890 + * SkGePollRxD() - Enable / Disable Descriptor Polling of RxD Ring
19893 + * Enable or disable the descriptor polling of the receive descriptor
19894 + * ring (RxD) for port 'Port'.
19895 + * The new configuration is *not* saved over any SkGeStopPort() and
19896 + * SkGeInitPort() calls.
19902 +SK_AC *pAC, /* Adapter Context */
19903 +SK_IOC IoC, /* I/O Context */
19904 +int Port, /* Port Index (MAC_1 + n) */
19905 +SK_BOOL PollRxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */
19909 + pPrt = &pAC->GIni.GP[Port];
19911 + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), (SK_U32)((PollRxD) ?
19912 + CSR_ENA_POL : CSR_DIS_POL));
19913 +} /* SkGePollRxD */
19916 /******************************************************************************
19918 * SkGePollTxD() - Enable / Disable Descriptor Polling of TxD Rings
19923 -SK_AC *pAC, /* adapter context */
19924 -SK_IOC IoC, /* IO context */
19925 +SK_AC *pAC, /* Adapter Context */
19926 +SK_IOC IoC, /* I/O Context */
19927 int Port, /* Port Index (MAC_1 + n) */
19928 SK_BOOL PollTxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */
19930 @@ -86,13 +208,13 @@
19931 if (pPrt->PXSQSize != 0) {
19932 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), DWord);
19936 if (pPrt->PXAQSize != 0) {
19937 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), DWord);
19939 } /* SkGePollTxD */
19943 /******************************************************************************
19945 * SkGeYellowLED() - Switch the yellow LED on or off.
19946 @@ -107,20 +229,30 @@
19949 void SkGeYellowLED(
19950 -SK_AC *pAC, /* adapter context */
19951 -SK_IOC IoC, /* IO context */
19952 +SK_AC *pAC, /* Adapter Context */
19953 +SK_IOC IoC, /* I/O Context */
19954 int State) /* yellow LED state, 0 = OFF, 0 != ON */
19958 + if (CHIP_ID_YUKON_2(pAC)) {
19959 + /* different mapping on Yukon-2 */
19960 + LedReg = B0_CTST + 1;
19967 - /* Switch yellow LED OFF */
19968 - SK_OUT8(IoC, B0_LED, LED_STAT_OFF);
19969 + /* Switch state LED OFF */
19970 + SK_OUT8(IoC, LedReg, LED_STAT_OFF);
19973 - /* Switch yellow LED ON */
19974 - SK_OUT8(IoC, B0_LED, LED_STAT_ON);
19975 + /* Switch state LED ON */
19976 + SK_OUT8(IoC, LedReg, LED_STAT_ON);
19978 } /* SkGeYellowLED */
19980 +#endif /* !SK_SLIM */
19982 #if (!defined(SK_SLIM) || defined(GENESIS))
19983 /******************************************************************************
19984 @@ -141,8 +273,8 @@
19988 -SK_AC *pAC, /* adapter context */
19989 -SK_IOC IoC, /* IO context */
19990 +SK_AC *pAC, /* Adapter Context */
19991 +SK_IOC IoC, /* I/O Context */
19992 int Led, /* offset to the LED Init Value register */
19993 int Mode) /* Mode may be SK_LED_DIS, SK_LED_ENA, SK_LED_TST */
19995 @@ -167,18 +299,17 @@
19997 SK_OUT32(IoC, Led + XMIT_LED_CNT, 0);
19998 SK_OUT8(IoC, Led + XMIT_LED_TST, LED_T_OFF);
20004 - * 1000BT: The Transmit LED is driven by the PHY.
20005 + * 1000BT: the Transmit LED is driven by the PHY.
20006 * But the default LED configuration is used for
20007 * Level One and Broadcom PHYs.
20008 - * (Broadcom: It may be that PHY_B_PEC_EN_LTR has to be set.)
20009 - * (In this case it has to be added here. But we will see. XXX)
20010 + * (Broadcom: It may be that PHY_B_PEC_EN_LTR has to be set.
20011 + * In this case it has to be added here.)
20013 } /* SkGeXmitLED */
20014 -#endif /* !SK_SLIM || GENESIS */
20015 +#endif /* !SK_SLIM || GENESIS */
20018 /******************************************************************************
20019 @@ -199,7 +330,7 @@
20020 * 1: configuration error
20022 static int DoCalcAddr(
20023 -SK_AC *pAC, /* adapter context */
20024 +SK_AC *pAC, /* Adapter Context */
20025 SK_GEPORT SK_FAR *pPrt, /* port index */
20026 int QuSize, /* size of the queue to configure in kB */
20027 SK_U32 SK_FAR *StartVal, /* start value for address calculation */
20028 @@ -236,12 +367,35 @@
20030 /******************************************************************************
20032 + * SkGeRoundQueueSize() - Round the given queue size to the adpaters QZ units
20035 + * This function rounds the given queue size in kBs to adapter specific
20036 + * queue size units (Genesis and Yukon: 8 kB, Yukon-2/EC: 1 kB).
20039 + * the rounded queue size in kB
20041 +static int SkGeRoundQueueSize(
20042 +SK_AC *pAC, /* Adapter Context */
20043 +int QueueSizeKB) /* Queue size in kB */
20045 + int QueueSizeSteps;
20047 + QueueSizeSteps = (CHIP_ID_YUKON_2(pAC)) ? QZ_STEP_Y2 : QZ_STEP;
20049 + return((QueueSizeKB + QueueSizeSteps - 1) & ~(QueueSizeSteps - 1));
20050 +} /* SkGeRoundQueueSize */
20053 +/******************************************************************************
20055 * SkGeInitAssignRamToQueues() - allocate default queue sizes
20058 * This function assigns the memory to the different queues and ports.
20059 * When DualNet is set to SK_TRUE all ports get the same amount of memory.
20060 - * Otherwise the first port gets most of the memory and all the
20061 + * Otherwise the first port gets most of the memory and all the
20062 * other ports just the required minimum.
20063 * This function can only be called when pAC->GIni.GIRamSize and
20064 * pAC->GIni.GIMacsFound have been initialized, usually this happens
20065 @@ -254,102 +408,146 @@
20068 int SkGeInitAssignRamToQueues(
20069 -SK_AC *pAC, /* Adapter context */
20070 +SK_AC *pAC, /* Adapter Context */
20071 int ActivePort, /* Active Port in RLMT mode */
20072 -SK_BOOL DualNet) /* adapter context */
20073 +SK_BOOL DualNet) /* Dual Net active */
20076 int UsedKilobytes; /* memory already assigned */
20077 int ActivePortKilobytes; /* memory available for active port */
20078 - SK_GEPORT *pGePort;
20080 - UsedKilobytes = 0;
20081 + int MinQueueSize; /* min. memory for queues */
20082 + int TotalRamSize; /* total memory for queues */
20083 + SK_BOOL DualPortYukon2;
20086 if (ActivePort >= pAC->GIni.GIMacsFound) {
20088 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
20089 ("SkGeInitAssignRamToQueues: ActivePort (%d) invalid\n",
20093 - if (((pAC->GIni.GIMacsFound * (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE)) +
20094 - ((RAM_QUOTA_SYNC == 0) ? 0 : SK_MIN_TXQ_SIZE)) > pAC->GIni.GIRamSize) {
20096 + DualPortYukon2 = (CHIP_ID_YUKON_2(pAC) && pAC->GIni.GIMacsFound == 2);
20098 + TotalRamSize = pAC->GIni.GIRamSize;
20100 + if (DualPortYukon2) {
20101 + TotalRamSize *= 2;
20104 + MinQueueSize = SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE;
20106 + if (MinQueueSize > pAC->GIni.GIRamSize) {
20107 + MinQueueSize = pAC->GIni.GIRamSize;
20110 + if ((pAC->GIni.GIMacsFound * MinQueueSize +
20111 + RAM_QUOTA_SYNC * SK_MIN_TXQ_SIZE) > TotalRamSize) {
20113 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
20114 ("SkGeInitAssignRamToQueues: Not enough memory (%d)\n",
20115 - pAC->GIni.GIRamSize));
20121 /* every port gets the same amount of memory */
20122 - ActivePortKilobytes = pAC->GIni.GIRamSize / pAC->GIni.GIMacsFound;
20123 + ActivePortKilobytes = TotalRamSize / pAC->GIni.GIMacsFound;
20125 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
20127 - pGePort = &pAC->GIni.GP[i];
20129 + pPrt = &pAC->GIni.GP[i];
20131 + if (DualPortYukon2) {
20132 + ActivePortKilobytes = pAC->GIni.GIRamSize;
20134 /* take away the minimum memory for active queues */
20135 - ActivePortKilobytes -= (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE);
20136 + ActivePortKilobytes -= MinQueueSize;
20138 /* receive queue gets the minimum + 80% of the rest */
20139 - pGePort->PRxQSize = (int) (ROUND_QUEUE_SIZE_KB((
20140 - ActivePortKilobytes * (unsigned long) RAM_QUOTA_RX) / 100))
20141 + pPrt->PRxQSize = SkGeRoundQueueSize(pAC,
20142 + (int)((long)ActivePortKilobytes * RAM_QUOTA_RX) / 100)
20145 - ActivePortKilobytes -= (pGePort->PRxQSize - SK_MIN_RXQ_SIZE);
20146 + ActivePortKilobytes -= (pPrt->PRxQSize - SK_MIN_RXQ_SIZE);
20148 /* synchronous transmit queue */
20149 - pGePort->PXSQSize = 0;
20150 + pPrt->PXSQSize = 0;
20152 /* asynchronous transmit queue */
20153 - pGePort->PXAQSize = (int) ROUND_QUEUE_SIZE_KB(ActivePortKilobytes +
20154 - SK_MIN_TXQ_SIZE);
20155 + pPrt->PXAQSize = SkGeRoundQueueSize(pAC,
20156 + ActivePortKilobytes + SK_MIN_TXQ_SIZE);
20160 - /* Rlmt Mode or single link adapter */
20161 + else { /* RLMT Mode or single link adapter */
20163 + UsedKilobytes = 0;
20165 - /* Set standby queue size defaults for all standby ports */
20166 + /* set standby queue size defaults for all standby ports */
20167 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
20169 if (i != ActivePort) {
20170 - pGePort = &pAC->GIni.GP[i];
20171 + pPrt = &pAC->GIni.GP[i];
20173 - pGePort->PRxQSize = SK_MIN_RXQ_SIZE;
20174 - pGePort->PXAQSize = SK_MIN_TXQ_SIZE;
20175 - pGePort->PXSQSize = 0;
20176 + if (DualPortYukon2) {
20177 + pPrt->PRxQSize = SkGeRoundQueueSize(pAC,
20178 + (int)((long)(pAC->GIni.GIRamSize - MinQueueSize) *
20179 + RAM_QUOTA_RX) / 100) + SK_MIN_RXQ_SIZE;
20181 + pPrt->PXAQSize = pAC->GIni.GIRamSize - pPrt->PRxQSize;
20184 + pPrt->PRxQSize = SK_MIN_RXQ_SIZE;
20185 + pPrt->PXAQSize = SK_MIN_TXQ_SIZE;
20187 + pPrt->PXSQSize = 0;
20189 /* Count used RAM */
20190 - UsedKilobytes += pGePort->PRxQSize + pGePort->PXAQSize;
20191 + UsedKilobytes += pPrt->PRxQSize + pPrt->PXAQSize;
20195 - ActivePortKilobytes = pAC->GIni.GIRamSize - UsedKilobytes;
20196 + ActivePortKilobytes = TotalRamSize - UsedKilobytes;
20198 /* assign it to the active port */
20199 /* first take away the minimum memory */
20200 - ActivePortKilobytes -= (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE);
20201 - pGePort = &pAC->GIni.GP[ActivePort];
20202 + ActivePortKilobytes -= MinQueueSize;
20203 + pPrt = &pAC->GIni.GP[ActivePort];
20205 + /* receive queue gets 80% of the rest */
20206 + pPrt->PRxQSize = SkGeRoundQueueSize(pAC,
20207 + (int)((long)ActivePortKilobytes * RAM_QUOTA_RX) / 100);
20209 - /* receive queue get's the minimum + 80% of the rest */
20210 - pGePort->PRxQSize = (int) (ROUND_QUEUE_SIZE_KB((ActivePortKilobytes *
20211 - (unsigned long) RAM_QUOTA_RX) / 100)) + SK_MIN_RXQ_SIZE;
20212 + ActivePortKilobytes -= pPrt->PRxQSize;
20214 - ActivePortKilobytes -= (pGePort->PRxQSize - SK_MIN_RXQ_SIZE);
20215 + /* add the minimum memory for Rx queue */
20216 + pPrt->PRxQSize += MinQueueSize/2;
20218 /* synchronous transmit queue */
20219 - pGePort->PXSQSize = 0;
20220 + pPrt->PXSQSize = 0;
20222 - /* asynchronous transmit queue */
20223 - pGePort->PXAQSize = (int) ROUND_QUEUE_SIZE_KB(ActivePortKilobytes) +
20225 + /* asynchronous transmit queue gets 20% of the rest */
20226 + pPrt->PXAQSize = SkGeRoundQueueSize(pAC, ActivePortKilobytes) +
20227 + /* add the minimum memory for Tx queue */
20231 - VCPUprintf(0, "PRxQSize=%u, PXSQSize=%u, PXAQSize=%u\n",
20232 - pGePort->PRxQSize, pGePort->PXSQSize, pGePort->PXAQSize);
20236 + for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
20238 + pPrt = &pAC->GIni.GP[i];
20240 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
20241 + ("Port %d: RxQSize=%u, TxAQSize=%u, TxSQSize=%u\n",
20242 + i, pPrt->PRxQSize, pPrt->PXAQSize, pPrt->PXSQSize));
20244 +#endif /* DEBUG */
20247 } /* SkGeInitAssignRamToQueues */
20250 /******************************************************************************
20252 * SkGeCheckQSize() - Checks the Adapters Queue Size Configuration
20253 @@ -360,12 +558,12 @@
20255 * This requirements must be fullfilled to have a valid configuration:
20256 * - The size of all queues must not exceed GIRamSize.
20257 - * - The queue sizes must be specified in units of 8 kB.
20258 + * - The queue sizes must be specified in units of 8 kB (Genesis & Yukon).
20259 * - The size of Rx queues of available ports must not be
20260 - * smaller than 16 kB.
20261 + * smaller than 16 kB (Genesis & Yukon) resp. 10 kB (Yukon-2).
20262 * - The size of at least one Tx queue (synch. or asynch.)
20263 - * of available ports must not be smaller than 16 kB
20264 - * when Jumbo Frames are used.
20265 + * of available ports must not be smaller than 16 kB (Genesis & Yukon),
20266 + * resp. 10 kB (Yukon-2) when Jumbo Frames are used.
20267 * - The RAM start and end addresses must not be changed
20268 * for ports which are already initialized.
20269 * Furthermore SkGeCheckQSize() defines the Start and End Addresses
20270 @@ -376,7 +574,7 @@
20271 * 1: Queue Size Configuration invalid
20273 static int SkGeCheckQSize(
20274 -SK_AC *pAC, /* adapter context */
20275 +SK_AC *pAC, /* Adapter Context */
20276 int Port) /* port index */
20279 @@ -386,55 +584,68 @@
20282 int UsedMem; /* total memory used (max. found ports) */
20293 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
20294 pPrt = &pAC->GIni.GP[i];
20296 - if ((pPrt->PRxQSize & QZ_UNITS) != 0 ||
20297 - (pPrt->PXSQSize & QZ_UNITS) != 0 ||
20298 - (pPrt->PXAQSize & QZ_UNITS) != 0) {
20299 + if (CHIP_ID_YUKON_2(pAC)) {
20302 + else if (((pPrt->PRxQSize & QZ_UNITS) != 0 ||
20303 + (pPrt->PXSQSize & QZ_UNITS) != 0 ||
20304 + (pPrt->PXAQSize & QZ_UNITS) != 0)) {
20306 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG);
20310 - if (i == Port && pPrt->PRxQSize < SK_MIN_RXQ_SIZE) {
20312 + if (i == Port && pAC->GIni.GIRamSize > SK_MIN_RXQ_SIZE &&
20313 + pPrt->PRxQSize < SK_MIN_RXQ_SIZE) {
20314 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E011, SKERR_HWI_E011MSG);
20320 * the size of at least one Tx queue (synch. or asynch.) has to be > 0.
20321 * if Jumbo Frames are used, this size has to be >= 16 kB.
20323 if ((i == Port && pPrt->PXSQSize == 0 && pPrt->PXAQSize == 0) ||
20324 - (pAC->GIni.GIPortUsage == SK_JUMBO_LINK &&
20325 - ((pPrt->PXSQSize > 0 && pPrt->PXSQSize < SK_MIN_TXQ_SIZE) ||
20326 + (pPrt->PPortUsage == SK_JUMBO_LINK &&
20327 + ((pPrt->PXSQSize > 0 && pPrt->PXSQSize < SK_MIN_TXQ_SIZE) ||
20328 (pPrt->PXAQSize > 0 && pPrt->PXAQSize < SK_MIN_TXQ_SIZE)))) {
20329 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E023, SKERR_HWI_E023MSG);
20333 +#endif /* !SK_DIAG */
20335 UsedMem += pPrt->PRxQSize + pPrt->PXSQSize + pPrt->PXAQSize;
20337 + if (UsedMem > pAC->GIni.GIRamSize) {
20338 + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG);
20343 - if (UsedMem > pAC->GIni.GIRamSize) {
20344 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG);
20347 -#endif /* !SK_SLIM */
20349 +#endif /* !SK_SLIM */
20351 /* Now start address calculation */
20352 StartAddr = pAC->GIni.GIRamOffs;
20353 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
20355 pPrt = &pAC->GIni.GP[i];
20357 + if (CHIP_ID_YUKON_2(pAC)) {
20361 /* Calculate/Check values for the receive queue */
20362 Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PRxQSize, &StartAddr,
20363 &pPrt->PRxQRamStart, &pPrt->PRxQRamEnd);
20364 @@ -474,8 +685,8 @@
20367 static void SkGeInitMacArb(
20368 -SK_AC *pAC, /* adapter context */
20369 -SK_IOC IoC) /* IO context */
20370 +SK_AC *pAC, /* Adapter Context */
20371 +SK_IOC IoC) /* I/O Context */
20373 /* release local reset */
20374 SK_OUT16(IoC, B3_MA_TO_CTRL, MA_RST_CLR);
20375 @@ -514,8 +725,8 @@
20378 static void SkGeInitPktArb(
20379 -SK_AC *pAC, /* adapter context */
20380 -SK_IOC IoC) /* IO context */
20381 +SK_AC *pAC, /* Adapter Context */
20382 +SK_IOC IoC) /* I/O Context */
20384 /* release local reset */
20385 SK_OUT16(IoC, B3_PA_CTRL, PA_RST_CLR);
20386 @@ -531,7 +742,8 @@
20387 * NOTE: the packet arbiter timeout interrupt is needed for
20388 * half duplex hangup workaround
20390 - if (pAC->GIni.GIPortUsage != SK_JUMBO_LINK) {
20391 + if (pAC->GIni.GP[MAC_1].PPortUsage != SK_JUMBO_LINK &&
20392 + pAC->GIni.GP[MAC_2].PPortUsage != SK_JUMBO_LINK) {
20393 if (pAC->GIni.GIMacsFound == 1) {
20394 SK_OUT16(IoC, B3_PA_CTRL, PA_ENA_TO_TX1);
20396 @@ -554,14 +766,11 @@
20399 static void SkGeInitMacFifo(
20400 -SK_AC *pAC, /* adapter context */
20401 -SK_IOC IoC, /* IO context */
20402 +SK_AC *pAC, /* Adapter Context */
20403 +SK_IOC IoC, /* I/O Context */
20404 int Port) /* Port Index (MAC_1 + n) */
20412 * - release local reset
20413 @@ -569,63 +778,107 @@
20414 * - setup defaults for the control register
20415 * - enable the FIFO
20420 if (pAC->GIni.GIGenesis) {
20421 - /* Configure Rx MAC FIFO */
20422 + /* configure Rx MAC FIFO */
20423 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_CLR);
20424 SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_RX_CTRL_DEF);
20425 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
20427 - /* Configure Tx MAC FIFO */
20429 + /* configure Tx MAC FIFO */
20430 SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_RST_CLR);
20431 SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
20432 SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
20434 - /* Enable frame flushing if jumbo frames used */
20435 - if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
20437 + /* enable frame flushing if jumbo frames used */
20438 + if (pAC->GIni.GP[Port].PPortUsage == SK_JUMBO_LINK) {
20439 SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
20442 #endif /* GENESIS */
20446 if (pAC->GIni.GIYukon) {
20447 - /* set Rx GMAC FIFO Flush Mask */
20448 - SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), (SK_U16)RX_FF_FL_DEF_MSK);
20451 Word = (SK_U16)GMF_RX_CTRL_DEF;
20453 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
20454 - if (pAC->GIni.GIYukonLite && pAC->GIni.GIChipId == CHIP_ID_YUKON) {
20455 + if (pAC->GIni.GIYukonLite /* && pAC->GIni.GIChipId == CHIP_ID_YUKON */) {
20457 Word &= ~GMF_RX_F_FL_ON;
20460 - /* Configure Rx MAC FIFO */
20462 + /* configure Rx GMAC FIFO */
20463 SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR);
20464 SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), Word);
20466 - /* set Rx GMAC FIFO Flush Threshold (default: 0x0a -> 56 bytes) */
20467 - SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
20469 - /* Configure Tx MAC FIFO */
20471 + Word = RX_FF_FL_DEF_MSK;
20474 + if (HW_FEATURE(pAC, HWF_WA_DEV_4115)) {
20476 + * Flushing must be enabled (needed for ASF see dev. #4.29),
20477 + * but the flushing mask should be disabled (see dev. #4.115)
20481 +#endif /* !SK_DIAG */
20483 + /* set Rx GMAC FIFO Flush Mask (after clearing reset) */
20484 + SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), Word);
20486 + /* default: 0x0a -> 56 bytes on Yukon-1 and 64 bytes on Yukon-2 */
20487 + Word = (SK_U16)RX_GMF_FL_THR_DEF;
20489 + if (CHIP_ID_YUKON_2(pAC)) {
20490 + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC &&
20491 + pAC->GIni.GIAsfEnabled) {
20492 + /* WA for dev. #4.30 (reduce to 0x08 -> 48 bytes) */
20498 + * because Pause Packet Truncation in GMAC is not working
20499 + * we have to increase the Flush Threshold to 64 bytes
20500 + * in order to flush pause packets in Rx FIFO on Yukon-1
20505 + /* set Rx GMAC FIFO Flush Threshold (after clearing reset) */
20506 + SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), Word);
20508 + /* configure Tx GMAC FIFO */
20509 SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR);
20510 SK_OUT16(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U16)GMF_TX_CTRL_DEF);
20513 - SK_IN32(IoC, MR_ADDR(Port, RX_GMF_AF_THR), &DWord);
20514 - SK_IN32(IoC, MR_ADDR(Port, TX_GMF_AE_THR), &DWord);
20517 - /* set Tx GMAC FIFO Almost Empty Threshold */
20518 -/* SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_AE_THR), 0); */
20520 + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) {
20521 + /* set Rx Pause Threshold */
20522 + SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_LP_THR), (SK_U16)SK_ECU_LLPP);
20523 + SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_UP_THR), (SK_U16)SK_ECU_ULPP);
20525 + if (pAC->GIni.GP[Port].PPortUsage == SK_JUMBO_LINK) {
20526 + /* set Tx GMAC FIFO Almost Empty Threshold */
20527 + SK_OUT16(IoC, MR_ADDR(Port, TX_GMF_AE_THR),
20528 + (SK_U16)SK_ECU_AE_THR);
20529 + /* disable Store & Forward mode for TX */
20530 + SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), TX_STFW_DIS);
20534 + /* enable Store & Forward mode for TX */
20535 + SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), TX_STFW_ENA);
20537 +#endif /* TEST_ONLY */
20542 } /* SkGeInitMacFifo */
20544 -#ifdef SK_LNK_SYNC_CNT
20545 +#ifdef SK_LNK_SYNC_CNT
20546 /******************************************************************************
20548 * SkGeLoadLnkSyncCnt() - Load the Link Sync Counter and starts counting
20549 @@ -646,8 +899,8 @@
20552 void SkGeLoadLnkSyncCnt(
20553 -SK_AC *pAC, /* adapter context */
20554 -SK_IOC IoC, /* IO context */
20555 +SK_AC *pAC, /* Adapter Context */
20556 +SK_IOC IoC, /* I/O Context */
20557 int Port, /* Port Index (MAC_1 + n) */
20558 SK_U32 CntVal) /* Counter value */
20560 @@ -657,7 +910,7 @@
20564 - SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_STOP);
20565 + SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LNK_STOP);
20569 @@ -670,6 +923,7 @@
20570 IrqPend = SK_FALSE;
20571 SK_IN32(IoC, B0_ISRC, &ISrc);
20572 SK_IN32(IoC, B0_IMSK, &OrgIMsk);
20574 if (Port == MAC_1) {
20575 NewIMsk = OrgIMsk & ~IS_LNK_SYNC_M1;
20576 if ((ISrc & IS_LNK_SYNC_M1) != 0) {
20577 @@ -682,6 +936,7 @@
20583 SK_OUT32(IoC, B0_IMSK, NewIMsk);
20585 @@ -690,15 +945,17 @@
20586 SK_OUT32(IoC, MR_ADDR(Port, LNK_SYNC_INI), CntVal);
20588 /* start counter */
20589 - SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_START);
20590 + SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LNK_START);
20593 - /* clear the unexpected IRQ, and restore the interrupt mask */
20594 - SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_CLR_IRQ);
20595 + /* clear the unexpected IRQ */
20596 + SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LNK_CLR_IRQ);
20598 + /* restore the interrupt mask */
20599 SK_OUT32(IoC, B0_IMSK, OrgIMsk);
20601 } /* SkGeLoadLnkSyncCnt*/
20602 -#endif /* SK_LNK_SYNC_CNT */
20603 +#endif /* SK_LNK_SYNC_CNT */
20605 #if defined(SK_DIAG) || defined(SK_CFG_SYNC)
20606 /******************************************************************************
20607 @@ -730,8 +987,8 @@
20608 * synchronous queue is configured
20611 -SK_AC *pAC, /* adapter context */
20612 -SK_IOC IoC, /* IO context */
20613 +SK_AC *pAC, /* Adapter Context */
20614 +SK_IOC IoC, /* I/O Context */
20615 int Port, /* Port Index (MAC_1 + n) */
20616 SK_U32 IntTime, /* Interval Timer Value in units of 8ns */
20617 SK_U32 LimCount, /* Number of bytes to transfer during IntTime */
20618 @@ -749,16 +1006,16 @@
20619 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG);
20624 if (pAC->GIni.GP[Port].PXSQSize == 0) {
20625 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E009, SKERR_HWI_E009MSG);
20630 /* calculate register values */
20631 IntTime = (IntTime / 2) * pAC->GIni.GIHstClkFact / 100;
20632 LimCount = LimCount / 8;
20635 if (IntTime > TXA_MAX_VAL || LimCount > TXA_MAX_VAL) {
20636 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG);
20638 @@ -776,13 +1033,13 @@
20640 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
20641 TXA_ENA_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
20644 SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), IntTime);
20645 SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), LimCount);
20648 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
20649 (SK_U8)(SyncMode & (TXA_ENA_ALLOC | TXA_DIS_ALLOC)));
20652 if (IntTime != 0 || LimCount != 0) {
20653 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_DIS_FSYNC | TXA_START_RC);
20655 @@ -803,10 +1060,10 @@
20659 -static void DoInitRamQueue(
20660 -SK_AC *pAC, /* adapter context */
20661 -SK_IOC IoC, /* IO context */
20662 -int QuIoOffs, /* Queue IO Address Offset */
20663 +void DoInitRamQueue(
20664 +SK_AC *pAC, /* Adapter Context */
20665 +SK_IOC IoC, /* I/O Context */
20666 +int QuIoOffs, /* Queue I/O Address Offset */
20667 SK_U32 QuStartAddr, /* Queue Start Address */
20668 SK_U32 QuEndAddr, /* Queue End Address */
20669 int QuType) /* Queue Type (SK_RX_SRAM_Q|SK_RX_BRAM_Q|SK_TX_RAM_Q) */
20670 @@ -839,8 +1096,7 @@
20672 /* continue with SK_RX_BRAM_Q */
20674 - /* write threshold for Rx Queue */
20676 + /* write threshold for Rx Queue (Pause packets) */
20677 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RX_UTPP), RxUpThresVal);
20678 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RX_LTPP), RxLoThresVal);
20680 @@ -854,7 +1110,8 @@
20681 * or YUKON is used ((GMAC Tx FIFO is only 1 kB)
20682 * we NEED Store & Forward of the RAM buffer.
20684 - if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK ||
20685 + if (pAC->GIni.GP[MAC_1].PPortUsage == SK_JUMBO_LINK ||
20686 + pAC->GIni.GP[MAC_2].PPortUsage == SK_JUMBO_LINK ||
20687 pAC->GIni.GIYukon) {
20688 /* enable Store & Forward Mode for the Tx Side */
20689 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_ENA_STFWD);
20690 @@ -883,8 +1140,8 @@
20693 static void SkGeInitRamBufs(
20694 -SK_AC *pAC, /* adapter context */
20695 -SK_IOC IoC, /* IO context */
20696 +SK_AC *pAC, /* Adapter Context */
20697 +SK_IOC IoC, /* I/O Context */
20698 int Port) /* Port Index (MAC_1 + n) */
20701 @@ -892,8 +1149,8 @@
20703 pPrt = &pAC->GIni.GP[Port];
20705 - if (pPrt->PRxQSize == SK_MIN_RXQ_SIZE) {
20706 - RxQType = SK_RX_SRAM_Q; /* small Rx Queue */
20707 + if (pPrt->PRxQSize <= SK_MIN_RXQ_SIZE) {
20708 + RxQType = SK_RX_SRAM_Q; /* small Rx Queue */
20711 RxQType = SK_RX_BRAM_Q; /* big Rx Queue */
20712 @@ -901,10 +1158,10 @@
20714 DoInitRamQueue(pAC, IoC, pPrt->PRxQOff, pPrt->PRxQRamStart,
20715 pPrt->PRxQRamEnd, RxQType);
20718 DoInitRamQueue(pAC, IoC, pPrt->PXsQOff, pPrt->PXsQRamStart,
20719 pPrt->PXsQRamEnd, SK_TX_RAM_Q);
20722 DoInitRamQueue(pAC, IoC, pPrt->PXaQOff, pPrt->PXaQRamStart,
20723 pPrt->PXaQRamEnd, SK_TX_RAM_Q);
20725 @@ -924,27 +1181,38 @@
20729 -static void SkGeInitRamIface(
20730 -SK_AC *pAC, /* adapter context */
20731 -SK_IOC IoC) /* IO context */
20732 +void SkGeInitRamIface(
20733 +SK_AC *pAC, /* Adapter Context */
20734 +SK_IOC IoC) /* I/O Context */
20736 - /* release local reset */
20737 - SK_OUT16(IoC, B3_RI_CTRL, RI_RST_CLR);
20741 - /* configure timeout values */
20742 - SK_OUT8(IoC, B3_RI_WTO_R1, SK_RI_TO_53);
20743 - SK_OUT8(IoC, B3_RI_WTO_XA1, SK_RI_TO_53);
20744 - SK_OUT8(IoC, B3_RI_WTO_XS1, SK_RI_TO_53);
20745 - SK_OUT8(IoC, B3_RI_RTO_R1, SK_RI_TO_53);
20746 - SK_OUT8(IoC, B3_RI_RTO_XA1, SK_RI_TO_53);
20747 - SK_OUT8(IoC, B3_RI_RTO_XS1, SK_RI_TO_53);
20748 - SK_OUT8(IoC, B3_RI_WTO_R2, SK_RI_TO_53);
20749 - SK_OUT8(IoC, B3_RI_WTO_XA2, SK_RI_TO_53);
20750 - SK_OUT8(IoC, B3_RI_WTO_XS2, SK_RI_TO_53);
20751 - SK_OUT8(IoC, B3_RI_RTO_R2, SK_RI_TO_53);
20752 - SK_OUT8(IoC, B3_RI_RTO_XA2, SK_RI_TO_53);
20753 - SK_OUT8(IoC, B3_RI_RTO_XS2, SK_RI_TO_53);
20754 + if (CHIP_ID_YUKON_2(pAC)) {
20755 + RamBuffers = pAC->GIni.GIMacsFound;
20761 + for (i = 0; i < RamBuffers; i++) {
20762 + /* release local reset */
20763 + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_CTRL), (SK_U8)RI_RST_CLR);
20765 + /* configure timeout values */
20766 + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
20767 + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
20768 + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
20769 + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
20770 + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
20771 + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
20772 + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
20773 + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
20774 + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
20775 + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
20776 + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
20777 + SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
20779 } /* SkGeInitRamIface */
20782 @@ -959,41 +1227,91 @@
20785 static void SkGeInitBmu(
20786 -SK_AC *pAC, /* adapter context */
20787 -SK_IOC IoC, /* IO context */
20788 +SK_AC *pAC, /* Adapter Context */
20789 +SK_IOC IoC, /* I/O Context */
20790 int Port) /* Port Index (MAC_1 + n) */
20798 pPrt = &pAC->GIni.GP[Port];
20800 RxWm = SK_BMU_RX_WM;
20801 TxWm = SK_BMU_TX_WM;
20803 - if (!pAC->GIni.GIPciSlot64 && !pAC->GIni.GIPciClock66) {
20804 - /* for better performance */
20809 - /* Rx Queue: Release all local resets and set the watermark */
20810 - SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_CLR_RESET);
20811 - SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_F), RxWm);
20812 + if (CHIP_ID_YUKON_2(pAC)) {
20815 - * Tx Queue: Release all local resets if the queue is used !
20818 - if (pPrt->PXSQSize != 0) {
20819 - SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_CLR_RESET);
20820 - SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_F), TxWm);
20821 + if (pAC->GIni.GIPciBus == SK_PEX_BUS) {
20822 + /* for better performance set it to 128 */
20823 + RxWm = SK_BMU_RX_WM_PEX;
20826 + /* Rx Queue: Release all local resets and set the watermark */
20827 + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), BMU_CLR_RESET);
20828 + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), BMU_OPER_INIT);
20829 + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), BMU_FIFO_OP_ON);
20831 + SK_OUT16(IoC, Q_ADDR(pPrt->PRxQOff, Q_WM), RxWm);
20833 + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U &&
20834 + pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A1) {
20835 + /* MAC Rx RAM Read is controlled by hardware */
20836 + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_F), F_M_RX_RAM_DIS);
20840 + * Tx Queue: Release all local resets if the queue is used !
20843 + if (pPrt->PXSQSize != 0 && HW_SYNC_TX_SUPPORTED(pAC)) {
20844 + /* Yukon-EC doesn't have a synchronous Tx queue */
20845 + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), BMU_CLR_RESET);
20846 + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), BMU_OPER_INIT);
20847 + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), BMU_FIFO_OP_ON);
20849 + SK_OUT16(IoC, Q_ADDR(pPrt->PXsQOff, Q_WM), TxWm);
20852 + if (pPrt->PXAQSize != 0) {
20854 + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), BMU_CLR_RESET);
20855 + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), BMU_OPER_INIT);
20856 + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), BMU_FIFO_OP_ON);
20858 + SK_OUT16(IoC, Q_ADDR(pPrt->PXaQOff, Q_WM), TxWm);
20860 + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U &&
20861 + pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A0) {
20862 + /* fix for Yukon-EC Ultra: set BMU FIFO level */
20863 + SK_OUT16(IoC, Q_ADDR(pPrt->PXaQOff, Q_AL), SK_ECU_TXFF_LEV);
20868 - if (pPrt->PXAQSize != 0) {
20869 - SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_CLR_RESET);
20870 - SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_F), TxWm);
20872 + if (!pAC->GIni.GIPciSlot64 && !pAC->GIni.GIPciClock66) {
20873 + /* for better performance */
20878 + /* Rx Queue: Release all local resets and set the watermark */
20879 + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_CLR_RESET);
20880 + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_F), RxWm);
20883 + * Tx Queue: Release all local resets if the queue is used !
20886 + if (pPrt->PXSQSize != 0) {
20887 + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_CLR_RESET);
20888 + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_F), TxWm);
20891 + if (pPrt->PXAQSize != 0) {
20892 + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_CLR_RESET);
20893 + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_F), TxWm);
20897 * Do NOT enable the descriptor poll timers here, because
20898 @@ -1017,20 +1335,29 @@
20900 static SK_U32 TestStopBit(
20901 SK_AC *pAC, /* Adapter Context */
20902 -SK_IOC IoC, /* IO Context */
20903 -int QuIoOffs) /* Queue IO Address Offset */
20904 +SK_IOC IoC, /* I/O Context */
20905 +int QuIoOffs) /* Queue I/O Address Offset */
20907 SK_U32 QuCsr; /* CSR contents */
20909 SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
20911 - if ((QuCsr & (CSR_STOP | CSR_SV_IDLE)) == 0) {
20912 - /* Stop Descriptor overridden by start command */
20913 - SK_OUT32(IoC, Q_ADDR(QuIoOffs, Q_CSR), CSR_STOP);
20915 - SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
20916 + if (CHIP_ID_YUKON_2(pAC)) {
20917 + if ((QuCsr & (BMU_STOP | BMU_IDLE)) == 0) {
20918 + /* Stop Descriptor overridden by start command */
20919 + SK_OUT32(IoC, Q_ADDR(QuIoOffs, Q_CSR), BMU_STOP);
20921 + SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
20925 + if ((QuCsr & (CSR_STOP | CSR_SV_IDLE)) == 0) {
20926 + /* Stop Descriptor overridden by start command */
20927 + SK_OUT32(IoC, Q_ADDR(QuIoOffs, Q_CSR), CSR_STOP);
20929 + SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
20934 } /* TestStopBit */
20936 @@ -1054,8 +1381,8 @@
20937 * has to be stopped once before.
20938 * SK_STOP_ALL SK_STOP_TX + SK_STOP_RX
20940 - * RstMode = SK_SOFT_RST Resets the MAC. The PHY is still alive.
20941 - * SK_HARD_RST Resets the MAC and the PHY.
20942 + * RstMode = SK_SOFT_RST Resets the MAC, the PHY is still alive.
20943 + * SK_HARD_RST Resets the MAC and the PHY.
20946 * 1) A Link Down event was signaled for a port. Therefore the activity
20947 @@ -1114,56 +1441,82 @@
20951 -SK_AC *pAC, /* adapter context */
20952 -SK_IOC IoC, /* I/O context */
20953 -int Port, /* port to stop (MAC_1 + n) */
20954 +SK_AC *pAC, /* Adapter Context */
20955 +SK_IOC IoC, /* I/O Context */
20956 +int Port, /* Port to stop (MAC_1 + n) */
20957 int Dir, /* Direction to Stop (SK_STOP_RX, SK_STOP_TX, SK_STOP_ALL) */
20958 int RstMode)/* Reset Mode (SK_SOFT_RST, SK_HARD_RST) */
20962 -#endif /* !SK_DIAG */
20973 + SK_U8 rsl; /* FIFO read shadow level */
20974 + SK_U8 rl; /* FIFO read level */
20978 pPrt = &pAC->GIni.GP[Port];
20980 + /* set the proper values of Q_CSR register layout depending on the chip */
20981 + if (CHIP_ID_YUKON_2(pAC)) {
20982 + CsrStart = BMU_START;
20983 + CsrStop = BMU_STOP;
20984 + CsrIdle = BMU_IDLE;
20985 + CsrTest = BMU_IDLE;
20988 + CsrStart = CSR_START;
20989 + CsrStop = CSR_STOP;
20990 + CsrIdle = CSR_SV_IDLE;
20991 + CsrTest = CSR_SV_IDLE | CSR_STOP;
20994 if ((Dir & SK_STOP_TX) != 0) {
20995 - /* disable receiver and transmitter */
20996 - SkMacRxTxDisable(pAC, IoC, Port);
20999 + if (!pAC->GIni.GIAsfEnabled) {
21000 + /* disable receiver and transmitter */
21001 + SkMacRxTxDisable(pAC, IoC, Port);
21004 /* stop both transmit queues */
21005 + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CsrStop);
21006 + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CsrStop);
21008 * If the BMU is in the reset state CSR_STOP will terminate
21011 - SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_STOP);
21012 - SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_STOP);
21014 ToutStart = SkOsGetTime(pAC);
21018 - * Clear packet arbiter timeout to make sure
21019 - * this loop will terminate.
21021 - SK_OUT16(IoC, B3_PA_CTRL, (SK_U16)((Port == MAC_1) ?
21022 - PA_CLR_TO_TX1 : PA_CLR_TO_TX2));
21025 - * If the transfer stucks at the MAC the STOP command will not
21026 - * terminate if we don't flush the XMAC's transmit FIFO !
21028 - SkMacFlushTxFifo(pAC, IoC, Port);
21030 - XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff);
21032 + if (pAC->GIni.GIGenesis) {
21033 + /* clear Tx packet arbiter timeout IRQ */
21034 + SK_OUT16(IoC, B3_PA_CTRL, (SK_U16)((Port == MAC_1) ?
21035 + PA_CLR_TO_TX1 : PA_CLR_TO_TX2));
21037 + * If the transfer stucks at the XMAC the STOP command will not
21038 + * terminate if we don't flush the XMAC's transmit FIFO !
21040 + SkMacFlushTxFifo(pAC, IoC, Port);
21042 +#endif /* GENESIS */
21044 XaCsr = TestStopBit(pAC, IoC, pPrt->PXaQOff);
21046 + if (HW_SYNC_TX_SUPPORTED(pAC)) {
21047 + XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff);
21053 if (SkOsGetTime(pAC) - ToutStart > (SK_TICKS_PER_SEC / 18)) {
21055 * Timeout of 1/18 second reached.
21056 @@ -1171,67 +1524,115 @@
21060 - /* Might be a problem when the driver event handler
21061 - * calls StopPort again. XXX.
21063 + * If BMU stop doesn't terminate, we assume that
21064 + * we have a stable state and can reset the BMU,
21065 + * the Prefetch Unit, and RAM buffer now.
21068 - /* Fatal Error, Loop aborted */
21069 - SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E018,
21070 - SKERR_HWI_E018MSG);
21072 - Para.Para64 = Port;
21073 - SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
21074 -#endif /* !SK_DIAG */
21076 + break; /* ===> leave do/while loop here */
21079 - * Cache incoherency workaround: Assume a start command
21080 + * Cache incoherency workaround: assume a start command
21081 * has been lost while sending the frame.
21083 ToutStart = SkOsGetTime(pAC);
21085 - if ((XsCsr & CSR_STOP) != 0) {
21086 - SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_START);
21087 + if ((XsCsr & CsrStop) != 0) {
21088 + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CsrStart);
21090 - if ((XaCsr & CSR_STOP) != 0) {
21091 - SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_START);
21093 + if ((XaCsr & CsrStop) != 0) {
21094 + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CsrStart);
21099 + * After the previous operations the X(s|a)Csr does no
21100 + * longer contain the proper values
21102 + XaCsr = TestStopBit(pAC, IoC, pPrt->PXaQOff);
21104 + if (HW_SYNC_TX_SUPPORTED(pAC)) {
21105 + XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff);
21112 * Because of the ASIC problem report entry from 21.08.1998 it is
21113 * required to wait until CSR_STOP is reset and CSR_SV_IDLE is set.
21114 + * (valid for GENESIS only)
21116 - } while ((XsCsr & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE ||
21117 - (XaCsr & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE);
21118 + } while (((XsCsr & CsrTest) != CsrIdle ||
21119 + (XaCsr & CsrTest) != CsrIdle));
21121 + if (pAC->GIni.GIAsfEnabled) {
21123 - /* Reset the MAC depending on the RstMode */
21124 - if (RstMode == SK_SOFT_RST) {
21125 - SkMacSoftRst(pAC, IoC, Port);
21126 + pPrt->PState = (RstMode == SK_SOFT_RST) ? SK_PRT_STOP :
21130 - SkMacHardRst(pAC, IoC, Port);
21131 + /* Reset the MAC depending on the RstMode */
21132 + if (RstMode == SK_SOFT_RST) {
21134 + SkMacSoftRst(pAC, IoC, Port);
21138 + if (HW_FEATURE(pAC, HWF_WA_DEV_472) && Port == MAC_1 &&
21139 + pAC->GIni.GP[MAC_2].PState == SK_PRT_RUN) {
21141 + pAC->GIni.GP[MAC_1].PState = SK_PRT_RESET;
21143 + /* set GPHY Control reset */
21144 + SK_OUT8(IoC, MR_ADDR(MAC_1, GPHY_CTRL), (SK_U8)GPC_RST_SET);
21148 + SkMacHardRst(pAC, IoC, Port);
21150 +#else /* !SK_DIAG */
21151 + SkMacHardRst(pAC, IoC, Port);
21152 +#endif /* !SK_DIAG */
21156 - /* Disable Force Sync bit and Enable Alloc bit */
21158 + /* disable Force Sync bit and Enable Alloc bit */
21159 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
21160 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
21163 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
21164 SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), 0L);
21165 SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), 0L);
21167 /* Perform a local reset of the port's Tx path */
21168 + if (CHIP_ID_YUKON_2(pAC)) {
21169 + /* Reset the PCI FIFO of the async Tx queue */
21170 + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR),
21171 + BMU_RST_SET | BMU_FIFO_RST);
21173 + /* Reset the PCI FIFO of the sync Tx queue */
21174 + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR),
21175 + BMU_RST_SET | BMU_FIFO_RST);
21177 + /* Reset the Tx prefetch units */
21178 + SK_OUT32(IoC, Y2_PREF_Q_ADDR(pPrt->PXaQOff, PREF_UNIT_CTRL_REG),
21179 + PREF_UNIT_RST_SET);
21180 + SK_OUT32(IoC, Y2_PREF_Q_ADDR(pPrt->PXsQOff, PREF_UNIT_CTRL_REG),
21181 + PREF_UNIT_RST_SET);
21184 + /* Reset the PCI FIFO of the async Tx queue */
21185 + SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_SET_RESET);
21186 + /* Reset the PCI FIFO of the sync Tx queue */
21187 + SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_SET_RESET);
21190 - /* Reset the PCI FIFO of the async Tx queue */
21191 - SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_SET_RESET);
21192 - /* Reset the PCI FIFO of the sync Tx queue */
21193 - SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_SET_RESET);
21194 /* Reset the RAM Buffer async Tx queue */
21195 SK_OUT8(IoC, RB_ADDR(pPrt->PXaQOff, RB_CTRL), RB_RST_SET);
21196 /* Reset the RAM Buffer sync Tx queue */
21197 SK_OUT8(IoC, RB_ADDR(pPrt->PXsQOff, RB_CTRL), RB_RST_SET);
21200 /* Reset Tx MAC FIFO */
21202 if (pAC->GIni.GIGenesis) {
21203 @@ -1243,74 +1644,132 @@
21204 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_DIS);
21206 #endif /* GENESIS */
21210 if (pAC->GIni.GIYukon) {
21211 - /* Reset TX MAC FIFO */
21212 - SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_SET);
21213 + /* do the reset only if ASF is not enabled */
21214 + if (!pAC->GIni.GIAsfEnabled) {
21215 + /* Reset Tx MAC FIFO */
21216 + SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_SET);
21219 + /* set Pause Off */
21220 + SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_PAUSE_OFF);
21225 if ((Dir & SK_STOP_RX) != 0) {
21227 - * The RX Stop Command will not terminate if no buffers
21228 - * are queued in the RxD ring. But it will always reach
21229 - * the Idle state. Therefore we can use this feature to
21230 - * stop the transfer of received packets.
21232 - /* stop the port's receive queue */
21233 - SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_STOP);
21238 + if (CHIP_ID_YUKON_2(pAC)) {
21240 - * Clear packet arbiter timeout to make sure
21241 - * this loop will terminate
21242 + * The RX Stop command will not work for Yukon-2 if the BMU does not
21243 + * reach the end of packet and since we can't make sure that we have
21244 + * incoming data, we must reset the BMU while it is not during a DMA
21245 + * transfer. Since it is possible that the RX path is still active,
21246 + * the RX RAM buffer will be stopped first, so any possible incoming
21247 + * data will not trigger a DMA. After the RAM buffer is stopped, the
21248 + * BMU is polled until any DMA in progress is ended and only then it
21251 - SK_OUT16(IoC, B3_PA_CTRL, (SK_U16)((Port == MAC_1) ?
21252 - PA_CLR_TO_RX1 : PA_CLR_TO_RX2));
21254 - DWord = TestStopBit(pAC, IoC, pPrt->PRxQOff);
21255 + /* disable the RAM Buffer receive queue */
21256 + SK_OUT8(IoC, RB_ADDR(pPrt->PRxQOff, RB_CTRL), RB_DIS_OP_MD);
21258 - /* timeout if i==0 (bug fix for #10748) */
21260 - SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E024,
21261 - SKERR_HWI_E024MSG);
21265 + SK_IN8(IoC, RB_ADDR(pPrt->PRxQOff, Q_RX_RSL), &rsl);
21266 + SK_IN8(IoC, RB_ADDR(pPrt->PRxQOff, Q_RX_RL), &rl);
21274 + * If the Rx side is blocked, the above loop cannot terminate.
21275 + * But, if there was any traffic it should be terminated, now.
21276 + * However, stop the Rx BMU and the Prefetch Unit !
21278 + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR),
21279 + BMU_RST_SET | BMU_FIFO_RST);
21280 + /* reset the Rx prefetch unit */
21281 + SK_OUT32(IoC, Y2_PREF_Q_ADDR(pPrt->PRxQOff, PREF_UNIT_CTRL_REG),
21282 + PREF_UNIT_RST_SET);
21286 - * because of the ASIC problem report entry from 21.08.98
21287 - * it is required to wait until CSR_STOP is reset and
21288 - * CSR_SV_IDLE is set.
21289 + * The RX Stop Command will not terminate if no buffers
21290 + * are queued in the RxD ring. But it will always reach
21291 + * the Idle state. Therefore we can use this feature to
21292 + * stop the transfer of received packets.
21294 - } while ((DWord & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE);
21295 + /* stop the port's receive queue */
21296 + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CsrStop);
21298 - /* The path data transfer activity is fully stopped now */
21302 + if (pAC->GIni.GIGenesis) {
21303 + /* clear Rx packet arbiter timeout IRQ */
21304 + SK_OUT16(IoC, B3_PA_CTRL, (SK_U16)((Port == MAC_1) ?
21305 + PA_CLR_TO_RX1 : PA_CLR_TO_RX2));
21307 +#endif /* GENESIS */
21309 - /* Perform a local reset of the port's Rx path */
21310 + RxCsr = TestStopBit(pAC, IoC, pPrt->PRxQOff);
21312 + /* timeout if i==0 (bug fix for #10748) */
21314 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E024,
21315 + SKERR_HWI_E024MSG);
21319 + * Because of the ASIC problem report entry from 21.08.1998 it is
21320 + * required to wait until CSR_STOP is reset and CSR_SV_IDLE is set.
21321 + * (valid for GENESIS only)
21323 + } while ((RxCsr & CsrTest) != CsrIdle);
21324 + /* The path data transfer activity is fully stopped now */
21326 + /* Perform a local reset of the port's Rx path */
21327 + /* Reset the PCI FIFO of the Rx queue */
21328 + SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_SET_RESET);
21331 - /* Reset the PCI FIFO of the Rx queue */
21332 - SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_SET_RESET);
21333 /* Reset the RAM Buffer receive queue */
21334 SK_OUT8(IoC, RB_ADDR(pPrt->PRxQOff, RB_CTRL), RB_RST_SET);
21336 - /* Reset Rx MAC FIFO */
21338 if (pAC->GIni.GIGenesis) {
21341 + /* Reset Rx MAC FIFO */
21342 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_SET);
21344 /* switch Rx LED off, stop the LED counter */
21345 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, RX_LED_INI), SK_LED_DIS);
21347 #endif /* GENESIS */
21351 - if (pAC->GIni.GIYukon) {
21352 + if (pAC->GIni.GIYukon && !pAC->GIni.GIAsfEnabled) {
21353 /* Reset Rx MAC FIFO */
21354 SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_RST_SET);
21357 +#ifndef NDIS_MINIPORT_DRIVER /* temp. ifndef, remove after PM module rework*/
21358 + /* WA for Dev. #4.169 */
21359 + if ((pAC->GIni.GIChipId == CHIP_ID_YUKON ||
21360 + pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) &&
21361 + RstMode == SK_HARD_RST) {
21362 + /* set Link Control reset */
21363 + SK_OUT8(IoC, MR_ADDR(Port, GMAC_LINK_CTRL), (SK_U8)GMLC_RST_SET);
21365 + /* clear Link Control reset */
21366 + SK_OUT8(IoC, MR_ADDR(Port, GMAC_LINK_CTRL), (SK_U8)GMLC_RST_CLR);
21368 +#endif /* !NDIS_MINIPORT */
21371 } /* SkGeStopPort */
21372 @@ -1327,8 +1786,8 @@
21375 static void SkGeInit0(
21376 -SK_AC *pAC, /* adapter context */
21377 -SK_IOC IoC) /* IO context */
21378 +SK_AC *pAC, /* Adapter Context */
21379 +SK_IOC IoC) /* I/O Context */
21383 @@ -1337,6 +1796,7 @@
21384 pPrt = &pAC->GIni.GP[i];
21386 pPrt->PState = SK_PRT_RESET;
21387 + pPrt->PPortUsage = SK_RED_LINK;
21388 pPrt->PRxQOff = QOffTab[i].RxQOff;
21389 pPrt->PXsQOff = QOffTab[i].XsQOff;
21390 pPrt->PXaQOff = QOffTab[i].XaQOff;
21391 @@ -1365,22 +1825,226 @@
21392 pPrt->PLipaAutoNeg = (SK_U8)SK_LIPA_UNKNOWN;
21393 pPrt->PAutoNegFail = SK_FALSE;
21394 pPrt->PHWLinkUp = SK_FALSE;
21395 - pPrt->PLinkBroken = SK_TRUE; /* See WA code */
21396 + pPrt->PLinkBroken = SK_TRUE; /* See WA code */
21397 pPrt->PPhyPowerState = PHY_PM_OPERATIONAL_MODE;
21398 pPrt->PMacColThres = TX_COL_DEF;
21399 pPrt->PMacJamLen = TX_JAM_LEN_DEF;
21400 pPrt->PMacJamIpgVal = TX_JAM_IPG_DEF;
21401 pPrt->PMacJamIpgData = TX_IPG_JAM_DEF;
21402 + pPrt->PMacBackOffLim = TX_BOF_LIM_DEF;
21403 + pPrt->PMacDataBlind = DATA_BLIND_DEF;
21404 pPrt->PMacIpgData = IPG_DATA_DEF;
21405 pPrt->PMacLimit4 = SK_FALSE;
21408 - pAC->GIni.GIPortUsage = SK_RED_LINK;
21409 pAC->GIni.GILedBlinkCtrl = (SK_U16)OemConfig.Value;
21410 - pAC->GIni.GIValIrqMask = IS_ALL_MSK;
21411 + pAC->GIni.GIChipCap = 0;
21413 + for (i = 0; i < 4; i++) {
21414 + pAC->GIni.HwF.Features[i]= 0x00000000;
21415 + pAC->GIni.HwF.OnMask[i] = 0x00000000;
21416 + pAC->GIni.HwF.OffMask[i] = 0x00000000;
21421 +#ifdef SK_PCI_RESET
21422 +/******************************************************************************
21424 + * SkGePciReset() - Reset PCI interface
21427 + * o Read PCI configuration.
21428 + * o Change power state to 3.
21429 + * o Change power state to 0.
21430 + * o Restore PCI configuration.
21434 + * 1: Power state could not be changed to 3.
21436 +static int SkGePciReset(
21437 +SK_AC *pAC, /* Adapter Context */
21438 +SK_IOC IoC) /* I/O Context */
21447 + SK_U8 ConfigSpace[PCI_CFG_SIZE];
21450 + * Note: Switching to D3 state is like a software reset.
21451 + * Switching from D3 to D0 is a hardware reset.
21452 + * We have to save and restore the configuration space.
21454 + for (i = 0; i < PCI_CFG_SIZE; i++) {
21455 + SkPciReadCfgDWord(pAC, i*4, &ConfigSpace[i]);
21458 + /* We know the RAM Interface Arbiter is enabled. */
21459 + SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D3);
21461 + SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);
21463 + if ((PmCtlSts & PCI_PM_STATE_MSK) != PCI_PM_STATE_D3) {
21467 + /* Return to D0 state. */
21468 + SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D0);
21470 + /* Check for D0 state. */
21471 + SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);
21473 + if ((PmCtlSts & PCI_PM_STATE_MSK) != PCI_PM_STATE_D0) {
21477 + /* Check PCI Config Registers. */
21478 + SkPciReadCfgWord(pAC, PCI_COMMAND, &PciCmd);
21479 + SkPciReadCfgByte(pAC, PCI_CACHE_LSZ, &Cls);
21480 + SkPciReadCfgDWord(pAC, PCI_BASE_1ST, &Bp1);
21483 + * Compute the location in PCI config space of BAR2
21484 + * relativ to the location of BAR1
21486 + if ((Bp1 & PCI_MEM_TYP_MSK) == PCI_MEM64BIT) {
21487 + /* BAR1 is 64 bits wide */
21494 + SkPciReadCfgDWord(pAC, PCI_BASE_1ST + i, &Bp2);
21495 + SkPciReadCfgByte(pAC, PCI_LAT_TIM, &Lat);
21497 + if (PciCmd != 0 || Cls != 0 || (Bp1 & 0xfffffff0L) != 0 || Bp2 != 1 ||
21502 + /* Restore PCI Config Space. */
21503 + for (i = 0; i < PCI_CFG_SIZE; i++) {
21504 + SkPciWriteCfgDWord(pAC, i*4, ConfigSpace[i]);
21508 +} /* SkGePciReset */
21509 +#endif /* SK_PCI_RESET */
21513 +/******************************************************************************
21515 + * SkGeSetUpSupFeatures() - Collect Feature List for HW_FEATURE Macro
21518 + * This function collects the available features and required
21519 + * deviation services of the Adapter and provides these
21520 + * information in the GIHwF struct. This information is used as
21521 + * default value and may be overritten by the driver using the
21522 + * SET_HW_FEATURE_MASK() macro in its Init0 phase.
21525 + * Using the On and Off mask: Never switch on the same bit in both
21526 + * masks simultaneously. However, if doing the Off mask will win.
21531 +static void SkGeSetUpSupFeatures(
21532 +SK_AC *pAC, /* Adapter Context */
21533 +SK_IOC IoC) /* I/O Context */
21538 + switch (pAC->GIni.GIChipId) {
21539 + case CHIP_ID_YUKON_EC:
21540 + if (pAC->GIni.GIChipRev == CHIP_REV_YU_EC_A1) {
21542 + pAC->GIni.HwF.Features[HW_DEV_LIST] =
21543 + HWF_WA_DEV_42 | HWF_WA_DEV_46 | HWF_WA_DEV_43_418 |
21544 + HWF_WA_DEV_420 | HWF_WA_DEV_423 |
21545 + HWF_WA_DEV_424 | HWF_WA_DEV_425 | HWF_WA_DEV_427 |
21546 + HWF_WA_DEV_428 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
21547 + HWF_WA_DEV_4152| HWF_WA_DEV_4167;
21551 + pAC->GIni.HwF.Features[HW_DEV_LIST] =
21552 + HWF_WA_DEV_424 | HWF_WA_DEV_425 | HWF_WA_DEV_427 |
21553 + HWF_WA_DEV_428 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
21554 + HWF_WA_DEV_4152| HWF_WA_DEV_4167;
21557 + case CHIP_ID_YUKON_FE:
21558 + pAC->GIni.HwF.Features[HW_DEV_LIST] =
21559 + HWF_WA_DEV_427 | HWF_WA_DEV_4109 |
21560 + HWF_WA_DEV_4152| HWF_WA_DEV_4167;
21562 + case CHIP_ID_YUKON_XL:
21563 + switch (pAC->GIni.GIChipRev) {
21564 + case CHIP_REV_YU_XL_A0: /* still needed for Diag */
21565 + pAC->GIni.HwF.Features[HW_DEV_LIST] =
21566 + HWF_WA_DEV_427 | HWF_WA_DEV_463 | HWF_WA_DEV_472 |
21567 + HWF_WA_DEV_479 | HWF_WA_DEV_483 | HWF_WA_DEV_4115 |
21568 + HWF_WA_DEV_4152| HWF_WA_DEV_4167;
21571 + case CHIP_REV_YU_XL_A1:
21572 + pAC->GIni.HwF.Features[HW_DEV_LIST] =
21573 + HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
21574 + HWF_WA_DEV_4115| HWF_WA_DEV_4152| HWF_WA_DEV_4167;
21577 + case CHIP_REV_YU_XL_A2:
21578 + pAC->GIni.HwF.Features[HW_DEV_LIST] =
21579 + HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
21580 + HWF_WA_DEV_4115 | HWF_WA_DEV_4167;
21583 + case CHIP_REV_YU_XL_A3:
21584 + pAC->GIni.HwF.Features[HW_DEV_LIST] =
21585 + HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
21590 + case CHIP_ID_YUKON_EC_U:
21591 + if (pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A0) {
21592 + pAC->GIni.HwF.Features[HW_DEV_LIST] =
21593 + HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109;
21595 + else if (pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A1) {
21596 + pAC->GIni.HwF.Features[HW_DEV_LIST] =
21597 + HWF_WA_DEV_427 | HWF_WA_DEV_4109 | HWF_WA_DEV_4185;
21599 + /* check for Rev. A1 */
21600 + SK_IN16(IoC, Q_ADDR(Q_XA1, Q_WM), &Word);
21603 + pAC->GIni.HwF.Features[HW_DEV_LIST] |=
21604 + HWF_WA_DEV_4185CS | HWF_WA_DEV_4200;
21610 + for (i = 0; i < 4; i++) {
21611 + pAC->GIni.HwF.Features[i] =
21612 + (pAC->GIni.HwF.Features[i] | pAC->GIni.HwF.OnMask[i]) &
21613 + ~pAC->GIni.HwF.OffMask[i];
21615 +} /* SkGeSetUpSupFeatures */
21616 +#endif /* !SK_SLIM */
21619 /******************************************************************************
21621 @@ -1404,76 +2068,253 @@
21622 * 6: HW self test failed
21624 static int SkGeInit1(
21625 -SK_AC *pAC, /* adapter context */
21626 -SK_IOC IoC) /* IO context */
21627 +SK_AC *pAC, /* Adapter Context */
21628 +SK_IOC IoC) /* I/O Context */
21634 + SK_U32 VauxAvail;
21637 + SK_U32 PowerDownBit;
21638 + SK_BOOL FiberType;
21646 - /* save CLK_RUN bits (YUKON-Lite) */
21647 - SK_IN16(IoC, B0_CTST, &CtrlStat);
21648 + /* save CLK_RUN & ASF_ENABLE bits (YUKON-Lite, YUKON-EC) */
21649 + SK_IN32(IoC, B0_CTST, &CtrlStat);
21651 - /* do the SW-reset */
21652 - SK_OUT8(IoC, B0_CTST, CS_RST_SET);
21653 +#ifdef SK_PCI_RESET
21654 + (void)SkGePciReset(pAC, IoC);
21655 +#endif /* SK_PCI_RESET */
21657 /* release the SW-reset */
21658 + /* Important: SW-reset has to be cleared here, to ensure
21659 + * the CHIP_ID can be read IO-mapped based, too -
21660 + * remember the RAP register can only be written if
21661 + * SW-reset is cleared.
21663 SK_OUT8(IoC, B0_CTST, CS_RST_CLR);
21665 + /* read Chip Identification Number */
21666 + SK_IN8(IoC, B2_CHIP_ID, &Byte);
21667 + pAC->GIni.GIChipId = Byte;
21669 + pAC->GIni.GIAsfEnabled = SK_FALSE;
21671 + /* ASF support only for Yukon-2 */
21672 + if ((pAC->GIni.GIChipId >= CHIP_ID_YUKON_XL) &&
21673 + (pAC->GIni.GIChipId <= CHIP_ID_YUKON_EC)) {
21675 + if ((CtrlStat & Y2_ASF_ENABLE) != 0) {
21676 + /* do the SW-reset only if ASF is not enabled */
21677 + pAC->GIni.GIAsfEnabled = SK_TRUE;
21679 +#else /* !SK_ASF */
21681 + SK_IN8(IoC, B28_Y2_ASF_STAT_CMD, &Byte);
21683 + pAC->GIni.GIAsfRunning = Byte & Y2_ASF_RUNNING;
21685 + /* put ASF system in reset state */
21686 + SK_OUT8(IoC, B28_Y2_ASF_STAT_CMD, (SK_U8)Y2_ASF_RESET);
21688 + /* disable ASF Unit */
21689 + SK_OUT16(IoC, B0_CTST, Y2_ASF_DISABLE);
21690 +#endif /* !SK_ASF */
21693 + if (!pAC->GIni.GIAsfEnabled) {
21694 + /* Yukon-2: required for Diag and Power Management */
21695 + /* set the SW-reset */
21696 + SK_OUT8(IoC, B0_CTST, CS_RST_SET);
21698 + /* release the SW-reset */
21699 + SK_OUT8(IoC, B0_CTST, CS_RST_CLR);
21702 + /* enable Config Write */
21703 + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
21705 /* reset all error bits in the PCI STATUS register */
21707 * Note: PCI Cfg cycles cannot be used, because they are not
21708 * available on some platforms after 'boot time'.
21710 - SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);
21712 - SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
21713 - SK_OUT16(IoC, PCI_C(PCI_STATUS), (SK_U16)(Word | PCI_ERRBITS));
21714 - SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
21715 + SK_IN16(IoC, PCI_C(pAC, PCI_STATUS), &Word);
21717 + SK_OUT16(IoC, PCI_C(pAC, PCI_STATUS), Word | (SK_U16)PCI_ERRBITS);
21719 /* release Master Reset */
21720 SK_OUT8(IoC, B0_CTST, CS_MRST_CLR);
21723 CtrlStat |= CS_CLK_RUN_ENA;
21724 -#endif /* CLK_RUN */
21726 /* restore CLK_RUN bits */
21727 SK_OUT16(IoC, B0_CTST, (SK_U16)(CtrlStat &
21728 (CS_CLK_RUN_HOT | CS_CLK_RUN_RST | CS_CLK_RUN_ENA)));
21729 +#endif /* CLK_RUN */
21731 + if ((pAC->GIni.GIChipId >= CHIP_ID_YUKON_XL) &&
21732 + (pAC->GIni.GIChipId <= CHIP_ID_YUKON_FE)) {
21734 + pAC->GIni.GIYukon2 = SK_TRUE;
21735 + pAC->GIni.GIValIrqMask = Y2_IS_ALL_MSK;
21736 + pAC->GIni.GIValHwIrqMask = Y2_HWE_ALL_MSK;
21738 + VauxAvail = Y2_VAUX_AVAIL;
21740 + SK_IN32(IoC, PCI_C(pAC, PCI_OUR_STATUS), &DWord);
21742 + if ((DWord & PCI_OS_PCI_X) != 0) {
21744 + /* this is a PCI / PCI-X bus */
21745 + if ((DWord & PCI_OS_PCIX) != 0) {
21746 + /* this is a PCI-X bus */
21747 + pAC->GIni.GIPciBus = SK_PCIX_BUS;
21749 + /* PCI-X is always 64-bit wide */
21750 + pAC->GIni.GIPciSlot64 = SK_TRUE;
21752 + pAC->GIni.GIPciMode = (SK_U8)(PCI_OS_SPEED(DWord));
21755 + /* this is a conventional PCI bus */
21756 + pAC->GIni.GIPciBus = SK_PCI_BUS;
21758 + SK_IN16(IoC, PCI_C(pAC, PCI_OUR_REG_2), &Word);
21760 + /* check if 64-bit width is used */
21761 + pAC->GIni.GIPciSlot64 = (SK_BOOL)
21762 + (((DWord & PCI_OS_PCI64B) != 0) &&
21763 + ((Word & PCI_USEDATA64) != 0));
21765 + /* check if 66 MHz PCI Clock is active */
21766 + pAC->GIni.GIPciClock66 = (SK_BOOL)((DWord & PCI_OS_PCI66M) != 0);
21768 +#endif /* !SK_SLIM */
21771 + /* this is a PEX bus */
21772 + pAC->GIni.GIPciBus = SK_PEX_BUS;
21774 + /* clear any PEX errors */
21775 + SK_OUT32(IoC, PCI_C(pAC, PEX_UNC_ERR_STAT), 0xffffffffUL);
21777 + SK_IN32(IoC, PCI_C(pAC, PEX_UNC_ERR_STAT), &DWord);
21779 + if ((DWord & PEX_RX_OV) != 0) {
21780 + /* Dev #4.205 occured */
21781 + pAC->GIni.GIValHwIrqMask &= ~Y2_IS_PCI_EXP;
21782 + pAC->GIni.GIValIrqMask &= ~Y2_IS_HW_ERR;
21785 + SK_IN16(IoC, PCI_C(pAC, PEX_LNK_STAT), &Word);
21787 + pAC->GIni.GIPexWidth = (SK_U8)((Word & PEX_LS_LINK_WI_MSK) >> 4);
21790 + * Yukon-2 chips family has a different way of providing
21791 + * the number of MACs available
21793 + pAC->GIni.GIMacsFound = 1;
21795 + /* get HW Resources */
21796 + SK_IN8(IoC, B2_Y2_HW_RES, &Byte);
21798 + if (CHIP_ID_YUKON_2(pAC)) {
21800 + * OEM config value is overwritten and should not
21801 + * be used for Yukon-2
21803 + pAC->GIni.GILedBlinkCtrl |= SK_ACT_LED_BLINK;
21806 + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) {
21807 + /* LED Configuration is stored in GPIO */
21808 + SK_IN8(IoC, B2_GP_IO, &Byte);
21810 + if (CFG_LED_MODE(Byte) == CFG_LED_LINK_MUX_P60) {
21812 + pAC->GIni.GILedBlinkCtrl |= SK_LED_LINK_MUX_P60;
21815 +#endif /* !SK_SLIM */
21817 + if (CFG_LED_MODE(Byte) == CFG_LED_DUAL_ACT_LNK) {
21819 + pAC->GIni.GILedBlinkCtrl |= SK_DUAL_LED_ACT_LNK;
21823 + /* save HW Resources / Application Information */
21824 + pAC->GIni.GIHwResInfo = Byte;
21826 + if ((Byte & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
21828 + SK_IN8(IoC, B2_Y2_CLK_GATE, &Byte);
21830 + if (!(Byte & Y2_STATUS_LNK2_INAC)) {
21831 + /* Link 2 activ */
21832 + pAC->GIni.GIMacsFound++;
21837 + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL) {
21838 + /* temporary WA for reported number of links */
21839 + pAC->GIni.GIMacsFound = 2;
21843 + /* read Chip Revision */
21844 + SK_IN8(IoC, B2_MAC_CFG, &Byte);
21846 + pAC->GIni.GIChipCap = Byte & 0x0f;
21849 + pAC->GIni.GIYukon2 = SK_FALSE;
21850 + pAC->GIni.GIValIrqMask = IS_ALL_MSK;
21851 + pAC->GIni.GIValHwIrqMask = 0; /* not activated */
21853 + VauxAvail = CS_VAUX_AVAIL;
21855 + /* read number of MACs and Chip Revision */
21856 + SK_IN8(IoC, B2_MAC_CFG, &Byte);
21858 + pAC->GIni.GIMacsFound = (Byte & CFG_SNG_MAC) ? 1 : 2;
21861 - /* read Chip Identification Number */
21862 - SK_IN8(IoC, B2_CHIP_ID, &Byte);
21863 - pAC->GIni.GIChipId = Byte;
21865 - /* read number of MACs */
21866 - SK_IN8(IoC, B2_MAC_CFG, &Byte);
21867 - pAC->GIni.GIMacsFound = (Byte & CFG_SNG_MAC) ? 1 : 2;
21869 /* get Chip Revision Number */
21870 pAC->GIni.GIChipRev = (SK_U8)((Byte & CFG_CHIP_R_MSK) >> 4);
21872 - /* get diff. PCI parameters */
21873 - SK_IN16(IoC, B0_CTST, &CtrlStat);
21876 + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL &&
21877 + pAC->GIni.GIChipRev == CHIP_REV_YU_XL_A0) {
21878 + /* Yukon-2 Chip Rev. A0 */
21881 +#endif /* !SK_DIAG */
21883 /* read the adapters RAM size */
21884 SK_IN8(IoC, B2_E_0, &Byte);
21887 pAC->GIni.GIGenesis = SK_FALSE;
21888 pAC->GIni.GIYukon = SK_FALSE;
21889 pAC->GIni.GIYukonLite = SK_FALSE;
21890 + pAC->GIni.GIVauxAvail = SK_FALSE;
21893 if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
21895 pAC->GIni.GIGenesis = SK_TRUE;
21897 - if (Byte == (SK_U8)3) {
21898 + if (Byte == (SK_U8)3) {
21899 /* special case: 4 x 64k x 36, offset = 0x80000 */
21900 pAC->GIni.GIRamSize = 1024;
21901 pAC->GIni.GIRamOffs = (SK_U32)512 * 1024;
21902 @@ -1482,57 +2323,83 @@
21903 pAC->GIni.GIRamSize = (int)Byte * 512;
21904 pAC->GIni.GIRamOffs = 0;
21906 - /* all GE adapters work with 53.125 MHz host clock */
21907 + /* all GENESIS adapters work with 53.125 MHz host clock */
21908 pAC->GIni.GIHstClkFact = SK_FACT_53;
21911 /* set Descr. Poll Timer Init Value to 250 ms */
21912 pAC->GIni.GIPollTimerVal =
21913 SK_DPOLL_DEF * (SK_U32)pAC->GIni.GIHstClkFact / 100;
21915 #endif /* GENESIS */
21919 if (pAC->GIni.GIChipId != CHIP_ID_GENESIS) {
21922 pAC->GIni.GIYukon = SK_TRUE;
21925 pAC->GIni.GIRamSize = (Byte == (SK_U8)0) ? 128 : (int)Byte * 4;
21929 pAC->GIni.GIRamOffs = 0;
21931 - /* WA for chip Rev. A */
21933 + /* WA for Yukon chip Rev. A */
21934 pAC->GIni.GIWolOffs = (pAC->GIni.GIChipId == CHIP_ID_YUKON &&
21935 pAC->GIni.GIChipRev == 0) ? WOL_REG_OFFS : 0;
21938 /* get PM Capabilities of PCI config space */
21939 - SK_IN16(IoC, PCI_C(PCI_PM_CAP_REG), &Word);
21940 + SK_IN16(IoC, PCI_C(pAC, PCI_PM_CAP_REG), &Word);
21942 /* check if VAUX is available */
21943 - if (((CtrlStat & CS_VAUX_AVAIL) != 0) &&
21944 + if (((CtrlStat & VauxAvail) != 0) &&
21945 /* check also if PME from D3cold is set */
21946 ((Word & PCI_PME_D3C_SUP) != 0)) {
21947 /* set entry in GE init struct */
21948 pAC->GIni.GIVauxAvail = SK_TRUE;
21951 - if (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) {
21952 - /* this is Rev. A1 */
21953 - pAC->GIni.GIYukonLite = SK_TRUE;
21956 - /* save Flash-Address Register */
21957 - SK_IN32(IoC, B2_FAR, &DWord);
21958 +#endif /* !SK_SLIM */
21960 - /* test Flash-Address Register */
21961 - SK_OUT8(IoC, B2_FAR + 3, 0xff);
21962 - SK_IN8(IoC, B2_FAR + 3, &Byte);
21963 + if (!CHIP_ID_YUKON_2(pAC)) {
21966 - /* this is Rev. A0 */
21967 + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) {
21968 + /* this is Rev. A1 */
21969 pAC->GIni.GIYukonLite = SK_TRUE;
21973 + /* save Flash-Address Register */
21974 + SK_IN32(IoC, B2_FAR, &DWord);
21976 + /* test Flash-Address Register */
21977 + SK_OUT8(IoC, B2_FAR + 3, 0xff);
21978 + SK_IN8(IoC, B2_FAR + 3, &Byte);
21981 + /* this is Rev. A0 */
21982 + pAC->GIni.GIYukonLite = SK_TRUE;
21984 + /* restore Flash-Address Register */
21985 + SK_OUT32(IoC, B2_FAR, DWord);
21988 +#endif /* !SK_SLIM */
21991 + /* Check for CLS = 0 (dev. #4.55) */
21992 + if (pAC->GIni.GIPciBus != SK_PEX_BUS) {
21993 + /* PCI and PCI-X */
21994 + SK_IN8(IoC, PCI_C(pAC, PCI_CACHE_LSZ), &Byte);
21997 + /* set CLS to 2 if configured to 0 */
21998 + SK_OUT8(IoC, PCI_C(pAC, PCI_CACHE_LSZ), 2);
22001 - /* restore Flash-Address Register */
22002 - SK_OUT32(IoC, B2_FAR, DWord);
22003 + if (pAC->GIni.GIPciBus == SK_PCIX_BUS) {
22004 + /* set Cache Line Size opt. */
22005 + SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_1), &DWord);
22006 + DWord |= PCI_CLS_OPT;
22007 + SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_1), DWord);
22012 @@ -1540,138 +2407,282 @@
22013 SK_OUT8(IoC, B0_POWER_CTRL, (SK_U8)(PC_VAUX_ENA | PC_VCC_ENA |
22014 PC_VAUX_OFF | PC_VCC_ON));
22016 - /* read the Interrupt source */
22017 - SK_IN32(IoC, B0_ISRC, &DWord);
22019 - if ((DWord & IS_HW_ERR) != 0) {
22020 - /* read the HW Error Interrupt source */
22021 - SK_IN32(IoC, B0_HWE_ISRC, &DWord);
22023 - if ((DWord & IS_IRQ_SENSOR) != 0) {
22024 - /* disable HW Error IRQ */
22025 - pAC->GIni.GIValIrqMask &= ~IS_HW_ERR;
22028 + if (CHIP_ID_YUKON_2(pAC)) {
22029 + switch (pAC->GIni.GIChipId) {
22030 + /* PEX adapters work with different host clock */
22031 + case CHIP_ID_YUKON_EC:
22032 + case CHIP_ID_YUKON_EC_U:
22033 + /* Yukon-EC works with 125 MHz host clock */
22034 + pAC->GIni.GIHstClkFact = SK_FACT_125;
22036 + case CHIP_ID_YUKON_FE:
22037 + /* Yukon-FE works with 100 MHz host clock */
22038 + pAC->GIni.GIHstClkFact = SK_FACT_100;
22040 + case CHIP_ID_YUKON_XL:
22041 + /* all Yukon-2 adapters work with 156 MHz host clock */
22042 + pAC->GIni.GIHstClkFact = 2 * SK_FACT_78;
22044 + if (pAC->GIni.GIChipRev > CHIP_REV_YU_XL_A1) {
22045 + /* enable bits are inverted */
22046 + Byte = (SK_U8)(Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
22047 + Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
22048 + Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
22052 + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E006,
22053 + SKERR_HWI_E006MSG);
22056 + pAC->GIni.GIPollTimerVal =
22057 + SK_DPOLL_DEF_Y2 * (SK_U32)pAC->GIni.GIHstClkFact / 100;
22059 + /* set power down bit */
22060 + PowerDownBit = PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD;
22062 + /* disable Core Clock Division, set Clock Select to 0 (Yukon-2) */
22063 + SK_OUT32(IoC, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
22065 + /* enable MAC/PHY, PCI and Core Clock for both Links */
22066 + SK_OUT8(IoC, B2_Y2_CLK_GATE, Byte);
22069 - for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
22070 - /* set GMAC Link Control reset */
22071 - SK_OUT16(IoC, MR_ADDR(i, GMAC_LINK_CTRL), GMLC_RST_SET);
22073 + /* YUKON adapters work with 78 MHz host clock */
22074 + pAC->GIni.GIHstClkFact = SK_FACT_78;
22076 - /* clear GMAC Link Control reset */
22077 - SK_OUT16(IoC, MR_ADDR(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
22078 + pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX; /* 215 ms */
22080 + /* read the Interrupt source */
22081 + SK_IN32(IoC, B0_ISRC, &DWord);
22083 + if ((DWord & IS_HW_ERR) != 0) {
22084 + /* read the HW Error Interrupt source */
22085 + SK_IN32(IoC, B0_HWE_ISRC, &DWord);
22087 + if ((DWord & IS_IRQ_SENSOR) != 0) {
22088 + /* disable HW Error IRQ */
22089 + pAC->GIni.GIValIrqMask &= ~IS_HW_ERR;
22092 + /* set power down bit */
22093 + PowerDownBit = PCI_PHY_COMA;
22096 + SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_1), &Our1);
22098 + Our1 &= ~PowerDownBit;
22100 + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL &&
22101 + pAC->GIni.GIChipRev > CHIP_REV_YU_XL_A1) {
22102 + /* deassert Low Power for 1st PHY */
22103 + Our1 |= PCI_Y2_PHY1_COMA;
22105 + if (pAC->GIni.GIMacsFound > 1) {
22106 + /* deassert Low Power for 2nd PHY */
22107 + Our1 |= PCI_Y2_PHY2_COMA;
22110 + else if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) {
22111 + /* enable HW WOL */
22112 + SK_OUT16(IoC, B0_CTST, (SK_U16)Y2_HW_WOL_ON);
22114 + /* enable all clocks */
22115 + SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_3), 0);
22117 + SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_4), &DWord);
22119 + DWord &= P_ASPM_CONTROL_MSK;
22120 + /* set all bits to 0 except bits 15..12 */
22121 + SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_4), DWord);
22123 + /* set to default value */
22124 + SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_5), 0);
22127 + /* release PHY from PowerDown/COMA Mode */
22128 + SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_1), Our1);
22130 + if (!pAC->GIni.GIAsfEnabled) {
22132 + for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
22133 + /* set Link Control reset */
22134 + SK_OUT8(IoC, MR_ADDR(i, GMAC_LINK_CTRL), (SK_U8)GMLC_RST_SET);
22136 + /* clear Link Control reset */
22137 + SK_OUT8(IoC, MR_ADDR(i, GMAC_LINK_CTRL), (SK_U8)GMLC_RST_CLR);
22140 - /* all YU chips work with 78.125 MHz host clock */
22141 - pAC->GIni.GIHstClkFact = SK_FACT_78;
22143 - pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX; /* 215 ms */
22147 - /* check if 64-bit PCI Slot is present */
22148 - pAC->GIni.GIPciSlot64 = (SK_BOOL)((CtrlStat & CS_BUS_SLOT_SZ) != 0);
22150 - /* check if 66 MHz PCI Clock is active */
22151 - pAC->GIni.GIPciClock66 = (SK_BOOL)((CtrlStat & CS_BUS_CLOCK) != 0);
22152 + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
22155 + if (!CHIP_ID_YUKON_2(pAC)) {
22156 + /* this is a conventional PCI bus */
22157 + pAC->GIni.GIPciBus = SK_PCI_BUS;
22159 + /* check if 64-bit PCI Slot is present */
22160 + pAC->GIni.GIPciSlot64 = (SK_BOOL)((CtrlStat & CS_BUS_SLOT_SZ) != 0);
22162 + /* check if 66 MHz PCI Clock is active */
22163 + pAC->GIni.GIPciClock66 = (SK_BOOL)((CtrlStat & CS_BUS_CLOCK) != 0);
22166 /* read PCI HW Revision Id. */
22167 - SK_IN8(IoC, PCI_C(PCI_REV_ID), &Byte);
22168 + SK_IN8(IoC, PCI_C(pAC, PCI_REV_ID), &Byte);
22169 pAC->GIni.GIPciHwRev = Byte;
22171 + /* read connector type */
22172 + SK_IN8(IoC, B2_CONN_TYP, &pAC->GIni.GIConTyp);
22173 +#endif /* !SK_SLIM */
22175 /* read the PMD type */
22176 SK_IN8(IoC, B2_PMD_TYP, &Byte);
22177 - pAC->GIni.GICopperType = (SK_U8)(Byte == 'T');
22179 - /* read the PHY type */
22180 + pAC->GIni.GIPmdTyp = Byte;
22182 + FiberType = (Byte == 'L' || Byte == 'S' || Byte == 'P');
22184 + pAC->GIni.GICopperType = (SK_BOOL)(Byte == 'T' || Byte == '1' ||
22185 + (pAC->GIni.GIYukon2 && !FiberType));
22187 + /* read the PHY type (Yukon and Genesis) */
22188 SK_IN8(IoC, B2_E_1, &Byte);
22190 Byte &= 0x0f; /* the PHY type is stored in the lower nibble */
22191 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
22194 + pPrt = &pAC->GIni.GP[i];
22196 + /* get the MAC addresses */
22197 + for (j = 0; j < 3; j++) {
22198 + SK_IN16(IoC, B2_MAC_1 + i * 8 + j * 2, &pPrt->PMacAddr[j]);
22202 if (pAC->GIni.GIGenesis) {
22205 - pAC->GIni.GP[i].PhyAddr = PHY_ADDR_XMAC;
22206 + pPrt->PhyAddr = PHY_ADDR_XMAC;
22209 - pAC->GIni.GP[i].PhyAddr = PHY_ADDR_BCOM;
22210 - pAC->GIni.GP[i].PMSCap = (SK_U8)(SK_MS_CAP_AUTO |
22211 + pPrt->PhyAddr = PHY_ADDR_BCOM;
22212 + pPrt->PMSCap = (SK_U8)(SK_MS_CAP_AUTO |
22213 SK_MS_CAP_MASTER | SK_MS_CAP_SLAVE);
22217 - pAC->GIni.GP[i].PhyAddr = PHY_ADDR_LONE;
22218 + pPrt->PhyAddr = PHY_ADDR_LONE;
22221 - pAC->GIni.GP[i].PhyAddr = PHY_ADDR_NAT;
22222 + pPrt->PhyAddr = PHY_ADDR_NAT;
22224 #endif /* OTHER_PHY */
22226 /* ERROR: unexpected PHY type detected */
22231 #endif /* GENESIS */
22235 if (pAC->GIni.GIYukon) {
22237 - if (Byte < (SK_U8)SK_PHY_MARV_COPPER) {
22239 + if (((Byte < (SK_U8)SK_PHY_MARV_COPPER) || pAC->GIni.GIYukon2) &&
22241 /* if this field is not initialized */
22242 Byte = (SK_U8)SK_PHY_MARV_COPPER;
22245 pAC->GIni.GICopperType = SK_TRUE;
22248 - pAC->GIni.GP[i].PhyAddr = PHY_ADDR_MARV;
22251 + pPrt->PhyAddr = PHY_ADDR_MARV;
22253 if (pAC->GIni.GICopperType) {
22255 - pAC->GIni.GP[i].PLinkSpeedCap = (SK_U8)(SK_LSPEED_CAP_AUTO |
22256 - SK_LSPEED_CAP_10MBPS | SK_LSPEED_CAP_100MBPS |
22257 - SK_LSPEED_CAP_1000MBPS);
22259 - pAC->GIni.GP[i].PLinkSpeed = (SK_U8)SK_LSPEED_AUTO;
22261 - pAC->GIni.GP[i].PMSCap = (SK_U8)(SK_MS_CAP_AUTO |
22262 + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE ||
22263 + (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC &&
22264 + pAC->GIni.GIChipCap == 2)) {
22266 + pPrt->PLinkSpeedCap = (SK_U8)(SK_LSPEED_CAP_100MBPS |
22267 + SK_LSPEED_CAP_10MBPS);
22269 + pAC->GIni.GIRamSize = 4;
22272 + pPrt->PLinkSpeedCap = (SK_U8)(SK_LSPEED_CAP_1000MBPS |
22273 + SK_LSPEED_CAP_100MBPS | SK_LSPEED_CAP_10MBPS |
22274 + SK_LSPEED_CAP_AUTO);
22277 + pPrt->PLinkSpeed = (SK_U8)SK_LSPEED_AUTO;
22279 + pPrt->PMSCap = (SK_U8)(SK_MS_CAP_AUTO |
22280 SK_MS_CAP_MASTER | SK_MS_CAP_SLAVE);
22283 Byte = (SK_U8)SK_PHY_MARV_FIBER;
22287 + /* clear TWSI IRQ */
22288 + SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
22292 - pAC->GIni.GP[i].PhyType = (int)Byte;
22295 + pPrt->PhyType = (int)Byte;
22297 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
22298 - ("PHY type: %d PHY addr: %04x\n", Byte,
22299 - pAC->GIni.GP[i].PhyAddr));
22300 + ("PHY type: %d PHY addr: %04x\n",
22301 + Byte, pPrt->PhyAddr));
22305 /* get MAC Type & set function pointers dependent on */
22307 if (pAC->GIni.GIGenesis) {
22310 pAC->GIni.GIMacType = SK_MAC_XMAC;
22312 pAC->GIni.GIFunc.pFnMacUpdateStats = SkXmUpdateStats;
22313 pAC->GIni.GIFunc.pFnMacStatistic = SkXmMacStatistic;
22314 pAC->GIni.GIFunc.pFnMacResetCounter = SkXmResetCounter;
22315 pAC->GIni.GIFunc.pFnMacOverflow = SkXmOverflowStatus;
22317 + pAC->GIni.GIFunc.pFnMacPhyRead = SkXmPhyRead;
22318 + pAC->GIni.GIFunc.pFnMacPhyWrite = SkXmPhyWrite;
22319 +#else /* SK_DIAG */
22320 + pAC->GIni.GIFunc.pSkGeSirqIsr = SkGeYuSirqIsr;
22321 +#endif /* !SK_DIAG */
22323 #endif /* GENESIS */
22327 if (pAC->GIni.GIYukon) {
22331 pAC->GIni.GIMacType = SK_MAC_GMAC;
22333 pAC->GIni.GIFunc.pFnMacUpdateStats = SkGmUpdateStats;
22334 pAC->GIni.GIFunc.pFnMacStatistic = SkGmMacStatistic;
22335 pAC->GIni.GIFunc.pFnMacResetCounter = SkGmResetCounter;
22336 pAC->GIni.GIFunc.pFnMacOverflow = SkGmOverflowStatus;
22337 +#endif /* !SK_SLIM */
22340 + pAC->GIni.GIFunc.pFnMacPhyRead = SkGmPhyRead;
22341 + pAC->GIni.GIFunc.pFnMacPhyWrite = SkGmPhyWrite;
22342 +#else /* SK_DIAG */
22343 + if (CHIP_ID_YUKON_2(pAC)) {
22344 + pAC->GIni.GIFunc.pSkGeSirqIsr = SkYuk2SirqIsr;
22347 + pAC->GIni.GIFunc.pSkGeSirqIsr = SkGeYuSirqIsr;
22349 +#endif /* !SK_DIAG */
22351 #ifdef SPECIAL_HANDLING
22352 if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {
22353 @@ -1684,7 +2695,13 @@
22361 + SkGeSetUpSupFeatures(pAC, IoC);
22363 +#endif /* !SK_SLIM */
22368 @@ -1705,9 +2722,15 @@
22371 static void SkGeInit2(
22372 -SK_AC *pAC, /* adapter context */
22373 -SK_IOC IoC) /* IO context */
22374 +SK_AC *pAC, /* Adapter Context */
22375 +SK_IOC IoC) /* I/O Context */
22379 +#if (!defined(SK_SLIM) && !defined(SK_DIAG))
22381 +#endif /* !SK_SLIM && !SK_DIAG */
22382 +#endif /* YUKON */
22385 #endif /* GENESIS */
22386 @@ -1720,7 +2743,9 @@
22388 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E017, SKERR_HWI_E017MSG);
22391 SK_OUT32(IoC, B28_DPT_INI, pAC->GIni.GIPollTimerVal);
22393 SK_OUT8(IoC, B28_DPT_CTRL, DPT_START);
22396 @@ -1730,6 +2755,7 @@
22397 DWord = SK_BLK_DUR * (SK_U32)pAC->GIni.GIHstClkFact / 100;
22399 SK_OUT32(IoC, B2_BSC_INI, DWord);
22401 SK_OUT8(IoC, B2_BSC_CTRL, BSC_START);
22404 @@ -1741,13 +2767,13 @@
22405 SkGeInitPktArb(pAC, IoC);
22407 #endif /* GENESIS */
22412 if (pAC->GIni.GIYukon) {
22413 /* start Time Stamp Timer */
22414 SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8)GMT_ST_START);
22416 -#endif /* YUKON */
22417 +#endif /* SK_DIAG */
22419 /* enable the Tx Arbiters */
22420 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
22421 @@ -1757,8 +2783,62 @@
22422 /* enable the RAM Interface Arbiter */
22423 SkGeInitRamIface(pAC, IoC);
22426 + if (CHIP_ID_YUKON_2(pAC)) {
22428 + if (pAC->GIni.GIPciBus == SK_PEX_BUS) {
22430 + SK_IN16(IoC, PCI_C(pAC, PEX_DEV_CTRL), &Word);
22432 + /* change Max. Read Request Size to 2048 bytes */
22433 + Word &= ~PEX_DC_MAX_RRS_MSK;
22434 + Word |= PEX_DC_MAX_RD_RQ_SIZE(4);
22436 + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
22438 + SK_OUT16(IoC, PCI_C(pAC, PEX_DEV_CTRL), Word);
22440 +#ifdef REPLAY_TIMER
22441 + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) {
22442 + /* PEX Ack Reply Timeout to 40 us */
22443 + SK_OUT16(IoC, PCI_C(pAC, PEX_ACK_RPLY_TOX1), 0x2710);
22447 + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
22449 +#if (!defined(SK_SLIM) && !defined(SK_DIAG))
22450 + SK_IN16(IoC, PCI_C(pAC, PEX_LNK_CAP), &Word);
22452 + Word = (Word & PEX_CAP_MAX_WI_MSK) >> 4;
22454 + /* compare PEX Negotiated Link Width against max. capabil */
22455 + if (pAC->GIni.GIPexWidth != (SK_U8)Word) {
22457 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
22458 + ("PEX negotiated Link width is: %d, exp.: %d\n",
22459 + pAC->GIni.GIPexWidth, Word));
22461 +#ifndef NDIS_MINIPORT_DRIVER
22462 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E026,
22463 + SKERR_HWI_E026MSG);
22466 + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PEX_LINK_WIDTH, Para);
22468 +#endif /* !SK_SLIM && !SK_DIAG */
22472 + * Writing the HW Error Mask Reg. will not generate an IRQ
22473 + * as long as the B0_IMSK is not set by the driver.
22475 + SK_OUT32(IoC, B0_HWE_IMSK, pAC->GIni.GIValHwIrqMask);
22477 +#endif /* YUKON */
22481 /******************************************************************************
22483 * SkGeInit() - Initialize the GE Adapter with the specified level.
22484 @@ -1780,7 +2860,7 @@
22485 * if Number of MACs > SK_MAX_MACS
22487 * After returning from Level 0 the adapter
22488 - * may be accessed with IO operations.
22489 + * may be accessed with I/O operations.
22491 * Level 2: start the Blink Source Counter
22493 @@ -1789,14 +2869,14 @@
22494 * 1: Number of MACs exceeds SK_MAX_MACS (after level 1)
22495 * 2: Adapter not present or not accessible
22496 * 3: Illegal initialization level
22497 - * 4: Initialization Level 1 Call missing
22498 + * 4: Initialization level 1 call missing
22499 * 5: Unexpected PHY type detected
22500 * 6: HW self test failed
22503 -SK_AC *pAC, /* adapter context */
22504 -SK_IOC IoC, /* IO context */
22505 -int Level) /* initialization level */
22506 +SK_AC *pAC, /* Adapter Context */
22507 +SK_IOC IoC, /* I/O Context */
22508 +int Level) /* Initialization Level */
22510 int RetVal; /* return value */
22512 @@ -1811,7 +2891,7 @@
22513 SkGeInit0(pAC, IoC);
22514 pAC->GIni.GILevel = SK_INIT_DATA;
22519 /* Initialization Level 1 */
22520 RetVal = SkGeInit1(pAC, IoC);
22521 @@ -1823,22 +2903,24 @@
22522 SK_OUT32(IoC, B2_IRQM_INI, SK_TEST_VAL);
22523 SK_IN32(IoC, B2_IRQM_INI, &DWord);
22524 SK_OUT32(IoC, B2_IRQM_INI, 0L);
22527 if (DWord != SK_TEST_VAL) {
22533 /* check if the number of GIMacsFound matches SK_MAX_MACS */
22534 if (pAC->GIni.GIMacsFound > SK_MAX_MACS) {
22538 +#endif /* DEBUG */
22540 /* Level 1 successfully passed */
22541 pAC->GIni.GILevel = SK_INIT_IO;
22546 /* Initialization Level 2 */
22547 if (pAC->GIni.GILevel != SK_INIT_IO) {
22548 @@ -1848,12 +2930,13 @@
22553 SkGeInit2(pAC, IoC);
22555 /* Level 2 successfully passed */
22556 pAC->GIni.GILevel = SK_INIT_RUN;
22561 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E003, SKERR_HWI_E003MSG);
22563 @@ -1876,40 +2959,88 @@
22567 -SK_AC *pAC, /* adapter context */
22568 -SK_IOC IoC) /* IO context */
22569 +SK_AC *pAC, /* Adapter Context */
22570 +SK_IOC IoC) /* I/O Context */
22575 +#ifdef SK_PHY_LP_MODE_DEEP_SLEEP
22579 #if (!defined(SK_SLIM) && !defined(VCPU))
22580 /* ensure I2C is ready */
22581 SkI2cWaitIrq(pAC, IoC);
22585 - /* stop all current transfer activity */
22586 - for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
22587 - if (pAC->GIni.GP[i].PState != SK_PRT_STOP &&
22588 - pAC->GIni.GP[i].PState != SK_PRT_RESET) {
22589 +#ifdef SK_PHY_LP_MODE_DEEP_SLEEP
22591 + * for power saving purposes within mobile environments
22592 + * we set the PHY to coma mode.
22595 + if (pAC->GIni.GIVauxAvail) {
22596 + /* switch power to VAUX */
22597 + SK_OUT8(IoC, B0_POWER_CTRL, (SK_U8)(PC_VAUX_ENA | PC_VCC_ENA |
22598 + PC_VAUX_ON | PC_VCC_OFF));
22602 + if (CHIP_ID_YUKON_2(pAC) && !pAC->GIni.GIAsfEnabled
22604 + || (pAC->GIni.GIYukonLite && pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3)
22608 + /* flag for SkGmEnterLowPowerMode() that the call was from here */
22609 + pAC->GIni.GILevel = SK_INIT_IO;
22611 + /* for all ports switch PHY to coma mode */
22612 + for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
22614 + /* Reset Rx MAC FIFO */
22615 + SK_OUT8(IoC, MR_ADDR(i, RX_GMF_CTRL_T), (SK_U8)GMF_RST_SET);
22617 - SkGeStopPort(pAC, IoC, i, SK_STOP_ALL, SK_HARD_RST);
22618 + (void)SkGmEnterLowPowerMode(pAC, IoC, i, PHY_PM_DEEP_SLEEP);
22621 + else if (pAC->GIni.GIYukonLite) {
22622 + /* switch PHY to IEEE Power Down mode */
22623 + (void)SkGmEnterLowPowerMode(pAC, IoC, 0, PHY_PM_IEEE_POWER_DOWN);
22625 +#else /* !SK_PHY_LP_MODE_DEEP_SLEEP */
22627 + if (!pAC->GIni.GIAsfEnabled) {
22628 + /* stop all current transfer activity */
22629 + for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
22630 + if (pAC->GIni.GP[i].PState != SK_PRT_STOP &&
22631 + pAC->GIni.GP[i].PState != SK_PRT_RESET) {
22633 + SkGeStopPort(pAC, IoC, i, SK_STOP_ALL, SK_HARD_RST);
22638 - /* Reset all bits in the PCI STATUS register */
22639 + /* reset all bits in the PCI STATUS register */
22641 * Note: PCI Cfg cycles cannot be used, because they are not
22642 * available on some platforms after 'boot time'.
22644 - SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);
22646 + SK_IN16(IoC, PCI_C(pAC, PCI_STATUS), &Word);
22648 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
22649 - SK_OUT16(IoC, PCI_C(PCI_STATUS), (SK_U16)(Word | PCI_ERRBITS));
22651 + SK_OUT16(IoC, PCI_C(pAC, PCI_STATUS), Word | (SK_U16)PCI_ERRBITS);
22653 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
22655 - /* do the reset, all LEDs are switched off now */
22656 - SK_OUT8(IoC, B0_CTST, CS_RST_SET);
22658 + if (!pAC->GIni.GIAsfEnabled) {
22659 + /* set the SW-reset */
22660 + SK_OUT8(IoC, B0_CTST, CS_RST_SET);
22662 +#endif /* !SK_PHY_LP_MODE_DEEP_SLEEP */
22664 pAC->GIni.GILevel = SK_INIT_DATA;
22667 @@ -1943,8 +3074,8 @@
22668 * 2: The port has to be stopped before it can be initialized again.
22671 -SK_AC *pAC, /* adapter context */
22672 -SK_IOC IoC, /* IO context */
22673 +SK_AC *pAC, /* Adapter Context */
22674 +SK_IOC IoC, /* I/O Context */
22675 int Port) /* Port to configure */
22678 @@ -1955,8 +3086,8 @@
22679 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E004, SKERR_HWI_E004MSG);
22683 - if (pPrt->PState == SK_PRT_INIT || pPrt->PState == SK_PRT_RUN) {
22685 + if (pPrt->PState >= SK_PRT_INIT) {
22686 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E005, SKERR_HWI_E005MSG);
22689 @@ -1967,35 +3098,35 @@
22690 if (pAC->GIni.GIGenesis) {
22691 /* initialize Rx, Tx and Link LED */
22693 - * If 1000BT Phy needs LED initialization than swap
22694 + * If 1000BT PHY needs LED initialization than swap
22695 * LED and XMAC initialization order
22697 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_ENA);
22698 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, RX_LED_INI), SK_LED_ENA);
22699 /* The Link LED is initialized by RLMT or Diagnostics itself */
22702 SkXmInitMac(pAC, IoC, Port);
22704 #endif /* GENESIS */
22708 if (pAC->GIni.GIYukon) {
22710 SkGmInitMac(pAC, IoC, Port);
22715 /* do NOT initialize the Link Sync Counter */
22717 SkGeInitMacFifo(pAC, IoC, Port);
22720 SkGeInitRamBufs(pAC, IoC, Port);
22723 if (pPrt->PXSQSize != 0) {
22724 /* enable Force Sync bit if synchronous queue available */
22725 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_ENA_FSYNC);
22729 SkGeInitBmu(pAC, IoC, Port);
22731 /* mark port as initialized */
22732 @@ -2003,3 +3134,219 @@
22735 } /* SkGeInitPort */
22738 +#if (defined(YUK2) && !defined(SK_SLIM))
22739 +/******************************************************************************
22741 + * SkGeRamWrite() - Writes One quadword to RAM
22746 +static void SkGeRamWrite(
22747 +SK_AC *pAC, /* Adapter Context */
22748 +SK_IOC IoC, /* I/O Context */
22749 +SK_U32 Addr, /* Address to be written to (in quadwords) */
22750 +SK_U32 LowDword, /* Lower Dword to be written */
22751 +SK_U32 HighDword, /* Upper Dword to be written */
22752 +int Port) /* Select RAM buffer (Yukon-2 has 2 RAM buffers) */
22754 + SK_OUT32(IoC, SELECT_RAM_BUFFER(Port, B3_RAM_ADDR), Addr);
22756 + /* Write Access is initiated by writing the upper Dword */
22757 + SK_OUT32(IoC, SELECT_RAM_BUFFER(Port, B3_RAM_DATA_LO), LowDword);
22759 + SK_OUT32(IoC, SELECT_RAM_BUFFER(Port, B3_RAM_DATA_HI), HighDword);
22762 +/******************************************************************************
22764 + * SkYuk2RestartRxBmu() - Restart Receive BMU on Yukon-2
22770 +int SkYuk2RestartRxBmu(
22771 +SK_AC *pAC, /* Adapter Context */
22772 +SK_IOC IoC, /* I/O Context */
22773 +int Port) /* Port Index (MAC_1 + n) */
22778 + SK_U16 FlushMask;
22779 + SK_U16 FlushTrsh;
22781 + SK_U32 StartTime;
22785 + SK_GEPORT *pPrt; /* GIni Port struct pointer */
22786 + SK_U16 WordBuffer[4]; /* Buffer to handle MAC address */
22792 + pPrt = &pAC->GIni.GP[Port];
22795 + 1. save Rx MAC FIFO Flush Mask and Rx MAC FIFO Flush Threshold
22796 + 2. save GMAC Rx Control Register
22797 + 3. re-initialize MAC Rx FIFO, Rx RAM Buffer Queue, PCI Rx FIFO,
22798 + Rx BMU and Rx Prefetch Unit of the link.
22799 + 4. set Rx MAC FIFO Flush Mask to 0xffff
22800 + set Rx MAC FIFO Flush Threshold to a high value, e.g. 0x20
22801 + 5. set GMAC to loopback mode and switch GMAC back to Rx/Tx enable
22802 + 6. clear Rx/Tx Frame Complete IRQ in Rx/T MAC FIFO Control Register
22803 + 7. send one packet with a size of 64bytes (size below flush threshold)
22804 + from TXA RAM Buffer Queue to set the rx_sop flop:
22805 + - set TxAQ Write Pointer to (packet size in qwords + 2)
22806 + - set TxAQ Level to (packet size in qwords + 2)
22807 + - write Internal Status Word 1 and 2 to TxAQ RAM Buffer Queue QWord 0,1
22808 + according to figure 61 on page 330 of Yukon-2 Spec.
22809 + - write MAC header with Destination Address = own MAC address to
22810 + TxAQ RAM Buffer Queue QWords 2 and 3
22811 + - set TxAQ Packet Counter to 1 -> packet is transmitted immediately
22812 + 8. poll GMAC IRQ Source Register for IRQ Rx/Tx Frame Complete
22813 + 9. restore GMAC Rx Control Register
22814 +10. restore Rx MAC FIFO Flush Mask and Rx MAC FIFO Flush Threshold
22815 +11. set GMAC back to GMII mode
22818 + /* save Rx GMAC FIFO Flush Mask */
22819 + SK_IN16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), &FlushMask);
22821 + /* save Rx GMAC FIFO Flush Threshold */
22822 + SK_IN16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), &FlushTrsh);
22824 + /* save GMAC Rx Control Register */
22825 + GM_IN16(IoC, Port, GM_RX_CTRL, &RxCtrl);
22827 + /* configure the GMAC FIFOs */
22828 + SkGeInitMacFifo(pAC, IoC, Port);
22830 + SkGeInitRamBufs(pAC, IoC, Port);
22832 + SkGeInitBmu(pAC, IoC, Port);
22834 + /* configure Rx GMAC FIFO */
22835 + SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), GMF_RX_CTRL_DEF);
22837 + /* set Rx GMAC FIFO Flush Mask */
22838 + SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), 0xffff);
22840 + /* set Rx GMAC FIFO Flush Threshold */
22841 + SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), 0x20);
22843 + /* set to promiscuous mode */
22844 + Word = RxCtrl & ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
22846 + /* set GMAC Rx Control Register */
22847 + GM_OUT16(IoC, Port, GM_RX_CTRL, Word);
22849 + /* get General Purpose Control */
22850 + GM_IN16(IoC, Port, GM_GP_CTRL, &MacCtrl);
22852 + /* enable MAC Loopback Mode */
22853 + GM_OUT16(IoC, Port, GM_GP_CTRL, MacCtrl | GM_GPCR_LOOP_ENA);
22855 + /* enable MAC Loopback Mode and Rx/Tx */
22856 + GM_OUT16(IoC, Port, GM_GP_CTRL, MacCtrl | GM_GPCR_LOOP_ENA |
22857 + GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
22859 + /* clear GMAC IRQ Rx Frame Complete */
22860 + SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_CLI_RX_FC);
22862 + /* clear GMAC IRQ Tx Frame Complete */
22863 + SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_CLI_TX_FC);
22865 + /* send one packet with a size of 64bytes from RAM buffer*/
22867 + RamAdr = pPrt->PXaQRamStart / 8;
22869 + SK_OUT32(IoC, RB_ADDR(pPrt->PXaQOff, RB_WP), RamAdr + 10);
22871 + SK_OUT32(IoC, RB_ADDR(pPrt->PXaQOff, RB_LEV), 10);
22873 + /* write 1st status quad word (packet end address in RAM, packet length */
22874 + SkGeRamWrite(pAC, IoC, RamAdr, (RamAdr + 9) << 16, 64, Port);
22876 + /* write 2nd status quad word */
22877 + SkGeRamWrite(pAC, IoC, RamAdr + 1, 0, 0, Port);
22879 + for (i = 0; i < 3; i++) {
22880 + /* set MAC Destination Address */
22881 + WordBuffer[i] = pPrt->PMacAddr[i];
22884 + WordBuffer[3] = WordBuffer[0];
22886 + /* write DA to MAC header */
22887 + SkGeRamWrite(pAC, IoC, RamAdr + 2, *(SK_U32 *)&WordBuffer[0],
22888 + *(SK_U32 *)&WordBuffer[2], Port);
22890 + WordBuffer[0] = WordBuffer[1];
22891 + WordBuffer[1] = WordBuffer[2];
22892 + WordBuffer[2] = 0x3200; /* len / type field (big endian) */
22893 + WordBuffer[3] = 0;
22895 + /* write SA and type field to MAC header */
22896 + SkGeRamWrite(pAC, IoC, RamAdr + 3, *(SK_U32 *)&WordBuffer[0],
22897 + *(SK_U32 *)&WordBuffer[2], Port);
22899 + SkGeRamWrite(pAC, IoC, RamAdr + 4, 0x4c56524d, /* "MRVL" */
22900 + 0x00464d2d, Port); /* "-MF" */
22902 + for (i = 0; i < 5; i++) {
22903 + /* fill packet with zeroes */
22904 + SkGeRamWrite(pAC, IoC, RamAdr + 5 + i, 0, 0, Port);
22907 + SK_OUT32(IoC, RB_ADDR(pPrt->PXaQOff, RB_PC), 1);
22909 + SK_IN32(IoC, GMAC_TI_ST_VAL, &StartTime);
22911 + /* set timeout to 10 ms */
22912 + TimeOut = HW_MS_TO_TICKS(pAC, 10);
22915 + SK_IN32(IoC, GMAC_TI_ST_VAL, &CurrTime);
22917 + if (CurrTime >= StartTime) {
22918 + Delta = CurrTime - StartTime;
22921 + Delta = CurrTime + ~StartTime + 1;
22924 + if (Delta > TimeOut) {
22929 + /* read the GMAC Interrupt source register */
22930 + SK_IN16(IoC, MR_ADDR(Port, GMAC_IRQ_SRC), &Word);
22932 + } while ((Word & (GM_IS_TX_COMPL | GM_IS_RX_COMPL)) !=
22933 + (GM_IS_TX_COMPL | GM_IS_RX_COMPL));
22935 + /* disable MAC Loopback Mode and Rx/Tx */
22936 + GM_OUT16(IoC, Port, GM_GP_CTRL, MacCtrl);
22938 + /* restore GMAC Rx Control Register */
22939 + GM_OUT16(IoC, Port, GM_RX_CTRL, RxCtrl);
22941 + /* restore Rx GMAC FIFO Flush Mask */
22942 + SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), FlushMask);
22944 + /* restore Rx GMAC FIFO Flush Threshold */
22945 + SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), FlushTrsh);
22949 +} /* SkYuk2RestartRxBmu */
22950 +#endif /* YUK2 && !SK_SLIM */
22952 diff -ruN linux/drivers/net/sk98lin/skgemib.c linux-new/drivers/net/sk98lin/skgemib.c
22953 --- linux/drivers/net/sk98lin/skgemib.c 2006-09-20 05:42:06.000000000 +0200
22954 +++ linux-new/drivers/net/sk98lin/skgemib.c 2006-07-28 14:13:54.000000000 +0200
22958 * Project: GEnesis, PCI Gigabit Ethernet Adapter
22959 - * Version: $Revision$
22961 + * Version: $Revision$
22963 * Purpose: Private Network Management Interface Management Database
22965 ****************************************************************************/
22967 /******************************************************************************
22970 * (C)Copyright 1998-2002 SysKonnect GmbH.
22971 * (C)Copyright 2002-2003 Marvell.
22974 * (at your option) any later version.
22976 * The information in this file is provided "AS IS" without warranty.
22979 ******************************************************************************/
22982 unsigned int TableIndex, SK_U32 NetIndex);
22983 #endif /* SK_DIAG_SUPPORT */
22986 +PNMI_STATIC int Asf(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
22987 + char *pBuf, unsigned int *pLen, SK_U32 Instance,
22988 + unsigned int TableIndex, SK_U32 NetIndex);
22989 +#endif /* SK_ASF */
22992 /* defines *******************************************************************/
22993 #define ID_TABLE_SIZE (sizeof(IdTable)/sizeof(IdTable[0]))
22994 @@ -251,6 +259,183 @@
22996 SK_PNMI_RW, DiagActions, 0},
22997 #endif /* SK_DIAG_SUPPORT */
23003 + SK_PNMI_RW, Asf, 0},
23004 + {OID_SKGE_ASF_STORE_CONFIG,
23008 + SK_PNMI_RW, Asf, 0},
23009 + {OID_SKGE_ASF_ENA,
23013 + SK_PNMI_RW, Asf, 0},
23014 + {OID_SKGE_ASF_RETRANS,
23018 + SK_PNMI_RW, Asf, 0},
23019 + {OID_SKGE_ASF_RETRANS_INT,
23023 + SK_PNMI_RW, Asf, 0},
23024 + {OID_SKGE_ASF_HB_ENA,
23028 + SK_PNMI_RW, Asf, 0},
23029 + {OID_SKGE_ASF_HB_INT,
23033 + SK_PNMI_RW, Asf, 0},
23034 + {OID_SKGE_ASF_WD_ENA,
23038 + SK_PNMI_RW, Asf, 0},
23039 + {OID_SKGE_ASF_WD_TIME,
23043 + SK_PNMI_RW, Asf, 0},
23044 + {OID_SKGE_ASF_IP_SOURCE,
23048 + SK_PNMI_RW, Asf, 0},
23049 + {OID_SKGE_ASF_MAC_SOURCE,
23053 + SK_PNMI_RW, Asf, 0},
23054 + {OID_SKGE_ASF_IP_DEST,
23058 + SK_PNMI_RW, Asf, 0},
23059 + {OID_SKGE_ASF_MAC_DEST,
23063 + SK_PNMI_RW, Asf, 0},
23064 + {OID_SKGE_ASF_COMMUNITY_NAME,
23068 + SK_PNMI_RW, Asf, 0},
23069 + {OID_SKGE_ASF_RSP_ENA,
23073 + SK_PNMI_RW, Asf, 0},
23074 + {OID_SKGE_ASF_RETRANS_COUNT_MIN,
23078 + SK_PNMI_RW, Asf, 0},
23079 + {OID_SKGE_ASF_RETRANS_COUNT_MAX,
23083 + SK_PNMI_RW, Asf, 0},
23084 + {OID_SKGE_ASF_RETRANS_INT_MIN,
23088 + SK_PNMI_RW, Asf, 0},
23089 + {OID_SKGE_ASF_RETRANS_INT_MAX,
23093 + SK_PNMI_RW, Asf, 0},
23094 + {OID_SKGE_ASF_HB_INT_MIN,
23098 + SK_PNMI_RW, Asf, 0},
23099 + {OID_SKGE_ASF_HB_INT_MAX,
23103 + SK_PNMI_RW, Asf, 0},
23104 + {OID_SKGE_ASF_WD_TIME_MIN,
23108 + SK_PNMI_RW, Asf, 0},
23109 + {OID_SKGE_ASF_WD_TIME_MAX,
23113 + SK_PNMI_RW, Asf, 0},
23114 + {OID_SKGE_ASF_HB_CAP,
23118 + SK_PNMI_RW, Asf, 0},
23119 + {OID_SKGE_ASF_WD_TIMER_RES,
23123 + SK_PNMI_RW, Asf, 0},
23124 + {OID_SKGE_ASF_GUID,
23128 + SK_PNMI_RW, Asf, 0},
23129 + {OID_SKGE_ASF_KEY_OP,
23133 + SK_PNMI_RW, Asf, 0},
23134 + {OID_SKGE_ASF_KEY_ADM,
23138 + SK_PNMI_RW, Asf, 0},
23139 + {OID_SKGE_ASF_KEY_GEN,
23143 + SK_PNMI_RW, Asf, 0},
23144 + {OID_SKGE_ASF_CAP,
23148 + SK_PNMI_RW, Asf, 0},
23149 + {OID_SKGE_ASF_PAR_1,
23153 + SK_PNMI_RW, Asf, 0},
23154 + {OID_SKGE_ASF_OVERALL_OID,
23158 + SK_PNMI_RW, Asf, 0},
23159 + {OID_SKGE_ASF_FWVER_OID,
23163 + SK_PNMI_RO, Asf, 0},
23164 + {OID_SKGE_ASF_ACPI_OID,
23168 + SK_PNMI_RO, Asf, 0},
23169 + {OID_SKGE_ASF_SMBUS_OID,
23173 + SK_PNMI_RO, Asf, 0},
23174 +#endif /* SK_ASF */
23175 {OID_SKGE_MDB_VERSION,
23178 @@ -871,6 +1056,13 @@
23179 sizeof(SK_PNMI_CONF),
23180 SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyType),
23181 SK_PNMI_RO, MacPrivateConf, 0},
23182 +#ifdef SK_PHY_LP_MODE
23183 + {OID_SKGE_PHY_LP_MODE,
23184 + SK_PNMI_MAC_ENTRIES,
23185 + sizeof(SK_PNMI_CONF),
23186 + SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyMode),
23187 + SK_PNMI_RW, MacPrivateConf, 0},
23189 {OID_SKGE_LINK_CAP,
23190 SK_PNMI_MAC_ENTRIES,
23191 sizeof(SK_PNMI_CONF),
23192 @@ -1066,6 +1258,11 @@
23195 SK_PNMI_RO, Vct, 0},
23196 + {OID_SKGE_VCT_CAPABILITIES,
23200 + SK_PNMI_RO, Vct, 0},
23201 {OID_SKGE_BOARDLEVEL,
23204 diff -ruN linux/drivers/net/sk98lin/skgepnmi.c linux-new/drivers/net/sk98lin/skgepnmi.c
23205 --- linux/drivers/net/sk98lin/skgepnmi.c 2006-09-20 05:42:06.000000000 +0200
23206 +++ linux-new/drivers/net/sk98lin/skgepnmi.c 2006-07-28 14:13:54.000000000 +0200
23208 /*****************************************************************************
23211 - * Project: GEnesis, PCI Gigabit Ethernet Adapter
23212 - * Version: $Revision$
23214 + * Project: Gigabit Ethernet Adapters, PNMI-Module
23215 + * Version: $Revision$
23217 * Purpose: Private Network Management Interface
23219 ****************************************************************************/
23221 /******************************************************************************
23224 * (C)Copyright 1998-2002 SysKonnect GmbH.
23225 * (C)Copyright 2002-2003 Marvell.
23227 @@ -19,14 +20,14 @@
23228 * (at your option) any later version.
23230 * The information in this file is provided "AS IS" without warranty.
23233 ******************************************************************************/
23237 +#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
23238 static const char SysKonnectFileId[] =
23239 - "@(#) $Id$ (C) Marvell.";
23240 -#endif /* !_lint */
23241 + "@(#) $Id$ (C) Marvell.";
23244 #include "h/skdrv1st.h"
23245 #include "h/sktypes.h"
23246 @@ -38,12 +39,14 @@
23247 #include "h/skcsum.h"
23248 #include "h/skvpd.h"
23249 #include "h/skgehw.h"
23250 +#include "h/sky2le.h"
23251 #include "h/skgeinit.h"
23252 #include "h/skdrv2nd.h"
23253 #include "h/skgepnm2.h"
23254 #ifdef SK_POWER_MGMT
23255 #include "h/skgepmgt.h"
23257 +#endif /* SK_POWER_MGMT */
23259 /* defines *******************************************************************/
23266 - * Public Function prototypes
23268 -int SkPnmiInit(SK_AC *pAC, SK_IOC IoC, int level);
23269 -int SkPnmiSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void *pBuf,
23270 - unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex);
23271 -int SkPnmiGetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf,
23272 - unsigned int *pLen, SK_U32 NetIndex);
23273 -int SkPnmiPreSetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf,
23274 - unsigned int *pLen, SK_U32 NetIndex);
23275 -int SkPnmiSetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf,
23276 - unsigned int *pLen, SK_U32 NetIndex);
23277 -int SkPnmiEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Param);
23278 -int SkPnmiGenIoctl(SK_AC *pAC, SK_IOC IoC, void * pBuf,
23279 - unsigned int * pLen, SK_U32 NetIndex);
23283 * Private Function prototypes
23287 PNMI_STATIC int RlmtUpdate(SK_AC *pAC, SK_IOC IoC, SK_U32 NetIndex);
23288 PNMI_STATIC int SirqUpdate(SK_AC *pAC, SK_IOC IoC);
23289 PNMI_STATIC void VirtualConf(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, char *pBuf);
23290 -PNMI_STATIC int Vct(SK_AC *pAC, SK_IOC IoC, int Action, SK_U32 Id, char *pBuf,
23291 - unsigned int *pLen, SK_U32 Instance, unsigned int TableIndex, SK_U32 NetIndex);
23292 PNMI_STATIC void CheckVctStatus(SK_AC *, SK_IOC, char *, SK_U32, SK_U32);
23293 +PNMI_STATIC void VctGetResults(SK_AC *, SK_IOC, SK_U32);
23296 * Table to correlate OID with handler function and index to
23297 @@ -349,17 +334,13 @@
23301 -SK_AC *pAC, /* Pointer to adapter context */
23302 -SK_IOC IoC, /* IO context handle */
23303 -int Level) /* Initialization level */
23304 +SK_AC *pAC, /* Pointer to adapter context */
23305 +SK_IOC IoC, /* IO context handle */
23306 +int Level) /* Initialization level */
23308 unsigned int PortMax; /* Number of ports */
23309 unsigned int PortIndex; /* Current port index in loop */
23310 - SK_U16 Val16; /* Multiple purpose 16 bit variable */
23311 - SK_U8 Val8; /* Mulitple purpose 8 bit variable */
23312 - SK_EVPARA EventParam; /* Event struct for timer event */
23313 - SK_PNMI_VCT *pVctBackupData;
23315 + SK_EVPARA EventParam; /* Event struct for timer event */
23317 SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
23318 ("PNMI: SkPnmiInit: Called, level=%d\n", Level));
23319 @@ -368,13 +349,19 @@
23322 SK_MEMSET((char *)&pAC->Pnmi, 0, sizeof(pAC->Pnmi));
23324 pAC->Pnmi.TrapBufFree = SK_PNMI_TRAP_QUEUE_LEN;
23325 pAC->Pnmi.StartUpTime = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC));
23326 pAC->Pnmi.RlmtChangeThreshold = SK_PNMI_DEF_RLMT_CHG_THRES;
23328 for (PortIndex = 0; PortIndex < SK_MAX_MACS; PortIndex ++) {
23330 pAC->Pnmi.Port[PortIndex].ActiveFlag = SK_FALSE;
23331 pAC->Pnmi.DualNetActiveFlag = SK_FALSE;
23333 + /* Initialize DSP variables for Vct() to 0xff => Never written! */
23334 + pAC->GIni.GP[PortIndex].PCableLen = 0xff;
23335 + pAC->Pnmi.VctBackup[PortIndex].CableLen = 0xff;
23338 #ifdef SK_PNMI_CHECK
23339 @@ -404,51 +391,36 @@
23344 - * Reset MAC counters
23347 + /* Reset MAC counters. */
23348 PortMax = pAC->GIni.GIMacsFound;
23350 for (PortIndex = 0; PortIndex < PortMax; PortIndex ++) {
23352 pAC->GIni.GIFunc.pFnMacResetCounter(pAC, IoC, PortIndex);
23355 - /* Initialize DSP variables for Vct() to 0xff => Never written! */
23356 - for (PortIndex = 0; PortIndex < PortMax; PortIndex ++) {
23357 - pAC->GIni.GP[PortIndex].PCableLen = 0xff;
23358 - pVctBackupData = &pAC->Pnmi.VctBackup[PortIndex];
23359 - pVctBackupData->PCableLen = 0xff;
23363 - * Get pci bus speed
23365 - SK_IN16(IoC, B0_CTST, &Val16);
23366 - if ((Val16 & CS_BUS_CLOCK) == 0) {
23368 - pAC->Pnmi.PciBusSpeed = 33;
23369 + /* Get PCI bus speed. */
23370 + if (pAC->GIni.GIPciClock66) {
23372 + pAC->Pnmi.PciBusSpeed = 66;
23375 - pAC->Pnmi.PciBusSpeed = 66;
23376 + pAC->Pnmi.PciBusSpeed = 33;
23380 - * Get pci bus width
23382 - SK_IN16(IoC, B0_CTST, &Val16);
23383 - if ((Val16 & CS_BUS_SLOT_SZ) == 0) {
23384 + /* Get PCI bus width. */
23385 + if (pAC->GIni.GIPciSlot64) {
23387 - pAC->Pnmi.PciBusWidth = 32;
23388 + pAC->Pnmi.PciBusWidth = 64;
23391 - pAC->Pnmi.PciBusWidth = 64;
23392 + pAC->Pnmi.PciBusWidth = 32;
23398 + /* Get chipset. */
23399 switch (pAC->GIni.GIChipId) {
23401 case CHIP_ID_GENESIS:
23402 pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_XMAC;
23404 @@ -457,57 +429,51 @@
23405 pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON;
23408 + case CHIP_ID_YUKON_LITE:
23409 + pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_LITE;
23412 + case CHIP_ID_YUKON_LP:
23413 + pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_LP;
23416 + case CHIP_ID_YUKON_XL:
23417 + pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_XL;
23420 + case CHIP_ID_YUKON_EC:
23421 + pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_EC;
23424 + case CHIP_ID_YUKON_FE:
23425 + pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_FE;
23433 - * Get PMD and DeviceType
23435 - SK_IN8(IoC, B2_PMD_TYP, &Val8);
23437 + /* Get PMD and Device Type. */
23438 + switch (pAC->GIni.GIPmdTyp) {
23442 - if (pAC->GIni.GIMacsFound > 1) {
23444 - pAC->Pnmi.DeviceType = 0x00020002;
23447 - pAC->Pnmi.DeviceType = 0x00020001;
23449 + pAC->Pnmi.DeviceType = 0x00020001;
23454 - if (pAC->GIni.GIMacsFound > 1) {
23456 - pAC->Pnmi.DeviceType = 0x00020004;
23459 - pAC->Pnmi.DeviceType = 0x00020003;
23461 + pAC->Pnmi.DeviceType = 0x00020003;
23466 - if (pAC->GIni.GIMacsFound > 1) {
23468 - pAC->Pnmi.DeviceType = 0x00020006;
23471 - pAC->Pnmi.DeviceType = 0x00020005;
23473 + pAC->Pnmi.DeviceType = 0x00020005;
23478 - if (pAC->GIni.GIMacsFound > 1) {
23480 - pAC->Pnmi.DeviceType = 0x00020008;
23483 - pAC->Pnmi.DeviceType = 0x00020007;
23485 + pAC->Pnmi.DeviceType = 0x00020007;
23489 @@ -516,11 +482,14 @@
23496 - SK_IN8(IoC, B2_CONN_TYP, &Val8);
23498 + if (pAC->GIni.GIMacsFound > 1) {
23500 + pAC->Pnmi.DeviceType++;
23503 + /* Get connector type. */
23504 + switch (pAC->GIni.GIConTyp) {
23507 pAC->Pnmi.Connector = 2;
23509 @@ -548,17 +517,17 @@
23514 - * Start timer for RLMT change counter
23517 + /* Start timer for RLMT change counter. */
23518 SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
23520 SkTimerStart(pAC, IoC, &pAC->Pnmi.RlmtChangeEstimate.EstTimer,
23521 - 28125000, SKGE_PNMI, SK_PNMI_EVT_CHG_EST_TIMER,
23522 + SK_PNMI_EVT_TIMER_CHECK, SKGE_PNMI, SK_PNMI_EVT_CHG_EST_TIMER,
23527 - break; /* Nothing todo */
23528 + break; /* Nothing to do. */
23532 @@ -583,7 +552,7 @@
23533 * exist (e.g. port instance 3 on a two port
23536 -static int SkPnmiGetVar(
23538 SK_AC *pAC, /* Pointer to adapter context */
23539 SK_IOC IoC, /* IO context handle */
23540 SK_U32 Id, /* Object ID that is to be processed */
23541 @@ -607,7 +576,7 @@
23543 * Calls a general sub-function for all this stuff. The preset does
23544 * the same as a set, but returns just before finally setting the
23545 - * new value. This is useful to check if a set might be successfull.
23546 + * new value. This is usefull to check if a set might be successfull.
23547 * If the instance -1 is passed, an array of values is supposed and
23548 * all instances of the OID will be set.
23550 @@ -625,7 +594,7 @@
23551 * exist (e.g. port instance 3 on a two port
23554 -static int SkPnmiPreSetVar(
23555 +int SkPnmiPreSetVar(
23556 SK_AC *pAC, /* Pointer to adapter context */
23557 SK_IOC IoC, /* IO context handle */
23558 SK_U32 Id, /* Object ID that is to be processed */
23559 @@ -638,7 +607,6 @@
23560 ("PNMI: SkPnmiPreSetVar: Called, Id=0x%x, BufLen=%d, Instance=%d, NetIndex=%d\n",
23561 Id, *pLen, Instance, NetIndex));
23564 return (PnmiVar(pAC, IoC, SK_PNMI_PRESET, Id, (char *)pBuf, pLen,
23565 Instance, NetIndex));
23567 @@ -650,7 +618,7 @@
23569 * Calls a general sub-function for all this stuff. The preset does
23570 * the same as a set, but returns just before finally setting the
23571 - * new value. This is useful to check if a set might be successfull.
23572 + * new value. This is usefull to check if a set might be successfull.
23573 * If the instance -1 is passed, an array of values is supposed and
23574 * all instances of the OID will be set.
23576 @@ -720,7 +688,6 @@
23577 unsigned int TmpLen;
23578 char KeyArr[SK_PNMI_VPD_ENTRIES][SK_PNMI_VPD_KEY_SIZE];
23581 SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
23582 ("PNMI: SkPnmiGetStruct: Called, BufLen=%d, NetIndex=%d\n",
23584 @@ -729,22 +696,19 @@
23586 if (*pLen >= SK_PNMI_MIN_STRUCT_SIZE) {
23588 - SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_TOO_SHORT,
23590 + SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_TOO_SHORT, (SK_U32)(-1));
23593 *pLen = SK_PNMI_STRUCT_SIZE;
23594 return (SK_PNMI_ERR_TOO_SHORT);
23600 + /* Check NetIndex. */
23601 if (NetIndex >= pAC->Rlmt.NumNets) {
23602 return (SK_PNMI_ERR_UNKNOWN_NET);
23605 - /* Update statistic */
23606 + /* Update statistics. */
23607 SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On call");
23609 if ((Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1)) !=
23610 @@ -769,35 +733,37 @@
23615 - * Increment semaphores to indicate that an update was
23618 + /* Increment semaphores to indicate that an update was already done. */
23619 pAC->Pnmi.MacUpdatedFlag ++;
23620 pAC->Pnmi.RlmtUpdatedFlag ++;
23621 pAC->Pnmi.SirqUpdatedFlag ++;
23623 - /* Get vpd keys for instance calculation */
23624 - Ret = GetVpdKeyArr(pAC, IoC, &KeyArr[0][0], sizeof(KeyArr), &TmpLen);
23625 - if (Ret != SK_PNMI_ERR_OK) {
23627 + * Get VPD keys for instance calculation.
23628 + * Please read comment in Vpd().
23630 + if (pAC->Pnmi.VpdKeyReadError == SK_FALSE) {
23631 + Ret = GetVpdKeyArr(pAC, IoC, &KeyArr[0][0], sizeof(KeyArr), &TmpLen);
23632 + if (Ret != SK_PNMI_ERR_OK) {
23634 - pAC->Pnmi.MacUpdatedFlag --;
23635 - pAC->Pnmi.RlmtUpdatedFlag --;
23636 - pAC->Pnmi.SirqUpdatedFlag --;
23637 + pAC->Pnmi.MacUpdatedFlag --;
23638 + pAC->Pnmi.RlmtUpdatedFlag --;
23639 + pAC->Pnmi.SirqUpdatedFlag --;
23641 - SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On return");
23642 - SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1));
23643 - *pLen = SK_PNMI_MIN_STRUCT_SIZE;
23644 - return (SK_PNMI_ERR_GENERAL);
23645 + SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On return");
23646 + SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1));
23647 + *pLen = SK_PNMI_MIN_STRUCT_SIZE;
23648 + return (SK_PNMI_ERR_GENERAL);
23652 - /* Retrieve values */
23653 + /* Retrieve values. */
23654 SK_MEMSET((char *)pBuf, 0, SK_PNMI_STRUCT_SIZE);
23656 for (TableIndex = 0; TableIndex < ID_TABLE_SIZE; TableIndex ++) {
23658 InstanceNo = IdTable[TableIndex].InstanceNo;
23659 - for (InstanceCnt = 1; InstanceCnt <= InstanceNo;
23660 - InstanceCnt ++) {
23661 + for (InstanceCnt = 1; InstanceCnt <= InstanceNo; InstanceCnt ++) {
23663 DstOffset = IdTable[TableIndex].Offset +
23664 (InstanceCnt - 1) *
23665 @@ -866,7 +832,7 @@
23667 * Calls a general sub-function for all this set stuff. The preset does
23668 * the same as a set, but returns just before finally setting the
23669 - * new value. This is useful to check if a set might be successfull.
23670 + * new value. This is usefull to check if a set might be successfull.
23671 * The sub-function runs through the IdTable, checks which OIDs are able
23672 * to set, and calls the handler function of the OID to perform the
23673 * preset. The return value of the function will also be stored in
23674 @@ -994,7 +960,6 @@
23675 unsigned int PhysPortIndex;
23676 unsigned int MaxNetNumber;
23680 SK_U64 OverflowStatus;
23682 @@ -1008,12 +973,7 @@
23684 SK_PNMI_ESTIMATE *pEst;
23687 - SK_PNMI_VCT *pVctBackupData;
23690 - SK_U32 CableLength;
23694 if (Event != SK_PNMI_EVT_XMAC_RESET) {
23695 @@ -1044,9 +1004,7 @@
23697 OverflowStatus = 0;
23700 - * Check which source caused an overflow interrupt.
23702 + /* Check which source caused an overflow interrupt. */
23703 if ((pAC->GIni.GIFunc.pFnMacOverflow(pAC, IoC, PhysPortIndex,
23704 MacStatus, &OverflowStatus) != 0) ||
23705 (OverflowStatus == 0)) {
23706 @@ -1064,7 +1022,6 @@
23708 Mask = (SK_U64)1 << CounterIndex;
23709 if ((OverflowStatus & Mask) == 0) {
23714 @@ -1096,9 +1053,7 @@
23715 case SK_PNMI_HRX_IRLENGTH:
23716 case SK_PNMI_HRX_RESERVED:
23719 - * the following counters aren't be handled (id > 63)
23721 + /* The following counters aren't be handled (id > 63). */
23722 case SK_PNMI_HTX_SYNC:
23723 case SK_PNMI_HTX_SYNC_OCTET:
23725 @@ -1185,7 +1140,7 @@
23726 if ((unsigned int)Param.Para64 >= (unsigned int)pAC->I2c.MaxSens) {
23728 SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
23729 - ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_SEN_ERR_UPP parameter wrong, SensorIndex=%d\n",
23730 + ("PNMI: ERR: SK_PNMI_EVT_SEN_ERR_UPP parameter wrong, SensorIndex=%d\n",
23731 (unsigned int)Param.Para64));
23734 @@ -1204,16 +1159,14 @@
23735 case SK_PNMI_EVT_CHG_EST_TIMER:
23737 * Calculate port switch average on a per hour basis
23738 - * Time interval for check : 28125 ms
23739 + * Time interval for check : 28125 ms (SK_PNMI_EVT_TIMER_CHECK)
23740 * Number of values for average : 8
23742 * Be careful in changing these values, on change check
23743 * - typedef of SK_PNMI_ESTIMATE (Size of EstValue
23744 * array one less than value number)
23745 * - Timer initialization SkTimerStart() in SkPnmiInit
23746 - * - Delta value below must be multiplicated with
23749 + * - Delta value below must be multiplicated with power of 2
23751 pEst = &pAC->Pnmi.RlmtChangeEstimate;
23752 CounterIndex = pEst->EstValueIndex + 1;
23753 @@ -1236,7 +1189,7 @@
23754 Delta = NewestValue - OldestValue;
23757 - /* Overflow situation */
23758 + /* Overflow situation. */
23759 Delta = (SK_U64)(0 - OldestValue) + NewestValue;
23762 @@ -1262,8 +1215,9 @@
23765 SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
23767 SkTimerStart(pAC, IoC, &pAC->Pnmi.RlmtChangeEstimate.EstTimer,
23768 - 28125000, SKGE_PNMI, SK_PNMI_EVT_CHG_EST_TIMER,
23769 + SK_PNMI_EVT_TIMER_CHECK, SKGE_PNMI, SK_PNMI_EVT_CHG_EST_TIMER,
23773 @@ -1307,29 +1261,25 @@
23774 (unsigned int)Param.Para64));
23778 +#endif /* DEBUG */
23780 PhysPortIndex = (unsigned int)Param.Para64;
23783 - * Update XMAC statistic to get fresh values
23785 - Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1);
23786 - if (Ret != SK_PNMI_ERR_OK) {
23787 + /* Update XMAC statistic to get fresh values. */
23788 + if (MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1) !=
23789 + SK_PNMI_ERR_OK) {
23791 SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return");
23795 - * Increment semaphore to indicate that an update was
23799 + /* Increment semaphore to indicate that an update was already done. */
23800 pAC->Pnmi.MacUpdatedFlag ++;
23802 for (CounterIndex = 0; CounterIndex < SK_PNMI_MAX_IDX;
23805 if (!StatAddr[CounterIndex][MacType].GetOffset) {
23810 @@ -1362,14 +1312,15 @@
23811 QueueRlmtPortTrap(pAC, OID_SKGE_TRAP_RLMT_PORT_UP, PhysPortIndex);
23812 (void)SK_DRIVER_SENDEVENT(pAC, IoC);
23814 - /* Bugfix for XMAC errata (#10620)*/
23815 + /* Bugfix for XMAC errata (#10620). */
23816 if (MacType == SK_MAC_XMAC) {
23817 - /* Add incremental difference to offset (#10620)*/
23818 + /* Add incremental difference to offset (#10620). */
23819 (void)pAC->GIni.GIFunc.pFnMacStatistic(pAC, IoC, PhysPortIndex,
23820 XM_RXE_SHT_ERR, &Val32);
23822 Value = (((SK_U64)pAC->Pnmi.Port[PhysPortIndex].
23823 CounterHigh[SK_PNMI_HRX_SHORTS] << 32) | (SK_U64)Val32);
23825 pAC->Pnmi.Port[PhysPortIndex].CounterOffset[SK_PNMI_HRX_SHORTS] +=
23826 Value - pAC->Pnmi.Port[PhysPortIndex].RxShortZeroMark;
23828 @@ -1399,7 +1350,7 @@
23829 QueueRlmtPortTrap(pAC, OID_SKGE_TRAP_RLMT_PORT_DOWN, PhysPortIndex);
23830 (void)SK_DRIVER_SENDEVENT(pAC, IoC);
23832 - /* Bugfix #10620 - get zero level for incremental difference */
23833 + /* Bugfix #10620 - get zero level for incremental difference. */
23834 if (MacType == SK_MAC_XMAC) {
23836 (void)pAC->GIni.GIFunc.pFnMacStatistic(pAC, IoC, PhysPortIndex,
23837 @@ -1431,17 +1382,13 @@
23842 - * For now, ignore event if NetIndex != 0.
23844 + /* For now, ignore event if NetIndex != 0. */
23845 if (Param.Para32[1] != 0) {
23851 - * Nothing to do if port is already inactive
23853 + /* Nothing to do if port is already inactive. */
23854 if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
23857 @@ -1472,7 +1419,6 @@
23860 if (!StatAddr[CounterIndex][MacType].GetOffset) {
23865 @@ -1481,9 +1427,7 @@
23866 pAC->Pnmi.VirtualCounterOffset[CounterIndex] += Value;
23870 - * Set port to inactive
23872 + /* Set port to inactive. */
23873 pAC->Pnmi.Port[PhysPortIndex].ActiveFlag = SK_FALSE;
23875 pAC->Pnmi.MacUpdatedFlag --;
23876 @@ -1509,25 +1453,19 @@
23881 - * For now, ignore event if NetIndex != 0.
23883 + /* For now, ignore event if NetIndex != 0. */
23884 if (Param.Para32[1] != 0) {
23890 - * Nothing to do if port is already active
23892 + /* Nothing to do if port is already inactive. */
23893 if (pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
23899 - * Statistic maintenance
23901 + /* Statistic maintenance. */
23902 pAC->Pnmi.RlmtChangeCts ++;
23903 pAC->Pnmi.RlmtChangeTime = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC));
23905 @@ -1561,7 +1499,6 @@
23908 if (!StatAddr[CounterIndex][MacType].GetOffset) {
23913 @@ -1570,16 +1507,14 @@
23914 pAC->Pnmi.VirtualCounterOffset[CounterIndex] -= Value;
23917 - /* Set port to active */
23918 + /* Set port to active. */
23919 pAC->Pnmi.Port[PhysPortIndex].ActiveFlag = SK_TRUE;
23921 pAC->Pnmi.MacUpdatedFlag --;
23924 case SK_PNMI_EVT_RLMT_SEGMENTATION:
23926 - * Para.Para32[0] contains the NetIndex.
23928 + /* Para.Para32[0] contains the NetIndex. */
23931 * Store a trap message in the trap buffer and generate an event for
23932 @@ -1594,71 +1529,53 @@
23933 * Param.Para32[0] contains the number of Nets.
23934 * Param.Para32[1] is reserved, contains -1.
23937 - * Check number of nets
23939 + /* Check number of nets. */
23940 MaxNetNumber = pAC->GIni.GIMacsFound;
23941 - if (((unsigned int)Param.Para32[0] < 1)
23942 - || ((unsigned int)Param.Para32[0] > MaxNetNumber)) {
23944 + if (((unsigned int)Param.Para32[0] < 1) ||
23945 + ((unsigned int)Param.Para32[0] > MaxNetNumber)) {
23947 return (SK_PNMI_ERR_UNKNOWN_NET);
23950 - if ((unsigned int)Param.Para32[0] == 1) { /* single net mode */
23951 + if ((unsigned int)Param.Para32[0] == 1) { /* SingleNet mode. */
23952 pAC->Pnmi.DualNetActiveFlag = SK_FALSE;
23954 - else { /* dual net mode */
23955 + else { /* DualNet mode. */
23956 pAC->Pnmi.DualNetActiveFlag = SK_TRUE;
23960 case SK_PNMI_EVT_VCT_RESET:
23961 PhysPortIndex = Param.Para32[0];
23962 - pPrt = &pAC->GIni.GP[PhysPortIndex];
23963 - pVctBackupData = &pAC->Pnmi.VctBackup[PhysPortIndex];
23965 if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_PENDING) {
23967 RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_FALSE);
23969 if (RetCode == 2) {
23971 * VCT test is still running.
23972 * Start VCT timer counter again.
23974 - SK_MEMSET((char *) &Param, 0, sizeof(Param));
23975 + SK_MEMSET((char *)&Param, 0, sizeof(Param));
23977 Param.Para32[0] = PhysPortIndex;
23978 Param.Para32[1] = -1;
23979 - SkTimerStart(pAC, IoC,
23980 - &pAC->Pnmi.VctTimeout[PhysPortIndex].VctTimer,
23981 - 4000000, SKGE_PNMI, SK_PNMI_EVT_VCT_RESET, Param);
23983 + SkTimerStart(pAC, IoC, &pAC->Pnmi.VctTimeout[PhysPortIndex],
23984 + SK_PNMI_VCT_TIMER_CHECK, SKGE_PNMI, SK_PNMI_EVT_VCT_RESET, Param);
23988 - pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_PENDING;
23989 - pAC->Pnmi.VctStatus[PhysPortIndex] |=
23990 - (SK_PNMI_VCT_NEW_VCT_DATA | SK_PNMI_VCT_TEST_DONE);
23992 - /* Copy results for later use to PNMI struct. */
23993 - for (i = 0; i < 4; i++) {
23994 - if (pPrt->PMdiPairSts[i] == SK_PNMI_VCT_NORMAL_CABLE) {
23995 - if ((pPrt->PMdiPairLen[i] > 35) &&
23996 - (pPrt->PMdiPairLen[i] < 0xff)) {
23997 - pPrt->PMdiPairSts[i] = SK_PNMI_VCT_IMPEDANCE_MISMATCH;
24000 - if ((pPrt->PMdiPairLen[i] > 35) &&
24001 - (pPrt->PMdiPairLen[i] != 0xff)) {
24002 - CableLength = 1000 *
24003 - (((175 * pPrt->PMdiPairLen[i]) / 210) - 28);
24008 - pVctBackupData->PMdiPairLen[i] = CableLength;
24009 - pVctBackupData->PMdiPairSts[i] = pPrt->PMdiPairSts[i];
24011 + VctGetResults(pAC, IoC, PhysPortIndex);
24013 - Param.Para32[0] = PhysPortIndex;
24014 - Param.Para32[1] = -1;
24015 - SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Param);
24016 - SkEventDispatcher(pAC, IoC);
24017 + EventParam.Para32[0] = PhysPortIndex;
24018 + EventParam.Para32[1] = -1;
24019 + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, EventParam);
24021 + /* SkEventDispatcher(pAC, IoC); */
24025 @@ -1706,14 +1623,13 @@
24026 unsigned int TableIndex;
24030 if ((TableIndex = LookupId(Id)) == (unsigned int)(-1)) {
24033 return (SK_PNMI_ERR_UNKNOWN_OID);
24036 - /* Check NetIndex */
24037 + /* Check NetIndex. */
24038 if (NetIndex >= pAC->Rlmt.NumNets) {
24039 return (SK_PNMI_ERR_UNKNOWN_NET);
24041 @@ -1763,22 +1679,20 @@
24046 - /* Check if the passed buffer has the right size */
24047 + /* Check if the passed buffer has the right size. */
24048 if (*pLen < SK_PNMI_STRUCT_SIZE) {
24050 - /* Check if we can return the error within the buffer */
24051 + /* Check if we can return the error within the buffer. */
24052 if (*pLen >= SK_PNMI_MIN_STRUCT_SIZE) {
24054 - SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_TOO_SHORT,
24056 + SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_TOO_SHORT, (SK_U32)(-1));
24059 *pLen = SK_PNMI_STRUCT_SIZE;
24060 return (SK_PNMI_ERR_TOO_SHORT);
24063 - /* Check NetIndex */
24064 + /* Check NetIndex. */
24065 if (NetIndex >= pAC->Rlmt.NumNets) {
24066 return (SK_PNMI_ERR_UNKNOWN_NET);
24068 @@ -1806,12 +1720,11 @@
24069 pAC->Pnmi.RlmtUpdatedFlag ++;
24070 pAC->Pnmi.SirqUpdatedFlag ++;
24072 - /* Preset/Set values */
24073 + /* PRESET/SET values. */
24074 for (TableIndex = 0; TableIndex < ID_TABLE_SIZE; TableIndex ++) {
24076 if ((IdTable[TableIndex].Access != SK_PNMI_RW) &&
24077 (IdTable[TableIndex].Access != SK_PNMI_WO)) {
24082 @@ -1822,8 +1735,7 @@
24085 DstOffset = IdTable[TableIndex].Offset +
24086 - (InstanceCnt - 1) *
24087 - IdTable[TableIndex].StructSize;
24088 + (InstanceCnt - 1) * IdTable[TableIndex].StructSize;
24091 * Because VPD multiple instance variables are
24092 @@ -1833,9 +1745,7 @@
24094 Instance = (SK_U32)InstanceCnt;
24097 - * Evaluate needed buffer length
24099 + /* Evaluate needed buffer length. */
24101 Ret = IdTable[TableIndex].Func(pAC, IoC,
24102 SK_PNMI_GET, IdTable[TableIndex].Id,
24103 @@ -1851,8 +1761,7 @@
24104 pAC->Pnmi.SirqUpdatedFlag --;
24106 SK_PNMI_CHECKFLAGS("PnmiStruct: On return");
24107 - SK_PNMI_SET_STAT(pBuf,
24108 - SK_PNMI_ERR_GENERAL, DstOffset);
24109 + SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_GENERAL, DstOffset);
24110 *pLen = SK_PNMI_MIN_STRUCT_SIZE;
24111 return (SK_PNMI_ERR_GENERAL);
24113 @@ -1874,7 +1783,7 @@
24117 - /* Call the OID handler function */
24118 + /* Call the OID handler function. */
24119 Ret = IdTable[TableIndex].Func(pAC, IoC, Action,
24120 IdTable[TableIndex].Id, pBuf + DstOffset,
24121 &Len, Instance, TableIndex, NetIndex);
24122 @@ -1885,8 +1794,7 @@
24123 pAC->Pnmi.SirqUpdatedFlag --;
24125 SK_PNMI_CHECKFLAGS("PnmiStruct: On return");
24126 - SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_BAD_VALUE,
24128 + SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_BAD_VALUE, DstOffset);
24129 *pLen = SK_PNMI_MIN_STRUCT_SIZE;
24130 return (SK_PNMI_ERR_BAD_VALUE);
24132 @@ -1920,7 +1828,7 @@
24134 if (IdTable[i].Id == Id) {
24141 @@ -1961,16 +1869,13 @@
24143 if (Id != OID_SKGE_ALL_DATA) {
24145 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR003,
24146 - SK_PNMI_ERR003MSG);
24147 + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR003, SK_PNMI_ERR003MSG);
24150 return (SK_PNMI_ERR_GENERAL);
24154 - * Check instance. We only handle single instance variables
24156 + /* Check instance. We only handle single instance variables. */
24157 if (Instance != (SK_U32)(-1) && Instance != 1) {
24160 @@ -2029,10 +1934,7 @@
24166 - * Check instance. We only handle single instance variables
24168 + /* Check instance. We only handle single instance variables. */
24169 if (Instance != (SK_U32)(-1) && Instance != 1) {
24172 @@ -2045,10 +1947,10 @@
24173 return (SK_PNMI_ERR_TOO_SHORT);
24176 - /* Check if a get should be performed */
24177 + /* Check if a GET should be performed. */
24178 if (Action == SK_PNMI_GET) {
24180 - /* A get is easy. We always return the same value */
24181 + /* A GET is easy. We always return the same value. */
24182 ActionOp = (SK_U32)SK_PNMI_ACT_IDLE;
24183 SK_PNMI_STORE_U32(pBuf, ActionOp);
24184 *pLen = sizeof(SK_U32);
24185 @@ -2056,13 +1958,13 @@
24186 return (SK_PNMI_ERR_OK);
24189 - /* Continue with PRESET/SET action */
24190 + /* Continue with PRESET/SET action. */
24191 if (*pLen > sizeof(SK_U32)) {
24193 return (SK_PNMI_ERR_BAD_VALUE);
24196 - /* Check if the command is a known one */
24197 + /* Check if the command is a known one. */
24198 SK_PNMI_READ_U32(pBuf, ActionOp);
24199 if (*pLen > sizeof(SK_U32) ||
24200 (ActionOp != SK_PNMI_ACT_IDLE &&
24201 @@ -2074,7 +1976,7 @@
24202 return (SK_PNMI_ERR_BAD_VALUE);
24205 - /* A preset ends here */
24206 + /* A PRESET ends here. */
24207 if (Action == SK_PNMI_PRESET) {
24209 return (SK_PNMI_ERR_OK);
24210 @@ -2083,19 +1985,15 @@
24211 switch (ActionOp) {
24213 case SK_PNMI_ACT_IDLE:
24214 - /* Nothing to do */
24215 + /* Nothing to do. */
24218 case SK_PNMI_ACT_RESET:
24220 - * Perform a driver reset or something that comes near
24223 + /* Perform a driver reset or something that comes near to this. */
24224 Ret = SK_DRIVER_RESET(pAC, IoC);
24227 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR005,
24228 - SK_PNMI_ERR005MSG);
24229 + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR005, SK_PNMI_ERR005MSG);
24231 return (SK_PNMI_ERR_GENERAL);
24233 @@ -2112,13 +2010,12 @@
24236 case SK_PNMI_ACT_RESETCNT:
24237 - /* Set all counters and timestamps to zero */
24238 + /* Set all counters and timestamps to zero. */
24239 ResetCounter(pAC, IoC, NetIndex);
24243 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR006,
24244 - SK_PNMI_ERR006MSG);
24245 + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR006, SK_PNMI_ERR006MSG);
24247 return (SK_PNMI_ERR_GENERAL);
24249 @@ -2162,25 +2059,21 @@
24251 SK_BOOL Is64BitReq = SK_FALSE;
24254 - * Only the active Mac is returned
24256 + /* Only the active MAC is returned. */
24257 if (Instance != (SK_U32)(-1) && Instance != 1) {
24260 return (SK_PNMI_ERR_UNKNOWN_INST);
24264 - * Check action type
24266 + /* Check action type. */
24267 if (Action != SK_PNMI_GET) {
24270 return (SK_PNMI_ERR_READ_ONLY);
24273 - /* Check length */
24274 + /* Check length. */
24277 case OID_802_3_PERMANENT_ADDRESS:
24278 @@ -2201,12 +2094,12 @@
24280 #else /* SK_NDIS_64BIT_CTR */
24282 - /* for compatibility, at least 32bit are required for OID */
24283 + /* For compatibility, at least 32 bits are required for OID. */
24284 if (*pLen < sizeof(SK_U32)) {
24286 - * but indicate handling for 64bit values,
24287 - * if insufficient space is provided
24289 + * Indicate handling for 64 bit values,
24290 + * if insufficient space is provided.
24292 *pLen = sizeof(SK_U64);
24293 return (SK_PNMI_ERR_TOO_SHORT);
24295 @@ -2222,16 +2115,14 @@
24296 * to indicate that an update was already done.
24298 Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1);
24299 - if ( Ret != SK_PNMI_ERR_OK) {
24300 + if (Ret != SK_PNMI_ERR_OK) {
24305 pAC->Pnmi.MacUpdatedFlag ++;
24308 - * Get value (MAC Index 0 identifies the virtual MAC)
24310 + /* Get value (MAC index 0 identifies the virtual MAC). */
24313 case OID_802_3_PERMANENT_ADDRESS:
24314 @@ -2247,7 +2138,7 @@
24316 StatVal = GetStatVal(pAC, IoC, 0, IdTable[TableIndex].Param, NetIndex);
24318 - /* by default 32bit values are evaluated */
24319 + /* By default 32 bit values are evaluated. */
24321 StatVal32 = (SK_U32)StatVal;
24322 SK_PNMI_STORE_U32(pBuf, StatVal32);
24323 @@ -2301,21 +2192,19 @@
24330 - /* Calculate instance if wished. MAC index 0 is the virtual MAC */
24331 + /* Calculate instance if wished. MAC index 0 is the virtual MAC. */
24332 PhysPortMax = pAC->GIni.GIMacsFound;
24333 LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax);
24335 MacType = pAC->GIni.GIMacType;
24337 - if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* Dual net mode */
24338 + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* DualNet mode. */
24342 - if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried */
24343 - /* Check instance range */
24344 + if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried. */
24345 + /* Check instance range. */
24346 if ((Instance < 1) || (Instance > LogPortMax)) {
24349 @@ -2325,20 +2214,20 @@
24350 Limit = LogPortIndex + 1;
24353 - else { /* Instance == (SK_U32)(-1), get all Instances of that OID */
24354 + else { /* Instance == (SK_U32)(-1), get all Instances of that OID. */
24357 Limit = LogPortMax;
24360 - /* Check action */
24361 + /* Check action. */
24362 if (Action != SK_PNMI_GET) {
24365 return (SK_PNMI_ERR_READ_ONLY);
24368 - /* Check length */
24369 + /* Check length. */
24370 if (*pLen < (Limit - LogPortIndex) * sizeof(SK_U64)) {
24372 *pLen = (Limit - LogPortIndex) * sizeof(SK_U64);
24373 @@ -2357,7 +2246,7 @@
24375 pAC->Pnmi.MacUpdatedFlag ++;
24380 for (; LogPortIndex < Limit; LogPortIndex ++) {
24382 @@ -2463,19 +2352,16 @@
24383 unsigned int Limit;
24384 unsigned int Offset = 0;
24387 - * Calculate instance if wished. MAC index 0 is the virtual
24390 + /* Calculate instance if wished. MAC index 0 is the virtual MAC. */
24391 PhysPortMax = pAC->GIni.GIMacsFound;
24392 LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax);
24394 - if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* Dual net mode */
24395 + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* DualNet mode. */
24399 - if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried */
24400 - /* Check instance range */
24401 + if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried. */
24402 + /* Check instance range. */
24403 if ((Instance < 1) || (Instance > LogPortMax)) {
24406 @@ -2484,27 +2370,23 @@
24407 LogPortIndex = SK_PNMI_PORT_INST2LOG(Instance);
24408 Limit = LogPortIndex + 1;
24410 - else { /* Instance == (SK_U32)(-1), get all Instances of that OID */
24411 + else { /* Instance == (SK_U32)(-1), get all Instances of that OID. */
24414 Limit = LogPortMax;
24420 + /* Perform action. */
24421 if (Action == SK_PNMI_GET) {
24423 - /* Check length */
24424 + /* Check length. */
24425 if (*pLen < (Limit - LogPortIndex) * 6) {
24427 *pLen = (Limit - LogPortIndex) * 6;
24428 return (SK_PNMI_ERR_TOO_SHORT);
24435 for (; LogPortIndex < Limit; LogPortIndex ++) {
24438 @@ -2528,8 +2410,7 @@
24439 &pAC->Addr.Net[NetIndex].PermanentMacAddress);
24442 - PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
24443 - pAC, LogPortIndex);
24444 + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);
24446 CopyMac(pBuf + Offset,
24447 &pAC->Addr.Port[PhysPortIndex].PermanentMacAddress);
24448 @@ -2538,8 +2419,7 @@
24452 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR008,
24453 - SK_PNMI_ERR008MSG);
24454 + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR008, SK_PNMI_ERR008MSG);
24457 return (SK_PNMI_ERR_GENERAL);
24458 @@ -2550,8 +2430,8 @@
24462 - * The logical MAC address may not be changed only
24463 - * the physical ones
24464 + * The logical MAC address may not be changed,
24465 + * only the physical ones.
24467 if (Id == OID_SKGE_PHYS_FAC_ADDR) {
24469 @@ -2559,19 +2439,16 @@
24470 return (SK_PNMI_ERR_READ_ONLY);
24474 - * Only the current address may be changed
24476 + /* Only the current address may be changed. */
24477 if (Id != OID_SKGE_PHYS_CUR_ADDR) {
24479 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR009,
24480 - SK_PNMI_ERR009MSG);
24481 + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR009, SK_PNMI_ERR009MSG);
24484 return (SK_PNMI_ERR_GENERAL);
24487 - /* Check length */
24488 + /* Check length. */
24489 if (*pLen < (Limit - LogPortIndex) * 6) {
24491 *pLen = (Limit - LogPortIndex) * 6;
24492 @@ -2583,32 +2460,26 @@
24493 return (SK_PNMI_ERR_BAD_VALUE);
24499 + /* Check action. */
24500 if (Action == SK_PNMI_PRESET) {
24503 return (SK_PNMI_ERR_OK);
24507 - * Set OID_SKGE_MAC_CUR_ADDR
24509 + /* Set OID_SKGE_MAC_CUR_ADDR. */
24510 for (; LogPortIndex < Limit; LogPortIndex ++, Offset += 6) {
24513 * A set to virtual port and set of broadcast
24514 - * address will be ignored
24515 + * address will be ignored.
24517 if (LogPortIndex == 0 || SK_MEMCMP(pBuf + Offset,
24518 "\xff\xff\xff\xff\xff\xff", 6) == 0) {
24523 - PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC,
24525 + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);
24527 Ret = SkAddrOverride(pAC, IoC, PhysPortIndex,
24528 (SK_MAC_ADDR *)(pBuf + Offset),
24529 @@ -2661,10 +2532,7 @@
24530 unsigned int Offset = 0;
24535 - * Calculate instance if wished
24537 + /* Calculate instance if wished. */
24538 if (Instance != (SK_U32)(-1)) {
24540 if ((Instance < 1) || (Instance > SKCS_NUM_PROTOCOLS)) {
24541 @@ -2680,25 +2548,21 @@
24542 Limit = SKCS_NUM_PROTOCOLS;
24548 + /* Check action. */
24549 if (Action != SK_PNMI_GET) {
24552 return (SK_PNMI_ERR_READ_ONLY);
24555 - /* Check length */
24556 + /* Check length. */
24557 if (*pLen < (Limit - Index) * sizeof(SK_U64)) {
24559 *pLen = (Limit - Index) * sizeof(SK_U64);
24560 return (SK_PNMI_ERR_TOO_SHORT);
24567 for (; Index < Limit; Index ++) {
24570 @@ -2724,8 +2588,7 @@
24574 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR010,
24575 - SK_PNMI_ERR010MSG);
24576 + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR010, SK_PNMI_ERR010MSG);
24579 return (SK_PNMI_ERR_GENERAL);
24580 @@ -2735,9 +2598,7 @@
24581 Offset += sizeof(SK_U64);
24585 - * Store used buffer space
24587 + /* Store used buffer space. */
24590 return (SK_PNMI_ERR_OK);
24591 @@ -2780,10 +2641,7 @@
24597 - * Calculate instance if wished
24599 + /* Calculate instance if wished. */
24600 if ((Instance != (SK_U32)(-1))) {
24602 if ((Instance < 1) || (Instance > (SK_U32)pAC->I2c.MaxSens)) {
24603 @@ -2800,16 +2658,14 @@
24604 Limit = (unsigned int) pAC->I2c.MaxSens;
24610 + /* Check action. */
24611 if (Action != SK_PNMI_GET) {
24614 return (SK_PNMI_ERR_READ_ONLY);
24617 - /* Check length */
24618 + /* Check length. */
24621 case OID_SKGE_SENSOR_VALUE:
24622 @@ -2868,38 +2724,33 @@
24626 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR012,
24627 - SK_PNMI_ERR012MSG);
24628 + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR012, SK_PNMI_ERR012MSG);
24631 return (SK_PNMI_ERR_GENERAL);
24639 for (Offset = 0; Index < Limit; Index ++) {
24643 case OID_SKGE_SENSOR_INDEX:
24644 *(pBuf + Offset) = (char)Index;
24645 - Offset += sizeof(char);
24649 case OID_SKGE_SENSOR_DESCR:
24650 Len = SK_STRLEN(pAC->I2c.SenTable[Index].SenDesc);
24651 - SK_MEMCPY(pBuf + Offset + 1,
24652 - pAC->I2c.SenTable[Index].SenDesc, Len);
24653 + SK_MEMCPY(pBuf + Offset + 1, pAC->I2c.SenTable[Index].SenDesc, Len);
24654 *(pBuf + Offset) = (char)Len;
24658 case OID_SKGE_SENSOR_TYPE:
24659 - *(pBuf + Offset) =
24660 - (char)pAC->I2c.SenTable[Index].SenType;
24661 - Offset += sizeof(char);
24662 + *(pBuf + Offset) = (char)pAC->I2c.SenTable[Index].SenType;
24666 case OID_SKGE_SENSOR_VALUE:
24667 @@ -2936,9 +2787,8 @@
24670 case OID_SKGE_SENSOR_STATUS:
24671 - *(pBuf + Offset) =
24672 - (char)pAC->I2c.SenTable[Index].SenErrFlag;
24673 - Offset += sizeof(char);
24674 + *(pBuf + Offset) = (char)pAC->I2c.SenTable[Index].SenErrFlag;
24678 case OID_SKGE_SENSOR_WAR_CTS:
24679 @@ -2975,9 +2825,7 @@
24684 - * Store used buffer space
24686 + /* Store used buffer space. */
24689 return (SK_PNMI_ERR_OK);
24690 @@ -3032,8 +2880,29 @@
24694 - * Get array of all currently stored VPD keys
24696 + * VpdKeyReadError will be set in GetVpdKeyArr() if an error occurs.
24697 + * Due to the fact that some drivers use SkPnmiGetStruct() to retrieve
24698 + * all statistical data, an error in GetVpdKeyArr() will generate a PNMI
24699 + * error and terminate SkPnmiGetStruct() without filling in statistical
24700 + * data into the PNMI struct. In this case the driver will get no values
24701 + * for statistical purposes (netstat, ifconfig etc.). GetVpdKeyArr() is
24702 + * the first function to be called in SkPnmiGetStruct(), so any error
24703 + * will terminate SkPnmiGetStruct() immediately. Hence, VpdKeyReadError will
24704 + * be set during the first call to GetVpdKeyArr() to make successful calls
24705 + * to SkPnmiGetStruct() possible. But there is another point to consider:
24706 + * When filling in the statistical data into the PNMI struct, the VPD
24707 + * handler Vpd() will also be called. If GetVpdKeyArr() in Vpd() would
24708 + * return with SK_PNMI_ERR_GENERAL, SkPnmiGetStruct() would fail again.
24709 + * For this reason VpdKeyReadError is checked here and, if set, Vpd()
24710 + * will return without doing anything and the return value SK_PNMI_ERR_OK.
24711 + * Therefore SkPnmiGetStruct() is able to continue and fill in all other
24712 + * statistical data.
24714 + if (pAC->Pnmi.VpdKeyReadError == SK_TRUE) {
24715 + return (SK_PNMI_ERR_OK);
24718 + /* Get array of all currently stored VPD keys. */
24719 Ret = GetVpdKeyArr(pAC, IoC, &KeyArr[0][0], sizeof(KeyArr), &KeyNo);
24720 if (Ret != SK_PNMI_ERR_OK) {
24722 @@ -3078,34 +2947,32 @@
24727 - * Get value, if a query should be performed
24729 + /* Get value, if a query should be performed. */
24730 if (Action == SK_PNMI_GET) {
24734 case OID_SKGE_VPD_FREE_BYTES:
24735 - /* Check length of buffer */
24736 + /* Check length of buffer. */
24737 if (*pLen < sizeof(SK_U32)) {
24739 *pLen = sizeof(SK_U32);
24740 return (SK_PNMI_ERR_TOO_SHORT);
24742 - /* Get number of free bytes */
24743 + /* Get number of free bytes. */
24744 pVpdStatus = VpdStat(pAC, IoC);
24745 if (pVpdStatus == NULL) {
24747 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR017,
24748 - SK_PNMI_ERR017MSG);
24749 + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
24750 + (SK_PNMI_ERR017MSG));
24753 return (SK_PNMI_ERR_GENERAL);
24755 if ((pVpdStatus->vpd_status & VPD_VALID) == 0) {
24757 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR018,
24758 - SK_PNMI_ERR018MSG);
24759 + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
24760 + (SK_PNMI_ERR018MSG));
24763 return (SK_PNMI_ERR_GENERAL);
24764 @@ -3117,7 +2984,7 @@
24767 case OID_SKGE_VPD_ENTRIES_LIST:
24768 - /* Check length */
24769 + /* Check length. */
24770 for (Len = 0, Index = 0; Index < KeyNo; Index ++) {
24772 Len += SK_STRLEN(KeyArr[Index]) + 1;
24773 @@ -3128,7 +2995,7 @@
24774 return (SK_PNMI_ERR_TOO_SHORT);
24779 *(pBuf) = (char)Len - 1;
24780 for (Offset = 1, Index = 0; Index < KeyNo; Index ++) {
24782 @@ -3147,7 +3014,7 @@
24785 case OID_SKGE_VPD_ENTRIES_NUMBER:
24786 - /* Check length */
24787 + /* Check length. */
24788 if (*pLen < sizeof(SK_U32)) {
24790 *pLen = sizeof(SK_U32);
24791 @@ -3160,7 +3027,7 @@
24794 case OID_SKGE_VPD_KEY:
24795 - /* Check buffer length, if it is large enough */
24796 + /* Check buffer length, if it is large enough. */
24797 for (Len = 0, Index = FirstIndex;
24798 Index < LastIndex; Index ++) {
24800 @@ -3176,32 +3043,28 @@
24801 * Get the key to an intermediate buffer, because
24802 * we have to prepend a length byte.
24804 - for (Offset = 0, Index = FirstIndex;
24805 - Index < LastIndex; Index ++) {
24806 + for (Offset = 0, Index = FirstIndex; Index < LastIndex; Index ++) {
24808 Len = SK_STRLEN(KeyArr[Index]);
24810 *(pBuf + Offset) = (char)Len;
24811 - SK_MEMCPY(pBuf + Offset + 1, KeyArr[Index],
24813 + SK_MEMCPY(pBuf + Offset + 1, KeyArr[Index], Len);
24819 case OID_SKGE_VPD_VALUE:
24820 - /* Check the buffer length if it is large enough */
24821 - for (Offset = 0, Index = FirstIndex;
24822 - Index < LastIndex; Index ++) {
24823 + /* Check the buffer length if it is large enough. */
24824 + for (Offset = 0, Index = FirstIndex; Index < LastIndex; Index ++) {
24827 if (VpdRead(pAC, IoC, KeyArr[Index], Buf,
24828 (int *)&BufLen) > 0 ||
24829 BufLen >= SK_PNMI_VPD_DATALEN) {
24831 - SK_ERR_LOG(pAC, SK_ERRCL_SW,
24833 - SK_PNMI_ERR021MSG);
24834 + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
24835 + (SK_PNMI_ERR021MSG));
24837 return (SK_PNMI_ERR_GENERAL);
24839 @@ -3217,17 +3080,15 @@
24840 * Get the value to an intermediate buffer, because
24841 * we have to prepend a length byte.
24843 - for (Offset = 0, Index = FirstIndex;
24844 - Index < LastIndex; Index ++) {
24845 + for (Offset = 0, Index = FirstIndex; Index < LastIndex; Index ++) {
24848 if (VpdRead(pAC, IoC, KeyArr[Index], Buf,
24849 (int *)&BufLen) > 0 ||
24850 BufLen >= SK_PNMI_VPD_DATALEN) {
24852 - SK_ERR_LOG(pAC, SK_ERRCL_SW,
24854 - SK_PNMI_ERR022MSG);
24855 + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
24856 + (SK_PNMI_ERR022MSG));
24859 return (SK_PNMI_ERR_GENERAL);
24860 @@ -3247,8 +3108,7 @@
24861 return (SK_PNMI_ERR_TOO_SHORT);
24864 - for (Offset = 0, Index = FirstIndex;
24865 - Index < LastIndex; Index ++) {
24866 + for (Offset = 0, Index = FirstIndex; Index < LastIndex; Index ++) {
24868 if (VpdMayWrite(KeyArr[Index])) {
24870 @@ -3274,15 +3134,15 @@
24874 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR023,
24875 - SK_PNMI_ERR023MSG);
24876 + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
24877 + (SK_PNMI_ERR023MSG));
24880 return (SK_PNMI_ERR_GENERAL);
24884 - /* The only OID which can be set is VPD_ACTION */
24885 + /* The only OID which can be set is VPD_ACTION. */
24886 if (Id != OID_SKGE_VPD_ACTION) {
24888 if (Id == OID_SKGE_VPD_FREE_BYTES ||
24889 @@ -3296,8 +3156,8 @@
24890 return (SK_PNMI_ERR_READ_ONLY);
24893 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR024,
24894 - SK_PNMI_ERR024MSG);
24895 + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
24896 + (SK_PNMI_ERR024MSG));
24899 return (SK_PNMI_ERR_GENERAL);
24900 @@ -3313,14 +3173,11 @@
24901 return (SK_PNMI_ERR_TOO_SHORT);
24905 - * The first byte contains the VPD action type we should
24908 + /* The first byte contains the VPD action type we should perform. */
24911 case SK_PNMI_VPD_IGNORE:
24912 - /* Nothing to do */
24913 + /* Nothing to do. */
24916 case SK_PNMI_VPD_CREATE:
24917 @@ -3352,13 +3209,13 @@
24918 SK_MEMCPY(Buf, pBuf + 4, Offset);
24921 - /* A preset ends here */
24922 + /* A PRESET ends here. */
24923 if (Action == SK_PNMI_PRESET) {
24925 return (SK_PNMI_ERR_OK);
24928 - /* Write the new entry or modify an existing one */
24929 + /* Write the new entry or modify an existing one .*/
24930 Ret = VpdWrite(pAC, IoC, KeyStr, Buf);
24931 if (Ret == SK_PNMI_VPD_NOWRITE ) {
24933 @@ -3367,8 +3224,8 @@
24935 else if (Ret != SK_PNMI_VPD_OK) {
24937 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR025,
24938 - SK_PNMI_ERR025MSG);
24939 + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
24940 + (SK_PNMI_ERR025MSG));
24943 return (SK_PNMI_ERR_GENERAL);
24944 @@ -3381,8 +3238,8 @@
24945 Ret = VpdUpdate(pAC, IoC);
24946 if (Ret != SK_PNMI_VPD_OK) {
24948 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR026,
24949 - SK_PNMI_ERR026MSG);
24950 + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
24951 + (SK_PNMI_ERR026MSG));
24954 return (SK_PNMI_ERR_GENERAL);
24955 @@ -3390,7 +3247,7 @@
24958 case SK_PNMI_VPD_DELETE:
24959 - /* Check if the buffer size is plausible */
24960 + /* Check if the buffer size is plausible. */
24964 @@ -3405,7 +3262,7 @@
24965 KeyStr[1] = pBuf[2];
24968 - /* Find the passed key in the array */
24969 + /* Find the passed key in the array. */
24970 for (Index = 0; Index < KeyNo; Index ++) {
24972 if (SK_STRCMP(KeyStr, KeyArr[Index]) == 0) {
24973 @@ -3413,6 +3270,7 @@
24979 * If we cannot find the key it is wrong, so we
24980 * return an appropriate error value.
24981 @@ -3428,12 +3286,12 @@
24982 return (SK_PNMI_ERR_OK);
24985 - /* Ok, you wanted it and you will get it */
24986 + /* Ok, you wanted it and you will get it. */
24987 Ret = VpdDelete(pAC, IoC, KeyStr);
24988 if (Ret != SK_PNMI_VPD_OK) {
24990 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR027,
24991 - SK_PNMI_ERR027MSG);
24992 + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
24993 + (SK_PNMI_ERR027MSG));
24996 return (SK_PNMI_ERR_GENERAL);
24997 @@ -3446,8 +3304,8 @@
24998 Ret = VpdUpdate(pAC, IoC);
24999 if (Ret != SK_PNMI_VPD_OK) {
25001 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR028,
25002 - SK_PNMI_ERR028MSG);
25003 + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
25004 + (SK_PNMI_ERR028MSG));
25007 return (SK_PNMI_ERR_GENERAL);
25008 @@ -3501,23 +3359,21 @@
25011 SK_U64 Val64RxHwErrs = 0;
25012 + SK_U64 Val64RxRunt = 0;
25013 + SK_U64 Val64RxFcs = 0;
25014 SK_U64 Val64TxHwErrs = 0;
25015 SK_BOOL Is64BitReq = SK_FALSE;
25020 - * Check instance. We only handle single instance variables.
25022 + /* Check instance. We only handle single instance variables. */
25023 if (Instance != (SK_U32)(-1) && Instance != 1) {
25026 return (SK_PNMI_ERR_UNKNOWN_INST);
25030 - * Check action. We only allow get requests.
25032 + /* Check action. We only allow get requests. */
25033 if (Action != SK_PNMI_GET) {
25036 @@ -3526,9 +3382,7 @@
25038 MacType = pAC->GIni.GIMacType;
25041 - * Check length for the various supported OIDs
25043 + /* Check length for the various supported OIDs. */
25046 case OID_GEN_XMIT_ERROR:
25047 @@ -3542,14 +3396,12 @@
25049 #else /* SK_NDIS_64BIT_CTR */
25052 - * for compatibility, at least 32bit are required for oid
25054 + /* For compatibility, at least 32bit are required for OID. */
25055 if (*pLen < sizeof(SK_U32)) {
25057 - * but indicate handling for 64bit values,
25058 - * if insufficient space is provided
25060 + * Indicate handling for 64bit values,
25061 + * if insufficient space is provided.
25063 *pLen = sizeof(SK_U64);
25064 return (SK_PNMI_ERR_TOO_SHORT);
25066 @@ -3620,11 +3472,11 @@
25070 - /* Checked later */
25071 + /* Checked later. */
25075 - /* Update statistic */
25076 + /* Update statistics. */
25077 if (Id == OID_SKGE_RX_HW_ERROR_CTS ||
25078 Id == OID_SKGE_TX_HW_ERROR_CTS ||
25079 Id == OID_SKGE_IN_ERRORS_CTS ||
25080 @@ -3632,7 +3484,8 @@
25081 Id == OID_GEN_XMIT_ERROR ||
25082 Id == OID_GEN_RCV_ERROR) {
25084 - /* Force the XMAC to update its statistic counters and
25086 + * Force the XMAC to update its statistic counters and
25087 * Increment semaphore to indicate that an update was
25090 @@ -3663,14 +3516,29 @@
25091 GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_IRLENGTH, NetIndex) +
25092 GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_SYMBOL, NetIndex) +
25093 GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_SHORTS, NetIndex) +
25094 - GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_RUNT, NetIndex) +
25095 GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_TOO_LONG, NetIndex) +
25096 - GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_FCS, NetIndex) +
25097 GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_CEXT, NetIndex);
25100 - case OID_SKGE_TX_HW_ERROR_CTS:
25101 - case OID_SKGE_OUT_ERROR_CTS:
25104 + * In some cases the runt and fcs counters are incremented when collisions
25105 + * occur. We have to correct those counters here.
25107 + Val64RxRunt = GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_RUNT, NetIndex);
25108 + Val64RxFcs = GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_FCS, NetIndex);
25110 + if (Val64RxRunt > Val64RxFcs) {
25111 + Val64RxRunt -= Val64RxFcs;
25112 + Val64RxHwErrs += Val64RxRunt;
25115 + Val64RxFcs -= Val64RxRunt;
25116 + Val64RxHwErrs += Val64RxFcs;
25120 + case OID_SKGE_TX_HW_ERROR_CTS:
25121 + case OID_SKGE_OUT_ERROR_CTS:
25122 case OID_GEN_XMIT_ERROR:
25124 GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_EXCESS_COL, NetIndex) +
25125 @@ -3681,9 +3549,7 @@
25132 + /* Retrieve value. */
25135 case OID_SKGE_SUPPORTED_LIST:
25136 @@ -3693,11 +3559,11 @@
25138 return (SK_PNMI_ERR_TOO_SHORT);
25140 - for (Offset = 0, Index = 0; Offset < Len;
25141 - Offset += sizeof(SK_U32), Index ++) {
25142 + for (Offset = 0, Index = 0; Offset < Len; Index ++) {
25144 Val32 = (SK_U32)IdTable[Index].Id;
25145 SK_PNMI_STORE_U32(pBuf + Offset, Val32);
25146 + Offset += sizeof(SK_U32);
25150 @@ -3723,8 +3589,7 @@
25151 case OID_SKGE_DRIVER_DESCR:
25152 if (pAC->Pnmi.pDriverDescription == NULL) {
25154 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR007,
25155 - SK_PNMI_ERR007MSG);
25156 + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR007, SK_PNMI_ERR007MSG);
25159 return (SK_PNMI_ERR_GENERAL);
25160 @@ -3733,8 +3598,7 @@
25161 Len = SK_STRLEN(pAC->Pnmi.pDriverDescription) + 1;
25162 if (Len > SK_PNMI_STRINGLEN1) {
25164 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR029,
25165 - SK_PNMI_ERR029MSG);
25166 + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR029, SK_PNMI_ERR029MSG);
25169 return (SK_PNMI_ERR_GENERAL);
25170 @@ -3753,8 +3617,7 @@
25171 case OID_SKGE_DRIVER_VERSION:
25172 if (pAC->Pnmi.pDriverVersion == NULL) {
25174 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR030,
25175 - SK_PNMI_ERR030MSG);
25176 + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR030, SK_PNMI_ERR030MSG);
25179 return (SK_PNMI_ERR_GENERAL);
25180 @@ -3763,8 +3626,7 @@
25181 Len = SK_STRLEN(pAC->Pnmi.pDriverVersion) + 1;
25182 if (Len > SK_PNMI_STRINGLEN1) {
25184 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR031,
25185 - SK_PNMI_ERR031MSG);
25186 + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR031, SK_PNMI_ERR031MSG);
25189 return (SK_PNMI_ERR_GENERAL);
25190 @@ -3783,8 +3645,7 @@
25191 case OID_SKGE_DRIVER_RELDATE:
25192 if (pAC->Pnmi.pDriverReleaseDate == NULL) {
25194 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR030,
25195 - SK_PNMI_ERR053MSG);
25196 + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR053, SK_PNMI_ERR053MSG);
25199 return (SK_PNMI_ERR_GENERAL);
25200 @@ -3793,8 +3654,7 @@
25201 Len = SK_STRLEN(pAC->Pnmi.pDriverReleaseDate) + 1;
25202 if (Len > SK_PNMI_STRINGLEN1) {
25204 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR031,
25205 - SK_PNMI_ERR054MSG);
25206 + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR054, SK_PNMI_ERR054MSG);
25209 return (SK_PNMI_ERR_GENERAL);
25210 @@ -3813,8 +3673,7 @@
25211 case OID_SKGE_DRIVER_FILENAME:
25212 if (pAC->Pnmi.pDriverFileName == NULL) {
25214 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR030,
25215 - SK_PNMI_ERR055MSG);
25216 + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR055, SK_PNMI_ERR055MSG);
25219 return (SK_PNMI_ERR_GENERAL);
25220 @@ -3823,8 +3682,7 @@
25221 Len = SK_STRLEN(pAC->Pnmi.pDriverFileName) + 1;
25222 if (Len > SK_PNMI_STRINGLEN1) {
25224 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR031,
25225 - SK_PNMI_ERR056MSG);
25226 + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR056, SK_PNMI_ERR056MSG);
25229 return (SK_PNMI_ERR_GENERAL);
25230 @@ -3846,12 +3704,16 @@
25231 * query may move to the initialisation routine. But
25232 * the VPD data is cached and therefore a call here
25233 * will not make much difference.
25234 + * Please read comment in Vpd().
25236 + if (pAC->Pnmi.VpdKeyReadError == SK_TRUE) {
25237 + return (SK_PNMI_ERR_OK);
25241 if (VpdRead(pAC, IoC, VPD_NAME, Buf, (int *)&Len) > 0) {
25243 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR032,
25244 - SK_PNMI_ERR032MSG);
25245 + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR032, SK_PNMI_ERR032MSG);
25248 return (SK_PNMI_ERR_GENERAL);
25249 @@ -3859,8 +3721,7 @@
25251 if (Len > SK_PNMI_STRINGLEN1) {
25253 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR033,
25254 - SK_PNMI_ERR033MSG);
25255 + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR033, SK_PNMI_ERR033MSG);
25258 return (SK_PNMI_ERR_GENERAL);
25259 @@ -3876,7 +3737,6 @@
25262 case OID_SKGE_HW_VERSION:
25263 - /* Oh, I love to do some string manipulation */
25267 @@ -3885,9 +3745,9 @@
25268 Val8 = (SK_U8)pAC->GIni.GIPciHwRev;
25271 - pBuf[2] = (char)(0x30 | ((Val8 >> 4) & 0x0F));
25272 + pBuf[2] = (char)('0' | ((Val8 >> 4) & 0x0f));
25274 - pBuf[4] = (char)(0x30 | (Val8 & 0x0F));
25275 + pBuf[4] = (char)('0' | (Val8 & 0x0f));
25279 @@ -3910,12 +3770,12 @@
25282 case OID_SKGE_VAUXAVAIL:
25283 - *pBuf = (char) pAC->GIni.GIVauxAvail;
25284 + *pBuf = (char)pAC->GIni.GIVauxAvail;
25285 *pLen = sizeof(char);
25288 case OID_SKGE_BUS_TYPE:
25289 - *pBuf = (char) SK_PNMI_BUS_PCI;
25290 + *pBuf = (char)SK_PNMI_BUS_PCI;
25291 *pLen = sizeof(char);
25294 @@ -3964,31 +3824,31 @@
25297 case OID_SKGE_RLMT_MONITOR_NUMBER:
25298 -/* XXX Not yet implemented by RLMT therefore we return zero elements */
25299 + /* Not yet implemented by RLMT, therefore we return zero elements. */
25301 SK_PNMI_STORE_U32(pBuf, Val32);
25302 *pLen = sizeof(SK_U32);
25305 case OID_SKGE_TX_SW_QUEUE_LEN:
25306 - /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25307 + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25308 if (MacType == SK_MAC_XMAC) {
25309 - /* Dual net mode */
25310 + /* DualNet mode. */
25311 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25312 Val64 = pAC->Pnmi.BufPort[NetIndex].TxSwQueueLen;
25314 - /* Single net mode */
25315 + /* SingleNet mode. */
25317 Val64 = pAC->Pnmi.BufPort[0].TxSwQueueLen +
25318 pAC->Pnmi.BufPort[1].TxSwQueueLen;
25322 - /* Dual net mode */
25323 + /* DualNet mode. */
25324 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25325 Val64 = pAC->Pnmi.Port[NetIndex].TxSwQueueLen;
25327 - /* Single net mode */
25328 + /* SingleNet mode. */
25330 Val64 = pAC->Pnmi.Port[0].TxSwQueueLen +
25331 pAC->Pnmi.Port[1].TxSwQueueLen;
25332 @@ -4000,24 +3860,24 @@
25335 case OID_SKGE_TX_SW_QUEUE_MAX:
25336 - /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25337 + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25338 if (MacType == SK_MAC_XMAC) {
25339 - /* Dual net mode */
25340 + /* DualNet mode. */
25341 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25342 Val64 = pAC->Pnmi.BufPort[NetIndex].TxSwQueueMax;
25344 - /* Single net mode */
25345 + /* SingleNet mode. */
25347 Val64 = pAC->Pnmi.BufPort[0].TxSwQueueMax +
25348 pAC->Pnmi.BufPort[1].TxSwQueueMax;
25352 - /* Dual net mode */
25353 + /* DualNet mode. */
25354 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25355 Val64 = pAC->Pnmi.Port[NetIndex].TxSwQueueMax;
25357 - /* Single net mode */
25358 + /* SingleNet mode. */
25360 Val64 = pAC->Pnmi.Port[0].TxSwQueueMax +
25361 pAC->Pnmi.Port[1].TxSwQueueMax;
25362 @@ -4028,24 +3888,24 @@
25365 case OID_SKGE_TX_RETRY:
25366 - /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25367 + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25368 if (MacType == SK_MAC_XMAC) {
25369 - /* Dual net mode */
25370 + /* DualNet mode. */
25371 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25372 Val64 = pAC->Pnmi.BufPort[NetIndex].TxRetryCts;
25374 - /* Single net mode */
25375 + /* SingleNet mode. */
25377 Val64 = pAC->Pnmi.BufPort[0].TxRetryCts +
25378 pAC->Pnmi.BufPort[1].TxRetryCts;
25382 - /* Dual net mode */
25383 + /* DualNet mode. */
25384 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25385 Val64 = pAC->Pnmi.Port[NetIndex].TxRetryCts;
25387 - /* Single net mode */
25388 + /* SingleNet mode. */
25390 Val64 = pAC->Pnmi.Port[0].TxRetryCts +
25391 pAC->Pnmi.Port[1].TxRetryCts;
25392 @@ -4056,24 +3916,24 @@
25395 case OID_SKGE_RX_INTR_CTS:
25396 - /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25397 + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25398 if (MacType == SK_MAC_XMAC) {
25399 - /* Dual net mode */
25400 + /* DualNet mode. */
25401 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25402 Val64 = pAC->Pnmi.BufPort[NetIndex].RxIntrCts;
25404 - /* Single net mode */
25405 + /* SingleNet mode. */
25407 Val64 = pAC->Pnmi.BufPort[0].RxIntrCts +
25408 pAC->Pnmi.BufPort[1].RxIntrCts;
25412 - /* Dual net mode */
25413 + /* DualNet mode. */
25414 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25415 Val64 = pAC->Pnmi.Port[NetIndex].RxIntrCts;
25417 - /* Single net mode */
25418 + /* SingleNet mode. */
25420 Val64 = pAC->Pnmi.Port[0].RxIntrCts +
25421 pAC->Pnmi.Port[1].RxIntrCts;
25422 @@ -4084,24 +3944,24 @@
25425 case OID_SKGE_TX_INTR_CTS:
25426 - /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25427 + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25428 if (MacType == SK_MAC_XMAC) {
25429 - /* Dual net mode */
25430 + /* DualNet mode. */
25431 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25432 Val64 = pAC->Pnmi.BufPort[NetIndex].TxIntrCts;
25434 - /* Single net mode */
25435 + /* SingleNet mode. */
25437 Val64 = pAC->Pnmi.BufPort[0].TxIntrCts +
25438 pAC->Pnmi.BufPort[1].TxIntrCts;
25442 - /* Dual net mode */
25443 + /* DualNet mode. */
25444 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25445 Val64 = pAC->Pnmi.Port[NetIndex].TxIntrCts;
25447 - /* Single net mode */
25448 + /* SingleNet mode. */
25450 Val64 = pAC->Pnmi.Port[0].TxIntrCts +
25451 pAC->Pnmi.Port[1].TxIntrCts;
25452 @@ -4112,24 +3972,24 @@
25455 case OID_SKGE_RX_NO_BUF_CTS:
25456 - /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25457 + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25458 if (MacType == SK_MAC_XMAC) {
25459 - /* Dual net mode */
25460 + /* DualNet mode. */
25461 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25462 Val64 = pAC->Pnmi.BufPort[NetIndex].RxNoBufCts;
25464 - /* Single net mode */
25465 + /* SingleNet mode. */
25467 Val64 = pAC->Pnmi.BufPort[0].RxNoBufCts +
25468 pAC->Pnmi.BufPort[1].RxNoBufCts;
25472 - /* Dual net mode */
25473 + /* DualNet mode. */
25474 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25475 Val64 = pAC->Pnmi.Port[NetIndex].RxNoBufCts;
25477 - /* Single net mode */
25478 + /* SingleNet mode. */
25480 Val64 = pAC->Pnmi.Port[0].RxNoBufCts +
25481 pAC->Pnmi.Port[1].RxNoBufCts;
25482 @@ -4140,24 +4000,24 @@
25485 case OID_SKGE_TX_NO_BUF_CTS:
25486 - /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25487 + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25488 if (MacType == SK_MAC_XMAC) {
25489 - /* Dual net mode */
25490 + /* DualNet mode. */
25491 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25492 Val64 = pAC->Pnmi.BufPort[NetIndex].TxNoBufCts;
25494 - /* Single net mode */
25495 + /* SingleNet mode. */
25497 Val64 = pAC->Pnmi.BufPort[0].TxNoBufCts +
25498 pAC->Pnmi.BufPort[1].TxNoBufCts;
25502 - /* Dual net mode */
25503 + /* DualNet mode. */
25504 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25505 Val64 = pAC->Pnmi.Port[NetIndex].TxNoBufCts;
25507 - /* Single net mode */
25508 + /* SingleNet mode. */
25510 Val64 = pAC->Pnmi.Port[0].TxNoBufCts +
25511 pAC->Pnmi.Port[1].TxNoBufCts;
25512 @@ -4168,24 +4028,24 @@
25515 case OID_SKGE_TX_USED_DESCR_NO:
25516 - /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25517 + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25518 if (MacType == SK_MAC_XMAC) {
25519 - /* Dual net mode */
25520 + /* DualNet mode. */
25521 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25522 Val64 = pAC->Pnmi.BufPort[NetIndex].TxUsedDescrNo;
25524 - /* Single net mode */
25525 + /* SingleNet mode. */
25527 Val64 = pAC->Pnmi.BufPort[0].TxUsedDescrNo +
25528 pAC->Pnmi.BufPort[1].TxUsedDescrNo;
25532 - /* Dual net mode */
25533 + /* DualNet mode. */
25534 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25535 Val64 = pAC->Pnmi.Port[NetIndex].TxUsedDescrNo;
25537 - /* Single net mode */
25538 + /* SingleNet mode. */
25540 Val64 = pAC->Pnmi.Port[0].TxUsedDescrNo +
25541 pAC->Pnmi.Port[1].TxUsedDescrNo;
25542 @@ -4196,24 +4056,24 @@
25545 case OID_SKGE_RX_DELIVERED_CTS:
25546 - /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25547 + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25548 if (MacType == SK_MAC_XMAC) {
25549 - /* Dual net mode */
25550 + /* DualNet mode. */
25551 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25552 Val64 = pAC->Pnmi.BufPort[NetIndex].RxDeliveredCts;
25554 - /* Single net mode */
25555 + /* SingleNet mode. */
25557 Val64 = pAC->Pnmi.BufPort[0].RxDeliveredCts +
25558 pAC->Pnmi.BufPort[1].RxDeliveredCts;
25562 - /* Dual net mode */
25563 + /* DualNet mode. */
25564 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25565 Val64 = pAC->Pnmi.Port[NetIndex].RxDeliveredCts;
25567 - /* Single net mode */
25568 + /* SingleNet mode. */
25570 Val64 = pAC->Pnmi.Port[0].RxDeliveredCts +
25571 pAC->Pnmi.Port[1].RxDeliveredCts;
25572 @@ -4224,24 +4084,24 @@
25575 case OID_SKGE_RX_OCTETS_DELIV_CTS:
25576 - /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25577 + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25578 if (MacType == SK_MAC_XMAC) {
25579 - /* Dual net mode */
25580 + /* DualNet mode. */
25581 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25582 Val64 = pAC->Pnmi.BufPort[NetIndex].RxOctetsDeliveredCts;
25584 - /* Single net mode */
25585 + /* SingleNet mode. */
25587 Val64 = pAC->Pnmi.BufPort[0].RxOctetsDeliveredCts +
25588 pAC->Pnmi.BufPort[1].RxOctetsDeliveredCts;
25592 - /* Dual net mode */
25593 + /* DualNet mode. */
25594 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25595 Val64 = pAC->Pnmi.Port[NetIndex].RxOctetsDeliveredCts;
25597 - /* Single net mode */
25598 + /* SingleNet mode. */
25600 Val64 = pAC->Pnmi.Port[0].RxOctetsDeliveredCts +
25601 pAC->Pnmi.Port[1].RxOctetsDeliveredCts;
25602 @@ -4262,13 +4122,13 @@
25605 case OID_SKGE_IN_ERRORS_CTS:
25606 - /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25607 + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25608 if (MacType == SK_MAC_XMAC) {
25609 - /* Dual net mode */
25610 + /* DualNet mode. */
25611 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25612 Val64 = Val64RxHwErrs + pAC->Pnmi.BufPort[NetIndex].RxNoBufCts;
25614 - /* Single net mode */
25615 + /* SingleNet mode. */
25617 Val64 = Val64RxHwErrs +
25618 pAC->Pnmi.BufPort[0].RxNoBufCts +
25619 @@ -4276,11 +4136,11 @@
25623 - /* Dual net mode */
25624 + /* DualNet mode. */
25625 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25626 Val64 = Val64RxHwErrs + pAC->Pnmi.Port[NetIndex].RxNoBufCts;
25628 - /* Single net mode */
25629 + /* SingleNet mode. */
25631 Val64 = Val64RxHwErrs +
25632 pAC->Pnmi.Port[0].RxNoBufCts +
25633 @@ -4292,13 +4152,13 @@
25636 case OID_SKGE_OUT_ERROR_CTS:
25637 - /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25638 + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25639 if (MacType == SK_MAC_XMAC) {
25640 - /* Dual net mode */
25641 + /* DualNet mode. */
25642 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25643 Val64 = Val64TxHwErrs + pAC->Pnmi.BufPort[NetIndex].TxNoBufCts;
25645 - /* Single net mode */
25646 + /* SingleNet mode. */
25648 Val64 = Val64TxHwErrs +
25649 pAC->Pnmi.BufPort[0].TxNoBufCts +
25650 @@ -4306,11 +4166,11 @@
25654 - /* Dual net mode */
25655 + /* DualNet mode. */
25656 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25657 Val64 = Val64TxHwErrs + pAC->Pnmi.Port[NetIndex].TxNoBufCts;
25659 - /* Single net mode */
25660 + /* SingleNet mode. */
25662 Val64 = Val64TxHwErrs +
25663 pAC->Pnmi.Port[0].TxNoBufCts +
25664 @@ -4322,24 +4182,24 @@
25667 case OID_SKGE_ERR_RECOVERY_CTS:
25668 - /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25669 + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25670 if (MacType == SK_MAC_XMAC) {
25671 - /* Dual net mode */
25672 + /* DualNet mode. */
25673 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25674 Val64 = pAC->Pnmi.BufPort[NetIndex].ErrRecoveryCts;
25676 - /* Single net mode */
25677 + /* SingleNet mode. */
25679 Val64 = pAC->Pnmi.BufPort[0].ErrRecoveryCts +
25680 pAC->Pnmi.BufPort[1].ErrRecoveryCts;
25684 - /* Dual net mode */
25685 + /* DualNet mode. */
25686 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25687 Val64 = pAC->Pnmi.Port[NetIndex].ErrRecoveryCts;
25689 - /* Single net mode */
25690 + /* SingleNet mode. */
25692 Val64 = pAC->Pnmi.Port[0].ErrRecoveryCts +
25693 pAC->Pnmi.Port[1].ErrRecoveryCts;
25694 @@ -4363,7 +4223,7 @@
25697 case OID_GEN_RCV_ERROR:
25698 - /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25699 + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25700 if (MacType == SK_MAC_XMAC) {
25701 Val64 = Val64RxHwErrs + pAC->Pnmi.BufPort[NetIndex].RxNoBufCts;
25703 @@ -4372,7 +4232,7 @@
25707 - * by default 32bit values are evaluated
25708 + * By default 32bit values are evaluated.
25711 Val32 = (SK_U32)Val64;
25712 @@ -4386,7 +4246,7 @@
25715 case OID_GEN_XMIT_ERROR:
25716 - /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25717 + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25718 if (MacType == SK_MAC_XMAC) {
25719 Val64 = Val64TxHwErrs + pAC->Pnmi.BufPort[NetIndex].TxNoBufCts;
25721 @@ -4395,7 +4255,7 @@
25725 - * by default 32bit values are evaluated
25726 + * By default 32bit values are evaluated.
25729 Val32 = (SK_U32)Val64;
25730 @@ -4409,16 +4269,19 @@
25733 case OID_GEN_RCV_NO_BUFFER:
25734 - /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25735 + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25736 if (MacType == SK_MAC_XMAC) {
25737 - Val64 = pAC->Pnmi.BufPort[NetIndex].RxNoBufCts;
25738 + Val64 = pAC->Pnmi.BufPort[NetIndex].RxNoBufCts +
25739 + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_OVERFLOW, NetIndex);
25743 - Val64 = pAC->Pnmi.Port[NetIndex].RxNoBufCts;
25744 + Val64 = pAC->Pnmi.Port[NetIndex].RxNoBufCts +
25745 + GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_OVERFLOW, NetIndex);
25749 - * by default 32bit values are evaluated
25750 + * By default 32bit values are evaluated.
25753 Val32 = (SK_U32)Val64;
25754 @@ -4438,8 +4301,7 @@
25758 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR034,
25759 - SK_PNMI_ERR034MSG);
25760 + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR034, SK_PNMI_ERR034MSG);
25763 return (SK_PNMI_ERR_GENERAL);
25764 @@ -4496,25 +4358,17 @@
25770 - * Check instance. Only single instance OIDs are allowed here.
25772 + /* Check instance. Only single instance OIDs are allowed here. */
25773 if (Instance != (SK_U32)(-1) && Instance != 1) {
25776 return (SK_PNMI_ERR_UNKNOWN_INST);
25780 - * Perform the requested action.
25782 + /* Perform the requested action. */
25783 if (Action == SK_PNMI_GET) {
25786 - * Check if the buffer length is large enough.
25789 + /* Check if the buffer length is large enough. */
25792 case OID_SKGE_RLMT_MODE:
25793 @@ -4547,8 +4401,7 @@
25797 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR035,
25798 - SK_PNMI_ERR035MSG);
25799 + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR035, SK_PNMI_ERR035MSG);
25802 return (SK_PNMI_ERR_GENERAL);
25803 @@ -4567,9 +4420,7 @@
25805 pAC->Pnmi.RlmtUpdatedFlag ++;
25810 + /* Retrieve value. */
25813 case OID_SKGE_RLMT_MODE:
25814 @@ -4647,17 +4498,17 @@
25815 pAC->Pnmi.RlmtUpdatedFlag --;
25818 - /* Perform a preset or set */
25819 + /* Perform a PRESET or SET. */
25822 case OID_SKGE_RLMT_MODE:
25823 - /* Check if the buffer length is plausible */
25824 + /* Check if the buffer length is plausible. */
25825 if (*pLen < sizeof(char)) {
25827 *pLen = sizeof(char);
25828 return (SK_PNMI_ERR_TOO_SHORT);
25830 - /* Check if the value range is correct */
25831 + /* Check if the value range is correct. */
25832 if (*pLen != sizeof(char) ||
25833 (*pBuf & SK_PNMI_RLMT_MODE_CHK_LINK) == 0 ||
25834 *(SK_U8 *)pBuf > 15) {
25835 @@ -4665,21 +4516,21 @@
25837 return (SK_PNMI_ERR_BAD_VALUE);
25839 - /* The preset ends here */
25840 + /* The PRESET ends here. */
25841 if (Action == SK_PNMI_PRESET) {
25844 return (SK_PNMI_ERR_OK);
25846 - /* Send an event to RLMT to change the mode */
25847 + /* Send an event to RLMT to change the mode. */
25848 SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
25850 EventParam.Para32[0] |= (SK_U32)(*pBuf);
25851 EventParam.Para32[1] = 0;
25852 if (SkRlmtEvent(pAC, IoC, SK_RLMT_MODE_CHANGE,
25855 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR037,
25856 - SK_PNMI_ERR037MSG);
25857 + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR037, SK_PNMI_ERR037MSG);
25860 return (SK_PNMI_ERR_GENERAL);
25861 @@ -4687,20 +4538,25 @@
25864 case OID_SKGE_RLMT_PORT_PREFERRED:
25865 - /* Check if the buffer length is plausible */
25866 + /* PRESET/SET action makes no sense in Dual Net mode. */
25867 + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25871 + /* Check if the buffer length is plausible. */
25872 if (*pLen < sizeof(char)) {
25874 *pLen = sizeof(char);
25875 return (SK_PNMI_ERR_TOO_SHORT);
25877 - /* Check if the value range is correct */
25878 + /* Check if the value range is correct. */
25879 if (*pLen != sizeof(char) || *(SK_U8 *)pBuf >
25880 (SK_U8)pAC->GIni.GIMacsFound) {
25883 return (SK_PNMI_ERR_BAD_VALUE);
25885 - /* The preset ends here */
25886 + /* The PRESET ends here. */
25887 if (Action == SK_PNMI_PRESET) {
25890 @@ -4713,13 +4569,13 @@
25891 * make the decision which is the preferred port.
25893 SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
25895 EventParam.Para32[0] = (SK_U32)(*pBuf) - 1;
25896 EventParam.Para32[1] = NetIndex;
25897 if (SkRlmtEvent(pAC, IoC, SK_RLMT_PREFPORT_CHANGE,
25900 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR038,
25901 - SK_PNMI_ERR038MSG);
25902 + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR038, SK_PNMI_ERR038MSG);
25905 return (SK_PNMI_ERR_GENERAL);
25906 @@ -4727,22 +4583,20 @@
25909 case OID_SKGE_RLMT_CHANGE_THRES:
25910 - /* Check if the buffer length is plausible */
25911 + /* Check if the buffer length is plausible. */
25912 if (*pLen < sizeof(SK_U64)) {
25914 *pLen = sizeof(SK_U64);
25915 return (SK_PNMI_ERR_TOO_SHORT);
25918 - * There are not many restrictions to the
25922 + /* There are not many restrictions to the value range. */
25923 if (*pLen != sizeof(SK_U64)) {
25926 return (SK_PNMI_ERR_BAD_VALUE);
25928 - /* A preset ends here */
25929 + /* The PRESET ends here. */
25930 if (Action == SK_PNMI_PRESET) {
25933 @@ -4757,7 +4611,7 @@
25937 - /* The other OIDs are not be able for set */
25938 + /* The other OIDs are not be able for set. */
25940 return (SK_PNMI_ERR_READ_ONLY);
25942 @@ -4802,54 +4656,49 @@
25947 - * Calculate the port indexes from the instance.
25950 + /* Calculate the port indexes from the instance. */
25951 PhysPortMax = pAC->GIni.GIMacsFound;
25953 if ((Instance != (SK_U32)(-1))) {
25954 - /* Check instance range */
25955 + /* Check instance range. */
25956 if ((Instance < 1) || (Instance > PhysPortMax)) {
25959 return (SK_PNMI_ERR_UNKNOWN_INST);
25962 - /* Single net mode */
25963 + /* SingleNet mode. */
25964 PhysPortIndex = Instance - 1;
25966 - /* Dual net mode */
25967 + /* DualNet mode. */
25968 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25969 PhysPortIndex = NetIndex;
25972 - /* Both net modes */
25973 + /* Both net modes. */
25974 Limit = PhysPortIndex + 1;
25977 - /* Single net mode */
25978 + /* SingleNet mode. */
25980 Limit = PhysPortMax;
25982 - /* Dual net mode */
25983 + /* DualNet mode. */
25984 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25985 PhysPortIndex = NetIndex;
25986 Limit = PhysPortIndex + 1;
25991 - * Currently only get requests are allowed.
25993 + /* Currently only GET requests are allowed. */
25994 if (Action != SK_PNMI_GET) {
25997 return (SK_PNMI_ERR_READ_ONLY);
26001 - * Check if the buffer length is large enough.
26003 + /* Check if the buffer length is large enough. */
26006 case OID_SKGE_RLMT_PORT_INDEX:
26007 @@ -4873,8 +4722,7 @@
26011 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR039,
26012 - SK_PNMI_ERR039MSG);
26013 + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR039, SK_PNMI_ERR039MSG);
26016 return (SK_PNMI_ERR_GENERAL);
26017 @@ -4892,9 +4740,7 @@
26019 pAC->Pnmi.RlmtUpdatedFlag ++;
26026 for (; PhysPortIndex < Limit; PhysPortIndex ++) {
26028 @@ -5007,19 +4853,21 @@
26030 SK_EVPARA EventParam;
26032 +#ifdef SK_PHY_LP_MODE
26033 + SK_U8 CurrentPhyPowerState;
26034 +#endif /* SK_PHY_LP_MODE */
26037 - * Calculate instance if wished. MAC index 0 is the virtual MAC.
26040 + /* Calculate instance if wished. MAC index 0 is the virtual MAC. */
26041 PhysPortMax = pAC->GIni.GIMacsFound;
26042 LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax);
26044 - if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* Dual net mode */
26045 + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* DualNet mode. */
26049 - if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried */
26050 - /* Check instance range */
26051 + if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried. */
26052 + /* Check instance range. */
26053 if ((Instance < 1) || (Instance > LogPortMax)) {
26056 @@ -5029,18 +4877,16 @@
26057 Limit = LogPortIndex + 1;
26060 - else { /* Instance == (SK_U32)(-1), get all Instances of that OID */
26061 + else { /* Instance == (SK_U32)(-1), get all Instances of that OID. */
26064 Limit = LogPortMax;
26070 + /* Perform action. */
26071 if (Action == SK_PNMI_GET) {
26073 - /* Check length */
26074 + /* Check length. */
26078 @@ -5058,6 +4904,9 @@
26079 case OID_SKGE_SPEED_CAP:
26080 case OID_SKGE_SPEED_MODE:
26081 case OID_SKGE_SPEED_STATUS:
26082 +#ifdef SK_PHY_LP_MODE
26083 + case OID_SKGE_PHY_LP_MODE:
26085 if (*pLen < (Limit - LogPortIndex) * sizeof(SK_U8)) {
26087 *pLen = (Limit - LogPortIndex) * sizeof(SK_U8);
26088 @@ -5075,8 +4924,7 @@
26092 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR041,
26093 - SK_PNMI_ERR041MSG);
26094 + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR041, SK_PNMI_ERR041MSG);
26096 return (SK_PNMI_ERR_GENERAL);
26098 @@ -5092,9 +4940,7 @@
26100 pAC->Pnmi.SirqUpdatedFlag ++;
26107 for (; LogPortIndex < Limit; LogPortIndex ++) {
26109 @@ -5104,85 +4950,99 @@
26112 *pBufPtr = pAC->Pnmi.PMD;
26113 - Offset += sizeof(char);
26117 case OID_SKGE_CONNECTOR:
26118 *pBufPtr = pAC->Pnmi.Connector;
26119 - Offset += sizeof(char);
26123 case OID_SKGE_PHY_TYPE:
26124 - if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26125 + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26126 if (LogPortIndex == 0) {
26130 - /* Get value for physical ports */
26131 - PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26132 - pAC, LogPortIndex);
26133 - Val32 = pAC->GIni.GP[PhysPortIndex].PhyType;
26134 - SK_PNMI_STORE_U32(pBufPtr, Val32);
26136 + /* Get value for physical port. */
26137 + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);
26138 + Val32 = pAC->GIni.GP[PhysPortIndex].PhyType;
26140 - else { /* DualNetMode */
26141 + else { /* DualNet mode. */
26143 Val32 = pAC->GIni.GP[NetIndex].PhyType;
26144 - SK_PNMI_STORE_U32(pBufPtr, Val32);
26146 + SK_PNMI_STORE_U32(pBufPtr, Val32);
26147 Offset += sizeof(SK_U32);
26150 +#ifdef SK_PHY_LP_MODE
26151 + case OID_SKGE_PHY_LP_MODE:
26152 + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26153 + if (LogPortIndex == 0) {
26156 + /* Get value for physical port. */
26157 + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);
26158 + *pBufPtr = (SK_U8)pAC->GIni.GP[PhysPortIndex].PPhyPowerState;
26160 + else { /* DualNet mode. */
26162 + *pBufPtr = (SK_U8)pAC->GIni.GP[NetIndex].PPhyPowerState;
26164 + Offset += sizeof(SK_U8);
26168 case OID_SKGE_LINK_CAP:
26169 - if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26170 + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26171 if (LogPortIndex == 0) {
26172 - /* Get value for virtual port */
26173 + /* Get value for virtual port. */
26174 VirtualConf(pAC, IoC, Id, pBufPtr);
26177 - /* Get value for physical ports */
26178 + /* Get value for physical port. */
26179 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26180 pAC, LogPortIndex);
26182 *pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkCap;
26185 - else { /* DualNetMode */
26186 + else { /* DualNet mode. */
26188 *pBufPtr = pAC->GIni.GP[NetIndex].PLinkCap;
26190 - Offset += sizeof(char);
26194 case OID_SKGE_LINK_MODE:
26195 - if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26196 + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26197 if (LogPortIndex == 0) {
26198 - /* Get value for virtual port */
26199 + /* Get value for virtual port. */
26200 VirtualConf(pAC, IoC, Id, pBufPtr);
26203 - /* Get value for physical ports */
26204 + /* Get value for physical port. */
26205 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26206 pAC, LogPortIndex);
26208 *pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkModeConf;
26211 - else { /* DualNetMode */
26212 + else { /* DualNet mode. */
26214 *pBufPtr = pAC->GIni.GP[NetIndex].PLinkModeConf;
26216 - Offset += sizeof(char);
26220 case OID_SKGE_LINK_MODE_STATUS:
26221 - if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26222 + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26223 if (LogPortIndex == 0) {
26224 - /* Get value for virtual port */
26225 + /* Get value for virtual port. */
26226 VirtualConf(pAC, IoC, Id, pBufPtr);
26229 - /* Get value for physical port */
26230 + /* Get value for physical port. */
26231 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26232 pAC, LogPortIndex);
26234 @@ -5190,147 +5050,147 @@
26235 CalculateLinkModeStatus(pAC, IoC, PhysPortIndex);
26238 - else { /* DualNetMode */
26239 + else { /* DualNet mode. */
26241 *pBufPtr = CalculateLinkModeStatus(pAC, IoC, NetIndex);
26243 - Offset += sizeof(char);
26247 case OID_SKGE_LINK_STATUS:
26248 - if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26249 + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26250 if (LogPortIndex == 0) {
26251 - /* Get value for virtual port */
26252 + /* Get value for virtual port. */
26253 VirtualConf(pAC, IoC, Id, pBufPtr);
26256 - /* Get value for physical ports */
26257 + /* Get value for physical port. */
26258 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26259 pAC, LogPortIndex);
26261 *pBufPtr = CalculateLinkStatus(pAC, IoC, PhysPortIndex);
26264 - else { /* DualNetMode */
26265 + else { /* DualNet mode. */
26267 *pBufPtr = CalculateLinkStatus(pAC, IoC, NetIndex);
26269 - Offset += sizeof(char);
26273 case OID_SKGE_FLOWCTRL_CAP:
26274 - if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26275 + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26276 if (LogPortIndex == 0) {
26277 - /* Get value for virtual port */
26278 + /* Get value for virtual port. */
26279 VirtualConf(pAC, IoC, Id, pBufPtr);
26282 - /* Get value for physical ports */
26283 + /* Get value for physical port. */
26284 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26285 pAC, LogPortIndex);
26287 *pBufPtr = pAC->GIni.GP[PhysPortIndex].PFlowCtrlCap;
26290 - else { /* DualNetMode */
26291 + else { /* DualNet mode. */
26293 *pBufPtr = pAC->GIni.GP[NetIndex].PFlowCtrlCap;
26295 - Offset += sizeof(char);
26299 case OID_SKGE_FLOWCTRL_MODE:
26300 - if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26301 + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26302 if (LogPortIndex == 0) {
26303 - /* Get value for virtual port */
26304 + /* Get value for virtual port. */
26305 VirtualConf(pAC, IoC, Id, pBufPtr);
26308 - /* Get value for physical port */
26309 + /* Get value for physical port. */
26310 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26311 pAC, LogPortIndex);
26313 *pBufPtr = pAC->GIni.GP[PhysPortIndex].PFlowCtrlMode;
26316 - else { /* DualNetMode */
26317 + else { /* DualNet mode. */
26319 *pBufPtr = pAC->GIni.GP[NetIndex].PFlowCtrlMode;
26321 - Offset += sizeof(char);
26325 case OID_SKGE_FLOWCTRL_STATUS:
26326 - if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26327 + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26328 if (LogPortIndex == 0) {
26329 - /* Get value for virtual port */
26330 + /* Get value for virtual port. */
26331 VirtualConf(pAC, IoC, Id, pBufPtr);
26334 - /* Get value for physical port */
26335 + /* Get value for physical port. */
26336 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26337 pAC, LogPortIndex);
26339 *pBufPtr = pAC->GIni.GP[PhysPortIndex].PFlowCtrlStatus;
26342 - else { /* DualNetMode */
26343 + else { /* DualNet mode. */
26345 *pBufPtr = pAC->GIni.GP[NetIndex].PFlowCtrlStatus;
26347 - Offset += sizeof(char);
26351 case OID_SKGE_PHY_OPERATION_CAP:
26352 - if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26353 + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet Mode. */
26354 if (LogPortIndex == 0) {
26355 - /* Get value for virtual port */
26356 + /* Get value for virtual port. */
26357 VirtualConf(pAC, IoC, Id, pBufPtr);
26360 - /* Get value for physical ports */
26361 + /* Get value for physical port. */
26362 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26363 pAC, LogPortIndex);
26365 *pBufPtr = pAC->GIni.GP[PhysPortIndex].PMSCap;
26368 - else { /* DualNetMode */
26369 + else { /* DualNet mode. */
26371 *pBufPtr = pAC->GIni.GP[NetIndex].PMSCap;
26373 - Offset += sizeof(char);
26377 case OID_SKGE_PHY_OPERATION_MODE:
26378 - if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26379 + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26380 if (LogPortIndex == 0) {
26381 - /* Get value for virtual port */
26382 + /* Get value for virtual port. */
26383 VirtualConf(pAC, IoC, Id, pBufPtr);
26386 - /* Get value for physical port */
26387 + /* Get value for physical port. */
26388 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26389 pAC, LogPortIndex);
26391 *pBufPtr = pAC->GIni.GP[PhysPortIndex].PMSMode;
26394 - else { /* DualNetMode */
26395 + else { /* DualNet mode. */
26397 *pBufPtr = pAC->GIni.GP[NetIndex].PMSMode;
26399 - Offset += sizeof(char);
26403 case OID_SKGE_PHY_OPERATION_STATUS:
26404 - if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26405 + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26406 if (LogPortIndex == 0) {
26407 - /* Get value for virtual port */
26408 + /* Get value for virtual port. */
26409 VirtualConf(pAC, IoC, Id, pBufPtr);
26412 - /* Get value for physical port */
26413 + /* Get value for physical port. */
26414 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26415 pAC, LogPortIndex);
26417 @@ -5341,70 +5201,70 @@
26419 *pBufPtr = pAC->GIni.GP[NetIndex].PMSStatus;
26421 - Offset += sizeof(char);
26425 case OID_SKGE_SPEED_CAP:
26426 - if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26427 + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26428 if (LogPortIndex == 0) {
26429 - /* Get value for virtual port */
26430 + /* Get value for virtual port. */
26431 VirtualConf(pAC, IoC, Id, pBufPtr);
26434 - /* Get value for physical ports */
26435 + /* Get value for physical port. */
26436 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26437 pAC, LogPortIndex);
26439 *pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkSpeedCap;
26442 - else { /* DualNetMode */
26443 + else { /* DualNet mode. */
26445 *pBufPtr = pAC->GIni.GP[NetIndex].PLinkSpeedCap;
26447 - Offset += sizeof(char);
26451 case OID_SKGE_SPEED_MODE:
26452 - if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26453 + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26454 if (LogPortIndex == 0) {
26455 - /* Get value for virtual port */
26456 + /* Get value for virtual port. */
26457 VirtualConf(pAC, IoC, Id, pBufPtr);
26460 - /* Get value for physical port */
26461 + /* Get value for physical port. */
26462 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26463 pAC, LogPortIndex);
26465 *pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkSpeed;
26468 - else { /* DualNetMode */
26469 + else { /* DualNet mode. */
26471 *pBufPtr = pAC->GIni.GP[NetIndex].PLinkSpeed;
26473 - Offset += sizeof(char);
26477 case OID_SKGE_SPEED_STATUS:
26478 - if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26479 + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26480 if (LogPortIndex == 0) {
26481 - /* Get value for virtual port */
26482 + /* Get value for virtual port. */
26483 VirtualConf(pAC, IoC, Id, pBufPtr);
26486 - /* Get value for physical port */
26487 + /* Get value for physical port. */
26488 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26489 pAC, LogPortIndex);
26491 *pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkSpeedUsed;
26494 - else { /* DualNetMode */
26495 + else { /* DualNet mode. */
26497 *pBufPtr = pAC->GIni.GP[NetIndex].PLinkSpeedUsed;
26499 - Offset += sizeof(char);
26504 @@ -5449,38 +5309,41 @@
26508 - case OID_SKGE_MTU:
26509 - if (*pLen < sizeof(SK_U32)) {
26510 +#ifdef SK_PHY_LP_MODE
26511 + case OID_SKGE_PHY_LP_MODE:
26512 + if (*pLen < Limit - LogPortIndex) {
26514 - *pLen = sizeof(SK_U32);
26515 + *pLen = Limit - LogPortIndex;
26516 return (SK_PNMI_ERR_TOO_SHORT);
26518 - if (*pLen != sizeof(SK_U32)) {
26520 +#endif /* SK_PHY_LP_MODE */
26523 - return (SK_PNMI_ERR_BAD_VALUE);
26524 + case OID_SKGE_MTU:
26525 + if (*pLen < (Limit - LogPortIndex) * sizeof(SK_U32)) {
26527 + *pLen = (Limit - LogPortIndex) * sizeof(SK_U32);
26528 + return (SK_PNMI_ERR_TOO_SHORT);
26535 return (SK_PNMI_ERR_READ_ONLY);
26539 - * Perform preset or set
26541 + /* Perform PRESET or SET. */
26543 for (; LogPortIndex < Limit; LogPortIndex ++) {
26545 + Val8 = *(pBuf + Offset);
26549 case OID_SKGE_LINK_MODE:
26550 - /* Check the value range */
26551 - Val8 = *(pBuf + Offset);
26552 + /* Check the value range. */
26555 - Offset += sizeof(char);
26559 if (Val8 < SK_LMODE_HALF ||
26560 @@ -5491,51 +5354,68 @@
26561 return (SK_PNMI_ERR_BAD_VALUE);
26564 - /* The preset ends here */
26565 + /* The PRESET ends here. */
26566 if (Action == SK_PNMI_PRESET) {
26568 return (SK_PNMI_ERR_OK);
26571 - if (LogPortIndex == 0) {
26574 - * The virtual port consists of all currently
26575 - * active ports. Find them and send an event
26576 - * with the new link mode to SIRQ.
26578 - for (PhysPortIndex = 0;
26579 - PhysPortIndex < PhysPortMax;
26580 - PhysPortIndex ++) {
26582 - if (!pAC->Pnmi.Port[PhysPortIndex].
26587 + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26588 + if (LogPortIndex == 0) {
26590 + * The virtual port consists of all currently
26591 + * active ports. Find them and send an event
26592 + * with the new link mode to SIRQ.
26594 + for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;
26595 + PhysPortIndex ++) {
26597 - EventParam.Para32[0] = PhysPortIndex;
26598 + if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
26602 + EventParam.Para32[0] = PhysPortIndex;
26603 + EventParam.Para32[1] = (SK_U32)Val8;
26604 + if (SkGeSirqEvent(pAC, IoC,
26605 + SK_HWEV_SET_LMODE,
26606 + EventParam) > 0) {
26608 + SK_ERR_LOG(pAC, SK_ERRCL_SW,
26610 + SK_PNMI_ERR043MSG);
26613 + return (SK_PNMI_ERR_GENERAL);
26619 + * Send an event with the new link mode to
26620 + * the SIRQ module.
26622 + EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
26623 + pAC, LogPortIndex);
26624 EventParam.Para32[1] = (SK_U32)Val8;
26625 - if (SkGeSirqEvent(pAC, IoC,
26626 - SK_HWEV_SET_LMODE,
26627 + if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_LMODE,
26631 SK_ERR_LOG(pAC, SK_ERRCL_SW,
26633 SK_PNMI_ERR043MSG);
26637 return (SK_PNMI_ERR_GENERAL);
26642 + else { /* DualNet mode. */
26645 * Send an event with the new link mode to
26648 - EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
26649 - pAC, LogPortIndex);
26650 + EventParam.Para32[0] = NetIndex;
26651 EventParam.Para32[1] = (SK_U32)Val8;
26652 if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_LMODE,
26654 @@ -5548,15 +5428,13 @@
26655 return (SK_PNMI_ERR_GENERAL);
26658 - Offset += sizeof(char);
26662 case OID_SKGE_FLOWCTRL_MODE:
26663 - /* Check the value range */
26664 - Val8 = *(pBuf + Offset);
26665 + /* Check the value range. */
26668 - Offset += sizeof(char);
26672 if (Val8 < SK_FLOW_MODE_NONE ||
26673 @@ -5567,30 +5445,48 @@
26674 return (SK_PNMI_ERR_BAD_VALUE);
26677 - /* The preset ends here */
26678 + /* The PRESET ends here. */
26679 if (Action == SK_PNMI_PRESET) {
26681 return (SK_PNMI_ERR_OK);
26684 - if (LogPortIndex == 0) {
26685 + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26686 + if (LogPortIndex == 0) {
26688 + * The virtual port consists of all currently
26689 + * active ports. Find them and send an event
26690 + * with the new flow control mode to SIRQ.
26692 + for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;
26693 + PhysPortIndex ++) {
26696 - * The virtual port consists of all currently
26697 - * active ports. Find them and send an event
26698 - * with the new flow control mode to SIRQ.
26700 - for (PhysPortIndex = 0;
26701 - PhysPortIndex < PhysPortMax;
26702 - PhysPortIndex ++) {
26703 + if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
26707 - if (!pAC->Pnmi.Port[PhysPortIndex].
26709 + EventParam.Para32[0] = PhysPortIndex;
26710 + EventParam.Para32[1] = (SK_U32)Val8;
26711 + if (SkGeSirqEvent(pAC, IoC,
26712 + SK_HWEV_SET_FLOWMODE,
26713 + EventParam) > 0) {
26715 + SK_ERR_LOG(pAC, SK_ERRCL_SW,
26717 + SK_PNMI_ERR044MSG);
26721 + return (SK_PNMI_ERR_GENERAL);
26725 - EventParam.Para32[0] = PhysPortIndex;
26729 + * Send an event with the new flow control
26730 + * mode to the SIRQ module.
26732 + EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
26733 + pAC, LogPortIndex);
26734 EventParam.Para32[1] = (SK_U32)Val8;
26735 if (SkGeSirqEvent(pAC, IoC,
26736 SK_HWEV_SET_FLOWMODE,
26737 @@ -5605,17 +5501,16 @@
26742 + else { /* DualNet mode. */
26745 - * Send an event with the new flow control
26746 - * mode to the SIRQ module.
26747 + * Send an event with the new link mode to
26748 + * the SIRQ module.
26750 - EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
26751 - pAC, LogPortIndex);
26752 + EventParam.Para32[0] = NetIndex;
26753 EventParam.Para32[1] = (SK_U32)Val8;
26754 - if (SkGeSirqEvent(pAC, IoC,
26755 - SK_HWEV_SET_FLOWMODE, EventParam)
26757 + if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_FLOWMODE,
26758 + EventParam) > 0) {
26760 SK_ERR_LOG(pAC, SK_ERRCL_SW,
26762 @@ -5625,15 +5520,14 @@
26763 return (SK_PNMI_ERR_GENERAL);
26766 - Offset += sizeof(char);
26770 case OID_SKGE_PHY_OPERATION_MODE :
26771 - /* Check the value range */
26772 - Val8 = *(pBuf + Offset);
26773 + /* Check the value range. */
26775 - /* mode of this port remains unchanged */
26776 - Offset += sizeof(char);
26777 + /* Mode of this port remains unchanged. */
26781 if (Val8 < SK_MS_MODE_AUTO ||
26782 @@ -5644,34 +5538,51 @@
26783 return (SK_PNMI_ERR_BAD_VALUE);
26786 - /* The preset ends here */
26787 + /* The PRESET ends here. */
26788 if (Action == SK_PNMI_PRESET) {
26790 return (SK_PNMI_ERR_OK);
26793 - if (LogPortIndex == 0) {
26794 + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26795 + if (LogPortIndex == 0) {
26797 + * The virtual port consists of all currently
26798 + * active ports. Find them and send an event
26799 + * with new master/slave (role) mode to SIRQ.
26801 + for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;
26802 + PhysPortIndex ++) {
26805 - * The virtual port consists of all currently
26806 - * active ports. Find them and send an event
26807 - * with new master/slave (role) mode to SIRQ.
26809 - for (PhysPortIndex = 0;
26810 - PhysPortIndex < PhysPortMax;
26811 - PhysPortIndex ++) {
26812 + if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
26816 - if (!pAC->Pnmi.Port[PhysPortIndex].
26818 + EventParam.Para32[0] = PhysPortIndex;
26819 + EventParam.Para32[1] = (SK_U32)Val8;
26820 + if (SkGeSirqEvent(pAC, IoC,
26821 + SK_HWEV_SET_ROLE,
26822 + EventParam) > 0) {
26824 + SK_ERR_LOG(pAC, SK_ERRCL_SW,
26826 + SK_PNMI_ERR042MSG);
26830 + return (SK_PNMI_ERR_GENERAL);
26834 - EventParam.Para32[0] = PhysPortIndex;
26838 + * Send an event with the new master/slave
26839 + * (role) mode to the SIRQ module.
26841 + EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
26842 + pAC, LogPortIndex);
26843 EventParam.Para32[1] = (SK_U32)Val8;
26844 if (SkGeSirqEvent(pAC, IoC,
26845 - SK_HWEV_SET_ROLE,
26846 - EventParam) > 0) {
26847 + SK_HWEV_SET_ROLE, EventParam) > 0) {
26849 SK_ERR_LOG(pAC, SK_ERRCL_SW,
26851 @@ -5682,16 +5593,16 @@
26856 + else { /* DualNet mode. */
26859 - * Send an event with the new master/slave
26860 - * (role) mode to the SIRQ module.
26861 + * Send an event with the new link mode to
26862 + * the SIRQ module.
26864 - EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
26865 - pAC, LogPortIndex);
26866 + EventParam.Para32[0] = NetIndex;
26867 EventParam.Para32[1] = (SK_U32)Val8;
26868 - if (SkGeSirqEvent(pAC, IoC,
26869 - SK_HWEV_SET_ROLE, EventParam) > 0) {
26870 + if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_ROLE,
26871 + EventParam) > 0) {
26873 SK_ERR_LOG(pAC, SK_ERRCL_SW,
26875 @@ -5701,16 +5612,13 @@
26876 return (SK_PNMI_ERR_GENERAL);
26880 - Offset += sizeof(char);
26884 case OID_SKGE_SPEED_MODE:
26885 - /* Check the value range */
26886 - Val8 = *(pBuf + Offset);
26887 + /* Check the value range. */
26890 - Offset += sizeof(char);
26894 if (Val8 < (SK_LSPEED_AUTO) ||
26895 @@ -5721,29 +5629,49 @@
26896 return (SK_PNMI_ERR_BAD_VALUE);
26899 - /* The preset ends here */
26900 + /* The PRESET ends here. */
26901 if (Action == SK_PNMI_PRESET) {
26903 return (SK_PNMI_ERR_OK);
26906 - if (LogPortIndex == 0) {
26907 + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26908 + if (LogPortIndex == 0) {
26911 - * The virtual port consists of all currently
26912 - * active ports. Find them and send an event
26913 - * with the new flow control mode to SIRQ.
26915 - for (PhysPortIndex = 0;
26916 - PhysPortIndex < PhysPortMax;
26917 - PhysPortIndex ++) {
26919 + * The virtual port consists of all currently
26920 + * active ports. Find them and send an event
26921 + * with the new flow control mode to SIRQ.
26923 + for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;
26924 + PhysPortIndex ++) {
26926 - if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
26927 + if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
26933 + EventParam.Para32[0] = PhysPortIndex;
26934 + EventParam.Para32[1] = (SK_U32)Val8;
26935 + if (SkGeSirqEvent(pAC, IoC,
26936 + SK_HWEV_SET_SPEED,
26937 + EventParam) > 0) {
26939 + SK_ERR_LOG(pAC, SK_ERRCL_SW,
26941 + SK_PNMI_ERR045MSG);
26943 - EventParam.Para32[0] = PhysPortIndex;
26945 + return (SK_PNMI_ERR_GENERAL);
26951 + * Send an event with the new flow control
26952 + * mode to the SIRQ module.
26954 + EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
26955 + pAC, LogPortIndex);
26956 EventParam.Para32[1] = (SK_U32)Val8;
26957 if (SkGeSirqEvent(pAC, IoC,
26959 @@ -5758,16 +5686,15 @@
26964 + else { /* DualNet mode. */
26967 - * Send an event with the new flow control
26968 - * mode to the SIRQ module.
26969 + * Send an event with the new link mode to
26970 + * the SIRQ module.
26972 - EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
26973 - pAC, LogPortIndex);
26974 + EventParam.Para32[0] = NetIndex;
26975 EventParam.Para32[1] = (SK_U32)Val8;
26976 - if (SkGeSirqEvent(pAC, IoC,
26977 - SK_HWEV_SET_SPEED,
26978 + if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_SPEED,
26981 SK_ERR_LOG(pAC, SK_ERRCL_SW,
26982 @@ -5778,23 +5705,25 @@
26983 return (SK_PNMI_ERR_GENERAL);
26986 - Offset += sizeof(char);
26990 - case OID_SKGE_MTU :
26991 - /* Check the value range */
26992 - Val32 = *(SK_U32*)(pBuf + Offset);
26993 + case OID_SKGE_MTU:
26994 + /* Check the value range. */
26995 + SK_PNMI_READ_U32((pBuf + Offset), Val32);
26998 - /* mtu of this port remains unchanged */
26999 + /* MTU of this port remains unchanged. */
27000 Offset += sizeof(SK_U32);
27004 if (SK_DRIVER_PRESET_MTU(pAC, IoC, NetIndex, Val32) != 0) {
27006 return (SK_PNMI_ERR_BAD_VALUE);
27009 - /* The preset ends here */
27010 + /* The PRESET ends here. */
27011 if (Action == SK_PNMI_PRESET) {
27012 return (SK_PNMI_ERR_OK);
27014 @@ -5805,7 +5734,70 @@
27016 Offset += sizeof(SK_U32);
27020 +#ifdef SK_PHY_LP_MODE
27021 + case OID_SKGE_PHY_LP_MODE:
27022 + /* The PRESET ends here. */
27023 + if (Action == SK_PNMI_PRESET) {
27025 + return (SK_PNMI_ERR_OK);
27028 + if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
27029 + if (LogPortIndex == 0) {
27034 + /* Set value for physical port. */
27035 + PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);
27036 + CurrentPhyPowerState = pAC->GIni.GP[PhysPortIndex].PPhyPowerState;
27039 + case PHY_PM_OPERATIONAL_MODE:
27040 + /* If LowPowerMode is active, we can leave it. */
27041 + if (CurrentPhyPowerState) {
27043 + Val32 = SkGmLeaveLowPowerMode(pAC, IoC, PhysPortIndex);
27045 + if ((CurrentPhyPowerState == PHY_PM_DEEP_SLEEP) ||
27046 + (CurrentPhyPowerState == PHY_PM_IEEE_POWER_DOWN)) {
27048 + SkDrvInitAdapter(pAC);
27054 + return (SK_PNMI_ERR_GENERAL);
27056 + case PHY_PM_DEEP_SLEEP:
27057 + case PHY_PM_IEEE_POWER_DOWN:
27058 + /* If no LowPowerMode is active, we can enter it. */
27059 + if (!CurrentPhyPowerState) {
27060 + SkDrvDeInitAdapter(pAC);
27063 + case PHY_PM_ENERGY_DETECT:
27064 + case PHY_PM_ENERGY_DETECT_PLUS:
27065 + /* If no LowPowerMode is active, we can enter it. */
27066 + if (!CurrentPhyPowerState) {
27068 + Val32 = SkGmEnterLowPowerMode(pAC, IoC, PhysPortIndex, *pBuf);
27073 + return (SK_PNMI_ERR_GENERAL);
27077 + return (SK_PNMI_ERR_BAD_VALUE);
27081 +#endif /* SK_PHY_LP_MODE */
27084 SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR,
27085 ("MacPrivateConf: Unknown OID should be handled before set"));
27086 @@ -5854,14 +5846,11 @@
27087 unsigned int Limit;
27088 unsigned int Offset;
27089 unsigned int Entries;
27093 - * Calculate instance if wished.
27095 - /* XXX Not yet implemented. Return always an empty table. */
27096 + /* Not implemented yet. Return always an empty table. */
27099 + /* Calculate instance if wished. */
27100 if ((Instance != (SK_U32)(-1))) {
27102 if ((Instance < 1) || (Instance > Entries)) {
27103 @@ -5878,12 +5867,10 @@
27110 + /* GET/SET value. */
27111 if (Action == SK_PNMI_GET) {
27113 - for (Offset=0; Index < Limit; Index ++) {
27114 + for (Offset = 0; Index < Limit; Index ++) {
27118 @@ -5905,32 +5892,29 @@
27122 - /* Only MONITOR_ADMIN can be set */
27123 + /* Only MONITOR_ADMIN can be set. */
27124 if (Id != OID_SKGE_RLMT_MONITOR_ADMIN) {
27127 return (SK_PNMI_ERR_READ_ONLY);
27130 - /* Check if the length is plausible */
27131 + /* Check if the length is plausible. */
27132 if (*pLen < (Limit - Index)) {
27134 return (SK_PNMI_ERR_TOO_SHORT);
27136 - /* Okay, we have a wide value range */
27137 + /* Okay, we have a wide value range. */
27138 if (*pLen != (Limit - Index)) {
27141 return (SK_PNMI_ERR_BAD_VALUE);
27144 - for (Offset=0; Index < Limit; Index ++) {
27148 - * XXX Not yet implemented. Return always BAD_VALUE, because the table
27153 + * Not yet implemented. Return always BAD_VALUE,
27154 + * because the table is empty.
27157 return (SK_PNMI_ERR_BAD_VALUE);
27159 @@ -5971,14 +5955,12 @@
27160 PortActiveFlag = SK_FALSE;
27161 PhysPortMax = pAC->GIni.GIMacsFound;
27163 - for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;
27164 - PhysPortIndex ++) {
27165 + for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax; PhysPortIndex ++) {
27167 pPrt = &pAC->GIni.GP[PhysPortIndex];
27169 - /* Check if the physical port is active */
27170 + /* Check if the physical port is active. */
27171 if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
27176 @@ -5987,12 +5969,13 @@
27179 case OID_SKGE_PHY_TYPE:
27180 - /* Check if it is the first active port */
27181 + /* Check if it is the first active port. */
27183 Val32 = pPrt->PhyType;
27184 SK_PNMI_STORE_U32(pBuf, Val32);
27189 case OID_SKGE_LINK_CAP:
27191 @@ -6006,7 +5989,7 @@
27194 case OID_SKGE_LINK_MODE:
27195 - /* Check if it is the first active port */
27196 + /* Check if it is the first active port. */
27199 *pBuf = pPrt->PLinkModeConf;
27200 @@ -6014,9 +5997,8 @@
27204 - * If we find an active port with a different link
27205 - * mode than the first one we return a value that
27206 - * indicates that the link mode is indeterminated.
27207 + * If we find an active port with a different link mode
27208 + * than the first one we return indeterminated.
27210 if (*pBuf != pPrt->PLinkModeConf) {
27212 @@ -6025,10 +6007,10 @@
27215 case OID_SKGE_LINK_MODE_STATUS:
27216 - /* Get the link mode of the physical port */
27217 + /* Get the link mode of the physical port. */
27218 Val8 = CalculateLinkModeStatus(pAC, IoC, PhysPortIndex);
27220 - /* Check if it is the first active port */
27221 + /* Check if it is the first active port. */
27225 @@ -6036,10 +6018,8 @@
27229 - * If we find an active port with a different link
27230 - * mode status than the first one we return a value
27231 - * that indicates that the link mode status is
27232 - * indeterminated.
27233 + * If we find an active port with a different link mode status
27234 + * than the first one we return indeterminated.
27236 if (*pBuf != Val8) {
27238 @@ -6048,10 +6028,10 @@
27241 case OID_SKGE_LINK_STATUS:
27242 - /* Get the link status of the physical port */
27243 + /* Get the link status of the physical port. */
27244 Val8 = CalculateLinkStatus(pAC, IoC, PhysPortIndex);
27246 - /* Check if it is the first active port */
27247 + /* Check if it is the first active port. */
27251 @@ -6059,10 +6039,8 @@
27255 - * If we find an active port with a different link
27256 - * status than the first one, we return a value
27257 - * that indicates that the link status is
27258 - * indeterminated.
27259 + * If we find an active port with a different link status
27260 + * than the first one we return indeterminated.
27262 if (*pBuf != Val8) {
27264 @@ -6071,7 +6049,7 @@
27267 case OID_SKGE_FLOWCTRL_CAP:
27268 - /* Check if it is the first active port */
27269 + /* Check if it is the first active port. */
27272 *pBuf = pPrt->PFlowCtrlCap;
27273 @@ -6086,7 +6064,7 @@
27276 case OID_SKGE_FLOWCTRL_MODE:
27277 - /* Check if it is the first active port */
27278 + /* Check if it is the first active port. */
27281 *pBuf = pPrt->PFlowCtrlMode;
27282 @@ -6094,9 +6072,8 @@
27286 - * If we find an active port with a different flow
27287 - * control mode than the first one, we return a value
27288 - * that indicates that the mode is indeterminated.
27289 + * If we find an active port with a different flow-control mode
27290 + * than the first one we return indeterminated.
27292 if (*pBuf != pPrt->PFlowCtrlMode) {
27294 @@ -6105,7 +6082,7 @@
27297 case OID_SKGE_FLOWCTRL_STATUS:
27298 - /* Check if it is the first active port */
27299 + /* Check if it is the first active port. */
27302 *pBuf = pPrt->PFlowCtrlStatus;
27303 @@ -6113,10 +6090,8 @@
27307 - * If we find an active port with a different flow
27308 - * control status than the first one, we return a
27309 - * value that indicates that the status is
27310 - * indeterminated.
27311 + * If we find an active port with a different flow-control status
27312 + * than the first one we return indeterminated.
27314 if (*pBuf != pPrt->PFlowCtrlStatus) {
27316 @@ -6125,7 +6100,7 @@
27319 case OID_SKGE_PHY_OPERATION_CAP:
27320 - /* Check if it is the first active port */
27321 + /* Check if it is the first active port. */
27324 *pBuf = pPrt->PMSCap;
27325 @@ -6140,7 +6115,7 @@
27328 case OID_SKGE_PHY_OPERATION_MODE:
27329 - /* Check if it is the first active port */
27330 + /* Check if it is the first active port. */
27333 *pBuf = pPrt->PMSMode;
27334 @@ -6148,9 +6123,8 @@
27338 - * If we find an active port with a different master/
27339 - * slave mode than the first one, we return a value
27340 - * that indicates that the mode is indeterminated.
27341 + * If we find an active port with a different master/slave mode
27342 + * than the first one we return indeterminated.
27344 if (*pBuf != pPrt->PMSMode) {
27346 @@ -6159,7 +6133,7 @@
27349 case OID_SKGE_PHY_OPERATION_STATUS:
27350 - /* Check if it is the first active port */
27351 + /* Check if it is the first active port. */
27354 *pBuf = pPrt->PMSStatus;
27355 @@ -6167,10 +6141,8 @@
27359 - * If we find an active port with a different master/
27360 - * slave status than the first one, we return a
27361 - * value that indicates that the status is
27362 - * indeterminated.
27363 + * If we find an active port with a different master/slave status
27364 + * than the first one we return indeterminated.
27366 if (*pBuf != pPrt->PMSStatus) {
27368 @@ -6179,7 +6151,7 @@
27371 case OID_SKGE_SPEED_MODE:
27372 - /* Check if it is the first active port */
27373 + /* Check if it is the first active port. */
27376 *pBuf = pPrt->PLinkSpeed;
27377 @@ -6187,9 +6159,8 @@
27381 - * If we find an active port with a different flow
27382 - * control mode than the first one, we return a value
27383 - * that indicates that the mode is indeterminated.
27384 + * If we find an active port with a different link speed
27385 + * than the first one we return indeterminated.
27387 if (*pBuf != pPrt->PLinkSpeed) {
27389 @@ -6198,7 +6169,7 @@
27392 case OID_SKGE_SPEED_STATUS:
27393 - /* Check if it is the first active port */
27394 + /* Check if it is the first active port. */
27397 *pBuf = pPrt->PLinkSpeedUsed;
27398 @@ -6206,10 +6177,8 @@
27402 - * If we find an active port with a different flow
27403 - * control status than the first one, we return a
27404 - * value that indicates that the status is
27405 - * indeterminated.
27406 + * If we find an active port with a different link speed used
27407 + * than the first one we return indeterminated.
27409 if (*pBuf != pPrt->PLinkSpeedUsed) {
27411 @@ -6219,9 +6188,7 @@
27416 - * If no port is active return an indeterminated answer
27418 + /* If no port is active return an indeterminated answer. */
27419 if (!PortActiveFlag) {
27422 @@ -6324,7 +6291,7 @@
27425 * The COMMON module only tells us if the mode is half or full duplex.
27426 - * But in the decade of auto sensing it is useful for the user to
27427 + * But in the decade of auto sensing it is usefull for the user to
27428 * know if the mode was negotiated or forced. Therefore we have a
27429 * look to the mode, which was last used by the negotiation process.
27431 @@ -6338,16 +6305,15 @@
27435 - /* Get the current mode, which can be full or half duplex */
27436 + /* Get the current mode, which can be full or half duplex. */
27437 Result = pAC->GIni.GP[PhysPortIndex].PLinkModeStatus;
27439 - /* Check if no valid mode could be found (link is down) */
27440 + /* Check if no valid mode could be found (link is down). */
27441 if (Result < SK_LMODE_STAT_HALF) {
27443 Result = SK_LMODE_STAT_UNKNOWN;
27445 else if (pAC->GIni.GP[PhysPortIndex].PLinkMode >= SK_LMODE_AUTOHALF) {
27448 * Auto-negotiation was used to bring up the link. Change
27449 * the already found duplex status that it indicates
27450 @@ -6392,22 +6358,22 @@
27455 SK_MEMSET(pKeyArr, 0, KeyArrLen);
27458 - * Get VPD key list
27460 - Ret = VpdKeys(pAC, IoC, (char *)&BufKeys, (int *)&BufKeysLen,
27461 + /* Get VPD key list. */
27462 + Ret = VpdKeys(pAC, IoC, BufKeys, (int *)&BufKeysLen,
27467 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR014,
27468 - SK_PNMI_ERR014MSG);
27469 + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
27470 + (SK_PNMI_ERR014MSG));
27472 + /* Please read comment in Vpd(). */
27473 + pAC->Pnmi.VpdKeyReadError = SK_TRUE;
27474 return (SK_PNMI_ERR_GENERAL);
27476 - /* If no keys are available return now */
27477 + /* If no keys are available return now. */
27478 if (*pKeyNo == 0 || BufKeysLen == 0) {
27480 return (SK_PNMI_ERR_OK);
27481 @@ -6415,12 +6381,12 @@
27483 * If the key list is too long for us trunc it and give a
27484 * errorlog notification. This case should not happen because
27485 - * the maximum number of keys is limited due to RAM limitations
27486 + * the maximum number of keys is limited due to RAM limitations.
27488 if (*pKeyNo > SK_PNMI_VPD_ENTRIES) {
27490 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR015,
27491 - SK_PNMI_ERR015MSG);
27492 + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
27493 + (SK_PNMI_ERR015MSG));
27495 *pKeyNo = SK_PNMI_VPD_ENTRIES;
27497 @@ -6433,14 +6399,14 @@
27500 if (BufKeys[Offset] != 0) {
27505 if (Offset - StartOffset > SK_PNMI_VPD_KEY_SIZE) {
27507 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR016,
27508 - SK_PNMI_ERR016MSG);
27509 + SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
27510 + (SK_PNMI_ERR016MSG));
27512 return (SK_PNMI_ERR_GENERAL);
27515 @@ -6451,7 +6417,7 @@
27516 StartOffset = Offset + 1;
27519 - /* Last key not zero terminated? Get it anyway */
27520 + /* Last key not zero terminated? Get it anyway. */
27521 if (StartOffset < Offset) {
27523 SK_STRNCPY(pKeyArr + Index * SK_PNMI_VPD_KEY_SIZE,
27524 @@ -6480,19 +6446,18 @@
27526 SK_EVPARA EventParam;
27529 /* Was the module already updated during the current PNMI call? */
27530 if (pAC->Pnmi.SirqUpdatedFlag > 0) {
27532 return (SK_PNMI_ERR_OK);
27535 - /* Send an synchronuous update event to the module */
27536 + /* Send an synchronuous update event to the module. */
27537 SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
27538 - if (SkGeSirqEvent(pAC, IoC, SK_HWEV_UPDATE_STAT, EventParam) > 0) {
27540 + if (SkGeSirqEvent(pAC, IoC, SK_HWEV_UPDATE_STAT, EventParam)) {
27542 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR047,
27543 - SK_PNMI_ERR047MSG);
27544 + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR047, SK_PNMI_ERR047MSG);
27546 return (SK_PNMI_ERR_GENERAL);
27548 @@ -6520,21 +6485,19 @@
27550 SK_EVPARA EventParam;
27553 /* Was the module already updated during the current PNMI call? */
27554 if (pAC->Pnmi.RlmtUpdatedFlag > 0) {
27556 return (SK_PNMI_ERR_OK);
27559 - /* Send an synchronuous update event to the module */
27560 + /* Send an synchronuous update event to the module. */
27561 SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
27562 EventParam.Para32[0] = NetIndex;
27563 EventParam.Para32[1] = (SK_U32)-1;
27564 if (SkRlmtEvent(pAC, IoC, SK_RLMT_STATS_UPDATE, EventParam) > 0) {
27566 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR048,
27567 - SK_PNMI_ERR048MSG);
27568 + SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR048, SK_PNMI_ERR048MSG);
27570 return (SK_PNMI_ERR_GENERAL);
27572 @@ -6572,20 +6535,20 @@
27573 return (SK_PNMI_ERR_OK);
27576 - /* Send an update command to all MACs specified */
27577 + /* Send an update command to all MACs specified. */
27578 for (MacIndex = FirstMac; MacIndex <= LastMac; MacIndex ++) {
27581 * 2002-09-13 pweber: Freeze the current SW counters.
27582 * (That should be done as close as
27583 * possible to the update of the
27587 if (pAC->GIni.GIMacType == SK_MAC_XMAC) {
27588 pAC->Pnmi.BufPort[MacIndex] = pAC->Pnmi.Port[MacIndex];
27591 - /* 2002-09-13 pweber: Update the HW counter */
27592 + /* 2002-09-13 pweber: Update the HW counter. */
27593 if (pAC->GIni.GIFunc.pFnMacUpdateStats(pAC, IoC, MacIndex) != 0) {
27595 return (SK_PNMI_ERR_GENERAL);
27596 @@ -6623,19 +6586,19 @@
27600 - if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* Dual net mode */
27601 + if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* DualNet mode. */
27603 PhysPortIndex = NetIndex;
27605 Val = GetPhysStatVal(pAC, IoC, PhysPortIndex, StatIndex);
27607 - else { /* Single Net mode */
27608 + else { /* SingleNet mode. */
27610 if (LogPortIndex == 0) {
27612 PhysPortMax = pAC->GIni.GIMacsFound;
27614 - /* Add counter of all active ports */
27615 + /* Add counter of all active ports. */
27616 for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;
27617 PhysPortIndex ++) {
27619 @@ -6645,11 +6608,11 @@
27623 - /* Correct value because of port switches */
27624 + /* Correct value because of port switches. */
27625 Val += pAC->Pnmi.VirtualCounterOffset[StatIndex];
27628 - /* Get counter value of physical port */
27629 + /* Get counter value of physical port. */
27630 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);
27632 Val = GetPhysStatVal(pAC, IoC, PhysPortIndex, StatIndex);
27633 @@ -6695,7 +6658,7 @@
27635 MacType = pAC->GIni.GIMacType;
27637 - /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
27638 + /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
27639 if (MacType == SK_MAC_XMAC) {
27640 pPnmiPrt = &pAC->Pnmi.BufPort[PhysPortIndex];
27642 @@ -6763,7 +6726,7 @@
27643 case SK_PNMI_HTX_BURST:
27644 case SK_PNMI_HTX_EXCESS_DEF:
27645 case SK_PNMI_HTX_CARRIER:
27646 - /* Not supported by GMAC */
27647 + /* Not supported by GMAC. */
27648 if (MacType == SK_MAC_GMAC) {
27651 @@ -6775,7 +6738,7 @@
27654 case SK_PNMI_HTX_MACC:
27655 - /* GMAC only supports PAUSE MAC control frames */
27656 + /* GMAC only supports PAUSE MAC control frames. */
27657 if (MacType == SK_MAC_GMAC) {
27658 HelpIndex = SK_PNMI_HTX_PMACC;
27660 @@ -6792,7 +6755,7 @@
27662 case SK_PNMI_HTX_COL:
27663 case SK_PNMI_HRX_UNDERSIZE:
27664 - /* Not supported by XMAC */
27665 + /* Not supported by XMAC. */
27666 if (MacType == SK_MAC_XMAC) {
27669 @@ -6804,7 +6767,7 @@
27672 case SK_PNMI_HTX_DEFFERAL:
27673 - /* Not supported by GMAC */
27674 + /* Not supported by GMAC. */
27675 if (MacType == SK_MAC_GMAC) {
27678 @@ -6822,7 +6785,7 @@
27682 - /* Otherwise get contents of hardware register */
27683 + /* Otherwise get contents of hardware register. */
27684 (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
27685 StatAddr[StatIndex][MacType].Reg,
27687 @@ -6831,7 +6794,7 @@
27690 case SK_PNMI_HRX_BADOCTET:
27691 - /* Not supported by XMAC */
27692 + /* Not supported by XMAC. */
27693 if (MacType == SK_MAC_XMAC) {
27696 @@ -6850,7 +6813,7 @@
27699 case SK_PNMI_HRX_LONGFRAMES:
27700 - /* For XMAC the SW counter is managed by PNMI */
27701 + /* For XMAC the SW counter is managed by PNMI. */
27702 if (MacType == SK_MAC_XMAC) {
27703 return (pPnmiPrt->StatRxLongFrameCts);
27705 @@ -6870,7 +6833,7 @@
27706 Val = (((SK_U64)HighVal << 32) | (SK_U64)LowVal);
27708 if (MacType == SK_MAC_GMAC) {
27709 - /* For GMAC the SW counter is additionally managed by PNMI */
27710 + /* For GMAC the SW counter is additionally managed by PNMI. */
27711 Val += pPnmiPrt->StatRxFrameTooLongCts;
27714 @@ -6888,20 +6851,19 @@
27717 case SK_PNMI_HRX_SHORTS:
27718 - /* Not supported by GMAC */
27719 + /* Not supported by GMAC. */
27720 if (MacType == SK_MAC_GMAC) {
27721 /* GM_RXE_FRAG?? */
27726 - * XMAC counts short frame errors even if link down (#10620)
27728 - * If link-down the counter remains constant
27729 + * XMAC counts short frame errors even if link down (#10620).
27730 + * If the link is down, the counter remains constant.
27732 if (pPrt->PLinkModeStatus != SK_LMODE_STAT_UNKNOWN) {
27734 - /* Otherwise get incremental difference */
27735 + /* Otherwise get incremental difference. */
27736 (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
27737 StatAddr[StatIndex][MacType].Reg,
27739 @@ -6924,7 +6886,7 @@
27740 case SK_PNMI_HRX_IRLENGTH:
27741 case SK_PNMI_HRX_SYMBOL:
27742 case SK_PNMI_HRX_CEXT:
27743 - /* Not supported by GMAC */
27744 + /* Not supported by GMAC. */
27745 if (MacType == SK_MAC_GMAC) {
27748 @@ -6936,7 +6898,7 @@
27751 case SK_PNMI_HRX_PMACC_ERR:
27752 - /* For GMAC the SW counter is managed by PNMI */
27753 + /* For GMAC the SW counter is managed by PNMI. */
27754 if (MacType == SK_MAC_GMAC) {
27755 return (pPnmiPrt->StatRxPMaccErr);
27757 @@ -6947,13 +6909,13 @@
27758 HighVal = pPnmiPrt->CounterHigh[StatIndex];
27761 - /* SW counter managed by PNMI */
27762 + /* SW counter managed by PNMI. */
27763 case SK_PNMI_HTX_SYNC:
27764 LowVal = (SK_U32)pPnmiPrt->StatSyncCts;
27765 HighVal = (SK_U32)(pPnmiPrt->StatSyncCts >> 32);
27768 - /* SW counter managed by PNMI */
27769 + /* SW counter managed by PNMI. */
27770 case SK_PNMI_HTX_SYNC_OCTET:
27771 LowVal = (SK_U32)pPnmiPrt->StatSyncOctetsCts;
27772 HighVal = (SK_U32)(pPnmiPrt->StatSyncOctetsCts >> 32);
27773 @@ -6961,17 +6923,19 @@
27775 case SK_PNMI_HRX_FCS:
27777 - * Broadcom filters FCS errors and counts it in
27778 - * Receive Error Counter register
27779 + * Broadcom filters FCS errors and counts them in
27780 + * Receive Error Counter register.
27782 if (pPrt->PhyType == SK_PHY_BCOM) {
27783 - /* do not read while not initialized (PHY_READ hangs!)*/
27785 + /* Do not read while not initialized (PHY_READ hangs!). */
27786 if (pPrt->PState != SK_PRT_RESET) {
27787 SkXmPhyRead(pAC, IoC, PhysPortIndex, PHY_BCOM_RE_CTR, &Word);
27791 HighVal = pPnmiPrt->CounterHigh[StatIndex];
27792 +#endif /* GENESIS */
27795 (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
27796 @@ -6991,7 +6955,7 @@
27798 Val = (((SK_U64)HighVal << 32) | (SK_U64)LowVal);
27800 - /* Correct value because of possible XMAC reset. XMAC Errata #2 */
27801 + /* Correct value because of possible XMAC reset (XMAC Errata #2). */
27802 Val += pPnmiPrt->CounterOffset[StatIndex];
27805 @@ -7016,22 +6980,21 @@
27806 unsigned int PhysPortIndex;
27807 SK_EVPARA EventParam;
27810 SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
27812 - /* Notify sensor module */
27813 + /* Notify sensor module. */
27814 SkEventQueue(pAC, SKGE_I2C, SK_I2CEV_CLEAR, EventParam);
27816 - /* Notify RLMT module */
27817 + /* Notify RLMT module. */
27818 EventParam.Para32[0] = NetIndex;
27819 EventParam.Para32[1] = (SK_U32)-1;
27820 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STATS_CLEAR, EventParam);
27821 EventParam.Para32[1] = 0;
27823 - /* Notify SIRQ module */
27824 + /* Notify SIRQ module. */
27825 SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_CLEAR_STAT, EventParam);
27827 - /* Notify CSUM module */
27828 + /* Notify CSUM module. */
27830 EventParam.Para32[0] = NetIndex;
27831 EventParam.Para32[1] = (SK_U32)-1;
27832 @@ -7039,7 +7002,7 @@
27834 #endif /* SK_USE_CSUM */
27836 - /* Clear XMAC statistic */
27837 + /* Clear XMAC statistics. */
27838 for (PhysPortIndex = 0; PhysPortIndex <
27839 (unsigned int)pAC->GIni.GIMacsFound; PhysPortIndex ++) {
27841 @@ -7066,13 +7029,13 @@
27842 PhysPortIndex].StatRxPMaccErr));
27846 - * Clear local statistics
27848 + /* Clear local statistics. */
27849 SK_MEMSET((char *)&pAC->Pnmi.VirtualCounterOffset, 0,
27850 sizeof(pAC->Pnmi.VirtualCounterOffset));
27852 pAC->Pnmi.RlmtChangeCts = 0;
27853 pAC->Pnmi.RlmtChangeTime = 0;
27855 SK_MEMSET((char *)&pAC->Pnmi.RlmtChangeEstimate.EstValue[0], 0,
27856 sizeof(pAC->Pnmi.RlmtChangeEstimate.EstValue));
27857 pAC->Pnmi.RlmtChangeEstimate.EstValueIndex = 0;
27858 @@ -7109,23 +7072,21 @@
27859 SK_U32 TrapId, /* SNMP ID of the trap */
27860 unsigned int Size) /* Space needed for trap entry */
27862 - unsigned int BufPad = pAC->Pnmi.TrapBufPad;
27863 - unsigned int BufFree = pAC->Pnmi.TrapBufFree;
27864 - unsigned int Beg = pAC->Pnmi.TrapQueueBeg;
27865 - unsigned int End = pAC->Pnmi.TrapQueueEnd;
27866 + unsigned int BufPad = pAC->Pnmi.TrapBufPad;
27867 + unsigned int BufFree = pAC->Pnmi.TrapBufFree;
27868 + unsigned int Beg = pAC->Pnmi.TrapQueueBeg;
27869 + unsigned int End = pAC->Pnmi.TrapQueueEnd;
27870 char *pBuf = &pAC->Pnmi.TrapBuf[0];
27872 - unsigned int NeededSpace;
27873 - unsigned int EntrySize;
27874 + unsigned int NeededSpace;
27875 + unsigned int EntrySize;
27880 - /* Last byte of entry will get a copy of the entry length */
27881 + /* Last byte of entry will get a copy of the entry length. */
27885 - * Calculate needed buffer space */
27886 + /* Calculate needed buffer space. */
27889 NeededSpace = Size;
27890 @@ -7140,7 +7101,7 @@
27891 * Check if enough buffer space is provided. Otherwise
27892 * free some entries. Leave one byte space between begin
27893 * and end of buffer to make it possible to detect whether
27894 - * the buffer is full or empty
27895 + * the buffer is full or empty.
27897 while (BufFree < NeededSpace + 1) {
27899 @@ -7179,13 +7140,13 @@
27901 BufFree -= NeededSpace;
27903 - /* Save the current offsets */
27904 + /* Save the current offsets. */
27905 pAC->Pnmi.TrapQueueBeg = Beg;
27906 pAC->Pnmi.TrapQueueEnd = End;
27907 pAC->Pnmi.TrapBufPad = BufPad;
27908 pAC->Pnmi.TrapBufFree = BufFree;
27910 - /* Initialize the trap entry */
27911 + /* Initialize the trap entry. */
27912 *(pBuf + Beg + Size - 1) = (char)Size;
27913 *(pBuf + Beg) = (char)Size;
27914 Val32 = (pAC->Pnmi.TrapUnique) ++;
27915 @@ -7220,7 +7181,6 @@
27917 unsigned int DstOff = 0;
27920 while (Trap != End) {
27922 Len = (unsigned int)*(pBuf + Trap);
27923 @@ -7265,7 +7225,6 @@
27924 unsigned int Entries = 0;
27925 unsigned int TotalLen = 0;
27928 while (Trap != End) {
27930 Len = (unsigned int)*(pBuf + Trap);
27931 @@ -7322,14 +7281,14 @@
27932 unsigned int DescrLen;
27936 - /* Get trap buffer entry */
27937 + /* Get trap buffer entry. */
27938 DescrLen = SK_STRLEN(pAC->I2c.SenTable[SensorIndex].SenDesc);
27940 pBuf = GetTrapEntry(pAC, TrapId,
27941 SK_PNMI_TRAP_SENSOR_LEN_BASE + DescrLen);
27942 Offset = SK_PNMI_TRAP_SIMPLE_LEN;
27944 - /* Store additionally sensor trap related data */
27945 + /* Store additionally sensor trap related data. */
27946 Val32 = OID_SKGE_SENSOR_INDEX;
27947 SK_PNMI_STORE_U32(pBuf + Offset, Val32);
27948 *(pBuf + Offset + 4) = 4;
27949 @@ -7374,7 +7333,6 @@
27954 pBuf = GetTrapEntry(pAC, OID_SKGE_TRAP_RLMT_CHANGE_PORT,
27955 SK_PNMI_TRAP_RLMT_CHANGE_LEN);
27957 @@ -7402,7 +7360,6 @@
27962 pBuf = GetTrapEntry(pAC, TrapId, SK_PNMI_TRAP_RLMT_PORT_LEN);
27964 Val32 = OID_SKGE_RLMT_PORT_INDEX;
27965 @@ -7422,12 +7379,11 @@
27968 PNMI_STATIC void CopyMac(
27969 -char *pDst, /* Pointer to destination buffer */
27970 +char *pDst, /* Pointer to destination buffer */
27971 SK_MAC_ADDR *pMac) /* Pointer of Source */
27976 for (i = 0; i < sizeof(SK_MAC_ADDR); i ++) {
27978 *(pDst + i) = pMac->a[i];
27979 @@ -7465,19 +7421,22 @@
27980 SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */
27984 + unsigned int HwPortIndex;
27986 SK_U32 RetCode = SK_PNMI_ERR_GENERAL;
27989 - * Check instance. We only handle single instance variables
27991 - if (Instance != (SK_U32)(-1) && Instance != 1) {
27992 + /* Check instance. We only handle single instance variables. */
27993 + if ((Instance != (SK_U32)(-1))) {
27996 return (SK_PNMI_ERR_UNKNOWN_INST);
27999 + /* Get hardware port index */
28000 + HwPortIndex = NetIndex;
28003 - /* Check length */
28004 + /* Check length. */
28007 case OID_PNP_CAPABILITIES:
28008 @@ -7515,14 +7474,10 @@
28015 + /* Perform action. */
28016 if (Action == SK_PNMI_GET) {
28024 case OID_PNP_CAPABILITIES:
28025 @@ -7530,18 +7485,21 @@
28028 case OID_PNP_QUERY_POWER:
28029 - /* The Windows DDK describes: An OID_PNP_QUERY_POWER requests
28030 - the miniport to indicate whether it can transition its NIC
28031 - to the low-power state.
28032 - A miniport driver must always return NDIS_STATUS_SUCCESS
28033 - to a query of OID_PNP_QUERY_POWER. */
28035 + * The Windows DDK describes: An OID_PNP_QUERY_POWER requests
28036 + * the miniport to indicate whether it can transition its NIC
28037 + * to the low-power state.
28038 + * A miniport driver must always return NDIS_STATUS_SUCCESS
28039 + * to a query of OID_PNP_QUERY_POWER.
28041 *pLen = sizeof(SK_DEVICE_POWER_STATE);
28042 RetCode = SK_PNMI_ERR_OK;
28045 - /* NDIS handles these OIDs as write-only.
28047 + * NDIS handles these OIDs as write-only.
28048 * So in case of get action the buffer with written length = 0
28052 case OID_PNP_SET_POWER:
28053 case OID_PNP_ADD_WAKE_UP_PATTERN:
28054 @@ -7551,7 +7509,7 @@
28057 case OID_PNP_ENABLE_WAKE_UP:
28058 - RetCode = SkPowerGetEnableWakeUp(pAC, IoC, pBuf, pLen);
28059 + RetCode = SkPowerGetEnableWakeUp(pAC, IoC, HwPortIndex, pBuf, pLen);
28063 @@ -7562,31 +7520,49 @@
28069 - * Perform preset or set
28071 + /* Perform PRESET or SET. */
28073 - /* POWER module does not support PRESET action */
28074 + /* The POWER module does not support PRESET action. */
28075 if (Action == SK_PNMI_PRESET) {
28077 return (SK_PNMI_ERR_OK);
28084 case OID_PNP_SET_POWER:
28085 - RetCode = SkPowerSetPower(pAC, IoC, pBuf, pLen);
28086 + /* Dual net mode? */
28087 + for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
28088 + if (RetCode = SkPowerSetPower(pAC, IoC, i, pBuf, pLen)) {
28094 case OID_PNP_ADD_WAKE_UP_PATTERN:
28095 - RetCode = SkPowerAddWakeUpPattern(pAC, IoC, pBuf, pLen);
28096 + for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
28097 + if (RetCode = SkPowerAddWakeUpPattern(pAC, IoC, i, pBuf, pLen)) {
28103 case OID_PNP_REMOVE_WAKE_UP_PATTERN:
28104 - RetCode = SkPowerRemoveWakeUpPattern(pAC, IoC, pBuf, pLen);
28105 + for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
28106 + if (RetCode = SkPowerRemoveWakeUpPattern(pAC, IoC, i, pBuf, pLen)) {
28112 case OID_PNP_ENABLE_WAKE_UP:
28113 - RetCode = SkPowerSetEnableWakeUp(pAC, IoC, pBuf, pLen);
28114 + for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
28115 + if (RetCode = SkPowerSetEnableWakeUp(pAC, IoC, i, pBuf, pLen)) {
28122 @@ -7600,7 +7576,7 @@
28123 #ifdef SK_DIAG_SUPPORT
28124 /*****************************************************************************
28126 - * DiagActions - OID handler function of Diagnostic driver
28127 + * DiagActions - OID handler function of Diagnostic driver
28130 * The code is simple. No description necessary.
28131 @@ -7627,22 +7603,17 @@
28132 unsigned int TableIndex, /* Index to the Id table */
28133 SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */
28137 SK_U32 RetCode = SK_PNMI_ERR_GENERAL;
28140 - * Check instance. We only handle single instance variables.
28142 + /* Check instance. We only handle single instance variables. */
28143 if (Instance != (SK_U32)(-1) && Instance != 1) {
28146 return (SK_PNMI_ERR_UNKNOWN_INST);
28152 + /* Check length. */
28155 case OID_SKGE_DIAG_MODE:
28156 @@ -7660,10 +7631,9 @@
28159 /* Perform action. */
28162 if (Action == SK_PNMI_GET) {
28167 case OID_SKGE_DIAG_MODE:
28168 @@ -7678,14 +7648,15 @@
28169 RetCode = SK_PNMI_ERR_GENERAL;
28172 - return (RetCode);
28173 + return (RetCode);
28176 /* From here SET or PRESET value. */
28178 /* PRESET value is not supported. */
28179 if (Action == SK_PNMI_PRESET) {
28180 - return (SK_PNMI_ERR_OK);
28182 + return (SK_PNMI_ERR_OK);
28186 @@ -7697,7 +7668,7 @@
28188 /* Attach the DIAG to this adapter. */
28189 case SK_DIAG_ATTACHED:
28190 - /* Check if we come from running */
28191 + /* Check if we come from running. */
28192 if (pAC->Pnmi.DiagAttached == SK_DIAG_RUNNING) {
28194 RetCode = SkDrvLeaveDiagMode(pAC);
28195 @@ -7732,7 +7703,7 @@
28196 /* If DiagMode is not active, we can enter it. */
28197 if (!pAC->DiagModeActive) {
28199 - RetCode = SkDrvEnterDiagMode(pAC);
28200 + RetCode = SkDrvEnterDiagMode(pAC);
28204 @@ -7751,7 +7722,7 @@
28208 - /* Check if we come from running */
28209 + /* Check if we come from running. */
28210 if (pAC->Pnmi.DiagAttached == SK_DIAG_RUNNING) {
28212 RetCode = SkDrvLeaveDiagMode(pAC);
28213 @@ -7797,7 +7768,7 @@
28215 /*****************************************************************************
28217 - * Vct - OID handler function of OIDs
28218 + * Vct - OID handler function of OIDs for Virtual Cable Tester (VCT)
28221 * The code is simple. No description necessary.
28222 @@ -7833,153 +7804,150 @@
28223 SK_U32 PhysPortIndex;
28227 - SK_U32 RetCode = SK_PNMI_ERR_GENERAL;
28232 - SK_U32 CableLength;
28235 - * Calculate the port indexes from the instance.
28238 + RetCode = SK_PNMI_ERR_GENERAL;
28240 + /* Calculate the port indexes from the instance. */
28241 PhysPortMax = pAC->GIni.GIMacsFound;
28242 LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax);
28245 /* Dual net mode? */
28246 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
28251 if ((Instance != (SK_U32) (-1))) {
28252 - /* Check instance range. */
28253 - if ((Instance < 2) || (Instance > LogPortMax)) {
28255 - return (SK_PNMI_ERR_UNKNOWN_INST);
28259 + * Get one instance of that OID, so check the instance range:
28260 + * There is no virtual port with an Instance == 1, so we get
28261 + * the values from one physical port only.
28263 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
28264 PhysPortIndex = NetIndex;
28267 + if ((Instance < 2) || (Instance > LogPortMax)) {
28269 + return (SK_PNMI_ERR_UNKNOWN_INST);
28271 PhysPortIndex = Instance - 2;
28273 Limit = PhysPortIndex + 1;
28277 - * Instance == (SK_U32) (-1), get all Instances of that OID.
28279 - * Not implemented yet. May be used in future releases.
28280 + * Instance == (SK_U32) (-1), so get all instances of that OID.
28281 + * There is no virtual port with an Instance == 1, so we get
28282 + * the values from all physical ports.
28285 Limit = PhysPortMax;
28288 - pPrt = &pAC->GIni.GP[PhysPortIndex];
28289 - if (pPrt->PHWLinkUp) {
28296 - /* Check MAC type */
28297 - if (pPrt->PhyType != SK_PHY_MARV_COPPER) {
28299 + /* Check MAC type. */
28300 + if ((Id != OID_SKGE_VCT_CAPABILITIES) &&
28301 + (pAC->GIni.GP[PhysPortIndex].PhyType != SK_PHY_MARV_COPPER)) {
28303 - return (SK_PNMI_ERR_GENERAL);
28304 + return (SK_PNMI_ERR_NOT_SUPPORTED);
28307 - /* Initialize backup data pointer. */
28308 - pVctBackupData = &pAC->Pnmi.VctBackup[PhysPortIndex];
28310 - /* Check action type */
28312 + /* Check action type. */
28313 if (Action == SK_PNMI_GET) {
28314 - /* Check length */
28315 + /* Check length. */
28319 case OID_SKGE_VCT_GET:
28320 if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_PNMI_VCT)) {
28321 *pLen = (Limit - PhysPortIndex) * sizeof(SK_PNMI_VCT);
28322 return (SK_PNMI_ERR_TOO_SHORT);
28327 case OID_SKGE_VCT_STATUS:
28328 + case OID_SKGE_VCT_CAPABILITIES:
28329 if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U8)) {
28330 *pLen = (Limit - PhysPortIndex) * sizeof(SK_U8);
28331 return (SK_PNMI_ERR_TOO_SHORT);
28338 return (SK_PNMI_ERR_GENERAL);
28345 for (; PhysPortIndex < Limit; PhysPortIndex++) {
28347 + pPrt = &pAC->GIni.GP[PhysPortIndex];
28352 case OID_SKGE_VCT_GET:
28353 - if ((Link == SK_FALSE) &&
28354 + if (!pPrt->PHWLinkUp &&
28355 (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_PENDING)) {
28357 RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_FALSE);
28359 if (RetCode == 0) {
28360 - pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_PENDING;
28361 - pAC->Pnmi.VctStatus[PhysPortIndex] |=
28362 - (SK_PNMI_VCT_NEW_VCT_DATA | SK_PNMI_VCT_TEST_DONE);
28364 - /* Copy results for later use to PNMI struct. */
28365 - for (i = 0; i < 4; i++) {
28366 - if (pPrt->PMdiPairSts[i] == SK_PNMI_VCT_NORMAL_CABLE) {
28367 - if ((pPrt->PMdiPairLen[i] > 35) && (pPrt->PMdiPairLen[i] < 0xff)) {
28368 - pPrt->PMdiPairSts[i] = SK_PNMI_VCT_IMPEDANCE_MISMATCH;
28371 - if ((pPrt->PMdiPairLen[i] > 35) && (pPrt->PMdiPairLen[i] != 0xff)) {
28372 - CableLength = 1000 * (((175 * pPrt->PMdiPairLen[i]) / 210) - 28);
28377 - pVctBackupData->PMdiPairLen[i] = CableLength;
28378 - pVctBackupData->PMdiPairSts[i] = pPrt->PMdiPairSts[i];
28381 + /* VCT test is finished, so save the data. */
28382 + VctGetResults(pAC, IoC, PhysPortIndex);
28384 Para.Para32[0] = PhysPortIndex;
28385 Para.Para32[1] = -1;
28386 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Para);
28387 - SkEventDispatcher(pAC, IoC);
28390 - ; /* VCT test is running. */
28392 + /* SkEventDispatcher(pAC, IoC); */
28397 + /* Initialize backup data pointer. */
28398 + pVctBackupData = &pAC->Pnmi.VctBackup[PhysPortIndex];
28400 /* Get all results. */
28401 CheckVctStatus(pAC, IoC, pBuf, Offset, PhysPortIndex);
28402 - Offset += sizeof(SK_U8);
28405 *(pBuf + Offset) = pPrt->PCableLen;
28406 - Offset += sizeof(SK_U8);
28408 for (i = 0; i < 4; i++) {
28409 - SK_PNMI_STORE_U32((pBuf + Offset), pVctBackupData->PMdiPairLen[i]);
28411 + SK_PNMI_STORE_U32((pBuf + Offset), pVctBackupData->MdiPairLen[i]);
28412 Offset += sizeof(SK_U32);
28414 for (i = 0; i < 4; i++) {
28415 - *(pBuf + Offset) = pVctBackupData->PMdiPairSts[i];
28416 - Offset += sizeof(SK_U8);
28418 + *(pBuf + Offset) = pVctBackupData->MdiPairSts[i];
28423 RetCode = SK_PNMI_ERR_OK;
28427 case OID_SKGE_VCT_STATUS:
28428 CheckVctStatus(pAC, IoC, pBuf, Offset, PhysPortIndex);
28429 - Offset += sizeof(SK_U8);
28432 RetCode = SK_PNMI_ERR_OK;
28436 + case OID_SKGE_VCT_CAPABILITIES:
28437 + if (pPrt->PhyType != SK_PHY_MARV_COPPER) {
28438 + *(pBuf + Offset) = SK_PNMI_VCT_NOT_SUPPORTED;
28441 + *(pBuf + Offset) = SK_PNMI_VCT_SUPPORTED;
28445 + RetCode = SK_PNMI_ERR_OK;
28450 return (SK_PNMI_ERR_GENERAL);
28451 @@ -7987,15 +7955,15 @@
28457 } /* if SK_PNMI_GET */
28461 * From here SET or PRESET action. Check if the passed
28462 * buffer length is plausible.
28465 - /* Check length */
28467 + /* Check length. */
28469 case OID_SKGE_VCT_SET:
28470 if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U32)) {
28471 @@ -8003,42 +7971,45 @@
28472 return (SK_PNMI_ERR_TOO_SHORT);
28479 return (SK_PNMI_ERR_GENERAL);
28483 - * Perform preset or set.
28487 + /* Perform PRESET or SET. */
28489 /* VCT does not support PRESET action. */
28490 if (Action == SK_PNMI_PRESET) {
28492 return (SK_PNMI_ERR_OK);
28497 for (; PhysPortIndex < Limit; PhysPortIndex++) {
28499 + pPrt = &pAC->GIni.GP[PhysPortIndex];
28502 case OID_SKGE_VCT_SET: /* Start VCT test. */
28503 - if (Link == SK_FALSE) {
28504 + if (!pPrt->PHWLinkUp) {
28505 SkGeStopPort(pAC, IoC, PhysPortIndex, SK_STOP_ALL, SK_SOFT_RST);
28508 RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_TRUE);
28510 if (RetCode == 0) { /* RetCode: 0 => Start! */
28511 pAC->Pnmi.VctStatus[PhysPortIndex] |= SK_PNMI_VCT_PENDING;
28512 - pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_NEW_VCT_DATA;
28513 - pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_LINK;
28516 - * Start VCT timer counter.
28518 - SK_MEMSET((char *) &Para, 0, sizeof(Para));
28519 + pAC->Pnmi.VctStatus[PhysPortIndex] &=
28520 + ~(SK_PNMI_VCT_NEW_VCT_DATA | SK_PNMI_VCT_LINK);
28522 + /* Start VCT timer counter. */
28523 + SK_MEMSET((char *)&Para, 0, sizeof(Para));
28524 Para.Para32[0] = PhysPortIndex;
28525 Para.Para32[1] = -1;
28526 - SkTimerStart(pAC, IoC, &pAC->Pnmi.VctTimeout[PhysPortIndex].VctTimer,
28527 - 4000000, SKGE_PNMI, SK_PNMI_EVT_VCT_RESET, Para);
28529 + SkTimerStart(pAC, IoC, &pAC->Pnmi.VctTimeout[PhysPortIndex],
28530 + SK_PNMI_VCT_TIMER_CHECK, SKGE_PNMI, SK_PNMI_EVT_VCT_RESET, Para);
28532 SK_PNMI_STORE_U32((pBuf + Offset), RetCode);
28533 RetCode = SK_PNMI_ERR_OK;
28535 @@ -8054,7 +8025,7 @@
28537 Offset += sizeof(SK_U32);
28543 return (SK_PNMI_ERR_GENERAL);
28544 @@ -8066,6 +8037,65 @@
28548 +PNMI_STATIC void VctGetResults(
28557 + SK_U32 MinLength;
28558 + SK_U32 CableLength;
28560 + pPrt = &pAC->GIni.GP[Port];
28562 + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) {
28569 + /* Copy results for later use to PNMI struct. */
28570 + for (i = 0; i < 4; i++) {
28572 + PairLen = pPrt->PMdiPairLen[i];
28574 + if (((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) == 0) && (i > 1)) {
28575 + PairSts = SK_PNMI_VCT_NOT_PRESENT;
28578 + PairSts = pPrt->PMdiPairSts[i];
28581 + if ((PairSts == SK_PNMI_VCT_NORMAL_CABLE) &&
28582 + (PairLen > 28) && (PairLen < 0xff)) {
28584 + PairSts = SK_PNMI_VCT_IMPEDANCE_MISMATCH;
28587 + /* Ignore values <= MinLength, the linear factor is 4/5. */
28588 + if ((PairLen > MinLength) && (PairLen < 0xff)) {
28590 + CableLength = 1000UL * (PairLen - MinLength) * 4 / 5;
28593 + /* No cable or short cable. */
28597 + pAC->Pnmi.VctBackup[Port].MdiPairLen[i] = CableLength;
28598 + pAC->Pnmi.VctBackup[Port].MdiPairSts[i] = PairSts;
28601 + pAC->Pnmi.VctStatus[Port] &= ~SK_PNMI_VCT_PENDING;
28602 + pAC->Pnmi.VctStatus[Port] |= (SK_PNMI_VCT_NEW_VCT_DATA |
28603 + SK_PNMI_VCT_TEST_DONE);
28605 +} /* GetVctResults */
28607 PNMI_STATIC void CheckVctStatus(
28610 @@ -8075,54 +8105,57 @@
28613 SK_PNMI_VCT *pVctData;
28618 pPrt = &pAC->GIni.GP[PhysPortIndex];
28621 pVctData = (SK_PNMI_VCT *) (pBuf + Offset);
28622 pVctData->VctStatus = SK_PNMI_VCT_NONE;
28625 + VctStatus = pAC->Pnmi.VctStatus[PhysPortIndex];
28627 if (!pPrt->PHWLinkUp) {
28630 /* Was a VCT test ever made before? */
28631 - if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_TEST_DONE) {
28632 - if ((pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_LINK)) {
28633 + if (VctStatus & SK_PNMI_VCT_TEST_DONE) {
28634 + if (VctStatus & SK_PNMI_VCT_LINK) {
28635 pVctData->VctStatus |= SK_PNMI_VCT_OLD_VCT_DATA;
28638 pVctData->VctStatus |= SK_PNMI_VCT_NEW_VCT_DATA;
28643 /* Check VCT test status. */
28644 RetCode = SkGmCableDiagStatus(pAC,IoC, PhysPortIndex, SK_FALSE);
28646 if (RetCode == 2) { /* VCT test is running. */
28647 pVctData->VctStatus |= SK_PNMI_VCT_RUNNING;
28649 else { /* VCT data was copied to pAC here. Check PENDING state. */
28650 - if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_PENDING) {
28651 + if (VctStatus & SK_PNMI_VCT_PENDING) {
28652 pVctData->VctStatus |= SK_PNMI_VCT_NEW_VCT_DATA;
28657 if (pPrt->PCableLen != 0xff) { /* Old DSP value. */
28658 pVctData->VctStatus |= SK_PNMI_VCT_OLD_DSP_DATA;
28663 /* Was a VCT test ever made before? */
28664 - if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_TEST_DONE) {
28665 + if (VctStatus & SK_PNMI_VCT_TEST_DONE) {
28666 pVctData->VctStatus &= ~SK_PNMI_VCT_NEW_VCT_DATA;
28667 pVctData->VctStatus |= SK_PNMI_VCT_OLD_VCT_DATA;
28671 /* DSP only valid in 100/1000 modes. */
28672 - if (pAC->GIni.GP[PhysPortIndex].PLinkSpeedUsed !=
28673 - SK_LSPEED_STAT_10MBPS) {
28674 + if (pPrt->PLinkSpeedUsed != SK_LSPEED_STAT_10MBPS) {
28675 pVctData->VctStatus |= SK_PNMI_VCT_NEW_DSP_DATA;
28679 } /* CheckVctStatus */
28682 @@ -8165,29 +8198,29 @@
28683 ReturnCode = SK_PNMI_ERR_GENERAL;
28685 SK_MEMCPY(&Mode, pBuf, sizeof(SK_I32));
28686 - SK_MEMCPY(&Oid, (char *) pBuf + sizeof(SK_I32), sizeof(SK_U32));
28687 + SK_MEMCPY(&Oid, (char *)pBuf + sizeof(SK_I32), sizeof(SK_U32));
28688 HeaderLength = sizeof(SK_I32) + sizeof(SK_U32);
28689 *pLen = *pLen - HeaderLength;
28690 - SK_MEMCPY((char *) pBuf + sizeof(SK_I32), (char *) pBuf + HeaderLength, *pLen);
28691 + SK_MEMCPY((char *)pBuf + sizeof(SK_I32), (char *)pBuf + HeaderLength, *pLen);
28694 case SK_GET_SINGLE_VAR:
28695 - ReturnCode = SkPnmiGetVar(pAC, IoC, Oid,
28696 - (char *) pBuf + sizeof(SK_I32), pLen,
28697 + ReturnCode = SkPnmiGetVar(pAC, IoC, Oid,
28698 + (char *)pBuf + sizeof(SK_I32), pLen,
28699 ((SK_U32) (-1)), NetIndex);
28700 SK_PNMI_STORE_U32(pBuf, ReturnCode);
28701 *pLen = *pLen + sizeof(SK_I32);
28703 case SK_PRESET_SINGLE_VAR:
28704 - ReturnCode = SkPnmiPreSetVar(pAC, IoC, Oid,
28705 - (char *) pBuf + sizeof(SK_I32), pLen,
28706 + ReturnCode = SkPnmiPreSetVar(pAC, IoC, Oid,
28707 + (char *)pBuf + sizeof(SK_I32), pLen,
28708 ((SK_U32) (-1)), NetIndex);
28709 SK_PNMI_STORE_U32(pBuf, ReturnCode);
28710 *pLen = *pLen + sizeof(SK_I32);
28712 case SK_SET_SINGLE_VAR:
28713 - ReturnCode = SkPnmiSetVar(pAC, IoC, Oid,
28714 - (char *) pBuf + sizeof(SK_I32), pLen,
28715 + ReturnCode = SkPnmiSetVar(pAC, IoC, Oid,
28716 + (char *)pBuf + sizeof(SK_I32), pLen,
28717 ((SK_U32) (-1)), NetIndex);
28718 SK_PNMI_STORE_U32(pBuf, ReturnCode);
28719 *pLen = *pLen + sizeof(SK_I32);
28720 @@ -8208,3 +8241,86 @@
28721 return (ReturnCode);
28726 +/*****************************************************************************
28731 + * The code is simple. No description necessary.
28734 + * SK_PNMI_ERR_OK The request was successfully performed.
28735 + * SK_PNMI_ERR_GENERAL A general severe internal error occured.
28736 + * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
28737 + * the correct data (e.g. a 32bit value is
28738 + * needed, but a 16 bit value was passed).
28739 + * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
28740 + * exist (e.g. port instance 3 on a two port
28744 +PNMI_STATIC int Asf(
28745 +SK_AC *pAC, /* Pointer to adapter context */
28746 +SK_IOC IoC, /* IO context handle */
28747 +int Action, /* GET/PRESET/SET action */
28748 +SK_U32 Id, /* Object ID that is to be processed */
28749 +char *pBuf, /* Buffer used for the management data transfer */
28750 +unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */
28751 +SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
28752 +unsigned int TableIndex, /* Index to the Id table */
28753 +SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */
28755 + SK_U32 RetCode = SK_PNMI_ERR_GENERAL;
28758 + * Check instance. We only handle single instance variables.
28760 + if (Instance != (SK_U32)(-1) && Instance != 1) {
28763 + return (SK_PNMI_ERR_UNKNOWN_INST);
28766 + /* Perform action. */
28768 + if (Action == SK_PNMI_GET) {
28770 + case OID_SKGE_ASF:
28771 + RetCode = SkAsfGet(pAC, IoC, (SK_U8 *) pBuf, pLen);
28774 + RetCode = SkAsfGetOid( pAC, IoC, Id, Instance, (SK_U8 *) pBuf, pLen );
28778 + return (RetCode);
28781 + /* PRESET value. */
28782 + if (Action == SK_PNMI_PRESET) {
28784 + case OID_SKGE_ASF:
28785 + RetCode = SkAsfPreSet(pAC, IoC, (SK_U8 *) pBuf, pLen);
28788 + RetCode = SkAsfPreSetOid( pAC, IoC, Id, Instance, (SK_U8 *) pBuf, pLen );
28794 + if (Action == SK_PNMI_SET) {
28796 + case OID_SKGE_ASF:
28797 + RetCode = SkAsfSet(pAC, IoC, (SK_U8 *) pBuf, pLen);
28800 + RetCode = SkAsfSetOid( pAC, IoC, Id, Instance, (SK_U8 *) pBuf, pLen );
28804 + return (RetCode);
28806 +#endif /* SK_ASF */
28807 diff -ruN linux/drivers/net/sk98lin/skgesirq.c linux-new/drivers/net/sk98lin/skgesirq.c
28808 --- linux/drivers/net/sk98lin/skgesirq.c 2006-09-20 05:42:06.000000000 +0200
28809 +++ linux-new/drivers/net/sk98lin/skgesirq.c 2006-07-28 14:13:54.000000000 +0200
28813 * Project: Gigabit Ethernet Adapters, Common Modules
28814 - * Version: $Revision$
28816 + * Version: $Revision$
28818 * Purpose: Special IRQ module
28820 ******************************************************************************/
28822 /******************************************************************************
28825 * (C)Copyright 1998-2002 SysKonnect.
28826 - * (C)Copyright 2002-2003 Marvell.
28827 + * (C)Copyright 2002-2006 Marvell.
28829 * This program is free software; you can redistribute it and/or modify
28830 * it under the terms of the GNU General Public License as published by
28831 * the Free Software Foundation; either version 2 of the License, or
28832 * (at your option) any later version.
28834 * The information in this file is provided "AS IS" without warranty.
28837 ******************************************************************************/
28840 * right after this ISR.
28842 * The Interrupt source register of the adapter is NOT read by this module.
28843 - * SO if the drivers implementor needs a while loop around the
28844 + * SO if the drivers implementor needs a while loop around the
28845 * slow data paths interrupt bits, he needs to call the SkGeSirqIsr() for
28846 * each loop entered.
28852 -#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
28853 -static const char SysKonnectFileId[] =
28854 - "@(#) $Id$ (C) Marvell.";
28857 #include "h/skdrv1st.h" /* Driver Specific Definitions */
28859 #include "h/skgepnmi.h" /* PNMI Definitions */
28862 #include "h/skdrv2nd.h" /* Adapter Control and Driver specific Def. */
28864 +/* local variables ************************************************************/
28866 +#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
28867 +static const char SysKonnectFileId[] =
28868 + "@(#) $Id$ (C) Marvell.";
28871 /* local function prototypes */
28873 static int SkGePortCheckUpXmac(SK_AC*, SK_IOC, int, SK_BOOL);
28880 #endif /* GENESIS */
28883 @@ -109,8 +112,8 @@
28886 static void SkHWInitDefSense(
28887 -SK_AC *pAC, /* adapter context */
28888 -SK_IOC IoC, /* IO context */
28889 +SK_AC *pAC, /* Adapter Context */
28890 +SK_IOC IoC, /* I/O context */
28891 int Port) /* Port Index (MAC_1 + n) */
28893 SK_GEPORT *pPrt; /* GIni Port struct pointer */
28894 @@ -119,7 +122,7 @@
28896 pPrt->PAutoNegTimeOut = 0;
28898 - if (pPrt->PLinkModeConf != SK_LMODE_AUTOSENSE) {
28899 + if (pPrt->PLinkModeConf != (SK_U8)SK_LMODE_AUTOSENSE) {
28900 pPrt->PLinkMode = pPrt->PLinkModeConf;
28903 @@ -145,8 +148,8 @@
28906 static SK_U8 SkHWSenseGetNext(
28907 -SK_AC *pAC, /* adapter context */
28908 -SK_IOC IoC, /* IO context */
28909 +SK_AC *pAC, /* Adapter Context */
28910 +SK_IOC IoC, /* I/O context */
28911 int Port) /* Port Index (MAC_1 + n) */
28913 SK_GEPORT *pPrt; /* GIni Port struct pointer */
28914 @@ -155,18 +158,18 @@
28916 pPrt->PAutoNegTimeOut = 0;
28918 - if (pPrt->PLinkModeConf != (SK_U8)SK_LMODE_AUTOSENSE) {
28919 + if (pPrt->PLinkModeConf != (SK_U8)SK_LMODE_AUTOSENSE) {
28920 /* Leave all as configured */
28921 return(pPrt->PLinkModeConf);
28924 - if (pPrt->PLinkMode == (SK_U8)SK_LMODE_AUTOFULL) {
28925 + if (pPrt->PLinkMode == (SK_U8)SK_LMODE_AUTOFULL) {
28926 /* Return next mode AUTOBOTH */
28927 - return ((SK_U8)SK_LMODE_AUTOBOTH);
28928 + return((SK_U8)SK_LMODE_AUTOBOTH);
28931 /* Return default autofull */
28932 - return ((SK_U8)SK_LMODE_AUTOFULL);
28933 + return((SK_U8)SK_LMODE_AUTOFULL);
28934 } /* SkHWSenseGetNext */
28937 @@ -179,8 +182,8 @@
28940 static void SkHWSenseSetNext(
28941 -SK_AC *pAC, /* adapter context */
28942 -SK_IOC IoC, /* IO context */
28943 +SK_AC *pAC, /* Adapter Context */
28944 +SK_IOC IoC, /* I/O context */
28945 int Port, /* Port Index (MAC_1 + n) */
28946 SK_U8 NewMode) /* New Mode to be written in sense mode */
28948 @@ -190,7 +193,7 @@
28950 pPrt->PAutoNegTimeOut = 0;
28952 - if (pPrt->PLinkModeConf != (SK_U8)SK_LMODE_AUTOSENSE) {
28953 + if (pPrt->PLinkModeConf != (SK_U8)SK_LMODE_AUTOSENSE) {
28957 @@ -214,8 +217,8 @@
28961 -SK_AC *pAC, /* adapter context */
28962 -SK_IOC IoC, /* IO context */
28963 +SK_AC *pAC, /* Adapter Context */
28964 +SK_IOC IoC, /* I/O context */
28965 int Port) /* Port Index (MAC_1 + n) */
28967 SK_GEPORT *pPrt; /* GIni Port struct pointer */
28968 @@ -227,26 +230,28 @@
28970 /* Disable Receiver and Transmitter */
28971 SkMacRxTxDisable(pAC, IoC, Port);
28974 /* Init default sense mode */
28975 SkHWInitDefSense(pAC, IoC, Port);
28977 - if (pPrt->PHWLinkUp == SK_FALSE) {
28978 + if (!pPrt->PHWLinkUp) {
28982 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
28983 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
28984 ("Link down Port %d\n", Port));
28986 /* Set Link to DOWN */
28987 pPrt->PHWLinkUp = SK_FALSE;
28990 /* Reset Port stati */
28991 - pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN;
28992 - pPrt->PFlowCtrlStatus = (SK_U8)SK_FLOW_STAT_NONE;
28993 + pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN;
28994 + pPrt->PFlowCtrlStatus = (SK_U8)SK_FLOW_STAT_NONE;
28995 pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_INDETERMINATED;
28996 +#endif /* !SK_SLIM */
28998 - /* Re-init Phy especially when the AutoSense default is set now */
28999 + /* Re-init PHY especially when the AutoSense default is set now */
29000 SkMacInitPhy(pAC, IoC, Port, SK_FALSE);
29002 /* GP0: used for workaround of Rev. C Errata 2 */
29003 @@ -265,9 +270,9 @@
29007 -static void SkHWLinkUp(
29008 -SK_AC *pAC, /* adapter context */
29009 -SK_IOC IoC, /* IO context */
29011 +SK_AC *pAC, /* Adapter Context */
29012 +SK_IOC IoC, /* I/O context */
29013 int Port) /* Port Index (MAC_1 + n) */
29015 SK_GEPORT *pPrt; /* GIni Port struct pointer */
29016 @@ -280,12 +285,14 @@
29019 pPrt->PHWLinkUp = SK_TRUE;
29022 pPrt->PAutoNegFail = SK_FALSE;
29023 - pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN;
29024 + pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN;
29026 - if (pPrt->PLinkMode != (SK_U8)SK_LMODE_AUTOHALF &&
29027 - pPrt->PLinkMode != (SK_U8)SK_LMODE_AUTOFULL &&
29028 - pPrt->PLinkMode != (SK_U8)SK_LMODE_AUTOBOTH) {
29029 + if (pPrt->PLinkMode != (SK_U8)SK_LMODE_AUTOHALF &&
29030 + pPrt->PLinkMode != (SK_U8)SK_LMODE_AUTOFULL &&
29031 + pPrt->PLinkMode != (SK_U8)SK_LMODE_AUTOBOTH) {
29032 /* Link is up and no Auto-negotiation should be done */
29034 /* Link speed should be the configured one */
29035 @@ -293,7 +300,9 @@
29036 case SK_LSPEED_AUTO:
29037 /* default is 1000 Mbps */
29038 case SK_LSPEED_1000MBPS:
29039 - pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_1000MBPS;
29040 + pPrt->PLinkSpeedUsed = (SK_U8)
29041 + ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) ?
29042 + SK_LSPEED_STAT_1000MBPS : SK_LSPEED_STAT_100MBPS;
29044 case SK_LSPEED_100MBPS:
29045 pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_100MBPS;
29046 @@ -304,19 +313,19 @@
29049 /* Set Link Mode Status */
29050 - if (pPrt->PLinkMode == SK_LMODE_FULL) {
29051 - pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_FULL;
29054 - pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_HALF;
29056 + pPrt->PLinkModeStatus = (SK_U8)
29057 + ((pPrt->PLinkMode == (SK_U8)SK_LMODE_FULL) ?
29058 + SK_LMODE_STAT_FULL : SK_LMODE_STAT_HALF);
29060 /* No flow control without auto-negotiation */
29061 - pPrt->PFlowCtrlStatus = (SK_U8)SK_FLOW_STAT_NONE;
29062 + pPrt->PFlowCtrlStatus = (SK_U8)SK_FLOW_STAT_NONE;
29063 +#endif /* !SK_SLIM */
29066 - (void)SkMacRxTxEnable(pAC, IoC, Port);
29067 + (void)SkMacRxTxEnable(pAC, IoC, Port);
29070 +#endif /* !SK_SLIM */
29074 @@ -329,14 +338,16 @@
29077 static void SkMacParity(
29078 -SK_AC *pAC, /* adapter context */
29079 -SK_IOC IoC, /* IO context */
29080 -int Port) /* Port Index of the port failed */
29081 +SK_AC *pAC, /* Adapter Context */
29082 +SK_IOC IoC, /* I/O context */
29083 +int Port) /* Port Index (MAC_1 + n) */
29086 SK_GEPORT *pPrt; /* GIni Port struct pointer */
29087 SK_U32 TxMax; /* Tx Max Size Counter */
29091 pPrt = &pAC->GIni.GP[Port];
29093 /* Clear IRQ Tx Parity Error */
29094 @@ -346,7 +357,7 @@
29095 SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_CLR_PERR);
29097 #endif /* GENESIS */
29101 if (pAC->GIni.GIYukon) {
29102 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
29103 @@ -355,7 +366,7 @@
29104 pAC->GIni.GIChipRev == 0) ? GMF_CLI_TX_FC : GMF_CLI_TX_PE));
29109 if (pPrt->PCheckPar) {
29111 if (Port == MAC_1) {
29112 @@ -366,7 +377,7 @@
29114 Para.Para64 = Port;
29115 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
29118 Para.Para32[0] = Port;
29119 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
29121 @@ -378,18 +389,18 @@
29122 if (pAC->GIni.GIGenesis) {
29123 /* Snap statistic counters */
29124 (void)SkXmUpdateStats(pAC, IoC, Port);
29127 (void)SkXmMacStatistic(pAC, IoC, Port, XM_TXF_MAX_SZ, &TxMax);
29129 #endif /* GENESIS */
29133 if (pAC->GIni.GIYukon) {
29135 (void)SkGmMacStatistic(pAC, IoC, Port, GM_TXF_1518B, &TxMax);
29141 /* From now on check the parity */
29142 pPrt->PCheckPar = SK_TRUE;
29143 @@ -399,15 +410,15 @@
29145 /******************************************************************************
29147 - * SkGeHwErr() - Hardware Error service routine
29148 + * SkGeYuHwErr() - Hardware Error service routine (Genesis and Yukon)
29150 * Description: handles all HW Error interrupts
29154 -static void SkGeHwErr(
29155 -SK_AC *pAC, /* adapter context */
29156 -SK_IOC IoC, /* IO context */
29157 +static void SkGeYuHwErr(
29158 +SK_AC *pAC, /* Adapter Context */
29159 +SK_IOC IoC, /* I/O context */
29160 SK_U32 HwStatus) /* Interrupt status word */
29163 @@ -423,10 +434,10 @@
29166 /* Reset all bits in the PCI STATUS register */
29167 - SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);
29169 + SK_IN16(IoC, PCI_C(pAC, PCI_STATUS), &Word);
29171 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
29172 - SK_OUT16(IoC, PCI_C(PCI_STATUS), (SK_U16)(Word | PCI_ERRBITS));
29173 + SK_OUT16(IoC, PCI_C(pAC, PCI_STATUS), (SK_U16)(Word | PCI_ERRBITS));
29174 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
29177 @@ -461,7 +472,7 @@
29180 #endif /* GENESIS */
29184 if (pAC->GIni.GIYukon) {
29185 /* This is necessary only for Rx timing measurements */
29186 @@ -484,14 +495,18 @@
29189 if ((HwStatus & IS_RAM_RD_PAR) != 0) {
29191 SK_OUT16(IoC, B3_RI_CTRL, RI_CLR_RD_PERR);
29193 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E014, SKERR_SIRQ_E014MSG);
29195 SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
29198 if ((HwStatus & IS_RAM_WR_PAR) != 0) {
29200 SK_OUT16(IoC, B3_RI_CTRL, RI_CLR_WR_PERR);
29202 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E015, SKERR_SIRQ_E015MSG);
29204 SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
29205 @@ -512,7 +527,7 @@
29206 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E018, SKERR_SIRQ_E018MSG);
29207 Para.Para64 = MAC_1;
29208 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
29211 Para.Para32[0] = MAC_1;
29212 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
29214 @@ -524,37 +539,297 @@
29215 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E019, SKERR_SIRQ_E019MSG);
29216 Para.Para64 = MAC_2;
29217 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
29220 Para.Para32[0] = MAC_2;
29221 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
29224 +} /* SkGeYuHwErr */
29227 +/******************************************************************************
29229 + * SkYuk2HwPortErr() - Service HW Errors for specified port (Yukon-2 only)
29231 + * Description: handles the HW Error interrupts for a specific port.
29235 +static void SkYuk2HwPortErr(
29236 +SK_AC *pAC, /* Adapter Context */
29237 +SK_IOC IoC, /* I/O Context */
29238 +SK_U32 HwStatus, /* Interrupt status word */
29239 +int Port) /* Port Index (MAC_1 + n) */
29244 + if (Port == MAC_2) {
29248 + if ((HwStatus & Y2_HWE_L1_MASK) == 0) {
29252 + if ((HwStatus & Y2_IS_PAR_RD1) != 0) {
29254 + SK_OUT16(IoC, SELECT_RAM_BUFFER(Port, B3_RI_CTRL), RI_CLR_RD_PERR);
29256 + if (Port == MAC_1) {
29257 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E028, SKERR_SIRQ_E028MSG);
29260 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E030, SKERR_SIRQ_E030MSG);
29264 + if ((HwStatus & Y2_IS_PAR_WR1) != 0) {
29266 + SK_OUT16(IoC, SELECT_RAM_BUFFER(Port, B3_RI_CTRL), RI_CLR_WR_PERR);
29268 + if (Port == MAC_1) {
29269 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E029, SKERR_SIRQ_E029MSG);
29272 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E031, SKERR_SIRQ_E031MSG);
29276 + if ((HwStatus & Y2_IS_PAR_MAC1) != 0) {
29278 + SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
29280 + if (Port == MAC_1) {
29281 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E016, SKERR_SIRQ_E016MSG);
29284 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E017, SKERR_SIRQ_E017MSG);
29288 + if ((HwStatus & Y2_IS_PAR_RX1) != 0) {
29289 + if (Port == MAC_1) {
29291 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E018, SKERR_SIRQ_E018MSG);
29295 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E019, SKERR_SIRQ_E019MSG);
29298 + SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_PAR);
29301 + if ((HwStatus & Y2_IS_TCP_TXS1) != 0) {
29302 + if (Port == MAC_1) {
29304 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E033, SKERR_SIRQ_E033MSG);
29308 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E035, SKERR_SIRQ_E035MSG);
29311 + SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_TCP);
29314 + if ((HwStatus & Y2_IS_TCP_TXA1) != 0) {
29315 + if (Port == MAC_1) {
29317 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E032, SKERR_SIRQ_E032MSG);
29321 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E034, SKERR_SIRQ_E034MSG);
29324 + SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_TCP);
29327 + Para.Para64 = Port;
29328 + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
29330 + Para.Para32[0] = Port;
29331 + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
29333 +} /* SkYuk2HwPortErr */
29335 /******************************************************************************
29337 - * SkGeSirqIsr() - Special Interrupt Service Routine
29338 + * SkYuk2HwErr() - Hardware Error service routine (Yukon-2 only)
29340 - * Description: handles all non data transfer specific interrupts (slow path)
29341 + * Description: handles all HW Error interrupts
29345 +static void SkYuk2HwErr(
29346 +SK_AC *pAC, /* Adapter Context */
29347 +SK_IOC IoC, /* I/O Context */
29348 +SK_U32 HwStatus) /* Interrupt status word */
29353 + SK_U32 TlpHead[4];
29356 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
29357 + ("HW-Error Status: 0x%08lX\n", HwStatus));
29359 + /* This is necessary only for Rx timing measurements */
29360 + if ((HwStatus & Y2_IS_TIST_OV) != 0) {
29361 + /* increment Time Stamp Timer counter (high) */
29362 + pAC->GIni.GITimeStampCnt++;
29364 + /* Clear Time Stamp Timer IRQ */
29365 + SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8)GMT_ST_CLR_IRQ);
29368 + /* Evaluate Y2_IS_PCI_NEXP before Y2_IS_MST_ERR or Y2_IS_IRQ_STAT */
29369 + if ((HwStatus & Y2_IS_PCI_NEXP) != 0) {
29371 + * This error is also mapped either to Master Abort (Y2_IS_MST_ERR)
29372 + * or Target Abort (Y2_IS_IRQ_STAT) bit and can only be cleared there.
29373 + * Therefore handle this event just by printing an error log entry.
29375 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E027, SKERR_SIRQ_E027MSG);
29378 + if ((HwStatus & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) {
29379 + /* PCI Errors occured */
29380 + if ((HwStatus & Y2_IS_IRQ_STAT) != 0) {
29381 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E013, SKERR_SIRQ_E013MSG);
29384 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E012, SKERR_SIRQ_E012MSG);
29387 + /* Reset all bits in the PCI STATUS register */
29388 + SK_IN16(IoC, PCI_C(pAC, PCI_STATUS), &Word);
29390 + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
29391 + SK_OUT16(IoC, PCI_C(pAC, PCI_STATUS), (SK_U16)(Word | PCI_ERRBITS));
29392 + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
29395 + SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
29398 + /* check for PCI-Express Uncorrectable Error */
29399 + if ((HwStatus & Y2_IS_PCI_EXP) != 0) {
29401 + * On PCI-Express bus bridges are called root complexes (RC).
29402 + * PCI-Express errors are recognized by the root complex too,
29403 + * which requests the system to handle the problem. After error
29404 + * occurence it may be that no access to the adapter may be performed
29408 + /* Get uncorrectable error status */
29409 + SK_IN32(IoC, PCI_C(pAC, PEX_UNC_ERR_STAT), &DWord);
29411 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
29412 + ("PEX Uncorr.Error Status: 0x%08lX\n", DWord));
29414 + if (DWord != PEX_UNSUP_REQ) {
29415 + /* ignore Unsupported Request Errors */
29416 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E026, SKERR_SIRQ_E026MSG);
29419 + if ((DWord & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) {
29421 + * Stop only, if the uncorrectable error is fatal or
29422 + * Poisoned TLP occured
29424 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, ("Header Log:"));
29426 + for (i = 0; i < 4; i++) {
29427 + /* get TLP Header from Log Registers */
29428 + SK_IN32(IoC, PCI_C(pAC, PEX_HEADER_LOG + i*4), &TlpHead[i]);
29430 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
29431 + (" 0x%08lX", TlpHead[i]));
29433 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, ("\n"));
29435 + /* check for vendor defined broadcast message */
29436 + if (TlpHead[0] == 0x73004001 && (SK_U8)TlpHead[1] == 0x7f) {
29438 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
29439 + ("Vendor defined broadcast message\n"));
29443 + SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
29445 + pAC->GIni.GIValHwIrqMask &= ~Y2_IS_PCI_EXP;
29446 + /* Rewrite HW IRQ mask */
29447 + SK_OUT32(IoC, B0_HWE_IMSK, pAC->GIni.GIValHwIrqMask);
29451 + /* clear any PEX errors */
29452 + SK_OUT32(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
29453 + SK_OUT32(IoC, PCI_C(pAC, PEX_UNC_ERR_STAT), 0xffffffffUL);
29454 + SK_OUT32(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
29456 + SK_IN32(IoC, PCI_C(pAC, PEX_UNC_ERR_STAT), &DWord);
29458 + if ((DWord & PEX_RX_OV) != 0) {
29459 + /* Dev #4.205 occured */
29460 + pAC->GIni.GIValHwIrqMask &= ~Y2_IS_PCI_EXP;
29461 + pAC->GIni.GIValIrqMask &= ~Y2_IS_HW_ERR;
29465 + for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
29467 + SkYuk2HwPortErr(pAC, IoC, HwStatus, i);
29470 +} /* SkYuk2HwErr */
29473 +/******************************************************************************
29475 + * SkGeSirqIsr() - Wrapper for Special Interrupt Service Routine
29477 + * Description: calls the preselected special ISR (slow path)
29482 -SK_AC *pAC, /* adapter context */
29483 -SK_IOC IoC, /* IO context */
29484 +SK_AC *pAC, /* Adapter Context */
29485 +SK_IOC IoC, /* I/O context */
29486 +SK_U32 Istatus) /* Interrupt status word */
29488 + pAC->GIni.GIFunc.pSkGeSirqIsr(pAC, IoC, Istatus);
29491 +/******************************************************************************
29493 + * SkGeYuSirqIsr() - Special Interrupt Service Routine
29495 + * Description: handles all non data transfer specific interrupts (slow path)
29499 +void SkGeYuSirqIsr(
29500 +SK_AC *pAC, /* Adapter Context */
29501 +SK_IOC IoC, /* I/O Context */
29502 SK_U32 Istatus) /* Interrupt status word */
29505 SK_U32 RegVal32; /* Read register value */
29506 SK_GEPORT *pPrt; /* GIni Port struct pointer */
29511 if (((Istatus & IS_HW_ERR) & pAC->GIni.GIValIrqMask) != 0) {
29512 /* read the HW Error Interrupt source */
29513 SK_IN32(IoC, B0_HWE_ISRC, &RegVal32);
29515 - SkGeHwErr(pAC, IoC, RegVal32);
29517 + SkGeYuHwErr(pAC, IoC, RegVal32);
29521 @@ -569,7 +844,7 @@
29524 if (((Istatus & (IS_PA_TO_RX2 | IS_PA_TO_TX2)) != 0) &&
29525 - pAC->GIni.GP[MAC_2].PState == SK_PRT_RESET) {
29526 + pAC->GIni.GP[MAC_2].PState == SK_PRT_RESET) {
29527 /* MAC 2 was not initialized but Packet timeout occured */
29528 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E005,
29529 SKERR_SIRQ_E005MSG);
29530 @@ -590,8 +865,8 @@
29533 if ((Istatus & IS_PA_TO_TX1) != 0) {
29535 - pPrt = &pAC->GIni.GP[0];
29537 + pPrt = &pAC->GIni.GP[MAC_1];
29539 /* May be a normal situation in a server with a slow network */
29540 SK_OUT16(IoC, B3_PA_CTRL, PA_CLR_TO_TX1);
29541 @@ -612,17 +887,18 @@
29544 pPrt->HalfDupTimerActive = SK_TRUE;
29546 /* Snap statistic counters */
29547 (void)SkXmUpdateStats(pAC, IoC, 0);
29549 (void)SkXmMacStatistic(pAC, IoC, 0, XM_TXO_OK_HI, &RegVal32);
29551 pPrt->LastOctets = (SK_U64)RegVal32 << 32;
29554 (void)SkXmMacStatistic(pAC, IoC, 0, XM_TXO_OK_LO, &RegVal32);
29556 pPrt->LastOctets += RegVal32;
29559 Para.Para32[0] = 0;
29560 SkTimerStart(pAC, IoC, &pPrt->HalfDupChkTimer, SK_HALFDUP_CHK_TIME,
29561 SKGE_HWAC, SK_HWEV_HALFDUP_CHK, Para);
29562 @@ -632,8 +908,8 @@
29565 if ((Istatus & IS_PA_TO_TX2) != 0) {
29567 - pPrt = &pAC->GIni.GP[1];
29569 + pPrt = &pAC->GIni.GP[MAC_2];
29571 /* May be a normal situation in a server with a slow network */
29572 SK_OUT16(IoC, B3_PA_CTRL, PA_CLR_TO_TX2);
29573 @@ -645,17 +921,18 @@
29574 pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOHALF) &&
29575 !pPrt->HalfDupTimerActive) {
29576 pPrt->HalfDupTimerActive = SK_TRUE;
29578 /* Snap statistic counters */
29579 (void)SkXmUpdateStats(pAC, IoC, 1);
29581 (void)SkXmMacStatistic(pAC, IoC, 1, XM_TXO_OK_HI, &RegVal32);
29583 pPrt->LastOctets = (SK_U64)RegVal32 << 32;
29586 (void)SkXmMacStatistic(pAC, IoC, 1, XM_TXO_OK_LO, &RegVal32);
29588 pPrt->LastOctets += RegVal32;
29591 Para.Para32[0] = 1;
29592 SkTimerStart(pAC, IoC, &pPrt->HalfDupChkTimer, SK_HALFDUP_CHK_TIME,
29593 SKGE_HWAC, SK_HWEV_HALFDUP_CHK, Para);
29594 @@ -668,6 +945,7 @@
29595 if ((Istatus & IS_R1_C) != 0) {
29597 SK_OUT32(IoC, B0_R1_CSR, CSR_IRQ_CL_C);
29599 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E006,
29600 SKERR_SIRQ_E006MSG);
29601 Para.Para64 = MAC_1;
29602 @@ -679,6 +957,7 @@
29603 if ((Istatus & IS_R2_C) != 0) {
29605 SK_OUT32(IoC, B0_R2_CSR, CSR_IRQ_CL_C);
29607 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E007,
29608 SKERR_SIRQ_E007MSG);
29609 Para.Para64 = MAC_2;
29610 @@ -690,6 +969,7 @@
29611 if ((Istatus & IS_XS1_C) != 0) {
29613 SK_OUT32(IoC, B0_XS1_CSR, CSR_IRQ_CL_C);
29615 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E008,
29616 SKERR_SIRQ_E008MSG);
29617 Para.Para64 = MAC_1;
29618 @@ -701,6 +981,7 @@
29619 if ((Istatus & IS_XA1_C) != 0) {
29621 SK_OUT32(IoC, B0_XA1_CSR, CSR_IRQ_CL_C);
29623 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E009,
29624 SKERR_SIRQ_E009MSG);
29625 Para.Para64 = MAC_1;
29626 @@ -712,6 +993,7 @@
29627 if ((Istatus & IS_XS2_C) != 0) {
29629 SK_OUT32(IoC, B0_XS2_CSR, CSR_IRQ_CL_C);
29631 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E010,
29632 SKERR_SIRQ_E010MSG);
29633 Para.Para64 = MAC_2;
29634 @@ -723,6 +1005,7 @@
29635 if ((Istatus & IS_XA2_C) != 0) {
29637 SK_OUT32(IoC, B0_XA2_CSR, CSR_IRQ_CL_C);
29639 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E011,
29640 SKERR_SIRQ_E011MSG);
29641 Para.Para64 = MAC_2;
29642 @@ -735,39 +1018,37 @@
29643 if ((Istatus & IS_EXT_REG) != 0) {
29644 /* Test IRQs from PHY */
29645 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
29648 pPrt = &pAC->GIni.GP[i];
29651 if (pPrt->PState == SK_PRT_RESET) {
29657 if (pAC->GIni.GIGenesis) {
29660 switch (pPrt->PhyType) {
29668 SkXmPhyRead(pAC, IoC, i, PHY_BCOM_INT_STAT, &PhyInt);
29671 if ((PhyInt & ~PHY_B_DEF_MSK) != 0) {
29672 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
29673 - ("Port %d Bcom Int: 0x%04X\n",
29675 + ("Port %d PHY Int: 0x%04X\n", i, PhyInt));
29676 SkPhyIsrBcom(pAC, IoC, i, PhyInt);
29681 SkXmPhyRead(pAC, IoC, i, PHY_LONE_INT_STAT, &PhyInt);
29684 if ((PhyInt & PHY_L_DEF_MSK) != 0) {
29685 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
29686 - ("Port %d Lone Int: %x\n",
29688 + ("Port %d PHY Int: 0x%04X\n", i, PhyInt));
29689 SkPhyIsrLone(pAC, IoC, i, PhyInt);
29692 @@ -775,7 +1056,7 @@
29695 #endif /* GENESIS */
29699 if (pAC->GIni.GIYukon) {
29700 /* Read PHY Interrupt Status */
29701 @@ -783,8 +1064,7 @@
29703 if ((PhyInt & PHY_M_DEF_MSK) != 0) {
29704 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
29705 - ("Port %d Marv Int: 0x%04X\n",
29707 + ("Port %d PHY Int: 0x%04X\n", i, PhyInt));
29708 SkPhyIsrGmac(pAC, IoC, i, PhyInt);
29711 @@ -792,13 +1072,13 @@
29715 - /* I2C Ready interrupt */
29716 + /* TWSI Ready interrupt */
29717 if ((Istatus & IS_I2C_READY) != 0) {
29719 - SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
29721 + SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
29723 SkI2cIsr(pAC, IoC);
29728 /* SW forced interrupt */
29729 @@ -813,7 +1093,7 @@
29730 * us only a link going down.
29732 /* clear interrupt */
29733 - SK_OUT8(IoC, MR_ADDR(MAC_1, LNK_SYNC_CTRL), LED_CLR_IRQ);
29734 + SK_OUT8(IoC, MR_ADDR(MAC_1, LNK_SYNC_CTRL), LNK_CLR_IRQ);
29737 /* Check MAC after link sync counter */
29738 @@ -828,7 +1108,7 @@
29739 * us only a link going down.
29741 /* clear interrupt */
29742 - SK_OUT8(IoC, MR_ADDR(MAC_2, LNK_SYNC_CTRL), LED_CLR_IRQ);
29743 + SK_OUT8(IoC, MR_ADDR(MAC_2, LNK_SYNC_CTRL), LNK_CLR_IRQ);
29746 /* Check MAC after link sync counter */
29747 @@ -844,13 +1124,201 @@
29748 /* read the HW Error Interrupt source */
29749 SK_IN32(IoC, B0_HWE_ISRC, &RegVal32);
29751 - SkGeHwErr(pAC, IoC, RegVal32);
29752 + SkGeYuHwErr(pAC, IoC, RegVal32);
29755 SkHwtIsr(pAC, IoC);
29758 -} /* SkGeSirqIsr */
29759 +} /* SkGeYuSirqIsr */
29762 +/******************************************************************************
29764 + * SkYuk2PortSirq() - Service HW Errors for specified port (Yukon-2 only)
29766 + * Description: handles the HW Error interrupts for a specific port.
29770 +static void SkYuk2PortSirq(
29771 +SK_AC *pAC, /* Adapter Context */
29772 +SK_IOC IoC, /* I/O Context */
29773 +SK_U32 IStatus, /* Interrupt status word */
29774 +int Port) /* Port Index (MAC_1 + n) */
29780 + if (Port == MAC_2) {
29784 + /* Interrupt from PHY */
29785 + if ((IStatus & Y2_IS_IRQ_PHY1) != 0) {
29786 + /* Read PHY Interrupt Status */
29787 + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_INT_STAT, &PhyInt);
29789 + if ((PhyInt & PHY_M_DEF_MSK) != 0) {
29790 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
29791 + ("Port %d PHY Int: 0x%04X\n", Port, PhyInt));
29792 + SkPhyIsrGmac(pAC, IoC, Port, PhyInt);
29796 + /* Interrupt from MAC */
29797 + if ((IStatus & Y2_IS_IRQ_MAC1) != 0) {
29798 + SkMacIrq(pAC, IoC, Port);
29801 + if ((IStatus & (Y2_IS_CHK_RX1 | Y2_IS_CHK_TXS1 | Y2_IS_CHK_TXA1)) != 0) {
29802 + if ((IStatus & Y2_IS_CHK_RX1) != 0) {
29803 + if (Port == MAC_1) {
29805 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E006,
29806 + SKERR_SIRQ_E006MSG);
29810 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E007,
29811 + SKERR_SIRQ_E007MSG);
29814 + SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_CHK);
29817 + if ((IStatus & Y2_IS_CHK_TXS1) != 0) {
29818 + if (Port == MAC_1) {
29820 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E008,
29821 + SKERR_SIRQ_E008MSG);
29825 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E010,
29826 + SKERR_SIRQ_E010MSG);
29829 + SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_CHK);
29832 + if ((IStatus & Y2_IS_CHK_TXA1) != 0) {
29833 + if (Port == MAC_1) {
29835 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E009,
29836 + SKERR_SIRQ_E009MSG);
29840 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E011,
29841 + SKERR_SIRQ_E011MSG);
29844 + SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_CHK);
29847 + Para.Para64 = Port;
29848 + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
29850 + Para.Para32[0] = Port;
29851 + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
29853 +} /* SkYuk2PortSirq */
29856 +/******************************************************************************
29858 + * SkYuk2SirqIsr() - Special Interrupt Service Routine (Yukon-2 only)
29860 + * Description: handles all non data transfer specific interrupts (slow path)
29864 +void SkYuk2SirqIsr(
29865 +SK_AC *pAC, /* Adapter Context */
29866 +SK_IOC IoC, /* I/O Context */
29867 +SK_U32 Istatus) /* Interrupt status word */
29871 + SK_U32 RegVal32; /* Read register value */
29874 + /* HW Error indicated ? */
29875 + if (((Istatus & Y2_IS_HW_ERR) & pAC->GIni.GIValIrqMask) != 0) {
29876 + /* read the HW Error Interrupt source */
29877 + SK_IN32(IoC, B0_HWE_ISRC, &RegVal32);
29879 + SkYuk2HwErr(pAC, IoC, RegVal32);
29882 + /* Interrupt from ASF Subsystem */
29883 + if ((Istatus & Y2_IS_ASF) != 0) {
29885 + /* later on clearing should be done in ASF ISR handler */
29886 + SK_IN8(IoC, B28_Y2_ASF_STAT_CMD, &Value);
29887 + Value |= Y2_ASF_CLR_HSTI;
29888 + SK_OUT8(IoC, B28_Y2_ASF_STAT_CMD, Value);
29889 + /* Call IRQ handler in ASF Module */
29893 + /* Check IRQ from polling unit */
29894 + if ((Istatus & Y2_IS_POLL_CHK) != 0) {
29896 + SK_OUT32(IoC, POLL_CTRL, PC_CLR_IRQ_CHK);
29898 + SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E036,
29899 + SKERR_SIRQ_E036MSG);
29901 + SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
29904 + /* TWSI Ready interrupt */
29905 + if ((Istatus & Y2_IS_TWSI_RDY) != 0) {
29907 + SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
29909 + SkI2cIsr(pAC, IoC);
29913 + /* SW forced interrupt */
29914 + if ((Istatus & Y2_IS_IRQ_SW) != 0) {
29915 + /* clear the software IRQ */
29916 + SK_OUT8(IoC, B0_CTST, CS_CL_SW_IRQ);
29919 + if ((Istatus & Y2_IS_L1_MASK) != 0) {
29920 + SkYuk2PortSirq(pAC, IoC, Istatus, MAC_1);
29923 + if ((Istatus & Y2_IS_L2_MASK) != 0) {
29924 + SkYuk2PortSirq(pAC, IoC, Istatus, MAC_2);
29927 + /* Timer interrupt (served last) */
29928 + if ((Istatus & Y2_IS_TIMINT) != 0) {
29930 + if (((Istatus & Y2_IS_HW_ERR) & ~pAC->GIni.GIValIrqMask) != 0) {
29931 + /* read the HW Error Interrupt source */
29932 + SK_IN32(IoC, B0_HWE_ISRC, &RegVal32);
29934 + /* otherwise we would generate error log entries periodically */
29935 + RegVal32 &= pAC->GIni.GIValHwIrqMask;
29936 + if (RegVal32 != 0) {
29937 + SkYuk2HwErr(pAC, IoC, RegVal32);
29941 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
29942 + ("Timer Int: 0x%08lX\n", Istatus));
29943 + SkHwtIsr(pAC, IoC);
29947 +} /* SkYuk2SirqIsr */
29951 @@ -864,8 +1332,8 @@
29953 static int SkGePortCheckShorts(
29954 SK_AC *pAC, /* Adapter Context */
29955 -SK_IOC IoC, /* IO Context */
29956 -int Port) /* Which port should be checked */
29957 +SK_IOC IoC, /* I/O Context */
29958 +int Port) /* Port Index (MAC_1 + n) */
29960 SK_U32 Shorts; /* Short Event Counter */
29961 SK_U32 CheckShorts; /* Check value for Short Event Counter */
29962 @@ -893,9 +1361,9 @@
29965 for (i = 0; i < sizeof(SkGeRxRegs)/sizeof(SkGeRxRegs[0]); i++) {
29968 (void)SkXmMacStatistic(pAC, IoC, Port, SkGeRxRegs[i], &RxTmp);
29971 RxCts += (SK_U64)RxTmp;
29974 @@ -912,11 +1380,11 @@
29977 (void)SkXmMacStatistic(pAC, IoC, Port, XM_RXF_FCS_ERR, &FcsErrCts);
29979 - if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE &&
29980 - pPrt->PLipaAutoNeg == SK_LIPA_UNKNOWN &&
29981 - (pPrt->PLinkMode == SK_LMODE_HALF ||
29982 - pPrt->PLinkMode == SK_LMODE_FULL)) {
29984 + if (pPrt->PLinkModeConf == (SK_U8)SK_LMODE_AUTOSENSE &&
29985 + pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_UNKNOWN &&
29986 + (pPrt->PLinkMode == (SK_U8)SK_LMODE_HALF ||
29987 + pPrt->PLinkMode == (SK_U8)SK_LMODE_FULL)) {
29989 * This is autosensing and we are in the fallback
29990 * manual full/half duplex mode.
29991 @@ -925,16 +1393,16 @@
29992 /* Nothing received, restart link */
29993 pPrt->PPrevFcs = FcsErrCts;
29994 pPrt->PPrevShorts = Shorts;
29997 return(SK_HW_PS_RESTART);
30000 - pPrt->PLipaAutoNeg = SK_LIPA_MANUAL;
30001 + pPrt->PLipaAutoNeg = (SK_U8)SK_LIPA_MANUAL;
30005 if (((RxCts - pPrt->PPrevRx) > pPrt->PRxLim) ||
30006 - (!(FcsErrCts - pPrt->PPrevFcs))) {
30007 + (!(FcsErrCts - pPrt->PPrevFcs))) {
30009 * Note: The compare with zero above has to be done the way shown,
30010 * otherwise the Linux driver will have a problem.
30011 @@ -979,29 +1447,25 @@
30013 static int SkGePortCheckUp(
30014 SK_AC *pAC, /* Adapter Context */
30015 -SK_IOC IoC, /* IO Context */
30016 -int Port) /* Which port should be checked */
30017 +SK_IOC IoC, /* I/O Context */
30018 +int Port) /* Port Index (MAC_1 + n) */
30020 SK_GEPORT *pPrt; /* GIni Port struct pointer */
30021 SK_BOOL AutoNeg; /* Is Auto-negotiation used ? */
30022 int Rtv; /* Return value */
30024 Rtv = SK_HW_PS_NONE;
30027 pPrt = &pAC->GIni.GP[Port];
30029 - if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
30030 - AutoNeg = SK_FALSE;
30033 - AutoNeg = SK_TRUE;
30035 + AutoNeg = pPrt->PLinkMode != SK_LMODE_HALF &&
30036 + pPrt->PLinkMode != SK_LMODE_FULL;
30039 if (pAC->GIni.GIGenesis) {
30041 switch (pPrt->PhyType) {
30045 Rtv = SkGePortCheckUpXmac(pAC, IoC, Port, AutoNeg);
30047 @@ -1019,15 +1483,15 @@
30050 #endif /* GENESIS */
30054 if (pAC->GIni.GIYukon) {
30057 Rtv = SkGePortCheckUpGmac(pAC, IoC, Port, AutoNeg);
30063 } /* SkGePortCheckUp */
30066 @@ -1043,8 +1507,8 @@
30068 static int SkGePortCheckUpXmac(
30069 SK_AC *pAC, /* Adapter Context */
30070 -SK_IOC IoC, /* IO Context */
30071 -int Port, /* Which port should be checked */
30072 +SK_IOC IoC, /* I/O Context */
30073 +int Port, /* Port Index (MAC_1 + n) */
30074 SK_BOOL AutoNeg) /* Is Auto-negotiation used ? */
30076 SK_U32 Shorts; /* Short Event Counter */
30077 @@ -1082,7 +1546,7 @@
30078 XM_IN16(IoC, Port, XM_ISRC, &Isrc);
30080 SkXmAutoNegLipaXmac(pAC, IoC, Port, IsrcSum);
30083 if ((Isrc & XM_IS_INP_ASS) == 0) {
30084 /* It has been in sync since last time */
30085 /* Restart the PORT */
30086 @@ -1101,14 +1565,14 @@
30087 * Link Restart Workaround:
30088 * it may be possible that the other Link side
30089 * restarts its link as well an we detect
30090 - * another LinkBroken. To prevent this
30091 + * another PLinkBroken. To prevent this
30092 * happening we check for a maximum number
30093 * of consecutive restart. If those happens,
30094 * we do NOT restart the active link and
30095 * check whether the link is now o.k.
30097 pPrt->PLinkResCt++;
30100 pPrt->PAutoNegTimeOut = 0;
30102 if (pPrt->PLinkResCt < SK_MAX_LRESTART) {
30103 @@ -1116,13 +1580,13 @@
30106 pPrt->PLinkResCt = 0;
30109 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30110 ("Do NOT restart on Port %d %x %x\n", Port, Isrc, IsrcSum));
30113 pPrt->PIsave = (SK_U16)(IsrcSum & XM_IS_AND);
30116 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30117 ("Save Sync/nosync Port %d %x %x\n", Port, Isrc, IsrcSum));
30119 @@ -1149,7 +1613,7 @@
30120 if ((Isrc & XM_IS_INP_ASS) != 0) {
30121 pPrt->PLinkBroken = SK_TRUE;
30122 /* Re-Init Link partner Autoneg flag */
30123 - pPrt->PLipaAutoNeg = SK_LIPA_UNKNOWN;
30124 + pPrt->PLipaAutoNeg = (SK_U8)SK_LIPA_UNKNOWN;
30125 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
30126 ("Link broken Port %d\n", Port));
30128 @@ -1162,7 +1626,7 @@
30131 SkXmAutoNegLipaXmac(pAC, IoC, Port, Isrc);
30134 if (SkGePortCheckShorts(pAC, IoC, Port) == SK_HW_PS_RESTART) {
30135 return(SK_HW_PS_RESTART);
30137 @@ -1178,7 +1642,7 @@
30140 SkXmAutoNegLipaXmac(pAC, IoC, Port, IsrcSum);
30143 if ((GpReg & XM_GP_INP_ASS) != 0 || (IsrcSum & XM_IS_INP_ASS) != 0) {
30144 if ((GpReg & XM_GP_INP_ASS) == 0) {
30145 /* Save Auto-negotiation Done interrupt only if link is in sync */
30146 @@ -1194,20 +1658,26 @@
30150 + /* Auto-Negotiation Done ? */
30151 if ((IsrcSum & XM_IS_AND) != 0) {
30153 SkHWLinkUp(pAC, IoC, Port);
30155 Done = SkMacAutoNegDone(pAC, IoC, Port);
30157 if (Done != SK_AND_OK) {
30158 /* Get PHY parameters, for debugging only */
30159 SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_AUNE_LP, &LpAb);
30160 SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_RES_ABI, &ResAb);
30161 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30162 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
30163 ("AutoNeg FAIL Port %d (LpAb %x, ResAb %x)\n",
30164 - Port, LpAb, ResAb));
30166 + Port, LpAb, ResAb));
30168 /* Try next possible mode */
30169 NextMode = SkHWSenseGetNext(pAC, IoC, Port);
30171 SkHWLinkDown(pAC, IoC, Port);
30173 if (Done == SK_AND_DUP_CAP) {
30174 /* GoTo next mode */
30175 SkHWSenseSetNext(pAC, IoC, Port, NextMode);
30176 @@ -1220,42 +1690,41 @@
30177 * (clear Page Received bit if set)
30179 SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_AUNE_EXP, &ExtStat);
30182 return(SK_HW_PS_LINK);
30186 /* AutoNeg not done, but HW link is up. Check for timeouts */
30187 - pPrt->PAutoNegTimeOut++;
30188 - if (pPrt->PAutoNegTimeOut >= SK_AND_MAX_TO) {
30189 + if (pPrt->PAutoNegTimeOut++ >= SK_AND_MAX_TO) {
30190 /* Increase the Timeout counter */
30191 pPrt->PAutoNegTOCt++;
30193 /* Timeout occured */
30194 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
30195 ("AutoNeg timeout Port %d\n", Port));
30196 - if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE &&
30197 - pPrt->PLipaAutoNeg != SK_LIPA_AUTO) {
30198 + if (pPrt->PLinkModeConf == (SK_U8)SK_LMODE_AUTOSENSE &&
30199 + pPrt->PLipaAutoNeg != (SK_U8)SK_LIPA_AUTO) {
30200 /* Set Link manually up */
30201 SkHWSenseSetNext(pAC, IoC, Port, SK_LMODE_FULL);
30202 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
30203 ("Set manual full duplex Port %d\n", Port));
30206 - if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE &&
30207 - pPrt->PLipaAutoNeg == SK_LIPA_AUTO &&
30208 + if (pPrt->PLinkModeConf == (SK_U8)SK_LMODE_AUTOSENSE &&
30209 + pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_AUTO &&
30210 pPrt->PAutoNegTOCt >= SK_MAX_ANEG_TO) {
30212 * This is rather complicated.
30213 * we need to check here whether the LIPA_AUTO
30214 * we saw before is false alert. We saw at one
30215 - * switch ( SR8800) that on boot time it sends
30216 + * switch (SR8800) that on boot time it sends
30217 * just one auto-neg packet and does no further
30218 * auto-negotiation.
30219 * Solution: we restart the autosensing after
30222 pPrt->PAutoNegTOCt = 0;
30223 - pPrt->PLipaAutoNeg = SK_LIPA_UNKNOWN;
30224 + pPrt->PLipaAutoNeg = (SK_U8)SK_LIPA_UNKNOWN;
30225 SkHWInitDefSense(pAC, IoC, Port);
30228 @@ -1266,18 +1735,18 @@
30230 /* Link is up and we don't need more */
30232 - if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) {
30233 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30234 + if (pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_AUTO) {
30235 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
30236 ("ERROR: Lipa auto detected on port %d\n", Port));
30239 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
30240 ("Link sync(GP), Port %d\n", Port));
30241 SkHWLinkUp(pAC, IoC, Port);
30245 - * Link sync (GP) and so assume a good connection. But if not received
30246 - * a bunch of frames received in a time slot (maybe broken tx cable)
30247 + * Link sync (GP) and so assume a good connection. But if no
30248 + * bunch of frames received in a time slot (maybe broken Tx cable)
30249 * the port is restart.
30251 return(SK_HW_PS_LINK);
30252 @@ -1298,14 +1767,14 @@
30254 static int SkGePortCheckUpBcom(
30255 SK_AC *pAC, /* Adapter Context */
30256 -SK_IOC IoC, /* IO Context */
30257 -int Port, /* Which port should be checked */
30258 +SK_IOC IoC, /* I/O Context */
30259 +int Port, /* Port Index (MAC_1 + n) */
30260 SK_BOOL AutoNeg) /* Is Auto-negotiation used ? */
30262 SK_GEPORT *pPrt; /* GIni Port struct pointer */
30264 SK_U16 Isrc; /* Interrupt source register */
30265 - SK_U16 PhyStat; /* Phy Status Register */
30266 + SK_U16 PhyStat; /* PHY Status Register */
30267 SK_U16 ResAb; /* Master/Slave resolution */
30268 SK_U16 Ctrl; /* Broadcom control flags */
30270 @@ -1318,74 +1787,6 @@
30271 /* Check for No HCD Link events (#10523) */
30272 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_STAT, &Isrc);
30275 - if ((Isrc & ~(PHY_B_IS_HCT | PHY_B_IS_LCT) ==
30276 - (PHY_B_IS_SCR_S_ER | PHY_B_IS_RRS_CHANGE | PHY_B_IS_LRS_CHANGE)) {
30278 - SK_U32 Stat1, Stat2, Stat3;
30281 - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_MASK, &Stat1);
30283 - pAC->pConfigTable,
30284 - MSG_TYPE_RUNTIME_INFO,
30285 - "CheckUp1 - Stat: %x, Mask: %x",
30290 - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_CTRL, &Stat1);
30292 - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_STAT, &Stat2);
30293 - Stat1 = Stat1 << 16 | Stat2;
30295 - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_ADV, &Stat2);
30297 - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &Stat3);
30298 - Stat2 = Stat2 << 16 | Stat3;
30300 - pAC->pConfigTable,
30301 - MSG_TYPE_RUNTIME_INFO,
30302 - "Ctrl/Stat: %x, AN Adv/LP: %x",
30307 - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_EXP, &Stat1);
30309 - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_EXT_STAT, &Stat2);
30310 - Stat1 = Stat1 << 16 | Stat2;
30312 - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_CTRL, &Stat2);
30314 - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &Stat3);
30315 - Stat2 = Stat2 << 16 | Stat3;
30317 - pAC->pConfigTable,
30318 - MSG_TYPE_RUNTIME_INFO,
30319 - "AN Exp/IEEE Ext: %x, 1000T Ctrl/Stat: %x",
30324 - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_CTRL, &Stat1);
30326 - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_STAT, &Stat2);
30327 - Stat1 = Stat1 << 16 | Stat2;
30329 - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &Stat2);
30331 - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_STAT, &Stat3);
30332 - Stat2 = Stat2 << 16 | Stat3;
30334 - pAC->pConfigTable,
30335 - MSG_TYPE_RUNTIME_INFO,
30336 - "PHY Ext Ctrl/Stat: %x, Aux Ctrl/Stat: %x",
30340 -#endif /* DEBUG */
30342 if ((Isrc & (PHY_B_IS_NO_HDCL /* | PHY_B_IS_NO_HDC */)) != 0) {
30344 * Workaround BCom Errata:
30345 @@ -1398,14 +1799,6 @@
30346 (SK_U16)(Ctrl & ~PHY_CT_LOOP));
30347 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30348 ("No HCD Link event, Port %d\n", Port));
30351 - pAC->pConfigTable,
30352 - MSG_TYPE_RUNTIME_INFO,
30353 - "No HCD link event, port %d.",
30356 -#endif /* DEBUG */
30359 /* Not obsolete: link status bit is latched to 0 and autoclearing! */
30360 @@ -1415,72 +1808,6 @@
30361 return(SK_HW_PS_NONE);
30366 - SK_U32 Stat1, Stat2, Stat3;
30369 - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_MASK, &Stat1);
30371 - pAC->pConfigTable,
30372 - MSG_TYPE_RUNTIME_INFO,
30373 - "CheckUp1a - Stat: %x, Mask: %x",
30378 - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_CTRL, &Stat1);
30380 - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_STAT, &PhyStat);
30381 - Stat1 = Stat1 << 16 | PhyStat;
30383 - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_ADV, &Stat2);
30385 - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &Stat3);
30386 - Stat2 = Stat2 << 16 | Stat3;
30388 - pAC->pConfigTable,
30389 - MSG_TYPE_RUNTIME_INFO,
30390 - "Ctrl/Stat: %x, AN Adv/LP: %x",
30395 - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_EXP, &Stat1);
30397 - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_EXT_STAT, &Stat2);
30398 - Stat1 = Stat1 << 16 | Stat2;
30400 - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_CTRL, &Stat2);
30402 - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &ResAb);
30403 - Stat2 = Stat2 << 16 | ResAb;
30405 - pAC->pConfigTable,
30406 - MSG_TYPE_RUNTIME_INFO,
30407 - "AN Exp/IEEE Ext: %x, 1000T Ctrl/Stat: %x",
30412 - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_CTRL, &Stat1);
30414 - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_STAT, &Stat2);
30415 - Stat1 = Stat1 << 16 | Stat2;
30417 - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &Stat2);
30419 - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_STAT, &Stat3);
30420 - Stat2 = Stat2 << 16 | Stat3;
30422 - pAC->pConfigTable,
30423 - MSG_TYPE_RUNTIME_INFO,
30424 - "PHY Ext Ctrl/Stat: %x, Aux Ctrl/Stat: %x",
30428 -#endif /* DEBUG */
30431 * Here we usually can check whether the link is in sync and
30432 * auto-negotiation is done.
30433 @@ -1489,7 +1816,7 @@
30434 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_STAT, &PhyStat);
30436 SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat);
30439 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30440 ("CheckUp Port %d, PhyStat: 0x%04X\n", Port, PhyStat));
30442 @@ -1497,88 +1824,62 @@
30444 if ((ResAb & PHY_B_1000S_MSF) != 0) {
30446 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30447 - ("Master/Slave Fault port %d\n", Port));
30449 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
30450 + ("Master/Slave Fault, ResAb: 0x%04X\n", ResAb));
30452 pPrt->PAutoNegFail = SK_TRUE;
30453 pPrt->PMSStatus = SK_MS_STAT_FAULT;
30456 return(SK_HW_PS_RESTART);
30459 if ((PhyStat & PHY_ST_LSYNC) == 0) {
30460 return(SK_HW_PS_NONE);
30464 pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
30465 SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE;
30468 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30469 ("Port %d, ResAb: 0x%04X\n", Port, ResAb));
30472 + /* Auto-Negotiation Over ? */
30473 if ((PhyStat & PHY_ST_AN_OVER) != 0) {
30476 SkHWLinkUp(pAC, IoC, Port);
30479 Done = SkMacAutoNegDone(pAC, IoC, Port);
30482 if (Done != SK_AND_OK) {
30484 /* Get PHY parameters, for debugging only */
30485 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &LpAb);
30486 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &ExtStat);
30487 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30488 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
30489 ("AutoNeg FAIL Port %d (LpAb %x, 1000TStat %x)\n",
30490 Port, LpAb, ExtStat));
30492 return(SK_HW_PS_RESTART);
30496 - /* Dummy read ISR to prevent extra link downs/ups */
30497 - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_STAT, &ExtStat);
30499 - if ((ExtStat & ~(PHY_B_IS_HCT | PHY_B_IS_LCT)) != 0) {
30501 - pAC->pConfigTable,
30502 - MSG_TYPE_RUNTIME_INFO,
30503 - "CheckUp2 - Stat: %x",
30507 -#endif /* DEBUG */
30508 return(SK_HW_PS_LINK);
30512 else { /* !AutoNeg */
30513 - /* Link is up and we don't need more. */
30514 + /* Link is up and we don't need more */
30516 - if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) {
30517 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30518 + if (pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_AUTO) {
30519 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
30520 ("ERROR: Lipa auto detected on port %d\n", Port));
30525 - /* Dummy read ISR to prevent extra link downs/ups */
30526 - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_STAT, &ExtStat);
30528 - if ((ExtStat & ~(PHY_B_IS_HCT | PHY_B_IS_LCT)) != 0) {
30530 - pAC->pConfigTable,
30531 - MSG_TYPE_RUNTIME_INFO,
30532 - "CheckUp3 - Stat: %x",
30536 -#endif /* DEBUG */
30538 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
30539 ("Link sync(GP), Port %d\n", Port));
30540 SkHWLinkUp(pAC, IoC, Port);
30543 return(SK_HW_PS_LINK);
30546 @@ -1599,17 +1900,18 @@
30548 static int SkGePortCheckUpGmac(
30549 SK_AC *pAC, /* Adapter Context */
30550 -SK_IOC IoC, /* IO Context */
30551 -int Port, /* Which port should be checked */
30552 +SK_IOC IoC, /* I/O Context */
30553 +int Port, /* Port Index (MAC_1 + n) */
30554 SK_BOOL AutoNeg) /* Is Auto-negotiation used ? */
30556 SK_GEPORT *pPrt; /* GIni Port struct pointer */
30558 - SK_U16 PhyIsrc; /* PHY Interrupt source */
30559 - SK_U16 PhyStat; /* PPY Status */
30560 + SK_U16 PhyStat; /* PHY Status */
30561 SK_U16 PhySpecStat;/* PHY Specific Status */
30562 SK_U16 ResAb; /* Master/Slave resolution */
30565 +#endif /* !SK_SLIM */
30567 SK_U16 Word; /* I/O helper */
30569 @@ -1626,107 +1928,145 @@
30570 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30571 ("CheckUp Port %d, PhyStat: 0x%04X\n", Port, PhyStat));
30573 - /* Read PHY Interrupt Status */
30574 - SkGmPhyRead(pAC, IoC, Port, PHY_MARV_INT_STAT, &PhyIsrc);
30575 + SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat);
30577 - if ((PhyIsrc & PHY_M_IS_AN_COMPL) != 0) {
30578 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30579 - ("Auto-Negotiation Completed, PhyIsrc: 0x%04X\n", PhyIsrc));
30581 + if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
30583 - if ((PhyIsrc & PHY_M_IS_LSP_CHANGE) != 0) {
30584 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30585 - ("Link Speed Changed, PhyIsrc: 0x%04X\n", PhyIsrc));
30587 + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_STAT, &ResAb);
30589 - SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat);
30591 - SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_STAT, &ResAb);
30592 + if ((ResAb & PHY_B_1000S_MSF) != 0) {
30594 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
30595 + ("Master/Slave Fault, ResAb: 0x%04X\n", ResAb));
30597 - if ((ResAb & PHY_B_1000S_MSF) != 0) {
30599 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30600 - ("Master/Slave Fault port %d\n", Port));
30602 - pPrt->PAutoNegFail = SK_TRUE;
30603 - pPrt->PMSStatus = SK_MS_STAT_FAULT;
30605 - return(SK_HW_PS_RESTART);
30606 + pPrt->PAutoNegFail = SK_TRUE;
30607 + pPrt->PMSStatus = SK_MS_STAT_FAULT;
30609 + return(SK_HW_PS_RESTART);
30613 /* Read PHY Specific Status */
30614 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &PhySpecStat);
30617 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30618 ("Phy1000BT: 0x%04X, PhySpecStat: 0x%04X\n", ResAb, PhySpecStat));
30621 +#if (defined(DEBUG) && !defined(SK_SLIM))
30622 + /* Read PHY Auto-Negotiation Expansion */
30623 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_EXP, &Word);
30625 - if ((PhyIsrc & PHY_M_IS_AN_PR) != 0 || (Word & PHY_ANE_RX_PG) != 0 ||
30626 - (PhySpecStat & PHY_M_PS_PAGE_REC) != 0) {
30627 + if (pAC->GIni.GICopperType && (Word & PHY_ANE_LP_CAP) == 0) {
30629 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30630 + ("Link Partner not Auto-Neg. able, AN Exp.: 0x%04X\n", Word));
30633 + if ((Word & PHY_ANE_RX_PG) != 0 ||
30634 + (PhySpecStat & PHY_M_PS_PAGE_REC) != 0) {
30635 /* Read PHY Next Page Link Partner */
30636 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_NEPG_LP, &Word);
30638 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30639 - ("Page Received, NextPage: 0x%04X\n", Word));
30640 + ("Page received, NextPage: 0x%04X\n", Word));
30642 -#endif /* DEBUG */
30643 +#endif /* DEBUG && !SK_SLIM */
30645 if ((PhySpecStat & PHY_M_PS_LINK_UP) == 0) {
30647 return(SK_HW_PS_NONE);
30650 - if ((PhySpecStat & PHY_M_PS_DOWNS_STAT) != 0 ||
30651 - (PhyIsrc & PHY_M_IS_DOWNSH_DET) != 0) {
30652 - /* Downshift detected */
30653 - SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E025, SKERR_SIRQ_E025MSG);
30655 - Para.Para64 = Port;
30656 - SkEventQueue(pAC, SKGE_DRV, SK_DRV_DOWNSHIFT_DET, Para);
30658 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30659 - ("Downshift detected, PhyIsrc: 0x%04X\n", PhyIsrc));
30663 + /* Read PHY Interrupt Status */
30664 + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_INT_STAT, &PhyInt);
30666 + /* cross check that the link is really up */
30667 + if ((PhyInt & PHY_M_IS_LST_CHANGE) == 0) {
30668 + /* Link Status unchanged */
30669 + return(SK_HW_PS_NONE);
30674 + if (pAC->GIni.GICopperType) {
30676 + if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
30678 + if ((PhySpecStat & PHY_M_PS_DOWNS_STAT) != 0) {
30679 + /* Downshift detected */
30680 + Para.Para64 = Port;
30681 + SkEventQueue(pAC, SKGE_DRV, SK_DRV_DOWNSHIFT_DET, Para);
30683 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30684 + ("Downshift detected, PhySpecStat: 0x%04X\n", PhySpecStat));
30686 + SK_ERR_LOG(pAC, SK_ERRCL_CONFIG, SKERR_SIRQ_E025,
30687 + SKERR_SIRQ_E025MSG);
30690 + pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
30691 + SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE;
30694 + if ((PhySpecStat & PHY_M_PS_MDI_X_STAT) != 0) {
30695 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30696 + ("MDI Xover detected, PhyStat: 0x%04X\n", PhySpecStat));
30699 + /* on PHY 88E1112 & 88E1145 cable length is in Reg. 26, Page 5 */
30700 + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL ||
30701 + pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) {
30702 + /* select page 5 to access VCT DSP distance register */
30703 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 5);
30705 + /* get VCT DSP distance */
30706 + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL_2, &PhySpecStat);
30708 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0);
30710 + pPrt->PCableLen = (SK_U8)(PhySpecStat & PHY_M_EC2_FO_AM_MSK);
30713 + pPrt->PCableLen = (SK_U8)((PhySpecStat & PHY_M_PS_CABLE_MSK) >> 7);
30716 +#endif /* !SK_SLIM */
30718 - pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
30719 - SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE;
30721 - pPrt->PCableLen = (SK_U8)((PhySpecStat & PHY_M_PS_CABLE_MSK) >> 7);
30724 - /* Auto-Negotiation Over ? */
30725 + /* Auto-Negotiation Complete ? */
30726 if ((PhyStat & PHY_ST_AN_OVER) != 0) {
30729 SkHWLinkUp(pAC, IoC, Port);
30732 Done = SkMacAutoNegDone(pAC, IoC, Port);
30735 if (Done != SK_AND_OK) {
30736 return(SK_HW_PS_RESTART);
30740 return(SK_HW_PS_LINK);
30743 else { /* !AutoNeg */
30744 - /* Link is up and we don't need more */
30746 - if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) {
30747 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30748 +#if (defined(DEBUG) && !defined(SK_SLIM))
30749 + if (pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_AUTO) {
30750 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
30751 ("ERROR: Lipa auto detected on port %d\n", Port));
30753 -#endif /* DEBUG */
30754 +#endif /* DEBUG && !SK_SLIM */
30756 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
30757 ("Link sync, Port %d\n", Port));
30758 SkHWLinkUp(pAC, IoC, Port);
30761 return(SK_HW_PS_LINK);
30764 return(SK_HW_PS_NONE);
30765 } /* SkGePortCheckUpGmac */
30770 @@ -1742,8 +2082,8 @@
30772 static int SkGePortCheckUpLone(
30773 SK_AC *pAC, /* Adapter Context */
30774 -SK_IOC IoC, /* IO Context */
30775 -int Port, /* Which port should be checked */
30776 +SK_IOC IoC, /* I/O Context */
30777 +int Port, /* Port Index (MAC_1 + n) */
30778 SK_BOOL AutoNeg) /* Is Auto-negotiation used ? */
30780 SK_GEPORT *pPrt; /* GIni Port struct pointer */
30781 @@ -1751,7 +2091,7 @@
30782 SK_U16 Isrc; /* Interrupt source register */
30783 SK_U16 LpAb; /* Link Partner Ability */
30784 SK_U16 ExtStat; /* Extended Status Register */
30785 - SK_U16 PhyStat; /* Phy Status Register */
30786 + SK_U16 PhyStat; /* PHY Status Register */
30788 SK_U8 NextMode; /* Next AutoSensing Mode */
30790 @@ -1772,7 +2112,7 @@
30791 StatSum |= PhyStat;
30793 SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat);
30796 if ((PhyStat & PHY_ST_LSYNC) == 0) {
30797 /* Save Auto-negotiation Done bit */
30798 pPrt->PIsave = (SK_U16)(StatSum & PHY_ST_AN_OVER);
30799 @@ -1786,20 +2126,26 @@
30803 + /* Auto-Negotiation Over ? */
30804 if ((StatSum & PHY_ST_AN_OVER) != 0) {
30806 SkHWLinkUp(pAC, IoC, Port);
30808 Done = SkMacAutoNegDone(pAC, IoC, Port);
30810 if (Done != SK_AND_OK) {
30811 /* Get PHY parameters, for debugging only */
30812 SkXmPhyRead(pAC, IoC, Port, PHY_LONE_AUNE_LP, &LpAb);
30813 SkXmPhyRead(pAC, IoC, Port, PHY_LONE_1000T_STAT, &ExtStat);
30814 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30815 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
30816 ("AutoNeg FAIL Port %d (LpAb %x, 1000TStat %x)\n",
30817 Port, LpAb, ExtStat));
30820 /* Try next possible mode */
30821 NextMode = SkHWSenseGetNext(pAC, IoC, Port);
30823 SkHWLinkDown(pAC, IoC, Port);
30825 if (Done == SK_AND_DUP_CAP) {
30826 /* GoTo next mode */
30827 SkHWSenseSetNext(pAC, IoC, Port, NextMode);
30828 @@ -1817,15 +2163,14 @@
30829 return(SK_HW_PS_LINK);
30834 /* AutoNeg not done, but HW link is up. Check for timeouts */
30835 - pPrt->PAutoNegTimeOut++;
30836 - if (pPrt->PAutoNegTimeOut >= SK_AND_MAX_TO) {
30837 + if (pPrt->PAutoNegTimeOut++ >= SK_AND_MAX_TO) {
30838 /* Timeout occured */
30839 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
30840 ("AutoNeg timeout Port %d\n", Port));
30841 - if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE &&
30842 - pPrt->PLipaAutoNeg != SK_LIPA_AUTO) {
30843 + if (pPrt->PLinkModeConf == (SK_U8)SK_LMODE_AUTOSENSE &&
30844 + pPrt->PLipaAutoNeg != (SK_U8)SK_LIPA_AUTO) {
30845 /* Set Link manually up */
30846 SkHWSenseSetNext(pAC, IoC, Port, SK_LMODE_FULL);
30847 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
30848 @@ -1839,8 +2184,8 @@
30850 /* Link is up and we don't need more */
30852 - if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) {
30853 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30854 + if (pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_AUTO) {
30855 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
30856 ("ERROR: Lipa auto detected on port %d\n", Port));
30859 @@ -1850,11 +2195,12 @@
30860 * extra link down/ups
30862 SkXmPhyRead(pAC, IoC, Port, PHY_LONE_INT_STAT, &ExtStat);
30865 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
30866 ("Link sync(GP), Port %d\n", Port));
30868 SkHWLinkUp(pAC, IoC, Port);
30871 return(SK_HW_PS_LINK);
30874 @@ -1873,8 +2219,8 @@
30876 static int SkGePortCheckUpNat(
30877 SK_AC *pAC, /* Adapter Context */
30878 -SK_IOC IoC, /* IO Context */
30879 -int Port, /* Which port should be checked */
30880 +SK_IOC IoC, /* I/O Context */
30881 +int Port, /* Port Index (MAC_1 + n) */
30882 SK_BOOL AutoNeg) /* Is Auto-negotiation used ? */
30884 /* todo: National */
30885 @@ -1893,38 +2239,40 @@
30888 SK_AC *pAC, /* Adapter Context */
30889 -SK_IOC IoC, /* Io Context */
30890 +SK_IOC IoC, /* I/O Context */
30891 SK_U32 Event, /* Module specific Event */
30892 SK_EVPARA Para) /* Event specific Parameter */
30894 SK_GEPORT *pPrt; /* GIni Port struct pointer */
30904 #endif /* GENESIS */
30906 - Port = Para.Para32[0];
30907 + Port = (int)Para.Para32[0];
30908 pPrt = &pAC->GIni.GP[Port];
30911 case SK_HWEV_WATIM:
30912 if (pPrt->PState == SK_PRT_RESET) {
30915 PortStat = SK_HW_PS_NONE;
30918 /* Check whether port came up */
30919 - PortStat = SkGePortCheckUp(pAC, IoC, (int)Port);
30920 + PortStat = SkGePortCheckUp(pAC, IoC, Port);
30923 switch (PortStat) {
30924 case SK_HW_PS_RESTART:
30925 if (pPrt->PHWLinkUp) {
30926 /* Set Link to down */
30927 - SkHWLinkDown(pAC, IoC, (int)Port);
30928 + SkHWLinkDown(pAC, IoC, Port);
30931 * Signal directly to RLMT to ensure correct
30932 @@ -1942,22 +2290,28 @@
30933 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_UP, Para);
30938 /* Start again the check Timer */
30939 if (pPrt->PHWLinkUp) {
30941 Val32 = SK_WA_ACT_TIME;
30944 Val32 = SK_WA_INA_TIME;
30947 - /* Todo: still needed for non-XMAC PHYs??? */
30948 + if (pAC->GIni.GIYukon) {
30952 /* Start workaround Errata #2 timer */
30953 SkTimerStart(pAC, IoC, &pPrt->PWaTimer, Val32,
30954 SKGE_HWAC, SK_HWEV_WATIM, Para);
30958 case SK_HWEV_PORT_START:
30961 if (pPrt->PHWLinkUp) {
30963 * Signal directly to RLMT to ensure correct
30964 @@ -1965,8 +2319,9 @@
30966 SkRlmtEvent(pAC, IoC, SK_RLMT_LINK_DOWN, Para);
30968 +#endif /* !SK_SLIM */
30970 - SkHWLinkDown(pAC, IoC, (int)Port);
30971 + SkHWLinkDown(pAC, IoC, Port);
30973 /* Schedule Port RESET */
30974 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Para);
30975 @@ -1974,9 +2329,11 @@
30976 /* Start workaround Errata #2 timer */
30977 SkTimerStart(pAC, IoC, &pPrt->PWaTimer, SK_WA_INA_TIME,
30978 SKGE_HWAC, SK_HWEV_WATIM, Para);
30982 case SK_HWEV_PORT_STOP:
30984 if (pPrt->PHWLinkUp) {
30986 * Signal directly to RLMT to ensure correct
30987 @@ -1984,20 +2341,22 @@
30989 SkRlmtEvent(pAC, IoC, SK_RLMT_LINK_DOWN, Para);
30991 +#endif /* !SK_SLIM */
30993 /* Stop Workaround Timer */
30994 SkTimerStop(pAC, IoC, &pPrt->PWaTimer);
30996 - SkHWLinkDown(pAC, IoC, (int)Port);
30997 + SkHWLinkDown(pAC, IoC, Port);
31001 case SK_HWEV_UPDATE_STAT:
31002 /* We do NOT need to update any statistics */
31005 case SK_HWEV_CLEAR_STAT:
31006 /* We do NOT need to clear any statistics */
31007 - for (Port = 0; Port < (SK_U32)pAC->GIni.GIMacsFound; Port++) {
31008 + for (Port = 0; Port < pAC->GIni.GIMacsFound; Port++) {
31010 pPrt->PPrevFcs = 0;
31011 pPrt->PPrevShorts = 0;
31012 @@ -2058,6 +2417,7 @@
31013 SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_START, Para);
31016 +#endif /* !SK_SLIM */
31019 case SK_HWEV_HALFDUP_CHK:
31020 @@ -2069,17 +2429,18 @@
31021 pPrt->HalfDupTimerActive = SK_FALSE;
31022 if (pPrt->PLinkModeStatus == SK_LMODE_STAT_HALF ||
31023 pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOHALF) {
31025 /* Snap statistic counters */
31026 (void)SkXmUpdateStats(pAC, IoC, Port);
31028 (void)SkXmMacStatistic(pAC, IoC, Port, XM_TXO_OK_HI, &Val32);
31030 Octets = (SK_U64)Val32 << 32;
31033 (void)SkXmMacStatistic(pAC, IoC, Port, XM_TXO_OK_LO, &Val32);
31038 if (pPrt->LastOctets == Octets) {
31039 /* Tx hanging, a FIFO flush restarts it */
31040 SkMacFlushTxFifo(pAC, IoC, Port);
31041 @@ -2088,7 +2449,7 @@
31044 #endif /* GENESIS */
31048 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_SIRQ_E001, SKERR_SIRQ_E001MSG);
31050 @@ -2109,8 +2470,8 @@
31052 static void SkPhyIsrBcom(
31053 SK_AC *pAC, /* Adapter Context */
31054 -SK_IOC IoC, /* Io Context */
31055 -int Port, /* Port Num = PHY Num */
31056 +SK_IOC IoC, /* I/O Context */
31057 +int Port, /* Port Index (MAC_1 + n) */
31058 SK_U16 IStatus) /* Interrupt Status */
31060 SK_GEPORT *pPrt; /* GIni Port struct pointer */
31061 @@ -2123,7 +2484,7 @@
31062 SK_ERR_LOG(pAC, SK_ERRCL_HW | SK_ERRCL_INIT, SKERR_SIRQ_E022,
31063 SKERR_SIRQ_E022MSG);
31067 if ((IStatus & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) != 0) {
31069 SkHWLinkDown(pAC, IoC, Port);
31070 @@ -2152,47 +2513,83 @@
31072 static void SkPhyIsrGmac(
31073 SK_AC *pAC, /* Adapter Context */
31074 -SK_IOC IoC, /* Io Context */
31075 -int Port, /* Port Num = PHY Num */
31076 +SK_IOC IoC, /* I/O Context */
31077 +int Port, /* Port Index (MAC_1 + n) */
31078 SK_U16 IStatus) /* Interrupt Status */
31080 - SK_GEPORT *pPrt; /* GIni Port struct pointer */
31081 + SK_GEPORT *pPrt; /* GIni Port struct pointer */
31087 pPrt = &pAC->GIni.GP[Port];
31089 - if ((IStatus & (PHY_M_IS_AN_PR | PHY_M_IS_LST_CHANGE)) != 0) {
31091 - SkHWLinkDown(pAC, IoC, Port);
31092 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
31093 + ("Port %d PHY IRQ, PhyIsrc: 0x%04X\n", Port, IStatus));
31095 - SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_ADV, &Word);
31096 + if ((IStatus & PHY_M_IS_LST_CHANGE) != 0) {
31098 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
31099 - ("AutoNeg.Adv: 0x%04X\n", Word));
31101 - /* Set Auto-negotiation advertisement */
31102 - if (pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM) {
31103 - /* restore Asymmetric Pause bit */
31104 - SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_AUNE_ADV,
31105 - (SK_U16)(Word | PHY_M_AN_ASP));
31108 + ("Link Status changed\n"));
31110 Para.Para32[0] = (SK_U32)Port;
31111 - /* Signal to RLMT */
31112 - SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
31114 + if (pPrt->PHWLinkUp) {
31116 + SkHWLinkDown(pAC, IoC, Port);
31119 + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_ADV, &Word);
31121 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
31122 + ("AutoNeg.Adv: 0x%04X\n", Word));
31124 + /* Set Auto-negotiation advertisement */
31125 + if (pAC->GIni.GIChipId != CHIP_ID_YUKON_FE &&
31126 + pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM) {
31127 + /* restore Asymmetric Pause bit */
31128 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_AUNE_ADV,
31129 + (SK_U16)(Word | PHY_M_AN_ASP));
31133 + /* Signal to RLMT */
31134 + SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
31137 + if ((IStatus & PHY_M_IS_AN_COMPL) != 0) {
31138 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
31139 + ("Auto-Negotiation completed\n"));
31142 + if ((IStatus & PHY_M_IS_LSP_CHANGE) != 0) {
31143 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
31144 + ("Link Speed changed\n"));
31147 + SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_WATIM, Para);
31152 if ((IStatus & PHY_M_IS_AN_ERROR) != 0) {
31153 - /* Auto-Negotiation Error */
31154 - SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E023, SKERR_SIRQ_E023MSG);
31155 + /* the copper PHY makes 1 retry */
31156 + if (pAC->GIni.GICopperType) {
31157 + /* not logged as error, it might be the first attempt */
31158 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
31159 + ("Auto-Negotiation Error\n"));
31162 + /* Auto-Negotiation Error */
31163 + SK_ERR_LOG(pAC, SK_ERRCL_CONFIG, SKERR_SIRQ_E023, SKERR_SIRQ_E023MSG);
31168 if ((IStatus & PHY_M_IS_FIFO_ERROR) != 0) {
31169 /* FIFO Overflow/Underrun Error */
31170 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E024, SKERR_SIRQ_E024MSG);
31174 } /* SkPhyIsrGmac */
31177 @@ -2208,14 +2605,14 @@
31179 static void SkPhyIsrLone(
31180 SK_AC *pAC, /* Adapter Context */
31181 -SK_IOC IoC, /* Io Context */
31182 -int Port, /* Port Num = PHY Num */
31183 +SK_IOC IoC, /* I/O Context */
31184 +int Port, /* Port Index (MAC_1 + n) */
31185 SK_U16 IStatus) /* Interrupt Status */
31189 if (IStatus & (PHY_L_IS_DUP | PHY_L_IS_ISOL)) {
31192 SkHWLinkDown(pAC, IoC, Port);
31194 Para.Para32[0] = (SK_U32)Port;
31195 @@ -2227,3 +2624,4 @@
31196 #endif /* OTHER_PHY */
31200 diff -ruN linux/drivers/net/sk98lin/ski2c.c linux-new/drivers/net/sk98lin/ski2c.c
31201 --- linux/drivers/net/sk98lin/ski2c.c 2006-09-20 05:42:06.000000000 +0200
31202 +++ linux-new/drivers/net/sk98lin/ski2c.c 1970-01-01 01:00:00.000000000 +0100
31204 -/******************************************************************************
31207 - * Project: Gigabit Ethernet Adapters, TWSI-Module
31208 - * Version: $Revision$
31210 - * Purpose: Functions to access Voltage and Temperature Sensor
31212 - ******************************************************************************/
31214 -/******************************************************************************
31216 - * (C)Copyright 1998-2002 SysKonnect.
31217 - * (C)Copyright 2002-2003 Marvell.
31219 - * This program is free software; you can redistribute it and/or modify
31220 - * it under the terms of the GNU General Public License as published by
31221 - * the Free Software Foundation; either version 2 of the License, or
31222 - * (at your option) any later version.
31224 - * The information in this file is provided "AS IS" without warranty.
31226 - ******************************************************************************/
31231 -#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
31232 -static const char SysKonnectFileId[] =
31233 - "@(#) $Id$ (C) Marvell. ";
31236 -#include "h/skdrv1st.h" /* Driver Specific Definitions */
31237 -#include "h/lm80.h"
31238 -#include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */
31242 - I2C protocol implementation.
31244 - General Description:
31246 - The I2C protocol is used for the temperature sensors and for
31247 - the serial EEPROM which hold the configuration.
31249 - This file covers functions that allow to read write and do
31250 - some bulk requests a specified I2C address.
31252 - The Genesis has 2 I2C buses. One for the EEPROM which holds
31253 - the VPD Data and one for temperature and voltage sensor.
31254 - The following picture shows the I2C buses, I2C devices and
31255 - their control registers.
31257 - Note: The VPD functions are in skvpd.c
31259 -. PCI Config I2C Bus for VPD Data:
31267 -. +-----------+-----------+
31269 -. +-----------------+ +-----------------+
31270 -. | PCI_VPD_ADR_REG | | PCI_VPD_DAT_REG |
31271 -. +-----------------+ +-----------------+
31274 -. I2C Bus for LM80 sensor:
31276 -. +-----------------+
31277 -. | Temperature and |
31278 -. | Voltage Sensor |
31280 -. +-----------------+
31286 -. +-------------->| OR |<--+
31288 -. +------+------+ |
31290 -. +--------+ +--------+ +----------+
31291 -. | B2_I2C | | B2_I2C | | B2_I2C |
31292 -. | _CTRL | | _DATA | | _SW |
31293 -. +--------+ +--------+ +----------+
31295 - The I2C bus may be driven by the B2_I2C_SW or by the B2_I2C_CTRL
31296 - and B2_I2C_DATA registers.
31297 - For driver software it is recommended to use the I2C control and
31298 - data register, because I2C bus timing is done by the ASIC and
31299 - an interrupt may be received when the I2C request is completed.
31301 - Clock Rate Timing: MIN MAX generated by
31302 - VPD EEPROM: 50 kHz 100 kHz HW
31303 - LM80 over I2C Ctrl/Data reg. 50 kHz 100 kHz HW
31304 - LM80 over B2_I2C_SW register 0 400 kHz SW
31306 - Note: The clock generated by the hardware is dependend on the
31307 - PCI clock. If the PCI bus clock is 33 MHz, the I2C/VPD
31316 - * I2C Fast Mode timing values used by the LM80.
31317 - * If new devices are added to the I2C bus the timing values have to be checked.
31319 -#ifndef I2C_SLOW_TIMING
31320 -#define T_CLK_LOW 1300L /* clock low time in ns */
31321 -#define T_CLK_HIGH 600L /* clock high time in ns */
31322 -#define T_DATA_IN_SETUP 100L /* data in Set-up Time */
31323 -#define T_START_HOLD 600L /* start condition hold time */
31324 -#define T_START_SETUP 600L /* start condition Set-up time */
31325 -#define T_STOP_SETUP 600L /* stop condition Set-up time */
31326 -#define T_BUS_IDLE 1300L /* time the bus must free after Tx */
31327 -#define T_CLK_2_DATA_OUT 900L /* max. clock low to data output valid */
31328 -#else /* I2C_SLOW_TIMING */
31329 -/* I2C Standard Mode Timing */
31330 -#define T_CLK_LOW 4700L /* clock low time in ns */
31331 -#define T_CLK_HIGH 4000L /* clock high time in ns */
31332 -#define T_DATA_IN_SETUP 250L /* data in Set-up Time */
31333 -#define T_START_HOLD 4000L /* start condition hold time */
31334 -#define T_START_SETUP 4700L /* start condition Set-up time */
31335 -#define T_STOP_SETUP 4000L /* stop condition Set-up time */
31336 -#define T_BUS_IDLE 4700L /* time the bus must free after Tx */
31337 -#endif /* !I2C_SLOW_TIMING */
31339 -#define NS2BCLK(x) (((x)*125)/10000)
31342 - * I2C Wire Operations
31344 - * About I2C_CLK_LOW():
31346 - * The Data Direction bit (I2C_DATA_DIR) has to be set to input when setting
31347 - * clock to low, to prevent the ASIC and the I2C data client from driving the
31348 - * serial data line simultaneously (ASIC: last bit of a byte = '1', I2C client
31349 - * send an 'ACK'). See also Concentrator Bugreport No. 10192.
31351 -#define I2C_DATA_HIGH(IoC) SK_I2C_SET_BIT(IoC, I2C_DATA)
31352 -#define I2C_DATA_LOW(IoC) SK_I2C_CLR_BIT(IoC, I2C_DATA)
31353 -#define I2C_DATA_OUT(IoC) SK_I2C_SET_BIT(IoC, I2C_DATA_DIR)
31354 -#define I2C_DATA_IN(IoC) SK_I2C_CLR_BIT(IoC, I2C_DATA_DIR | I2C_DATA)
31355 -#define I2C_CLK_HIGH(IoC) SK_I2C_SET_BIT(IoC, I2C_CLK)
31356 -#define I2C_CLK_LOW(IoC) SK_I2C_CLR_BIT(IoC, I2C_CLK | I2C_DATA_DIR)
31357 -#define I2C_START_COND(IoC) SK_I2C_CLR_BIT(IoC, I2C_CLK)
31359 -#define NS2CLKT(x) ((x*125L)/10000)
31361 -/*--------------- I2C Interface Register Functions --------------- */
31364 - * sending one bit
31367 -SK_IOC IoC, /* I/O Context */
31368 -SK_U8 Bit) /* Bit to send */
31370 - I2C_DATA_OUT(IoC);
31372 - I2C_DATA_HIGH(IoC);
31375 - I2C_DATA_LOW(IoC);
31377 - SkDgWaitTime(IoC, NS2BCLK(T_DATA_IN_SETUP));
31378 - I2C_CLK_HIGH(IoC);
31379 - SkDgWaitTime(IoC, NS2BCLK(T_CLK_HIGH));
31380 - I2C_CLK_LOW(IoC);
31381 -} /* SkI2cSndBit*/
31385 - * Signal a start to the I2C Bus.
31387 - * A start is signaled when data goes to low in a high clock cycle.
31389 - * Ends with Clock Low.
31391 - * Status: not tested
31394 -SK_IOC IoC) /* I/O Context */
31396 - /* Init data and Clock to output lines */
31397 - /* Set Data high */
31398 - I2C_DATA_OUT(IoC);
31399 - I2C_DATA_HIGH(IoC);
31400 - /* Set Clock high */
31401 - I2C_CLK_HIGH(IoC);
31403 - SkDgWaitTime(IoC, NS2BCLK(T_START_SETUP));
31405 - /* Set Data Low */
31406 - I2C_DATA_LOW(IoC);
31408 - SkDgWaitTime(IoC, NS2BCLK(T_START_HOLD));
31410 - /* Clock low without Data to Input */
31411 - I2C_START_COND(IoC);
31413 - SkDgWaitTime(IoC, NS2BCLK(T_CLK_LOW));
31414 -} /* SkI2cStart */
31418 -SK_IOC IoC) /* I/O Context */
31420 - /* Init data and Clock to output lines */
31421 - /* Set Data low */
31422 - I2C_DATA_OUT(IoC);
31423 - I2C_DATA_LOW(IoC);
31425 - SkDgWaitTime(IoC, NS2BCLK(T_CLK_2_DATA_OUT));
31427 - /* Set Clock high */
31428 - I2C_CLK_HIGH(IoC);
31430 - SkDgWaitTime(IoC, NS2BCLK(T_STOP_SETUP));
31433 - * Set Data High: Do it by setting the Data Line to Input.
31434 - * Because of a pull up resistor the Data Line
31435 - * floods to high.
31437 - I2C_DATA_IN(IoC);
31440 - * When I2C activity is stopped
31441 - * o DATA should be set to input and
31442 - * o CLOCK should be set to high!
31444 - SkDgWaitTime(IoC, NS2BCLK(T_BUS_IDLE));
31449 - * Receive just one bit via the I2C bus.
31451 - * Note: Clock must be set to LOW before calling this function.
31453 - * Returns The received bit.
31456 -SK_IOC IoC) /* I/O Context */
31461 - /* Init data as input line */
31462 - I2C_DATA_IN(IoC);
31464 - SkDgWaitTime(IoC, NS2BCLK(T_CLK_2_DATA_OUT));
31466 - I2C_CLK_HIGH(IoC);
31468 - SkDgWaitTime(IoC, NS2BCLK(T_CLK_HIGH));
31470 - SK_I2C_GET_SW(IoC, &I2cSwCtrl);
31472 - Bit = (I2cSwCtrl & I2C_DATA) ? 1 : 0;
31474 - I2C_CLK_LOW(IoC);
31475 - SkDgWaitTime(IoC, NS2BCLK(T_CLK_LOW-T_CLK_2_DATA_OUT));
31478 -} /* SkI2cRcvBit */
31482 - * Receive an ACK.
31484 - * returns 0 If acknowledged
31485 - * 1 in case of an error
31488 -SK_IOC IoC) /* I/O Context */
31491 - * Received bit must be zero.
31493 - return(SkI2cRcvBit(IoC) != 0);
31494 -} /* SkI2cRcvAck */
31500 -void SkI2cSndNAck(
31501 -SK_IOC IoC) /* I/O Context */
31504 - * Received bit must be zero.
31506 - SkI2cSndBit(IoC, 1);
31507 -} /* SkI2cSndNAck */
31514 -SK_IOC IoC) /* I/O Context */
31517 - * Received bit must be zero.
31519 - SkI2cSndBit(IoC, 0);
31520 -} /* SkI2cSndAck */
31524 - * Send one byte to the I2C device and wait for ACK.
31526 - * Return acknowleged status.
31529 -SK_IOC IoC, /* I/O Context */
31530 -int Byte) /* byte to send */
31534 - for (i = 0; i < 8; i++) {
31535 - if (Byte & (1<<(7-i))) {
31536 - SkI2cSndBit(IoC, 1);
31539 - SkI2cSndBit(IoC, 0);
31543 - return(SkI2cRcvAck(IoC));
31544 -} /* SkI2cSndByte */
31548 - * Receive one byte and ack it.
31553 -SK_IOC IoC, /* I/O Context */
31554 -int Last) /* Last Byte Flag */
31559 - for (i = 0; i < 8; i++) {
31561 - Byte |= SkI2cRcvBit(IoC);
31565 - SkI2cSndNAck(IoC);
31568 - SkI2cSndAck(IoC);
31572 -} /* SkI2cRcvByte */
31576 - * Start dialog and send device address
31578 - * Return 0 if acknowleged, 1 in case of an error
31581 -SK_IOC IoC, /* I/O Context */
31582 -int Addr, /* Device Address */
31583 -int Rw) /* Read / Write Flag */
31588 - return(SkI2cSndByte(IoC, (Addr<<1) | Rw));
31589 -} /* SkI2cSndDev */
31591 -#endif /* SK_DIAG */
31593 -/*----------------- I2C CTRL Register Functions ----------*/
31596 - * waits for a completion of an I2C transfer
31598 - * returns 0: success, transfer completes
31599 - * 1: error, transfer does not complete, I2C transfer
31600 - * killed, wait loop terminated.
31602 -static int SkI2cWait(
31603 -SK_AC *pAC, /* Adapter Context */
31604 -SK_IOC IoC, /* I/O Context */
31605 -int Event) /* complete event to wait for (I2C_READ or I2C_WRITE) */
31607 - SK_U64 StartTime;
31608 - SK_U64 CurrentTime;
31611 - StartTime = SkOsGetTime(pAC);
31614 - CurrentTime = SkOsGetTime(pAC);
31616 - if (CurrentTime - StartTime > SK_TICKS_PER_SEC / 8) {
31618 - SK_I2C_STOP(IoC);
31620 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E002, SKERR_I2C_E002MSG);
31621 -#endif /* !SK_DIAG */
31625 - SK_I2C_GET_CTL(IoC, &I2cCtrl);
31628 - printf("StartTime=%lu, CurrentTime=%lu\n",
31629 - StartTime, CurrentTime);
31633 -#endif /* YUKON_DBG */
31635 - } while ((I2cCtrl & I2C_FLAG) == (SK_U32)Event << 31);
31642 - * waits for a completion of an I2C transfer
31647 -void SkI2cWaitIrq(
31648 -SK_AC *pAC, /* Adapter Context */
31649 -SK_IOC IoC) /* I/O Context */
31652 - SK_U64 StartTime;
31655 - pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
31657 - if (pSen->SenState == SK_SEN_IDLE) {
31661 - StartTime = SkOsGetTime(pAC);
31664 - if (SkOsGetTime(pAC) - StartTime > SK_TICKS_PER_SEC / 8) {
31666 - SK_I2C_STOP(IoC);
31668 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E016, SKERR_I2C_E016MSG);
31669 -#endif /* !SK_DIAG */
31673 - SK_IN32(IoC, B0_ISRC, &IrqSrc);
31675 - } while ((IrqSrc & IS_I2C_READY) == 0);
31677 - pSen->SenState = SK_SEN_IDLE;
31679 -} /* SkI2cWaitIrq */
31682 - * writes a single byte or 4 bytes into the I2C device
31684 - * returns 0: success
31687 -static int SkI2cWrite(
31688 -SK_AC *pAC, /* Adapter Context */
31689 -SK_IOC IoC, /* I/O Context */
31690 -SK_U32 I2cData, /* I2C Data to write */
31691 -int I2cDev, /* I2C Device Address */
31692 -int I2cDevSize, /* I2C Device Size (e.g. I2C_025K_DEV or I2C_2K_DEV) */
31693 -int I2cReg, /* I2C Device Register Address */
31694 -int I2cBurst) /* I2C Burst Flag */
31696 - SK_OUT32(IoC, B2_I2C_DATA, I2cData);
31698 - SK_I2C_CTL(IoC, I2C_WRITE, I2cDev, I2cDevSize, I2cReg, I2cBurst);
31700 - return(SkI2cWait(pAC, IoC, I2C_WRITE));
31706 - * reads a single byte or 4 bytes from the I2C device
31708 - * returns the word read
31711 -SK_AC *pAC, /* Adapter Context */
31712 -SK_IOC IoC, /* I/O Context */
31713 -int I2cDev, /* I2C Device Address */
31714 -int I2cDevSize, /* I2C Device Size (e.g. I2C_025K_DEV or I2C_2K_DEV) */
31715 -int I2cReg, /* I2C Device Register Address */
31716 -int I2cBurst) /* I2C Burst Flag */
31720 - SK_OUT32(IoC, B2_I2C_DATA, 0);
31721 - SK_I2C_CTL(IoC, I2C_READ, I2cDev, I2cDevSize, I2cReg, I2cBurst);
31723 - if (SkI2cWait(pAC, IoC, I2C_READ) != 0) {
31724 - w_print("%s\n", SKERR_I2C_E002MSG);
31727 - SK_IN32(IoC, B2_I2C_DATA, &Data);
31731 -#endif /* SK_DIAG */
31735 - * read a sensor's value
31737 - * This function reads a sensor's value from the I2C sensor chip. The sensor
31738 - * is defined by its index into the sensors database in the struct pAC points
31741 - * 1 if the read is completed
31742 - * 0 if the read must be continued (I2C Bus still allocated)
31744 -static int SkI2cReadSensor(
31745 -SK_AC *pAC, /* Adapter Context */
31746 -SK_IOC IoC, /* I/O Context */
31747 -SK_SENSOR *pSen) /* Sensor to be read */
31749 - if (pSen->SenRead != NULL) {
31750 - return((*pSen->SenRead)(pAC, IoC, pSen));
31753 - return(0); /* no success */
31755 -} /* SkI2cReadSensor */
31758 - * Do the Init state 0 initialization
31760 -static int SkI2cInit0(
31761 -SK_AC *pAC) /* Adapter Context */
31765 - /* Begin with first sensor */
31766 - pAC->I2c.CurrSens = 0;
31768 - /* Begin with timeout control for state machine */
31769 - pAC->I2c.TimerMode = SK_TIMER_WATCH_SM;
31771 - /* Set sensor number to zero */
31772 - pAC->I2c.MaxSens = 0;
31775 - /* Initialize Number of Dummy Reads */
31776 - pAC->I2c.DummyReads = SK_MAX_SENSORS;
31779 - for (i = 0; i < SK_MAX_SENSORS; i++) {
31780 - pAC->I2c.SenTable[i].SenDesc = "unknown";
31781 - pAC->I2c.SenTable[i].SenType = SK_SEN_UNKNOWN;
31782 - pAC->I2c.SenTable[i].SenThreErrHigh = 0;
31783 - pAC->I2c.SenTable[i].SenThreErrLow = 0;
31784 - pAC->I2c.SenTable[i].SenThreWarnHigh = 0;
31785 - pAC->I2c.SenTable[i].SenThreWarnLow = 0;
31786 - pAC->I2c.SenTable[i].SenReg = LM80_FAN2_IN;
31787 - pAC->I2c.SenTable[i].SenInit = SK_SEN_DYN_INIT_NONE;
31788 - pAC->I2c.SenTable[i].SenValue = 0;
31789 - pAC->I2c.SenTable[i].SenErrFlag = SK_SEN_ERR_NOT_PRESENT;
31790 - pAC->I2c.SenTable[i].SenErrCts = 0;
31791 - pAC->I2c.SenTable[i].SenBegErrTS = 0;
31792 - pAC->I2c.SenTable[i].SenState = SK_SEN_IDLE;
31793 - pAC->I2c.SenTable[i].SenRead = NULL;
31794 - pAC->I2c.SenTable[i].SenDev = 0;
31797 - /* Now we are "INIT data"ed */
31798 - pAC->I2c.InitLevel = SK_INIT_DATA;
31804 - * Do the init state 1 initialization
31806 - * initialize the following register of the LM80:
31807 - * Configuration register:
31808 - * - START, noINT, activeLOW, noINT#Clear, noRESET, noCI, noGPO#, noINIT
31810 - * Interrupt Mask Register 1:
31811 - * - all interrupts are Disabled (0xff)
31813 - * Interrupt Mask Register 2:
31814 - * - all interrupts are Disabled (0xff) Interrupt modi doesn't matter.
31816 - * Fan Divisor/RST_OUT register:
31817 - * - Divisors set to 1 (bits 00), all others 0s.
31819 - * OS# Configuration/Temperature resolution Register:
31823 -static int SkI2cInit1(
31824 -SK_AC *pAC, /* Adapter Context */
31825 -SK_IOC IoC) /* I/O Context */
31829 - SK_GEPORT *pPrt; /* GIni Port struct pointer */
31831 - if (pAC->I2c.InitLevel != SK_INIT_DATA) {
31832 - /* ReInit not needed in I2C module */
31836 - /* Set the Direction of I2C-Data Pin to IN */
31837 - SK_I2C_CLR_BIT(IoC, I2C_DATA_DIR | I2C_DATA);
31838 - /* Check for 32-Bit Yukon with Low at I2C-Data Pin */
31839 - SK_I2C_GET_SW(IoC, &I2cSwCtrl);
31841 - if ((I2cSwCtrl & I2C_DATA) == 0) {
31842 - /* this is a 32-Bit board */
31843 - pAC->GIni.GIYukon32Bit = SK_TRUE;
31847 - /* Check for 64 Bit Yukon without sensors */
31848 - if (SkI2cWrite(pAC, IoC, 0, LM80_ADDR, I2C_025K_DEV, LM80_CFG, 0) != 0) {
31852 - (void)SkI2cWrite(pAC, IoC, 0xffUL, LM80_ADDR, I2C_025K_DEV, LM80_IMSK_1, 0);
31854 - (void)SkI2cWrite(pAC, IoC, 0xffUL, LM80_ADDR, I2C_025K_DEV, LM80_IMSK_2, 0);
31856 - (void)SkI2cWrite(pAC, IoC, 0, LM80_ADDR, I2C_025K_DEV, LM80_FAN_CTRL, 0);
31858 - (void)SkI2cWrite(pAC, IoC, 0, LM80_ADDR, I2C_025K_DEV, LM80_TEMP_CTRL, 0);
31860 - (void)SkI2cWrite(pAC, IoC, (SK_U32)LM80_CFG_START, LM80_ADDR, I2C_025K_DEV,
31864 - * MaxSens has to be updated here, because PhyType is not
31865 - * set when performing Init Level 0
31867 - pAC->I2c.MaxSens = 5;
31869 - pPrt = &pAC->GIni.GP[0];
31871 - if (pAC->GIni.GIGenesis) {
31872 - if (pPrt->PhyType == SK_PHY_BCOM) {
31873 - if (pAC->GIni.GIMacsFound == 1) {
31874 - pAC->I2c.MaxSens += 1;
31877 - pAC->I2c.MaxSens += 3;
31882 - pAC->I2c.MaxSens += 3;
31885 - for (i = 0; i < pAC->I2c.MaxSens; i++) {
31888 - pAC->I2c.SenTable[i].SenDesc = "Temperature";
31889 - pAC->I2c.SenTable[i].SenType = SK_SEN_TEMP;
31890 - pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_TEMP_HIGH_ERR;
31891 - pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_TEMP_HIGH_WARN;
31892 - pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_TEMP_LOW_WARN;
31893 - pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_TEMP_LOW_ERR;
31894 - pAC->I2c.SenTable[i].SenReg = LM80_TEMP_IN;
31897 - pAC->I2c.SenTable[i].SenDesc = "Voltage PCI";
31898 - pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
31899 - pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PCI_5V_HIGH_ERR;
31900 - pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PCI_5V_HIGH_WARN;
31901 - pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PCI_5V_LOW_WARN;
31902 - pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PCI_5V_LOW_ERR;
31903 - pAC->I2c.SenTable[i].SenReg = LM80_VT0_IN;
31906 - pAC->I2c.SenTable[i].SenDesc = "Voltage PCI-IO";
31907 - pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
31908 - pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PCI_IO_5V_HIGH_ERR;
31909 - pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PCI_IO_5V_HIGH_WARN;
31910 - pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PCI_IO_3V3_LOW_WARN;
31911 - pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PCI_IO_3V3_LOW_ERR;
31912 - pAC->I2c.SenTable[i].SenReg = LM80_VT1_IN;
31913 - pAC->I2c.SenTable[i].SenInit = SK_SEN_DYN_INIT_PCI_IO;
31916 - pAC->I2c.SenTable[i].SenDesc = "Voltage ASIC";
31917 - pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
31918 - pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_VDD_HIGH_ERR;
31919 - pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_VDD_HIGH_WARN;
31920 - pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_VDD_LOW_WARN;
31921 - pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_VDD_LOW_ERR;
31922 - pAC->I2c.SenTable[i].SenReg = LM80_VT2_IN;
31925 - if (pAC->GIni.GIGenesis) {
31926 - if (pPrt->PhyType == SK_PHY_BCOM) {
31927 - pAC->I2c.SenTable[i].SenDesc = "Voltage PHY A PLL";
31928 - pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR;
31929 - pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN;
31930 - pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN;
31931 - pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR;
31934 - pAC->I2c.SenTable[i].SenDesc = "Voltage PMA";
31935 - pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR;
31936 - pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN;
31937 - pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN;
31938 - pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR;
31942 - pAC->I2c.SenTable[i].SenDesc = "Voltage VAUX";
31943 - pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_VAUX_3V3_HIGH_ERR;
31944 - pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_VAUX_3V3_HIGH_WARN;
31945 - if (pAC->GIni.GIVauxAvail) {
31946 - pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_VAUX_3V3_LOW_WARN;
31947 - pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_VAUX_3V3_LOW_ERR;
31950 - pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_VAUX_0V_WARN_ERR;
31951 - pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_VAUX_0V_WARN_ERR;
31954 - pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
31955 - pAC->I2c.SenTable[i].SenReg = LM80_VT3_IN;
31958 - if (pAC->GIni.GIGenesis) {
31959 - pAC->I2c.SenTable[i].SenDesc = "Voltage PHY 2V5";
31960 - pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PHY_2V5_HIGH_ERR;
31961 - pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PHY_2V5_HIGH_WARN;
31962 - pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PHY_2V5_LOW_WARN;
31963 - pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PHY_2V5_LOW_ERR;
31966 - pAC->I2c.SenTable[i].SenDesc = "Voltage Core 1V5";
31967 - pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_CORE_1V5_HIGH_ERR;
31968 - pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_CORE_1V5_HIGH_WARN;
31969 - pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_CORE_1V5_LOW_WARN;
31970 - pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_CORE_1V5_LOW_ERR;
31972 - pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
31973 - pAC->I2c.SenTable[i].SenReg = LM80_VT4_IN;
31976 - if (pAC->GIni.GIGenesis) {
31977 - pAC->I2c.SenTable[i].SenDesc = "Voltage PHY B PLL";
31980 - pAC->I2c.SenTable[i].SenDesc = "Voltage PHY 3V3";
31982 - pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
31983 - pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR;
31984 - pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN;
31985 - pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN;
31986 - pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR;
31987 - pAC->I2c.SenTable[i].SenReg = LM80_VT5_IN;
31990 - if (pAC->GIni.GIGenesis) {
31991 - pAC->I2c.SenTable[i].SenDesc = "Speed Fan";
31992 - pAC->I2c.SenTable[i].SenType = SK_SEN_FAN;
31993 - pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_FAN_HIGH_ERR;
31994 - pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_FAN_HIGH_WARN;
31995 - pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_FAN_LOW_WARN;
31996 - pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_FAN_LOW_ERR;
31997 - pAC->I2c.SenTable[i].SenReg = LM80_FAN2_IN;
32000 - pAC->I2c.SenTable[i].SenDesc = "Voltage PHY 2V5";
32001 - pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
32002 - pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PHY_2V5_HIGH_ERR;
32003 - pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PHY_2V5_HIGH_WARN;
32004 - pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PHY_2V5_LOW_WARN;
32005 - pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PHY_2V5_LOW_ERR;
32006 - pAC->I2c.SenTable[i].SenReg = LM80_VT6_IN;
32010 - SK_ERR_LOG(pAC, SK_ERRCL_INIT | SK_ERRCL_SW,
32011 - SKERR_I2C_E001, SKERR_I2C_E001MSG);
32015 - pAC->I2c.SenTable[i].SenValue = 0;
32016 - pAC->I2c.SenTable[i].SenErrFlag = SK_SEN_ERR_OK;
32017 - pAC->I2c.SenTable[i].SenErrCts = 0;
32018 - pAC->I2c.SenTable[i].SenBegErrTS = 0;
32019 - pAC->I2c.SenTable[i].SenState = SK_SEN_IDLE;
32020 - pAC->I2c.SenTable[i].SenRead = SkLm80ReadSensor;
32021 - pAC->I2c.SenTable[i].SenDev = LM80_ADDR;
32025 - pAC->I2c.DummyReads = pAC->I2c.MaxSens;
32026 -#endif /* !SK_DIAG */
32028 - /* Clear I2C IRQ */
32029 - SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
32031 - /* Now we are I/O initialized */
32032 - pAC->I2c.InitLevel = SK_INIT_IO;
32034 -} /* SkI2cInit1 */
32038 - * Init level 2: Start first sensor read.
32040 -static int SkI2cInit2(
32041 -SK_AC *pAC, /* Adapter Context */
32042 -SK_IOC IoC) /* I/O Context */
32044 - int ReadComplete;
32047 - if (pAC->I2c.InitLevel != SK_INIT_IO) {
32048 - /* ReInit not needed in I2C module */
32049 - /* Init0 and Init2 not permitted */
32053 - pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
32054 - ReadComplete = SkI2cReadSensor(pAC, IoC, pSen);
32056 - if (ReadComplete) {
32057 - SK_ERR_LOG(pAC, SK_ERRCL_INIT, SKERR_I2C_E008, SKERR_I2C_E008MSG);
32060 - /* Now we are correctly initialized */
32061 - pAC->I2c.InitLevel = SK_INIT_RUN;
32068 - * Initialize I2C devices
32070 - * Get the first voltage value and discard it.
32071 - * Go into temperature read mode. A default pointer is not set.
32073 - * The things to be done depend on the init level in the parameter list:
32075 - * Initialize only the data structures. Do NOT access hardware.
32077 - * Initialize hardware through SK_IN / SK_OUT commands. Do NOT use interrupts.
32079 - * Everything is possible. Interrupts may be used from now on.
32086 -SK_AC *pAC, /* Adapter Context */
32087 -SK_IOC IoC, /* I/O Context needed in levels 1 and 2 */
32088 -int Level) /* Init Level */
32092 - case SK_INIT_DATA:
32093 - return(SkI2cInit0(pAC));
32095 - return(SkI2cInit1(pAC, IoC));
32096 - case SK_INIT_RUN:
32097 - return(SkI2cInit2(pAC, IoC));
32109 - * Interrupt service function for the I2C Interface
32111 - * Clears the Interrupt source
32113 - * Reads the register and check it for sending a trap.
32115 - * Starts the timer if necessary.
32118 -SK_AC *pAC, /* Adapter Context */
32119 -SK_IOC IoC) /* I/O Context */
32123 - /* Clear I2C IRQ */
32124 - SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
32127 - SkEventQueue(pAC, SKGE_I2C, SK_I2CEV_IRQ, Para);
32132 - * Check this sensors Value against the threshold and send events.
32134 -static void SkI2cCheckSensor(
32135 -SK_AC *pAC, /* Adapter Context */
32138 - SK_EVPARA ParaLocal;
32139 - SK_BOOL TooHigh; /* Is sensor too high? */
32140 - SK_BOOL TooLow; /* Is sensor too low? */
32141 - SK_U64 CurrTime; /* Current Time */
32142 - SK_BOOL DoTrapSend; /* We need to send a trap */
32143 - SK_BOOL DoErrLog; /* We need to log the error */
32144 - SK_BOOL IsError; /* We need to log the error */
32146 - /* Check Dummy Reads first */
32147 - if (pAC->I2c.DummyReads > 0) {
32148 - pAC->I2c.DummyReads--;
32152 - /* Get the current time */
32153 - CurrTime = SkOsGetTime(pAC);
32155 - /* Set para to the most useful setting: The current sensor. */
32156 - ParaLocal.Para64 = (SK_U64)pAC->I2c.CurrSens;
32158 - /* Check the Value against the thresholds. First: Error Thresholds */
32159 - TooHigh = (pSen->SenValue > pSen->SenThreErrHigh);
32160 - TooLow = (pSen->SenValue < pSen->SenThreErrLow);
32162 - IsError = SK_FALSE;
32163 - if (TooHigh || TooLow) {
32164 - /* Error condition is satisfied */
32165 - DoTrapSend = SK_TRUE;
32166 - DoErrLog = SK_TRUE;
32168 - /* Now error condition is satisfied */
32169 - IsError = SK_TRUE;
32171 - if (pSen->SenErrFlag == SK_SEN_ERR_ERR) {
32172 - /* This state is the former one */
32174 - /* So check first whether we have to send a trap */
32175 - if (pSen->SenLastErrTrapTS + SK_SEN_ERR_TR_HOLD >
32178 - * Do NOT send the Trap. The hold back time
32179 - * has to run out first.
32181 - DoTrapSend = SK_FALSE;
32184 - /* Check now whether we have to log an Error */
32185 - if (pSen->SenLastErrLogTS + SK_SEN_ERR_LOG_HOLD >
32188 - * Do NOT log the error. The hold back time
32189 - * has to run out first.
32191 - DoErrLog = SK_FALSE;
32195 - /* We came from a different state -> Set Begin Time Stamp */
32196 - pSen->SenBegErrTS = CurrTime;
32197 - pSen->SenErrFlag = SK_SEN_ERR_ERR;
32200 - if (DoTrapSend) {
32201 - /* Set current Time */
32202 - pSen->SenLastErrTrapTS = CurrTime;
32203 - pSen->SenErrCts++;
32205 - /* Queue PNMI Event */
32206 - SkEventQueue(pAC, SKGE_PNMI, (TooHigh ?
32207 - SK_PNMI_EVT_SEN_ERR_UPP :
32208 - SK_PNMI_EVT_SEN_ERR_LOW),
32213 - /* Set current Time */
32214 - pSen->SenLastErrLogTS = CurrTime;
32216 - if (pSen->SenType == SK_SEN_TEMP) {
32217 - SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E011, SKERR_I2C_E011MSG);
32219 - else if (pSen->SenType == SK_SEN_VOLT) {
32220 - SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E012, SKERR_I2C_E012MSG);
32223 - SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E015, SKERR_I2C_E015MSG);
32228 - /* Check the Value against the thresholds */
32229 - /* 2nd: Warning thresholds */
32230 - TooHigh = (pSen->SenValue > pSen->SenThreWarnHigh);
32231 - TooLow = (pSen->SenValue < pSen->SenThreWarnLow);
32233 - if (!IsError && (TooHigh || TooLow)) {
32234 - /* Error condition is satisfied */
32235 - DoTrapSend = SK_TRUE;
32236 - DoErrLog = SK_TRUE;
32238 - if (pSen->SenErrFlag == SK_SEN_ERR_WARN) {
32239 - /* This state is the former one */
32241 - /* So check first whether we have to send a trap */
32242 - if (pSen->SenLastWarnTrapTS + SK_SEN_WARN_TR_HOLD > CurrTime) {
32244 - * Do NOT send the Trap. The hold back time
32245 - * has to run out first.
32247 - DoTrapSend = SK_FALSE;
32250 - /* Check now whether we have to log an Error */
32251 - if (pSen->SenLastWarnLogTS + SK_SEN_WARN_LOG_HOLD > CurrTime) {
32253 - * Do NOT log the error. The hold back time
32254 - * has to run out first.
32256 - DoErrLog = SK_FALSE;
32260 - /* We came from a different state -> Set Begin Time Stamp */
32261 - pSen->SenBegWarnTS = CurrTime;
32262 - pSen->SenErrFlag = SK_SEN_ERR_WARN;
32265 - if (DoTrapSend) {
32266 - /* Set current Time */
32267 - pSen->SenLastWarnTrapTS = CurrTime;
32268 - pSen->SenWarnCts++;
32270 - /* Queue PNMI Event */
32271 - SkEventQueue(pAC, SKGE_PNMI, (TooHigh ?
32272 - SK_PNMI_EVT_SEN_WAR_UPP :
32273 - SK_PNMI_EVT_SEN_WAR_LOW),
32278 - /* Set current Time */
32279 - pSen->SenLastWarnLogTS = CurrTime;
32281 - if (pSen->SenType == SK_SEN_TEMP) {
32282 - SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E009, SKERR_I2C_E009MSG);
32284 - else if (pSen->SenType == SK_SEN_VOLT) {
32285 - SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E010, SKERR_I2C_E010MSG);
32288 - SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E014, SKERR_I2C_E014MSG);
32293 - /* Check for NO error at all */
32294 - if (!IsError && !TooHigh && !TooLow) {
32295 - /* Set o.k. Status if no error and no warning condition */
32296 - pSen->SenErrFlag = SK_SEN_ERR_OK;
32299 - /* End of check against the thresholds */
32301 - /* Bug fix AF: 16.Aug.2001: Correct the init base
32302 - * of LM80 sensor.
32304 - if (pSen->SenInit == SK_SEN_DYN_INIT_PCI_IO) {
32306 - pSen->SenInit = SK_SEN_DYN_INIT_NONE;
32308 - if (pSen->SenValue > SK_SEN_PCI_IO_RANGE_LIMITER) {
32309 - /* 5V PCI-IO Voltage */
32310 - pSen->SenThreWarnLow = SK_SEN_PCI_IO_5V_LOW_WARN;
32311 - pSen->SenThreErrLow = SK_SEN_PCI_IO_5V_LOW_ERR;
32314 - /* 3.3V PCI-IO Voltage */
32315 - pSen->SenThreWarnHigh = SK_SEN_PCI_IO_3V3_HIGH_WARN;
32316 - pSen->SenThreErrHigh = SK_SEN_PCI_IO_3V3_HIGH_ERR;
32321 - /* Dynamic thresholds also for VAUX of LM80 sensor */
32322 - if (pSen->SenInit == SK_SEN_DYN_INIT_VAUX) {
32324 - pSen->SenInit = SK_SEN_DYN_INIT_NONE;
32326 - /* 3.3V VAUX Voltage */
32327 - if (pSen->SenValue > SK_SEN_VAUX_RANGE_LIMITER) {
32328 - pSen->SenThreWarnLow = SK_SEN_VAUX_3V3_LOW_WARN;
32329 - pSen->SenThreErrLow = SK_SEN_VAUX_3V3_LOW_ERR;
32331 - /* 0V VAUX Voltage */
32333 - pSen->SenThreWarnHigh = SK_SEN_VAUX_0V_WARN_ERR;
32334 - pSen->SenThreErrHigh = SK_SEN_VAUX_0V_WARN_ERR;
32339 - * Check initialization state:
32340 - * The VIO Thresholds need adaption
32342 - if (!pSen->SenInit && pSen->SenReg == LM80_VT1_IN &&
32343 - pSen->SenValue > SK_SEN_WARNLOW2C &&
32344 - pSen->SenValue < SK_SEN_WARNHIGH2) {
32345 - pSen->SenThreErrLow = SK_SEN_ERRLOW2C;
32346 - pSen->SenThreWarnLow = SK_SEN_WARNLOW2C;
32347 - pSen->SenInit = SK_TRUE;
32350 - if (!pSen->SenInit && pSen->SenReg == LM80_VT1_IN &&
32351 - pSen->SenValue > SK_SEN_WARNLOW2 &&
32352 - pSen->SenValue < SK_SEN_WARNHIGH2C) {
32353 - pSen->SenThreErrHigh = SK_SEN_ERRHIGH2C;
32354 - pSen->SenThreWarnHigh = SK_SEN_WARNHIGH2C;
32355 - pSen->SenInit = SK_TRUE;
32359 - if (pSen->SenInit != SK_SEN_DYN_INIT_NONE) {
32360 - SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E013, SKERR_I2C_E013MSG);
32362 -} /* SkI2cCheckSensor */
32366 - * The only Event to be served is the timeout event
32370 -SK_AC *pAC, /* Adapter Context */
32371 -SK_IOC IoC, /* I/O Context */
32372 -SK_U32 Event, /* Module specific Event */
32373 -SK_EVPARA Para) /* Event specific Parameter */
32375 - int ReadComplete;
32378 - SK_EVPARA ParaLocal;
32381 - /* New case: no sensors */
32382 - if (pAC->I2c.MaxSens == 0) {
32387 - case SK_I2CEV_IRQ:
32388 - pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
32389 - ReadComplete = SkI2cReadSensor(pAC, IoC, pSen);
32391 - if (ReadComplete) {
32392 - /* Check sensor against defined thresholds */
32393 - SkI2cCheckSensor(pAC, pSen);
32395 - /* Increment Current sensor and set appropriate Timeout */
32396 - pAC->I2c.CurrSens++;
32397 - if (pAC->I2c.CurrSens >= pAC->I2c.MaxSens) {
32398 - pAC->I2c.CurrSens = 0;
32399 - Time = SK_I2C_TIM_LONG;
32402 - Time = SK_I2C_TIM_SHORT;
32405 - /* Start Timer */
32406 - ParaLocal.Para64 = (SK_U64)0;
32408 - pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING;
32410 - SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time,
32411 - SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
32414 - /* Start Timer */
32415 - ParaLocal.Para64 = (SK_U64)0;
32417 - pAC->I2c.TimerMode = SK_TIMER_WATCH_SM;
32419 - SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, SK_I2C_TIM_WATCH,
32420 - SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
32423 - case SK_I2CEV_TIM:
32424 - if (pAC->I2c.TimerMode == SK_TIMER_NEW_GAUGING) {
32426 - ParaLocal.Para64 = (SK_U64)0;
32427 - SkTimerStop(pAC, IoC, &pAC->I2c.SenTimer);
32429 - pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
32430 - ReadComplete = SkI2cReadSensor(pAC, IoC, pSen);
32432 - if (ReadComplete) {
32433 - /* Check sensor against defined thresholds */
32434 - SkI2cCheckSensor(pAC, pSen);
32436 - /* Increment Current sensor and set appropriate Timeout */
32437 - pAC->I2c.CurrSens++;
32438 - if (pAC->I2c.CurrSens == pAC->I2c.MaxSens) {
32439 - pAC->I2c.CurrSens = 0;
32440 - Time = SK_I2C_TIM_LONG;
32443 - Time = SK_I2C_TIM_SHORT;
32446 - /* Start Timer */
32447 - ParaLocal.Para64 = (SK_U64)0;
32449 - pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING;
32451 - SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time,
32452 - SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
32456 - pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
32457 - pSen->SenErrFlag = SK_SEN_ERR_FAULTY;
32458 - SK_I2C_STOP(IoC);
32460 - /* Increment Current sensor and set appropriate Timeout */
32461 - pAC->I2c.CurrSens++;
32462 - if (pAC->I2c.CurrSens == pAC->I2c.MaxSens) {
32463 - pAC->I2c.CurrSens = 0;
32464 - Time = SK_I2C_TIM_LONG;
32467 - Time = SK_I2C_TIM_SHORT;
32470 - /* Start Timer */
32471 - ParaLocal.Para64 = (SK_U64)0;
32473 - pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING;
32475 - SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time,
32476 - SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
32479 - case SK_I2CEV_CLEAR:
32480 - for (i = 0; i < SK_MAX_SENSORS; i++) {
32481 - pAC->I2c.SenTable[i].SenErrFlag = SK_SEN_ERR_OK;
32482 - pAC->I2c.SenTable[i].SenErrCts = 0;
32483 - pAC->I2c.SenTable[i].SenWarnCts = 0;
32484 - pAC->I2c.SenTable[i].SenBegErrTS = 0;
32485 - pAC->I2c.SenTable[i].SenBegWarnTS = 0;
32486 - pAC->I2c.SenTable[i].SenLastErrTrapTS = (SK_U64)0;
32487 - pAC->I2c.SenTable[i].SenLastErrLogTS = (SK_U64)0;
32488 - pAC->I2c.SenTable[i].SenLastWarnTrapTS = (SK_U64)0;
32489 - pAC->I2c.SenTable[i].SenLastWarnLogTS = (SK_U64)0;
32493 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E006, SKERR_I2C_E006MSG);
32499 -#endif /* !SK_DIAG */
32500 diff -ruN linux/drivers/net/sk98lin/sklm80.c linux-new/drivers/net/sk98lin/sklm80.c
32501 --- linux/drivers/net/sk98lin/sklm80.c 2006-09-20 05:42:06.000000000 +0200
32502 +++ linux-new/drivers/net/sk98lin/sklm80.c 2006-07-28 14:13:54.000000000 +0200
32506 * Project: Gigabit Ethernet Adapters, TWSI-Module
32507 - * Version: $Revision$
32509 + * Version: $Revision$
32511 * Purpose: Functions to access Voltage and Temperature Sensor (LM80)
32513 ******************************************************************************/
32515 /******************************************************************************
32518 * (C)Copyright 1998-2002 SysKonnect.
32519 * (C)Copyright 2002-2003 Marvell.
32522 * (at your option) any later version.
32524 * The information in this file is provided "AS IS" without warranty.
32527 ******************************************************************************/
32529 @@ -27,24 +29,96 @@
32531 #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
32532 static const char SysKonnectFileId[] =
32533 - "@(#) $Id$ (C) Marvell. ";
32534 + "@(#) $Id$ (C) Marvell. ";
32537 #include "h/skdrv1st.h" /* Driver Specific Definitions */
32538 #include "h/lm80.h"
32539 #include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */
32542 +#define BREAK_OR_WAIT(pAC,IoC,Event) SkI2cWait(pAC,IoC,Event)
32543 +#else /* nSK_DIAG */
32544 #define BREAK_OR_WAIT(pAC,IoC,Event) break
32545 +#endif /* nSK_DIAG */
32549 + * read the register 'Reg' from the device 'Dev'
32551 + * return read error -1
32552 + * success the read value
32555 +SK_IOC IoC, /* Adapter Context */
32556 +int Dev, /* I2C device address */
32557 +int Reg) /* register to read */
32562 + /* Signal device number */
32563 + if (SkI2cSndDev(IoC, Dev, I2C_WRITE)) {
32567 + if (SkI2cSndByte(IoC, Reg)) {
32571 + /* repeat start */
32572 + if (SkI2cSndDev(IoC, Dev, I2C_READ)) {
32577 + case LM80_TEMP_IN:
32578 + Val = (int)SkI2cRcvByte(IoC, 1);
32580 + /* First: correct the value: it might be negative */
32581 + if ((Val & 0x80) != 0) {
32582 + /* Value is negative */
32585 + Val = Val * SK_LM80_TEMP_LSB;
32588 + TempExt = (int)SkLm80RcvReg(IoC, LM80_ADDR, LM80_TEMP_CTRL);
32591 + Val += ((TempExt >> 7) * SK_LM80_TEMPEXT_LSB);
32594 + Val -= ((TempExt >> 7) * SK_LM80_TEMPEXT_LSB);
32598 + case LM80_VT0_IN:
32599 + case LM80_VT1_IN:
32600 + case LM80_VT2_IN:
32601 + case LM80_VT3_IN:
32602 + Val = (int)SkI2cRcvByte(IoC, 1) * SK_LM80_VT_LSB;
32606 + Val = (int)SkI2cRcvByte(IoC, 1);
32613 +#endif /* SK_DIAG */
32616 * read a sensors value (LM80 specific)
32618 - * This function reads a sensors value from the I2C sensor chip LM80.
32619 + * This function reads a sensors value from the TWSI sensor chip LM80.
32620 * The sensor is defined by its index into the sensors database in the struct
32623 * Returns 1 if the read is completed
32624 - * 0 if the read must be continued (I2C Bus still allocated)
32625 + * 0 if the read must be continued (TWSI Bus still allocated)
32627 int SkLm80ReadSensor(
32628 SK_AC *pAC, /* Adapter Context */
32629 diff -ruN linux/drivers/net/sk98lin/skproc.c linux-new/drivers/net/sk98lin/skproc.c
32630 --- linux/drivers/net/sk98lin/skproc.c 1970-01-01 01:00:00.000000000 +0100
32631 +++ linux-new/drivers/net/sk98lin/skproc.c 2006-07-28 14:13:56.000000000 +0200
32633 +/******************************************************************************
32636 + * Project: GEnesis, PCI Gigabit Ethernet Adapter
32637 + * Version: $Revision$
32639 + * Purpose: Functions to display statictic data
32641 + ******************************************************************************/
32643 +/******************************************************************************
32645 + * (C)Copyright 1998-2002 SysKonnect GmbH.
32646 + * (C)Copyright 2002-2005 Marvell.
32648 + * Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet
32649 + * Server Adapters.
32651 + * Author: Ralph Roesler (rroesler@syskonnect.de)
32652 + * Mirko Lindner (mlindner@syskonnect.de)
32654 + * Address all question to: linux@syskonnect.de
32656 + * This program is free software; you can redistribute it and/or modify
32657 + * it under the terms of the GNU General Public License as published by
32658 + * the Free Software Foundation; either version 2 of the License, or
32659 + * (at your option) any later version.
32661 + * The information in this file is provided "AS IS" without warranty.
32663 + *****************************************************************************/
32665 +#include <linux/proc_fs.h>
32666 +#include <linux/seq_file.h>
32668 +#include "h/skdrv1st.h"
32669 +#include "h/skdrv2nd.h"
32670 +#include "h/skversion.h"
32672 +extern struct SK_NET_DEVICE *SkGeRootDev;
32674 +/******************************************************************************
32676 + * Local Function Prototypes and Local Variables
32678 + *****************************************************************************/
32680 +static int sk_proc_print(void *writePtr, char *format, ...);
32681 +static void sk_gen_browse(void *buffer);
32684 +static int sk_seq_show(struct seq_file *seq, void *v);
32685 +static int sk_proc_open(struct inode *inode, struct file *file);
32686 +struct file_operations sk_proc_fops = {
32687 + .owner = THIS_MODULE,
32688 + .open = sk_proc_open,
32689 + .read = seq_read,
32690 + .llseek = seq_lseek,
32691 + .release = single_release,
32693 +struct net_device *currDev = NULL;
32695 +/*****************************************************************************
32697 + * sk_gen_browse -generic print "summaries" entry
32700 + * This function fills the proc entry with statistic data about
32701 + * the ethernet device.
32706 +static void sk_gen_browse(
32707 +void *buffer) /* buffer where the statistics will be stored in */
32709 + struct SK_NET_DEVICE *SkgeProcDev = SkGeRootDev;
32710 + struct SK_NET_DEVICE *next;
32711 + SK_BOOL DisableStatistic = 0;
32712 + SK_PNMI_STRUCT_DATA *pPnmiStruct;
32713 + SK_PNMI_STAT *pPnmiStat;
32714 + unsigned long Flags;
32715 + unsigned int Size;
32718 + char sens_msg[50];
32720 + int MaxSecurityCount = 0;
32724 + while (SkgeProcDev) {
32725 + MaxSecurityCount++;
32726 + if (MaxSecurityCount > 100) {
32727 + printk("Max limit for sk_proc_read security counter!\n");
32730 + pNet = (DEV_NET*) SkgeProcDev->priv;
32732 + next = pAC->Next;
32733 + pPnmiStruct = &pAC->PnmiStruct;
32734 + /* NetIndex in GetStruct is now required, zero is only dummy */
32736 + for (t=pAC->GIni.GIMacsFound; t > 0; t--) {
32737 + if ((pAC->GIni.GIMacsFound == 2) && pAC->RlmtNets == 1)
32740 + spin_lock_irqsave(&pAC->SlowPathLock, Flags);
32741 + Size = SK_PNMI_STRUCT_SIZE;
32742 + DisableStatistic = 0;
32743 + if (pAC->BoardLevel == SK_INIT_DATA) {
32744 + SK_MEMCPY(&(pAC->PnmiStruct), &(pAC->PnmiBackup), sizeof(SK_PNMI_STRUCT_DATA));
32745 + if (pAC->DiagModeActive == DIAG_NOTACTIVE) {
32746 + pAC->Pnmi.DiagAttached = SK_DIAG_IDLE;
32749 + SkPnmiGetStruct(pAC, pAC->IoBase, pPnmiStruct, &Size, t-1);
32751 + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
32752 + if (strcmp(pAC->dev[t-1]->name, currDev->name) == 0) {
32753 + if (!pAC->GIni.GIYukon32Bit)
32758 + pPnmiStat = &pPnmiStruct->Stat[0];
32759 + len = sk_proc_print(buffer,
32760 + "\nDetailed statistic for device %s\n",
32761 + pAC->dev[t-1]->name);
32762 + len += sk_proc_print(buffer,
32763 + "=======================================\n");
32765 + /* Board statistics */
32766 + len += sk_proc_print(buffer,
32767 + "\nBoard statistics\n\n");
32768 + len += sk_proc_print(buffer,
32769 + "Card name %s\n",
32771 + len += sk_proc_print(buffer,
32772 + "Vendor/Device ID %x/%x\n",
32773 + pAC->PciDev->vendor,
32774 + pAC->PciDev->device);
32775 + len += sk_proc_print(buffer,
32776 + "Card type (Bit) %d\n",
32779 + len += sk_proc_print(buffer,
32780 + "Active Port %c\n",
32781 + 'A' + pAC->Rlmt.Net[t-1].Port[pAC->Rlmt.
32782 + Net[t-1].PrefPort]->PortNumber);
32783 + len += sk_proc_print(buffer,
32784 + "Preferred Port %c\n",
32785 + 'A' + pAC->Rlmt.Net[t-1].Port[pAC->Rlmt.
32786 + Net[t-1].PrefPort]->PortNumber);
32788 + if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_STATIC) {
32789 + len += sk_proc_print(buffer,
32790 + "Interrupt Moderation static (%d ints/sec)\n",
32791 + pAC->DynIrqModInfo.MaxModIntsPerSec);
32792 + } else if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
32793 + len += sk_proc_print(buffer,
32794 + "Interrupt Moderation dynamic (%d ints/sec)\n",
32795 + pAC->DynIrqModInfo.MaxModIntsPerSec);
32797 + len += sk_proc_print(buffer,
32798 + "Interrupt Moderation disabled\n");
32801 + if (pAC->GIni.GIPciBus == SK_PEX_BUS) {
32802 + len += sk_proc_print(buffer,
32803 + "Bus type PCI-Express\n");
32804 + len += sk_proc_print(buffer,
32805 + "Bus width (Lanes) %d\n",
32806 + pAC->GIni.GIPexWidth);
32808 + if (pAC->GIni.GIPciBus == SK_PCIX_BUS) {
32809 + len += sk_proc_print(buffer,
32810 + "Bus type PCI-X\n");
32811 + if (pAC->GIni.GIPciMode == PCI_OS_SPD_X133) {
32812 + len += sk_proc_print(buffer,
32813 + "Bus speed (MHz) 133\n");
32814 + } else if (pAC->GIni.GIPciMode == PCI_OS_SPD_X100) {
32815 + len += sk_proc_print(buffer,
32816 + "Bus speed (MHz) 100\n");
32817 + } else if (pAC->GIni.GIPciMode == PCI_OS_SPD_X66) {
32818 + len += sk_proc_print(buffer,
32819 + "Bus speed (MHz) 66\n");
32821 + len += sk_proc_print(buffer,
32822 + "Bus speed (MHz) 33\n");
32825 + len += sk_proc_print(buffer,
32826 + "Bus type PCI\n");
32827 + len += sk_proc_print(buffer,
32828 + "Bus speed (MHz) %d\n",
32829 + pPnmiStruct->BusSpeed);
32831 + len += sk_proc_print(buffer,
32832 + "Bus width (Bit) %d\n",
32833 + pPnmiStruct->BusWidth);
32836 + len += sk_proc_print(buffer,
32837 + "Driver version %s (%s)\n",
32838 + VER_STRING, PATCHLEVEL);
32839 + len += sk_proc_print(buffer,
32840 + "Driver release date %s\n",
32841 + pAC->Pnmi.pDriverReleaseDate);
32842 + len += sk_proc_print(buffer,
32843 + "Hardware revision v%d.%d\n",
32844 + (pAC->GIni.GIPciHwRev >> 4) & 0x0F,
32845 + pAC->GIni.GIPciHwRev & 0x0F);
32847 + if (!netif_running(pAC->dev[t-1])) {
32848 + len += sk_proc_print(buffer,
32849 + "\n Device %s is down.\n"
32850 + " Therefore no statistics are available.\n"
32851 + " After bringing the device up (ifconfig)"
32852 + " statistics will\n"
32853 + " be displayed.\n",
32854 + pAC->dev[t-1]->name);
32855 + DisableStatistic = 1;
32858 + /* Display only if statistic info available */
32859 + /* Print sensor informations */
32860 + if (!DisableStatistic) {
32861 + for (i=0; i < pAC->I2c.MaxSens; i ++) {
32863 + switch (pAC->I2c.SenTable[i].SenType) {
32865 + strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc);
32866 + strcat(sens_msg, " (C)");
32867 + len += sk_proc_print(buffer,
32868 + "%-25s %d.%02d\n",
32870 + pAC->I2c.SenTable[i].SenValue / 10,
32871 + pAC->I2c.SenTable[i].SenValue %
32874 + strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc);
32875 + strcat(sens_msg, " (F)");
32876 + len += sk_proc_print(buffer,
32877 + "%-25s %d.%02d\n",
32879 + ((((pAC->I2c.SenTable[i].SenValue)
32880 + *10)*9)/5 + 3200)/100,
32881 + ((((pAC->I2c.SenTable[i].SenValue)
32882 + *10)*9)/5 + 3200) % 10);
32885 + strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc);
32886 + strcat(sens_msg, " (V)");
32887 + len += sk_proc_print(buffer,
32888 + "%-25s %d.%03d\n",
32890 + pAC->I2c.SenTable[i].SenValue / 1000,
32891 + pAC->I2c.SenTable[i].SenValue % 1000);
32894 + strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc);
32895 + strcat(sens_msg, " (rpm)");
32896 + len += sk_proc_print(buffer,
32899 + pAC->I2c.SenTable[i].SenValue);
32906 + /*Receive statistics */
32907 + len += sk_proc_print(buffer,
32908 + "\nReceive statistics\n\n");
32910 + len += sk_proc_print(buffer,
32911 + "Received bytes %Lu\n",
32912 + (unsigned long long) pPnmiStat->StatRxOctetsOkCts);
32913 + len += sk_proc_print(buffer,
32914 + "Received packets %Lu\n",
32915 + (unsigned long long) pPnmiStat->StatRxOkCts);
32917 + if (pAC->GIni.GP[0].PhyType == SK_PHY_XMAC &&
32918 + pAC->HWRevision < 12) {
32919 + pPnmiStruct->InErrorsCts = pPnmiStruct->InErrorsCts -
32920 + pPnmiStat->StatRxShortsCts;
32921 + pPnmiStat->StatRxShortsCts = 0;
32924 + if (pAC->dev[t-1]->mtu > 1500)
32925 + pPnmiStruct->InErrorsCts = pPnmiStruct->InErrorsCts -
32926 + pPnmiStat->StatRxTooLongCts;
32928 + len += sk_proc_print(buffer,
32929 + "Receive errors %Lu\n",
32930 + (unsigned long long) pPnmiStruct->InErrorsCts);
32931 + len += sk_proc_print(buffer,
32932 + "Receive dropped %Lu\n",
32933 + (unsigned long long) pPnmiStruct->RxNoBufCts);
32934 + len += sk_proc_print(buffer,
32935 + "Received multicast %Lu\n",
32936 + (unsigned long long) pPnmiStat->StatRxMulticastOkCts);
32937 +#ifdef ADVANCED_STATISTIC_OUTPUT
32938 + len += sk_proc_print(buffer,
32939 + "Receive error types\n");
32940 + len += sk_proc_print(buffer,
32942 + (unsigned long long) pPnmiStat->StatRxRuntCts);
32943 + len += sk_proc_print(buffer,
32944 + " buffer overflow %Lu\n",
32945 + (unsigned long long) pPnmiStat->StatRxFifoOverflowCts);
32946 + len += sk_proc_print(buffer,
32947 + " bad crc %Lu\n",
32948 + (unsigned long long) pPnmiStat->StatRxFcsCts);
32949 + len += sk_proc_print(buffer,
32950 + " framing %Lu\n",
32951 + (unsigned long long) pPnmiStat->StatRxFramingCts);
32952 + len += sk_proc_print(buffer,
32953 + " missed frames %Lu\n",
32954 + (unsigned long long) pPnmiStat->StatRxMissedCts);
32956 + if (pAC->dev[t-1]->mtu > 1500)
32957 + pPnmiStat->StatRxTooLongCts = 0;
32959 + len += sk_proc_print(buffer,
32960 + " too long %Lu\n",
32961 + (unsigned long long) pPnmiStat->StatRxTooLongCts);
32962 + len += sk_proc_print(buffer,
32963 + " carrier extension %Lu\n",
32964 + (unsigned long long) pPnmiStat->StatRxCextCts);
32965 + len += sk_proc_print(buffer,
32966 + " too short %Lu\n",
32967 + (unsigned long long) pPnmiStat->StatRxShortsCts);
32968 + len += sk_proc_print(buffer,
32970 + (unsigned long long) pPnmiStat->StatRxSymbolCts);
32971 + len += sk_proc_print(buffer,
32972 + " LLC MAC size %Lu\n",
32973 + (unsigned long long) pPnmiStat->StatRxIRLengthCts);
32974 + len += sk_proc_print(buffer,
32975 + " carrier event %Lu\n",
32976 + (unsigned long long) pPnmiStat->StatRxCarrierCts);
32977 + len += sk_proc_print(buffer,
32979 + (unsigned long long) pPnmiStat->StatRxJabberCts);
32982 + /*Transmit statistics */
32983 + len += sk_proc_print(buffer,
32984 + "\nTransmit statistics\n\n");
32986 + len += sk_proc_print(buffer,
32987 + "Transmitted bytes %Lu\n",
32988 + (unsigned long long) pPnmiStat->StatTxOctetsOkCts);
32989 + len += sk_proc_print(buffer,
32990 + "Transmitted packets %Lu\n",
32991 + (unsigned long long) pPnmiStat->StatTxOkCts);
32992 + len += sk_proc_print(buffer,
32993 + "Transmit errors %Lu\n",
32994 + (unsigned long long) pPnmiStat->StatTxSingleCollisionCts);
32995 + len += sk_proc_print(buffer,
32996 + "Transmit dropped %Lu\n",
32997 + (unsigned long long) pPnmiStruct->TxNoBufCts);
32998 + len += sk_proc_print(buffer,
32999 + "Transmit collisions %Lu\n",
33000 + (unsigned long long) pPnmiStat->StatTxSingleCollisionCts);
33001 +#ifdef ADVANCED_STATISTIC_OUTPUT
33002 + len += sk_proc_print(buffer,
33003 + "Transmit error types\n");
33004 + len += sk_proc_print(buffer,
33005 + " excessive collision %ld\n",
33006 + pAC->stats.tx_aborted_errors);
33007 + len += sk_proc_print(buffer,
33008 + " carrier %Lu\n",
33009 + (unsigned long long) pPnmiStat->StatTxCarrierCts);
33010 + len += sk_proc_print(buffer,
33011 + " fifo underrun %Lu\n",
33012 + (unsigned long long) pPnmiStat->StatTxFifoUnderrunCts);
33013 + len += sk_proc_print(buffer,
33014 + " heartbeat %Lu\n",
33015 + (unsigned long long) pPnmiStat->StatTxCarrierCts);
33016 + len += sk_proc_print(buffer,
33018 + pAC->stats.tx_window_errors);
33020 + } /* if (!DisableStatistic) */
33022 + } /* if (strcmp(pACname, currDeviceName) == 0) */
33024 + SkgeProcDev = next;
33028 +/*****************************************************************************
33030 + * sk_proc_print - generic line print
33033 + * This function fills the proc entry with statistic data about the
33034 + * ethernet device.
33037 + * the number of bytes written
33040 +static int sk_proc_print(
33041 +void *writePtr, /* the buffer pointer */
33042 +char *format, /* the format of the string */
33043 +...) /* variable list of arguments */
33045 +#define MAX_LEN_SINGLE_LINE 256
33046 + char str[MAX_LEN_SINGLE_LINE];
33050 + struct seq_file *seq = (struct seq_file *) writePtr;
33052 + SK_MEMSET(str, 0, MAX_LEN_SINGLE_LINE);
33054 + va_start(a_start, format);
33055 + vsprintf(str, format, a_start);
33058 + lenght = strlen(str);
33060 + seq_printf(seq, str);
33064 +/*****************************************************************************
33066 + * sk_seq_show - show proc information of a particular adapter
33069 + * This function fills the proc entry with statistic data about the
33070 + * ethernet device. It invokes the generic sk_gen_browse() to print
33071 + * out all items one per one.
33074 + * the number of bytes written
33077 +static int sk_seq_show(
33078 +struct seq_file *seq, /* the sequence pointer */
33079 +void *v) /* additional pointer */
33081 + void *castedBuffer = (void *) seq;
33082 + currDev = seq->private;
33083 + sk_gen_browse(castedBuffer);
33087 +/*****************************************************************************
33089 + * sk_proc_open - register the show function when proc is open'ed
33092 + * This function is called whenever a sk98lin proc file is queried.
33095 + * the return value of single_open()
33098 +static int sk_proc_open(
33099 +struct inode *inode, /* the inode of the file */
33100 +struct file *file) /* the file pointer itself */
33102 + return single_open(file, sk_seq_show, PDE(inode)->data);
33105 +/*******************************************************************************
33109 + ******************************************************************************/
33110 diff -ruN linux/drivers/net/sk98lin/skqueue.c linux-new/drivers/net/sk98lin/skqueue.c
33111 --- linux/drivers/net/sk98lin/skqueue.c 2006-09-20 05:42:06.000000000 +0200
33112 +++ linux-new/drivers/net/sk98lin/skqueue.c 2006-07-28 14:13:54.000000000 +0200
33116 * Project: Gigabit Ethernet Adapters, Event Scheduler Module
33117 - * Version: $Revision$
33119 + * Version: $Revision$
33121 * Purpose: Management of an event queue.
33123 ******************************************************************************/
33125 /******************************************************************************
33128 * (C)Copyright 1998-2002 SysKonnect GmbH.
33129 * (C)Copyright 2002-2003 Marvell.
33132 * (at your option) any later version.
33134 * The information in this file is provided "AS IS" without warranty.
33137 ******************************************************************************/
33141 #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
33142 static const char SysKonnectFileId[] =
33143 - "@(#) $Id$ (C) Marvell.";
33144 + "@(#) $Id$ (C) Marvell.";
33147 #include "h/skdrv1st.h" /* Driver Specific Definitions */
33148 @@ -48,10 +50,16 @@
33150 #define PRINTF(a,b,c)
33153 - * init event queue management
33154 +/******************************************************************************
33156 + * SkEventInit() - init event queue management
33158 - * Must be called during init level 0.
33160 + * This function initializes event queue management.
33161 + * It must be called during init level 0.
33167 SK_AC *pAC, /* Adapter context */
33173 - * add event to queue
33174 +/******************************************************************************
33176 + * SkEventQueue() - add event to queue
33179 + * This function adds an event to the event queue.
33180 + * At least Init Level 1 is required to queue events,
33181 + * but will be scheduled add Init Level 2.
33187 SK_AC *pAC, /* Adapters context */
33188 @@ -76,26 +93,45 @@
33189 SK_U32 Event, /* Event to be queued */
33190 SK_EVPARA Para) /* Event parameter */
33192 - pAC->Event.EvPut->Class = Class;
33193 - pAC->Event.EvPut->Event = Event;
33194 - pAC->Event.EvPut->Para = Para;
33196 + if (pAC->GIni.GILevel == SK_INIT_DATA) {
33197 + SK_ERR_LOG(pAC, SK_ERRCL_NORES, SKERR_Q_E003, SKERR_Q_E003MSG);
33200 + pAC->Event.EvPut->Class = Class;
33201 + pAC->Event.EvPut->Event = Event;
33202 + pAC->Event.EvPut->Para = Para;
33204 - if (++pAC->Event.EvPut == &pAC->Event.EvQueue[SK_MAX_EVENT])
33205 - pAC->Event.EvPut = pAC->Event.EvQueue;
33206 + if (++pAC->Event.EvPut == &pAC->Event.EvQueue[SK_MAX_EVENT])
33207 + pAC->Event.EvPut = pAC->Event.EvQueue;
33209 - if (pAC->Event.EvPut == pAC->Event.EvGet) {
33210 - SK_ERR_LOG(pAC, SK_ERRCL_NORES, SKERR_Q_E001, SKERR_Q_E001MSG);
33211 + if (pAC->Event.EvPut == pAC->Event.EvGet) {
33212 + SK_ERR_LOG(pAC, SK_ERRCL_NORES, SKERR_Q_E001, SKERR_Q_E001MSG);
33218 - * event dispatcher
33219 - * while event queue is not empty
33220 - * get event from queue
33221 - * send command to state machine
33223 - * return error reported by individual Event function
33224 - * 0 if no error occured.
33225 +/******************************************************************************
33227 + * SkEventDispatcher() - Event Dispatcher
33230 + * The event dispatcher performs the following operations:
33231 + * o while event queue is not empty
33232 + * - get event from queue
33233 + * - send event to state machine
33237 + * The event functions MUST report an error if performing a reinitialization
33238 + * of the event queue, e.g. performing level Init 0..2 while in dispatcher
33240 + * ANY OTHER return value delays scheduling the other events in the
33241 + * queue. In this case the event blocks the queue until
33242 + * the error condition is cleared!
33245 + * The return value error reported by individual event function
33247 int SkEventDispatcher(
33248 SK_AC *pAC, /* Adapters Context */
33249 @@ -105,6 +141,10 @@
33253 + if (pAC->GIni.GILevel != SK_INIT_RUN) {
33254 + SK_ERR_LOG(pAC, SK_ERRCL_NORES, SKERR_Q_E005, SKERR_Q_E005MSG);
33257 pEv = pAC->Event.EvGet;
33259 PRINTF("dispatch get %x put %x\n", pEv, pAC->Event.ev_put);
33260 @@ -138,7 +178,7 @@
33261 Rtv = SkSwtEvent(pAC, Ioc, pEv->Event, pEv->Para);
33263 #endif /* !SK_USE_SW_TIMER */
33264 -#ifdef SK_USE_LAC_EV
33265 +#if defined(SK_USE_LAC_EV) || defined(SK_LBFO)
33267 Rtv = SkLacpEvent(pAC, Ioc, pEv->Event, pEv->Para);
33269 @@ -152,6 +192,11 @@
33270 Rtv = SkFdEvent(pAC, Ioc, pEv->Event, pEv->Para);
33272 #endif /* SK_USE_LAC_EV */
33275 + Rtv = SkAsfEvent(pAC,Ioc,pEv->Event,pEv->Para);
33280 Rtv = SkCsEvent(pAC, Ioc, pEv->Event, pEv->Para);
33281 @@ -163,6 +208,20 @@
33286 + * Special Case: See CAUTION statement above.
33287 + * We assume the event queue is reset.
33289 + if (pAC->Event.EvGet != pAC->Event.EvQueue &&
33290 + pAC->Event.EvGet != pEv) {
33292 + * Create an error log entry if the
33293 + * event queue isn't reset.
33294 + * In this case it may be blocked.
33296 + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_Q_E004, SKERR_Q_E004MSG);
33302 diff -ruN linux/drivers/net/sk98lin/skrlmt.c linux-new/drivers/net/sk98lin/skrlmt.c
33303 --- linux/drivers/net/sk98lin/skrlmt.c 2006-09-20 05:42:06.000000000 +0200
33304 +++ linux-new/drivers/net/sk98lin/skrlmt.c 2006-07-28 14:13:54.000000000 +0200
33308 * Project: GEnesis, PCI Gigabit Ethernet Adapter
33309 - * Version: $Revision$
33311 + * Version: $Revision$
33313 * Purpose: Manage links on SK-NET Adapters, esp. redundant ones.
33315 ******************************************************************************/
33317 /******************************************************************************
33320 * (C)Copyright 1998-2002 SysKonnect GmbH.
33321 * (C)Copyright 2002-2003 Marvell.
33324 * (at your option) any later version.
33326 * The information in this file is provided "AS IS" without warranty.
33329 ******************************************************************************/
33334 static const char SysKonnectFileId[] =
33335 - "@(#) $Id$ (C) Marvell.";
33336 + "@(#) $Id$ (C) Marvell.";
33337 #endif /* !defined(lint) */
33340 @@ -282,6 +284,7 @@
33342 SK_MAC_ADDR SkRlmtMcAddr = {{0x01, 0x00, 0x5A, 0x52, 0x4C, 0x4D}};
33343 SK_MAC_ADDR BridgeMcAddr = {{0x01, 0x80, 0xC2, 0x00, 0x00, 0x00}};
33344 +SK_MAC_ADDR BcAddr = {{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}};
33346 /* local variables ************************************************************/
33348 @@ -349,7 +352,7 @@
33349 SK_BOOL PhysicalAMacAddressSet;
33351 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_INIT,
33352 - ("RLMT Init level %d.\n", Level))
33353 + ("RLMT Init level %d.\n", Level));
33356 case SK_INIT_DATA: /* Initialize data structures. */
33357 @@ -389,7 +392,7 @@
33359 case SK_INIT_IO: /* GIMacsFound first available here. */
33360 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_INIT,
33361 - ("RLMT: %d MACs were detected.\n", pAC->GIni.GIMacsFound))
33362 + ("RLMT: %d MACs were detected.\n", pAC->GIni.GIMacsFound));
33364 pAC->Rlmt.Net[0].NumPorts = pAC->GIni.GIMacsFound;
33366 @@ -511,7 +514,7 @@
33369 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33370 - ("SkRlmtBuildCheckChain.\n"))
33371 + ("SkRlmtBuildCheckChain.\n"));
33375 @@ -557,7 +560,7 @@
33376 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33377 ("Port %d checks %d other ports: %2X.\n", i,
33378 pAC->Rlmt.Net[NetIdx].Port[i]->PortsChecked,
33379 - pAC->Rlmt.Net[NetIdx].Port[i]->PortCheck[0].CheckAddr.a[5]))
33380 + pAC->Rlmt.Net[NetIdx].Port[i]->PortCheck[0].CheckAddr.a[5]));
33384 @@ -603,7 +606,7 @@
33385 if ((CheckSrc == 0) || (CheckDest == 0)) {
33386 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_ERR,
33387 ("SkRlmtBuildPacket: Invalid %s%saddr.\n",
33388 - (CheckSrc == 0 ? "Src" : ""), (CheckDest == 0 ? "Dest" : "")))
33389 + (CheckSrc == 0 ? "Src" : ""), (CheckDest == 0 ? "Dest" : "")));
33393 @@ -795,7 +798,7 @@
33395 SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para);
33396 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_TX,
33397 - ("SkRlmtSend: BPDU Packet on Port %u.\n", PortNumber))
33398 + ("SkRlmtSend: BPDU Packet on Port %u.\n", PortNumber));
33402 @@ -834,7 +837,7 @@
33405 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33406 - ("SkRlmtPacketReceive: Received on PortDown.\n"))
33407 + ("SkRlmtPacketReceive: Received on PortDown.\n"));
33409 pRPort->PortState = SK_RLMT_PS_GOING_UP;
33410 pRPort->GuTimeStamp = SkOsGetTime(pAC);
33411 @@ -848,7 +851,7 @@
33412 } /* PortDown && !SuspectTx */
33413 else if (pRPort->CheckingState & SK_RLMT_PCS_RX) {
33414 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33415 - ("SkRlmtPacketReceive: Stop bringing port down.\n"))
33416 + ("SkRlmtPacketReceive: Stop bringing port down.\n"));
33417 SkTimerStop(pAC, IoC, &pRPort->DownRxTimer);
33418 pRPort->CheckingState &= ~SK_RLMT_PCS_RX;
33419 /* pAC->Rlmt.CheckSwitch = SK_TRUE; */
33420 @@ -895,7 +898,7 @@
33421 pRPort = &pAC->Rlmt.Port[PortNumber];
33423 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33424 - ("SkRlmtPacketReceive: PortNumber == %d.\n", PortNumber))
33425 + ("SkRlmtPacketReceive: PortNumber == %d.\n", PortNumber));
33427 pRPacket = (SK_RLMT_PACKET*)pMb->pData;
33428 pSPacket = (SK_SPTREE_PACKET*)pRPacket;
33429 @@ -916,7 +919,7 @@
33431 /* Not sent to current MAC or registered MC address => Trash it. */
33432 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33433 - ("SkRlmtPacketReceive: Not for me.\n"))
33434 + ("SkRlmtPacketReceive: Not for me.\n"));
33436 SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
33438 @@ -954,7 +957,7 @@
33439 pRPacket->Indicator[5] == SK_RLMT_INDICATOR5 &&
33440 pRPacket->Indicator[6] == SK_RLMT_INDICATOR6) {
33441 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33442 - ("SkRlmtPacketReceive: Duplicate MAC Address.\n"))
33443 + ("SkRlmtPacketReceive: Duplicate MAC Address.\n"));
33445 /* Error Log entry. */
33446 SK_ERR_LOG(pAC, SK_ERRCL_COMM, SKERR_RLMT_E006, SKERR_RLMT_E006_MSG);
33447 @@ -962,7 +965,7 @@
33449 /* Simply trash it. */
33450 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33451 - ("SkRlmtPacketReceive: Sent by me.\n"))
33452 + ("SkRlmtPacketReceive: Sent by me.\n"));
33455 SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
33456 @@ -1006,7 +1009,7 @@
33459 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33460 - ("SkRlmtPacketReceive: Announce.\n"))
33461 + ("SkRlmtPacketReceive: Announce.\n"));
33463 SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
33465 @@ -1014,7 +1017,7 @@
33466 case SK_PACKET_ALIVE:
33467 if (pRPacket->SSap & LLC_COMMAND_RESPONSE_BIT) {
33468 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33469 - ("SkRlmtPacketReceive: Alive Reply.\n"))
33470 + ("SkRlmtPacketReceive: Alive Reply.\n"));
33472 if (!(pAC->Addr.Port[PortNumber].PromMode & SK_PROM_MODE_LLC) ||
33474 @@ -1045,7 +1048,7 @@
33476 else { /* Alive Request Packet. */
33477 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33478 - ("SkRlmtPacketReceive: Alive Request.\n"))
33479 + ("SkRlmtPacketReceive: Alive Request.\n"));
33481 pRPort->RxHelloCts++;
33483 @@ -1064,7 +1067,7 @@
33485 case SK_PACKET_CHECK_TX:
33486 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33487 - ("SkRlmtPacketReceive: Check your tx line.\n"))
33488 + ("SkRlmtPacketReceive: Check your tx line.\n"));
33490 /* A port checking us requests us to check our tx line. */
33491 pRPort->CheckingState |= SK_RLMT_PCS_TX;
33492 @@ -1087,7 +1090,7 @@
33494 case SK_PACKET_ADDR_CHANGED:
33495 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33496 - ("SkRlmtPacketReceive: Address Change.\n"))
33497 + ("SkRlmtPacketReceive: Address Change.\n"));
33499 /* Build the check chain. */
33500 SkRlmtBuildCheckChain(pAC, pRPort->Net->NetNumber);
33501 @@ -1096,7 +1099,7 @@
33504 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33505 - ("SkRlmtPacketReceive: Unknown RLMT packet.\n"))
33506 + ("SkRlmtPacketReceive: Unknown RLMT packet.\n"));
33509 SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
33510 @@ -1106,7 +1109,7 @@
33511 pSPacket->Ctrl == SK_RLMT_SPT_CTRL &&
33512 (pSPacket->SSap & ~LLC_COMMAND_RESPONSE_BIT) == SK_RLMT_SPT_SSAP) {
33513 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33514 - ("SkRlmtPacketReceive: BPDU Packet.\n"))
33515 + ("SkRlmtPacketReceive: BPDU Packet.\n"));
33517 /* Spanning Tree packet. */
33518 pRPort->RxSpHelloCts++;
33519 @@ -1138,7 +1141,7 @@
33520 pRPort->Root.Id[0], pRPort->Root.Id[1],
33521 pRPort->Root.Id[2], pRPort->Root.Id[3],
33522 pRPort->Root.Id[4], pRPort->Root.Id[5],
33523 - pRPort->Root.Id[6], pRPort->Root.Id[7]))
33524 + pRPort->Root.Id[6], pRPort->Root.Id[7]));
33527 SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
33528 @@ -1149,7 +1152,7 @@
33531 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33532 - ("SkRlmtPacketReceive: Unknown Packet Type.\n"))
33533 + ("SkRlmtPacketReceive: Unknown Packet Type.\n"));
33535 /* Unknown packet. */
33536 SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
33537 @@ -1231,7 +1234,7 @@
33538 if ((pRPort->PacketsPerTimeSlot - pRPort->BpduPacketsPerTimeSlot) == 0) {
33539 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33540 ("SkRlmtCheckPort %d: No (%d) receives in last time slot.\n",
33541 - PortNumber, pRPort->PacketsPerTimeSlot))
33542 + PortNumber, pRPort->PacketsPerTimeSlot));
33545 * Check segmentation if there was no receive at least twice
33546 @@ -1248,7 +1251,7 @@
33548 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33549 ("SkRlmtCheckPort: PortsSuspect %d, PcsRx %d.\n",
33550 - pRPort->PortsSuspect, pRPort->CheckingState & SK_RLMT_PCS_RX))
33551 + pRPort->PortsSuspect, pRPort->CheckingState & SK_RLMT_PCS_RX));
33553 if (pRPort->PortState != SK_RLMT_PS_DOWN) {
33554 NewTimeout = TO_SHORTEN(pAC->Rlmt.Port[PortNumber].Net->TimeoutValue);
33555 @@ -1294,7 +1297,7 @@
33556 ("SkRlmtCheckPort %d: %d (%d) receives in last time slot.\n",
33558 pRPort->PacketsPerTimeSlot - pRPort->BpduPacketsPerTimeSlot,
33559 - pRPort->PacketsPerTimeSlot))
33560 + pRPort->PacketsPerTimeSlot));
33562 SkRlmtPortReceives(pAC, IoC, PortNumber);
33563 if (pAC->Rlmt.CheckSwitch) {
33564 @@ -1344,7 +1347,7 @@
33566 pAC->Rlmt.Port[i].PortDown, pAC->Rlmt.Port[i].PortNoRx,
33567 *((SK_U32*)(&pAC->Rlmt.Port[i].BcTimeStamp) + OFFS_HI32),
33568 - *((SK_U32*)(&pAC->Rlmt.Port[i].BcTimeStamp) + OFFS_LO32)))
33569 + *((SK_U32*)(&pAC->Rlmt.Port[i].BcTimeStamp) + OFFS_LO32)));
33571 if (!pAC->Rlmt.Port[i].PortDown && !pAC->Rlmt.Port[i].PortNoRx) {
33572 if (!PortFound || pAC->Rlmt.Port[i].BcTimeStamp > BcTimeStamp) {
33573 @@ -1357,7 +1360,7 @@
33576 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33577 - ("Port %d received the last broadcast.\n", *pSelect))
33578 + ("Port %d received the last broadcast.\n", *pSelect));
33580 /* Look if another port's time stamp is similar. */
33581 for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) {
33582 @@ -1372,7 +1375,7 @@
33583 PortFound = SK_FALSE;
33585 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33586 - ("Port %d received a broadcast at a similar time.\n", i))
33587 + ("Port %d received a broadcast at a similar time.\n", i));
33591 @@ -1384,7 +1387,7 @@
33592 ("SK_RLMT_SELECT_BCRX found Port %d receiving the substantially "
33593 "latest broadcast (%u).\n",
33595 - BcTimeStamp - pAC->Rlmt.Port[1 - *pSelect].BcTimeStamp))
33596 + BcTimeStamp - pAC->Rlmt.Port[1 - *pSelect].BcTimeStamp));
33600 @@ -1433,7 +1436,7 @@
33601 PortFound = SK_TRUE;
33602 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33603 ("SK_RLMT_SELECT_NOTSUSPECT found Port %d up and not check RX.\n",
33609 @@ -1482,7 +1485,7 @@
33611 PortFound = SK_TRUE;
33612 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33613 - ("SK_RLMT_SELECT_UP found Port %d up.\n", *pSelect))
33614 + ("SK_RLMT_SELECT_UP found Port %d up.\n", *pSelect));
33618 @@ -1543,7 +1546,7 @@
33621 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33622 - ("SK_RLMT_SELECT_GOINGUP found Port %d going up.\n", *pSelect))
33623 + ("SK_RLMT_SELECT_GOINGUP found Port %d going up.\n", *pSelect));
33625 } /* SkRlmtSelectGoingUp */
33627 @@ -1589,7 +1592,7 @@
33629 PortFound = SK_TRUE;
33630 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33631 - ("SK_RLMT_SELECT_DOWN found Port %d down.\n", *pSelect))
33632 + ("SK_RLMT_SELECT_DOWN found Port %d down.\n", *pSelect));
33636 @@ -1679,16 +1682,19 @@
33637 Para.Para32[1] = NetIdx;
33638 SkEventQueue(pAC, SKGE_DRV, SK_DRV_NET_UP, Para);
33640 - if ((pAC->Rlmt.Net[NetIdx].RlmtMode & SK_RLMT_TRANSPARENT) == 0 &&
33641 - (Para.pParaPtr = SkRlmtBuildPacket(pAC, IoC,
33642 - pAC->Rlmt.Net[NetIdx].Port[i]->PortNumber,
33643 - SK_PACKET_ANNOUNCE, &pAC->Addr.Net[NetIdx].
33644 - CurrentMacAddress, &SkRlmtMcAddr)) != NULL) {
33646 - * Send announce packet to RLMT multicast address to force
33647 - * switches to learn the new location of the logical MAC address.
33649 - SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para);
33650 + if (pAC->Rlmt.NumNets == 1) {
33651 + if ((pAC->Rlmt.Net[NetIdx].RlmtMode & SK_RLMT_TRANSPARENT) == 0 &&
33652 + (Para.pParaPtr = SkRlmtBuildPacket(pAC, IoC,
33653 + pAC->Rlmt.Net[NetIdx].Port[i]->PortNumber,
33654 + SK_PACKET_ANNOUNCE, &pAC->Addr.Net[NetIdx].
33655 + CurrentMacAddress, &SkRlmtMcAddr)) != NULL) {
33658 + * Send announce packet to RLMT multicast address to force
33659 + * switches to learn the new location of the logical MAC address.
33661 + SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para);
33666 @@ -1787,7 +1793,7 @@
33668 if (Para.Para32[1] != Active) {
33669 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33670 - ("Active: %d, Para1: %d.\n", Active, Para.Para32[1]))
33671 + ("Active: %d, Para1: %d.\n", Active, Para.Para32[1]));
33672 pAC->Rlmt.Net[NetIdx].ActivePort = Para.Para32[1];
33673 Para.Para32[0] = pAC->Rlmt.Net[NetIdx].
33674 Port[Para.Para32[0]]->PortNumber;
33675 @@ -1867,7 +1873,7 @@
33676 pNet->Port[i]->Root.Id[0], pNet->Port[i]->Root.Id[1],
33677 pNet->Port[i]->Root.Id[2], pNet->Port[i]->Root.Id[3],
33678 pNet->Port[i]->Root.Id[4], pNet->Port[i]->Root.Id[5],
33679 - pNet->Port[i]->Root.Id[6], pNet->Port[i]->Root.Id[7]))
33680 + pNet->Port[i]->Root.Id[6], pNet->Port[i]->Root.Id[7]));
33682 if (!pNet->RootIdSet) {
33683 pNet->Root = pNet->Port[i]->Root;
33684 @@ -1962,13 +1968,13 @@
33687 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33688 - ("SK_RLMT_PORTSTART_TIMEOUT Port %d Event BEGIN.\n", Para.Para32[0]))
33689 + ("SK_RLMT_PORTSTART_TIMEOUT Port %d Event BEGIN.\n", Para.Para32[0]));
33691 if (Para.Para32[1] != (SK_U32)-1) {
33692 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33693 - ("Bad Parameter.\n"))
33694 + ("Bad Parameter.\n"));
33695 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33696 - ("SK_RLMT_PORTSTART_TIMEOUT Event EMPTY.\n"))
33697 + ("SK_RLMT_PORTSTART_TIMEOUT Event EMPTY.\n"));
33701 @@ -1989,7 +1995,7 @@
33704 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33705 - ("SK_RLMT_PORTSTART_TIMEOUT Event END.\n"))
33706 + ("SK_RLMT_PORTSTART_TIMEOUT Event END.\n"));
33707 } /* SkRlmtEvtPortStartTim */
33710 @@ -2017,21 +2023,21 @@
33713 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33714 - ("SK_RLMT_LINK_UP Port %d Event BEGIN.\n", Para.Para32[0]))
33715 + ("SK_RLMT_LINK_UP Port %d Event BEGIN.\n", Para.Para32[0]));
33717 pRPort = &pAC->Rlmt.Port[Para.Para32[0]];
33718 if (!pRPort->PortStarted) {
33719 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_RLMT_E008, SKERR_RLMT_E008_MSG);
33721 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33722 - ("SK_RLMT_LINK_UP Event EMPTY.\n"))
33723 + ("SK_RLMT_LINK_UP Event EMPTY.\n"));
33727 if (!pRPort->LinkDown) {
33728 /* RA;:;: Any better solution? */
33729 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33730 - ("SK_RLMT_LINK_UP Event EMPTY.\n"))
33731 + ("SK_RLMT_LINK_UP Event EMPTY.\n"));
33735 @@ -2081,16 +2087,19 @@
33736 Para2.Para32[1] = (SK_U32)-1;
33737 SkTimerStart(pAC, IoC, &pRPort->UpTimer, SK_RLMT_PORTUP_TIM_VAL,
33738 SKGE_RLMT, SK_RLMT_PORTUP_TIM, Para2);
33741 /* Later: if (pAC->Rlmt.RlmtMode & SK_RLMT_CHECK_LOC_LINK) && */
33742 - if ((pRPort->Net->RlmtMode & SK_RLMT_TRANSPARENT) == 0 &&
33743 - (pRPort->Net->RlmtMode & SK_RLMT_CHECK_LINK) != 0 &&
33744 - (Para2.pParaPtr =
33745 - SkRlmtBuildPacket(pAC, IoC, Para.Para32[0], SK_PACKET_ANNOUNCE,
33746 - &pAC->Addr.Port[Para.Para32[0]].CurrentMacAddress, &SkRlmtMcAddr)
33748 - /* Send "new" packet to RLMT multicast address. */
33749 - SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para2);
33750 + if (pAC->Rlmt.NumNets == 1) {
33751 + if ((pRPort->Net->RlmtMode & SK_RLMT_TRANSPARENT) == 0 &&
33752 + (pRPort->Net->RlmtMode & SK_RLMT_CHECK_LINK) != 0 &&
33753 + (Para2.pParaPtr =
33754 + SkRlmtBuildPacket(pAC, IoC, Para.Para32[0], SK_PACKET_ANNOUNCE,
33755 + &pAC->Addr.Port[Para.Para32[0]].CurrentMacAddress, &SkRlmtMcAddr)
33758 + /* Send "new" packet to RLMT multicast address. */
33759 + SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para2);
33763 if (pRPort->Net->RlmtMode & SK_RLMT_CHECK_SEG) {
33764 @@ -2109,7 +2118,7 @@
33767 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33768 - ("SK_RLMT_LINK_UP Event END.\n"))
33769 + ("SK_RLMT_LINK_UP Event END.\n"));
33770 } /* SkRlmtEvtLinkUp */
33773 @@ -2135,20 +2144,20 @@
33774 SK_RLMT_PORT *pRPort;
33776 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33777 - ("SK_RLMT_PORTUP_TIM Port %d Event BEGIN.\n", Para.Para32[0]))
33778 + ("SK_RLMT_PORTUP_TIM Port %d Event BEGIN.\n", Para.Para32[0]));
33780 if (Para.Para32[1] != (SK_U32)-1) {
33781 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33782 - ("Bad Parameter.\n"))
33783 + ("Bad Parameter.\n"));
33784 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33785 - ("SK_RLMT_PORTUP_TIM Event EMPTY.\n"))
33786 + ("SK_RLMT_PORTUP_TIM Event EMPTY.\n"));
33790 pRPort = &pAC->Rlmt.Port[Para.Para32[0]];
33791 if (pRPort->LinkDown || (pRPort->PortState == SK_RLMT_PS_UP)) {
33792 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33793 - ("SK_RLMT_PORTUP_TIM Port %d Event EMPTY.\n", Para.Para32[0]))
33794 + ("SK_RLMT_PORTUP_TIM Port %d Event EMPTY.\n", Para.Para32[0]));
33798 @@ -2163,7 +2172,7 @@
33801 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33802 - ("SK_RLMT_PORTUP_TIM Event END.\n"))
33803 + ("SK_RLMT_PORTUP_TIM Event END.\n"));
33804 } /* SkRlmtEvtPortUpTim */
33807 @@ -2191,13 +2200,13 @@
33809 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33810 ("SK_RLMT_PORTDOWN* Port %d Event (%d) BEGIN.\n",
33811 - Para.Para32[0], Event))
33812 + Para.Para32[0], Event));
33814 if (Para.Para32[1] != (SK_U32)-1) {
33815 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33816 - ("Bad Parameter.\n"))
33817 + ("Bad Parameter.\n"));
33818 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33819 - ("SK_RLMT_PORTDOWN* Event EMPTY.\n"))
33820 + ("SK_RLMT_PORTDOWN* Event EMPTY.\n"));
33824 @@ -2205,7 +2214,7 @@
33825 if (!pRPort->PortStarted || (Event == SK_RLMT_PORTDOWN_TX_TIM &&
33826 !(pRPort->CheckingState & SK_RLMT_PCS_TX))) {
33827 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33828 - ("SK_RLMT_PORTDOWN* Event (%d) EMPTY.\n", Event))
33829 + ("SK_RLMT_PORTDOWN* Event (%d) EMPTY.\n", Event));
33833 @@ -2242,7 +2251,7 @@
33836 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33837 - ("SK_RLMT_PORTDOWN* Event (%d) END.\n", Event))
33838 + ("SK_RLMT_PORTDOWN* Event (%d) END.\n", Event));
33839 } /* SkRlmtEvtPortDownX */
33842 @@ -2269,7 +2278,7 @@
33844 pRPort = &pAC->Rlmt.Port[Para.Para32[0]];
33845 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33846 - ("SK_RLMT_LINK_DOWN Port %d Event BEGIN.\n", Para.Para32[0]))
33847 + ("SK_RLMT_LINK_DOWN Port %d Event BEGIN.\n", Para.Para32[0]));
33849 if (!pAC->Rlmt.Port[Para.Para32[0]].LinkDown) {
33850 pRPort->Net->LinksUp--;
33851 @@ -2288,7 +2297,7 @@
33854 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33855 - ("SK_RLMT_LINK_DOWN Event END.\n"))
33856 + ("SK_RLMT_LINK_DOWN Event END.\n"));
33857 } /* SkRlmtEvtLinkDown */
33860 @@ -2317,13 +2326,13 @@
33861 SK_MAC_ADDR *pNewMacAddr;
33863 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33864 - ("SK_RLMT_PORT_ADDR Port %d Event BEGIN.\n", Para.Para32[0]))
33865 + ("SK_RLMT_PORT_ADDR Port %d Event BEGIN.\n", Para.Para32[0]));
33867 if (Para.Para32[1] != (SK_U32)-1) {
33868 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33869 - ("Bad Parameter.\n"))
33870 + ("Bad Parameter.\n"));
33871 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33872 - ("SK_RLMT_PORT_ADDR Event EMPTY.\n"))
33873 + ("SK_RLMT_PORT_ADDR Event EMPTY.\n"));
33877 @@ -2347,7 +2356,7 @@
33880 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33881 - ("SK_RLMT_PORT_ADDR Event END.\n"))
33882 + ("SK_RLMT_PORT_ADDR Event END.\n"));
33883 } /* SkRlmtEvtPortAddr */
33886 @@ -2375,35 +2384,35 @@
33889 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33890 - ("SK_RLMT_START Net %d Event BEGIN.\n", Para.Para32[0]))
33891 + ("SK_RLMT_START Net %d Event BEGIN.\n", Para.Para32[0]));
33893 if (Para.Para32[1] != (SK_U32)-1) {
33894 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33895 - ("Bad Parameter.\n"))
33896 + ("Bad Parameter.\n"));
33897 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33898 - ("SK_RLMT_START Event EMPTY.\n"))
33899 + ("SK_RLMT_START Event EMPTY.\n"));
33903 if (Para.Para32[0] >= pAC->Rlmt.NumNets) {
33904 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33905 - ("Bad NetNumber %d.\n", Para.Para32[0]))
33906 + ("Bad NetNumber %d.\n", Para.Para32[0]));
33907 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33908 - ("SK_RLMT_START Event EMPTY.\n"))
33909 + ("SK_RLMT_START Event EMPTY.\n"));
33913 if (pAC->Rlmt.Net[Para.Para32[0]].RlmtState != SK_RLMT_RS_INIT) {
33914 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33915 - ("SK_RLMT_START Event EMPTY.\n"))
33916 + ("SK_RLMT_START Event EMPTY.\n"));
33920 if (pAC->Rlmt.NetsStarted >= pAC->Rlmt.NumNets) {
33921 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33922 - ("All nets should have been started.\n"))
33923 + ("All nets should have been started.\n"));
33924 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33925 - ("SK_RLMT_START Event EMPTY.\n"))
33926 + ("SK_RLMT_START Event EMPTY.\n"));
33930 @@ -2437,7 +2446,7 @@
33931 pAC->Rlmt.NetsStarted++;
33933 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33934 - ("SK_RLMT_START Event END.\n"))
33935 + ("SK_RLMT_START Event END.\n"));
33936 } /* SkRlmtEvtStart */
33939 @@ -2465,35 +2474,35 @@
33942 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33943 - ("SK_RLMT_STOP Net %d Event BEGIN.\n", Para.Para32[0]))
33944 + ("SK_RLMT_STOP Net %d Event BEGIN.\n", Para.Para32[0]));
33946 if (Para.Para32[1] != (SK_U32)-1) {
33947 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33948 - ("Bad Parameter.\n"))
33949 + ("Bad Parameter.\n"));
33950 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33951 - ("SK_RLMT_STOP Event EMPTY.\n"))
33952 + ("SK_RLMT_STOP Event EMPTY.\n"));
33956 if (Para.Para32[0] >= pAC->Rlmt.NumNets) {
33957 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33958 - ("Bad NetNumber %d.\n", Para.Para32[0]))
33959 + ("Bad NetNumber %d.\n", Para.Para32[0]));
33960 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33961 - ("SK_RLMT_STOP Event EMPTY.\n"))
33962 + ("SK_RLMT_STOP Event EMPTY.\n"));
33966 if (pAC->Rlmt.Net[Para.Para32[0]].RlmtState == SK_RLMT_RS_INIT) {
33967 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33968 - ("SK_RLMT_STOP Event EMPTY.\n"))
33969 + ("SK_RLMT_STOP Event EMPTY.\n"));
33973 if (pAC->Rlmt.NetsStarted == 0) {
33974 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33975 - ("All nets are stopped.\n"))
33976 + ("All nets are stopped.\n"));
33977 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33978 - ("SK_RLMT_STOP Event EMPTY.\n"))
33979 + ("SK_RLMT_STOP Event EMPTY.\n"));
33983 @@ -2528,7 +2537,7 @@
33984 pAC->Rlmt.NetsStarted--;
33986 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33987 - ("SK_RLMT_STOP Event END.\n"))
33988 + ("SK_RLMT_STOP Event END.\n"));
33989 } /* SkRlmtEvtStop */
33992 @@ -2558,13 +2567,13 @@
33995 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33996 - ("SK_RLMT_TIM Event BEGIN.\n"))
33997 + ("SK_RLMT_TIM Event BEGIN.\n"));
33999 if (Para.Para32[1] != (SK_U32)-1) {
34000 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34001 - ("Bad Parameter.\n"))
34002 + ("Bad Parameter.\n"));
34003 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34004 - ("SK_RLMT_TIM Event EMPTY.\n"))
34005 + ("SK_RLMT_TIM Event EMPTY.\n"));
34009 @@ -2636,7 +2645,7 @@
34012 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34013 - ("SK_RLMT_TIM Event END.\n"))
34014 + ("SK_RLMT_TIM Event END.\n"));
34015 } /* SkRlmtEvtTim */
34018 @@ -2664,13 +2673,13 @@
34021 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34022 - ("SK_RLMT_SEG_TIM Event BEGIN.\n"))
34023 + ("SK_RLMT_SEG_TIM Event BEGIN.\n"));
34025 if (Para.Para32[1] != (SK_U32)-1) {
34026 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34027 - ("Bad Parameter.\n"))
34028 + ("Bad Parameter.\n"));
34029 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34030 - ("SK_RLMT_SEG_TIM Event EMPTY.\n"))
34031 + ("SK_RLMT_SEG_TIM Event EMPTY.\n"));
34035 @@ -2694,7 +2703,7 @@
34036 InAddr8[3], InAddr8[4], InAddr8[5],
34037 pAPort->Exact[k].a[0], pAPort->Exact[k].a[1],
34038 pAPort->Exact[k].a[2], pAPort->Exact[k].a[3],
34039 - pAPort->Exact[k].a[4], pAPort->Exact[k].a[5]))
34040 + pAPort->Exact[k].a[4], pAPort->Exact[k].a[5]));
34043 #endif /* xDEBUG */
34044 @@ -2702,7 +2711,7 @@
34045 SkRlmtCheckSeg(pAC, IoC, Para.Para32[0]);
34047 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34048 - ("SK_RLMT_SEG_TIM Event END.\n"))
34049 + ("SK_RLMT_SEG_TIM Event END.\n"));
34050 } /* SkRlmtEvtSegTim */
34053 @@ -2731,18 +2740,18 @@
34056 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34057 - ("SK_RLMT_PACKET_RECEIVED Event BEGIN.\n"))
34058 + ("SK_RLMT_PACKET_RECEIVED Event BEGIN.\n"));
34060 /* Should we ignore frames during port switching? */
34063 pMb = Para.pParaPtr;
34065 - SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, ("No mbuf.\n"))
34066 + SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, ("No mbuf.\n"));
34068 else if (pMb->pNext != NULL) {
34069 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34070 - ("More than one mbuf or pMb->pNext not set.\n"))
34071 + ("More than one mbuf or pMb->pNext not set.\n"));
34075 @@ -2760,7 +2769,7 @@
34078 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34079 - ("SK_RLMT_PACKET_RECEIVED Event END.\n"))
34080 + ("SK_RLMT_PACKET_RECEIVED Event END.\n"));
34081 } /* SkRlmtEvtPacketRx */
34084 @@ -2787,21 +2796,21 @@
34085 SK_RLMT_PORT *pRPort;
34087 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34088 - ("SK_RLMT_STATS_CLEAR Event BEGIN.\n"))
34089 + ("SK_RLMT_STATS_CLEAR Event BEGIN.\n"));
34091 if (Para.Para32[1] != (SK_U32)-1) {
34092 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34093 - ("Bad Parameter.\n"))
34094 + ("Bad Parameter.\n"));
34095 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34096 - ("SK_RLMT_STATS_CLEAR Event EMPTY.\n"))
34097 + ("SK_RLMT_STATS_CLEAR Event EMPTY.\n"));
34101 if (Para.Para32[0] >= pAC->Rlmt.NumNets) {
34102 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34103 - ("Bad NetNumber %d.\n", Para.Para32[0]))
34104 + ("Bad NetNumber %d.\n", Para.Para32[0]));
34105 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34106 - ("SK_RLMT_STATS_CLEAR Event EMPTY.\n"))
34107 + ("SK_RLMT_STATS_CLEAR Event EMPTY.\n"));
34111 @@ -2816,7 +2825,7 @@
34114 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34115 - ("SK_RLMT_STATS_CLEAR Event END.\n"))
34116 + ("SK_RLMT_STATS_CLEAR Event END.\n"));
34117 } /* SkRlmtEvtStatsClear */
34120 @@ -2840,28 +2849,28 @@
34121 SK_EVPARA Para) /* SK_U32 NetNumber; SK_U32 -1 */
34123 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34124 - ("SK_RLMT_STATS_UPDATE Event BEGIN.\n"))
34125 + ("SK_RLMT_STATS_UPDATE Event BEGIN.\n"));
34127 if (Para.Para32[1] != (SK_U32)-1) {
34128 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34129 - ("Bad Parameter.\n"))
34130 + ("Bad Parameter.\n"));
34131 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34132 - ("SK_RLMT_STATS_UPDATE Event EMPTY.\n"))
34133 + ("SK_RLMT_STATS_UPDATE Event EMPTY.\n"));
34137 if (Para.Para32[0] >= pAC->Rlmt.NumNets) {
34138 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34139 - ("Bad NetNumber %d.\n", Para.Para32[0]))
34140 + ("Bad NetNumber %d.\n", Para.Para32[0]));
34141 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34142 - ("SK_RLMT_STATS_UPDATE Event EMPTY.\n"))
34143 + ("SK_RLMT_STATS_UPDATE Event EMPTY.\n"));
34147 /* Update statistics - currently always up-to-date. */
34149 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34150 - ("SK_RLMT_STATS_UPDATE Event END.\n"))
34151 + ("SK_RLMT_STATS_UPDATE Event END.\n"));
34152 } /* SkRlmtEvtStatsUpdate */
34155 @@ -2885,13 +2894,13 @@
34156 SK_EVPARA Para) /* SK_U32 PortIndex; SK_U32 NetNumber */
34158 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34159 - ("SK_RLMT_PREFPORT_CHANGE to Port %d Event BEGIN.\n", Para.Para32[0]))
34160 + ("SK_RLMT_PREFPORT_CHANGE to Port %d Event BEGIN.\n", Para.Para32[0]));
34162 if (Para.Para32[1] >= pAC->Rlmt.NumNets) {
34163 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34164 - ("Bad NetNumber %d.\n", Para.Para32[1]))
34165 + ("Bad NetNumber %d.\n", Para.Para32[1]));
34166 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34167 - ("SK_RLMT_PREFPORT_CHANGE Event EMPTY.\n"))
34168 + ("SK_RLMT_PREFPORT_CHANGE Event EMPTY.\n"));
34172 @@ -2904,7 +2913,7 @@
34173 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_RLMT_E010, SKERR_RLMT_E010_MSG);
34175 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34176 - ("SK_RLMT_PREFPORT_CHANGE Event EMPTY.\n"))
34177 + ("SK_RLMT_PREFPORT_CHANGE Event EMPTY.\n"));
34181 @@ -2918,7 +2927,7 @@
34184 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34185 - ("SK_RLMT_PREFPORT_CHANGE Event END.\n"))
34186 + ("SK_RLMT_PREFPORT_CHANGE Event END.\n"));
34187 } /* SkRlmtEvtPrefportChange */
34190 @@ -2944,37 +2953,37 @@
34193 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34194 - ("SK_RLMT_SET_NETS Event BEGIN.\n"))
34195 + ("SK_RLMT_SET_NETS Event BEGIN.\n"));
34197 if (Para.Para32[1] != (SK_U32)-1) {
34198 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34199 - ("Bad Parameter.\n"))
34200 + ("Bad Parameter.\n"));
34201 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34202 - ("SK_RLMT_SET_NETS Event EMPTY.\n"))
34203 + ("SK_RLMT_SET_NETS Event EMPTY.\n"));
34207 if (Para.Para32[0] == 0 || Para.Para32[0] > SK_MAX_NETS ||
34208 Para.Para32[0] > (SK_U32)pAC->GIni.GIMacsFound) {
34209 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34210 - ("Bad number of nets: %d.\n", Para.Para32[0]))
34211 + ("Bad number of nets: %d.\n", Para.Para32[0]));
34212 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34213 - ("SK_RLMT_SET_NETS Event EMPTY.\n"))
34214 + ("SK_RLMT_SET_NETS Event EMPTY.\n"));
34218 if (Para.Para32[0] == pAC->Rlmt.NumNets) { /* No change. */
34219 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34220 - ("SK_RLMT_SET_NETS Event EMPTY.\n"))
34221 + ("SK_RLMT_SET_NETS Event EMPTY.\n"));
34225 /* Entering and leaving dual mode only allowed while nets are stopped. */
34226 if (pAC->Rlmt.NetsStarted > 0) {
34227 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34228 - ("Changing dual mode only allowed while all nets are stopped.\n"))
34229 + ("Changing dual mode only allowed while all nets are stopped.\n"));
34230 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34231 - ("SK_RLMT_SET_NETS Event EMPTY.\n"))
34232 + ("SK_RLMT_SET_NETS Event EMPTY.\n"));
34236 @@ -3005,9 +3014,10 @@
34237 SkEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_RLMT_SET_NETS, Para);
34239 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34240 - ("RLMT: Changed to one net with two ports.\n"))
34241 + ("RLMT: Changed to one net with two ports.\n"));
34243 else if (Para.Para32[0] == 2) {
34244 + pAC->Rlmt.RlmtOff = SK_TRUE;
34245 pAC->Rlmt.Port[1].Net= &pAC->Rlmt.Net[1];
34246 pAC->Rlmt.Net[1].NumPorts = pAC->GIni.GIMacsFound - 1;
34247 pAC->Rlmt.Net[0].NumPorts =
34248 @@ -3034,19 +3044,19 @@
34249 SkEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_RLMT_SET_NETS, Para);
34251 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34252 - ("RLMT: Changed to two nets with one port each.\n"))
34253 + ("RLMT: Changed to two nets with one port each.\n"));
34256 /* Not implemented for more than two nets. */
34257 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34258 - ("SetNets not implemented for more than two nets.\n"))
34259 + ("SetNets not implemented for more than two nets.\n"));
34260 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34261 - ("SK_RLMT_SET_NETS Event EMPTY.\n"))
34262 + ("SK_RLMT_SET_NETS Event EMPTY.\n"));
34266 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34267 - ("SK_RLMT_SET_NETS Event END.\n"))
34268 + ("SK_RLMT_SET_NETS Event END.\n"));
34269 } /* SkRlmtSetNets */
34272 @@ -3074,13 +3084,13 @@
34273 SK_U32 PrevRlmtMode;
34275 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34276 - ("SK_RLMT_MODE_CHANGE Event BEGIN.\n"))
34277 + ("SK_RLMT_MODE_CHANGE Event BEGIN.\n"));
34279 if (Para.Para32[1] >= pAC->Rlmt.NumNets) {
34280 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34281 - ("Bad NetNumber %d.\n", Para.Para32[1]))
34282 + ("Bad NetNumber %d.\n", Para.Para32[1]));
34283 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34284 - ("SK_RLMT_MODE_CHANGE Event EMPTY.\n"))
34285 + ("SK_RLMT_MODE_CHANGE Event EMPTY.\n"));
34289 @@ -3090,9 +3100,9 @@
34290 Para.Para32[0] != SK_RLMT_MODE_CLS) {
34291 pAC->Rlmt.Net[Para.Para32[1]].RlmtMode = SK_RLMT_MODE_CLS;
34292 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34293 - ("Forced RLMT mode to CLS on single port net.\n"))
34294 + ("Forced RLMT mode to CLS on single port net.\n"));
34295 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34296 - ("SK_RLMT_MODE_CHANGE Event EMPTY.\n"))
34297 + ("SK_RLMT_MODE_CHANGE Event EMPTY.\n"));
34301 @@ -3158,7 +3168,7 @@
34302 } /* SK_RLMT_CHECK_SEG bit changed. */
34304 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34305 - ("SK_RLMT_MODE_CHANGE Event END.\n"))
34306 + ("SK_RLMT_MODE_CHANGE Event END.\n"));
34307 } /* SkRlmtEvtModeChange */
34310 @@ -3244,7 +3254,7 @@
34312 default: /* Create error log entry. */
34313 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34314 - ("Unknown RLMT Event %d.\n", Event))
34315 + ("Unknown RLMT Event %d.\n", Event));
34316 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_RLMT_E003, SKERR_RLMT_E003_MSG);
34319 diff -ruN linux/drivers/net/sk98lin/sktimer.c linux-new/drivers/net/sk98lin/sktimer.c
34320 --- linux/drivers/net/sk98lin/sktimer.c 2006-09-20 05:42:06.000000000 +0200
34321 +++ linux-new/drivers/net/sk98lin/sktimer.c 2006-07-28 14:13:54.000000000 +0200
34325 * Project: Gigabit Ethernet Adapters, Event Scheduler Module
34326 - * Version: $Revision$
34328 + * Version: $Revision$
34330 * Purpose: High level timer functions.
34332 ******************************************************************************/
34334 /******************************************************************************
34337 * (C)Copyright 1998-2002 SysKonnect GmbH.
34338 - * (C)Copyright 2002-2003 Marvell.
34339 + * (C)Copyright 2002-2004 Marvell.
34341 * This program is free software; you can redistribute it and/or modify
34342 * it under the terms of the GNU General Public License as published by
34343 @@ -19,16 +20,16 @@
34344 * (at your option) any later version.
34346 * The information in this file is provided "AS IS" without warranty.
34349 ******************************************************************************/
34353 * Event queue and dispatcher
34355 #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
34356 static const char SysKonnectFileId[] =
34357 - "@(#) $Id$ (C) Marvell.";
34358 + "@(#) $Id$ (C) Marvell.";
34361 #include "h/skdrv1st.h" /* Driver Specific Definitions */
34366 - pAC->Tim.StQueue = NULL;
34367 + pAC->Tim.StQueue = 0;
34370 SkHwtInit(pAC, Ioc);
34371 @@ -85,22 +86,20 @@
34372 SK_TIMER **ppTimPrev;
34376 - * remove timer from queue
34378 + /* remove timer from queue */
34379 pTimer->TmActive = SK_FALSE;
34382 if (pAC->Tim.StQueue == pTimer && !pTimer->TmNext) {
34383 SkHwtStop(pAC, Ioc);
34387 for (ppTimPrev = &pAC->Tim.StQueue; (pTm = *ppTimPrev);
34388 ppTimPrev = &pTm->TmNext ) {
34391 if (pTm == pTimer) {
34393 * Timer found in queue
34394 - * - dequeue it and
34396 * - correct delta of the next timer
34398 *ppTimPrev = pTm->TmNext;
34399 @@ -121,7 +120,7 @@
34400 SK_AC *pAC, /* Adapters context */
34401 SK_IOC Ioc, /* IoContext */
34402 SK_TIMER *pTimer, /* Timer Pointer to be started */
34403 -SK_U32 Time, /* Time value */
34404 +SK_U32 Time, /* Time Value (in microsec.) */
34405 SK_U32 Class, /* Event Class for this timer */
34406 SK_U32 Event, /* Event Value for this timer */
34407 SK_EVPARA Para) /* Event Parameter for this timer */
34408 @@ -130,11 +129,6 @@
34412 - Time /= 16; /* input is uS, clock ticks are 16uS */
34417 SkTimerStop(pAC, Ioc, pTimer);
34419 pTimer->TmClass = Class;
34420 @@ -143,31 +137,26 @@
34421 pTimer->TmActive = SK_TRUE;
34423 if (!pAC->Tim.StQueue) {
34424 - /* First Timer to be started */
34425 + /* first Timer to be started */
34426 pAC->Tim.StQueue = pTimer;
34427 - pTimer->TmNext = NULL;
34428 + pTimer->TmNext = 0;
34429 pTimer->TmDelta = Time;
34432 SkHwtStart(pAC, Ioc, Time);
34439 - * timer correction
34441 + /* timer correction */
34442 timer_done(pAC, Ioc, 0);
34445 - * find position in queue
34447 + /* find position in queue */
34449 for (ppTimPrev = &pAC->Tim.StQueue; (pTm = *ppTimPrev);
34450 ppTimPrev = &pTm->TmNext ) {
34453 if (Delta + pTm->TmDelta > Time) {
34454 - /* Position found */
34455 - /* Here the timer needs to be inserted. */
34456 + /* the timer needs to be inserted here */
34459 Delta += pTm->TmDelta;
34460 @@ -179,9 +168,7 @@
34461 pTimer->TmDelta = Time - Delta;
34464 - /* There is a next timer
34465 - * -> correct its Delta value.
34467 + /* there is a next timer: correct its Delta value */
34468 pTm->TmDelta -= pTimer->TmDelta;
34471 @@ -210,7 +197,7 @@
34474 Delta = SkHwtRead(pAC, Ioc);
34477 ppLast = &pAC->Tim.StQueue;
34478 pTm = pAC->Tim.StQueue;
34479 while (pTm && !Done) {
34480 @@ -228,13 +215,13 @@
34487 * pTm points to the first Timer that did not run out.
34488 * StQueue points to the first Timer that run out.
34491 - for ( pTComp = pAC->Tim.StQueue; pTComp; pTComp = pTComp->TmNext) {
34492 + for (pTComp = pAC->Tim.StQueue; pTComp; pTComp = pTComp->TmNext) {
34493 SkEventQueue(pAC,pTComp->TmClass, pTComp->TmEvent, pTComp->TmPara);
34496 diff -ruN linux/drivers/net/sk98lin/sktwsi.c linux-new/drivers/net/sk98lin/sktwsi.c
34497 --- linux/drivers/net/sk98lin/sktwsi.c 1970-01-01 01:00:00.000000000 +0100
34498 +++ linux-new/drivers/net/sk98lin/sktwsi.c 2006-07-28 14:13:54.000000000 +0200
34500 +/******************************************************************************
34503 + * Project: Gigabit Ethernet Adapters, TWSI-Module
34504 + * Version: $Revision$
34506 + * Purpose: Functions to access Voltage and Temperature Sensor
34508 + ******************************************************************************/
34510 +/******************************************************************************
34513 + * (C)Copyright 1998-2002 SysKonnect.
34514 + * (C)Copyright 2002-2005 Marvell.
34516 + * This program is free software; you can redistribute it and/or modify
34517 + * it under the terms of the GNU General Public License as published by
34518 + * the Free Software Foundation; either version 2 of the License, or
34519 + * (at your option) any later version.
34520 + * The information in this file is provided "AS IS" without warranty.
34523 + ******************************************************************************/
34528 +#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
34529 +static const char SysKonnectFileId[] =
34530 + "@(#) $Id$ (C) Marvell.";
34533 +#include "h/skdrv1st.h" /* Driver Specific Definitions */
34534 +#include "h/lm80.h"
34535 +#include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */
34539 + TWSI protocol implementation.
34541 + General Description:
34543 + The TWSI protocol is used for the temperature sensors and for
34544 + the serial EEPROM which hold the configuration.
34546 + This file covers functions that allow to read write and do
34547 + some bulk requests a specified TWSI address.
34549 + The Genesis has 2 TWSI buses. One for the EEPROM which holds
34550 + the VPD Data and one for temperature and voltage sensor.
34551 + The following picture shows the TWSI buses, TWSI devices and
34552 + their control registers.
34554 + Note: The VPD functions are in skvpd.c
34556 +. PCI Config TWSI Bus for VPD Data:
34564 +. +-----------+-----------+
34566 +. +-----------------+ +-----------------+
34567 +. | PCI_VPD_ADR_REG | | PCI_VPD_DAT_REG |
34568 +. +-----------------+ +-----------------+
34571 +. TWSI Bus for LM80 sensor:
34573 +. +-----------------+
34574 +. | Temperature and |
34575 +. | Voltage Sensor |
34577 +. +-----------------+
34583 +. +-------------->| OR |<--+
34585 +. +------+------+ |
34587 +. +--------+ +--------+ +----------+
34588 +. | B2_I2C | | B2_I2C | | B2_I2C |
34589 +. | _CTRL | | _DATA | | _SW |
34590 +. +--------+ +--------+ +----------+
34592 + The TWSI bus may be driven by the B2_I2C_SW or by the B2_I2C_CTRL
34593 + and B2_I2C_DATA registers.
34594 + For driver software it is recommended to use the TWSI control and
34595 + data register, because TWSI bus timing is done by the ASIC and
34596 + an interrupt may be received when the TWSI request is completed.
34598 + Clock Rate Timing: MIN MAX generated by
34599 + VPD EEPROM: 50 kHz 100 kHz HW
34600 + LM80 over TWSI Ctrl/Data reg. 50 kHz 100 kHz HW
34601 + LM80 over B2_I2C_SW register 0 400 kHz SW
34603 + Note: The clock generated by the hardware is dependend on the
34604 + PCI clock. If the PCI bus clock is 33 MHz, the I2C/VPD
34613 + * TWSI Fast Mode timing values used by the LM80.
34614 + * If new devices are added to the TWSI bus the timing values have to be checked.
34616 +#ifndef I2C_SLOW_TIMING
34617 +#define T_CLK_LOW 1300L /* clock low time in ns */
34618 +#define T_CLK_HIGH 600L /* clock high time in ns */
34619 +#define T_DATA_IN_SETUP 100L /* data in Set-up Time */
34620 +#define T_START_HOLD 600L /* start condition hold time */
34621 +#define T_START_SETUP 600L /* start condition Set-up time */
34622 +#define T_STOP_SETUP 600L /* stop condition Set-up time */
34623 +#define T_BUS_IDLE 1300L /* time the bus must free after Tx */
34624 +#define T_CLK_2_DATA_OUT 900L /* max. clock low to data output valid */
34625 +#else /* I2C_SLOW_TIMING */
34626 +/* TWSI Standard Mode Timing */
34627 +#define T_CLK_LOW 4700L /* clock low time in ns */
34628 +#define T_CLK_HIGH 4000L /* clock high time in ns */
34629 +#define T_DATA_IN_SETUP 250L /* data in Set-up Time */
34630 +#define T_START_HOLD 4000L /* start condition hold time */
34631 +#define T_START_SETUP 4700L /* start condition Set-up time */
34632 +#define T_STOP_SETUP 4000L /* stop condition Set-up time */
34633 +#define T_BUS_IDLE 4700L /* time the bus must free after Tx */
34634 +#endif /* !I2C_SLOW_TIMING */
34636 +#define NS2BCLK(x) (((x)*125)/10000)
34639 + * TWSI Wire Operations
34641 + * About I2C_CLK_LOW():
34643 + * The Data Direction bit (I2C_DATA_DIR) has to be set to input when setting
34644 + * clock to low, to prevent the ASIC and the TWSI data client from driving the
34645 + * serial data line simultaneously (ASIC: last bit of a byte = '1', TWSI client
34646 + * send an 'ACK'). See also Concentrator Bugreport No. 10192.
34648 +#define I2C_DATA_HIGH(IoC) SK_I2C_SET_BIT(IoC, I2C_DATA)
34649 +#define I2C_DATA_LOW(IoC) SK_I2C_CLR_BIT(IoC, I2C_DATA)
34650 +#define I2C_DATA_OUT(IoC) SK_I2C_SET_BIT(IoC, I2C_DATA_DIR)
34651 +#define I2C_DATA_IN(IoC) SK_I2C_CLR_BIT(IoC, I2C_DATA_DIR | I2C_DATA)
34652 +#define I2C_CLK_HIGH(IoC) SK_I2C_SET_BIT(IoC, I2C_CLK)
34653 +#define I2C_CLK_LOW(IoC) SK_I2C_CLR_BIT(IoC, I2C_CLK | I2C_DATA_DIR)
34654 +#define I2C_START_COND(IoC) SK_I2C_CLR_BIT(IoC, I2C_CLK)
34656 +#define NS2CLKT(x) ((x*125L)/10000)
34658 +/*--------------- TWSI Interface Register Functions --------------- */
34661 + * sending one bit
34664 +SK_IOC IoC, /* I/O Context */
34665 +SK_U8 Bit) /* Bit to send */
34667 + I2C_DATA_OUT(IoC);
34669 + I2C_DATA_HIGH(IoC);
34672 + I2C_DATA_LOW(IoC);
34674 + SkDgWaitTime(IoC, NS2BCLK(T_DATA_IN_SETUP));
34675 + I2C_CLK_HIGH(IoC);
34676 + SkDgWaitTime(IoC, NS2BCLK(T_CLK_HIGH));
34677 + I2C_CLK_LOW(IoC);
34678 +} /* SkI2cSndBit*/
34682 + * Signal a start to the TWSI Bus.
34684 + * A start is signaled when data goes to low in a high clock cycle.
34686 + * Ends with Clock Low.
34688 + * Status: not tested
34691 +SK_IOC IoC) /* I/O Context */
34693 + /* Init data and Clock to output lines */
34694 + /* Set Data high */
34695 + I2C_DATA_OUT(IoC);
34696 + I2C_DATA_HIGH(IoC);
34697 + /* Set Clock high */
34698 + I2C_CLK_HIGH(IoC);
34700 + SkDgWaitTime(IoC, NS2BCLK(T_START_SETUP));
34702 + /* Set Data Low */
34703 + I2C_DATA_LOW(IoC);
34705 + SkDgWaitTime(IoC, NS2BCLK(T_START_HOLD));
34707 + /* Clock low without Data to Input */
34708 + I2C_START_COND(IoC);
34710 + SkDgWaitTime(IoC, NS2BCLK(T_CLK_LOW));
34711 +} /* SkI2cStart */
34715 +SK_IOC IoC) /* I/O Context */
34717 + /* Init data and Clock to output lines */
34718 + /* Set Data low */
34719 + I2C_DATA_OUT(IoC);
34720 + I2C_DATA_LOW(IoC);
34722 + SkDgWaitTime(IoC, NS2BCLK(T_CLK_2_DATA_OUT));
34724 + /* Set Clock high */
34725 + I2C_CLK_HIGH(IoC);
34727 + SkDgWaitTime(IoC, NS2BCLK(T_STOP_SETUP));
34730 + * Set Data High: Do it by setting the Data Line to Input.
34731 + * Because of a pull up resistor the Data Line
34732 + * floods to high.
34734 + I2C_DATA_IN(IoC);
34737 + * When TWSI activity is stopped
34738 + * o DATA should be set to input and
34739 + * o CLOCK should be set to high!
34741 + SkDgWaitTime(IoC, NS2BCLK(T_BUS_IDLE));
34746 + * Receive just one bit via the TWSI bus.
34748 + * Note: Clock must be set to LOW before calling this function.
34750 + * Returns The received bit.
34753 +SK_IOC IoC) /* I/O Context */
34758 + /* Init data as input line */
34759 + I2C_DATA_IN(IoC);
34761 + SkDgWaitTime(IoC, NS2BCLK(T_CLK_2_DATA_OUT));
34763 + I2C_CLK_HIGH(IoC);
34765 + SkDgWaitTime(IoC, NS2BCLK(T_CLK_HIGH));
34767 + SK_I2C_GET_SW(IoC, &I2cSwCtrl);
34769 + Bit = (I2cSwCtrl & I2C_DATA) ? 1 : 0;
34771 + I2C_CLK_LOW(IoC);
34772 + SkDgWaitTime(IoC, NS2BCLK(T_CLK_LOW-T_CLK_2_DATA_OUT));
34775 +} /* SkI2cRcvBit */
34779 + * Receive an ACK.
34781 + * returns 0 If acknowledged
34782 + * 1 in case of an error
34785 +SK_IOC IoC) /* I/O Context */
34788 + * Received bit must be zero.
34790 + return(SkI2cRcvBit(IoC) != 0);
34791 +} /* SkI2cRcvAck */
34797 +void SkI2cSndNAck(
34798 +SK_IOC IoC) /* I/O Context */
34801 + * Received bit must be zero.
34803 + SkI2cSndBit(IoC, 1);
34804 +} /* SkI2cSndNAck */
34811 +SK_IOC IoC) /* I/O Context */
34814 + * Received bit must be zero.
34816 + SkI2cSndBit(IoC, 0);
34817 +} /* SkI2cSndAck */
34821 + * Send one byte to the TWSI device and wait for ACK.
34823 + * Return acknowleged status.
34826 +SK_IOC IoC, /* I/O Context */
34827 +int Byte) /* byte to send */
34831 + for (i = 0; i < 8; i++) {
34832 + if (Byte & (1<<(7-i))) {
34833 + SkI2cSndBit(IoC, 1);
34836 + SkI2cSndBit(IoC, 0);
34840 + return(SkI2cRcvAck(IoC));
34841 +} /* SkI2cSndByte */
34845 + * Receive one byte and ack it.
34850 +SK_IOC IoC, /* I/O Context */
34851 +int Last) /* Last Byte Flag */
34856 + for (i = 0; i < 8; i++) {
34858 + Byte |= SkI2cRcvBit(IoC);
34862 + SkI2cSndNAck(IoC);
34865 + SkI2cSndAck(IoC);
34869 +} /* SkI2cRcvByte */
34873 + * Start dialog and send device address
34875 + * Return 0 if acknowleged, 1 in case of an error
34878 +SK_IOC IoC, /* I/O Context */
34879 +int Addr, /* Device Address */
34880 +int Rw) /* Read / Write Flag */
34885 + return(SkI2cSndByte(IoC, (Addr << 1) | Rw));
34886 +} /* SkI2cSndDev */
34888 +#endif /* SK_DIAG */
34890 +/*----------------- TWSI CTRL Register Functions ----------*/
34893 + * waits for a completion of a TWSI transfer
34895 + * returns 0: success, transfer completes
34896 + * 1: error, transfer does not complete, TWSI transfer
34897 + * killed, wait loop terminated.
34900 +SK_AC *pAC, /* Adapter Context */
34901 +SK_IOC IoC, /* I/O Context */
34902 +int Event) /* complete event to wait for (I2C_READ or I2C_WRITE) */
34904 + SK_U64 StartTime;
34905 + SK_U64 CurrentTime;
34908 + StartTime = SkOsGetTime(pAC);
34911 + CurrentTime = SkOsGetTime(pAC);
34913 + if (CurrentTime - StartTime > SK_TICKS_PER_SEC / 8) {
34915 + SK_I2C_STOP(IoC);
34917 + if (pAC->I2c.InitLevel > SK_INIT_DATA) {
34918 + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E002, SKERR_I2C_E002MSG);
34920 +#endif /* !SK_DIAG */
34924 + SK_I2C_GET_CTL(IoC, &I2cCtrl);
34927 + printf("StartTime=%lu, CurrentTime=%lu\n",
34928 + StartTime, CurrentTime);
34932 +#endif /* YUKON_DBG */
34934 + } while ((I2cCtrl & I2C_FLAG) == (SK_U32)Event << 31);
34941 + * waits for a completion of a TWSI transfer
34946 +void SkI2cWaitIrq(
34947 +SK_AC *pAC, /* Adapter Context */
34948 +SK_IOC IoC) /* I/O Context */
34951 + SK_U64 StartTime;
34953 + SK_U32 IsTwsiReadyBit;
34955 + pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
34957 + if (pSen->SenState == SK_SEN_IDLE) {
34961 + IsTwsiReadyBit = CHIP_ID_YUKON_2(pAC) ? Y2_IS_TWSI_RDY : IS_I2C_READY;
34963 + StartTime = SkOsGetTime(pAC);
34966 + if (SkOsGetTime(pAC) - StartTime > SK_TICKS_PER_SEC / 8) {
34968 + SK_I2C_STOP(IoC);
34970 + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E016, SKERR_I2C_E016MSG);
34971 +#endif /* !SK_DIAG */
34975 + SK_IN32(IoC, B0_ISRC, &IrqSrc);
34977 + } while ((IrqSrc & IsTwsiReadyBit) == 0);
34979 + pSen->SenState = SK_SEN_IDLE;
34981 +} /* SkI2cWaitIrq */
34984 + * writes a single byte or 4 bytes into the TWSI device
34986 + * returns 0: success
34990 +SK_AC *pAC, /* Adapter Context */
34991 +SK_IOC IoC, /* I/O Context */
34992 +SK_U32 I2cData, /* TWSI Data to write */
34993 +int I2cDev, /* TWSI Device Address */
34994 +int I2cDevSize, /* TWSI Device Size (e.g. I2C_025K_DEV or I2C_2K_DEV) */
34995 +int I2cReg, /* TWSI Device Register Address */
34996 +int I2cBurst) /* TWSI Burst Flag */
34998 + SK_OUT32(IoC, B2_I2C_DATA, I2cData);
35000 + SK_I2C_CTL(IoC, I2C_WRITE, I2cDev, I2cDevSize, I2cReg, I2cBurst);
35002 + return(SkI2cWait(pAC, IoC, I2C_WRITE));
35008 + * reads a single byte or 4 bytes from the TWSI device
35010 + * returns the word read
35013 +SK_AC *pAC, /* Adapter Context */
35014 +SK_IOC IoC, /* I/O Context */
35015 +int I2cDev, /* TWSI Device Address */
35016 +int I2cDevSize, /* TWSI Device Size (e.g. I2C_025K_DEV or I2C_2K_DEV) */
35017 +int I2cReg, /* TWSI Device Register Address */
35018 +int I2cBurst) /* TWSI Burst Flag */
35022 + SK_OUT32(IoC, B2_I2C_DATA, 0);
35024 + SK_I2C_CTL(IoC, I2C_READ, I2cDev, I2cDevSize, I2cReg, I2cBurst);
35026 + if (SkI2cWait(pAC, IoC, I2C_READ) != 0) {
35027 + w_print("%s\n", SKERR_I2C_E002MSG);
35030 + SK_IN32(IoC, B2_I2C_DATA, &Data);
35034 +#endif /* SK_DIAG */
35038 + * read a sensor's value
35040 + * This function reads a sensor's value from the TWSI sensor chip. The sensor
35041 + * is defined by its index into the sensors database in the struct pAC points
35044 + * 1 if the read is completed
35045 + * 0 if the read must be continued (TWSI Bus still allocated)
35047 +int SkI2cReadSensor(
35048 +SK_AC *pAC, /* Adapter Context */
35049 +SK_IOC IoC, /* I/O Context */
35050 +SK_SENSOR *pSen) /* Sensor to be read */
35052 + if (pSen->SenRead != NULL) {
35053 + return((*pSen->SenRead)(pAC, IoC, pSen));
35056 + return(0); /* no success */
35057 +} /* SkI2cReadSensor */
35060 + * Do the Init state 0 initialization
35062 +static int SkI2cInit0(
35063 +SK_AC *pAC) /* Adapter Context */
35068 + /* Begin with first sensor */
35069 + pAC->I2c.CurrSens = 0;
35071 + /* Begin with timeout control for state machine */
35072 + pAC->I2c.TimerMode = SK_TIMER_WATCH_SM;
35074 + /* Set sensor number to zero */
35075 + pAC->I2c.MaxSens = 0;
35078 + /* Initialize Number of Dummy Reads */
35079 + pAC->I2c.DummyReads = SK_MAX_SENSORS;
35080 +#endif /* !SK_DIAG */
35082 + for (i = 0; i < SK_MAX_SENSORS; i++) {
35083 + pSen = &pAC->I2c.SenTable[i];
35085 + pSen->SenDesc = "unknown";
35086 + pSen->SenType = SK_SEN_UNKNOWN;
35087 + pSen->SenThreErrHigh = 0;
35088 + pSen->SenThreErrLow = 0;
35089 + pSen->SenThreWarnHigh = 0;
35090 + pSen->SenThreWarnLow = 0;
35091 + pSen->SenReg = LM80_FAN2_IN;
35092 + pSen->SenInit = SK_SEN_DYN_INIT_NONE;
35093 + pSen->SenValue = 0;
35094 + pSen->SenErrFlag = SK_SEN_ERR_NOT_PRESENT;
35095 + pSen->SenErrCts = 0;
35096 + pSen->SenBegErrTS = 0;
35097 + pSen->SenState = SK_SEN_IDLE;
35098 + pSen->SenRead = NULL;
35099 + pSen->SenDev = 0;
35102 + /* Now we are "INIT data"ed */
35103 + pAC->I2c.InitLevel = SK_INIT_DATA;
35109 + * Do the init state 1 initialization
35111 + * initialize the following register of the LM80:
35112 + * Configuration register:
35113 + * - START, noINT, activeLOW, noINT#Clear, noRESET, noCI, noGPO#, noINIT
35115 + * Interrupt Mask Register 1:
35116 + * - all interrupts are Disabled (0xff)
35118 + * Interrupt Mask Register 2:
35119 + * - all interrupts are Disabled (0xff) Interrupt modi doesn't matter.
35121 + * Fan Divisor/RST_OUT register:
35122 + * - Divisors set to 1 (bits 00), all others 0s.
35124 + * OS# Configuration/Temperature resolution Register:
35128 +static int SkI2cInit1(
35129 +SK_AC *pAC, /* Adapter Context */
35130 +SK_IOC IoC) /* I/O Context */
35134 + SK_GEPORT *pPrt; /* GIni Port struct pointer */
35137 + if (pAC->I2c.InitLevel != SK_INIT_DATA) {
35138 + /* Re-init not needed in TWSI module */
35142 + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC ||
35143 + pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) {
35144 + /* No sensors on Yukon-EC and Yukon-FE */
35148 + /* Set the Direction of TWSI-Data Pin to IN */
35149 + SK_I2C_CLR_BIT(IoC, I2C_DATA_DIR | I2C_DATA);
35151 + /* Check for 32-Bit Yukon with Low at TWSI-Data Pin */
35152 + SK_I2C_GET_SW(IoC, &I2cSwCtrl);
35154 + if ((I2cSwCtrl & I2C_DATA) == 0) {
35155 + /* this is a 32-Bit board */
35156 + pAC->GIni.GIYukon32Bit = SK_TRUE;
35160 + /* Check for 64 Bit Yukon without sensors */
35161 + if (SkI2cWrite(pAC, IoC, 0, LM80_ADDR, I2C_025K_DEV, LM80_CFG, 0) != 0) {
35165 + (void)SkI2cWrite(pAC, IoC, 0xffUL, LM80_ADDR, I2C_025K_DEV, LM80_IMSK_1, 0);
35167 + (void)SkI2cWrite(pAC, IoC, 0xffUL, LM80_ADDR, I2C_025K_DEV, LM80_IMSK_2, 0);
35169 + (void)SkI2cWrite(pAC, IoC, 0, LM80_ADDR, I2C_025K_DEV, LM80_FAN_CTRL, 0);
35171 + (void)SkI2cWrite(pAC, IoC, 0, LM80_ADDR, I2C_025K_DEV, LM80_TEMP_CTRL, 0);
35173 + (void)SkI2cWrite(pAC, IoC, (SK_U32)LM80_CFG_START, LM80_ADDR, I2C_025K_DEV,
35177 + * MaxSens has to be updated here, because PhyType is not
35178 + * set when performing Init Level 0
35180 + pAC->I2c.MaxSens = 5;
35182 + pPrt = &pAC->GIni.GP[0];
35184 + if (pAC->GIni.GIGenesis) {
35185 + if (pPrt->PhyType == SK_PHY_BCOM) {
35186 + if (pAC->GIni.GIMacsFound == 1) {
35187 + pAC->I2c.MaxSens += 1;
35190 + pAC->I2c.MaxSens += 3;
35195 + pAC->I2c.MaxSens += 3;
35198 + for (i = 0; i < pAC->I2c.MaxSens; i++) {
35199 + pSen = &pAC->I2c.SenTable[i];
35202 + pSen->SenDesc = "Temperature";
35203 + pSen->SenType = SK_SEN_TEMP;
35204 + pSen->SenThreErrHigh = SK_SEN_TEMP_HIGH_ERR;
35205 + pSen->SenThreWarnHigh = SK_SEN_TEMP_HIGH_WARN;
35206 + pSen->SenThreWarnLow = SK_SEN_TEMP_LOW_WARN;
35207 + pSen->SenThreErrLow = SK_SEN_TEMP_LOW_ERR;
35208 + pSen->SenReg = LM80_TEMP_IN;
35211 + pSen->SenDesc = "Voltage PCI";
35212 + pSen->SenType = SK_SEN_VOLT;
35213 + pSen->SenThreErrHigh = SK_SEN_PCI_5V_HIGH_ERR;
35214 + pSen->SenThreWarnHigh = SK_SEN_PCI_5V_HIGH_WARN;
35215 + if (pAC->GIni.GIPciBus != SK_PEX_BUS) {
35216 + pSen->SenThreWarnLow = SK_SEN_PCI_5V_LOW_WARN;
35217 + pSen->SenThreErrLow = SK_SEN_PCI_5V_LOW_ERR;
35220 + pSen->SenThreWarnLow = 0;
35221 + pSen->SenThreErrLow = 0;
35223 + pSen->SenReg = LM80_VT0_IN;
35226 + pSen->SenDesc = "Voltage PCI-IO";
35227 + pSen->SenType = SK_SEN_VOLT;
35228 + pSen->SenThreErrHigh = SK_SEN_PCI_IO_5V_HIGH_ERR;
35229 + pSen->SenThreWarnHigh = SK_SEN_PCI_IO_5V_HIGH_WARN;
35230 + if (pAC->GIni.GIPciBus != SK_PEX_BUS) {
35231 + pSen->SenThreWarnLow = SK_SEN_PCI_IO_3V3_LOW_WARN;
35232 + pSen->SenThreErrLow = SK_SEN_PCI_IO_3V3_LOW_ERR;
35235 + pSen->SenThreWarnLow = 0;
35236 + pSen->SenThreErrLow = 0;
35238 + pSen->SenReg = LM80_VT1_IN;
35239 + pSen->SenInit = SK_SEN_DYN_INIT_PCI_IO;
35242 + if (pAC->GIni.GIGenesis) {
35243 + pSen->SenDesc = "Voltage ASIC";
35246 + pSen->SenDesc = "Voltage VMAIN";
35248 + pSen->SenType = SK_SEN_VOLT;
35249 + pSen->SenThreErrHigh = SK_SEN_VDD_HIGH_ERR;
35250 + pSen->SenThreWarnHigh = SK_SEN_VDD_HIGH_WARN;
35251 + pSen->SenThreWarnLow = SK_SEN_VDD_LOW_WARN;
35252 + pSen->SenThreErrLow = SK_SEN_VDD_LOW_ERR;
35253 + pSen->SenReg = LM80_VT2_IN;
35256 + if (pAC->GIni.GIGenesis) {
35257 + if (pPrt->PhyType == SK_PHY_BCOM) {
35258 + pSen->SenDesc = "Voltage PHY A PLL";
35259 + pSen->SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR;
35260 + pSen->SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN;
35261 + pSen->SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN;
35262 + pSen->SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR;
35265 + pSen->SenDesc = "Voltage PMA";
35266 + pSen->SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR;
35267 + pSen->SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN;
35268 + pSen->SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN;
35269 + pSen->SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR;
35273 + pSen->SenDesc = "Voltage VAUX";
35274 + pSen->SenThreErrHigh = SK_SEN_VAUX_3V3_HIGH_ERR;
35275 + pSen->SenThreWarnHigh = SK_SEN_VAUX_3V3_HIGH_WARN;
35276 + if (pAC->GIni.GIVauxAvail) {
35277 + pSen->SenThreWarnLow = SK_SEN_VAUX_3V3_LOW_WARN;
35278 + pSen->SenThreErrLow = SK_SEN_VAUX_3V3_LOW_ERR;
35281 + pSen->SenThreErrLow = 0;
35282 + pSen->SenThreWarnLow = 0;
35285 + pSen->SenType = SK_SEN_VOLT;
35286 + pSen->SenReg = LM80_VT3_IN;
35289 + if (CHIP_ID_YUKON_2(pAC)) {
35290 + if (pAC->GIni.GIChipRev == CHIP_REV_YU_XL_A0) {
35291 + pSen->SenDesc = "Voltage Core 1V3";
35292 + pSen->SenThreErrHigh = SK_SEN_CORE_1V3_HIGH_ERR;
35293 + pSen->SenThreWarnHigh = SK_SEN_CORE_1V3_HIGH_WARN;
35294 + pSen->SenThreWarnLow = SK_SEN_CORE_1V3_LOW_WARN;
35295 + pSen->SenThreErrLow = SK_SEN_CORE_1V3_LOW_ERR;
35298 + pSen->SenDesc = "Voltage Core 1V2";
35299 + pSen->SenThreErrHigh = SK_SEN_CORE_1V2_HIGH_ERR;
35300 + pSen->SenThreWarnHigh = SK_SEN_CORE_1V2_HIGH_WARN;
35301 + pSen->SenThreWarnLow = SK_SEN_CORE_1V2_LOW_WARN;
35302 + pSen->SenThreErrLow = SK_SEN_CORE_1V2_LOW_ERR;
35306 + if (pAC->GIni.GIGenesis) {
35307 + pSen->SenDesc = "Voltage PHY 2V5";
35308 + pSen->SenThreErrHigh = SK_SEN_PHY_2V5_HIGH_ERR;
35309 + pSen->SenThreWarnHigh = SK_SEN_PHY_2V5_HIGH_WARN;
35310 + pSen->SenThreWarnLow = SK_SEN_PHY_2V5_LOW_WARN;
35311 + pSen->SenThreErrLow = SK_SEN_PHY_2V5_LOW_ERR;
35314 + pSen->SenDesc = "Voltage Core 1V5";
35315 + pSen->SenThreErrHigh = SK_SEN_CORE_1V5_HIGH_ERR;
35316 + pSen->SenThreWarnHigh = SK_SEN_CORE_1V5_HIGH_WARN;
35317 + pSen->SenThreWarnLow = SK_SEN_CORE_1V5_LOW_WARN;
35318 + pSen->SenThreErrLow = SK_SEN_CORE_1V5_LOW_ERR;
35321 + pSen->SenType = SK_SEN_VOLT;
35322 + pSen->SenReg = LM80_VT4_IN;
35325 + if (CHIP_ID_YUKON_2(pAC)) {
35326 + pSen->SenDesc = "Voltage PHY 1V5";
35327 + pSen->SenThreErrHigh = SK_SEN_CORE_1V5_HIGH_ERR;
35328 + pSen->SenThreWarnHigh = SK_SEN_CORE_1V5_HIGH_WARN;
35329 + if (pAC->GIni.GIPciBus == SK_PEX_BUS) {
35330 + pSen->SenThreWarnLow = SK_SEN_CORE_1V5_LOW_WARN;
35331 + pSen->SenThreErrLow = SK_SEN_CORE_1V5_LOW_ERR;
35334 + pSen->SenThreWarnLow = 0;
35335 + pSen->SenThreErrLow = 0;
35339 + if (pAC->GIni.GIGenesis) {
35340 + pSen->SenDesc = "Voltage PHY B PLL";
35343 + pSen->SenDesc = "Voltage PHY 3V3";
35345 + pSen->SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR;
35346 + pSen->SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN;
35347 + pSen->SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN;
35348 + pSen->SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR;
35350 + pSen->SenType = SK_SEN_VOLT;
35351 + pSen->SenReg = LM80_VT5_IN;
35354 + if (pAC->GIni.GIGenesis) {
35355 + pSen->SenDesc = "Speed Fan";
35356 + pSen->SenType = SK_SEN_FAN;
35357 + pSen->SenThreErrHigh = SK_SEN_FAN_HIGH_ERR;
35358 + pSen->SenThreWarnHigh = SK_SEN_FAN_HIGH_WARN;
35359 + pSen->SenThreWarnLow = SK_SEN_FAN_LOW_WARN;
35360 + pSen->SenThreErrLow = SK_SEN_FAN_LOW_ERR;
35361 + pSen->SenReg = LM80_FAN2_IN;
35364 + pSen->SenDesc = "Voltage PHY 2V5";
35365 + pSen->SenType = SK_SEN_VOLT;
35366 + pSen->SenThreErrHigh = SK_SEN_PHY_2V5_HIGH_ERR;
35367 + pSen->SenThreWarnHigh = SK_SEN_PHY_2V5_HIGH_WARN;
35368 + pSen->SenThreWarnLow = SK_SEN_PHY_2V5_LOW_WARN;
35369 + pSen->SenThreErrLow = SK_SEN_PHY_2V5_LOW_ERR;
35370 + pSen->SenReg = LM80_VT6_IN;
35374 + SK_ERR_LOG(pAC, SK_ERRCL_INIT | SK_ERRCL_SW,
35375 + SKERR_I2C_E001, SKERR_I2C_E001MSG);
35379 + pSen->SenValue = 0;
35380 + pSen->SenErrFlag = SK_SEN_ERR_OK;
35381 + pSen->SenErrCts = 0;
35382 + pSen->SenBegErrTS = 0;
35383 + pSen->SenState = SK_SEN_IDLE;
35384 + if (pSen->SenThreWarnLow != 0) {
35385 + pSen->SenRead = SkLm80ReadSensor;
35387 + pSen->SenDev = LM80_ADDR;
35391 + pAC->I2c.DummyReads = pAC->I2c.MaxSens;
35392 +#endif /* !SK_DIAG */
35394 + /* Clear TWSI IRQ */
35395 + SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
35397 + /* Now we are I/O initialized */
35398 + pAC->I2c.InitLevel = SK_INIT_IO;
35400 +} /* SkI2cInit1 */
35404 + * Init level 2: Start first sensor read.
35406 +static int SkI2cInit2(
35407 +SK_AC *pAC, /* Adapter Context */
35408 +SK_IOC IoC) /* I/O Context */
35410 + int ReadComplete;
35413 + if (pAC->I2c.InitLevel != SK_INIT_IO) {
35414 + /* ReInit not needed in TWSI module */
35415 + /* Init0 and Init2 not permitted */
35419 + pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
35421 + ReadComplete = SkI2cReadSensor(pAC, IoC, pSen);
35423 + if (ReadComplete) {
35424 + SK_ERR_LOG(pAC, SK_ERRCL_INIT, SKERR_I2C_E008, SKERR_I2C_E008MSG);
35427 + /* Now we are correctly initialized */
35428 + pAC->I2c.InitLevel = SK_INIT_RUN;
35435 + * Initialize TWSI devices
35437 + * Get the first voltage value and discard it.
35438 + * Go into temperature read mode. A default pointer is not set.
35440 + * The things to be done depend on the init level in the parameter list:
35442 + * Initialize only the data structures. Do NOT access hardware.
35444 + * Initialize hardware through SK_IN / SK_OUT commands. Do NOT use interrupts.
35446 + * Everything is possible. Interrupts may be used from now on.
35453 +SK_AC *pAC, /* Adapter Context */
35454 +SK_IOC IoC, /* I/O Context needed in levels 1 and 2 */
35455 +int Level) /* Init Level */
35459 + case SK_INIT_DATA:
35460 + return(SkI2cInit0(pAC));
35462 + return(SkI2cInit1(pAC, IoC));
35463 + case SK_INIT_RUN:
35464 + return(SkI2cInit2(pAC, IoC));
35475 + * Interrupt service function for the TWSI Interface
35477 + * Clears the Interrupt source
35479 + * Reads the register and check it for sending a trap.
35481 + * Starts the timer if necessary.
35484 +SK_AC *pAC, /* Adapter Context */
35485 +SK_IOC IoC) /* I/O Context */
35489 + /* Clear TWSI IRQ */
35490 + SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
35493 + SkEventQueue(pAC, SKGE_I2C, SK_I2CEV_IRQ, Para);
35498 + * Check this sensors Value against the threshold and send events.
35500 +static void SkI2cCheckSensor(
35501 +SK_AC *pAC, /* Adapter Context */
35504 + SK_EVPARA ParaLocal;
35505 + SK_BOOL TooHigh; /* Is sensor too high? */
35506 + SK_BOOL TooLow; /* Is sensor too low? */
35507 + SK_U64 CurrTime; /* Current Time */
35508 + SK_BOOL DoTrapSend; /* We need to send a trap */
35509 + SK_BOOL DoErrLog; /* We need to log the error */
35510 + SK_BOOL IsError; /* Error occured */
35512 + /* Check Dummy Reads first */
35513 + if (pAC->I2c.DummyReads > 0) {
35514 + pAC->I2c.DummyReads--;
35518 + /* Get the current time */
35519 + CurrTime = SkOsGetTime(pAC);
35521 + /* Set para to the most useful setting: The current sensor. */
35522 + ParaLocal.Para64 = (SK_U64)pAC->I2c.CurrSens;
35524 + /* Check the Value against the thresholds. First: Error Thresholds */
35525 + TooHigh = pSen->SenValue > pSen->SenThreErrHigh;
35526 + TooLow = pSen->SenValue < pSen->SenThreErrLow;
35528 + IsError = SK_FALSE;
35530 + if (TooHigh || TooLow) {
35531 + /* Error condition is satisfied */
35532 + DoTrapSend = SK_TRUE;
35533 + DoErrLog = SK_TRUE;
35535 + /* Now error condition is satisfied */
35536 + IsError = SK_TRUE;
35538 + if (pSen->SenErrFlag == SK_SEN_ERR_ERR) {
35539 + /* This state is the former one */
35541 + /* So check first whether we have to send a trap */
35542 + if (pSen->SenLastErrTrapTS + SK_SEN_ERR_TR_HOLD > CurrTime) {
35544 + * Do NOT send the Trap. The hold back time
35545 + * has to run out first.
35547 + DoTrapSend = SK_FALSE;
35550 + /* Check now whether we have to log an Error */
35551 + if (pSen->SenLastErrLogTS + SK_SEN_ERR_LOG_HOLD > CurrTime) {
35553 + * Do NOT log the error. The hold back time
35554 + * has to run out first.
35556 + DoErrLog = SK_FALSE;
35560 + /* We came from a different state -> Set Begin Time Stamp */
35561 + pSen->SenBegErrTS = CurrTime;
35562 + pSen->SenErrFlag = SK_SEN_ERR_ERR;
35565 + if (DoTrapSend) {
35566 + /* Set current Time */
35567 + pSen->SenLastErrTrapTS = CurrTime;
35568 + pSen->SenErrCts++;
35570 + /* Queue PNMI Event */
35571 + SkEventQueue(pAC, SKGE_PNMI, TooHigh ?
35572 + SK_PNMI_EVT_SEN_ERR_UPP : SK_PNMI_EVT_SEN_ERR_LOW,
35577 + /* Set current Time */
35578 + pSen->SenLastErrLogTS = CurrTime;
35580 + if (pSen->SenType == SK_SEN_TEMP) {
35581 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E011, SKERR_I2C_E011MSG);
35583 + else if (pSen->SenType == SK_SEN_VOLT) {
35584 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E012, SKERR_I2C_E012MSG);
35587 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E015, SKERR_I2C_E015MSG);
35592 + /* Check the Value against the thresholds */
35593 + /* 2nd: Warning thresholds */
35594 + TooHigh = pSen->SenValue > pSen->SenThreWarnHigh;
35595 + TooLow = pSen->SenValue < pSen->SenThreWarnLow;
35597 + if (!IsError && (TooHigh || TooLow)) {
35598 + /* Error condition is satisfied */
35599 + DoTrapSend = SK_TRUE;
35600 + DoErrLog = SK_TRUE;
35602 + if (pSen->SenErrFlag == SK_SEN_ERR_WARN) {
35603 + /* This state is the former one */
35605 + /* So check first whether we have to send a trap */
35606 + if (pSen->SenLastWarnTrapTS + SK_SEN_WARN_TR_HOLD > CurrTime) {
35608 + * Do NOT send the Trap. The hold back time
35609 + * has to run out first.
35611 + DoTrapSend = SK_FALSE;
35614 + /* Check now whether we have to log an Error */
35615 + if (pSen->SenLastWarnLogTS + SK_SEN_WARN_LOG_HOLD > CurrTime) {
35617 + * Do NOT log the error. The hold back time
35618 + * has to run out first.
35620 + DoErrLog = SK_FALSE;
35624 + /* We came from a different state -> Set Begin Time Stamp */
35625 + pSen->SenBegWarnTS = CurrTime;
35626 + pSen->SenErrFlag = SK_SEN_ERR_WARN;
35629 + if (DoTrapSend) {
35630 + /* Set current Time */
35631 + pSen->SenLastWarnTrapTS = CurrTime;
35632 + pSen->SenWarnCts++;
35634 + /* Queue PNMI Event */
35635 + SkEventQueue(pAC, SKGE_PNMI, TooHigh ?
35636 + SK_PNMI_EVT_SEN_WAR_UPP : SK_PNMI_EVT_SEN_WAR_LOW, ParaLocal);
35640 + /* Set current Time */
35641 + pSen->SenLastWarnLogTS = CurrTime;
35643 + if (pSen->SenType == SK_SEN_TEMP) {
35644 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E009, SKERR_I2C_E009MSG);
35646 + else if (pSen->SenType == SK_SEN_VOLT) {
35647 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E010, SKERR_I2C_E010MSG);
35650 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E014, SKERR_I2C_E014MSG);
35655 + /* Check for NO error at all */
35656 + if (!IsError && !TooHigh && !TooLow) {
35657 + /* Set o.k. Status if no error and no warning condition */
35658 + pSen->SenErrFlag = SK_SEN_ERR_OK;
35661 + /* End of check against the thresholds */
35663 + if (pSen->SenInit == SK_SEN_DYN_INIT_PCI_IO) {
35664 + /* Bug fix AF: 16.Aug.2001: Correct the init base of LM80 sensor */
35665 + pSen->SenInit = SK_SEN_DYN_INIT_NONE;
35667 + if (pSen->SenValue > SK_SEN_PCI_IO_RANGE_LIMITER) {
35668 + /* 5V PCI-IO Voltage */
35669 + pSen->SenThreWarnLow = SK_SEN_PCI_IO_5V_LOW_WARN;
35670 + pSen->SenThreErrLow = SK_SEN_PCI_IO_5V_LOW_ERR;
35673 + /* 3.3V PCI-IO Voltage */
35674 + pSen->SenThreWarnHigh = SK_SEN_PCI_IO_3V3_HIGH_WARN;
35675 + pSen->SenThreErrHigh = SK_SEN_PCI_IO_3V3_HIGH_ERR;
35680 + /* Dynamic thresholds also for VAUX of LM80 sensor */
35681 + if (pSen->SenInit == SK_SEN_DYN_INIT_VAUX) {
35683 + pSen->SenInit = SK_SEN_DYN_INIT_NONE;
35685 + /* 3.3V VAUX Voltage */
35686 + if (pSen->SenValue > SK_SEN_VAUX_RANGE_LIMITER) {
35687 + pSen->SenThreWarnLow = SK_SEN_VAUX_3V3_LOW_WARN;
35688 + pSen->SenThreErrLow = SK_SEN_VAUX_3V3_LOW_ERR;
35690 + /* 0V VAUX Voltage */
35692 + pSen->SenThreWarnHigh = SK_SEN_VAUX_0V_WARN_ERR;
35693 + pSen->SenThreErrHigh = SK_SEN_VAUX_0V_WARN_ERR;
35697 + /* Check initialization state: the VIO Thresholds need adaption */
35698 + if (!pSen->SenInit && pSen->SenReg == LM80_VT1_IN &&
35699 + pSen->SenValue > SK_SEN_WARNLOW2C &&
35700 + pSen->SenValue < SK_SEN_WARNHIGH2) {
35702 + pSen->SenThreErrLow = SK_SEN_ERRLOW2C;
35703 + pSen->SenThreWarnLow = SK_SEN_WARNLOW2C;
35704 + pSen->SenInit = SK_TRUE;
35707 + if (!pSen->SenInit && pSen->SenReg == LM80_VT1_IN &&
35708 + pSen->SenValue > SK_SEN_WARNLOW2 &&
35709 + pSen->SenValue < SK_SEN_WARNHIGH2C) {
35711 + pSen->SenThreErrHigh = SK_SEN_ERRHIGH2C;
35712 + pSen->SenThreWarnHigh = SK_SEN_WARNHIGH2C;
35713 + pSen->SenInit = SK_TRUE;
35717 + if (pSen->SenInit != SK_SEN_DYN_INIT_NONE) {
35718 + SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E013, SKERR_I2C_E013MSG);
35720 +} /* SkI2cCheckSensor */
35724 + * The only Event to be served is the timeout event
35728 +SK_AC *pAC, /* Adapter Context */
35729 +SK_IOC IoC, /* I/O Context */
35730 +SK_U32 Event, /* Module specific Event */
35731 +SK_EVPARA Para) /* Event specific Parameter */
35733 + int ReadComplete;
35736 + SK_EVPARA ParaLocal;
35739 + /* New case: no sensors */
35740 + if (pAC->I2c.MaxSens == 0) {
35745 + case SK_I2CEV_IRQ:
35746 + pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
35747 + ReadComplete = SkI2cReadSensor(pAC, IoC, pSen);
35749 + if (ReadComplete) {
35750 + /* Check sensor against defined thresholds */
35751 + SkI2cCheckSensor(pAC, pSen);
35753 + /* Increment Current sensor and set appropriate Timeout */
35754 + pAC->I2c.CurrSens++;
35755 + if (pAC->I2c.CurrSens >= pAC->I2c.MaxSens) {
35756 + pAC->I2c.CurrSens = 0;
35757 + Time = SK_I2C_TIM_LONG;
35760 + Time = SK_I2C_TIM_SHORT;
35763 + /* Start Timer */
35764 + ParaLocal.Para64 = (SK_U64)0;
35766 + pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING;
35768 + SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time,
35769 + SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
35772 + /* Start Timer */
35773 + ParaLocal.Para64 = (SK_U64)0;
35775 + pAC->I2c.TimerMode = SK_TIMER_WATCH_SM;
35777 + SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, SK_I2C_TIM_WATCH,
35778 + SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
35781 + case SK_I2CEV_TIM:
35782 + if (pAC->I2c.TimerMode == SK_TIMER_NEW_GAUGING) {
35784 + ParaLocal.Para64 = (SK_U64)0;
35785 + SkTimerStop(pAC, IoC, &pAC->I2c.SenTimer);
35787 + pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
35788 + ReadComplete = SkI2cReadSensor(pAC, IoC, pSen);
35790 + if (ReadComplete) {
35791 + /* Check sensor against defined thresholds */
35792 + SkI2cCheckSensor(pAC, pSen);
35794 + /* Increment Current sensor and set appropriate Timeout */
35795 + pAC->I2c.CurrSens++;
35796 + if (pAC->I2c.CurrSens == pAC->I2c.MaxSens) {
35797 + pAC->I2c.CurrSens = 0;
35798 + Time = SK_I2C_TIM_LONG;
35801 + Time = SK_I2C_TIM_SHORT;
35804 + /* Start Timer */
35805 + ParaLocal.Para64 = (SK_U64)0;
35807 + pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING;
35809 + SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time,
35810 + SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
35814 + pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
35815 + pSen->SenErrFlag = SK_SEN_ERR_FAULTY;
35816 + SK_I2C_STOP(IoC);
35818 + /* Increment Current sensor and set appropriate Timeout */
35819 + pAC->I2c.CurrSens++;
35820 + if (pAC->I2c.CurrSens == pAC->I2c.MaxSens) {
35821 + pAC->I2c.CurrSens = 0;
35822 + Time = SK_I2C_TIM_LONG;
35825 + Time = SK_I2C_TIM_SHORT;
35828 + /* Start Timer */
35829 + ParaLocal.Para64 = (SK_U64)0;
35831 + pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING;
35833 + SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time,
35834 + SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
35837 + case SK_I2CEV_CLEAR:
35838 + for (i = 0; i < SK_MAX_SENSORS; i++) {
35839 + pSen = &pAC->I2c.SenTable[i];
35841 + pSen->SenErrFlag = SK_SEN_ERR_OK;
35842 + pSen->SenErrCts = 0;
35843 + pSen->SenWarnCts = 0;
35844 + pSen->SenBegErrTS = 0;
35845 + pSen->SenBegWarnTS = 0;
35846 + pSen->SenLastErrTrapTS = (SK_U64)0;
35847 + pSen->SenLastErrLogTS = (SK_U64)0;
35848 + pSen->SenLastWarnTrapTS = (SK_U64)0;
35849 + pSen->SenLastWarnLogTS = (SK_U64)0;
35853 + SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E006, SKERR_I2C_E006MSG);
35859 +#endif /* !SK_DIAG */
35861 diff -ruN linux/drivers/net/sk98lin/skvpd.c linux-new/drivers/net/sk98lin/skvpd.c
35862 --- linux/drivers/net/sk98lin/skvpd.c 2006-09-20 05:42:06.000000000 +0200
35863 +++ linux-new/drivers/net/sk98lin/skvpd.c 2006-07-28 14:13:54.000000000 +0200
35865 /******************************************************************************
35868 - * Project: GEnesis, PCI Gigabit Ethernet Adapter
35869 - * Version: $Revision$
35871 - * Purpose: Shared software to read and write VPD data
35872 + * Project: Gigabit Ethernet Adapters, VPD-Module
35873 + * Version: $Revision$
35875 + * Purpose: Shared software to read and write VPD
35877 ******************************************************************************/
35879 /******************************************************************************
35881 - * (C)Copyright 1998-2003 SysKonnect GmbH.
35883 + * (C)Copyright 1998-2002 SysKonnect.
35884 + * (C)Copyright 2002-2005 Marvell.
35886 * This program is free software; you can redistribute it and/or modify
35887 * it under the terms of the GNU General Public License as published by
35888 * the Free Software Foundation; either version 2 of the License, or
35889 * (at your option) any later version.
35891 * The information in this file is provided "AS IS" without warranty.
35894 ******************************************************************************/
35897 Please refer skvpd.txt for information how to include this module
35899 static const char SysKonnectFileId[] =
35900 - "@(#)$Id$ (C) SK";
35901 + "@(#) $Id$ (C) Marvell.";
35903 #include "h/skdrv1st.h"
35904 #include "h/sktypes.h"
35905 @@ -52,18 +54,23 @@
35906 * error exit(9) with a error message
35908 static int VpdWait(
35909 -SK_AC *pAC, /* Adapters context */
35910 +SK_AC *pAC, /* Adapters Context */
35911 SK_IOC IoC, /* IO Context */
35912 int event) /* event to wait for (VPD_READ / VPD_write) completion*/
35914 - SK_U64 start_time;
35915 + SK_I64 start_time;
35916 + SK_I64 curr_time;
35919 - SK_DBG_MSG(pAC,SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
35920 - ("VPD wait for %s\n", event?"Write":"Read"));
35921 - start_time = SkOsGetTime(pAC);
35922 + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
35923 + ("VPD wait for %s\n", event ? "Write" : "Read"));
35925 + start_time = (SK_I64)SkOsGetTime(pAC);
35928 - if (SkOsGetTime(pAC) - start_time > SK_TICKS_PER_SEC) {
35929 + curr_time = (SK_I64)SkOsGetTime(pAC);
35931 + if (curr_time - start_time > SK_TICKS_PER_SEC) {
35933 /* Bug fix AF: Thu Mar 28 2002
35934 * Do not call: VPD_STOP(pAC, IoC);
35935 @@ -81,18 +88,19 @@
35936 ("ERROR:VPD wait timeout\n"));
35941 VPD_IN16(pAC, IoC, PCI_VPD_ADR_REG, &state);
35944 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
35945 - ("state = %x, event %x\n",state,event));
35946 - } while((int)(state & PCI_VPD_FLAG) == event);
35947 + ("state = %x, event %x\n", state, event));
35949 + } while ((int)(state & PCI_VPD_FLAG) == event);
35958 * Read the dword at address 'addr' from the VPD EEPROM.
35960 @@ -104,7 +112,7 @@
35961 * Returns the data read.
35963 SK_U32 VpdReadDWord(
35964 -SK_AC *pAC, /* Adapters context */
35965 +SK_AC *pAC, /* Adapters Context */
35966 SK_IOC IoC, /* IO Context */
35967 int addr) /* VPD address */
35969 @@ -112,7 +120,7 @@
35971 /* start VPD read */
35972 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
35973 - ("VPD read dword at 0x%x\n",addr));
35974 + ("VPD read dword at 0x%x\n", addr));
35975 addr &= ~VPD_WRITE; /* ensure the R/W bit is set to read */
35977 VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, (SK_U16)addr);
35978 @@ -124,14 +132,73 @@
35981 VPD_IN32(pAC, IoC, PCI_VPD_DAT_REG, &Rtv);
35984 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
35985 - ("VPD read dword data = 0x%x\n",Rtv));
35986 + ("VPD read dword data = 0x%x\n", Rtv));
35989 +#endif /* SK_DIAG */
35994 + Write the dword 'data' at address 'addr' into the VPD EEPROM, and
35995 + verify that the data is written.
36000 +. -------------------------------------------------------------------
36001 +. write 1.8 ms 3.6 ms
36002 +. internal write cyles 0.7 ms 7.0 ms
36003 +. -------------------------------------------------------------------
36004 +. over all program time 2.5 ms 10.6 ms
36005 +. read 1.3 ms 2.6 ms
36006 +. -------------------------------------------------------------------
36007 +. over all 3.8 ms 13.2 ms
36010 + Returns 0: success
36011 + 1: error, I2C transfer does not terminate
36012 + 2: error, data verify error
36015 +static int VpdWriteDWord(
36016 +SK_AC *pAC, /* Adapters Context */
36017 +SK_IOC IoC, /* IO Context */
36018 +int addr, /* VPD address */
36019 +SK_U32 data) /* VPD data to write */
36021 + /* start VPD write */
36022 + /* Don't swap here, it's a data stream of bytes */
36023 + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
36024 + ("VPD write dword at addr 0x%x, data = 0x%x\n", addr, data));
36025 + VPD_OUT32(pAC, IoC, PCI_VPD_DAT_REG, (SK_U32)data);
36026 + /* But do it here */
36027 + addr |= VPD_WRITE;
36029 + VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, (SK_U16)(addr | VPD_WRITE));
36031 + /* this may take up to 10,6 ms */
36032 + if (VpdWait(pAC, IoC, VPD_WRITE)) {
36033 + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36034 + ("Write Timed Out\n"));
36038 + /* verify data */
36039 + if (VpdReadDWord(pAC, IoC, addr) != data) {
36040 + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
36041 + ("Data Verify Error\n"));
36045 +} /* VpdWriteDWord */
36047 -#endif /* SKDIAG */
36053 * Read one Stream of 'len' bytes of VPD data, starting at 'addr' from
36054 * or to the I2C EEPROM.
36055 @@ -139,7 +206,7 @@
36056 * Returns number of bytes read / written.
36058 static int VpdWriteStream(
36059 -SK_AC *pAC, /* Adapters context */
36060 +SK_AC *pAC, /* Adapters Context */
36061 SK_IOC IoC, /* IO Context */
36062 char *buf, /* data buffer */
36063 int Addr, /* VPD start address */
36064 @@ -156,7 +223,7 @@
36065 pComp = (SK_U8 *) buf;
36067 for (i = 0; i < Len; i++, buf++) {
36068 - if ((i%sizeof(SK_U32)) == 0) {
36069 + if ((i % SZ_LONG) == 0) {
36071 * At the begin of each cycle read the Data Reg
36072 * So it is initialized even if only a few bytes
36073 @@ -174,14 +241,13 @@
36077 - /* Write current Byte */
36078 - VPD_OUT8(pAC, IoC, PCI_VPD_DAT_REG + (i%sizeof(SK_U32)),
36080 + /* Write current byte */
36081 + VPD_OUT8(pAC, IoC, PCI_VPD_DAT_REG + (i % SZ_LONG), *(SK_U8 *)buf);
36083 - if (((i%sizeof(SK_U32)) == 3) || (i == (Len - 1))) {
36084 + if (((i % SZ_LONG) == 3) || (i == (Len - 1))) {
36085 /* New Address needs to be written to VPD_ADDR reg */
36086 AdrReg = (SK_U16) Addr;
36087 - Addr += sizeof(SK_U32);
36089 AdrReg |= VPD_WRITE; /* WRITE operation */
36091 VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, AdrReg);
36092 @@ -191,7 +257,7 @@
36094 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36095 ("Write Timed Out\n"));
36096 - return(i - (i%sizeof(SK_U32)));
36097 + return(i - (i % SZ_LONG));
36101 @@ -206,18 +272,18 @@
36103 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36104 ("Verify Timed Out\n"));
36105 - return(i - (i%sizeof(SK_U32)));
36106 + return(i - (i % SZ_LONG));
36109 - for (j = 0; j <= (int)(i%sizeof(SK_U32)); j++, pComp++) {
36111 + for (j = 0; j <= (int)(i % SZ_LONG); j++, pComp++) {
36113 VPD_IN8(pAC, IoC, PCI_VPD_DAT_REG + j, &Data);
36116 if (Data != *pComp) {
36118 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36119 ("WriteStream Verify Error\n"));
36120 - return(i - (i%sizeof(SK_U32)) + j);
36121 + return(i - (i % SZ_LONG) + j);
36125 @@ -225,7 +291,7 @@
36130 +#endif /* !SK_SLIM */
36133 * Read one Stream of 'len' bytes of VPD data, starting at 'addr' from
36134 @@ -234,7 +300,7 @@
36135 * Returns number of bytes read / written.
36137 static int VpdReadStream(
36138 -SK_AC *pAC, /* Adapters context */
36139 +SK_AC *pAC, /* Adapters Context */
36140 SK_IOC IoC, /* IO Context */
36141 char *buf, /* data buffer */
36142 int Addr, /* VPD start address */
36143 @@ -245,10 +311,10 @@
36146 for (i = 0; i < Len; i++, buf++) {
36147 - if ((i%sizeof(SK_U32)) == 0) {
36148 + if ((i % SZ_LONG) == 0) {
36149 /* New Address needs to be written to VPD_ADDR reg */
36150 AdrReg = (SK_U16) Addr;
36151 - Addr += sizeof(SK_U32);
36153 AdrReg &= ~VPD_WRITE; /* READ operation */
36155 VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, AdrReg);
36156 @@ -259,13 +325,13 @@
36160 - VPD_IN8(pAC, IoC, PCI_VPD_DAT_REG + (i%sizeof(SK_U32)),
36162 + VPD_IN8(pAC, IoC, PCI_VPD_DAT_REG + (i % SZ_LONG), (SK_U8 *)buf);
36170 * Read ore writes 'len' bytes of VPD data, starting at 'addr' from
36171 * or to the I2C EEPROM.
36172 @@ -273,7 +339,7 @@
36173 * Returns number of bytes read / written.
36175 static int VpdTransferBlock(
36176 -SK_AC *pAC, /* Adapters context */
36177 +SK_AC *pAC, /* Adapters Context */
36178 SK_IOC IoC, /* IO Context */
36179 char *buf, /* data buffer */
36180 int addr, /* VPD start address */
36181 @@ -287,18 +353,19 @@
36182 ("VPD %s block, addr = 0x%x, len = %d\n",
36183 dir ? "write" : "read", addr, len));
36190 vpd_rom_size = pAC->vpd.rom_size;
36193 if (addr > vpd_rom_size - 4) {
36194 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
36195 ("Address error: 0x%x, exp. < 0x%x\n",
36196 addr, vpd_rom_size - 4));
36201 if (addr + len > vpd_rom_size) {
36202 len = vpd_rom_size - addr;
36203 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36204 @@ -308,22 +375,24 @@
36205 if (dir == VPD_READ) {
36206 Rtv = VpdReadStream(pAC, IoC, buf, addr, len);
36210 Rtv = VpdWriteStream(pAC, IoC, buf, addr, len);
36212 +#endif /* !SK_SLIM */
36219 +#if defined(SK_DIAG) || defined(SK_ASF)
36221 * Read 'len' bytes of VPD data, starting at 'addr'.
36223 * Returns number of bytes read.
36226 -SK_AC *pAC, /* pAC pointer */
36227 +SK_AC *pAC, /* Adapters Context */
36228 SK_IOC IoC, /* IO Context */
36229 char *buf, /* buffer were the data should be stored */
36230 int addr, /* start reading at the VPD address */
36231 @@ -332,13 +401,14 @@
36232 return(VpdTransferBlock(pAC, IoC, buf, addr, len, VPD_READ));
36237 * Write 'len' bytes of *but to the VPD EEPROM, starting at 'addr'.
36239 * Returns number of bytes writes.
36242 -SK_AC *pAC, /* pAC pointer */
36243 +SK_AC *pAC, /* Adapters Context */
36244 SK_IOC IoC, /* IO Context */
36245 char *buf, /* buffer, holds the data to write */
36246 int addr, /* start writing at the VPD address */
36247 @@ -346,19 +416,28 @@
36249 return(VpdTransferBlock(pAC, IoC, buf, addr, len, VPD_WRITE));
36251 -#endif /* SKDIAG */
36252 +#endif /* SK_DIAG || SK_ASF */
36255 - * (re)initialize the VPD buffer
36257 +/******************************************************************************
36259 - * Reads the VPD data from the EEPROM into the VPD buffer.
36260 - * Get the remaining read only and read / write space.
36261 + * VpdInit() - (re)initialize the VPD buffer
36263 - * return 0: success
36264 - * 1: fatal VPD error
36266 + * Reads the VPD data from the EEPROM into the VPD buffer.
36267 + * Get the remaining read only and read / write space.
36270 + * This is a local function and should be used locally only.
36271 + * However, the ASF module needs to use this function also.
36272 + * Therfore it has been published.
36276 + * 1: fatal VPD error
36278 -static int VpdInit(
36279 -SK_AC *pAC, /* Adapters context */
36281 +SK_AC *pAC, /* Adapters Context */
36282 SK_IOC IoC) /* IO Context */
36284 SK_VPD_PARA *r, rp; /* RW or RV */
36285 @@ -368,14 +447,14 @@
36289 - SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_INIT, ("VpdInit .. "));
36291 + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_INIT, ("VpdInit ... "));
36293 VPD_IN16(pAC, IoC, PCI_DEVICE_ID, &dev_id);
36296 VPD_IN32(pAC, IoC, PCI_OUR_REG_2, &our_reg2);
36299 pAC->vpd.rom_size = 256 << ((our_reg2 & PCI_VPD_ROM_SZ) >> 14);
36303 * this function might get used before the hardware is initialized
36304 * therefore we cannot always trust in GIChipId
36305 @@ -388,6 +467,7 @@
36306 /* for Yukon the VPD size is always 256 */
36307 vpd_size = VPD_SIZE_YUKON;
36311 /* Genesis uses the maximum ROM size up to 512 for VPD */
36312 if (pAC->vpd.rom_size > VPD_SIZE_GENESIS) {
36313 @@ -397,6 +477,7 @@
36314 vpd_size = pAC->vpd.rom_size;
36317 +#endif /* !SK_SLIM */
36319 /* read the VPD data into the VPD buffer */
36320 if (VpdTransferBlock(pAC, IoC, pAC->vpd.vpd_buf, 0, vpd_size, VPD_READ)
36321 @@ -406,19 +487,17 @@
36322 ("Block Read Error\n"));
36327 pAC->vpd.vpd_size = vpd_size;
36330 /* Asus K8V Se Deluxe bugfix. Correct VPD content */
36331 - /* MBo April 2004 */
36332 - if (((unsigned char)pAC->vpd.vpd_buf[0x3f] == 0x38) &&
36333 - ((unsigned char)pAC->vpd.vpd_buf[0x40] == 0x3c) &&
36334 - ((unsigned char)pAC->vpd.vpd_buf[0x41] == 0x45)) {
36335 - printk("sk98lin: Asus mainboard with buggy VPD? "
36336 - "Correcting data.\n");
36337 - pAC->vpd.vpd_buf[0x40] = 0x38;
36340 + if (!SK_STRNCMP(pAC->vpd.vpd_buf + i, " 8<E", 4)) {
36342 + pAC->vpd.vpd_buf[i + 2] = '8';
36344 +#endif /* !SK_SLIM */
36346 /* find the end tag of the RO area */
36347 if (!(r = vpd_find_para(pAC, VPD_RV, &rp))) {
36348 @@ -426,9 +505,9 @@
36349 ("Encoding Error: RV Tag not found\n"));
36354 if (r->p_val + r->p_len > pAC->vpd.vpd_buf + vpd_size/2) {
36355 - SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
36356 + SK_DBG_MSG(pAC, SK_DBGMOD_VPD,SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
36357 ("Encoding Error: Invalid VPD struct size\n"));
36360 @@ -438,7 +517,7 @@
36361 for (i = 0, x = 0; (unsigned)i <= (unsigned)vpd_size/2 - r->p_len; i++) {
36362 x += pAC->vpd.vpd_buf[i];
36367 /* checksum error */
36368 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
36369 @@ -452,7 +531,7 @@
36370 ("Encoding Error: RV Tag not found\n"));
36375 if (r->p_val < pAC->vpd.vpd_buf + vpd_size/2) {
36376 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
36377 ("Encoding Error: Invalid VPD struct size\n"));
36378 @@ -472,6 +551,7 @@
36384 * find the Keyword 'key' in the VPD buffer and fills the
36385 * parameter struct 'p' with it's values
36386 @@ -480,58 +560,63 @@
36387 * 0: parameter was not found or VPD encoding error
36389 static SK_VPD_PARA *vpd_find_para(
36390 -SK_AC *pAC, /* common data base */
36391 +SK_AC *pAC, /* Adapters Context */
36392 const char *key, /* keyword to find (e.g. "MN") */
36393 -SK_VPD_PARA *p) /* parameter description struct */
36394 +SK_VPD_PARA *p) /* parameter description struct */
36396 char *v ; /* points to VPD buffer */
36397 int max; /* Maximum Number of Iterations */
36400 v = pAC->vpd.vpd_buf;
36403 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
36404 - ("VPD find para %s .. ",key));
36405 + ("VPD find para %s .. ", key));
36407 /* check mandatory resource type ID string (Product Name) */
36408 if (*v != (char)RES_ID) {
36409 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
36410 ("Error: 0x%x missing\n", RES_ID));
36415 - if (strcmp(key, VPD_NAME) == 0) {
36416 - p->p_len = VPD_GET_RES_LEN(v);
36417 + len = VPD_GET_RES_LEN(v);
36419 + if (SK_STRCMP(key, VPD_NAME) == 0) {
36421 p->p_val = VPD_GET_VAL(v);
36422 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
36423 - ("found, len = %d\n", p->p_len));
36424 + ("found, len = %d\n", len));
36428 - v += 3 + VPD_GET_RES_LEN(v) + 3;
36430 - if (SK_MEMCMP(key,v,2) == 0) {
36431 + v += 3 + len + 3;
36434 + if (SK_MEMCMP(key, v, 2) == 0) {
36435 p->p_len = VPD_GET_VPD_LEN(v);
36436 p->p_val = VPD_GET_VAL(v);
36437 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
36438 - ("found, len = %d\n",p->p_len));
36439 + ("found, len = %d\n", p->p_len));
36443 /* exit when reaching the "RW" Tag or the maximum of itera. */
36445 - if (SK_MEMCMP(VPD_RW,v,2) == 0 || max == 0) {
36446 + if (SK_MEMCMP(VPD_RW, v, 2) == 0 || max == 0) {
36450 - if (SK_MEMCMP(VPD_RV,v,2) == 0) {
36451 - v += 3 + VPD_GET_VPD_LEN(v) + 3; /* skip VPD-W */
36454 - v += 3 + VPD_GET_VPD_LEN(v);
36455 + len = 3 + VPD_GET_VPD_LEN(v);
36457 + if (SK_MEMCMP(VPD_RV, v, 2) == 0) {
36458 + len += 3; /* skip VPD-W */
36462 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
36463 - ("scanning '%c%c' len = %d\n",v[0],v[1],v[2]));
36464 + ("scanning '%c%c' len = %d\n", v[0], v[1], v[2]));
36468 @@ -541,9 +626,10 @@
36469 ("Key/Len Encoding error\n"));
36478 * Move 'n' bytes. Begin with the last byte if 'n' is > 0,
36479 * Start with the last byte if n is < 0.
36480 @@ -558,8 +644,9 @@
36482 int i; /* number of byte copied */
36489 i = (int) (end - start + 1);
36491 @@ -578,6 +665,7 @@
36497 * setup the VPD keyword 'key' at 'ip'.
36499 @@ -594,10 +682,11 @@
36500 p = (SK_VPD_KEY *) ip;
36501 p->p_key[0] = key[0];
36502 p->p_key[1] = key[1];
36503 - p->p_len = (unsigned char) len;
36504 - SK_MEMCPY(&p->p_val,buf,len);
36505 + p->p_len = (unsigned char)len;
36506 + SK_MEMCPY(&p->p_val, buf, len);
36511 * Setup the VPD end tag "RV" / "RW".
36512 * Also correct the remaining space variables vpd_free_ro / vpd_free_rw.
36513 @@ -606,7 +695,7 @@
36514 * 1: encoding error
36516 static int vpd_mod_endtag(
36517 -SK_AC *pAC, /* common data base */
36518 +SK_AC *pAC, /* Adapters Context */
36519 char *etp) /* end pointer input position */
36522 @@ -615,7 +704,7 @@
36525 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
36526 - ("VPD modify endtag at 0x%x = '%c%c'\n",etp,etp[0],etp[1]));
36527 + ("VPD modify endtag at 0x%x = '%c%c'\n", etp, etp[0], etp[1]));
36529 vpd_size = pAC->vpd.vpd_size;
36531 @@ -623,7 +712,7 @@
36533 if (p->p_key[0] != 'R' || (p->p_key[1] != 'V' && p->p_key[1] != 'W')) {
36534 /* something wrong here, encoding error */
36535 - SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
36536 + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
36537 ("Encoding Error: invalid end tag\n"));
36540 @@ -655,6 +744,7 @@
36546 * Insert a VPD keyword into the VPD buffer.
36548 @@ -669,8 +759,8 @@
36549 * 6: fatal VPD error
36552 -static int VpdSetupPara(
36553 -SK_AC *pAC, /* common data base */
36555 +SK_AC *pAC, /* Adapters Context */
36556 const char *key, /* keyword to insert */
36557 const char *buf, /* buffer with the keyword value */
36558 int len, /* length of the keyword value */
36559 @@ -687,12 +777,12 @@
36562 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
36563 - ("VPD setup para key = %s, val = %s\n",key,buf));
36565 + ("VPD setup para key = %s, val = %s\n", key, buf));
36567 vpd_size = pAC->vpd.vpd_size;
36572 if (type == VPD_RW_KEY) {
36573 /* end tag is "RW" */
36574 free = pAC->vpd.v.vpd_free_rw;
36575 @@ -743,7 +833,9 @@
36578 vpd_move_para(ip + vp.p_len + found, etp+2, len-vp.p_len+head);
36580 vpd_insert_key(key, buf, len, ip);
36582 if (vpd_mod_endtag(pAC, etp + len - vp.p_len + head)) {
36583 pAC->vpd.v.vpd_status &= ~VPD_VALID;
36584 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36585 @@ -754,7 +846,7 @@
36592 * Read the contents of the VPD EEPROM and copy it to the
36593 * VPD buffer if not already done.
36594 @@ -763,7 +855,7 @@
36597 SK_VPD_STATUS *VpdStat(
36598 -SK_AC *pAC, /* Adapters context */
36599 +SK_AC *pAC, /* Adapters Context */
36600 SK_IOC IoC) /* IO Context */
36602 if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) {
36603 @@ -780,13 +872,14 @@
36604 * keyword list by copying the keywords to 'buf', all after
36605 * each other and terminated with a '\0'.
36607 - * Exceptions: o The Resource Type ID String (product name) is called "Name"
36609 + * o The Resource Type ID String (product name) is called "Name"
36610 * o The VPD end tags 'RV' and 'RW' are not listed
36612 * The number of copied keywords is counted in 'elements'.
36614 * returns 0: success
36615 - * 2: buffer overfull, one or more keywords are missing
36616 + * 2: buffer overflow, one or more keywords are missing
36617 * 6: fatal VPD error
36619 * example values after returning:
36620 @@ -796,7 +889,7 @@
36624 -SK_AC *pAC, /* common data base */
36625 +SK_AC *pAC, /* Adapters Context */
36626 SK_IOC IoC, /* IO Context */
36627 char *buf, /* buffer where to copy the keywords */
36628 int *len, /* buffer length */
36629 @@ -806,6 +899,7 @@
36632 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX, ("list VPD keys .. "));
36635 if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) {
36636 if (VpdInit(pAC, IoC) != 0) {
36637 @@ -816,43 +910,44 @@
36641 - if ((signed)strlen(VPD_NAME) + 1 <= *len) {
36642 + if ((signed)SK_STRLEN(VPD_NAME) + 1 <= *len) {
36643 v = pAC->vpd.vpd_buf;
36644 - strcpy(buf,VPD_NAME);
36645 - n = strlen(VPD_NAME) + 1;
36646 + SK_STRCPY(buf, VPD_NAME);
36647 + n = SK_STRLEN(VPD_NAME) + 1;
36650 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX,
36651 - ("'%c%c' ",v[0],v[1]));
36652 + ("'%c%c' ", v[0], v[1]));
36656 - SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR,
36657 + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36658 ("buffer overflow\n"));
36662 v += 3 + VPD_GET_RES_LEN(v) + 3;
36666 /* exit when reaching the "RW" Tag */
36667 - if (SK_MEMCMP(VPD_RW,v,2) == 0) {
36668 + if (SK_MEMCMP(VPD_RW, v, 2) == 0) {
36672 - if (SK_MEMCMP(VPD_RV,v,2) == 0) {
36673 + if (SK_MEMCMP(VPD_RV, v, 2) == 0) {
36674 v += 3 + VPD_GET_VPD_LEN(v) + 3; /* skip VPD-W */
36678 - if (n+3 <= *len) {
36679 - SK_MEMCPY(buf,v,2);
36680 + if (n + 3 <= *len) {
36681 + SK_MEMCPY(buf, v, 2);
36685 v += 3 + VPD_GET_VPD_LEN(v);
36687 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX,
36688 - ("'%c%c' ",v[0],v[1]));
36689 + ("'%c%c' ", v[0], v[1]));
36693 @@ -867,6 +962,7 @@
36697 +#endif /* !SK_SLIM */
36700 * Read the contents of the VPD EEPROM and copy it to the
36701 @@ -882,7 +978,7 @@
36702 * 6: fatal VPD error
36705 -SK_AC *pAC, /* common data base */
36706 +SK_AC *pAC, /* Adapters Context */
36707 SK_IOC IoC, /* IO Context */
36708 const char *key, /* keyword to read (e.g. "MN") */
36709 char *buf, /* buffer where to copy the keyword value */
36710 @@ -891,6 +987,7 @@
36711 SK_VPD_PARA *p, vp;
36713 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX, ("VPD read %s .. ", key));
36715 if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) {
36716 if (VpdInit(pAC, IoC) != 0) {
36718 @@ -901,7 +998,7 @@
36721 if ((p = vpd_find_para(pAC, key, &vp)) != NULL) {
36722 - if (p->p_len > (*(unsigned *)len)-1) {
36723 + if (p->p_len > (*(unsigned *)len) - 1) {
36724 p->p_len = *len - 1;
36726 SK_MEMCPY(buf, p->p_val, p->p_len);
36727 @@ -909,7 +1006,7 @@
36729 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX,
36730 ("%c%c%c%c.., len = %d\n",
36731 - buf[0],buf[1],buf[2],buf[3],*len));
36732 + buf[0], buf[1], buf[2], buf[3], *len));
36736 @@ -919,7 +1016,7 @@
36743 * Check whether a given key may be written
36745 @@ -932,12 +1029,13 @@
36747 if ((*key != 'Y' && *key != 'V') ||
36748 key[1] < '0' || key[1] > 'Z' ||
36749 - (key[1] > '9' && key[1] < 'A') || strlen(key) != 2) {
36750 + (key[1] > '9' && key[1] < 'A') || SK_STRLEN(key) != 2) {
36756 +#endif /* !SK_SLIM */
36759 * Read the contents of the VPD EEPROM and copy it to the VPD
36760 @@ -953,7 +1051,7 @@
36761 * 6: fatal VPD error
36764 -SK_AC *pAC, /* common data base */
36765 +SK_AC *pAC, /* Adapters Context */
36766 SK_IOC IoC, /* IO Context */
36767 const char *key, /* keyword to write (allowed values "Yx", "Vx") */
36768 const char *buf) /* buffer where the keyword value can be read from */
36769 @@ -963,11 +1061,11 @@
36772 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX,
36773 - ("VPD write %s = %s\n",key,buf));
36774 + ("VPD write %s = %s\n", key, buf));
36776 if ((*key != 'Y' && *key != 'V') ||
36777 key[1] < '0' || key[1] > 'Z' ||
36778 - (key[1] > '9' && key[1] < 'A') || strlen(key) != 2) {
36779 + (key[1] > '9' && key[1] < 'A') || SK_STRLEN(key) != 2) {
36781 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36782 ("illegal key tag, keyword not written\n"));
36783 @@ -983,13 +1081,13 @@
36787 - len = strlen(buf);
36788 + len = SK_STRLEN(buf);
36789 if (len > VPD_MAX_LEN) {
36793 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36794 - ("keyword too long, cut after %d bytes\n",VPD_MAX_LEN));
36795 + ("keyword too long, cut after %d bytes\n", VPD_MAX_LEN));
36797 if ((rtv2 = VpdSetupPara(pAC, key, buf, len, VPD_RW_KEY, OWR_KEY)) != 0) {
36798 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36799 @@ -1000,6 +1098,7 @@
36805 * Read the contents of the VPD EEPROM and copy it to the
36806 * VPD buffer if not already done. Remove the VPD keyword
36807 @@ -1013,7 +1112,7 @@
36808 * 6: fatal VPD error
36811 -SK_AC *pAC, /* common data base */
36812 +SK_AC *pAC, /* Adapters Context */
36813 SK_IOC IoC, /* IO Context */
36814 char *key) /* keyword to read (e.g. "MN") */
36816 @@ -1023,7 +1122,7 @@
36818 vpd_size = pAC->vpd.vpd_size;
36820 - SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_TX,("VPD delete key %s\n",key));
36821 + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX, ("VPD delete key %s\n", key));
36822 if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) {
36823 if (VpdInit(pAC, IoC) != 0) {
36824 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36825 @@ -1042,7 +1141,7 @@
36827 etp = pAC->vpd.vpd_buf + (vpd_size-pAC->vpd.v.vpd_free_rw-1-3);
36829 - vpd_move_para(vp.p_val+vp.p_len, etp+2,
36830 + vpd_move_para(vp.p_val + vp.p_len, etp + 2,
36831 - ((int)(vp.p_len + 3)));
36832 if (vpd_mod_endtag(pAC, etp - vp.p_len - 3)) {
36833 pAC->vpd.v.vpd_status &= ~VPD_VALID;
36834 @@ -1059,6 +1158,7 @@
36838 +#endif /* !SK_SLIM */
36841 * If the VPD buffer contains valid data write the VPD
36842 @@ -1068,7 +1168,7 @@
36843 * 3: VPD transfer timeout
36846 -SK_AC *pAC, /* Adapters context */
36847 +SK_AC *pAC, /* Adapters Context */
36848 SK_IOC IoC) /* IO Context */
36851 @@ -1089,3 +1189,51 @@
36857 + * Read the contents of the VPD EEPROM and copy it to the VPD buffer
36858 + * if not already done. If the keyword "VF" is not present it will be
36859 + * created and the error log message will be stored to this keyword.
36860 + * If "VF" is not present the error log message will be stored to the
36861 + * keyword "VL". "VL" will created or overwritten if "VF" is present.
36862 + * The VPD read/write area is saved to the VPD EEPROM.
36864 + * returns nothing, errors will be ignored.
36867 +SK_AC *pAC, /* Adapters Context */
36868 +SK_IOC IoC, /* IO Context */
36869 +char *msg) /* error log message */
36871 + SK_VPD_PARA *v, vf; /* VF */
36874 + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX,
36875 + ("VPD error log msg %s\n", msg));
36877 + if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) {
36878 + if (VpdInit(pAC, IoC) != 0) {
36879 + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36880 + ("VPD init error\n"));
36885 + len = SK_STRLEN(msg);
36886 + if (len > VPD_MAX_LEN) {
36888 + len = VPD_MAX_LEN;
36890 + if ((v = vpd_find_para(pAC, VPD_VF, &vf)) != NULL) {
36891 + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX, ("overwrite VL\n"));
36892 + (void)VpdSetupPara(pAC, VPD_VL, msg, len, VPD_RW_KEY, OWR_KEY);
36895 + SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX, ("write VF\n"));
36896 + (void)VpdSetupPara(pAC, VPD_VF, msg, len, VPD_RW_KEY, ADD_KEY);
36899 + (void)VpdUpdate(pAC, IoC);
36901 +#endif /* !SK_SLIM */
36903 diff -ruN linux/drivers/net/sk98lin/skxmac2.c linux-new/drivers/net/sk98lin/skxmac2.c
36904 --- linux/drivers/net/sk98lin/skxmac2.c 2006-09-20 05:42:06.000000000 +0200
36905 +++ linux-new/drivers/net/sk98lin/skxmac2.c 2006-07-28 14:13:54.000000000 +0200
36909 * Project: Gigabit Ethernet Adapters, Common Modules
36910 - * Version: $Revision$
36912 + * Version: $Revision$
36914 * Purpose: Contains functions to initialize the MACs and PHYs
36916 ******************************************************************************/
36918 /******************************************************************************
36921 * (C)Copyright 1998-2002 SysKonnect.
36922 - * (C)Copyright 2002-2003 Marvell.
36923 + * (C)Copyright 2002-2006 Marvell.
36925 * This program is free software; you can redistribute it and/or modify
36926 * it under the terms of the GNU General Public License as published by
36927 * the Free Software Foundation; either version 2 of the License, or
36928 * (at your option) any later version.
36930 * The information in this file is provided "AS IS" without warranty.
36933 ******************************************************************************/
36937 /* BCOM PHY magic pattern list */
36938 typedef struct s_PhyHack {
36939 - int PhyReg; /* Phy register */
36940 + int PhyReg; /* PHY register */
36941 SK_U16 PhyVal; /* Value to write */
36944 @@ -37,17 +38,17 @@
36946 #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
36947 static const char SysKonnectFileId[] =
36948 - "@(#) $Id$ (C) Marvell.";
36949 + "@(#) $Id$ (C) Marvell.";
36953 -static BCOM_HACK BcomRegA1Hack[] = {
36954 +BCOM_HACK BcomRegA1Hack[] = {
36955 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
36956 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
36957 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
36960 -static BCOM_HACK BcomRegC0Hack[] = {
36961 +BCOM_HACK BcomRegC0Hack[] = {
36962 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 }, { 0x17, 0x0013 },
36963 { 0x15, 0x0A04 }, { 0x18, 0x0420 },
36971 SK_AC *pAC, /* Adapter Context */
36972 SK_IOC IoC, /* I/O Context */
36973 int Port, /* Port Index (MAC_1 + n) */
36974 @@ -94,13 +95,13 @@
36977 pPrt = &pAC->GIni.GP[Port];
36980 /* write the PHY register's address */
36981 XM_OUT16(IoC, Port, XM_PHY_ADDR, PhyReg | pPrt->PhyAddr);
36984 /* get the PHY register's value */
36985 XM_IN16(IoC, Port, XM_PHY_DATA, pVal);
36988 if (pPrt->PhyType != SK_PHY_XMAC) {
36990 XM_IN16(IoC, Port, XM_MMU_CMD, &Mmu);
36991 @@ -110,6 +111,8 @@
36992 /* get the PHY register's value */
36993 XM_IN16(IoC, Port, XM_PHY_DATA, pVal);
36997 } /* SkXmPhyRead */
37000 @@ -122,7 +125,7 @@
37004 -void SkXmPhyWrite(
37006 SK_AC *pAC, /* Adapter Context */
37007 SK_IOC IoC, /* I/O Context */
37008 int Port, /* Port Index (MAC_1 + n) */
37009 @@ -133,26 +136,28 @@
37012 pPrt = &pAC->GIni.GP[Port];
37015 if (pPrt->PhyType != SK_PHY_XMAC) {
37017 XM_IN16(IoC, Port, XM_MMU_CMD, &Mmu);
37018 /* wait until 'Busy' is cleared */
37019 } while ((Mmu & XM_MMU_PHY_BUSY) != 0);
37023 /* write the PHY register's address */
37024 XM_OUT16(IoC, Port, XM_PHY_ADDR, PhyReg | pPrt->PhyAddr);
37027 /* write the PHY register's value */
37028 XM_OUT16(IoC, Port, XM_PHY_DATA, Val);
37031 if (pPrt->PhyType != SK_PHY_XMAC) {
37033 XM_IN16(IoC, Port, XM_MMU_CMD, &Mmu);
37034 /* wait until 'Busy' is cleared */
37035 } while ((Mmu & XM_MMU_PHY_BUSY) != 0);
37039 } /* SkXmPhyWrite */
37040 #endif /* GENESIS */
37042 @@ -165,63 +170,97 @@
37043 * Description: reads a 16-bit word from GPHY through MDIO
37048 + * 1 error during MDIO read
37053 SK_AC *pAC, /* Adapter Context */
37054 SK_IOC IoC, /* I/O Context */
37055 int Port, /* Port Index (MAC_1 + n) */
37056 int PhyReg, /* Register Address (Offset) */
37057 SK_U16 SK_FAR *pVal) /* Pointer to Value */
37064 - u_long SimLowTime;
37066 - VCPUgetTime(&SimCyle, &SimLowTime);
37067 - VCPUprintf(0, "SkGmPhyRead(%u), SimCyle=%u, SimLowTime=%u\n",
37068 - PhyReg, SimCyle, SimLowTime);
37071 + SK_U32 StartTime;
37081 pPrt = &pAC->GIni.GP[Port];
37084 /* set PHY-Register offset and 'Read' OpCode (= 1) */
37085 - *pVal = (SK_U16)(GM_SMI_CT_PHY_AD(pPrt->PhyAddr) |
37086 + Word = (SK_U16)(GM_SMI_CT_PHY_AD(pPrt->PhyAddr) |
37087 GM_SMI_CT_REG_AD(PhyReg) | GM_SMI_CT_OP_RD);
37089 - GM_OUT16(IoC, Port, GM_SMI_CTRL, *pVal);
37090 + GM_OUT16(IoC, Port, GM_SMI_CTRL, Word);
37092 - GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);
37094 /* additional check for MDC/MDIO activity */
37095 - if ((Ctrl & GM_SMI_CT_BUSY) == 0) {
37098 + GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);
37100 + if (Ctrl == 0xffff || (Ctrl & GM_SMI_CT_OP_RD) == 0) {
37102 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
37103 + ("PHY read impossible on Port %d (Ctrl=0x%04x)\n", Port, Ctrl));
37108 - *pVal |= GM_SMI_CT_BUSY;
37111 + Word |= GM_SMI_CT_BUSY;
37113 + SK_IN32(IoC, GMAC_TI_ST_VAL, &StartTime);
37115 + /* set timeout to 10 ms */
37116 + TimeOut = HW_MS_TO_TICKS(pAC, 10);
37118 + do { /* wait until 'Busy' is cleared and 'ReadValid' is set */
37120 VCPUwaitTime(1000);
37123 + SK_IN32(IoC, GMAC_TI_ST_VAL, &CurrTime);
37125 + if (CurrTime >= StartTime) {
37126 + Delta = CurrTime - StartTime;
37129 + Delta = CurrTime + ~StartTime + 1;
37132 + if (Delta > TimeOut) {
37134 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
37135 + ("PHY read timeout on Port %d (Ctrl=0x%04x)\n", Port, Ctrl));
37140 GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);
37142 - /* wait until 'ReadValid' is set */
37143 - } while (Ctrl == *pVal);
37145 - /* get the PHY register's value */
37146 + /* Error on reading SMI Control Register */
37147 + if (Ctrl == 0xffff) {
37151 + } while ((Ctrl ^ Word) != (GM_SMI_CT_RD_VAL | GM_SMI_CT_BUSY));
37153 GM_IN16(IoC, Port, GM_SMI_DATA, pVal);
37156 - VCPUgetTime(&SimCyle, &SimLowTime);
37157 - VCPUprintf(0, "VCPUgetTime(), SimCyle=%u, SimLowTime=%u\n",
37158 - SimCyle, SimLowTime);
37160 + /* dummy read after GM_IN16() */
37161 + SK_IN32(IoC, GMAC_TI_ST_VAL, &CurrTime);
37163 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
37164 + ("SkGmPhyRead Port:%d, Reg=%d, Val = 0x%04X\n",
37165 + Port, PhyReg, *pVal));
37168 } /* SkGmPhyRead */
37171 @@ -232,9 +271,11 @@
37172 * Description: writes a 16-bit word to GPHY through MDIO
37177 + * 1 error during MDIO read
37180 -void SkGmPhyWrite(
37182 SK_AC *pAC, /* Adapter Context */
37183 SK_IOC IoC, /* I/O Context */
37184 int Port, /* Port Index (MAC_1 + n) */
37185 @@ -243,54 +284,78 @@
37192 - u_long SimLowTime;
37194 - VCPUgetTime(&SimCyle, &SimLowTime);
37195 - VCPUprintf(0, "SkGmPhyWrite(Reg=%u, Val=0x%04x), SimCyle=%u, SimLowTime=%u\n",
37196 - PhyReg, Val, SimCyle, SimLowTime);
37199 + SK_U32 StartTime;
37204 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
37205 + ("SkGmPhyWrite Port:%d, Reg=%d, Val = 0x%04X\n",
37206 + Port, PhyReg, Val));
37208 pPrt = &pAC->GIni.GP[Port];
37211 /* write the PHY register's value */
37212 GM_OUT16(IoC, Port, GM_SMI_DATA, Val);
37214 - /* set PHY-Register offset and 'Write' OpCode (= 0) */
37215 - Val = GM_SMI_CT_PHY_AD(pPrt->PhyAddr) | GM_SMI_CT_REG_AD(PhyReg);
37217 - GM_OUT16(IoC, Port, GM_SMI_CTRL, Val);
37219 - GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);
37222 /* additional check for MDC/MDIO activity */
37223 - if ((Ctrl & GM_SMI_CT_BUSY) == 0) {
37225 + GM_IN16(IoC, Port, GM_SMI_DATA, &Ctrl);
37227 + if (Ctrl != Val) {
37229 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
37230 + ("PHY write impossible on Port %d (Val=0x%04x)\n", Port, Ctrl));
37235 - Val |= GM_SMI_CT_BUSY;
37236 +#endif /* DEBUG */
37240 - /* read Timer value */
37241 - SK_IN32(IoC, B2_TI_VAL, &DWord);
37242 + /* set PHY-Register offset and 'Write' OpCode (= 0) */
37243 + Ctrl = (SK_U16)(GM_SMI_CT_PHY_AD(pPrt->PhyAddr) |
37244 + GM_SMI_CT_REG_AD(PhyReg));
37246 + GM_OUT16(IoC, Port, GM_SMI_CTRL, Ctrl);
37248 + SK_IN32(IoC, GMAC_TI_ST_VAL, &StartTime);
37250 + /* set timeout to 10 ms */
37251 + TimeOut = HW_MS_TO_TICKS(pAC, 10);
37253 + do { /* wait until 'Busy' is cleared */
37255 VCPUwaitTime(1000);
37258 + SK_IN32(IoC, GMAC_TI_ST_VAL, &CurrTime);
37260 + if (CurrTime >= StartTime) {
37261 + Delta = CurrTime - StartTime;
37264 + Delta = CurrTime + ~StartTime + 1;
37267 + if (Delta > TimeOut) {
37269 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
37270 + ("PHY write timeout on Port %d (Ctrl=0x%04x)\n", Port, Ctrl));
37274 GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);
37276 - /* wait until 'Busy' is cleared */
37277 - } while (Ctrl == Val);
37280 - VCPUgetTime(&SimCyle, &SimLowTime);
37281 - VCPUprintf(0, "VCPUgetTime(), SimCyle=%u, SimLowTime=%u\n",
37282 - SimCyle, SimLowTime);
37284 + /* Error on reading SMI Control Register */
37285 + if (Ctrl == 0xffff) {
37289 + } while ((Ctrl & GM_SMI_CT_BUSY) != 0);
37291 + /* dummy read after GM_IN16() */
37292 + SK_IN32(IoC, GMAC_TI_ST_VAL, &CurrTime);
37295 } /* SkGmPhyWrite */
37298 @@ -312,16 +377,8 @@
37299 int PhyReg, /* Register Address (Offset) */
37300 SK_U16 *pVal) /* Pointer to Value */
37302 - void (*r_func)(SK_AC *pAC, SK_IOC IoC, int Port, int Reg, SK_U16 *pVal);
37304 - if (pAC->GIni.GIGenesis) {
37305 - r_func = SkXmPhyRead;
37308 - r_func = SkGmPhyRead;
37311 - r_func(pAC, IoC, Port, PhyReg, pVal);
37312 + pAC->GIni.GIFunc.pFnMacPhyRead(pAC, IoC, Port, PhyReg, pVal);
37313 } /* SkGePhyRead */
37316 @@ -341,16 +398,8 @@
37317 int PhyReg, /* Register Address (Offset) */
37318 SK_U16 Val) /* Value */
37320 - void (*w_func)(SK_AC *pAC, SK_IOC IoC, int Port, int Reg, SK_U16 Val);
37322 - if (pAC->GIni.GIGenesis) {
37323 - w_func = SkXmPhyWrite;
37326 - w_func = SkGmPhyWrite;
37329 - w_func(pAC, IoC, Port, PhyReg, Val);
37330 + pAC->GIni.GIFunc.pFnMacPhyWrite(pAC, IoC, Port, PhyReg, Val);
37331 } /* SkGePhyWrite */
37332 #endif /* SK_DIAG */
37334 @@ -360,15 +409,15 @@
37335 * SkMacPromiscMode() - Enable / Disable Promiscuous Mode
37338 - * enables / disables promiscuous mode by setting Mode Register (XMAC) or
37339 - * Receive Control Register (GMAC) dep. on board type
37340 + * enables / disables promiscuous mode by setting Mode Register (XMAC) or
37341 + * Receive Control Register (GMAC) dep. on board type
37346 void SkMacPromiscMode(
37347 -SK_AC *pAC, /* adapter context */
37348 -SK_IOC IoC, /* IO context */
37349 +SK_AC *pAC, /* Adapter Context */
37350 +SK_IOC IoC, /* I/O Context */
37351 int Port, /* Port Index (MAC_1 + n) */
37352 SK_BOOL Enable) /* Enable / Disable */
37354 @@ -377,11 +426,11 @@
37362 if (pAC->GIni.GIGenesis) {
37365 XM_IN32(IoC, Port, XM_MODE, &MdReg);
37366 /* enable or disable promiscuous mode */
37368 @@ -394,12 +443,12 @@
37369 XM_OUT32(IoC, Port, XM_MODE, MdReg);
37371 #endif /* GENESIS */
37375 if (pAC->GIni.GIYukon) {
37378 GM_IN16(IoC, Port, GM_RX_CTRL, &RcReg);
37381 /* enable or disable unicast and multicast filtering */
37383 RcReg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
37384 @@ -420,28 +469,28 @@
37385 * SkMacHashing() - Enable / Disable Hashing
37388 - * enables / disables hashing by setting Mode Register (XMAC) or
37389 - * Receive Control Register (GMAC) dep. on board type
37390 + * enables / disables hashing by setting Mode Register (XMAC) or
37391 + * Receive Control Register (GMAC) dep. on board type
37397 -SK_AC *pAC, /* adapter context */
37398 -SK_IOC IoC, /* IO context */
37399 +SK_AC *pAC, /* Adapter Context */
37400 +SK_IOC IoC, /* I/O Context */
37401 int Port, /* Port Index (MAC_1 + n) */
37402 SK_BOOL Enable) /* Enable / Disable */
37413 if (pAC->GIni.GIGenesis) {
37416 XM_IN32(IoC, Port, XM_MODE, &MdReg);
37417 /* enable or disable hashing */
37419 @@ -454,12 +503,12 @@
37420 XM_OUT32(IoC, Port, XM_MODE, MdReg);
37422 #endif /* GENESIS */
37426 if (pAC->GIni.GIYukon) {
37429 GM_IN16(IoC, Port, GM_RX_CTRL, &RcReg);
37432 /* enable or disable multicast filtering */
37434 RcReg |= GM_RXCR_MCF_ENA;
37435 @@ -487,8 +536,8 @@
37436 * - don't set XMR_FS_ERR in status SK_LENERR_OK_ON/OFF
37437 * for inrange length error frames
37438 * - don't set XMR_FS_ERR in status SK_BIG_PK_OK_ON/OFF
37439 - * for frames > 1514 bytes
37440 - * - enable Rx of own packets SK_SELF_RX_ON/OFF
37441 + * for frames > 1514 bytes
37442 + * - enable Rx of own packets SK_SELF_RX_ON/OFF
37444 * for incoming packets may be enabled/disabled by this function.
37445 * Additional modes may be added later.
37446 @@ -499,11 +548,11 @@
37449 static void SkXmSetRxCmd(
37450 -SK_AC *pAC, /* adapter context */
37451 -SK_IOC IoC, /* IO context */
37452 +SK_AC *pAC, /* Adapter Context */
37453 +SK_IOC IoC, /* I/O Context */
37454 int Port, /* Port Index (MAC_1 + n) */
37455 int Mode) /* Mode is SK_STRIP_FCS_ON/OFF, SK_STRIP_PAD_ON/OFF,
37456 - SK_LENERR_OK_ON/OFF, or SK_BIG_PK_OK_ON/OFF */
37457 + SK_LENERR_OK_ON/OFF, or SK_BIG_PK_OK_ON/OFF */
37461 @@ -511,7 +560,7 @@
37462 XM_IN16(IoC, Port, XM_RX_CMD, &OldRxCmd);
37467 switch (Mode & (SK_STRIP_FCS_ON | SK_STRIP_FCS_OFF)) {
37468 case SK_STRIP_FCS_ON:
37469 RxCmd |= XM_RX_STRIP_FCS;
37470 @@ -572,8 +621,8 @@
37472 * - FCS (CRC) stripping, SK_STRIP_FCS_ON/OFF
37473 * - don't set GMR_FS_LONG_ERR SK_BIG_PK_OK_ON/OFF
37474 - * for frames > 1514 bytes
37475 - * - enable Rx of own packets SK_SELF_RX_ON/OFF
37476 + * for frames > 1514 bytes
37477 + * - enable Rx of own packets SK_SELF_RX_ON/OFF
37479 * for incoming packets may be enabled/disabled by this function.
37480 * Additional modes may be added later.
37481 @@ -584,20 +633,17 @@
37484 static void SkGmSetRxCmd(
37485 -SK_AC *pAC, /* adapter context */
37486 -SK_IOC IoC, /* IO context */
37487 +SK_AC *pAC, /* Adapter Context */
37488 +SK_IOC IoC, /* I/O Context */
37489 int Port, /* Port Index (MAC_1 + n) */
37490 int Mode) /* Mode is SK_STRIP_FCS_ON/OFF, SK_STRIP_PAD_ON/OFF,
37491 - SK_LENERR_OK_ON/OFF, or SK_BIG_PK_OK_ON/OFF */
37492 + SK_LENERR_OK_ON/OFF, or SK_BIG_PK_OK_ON/OFF */
37497 if ((Mode & (SK_STRIP_FCS_ON | SK_STRIP_FCS_OFF)) != 0) {
37499 - GM_IN16(IoC, Port, GM_RX_CTRL, &OldRxCmd);
37501 - RxCmd = OldRxCmd;
37502 + GM_IN16(IoC, Port, GM_RX_CTRL, &RxCmd);
37504 if ((Mode & SK_STRIP_FCS_ON) != 0) {
37505 RxCmd |= GM_RXCR_CRC_DIS;
37506 @@ -605,17 +651,13 @@
37508 RxCmd &= ~GM_RXCR_CRC_DIS;
37510 - /* Write the new mode to the Rx control register if required */
37511 - if (OldRxCmd != RxCmd) {
37512 - GM_OUT16(IoC, Port, GM_RX_CTRL, RxCmd);
37514 + /* Write the new mode to the Rx Control register */
37515 + GM_OUT16(IoC, Port, GM_RX_CTRL, RxCmd);
37518 if ((Mode & (SK_BIG_PK_OK_ON | SK_BIG_PK_OK_OFF)) != 0) {
37520 - GM_IN16(IoC, Port, GM_SERIAL_MODE, &OldRxCmd);
37522 - RxCmd = OldRxCmd;
37523 + GM_IN16(IoC, Port, GM_SERIAL_MODE, &RxCmd);
37525 if ((Mode & SK_BIG_PK_OK_ON) != 0) {
37526 RxCmd |= GM_SMOD_JUMBO_ENA;
37527 @@ -623,10 +665,8 @@
37529 RxCmd &= ~GM_SMOD_JUMBO_ENA;
37531 - /* Write the new mode to the Rx control register if required */
37532 - if (OldRxCmd != RxCmd) {
37533 - GM_OUT16(IoC, Port, GM_SERIAL_MODE, RxCmd);
37535 + /* Write the new mode to the Serial Mode register */
37536 + GM_OUT16(IoC, Port, GM_SERIAL_MODE, RxCmd);
37538 } /* SkGmSetRxCmd */
37540 @@ -641,17 +681,17 @@
37543 void SkMacSetRxCmd(
37544 -SK_AC *pAC, /* adapter context */
37545 -SK_IOC IoC, /* IO context */
37546 +SK_AC *pAC, /* Adapter Context */
37547 +SK_IOC IoC, /* I/O Context */
37548 int Port, /* Port Index (MAC_1 + n) */
37549 int Mode) /* Rx Mode */
37551 if (pAC->GIni.GIGenesis) {
37554 SkXmSetRxCmd(pAC, IoC, Port, Mode);
37559 SkGmSetRxCmd(pAC, IoC, Port, Mode);
37562 @@ -668,15 +708,15 @@
37565 void SkMacCrcGener(
37566 -SK_AC *pAC, /* adapter context */
37567 -SK_IOC IoC, /* IO context */
37568 +SK_AC *pAC, /* Adapter Context */
37569 +SK_IOC IoC, /* I/O Context */
37570 int Port, /* Port Index (MAC_1 + n) */
37571 SK_BOOL Enable) /* Enable / Disable */
37575 if (pAC->GIni.GIGenesis) {
37578 XM_IN16(IoC, Port, XM_TX_CMD, &Word);
37581 @@ -689,9 +729,9 @@
37582 XM_OUT16(IoC, Port, XM_TX_CMD, Word);
37587 GM_IN16(IoC, Port, GM_TX_CTRL, &Word);
37591 Word &= ~GM_TXCR_CRC_DIS;
37593 @@ -721,14 +761,14 @@
37596 void SkXmClrExactAddr(
37597 -SK_AC *pAC, /* adapter context */
37598 -SK_IOC IoC, /* IO context */
37599 +SK_AC *pAC, /* Adapter Context */
37600 +SK_IOC IoC, /* I/O Context */
37601 int Port, /* Port Index (MAC_1 + n) */
37602 int StartNum, /* Begin with this Address Register Index (0..15) */
37603 int StopNum) /* Stop after finished with this Register Idx (0..15) */
37606 - SK_U16 ZeroAddr[3] = {0x0000, 0x0000, 0x0000};
37607 + SK_U16 ZeroAddr[3] = {0, 0, 0};
37609 if ((unsigned)StartNum > 15 || (unsigned)StopNum > 15 ||
37610 StartNum > StopNum) {
37611 @@ -738,7 +778,7 @@
37614 for (i = StartNum; i <= StopNum; i++) {
37615 - XM_OUTADDR(IoC, Port, XM_EXM(i), &ZeroAddr[0]);
37616 + XM_OUTADDR(IoC, Port, XM_EXM(i), ZeroAddr);
37618 } /* SkXmClrExactAddr */
37619 #endif /* GENESIS */
37620 @@ -755,21 +795,21 @@
37623 void SkMacFlushTxFifo(
37624 -SK_AC *pAC, /* adapter context */
37625 -SK_IOC IoC, /* IO context */
37626 +SK_AC *pAC, /* Adapter Context */
37627 +SK_IOC IoC, /* I/O Context */
37628 int Port) /* Port Index (MAC_1 + n) */
37633 if (pAC->GIni.GIGenesis) {
37636 XM_IN32(IoC, Port, XM_MODE, &MdReg);
37638 XM_OUT32(IoC, Port, XM_MODE, MdReg | XM_MD_FTF);
37640 #endif /* GENESIS */
37644 if (pAC->GIni.GIYukon) {
37645 /* no way to flush the FIFO we have to issue a reset */
37646 @@ -790,9 +830,9 @@
37650 -static void SkMacFlushRxFifo(
37651 -SK_AC *pAC, /* adapter context */
37652 -SK_IOC IoC, /* IO context */
37653 +void SkMacFlushRxFifo(
37654 +SK_AC *pAC, /* Adapter Context */
37655 +SK_IOC IoC, /* I/O Context */
37656 int Port) /* Port Index (MAC_1 + n) */
37659 @@ -805,7 +845,7 @@
37660 XM_OUT32(IoC, Port, XM_MODE, MdReg | XM_MD_FRF);
37662 #endif /* GENESIS */
37666 if (pAC->GIni.GIYukon) {
37667 /* no way to flush the FIFO we have to issue a reset */
37668 @@ -853,23 +893,23 @@
37671 static void SkXmSoftRst(
37672 -SK_AC *pAC, /* adapter context */
37673 -SK_IOC IoC, /* IO context */
37674 +SK_AC *pAC, /* Adapter Context */
37675 +SK_IOC IoC, /* I/O Context */
37676 int Port) /* Port Index (MAC_1 + n) */
37678 - SK_U16 ZeroAddr[4] = {0x0000, 0x0000, 0x0000, 0x0000};
37680 + SK_U16 ZeroAddr[4] = {0, 0, 0, 0};
37682 /* reset the statistics module */
37683 XM_OUT32(IoC, Port, XM_GP_PORT, XM_GP_RES_STAT);
37685 /* disable all XMAC IRQs */
37686 XM_OUT16(IoC, Port, XM_IMSK, 0xffff);
37689 XM_OUT32(IoC, Port, XM_MODE, 0); /* clear Mode Reg */
37692 XM_OUT16(IoC, Port, XM_TX_CMD, 0); /* reset TX CMD Reg */
37693 XM_OUT16(IoC, Port, XM_RX_CMD, 0); /* reset RX CMD Reg */
37696 /* disable all PHY IRQs */
37697 switch (pAC->GIni.GP[Port].PhyType) {
37699 @@ -887,13 +927,13 @@
37702 /* clear the Hash Register */
37703 - XM_OUTHASH(IoC, Port, XM_HSM, &ZeroAddr);
37704 + XM_OUTHASH(IoC, Port, XM_HSM, ZeroAddr);
37706 /* clear the Exact Match Address registers */
37707 SkXmClrExactAddr(pAC, IoC, Port, 0, 15);
37710 /* clear the Source Check Address registers */
37711 - XM_OUTHASH(IoC, Port, XM_SRC_CHK, &ZeroAddr);
37712 + XM_OUTHASH(IoC, Port, XM_SRC_CHK, ZeroAddr);
37714 } /* SkXmSoftRst */
37716 @@ -916,8 +956,8 @@
37719 static void SkXmHardRst(
37720 -SK_AC *pAC, /* adapter context */
37721 -SK_IOC IoC, /* IO context */
37722 +SK_AC *pAC, /* Adapter Context */
37723 +SK_IOC IoC, /* I/O Context */
37724 int Port) /* Port Index (MAC_1 + n) */
37727 @@ -940,19 +980,19 @@
37730 SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
37733 SK_IN16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), &Word);
37736 } while ((Word & MFF_SET_MAC_RST) == 0);
37739 /* For external PHYs there must be special handling */
37740 if (pAC->GIni.GP[Port].PhyType != SK_PHY_XMAC) {
37743 SK_IN32(IoC, B2_GP_IO, &Reg);
37747 - Reg |= GP_DIR_0; /* set to output */
37748 + Reg |= GP_DIR_0; /* set to output */
37749 Reg &= ~GP_IO_0; /* set PHY reset (active low) */
37752 @@ -978,12 +1018,12 @@
37755 static void SkXmClearRst(
37756 -SK_AC *pAC, /* adapter context */
37757 -SK_IOC IoC, /* IO context */
37758 +SK_AC *pAC, /* Adapter Context */
37759 +SK_IOC IoC, /* I/O Context */
37760 int Port) /* Port Index (MAC_1 + n) */
37765 /* clear HW reset */
37766 SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
37768 @@ -1000,7 +1040,7 @@
37769 /* Clear PHY reset */
37770 SK_OUT32(IoC, B2_GP_IO, DWord);
37772 - /* Enable GMII interface */
37773 + /* enable GMII interface */
37774 XM_OUT16(IoC, Port, XM_HW_CFG, XM_HW_GMII_MD);
37776 } /* SkXmClearRst */
37777 @@ -1020,29 +1060,28 @@
37780 static void SkGmSoftRst(
37781 -SK_AC *pAC, /* adapter context */
37782 -SK_IOC IoC, /* IO context */
37783 +SK_AC *pAC, /* Adapter Context */
37784 +SK_IOC IoC, /* I/O Context */
37785 int Port) /* Port Index (MAC_1 + n) */
37787 - SK_U16 EmptyHash[4] = {0x0000, 0x0000, 0x0000, 0x0000};
37789 + SK_U16 EmptyHash[4] = { 0x0000, 0x0000, 0x0000, 0x0000 };
37792 /* reset the statistics module */
37794 /* disable all GMAC IRQs */
37795 - SK_OUT8(IoC, GMAC_IRQ_MSK, 0);
37797 + SK_OUT8(IoC, MR_ADDR(Port, GMAC_IRQ_MSK), 0);
37799 /* disable all PHY IRQs */
37800 SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, 0);
37803 /* clear the Hash Register */
37804 GM_OUTHASH(IoC, Port, GM_MC_ADDR_H1, EmptyHash);
37806 - /* Enable Unicast and Multicast filtering */
37807 + /* enable Unicast and Multicast filtering */
37808 GM_IN16(IoC, Port, GM_RX_CTRL, &RxCtrl);
37810 - GM_OUT16(IoC, Port, GM_RX_CTRL,
37811 - (SK_U16)(RxCtrl | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA));
37813 + GM_OUT16(IoC, Port, GM_RX_CTRL, RxCtrl | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
37815 } /* SkGmSoftRst */
37817 @@ -1057,16 +1096,16 @@
37820 static void SkGmHardRst(
37821 -SK_AC *pAC, /* adapter context */
37822 -SK_IOC IoC, /* IO context */
37823 +SK_AC *pAC, /* Adapter Context */
37824 +SK_IOC IoC, /* I/O Context */
37825 int Port) /* Port Index (MAC_1 + n) */
37830 /* WA code for COMA mode */
37831 if (pAC->GIni.GIYukonLite &&
37832 pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3) {
37835 SK_IN32(IoC, B2_GP_IO, &DWord);
37837 DWord |= (GP_DIR_9 | GP_IO_9);
37838 @@ -1076,10 +1115,10 @@
37841 /* set GPHY Control reset */
37842 - SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), GPC_RST_SET);
37843 + SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_SET);
37845 /* set GMAC Control reset */
37846 - SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_RST_SET);
37847 + SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_SET);
37849 } /* SkGmHardRst */
37851 @@ -1094,24 +1133,24 @@
37854 static void SkGmClearRst(
37855 -SK_AC *pAC, /* adapter context */
37856 -SK_IOC IoC, /* IO context */
37857 +SK_AC *pAC, /* Adapter Context */
37858 +SK_IOC IoC, /* I/O Context */
37859 int Port) /* Port Index (MAC_1 + n) */
37864 - /* clear GMAC Control reset */
37865 - SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_RST_CLR);
37869 +#endif /* SK_DIAG */
37871 - /* set GMAC Control reset */
37872 - SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_RST_SET);
37874 +#if defined(SK_DIAG) || defined(DEBUG)
37876 +#endif /* SK_DIAG || DEBUG */
37878 /* WA code for COMA mode */
37879 if (pAC->GIni.GIYukonLite &&
37880 pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3) {
37883 SK_IN32(IoC, B2_GP_IO, &DWord);
37885 DWord |= GP_DIR_9; /* set to output */
37886 @@ -1121,30 +1160,87 @@
37887 SK_OUT32(IoC, B2_GP_IO, DWord);
37890 - /* set HWCFG_MODE */
37891 - DWord = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
37892 - GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE |
37893 - (pAC->GIni.GICopperType ? GPC_HWCFG_GMII_COP :
37894 - GPC_HWCFG_GMII_FIB);
37896 + /* set MAC Reset before PHY reset is set */
37897 + SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_SET);
37900 - /* set GPHY Control reset */
37901 - SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), DWord | GPC_RST_SET);
37902 + if (CHIP_ID_YUKON_2(pAC)) {
37903 + /* set GPHY Control reset */
37904 + SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_SET);
37906 - /* release GPHY Control reset */
37907 - SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), DWord | GPC_RST_CLR);
37908 + /* release GPHY Control reset */
37909 + SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_CLR);
37912 + /* additional check for PEX */
37913 + SK_IN16(IoC, GPHY_CTRL, &Word);
37915 + if (pAC->GIni.GIPciBus == SK_PEX_BUS && Word != GPC_RST_CLR) {
37917 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
37918 + ("Error on PEX-bus after GPHY reset\n"));
37920 +#endif /* DEBUG */
37923 + /* set HWCFG_MODE */
37924 + DWord = GPC_INT_POL | GPC_DIS_FC | GPC_DIS_SLEEP |
37925 + GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE |
37926 + (pAC->GIni.GICopperType ? GPC_HWCFG_GMII_COP :
37927 + GPC_HWCFG_GMII_FIB);
37929 + /* set GPHY Control reset */
37930 + SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), DWord | GPC_RST_SET);
37932 + /* release GPHY Control reset */
37933 + SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), DWord | GPC_RST_CLR);
37937 + /* wait for internal initialization of GPHY */
37938 + VCPUprintf(0, "Waiting until PHY %d is ready to initialize\n", Port);
37941 + /* release GMAC reset */
37942 + SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_CLR);
37944 + /* wait for stable GMAC clock */
37948 /* clear GMAC Control reset */
37949 - SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
37950 + SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_CLR);
37953 + if (HW_FEATURE(pAC, HWF_WA_DEV_472) && Port == MAC_2) {
37955 + /* clear GMAC 1 Control reset */
37956 + SK_OUT8(IoC, MR_ADDR(MAC_1, GMAC_CTRL), (SK_U8)GMC_RST_CLR);
37959 + /* set GMAC 2 Control reset */
37960 + SK_OUT8(IoC, MR_ADDR(MAC_2, GMAC_CTRL), (SK_U8)GMC_RST_SET);
37962 + /* clear GMAC 2 Control reset */
37963 + SK_OUT8(IoC, MR_ADDR(MAC_2, GMAC_CTRL), (SK_U8)GMC_RST_CLR);
37965 + SkGmPhyRead(pAC, IoC, MAC_2, PHY_MARV_ID0, &PhyId0);
37967 + SkGmPhyRead(pAC, IoC, MAC_2, PHY_MARV_ID1, &PhyId1);
37969 + SkGmPhyRead(pAC, IoC, MAC_2, PHY_MARV_INT_MASK, &Word);
37971 + } while (Word != 0 || PhyId0 != PHY_MARV_ID0_VAL ||
37972 + PhyId1 != PHY_MARV_ID1_Y2);
37974 +#endif /* SK_DIAG */
37980 SK_IN32(IoC, MR_ADDR(Port, GPHY_CTRL), &DWord);
37983 SK_IN32(IoC, B0_ISRC, &DWord);
37986 @@ -1162,37 +1258,33 @@
37990 -SK_AC *pAC, /* adapter context */
37991 -SK_IOC IoC, /* IO context */
37992 +SK_AC *pAC, /* Adapter Context */
37993 +SK_IOC IoC, /* I/O Context */
37994 int Port) /* Port Index (MAC_1 + n) */
37998 - pPrt = &pAC->GIni.GP[Port];
38000 /* disable receiver and transmitter */
38001 SkMacRxTxDisable(pAC, IoC, Port);
38004 if (pAC->GIni.GIGenesis) {
38007 SkXmSoftRst(pAC, IoC, Port);
38009 #endif /* GENESIS */
38013 if (pAC->GIni.GIYukon) {
38016 SkGmSoftRst(pAC, IoC, Port);
38020 /* flush the MAC's Rx and Tx FIFOs */
38021 SkMacFlushTxFifo(pAC, IoC, Port);
38024 SkMacFlushRxFifo(pAC, IoC, Port);
38026 - pPrt->PState = SK_PRT_STOP;
38027 + pAC->GIni.GP[Port].PState = SK_PRT_STOP;
38029 } /* SkMacSoftRst */
38031 @@ -1207,29 +1299,63 @@
38035 -SK_AC *pAC, /* adapter context */
38036 -SK_IOC IoC, /* IO context */
38037 +SK_AC *pAC, /* Adapter Context */
38038 +SK_IOC IoC, /* I/O Context */
38039 int Port) /* Port Index (MAC_1 + n) */
38044 if (pAC->GIni.GIGenesis) {
38047 SkXmHardRst(pAC, IoC, Port);
38049 #endif /* GENESIS */
38053 if (pAC->GIni.GIYukon) {
38056 SkGmHardRst(pAC, IoC, Port);
38060 + pAC->GIni.GP[Port].PHWLinkUp = SK_FALSE;
38062 pAC->GIni.GP[Port].PState = SK_PRT_RESET;
38064 } /* SkMacHardRst */
38067 +/******************************************************************************
38069 + * SkMacClearRst() - Clear the MAC reset
38071 + * Description: calls a clear MAC reset routine dep. on board type
38076 +void SkMacClearRst(
38077 +SK_AC *pAC, /* Adapter Context */
38078 +SK_IOC IoC, /* I/O Context */
38079 +int Port) /* Port Index (MAC_1 + n) */
38083 + if (pAC->GIni.GIGenesis) {
38085 + SkXmClearRst(pAC, IoC, Port);
38087 +#endif /* GENESIS */
38090 + if (pAC->GIni.GIYukon) {
38092 + SkGmClearRst(pAC, IoC, Port);
38094 +#endif /* YUKON */
38096 +} /* SkMacClearRst */
38097 +#endif /* !SK_SLIM */
38100 /******************************************************************************
38101 @@ -1247,8 +1373,8 @@
38105 -SK_AC *pAC, /* adapter context */
38106 -SK_IOC IoC, /* IO context */
38107 +SK_AC *pAC, /* Adapter Context */
38108 +SK_IOC IoC, /* I/O Context */
38109 int Port) /* Port Index (MAC_1 + n) */
38112 @@ -1258,13 +1384,13 @@
38113 pPrt = &pAC->GIni.GP[Port];
38115 if (pPrt->PState == SK_PRT_STOP) {
38116 - /* Port State: SK_PRT_STOP */
38117 /* Verify that the reset bit is cleared */
38118 SK_IN16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), &SWord);
38120 if ((SWord & MFF_SET_MAC_RST) != 0) {
38121 /* PState does not match HW state */
38122 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E006, SKERR_HWI_E006MSG);
38123 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
38124 + ("SkXmInitMac: PState does not match HW state"));
38126 pPrt->PState = SK_PRT_RESET;
38128 @@ -1283,7 +1409,7 @@
38129 * Must be done AFTER first access to BCOM chip.
38131 XM_IN16(IoC, Port, XM_MMU_CMD, &SWord);
38134 XM_OUT16(IoC, Port, XM_MMU_CMD, SWord | XM_MMU_NO_PRE);
38136 if (pPrt->PhyId1 == PHY_BCOM_ID1_C0) {
38137 @@ -1316,7 +1442,7 @@
38138 * Disable Power Management after reset.
38140 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &SWord);
38143 SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUX_CTRL,
38144 (SK_U16)(SWord | PHY_B_AC_DIS_PM));
38146 @@ -1325,19 +1451,13 @@
38148 /* Dummy read the Interrupt source register */
38149 XM_IN16(IoC, Port, XM_ISRC, &SWord);
38153 * The auto-negotiation process starts immediately after
38154 * clearing the reset. The auto-negotiation process should be
38155 * started by the SIRQ, therefore stop it here immediately.
38157 SkMacInitPhy(pAC, IoC, Port, SK_FALSE);
38160 - /* temp. code: enable signal detect */
38161 - /* WARNING: do not override GMII setting above */
38162 - XM_OUT16(IoC, Port, XM_HW_CFG, XM_HW_COM4SIG);
38167 @@ -1351,7 +1471,7 @@
38168 * independent. Remember this when changing.
38170 SK_IN16(IoC, (B2_MAC_2 + Port * 8 + i * 2), &SWord);
38173 XM_OUT16(IoC, Port, (XM_SA + i * 2), SWord);
38176 @@ -1369,7 +1489,7 @@
38177 SWord = SK_XM_THR_SL; /* for single port */
38179 if (pAC->GIni.GIMacsFound > 1) {
38180 - switch (pAC->GIni.GIPortUsage) {
38181 + switch (pPrt->PPortUsage) {
38183 SWord = SK_XM_THR_REDL; /* redundant link */
38185 @@ -1392,7 +1512,7 @@
38186 /* setup register defaults for the Rx Command Register */
38187 SWord = XM_RX_STRIP_FCS | XM_RX_LENERR_OK;
38189 - if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
38190 + if (pPrt->PPortUsage == SK_JUMBO_LINK) {
38191 SWord |= XM_RX_BIG_PK_OK;
38194 @@ -1404,7 +1524,7 @@
38196 SWord |= XM_RX_DIS_CEXT;
38200 XM_OUT16(IoC, Port, XM_RX_CMD, SWord);
38203 @@ -1461,8 +1581,8 @@
38207 -SK_AC *pAC, /* adapter context */
38208 -SK_IOC IoC, /* IO context */
38209 +SK_AC *pAC, /* Adapter Context */
38210 +SK_IOC IoC, /* I/O Context */
38211 int Port) /* Port Index (MAC_1 + n) */
38214 @@ -1473,26 +1593,41 @@
38215 pPrt = &pAC->GIni.GP[Port];
38217 if (pPrt->PState == SK_PRT_STOP) {
38218 - /* Port State: SK_PRT_STOP */
38219 /* Verify that the reset bit is cleared */
38220 SK_IN32(IoC, MR_ADDR(Port, GMAC_CTRL), &DWord);
38223 if ((DWord & GMC_RST_SET) != 0) {
38224 /* PState does not match HW state */
38225 - SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E006, SKERR_HWI_E006MSG);
38226 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38227 + ("SkGmInitMac: PState does not match HW state"));
38229 pPrt->PState = SK_PRT_RESET;
38232 + /* enable PHY interrupts */
38233 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK,
38234 + (SK_U16)PHY_M_DEF_MSK);
38238 if (pPrt->PState == SK_PRT_RESET) {
38241 SkGmHardRst(pAC, IoC, Port);
38243 SkGmClearRst(pAC, IoC, Port);
38247 + if (HW_FEATURE(pAC, HWF_FORCE_AUTO_NEG) &&
38248 + pPrt->PLinkModeConf < SK_LMODE_AUTOHALF) {
38249 + /* Force Auto-Negotiation */
38250 + pPrt->PLinkMode = (pPrt->PLinkModeConf == SK_LMODE_FULL) ?
38251 + SK_LMODE_AUTOBOTH : SK_LMODE_AUTOHALF;
38253 +#endif /* !SK_SLIM */
38255 /* Auto-negotiation ? */
38256 - if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
38257 + if (pPrt->PLinkMode == SK_LMODE_HALF ||
38258 + pPrt->PLinkMode == SK_LMODE_FULL) {
38259 /* Auto-negotiation disabled */
38261 /* get General Purpose Control */
38262 @@ -1500,10 +1635,10 @@
38264 /* disable auto-update for speed, duplex and flow-control */
38265 SWord |= GM_GPCR_AU_ALL_DIS;
38268 /* setup General Purpose Control Register */
38269 GM_OUT16(IoC, Port, GM_GP_CTRL, SWord);
38272 SWord = GM_GPCR_AU_ALL_DIS;
38275 @@ -1514,7 +1649,10 @@
38276 switch (pPrt->PLinkSpeed) {
38277 case SK_LSPEED_AUTO:
38278 case SK_LSPEED_1000MBPS:
38279 - SWord |= GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100;
38280 + if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
38282 + SWord |= GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100;
38285 case SK_LSPEED_100MBPS:
38286 SWord |= GM_GPCR_SPEED_100;
38287 @@ -1532,8 +1670,6 @@
38288 /* flow-control settings */
38289 switch (pPrt->PFlowCtrlMode) {
38290 case SK_FLOW_MODE_NONE:
38291 - /* set Pause Off */
38292 - SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_PAUSE_OFF);
38293 /* disable Tx & Rx flow-control */
38294 SWord |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
38296 @@ -1551,24 +1687,22 @@
38297 GM_OUT16(IoC, Port, GM_GP_CTRL, SWord);
38299 /* dummy read the Interrupt Source Register */
38300 - SK_IN16(IoC, GMAC_IRQ_SRC, &SWord);
38302 + SK_IN16(IoC, MR_ADDR(Port, GMAC_IRQ_SRC), &SWord);
38305 - /* read Id from PHY */
38306 - SkGmPhyRead(pAC, IoC, Port, PHY_MARV_ID1, &pPrt->PhyId1);
38308 SkGmInitPhyMarv(pAC, IoC, Port, SK_FALSE);
38310 +#endif /* !VCPU */
38313 (void)SkGmResetCounter(pAC, IoC, Port);
38315 /* setup Transmit Control Register */
38316 - GM_OUT16(IoC, Port, GM_TX_CTRL, TX_COL_THR(pPrt->PMacColThres));
38317 + GM_OUT16(IoC, Port, GM_TX_CTRL, (SK_U16)TX_COL_THR(pPrt->PMacColThres));
38319 /* setup Receive Control Register */
38320 - GM_OUT16(IoC, Port, GM_RX_CTRL, GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA |
38321 - GM_RXCR_CRC_DIS);
38322 + SWord = GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA | GM_RXCR_CRC_DIS;
38324 + GM_OUT16(IoC, Port, GM_RX_CTRL, SWord);
38326 /* setup Transmit Flow Control Register */
38327 GM_OUT16(IoC, Port, GM_TX_FLOW_CTRL, 0xffff);
38328 @@ -1578,31 +1712,29 @@
38329 GM_IN16(IoC, Port, GM_TX_PARAM, &SWord);
38332 - SWord = TX_JAM_LEN_VAL(pPrt->PMacJamLen) |
38333 - TX_JAM_IPG_VAL(pPrt->PMacJamIpgVal) |
38334 - TX_IPG_JAM_DATA(pPrt->PMacJamIpgData);
38336 + SWord = (SK_U16)(TX_JAM_LEN_VAL(pPrt->PMacJamLen) |
38337 + TX_JAM_IPG_VAL(pPrt->PMacJamIpgVal) |
38338 + TX_IPG_JAM_DATA(pPrt->PMacJamIpgData) |
38339 + TX_BACK_OFF_LIM(pPrt->PMacBackOffLim));
38341 GM_OUT16(IoC, Port, GM_TX_PARAM, SWord);
38343 /* configure the Serial Mode Register */
38345 - GM_IN16(IoC, Port, GM_SERIAL_MODE, &SWord);
38348 - SWord = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(pPrt->PMacIpgData);
38349 + SWord = (SK_U16)(DATA_BLIND_VAL(pPrt->PMacDataBlind) |
38350 + GM_SMOD_VLAN_ENA | IPG_DATA_VAL(pPrt->PMacIpgData));
38352 if (pPrt->PMacLimit4) {
38353 /* reset of collision counter after 4 consecutive collisions */
38354 SWord |= GM_SMOD_LIMIT_4;
38357 - if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
38358 + if (pPrt->PPortUsage == SK_JUMBO_LINK) {
38359 /* enable jumbo mode (Max. Frame Length = 9018) */
38360 SWord |= GM_SMOD_JUMBO_ENA;
38364 GM_OUT16(IoC, Port, GM_SERIAL_MODE, SWord);
38368 * configure the GMACs Station Addresses
38369 * in PROM you can find our addresses at:
38370 @@ -1631,17 +1763,17 @@
38372 GM_OUT16(IoC, Port, (GM_SRC_ADDR_1L + i * 4), SWord);
38376 GM_OUT16(IoC, Port, (GM_SRC_ADDR_1L + i * 4), SWord);
38377 #endif /* WA_DEV_16 */
38380 /* virtual address: will be used for data */
38381 SK_IN16(IoC, (B2_MAC_1 + Port * 8 + i * 2), &SWord);
38383 GM_OUT16(IoC, Port, (GM_SRC_ADDR_2L + i * 4), SWord);
38386 /* reset Multicast filtering Hash registers 1-3 */
38387 - GM_OUT16(IoC, Port, GM_MC_ADDR_H1 + 4*i, 0);
38388 + GM_OUT16(IoC, Port, GM_MC_ADDR_H1 + i * 4, 0);
38391 /* reset Multicast filtering Hash register 4 */
38392 @@ -1652,18 +1784,6 @@
38393 GM_OUT16(IoC, Port, GM_RX_IRQ_MSK, 0);
38394 GM_OUT16(IoC, Port, GM_TR_IRQ_MSK, 0);
38396 -#if defined(SK_DIAG) || defined(DEBUG)
38397 - /* read General Purpose Status */
38398 - GM_IN16(IoC, Port, GM_GP_STAT, &SWord);
38400 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38401 - ("MAC Stat Reg.=0x%04X\n", SWord));
38402 -#endif /* SK_DIAG || DEBUG */
38405 - c_print("MAC Stat Reg=0x%04X\n", SWord);
38406 -#endif /* SK_DIAG */
38408 } /* SkGmInitMac */
38411 @@ -1681,9 +1801,9 @@
38415 -static void SkXmInitDupMd(
38416 -SK_AC *pAC, /* adapter context */
38417 -SK_IOC IoC, /* IO context */
38418 +void SkXmInitDupMd(
38419 +SK_AC *pAC, /* Adapter Context */
38420 +SK_IOC IoC, /* I/O Context */
38421 int Port) /* Port Index (MAC_1 + n) */
38423 switch (pAC->GIni.GP[Port].PLinkModeStatus) {
38424 @@ -1729,9 +1849,9 @@
38428 -static void SkXmInitPauseMd(
38429 -SK_AC *pAC, /* adapter context */
38430 -SK_IOC IoC, /* IO context */
38431 +void SkXmInitPauseMd(
38432 +SK_AC *pAC, /* Adapter Context */
38433 +SK_IOC IoC, /* I/O Context */
38434 int Port) /* Port Index (MAC_1 + n) */
38437 @@ -1741,11 +1861,11 @@
38438 pPrt = &pAC->GIni.GP[Port];
38440 XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
38443 if (pPrt->PFlowCtrlStatus == SK_FLOW_STAT_NONE ||
38444 pPrt->PFlowCtrlStatus == SK_FLOW_STAT_LOC_SEND) {
38446 - /* Disable Pause Frame Reception */
38447 + /* disable Pause Frame Reception */
38448 Word |= XM_MMU_IGN_PF;
38451 @@ -1753,10 +1873,10 @@
38452 * enabling pause frame reception is required for 1000BT
38453 * because the XMAC is not reset if the link is going down
38455 - /* Enable Pause Frame Reception */
38456 + /* enable Pause Frame Reception */
38457 Word &= ~XM_MMU_IGN_PF;
38462 XM_OUT16(IoC, Port, XM_MMU_CMD, Word);
38464 XM_IN32(IoC, Port, XM_MODE, &DWord);
38465 @@ -1779,10 +1899,10 @@
38466 /* remember this value is defined in big endian (!) */
38467 XM_OUT16(IoC, Port, XM_MAC_PTIME, 0xffff);
38469 - /* Set Pause Mode in Mode Register */
38470 + /* set Pause Mode in Mode Register */
38471 DWord |= XM_PAUSE_MODE;
38473 - /* Set Pause Mode in MAC Rx FIFO */
38474 + /* set Pause Mode in MAC Rx FIFO */
38475 SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
38478 @@ -1790,22 +1910,22 @@
38479 * disable pause frame generation is required for 1000BT
38480 * because the XMAC is not reset if the link is going down
38482 - /* Disable Pause Mode in Mode Register */
38483 + /* disable Pause Mode in Mode Register */
38484 DWord &= ~XM_PAUSE_MODE;
38486 - /* Disable Pause Mode in MAC Rx FIFO */
38487 + /* disable Pause Mode in MAC Rx FIFO */
38488 SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
38492 XM_OUT32(IoC, Port, XM_MODE, DWord);
38493 } /* SkXmInitPauseMd*/
38496 /******************************************************************************
38498 - * SkXmInitPhyXmac() - Initialize the XMAC Phy registers
38499 + * SkXmInitPhyXmac() - Initialize the XMAC PHY registers
38501 - * Description: initializes all the XMACs Phy registers
38502 + * Description: initializes all the XMACs PHY registers
38506 @@ -1813,22 +1933,22 @@
38509 static void SkXmInitPhyXmac(
38510 -SK_AC *pAC, /* adapter context */
38511 -SK_IOC IoC, /* IO context */
38512 +SK_AC *pAC, /* Adapter Context */
38513 +SK_IOC IoC, /* I/O Context */
38514 int Port, /* Port Index (MAC_1 + n) */
38515 -SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */
38516 +SK_BOOL DoLoop) /* Should a PHY LoopBack be set-up? */
38521 pPrt = &pAC->GIni.GP[Port];
38525 /* Auto-negotiation ? */
38526 if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
38527 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38528 ("InitPhyXmac: no auto-negotiation Port %d\n", Port));
38529 - /* Set DuplexMode in Config register */
38530 + /* set DuplexMode in Config register */
38531 if (pPrt->PLinkMode == SK_LMODE_FULL) {
38532 Ctrl |= PHY_CT_DUP_MD;
38534 @@ -1841,9 +1961,9 @@
38536 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38537 ("InitPhyXmac: with auto-negotiation Port %d\n", Port));
38538 - /* Set Auto-negotiation advertisement */
38539 + /* set Auto-negotiation advertisement */
38541 - /* Set Full/half duplex capabilities */
38542 + /* set Full/half duplex capabilities */
38543 switch (pPrt->PLinkMode) {
38544 case SK_LMODE_AUTOHALF:
38545 Ctrl |= PHY_X_AN_HD;
38546 @@ -1859,7 +1979,7 @@
38547 SKERR_HWI_E015MSG);
38550 - /* Set Flow-control capabilities */
38551 + /* set Flow-control capabilities */
38552 switch (pPrt->PFlowCtrlMode) {
38553 case SK_FLOW_MODE_NONE:
38554 Ctrl |= PHY_X_P_NO_PAUSE;
38555 @@ -1886,20 +2006,20 @@
38559 - /* Set the Phy Loopback bit, too */
38560 + /* set the PHY Loopback bit, too */
38561 Ctrl |= PHY_CT_LOOP;
38564 - /* Write to the Phy control register */
38565 + /* Write to the PHY control register */
38566 SkXmPhyWrite(pAC, IoC, Port, PHY_XMAC_CTRL, Ctrl);
38567 } /* SkXmInitPhyXmac */
38570 /******************************************************************************
38572 - * SkXmInitPhyBcom() - Initialize the Broadcom Phy registers
38573 + * SkXmInitPhyBcom() - Initialize the Broadcom PHY registers
38575 - * Description: initializes all the Broadcom Phy registers
38576 + * Description: initializes all the Broadcom PHY registers
38580 @@ -1907,10 +2027,10 @@
38583 static void SkXmInitPhyBcom(
38584 -SK_AC *pAC, /* adapter context */
38585 -SK_IOC IoC, /* IO context */
38586 +SK_AC *pAC, /* Adapter Context */
38587 +SK_IOC IoC, /* I/O Context */
38588 int Port, /* Port Index (MAC_1 + n) */
38589 -SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */
38590 +SK_BOOL DoLoop) /* Should a PHY LoopBack be set-up? */
38594 @@ -1930,16 +2050,17 @@
38595 /* manually Master/Slave ? */
38596 if (pPrt->PMSMode != SK_MS_MODE_AUTO) {
38597 Ctrl2 |= PHY_B_1000C_MSE;
38600 if (pPrt->PMSMode == SK_MS_MODE_MASTER) {
38601 Ctrl2 |= PHY_B_1000C_MSC;
38605 /* Auto-negotiation ? */
38606 if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
38607 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38608 ("InitPhyBcom: no auto-negotiation Port %d\n", Port));
38609 - /* Set DuplexMode in Config register */
38610 + /* set DuplexMode in Config register */
38611 if (pPrt->PLinkMode == SK_LMODE_FULL) {
38612 Ctrl1 |= PHY_CT_DUP_MD;
38614 @@ -1957,7 +2078,7 @@
38616 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38617 ("InitPhyBcom: with auto-negotiation Port %d\n", Port));
38618 - /* Set Auto-negotiation advertisement */
38619 + /* set Auto-negotiation advertisement */
38622 * Workaround BCOM Errata #1 for the C5 type.
38623 @@ -1965,8 +2086,8 @@
38624 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
38626 Ctrl2 |= PHY_B_1000C_RD;
38628 - /* Set Full/half duplex capabilities */
38630 + /* set Full/half duplex capabilities */
38631 switch (pPrt->PLinkMode) {
38632 case SK_LMODE_AUTOHALF:
38633 Ctrl2 |= PHY_B_1000C_AHD;
38634 @@ -1982,7 +2103,7 @@
38635 SKERR_HWI_E015MSG);
38638 - /* Set Flow-control capabilities */
38639 + /* set Flow-control capabilities */
38640 switch (pPrt->PFlowCtrlMode) {
38641 case SK_FLOW_MODE_NONE:
38642 Ctrl3 |= PHY_B_P_NO_PAUSE;
38643 @@ -2004,27 +2125,27 @@
38644 /* Restart Auto-negotiation */
38645 Ctrl1 |= PHY_CT_ANE | PHY_CT_RE_CFG;
38649 /* Initialize LED register here? */
38650 /* No. Please do it in SkDgXmitLed() (if required) and swap
38651 - init order of LEDs and XMAC. (MAl) */
38653 + init order of LEDs and XMAC. (MAl) */
38655 /* Write 1000Base-T Control Register */
38656 SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_1000T_CTRL, Ctrl2);
38657 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38658 - ("Set 1000B-T Ctrl Reg=0x%04X\n", Ctrl2));
38660 + ("Set 1000B-T Ctrl Reg = 0x%04X\n", Ctrl2));
38662 /* Write AutoNeg Advertisement Register */
38663 SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUNE_ADV, Ctrl3);
38664 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38665 - ("Set Auto-Neg.Adv.Reg=0x%04X\n", Ctrl3));
38667 + ("Set Auto-Neg.Adv.Reg = 0x%04X\n", Ctrl3));
38670 - /* Set the Phy Loopback bit, too */
38671 + /* set the PHY Loopback bit, too */
38672 Ctrl1 |= PHY_CT_LOOP;
38675 - if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
38676 + if (pPrt->PPortUsage == SK_JUMBO_LINK) {
38677 /* configure FIFO to high latency for transmission of ext. packets */
38678 Ctrl4 |= PHY_B_PEC_HIGH_LA;
38680 @@ -2036,20 +2157,553 @@
38682 /* Configure LED Traffic Mode and Jumbo Frame usage if specified */
38683 SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_P_EXT_CTRL, Ctrl4);
38685 - /* Write to the Phy control register */
38687 + /* Write to the PHY control register */
38688 SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_CTRL, Ctrl1);
38689 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38690 - ("PHY Control Reg=0x%04X\n", Ctrl1));
38691 + ("PHY Control Reg = 0x%04X\n", Ctrl1));
38692 } /* SkXmInitPhyBcom */
38693 #endif /* GENESIS */
38697 +#ifdef SK_PHY_LP_MODE
38698 +/******************************************************************************
38700 + * SkGmEnterLowPowerMode()
38703 + * This function sets the Marvell Alaska PHY to the low power mode
38704 + * given by parameter mode.
38705 + * The following low power modes are available:
38707 + * - COMA Mode (Deep Sleep):
38708 + * The PHY cannot wake up on its own.
38710 + * - IEEE 22.2.4.1.5 compatible power down mode
38711 + * The PHY cannot wake up on its own.
38713 + * - energy detect mode
38714 + * The PHY can wake up on its own by detecting activity
38715 + * on the CAT 5 cable.
38717 + * - energy detect plus mode
38718 + * The PHY can wake up on its own by detecting activity
38719 + * on the CAT 5 cable.
38720 + * Connected devices can be woken up by sending normal link
38721 + * pulses every second.
38729 +int SkGmEnterLowPowerMode(
38730 +SK_AC *pAC, /* Adapter Context */
38731 +SK_IOC IoC, /* I/O Context */
38732 +int Port, /* Port Index (e.g. MAC_1) */
38733 +SK_U8 Mode) /* low power mode */
38740 + SK_U32 PowerDownBit;
38744 + if (!(CHIP_ID_YUKON_2(pAC) || (pAC->GIni.GIYukonLite &&
38745 + pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3))) {
38750 + /* save current power mode */
38751 + LastMode = pAC->GIni.GP[Port].PPhyPowerState;
38752 + pAC->GIni.GP[Port].PPhyPowerState = Mode;
38754 + ChipId = pAC->GIni.GIChipId;
38756 + SK_DBG_MSG(pAC, SK_DBGMOD_POWM, SK_DBGCAT_CTRL,
38757 + ("SkGmEnterLowPowerMode: %u\n", Mode));
38759 + /* release GPHY Control reset */
38760 + SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_CLR);
38762 + /* release GMAC reset */
38763 + SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_CLR);
38765 + if (ChipId == CHIP_ID_YUKON_EC_U) {
38766 + /* select page 2 to access MAC control register */
38767 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 2);
38769 + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
38770 + /* allow GMII Power Down */
38771 + Word &= ~PHY_M_MAC_GMIF_PUP;
38772 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
38774 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0);
38778 + /* COMA mode (deep sleep) */
38779 + case PHY_PM_DEEP_SLEEP:
38780 + /* setup General Purpose Control Register */
38781 + GM_OUT16(IoC, Port, GM_GP_CTRL, GM_GPCR_FL_PASS |
38782 + GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
38784 + if (CHIP_ID_YUKON_2(pAC)) {
38785 + /* set power down bit */
38786 + PowerDownBit = (Port == MAC_1) ? PCI_Y2_PHY1_POWD :
38787 + PCI_Y2_PHY2_POWD;
38789 + if (ChipId != CHIP_ID_YUKON_EC) {
38791 + if (ChipId == CHIP_ID_YUKON_EC_U) {
38793 + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
38794 + /* enable Power Down */
38795 + Word |= PHY_M_PC_POW_D_ENA;
38796 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
38799 + /* set IEEE compatible Power Down Mode (dev. #4.99) */
38800 + Ret = SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PHY_CT_PDOWN);
38804 + /* apply COMA mode workaround for Yukon-Plus*/
38805 + (void)SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_ADDR, 0x001f);
38807 + Ret = SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xfff3);
38809 + PowerDownBit = PCI_PHY_COMA;
38812 + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
38814 + SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_1), &DWord);
38816 + /* set PHY to PowerDown/COMA Mode */
38817 + SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_1), DWord | PowerDownBit);
38819 + /* check if this routine was called from a for() loop */
38820 + if (CHIP_ID_YUKON_2(pAC) &&
38821 + (pAC->GIni.GIMacsFound == 1 || Port == MAC_2)) {
38823 + /* ASF system clock stopped */
38824 + SK_OUT8(IoC, B28_Y2_ASF_STAT_CMD, (SK_U8)Y2_ASF_CLK_HALT);
38826 + if (ChipId == CHIP_ID_YUKON_EC_U) {
38827 + /* set GPHY Control reset */
38828 + SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_SET);
38830 + /* additional power saving measurements */
38831 + SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_4), &DWord);
38833 + /* set gating core clock for LTSSM in L1 state */
38834 + DWord |= (P_PEX_LTSSM_STAT(P_PEX_LTSSM_L1_STAT) |
38835 + /* auto clock gated scheme controlled by CLKREQ */
38836 + P_ASPM_A1_MODE_SELECT |
38837 + /* enable Gate Root Core Clock */
38838 + P_CLK_GATE_ROOT_COR_ENA);
38840 + if (HW_FEATURE(pAC, HWF_WA_DEV_4200)) {
38841 + /* enable Clock Power Management (CLKREQ) */
38842 + SK_IN16(IoC, PCI_C(pAC, PEX_LNK_CTRL), &Word);
38843 + Word |= PEX_LC_CLK_PM_ENA;
38844 + SK_OUT16(IoC, PCI_C(pAC, PEX_LNK_CTRL), Word);
38847 + /* force CLKREQ Enable in Our4 (A1b only) */
38848 + DWord |= P_ASPM_FORCE_CLKREQ_ENA;
38851 + SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_4), DWord);
38853 + /* set Mask Register for Release/Gate Clock */
38854 + SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_5),
38855 + P_REL_PCIE_EXIT_L1_ST | P_GAT_PCIE_ENTER_L1_ST |
38856 + P_REL_PCIE_RX_EX_IDLE | P_GAT_PCIE_RX_EL_IDLE |
38857 + P_REL_GPHY_LINK_UP | P_GAT_GPHY_LINK_DOWN);
38860 + if (HW_FEATURE(pAC, HWF_RED_CORE_CLK_SUP)) {
38861 + /* divide clock by 4 only for Yukon-EC */
38862 + ClkDiv = (ChipId == CHIP_ID_YUKON_EC) ? 1 : 0;
38864 + /* on Yukon-2 clock select value is 31 */
38865 + DWord = (ChipId == CHIP_ID_YUKON_XL) ?
38866 + (Y2_CLK_DIV_VAL_2(0) | Y2_CLK_SEL_VAL_2(31)) :
38867 + Y2_CLK_DIV_VAL(ClkDiv);
38869 + /* check for Yukon-2 dual port PCI-Express adapter */
38870 + if (!(pAC->GIni.GIMacsFound == 2 &&
38871 + pAC->GIni.GIPciBus == SK_PEX_BUS)) {
38872 + /* enable Core Clock Division */
38873 + DWord |= Y2_CLK_DIV_ENA;
38876 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38877 + ("Set Core Clock: 0x%08X\n", DWord));
38879 + /* reduce Core Clock Frequency */
38880 + SK_OUT32(IoC, B2_Y2_CLK_CTRL, DWord);
38883 + if (HW_FEATURE(pAC, HWF_CLK_GATING_ENABLE)) {
38884 + /* check for Yukon-2 Rev. A2 */
38885 + if (ChipId == CHIP_ID_YUKON_XL &&
38886 + pAC->GIni.GIChipRev > CHIP_REV_YU_XL_A1) {
38887 + /* enable bits are inverted */
38891 + Byte = (SK_U8)(Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
38892 + Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
38893 + Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
38896 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38897 + ("Set Clock Gating: 0x%02X\n", Byte));
38899 + /* disable MAC/PHY, PCI and Core Clock for both Links */
38900 + SK_OUT8(IoC, B2_Y2_CLK_GATE, Byte);
38903 + if (pAC->GIni.GIVauxAvail) {
38904 + /* switch power to VAUX */
38905 + SK_OUT8(IoC, B0_POWER_CTRL, (SK_U8)(PC_VAUX_ENA | PC_VCC_ENA |
38906 + PC_VAUX_ON | PC_VCC_OFF));
38909 + SK_IN32(IoC, B0_CTST, &DWord);
38911 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38912 + ("Ctrl/Stat & Switch: 0x%08x\n", DWord));
38913 +#endif /* DEBUG */
38915 + if (pAC->GIni.GILevel != SK_INIT_IO &&
38916 + pAC->GIni.GIMacsFound == 1 &&
38917 + pAC->GIni.GIPciBus == SK_PEX_BUS) {
38919 + if (ChipId == CHIP_ID_YUKON_EC_U) {
38921 +#ifdef PCI_E_L1_STATE
38922 + SK_IN16(IoC, PCI_C(pAC, PCI_OUR_REG_1), &Word);
38923 + /* force to PCIe L1 */
38924 + Word |= (SK_U16)PCI_FORCE_PEX_L1;
38925 + SK_OUT16(IoC, PCI_C(pAC, PCI_OUR_REG_1), Word);
38926 +#endif /* PCI_E_L1_STATE */
38929 + /* switch to D1 state */
38930 + SK_OUT8(IoC, PCI_C(pAC, PCI_PM_CTL_STS), PCI_PM_STATE_D1);
38937 + /* IEEE 22.2.4.1.5 compatible power down mode */
38938 + case PHY_PM_IEEE_POWER_DOWN:
38940 + if (!CHIP_ID_YUKON_2(pAC) && !pAC->GIni.GIYukonLite) {
38942 + Ret = SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
38944 + /* disable MAC 125 MHz clock */
38945 + Word |= PHY_M_PC_DIS_125CLK;
38946 + Word &= ~PHY_M_PC_MAC_POW_UP;
38948 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
38950 + /* these register changes must be followed by a software reset */
38951 + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word);
38953 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word | PHY_CT_RESET);
38956 + /* switch IEEE compatible power down mode on */
38957 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PHY_CT_PDOWN);
38961 + /* energy detect and energy detect plus mode */
38962 + case PHY_PM_ENERGY_DETECT:
38963 + case PHY_PM_ENERGY_DETECT_PLUS:
38965 + Ret = SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
38968 + /* disable Polarity Reversal */
38969 + Word |= PHY_M_PC_POL_R_DIS;
38972 + if (!CHIP_ID_YUKON_2(pAC)) {
38973 + /* disable MAC 125 MHz clock */
38974 + Word |= PHY_M_PC_DIS_125CLK;
38977 + if (ChipId == CHIP_ID_YUKON_FE) {
38978 + /* enable Energy Detect (sense & pulse) */
38979 + Word |= PHY_M_PC_ENA_ENE_DT;
38982 + /* clear energy detect mode bits */
38983 + Word &= ~PHY_M_PC_EN_DET_MSK;
38985 + Word |= (Mode == PHY_PM_ENERGY_DETECT) ? PHY_M_PC_EN_DET :
38986 + PHY_M_PC_EN_DET_PLUS;
38989 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
38991 + /* these register changes must be followed by a software reset */
38992 + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word);
38993 + Word |= PHY_CT_RESET;
38994 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word);
38996 + if (ChipId == CHIP_ID_YUKON_EC_U) {
38997 + /* additional power saving measurements */
38998 + SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_4), &DWord);
39000 + /* set gating core clock for LTSSM in L1 state */
39001 + DWord |= (P_PEX_LTSSM_STAT(P_PEX_LTSSM_L1_STAT) |
39002 + /* auto clock gated scheme controlled by CLKREQ */
39003 + P_ASPM_A1_MODE_SELECT |
39004 + /* Enable Gate Root Core Clock */
39005 + P_CLK_GATE_ROOT_COR_ENA);
39007 + if (HW_FEATURE(pAC, HWF_WA_DEV_4200)) {
39008 + /* enable Clock Power Management (CLKREQ) */
39009 + SK_IN16(IoC, PCI_C(pAC, PEX_LNK_CTRL), &Word);
39010 + Word |= PEX_LC_CLK_PM_ENA;
39011 + SK_OUT16(IoC, PCI_C(pAC, PEX_LNK_CTRL), Word);
39014 + /* force CLKREQ Enable in Our4 (A1b only) */
39015 + DWord |= P_ASPM_FORCE_CLKREQ_ENA;
39018 + SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_4), DWord);
39020 + /* set Mask Register for Release/Gate Clock */
39021 + SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_5),
39022 + P_REL_PCIE_EXIT_L1_ST | P_GAT_PCIE_ENTER_L1_ST |
39023 + P_REL_PCIE_RX_EX_IDLE | P_GAT_PCIE_RX_EL_IDLE |
39024 + P_REL_GPHY_LINK_UP | P_GAT_GPHY_LINK_DOWN);
39026 +#ifdef PCI_E_L1_STATE
39027 + SK_IN16(IoC, PCI_C(pAC, PCI_OUR_REG_1), &Word);
39028 + /* enable PCIe L1 on GPHY link down */
39029 + Word |= (SK_U16)PCI_ENA_GPHY_LNK;
39030 + SK_OUT16(IoC, PCI_C(pAC, PCI_OUR_REG_1), Word);
39031 +#endif /* PCI_E_L1_STATE */
39036 + /* don't change current power mode */
39038 + pAC->GIni.GP[Port].PPhyPowerState = LastMode;
39044 +} /* SkGmEnterLowPowerMode */
39046 +/******************************************************************************
39048 + * SkGmLeaveLowPowerMode()
39051 + * Leave the current low power mode and switch to normal mode
39059 +int SkGmLeaveLowPowerMode(
39060 +SK_AC *pAC, /* Adapter Context */
39061 +SK_IOC IoC, /* I/O Context */
39062 +int Port) /* Port Index (e.g. MAC_1) */
39065 + SK_U32 PowerDownBit;
39071 + if (!(CHIP_ID_YUKON_2(pAC) || (pAC->GIni.GIYukonLite &&
39072 + pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3))) {
39077 + /* save current power mode */
39078 + LastMode = pAC->GIni.GP[Port].PPhyPowerState;
39079 + pAC->GIni.GP[Port].PPhyPowerState = PHY_PM_OPERATIONAL_MODE;
39081 + ChipId = pAC->GIni.GIChipId;
39083 + SK_DBG_MSG(pAC, SK_DBGMOD_POWM, SK_DBGCAT_CTRL,
39084 + ("SkGmLeaveLowPowerMode: %u\n", LastMode));
39086 + switch (LastMode) {
39087 + /* COMA mode (deep sleep) */
39088 + case PHY_PM_DEEP_SLEEP:
39090 + if (ChipId == CHIP_ID_YUKON_EC_U) {
39091 +#ifdef PCI_E_L1_STATE
39092 + /* set to default value (leave PCIe L1) */
39093 + SkPciWriteCfgWord(pAC, PCI_OUR_REG_1, 0);
39094 +#endif /* PCI_E_L1_STATE */
39096 + SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_4), &DWord);
39098 + DWord &= P_ASPM_CONTROL_MSK;
39099 + /* set all bits to 0 except bits 15..12 */
39100 + SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_4), DWord);
39102 + /* set to default value */
39103 + SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_5), 0);
39106 + SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &Word);
39108 + /* reset all DState bits */
39109 + Word &= ~PCI_PM_STATE_MSK;
39111 + /* switch to D0 state */
39112 + SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, Word);
39115 + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
39117 + if (CHIP_ID_YUKON_2(pAC)) {
39118 + /* disable Core Clock Division */
39119 + SK_OUT32(IoC, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
39121 + /* set power down bit */
39122 + PowerDownBit = (Port == MAC_1) ? PCI_Y2_PHY1_POWD :
39123 + PCI_Y2_PHY2_POWD;
39126 + PowerDownBit = PCI_PHY_COMA;
39129 + SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_1), &DWord);
39131 + /* Release PHY from PowerDown/COMA Mode */
39132 + SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_1), DWord & ~PowerDownBit);
39134 + SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
39136 + if (CHIP_ID_YUKON_2(pAC)) {
39138 + if (ChipId == CHIP_ID_YUKON_FE) {
39139 + /* release IEEE compatible Power Down Mode */
39140 + Ret = SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PHY_CT_ANE);
39142 + else if (ChipId == CHIP_ID_YUKON_EC_U) {
39143 + /* release GPHY Control reset */
39144 + SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_CLR);
39148 + SK_IN32(IoC, B2_GP_IO, &DWord);
39150 + /* set to output */
39151 + DWord |= (GP_DIR_9 | GP_IO_9);
39153 + /* set PHY reset */
39154 + SK_OUT32(IoC, B2_GP_IO, DWord);
39156 + DWord &= ~GP_IO_9; /* clear PHY reset (active high) */
39158 + /* clear PHY reset */
39159 + SK_OUT32(IoC, B2_GP_IO, DWord);
39164 + /* IEEE 22.2.4.1.5 compatible power down mode */
39165 + case PHY_PM_IEEE_POWER_DOWN:
39167 + if (ChipId != CHIP_ID_YUKON_XL) {
39169 + Ret = SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
39170 + Word &= ~PHY_M_PC_DIS_125CLK; /* enable MAC 125 MHz clock */
39171 + Word |= PHY_M_PC_MAC_POW_UP; /* set MAC power up */
39172 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
39174 + /* these register changes must be followed by a software reset */
39175 + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word);
39176 + Word |= PHY_CT_RESET;
39177 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word);
39180 + /* switch IEEE compatible power down mode off */
39181 + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word);
39182 + Word &= ~PHY_CT_PDOWN;
39183 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word);
39187 + /* energy detect and energy detect plus mode */
39188 + case PHY_PM_ENERGY_DETECT:
39189 + case PHY_PM_ENERGY_DETECT_PLUS:
39191 + if (ChipId != CHIP_ID_YUKON_XL) {
39193 + Ret = SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
39195 + if (ChipId == CHIP_ID_YUKON_FE) {
39196 + /* disable Energy Detect */
39197 + Word &= ~PHY_M_PC_ENA_ENE_DT;
39200 + /* disable energy detect mode & enable MAC 125 MHz clock */
39201 + Word &= ~(PHY_M_PC_EN_DET_MSK | PHY_M_PC_DIS_125CLK);
39205 + /* enable Polarity Reversal */
39206 + Word &= ~PHY_M_PC_POL_R_DIS;
39209 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
39211 + /* these register changes must be followed by a software reset */
39212 + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word);
39213 + Word |= PHY_CT_RESET;
39214 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word);
39218 + /* don't change current power mode */
39220 + pAC->GIni.GP[Port].PPhyPowerState = LastMode;
39226 +} /* SkGmLeaveLowPowerMode */
39227 +#endif /* SK_PHY_LP_MODE */
39229 /******************************************************************************
39231 - * SkGmInitPhyMarv() - Initialize the Marvell Phy registers
39232 + * SkGmInitPhyMarv() - Initialize the Marvell PHY registers
39234 - * Description: initializes all the Marvell Phy registers
39235 + * Description: initializes all the Marvell PHY registers
39239 @@ -2057,107 +2711,246 @@
39242 static void SkGmInitPhyMarv(
39243 -SK_AC *pAC, /* adapter context */
39244 -SK_IOC IoC, /* IO context */
39245 +SK_AC *pAC, /* Adapter Context */
39246 +SK_IOC IoC, /* I/O Context */
39247 int Port, /* Port Index (MAC_1 + n) */
39248 -SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */
39249 +SK_BOOL DoLoop) /* Should a PHY LoopBack be set-up? */
39263 + SK_U16 LoopSpeed;
39264 +#endif /* !SK_SLIM */
39266 + SK_U16 BlinkCtrl;
39273 +#endif /* !SK_DIAG */
39274 #if defined(SK_DIAG) || defined(DEBUG)
39277 SK_U16 PhySpecStat;
39278 #endif /* SK_DIAG || DEBUG */
39279 +#endif /* !VCPU */
39281 + /* set Pause On */
39282 + PauseMode = (SK_U8)GMC_PAUSE_ON;
39284 pPrt = &pAC->GIni.GP[Port];
39286 + ChipId = pAC->GIni.GIChipId;
39288 /* Auto-negotiation ? */
39289 - if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
39290 - AutoNeg = SK_FALSE;
39291 + AutoNeg = pPrt->PLinkMode != SK_LMODE_HALF &&
39292 + pPrt->PLinkMode != SK_LMODE_FULL;
39294 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39295 + ("InitPhyMarv: Port %d, Auto-neg. %s, LMode %d, LSpeed %d, FlowC %d\n",
39296 + Port, AutoNeg ? "ON" : "OFF",
39297 + pPrt->PLinkMode, pPrt->PLinkSpeed, pPrt->PFlowCtrlMode));
39300 + /* read Id from PHY */
39301 + if (SkGmPhyRead(pAC, IoC, Port, PHY_MARV_ID1, &pPrt->PhyId1) != 0) {
39304 + Para.Para64 = Port;
39305 + SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
39306 +#endif /* !SK_DIAG */
39311 - AutoNeg = SK_TRUE;
39313 + if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
39317 + /* special setup for PHY 88E1112 */
39318 + if (ChipId == CHIP_ID_YUKON_XL) {
39320 + LoopSpeed = pPrt->PLinkSpeed;
39322 + if (LoopSpeed == SK_LSPEED_AUTO) {
39323 + /* force 1000 Mbps */
39324 + LoopSpeed = SK_LSPEED_1000MBPS;
39328 + /* save page register */
39329 + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_ADR, &PageReg);
39331 + /* select page 2 to access MAC control register */
39332 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 2);
39334 + /* set MAC interface speed */
39335 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, LoopSpeed << 4);
39337 + /* restore page register */
39338 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, PageReg);
39340 + /* disable link pulses */
39341 + Word = PHY_M_PC_DIS_LINK_P;
39344 + /* set 'MAC Power up'-bit, set Manual MDI configuration */
39345 + Word = PHY_M_PC_MAC_POW_UP;
39348 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
39351 +#endif /* !SK_SLIM */
39352 + if (AutoNeg && pPrt->PLinkSpeed == SK_LSPEED_AUTO &&
39353 + !(ChipId == CHIP_ID_YUKON_XL || ChipId == CHIP_ID_YUKON_EC_U)) {
39354 + /* Read Ext. PHY Specific Control */
39355 + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl);
39357 + ExtPhyCtrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
39358 + PHY_M_EC_MAC_S_MSK);
39360 + ExtPhyCtrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
39362 + /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
39363 + if (pAC->GIni.GIYukonLite || ChipId == CHIP_ID_YUKON_EC) {
39364 + /* set downshift counter to 3x and enable downshift */
39365 + ExtPhyCtrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
39368 + /* set master & slave downshift counter to 1x */
39369 + ExtPhyCtrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
39372 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_CTRL, ExtPhyCtrl);
39373 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39374 + ("Set Ext. PHY Ctrl = 0x%04X\n", ExtPhyCtrl));
39378 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39379 - ("InitPhyMarv: Port %d, auto-negotiation %s\n",
39380 - Port, AutoNeg ? "ON" : "OFF"));
39383 - VCPUprintf(0, "SkGmInitPhyMarv(), Port=%u, DoLoop=%u\n",
39387 - /* Set 'MAC Power up'-bit, set Manual MDI configuration */
39388 - SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL,
39389 - PHY_M_PC_MAC_POW_UP);
39390 + if (CHIP_ID_YUKON_2(pAC)) {
39391 + /* Read PHY Specific Control */
39392 + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &PhyCtrl);
39394 + if (!DoLoop && pAC->GIni.GICopperType) {
39396 + if (ChipId == CHIP_ID_YUKON_FE) {
39397 + /* enable Automatic Crossover (!!! Bits 5..4) */
39398 + PhyCtrl |= (SK_U16)(PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1);
39402 + /* disable Energy Detect Mode */
39403 + PhyCtrl &= ~PHY_M_PC_EN_DET_MSK;
39404 +#endif /* !SK_DIAG */
39406 + /* enable Automatic Crossover */
39407 + PhyCtrl |= (SK_U16)PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
39409 + /* downshift on PHY 88E1112 and 88E1149 is changed */
39410 + if (AutoNeg && pPrt->PLinkSpeed == SK_LSPEED_AUTO &&
39411 + (ChipId == CHIP_ID_YUKON_XL ||
39412 + ChipId == CHIP_ID_YUKON_EC_U)) {
39413 + /* set downshift counter to 3x and enable downshift */
39414 + PhyCtrl &= ~PHY_M_PC_DSC_MSK;
39415 + PhyCtrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
39419 + /* workaround for deviation #4.88 (CRC errors) */
39421 + /* disable Automatic Crossover */
39422 + PhyCtrl &= ~PHY_M_PC_MDIX_MSK;
39425 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, PhyCtrl);
39427 - else if (AutoNeg && pPrt->PLinkSpeed == SK_LSPEED_AUTO) {
39428 - /* Read Ext. PHY Specific Control */
39429 - SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl);
39431 - ExtPhyCtrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
39432 - PHY_M_EC_MAC_S_MSK);
39434 - ExtPhyCtrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ) |
39435 - PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
39437 - SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_CTRL, ExtPhyCtrl);
39438 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39439 - ("Set Ext. PHY Ctrl=0x%04X\n", ExtPhyCtrl));
39441 + /* special setup for PHY 88E1112 Fiber */
39442 + if (ChipId == CHIP_ID_YUKON_XL && !pAC->GIni.GICopperType) {
39443 + /* select 1000BASE-X only mode in MAC Specific Ctrl Reg. */
39444 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 2);
39446 + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
39448 + Word &= ~PHY_M_MAC_MD_MSK;
39449 + Word |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
39451 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
39453 + /* select page 1 to access Fiber registers */
39454 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 1);
39456 + if (pAC->GIni.GIPmdTyp == 'P') {
39457 + /* for SFP-module set SIGDET polarity to low */
39458 + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
39460 + Word |= PHY_M_FIB_SIGD_POL;
39462 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
39466 /* Read PHY Control */
39467 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &PhyCtrl);
39470 - /* Disable Auto-negotiation */
39471 + /* disable Auto-negotiation */
39472 PhyCtrl &= ~PHY_CT_ANE;
39475 PhyCtrl |= PHY_CT_RESET;
39476 - /* Assert software reset */
39477 + /* assert software reset */
39478 SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PhyCtrl);
39480 +#endif /* !VCPU */
39482 PhyCtrl = 0 /* PHY_CT_COL_TST */;
39484 AutoNegAdv = PHY_SEL_TYPE;
39487 /* manually Master/Slave ? */
39488 if (pPrt->PMSMode != SK_MS_MODE_AUTO) {
39489 /* enable Manual Master/Slave */
39490 C1000BaseT |= PHY_M_1000C_MSE;
39493 if (pPrt->PMSMode == SK_MS_MODE_MASTER) {
39494 C1000BaseT |= PHY_M_1000C_MSC; /* set it to Master */
39498 +#endif /* !SK_SLIM */
39500 /* Auto-negotiation ? */
39504 if (pPrt->PLinkMode == SK_LMODE_FULL) {
39505 - /* Set Full Duplex Mode */
39506 + /* set Full Duplex Mode */
39507 PhyCtrl |= PHY_CT_DUP_MD;
39510 - /* Set Master/Slave manually if not already done */
39512 + /* set Master/Slave manually if not already done */
39513 if (pPrt->PMSMode == SK_MS_MODE_AUTO) {
39514 C1000BaseT |= PHY_M_1000C_MSE; /* set it to Slave */
39516 +#endif /* !SK_SLIM */
39520 switch (pPrt->PLinkSpeed) {
39521 case SK_LSPEED_AUTO:
39522 case SK_LSPEED_1000MBPS:
39523 - PhyCtrl |= PHY_CT_SP1000;
39524 + PhyCtrl |= (((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) ?
39525 + PHY_CT_SP1000 : PHY_CT_SP100);
39527 case SK_LSPEED_100MBPS:
39528 PhyCtrl |= PHY_CT_SP100;
39529 @@ -2169,38 +2962,66 @@
39530 SKERR_HWI_E019MSG);
39533 + if ((pPrt->PFlowCtrlMode == SK_FLOW_STAT_NONE) ||
39534 + /* disable Pause also for 10/100 Mbps in half duplex mode */
39535 + ((ChipId != CHIP_ID_YUKON_EC_U) &&
39536 + (pPrt->PLinkMode == SK_LMODE_HALF) &&
39537 + ((pPrt->PLinkSpeed == SK_LSPEED_STAT_100MBPS) ||
39538 + (pPrt->PLinkSpeed == SK_LSPEED_STAT_10MBPS)))) {
39540 + /* set Pause Off */
39541 + PauseMode = (SK_U8)GMC_PAUSE_OFF;
39544 + SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), PauseMode);
39547 + /* assert software reset */
39548 PhyCtrl |= PHY_CT_RESET;
39552 - /* Set Auto-negotiation advertisement */
39554 + /* set Auto-negotiation advertisement */
39556 if (pAC->GIni.GICopperType) {
39557 - /* Set Speed capabilities */
39558 + /* set Speed capabilities */
39559 switch (pPrt->PLinkSpeed) {
39560 case SK_LSPEED_AUTO:
39561 - C1000BaseT |= PHY_M_1000C_AHD | PHY_M_1000C_AFD;
39562 + if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
39563 + C1000BaseT |= PHY_M_1000C_AFD;
39565 + C1000BaseT |= PHY_M_1000C_AHD;
39566 +#endif /* SK_DIAG */
39568 AutoNegAdv |= PHY_M_AN_100_FD | PHY_M_AN_100_HD |
39569 PHY_M_AN_10_FD | PHY_M_AN_10_HD;
39571 case SK_LSPEED_1000MBPS:
39572 - C1000BaseT |= PHY_M_1000C_AHD | PHY_M_1000C_AFD;
39573 + if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
39574 + C1000BaseT |= PHY_M_1000C_AFD;
39576 + C1000BaseT |= PHY_M_1000C_AHD;
39577 +#endif /* SK_DIAG */
39580 case SK_LSPEED_100MBPS:
39581 - AutoNegAdv |= PHY_M_AN_100_FD | PHY_M_AN_100_HD |
39582 - /* advertise 10Base-T also */
39583 - PHY_M_AN_10_FD | PHY_M_AN_10_HD;
39584 + if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_100MBPS) != 0) {
39585 + AutoNegAdv |= PHY_M_AN_100_FD | PHY_M_AN_100_HD |
39586 + /* advertise 10Base-T also */
39587 + PHY_M_AN_10_FD | PHY_M_AN_10_HD;
39590 case SK_LSPEED_10MBPS:
39591 - AutoNegAdv |= PHY_M_AN_10_FD | PHY_M_AN_10_HD;
39592 + if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_10MBPS) != 0) {
39593 + AutoNegAdv |= PHY_M_AN_10_FD | PHY_M_AN_10_HD;
39597 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E019,
39598 SKERR_HWI_E019MSG);
39601 - /* Set Full/half duplex capabilities */
39602 + /* set Full/half duplex capabilities */
39603 switch (pPrt->PLinkMode) {
39604 case SK_LMODE_AUTOHALF:
39605 C1000BaseT &= ~PHY_M_1000C_AFD;
39606 @@ -2216,8 +3037,8 @@
39607 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E015,
39608 SKERR_HWI_E015MSG);
39611 - /* Set Flow-control capabilities */
39613 + /* set Flow-control capabilities */
39614 switch (pPrt->PFlowCtrlMode) {
39615 case SK_FLOW_MODE_NONE:
39616 AutoNegAdv |= PHY_B_P_NO_PAUSE;
39617 @@ -2236,9 +3057,9 @@
39618 SKERR_HWI_E016MSG);
39621 - else { /* special defines for FIBER (88E1011S only) */
39623 - /* Set Full/half duplex capabilities */
39624 + else { /* special defines for FIBER (88E1040S only) */
39626 + /* set Full/half duplex capabilities */
39627 switch (pPrt->PLinkMode) {
39628 case SK_LMODE_AUTOHALF:
39629 AutoNegAdv |= PHY_M_AN_1000X_AHD;
39630 @@ -2253,8 +3074,8 @@
39631 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E015,
39632 SKERR_HWI_E015MSG);
39635 - /* Set Flow-control capabilities */
39637 + /* set Flow-control capabilities */
39638 switch (pPrt->PFlowCtrlMode) {
39639 case SK_FLOW_MODE_NONE:
39640 AutoNegAdv |= PHY_M_P_NO_PAUSE_X;
39641 @@ -2279,138 +3100,247 @@
39642 PhyCtrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
39649 * E-mail from Gu Lin (08-03-2002):
39653 /* Program PHY register 30 as 16'h0708 for simulation speed up */
39654 SkGmPhyWrite(pAC, IoC, Port, 30, 0x0700 /* 0x0708 */);
39661 - /* Write 1000Base-T Control Register */
39662 - SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_1000T_CTRL, C1000BaseT);
39663 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39664 - ("Set 1000B-T Ctrl =0x%04X\n", C1000BaseT));
39668 + if (ChipId != CHIP_ID_YUKON_FE) {
39669 + /* Write 1000Base-T Control Register */
39670 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_1000T_CTRL, C1000BaseT);
39671 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39672 + ("Set 1000B-T Ctrl = 0x%04X\n", C1000BaseT));
39675 /* Write AutoNeg Advertisement Register */
39676 SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_AUNE_ADV, AutoNegAdv);
39677 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39678 - ("Set Auto-Neg.Adv.=0x%04X\n", AutoNegAdv));
39681 + ("Set Auto-Neg.Adv. = 0x%04X\n", AutoNegAdv));
39682 +#endif /* !VCPU */
39686 - /* Set the PHY Loopback bit */
39687 + /* set the PHY Loopback bit */
39688 PhyCtrl |= PHY_CT_LOOP;
39691 - /* Program PHY register 16 as 16'h0400 to force link good */
39692 - SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, PHY_M_PC_FL_GOOD);
39696 - if (pPrt->PLinkSpeed != SK_LSPEED_AUTO) {
39697 - /* Write Ext. PHY Specific Control */
39698 - SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_CTRL,
39699 - (SK_U16)((pPrt->PLinkSpeed + 2) << 4));
39704 - else if (pPrt->PLinkSpeed == SK_LSPEED_10MBPS) {
39705 - /* Write PHY Specific Control */
39706 - SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL,
39707 - PHY_M_PC_EN_DET_MSK);
39710 +#endif /* !SK_SLIM */
39712 /* Write to the PHY Control register */
39713 SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PhyCtrl);
39714 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39715 - ("Set PHY Ctrl Reg.=0x%04X\n", PhyCtrl));
39716 + ("Set PHY Ctrl Reg. = 0x%04X\n", PhyCtrl));
39723 + LedCtrl = PHY_M_LED_PULS_DUR(PULS_170MS);
39727 + BlinkCtrl = pAC->GIni.GILedBlinkCtrl;
39729 + if ((BlinkCtrl & SK_ACT_LED_BLINK) != 0) {
39731 + if (ChipId == CHIP_ID_YUKON_FE) {
39732 + /* on 88E3082 these bits are at 11..9 (shifted left) */
39733 + LedCtrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
39735 + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_FE_LED_PAR, &Word);
39737 + /* delete ACT LED control bits */
39738 + Word &= ~PHY_M_FELP_LED1_MSK;
39739 + /* change ACT LED control to blink mode */
39740 + Word |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
39742 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_FE_LED_PAR, Word);
39744 + else if (ChipId == CHIP_ID_YUKON_XL || ChipId == CHIP_ID_YUKON_EC_U) {
39745 + /* save page register */
39746 + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_ADR, &PageReg);
39748 + /* select page 3 to access LED control register */
39749 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 3);
39751 + LedConf = PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT (Yukon-2 only) */
39752 + PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
39753 + PHY_M_LEDC_STA0_CTRL(7); /* 1000 Mbps */
39755 - LedCtrl = PHY_M_LED_PULS_DUR(PULS_170MS) | PHY_M_LED_BLINK_RT(BLINK_84MS);
39756 + Mode = 7; /* 10 Mbps: On */
39758 - if ((pAC->GIni.GILedBlinkCtrl & SK_ACT_LED_BLINK) != 0) {
39759 - LedCtrl |= PHY_M_LEDC_RX_CTRL | PHY_M_LEDC_TX_CTRL;
39760 + if (ChipId == CHIP_ID_YUKON_XL) {
39761 + /* set Polarity Control register */
39762 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_STAT, (SK_U16)
39763 + (PHY_M_POLC_LS1_P_MIX(4) | PHY_M_POLC_IS0_P_MIX(4) |
39764 + PHY_M_POLC_LOS_CTRL(2) | PHY_M_POLC_INIT_CTRL(2) |
39765 + PHY_M_POLC_STA1_CTRL(2) | PHY_M_POLC_STA0_CTRL(2)));
39767 + else if (ChipId == CHIP_ID_YUKON_EC_U) {
39768 + /* check for LINK_LED mux */
39769 + if ((BlinkCtrl & SK_LED_LINK_MUX_P60) != 0) {
39771 + SK_IN16(pAC, GPHY_CTRL, &Word);
39773 + Word |= GPC_LED_CONF_VAL(4);
39775 + /* set GPHY LED Config */
39776 + SK_OUT16(pAC, GPHY_CTRL, Word);
39779 + Mode = 8; /* Forced Off */
39781 + /* set LED[5:4] Function Control and Polarity register */
39782 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_STAT, (SK_U16)
39783 + (PHY_M_LEDC_STA1_CTRL(1) | /* LED_ACT to Link/Act. */
39784 + PHY_M_LEDC_STA0_CTRL(6))); /* LED_DUP to Duplex */
39787 + /* set Blink Rate in LED Timer Control Register */
39788 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK,
39789 + LedCtrl | (SK_U16)PHY_M_LED_BLINK_RT(BLINK_84MS));
39792 + LedConf |= PHY_M_LEDC_INIT_CTRL(Mode);
39794 + /* set LED Function Control register */
39795 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, LedConf);
39797 +#if (defined(SK_DIAG) || (defined(DEBUG) && !defined(SK_SLIM)))
39798 + /* select page 6 to access Packet Generation register */
39799 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 6);
39801 + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &PhyCtrl);
39803 + PhyCtrl |= BIT_4S; /* enable CRC checker */
39805 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, PhyCtrl);
39806 +#endif /* SK_DIAG || (DEBUG && !SK_SLIM) */
39808 + /* restore page register */
39809 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, PageReg);
39812 + /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
39813 + LedCtrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
39815 + /* on PHY 88E1111 there is a change for LED control */
39816 + if (ChipId == CHIP_ID_YUKON_EC &&
39817 + (BlinkCtrl & SK_DUAL_LED_ACT_LNK) != 0) {
39818 + /* Yukon-EC needs setting of 2 bits: 0,6=11) */
39819 + LedCtrl |= PHY_M_LEDC_TX_C_LSB;
39821 + /* turn off the Rx LED (LED_RX) */
39822 + LedOver |= PHY_M_LED_MO_RX(MO_LED_OFF);
39826 - if ((pAC->GIni.GILedBlinkCtrl & SK_DUP_LED_NORMAL) != 0) {
39827 + if ((BlinkCtrl & SK_DUP_LED_NORMAL) != 0) {
39828 + /* disable blink mode (LED_DUPLEX) on collisions */
39829 LedCtrl |= PHY_M_LEDC_DP_CTRL;
39832 - SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_LED_CTRL, LedCtrl);
39834 - if ((pAC->GIni.GILedBlinkCtrl & SK_LED_LINK100_ON) != 0) {
39835 - /* only in forced 100 Mbps mode */
39836 - if (!AutoNeg && pPrt->PLinkSpeed == SK_LSPEED_100MBPS) {
39837 + if (ChipId == CHIP_ID_YUKON_EC_U) {
39838 + if (pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A1) {
39839 + /* apply fixes in PHY AFE */
39840 + SkGmPhyWrite(pAC, IoC, Port, 22, 255);
39841 + /* increase differential signal amplitude in 10BASE-T */
39842 + SkGmPhyWrite(pAC, IoC, Port, 24, 0xaa99);
39843 + SkGmPhyWrite(pAC, IoC, Port, 23, 0x2011);
39845 + /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
39846 + SkGmPhyWrite(pAC, IoC, Port, 24, 0xa204);
39847 + SkGmPhyWrite(pAC, IoC, Port, 23, 0x2002);
39849 + /* set page register to 0 */
39850 + SkGmPhyWrite(pAC, IoC, Port, 22, 0);
39854 + /* no effect on Yukon-XL */
39855 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_LED_CTRL, LedCtrl);
39858 + if ((BlinkCtrl & SK_LED_LINK100_ON) != 0) {
39859 + /* only in forced 100 Mbps mode */
39860 + if (!AutoNeg && pPrt->PLinkSpeed == SK_LSPEED_100MBPS) {
39861 + /* turn on 100 Mbps LED (LED_LINK100) */
39862 + LedOver |= PHY_M_LED_MO_100(MO_LED_ON);
39865 +#endif /* !SK_SLIM */
39867 - SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_LED_OVER,
39868 - PHY_M_LED_MO_100(MO_LED_ON));
39869 + if (LedOver != 0) {
39870 + /* set Manual LED Override */
39871 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_LED_OVER, LedOver);
39876 - c_print("Set PHY Ctrl=0x%04X\n", PhyCtrl);
39877 - c_print("Set 1000 B-T=0x%04X\n", C1000BaseT);
39878 - c_print("Set Auto-Neg=0x%04X\n", AutoNegAdv);
39879 - c_print("Set Ext Ctrl=0x%04X\n", ExtPhyCtrl);
39880 + c_print("Set PHY Ctrl = 0x%04X\n", PhyCtrl);
39881 + c_print("Set 1000 B-T = 0x%04X\n", C1000BaseT);
39882 + c_print("Set Auto-Neg = 0x%04X\n", AutoNegAdv);
39883 + c_print("Set Ext Ctrl = 0x%04X\n", ExtPhyCtrl);
39884 #endif /* SK_DIAG */
39886 -#if defined(SK_DIAG) || defined(DEBUG)
39887 +#if (defined(SK_DIAG) || (defined(DEBUG) && !defined(SK_SLIM)))
39888 /* Read PHY Control */
39889 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &PhyCtrl);
39890 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39891 - ("PHY Ctrl Reg.=0x%04X\n", PhyCtrl));
39893 - /* Read 1000Base-T Control Register */
39894 - SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_CTRL, &C1000BaseT);
39895 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39896 - ("1000B-T Ctrl =0x%04X\n", C1000BaseT));
39898 + ("PHY Ctrl Reg. = 0x%04X\n", PhyCtrl));
39900 /* Read AutoNeg Advertisement Register */
39901 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_ADV, &AutoNegAdv);
39902 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39903 - ("Auto-Neg.Adv.=0x%04X\n", AutoNegAdv));
39905 - /* Read Ext. PHY Specific Control */
39906 - SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl);
39907 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39908 - ("Ext. PHY Ctrl=0x%04X\n", ExtPhyCtrl));
39910 + ("Auto-Neg.Adv. = 0x%04X\n", AutoNegAdv));
39912 + if (ChipId != CHIP_ID_YUKON_FE) {
39913 + /* Read 1000Base-T Control Register */
39914 + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_CTRL, &C1000BaseT);
39915 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39916 + ("1000B-T Ctrl = 0x%04X\n", C1000BaseT));
39918 + /* Read Ext. PHY Specific Control */
39919 + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl);
39920 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39921 + ("Ext. PHY Ctrl = 0x%04X\n", ExtPhyCtrl));
39924 /* Read PHY Status */
39925 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_STAT, &PhyStat);
39926 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39927 - ("PHY Stat Reg.=0x%04X\n", PhyStat));
39928 + ("PHY Stat Reg. = 0x%04X\n", PhyStat));
39930 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_STAT, &PhyStat1);
39931 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39932 - ("PHY Stat Reg.=0x%04X\n", PhyStat1));
39934 + ("PHY Stat Reg. = 0x%04X\n", PhyStat1));
39936 /* Read PHY Specific Status */
39937 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &PhySpecStat);
39938 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39939 - ("PHY Spec Stat=0x%04X\n", PhySpecStat));
39940 -#endif /* SK_DIAG || DEBUG */
39941 + ("PHY Spec Stat = 0x%04X\n", PhySpecStat));
39942 +#endif /* SK_DIAG || (DEBUG && !SK_SLIM) */
39945 - c_print("PHY Ctrl Reg=0x%04X\n", PhyCtrl);
39946 - c_print("PHY 1000 Reg=0x%04X\n", C1000BaseT);
39947 - c_print("PHY AnAd Reg=0x%04X\n", AutoNegAdv);
39948 - c_print("Ext Ctrl Reg=0x%04X\n", ExtPhyCtrl);
39949 - c_print("PHY Stat Reg=0x%04X\n", PhyStat);
39950 - c_print("PHY Stat Reg=0x%04X\n", PhyStat1);
39951 - c_print("PHY Spec Reg=0x%04X\n", PhySpecStat);
39952 + c_print("PHY Ctrl Reg = 0x%04X\n", PhyCtrl);
39953 + c_print("PHY 1000 Reg = 0x%04X\n", C1000BaseT);
39954 + c_print("PHY AnAd Reg = 0x%04X\n", AutoNegAdv);
39955 + c_print("Ext Ctrl Reg = 0x%04X\n", ExtPhyCtrl);
39956 + c_print("PHY Stat Reg = 0x%04X\n", PhyStat);
39957 + c_print("PHY Stat Reg = 0x%04X\n", PhyStat1);
39958 + c_print("PHY Spec Reg = 0x%04X\n", PhySpecStat);
39959 #endif /* SK_DIAG */
39962 + /* enable PHY interrupts */
39963 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, (SK_U16)PHY_M_DEF_MSK);
39964 +#endif /* !VCPU */
39966 } /* SkGmInitPhyMarv */
39968 @@ -2419,9 +3349,9 @@
39970 /******************************************************************************
39972 - * SkXmInitPhyLone() - Initialize the Level One Phy registers
39973 + * SkXmInitPhyLone() - Initialize the Level One PHY registers
39975 - * Description: initializes all the Level One Phy registers
39976 + * Description: initializes all the Level One PHY registers
39980 @@ -2429,10 +3359,10 @@
39983 static void SkXmInitPhyLone(
39984 -SK_AC *pAC, /* adapter context */
39985 -SK_IOC IoC, /* IO context */
39986 +SK_AC *pAC, /* Adapter Context */
39987 +SK_IOC IoC, /* I/O Context */
39988 int Port, /* Port Index (MAC_1 + n) */
39989 -SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */
39990 +SK_BOOL DoLoop) /* Should a PHY LoopBack be set-up? */
39994 @@ -2448,11 +3378,12 @@
39995 /* manually Master/Slave ? */
39996 if (pPrt->PMSMode != SK_MS_MODE_AUTO) {
39997 Ctrl2 |= PHY_L_1000C_MSE;
40000 if (pPrt->PMSMode == SK_MS_MODE_MASTER) {
40001 Ctrl2 |= PHY_L_1000C_MSC;
40005 /* Auto-negotiation ? */
40006 if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
40008 @@ -2461,7 +3392,7 @@
40010 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40011 ("InitPhyLone: no auto-negotiation Port %d\n", Port));
40012 - /* Set DuplexMode in Config register */
40013 + /* set DuplexMode in Config register */
40014 if (pPrt->PLinkMode == SK_LMODE_FULL) {
40015 Ctrl1 |= PHY_CT_DUP_MD;
40017 @@ -2470,7 +3401,6 @@
40018 if (pPrt->PMSMode == SK_MS_MODE_AUTO) {
40019 Ctrl2 |= PHY_L_1000C_MSE; /* set it to Slave */
40023 * Do NOT enable Auto-negotiation here. This would hold
40024 * the link down because no IDLES are transmitted
40025 @@ -2479,9 +3409,9 @@
40027 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40028 ("InitPhyLone: with auto-negotiation Port %d\n", Port));
40029 - /* Set Auto-negotiation advertisement */
40030 + /* set Auto-negotiation advertisement */
40032 - /* Set Full/half duplex capabilities */
40033 + /* set Full/half duplex capabilities */
40034 switch (pPrt->PLinkMode) {
40035 case SK_LMODE_AUTOHALF:
40036 Ctrl2 |= PHY_L_1000C_AHD;
40037 @@ -2497,7 +3427,7 @@
40038 SKERR_HWI_E015MSG);
40041 - /* Set Flow-control capabilities */
40042 + /* set Flow-control capabilities */
40043 switch (pPrt->PFlowCtrlMode) {
40044 case SK_FLOW_MODE_NONE:
40045 Ctrl3 |= PHY_L_P_NO_PAUSE;
40046 @@ -2519,34 +3449,34 @@
40047 /* Restart Auto-negotiation */
40048 Ctrl1 = PHY_CT_ANE | PHY_CT_RE_CFG;
40052 /* Write 1000Base-T Control Register */
40053 SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_1000T_CTRL, Ctrl2);
40054 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40055 - ("1000B-T Ctrl Reg=0x%04X\n", Ctrl2));
40057 + ("1000B-T Ctrl Reg = 0x%04X\n", Ctrl2));
40059 /* Write AutoNeg Advertisement Register */
40060 SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_AUNE_ADV, Ctrl3);
40061 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40062 - ("Auto-Neg.Adv.Reg=0x%04X\n", Ctrl3));
40063 + ("Auto-Neg.Adv.Reg = 0x%04X\n", Ctrl3));
40066 - /* Set the Phy Loopback bit, too */
40067 + /* set the PHY Loopback bit, too */
40068 Ctrl1 |= PHY_CT_LOOP;
40071 - /* Write to the Phy control register */
40072 + /* Write to the PHY control register */
40073 SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_CTRL, Ctrl1);
40074 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40075 - ("PHY Control Reg=0x%04X\n", Ctrl1));
40076 + ("PHY Control Reg = 0x%04X\n", Ctrl1));
40077 } /* SkXmInitPhyLone */
40080 /******************************************************************************
40082 - * SkXmInitPhyNat() - Initialize the National Phy registers
40083 + * SkXmInitPhyNat() - Initialize the National PHY registers
40085 - * Description: initializes all the National Phy registers
40086 + * Description: initializes all the National PHY registers
40090 @@ -2554,10 +3484,10 @@
40093 static void SkXmInitPhyNat(
40094 -SK_AC *pAC, /* adapter context */
40095 -SK_IOC IoC, /* IO context */
40096 +SK_AC *pAC, /* Adapter Context */
40097 +SK_IOC IoC, /* I/O Context */
40098 int Port, /* Port Index (MAC_1 + n) */
40099 -SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */
40100 +SK_BOOL DoLoop) /* Should a PHY LoopBack be set-up? */
40102 /* todo: National */
40103 } /* SkXmInitPhyNat */
40104 @@ -2576,10 +3506,10 @@
40108 -SK_AC *pAC, /* adapter context */
40109 -SK_IOC IoC, /* IO context */
40110 +SK_AC *pAC, /* Adapter Context */
40111 +SK_IOC IoC, /* I/O Context */
40112 int Port, /* Port Index (MAC_1 + n) */
40113 -SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */
40114 +SK_BOOL DoLoop) /* Should a PHY LoopBack be set-up? */
40118 @@ -2587,7 +3517,7 @@
40121 if (pAC->GIni.GIGenesis) {
40124 switch (pPrt->PhyType) {
40126 SkXmInitPhyXmac(pAC, IoC, Port, DoLoop);
40127 @@ -2606,10 +3536,10 @@
40130 #endif /* GENESIS */
40134 if (pAC->GIni.GIYukon) {
40137 SkGmInitPhyMarv(pAC, IoC, Port, DoLoop);
40140 @@ -2627,17 +3557,17 @@
40144 - * SK_AND_DUP_CAP Duplex capability error happened
40145 - * SK_AND_OTHER Other error happened
40146 + * SK_AND_DUP_CAP Duplex capability error happened
40147 + * SK_AND_OTHER Other error happened
40149 static int SkXmAutoNegDoneXmac(
40150 -SK_AC *pAC, /* adapter context */
40151 -SK_IOC IoC, /* IO context */
40152 +SK_AC *pAC, /* Adapter Context */
40153 +SK_IOC IoC, /* I/O Context */
40154 int Port) /* Port Index (MAC_1 + n) */
40157 SK_U16 ResAb; /* Resolved Ability */
40158 - SK_U16 LPAb; /* Link Partner Ability */
40159 + SK_U16 LinkPartAb; /* Link Partner Ability */
40161 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40162 ("AutoNegDoneXmac, Port %d\n", Port));
40163 @@ -2645,15 +3575,15 @@
40164 pPrt = &pAC->GIni.GP[Port];
40166 /* Get PHY parameters */
40167 - SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_AUNE_LP, &LPAb);
40168 + SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_AUNE_LP, &LinkPartAb);
40169 SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_RES_ABI, &ResAb);
40171 - if ((LPAb & PHY_X_AN_RFB) != 0) {
40172 + if ((LinkPartAb & PHY_X_AN_RFB) != 0) {
40173 /* At least one of the remote fault bit is set */
40175 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40176 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
40177 ("AutoNegFail: Remote fault bit set Port %d\n", Port));
40178 pPrt->PAutoNegFail = SK_TRUE;
40180 return(SK_AND_OTHER);
40183 @@ -2666,9 +3596,10 @@
40187 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40188 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
40189 ("AutoNegFail: Duplex mode mismatch Port %d\n", Port));
40190 pPrt->PAutoNegFail = SK_TRUE;
40192 return(SK_AND_DUP_CAP);
40195 @@ -2676,25 +3607,26 @@
40196 /* We are NOT using chapter 4.23 of the Xaqti manual */
40197 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
40198 if ((pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYMMETRIC ||
40199 - pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM) &&
40200 - (LPAb & PHY_X_P_SYM_MD) != 0) {
40201 + pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM) &&
40202 + (LinkPartAb & PHY_X_P_SYM_MD) != 0) {
40203 /* Symmetric PAUSE */
40204 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC;
40206 else if (pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM &&
40207 - (LPAb & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD) {
40208 - /* Enable PAUSE receive, disable PAUSE transmit */
40209 + (LinkPartAb & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD) {
40210 + /* enable PAUSE receive, disable PAUSE transmit */
40211 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND;
40213 else if (pPrt->PFlowCtrlMode == SK_FLOW_MODE_LOC_SEND &&
40214 - (LPAb & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD) {
40215 - /* Disable PAUSE receive, enable PAUSE transmit */
40216 + (LinkPartAb & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD) {
40217 + /* disable PAUSE receive, enable PAUSE transmit */
40218 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND;
40221 /* PAUSE mismatch -> no PAUSE */
40222 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
40225 pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_1000MBPS;
40228 @@ -2710,41 +3642,39 @@
40232 - * SK_AND_DUP_CAP Duplex capability error happened
40233 - * SK_AND_OTHER Other error happened
40234 + * SK_AND_DUP_CAP Duplex capability error happened
40235 + * SK_AND_OTHER Other error happened
40237 static int SkXmAutoNegDoneBcom(
40238 -SK_AC *pAC, /* adapter context */
40239 -SK_IOC IoC, /* IO context */
40240 +SK_AC *pAC, /* Adapter Context */
40241 +SK_IOC IoC, /* I/O Context */
40242 int Port) /* Port Index (MAC_1 + n) */
40245 - SK_U16 LPAb; /* Link Partner Ability */
40246 - SK_U16 AuxStat; /* Auxiliary Status */
40249 -01-Sep-2000 RA;:;:
40250 SK_U16 ResAb; /* Resolved Ability */
40253 + SK_U16 LinkPartAb; /* Link Partner Ability */
40254 + SK_U16 AuxStat; /* Auxiliary Status */
40256 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40257 ("AutoNegDoneBcom, Port %d\n", Port));
40258 pPrt = &pAC->GIni.GP[Port];
40260 /* Get PHY parameters */
40261 - SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &LPAb);
40262 + SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &LinkPartAb);
40264 -01-Sep-2000 RA;:;:
40265 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &ResAb);
40270 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_STAT, &AuxStat);
40272 - if ((LPAb & PHY_B_AN_RF) != 0) {
40273 + if ((LinkPartAb & PHY_B_AN_RF) != 0) {
40274 /* Remote fault bit is set: Error */
40275 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40276 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
40277 ("AutoNegFail: Remote fault bit set Port %d\n", Port));
40278 pPrt->PAutoNegFail = SK_TRUE;
40280 return(SK_AND_OTHER);
40283 @@ -2757,26 +3687,26 @@
40287 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40288 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
40289 ("AutoNegFail: Duplex mode mismatch Port %d\n", Port));
40290 pPrt->PAutoNegFail = SK_TRUE;
40292 return(SK_AND_DUP_CAP);
40297 -01-Sep-2000 RA;:;:
40298 /* Check Master/Slave resolution */
40299 if ((ResAb & PHY_B_1000S_MSF) != 0) {
40300 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40301 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
40302 ("Master/Slave Fault Port %d\n", Port));
40303 pPrt->PAutoNegFail = SK_TRUE;
40304 pPrt->PMSStatus = SK_MS_STAT_FAULT;
40305 return(SK_AND_OTHER);
40309 pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
40310 SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE;
40314 /* Check PAUSE mismatch ??? */
40315 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
40316 @@ -2785,17 +3715,18 @@
40317 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC;
40319 else if ((AuxStat & PHY_B_AS_PAUSE_MSK) == PHY_B_AS_PRR) {
40320 - /* Enable PAUSE receive, disable PAUSE transmit */
40321 + /* enable PAUSE receive, disable PAUSE transmit */
40322 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND;
40324 else if ((AuxStat & PHY_B_AS_PAUSE_MSK) == PHY_B_AS_PRT) {
40325 - /* Disable PAUSE receive, enable PAUSE transmit */
40326 + /* disable PAUSE receive, enable PAUSE transmit */
40327 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND;
40330 /* PAUSE mismatch -> no PAUSE */
40331 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
40334 pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_1000MBPS;
40337 @@ -2813,99 +3744,182 @@
40341 - * SK_AND_DUP_CAP Duplex capability error happened
40342 - * SK_AND_OTHER Other error happened
40343 + * SK_AND_DUP_CAP Duplex capability error happened
40344 + * SK_AND_OTHER Other error happened
40346 static int SkGmAutoNegDoneMarv(
40347 -SK_AC *pAC, /* adapter context */
40348 -SK_IOC IoC, /* IO context */
40349 +SK_AC *pAC, /* Adapter Context */
40350 +SK_IOC IoC, /* I/O Context */
40351 int Port) /* Port Index (MAC_1 + n) */
40354 - SK_U16 LPAb; /* Link Partner Ability */
40355 SK_U16 ResAb; /* Resolved Ability */
40356 SK_U16 AuxStat; /* Auxiliary Status */
40357 + SK_U8 PauseMode; /* Pause Mode */
40359 + SK_U16 LinkPartAb; /* Link Partner Ability */
40362 +#endif /* !SK_DIAG */
40363 +#endif /* !SK_SLIM */
40365 + /* set Pause On */
40366 + PauseMode = (SK_U8)GMC_PAUSE_ON;
40368 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40369 ("AutoNegDoneMarv, Port %d\n", Port));
40371 pPrt = &pAC->GIni.GP[Port];
40374 /* Get PHY parameters */
40375 - SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_LP, &LPAb);
40376 + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_LP, &LinkPartAb);
40378 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40379 - ("Link P.Abil.=0x%04X\n", LPAb));
40381 - if ((LPAb & PHY_M_AN_RF) != 0) {
40382 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40383 + ("Link P.Abil. = 0x%04X\n", LinkPartAb));
40385 + if ((LinkPartAb & PHY_M_AN_RF) != 0) {
40386 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
40387 ("AutoNegFail: Remote fault bit set Port %d\n", Port));
40388 pPrt->PAutoNegFail = SK_TRUE;
40390 return(SK_AND_OTHER);
40393 - SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_STAT, &ResAb);
40395 - /* Check Master/Slave resolution */
40396 - if ((ResAb & PHY_B_1000S_MSF) != 0) {
40397 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40398 - ("Master/Slave Fault Port %d\n", Port));
40399 - pPrt->PAutoNegFail = SK_TRUE;
40400 - pPrt->PMSStatus = SK_MS_STAT_FAULT;
40401 - return(SK_AND_OTHER);
40402 + if (pAC->GIni.GICopperType) {
40403 + /* Read PHY Auto-Negotiation Expansion */
40404 + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_EXP, &LinkPartAb);
40406 + if ((LinkPartAb & PHY_ANE_LP_CAP) == 0) {
40409 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40410 + ("Link Partner not Auto-Neg. able, AN Exp.: 0x%04X\n",
40413 +#ifndef NDIS_MINIPORT_DRIVER
40414 + SK_ERR_LOG(pAC, SK_ERRCL_CONFIG, SKERR_HWI_E025, SKERR_HWI_E025MSG);
40417 + Para.Para64 = Port;
40418 + SkEventQueue(pAC, SKGE_DRV, SK_DRV_LIPA_NOT_AN_ABLE, Para);
40420 + c_print("Link Partner not Auto-Neg. able, AN Exp.: 0x%04X\n",
40422 +#endif /* !SK_DIAG */
40424 + if (HW_FEATURE(pAC, HWF_FORCE_AUTO_NEG) &&
40425 + pPrt->PLinkModeConf < SK_LMODE_AUTOHALF) {
40426 + /* set used link speed */
40427 + pPrt->PLinkSpeedUsed = pPrt->PLinkSpeed;
40429 + /* Set Link Mode Status */
40430 + pPrt->PLinkModeStatus = (pPrt->PLinkModeConf == SK_LMODE_FULL) ?
40431 + SK_LMODE_STAT_FULL : SK_LMODE_STAT_HALF;
40433 + return(SK_AND_OK);
40438 - pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
40439 - (SK_U8)SK_MS_STAT_MASTER : (SK_U8)SK_MS_STAT_SLAVE;
40441 +#endif /* !SK_SLIM */
40443 + if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
40445 + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_STAT, &ResAb);
40447 + /* Check Master/Slave resolution */
40448 + if ((ResAb & PHY_B_1000S_MSF) != 0) {
40449 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
40450 + ("Master/Slave Fault Port %d\n", Port));
40451 + pPrt->PAutoNegFail = SK_TRUE;
40452 + pPrt->PMSStatus = SK_MS_STAT_FAULT;
40453 + return(SK_AND_OTHER);
40456 + pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
40457 + (SK_U8)SK_MS_STAT_MASTER : (SK_U8)SK_MS_STAT_SLAVE;
40460 /* Read PHY Specific Status */
40461 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &AuxStat);
40464 /* Check Speed & Duplex resolved */
40465 if ((AuxStat & PHY_M_PS_SPDUP_RES) == 0) {
40466 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40467 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
40468 ("AutoNegFail: Speed & Duplex not resolved, Port %d\n", Port));
40469 pPrt->PAutoNegFail = SK_TRUE;
40470 pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN;
40472 return(SK_AND_DUP_CAP);
40475 - if ((AuxStat & PHY_M_PS_FULL_DUP) != 0) {
40476 - pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_AUTOFULL;
40479 - pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_AUTOHALF;
40482 - /* Check PAUSE mismatch ??? */
40483 - /* We are using IEEE 802.3z/D5.0 Table 37-4 */
40484 - if ((AuxStat & PHY_M_PS_PAUSE_MSK) == PHY_M_PS_PAUSE_MSK) {
40485 - /* Symmetric PAUSE */
40486 - pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC;
40488 - else if ((AuxStat & PHY_M_PS_PAUSE_MSK) == PHY_M_PS_RX_P_EN) {
40489 - /* Enable PAUSE receive, disable PAUSE transmit */
40490 - pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND;
40492 - else if ((AuxStat & PHY_M_PS_PAUSE_MSK) == PHY_M_PS_TX_P_EN) {
40493 - /* Disable PAUSE receive, enable PAUSE transmit */
40494 - pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND;
40496 + pPrt->PLinkModeStatus = (SK_U8)(((AuxStat & PHY_M_PS_FULL_DUP) != 0) ?
40497 + SK_LMODE_STAT_AUTOFULL : SK_LMODE_STAT_AUTOHALF);
40499 + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) {
40500 + /* set used link speed */
40501 + pPrt->PLinkSpeedUsed = (SK_U8)(((AuxStat & PHY_M_PS_SPEED_100) != 0) ?
40502 + SK_LSPEED_STAT_100MBPS : SK_LSPEED_STAT_10MBPS);
40505 - /* PAUSE mismatch -> no PAUSE */
40506 - pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
40507 + /* set used link speed */
40508 + switch ((unsigned)(AuxStat & PHY_M_PS_SPEED_MSK)) {
40509 + case (unsigned)PHY_M_PS_SPEED_1000:
40510 + pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_1000MBPS;
40512 + case PHY_M_PS_SPEED_100:
40513 + pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_100MBPS;
40516 + pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_10MBPS;
40519 + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL ||
40520 + pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) {
40521 + /* Tx & Rx Pause Enabled bits are at 9..8 */
40524 + if (!pAC->GIni.GICopperType) {
40525 + /* always 1000 Mbps on fiber */
40526 + pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_1000MBPS;
40530 + AuxStat &= PHY_M_PS_PAUSE_MSK;
40531 + /* We are using IEEE 802.3z/D5.0 Table 37-4 */
40532 + if (AuxStat == PHY_M_PS_PAUSE_MSK) {
40533 + /* Symmetric PAUSE */
40534 + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC;
40536 + else if (AuxStat == PHY_M_PS_RX_P_EN) {
40537 + /* enable PAUSE receive, disable PAUSE transmit */
40538 + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND;
40540 + else if (AuxStat == PHY_M_PS_TX_P_EN) {
40541 + /* disable PAUSE receive, enable PAUSE transmit */
40542 + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND;
40545 + /* PAUSE mismatch -> no PAUSE */
40546 + pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
40550 - /* set used link speed */
40551 - switch ((unsigned)(AuxStat & PHY_M_PS_SPEED_MSK)) {
40552 - case (unsigned)PHY_M_PS_SPEED_1000:
40553 - pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_1000MBPS;
40555 - case PHY_M_PS_SPEED_100:
40556 - pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_100MBPS;
40559 - pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_10MBPS;
40561 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40562 + ("LinkSpeedUsed = %d\n", pPrt->PLinkSpeedUsed));
40564 + if ((pPrt->PFlowCtrlStatus == SK_FLOW_STAT_NONE) ||
40565 + /* disable Pause also for 10/100 Mbps in half duplex mode */
40566 + ((pAC->GIni.GIChipId != CHIP_ID_YUKON_EC_U) &&
40567 + (pPrt->PLinkSpeedUsed < (SK_U8)SK_LSPEED_STAT_1000MBPS) &&
40568 + pPrt->PLinkModeStatus == (SK_U8)SK_LMODE_STAT_AUTOHALF)) {
40570 + /* set Pause Off */
40571 + PauseMode = (SK_U8)GMC_PAUSE_OFF;
40574 + SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), PauseMode);
40577 } /* SkGmAutoNegDoneMarv */
40579 @@ -2921,17 +3935,17 @@
40583 - * SK_AND_DUP_CAP Duplex capability error happened
40584 - * SK_AND_OTHER Other error happened
40585 + * SK_AND_DUP_CAP Duplex capability error happened
40586 + * SK_AND_OTHER Other error happened
40588 static int SkXmAutoNegDoneLone(
40589 -SK_AC *pAC, /* adapter context */
40590 -SK_IOC IoC, /* IO context */
40591 +SK_AC *pAC, /* Adapter Context */
40592 +SK_IOC IoC, /* I/O Context */
40593 int Port) /* Port Index (MAC_1 + n) */
40596 SK_U16 ResAb; /* Resolved Ability */
40597 - SK_U16 LPAb; /* Link Partner Ability */
40598 + SK_U16 LinkPartAb; /* Link Partner Ability */
40599 SK_U16 QuickStat; /* Auxiliary Status */
40601 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40602 @@ -2939,16 +3953,16 @@
40603 pPrt = &pAC->GIni.GP[Port];
40605 /* Get PHY parameters */
40606 - SkXmPhyRead(pAC, IoC, Port, PHY_LONE_AUNE_LP, &LPAb);
40607 + SkXmPhyRead(pAC, IoC, Port, PHY_LONE_AUNE_LP, &LinkPartAb);
40608 SkXmPhyRead(pAC, IoC, Port, PHY_LONE_1000T_STAT, &ResAb);
40609 SkXmPhyRead(pAC, IoC, Port, PHY_LONE_Q_STAT, &QuickStat);
40611 - if ((LPAb & PHY_L_AN_RF) != 0) {
40612 + if ((LinkPartAb & PHY_L_AN_RF) != 0) {
40613 /* Remote fault bit is set */
40615 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40616 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
40617 ("AutoNegFail: Remote fault bit set Port %d\n", Port));
40618 pPrt->PAutoNegFail = SK_TRUE;
40620 return(SK_AND_OTHER);
40623 @@ -2959,28 +3973,25 @@
40625 pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_AUTOHALF;
40629 /* Check Master/Slave resolution */
40630 if ((ResAb & PHY_L_1000S_MSF) != 0) {
40632 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40633 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
40634 ("Master/Slave Fault Port %d\n", Port));
40635 pPrt->PAutoNegFail = SK_TRUE;
40636 pPrt->PMSStatus = SK_MS_STAT_FAULT;
40637 return(SK_AND_OTHER);
40639 - else if (ResAb & PHY_L_1000S_MSR) {
40640 - pPrt->PMSStatus = SK_MS_STAT_MASTER;
40643 - pPrt->PMSStatus = SK_MS_STAT_SLAVE;
40646 + pPrt->PMSStatus = ((ResAb & PHY_L_1000S_MSR) != 0) ?
40647 + (SK_U8)SK_MS_STAT_MASTER : (SK_U8)SK_MS_STAT_SLAVE;
40649 /* Check PAUSE mismatch */
40650 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
40651 /* we must manually resolve the abilities here */
40652 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
40655 switch (pPrt->PFlowCtrlMode) {
40656 case SK_FLOW_MODE_NONE:
40658 @@ -2988,7 +3999,7 @@
40659 case SK_FLOW_MODE_LOC_SEND:
40660 if ((QuickStat & (PHY_L_QS_PAUSE | PHY_L_QS_AS_PAUSE)) ==
40661 (PHY_L_QS_PAUSE | PHY_L_QS_AS_PAUSE)) {
40662 - /* Disable PAUSE receive, enable PAUSE transmit */
40663 + /* disable PAUSE receive, enable PAUSE transmit */
40664 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND;
40667 @@ -3001,7 +4012,7 @@
40668 case SK_FLOW_MODE_SYM_OR_REM:
40669 if ((QuickStat & (PHY_L_QS_PAUSE | PHY_L_QS_AS_PAUSE)) ==
40670 PHY_L_QS_AS_PAUSE) {
40671 - /* Enable PAUSE receive, disable PAUSE transmit */
40672 + /* enable PAUSE receive, disable PAUSE transmit */
40673 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND;
40675 else if ((QuickStat & PHY_L_QS_PAUSE) != 0) {
40676 @@ -3013,103 +4024,238 @@
40677 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E016,
40678 SKERR_HWI_E016MSG);
40681 - return(SK_AND_OK);
40682 -} /* SkXmAutoNegDoneLone */
40684 + return(SK_AND_OK);
40685 +} /* SkXmAutoNegDoneLone */
40688 +/******************************************************************************
40690 + * SkXmAutoNegDoneNat() - Auto-negotiation handling
40693 + * This function handles the auto-negotiation if the Done bit is set.
40697 + * SK_AND_DUP_CAP Duplex capability error happened
40698 + * SK_AND_OTHER Other error happened
40700 +static int SkXmAutoNegDoneNat(
40701 +SK_AC *pAC, /* Adapter Context */
40702 +SK_IOC IoC, /* I/O Context */
40703 +int Port) /* Port Index (MAC_1 + n) */
40705 +/* todo: National */
40706 + return(SK_AND_OK);
40707 +} /* SkXmAutoNegDoneNat */
40708 +#endif /* OTHER_PHY */
40711 +/******************************************************************************
40713 + * SkMacAutoNegDone() - Auto-negotiation handling
40715 + * Description: calls the auto-negotiation done routines dep. on board type
40719 + * SK_AND_DUP_CAP Duplex capability error happened
40720 + * SK_AND_OTHER Other error happened
40722 +int SkMacAutoNegDone(
40723 +SK_AC *pAC, /* Adapter Context */
40724 +SK_IOC IoC, /* I/O Context */
40725 +int Port) /* Port Index (MAC_1 + n) */
40732 + pPrt = &pAC->GIni.GP[Port];
40735 + if (pAC->GIni.GIGenesis) {
40737 + switch (pPrt->PhyType) {
40739 + case SK_PHY_XMAC:
40740 + Rtv = SkXmAutoNegDoneXmac(pAC, IoC, Port);
40742 + case SK_PHY_BCOM:
40743 + Rtv = SkXmAutoNegDoneBcom(pAC, IoC, Port);
40746 + case SK_PHY_LONE:
40747 + Rtv = SkXmAutoNegDoneLone(pAC, IoC, Port);
40750 + Rtv = SkXmAutoNegDoneNat(pAC, IoC, Port);
40752 +#endif /* OTHER_PHY */
40754 + return(SK_AND_OTHER);
40757 +#endif /* GENESIS */
40760 + if (pAC->GIni.GIYukon) {
40762 + Rtv = SkGmAutoNegDoneMarv(pAC, IoC, Port);
40764 +#endif /* YUKON */
40766 + if (Rtv != SK_AND_OK) {
40770 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40771 + ("AutoNeg done Port %d\n", Port));
40773 + /* We checked everything and may now enable the link */
40774 + pPrt->PAutoNegFail = SK_FALSE;
40776 + SkMacRxTxEnable(pAC, IoC, Port);
40778 + return(SK_AND_OK);
40779 +} /* SkMacAutoNegDone */
40784 +/******************************************************************************
40786 + * SkXmSetRxTxEn() - Special Set Rx/Tx Enable and some features in XMAC
40789 + * sets MAC or PHY LoopBack and Duplex Mode in the MMU Command Reg.
40794 +static void SkXmSetRxTxEn(
40795 +SK_AC *pAC, /* Adapter Context */
40796 +SK_IOC IoC, /* I/O Context */
40797 +int Port, /* Port Index (MAC_1 + n) */
40798 +int Para) /* Parameter to set: MAC or PHY LoopBack, Duplex Mode */
40802 + XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
40804 + switch (Para & (SK_MAC_LOOPB_ON | SK_MAC_LOOPB_OFF)) {
40805 + case SK_MAC_LOOPB_ON:
40806 + Word |= XM_MMU_MAC_LB;
40808 + case SK_MAC_LOOPB_OFF:
40809 + Word &= ~XM_MMU_MAC_LB;
40813 + switch (Para & (SK_PHY_LOOPB_ON | SK_PHY_LOOPB_OFF)) {
40814 + case SK_PHY_LOOPB_ON:
40815 + Word |= XM_MMU_GMII_LOOP;
40817 + case SK_PHY_LOOPB_OFF:
40818 + Word &= ~XM_MMU_GMII_LOOP;
40822 + switch (Para & (SK_PHY_FULLD_ON | SK_PHY_FULLD_OFF)) {
40823 + case SK_PHY_FULLD_ON:
40824 + Word |= XM_MMU_GMII_FD;
40826 + case SK_PHY_FULLD_OFF:
40827 + Word &= ~XM_MMU_GMII_FD;
40831 + XM_OUT16(IoC, Port, XM_MMU_CMD, Word | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
40833 + /* dummy read to ensure writing */
40834 + XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
40836 +} /* SkXmSetRxTxEn */
40837 +#endif /* GENESIS */
40841 /******************************************************************************
40843 - * SkXmAutoNegDoneNat() - Auto-negotiation handling
40844 + * SkGmSetRxTxEn() - Special Set Rx/Tx Enable and some features in GMAC
40847 - * This function handles the auto-negotiation if the Done bit is set.
40848 + * sets MAC LoopBack and Duplex Mode in the General Purpose Control Reg.
40853 - * SK_AND_DUP_CAP Duplex capability error happened
40854 - * SK_AND_OTHER Other error happened
40857 -static int SkXmAutoNegDoneNat(
40858 -SK_AC *pAC, /* adapter context */
40859 -SK_IOC IoC, /* IO context */
40860 -int Port) /* Port Index (MAC_1 + n) */
40861 +static void SkGmSetRxTxEn(
40862 +SK_AC *pAC, /* Adapter Context */
40863 +SK_IOC IoC, /* I/O Context */
40864 +int Port, /* Port Index (MAC_1 + n) */
40865 +int Para) /* Parameter to set: MAC LoopBack, Duplex Mode */
40867 -/* todo: National */
40868 - return(SK_AND_OK);
40869 -} /* SkXmAutoNegDoneNat */
40870 -#endif /* OTHER_PHY */
40873 + GM_IN16(IoC, Port, GM_GP_CTRL, &Ctrl);
40875 + switch (Para & (SK_MAC_LOOPB_ON | SK_MAC_LOOPB_OFF)) {
40876 + case SK_MAC_LOOPB_ON:
40877 + Ctrl |= GM_GPCR_LOOP_ENA;
40879 + case SK_MAC_LOOPB_OFF:
40880 + Ctrl &= ~GM_GPCR_LOOP_ENA;
40884 + switch (Para & (SK_PHY_FULLD_ON | SK_PHY_FULLD_OFF)) {
40885 + case SK_PHY_FULLD_ON:
40886 + Ctrl |= GM_GPCR_DUP_FULL;
40888 + case SK_PHY_FULLD_OFF:
40889 + Ctrl &= ~GM_GPCR_DUP_FULL;
40893 + GM_OUT16(IoC, Port, GM_GP_CTRL, Ctrl | GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
40895 +} /* SkGmSetRxTxEn */
40896 +#endif /* YUKON */
40899 /******************************************************************************
40901 - * SkMacAutoNegDone() - Auto-negotiation handling
40902 + * SkMacSetRxTxEn() - Special Set Rx/Tx Enable and parameters
40904 - * Description: calls the auto-negotiation done routines dep. on board type
40905 + * Description: calls the Special Set Rx/Tx Enable routines dep. on board type
40909 - * SK_AND_DUP_CAP Duplex capability error happened
40910 - * SK_AND_OTHER Other error happened
40913 -int SkMacAutoNegDone(
40914 -SK_AC *pAC, /* adapter context */
40915 -SK_IOC IoC, /* IO context */
40916 -int Port) /* Port Index (MAC_1 + n) */
40917 +void SkMacSetRxTxEn(
40918 +SK_AC *pAC, /* Adapter Context */
40919 +SK_IOC IoC, /* I/O Context */
40920 +int Port, /* Port Index (MAC_1 + n) */
40928 - pPrt = &pAC->GIni.GP[Port];
40931 if (pAC->GIni.GIGenesis) {
40933 - switch (pPrt->PhyType) {
40935 - case SK_PHY_XMAC:
40936 - Rtv = SkXmAutoNegDoneXmac(pAC, IoC, Port);
40938 - case SK_PHY_BCOM:
40939 - Rtv = SkXmAutoNegDoneBcom(pAC, IoC, Port);
40942 - case SK_PHY_LONE:
40943 - Rtv = SkXmAutoNegDoneLone(pAC, IoC, Port);
40946 - Rtv = SkXmAutoNegDoneNat(pAC, IoC, Port);
40948 -#endif /* OTHER_PHY */
40950 - return(SK_AND_OTHER);
40953 + SkXmSetRxTxEn(pAC, IoC, Port, Para);
40955 #endif /* GENESIS */
40959 if (pAC->GIni.GIYukon) {
40961 - Rtv = SkGmAutoNegDoneMarv(pAC, IoC, Port);
40963 + SkGmSetRxTxEn(pAC, IoC, Port, Para);
40967 - if (Rtv != SK_AND_OK) {
40971 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40972 - ("AutoNeg done Port %d\n", Port));
40974 - /* We checked everything and may now enable the link */
40975 - pPrt->PAutoNegFail = SK_FALSE;
40977 - SkMacRxTxEnable(pAC, IoC, Port);
40979 - return(SK_AND_OK);
40980 -} /* SkMacAutoNegDone */
40981 +} /* SkMacSetRxTxEn */
40982 +#endif /* !SK_SLIM */
40985 /******************************************************************************
40986 @@ -3123,8 +4269,8 @@
40987 * != 0 Error happened
40989 int SkMacRxTxEnable(
40990 -SK_AC *pAC, /* adapter context */
40991 -SK_IOC IoC, /* IO context */
40992 +SK_AC *pAC, /* Adapter Context */
40993 +SK_IOC IoC, /* I/O Context */
40994 int Port) /* Port Index (MAC_1 + n) */
40997 @@ -3142,9 +4288,9 @@
41000 if ((pPrt->PLinkMode == SK_LMODE_AUTOHALF ||
41001 - pPrt->PLinkMode == SK_LMODE_AUTOFULL ||
41002 - pPrt->PLinkMode == SK_LMODE_AUTOBOTH) &&
41003 - pPrt->PAutoNegFail) {
41004 + pPrt->PLinkMode == SK_LMODE_AUTOFULL ||
41005 + pPrt->PLinkMode == SK_LMODE_AUTOBOTH) &&
41006 + pPrt->PAutoNegFail) {
41007 /* Auto-negotiation is not done or failed */
41010 @@ -3153,9 +4299,9 @@
41011 if (pAC->GIni.GIGenesis) {
41012 /* set Duplex Mode and Pause Mode */
41013 SkXmInitDupMd(pAC, IoC, Port);
41016 SkXmInitPauseMd(pAC, IoC, Port);
41020 * Initialize the Interrupt Mask Register. Default IRQs are...
41021 * - Link Asynchronous Event
41022 @@ -3171,23 +4317,24 @@
41023 /* add IRQ for Receive FIFO Overflow */
41024 IntMask &= ~XM_IS_RXF_OV;
41028 if (pPrt->PhyType != SK_PHY_XMAC) {
41029 /* disable GP0 interrupt bit */
41030 IntMask |= XM_IS_INP_ASS;
41033 XM_OUT16(IoC, Port, XM_IMSK, IntMask);
41036 /* get MMU Command Reg. */
41037 XM_IN16(IoC, Port, XM_MMU_CMD, &Reg);
41040 if (pPrt->PhyType != SK_PHY_XMAC &&
41041 (pPrt->PLinkModeStatus == SK_LMODE_STAT_FULL ||
41042 pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOFULL)) {
41043 /* set to Full Duplex */
41044 Reg |= XM_MMU_GMII_FD;
41048 switch (pPrt->PhyType) {
41051 @@ -3197,7 +4344,7 @@
41052 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &SWord);
41053 SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUX_CTRL,
41054 (SK_U16)(SWord & ~PHY_B_AC_DIS_PM));
41055 - SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_INT_MASK,
41056 + SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_INT_MASK,
41057 (SK_U16)PHY_B_DEF_MSK);
41060 @@ -3211,12 +4358,12 @@
41062 #endif /* OTHER_PHY */
41067 XM_OUT16(IoC, Port, XM_MMU_CMD, Reg | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
41069 #endif /* GENESIS */
41073 if (pAC->GIni.GIYukon) {
41075 @@ -3227,34 +4374,46 @@
41077 IntMask = GMAC_DEF_MSK;
41080 +#if (defined(DEBUG) || defined(YUK2)) && (!defined(SK_SLIM))
41081 /* add IRQ for Receive FIFO Overrun */
41082 IntMask |= GM_IS_RX_FF_OR;
41083 -#endif /* DEBUG */
41085 - SK_OUT8(IoC, GMAC_IRQ_MSK, (SK_U8)IntMask);
41089 + SK_OUT8(IoC, MR_ADDR(Port, GMAC_IRQ_MSK), (SK_U8)IntMask);
41091 /* get General Purpose Control */
41092 GM_IN16(IoC, Port, GM_GP_CTRL, &Reg);
41095 if (pPrt->PLinkModeStatus == SK_LMODE_STAT_FULL ||
41096 pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOFULL) {
41097 /* set to Full Duplex */
41098 Reg |= GM_GPCR_DUP_FULL;
41101 + if (HW_FEATURE(pAC, HWF_FORCE_AUTO_NEG) &&
41102 + pPrt->PLinkModeConf < SK_LMODE_AUTOHALF) {
41103 + /* disable auto-update for speed, duplex and flow-control */
41104 + Reg |= GM_GPCR_AU_ALL_DIS;
41106 +#endif /* !SK_SLIM */
41109 - /* enable Rx/Tx */
41110 - GM_OUT16(IoC, Port, GM_GP_CTRL, (SK_U16)(Reg | GM_GPCR_RX_ENA |
41111 - GM_GPCR_TX_ENA));
41114 - /* Enable all PHY interrupts */
41115 - SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK,
41116 - (SK_U16)PHY_M_DEF_MSK);
41118 + /* WA for dev. #4.209 */
41119 + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U &&
41120 + pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A1) {
41121 + /* enable/disable Store & Forward mode for TX */
41122 + SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_CTRL_T),
41123 + pPrt->PLinkSpeedUsed != (SK_U8)SK_LSPEED_STAT_1000MBPS ?
41124 + TX_STFW_ENA : TX_STFW_DIS);
41127 + /* enable Rx/Tx */
41128 + GM_OUT16(IoC, Port, GM_GP_CTRL, Reg | GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
41133 + pAC->GIni.GP[Port].PState = SK_PRT_RUN;
41137 } /* SkMacRxTxEnable */
41138 @@ -3270,33 +4429,33 @@
41140 void SkMacRxTxDisable(
41141 SK_AC *pAC, /* Adapter Context */
41142 -SK_IOC IoC, /* IO context */
41143 +SK_IOC IoC, /* I/O Context */
41144 int Port) /* Port Index (MAC_1 + n) */
41149 if (pAC->GIni.GIGenesis) {
41152 XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
41154 - XM_OUT16(IoC, Port, XM_MMU_CMD, Word & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
41157 + Word &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
41159 + XM_OUT16(IoC, Port, XM_MMU_CMD, Word);
41161 /* dummy read to ensure writing */
41162 XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
41164 #endif /* GENESIS */
41168 if (pAC->GIni.GIYukon) {
41171 GM_IN16(IoC, Port, GM_GP_CTRL, &Word);
41173 - GM_OUT16(IoC, Port, GM_GP_CTRL, (SK_U16)(Word & ~(GM_GPCR_RX_ENA |
41174 - GM_GPCR_TX_ENA)));
41175 + Word &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
41177 - /* dummy read to ensure writing */
41178 - GM_IN16(IoC, Port, GM_GP_CTRL, &Word);
41179 + GM_OUT16(IoC, Port, GM_GP_CTRL, Word);
41183 @@ -3313,7 +4472,7 @@
41185 void SkMacIrqDisable(
41186 SK_AC *pAC, /* Adapter Context */
41187 -SK_IOC IoC, /* IO context */
41188 +SK_IOC IoC, /* I/O Context */
41189 int Port) /* Port Index (MAC_1 + n) */
41192 @@ -3325,18 +4484,18 @@
41195 if (pAC->GIni.GIGenesis) {
41198 /* disable all XMAC IRQs */
41199 - XM_OUT16(IoC, Port, XM_IMSK, 0xffff);
41201 - /* Disable all PHY interrupts */
41202 + XM_OUT16(IoC, Port, XM_IMSK, 0xffff);
41204 + /* disable all PHY interrupts */
41205 switch (pPrt->PhyType) {
41207 /* Make sure that PHY is initialized */
41208 if (pPrt->PState != SK_PRT_RESET) {
41209 /* NOT allowed if BCOM is in RESET state */
41210 /* Workaround BCOM Errata (#10523) all BCom */
41211 - /* Disable Power Management if link is down */
41212 + /* disable Power Management if link is down */
41213 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &Word);
41214 SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUX_CTRL,
41215 (SK_U16)(Word | PHY_B_AC_DIS_PM));
41216 @@ -3355,16 +4514,16 @@
41219 #endif /* GENESIS */
41223 if (pAC->GIni.GIYukon) {
41224 /* disable all GMAC IRQs */
41225 - SK_OUT8(IoC, GMAC_IRQ_MSK, 0);
41227 + SK_OUT8(IoC, MR_ADDR(Port, GMAC_IRQ_MSK), 0);
41230 - /* Disable all PHY interrupts */
41231 + /* disable all PHY interrupts */
41232 SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, 0);
41234 +#endif /* !VCPU */
41238 @@ -3376,29 +4535,72 @@
41240 * SkXmSendCont() - Enable / Disable Send Continuous Mode
41242 - * Description: enable / disable Send Continuous Mode on XMAC
41243 + * Description: enable / disable Send Continuous Mode on XMAC resp.
41244 + * Packet Generation on GPHY
41250 -SK_AC *pAC, /* adapter context */
41251 -SK_IOC IoC, /* IO context */
41252 +SK_AC *pAC, /* Adapter Context */
41253 +SK_IOC IoC, /* I/O Context */
41254 int Port, /* Port Index (MAC_1 + n) */
41255 SK_BOOL Enable) /* Enable / Disable */
41261 - XM_IN32(IoC, Port, XM_MODE, &MdReg);
41262 + if (pAC->GIni.GIGenesis) {
41263 + XM_IN32(IoC, Port, XM_MODE, &MdReg);
41266 - MdReg |= XM_MD_TX_CONT;
41268 + MdReg |= XM_MD_TX_CONT;
41271 + MdReg &= ~XM_MD_TX_CONT;
41273 + /* setup Mode Register */
41274 + XM_OUT32(IoC, Port, XM_MODE, MdReg);
41277 - MdReg &= ~XM_MD_TX_CONT;
41278 + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) {
41279 + /* select page 18 */
41280 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_ADDR, 18);
41282 + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PAGE_DATA, &Reg);
41284 + Reg &= ~0x003c; /* clear bits 5..2 */
41287 + /* enable packet generation, 1518 byte length */
41288 + Reg |= (BIT_5S | BIT_3S);
41291 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, Reg);
41293 + else if (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL) {
41294 + /* save page register */
41295 + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_ADR, &Save);
41297 + /* select page 6 to access Packet Generation register */
41298 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 6);
41300 + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Reg);
41302 + Reg &= ~0x003f; /* clear bits 5..0 */
41305 + /* enable packet generation, 1518 byte length */
41306 + Reg |= (BIT_3S | BIT_1S);
41309 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Reg);
41311 + /* restore page register */
41312 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, Save);
41315 - /* setup Mode Register */
41316 - XM_OUT32(IoC, Port, XM_MODE, MdReg);
41318 } /* SkXmSendCont */
41320 @@ -3413,8 +4615,8 @@
41323 void SkMacTimeStamp(
41324 -SK_AC *pAC, /* adapter context */
41325 -SK_IOC IoC, /* IO context */
41326 +SK_AC *pAC, /* Adapter Context */
41327 +SK_IOC IoC, /* I/O Context */
41328 int Port, /* Port Index (MAC_1 + n) */
41329 SK_BOOL Enable) /* Enable / Disable */
41331 @@ -3459,8 +4661,8 @@
41334 void SkXmAutoNegLipaXmac(
41335 -SK_AC *pAC, /* adapter context */
41336 -SK_IOC IoC, /* IO context */
41337 +SK_AC *pAC, /* Adapter Context */
41338 +SK_IOC IoC, /* I/O Context */
41339 int Port, /* Port Index (MAC_1 + n) */
41340 SK_U16 IStatus) /* Interrupt Status word to analyse */
41342 @@ -3472,8 +4674,9 @@
41343 (IStatus & (XM_IS_LIPA_RC | XM_IS_RX_PAGE | XM_IS_AND)) != 0) {
41345 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
41346 - ("AutoNegLipa: AutoNeg detected on Port %d, IStatus=0x%04X\n",
41347 + ("AutoNegLipa: AutoNeg detected on Port %d, IStatus = 0x%04X\n",
41350 pPrt->PLipaAutoNeg = SK_LIPA_AUTO;
41352 } /* SkXmAutoNegLipaXmac */
41353 @@ -3489,8 +4692,8 @@
41356 void SkMacAutoNegLipaPhy(
41357 -SK_AC *pAC, /* adapter context */
41358 -SK_IOC IoC, /* IO context */
41359 +SK_AC *pAC, /* Adapter Context */
41360 +SK_IOC IoC, /* I/O Context */
41361 int Port, /* Port Index (MAC_1 + n) */
41362 SK_U16 PhyStat) /* PHY Status word to analyse */
41364 @@ -3502,8 +4705,9 @@
41365 (PhyStat & PHY_ST_AN_OVER) != 0) {
41367 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
41368 - ("AutoNegLipa: AutoNeg detected on Port %d, PhyStat=0x%04X\n",
41369 + ("AutoNegLipa: AutoNeg detected on Port %d, PhyStat = 0x%04X\n",
41372 pPrt->PLipaAutoNeg = SK_LIPA_AUTO;
41374 } /* SkMacAutoNegLipaPhy */
41375 @@ -3518,7 +4722,7 @@
41378 * With an external PHY, some interrupt bits are not meaningfull any more:
41379 - * - LinkAsyncEvent (bit #14) XM_IS_LNK_AE
41380 + * - LinkAsyncEvent (bit #14) XM_IS_LNK_AE
41381 * - LinkPartnerReqConfig (bit #10) XM_IS_LIPA_RC
41382 * - Page Received (bit #9) XM_IS_RX_PAGE
41383 * - NextPageLoadedForXmt (bit #8) XM_IS_TX_PAGE
41384 @@ -3530,22 +4734,23 @@
41387 static void SkXmIrq(
41388 -SK_AC *pAC, /* adapter context */
41389 -SK_IOC IoC, /* IO context */
41390 +SK_AC *pAC, /* Adapter Context */
41391 +SK_IOC IoC, /* I/O Context */
41392 int Port) /* Port Index (MAC_1 + n) */
41396 SK_U16 IStatus; /* Interrupt status read from the XMAC */
41399 - SK_U64 OverflowStatus;
41401 + SK_U64 OverflowStatus;
41404 +#endif /* SK_SLIM */
41406 pPrt = &pAC->GIni.GP[Port];
41409 XM_IN16(IoC, Port, XM_ISRC, &IStatus);
41412 /* LinkPartner Auto-negable? */
41413 if (pPrt->PhyType == SK_PHY_XMAC) {
41414 SkXmAutoNegLipaXmac(pAC, IoC, Port, IStatus);
41415 @@ -3556,7 +4761,7 @@
41416 XM_IS_RX_PAGE | XM_IS_TX_PAGE |
41417 XM_IS_AND | XM_IS_INP_ASS);
41421 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
41422 ("XmacIrq Port %d Isr 0x%04X\n", Port, IStatus));
41424 @@ -3666,49 +4871,55 @@
41427 static void SkGmIrq(
41428 -SK_AC *pAC, /* adapter context */
41429 -SK_IOC IoC, /* IO context */
41430 +SK_AC *pAC, /* Adapter Context */
41431 +SK_IOC IoC, /* I/O Context */
41432 int Port) /* Port Index (MAC_1 + n) */
41435 SK_U8 IStatus; /* Interrupt status */
41437 - SK_U64 OverflowStatus;
41438 + SK_U64 OverflowStatus;
41442 +#endif /* SK_SLIM */
41444 pPrt = &pAC->GIni.GP[Port];
41446 - SK_IN8(IoC, GMAC_IRQ_SRC, &IStatus);
41449 + SK_IN8(IoC, MR_ADDR(Port, GMAC_IRQ_SRC), &IStatus);
41452 /* LinkPartner Auto-negable? */
41453 SkMacAutoNegLipaPhy(pAC, IoC, Port, IStatus);
41457 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
41458 - ("GmacIrq Port %d Isr 0x%04X\n", Port, IStatus));
41459 + ("GmacIrq Port %d Isr 0x%02X\n", Port, IStatus));
41461 /* Combined Tx & Rx Counter Overflow SIRQ Event */
41462 if (IStatus & (GM_IS_RX_CO_OV | GM_IS_TX_CO_OV)) {
41463 /* these IRQs will be cleared by reading GMACs register */
41465 - SkGmOverflowStatus(pAC, IoC, Port, IStatus, &OverflowStatus);
41466 + SkGmOverflowStatus(pAC, IoC, Port, (SK_U16)IStatus, &OverflowStatus);
41468 Para.Para32[0] = (SK_U32)Port;
41469 Para.Para32[1] = (SK_U32)IStatus;
41470 SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_SIRQ_OVERFLOW, Para);
41472 +#endif /* SK_SLIM */
41476 if (IStatus & GM_IS_RX_FF_OR) {
41477 /* clear GMAC Rx FIFO Overrun IRQ */
41478 SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_CLI_RX_FO);
41480 + Para.Para64 = Port;
41481 + SkEventQueue(pAC, SKGE_DRV, SK_DRV_RX_OVERFLOW, Para);
41484 pPrt->PRxOverCnt++;
41487 +#endif /* !SK_SLIM */
41489 if (IStatus & GM_IS_TX_FF_UR) {
41490 /* clear GMAC Tx FIFO Underrun IRQ */
41491 @@ -3738,8 +4949,8 @@
41495 -SK_AC *pAC, /* adapter context */
41496 -SK_IOC IoC, /* IO context */
41497 +SK_AC *pAC, /* Adapter Context */
41498 +SK_IOC IoC, /* I/O Context */
41499 int Port) /* Port Index (MAC_1 + n) */
41502 @@ -3748,7 +4959,7 @@
41503 SkXmIrq(pAC, IoC, Port);
41505 #endif /* GENESIS */
41509 if (pAC->GIni.GIYukon) {
41510 /* IRQ from GMAC */
41511 @@ -3775,8 +4986,8 @@
41512 * 1: something went wrong
41514 int SkXmUpdateStats(
41515 -SK_AC *pAC, /* adapter context */
41516 -SK_IOC IoC, /* IO context */
41517 +SK_AC *pAC, /* Adapter Context */
41518 +SK_IOC IoC, /* I/O Context */
41519 unsigned int Port) /* Port Index (MAC_1 + n) */
41522 @@ -3798,7 +5009,7 @@
41525 XM_IN16(IoC, Port, XM_STAT_CMD, &StatReg);
41528 if (++WaitIndex > 10) {
41530 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E021, SKERR_HWI_E021MSG);
41531 @@ -3806,7 +5017,7 @@
41534 } while ((StatReg & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) != 0);
41538 } /* SkXmUpdateStats */
41540 @@ -3825,19 +5036,19 @@
41541 * 1: something went wrong
41543 int SkXmMacStatistic(
41544 -SK_AC *pAC, /* adapter context */
41545 -SK_IOC IoC, /* IO context */
41546 +SK_AC *pAC, /* Adapter Context */
41547 +SK_IOC IoC, /* I/O Context */
41548 unsigned int Port, /* Port Index (MAC_1 + n) */
41549 SK_U16 StatAddr, /* MIB counter base address */
41550 -SK_U32 SK_FAR *pVal) /* ptr to return statistic value */
41551 +SK_U32 SK_FAR *pVal) /* Pointer to return statistic value */
41553 if ((StatAddr < XM_TXF_OK) || (StatAddr > XM_RXF_MAX_SZ)) {
41556 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E022, SKERR_HWI_E022MSG);
41563 XM_IN32(IoC, Port, StatAddr, pVal);
41566 @@ -3856,12 +5067,12 @@
41567 * 1: something went wrong
41569 int SkXmResetCounter(
41570 -SK_AC *pAC, /* adapter context */
41571 -SK_IOC IoC, /* IO context */
41572 +SK_AC *pAC, /* Adapter Context */
41573 +SK_IOC IoC, /* I/O Context */
41574 unsigned int Port) /* Port Index (MAC_1 + n) */
41576 XM_OUT16(IoC, Port, XM_STAT_CMD, XM_SC_CLR_RXC | XM_SC_CLR_TXC);
41577 - /* Clear two times according to Errata #3 */
41578 + /* Clear two times according to XMAC Errata #3 */
41579 XM_OUT16(IoC, Port, XM_STAT_CMD, XM_SC_CLR_RXC | XM_SC_CLR_TXC);
41582 @@ -3888,11 +5099,11 @@
41583 * 1: something went wrong
41585 int SkXmOverflowStatus(
41586 -SK_AC *pAC, /* adapter context */
41587 -SK_IOC IoC, /* IO context */
41588 +SK_AC *pAC, /* Adapter Context */
41589 +SK_IOC IoC, /* I/O Context */
41590 unsigned int Port, /* Port Index (MAC_1 + n) */
41591 -SK_U16 IStatus, /* Interupt Status from MAC */
41592 -SK_U64 SK_FAR *pStatus) /* ptr for return overflow status value */
41593 +SK_U16 IStatus, /* Interrupt Status from MAC */
41594 +SK_U64 SK_FAR *pStatus) /* Pointer for return overflow status value */
41596 SK_U64 Status; /* Overflow status */
41598 @@ -3904,7 +5115,7 @@
41599 XM_IN32(IoC, Port, XM_RX_CNT_EV, &RegVal);
41600 Status |= (SK_U64)RegVal << 32;
41604 if ((IStatus & XM_IS_TXC_OV) != 0) {
41606 XM_IN32(IoC, Port, XM_TX_CNT_EV, &RegVal);
41607 @@ -3931,8 +5142,8 @@
41608 * 1: something went wrong
41610 int SkGmUpdateStats(
41611 -SK_AC *pAC, /* adapter context */
41612 -SK_IOC IoC, /* IO context */
41613 +SK_AC *pAC, /* Adapter Context */
41614 +SK_IOC IoC, /* I/O Context */
41615 unsigned int Port) /* Port Index (MAC_1 + n) */
41618 @@ -3953,24 +5164,27 @@
41619 * 1: something went wrong
41621 int SkGmMacStatistic(
41622 -SK_AC *pAC, /* adapter context */
41623 -SK_IOC IoC, /* IO context */
41624 +SK_AC *pAC, /* Adapter Context */
41625 +SK_IOC IoC, /* I/O Context */
41626 unsigned int Port, /* Port Index (MAC_1 + n) */
41627 SK_U16 StatAddr, /* MIB counter base address */
41628 -SK_U32 SK_FAR *pVal) /* ptr to return statistic value */
41629 +SK_U32 SK_FAR *pVal) /* Pointer to return statistic value */
41632 if ((StatAddr < GM_RXF_UC_OK) || (StatAddr > GM_TXE_FIFO_UR)) {
41635 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E022, SKERR_HWI_E022MSG);
41637 - SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
41639 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
41640 ("SkGmMacStat: wrong MIB counter 0x%04X\n", StatAddr));
41645 GM_IN32(IoC, Port, StatAddr, pVal);
41647 + /* dummy read after GM_IN32() */
41648 + SK_IN16(IoC, B0_RAP, &StatAddr);
41651 } /* SkGmMacStatistic */
41653 @@ -3987,11 +5201,11 @@
41654 * 1: something went wrong
41656 int SkGmResetCounter(
41657 -SK_AC *pAC, /* adapter context */
41658 -SK_IOC IoC, /* IO context */
41659 +SK_AC *pAC, /* Adapter Context */
41660 +SK_IOC IoC, /* I/O Context */
41661 unsigned int Port) /* Port Index (MAC_1 + n) */
41663 - SK_U16 Reg; /* Phy Address Register */
41664 + SK_U16 Reg; /* PHY Address Register */
41668 @@ -3999,16 +5213,16 @@
41670 /* set MIB Clear Counter Mode */
41671 GM_OUT16(IoC, Port, GM_PHY_ADDR, Reg | GM_PAR_MIB_CLR);
41674 /* read all MIB Counters with Clear Mode set */
41675 for (i = 0; i < GM_MIB_CNT_SIZE; i++) {
41676 /* the reset is performed only when the lower 16 bits are read */
41677 GM_IN16(IoC, Port, GM_MIB_CNT_BASE + 8*i, &Word);
41681 /* clear MIB Clear Counter Mode */
41682 GM_OUT16(IoC, Port, GM_PHY_ADDR, Reg);
41686 } /* SkGmResetCounter */
41688 @@ -4022,48 +5236,62 @@
41689 * resulting counter overflow status is written to <pStatus>, whereas the
41690 * the following bit coding is used:
41692 - * 55:48 - TxRx interrupt register bit7:0
41693 - * 32:47 - Rx interrupt register
41694 + * 55:48 - TxRx interrupt register bit 7:0
41695 + * 47:32 - Rx interrupt register
41697 - * 23:16 - TxRx interrupt register bit15:8
41698 - * 15:0 - Tx interrupt register
41699 + * 23:16 - TxRx interrupt register bit 15:8
41700 + * 15: 0 - Tx interrupt register
41704 * 1: something went wrong
41706 int SkGmOverflowStatus(
41707 -SK_AC *pAC, /* adapter context */
41708 -SK_IOC IoC, /* IO context */
41709 +SK_AC *pAC, /* Adapter Context */
41710 +SK_IOC IoC, /* I/O Context */
41711 unsigned int Port, /* Port Index (MAC_1 + n) */
41712 -SK_U16 IStatus, /* Interupt Status from MAC */
41713 -SK_U64 SK_FAR *pStatus) /* ptr for return overflow status value */
41714 +SK_U16 IStatus, /* Interrupt Status from MAC */
41715 +SK_U64 SK_FAR *pStatus) /* Pointer for return overflow status value */
41717 - SK_U64 Status; /* Overflow status */
41720 + SK_U64 Status; /* Overflow status */
41723 +#endif /* !SK_SLIM */
41725 if ((IStatus & GM_IS_RX_CO_OV) != 0) {
41726 /* this register is self-clearing after read */
41727 GM_IN16(IoC, Port, GM_RX_IRQ_SRC, &RegVal);
41730 Status |= (SK_U64)RegVal << 32;
41731 +#endif /* !SK_SLIM */
41735 if ((IStatus & GM_IS_TX_CO_OV) != 0) {
41736 /* this register is self-clearing after read */
41737 GM_IN16(IoC, Port, GM_TX_IRQ_SRC, &RegVal);
41740 Status |= (SK_U64)RegVal;
41741 +#endif /* !SK_SLIM */
41745 /* this register is self-clearing after read */
41746 GM_IN16(IoC, Port, GM_TR_IRQ_SRC, &RegVal);
41749 /* Rx overflow interrupt register bits (LoByte)*/
41750 Status |= (SK_U64)((SK_U8)RegVal) << 48;
41751 /* Tx overflow interrupt register bits (HiByte)*/
41752 Status |= (SK_U64)(RegVal >> 8) << 16;
41755 +#endif /* !SK_SLIM */
41757 + /* dummy read after GM_IN16() */
41758 + SK_IN16(IoC, B0_RAP, &RegVal);
41761 } /* SkGmOverflowStatus */
41762 @@ -4079,60 +5307,124 @@
41763 * gets the results if 'StartTest' is true
41765 * NOTE: this test is meaningful only when link is down
41770 * 1: no YUKON copper
41771 * 2: test in progress
41773 int SkGmCableDiagStatus(
41774 -SK_AC *pAC, /* adapter context */
41775 -SK_IOC IoC, /* IO context */
41776 +SK_AC *pAC, /* Adapter Context */
41777 +SK_IOC IoC, /* I/O Context */
41778 int Port, /* Port Index (MAC_1 + n) */
41779 SK_BOOL StartTest) /* flag for start / get result */
41782 + int CableDiagOffs;
41785 + SK_BOOL FastEthernet;
41790 pPrt = &pAC->GIni.GP[Port];
41792 if (pPrt->PhyType != SK_PHY_MARV_COPPER) {
41798 + Yukon2 = pAC->GIni.GIChipId == CHIP_ID_YUKON_XL ||
41799 + pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U;
41801 + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) {
41803 + CableDiagOffs = PHY_MARV_FE_VCT_TX;
41804 + FastEthernet = SK_TRUE;
41808 + CableDiagOffs = Yukon2 ? PHY_MARV_PHY_CTRL : PHY_MARV_CABLE_DIAG;
41809 + FastEthernet = SK_FALSE;
41815 + /* set to RESET to avoid PortCheckUp */
41816 + pPrt->PState = SK_PRT_RESET;
41818 /* only start the cable test */
41819 - if ((pPrt->PhyId1 & PHY_I1_REV_MSK) < 4) {
41820 - /* apply TDR workaround from Marvell */
41821 - SkGmPhyWrite(pAC, IoC, Port, 29, 0x001e);
41823 - SkGmPhyWrite(pAC, IoC, Port, 30, 0xcc00);
41824 - SkGmPhyWrite(pAC, IoC, Port, 30, 0xc800);
41825 - SkGmPhyWrite(pAC, IoC, Port, 30, 0xc400);
41826 - SkGmPhyWrite(pAC, IoC, Port, 30, 0xc000);
41827 - SkGmPhyWrite(pAC, IoC, Port, 30, 0xc100);
41828 + if (!FastEthernet) {
41830 + if ((((pPrt->PhyId1 & PHY_I1_MOD_NUM) >> 4) == 2) &&
41831 + ((pPrt->PhyId1 & PHY_I1_REV_MSK) < 4)) {
41832 + /* apply TDR workaround for model 2, rev. < 4 */
41833 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_ADDR, 0x001e);
41835 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xcc00);
41836 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xc800);
41837 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xc400);
41838 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xc000);
41839 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xc100);
41843 + if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) {
41844 + /* set address to 1 for page 1 */
41845 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 1);
41847 + /* disable waiting period */
41848 + SkGmPhyWrite(pAC, IoC, Port, CableDiagOffs,
41849 + PHY_M_CABD_DIS_WAIT);
41853 + /* set address to 5 for page 5 */
41854 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 5);
41857 + /* disable waiting period */
41858 + SkGmPhyWrite(pAC, IoC, Port, CableDiagOffs + 1,
41859 + PHY_M_CABD_DIS_WAIT);
41863 + /* set address to 0 for MDI[0] (Page 0) */
41864 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0);
41868 + RegVal = PHY_CT_RESET | PHY_CT_SP100;
41870 - /* set address to 0 for MDI[0] */
41871 - SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0);
41872 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, RegVal);
41874 - /* Read Cable Diagnostic Reg */
41875 - SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CABLE_DIAG, &RegVal);
41877 + SkGmPhyRead(pAC, IoC, Port, PHY_MARV_FE_SPEC_2, &RegVal);
41878 + /* disable waiting period */
41879 + RegVal |= PHY_M_FESC_DIS_WAIT;
41881 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_FE_SPEC_2, RegVal);
41885 /* start Cable Diagnostic Test */
41886 - SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CABLE_DIAG,
41887 - (SK_U16)(RegVal | PHY_M_CABD_ENA_TEST));
41889 + SkGmPhyWrite(pAC, IoC, Port, CableDiagOffs, PHY_M_CABD_ENA_TEST);
41895 /* Read Cable Diagnostic Reg */
41896 - SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CABLE_DIAG, &RegVal);
41897 + Rtv = SkGmPhyRead(pAC, IoC, Port, CableDiagOffs, &RegVal);
41900 + /* PHY read timeout */
41904 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
41905 - ("PHY Cable Diag.=0x%04X\n", RegVal));
41906 + ("PHY Cable Diag. = 0x%04X\n", RegVal));
41908 if ((RegVal & PHY_M_CABD_ENA_TEST) != 0) {
41909 /* test is running */
41910 @@ -4140,16 +5432,24 @@
41913 /* get the test results */
41914 - for (i = 0; i < 4; i++) {
41915 - /* set address to i for MDI[i] */
41916 - SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, (SK_U16)i);
41917 + for (i = 0; i < MdiPairs; i++) {
41919 + if (!FastEthernet && !Yukon2) {
41920 + /* set address to i for MDI[i] */
41921 + SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, (SK_U16)i);
41924 /* get Cable Diagnostic values */
41925 - SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CABLE_DIAG, &RegVal);
41926 + SkGmPhyRead(pAC, IoC, Port, CableDiagOffs, &RegVal);
41928 pPrt->PMdiPairLen[i] = (SK_U8)(RegVal & PHY_M_CABD_DIST_MSK);
41930 pPrt->PMdiPairSts[i] = (SK_U8)((RegVal & PHY_M_CABD_STAT_MSK) >> 13);
41932 + if (FastEthernet || Yukon2) {
41933 + /* get next register */
41939 @@ -4158,3 +5458,4 @@
41944 diff -ruN linux/drivers/net/sk98lin/sky2.c linux-new/drivers/net/sk98lin/sky2.c
41945 --- linux/drivers/net/sk98lin/sky2.c 1970-01-01 01:00:00.000000000 +0100
41946 +++ linux-new/drivers/net/sk98lin/sky2.c 2006-07-28 14:13:56.000000000 +0200
41948 +/******************************************************************************
41951 + * Project: Yukon2 specific functions and implementations
41952 + * Version: $Revision$
41954 + * Purpose: The main driver source module
41956 + *****************************************************************************/
41958 +/******************************************************************************
41960 + * (C)Copyright 1998-2002 SysKonnect GmbH.
41961 + * (C)Copyright 2002-2005 Marvell.
41963 + * Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet
41964 + * Server Adapters.
41966 + * Author: Ralph Roesler (rroesler@syskonnect.de)
41967 + * Mirko Lindner (mlindner@syskonnect.de)
41969 + * Address all question to: linux@syskonnect.de
41971 + * This program is free software; you can redistribute it and/or modify
41972 + * it under the terms of the GNU General Public License as published by
41973 + * the Free Software Foundation; either version 2 of the License, or
41974 + * (at your option) any later version.
41976 + * The information in this file is provided "AS IS" without warranty.
41978 + *****************************************************************************/
41980 +#include "h/skdrv1st.h"
41981 +#include "h/skdrv2nd.h"
41982 +#include <linux/tcp.h>
41983 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,14)
41984 +#include <linux/ip.h>
41986 +/******************************************************************************
41988 + * Local Function Prototypes
41990 + *****************************************************************************/
41992 +static void InitPacketQueues(SK_AC *pAC,int Port);
41993 +static void GiveTxBufferToHw(SK_AC *pAC,SK_IOC IoC,int Port);
41994 +static void GiveRxBufferToHw(SK_AC *pAC,SK_IOC IoC,int Port,SK_PACKET *pPacket);
41995 +static SK_BOOL HandleReceives(SK_AC *pAC,int Port,SK_U16 Len,SK_U32 FrameStatus,SK_U16 Tcp1,SK_U16 Tcp2,SK_U32 Tist,SK_U16 Vlan);
41996 +static void CheckForSendComplete(SK_AC *pAC,SK_IOC IoC,int Port,SK_PKT_QUEUE *pPQ,SK_LE_TABLE *pLETab,unsigned int Done);
41997 +static void UnmapAndFreeTxPktBuffer(SK_AC *pAC,SK_PACKET *pSkPacket,int TxPort);
41998 +static SK_BOOL AllocateAndInitLETables(SK_AC *pAC);
41999 +static SK_BOOL AllocatePacketBuffersYukon2(SK_AC *pAC);
42000 +static void FreeLETables(SK_AC *pAC);
42001 +static void FreePacketBuffers(SK_AC *pAC);
42002 +static SK_BOOL AllocAndMapRxBuffer(SK_AC *pAC,SK_PACKET *pSkPacket,int Port);
42003 +#ifdef CONFIG_SK98LIN_NAPI
42004 +static SK_BOOL HandleStatusLEs(SK_AC *pAC,int *WorkDone,int WorkToDo);
42006 +static SK_BOOL HandleStatusLEs(SK_AC *pAC);
42009 +extern void SkGeCheckTimer (DEV_NET *pNet);
42010 +extern void SkLocalEventQueue( SK_AC *pAC,
42016 +extern void SkLocalEventQueue64( SK_AC *pAC,
42022 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,15)
42023 +/* Need way to schedule device 0 even when it's offline. */
42024 +static inline int __netif_rx_schedule_prep(struct net_device *dev)
42026 + return !test_and_set_bit(__LINK_STATE_RX_SCHED, &dev->state);
42031 +/******************************************************************************
42033 + * Local Variables
42035 + *****************************************************************************/
42037 +#define MAX_NBR_RX_BUFFERS_IN_HW 0x15
42038 +static SK_U8 NbrRxBuffersInHW;
42039 +#define FLUSH_OPC(le)
42041 +/******************************************************************************
42043 + * Global Functions
42045 + *****************************************************************************/
42047 +int SkY2Xmit( struct sk_buff *skb, struct SK_NET_DEVICE *dev);
42048 +void FillReceiveTableYukon2(SK_AC *pAC,SK_IOC IoC,int Port);
42050 +/*****************************************************************************
42052 + * SkY2RestartStatusUnit - restarts teh status unit
42055 + * Reenables the status unit after any De-Init (e.g. when altering
42056 + * the sie of the MTU via 'ifconfig a.b.c.d mtu xxx')
42060 +void SkY2RestartStatusUnit(
42061 +SK_AC *pAC) /* pointer to adapter control context */
42063 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42064 + ("==> SkY2RestartStatusUnit\n"));
42067 + ** It might be that the TX timer is not started. Therefore
42068 + ** it is initialized here -> to be more investigated!
42070 + SK_OUT32(pAC->IoBase, STAT_TX_TIMER_INI, HW_MS_TO_TICKS(pAC,10));
42072 + pAC->StatusLETable.Done = 0;
42073 + pAC->StatusLETable.Put = 0;
42074 + pAC->StatusLETable.HwPut = 0;
42075 + SkGeY2InitStatBmu(pAC, pAC->IoBase, &pAC->StatusLETable);
42077 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42078 + ("<== SkY2RestartStatusUnit\n"));
42081 +/*****************************************************************************
42083 + * SkY2RlmtSend - sends out a single RLMT notification
42086 + * This function sends out an RLMT frame
42089 + * > 0 - on succes: the number of bytes in the message
42090 + * = 0 - on resource shortage: this frame sent or dropped, now
42091 + * the ring is full ( -> set tbusy)
42092 + * < 0 - on failure: other problems ( -> return failure to upper layers)
42094 +int SkY2RlmtSend (
42095 +SK_AC *pAC, /* pointer to adapter control context */
42096 +int PortNr, /* index of port the packet(s) shall be send to */
42097 +struct sk_buff *pMessage) /* pointer to send-message */
42099 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42100 + ("=== SkY2RlmtSend\n"));
42102 + return -1; // temporarily do not send out RLMT frames
42104 + skb_shinfo(pMessage)->nr_frags = (2*MAX_SKB_FRAGS) + PortNr;
42105 + return(SkY2Xmit(pMessage, pAC->dev[PortNr])); // SkY2Xmit needs device
42108 +/*****************************************************************************
42110 + * SkY2AllocateResources - Allocates all required resources for Yukon2
42113 + * This function allocates all memory needed for the Yukon2.
42114 + * It maps also RX buffers to the LETables and initializes the
42115 + * status list element table.
42118 + * SK_TRUE, if all resources could be allocated and setup succeeded
42119 + * SK_FALSE, if an error
42121 +SK_BOOL SkY2AllocateResources (
42122 +SK_AC *pAC) /* pointer to adapter control context */
42126 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
42127 + ("==> SkY2AllocateResources\n"));
42130 + ** Initialize the packet queue variables first
42132 + for (CurrMac = 0; CurrMac < pAC->GIni.GIMacsFound; CurrMac++) {
42133 + InitPacketQueues(pAC, CurrMac);
42137 + ** Get sufficient memory for the LETables
42139 + if (!AllocateAndInitLETables(pAC)) {
42140 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
42141 + SK_DBGCAT_INIT | SK_DBGCAT_DRV_ERROR,
42142 + ("No memory for LETable.\n"));
42143 + return(SK_FALSE);
42147 + ** Allocate and intialize memory for both RX and TX
42148 + ** packet and fragment buffers. On an error, free
42149 + ** previously allocated LETable memory and quit.
42151 + if (!AllocatePacketBuffersYukon2(pAC)) {
42152 + FreeLETables(pAC);
42153 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
42154 + SK_DBGCAT_INIT | SK_DBGCAT_DRV_ERROR,
42155 + ("No memory for Packetbuffers.\n"));
42156 + return(SK_FALSE);
42160 + ** Rx and Tx LE tables will be initialized in SkGeOpen()
42162 + ** It might be that the TX timer is not started. Therefore
42163 + ** it is initialized here -> to be more investigated!
42165 + SK_OUT32(pAC->IoBase, STAT_TX_TIMER_INI, HW_MS_TO_TICKS(pAC,10));
42166 + SkGeY2InitStatBmu(pAC, pAC->IoBase, &pAC->StatusLETable);
42168 + pAC->MaxUnusedRxLeWorking = MAX_UNUSED_RX_LE_WORKING;
42170 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
42171 + ("<== SkY2AllocateResources\n"));
42173 + return (SK_TRUE);
42176 +/*****************************************************************************
42178 + * SkY2FreeResources - Frees previously allocated resources of Yukon2
42181 + * This function frees all previously allocated memory of the Yukon2.
42185 +void SkY2FreeResources (
42186 +SK_AC *pAC) /* pointer to adapter control context */
42188 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42189 + ("==> SkY2FreeResources\n"));
42191 + FreeLETables(pAC);
42192 + FreePacketBuffers(pAC);
42194 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42195 + ("<== SkY2FreeResources\n"));
42198 +/*****************************************************************************
42200 + * SkY2AllocateRxBuffers - Allocates the receive buffers for a port
42203 + * This function allocated all the RX buffers of the Yukon2.
42207 +void SkY2AllocateRxBuffers (
42208 +SK_AC *pAC, /* pointer to adapter control context */
42209 +SK_IOC IoC, /* I/O control context */
42210 +int Port) /* port index of RX */
42212 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
42213 + ("==> SkY2AllocateRxBuffers (Port %c)\n", Port));
42215 + FillReceiveTableYukon2(pAC, IoC, Port);
42217 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
42218 + ("<== SkY2AllocateRxBuffers\n"));
42221 +/*****************************************************************************
42223 + * SkY2FreeRxBuffers - Free's all allocates RX buffers of
42226 + * This function frees all RX buffers of the Yukon2 for a single port
42230 +void SkY2FreeRxBuffers (
42231 +SK_AC *pAC, /* pointer to adapter control context */
42232 +SK_IOC IoC, /* I/O control context */
42233 +int Port) /* port index of RX */
42235 + SK_PACKET *pSkPacket;
42236 + unsigned long Flags; /* for POP/PUSH macros */
42238 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42239 + ("==> SkY2FreeRxBuffers (Port %c)\n", Port));
42241 + if (pAC->RxPort[Port].ReceivePacketTable != NULL) {
42242 + POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_working, pSkPacket);
42243 + while (pSkPacket != NULL) {
42244 + if ((pSkPacket->pFrag) != NULL) {
42245 + pci_unmap_page(pAC->PciDev,
42246 + (dma_addr_t) pSkPacket->pFrag->pPhys,
42247 + pSkPacket->pFrag->FragLen - 2,
42248 + PCI_DMA_FROMDEVICE);
42250 + /* wipe out any rubbish data that may interfere */
42251 + skb_shinfo(pSkPacket->pMBuf)->nr_frags = 0;
42252 + skb_shinfo(pSkPacket->pMBuf)->frag_list = NULL;
42253 + DEV_KFREE_SKB_ANY(pSkPacket->pMBuf);
42254 + pSkPacket->pMBuf = NULL;
42255 + pSkPacket->pFrag->pPhys = (SK_U64) 0;
42256 + pSkPacket->pFrag->pVirt = NULL;
42258 + PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pSkPacket);
42259 + POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_working, pSkPacket);
42263 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42264 + ("<== SkY2FreeRxBuffers\n"));
42267 +/*****************************************************************************
42269 + * SkY2FreeTxBuffers - Free's any currently maintained Tx buffer
42272 + * This function frees the TX buffers of the Yukon2 for a single port
42273 + * which might be in use by a transmit action
42277 +void SkY2FreeTxBuffers (
42278 +SK_AC *pAC, /* pointer to adapter control context */
42279 +SK_IOC IoC, /* I/O control context */
42280 +int Port) /* port index of TX */
42282 + SK_PACKET *pSkPacket;
42283 + SK_FRAG *pSkFrag;
42284 + unsigned long Flags;
42286 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42287 + ("==> SkY2FreeTxBuffers (Port %c)\n", Port));
42289 + if (pAC->TxPort[Port][0].TransmitPacketTable != NULL) {
42290 + POP_FIRST_PKT_FROM_QUEUE(&pAC->TxPort[Port][0].TxAQ_working, pSkPacket);
42291 + while (pSkPacket != NULL) {
42292 + if ((pSkFrag = pSkPacket->pFrag) != NULL) {
42293 + UnmapAndFreeTxPktBuffer(pAC, pSkPacket, Port);
42295 + PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->TxPort[Port][0].TxQ_free, pSkPacket);
42296 + POP_FIRST_PKT_FROM_QUEUE(&pAC->TxPort[Port][0].TxAQ_working, pSkPacket);
42298 +#ifdef USE_SYNC_TX_QUEUE
42299 + POP_FIRST_PKT_FROM_QUEUE(&pAC->TxPort[Port][0].TxSQ_working, pSkPacket);
42300 + while (pSkPacket != NULL) {
42301 + if ((pSkFrag = pSkPacket->pFrag) != NULL) {
42302 + UnmapAndFreeTxPktBuffer(pAC, pSkPacket, Port);
42304 + PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->TxPort[Port][0].TxQ_free, pSkPacket);
42305 + POP_FIRST_PKT_FROM_QUEUE(&pAC->TxPort[Port][0].TxSQ_working, pSkPacket);
42310 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42311 + ("<== SkY2FreeTxBuffers\n"));
42314 +/*****************************************************************************
42316 + * SkY2Isr - handle a receive IRQ for all yukon2 cards
42319 + * This function is called when a receive IRQ is set. (only for yukon2)
42320 + * HandleReceives does the deferred processing of all outstanding
42321 + * interrupt operations.
42325 +SkIsrRetVar SkY2Isr (
42326 +int irq, /* the irq we have received (might be shared!) */
42327 +void *dev_id /* current device id */
42330 + struct SK_NET_DEVICE *dev = (struct SK_NET_DEVICE *)dev_id;
42331 + DEV_NET *pNet = (DEV_NET*) dev->priv;
42332 + SK_AC *pAC = pNet->pAC;
42334 +#ifdef CONFIG_SK98LIN_NAPI
42335 + SK_BOOL SetIntMask = SK_FALSE;
42337 + SK_BOOL handledStatLE = SK_FALSE;
42338 + unsigned long Flags;
42341 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
42342 + ("==> SkY2Isr\n"));
42344 + SK_IN32(pAC->IoBase, B0_Y2_SP_ISRC2, &IntSrc);
42346 + if ((IntSrc == 0) && (!pNet->NetConsoleMode)){
42347 + SK_OUT32(pAC->IoBase, B0_Y2_SP_ICR, 2);
42348 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
42349 + ("No Interrupt\n ==> SkY2Isr\n"));
42350 + return SkIsrRetNone;
42354 +#ifdef Y2_RECOVERY
42355 + if (pNet->InRecover) {
42356 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
42357 + ("Already in recover\n ==> SkY2Isr\n"));
42358 + SK_OUT32(pAC->IoBase, B0_Y2_SP_ICR, 2);
42359 + return SkIsrRetNone;
42363 +#ifdef CONFIG_SK98LIN_NAPI
42364 + /* Since both boards share one irq, they share one poll routine */
42365 + if (__netif_rx_schedule_prep(pAC->dev[0])) {
42366 + pAC->GIni.GIValIrqMask &= ~(Y2_IS_STAT_BMU);
42367 + SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
42368 + SetIntMask = SK_TRUE;
42369 + __netif_rx_schedule(pAC->dev[0]);
42372 + handledStatLE = HandleStatusLEs(pAC);
42376 + ** Check for Special Interrupts
42378 + if ((IntSrc & ~Y2_IS_STAT_BMU) || pAC->CheckQueue || pNet->TimerExpired) {
42379 + pAC->CheckQueue = SK_FALSE;
42380 +#ifdef CONFIG_SK98LIN_NAPI
42381 + spin_lock(&pAC->SlowPathLock);
42383 + spin_lock_irqsave(&pAC->SetPutIndexLock, Flags);
42385 + SkGeSirqIsr(pAC, pAC->IoBase, IntSrc);
42386 + SkEventDispatcher(pAC, pAC->IoBase);
42387 +#ifdef CONFIG_SK98LIN_NAPI
42388 + spin_unlock(&pAC->SlowPathLock);
42390 + spin_unlock_irqrestore(&pAC->SetPutIndexLock, Flags);
42394 + /* Speed enhancement for a2 chipsets */
42395 + if (HW_FEATURE(pAC, HWF_WA_DEV_42)) {
42396 +#ifdef CONFIG_SK98LIN_NAPI
42397 + spin_lock(&pAC->SlowPathLock);
42399 + spin_lock_irqsave(&pAC->SetPutIndexLock, Flags);
42401 + SkGeY2SetPutIndex(pAC, pAC->IoBase, Y2_PREF_Q_ADDR(Q_XA1,0), &pAC->TxPort[0][0].TxALET);
42402 + SkGeY2SetPutIndex(pAC, pAC->IoBase, Y2_PREF_Q_ADDR(Q_R1,0), &pAC->RxPort[0].RxLET);
42403 +#ifdef CONFIG_SK98LIN_NAPI
42404 + spin_unlock(&pAC->SlowPathLock);
42406 + spin_unlock_irqrestore(&pAC->SetPutIndexLock, Flags);
42411 + ** Reenable interrupts and signal end of ISR
42413 + SK_OUT32(pAC->IoBase, B0_Y2_SP_ICR, 2);
42416 + ** Stop and restart TX timer in case a Status LE was handled
42418 +#ifndef CONFIG_SK98LIN_NAPI
42419 + if ((HW_FEATURE(pAC, HWF_WA_DEV_43_418)) && (handledStatLE)) {
42420 + SK_OUT8(pAC->IoBase, STAT_TX_TIMER_CTRL, TIM_STOP);
42421 + SK_OUT8(pAC->IoBase, STAT_TX_TIMER_CTRL, TIM_START);
42425 + if (!(IS_Q_EMPTY(&(pAC->TxPort[0][TX_PRIO_LOW].TxAQ_waiting)))) {
42426 + GiveTxBufferToHw(pAC, pAC->IoBase, 0);
42428 + if (!(IS_Q_EMPTY(&(pAC->TxPort[1][TX_PRIO_LOW].TxAQ_waiting)))) {
42429 + GiveTxBufferToHw(pAC, pAC->IoBase, 1);
42432 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
42433 + ("<== SkY2Isr\n"));
42435 + return SkIsrRetHandled;
42438 +/*****************************************************************************
42440 + * SkY2Xmit - Linux frame transmit function for Yukon2
42443 + * The system calls this function to send frames onto the wire.
42444 + * It puts the frame in the tx descriptor ring. If the ring is
42445 + * full then, the 'tbusy' flag is set.
42448 + * 0, if everything is ok
42452 + * returning 1 in 'tbusy' case caused system crashes (double
42453 + * allocated skb's) !!!
42456 +struct sk_buff *skb, /* socket buffer to be sent */
42457 +struct SK_NET_DEVICE *dev) /* via which device? */
42459 + DEV_NET *pNet = (DEV_NET*) dev->priv;
42460 + SK_AC *pAC = pNet->pAC;
42461 + SK_U8 FragIdx = 0;
42462 + SK_PACKET *pSkPacket;
42463 + SK_FRAG *PrevFrag;
42464 + SK_FRAG *CurrFrag;
42465 + SK_PKT_QUEUE *pWorkQueue; /* corresponding TX queue */
42466 + SK_PKT_QUEUE *pWaitQueue;
42467 + SK_PKT_QUEUE *pFreeQueue;
42468 + SK_LE_TABLE *pLETab; /* corresponding LETable */
42469 + skb_frag_t *sk_frag;
42471 + unsigned long Flags;
42472 + unsigned int Port;
42475 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
42476 + ("==> SkY2Xmit\n"));
42479 + ** Get port and return if no free packet is available
42481 + if (skb_shinfo(skb)->nr_frags > MAX_SKB_FRAGS) {
42482 + Port = skb_shinfo(skb)->nr_frags - (2*MAX_SKB_FRAGS);
42483 + skb_shinfo(skb)->nr_frags = 0;
42485 + Port = (pAC->RlmtNets == 2) ? pNet->PortNr : pAC->ActivePort;
42488 + if (IS_Q_EMPTY(&(pAC->TxPort[Port][TX_PRIO_LOW].TxQ_free))) {
42489 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
42490 + SK_DBGCAT_DRV_TX_PROGRESS | SK_DBGCAT_DRV_ERROR,
42491 + ("Not free packets available for send\n"));
42492 + return 1; /* zero bytes sent! */
42496 + ** Put any new packet to be sent in the waiting queue and
42497 + ** handle also any possible fragment of that packet.
42499 + pWorkQueue = &(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_working);
42500 + pWaitQueue = &(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting);
42501 + pFreeQueue = &(pAC->TxPort[Port][TX_PRIO_LOW].TxQ_free);
42502 + pLETab = &(pAC->TxPort[Port][TX_PRIO_LOW].TxALET);
42505 + ** Normal send operations require only one fragment, because
42506 + ** only one sk_buff data area is passed.
42507 + ** In contradiction to this, scatter-gather (zerocopy) send
42508 + ** operations might pass one or more additional fragments
42509 + ** where each fragment needs a separate fragment info packet.
42511 + if (((skb_shinfo(skb)->nr_frags + 1) * MAX_FRAG_OVERHEAD) >
42512 + NUM_FREE_LE_IN_TABLE(pLETab)) {
42513 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
42514 + SK_DBGCAT_DRV_TX_PROGRESS | SK_DBGCAT_DRV_ERROR,
42515 + ("Not enough LE available for send\n"));
42516 + return 1; /* zero bytes sent! */
42519 + if ((skb_shinfo(skb)->nr_frags + 1) > MAX_NUM_FRAGS) {
42520 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
42521 + SK_DBGCAT_DRV_TX_PROGRESS | SK_DBGCAT_DRV_ERROR,
42522 + ("Not even one fragment available for send\n"));
42523 + return 1; /* zero bytes sent! */
42527 + ** Get first packet from free packet queue
42529 + POP_FIRST_PKT_FROM_QUEUE(pFreeQueue, pSkPacket);
42530 + if(pSkPacket == NULL) {
42531 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
42532 + SK_DBGCAT_DRV_TX_PROGRESS | SK_DBGCAT_DRV_ERROR,
42533 + ("Could not obtain free packet used for xmit\n"));
42534 + return 1; /* zero bytes sent! */
42537 + pSkPacket->pFrag = &(pSkPacket->FragArray[FragIdx]);
42540 + ** map the sk_buff to be available for the adapter
42542 + PhysAddr = (SK_U64) pci_map_page(pAC->PciDev,
42543 + virt_to_page(skb->data),
42544 + ((unsigned long) skb->data & ~PAGE_MASK),
42545 + skb_headlen(skb),
42546 + PCI_DMA_TODEVICE);
42547 + pSkPacket->pMBuf = skb;
42548 + pSkPacket->pFrag->pPhys = PhysAddr;
42549 + pSkPacket->pFrag->FragLen = skb_headlen(skb);
42550 + pSkPacket->pFrag->pNext = NULL; /* initial has no next default */
42551 + pSkPacket->NumFrags = skb_shinfo(skb)->nr_frags + 1;
42553 + PrevFrag = pSkPacket->pFrag;
42556 + ** Each scatter-gather fragment need to be mapped...
42558 + for ( CurrFragCtr = 0;
42559 + CurrFragCtr < skb_shinfo(skb)->nr_frags;
42562 + sk_frag = &skb_shinfo(skb)->frags[CurrFragCtr];
42563 + CurrFrag = &(pSkPacket->FragArray[FragIdx]);
42566 + ** map the sk_buff to be available for the adapter
42568 + PhysAddr = (SK_U64) pci_map_page(pAC->PciDev,
42570 + sk_frag->page_offset,
42572 + PCI_DMA_TODEVICE);
42574 + CurrFrag->pPhys = PhysAddr;
42575 + CurrFrag->FragLen = sk_frag->size;
42576 + CurrFrag->pNext = NULL;
42579 + ** Add the new fragment to the list of fragments
42581 + PrevFrag->pNext = CurrFrag;
42582 + PrevFrag = CurrFrag;
42586 + ** Add packet to waiting packets queue
42588 + PUSH_PKT_AS_LAST_IN_QUEUE(pWaitQueue, pSkPacket);
42589 + GiveTxBufferToHw(pAC, pAC->IoBase, Port);
42590 + dev->trans_start = jiffies;
42591 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
42592 + ("<== SkY2Xmit(return 0)\n"));
42596 +#ifdef CONFIG_SK98LIN_NAPI
42597 +/*****************************************************************************
42599 + * SkY2Poll - NAPI Rx polling callback for Yukon2 chipsets
42602 + * Called by the Linux system in case NAPI polling is activated
42605 + * The number of work data still to be handled
42608 + * The slowpath lock needs to be set because HW accesses may
42609 + * interfere with slowpath events (e.g. TWSI)
42612 +struct net_device *dev, /* device that needs to be polled */
42613 +int *budget) /* how many budget do we have? */
42615 + SK_AC *pAC = ((DEV_NET*)(dev->priv))->pAC;
42616 + int WorkToDo = min(*budget, dev->quota);
42617 + int WorkDone = 0;
42618 + SK_BOOL handledStatLE = SK_FALSE;
42620 + handledStatLE = HandleStatusLEs(pAC, &WorkDone, WorkToDo);
42622 + *budget -= WorkDone;
42623 + dev->quota -= WorkDone;
42625 + if(WorkDone < WorkToDo) {
42626 + netif_rx_complete(dev);
42627 + pAC->GIni.GIValIrqMask |= (Y2_IS_STAT_BMU);
42628 + SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
42629 + if ((HW_FEATURE(pAC, HWF_WA_DEV_43_418)) && (handledStatLE)) {
42630 + SK_OUT8(pAC->IoBase, STAT_TX_TIMER_CTRL, TIM_STOP);
42631 + SK_OUT8(pAC->IoBase, STAT_TX_TIMER_CTRL, TIM_START);
42634 + return (WorkDone >= WorkToDo);
42638 +/******************************************************************************
42640 + * SkY2PortStop - stop a port on Yukon2
42643 + * This function stops a port of the Yukon2 chip. This stop
42644 + * stop needs to be performed in a specific order:
42646 + * a) Stop the Prefetch unit
42647 + * b) Stop the Port (MAC, PHY etc.)
42651 +void SkY2PortStop(
42652 +SK_AC *pAC, /* adapter control context */
42653 +SK_IOC IoC, /* I/O control context (address of adapter registers) */
42654 +int Port, /* port to stop (MAC_1 + n) */
42655 +int Dir, /* StopDirection (SK_STOP_RX, SK_STOP_TX, SK_STOP_ALL) */
42656 +int RstMode) /* Reset Mode (SK_SOFT_RST, SK_HARD_RST) */
42658 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42659 + ("==> SkY2PortStop (Port %c)\n", 'A' + Port));
42664 + SkGeStopPort(pAC, IoC, Port, Dir, RstMode);
42667 + ** Move any TX packet from work queues into the free queue again
42668 + ** and initialize the TX LETable variables
42670 + SkY2FreeTxBuffers(pAC, pAC->IoBase, Port);
42671 + pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Bmu.RxTx.TcpWp = 0;
42672 + pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Bmu.RxTx.MssValue = 0;
42673 + pAC->TxPort[Port][TX_PRIO_LOW].TxALET.BufHighAddr = 0;
42674 + pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Done = 0;
42675 + pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Put = 0;
42676 + // pAC->GIni.GP[Port].PState = SK_PRT_STOP;
42679 + ** Move any RX packet from work queue into the waiting queue
42680 + ** and initialize the RX LETable variables
42682 + SkY2FreeRxBuffers(pAC, pAC->IoBase, Port);
42683 + pAC->RxPort[Port].RxLET.BufHighAddr = 0;
42685 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42686 + ("<== SkY2PortStop()\n"));
42689 +/******************************************************************************
42691 + * SkY2PortStart - start a port on Yukon2
42694 + * This function starts a port of the Yukon2 chip. This start
42695 + * action needs to be performed in a specific order:
42697 + * a) Initialize the LET indices (PUT/GET to 0)
42698 + * b) Initialize the LET in HW (enables also prefetch unit)
42699 + * c) Move all RX buffers from waiting queue to working queue
42700 + * which involves also setting up of RX list elements
42701 + * d) Initialize the FIFO settings of Yukon2 (Watermark etc.)
42702 + * e) Initialize the Port (MAC, PHY etc.)
42703 + * f) Initialize the MC addresses
42707 +void SkY2PortStart(
42708 +SK_AC *pAC, /* adapter control context */
42709 +SK_IOC IoC, /* I/O control context (address of adapter registers) */
42710 +int Port) /* port to start */
42712 + // SK_GEPORT *pPrt = &pAC->GIni.GP[Port];
42715 + SK_U32 PrefetchReg; /* register for Put index */
42717 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42718 + ("==> SkY2PortStart (Port %c)\n", 'A' + Port));
42721 + ** Initialize the LET indices
42723 + pAC->RxPort[Port].RxLET.Done = 0;
42724 + pAC->RxPort[Port].RxLET.Put = 0;
42725 + pAC->RxPort[Port].RxLET.HwPut = 0;
42726 + pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Done = 0;
42727 + pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Put = 0;
42728 + pAC->TxPort[Port][TX_PRIO_LOW].TxALET.HwPut = 0;
42729 + if (HW_SYNC_TX_SUPPORTED(pAC)) {
42730 + pAC->TxPort[Port][TX_PRIO_LOW].TxSLET.Done = 0;
42731 + pAC->TxPort[Port][TX_PRIO_LOW].TxSLET.Put = 0;
42732 + pAC->TxPort[Port][TX_PRIO_LOW].TxSLET.HwPut = 0;
42735 + if (HW_FEATURE(pAC, HWF_WA_DEV_420)) {
42737 + ** It might be that we have to limit the RX buffers
42738 + ** effectively passed to HW. Initialize the start
42739 + ** value in that case...
42741 + NbrRxBuffersInHW = 0;
42745 + ** TODO on dual net adapters we need to check if
42746 + ** StatusLETable need to be set...
42748 + ** pAC->StatusLETable.Done = 0;
42749 + ** pAC->StatusLETable.Put = 0;
42750 + ** pAC->StatusLETable.HwPut = 0;
42751 + ** SkGeY2InitPrefetchUnit(pAC, pAC->IoBase, Q_ST, &pAC->StatusLETable);
42755 + ** Initialize the LET in HW (enables also prefetch unit)
42757 + SkGeY2InitPrefetchUnit(pAC, IoC,(Port == 0) ? Q_R1 : Q_R2,
42758 + &pAC->RxPort[Port].RxLET);
42759 + SkGeY2InitPrefetchUnit( pAC, IoC,(Port == 0) ? Q_XA1 : Q_XA2,
42760 + &pAC->TxPort[Port][TX_PRIO_LOW].TxALET);
42761 + if (HW_SYNC_TX_SUPPORTED(pAC)) {
42762 + SkGeY2InitPrefetchUnit( pAC, IoC, (Port == 0) ? Q_XS1 : Q_XS2,
42763 + &pAC->TxPort[Port][TX_PRIO_HIGH].TxSLET);
42768 + ** Using new values for the watermarks and the timer for
42769 + ** low latency optimization
42771 + if (pAC->LowLatency) {
42772 + SK_OUT8(IoC, STAT_FIFO_WM, 1);
42773 + SK_OUT8(IoC, STAT_FIFO_ISR_WM, 1);
42774 + SK_OUT32(IoC, STAT_LEV_TIMER_INI, 50);
42775 + SK_OUT32(IoC, STAT_ISR_TIMER_INI, 10);
42780 + ** Initialize the Port (MAC, PHY etc.)
42782 + if (SkGeInitPort(pAC, IoC, Port)) {
42784 + printk("%s: SkGeInitPort A failed.\n",pAC->dev[0]->name);
42786 + printk("%s: SkGeInitPort B failed.\n",pAC->dev[1]->name);
42790 + if (IS_GMAC(pAC)) {
42791 + /* disable Rx GMAC FIFO Flush Mode */
42792 + SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8) GMF_RX_F_FL_OFF);
42796 + ** Initialize the MC addresses
42798 + SkAddrMcUpdate(pAC,IoC, Port);
42800 + SkMacRxTxEnable(pAC, IoC,Port);
42802 + if (pAC->RxPort[Port].UseRxCsum) {
42803 + SkGeRxCsum(pAC, IoC, Port, SK_TRUE);
42805 + GET_RX_LE(pLE, &pAC->RxPort[Port].RxLET);
42806 + RXLE_SET_STACS1(pLE, pAC->CsOfs1);
42807 + RXLE_SET_STACS2(pLE, pAC->CsOfs2);
42808 + RXLE_SET_CTRL(pLE, 0);
42810 + RXLE_SET_OPC(pLE, OP_TCPSTART | HW_OWNER);
42813 + PrefetchReg=Y2_PREF_Q_ADDR(Q_R1,PREF_UNIT_PUT_IDX_REG);
42815 + PrefetchReg=Y2_PREF_Q_ADDR(Q_R2,PREF_UNIT_PUT_IDX_REG);
42817 + DWord = GET_PUT_IDX(&pAC->RxPort[Port].RxLET);
42818 + SK_OUT32(IoC, PrefetchReg, DWord);
42819 + UPDATE_HWPUT_IDX(&pAC->RxPort[Port].RxLET);
42822 + pAC->GIni.GP[Port].PState = SK_PRT_RUN;
42823 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42824 + ("<== SkY2PortStart()\n"));
42827 +/******************************************************************************
42829 + * Local Functions
42831 + *****************************************************************************/
42833 +/*****************************************************************************
42835 + * InitPacketQueues - initialize SW settings of packet queues
42838 + * This function will initialize the packet queues for a port.
42842 +static void InitPacketQueues(
42843 +SK_AC *pAC, /* pointer to adapter control context */
42844 +int Port) /* index of port to be initialized */
42846 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
42847 + ("==> InitPacketQueues(Port %c)\n", 'A' + Port));
42849 + pAC->RxPort[Port].RxQ_working.pHead = NULL;
42850 + pAC->RxPort[Port].RxQ_working.pTail = NULL;
42851 + spin_lock_init(&pAC->RxPort[Port].RxQ_working.QueueLock);
42853 + pAC->RxPort[Port].RxQ_waiting.pHead = NULL;
42854 + pAC->RxPort[Port].RxQ_waiting.pTail = NULL;
42855 + spin_lock_init(&pAC->RxPort[Port].RxQ_waiting.QueueLock);
42857 + pAC->TxPort[Port][TX_PRIO_LOW].TxQ_free.pHead = NULL;
42858 + pAC->TxPort[Port][TX_PRIO_LOW].TxQ_free.pTail = NULL;
42859 + spin_lock_init(&pAC->TxPort[Port][TX_PRIO_LOW].TxQ_free.QueueLock);
42861 + pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_working.pHead = NULL;
42862 + pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_working.pTail = NULL;
42863 + spin_lock_init(&pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_working.QueueLock);
42865 + pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting.pHead = NULL;
42866 + pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting.pTail = NULL;
42867 + spin_lock_init(&pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting.QueueLock);
42869 +#ifdef USE_SYNC_TX_QUEUE
42870 + pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_working.pHead = NULL;
42871 + pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_working.pTail = NULL;
42872 + spin_lock_init(&pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_working.QueueLock);
42874 + pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_waiting.pHead = NULL;
42875 + pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_waiting.pTail = NULL;
42876 + spin_lock_init(&pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_waiting.QueueLock);
42879 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
42880 + ("<== InitPacketQueues(Port %c)\n", 'A' + Port));
42881 +} /* InitPacketQueues */
42883 +/*****************************************************************************
42885 + * GiveTxBufferToHw - commits a previously allocated DMA area to HW
42888 + * This functions gives transmit buffers to HW. If no list elements
42889 + * are available the buffers will be queued.
42892 + * This function can run only once in a system at one time.
42896 +static void GiveTxBufferToHw(
42897 +SK_AC *pAC, /* pointer to adapter control context */
42898 +SK_IOC IoC, /* I/O control context (address of registers) */
42899 +int Port) /* port index for which the buffer is used */
42902 + SK_PACKET *pSkPacket;
42904 + SK_PKT_QUEUE *pWorkQueue; /* corresponding TX queue */
42905 + SK_PKT_QUEUE *pWaitQueue;
42906 + SK_LE_TABLE *pLETab; /* corresponding LETable */
42907 + SK_BOOL SetOpcodePacketFlag;
42908 + SK_U32 HighAddress;
42909 + SK_U32 LowAddress;
42910 + SK_U16 TcpSumStart;
42911 + SK_U16 TcpSumWrite;
42914 + unsigned long Flags;
42915 + unsigned long LockFlag;
42917 +#ifdef NETIF_F_TSO
42923 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
42924 + ("==> GiveTxBufferToHw\n"));
42926 + if (IS_Q_EMPTY(&(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting))) {
42930 + spin_lock_irqsave(&pAC->TxQueueLock, LockFlag);
42933 + ** Initialize queue settings
42935 + pWorkQueue = &(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_working);
42936 + pWaitQueue = &(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting);
42937 + pLETab = &(pAC->TxPort[Port][TX_PRIO_LOW].TxALET);
42939 + POP_FIRST_PKT_FROM_QUEUE(pWaitQueue, pSkPacket);
42940 + while (pSkPacket != NULL) {
42941 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
42942 + ("\tWe have a packet to send %p\n", pSkPacket));
42945 + ** the first frag of a packet gets opcode OP_PACKET
42947 + SetOpcodePacketFlag = SK_TRUE;
42948 + pFrag = pSkPacket->pFrag;
42951 + ** fill list elements with data from fragments
42953 + while (pFrag != NULL) {
42954 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
42956 +#ifdef NETIF_F_TSO
42957 + Mss = skb_shinfo(pSkPacket->pMBuf)->gso_size;
42959 + TcpOptLen = ((pSkPacket->pMBuf->h.th->doff - 5) * 4);
42960 + IpTcpLen = ((pSkPacket->pMBuf->nh.iph->ihl * 4) +
42961 + sizeof(struct tcphdr));
42962 + Mss += (TcpOptLen + IpTcpLen + C_LEN_ETHERMAC_HEADER);
42964 + if (pLETab->Bmu.RxTx.MssValue != Mss) {
42965 + pLETab->Bmu.RxTx.MssValue = Mss;
42966 + /* Take a new LE for TSO from the table */
42967 + GET_TX_LE(pLE, pLETab);
42970 + if(pSkPacket->VlanId) {
42971 + TXLE_SET_OPC(pLE, OP_LRGLENVLAN | HW_OWNER);
42972 + TXLE_SET_VLAN(pLE, pSkPacket->VlanId);
42973 + pSkPacket->VlanId = 0;
42974 + Ctrl |= INS_VLAN;
42977 + TXLE_SET_OPC(pLE, OP_LRGLEN | HW_OWNER);
42981 + /* set maximum segment size for new packet */
42982 + TXLE_SET_LSLEN(pLE, pLETab->Bmu.RxTx.MssValue);
42986 + GET_TX_LE(pLE, pLETab);
42989 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
42990 + ("\tGot empty LE %p idx %d\n", pLE, GET_PUT_IDX(pLETab)));
42992 + SK_DBG_DUMP_TX_LE(pLE);
42994 + LowAddress = (SK_U32) (pFrag->pPhys & 0xffffffff);
42995 + HighAddress = (SK_U32) (pFrag->pPhys >> 32);
42997 + if (HighAddress != pLETab->BufHighAddr) {
42998 + /* set opcode high part of the address in one LE */
42999 + OpCode = OP_ADDR64 | HW_OWNER;
43001 + /* Set now the 32 high bits of the address */
43002 + TXLE_SET_ADDR( pLE, HighAddress);
43004 + /* Set the opcode into the LE */
43005 + TXLE_SET_OPC(pLE, OpCode);
43007 + /* Flush the LE to memory */
43010 + /* remember the HighAddress we gave to the Hardware */
43011 + pLETab->BufHighAddr = HighAddress;
43013 + /* get a new LE because we filled one with high address */
43014 + GET_TX_LE(pLE, pLETab);
43018 + ** TCP checksum offload
43020 + if ((pSkPacket->pMBuf->ip_summed == CHECKSUM_PARTIAL) &&
43021 + (SetOpcodePacketFlag == SK_TRUE)) {
43022 + Protocol = ((SK_U8)pSkPacket->pMBuf->data[C_OFFSET_IPPROTO] & 0xff);
43023 + /* if (Protocol & C_PROTO_ID_IP) { Ctrl = 0; } */
43024 + if (Protocol & C_PROTO_ID_TCP) {
43025 + Ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
43026 + /* TCP Checksum Calculation Start Position */
43027 + TcpSumStart = C_LEN_ETHERMAC_HEADER + IP_HDR_LEN;
43028 + /* TCP Checksum Write Position */
43029 + TcpSumWrite = TcpSumStart + TCP_CSUM_OFFS;
43031 + Ctrl = UDPTCP | CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
43032 + /* TCP Checksum Calculation Start Position */
43033 + TcpSumStart = ETHER_MAC_HDR_LEN + IP_HDR_LEN;
43034 + /* UDP Checksum Write Position */
43035 + TcpSumWrite = TcpSumStart + UDP_CSUM_OFFS;
43038 + if ((Ctrl) && (pLETab->Bmu.RxTx.TcpWp != TcpSumWrite)) {
43039 + /* Update the last value of the write position */
43040 + pLETab->Bmu.RxTx.TcpWp = TcpSumWrite;
43042 + /* Set the Lock field for this LE: */
43043 + /* Checksum calculation for one packet only */
43044 + TXLE_SET_LCKCS(pLE, 1);
43046 + /* Set the start position for checksum. */
43047 + TXLE_SET_STACS(pLE, TcpSumStart);
43049 + /* Set the position where the checksum will be writen */
43050 + TXLE_SET_WRICS(pLE, TcpSumWrite);
43052 + /* Set the initial value for checksum */
43053 + /* PseudoHeader CS passed from Linux -> 0! */
43054 + TXLE_SET_INICS(pLE, 0);
43056 + /* Set the opcode for tcp checksum */
43057 + TXLE_SET_OPC(pLE, OP_TCPLISW | HW_OWNER);
43059 + /* Flush the LE to memory */
43062 + /* get a new LE because we filled one with data for checksum */
43063 + GET_TX_LE(pLE, pLETab);
43065 + } /* end TCP offload handling */
43067 + TXLE_SET_ADDR(pLE, LowAddress);
43068 + TXLE_SET_LEN(pLE, pFrag->FragLen);
43070 + if (SetOpcodePacketFlag){
43071 +#ifdef NETIF_F_TSO
43073 + OpCode = OP_LARGESEND | HW_OWNER;
43076 + OpCode = OP_PACKET| HW_OWNER;
43077 +#ifdef NETIF_F_TSO
43080 + SetOpcodePacketFlag = SK_FALSE;
43082 + /* Follow packet in a sequence has always OP_BUFFER */
43083 + OpCode = OP_BUFFER | HW_OWNER;
43086 + /* Check if the low address is near the upper limit. */
43087 + CHECK_LOW_ADDRESS(pLETab->BufHighAddr, LowAddress, pFrag->FragLen);
43089 + pFrag = pFrag->pNext;
43090 + if (pFrag == NULL) {
43091 + /* mark last fragment */
43094 + TXLE_SET_CTRL(pLE, Ctrl);
43095 + TXLE_SET_OPC(pLE, OpCode);
43098 + SK_DBG_DUMP_TX_LE(pLE);
43102 + ** Remember next LE for tx complete
43104 + pSkPacket->NextLE = GET_PUT_IDX(pLETab);
43105 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43106 + ("\tNext LE for pkt %p is %d\n", pSkPacket, pSkPacket->NextLE));
43109 + ** Add packet to working packets queue
43111 + PUSH_PKT_AS_LAST_IN_QUEUE(pWorkQueue, pSkPacket);
43114 + ** give transmit start command
43116 + if (HW_FEATURE(pAC, HWF_WA_DEV_42)) {
43117 + spin_lock(&pAC->SetPutIndexLock);
43118 + SkGeY2SetPutIndex(pAC, pAC->IoBase, Y2_PREF_Q_ADDR(Q_XA1,0), &pAC->TxPort[0][0].TxALET);
43119 + spin_unlock(&pAC->SetPutIndexLock);
43121 + /* write put index */
43123 + SK_OUT32(pAC->IoBase,
43124 + Y2_PREF_Q_ADDR(Q_XA1,PREF_UNIT_PUT_IDX_REG),
43125 + GET_PUT_IDX(&pAC->TxPort[0][0].TxALET));
43126 + UPDATE_HWPUT_IDX(&pAC->TxPort[0][0].TxALET);
43128 + SK_OUT32(pAC->IoBase,
43129 + Y2_PREF_Q_ADDR(Q_XA2, PREF_UNIT_PUT_IDX_REG),
43130 + GET_PUT_IDX(&pAC->TxPort[1][0].TxALET));
43131 + UPDATE_HWPUT_IDX(&pAC->TxPort[1][0].TxALET);
43135 + if (IS_Q_EMPTY(&(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting))) {
43136 + break; /* get out of while */
43138 + POP_FIRST_PKT_FROM_QUEUE(pWaitQueue, pSkPacket);
43139 + } /* while (pSkPacket != NULL) */
43141 + spin_unlock_irqrestore(&pAC->TxQueueLock, LockFlag);
43143 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43144 + ("<== GiveTxBufferToHw\n"));
43146 +} /* GiveTxBufferToHw */
43148 +/***********************************************************************
43150 + * GiveRxBufferToHw - commits a previously allocated DMA area to HW
43153 + * This functions gives receive buffers to HW. If no list elements
43154 + * are available the buffers will be queued.
43157 + * This function can run only once in a system at one time.
43161 +static void GiveRxBufferToHw(
43162 +SK_AC *pAC, /* pointer to adapter control context */
43163 +SK_IOC IoC, /* I/O control context (address of registers) */
43164 +int Port, /* port index for which the buffer is used */
43165 +SK_PACKET *pPacket) /* receive buffer(s) */
43168 + SK_LE_TABLE *pLETab;
43169 + SK_BOOL Done = SK_FALSE; /* at least on LE changed? */
43170 + SK_U32 LowAddress;
43171 + SK_U32 HighAddress;
43172 + SK_U32 PrefetchReg; /* register for Put index */
43173 + unsigned NumFree;
43174 + unsigned Required;
43175 + unsigned long Flags;
43177 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43178 + ("==> GiveRxBufferToHw(Port %c, Packet %p)\n", 'A' + Port, pPacket));
43180 + pLETab = &pAC->RxPort[Port].RxLET;
43183 + PrefetchReg = Y2_PREF_Q_ADDR(Q_R1, PREF_UNIT_PUT_IDX_REG);
43185 + PrefetchReg = Y2_PREF_Q_ADDR(Q_R2, PREF_UNIT_PUT_IDX_REG);
43188 + if (pPacket != NULL) {
43190 + ** For the time being, we have only one packet passed
43191 + ** to this function which might be changed in future!
43193 + PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket);
43197 + ** now pPacket contains the very first waiting packet
43199 + POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket);
43200 + while (pPacket != NULL) {
43201 + if (HW_FEATURE(pAC, HWF_WA_DEV_420)) {
43202 + if (NbrRxBuffersInHW >= MAX_NBR_RX_BUFFERS_IN_HW) {
43203 + PUSH_PKT_AS_FIRST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket);
43204 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43205 + ("<== GiveRxBufferToHw()\n"));
43208 + NbrRxBuffersInHW++;
43211 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43212 + ("Try to add packet %p\n", pPacket));
43215 + ** Check whether we have enough listelements:
43217 + ** we have to take into account that each fragment
43218 + ** may need an additional list element for the high
43219 + ** part of the address here I simplified it by
43220 + ** using MAX_FRAG_OVERHEAD maybe it's worth to split
43221 + ** this constant for Rx and Tx or to calculate the
43222 + ** real number of needed LE's
43224 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43225 + ("\tNum %d Put %d Done %d Free %d %d\n",
43226 + pLETab->Num, pLETab->Put, pLETab->Done,
43227 + NUM_FREE_LE_IN_TABLE(pLETab),
43228 + (NUM_FREE_LE_IN_TABLE(pLETab))));
43230 + Required = pPacket->NumFrags + MAX_FRAG_OVERHEAD;
43231 + NumFree = NUM_FREE_LE_IN_TABLE(pLETab);
43236 + if (Required > NumFree ) {
43237 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
43238 + SK_DBGCAT_DRV_RX_PROGRESS | SK_DBGCAT_DRV_ERROR,
43239 + ("\tOut of LEs have %d need %d\n",
43240 + NumFree, Required));
43242 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43243 + ("\tWaitQueue starts with packet %p\n", pPacket));
43244 + PUSH_PKT_AS_FIRST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket);
43247 + ** write Put index to BMU or Polling Unit and make the LE's
43248 + ** available for the hardware
43250 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43251 + ("\tWrite new Put Idx\n"));
43253 + SK_OUT32(IoC, PrefetchReg, GET_PUT_IDX(pLETab));
43254 + UPDATE_HWPUT_IDX(pLETab);
43256 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43257 + ("<== GiveRxBufferToHw()\n"));
43260 + if (!AllocAndMapRxBuffer(pAC, pPacket, Port)) {
43262 + ** Failure while allocating sk_buff might
43263 + ** be due to temporary short of resources
43264 + ** Maybe next time buffers are available.
43265 + ** Until this, the packet remains in the
43266 + ** RX waiting queue...
43268 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
43269 + SK_DBGCAT_DRV_RX_PROGRESS | SK_DBGCAT_DRV_ERROR,
43270 + ("Failed to allocate Rx buffer\n"));
43272 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43273 + ("WaitQueue starts with packet %p\n", pPacket));
43274 + PUSH_PKT_AS_FIRST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket);
43277 + ** write Put index to BMU or Polling
43278 + ** Unit and make the LE's
43279 + ** available for the hardware
43281 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43282 + ("\tWrite new Put Idx\n"));
43284 + SK_OUT32(IoC, PrefetchReg, GET_PUT_IDX(pLETab));
43285 + UPDATE_HWPUT_IDX(pLETab);
43287 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43288 + ("<== GiveRxBufferToHw()\n"));
43294 + LowAddress = (SK_U32) (pPacket->pFrag->pPhys & 0xffffffff);
43295 + HighAddress = (SK_U32) (pPacket->pFrag->pPhys >> 32);
43296 + if (HighAddress != pLETab->BufHighAddr) {
43297 + /* get a new LE for high address */
43298 + GET_RX_LE(pLE, pLETab);
43300 + /* Set now the 32 high bits of the address */
43301 + RXLE_SET_ADDR(pLE, HighAddress);
43303 + /* Set the control bits of the address */
43304 + RXLE_SET_CTRL(pLE, 0);
43306 + /* Set the opcode into the LE */
43307 + RXLE_SET_OPC(pLE, (OP_ADDR64 | HW_OWNER));
43309 + /* Flush the LE to memory */
43312 + /* remember the HighAddress we gave to the Hardware */
43313 + pLETab->BufHighAddr = HighAddress;
43317 + ** Fill data into listelement
43319 + GET_RX_LE(pLE, pLETab);
43320 + RXLE_SET_ADDR(pLE, LowAddress);
43321 + RXLE_SET_LEN(pLE, pPacket->pFrag->FragLen);
43322 + RXLE_SET_CTRL(pLE, 0);
43323 + RXLE_SET_OPC(pLE, (OP_PACKET | HW_OWNER));
43326 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43327 + ("=== LE filled\n"));
43329 + SK_DBG_DUMP_RX_LE(pLE);
43332 + ** Remember next LE for rx complete
43334 + pPacket->NextLE = GET_PUT_IDX(pLETab);
43336 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43337 + ("\tPackets Next LE is %d\n", pPacket->NextLE));
43340 + ** Add packet to working receive buffer queue and get
43341 + ** any next packet out of the waiting queue
43343 + PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_working, pPacket);
43344 + if (IS_Q_EMPTY(&(pAC->RxPort[Port].RxQ_waiting))) {
43345 + break; /* get out of while processing */
43347 + POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket);
43350 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43351 + ("\tWaitQueue is empty\n"));
43355 + ** write Put index to BMU or Polling Unit and make the LE's
43356 + ** available for the hardware
43358 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43359 + ("\tWrite new Put Idx\n"));
43361 + /* Speed enhancement for a2 chipsets */
43362 + if (HW_FEATURE(pAC, HWF_WA_DEV_42)) {
43363 + spin_lock_irqsave(&pAC->SetPutIndexLock, Flags);
43364 + SkGeY2SetPutIndex(pAC, pAC->IoBase, Y2_PREF_Q_ADDR(Q_R1,0), pLETab);
43365 + spin_unlock_irqrestore(&pAC->SetPutIndexLock, Flags);
43367 + /* write put index */
43370 + Y2_PREF_Q_ADDR(Q_R1, PREF_UNIT_PUT_IDX_REG),
43371 + GET_PUT_IDX(pLETab));
43374 + Y2_PREF_Q_ADDR(Q_R2, PREF_UNIT_PUT_IDX_REG),
43375 + GET_PUT_IDX(pLETab));
43378 + /* Update put index */
43379 + UPDATE_HWPUT_IDX(pLETab);
43383 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43384 + ("<== GiveRxBufferToHw()\n"));
43385 +} /* GiveRxBufferToHw */
43387 +/***********************************************************************
43389 + * FillReceiveTableYukon2 - map any waiting RX buffers to HW
43392 + * If the list element table contains more empty elements than
43393 + * specified this function tries to refill them.
43396 + * This function can run only once per port in a system at one time.
43400 +void FillReceiveTableYukon2(
43401 +SK_AC *pAC, /* pointer to adapter control context */
43402 +SK_IOC IoC, /* I/O control context */
43403 +int Port) /* port index of RX */
43405 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43406 + ("==> FillReceiveTableYukon2 (Port %c)\n", 'A' + Port));
43408 + if (NUM_FREE_LE_IN_TABLE(&pAC->RxPort[Port].RxLET) >
43409 + pAC->MaxUnusedRxLeWorking) {
43412 + ** Give alle waiting receive buffers down
43413 + ** The queue holds all RX packets that
43414 + ** need a fresh allocation of the sk_buff.
43416 + if (pAC->RxPort[Port].RxQ_waiting.pHead != NULL) {
43417 + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43418 + ("Waiting queue is not empty -> give it to HW"));
43419 + GiveRxBufferToHw(pAC, IoC, Port, NULL);
43423 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43424 + ("<== FillReceiveTableYukon2 ()\n"));
43425 +} /* FillReceiveTableYukon2 */
43427 +/******************************************************************************
43430 + * HandleReceives - will pass any ready RX packet to kernel
43433 + * This functions handles a received packet. It checks wether it is
43434 + * valid, updates the receive list element table and gives the receive
43435 + * buffer to Linux
43438 + * This function can run only once per port at one time in the system.
43442 +static SK_BOOL HandleReceives(
43443 +SK_AC *pAC, /* adapter control context */
43444 +int Port, /* port on which a packet has been received */
43445 +SK_U16 Len, /* number of bytes which was actually received */
43446 +SK_U32 FrameStatus, /* MAC frame status word */
43447 +SK_U16 Tcp1, /* first hw checksum */
43448 +SK_U16 Tcp2, /* second hw checksum */
43449 +SK_U32 Tist, /* timestamp */
43450 +SK_U16 Vlan) /* Vlan Id */
43453 + SK_PACKET *pSkPacket;
43454 + SK_LE_TABLE *pLETab;
43455 + SK_MBUF *pRlmtMbuf; /* buffer for giving RLMT frame */
43456 + struct sk_buff *pMsg; /* ptr to message holding frame */
43458 + struct sk_buff *pNewMsg; /* used when IP aligning */
43461 + SK_BOOL IsGoodPkt;
43464 + SK_EVPARA EvPara; /* an event parameter union */
43465 + SK_I16 LenToFree; /* must be signed integer */
43467 + unsigned long Flags; /* for spin lock */
43468 + unsigned int RlmtNotifier;
43469 + unsigned short Type;
43470 + int IpFrameLength;
43471 + int FrameLength; /* total length of recvd frame */
43472 + int HeaderLength;
43477 +#ifdef Y2_SYNC_CHECK
43481 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43482 + ("==> HandleReceives (Port %c)\n", 'A' + Port));
43485 + ** initialize vars for selected port
43487 + pLETab = &pAC->RxPort[Port].RxLET;
43490 + ** check whether we want to receive this packet
43492 + SK_Y2_RXSTAT_CHECK_PKT(Len, FrameStatus, IsGoodPkt);
43495 + ** Remember length to free (in case of RxBuffer overruns;
43496 + ** unlikely, but might happen once in a while)
43498 + LenToFree = (SK_I16) Len;
43501 + ** maybe we put these two checks into the SK_RXDESC_CHECK_PKT macro too
43503 + if (Len > pAC->RxPort[Port].RxBufSize) {
43504 + IsGoodPkt = SK_FALSE;
43508 + ** take first receive buffer out of working queue
43510 + POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_working, pSkPacket);
43511 + if (pSkPacket == NULL) {
43512 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
43513 + SK_DBGCAT_DRV_ERROR,
43514 + ("Packet not available. NULL pointer.\n"));
43518 + if (HW_FEATURE(pAC, HWF_WA_DEV_420)) {
43519 + NbrRxBuffersInHW--;
43523 + ** Verify the received length of the frame! Note that having
43524 + ** multiple RxBuffers being aware of one single receive packet
43525 + ** (one packet spread over multiple RxBuffers) is not supported
43526 + ** by this driver!
43528 + if ((Len > pAC->RxPort[Port].RxBufSize) ||
43529 + (Len > (SK_U16) pSkPacket->PacketLen)) {
43530 + IsGoodPkt = SK_FALSE;
43534 + ** Reset own bit in LE's between old and new Done index
43535 + ** This is not really necessary but makes debugging easier
43537 + CLEAR_LE_OWN_FROM_DONE_TO(pLETab, pSkPacket->NextLE);
43540 + ** Free the list elements for new Rx buffers
43542 + SET_DONE_INDEX(pLETab, pSkPacket->NextLE);
43543 + pMsg = pSkPacket->pMBuf;
43544 + FrameLength = Len;
43546 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43547 + ("Received frame of length %d on port %d\n",FrameLength, Port));
43549 + if (!IsGoodPkt) {
43551 + ** release the DMA mapping
43553 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5)
43554 + pci_dma_sync_single(pAC->PciDev,
43555 + (dma_addr_t) pSkPacket->pFrag->pPhys,
43556 + pSkPacket->pFrag->FragLen,
43557 + PCI_DMA_FROMDEVICE);
43560 + pci_dma_sync_single_for_cpu(pAC->PciDev,
43561 + (dma_addr_t) pSkPacket->pFrag->pPhys,
43562 + pSkPacket->pFrag->FragLen,
43563 + PCI_DMA_FROMDEVICE);
43566 + DEV_KFREE_SKB_ANY(pSkPacket->pMBuf);
43567 + PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pSkPacket);
43568 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43569 + ("<== HandleReceives (Port %c)\n", 'A' + Port));
43572 + ** Sanity check for RxBuffer overruns...
43574 + LenToFree = LenToFree - (pSkPacket->pFrag->FragLen);
43575 + while (LenToFree > 0) {
43576 + POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_working, pSkPacket);
43577 + if (HW_FEATURE(pAC, HWF_WA_DEV_420)) {
43578 + NbrRxBuffersInHW--;
43580 + CLEAR_LE_OWN_FROM_DONE_TO(pLETab, pSkPacket->NextLE);
43581 + SET_DONE_INDEX(pLETab, pSkPacket->NextLE);
43582 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5)
43583 + pci_dma_sync_single(pAC->PciDev,
43584 + (dma_addr_t) pSkPacket->pFrag->pPhys,
43585 + pSkPacket->pFrag->FragLen,
43586 + PCI_DMA_FROMDEVICE);
43588 + pci_dma_sync_single_for_device(pAC->PciDev,
43589 + (dma_addr_t) pSkPacket->pFrag->pPhys,
43590 + pSkPacket->pFrag->FragLen,
43591 + PCI_DMA_FROMDEVICE);
43594 + DEV_KFREE_SKB_ANY(pSkPacket->pMBuf);
43595 + PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pSkPacket);
43596 + LenToFree = LenToFree - ((SK_I16)(pSkPacket->pFrag->FragLen));
43598 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
43599 + SK_DBGCAT_DRV_RX_PROGRESS | SK_DBGCAT_DRV_ERROR,
43600 + ("<==HandleReceives (Port %c) drop faulty len pkt(2)\n",'A'+Port));
43605 + ** Release the DMA mapping
43607 + pci_unmap_single(pAC->PciDev,
43608 + pSkPacket->pFrag->pPhys,
43609 + pAC->RxPort[Port].RxBufSize,
43610 + PCI_DMA_FROMDEVICE);
43612 + skb_put(pMsg, FrameLength); /* set message len */
43613 + pMsg->ip_summed = CHECKSUM_NONE; /* initial default */
43615 +#ifdef Y2_SYNC_CHECK
43616 + pAC->FramesWithoutSyncCheck++;
43617 + if (pAC->FramesWithoutSyncCheck > Y2_RESYNC_WATERMARK) {
43618 + if ((Tcp1 != 1) || (Tcp2 != 0)) {
43619 + pAC->FramesWithoutSyncCheck = 0;
43620 + MyTcp = (SK_U16) SkCsCalculateChecksum(
43622 + FrameLength - 14);
43623 + if (MyTcp != Tcp1) {
43624 + /* Queue port reset event */
43625 + SkLocalEventQueue(pAC, SKGE_DRV,
43626 + SK_DRV_RECOVER,Port,-1,SK_FALSE);
43632 + if (pAC->RxPort[Port].UseRxCsum) {
43633 + Type = ntohs(*((short*)&pMsg->data[12]));
43634 + if (Type == 0x800) {
43635 + *((char *)&(IpFrameLength)) = pMsg->data[16];
43636 + *(((char *)&(IpFrameLength))+1) = pMsg->data[17];
43637 + IpFrameLength = ntohs(IpFrameLength);
43638 + HeaderLength = FrameLength - IpFrameLength;
43639 + if (HeaderLength == 0xe) {
43641 + SkCsGetReceiveInfo(pAC,&pMsg->data[14],Tcp1,Tcp2, Port);
43642 + if ((Result == SKCS_STATUS_IP_FRAGMENT) ||
43643 + (Result == SKCS_STATUS_IP_CSUM_OK) ||
43644 + (Result == SKCS_STATUS_TCP_CSUM_OK) ||
43645 + (Result == SKCS_STATUS_UDP_CSUM_OK)) {
43646 + pMsg->ip_summed = CHECKSUM_UNNECESSARY;
43647 + } else if ((Result == SKCS_STATUS_TCP_CSUM_ERROR) ||
43648 + (Result == SKCS_STATUS_UDP_CSUM_ERROR) ||
43649 + (Result == SKCS_STATUS_IP_CSUM_ERROR_UDP) ||
43650 + (Result == SKCS_STATUS_IP_CSUM_ERROR_TCP) ||
43651 + (Result == SKCS_STATUS_IP_CSUM_ERROR)) {
43652 + SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
43653 + SK_DBGCAT_DRV_RX_PROGRESS | SK_DBGCAT_DRV_ERROR,
43654 + ("skge: CRC error. Frame dropped!\n"));
43655 + DEV_KFREE_SKB_ANY(pMsg);
43656 + PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pSkPacket);
43657 + SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_RX_PROGRESS,
43658 + ("<==HandleReceives(Port %c)\n",'A'+Port));
43661 + pMsg->ip_summed = CHECKSUM_NONE;
43663 + } /* end if (HeaderLength == valid) */
43664 + } /* end if (Type == 0x800) -> IP frame */
43665 + } /* end if (pRxPort->UseRxCsum) */
43667 + SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
43668 + SK_DBGCAT_DRV_RX_PROGRESS,("V"));
43669 + RlmtNotifier = SK_RLMT_RX_PROTOCOL;
43671 + IsBc = (FrameStatus & GMR_FS_BC) ? SK_TRUE : SK_FALSE;
43672 + SK_RLMT_PRE_LOOKAHEAD(pAC,Port,FrameLength,
43673 + IsBc,&Offset,&NumBytes);
43674 + if (NumBytes != 0) {
43675 + IsMc = (FrameStatus & GMR_FS_MC) ? SK_TRUE : SK_FALSE;
43676 + SK_RLMT_LOOKAHEAD(pAC,Port,&pMsg->data[Offset],
43677 + IsBc,IsMc,&RlmtNotifier);
43680 + if (RlmtNotifier == SK_RLMT_RX_PROTOCOL) {
43681 + SK_DBG_MSG(NULL,SK_DBGMOD_DRV,
43682 + SK_DBGCAT_DRV_RX_PROGRESS,("W"));
43683 + if ((Port == pAC->ActivePort)||(pAC->RlmtNets == 2)) {
43684 + /* send up only frames from active port */
43685 + SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
43686 + SK_DBGCAT_DRV_RX_PROGRESS,("U"));
43688 + DumpMsg(pMsg, "Rx");
43690 + SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC,
43691 + FrameLength, Port);
43693 + pNewMsg = alloc_skb(pMsg->len, GFP_ATOMIC);
43694 + skb_reserve(pNewMsg, 2); /* to align IP */
43695 + SK_MEMCPY(pNewMsg->data,pMsg->data,pMsg->len);
43696 + pNewMsg->ip_summed = pMsg->ip_summed;
43697 + skb_put(pNewMsg, pMsg->len);
43698 + DEV_KFREE_SKB_ANY(pMsg);
43701 + pMsg->dev = pAC->dev[Port];
43702 + pMsg->protocol = eth_type_trans(pMsg,
43704 +#ifdef CONFIG_SK98LIN_NAPI
43705 + netif_receive_skb(pMsg);
43709 + pAC->dev[Port]->last_rx = jiffies;
43710 + } else { /* drop frame */
43711 + SK_DBG_MSG(NULL,SK_DBGMOD_DRV,
43712 + SK_DBGCAT_DRV_RX_PROGRESS,("D"));
43713 + DEV_KFREE_SKB_ANY(pMsg);
43715 + } else { /* This is an RLMT-packet! */
43716 + SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
43717 + SK_DBGCAT_DRV_RX_PROGRESS,("R"));
43718 + pRlmtMbuf = SkDrvAllocRlmtMbuf(pAC,
43719 + pAC->IoBase, FrameLength);
43720 + if (pRlmtMbuf != NULL) {
43721 + pRlmtMbuf->pNext = NULL;
43722 + pRlmtMbuf->Length = FrameLength;
43723 + pRlmtMbuf->PortIdx = Port;
43724 + EvPara.pParaPtr = pRlmtMbuf;
43725 + SK_MEMCPY((char*)(pRlmtMbuf->pData),
43726 + (char*)(pMsg->data),FrameLength);
43728 +#ifdef CONFIG_SK98LIN_NAPI
43729 + spin_lock_irqsave(&pAC->SlowPathLock, Flags);
43731 + SkEventQueue(pAC, SKGE_RLMT,
43732 + SK_RLMT_PACKET_RECEIVED,
43734 + pAC->CheckQueue = SK_TRUE;
43735 +#ifdef CONFIG_SK98LIN_NAPI
43736 + spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
43738 + SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
43739 + SK_DBGCAT_DRV_RX_PROGRESS,("Q"));
43741 + if (pAC->dev[Port]->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
43743 + pNewMsg = alloc_skb(pMsg->len, GFP_ATOMIC);
43744 + skb_reserve(pNewMsg, 2); /* to align IP */
43745 + SK_MEMCPY(pNewMsg->data,pMsg->data,pMsg->len);
43746 + pNewMsg->ip_summed = pMsg->ip_summed;
43747 + pNewMsg->len = pMsg->len;
43748 + DEV_KFREE_SKB_ANY(pMsg);
43751 + pMsg->dev = pAC->dev[Port];
43752 + pMsg->protocol = eth_type_trans(pMsg,pAC->dev[Port]);
43754 + pAC->dev[Port]->last_rx = jiffies;
43756 + DEV_KFREE_SKB_ANY(pMsg);
43758 + } /* if packet for rlmt */
43759 + PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pSkPacket);
43760 + } /* end if-else (IsGoodPkt) */
43762 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43763 + ("<== HandleReceives (Port %c)\n", 'A' + Port));
43766 +} /* HandleReceives */
43768 +/***********************************************************************
43770 + * CheckForSendComplete - Frees any freeable Tx bufffer
43773 + * This function checks the queues of a port for completed send
43774 + * packets and returns these packets back to the OS.
43777 + * This function can run simultaneously for both ports if
43778 + * the OS function OSReturnPacket() can handle this,
43780 + * Such a send complete does not mean, that the packet is really
43781 + * out on the wire. We just know that the adapter has copied it
43782 + * into its internal memory and the buffer in the systems memory
43783 + * is no longer needed.
43787 +static void CheckForSendComplete(
43788 +SK_AC *pAC, /* pointer to adapter control context */
43789 +SK_IOC IoC, /* I/O control context */
43790 +int Port, /* port index */
43791 +SK_PKT_QUEUE *pPQ, /* tx working packet queue to check */
43792 +SK_LE_TABLE *pLETab, /* corresponding list element table */
43793 +unsigned int Done) /* done index reported for this LET */
43795 + SK_PACKET *pSkPacket;
43796 + SK_PKT_QUEUE SendCmplPktQ = { NULL, NULL, SPIN_LOCK_UNLOCKED };
43797 + SK_BOOL DoWakeQueue = SK_FALSE;
43798 + unsigned long Flags;
43801 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43802 + ("==> CheckForSendComplete(Port %c)\n", 'A' + Port));
43805 + ** Reset own bit in LE's between old and new Done index
43806 + ** This is not really necessairy but makes debugging easier
43808 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43809 + ("Clear Own Bits in TxTable from %d to %d\n",
43810 + pLETab->Done, (Done == 0) ?
43811 + NUM_LE_IN_TABLE(pLETab) :
43814 + spin_lock_irqsave(&(pPQ->QueueLock), Flags);
43816 + CLEAR_LE_OWN_FROM_DONE_TO(pLETab, Done);
43818 + Put = GET_PUT_IDX(pLETab);
43821 + ** Check whether some packets have been completed
43823 + PLAIN_POP_FIRST_PKT_FROM_QUEUE(pPQ, pSkPacket);
43824 + while (pSkPacket != NULL) {
43826 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43827 + ("Check Completion of Tx packet %p\n", pSkPacket));
43828 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43829 + ("Put %d NewDone %d NextLe of Packet %d\n", Put, Done,
43830 + pSkPacket->NextLE));
43832 + if ((Put > Done) &&
43833 + ((pSkPacket->NextLE > Put) || (pSkPacket->NextLE <= Done))) {
43834 + PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(&SendCmplPktQ, pSkPacket);
43835 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43836 + ("Packet finished (a)\n"));
43837 + } else if ((Done > Put) &&
43838 + (pSkPacket->NextLE > Put) && (pSkPacket->NextLE <= Done)) {
43839 + PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(&SendCmplPktQ, pSkPacket);
43840 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43841 + ("Packet finished (b)\n"));
43842 + } else if ((Done == TXA_MAX_LE-1) && (Put == 0) && (pSkPacket->NextLE == 0)) {
43843 + PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(&SendCmplPktQ, pSkPacket);
43844 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43845 + ("Packet finished (b)\n"));
43846 + DoWakeQueue = SK_TRUE;
43847 + } else if (Done == Put) {
43848 + /* all packets have been sent */
43849 + PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(&SendCmplPktQ, pSkPacket);
43850 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43851 + ("Packet finished (c)\n"));
43853 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43854 + ("Packet not yet finished\n"));
43855 + PLAIN_PUSH_PKT_AS_FIRST_IN_QUEUE(pPQ, pSkPacket);
43858 + PLAIN_POP_FIRST_PKT_FROM_QUEUE(pPQ, pSkPacket);
43860 + spin_unlock_irqrestore(&(pPQ->QueueLock), Flags);
43863 + ** Set new done index in list element table
43865 + SET_DONE_INDEX(pLETab, Done);
43868 + ** All TX packets that are send complete should be added to
43869 + ** the free queue again for new sents to come
43871 + pSkPacket = SendCmplPktQ.pHead;
43872 + while (pSkPacket != NULL) {
43873 + while (pSkPacket->pFrag != NULL) {
43874 + pci_unmap_page(pAC->PciDev,
43875 + (dma_addr_t) pSkPacket->pFrag->pPhys,
43876 + pSkPacket->pFrag->FragLen,
43877 + PCI_DMA_FROMDEVICE);
43878 + pSkPacket->pFrag = pSkPacket->pFrag->pNext;
43881 + DEV_KFREE_SKB_ANY(pSkPacket->pMBuf);
43882 + pSkPacket->pMBuf = NULL;
43883 + pSkPacket = pSkPacket->pNext; /* get next packet */
43887 + ** Append the available TX packets back to free queue
43889 + if (SendCmplPktQ.pHead != NULL) {
43890 + spin_lock_irqsave(&(pAC->TxPort[Port][0].TxQ_free.QueueLock), Flags);
43891 + if (pAC->TxPort[Port][0].TxQ_free.pTail != NULL) {
43892 + pAC->TxPort[Port][0].TxQ_free.pTail->pNext = SendCmplPktQ.pHead;
43893 + pAC->TxPort[Port][0].TxQ_free.pTail = SendCmplPktQ.pTail;
43894 + if (pAC->TxPort[Port][0].TxQ_free.pHead->pNext == NULL) {
43895 + netif_wake_queue(pAC->dev[Port]);
43898 + pAC->TxPort[Port][0].TxQ_free.pHead = SendCmplPktQ.pHead;
43899 + pAC->TxPort[Port][0].TxQ_free.pTail = SendCmplPktQ.pTail;
43900 + netif_wake_queue(pAC->dev[Port]);
43902 + if (Done == Put) {
43903 + netif_wake_queue(pAC->dev[Port]);
43905 + if (DoWakeQueue) {
43906 + netif_wake_queue(pAC->dev[Port]);
43907 + DoWakeQueue = SK_FALSE;
43909 + spin_unlock_irqrestore(&pAC->TxPort[Port][0].TxQ_free.QueueLock, Flags);
43912 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43913 + ("<== CheckForSendComplete()\n"));
43916 +} /* CheckForSendComplete */
43918 +/*****************************************************************************
43920 + * UnmapAndFreeTxPktBuffer
43923 + * This function free any allocated space of receive buffers
43926 + * pAC - A pointer to the adapter context struct.
43929 +static void UnmapAndFreeTxPktBuffer(
43930 +SK_AC *pAC, /* pointer to adapter context */
43931 +SK_PACKET *pSkPacket, /* pointer to port struct of ring to fill */
43932 +int TxPort) /* TX port index */
43934 + SK_FRAG *pFrag = pSkPacket->pFrag;
43936 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43937 + ("--> UnmapAndFreeTxPktBuffer\n"));
43939 + while (pFrag != NULL) {
43940 + pci_unmap_page(pAC->PciDev,
43941 + (dma_addr_t) pFrag->pPhys,
43943 + PCI_DMA_FROMDEVICE);
43944 + pFrag = pFrag->pNext;
43947 + DEV_KFREE_SKB_ANY(pSkPacket->pMBuf);
43948 + pSkPacket->pMBuf = NULL;
43950 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43951 + ("<-- UnmapAndFreeTxPktBuffer\n"));
43954 +/*****************************************************************************
43956 + * HandleStatusLEs
43959 + * This function checks for any new status LEs that may have been
43960 + * received. Those status LEs may either be Rx or Tx ones.
43964 +static SK_BOOL HandleStatusLEs(
43965 +#ifdef CONFIG_SK98LIN_NAPI
43966 +SK_AC *pAC, /* pointer to adapter context */
43967 +int *WorkDone, /* Done counter needed for NAPI */
43968 +int WorkToDo) /* ToDo counter for NAPI */
43970 +SK_AC *pAC) /* pointer to adapter context */
43973 + int DoneTxA[SK_MAX_MACS];
43974 + int DoneTxS[SK_MAX_MACS];
43976 + SK_BOOL handledStatLE = SK_FALSE;
43977 + SK_BOOL NewDone = SK_FALSE;
43984 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
43985 + ("==> HandleStatusLEs\n"));
43988 + if (OWN_OF_FIRST_LE(&pAC->StatusLETable) != HW_OWNER)
43991 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
43992 + ("Check next Own Bit of ST-LE[%d]: 0x%li \n",
43993 + (pAC->StatusLETable.Done + 1) % NUM_LE_IN_TABLE(&pAC->StatusLETable),
43994 + OWN_OF_FIRST_LE(&pAC->StatusLETable)));
43996 + while (OWN_OF_FIRST_LE(&pAC->StatusLETable) == HW_OWNER) {
43997 + GET_ST_LE(pLE, &pAC->StatusLETable);
43998 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
43999 + ("Working on finished status LE[%d]:\n",
44000 + GET_DONE_INDEX(&pAC->StatusLETable)));
44001 + SK_DBG_DUMP_ST_LE(pLE);
44002 + handledStatLE = SK_TRUE;
44003 + OpCode = STLE_GET_OPC(pLE) & ~HW_OWNER;
44004 + Port = STLE_GET_LINK(pLE);
44006 +#ifdef USE_TIST_FOR_RESET
44007 + if (SK_ADAPTER_WAITING_FOR_TIST(pAC)) {
44008 + /* do we just have a tist LE ? */
44009 + if ((OpCode & OP_RXTIMESTAMP) == OP_RXTIMESTAMP) {
44010 + for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
44011 + if (SK_PORT_WAITING_FOR_ANY_TIST(pAC, i)) {
44012 + /* if a port is waiting for any tist it is done */
44013 + SK_CLR_STATE_FOR_PORT(pAC, i);
44014 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
44015 + ("Got any Tist on port %c (now 0x%X!!!)\n",
44016 + 'A' + i, pAC->AdapterResetState));
44018 + if (SK_PORT_WAITING_FOR_SPECIFIC_TIST(pAC, i)) {
44019 + Y2_GET_TIST_LOW_VAL(pAC->IoBase, &LowVal);
44020 + if ((pAC->MinTistHi != pAC->GIni.GITimeStampCnt) ||
44021 + (pAC->MinTistLo < LowVal)) {
44022 + /* time is up now */
44023 + SK_CLR_STATE_FOR_PORT(pAC, i);
44024 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
44025 + ("Got expected Tist on Port %c (now 0x%X)!!!\n",
44026 + 'A' + i, pAC->AdapterResetState));
44027 +#ifdef Y2_SYNC_CHECK
44028 + pAC->FramesWithoutSyncCheck =
44029 + Y2_RESYNC_WATERMARK;
44032 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
44033 + ("Got Tist %l:%l on Port %c but still waiting\n",
44034 + pAC->GIni.GITimeStampCnt, pAC->MinTistLo,
44039 +#ifndef Y2_RECOVERY
44040 + if (!SK_ADAPTER_WAITING_FOR_TIST(pAC)) {
44041 + /* nobody needs tist anymore - turn it off */
44042 + Y2_DISABLE_TIST(pAC->IoBase);
44043 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
44044 + ("Turn off Tist !!!\n"));
44047 + } else if (OpCode == OP_TXINDEXLE) {
44049 + * change OpCode to notify the folowing code
44050 + * to ignore the done index from this LE
44051 + * unfortunately tist LEs will be generated only
44053 + * so in order to get a safe Done index for a
44054 + * port currently waiting for a tist we have to
44055 + * get the done index directly from the BMU
44057 + OpCode = OP_MOD_TXINDEX;
44058 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
44059 + ("Mark unusable TX_INDEX LE!!!\n"));
44061 + if (SK_PORT_WAITING_FOR_TIST(pAC, Port)) {
44062 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
44063 + ("Ignore LE 0x%X on Port %c!!!\n",
44064 + OpCode, 'A' + Port));
44065 + OpCode = OP_MOD_LE;
44066 +#ifdef Y2_LE_CHECK
44067 + /* mark entries invalid */
44068 + pAC->LastOpc = 0xFF;
44069 + pAC->LastPort = 3;
44073 + } /* if (SK_ADAPTER_WAITING_FOR_TIST(pAC)) */
44080 +#ifdef Y2_LE_CHECK
44081 + if (pAC->LastOpc != 0xFF) {
44082 + /* last opc is valid
44083 + * check if current opcode follows last opcode
44085 + if ((((OpCode & OP_RXTIMESTAMP) == OP_RXTIMESTAMP) && (pAC->LastOpc != OP_RXSTAT)) ||
44086 + (((OpCode & OP_RXCHKS) == OP_RXCHKS) && (pAC->LastOpc != OP_RXTIMESTAMP)) ||
44087 + ((OpCode == OP_RXSTAT) && (pAC->LastOpc != OP_RXCHKS))) {
44089 + /* opcode sequence broken
44090 + * current LE is invalid
44093 + if (pAC->LastOpc == OP_RXTIMESTAMP) {
44094 + /* force invalid checksum */
44095 + pLE->St.StUn.StRxTCPCSum.RxTCPSum1 = 1;
44096 + pLE->St.StUn.StRxTCPCSum.RxTCPSum2 = 0;
44097 + OpCode = pAC->LastOpc = OP_RXCHKS;
44098 + Port = pAC->LastPort;
44099 + } else if (pAC->LastOpc == OP_RXCHKS) {
44100 + /* force invalid frame */
44101 + Port = pAC->LastPort;
44102 + pLE->St.Stat.BufLen = 64;
44103 + pLE->St.StUn.StRxStatWord = GMR_FS_CRC_ERR;
44104 + OpCode = pAC->LastOpc = OP_RXSTAT;
44105 +#ifdef Y2_SYNC_CHECK
44106 + /* force rx sync check */
44107 + pAC->FramesWithoutSyncCheck = Y2_RESYNC_WATERMARK;
44109 + } else if (pAC->LastOpc == OP_RXSTAT) {
44110 + /* create dont care tist */
44111 + pLE->St.StUn.StRxTimeStamp = 0;
44112 + OpCode = pAC->LastOpc = OP_RXTIMESTAMP;
44113 + /* dont know the port yet */
44116 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
44117 + ("Unknown LastOpc %X for Timestamp on port %c.\n",
44118 + pAC->LastOpc, Port));
44125 + switch (OpCode) {
44127 +#ifdef Y2_RECOVERY
44128 + pAC->LastOpc = OP_RXSTAT;
44131 + ** This is always the last Status LE belonging
44132 + ** to a received packet -> handle it...
44134 + if ((Port != 0) && (Port != 1)) {
44135 + /* Unknown port */
44136 + panic("sk98lin: Unknown port %d\n",
44143 + STLE_GET_LEN(pLE),
44144 + STLE_GET_FRSTATUS(pLE),
44145 + pAC->StatusLETable.Bmu.Stat.TcpSum1,
44146 + pAC->StatusLETable.Bmu.Stat.TcpSum2,
44147 + pAC->StatusLETable.Bmu.Stat.RxTimeStamp,
44148 + pAC->StatusLETable.Bmu.Stat.VlanId);
44149 +#ifdef CONFIG_SK98LIN_NAPI
44150 + if (*WorkDone >= WorkToDo) {
44157 + /* this value will be used for next RXSTAT */
44158 + pAC->StatusLETable.Bmu.Stat.VlanId = STLE_GET_VLAN(pLE);
44160 + case OP_RXTIMEVLAN:
44161 + /* this value will be used for next RXSTAT */
44162 + pAC->StatusLETable.Bmu.Stat.VlanId = STLE_GET_VLAN(pLE);
44163 + /* fall through */
44164 + case OP_RXTIMESTAMP:
44165 + /* this value will be used for next RXSTAT */
44166 + pAC->StatusLETable.Bmu.Stat.RxTimeStamp = STLE_GET_TIST(pLE);
44167 +#ifdef Y2_RECOVERY
44168 + pAC->LastOpc = OP_RXTIMESTAMP;
44169 + pAC->LastPort = Port;
44172 + case OP_RXCHKSVLAN:
44173 + /* this value will be used for next RXSTAT */
44174 + pAC->StatusLETable.Bmu.Stat.VlanId = STLE_GET_VLAN(pLE);
44175 + /* fall through */
44177 + /* this value will be used for next RXSTAT */
44178 + pAC->StatusLETable.Bmu.Stat.TcpSum1 = STLE_GET_TCP1(pLE);
44179 + pAC->StatusLETable.Bmu.Stat.TcpSum2 = STLE_GET_TCP2(pLE);
44180 +#ifdef Y2_RECOVERY
44181 + pAC->LastPort = Port;
44182 + pAC->LastOpc = OP_RXCHKS;
44185 + case OP_RSS_HASH:
44186 + /* this value will be used for next RXSTAT */
44188 + pAC->StatusLETable.Bmu.Stat.RssHashValue = STLE_GET_RSS(pLE);
44191 + case OP_TXINDEXLE:
44194 + ** it would be possible to check for which queues
44195 + ** the index has been changed and call
44196 + ** CheckForSendComplete() only for such queues
44198 + STLE_GET_DONE_IDX(pLE,LowVal,HighVal);
44199 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
44200 + ("LowVal: 0x%x HighVal: 0x%x\n", LowVal, HighVal));
44203 + ** It would be possible to check whether we really
44204 + ** need the values for second port or sync queue,
44205 + ** but I think checking whether we need them is
44206 + ** more expensive than the calculation
44208 + DoneTxA[0] = STLE_GET_DONE_IDX_TXA1(LowVal,HighVal);
44209 + DoneTxS[0] = STLE_GET_DONE_IDX_TXS1(LowVal,HighVal);
44210 + DoneTxA[1] = STLE_GET_DONE_IDX_TXA2(LowVal,HighVal);
44211 + DoneTxS[1] = STLE_GET_DONE_IDX_TXS2(LowVal,HighVal);
44213 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
44214 + ("DoneTxa1 0x%x DoneTxS1: 0x%x DoneTxa2 0x%x DoneTxS2: 0x%x\n",
44215 + DoneTxA[0], DoneTxS[0], DoneTxA[1], DoneTxS[1]));
44217 + NewDone = SK_TRUE;
44219 +#ifdef USE_TIST_FOR_RESET
44220 + case OP_MOD_TXINDEX:
44221 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
44222 + ("OP_MOD_TXINDEX\n"));
44223 + SK_IN16(pAC->IoBase, Q_ADDR(Q_XA1, Q_DONE), &DoneTxA[0]);
44224 + if (pAC->GIni.GIMacsFound > 1) {
44225 + SK_IN16(pAC->IoBase, Q_ADDR(Q_XA2, Q_DONE), &DoneTxA[1]);
44227 + NewDone = SK_TRUE;
44230 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
44231 + ("Ignore marked LE on port in Reset\n"));
44237 + ** Have to handle the illegal Opcode in Status LE
44239 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
44240 + ("Unexpected OpCode\n"));
44244 +#ifdef Y2_RECOVERY
44245 + OpCode = STLE_GET_OPC(pLE) & ~HW_OWNER;
44246 + STLE_SET_OPC(pLE, OpCode);
44249 + ** Reset own bit we have to do this in order to detect a overflow
44251 + STLE_SET_OPC(pLE, SW_OWNER);
44253 + } /* while (OWN_OF_FIRST_LE(&pAC->StatusLETable) == HW_OWNER) */
44256 + ** Now handle any new transmit complete
44259 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
44260 + ("Done Index for Tx BMU has been changed\n"));
44261 + for (Port = 0; Port < pAC->GIni.GIMacsFound; Port++) {
44263 + ** Do we have a new Done idx ?
44265 + if (DoneTxA[Port] != GET_DONE_INDEX(&pAC->TxPort[Port][0].TxALET)) {
44266 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
44267 + ("Check TxA%d\n", Port + 1));
44268 + CheckForSendComplete(pAC, pAC->IoBase, Port,
44269 + &(pAC->TxPort[Port][0].TxAQ_working),
44270 + &pAC->TxPort[Port][0].TxALET,
44273 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
44274 + ("No changes for TxA%d\n", Port + 1));
44276 +#ifdef USE_SYNC_TX_QUEUE
44277 + if (HW_SYNC_TX_SUPPORTED(pAC)) {
44279 + ** Do we have a new Done idx ?
44281 + if (DoneTxS[Port] !=
44282 + GET_DONE_INDEX(&pAC->TxPort[Port][0].TxSLET)) {
44283 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
44284 + SK_DBGCAT_DRV_INT_SRC,
44285 + ("Check TxS%d\n", Port));
44286 + CheckForSendComplete(pAC, pAC->IoBase, Port,
44287 + &(pAC->TxPort[Port][0].TxSQ_working),
44288 + &pAC->TxPort[Port][0].TxSLET,
44291 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
44292 + SK_DBGCAT_DRV_INT_SRC,
44293 + ("No changes for TxS%d\n", Port));
44299 + NewDone = SK_FALSE;
44302 + ** Check whether we have to refill our RX table
44304 + if (HW_FEATURE(pAC, HWF_WA_DEV_420)) {
44305 + if (NbrRxBuffersInHW < MAX_NBR_RX_BUFFERS_IN_HW) {
44306 + for (Port = 0; Port < pAC->GIni.GIMacsFound; Port++) {
44307 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
44308 + ("Check for refill of RxBuffers on Port %c\n", 'A' + Port));
44309 + FillReceiveTableYukon2(pAC, pAC->IoBase, Port);
44313 + for (Port = 0; Port < pAC->GIni.GIMacsFound; Port++) {
44314 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
44315 + ("Check for refill of RxBuffers on Port %c\n", 'A' + Port));
44316 + if (NUM_FREE_LE_IN_TABLE(&pAC->RxPort[Port].RxLET) >= 64) {
44317 + FillReceiveTableYukon2(pAC, pAC->IoBase, Port);
44321 +#ifdef CONFIG_SK98LIN_NAPI
44322 + if (*WorkDone >= WorkToDo) {
44326 + } while (OWN_OF_FIRST_LE(&pAC->StatusLETable) == HW_OWNER);
44329 + ** Clear status BMU
44331 + if (handledStatLE)
44332 + SK_OUT32(pAC->IoBase, STAT_CTRL, SC_STAT_CLR_IRQ);
44334 + return(handledStatLE);
44335 +} /* HandleStatusLEs */
44337 +/*****************************************************************************
44339 + * AllocateAndInitLETables - allocate memory for the LETable and init
44342 + * This function will allocate space for the LETable and will also
44343 + * initialize them. The size of the tables must have been specified
44347 + * pAC - A pointer to the adapter context struct.
44350 + * SK_TRUE - all LETables initialized
44351 + * SK_FALSE - failed
44353 +static SK_BOOL AllocateAndInitLETables(
44354 +SK_AC *pAC) /* pointer to adapter context */
44356 + char *pVirtMemAddr;
44357 + dma_addr_t pPhysMemAddr = 0;
44360 + unsigned Aligned;
44361 + unsigned Alignment;
44363 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
44364 + ("==> AllocateAndInitLETables()\n"));
44367 + ** Determine how much memory we need with respect to alignment
44369 + Alignment = MAX_LEN_OF_LE_TAB;
44371 + for (CurrMac = 0; CurrMac < pAC->GIni.GIMacsFound; CurrMac++) {
44372 + SK_ALIGN_SIZE(LE_TAB_SIZE(RX_MAX_LE), Alignment, Aligned);
44374 + SK_ALIGN_SIZE(LE_TAB_SIZE(TXA_MAX_LE), Alignment, Aligned);
44376 + SK_ALIGN_SIZE(LE_TAB_SIZE(TXS_MAX_LE), Alignment, Aligned);
44379 + SK_ALIGN_SIZE(LE_TAB_SIZE(ST_MAX_LE), Alignment, Aligned);
44381 + Size += Alignment;
44382 + pAC->SizeOfAlignedLETables = Size;
44384 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
44385 + ("Need %08x bytes in total\n", Size));
44388 + ** Allocate the memory
44390 + pVirtMemAddr = pci_alloc_consistent(pAC->PciDev, Size, &pPhysMemAddr);
44391 + if (pVirtMemAddr == NULL) {
44392 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
44393 + SK_DBGCAT_INIT | SK_DBGCAT_DRV_ERROR,
44394 + ("AllocateAndInitLETables: kernel malloc failed!\n"));
44395 + return (SK_FALSE);
44399 + ** Initialize the memory
44401 + SK_MEMSET(pVirtMemAddr, 0, Size);
44402 + ALIGN_ADDR(pVirtMemAddr, Alignment); /* Macro defined in skgew.h */
44404 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
44405 + ("Virtual address of LETab is %8p!\n", pVirtMemAddr));
44406 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
44407 + ("Phys address of LETab is %8p!\n", (void *) pPhysMemAddr));
44409 + for (CurrMac = 0; CurrMac < pAC->GIni.GIMacsFound; CurrMac++) {
44410 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
44411 + ("RxLeTable for Port %c", 'A' + CurrMac));
44412 + SkGeY2InitSingleLETable(
44414 + &pAC->RxPort[CurrMac].RxLET,
44417 + (SK_U32) (pPhysMemAddr & 0xffffffff),
44418 + (SK_U32) (((SK_U64) pPhysMemAddr) >> 32));
44420 + SK_ALIGN_SIZE(LE_TAB_SIZE(RX_MAX_LE), Alignment, Aligned);
44421 + pVirtMemAddr += Aligned;
44422 + pPhysMemAddr += Aligned;
44424 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
44425 + ("TxALeTable for Port %c", 'A' + CurrMac));
44426 + SkGeY2InitSingleLETable(
44428 + &pAC->TxPort[CurrMac][0].TxALET,
44431 + (SK_U32) (pPhysMemAddr & 0xffffffff),
44432 + (SK_U32) (((SK_U64) pPhysMemAddr) >> 32));
44434 + SK_ALIGN_SIZE(LE_TAB_SIZE(TXA_MAX_LE), Alignment, Aligned);
44435 + pVirtMemAddr += Aligned;
44436 + pPhysMemAddr += Aligned;
44438 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
44439 + ("TxSLeTable for Port %c", 'A' + CurrMac));
44440 + SkGeY2InitSingleLETable(
44442 + &pAC->TxPort[CurrMac][0].TxSLET,
44445 + (SK_U32) (pPhysMemAddr & 0xffffffff),
44446 + (SK_U32) (((SK_U64) pPhysMemAddr) >> 32));
44448 + SK_ALIGN_SIZE(LE_TAB_SIZE(TXS_MAX_LE), Alignment, Aligned);
44449 + pVirtMemAddr += Aligned;
44450 + pPhysMemAddr += Aligned;
44453 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,("StLeTable"));
44455 + SkGeY2InitSingleLETable(
44457 + &pAC->StatusLETable,
44460 + (SK_U32) (pPhysMemAddr & 0xffffffff),
44461 + (SK_U32) (((SK_U64) pPhysMemAddr) >> 32));
44463 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
44464 + ("<== AllocateAndInitLETables(OK)\n"));
44466 +} /* AllocateAndInitLETables */
44468 +/*****************************************************************************
44470 + * AllocatePacketBuffersYukon2 - allocate packet and fragment buffers
44473 + * This function will allocate space for the packets and fragments
44476 + * pAC - A pointer to the adapter context struct.
44479 + * SK_TRUE - Memory was allocated correctly
44480 + * SK_FALSE - An error occured
44482 +static SK_BOOL AllocatePacketBuffersYukon2(
44483 +SK_AC *pAC) /* pointer to adapter context */
44485 + SK_PACKET *pRxPacket;
44486 + SK_PACKET *pTxPacket;
44489 + unsigned long Flags; /* needed for POP/PUSH functions */
44491 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
44492 + ("==> AllocatePacketBuffersYukon2()"));
44494 + for (CurrMac = 0; CurrMac < pAC->GIni.GIMacsFound; CurrMac++) {
44496 + ** Allocate RX packet space, initialize the packets and
44497 + ** add them to the RX waiting queue. Waiting queue means
44498 + ** that packet and fragment are initialized, but no sk_buff
44499 + ** has been assigned to it yet.
44501 + pAC->RxPort[CurrMac].ReceivePacketTable =
44502 + kmalloc((RX_MAX_NBR_BUFFERS * sizeof(SK_PACKET)), GFP_KERNEL);
44504 + if (pAC->RxPort[CurrMac].ReceivePacketTable == NULL) {
44505 + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_INIT | SK_DBGCAT_DRV_ERROR,
44506 + ("AllocatePacketBuffersYukon2: no mem RxPkts (port %i)",CurrMac));
44509 + SK_MEMSET(pAC->RxPort[CurrMac].ReceivePacketTable, 0,
44510 + (RX_MAX_NBR_BUFFERS * sizeof(SK_PACKET)));
44512 + pRxPacket = pAC->RxPort[CurrMac].ReceivePacketTable;
44514 + for (CurrBuff=0;CurrBuff<RX_MAX_NBR_BUFFERS;CurrBuff++) {
44515 + pRxPacket->pFrag = &(pRxPacket->FragArray[0]);
44516 + pRxPacket->NumFrags = 1;
44517 + PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[CurrMac].RxQ_waiting, pRxPacket);
44523 + ** Allocate TX packet space, initialize the packets and
44524 + ** add them to the TX free queue. Free queue means that
44525 + ** packet is available and initialized, but no fragment
44526 + ** has been assigned to it. (Must be done at TX side)
44528 + pAC->TxPort[CurrMac][0].TransmitPacketTable =
44529 + kmalloc((TX_MAX_NBR_BUFFERS * sizeof(SK_PACKET)), GFP_KERNEL);
44531 + if (pAC->TxPort[CurrMac][0].TransmitPacketTable == NULL) {
44532 + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_INIT | SK_DBGCAT_DRV_ERROR,
44533 + ("AllocatePacketBuffersYukon2: no mem TxPkts (port %i)",CurrMac));
44534 + kfree(pAC->RxPort[CurrMac].ReceivePacketTable);
44535 + return(SK_FALSE);
44537 + SK_MEMSET(pAC->TxPort[CurrMac][0].TransmitPacketTable, 0,
44538 + (TX_MAX_NBR_BUFFERS * sizeof(SK_PACKET)));
44540 + pTxPacket = pAC->TxPort[CurrMac][0].TransmitPacketTable;
44542 + for (CurrBuff=0;CurrBuff<TX_MAX_NBR_BUFFERS;CurrBuff++) {
44543 + PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->TxPort[CurrMac][0].TxQ_free, pTxPacket);
44547 + } /* end for (CurrMac = 0; CurrMac < pAC->GIni.GIMacsFound; CurrMac++) */
44549 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
44550 + ("<== AllocatePacketBuffersYukon2 (OK)\n"));
44553 +} /* AllocatePacketBuffersYukon2 */
44555 +/*****************************************************************************
44557 + * FreeLETables - release allocated memory of LETables
44560 + * This function will free all resources of the LETables
44563 + * pAC - A pointer to the adapter context struct.
44567 +static void FreeLETables(
44568 +SK_AC *pAC) /* pointer to adapter control context */
44570 + dma_addr_t pPhysMemAddr;
44571 + char *pVirtMemAddr;
44573 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
44574 + ("==> FreeLETables()\n"));
44577 + ** The RxLETable is the first of all LET.
44578 + ** Therefore we can use its address for the input
44579 + ** of the free function.
44581 + pVirtMemAddr = (char *) pAC->RxPort[0].RxLET.pLETab;
44582 + pPhysMemAddr = (((SK_U64) pAC->RxPort[0].RxLET.pPhyLETABHigh << (SK_U64) 32) |
44583 + ((SK_U64) pAC->RxPort[0].RxLET.pPhyLETABLow));
44585 + /* free continuous memory */
44586 + pci_free_consistent(pAC->PciDev, pAC->SizeOfAlignedLETables,
44587 + pVirtMemAddr, pPhysMemAddr);
44589 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
44590 + ("<== FreeLETables()\n"));
44591 +} /* FreeLETables */
44593 +/*****************************************************************************
44595 + * FreePacketBuffers - free's all packet buffers of an adapter
44598 + * This function will free all previously allocated memory of the
44599 + * packet buffers.
44602 + * pAC - A pointer to the adapter context struct.
44606 +static void FreePacketBuffers(
44607 +SK_AC *pAC) /* pointer to adapter control context */
44611 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
44612 + ("==> FreePacketBuffers()\n"));
44614 + for (Port = 0; Port < pAC->GIni.GIMacsFound; Port++) {
44615 + kfree(pAC->RxPort[Port].ReceivePacketTable);
44616 + kfree(pAC->TxPort[Port][0].TransmitPacketTable);
44619 + SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
44620 + ("<== FreePacketBuffers()\n"));
44621 +} /* FreePacketBuffers */
44623 +/*****************************************************************************
44625 + * AllocAndMapRxBuffer - fill one buffer into the receive packet/fragment
44628 + * The function allocates a new receive buffer and assigns it to the
44629 + * the passsed receive packet/fragment
44632 + * SK_TRUE - a buffer was allocated and assigned
44633 + * SK_FALSE - a buffer could not be added
44635 +static SK_BOOL AllocAndMapRxBuffer(
44636 +SK_AC *pAC, /* pointer to the adapter control context */
44637 +SK_PACKET *pSkPacket, /* pointer to packet that is to fill */
44638 +int Port) /* port the packet belongs to */
44640 + struct sk_buff *pMsgBlock; /* pointer to a new message block */
44641 + SK_U64 PhysAddr; /* physical address of a rx buffer */
44643 + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
44644 + ("--> AllocAndMapRxBuffer (Port: %i)\n", Port));
44646 + pMsgBlock = alloc_skb(pAC->RxPort[Port].RxBufSize, GFP_ATOMIC);
44647 + if (pMsgBlock == NULL) {
44648 + SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
44649 + SK_DBGCAT_DRV_RX_PROGRESS | SK_DBGCAT_DRV_ERROR,
44650 + ("%s: Allocation of rx buffer failed !\n",
44651 + pAC->dev[Port]->name));
44652 + SK_PNMI_CNT_NO_RX_BUF(pAC, pAC->RxPort[Port].PortIndex);
44653 + return(SK_FALSE);
44655 + skb_reserve(pMsgBlock, 8);
44657 + PhysAddr = (SK_U64) pci_map_page(pAC->PciDev,
44658 + virt_to_page(pMsgBlock->data),
44659 + ((unsigned long) pMsgBlock->data &
44661 + pAC->RxPort[Port].RxBufSize,
44662 + PCI_DMA_FROMDEVICE);
44664 + pSkPacket->pFrag->pVirt = pMsgBlock->data;
44665 + pSkPacket->pFrag->pPhys = PhysAddr;
44666 + pSkPacket->pFrag->FragLen = pAC->RxPort[Port].RxBufSize; /* for correct unmap */
44667 + pSkPacket->pMBuf = pMsgBlock;
44668 + pSkPacket->PacketLen = pAC->RxPort[Port].RxBufSize;
44670 + SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
44671 + ("<-- AllocAndMapRxBuffer\n"));
44673 + return (SK_TRUE);
44674 +} /* AllocAndMapRxBuffer */
44676 +/*******************************************************************************
44680 + ******************************************************************************/
44681 diff -ruN linux/drivers/net/sk98lin/sky2le.c linux-new/drivers/net/sk98lin/sky2le.c
44682 --- linux/drivers/net/sk98lin/sky2le.c 1970-01-01 01:00:00.000000000 +0100
44683 +++ linux-new/drivers/net/sk98lin/sky2le.c 2006-07-28 14:13:54.000000000 +0200
44685 +/*****************************************************************************
44688 + * Project: Gigabit Ethernet Adapters, Common Modules
44689 + * Version: $Revision$
44691 + * Purpose: Functions for handling List Element Tables
44693 + *****************************************************************************/
44695 +/******************************************************************************
44698 + * (C)Copyright 2002-2006 Marvell.
44700 + * This program is free software; you can redistribute it and/or modify
44701 + * it under the terms of the GNU General Public License as published by
44702 + * the Free Software Foundation; either version 2 of the License, or
44703 + * (at your option) any later version.
44704 + * The information in this file is provided "AS IS" without warranty.
44707 + ******************************************************************************/
44709 +/*****************************************************************************
44713 + * This module contains the code necessary for handling List Elements.
44715 + * Supported Gigabit Ethernet Chipsets:
44716 + * Yukon-2 (PCI, PCI-X, PCI-Express)
44718 + * Include File Hierarchy:
44721 + *****************************************************************************/
44722 +#include "h/skdrv1st.h"
44723 +#include "h/skdrv2nd.h"
44725 +/* defines *******************************************************************/
44726 +/* typedefs ******************************************************************/
44727 +/* global variables **********************************************************/
44728 +/* local variables ***********************************************************/
44730 +#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
44731 +static const char SysKonnectFileId[] =
44732 + "@(#) $Id$ (C) Marvell.";
44733 +#endif /* DEBUG || (!LINT && !SK_SLIM) */
44735 +/* function prototypes *******************************************************/
44737 +/*****************************************************************************
44739 + * SkGeY2InitSingleLETable() - initializes a list element table
44742 + * This function will initialize the selected list element table.
44743 + * Should be called once during DriverInit. No InitLevel required.
44746 + * pAC - pointer to the adapter context struct.
44747 + * pLETab - pointer to list element table structure
44748 + * NumLE - number of list elements in this table
44749 + * pVMem - virtual address of memory allocated for this LE table
44750 + * PMemLowAddr - physical address of memory to be used for the LE table
44756 +void SkGeY2InitSingleLETable(
44757 +SK_AC *pAC, /* pointer to adapter context */
44758 +SK_LE_TABLE *pLETab, /* pointer to list element table to be initialized */
44759 +unsigned int NumLE, /* number of list elements to be filled in tab */
44760 +void *pVMem, /* virtual address of memory used for list elements */
44761 +SK_U32 PMemLowAddr, /* physical addr of mem used for LE */
44762 +SK_U32 PMemHighAddr)
44766 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44767 + ("==> SkGeY2InitSingleLETable()\n"));
44770 + if (NumLE != 2) { /* not table for polling unit */
44771 + if ((NumLE % MIN_LEN_OF_LE_TAB) != 0 || NumLE > MAX_LEN_OF_LE_TAB) {
44772 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
44773 + ("ERROR: Illegal number of list elements %d\n", NumLE));
44776 +#endif /* DEBUG */
44778 + /* special case: unused list element table */
44779 + if (NumLE == 0) {
44781 + PMemHighAddr = 0;
44786 + * in order to get the best possible performance the macros to access
44787 + * list elements use & instead of %
44788 + * this requires the length of LE tables to be a power of 2
44792 + * this code guarantees that we use the next power of 2 below the
44793 + * value specified for NumLe - this way some LEs in the table may
44794 + * not be used but the macros work correctly
44795 + * this code does not check for bad values below 128 because in such a
44796 + * case we cannot do anything here
44799 + if ((NumLE != 2) && (NumLE != 0)) {
44800 + /* no check for polling unit and unused sync Tx */
44801 + i = MIN_LEN_OF_LE_TAB;
44802 + while (NumLE > i) {
44804 + if (i > MAX_LEN_OF_LE_TAB) {
44808 + if (NumLE != i) {
44809 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
44810 + ("ERROR: Illegal number of list elements %d adjusted to %d\n",
44811 + NumLE, (i / 2)));
44816 + /* set addresses */
44817 + pLETab->pPhyLETABLow = PMemLowAddr;
44818 + pLETab->pPhyLETABHigh = PMemHighAddr;
44819 + pLETab->pLETab = pVMem;
44821 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44822 + ("contains %d LEs", NumLE));
44823 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44824 + (" and starts at virt %08lx and phys %08lx:%08lx\n",
44825 + pVMem, PMemHighAddr, PMemLowAddr));
44827 + /* initialize indexes */
44828 + pLETab->Done = 0;
44830 + pLETab->HwPut = 0;
44831 + /* initialize size */
44832 + pLETab->Num = NumLE;
44834 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44835 + ("<== SkGeY2InitSingleLETable()\n"));
44836 +} /* SkGeY2InitSingleLETable */
44838 +/*****************************************************************************
44840 + * SkGeY2InitPrefetchUnit() - Initialize a Prefetch Unit
44843 + * Calling this function requires an already configured list element
44844 + * table. The prefetch unit to be configured is specified in the parameter
44845 + * 'Queue'. The function is able to initialze the prefetch units of
44846 + * the following queues: Q_R1, Q_R2, Q_XS1, Q_XS2, Q_XA1, Q_XA2.
44847 + * The funcution should be called before SkGeInitPort().
44850 + * pAC - pointer to the adapter context struct.
44851 + * IoC - I/O context.
44852 + * Queue - I/O offset of queue e.g. Q_XA1.
44853 + * pLETab - pointer to list element table to be initialized
44857 +void SkGeY2InitPrefetchUnit(
44858 +SK_AC *pAC, /* pointer to adapter context */
44859 +SK_IOC IoC, /* I/O context */
44860 +unsigned int Queue, /* Queue offset for finding the right registers */
44861 +SK_LE_TABLE *pLETab) /* pointer to list element table to be initialized */
44863 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44864 + ("==> SkGeY2InitPrefetchUnit()\n"));
44867 + if (Queue != Q_R1 && Queue != Q_R2 && Queue != Q_XS1 &&
44868 + Queue != Q_XS2 && Queue != Q_XA1 && Queue != Q_XA2) {
44869 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
44870 + ("ERROR: Illegal queue identifier %x\n", Queue));
44872 +#endif /* DEBUG */
44874 + /* disable the prefetch unit */
44875 + SK_OUT32(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_CTRL_REG), PREF_UNIT_RST_SET);
44876 + SK_OUT32(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_CTRL_REG), PREF_UNIT_RST_CLR);
44878 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44879 + ("Base address: %08lx:%08lx\n", pLETab->pPhyLETABHigh,
44880 + pLETab->pPhyLETABLow));
44882 + /* Set the list base address high part*/
44883 + SK_OUT32(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_ADDR_HI_REG),
44884 + pLETab->pPhyLETABHigh);
44886 + /* Set the list base address low part */
44887 + SK_OUT32(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_ADDR_LOW_REG),
44888 + pLETab->pPhyLETABLow);
44890 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44891 + ("Last index: %d\n", pLETab->Num-1));
44893 + /* Set the list last index */
44894 + SK_OUT16(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_LAST_IDX_REG),
44895 + (SK_U16)(pLETab->Num - 1));
44897 + /* turn on prefetch unit */
44898 + SK_OUT32(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_CTRL_REG), PREF_UNIT_OP_ON);
44900 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44901 + ("<== SkGeY2InitPrefetchUnit()\n"));
44902 +} /* SkGeY2InitPrefetchUnit */
44905 +/*****************************************************************************
44907 + * SkGeY2InitStatBmu() - Initialize the Status BMU
44910 + * Calling this function requires an already configured list element
44911 + * table. Ensure the status BMU is only initialized once during
44912 + * DriverInit - InitLevel2 required.
44915 + * pAC - pointer to the adapter context struct.
44916 + * IoC - I/O context.
44917 + * pLETab - pointer to status LE table to be initialized
44921 +void SkGeY2InitStatBmu(
44922 +SK_AC *pAC, /* pointer to adapter context */
44923 +SK_IOC IoC, /* I/O context */
44924 +SK_LE_TABLE *pLETab) /* pointer to status LE table */
44926 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44927 + ("==> SkGeY2InitStatBmu()\n"));
44929 + /* disable the prefetch unit */
44930 + SK_OUT32(IoC, STAT_CTRL, SC_STAT_RST_SET);
44931 + SK_OUT32(IoC, STAT_CTRL, SC_STAT_RST_CLR);
44933 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44934 + ("Base address Low: %08lX\n", pLETab->pPhyLETABLow));
44936 + /* Set the list base address */
44937 + SK_OUT32(IoC, STAT_LIST_ADDR_LO, pLETab->pPhyLETABLow);
44939 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44940 + ("Base address High: %08lX\n", pLETab->pPhyLETABHigh));
44942 + SK_OUT32(IoC, STAT_LIST_ADDR_HI, pLETab->pPhyLETABHigh);
44944 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44945 + ("Last index: %d\n", pLETab->Num - 1));
44947 + /* Set the list last index */
44948 + SK_OUT16(IoC, STAT_LAST_IDX, (SK_U16)(pLETab->Num - 1));
44950 + if (HW_FEATURE(pAC, HWF_WA_DEV_43_418)) {
44952 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44953 + ("Set Tx index threshold\n"));
44954 + /* WA for dev. #4.3 */
44955 + SK_OUT16(IoC, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK);
44957 + /* set Status-FIFO watermark */
44958 + SK_OUT8(IoC, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
44960 + /* set Status-FIFO ISR watermark */
44961 + SK_OUT8(IoC, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
44963 + /* WA for dev. #4.3 and #4.18 */
44964 + /* set Status-FIFO Tx timer init value */
44965 + SK_OUT32(IoC, STAT_TX_TIMER_INI, HW_MS_TO_TICKS(pAC, 10));
44969 + * Further settings may be added if required...
44970 + * 1) Status-FIFO watermark (STAT_FIFO_WM, STAT_FIFO_ISR_WM)
44971 + * 2) Status-FIFO timer values (STAT_TX_TIMER_INI,
44972 + * STAT_LEV_TIMER_INI and STAT_ISR_TIMER_INI)
44973 + * but tests shows that the default values give the best results,
44974 + * therefore the defaults are used.
44978 + * Theses settings should avoid the temporary hang of the status BMU.
44979 + * May be not all required... still under investigation...
44981 + SK_OUT16(IoC, STAT_TX_IDX_TH, 0x000a);
44983 + /* set Status-FIFO watermark */
44984 + SK_OUT8(IoC, STAT_FIFO_WM, 0x10);
44986 + /* set Status-FIFO ISR watermark */
44987 + SK_OUT8(IoC, STAT_FIFO_ISR_WM,
44988 + HW_FEATURE(pAC, HWF_WA_DEV_4109) ? 0x10 : 0x04);
44990 + /* set ISR Timer Init Value to 400 (3.2 us on Yukon-EC) */
44991 + SK_OUT32(IoC, STAT_ISR_TIMER_INI, 0x0190);
44994 + /* start Status-FIFO timer */
44995 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44996 + ("Start Status FiFo timer\n"));
44998 + /* enable the prefetch unit */
44999 + /* operational bit not functional for Yukon-EC, but fixed in Yukon-2 */
45000 + SK_OUT32(IoC, STAT_CTRL, SC_STAT_OP_ON);
45002 + /* start Status-FIFO timer */
45003 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
45004 + ("Start Status FiFo timer\n"));
45006 + SK_OUT8(IoC, STAT_TX_TIMER_CTRL, TIM_START);
45007 + SK_OUT8(IoC, STAT_LEV_TIMER_CTRL, TIM_START);
45008 + SK_OUT8(IoC, STAT_ISR_TIMER_CTRL, TIM_START);
45010 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
45011 + ("<== SkGeY2InitStatBmu()\n"));
45012 +} /* SkGeY2InitStatBmu */
45014 +#ifdef USE_POLLING_UNIT
45015 +/*****************************************************************************
45017 + * SkGeY2InitPollUnit() - Initialize the Polling Unit
45020 + * This function will write the data of one polling LE table into the
45024 + * pAC - pointer to the adapter context struct.
45025 + * IoC - I/O context.
45026 + * pLETab - pointer to polling LE table to be initialized
45030 +void SkGeY2InitPollUnit(
45031 +SK_AC *pAC, /* pointer to adapter context */
45032 +SK_IOC IoC, /* I/O context */
45033 +SK_LE_TABLE *pLETab) /* pointer to polling LE table */
45041 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
45042 + ("==> SkGeY2InitPollUnit()\n"));
45045 + for (i = 0; i < SK_MAX_MACS; i++) {
45046 + GET_PO_LE(pLE, pLETab, i);
45047 + VCPU_START_AND_COPY_LE();
45048 + /* initialize polling LE but leave indexes invalid */
45049 + POLE_SET_OPC(pLE, OP_PUTIDX | HW_OWNER);
45050 + POLE_SET_LINK(pLE, i);
45051 + POLE_SET_RXIDX(pLE, 0);
45052 + POLE_SET_TXAIDX(pLE, 0);
45053 + POLE_SET_TXSIDX(pLE, 0);
45055 + SK_DBG_DUMP_PO_LE(pLE);
45059 + /* disable the polling unit */
45060 + SK_OUT32(IoC, POLL_CTRL, PC_POLL_RST_SET);
45061 + SK_OUT32(IoC, POLL_CTRL, PC_POLL_RST_CLR);
45063 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
45064 + ("Base address Low: %08lX\n", pLETab->pPhyLETABLow));
45066 + /* Set the list base address */
45067 + SK_OUT32(IoC, POLL_LIST_ADDR_LO, pLETab->pPhyLETABLow);
45069 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
45070 + ("Base address High: %08lX\n", pLETab->pPhyLETABHigh));
45072 + SK_OUT32(IoC, POLL_LIST_ADDR_HI, pLETab->pPhyLETABHigh);
45074 + /* we don't need to write the last index - it is hardwired to 1 */
45076 + /* enable the prefetch unit */
45077 + SK_OUT32(IoC, POLL_CTRL, PC_POLL_OP_ON);
45080 + * now we have to start the descriptor poll timer because it triggers
45081 + * the polling unit
45085 + * still playing with the value (timer runs at 125 MHz)
45086 + * descriptor poll timer is enabled by GeInit
45088 + SK_OUT32(IoC, B28_DPT_INI,
45089 + (SK_DPOLL_DEF_Y2 * (SK_U32)pAC->GIni.GIHstClkFact / 100));
45091 + SK_OUT8(IoC, B28_DPT_CTRL, TIM_START);
45093 + SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
45094 + ("<== SkGeY2InitPollUnit()\n"));
45095 +} /* SkGeY2InitPollUnit */
45096 +#endif /* USE_POLLING_UNIT */
45099 +/******************************************************************************
45101 + * SkGeY2SetPutIndex
45104 + * This function is writing the Done index of a transmit
45105 + * list element table.
45112 +void SkGeY2SetPutIndex(
45113 +SK_AC *pAC, /* pointer to adapter context */
45114 +SK_IOC IoC, /* pointer to the IO context */
45115 +SK_U32 StartAddrPrefetchUnit, /* start address of the prefetch unit */
45116 +SK_LE_TABLE *pLETab) /* list element table to work with */
45118 + unsigned int Put;
45119 + SK_U16 EndOfListIndex;
45120 + SK_U16 HwGetIndex;
45121 + SK_U16 HwPutIndex;
45123 + /* set put index we would like to write */
45124 + Put = GET_PUT_IDX(pLETab);
45127 + * in this case we wrap around
45128 + * new put is lower than last put given to HW
45130 + if (Put < pLETab->HwPut) {
45132 + /* set put index = last index of list */
45133 + EndOfListIndex = (NUM_LE_IN_TABLE(pLETab)-1);
45135 + /* read get index of hw prefetch unit */
45136 + SK_IN16(IoC, (StartAddrPrefetchUnit + PREF_UNIT_GET_IDX_REG),
45139 + /* read put index of hw prefetch unit */
45140 + SK_IN16(IoC, (StartAddrPrefetchUnit + PREF_UNIT_PUT_IDX_REG),
45143 + /* prefetch unit reached end of list */
45144 + /* prefetch unit reached first list element */
45145 + if (HwGetIndex == 0) {
45146 + /* restore watermark */
45147 + SK_OUT8(IoC, StartAddrPrefetchUnit + PREF_UNIT_FIFO_WM_REG, 0xe0U);
45148 + /* write put index */
45149 + SK_OUT16(IoC, StartAddrPrefetchUnit + PREF_UNIT_PUT_IDX_REG,
45152 + /* remember put index we wrote to hw */
45153 + pLETab->HwPut = Put;
45155 + else if (HwGetIndex == EndOfListIndex) {
45156 + /* set watermark to one list element */
45157 + SK_OUT8(IoC, StartAddrPrefetchUnit + PREF_UNIT_FIFO_WM_REG, 8);
45158 + /* set put index to first list element */
45159 + SK_OUT16(IoC, StartAddrPrefetchUnit + PREF_UNIT_PUT_IDX_REG, 0);
45161 + /* prefetch unit did not reach end of list yet */
45162 + /* and we did not write put index to end of list yet */
45163 + else if ((HwPutIndex != EndOfListIndex) &&
45164 + (HwGetIndex != EndOfListIndex)) {
45165 + /* write put index */
45166 + SK_OUT16(IoC, StartAddrPrefetchUnit + PREF_UNIT_PUT_IDX_REG,
45174 +#ifdef XXX /* leads in to problems in the Windows Driver */
45175 + if (Put != pLETab->HwPut) {
45176 + /* write put index */
45177 + SK_OUT16(IoC, StartAddrPrefetchUnit + PREF_UNIT_PUT_IDX_REG,
45179 + /* update put index */
45180 + UPDATE_HWPUT_IDX(pLETab);
45183 + /* write put index */
45184 + SK_OUT16(IoC, StartAddrPrefetchUnit + PREF_UNIT_PUT_IDX_REG,
45186 + /* update put index */
45187 + UPDATE_HWPUT_IDX(pLETab);
45190 +} /* SkGeY2SetPutIndex */
45192 diff -ruN linux/Documentation/networking/sk98lin.txt linux-new/Documentation/networking/sk98lin.txt
45193 --- linux/Documentation/networking/sk98lin.txt 2006-09-20 05:42:06.000000000 +0200
45194 +++ linux-new/drivers/net/sk98lin/sk98lin.txt 2006-07-28 14:13:54.000000000 +0200
45196 -(C)Copyright 1999-2004 Marvell(R).
45197 -All rights reserved
45198 -===========================================================================
45199 +(C)Copyright 1999-2006 Marvell(R).
45200 +All rights reserved.
45201 +================================================================================
45203 -sk98lin.txt created 13-Feb-2004
45204 +sk98lin.txt created 28-Jul-2006
45206 -Readme File for sk98lin v6.23
45207 -Marvell Yukon/SysKonnect SK-98xx Gigabit Ethernet Adapter family driver for LINUX
45208 +Readme File for sk98lin v8.36.1.3
45209 +Marvell Yukon/SysKonnect SK-98xx Gigabit Ethernet Adapter driver for LINUX
45215 - 3.1 Driver Installation
45216 - 3.2 Inclusion of adapter at system start
45217 - 4 Driver Parameters
45218 - 4.1 Per-Port Parameters
45219 - 4.2 Adapter Parameters
45220 - 5 Large Frame Support
45221 - 6 VLAN and Link Aggregation Support (IEEE 802.1, 802.1q, 802.3ad)
45222 - 7 Troubleshooting
45223 + 2 Supported Functions
45226 + 4.1 Driver Installation
45227 + 4.2 Inclusion of adapter at system start
45228 + 5 Driver Parameters
45229 + 5.1 Per-Port Parameters
45230 + 5.2 Adapter Parameters
45231 + 6 Ethtool Support
45232 + 7 Large Frame Support
45233 + 8 VLAN and Link Aggregation Support (IEEE 802.1, 802.1q, 802.3ad)
45234 + 9 Wake on Lan support
45235 +10 Troubleshooting
45237 -===========================================================================
45238 +================================================================================
45244 -The sk98lin driver supports the Marvell Yukon and SysKonnect
45245 -SK-98xx/SK-95xx compliant Gigabit Ethernet Adapter on Linux. It has
45246 -been tested with Linux on Intel/x86 machines.
45247 +The sk98lin driver supports the Marvell Yukon, Yukon EC/FE, Yukon 2
45248 +and SysKonnect SK-98xx/SK-95xx compliant Gigabit Ethernet Adapter on Linux.
45249 +It has been tested with Linux on Intel/x86, x86_64 and IA64 machines.
45252 +2 Supported Functions
45253 +======================
45255 +The following functions are supported by the driver:
45258 + NOTE 1: The hardware support depends on the used card
45260 + - RX/TX HW Checksum
45261 + - Hardware interrupt moderation (static/dynamic)
45263 + - Zerocopy/Scatter-Gather
45264 + - Ethtool support
45265 + - Wake on Lan (Magic Packet only)
45272 The linux kernel source.
45273 @@ -40,16 +58,14 @@
45281 It is recommended to download the latest version of the driver from the
45282 -SysKonnect web site www.syskonnect.com. If you have downloaded the latest
45283 -driver, the Linux kernel has to be patched before the driver can be
45284 -installed. For details on how to patch a Linux kernel, refer to the
45286 +SysKonnect web site www.syskonnect.com. For details on Installation
45287 +Instructions for sk98lin Driver, please refer to the README.txt file.
45289 -3.1 Driver Installation
45290 +4.1 Driver Installation
45291 ------------------------
45293 The following steps describe the actions that are required to install
45296 5. Execute the command "make modules".
45297 6. Execute the command "make modules_install".
45298 - The appropriate modules will be installed.
45299 + The appropiate modules will be installed.
45300 7. Reboot your system.
45303 @@ -110,13 +126,13 @@
45305 NOTE 1: If you have more than one Marvell Yukon or SysKonnect SK-98xx
45306 adapter installed, the adapters will be listed as 'eth0',
45307 - 'eth1', 'eth2', etc.
45308 - For each adapter, repeat steps 3 and 4 below.
45309 + 'eth1', 'eth2', etc.
45310 + For each adapter, repeat steps 3 and 4 below.
45312 NOTE 2: If you have other Ethernet adapters installed, your Marvell
45313 Yukon or SysKonnect SK-98xx adapter will be mapped to the
45314 - next available number, e.g. 'eth1'. The mapping is executed
45316 + next available number, e.g. 'eth1'. The mapping is executed
45318 The module installation message (displayed either in a system
45319 log file or on the console) prints a line for each adapter
45320 found containing the corresponding 'ethX'.
45321 @@ -153,7 +169,7 @@
45322 1. Execute the command "ifconfig eth0 down".
45323 2. Execute the command "rmmod sk98lin".
45325 -3.2 Inclusion of adapter at system start
45326 +4.2 Inclusion of adapter at system start
45327 -----------------------------------------
45329 Since a large number of different Linux distributions are
45330 @@ -165,7 +181,8 @@
45334 -4 Driver Parameters
45336 +5 Driver Parameters
45337 ====================
45339 Parameters can be set at the command line after the module has been
45340 @@ -174,7 +191,7 @@
45341 to the driver module.
45343 If you use the kernel module loader, you can set driver parameters
45344 -in the file /etc/modprobe.conf (or /etc/modules.conf in 2.4 or earlier).
45345 +in the file /etc/modules.conf (or old name: /etc/conf.modules).
45346 To set the driver parameters in this file, proceed as follows:
45348 1. Insert a line of the form :
45349 @@ -208,7 +225,7 @@
45350 more adapters, adjust this and recompile.
45353 -4.1 Per-Port Parameters
45354 +5.1 Per-Port Parameters
45355 ------------------------
45357 These settings are available for each port on the adapter.
45358 @@ -245,7 +262,7 @@
45359 This parameters is only relevant if auto-negotiation for this port is
45360 not set to "Sense". If auto-negotiation is set to "On", all three values
45361 are possible. If it is set to "Off", only "Full" and "Half" are allowed.
45362 -This parameter is useful if your link partner does not support all
45363 +This parameter is usefull if your link partner does not support all
45364 possible combinations.
45367 @@ -268,6 +285,18 @@
45369 NOTE: This parameter is ignored if auto-negotiation is set to "Off".
45371 +Broadcast Priority
45372 +-------------------
45373 +Parameter: BroadcastPrio
45377 +This parameter specifies whether received broadcast packets have the
45378 +highest priority for the port switch decision ("Off") or not ("On").
45380 +NOTE: This parameter is only valid for dual port adapters.
45383 Role in Master-Slave-Negotiation (1000Base-T only)
45384 --------------------------------------------------
45386 @@ -282,13 +311,13 @@
45387 with this parameter.
45390 -4.2 Adapter Parameters
45391 +5.2 Adapter Parameters
45392 -----------------------
45394 -Connection Type (SK-98xx V2.0 copper adapters only)
45395 +Connection Type (for copper adapters only)
45398 -Values: Auto, 100FD, 100HD, 10FD, 10HD
45399 +Values: Auto, 1000FD, 100FD, 100HD, 10FD, 10HD
45402 The parameter 'ConType' is a combination of all five per-port parameters
45403 @@ -302,6 +331,7 @@
45404 ConType | DupCap AutoNeg FlowCtrl Role Speed
45405 ----------+------------------------------------------------------
45406 Auto | Both On SymOrRem Auto Auto
45407 + 1000FD | Full Off None Auto (ignored) 1000
45408 100FD | Full Off None Auto (ignored) 100
45409 100HD | Half Off None Auto (ignored) 100
45410 10FD | Full Off None Auto (ignored) 10
45411 @@ -379,7 +409,6 @@
45412 is tremendous. On the other hand, selecting a very short moderation time might
45413 compensate the use of any moderation being applied.
45418 Parameter: PrefPort
45419 @@ -394,7 +423,7 @@
45420 ------------------------------------------------
45421 Parameter: RlmtMode
45422 Values: CheckLinkState,CheckLocalPort, CheckSeg, DualNet
45423 -Default: CheckLinkState
45424 +Default: CheckLinkState (DualNet on dual port adapters)
45426 RLMT monitors the status of the port. If the link of the active port
45427 fails, RLMT switches immediately to the standby link. The virtual link is
45428 @@ -429,10 +458,100 @@
45429 where a network path between the ports on one adapter exists.
45430 Moreover, they are not designed to work where adapters are connected
45435 +Parameter: LowLatency
45439 +This is used to reduce the packet latency time of the adapter. Setting the
45440 +LowLatency parameter to 'On' forces the adapter to pass any received packet
45441 +immediately to upper network layers and to send out any transmit packet as
45444 +NOTE 1: The system load increases if LowLatency is set to 'On' and a lot
45445 + of data packets are transmitted and received.
45447 +NOTE 2: This parameter is only used on adapters which are based on
45448 + PCI Express compatible chipsets.
45453 +==================
45455 +The sk98lin driver provides built-in ethtool support. The ethtool
45456 +can be used to display or modify interface specific configurations.
45458 +Ethtool commands are invoked using a single parameter which reflects
45459 +the requested ethtool command plus an optional number of parameters
45460 +which belong to the desired command.
45462 +It is not the intention of this section to explain the ethtool command
45463 +line tool and all its options. For further information refer to the
45464 +manpage of the ethtool. This sections describes only the sk98lin
45465 +driver supported ethtool commands.
45470 +Set command: -A [autoneg on|off] [rx on|off] [tx on|off]
45471 +Sample: ethtool -A eth0 rx off tx off
45473 +Coalescing Parameters
45474 +---------------------
45476 +Set command: -C [sample-interval I]
45477 + [rx-usecs N] [tx-usecs N]
45478 + [rx-usecs-low N] [tx-usecs-low N]
45479 + [rx-usecs-high N] [tx-usecs-high N]
45480 +Parameter: I = Length of sample interval, in seconds
45481 + (supported values range from 1...10)
45482 + N = Length of coalescing interval, in microseconds
45483 + (supported values range from 25...33,333)
45484 +Sample: ethtool -C eth2 rx-usecs 500 tx-usecs 500
45486 +NOTE: The sk98lin driver does not support different settings
45487 + for the rx and tx interrupt coalescing parameters.
45489 +Driver Information
45490 +------------------
45492 +Sample: ethtool -i eth1
45494 +Checksumming Parameters
45495 +-----------------------
45497 +Set command: -K [rx on|off] [tx on|off] [sg on|off]
45498 +Sample: ethtool -K eth0 sg off
45500 +Locate NIC Command
45501 +------------------
45502 +Query command: -p [N]
45503 +Parameter: N = Amount of time to perform locate NIC command, in seconds
45504 +Sample: ethtool -p 10 eth1
45506 +Driver-specific Statistics
45507 +--------------------------
45509 +Sample: ethtool -S eth0
45511 +Setting Parameters
45512 +------------------
45513 +Set command: -s [speed 10|100|1000] [duplex half|full]
45514 + [autoneg on|off] [wol gd]
45515 +Sample: ethtool -s eth2 wol d
45517 +NOTE: If cable is disconnected, please set the speed and duplex mode
45518 + if you disable/enable autonegotiation
45520 +NOTE: To set back to the default values use the "autoneg on" command.
45521 + Sample: ethtool -s eth2 autoneg on
45525 -5 Large Frame Support
45526 +7 Large Frame Support
45527 ======================
45529 The driver supports large frames (also called jumbo frames). Using large
45530 @@ -444,10 +563,10 @@
45531 ifconfig eth0 mtu 9000
45532 This will only work if you have two adapters connected back-to-back
45533 or if you use a switch that supports large frames. When using a switch,
45534 -it should be configured to allow large frames and auto-negotiation should
45535 -be set to OFF. The setting must be configured on all adapters that can be
45536 -reached by the large frames. If one adapter is not set to receive large
45537 -frames, it will simply drop them.
45538 +it should be configured to allow large frames. The setting must be
45539 +configured on all adapters that can be reached by the large frames.
45540 +If one adapter is not set to receive large frames, it will simply drop
45543 You can switch back to the standard ethernet frame size by executing the
45545 @@ -459,7 +578,7 @@
45549 -6 VLAN and Link Aggregation Support (IEEE 802.1, 802.1q, 802.3ad)
45550 +8 VLAN and Link Aggregation Support (IEEE 802.1, 802.1q, 802.3ad)
45551 ==================================================================
45553 The Marvell Yukon/SysKonnect Linux drivers are able to support VLAN and
45554 @@ -477,8 +596,21 @@
45555 cause problems when unloading the driver.
45559 -==================
45560 +9 Wake on Lan support
45561 +======================
45563 +The sk98lin driver supports wake up from suspend mode with MagicPacket
45564 +on APM systems. Wake on Lan support is enabled by default. To disable it
45565 +please use the ethtool.
45567 +NOTE 1: APM support has to be enabled in BIOS and in the kernel.
45569 +NOTE 2: Refer to the kernel documentation for additional requirements
45570 + regarding APM support.
45573 +10 Troubleshooting
45574 +===================
45576 If any problems occur during the installation process, check the
45578 diff -ruN linux/drivers/net/Kconfig linux-new/drivers/net/Kconfig
45579 --- linux/drivers/net/Kconfig 2006-09-20 05:42:06.000000000 +0200
45580 +++ linux-new/drivers/net/Kconfig 2006-09-20 18:58:02.475331500 +0200
45581 @@ -2096,22 +2096,33 @@
45582 To compile this driver as a module, choose M here: the module
45583 will be called sky2. This is recommended.
45587 tristate "Marvell Yukon Chipset / SysKonnect SK-98xx Support"
45590 Say Y here if you have a Marvell Yukon or SysKonnect SK-98xx/SK-95xx
45591 - compliant Gigabit Ethernet Adapter.
45593 - This driver supports the original Yukon chipset. A cleaner driver is
45594 - also available (skge) which seems to work better than this one.
45596 - This driver does not support the newer Yukon2 chipset. A seperate
45597 - driver, sky2, is provided to support Yukon2-based adapters.
45599 - The following adapters are supported by this driver:
45600 + compliant Gigabit Ethernet Adapter. The following adapters are supported
45602 - 3Com 3C940 Gigabit LOM Ethernet Adapter
45603 - 3Com 3C941 Gigabit LOM Ethernet Adapter
45604 + - 88E8021 Marvell 1000 Mbit PCI-X, single Port Copper
45605 + - 88E8021 Marvell 1000 Mbit PCI-X, single Port Fiber LX
45606 + - 88E8021 Marvell 1000 Mbit PCI-X, single Port Fiber SX
45607 + - 88E8022 Marvell 1000 Mbit PCI-X, dual Port Copper
45608 + - 88E8022 Marvell 1000 Mbit PCI-X, dual Port Copper (Gateway)
45609 + - 88E8022 Marvell 1000 Mbit PCI-X, dual Port Fiber LX
45610 + - 88E8022 Marvell 1000 Mbit PCI-X, dual Port Fiber SX
45611 + - 88E8061 Marvell 1000 Mbit PCI-E, single Port Copper
45612 + - 88E8061 Marvell 1000 Mbit PCI-E, single Port Fiber LX
45613 + - 88E8061 Marvell 1000 Mbit PCI-E, single Port Fiber SX
45614 + - 88E8062 Marvell 1000 Mbit PCI-E, dual Port Copper
45615 + - 88E8062 Marvell 1000 Mbit PCI-E, dual Port Copper (Gateway)
45616 + - 88E8062 Marvell 1000 Mbit PCI-E, dual Port Fiber LX
45617 + - 88E8062 Marvell 1000 Mbit PCI-E, dual Port Fiber SX
45618 + - Abocom EFE3K - 10/100 Ethernet Expresscard
45619 + - Abocom EGE5K - Giga Ethernet Expresscard
45621 - Allied Telesyn AT-2970LX Gigabit Ethernet Adapter
45622 - Allied Telesyn AT-2970LX/2SC Gigabit Ethernet Adapter
45623 - Allied Telesyn AT-2970SX Gigabit Ethernet Adapter
45624 @@ -2121,31 +2132,85 @@
45625 - Allied Telesyn AT-2971SX Gigabit Ethernet Adapter
45626 - Allied Telesyn AT-2971T Gigabit Ethernet Adapter
45627 - Belkin Gigabit Desktop Card 10/100/1000Base-T Adapter, Copper RJ-45
45628 + - DGE-530T Gigabit Ethernet Adapter
45629 + - DGE-550SX Gigabit Ethernet Adapter
45630 + - DGE-560SX Single fiber Gigabit Ethernet Adapter
45631 + - DGE-560T Gigabit Ethernet Adapter
45632 - EG1032 v2 Instant Gigabit Network Adapter
45633 - EG1064 v2 Instant Gigabit Network Adapter
45634 - - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Abit)
45635 - - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Albatron)
45636 - - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Asus)
45637 - - Marvell 88E8001 Gigabit LOM Ethernet Adapter (ECS)
45638 - - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Epox)
45639 - - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Foxconn)
45640 - - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Gigabyte)
45641 - - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Iwill)
45642 - - Marvell 88E8050 Gigabit LOM Ethernet Adapter (Intel)
45643 + - Marvell 88E8001 Gigabit Ethernet Controller (Abit)
45644 + - Marvell 88E8001 Gigabit Ethernet Controller (Albatron)
45645 + - Marvell 88E8001 Gigabit Ethernet Controller (Asus)
45646 + - Marvell 88E8001 Gigabit Ethernet Controller (Chaintech)
45647 + - Marvell 88E8001 Gigabit Ethernet Controller (ECS)
45648 + - Marvell 88E8001 Gigabit Ethernet Controller (Epox)
45649 + - Marvell 88E8001 Gigabit Ethernet Controller (Foxconn)
45650 + - Marvell 88E8001 Gigabit Ethernet Controller (Gigabyte)
45651 + - Marvell 88E8001 Gigabit Ethernet Controller (Iwill)
45652 + - Marvell 88E8035 Fast Ethernet Controller (LGE)
45653 + - Marvell 88E8035 Fast Ethernet Controller (Toshiba)
45654 + - Marvell 88E8036 Fast Ethernet Controller (Arima)
45655 + - Marvell 88E8036 Fast Ethernet Controller (Compal)
45656 + - Marvell 88E8036 Fast Ethernet Controller (Inventec)
45657 + - Marvell 88E8036 Fast Ethernet Controller (LGE)
45658 + - Marvell 88E8036 Fast Ethernet Controller (Mitac)
45659 + - Marvell 88E8036 Fast Ethernet Controller (Panasonic)
45660 + - Marvell 88E8036 Fast Ethernet Controller (Quanta)
45661 + - Marvell 88E8036 Fast Ethernet Controller (Toshiba)
45662 + - Marvell 88E8036 Fast Ethernet Controller (Wistron)
45663 + - Marvell 88E8050 Gigabit Ethernet Controller (Gateway)
45664 + - Marvell 88E8050 Gigabit Ethernet Controller (Intel)
45665 + - Marvell 88E8052 Gigabit Ethernet Controller (ASRock)
45666 + - Marvell 88E8052 Gigabit Ethernet Controller (Aopen)
45667 + - Marvell 88E8052 Gigabit Ethernet Controller (Asus)
45668 + - Marvell 88E8052 Gigabit Ethernet Controller (Gateway)
45669 + - Marvell 88E8052 Gigabit Ethernet Controller (Gigabyte)
45670 + - Marvell 88E8052 Gigabit Ethernet Controller (MSI)
45671 + - Marvell 88E8052 Gigabit Ethernet Controller (Wistron)
45672 + - Marvell 88E8053 Gigabit Ethernet Controller (ASRock)
45673 + - Marvell 88E8053 Gigabit Ethernet Controller (Albatron)
45674 + - Marvell 88E8053 Gigabit Ethernet Controller (Aopen)
45675 + - Marvell 88E8053 Gigabit Ethernet Controller (Arima)
45676 + - Marvell 88E8053 Gigabit Ethernet Controller (Asus)
45677 + - Marvell 88E8053 Gigabit Ethernet Controller (Chaintech)
45678 + - Marvell 88E8053 Gigabit Ethernet Controller (Clevo)
45679 + - Marvell 88E8053 Gigabit Ethernet Controller (Compal)
45680 + - Marvell 88E8053 Gigabit Ethernet Controller (DFI)
45681 + - Marvell 88E8053 Gigabit Ethernet Controller (ECS)
45682 + - Marvell 88E8053 Gigabit Ethernet Controller (Epox)
45683 + - Marvell 88E8053 Gigabit Ethernet Controller (Gigabyte)
45684 + - Marvell 88E8053 Gigabit Ethernet Controller (Inventec)
45685 + - Marvell 88E8053 Gigabit Ethernet Controller (LGE)
45686 + - Marvell 88E8053 Gigabit Ethernet Controller (MSI)
45687 + - Marvell 88E8053 Gigabit Ethernet Controller (Mitac)
45688 + - Marvell 88E8053 Gigabit Ethernet Controller (Panasonic)
45689 + - Marvell 88E8053 Gigabit Ethernet Controller (Quanta)
45690 + - Marvell 88E8053 Gigabit Ethernet Controller (SOYO)
45691 + - Marvell 88E8053 Gigabit Ethernet Controller (Shuttle)
45692 + - Marvell 88E8053 Gigabit Ethernet Controller (Toshiba)
45693 + - Marvell 88E8053 Gigabit Ethernet Controller (Trigem)
45694 + - Marvell RDK-8001
45695 - Marvell RDK-8001 Adapter
45696 - Marvell RDK-8002 Adapter
45697 + - Marvell RDK-8003
45698 - Marvell RDK-8003 Adapter
45699 - Marvell RDK-8004 Adapter
45700 - Marvell RDK-8006 Adapter
45701 - Marvell RDK-8007 Adapter
45702 - Marvell RDK-8008 Adapter
45703 - Marvell RDK-8009 Adapter
45704 - - Marvell RDK-8010 Adapter
45705 + - Marvell RDK-8010
45706 - Marvell RDK-8011 Adapter
45707 - Marvell RDK-8012 Adapter
45708 - - Marvell RDK-8052 Adapter
45709 - - Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Adapter (32 bit)
45710 - - Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Adapter (64 bit)
45711 + - Marvell RDK-8035
45712 + - Marvell RDK-8036
45713 + - Marvell RDK-8052
45714 + - Marvell RDK-8053
45715 + - Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Controller (32 bit)
45716 + - Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Controller (64 bit)
45717 + - Marvell Yukon PCI-E Fast Ethernet
45718 + - Marvell Yukon-EC Ultra, no ASF (Battery Power Service Support)
45719 + - Marvell Yukon-FE Fast Ethernet, Reduced Battery Power Service Support)
45720 - N-Way PCI-Bus Giga-Card 1000/100/10Mbps(L)
45721 - SK-9521 10/100/1000Base-T Adapter
45722 - SK-9521 V2.0 10/100/1000Base-T Adapter
45723 @@ -2165,21 +2230,37 @@
45724 - SK-9871 Gigabit Ethernet Server Adapter (SK-NET GE-ZX)
45725 - SK-9871 V2.0 Gigabit Ethernet 1000Base-ZX Adapter
45726 - SK-9872 Gigabit Ethernet Server Adapter (SK-NET GE-ZX dual link)
45727 + - SK-9S21 Server Adapter
45728 + - SK-9S22 Server Adapter
45729 + - SK-9S24 Server Adapter
45730 + - SK-9S34 Server Adapter
45731 + - SK-9S81 Server Adapter
45732 + - SK-9S82 Server Adapter
45733 + - SK-9S91 Server Adapter
45734 + - SK-9S92 Server Adapter
45735 - SMC EZ Card 1000 (SMC9452TXV.2)
45737 The adapters support Jumbo Frames.
45738 The dual link adapters support link-failover and dual port features.
45739 Both Marvell Yukon and SysKonnect SK-98xx/SK-95xx adapters support
45740 the scatter-gather functionality with sendfile(). Please refer to
45741 - <file:Documentation/networking/sk98lin.txt> for more information about
45742 + Documentation/networking/sk98lin.txt for more information about
45743 optional driver parameters.
45744 Questions concerning this driver may be addressed to:
45745 - <linux@syskonnect.de>
45746 + linux@syskonnect.de
45748 If you want to compile this driver as a module ( = code which can be
45749 inserted in and removed from the running kernel whenever you want),
45750 - say M here and read <file:Documentation/kbuild/modules.txt>. The module will
45751 - be called sk98lin. This is recommended.
45752 + say M here and read Documentation/modules.txt. This is recommended.
45753 + The module will be called sk98lin. This is recommended.
45755 +config SK98LIN_NAPI
45756 + bool "Use Rx polling (NAPI)"
45757 + depends on SK98LIN
45759 + NAPI is a new driver API designed to reduce CPU and interrupt load
45760 + when the driver is receiving lots of packets from the card.
45763 config VIA_VELOCITY
45764 tristate "VIA Velocity support"