kernel-small_fixes.patch

   1 --- linux-2.6.33/scripts/mod/modpost.c~ 2010-02-24 19:52:17.000000000 +0100
   2 +++ linux-2.6.33/scripts/mod/modpost.c  2010-03-07 14:26:47.242168558 +0100
   3 @@ -15,7 +15,8 @@
   4  #include <stdio.h>
   5  #include <ctype.h>
   6  #include "modpost.h"
   7 -#include "../../include/generated/autoconf.h"
   8 +// PLD architectures don't use CONFIG_SYMBOL_PREFIX
   9 +//#include "../../include/generated/autoconf.h"
  10  #include "../../include/linux/license.h"
  11
  12  /* Some toolchains use a `_' prefix for all user symbols. */
  13
  14 --- linux-3.0/scripts/kconfig/lxdialog/check-lxdialog.sh~       2011-07-22 04:17:23.000000000 +0200
  15 +++ linux-3.0/scripts/kconfig/lxdialog/check-lxdialog.sh        2011-08-25 21:26:04.799150642 +0200
  16 @@ -9,6 +9,12 @@
  17                         $cc -print-file-name=lib${lib}.${ext} | grep -q /
  18                         if [ $? -eq 0 ]; then
  19                                 echo "-l${lib}"
  20 +                               for libt in tinfow tinfo ; do
  21 +                                       $cc -print-file-name=lib${libt}.${ext} | grep -q /
  22 +                                       if [ $? -eq 0 ]; then
  23 +                                               echo "-l${libt}"
  24 +                                       fi
  25 +                               done
  26                                 exit
  27                         fi
  28                 done
  29
  30 diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
  31 index 7a0c800..ec5ebbb 100644
  32 --- a/drivers/net/ethernet/realtek/r8169.c
  33 +++ b/drivers/net/ethernet/realtek/r8169.c
  34 @@ -4103,6 +4103,14 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  35         /* Get MAC address */
  36         for (i = 0; i < ETH_ALEN; i++)
  37                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
  38 +
  39 +       if (!is_valid_ether_addr(dev->dev_addr)) {
  40 +               /* Report it and use a random ethernet address instead */
  41 +               netdev_err(dev, "Invalid MAC address: %pM\n", dev->dev_addr);
  42 +               random_ether_addr(dev->dev_addr);
  43 +               netdev_info(dev, "Using random MAC address: %pM\n",
  44 +                           dev->dev_addr);
  45 +       }
  46         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  47
  48         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
  49 --
  50 1.7.7.3
  51
  52 From patchwork Sun Aug 12 11:57:49 2012
  53 Content-Type: text/plain; charset="utf-8"
  54 MIME-Version: 1.0
  55 Content-Transfer-Encoding: 7bit
  56 Subject: sp5100_tco: Add SB8x0 chipset support
  57 Date: Sun, 12 Aug 2012 11:57:49 -0000
  58 From: Takahisa Tanaka <mc74hc00@gmail.com>
  59 X-Patchwork-Id: 1309571
  60 Message-Id: <1344772669-2872-1-git-send-email-mc74hc00@gmail.com>
  61 To: linux-watchdog@vger.kernel.org
  62 Cc: wim@iguana.be, stable@kernel.org,
  63  paulepanter@users.sourceforge.net, post+kernel@ralfj.de,
  64  linux-kernel@vger.kernel.org, Takahisa Tanaka <mc74hc00@gmail.com>
  65
  66 The current sp5100_tco driver only supports SP5100/SB7x0 chipset, doesn't
  67 support SB8x0 chipset, because current sp5100_tco driver doesn't know that the
  68 offset address for watchdog timer was changed from SB8x0 chipset.
  69
  70 The offset address of SP5100 and SB7x0 chipsets are as follows, quote from the
  71 AMD SB700/710/750 Register Reference Guide(Page 164) and the AMD SP5100
  72 Register Reference Guide(Page 166).
  73
  74   WatchDogTimerControl 69h
  75   WatchDogTimerBase0   6Ch
  76   WatchDogTimerBase1   6Dh
  77   WatchDogTimerBase2   6Eh
  78   WatchDogTimerBase3   6Fh
  79
  80 In contrast, the offset address of SB8x0 chipset is as follows, quote from
  81 AMD SB800-Series Southbridges Register Reference Guide(Page 147).
  82
  83   WatchDogTimerEn      48h
  84   WatchDogTimerConfig  4Ch
  85
  86 So, In the case of SB8x0 chipset, sp5100_tco reads meaningless MMIO
  87 address(for example, 0xbafe00) from wrong offset address, and the following
  88 message is logged.
  89
  90    SP5100 TCO timer: mmio address 0xbafe00 already in use
  91
  92 With this patch, sp5100_tco driver supports SB8x0 chipset, and can avoid
  93 iomem resource conflict. The processing of this patch is as follows.
  94
  95  Step 1) Attempt to get the watchdog base address from indirect I/O(0xCD6
  96          and 0xCD7).
  97   - Go to the step 7 if obtained address hasn't conflicted with other
  98     resource. But, currently, the address(0xfec000f0) conflicts with the
  99     IOAPIC MMIO address, and the following message is logged.
 100
 101        SP5100 TCO timer: mmio address 0xfec000f0 already in use
 102
 103     0xfec000f0 is recommended by AMD BIOS Developer's Guide. So, go to the
 104     next step.
 105
 106  Step 2) Attempt to get the SBResource_MMIO base address from AcpiMmioEN(for
 107          SB8x0,  PM_Reg:24h) or SBResource_MMIO(SP5100/SB7x0, PCI_Reg:9Ch)
 108          register.
 109   - Go to the step 7 if these register has enabled by BIOS, and obtained
 110     address hasn't conflicted with other resource.
 111   - If above condition isn't true, go to the next step.
 112
 113  Step 3) Attempt to get the free MMIO address from allocate_resource().
 114   - Go to the step 7 if these register has enabled by BIOS, and obtained
 115     address hasn't conflicted with other resource.
 116   - Driver initialization has failed if obtained address has conflicted
 117     with other resource, and no 'force_addr' parameter is specified.
 118
 119  Step 4) Use the specified address If 'force_addr' parameter is specified.
 120   - allocate_resource() function may fail, when the PCI bridge device occupies
 121     iomem resource from 0xf0000000 to 0xffffffff. To handle such a case,
 122     I added 'force_addr' parameter to sp5100_tco driver. With 'force_addr'
 123     parameter, sp5100_tco driver directly can assign MMIO address for watchdog
 124     timer from free iomem region. Note that It's dangerous to specify wrong
 125     address in the 'force_addr' parameter.
 126
 127       Example of force_addr parameter use
 128         # cat /proc/iomem
 129         ...snip...
 130         fec00000-fec003ff : IOAPIC 0
 131                                       <--- free MMIO region
 132         fec10000-fec1001f : pnp 00:0b
 133         fec20000-fec203ff : IOAPIC 1
 134         ...snip...
 135         # cat /etc/modprobe.d/sp5100_tco.conf
 136         options sp5100_tco force_addr=0xfec00800
 137         # modprobe sp5100_tco
 138         # cat /proc/iomem
 139         ...snip...
 140         fec00000-fec003ff : IOAPIC 0
 141         fec00800-fec00807 : SP5100 TCO  <--- watchdog timer MMIO address
 142         fec10000-fec1001f : pnp 00:0b
 143         fec20000-fec203ff : IOAPIC 1
 144         ...snip...
 145         #
 146
 147   - Driver initialization has failed if specified address has conflicted
 148     with other resource.
 149
 150  Step 5) Disable the watchdog timer
 151   - To rewrite the watchdog timer register of the chipset, absolutely
 152     guarantee that the watchdog timer is disabled.
 153
 154  Step 6) Re-program the watchdog timer MMIO address to chipset.
 155   - Re-program the obtained MMIO address in Step 3 or Step 4 to chipset via
 156     indirect I/O(0xCD6 and 0xCD7).
 157
 158  Step 7) Enable and setup the watchdog timer
 159
 160 This patch has worked fine on my test environment(ASUS M4A89GTD-PRO/USB3 and
 161 DL165G7). therefore I believe that it's no problem to re-program the MMIO
 162 address for watchdog timer to chipset during disabled watchdog. However,
 163 I'm not sure about it, because I don't know much about chipset programming.
 164
 165 So, any comments will be welcome.
 166
 167 Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
 168 CC: stable@kernel.org
 169 Signed-off-by: Takahisa Tanaka <mc74hc00@gmail.com>
 170
 171 ---
 172 drivers/watchdog/sp5100_tco.c | 291 ++++++++++++++++++++++++++++++++++++------
 173  drivers/watchdog/sp5100_tco.h |  46 +++++--
 174  2 files changed, 286 insertions(+), 51 deletions(-)
 175
 176 diff --git a/drivers/watchdog/sp5100_tco.c b/drivers/watchdog/sp5100_tco.c
 177 index ae5e82c..36e917f 100644
 178 --- a/drivers/watchdog/sp5100_tco.c
 179 +++ b/drivers/watchdog/sp5100_tco.c
 180 @@ -13,7 +13,9 @@
 181   *     as published by the Free Software Foundation; either version
 182   *     2 of the License, or (at your option) any later version.
 183   *
 184 - *     See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide"
 185 + *     See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide",
 186 + *         AMD Publication 45482 "AMD SB800-Series Sourthbridges Register
 187 + *                                                           Reference Guide"
 188   */
 189
 190  /*
 191 @@ -38,18 +40,23 @@
 192  #include "sp5100_tco.h"
 193
 194  /* Module and version information */
 195 -#define TCO_VERSION "0.01"
 196 +#define TCO_VERSION "0.03"
 197  #define TCO_MODULE_NAME "SP5100 TCO timer"
 198  #define TCO_DRIVER_NAME   TCO_MODULE_NAME ", v" TCO_VERSION
 199
 200  /* internal variables */
 201  static u32 tcobase_phys;
 202 +static u32 resbase_phys;
 203  static void __iomem *tcobase;
 204  static unsigned int pm_iobase;
 205  static DEFINE_SPINLOCK(tco_lock);      /* Guards the hardware */
 206  static unsigned long timer_alive;
 207  static char tco_expect_close;
 208  static struct pci_dev *sp5100_tco_pci;
 209 +static struct resource wdt_res = {
 210 +       .name = "Watchdog Timer",
 211 +       .flags = IORESOURCE_MEM,
 212 +};
 213
 214  /* the watchdog platform device */
 215  static struct platform_device *sp5100_tco_platform_device;
 216 @@ -67,6 +74,12 @@ module_param(nowayout, bool, 0);
 217  MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started"
 218                 " (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
 219
 220 +static unsigned int force_addr;
 221 +module_param(force_addr, uint, 0);
 222 +MODULE_PARM_DESC(force_addr, "Force the use of specified MMIO address, "
 223 +               "default is disabled. DON'T USE THIS PARAMETER ONLY "
 224 +               "IF YOU REALLY KNOW WHAT YOU ARE DOING");
 225 +
 226  /*
 227   * Some TCO specific functions
 228   */
 229 @@ -122,6 +135,79 @@ static int tco_timer_set_heartbeat(int t)
 230         return 0;
 231  }
 232
 233 +static void tco_timer_enable(void)
 234 +{
 235 +       int val;
 236 +
 237 +       if (sp5100_tco_pci->revision >= 0x40) {
 238 +               /* For SB800 or later */
 239 +               /* Set the Watchdog timer resolution to 1 sec */
 240 +               outb(SB800_PM_WATCHDOG_CONFIG, SB800_IO_PM_INDEX_REG);
 241 +               val = inb(SB800_IO_PM_DATA_REG);
 242 +               val |= SB800_PM_WATCHDOG_SECOND_RES;
 243 +               outb(val, SB800_IO_PM_DATA_REG);
 244 +
 245 +               /* Enable watchdog decode bit and watchdog timer */
 246 +               outb(SB800_PM_WATCHDOG_CONTROL, SB800_IO_PM_INDEX_REG);
 247 +               val = inb(SB800_IO_PM_DATA_REG);
 248 +               val |= SB800_PCI_WATCHDOG_DECODE_EN;
 249 +               val &= ~SB800_PM_WATCHDOG_DISABLE;
 250 +               outb(val, SB800_IO_PM_DATA_REG);
 251 +       } else {
 252 +               /* For SP5100 or SB7x0 */
 253 +               /* Enable watchdog decode bit */
 254 +               pci_read_config_dword(sp5100_tco_pci,
 255 +                                     SP5100_PCI_WATCHDOG_MISC_REG,
 256 +                                     &val);
 257 +
 258 +               val |= SP5100_PCI_WATCHDOG_DECODE_EN;
 259 +
 260 +               pci_write_config_dword(sp5100_tco_pci,
 261 +                                      SP5100_PCI_WATCHDOG_MISC_REG,
 262 +                                      val);
 263 +
 264 +               /* Enable Watchdog timer and set the resolution to 1 sec */
 265 +               outb(SP5100_PM_WATCHDOG_CONTROL, SP5100_IO_PM_INDEX_REG);
 266 +               val = inb(SP5100_IO_PM_DATA_REG);
 267 +               val |= SP5100_PM_WATCHDOG_SECOND_RES;
 268 +               val &= ~SP5100_PM_WATCHDOG_DISABLE;
 269 +               outb(val, SP5100_IO_PM_DATA_REG);
 270 +       }
 271 +}
 272 +
 273 +static void tco_timer_disable(void)
 274 +{
 275 +       int val;
 276 +
 277 +       if (sp5100_tco_pci->revision >= 0x40) {
 278 +               /* For SB800 or later */
 279 +               /* Enable watchdog decode bit and Disable watchdog timer */
 280 +               outb(SB800_PM_WATCHDOG_CONTROL, SB800_IO_PM_INDEX_REG);
 281 +               val = inb(SB800_IO_PM_DATA_REG);
 282 +               val |= SB800_PCI_WATCHDOG_DECODE_EN;
 283 +               val |= SB800_PM_WATCHDOG_DISABLE;
 284 +               outb(val, SB800_IO_PM_DATA_REG);
 285 +       } else {
 286 +               /* For SP5100 or SB7x0 */
 287 +               /* Enable watchdog decode bit */
 288 +               pci_read_config_dword(sp5100_tco_pci,
 289 +                                     SP5100_PCI_WATCHDOG_MISC_REG,
 290 +                                     &val);
 291 +
 292 +               val |= SP5100_PCI_WATCHDOG_DECODE_EN;
 293 +
 294 +               pci_write_config_dword(sp5100_tco_pci,
 295 +                                      SP5100_PCI_WATCHDOG_MISC_REG,
 296 +                                      val);
 297 +
 298 +               /* Disable Watchdog timer */
 299 +               outb(SP5100_PM_WATCHDOG_CONTROL, SP5100_IO_PM_INDEX_REG);
 300 +               val = inb(SP5100_IO_PM_DATA_REG);
 301 +               val |= SP5100_PM_WATCHDOG_DISABLE;
 302 +               outb(val, SP5100_IO_PM_DATA_REG);
 303 +       }
 304 +}
 305 +
 306  /*
 307   *     /dev/watchdog handling
 308   */
 309 @@ -270,11 +356,12 @@ MODULE_DEVICE_TABLE(pci, sp5100_tco_pci_tbl);
 310  /*
 311   * Init & exit routines
 312   */
 313 -
 314  static unsigned char __devinit sp5100_tco_setupdevice(void)
 315  {
 316         struct pci_dev *dev = NULL;
 317 +       const char *dev_name = NULL;
 318         u32 val;
 319 +       u32 index_reg, data_reg, base_addr;
 320
 321         /* Match the PCI device */
 322         for_each_pci_dev(dev) {
 323 @@ -287,29 +374,158 @@ static unsigned char __devinit sp5100_tco_setupdevice(void)
 324         if (!sp5100_tco_pci)
 325                 return 0;
 326
 327 +       pr_info("PCI Revision ID: 0x%x\n", sp5100_tco_pci->revision);
 328 +
 329 +       /*
 330 +        * Determine type of southbridge chipset.
 331 +        */
 332 +       if (sp5100_tco_pci->revision >= 0x40) {
 333 +               dev_name = SB800_DEVNAME;
 334 +               index_reg = SB800_IO_PM_INDEX_REG;
 335 +               data_reg = SB800_IO_PM_DATA_REG;
 336 +               base_addr = SB800_PM_WATCHDOG_BASE;
 337 +       } else {
 338 +               dev_name = SP5100_DEVNAME;
 339 +               index_reg = SP5100_IO_PM_INDEX_REG;
 340 +               data_reg = SP5100_IO_PM_DATA_REG;
 341 +               base_addr = SP5100_PM_WATCHDOG_BASE;
 342 +       }
 343 +
 344         /* Request the IO ports used by this driver */
 345         pm_iobase = SP5100_IO_PM_INDEX_REG;
 346 -       if (!request_region(pm_iobase, SP5100_PM_IOPORTS_SIZE, "SP5100 TCO")) {
 347 -               pr_err("I/O address 0x%04x already in use\n", pm_iobase);
 348 +       if (!request_region(pm_iobase, SP5100_PM_IOPORTS_SIZE, dev_name)) {
 349 +               pr_err("I/O address 0x%08x already in use\n", pm_iobase);
 350                 goto exit;
 351         }
 352
 353 -       /* Find the watchdog base address. */
 354 -       outb(SP5100_PM_WATCHDOG_BASE3, SP5100_IO_PM_INDEX_REG);
 355 -       val = inb(SP5100_IO_PM_DATA_REG);
 356 -       outb(SP5100_PM_WATCHDOG_BASE2, SP5100_IO_PM_INDEX_REG);
 357 -       val = val << 8 | inb(SP5100_IO_PM_DATA_REG);
 358 -       outb(SP5100_PM_WATCHDOG_BASE1, SP5100_IO_PM_INDEX_REG);
 359 -       val = val << 8 | inb(SP5100_IO_PM_DATA_REG);
 360 -       outb(SP5100_PM_WATCHDOG_BASE0, SP5100_IO_PM_INDEX_REG);
 361 -       /* Low three bits of BASE0 are reserved. */
 362 -       val = val << 8 | (inb(SP5100_IO_PM_DATA_REG) & 0xf8);
 363 +       /*
 364 +        * First, Find the watchdog timer MMIO address from indirect I/O.
 365 +        */
 366 +       outb(base_addr+3, index_reg);
 367 +       val = inb(data_reg);
 368 +       outb(base_addr+2, index_reg);
 369 +       val = val << 8 | inb(data_reg);
 370 +       outb(base_addr+1, index_reg);
 371 +       val = val << 8 | inb(data_reg);
 372 +       outb(base_addr+0, index_reg);
 373 +       /* Low three bits of BASE are reserved */
 374 +       val = val << 8 | (inb(data_reg) & 0xf8);
 375 +
 376 +       pr_debug("Got 0x%08x from indirect I/O\n", val);
 377 +
 378 +       /* Check MMIO address conflict */
 379 +       if (request_mem_region_exclusive(val, SP5100_WDT_MEM_MAP_SIZE,
 380 +                                                               dev_name))
 381 +               goto setup_wdt;
 382 +       else
 383 +               pr_debug("MMIO address 0x%08x already in use\n", val);
 384 +
 385 +       /*
 386 +        * Second, Find the watchdog timer MMIO address
 387 +        * from SBResource_MMIO register.
 388 +        */
 389 +       if (sp5100_tco_pci->revision >= 0x40) {
 390 +               /* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */
 391 +               outb(SB800_PM_ACPI_MMIO_EN+3, SB800_IO_PM_INDEX_REG);
 392 +               val = inb(SB800_IO_PM_DATA_REG);
 393 +               outb(SB800_PM_ACPI_MMIO_EN+2, SB800_IO_PM_INDEX_REG);
 394 +               val = val << 8 | inb(SB800_IO_PM_DATA_REG);
 395 +               outb(SB800_PM_ACPI_MMIO_EN+1, SB800_IO_PM_INDEX_REG);
 396 +               val = val << 8 | inb(SB800_IO_PM_DATA_REG);
 397 +               outb(SB800_PM_ACPI_MMIO_EN+0, SB800_IO_PM_INDEX_REG);
 398 +               val = val << 8 | inb(SB800_IO_PM_DATA_REG);
 399 +       } else {
 400 +               /* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */
 401 +               pci_read_config_dword(sp5100_tco_pci,
 402 +                                     SP5100_SB_RESOURCE_MMIO_BASE, &val);
 403 +       }
 404 +
 405 +       /* The SBResource_MMIO is enabled and mapped memory space? */
 406 +       if ((val & (SB800_ACPI_MMIO_DECODE_EN | SB800_ACPI_MMIO_SEL)) ==
 407 +                                                 SB800_ACPI_MMIO_DECODE_EN) {
 408 +               /* Clear unnecessary the low twelve bits */
 409 +               val &= ~0xFFF;
 410 +               /* Add the Watchdog Timer offset to base address. */
 411 +               val += SB800_PM_WDT_MMIO_OFFSET;
 412 +               /* Check mmio base address conflict */
 413 +               if (request_mem_region_exclusive(val, SP5100_WDT_MEM_MAP_SIZE,
 414 +                                                                  dev_name)) {
 415 +                       pr_debug("Got 0x%08x from SBResource_MMIO register\n",
 416 +                               val);
 417 +                       goto setup_wdt;
 418 +               } else
 419 +                       pr_debug("MMIO address 0x%08x already in use\n", val);
 420 +       } else
 421 +               pr_debug("SBResource_MMIO is disabled(0x%08x)\n", val);
 422 +
 423 +       /*
 424 +        * Lastly re-programming the watchdog MMIO address,
 425 +        * This method is a last resort...
 426 +        *
 427 +        * Before re-programming, to ensure that the watchdog timer
 428 +        * is disabled, disable the watchdog timer.
 429 +        */
 430 +       tco_timer_disable();
 431 +
 432 +       if (force_addr) {
 433 +               /* Force the use of base address */
 434 +               val = force_addr;
 435 +               /* The alignment of the MMIO address to a 8byte boundary */
 436 +               val &= ~0x7;
 437 +
 438 +               pr_info("Force the use of 0x%08x as MMIO address\n", val);
 439 +       } else {
 440 +               /*
 441 +                * Get empty slot into the resource tree for watchdog timer.
 442 +                */
 443 +               if (allocate_resource(&iomem_resource,
 444 +                                     &wdt_res,
 445 +                                     SP5100_WDT_MEM_MAP_SIZE,
 446 +                                     0xf0000000,
 447 +                                     0xfffffff8,
 448 +                                     0x8,
 449 +                                     NULL,
 450 +                                     NULL)) {
 451 +                       pr_err("MMIO allocation failed\n");
 452 +                       goto unreg_region;
 453 +               }
 454 +
 455 +               val = resbase_phys = wdt_res.start;
 456 +               pr_debug("Got 0x%08x from resource tree\n", val);
 457 +       }
 458 +
 459 +       /* Restore to the low three bits, if chipset is SB8x0(or later) */
 460 +       if (sp5100_tco_pci->revision >= 0x40) {
 461 +               u8 reserved_bit;
 462 +               reserved_bit = inb(base_addr) & 0x7;
 463 +               val |= (u32)reserved_bit;
 464 +       }
 465 +
 466 +       /* Re-programming the watchdog timer base address */
 467 +       outb(base_addr+0, index_reg);
 468 +       /* Low three bits of BASE are reserved */
 469 +       outb((val >>  0) & 0xf8, data_reg);
 470 +       outb(base_addr+1, index_reg);
 471 +       outb((val >>  8) & 0xff, data_reg);
 472 +       outb(base_addr+2, index_reg);
 473 +       outb((val >> 16) & 0xff, data_reg);
 474 +       outb(base_addr+3, index_reg);
 475 +       outb((val >> 24) & 0xff, data_reg);
 476 +
 477 +       /*
 478 +        * Clear unnecessary the low three bits,
 479 +        * if chipset is SB8x0(or later)
 480 +        */
 481 +       if (sp5100_tco_pci->revision >= 0x40)
 482 +               val &= ~0x7;
 483
 484         if (!request_mem_region_exclusive(val, SP5100_WDT_MEM_MAP_SIZE,
 485 -                                                               "SP5100 TCO")) {
 486 -               pr_err("mmio address 0x%04x already in use\n", val);
 487 -               goto unreg_region;
 488 +                                                                  dev_name)) {
 489 +               pr_err("MMIO address 0x%08x already in use\n", val);
 490 +               goto unreg_resource;
 491         }
 492 +
 493 +setup_wdt:
 494         tcobase_phys = val;
 495
 496         tcobase = ioremap(val, SP5100_WDT_MEM_MAP_SIZE);
 497 @@ -318,25 +534,12 @@ static unsigned char __devinit sp5100_tco_setupdevice(void)
 498                 goto unreg_mem_region;
 499         }
 500
 501 -       /* Enable watchdog decode bit */
 502 -       pci_read_config_dword(sp5100_tco_pci,
 503 -                             SP5100_PCI_WATCHDOG_MISC_REG,
 504 -                             &val);
 505 -
 506 -       val |= SP5100_PCI_WATCHDOG_DECODE_EN;
 507 -
 508 -       pci_write_config_dword(sp5100_tco_pci,
 509 -                              SP5100_PCI_WATCHDOG_MISC_REG,
 510 -                              val);
 511 +       pr_info("Using 0x%08x for watchdog MMIO address\n", val);
 512
 513 -       /* Enable Watchdog timer and set the resolution to 1 sec. */
 514 -       outb(SP5100_PM_WATCHDOG_CONTROL, SP5100_IO_PM_INDEX_REG);
 515 -       val = inb(SP5100_IO_PM_DATA_REG);
 516 -       val |= SP5100_PM_WATCHDOG_SECOND_RES;
 517 -       val &= ~SP5100_PM_WATCHDOG_DISABLE;
 518 -       outb(val, SP5100_IO_PM_DATA_REG);
 519 +       /* Setup the watchdog timer */
 520 +       tco_timer_enable();
 521
 522 -       /* Check that the watchdog action is set to reset the system. */
 523 +       /* Check that the watchdog action is set to reset the system */
 524         val = readl(SP5100_WDT_CONTROL(tcobase));
 525         val &= ~SP5100_PM_WATCHDOG_ACTION_RESET;
 526         writel(val, SP5100_WDT_CONTROL(tcobase));
 527 @@ -355,6 +558,9 @@ static unsigned char __devinit sp5100_tco_setupdevice(void)
 528
 529  unreg_mem_region:
 530         release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE);
 531 +unreg_resource:
 532 +       if (resbase_phys)
 533 +               release_resource(&wdt_res);
 534  unreg_region:
 535         release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE);
 536  exit:
 537 @@ -400,14 +606,17 @@ static int __devinit sp5100_tco_init(struct platform_device *dev)
 538
 539         clear_bit(0, &timer_alive);
 540
 541 -       pr_info("initialized (0x%p). heartbeat=%d sec (nowayout=%d)\n",
 542 -               tcobase, heartbeat, nowayout);
 543 +       pr_info("initialized (0x%p). heartbeat=%d sec (nowayout=%d, "
 544 +               "force_addr=0x%x)\n",
 545 +               tcobase, heartbeat, nowayout, force_addr);
 546
 547         return 0;
 548
 549  exit:
 550         iounmap(tcobase);
 551         release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE);
 552 +       if (resbase_phys)
 553 +               release_resource(&wdt_res);
 554         release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE);
 555         return ret;
 556  }
 557 @@ -422,6 +631,8 @@ static void __devexit sp5100_tco_cleanup(void)
 558         misc_deregister(&sp5100_tco_miscdev);
 559         iounmap(tcobase);
 560         release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE);
 561 +       if (resbase_phys)
 562 +               release_resource(&wdt_res);
 563         release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE);
 564  }
 565
 566 @@ -451,7 +662,7 @@ static int __init sp5100_tco_init_module(void)
 567  {
 568         int err;
 569
 570 -       pr_info("SP5100 TCO WatchDog Timer Driver v%s\n", TCO_VERSION);
 571 +       pr_info("SP5100/SB800 TCO WatchDog Timer Driver v%s\n", TCO_VERSION);
 572
 573         err = platform_driver_register(&sp5100_tco_driver);
 574         if (err)
 575 @@ -475,13 +686,13 @@ static void __exit sp5100_tco_cleanup_module(void)
 576  {
 577         platform_device_unregister(sp5100_tco_platform_device);
 578         platform_driver_unregister(&sp5100_tco_driver);
 579 -       pr_info("SP5100 TCO Watchdog Module Unloaded\n");
 580 +       pr_info("SP5100/SB800 TCO Watchdog Module Unloaded\n");
 581  }
 582
 583  module_init(sp5100_tco_init_module);
 584  module_exit(sp5100_tco_cleanup_module);
 585
 586  MODULE_AUTHOR("Priyanka Gupta");
 587 -MODULE_DESCRIPTION("TCO timer driver for SP5100 chipset");
 588 +MODULE_DESCRIPTION("TCO timer driver for SP5100/SB800 chipset");
 589  MODULE_LICENSE("GPL");
 590  MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
 591 diff --git a/drivers/watchdog/sp5100_tco.h b/drivers/watchdog/sp5100_tco.h
 592 index a5a16cc..71594a0 100644
 593 --- a/drivers/watchdog/sp5100_tco.h
 594 +++ b/drivers/watchdog/sp5100_tco.h
 595 @@ -9,33 +9,57 @@
 596  /*
 597   * Some address definitions for the Watchdog
 598   */
 599 -
 600  #define SP5100_WDT_MEM_MAP_SIZE                0x08
 601  #define SP5100_WDT_CONTROL(base)       ((base) + 0x00) /* Watchdog Control */
 602  #define SP5100_WDT_COUNT(base)         ((base) + 0x04) /* Watchdog Count */
 603
 604 -#define SP5100_WDT_START_STOP_BIT      1
 605 +#define SP5100_WDT_START_STOP_BIT      (1 << 0)
 606  #define SP5100_WDT_TRIGGER_BIT         (1 << 7)
 607
 608 -#define SP5100_PCI_WATCHDOG_MISC_REG   0x41
 609 -#define SP5100_PCI_WATCHDOG_DECODE_EN  (1 << 3)
 610 -
 611  #define SP5100_PM_IOPORTS_SIZE         0x02
 612
 613 -/* These two IO registers are hardcoded and there doesn't seem to be a way to
 614 +/*
 615 + * These two IO registers are hardcoded and there doesn't seem to be a way to
 616   * read them from a register.
 617   */
 618 +
 619 +/*  For SP5100/SB7x0 chipset */
 620  #define SP5100_IO_PM_INDEX_REG         0xCD6
 621  #define SP5100_IO_PM_DATA_REG          0xCD7
 622
 623 +#define SP5100_SB_RESOURCE_MMIO_BASE   0x9C
 624 +
 625  #define SP5100_PM_WATCHDOG_CONTROL     0x69
 626 -#define SP5100_PM_WATCHDOG_BASE0       0x6C
 627 -#define SP5100_PM_WATCHDOG_BASE1       0x6D
 628 -#define SP5100_PM_WATCHDOG_BASE2       0x6E
 629 -#define SP5100_PM_WATCHDOG_BASE3       0x6F
 630 +#define SP5100_PM_WATCHDOG_BASE                0x6C
 631
 632  #define SP5100_PM_WATCHDOG_FIRED       (1 << 1)
 633  #define SP5100_PM_WATCHDOG_ACTION_RESET        (1 << 2)
 634
 635 -#define SP5100_PM_WATCHDOG_DISABLE     1
 636 +#define SP5100_PCI_WATCHDOG_MISC_REG   0x41
 637 +#define SP5100_PCI_WATCHDOG_DECODE_EN  (1 << 3)
 638 +
 639 +#define SP5100_PM_WATCHDOG_DISABLE     (1 << 0)
 640  #define SP5100_PM_WATCHDOG_SECOND_RES  (3 << 1)
 641 +
 642 +#define SP5100_DEVNAME                 "SP5100 TCO"
 643 +
 644 +
 645 +/*  For SB8x0(or later) chipset */
 646 +#define SB800_IO_PM_INDEX_REG          0xCD6
 647 +#define SB800_IO_PM_DATA_REG           0xCD7
 648 +
 649 +#define SB800_PM_ACPI_MMIO_EN          0x24
 650 +#define SB800_PM_WATCHDOG_CONTROL      0x48
 651 +#define SB800_PM_WATCHDOG_BASE         0x48
 652 +#define SB800_PM_WATCHDOG_CONFIG       0x4C
 653 +
 654 +#define SB800_PCI_WATCHDOG_DECODE_EN   (1 << 0)
 655 +#define SB800_PM_WATCHDOG_DISABLE      (1 << 2)
 656 +#define SB800_PM_WATCHDOG_SECOND_RES   (3 << 0)
 657 +#define SB800_ACPI_MMIO_DECODE_EN      (1 << 0)
 658 +#define SB800_ACPI_MMIO_SEL            (1 << 2)
 659 +
 660 +
 661 +#define SB800_PM_WDT_MMIO_OFFSET       0xB00
 662 +
 663 +#define SB800_DEVNAME                  "SB800 TCO"