kernel-small_fixes.patch

   1 --- linux-2.6.33/scripts/mod/modpost.c~ 2010-02-24 19:52:17.000000000 +0100
   2 +++ linux-2.6.33/scripts/mod/modpost.c  2010-03-07 14:26:47.242168558 +0100
   3 @@ -15,7 +15,8 @@
   4  #include <stdio.h>
   5  #include <ctype.h>
   6  #include "modpost.h"
   7 -#include "../../include/generated/autoconf.h"
   8 +// PLD architectures don't use CONFIG_SYMBOL_PREFIX
   9 +//#include "../../include/generated/autoconf.h"
  10  #include "../../include/linux/license.h"
  11
  12  /* Some toolchains use a `_' prefix for all user symbols. */
  13
  14 --- linux-3.0/scripts/kconfig/lxdialog/check-lxdialog.sh~       2011-07-22 04:17:23.000000000 +0200
  15 +++ linux-3.0/scripts/kconfig/lxdialog/check-lxdialog.sh        2011-08-25 21:26:04.799150642 +0200
  16 @@ -9,6 +9,12 @@
  17                         $cc -print-file-name=lib${lib}.${ext} | grep -q /
  18                         if [ $? -eq 0 ]; then
  19                                 echo "-l${lib}"
  20 +                               for libt in tinfow tinfo ; do
  21 +                                       $cc -print-file-name=lib${libt}.${ext} | grep -q /
  22 +                                       if [ $? -eq 0 ]; then
  23 +                                               echo "-l${libt}"
  24 +                                       fi
  25 +                               done
  26                                 exit
  27                         fi
  28                 done
  29
  30 diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
  31 index 7a0c800..ec5ebbb 100644
  32 --- a/drivers/net/ethernet/realtek/r8169.c
  33 +++ b/drivers/net/ethernet/realtek/r8169.c
  34 @@ -4103,6 +4103,14 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  35         /* Get MAC address */
  36         for (i = 0; i < ETH_ALEN; i++)
  37                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
  38 +
  39 +       if (!is_valid_ether_addr(dev->dev_addr)) {
  40 +               /* Report it and use a random ethernet address instead */
  41 +               netdev_err(dev, "Invalid MAC address: %pM\n", dev->dev_addr);
  42 +               random_ether_addr(dev->dev_addr);
  43 +               netdev_info(dev, "Using random MAC address: %pM\n",
  44 +                           dev->dev_addr);
  45 +       }
  46         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
  47
  48         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
  49 --
  50 1.7.7.3
  51
  52
  53 --- linux-3.4/fs/unionfs/commonfops.c.org       2012-05-29 20:40:20.756489877 +0200
  54 +++ linux-3.4/fs/unionfs/commonfops.c   2012-05-29 21:07:12.021252743 +0200
  55 @@ -766,7 +766,7 @@
  56                                    unsigned int cmd, unsigned long arg)
  57  {
  58         int err = 0;
  59 -       fd_set branchlist;
  60 +       unsigned long branchlist = 0;
  61         int bstart = 0, bend = 0, bindex = 0;
  62         int orig_bstart, orig_bend;
  63         struct dentry *dentry, *lower_dentry;
  64 @@ -781,14 +781,12 @@
  65         bstart = dbstart(dentry);
  66         bend = dbend(dentry);
  67
  68 -       FD_ZERO(&branchlist);
  69 -
  70         for (bindex = bstart; bindex <= bend; bindex++) {
  71                 lower_dentry = unionfs_lower_dentry_idx(dentry, bindex);
  72                 if (!lower_dentry)
  73                         continue;
  74                 if (likely(lower_dentry->d_inode))
  75 -                       FD_SET(bindex, &branchlist);
  76 +                       __set_bit(bindex, &branchlist);
  77                 /* purge any lower objects after partial_lookup */
  78                 if (bindex < orig_bstart || bindex > orig_bend) {
  79                         dput(lower_dentry);
  80
  81 From patchwork Sun Aug 12 11:57:49 2012
  82 Content-Type: text/plain; charset="utf-8"
  83 MIME-Version: 1.0
  84 Content-Transfer-Encoding: 7bit
  85 Subject: sp5100_tco: Add SB8x0 chipset support
  86 Date: Sun, 12 Aug 2012 11:57:49 -0000
  87 From: Takahisa Tanaka <mc74hc00@gmail.com>
  88 X-Patchwork-Id: 1309571
  89 Message-Id: <1344772669-2872-1-git-send-email-mc74hc00@gmail.com>
  90 To: linux-watchdog@vger.kernel.org
  91 Cc: wim@iguana.be, stable@kernel.org,
  92  paulepanter@users.sourceforge.net, post+kernel@ralfj.de,
  93  linux-kernel@vger.kernel.org, Takahisa Tanaka <mc74hc00@gmail.com>
  94
  95 The current sp5100_tco driver only supports SP5100/SB7x0 chipset, doesn't
  96 support SB8x0 chipset, because current sp5100_tco driver doesn't know that the
  97 offset address for watchdog timer was changed from SB8x0 chipset.
  98
  99 The offset address of SP5100 and SB7x0 chipsets are as follows, quote from the
 100 AMD SB700/710/750 Register Reference Guide(Page 164) and the AMD SP5100
 101 Register Reference Guide(Page 166).
 102
 103   WatchDogTimerControl 69h
 104   WatchDogTimerBase0   6Ch
 105   WatchDogTimerBase1   6Dh
 106   WatchDogTimerBase2   6Eh
 107   WatchDogTimerBase3   6Fh
 108
 109 In contrast, the offset address of SB8x0 chipset is as follows, quote from
 110 AMD SB800-Series Southbridges Register Reference Guide(Page 147).
 111
 112   WatchDogTimerEn      48h
 113   WatchDogTimerConfig  4Ch
 114
 115 So, In the case of SB8x0 chipset, sp5100_tco reads meaningless MMIO
 116 address(for example, 0xbafe00) from wrong offset address, and the following
 117 message is logged.
 118
 119    SP5100 TCO timer: mmio address 0xbafe00 already in use
 120
 121 With this patch, sp5100_tco driver supports SB8x0 chipset, and can avoid
 122 iomem resource conflict. The processing of this patch is as follows.
 123
 124  Step 1) Attempt to get the watchdog base address from indirect I/O(0xCD6
 125          and 0xCD7).
 126   - Go to the step 7 if obtained address hasn't conflicted with other
 127     resource. But, currently, the address(0xfec000f0) conflicts with the
 128     IOAPIC MMIO address, and the following message is logged.
 129
 130        SP5100 TCO timer: mmio address 0xfec000f0 already in use
 131
 132     0xfec000f0 is recommended by AMD BIOS Developer's Guide. So, go to the
 133     next step.
 134
 135  Step 2) Attempt to get the SBResource_MMIO base address from AcpiMmioEN(for
 136          SB8x0,  PM_Reg:24h) or SBResource_MMIO(SP5100/SB7x0, PCI_Reg:9Ch)
 137          register.
 138   - Go to the step 7 if these register has enabled by BIOS, and obtained
 139     address hasn't conflicted with other resource.
 140   - If above condition isn't true, go to the next step.
 141
 142  Step 3) Attempt to get the free MMIO address from allocate_resource().
 143   - Go to the step 7 if these register has enabled by BIOS, and obtained
 144     address hasn't conflicted with other resource.
 145   - Driver initialization has failed if obtained address has conflicted
 146     with other resource, and no 'force_addr' parameter is specified.
 147
 148  Step 4) Use the specified address If 'force_addr' parameter is specified.
 149   - allocate_resource() function may fail, when the PCI bridge device occupies
 150     iomem resource from 0xf0000000 to 0xffffffff. To handle such a case,
 151     I added 'force_addr' parameter to sp5100_tco driver. With 'force_addr'
 152     parameter, sp5100_tco driver directly can assign MMIO address for watchdog
 153     timer from free iomem region. Note that It's dangerous to specify wrong
 154     address in the 'force_addr' parameter.
 155
 156       Example of force_addr parameter use
 157         # cat /proc/iomem
 158         ...snip...
 159         fec00000-fec003ff : IOAPIC 0
 160                                       <--- free MMIO region
 161         fec10000-fec1001f : pnp 00:0b
 162         fec20000-fec203ff : IOAPIC 1
 163         ...snip...
 164         # cat /etc/modprobe.d/sp5100_tco.conf
 165         options sp5100_tco force_addr=0xfec00800
 166         # modprobe sp5100_tco
 167         # cat /proc/iomem
 168         ...snip...
 169         fec00000-fec003ff : IOAPIC 0
 170         fec00800-fec00807 : SP5100 TCO  <--- watchdog timer MMIO address
 171         fec10000-fec1001f : pnp 00:0b
 172         fec20000-fec203ff : IOAPIC 1
 173         ...snip...
 174         #
 175
 176   - Driver initialization has failed if specified address has conflicted
 177     with other resource.
 178
 179  Step 5) Disable the watchdog timer
 180   - To rewrite the watchdog timer register of the chipset, absolutely
 181     guarantee that the watchdog timer is disabled.
 182
 183  Step 6) Re-program the watchdog timer MMIO address to chipset.
 184   - Re-program the obtained MMIO address in Step 3 or Step 4 to chipset via
 185     indirect I/O(0xCD6 and 0xCD7).
 186
 187  Step 7) Enable and setup the watchdog timer
 188
 189 This patch has worked fine on my test environment(ASUS M4A89GTD-PRO/USB3 and
 190 DL165G7). therefore I believe that it's no problem to re-program the MMIO
 191 address for watchdog timer to chipset during disabled watchdog. However,
 192 I'm not sure about it, because I don't know much about chipset programming.
 193
 194 So, any comments will be welcome.
 195
 196 Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
 197 CC: stable@kernel.org
 198 Signed-off-by: Takahisa Tanaka <mc74hc00@gmail.com>
 199
 200 ---
 201 drivers/watchdog/sp5100_tco.c | 291 ++++++++++++++++++++++++++++++++++++------
 202  drivers/watchdog/sp5100_tco.h |  46 +++++--
 203  2 files changed, 286 insertions(+), 51 deletions(-)
 204
 205 diff --git a/drivers/watchdog/sp5100_tco.c b/drivers/watchdog/sp5100_tco.c
 206 index ae5e82c..36e917f 100644
 207 --- a/drivers/watchdog/sp5100_tco.c
 208 +++ b/drivers/watchdog/sp5100_tco.c
 209 @@ -13,7 +13,9 @@
 210   *     as published by the Free Software Foundation; either version
 211   *     2 of the License, or (at your option) any later version.
 212   *
 213 - *     See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide"
 214 + *     See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide",
 215 + *         AMD Publication 45482 "AMD SB800-Series Sourthbridges Register
 216 + *                                                           Reference Guide"
 217   */
 218
 219  /*
 220 @@ -38,18 +40,23 @@
 221  #include "sp5100_tco.h"
 222
 223  /* Module and version information */
 224 -#define TCO_VERSION "0.01"
 225 +#define TCO_VERSION "0.03"
 226  #define TCO_MODULE_NAME "SP5100 TCO timer"
 227  #define TCO_DRIVER_NAME   TCO_MODULE_NAME ", v" TCO_VERSION
 228
 229  /* internal variables */
 230  static u32 tcobase_phys;
 231 +static u32 resbase_phys;
 232  static void __iomem *tcobase;
 233  static unsigned int pm_iobase;
 234  static DEFINE_SPINLOCK(tco_lock);      /* Guards the hardware */
 235  static unsigned long timer_alive;
 236  static char tco_expect_close;
 237  static struct pci_dev *sp5100_tco_pci;
 238 +static struct resource wdt_res = {
 239 +       .name = "Watchdog Timer",
 240 +       .flags = IORESOURCE_MEM,
 241 +};
 242
 243  /* the watchdog platform device */
 244  static struct platform_device *sp5100_tco_platform_device;
 245 @@ -67,6 +74,12 @@ module_param(nowayout, bool, 0);
 246  MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started"
 247                 " (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
 248
 249 +static unsigned int force_addr;
 250 +module_param(force_addr, uint, 0);
 251 +MODULE_PARM_DESC(force_addr, "Force the use of specified MMIO address, "
 252 +               "default is disabled. DON'T USE THIS PARAMETER ONLY "
 253 +               "IF YOU REALLY KNOW WHAT YOU ARE DOING");
 254 +
 255  /*
 256   * Some TCO specific functions
 257   */
 258 @@ -122,6 +135,79 @@ static int tco_timer_set_heartbeat(int t)
 259         return 0;
 260  }
 261
 262 +static void tco_timer_enable(void)
 263 +{
 264 +       int val;
 265 +
 266 +       if (sp5100_tco_pci->revision >= 0x40) {
 267 +               /* For SB800 or later */
 268 +               /* Set the Watchdog timer resolution to 1 sec */
 269 +               outb(SB800_PM_WATCHDOG_CONFIG, SB800_IO_PM_INDEX_REG);
 270 +               val = inb(SB800_IO_PM_DATA_REG);
 271 +               val |= SB800_PM_WATCHDOG_SECOND_RES;
 272 +               outb(val, SB800_IO_PM_DATA_REG);
 273 +
 274 +               /* Enable watchdog decode bit and watchdog timer */
 275 +               outb(SB800_PM_WATCHDOG_CONTROL, SB800_IO_PM_INDEX_REG);
 276 +               val = inb(SB800_IO_PM_DATA_REG);
 277 +               val |= SB800_PCI_WATCHDOG_DECODE_EN;
 278 +               val &= ~SB800_PM_WATCHDOG_DISABLE;
 279 +               outb(val, SB800_IO_PM_DATA_REG);
 280 +       } else {
 281 +               /* For SP5100 or SB7x0 */
 282 +               /* Enable watchdog decode bit */
 283 +               pci_read_config_dword(sp5100_tco_pci,
 284 +                                     SP5100_PCI_WATCHDOG_MISC_REG,
 285 +                                     &val);
 286 +
 287 +               val |= SP5100_PCI_WATCHDOG_DECODE_EN;
 288 +
 289 +               pci_write_config_dword(sp5100_tco_pci,
 290 +                                      SP5100_PCI_WATCHDOG_MISC_REG,
 291 +                                      val);
 292 +
 293 +               /* Enable Watchdog timer and set the resolution to 1 sec */
 294 +               outb(SP5100_PM_WATCHDOG_CONTROL, SP5100_IO_PM_INDEX_REG);
 295 +               val = inb(SP5100_IO_PM_DATA_REG);
 296 +               val |= SP5100_PM_WATCHDOG_SECOND_RES;
 297 +               val &= ~SP5100_PM_WATCHDOG_DISABLE;
 298 +               outb(val, SP5100_IO_PM_DATA_REG);
 299 +       }
 300 +}
 301 +
 302 +static void tco_timer_disable(void)
 303 +{
 304 +       int val;
 305 +
 306 +       if (sp5100_tco_pci->revision >= 0x40) {
 307 +               /* For SB800 or later */
 308 +               /* Enable watchdog decode bit and Disable watchdog timer */
 309 +               outb(SB800_PM_WATCHDOG_CONTROL, SB800_IO_PM_INDEX_REG);
 310 +               val = inb(SB800_IO_PM_DATA_REG);
 311 +               val |= SB800_PCI_WATCHDOG_DECODE_EN;
 312 +               val |= SB800_PM_WATCHDOG_DISABLE;
 313 +               outb(val, SB800_IO_PM_DATA_REG);
 314 +       } else {
 315 +               /* For SP5100 or SB7x0 */
 316 +               /* Enable watchdog decode bit */
 317 +               pci_read_config_dword(sp5100_tco_pci,
 318 +                                     SP5100_PCI_WATCHDOG_MISC_REG,
 319 +                                     &val);
 320 +
 321 +               val |= SP5100_PCI_WATCHDOG_DECODE_EN;
 322 +
 323 +               pci_write_config_dword(sp5100_tco_pci,
 324 +                                      SP5100_PCI_WATCHDOG_MISC_REG,
 325 +                                      val);
 326 +
 327 +               /* Disable Watchdog timer */
 328 +               outb(SP5100_PM_WATCHDOG_CONTROL, SP5100_IO_PM_INDEX_REG);
 329 +               val = inb(SP5100_IO_PM_DATA_REG);
 330 +               val |= SP5100_PM_WATCHDOG_DISABLE;
 331 +               outb(val, SP5100_IO_PM_DATA_REG);
 332 +       }
 333 +}
 334 +
 335  /*
 336   *     /dev/watchdog handling
 337   */
 338 @@ -270,11 +356,12 @@ MODULE_DEVICE_TABLE(pci, sp5100_tco_pci_tbl);
 339  /*
 340   * Init & exit routines
 341   */
 342 -
 343  static unsigned char __devinit sp5100_tco_setupdevice(void)
 344  {
 345         struct pci_dev *dev = NULL;
 346 +       const char *dev_name = NULL;
 347         u32 val;
 348 +       u32 index_reg, data_reg, base_addr;
 349
 350         /* Match the PCI device */
 351         for_each_pci_dev(dev) {
 352 @@ -287,29 +374,158 @@ static unsigned char __devinit sp5100_tco_setupdevice(void)
 353         if (!sp5100_tco_pci)
 354                 return 0;
 355
 356 +       pr_info("PCI Revision ID: 0x%x\n", sp5100_tco_pci->revision);
 357 +
 358 +       /*
 359 +        * Determine type of southbridge chipset.
 360 +        */
 361 +       if (sp5100_tco_pci->revision >= 0x40) {
 362 +               dev_name = SB800_DEVNAME;
 363 +               index_reg = SB800_IO_PM_INDEX_REG;
 364 +               data_reg = SB800_IO_PM_DATA_REG;
 365 +               base_addr = SB800_PM_WATCHDOG_BASE;
 366 +       } else {
 367 +               dev_name = SP5100_DEVNAME;
 368 +               index_reg = SP5100_IO_PM_INDEX_REG;
 369 +               data_reg = SP5100_IO_PM_DATA_REG;
 370 +               base_addr = SP5100_PM_WATCHDOG_BASE;
 371 +       }
 372 +
 373         /* Request the IO ports used by this driver */
 374         pm_iobase = SP5100_IO_PM_INDEX_REG;
 375 -       if (!request_region(pm_iobase, SP5100_PM_IOPORTS_SIZE, "SP5100 TCO")) {
 376 -               pr_err("I/O address 0x%04x already in use\n", pm_iobase);
 377 +       if (!request_region(pm_iobase, SP5100_PM_IOPORTS_SIZE, dev_name)) {
 378 +               pr_err("I/O address 0x%08x already in use\n", pm_iobase);
 379                 goto exit;
 380         }
 381
 382 -       /* Find the watchdog base address. */
 383 -       outb(SP5100_PM_WATCHDOG_BASE3, SP5100_IO_PM_INDEX_REG);
 384 -       val = inb(SP5100_IO_PM_DATA_REG);
 385 -       outb(SP5100_PM_WATCHDOG_BASE2, SP5100_IO_PM_INDEX_REG);
 386 -       val = val << 8 | inb(SP5100_IO_PM_DATA_REG);
 387 -       outb(SP5100_PM_WATCHDOG_BASE1, SP5100_IO_PM_INDEX_REG);
 388 -       val = val << 8 | inb(SP5100_IO_PM_DATA_REG);
 389 -       outb(SP5100_PM_WATCHDOG_BASE0, SP5100_IO_PM_INDEX_REG);
 390 -       /* Low three bits of BASE0 are reserved. */
 391 -       val = val << 8 | (inb(SP5100_IO_PM_DATA_REG) & 0xf8);
 392 +       /*
 393 +        * First, Find the watchdog timer MMIO address from indirect I/O.
 394 +        */
 395 +       outb(base_addr+3, index_reg);
 396 +       val = inb(data_reg);
 397 +       outb(base_addr+2, index_reg);
 398 +       val = val << 8 | inb(data_reg);
 399 +       outb(base_addr+1, index_reg);
 400 +       val = val << 8 | inb(data_reg);
 401 +       outb(base_addr+0, index_reg);
 402 +       /* Low three bits of BASE are reserved */
 403 +       val = val << 8 | (inb(data_reg) & 0xf8);
 404 +
 405 +       pr_debug("Got 0x%08x from indirect I/O\n", val);
 406 +
 407 +       /* Check MMIO address conflict */
 408 +       if (request_mem_region_exclusive(val, SP5100_WDT_MEM_MAP_SIZE,
 409 +                                                               dev_name))
 410 +               goto setup_wdt;
 411 +       else
 412 +               pr_debug("MMIO address 0x%08x already in use\n", val);
 413 +
 414 +       /*
 415 +        * Second, Find the watchdog timer MMIO address
 416 +        * from SBResource_MMIO register.
 417 +        */
 418 +       if (sp5100_tco_pci->revision >= 0x40) {
 419 +               /* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */
 420 +               outb(SB800_PM_ACPI_MMIO_EN+3, SB800_IO_PM_INDEX_REG);
 421 +               val = inb(SB800_IO_PM_DATA_REG);
 422 +               outb(SB800_PM_ACPI_MMIO_EN+2, SB800_IO_PM_INDEX_REG);
 423 +               val = val << 8 | inb(SB800_IO_PM_DATA_REG);
 424 +               outb(SB800_PM_ACPI_MMIO_EN+1, SB800_IO_PM_INDEX_REG);
 425 +               val = val << 8 | inb(SB800_IO_PM_DATA_REG);
 426 +               outb(SB800_PM_ACPI_MMIO_EN+0, SB800_IO_PM_INDEX_REG);
 427 +               val = val << 8 | inb(SB800_IO_PM_DATA_REG);
 428 +       } else {
 429 +               /* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */
 430 +               pci_read_config_dword(sp5100_tco_pci,
 431 +                                     SP5100_SB_RESOURCE_MMIO_BASE, &val);
 432 +       }
 433 +
 434 +       /* The SBResource_MMIO is enabled and mapped memory space? */
 435 +       if ((val & (SB800_ACPI_MMIO_DECODE_EN | SB800_ACPI_MMIO_SEL)) ==
 436 +                                                 SB800_ACPI_MMIO_DECODE_EN) {
 437 +               /* Clear unnecessary the low twelve bits */
 438 +               val &= ~0xFFF;
 439 +               /* Add the Watchdog Timer offset to base address. */
 440 +               val += SB800_PM_WDT_MMIO_OFFSET;
 441 +               /* Check mmio base address conflict */
 442 +               if (request_mem_region_exclusive(val, SP5100_WDT_MEM_MAP_SIZE,
 443 +                                                                  dev_name)) {
 444 +                       pr_debug("Got 0x%08x from SBResource_MMIO register\n",
 445 +                               val);
 446 +                       goto setup_wdt;
 447 +               } else
 448 +                       pr_debug("MMIO address 0x%08x already in use\n", val);
 449 +       } else
 450 +               pr_debug("SBResource_MMIO is disabled(0x%08x)\n", val);
 451 +
 452 +       /*
 453 +        * Lastly re-programming the watchdog MMIO address,
 454 +        * This method is a last resort...
 455 +        *
 456 +        * Before re-programming, to ensure that the watchdog timer
 457 +        * is disabled, disable the watchdog timer.
 458 +        */
 459 +       tco_timer_disable();
 460 +
 461 +       if (force_addr) {
 462 +               /* Force the use of base address */
 463 +               val = force_addr;
 464 +               /* The alignment of the MMIO address to a 8byte boundary */
 465 +               val &= ~0x7;
 466 +
 467 +               pr_info("Force the use of 0x%08x as MMIO address\n", val);
 468 +       } else {
 469 +               /*
 470 +                * Get empty slot into the resource tree for watchdog timer.
 471 +                */
 472 +               if (allocate_resource(&iomem_resource,
 473 +                                     &wdt_res,
 474 +                                     SP5100_WDT_MEM_MAP_SIZE,
 475 +                                     0xf0000000,
 476 +                                     0xfffffff8,
 477 +                                     0x8,
 478 +                                     NULL,
 479 +                                     NULL)) {
 480 +                       pr_err("MMIO allocation failed\n");
 481 +                       goto unreg_region;
 482 +               }
 483 +
 484 +               val = resbase_phys = wdt_res.start;
 485 +               pr_debug("Got 0x%08x from resource tree\n", val);
 486 +       }
 487 +
 488 +       /* Restore to the low three bits, if chipset is SB8x0(or later) */
 489 +       if (sp5100_tco_pci->revision >= 0x40) {
 490 +               u8 reserved_bit;
 491 +               reserved_bit = inb(base_addr) & 0x7;
 492 +               val |= (u32)reserved_bit;
 493 +       }
 494 +
 495 +       /* Re-programming the watchdog timer base address */
 496 +       outb(base_addr+0, index_reg);
 497 +       /* Low three bits of BASE are reserved */
 498 +       outb((val >>  0) & 0xf8, data_reg);
 499 +       outb(base_addr+1, index_reg);
 500 +       outb((val >>  8) & 0xff, data_reg);
 501 +       outb(base_addr+2, index_reg);
 502 +       outb((val >> 16) & 0xff, data_reg);
 503 +       outb(base_addr+3, index_reg);
 504 +       outb((val >> 24) & 0xff, data_reg);
 505 +
 506 +       /*
 507 +        * Clear unnecessary the low three bits,
 508 +        * if chipset is SB8x0(or later)
 509 +        */
 510 +       if (sp5100_tco_pci->revision >= 0x40)
 511 +               val &= ~0x7;
 512
 513         if (!request_mem_region_exclusive(val, SP5100_WDT_MEM_MAP_SIZE,
 514 -                                                               "SP5100 TCO")) {
 515 -               pr_err("mmio address 0x%04x already in use\n", val);
 516 -               goto unreg_region;
 517 +                                                                  dev_name)) {
 518 +               pr_err("MMIO address 0x%08x already in use\n", val);
 519 +               goto unreg_resource;
 520         }
 521 +
 522 +setup_wdt:
 523         tcobase_phys = val;
 524
 525         tcobase = ioremap(val, SP5100_WDT_MEM_MAP_SIZE);
 526 @@ -318,25 +534,12 @@ static unsigned char __devinit sp5100_tco_setupdevice(void)
 527                 goto unreg_mem_region;
 528         }
 529
 530 -       /* Enable watchdog decode bit */
 531 -       pci_read_config_dword(sp5100_tco_pci,
 532 -                             SP5100_PCI_WATCHDOG_MISC_REG,
 533 -                             &val);
 534 -
 535 -       val |= SP5100_PCI_WATCHDOG_DECODE_EN;
 536 -
 537 -       pci_write_config_dword(sp5100_tco_pci,
 538 -                              SP5100_PCI_WATCHDOG_MISC_REG,
 539 -                              val);
 540 +       pr_info("Using 0x%08x for watchdog MMIO address\n", val);
 541
 542 -       /* Enable Watchdog timer and set the resolution to 1 sec. */
 543 -       outb(SP5100_PM_WATCHDOG_CONTROL, SP5100_IO_PM_INDEX_REG);
 544 -       val = inb(SP5100_IO_PM_DATA_REG);
 545 -       val |= SP5100_PM_WATCHDOG_SECOND_RES;
 546 -       val &= ~SP5100_PM_WATCHDOG_DISABLE;
 547 -       outb(val, SP5100_IO_PM_DATA_REG);
 548 +       /* Setup the watchdog timer */
 549 +       tco_timer_enable();
 550
 551 -       /* Check that the watchdog action is set to reset the system. */
 552 +       /* Check that the watchdog action is set to reset the system */
 553         val = readl(SP5100_WDT_CONTROL(tcobase));
 554         val &= ~SP5100_PM_WATCHDOG_ACTION_RESET;
 555         writel(val, SP5100_WDT_CONTROL(tcobase));
 556 @@ -355,6 +558,9 @@ static unsigned char __devinit sp5100_tco_setupdevice(void)
 557
 558  unreg_mem_region:
 559         release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE);
 560 +unreg_resource:
 561 +       if (resbase_phys)
 562 +               release_resource(&wdt_res);
 563  unreg_region:
 564         release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE);
 565  exit:
 566 @@ -400,14 +606,17 @@ static int __devinit sp5100_tco_init(struct platform_device *dev)
 567
 568         clear_bit(0, &timer_alive);
 569
 570 -       pr_info("initialized (0x%p). heartbeat=%d sec (nowayout=%d)\n",
 571 -               tcobase, heartbeat, nowayout);
 572 +       pr_info("initialized (0x%p). heartbeat=%d sec (nowayout=%d, "
 573 +               "force_addr=0x%x)\n",
 574 +               tcobase, heartbeat, nowayout, force_addr);
 575
 576         return 0;
 577
 578  exit:
 579         iounmap(tcobase);
 580         release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE);
 581 +       if (resbase_phys)
 582 +               release_resource(&wdt_res);
 583         release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE);
 584         return ret;
 585  }
 586 @@ -422,6 +631,8 @@ static void __devexit sp5100_tco_cleanup(void)
 587         misc_deregister(&sp5100_tco_miscdev);
 588         iounmap(tcobase);
 589         release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE);
 590 +       if (resbase_phys)
 591 +               release_resource(&wdt_res);
 592         release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE);
 593  }
 594
 595 @@ -451,7 +662,7 @@ static int __init sp5100_tco_init_module(void)
 596  {
 597         int err;
 598
 599 -       pr_info("SP5100 TCO WatchDog Timer Driver v%s\n", TCO_VERSION);
 600 +       pr_info("SP5100/SB800 TCO WatchDog Timer Driver v%s\n", TCO_VERSION);
 601
 602         err = platform_driver_register(&sp5100_tco_driver);
 603         if (err)
 604 @@ -475,13 +686,13 @@ static void __exit sp5100_tco_cleanup_module(void)
 605  {
 606         platform_device_unregister(sp5100_tco_platform_device);
 607         platform_driver_unregister(&sp5100_tco_driver);
 608 -       pr_info("SP5100 TCO Watchdog Module Unloaded\n");
 609 +       pr_info("SP5100/SB800 TCO Watchdog Module Unloaded\n");
 610  }
 611
 612  module_init(sp5100_tco_init_module);
 613  module_exit(sp5100_tco_cleanup_module);
 614
 615  MODULE_AUTHOR("Priyanka Gupta");
 616 -MODULE_DESCRIPTION("TCO timer driver for SP5100 chipset");
 617 +MODULE_DESCRIPTION("TCO timer driver for SP5100/SB800 chipset");
 618  MODULE_LICENSE("GPL");
 619  MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
 620 diff --git a/drivers/watchdog/sp5100_tco.h b/drivers/watchdog/sp5100_tco.h
 621 index a5a16cc..71594a0 100644
 622 --- a/drivers/watchdog/sp5100_tco.h
 623 +++ b/drivers/watchdog/sp5100_tco.h
 624 @@ -9,33 +9,57 @@
 625  /*
 626   * Some address definitions for the Watchdog
 627   */
 628 -
 629  #define SP5100_WDT_MEM_MAP_SIZE                0x08
 630  #define SP5100_WDT_CONTROL(base)       ((base) + 0x00) /* Watchdog Control */
 631  #define SP5100_WDT_COUNT(base)         ((base) + 0x04) /* Watchdog Count */
 632
 633 -#define SP5100_WDT_START_STOP_BIT      1
 634 +#define SP5100_WDT_START_STOP_BIT      (1 << 0)
 635  #define SP5100_WDT_TRIGGER_BIT         (1 << 7)
 636
 637 -#define SP5100_PCI_WATCHDOG_MISC_REG   0x41
 638 -#define SP5100_PCI_WATCHDOG_DECODE_EN  (1 << 3)
 639 -
 640  #define SP5100_PM_IOPORTS_SIZE         0x02
 641
 642 -/* These two IO registers are hardcoded and there doesn't seem to be a way to
 643 +/*
 644 + * These two IO registers are hardcoded and there doesn't seem to be a way to
 645   * read them from a register.
 646   */
 647 +
 648 +/*  For SP5100/SB7x0 chipset */
 649  #define SP5100_IO_PM_INDEX_REG         0xCD6
 650  #define SP5100_IO_PM_DATA_REG          0xCD7
 651
 652 +#define SP5100_SB_RESOURCE_MMIO_BASE   0x9C
 653 +
 654  #define SP5100_PM_WATCHDOG_CONTROL     0x69
 655 -#define SP5100_PM_WATCHDOG_BASE0       0x6C
 656 -#define SP5100_PM_WATCHDOG_BASE1       0x6D
 657 -#define SP5100_PM_WATCHDOG_BASE2       0x6E
 658 -#define SP5100_PM_WATCHDOG_BASE3       0x6F
 659 +#define SP5100_PM_WATCHDOG_BASE                0x6C
 660
 661  #define SP5100_PM_WATCHDOG_FIRED       (1 << 1)
 662  #define SP5100_PM_WATCHDOG_ACTION_RESET        (1 << 2)
 663
 664 -#define SP5100_PM_WATCHDOG_DISABLE     1
 665 +#define SP5100_PCI_WATCHDOG_MISC_REG   0x41
 666 +#define SP5100_PCI_WATCHDOG_DECODE_EN  (1 << 3)
 667 +
 668 +#define SP5100_PM_WATCHDOG_DISABLE     (1 << 0)
 669  #define SP5100_PM_WATCHDOG_SECOND_RES  (3 << 1)
 670 +
 671 +#define SP5100_DEVNAME                 "SP5100 TCO"
 672 +
 673 +
 674 +/*  For SB8x0(or later) chipset */
 675 +#define SB800_IO_PM_INDEX_REG          0xCD6
 676 +#define SB800_IO_PM_DATA_REG           0xCD7
 677 +
 678 +#define SB800_PM_ACPI_MMIO_EN          0x24
 679 +#define SB800_PM_WATCHDOG_CONTROL      0x48
 680 +#define SB800_PM_WATCHDOG_BASE         0x48
 681 +#define SB800_PM_WATCHDOG_CONFIG       0x4C
 682 +
 683 +#define SB800_PCI_WATCHDOG_DECODE_EN   (1 << 0)
 684 +#define SB800_PM_WATCHDOG_DISABLE      (1 << 2)
 685 +#define SB800_PM_WATCHDOG_SECOND_RES   (3 << 0)
 686 +#define SB800_ACPI_MMIO_DECODE_EN      (1 << 0)
 687 +#define SB800_ACPI_MMIO_SEL            (1 << 2)
 688 +
 689 +
 690 +#define SB800_PM_WDT_MMIO_OFFSET       0xB00
 691 +
 692 +#define SB800_DEVNAME                  "SB800 TCO"