1 Use specific machine level instructions for mb() for new
2 processors (P3,P4,Athlon).
3 Author: Zwane Mwaikambo <zwane@linux.realnet.co.sz>
5 --- linux-2.5.19/arch/i386/config.in.orig Mon Jun 3 10:33:18 2002
6 +++ linux-2.5.19/arch/i386/config.in Mon Jun 10 08:12:02 2002
8 define_bool CONFIG_X86_PGE y
9 define_bool CONFIG_X86_USE_PPRO_CHECKSUM y
10 define_bool CONFIG_X86_F00F_WORKS_OK y
11 + define_bool CONFIG_X86_SFENCE y
13 if [ "$CONFIG_MPENTIUM4" = "y" ]; then
14 define_int CONFIG_X86_L1_CACHE_SHIFT 7
16 define_bool CONFIG_X86_PGE y
17 define_bool CONFIG_X86_USE_PPRO_CHECKSUM y
18 define_bool CONFIG_X86_F00F_WORKS_OK y
19 + define_bool CONFIG_X86_SFENCE y
20 + define_bool CONFIG_X86_LFENCE y
21 + define_bool CONFIG_X86_MFENCE y
23 if [ "$CONFIG_MK6" = "y" ]; then
24 define_int CONFIG_X86_L1_CACHE_SHIFT 5
26 define_bool CONFIG_X86_PGE y
27 define_bool CONFIG_X86_USE_PPRO_CHECKSUM y
28 define_bool CONFIG_X86_F00F_WORKS_OK y
29 + define_bool CONFIG_X86_SFENCE y
31 if [ "$CONFIG_MELAN" = "y" ]; then
32 define_int CONFIG_X86_L1_CACHE_SHIFT 4
33 --- linux-2.5.19/include/asm-i386/system.h.orig Mon Jun 10 08:10:55 2002
34 +++ linux-2.5.19/include/asm-i386/system.h Mon Jun 10 08:11:04 2002
37 * Some non intel clones support out of order store. wmb() ceases to be a
40 + * Pentium III introduced the SFENCE instruction for serialising all store
41 + * operations, Pentium IV further introduced LFENCE and MFENCE for load and
42 + * memory barriers respecively.
46 +#ifdef CONFIG_X86_MFENCE
47 +#define mb() __asm__ __volatile__ ("mfence": : :"memory")
49 #define mb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory")
52 +#ifdef CONFIG_X86_LFENCE
53 +#define rmb() __asm__ __volatile__ ("lfence": : :"memory")
58 +#ifdef CONFIG_X86_SFENCE
59 +#define wmb() __asm__ __volatile__ ("sfence": : :"memory")
61 #ifdef CONFIG_X86_OOSTORE
62 #define wmb() __asm__ __volatile__ ("lock; addl $0,0(%%esp)": : :"memory")
64 #define wmb() __asm__ __volatile__ ("": : :"memory")
66 +#endif /* CONFIG_X86_SFENCE */