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37 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
38 To: Bjorn Helgaas <bhelgaas@google.com>,
39 Kalle Valo <kvalo@codeaurora.org>,
40 =?UTF-8?q?Toke=20H=C3=B8iland-J=C3=B8rgensen?= <toke@redhat.com>,
41 =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>,
42 =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= <kw@linux.com>
43 Cc: vtolkm@gmail.com, Rob Herring <robh@kernel.org>,
44 Ilias Apalodimas <ilias.apalodimas@linaro.org>,
45 Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
46 linux-pci@vger.kernel.org, ath10k@lists.infradead.org,
47 linux-wireless@vger.kernel.org, linux-kernel@vger.kernel.org
48 Subject: [PATCH v3] PCI: Disallow retraining link for Atheros chips on non-Gen1 PCIe bridges
49 Date: Wed, 5 May 2021 18:33:57 +0200
50 Message-Id: <20210505163357.16012-1-pali@kernel.org>
51 X-Mailer: git-send-email 2.20.1
52 In-Reply-To: <20210326124326.21163-1-pali@kernel.org>
53 References: <20210326124326.21163-1-pali@kernel.org>
55 Content-Type: text/plain; charset=UTF-8
56 Content-Transfer-Encoding: 8bit
58 List-ID: <linux-pci.vger.kernel.org>
59 X-Mailing-List: linux-pci@vger.kernel.org
61 Atheros AR9xxx and QCA9xxx chips have behaviour issues not only after a
62 bus reset, but also after doing retrain link, if PCIe bridge is not in
63 GEN1 mode (at 2.5 GT/s speed):
65 - QCA9880 and QCA9890 chips throw a Link Down event and completely
66 disappear from the bus and their config space is not accessible
69 - QCA9377 chip throws a Link Down event followed by Link Up event, the
70 config space is accessible and PCI device ID is correct. But trying to
71 access chip's I/O space causes Uncorrected (Non-Fatal) AER error,
72 followed by Synchronous external abort 96000210 and Segmentation fault
73 of insmod while loading ath10k_pci.ko module.
75 - AR9390 chip throws a Link Down event followed by Link Up event, config
76 space is accessible, but contains nonsense values. PCI device ID is
77 0xABCD which indicates HW bug that chip itself was not able to read
78 values from internal EEPROM/OTP.
80 - AR9287 chip throws also Link Down and Link Up events, also has
81 accessible config space containing correct values. But ath9k driver
82 fails to initialize card from this state as it is unable to access HW
83 registers. This also indicates that the chip iself is not able to read
84 values from internal EEPROM/OTP.
86 These issues related to PCI device ID 0xABCD and to reading internal
87 EEPROM/OTP were previously discussed at ath9k-devel mailing list in
90 https://www.mail-archive.com/ath9k-devel@lists.ath9k.org/msg07529.html
92 After experiments we've come up with a solution: it seems that Retrain
93 link can be called only when using GEN1 PCIe bridge or when PCIe bridge
94 link speed is forced to 2.5 GT/s. Applying this workaround fixes all
97 This issue was reproduced with more cards:
98 - Compex WLE900VX (QCA9880 based / device ID 0x003c)
99 - QCNFA435 (QCA9377 based / device ID 0x0042)
100 - Compex WLE200NX (AR9287 based / device ID 0x002e)
101 - "noname" card (QCA9890 based / device ID 0x003c)
102 - Wistron NKR-DNXAH1 (AR9390 based / device ID 0x0030)
103 on Armada 385 with pci-mvebu.c driver and also on Armada 3720 with
104 pci-aardvark.c driver.
106 To workaround this issue, this change introduces a new PCI quirk called
107 PCI_DEV_FLAGS_NO_RETRAIN_LINK_WHEN_NOT_GEN1, which is enabled for all
108 Atheros chips with PCI_DEV_FLAGS_NO_BUS_RESET quirk, and also for Atheros
111 When this quirk is set, kernel disallows triggering PCI_EXP_LNKCTL_RL
112 bit in config space of PCIe Bridge in the case when PCIe Bridge is
113 capable of higher speed than 2.5 GT/s and this higher speed is already
114 allowed. When PCIe Bridge has accessible LNKCTL2 register, we try to
115 force target link speed to 2.5 GT/s. After this change it is possible
116 to trigger PCI_EXP_LNKCTL_RL bit without issues.
118 Currently only PCIe ASPM kernel code triggers this PCI_EXP_LNKCTL_RL bit,
119 so quirk check is added only into pcie/aspm.c file.
121 Signed-off-by: Pali Rohár <pali@kernel.org>
122 Reported-by: Toke Høiland-Jørgensen <toke@redhat.com>
123 Tested-by: Toke Høiland-Jørgensen <toke@redhat.com>
124 Tested-by: Marek Behún <kabel@kernel.org>
125 BugLink: https://lore.kernel.org/linux-pci/87h7l8axqp.fsf@toke.dk/
126 BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=84821
127 BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=192441
128 BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=209833
129 Cc: stable@vger.kernel.org # c80851f6ce63a ("PCI: Add PCI_EXP_LNKCTL2_TLS* macros")
133 * Move whole quirk code into pcie_downgrade_link_to_gen1() function
134 * Reformat to 80 chars per line where possible
135 * Add quirk also for cards with AR9287 chip (PCI ID 0x002e)
136 * Extend commit message description and add information about 0xABCD
139 * Add quirk also for Atheros QCA9377 chip
141 drivers/pci/pcie/aspm.c | 44 +++++++++++++++++++++++++++++++++++++++++
142 drivers/pci/quirks.c | 39 ++++++++++++++++++++++++++++--------
143 include/linux/pci.h | 2 ++
144 3 files changed, 77 insertions(+), 8 deletions(-)
146 diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
147 index ac0557a305af..729b0389562b 100644
148 --- a/drivers/pci/pcie/aspm.c
149 +++ b/drivers/pci/pcie/aspm.c
150 @@ -192,12 +192,56 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
151 link->clkpm_disable = blacklist ? 1 : 0;
154 +static int pcie_downgrade_link_to_gen1(struct pci_dev *parent)
160 + /* Check if link is capable of higher speed than 2.5 GT/s */
161 + pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, ®32);
162 + if ((reg32 & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
165 + /* Check if link speed can be downgraded to 2.5 GT/s */
166 + pcie_capability_read_dword(parent, PCI_EXP_LNKCAP2, ®32);
167 + if (!(reg32 & PCI_EXP_LNKCAP2_SLS_2_5GB)) {
168 + pci_err(parent, "ASPM: Bridge does not support changing Link Speed to 2.5 GT/s\n");
169 + return -EOPNOTSUPP;
172 + /* Force link speed to 2.5 GT/s */
173 + ret = pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL2,
174 + PCI_EXP_LNKCTL2_TLS,
175 + PCI_EXP_LNKCTL2_TLS_2_5GT);
177 + /* Verify that new value was really set */
178 + pcie_capability_read_word(parent, PCI_EXP_LNKCTL2, ®16);
179 + if ((reg16 & PCI_EXP_LNKCTL2_TLS) != PCI_EXP_LNKCTL2_TLS_2_5GT)
184 + pci_err(parent, "ASPM: Changing Target Link Speed to 2.5 GT/s failed: %d\n", ret);
188 + pci_info(parent, "ASPM: Target Link Speed changed to 2.5 GT/s due to quirk\n");
192 static bool pcie_retrain_link(struct pcie_link_state *link)
194 struct pci_dev *parent = link->pdev;
195 unsigned long end_jiffies;
198 + if ((link->downstream->dev_flags & PCI_DEV_FLAGS_NO_RETRAIN_LINK_WHEN_NOT_GEN1) &&
199 + pcie_downgrade_link_to_gen1(parent)) {
200 + pci_err(parent, "ASPM: Retrain Link at higher speed is disallowed by quirk\n");
204 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
205 reg16 |= PCI_EXP_LNKCTL_RL;
206 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
207 diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
208 index 653660e3ba9e..4999ad9d08b8 100644
209 --- a/drivers/pci/quirks.c
210 +++ b/drivers/pci/quirks.c
211 @@ -3553,31 +3553,55 @@ static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
212 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
215 +static void quirk_no_bus_reset_and_no_retrain_link(struct pci_dev *dev)
217 + dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET |
218 + PCI_DEV_FLAGS_NO_RETRAIN_LINK_WHEN_NOT_GEN1;
222 * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be
223 * prevented for those affected devices.
225 static void quirk_nvidia_no_bus_reset(struct pci_dev *dev)
227 if ((dev->device & 0xffc0) == 0x2340)
228 quirk_no_bus_reset(dev);
230 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
231 quirk_nvidia_no_bus_reset);
234 - * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
235 + * Atheros AR9xxx and QCA9xxx chips do not behave after a bus reset and also
236 + * after retrain link when PCIe bridge is not in GEN1 mode at 2.5 GT/s speed.
237 * The device will throw a Link Down error on AER-capable systems and
238 * regardless of AER, config space of the device is never accessible again
239 * and typically causes the system to hang or reset when access is attempted.
240 + * Or if config space is accessible again then it contains only dummy values
241 + * like fixed PCI device ID 0xABCD or values not initialized at all.
242 + * Retrain link can be called only when using GEN1 PCIe bridge or when
243 + * PCIe bridge has forced link speed to 2.5 GT/s via PCI_EXP_LNKCTL2 register.
244 + * To reset these cards it is required to do PCIe Warm Reset via PERST# pin.
245 * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/
246 + * https://lore.kernel.org/r/87h7l8axqp.fsf@toke.dk/
247 + * https://www.mail-archive.com/ath9k-devel@lists.ath9k.org/msg07529.html
249 -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
250 -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
251 -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
252 -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
253 -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
254 -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset);
255 +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x002e,
256 + quirk_no_bus_reset_and_no_retrain_link);
257 +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030,
258 + quirk_no_bus_reset_and_no_retrain_link);
259 +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032,
260 + quirk_no_bus_reset_and_no_retrain_link);
261 +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033,
262 + quirk_no_bus_reset_and_no_retrain_link);
263 +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034,
264 + quirk_no_bus_reset_and_no_retrain_link);
265 +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c,
266 + quirk_no_bus_reset_and_no_retrain_link);
267 +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e,
268 + quirk_no_bus_reset_and_no_retrain_link);
269 +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0042,
270 + quirk_no_bus_reset_and_no_retrain_link);
273 * Root port on some Cavium CN8xxx chips do not successfully complete a bus
274 diff --git a/include/linux/pci.h b/include/linux/pci.h
275 index 86c799c97b77..fdbf7254e4ab 100644
276 --- a/include/linux/pci.h
277 +++ b/include/linux/pci.h
278 @@ -227,6 +227,8 @@ enum pci_dev_flags {
279 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
280 /* Device does honor MSI masking despite saying otherwise */
281 PCI_DEV_FLAGS_HAS_MSI_MASKING = (__force pci_dev_flags_t) (1 << 12),
282 + /* Don't Retrain Link for device when bridge is not in GEN1 mode */
283 + PCI_DEV_FLAGS_NO_RETRAIN_LINK_WHEN_NOT_GEN1 = (__force pci_dev_flags_t) (1 << 12),
286 enum pci_irq_reroute_variant {