2.6.x-TGA-fbdev-lkml.patch

   1 diff -urN -X /home/jsimmons/dontdiff linus-2.6/drivers/video/logo/Kconfig fbdev-2.6/drivers/video/logo/Kconfig
   2 --- linus-2.6/drivers/video/logo/Kconfig        2004-02-18 20:59:12.000000000 -0800
   3 +++ fbdev-2.6/drivers/video/logo/Kconfig        2004-02-18 20:10:03.000000000 -0800
   4 @@ -25,7 +25,7 @@
   5
   6  config LOGO_DEC_CLUT224
   7         bool "224-color Digital Equipment Corporation Linux logo"
   8 -       depends on LOGO && DECSTATION
   9 +       depends on LOGO && (DECSTATION || ALPHA)
  10         default y
  11
  12  config LOGO_MAC_CLUT224
  13 diff -urN -X /home/jsimmons/dontdiff linus-2.6/drivers/video/logo/logo.c fbdev-2.6/drivers/video/logo/logo.c
  14 --- linus-2.6/drivers/video/logo/logo.c 2004-02-18 20:59:12.000000000 -0800
  15 +++ fbdev-2.6/drivers/video/logo/logo.c 2004-02-18 20:10:04.000000000 -0800
  16 @@ -65,9 +65,14 @@
  17                 logo = &logo_linux_clut224;
  18  #endif
  19  #ifdef CONFIG_LOGO_DEC_CLUT224
  20 +# if defined(CONFIG_MIPS) || defined(CONFIG_MIPS64)
  21                 /* DEC Linux logo on MIPS/MIPS64 */
  22                 if (mips_machgroup == MACH_GROUP_DEC)
  23                         logo = &logo_dec_clut224;
  24 +# else
  25 +               /* Assume DEC Linux logo on ALPHA */
  26 +               logo = &logo_dec_clut224;
  27 +# endif
  28  #endif
  29  #ifdef CONFIG_LOGO_MAC_CLUT224
  30                 /* Macintosh Linux logo on m68k */
  31 diff -urN -X /home/jsimmons/dontdiff linus-2.6/drivers/video/tgafb.c fbdev-2.6/drivers/video/tgafb.c
  32 --- linus-2.6/drivers/video/tgafb.c     2004-02-18 20:59:10.000000000 -0800
  33 +++ fbdev-2.6/drivers/video/tgafb.c     2004-02-18 20:53:34.000000000 -0800
  34 @@ -24,7 +24,7 @@
  35  #include <linux/fb.h>
  36  #include <linux/pci.h>
  37  #include <asm/io.h>
  38 -#include <video/tgafb.h>
  39 +#include <video/tga.h>
  40  #include <linux/selection.h>
  41
  42  /*
  43 @@ -41,6 +41,7 @@
  44  static void tgafb_imageblit(struct fb_info *, const struct fb_image *);
  45  static void tgafb_fillrect(struct fb_info *, const struct fb_fillrect *);
  46  static void tgafb_copyarea(struct fb_info *, const struct fb_copyarea *);
  47 +static int tgafb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
  48
  49  static int tgafb_pci_register(struct pci_dev *, const struct pci_device_id *);
  50  #ifdef MODULE
  51 @@ -49,7 +50,6 @@
  52
  53  static const char *mode_option = "640x480@60";
  54
  55 -
  56  /*
  57   *  Frame buffer operations
  58   */
  59 @@ -60,6 +60,7 @@
  60         .fb_set_par             = tgafb_set_par,
  61         .fb_setcolreg           = tgafb_setcolreg,
  62         .fb_blank               = tgafb_blank,
  63 +       .fb_pan_display         = tgafb_pan_display,
  64         .fb_fillrect            = tgafb_fillrect,
  65         .fb_copyarea            = tgafb_copyarea,
  66         .fb_imageblit           = tgafb_imageblit,
  67 @@ -127,10 +128,10 @@
  68  tgafb_set_par(struct fb_info *info)
  69  {
  70         static unsigned int const deep_presets[4] = {
  71 -               0x00014000,
  72 -               0x0001440d,
  73 +               0x00004000,
  74 +               0x0000440d,
  75                 0xffffffff,
  76 -               0x0001441d
  77 +               0x0000441d
  78         };
  79         static unsigned int const rasterop_presets[4] = {
  80                 0x00000003,
  81 @@ -154,7 +155,7 @@
  82         struct tga_par *par = (struct tga_par *) info->par;
  83         u32 htimings, vtimings, pll_freq;
  84         u8 tga_type;
  85 -       int i, j;
  86 +       int i;
  87
  88         /* Encode video timings.  */
  89         htimings = (((info->var.xres/4) & TGA_HORIZ_ACT_LSB)
  90 @@ -192,7 +193,8 @@
  91         while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
  92                 continue;
  93         mb();
  94 -       TGA_WRITE_REG(par, deep_presets[tga_type], TGA_DEEP_REG);
  95 +       TGA_WRITE_REG(par, deep_presets[tga_type] |
  96 +                       (par->sync_on_green ? 0x0 : 0x00010000), TGA_DEEP_REG);
  97         while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
  98                 continue;
  99         mb();
 100 @@ -225,37 +227,13 @@
 101                 BT485_WRITE(par, 0x20, BT485_CMD_2); /* cursor off, for now */
 102                 BT485_WRITE(par, 0xff, BT485_PIXEL_MASK);
 103
 104 -               /* Fill palette registers.  */
 105 -               BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE);
 106 -               TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
 107 -
 108 -               for (i = 0; i < 16; i++) {
 109 -                       j = color_table[i];
 110 -                       TGA_WRITE_REG(par, default_red[j]|(BT485_DATA_PAL<<8),
 111 -                                     TGA_RAMDAC_REG);
 112 -                       TGA_WRITE_REG(par, default_grn[j]|(BT485_DATA_PAL<<8),
 113 -                                     TGA_RAMDAC_REG);
 114 -                       TGA_WRITE_REG(par, default_blu[j]|(BT485_DATA_PAL<<8),
 115 -                                     TGA_RAMDAC_REG);
 116 -               }
 117 -               for (i = 0; i < 240*3; i += 4) {
 118 -                       TGA_WRITE_REG(par, 0x55|(BT485_DATA_PAL<<8),
 119 -                                     TGA_RAMDAC_REG);
 120 -                       TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
 121 -                                     TGA_RAMDAC_REG);
 122 -                       TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
 123 -                                     TGA_RAMDAC_REG);
 124 -                       TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
 125 -                                     TGA_RAMDAC_REG);
 126 -               }
 127 -
 128         } else { /* 24-plane or 24plusZ */
 129
 130                 /* Init BT463 registers.  */
 131                 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_0, 0x40);
 132                 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_1, 0x08);
 133                 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_2,
 134 -                           (par->sync_on_green ? 0x80 : 0x40));
 135 +                           (par->sync_on_green ? 0xc0 : 0x40));
 136
 137                 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_0, 0xff);
 138                 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_1, 0xff);
 139 @@ -267,30 +245,6 @@
 140                 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00);
 141                 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00);
 142
 143 -               /* Fill the palette.  */
 144 -               BT463_LOAD_ADDR(par, 0x0000);
 145 -               TGA_WRITE_REG(par, BT463_PALETTE<<2, TGA_RAMDAC_REG);
 146 -
 147 -               for (i = 0; i < 16; i++) {
 148 -                       j = color_table[i];
 149 -                       TGA_WRITE_REG(par, default_red[j]|(BT463_PALETTE<<10),
 150 -                                     TGA_RAMDAC_REG);
 151 -                       TGA_WRITE_REG(par, default_grn[j]|(BT463_PALETTE<<10),
 152 -                                     TGA_RAMDAC_REG);
 153 -                       TGA_WRITE_REG(par, default_blu[j]|(BT463_PALETTE<<10),
 154 -                                     TGA_RAMDAC_REG);
 155 -               }
 156 -               for (i = 0; i < 512*3; i += 4) {
 157 -                       TGA_WRITE_REG(par, 0x55|(BT463_PALETTE<<10),
 158 -                                     TGA_RAMDAC_REG);
 159 -                       TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
 160 -                                     TGA_RAMDAC_REG);
 161 -                       TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
 162 -                                     TGA_RAMDAC_REG);
 163 -                       TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
 164 -                                     TGA_RAMDAC_REG);
 165 -               }
 166 -
 167                 /* Fill window type table after start of vertical retrace.  */
 168                 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
 169                         continue;
 170 @@ -314,6 +268,9 @@
 171
 172         }
 173
 174 +       /* Init the palette. */
 175 +       fb_set_cmap(fb_default_cmap(16), 1, info);
 176 +
 177         /* Finally, enable video scan (and pray for the monitor... :-) */
 178         TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG);
 179
 180 @@ -509,16 +466,8 @@
 181   *  Acceleration.
 182   */
 183
 184 -/**
 185 - *      tgafb_imageblit - REQUIRED function. Can use generic routines if
 186 - *                        non acclerated hardware and packed pixel based.
 187 - *                        Copies a image from system memory to the screen.
 188 - *
 189 - *      @info: frame buffer structure that represents a single frame buffer
 190 - *      @image: structure defining the image.
 191 - */
 192  static void
 193 -tgafb_imageblit(struct fb_info *info, const struct fb_image *image)
 194 +tgafb_mono_imageblit(struct fb_info *info, const struct fb_image *image)
 195  {
 196         static unsigned char const bitrev[256] = {
 197                 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
 198 @@ -562,6 +511,17 @@
 199         const unsigned char *data;
 200         void *regs_base, *fb_base;
 201
 202 +       is8bpp = info->var.bits_per_pixel == 8;
 203 +
 204 +       /* For copies that aren't pixel expansion, there's little we
 205 +          can do better than the generic code.  */
 206 +       /* ??? There is a DMA write mode; I wonder if that could be
 207 +          made to pull the data from the image buffer...  */
 208 +       if (image->depth > 1) {
 209 +               cfb_imageblit(info, image);
 210 +               return;
 211 +       }
 212 +
 213         dx = image->dx;
 214         dy = image->dy;
 215         width = image->width;
 216 @@ -579,18 +539,8 @@
 217         if (dy + height > vyres)
 218                 height = vyres - dy;
 219
 220 -       /* For copies that aren't pixel expansion, there's little we
 221 -          can do better than the generic code.  */
 222 -       /* ??? There is a DMA write mode; I wonder if that could be
 223 -          made to pull the data from the image buffer...  */
 224 -       if (image->depth > 1) {
 225 -               cfb_imageblit(info, image);
 226 -               return;
 227 -       }
 228 -
 229         regs_base = par->tga_regs_base;
 230         fb_base = par->tga_fb_base;
 231 -       is8bpp = info->var.bits_per_pixel == 8;
 232
 233         /* Expand the color values to fill 32-bits.  */
 234         /* ??? Would be nice to notice colour changes elsewhere, so
 235 @@ -768,6 +718,86 @@
 236                      regs_base + TGA_MODE_REG);
 237  }
 238
 239 +static void
 240 +tgafb_clut_imageblit(struct fb_info *info, const struct fb_image *image)
 241 +{
 242 +       struct tga_par *par = (struct tga_par *) info->par;
 243 +       u32 color, dx, dy, width, height, vxres, vyres;
 244 +       u32 *palette = ((u32 *)info->pseudo_palette);
 245 +       unsigned long pos, line_length;
 246 +       unsigned long i, j;
 247 +       const unsigned char *data;
 248 +       void *regs_base, *fb_base;
 249 +
 250 +       dx = image->dx;
 251 +       dy = image->dy;
 252 +       width = image->width;
 253 +       height = image->height;
 254 +       vxres = info->var.xres_virtual;
 255 +       vyres = info->var.yres_virtual;
 256 +       line_length = info->fix.line_length;
 257 +
 258 +       /* Crop the image to the screen.  */
 259 +       if (dx > vxres || dy > vyres)
 260 +               return;
 261 +       if (dx + width > vxres)
 262 +               width = vxres - dx;
 263 +       if (dy + height > vyres)
 264 +               height = vyres - dy;
 265 +
 266 +       regs_base = par->tga_regs_base;
 267 +       fb_base = par->tga_fb_base;
 268 +
 269 +       pos = dy * line_length + (dx * 4);
 270 +       data = image->data;
 271 +
 272 +       /* Now copy the image, color_expanding via the palette. */
 273 +       for (i = 0; i < height; i++) {
 274 +               for (j = 0; j < width; j++) {
 275 +                       color = palette[*data++];
 276 +                       __raw_writel(color, fb_base + pos + j*4);
 277 +               }
 278 +               pos += line_length;
 279 +       }
 280 +}
 281 +
 282 +/**
 283 + *      tgafb_imageblit - REQUIRED function. Can use generic routines if
 284 + *                        non acclerated hardware and packed pixel based.
 285 + *                        Copies a image from system memory to the screen.
 286 + *
 287 + *      @info: frame buffer structure that represents a single frame buffer
 288 + *      @image: structure defining the image.
 289 + */
 290 +static void
 291 +tgafb_imageblit(struct fb_info *info, const struct fb_image *image)
 292 +{
 293 +       unsigned int is8bpp = info->var.bits_per_pixel == 8;
 294 +
 295 +       /* If a mono image, regardless of FB depth, go do it. */
 296 +       if (image->depth == 1) {
 297 +               tgafb_mono_imageblit(info, image);
 298 +               return;
 299 +       }
 300 +
 301 +       /* For copies that aren't pixel expansion, there's little we
 302 +          can do better than the generic code.  */
 303 +       /* ??? There is a DMA write mode; I wonder if that could be
 304 +          made to pull the data from the image buffer...  */
 305 +       if (image->depth == info->var.bits_per_pixel) {
 306 +               cfb_imageblit(info, image);
 307 +               return;
 308 +       }
 309 +
 310 +       /* If 24-plane FB and the image is 8-plane with CLUT, we can do it. */
 311 +       if (!is8bpp && image->depth == 8) {
 312 +               tgafb_clut_imageblit(info, image);
 313 +               return;
 314 +       }
 315 +
 316 +       /* Silently return... */
 317 +}
 318 +
 319  /**
 320   *      tgafb_fillrect - REQUIRED function. Can use generic routines if
 321   *                       non acclerated hardware and packed pixel based.
 322 @@ -1360,6 +1390,31 @@
 323         info->fix.ywrapstep = 0;
 324
 325         info->fix.accel = FB_ACCEL_DEC_TGA;
 326 +
 327 +       /*
 328 +        * These are needed by fb_set_logo_truepalette(), so we
 329 +        * set them here for 24-plane cards.
 330 +        */
 331 +       if (tga_type != TGA_TYPE_8PLANE) {
 332 +               info->var.red.length = 8;
 333 +               info->var.green.length = 8;
 334 +               info->var.blue.length = 8;
 335 +               info->var.red.offset = 16;
 336 +               info->var.green.offset = 8;
 337 +               info->var.blue.offset = 0;
 338 +       }
 339 +}
 340 +
 341 +static int tgafb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
 342 +{
 343 +       /* We just use this to catch switches out of
 344 +        * graphics mode.
 345 +        */
 346 +       tgafb_set_par(info); /* A bit of overkill for BASE_ADDR reset. */
 347 +
 348 +       if (var->xoffset || var->yoffset || var->vmode)
 349 +               return -EINVAL;
 350 +       return 0;
 351  }
 352
 353  static __devinit int
 354 @@ -1371,15 +1426,10 @@
 355                 0xffffffff,
 356                 TGA_24PLUSZ_FB_OFFSET
 357         };
 358 -
 359 -       struct all_info {
 360 -               struct fb_info info;
 361 -               struct tga_par par;
 362 -               u32 pseudo_palette[16];
 363 -       } *all;
 364 -
 365 -       void *mem_base;
 366         unsigned long bar0_start, bar0_len;
 367 +       struct fb_info *info;
 368 +       struct tga_par *par;
 369 +       void *mem_base;
 370         u8 tga_type;
 371         int ret;
 372
 373 @@ -1390,13 +1440,12 @@
 374         }
 375
 376         /* Allocate the fb and par structures.  */
 377 -       all = kmalloc(sizeof(*all), GFP_KERNEL);
 378 -       if (!all) {
 379 +       info = framebuffer_alloc(sizeof(struct tga_par), &pdev->dev);
 380 +       if (!info) {
 381                 printk(KERN_ERR "tgafb: Cannot allocate memory\n");
 382                 return -ENOMEM;
 383         }
 384 -       memset(all, 0, sizeof(*all));
 385 -       pci_set_drvdata(pdev, all);
 386 +       pci_set_drvdata(pdev, info);
 387
 388         /* Request the mem regions.  */
 389         bar0_start = pci_resource_start(pdev, 0);
 390 @@ -1416,24 +1465,22 @@
 391
 392         /* Grab info about the card.  */
 393         tga_type = (readl(mem_base) >> 12) & 0x0f;
 394 -       all->par.pdev = pdev;
 395 -       all->par.tga_mem_base = mem_base;
 396 -       all->par.tga_fb_base = mem_base + fb_offset_presets[tga_type];
 397 -       all->par.tga_regs_base = mem_base + TGA_REGS_OFFSET;
 398 -       all->par.tga_type = tga_type;
 399 -       pci_read_config_byte(pdev, PCI_REVISION_ID, &all->par.tga_chip_rev);
 400 +       par = info->par;
 401 +       par->tga_mem_base = mem_base;
 402 +       par->tga_fb_base = mem_base + fb_offset_presets[tga_type];
 403 +       par->tga_regs_base = mem_base + TGA_REGS_OFFSET;
 404 +       par->tga_type = tga_type;
 405 +       pci_read_config_byte(pdev, PCI_REVISION_ID, par->tga_chip_rev);
 406
 407         /* Setup framebuffer.  */
 408 -       all->info.flags = FBINFO_FLAG_DEFAULT;
 409 -       all->info.fbops = &tgafb_ops;
 410 -       all->info.screen_base = (char *) all->par.tga_fb_base;
 411 -       all->info.currcon = -1;
 412 -       all->info.par = &all->par;
 413 -       all->info.pseudo_palette = all->pseudo_palette;
 414 +       info->flags = FBINFO_FLAG_DEFAULT;
 415 +       info->fbops = &tgafb_ops;
 416 +       info->screen_base = (char *) par->tga_fb_base;
 417 +       info->pseudo_palette = par->pseudo_palette;
 418
 419         /* This should give a reasonable default video mode.  */
 420
 421 -       ret = fb_find_mode(&all->info.var, &all->info, mode_option,
 422 +       ret = fb_find_mode(&info->var, info, mode_option,
 423                            NULL, 0, NULL,
 424                            tga_type == TGA_TYPE_8PLANE ? 8 : 32);
 425         if (ret == 0 || ret == 4) {
 426 @@ -1442,35 +1489,34 @@
 427                 goto err1;
 428         }
 429
 430 -       if (fb_alloc_cmap(&all->info.cmap, 256, 0)) {
 431 +       if (fb_alloc_cmap(&info->cmap, 256, 0)) {
 432                 printk(KERN_ERR "tgafb: Could not allocate color map\n");
 433                 ret = -ENOMEM;
 434                 goto err1;
 435         }
 436
 437 -       tgafb_set_par(&all->info);
 438 -       tgafb_init_fix(&all->info);
 439 +       tgafb_init_fix(info);
 440
 441 -       if (register_framebuffer(&all->info) < 0) {
 442 +       if (register_framebuffer(info) < 0) {
 443                 printk(KERN_ERR "tgafb: Could not register framebuffer\n");
 444                 ret = -EINVAL;
 445                 goto err1;
 446         }
 447
 448         printk(KERN_INFO "tgafb: DC21030 [TGA] detected, rev=0x%02x\n",
 449 -              all->par.tga_chip_rev);
 450 +              par->tga_chip_rev);
 451         printk(KERN_INFO "tgafb: at PCI bus %d, device %d, function %d\n",
 452                pdev->bus->number, PCI_SLOT(pdev->devfn),
 453                PCI_FUNC(pdev->devfn));
 454         printk(KERN_INFO "fb%d: %s frame buffer device at 0x%lx\n",
 455 -              all->info.node, all->info.fix.id, bar0_start);
 456 +              info->node, info->fix.id, bar0_start);
 457
 458         return 0;
 459
 460   err1:
 461         release_mem_region(bar0_start, bar0_len);
 462   err0:
 463 -       kfree(all);
 464 +       framebuffer_release(info);
 465         return ret;
 466  }
 467
 468 @@ -1493,7 +1539,7 @@
 469         iounmap(par->tga_mem_base);
 470         release_mem_region(pci_resource_start(pdev, 0),
 471                            pci_resource_len(pdev, 0));
 472 -       kfree(info);
 473 +       framebuffer_release(info);
 474  }
 475
 476  static void __exit
 477 diff -urN -X /home/jsimmons/dontdiff linus-2.6/include/video/tga.h fbdev-2.6/include/video/tga.h
 478 --- linus-2.6/include/video/tga.h       1969-12-31 16:00:00.000000000 -0800
 479 +++ fbdev-2.6/include/video/tga.h       2004-02-18 20:53:12.000000000 -0800
 480 @@ -0,0 +1,241 @@
 481 +/*
 482 + *  linux/drivers/video/tgafb.h -- DEC 21030 TGA frame buffer device
 483 + *
 484 + *     Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
 485 + *
 486 + *  $Id$
 487 + *
 488 + *  This file is subject to the terms and conditions of the GNU General Public
 489 + *  License. See the file COPYING in the main directory of this archive for
 490 + *  more details.
 491 + */
 492 +
 493 +#ifndef TGAFB_H
 494 +#define TGAFB_H
 495 +
 496 +/*
 497 + * TGA hardware description (minimal)
 498 + */
 499 +
 500 +#define TGA_TYPE_8PLANE                        0
 501 +#define TGA_TYPE_24PLANE               1
 502 +#define TGA_TYPE_24PLUSZ               3
 503 +
 504 +/*
 505 + * Offsets within Memory Space
 506 + */
 507 +
 508 +#define        TGA_ROM_OFFSET                  0x0000000
 509 +#define        TGA_REGS_OFFSET                 0x0100000
 510 +#define        TGA_8PLANE_FB_OFFSET            0x0200000
 511 +#define        TGA_24PLANE_FB_OFFSET           0x0804000
 512 +#define        TGA_24PLUSZ_FB_OFFSET           0x1004000
 513 +
 514 +#define TGA_FOREGROUND_REG             0x0020
 515 +#define TGA_BACKGROUND_REG             0x0024
 516 +#define        TGA_PLANEMASK_REG               0x0028
 517 +#define TGA_PIXELMASK_ONESHOT_REG      0x002c
 518 +#define        TGA_MODE_REG                    0x0030
 519 +#define        TGA_RASTEROP_REG                0x0034
 520 +#define        TGA_PIXELSHIFT_REG              0x0038
 521 +#define        TGA_DEEP_REG                    0x0050
 522 +#define        TGA_PIXELMASK_REG               0x005c
 523 +#define        TGA_CURSOR_BASE_REG             0x0060
 524 +#define        TGA_HORIZ_REG                   0x0064
 525 +#define        TGA_VERT_REG                    0x0068
 526 +#define        TGA_BASE_ADDR_REG               0x006c
 527 +#define        TGA_VALID_REG                   0x0070
 528 +#define        TGA_CURSOR_XY_REG               0x0074
 529 +#define        TGA_INTR_STAT_REG               0x007c
 530 +#define TGA_DATA_REG                   0x0080
 531 +#define        TGA_RAMDAC_SETUP_REG            0x00c0
 532 +#define        TGA_BLOCK_COLOR0_REG            0x0140
 533 +#define        TGA_BLOCK_COLOR1_REG            0x0144
 534 +#define        TGA_BLOCK_COLOR2_REG            0x0148
 535 +#define        TGA_BLOCK_COLOR3_REG            0x014c
 536 +#define        TGA_BLOCK_COLOR4_REG            0x0150
 537 +#define        TGA_BLOCK_COLOR5_REG            0x0154
 538 +#define        TGA_BLOCK_COLOR6_REG            0x0158
 539 +#define        TGA_BLOCK_COLOR7_REG            0x015c
 540 +#define TGA_COPY64_SRC                 0x0160
 541 +#define TGA_COPY64_DST                 0x0164
 542 +#define        TGA_CLOCK_REG                   0x01e8
 543 +#define        TGA_RAMDAC_REG                  0x01f0
 544 +#define        TGA_CMD_STAT_REG                0x01f8
 545 +
 546 +
 547 +/*
 548 + * Useful defines for managing the registers
 549 + */
 550 +
 551 +#define TGA_HORIZ_ODD                  0x80000000
 552 +#define TGA_HORIZ_POLARITY             0x40000000
 553 +#define TGA_HORIZ_ACT_MSB              0x30000000
 554 +#define TGA_HORIZ_BP                   0x0fe00000
 555 +#define TGA_HORIZ_SYNC                 0x001fc000
 556 +#define TGA_HORIZ_FP                   0x00007c00
 557 +#define TGA_HORIZ_ACT_LSB              0x000001ff
 558 +
 559 +#define TGA_VERT_SE                    0x80000000
 560 +#define TGA_VERT_POLARITY              0x40000000
 561 +#define TGA_VERT_RESERVED              0x30000000
 562 +#define TGA_VERT_BP                    0x0fc00000
 563 +#define TGA_VERT_SYNC                  0x003f0000
 564 +#define TGA_VERT_FP                    0x0000f800
 565 +#define TGA_VERT_ACTIVE                        0x000007ff
 566 +
 567 +#define TGA_VALID_VIDEO                        0x01
 568 +#define TGA_VALID_BLANK                        0x02
 569 +#define TGA_VALID_CURSOR               0x04
 570 +
 571 +#define TGA_MODE_SBM_8BPP              0x000
 572 +#define TGA_MODE_SBM_24BPP             0x300
 573 +
 574 +#define TGA_MODE_SIMPLE                        0x00
 575 +#define TGA_MODE_SIMPLEZ               0x10
 576 +#define TGA_MODE_OPAQUE_STIPPLE                0x01
 577 +#define TGA_MODE_OPAQUE_FILL           0x21
 578 +#define TGA_MODE_TRANSPARENT_STIPPLE   0x03
 579 +#define TGA_MODE_TRANSPARENT_FILL      0x23
 580 +#define TGA_MODE_BLOCK_STIPPLE         0x0d
 581 +#define TGA_MODE_BLOCK_FILL            0x2d
 582 +#define TGA_MODE_COPY                  0x07
 583 +#define TGA_MODE_DMA_READ_COPY_ND      0x17
 584 +#define TGA_MODE_DMA_READ_COPY_D       0x37
 585 +#define TGA_MODE_DMA_WRITE_COPY                0x1f
 586 +
 587 +
 588 +/*
 589 + * Useful defines for managing the ICS1562 PLL clock
 590 + */
 591 +
 592 +#define TGA_PLL_BASE_FREQ              14318           /* .18 */
 593 +#define TGA_PLL_MAX_FREQ               230000
 594 +
 595 +
 596 +/*
 597 + * Useful defines for managing the BT485 on the 8-plane TGA
 598 + */
 599 +
 600 +#define        BT485_READ_BIT                  0x01
 601 +#define        BT485_WRITE_BIT                 0x00
 602 +
 603 +#define        BT485_ADDR_PAL_WRITE            0x00
 604 +#define        BT485_DATA_PAL                  0x02
 605 +#define        BT485_PIXEL_MASK                0x04
 606 +#define        BT485_ADDR_PAL_READ             0x06
 607 +#define        BT485_ADDR_CUR_WRITE            0x08
 608 +#define        BT485_DATA_CUR                  0x0a
 609 +#define        BT485_CMD_0                     0x0c
 610 +#define        BT485_ADDR_CUR_READ             0x0e
 611 +#define        BT485_CMD_1                     0x10
 612 +#define        BT485_CMD_2                     0x12
 613 +#define        BT485_STATUS                    0x14
 614 +#define        BT485_CMD_3                     0x14
 615 +#define        BT485_CUR_RAM                   0x16
 616 +#define        BT485_CUR_LOW_X                 0x18
 617 +#define        BT485_CUR_HIGH_X                0x1a
 618 +#define        BT485_CUR_LOW_Y                 0x1c
 619 +#define        BT485_CUR_HIGH_Y                0x1e
 620 +
 621 +
 622 +/*
 623 + * Useful defines for managing the BT463 on the 24-plane TGAs
 624 + */
 625 +
 626 +#define        BT463_ADDR_LO           0x0
 627 +#define        BT463_ADDR_HI           0x1
 628 +#define        BT463_REG_ACC           0x2
 629 +#define        BT463_PALETTE           0x3
 630 +
 631 +#define        BT463_CUR_CLR_0         0x0100
 632 +#define        BT463_CUR_CLR_1         0x0101
 633 +
 634 +#define        BT463_CMD_REG_0         0x0201
 635 +#define        BT463_CMD_REG_1         0x0202
 636 +#define        BT463_CMD_REG_2         0x0203
 637 +
 638 +#define        BT463_READ_MASK_0       0x0205
 639 +#define        BT463_READ_MASK_1       0x0206
 640 +#define        BT463_READ_MASK_2       0x0207
 641 +#define        BT463_READ_MASK_3       0x0208
 642 +
 643 +#define        BT463_BLINK_MASK_0      0x0209
 644 +#define        BT463_BLINK_MASK_1      0x020a
 645 +#define        BT463_BLINK_MASK_2      0x020b
 646 +#define        BT463_BLINK_MASK_3      0x020c
 647 +
 648 +#define        BT463_WINDOW_TYPE_BASE  0x0300
 649 +
 650 +#ifdef __KERNEL__
 651 +
 652 +/*
 653 + * The framebuffer driver private data.
 654 + */
 655 +
 656 +struct tga_par {
 657 +       /* PCI device.  */
 658 +       struct pci_dev *pdev;
 659 +
 660 +       /* Device dependent information.  */
 661 +       void *tga_mem_base;
 662 +       void *tga_fb_base;
 663 +       void *tga_regs_base;
 664 +       u8 tga_type;                            /* TGA_TYPE_XXX */
 665 +       u8 tga_chip_rev;                        /* dc21030 revision */
 666 +
 667 +       /* Remember blank mode.  */
 668 +       u8 vesa_blanked;
 669 +
 670 +       /* Define the video mode.  */
 671 +       u32 xres, yres;                 /* resolution in pixels */
 672 +       u32 htimings;                   /* horizontal timing register */
 673 +       u32 vtimings;                   /* vertical timing register */
 674 +       u32 pll_freq;                   /* pixclock in mhz */
 675 +       u32 bits_per_pixel;             /* bits per pixel */
 676 +       u32 sync_on_green;              /* set if sync is on green */
 677 +};
 678 +
 679 +
 680 +/*
 681 + * Macros for reading/writing TGA and RAMDAC registers
 682 + */
 683 +
 684 +static inline void
 685 +TGA_WRITE_REG(struct tga_par *par, u32 v, u32 r)
 686 +{
 687 +       writel(v, par->tga_regs_base +r);
 688 +}
 689 +
 690 +static inline u32
 691 +TGA_READ_REG(struct tga_par *par, u32 r)
 692 +{
 693 +       return readl(par->tga_regs_base +r);
 694 +}
 695 +
 696 +static inline void
 697 +BT485_WRITE(struct tga_par *par, u8 v, u8 r)
 698 +{
 699 +       TGA_WRITE_REG(par, r, TGA_RAMDAC_SETUP_REG);
 700 +       TGA_WRITE_REG(par, v | (r << 8), TGA_RAMDAC_REG);
 701 +}
 702 +
 703 +static inline void
 704 +BT463_LOAD_ADDR(struct tga_par *par, u16 a)
 705 +{
 706 +       TGA_WRITE_REG(par, BT463_ADDR_LO<<2, TGA_RAMDAC_SETUP_REG);
 707 +       TGA_WRITE_REG(par, (BT463_ADDR_LO<<10) | (a & 0xff), TGA_RAMDAC_REG);
 708 +       TGA_WRITE_REG(par, BT463_ADDR_HI<<2, TGA_RAMDAC_SETUP_REG);
 709 +       TGA_WRITE_REG(par, (BT463_ADDR_HI<<10) | (a >> 8), TGA_RAMDAC_REG);
 710 +}
 711 +
 712 +static inline void
 713 +BT463_WRITE(struct tga_par *par, u32 m, u16 a, u8 v)
 714 +{
 715 +       BT463_LOAD_ADDR(par, a);
 716 +       TGA_WRITE_REG(par, m << 2, TGA_RAMDAC_SETUP_REG);
 717 +       TGA_WRITE_REG(par, m << 10 | v, TGA_RAMDAC_REG);
 718 +}
 719 +#endif /* __KERNEL__ */
 720 +
 721 +#endif /* TGAFB_H */
 722 diff -urN -X /home/jsimmons/dontdiff linus-2.6/include/video/tgafb.h fbdev-2.6/include/video/tgafb.h
 723 --- linus-2.6/include/video/tgafb.h     2004-02-18 21:01:55.000000000 -0800
 724 +++ fbdev-2.6/include/video/tgafb.h     1969-12-31 16:00:00.000000000 -0800
 725 @@ -1,238 +0,0 @@
 726 -/*
 727 - *  linux/drivers/video/tgafb.h -- DEC 21030 TGA frame buffer device
 728 - *
 729 - *     Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
 730 - *
 731 - *  $Id$
 732 - *
 733 - *  This file is subject to the terms and conditions of the GNU General Public
 734 - *  License. See the file COPYING in the main directory of this archive for
 735 - *  more details.
 736 - */
 737 -
 738 -#ifndef TGAFB_H
 739 -#define TGAFB_H
 740 -
 741 -/*
 742 - * TGA hardware description (minimal)
 743 - */
 744 -
 745 -#define TGA_TYPE_8PLANE                        0
 746 -#define TGA_TYPE_24PLANE               1
 747 -#define TGA_TYPE_24PLUSZ               3
 748 -
 749 -/*
 750 - * Offsets within Memory Space
 751 - */
 752 -
 753 -#define        TGA_ROM_OFFSET                  0x0000000
 754 -#define        TGA_REGS_OFFSET                 0x0100000
 755 -#define        TGA_8PLANE_FB_OFFSET            0x0200000
 756 -#define        TGA_24PLANE_FB_OFFSET           0x0804000
 757 -#define        TGA_24PLUSZ_FB_OFFSET           0x1004000
 758 -
 759 -#define TGA_FOREGROUND_REG             0x0020
 760 -#define TGA_BACKGROUND_REG             0x0024
 761 -#define        TGA_PLANEMASK_REG               0x0028
 762 -#define TGA_PIXELMASK_ONESHOT_REG      0x002c
 763 -#define        TGA_MODE_REG                    0x0030
 764 -#define        TGA_RASTEROP_REG                0x0034
 765 -#define        TGA_PIXELSHIFT_REG              0x0038
 766 -#define        TGA_DEEP_REG                    0x0050
 767 -#define        TGA_PIXELMASK_REG               0x005c
 768 -#define        TGA_CURSOR_BASE_REG             0x0060
 769 -#define        TGA_HORIZ_REG                   0x0064
 770 -#define        TGA_VERT_REG                    0x0068
 771 -#define        TGA_BASE_ADDR_REG               0x006c
 772 -#define        TGA_VALID_REG                   0x0070
 773 -#define        TGA_CURSOR_XY_REG               0x0074
 774 -#define        TGA_INTR_STAT_REG               0x007c
 775 -#define TGA_DATA_REG                   0x0080
 776 -#define        TGA_RAMDAC_SETUP_REG            0x00c0
 777 -#define        TGA_BLOCK_COLOR0_REG            0x0140
 778 -#define        TGA_BLOCK_COLOR1_REG            0x0144
 779 -#define        TGA_BLOCK_COLOR2_REG            0x0148
 780 -#define        TGA_BLOCK_COLOR3_REG            0x014c
 781 -#define        TGA_BLOCK_COLOR4_REG            0x0150
 782 -#define        TGA_BLOCK_COLOR5_REG            0x0154
 783 -#define        TGA_BLOCK_COLOR6_REG            0x0158
 784 -#define        TGA_BLOCK_COLOR7_REG            0x015c
 785 -#define TGA_COPY64_SRC                 0x0160
 786 -#define TGA_COPY64_DST                 0x0164
 787 -#define        TGA_CLOCK_REG                   0x01e8
 788 -#define        TGA_RAMDAC_REG                  0x01f0
 789 -#define        TGA_CMD_STAT_REG                0x01f8
 790 -
 791 -
 792 -/*
 793 - * Useful defines for managing the registers
 794 - */
 795 -
 796 -#define TGA_HORIZ_ODD                  0x80000000
 797 -#define TGA_HORIZ_POLARITY             0x40000000
 798 -#define TGA_HORIZ_ACT_MSB              0x30000000
 799 -#define TGA_HORIZ_BP                   0x0fe00000
 800 -#define TGA_HORIZ_SYNC                 0x001fc000
 801 -#define TGA_HORIZ_FP                   0x00007c00
 802 -#define TGA_HORIZ_ACT_LSB              0x000001ff
 803 -
 804 -#define TGA_VERT_SE                    0x80000000
 805 -#define TGA_VERT_POLARITY              0x40000000
 806 -#define TGA_VERT_RESERVED              0x30000000
 807 -#define TGA_VERT_BP                    0x0fc00000
 808 -#define TGA_VERT_SYNC                  0x003f0000
 809 -#define TGA_VERT_FP                    0x0000f800
 810 -#define TGA_VERT_ACTIVE                        0x000007ff
 811 -
 812 -#define TGA_VALID_VIDEO                        0x01
 813 -#define TGA_VALID_BLANK                        0x02
 814 -#define TGA_VALID_CURSOR               0x04
 815 -
 816 -#define TGA_MODE_SBM_8BPP              0x000
 817 -#define TGA_MODE_SBM_24BPP             0x300
 818 -
 819 -#define TGA_MODE_SIMPLE                        0x00
 820 -#define TGA_MODE_SIMPLEZ               0x10
 821 -#define TGA_MODE_OPAQUE_STIPPLE                0x01
 822 -#define TGA_MODE_OPAQUE_FILL           0x21
 823 -#define TGA_MODE_TRANSPARENT_STIPPLE   0x03
 824 -#define TGA_MODE_TRANSPARENT_FILL      0x23
 825 -#define TGA_MODE_BLOCK_STIPPLE         0x0d
 826 -#define TGA_MODE_BLOCK_FILL            0x2d
 827 -#define TGA_MODE_COPY                  0x07
 828 -#define TGA_MODE_DMA_READ_COPY_ND      0x17
 829 -#define TGA_MODE_DMA_READ_COPY_D       0x37
 830 -#define TGA_MODE_DMA_WRITE_COPY                0x1f
 831 -
 832 -
 833 -/*
 834 - * Useful defines for managing the ICS1562 PLL clock
 835 - */
 836 -
 837 -#define TGA_PLL_BASE_FREQ              14318           /* .18 */
 838 -#define TGA_PLL_MAX_FREQ               230000
 839 -
 840 -
 841 -/*
 842 - * Useful defines for managing the BT485 on the 8-plane TGA
 843 - */
 844 -
 845 -#define        BT485_READ_BIT                  0x01
 846 -#define        BT485_WRITE_BIT                 0x00
 847 -
 848 -#define        BT485_ADDR_PAL_WRITE            0x00
 849 -#define        BT485_DATA_PAL                  0x02
 850 -#define        BT485_PIXEL_MASK                0x04
 851 -#define        BT485_ADDR_PAL_READ             0x06
 852 -#define        BT485_ADDR_CUR_WRITE            0x08
 853 -#define        BT485_DATA_CUR                  0x0a
 854 -#define        BT485_CMD_0                     0x0c
 855 -#define        BT485_ADDR_CUR_READ             0x0e
 856 -#define        BT485_CMD_1                     0x10
 857 -#define        BT485_CMD_2                     0x12
 858 -#define        BT485_STATUS                    0x14
 859 -#define        BT485_CMD_3                     0x14
 860 -#define        BT485_CUR_RAM                   0x16
 861 -#define        BT485_CUR_LOW_X                 0x18
 862 -#define        BT485_CUR_HIGH_X                0x1a
 863 -#define        BT485_CUR_LOW_Y                 0x1c
 864 -#define        BT485_CUR_HIGH_Y                0x1e
 865 -
 866 -
 867 -/*
 868 - * Useful defines for managing the BT463 on the 24-plane TGAs
 869 - */
 870 -
 871 -#define        BT463_ADDR_LO           0x0
 872 -#define        BT463_ADDR_HI           0x1
 873 -#define        BT463_REG_ACC           0x2
 874 -#define        BT463_PALETTE           0x3
 875 -
 876 -#define        BT463_CUR_CLR_0         0x0100
 877 -#define        BT463_CUR_CLR_1         0x0101
 878 -
 879 -#define        BT463_CMD_REG_0         0x0201
 880 -#define        BT463_CMD_REG_1         0x0202
 881 -#define        BT463_CMD_REG_2         0x0203
 882 -
 883 -#define        BT463_READ_MASK_0       0x0205
 884 -#define        BT463_READ_MASK_1       0x0206
 885 -#define        BT463_READ_MASK_2       0x0207
 886 -#define        BT463_READ_MASK_3       0x0208
 887 -
 888 -#define        BT463_BLINK_MASK_0      0x0209
 889 -#define        BT463_BLINK_MASK_1      0x020a
 890 -#define        BT463_BLINK_MASK_2      0x020b
 891 -#define        BT463_BLINK_MASK_3      0x020c
 892 -
 893 -#define        BT463_WINDOW_TYPE_BASE  0x0300
 894 -
 895 -/*
 896 - * The framebuffer driver private data.
 897 - */
 898 -
 899 -struct tga_par {
 900 -       /* PCI device.  */
 901 -       struct pci_dev *pdev;
 902 -
 903 -       /* Device dependent information.  */
 904 -       void *tga_mem_base;
 905 -       void *tga_fb_base;
 906 -       void *tga_regs_base;
 907 -       u8 tga_type;                            /* TGA_TYPE_XXX */
 908 -       u8 tga_chip_rev;                        /* dc21030 revision */
 909 -
 910 -       /* Remember blank mode.  */
 911 -       u8 vesa_blanked;
 912 -
 913 -       /* Define the video mode.  */
 914 -       u32 xres, yres;                 /* resolution in pixels */
 915 -       u32 htimings;                   /* horizontal timing register */
 916 -       u32 vtimings;                   /* vertical timing register */
 917 -       u32 pll_freq;                   /* pixclock in mhz */
 918 -       u32 bits_per_pixel;             /* bits per pixel */
 919 -       u32 sync_on_green;              /* set if sync is on green */
 920 -};
 921 -
 922 -
 923 -/*
 924 - * Macros for reading/writing TGA and RAMDAC registers
 925 - */
 926 -
 927 -static inline void
 928 -TGA_WRITE_REG(struct tga_par *par, u32 v, u32 r)
 929 -{
 930 -       writel(v, par->tga_regs_base +r);
 931 -}
 932 -
 933 -static inline u32
 934 -TGA_READ_REG(struct tga_par *par, u32 r)
 935 -{
 936 -       return readl(par->tga_regs_base +r);
 937 -}
 938 -
 939 -static inline void
 940 -BT485_WRITE(struct tga_par *par, u8 v, u8 r)
 941 -{
 942 -       TGA_WRITE_REG(par, r, TGA_RAMDAC_SETUP_REG);
 943 -       TGA_WRITE_REG(par, v | (r << 8), TGA_RAMDAC_REG);
 944 -}
 945 -
 946 -static inline void
 947 -BT463_LOAD_ADDR(struct tga_par *par, u16 a)
 948 -{
 949 -       TGA_WRITE_REG(par, BT463_ADDR_LO<<2, TGA_RAMDAC_SETUP_REG);
 950 -       TGA_WRITE_REG(par, (BT463_ADDR_LO<<10) | (a & 0xff), TGA_RAMDAC_REG);
 951 -       TGA_WRITE_REG(par, BT463_ADDR_HI<<2, TGA_RAMDAC_SETUP_REG);
 952 -       TGA_WRITE_REG(par, (BT463_ADDR_HI<<10) | (a >> 8), TGA_RAMDAC_REG);
 953 -}
 954 -
 955 -static inline void
 956 -BT463_WRITE(struct tga_par *par, u32 m, u16 a, u8 v)
 957 -{
 958 -       BT463_LOAD_ADDR(par, a);
 959 -       TGA_WRITE_REG(par, m << 2, TGA_RAMDAC_SETUP_REG);
 960 -       TGA_WRITE_REG(par, m << 10 | v, TGA_RAMDAC_REG);
 961 -}
 962 -
 963 -#endif /* TGAFB_H */