]> git.pld-linux.org Git - packages/kernel.git/blame - linux-2.6-sk98lin_8.41.2.3.patch
projects / packages / kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
- up to 2.6.27.10
[packages/kernel.git] / linux-2.6-sk98lin_8.41.2.3.patch
Content-type: text/html ]> git.pld-linux.org Git - packages/kernel.git/blame - linux-2.6-sk98lin_8.41.2.3.patch
projects / packages / kernel.git / blame
? search:


500 - Internal Server Error
Malformed UTF-8 character (fatal) at (eval 6) line 1, <$fd> line 43871.
The Linux kernel (the core of the Linux operating system)
This page took 4.992674 seconds and 4 git commands to generate.
CommitLineData
a3b93527 1diff -ruN linux/drivers/net/sk98lin/Makefile linux-new/drivers/net/sk98lin/Makefile
2--- linux/drivers/net/sk98lin/Makefile 2007-01-02 23:21:17.000000000 +0100
3+++ linux-new/drivers/net/sk98lin/Makefile 2007-01-02 23:31:52.000000000 +0100
4@@ -1,6 +1,68 @@
5+#******************************************************************************
6 #
7-# Makefile for the SysKonnect SK-98xx device driver.
8+# Name: skge.c
9+# Project: GEnesis, PCI Gigabit Ethernet Adapter
10+# Version: $Revision$
11+# Date: $Date$
12+# Purpose: The main driver source module
13 #
14+#******************************************************************************
15+
16+#******************************************************************************
17+#
18+# (C)Copyright 1998-2002 SysKonnect GmbH.
19+# (C)Copyright 2002-2005 Marvell.
20+#
21+# Makefile for Marvell Yukon chipset and SysKonnect Gigabit Ethernet
22+# Server Adapter driver. (Kernel 2.6)
23+#
24+# Author: Mirko Lindner (mlindner@syskonnect.de)
25+# Ralph Roesler (rroesler@syskonnect.de)
26+#
27+# Address all question to: linux@syskonnect.de
28+#
29+# This program is free software; you can redistribute it and/or modify
30+# it under the terms of the GNU General Public License as published by
31+# the Free Software Foundation; either version 2 of the License, or
32+# (at your option) any later version.
33+#
34+# The information in this file is provided "AS IS" without warranty.
35+#
36+#******************************************************************************
37+
38+#******************************************************************************
39+#
40+# History:
41+#
42+# $Log$
43+# Revision 1.1.4.2 2006/08/28 12:44:39 mlindner
44+# Add: install.sh script handling added
45+#
46+# Revision 1.1.4.1 2006/08/28 09:01:59 mlindner
47+# Add: Initial IPMI kernel 2.4 and 2.6 support
48+#
49+# Revision 1.1 2006/07/19 15:37:22 amock
50+# Imported/updated from Release Server GELIN_V8_35_02
51+#
52+# Revision 1.9.2.1 2005/04/11 09:01:18 mlindner
53+# Fix: Copyright year changed
54+#
55+# Revision 1.9 2004/07/13 15:54:50 rroesler
56+# Add: file skethtool.c
57+# Fix: corrected header regarding copyright
58+# Fix: minor typos corrected
59+#
60+# Revision 1.8 2004/06/08 08:39:38 mlindner
61+# Fix: Add CONFIG_SK98LIN_ZEROCOPY as default
62+#
63+# Revision 1.7 2004/06/03 16:06:56 mlindner
64+# Fix: Added compile flag SK_DIAG_SUPPORT
65+#
66+# Revision 1.6 2004/06/02 08:02:59 mlindner
67+# Add: Changed header information and inserted a GPL statement
68+#
69+#
70+#******************************************************************************
71
72
73 #
74@@ -9,25 +71,43 @@
75 # SKPARAM += -DSK_KERNEL_24_26
76 # SKPARAM += -DSK_KERNEL_26
77 # SKPARAM += -DSK_KERNEL_22_24
78+# ASFPARAM += -DSK_ASF
79+
80+ifdef ASFPARAM
81+ ASF_OPS += \
82+ skgeasf.o \
83+ skgeasfconv.o \
84+ skgespi.o \
85+ skgespilole.o \
86+ skfops.o
87+else
88+ ASF_OPS +=
89+endif
90+
91+
92
93 obj-$(CONFIG_SK98LIN) += sk98lin.o
94 sk98lin-objs := \
95 skge.o \
96+ sky2.o \
97 skethtool.o \
98+ sky2le.o \
99 skdim.o \
100 skaddr.o \
101 skgehwt.o \
102 skgeinit.o \
103 skgepnmi.o \
104 skgesirq.o \
105- ski2c.o \
106+ sktwsi.o \
107 sklm80.o \
108 skqueue.o \
109 skrlmt.o \
110 sktimer.o \
111 skvpd.o \
112- skxmac2.o
113-
114+ skxmac2.o \
115+ skproc.o \
116+ skcsum.o \
117+ $(ASF_OPS)
118 # DBGDEF = \
119 # -DDEBUG
120
121@@ -75,13 +155,11 @@
122 # SK_DBGCAT_DRV_INT_SRC 0x04000000 interrupts sources
123 # SK_DBGCAT_DRV_EVENT 0x08000000 driver events
124
125-EXTRA_CFLAGS += -Idrivers/net/sk98lin -DSK_DIAG_SUPPORT -DGENESIS -DYUKON $(DBGDEF) $(SKPARAM)
126+EXTRA_CFLAGS += -Idrivers/net/sk98lin -DSK_USE_CSUM -DSK_DIAG_SUPPORT \
127+ -DGENESIS -DYUKON -DYUK2 -DCONFIG_SK98LIN_ZEROCOPY \
128+ $(DBGDEF) $(SKPARAM) $(ASFPARAM)
129
130 clean:
131 rm -f core *.o *.a *.s
132
133
134-
135-
136-
137-
138diff -ruN linux/drivers/net/sk98lin/h/lm80.h linux-new/drivers/net/sk98lin/h/lm80.h
139--- linux/drivers/net/sk98lin/h/lm80.h 2007-01-02 23:21:17.000000000 +0100
140+++ linux-new/drivers/net/sk98lin/h/lm80.h 2006-10-13 11:18:49.000000000 +0200
141@@ -2,8 +2,8 @@
142 *
143 * Name: lm80.h
144 * Project: Gigabit Ethernet Adapters, Common Modules
145- * Version: $Revision$
146- * Date: $Date$
147+ * Version: $Revision$
148+ * Date: $Date$
149 * Purpose: Contains all defines for the LM80 Chip
150 * (National Semiconductor).
151 *
152@@ -11,6 +11,7 @@
153
154 /******************************************************************************
155 *
156+ * LICENSE:
157 * (C)Copyright 1998-2002 SysKonnect.
158 * (C)Copyright 2002-2003 Marvell.
159 *
160@@ -20,6 +21,7 @@
161 * (at your option) any later version.
162 *
163 * The information in this file is provided "AS IS" without warranty.
164+ * /LICENSE
165 *
166 ******************************************************************************/
167
168diff -ruN linux/drivers/net/sk98lin/h/skaddr.h linux-new/drivers/net/sk98lin/h/skaddr.h
169--- linux/drivers/net/sk98lin/h/skaddr.h 2007-01-02 23:21:17.000000000 +0100
170+++ linux-new/drivers/net/sk98lin/h/skaddr.h 2006-10-13 11:18:49.000000000 +0200
171@@ -2,14 +2,15 @@
172 *
173 * Name: skaddr.h
174 * Project: Gigabit Ethernet Adapters, ADDR-Modul
175- * Version: $Revision$
176- * Date: $Date$
177+ * Version: $Revision$
178+ * Date: $Date$
179 * Purpose: Header file for Address Management (MC, UC, Prom).
180 *
181 ******************************************************************************/
182
183 /******************************************************************************
184 *
185+ * LICENSE:
186 * (C)Copyright 1998-2002 SysKonnect GmbH.
187 * (C)Copyright 2002-2003 Marvell.
188 *
189@@ -19,6 +20,7 @@
190 * (at your option) any later version.
191 *
192 * The information in this file is provided "AS IS" without warranty.
193+ * /LICENSE
194 *
195 ******************************************************************************/
196
197@@ -236,6 +238,18 @@
198 SK_U32 PortNumber,
199 int Flags);
200
201+extern int SkAddrXmacMcClear(
202+ SK_AC *pAC,
203+ SK_IOC IoC,
204+ SK_U32 PortNumber,
205+ int Flags);
206+
207+extern int SkAddrGmacMcClear(
208+ SK_AC *pAC,
209+ SK_IOC IoC,
210+ SK_U32 PortNumber,
211+ int Flags);
212+
213 extern int SkAddrMcAdd(
214 SK_AC *pAC,
215 SK_IOC IoC,
216@@ -243,11 +257,41 @@
217 SK_MAC_ADDR *pMc,
218 int Flags);
219
220+extern int SkAddrXmacMcAdd(
221+ SK_AC *pAC,
222+ SK_IOC IoC,
223+ SK_U32 PortNumber,
224+ SK_MAC_ADDR *pMc,
225+ int Flags);
226+
227+extern SK_U32 SkXmacMcHash(
228+ unsigned char *pMc);
229+
230+extern int SkAddrGmacMcAdd(
231+ SK_AC *pAC,
232+ SK_IOC IoC,
233+ SK_U32 PortNumber,
234+ SK_MAC_ADDR *pMc,
235+ int Flags);
236+
237+extern SK_U32 SkGmacMcHash(
238+ unsigned char *pMc);
239+
240 extern int SkAddrMcUpdate(
241 SK_AC *pAC,
242 SK_IOC IoC,
243 SK_U32 PortNumber);
244
245+extern int SkAddrXmacMcUpdate(
246+ SK_AC *pAC,
247+ SK_IOC IoC,
248+ SK_U32 PortNumber);
249+
250+extern int SkAddrGmacMcUpdate(
251+ SK_AC *pAC,
252+ SK_IOC IoC,
253+ SK_U32 PortNumber);
254+
255 extern int SkAddrOverride(
256 SK_AC *pAC,
257 SK_IOC IoC,
258@@ -261,6 +305,18 @@
259 SK_U32 PortNumber,
260 int NewPromMode);
261
262+extern int SkAddrXmacPromiscuousChange(
263+ SK_AC *pAC,
264+ SK_IOC IoC,
265+ SK_U32 PortNumber,
266+ int NewPromMode);
267+
268+extern int SkAddrGmacPromiscuousChange(
269+ SK_AC *pAC,
270+ SK_IOC IoC,
271+ SK_U32 PortNumber,
272+ int NewPromMode);
273+
274 #ifndef SK_SLIM
275 extern int SkAddrSwap(
276 SK_AC *pAC,
277diff -ruN linux/drivers/net/sk98lin/h/skcsum.h linux-new/drivers/net/sk98lin/h/skcsum.h
278--- linux/drivers/net/sk98lin/h/skcsum.h 2007-01-02 23:21:17.000000000 +0100
279+++ linux-new/drivers/net/sk98lin/h/skcsum.h 2006-10-13 11:18:49.000000000 +0200
280@@ -2,14 +2,15 @@
281 *
282 * Name: skcsum.h
283 * Project: GEnesis - SysKonnect SK-NET Gigabit Ethernet (SK-98xx)
284- * Version: $Revision$
285- * Date: $Date$
286+ * Version: $Revision$
287+ * Date: $Date$
288 * Purpose: Store/verify Internet checksum in send/receive packets.
289 *
290 ******************************************************************************/
291
292 /******************************************************************************
293 *
294+ * LICENSE:
295 * (C)Copyright 1998-2001 SysKonnect GmbH.
296 *
297 * This program is free software; you can redistribute it and/or modify
298@@ -18,6 +19,7 @@
299 * (at your option) any later version.
300 *
301 * The information in this file is provided "AS IS" without warranty.
302+ * /LICENSE
303 *
304 ******************************************************************************/
305
306@@ -157,9 +159,7 @@
307 typedef struct s_Csum {
308 /* Enabled receive SK_PROTO_XXX bit flags. */
309 unsigned ReceiveFlags[SK_MAX_NETS];
310-#ifdef TX_CSUM
311 unsigned TransmitFlags[SK_MAX_NETS];
312-#endif /* TX_CSUM */
313
314 /* The protocol statistics structure; one per supported protocol. */
315 SKCS_PROTO_STATS ProtoStats[SK_MAX_NETS][SKCS_NUM_PROTOCOLS];
316@@ -203,6 +203,12 @@
317 unsigned Checksum2,
318 int NetNumber);
319
320+extern void SkCsGetSendInfo(
321+ SK_AC *pAc,
322+ void *pIpHeader,
323+ SKCS_PACKET_INFO *pPacketInfo,
324+ int NetNumber);
325+
326 extern void SkCsSetReceiveFlags(
327 SK_AC *pAc,
328 unsigned ReceiveFlags,
329diff -ruN linux/drivers/net/sk98lin/h/skdebug.h linux-new/drivers/net/sk98lin/h/skdebug.h
330--- linux/drivers/net/sk98lin/h/skdebug.h 2007-01-02 23:21:17.000000000 +0100
331+++ linux-new/drivers/net/sk98lin/h/skdebug.h 2006-10-13 11:18:49.000000000 +0200
332@@ -2,23 +2,24 @@
333 *
334 * Name: skdebug.h
335 * Project: Gigabit Ethernet Adapters, Common Modules
336- * Version: $Revision$
337- * Date: $Date$
338+ * Version: $Revision$
339+ * Date: $Date$
340 * Purpose: SK specific DEBUG support
341 *
342 ******************************************************************************/
343
344 /******************************************************************************
345 *
346+ * LICENSE:
347 * (C)Copyright 1998-2002 SysKonnect.
348- * (C)Copyright 2002-2003 Marvell.
349+ * (C)Copyright 2002-2005 Marvell.
350 *
351 * This program is free software; you can redistribute it and/or modify
352 * it under the terms of the GNU General Public License as published by
353 * the Free Software Foundation; either version 2 of the License, or
354 * (at your option) any later version.
355- *
356 * The information in this file is provided "AS IS" without warranty.
357+ * /LICENSE
358 *
359 ******************************************************************************/
360
361@@ -28,9 +29,9 @@
362 #ifdef DEBUG
363 #ifndef SK_DBG_MSG
364 #define SK_DBG_MSG(pAC,comp,cat,arg) \
365- if ( ((comp) & SK_DBG_CHKMOD(pAC)) && \
366- ((cat) & SK_DBG_CHKCAT(pAC)) ) { \
367- SK_DBG_PRINTF arg ; \
368+ if ( ((comp) & SK_DBG_CHKMOD(pAC)) && \
369+ ((cat) & SK_DBG_CHKCAT(pAC)) ) { \
370+ SK_DBG_PRINTF arg; \
371 }
372 #endif
373 #else
374@@ -58,6 +59,13 @@
375 #define SK_DBGMOD_ADDR 0x00000080L /* ADDR module */
376 #define SK_DBGMOD_PECP 0x00000100L /* PECP module */
377 #define SK_DBGMOD_POWM 0x00000200L /* Power Management module */
378+#ifdef SK_ASF
379+#define SK_DBGMOD_ASF 0x00000400L /* ASF module */
380+#endif
381+#ifdef SK_LBFO
382+#define SK_DBGMOD_LACP 0x00000800L /* link aggregation control protocol */
383+#define SK_DBGMOD_FD 0x00001000L /* frame distributor (link aggregation) */
384+#endif /* SK_LBFO */
385
386 /* Debug events */
387
388diff -ruN linux/drivers/net/sk98lin/h/skdrv1st.h linux-new/drivers/net/sk98lin/h/skdrv1st.h
389--- linux/drivers/net/sk98lin/h/skdrv1st.h 2007-01-02 23:21:17.000000000 +0100
390+++ linux-new/drivers/net/sk98lin/h/skdrv1st.h 2006-10-13 11:18:50.000000000 +0200
391@@ -2,8 +2,8 @@
392 *
393 * Name: skdrv1st.h
394 * Project: GEnesis, PCI Gigabit Ethernet Adapter
395- * Version: $Revision$
396- * Date: $Date$
397+ * Version: $Revision$
398+ * Date: $Date$
399 * Purpose: First header file for driver and all other modules
400 *
401 ******************************************************************************/
402@@ -11,7 +11,7 @@
403 /******************************************************************************
404 *
405 * (C)Copyright 1998-2002 SysKonnect GmbH.
406- * (C)Copyright 2002-2003 Marvell.
407+ * (C)Copyright 2002-2005 Marvell.
408 *
409 * This program is free software; you can redistribute it and/or modify
410 * it under the terms of the GNU General Public License as published by
411@@ -22,23 +22,12 @@
412 *
413 ******************************************************************************/
414
415-/******************************************************************************
416- *
417- * Description:
418- *
419- * This is the first include file of the driver, which includes all
420- * neccessary system header files and some of the GEnesis header files.
421- * It also defines some basic items.
422- *
423- * Include File Hierarchy:
424- *
425- * see skge.c
426- *
427- ******************************************************************************/
428-
429 #ifndef __INC_SKDRV1ST_H
430 #define __INC_SKDRV1ST_H
431
432+/* Check kernel version */
433+#include <linux/version.h>
434+
435 typedef struct s_AC SK_AC;
436
437 /* Set card versions */
438@@ -55,6 +44,9 @@
439
440 #define SK_ADDR_EQUAL(a1,a2) (!memcmp(a1,a2,6))
441
442+#define SK_STRNCMP(s1,s2,len) strncmp(s1,s2,len)
443+#define SK_STRCPY(dest,src) strcpy(dest,src)
444+
445 #include <linux/types.h>
446 #include <linux/kernel.h>
447 #include <linux/string.h>
448@@ -63,10 +55,9 @@
449 #include <linux/slab.h>
450 #include <linux/interrupt.h>
451 #include <linux/pci.h>
452-#include <linux/bitops.h>
453 #include <asm/byteorder.h>
454+#include <asm/bitops.h>
455 #include <asm/io.h>
456-#include <asm/irq.h>
457 #include <linux/netdevice.h>
458 #include <linux/etherdevice.h>
459 #include <linux/skbuff.h>
460@@ -76,11 +67,7 @@
461 #include <net/checksum.h>
462
463 #define SK_CS_CALCULATE_CHECKSUM
464-#ifndef CONFIG_X86_64
465-#define SkCsCalculateChecksum(p,l) ((~ip_compute_csum(p, l)) & 0xffff)
466-#else
467-#define SkCsCalculateChecksum(p,l) ((~ip_fast_csum(p, l)) & 0xffff)
468-#endif
469+#define SkCsCalculateChecksum(p,l) (~csum_fold(csum_partial(p, l, 0)))
470
471 #include "h/sktypes.h"
472 #include "h/skerror.h"
473@@ -88,10 +75,15 @@
474 #include "h/lm80.h"
475 #include "h/xmac_ii.h"
476
477+#ifndef SK_BMU_RX_WM_PEX
478+#define SK_BMU_RX_WM_PEX 0x80
479+#endif
480+
481 #ifdef __LITTLE_ENDIAN
482 #define SK_LITTLE_ENDIAN
483 #else
484 #define SK_BIG_ENDIAN
485+#define SK_USE_REV_DESC
486 #endif
487
488 #define SK_NET_DEVICE net_device
489@@ -107,7 +99,7 @@
490 #define SK_MAX_MACS 2
491 #define SK_MAX_NETS 2
492
493-#define SK_IOC char __iomem *
494+#define SK_IOC char*
495
496 typedef struct s_DrvRlmtMbuf SK_MBUF;
497
498@@ -186,3 +178,8 @@
499
500 #endif
501
502+/*******************************************************************************
503+ *
504+ * End of file
505+ *
506+ ******************************************************************************/
507diff -ruN linux/drivers/net/sk98lin/h/skdrv2nd.h linux-new/drivers/net/sk98lin/h/skdrv2nd.h
508--- linux/drivers/net/sk98lin/h/skdrv2nd.h 2007-01-02 23:21:17.000000000 +0100
509+++ linux-new/drivers/net/sk98lin/h/skdrv2nd.h 2006-10-13 11:18:50.000000000 +0200
510@@ -1,17 +1,17 @@
511 /******************************************************************************
512 *
513- * Name: skdrv2nd.h
514- * Project: GEnesis, PCI Gigabit Ethernet Adapter
515- * Version: $Revision$
516- * Date: $Date$
517- * Purpose: Second header file for driver and all other modules
518+ * Name: skdrv2nd.h
519+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
520+ * Version: $Revision$
521+ * Date: $Date$
522+ * Purpose: Second header file for driver and all other modules
523 *
524 ******************************************************************************/
525
526 /******************************************************************************
527 *
528 * (C)Copyright 1998-2002 SysKonnect GmbH.
529- * (C)Copyright 2002-2003 Marvell.
530+ * (C)Copyright 2002-2005 Marvell.
531 *
532 * This program is free software; you can redistribute it and/or modify
533 * it under the terms of the GNU General Public License as published by
534@@ -42,10 +42,11 @@
535 #include "h/skqueue.h"
536 #include "h/skgehwt.h"
537 #include "h/sktimer.h"
538-#include "h/ski2c.h"
539+#include "h/sktwsi.h"
540 #include "h/skgepnmi.h"
541 #include "h/skvpd.h"
542 #include "h/skgehw.h"
543+#include "h/sky2le.h"
544 #include "h/skgeinit.h"
545 #include "h/skaddr.h"
546 #include "h/skgesirq.h"
547@@ -53,103 +54,194 @@
548 #include "h/skrlmt.h"
549 #include "h/skgedrv.h"
550
551+/* Defines for the poll cotroller */
552+#define SK_NETDUMP_POLL
553
554-extern SK_MBUF *SkDrvAllocRlmtMbuf(SK_AC*, SK_IOC, unsigned);
555-extern void SkDrvFreeRlmtMbuf(SK_AC*, SK_IOC, SK_MBUF*);
556-extern SK_U64 SkOsGetTime(SK_AC*);
557-extern int SkPciReadCfgDWord(SK_AC*, int, SK_U32*);
558-extern int SkPciReadCfgWord(SK_AC*, int, SK_U16*);
559-extern int SkPciReadCfgByte(SK_AC*, int, SK_U8*);
560-extern int SkPciWriteCfgWord(SK_AC*, int, SK_U16);
561-extern int SkPciWriteCfgByte(SK_AC*, int, SK_U8);
562-extern int SkDrvEvent(SK_AC*, SK_IOC IoC, SK_U32, SK_EVPARA);
563-
564-#ifdef SK_DIAG_SUPPORT
565-extern int SkDrvEnterDiagMode(SK_AC *pAc);
566-extern int SkDrvLeaveDiagMode(SK_AC *pAc);
567+#ifdef SK_NETDUMP_POLL
568+#ifdef HAVE_POLL_CONTROLLER
569+#define SK_POLL_CONTROLLER
570+#define CONFIG_SK98LIN_NAPI
571+#elif CONFIG_NET_POLL_CONTROLLER
572+#define SK_POLL_CONTROLLER
573+#define CONFIG_SK98LIN_NAPI
574 #endif
575+#endif
576+
577+
578+/******************************************************************************
579+ *
580+ * Generic driver defines
581+ *
582+ ******************************************************************************/
583+
584+#define USE_TIST_FOR_RESET /* Use timestamp for reset */
585+#define Y2_RECOVERY /* use specific recovery yukon2 functions */
586+#define Y2_LE_CHECK /* activate check for LE order */
587+#define Y2_SYNC_CHECK /* activate check for receiver in sync */
588+#define SK_YUKON2 /* Enable Yukon2 dual net support */
589+#define USE_SK_TX_CHECKSUM /* use the tx hw checksum driver functionality */
590+#define USE_SK_RX_CHECKSUM /* use the rx hw checksum driver functionality */
591+#define USE_SK_TSO_FEATURE /* use TCP segmentation offload if possible */
592+#define SK_COPY_THRESHOLD 50 /* threshold for copying small RX frames;
593+ * 0 avoids copying, 9001 copies all */
594+#define SK_MAX_CARD_PARAM 16 /* number of adapters that can be configured via
595+ * command line params */
596+//#define USE_TX_COMPLETE /* use of a transmit complete interrupt */
597+#define Y2_RX_CHECK /* RX Check timestamp */
598+
599+#define SK_REL_SPIN_LOCK(IoC)
600+#define SK_ACQ_SPIN_LOCK(IoC)
601+
602+/*
603+ * use those defines for a compile-in version of the driver instead
604+ * of command line parameters
605+ */
606+// #define LINK_SPEED_A {"Auto",}
607+// #define LINK_SPEED_B {"Auto",}
608+// #define AUTO_NEG_A {"Sense",}
609+// #define AUTO_NEG_B {"Sense"}
610+// #define DUP_CAP_A {"Both",}
611+// #define DUP_CAP_B {"Both",}
612+// #define FLOW_CTRL_A {"SymOrRem",}
613+// #define FLOW_CTRL_B {"SymOrRem",}
614+// #define ROLE_A {"Auto",}
615+// #define ROLE_B {"Auto",}
616+// #define PREF_PORT {"A",}
617+// #define CON_TYPE {"Auto",}
618+// #define RLMT_MODE {"CheckLinkState",}
619+
620+#ifdef Y2_RECOVERY
621+#define CHECK_TRANSMIT_TIMEOUT
622+#define Y2_RESYNC_WATERMARK 1000000L
623+#endif
624+
625+
626+/******************************************************************************
627+ *
628+ * Generic ISR defines
629+ *
630+ ******************************************************************************/
631+
632+#define SkIsrRetVar irqreturn_t
633+#define SkIsrRetNone IRQ_NONE
634+#define SkIsrRetHandled IRQ_HANDLED
635+
636+#define DEV_KFREE_SKB(skb) dev_kfree_skb(skb)
637+#define DEV_KFREE_SKB_IRQ(skb) dev_kfree_skb_irq(skb)
638+#define DEV_KFREE_SKB_ANY(skb) dev_kfree_skb_any(skb)
639+
640+/******************************************************************************
641+ *
642+ * Global function prototypes
643+ *
644+ ******************************************************************************/
645+
646+extern SK_MBUF *SkDrvAllocRlmtMbuf(SK_AC*, SK_IOC, unsigned);
647+extern void SkDrvFreeRlmtMbuf(SK_AC*, SK_IOC, SK_MBUF*);
648+extern SK_U64 SkOsGetTime(SK_AC*);
649+extern int SkPciReadCfgDWord(SK_AC*, int, SK_U32*);
650+extern int SkPciReadCfgWord(SK_AC*, int, SK_U16*);
651+extern int SkPciReadCfgByte(SK_AC*, int, SK_U8*);
652+extern int SkPciWriteCfgDWord(SK_AC*, int, SK_U32);
653+extern int SkPciWriteCfgWord(SK_AC*, int, SK_U16);
654+extern int SkPciWriteCfgByte(SK_AC*, int, SK_U8);
655+extern int SkDrvEvent(SK_AC*, SK_IOC IoC, SK_U32, SK_EVPARA);
656+extern int SkDrvEnterDiagMode(SK_AC *pAc);
657+extern int SkDrvLeaveDiagMode(SK_AC *pAc);
658+
659+/******************************************************************************
660+ *
661+ * Linux specific RLMT buffer structure (SK_MBUF typedef in skdrv1st)!
662+ *
663+ ******************************************************************************/
664
665 struct s_DrvRlmtMbuf {
666- SK_MBUF *pNext; /* Pointer to next RLMT Mbuf. */
667- SK_U8 *pData; /* Data buffer (virtually contig.). */
668- unsigned Size; /* Data buffer size. */
669- unsigned Length; /* Length of packet (<= Size). */
670- SK_U32 PortIdx; /* Receiving/transmitting port. */
671+ SK_MBUF *pNext; /* Pointer to next RLMT Mbuf. */
672+ SK_U8 *pData; /* Data buffer (virtually contig.). */
673+ unsigned Size; /* Data buffer size. */
674+ unsigned Length; /* Length of packet (<= Size). */
675+ SK_U32 PortIdx; /* Receiving/transmitting port. */
676 #ifdef SK_RLMT_MBUF_PRIVATE
677- SK_RLMT_MBUF Rlmt; /* Private part for RLMT. */
678-#endif /* SK_RLMT_MBUF_PRIVATE */
679- struct sk_buff *pOs; /* Pointer to message block */
680+ SK_RLMT_MBUF Rlmt; /* Private part for RLMT. */
681+#endif
682+ struct sk_buff *pOs; /* Pointer to message block */
683 };
684
685+/******************************************************************************
686+ *
687+ * Linux specific TIME defines
688+ *
689+ ******************************************************************************/
690
691-/*
692- * Time macros
693- */
694 #if SK_TICKS_PER_SEC == 100
695 #define SK_PNMI_HUNDREDS_SEC(t) (t)
696 #else
697-#define SK_PNMI_HUNDREDS_SEC(t) ((((unsigned long)t) * 100) / \
698- (SK_TICKS_PER_SEC))
699+#define SK_PNMI_HUNDREDS_SEC(t) ((((unsigned long)t)*100)/(SK_TICKS_PER_SEC))
700 #endif
701
702-/*
703- * New SkOsGetTime
704- */
705 #define SkOsGetTimeCurrent(pAC, pUsec) {\
706+ static struct timeval prev_t; \
707 struct timeval t;\
708 do_gettimeofday(&t);\
709- *pUsec = ((((t.tv_sec) * 1000000L)+t.tv_usec)/10000);\
710+ if (prev_t.tv_sec == t.tv_sec) { \
711+ if (prev_t.tv_usec > t.tv_usec) { \
712+ t.tv_usec = prev_t.tv_usec; \
713+ } else { \
714+ prev_t.tv_usec = t.tv_usec; \
715+ } \
716+ } else { \
717+ prev_t = t; \
718+ } \
719+ *pUsec = ((t.tv_sec*100L)+(t.tv_usec/10000));\
720 }
721
722+/******************************************************************************
723+ *
724+ * Linux specific IOCTL defines and typedefs
725+ *
726+ ******************************************************************************/
727
728-/*
729- * ioctl definitions
730- */
731-#define SK_IOCTL_BASE (SIOCDEVPRIVATE)
732-#define SK_IOCTL_GETMIB (SK_IOCTL_BASE + 0)
733-#define SK_IOCTL_SETMIB (SK_IOCTL_BASE + 1)
734-#define SK_IOCTL_PRESETMIB (SK_IOCTL_BASE + 2)
735-#define SK_IOCTL_GEN (SK_IOCTL_BASE + 3)
736-#define SK_IOCTL_DIAG (SK_IOCTL_BASE + 4)
737-
738-typedef struct s_IOCTL SK_GE_IOCTL;
739+#define SK_IOCTL_BASE (SIOCDEVPRIVATE)
740+#define SK_IOCTL_GETMIB (SK_IOCTL_BASE + 0)
741+#define SK_IOCTL_SETMIB (SK_IOCTL_BASE + 1)
742+#define SK_IOCTL_PRESETMIB (SK_IOCTL_BASE + 2)
743+#define SK_IOCTL_GEN (SK_IOCTL_BASE + 3)
744+#define SK_IOCTL_DIAG (SK_IOCTL_BASE + 4)
745
746+typedef struct s_IOCTL SK_GE_IOCTL;
747 struct s_IOCTL {
748 char __user * pData;
749 unsigned int Len;
750 };
751
752+/******************************************************************************
753+ *
754+ * Generic sizes and length definitions
755+ *
756+ ******************************************************************************/
757
758-/*
759- * define sizes of descriptor rings in bytes
760- */
761-
762-#define TX_RING_SIZE (8*1024)
763-#define RX_RING_SIZE (24*1024)
764-
765-/*
766- * Buffer size for ethernet packets
767- */
768-#define ETH_BUF_SIZE 1540
769-#define ETH_MAX_MTU 1514
770-#define ETH_MIN_MTU 60
771-#define ETH_MULTICAST_BIT 0x01
772-#define SK_JUMBO_MTU 9000
773-
774-/*
775- * transmit priority selects the queue: LOW=asynchron, HIGH=synchron
776- */
777-#define TX_PRIO_LOW 0
778-#define TX_PRIO_HIGH 1
779+#define TX_RING_SIZE (24*1024) /* GEnesis/Yukon */
780+#define RX_RING_SIZE (24*1024) /* GEnesis/Yukon */
781+#define RX_MAX_NBR_BUFFERS 128 /* Yukon-EC/-II */
782+#define TX_MAX_NBR_BUFFERS 128 /* Yukon-EC/-II */
783+#define MAXIMUM_LOW_ADDRESS 0xFFFFFFFF /* Max. low address */
784+
785+#define ETH_BUF_SIZE 1560 /* multiples of 8 bytes */
786+#define ETH_MAX_MTU 1514
787+#define ETH_MIN_MTU 60
788+#define ETH_MULTICAST_BIT 0x01
789+#define SK_JUMBO_MTU 9000
790+
791+#define TX_PRIO_LOW 0 /* asynchronous queue */
792+#define TX_PRIO_HIGH 1 /* synchronous queue */
793+#define DESCR_ALIGN 64 /* alignment of Rx/Tx descriptors */
794
795-/*
796- * alignment of rx/tx descriptors
797- */
798-#define DESCR_ALIGN 64
799+/******************************************************************************
800+ *
801+ * PNMI related definitions
802+ *
803+ ******************************************************************************/
804
805-/*
806- * definitions for pnmi. TODO
807- */
808 #define SK_DRIVER_RESET(pAC, IoC) 0
809 #define SK_DRIVER_SENDEVENT(pAC, IoC) 0
810 #define SK_DRIVER_SELFTEST(pAC, IoC) 0
811@@ -158,20 +250,16 @@
812 #define SK_DRIVER_SET_MTU(pAc,IoC,i,v) 0
813 #define SK_DRIVER_PRESET_MTU(pAc,IoC,i,v) 0
814
815-/*
816-** Interim definition of SK_DRV_TIMER placed in this file until
817-** common modules have been finalized
818-*/
819-#define SK_DRV_TIMER 11
820-#define SK_DRV_MODERATION_TIMER 1
821-#define SK_DRV_MODERATION_TIMER_LENGTH 1000000 /* 1 second */
822-#define SK_DRV_RX_CLEANUP_TIMER 2
823-#define SK_DRV_RX_CLEANUP_TIMER_LENGTH 1000000 /* 100 millisecs */
824
825-/*
826-** Definitions regarding transmitting frames
827-** any calculating any checksum.
828-*/
829+/******************************************************************************
830+ *
831+ * Various offsets and sizes
832+ *
833+ ******************************************************************************/
834+
835+#define SK_DRV_MODERATION_TIMER 1 /* id */
836+#define SK_DRV_MODERATION_TIMER_LENGTH 1 /* 1 second */
837+
838 #define C_LEN_ETHERMAC_HEADER_DEST_ADDR 6
839 #define C_LEN_ETHERMAC_HEADER_SRC_ADDR 6
840 #define C_LEN_ETHERMAC_HEADER_LENTYPE 2
841@@ -197,112 +285,448 @@
842 #define C_PROTO_ID_UDP 17 /* refer to RFC 790 or Stevens' */
843 #define C_PROTO_ID_TCP 6 /* TCP/IP illustrated for details */
844
845-/* TX and RX descriptors *****************************************************/
846+/******************************************************************************
847+ *
848+ * Tx and Rx descriptor definitions
849+ *
850+ ******************************************************************************/
851
852 typedef struct s_RxD RXD; /* the receive descriptor */
853-
854 struct s_RxD {
855- volatile SK_U32 RBControl; /* Receive Buffer Control */
856- SK_U32 VNextRxd; /* Next receive descriptor,low dword */
857- SK_U32 VDataLow; /* Receive buffer Addr, low dword */
858- SK_U32 VDataHigh; /* Receive buffer Addr, high dword */
859- SK_U32 FrameStat; /* Receive Frame Status word */
860- SK_U32 TimeStamp; /* Time stamp from XMAC */
861- SK_U32 TcpSums; /* TCP Sum 2 / TCP Sum 1 */
862- SK_U32 TcpSumStarts; /* TCP Sum Start 2 / TCP Sum Start 1 */
863- RXD *pNextRxd; /* Pointer to next Rxd */
864- struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */
865+ volatile SK_U32 RBControl; /* Receive Buffer Control */
866+ SK_U32 VNextRxd; /* Next receive descriptor,low dword */
867+ SK_U32 VDataLow; /* Receive buffer Addr, low dword */
868+ SK_U32 VDataHigh; /* Receive buffer Addr, high dword */
869+ SK_U32 FrameStat; /* Receive Frame Status word */
870+ SK_U32 TimeStamp; /* Time stamp from XMAC */
871+ SK_U32 TcpSums; /* TCP Sum 2 / TCP Sum 1 */
872+ SK_U32 TcpSumStarts; /* TCP Sum Start 2 / TCP Sum Start 1 */
873+ RXD *pNextRxd; /* Pointer to next Rxd */
874+ struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */
875 };
876
877 typedef struct s_TxD TXD; /* the transmit descriptor */
878-
879 struct s_TxD {
880- volatile SK_U32 TBControl; /* Transmit Buffer Control */
881- SK_U32 VNextTxd; /* Next transmit descriptor,low dword */
882- SK_U32 VDataLow; /* Transmit Buffer Addr, low dword */
883- SK_U32 VDataHigh; /* Transmit Buffer Addr, high dword */
884- SK_U32 FrameStat; /* Transmit Frame Status Word */
885- SK_U32 TcpSumOfs; /* Reserved / TCP Sum Offset */
886- SK_U16 TcpSumSt; /* TCP Sum Start */
887- SK_U16 TcpSumWr; /* TCP Sum Write */
888- SK_U32 TcpReserved; /* not used */
889- TXD *pNextTxd; /* Pointer to next Txd */
890- struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */
891+ volatile SK_U32 TBControl; /* Transmit Buffer Control */
892+ SK_U32 VNextTxd; /* Next transmit descriptor,low dword */
893+ SK_U32 VDataLow; /* Transmit Buffer Addr, low dword */
894+ SK_U32 VDataHigh; /* Transmit Buffer Addr, high dword */
895+ SK_U32 FrameStat; /* Transmit Frame Status Word */
896+ SK_U32 TcpSumOfs; /* Reserved / TCP Sum Offset */
897+ SK_U16 TcpSumSt; /* TCP Sum Start */
898+ SK_U16 TcpSumWr; /* TCP Sum Write */
899+ SK_U32 TcpReserved; /* not used */
900+ TXD *pNextTxd; /* Pointer to next Txd */
901+ struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */
902+};
903+
904+/******************************************************************************
905+ *
906+ * Generic Yukon-II defines
907+ *
908+ ******************************************************************************/
909+
910+#define LE_SIZE sizeof(SK_HWLE)
911+#define MAX_NUM_FRAGS (MAX_SKB_FRAGS + 1)
912+#define MIN_LEN_OF_LE_TAB 128
913+#define MAX_LEN_OF_LE_TAB 4096
914+#define MAX_UNUSED_RX_LE_WORKING 8
915+#ifdef MAX_FRAG_OVERHEAD
916+#undef MAX_FRAG_OVERHEAD
917+#define MAX_FRAG_OVERHEAD 4
918+#endif
919+// as we have a maximum of 16 physical fragments,
920+// maximum 1 ADDR64 per physical fragment
921+// maximum 4 LEs for VLAN, Csum, LargeSend, Packet
922+#define MIN_LE_FREE_REQUIRED ((16*2) + 4)
923+#define IS_GMAC(pAc) (!pAc->GIni.GIGenesis)
924+#ifdef USE_SYNC_TX_QUEUE
925+#define TXS_MAX_LE 256
926+#else /* !USE_SYNC_TX_QUEUE */
927+#define TXS_MAX_LE 0
928+#endif
929+
930+#define ETHER_MAC_HDR_LEN (6+6+2) // MAC SRC ADDR, MAC DST ADDR, TYPE
931+#define IP_HDR_LEN 20
932+#define TCP_CSUM_OFFS 0x10
933+#define UDP_CSUM_OFFS 0x06
934+#define TXA_MAX_LE 256
935+#define RX_MAX_LE 256
936+#define ST_MAX_LE (SK_MAX_MACS)*((3*RX_MAX_LE)+(TXA_MAX_LE)+(TXS_MAX_LE))
937+
938+#if (defined (Y2_RECOVERY) || defined (Y2_LE_CHECK))
939+/* event for recovery from tx hang or rx out of sync */
940+#define SK_DRV_RECOVER 17
941+#endif
942+/******************************************************************************
943+ *
944+ * Structures specific for Yukon-II
945+ *
946+ ******************************************************************************/
947+
948+typedef struct s_frag SK_FRAG;
949+struct s_frag {
950+ SK_FRAG *pNext;
951+ char *pVirt;
952+ SK_U64 pPhys;
953+ unsigned int FragLen;
954+};
955+
956+typedef struct s_packet SK_PACKET;
957+struct s_packet {
958+ /* Common infos: */
959+ SK_PACKET *pNext; /* pointer for packet queues */
960+ unsigned int PacketLen; /* length of packet */
961+ unsigned int NumFrags; /* nbr of fragments (for Rx always 1) */
962+ SK_FRAG *pFrag; /* fragment list */
963+ SK_FRAG FragArray[MAX_NUM_FRAGS]; /* TX fragment array */
964+ unsigned int NextLE; /* next LE to use for the next packet */
965+
966+ /* Private infos: */
967+ struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */
968+};
969+
970+typedef struct s_queue SK_PKT_QUEUE;
971+struct s_queue {
972+ SK_PACKET *pHead;
973+ SK_PACKET *pTail;
974+ spinlock_t QueueLock; /* serialize packet accesses */
975 };
976
977-/* Used interrupt bits in the interrupts source register *********************/
978+/*******************************************************************************
979+ *
980+ * Macros specific for Yukon-II queues
981+ *
982+ ******************************************************************************/
983+
984+#define IS_Q_EMPTY(pQueue) ((pQueue)->pHead != NULL) ? SK_FALSE : SK_TRUE
985+#define IS_Q_LOCKED(pQueue) spin_is_locked(&((pQueue)->QueueLock))
986+
987+#define PLAIN_POP_FIRST_PKT_FROM_QUEUE(pQueue, pPacket) { \
988+ if ((pQueue)->pHead != NULL) { \
989+ (pPacket) = (pQueue)->pHead; \
990+ (pQueue)->pHead = (pPacket)->pNext; \
991+ if ((pQueue)->pHead == NULL) { \
992+ (pQueue)->pTail = NULL; \
993+ } \
994+ (pPacket)->pNext = NULL; \
995+ } else { \
996+ (pPacket) = NULL; \
997+ } \
998+}
999+
1000+#define PLAIN_PUSH_PKT_AS_FIRST_IN_QUEUE(pQueue, pPacket) { \
1001+ if ((pQueue)->pHead != NULL) { \
1002+ (pPacket)->pNext = (pQueue)->pHead; \
1003+ } else { \
1004+ (pPacket)->pNext = NULL; \
1005+ (pQueue)->pTail = (pPacket); \
1006+ } \
1007+ (pQueue)->pHead = (pPacket); \
1008+}
1009+
1010+#define PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(pQueue, pPacket) { \
1011+ (pPacket)->pNext = NULL; \
1012+ if ((pQueue)->pTail != NULL) { \
1013+ (pQueue)->pTail->pNext = (pPacket); \
1014+ } else { \
1015+ (pQueue)->pHead = (pPacket); \
1016+ } \
1017+ (pQueue)->pTail = (pPacket); \
1018+}
1019+
1020+#define PLAIN_PUSH_MULTIPLE_PKT_AS_LAST_IN_QUEUE(pQueue,pPktGrpStart,pPktGrpEnd) { \
1021+ if ((pPktGrpStart) != NULL) { \
1022+ if ((pQueue)->pTail != NULL) { \
1023+ (pQueue)->pTail->pNext = (pPktGrpStart); \
1024+ } else { \
1025+ (pQueue)->pHead = (pPktGrpStart); \
1026+ } \
1027+ (pQueue)->pTail = (pPktGrpEnd); \
1028+ } \
1029+}
1030+
1031+/* Required: 'Flags' */
1032+#define POP_FIRST_PKT_FROM_QUEUE(pQueue, pPacket) { \
1033+ spin_lock_irqsave(&((pQueue)->QueueLock), Flags); \
1034+ if ((pQueue)->pHead != NULL) { \
1035+ (pPacket) = (pQueue)->pHead; \
1036+ (pQueue)->pHead = (pPacket)->pNext; \
1037+ if ((pQueue)->pHead == NULL) { \
1038+ (pQueue)->pTail = NULL; \
1039+ } \
1040+ (pPacket)->pNext = NULL; \
1041+ } else { \
1042+ (pPacket) = NULL; \
1043+ } \
1044+ spin_unlock_irqrestore(&((pQueue)->QueueLock), Flags); \
1045+}
1046+
1047+/* Required: 'Flags' */
1048+#define PUSH_PKT_AS_FIRST_IN_QUEUE(pQueue, pPacket) { \
1049+ spin_lock_irqsave(&(pQueue)->QueueLock, Flags); \
1050+ if ((pQueue)->pHead != NULL) { \
1051+ (pPacket)->pNext = (pQueue)->pHead; \
1052+ } else { \
1053+ (pPacket)->pNext = NULL; \
1054+ (pQueue)->pTail = (pPacket); \
1055+ } \
1056+ (pQueue)->pHead = (pPacket); \
1057+ spin_unlock_irqrestore(&(pQueue)->QueueLock, Flags); \
1058+}
1059+
1060+/* Required: 'Flags' */
1061+#define PUSH_PKT_AS_LAST_IN_QUEUE(pQueue, pPacket) { \
1062+ (pPacket)->pNext = NULL; \
1063+ spin_lock_irqsave(&(pQueue)->QueueLock, Flags); \
1064+ if ((pQueue)->pTail != NULL) { \
1065+ (pQueue)->pTail->pNext = (pPacket); \
1066+ } else { \
1067+ (pQueue)->pHead = (pPacket); \
1068+ } \
1069+ (pQueue)->pTail = (pPacket); \
1070+ spin_unlock_irqrestore(&(pQueue)->QueueLock, Flags); \
1071+}
1072+
1073+/* Required: 'Flags' */
1074+#define PUSH_MULTIPLE_PKT_AS_LAST_IN_QUEUE(pQueue,pPktGrpStart,pPktGrpEnd) { \
1075+ if ((pPktGrpStart) != NULL) { \
1076+ spin_lock_irqsave(&(pQueue)->QueueLock, Flags); \
1077+ if ((pQueue)->pTail != NULL) { \
1078+ (pQueue)->pTail->pNext = (pPktGrpStart); \
1079+ } else { \
1080+ (pQueue)->pHead = (pPktGrpStart); \
1081+ } \
1082+ (pQueue)->pTail = (pPktGrpEnd); \
1083+ spin_unlock_irqrestore(&(pQueue)->QueueLock, Flags); \
1084+ } \
1085+}
1086+
1087+/*
1088+ *Check if the low address (32 bit) is near the 4G limit or over it.
1089+ * Set the high address to a wrong value.
1090+ * Doing so we force to write the ADDR64 LE.
1091+ */
1092+#define CHECK_LOW_ADDRESS( _HighAddress, _LowAddress , _Length) { \
1093+ if ((~0-_LowAddress) <_Length) { \
1094+ _HighAddress= MAXIMUM_LOW_ADDRESS; \
1095+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, \
1096+ ("High Address must be set for HW. LowAddr = %d Length = %d\n", \
1097+ _LowAddress, _Length)); \
1098+ } \
1099+}
1100+
1101+/*******************************************************************************
1102+ *
1103+ * Macros specific for Yukon-II queues (tist)
1104+ *
1105+ ******************************************************************************/
1106+
1107+#ifdef USE_TIST_FOR_RESET
1108+/* port is fully operational */
1109+#define SK_PSTATE_NOT_WAITING_FOR_TIST 0
1110+/* port in reset until any tist LE */
1111+#define SK_PSTATE_WAITING_FOR_ANY_TIST BIT_0
1112+/* port in reset until timer reaches pAC->MinTistLo */
1113+#define SK_PSTATE_WAITING_FOR_SPECIFIC_TIST BIT_1
1114+#define SK_PSTATE_PORT_SHIFT 4
1115+#define SK_PSTATE_PORT_MASK ((1 << SK_PSTATE_PORT_SHIFT) - 1)
1116+
1117+/* use this + Port to build OP_MOD_TXINDEX_NO_PORT_A|B */
1118+#define OP_MOD_TXINDEX 0x71
1119+/* opcode for a TX_INDEX LE in which Port A has to be ignored */
1120+#define OP_MOD_TXINDEX_NO_PORT_A 0x71
1121+/* opcode for a TX_INDEX LE in which Port B has to be ignored */
1122+#define OP_MOD_TXINDEX_NO_PORT_B 0x72
1123+/* opcode for LE to be ignored because port is still in reset */
1124+#define OP_MOD_LE 0x7F
1125+
1126+/* set tist wait mode Bit for port */
1127+#define SK_SET_WAIT_BIT_FOR_PORT(pAC, Bit, Port) \
1128+ { \
1129+ (pAC)->AdapterResetState |= ((Bit) << (SK_PSTATE_PORT_SHIFT * Port)); \
1130+ }
1131+
1132+/* reset tist waiting for specified port */
1133+#define SK_CLR_STATE_FOR_PORT(pAC, Port) \
1134+ { \
1135+ (pAC)->AdapterResetState &= \
1136+ ~(SK_PSTATE_PORT_MASK << (SK_PSTATE_PORT_SHIFT * Port)); \
1137+ }
1138+
1139+/* return SK_TRUE when port is in reset waiting for tist */
1140+#define SK_PORT_WAITING_FOR_TIST(pAC, Port) \
1141+ ((((pAC)->AdapterResetState >> (SK_PSTATE_PORT_SHIFT * Port)) & \
1142+ SK_PSTATE_PORT_MASK) != SK_PSTATE_NOT_WAITING_FOR_TIST)
1143+
1144+/* return SK_TRUE when port is in reset waiting for any tist */
1145+#define SK_PORT_WAITING_FOR_ANY_TIST(pAC, Port) \
1146+ ((((pAC)->AdapterResetState >> (SK_PSTATE_PORT_SHIFT * Port)) & \
1147+ SK_PSTATE_WAITING_FOR_ANY_TIST) == SK_PSTATE_WAITING_FOR_ANY_TIST)
1148+
1149+/* return SK_TRUE when port is in reset waiting for a specific tist */
1150+#define SK_PORT_WAITING_FOR_SPECIFIC_TIST(pAC, Port) \
1151+ ((((pAC)->AdapterResetState >> (SK_PSTATE_PORT_SHIFT * Port)) & \
1152+ SK_PSTATE_WAITING_FOR_SPECIFIC_TIST) == \
1153+ SK_PSTATE_WAITING_FOR_SPECIFIC_TIST)
1154+
1155+/* return whether adapter is expecting a tist LE */
1156+#define SK_ADAPTER_WAITING_FOR_TIST(pAC) ((pAC)->AdapterResetState != 0)
1157+
1158+/* enable timestamp timer and force creation of tist LEs */
1159+#define Y2_ENABLE_TIST(IoC) \
1160+ SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8) GMT_ST_START)
1161+
1162+/* disable timestamp timer and stop creation of tist LEs */
1163+#define Y2_DISABLE_TIST(IoC) \
1164+ SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8) GMT_ST_STOP)
1165+
1166+/* get current value of timestamp timer */
1167+#define Y2_GET_TIST_LOW_VAL(IoC, pVal) \
1168+ SK_IN32(IoC, GMAC_TI_ST_VAL, pVal)
1169
1170-#define DRIVER_IRQS ((IS_IRQ_SW) | \
1171- (IS_R1_F) |(IS_R2_F) | \
1172- (IS_XS1_F) |(IS_XA1_F) | \
1173- (IS_XS2_F) |(IS_XA2_F))
1174-
1175-#define SPECIAL_IRQS ((IS_HW_ERR) |(IS_I2C_READY) | \
1176- (IS_EXT_REG) |(IS_TIMINT) | \
1177- (IS_PA_TO_RX1) |(IS_PA_TO_RX2) | \
1178- (IS_PA_TO_TX1) |(IS_PA_TO_TX2) | \
1179- (IS_MAC1) |(IS_LNK_SYNC_M1)| \
1180- (IS_MAC2) |(IS_LNK_SYNC_M2)| \
1181- (IS_R1_C) |(IS_R2_C) | \
1182- (IS_XS1_C) |(IS_XA1_C) | \
1183- (IS_XS2_C) |(IS_XA2_C))
1184-
1185-#define IRQ_MASK ((IS_IRQ_SW) | \
1186- (IS_R1_B) |(IS_R1_F) |(IS_R2_B) |(IS_R2_F) | \
1187- (IS_XS1_B) |(IS_XS1_F) |(IS_XA1_B)|(IS_XA1_F)| \
1188- (IS_XS2_B) |(IS_XS2_F) |(IS_XA2_B)|(IS_XA2_F)| \
1189- (IS_HW_ERR) |(IS_I2C_READY)| \
1190- (IS_EXT_REG) |(IS_TIMINT) | \
1191- (IS_PA_TO_RX1) |(IS_PA_TO_RX2)| \
1192- (IS_PA_TO_TX1) |(IS_PA_TO_TX2)| \
1193- (IS_MAC1) |(IS_MAC2) | \
1194- (IS_R1_C) |(IS_R2_C) | \
1195- (IS_XS1_C) |(IS_XA1_C) | \
1196- (IS_XS2_C) |(IS_XA2_C))
1197+#endif
1198+
1199+
1200+/*******************************************************************************
1201+ *
1202+ * Used interrupt bits in the interrupts source register
1203+ *
1204+ ******************************************************************************/
1205
1206-#define IRQ_HWE_MASK (IS_ERR_MSK) /* enable all HW irqs */
1207+#define DRIVER_IRQS ((IS_IRQ_SW) | \
1208+ (IS_R1_F) | (IS_R2_F) | \
1209+ (IS_XS1_F) | (IS_XA1_F) | \
1210+ (IS_XS2_F) | (IS_XA2_F))
1211+
1212+#define TX_COMPL_IRQS ((IS_XS1_B) | (IS_XS1_F) | \
1213+ (IS_XA1_B) | (IS_XA1_F) | \
1214+ (IS_XS2_B) | (IS_XS2_F) | \
1215+ (IS_XA2_B) | (IS_XA2_F))
1216+
1217+#define NAPI_DRV_IRQS ((IS_R1_F) | (IS_R2_F) | \
1218+ (IS_XS1_F) | (IS_XA1_F)| \
1219+ (IS_XS2_F) | (IS_XA2_F))
1220+
1221+#define Y2_DRIVER_IRQS ((Y2_IS_STAT_BMU) | (Y2_IS_IRQ_SW) | (Y2_IS_POLL_CHK))
1222+
1223+#define SPECIAL_IRQS ((IS_HW_ERR) |(IS_I2C_READY) | \
1224+ (IS_EXT_REG) |(IS_TIMINT) | \
1225+ (IS_PA_TO_RX1) |(IS_PA_TO_RX2) | \
1226+ (IS_PA_TO_TX1) |(IS_PA_TO_TX2) | \
1227+ (IS_MAC1) |(IS_LNK_SYNC_M1)| \
1228+ (IS_MAC2) |(IS_LNK_SYNC_M2)| \
1229+ (IS_R1_C) |(IS_R2_C) | \
1230+ (IS_XS1_C) |(IS_XA1_C) | \
1231+ (IS_XS2_C) |(IS_XA2_C))
1232+
1233+#define Y2_SPECIAL_IRQS ((Y2_IS_HW_ERR) |(Y2_IS_ASF) | \
1234+ (Y2_IS_TWSI_RDY) |(Y2_IS_TIMINT) | \
1235+ (Y2_IS_IRQ_PHY2) |(Y2_IS_IRQ_MAC2) | \
1236+ (Y2_IS_CHK_RX2) |(Y2_IS_CHK_TXS2) | \
1237+ (Y2_IS_CHK_TXA2) |(Y2_IS_IRQ_PHY1) | \
1238+ (Y2_IS_IRQ_MAC1) |(Y2_IS_CHK_RX1) | \
1239+ (Y2_IS_CHK_TXS1) |(Y2_IS_CHK_TXA1))
1240+
1241+#define IRQ_MASK ((IS_IRQ_SW) | \
1242+ (IS_R1_F) |(IS_R2_F) | \
1243+ (IS_XS1_F) |(IS_XA1_F) | \
1244+ (IS_XS2_F) |(IS_XA2_F) | \
1245+ (IS_HW_ERR) |(IS_I2C_READY)| \
1246+ (IS_EXT_REG) |(IS_TIMINT) | \
1247+ (IS_PA_TO_RX1) |(IS_PA_TO_RX2)| \
1248+ (IS_PA_TO_TX1) |(IS_PA_TO_TX2)| \
1249+ (IS_MAC1) |(IS_MAC2) | \
1250+ (IS_R1_C) |(IS_R2_C) | \
1251+ (IS_XS1_C) |(IS_XA1_C) | \
1252+ (IS_XS2_C) |(IS_XA2_C))
1253+
1254+#define Y2_IRQ_MASK ((Y2_DRIVER_IRQS) | (Y2_SPECIAL_IRQS))
1255+
1256+#define IRQ_HWE_MASK (IS_ERR_MSK) /* enable all HW irqs */
1257+#define Y2_IRQ_HWE_MASK (Y2_HWE_ALL_MSK) /* enable all HW irqs */
1258
1259 typedef struct s_DevNet DEV_NET;
1260
1261 struct s_DevNet {
1262- int PortNr;
1263- int NetNr;
1264- SK_AC *pAC;
1265+ struct proc_dir_entry *proc;
1266+ int PortNr;
1267+ int NetNr;
1268+ char InitialDevName[20];
1269+ char CurrentName[20];
1270+ SK_BOOL NetConsoleMode;
1271+#ifdef Y2_RECOVERY
1272+ struct timer_list KernelTimer; /* Kernel timer struct */
1273+ int TransmitTimeoutTimer; /* Transmit timer */
1274+ SK_BOOL TimerExpired; /* Transmit timer */
1275+ SK_BOOL InRecover; /* Recover flag */
1276+#ifdef Y2_RX_CHECK
1277+ SK_U32 PreviousMACFifoRP; /* Backup of the FRP */
1278+ SK_U32 PreviousMACFifoRLev; /* Backup of the FRL */
1279+ SK_U32 PreviousRXFifoRP; /* Backup of the RX FRP */
1280+ SK_U8 PreviousRXFifoRLev; /* Backup of the RX FRL */
1281+ SK_U32 LastJiffies; /* Backup of the jiffies*/
1282+#endif
1283+#endif
1284+ SK_AC *pAC;
1285+ struct timer_list ProcfsTimer; /* Procfs timer struct */
1286+
1287 };
1288
1289-typedef struct s_TxPort TX_PORT;
1290+/*******************************************************************************
1291+ *
1292+ * Rx/Tx Port structures
1293+ *
1294+ ******************************************************************************/
1295
1296-struct s_TxPort {
1297- /* the transmit descriptor rings */
1298- caddr_t pTxDescrRing; /* descriptor area memory */
1299- SK_U64 VTxDescrRing; /* descr. area bus virt. addr. */
1300- TXD *pTxdRingHead; /* Head of Tx rings */
1301- TXD *pTxdRingTail; /* Tail of Tx rings */
1302- TXD *pTxdRingPrev; /* descriptor sent previously */
1303- int TxdRingFree; /* # of free entrys */
1304- spinlock_t TxDesRingLock; /* serialize descriptor accesses */
1305- SK_IOC HwAddr; /* bmu registers address */
1306- int PortIndex; /* index number of port (0 or 1) */
1307+typedef struct s_TxPort TX_PORT;
1308+struct s_TxPort { /* the transmit descriptor rings */
1309+ caddr_t pTxDescrRing; /* descriptor area memory */
1310+ SK_U64 VTxDescrRing; /* descr. area bus virt. addr. */
1311+ TXD *pTxdRingHead; /* Head of Tx rings */
1312+ TXD *pTxdRingTail; /* Tail of Tx rings */
1313+ TXD *pTxdRingPrev; /* descriptor sent previously */
1314+ int TxdRingPrevFree;/* previously # of free entrys */
1315+ int TxdRingFree; /* # of free entrys */
1316+ spinlock_t TxDesRingLock; /* serialize descriptor accesses */
1317+ caddr_t HwAddr; /* bmu registers address */
1318+ int PortIndex; /* index number of port (0 or 1) */
1319+ SK_PACKET *TransmitPacketTable;
1320+ SK_LE_TABLE TxALET; /* tx (async) list element table */
1321+ SK_LE_TABLE TxSLET; /* tx (sync) list element table */
1322+ SK_PKT_QUEUE TxQ_free;
1323+ SK_PKT_QUEUE TxAQ_waiting;
1324+ SK_PKT_QUEUE TxSQ_waiting;
1325+ SK_PKT_QUEUE TxAQ_working;
1326+ SK_PKT_QUEUE TxSQ_working;
1327+ unsigned LastDone;
1328 };
1329
1330-typedef struct s_RxPort RX_PORT;
1331-
1332-struct s_RxPort {
1333- /* the receive descriptor rings */
1334- caddr_t pRxDescrRing; /* descriptor area memory */
1335- SK_U64 VRxDescrRing; /* descr. area bus virt. addr. */
1336- RXD *pRxdRingHead; /* Head of Rx rings */
1337- RXD *pRxdRingTail; /* Tail of Rx rings */
1338- RXD *pRxdRingPrev; /* descriptor given to BMU previously */
1339- int RxdRingFree; /* # of free entrys */
1340- int RxCsum; /* use receive checksum hardware */
1341- spinlock_t RxDesRingLock; /* serialize descriptor accesses */
1342- int RxFillLimit; /* limit for buffers in ring */
1343- SK_IOC HwAddr; /* bmu registers address */
1344- int PortIndex; /* index number of port (0 or 1) */
1345+typedef struct s_RxPort RX_PORT;
1346+struct s_RxPort { /* the receive descriptor rings */
1347+ caddr_t pRxDescrRing; /* descriptor area memory */
1348+ SK_U64 VRxDescrRing; /* descr. area bus virt. addr. */
1349+ RXD *pRxdRingHead; /* Head of Rx rings */
1350+ RXD *pRxdRingTail; /* Tail of Rx rings */
1351+ RXD *pRxdRingPrev; /* descr given to BMU previously */
1352+ int RxdRingFree; /* # of free entrys */
1353+ spinlock_t RxDesRingLock; /* serialize descriptor accesses */
1354+ int RxFillLimit; /* limit for buffers in ring */
1355+ caddr_t HwAddr; /* bmu registers address */
1356+ int PortIndex; /* index number of port (0 or 1) */
1357+ SK_BOOL UseRxCsum; /* use Rx checksumming (yes/no) */
1358+ SK_PACKET *ReceivePacketTable;
1359+ SK_LE_TABLE RxLET; /* rx list element table */
1360+ SK_PKT_QUEUE RxQ_working;
1361+ SK_PKT_QUEUE RxQ_waiting;
1362+ int RxBufSize;
1363 };
1364
1365-/* Definitions needed for interrupt moderation *******************************/
1366+/*******************************************************************************
1367+ *
1368+ * Interrupt masks used in combination with interrupt moderation
1369+ *
1370+ ******************************************************************************/
1371
1372 #define IRQ_EOF_AS_TX ((IS_XA1_F) | (IS_XA2_F))
1373 #define IRQ_EOF_SY_TX ((IS_XS1_F) | (IS_XS2_F))
1374@@ -314,134 +738,157 @@
1375 #define IRQ_MASK_SP_TX ((SPECIAL_IRQS) | (IRQ_MASK_TX_ONLY))
1376 #define IRQ_MASK_RX_TX_SP ((SPECIAL_IRQS) | (IRQ_MASK_TX_RX))
1377
1378-#define C_INT_MOD_NONE 1
1379-#define C_INT_MOD_STATIC 2
1380-#define C_INT_MOD_DYNAMIC 4
1381-
1382-#define C_CLK_FREQ_GENESIS 53215000 /* shorter: 53.125 MHz */
1383-#define C_CLK_FREQ_YUKON 78215000 /* shorter: 78.125 MHz */
1384-
1385-#define C_INTS_PER_SEC_DEFAULT 2000
1386-#define C_INT_MOD_ENABLE_PERCENTAGE 50 /* if higher 50% enable */
1387-#define C_INT_MOD_DISABLE_PERCENTAGE 50 /* if lower 50% disable */
1388-#define C_INT_MOD_IPS_LOWER_RANGE 30
1389-#define C_INT_MOD_IPS_UPPER_RANGE 40000
1390-
1391-
1392-typedef struct s_DynIrqModInfo DIM_INFO;
1393-struct s_DynIrqModInfo {
1394- unsigned long PrevTimeVal;
1395- unsigned int PrevSysLoad;
1396- unsigned int PrevUsedTime;
1397- unsigned int PrevTotalTime;
1398- int PrevUsedDescrRatio;
1399- int NbrProcessedDescr;
1400- SK_U64 PrevPort0RxIntrCts;
1401- SK_U64 PrevPort1RxIntrCts;
1402- SK_U64 PrevPort0TxIntrCts;
1403- SK_U64 PrevPort1TxIntrCts;
1404- SK_BOOL ModJustEnabled; /* Moderation just enabled yes/no */
1405-
1406- int MaxModIntsPerSec; /* Moderation Threshold */
1407- int MaxModIntsPerSecUpperLimit; /* Upper limit for DIM */
1408- int MaxModIntsPerSecLowerLimit; /* Lower limit for DIM */
1409-
1410- long MaskIrqModeration; /* ModIrqType (eg. 'TxRx') */
1411- SK_BOOL DisplayStats; /* Stats yes/no */
1412- SK_BOOL AutoSizing; /* Resize DIM-timer on/off */
1413- int IntModTypeSelect; /* EnableIntMod (eg. 'dynamic') */
1414+#define IRQ_MASK_Y2_TX_ONLY (Y2_IS_STAT_BMU)
1415+#define IRQ_MASK_Y2_RX_ONLY (Y2_IS_STAT_BMU)
1416+#define IRQ_MASK_Y2_SP_ONLY (SPECIAL_IRQS)
1417+#define IRQ_MASK_Y2_TX_RX ((IRQ_MASK_TX_ONLY)| (IRQ_MASK_RX_ONLY))
1418+#define IRQ_MASK_Y2_SP_RX ((SPECIAL_IRQS) | (IRQ_MASK_RX_ONLY))
1419+#define IRQ_MASK_Y2_SP_TX ((SPECIAL_IRQS) | (IRQ_MASK_TX_ONLY))
1420+#define IRQ_MASK_Y2_RX_TX_SP ((SPECIAL_IRQS) | (IRQ_MASK_TX_RX))
1421
1422- SK_TIMER ModTimer; /* just some timer */
1423-};
1424+/*******************************************************************************
1425+ *
1426+ * Defines and typedefs regarding interrupt moderation
1427+ *
1428+ ******************************************************************************/
1429
1430-typedef struct s_PerStrm PER_STRM;
1431+#define C_INT_MOD_NONE 1
1432+#define C_INT_MOD_STATIC 2
1433+#define C_INT_MOD_DYNAMIC 4
1434+
1435+#define C_CLK_FREQ_GENESIS 53215000 /* or: 53.125 MHz */
1436+#define C_CLK_FREQ_YUKON 78215000 /* or: 78.125 MHz */
1437+#define C_CLK_FREQ_YUKON_EC 125000000 /* or: 125.000 MHz */
1438+
1439+#define C_Y2_INTS_PER_SEC_DEFAULT 5000
1440+#define C_INTS_PER_SEC_DEFAULT 2000
1441+#define C_INT_MOD_IPS_LOWER_RANGE 30 /* in IRQs/second */
1442+#define C_INT_MOD_IPS_UPPER_RANGE 40000 /* in IRQs/second */
1443+
1444+typedef struct s_DynIrqModInfo {
1445+ SK_U64 PrevPort0RxIntrCts;
1446+ SK_U64 PrevPort1RxIntrCts;
1447+ SK_U64 PrevPort0TxIntrCts;
1448+ SK_U64 PrevPort1TxIntrCts;
1449+ SK_U64 PrevPort0StatusLeIntrCts;
1450+ SK_U64 PrevPort1StatusLeIntrCts;
1451+ int MaxModIntsPerSec; /* Moderation Threshold */
1452+ int MaxModIntsPerSecUpperLimit; /* Upper limit for DIM */
1453+ int MaxModIntsPerSecLowerLimit; /* Lower limit for DIM */
1454+ long MaskIrqModeration; /* IRQ Mask (eg. 'TxRx') */
1455+ int IntModTypeSelect; /* Type (eg. 'dynamic') */
1456+ int DynIrqModSampleInterval; /* expressed in seconds! */
1457+ SK_TIMER ModTimer; /* Timer for dynamic mod. */
1458+} DIM_INFO;
1459
1460-#define SK_ALLOC_IRQ 0x00000001
1461+/*******************************************************************************
1462+ *
1463+ * Defines and typedefs regarding wake-on-lan
1464+ *
1465+ ******************************************************************************/
1466+
1467+typedef struct s_WakeOnLanInfo {
1468+ SK_U32 SupportedWolOptions; /* e.g. WAKE_PHY... */
1469+ SK_U32 ConfiguredWolOptions; /* e.g. WAKE_PHY... */
1470+} WOL_INFO;
1471
1472-#ifdef SK_DIAG_SUPPORT
1473+#define SK_ALLOC_IRQ 0x00000001
1474 #define DIAG_ACTIVE 1
1475 #define DIAG_NOTACTIVE 0
1476-#endif
1477
1478 /****************************************************************************
1479+ *
1480 * Per board structure / Adapter Context structure:
1481- * Allocated within attach(9e) and freed within detach(9e).
1482- * Contains all 'per device' necessary handles, flags, locks etc.:
1483- */
1484+ * Contains all 'per device' necessary handles, flags, locks etc.:
1485+ *
1486+ ******************************************************************************/
1487+
1488 struct s_AC {
1489- SK_GEINIT GIni; /* GE init struct */
1490- SK_PNMI Pnmi; /* PNMI data struct */
1491- SK_VPD vpd; /* vpd data struct */
1492- SK_QUEUE Event; /* Event queue */
1493- SK_HWT Hwt; /* Hardware Timer control struct */
1494- SK_TIMCTRL Tim; /* Software Timer control struct */
1495- SK_I2C I2c; /* I2C relevant data structure */
1496- SK_ADDR Addr; /* for Address module */
1497- SK_CSUM Csum; /* for checksum module */
1498- SK_RLMT Rlmt; /* for rlmt module */
1499- spinlock_t SlowPathLock; /* Normal IRQ lock */
1500- struct timer_list BlinkTimer; /* for LED blinking */
1501- int LedsOn;
1502- SK_PNMI_STRUCT_DATA PnmiStruct; /* structure to get all Pnmi-Data */
1503- int RlmtMode; /* link check mode to set */
1504- int RlmtNets; /* Number of nets */
1505-
1506- SK_IOC IoBase; /* register set of adapter */
1507- int BoardLevel; /* level of active hw init (0-2) */
1508-
1509- SK_U32 AllocFlag; /* flag allocation of resources */
1510- struct pci_dev *PciDev; /* for access to pci config space */
1511- struct SK_NET_DEVICE *dev[2]; /* pointer to device struct */
1512-
1513- int RxBufSize; /* length of receive buffers */
1514- struct net_device_stats stats; /* linux 'netstat -i' statistics */
1515- int Index; /* internal board index number */
1516-
1517- /* adapter RAM sizes for queues of active port */
1518- int RxQueueSize; /* memory used for receive queue */
1519- int TxSQueueSize; /* memory used for sync. tx queue */
1520- int TxAQueueSize; /* memory used for async. tx queue */
1521-
1522- int PromiscCount; /* promiscuous mode counter */
1523- int AllMultiCount; /* allmulticast mode counter */
1524- int MulticCount; /* number of different MC */
1525- /* addresses for this board */
1526- /* (may be more than HW can)*/
1527-
1528- int HWRevision; /* Hardware revision */
1529- int ActivePort; /* the active XMAC port */
1530- int MaxPorts; /* number of activated ports */
1531- int TxDescrPerRing; /* # of descriptors per tx ring */
1532- int RxDescrPerRing; /* # of descriptors per rx ring */
1533-
1534- caddr_t pDescrMem; /* Pointer to the descriptor area */
1535- dma_addr_t pDescrMemDMA; /* PCI DMA address of area */
1536-
1537- /* the port structures with descriptor rings */
1538- TX_PORT TxPort[SK_MAX_MACS][2];
1539- RX_PORT RxPort[SK_MAX_MACS];
1540-
1541- SK_BOOL CheckQueue; /* check event queue soon */
1542- SK_TIMER DrvCleanupTimer;/* to check for pending descriptors */
1543- DIM_INFO DynIrqModInfo; /* all data related to DIM */
1544-
1545- /* Only for tests */
1546- int PortDown;
1547- int ChipsetType; /* Chipset family type
1548- * 0 == Genesis family support
1549- * 1 == Yukon family support
1550- */
1551-#ifdef SK_DIAG_SUPPORT
1552- SK_U32 DiagModeActive; /* is diag active? */
1553- SK_BOOL DiagFlowCtrl; /* for control purposes */
1554- SK_PNMI_STRUCT_DATA PnmiBackup; /* backup structure for all Pnmi-Data */
1555- SK_BOOL WasIfUp[SK_MAX_MACS]; /* for OpenClose while
1556- * DIAG is busy with NIC
1557- */
1558+ SK_GEINIT GIni; /* GE init struct */
1559+ SK_PNMI Pnmi; /* PNMI data struct */
1560+ SK_VPD vpd; /* vpd data struct */
1561+ SK_QUEUE Event; /* Event queue */
1562+ SK_HWT Hwt; /* Hardware Timer ctrl struct */
1563+ SK_TIMCTRL Tim; /* Software Timer ctrl struct */
1564+ SK_I2C I2c; /* I2C relevant data structure*/
1565+ SK_ADDR Addr; /* for Address module */
1566+ SK_CSUM Csum; /* for checksum module */
1567+ SK_RLMT Rlmt; /* for rlmt module */
1568+#ifdef SK_ASF
1569+ SK_ASF_DATA AsfData;
1570+ unsigned char IpAddr[4];
1571+#endif
1572+ spinlock_t SlowPathLock; /* Normal IRQ lock */
1573+ spinlock_t InitLock; /* Init lock */
1574+ spinlock_t TxQueueLock; /* TX Queue lock */
1575+ SK_PNMI_STRUCT_DATA PnmiStruct; /* struct for all Pnmi-Data */
1576+ int RlmtMode; /* link check mode to set */
1577+ int RlmtNets; /* Number of nets */
1578+ SK_IOC IoBase; /* register set of adapter */
1579+ int BoardLevel; /* level of hw init (0-2) */
1580+ char DeviceStr[80]; /* adapter string from vpd */
1581+ SK_U32 AllocFlag; /* alloc flag of resources */
1582+ struct pci_dev *PciDev; /* for access to pci cfg space*/
1583+ SK_U32 PciDevId; /* pci device id */
1584+ struct SK_NET_DEVICE *dev[2]; /* pointer to device struct */
1585+ char Name[30]; /* driver name */
1586+ struct SK_NET_DEVICE *Next; /* link all devs for cleanup */
1587+ struct net_device_stats stats; /* linux 'netstat -i' stats */
1588+ int Index; /* internal board idx number */
1589+ int RxQueueSize; /* memory used for RX queue */
1590+ int TxSQueueSize; /* memory used for TXS queue */
1591+ int TxAQueueSize; /* memory used for TXA queue */
1592+ int PromiscCount; /* promiscuous mode counter */
1593+ int AllMultiCount; /* allmulticast mode counter */
1594+ int MulticCount; /* number of MC addresses used*/
1595+ int HWRevision; /* Hardware revision */
1596+ int ActivePort; /* the active XMAC port */
1597+ int MaxPorts; /* number of activated ports */
1598+ int TxDescrPerRing;/* # of descriptors TX ring */
1599+ int RxDescrPerRing;/* # of descriptors RX ring */
1600+ caddr_t pDescrMem; /* Ptr to the descriptor area */
1601+ dma_addr_t pDescrMemDMA; /* PCI DMA address of area */
1602+ SK_U32 PciState[16]; /* PCI state */
1603+ TX_PORT TxPort[SK_MAX_MACS][2];
1604+ RX_PORT RxPort[SK_MAX_MACS];
1605+ SK_LE_TABLE StatusLETable;
1606+ unsigned SizeOfAlignedLETables;
1607+ spinlock_t SetPutIndexLock;
1608+ int MaxUnusedRxLeWorking;
1609+ int InterfaceUp[2];
1610+ unsigned int CsOfs1; /* for checksum calculation */
1611+ unsigned int CsOfs2; /* for checksum calculation */
1612+ SK_U32 CsOfs; /* for checksum calculation */
1613+ SK_BOOL CheckQueue; /* check event queue soon */
1614+ DIM_INFO DynIrqModInfo; /* all data related to IntMod */
1615+ WOL_INFO WolInfo; /* all info regarding WOL */
1616+ int ChipsetType; /* 0=GENESIS; 1=Yukon */
1617+ SK_BOOL LowLatency; /* LowLatency optimization on?*/
1618+ SK_U32 DiagModeActive;/* is diag active? */
1619+ SK_BOOL DiagFlowCtrl; /* for control purposes */
1620+ SK_PNMI_STRUCT_DATA PnmiBackup; /* backup structure for PNMI */
1621+ SK_BOOL WasIfUp[SK_MAX_MACS];
1622+#ifdef USE_TIST_FOR_RESET
1623+ int AdapterResetState;
1624+ SK_U32 MinTistLo;
1625+ SK_U32 MinTistHi;
1626+#endif
1627+#ifdef Y2_RECOVERY
1628+ int LastPort; /* port for curr. handled rx */
1629+ int LastOpc; /* last rx LEs opcode */
1630+#endif
1631+#ifdef Y2_SYNC_CHECK
1632+ unsigned long FramesWithoutSyncCheck; /* since last check */
1633 #endif
1634-
1635 };
1636
1637
1638-#endif /* __INC_SKDRV2ND_H */
1639+
1640+#endif
1641+
1642+/*******************************************************************************
1643+ *
1644+ * End of file
1645+ *
1646+ ******************************************************************************/
1647
1648diff -ruN linux/drivers/net/sk98lin/h/skerror.h linux-new/drivers/net/sk98lin/h/skerror.h
1649--- linux/drivers/net/sk98lin/h/skerror.h 2007-01-02 23:21:17.000000000 +0100
1650+++ linux-new/drivers/net/sk98lin/h/skerror.h 2006-10-13 11:18:49.000000000 +0200
1651@@ -2,23 +2,24 @@
1652 *
1653 * Name: skerror.h
1654 * Project: Gigabit Ethernet Adapters, Common Modules
1655- * Version: $Revision$
1656- * Date: $Date$
1657+ * Version: $Revision$
1658+ * Date: $Date$
1659 * Purpose: SK specific Error log support
1660 *
1661 ******************************************************************************/
1662
1663 /******************************************************************************
1664 *
1665+ * LICENSE:
1666 * (C)Copyright 1998-2002 SysKonnect.
1667- * (C)Copyright 2002-2003 Marvell.
1668+ * (C)Copyright 2002-2006 Marvell.
1669 *
1670 * This program is free software; you can redistribute it and/or modify
1671 * it under the terms of the GNU General Public License as published by
1672 * the Free Software Foundation; either version 2 of the License, or
1673 * (at your option) any later version.
1674- *
1675 * The information in this file is provided "AS IS" without warranty.
1676+ * /LICENSE
1677 *
1678 ******************************************************************************/
1679
1680@@ -28,28 +29,30 @@
1681 /*
1682 * Define Error Classes
1683 */
1684-#define SK_ERRCL_OTHER (0) /* Other error */
1685-#define SK_ERRCL_CONFIG (1L<<0) /* Configuration error */
1686-#define SK_ERRCL_INIT (1L<<1) /* Initialization error */
1687-#define SK_ERRCL_NORES (1L<<2) /* Out of Resources error */
1688-#define SK_ERRCL_SW (1L<<3) /* Internal Software error */
1689-#define SK_ERRCL_HW (1L<<4) /* Hardware Failure */
1690-#define SK_ERRCL_COMM (1L<<5) /* Communication error */
1691-
1692+#define SK_ERRCL_OTHER (0) /* Other error */
1693+#define SK_ERRCL_CONFIG (1L<<0) /* Configuration error */
1694+#define SK_ERRCL_INIT (1L<<1) /* Initialization error */
1695+#define SK_ERRCL_NORES (1L<<2) /* Out of Resources error */
1696+#define SK_ERRCL_SW (1L<<3) /* Internal Software error */
1697+#define SK_ERRCL_HW (1L<<4) /* Hardware Failure */
1698+#define SK_ERRCL_COMM (1L<<5) /* Communication error */
1699+#define SK_ERRCL_INFO (1L<<6) /* Information */
1700
1701 /*
1702 * Define Error Code Bases
1703 */
1704-#define SK_ERRBASE_RLMT 100 /* Base Error number for RLMT */
1705-#define SK_ERRBASE_HWINIT 200 /* Base Error number for HWInit */
1706-#define SK_ERRBASE_VPD 300 /* Base Error number for VPD */
1707-#define SK_ERRBASE_PNMI 400 /* Base Error number for PNMI */
1708-#define SK_ERRBASE_CSUM 500 /* Base Error number for Checksum */
1709-#define SK_ERRBASE_SIRQ 600 /* Base Error number for Special IRQ */
1710-#define SK_ERRBASE_I2C 700 /* Base Error number for I2C module */
1711-#define SK_ERRBASE_QUEUE 800 /* Base Error number for Scheduler */
1712-#define SK_ERRBASE_ADDR 900 /* Base Error number for Address module */
1713-#define SK_ERRBASE_PECP 1000 /* Base Error number for PECP */
1714-#define SK_ERRBASE_DRV 1100 /* Base Error number for Driver */
1715+#define SK_ERRBASE_RLMT 100 /* Base Error number for RLMT */
1716+#define SK_ERRBASE_HWINIT 200 /* Base Error number for HWInit */
1717+#define SK_ERRBASE_VPD 300 /* Base Error number for VPD */
1718+#define SK_ERRBASE_PNMI 400 /* Base Error number for PNMI */
1719+#define SK_ERRBASE_CSUM 500 /* Base Error number for Checksum */
1720+#define SK_ERRBASE_SIRQ 600 /* Base Error number for Special IRQ */
1721+#define SK_ERRBASE_I2C 700 /* Base Error number for I2C module */
1722+#define SK_ERRBASE_QUEUE 800 /* Base Error number for Scheduler */
1723+#define SK_ERRBASE_ADDR 900 /* Base Error number for Address module */
1724+#define SK_ERRBASE_PECP 1000 /* Base Error number for PECP */
1725+#define SK_ERRBASE_DRV 1100 /* Base Error number for Driver */
1726+#define SK_ERRBASE_ASF 1200 /* Base Error number for ASF */
1727
1728 #endif /* _INC_SKERROR_H_ */
1729+
1730diff -ruN linux/drivers/net/sk98lin/h/skfops.h linux-new/drivers/net/sk98lin/h/skfops.h
1731--- linux/drivers/net/sk98lin/h/skfops.h 1970-01-01 01:00:00.000000000 +0100
1732+++ linux-new/drivers/net/sk98lin/h/skfops.h 2006-10-13 11:18:49.000000000 +0200
1733@@ -0,0 +1,39 @@
1734+
1735+/******************************************************************************
1736+ *
1737+ * Name: skfops.c
1738+ * Project: Gigabit Ethernet Adapters, Common Modules
1739+ * Version: $Revision$
1740+ * Date: $Date$
1741+ * Purpose: Kernel mode file read functions.
1742+ *
1743+ ******************************************************************************/
1744+
1745+/******************************************************************************
1746+ *
1747+ * (C)Copyright 1998-2002 SysKonnect
1748+ * (C)Copyright 2002-2003 Marvell
1749+ *
1750+ * THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF SYSKONNECT
1751+ * The copyright notice above does not evidence any
1752+ * actual or intended publication of such source code.
1753+ *
1754+ * This Module contains Proprietary Information of SysKonnect
1755+ * and should be treated as Confidential.
1756+ *
1757+ * The information in this file is provided for the exclusive use of
1758+ * the licensees of SysKonnect.
1759+ * Such users have the right to use, modify, and incorporate this code
1760+ * into products for purposes authorized by the license agreement
1761+ * provided they include this notice and the associated copyright notice
1762+ * with any such product.
1763+ * The information in this file is provided "AS IS" without warranty.
1764+ *
1765+ ******************************************************************************/
1766+
1767+
1768+SK_BOOL fw_read( SK_AC *pAC, /* Pointer to adapter context */
1769+ char *name, SK_U8 **addr, SK_U32 *len );
1770+SK_BOOL fw_file_exists( SK_AC *pAC, /* Pointer to adapter context */
1771+ char *name );
1772+
1773diff -ruN linux/drivers/net/sk98lin/h/skgeasf.h linux-new/drivers/net/sk98lin/h/skgeasf.h
1774--- linux/drivers/net/sk98lin/h/skgeasf.h 1970-01-01 01:00:00.000000000 +0100
1775+++ linux-new/drivers/net/sk98lin/h/skgeasf.h 2006-10-13 10:18:34.000000000 +0200
1776@@ -0,0 +1,547 @@
1777+/******************************************************************************
1778+ *
1779+ * Name: skgeasf.h
1780+ * Project: asf/ipmi
1781+ * Version: $Revision$
1782+ * Date: $Date$
1783+ * Purpose: asf/ipmi interface in windows driver
1784+ *
1785+ ******************************************************************************/
1786+
1787+/******************************************************************************
1788+ *
1789+ * (C)Copyright 1998-2002 SysKonnect.
1790+ * (C)Copyright 2002-2003 Marvell.
1791+ *
1792+ * This program is free software; you can redistribute it and/or modify
1793+ * it under the terms of the GNU General Public License as published by
1794+ * the Free Software Foundation; either version 2 of the License, or
1795+ * (at your option) any later version.
1796+ *
1797+ * The information in this file is provided "AS IS" without warranty.
1798+ *
1799+ ******************************************************************************/
1800+
1801+#ifndef _INC_SKGEASF_H_
1802+#define _INC_SKGEASF_H_
1803+
1804+#ifdef __cplusplus
1805+extern "C" {
1806+#endif /* __cplusplus */
1807+
1808+/* DEFINES */
1809+#define ASF_FW_ARP_RESOLVE // FW is resolving the destination IP addr
1810+#define ASF_FW_WD // Driver is watching the FW
1811+#define ASF_CHECK_HIDDEN_ID // ASF init checks hidden id
1812+
1813+// modes for the asf driver
1814+#define SK_GEASF_MODE_UNKNOWN 0 // unknown operation mode (initial)
1815+#define SK_GEASF_MODE_ASF 1 // asfec.bin binary found -> ASF operation
1816+#define SK_GEASF_MODE_IPMI 2 // ipmiy2.bin binary found -> IPMI operation
1817+
1818+// chip modes for asf driver
1819+#define SK_GEASF_CHIP_UNKNOWN 0 // bad chip id / hidden id
1820+#define SK_GEASF_CHIP_EC 1 // EC: ASF
1821+#define SK_GEASF_CHIP_Y2 2 // Yukon2
1822+
1823+// dual link mode
1824+#define SK_GEASF_Y2_SINGLEPORT 1 // Yukon2 sigle link adapter
1825+#define SK_GEASF_Y2_DUALPORT 2 // Yukon2 dual link adapter
1826+
1827+#define ASF_GUI_TSF 10 /* Time Scale Factor: 1s(GUI) <-> 10*100ms(FW) */
1828+
1829+#define ASF_MAX_STRLEN 64
1830+
1831+// lengths used in get oid
1832+#define ASF_ACPI_MAXBUFFLENGTH 256 // max bytes for holding ACPI table
1833+#define ASF_SMBUS_MAXBUFFLENGTH 128 // max bytes for holding SMBus info
1834+#define ASF_FWVER_MAXBUFFLENGTH 40 // max stringlen for firmware version
1835+
1836+#define SK_ASF_EVT_TIMER_EXPIRED 1 /* Counter overflow */
1837+#define SK_ASF_EVT_TIMER_SPI_EXPIRED 2 /* Counter overflow */
1838+#define SK_ASF_EVT_TIMER_HCI_EXPIRED 3 /* Counter overflow */
1839+
1840+/* Return codes to the PNMI module */
1841+#define SK_ASF_PNMI_ERR_OK 0
1842+#define SK_ASF_PNMI_ERR_GENERAL 1
1843+#define SK_ASF_PNMI_ERR_TOO_SHORT 2
1844+#define SK_ASF_PNMI_ERR_BAD_VALUE 3
1845+#define SK_ASF_PNMI_ERR_READ_ONLY 4
1846+#define SK_ASF_PNMI_ERR_UNKNOWN_OID 5
1847+#define SK_ASF_PNMI_ERR_UNKNOWN_INST 6
1848+#define SK_ASF_PNMI_ERR_UNKNOWN_NET 7
1849+#define SK_ASF_PNMI_ERR_NOT_SUPPORTED 10
1850+
1851+#define REG_ASF_MAC_ADDR 0x0f24
1852+#define REG_ASF_MY_IP 0x0f50
1853+#define REG_ASF_STATUS_CMD 0x0e68
1854+#define REG_ASF_SMBUS_CFG 0x0e40
1855+
1856+#define ASF_CPU_STATE_UNKNOWN 0
1857+#define ASF_CPU_STATE_RESET 1
1858+#define ASF_CPU_STATE_RUNNING 2
1859+
1860+
1861+/* ASF MIB default values */
1862+#define ASF_DEF_RETRANS_COUNT_MIN 0 // x1
1863+#define ASF_DEF_RETRANS_COUNT_MAX 255 // x1
1864+#define ASF_DEF_WATCHDOG_ENA 0 //
1865+#define ASF_DEF_WATCHDOG_TIME 1200 // *100ms
1866+#define ASF_DEF_WATCHDOG_TIME_MAX 36000 // *100ms
1867+#define ASF_DEF_WATCHDOG_TIME_MIN 600 // *100ms
1868+#define ASF_DEF_RETRANS_INT_MIN 0 // *100ms
1869+#define ASF_DEF_RETRANS_INT_MAX 2550 // *100ms
1870+#define ASF_DEF_HB_INT_MIN 10 // *100ms
1871+#define ASF_DEF_HB_INT_MAX 2550 // *100ms
1872+#define ASF_DEF_ASF_ENA 0
1873+#define ASF_DEF_RETRANS 2
1874+#define ASF_DEF_RETRANS_INT 10 // *100ms
1875+#define ASF_DEF_HB_ENA 0
1876+#define ASF_DEF_HB_INT 600 // *100ms
1877+
1878+/* ASF HCI Commands */
1879+#define YASF_HOSTCMD_ASF_INFO 1
1880+#define YASF_HOSTCMD_LEG_CONF 2
1881+#define YASF_HOSTCMD_ASF_CONF 3
1882+#define YASF_HOSTCMD_RCTRL_CONF 4
1883+#define YASF_HOSTCMD_KEEP_ALIVE 5
1884+#define YASF_HOSTCMD_NEW_SEPROM_CONFIG 6
1885+#define YASF_HOSTCMD_ENTER_RAM_IDLE 7
1886+#define YASF_HOSTCMD_LEAVE_RAM_IDLE 8
1887+#define YASF_HOSTCMD_RUN_DIAG 9
1888+#define YASF_HOSTCMD_RESET_STATE 10
1889+#define YASF_HOSTCMD_RESET 11
1890+#define YASF_HOSTCMD_CHECK_ALIVE 12
1891+#define YASF_HOSTCMD_DRV_HELLO 13
1892+#define YASF_HOSTCMD_DRV_GOODBYE 14
1893+#define YASF_HOSTCMD_DRV_STANDBY 15
1894+#define YASF_HOSTCMD_UPDATE_OWN_MACADDR 16
1895+#define YASF_HOSTCMD_ARP_RESOLVE 17
1896+#define YASF_HOSTCMD_RESET_COLD 18
1897+#define YASF_HOSTCMD_ACPI_RMCP_DATA 19
1898+#define YASF_HOSTCMD_ACPI_ERROR 20
1899+
1900+#define YASF_HOSTCMD_CFG_SET_ASF_ENABLE 100
1901+#define YASF_HOSTCMD_CFG_SET_RSP_ENABLE 101
1902+#define YASF_HOSTCMD_CFG_SET_RETRANS 102
1903+#define YASF_HOSTCMD_CFG_SET_RETRANS_INT 103
1904+#define YASF_HOSTCMD_CFG_SET_HB_ENABLE 104
1905+#define YASF_HOSTCMD_CFG_SET_HB_INT 105
1906+#define YASF_HOSTCMD_CFG_SET_IP_DESTINATION 106
1907+#define YASF_HOSTCMD_CFG_SET_IP_SOURCE 107
1908+#define YASF_HOSTCMD_CFG_SET_MAC_DESTINATION 108
1909+#define YASF_HOSTCMD_CFG_SET_COMMUNITY_NAME 109
1910+#define YASF_HOSTCMD_CFG_SET_RSP_KEY_1 110
1911+#define YASF_HOSTCMD_CFG_SET_RSP_KEY_2 111
1912+#define YASF_HOSTCMD_CFG_SET_RSP_KEY_3 112
1913+#define YASF_HOSTCMD_CFG_SET_DRWD_ENABLE 113
1914+#define YASF_HOSTCMD_CFG_SET_DRWD_INT 114
1915+#define YASF_HOSTCMD_CFG_SET_WD_ENABLE 115
1916+#define YASF_HOSTCMD_CFG_SET_WD_INT 116
1917+#define YASF_HOSTCMD_CFG_SET_ASF_RAMSIZE 117
1918+#define YASF_HOSTCMD_CFG_SET_ACTIVE_PORT 118
1919+
1920+#define YASF_HOSTCMD_CFG_STORE_CONFIG 130
1921+
1922+#define YASF_HOSTCMD_CFG_GET_ASF_ENABLE 150
1923+#define YASF_HOSTCMD_CFG_GET_RSP_ENABLE 151
1924+#define YASF_HOSTCMD_CFG_GET_RETRANS 152
1925+#define YASF_HOSTCMD_CFG_GET_RETRANS_INT 153
1926+#define YASF_HOSTCMD_CFG_GET_HB_ENABLE 154
1927+#define YASF_HOSTCMD_CFG_GET_HB_INT 155
1928+#define YASF_HOSTCMD_CFG_GET_IP_DESTINATION 156
1929+#define YASF_HOSTCMD_CFG_GET_IP_SOURCE 157
1930+#define YASF_HOSTCMD_CFG_GET_MAC_DESTINATION 158
1931+#define YASF_HOSTCMD_CFG_GET_COMMUNITY_NAME 159
1932+#define YASF_HOSTCMD_CFG_GET_RSP_KEY_1 160
1933+#define YASF_HOSTCMD_CFG_GET_RSP_KEY_2 161
1934+#define YASF_HOSTCMD_CFG_GET_RSP_KEY_3 162
1935+#define YASF_HOSTCMD_CFG_GET_DRWD_ENABLE 163
1936+#define YASF_HOSTCMD_CFG_GET_DRWD_INT 164
1937+#define YASF_HOSTCMD_CFG_GET_WD_ENABLE 165
1938+#define YASF_HOSTCMD_CFG_GET_WD_INT 166
1939+#define YASF_HOSTCMD_CFG_GET_ASF_RAMSIZE 167
1940+#define YASF_HOSTCMD_CFG_GET_FW_VERSION_STRING 168
1941+#define YASF_HOSTCMD_CFG_GET_SMBUS_INFOS 169
1942+#define YASF_HOSTCMD_CFG_GET_ACTIVE_PORT 170
1943+#define YASF_HOSTCMD_CFG_READ_CONFIG 180
1944+
1945+
1946+/* ASF HCI Master */
1947+#define ASF_HCI_READ 0x08000000
1948+#define ASF_HCI_WRITE 0x04000000
1949+#define ASF_HCI_CMD_RD_READY 0x02000000
1950+#define ASF_HCI_CMD_WR_READY 0x01000000
1951+#define ASF_HCI_UNSUCCESS 0x00800000
1952+#define ASF_HCI_OFFSET 0x000000ff
1953+
1954+#define ASF_HCI_CMDREG 0x0e70
1955+#define ASF_HCI_DATAREG 0x0e78
1956+
1957+#define ASF_HCI_WAIT 1
1958+#define ASF_HCI_NOWAIT 0
1959+
1960+#define ASF_HCI_TO 100 /* 1s */
1961+
1962+#define HCI_EN_CMD_IDLE 0
1963+#define HCI_EN_CMD_WRITING 1
1964+#define HCI_EN_CMD_READING 2
1965+#define HCI_EN_CMD_WAIT 3
1966+#define HCI_EN_CMD_READY 4
1967+#define HCI_EN_CMD_ERROR 5
1968+
1969+#define ASF_HCI_REC_BUF_SIZE 128
1970+#define ASF_HCI_TRA_BUF_SIZE 128
1971+
1972+
1973+/* SEPROM (VPD) */
1974+#define ASF_VPD_CONFIG_BASE 0x340
1975+#define ASF_VPD_CONFIG_SIZE 0x80
1976+#define ASF_VPD_DATA_BASE 0x3c0
1977+#define ASF_VPD_DATA_SIZE 0x40
1978+
1979+/* Flash (SPI)*/
1980+#define ASF_FLASH_SIZE (1024*64)
1981+#define ASF_FLASH_OFFS 0x20000
1982+#define ASF_FLASH_OFFS_VER 0x1fc00
1983+#define ASF_FLASH_OFFS_REV 0x1fc0b
1984+#define ASF_FLASH_OFFS_CS 0x1fffc
1985+#define ASF_FLASH_OFFS_GUID 0x1f000
1986+#define ASF_FLASH_OFFS_ACPI 0x1f010
1987+
1988+#define ASF_RESET_HOT 0
1989+#define ASF_RESET_COLD 1
1990+
1991+#define ASF_INIT_UNDEFINED 0
1992+#define ASF_INIT_OK 1
1993+#define ASF_INIT_ERROR 2
1994+#define ASF_INIT_ERROR_CHIP_ID 3
1995+#define ASF_INIT_ERROR_OPMODE 4
1996+
1997+#define RSP_KEYLENGTH 20
1998+
1999+// ACPI module defines
2000+#define ASF_ACPI_STATE_OK 1
2001+#define ASF_ACPI_STATE_UNDEFINED 0
2002+#define ASF_ACPI_STATE_ERROR -1
2003+#define ASF_ACPI_STATE_ERROR_NO_RSDPTR -2
2004+#define ASF_ACPI_STATE_ERROR_RSDT -3
2005+#define ASF_ACPI_STATE_ERROR_XSDT -4
2006+#define ASF_ACPI_STATE_ERROR_RSDT_NO_TABLE -5
2007+#define ASF_ACPI_STATE_ERROR_RSDT_HEADER -6
2008+#define ASF_ACPI_STATE_ERROR_ASF -7
2009+#define ASF_ACPI_STATE_ERROR_ASF_HEADER -8
2010+#define ASF_ACPI_STATE_ERROR_RSDT_NO_ASF_TABLE -9
2011+#define ASF_ACPI_STATE_ERROR_FILE_OPEN -10
2012+#define ASF_ACPI_STATE_ERROR_FILE_MAP -11
2013+#define ASF_ACPI_STATE_ERROR_FILE_SIZE -12
2014+#define ASF_ACPI_STATE_ERROR_FILE_CS -13
2015+
2016+#define ASF_RECORD_INFO 0x00
2017+#define ASF_RECORD_ALRT 0x01
2018+#define ASF_RECORD_RCTL 0x02
2019+#define ASF_RECORD_RMCP 0x03
2020+#define ASF_RECORD_ADDR 0x04
2021+
2022+#define TABLE_HEADER_LENGTH 36
2023+#define SEC_COMMIT 0x08000000
2024+
2025+
2026+// endianess depended macros
2027+
2028+#define REVERSE_16(x) ((((x)<<8)&0xff00) + (((x)>>8)&0x00ff))
2029+
2030+#define REVERSE_32(x) ( ((((SK_U32)(x))<<24UL)&0xff000000UL) + \
2031+ ((((SK_U32)(x))<< 8UL)&0x00ff0000UL) + \
2032+ ((((SK_U32)(x))>> 8UL)&0x0000ff00UL) + \
2033+ ((((SK_U32)(x))>>24UL)&0x000000ffUL) )
2034+
2035+#ifdef SK_LITTLE_ENDIAN
2036+#define NTOHS(x) REVERSE_16(x)
2037+#define HTONS(x) REVERSE_16(x)
2038+#define NTOHL(x) REVERSE_32(x)
2039+#define HTONL(x) REVERSE_32(x)
2040+#else
2041+#define NTOHS(x) (x)
2042+#define HTONS(x) (x)
2043+#define NTOHL(x) (x)
2044+#define HTONL(x) (x)
2045+#endif
2046+
2047+/*
2048+ * ASF MIB structure
2049+ */
2050+struct _STR_PET_DAT
2051+{
2052+ SK_U8 EventSensorType;
2053+ SK_U8 EventType;
2054+ SK_U8 EventOffset;
2055+ SK_U8 TrapSourceType;
2056+ SK_U8 EventSourceType;
2057+ SK_U8 EventSeverity;
2058+ SK_U8 SensorDevice;
2059+ SK_U8 SensorNumber;
2060+ SK_U8 Entity;
2061+ SK_U8 EntityInstance;
2062+ SK_U8 EventData [8];
2063+ SK_U8 LanguageCode;
2064+ SK_U8 OemCustomField [64];
2065+ // 83 Bytes so far
2066+};
2067+typedef struct _STR_PET_DAT STR_PET_DAT;
2068+
2069+// structure for ACPI data for reporting to GUI
2070+struct _STR_ASF_ACPI
2071+{
2072+ SK_U8 buffer [ASF_ACPI_MAXBUFFLENGTH];
2073+ SK_U32 length;
2074+};
2075+typedef struct _STR_ASF_ACPI STR_ASF_ACPI;
2076+
2077+// structure for SMBus data for reporting to GUI
2078+struct _STR_ASF_SMBUSINFO
2079+{
2080+ SK_U8 UpdateReq;
2081+ SK_U8 buffer [ASF_SMBUS_MAXBUFFLENGTH];
2082+ SK_U32 length;
2083+};
2084+typedef struct _STR_ASF_SMBUSINFO STR_ASF_SMBUSINFO;
2085+
2086+struct _STR_ASF_MIB
2087+{
2088+ SK_U8 WriteToFlash;
2089+ SK_U8 ConfigChange;
2090+ // Configuration parameter related to registers
2091+ SK_U8 NewParam;
2092+ SK_U8 Ena;
2093+ SK_U16 Retrans;
2094+ SK_U32 RetransInt;
2095+ SK_U8 HbEna;
2096+ SK_U32 HbInt;
2097+ SK_U8 WdEna;
2098+ SK_U32 WdTime;
2099+ SK_U8 IpSource [4];
2100+ SK_U8 MacSource [6];
2101+ SK_U8 IpDest [4];
2102+ SK_U8 MacDest [6];
2103+ SK_U8 CommunityName [64];
2104+ SK_U8 Guid [16];
2105+ SK_U8 RspEnable;
2106+ SK_U32 RetransCountMin;
2107+ SK_U32 RetransCountMax;
2108+ SK_U32 RetransIntMin;
2109+ SK_U32 RetransIntMax;
2110+ SK_U32 HbIntMin;
2111+ SK_U32 HbIntMax;
2112+ SK_U32 WdTimeMax;
2113+ SK_U32 WdTimeMin;
2114+ SK_U8 KeyOperator [RSP_KEYLENGTH];
2115+ SK_U8 KeyAdministrator [RSP_KEYLENGTH];
2116+ SK_U8 KeyGenerator [RSP_KEYLENGTH];
2117+ STR_ASF_ACPI Acpi;
2118+ STR_ASF_SMBUSINFO SMBus;
2119+ SK_U8 RlmtMode;
2120+ SK_U8 Reserved [6]; // reserved bytes in vpd
2121+ SK_U8 PattUpReq;
2122+};
2123+typedef struct _STR_ASF_MIB STR_ASF_MIB;
2124+
2125+typedef struct s_Hci
2126+{
2127+ SK_U32 To;
2128+ SK_U8 Status;
2129+ SK_U8 OldStatus;
2130+ SK_U32 OldCmdReg;
2131+ SK_U8 SendIndex;
2132+ SK_U8 ReceiveIndex;
2133+ SK_U8 SendLength;
2134+ SK_U8 ReceiveLength;
2135+ SK_U8 ExpectResponse;
2136+ SK_U8 Cycles;
2137+ SK_U64 Time;
2138+ SK_U8 ReceiveBuf [ASF_HCI_REC_BUF_SIZE];
2139+ SK_U8 TransmitBuf [ASF_HCI_TRA_BUF_SIZE];
2140+ SK_TIMER AsfTimerHci;
2141+} STR_HCI;
2142+
2143+/*
2144+ * ASF specific adapter context structure
2145+ */
2146+typedef struct s_AsfData
2147+{
2148+ SK_U8 CurrentMacAddr[6];
2149+ SK_U8 IpAddress[4];
2150+ SK_TIMER AsfTimer;
2151+ SK_TIMER AsfTimerWrSpi;
2152+ SK_U8 StateHci;
2153+ SK_U8 StateWrSpi;
2154+ SK_U8 DriverVersion [5];
2155+ SK_U8 FlashFwVersion [5];
2156+ SK_U8 FlashFwRev;
2157+ SK_U8 FileFwVersion [5];
2158+ SK_U8 FileFwRev;
2159+//VSz
2160+ SK_U8 FlashBuffer [ASF_FLASH_SIZE];
2161+ SK_U8 VpdConfigBuf [ASF_VPD_CONFIG_SIZE];
2162+ STR_ASF_MIB Mib;
2163+ STR_HCI Hci;
2164+ SK_U8 GlHciState;
2165+ SK_U8 LastGlHciState;
2166+ SK_U8 InitState;
2167+ SK_U8 VpdInitOk;
2168+ SK_U32 FwError;
2169+ SK_U8 CpuAlive;
2170+ SK_U16 FwWdIntervall;
2171+ SK_U16 FwRamSize;
2172+ SK_U8 ActivePort;
2173+ SK_U8 PrefPort;
2174+ SK_U8 FwVersionString [80];
2175+ SK_U8 NewGuid;
2176+ SK_U8 OpMode; // ASF or IPMI operation mode - see SkAsfInit
2177+ SK_U8 ChipMode; // relevant for ASF or IPMI operation mode
2178+ SK_U8 DualMode;
2179+}SK_ASF_DATA;
2180+
2181+#define MAX_EVENT_DATA 8
2182+
2183+struct _STR_EVENT_DATA {
2184+ struct _STR_EVENT_DATA *next;
2185+ SK_U8 SensorType; // SNMP (Specific Trap)
2186+ SK_U8 Type; // SNMP (Specific Trap)
2187+ SK_U8 Offset; // SNMP (Specific Trap)
2188+ SK_U8 SourceType; // PET
2189+ SK_U8 Severity; // PET
2190+ SK_U8 SensorDevice; // PET
2191+ SK_U8 SensorNumber; // PET
2192+ SK_U8 Entity; // PET
2193+ SK_U8 EntityInstance; // PET
2194+ SK_U8 DataLen;
2195+ SK_U8 Data [MAX_EVENT_DATA]; // PET
2196+};
2197+typedef struct _STR_EVENT_DATA STR_EVENT_DATA;
2198+
2199+
2200+/* Functions provided by SkGeAsf */
2201+
2202+/* ANSI/C++ compliant function prototypes */
2203+
2204+/*
2205+ * Public Function prototypes
2206+ */
2207+extern int SkAsfDeInit(SK_AC *pAC, SK_IOC IoC );
2208+extern int SkAsfInit (SK_AC *pAC , SK_IOC IoC , int level);
2209+extern int SkAsfDeInitStandBy( SK_AC *pAC, SK_IOC IoC );
2210+extern int SkAsfInitStandBy( SK_AC *pAC, SK_IOC IoC, int Level );
2211+extern int SkAsfGet (SK_AC *pAC , SK_IOC IoC , SK_U8 *pBuf, unsigned int *pLen);
2212+extern int SkAsfPreSet (SK_AC *pAC , SK_IOC IoC , SK_U8 *pBuf, unsigned int *pLen);
2213+extern int SkAsfSet (SK_AC *pAC , SK_IOC IoC , SK_U8 *pBuf, unsigned int *pLen);
2214+extern int SkAsfEvent (SK_AC *pAC , SK_IOC IoC , SK_U32 Event , SK_EVPARA Param);
2215+extern int SkAsfSetOid(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, SK_U32 Inst, SK_U8 *pBuf, unsigned int *pLen);
2216+extern int SkAsfPreSetOid(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, SK_U32 Inst, SK_U8 *pBuf, unsigned int *pLen);
2217+extern int SkAsfGetOid(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, SK_U32 Inst, SK_U8 *pBuf, unsigned int *pLen);
2218+extern int SkAsfRestorePattern(SK_AC *pAC , SK_IOC IoC);
2219+
2220+
2221+SK_I8 SkAsfReadSpiConfigData( SK_AC *pAC );
2222+SK_I8 SkAsfWriteSpiConfigData( SK_AC *pAC );
2223+SK_I8 SkAsfUpdateSpiConfigData(SK_AC *pAC, SK_U8 *data , SK_U32 off , SK_U32 len, SK_U32 ClrCnt );
2224+SK_I8 SkAsfUpdateConfDat( SK_AC *pAC, SK_U8 Pig, SK_U16 RegOffs, SK_U8 ByteEnable, SK_U32 Val, SK_U8 ForceNewEntry );
2225+SK_I8 SkAsfReadConfDat( SK_AC *pAC, SK_U8 Pig, SK_U16 RegOffs, SK_U8 ByteEnable, SK_U32 *Val );
2226+SK_I8 SkAsfWriteDeferredFlash( SK_AC *pAC, SK_IOC IoC );
2227+SK_I8 SkAsfStartWriteDeferredFlash( SK_AC *pAC, SK_IOC IoC );
2228+void SkAsfTimer( SK_AC *pAC, SK_IOC IoC );
2229+void SkAsfShowMib( SK_AC *pAC );
2230+void AsfResetCpu( SK_IOC IoC );
2231+void AsfRunCpu( SK_IOC IoC );
2232+SK_U8 AsfCheckAliveCpu( SK_AC *pAC, SK_IOC IoC );
2233+SK_I8 SkAsfSeprom2Mib( SK_AC *pAC, SK_IOC IoC );
2234+SK_I8 SkAsfMib2Seprom( SK_AC *pAC, SK_IOC IoC );
2235+SK_U8 AsfSmartResetCpu( SK_AC *pAC, SK_IOC IoC, SK_U8 Cold );
2236+SK_U8 AsfSmartResetStateCpu( SK_AC *pAC, SK_IOC IoC );
2237+SK_U8 AsfCpuState( SK_IOC Ioc );
2238+
2239+SK_U8 AsfHciGetData( SK_AC *pAC, SK_U8 **pHciRecBuf );
2240+SK_U8 AsfHciGetState( SK_AC *pAC );
2241+SK_U8 AsfHciSendCommand( SK_AC *pAC, SK_IOC IoC, SK_U8 Command, SK_U8 Par1, SK_U8 Par2, SK_U8 ExpectResponse, SK_U8 Wait, SK_U8 Retry );
2242+SK_U8 AsfHciSendData( SK_AC *pAC, SK_IOC IoC, SK_U8 *Buffer, SK_U8 ExpectResponse, SK_U8 Wait, SK_U8 Retry );
2243+SK_U8 AsfHciSendMessage( SK_AC *pAC, SK_IOC IoC, SK_U8 *message, SK_U8 length, SK_U8 ExpectResponse, SK_U8 Wait );
2244+
2245+void SkAsfHci( SK_AC *pAC, SK_IOC IoC, SK_U8 ToEna );
2246+void AsfWatchCpu( SK_AC *pAC, SK_IOC IoC, SK_U32 par );
2247+void AsfEnable(SK_AC *pAC, SK_IOC IoC );
2248+void AsfDisable(SK_AC *pAC, SK_IOC IoC );
2249+
2250+void AsfSetUpPattern(SK_AC *pAC, SK_IOC IoC, SK_U8 port );
2251+SK_I8 AsfWritePatternRam( SK_AC *pAC,
2252+ SK_IOC IoC,
2253+ SK_U8 Port,
2254+ SK_U8 PatternId1,
2255+ SK_U8 PatternId2,
2256+ SK_U8 Length1,
2257+ SK_U8 Length2,
2258+ SK_U8 *pMask1,
2259+ SK_U8 *pPattern1,
2260+ SK_U8 *pMask2,
2261+ SK_U8 *pPattern2 );
2262+SK_I8 YlciEnablePattern (SK_AC *pAC, SK_IOC IoC, SK_U8 port, SK_U8 pattno );
2263+SK_I8 YlciDisablePattern (SK_AC *pAC, SK_IOC IoC, SK_U8 port, SK_U8 pattno );
2264+
2265+// ACPI and "ASF!" stuff
2266+SK_I8 SkAsfAcpi( SK_AC *pAC, SK_IOC IoC, SK_U8 *pImage );
2267+//SK_I8 SkAsfAcpiRsdt( SK_AC *pAC, SK_IOC IoC, SK_U8 *pImage, HANDLE SectionHandle, SK_U32 PhysAddr );
2268+//SK_I8 SkAsfAcpiXsdt( SK_AC *pAC, SK_IOC IoC, SK_U8 *pImage, HANDLE SectionHandle, SK_U64 PhysAddr );
2269+//SK_I8 SkAsfAcpiAsf( SK_AC *pAC, SK_IOC IoC, SK_U8 *pImage, HANDLE SectionHandle, SK_U32 PhysAddr );
2270+SK_I8 SkAsfPatchAsfTable( SK_AC *pAC, SK_IOC IoC, SK_U8 *pImage, SK_U8 *pAsfTable, SK_U32 TableLength );
2271+SK_I8 SkAsfPatchGuid( SK_AC *pAC, SK_IOC IoC, SK_U8 *pImage, SK_U8 *pGuid );
2272+void SkAsfExamineAsfTable( SK_AC *pAC, SK_IOC IoC, SK_U8 *pAsf, SK_U32 TableLength );
2273+SK_I8 SkAsfSendRmcpData(SK_AC *pAC, SK_IOC IoC,SK_U8 *pData, SK_U8 Length );
2274+
2275+// ipmi
2276+SK_I8 AsfWriteIpmiPattern(SK_AC *pAC, SK_IOC IoC, SK_U8 port);
2277+
2278+/* in file skspilole.c */
2279+void spi_init_pac( SK_AC *pAC );
2280+
2281+// for cleaning up smbus register
2282+void AsfSetSMBusRegister(SK_IOC IoC);
2283+
2284+#define SKERR_ASF_E001 (SK_ERRBASE_ASF)
2285+#define SKERR_ASF_E001MSG "SkAsfInit() error: wrong HCI version"
2286+#define SKERR_ASF_E002 (SKERR_ASF_E001+1)
2287+#define SKERR_ASF_E002MSG "SkAsfInit() error: flash read"
2288+#define SKERR_ASF_E003 (SKERR_ASF_E001+2)
2289+#define SKERR_ASF_E003MSG "SkAsfInit() error: flash erase"
2290+#define SKERR_ASF_E004 (SKERR_ASF_E001+3)
2291+#define SKERR_ASF_E004MSG "SkAsfInit() error: flash write"
2292+#define SKERR_ASF_E005 (SKERR_ASF_E001+4)
2293+#define SKERR_ASF_E005MSG "SkAsfInit() error: map FW image"
2294+#define SKERR_ASF_E006 (SKERR_ASF_E001+5)
2295+#define SKERR_ASF_E006MSG "SkAsfInit() error: flash reread"
2296+#define SKERR_ASF_E007 (SKERR_ASF_E001+6)
2297+#define SKERR_ASF_E007MSG "SkAsfInit() error: flash compare"
2298+#define SKERR_ASF_E008 (SKERR_ASF_E001+7)
2299+#define SKERR_ASF_E008MSG "SkAsfInit() flash successfully updated"
2300+#define SKERR_ASF_E009 (SKERR_ASF_E001+8)
2301+#define SKERR_ASF_E009MSG "SkAsfInit() updating flash"
2302+
2303+
2304+#define ASF_YEC_YTB_BASE_WOL_CTRL1 ((SK_U32)0x0f20) // YTB WOL CTRL register link 1
2305+#define ASF_YEC_PATTRAM_CLUSTER_BYTES ((SK_U8)4) // 4 bytes is a word
2306+#define ASF_YEC_PATTRAM_CLUSTER_WORDS ((SK_U8)4) // 4 words in a cluster
2307+#define ASF_YEC_PATTRAM_CLUSTER_SIZE ((SK_U8)64) // pattern ram has 64 cluster
2308+
2309+#define ASF_YEC_PATTERN_ENA1 (ASF_YEC_YTB_BASE_WOL_CTRL1 + 0x02) // enable pattern register, width:8
2310+#define ASF_YEC_PATTERN_LENGTH_R1_L (ASF_YEC_YTB_BASE_WOL_CTRL1 + 0x10) // pattern length register, pattern 0-3, width: 4x8
2311+#define ASF_YEC_PATTERN_LENGTH_R1_H (ASF_YEC_YTB_BASE_WOL_CTRL1 + 0x14) // pattern length register, pattern 4-6, width: 3x8
2312+#define ASF_YEC_PATTERN_MATCHENA1 (ASF_YEC_YTB_BASE_WOL_CTRL1 + 0x0b) // ASF/PME match enable register, width: 8
2313+#define ASF_YEC_PATTERN_CTRL1 (ASF_YEC_YTB_BASE_WOL_CTRL1 + 0x00) // match result, match control, wol ctrl and status
2314+
2315+#define ASF_YEC_YTB_BASE_MACRXFIFO1 ((SK_U32)0x0c40) // base of receive MAC fifo registers, port 1
2316+#define ASF_YEC_MAC_FIFO_CTRL1 (ASF_YEC_YTB_BASE_MACRXFIFO1 + 0x08) // control/test Rx MAC, link1, 32 bit
2317+#define ASF_YEC_MAC_FIFO_FLUSHMASK1 (ASF_YEC_YTB_BASE_MACRXFIFO1 + 0x0c) // flush mask register Rx MAC, link1, 32 bit
2318+#define ASF_YEC_MAC_FIFO_FLUSHTHRES1 (ASF_YEC_YTB_BASE_MACRXFIFO1 + 0x10) // Rx MAC FIFO Flush Threshold, link1, 32 bit
2319+
2320+#define ASF_YLCI_MACRXFIFOTHRES 8 // mac rx threshold in qwords
2321+
2322+
2323+#endif /* _INC_SKGEASF_H_ */
2324diff -ruN linux/drivers/net/sk98lin/h/skgeasfconv.h linux-new/drivers/net/sk98lin/h/skgeasfconv.h
2325--- linux/drivers/net/sk98lin/h/skgeasfconv.h 1970-01-01 01:00:00.000000000 +0100
2326+++ linux-new/drivers/net/sk98lin/h/skgeasfconv.h 2006-10-13 11:18:49.000000000 +0200
2327@@ -0,0 +1,94 @@
2328+
2329+/******************************************************************************
2330+ *
2331+ * Name: skgeasfconv.h
2332+ * Project: asf/ipmi
2333+ * Version: $Revision$
2334+ * Date: $Date$
2335+ * Purpose: asf/ipmi interface in windows driver
2336+ *
2337+ ******************************************************************************/
2338+
2339+/******************************************************************************
2340+ *
2341+ * (C)Copyright 1998-2002 SysKonnect.
2342+ * (C)Copyright 2002-2003 Marvell.
2343+ *
2344+ * This program is free software; you can redistribute it and/or modify
2345+ * it under the terms of the GNU General Public License as published by
2346+ * the Free Software Foundation; either version 2 of the License, or
2347+ * (at your option) any later version.
2348+ *
2349+ * The information in this file is provided "AS IS" without warranty.
2350+ *
2351+ ******************************************************************************/
2352+
2353+#ifndef _ASFWMI_H
2354+#define _ASFWMI_H
2355+
2356+#ifdef __cplusplus
2357+extern "C" {
2358+#endif
2359+
2360+// lengths for string conversion
2361+#define ASF_IPADDRGRPSIZE (4) // 4 groups in ip address string (111.222.333.444)
2362+#define ASF_MACADDRGRPSIZE (6) // 6 groups in mac address string (11-22-33-44-55-66)
2363+#define ASF_GUIDGRPSIZE (16) // 16 groups in a GUID string
2364+#define ASF_COMMUNITYSTRLEN (64) // length of community string
2365+#define ASF_IPADDRSTRLEN (3*ASF_IPADDRGRPSIZE+3) // length of xxx.xxx.xxx.xxx
2366+#define ASF_MACADDRSTRLEN (2*ASF_MACADDRGRPSIZE+5) // length of xx-xx-xx-xx-xx-xx
2367+#define ASF_GUIDSTRLEN (2*ASF_GUIDGRPSIZE) // length of GUID string
2368+
2369+// module sizes
2370+#define ASF_MAX_STRINGLEN (ASF_COMMUNITYSTRLEN+1) // length of a ascii string (with string end marker 0x00)
2371+#define ASF_MAX_UNICODESTRINGLEN (ASF_COMMUNITYSTRLEN) // length of a unicode string (without length information)
2372+
2373+
2374+// tags in strings
2375+#define ASF_IPSEPARATOR ('.') // separator in ip string
2376+#define ASF_MACSEPARATOR ('-') // separator in mac address
2377+
2378+
2379+// modes for AsfWmiInternal2External() and AsfWmiExternal2Internal()
2380+#define ASF_MODE_IPADDR (10) // input is a IP address (IPv4 format)
2381+#define ASF_MODE_MACADDR (11) // input is a MAC address
2382+#define ASF_MODE_COMMUNITY (12) // input is a community string
2383+#define ASF_MODE_GUID (13) // input is a number
2384+#define ASF_MODE_SYSID (14) // input is a number
2385+#define ASF_MODE_MANUID (15) // input is a number
2386+
2387+// modes for AsfWmiHexVal2Str()
2388+#define ASF_MODE_IPSTRDECIMAL (15) // get string with ip in decimal
2389+#define ASF_MODE_MACADDRHEX (16) // get string in hex
2390+
2391+// returncodes
2392+#define ASF_RETVAL_FAIL (-1)
2393+#define ASF_RETVAL_UNDEFINED (0)
2394+#define ASF_RETVAL_SUCCESS (1)
2395+
2396+// Unicode String structure
2397+typedef struct _STR_ASF_UNISTRING
2398+{
2399+ SK_U16 len;
2400+ SK_U16 buf[ASF_MAX_UNICODESTRINGLEN];
2401+
2402+} STR_ASF_UNISTRING;
2403+
2404+
2405+// function prototypes
2406+SK_I8 AsfMac2Asci( SK_U8 *buf, SK_U32 *len, SK_U8 *mac );
2407+SK_I8 AsfIp2Asci( SK_U8 *buf, SK_U32 *len, SK_U8 *ip );
2408+SK_I8 AsfAsci2Mac( SK_U8 *buf, SK_U32 len, SK_U8 *mac );
2409+SK_I8 AsfAsci2Ip( SK_U8 *buf, SK_U32 len, SK_U8 *ip );
2410+SK_I8 AsfHex2Array( SK_U8 *buf, SK_U32 len, SK_U8 *array );
2411+SK_I8 AsfArray2Hex( SK_U8 *buf, SK_U32 len, SK_U8 *array );
2412+SK_I8 AsfHex2U8( SK_U8 *buf, SK_U8 *val );
2413+SK_I8 AsfInt2Hex( SK_U8 *buf, SK_U8 size, SK_U32 val );
2414+SK_I8 AsfDec2Int( SK_U8 *buf, SK_U8 size, SK_U32 *val );
2415+
2416+#ifdef __cplusplus
2417+}
2418+#endif // cpp
2419+
2420+#endif // asfwmi.h
2421+
2422diff -ruN linux/drivers/net/sk98lin/h/skgedrv.h linux-new/drivers/net/sk98lin/h/skgedrv.h
2423--- linux/drivers/net/sk98lin/h/skgedrv.h 2007-01-02 23:21:17.000000000 +0100
2424+++ linux-new/drivers/net/sk98lin/h/skgedrv.h 2006-10-13 11:18:49.000000000 +0200
2425@@ -2,23 +2,24 @@
2426 *
2427 * Name: skgedrv.h
2428 * Project: Gigabit Ethernet Adapters, Common Modules
2429- * Version: $Revision$
2430- * Date: $Date$
2431+ * Version: $Revision$
2432+ * Date: $Date$
2433 * Purpose: Interface with the driver
2434 *
2435 ******************************************************************************/
2436
2437 /******************************************************************************
2438 *
2439+ * LICENSE:
2440 * (C)Copyright 1998-2002 SysKonnect.
2441- * (C)Copyright 2002-2003 Marvell.
2442+ * (C)Copyright 2002-2006 Marvell.
2443 *
2444 * This program is free software; you can redistribute it and/or modify
2445 * it under the terms of the GNU General Public License as published by
2446 * the Free Software Foundation; either version 2 of the License, or
2447 * (at your option) any later version.
2448- *
2449 * The information in this file is provided "AS IS" without warranty.
2450+ * /LICENSE
2451 *
2452 ******************************************************************************/
2453
2454@@ -33,7 +34,7 @@
2455 * In case of the driver we put the definition of the events here.
2456 */
2457 #define SK_DRV_PORT_RESET 1 /* The port needs to be reset */
2458-#define SK_DRV_NET_UP 2 /* The net is operational */
2459+#define SK_DRV_NET_UP 2 /* The net is operational */
2460 #define SK_DRV_NET_DOWN 3 /* The net is down */
2461 #define SK_DRV_SWITCH_SOFT 4 /* Ports switch with both links connected */
2462 #define SK_DRV_SWITCH_HARD 5 /* Port switch due to link failure */
2463@@ -44,8 +45,11 @@
2464 #define SK_DRV_POWER_DOWN 10 /* Power down mode */
2465 #define SK_DRV_TIMER 11 /* Timer for free use */
2466 #ifdef SK_NO_RLMT
2467-#define SK_DRV_LINK_UP 12 /* Link Up event for driver */
2468+#define SK_DRV_LINK_UP 12 /* Link Up event for driver */
2469 #define SK_DRV_LINK_DOWN 13 /* Link Down event for driver */
2470 #endif
2471 #define SK_DRV_DOWNSHIFT_DET 14 /* Downshift 4-Pair / 2-Pair (YUKON only) */
2472+#define SK_DRV_RX_OVERFLOW 15 /* Receive Overflow */
2473+#define SK_DRV_LIPA_NOT_AN_ABLE 16 /* Link Partner not Auto-Negotiation able */
2474+#define SK_DRV_PEX_LINK_WIDTH 17 /* PEX negotiated Link width not maximum */
2475 #endif /* __INC_SKGEDRV_H_ */
2476diff -ruN linux/drivers/net/sk98lin/h/skgehw.h linux-new/drivers/net/sk98lin/h/skgehw.h
2477--- linux/drivers/net/sk98lin/h/skgehw.h 2007-01-02 23:21:17.000000000 +0100
2478+++ linux-new/drivers/net/sk98lin/h/skgehw.h 2006-10-13 10:18:34.000000000 +0200
2479@@ -2,23 +2,24 @@
2480 *
2481 * Name: skgehw.h
2482 * Project: Gigabit Ethernet Adapters, Common Modules
2483- * Version: $Revision$
2484- * Date: $Date$
2485+ * Version: $Revision$
2486+ * Date: $Date$
2487 * Purpose: Defines and Macros for the Gigabit Ethernet Adapter Product Family
2488 *
2489 ******************************************************************************/
2490
2491 /******************************************************************************
2492 *
2493+ * LICENSE:
2494 * (C)Copyright 1998-2002 SysKonnect.
2495- * (C)Copyright 2002-2003 Marvell.
2496+ * (C)Copyright 2002-2006 Marvell.
2497 *
2498 * This program is free software; you can redistribute it and/or modify
2499 * it under the terms of the GNU General Public License as published by
2500 * the Free Software Foundation; either version 2 of the License, or
2501 * (at your option) any later version.
2502- *
2503 * The information in this file is provided "AS IS" without warranty.
2504+ * /LICENSE
2505 *
2506 ******************************************************************************/
2507
2508@@ -114,6 +115,16 @@
2509 #define SHIFT1(x) ((x) << 1)
2510 #define SHIFT0(x) ((x) << 0)
2511
2512+/* Macro for arbitrary alignment of a given pointer */
2513+#define ALIGN_ADDR( ADDRESS, GRANULARITY ) { \
2514+ SK_UPTR addr = (SK_UPTR)(ADDRESS); \
2515+ if (addr & ((GRANULARITY)-1)) { \
2516+ addr += (GRANULARITY); \
2517+ addr &= ~(SK_UPTR)((GRANULARITY)-1); \
2518+ ADDRESS = (void *)addr; \
2519+ }\
2520+}
2521+
2522 /*
2523 * Configuration Space header
2524 * Since this module is used for different OS', those may be
2525@@ -132,34 +143,81 @@
2526 #define PCI_BIST 0x0f /* 8 bit Built-in selftest */
2527 #define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */
2528 #define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */
2529- /* Byte 0x18..0x2b: reserved */
2530+ /* Bytes 0x18..0x2b: reserved */
2531 #define PCI_SUB_VID 0x2c /* 16 bit Subsystem Vendor ID */
2532 #define PCI_SUB_ID 0x2e /* 16 bit Subsystem ID */
2533 #define PCI_BASE_ROM 0x30 /* 32 bit Expansion ROM Base Address */
2534-#define PCI_CAP_PTR 0x34 /* 8 bit Capabilities Ptr */
2535- /* Byte 0x35..0x3b: reserved */
2536+#define PCI_CAP_PTR 0x34 /* 8 bit Capabilities Pointer */
2537+ /* Bytes 0x35..0x3b: reserved */
2538 #define PCI_IRQ_LINE 0x3c /* 8 bit Interrupt Line */
2539 #define PCI_IRQ_PIN 0x3d /* 8 bit Interrupt Pin */
2540 #define PCI_MIN_GNT 0x3e /* 8 bit Min_Gnt */
2541 #define PCI_MAX_LAT 0x3f /* 8 bit Max_Lat */
2542 /* Device Dependent Region */
2543-#define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */
2544-#define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */
2545+#define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */
2546+#define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */
2547 /* Power Management Region */
2548-#define PCI_PM_CAP_ID 0x48 /* 8 bit Power Management Cap. ID */
2549-#define PCI_PM_NITEM 0x49 /* 8 bit Next Item Ptr */
2550-#define PCI_PM_CAP_REG 0x4a /* 16 bit Power Management Capabilities */
2551-#define PCI_PM_CTL_STS 0x4c /* 16 bit Power Manag. Control/Status */
2552+#define PCI_PM_CAP_ID 0x48 /* 8 bit Power Management Cap. ID */
2553+#define PCI_PM_NITEM 0x49 /* 8 bit PM Next Item Pointer */
2554+#define PCI_PM_CAP_REG 0x4a /* 16 bit Power Management Capabilities */
2555+#define PCI_PM_CTL_STS 0x4c /* 16 bit Power Manag. Control/Status */
2556 /* Byte 0x4e: reserved */
2557-#define PCI_PM_DAT_REG 0x4f /* 8 bit Power Manag. Data Register */
2558+#define PCI_PM_DAT_REG 0x4f /* 8 bit Power Manag. Data Register */
2559 /* VPD Region */
2560-#define PCI_VPD_CAP_ID 0x50 /* 8 bit VPD Cap. ID */
2561-#define PCI_VPD_NITEM 0x51 /* 8 bit Next Item Ptr */
2562-#define PCI_VPD_ADR_REG 0x52 /* 16 bit VPD Address Register */
2563-#define PCI_VPD_DAT_REG 0x54 /* 32 bit VPD Data Register */
2564- /* Byte 0x58..0x59: reserved */
2565-#define PCI_SER_LD_CTRL 0x5a /* 16 bit SEEPROM Loader Ctrl (YUKON only) */
2566- /* Byte 0x5c..0xff: reserved */
2567+#define PCI_VPD_CAP_ID 0x50 /* 8 bit VPD Cap. ID */
2568+#define PCI_VPD_NITEM 0x51 /* 8 bit VPD Next Item Pointer */
2569+#define PCI_VPD_ADR_REG 0x52 /* 16 bit VPD Address Register */
2570+#define PCI_VPD_DAT_REG 0x54 /* 32 bit VPD Data Register */
2571+ /* Bytes 0x58..0x59: reserved */
2572+#define PCI_SER_LD_CTRL 0x5a /* 16 bit SEEPROM Loader Ctrl (YUKON only) */
2573+ /* Bytes 0x5c..0xfc: used by Yukon-2 */
2574+#define PCI_MSI_CAP_ID 0x5c /* 8 bit MSI Capability ID Register */
2575+#define PCI_MSI_NITEM 0x5d /* 8 bit MSI Next Item Pointer */
2576+#define PCI_MSI_CTRL 0x5e /* 16 bit MSI Message Control */
2577+#define PCI_MSI_ADR_LO 0x60 /* 32 bit MSI Message Address (Lower) */
2578+#define PCI_MSI_ADR_HI 0x64 /* 32 bit MSI Message Address (Upper) */
2579+#define PCI_MSI_DATA 0x68 /* 16 bit MSI Message Data */
2580+ /* Bytes 0x6a..0x6b: reserved */
2581+#define PCI_X_CAP_ID 0x6c /* 8 bit PCI-X Capability ID Register */
2582+#define PCI_X_NITEM 0x6d /* 8 bit PCI-X Next Item Pointer */
2583+#define PCI_X_COMMAND 0x6e /* 16 bit PCI-X Command */
2584+#define PCI_X_PE_STAT 0x70 /* 32 bit PCI-X / PE Status */
2585+#define PCI_CAL_CTRL 0x74 /* 16 bit PCI Calibration Control Register */
2586+#define PCI_CAL_STAT 0x76 /* 16 bit PCI Calibration Status Register */
2587+#define PCI_DISC_CNT 0x78 /* 16 bit PCI Discard Counter */
2588+#define PCI_RETRY_CNT 0x7a /* 8 bit PCI Retry Counter */
2589+ /* Byte 0x7b: reserved */
2590+#define PCI_OUR_STATUS 0x7c /* 32 bit Adapter Status Register */
2591+#define PCI_OUR_REG_3 0x80 /* 32 bit Our Register 3 (Yukon-ECU only) */
2592+#define PCI_OUR_REG_4 0x84 /* 32 bit Our Register 4 (Yukon-ECU only) */
2593+#define PCI_OUR_REG_5 0x88 /* 32 bit Our Register 5 (Yukon-ECU only) */
2594+ /* Bytes 0x8c..0xdf: reserved */
2595+
2596+/* PCI Express Capability */
2597+#define PEX_CAP_ID 0xe0 /* 8 bit PEX Capability ID */
2598+#define PEX_NITEM 0xe1 /* 8 bit PEX Next Item Pointer */
2599+#define PEX_CAP_REG 0xe2 /* 16 bit PEX Capability Register */
2600+#define PEX_DEV_CAP 0xe4 /* 32 bit PEX Device Capabilities */
2601+#define PEX_DEV_CTRL 0xe8 /* 16 bit PEX Device Control */
2602+#define PEX_DEV_STAT 0xea /* 16 bit PEX Device Status */
2603+#define PEX_LNK_CAP 0xec /* 32 bit PEX Link Capabilities */
2604+#define PEX_LNK_CTRL 0xf0 /* 16 bit PEX Link Control */
2605+#define PEX_LNK_STAT 0xf2 /* 16 bit PEX Link Status */
2606+ /* Bytes 0xf4..0xff: reserved */
2607+
2608+/* PCI Express Extended Capabilities */
2609+#define PEX_ADV_ERR_REP 0x100 /* 32 bit PEX Advanced Error Reporting */
2610+#define PEX_UNC_ERR_STAT 0x104 /* 32 bit PEX Uncorr. Errors Status */
2611+#define PEX_UNC_ERR_MASK 0x108 /* 32 bit PEX Uncorr. Errors Mask */
2612+#define PEX_UNC_ERR_SEV 0x10c /* 32 bit PEX Uncorr. Errors Severity */
2613+#define PEX_COR_ERR_STAT 0x110 /* 32 bit PEX Correc. Errors Status */
2614+#define PEX_COR_ERR_MASK 0x114 /* 32 bit PEX Correc. Errors Mask */
2615+#define PEX_ADV_ERR_CAP_C 0x118 /* 32 bit PEX Advanced Error Cap./Ctrl */
2616+#define PEX_HEADER_LOG 0x11c /* 4x32 bit PEX Header Log Register */
2617+
2618+/* PCI Express Ack Timer for 1x Link */
2619+#define PEX_ACK_LAT_TOX1 0x228 /* 16 bit PEX Ack Latency Timeout x1 */
2620+#define PEX_ACK_RPLY_TOX1 0x22a /* 16 bit PEX Ack Reply Timeout val x1 */
2621
2622 /*
2623 * I2C Address (PCI Config)
2624@@ -180,13 +238,13 @@
2625 #define PCI_ADSTEP BIT_7S /* Address Stepping */
2626 #define PCI_PERREN BIT_6S /* Parity Report Response enable */
2627 #define PCI_VGA_SNOOP BIT_5S /* VGA palette snoop */
2628-#define PCI_MWIEN BIT_4S /* Memory write an inv cycl ena */
2629+#define PCI_MWIEN BIT_4S /* Memory write an inv cycl enable */
2630 #define PCI_SCYCEN BIT_3S /* Special Cycle enable */
2631 #define PCI_BMEN BIT_2S /* Bus Master enable */
2632 #define PCI_MEMEN BIT_1S /* Memory Space Access enable */
2633 #define PCI_IOEN BIT_0S /* I/O Space Access enable */
2634
2635-#define PCI_COMMAND_VAL (PCI_FBTEN | PCI_SERREN | PCI_PERREN | PCI_MWIEN |\
2636+#define PCI_COMMAND_VAL (PCI_INT_DIS | PCI_SERREN | PCI_PERREN | \
2637 PCI_BMEN | PCI_MEMEN | PCI_IOEN)
2638
2639 /* PCI_STATUS 16 bit Status */
2640@@ -220,7 +278,7 @@
2641
2642 /* PCI_HEADER_T 8 bit Header Type */
2643 #define PCI_HD_MF_DEV BIT_7S /* 0= single, 1= multi-func dev */
2644-#define PCI_HD_TYPE 0x7f /* Bit 6..0: Header Layout 0= normal */
2645+#define PCI_HD_TYPE 0x7f /* Bit 6..0: Header Layout (0=normal) */
2646
2647 /* PCI_BIST 8 bit Built-in selftest */
2648 /* Built-in Self test not supported (optional) */
2649@@ -229,33 +287,42 @@
2650 #define PCI_MEMSIZE 0x4000L /* use 16 kB Memory Base */
2651 #define PCI_MEMBASE_MSK 0xffffc000L /* Bit 31..14: Memory Base Address */
2652 #define PCI_MEMSIZE_MSK 0x00003ff0L /* Bit 13.. 4: Memory Size Req. */
2653-#define PCI_PREFEN BIT_3 /* Prefetchable */
2654-#define PCI_MEM_TYP (3L<<2) /* Bit 2.. 1: Memory Type */
2655+#define PCI_PREFEN BIT_3 /* Prefetch enable */
2656+#define PCI_MEM_TYP_MSK (3L<<1) /* Bit 2.. 1: Memory Type Mask */
2657+#define PCI_MEMSPACE BIT_0 /* Memory Space Indicator */
2658+
2659 #define PCI_MEM32BIT (0L<<1) /* Base addr anywhere in 32 Bit range */
2660 #define PCI_MEM1M (1L<<1) /* Base addr below 1 MegaByte */
2661 #define PCI_MEM64BIT (2L<<1) /* Base addr anywhere in 64 Bit range */
2662-#define PCI_MEMSPACE BIT_0 /* Memory Space Indicator */
2663
2664 /* PCI_BASE_2ND 32 bit 2nd Base address */
2665 #define PCI_IOBASE 0xffffff00L /* Bit 31.. 8: I/O Base address */
2666 #define PCI_IOSIZE 0x000000fcL /* Bit 7.. 2: I/O Size Requirements */
2667- /* Bit 1: reserved */
2668+ /* Bit 1: reserved */
2669 #define PCI_IOSPACE BIT_0 /* I/O Space Indicator */
2670
2671 /* PCI_BASE_ROM 32 bit Expansion ROM Base Address */
2672 #define PCI_ROMBASE_MSK 0xfffe0000L /* Bit 31..17: ROM Base address */
2673 #define PCI_ROMBASE_SIZ (0x1cL<<14) /* Bit 16..14: Treat as Base or Size */
2674 #define PCI_ROMSIZE (0x38L<<11) /* Bit 13..11: ROM Size Requirements */
2675- /* Bit 10.. 1: reserved */
2676+ /* Bit 10.. 1: reserved */
2677 #define PCI_ROMEN BIT_0 /* Address Decode enable */
2678
2679 /* Device Dependent Region */
2680 /* PCI_OUR_REG_1 32 bit Our Register 1 */
2681- /* Bit 31..29: reserved */
2682+ /* Bit 31..29: reserved */
2683 #define PCI_PHY_COMA BIT_28 /* Set PHY to Coma Mode (YUKON only) */
2684 #define PCI_TEST_CAL BIT_27 /* Test PCI buffer calib. (YUKON only) */
2685 #define PCI_EN_CAL BIT_26 /* Enable PCI buffer calib. (YUKON only) */
2686 #define PCI_VIO BIT_25 /* PCI I/O Voltage, 0 = 3.3V, 1 = 5V */
2687+/* Yukon-2 */
2688+#define PCI_Y2_PIG_ENA BIT_31 /* Enable Plug-in-Go (YUKON-2) */
2689+#define PCI_Y2_DLL_DIS BIT_30 /* Disable PCI DLL (YUKON-2) */
2690+#define PCI_Y2_PHY2_COMA BIT_29 /* Set PHY 2 to Coma Mode (YUKON-2) */
2691+#define PCI_Y2_PHY1_COMA BIT_28 /* Set PHY 1 to Coma Mode (YUKON-2) */
2692+#define PCI_Y2_PHY2_POWD BIT_27 /* Set PHY 2 to Power Down (YUKON-2) */
2693+#define PCI_Y2_PHY1_POWD BIT_26 /* Set PHY 1 to Power Down (YUKON-2) */
2694+ /* Bit 25: reserved */
2695 #define PCI_DIS_BOOT BIT_24 /* Disable BOOT via ROM */
2696 #define PCI_EN_IO BIT_23 /* Mapping to I/O space */
2697 #define PCI_EN_FPROM BIT_22 /* Enable FLASH mapping to memory */
2698@@ -266,9 +333,10 @@
2699 #define PCI_PAGE_32K (1L<<20) /* 32 k pages */
2700 #define PCI_PAGE_64K (2L<<20) /* 64 k pages */
2701 #define PCI_PAGE_128K (3L<<20) /* 128 k pages */
2702- /* Bit 19: reserved */
2703-#define PCI_PAGEREG (7L<<16) /* Bit 18..16: Page Register */
2704+ /* Bit 19: reserved */
2705+#define PCI_PAGEREG (7L<<16) /* Bit 18..16: Page Register */
2706 #define PCI_NOTAR BIT_15 /* No turnaround cycle */
2707+#define PCI_PEX_LEGNAT BIT_15 /* PEX PM legacy/native mode (YUKON-2) */
2708 #define PCI_FORCE_BE BIT_14 /* Assert all BEs on MR */
2709 #define PCI_DIS_MRL BIT_13 /* Disable Mem Read Line */
2710 #define PCI_DIS_MRM BIT_12 /* Disable Mem Read Multiple */
2711@@ -278,13 +346,21 @@
2712 #define PCI_DIS_PCI_CLK BIT_8 /* Disable PCI clock driving */
2713 #define PCI_SKEW_DAS (0xfL<<4) /* Bit 7.. 4: Skew Ctrl, DAS Ext */
2714 #define PCI_SKEW_BASE 0xfL /* Bit 3.. 0: Skew Ctrl, Base */
2715+#define PCI_CLS_OPT BIT_3 /* Cache Line Size opt. PCI-X (YUKON-2) */
2716
2717+/* Yukon-EC Ultra only */
2718+ /* Bit 14..10: reserved */
2719+#define PCI_PHY_LNK_TIM_MSK (3L<<8) /* Bit 9.. 8: GPHY Link Trigger Timer */
2720+#define PCI_ENA_L1_EVENT BIT_7 /* Enable PEX L1 Event */
2721+#define PCI_ENA_GPHY_LNK BIT_6 /* Enable PEX L1 on GPHY Link down */
2722+#define PCI_FORCE_PEX_L1 BIT_5 /* Force to PEX L1 */
2723+ /* Bit 4.. 0: reserved */
2724
2725 /* PCI_OUR_REG_2 32 bit Our Register 2 */
2726 #define PCI_VPD_WR_THR (0xffL<<24) /* Bit 31..24: VPD Write Threshold */
2727 #define PCI_DEV_SEL (0x7fL<<17) /* Bit 23..17: EEPROM Device Select */
2728 #define PCI_VPD_ROM_SZ (7L<<14) /* Bit 16..14: VPD ROM Size */
2729- /* Bit 13..12: reserved */
2730+ /* Bit 13..12: reserved */
2731 #define PCI_PATCH_DIR (0xfL<<8) /* Bit 11.. 8: Ext Patches dir 3..0 */
2732 #define PCI_PATCH_DIR_3 BIT_11
2733 #define PCI_PATCH_DIR_2 BIT_10
2734@@ -296,22 +372,21 @@
2735 #define PCI_EXT_PATCH_1 BIT_5
2736 #define PCI_EXT_PATCH_0 BIT_4
2737 #define PCI_EN_DUMMY_RD BIT_3 /* Enable Dummy Read */
2738-#define PCI_REV_DESC BIT_2 /* Reverse Desc. Bytes */
2739- /* Bit 1: reserved */
2740+#define PCI_REV_DESC BIT_2 /* Reverse Descriptor Bytes */
2741+ /* Bit 1: reserved */
2742 #define PCI_USEDATA64 BIT_0 /* Use 64Bit Data bus ext */
2743
2744-
2745-/* Power Management Region */
2746+/* Power Management (PM) Region */
2747 /* PCI_PM_CAP_REG 16 bit Power Management Capabilities */
2748-#define PCI_PME_SUP_MSK (0x1f<<11) /* Bit 15..11: PM Event Support Mask */
2749-#define PCI_PME_D3C_SUP BIT_15S /* PME from D3cold Support (if Vaux) */
2750+#define PCI_PME_SUP_MSK (0x1f<<11) /* Bit 15..11: PM Event (PME) Supp. Mask */
2751+#define PCI_PME_D3C_SUP BIT_15S /* PME from D3cold Support (if VAUX) */
2752 #define PCI_PME_D3H_SUP BIT_14S /* PME from D3hot Support */
2753 #define PCI_PME_D2_SUP BIT_13S /* PME from D2 Support */
2754 #define PCI_PME_D1_SUP BIT_12S /* PME from D1 Support */
2755 #define PCI_PME_D0_SUP BIT_11S /* PME from D0 Support */
2756 #define PCI_PM_D2_SUP BIT_10S /* D2 Support in 33 MHz mode */
2757 #define PCI_PM_D1_SUP BIT_9S /* D1 Support */
2758- /* Bit 8.. 6: reserved */
2759+ /* Bit 8.. 6: reserved */
2760 #define PCI_PM_DSI BIT_5S /* Device Specific Initialization */
2761 #define PCI_PM_APS BIT_4S /* Auxialiary Power Source */
2762 #define PCI_PME_CLOCK BIT_3S /* PM Event Clock */
2763@@ -322,7 +397,7 @@
2764 #define PCI_PM_DAT_SCL (3<<13) /* Bit 14..13: Data Reg. scaling factor */
2765 #define PCI_PM_DAT_SEL (0xf<<9) /* Bit 12.. 9: PM data selector field */
2766 #define PCI_PME_EN BIT_8S /* Enable PME# generation (YUKON only) */
2767- /* Bit 7.. 2: reserved */
2768+ /* Bit 7.. 2: reserved */
2769 #define PCI_PM_STATE_MSK 3 /* Bit 1.. 0: Power Management State */
2770
2771 #define PCI_PM_STATE_D0 0 /* D0: Operational (default) */
2772@@ -333,7 +408,153 @@
2773 /* VPD Region */
2774 /* PCI_VPD_ADR_REG 16 bit VPD Address Register */
2775 #define PCI_VPD_FLAG BIT_15S /* starts VPD rd/wr cycle */
2776-#define PCI_VPD_ADR_MSK 0x7fffL /* Bit 14.. 0: VPD address mask */
2777+#define PCI_VPD_ADR_MSK 0x7fffL /* Bit 14.. 0: VPD Address Mask */
2778+
2779+/* PCI_OUR_STATUS 32 bit Adapter Status Register (Yukon-2) */
2780+#define PCI_OS_PCI64B BIT_31 /* Conventional PCI 64 bits Bus */
2781+#define PCI_OS_PCIX BIT_30 /* PCI-X Bus */
2782+#define PCI_OS_MODE_MSK (3L<<28) /* Bit 29..28: PCI-X Bus Mode Mask */
2783+#define PCI_OS_PCI66M BIT_27 /* PCI 66 MHz Bus */
2784+#define PCI_OS_PCI_X BIT_26 /* PCI/PCI-X Bus (0 = PEX) */
2785+#define PCI_OS_DLLE_MSK (3L<<24) /* Bit 25..24: DLL Status Indication */
2786+#define PCI_OS_DLLR_MSK (0xfL<<20) /* Bit 23..20: DLL Row Counters Values */
2787+#define PCI_OS_DLLC_MSK (0xfL<<16) /* Bit 19..16: DLL Col. Counters Values */
2788+ /* Bit 15.. 8: reserved */
2789+
2790+#define PCI_OS_SPEED(val) ((val & PCI_OS_MODE_MSK) >> 28) /* PCI-X Speed */
2791+/* possible values for the speed field of the register */
2792+#define PCI_OS_SPD_PCI 0 /* PCI Conventional Bus */
2793+#define PCI_OS_SPD_X66 1 /* PCI-X 66MHz Bus */
2794+#define PCI_OS_SPD_X100 2 /* PCI-X 100MHz Bus */
2795+#define PCI_OS_SPD_X133 3 /* PCI-X 133MHz Bus */
2796+
2797+/* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */
2798+ /* Bit 31..18: reserved */
2799+#define P_CLK_COR_REGS_D0_DIS BIT_17 /* Disable Clock Core Regs in D0 */
2800+#define P_CLK_PCI_REGS_D0_DIS BIT_16 /* Disable Clock PCI Regs in D0 */
2801+#define P_CLK_COR_YTB_ARB_DIS BIT_15 /* Disable Clock YTB Arbiter */
2802+#define P_CLK_MAC_LNK1_D3_DIS BIT_14 /* Disable Clock MAC Link1 in D3 */
2803+#define P_CLK_COR_LNK1_D0_DIS BIT_13 /* Disable Clock Core Link1 in D0 */
2804+#define P_CLK_MAC_LNK1_D0_DIS BIT_12 /* Disable Clock MAC Link1 in D0 */
2805+#define P_CLK_COR_LNK1_D3_DIS BIT_11 /* Disable Clock Core Link1 in D3 */
2806+#define P_CLK_PCI_MST_ARB_DIS BIT_10 /* Disable Clock PCI Master Arb. */
2807+#define P_CLK_COR_REGS_D3_DIS BIT_9 /* Disable Clock Core Regs in D3 */
2808+#define P_CLK_PCI_REGS_D3_DIS BIT_8 /* Disable Clock PCI Regs in D3 */
2809+#define P_CLK_REF_LNK1_GM_DIS BIT_7 /* Disable Clock Ref. Link1 GMAC */
2810+#define P_CLK_COR_LNK1_GM_DIS BIT_6 /* Disable Clock Core Link1 GMAC */
2811+#define P_CLK_PCI_COMMON_DIS BIT_5 /* Disable Clock PCI Common */
2812+#define P_CLK_COR_COMMON_DIS BIT_4 /* Disable Clock Core Common */
2813+#define P_CLK_PCI_LNK1_BMU_DIS BIT_3 /* Disable Clock PCI Link1 BMU */
2814+#define P_CLK_COR_LNK1_BMU_DIS BIT_2 /* Disable Clock Core Link1 BMU */
2815+#define P_CLK_PCI_LNK1_BIU_DIS BIT_1 /* Disable Clock PCI Link1 BIU */
2816+#define P_CLK_COR_LNK1_BIU_DIS BIT_0 /* Disable Clock Core Link1 BIU */
2817+
2818+/* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
2819+#define P_PEX_LTSSM_STAT_MSK (0x7fL<<25) /* Bit 31..25: PEX LTSSM Mask */
2820+ /* (Link Training & Status State Machine) */
2821+ /* Bit 24: reserved */
2822+#define P_TIMER_VALUE_MSK (0xffL<<16) /* Bit 23..16: Timer Value Mask */
2823+#define P_FORCE_ASPM_REQUEST BIT_15 /* Force ASPM Request (A1 only) */
2824+ /* (Active State Power Management) */
2825+ /* Bit 14..12: Force ASPM on Event */
2826+#define P_ASPM_GPHY_LINK_DOWN BIT_14 /* GPHY Link Down (A1 only) */
2827+#define P_ASPM_INT_FIFO_EMPTY BIT_13 /* Internal FIFO Empty (A1 only) */
2828+#define P_ASPM_CLKRUN_REQUEST BIT_12 /* CLKRUN Request (A1 only) */
2829+ /* Bit 11.. 7: reserved */
2830+#define P_PIN63_LINK_LED_ENA BIT_8 /* Enable Pin #63 as Link LED (A3) */
2831+#define P_ASPM_FORCE_ASPM_L1 BIT_7 /* Force ASPM L1 Enable (A1b only) */
2832+#define P_ASPM_FORCE_ASPM_L0S BIT_6 /* Force ASPM L0s Enable (A1b only) */
2833+#define P_ASPM_FORCE_CLKREQ_PIN BIT_5 /* Force CLKREQn pin low (A1b only) */
2834+#define P_ASPM_FORCE_CLKREQ_ENA BIT_4 /* Force CLKREQ Enable (A1b only) */
2835+#define P_ASPM_CLKREQ_PAD_CTL BIT_3 /* CLKREQ PAD Control (A1 only) */
2836+#define P_ASPM_A1_MODE_SELECT BIT_2 /* A1 Mode Select (A1 only) */
2837+#define P_CLK_GATE_PEX_UNIT_ENA BIT_1 /* Enable Gate PEX Unit Clock */
2838+#define P_CLK_GATE_ROOT_COR_ENA BIT_0 /* Enable Gate Root Core Clock */
2839+
2840+#define P_PEX_LTSSM_STAT(x) (SHIFT25(x) & P_PEX_LTSSM_STAT_MSK)
2841+#define P_PEX_LTSSM_L1_STAT 0x34
2842+#define P_PEX_LTSSM_DET_STAT 0x01
2843+
2844+#define P_ASPM_CONTROL_MSK (P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN | \
2845+ P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY | \
2846+ P_PIN63_LINK_LED_ENA)
2847+
2848+/* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */
2849+ /* Bit 31..27: reserved */
2850+ /* Bit 26..16: Release Clock on Event */
2851+#define P_REL_PCIE_RST_DE_ASS BIT_26 /* PCIe Reset De-Asserted */
2852+#define P_REL_GPHY_REC_PACKET BIT_25 /* GPHY Received Packet */
2853+#define P_REL_INT_FIFO_N_EMPTY BIT_24 /* Internal FIFO Not Empty */
2854+#define P_REL_MAIN_PWR_AVAIL BIT_23 /* Main Power Available */
2855+#define P_REL_CLKRUN_REQ_REL BIT_22 /* CLKRUN Request Release */
2856+#define P_REL_PCIE_RESET_ASS BIT_21 /* PCIe Reset Asserted */
2857+#define P_REL_PME_ASSERTED BIT_20 /* PME Asserted */
2858+#define P_REL_PCIE_EXIT_L1_ST BIT_19 /* PCIe Exit L1 State */
2859+#define P_REL_LOADER_NOT_FIN BIT_18 /* EPROM Loader Not Finished */
2860+#define P_REL_PCIE_RX_EX_IDLE BIT_17 /* PCIe Rx Exit Electrical Idle State */
2861+#define P_REL_GPHY_LINK_UP BIT_16 /* GPHY Link Up */
2862+ /* Bit 15..11: reserved */
2863+ /* Bit 10.. 0: Mask for Gate Clock */
2864+#define P_GAT_PCIE_RST_DE_ASS BIT_10 /* PCIe Reset De-Asserted */
2865+#define P_GAT_GPHY_N_REC_PACKET BIT_9 /* GPHY Not Received Packet */
2866+#define P_GAT_INT_FIFO_EMPTY BIT_8 /* Internal FIFO Empty */
2867+#define P_GAT_MAIN_PWR_N_AVAIL BIT_7 /* Main Power Not Available */
2868+#define P_GAT_CLKRUN_REQ_REL BIT_6 /* CLKRUN Not Requested */
2869+#define P_GAT_PCIE_RESET_ASS BIT_5 /* PCIe Reset Asserted */
2870+#define P_GAT_PME_DE_ASSERTED BIT_4 /* PME De-Asserted */
2871+#define P_GAT_PCIE_ENTER_L1_ST BIT_3 /* PCIe Enter L1 State */
2872+#define P_GAT_LOADER_FINISHED BIT_2 /* EPROM Loader Finished */
2873+#define P_GAT_PCIE_RX_EL_IDLE BIT_1 /* PCIe Rx Electrical Idle State */
2874+#define P_GAT_GPHY_LINK_DOWN BIT_0 /* GPHY Link Down */
2875+
2876+/* PEX_DEV_CTRL 16 bit PEX Device Control (Yukon-2) */
2877+ /* Bit 15 reserved */
2878+#define PEX_DC_MAX_RRS_MSK (7<<12) /* Bit 14..12: Max. Read Request Size */
2879+#define PEX_DC_EN_NO_SNOOP BIT_11S /* Enable No Snoop */
2880+#define PEX_DC_EN_AUX_POW BIT_10S /* Enable AUX Power */
2881+#define PEX_DC_EN_PHANTOM BIT_9S /* Enable Phantom Functions */
2882+#define PEX_DC_EN_EXT_TAG BIT_8S /* Enable Extended Tag Field */
2883+#define PEX_DC_MAX_PLS_MSK (7<<5) /* Bit 7.. 5: Max. Payload Size Mask */
2884+#define PEX_DC_EN_REL_ORD BIT_4S /* Enable Relaxed Ordering */
2885+#define PEX_DC_EN_UNS_RQ_RP BIT_3S /* Enable Unsupported Request Reporting */
2886+#define PEX_DC_EN_FAT_ER_RP BIT_2S /* Enable Fatal Error Reporting */
2887+#define PEX_DC_EN_NFA_ER_RP BIT_1S /* Enable Non-Fatal Error Reporting */
2888+#define PEX_DC_EN_COR_ER_RP BIT_0S /* Enable Correctable Error Reporting */
2889+
2890+#define PEX_DC_MAX_RD_RQ_SIZE(x) (SHIFT12(x) & PEX_DC_MAX_RRS_MSK)
2891+
2892+/* PEX_LNK_CAP 32 bit PEX Link Capabilities */
2893+#define PEX_CAP_MAX_WI_MSK (0x3f<<4) /* Bit 9.. 4: Max. Link Width Mask */
2894+#define PEX_CAP_MAX_SP_MSK 0x0f /* Bit 3.. 0: Max. Link Speed Mask */
2895+
2896+/* PEX_LNK_CTRL 16 bit PEX Link Control (Yukon-2) */
2897+#define PEX_LC_CLK_PM_ENA BIT_8S /* Enable Clock Power Management (CLKREQ) */
2898+
2899+/* PEX_LNK_STAT 16 bit PEX Link Status (Yukon-2) */
2900+ /* Bit 15..13 reserved */
2901+#define PEX_LS_SLOT_CLK_CFG BIT_12S /* Slot Clock Config */
2902+#define PEX_LS_LINK_TRAIN BIT_11S /* Link Training */
2903+#define PEX_LS_TRAIN_ERROR BIT_10S /* Training Error */
2904+#define PEX_LS_LINK_WI_MSK (0x3f<<4) /* Bit 9.. 4: Neg. Link Width Mask */
2905+#define PEX_LS_LINK_SP_MSK 0x0f /* Bit 3.. 0: Link Speed Mask */
2906+
2907+/* PEX_UNC_ERR_STAT 16 bit PEX Uncorrectable Errors Status (Yukon-2) */
2908+ /* Bit 31..21 reserved */
2909+#define PEX_UNSUP_REQ BIT_20 /* Unsupported Request Error */
2910+ /* ECRC Error (not supported) */
2911+#define PEX_MALFOR_TLP BIT_18 /* Malformed TLP */
2912+#define PEX_RX_OV BIT_17 /* Receiver Overflow (not supported) */
2913+#define PEX_UNEXP_COMP BIT_16 /* Unexpected Completion */
2914+ /* Completer Abort (not supported) */
2915+#define PEX_COMP_TO BIT_14 /* Completion Timeout */
2916+#define PEX_FLOW_CTRL_P BIT_13 /* Flow Control Protocol Error */
2917+#define PEX_POIS_TLP BIT_12 /* Poisoned TLP */
2918+ /* Bit 11.. 5: reserved */
2919+#define PEX_DATA_LINK_P BIT_4 /* Data Link Protocol Error */
2920+ /* Bit 3.. 1: reserved */
2921+ /* Training Error (not supported) */
2922+
2923+#define PEX_FATAL_ERRORS (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P)
2924
2925 /* Control Register File (Address Map) */
2926
2927@@ -342,15 +563,21 @@
2928 */
2929 #define B0_RAP 0x0000 /* 8 bit Register Address Port */
2930 /* 0x0001 - 0x0003: reserved */
2931-#define B0_CTST 0x0004 /* 16 bit Control/Status register */
2932-#define B0_LED 0x0006 /* 8 Bit LED register */
2933+#define B0_CTST 0x0004 /* 16 bit Control/Status Register */
2934+#define B0_LED 0x0006 /* 8 Bit LED Register */
2935 #define B0_POWER_CTRL 0x0007 /* 8 Bit Power Control reg (YUKON only) */
2936 #define B0_ISRC 0x0008 /* 32 bit Interrupt Source Register */
2937 #define B0_IMSK 0x000c /* 32 bit Interrupt Mask Register */
2938 #define B0_HWE_ISRC 0x0010 /* 32 bit HW Error Interrupt Src Reg */
2939 #define B0_HWE_IMSK 0x0014 /* 32 bit HW Error Interrupt Mask Reg */
2940-#define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg */
2941- /* 0x001c: reserved */
2942+#define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg 1 */
2943+
2944+/* Special ISR registers (Yukon-2 only) */
2945+#define B0_Y2_SP_ISRC2 0x001c /* 32 bit Special Interrupt Source Reg 2 */
2946+#define B0_Y2_SP_ISRC3 0x0020 /* 32 bit Special Interrupt Source Reg 3 */
2947+#define B0_Y2_SP_EISR 0x0024 /* 32 bit Enter ISR Register */
2948+#define B0_Y2_SP_LISR 0x0028 /* 32 bit Leave ISR Register */
2949+#define B0_Y2_SP_ICR 0x002c /* 32 bit Interrupt Control Register */
2950
2951 /* B0 XMAC 1 registers (GENESIS only) */
2952 #define B0_XM1_IMSK 0x0020 /* 16 bit r/w XMAC 1 Interrupt Mask Register*/
2953@@ -372,7 +599,7 @@
2954 #define B0_XM2_PHY_DATA 0x0054 /* 16 bit r/w XMAC 2 PHY Data Register */
2955 /* 0x0056 - 0x005f: reserved */
2956
2957-/* BMU Control Status Registers */
2958+/* BMU Control Status Registers (Yukon and Genesis) */
2959 #define B0_R1_CSR 0x0060 /* 32 bit BMU Ctrl/Stat Rx Queue 1 */
2960 #define B0_R2_CSR 0x0064 /* 32 bit BMU Ctrl/Stat Rx Queue 2 */
2961 #define B0_XS1_CSR 0x0068 /* 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
2962@@ -390,7 +617,7 @@
2963 /*
2964 * Bank 2
2965 */
2966-/* NA reg = 48 bit Network Address Register, 3x16 or 8x8 bit readable */
2967+/* NA reg = 48 bit Network Address Register, 3x16 or 6x8 bit readable */
2968 #define B2_MAC_1 0x0100 /* NA reg MAC Address 1 */
2969 /* 0x0106 - 0x0107: reserved */
2970 #define B2_MAC_2 0x0108 /* NA reg MAC Address 2 */
2971@@ -400,14 +627,23 @@
2972 #define B2_CONN_TYP 0x0118 /* 8 bit Connector type */
2973 #define B2_PMD_TYP 0x0119 /* 8 bit PMD type */
2974 #define B2_MAC_CFG 0x011a /* 8 bit MAC Configuration / Chip Revision */
2975-#define B2_CHIP_ID 0x011b /* 8 bit Chip Identification Number */
2976- /* Eprom registers are currently of no use */
2977+#define B2_CHIP_ID 0x011b /* 8 bit Chip Identification Number */
2978+ /* Eprom registers */
2979 #define B2_E_0 0x011c /* 8 bit EPROM Byte 0 (ext. SRAM size */
2980+/* Yukon and Genesis */
2981 #define B2_E_1 0x011d /* 8 bit EPROM Byte 1 (PHY type) */
2982 #define B2_E_2 0x011e /* 8 bit EPROM Byte 2 */
2983+/* Yukon-2 */
2984+#define B2_Y2_CLK_GATE 0x011d /* 8 bit Clock Gating (Yukon-2) */
2985+#define B2_Y2_HW_RES 0x011e /* 8 bit HW Resources (Yukon-2) */
2986+
2987 #define B2_E_3 0x011f /* 8 bit EPROM Byte 3 */
2988+
2989+/* Yukon and Genesis */
2990 #define B2_FAR 0x0120 /* 32 bit Flash-Prom Addr Reg/Cnt */
2991 #define B2_FDP 0x0124 /* 8 bit Flash-Prom Data Port */
2992+/* Yukon-2 */
2993+#define B2_Y2_CLK_CTRL 0x0120 /* 32 bit Core Clock Frequency Control */
2994 /* 0x0125 - 0x0127: reserved */
2995 #define B2_LD_CTRL 0x0128 /* 8 bit EPROM loader control register */
2996 #define B2_LD_TEST 0x0129 /* 8 bit EPROM loader test register */
2997@@ -439,6 +675,10 @@
2998 #define B2_BSC_CTRL 0x0178 /* 8 bit Blink Source Counter Control */
2999 #define B2_BSC_STAT 0x0179 /* 8 bit Blink Source Counter Status */
3000 #define B2_BSC_TST 0x017a /* 16 bit Blink Source Counter Test Reg */
3001+
3002+/* Yukon-2 */
3003+#define Y2_PEX_PHY_DATA 0x0170 /* 16 bit PEX PHY Data Register */
3004+#define Y2_PEX_PHY_ADDR 0x0172 /* 16 bit PEX PHY Address Register */
3005 /* 0x017c - 0x017f: reserved */
3006
3007 /*
3008@@ -448,9 +688,14 @@
3009 #define B3_RAM_ADDR 0x0180 /* 32 bit RAM Address, to read or write */
3010 #define B3_RAM_DATA_LO 0x0184 /* 32 bit RAM Data Word (low dWord) */
3011 #define B3_RAM_DATA_HI 0x0188 /* 32 bit RAM Data Word (high dWord) */
3012+#define B3_RAM_PARITY 0x018c /* 8 bit RAM Parity (Yukon-ECU A1) */
3013+
3014+#define SELECT_RAM_BUFFER(rb, addr) (addr | (rb << 6)) /* Yukon-2 only */
3015+
3016 /* 0x018c - 0x018f: reserved */
3017
3018 /* RAM Interface Registers */
3019+/* Yukon-2: use SELECT_RAM_BUFFER() to access the RAM buffer */
3020 /*
3021 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
3022 * not usable in SW. Please notice these are NOT real timeouts, these are
3023@@ -517,8 +762,8 @@
3024 /* 0x01ea - 0x01eb: reserved */
3025 #define B3_PA_TOVAL_TX2 0x01ec /* 16 bit Timeout Val Tx Path MAC 2 */
3026 /* 0x01ee - 0x01ef: reserved */
3027-#define B3_PA_CTRL 0x01f0 /* 16 bit Packet Arbiter Ctrl Register */
3028-#define B3_PA_TEST 0x01f2 /* 16 bit Packet Arbiter Test Register */
3029+#define B3_PA_CTRL 0x01f0 /* 16 bit Packet Arbiter Ctrl Register */
3030+#define B3_PA_TEST 0x01f2 /* 16 bit Packet Arbiter Test Register */
3031 /* 0x01f4 - 0x01ff: reserved */
3032
3033 /*
3034@@ -532,7 +777,16 @@
3035 #define TXA_CTRL 0x0210 /* 8 bit Tx Arbiter Control Register */
3036 #define TXA_TEST 0x0211 /* 8 bit Tx Arbiter Test Register */
3037 #define TXA_STAT 0x0212 /* 8 bit Tx Arbiter Status Register */
3038- /* 0x0213 - 0x027f: reserved */
3039+ /* 0x0213 - 0x021f: reserved */
3040+
3041+ /* RSS key registers for Yukon-2 Family */
3042+#define B4_RSS_KEY 0x0220 /* 4x32 bit RSS Key register (Yukon-2) */
3043+ /* RSS key register offsets */
3044+#define KEY_IDX_0 0 /* offset for location of KEY 0 */
3045+#define KEY_IDX_1 4 /* offset for location of KEY 1 */
3046+#define KEY_IDX_2 8 /* offset for location of KEY 2 */
3047+#define KEY_IDX_3 12 /* offset for location of KEY 3 */
3048+
3049 /* 0x0280 - 0x0292: MAC 2 */
3050 /* 0x0213 - 0x027f: reserved */
3051
3052@@ -556,10 +810,10 @@
3053
3054 /* Queue Register Offsets, use Q_ADDR() to access */
3055 #define Q_D 0x00 /* 8*32 bit Current Descriptor */
3056-#define Q_DA_L 0x20 /* 32 bit Current Descriptor Address Low dWord */
3057-#define Q_DA_H 0x24 /* 32 bit Current Descriptor Address High dWord */
3058-#define Q_AC_L 0x28 /* 32 bit Current Address Counter Low dWord */
3059-#define Q_AC_H 0x2c /* 32 bit Current Address Counter High dWord */
3060+#define Q_DA_L 0x20 /* 32 bit Current Descriptor Address Low DWord */
3061+#define Q_DA_H 0x24 /* 32 bit Current Descriptor Address High DWord */
3062+#define Q_AC_L 0x28 /* 32 bit Current Address Counter Low DWord */
3063+#define Q_AC_H 0x2c /* 32 bit Current Address Counter High DWord */
3064 #define Q_BC 0x30 /* 32 bit Current Byte Counter */
3065 #define Q_CSR 0x34 /* 32 bit BMU Control/Status Register */
3066 #define Q_F 0x38 /* 32 bit Flag Register */
3067@@ -570,8 +824,56 @@
3068 #define Q_T1_SV 0x3f /* 8 bit Test Register 1 Supervisor SM */
3069 #define Q_T2 0x40 /* 32 bit Test Register 2 */
3070 #define Q_T3 0x44 /* 32 bit Test Register 3 */
3071+
3072+/* Yukon-2 */
3073+#define Q_DONE 0x24 /* 16 bit Done Index */
3074+
3075+#define Q_WM 0x40 /* 16 bit FIFO Watermark */
3076+#define Q_AL 0x42 /* 8 bit FIFO Alignment */
3077+ /* 0x43: reserved */
3078+/* RX Queue */
3079+#define Q_RX_RSP 0x44 /* 16 bit FIFO Read Shadow Pointer */
3080+#define Q_RX_RSL 0x46 /* 8 bit FIFO Read Shadow Level */
3081+ /* 0x47: reserved */
3082+#define Q_RX_RP 0x48 /* 8 bit FIFO Read Pointer */
3083+ /* 0x49: reserved */
3084+#define Q_RX_RL 0x4a /* 8 bit FIFO Read Level */
3085+ /* 0x4b: reserved */
3086+#define Q_RX_WP 0x4c /* 8 bit FIFO Write Pointer */
3087+#define Q_RX_WSP 0x4d /* 8 bit FIFO Write Shadow Pointer */
3088+#define Q_RX_WL 0x4e /* 8 bit FIFO Write Level */
3089+#define Q_RX_WSL 0x4f /* 8 bit FIFO Write Shadow Level */
3090+/* TX Queue */
3091+#define Q_TX_WSP 0x44 /* 16 bit FIFO Write Shadow Pointer */
3092+#define Q_TX_WSL 0x46 /* 8 bit FIFO Write Shadow Level */
3093+ /* 0x47: reserved */
3094+#define Q_TX_WP 0x48 /* 8 bit FIFO Write Pointer */
3095+ /* 0x49: reserved */
3096+#define Q_TX_WL 0x4a /* 8 bit FIFO Write Level */
3097+ /* 0x4b: reserved */
3098+#define Q_TX_RP 0x4c /* 8 bit FIFO Read Pointer */
3099+ /* 0x4d: reserved */
3100+#define Q_TX_RL 0x4e /* 8 bit FIFO Read Level */
3101+ /* 0x4f: reserved */
3102+
3103 /* 0x48 - 0x7f: reserved */
3104
3105+/* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/
3106+#define Y2_B8_PREF_REGS 0x0450
3107+
3108+#define PREF_UNIT_CTRL_REG 0x00 /* 32 bit Prefetch Control register */
3109+#define PREF_UNIT_LAST_IDX_REG 0x04 /* 16 bit Last Index */
3110+#define PREF_UNIT_ADDR_LOW_REG 0x08 /* 32 bit List start addr, low part */
3111+#define PREF_UNIT_ADDR_HI_REG 0x0c /* 32 bit List start addr, high part*/
3112+#define PREF_UNIT_GET_IDX_REG 0x10 /* 16 bit Get Index */
3113+#define PREF_UNIT_PUT_IDX_REG 0x14 /* 16 bit Put Index */
3114+#define PREF_UNIT_FIFO_WP_REG 0x20 /* 8 bit FIFO write pointer */
3115+#define PREF_UNIT_FIFO_RP_REG 0x24 /* 8 bit FIFO read pointer */
3116+#define PREF_UNIT_FIFO_WM_REG 0x28 /* 8 bit FIFO watermark */
3117+#define PREF_UNIT_FIFO_LEV_REG 0x2c /* 8 bit FIFO level */
3118+
3119+#define PREF_UNIT_MASK_IDX 0x0fff
3120+
3121 /*
3122 * Bank 16 - 23
3123 */
3124@@ -583,17 +885,17 @@
3125 #define RB_END 0x04 /* 32 bit RAM Buffer End Address */
3126 #define RB_WP 0x08 /* 32 bit RAM Buffer Write Pointer */
3127 #define RB_RP 0x0c /* 32 bit RAM Buffer Read Pointer */
3128-#define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Pack */
3129-#define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Pack */
3130+#define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Packet */
3131+#define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Packet */
3132 #define RB_RX_UTHP 0x18 /* 32 bit Rx Upper Threshold, High Prio */
3133 #define RB_RX_LTHP 0x1c /* 32 bit Rx Lower Threshold, High Prio */
3134 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
3135 #define RB_PC 0x20 /* 32 bit RAM Buffer Packet Counter */
3136 #define RB_LEV 0x24 /* 32 bit RAM Buffer Level Register */
3137-#define RB_CTRL 0x28 /* 8 bit RAM Buffer Control Register */
3138+#define RB_CTRL 0x28 /* 32 bit RAM Buffer Control Register */
3139 #define RB_TST1 0x29 /* 8 bit RAM Buffer Test Register 1 */
3140-#define RB_TST2 0x2A /* 8 bit RAM Buffer Test Register 2 */
3141- /* 0x2c - 0x7f: reserved */
3142+#define RB_TST2 0x2a /* 8 bit RAM Buffer Test Register 2 */
3143+ /* 0x2b - 0x7f: reserved */
3144
3145 /*
3146 * Bank 24
3147@@ -603,7 +905,7 @@
3148 * use MR_ADDR() to access
3149 */
3150 #define RX_MFF_EA 0x0c00 /* 32 bit Receive MAC FIFO End Address */
3151-#define RX_MFF_WP 0x0c04 /* 32 bit Receive MAC FIFO Write Pointer */
3152+#define RX_MFF_WP 0x0c04 /* 32 bit Receive MAC FIFO Write Pointer */
3153 /* 0x0c08 - 0x0c0b: reserved */
3154 #define RX_MFF_RP 0x0c0c /* 32 bit Receive MAC FIFO Read Pointer */
3155 #define RX_MFF_PC 0x0c10 /* 32 bit Receive MAC FIFO Packet Cnt */
3156@@ -628,20 +930,23 @@
3157 #define LNK_LED_REG 0x0c3c /* 8 bit Link LED Register */
3158 /* 0x0c3d - 0x0c3f: reserved */
3159
3160-/* Receive GMAC FIFO (YUKON only), use MR_ADDR() to access */
3161+/* Receive GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
3162 #define RX_GMF_EA 0x0c40 /* 32 bit Rx GMAC FIFO End Address */
3163 #define RX_GMF_AF_THR 0x0c44 /* 32 bit Rx GMAC FIFO Almost Full Thresh. */
3164 #define RX_GMF_CTRL_T 0x0c48 /* 32 bit Rx GMAC FIFO Control/Test */
3165 #define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */
3166 #define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */
3167- /* 0x0c54 - 0x0c5f: reserved */
3168-#define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */
3169+#define RX_GMF_TR_THR 0x0c54 /* 32 bit Rx Truncation Threshold (Yukon-2) */
3170+#define RX_GMF_UP_THR 0x0c58 /* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */
3171+#define RX_GMF_LP_THR 0x0c5a /* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */
3172+#define RX_GMF_VLAN 0x0c5c /* 32 bit Rx VLAN Type Register (Yukon-2) */
3173+#define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */
3174 /* 0x0c64 - 0x0c67: reserved */
3175-#define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */
3176+#define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */
3177 /* 0x0c6c - 0x0c6f: reserved */
3178-#define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */
3179+#define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */
3180 /* 0x0c74 - 0x0c77: reserved */
3181-#define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */
3182+#define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */
3183 /* 0x0c7c - 0x0c7f: reserved */
3184
3185 /*
3186@@ -658,7 +963,7 @@
3187 * use MR_ADDR() to access
3188 */
3189 #define TX_MFF_EA 0x0d00 /* 32 bit Transmit MAC FIFO End Address */
3190-#define TX_MFF_WP 0x0d04 /* 32 bit Transmit MAC FIFO WR Pointer */
3191+#define TX_MFF_WP 0x0d04 /* 32 bit Transmit MAC FIFO WR Pointer */
3192 #define TX_MFF_WSP 0x0d08 /* 32 bit Transmit MAC FIFO WR Shadow Ptr */
3193 #define TX_MFF_RP 0x0d0c /* 32 bit Transmit MAC FIFO RD Pointer */
3194 #define TX_MFF_PC 0x0d10 /* 32 bit Transmit MAC FIFO Packet Cnt */
3195@@ -676,18 +981,19 @@
3196 #define TX_LED_TST 0x0d29 /* 8 bit Transmit LED Cnt Test Reg */
3197 /* 0x0d2a - 0x0d3f: reserved */
3198
3199-/* Transmit GMAC FIFO (YUKON only), use MR_ADDR() to access */
3200+/* Transmit GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
3201 #define TX_GMF_EA 0x0d40 /* 32 bit Tx GMAC FIFO End Address */
3202-#define TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
3203+#define TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh. */
3204 #define TX_GMF_CTRL_T 0x0d48 /* 32 bit Tx GMAC FIFO Control/Test */
3205- /* 0x0d4c - 0x0d5f: reserved */
3206-#define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */
3207-#define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
3208-#define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */
3209+ /* 0x0d4c - 0x0d5b: reserved */
3210+#define TX_GMF_VLAN 0x0d5c /* 32 bit Tx VLAN Type Register (Yukon-2) */
3211+#define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */
3212+#define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Pointer */
3213+#define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */
3214 /* 0x0d6c - 0x0d6f: reserved */
3215-#define TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */
3216-#define TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */
3217-#define TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */
3218+#define TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */
3219+#define TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */
3220+#define TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */
3221 /* 0x0d7c - 0x0d7f: reserved */
3222
3223 /*
3224@@ -713,12 +1019,84 @@
3225 #define GMAC_TI_ST_CTRL 0x0e18 /* 8 bit Time Stamp Timer Ctrl Reg */
3226 /* 0x0e19: reserved */
3227 #define GMAC_TI_ST_TST 0x0e1a /* 8 bit Time Stamp Timer Test Reg */
3228- /* 0x0e1b - 0x0e7f: reserved */
3229+ /* 0x0e1b - 0x0e1f: reserved */
3230+
3231+/* Polling Unit Registers (Yukon-2 only) */
3232+#define POLL_CTRL 0x0e20 /* 32 bit Polling Unit Control Reg */
3233+#define POLL_LAST_IDX 0x0e24 /* 16 bit Polling Unit List Last Index */
3234+ /* 0x0e26 - 0x0e27: reserved */
3235+#define POLL_LIST_ADDR_LO 0x0e28 /* 32 bit Poll. List Start Addr (low) */
3236+#define POLL_LIST_ADDR_HI 0x0e2c /* 32 bit Poll. List Start Addr (high) */
3237+ /* 0x0e30 - 0x0e3f: reserved */
3238+
3239+/* ASF Subsystem Registers (Yukon-2 only) */
3240+#define B28_Y2_SMB_CONFIG 0x0e40 /* 32 bit ASF SMBus Config Register */
3241+#define B28_Y2_SMB_CSD_REG 0x0e44 /* 32 bit ASF SMB Control/Status/Data */
3242+ /* 0x0e48 - 0x0e5f: reserved */
3243+#define B28_Y2_ASF_IRQ_V_BASE 0x0e60 /* 32 bit ASF IRQ Vector Base */
3244+ /* 0x0e64 - 0x0e67: reserved */
3245+#define B28_Y2_ASF_STAT_CMD 0x0e68 /* 32 bit ASF Status and Command Reg */
3246+#define B28_Y2_ASF_HOST_COM 0x0e6c /* 32 bit ASF Host Communication Reg */
3247+#define B28_Y2_DATA_REG_1 0x0e70 /* 32 bit ASF/Host Data Register 1 */
3248+#define B28_Y2_DATA_REG_2 0x0e74 /* 32 bit ASF/Host Data Register 2 */
3249+#define B28_Y2_DATA_REG_3 0x0e78 /* 32 bit ASF/Host Data Register 3 */
3250+#define B28_Y2_DATA_REG_4 0x0e7c /* 32 bit ASF/Host Data Register 4 */
3251
3252 /*
3253 * Bank 29
3254 */
3255- /* 0x0e80 - 0x0efc: reserved */
3256+
3257+/* Status BMU Registers (Yukon-2 only)*/
3258+#define STAT_CTRL 0x0e80 /* 32 bit Status BMU Control Reg */
3259+#define STAT_LAST_IDX 0x0e84 /* 16 bit Status BMU Last Index */
3260+ /* 0x0e85 - 0x0e86: reserved */
3261+#define STAT_LIST_ADDR_LO 0x0e88 /* 32 bit Status List Start Addr (low) */
3262+#define STAT_LIST_ADDR_HI 0x0e8c /* 32 bit Status List Start Addr (high) */
3263+#define STAT_TXA1_RIDX 0x0e90 /* 16 bit Status TxA1 Report Index Reg */
3264+#define STAT_TXS1_RIDX 0x0e92 /* 16 bit Status TxS1 Report Index Reg */
3265+#define STAT_TXA2_RIDX 0x0e94 /* 16 bit Status TxA2 Report Index Reg */
3266+#define STAT_TXS2_RIDX 0x0e96 /* 16 bit Status TxS2 Report Index Reg */
3267+#define STAT_TX_IDX_TH 0x0e98 /* 16 bit Status Tx Index Threshold Reg */
3268+ /* 0x0e9a - 0x0e9b: reserved */
3269+#define STAT_PUT_IDX 0x0e9c /* 16 bit Status Put Index Reg */
3270+ /* 0x0e9e - 0x0e9f: reserved */
3271+
3272+/* FIFO Control/Status Registers (Yukon-2 only) */
3273+#define STAT_FIFO_WP 0x0ea0 /* 8 bit Status FIFO Write Pointer Reg */
3274+ /* 0x0ea1 - 0x0ea3: reserved */
3275+#define STAT_FIFO_RP 0x0ea4 /* 8 bit Status FIFO Read Pointer Reg */
3276+ /* 0x0ea5: reserved */
3277+#define STAT_FIFO_RSP 0x0ea6 /* 8 bit Status FIFO Read Shadow Ptr */
3278+ /* 0x0ea7: reserved */
3279+#define STAT_FIFO_LEVEL 0x0ea8 /* 8 bit Status FIFO Level Reg */
3280+ /* 0x0ea9: reserved */
3281+#define STAT_FIFO_SHLVL 0x0eaa /* 8 bit Status FIFO Shadow Level Reg */
3282+ /* 0x0eab: reserved */
3283+#define STAT_FIFO_WM 0x0eac /* 8 bit Status FIFO Watermark Reg */
3284+#define STAT_FIFO_ISR_WM 0x0ead /* 8 bit Status FIFO ISR Watermark Reg */
3285+ /* 0x0eae - 0x0eaf: reserved */
3286+
3287+/* Level and ISR Timer Registers (Yukon-2 only) */
3288+#define STAT_LEV_TIMER_INI 0x0eb0 /* 32 bit Level Timer Init. Value Reg */
3289+#define STAT_LEV_TIMER_CNT 0x0eb4 /* 32 bit Level Timer Counter Reg */
3290+#define STAT_LEV_TIMER_CTRL 0x0eb8 /* 8 bit Level Timer Control Reg */
3291+#define STAT_LEV_TIMER_TEST 0x0eb9 /* 8 bit Level Timer Test Reg */
3292+ /* 0x0eba - 0x0ebf: reserved */
3293+#define STAT_TX_TIMER_INI 0x0ec0 /* 32 bit Tx Timer Init. Value Reg */
3294+#define STAT_TX_TIMER_CNT 0x0ec4 /* 32 bit Tx Timer Counter Reg */
3295+#define STAT_TX_TIMER_CTRL 0x0ec8 /* 8 bit Tx Timer Control Reg */
3296+#define STAT_TX_TIMER_TEST 0x0ec9 /* 8 bit Tx Timer Test Reg */
3297+ /* 0x0eca - 0x0ecf: reserved */
3298+#define STAT_ISR_TIMER_INI 0x0ed0 /* 32 bit ISR Timer Init. Value Reg */
3299+#define STAT_ISR_TIMER_CNT 0x0ed4 /* 32 bit ISR Timer Counter Reg */
3300+#define STAT_ISR_TIMER_CTRL 0x0ed8 /* 8 bit ISR Timer Control Reg */
3301+#define STAT_ISR_TIMER_TEST 0x0ed9 /* 8 bit ISR Timer Test Reg */
3302+ /* 0x0eda - 0x0eff: reserved */
3303+
3304+#define ST_LAST_IDX_MASK 0x007f /* Last Index Mask */
3305+#define ST_TXRP_IDX_MASK 0x0fff /* Tx Report Index Mask */
3306+#define ST_TXTH_IDX_MASK 0x0fff /* Tx Threshold Index Mask */
3307+#define ST_WM_IDX_MASK 0x3f /* FIFO Watermark Index Mask */
3308
3309 /*
3310 * Bank 30
3311@@ -742,11 +1120,9 @@
3312 #define WOL_MATCH_RES 0x0f23 /* 8 bit WOL Match Result Reg */
3313 #define WOL_MAC_ADDR_LO 0x0f24 /* 32 bit WOL MAC Address Low */
3314 #define WOL_MAC_ADDR_HI 0x0f28 /* 16 bit WOL MAC Address High */
3315-#define WOL_PATT_RPTR 0x0f2c /* 8 bit WOL Pattern Read Ptr */
3316-
3317-/* use this macro to access above registers */
3318-#define WOL_REG(Reg) ((Reg) + (pAC->GIni.GIWolOffs))
3319-
3320+#define WOL_PATT_PME 0x0f2a /* 8 bit WOL PME Match Enable (Yukon-2) */
3321+#define WOL_PATT_ASFM 0x0f2b /* 8 bit WOL ASF Match Enable (Yukon-2) */
3322+#define WOL_PATT_RPTR 0x0f2c /* 8 bit WOL Pattern Read Pointer */
3323
3324 /* WOL Pattern Length Registers (YUKON only) */
3325
3326@@ -764,11 +1140,22 @@
3327 */
3328 /* 0x0f80 - 0x0fff: reserved */
3329
3330+/* WOL registers link 2 */
3331+
3332+/* use this macro to access WOL registers */
3333+#define WOL_REG(Port, Reg) ((Reg) + ((Port)*0x80) + (pAC->GIni.GIWolOffs))
3334+
3335 /*
3336 * Bank 32 - 33
3337 */
3338 #define WOL_PATT_RAM_1 0x1000 /* WOL Pattern RAM Link 1 */
3339+#define WOL_PATT_RAM_2 0x1400 /* WOL Pattern RAM Link 2 */
3340
3341+/* use this macro to retrieve the pattern ram base address */
3342+#define WOL_PATT_RAM_BASE(Port) (WOL_PATT_RAM_1 + (Port)*0x400)
3343+
3344+/* offset to configuration space on Yukon-2 */
3345+#define Y2_CFG_SPC 0x1c00
3346 /*
3347 * Bank 0x22 - 0x3f
3348 */
3349@@ -800,13 +1187,27 @@
3350 */
3351 /* B0_RAP 8 bit Register Address Port */
3352 /* Bit 7: reserved */
3353-#define RAP_RAP 0x3f /* Bit 6..0: 0 = block 0,..,6f = block 6f */
3354+#define RAP_MSK 0x7f /* Bit 6..0: 0 = block 0,..,6f = block 6f */
3355+
3356+/* B0_CTST 24 bit Control/Status register */
3357+ /* Bit 23..18: reserved */
3358+#define Y2_VMAIN_AVAIL BIT_17 /* VMAIN available (YUKON-2 only) */
3359+#define Y2_VAUX_AVAIL BIT_16 /* VAUX available (YUKON-2 only) */
3360+#define Y2_HW_WOL_ON BIT_15S /* HW WOL On (Yukon-EC Ultra A1 only) */
3361+#define Y2_HW_WOL_OFF BIT_14S /* HW WOL Off (Yukon-EC Ultra A1 only) */
3362+#define Y2_ASF_ENABLE BIT_13S /* ASF Unit Enable (YUKON-2 only) */
3363+#define Y2_ASF_DISABLE BIT_12S /* ASF Unit Disable (YUKON-2 only) */
3364+#define Y2_CLK_RUN_ENA BIT_11S /* CLK_RUN Enable (YUKON-2 only) */
3365+#define Y2_CLK_RUN_DIS BIT_10S /* CLK_RUN Disable (YUKON-2 only) */
3366+#define Y2_LED_STAT_ON BIT_9S /* Status LED On (YUKON-2 only) */
3367+#define Y2_LED_STAT_OFF BIT_8S /* Status LED Off (YUKON-2 only) */
3368+ /* Bit 7.. 0: same as below */
3369
3370 /* B0_CTST 16 bit Control/Status register */
3371 /* Bit 15..14: reserved */
3372-#define CS_CLK_RUN_HOT BIT_13S /* CLK_RUN hot m. (YUKON-Lite only) */
3373-#define CS_CLK_RUN_RST BIT_12S /* CLK_RUN reset (YUKON-Lite only) */
3374-#define CS_CLK_RUN_ENA BIT_11S /* CLK_RUN enable (YUKON-Lite only) */
3375+#define CS_CLK_RUN_HOT BIT_13S /* CLK_RUN Hot m. (YUKON-Lite only) */
3376+#define CS_CLK_RUN_RST BIT_12S /* CLK_RUN Reset (YUKON-Lite only) */
3377+#define CS_CLK_RUN_ENA BIT_11S /* CLK_RUN Enable (YUKON-Lite only) */
3378 #define CS_VAUX_AVAIL BIT_10S /* VAUX available (YUKON only) */
3379 #define CS_BUS_CLOCK BIT_9S /* Bus Clock 0/1 = 33/66 MHz */
3380 #define CS_BUS_SLOT_SZ BIT_8S /* Slot Size 0/1 = 32/64 bit slot */
3381@@ -814,26 +1215,27 @@
3382 #define CS_CL_SW_IRQ BIT_6S /* Clear IRQ SW Request */
3383 #define CS_STOP_DONE BIT_5S /* Stop Master is finished */
3384 #define CS_STOP_MAST BIT_4S /* Command Bit to stop the master */
3385-#define CS_MRST_CLR BIT_3S /* Clear Master reset */
3386-#define CS_MRST_SET BIT_2S /* Set Master reset */
3387-#define CS_RST_CLR BIT_1S /* Clear Software reset */
3388-#define CS_RST_SET BIT_0S /* Set Software reset */
3389+#define CS_MRST_CLR BIT_3S /* Clear Master Reset */
3390+#define CS_MRST_SET BIT_2S /* Set Master Reset */
3391+#define CS_RST_CLR BIT_1S /* Clear Software Reset */
3392+#define CS_RST_SET BIT_0S /* Set Software Reset */
3393
3394-/* B0_LED 8 Bit LED register */
3395+/* B0_LED 8 Bit LED register (GENESIS only)*/
3396 /* Bit 7.. 2: reserved */
3397-#define LED_STAT_ON BIT_1S /* Status LED on */
3398-#define LED_STAT_OFF BIT_0S /* Status LED off */
3399+#define LED_STAT_ON BIT_1S /* Status LED On */
3400+#define LED_STAT_OFF BIT_0S /* Status LED Off */
3401
3402 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
3403 #define PC_VAUX_ENA BIT_7 /* Switch VAUX Enable */
3404-#define PC_VAUX_DIS BIT_6 /* Switch VAUX Disable */
3405-#define PC_VCC_ENA BIT_5 /* Switch VCC Enable */
3406-#define PC_VCC_DIS BIT_4 /* Switch VCC Disable */
3407-#define PC_VAUX_ON BIT_3 /* Switch VAUX On */
3408-#define PC_VAUX_OFF BIT_2 /* Switch VAUX Off */
3409-#define PC_VCC_ON BIT_1 /* Switch VCC On */
3410-#define PC_VCC_OFF BIT_0 /* Switch VCC Off */
3411+#define PC_VAUX_DIS BIT_6 /* Switch VAUX Disable */
3412+#define PC_VCC_ENA BIT_5 /* Switch VCC Enable */
3413+#define PC_VCC_DIS BIT_4 /* Switch VCC Disable */
3414+#define PC_VAUX_ON BIT_3 /* Switch VAUX On */
3415+#define PC_VAUX_OFF BIT_2 /* Switch VAUX Off */
3416+#define PC_VCC_ON BIT_1 /* Switch VCC On */
3417+#define PC_VCC_OFF BIT_0 /* Switch VCC Off */
3418
3419+/* Yukon and Genesis */
3420 /* B0_ISRC 32 bit Interrupt Source Register */
3421 /* B0_IMSK 32 bit Interrupt Mask Register */
3422 /* B0_SP_ISRC 32 bit Special Interrupt Source Reg */
3423@@ -879,12 +1281,58 @@
3424 #define IS_XA2_F BIT_1 /* Q_XA2 End of Frame */
3425 #define IS_XA2_C BIT_0 /* Q_XA2 Encoding Error */
3426
3427+/* Yukon-2 */
3428+/* B0_ISRC 32 bit Interrupt Source Register */
3429+/* B0_IMSK 32 bit Interrupt Mask Register */
3430+/* B0_SP_ISRC 32 bit Special Interrupt Source Reg */
3431+/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
3432+/* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */
3433+/* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */
3434+/* B0_Y2_SP_EISR 32 bit Enter ISR Reg */
3435+/* B0_Y2_SP_LISR 32 bit Leave ISR Reg */
3436+#define Y2_IS_PORT_MASK(Port, Mask) ((Mask) << (Port*8))
3437+#define Y2_IS_HW_ERR BIT_31 /* Interrupt HW Error */
3438+#define Y2_IS_STAT_BMU BIT_30 /* Status BMU Interrupt */
3439+#define Y2_IS_ASF BIT_29 /* ASF subsystem Interrupt */
3440+ /* Bit 28: reserved */
3441+#define Y2_IS_POLL_CHK BIT_27 /* Check IRQ from polling unit */
3442+#define Y2_IS_TWSI_RDY BIT_26 /* IRQ on end of TWSI Tx */
3443+#define Y2_IS_IRQ_SW BIT_25 /* SW forced IRQ */
3444+#define Y2_IS_TIMINT BIT_24 /* IRQ from Timer */
3445+ /* Bit 23..16 reserved */
3446+ /* Link 2 Interrupts */
3447+#define Y2_IS_IRQ_PHY2 BIT_12 /* Interrupt from PHY 2 */
3448+#define Y2_IS_IRQ_MAC2 BIT_11 /* Interrupt from MAC 2 */
3449+#define Y2_IS_CHK_RX2 BIT_10 /* Descriptor error Rx 2 */
3450+#define Y2_IS_CHK_TXS2 BIT_9 /* Descriptor error TXS 2 */
3451+#define Y2_IS_CHK_TXA2 BIT_8 /* Descriptor error TXA 2 */
3452+ /* Bit 7.. 5 reserved */
3453+ /* Link 1 interrupts */
3454+#define Y2_IS_IRQ_PHY1 BIT_4 /* Interrupt from PHY 1 */
3455+#define Y2_IS_IRQ_MAC1 BIT_3 /* Interrupt from MAC 1 */
3456+#define Y2_IS_CHK_RX1 BIT_2 /* Descriptor error Rx 1 */
3457+#define Y2_IS_CHK_TXS1 BIT_1 /* Descriptor error TXS 1 */
3458+#define Y2_IS_CHK_TXA1 BIT_0 /* Descriptor error TXA 1 */
3459+
3460+#define Y2_IS_L1_MASK 0x0000001fUL /* IRQ Mask for port 1 */
3461+
3462+#define Y2_IS_L2_MASK 0x00001f00UL /* IRQ Mask for port 2 */
3463+
3464+#define Y2_IS_ALL_MSK 0xef001f1fUL /* All Interrupt bits */
3465+
3466+/* B0_Y2_SP_ICR 32 bit Interrupt Control Register */
3467+ /* Bit 31.. 4: reserved */
3468+#define Y2_IC_ISR_MASK BIT_3 /* ISR mask flag */
3469+#define Y2_IC_ISR_STAT BIT_2 /* ISR status flag */
3470+#define Y2_IC_LEAVE_ISR BIT_1 /* Leave ISR */
3471+#define Y2_IC_ENTER_ISR BIT_0 /* Enter ISR */
3472
3473+/* Yukon and Genesis */
3474 /* B0_HWE_ISRC 32 bit HW Error Interrupt Src Reg */
3475 /* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */
3476 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
3477 #define IS_ERR_MSK 0x00000fffL /* All Error bits */
3478- /* Bit 31..14: reserved */
3479+ /* Bit 31..14: reserved */
3480 #define IS_IRQ_TIST_OV BIT_13 /* Time Stamp Timer Overflow (YUKON only) */
3481 #define IS_IRQ_SENSOR BIT_12 /* IRQ from Sensor (YUKON only) */
3482 #define IS_IRQ_MST_ERR BIT_11 /* IRQ master error detected */
3483@@ -900,6 +1348,43 @@
3484 #define IS_R1_PAR_ERR BIT_1 /* Queue R1 Parity Error */
3485 #define IS_R2_PAR_ERR BIT_0 /* Queue R2 Parity Error */
3486
3487+/* Yukon-2 */
3488+/* B0_HWE_ISRC 32 bit HW Error Interrupt Src Reg */
3489+/* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */
3490+/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
3491+ /* Bit: 31..30 reserved */
3492+#define Y2_IS_TIST_OV BIT_29 /* Time Stamp Timer overflow interrupt */
3493+#define Y2_IS_SENSOR BIT_28 /* Sensor interrupt */
3494+#define Y2_IS_MST_ERR BIT_27 /* Master error interrupt */
3495+#define Y2_IS_IRQ_STAT BIT_26 /* Status exception interrupt */
3496+#define Y2_IS_PCI_EXP BIT_25 /* PCI-Express interrupt */
3497+#define Y2_IS_PCI_NEXP BIT_24 /* Bus Abort detected */
3498+ /* Bit: 23..14 reserved */
3499+ /* Link 2 */
3500+#define Y2_IS_PAR_RD2 BIT_13 /* Read RAM parity error interrupt */
3501+#define Y2_IS_PAR_WR2 BIT_12 /* Write RAM parity error interrupt */
3502+#define Y2_IS_PAR_MAC2 BIT_11 /* MAC hardware fault interrupt */
3503+#define Y2_IS_PAR_RX2 BIT_10 /* Parity Error Rx Queue 2 */
3504+#define Y2_IS_TCP_TXS2 BIT_9 /* TCP length mismatch sync Tx queue IRQ */
3505+#define Y2_IS_TCP_TXA2 BIT_8 /* TCP length mismatch async Tx queue IRQ */
3506+ /* Bit: 9.. 6 reserved */
3507+ /* Link 1 */
3508+#define Y2_IS_PAR_RD1 BIT_5 /* Read RAM parity error interrupt */
3509+#define Y2_IS_PAR_WR1 BIT_4 /* Write RAM parity error interrupt */
3510+#define Y2_IS_PAR_MAC1 BIT_3 /* MAC hardware fault interrupt */
3511+#define Y2_IS_PAR_RX1 BIT_2 /* Parity Error Rx Queue 1 */
3512+#define Y2_IS_TCP_TXS1 BIT_1 /* TCP length mismatch sync Tx queue IRQ */
3513+#define Y2_IS_TCP_TXA1 BIT_0 /* TCP length mismatch async Tx queue IRQ */
3514+
3515+#define Y2_HWE_L1_MASK (Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |\
3516+ Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1)
3517+#define Y2_HWE_L2_MASK (Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |\
3518+ Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2)
3519+
3520+#define Y2_HWE_ALL_MSK (Y2_IS_TIST_OV | /* Y2_IS_SENSOR | */ Y2_IS_MST_ERR |\
3521+ Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP |\
3522+ Y2_HWE_L1_MASK | Y2_HWE_L2_MASK)
3523+
3524 /* B2_CONN_TYP 8 bit Connector type */
3525 /* B2_PMD_TYP 8 bit PMD type */
3526 /* Values of connector and PMD type comply to SysKonnect internal std */
3527@@ -908,19 +1393,79 @@
3528 #define CFG_CHIP_R_MSK (0xf<<4) /* Bit 7.. 4: Chip Revision */
3529 /* Bit 3.. 2: reserved */
3530 #define CFG_DIS_M2_CLK BIT_1S /* Disable Clock for 2nd MAC */
3531-#define CFG_SNG_MAC BIT_0S /* MAC Config: 0=2 MACs / 1=1 MAC*/
3532+#define CFG_SNG_MAC BIT_0S /* MAC Config: 0 = 2 MACs; 1 = 1 MAC */
3533
3534-/* B2_CHIP_ID 8 bit Chip Identification Number */
3535+/* B2_CHIP_ID 8 bit Chip Identification Number */
3536 #define CHIP_ID_GENESIS 0x0a /* Chip ID for GENESIS */
3537 #define CHIP_ID_YUKON 0xb0 /* Chip ID for YUKON */
3538 #define CHIP_ID_YUKON_LITE 0xb1 /* Chip ID for YUKON-Lite (Rev. A1-A3) */
3539 #define CHIP_ID_YUKON_LP 0xb2 /* Chip ID for YUKON-LP */
3540+#define CHIP_ID_YUKON_XL 0xb3 /* Chip ID for YUKON-2 XL */
3541+#define CHIP_ID_YUKON_EC_U 0xb4 /* Chip ID for YUKON-2 EC Ultra */
3542+#define CHIP_ID_YUKON_EC 0xb6 /* Chip ID for YUKON-2 EC */
3543+#define CHIP_ID_YUKON_FE 0xb7 /* Chip ID for YUKON-2 FE */
3544
3545 #define CHIP_REV_YU_LITE_A1 3 /* Chip Rev. for YUKON-Lite A1,A2 */
3546 #define CHIP_REV_YU_LITE_A3 7 /* Chip Rev. for YUKON-Lite A3 */
3547
3548+#define CHIP_REV_YU_XL_A0 0 /* Chip Rev. for Yukon-2 A0 */
3549+#define CHIP_REV_YU_XL_A1 1 /* Chip Rev. for Yukon-2 A1 */
3550+#define CHIP_REV_YU_XL_A2 2 /* Chip Rev. for Yukon-2 A2 */
3551+#define CHIP_REV_YU_XL_A3 3 /* Chip Rev. for Yukon-2 A3 */
3552+
3553+#define CHIP_REV_YU_EC_A1 0 /* Chip Rev. for Yukon-EC A0,A1 */
3554+#define CHIP_REV_YU_EC_A2 1 /* Chip Rev. for Yukon-EC A2 */
3555+#define CHIP_REV_YU_EC_A3 2 /* Chip Rev. for Yukon-EC A3 */
3556+
3557+#define CHIP_REV_YU_EC_U_A0 1 /* Chip Rev. for Yukon-EC Ultra A0 */
3558+#define CHIP_REV_YU_EC_U_A1 2 /* Chip Rev. for Yukon-EC Ultra A1 */
3559+#define CHIP_REV_YU_EC_U_B0 3 /* Chip Rev. for Yukon-EC Ultra B0 */
3560+
3561+#define CHIP_REV_YU_FE_A1 1 /* Chip Rev. for Yukon-FE A1 */
3562+#define CHIP_REV_YU_FE_A2 3 /* Chip Rev. for Yukon-FE A2 */
3563+
3564+/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
3565+#define Y2_STATUS_LNK2_INAC BIT_7S /* Status Link 2 inactiv (0 = activ) */
3566+#define Y2_CLK_GAT_LNK2_DIS BIT_6S /* Disable PHY clock for Link 2 */
3567+#define Y2_COR_CLK_LNK2_DIS BIT_5S /* Disable Core clock Link 2 */
3568+#define Y2_PCI_CLK_LNK2_DIS BIT_4S /* Disable PCI clock Link 2 */
3569+#define Y2_STATUS_LNK1_INAC BIT_3S /* Status Link 1 inactiv (0 = activ) */
3570+#define Y2_CLK_GAT_LNK1_DIS BIT_2S /* Disable PHY clock for Link 1 */
3571+#define Y2_COR_CLK_LNK1_DIS BIT_1S /* Disable Core clock Link 1 */
3572+#define Y2_PCI_CLK_LNK1_DIS BIT_0S /* Disable PCI clock Link 1 */
3573+
3574+/* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
3575+ /* Bit 7.. 6: reserved */
3576+#define CFG_PEX_PME_NATIVE BIT_5S /* PCI-E PME native mode select */
3577+#define CFG_LED_MODE_MSK (7<<2) /* Bit 4.. 2: LED Mode Mask */
3578+#define CFG_LINK_2_AVAIL BIT_1S /* Link 2 available */
3579+#define CFG_LINK_1_AVAIL BIT_0S /* Link 1 available */
3580+
3581+#define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2)
3582+#define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)
3583+
3584+#define CFG_LED_DUAL_ACT_LNK 1 /* Dual LED ACT/LNK mode */
3585+#define CFG_LED_LINK_MUX_P60 2 /* Link LED on pin 60 (Yukon-EC Ultra) */
3586+
3587+/* B2_E_3 8 bit lower 4 bits used for HW self test result */
3588+#define B2_E3_RES_MASK 0x0f
3589+
3590 /* B2_FAR 32 bit Flash-Prom Addr Reg/Cnt */
3591-#define FAR_ADDR 0x1ffffL /* Bit 16.. 0: FPROM Address mask */
3592+#define FAR_ADDR 0x1ffffL /* Bit 16.. 0: FPROM Address Mask */
3593+
3594+/* B2_Y2_CLK_CTRL 32 bit Core Clock Frequency Control Register (Yukon-2/EC) */
3595+ /* Bit 31..24: reserved */
3596+/* Yukon-EC/FE */
3597+#define Y2_CLK_DIV_VAL_MSK (0xffL<<16) /* Bit 23..16: Clock Divisor Value */
3598+#define Y2_CLK_DIV_VAL(x) (SHIFT16(x) & Y2_CLK_DIV_VAL_MSK)
3599+/* Yukon-2 */
3600+#define Y2_CLK_DIV_VAL2_MSK (7L<<21) /* Bit 23..21: Clock Divisor Value */
3601+#define Y2_CLK_SELECT2_MSK (0x1fL<<16) /* Bit 20..16: Clock Select */
3602+#define Y2_CLK_DIV_VAL_2(x) (SHIFT21(x) & Y2_CLK_DIV_VAL2_MSK)
3603+#define Y2_CLK_SEL_VAL_2(x) (SHIFT16(x) & Y2_CLK_SELECT2_MSK)
3604+ /* Bit 15.. 2: reserved */
3605+#define Y2_CLK_DIV_ENA BIT_1S /* Enable Core Clock Division */
3606+#define Y2_CLK_DIV_DIS BIT_0S /* Disable Core Clock Division */
3607
3608 /* B2_LD_CTRL 8 bit EPROM loader control register */
3609 /* Bits are currently reserved */
3610@@ -960,9 +1505,6 @@
3611 #define DPT_START BIT_1S /* Start Descriptor Poll Timer */
3612 #define DPT_STOP BIT_0S /* Stop Descriptor Poll Timer */
3613
3614-/* B2_E_3 8 bit lower 4 bits used for HW self test result */
3615-#define B2_E3_RES_MASK 0x0f
3616-
3617 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
3618 #define TST_FRC_DPERR_MR BIT_7S /* force DATAPERR on MST RD */
3619 #define TST_FRC_DPERR_MW BIT_6S /* force DATAPERR on MST WR */
3620@@ -975,14 +1517,14 @@
3621
3622 /* B2_TST_CTRL2 8 bit Test Control Register 2 */
3623 /* Bit 7.. 4: reserved */
3624- /* force the following error on the next master read/write */
3625+ /* force the following error on the next master read/write */
3626 #define TST_FRC_DPERR_MR64 BIT_3S /* DataPERR RD 64 */
3627 #define TST_FRC_DPERR_MW64 BIT_2S /* DataPERR WR 64 */
3628 #define TST_FRC_APERR_1M64 BIT_1S /* AddrPERR on 1. phase */
3629 #define TST_FRC_APERR_2M64 BIT_0S /* AddrPERR on 2. phase */
3630
3631 /* B2_GP_IO 32 bit General Purpose I/O Register */
3632- /* Bit 31..26: reserved */
3633+ /* Bit 31..26: reserved */
3634 #define GP_DIR_9 BIT_25 /* IO_9 direct, 0=In/1=Out */
3635 #define GP_DIR_8 BIT_24 /* IO_8 direct, 0=In/1=Out */
3636 #define GP_DIR_7 BIT_23 /* IO_7 direct, 0=In/1=Out */
3637@@ -1009,15 +1551,15 @@
3638 #define I2C_FLAG BIT_31 /* Start read/write if WR */
3639 #define I2C_ADDR (0x7fffL<<16) /* Bit 30..16: Addr to be RD/WR */
3640 #define I2C_DEV_SEL (0x7fL<<9) /* Bit 15.. 9: I2C Device Select */
3641- /* Bit 8.. 5: reserved */
3642+ /* Bit 8.. 5: reserved */
3643 #define I2C_BURST_LEN BIT_4 /* Burst Len, 1/4 bytes */
3644-#define I2C_DEV_SIZE (7<<1) /* Bit 3.. 1: I2C Device Size */
3645-#define I2C_025K_DEV (0<<1) /* 0: 256 Bytes or smal. */
3646-#define I2C_05K_DEV (1<<1) /* 1: 512 Bytes */
3647-#define I2C_1K_DEV (2<<1) /* 2: 1024 Bytes */
3648-#define I2C_2K_DEV (3<<1) /* 3: 2048 Bytes */
3649-#define I2C_4K_DEV (4<<1) /* 4: 4096 Bytes */
3650-#define I2C_8K_DEV (5<<1) /* 5: 8192 Bytes */
3651+#define I2C_DEV_SIZE (7<<1) /* Bit 3.. 1: I2C Device Size */
3652+#define I2C_025K_DEV (0<<1) /* 0: 256 Bytes or smaller */
3653+#define I2C_05K_DEV (1<<1) /* 1: 512 Bytes */
3654+#define I2C_1K_DEV (2<<1) /* 2: 1024 Bytes */
3655+#define I2C_2K_DEV (3<<1) /* 3: 2048 Bytes */
3656+#define I2C_4K_DEV (4<<1) /* 4: 4096 Bytes */
3657+#define I2C_8K_DEV (5<<1) /* 5: 8192 Bytes */
3658 #define I2C_16K_DEV (6<<1) /* 6: 16384 Bytes */
3659 #define I2C_32K_DEV (7<<1) /* 7: 32768 Bytes */
3660 #define I2C_STOP BIT_0 /* Interrupt I2C transfer */
3661@@ -1026,16 +1568,14 @@
3662 /* Bit 31.. 1 reserved */
3663 #define I2C_CLR_IRQ BIT_0 /* Clear I2C IRQ */
3664
3665-/* B2_I2C_SW 32 bit (8 bit access) I2C HW SW Port Register */
3666+/* B2_I2C_SW 32 bit (8 bit access) I2C SW Port Register */
3667 /* Bit 7.. 3: reserved */
3668 #define I2C_DATA_DIR BIT_2S /* direction of I2C_DATA */
3669-#define I2C_DATA BIT_1S /* I2C Data Port */
3670-#define I2C_CLK BIT_0S /* I2C Clock Port */
3671+#define I2C_DATA BIT_1S /* I2C Data Port */
3672+#define I2C_CLK BIT_0S /* I2C Clock Port */
3673
3674-/*
3675- * I2C Address
3676- */
3677-#define I2C_SENS_ADDR LM80_ADDR /* I2C Sensor Address, (Volt and Temp)*/
3678+/* I2C Address */
3679+#define I2C_SENS_ADDR LM80_ADDR /* I2C Sensor Address (Volt and Temp) */
3680
3681
3682 /* B2_BSC_CTRL 8 bit Blink Source Counter Control */
3683@@ -1052,16 +1592,20 @@
3684 #define BSC_T_OFF BIT_1S /* Test mode off */
3685 #define BSC_T_STEP BIT_0S /* Test step */
3686
3687+/* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */
3688+#define PEX_RD_ACCESS BIT_31 /* Access Mode Read = 1, Write = 0 */
3689+#define PEX_DB_ACCESS BIT_30 /* Access to debug register */
3690+
3691
3692 /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
3693 /* Bit 31..19: reserved */
3694 #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
3695
3696 /* RAM Interface Registers */
3697-/* B3_RI_CTRL 16 bit RAM Iface Control Register */
3698+/* B3_RI_CTRL 16 bit RAM Interface Control Register */
3699 /* Bit 15..10: reserved */
3700-#define RI_CLR_RD_PERR BIT_9S /* Clear IRQ RAM Read Parity Err */
3701-#define RI_CLR_WR_PERR BIT_8S /* Clear IRQ RAM Write Parity Err*/
3702+#define RI_CLR_RD_PERR BIT_9S /* Clear IRQ RAM Read Parity Err */
3703+#define RI_CLR_WR_PERR BIT_8S /* Clear IRQ RAM Write Parity Err */
3704 /* Bit 7.. 2: reserved */
3705 #define RI_RST_CLR BIT_1S /* Clear RAM Interface Reset */
3706 #define RI_RST_SET BIT_0S /* Set RAM Interface Reset */
3707@@ -1171,7 +1715,7 @@
3708 /* Bit 31..16: reserved */
3709 #define BC_MAX 0xffff /* Bit 15.. 0: Byte counter */
3710
3711-/* BMU Control Status Registers */
3712+/* BMU Control / Status Registers (Yukon and Genesis) */
3713 /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
3714 /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
3715 /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
3716@@ -1212,13 +1756,48 @@
3717 CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\
3718 CSR_TRANS_RUN)
3719
3720+/* Rx BMU Control / Status Registers (Yukon-2) */
3721+#define BMU_IDLE BIT_31 /* BMU Idle State */
3722+#define BMU_RX_TCP_PKT BIT_30 /* Rx TCP Packet (when RSS Hash enabled) */
3723+#define BMU_RX_IP_PKT BIT_29 /* Rx IP Packet (when RSS Hash enabled) */
3724+ /* Bit 28..16: reserved */
3725+#define BMU_ENA_RX_RSS_HASH BIT_15 /* Enable Rx RSS Hash */
3726+#define BMU_DIS_RX_RSS_HASH BIT_14 /* Disable Rx RSS Hash */
3727+#define BMU_ENA_RX_CHKSUM BIT_13 /* Enable Rx TCP/IP Checksum Check */
3728+#define BMU_DIS_RX_CHKSUM BIT_12 /* Disable Rx TCP/IP Checksum Check */
3729+#define BMU_CLR_IRQ_PAR BIT_11 /* Clear IRQ on Parity errors (Rx) */
3730+#define BMU_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segmen. error (Tx) */
3731+#define BMU_CLR_IRQ_CHK BIT_10 /* Clear IRQ Check */
3732+#define BMU_STOP BIT_9 /* Stop Rx/Tx Queue */
3733+#define BMU_START BIT_8 /* Start Rx/Tx Queue */
3734+#define BMU_FIFO_OP_ON BIT_7 /* FIFO Operational On */
3735+#define BMU_FIFO_OP_OFF BIT_6 /* FIFO Operational Off */
3736+#define BMU_FIFO_ENA BIT_5 /* Enable FIFO */
3737+#define BMU_FIFO_RST BIT_4 /* Reset FIFO */
3738+#define BMU_OP_ON BIT_3 /* BMU Operational On */
3739+#define BMU_OP_OFF BIT_2 /* BMU Operational Off */
3740+#define BMU_RST_CLR BIT_1 /* Clear BMU Reset (Enable) */
3741+#define BMU_RST_SET BIT_0 /* Set BMU Reset */
3742+
3743+#define BMU_CLR_RESET (BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR)
3744+#define BMU_OPER_INIT (BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START | \
3745+ BMU_FIFO_ENA | BMU_OP_ON)
3746+
3747+/* Tx BMU Control / Status Registers (Yukon-2) */
3748+ /* Bit 31: same as for Rx */
3749+ /* Bit 30..14: reserved */
3750+#define BMU_TX_IPIDINCR_ON BIT_13 /* Enable IP ID Increment */
3751+#define BMU_TX_IPIDINCR_OFF BIT_12 /* Disable IP ID Increment */
3752+#define BMU_TX_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segm. length mism. */
3753+ /* Bit 10..0: same as for Rx */
3754+
3755 /* Q_F 32 bit Flag Register */
3756 /* Bit 31..28: reserved */
3757 #define F_ALM_FULL BIT_27 /* Rx FIFO: almost full */
3758 #define F_EMPTY BIT_27 /* Tx FIFO: empty flag */
3759 #define F_FIFO_EOF BIT_26 /* Tag (EOF Flag) bit in FIFO */
3760 #define F_WM_REACHED BIT_25 /* Watermark reached */
3761- /* reserved */
3762+#define F_M_RX_RAM_DIS BIT_24 /* MAC Rx RAM Read Port disable */
3763 #define F_FIFO_LEVEL (0x1fL<<16) /* Bit 23..16: # of Qwords in FIFO */
3764 /* Bit 15..11: reserved */
3765 #define F_WATER_MARK 0x0007ffL /* Bit 10.. 0: Watermark */
3766@@ -1260,6 +1839,13 @@
3767 /* Bit 3: reserved */
3768 #define T3_VRAM_MSK 7 /* Bit 2.. 0: Virtual RAM Buffer Address */
3769
3770+/* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/
3771+/* PREF_UNIT_CTRL_REG 32 bit Prefetch Control register */
3772+#define PREF_UNIT_OP_ON BIT_3 /* prefetch unit operational */
3773+#define PREF_UNIT_OP_OFF BIT_2 /* prefetch unit not operational */
3774+#define PREF_UNIT_RST_CLR BIT_1 /* Clear Prefetch Unit Reset */
3775+#define PREF_UNIT_RST_SET BIT_0 /* Set Prefetch Unit Reset */
3776+
3777 /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
3778 /* RB_START 32 bit RAM Buffer Start Address */
3779 /* RB_END 32 bit RAM Buffer End Address */
3780@@ -1275,24 +1861,24 @@
3781 #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
3782
3783 /* RB_TST2 8 bit RAM Buffer Test Register 2 */
3784- /* Bit 7.. 4: reserved */
3785-#define RB_PC_DEC BIT_3S /* Packet Counter Decrem */
3786+ /* Bit 7.. 4: reserved */
3787+#define RB_PC_DEC BIT_3S /* Packet Counter Decrement */
3788 #define RB_PC_T_ON BIT_2S /* Packet Counter Test On */
3789-#define RB_PC_T_OFF BIT_1S /* Packet Counter Tst Off */
3790-#define RB_PC_INC BIT_0S /* Packet Counter Increm */
3791+#define RB_PC_T_OFF BIT_1S /* Packet Counter Test Off */
3792+#define RB_PC_INC BIT_0S /* Packet Counter Increment */
3793
3794 /* RB_TST1 8 bit RAM Buffer Test Register 1 */
3795 /* Bit 7: reserved */
3796 #define RB_WP_T_ON BIT_6S /* Write Pointer Test On */
3797 #define RB_WP_T_OFF BIT_5S /* Write Pointer Test Off */
3798-#define RB_WP_INC BIT_4S /* Write Pointer Increm */
3799+#define RB_WP_INC BIT_4S /* Write Pointer Increment */
3800 /* Bit 3: reserved */
3801 #define RB_RP_T_ON BIT_2S /* Read Pointer Test On */
3802 #define RB_RP_T_OFF BIT_1S /* Read Pointer Test Off */
3803-#define RB_RP_DEC BIT_0S /* Read Pointer Decrement */
3804+#define RB_RP_INC BIT_0S /* Read Pointer Increment */
3805
3806 /* RB_CTRL 8 bit RAM Buffer Control Register */
3807- /* Bit 7.. 6: reserved */
3808+ /* Bit 7.. 6: reserved */
3809 #define RB_ENA_STFWD BIT_5S /* Enable Store & Forward */
3810 #define RB_DIS_STFWD BIT_4S /* Disable Store & Forward */
3811 #define RB_ENA_OP_MD BIT_3S /* Enable Operation Mode */
3812@@ -1300,16 +1886,31 @@
3813 #define RB_RST_CLR BIT_1S /* Clear RAM Buf STM Reset */
3814 #define RB_RST_SET BIT_0S /* Set RAM Buf STM Reset */
3815
3816+/* Yukon-2 */
3817+ /* Bit 31..20: reserved */
3818+#define RB_CNT_DOWN BIT_19 /* Packet Counter Decrement */
3819+#define RB_CNT_TST_ON BIT_18 /* Packet Counter Test On */
3820+#define RB_CNT_TST_OFF BIT_17 /* Packet Counter Test Off */
3821+#define RB_CNT_UP BIT_16 /* Packet Counter Increment */
3822+ /* Bit 15: reserved */
3823+#define RB_WP_TST_ON BIT_14 /* Write Pointer Test On */
3824+#define RB_WP_TST_OFF BIT_13 /* Write Pointer Test Off */
3825+#define RB_WP_UP BIT_12 /* Write Pointer Increment */
3826+ /* Bit 11: reserved */
3827+#define RB_RP_TST_ON BIT_10 /* Read Pointer Test On */
3828+#define RB_RP_TST_OFF BIT_9 /* Read Pointer Test Off */
3829+#define RB_RP_UP BIT_8 /* Read Pointer Increment */
3830+
3831
3832 /* Receive and Transmit MAC FIFO Registers (GENESIS only) */
3833
3834 /* RX_MFF_EA 32 bit Receive MAC FIFO End Address */
3835-/* RX_MFF_WP 32 bit Receive MAC FIFO Write Pointer */
3836+/* RX_MFF_WP 32 bit Receive MAC FIFO Write Pointer */
3837 /* RX_MFF_RP 32 bit Receive MAC FIFO Read Pointer */
3838 /* RX_MFF_PC 32 bit Receive MAC FIFO Packet Counter */
3839 /* RX_MFF_LEV 32 bit Receive MAC FIFO Level */
3840 /* TX_MFF_EA 32 bit Transmit MAC FIFO End Address */
3841-/* TX_MFF_WP 32 bit Transmit MAC FIFO Write Pointer */
3842+/* TX_MFF_WP 32 bit Transmit MAC FIFO Write Pointer */
3843 /* TX_MFF_WSP 32 bit Transmit MAC FIFO WR Shadow Pointer */
3844 /* TX_MFF_RP 32 bit Transmit MAC FIFO Read Pointer */
3845 /* TX_MFF_PC 32 bit Transmit MAC FIFO Packet Cnt */
3846@@ -1359,9 +1960,9 @@
3847 /* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */
3848 /* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */
3849 /* Bit 7: reserved */
3850-#define MFF_WSP_T_ON BIT_6S /* Tx: Write Shadow Ptr TestOn */
3851-#define MFF_WSP_T_OFF BIT_5S /* Tx: Write Shadow Ptr TstOff */
3852-#define MFF_WSP_INC BIT_4S /* Tx: Write Shadow Ptr Increment */
3853+#define MFF_WSP_T_ON BIT_6S /* Tx: Write Shadow Pointer Test On */
3854+#define MFF_WSP_T_OFF BIT_5S /* Tx: Write Shadow Pointer Test Off */
3855+#define MFF_WSP_INC BIT_4S /* Tx: Write Shadow Pointer Increment */
3856 #define MFF_PC_DEC BIT_3S /* Packet Counter Decrement */
3857 #define MFF_PC_T_ON BIT_2S /* Packet Counter Test On */
3858 #define MFF_PC_T_OFF BIT_1S /* Packet Counter Test Off */
3859@@ -1372,7 +1973,7 @@
3860 /* Bit 7: reserved */
3861 #define MFF_WP_T_ON BIT_6S /* Write Pointer Test On */
3862 #define MFF_WP_T_OFF BIT_5S /* Write Pointer Test Off */
3863-#define MFF_WP_INC BIT_4S /* Write Pointer Increm */
3864+#define MFF_WP_INC BIT_4S /* Write Pointer Increment */
3865 /* Bit 3: reserved */
3866 #define MFF_RP_T_ON BIT_2S /* Read Pointer Test On */
3867 #define MFF_RP_T_OFF BIT_1S /* Read Pointer Test Off */
3868@@ -1391,12 +1992,16 @@
3869
3870 /* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */
3871 /* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */
3872+ /* Bit 7.. 3: reserved */
3873+#define LED_START BIT_2S /* Start Counter */
3874+#define LED_STOP BIT_1S /* Stop Counter */
3875+#define LED_STATE BIT_0S /* Rx/Tx: LED State, 1=LED On */
3876+
3877 /* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */
3878 /* Bit 7.. 3: reserved */
3879-#define LED_START BIT_2S /* Start Timer */
3880-#define LED_STOP BIT_1S /* Stop Timer */
3881-#define LED_STATE BIT_0S /* Rx/Tx: LED State, 1=LED on */
3882-#define LED_CLR_IRQ BIT_0S /* Lnk: Clear Link IRQ */
3883+#define LNK_START BIT_2S /* Start Counter */
3884+#define LNK_STOP BIT_1S /* Stop Counter */
3885+#define LNK_CLR_IRQ BIT_0S /* Clear Link IRQ */
3886
3887 /* RX_LED_TST 8 bit Receive LED Cnt Test Register */
3888 /* TX_LED_TST 8 bit Transmit LED Cnt Test Register */
3889@@ -1407,86 +2012,142 @@
3890 #define LED_T_STEP BIT_0S /* LED Counter Step */
3891
3892 /* LNK_LED_REG 8 bit Link LED Register */
3893- /* Bit 7.. 6: reserved */
3894+ /* Bit 7.. 6: reserved */
3895 #define LED_BLK_ON BIT_5S /* Link LED Blinking On */
3896 #define LED_BLK_OFF BIT_4S /* Link LED Blinking Off */
3897 #define LED_SYNC_ON BIT_3S /* Use Sync Wire to switch LED */
3898 #define LED_SYNC_OFF BIT_2S /* Disable Sync Wire Input */
3899-#define LED_ON BIT_1S /* switch LED on */
3900-#define LED_OFF BIT_0S /* switch LED off */
3901+#define LED_ON BIT_1S /* Switch LED On */
3902+#define LED_OFF BIT_0S /* Switch LED Off */
3903
3904 /* Receive and Transmit GMAC FIFO Registers (YUKON only) */
3905
3906 /* RX_GMF_EA 32 bit Rx GMAC FIFO End Address */
3907 /* RX_GMF_AF_THR 32 bit Rx GMAC FIFO Almost Full Thresh. */
3908-/* RX_GMF_WP 32 bit Rx GMAC FIFO Write Pointer */
3909-/* RX_GMF_WLEV 32 bit Rx GMAC FIFO Write Level */
3910-/* RX_GMF_RP 32 bit Rx GMAC FIFO Read Pointer */
3911-/* RX_GMF_RLEV 32 bit Rx GMAC FIFO Read Level */
3912+/* RX_GMF_WP 32 bit Rx GMAC FIFO Write Pointer */
3913+/* RX_GMF_WLEV 32 bit Rx GMAC FIFO Write Level */
3914+/* RX_GMF_RP 32 bit Rx GMAC FIFO Read Pointer */
3915+/* RX_GMF_RLEV 32 bit Rx GMAC FIFO Read Level */
3916 /* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */
3917 /* TX_GMF_AE_THR 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
3918-/* TX_GMF_WP 32 bit Tx GMAC FIFO Write Pointer */
3919-/* TX_GMF_WSP 32 bit Tx GMAC FIFO Write Shadow Ptr. */
3920-/* TX_GMF_WLEV 32 bit Tx GMAC FIFO Write Level */
3921-/* TX_GMF_RP 32 bit Tx GMAC FIFO Read Pointer */
3922-/* TX_GMF_RSTP 32 bit Tx GMAC FIFO Restart Pointer */
3923-/* TX_GMF_RLEV 32 bit Tx GMAC FIFO Read Level */
3924+/* TX_GMF_WP 32 bit Tx GMAC FIFO Write Pointer */
3925+/* TX_GMF_WSP 32 bit Tx GMAC FIFO Write Shadow Pointer */
3926+/* TX_GMF_WLEV 32 bit Tx GMAC FIFO Write Level */
3927+/* TX_GMF_RP 32 bit Tx GMAC FIFO Read Pointer */
3928+/* TX_GMF_RSTP 32 bit Tx GMAC FIFO Restart Pointer */
3929+/* TX_GMF_RLEV 32 bit Tx GMAC FIFO Read Level */
3930
3931 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
3932- /* Bits 31..15: reserved */
3933-#define GMF_WP_TST_ON BIT_14 /* Write Pointer Test On */
3934-#define GMF_WP_TST_OFF BIT_13 /* Write Pointer Test Off */
3935-#define GMF_WP_STEP BIT_12 /* Write Pointer Step/Increment */
3936+ /* Bit 31..28 reserved */
3937+#define RX_TRUNC_ON BIT_27 /* Enable Packet Truncation */
3938+#define RX_TRUNC_OFF BIT_26 /* Disable Packet Truncation */
3939+#define RX_VLAN_STRIP_ON BIT_25 /* Enable VLAN Stripping */
3940+#define RX_VLAN_STRIP_OFF BIT_24 /* Disable VLAN Stripping */
3941+ /* Bit 23..15 reserved */
3942+#define GMF_WP_TST_ON BIT_14 /* Write Pointer Test On */
3943+#define GMF_WP_TST_OFF BIT_13 /* Write Pointer Test Off */
3944+#define GMF_WP_STEP BIT_12 /* Write Pointer Step/Increment */
3945 /* Bit 11: reserved */
3946-#define GMF_RP_TST_ON BIT_10 /* Read Pointer Test On */
3947-#define GMF_RP_TST_OFF BIT_9 /* Read Pointer Test Off */
3948-#define GMF_RP_STEP BIT_8 /* Read Pointer Step/Increment */
3949-#define GMF_RX_F_FL_ON BIT_7 /* Rx FIFO Flush Mode On */
3950-#define GMF_RX_F_FL_OFF BIT_6 /* Rx FIFO Flush Mode Off */
3951-#define GMF_CLI_RX_FO BIT_5 /* Clear IRQ Rx FIFO Overrun */
3952-#define GMF_CLI_RX_FC BIT_4 /* Clear IRQ Rx Frame Complete */
3953-#define GMF_OPER_ON BIT_3 /* Operational Mode On */
3954-#define GMF_OPER_OFF BIT_2 /* Operational Mode Off */
3955-#define GMF_RST_CLR BIT_1 /* Clear GMAC FIFO Reset */
3956-#define GMF_RST_SET BIT_0 /* Set GMAC FIFO Reset */
3957-
3958-/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
3959- /* Bits 31..19: reserved */
3960-#define GMF_WSP_TST_ON BIT_18 /* Write Shadow Pointer Test On */
3961-#define GMF_WSP_TST_OFF BIT_17 /* Write Shadow Pointer Test Off */
3962-#define GMF_WSP_STEP BIT_16 /* Write Shadow Pointer Step/Increment */
3963- /* Bits 15..7: same as for RX_GMF_CTRL_T */
3964-#define GMF_CLI_TX_FU BIT_6 /* Clear IRQ Tx FIFO Underrun */
3965-#define GMF_CLI_TX_FC BIT_5 /* Clear IRQ Tx Frame Complete */
3966-#define GMF_CLI_TX_PE BIT_4 /* Clear IRQ Tx Parity Error */
3967+#define GMF_RP_TST_ON BIT_10 /* Read Pointer Test On */
3968+#define GMF_RP_TST_OFF BIT_9 /* Read Pointer Test Off */
3969+#define GMF_RP_STEP BIT_8 /* Read Pointer Step/Increment */
3970+#define GMF_RX_F_FL_ON BIT_7 /* Rx FIFO Flush Mode On */
3971+#define GMF_RX_F_FL_OFF BIT_6 /* Rx FIFO Flush Mode Off */
3972+#define GMF_CLI_RX_FO BIT_5 /* Clear IRQ Rx FIFO Overrun */
3973+#define GMF_CLI_RX_FC BIT_4 /* Clear IRQ Rx Frame Complete */
3974+#define GMF_OPER_ON BIT_3 /* Operational Mode On */
3975+#define GMF_OPER_OFF BIT_2 /* Operational Mode Off */
3976+#define GMF_RST_CLR BIT_1 /* Clear GMAC FIFO Reset */
3977+#define GMF_RST_SET BIT_0 /* Set GMAC FIFO Reset */
3978+
3979+/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test (YUKON and Yukon-2) */
3980+#define TX_STFW_DIS BIT_31 /* Disable Store & Forward (Yukon-EC Ultra) */
3981+#define TX_STFW_ENA BIT_30 /* Enable Store & Forward (Yukon-EC Ultra) */
3982+ /* Bits 29..26: reserved */
3983+#define TX_VLAN_TAG_ON BIT_25 /* Enable VLAN tagging */
3984+#define TX_VLAN_TAG_OFF BIT_24 /* Disable VLAN tagging */
3985+#define TX_PCI_JUM_ENA BIT_23 /* Enable PCI Jumbo Mode (Yukon-EC Ultra) */
3986+#define TX_PCI_JUM_DIS BIT_22 /* Disable PCI Jumbo Mode (Yukon-EC Ultra) */
3987+ /* Bits 21..19: reserved */
3988+#define GMF_WSP_TST_ON BIT_18 /* Write Shadow Pointer Test On */
3989+#define GMF_WSP_TST_OFF BIT_17 /* Write Shadow Pointer Test Off */
3990+#define GMF_WSP_STEP BIT_16 /* Write Shadow Pointer Step/Increment */
3991+ /* Bits 15..8: same as for RX_GMF_CTRL_T */
3992+ /* Bit 7: reserved */
3993+#define GMF_CLI_TX_FU BIT_6 /* Clear IRQ Tx FIFO Underrun */
3994+#define GMF_CLI_TX_FC BIT_5 /* Clear IRQ Tx Frame Complete */
3995+#define GMF_CLI_TX_PE BIT_4 /* Clear IRQ Tx Parity Error */
3996 /* Bits 3..0: same as for RX_GMF_CTRL_T */
3997
3998 #define GMF_RX_CTRL_DEF (GMF_OPER_ON | GMF_RX_F_FL_ON)
3999 #define GMF_TX_CTRL_DEF GMF_OPER_ON
4000
4001+#define RX_GMF_AF_THR_MIN 0x0c /* Rx GMAC FIFO Almost Full Thresh. min. */
4002 #define RX_GMF_FL_THR_DEF 0x0a /* Rx GMAC FIFO Flush Threshold default */
4003
4004 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
4005- /* Bit 7.. 3: reserved */
4006-#define GMT_ST_START BIT_2S /* Start Time Stamp Timer */
4007-#define GMT_ST_STOP BIT_1S /* Stop Time Stamp Timer */
4008-#define GMT_ST_CLR_IRQ BIT_0S /* Clear Time Stamp Timer IRQ */
4009-
4010+ /* Bit 7.. 3: reserved */
4011+#define GMT_ST_START BIT_2S /* Start Time Stamp Timer */
4012+#define GMT_ST_STOP BIT_1S /* Stop Time Stamp Timer */
4013+#define GMT_ST_CLR_IRQ BIT_0S /* Clear Time Stamp Timer IRQ */
4014+
4015+/* POLL_CTRL 32 bit Polling Unit control register (Yukon-2 only) */
4016+ /* Bit 31.. 6: reserved */
4017+#define PC_CLR_IRQ_CHK BIT_5 /* Clear IRQ Check */
4018+#define PC_POLL_RQ BIT_4 /* Poll Request Start */
4019+#define PC_POLL_OP_ON BIT_3 /* Operational Mode On */
4020+#define PC_POLL_OP_OFF BIT_2 /* Operational Mode Off */
4021+#define PC_POLL_RST_CLR BIT_1 /* Clear Polling Unit Reset (Enable) */
4022+#define PC_POLL_RST_SET BIT_0 /* Set Polling Unit Reset */
4023+
4024+
4025+/* The bit definition of the following registers is still missing! */
4026+/* B28_Y2_SMB_CONFIG 32 bit ASF SMBus Config Register */
4027+/* B28_Y2_SMB_CSD_REG 32 bit ASF SMB Control/Status/Data */
4028+/* B28_Y2_ASF_IRQ_V_BASE 32 bit ASF IRQ Vector Base */
4029+
4030+/* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */
4031+/* This register is used by the host driver software */
4032+ /* Bit 31.. 5 reserved */
4033+#define Y2_ASF_OS_PRES BIT_4S /* ASF operation system present */
4034+#define Y2_ASF_RESET BIT_3S /* ASF system in reset state */
4035+#define Y2_ASF_RUNNING BIT_2S /* ASF system operational */
4036+#define Y2_ASF_CLR_HSTI BIT_1S /* Clear ASF IRQ */
4037+#define Y2_ASF_IRQ BIT_0S /* Issue an IRQ to ASF system */
4038+
4039+#define Y2_ASF_UC_STATE (3<<2) /* ASF uC State */
4040+#define Y2_ASF_CLK_HALT 0 /* ASF system clock stopped */
4041+
4042+/* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */
4043+/* This register is used by the ASF firmware */
4044+ /* Bit 31.. 2 reserved */
4045+#define Y2_ASF_CLR_ASFI BIT_1 /* Clear host IRQ */
4046+#define Y2_ASF_HOST_IRQ BIT_0 /* Issue an IRQ to HOST system */
4047+
4048+
4049+/* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
4050+ /* Bit 7.. 5: reserved */
4051+#define SC_STAT_CLR_IRQ BIT_4 /* Status Burst IRQ clear */
4052+#define SC_STAT_OP_ON BIT_3 /* Operational Mode On */
4053+#define SC_STAT_OP_OFF BIT_2 /* Operational Mode Off */
4054+#define SC_STAT_RST_CLR BIT_1 /* Clear Status Unit Reset (Enable) */
4055+#define SC_STAT_RST_SET BIT_0 /* Set Status Unit Reset */
4056+
4057 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
4058 /* Bits 31.. 8: reserved */
4059-#define GMC_H_BURST_ON BIT_7 /* Half Duplex Burst Mode On */
4060-#define GMC_H_BURST_OFF BIT_6 /* Half Duplex Burst Mode Off */
4061-#define GMC_F_LOOPB_ON BIT_5 /* FIFO Loopback On */
4062-#define GMC_F_LOOPB_OFF BIT_4 /* FIFO Loopback Off */
4063-#define GMC_PAUSE_ON BIT_3 /* Pause On */
4064-#define GMC_PAUSE_OFF BIT_2 /* Pause Off */
4065-#define GMC_RST_CLR BIT_1 /* Clear GMAC Reset */
4066-#define GMC_RST_SET BIT_0 /* Set GMAC Reset */
4067+#define GMC_H_BURST_ON BIT_7 /* Half Duplex Burst Mode On */
4068+#define GMC_H_BURST_OFF BIT_6 /* Half Duplex Burst Mode Off */
4069+#define GMC_F_LOOPB_ON BIT_5 /* FIFO Loopback On */
4070+#define GMC_F_LOOPB_OFF BIT_4 /* FIFO Loopback Off */
4071+#define GMC_PAUSE_ON BIT_3 /* Pause On */
4072+#define GMC_PAUSE_OFF BIT_2 /* Pause Off */
4073+#define GMC_RST_CLR BIT_1 /* Clear GMAC Reset */
4074+#define GMC_RST_SET BIT_0 /* Set GMAC Reset */
4075
4076 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
4077 /* Bits 31..29: reserved */
4078 #define GPC_SEL_BDT BIT_28 /* Select Bi-Dir. Transfer for MDC/MDIO */
4079-#define GPC_INT_POL_HI BIT_27 /* IRQ Polarity is Active HIGH */
4080+#define GPC_INT_POL BIT_27 /* IRQ Polarity is Active Low */
4081 #define GPC_75_OHM BIT_26 /* Use 75 Ohm Termination instead of 50 */
4082 #define GPC_DIS_FC BIT_25 /* Disable Automatic Fiber/Copper Detection */
4083 #define GPC_DIS_SLEEP BIT_24 /* Disable Energy Detect */
4084@@ -1501,15 +2162,24 @@
4085 #define GPC_ANEG_2 BIT_15 /* ANEG[2] */
4086 #define GPC_ANEG_1 BIT_14 /* ANEG[1] */
4087 #define GPC_ENA_PAUSE BIT_13 /* Enable Pause (SYM_OR_REM) */
4088-#define GPC_PHYADDR_4 BIT_12 /* Bit 4 of Phy Addr */
4089-#define GPC_PHYADDR_3 BIT_11 /* Bit 3 of Phy Addr */
4090-#define GPC_PHYADDR_2 BIT_10 /* Bit 2 of Phy Addr */
4091-#define GPC_PHYADDR_1 BIT_9 /* Bit 1 of Phy Addr */
4092-#define GPC_PHYADDR_0 BIT_8 /* Bit 0 of Phy Addr */
4093+#define GPC_PHYADDR_4 BIT_12 /* Bit 4 of PHY Addr */
4094+#define GPC_PHYADDR_3 BIT_11 /* Bit 3 of PHY Addr */
4095+#define GPC_PHYADDR_2 BIT_10 /* Bit 2 of PHY Addr */
4096+#define GPC_PHYADDR_1 BIT_9 /* Bit 1 of PHY Addr */
4097+#define GPC_PHYADDR_0 BIT_8 /* Bit 0 of PHY Addr */
4098 /* Bits 7..2: reserved */
4099 #define GPC_RST_CLR BIT_1 /* Clear GPHY Reset */
4100 #define GPC_RST_SET BIT_0 /* Set GPHY Reset */
4101
4102+/* Yukon-EC Ultra only */
4103+#define GPC_LED_CONF_MSK (7<<6) /* Bit 8.. 6: GPHY LED Config */
4104+#define GPC_PD_125M_CLK_OFF BIT_5 /* Disable Power Down Clock 125 MHz */
4105+#define GPC_PD_125M_CLK_ON BIT_4 /* Enable Power Down Clock 125 MHz */
4106+#define GPC_DPLL_RST_SET BIT_3 /* Set GPHY's DPLL Reset */
4107+#define GPC_DPLL_RST_CLR BIT_2 /* Clear GPHY's DPLL Reset */
4108+ /* (DPLL = Digital Phase Lock Loop) */
4109+#define GPC_LED_CONF_VAL(x) (SHIFT6(x) & GPC_LED_CONF_MSK)
4110+
4111 #define GPC_HWCFG_GMII_COP (GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | \
4112 GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
4113
4114@@ -1540,20 +2210,20 @@
4115
4116 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
4117 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
4118-#define GM_IS_TX_CO_OV BIT_5 /* Transmit Counter Overflow IRQ */
4119-#define GM_IS_RX_CO_OV BIT_4 /* Receive Counter Overflow IRQ */
4120-#define GM_IS_TX_FF_UR BIT_3 /* Transmit FIFO Underrun */
4121-#define GM_IS_TX_COMPL BIT_2 /* Frame Transmission Complete */
4122-#define GM_IS_RX_FF_OR BIT_1 /* Receive FIFO Overrun */
4123-#define GM_IS_RX_COMPL BIT_0 /* Frame Reception Complete */
4124+#define GM_IS_RX_CO_OV BIT_5S /* Receive Counter Overflow IRQ */
4125+#define GM_IS_TX_CO_OV BIT_4S /* Transmit Counter Overflow IRQ */
4126+#define GM_IS_TX_FF_UR BIT_3S /* Transmit FIFO Underrun */
4127+#define GM_IS_TX_COMPL BIT_2S /* Frame Transmission Complete */
4128+#define GM_IS_RX_FF_OR BIT_1S /* Receive FIFO Overrun */
4129+#define GM_IS_RX_COMPL BIT_0S /* Frame Reception Complete */
4130
4131-#define GMAC_DEF_MSK (GM_IS_TX_CO_OV | GM_IS_RX_CO_OV | \
4132+#define GMAC_DEF_MSK (GM_IS_RX_CO_OV | GM_IS_TX_CO_OV | \
4133 GM_IS_TX_FF_UR)
4134
4135-/* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
4136+/* GMAC_LINK_CTRL 16 bit Link Control Reg (YUKON only) */
4137 /* Bits 15.. 2: reserved */
4138-#define GMLC_RST_CLR BIT_1S /* Clear GMAC Link Reset */
4139-#define GMLC_RST_SET BIT_0S /* Set GMAC Link Reset */
4140+#define GMLC_RST_CLR BIT_1S /* Clear Link Reset */
4141+#define GMLC_RST_SET BIT_0S /* Set Link Reset */
4142
4143
4144 /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
4145@@ -1579,15 +2249,19 @@
4146
4147 #define WOL_CTL_DEFAULT \
4148 (WOL_CTL_DIS_PME_ON_LINK_CHG | \
4149- WOL_CTL_DIS_PME_ON_PATTERN | \
4150- WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
4151- WOL_CTL_DIS_LINK_CHG_UNIT | \
4152- WOL_CTL_DIS_PATTERN_UNIT | \
4153- WOL_CTL_DIS_MAGIC_PKT_UNIT)
4154+ WOL_CTL_DIS_PME_ON_PATTERN | \
4155+ WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
4156+ WOL_CTL_DIS_LINK_CHG_UNIT | \
4157+ WOL_CTL_DIS_PATTERN_UNIT | \
4158+ WOL_CTL_DIS_MAGIC_PKT_UNIT)
4159
4160 /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
4161 #define WOL_CTL_PATT_ENA(x) (BIT_0 << (x))
4162
4163+/* WOL_PATT_PME 8 bit WOL PME Match Enable (Yukon-2) */
4164+#define WOL_PATT_FORCE_PME BIT_7 /* Generates a PME */
4165+#define WOL_PATT_MATCH_PME_ALL 0x7f
4166+
4167 #define SK_NUM_WOL_PATTERN 7
4168 #define SK_PATTERN_PER_WORD 4
4169 #define SK_BITMASK_PATTERN 7
4170@@ -1597,26 +2271,28 @@
4171 #define WOL_LENGTH_SHIFT 8
4172
4173
4174+/* typedefs ******************************************************************/
4175+
4176 /* Receive and Transmit Descriptors ******************************************/
4177
4178 /* Transmit Descriptor struct */
4179 typedef struct s_HwTxd {
4180 SK_U32 volatile TxCtrl; /* Transmit Buffer Control Field */
4181 SK_U32 TxNext; /* Physical Address Pointer to the next TxD */
4182- SK_U32 TxAdrLo; /* Physical Tx Buffer Address lower dword */
4183- SK_U32 TxAdrHi; /* Physical Tx Buffer Address upper dword */
4184+ SK_U32 TxAdrLo; /* Physical Tx Buffer Address lower DWord */
4185+ SK_U32 TxAdrHi; /* Physical Tx Buffer Address upper DWord */
4186 SK_U32 TxStat; /* Transmit Frame Status Word */
4187-#ifndef SK_USE_REV_DESC
4188+#ifndef SK_USE_REV_DESC
4189 SK_U16 TxTcpOffs; /* TCP Checksum Calculation Start Value */
4190 SK_U16 TxRes1; /* 16 bit reserved field */
4191 SK_U16 TxTcpWp; /* TCP Checksum Write Position */
4192 SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */
4193-#else /* SK_USE_REV_DESC */
4194+#else /* SK_USE_REV_DESC */
4195 SK_U16 TxRes1; /* 16 bit reserved field */
4196 SK_U16 TxTcpOffs; /* TCP Checksum Calculation Start Value */
4197 SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */
4198 SK_U16 TxTcpWp; /* TCP Checksum Write Position */
4199-#endif /* SK_USE_REV_DESC */
4200+#endif /* SK_USE_REV_DESC */
4201 SK_U32 TxRes2; /* 32 bit reserved field */
4202 } SK_HWTXD;
4203
4204@@ -1624,33 +2300,266 @@
4205 typedef struct s_HwRxd {
4206 SK_U32 volatile RxCtrl; /* Receive Buffer Control Field */
4207 SK_U32 RxNext; /* Physical Address Pointer to the next RxD */
4208- SK_U32 RxAdrLo; /* Physical Rx Buffer Address lower dword */
4209- SK_U32 RxAdrHi; /* Physical Rx Buffer Address upper dword */
4210+ SK_U32 RxAdrLo; /* Physical Rx Buffer Address lower DWord */
4211+ SK_U32 RxAdrHi; /* Physical Rx Buffer Address upper DWord */
4212 SK_U32 RxStat; /* Receive Frame Status Word */
4213 SK_U32 RxTiSt; /* Receive Time Stamp (from XMAC on GENESIS) */
4214-#ifndef SK_USE_REV_DESC
4215- SK_U16 RxTcpSum1; /* TCP Checksum 1 */
4216- SK_U16 RxTcpSum2; /* TCP Checksum 2 */
4217+#ifndef SK_USE_REV_DESC
4218+ SK_U16 RxTcpSum1; /* Rx TCP Checksum 1 */
4219+ SK_U16 RxTcpSum2; /* Rx TCP Checksum 2 */
4220 SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */
4221 SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */
4222-#else /* SK_USE_REV_DESC */
4223- SK_U16 RxTcpSum2; /* TCP Checksum 2 */
4224- SK_U16 RxTcpSum1; /* TCP Checksum 1 */
4225+#else /* SK_USE_REV_DESC */
4226+ SK_U16 RxTcpSum2; /* Rx TCP Checksum 2 */
4227+ SK_U16 RxTcpSum1; /* Rx TCP Checksum 1 */
4228 SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */
4229 SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */
4230-#endif /* SK_USE_REV_DESC */
4231+#endif /* SK_USE_REV_DESC */
4232 } SK_HWRXD;
4233
4234 /*
4235 * Drivers which use the reverse descriptor feature (PCI_OUR_REG_2)
4236 * should set the define SK_USE_REV_DESC.
4237- * Structures are 'normaly' not endianess dependent. But in
4238- * this case the SK_U16 fields are bound to bit positions inside the
4239- * descriptor. RxTcpSum1 e.g. must start at bit 0 within the 6.th DWord.
4240+ * Structures are 'normally' not endianess dependent. But in this case
4241+ * the SK_U16 fields are bound to bit positions inside the descriptor.
4242+ * RxTcpSum1 e.g. must start at bit 0 within the 7.th DWord.
4243 * The bit positions inside a DWord are of course endianess dependent and
4244- * swaps if the DWord is swapped by the hardware.
4245+ * swap if the DWord is swapped by the hardware.
4246 */
4247
4248+/* YUKON-2 descriptors ******************************************************/
4249+
4250+typedef struct _TxChksum {
4251+#ifndef SK_USE_REV_DESC
4252+ SK_U16 TxTcpWp; /* TCP Checksum Write Position */
4253+ SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */
4254+#else /* SK_USE_REV_DESC */
4255+ SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */
4256+ SK_U16 TxTcpWp; /* TCP Checksum Write Position */
4257+#endif /* SK_USE_REV_DESC */
4258+} SK_HWTXCS;
4259+
4260+typedef struct _LargeSend {
4261+#ifndef SK_USE_REV_DESC
4262+ SK_U16 Length; /* Large Send Segment Length */
4263+ SK_U16 Reserved; /* reserved */
4264+#else /* SK_USE_REV_DESC */
4265+ SK_U16 Reserved; /* reserved */
4266+ SK_U16 Length; /* Large Send Segment Length */
4267+#endif /* SK_USE_REV_DESC */
4268+} SK_HWTXLS;
4269+
4270+typedef union u_HwTxBuf {
4271+ SK_U16 BufLen; /* Tx Buffer Length */
4272+ SK_U16 VlanTag; /* VLAN Tag */
4273+ SK_U16 InitCsum; /* Init. Checksum */
4274+} SK_HWTXBUF;
4275+
4276+/* Tx List Element structure */
4277+typedef struct s_HwLeTx {
4278+ union {
4279+ SK_U32 BufAddr; /* Tx LE Buffer Address high/low */
4280+ SK_HWTXCS ChkSum; /* Tx LE TCP Checksum parameters */
4281+ SK_HWTXLS LargeSend;/* Large Send length */
4282+ } TxUn;
4283+#ifndef SK_USE_REV_DESC
4284+ SK_HWTXBUF Send;
4285+ SK_U8 ControlFlags; /* Tx LE Control field or Lock Number */
4286+ SK_U8 Opcode; /* Tx LE Opcode field */
4287+#else /* SK_USE_REV_DESC */
4288+ SK_U8 Opcode; /* Tx LE Opcode field */
4289+ SK_U8 ControlFlags; /* Tx LE Control field or Lock Number */
4290+ SK_HWTXBUF Send;
4291+#endif /* SK_USE_REV_DESC */
4292+} SK_HWLETX;
4293+
4294+typedef struct _RxChkSum{
4295+#ifndef SK_USE_REV_DESC
4296+ SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */
4297+ SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */
4298+#else /* SK_USE_REV_DESC */
4299+ SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */
4300+ SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */
4301+#endif /* SK_USE_REV_DESC */
4302+} SK_HWRXCS;
4303+
4304+/* Rx List Element structure */
4305+typedef struct s_HwLeRx {
4306+ union {
4307+ SK_U32 BufAddr; /* Rx LE Buffer Address high/low */
4308+ SK_HWRXCS ChkSum; /* Rx LE TCP Checksum parameters */
4309+ } RxUn;
4310+#ifndef SK_USE_REV_DESC
4311+ SK_U16 BufferLength; /* Rx LE Buffer Length field */
4312+ SK_U8 ControlFlags; /* Rx LE Control field */
4313+ SK_U8 Opcode; /* Rx LE Opcode field */
4314+#else /* SK_USE_REV_DESC */
4315+ SK_U8 Opcode; /* Rx LE Opcode field */
4316+ SK_U8 ControlFlags; /* Rx LE Control field */
4317+ SK_U16 BufferLength; /* Rx LE Buffer Length field */
4318+#endif /* SK_USE_REV_DESC */
4319+} SK_HWLERX;
4320+
4321+typedef struct s_StRxTCPChkSum {
4322+#ifndef SK_USE_REV_DESC
4323+ SK_U16 RxTCPSum1; /* Rx TCP Checksum 1 */
4324+ SK_U16 RxTCPSum2; /* Rx TCP Checksum 2 */
4325+#else /* SK_USE_REV_DESC */
4326+ SK_U16 RxTCPSum2; /* Rx TCP Checksum 2 */
4327+ SK_U16 RxTCPSum1; /* Rx TCP Checksum 1 */
4328+#endif /* SK_USE_REV_DESC */
4329+} SK_HWSTCS;
4330+
4331+typedef struct s_StRxRssFlags {
4332+#ifndef SK_USE_REV_DESC
4333+ SK_U8 FlagField; /* contains TCP and IP flags */
4334+ SK_U8 reserved; /* reserved */
4335+#else /* SK_USE_REV_DESC */
4336+ SK_U8 reserved; /* reserved */
4337+ SK_U8 FlagField; /* contains TCP and IP flags */
4338+#endif /* SK_USE_REV_DESC */
4339+} SK_HWSTRSS;
4340+
4341+/* bit definition of RSS LE bit 32/33 (SK_HWSTRSS.FlagField) */
4342+ /* bit 7..2 reserved */
4343+#define RSS_TCP_FLAG BIT_1S /* RSS value related to TCP area */
4344+#define RSS_IP_FLAG BIT_0S /* RSS value related to IP area */
4345+/* StRxRssValue is valid if at least RSS_IP_FLAG is set */
4346+/* For protocol errors or other protocols an empty RSS LE is generated */
4347+
4348+typedef union u_HwStBuf {
4349+ SK_U16 BufLen; /* Rx Buffer Length */
4350+ SK_U16 VlanTag; /* VLAN Tag */
4351+ SK_U16 StTxStatHi; /* Tx Queue Status (high) */
4352+ SK_HWSTRSS Rss; /* Flag Field for TCP and IP protocol */
4353+} SK_HWSTBUF;
4354+
4355+/* Status List Element structure */
4356+typedef struct s_HwLeSt {
4357+ union {
4358+ SK_U32 StRxStatWord; /* Rx Status Dword */
4359+ SK_U32 StRxTimeStamp; /* Rx Timestamp */
4360+ SK_HWSTCS StRxTCPCSum; /* Rx TCP Checksum */
4361+ SK_U32 StTxStatLow; /* Tx Queue Status (low) */
4362+ SK_U32 StRxRssValue; /* Rx RSS value */
4363+ } StUn;
4364+#ifndef SK_USE_REV_DESC
4365+ SK_HWSTBUF Stat;
4366+ SK_U8 Link; /* Status LE Link field */
4367+ SK_U8 Opcode; /* Status LE Opcode field */
4368+#else /* SK_USE_REV_DESC */
4369+ SK_U8 Opcode; /* Status LE Opcode field */
4370+ SK_U8 Link; /* Status LE Link field */
4371+ SK_HWSTBUF Stat;
4372+#endif /* SK_USE_REV_DESC */
4373+} SK_HWLEST;
4374+
4375+/* Special Action List Element */
4376+typedef struct s_HwLeSa {
4377+#ifndef SK_USE_REV_DESC
4378+ SK_U16 TxAIdxVld; /* Special Action LE TxA Put Index field */
4379+ SK_U16 TxSIdxVld; /* Special Action LE TxS Put Index field */
4380+ SK_U16 RxIdxVld; /* Special Action LE Rx Put Index field */
4381+ SK_U8 Link; /* Special Action LE Link field */
4382+ SK_U8 Opcode; /* Special Action LE Opcode field */
4383+#else /* SK_USE_REV_DESC */
4384+ SK_U16 TxSIdxVld; /* Special Action LE TxS Put Index field */
4385+ SK_U16 TxAIdxVld; /* Special Action LE TxA Put Index field */
4386+ SK_U8 Opcode; /* Special Action LE Opcode field */
4387+ SK_U8 Link; /* Special Action LE Link field */
4388+ SK_U16 RxIdxVld; /* Special Action LE Rx Put Index field */
4389+#endif /* SK_USE_REV_DESC */
4390+} SK_HWLESA;
4391+
4392+/* Common List Element union */
4393+typedef union u_HwLeTxRxSt {
4394+ /* Transmit List Element Structure */
4395+ SK_HWLETX Tx;
4396+ /* Receive List Element Structure */
4397+ SK_HWLERX Rx;
4398+ /* Status List Element Structure */
4399+ SK_HWLEST St;
4400+ /* Special Action List Element Structure */
4401+ SK_HWLESA Sa;
4402+ /* Full List Element */
4403+ SK_U64 Full;
4404+} SK_HWLE;
4405+
4406+/* mask and shift value to get Tx async queue status for port 1 */
4407+#define STLE_TXA1_MSKL 0x00000fff
4408+#define STLE_TXA1_SHIFTL 0
4409+
4410+/* mask and shift value to get Tx sync queue status for port 1 */
4411+#define STLE_TXS1_MSKL 0x00fff000
4412+#define STLE_TXS1_SHIFTL 12
4413+
4414+/* mask and shift value to get Tx async queue status for port 2 */
4415+#define STLE_TXA2_MSKL 0xff000000
4416+#define STLE_TXA2_SHIFTL 24
4417+#define STLE_TXA2_MSKH 0x000f
4418+/* this one shifts up */
4419+#define STLE_TXA2_SHIFTH 8
4420+
4421+/* mask and shift value to get Tx sync queue status for port 2 */
4422+#define STLE_TXS2_MSKL 0x00000000
4423+#define STLE_TXS2_SHIFTL 0
4424+#define STLE_TXS2_MSKH 0xfff0
4425+#define STLE_TXS2_SHIFTH 4
4426+
4427+/* YUKON-2 bit values */
4428+#define HW_OWNER BIT_7
4429+#define SW_OWNER 0
4430+
4431+#define PU_PUTIDX_VALID BIT_12
4432+
4433+/* YUKON-2 Control flags */
4434+#define UDPTCP BIT_0S
4435+#define CALSUM BIT_1S
4436+#define WR_SUM BIT_2S
4437+#define INIT_SUM BIT_3S
4438+#define LOCK_SUM BIT_4S
4439+#define INS_VLAN BIT_5S
4440+#define FRC_STAT BIT_6S
4441+#define EOP BIT_7S
4442+
4443+#define TX_LOCK BIT_8S
4444+#define BUF_SEND BIT_9S
4445+#define PACKET_SEND BIT_10S
4446+
4447+#define NO_WARNING BIT_14S
4448+#define NO_UPDATE BIT_15S
4449+
4450+/* YUKON-2 Rx/Tx opcodes defines */
4451+#define OP_TCPWRITE 0x11
4452+#define OP_TCPSTART 0x12
4453+#define OP_TCPINIT 0x14
4454+#define OP_TCPLCK 0x18
4455+#define OP_TCPCHKSUM OP_TCPSTART
4456+#define OP_TCPIS (OP_TCPINIT | OP_TCPSTART)
4457+#define OP_TCPLW (OP_TCPLCK | OP_TCPWRITE)
4458+#define OP_TCPLSW (OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE)
4459+#define OP_TCPLISW (OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE)
4460+#define OP_ADDR64 0x21
4461+#define OP_VLAN 0x22
4462+#define OP_ADDR64VLAN (OP_ADDR64 | OP_VLAN)
4463+#define OP_LRGLEN 0x24
4464+#define OP_LRGLENVLAN (OP_LRGLEN | OP_VLAN)
4465+#define OP_BUFFER 0x40
4466+#define OP_PACKET 0x41
4467+#define OP_LARGESEND 0x43
4468+
4469+/* YUKON-2 STATUS opcodes defines */
4470+#define OP_RXSTAT 0x60
4471+#define OP_RXTIMESTAMP 0x61
4472+#define OP_RXVLAN 0x62
4473+#define OP_RXCHKS 0x64
4474+#define OP_RXCHKSVLAN (OP_RXCHKS | OP_RXVLAN)
4475+#define OP_RXTIMEVLAN (OP_RXTIMESTAMP | OP_RXVLAN)
4476+#define OP_RSS_HASH 0x65
4477+#define OP_TXINDEXLE 0x68
4478+
4479+/* YUKON-2 SPECIAL opcodes defines */
4480+#define OP_PUTIDX 0x70
4481
4482 /* Descriptor Bit Definition */
4483 /* TxCtrl Transmit Buffer Control Field */
4484@@ -1685,6 +2594,10 @@
4485
4486 /* macros ********************************************************************/
4487
4488+/* Macro for accessing the key registers */
4489+#define RSS_KEY_ADDR(Port, KeyIndex) \
4490+ ((B4_RSS_KEY | ( ((Port) == 0) ? 0 : 0x80)) + (KeyIndex))
4491+
4492 /* Receive and Transmit Queues */
4493 #define Q_R1 0x0000 /* Receive Queue 1 */
4494 #define Q_R2 0x0080 /* Receive Queue 2 */
4495@@ -1693,6 +2606,10 @@
4496 #define Q_XS2 0x0300 /* Synchronous Transmit Queue 2 */
4497 #define Q_XA2 0x0380 /* Asynchronous Transmit Queue 2 */
4498
4499+#define Q_ASF_R1 0x100 /* ASF Rx Queue 1 */
4500+#define Q_ASF_R2 0x180 /* ASF Rx Queue 2 */
4501+#define Q_ASF_T1 0x140 /* ASF Tx Queue 1 */
4502+#define Q_ASF_T2 0x1c0 /* ASF Tx Queue 2 */
4503 /*
4504 * Macro Q_ADDR()
4505 *
4506@@ -1704,11 +2621,27 @@
4507 * Offs Queue register offset.
4508 * Values: Q_D, Q_DA_L ... Q_T2, Q_T3
4509 *
4510- * usage SK_IN32(pAC, Q_ADDR(Q_R2, Q_BC), pVal)
4511+ * usage SK_IN32(IoC, Q_ADDR(Q_R2, Q_BC), pVal)
4512 */
4513 #define Q_ADDR(Queue, Offs) (B8_Q_REGS + (Queue) + (Offs))
4514
4515 /*
4516+ * Macro Y2_PREF_Q_ADDR()
4517+ *
4518+ * Use this macro to access the Prefetch Units of the receive and
4519+ * transmit queues of Yukon-2.
4520+ *
4521+ * para:
4522+ * Queue Queue to access.
4523+ * Values: Q_R1, Q_R2, Q_XS1, Q_XA1, Q_XS2, Q_XA2,
4524+ * Offs Queue register offset.
4525+ * Values: PREF_UNIT_CTRL_REG ... PREF_UNIT_FIFO_LEV_REG
4526+ *
4527+ * usage SK_IN16(IoC, Y2_Q_ADDR(Q_R2, PREF_UNIT_GET_IDX_REG), pVal)
4528+ */
4529+#define Y2_PREF_Q_ADDR(Queue, Offs) (Y2_B8_PREF_REGS + (Queue) + (Offs))
4530+
4531+/*
4532 * Macro RB_ADDR()
4533 *
4534 * Use this macro to access the RAM Buffer Registers.
4535@@ -1719,14 +2652,14 @@
4536 * Offs Queue register offset.
4537 * Values: RB_START, RB_END ... RB_LEV, RB_CTRL
4538 *
4539- * usage SK_IN32(pAC, RB_ADDR(Q_R2, RB_RP), pVal)
4540+ * usage SK_IN32(IoC, RB_ADDR(Q_R2, RB_RP), pVal)
4541 */
4542 #define RB_ADDR(Queue, Offs) (B16_RAM_REGS + (Queue) + (Offs))
4543
4544
4545 /* MAC Related Registers */
4546-#define MAC_1 0 /* belongs to the port near the slot */
4547-#define MAC_2 1 /* belongs to the port far away from the slot */
4548+#define MAC_1 0 /* 1st port */
4549+#define MAC_2 1 /* 2nd port */
4550
4551 /*
4552 * Macro MR_ADDR()
4553@@ -1740,19 +2673,10 @@
4554 * Values: RX_MFF_EA, RX_MFF_WP ... LNK_LED_REG,
4555 * TX_MFF_EA, TX_MFF_WP ... TX_LED_TST
4556 *
4557- * usage SK_IN32(pAC, MR_ADDR(MAC_1, TX_MFF_EA), pVal)
4558+ * usage SK_IN32(IoC, MR_ADDR(MAC_1, TX_MFF_EA), pVal)
4559 */
4560 #define MR_ADDR(Mac, Offs) (((Mac) << 7) + (Offs))
4561
4562-#ifdef SK_LITTLE_ENDIAN
4563-#define XM_WORD_LO 0
4564-#define XM_WORD_HI 1
4565-#else /* !SK_LITTLE_ENDIAN */
4566-#define XM_WORD_LO 1
4567-#define XM_WORD_HI 0
4568-#endif /* !SK_LITTLE_ENDIAN */
4569-
4570-
4571 /*
4572 * macros to access the XMAC (GENESIS only)
4573 *
4574@@ -1777,22 +2701,31 @@
4575 #define XMA(Mac, Reg) \
4576 ((BASE_XMAC_1 + (Mac) * (BASE_XMAC_2 - BASE_XMAC_1)) | ((Reg) << 1))
4577
4578-#define XM_IN16(IoC, Mac, Reg, pVal) \
4579- SK_IN16((IoC), XMA((Mac), (Reg)), (pVal))
4580+#define XM_IN16(IoC, Mac, Reg, pVal) \
4581+ SK_IN16(IoC, XMA(Mac, Reg), pVal)
4582+
4583+#define XM_OUT16(IoC, Mac, Reg, Val) \
4584+ SK_OUT16(IoC, XMA(Mac, Reg), Val)
4585
4586-#define XM_OUT16(IoC, Mac, Reg, Val) \
4587- SK_OUT16((IoC), XMA((Mac), (Reg)), (Val))
4588+#ifdef SK_LITTLE_ENDIAN
4589
4590-#define XM_IN32(IoC, Mac, Reg, pVal) { \
4591- SK_IN16((IoC), XMA((Mac), (Reg)), \
4592- (SK_U16 SK_FAR*)&((SK_U16 SK_FAR*)(pVal))[XM_WORD_LO]); \
4593- SK_IN16((IoC), XMA((Mac), (Reg+2)), \
4594- (SK_U16 SK_FAR*)&((SK_U16 SK_FAR*)(pVal))[XM_WORD_HI]); \
4595+#define XM_IN32(IoC, Mac, Reg, pVal) { \
4596+ SK_IN16(IoC, XMA(Mac, Reg), (SK_U16 SK_FAR *)(pVal)); \
4597+ SK_IN16(IoC, XMA(Mac, (Reg) + 2), (SK_U16 SK_FAR *)(pVal) + 1); \
4598 }
4599
4600+#else /* !SK_LITTLE_ENDIAN */
4601+
4602+#define XM_IN32(IoC, Mac, Reg, pVal) { \
4603+ SK_IN16(IoC, XMA(Mac, Reg), (SK_U16 SK_FAR *)(pVal) + 1); \
4604+ SK_IN16(IoC, XMA(Mac, (Reg) + 2), (SK_U16 SK_FAR *)(pVal)); \
4605+}
4606+
4607+#endif /* !SK_LITTLE_ENDIAN */
4608+
4609 #define XM_OUT32(IoC, Mac, Reg, Val) { \
4610- SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16)((Val) & 0xffffL)); \
4611- SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16)(((Val) >> 16) & 0xffffL));\
4612+ SK_OUT16(IoC, XMA(Mac, Reg), (SK_U16)((Val) & 0xffffL)); \
4613+ SK_OUT16(IoC, XMA(Mac, (Reg) + 2), (SK_U16)(((Val) >> 16) & 0xffffL)); \
4614 }
4615
4616 /* Remember: we are always writing to / reading from LITTLE ENDIAN memory */
4617@@ -1802,13 +2735,13 @@
4618 SK_U8 *pByte; \
4619 pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \
4620 SK_IN16((IoC), XMA((Mac), (Reg)), &Word); \
4621- pByte[0] = (SK_U8)(Word & 0x00ff); \
4622+ pByte[0] = (SK_U8)(Word & 0x00ff); \
4623 pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \
4624- SK_IN16((IoC), XMA((Mac), (Reg+2)), &Word); \
4625- pByte[2] = (SK_U8)(Word & 0x00ff); \
4626+ SK_IN16((IoC), XMA((Mac), (Reg) + 2), &Word); \
4627+ pByte[2] = (SK_U8)(Word & 0x00ff); \
4628 pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \
4629- SK_IN16((IoC), XMA((Mac), (Reg+4)), &Word); \
4630- pByte[4] = (SK_U8)(Word & 0x00ff); \
4631+ SK_IN16((IoC), XMA((Mac), (Reg) + 4), &Word); \
4632+ pByte[4] = (SK_U8)(Word & 0x00ff); \
4633 pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \
4634 }
4635
4636@@ -1818,10 +2751,10 @@
4637 SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16) \
4638 (((SK_U16)(pByte[0]) & 0x00ff) | \
4639 (((SK_U16)(pByte[1]) << 8) & 0xff00))); \
4640- SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16) \
4641+ SK_OUT16((IoC), XMA((Mac), (Reg) + 2), (SK_U16) \
4642 (((SK_U16)(pByte[2]) & 0x00ff) | \
4643 (((SK_U16)(pByte[3]) << 8) & 0xff00))); \
4644- SK_OUT16((IoC), XMA((Mac), (Reg+4)), (SK_U16) \
4645+ SK_OUT16((IoC), XMA((Mac), (Reg) + 4), (SK_U16) \
4646 (((SK_U16)(pByte[4]) & 0x00ff) | \
4647 (((SK_U16)(pByte[5]) << 8) & 0xff00))); \
4648 }
4649@@ -1831,16 +2764,16 @@
4650 SK_U8 SK_FAR *pByte; \
4651 pByte = (SK_U8 SK_FAR *)&((SK_U8 SK_FAR *)(pVal))[0]; \
4652 SK_IN16((IoC), XMA((Mac), (Reg)), &Word); \
4653- pByte[0] = (SK_U8)(Word & 0x00ff); \
4654+ pByte[0] = (SK_U8)(Word & 0x00ff); \
4655 pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \
4656- SK_IN16((IoC), XMA((Mac), (Reg+2)), &Word); \
4657- pByte[2] = (SK_U8)(Word & 0x00ff); \
4658+ SK_IN16((IoC), XMA((Mac), (Reg) + 2), &Word); \
4659+ pByte[2] = (SK_U8)(Word & 0x00ff); \
4660 pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \
4661- SK_IN16((IoC), XMA((Mac), (Reg+4)), &Word); \
4662- pByte[4] = (SK_U8)(Word & 0x00ff); \
4663+ SK_IN16((IoC), XMA((Mac), (Reg) + 4), &Word); \
4664+ pByte[4] = (SK_U8)(Word & 0x00ff); \
4665 pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \
4666- SK_IN16((IoC), XMA((Mac), (Reg+6)), &Word); \
4667- pByte[6] = (SK_U8)(Word & 0x00ff); \
4668+ SK_IN16((IoC), XMA((Mac), (Reg) + 6), &Word); \
4669+ pByte[6] = (SK_U8)(Word & 0x00ff); \
4670 pByte[7] = (SK_U8)((Word >> 8) & 0x00ff); \
4671 }
4672
4673@@ -1850,13 +2783,13 @@
4674 SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16) \
4675 (((SK_U16)(pByte[0]) & 0x00ff)| \
4676 (((SK_U16)(pByte[1]) << 8) & 0xff00))); \
4677- SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16) \
4678+ SK_OUT16((IoC), XMA((Mac), (Reg) + 2), (SK_U16) \
4679 (((SK_U16)(pByte[2]) & 0x00ff)| \
4680 (((SK_U16)(pByte[3]) << 8) & 0xff00))); \
4681- SK_OUT16((IoC), XMA((Mac), (Reg+4)), (SK_U16) \
4682+ SK_OUT16((IoC), XMA((Mac), (Reg) + 4), (SK_U16) \
4683 (((SK_U16)(pByte[4]) & 0x00ff)| \
4684 (((SK_U16)(pByte[5]) << 8) & 0xff00))); \
4685- SK_OUT16((IoC), XMA((Mac), (Reg+6)), (SK_U16) \
4686+ SK_OUT16((IoC), XMA((Mac), (Reg) + 6), (SK_U16) \
4687 (((SK_U16)(pByte[6]) & 0x00ff)| \
4688 (((SK_U16)(pByte[7]) << 8) & 0xff00))); \
4689 }
4690@@ -1866,12 +2799,12 @@
4691 *
4692 * GM_IN16(), to read a 16 bit register (e.g. GM_GP_STAT)
4693 * GM_OUT16(), to write a 16 bit register (e.g. GM_GP_CTRL)
4694- * GM_IN32(), to read a 32 bit register (e.g. GM_)
4695- * GM_OUT32(), to write a 32 bit register (e.g. GM_)
4696+ * GM_IN32(), to read a 32 bit register (e.g. GM_RXF_UC_OK)
4697+ * GM_OUT32(), to write a 32 bit register
4698 * GM_INADDR(), to read a network address register (e.g. GM_SRC_ADDR_1L)
4699 * GM_OUTADDR(), to write a network address register (e.g. GM_SRC_ADDR_2L)
4700- * GM_INHASH(), to read the GM_MC_ADDR_H1 register
4701- * GM_OUTHASH() to write the GM_MC_ADDR_H1 register
4702+ * GM_INHASH(), to read the hash registers (e.g. GM_MC_ADDR_H1..4)
4703+ * GM_OUTHASH() to write the hash registers (e.g. GM_MC_ADDR_H1..4)
4704 *
4705 * para:
4706 * Mac GMAC to access values: MAC_1 or MAC_2
4707@@ -1885,37 +2818,63 @@
4708 #define GMA(Mac, Reg) \
4709 ((BASE_GMAC_1 + (Mac) * (BASE_GMAC_2 - BASE_GMAC_1)) | (Reg))
4710
4711-#define GM_IN16(IoC, Mac, Reg, pVal) \
4712- SK_IN16((IoC), GMA((Mac), (Reg)), (pVal))
4713+#define GM_IN16(IoC, Mac, Reg, pVal) { \
4714+ SK_U8 Dummy; \
4715+ SK_ACQ_SPIN_LOCK(IoC); \
4716+ SK_IN16(IoC, GMA(Mac, Reg), pVal); \
4717+ SK_IN8(IoC, B0_RAP, &Dummy); \
4718+ SK_REL_SPIN_LOCK(IoC); \
4719+}
4720+
4721+#define GM_OUT16(IoC, Mac, Reg, Val) \
4722+ SK_OUT16(IoC, GMA(Mac, Reg), Val)
4723+
4724+#ifdef SK_LITTLE_ENDIAN
4725+
4726+#define GM_IN32(IoC, Mac, Reg, pVal) { \
4727+ SK_U8 Dummy; \
4728+ SK_ACQ_SPIN_LOCK(IoC); \
4729+ SK_IN16(IoC, GMA(Mac, Reg), (SK_U16 SK_FAR *)(pVal)); \
4730+ SK_IN16((IoC), GMA(Mac, (Reg) + 4), (SK_U16 SK_FAR *)(pVal) + 1); \
4731+ SK_IN8(IoC, B0_RAP, &Dummy); \
4732+ SK_REL_SPIN_LOCK(IoC); \
4733+}
4734
4735-#define GM_OUT16(IoC, Mac, Reg, Val) \
4736- SK_OUT16((IoC), GMA((Mac), (Reg)), (Val))
4737+#else /* !SK_LITTLE_ENDIAN */
4738
4739-#define GM_IN32(IoC, Mac, Reg, pVal) { \
4740- SK_IN16((IoC), GMA((Mac), (Reg)), \
4741- (SK_U16 SK_FAR*)&((SK_U16 SK_FAR*)(pVal))[XM_WORD_LO]); \
4742- SK_IN16((IoC), GMA((Mac), (Reg+4)), \
4743- (SK_U16 SK_FAR*)&((SK_U16 SK_FAR*)(pVal))[XM_WORD_HI]); \
4744+#define GM_IN32(IoC, Mac, Reg, pVal) { \
4745+ SK_U8 Dummy; \
4746+ SK_ACQ_SPIN_LOCK(IoC); \
4747+ SK_IN16(IoC, GMA(Mac, Reg), (SK_U16 SK_FAR *)(pVal) + 1); \
4748+ SK_IN16(IoC, GMA(Mac, (Reg) + 4), (SK_U16 SK_FAR *)(pVal)); \
4749+ SK_IN8(IoC, B0_RAP, &Dummy); \
4750+ SK_REL_SPIN_LOCK(IoC); \
4751 }
4752
4753+#endif /* !SK_LITTLE_ENDIAN */
4754+
4755 #define GM_OUT32(IoC, Mac, Reg, Val) { \
4756- SK_OUT16((IoC), GMA((Mac), (Reg)), (SK_U16)((Val) & 0xffffL)); \
4757- SK_OUT16((IoC), GMA((Mac), (Reg+4)), (SK_U16)(((Val) >> 16) & 0xffffL));\
4758+ SK_OUT16(IoC, GMA(Mac, Reg), (SK_U16)((Val) & 0xffffL)); \
4759+ SK_OUT16(IoC, GMA(Mac, (Reg) + 4), (SK_U16)(((Val) >> 16) & 0xffffL)); \
4760 }
4761
4762-#define GM_INADDR(IoC, Mac, Reg, pVal) { \
4763- SK_U16 Word; \
4764- SK_U8 *pByte; \
4765- pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \
4766- SK_IN16((IoC), GMA((Mac), (Reg)), &Word); \
4767- pByte[0] = (SK_U8)(Word & 0x00ff); \
4768- pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \
4769- SK_IN16((IoC), GMA((Mac), (Reg+4)), &Word); \
4770- pByte[2] = (SK_U8)(Word & 0x00ff); \
4771- pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \
4772- SK_IN16((IoC), GMA((Mac), (Reg+8)), &Word); \
4773- pByte[4] = (SK_U8)(Word & 0x00ff); \
4774- pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \
4775+#define GM_INADDR(IoC, Mac, Reg, pVal) { \
4776+ SK_U16 Word; \
4777+ SK_U8 Dummy; \
4778+ SK_U8 *pByte; \
4779+ pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \
4780+ SK_ACQ_SPIN_LOCK(IoC); \
4781+ SK_IN16((IoC), GMA((Mac), (Reg)), &Word); \
4782+ pByte[0] = (SK_U8)(Word & 0x00ff); \
4783+ pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \
4784+ SK_IN16((IoC), GMA((Mac), (Reg) + 4), &Word); \
4785+ pByte[2] = (SK_U8)(Word & 0x00ff); \
4786+ pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \
4787+ SK_IN16((IoC), GMA((Mac), (Reg) + 8), &Word); \
4788+ pByte[4] = (SK_U8)(Word & 0x00ff); \
4789+ pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \
4790+ SK_IN8(IoC, B0_RAP, &Dummy); \
4791+ SK_REL_SPIN_LOCK(IoC); \
4792 }
4793
4794 #define GM_OUTADDR(IoC, Mac, Reg, pVal) { \
4795@@ -1924,30 +2883,34 @@
4796 SK_OUT16((IoC), GMA((Mac), (Reg)), (SK_U16) \
4797 (((SK_U16)(pByte[0]) & 0x00ff) | \
4798 (((SK_U16)(pByte[1]) << 8) & 0xff00))); \
4799- SK_OUT16((IoC), GMA((Mac), (Reg+4)), (SK_U16) \
4800+ SK_OUT16((IoC), GMA((Mac), (Reg) + 4), (SK_U16) \
4801 (((SK_U16)(pByte[2]) & 0x00ff) | \
4802 (((SK_U16)(pByte[3]) << 8) & 0xff00))); \
4803- SK_OUT16((IoC), GMA((Mac), (Reg+8)), (SK_U16) \
4804+ SK_OUT16((IoC), GMA((Mac), (Reg) + 8), (SK_U16) \
4805 (((SK_U16)(pByte[4]) & 0x00ff) | \
4806 (((SK_U16)(pByte[5]) << 8) & 0xff00))); \
4807 }
4808
4809 #define GM_INHASH(IoC, Mac, Reg, pVal) { \
4810 SK_U16 Word; \
4811+ SK_U8 Dummy; \
4812 SK_U8 *pByte; \
4813 pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \
4814+ SK_ACQ_SPIN_LOCK(IoC); \
4815 SK_IN16((IoC), GMA((Mac), (Reg)), &Word); \
4816- pByte[0] = (SK_U8)(Word & 0x00ff); \
4817+ pByte[0] = (SK_U8)(Word & 0x00ff); \
4818 pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \
4819- SK_IN16((IoC), GMA((Mac), (Reg+4)), &Word); \
4820- pByte[2] = (SK_U8)(Word & 0x00ff); \
4821+ SK_IN16((IoC), GMA((Mac), (Reg) + 4), &Word); \
4822+ pByte[2] = (SK_U8)(Word & 0x00ff); \
4823 pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \
4824- SK_IN16((IoC), GMA((Mac), (Reg+8)), &Word); \
4825- pByte[4] = (SK_U8)(Word & 0x00ff); \
4826+ SK_IN16((IoC), GMA((Mac), (Reg) + 8), &Word); \
4827+ pByte[4] = (SK_U8)(Word & 0x00ff); \
4828 pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \
4829- SK_IN16((IoC), GMA((Mac), (Reg+12)), &Word); \
4830- pByte[6] = (SK_U8)(Word & 0x00ff); \
4831+ SK_IN16((IoC), GMA((Mac), (Reg) + 12), &Word); \
4832+ pByte[6] = (SK_U8)(Word & 0x00ff); \
4833 pByte[7] = (SK_U8)((Word >> 8) & 0x00ff); \
4834+ SK_IN8(IoC, B0_RAP, &Dummy); \
4835+ SK_REL_SPIN_LOCK(IoC); \
4836 }
4837
4838 #define GM_OUTHASH(IoC, Mac, Reg, pVal) { \
4839@@ -1956,13 +2919,13 @@
4840 SK_OUT16((IoC), GMA((Mac), (Reg)), (SK_U16) \
4841 (((SK_U16)(pByte[0]) & 0x00ff)| \
4842 (((SK_U16)(pByte[1]) << 8) & 0xff00))); \
4843- SK_OUT16((IoC), GMA((Mac), (Reg+4)), (SK_U16) \
4844+ SK_OUT16((IoC), GMA((Mac), (Reg) + 4), (SK_U16) \
4845 (((SK_U16)(pByte[2]) & 0x00ff)| \
4846 (((SK_U16)(pByte[3]) << 8) & 0xff00))); \
4847- SK_OUT16((IoC), GMA((Mac), (Reg+8)), (SK_U16) \
4848+ SK_OUT16((IoC), GMA((Mac), (Reg) + 8), (SK_U16) \
4849 (((SK_U16)(pByte[4]) & 0x00ff)| \
4850 (((SK_U16)(pByte[5]) << 8) & 0xff00))); \
4851- SK_OUT16((IoC), GMA((Mac), (Reg+12)), (SK_U16) \
4852+ SK_OUT16((IoC), GMA((Mac), (Reg) + 12), (SK_U16) \
4853 (((SK_U16)(pByte[6]) & 0x00ff)| \
4854 (((SK_U16)(pByte[7]) << 8) & 0xff00))); \
4855 }
4856@@ -1980,8 +2943,8 @@
4857 #define SK_PHY_BCOM 1 /* Broadcom BCM5400 */
4858 #define SK_PHY_LONE 2 /* Level One LXT1000 */
4859 #define SK_PHY_NAT 3 /* National DP83891 */
4860-#define SK_PHY_MARV_COPPER 4 /* Marvell 88E1011S */
4861-#define SK_PHY_MARV_FIBER 5 /* Marvell 88E1011S working on fiber */
4862+#define SK_PHY_MARV_COPPER 4 /* Marvell 88E1040S */
4863+#define SK_PHY_MARV_FIBER 5 /* Marvell 88E1040S working on fiber */
4864
4865 /*
4866 * PHY addresses (bits 12..8 of PHY address reg)
4867@@ -2010,30 +2973,30 @@
4868 *
4869 * usage: PHY_READ(IoC, pPort, MAC_1, PHY_CTRL, Value);
4870 * Warning: a PHY_READ on an uninitialized PHY (PHY still in reset) never
4871- * comes back. This is checked in DEBUG mode.
4872+ * comes back. This is checked in DEBUG mode.
4873 */
4874 #ifndef DEBUG
4875 #define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) { \
4876- SK_U16 Mmu; \
4877+ SK_U16 Mmu; \
4878 \
4879 XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \
4880 XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
4881 if ((pPort)->PhyType != SK_PHY_XMAC) { \
4882- do { \
4883+ do { \
4884 XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
4885 } while ((Mmu & XM_MMU_PHY_RDY) == 0); \
4886 XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
4887- } \
4888+ } \
4889 }
4890 #else
4891 #define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) { \
4892- SK_U16 Mmu; \
4893+ SK_U16 Mmu; \
4894 int __i = 0; \
4895 \
4896 XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \
4897 XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
4898 if ((pPort)->PhyType != SK_PHY_XMAC) { \
4899- do { \
4900+ do { \
4901 XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
4902 __i++; \
4903 if (__i > 100000) { \
4904@@ -2044,7 +3007,7 @@
4905 } \
4906 } while ((Mmu & XM_MMU_PHY_RDY) == 0); \
4907 XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
4908- } \
4909+ } \
4910 }
4911 #endif /* DEBUG */
4912
4913@@ -2052,17 +3015,17 @@
4914 SK_U16 Mmu; \
4915 \
4916 if ((pPort)->PhyType != SK_PHY_XMAC) { \
4917- do { \
4918+ do { \
4919 XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
4920 } while ((Mmu & XM_MMU_PHY_BUSY) != 0); \
4921- } \
4922+ } \
4923 XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \
4924 XM_OUT16((IoC), (Mac), XM_PHY_DATA, (Val)); \
4925 if ((pPort)->PhyType != SK_PHY_XMAC) { \
4926- do { \
4927+ do { \
4928 XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
4929 } while ((Mmu & XM_MMU_PHY_BUSY) != 0); \
4930- } \
4931+ } \
4932 }
4933
4934 /*
4935@@ -2071,12 +3034,14 @@
4936 * Use this macro to access PCI config register from the I/O space.
4937 *
4938 * para:
4939+ * pAC Pointer to adapter context
4940 * Addr PCI configuration register to access.
4941 * Values: PCI_VENDOR_ID ... PCI_VPD_ADR_REG,
4942 *
4943- * usage SK_IN16(pAC, PCI_C(PCI_VENDOR_ID), pVal);
4944+ * usage SK_IN16(IoC, PCI_C(pAC, PCI_VENDOR_ID), pVal);
4945 */
4946-#define PCI_C(Addr) (B7_CFG_SPC + (Addr)) /* PCI Config Space */
4947+#define PCI_C(p, Addr) \
4948+ (((CHIP_ID_YUKON_2(p)) ? Y2_CFG_SPC : B7_CFG_SPC) + (Addr))
4949
4950 /*
4951 * Macro SK_HW_ADDR(Base, Addr)
4952@@ -2088,7 +3053,7 @@
4953 * Addr Address offset
4954 *
4955 * usage: May be used in SK_INxx and SK_OUTxx macros
4956- * #define SK_IN8(pAC, Addr, pVal) ...\
4957+ * #define SK_IN8(IoC, Addr, pVal) ...\
4958 * *pVal = (SK_U8)inp(SK_HW_ADDR(pAC->Hw.Iop, Addr)))
4959 */
4960 #ifdef SK_MEM_MAPPED_IO
4961@@ -2107,20 +3072,31 @@
4962 * para:
4963 * pAC Pointer to adapter context struct
4964 * IoC I/O context needed for SK I/O macros
4965- * Port Port number
4966+ * Port Port number
4967 * Mode Mode to set for this LED
4968 */
4969 #define SK_HWAC_LINK_LED(pAC, IoC, Port, Mode) \
4970 SK_OUT8(IoC, MR_ADDR(Port, LNK_LED_REG), Mode);
4971
4972+#define SK_SET_GP_IO(IoC, Bit) { \
4973+ SK_U32 DWord; \
4974+ SK_IN32(IoC, B2_GP_IO, &DWord); \
4975+ DWord |= ((GP_DIR_0 | GP_IO_0) << (Bit));\
4976+ SK_OUT32(IoC, B2_GP_IO, DWord); \
4977+}
4978
4979-/* typedefs *******************************************************************/
4980-
4981+#define SK_CLR_GP_IO(IoC, Bit) { \
4982+ SK_U32 DWord; \
4983+ SK_IN32(IoC, B2_GP_IO, &DWord); \
4984+ DWord &= ~((GP_DIR_0 | GP_IO_0) << (Bit));\
4985+ SK_OUT32(IoC, B2_GP_IO, DWord); \
4986+}
4987
4988-/* function prototypes ********************************************************/
4989+#define SK_GE_PCI_FIFO_SIZE 1600 /* PCI FIFO Size */
4990
4991 #ifdef __cplusplus
4992 }
4993 #endif /* __cplusplus */
4994
4995 #endif /* __INC_SKGEHW_H */
4996+
4997diff -ruN linux/drivers/net/sk98lin/h/skgehwt.h linux-new/drivers/net/sk98lin/h/skgehwt.h
4998--- linux/drivers/net/sk98lin/h/skgehwt.h 2007-01-02 23:21:17.000000000 +0100
4999+++ linux-new/drivers/net/sk98lin/h/skgehwt.h 2006-10-13 11:18:49.000000000 +0200
5000@@ -2,14 +2,15 @@
5001 *
5002 * Name: skhwt.h
5003 * Project: Gigabit Ethernet Adapters, Event Scheduler Module
5004- * Version: $Revision$
5005- * Date: $Date$
5006+ * Version: $Revision$
5007+ * Date: $Date$
5008 * Purpose: Defines for the hardware timer functions
5009 *
5010 ******************************************************************************/
5011
5012 /******************************************************************************
5013 *
5014+ * LICENSE:
5015 * (C)Copyright 1998-2002 SysKonnect GmbH.
5016 * (C)Copyright 2002-2003 Marvell.
5017 *
5018@@ -19,6 +20,7 @@
5019 * (at your option) any later version.
5020 *
5021 * The information in this file is provided "AS IS" without warranty.
5022+ * /LICENSE
5023 *
5024 ******************************************************************************/
5025
5026diff -ruN linux/drivers/net/sk98lin/h/skgei2c.h linux-new/drivers/net/sk98lin/h/skgei2c.h
5027--- linux/drivers/net/sk98lin/h/skgei2c.h 2007-01-02 23:21:17.000000000 +0100
5028+++ linux-new/drivers/net/sk98lin/h/skgei2c.h 1970-01-01 01:00:00.000000000 +0100
5029@@ -1,210 +0,0 @@
5030-/******************************************************************************
5031- *
5032- * Name: skgei2c.h
5033- * Project: Gigabit Ethernet Adapters, TWSI-Module
5034- * Version: $Revision$
5035- * Date: $Date$
5036- * Purpose: Special defines for TWSI
5037- *
5038- ******************************************************************************/
5039-
5040-/******************************************************************************
5041- *
5042- * (C)Copyright 1998-2002 SysKonnect.
5043- * (C)Copyright 2002-2003 Marvell.
5044- *
5045- * This program is free software; you can redistribute it and/or modify
5046- * it under the terms of the GNU General Public License as published by
5047- * the Free Software Foundation; either version 2 of the License, or
5048- * (at your option) any later version.
5049- *
5050- * The information in this file is provided "AS IS" without warranty.
5051- *
5052- ******************************************************************************/
5053-
5054-/*
5055- * SKGEI2C.H contains all SK-98xx specific defines for the TWSI handling
5056- */
5057-
5058-#ifndef _INC_SKGEI2C_H_
5059-#define _INC_SKGEI2C_H_
5060-
5061-/*
5062- * Macros to access the B2_I2C_CTRL
5063- */
5064-#define SK_I2C_CTL(IoC, flag, dev, dev_size, reg, burst) \
5065- SK_OUT32(IoC, B2_I2C_CTRL,\
5066- (flag ? 0x80000000UL : 0x0L) | \
5067- (((SK_U32)reg << 16) & I2C_ADDR) | \
5068- (((SK_U32)dev << 9) & I2C_DEV_SEL) | \
5069- (dev_size & I2C_DEV_SIZE) | \
5070- ((burst << 4) & I2C_BURST_LEN))
5071-
5072-#define SK_I2C_STOP(IoC) { \
5073- SK_U32 I2cCtrl; \
5074- SK_IN32(IoC, B2_I2C_CTRL, &I2cCtrl); \
5075- SK_OUT32(IoC, B2_I2C_CTRL, I2cCtrl | I2C_STOP); \
5076-}
5077-
5078-#define SK_I2C_GET_CTL(IoC, pI2cCtrl) SK_IN32(IoC, B2_I2C_CTRL, pI2cCtrl)
5079-
5080-/*
5081- * Macros to access the TWSI SW Registers
5082- */
5083-#define SK_I2C_SET_BIT(IoC, SetBits) { \
5084- SK_U8 OrgBits; \
5085- SK_IN8(IoC, B2_I2C_SW, &OrgBits); \
5086- SK_OUT8(IoC, B2_I2C_SW, OrgBits | (SK_U8)(SetBits)); \
5087-}
5088-
5089-#define SK_I2C_CLR_BIT(IoC, ClrBits) { \
5090- SK_U8 OrgBits; \
5091- SK_IN8(IoC, B2_I2C_SW, &OrgBits); \
5092- SK_OUT8(IoC, B2_I2C_SW, OrgBits & ~((SK_U8)(ClrBits))); \
5093-}
5094-
5095-#define SK_I2C_GET_SW(IoC, pI2cSw) SK_IN8(IoC, B2_I2C_SW, pI2cSw)
5096-
5097-/*
5098- * define the possible sensor states
5099- */
5100-#define SK_SEN_IDLE 0 /* Idle: sensor not read */
5101-#define SK_SEN_VALUE 1 /* Value Read cycle */
5102-#define SK_SEN_VALEXT 2 /* Extended Value Read cycle */
5103-
5104-/*
5105- * Conversion factor to convert read Voltage sensor to milli Volt
5106- * Conversion factor to convert read Temperature sensor to 10th degree Celsius
5107- */
5108-#define SK_LM80_VT_LSB 22 /* 22mV LSB resolution */
5109-#define SK_LM80_TEMP_LSB 10 /* 1 degree LSB resolution */
5110-#define SK_LM80_TEMPEXT_LSB 5 /* 0.5 degree LSB resolution for ext. val. */
5111-
5112-/*
5113- * formula: counter = (22500*60)/(rpm * divisor * pulses/2)
5114- * assuming: 6500rpm, 4 pulses, divisor 1
5115- */
5116-#define SK_LM80_FAN_FAKTOR ((22500L*60)/(1*2))
5117-
5118-/*
5119- * Define sensor management data
5120- * Maximum is reached on Genesis copper dual port and Yukon-64
5121- * Board specific maximum is in pAC->I2c.MaxSens
5122- */
5123-#define SK_MAX_SENSORS 8 /* maximal no. of installed sensors */
5124-#define SK_MIN_SENSORS 5 /* minimal no. of installed sensors */
5125-
5126-/*
5127- * To watch the state machine (SM) use the timer in two ways
5128- * instead of one as hitherto
5129- */
5130-#define SK_TIMER_WATCH_SM 0 /* Watch the SM to finish in a spec. time */
5131-#define SK_TIMER_NEW_GAUGING 1 /* Start a new gauging when timer expires */
5132-
5133-/*
5134- * Defines for the individual thresholds
5135- */
5136-
5137-/* Temperature sensor */
5138-#define SK_SEN_TEMP_HIGH_ERR 800 /* Temperature High Err Threshold */
5139-#define SK_SEN_TEMP_HIGH_WARN 700 /* Temperature High Warn Threshold */
5140-#define SK_SEN_TEMP_LOW_WARN 100 /* Temperature Low Warn Threshold */
5141-#define SK_SEN_TEMP_LOW_ERR 0 /* Temperature Low Err Threshold */
5142-
5143-/* VCC which should be 5 V */
5144-#define SK_SEN_PCI_5V_HIGH_ERR 5588 /* Voltage PCI High Err Threshold */
5145-#define SK_SEN_PCI_5V_HIGH_WARN 5346 /* Voltage PCI High Warn Threshold */
5146-#define SK_SEN_PCI_5V_LOW_WARN 4664 /* Voltage PCI Low Warn Threshold */
5147-#define SK_SEN_PCI_5V_LOW_ERR 4422 /* Voltage PCI Low Err Threshold */
5148-
5149-/*
5150- * VIO may be 5 V or 3.3 V. Initialization takes two parts:
5151- * 1. Initialize lowest lower limit and highest higher limit.
5152- * 2. After the first value is read correct the upper or the lower limit to
5153- * the appropriate C constant.
5154- *
5155- * Warning limits are +-5% of the exepected voltage.
5156- * Error limits are +-10% of the expected voltage.
5157- */
5158-
5159-/* Bug fix AF: 16.Aug.2001: Correct the init base of LM80 sensor */
5160-
5161-#define SK_SEN_PCI_IO_5V_HIGH_ERR 5566 /* + 10% V PCI-IO High Err Threshold */
5162-#define SK_SEN_PCI_IO_5V_HIGH_WARN 5324 /* + 5% V PCI-IO High Warn Threshold */
5163- /* 5000 mVolt */
5164-#define SK_SEN_PCI_IO_5V_LOW_WARN 4686 /* - 5% V PCI-IO Low Warn Threshold */
5165-#define SK_SEN_PCI_IO_5V_LOW_ERR 4444 /* - 10% V PCI-IO Low Err Threshold */
5166-
5167-#define SK_SEN_PCI_IO_RANGE_LIMITER 4000 /* 4000 mV range delimiter */
5168-
5169-/* correction values for the second pass */
5170-#define SK_SEN_PCI_IO_3V3_HIGH_ERR 3850 /* + 15% V PCI-IO High Err Threshold */
5171-#define SK_SEN_PCI_IO_3V3_HIGH_WARN 3674 /* + 10% V PCI-IO High Warn Threshold */
5172- /* 3300 mVolt */
5173-#define SK_SEN_PCI_IO_3V3_LOW_WARN 2926 /* - 10% V PCI-IO Low Warn Threshold */
5174-#define SK_SEN_PCI_IO_3V3_LOW_ERR 2772 /* - 15% V PCI-IO Low Err Threshold */
5175-
5176-/*
5177- * VDD voltage
5178- */
5179-#define SK_SEN_VDD_HIGH_ERR 3630 /* Voltage ASIC High Err Threshold */
5180-#define SK_SEN_VDD_HIGH_WARN 3476 /* Voltage ASIC High Warn Threshold */
5181-#define SK_SEN_VDD_LOW_WARN 3146 /* Voltage ASIC Low Warn Threshold */
5182-#define SK_SEN_VDD_LOW_ERR 2970 /* Voltage ASIC Low Err Threshold */
5183-
5184-/*
5185- * PHY PLL 3V3 voltage
5186- */
5187-#define SK_SEN_PLL_3V3_HIGH_ERR 3630 /* Voltage PMA High Err Threshold */
5188-#define SK_SEN_PLL_3V3_HIGH_WARN 3476 /* Voltage PMA High Warn Threshold */
5189-#define SK_SEN_PLL_3V3_LOW_WARN 3146 /* Voltage PMA Low Warn Threshold */
5190-#define SK_SEN_PLL_3V3_LOW_ERR 2970 /* Voltage PMA Low Err Threshold */
5191-
5192-/*
5193- * VAUX (YUKON only)
5194- */
5195-#define SK_SEN_VAUX_3V3_HIGH_ERR 3630 /* Voltage VAUX High Err Threshold */
5196-#define SK_SEN_VAUX_3V3_HIGH_WARN 3476 /* Voltage VAUX High Warn Threshold */
5197-#define SK_SEN_VAUX_3V3_LOW_WARN 3146 /* Voltage VAUX Low Warn Threshold */
5198-#define SK_SEN_VAUX_3V3_LOW_ERR 2970 /* Voltage VAUX Low Err Threshold */
5199-#define SK_SEN_VAUX_0V_WARN_ERR 0 /* if VAUX not present */
5200-#define SK_SEN_VAUX_RANGE_LIMITER 1000 /* 1000 mV range delimiter */
5201-
5202-/*
5203- * PHY 2V5 voltage
5204- */
5205-#define SK_SEN_PHY_2V5_HIGH_ERR 2750 /* Voltage PHY High Err Threshold */
5206-#define SK_SEN_PHY_2V5_HIGH_WARN 2640 /* Voltage PHY High Warn Threshold */
5207-#define SK_SEN_PHY_2V5_LOW_WARN 2376 /* Voltage PHY Low Warn Threshold */
5208-#define SK_SEN_PHY_2V5_LOW_ERR 2222 /* Voltage PHY Low Err Threshold */
5209-
5210-/*
5211- * ASIC Core 1V5 voltage (YUKON only)
5212- */
5213-#define SK_SEN_CORE_1V5_HIGH_ERR 1650 /* Voltage ASIC Core High Err Threshold */
5214-#define SK_SEN_CORE_1V5_HIGH_WARN 1575 /* Voltage ASIC Core High Warn Threshold */
5215-#define SK_SEN_CORE_1V5_LOW_WARN 1425 /* Voltage ASIC Core Low Warn Threshold */
5216-#define SK_SEN_CORE_1V5_LOW_ERR 1350 /* Voltage ASIC Core Low Err Threshold */
5217-
5218-/*
5219- * FAN 1 speed
5220- */
5221-/* assuming: 6500rpm +-15%, 4 pulses,
5222- * warning at: 80 %
5223- * error at: 70 %
5224- * no upper limit
5225- */
5226-#define SK_SEN_FAN_HIGH_ERR 20000 /* FAN Speed High Err Threshold */
5227-#define SK_SEN_FAN_HIGH_WARN 20000 /* FAN Speed High Warn Threshold */
5228-#define SK_SEN_FAN_LOW_WARN 5200 /* FAN Speed Low Warn Threshold */
5229-#define SK_SEN_FAN_LOW_ERR 4550 /* FAN Speed Low Err Threshold */
5230-
5231-/*
5232- * Some Voltages need dynamic thresholds
5233- */
5234-#define SK_SEN_DYN_INIT_NONE 0 /* No dynamic init of thresholds */
5235-#define SK_SEN_DYN_INIT_PCI_IO 10 /* Init PCI-IO with new thresholds */
5236-#define SK_SEN_DYN_INIT_VAUX 11 /* Init VAUX with new thresholds */
5237-
5238-extern int SkLm80ReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen);
5239-#endif /* n_INC_SKGEI2C_H */
5240diff -ruN linux/drivers/net/sk98lin/h/skgeinit.h linux-new/drivers/net/sk98lin/h/skgeinit.h
5241--- linux/drivers/net/sk98lin/h/skgeinit.h 2007-01-02 23:21:17.000000000 +0100
5242+++ linux-new/drivers/net/sk98lin/h/skgeinit.h 2006-10-13 11:18:49.000000000 +0200
5243@@ -2,23 +2,24 @@
5244 *
5245 * Name: skgeinit.h
5246 * Project: Gigabit Ethernet Adapters, Common Modules
5247- * Version: $Revision$
5248- * Date: $Date$
5249+ * Version: $Revision$
5250+ * Date: $Date$
5251 * Purpose: Structures and prototypes for the GE Init Module
5252 *
5253 ******************************************************************************/
5254
5255 /******************************************************************************
5256 *
5257+ * LICENSE:
5258 * (C)Copyright 1998-2002 SysKonnect.
5259- * (C)Copyright 2002-2003 Marvell.
5260+ * (C)Copyright 2002-2006 Marvell.
5261 *
5262 * This program is free software; you can redistribute it and/or modify
5263 * it under the terms of the GNU General Public License as published by
5264 * the Free Software Foundation; either version 2 of the License, or
5265 * (at your option) any later version.
5266- *
5267 * The information in this file is provided "AS IS" without warranty.
5268+ * /LICENSE
5269 *
5270 ******************************************************************************/
5271
5272@@ -60,14 +61,17 @@
5273 #define SK_XMIT_DUR 0x002faf08UL /* 50 ms */
5274 #define SK_BLK_DUR 0x01dcd650UL /* 500 ms */
5275
5276-#define SK_DPOLL_DEF 0x00ee6b28UL /* 250 ms at 62.5 MHz */
5277+#define SK_DPOLL_DEF 0x00ee6b28UL /* 250 ms at 62.5 MHz (Genesis) */
5278+#define SK_DPOLL_DEF_Y2 0x0000124fUL /* 75 us (Yukon-2) */
5279
5280 #define SK_DPOLL_MAX 0x00ffffffUL /* 268 ms at 62.5 MHz */
5281- /* 215 ms at 78.12 MHz */
5282+ /* 215 ms at 78.12 MHz (Yukon) */
5283
5284 #define SK_FACT_62 100 /* is given in percent */
5285-#define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */
5286+#define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */
5287 #define SK_FACT_78 125 /* on YUKON: 78.12 MHz */
5288+#define SK_FACT_100 161 /* on YUKON-FE: 100 MHz */
5289+#define SK_FACT_125 202 /* on YUKON-EC: 125 MHz */
5290
5291 /* Timeout values */
5292 #define SK_MAC_TO_53 72 /* MAC arbiter timeout */
5293@@ -82,11 +86,23 @@
5294 #define SK_RB_LLPP_S (10 * 1024) /* Lower Level for small Queues */
5295 #define SK_RB_LLPP_B (16 * 1024) /* Lower Level for big Queues */
5296
5297+/* Threshold values for Yukon-EC Ultra */
5298+#define SK_ECU_ULPP 0x0080 /* Upper Pause Threshold (multiples of 8) */
5299+#define SK_ECU_LLPP 0x0060 /* Lower Pause Threshold (multiples of 8) */
5300+#define SK_ECU_AE_THR 0x0180 /* Almost Empty Threshold */
5301+#define SK_ECU_TXFF_LEV 0x01a0 /* Tx BMU FIFO Level */
5302+
5303 #ifndef SK_BMU_RX_WM
5304-#define SK_BMU_RX_WM 0x600 /* BMU Rx Watermark */
5305+#define SK_BMU_RX_WM 0x600 /* BMU Rx Watermark */
5306 #endif
5307+
5308 #ifndef SK_BMU_TX_WM
5309-#define SK_BMU_TX_WM 0x600 /* BMU Tx Watermark */
5310+#define SK_BMU_TX_WM 0x600 /* BMU Tx Watermark */
5311+#endif
5312+
5313+/* performance sensitive drivers should set this define to 0x80 */
5314+#ifndef SK_BMU_RX_WM_PEX
5315+#define SK_BMU_RX_WM_PEX 0x600 /* BMU Rx Watermark for PEX */
5316 #endif
5317
5318 /* XMAC II Rx High Watermark */
5319@@ -98,37 +114,31 @@
5320 #define SK_XM_THR_MULL 0x01fb /* .. for multiple link usage */
5321 #define SK_XM_THR_JUMBO 0x03fc /* .. for jumbo frame usage */
5322
5323-/* values for GIPortUsage */
5324+/* values for PortUsage */
5325 #define SK_RED_LINK 1 /* redundant link usage */
5326 #define SK_MUL_LINK 2 /* multiple link usage */
5327 #define SK_JUMBO_LINK 3 /* driver uses jumbo frames */
5328
5329 /* Minimum RAM Buffer Rx Queue Size */
5330-#define SK_MIN_RXQ_SIZE 16 /* 16 kB */
5331+#define SK_MIN_RXQ_SIZE (((pAC)->GIni.GIYukon2) ? 10 : 16) /* 10/16 kB */
5332
5333 /* Minimum RAM Buffer Tx Queue Size */
5334-#define SK_MIN_TXQ_SIZE 16 /* 16 kB */
5335+#define SK_MIN_TXQ_SIZE (((pAC)->GIni.GIYukon2) ? 10 : 16) /* 10/16 kB */
5336
5337-/* Queue Size units */
5338-#define QZ_UNITS 0x7
5339+/* Queue Size units (Genesis/Yukon) */
5340+#define QZ_UNITS 7
5341 #define QZ_STEP 8
5342
5343+/* Queue Size units (Yukon-2) */
5344+#define QZ_STEP_Y2 1
5345+
5346 /* Percentage of queue size from whole memory */
5347 /* 80 % for receive */
5348-#define RAM_QUOTA_RX 80L
5349-/* 0% for sync transfer */
5350-#define RAM_QUOTA_SYNC 0L
5351+#define RAM_QUOTA_RX 80
5352+/* 0 % for sync transfer */
5353+#define RAM_QUOTA_SYNC 0
5354 /* the rest (20%) is taken for async transfer */
5355
5356-/* Get the rounded queue size in Bytes in 8k steps */
5357-#define ROUND_QUEUE_SIZE(SizeInBytes) \
5358- ((((unsigned long) (SizeInBytes) + (QZ_STEP*1024L)-1) / 1024) & \
5359- ~(QZ_STEP-1))
5360-
5361-/* Get the rounded queue size in KBytes in 8k steps */
5362-#define ROUND_QUEUE_SIZE_KB(Kilobytes) \
5363- ROUND_QUEUE_SIZE((Kilobytes) * 1024L)
5364-
5365 /* Types of RAM Buffer Queues */
5366 #define SK_RX_SRAM_Q 1 /* small receive queue */
5367 #define SK_RX_BRAM_Q 2 /* big receive queue */
5368@@ -167,11 +177,11 @@
5369
5370
5371 /* Link Speed Capabilities */
5372-#define SK_LSPEED_CAP_AUTO (1<<0) /* Automatic resolution */
5373-#define SK_LSPEED_CAP_10MBPS (1<<1) /* 10 Mbps */
5374-#define SK_LSPEED_CAP_100MBPS (1<<2) /* 100 Mbps */
5375-#define SK_LSPEED_CAP_1000MBPS (1<<3) /* 1000 Mbps */
5376-#define SK_LSPEED_CAP_INDETERMINATED (1<<4) /* indeterminated */
5377+#define SK_LSPEED_CAP_AUTO BIT_0S /* Automatic resolution */
5378+#define SK_LSPEED_CAP_10MBPS BIT_1S /* 10 Mbps */
5379+#define SK_LSPEED_CAP_100MBPS BIT_2S /* 100 Mbps */
5380+#define SK_LSPEED_CAP_1000MBPS BIT_3S /* 1000 Mbps */
5381+#define SK_LSPEED_CAP_INDETERMINATED BIT_4S /* indeterminated */
5382
5383 /* Link Speed Parameter */
5384 #define SK_LSPEED_AUTO 1 /* Automatic resolution */
5385@@ -189,11 +199,11 @@
5386
5387
5388 /* Link Capability Parameter */
5389-#define SK_LMODE_CAP_HALF (1<<0) /* Half Duplex Mode */
5390-#define SK_LMODE_CAP_FULL (1<<1) /* Full Duplex Mode */
5391-#define SK_LMODE_CAP_AUTOHALF (1<<2) /* AutoHalf Duplex Mode */
5392-#define SK_LMODE_CAP_AUTOFULL (1<<3) /* AutoFull Duplex Mode */
5393-#define SK_LMODE_CAP_INDETERMINATED (1<<4) /* indeterminated */
5394+#define SK_LMODE_CAP_HALF BIT_0S /* Half Duplex Mode */
5395+#define SK_LMODE_CAP_FULL BIT_1S /* Full Duplex Mode */
5396+#define SK_LMODE_CAP_AUTOHALF BIT_2S /* AutoHalf Duplex Mode */
5397+#define SK_LMODE_CAP_AUTOFULL BIT_3S /* AutoFull Duplex Mode */
5398+#define SK_LMODE_CAP_INDETERMINATED BIT_4S /* indeterminated */
5399
5400 /* Link Mode Current State */
5401 #define SK_LMODE_STAT_UNKNOWN 1 /* Unknown Duplex Mode */
5402@@ -204,7 +214,7 @@
5403 #define SK_LMODE_STAT_INDETERMINATED 6 /* indeterminated */
5404
5405 /* Flow Control Mode Parameter (and capabilities) */
5406-#define SK_FLOW_MODE_NONE 1 /* No Flow-Control */
5407+#define SK_FLOW_MODE_NONE 1 /* No Flow Control */
5408 #define SK_FLOW_MODE_LOC_SEND 2 /* Local station sends PAUSE */
5409 #define SK_FLOW_MODE_SYMMETRIC 3 /* Both stations may send PAUSE */
5410 #define SK_FLOW_MODE_SYM_OR_REM 4 /* Both stations may send PAUSE or
5411@@ -220,10 +230,10 @@
5412 #define SK_FLOW_STAT_INDETERMINATED 5 /* indeterminated */
5413
5414 /* Master/Slave Mode Capabilities */
5415-#define SK_MS_CAP_AUTO (1<<0) /* Automatic resolution */
5416-#define SK_MS_CAP_MASTER (1<<1) /* This station is master */
5417-#define SK_MS_CAP_SLAVE (1<<2) /* This station is slave */
5418-#define SK_MS_CAP_INDETERMINATED (1<<3) /* indeterminated */
5419+#define SK_MS_CAP_AUTO BIT_0S /* Automatic resolution */
5420+#define SK_MS_CAP_MASTER BIT_1S /* This station is master */
5421+#define SK_MS_CAP_SLAVE BIT_2S /* This station is slave */
5422+#define SK_MS_CAP_INDETERMINATED BIT_3S /* indeterminated */
5423
5424 /* Set Master/Slave Mode Parameter (and capabilities) */
5425 #define SK_MS_MODE_AUTO 1 /* Automatic resolution */
5426@@ -238,25 +248,25 @@
5427 #define SK_MS_STAT_FAULT 4 /* M/S resolution failed */
5428 #define SK_MS_STAT_INDETERMINATED 5 /* indeterminated */
5429
5430-/* parameter 'Mode' when calling SkXmSetRxCmd() */
5431-#define SK_STRIP_FCS_ON (1<<0) /* Enable FCS stripping of Rx frames */
5432-#define SK_STRIP_FCS_OFF (1<<1) /* Disable FCS stripping of Rx frames */
5433-#define SK_STRIP_PAD_ON (1<<2) /* Enable pad byte stripping of Rx fr */
5434-#define SK_STRIP_PAD_OFF (1<<3) /* Disable pad byte stripping of Rx fr */
5435-#define SK_LENERR_OK_ON (1<<4) /* Don't chk fr for in range len error */
5436-#define SK_LENERR_OK_OFF (1<<5) /* Check frames for in range len error */
5437-#define SK_BIG_PK_OK_ON (1<<6) /* Don't set Rx Error bit for big frames */
5438-#define SK_BIG_PK_OK_OFF (1<<7) /* Set Rx Error bit for big frames */
5439-#define SK_SELF_RX_ON (1<<8) /* Enable Rx of own packets */
5440-#define SK_SELF_RX_OFF (1<<9) /* Disable Rx of own packets */
5441+/* parameter 'Mode' when calling SkMacSetRxCmd() */
5442+#define SK_STRIP_FCS_ON BIT_0S /* Enable FCS stripping of Rx frames */
5443+#define SK_STRIP_FCS_OFF BIT_1S /* Disable FCS stripping of Rx frames */
5444+#define SK_STRIP_PAD_ON BIT_2S /* Enable pad byte stripping of Rx fr */
5445+#define SK_STRIP_PAD_OFF BIT_3S /* Disable pad byte stripping of Rx fr */
5446+#define SK_LENERR_OK_ON BIT_4S /* Don't chk fr for in range len error */
5447+#define SK_LENERR_OK_OFF BIT_5S /* Check frames for in range len error */
5448+#define SK_BIG_PK_OK_ON BIT_6S /* Don't set Rx Error bit for big frames */
5449+#define SK_BIG_PK_OK_OFF BIT_7S /* Set Rx Error bit for big frames */
5450+#define SK_SELF_RX_ON BIT_8S /* Enable Rx of own packets */
5451+#define SK_SELF_RX_OFF BIT_9S /* Disable Rx of own packets */
5452
5453 /* parameter 'Para' when calling SkMacSetRxTxEn() */
5454-#define SK_MAC_LOOPB_ON (1<<0) /* Enable MAC Loopback Mode */
5455-#define SK_MAC_LOOPB_OFF (1<<1) /* Disable MAC Loopback Mode */
5456-#define SK_PHY_LOOPB_ON (1<<2) /* Enable PHY Loopback Mode */
5457-#define SK_PHY_LOOPB_OFF (1<<3) /* Disable PHY Loopback Mode */
5458-#define SK_PHY_FULLD_ON (1<<4) /* Enable GMII Full Duplex */
5459-#define SK_PHY_FULLD_OFF (1<<5) /* Disable GMII Full Duplex */
5460+#define SK_MAC_LOOPB_ON BIT_0S /* Enable MAC Loopback Mode */
5461+#define SK_MAC_LOOPB_OFF BIT_1S /* Disable MAC Loopback Mode */
5462+#define SK_PHY_LOOPB_ON BIT_2S /* Enable PHY Loopback Mode */
5463+#define SK_PHY_LOOPB_OFF BIT_3S /* Disable PHY Loopback Mode */
5464+#define SK_PHY_FULLD_ON BIT_4S /* Enable GMII Full Duplex */
5465+#define SK_PHY_FULLD_OFF BIT_5S /* Disable GMII Full Duplex */
5466
5467 /* States of PState */
5468 #define SK_PRT_RESET 0 /* the port is reset */
5469@@ -266,18 +276,25 @@
5470
5471 /* PHY power down modes */
5472 #define PHY_PM_OPERATIONAL_MODE 0 /* PHY operational mode */
5473-#define PHY_PM_DEEP_SLEEP 1 /* coma mode --> minimal power */
5474+#define PHY_PM_DEEP_SLEEP 1 /* Coma mode --> minimal power */
5475 #define PHY_PM_IEEE_POWER_DOWN 2 /* IEEE 22.2.4.1.5 compl. power down */
5476-#define PHY_PM_ENERGY_DETECT 3 /* energy detect */
5477-#define PHY_PM_ENERGY_DETECT_PLUS 4 /* energy detect plus */
5478+#define PHY_PM_ENERGY_DETECT 3 /* Energy detect */
5479+#define PHY_PM_ENERGY_DETECT_PLUS 4 /* Energy detect plus */
5480+
5481+/* PCI Bus Types */
5482+#define SK_PCI_BUS BIT_0S /* normal PCI bus */
5483+#define SK_PCIX_BUS BIT_1S /* PCI-X bus */
5484+#define SK_PEX_BUS BIT_2S /* PCI-Express bus */
5485
5486 /* Default receive frame limit for Workaround of XMAC Errata */
5487 #define SK_DEF_RX_WA_LIM SK_CONSTU64(100)
5488
5489 /* values for GILedBlinkCtrl (LED Blink Control) */
5490-#define SK_ACT_LED_BLINK (1<<0) /* Active LED blinking */
5491-#define SK_DUP_LED_NORMAL (1<<1) /* Duplex LED normal */
5492-#define SK_LED_LINK100_ON (1<<2) /* Link 100M LED on */
5493+#define SK_ACT_LED_BLINK BIT_0S /* Active LED blinking */
5494+#define SK_DUP_LED_NORMAL BIT_1S /* Duplex LED normal */
5495+#define SK_LED_LINK100_ON BIT_2S /* Link 100M LED on */
5496+#define SK_DUAL_LED_ACT_LNK BIT_3S /* Dual LED ACT/LNK configuration */
5497+#define SK_LED_LINK_MUX_P60 BIT_4S /* Link LED muxed to pin 60 */
5498
5499 /* Link Partner Status */
5500 #define SK_LIPA_UNKNOWN 0 /* Link partner is in unknown state */
5501@@ -290,18 +307,189 @@
5502 /* Max. Auto-neg. timeouts before link detection in sense mode is reset */
5503 #define SK_MAX_ANEG_TO 10 /* Max. 10 times the sense mode is reset */
5504
5505+
5506+/******************************************************************************
5507+ *
5508+ * HW_FEATURE() macro
5509+ */
5510+
5511+/* DWORD 0: Features */
5512+#define HWF_FORCE_AUTO_NEG 0x04000000UL /* Force Auto-Negotiation */
5513+#define HWF_CLK_GATING_ENABLE 0x02000000UL /* Enable Clock Gating */
5514+#define HWF_RED_CORE_CLK_SUP 0x01000000UL /* Reduced Core Clock supp. */
5515+#define HWF_RESTORE_LOST_BARS 0x00800000UL /* Save and restore PCI BARs */
5516+#define HWF_ASPM_SWITCHING 0x00400000UL /* Activate ASPM feature */
5517+#define HWF_TX_IP_ID_INCR_ON 0x00200000UL /* Enable Tx IP ID Increment */
5518+
5519+/*-RMV- DWORD 1: Deviations */
5520+#define HWF_WA_DEV_4200 0x10200000UL /*-RMV- 4.200 (D3 Blue Screen)*/
5521+#define HWF_WA_DEV_4185CS 0x10100000UL /*-RMV- 4.185 (ECU 100 CS cal)*/
5522+#define HWF_WA_DEV_4185 0x10080000UL /*-RMV- 4.185 (ECU Tx h check)*/
5523+#define HWF_WA_DEV_4167 0x10040000UL /*-RMV- 4.167 (Rx OvSize Hang)*/
5524+#define HWF_WA_DEV_4152 0x10020000UL /*-RMV- 4.152 (RSS issue) */
5525+#define HWF_WA_DEV_4115 0x10010000UL /*-RMV- 4.115 (Rx MAC FIFO) */
5526+#define HWF_WA_DEV_4109 0x10008000UL /*-RMV- 4.109 (BIU hang) */
5527+#define HWF_WA_DEV_483 0x10004000UL /*-RMV- 4.83 (Rx TCP wrong) */
5528+#define HWF_WA_DEV_479 0x10002000UL /*-RMV- 4.79 (Rx BMU hang II) */
5529+#define HWF_WA_DEV_472 0x10001000UL /*-RMV- 4.72 (GPHY2 MDC clk) */
5530+#define HWF_WA_DEV_463 0x10000800UL /*-RMV- 4.63 (Rx BMU hang I) */
5531+#define HWF_WA_DEV_427 0x10000400UL /*-RMV- 4.27 (Tx Done Rep) */
5532+#define HWF_WA_DEV_42 0x10000200UL /*-RMV- 4.2 (pref unit burst) */
5533+#define HWF_WA_DEV_46 0x10000100UL /*-RMV- 4.6 (CPU crash II) */
5534+#define HWF_WA_DEV_43_418 0x10000080UL /*-RMV- 4.3 & 4.18 (PCI unexp */
5535+ /*-RMV- compl&Stat BMU deadl) */
5536+#define HWF_WA_DEV_420 0x10000040UL /*-RMV- 4.20 (Status BMU ov) */
5537+#define HWF_WA_DEV_423 0x10000020UL /*-RMV- 4.23 (TCP Segm Hang) */
5538+#define HWF_WA_DEV_424 0x10000010UL /*-RMV- 4.24 (MAC reg overwr) */
5539+#define HWF_WA_DEV_425 0x10000008UL /*-RMV- 4.25 (Magic packet */
5540+ /*-RMV- with odd offset) */
5541+#define HWF_WA_DEV_428 0x10000004UL /*-RMV- 4.28 (Poll-U &BigEndi)*/
5542+#define HWF_WA_FIFO_FLUSH_YLA0 0x10000002UL /*-RMV- dis Rx GMAC FIFO Flush*/
5543+ /*-RMV- for Yu-L Rev. A0 only */
5544+#define HWF_WA_COMA_MODE 0x10000001UL /*-RMV- Coma Mode WA req */
5545+
5546+/* DWORD 2: Real HW features not settable from outside */
5547+/* not yet used */
5548+#if 0
5549+#define HWF_SYNC_TX_SUP 0x20800000UL /* Synch. Tx Queue available */
5550+#define HWF_SINGLE_PORT_DEVICE 0x20400000UL /* Device has only one LAN IF */
5551+#define HWF_JUMBO_FRAMES_SUP 0x20200000UL /* Jumbo Frames supported */
5552+#define HWF_TX_TCP_CSUM_SUP 0x20100000UL /* TCP Tx checksum supported */
5553+#define HWF_TX_UDP_CSUM_SUP 0x20080000UL /* UDP Tx checksum supported */
5554+#define HWF_RX_CSUM_SUP 0x20040000UL /* RX checksum supported */
5555+#define HWF_TCP_SEGM_SUP 0x20020000UL /* TCP segmentation supported */
5556+#define HWF_RSS_HASH_SUP 0x20010000UL /* RSS Hash supported */
5557+#define HWF_PORT_VLAN_SUP 0x20008000UL /* VLAN can be config per port*/
5558+#define HWF_ROLE_PARAM_SUP 0x20004000UL /* Role parameter supported */
5559+#define HWF_LOW_PMODE_SUP 0x20002000UL /* Low Power Mode supported */
5560+#define HWF_ENERGIE_DEMO_SUP 0x20001000UL /* Energy Detect mode supp. */
5561+#define HWF_SPEED1000_SUP 0x20000800UL /* Line Speed 1000 supported */
5562+#define HWF_SPEED100_SUP 0x20000400UL /* Line Speed 100 supported */
5563+#define HWF_SPEED10_SUP 0x20000200UL /* Line Speed 10 supported */
5564+#define HWF_AUTONEGSENSE_SUP 0x20000100UL /* Autoneg Sense supported */
5565+#define HWF_PHY_LOOPB_MD_SUP 0x20000080UL /* PHY loopback mode supp. */
5566+#define HWF_ASF_SUP 0x20000040UL /* ASF support possible */
5567+#define HWF_QS_STEPS_1KB 0x20000020UL /* The Rx/Tx queues can be */
5568+ /* configured with 1 kB res. */
5569+#define HWF_OWN_RAM_PER_PORT 0x20000010UL /* Each port has a separate */
5570+ /* RAM buffer */
5571+#define HWF_MIN_LED_IF 0x20000008UL /* Minimal LED interface */
5572+ /* (e.g. for Yukon-EC) */
5573+#define HWF_LIST_ELEMENTS_USED 0x20000004UL /* HW uses list elements */
5574+ /* (otherwise desc. are used) */
5575+#define HWF_GMAC_INSIDE 0x20000002UL /* Device contains GMAC */
5576+#define HWF_TWSI_PRESENT 0x20000001UL /* TWSI sensor bus present */
5577+#endif
5578+
5579+/* DWORD 3: still unused */
5580+
5581+
5582+/*
5583+ * HW_FEATURE() - returns whether the feature is serviced or not
5584+ */
5585+#define HW_FEATURE(pAC, ReqFeature) \
5586+ (((pAC)->GIni.HwF.Features[((ReqFeature) & 0x30000000UL) >> 28] &\
5587+ ((ReqFeature) & 0x0fffffffUL)) != 0)
5588+
5589+#define HW_FEAT_LIST 0
5590+#define HW_DEV_LIST 1
5591+#define HW_FEAT_LIST_2 2
5592+
5593+#define SET_HW_FEATURE_MASK(pAC, List, OffMaskValue, OnMaskValue) { \
5594+ if ((List) == HW_FEAT_LIST || (List) == HW_DEV_LIST) { \
5595+ (pAC)->GIni.HwF.OffMask[List] = (OffMaskValue); \
5596+ (pAC)->GIni.HwF.OnMask[List] = (OnMaskValue); \
5597+ } \
5598+}
5599+
5600+/* driver access macros for GIni structure ***********************************/
5601+
5602+#define CHIP_ID_YUKON_2(pAC) ((pAC)->GIni.GIYukon2)
5603+
5604+#define HW_SYNC_TX_SUPPORTED(pAC) \
5605+ ((pAC)->GIni.GIChipId != CHIP_ID_YUKON_EC && \
5606+ (pAC)->GIni.GIChipId != CHIP_ID_YUKON_FE && \
5607+ (pAC)->GIni.GIChipId != CHIP_ID_YUKON_EC_U)
5608+
5609+#define HW_MS_TO_TICKS(pAC, MsTime) \
5610+ ((MsTime) * (62500L/100) * (pAC)->GIni.GIHstClkFact)
5611+
5612+#define HW_IS_8056(pAC) \
5613+ ((pAC)->GIni.GIChipId == CHIP_ID_YUKON_EC_U && \
5614+ ((pAC)->GIni.GIChipRev == CHIP_REV_YU_EC_U_A1 || \
5615+ (pAC)->GIni.GIChipRev == CHIP_REV_YU_EC_U_B0) && \
5616+ (pAC)->GIni.GIChipCap == 2 && \
5617+ !HW_FEATURE(pAC, HWF_WA_DEV_4200))
5618+
5619+#ifdef XXX
5620+/* still under construction */
5621+#define HW_IS_SINGLE_PORT(pAC) ((pAC)->GIni.GIMacsFound == 1)
5622+#define HW_NUMBER_OF_PORTS(pAC) ((pAC)->GIni.GIMacsFound)
5623+
5624+#define HW_TX_UDP_CSUM_SUPPORTED(pAC) \
5625+ ((((pAC)->GIni.GIChipId >= CHIP_ID_YUKON) && ((pAC)->GIni.GIChipRev != 0))
5626+
5627+#define HW_DEFAULT_LINESPEED(pAC) \
5628+ ((!(pAC)->GIni.GIGenesis && (pAC)->GIni.GICopperType) ? \
5629+ SK_LSPEED_AUTO : SK_LSPEED_1000MBPS)
5630+
5631+#define HW_ROLE_PARAM_SUPPORTED(pAC) ((pAC)->GIni.GICopperType)
5632+
5633+#define HW_SPEED1000_SUPPORTED(pAC, Port) \
5634+ ((pAC)->GIni.GP[Port].PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS)
5635+
5636+#define HW_SPEED100_SUPPORTED(pAC, Port) \
5637+ ((pAC)->GIni.GP[Port].PLinkSpeedCap & SK_LSPEED_CAP_100MBPS)
5638+
5639+#define HW_SPEED10_SUPPORTED(pAC, Port) \
5640+ ((pAC)->GIni.GP[Port].PLinkSpeedCap & SK_LSPEED_CAP_10MBPS)
5641+
5642+#define HW_AUTONEGSENSE_SUPPORTED(pAC) ((pAC)->GIni.GP[0].PhyType==SK_PHY_XMAC)
5643+
5644+#define HW_FREQ_TO_CARD_TICKS(pAC, AdapterClkSpeed, Freq) \
5645+ (((AdapterClkSpeed / 100) * (pAC)->GIni.GIHstClkFact) / Freq)
5646+
5647+#define HW_IS_LINK_UP(pAC, Port) ((pAC)->GIni.GP[Port].PHWLinkUp)
5648+#define HW_LINK_SPEED_USED(pAC, Port) ((pAC)->GIni.GP[Port].PLinkSpeedUsed)
5649+#define HW_RAM_SIZE(pAC) ((pAC)->GIni.GIRamSize)
5650+
5651+#define HW_PHY_LP_MODE_SUPPORTED(pAC) (pAC0->???
5652+#define HW_ASF_ACTIVE(pAC) ???
5653+#define RAWIO_OUT32(pAC, pAC->RegIrqMask, pAC->GIni.GIValIrqMask)...
5654+
5655+/* macro to check whether Tx checksum is supported */
5656+#define HW_TX_CSUM_SUPPORTED(pAC) ((pAC)->GIni.GIChipId != CHIP_ID_GENESIS)
5657+
5658+BMU_UDP_CHECK : BMU_TCP_CHECK;
5659+
5660+/* macro for - Own Bit mirrored to DWORD7 (Yukon LP receive descriptor) */
5661+#endif /* 0 */
5662+
5663+
5664 /* structures *****************************************************************/
5665
5666 /*
5667+ * HW Feature structure
5668+ */
5669+typedef struct s_HwFeatures {
5670+ SK_U32 Features[4]; /* Feature list */
5671+ SK_U32 OffMask[4]; /* Off Mask */
5672+ SK_U32 OnMask[4]; /* On Mask */
5673+} SK_HW_FEATURES;
5674+
5675+/*
5676 * MAC specific functions
5677 */
5678 typedef struct s_GeMacFunc {
5679- int (*pFnMacUpdateStats)(SK_AC *pAC, SK_IOC IoC, unsigned int Port);
5680- int (*pFnMacStatistic)(SK_AC *pAC, SK_IOC IoC, unsigned int Port,
5681- SK_U16 StatAddr, SK_U32 SK_FAR *pVal);
5682- int (*pFnMacResetCounter)(SK_AC *pAC, SK_IOC IoC, unsigned int Port);
5683- int (*pFnMacOverflow)(SK_AC *pAC, SK_IOC IoC, unsigned int Port,
5684- SK_U16 IStatus, SK_U64 SK_FAR *pVal);
5685+ int (*pFnMacUpdateStats)(SK_AC *, SK_IOC, unsigned int);
5686+ int (*pFnMacStatistic)(SK_AC *, SK_IOC, unsigned int, SK_U16, SK_U32 SK_FAR *);
5687+ int (*pFnMacResetCounter)(SK_AC *, SK_IOC, unsigned int);
5688+ int (*pFnMacOverflow)(SK_AC *, SK_IOC, unsigned int, SK_U16, SK_U64 SK_FAR *);
5689+ void (*pSkGeSirqIsr)(SK_AC *, SK_IOC, SK_U32);
5690+#ifdef SK_DIAG
5691+ int (*pFnMacPhyRead)(SK_AC *, SK_IOC, int, int, SK_U16 SK_FAR *);
5692+ int (*pFnMacPhyWrite)(SK_AC *, SK_IOC, int, int, SK_U16);
5693+#endif /* SK_DIAG */
5694 } SK_GEMACFUNC;
5695
5696 /*
5697@@ -311,7 +499,7 @@
5698 #ifndef SK_DIAG
5699 SK_TIMER PWaTimer; /* Workaround Timer */
5700 SK_TIMER HalfDupChkTimer;
5701-#endif /* SK_DIAG */
5702+#endif /* !SK_DIAG */
5703 SK_U32 PPrevShorts; /* Previous Short Counter checking */
5704 SK_U32 PPrevFcs; /* Previous FCS Error Counter checking */
5705 SK_U64 PPrevRx; /* Previous RxOk Counter checking */
5706@@ -335,6 +523,7 @@
5707 int PXaQOff; /* Asynchronous Tx Queue Address Offset */
5708 int PhyType; /* PHY used on this port */
5709 int PState; /* Port status (reset, stop, init, run) */
5710+ int PPortUsage; /* Driver Port Usage */
5711 SK_U16 PhyId1; /* PHY Id1 on this port */
5712 SK_U16 PhyAddr; /* MDIO/MDC PHY address */
5713 SK_U16 PIsave; /* Saved Interrupt status word */
5714@@ -348,7 +537,7 @@
5715 SK_U8 PLinkModeConf; /* Link Mode configured */
5716 SK_U8 PLinkMode; /* Link Mode currently used */
5717 SK_U8 PLinkModeStatus;/* Link Mode Status */
5718- SK_U8 PLinkSpeedCap; /* Link Speed Capabilities(10/100/1000 Mbps) */
5719+ SK_U8 PLinkSpeedCap; /* Link Speed Capabilities (10/100/1000 Mbps) */
5720 SK_U8 PLinkSpeed; /* configured Link Speed (10/100/1000 Mbps) */
5721 SK_U8 PLinkSpeedUsed; /* current Link Speed (10/100/1000 Mbps) */
5722 SK_U8 PFlowCtrlCap; /* Flow Control Capabilities */
5723@@ -367,7 +556,10 @@
5724 int PMacJamLen; /* MAC Jam length */
5725 int PMacJamIpgVal; /* MAC Jam IPG */
5726 int PMacJamIpgData; /* MAC IPG Jam to Data */
5727+ int PMacBackOffLim; /* MAC Back-off Limit */
5728+ int PMacDataBlind; /* MAC Data Blinder */
5729 int PMacIpgData; /* MAC Data IPG */
5730+ SK_U16 PMacAddr[3]; /* MAC address */
5731 SK_BOOL PMacLimit4; /* reset collision counter and backoff algorithm */
5732 } SK_GEPORT;
5733
5734@@ -379,27 +571,38 @@
5735 int GIChipId; /* Chip Identification Number */
5736 int GIChipRev; /* Chip Revision Number */
5737 SK_U8 GIPciHwRev; /* PCI HW Revision Number */
5738+ SK_U8 GIPciBus; /* PCI Bus Type (PCI / PCI-X / PCI-Express) */
5739+ SK_U8 GIPciMode; /* PCI / PCI-X Mode @ Clock */
5740+ SK_U8 GIPexWidth; /* PCI-Express Negotiated Link Width */
5741 SK_BOOL GIGenesis; /* Genesis adapter ? */
5742- SK_BOOL GIYukon; /* YUKON-A1/Bx chip */
5743+ SK_BOOL GIYukon; /* YUKON family (1 and 2) */
5744 SK_BOOL GIYukonLite; /* YUKON-Lite chip */
5745+ SK_BOOL GIYukon2; /* YUKON-2 chip (-XL, -EC or -FE) */
5746+ SK_U8 GIConTyp; /* Connector Type */
5747+ SK_U8 GIPmdTyp; /* PMD Type */
5748 SK_BOOL GICopperType; /* Copper Type adapter ? */
5749 SK_BOOL GIPciSlot64; /* 64-bit PCI Slot */
5750 SK_BOOL GIPciClock66; /* 66 MHz PCI Clock */
5751 SK_BOOL GIVauxAvail; /* VAUX available (YUKON) */
5752 SK_BOOL GIYukon32Bit; /* 32-Bit YUKON adapter */
5753+ SK_BOOL GIAsfEnabled; /* ASF subsystem enabled */
5754+ SK_BOOL GIAsfRunning; /* ASF subsystem running */
5755 SK_U16 GILedBlinkCtrl; /* LED Blink Control */
5756 int GIMacsFound; /* Number of MACs found on this adapter */
5757 int GIMacType; /* MAC Type used on this adapter */
5758- int GIHstClkFact; /* Host Clock Factor (62.5 / HstClk * 100) */
5759- int GIPortUsage; /* Driver Port Usage */
5760+ int GIChipCap; /* Adapter's Capabilities */
5761+ int GIHwResInfo; /* HW Resources / Application Information */
5762+ int GIHstClkFact; /* Host Clock Factor (HstClk / 62.5 * 100) */
5763 int GILevel; /* Initialization Level completed */
5764 int GIRamSize; /* The RAM size of the adapter in kB */
5765 int GIWolOffs; /* WOL Register Offset (HW-Bug in Rev. A) */
5766 SK_U32 GIRamOffs; /* RAM Address Offset for addr calculation */
5767 SK_U32 GIPollTimerVal; /* Descr. Poll Timer Init Val (HstClk ticks) */
5768 SK_U32 GIValIrqMask; /* Value for Interrupt Mask */
5769+ SK_U32 GIValHwIrqMask; /* Value for HWE Interrupt Mask */
5770 SK_U32 GITimeStampCnt; /* Time Stamp High Counter (YUKON only) */
5771 SK_GEPORT GP[SK_MAX_MACS];/* Port Dependent Information */
5772+ SK_HW_FEATURES HwF; /* HW Features struct */
5773 SK_GEMACFUNC GIFunc; /* MAC depedent functions */
5774 } SK_GEINIT;
5775
5776@@ -417,7 +620,7 @@
5777 #define SKERR_HWI_E005 (SKERR_HWI_E004+1)
5778 #define SKERR_HWI_E005MSG "SkGeInitPort(): cannot init running ports"
5779 #define SKERR_HWI_E006 (SKERR_HWI_E005+1)
5780-#define SKERR_HWI_E006MSG "SkGeMacInit(): PState does not match HW state"
5781+#define SKERR_HWI_E006MSG "SkGeInit() called with illegal Chip Id"
5782 #define SKERR_HWI_E007 (SKERR_HWI_E006+1)
5783 #define SKERR_HWI_E007MSG "SkXmInitDupMd() called with invalid Dup Mode"
5784 #define SKERR_HWI_E008 (SKERR_HWI_E007+1)
5785@@ -433,11 +636,11 @@
5786 #define SKERR_HWI_E013 (SKERR_HWI_E012+1)
5787 #define SKERR_HWI_E013MSG "SkGeInitPort(): cfg changed for running queue"
5788 #define SKERR_HWI_E014 (SKERR_HWI_E013+1)
5789-#define SKERR_HWI_E014MSG "SkGeInitPort(): unknown GIPortUsage specified"
5790+#define SKERR_HWI_E014MSG "SkGeInitPort(): unknown PortUsage specified"
5791 #define SKERR_HWI_E015 (SKERR_HWI_E014+1)
5792-#define SKERR_HWI_E015MSG "Illegal Link mode parameter"
5793+#define SKERR_HWI_E015MSG "Illegal Link Mode parameter"
5794 #define SKERR_HWI_E016 (SKERR_HWI_E015+1)
5795-#define SKERR_HWI_E016MSG "Illegal Flow control mode parameter"
5796+#define SKERR_HWI_E016MSG "Illegal Flow Control Mode parameter"
5797 #define SKERR_HWI_E017 (SKERR_HWI_E016+1)
5798 #define SKERR_HWI_E017MSG "Illegal value specified for GIPollTimerVal"
5799 #define SKERR_HWI_E018 (SKERR_HWI_E017+1)
5800@@ -447,15 +650,19 @@
5801 #define SKERR_HWI_E020 (SKERR_HWI_E019+1)
5802 #define SKERR_HWI_E020MSG "Illegal Master/Slave parameter"
5803 #define SKERR_HWI_E021 (SKERR_HWI_E020+1)
5804-#define SKERR_HWI_E021MSG "MacUpdateStats(): cannot update statistic counter"
5805-#define SKERR_HWI_E022 (SKERR_HWI_E021+1)
5806-#define SKERR_HWI_E022MSG "MacStatistic(): illegal statistic base address"
5807+#define SKERR_HWI_E021MSG "MacUpdateStats(): cannot update statistic counter"
5808+#define SKERR_HWI_E022 (SKERR_HWI_E021+1)
5809+#define SKERR_HWI_E022MSG "MacStatistic(): illegal statistic base address"
5810 #define SKERR_HWI_E023 (SKERR_HWI_E022+1)
5811 #define SKERR_HWI_E023MSG "SkGeInitPort(): Transmit Queue Size too small"
5812 #define SKERR_HWI_E024 (SKERR_HWI_E023+1)
5813 #define SKERR_HWI_E024MSG "FATAL: SkGeStopPort() does not terminate (Rx)"
5814 #define SKERR_HWI_E025 (SKERR_HWI_E024+1)
5815-#define SKERR_HWI_E025MSG ""
5816+#define SKERR_HWI_E025MSG "Link Partner not Auto-Neg. able"
5817+#define SKERR_HWI_E026 (SKERR_HWI_E025+1)
5818+#define SKERR_HWI_E026MSG "PEX negotiated Link width not max."
5819+#define SKERR_HWI_E027 (SKERR_HWI_E026+1)
5820+#define SKERR_HWI_E027MSG ""
5821
5822 /* function prototypes ********************************************************/
5823
5824@@ -464,6 +671,30 @@
5825 /*
5826 * public functions in skgeinit.c
5827 */
5828+extern void SkGePortVlan(
5829+ SK_AC *pAC,
5830+ SK_IOC IoC,
5831+ int Port,
5832+ SK_BOOL Enable);
5833+
5834+extern void SkGeRxRss(
5835+ SK_AC *pAC,
5836+ SK_IOC IoC,
5837+ int Port,
5838+ SK_BOOL Enable);
5839+
5840+extern void SkGeRxCsum(
5841+ SK_AC *pAC,
5842+ SK_IOC IoC,
5843+ int Port,
5844+ SK_BOOL Enable);
5845+
5846+extern void SkGePollRxD(
5847+ SK_AC *pAC,
5848+ SK_IOC IoC,
5849+ int Port,
5850+ SK_BOOL PollRxD);
5851+
5852 extern void SkGePollTxD(
5853 SK_AC *pAC,
5854 SK_IOC IoC,
5855@@ -516,11 +747,28 @@
5856 int Led,
5857 int Mode);
5858
5859+extern void SkGeInitRamIface(
5860+ SK_AC *pAC,
5861+ SK_IOC IoC);
5862+
5863 extern int SkGeInitAssignRamToQueues(
5864 SK_AC *pAC,
5865- int ActivePort,
5866+ int Port,
5867 SK_BOOL DualNet);
5868
5869+extern void DoInitRamQueue(
5870+ SK_AC *pAC,
5871+ SK_IOC IoC,
5872+ int QuIoOffs,
5873+ SK_U32 QuStartAddr,
5874+ SK_U32 QuEndAddr,
5875+ int QuType);
5876+
5877+extern int SkYuk2RestartRxBmu(
5878+ SK_AC *pAC,
5879+ SK_IOC IoC,
5880+ int Port);
5881+
5882 /*
5883 * public functions in skxmac2.c
5884 */
5885@@ -539,6 +787,11 @@
5886 SK_IOC IoC,
5887 int Port);
5888
5889+extern void SkMacClearRst(
5890+ SK_AC *pAC,
5891+ SK_IOC IoC,
5892+ int Port);
5893+
5894 extern void SkXmInitMac(
5895 SK_AC *pAC,
5896 SK_IOC IoC,
5897@@ -565,6 +818,11 @@
5898 SK_IOC IoC,
5899 int Port);
5900
5901+extern void SkMacFlushRxFifo(
5902+ SK_AC *pAC,
5903+ SK_IOC IoC,
5904+ int Port);
5905+
5906 extern void SkMacIrq(
5907 SK_AC *pAC,
5908 SK_IOC IoC,
5909@@ -581,7 +839,13 @@
5910 int Port,
5911 SK_U16 IStatus);
5912
5913-extern int SkMacRxTxEnable(
5914+extern void SkMacSetRxTxEn(
5915+ SK_AC *pAC,
5916+ SK_IOC IoC,
5917+ int Port,
5918+ int Para);
5919+
5920+extern int SkMacRxTxEnable(
5921 SK_AC *pAC,
5922 SK_IOC IoC,
5923 int Port);
5924@@ -598,28 +862,34 @@
5925 int Port,
5926 SK_BOOL Enable);
5927
5928-extern void SkXmPhyRead(
5929+extern void SkMacTimeStamp(
5930+ SK_AC *pAC,
5931+ SK_IOC IoC,
5932+ int Port,
5933+ SK_BOOL Enable);
5934+
5935+extern int SkXmPhyRead(
5936 SK_AC *pAC,
5937 SK_IOC IoC,
5938 int Port,
5939 int Addr,
5940 SK_U16 SK_FAR *pVal);
5941
5942-extern void SkXmPhyWrite(
5943+extern int SkXmPhyWrite(
5944 SK_AC *pAC,
5945 SK_IOC IoC,
5946 int Port,
5947 int Addr,
5948 SK_U16 Val);
5949
5950-extern void SkGmPhyRead(
5951+extern int SkGmPhyRead(
5952 SK_AC *pAC,
5953 SK_IOC IoC,
5954 int Port,
5955 int Addr,
5956 SK_U16 SK_FAR *pVal);
5957
5958-extern void SkGmPhyWrite(
5959+extern int SkGmPhyWrite(
5960 SK_AC *pAC,
5961 SK_IOC IoC,
5962 int Port,
5963@@ -633,6 +903,16 @@
5964 int StartNum,
5965 int StopNum);
5966
5967+extern void SkXmInitDupMd(
5968+ SK_AC *pAC,
5969+ SK_IOC IoC,
5970+ int Port);
5971+
5972+extern void SkXmInitPauseMd(
5973+ SK_AC *pAC,
5974+ SK_IOC IoC,
5975+ int Port);
5976+
5977 extern void SkXmAutoNegLipaXmac(
5978 SK_AC *pAC,
5979 SK_IOC IoC,
5980@@ -677,7 +957,7 @@
5981 SK_AC *pAC,
5982 SK_IOC IoC,
5983 unsigned int Port,
5984- SK_U16 IStatus,
5985+ SK_U16 IStatus,
5986 SK_U64 SK_FAR *pStatus);
5987
5988 extern int SkGmOverflowStatus(
5989@@ -693,6 +973,19 @@
5990 int Port,
5991 SK_BOOL StartTest);
5992
5993+#ifdef SK_PHY_LP_MODE
5994+extern int SkGmEnterLowPowerMode(
5995+ SK_AC *pAC,
5996+ SK_IOC IoC,
5997+ int Port,
5998+ SK_U8 Mode);
5999+
6000+extern int SkGmLeaveLowPowerMode(
6001+ SK_AC *pAC,
6002+ SK_IOC IoC,
6003+ int Port);
6004+#endif /* SK_PHY_LP_MODE */
6005+
6006 #ifdef SK_DIAG
6007 extern void SkGePhyRead(
6008 SK_AC *pAC,
6009@@ -718,11 +1011,6 @@
6010 SK_IOC IoC,
6011 int Port,
6012 SK_BOOL Enable);
6013-extern void SkMacTimeStamp(
6014- SK_AC *pAC,
6015- SK_IOC IoC,
6016- int Port,
6017- SK_BOOL Enable);
6018 extern void SkXmSendCont(
6019 SK_AC *pAC,
6020 SK_IOC IoC,
6021@@ -735,6 +1023,7 @@
6022 /*
6023 * public functions in skgeinit.c
6024 */
6025+extern void SkGePollRxD();
6026 extern void SkGePollTxD();
6027 extern void SkGeYellowLED();
6028 extern int SkGeCfgSync();
6029@@ -744,30 +1033,42 @@
6030 extern void SkGeDeInit();
6031 extern int SkGeInitPort();
6032 extern void SkGeXmitLED();
6033+extern void SkGeInitRamIface();
6034 extern int SkGeInitAssignRamToQueues();
6035+extern void SkGePortVlan();
6036+extern void SkGeRxCsum();
6037+extern void SkGeRxRss();
6038+extern void DoInitRamQueue();
6039+extern int SkYuk2RestartRxBmu();
6040
6041 /*
6042 * public functions in skxmac2.c
6043 */
6044-extern void SkMacRxTxDisable();
6045+extern void SkMacRxTxDisable();
6046 extern void SkMacSoftRst();
6047 extern void SkMacHardRst();
6048-extern void SkMacInitPhy();
6049-extern int SkMacRxTxEnable();
6050-extern void SkMacPromiscMode();
6051-extern void SkMacHashing();
6052-extern void SkMacIrqDisable();
6053+extern void SkMacClearRst();
6054+extern void SkMacInitPhy();
6055+extern int SkMacRxTxEnable();
6056+extern void SkMacPromiscMode();
6057+extern void SkMacHashing();
6058+extern void SkMacIrqDisable();
6059 extern void SkMacFlushTxFifo();
6060+extern void SkMacFlushRxFifo();
6061 extern void SkMacIrq();
6062 extern int SkMacAutoNegDone();
6063 extern void SkMacAutoNegLipaPhy();
6064+extern void SkMacSetRxTxEn();
6065+extern void SkMacTimeStamp();
6066 extern void SkXmInitMac();
6067-extern void SkXmPhyRead();
6068-extern void SkXmPhyWrite();
6069+extern int SkXmPhyRead();
6070+extern int SkXmPhyWrite();
6071 extern void SkGmInitMac();
6072-extern void SkGmPhyRead();
6073-extern void SkGmPhyWrite();
6074+extern int SkGmPhyRead();
6075+extern int SkGmPhyWrite();
6076 extern void SkXmClrExactAddr();
6077+extern void SkXmInitDupMd();
6078+extern void SkXmInitPauseMd();
6079 extern void SkXmAutoNegLipaXmac();
6080 extern int SkXmUpdateStats();
6081 extern int SkGmUpdateStats();
6082@@ -778,20 +1079,24 @@
6083 extern int SkXmOverflowStatus();
6084 extern int SkGmOverflowStatus();
6085 extern int SkGmCableDiagStatus();
6086+#ifdef SK_PHY_LP_MODE
6087+extern int SkGmEnterLowPowerMode();
6088+extern int SkGmLeaveLowPowerMode();
6089+#endif /* SK_PHY_LP_MODE */
6090
6091 #ifdef SK_DIAG
6092 extern void SkGePhyRead();
6093 extern void SkGePhyWrite();
6094 extern void SkMacSetRxCmd();
6095 extern void SkMacCrcGener();
6096-extern void SkMacTimeStamp();
6097 extern void SkXmSendCont();
6098 #endif /* SK_DIAG */
6099
6100-#endif /* SK_KR_PROTO */
6101+#endif /* SK_KR_PROTO */
6102
6103 #ifdef __cplusplus
6104 }
6105-#endif /* __cplusplus */
6106+#endif /* __cplusplus */
6107+
6108+#endif /* __INC_SKGEINIT_H_ */
6109
6110-#endif /* __INC_SKGEINIT_H_ */
6111diff -ruN linux/drivers/net/sk98lin/h/skgepnm2.h linux-new/drivers/net/sk98lin/h/skgepnm2.h
6112--- linux/drivers/net/sk98lin/h/skgepnm2.h 2007-01-02 23:21:17.000000000 +0100
6113+++ linux-new/drivers/net/sk98lin/h/skgepnm2.h 2006-10-13 10:18:34.000000000 +0200
6114@@ -2,14 +2,15 @@
6115 *
6116 * Name: skgepnm2.h
6117 * Project: GEnesis, PCI Gigabit Ethernet Adapter
6118- * Version: $Revision$
6119- * Date: $Date$
6120+ * Version: $Revision$
6121+ * Date: $Date$
6122 * Purpose: Defines for Private Network Management Interface
6123 *
6124 ****************************************************************************/
6125
6126 /******************************************************************************
6127 *
6128+ * LICENSE:
6129 * (C)Copyright 1998-2002 SysKonnect GmbH.
6130 * (C)Copyright 2002-2003 Marvell.
6131 *
6132@@ -19,6 +20,7 @@
6133 * (at your option) any later version.
6134 *
6135 * The information in this file is provided "AS IS" without warranty.
6136+ * /LICENSE
6137 *
6138 ******************************************************************************/
6139
6140@@ -28,8 +30,13 @@
6141 /*
6142 * General definitions
6143 */
6144-#define SK_PNMI_CHIPSET_XMAC 1 /* XMAC11800FP */
6145-#define SK_PNMI_CHIPSET_YUKON 2 /* YUKON */
6146+#define SK_PNMI_CHIPSET_XMAC 1 /* XMAC11800FP */
6147+#define SK_PNMI_CHIPSET_YUKON 2 /* YUKON */
6148+#define SK_PNMI_CHIPSET_YUKON_LITE 3 /* YUKON-Lite (Rev. A1-A3) */
6149+#define SK_PNMI_CHIPSET_YUKON_LP 4 /* YUKON-LP */
6150+#define SK_PNMI_CHIPSET_YUKON_XL 5 /* YUKON-2 XL */
6151+#define SK_PNMI_CHIPSET_YUKON_EC 6 /* YUKON-2 EC */
6152+#define SK_PNMI_CHIPSET_YUKON_FE 7 /* YUKON-2 FE */
6153
6154 #define SK_PNMI_BUS_PCI 1 /* PCI bus*/
6155
6156@@ -70,9 +77,9 @@
6157 /*
6158 * VCT internal status values
6159 */
6160-#define SK_PNMI_VCT_PENDING 32
6161-#define SK_PNMI_VCT_TEST_DONE 64
6162-#define SK_PNMI_VCT_LINK 128
6163+#define SK_PNMI_VCT_PENDING 0x20
6164+#define SK_PNMI_VCT_TEST_DONE 0x40
6165+#define SK_PNMI_VCT_LINK 0x80
6166
6167 /*
6168 * Internal table definitions
6169@@ -323,7 +330,7 @@
6170 vSt, \
6171 pAC->Pnmi.MacUpdatedFlag, \
6172 pAC->Pnmi.RlmtUpdatedFlag, \
6173- pAC->Pnmi.SirqUpdatedFlag))}}
6174+ pAC->Pnmi.SirqUpdatedFlag));}}
6175
6176 #else /* !DEBUG */
6177
6178diff -ruN linux/drivers/net/sk98lin/h/skgepnmi.h linux-new/drivers/net/sk98lin/h/skgepnmi.h
6179--- linux/drivers/net/sk98lin/h/skgepnmi.h 2007-01-02 23:21:17.000000000 +0100
6180+++ linux-new/drivers/net/sk98lin/h/skgepnmi.h 2006-10-13 10:18:34.000000000 +0200
6181@@ -1,15 +1,16 @@
6182 /*****************************************************************************
6183 *
6184 * Name: skgepnmi.h
6185- * Project: GEnesis, PCI Gigabit Ethernet Adapter
6186- * Version: $Revision$
6187- * Date: $Date$
6188+ * Project: Gigabit Ethernet Adapters, PNMI-Module
6189+ * Version: $Revision$
6190+ * Date: $Date$
6191 * Purpose: Defines for Private Network Management Interface
6192 *
6193 ****************************************************************************/
6194
6195 /******************************************************************************
6196 *
6197+ * LICENSE:
6198 * (C)Copyright 1998-2002 SysKonnect GmbH.
6199 * (C)Copyright 2002-2003 Marvell.
6200 *
6201@@ -19,6 +20,7 @@
6202 * (at your option) any later version.
6203 *
6204 * The information in this file is provided "AS IS" without warranty.
6205+ * /LICENSE
6206 *
6207 ******************************************************************************/
6208
6209@@ -31,7 +33,7 @@
6210 #include "h/sktypes.h"
6211 #include "h/skerror.h"
6212 #include "h/sktimer.h"
6213-#include "h/ski2c.h"
6214+#include "h/sktwsi.h"
6215 #include "h/skaddr.h"
6216 #include "h/skrlmt.h"
6217 #include "h/skvpd.h"
6218@@ -41,7 +43,6 @@
6219 */
6220 #define SK_PNMI_MDB_VERSION 0x00030001 /* 3.1 */
6221
6222-
6223 /*
6224 * Event definitions
6225 */
6226@@ -54,16 +55,13 @@
6227 #define SK_PNMI_EVT_UTILIZATION_TIMER 7 /* Timer event for Utiliza. */
6228 #define SK_PNMI_EVT_CLEAR_COUNTER 8 /* Clear statistic counters */
6229 #define SK_PNMI_EVT_XMAC_RESET 9 /* XMAC will be reset */
6230-
6231 #define SK_PNMI_EVT_RLMT_PORT_UP 10 /* Port came logically up */
6232 #define SK_PNMI_EVT_RLMT_PORT_DOWN 11 /* Port went logically down */
6233 #define SK_PNMI_EVT_RLMT_SEGMENTATION 13 /* Two SP root bridges found */
6234 #define SK_PNMI_EVT_RLMT_ACTIVE_DOWN 14 /* Port went logically down */
6235 #define SK_PNMI_EVT_RLMT_ACTIVE_UP 15 /* Port came logically up */
6236-#define SK_PNMI_EVT_RLMT_SET_NETS 16 /* 1. Parameter is number of nets
6237- 1 = single net; 2 = dual net */
6238-#define SK_PNMI_EVT_VCT_RESET 17 /* VCT port reset timer event started with SET. */
6239-
6240+#define SK_PNMI_EVT_RLMT_SET_NETS 16 /* Number of nets (1 or 2). */
6241+#define SK_PNMI_EVT_VCT_RESET 17 /* VCT port reset timer event started with SET. */
6242
6243 /*
6244 * Return values
6245@@ -78,7 +76,6 @@
6246 #define SK_PNMI_ERR_UNKNOWN_NET 7
6247 #define SK_PNMI_ERR_NOT_SUPPORTED 10
6248
6249-
6250 /*
6251 * Return values of driver reset function SK_DRIVER_RESET() and
6252 * driver event function SK_DRIVER_EVENT()
6253@@ -86,19 +83,17 @@
6254 #define SK_PNMI_ERR_OK 0
6255 #define SK_PNMI_ERR_FAIL 1
6256
6257-
6258 /*
6259 * Return values of driver test function SK_DRIVER_SELFTEST()
6260 */
6261 #define SK_PNMI_TST_UNKNOWN (1 << 0)
6262-#define SK_PNMI_TST_TRANCEIVER (1 << 1)
6263+#define SK_PNMI_TST_TRANCEIVER (1 << 1)
6264 #define SK_PNMI_TST_ASIC (1 << 2)
6265 #define SK_PNMI_TST_SENSOR (1 << 3)
6266-#define SK_PNMI_TST_POWERMGMT (1 << 4)
6267+#define SK_PNMI_TST_POWERMGMT (1 << 4)
6268 #define SK_PNMI_TST_PCI (1 << 5)
6269 #define SK_PNMI_TST_MAC (1 << 6)
6270
6271-
6272 /*
6273 * RLMT specific definitions
6274 */
6275@@ -223,7 +218,17 @@
6276 #define OID_SKGE_RLMT_PORT_NUMBER 0xFF010141
6277 #define OID_SKGE_RLMT_PORT_ACTIVE 0xFF010142
6278 #define OID_SKGE_RLMT_PORT_PREFERRED 0xFF010143
6279-#define OID_SKGE_INTERMEDIATE_SUPPORT 0xFF010160
6280+
6281+#define OID_SKGE_RLMT_MONITOR_NUMBER 0xFF010150
6282+#define OID_SKGE_RLMT_MONITOR_INDEX 0xFF010151
6283+#define OID_SKGE_RLMT_MONITOR_ADDR 0xFF010152
6284+#define OID_SKGE_RLMT_MONITOR_ERRS 0xFF010153
6285+#define OID_SKGE_RLMT_MONITOR_TIMESTAMP 0xFF010154
6286+#define OID_SKGE_RLMT_MONITOR_ADMIN 0xFF010155
6287+
6288+#define OID_SKGE_INTERMEDIATE_SUPPORT 0xFF010160
6289+#define OID_SKGE_SET_TEAM_MAC_ADDRESS 0xFF010161
6290+#define OID_SKGE_DEVICE_INFORMATION 0xFF010162
6291
6292 #define OID_SKGE_SPEED_CAP 0xFF010170
6293 #define OID_SKGE_SPEED_MODE 0xFF010171
6294@@ -322,13 +327,6 @@
6295 #define OID_SKGE_RLMT_TX_SP_REQ_CTS 0xFF020168
6296 #define OID_SKGE_RLMT_RX_SP_CTS 0xFF020169
6297
6298-#define OID_SKGE_RLMT_MONITOR_NUMBER 0xFF010150
6299-#define OID_SKGE_RLMT_MONITOR_INDEX 0xFF010151
6300-#define OID_SKGE_RLMT_MONITOR_ADDR 0xFF010152
6301-#define OID_SKGE_RLMT_MONITOR_ERRS 0xFF010153
6302-#define OID_SKGE_RLMT_MONITOR_TIMESTAMP 0xFF010154
6303-#define OID_SKGE_RLMT_MONITOR_ADMIN 0xFF010155
6304-
6305 #define OID_SKGE_TX_SW_QUEUE_LEN 0xFF020170
6306 #define OID_SKGE_TX_SW_QUEUE_MAX 0xFF020171
6307 #define OID_SKGE_TX_RETRY 0xFF020172
6308@@ -352,6 +350,7 @@
6309 #define OID_SKGE_VCT_GET 0xFF020200
6310 #define OID_SKGE_VCT_SET 0xFF020201
6311 #define OID_SKGE_VCT_STATUS 0xFF020202
6312+#define OID_SKGE_VCT_CAPABILITIES 0xFF020203
6313
6314 #ifdef SK_DIAG_SUPPORT
6315 /* Defines for driver DIAG mode. */
6316@@ -367,22 +366,79 @@
6317 #define OID_SKGE_PHY_TYPE 0xFF020215
6318 #define OID_SKGE_PHY_LP_MODE 0xFF020216
6319
6320+/*
6321+ * Added for new DualNet IM driver V2
6322+ * these OIDs should later be in pnmi.h
6323+ */
6324+#define OID_SKGE_MAC_COUNT 0xFF020217
6325+#define OID_SKGE_DUALNET_MODE 0xFF020218
6326+#define OID_SKGE_SET_TAGHEADER 0xFF020219
6327+
6328+#ifdef SK_ASF
6329+/* Defines for ASF */
6330+#define OID_SKGE_ASF 0xFF02021a
6331+#define OID_SKGE_ASF_STORE_CONFIG 0xFF02021b
6332+#define OID_SKGE_ASF_ENA 0xFF02021c
6333+#define OID_SKGE_ASF_RETRANS 0xFF02021d
6334+#define OID_SKGE_ASF_RETRANS_INT 0xFF02021e
6335+#define OID_SKGE_ASF_HB_ENA 0xFF02021f
6336+#define OID_SKGE_ASF_HB_INT 0xFF020220
6337+#define OID_SKGE_ASF_WD_ENA 0xFF020221
6338+#define OID_SKGE_ASF_WD_TIME 0xFF020222
6339+#define OID_SKGE_ASF_IP_SOURCE 0xFF020223
6340+#define OID_SKGE_ASF_MAC_SOURCE 0xFF020224
6341+#define OID_SKGE_ASF_IP_DEST 0xFF020225
6342+#define OID_SKGE_ASF_MAC_DEST 0xFF020226
6343+#define OID_SKGE_ASF_COMMUNITY_NAME 0xFF020227
6344+#define OID_SKGE_ASF_RSP_ENA 0xFF020228
6345+#define OID_SKGE_ASF_RETRANS_COUNT_MIN 0xFF020229
6346+#define OID_SKGE_ASF_RETRANS_COUNT_MAX 0xFF02022a
6347+#define OID_SKGE_ASF_RETRANS_INT_MIN 0xFF02022b
6348+#define OID_SKGE_ASF_RETRANS_INT_MAX 0xFF02022c
6349+#define OID_SKGE_ASF_HB_INT_MIN 0xFF02022d
6350+#define OID_SKGE_ASF_HB_INT_MAX 0xFF02022e
6351+#define OID_SKGE_ASF_WD_TIME_MIN 0xFF02022f
6352+#define OID_SKGE_ASF_WD_TIME_MAX 0xFF020230
6353+#define OID_SKGE_ASF_HB_CAP 0xFF020231
6354+#define OID_SKGE_ASF_WD_TIMER_RES 0xFF020232
6355+#define OID_SKGE_ASF_GUID 0xFF020233
6356+#define OID_SKGE_ASF_KEY_OP 0xFF020234
6357+#define OID_SKGE_ASF_KEY_ADM 0xFF020235
6358+#define OID_SKGE_ASF_KEY_GEN 0xFF020236
6359+#define OID_SKGE_ASF_CAP 0xFF020237
6360+#define OID_SKGE_ASF_PAR_1 0xFF020238
6361+#define OID_SKGE_ASF_OVERALL_OID 0xFF020239
6362+#endif /* SK_ASF */
6363+
6364+
6365+// Defined for yukon2 path only
6366+#define OID_SKGE_UPPER_MINIPORT 0xFF02023D
6367+
6368+
6369+#ifdef SK_ASF
6370+/* Defines for ASF */
6371+#define OID_SKGE_ASF_FWVER_OID 0xFF020240
6372+#define OID_SKGE_ASF_ACPI_OID 0xFF020241
6373+#define OID_SKGE_ASF_SMBUS_OID 0xFF020242
6374+#endif /* SK_ASF */
6375+
6376+
6377 /* VCT struct to store a backup copy of VCT data after a port reset. */
6378 typedef struct s_PnmiVct {
6379 SK_U8 VctStatus;
6380- SK_U8 PCableLen;
6381- SK_U32 PMdiPairLen[4];
6382- SK_U8 PMdiPairSts[4];
6383+ SK_U8 CableLen;
6384+ SK_U32 MdiPairLen[4];
6385+ SK_U8 MdiPairSts[4];
6386 } SK_PNMI_VCT;
6387
6388
6389 /* VCT status values (to be given to CPA via OID_SKGE_VCT_STATUS). */
6390-#define SK_PNMI_VCT_NONE 0
6391-#define SK_PNMI_VCT_OLD_VCT_DATA 1
6392-#define SK_PNMI_VCT_NEW_VCT_DATA 2
6393-#define SK_PNMI_VCT_OLD_DSP_DATA 4
6394-#define SK_PNMI_VCT_NEW_DSP_DATA 8
6395-#define SK_PNMI_VCT_RUNNING 16
6396+#define SK_PNMI_VCT_NONE 0x00
6397+#define SK_PNMI_VCT_OLD_VCT_DATA 0x01
6398+#define SK_PNMI_VCT_NEW_VCT_DATA 0x02
6399+#define SK_PNMI_VCT_OLD_DSP_DATA 0x04
6400+#define SK_PNMI_VCT_NEW_DSP_DATA 0x08
6401+#define SK_PNMI_VCT_RUNNING 0x10
6402
6403
6404 /* VCT cable test status. */
6405@@ -390,7 +446,12 @@
6406 #define SK_PNMI_VCT_SHORT_CABLE 1
6407 #define SK_PNMI_VCT_OPEN_CABLE 2
6408 #define SK_PNMI_VCT_TEST_FAIL 3
6409-#define SK_PNMI_VCT_IMPEDANCE_MISMATCH 4
6410+#define SK_PNMI_VCT_IMPEDANCE_MISMATCH 4
6411+#define SK_PNMI_VCT_NOT_PRESENT 5
6412+
6413+/* VCT capabilities (needed for OID_SKGE_VCT_CAPABILITIES. */
6414+#define SK_PNMI_VCT_SUPPORTED 1
6415+#define SK_PNMI_VCT_NOT_SUPPORTED 0
6416
6417 #define OID_SKGE_TRAP_SEN_WAR_LOW 500
6418 #define OID_SKGE_TRAP_SEN_WAR_UPP 501
6419@@ -419,7 +480,6 @@
6420 #define SK_SET_FULL_MIB 5
6421 #define SK_PRESET_FULL_MIB 6
6422
6423-
6424 /*
6425 * Define error numbers and messages for syslog
6426 */
6427@@ -452,7 +512,7 @@
6428 #define SK_PNMI_ERR014 (SK_ERRBASE_PNMI + 14)
6429 #define SK_PNMI_ERR014MSG "Vpd: Cannot read VPD keys"
6430 #define SK_PNMI_ERR015 (SK_ERRBASE_PNMI + 15)
6431-#define SK_PNMI_ERR015MSG "Vpd: Internal array for VPD keys to small"
6432+#define SK_PNMI_ERR015MSG "Vpd: Internal array for VPD keys too small"
6433 #define SK_PNMI_ERR016 (SK_ERRBASE_PNMI + 16)
6434 #define SK_PNMI_ERR016MSG "Vpd: Key string too long"
6435 #define SK_PNMI_ERR017 (SK_ERRBASE_PNMI + 17)
6436@@ -494,9 +554,9 @@
6437 #define SK_PNMI_ERR036 (SK_ERRBASE_PNMI + 36)
6438 #define SK_PNMI_ERR036MSG ""
6439 #define SK_PNMI_ERR037 (SK_ERRBASE_PNMI + 37)
6440-#define SK_PNMI_ERR037MSG "Rlmt: SK_RLMT_MODE_CHANGE event return not 0"
6441+#define SK_PNMI_ERR037MSG "Rlmt: SK_RLMT_MODE_CHANGE event returned not 0"
6442 #define SK_PNMI_ERR038 (SK_ERRBASE_PNMI + 38)
6443-#define SK_PNMI_ERR038MSG "Rlmt: SK_RLMT_PREFPORT_CHANGE event return not 0"
6444+#define SK_PNMI_ERR038MSG "Rlmt: SK_RLMT_PREFPORT_CHANGE event returned not 0"
6445 #define SK_PNMI_ERR039 (SK_ERRBASE_PNMI + 39)
6446 #define SK_PNMI_ERR039MSG "RlmtStat: Unknown OID"
6447 #define SK_PNMI_ERR040 (SK_ERRBASE_PNMI + 40)
6448@@ -514,9 +574,9 @@
6449 #define SK_PNMI_ERR046 (SK_ERRBASE_PNMI + 46)
6450 #define SK_PNMI_ERR046MSG "Monitor: Unknown OID"
6451 #define SK_PNMI_ERR047 (SK_ERRBASE_PNMI + 47)
6452-#define SK_PNMI_ERR047MSG "SirqUpdate: Event function returns not 0"
6453+#define SK_PNMI_ERR047MSG "SirqUpdate: Event function returned not 0"
6454 #define SK_PNMI_ERR048 (SK_ERRBASE_PNMI + 48)
6455-#define SK_PNMI_ERR048MSG "RlmtUpdate: Event function returns not 0"
6456+#define SK_PNMI_ERR048MSG "RlmtUpdate: Event function returned not 0"
6457 #define SK_PNMI_ERR049 (SK_ERRBASE_PNMI + 49)
6458 #define SK_PNMI_ERR049MSG "SkPnmiInit: Invalid size of 'CounterOffset' struct!!"
6459 #define SK_PNMI_ERR050 (SK_ERRBASE_PNMI + 50)
6460@@ -826,23 +886,25 @@
6461 } SK_PNMI_STRUCT_DATA;
6462
6463 #define SK_PNMI_STRUCT_SIZE (sizeof(SK_PNMI_STRUCT_DATA))
6464+
6465+/* The ReturnStatus field must be located before VpdFreeBytes! */
6466 #define SK_PNMI_MIN_STRUCT_SIZE ((unsigned int)(SK_UPTR)\
6467 &(((SK_PNMI_STRUCT_DATA *)0)->VpdFreeBytes))
6468- /*
6469- * ReturnStatus field
6470- * must be located
6471- * before VpdFreeBytes
6472- */
6473
6474 /*
6475 * Various definitions
6476 */
6477+#define SK_PNMI_EVT_TIMER_CHECK 28125000L /* 28125 ms */
6478+
6479+#define SK_PNMI_VCT_TIMER_CHECK 4000000L /* 4 sec. */
6480+
6481 #define SK_PNMI_MAX_PROTOS 3
6482
6483-#define SK_PNMI_CNT_NO 66 /* Must have the value of the enum
6484- * SK_PNMI_MAX_IDX. Define SK_PNMI_CHECK
6485- * for check while init phase 1
6486- */
6487+/*
6488+ * SK_PNMI_CNT_NO must have the value of the enum SK_PNMI_MAX_IDX.
6489+ * Define SK_PNMI_CHECK to check this during init level SK_INIT_IO.
6490+ */
6491+#define SK_PNMI_CNT_NO 66
6492
6493 /*
6494 * Estimate data structure
6495@@ -856,14 +918,6 @@
6496
6497
6498 /*
6499- * VCT timer data structure
6500- */
6501-typedef struct s_VctTimer {
6502- SK_TIMER VctTimer;
6503-} SK_PNMI_VCT_TIMER;
6504-
6505-
6506-/*
6507 * PNMI specific adapter context structure
6508 */
6509 typedef struct s_PnmiPort {
6510@@ -933,12 +987,13 @@
6511 unsigned int TrapQueueEnd;
6512 unsigned int TrapBufPad;
6513 unsigned int TrapUnique;
6514- SK_U8 VctStatus[SK_MAX_MACS];
6515- SK_PNMI_VCT VctBackup[SK_MAX_MACS];
6516- SK_PNMI_VCT_TIMER VctTimeout[SK_MAX_MACS];
6517+ SK_U8 VctStatus[SK_MAX_MACS];
6518+ SK_PNMI_VCT VctBackup[SK_MAX_MACS];
6519+ SK_TIMER VctTimeout[SK_MAX_MACS];
6520 #ifdef SK_DIAG_SUPPORT
6521 SK_U32 DiagAttached;
6522 #endif /* SK_DIAG_SUPPORT */
6523+ SK_BOOL VpdKeyReadError;
6524 } SK_PNMI;
6525
6526
6527@@ -946,6 +1001,10 @@
6528 * Function prototypes
6529 */
6530 extern int SkPnmiInit(SK_AC *pAC, SK_IOC IoC, int Level);
6531+extern int SkPnmiGetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void* pBuf,
6532+ unsigned int* pLen, SK_U32 Instance, SK_U32 NetIndex);
6533+extern int SkPnmiPreSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id,
6534+ void* pBuf, unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex);
6535 extern int SkPnmiSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void* pBuf,
6536 unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex);
6537 extern int SkPnmiGetStruct(SK_AC *pAC, SK_IOC IoC, void* pBuf,
6538diff -ruN linux/drivers/net/sk98lin/h/skgesirq.h linux-new/drivers/net/sk98lin/h/skgesirq.h
6539--- linux/drivers/net/sk98lin/h/skgesirq.h 2007-01-02 23:21:17.000000000 +0100
6540+++ linux-new/drivers/net/sk98lin/h/skgesirq.h 2006-10-13 11:18:49.000000000 +0200
6541@@ -2,23 +2,24 @@
6542 *
6543 * Name: skgesirq.h
6544 * Project: Gigabit Ethernet Adapters, Common Modules
6545- * Version: $Revision$
6546- * Date: $Date$
6547- * Purpose: SK specific Gigabit Ethernet special IRQ functions
6548+ * Version: $Revision$
6549+ * Date: $Date$
6550+ * Purpose: Gigabit Ethernet special IRQ functions
6551 *
6552 ******************************************************************************/
6553
6554 /******************************************************************************
6555 *
6556+ * LICENSE:
6557 * (C)Copyright 1998-2002 SysKonnect.
6558- * (C)Copyright 2002-2003 Marvell.
6559+ * (C)Copyright 2002-2005 Marvell.
6560 *
6561 * This program is free software; you can redistribute it and/or modify
6562 * it under the terms of the GNU General Public License as published by
6563 * the Free Software Foundation; either version 2 of the License, or
6564 * (at your option) any later version.
6565- *
6566 * The information in this file is provided "AS IS" without warranty.
6567+ * /LICENSE
6568 *
6569 ******************************************************************************/
6570
6571@@ -26,9 +27,9 @@
6572 #define _INC_SKGESIRQ_H_
6573
6574 /* Define return codes of SkGePortCheckUp and CheckShort */
6575-#define SK_HW_PS_NONE 0 /* No action needed */
6576-#define SK_HW_PS_RESTART 1 /* Restart needed */
6577-#define SK_HW_PS_LINK 2 /* Link Up actions needed */
6578+#define SK_HW_PS_NONE 0 /* No action needed */
6579+#define SK_HW_PS_RESTART 1 /* Restart needed */
6580+#define SK_HW_PS_LINK 2 /* Link Up actions needed */
6581
6582 /*
6583 * Define the Event the special IRQ/INI module can handle
6584@@ -44,10 +45,10 @@
6585 #define SK_HWEV_SET_SPEED 9 /* Set Link Speed by PNMI */
6586 #define SK_HWEV_HALFDUP_CHK 10 /* Half Duplex Hangup Workaround */
6587
6588-#define SK_WA_ACT_TIME (5000000UL) /* 5 sec */
6589-#define SK_WA_INA_TIME (100000UL) /* 100 msec */
6590+#define SK_WA_ACT_TIME 1000000UL /* 1000 msec (1 sec) */
6591+#define SK_WA_INA_TIME 100000UL /* 100 msec */
6592
6593-#define SK_HALFDUP_CHK_TIME (10000UL) /* 10 msec */
6594+#define SK_HALFDUP_CHK_TIME 10000UL /* 10 msec */
6595
6596 /*
6597 * Define the error numbers and messages
6598@@ -75,9 +76,9 @@
6599 #define SKERR_SIRQ_E011 (SKERR_SIRQ_E010+1)
6600 #define SKERR_SIRQ_E011MSG "CHECK failure XA2"
6601 #define SKERR_SIRQ_E012 (SKERR_SIRQ_E011+1)
6602-#define SKERR_SIRQ_E012MSG "unexpected IRQ Master error"
6603+#define SKERR_SIRQ_E012MSG "Unexpected IRQ Master error"
6604 #define SKERR_SIRQ_E013 (SKERR_SIRQ_E012+1)
6605-#define SKERR_SIRQ_E013MSG "unexpected IRQ Status error"
6606+#define SKERR_SIRQ_E013MSG "Unexpected IRQ Status error"
6607 #define SKERR_SIRQ_E014 (SKERR_SIRQ_E013+1)
6608 #define SKERR_SIRQ_E014MSG "Parity error on RAM (read)"
6609 #define SKERR_SIRQ_E015 (SKERR_SIRQ_E014+1)
6610@@ -102,9 +103,35 @@
6611 #define SKERR_SIRQ_E024MSG "FIFO overflow error"
6612 #define SKERR_SIRQ_E025 (SKERR_SIRQ_E024+1)
6613 #define SKERR_SIRQ_E025MSG "2 Pair Downshift detected"
6614+#define SKERR_SIRQ_E026 (SKERR_SIRQ_E025+1)
6615+#define SKERR_SIRQ_E026MSG "Uncorrectable PCI Express error"
6616+#define SKERR_SIRQ_E027 (SKERR_SIRQ_E026+1)
6617+#define SKERR_SIRQ_E027MSG "PCI Bus Abort detected"
6618+#define SKERR_SIRQ_E028 (SKERR_SIRQ_E027+1)
6619+#define SKERR_SIRQ_E028MSG "Parity error on RAM 1 (read)"
6620+#define SKERR_SIRQ_E029 (SKERR_SIRQ_E028+1)
6621+#define SKERR_SIRQ_E029MSG "Parity error on RAM 1 (write)"
6622+#define SKERR_SIRQ_E030 (SKERR_SIRQ_E029+1)
6623+#define SKERR_SIRQ_E030MSG "Parity error on RAM 2 (read)"
6624+#define SKERR_SIRQ_E031 (SKERR_SIRQ_E030+1)
6625+#define SKERR_SIRQ_E031MSG "Parity error on RAM 2 (write)"
6626+#define SKERR_SIRQ_E032 (SKERR_SIRQ_E031+1)
6627+#define SKERR_SIRQ_E032MSG "TCP segmentation error async. queue 1"
6628+#define SKERR_SIRQ_E033 (SKERR_SIRQ_E032+1)
6629+#define SKERR_SIRQ_E033MSG "TCP segmentation error sync. queue 1"
6630+#define SKERR_SIRQ_E034 (SKERR_SIRQ_E033+1)
6631+#define SKERR_SIRQ_E034MSG "TCP segmentation error async. queue 2"
6632+#define SKERR_SIRQ_E035 (SKERR_SIRQ_E034+1)
6633+#define SKERR_SIRQ_E035MSG "TCP segmentation error sync. queue 2"
6634+#define SKERR_SIRQ_E036 (SKERR_SIRQ_E035+1)
6635+#define SKERR_SIRQ_E036MSG "CHECK failure polling unit"
6636
6637 extern void SkGeSirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus);
6638 extern int SkGeSirqEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Para);
6639+extern void SkHWLinkUp(SK_AC *pAC, SK_IOC IoC, int Port);
6640 extern void SkHWLinkDown(SK_AC *pAC, SK_IOC IoC, int Port);
6641+extern void SkGeYuSirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus);
6642+extern void SkYuk2SirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus);
6643
6644 #endif /* _INC_SKGESIRQ_H_ */
6645+
6646diff -ruN linux/drivers/net/sk98lin/h/skgespi.h linux-new/drivers/net/sk98lin/h/skgespi.h
6647--- linux/drivers/net/sk98lin/h/skgespi.h 1970-01-01 01:00:00.000000000 +0100
6648+++ linux-new/drivers/net/sk98lin/h/skgespi.h 2006-10-13 11:18:49.000000000 +0200
6649@@ -0,0 +1,246 @@
6650+/******************************************************************************
6651+ *
6652+ * Name: skspi.h
6653+ * Project: Flash Programmer, Manufacturing and Diagnostic Tools
6654+ * Version: $Revision$
6655+ * Date: $Date$
6656+ * Purpose: Contains SPI-Flash EEPROM specific definitions and constants
6657+ *
6658+ ******************************************************************************/
6659+
6660+/******************************************************************************
6661+ *
6662+ * (C)Copyright 1998-2002 SysKonnect
6663+ * (C)Copyright 2002-2003 Marvell
6664+ *
6665+ * THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF SYSKONNECT
6666+ * The copyright notice above does not evidence any
6667+ * actual or intended publication of such source code.
6668+ *
6669+ * This Module contains Proprietary Information of SysKonnect
6670+ * and should be treated as Confidential.
6671+ *
6672+ * The information in this file is provided for the exclusive use of
6673+ * the licensees of SysKonnect.
6674+ * Such users have the right to use, modify, and incorporate this code
6675+ * into products for purposes authorized by the license agreement
6676+ * provided they include this notice and the associated copyright notice
6677+ * with any such product.
6678+ * The information in this file is provided "AS IS" without warranty.
6679+ *
6680+ ******************************************************************************/
6681+
6682+#define __INC_SKSPI_H
6683+
6684+/* SPI registers */
6685+// CHIP_IDs should be defined in skgehw.h
6686+#ifndef B2_CHIP_ID
6687+#define B2_CHIP_ID 0x011b /* Chip Identification Number */
6688+#endif
6689+
6690+#ifndef CHIP_ID_GENESIS
6691+#define CHIP_ID_GENESIS 0x0a /* Chip ID for GENESIS */
6692+#endif
6693+
6694+#ifndef CHIP_ID_YUKON
6695+#define CHIP_ID_YUKON 0xb0 /* Chip ID for YUKON */
6696+#endif
6697+
6698+#ifndef CHIP_ID_YUKON_LITE
6699+#define CHIP_ID_YUKON_LITE 0xb1 /* Chip ID for YUKON-Lite (Rev. A1) */
6700+#endif
6701+
6702+#ifndef CHIP_ID_YUKON_LP
6703+#define CHIP_ID_YUKON_LP 0xb2 /* Chip ID for YUKON-LP */
6704+#endif
6705+
6706+#ifndef CHIP_ID_YUKON_XL
6707+#define CHIP_ID_YUKON_XL 0xb3 /* Chip ID for YUKON-2 XL */
6708+#endif
6709+
6710+#ifndef CHIP_ID_YUKON_EC
6711+#define CHIP_ID_YUKON_EC 0xb6 /* Chip ID for YUKON-2 EC */
6712+#endif
6713+
6714+#define SPI_ADR_REG1 0x0120 /* VPD low addr, SPI loader start addr */
6715+#define SPI_ADR_REG2 0x0124 /* VPD high addr, PiG loader start addr */
6716+#define SPI_CTRL_REG 0x0128 /* SPI control & status register */
6717+
6718+#define B2_TST_REG1 0x0158 /* Test control register */
6719+
6720+/* SPI commands and constants */
6721+
6722+#define SPI_PATTERN 0xffffffffL /* Write value for SPI identification */
6723+#define SPI_COMP_MASK 0xfffe0000L /* Compare Mask for SPI identification */
6724+
6725+#define SPI_VPD_MIN 0x0001f800L /* Min Eprom addr for access via VPD port */
6726+#define SPI_VPD_MAX 0xfffff000L /* Max Eprom addr for access via VPD port */
6727+
6728+#define SPI_LSECT_OFF 0x18000L /* Offset of last sector in SPI eprom */
6729+#define SPI_CONF_OFF 0x1c000L /* Offset of config space in SPI eprom */
6730+
6731+#define SPI_PIG_OFF 0x1f000L /* Plug-In-Go (PiG) Config space */
6732+#define SPI_NOC_OFF 0x1f800L /* Normal Oper. Config (NOC) space */
6733+#define SPI_VPD_OFF 0x1c000L /* Vital Product Data (VPD) space */
6734+#define SPI_PET_OFF 0x1d000L /* Pet Frames space */
6735+
6736+#define SPI_CHIP_SIZE 0x20000L /* Size of whole SPI eprom */
6737+#define SPI_SECT_SIZE 0x8000L /* Size of a sector in SPI eprom */
6738+
6739+#define SPI_CONF_SIZE 0x4000L /* Size of config area in SPI eprom */
6740+#define SPI_PIG_SIZE 0x0800L /* Size of PiG area in SPI eprom */
6741+#define SPI_NOC_SIZE 0x0800L /* Size of NOC area in SPI eprom */
6742+#define SPI_VPD_SIZE 0x0100L /* Size of VPD area in SPI eprom */
6743+#define SPI_PET_SIZE 0x2000L /* Size of PET area in SPI eprom */
6744+
6745+#define SPI_SECT_ERASE 0x00008000L /* Sector erase command */
6746+#define SPI_CHIP_ERASE 0x00001000L /* Chip erase command */
6747+#define SPI_VPD_MAP 0x00080000L /* VPD to Eprom mapping flag */
6748+#define SPI_TIMER_SET 5 /* SPI timeout value (sec.) */
6749+#define SPI_TIMEOUT 0 /* Timeout check flag */
6750+#define SPI_READ 1 /* Read flag for spi_flash_manage() */
6751+#define SPI_VERIFY 2 /* Verify flag for spi_flash_manage() */
6752+#define SPI_WRITE 3 /* Write flag for spi_flash_manage() */
6753+
6754+/* VPD regs from PCI config reg. file mapped to control reg. file */
6755+
6756+#define VPD_ADR_REG 0x03d2 /* VPD address register in config file */
6757+#define VPD_DATA_PORT 0x03d4 /* VPD data port in configuration file */
6758+#define VPD_FLAG_MASK 0x8000 /* VPD read-write flag */
6759+
6760+#define FT_SPI_UNKNOWN (-1)
6761+#define FT_SPI 3 /* Flash type */
6762+#define FT_SPI_Y2 4 /* Yukon 2/EC SPI flash */
6763+
6764+/********************************************************************************
6765+ * Yukon 2/EC definitions and macros
6766+ ********************************************************************************/
6767+
6768+/* SPI EPROM CONTROL REGISTER */
6769+#define SPI_Y2_CONTROL_REG 0x60
6770+/* SPI EPROM ADDRESS REGISTER */
6771+#define SPI_Y2_ADDRESS_REG 0x64
6772+/* SPI EPROM DATA REGISTER */
6773+#define SPI_Y2_DATA_REG 0x68
6774+/* SPI EPROM VENDOR-/DEVICE-ID REGISTER */
6775+#define SPI_Y2_VENDOR_DEVICE_ID_REG 0x6c
6776+/* SPI EPROM FIRST OPCODE REGISTER */
6777+#define SPI_Y2_OPCODE_REG1 0x78
6778+/* SPI EPROM SECOND OPCODE REGISTER */
6779+#define SPI_Y2_OPCODE_REG2 0x7c
6780+
6781+/* SPI EPROM READ INSTRUCTION */
6782+#define SPI_Y2_RD (0x09L<<16)
6783+/* SPI EPROM READ ID INSTRUCTION */
6784+#define SPI_Y2_RDID (0x0AL<<16)
6785+/* SPI EPROM READ STATUS REGISTER INSTRUCTION */
6786+#define SPI_Y2_RDST (0x0BL<<16)
6787+/* SPI EPROM WRITE ENABLE INSTRUCTION */
6788+#define SPI_Y2_WEN (0x0CL<<16)
6789+/* SPI EPROM WRITE INSTRUCTION */
6790+#define SPI_Y2_WR (0x0DL<<16)
6791+/* SPI EPROM SECTOR ERASE INSTRUCTION */
6792+#define SPI_Y2_SERS (0x0EL<<16)
6793+/* SPI EPROM CHIP ERASE INSTRUCTION */
6794+#define SPI_Y2_CERS (0x0FL<<16)
6795+/* SPI EPROM command mask */
6796+#define SPI_Y2_CMD_MASK (0x07L<<16)
6797+
6798+/* SPI flash read ID protocol */
6799+#define SPI_Y2_RDID_PROT (0x01L<<28)
6800+
6801+/* SPI flash VPD mapping enable */
6802+#define SPI_Y2_VPD_ENABLE (0x01L<<29)
6803+
6804+/* SPI EPROM BUSY CHECK */
6805+#define SPI_Y2_IS_BUSY(w) ((w)&(1L<<30))
6806+#define SPI_Y2_IS_BUSY_WR(w) ((w)&(1))
6807+
6808+#define SPI_Y2_MAN_ID_MASK 0xff00
6809+#define SPI_Y2_DEV_ID_MASK 0x00ff
6810+
6811+/* SPI flash manufacturer ID's */
6812+#define SPI_MAN_ID_ATMEL 0x1f
6813+#define SPI_MAN_ID_SST 0xbf
6814+#define SPI_MAN_ID_ST_M25P20 0x11
6815+#define SPI_MAN_ID_ST_M25P10 0x10
6816+
6817+/* wait for SPI EPROM to finish write/erase operation */
6818+#define SPI_Y2_WAIT_SE_FINISH_WR() { \
6819+ unsigned long stat=1; \
6820+ SPI_Y2_WAIT_SE_FINISH_CMD(); \
6821+ /* wait for write to finish or timeout */ \
6822+ spi_timer(SPI_TIMER_SET); \
6823+ while( SPI_Y2_IS_BUSY_WR(stat) ){ \
6824+ if (spi_timer(SPI_TIMEOUT)) { \
6825+ break; \
6826+ } \
6827+ spi_out32(SPI_Y2_CONTROL_REG, SPI_Y2_RDST); \
6828+ SPI_Y2_WAIT_SE_FINISH_CMD() \
6829+ spi_in32(SPI_Y2_CONTROL_REG, &stat); \
6830+ } \
6831+}
6832+
6833+/* wait for SPI EPROM to finish command */
6834+#define SPI_Y2_WAIT_SE_FINISH_CMD() { \
6835+ unsigned long stat=(1L<<30); \
6836+ /* wait for command to finish */ \
6837+ spi_timer(SPI_TIMER_SET); \
6838+ while( SPI_Y2_IS_BUSY(stat) ){ \
6839+ if (spi_timer(SPI_TIMEOUT)) { \
6840+ break; \
6841+ } \
6842+ spi_in32(SPI_Y2_CONTROL_REG, &stat); \
6843+ } \
6844+}
6845+
6846+#if (defined Core || defined DJGPP || !defined MSDOS)
6847+#define huge
6848+#endif /* Core || DJGPP || !MSDOS */
6849+
6850+/* function prototypes */
6851+
6852+int flash_check_spi( unsigned long *FlashSize );
6853+
6854+int spi_flash_erase(
6855+ unsigned long off,
6856+ unsigned long len);
6857+
6858+int spi_flash_manage(
6859+ unsigned char *data,
6860+ unsigned long off,
6861+ unsigned long len,
6862+ int flag);
6863+
6864+int spi_vpd_transfer(
6865+ char *buf,
6866+ int addr,
6867+ int len,
6868+ int dir);
6869+
6870+int spi_get_pig(
6871+ unsigned char *data,
6872+ unsigned long len);
6873+
6874+int spi_get_noc(
6875+ unsigned char *data,
6876+ unsigned long len);
6877+
6878+int spi_update_pig(
6879+ unsigned char *data,
6880+ unsigned long len);
6881+
6882+int spi_update_noc(
6883+ unsigned char *data,
6884+ unsigned long len);
6885+
6886+int spi_update_pet(
6887+ unsigned char *data,
6888+ unsigned long len);
6889+
6890+void spi_yuk2_write_enable(void);
6891+void spi_yuk2_sst_clear_write_protection(void);
6892+void spi_yuk2_erase_chip(void);
6893+unsigned short spi_yuk2_read_chip_id(void);
6894+int spi_yuk2_get_dev_index(void);
6895+
6896diff -ruN linux/drivers/net/sk98lin/h/skgetwsi.h linux-new/drivers/net/sk98lin/h/skgetwsi.h
6897--- linux/drivers/net/sk98lin/h/skgetwsi.h 1970-01-01 01:00:00.000000000 +0100
6898+++ linux-new/drivers/net/sk98lin/h/skgetwsi.h 2006-10-13 11:18:49.000000000 +0200
6899@@ -0,0 +1,243 @@
6900+/******************************************************************************
6901+ *
6902+ * Name: skgetwsi.h
6903+ * Project: Gigabit Ethernet Adapters, TWSI-Module
6904+ * Version: $Revision$
6905+ * Date: $Date$
6906+ * Purpose: Special defines for TWSI
6907+ *
6908+ ******************************************************************************/
6909+
6910+/******************************************************************************
6911+ *
6912+ * LICENSE:
6913+ * (C)Copyright 1998-2002 SysKonnect.
6914+ * (C)Copyright 2002-2004 Marvell.
6915+ *
6916+ * This program is free software; you can redistribute it and/or modify
6917+ * it under the terms of the GNU General Public License as published by
6918+ * the Free Software Foundation; either version 2 of the License, or
6919+ * (at your option) any later version.
6920+ * The information in this file is provided "AS IS" without warranty.
6921+ * /LICENSE
6922+ *
6923+ ******************************************************************************/
6924+
6925+/*
6926+ * SKGETWSI.H contains all SK-98xx specific defines for the TWSI handling
6927+ */
6928+
6929+#ifndef _INC_SKGETWSI_H_
6930+#define _INC_SKGETWSI_H_
6931+
6932+/*
6933+ * Macros to access the B2_I2C_CTRL
6934+ */
6935+#define SK_I2C_CTL(IoC, flag, dev, dev_size, reg, burst) \
6936+ SK_OUT32(IoC, B2_I2C_CTRL,\
6937+ (flag ? 0x80000000UL : 0x0L) | \
6938+ (((SK_U32)reg << 16) & I2C_ADDR) | \
6939+ (((SK_U32)dev << 9) & I2C_DEV_SEL) | \
6940+ (dev_size & I2C_DEV_SIZE) | \
6941+ ((burst << 4) & I2C_BURST_LEN))
6942+
6943+#define SK_I2C_STOP(IoC) { \
6944+ SK_U32 I2cCtrl; \
6945+ SK_IN32(IoC, B2_I2C_CTRL, &I2cCtrl); \
6946+ SK_OUT32(IoC, B2_I2C_CTRL, I2cCtrl | I2C_STOP); \
6947+}
6948+
6949+#define SK_I2C_GET_CTL(IoC, pI2cCtrl) SK_IN32(IoC, B2_I2C_CTRL, pI2cCtrl)
6950+
6951+/*
6952+ * Macros to access the TWSI SW Registers
6953+ */
6954+#define SK_I2C_SET_BIT(IoC, SetBits) { \
6955+ SK_U8 OrgBits; \
6956+ SK_IN8(IoC, B2_I2C_SW, &OrgBits); \
6957+ SK_OUT8(IoC, B2_I2C_SW, OrgBits | (SK_U8)(SetBits)); \
6958+}
6959+
6960+#define SK_I2C_CLR_BIT(IoC, ClrBits) { \
6961+ SK_U8 OrgBits; \
6962+ SK_IN8(IoC, B2_I2C_SW, &OrgBits); \
6963+ SK_OUT8(IoC, B2_I2C_SW, OrgBits & ~((SK_U8)(ClrBits))); \
6964+}
6965+
6966+#define SK_I2C_GET_SW(IoC, pI2cSw) SK_IN8(IoC, B2_I2C_SW, pI2cSw)
6967+
6968+/*
6969+ * define the possible sensor states
6970+ */
6971+#define SK_SEN_IDLE 0 /* Idle: sensor not read */
6972+#define SK_SEN_VALUE 1 /* Value Read cycle */
6973+#define SK_SEN_VALEXT 2 /* Extended Value Read cycle */
6974+
6975+/*
6976+ * Conversion factor to convert read Voltage sensor to milli Volt
6977+ * Conversion factor to convert read Temperature sensor to 10th degree Celsius
6978+ */
6979+#define SK_LM80_VT_LSB 22 /* 22mV LSB resolution */
6980+#define SK_LM80_TEMP_LSB 10 /* 1 degree LSB resolution */
6981+#define SK_LM80_TEMPEXT_LSB 5 /* 0.5 degree LSB resolution for ext. val. */
6982+
6983+/*
6984+ * formula: counter = (22500*60)/(rpm * divisor * pulses/2)
6985+ * assuming: 6500rpm, 4 pulses, divisor 1
6986+ */
6987+#define SK_LM80_FAN_FAKTOR ((22500L*60)/(1*2))
6988+
6989+/*
6990+ * Define sensor management data
6991+ * Maximum is reached on Genesis copper dual port and Yukon-64
6992+ * Board specific maximum is in pAC->I2c.MaxSens
6993+ */
6994+#define SK_MAX_SENSORS 8 /* maximal no. of installed sensors */
6995+#define SK_MIN_SENSORS 5 /* minimal no. of installed sensors */
6996+
6997+/*
6998+ * To watch the state machine (SM) use the timer in two ways
6999+ * instead of one as hitherto
7000+ */
7001+#define SK_TIMER_WATCH_SM 0 /* Watch the SM to finish in a spec. time */
7002+#define SK_TIMER_NEW_GAUGING 1 /* Start a new gauging when timer expires */
7003+
7004+/*
7005+ * Defines for the individual thresholds
7006+ */
7007+
7008+#define C_PLUS_20 120 / 100
7009+#define C_PLUS_15 115 / 100
7010+#define C_PLUS_10 110 / 100
7011+#define C_PLUS_5 105 / 100
7012+#define C_MINUS_5 95 / 100
7013+#define C_MINUS_10 90 / 100
7014+#define C_MINUS_15 85 / 100
7015+
7016+/* Temperature sensor */
7017+#define SK_SEN_TEMP_HIGH_ERR 800 /* Temperature High Err Threshold */
7018+#define SK_SEN_TEMP_HIGH_WARN 700 /* Temperature High Warn Threshold */
7019+#define SK_SEN_TEMP_LOW_WARN 100 /* Temperature Low Warn Threshold */
7020+#define SK_SEN_TEMP_LOW_ERR 0 /* Temperature Low Err Threshold */
7021+
7022+/* VCC which should be 5 V */
7023+#define SK_SEN_PCI_5V_HIGH_ERR 5588 /* Voltage PCI High Err Threshold */
7024+#define SK_SEN_PCI_5V_HIGH_WARN 5346 /* Voltage PCI High Warn Threshold */
7025+#define SK_SEN_PCI_5V_LOW_WARN 4664 /* Voltage PCI Low Warn Threshold */
7026+#define SK_SEN_PCI_5V_LOW_ERR 4422 /* Voltage PCI Low Err Threshold */
7027+
7028+/*
7029+ * VIO may be 5 V or 3.3 V. Initialization takes two parts:
7030+ * 1. Initialize lowest lower limit and highest higher limit.
7031+ * 2. After the first value is read correct the upper or the lower limit to
7032+ * the appropriate C constant.
7033+ *
7034+ * Warning limits are +-5% of the exepected voltage.
7035+ * Error limits are +-10% of the expected voltage.
7036+ */
7037+
7038+/* Bug fix AF: 16.Aug.2001: Correct the init base of LM80 sensor */
7039+
7040+#define SK_SEN_PCI_IO_5V_HIGH_ERR 5566 /* + 10% V PCI-IO High Err Threshold */
7041+#define SK_SEN_PCI_IO_5V_HIGH_WARN 5324 /* + 5% V PCI-IO High Warn Threshold */
7042+ /* 5000 mVolt */
7043+#define SK_SEN_PCI_IO_5V_LOW_WARN 4686 /* - 5% V PCI-IO Low Warn Threshold */
7044+#define SK_SEN_PCI_IO_5V_LOW_ERR 4444 /* - 10% V PCI-IO Low Err Threshold */
7045+
7046+#define SK_SEN_PCI_IO_RANGE_LIMITER 4000 /* 4000 mV range delimiter */
7047+
7048+/* correction values for the second pass */
7049+#define SK_SEN_PCI_IO_3V3_HIGH_ERR 3850 /* + 15% V PCI-IO High Err Threshold */
7050+#define SK_SEN_PCI_IO_3V3_HIGH_WARN 3674 /* + 10% V PCI-IO High Warn Threshold */
7051+ /* 3300 mVolt */
7052+#define SK_SEN_PCI_IO_3V3_LOW_WARN 2926 /* - 10% V PCI-IO Low Warn Threshold */
7053+#define SK_SEN_PCI_IO_3V3_LOW_ERR 2772 /* - 15% V PCI-IO Low Err Threshold */
7054+
7055+/*
7056+ * VDD voltage
7057+ */
7058+#define SK_SEN_VDD_HIGH_ERR 3630 /* Voltage ASIC High Err Threshold */
7059+#define SK_SEN_VDD_HIGH_WARN 3476 /* Voltage ASIC High Warn Threshold */
7060+#define SK_SEN_VDD_LOW_WARN 3146 /* Voltage ASIC Low Warn Threshold */
7061+#define SK_SEN_VDD_LOW_ERR 2970 /* Voltage ASIC Low Err Threshold */
7062+
7063+/*
7064+ * PHY PLL 3V3 voltage
7065+ */
7066+#define SK_SEN_PLL_3V3_HIGH_ERR 3630 /* Voltage PMA High Err Threshold */
7067+#define SK_SEN_PLL_3V3_HIGH_WARN 3476 /* Voltage PMA High Warn Threshold */
7068+#define SK_SEN_PLL_3V3_LOW_WARN 3146 /* Voltage PMA Low Warn Threshold */
7069+#define SK_SEN_PLL_3V3_LOW_ERR 2970 /* Voltage PMA Low Err Threshold */
7070+
7071+/*
7072+ * VAUX (YUKON only)
7073+ */
7074+#define SK_SEN_VAUX_3V3_VAL 3300 /* Voltage VAUX 3.3 Volt */
7075+
7076+#define SK_SEN_VAUX_3V3_HIGH_ERR (SK_I32)(SK_SEN_VAUX_3V3_VAL * C_PLUS_10)
7077+#define SK_SEN_VAUX_3V3_HIGH_WARN (SK_I32)(SK_SEN_VAUX_3V3_VAL * C_PLUS_5)
7078+#define SK_SEN_VAUX_3V3_LOW_WARN (SK_I32)(SK_SEN_VAUX_3V3_VAL * C_MINUS_5)
7079+#define SK_SEN_VAUX_3V3_LOW_ERR (SK_I32)(SK_SEN_VAUX_3V3_VAL * C_MINUS_10)
7080+
7081+#define SK_SEN_VAUX_RANGE_LIMITER 1000 /* 1000 mV range delimiter */
7082+
7083+/*
7084+ * PHY 2V5 voltage
7085+ */
7086+#define SK_SEN_PHY_2V5_VAL 2500 /* Voltage PHY 2.5 Volt */
7087+
7088+#define SK_SEN_PHY_2V5_HIGH_ERR (SK_I32)(SK_SEN_PHY_2V5_VAL * C_PLUS_10)
7089+#define SK_SEN_PHY_2V5_HIGH_WARN (SK_I32)(SK_SEN_PHY_2V5_VAL * C_PLUS_5)
7090+#define SK_SEN_PHY_2V5_LOW_WARN (SK_I32)(SK_SEN_PHY_2V5_VAL * C_MINUS_5)
7091+#define SK_SEN_PHY_2V5_LOW_ERR (SK_I32)(SK_SEN_PHY_2V5_VAL * C_MINUS_10)
7092+
7093+/*
7094+ * ASIC Core 1V5 voltage (YUKON only)
7095+ */
7096+#define SK_SEN_CORE_1V5_VAL 1500 /* Voltage ASIC Core 1.5 Volt */
7097+
7098+#define SK_SEN_CORE_1V5_HIGH_ERR (SK_I32)(SK_SEN_CORE_1V5_VAL * C_PLUS_10)
7099+#define SK_SEN_CORE_1V5_HIGH_WARN (SK_I32)(SK_SEN_CORE_1V5_VAL * C_PLUS_5)
7100+#define SK_SEN_CORE_1V5_LOW_WARN (SK_I32)(SK_SEN_CORE_1V5_VAL * C_MINUS_5)
7101+#define SK_SEN_CORE_1V5_LOW_ERR (SK_I32)(SK_SEN_CORE_1V5_VAL * C_MINUS_10)
7102+
7103+/*
7104+ * ASIC Core 1V2 (1V3) voltage (YUKON-2 only)
7105+ */
7106+#define SK_SEN_CORE_1V2_VAL 1200 /* Voltage ASIC Core 1.2 Volt */
7107+
7108+#define SK_SEN_CORE_1V2_HIGH_ERR (SK_I32)(SK_SEN_CORE_1V2_VAL * C_PLUS_20)
7109+#define SK_SEN_CORE_1V2_HIGH_WARN (SK_I32)(SK_SEN_CORE_1V2_VAL * C_PLUS_15)
7110+#define SK_SEN_CORE_1V2_LOW_WARN (SK_I32)(SK_SEN_CORE_1V2_VAL * C_MINUS_5)
7111+#define SK_SEN_CORE_1V2_LOW_ERR (SK_I32)(SK_SEN_CORE_1V2_VAL * C_MINUS_10)
7112+
7113+#define SK_SEN_CORE_1V3_VAL 1300 /* Voltage ASIC Core 1.3 Volt */
7114+
7115+#define SK_SEN_CORE_1V3_HIGH_ERR (SK_I32)(SK_SEN_CORE_1V3_VAL * C_PLUS_15)
7116+#define SK_SEN_CORE_1V3_HIGH_WARN (SK_I32)(SK_SEN_CORE_1V3_VAL * C_PLUS_10)
7117+#define SK_SEN_CORE_1V3_LOW_WARN (SK_I32)(SK_SEN_CORE_1V3_VAL * C_MINUS_5)
7118+#define SK_SEN_CORE_1V3_LOW_ERR (SK_I32)(SK_SEN_CORE_1V3_VAL * C_MINUS_10)
7119+
7120+/*
7121+ * FAN 1 speed
7122+ */
7123+/* assuming: 6500rpm +-15%, 4 pulses,
7124+ * warning at: 80 %
7125+ * error at: 70 %
7126+ * no upper limit
7127+ */
7128+#define SK_SEN_FAN_HIGH_ERR 20000 /* FAN Speed High Err Threshold */
7129+#define SK_SEN_FAN_HIGH_WARN 20000 /* FAN Speed High Warn Threshold */
7130+#define SK_SEN_FAN_LOW_WARN 5200 /* FAN Speed Low Warn Threshold */
7131+#define SK_SEN_FAN_LOW_ERR 4550 /* FAN Speed Low Err Threshold */
7132+
7133+/*
7134+ * Some Voltages need dynamic thresholds
7135+ */
7136+#define SK_SEN_DYN_INIT_NONE 0 /* No dynamic init of thresholds */
7137+#define SK_SEN_DYN_INIT_PCI_IO 10 /* Init PCI-IO with new thresholds */
7138+#define SK_SEN_DYN_INIT_VAUX 11 /* Init VAUX with new thresholds */
7139+
7140+extern int SkLm80ReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen);
7141+#endif /* n_INC_SKGETWSI_H */
7142+
7143diff -ruN linux/drivers/net/sk98lin/h/ski2c.h linux-new/drivers/net/sk98lin/h/ski2c.h
7144--- linux/drivers/net/sk98lin/h/ski2c.h 2007-01-02 23:21:17.000000000 +0100
7145+++ linux-new/drivers/net/sk98lin/h/ski2c.h 1970-01-01 01:00:00.000000000 +0100
7146@@ -1,174 +0,0 @@
7147-/******************************************************************************
7148- *
7149- * Name: ski2c.h
7150- * Project: Gigabit Ethernet Adapters, TWSI-Module
7151- * Version: $Revision$
7152- * Date: $Date$
7153- * Purpose: Defines to access Voltage and Temperature Sensor
7154- *
7155- ******************************************************************************/
7156-
7157-/******************************************************************************
7158- *
7159- * (C)Copyright 1998-2002 SysKonnect.
7160- * (C)Copyright 2002-2003 Marvell.
7161- *
7162- * This program is free software; you can redistribute it and/or modify
7163- * it under the terms of the GNU General Public License as published by
7164- * the Free Software Foundation; either version 2 of the License, or
7165- * (at your option) any later version.
7166- *
7167- * The information in this file is provided "AS IS" without warranty.
7168- *
7169- ******************************************************************************/
7170-
7171-/*
7172- * SKI2C.H contains all I2C specific defines
7173- */
7174-
7175-#ifndef _SKI2C_H_
7176-#define _SKI2C_H_
7177-
7178-typedef struct s_Sensor SK_SENSOR;
7179-
7180-#include "h/skgei2c.h"
7181-
7182-/*
7183- * Define the I2C events.
7184- */
7185-#define SK_I2CEV_IRQ 1 /* IRQ happened Event */
7186-#define SK_I2CEV_TIM 2 /* Timeout event */
7187-#define SK_I2CEV_CLEAR 3 /* Clear MIB Values */
7188-
7189-/*
7190- * Define READ and WRITE Constants.
7191- */
7192-#define I2C_READ 0
7193-#define I2C_WRITE 1
7194-#define I2C_BURST 1
7195-#define I2C_SINGLE 0
7196-
7197-#define SKERR_I2C_E001 (SK_ERRBASE_I2C+0)
7198-#define SKERR_I2C_E001MSG "Sensor index unknown"
7199-#define SKERR_I2C_E002 (SKERR_I2C_E001+1)
7200-#define SKERR_I2C_E002MSG "TWSI: transfer does not complete"
7201-#define SKERR_I2C_E003 (SKERR_I2C_E002+1)
7202-#define SKERR_I2C_E003MSG "LM80: NAK on device send"
7203-#define SKERR_I2C_E004 (SKERR_I2C_E003+1)
7204-#define SKERR_I2C_E004MSG "LM80: NAK on register send"
7205-#define SKERR_I2C_E005 (SKERR_I2C_E004+1)
7206-#define SKERR_I2C_E005MSG "LM80: NAK on device (2) send"
7207-#define SKERR_I2C_E006 (SKERR_I2C_E005+1)
7208-#define SKERR_I2C_E006MSG "Unknown event"
7209-#define SKERR_I2C_E007 (SKERR_I2C_E006+1)
7210-#define SKERR_I2C_E007MSG "LM80 read out of state"
7211-#define SKERR_I2C_E008 (SKERR_I2C_E007+1)
7212-#define SKERR_I2C_E008MSG "Unexpected sensor read completed"
7213-#define SKERR_I2C_E009 (SKERR_I2C_E008+1)
7214-#define SKERR_I2C_E009MSG "WARNING: temperature sensor out of range"
7215-#define SKERR_I2C_E010 (SKERR_I2C_E009+1)
7216-#define SKERR_I2C_E010MSG "WARNING: voltage sensor out of range"
7217-#define SKERR_I2C_E011 (SKERR_I2C_E010+1)
7218-#define SKERR_I2C_E011MSG "ERROR: temperature sensor out of range"
7219-#define SKERR_I2C_E012 (SKERR_I2C_E011+1)
7220-#define SKERR_I2C_E012MSG "ERROR: voltage sensor out of range"
7221-#define SKERR_I2C_E013 (SKERR_I2C_E012+1)
7222-#define SKERR_I2C_E013MSG "ERROR: couldn't init sensor"
7223-#define SKERR_I2C_E014 (SKERR_I2C_E013+1)
7224-#define SKERR_I2C_E014MSG "WARNING: fan sensor out of range"
7225-#define SKERR_I2C_E015 (SKERR_I2C_E014+1)
7226-#define SKERR_I2C_E015MSG "ERROR: fan sensor out of range"
7227-#define SKERR_I2C_E016 (SKERR_I2C_E015+1)
7228-#define SKERR_I2C_E016MSG "TWSI: active transfer does not complete"
7229-
7230-/*
7231- * Define Timeout values
7232- */
7233-#define SK_I2C_TIM_LONG 2000000L /* 2 seconds */
7234-#define SK_I2C_TIM_SHORT 100000L /* 100 milliseconds */
7235-#define SK_I2C_TIM_WATCH 1000000L /* 1 second */
7236-
7237-/*
7238- * Define trap and error log hold times
7239- */
7240-#ifndef SK_SEN_ERR_TR_HOLD
7241-#define SK_SEN_ERR_TR_HOLD (4*SK_TICKS_PER_SEC)
7242-#endif
7243-#ifndef SK_SEN_ERR_LOG_HOLD
7244-#define SK_SEN_ERR_LOG_HOLD (60*SK_TICKS_PER_SEC)
7245-#endif
7246-#ifndef SK_SEN_WARN_TR_HOLD
7247-#define SK_SEN_WARN_TR_HOLD (15*SK_TICKS_PER_SEC)
7248-#endif
7249-#ifndef SK_SEN_WARN_LOG_HOLD
7250-#define SK_SEN_WARN_LOG_HOLD (15*60*SK_TICKS_PER_SEC)
7251-#endif
7252-
7253-/*
7254- * Defines for SenType
7255- */
7256-#define SK_SEN_UNKNOWN 0
7257-#define SK_SEN_TEMP 1
7258-#define SK_SEN_VOLT 2
7259-#define SK_SEN_FAN 3
7260-
7261-/*
7262- * Define for the SenErrorFlag
7263- */
7264-#define SK_SEN_ERR_NOT_PRESENT 0 /* Error Flag: Sensor not present */
7265-#define SK_SEN_ERR_OK 1 /* Error Flag: O.K. */
7266-#define SK_SEN_ERR_WARN 2 /* Error Flag: Warning */
7267-#define SK_SEN_ERR_ERR 3 /* Error Flag: Error */
7268-#define SK_SEN_ERR_FAULTY 4 /* Error Flag: Faulty */
7269-
7270-/*
7271- * Define the Sensor struct
7272- */
7273-struct s_Sensor {
7274- char *SenDesc; /* Description */
7275- int SenType; /* Voltage or Temperature */
7276- SK_I32 SenValue; /* Current value of the sensor */
7277- SK_I32 SenThreErrHigh; /* High error Threshhold of this sensor */
7278- SK_I32 SenThreWarnHigh; /* High warning Threshhold of this sensor */
7279- SK_I32 SenThreErrLow; /* Lower error Threshold of the sensor */
7280- SK_I32 SenThreWarnLow; /* Lower warning Threshold of the sensor */
7281- int SenErrFlag; /* Sensor indicated an error */
7282- SK_BOOL SenInit; /* Is sensor initialized ? */
7283- SK_U64 SenErrCts; /* Error trap counter */
7284- SK_U64 SenWarnCts; /* Warning trap counter */
7285- SK_U64 SenBegErrTS; /* Begin error timestamp */
7286- SK_U64 SenBegWarnTS; /* Begin warning timestamp */
7287- SK_U64 SenLastErrTrapTS; /* Last error trap timestamp */
7288- SK_U64 SenLastErrLogTS; /* Last error log timestamp */
7289- SK_U64 SenLastWarnTrapTS; /* Last warning trap timestamp */
7290- SK_U64 SenLastWarnLogTS; /* Last warning log timestamp */
7291- int SenState; /* Sensor State (see HW specific include) */
7292- int (*SenRead)(SK_AC *pAC, SK_IOC IoC, struct s_Sensor *pSen);
7293- /* Sensors read function */
7294- SK_U16 SenReg; /* Register Address for this sensor */
7295- SK_U8 SenDev; /* Device Selection for this sensor */
7296-};
7297-
7298-typedef struct s_I2c {
7299- SK_SENSOR SenTable[SK_MAX_SENSORS]; /* Sensor Table */
7300- int CurrSens; /* Which sensor is currently queried */
7301- int MaxSens; /* Max. number of sensors */
7302- int TimerMode; /* Use the timer also to watch the state machine */
7303- int InitLevel; /* Initialized Level */
7304-#ifndef SK_DIAG
7305- int DummyReads; /* Number of non-checked dummy reads */
7306- SK_TIMER SenTimer; /* Sensors timer */
7307-#endif /* !SK_DIAG */
7308-} SK_I2C;
7309-
7310-extern int SkI2cInit(SK_AC *pAC, SK_IOC IoC, int Level);
7311-#ifdef SK_DIAG
7312-extern SK_U32 SkI2cRead(SK_AC *pAC, SK_IOC IoC, int Dev, int Size, int Reg,
7313- int Burst);
7314-#else /* !SK_DIAG */
7315-extern int SkI2cEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Para);
7316-extern void SkI2cWaitIrq(SK_AC *pAC, SK_IOC IoC);
7317-extern void SkI2cIsr(SK_AC *pAC, SK_IOC IoC);
7318-#endif /* !SK_DIAG */
7319-#endif /* n_SKI2C_H */
7320-
7321diff -ruN linux/drivers/net/sk98lin/h/skpcidevid.h linux-new/drivers/net/sk98lin/h/skpcidevid.h
7322--- linux/drivers/net/sk98lin/h/skpcidevid.h 1970-01-01 01:00:00.000000000 +0100
7323+++ linux-new/drivers/net/sk98lin/h/skpcidevid.h 2006-10-13 10:18:34.000000000 +0200
7324@@ -0,0 +1,120 @@
7325+static struct pci_device_id sk98lin_pci_tbl[] __devinitdata = {
7326+/* { pci_vendor_id, pci_device_id, * SAMPLE ENTRY! *
7327+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, */
7328+
7329+ /* 1 */
7330+ { 0x10B7, 0x1700, /* Generic 3Com 3C940 Gigabit Ethernet Adapter */
7331+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7332+ /* 2 */
7333+ { 0x10B7, 0x80EB, /* Generic 3Com 3C940B Gigabit LOM Ethernet Adapter */
7334+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7335+ /* 3 */
7336+ { 0x1148, 0x4300, /* Generic SysKonnect SK-98xx Gigabit Ethernet Server Adapter */
7337+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7338+ /* 4 */
7339+ { 0x1148, 0x4320, /* Generic SysKonnect SK-98xx V2.0 Gigabit Ethernet Adapter */
7340+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7341+ /* 5 */
7342+ { 0x1148, 0x9000, /* Generic SysKonnect SK-9Sxx 10/100/1000Base-T Server Adapter */
7343+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7344+ /* 6 */
7345+ { 0x1148, 0x9E00, /* Generic SysKonnect SK-9Exx 10/100/1000Base-T Adapter */
7346+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7347+ /* 7 */
7348+ { 0x1186, 0x4001, /* D-Link DGE-550SX PCI-X Gigabit Ethernet Adapter */
7349+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7350+ /* 8 */
7351+ { 0x1186, 0x4B00, /* D-Link DGE-560T PCI Express Gigabit Ethernet Adapter */
7352+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7353+ /* 9 */
7354+ { 0x1186, 0x4B01, /* D-Link DGE-530T Gigabit Ethernet Adapter */
7355+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7356+ /* 10 */
7357+ { 0x1186, 0x4B02, /* D-Link DGE-560SX PCI Express Gigabit Ethernet Adapter */
7358+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7359+ /* 11 */
7360+ { 0x1186, 0x4C00, /* D-Link DGE-530T Gigabit Ethernet Adapter */
7361+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7362+ /* 12 */
7363+ { 0x11AB, 0x4320, /* Generic Marvell Yukon 88E8001/8003/8010 based Ethernet Controller */
7364+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7365+ /* 13 */
7366+ { 0x11AB, 0x4340, /* Generic Marvell Yukon 88E8021 based Ethernet Controller */
7367+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7368+ /* 14 */
7369+ { 0x11AB, 0x4341, /* Generic Marvell Yukon 88E8022 based Ethernet Controller */
7370+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7371+ /* 15 */
7372+ { 0x11AB, 0x4342, /* Generic Marvell Yukon 88E8061 based Ethernet Controller */
7373+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7374+ /* 16 */
7375+ { 0x11AB, 0x4343, /* Generic Marvell Yukon 88E8062 based Ethernet Controller */
7376+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7377+ /* 17 */
7378+ { 0x11AB, 0x4344, /* Generic Marvell Yukon 88E8021 based Ethernet Controller */
7379+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7380+ /* 18 */
7381+ { 0x11AB, 0x4345, /* Generic Marvell Yukon 88E8022 based Ethernet Controller */
7382+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7383+ /* 19 */
7384+ { 0x11AB, 0x4346, /* Generic Marvell Yukon 88E8061 based Ethernet Controller */
7385+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7386+ /* 20 */
7387+ { 0x11AB, 0x4347, /* Generic Marvell Yukon 88E8062 based Ethernet Controller */
7388+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7389+ /* 21 */
7390+ { 0x11AB, 0x4350, /* Generic Marvell Yukon 88E8035 based Ethernet Controller */
7391+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7392+ /* 22 */
7393+ { 0x11AB, 0x4351, /* Generic Marvell Yukon 88E8036 based Ethernet Controller */
7394+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7395+ /* 23 */
7396+ { 0x11AB, 0x4352, /* Generic Marvell Yukon 88E8038 based Ethernet Controller */
7397+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7398+ /* 24 */
7399+ { 0x11AB, 0x4353, /* Generic Marvell Yukon 88E8039 PCI-E Fast Ethernet Controller */
7400+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7401+ /* 25 */
7402+ { 0x11AB, 0x4356, /* Generic Marvell Yukon 88EC033 based Ethernet Controller */
7403+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7404+ /* 26 */
7405+ { 0x11AB, 0x4360, /* Generic Marvell Yukon 88E8052 based Ethernet Controller */
7406+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7407+ /* 27 */
7408+ { 0x11AB, 0x4361, /* Generic Marvell Yukon 88E8050 based Ethernet Controller */
7409+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7410+ /* 28 */
7411+ { 0x11AB, 0x4362, /* Generic Marvell Yukon 88E8053 based Ethernet Controller */
7412+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7413+ /* 29 */
7414+ { 0x11AB, 0x4363, /* Generic Marvell Yukon 88E8055 PCI-E Gigabit Ethernet Controller */
7415+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7416+ /* 30 */
7417+ { 0x11AB, 0x4364, /* Generic Marvell Yukon 88E8056 based Ethernet Controller */
7418+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7419+ /* 31 */
7420+ { 0x11AB, 0x4366, /* Generic Marvell Yukon 88EC036 PCI-E Gigabit Ethernet Controller */
7421+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7422+ /* 32 */
7423+ { 0x11AB, 0x4367, /* Generic Marvell Yukon 88EC032 based Ethernet Controller */
7424+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7425+ /* 33 */
7426+ { 0x11AB, 0x4368, /* Generic Marvell Yukon 88EC034 based Ethernet Controller */
7427+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7428+ /* 34 */
7429+ { 0x11AB, 0x4369, /* Generic Marvell Yukon 88EC042 based Ethernet Controller */
7430+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7431+ /* 35 */
7432+ { 0x11AB, 0x5005, /* Belkin Gigabit Desktop Card10/100/1000Base-T Adapter, Copper RJ-45 */
7433+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7434+ /* 36 */
7435+ { 0x1371, 0x434E, /* Generic CNet PowerG-2000 1000/100/10Mbps N-Way PCI-Bus Giga-Card */
7436+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7437+ /* 37 */
7438+ { 0x1737, 0x1032, /* Linksys EG1032 v2 Instant Gigabit Network Adapter */
7439+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7440+ /* 38 */
7441+ { 0x1737, 0x1064, /* Linksys EG1064 v2 Instant Gigabit Network Adapter */
7442+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7443+ { 0, }
7444+};
7445diff -ruN linux/drivers/net/sk98lin/h/skqueue.h linux-new/drivers/net/sk98lin/h/skqueue.h
7446--- linux/drivers/net/sk98lin/h/skqueue.h 2007-01-02 23:21:17.000000000 +0100
7447+++ linux-new/drivers/net/sk98lin/h/skqueue.h 2006-10-13 11:18:49.000000000 +0200
7448@@ -2,14 +2,15 @@
7449 *
7450 * Name: skqueue.h
7451 * Project: Gigabit Ethernet Adapters, Event Scheduler Module
7452- * Version: $Revision$
7453- * Date: $Date$
7454+ * Version: $Revision$
7455+ * Date: $Date$
7456 * Purpose: Defines for the Event queue
7457 *
7458 ******************************************************************************/
7459
7460 /******************************************************************************
7461 *
7462+ * LICENSE:
7463 * (C)Copyright 1998-2002 SysKonnect GmbH.
7464 * (C)Copyright 2002-2003 Marvell.
7465 *
7466@@ -19,6 +20,7 @@
7467 * (at your option) any later version.
7468 *
7469 * The information in this file is provided "AS IS" without warranty.
7470+ * /LICENSE
7471 *
7472 ******************************************************************************/
7473
7474@@ -45,6 +47,9 @@
7475 #define SKGE_RSF 11 /* RSF Aggregation Event Class */
7476 #define SKGE_MARKER 12 /* MARKER Aggregation Event Class */
7477 #define SKGE_FD 13 /* FD Distributor Event Class */
7478+#ifdef SK_ASF
7479+#define SKGE_ASF 14 /* ASF Event Class */
7480+#endif
7481
7482 /*
7483 * define event queue as circular buffer
7484@@ -90,5 +95,11 @@
7485 #define SKERR_Q_E001MSG "Event queue overflow"
7486 #define SKERR_Q_E002 (SKERR_Q_E001+1)
7487 #define SKERR_Q_E002MSG "Undefined event class"
7488+#define SKERR_Q_E003 (SKERR_Q_E001+2)
7489+#define SKERR_Q_E003MSG "Event queued in Init Level 0"
7490+#define SKERR_Q_E004 (SKERR_Q_E001+3)
7491+#define SKERR_Q_E004MSG "Error Reported from Event Fuction (Queue Blocked)"
7492+#define SKERR_Q_E005 (SKERR_Q_E001+4)
7493+#define SKERR_Q_E005MSG "Event scheduler called in Init Level 0 or 1"
7494 #endif /* _SKQUEUE_H_ */
7495
7496diff -ruN linux/drivers/net/sk98lin/h/skrlmt.h linux-new/drivers/net/sk98lin/h/skrlmt.h
7497--- linux/drivers/net/sk98lin/h/skrlmt.h 2007-01-02 23:21:17.000000000 +0100
7498+++ linux-new/drivers/net/sk98lin/h/skrlmt.h 2006-10-13 11:18:49.000000000 +0200
7499@@ -2,14 +2,15 @@
7500 *
7501 * Name: skrlmt.h
7502 * Project: GEnesis, PCI Gigabit Ethernet Adapter
7503- * Version: $Revision$
7504- * Date: $Date$
7505+ * Version: $Revision$
7506+ * Date: $Date$
7507 * Purpose: Header file for Redundant Link ManagemenT.
7508 *
7509 ******************************************************************************/
7510
7511 /******************************************************************************
7512 *
7513+ * LICENSE:
7514 * (C)Copyright 1998-2002 SysKonnect GmbH.
7515 * (C)Copyright 2002-2003 Marvell.
7516 *
7517@@ -19,6 +20,7 @@
7518 * (at your option) any later version.
7519 *
7520 * The information in this file is provided "AS IS" without warranty.
7521+ * /LICENSE
7522 *
7523 ******************************************************************************/
7524
7525diff -ruN linux/drivers/net/sk98lin/h/sktimer.h linux-new/drivers/net/sk98lin/h/sktimer.h
7526--- linux/drivers/net/sk98lin/h/sktimer.h 2007-01-02 23:21:17.000000000 +0100
7527+++ linux-new/drivers/net/sk98lin/h/sktimer.h 2006-10-13 11:18:49.000000000 +0200
7528@@ -2,14 +2,15 @@
7529 *
7530 * Name: sktimer.h
7531 * Project: Gigabit Ethernet Adapters, Event Scheduler Module
7532- * Version: $Revision$
7533- * Date: $Date$
7534+ * Version: $Revision$
7535+ * Date: $Date$
7536 * Purpose: Defines for the timer functions
7537 *
7538 ******************************************************************************/
7539
7540 /******************************************************************************
7541 *
7542+ * LICENSE:
7543 * (C)Copyright 1998-2002 SysKonnect GmbH.
7544 * (C)Copyright 2002-2003 Marvell.
7545 *
7546@@ -19,6 +20,7 @@
7547 * (at your option) any later version.
7548 *
7549 * The information in this file is provided "AS IS" without warranty.
7550+ * /LICENSE
7551 *
7552 ******************************************************************************/
7553
7554diff -ruN linux/drivers/net/sk98lin/h/sktwsi.h linux-new/drivers/net/sk98lin/h/sktwsi.h
7555--- linux/drivers/net/sk98lin/h/sktwsi.h 1970-01-01 01:00:00.000000000 +0100
7556+++ linux-new/drivers/net/sk98lin/h/sktwsi.h 2006-10-13 10:18:34.000000000 +0200
7557@@ -0,0 +1,179 @@
7558+/******************************************************************************
7559+ *
7560+ * Name: sktwsi.h
7561+ * Project: Gigabit Ethernet Adapters, TWSI-Module
7562+ * Version: $Revision$
7563+ * Date: $Date$
7564+ * Purpose: Defines to access Voltage and Temperature Sensor
7565+ *
7566+ ******************************************************************************/
7567+
7568+/******************************************************************************
7569+ *
7570+ * LICENSE:
7571+ * (C)Copyright 1998-2002 SysKonnect.
7572+ * (C)Copyright 2002-2003 Marvell.
7573+ *
7574+ * This program is free software; you can redistribute it and/or modify
7575+ * it under the terms of the GNU General Public License as published by
7576+ * the Free Software Foundation; either version 2 of the License, or
7577+ * (at your option) any later version.
7578+ *
7579+ * The information in this file is provided "AS IS" without warranty.
7580+ * /LICENSE
7581+ *
7582+ ******************************************************************************/
7583+
7584+/*
7585+ * SKTWSI.H contains all TWSI specific defines
7586+ */
7587+
7588+#ifndef _SKTWSI_H_
7589+#define _SKTWSI_H_
7590+
7591+typedef struct s_Sensor SK_SENSOR;
7592+
7593+#include "h/skgetwsi.h"
7594+
7595+/*
7596+ * Define the TWSI events.
7597+ */
7598+#define SK_I2CEV_IRQ 1 /* IRQ happened Event */
7599+#define SK_I2CEV_TIM 2 /* Timeout event */
7600+#define SK_I2CEV_CLEAR 3 /* Clear MIB Values */
7601+
7602+/*
7603+ * Define READ and WRITE Constants.
7604+ */
7605+#define I2C_READ 0
7606+#define I2C_WRITE 1
7607+#define I2C_BURST 1
7608+#define I2C_SINGLE 0
7609+
7610+#define SKERR_I2C_E001 (SK_ERRBASE_I2C+0)
7611+#define SKERR_I2C_E001MSG "Sensor index unknown"
7612+#define SKERR_I2C_E002 (SKERR_I2C_E001+1)
7613+#define SKERR_I2C_E002MSG "TWSI: transfer does not complete"
7614+#define SKERR_I2C_E003 (SKERR_I2C_E002+1)
7615+#define SKERR_I2C_E003MSG "LM80: NAK on device send"
7616+#define SKERR_I2C_E004 (SKERR_I2C_E003+1)
7617+#define SKERR_I2C_E004MSG "LM80: NAK on register send"
7618+#define SKERR_I2C_E005 (SKERR_I2C_E004+1)
7619+#define SKERR_I2C_E005MSG "LM80: NAK on device (2) send"
7620+#define SKERR_I2C_E006 (SKERR_I2C_E005+1)
7621+#define SKERR_I2C_E006MSG "Unknown event"
7622+#define SKERR_I2C_E007 (SKERR_I2C_E006+1)
7623+#define SKERR_I2C_E007MSG "LM80 read out of state"
7624+#define SKERR_I2C_E008 (SKERR_I2C_E007+1)
7625+#define SKERR_I2C_E008MSG "Unexpected sensor read completed"
7626+#define SKERR_I2C_E009 (SKERR_I2C_E008+1)
7627+#define SKERR_I2C_E009MSG "WARNING: temperature sensor out of range"
7628+#define SKERR_I2C_E010 (SKERR_I2C_E009+1)
7629+#define SKERR_I2C_E010MSG "WARNING: voltage sensor out of range"
7630+#define SKERR_I2C_E011 (SKERR_I2C_E010+1)
7631+#define SKERR_I2C_E011MSG "ERROR: temperature sensor out of range"
7632+#define SKERR_I2C_E012 (SKERR_I2C_E011+1)
7633+#define SKERR_I2C_E012MSG "ERROR: voltage sensor out of range"
7634+#define SKERR_I2C_E013 (SKERR_I2C_E012+1)
7635+#define SKERR_I2C_E013MSG "ERROR: couldn't init sensor"
7636+#define SKERR_I2C_E014 (SKERR_I2C_E013+1)
7637+#define SKERR_I2C_E014MSG "WARNING: fan sensor out of range"
7638+#define SKERR_I2C_E015 (SKERR_I2C_E014+1)
7639+#define SKERR_I2C_E015MSG "ERROR: fan sensor out of range"
7640+#define SKERR_I2C_E016 (SKERR_I2C_E015+1)
7641+#define SKERR_I2C_E016MSG "TWSI: active transfer does not complete"
7642+
7643+/*
7644+ * Define Timeout values
7645+ */
7646+#define SK_I2C_TIM_LONG 2000000L /* 2 seconds */
7647+#define SK_I2C_TIM_SHORT 100000L /* 100 milliseconds */
7648+#define SK_I2C_TIM_WATCH 1000000L /* 1 second */
7649+
7650+/*
7651+ * Define trap and error log hold times
7652+ */
7653+#ifndef SK_SEN_ERR_TR_HOLD
7654+#define SK_SEN_ERR_TR_HOLD (4*SK_TICKS_PER_SEC)
7655+#endif
7656+#ifndef SK_SEN_ERR_LOG_HOLD
7657+#define SK_SEN_ERR_LOG_HOLD (60*SK_TICKS_PER_SEC)
7658+#endif
7659+#ifndef SK_SEN_WARN_TR_HOLD
7660+#define SK_SEN_WARN_TR_HOLD (15*SK_TICKS_PER_SEC)
7661+#endif
7662+#ifndef SK_SEN_WARN_LOG_HOLD
7663+#define SK_SEN_WARN_LOG_HOLD (15*60*SK_TICKS_PER_SEC)
7664+#endif
7665+
7666+/*
7667+ * Defines for SenType
7668+ */
7669+#define SK_SEN_UNKNOWN 0
7670+#define SK_SEN_TEMP 1
7671+#define SK_SEN_VOLT 2
7672+#define SK_SEN_FAN 3
7673+
7674+/*
7675+ * Define for the SenErrorFlag
7676+ */
7677+#define SK_SEN_ERR_NOT_PRESENT 0 /* Error Flag: Sensor not present */
7678+#define SK_SEN_ERR_OK 1 /* Error Flag: O.K. */
7679+#define SK_SEN_ERR_WARN 2 /* Error Flag: Warning */
7680+#define SK_SEN_ERR_ERR 3 /* Error Flag: Error */
7681+#define SK_SEN_ERR_FAULTY 4 /* Error Flag: Faulty */
7682+
7683+/*
7684+ * Define the Sensor struct
7685+ */
7686+struct s_Sensor {
7687+ char *SenDesc; /* Description */
7688+ int SenType; /* Voltage or Temperature */
7689+ SK_I32 SenValue; /* Current value of the sensor */
7690+ SK_I32 SenThreErrHigh; /* High error Threshhold of this sensor */
7691+ SK_I32 SenThreWarnHigh; /* High warning Threshhold of this sensor */
7692+ SK_I32 SenThreErrLow; /* Lower error Threshold of the sensor */
7693+ SK_I32 SenThreWarnLow; /* Lower warning Threshold of the sensor */
7694+ int SenErrFlag; /* Sensor indicated an error */
7695+ SK_BOOL SenInit; /* Is sensor initialized ? */
7696+ SK_U64 SenErrCts; /* Error trap counter */
7697+ SK_U64 SenWarnCts; /* Warning trap counter */
7698+ SK_U64 SenBegErrTS; /* Begin error timestamp */
7699+ SK_U64 SenBegWarnTS; /* Begin warning timestamp */
7700+ SK_U64 SenLastErrTrapTS; /* Last error trap timestamp */
7701+ SK_U64 SenLastErrLogTS; /* Last error log timestamp */
7702+ SK_U64 SenLastWarnTrapTS; /* Last warning trap timestamp */
7703+ SK_U64 SenLastWarnLogTS; /* Last warning log timestamp */
7704+ int SenState; /* Sensor State (see HW specific include) */
7705+ int (*SenRead)(SK_AC *pAC, SK_IOC IoC, struct s_Sensor *pSen);
7706+ /* Sensors read function */
7707+ SK_U16 SenReg; /* Register Address for this sensor */
7708+ SK_U8 SenDev; /* Device Selection for this sensor */
7709+};
7710+
7711+typedef struct s_I2c {
7712+ SK_SENSOR SenTable[SK_MAX_SENSORS]; /* Sensor Table */
7713+ int CurrSens; /* Which sensor is currently queried */
7714+ int MaxSens; /* Max. number of sensors */
7715+ int TimerMode; /* Use the timer also to watch the state machine */
7716+ int InitLevel; /* Initialized Level */
7717+#ifndef SK_DIAG
7718+ int DummyReads; /* Number of non-checked dummy reads */
7719+ SK_TIMER SenTimer; /* Sensors timer */
7720+#endif /* !SK_DIAG */
7721+} SK_I2C;
7722+
7723+extern int SkI2cInit(SK_AC *pAC, SK_IOC IoC, int Level);
7724+extern int SkI2cWrite(SK_AC *pAC, SK_IOC IoC, SK_U32 Data, int Dev, int Size,
7725+ int Reg, int Burst);
7726+extern int SkI2cReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen);
7727+#ifdef SK_DIAG
7728+extern SK_U32 SkI2cRead(SK_AC *pAC, SK_IOC IoC, int Dev, int Size, int Reg,
7729+ int Burst);
7730+#else /* !SK_DIAG */
7731+extern int SkI2cEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Para);
7732+extern void SkI2cWaitIrq(SK_AC *pAC, SK_IOC IoC);
7733+extern void SkI2cIsr(SK_AC *pAC, SK_IOC IoC);
7734+#endif /* !SK_DIAG */
7735+#endif /* n_SKTWSI_H */
7736+
7737diff -ruN linux/drivers/net/sk98lin/h/sktypes.h linux-new/drivers/net/sk98lin/h/sktypes.h
7738--- linux/drivers/net/sk98lin/h/sktypes.h 2007-01-02 23:21:17.000000000 +0100
7739+++ linux-new/drivers/net/sk98lin/h/sktypes.h 2006-10-13 11:18:49.000000000 +0200
7740@@ -2,8 +2,8 @@
7741 *
7742 * Name: sktypes.h
7743 * Project: GEnesis, PCI Gigabit Ethernet Adapter
7744- * Version: $Revision$
7745- * Date: $Date$
7746+ * Version: $Revision$
7747+ * Date: $Date$
7748 * Purpose: Define data types for Linux
7749 *
7750 ******************************************************************************/
7751@@ -11,7 +11,7 @@
7752 /******************************************************************************
7753 *
7754 * (C)Copyright 1998-2002 SysKonnect GmbH.
7755- * (C)Copyright 2002-2003 Marvell.
7756+ * (C)Copyright 2002-2005 Marvell.
7757 *
7758 * This program is free software; you can redistribute it and/or modify
7759 * it under the terms of the GNU General Public License as published by
7760@@ -22,48 +22,28 @@
7761 *
7762 ******************************************************************************/
7763
7764-/******************************************************************************
7765- *
7766- * Description:
7767- *
7768- * In this file, all data types that are needed by the common modules
7769- * are mapped to Linux data types.
7770- *
7771- *
7772- * Include File Hierarchy:
7773- *
7774- *
7775- ******************************************************************************/
7776-
7777 #ifndef __INC_SKTYPES_H
7778 #define __INC_SKTYPES_H
7779
7780-
7781-/* defines *******************************************************************/
7782-
7783-/*
7784- * Data types with a specific size. 'I' = signed, 'U' = unsigned.
7785- */
7786-#define SK_I8 s8
7787-#define SK_U8 u8
7788-#define SK_I16 s16
7789-#define SK_U16 u16
7790-#define SK_I32 s32
7791-#define SK_U32 u32
7792-#define SK_I64 s64
7793-#define SK_U64 u64
7794-
7795-#define SK_UPTR ulong /* casting pointer <-> integral */
7796-
7797-/*
7798-* Boolean type.
7799-*/
7800-#define SK_BOOL SK_U8
7801-#define SK_FALSE 0
7802-#define SK_TRUE (!SK_FALSE)
7803-
7804-/* typedefs *******************************************************************/
7805-
7806-/* function prototypes ********************************************************/
7807+#define SK_I8 s8 /* 8 bits (1 byte) signed */
7808+#define SK_U8 u8 /* 8 bits (1 byte) unsigned */
7809+#define SK_I16 s16 /* 16 bits (2 bytes) signed */
7810+#define SK_U16 u16 /* 16 bits (2 bytes) unsigned */
7811+#define SK_I32 s32 /* 32 bits (4 bytes) signed */
7812+#define SK_U32 u32 /* 32 bits (4 bytes) unsigned */
7813+#define SK_I64 s64 /* 64 bits (8 bytes) signed */
7814+#define SK_U64 u64 /* 64 bits (8 bytes) unsigned */
7815+
7816+#define SK_UPTR ulong /* casting pointer <-> integral */
7817+
7818+#define SK_BOOL SK_U8
7819+#define SK_FALSE 0
7820+#define SK_TRUE (!SK_FALSE)
7821
7822 #endif /* __INC_SKTYPES_H */
7823+
7824+/*******************************************************************************
7825+ *
7826+ * End of file
7827+ *
7828+ ******************************************************************************/
7829diff -ruN linux/drivers/net/sk98lin/h/skversion.h linux-new/drivers/net/sk98lin/h/skversion.h
7830--- linux/drivers/net/sk98lin/h/skversion.h 2007-01-02 23:21:17.000000000 +0100
7831+++ linux-new/drivers/net/sk98lin/h/skversion.h 2006-10-13 11:18:49.000000000 +0200
7832@@ -1,17 +1,17 @@
7833 /******************************************************************************
7834 *
7835- * Name: version.h
7836+ * Name: skversion.h
7837 * Project: GEnesis, PCI Gigabit Ethernet Adapter
7838- * Version: $Revision$
7839- * Date: $Date$
7840- * Purpose: SK specific Error log support
7841+ * Version: $Revision$
7842+ * Date: $Date$
7843+ * Purpose: specific version strings and numbers
7844 *
7845 ******************************************************************************/
7846
7847 /******************************************************************************
7848 *
7849 * (C)Copyright 1998-2002 SysKonnect GmbH.
7850- * (C)Copyright 2002-2003 Marvell.
7851+ * (C)Copyright 2002-2005 Marvell.
7852 *
7853 * This program is free software; you can redistribute it and/or modify
7854 * it under the terms of the GNU General Public License as published by
7855@@ -22,17 +22,17 @@
7856 *
7857 ******************************************************************************/
7858
7859-#ifdef lint
7860-static const char SysKonnectFileId[] = "@(#) (C) SysKonnect GmbH.";
7861-static const char SysKonnectBuildNumber[] =
7862- "@(#)SK-BUILD: 6.23 PL: 01";
7863-#endif /* !defined(lint) */
7864-
7865-#define BOOT_STRING "sk98lin: Network Device Driver v6.23\n" \
7866- "(C)Copyright 1999-2004 Marvell(R)."
7867-
7868-#define VER_STRING "6.23"
7869-#define DRIVER_FILE_NAME "sk98lin"
7870-#define DRIVER_REL_DATE "Feb-13-2004"
7871-
7872+#define BOOT_STRING "sk98lin: Network Device Driver v8.41.2.3\n" \
7873+ "(C)Copyright 1999-2006 Marvell(R)."
7874+#define VER_STRING "8.41.2.3"
7875+#define PATCHLEVEL "02"
7876+#define DRIVER_FILE_NAME "sk98lin"
7877+#define DRIVER_REL_DATE "Oct-13-2006"
7878+#define DRV_NAME "sk98lin"
7879+#define DRV_VERSION "8.41.2.3"
7880
7881+/*******************************************************************************
7882+ *
7883+ * End of file
7884+ *
7885+ ******************************************************************************/
7886diff -ruN linux/drivers/net/sk98lin/h/skvpd.h linux-new/drivers/net/sk98lin/h/skvpd.h
7887--- linux/drivers/net/sk98lin/h/skvpd.h 2007-01-02 23:21:17.000000000 +0100
7888+++ linux-new/drivers/net/sk98lin/h/skvpd.h 2006-10-13 11:18:49.000000000 +0200
7889@@ -1,23 +1,25 @@
7890 /******************************************************************************
7891 *
7892 * Name: skvpd.h
7893- * Project: GEnesis, PCI Gigabit Ethernet Adapter
7894- * Version: $Revision$
7895- * Date: $Date$
7896+ * Project: Gigabit Ethernet Adapters, VPD-Module
7897+ * Version: $Revision$
7898+ * Date: $Date$
7899 * Purpose: Defines and Macros for VPD handling
7900 *
7901 ******************************************************************************/
7902
7903 /******************************************************************************
7904 *
7905- * (C)Copyright 1998-2003 SysKonnect GmbH.
7906+ * LICENSE:
7907+ * (C)Copyright 1998-2002 SysKonnect.
7908+ * (C)Copyright 2002-2004 Marvell.
7909 *
7910 * This program is free software; you can redistribute it and/or modify
7911 * it under the terms of the GNU General Public License as published by
7912 * the Free Software Foundation; either version 2 of the License, or
7913 * (at your option) any later version.
7914- *
7915 * The information in this file is provided "AS IS" without warranty.
7916+ * /LICENSE
7917 *
7918 ******************************************************************************/
7919
7920@@ -31,7 +33,7 @@
7921 /*
7922 * Define Resource Type Identifiers and VPD keywords
7923 */
7924-#define RES_ID 0x82 /* Resource Type ID String (Product Name) */
7925+#define RES_ID 0x82 /* Resource Type ID String (Product Name) */
7926 #define RES_VPD_R 0x90 /* start of VPD read only area */
7927 #define RES_VPD_W 0x91 /* start of VPD read/write area */
7928 #define RES_END 0x78 /* Resource Type End Tag */
7929@@ -40,14 +42,16 @@
7930 #define VPD_NAME "Name" /* Product Name, VPD name of RES_ID */
7931 #endif /* VPD_NAME */
7932 #define VPD_PN "PN" /* Adapter Part Number */
7933-#define VPD_EC "EC" /* Adapter Engineering Level */
7934+#define VPD_EC "EC" /* Adapter Engineering Level */
7935 #define VPD_MN "MN" /* Manufacture ID */
7936 #define VPD_SN "SN" /* Serial Number */
7937 #define VPD_CP "CP" /* Extended Capability */
7938 #define VPD_RV "RV" /* Checksum and Reserved */
7939-#define VPD_YA "YA" /* Asset Tag Identifier */
7940+#define VPD_YA "YA" /* Asset Tag Identifier */
7941 #define VPD_VL "VL" /* First Error Log Message (SK specific) */
7942 #define VPD_VF "VF" /* Second Error Log Message (SK specific) */
7943+#define VPD_VB "VB" /* Boot Agent ROM Configuration (SK specific) */
7944+#define VPD_VE "VE" /* EFI UNDI Configuration (SK specific) */
7945 #define VPD_RW "RW" /* Remaining Read / Write Area */
7946
7947 /* 'type' values for vpd_setup_para() */
7948@@ -55,7 +59,7 @@
7949 #define VPD_RW_KEY 2 /* RW keys are "Yx", "Vx", and "RW" */
7950
7951 /* 'op' values for vpd_setup_para() */
7952-#define ADD_KEY 1 /* add the key at the pos "RV" or "RW" */
7953+#define ADD_KEY 1 /* add the key at the pos "RV" or "RW" */
7954 #define OWR_KEY 2 /* overwrite key if already exists */
7955
7956 /*
7957@@ -64,18 +68,18 @@
7958
7959 #define VPD_DEV_ID_GENESIS 0x4300
7960
7961-#define VPD_SIZE_YUKON 256
7962-#define VPD_SIZE_GENESIS 512
7963-#define VPD_SIZE 512
7964+#define VPD_SIZE_YUKON 256
7965+#define VPD_SIZE_GENESIS 512
7966+#define VPD_SIZE 512
7967 #define VPD_READ 0x0000
7968 #define VPD_WRITE 0x8000
7969
7970 #define VPD_STOP(pAC,IoC) VPD_OUT16(pAC,IoC,PCI_VPD_ADR_REG,VPD_WRITE)
7971
7972-#define VPD_GET_RES_LEN(p) ((unsigned int) \
7973- (* (SK_U8 *)&(p)[1]) |\
7974- ((* (SK_U8 *)&(p)[2]) << 8))
7975-#define VPD_GET_VPD_LEN(p) ((unsigned int)(* (SK_U8 *)&(p)[2]))
7976+#define VPD_GET_RES_LEN(p) ((unsigned int)\
7977+ (*(SK_U8 *)&(p)[1]) |\
7978+ ((*(SK_U8 *)&(p)[2]) << 8))
7979+#define VPD_GET_VPD_LEN(p) ((unsigned int)(*(SK_U8 *)&(p)[2]))
7980 #define VPD_GET_VAL(p) ((char *)&(p)[3])
7981
7982 #define VPD_MAX_LEN 50
7983@@ -126,62 +130,78 @@
7984 /*
7985 * System specific VPD macros
7986 */
7987-#ifndef SKDIAG
7988+#ifndef SK_DIAG
7989 #ifndef VPD_DO_IO
7990 #define VPD_OUT8(pAC,IoC,Addr,Val) (void)SkPciWriteCfgByte(pAC,Addr,Val)
7991 #define VPD_OUT16(pAC,IoC,Addr,Val) (void)SkPciWriteCfgWord(pAC,Addr,Val)
7992+#define VPD_OUT32(pAC,IoC,Addr,Val) (void)SkPciWriteCfgDWord(pAC,Addr,Val)
7993 #define VPD_IN8(pAC,IoC,Addr,pVal) (void)SkPciReadCfgByte(pAC,Addr,pVal)
7994 #define VPD_IN16(pAC,IoC,Addr,pVal) (void)SkPciReadCfgWord(pAC,Addr,pVal)
7995 #define VPD_IN32(pAC,IoC,Addr,pVal) (void)SkPciReadCfgDWord(pAC,Addr,pVal)
7996 #else /* VPD_DO_IO */
7997-#define VPD_OUT8(pAC,IoC,Addr,Val) SK_OUT8(IoC,PCI_C(Addr),Val)
7998-#define VPD_OUT16(pAC,IoC,Addr,Val) SK_OUT16(IoC,PCI_C(Addr),Val)
7999-#define VPD_IN8(pAC,IoC,Addr,pVal) SK_IN8(IoC,PCI_C(Addr),pVal)
8000-#define VPD_IN16(pAC,IoC,Addr,pVal) SK_IN16(IoC,PCI_C(Addr),pVal)
8001-#define VPD_IN32(pAC,IoC,Addr,pVal) SK_IN32(IoC,PCI_C(Addr),pVal)
8002+#define VPD_OUT8(pAC,IoC,Addr,Val) SK_OUT8(IoC,PCI_C(pAC,Addr),Val)
8003+#define VPD_OUT16(pAC,IoC,Addr,Val) SK_OUT16(IoC,PCI_C(pAC,Addr),Val)
8004+#define VPD_OUT32(pAC,IoC,Addr,Val) SK_OUT32(IoC,PCI_C(pAC,Addr),Val)
8005+#define VPD_IN8(pAC,IoC,Addr,pVal) SK_IN8(IoC,PCI_C(pAC,Addr),pVal)
8006+#define VPD_IN16(pAC,IoC,Addr,pVal) SK_IN16(IoC,PCI_C(pAC,Addr),pVal)
8007+#define VPD_IN32(pAC,IoC,Addr,pVal) SK_IN32(IoC,PCI_C(pAC,Addr),pVal)
8008 #endif /* VPD_DO_IO */
8009-#else /* SKDIAG */
8010+#else /* SK_DIAG */
8011 #define VPD_OUT8(pAC,Ioc,Addr,Val) { \
8012 if ((pAC)->DgT.DgUseCfgCycle) \
8013 SkPciWriteCfgByte(pAC,Addr,Val); \
8014 else \
8015- SK_OUT8(pAC,PCI_C(Addr),Val); \
8016+ SK_OUT8(pAC,PCI_C(pAC,Addr),Val); \
8017 }
8018 #define VPD_OUT16(pAC,Ioc,Addr,Val) { \
8019 if ((pAC)->DgT.DgUseCfgCycle) \
8020 SkPciWriteCfgWord(pAC,Addr,Val); \
8021 else \
8022- SK_OUT16(pAC,PCI_C(Addr),Val); \
8023+ SK_OUT16(pAC,PCI_C(pAC,Addr),Val); \
8024+ }
8025+#define VPD_OUT32(pAC,Ioc,Addr,Val) { \
8026+ if ((pAC)->DgT.DgUseCfgCycle) \
8027+ SkPciWriteCfgDWord(pAC,Addr,Val); \
8028+ else \
8029+ SK_OUT32(pAC,PCI_C(pAC,Addr),Val); \
8030 }
8031 #define VPD_IN8(pAC,Ioc,Addr,pVal) { \
8032- if ((pAC)->DgT.DgUseCfgCycle) \
8033+ if ((pAC)->DgT.DgUseCfgCycle) \
8034 SkPciReadCfgByte(pAC,Addr,pVal); \
8035 else \
8036- SK_IN8(pAC,PCI_C(Addr),pVal); \
8037+ SK_IN8(pAC,PCI_C(pAC,Addr),pVal); \
8038 }
8039 #define VPD_IN16(pAC,Ioc,Addr,pVal) { \
8040- if ((pAC)->DgT.DgUseCfgCycle) \
8041+ if ((pAC)->DgT.DgUseCfgCycle) \
8042 SkPciReadCfgWord(pAC,Addr,pVal); \
8043 else \
8044- SK_IN16(pAC,PCI_C(Addr),pVal); \
8045+ SK_IN16(pAC,PCI_C(pAC,Addr),pVal); \
8046 }
8047 #define VPD_IN32(pAC,Ioc,Addr,pVal) { \
8048 if ((pAC)->DgT.DgUseCfgCycle) \
8049 SkPciReadCfgDWord(pAC,Addr,pVal); \
8050 else \
8051- SK_IN32(pAC,PCI_C(Addr),pVal); \
8052+ SK_IN32(pAC,PCI_C(pAC,Addr),pVal); \
8053 }
8054-#endif /* nSKDIAG */
8055+#endif /* SK_DIAG */
8056
8057 /* function prototypes ********************************************************/
8058
8059 #ifndef SK_KR_PROTO
8060-#ifdef SKDIAG
8061+#ifdef SK_DIAG
8062 extern SK_U32 VpdReadDWord(
8063 SK_AC *pAC,
8064 SK_IOC IoC,
8065 int addr);
8066-#endif /* SKDIAG */
8067+#endif /* SK_DIAG */
8068+
8069+extern int VpdSetupPara(
8070+ SK_AC *pAC,
8071+ const char *key,
8072+ const char *buf,
8073+ int len,
8074+ int type,
8075+ int op);
8076
8077 extern SK_VPD_STATUS *VpdStat(
8078 SK_AC *pAC,
8079@@ -219,7 +239,17 @@
8080 SK_AC *pAC,
8081 SK_IOC IoC);
8082
8083-#ifdef SKDIAG
8084+extern void VpdErrLog(
8085+ SK_AC *pAC,
8086+ SK_IOC IoC,
8087+ char *msg);
8088+
8089+int VpdInit(
8090+ SK_AC *pAC,
8091+ SK_IOC IoC);
8092+
8093+#if defined(SK_DIAG) || defined(SK_ASF)
8094+
8095 extern int VpdReadBlock(
8096 SK_AC *pAC,
8097 SK_IOC IoC,
8098@@ -233,9 +263,12 @@
8099 char *buf,
8100 int addr,
8101 int len);
8102-#endif /* SKDIAG */
8103+
8104+#endif /* SK_DIAG || SK_ASF */
8105+
8106 #else /* SK_KR_PROTO */
8107 extern SK_U32 VpdReadDWord();
8108+extern int VpdSetupPara();
8109 extern SK_VPD_STATUS *VpdStat();
8110 extern int VpdKeys();
8111 extern int VpdRead();
8112@@ -243,6 +276,8 @@
8113 extern int VpdWrite();
8114 extern int VpdDelete();
8115 extern int VpdUpdate();
8116+extern void VpdErrLog();
8117 #endif /* SK_KR_PROTO */
8118
8119 #endif /* __INC_SKVPD_H_ */
8120+
8121diff -ruN linux/drivers/net/sk98lin/h/sky2le.h linux-new/drivers/net/sk98lin/h/sky2le.h
8122--- linux/drivers/net/sk98lin/h/sky2le.h 1970-01-01 01:00:00.000000000 +0100
8123+++ linux-new/drivers/net/sk98lin/h/sky2le.h 2006-10-13 11:18:49.000000000 +0200
8124@@ -0,0 +1,890 @@
8125+/******************************************************************************
8126+ *
8127+ * Name: sky2le.h
8128+ * Project: Gigabit Ethernet Adapters, Common Modules
8129+ * Version: $Revision$
8130+ * Date: $Date$
8131+ * Purpose: Common list element definitions and access macros.
8132+ *
8133+ ******************************************************************************/
8134+
8135+/******************************************************************************
8136+ *
8137+ * LICENSE:
8138+ * (C)Copyright 2002-2006 Marvell.
8139+ *
8140+ * This program is free software; you can redistribute it and/or modify
8141+ * it under the terms of the GNU General Public License as published by
8142+ * the Free Software Foundation; either version 2 of the License, or
8143+ * (at your option) any later version.
8144+ * The information in this file is provided "AS IS" without warranty.
8145+ * /LICENSE
8146+ *
8147+ ******************************************************************************/
8148+
8149+#ifndef __INC_SKY2LE_H
8150+#define __INC_SKY2LE_H
8151+
8152+#ifdef __cplusplus
8153+extern "C" {
8154+#endif /* __cplusplus */
8155+
8156+/* defines ********************************************************************/
8157+
8158+#define MIN_LEN_OF_LE_TAB 128
8159+#define MAX_LEN_OF_LE_TAB 4096
8160+#ifdef USE_POLLING_UNIT
8161+#define NUM_LE_POLLING_UNIT 2
8162+#endif
8163+#define MAX_FRAG_OVERHEAD 10
8164+
8165+/* Macro for aligning a given value */
8166+#define SK_ALIGN_SIZE(Value, Alignment, AlignedVal) { \
8167+ (AlignedVal) = (((Value) + (Alignment) - 1) & (~((Alignment) - 1)));\
8168+}
8169+
8170+/******************************************************************************
8171+ *
8172+ * LE2DWord() - Converts the given Little Endian value to machine order value
8173+ *
8174+ * Description:
8175+ * This function converts the Little Endian value received as an argument to
8176+ * the machine order value.
8177+ *
8178+ * Returns:
8179+ * The converted value
8180+ *
8181+ */
8182+
8183+#ifdef SK_LITTLE_ENDIAN
8184+
8185+#ifndef SK_USE_REV_DESC
8186+#define LE2DWord(value) (value)
8187+#else /* SK_USE_REV_DESC */
8188+#define LE2DWord(value) \
8189+ ((((value)<<24L) & 0xff000000L) + \
8190+ (((value)<< 8L) & 0x00ff0000L) + \
8191+ (((value)>> 8L) & 0x0000ff00L) + \
8192+ (((value)>>24L) & 0x000000ffL))
8193+#endif /* SK_USE_REV_DESC */
8194+
8195+#else /* !SK_LITTLE_ENDIAN */
8196+
8197+#ifndef SK_USE_REV_DESC
8198+#define LE2DWord(value) \
8199+ ((((value)<<24L) & 0xff000000L) + \
8200+ (((value)<< 8L) & 0x00ff0000L) + \
8201+ (((value)>> 8L) & 0x0000ff00L) + \
8202+ (((value)>>24L) & 0x000000ffL))
8203+#else /* SK_USE_REV_DESC */
8204+#define LE2DWord(value) (value)
8205+#endif /* SK_USE_REV_DESC */
8206+
8207+#endif /* !SK_LITTLE_ENDIAN */
8208+
8209+/******************************************************************************
8210+ *
8211+ * DWord2LE() - Converts the given value to a Little Endian value
8212+ *
8213+ * Description:
8214+ * This function converts the value received as an argument to a Little Endian
8215+ * value on Big Endian machines. If the machine running the code is Little
8216+ * Endian, then no conversion is done.
8217+ *
8218+ * Returns:
8219+ * The converted value
8220+ *
8221+ */
8222+
8223+#ifdef SK_LITTLE_ENDIAN
8224+
8225+#ifndef SK_USE_REV_DESC
8226+#define DWord2LE(value) (value)
8227+#else /* SK_USE_REV_DESC */
8228+#define DWord2LE(value) \
8229+ ((((value)<<24L) & 0xff000000L) + \
8230+ (((value)<< 8L) & 0x00ff0000L) + \
8231+ (((value)>> 8L) & 0x0000ff00L) + \
8232+ (((value)>>24L) & 0x000000ffL))
8233+#endif /* SK_USE_REV_DESC */
8234+
8235+#else /* !SK_LITTLE_ENDIAN */
8236+
8237+#ifndef SK_USE_REV_DESC
8238+#define DWord2LE(value) \
8239+ ((((value)<<24L) & 0xff000000L) + \
8240+ (((value)<< 8L) & 0x00ff0000L) + \
8241+ (((value)>> 8L) & 0x0000ff00L) + \
8242+ (((value)>>24L) & 0x000000ffL))
8243+#else /* SK_USE_REV_DESC */
8244+#define DWord2LE(value) (value)
8245+#endif /* SK_USE_REV_DESC */
8246+#endif /* !SK_LITTLE_ENDIAN */
8247+
8248+/******************************************************************************
8249+ *
8250+ * LE2Word() - Converts the given Little Endian value to machine order value
8251+ *
8252+ * Description:
8253+ * This function converts the Little Endian value received as an argument to
8254+ * the machine order value.
8255+ *
8256+ * Returns:
8257+ * The converted value
8258+ *
8259+ */
8260+
8261+#ifdef SK_LITTLE_ENDIAN
8262+#ifndef SK_USE_REV_DESC
8263+#define LE2Word(value) (value)
8264+#else /* SK_USE_REV_DESC */
8265+#define LE2Word(value) \
8266+ ((((value)<< 8L) & 0xff00) + \
8267+ (((value)>> 8L) & 0x00ff))
8268+#endif /* SK_USE_REV_DESC */
8269+
8270+#else /* !SK_LITTLE_ENDIAN */
8271+#ifndef SK_USE_REV_DESC
8272+#define LE2Word(value) \
8273+ ((((value)<< 8L) & 0xff00) + \
8274+ (((value)>> 8L) & 0x00ff))
8275+#else /* SK_USE_REV_DESC */
8276+#define LE2Word(value) (value)
8277+#endif /* SK_USE_REV_DESC */
8278+#endif /* !SK_LITTLE_ENDIAN */
8279+
8280+/******************************************************************************
8281+ *
8282+ * Word2LE() - Converts the given value to a Little Endian value
8283+ *
8284+ * Description:
8285+ * This function converts the value received as an argument to a Little Endian
8286+ * value on Big Endian machines. If the machine running the code is Little
8287+ * Endian, then no conversion is done.
8288+ *
8289+ * Returns:
8290+ * The converted value
8291+ *
8292+ */
8293+
8294+#ifdef SK_LITTLE_ENDIAN
8295+#ifndef SK_USE_REV_DESC
8296+#define Word2LE(value) (value)
8297+#else /* SK_USE_REV_DESC */
8298+#define Word2LE(value) \
8299+ ((((value)<< 8L) & 0xff00) + \
8300+ (((value)>> 8L) & 0x00ff))
8301+#endif /* SK_USE_REV_DESC */
8302+
8303+#else /* !SK_LITTLE_ENDIAN */
8304+#ifndef SK_USE_REV_DESC
8305+#define Word2LE(value) \
8306+ ((((value)<< 8L) & 0xff00) + \
8307+ (((value)>> 8L) & 0x00ff))
8308+#else /* SK_USE_REV_DESC */
8309+#define Word2LE(value) (value)
8310+#endif /* SK_USE_REV_DESC */
8311+#endif /* !SK_LITTLE_ENDIAN */
8312+
8313+/******************************************************************************
8314+ *
8315+ * Transmit list element macros
8316+ *
8317+ */
8318+
8319+#define TXLE_SET_ADDR(pLE, Addr) \
8320+ ((pLE)->Tx.TxUn.BufAddr = DWord2LE(Addr))
8321+#define TXLE_SET_LSLEN(pLE, Len) \
8322+ ((pLE)->Tx.TxUn.LargeSend.Length = Word2LE(Len))
8323+#define TXLE_SET_STACS(pLE, Start) \
8324+ ((pLE)->Tx.TxUn.ChkSum.TxTcpSp = Word2LE(Start))
8325+#define TXLE_SET_WRICS(pLE, Write) \
8326+ ((pLE)->Tx.TxUn.ChkSum.TxTcpWp = Word2LE(Write))
8327+#define TXLE_SET_INICS(pLE, Ini) ((pLE)->Tx.Send.InitCsum = Word2LE(Ini))
8328+#define TXLE_SET_LEN(pLE, Len) ((pLE)->Tx.Send.BufLen = Word2LE(Len))
8329+#define TXLE_SET_VLAN(pLE, Vlan) ((pLE)->Tx.Send.VlanTag = Word2LE(Vlan))
8330+#define TXLE_SET_LCKCS(pLE, Lock) ((pLE)->Tx.ControlFlags = (Lock))
8331+#define TXLE_SET_CTRL(pLE, Ctrl) ((pLE)->Tx.ControlFlags = (Ctrl))
8332+#define TXLE_SET_OPC(pLE, Opc) ((pLE)->Tx.Opcode = (Opc))
8333+
8334+#define TXLE_GET_ADDR(pLE) LE2DWord((pLE)->Tx.TxUn.BufAddr)
8335+#define TXLE_GET_LSLEN(pLE) LE2Word((pLE)->Tx.TxUn.LargeSend.Length)
8336+#define TXLE_GET_STACS(pLE) LE2Word((pLE)->Tx.TxUn.ChkSum.TxTcpSp)
8337+#define TXLE_GET_WRICS(pLE) LE2Word((pLE)->Tx.TxUn.ChkSum.TxTcpWp)
8338+#define TXLE_GET_INICS(pLE) LE2Word((pLE)->Tx.Send.InitCsum)
8339+#define TXLE_GET_LEN(pLE) LE2Word((pLE)->Tx.Send.BufLen)
8340+#define TXLE_GET_VLAN(pLE) LE2Word((pLE)->Tx.Send.VlanTag)
8341+#define TXLE_GET_LCKCS(pLE) ((pLE)->Tx.ControlFlags)
8342+#define TXLE_GET_CTRL(pLE) ((pLE)->Tx.ControlFlags)
8343+#define TXLE_GET_OPC(pLE) ((pLE)->Tx.Opcode)
8344+
8345+/******************************************************************************
8346+ *
8347+ * Receive list element macros
8348+ *
8349+ */
8350+
8351+#define RXLE_SET_ADDR(pLE, Addr) \
8352+ ((pLE)->Rx.RxUn.BufAddr = (SK_U32)DWord2LE(Addr))
8353+#define RXLE_SET_STACS2(pLE, Offs) \
8354+ ((pLE)->Rx.RxUn.ChkSum.RxTcpSp2 = Word2LE(Offs))
8355+#define RXLE_SET_STACS1(pLE, Offs) \
8356+ ((pLE)->Rx.RxUn.ChkSum.RxTcpSp1 = Word2LE(Offs))
8357+#define RXLE_SET_LEN(pLE, Len) ((pLE)->Rx.BufferLength = Word2LE(Len))
8358+#define RXLE_SET_CTRL(pLE, Ctrl) ((pLE)->Rx.ControlFlags = (Ctrl))
8359+#define RXLE_SET_OPC(pLE, Opc) ((pLE)->Rx.Opcode = (Opc))
8360+
8361+#define RXLE_GET_ADDR(pLE) LE2DWord((pLE)->Rx.RxUn.BufAddr)
8362+#define RXLE_GET_STACS2(pLE) LE2Word((pLE)->Rx.RxUn.ChkSum.RxTcpSp2)
8363+#define RXLE_GET_STACS1(pLE) LE2Word((pLE)->Rx.RxUn.ChkSum.RxTcpSp1)
8364+#define RXLE_GET_LEN(pLE) LE2Word((pLE)->Rx.BufferLength)
8365+#define RXLE_GET_CTRL(pLE) ((pLE)->Rx.ControlFlags)
8366+#define RXLE_GET_OPC(pLE) ((pLE)->Rx.Opcode)
8367+
8368+/******************************************************************************
8369+ *
8370+ * Status list element macros
8371+ *
8372+ */
8373+
8374+#define STLE_SET_OPC(pLE, Opc) ((pLE)->St.Opcode = (Opc))
8375+
8376+#define STLE_GET_FRSTATUS(pLE) LE2DWord((pLE)->St.StUn.StRxStatWord)
8377+#define STLE_GET_TIST(pLE) LE2DWord((pLE)->St.StUn.StRxTimeStamp)
8378+#define STLE_GET_TCP1(pLE) LE2Word((pLE)->St.StUn.StRxTCPCSum.RxTCPSum1)
8379+#define STLE_GET_TCP2(pLE) LE2Word((pLE)->St.StUn.StRxTCPCSum.RxTCPSum2)
8380+#define STLE_GET_LEN(pLE) LE2Word((pLE)->St.Stat.BufLen)
8381+#define STLE_GET_VLAN(pLE) LE2Word((pLE)->St.Stat.VlanTag)
8382+#define STLE_GET_LINK(pLE) ((pLE)->St.Link)
8383+#define STLE_GET_OPC(pLE) ((pLE)->St.Opcode)
8384+#define STLE_GET_DONE_IDX(pLE,LowVal,HighVal) { \
8385+ (LowVal) = LE2DWord((pLE)->St.StUn.StTxStatLow); \
8386+ (HighVal) = LE2Word((pLE)->St.Stat.StTxStatHi); \
8387+}
8388+
8389+#define STLE_GET_RSS(pLE) LE2DWord((pLE)->St.StUn.StRxRssValue)
8390+#define STLE_GET_IPBIT(pLE) ((pLE)->St.Stat.Rss.FlagField & RSS_IP_FLAG)
8391+#define STLE_GET_TCPBIT(pLE) ((pLE)->St.Stat.Rss.FlagField & RSS_TCP_FLAG)
8392+
8393+
8394+/* always take both values as a parameter to avoid typos */
8395+#define STLE_GET_DONE_IDX_TXA1(LowVal,HighVal) \
8396+ (((LowVal) & STLE_TXA1_MSKL) >> STLE_TXA1_SHIFTL)
8397+#define STLE_GET_DONE_IDX_TXS1(LowVal,HighVal) \
8398+ ((LowVal & STLE_TXS1_MSKL) >> STLE_TXS1_SHIFTL)
8399+#define STLE_GET_DONE_IDX_TXA2(LowVal,HighVal) \
8400+ (((LowVal & STLE_TXA2_MSKL) >> STLE_TXA2_SHIFTL) + \
8401+ ((HighVal & STLE_TXA2_MSKH) << STLE_TXA2_SHIFTH))
8402+#define STLE_GET_DONE_IDX_TXS2(LowVal,HighVal) \
8403+ ((HighVal & STLE_TXS2_MSKH) >> STLE_TXS2_SHIFTH)
8404+
8405+
8406+#define SK_Y2_RXSTAT_CHECK_PKT(Len, RxStat, IsOk) { \
8407+ (IsOk) = (((RxStat) & GMR_FS_RX_OK) != 0) && \
8408+ (((RxStat) & GMR_FS_ANY_ERR) == 0); \
8409+ \
8410+ if ((IsOk) && ((SK_U16)(((RxStat) & GMR_FS_LEN_MSK) >> \
8411+ GMR_FS_LEN_SHIFT) != (Len))) { \
8412+ /* length in MAC status differs from length in LE */\
8413+ (IsOk) = SK_FALSE; \
8414+ } \
8415+}
8416+
8417+
8418+/******************************************************************************
8419+ *
8420+ * Polling unit list element macros
8421+ *
8422+ * NOTE: the Idx must be <= 0xfff and PU_PUTIDX_VALID makes them valid
8423+ *
8424+ */
8425+
8426+#ifdef USE_POLLING_UNIT
8427+
8428+#define POLE_SET_OPC(pLE, Opc) ((pLE)->Sa.Opcode = (Opc))
8429+#define POLE_SET_LINK(pLE, Port) ((pLE)->Sa.Link = (Port))
8430+#define POLE_SET_RXIDX(pLE, Idx) ((pLE)->Sa.RxIdxVld = Word2LE(Idx))
8431+#define POLE_SET_TXAIDX(pLE, Idx) ((pLE)->Sa.TxAIdxVld = Word2LE(Idx))
8432+#define POLE_SET_TXSIDX(pLE, Idx) ((pLE)->Sa.TxSIdxVld = Word2LE(Idx))
8433+
8434+#define POLE_GET_OPC(pLE) ((pLE)->Sa.Opcode)
8435+#define POLE_GET_LINK(pLE) ((pLE)->Sa.Link)
8436+#define POLE_GET_RXIDX(pLE) LE2Word((pLE)->Sa.RxIdxVld)
8437+#define POLE_GET_TXAIDX(pLE) LE2Word((pLE)->Sa.TxAIdxVld)
8438+#define POLE_GET_TXSIDX(pLE) LE2Word((pLE)->Sa.TxSIdxVld)
8439+
8440+#endif /* USE_POLLING_UNIT */
8441+
8442+/******************************************************************************
8443+ *
8444+ * Debug macros for list elements
8445+ *
8446+ */
8447+
8448+#ifdef DEBUG
8449+
8450+#define SK_DBG_DUMP_RX_LE(pLE) { \
8451+ SK_U8 Opcode; \
8452+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8453+ ("=== RX_LIST_ELEMENT @addr: %p cont: %02x %02x %02x %02x %02x %02x %02x %02x\n", \
8454+ pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\
8455+ ((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5], \
8456+ ((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7])); \
8457+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8458+ ("\t (16bit) %04x %04x %04x %04x\n", \
8459+ ((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2], \
8460+ ((SK_U16 *) pLE)[3])); \
8461+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8462+ ("\t (32bit) %08x %08x\n", \
8463+ ((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1])); \
8464+ Opcode = RXLE_GET_OPC(pLE); \
8465+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8466+ ("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == HW_OWNER) ? \
8467+ "Hardware" : "Software")); \
8468+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8469+ ("\tOpc: 0x%x ",Opcode)); \
8470+ switch (Opcode & (~HW_OWNER)) { \
8471+ case OP_BUFFER: \
8472+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8473+ ("\tOP_BUFFER\n")); \
8474+ break; \
8475+ case OP_PACKET: \
8476+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8477+ ("\tOP_PACKET\n")); \
8478+ break; \
8479+ case OP_ADDR64: \
8480+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8481+ ("\tOP_ADDR64\n")); \
8482+ break; \
8483+ case OP_TCPSTART: \
8484+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8485+ ("\tOP_TCPPAR\n")); \
8486+ break; \
8487+ case SW_OWNER: \
8488+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8489+ ("\tunused LE\n")); \
8490+ break; \
8491+ default: \
8492+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8493+ ("\tunknown Opcode!!!\n")); \
8494+ } \
8495+ if ((Opcode & OP_BUFFER) == OP_BUFFER) { \
8496+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8497+ ("\tControl: 0x%x\n", RXLE_GET_CTRL(pLE))); \
8498+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8499+ ("\tBufLen: 0x%x\n", RXLE_GET_LEN(pLE))); \
8500+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8501+ ("\tLowAddr: 0x%x\n", RXLE_GET_ADDR(pLE))); \
8502+ } \
8503+ if ((Opcode & OP_ADDR64) == OP_ADDR64) { \
8504+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8505+ ("\tHighAddr: 0x%x\n", RXLE_GET_ADDR(pLE))); \
8506+ } \
8507+ if ((Opcode & OP_TCPSTART) == OP_TCPSTART) { \
8508+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8509+ ("\tTCP Sum Start 1 : 0x%x\n", RXLE_GET_STACS1(pLE))); \
8510+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8511+ ("\tTCP Sum Start 2 : 0x%x\n", RXLE_GET_STACS2(pLE))); \
8512+ } \
8513+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8514+ ("=====================\n")); \
8515+}
8516+
8517+#define SK_DBG_DUMP_TX_LE(pLE) { \
8518+ SK_U8 Opcode; \
8519+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8520+ ("=== TX_LIST_ELEMENT @addr: %p cont: %02x %02x %02x %02x %02x %02x %02x %02x\n", \
8521+ pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\
8522+ ((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5], \
8523+ ((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7])); \
8524+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8525+ ("\t (16bit) %04x %04x %04x %04x\n", \
8526+ ((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2], \
8527+ ((SK_U16 *) pLE)[3])); \
8528+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8529+ ("\t (32bit) %08x %08x\n", \
8530+ ((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1])); \
8531+ Opcode = TXLE_GET_OPC(pLE); \
8532+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8533+ ("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == HW_OWNER) ? \
8534+ "Hardware" : "Software")); \
8535+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8536+ ("\tOpc: 0x%x ",Opcode)); \
8537+ switch (Opcode & (~HW_OWNER)) { \
8538+ case OP_TCPCHKSUM: \
8539+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8540+ ("\tOP_TCPCHKSUM\n")); \
8541+ break; \
8542+ case OP_TCPIS: \
8543+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8544+ ("\tOP_TCPIS\n")); \
8545+ break; \
8546+ case OP_TCPLCK: \
8547+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8548+ ("\tOP_TCPLCK\n")); \
8549+ break; \
8550+ case OP_TCPLW: \
8551+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8552+ ("\tOP_TCPLW\n")); \
8553+ break; \
8554+ case OP_TCPLSW: \
8555+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8556+ ("\tOP_TCPLSW\n")); \
8557+ break; \
8558+ case OP_TCPLISW: \
8559+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8560+ ("\tOP_TCPLISW\n")); \
8561+ break; \
8562+ case OP_ADDR64: \
8563+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8564+ ("\tOP_ADDR64\n")); \
8565+ break; \
8566+ case OP_VLAN: \
8567+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8568+ ("\tOP_VLAN\n")); \
8569+ break; \
8570+ case OP_ADDR64VLAN: \
8571+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8572+ ("\tOP_ADDR64VLAN\n")); \
8573+ break; \
8574+ case OP_LRGLEN: \
8575+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8576+ ("\tOP_LRGLEN\n")); \
8577+ break; \
8578+ case OP_LRGLENVLAN: \
8579+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8580+ ("\tOP_LRGLENVLAN\n")); \
8581+ break; \
8582+ case OP_BUFFER: \
8583+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8584+ ("\tOP_BUFFER\n")); \
8585+ break; \
8586+ case OP_PACKET: \
8587+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8588+ ("\tOP_PACKET\n")); \
8589+ break; \
8590+ case OP_LARGESEND: \
8591+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8592+ ("\tOP_LARGESEND\n")); \
8593+ break; \
8594+ case SW_OWNER: \
8595+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8596+ ("\tunused LE\n")); \
8597+ break; \
8598+ default: \
8599+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8600+ ("\tunknown Opcode!!!\n")); \
8601+ } \
8602+ if ((Opcode & OP_BUFFER) == OP_BUFFER) { \
8603+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8604+ ("\tControl: 0x%x\n", TXLE_GET_CTRL(pLE))); \
8605+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8606+ ("\tBufLen: 0x%x\n", TXLE_GET_LEN(pLE))); \
8607+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8608+ ("\tLowAddr: 0x%x\n", TXLE_GET_ADDR(pLE))); \
8609+ } \
8610+ if ((Opcode & OP_ADDR64) == OP_ADDR64) { \
8611+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8612+ ("\tHighAddr: 0x%x\n", TXLE_GET_ADDR(pLE))); \
8613+ } \
8614+ if ((Opcode & OP_VLAN) == OP_VLAN) { \
8615+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8616+ ("\tVLAN Id: 0x%x\n", TXLE_GET_VLAN(pLE))); \
8617+ } \
8618+ if ((Opcode & OP_LRGLEN) == OP_LRGLEN) { \
8619+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8620+ ("\tLarge send length: 0x%x\n", TXLE_GET_LSLEN(pLE))); \
8621+ } \
8622+ if ((Opcode &(~HW_OWNER)) <= OP_ADDR64) { \
8623+ if ((Opcode & OP_TCPWRITE) == OP_TCPWRITE) { \
8624+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8625+ ("\tTCP Sum Write: 0x%x\n", TXLE_GET_WRICS(pLE))); \
8626+ } \
8627+ if ((Opcode & OP_TCPSTART) == OP_TCPSTART) { \
8628+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8629+ ("\tTCP Sum Start: 0x%x\n", TXLE_GET_STACS(pLE))); \
8630+ } \
8631+ if ((Opcode & OP_TCPINIT) == OP_TCPINIT) { \
8632+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8633+ ("\tTCP Sum Init: 0x%x\n", TXLE_GET_INICS(pLE))); \
8634+ } \
8635+ if ((Opcode & OP_TCPLCK) == OP_TCPLCK) { \
8636+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8637+ ("\tTCP Sum Lock: 0x%x\n", TXLE_GET_LCKCS(pLE))); \
8638+ } \
8639+ } \
8640+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8641+ ("=====================\n")); \
8642+}
8643+
8644+#define SK_DBG_DUMP_ST_LE(pLE) { \
8645+ SK_U8 Opcode; \
8646+ SK_U16 HighVal; \
8647+ SK_U32 LowVal; \
8648+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8649+ ("=== ST_LIST_ELEMENT @addr: %p contains: %02x %02x %02x %02x %02x %02x %02x %02x\n",\
8650+ pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\
8651+ ((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5], \
8652+ ((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7])); \
8653+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8654+ ("\t (16bit) %04x %04x %04x %04x\n", \
8655+ ((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2], \
8656+ ((SK_U16 *) pLE)[3])); \
8657+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8658+ ("\t (32bit) %08x %08x\n", \
8659+ ((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1])); \
8660+ Opcode = STLE_GET_OPC(pLE); \
8661+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8662+ ("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == SW_OWNER) ? \
8663+ "Hardware" : "Software")); \
8664+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8665+ ("\tOpc: 0x%x", Opcode)); \
8666+ Opcode &= (~HW_OWNER); \
8667+ switch (Opcode) { \
8668+ case OP_RXSTAT: \
8669+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8670+ ("\tOP_RXSTAT\n")); \
8671+ break; \
8672+ case OP_RXTIMESTAMP: \
8673+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8674+ ("\tOP_RXTIMESTAMP\n")); \
8675+ break; \
8676+ case OP_RXVLAN: \
8677+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8678+ ("\tOP_RXVLAN\n")); \
8679+ break; \
8680+ case OP_RXCHKS: \
8681+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8682+ ("\tOP_RXCHKS\n")); \
8683+ break; \
8684+ case OP_RXCHKSVLAN: \
8685+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8686+ ("\tOP_RXCHKSVLAN\n")); \
8687+ break; \
8688+ case OP_RXTIMEVLAN: \
8689+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8690+ ("\tOP_RXTIMEVLAN\n")); \
8691+ break; \
8692+ case OP_RSS_HASH: \
8693+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8694+ ("\tOP_RSS_HASH\n")); \
8695+ break; \
8696+ case OP_TXINDEXLE: \
8697+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8698+ ("\tOP_TXINDEXLE\n")); \
8699+ break; \
8700+ case HW_OWNER: \
8701+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8702+ ("\tunused LE\n")); \
8703+ break; \
8704+ default: \
8705+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8706+ ("\tunknown status list element!!!\n")); \
8707+ } \
8708+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8709+ ("\tPort: %c\n", 'A' + STLE_GET_LINK(pLE))); \
8710+ if (Opcode == OP_RXSTAT) { \
8711+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8712+ ("\tFrameLen: 0x%x\n", STLE_GET_LEN(pLE))); \
8713+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8714+ ("\tFrameStat: 0x%x\n", STLE_GET_FRSTATUS(pLE))); \
8715+ } \
8716+ if ((Opcode & OP_RXVLAN) == OP_RXVLAN) { \
8717+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8718+ ("\tVLAN Id: 0x%x\n", STLE_GET_VLAN(pLE))); \
8719+ } \
8720+ if ((Opcode & OP_RXTIMESTAMP) == OP_RXTIMESTAMP) { \
8721+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8722+ ("\tTimestamp: 0x%x\n", STLE_GET_TIST(pLE))); \
8723+ } \
8724+ if ((Opcode & OP_RXCHKS) == OP_RXCHKS) { \
8725+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8726+ ("\tTCP: 0x%x 0x%x\n", STLE_GET_TCP1(pLE), \
8727+ STLE_GET_TCP2(pLE))); \
8728+ } \
8729+ if (Opcode == OP_TXINDEXLE) { \
8730+ STLE_GET_DONE_IDX(pLE, LowVal, HighVal); \
8731+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8732+ ("\tTx Index TxA1: 0x%x\n", \
8733+ STLE_GET_DONE_IDX_TXA1(LowVal,HighVal))); \
8734+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8735+ ("\tTx Index TxS1: 0x%x\n", \
8736+ STLE_GET_DONE_IDX_TXS1(LowVal,HighVal))); \
8737+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8738+ ("\tTx Index TxA2: 0x%x\n", \
8739+ STLE_GET_DONE_IDX_TXA2(LowVal,HighVal))); \
8740+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8741+ ("\tTx Index TxS2: 0x%x\n", \
8742+ STLE_GET_DONE_IDX_TXS2(LowVal,HighVal))); \
8743+ } \
8744+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8745+ ("=====================\n")); \
8746+}
8747+
8748+#ifdef USE_POLLING_UNIT
8749+#define SK_DBG_DUMP_PO_LE(pLE) { \
8750+ SK_U8 Opcode; \
8751+ SK_U16 Idx; \
8752+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8753+ ("=== PO_LIST_ELEMENT @addr: %p cont: %02x %02x %02x %02x %02x %02x %02x %02x\n", \
8754+ pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\
8755+ ((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5], \
8756+ ((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7])); \
8757+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8758+ ("\t (16bit) %04x %04x %04x %04x\n", \
8759+ ((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2], \
8760+ ((SK_U16 *) pLE)[3])); \
8761+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8762+ ("\t (32bit) %08x %08x\n", \
8763+ ((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1])); \
8764+ Opcode = POLE_GET_OPC(pLE); \
8765+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8766+ ("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == HW_OWNER) ? \
8767+ "Hardware" : "Software")); \
8768+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8769+ ("\tOpc: 0x%x ",Opcode)); \
8770+ if ((Opcode & ~HW_OWNER) == OP_PUTIDX) { \
8771+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8772+ ("\tOP_PUTIDX\n")); \
8773+ } \
8774+ else { \
8775+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8776+ ("\tunknown Opcode!!!\n")); \
8777+ } \
8778+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8779+ ("\tPort %c\n", 'A' + POLE_GET_LINK(pLE))); \
8780+ Idx = POLE_GET_TXAIDX(pLE); \
8781+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8782+ ("\tTxA Index is 0x%X and %svalid\n", Idx, \
8783+ (Idx & PU_PUTIDX_VALID) ? "" : "not ")); \
8784+ Idx = POLE_GET_TXSIDX(pLE); \
8785+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8786+ ("\tTxS Index is 0x%X and %svalid\n", Idx, \
8787+ (Idx & PU_PUTIDX_VALID) ? "" : "not ")); \
8788+ Idx = POLE_GET_RXIDX(pLE); \
8789+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8790+ ("\tRx Index is 0x%X and %svalid\n", Idx, \
8791+ (Idx & PU_PUTIDX_VALID) ? "" : "not ")); \
8792+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8793+ ("=====================\n")); \
8794+}
8795+#endif /* USE_POLLING_UNIT */
8796+
8797+#else /* !DEBUG */
8798+
8799+#define SK_DBG_DUMP_RX_LE(pLE)
8800+#define SK_DBG_DUMP_TX_LE(pLE)
8801+#define SK_DBG_DUMP_ST_LE(pLE)
8802+#define SK_DBG_DUMP_PO_LE(pLE)
8803+
8804+#endif /* !DEBUG */
8805+
8806+/******************************************************************************
8807+ *
8808+ * Macros for listelement tables
8809+ *
8810+ *
8811+ */
8812+
8813+#define LE_SIZE sizeof(SK_HWLE)
8814+#define LE_TAB_SIZE(NumElements) ((NumElements) * LE_SIZE)
8815+
8816+/* Number of unused list elements in table
8817+ * this macro always returns the number of free listelements - 1
8818+ * this way we want to guarantee that always one LE remains unused
8819+ */
8820+#define NUM_FREE_LE_IN_TABLE(pTable) \
8821+ ( ((pTable)->Put >= (pTable)->Done) ? \
8822+ (NUM_LE_IN_TABLE(pTable) - (pTable)->Put + (pTable)->Done - 1) :\
8823+ ((pTable)->Done - (pTable)->Put - 1) )
8824+
8825+/* total number of list elements in table */
8826+#define NUM_LE_IN_TABLE(pTable) ((pTable)->Num)
8827+
8828+/* get next unused Rx list element */
8829+#define GET_RX_LE(pLE, pTable) { \
8830+ pLE = &(pTable)->pLETab[(pTable)->Put]; \
8831+ (pTable)->Put = ((pTable)->Put + 1) & (NUM_LE_IN_TABLE(pTable) - 1);\
8832+}
8833+
8834+/* get next unused Tx list element */
8835+#define GET_TX_LE(pLE, pTable) GET_RX_LE(pLE, pTable)
8836+
8837+/* get next status list element expected to be finished by hw */
8838+#define GET_ST_LE(pLE, pTable) { \
8839+ pLE = &(pTable)->pLETab[(pTable)->Done]; \
8840+ (pTable)->Done = ((pTable)->Done +1) & (NUM_LE_IN_TABLE(pTable) - 1);\
8841+}
8842+
8843+#ifdef USE_POLLING_UNIT
8844+/* get next polling unit list element for port */
8845+#define GET_PO_LE(pLE, pTable, Port) { \
8846+ pLE = &(pTable)->pLETab[(Port)]; \
8847+}
8848+#endif /* USE_POLLING_UNIT */
8849+
8850+#define GET_PUT_IDX(pTable) ((pTable)->Put)
8851+
8852+#define UPDATE_HWPUT_IDX(pTable) {(pTable)->HwPut = (pTable)->Put; }
8853+
8854+/*
8855+ * get own bit of next status LE
8856+ * if the result is != 0 there has been at least one status LE finished
8857+ */
8858+#define OWN_OF_FIRST_LE(pTable) \
8859+ (STLE_GET_OPC(&(pTable)->pLETab[(pTable)->Done]) & HW_OWNER)
8860+
8861+#define SET_DONE_INDEX(pTable, Idx) (pTable)->Done = (Idx);
8862+
8863+#define GET_DONE_INDEX(pTable) ((pTable)->Done)
8864+
8865+#ifdef SAFE_BUT_SLOW
8866+
8867+/* check own bit of LE before current done idx */
8868+#define CHECK_STLE_OVERFLOW(pTable, IsOk) { \
8869+ unsigned i; \
8870+ if ((i = (pTable)->Done) == 0) { \
8871+ i = NUM_LE_IN_TABLE(pTable); \
8872+ } \
8873+ else { \
8874+ i = i - 1; \
8875+ } \
8876+ if (STLE_GET_OPC(&(pTable)->pLETab[i]) == HW_OWNER) { \
8877+ (IsOk) = SK_TRUE; \
8878+ } \
8879+ else { \
8880+ (IsOk) = SK_FALSE; \
8881+ } \
8882+ }
8883+
8884+
8885+/*
8886+ * for Yukon-2 the hardware is not polling the list elements, so it
8887+ * is not necessary to change the own-bit of Rx or Tx LEs before
8888+ * reusing them
8889+ * but it might make debugging easier if one simply can see whether
8890+ * a LE has been worked on
8891+ */
8892+
8893+#define CLEAR_LE_OWN(pTable, Idx) \
8894+ STLE_SET_OPC(&(pTable)->pLETab[(Idx)], SW_OWNER)
8895+
8896+/*
8897+ * clear all own bits starting from old done index up to the LE before
8898+ * the new done index
8899+ */
8900+#define CLEAR_LE_OWN_FROM_DONE_TO(pTable, To) { \
8901+ int i; \
8902+ i = (pTable)->Done; \
8903+ while (i != To) { \
8904+ CLEAR_LE_OWN(pTable, i); \
8905+ i = (i + 1) & (NUM_LE_IN_TABLE(pTable) - 1); \
8906+ } \
8907+ }
8908+
8909+#else /* !SAFE_BUT_SLOW */
8910+
8911+#define CHECK_STLE_OVERFLOW(pTable, IsOk)
8912+#define CLEAR_LE_OWN(pTable, Idx)
8913+#define CLEAR_LE_OWN_FROM_DONE_TO(pTable, To)
8914+
8915+#endif /* !SAFE_BUT_SLOW */
8916+
8917+
8918+/* typedefs *******************************************************************/
8919+
8920+typedef struct s_LetRxTx {
8921+ SK_U16 VlanId; /* VLAN Id given down last time */
8922+ SK_U16 TcpWp; /* TCP Checksum Write Position */
8923+ SK_U16 TcpSp1; /* TCP Checksum Calculation Start Position 1 */
8924+ SK_U16 TcpSp2; /* TCP Checksum Calculation Start Position 2 */
8925+ SK_U16 MssValue; /* Maximum Segment Size */
8926+ SK_U16 Reserved1; /* reserved word for furture extensions */
8927+ SK_U16 Reserved2; /* reserved word for furture extensions */
8928+ SK_U16 Reserved3; /* reserved word for furture extensions */
8929+} SK_LET_RX_TX;
8930+
8931+typedef struct s_LetStat {
8932+ SK_U32 RxTimeStamp; /* Receive Timestamp */
8933+ SK_U32 RssHashValue; /* RSS Hash Value */
8934+ SK_BOOL RssIsIp; /* RSS Hash Value: IP packet detected */
8935+ SK_BOOL RssIsTcp; /* RSS Hash Value: IP+TCP packet detected */
8936+ SK_U16 VlanId; /* VLAN Id given received by Status BMU */
8937+ SK_U16 TcpSum1; /* TCP checksum 1 (status BMU) */
8938+ SK_U16 TcpSum2; /* TCP checksum 2 (status BMU) */
8939+} SK_LET_STAT;
8940+
8941+typedef union s_LetBmuSpec {
8942+ SK_LET_RX_TX RxTx; /* Rx/Tx BMU specific variables */
8943+ SK_LET_STAT Stat; /* Status BMU specific variables */
8944+} SK_LET_BMU_S;
8945+
8946+typedef struct s_le_table {
8947+ /* all LE's between Done and HWPut are owned by the hardware */
8948+ /* all LE's between Put and Done can be used from software */
8949+ /* all LE's between HWPut and Put are currently processed in DriverSend */
8950+ unsigned Done; /* done index - consumed from HW and available */
8951+ unsigned Put; /* put index - to be given to hardware */
8952+ unsigned HwPut; /* put index actually given to hardware */
8953+ unsigned Num; /* total number of list elements */
8954+ SK_HWLE *pLETab; /* virtual address of list element table */
8955+ SK_U32 pPhyLETABLow; /* physical address of list element table */
8956+ SK_U32 pPhyLETABHigh; /* physical address of list element table */
8957+ /* values to remember in order to save some LEs */
8958+ SK_U32 BufHighAddr; /* high address given down last time */
8959+ SK_LET_BMU_S Bmu; /* contains BMU specific information */
8960+ SK_U32 Private; /* driver private variable free usable */
8961+ SK_U16 TcpInitCsum; /* init checksum */
8962+} SK_LE_TABLE;
8963+
8964+/* function prototypes ********************************************************/
8965+
8966+#ifndef SK_KR_PROTO
8967+
8968+/*
8969+ * public functions in sky2le.c
8970+ */
8971+extern void SkGeY2SetPutIndex(
8972+ SK_AC *pAC,
8973+ SK_IOC IoC,
8974+ SK_U32 StartAddrPrefetchUnit,
8975+ SK_LE_TABLE *pLETab);
8976+
8977+extern void SkGeY2InitPrefetchUnit(
8978+ SK_AC *pAC,
8979+ SK_IOC IoC,
8980+ unsigned int Queue,
8981+ SK_LE_TABLE *pLETab);
8982+
8983+extern void SkGeY2InitStatBmu(
8984+ SK_AC *pAC,
8985+ SK_IOC IoC,
8986+ SK_LE_TABLE *pLETab);
8987+
8988+extern void SkGeY2InitPollUnit(
8989+ SK_AC *pAC,
8990+ SK_IOC IoC,
8991+ SK_LE_TABLE *pLETab);
8992+
8993+extern void SkGeY2InitSingleLETable(
8994+ SK_AC *pAC,
8995+ SK_LE_TABLE *pLETab,
8996+ unsigned int NumLE,
8997+ void *pVMem,
8998+ SK_U32 PMemLowAddr,
8999+ SK_U32 PMemHighAddr);
9000+
9001+#else /* SK_KR_PROTO */
9002+extern void SkGeY2SetPutIndex();
9003+extern void SkGeY2InitPrefetchUnit();
9004+extern void SkGeY2InitStatBmu();
9005+extern void SkGeY2InitPollUnit();
9006+extern void SkGeY2InitSingleLETable();
9007+#endif /* SK_KR_PROTO */
9008+
9009+#ifdef __cplusplus
9010+}
9011+#endif /* __cplusplus */
9012+
9013+#endif /* __INC_SKY2LE_H */
9014+
9015diff -ruN linux/drivers/net/sk98lin/h/xmac_ii.h linux-new/drivers/net/sk98lin/h/xmac_ii.h
9016--- linux/drivers/net/sk98lin/h/xmac_ii.h 2007-01-02 23:21:17.000000000 +0100
9017+++ linux-new/drivers/net/sk98lin/h/xmac_ii.h 2006-10-13 10:18:34.000000000 +0200
9018@@ -2,23 +2,24 @@
9019 *
9020 * Name: xmac_ii.h
9021 * Project: Gigabit Ethernet Adapters, Common Modules
9022- * Version: $Revision$
9023- * Date: $Date$
9024+ * Version: $Revision$
9025+ * Date: $Date$
9026 * Purpose: Defines and Macros for Gigabit Ethernet Controller
9027 *
9028 ******************************************************************************/
9029
9030 /******************************************************************************
9031 *
9032+ * LICENSE:
9033 * (C)Copyright 1998-2002 SysKonnect.
9034- * (C)Copyright 2002-2003 Marvell.
9035+ * (C)Copyright 2002-2006 Marvell.
9036 *
9037 * This program is free software; you can redistribute it and/or modify
9038 * it under the terms of the GNU General Public License as published by
9039 * the Free Software Foundation; either version 2 of the License, or
9040 * (at your option) any later version.
9041- *
9042 * The information in this file is provided "AS IS" without warranty.
9043+ * /LICENSE
9044 *
9045 ******************************************************************************/
9046
9047@@ -371,18 +372,18 @@
9048 /* Bit 16..6: reserved */
9049 #define XM_SC_SNP_RXC (1<<5) /* Bit 5: (sc) Snap Rx Counters */
9050 #define XM_SC_SNP_TXC (1<<4) /* Bit 4: (sc) Snap Tx Counters */
9051-#define XM_SC_CP_RXC (1<<3) /* Bit 3: Copy Rx Counters Continuously */
9052+#define XM_SC_CP_RXC (1<<3) /* Bit 3: Copy Rx Counters Continuously */
9053 #define XM_SC_CP_TXC (1<<2) /* Bit 2: Copy Tx Counters Continuously */
9054 #define XM_SC_CLR_RXC (1<<1) /* Bit 1: (sc) Clear Rx Counters */
9055-#define XM_SC_CLR_TXC (1<<0) /* Bit 0: (sc) Clear Tx Counters */
9056+#define XM_SC_CLR_TXC (1<<0) /* Bit 0: (sc) Clear Tx Counters */
9057
9058
9059 /* XM_RX_CNT_EV 32 bit r/o Rx Counter Event Register */
9060 /* XM_RX_EV_MSK 32 bit r/w Rx Counter Event Mask */
9061-#define XMR_MAX_SZ_OV (1UL<<31) /* Bit 31: 1024-MaxSize Rx Cnt Ov*/
9062-#define XMR_1023B_OV (1L<<30) /* Bit 30: 512-1023Byte Rx Cnt Ov*/
9063-#define XMR_511B_OV (1L<<29) /* Bit 29: 256-511 Byte Rx Cnt Ov*/
9064-#define XMR_255B_OV (1L<<28) /* Bit 28: 128-255 Byte Rx Cnt Ov*/
9065+#define XMR_MAX_SZ_OV (1UL<<31) /* Bit 31: 1024-MaxSize Rx Cnt Ov */
9066+#define XMR_1023B_OV (1L<<30) /* Bit 30: 512-1023Byte Rx Cnt Ov */
9067+#define XMR_511B_OV (1L<<29) /* Bit 29: 256-511 Byte Rx Cnt Ov */
9068+#define XMR_255B_OV (1L<<28) /* Bit 28: 128-255 Byte Rx Cnt Ov */
9069 #define XMR_127B_OV (1L<<27) /* Bit 27: 65-127 Byte Rx Cnt Ov */
9070 #define XMR_64B_OV (1L<<26) /* Bit 26: 64 Byte Rx Cnt Ov */
9071 #define XMR_UTIL_OV (1L<<25) /* Bit 25: Rx Util Cnt Overflow */
9072@@ -390,9 +391,9 @@
9073 #define XMR_CEX_ERR_OV (1L<<23) /* Bit 23: CEXT Err Cnt Ov */
9074 /* Bit 22: reserved */
9075 #define XMR_FCS_ERR_OV (1L<<21) /* Bit 21: Rx FCS Error Cnt Ov */
9076-#define XMR_LNG_ERR_OV (1L<<20) /* Bit 20: Rx too Long Err Cnt Ov*/
9077+#define XMR_LNG_ERR_OV (1L<<20) /* Bit 20: Rx too Long Err Cnt Ov */
9078 #define XMR_RUNT_OV (1L<<19) /* Bit 19: Runt Event Cnt Ov */
9079-#define XMR_SHT_ERR_OV (1L<<18) /* Bit 18: Rx Short Ev Err Cnt Ov*/
9080+#define XMR_SHT_ERR_OV (1L<<18) /* Bit 18: Rx Short Ev Err Cnt Ov */
9081 #define XMR_SYM_ERR_OV (1L<<17) /* Bit 17: Rx Sym Err Cnt Ov */
9082 /* Bit 16: reserved */
9083 #define XMR_CAR_ERR_OV (1L<<15) /* Bit 15: Rx Carr Ev Err Cnt Ov */
9084@@ -401,57 +402,57 @@
9085 #define XMR_FRA_ERR_OV (1L<<12) /* Bit 12: Rx Framing Err Cnt Ov */
9086 #define XMR_FMISS_OV (1L<<11) /* Bit 11: Rx Missed Ev Cnt Ov */
9087 #define XMR_BURST (1L<<10) /* Bit 10: Rx Burst Event Cnt Ov */
9088-#define XMR_INV_MOC (1L<<9) /* Bit 9: Rx with inv. MAC OC Ov*/
9089+#define XMR_INV_MOC (1L<<9) /* Bit 9: Rx with inv. MAC OC Ov */
9090 #define XMR_INV_MP (1L<<8) /* Bit 8: Rx inv Pause Frame Ov */
9091 #define XMR_MCTRL_OV (1L<<7) /* Bit 7: Rx MAC Ctrl-F Cnt Ov */
9092-#define XMR_MPAUSE_OV (1L<<6) /* Bit 6: Rx Pause MAC Ctrl-F Ov*/
9093-#define XMR_UC_OK_OV (1L<<5) /* Bit 5: Rx Unicast Frame CntOv*/
9094+#define XMR_MPAUSE_OV (1L<<6) /* Bit 6: Rx Pause MAC Ctrl-F Ov */
9095+#define XMR_UC_OK_OV (1L<<5) /* Bit 5: Rx Unicast Frame Cnt Ov */
9096 #define XMR_MC_OK_OV (1L<<4) /* Bit 4: Rx Multicast Cnt Ov */
9097 #define XMR_BC_OK_OV (1L<<3) /* Bit 3: Rx Broadcast Cnt Ov */
9098-#define XMR_OK_LO_OV (1L<<2) /* Bit 2: Octets Rx OK Low CntOv*/
9099-#define XMR_OK_HI_OV (1L<<1) /* Bit 1: Octets Rx OK Hi Cnt Ov*/
9100-#define XMR_OK_OV (1L<<0) /* Bit 0: Frames Received Ok Ov */
9101+#define XMR_OK_LO_OV (1L<<2) /* Bit 2: Octets Rx OK Low Cnt Ov */
9102+#define XMR_OK_HI_OV (1L<<1) /* Bit 1: Octets Rx OK High Cnt Ov */
9103+#define XMR_OK_OV (1L<<0) /* Bit 0: Frames Received OK Ov */
9104
9105 #define XMR_DEF_MSK (XMR_OK_LO_OV | XMR_OK_HI_OV)
9106
9107 /* XM_TX_CNT_EV 32 bit r/o Tx Counter Event Register */
9108 /* XM_TX_EV_MSK 32 bit r/w Tx Counter Event Mask */
9109 /* Bit 31..26: reserved */
9110-#define XMT_MAX_SZ_OV (1L<<25) /* Bit 25: 1024-MaxSize Tx Cnt Ov*/
9111-#define XMT_1023B_OV (1L<<24) /* Bit 24: 512-1023Byte Tx Cnt Ov*/
9112-#define XMT_511B_OV (1L<<23) /* Bit 23: 256-511 Byte Tx Cnt Ov*/
9113-#define XMT_255B_OV (1L<<22) /* Bit 22: 128-255 Byte Tx Cnt Ov*/
9114+#define XMT_MAX_SZ_OV (1L<<25) /* Bit 25: 1024-MaxSize Tx Cnt Ov */
9115+#define XMT_1023B_OV (1L<<24) /* Bit 24: 512-1023Byte Tx Cnt Ov */
9116+#define XMT_511B_OV (1L<<23) /* Bit 23: 256-511 Byte Tx Cnt Ov */
9117+#define XMT_255B_OV (1L<<22) /* Bit 22: 128-255 Byte Tx Cnt Ov */
9118 #define XMT_127B_OV (1L<<21) /* Bit 21: 65-127 Byte Tx Cnt Ov */
9119 #define XMT_64B_OV (1L<<20) /* Bit 20: 64 Byte Tx Cnt Ov */
9120 #define XMT_UTIL_OV (1L<<19) /* Bit 19: Tx Util Cnt Overflow */
9121 #define XMT_UTIL_UR (1L<<18) /* Bit 18: Tx Util Cnt Underrun */
9122-#define XMT_CS_ERR_OV (1L<<17) /* Bit 17: Tx Carr Sen Err Cnt Ov*/
9123+#define XMT_CS_ERR_OV (1L<<17) /* Bit 17: Tx Carr Sen Err Cnt Ov */
9124 #define XMT_FIFO_UR_OV (1L<<16) /* Bit 16: Tx FIFO Ur Ev Cnt Ov */
9125 #define XMT_EX_DEF_OV (1L<<15) /* Bit 15: Tx Ex Deferall Cnt Ov */
9126 #define XMT_DEF (1L<<14) /* Bit 14: Tx Deferred Cnt Ov */
9127 #define XMT_LAT_COL_OV (1L<<13) /* Bit 13: Tx Late Col Cnt Ov */
9128-#define XMT_ABO_COL_OV (1L<<12) /* Bit 12: Tx abo dueto Ex Col Ov*/
9129+#define XMT_ABO_COL_OV (1L<<12) /* Bit 12: Tx abo dueto Ex Col Ov */
9130 #define XMT_MUL_COL_OV (1L<<11) /* Bit 11: Tx Mult Col Cnt Ov */
9131 #define XMT_SNG_COL (1L<<10) /* Bit 10: Tx Single Col Cnt Ov */
9132-#define XMT_MCTRL_OV (1L<<9) /* Bit 9: Tx MAC Ctrl Counter Ov*/
9133-#define XMT_MPAUSE (1L<<8) /* Bit 8: Tx Pause MAC Ctrl-F Ov*/
9134+#define XMT_MCTRL_OV (1L<<9) /* Bit 9: Tx MAC Ctrl Counter Ov */
9135+#define XMT_MPAUSE (1L<<8) /* Bit 8: Tx Pause MAC Ctrl-F Ov */
9136 #define XMT_BURST (1L<<7) /* Bit 7: Tx Burst Event Cnt Ov */
9137 #define XMT_LONG (1L<<6) /* Bit 6: Tx Long Frame Cnt Ov */
9138 #define XMT_UC_OK_OV (1L<<5) /* Bit 5: Tx Unicast Cnt Ov */
9139 #define XMT_MC_OK_OV (1L<<4) /* Bit 4: Tx Multicast Cnt Ov */
9140 #define XMT_BC_OK_OV (1L<<3) /* Bit 3: Tx Broadcast Cnt Ov */
9141-#define XMT_OK_LO_OV (1L<<2) /* Bit 2: Octets Tx OK Low CntOv*/
9142-#define XMT_OK_HI_OV (1L<<1) /* Bit 1: Octets Tx OK Hi Cnt Ov*/
9143-#define XMT_OK_OV (1L<<0) /* Bit 0: Frames Tx Ok Ov */
9144+#define XMT_OK_LO_OV (1L<<2) /* Bit 2: Octets Tx OK Low Cnt Ov */
9145+#define XMT_OK_HI_OV (1L<<1) /* Bit 1: Octets Tx OK High Cnt Ov */
9146+#define XMT_OK_OV (1L<<0) /* Bit 0: Frames Tx OK Ov */
9147
9148 #define XMT_DEF_MSK (XMT_OK_LO_OV | XMT_OK_HI_OV)
9149
9150 /*
9151 * Receive Frame Status Encoding
9152 */
9153-#define XMR_FS_LEN (0x3fffUL<<18) /* Bit 31..18: Rx Frame Length */
9154-#define XMR_FS_2L_VLAN (1L<<17) /* Bit 17: tagged wh 2Lev VLAN ID*/
9155-#define XMR_FS_1L_VLAN (1L<<16) /* Bit 16: tagged wh 1Lev VLAN ID*/
9156+#define XMR_FS_LEN_MSK (0x3fffUL<<18) /* Bit 31..18: Rx Frame Length */
9157+#define XMR_FS_2L_VLAN (1L<<17) /* Bit 17: Tagged wh 2Lev VLAN ID */
9158+#define XMR_FS_1L_VLAN (1L<<16) /* Bit 16: Tagged wh 1Lev VLAN ID */
9159 #define XMR_FS_BC (1L<<15) /* Bit 15: Broadcast Frame */
9160 #define XMR_FS_MC (1L<<14) /* Bit 14: Multicast Frame */
9161 #define XMR_FS_UC (1L<<13) /* Bit 13: Unicast Frame */
9162@@ -469,6 +470,8 @@
9163 #define XMR_FS_ERR (1L<<1) /* Bit 1: Frame Error */
9164 #define XMR_FS_MCTRL (1L<<0) /* Bit 0: MAC Control Packet */
9165
9166+#define XMR_FS_LEN_SHIFT 18
9167+
9168 /*
9169 * XMR_FS_ERR will be set if
9170 * XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT,
9171@@ -488,7 +491,7 @@
9172 #define PHY_XMAC_ID0 0x02 /* 16 bit r/o PHY ID0 Register */
9173 #define PHY_XMAC_ID1 0x03 /* 16 bit r/o PHY ID1 Register */
9174 #define PHY_XMAC_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */
9175-#define PHY_XMAC_AUNE_LP 0x05 /* 16 bit r/o Link Partner Abi Reg */
9176+#define PHY_XMAC_AUNE_LP 0x05 /* 16 bit r/o Link Partner Ability Reg */
9177 #define PHY_XMAC_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */
9178 #define PHY_XMAC_NEPG 0x07 /* 16 bit r/w Next Page Register */
9179 #define PHY_XMAC_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */
9180@@ -505,12 +508,12 @@
9181 #define PHY_BCOM_ID0 0x02 /* 16 bit r/o PHY ID0 Register */
9182 #define PHY_BCOM_ID1 0x03 /* 16 bit r/o PHY ID1 Register */
9183 #define PHY_BCOM_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */
9184-#define PHY_BCOM_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */
9185+#define PHY_BCOM_AUNE_LP 0x05 /* 16 bit r/o Link Partner Ability Reg */
9186 #define PHY_BCOM_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */
9187 #define PHY_BCOM_NEPG 0x07 /* 16 bit r/w Next Page Register */
9188 #define PHY_BCOM_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */
9189 /* Broadcom-specific registers */
9190-#define PHY_BCOM_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Ctrl Reg */
9191+#define PHY_BCOM_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */
9192 #define PHY_BCOM_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */
9193 /* 0x0b - 0x0e: reserved */
9194 #define PHY_BCOM_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */
9195@@ -536,29 +539,37 @@
9196 #define PHY_MARV_ID0 0x02 /* 16 bit r/o PHY ID0 Register */
9197 #define PHY_MARV_ID1 0x03 /* 16 bit r/o PHY ID1 Register */
9198 #define PHY_MARV_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */
9199-#define PHY_MARV_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */
9200+#define PHY_MARV_AUNE_LP 0x05 /* 16 bit r/o Link Partner Ability Reg */
9201 #define PHY_MARV_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */
9202 #define PHY_MARV_NEPG 0x07 /* 16 bit r/w Next Page Register */
9203 #define PHY_MARV_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */
9204 /* Marvel-specific registers */
9205-#define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Ctrl Reg */
9206+#define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */
9207 #define PHY_MARV_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */
9208 /* 0x0b - 0x0e: reserved */
9209 #define PHY_MARV_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */
9210-#define PHY_MARV_PHY_CTRL 0x10 /* 16 bit r/w PHY Specific Ctrl Reg */
9211-#define PHY_MARV_PHY_STAT 0x11 /* 16 bit r/o PHY Specific Stat Reg */
9212+#define PHY_MARV_PHY_CTRL 0x10 /* 16 bit r/w PHY Specific Control Reg */
9213+#define PHY_MARV_PHY_STAT 0x11 /* 16 bit r/o PHY Specific Status Reg */
9214 #define PHY_MARV_INT_MASK 0x12 /* 16 bit r/w Interrupt Mask Reg */
9215 #define PHY_MARV_INT_STAT 0x13 /* 16 bit r/o Interrupt Status Reg */
9216 #define PHY_MARV_EXT_CTRL 0x14 /* 16 bit r/w Ext. PHY Specific Ctrl */
9217 #define PHY_MARV_RXE_CNT 0x15 /* 16 bit r/w Receive Error Counter */
9218 #define PHY_MARV_EXT_ADR 0x16 /* 16 bit r/w Ext. Ad. for Cable Diag. */
9219- /* 0x17: reserved */
9220+#define PHY_MARV_PORT_IRQ 0x17 /* 16 bit r/o Port 0 IRQ (88E1111 only) */
9221 #define PHY_MARV_LED_CTRL 0x18 /* 16 bit r/w LED Control Reg */
9222 #define PHY_MARV_LED_OVER 0x19 /* 16 bit r/w Manual LED Override Reg */
9223 #define PHY_MARV_EXT_CTRL_2 0x1a /* 16 bit r/w Ext. PHY Specific Ctrl 2 */
9224 #define PHY_MARV_EXT_P_STAT 0x1b /* 16 bit r/w Ext. PHY Spec. Stat Reg */
9225 #define PHY_MARV_CABLE_DIAG 0x1c /* 16 bit r/o Cable Diagnostic Reg */
9226- /* 0x1d - 0x1f: reserved */
9227+#define PHY_MARV_PAGE_ADDR 0x1d /* 16 bit r/w Extended Page Address Reg */
9228+#define PHY_MARV_PAGE_DATA 0x1e /* 16 bit r/w Extended Page Data Reg */
9229+
9230+/* for 10/100 Fast Ethernet PHY (88E3082 only) */
9231+#define PHY_MARV_FE_LED_PAR 0x16 /* 16 bit r/w LED Parallel Select Reg. */
9232+#define PHY_MARV_FE_LED_SER 0x17 /* 16 bit r/w LED Stream Select S. LED */
9233+#define PHY_MARV_FE_VCT_TX 0x1a /* 16 bit r/w VCT Reg. for TXP/N Pins */
9234+#define PHY_MARV_FE_VCT_RX 0x1b /* 16 bit r/o VCT Reg. for RXP/N Pins */
9235+#define PHY_MARV_FE_SPEC_2 0x1c /* 16 bit r/w Specific Control Reg. 2 */
9236
9237 /*----------------------------------------------------------------------------*/
9238 /*
9239@@ -569,14 +580,14 @@
9240 #define PHY_LONE_ID0 0x02 /* 16 bit r/o PHY ID0 Register */
9241 #define PHY_LONE_ID1 0x03 /* 16 bit r/o PHY ID1 Register */
9242 #define PHY_LONE_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */
9243-#define PHY_LONE_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */
9244+#define PHY_LONE_AUNE_LP 0x05 /* 16 bit r/o Link Partner Ability Reg */
9245 #define PHY_LONE_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */
9246 #define PHY_LONE_NEPG 0x07 /* 16 bit r/w Next Page Register */
9247 #define PHY_LONE_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */
9248 /* Level One-specific registers */
9249-#define PHY_LONE_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg*/
9250+#define PHY_LONE_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */
9251 #define PHY_LONE_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */
9252- /* 0x0b -0x0e: reserved */
9253+ /* 0x0b - 0x0e: reserved */
9254 #define PHY_LONE_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */
9255 #define PHY_LONE_PORT_CFG 0x10 /* 16 bit r/w Port Configuration Reg*/
9256 #define PHY_LONE_Q_STAT 0x11 /* 16 bit r/o Quick Status Reg */
9257@@ -585,7 +596,7 @@
9258 #define PHY_LONE_LED_CFG 0x14 /* 16 bit r/w LED Configuration Reg */
9259 #define PHY_LONE_PORT_CTRL 0x15 /* 16 bit r/w Port Control Reg */
9260 #define PHY_LONE_CIM 0x16 /* 16 bit r/o CIM Reg */
9261- /* 0x17 -0x1c: reserved */
9262+ /* 0x17 - 0x1c: reserved */
9263
9264 /*----------------------------------------------------------------------------*/
9265 /*
9266@@ -603,14 +614,14 @@
9267 /* National-specific registers */
9268 #define PHY_NAT_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */
9269 #define PHY_NAT_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */
9270- /* 0x0b -0x0e: reserved */
9271+ /* 0x0b - 0x0e: reserved */
9272 #define PHY_NAT_EXT_STAT 0x0f /* 16 bit r/o Extended Status Register */
9273 #define PHY_NAT_EXT_CTRL1 0x10 /* 16 bit r/o Extended Control Reg1 */
9274 #define PHY_NAT_Q_STAT1 0x11 /* 16 bit r/o Quick Status Reg1 */
9275 #define PHY_NAT_10B_OP 0x12 /* 16 bit r/o 10Base-T Operations Reg */
9276 #define PHY_NAT_EXT_CTRL2 0x13 /* 16 bit r/o Extended Control Reg1 */
9277 #define PHY_NAT_Q_STAT2 0x14 /* 16 bit r/o Quick Status Reg2 */
9278- /* 0x15 -0x18: reserved */
9279+ /* 0x15 - 0x18: reserved */
9280 #define PHY_NAT_PHY_ADDR 0x19 /* 16 bit r/o PHY Address Register */
9281
9282
9283@@ -618,7 +629,7 @@
9284
9285 /*
9286 * PHY bit definitions
9287- * Bits defined as PHY_X_..., PHY_B_..., PHY_L_... or PHY_N_... are
9288+ * Bits defined as PHY_X_..., PHY_B_..., PHY_L_..., PHY_N_... or PHY_M_... are
9289 * XMAC/Broadcom/LevelOne/National/Marvell-specific.
9290 * All other are general.
9291 */
9292@@ -629,14 +640,14 @@
9293 /***** PHY_LONE_CTRL 16 bit r/w PHY Control Register *****/
9294 #define PHY_CT_RESET (1<<15) /* Bit 15: (sc) clear all PHY related regs */
9295 #define PHY_CT_LOOP (1<<14) /* Bit 14: enable Loopback over PHY */
9296-#define PHY_CT_SPS_LSB (1<<13) /* Bit 13: (BC,L1) Speed select, lower bit */
9297+#define PHY_CT_SPS_LSB (1<<13) /* Bit 13: Speed select, lower bit */
9298 #define PHY_CT_ANE (1<<12) /* Bit 12: Auto-Negotiation Enabled */
9299-#define PHY_CT_PDOWN (1<<11) /* Bit 11: (BC,L1) Power Down Mode */
9300-#define PHY_CT_ISOL (1<<10) /* Bit 10: (BC,L1) Isolate Mode */
9301-#define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Auto-Negotiation */
9302+#define PHY_CT_PDOWN (1<<11) /* Bit 11: Power Down Mode */
9303+#define PHY_CT_ISOL (1<<10) /* Bit 10: Isolate Mode */
9304+#define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Auto-Negotiation */
9305 #define PHY_CT_DUP_MD (1<<8) /* Bit 8: Duplex Mode */
9306-#define PHY_CT_COL_TST (1<<7) /* Bit 7: (BC,L1) Collision Test enabled */
9307-#define PHY_CT_SPS_MSB (1<<6) /* Bit 6: (BC,L1) Speed select, upper bit */
9308+#define PHY_CT_COL_TST (1<<7) /* Bit 7: Collision Test enabled */
9309+#define PHY_CT_SPS_MSB (1<<6) /* Bit 6: Speed select, upper bit */
9310 /* Bit 5..0: reserved */
9311
9312 #define PHY_CT_SP1000 PHY_CT_SPS_MSB /* enable speed of 1000 Mbps */
9313@@ -649,25 +660,25 @@
9314 /***** PHY_MARV_STAT 16 bit r/w PHY Status Register *****/
9315 /***** PHY_LONE_STAT 16 bit r/w PHY Status Register *****/
9316 /* Bit 15..9: reserved */
9317- /* (BC/L1) 100/10 Mbps cap bits ignored*/
9318+ /* (BC/L1) 100/10 Mbps cap bits ignored */
9319 #define PHY_ST_EXT_ST (1<<8) /* Bit 8: Extended Status Present */
9320 /* Bit 7: reserved */
9321-#define PHY_ST_PRE_SUP (1<<6) /* Bit 6: (BC/L1) preamble suppression */
9322+#define PHY_ST_PRE_SUP (1<<6) /* Bit 6: Preamble Suppression */
9323 #define PHY_ST_AN_OVER (1<<5) /* Bit 5: Auto-Negotiation Over */
9324 #define PHY_ST_REM_FLT (1<<4) /* Bit 4: Remote Fault Condition Occured */
9325 #define PHY_ST_AN_CAP (1<<3) /* Bit 3: Auto-Negotiation Capability */
9326 #define PHY_ST_LSYNC (1<<2) /* Bit 2: Link Synchronized */
9327-#define PHY_ST_JAB_DET (1<<1) /* Bit 1: (BC/L1) Jabber Detected */
9328+#define PHY_ST_JAB_DET (1<<1) /* Bit 1: Jabber Detected */
9329 #define PHY_ST_EXT_REG (1<<0) /* Bit 0: Extended Register available */
9330
9331
9332-/***** PHY_XMAC_ID1 16 bit r/o PHY ID1 Register */
9333-/***** PHY_BCOM_ID1 16 bit r/o PHY ID1 Register */
9334-/***** PHY_MARV_ID1 16 bit r/o PHY ID1 Register */
9335-/***** PHY_LONE_ID1 16 bit r/o PHY ID1 Register */
9336+/***** PHY_XMAC_ID1 16 bit r/o PHY ID1 Register */
9337+/***** PHY_BCOM_ID1 16 bit r/o PHY ID1 Register */
9338+/***** PHY_MARV_ID1 16 bit r/o PHY ID1 Register */
9339+/***** PHY_LONE_ID1 16 bit r/o PHY ID1 Register */
9340 #define PHY_I1_OUI_MSK (0x3f<<10) /* Bit 15..10: Organization Unique ID */
9341 #define PHY_I1_MOD_NUM (0x3f<<4) /* Bit 9.. 4: Model Number */
9342-#define PHY_I1_REV_MSK 0x0f /* Bit 3.. 0: Revision Number */
9343+#define PHY_I1_REV_MSK 0xf /* Bit 3.. 0: Revision Number */
9344
9345 /* different Broadcom PHY Ids */
9346 #define PHY_BCOM_ID1_A1 0x6041
9347@@ -675,11 +686,21 @@
9348 #define PHY_BCOM_ID1_C0 0x6044
9349 #define PHY_BCOM_ID1_C5 0x6047
9350
9351+/* different Marvell PHY Ids */
9352+#define PHY_MARV_ID0_VAL 0x0141 /* Marvell Unique Identifier */
9353+
9354+#define PHY_MARV_ID1_B0 0x0C23 /* Yukon (PHY 88E1040 Rev.C0) */
9355+#define PHY_MARV_ID1_B2 0x0C25 /* Yukon-Plus (PHY 88E1040 Rev.D0) */
9356+#define PHY_MARV_ID1_C2 0x0CC2 /* Yukon-EC (PHY 88E1111 Rev.B1) */
9357+#define PHY_MARV_ID1_Y2 0x0C91 /* Yukon-XL (PHY 88E1112 Rev.B0) */
9358+#define PHY_MARV_ID1_FE 0x0C83 /* Yukon-FE (PHY 88E3082 Rev.A1) */
9359+#define PHY_MARV_ID1_ECU 0x0CB0 /* Yukon-ECU (PHY 88E1149 Rev.B2?) */
9360+
9361
9362 /***** PHY_XMAC_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
9363 /***** PHY_XMAC_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/
9364 #define PHY_AN_NXT_PG (1<<15) /* Bit 15: Request Next Page */
9365-#define PHY_X_AN_ACK (1<<14) /* Bit 14: (ro) Acknowledge Received */
9366+#define PHY_X_AN_ACK (1<<14) /* Bit 14: (ro) Acknowledge Received */
9367 #define PHY_X_AN_RFB (3<<12) /* Bit 13..12: Remote Fault Bits */
9368 /* Bit 11.. 9: reserved */
9369 #define PHY_X_AN_PAUSE (3<<7) /* Bit 8.. 7: Pause Bits */
9370@@ -738,7 +759,7 @@
9371 /* PHY_ANE_LP_NP (see XMAC) Bit 3: Link Partner can Next Page */
9372 /* PHY_ANE_LOC_NP (see XMAC) Bit 2: Local PHY can Next Page */
9373 /* PHY_ANE_RX_PG (see XMAC) Bit 1: Page Received */
9374-#define PHY_ANE_LP_CAP (1<<0) /* Bit 0: Link Partner Auto-Neg. Cap. */
9375+#define PHY_ANE_LP_CAP (1<<0) /* Bit 0: Link Partner Auto-Neg. Able */
9376
9377 /***** PHY_XMAC_NEPG 16 bit r/w Next Page Register *****/
9378 /***** PHY_BCOM_NEPG 16 bit r/w Next Page Register *****/
9379@@ -827,7 +848,7 @@
9380 #define PHY_B_PEC_BY_MLT3 (1<<8) /* Bit 8: Bypass MLT3 Encoder */
9381 #define PHY_B_PEC_BY_RXA (1<<7) /* Bit 7: Bypass Rx Alignm. */
9382 #define PHY_B_PEC_RES_SCR (1<<6) /* Bit 6: Reset Scrambler */
9383-#define PHY_B_PEC_EN_LTR (1<<5) /* Bit 5: Ena LED Traffic Mode */
9384+#define PHY_B_PEC_EN_LTR (1<<5) /* Bit 5: Enable LED Traffic Mode */
9385 #define PHY_B_PEC_LED_ON (1<<4) /* Bit 4: Force LED's on */
9386 #define PHY_B_PEC_LED_OFF (1<<3) /* Bit 3: Force LED's off */
9387 #define PHY_B_PEC_EX_IPG (1<<2) /* Bit 2: Extend Tx IPG Mode */
9388@@ -981,7 +1002,7 @@
9389 #define PHY_L_QS_DUP_MOD (1<<9) /* Bit 9: Full/Half Duplex */
9390 #define PHY_L_QS_AN (1<<8) /* Bit 8: AutoNeg is On */
9391 #define PHY_L_QS_AN_C (1<<7) /* Bit 7: AN is Complete */
9392-#define PHY_L_QS_LLE (7<<4) /* Bit 6: Line Length Estim. */
9393+#define PHY_L_QS_LLE (7<<4) /* Bit 6..4: Line Length Estim. */
9394 #define PHY_L_QS_PAUSE (1<<3) /* Bit 3: LP advertised Pause */
9395 #define PHY_L_QS_AS_PAUSE (1<<2) /* Bit 2: LP adv. asym. Pause */
9396 #define PHY_L_QS_ISOLATE (1<<1) /* Bit 1: CIM Isolated */
9397@@ -1029,9 +1050,8 @@
9398 /* Bit 9..0: not described */
9399
9400 /***** PHY_LONE_CIM 16 bit r/o CIM Reg *****/
9401-#define PHY_L_CIM_ISOL (255<<8)/* Bit 15..8: Isolate Count */
9402-#define PHY_L_CIM_FALSE_CAR (255<<0)/* Bit 7..0: False Carrier Count */
9403-
9404+#define PHY_L_CIM_ISOL (0xff<<8) /* Bit 15..8: Isolate Count */
9405+#define PHY_L_CIM_FALSE_CAR 0xff /* Bit 7..0: False Carrier Count */
9406
9407 /*
9408 * Pause Bits (PHY_L_AN_ASP and PHY_L_AN_PC) encoding
9409@@ -1041,7 +1061,6 @@
9410 #define PHY_L_P_ASYM_MD (2<<10) /* Bit 11..10: asymmetric Pause Mode */
9411 #define PHY_L_P_BOTH_MD (3<<10) /* Bit 11..10: both Pause Mode */
9412
9413-
9414 /*
9415 * National-Specific
9416 */
9417@@ -1085,23 +1104,25 @@
9418 * Marvell-Specific
9419 */
9420 /***** PHY_MARV_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
9421-/***** PHY_MARV_AUNE_LP 16 bit r/w Link Part Ability Reg *****/
9422-#define PHY_M_AN_NXT_PG BIT_15 /* Request Next Page */
9423-#define PHY_M_AN_ACK BIT_14 /* (ro) Acknowledge Received */
9424-#define PHY_M_AN_RF BIT_13 /* Remote Fault */
9425- /* Bit 12: reserved */
9426-#define PHY_M_AN_ASP BIT_11 /* Asymmetric Pause */
9427-#define PHY_M_AN_PC BIT_10 /* MAC Pause implemented */
9428-#define PHY_M_AN_100_FD BIT_8 /* Advertise 100Base-TX Full Duplex */
9429-#define PHY_M_AN_100_HD BIT_7 /* Advertise 100Base-TX Half Duplex */
9430-#define PHY_M_AN_10_FD BIT_6 /* Advertise 10Base-TX Full Duplex */
9431-#define PHY_M_AN_10_HD BIT_5 /* Advertise 10Base-TX Half Duplex */
9432-
9433-/* special defines for FIBER (88E1011S only) */
9434-#define PHY_M_AN_ASP_X BIT_8 /* Asymmetric Pause */
9435-#define PHY_M_AN_PC_X BIT_7 /* MAC Pause implemented */
9436-#define PHY_M_AN_1000X_AHD BIT_6 /* Advertise 10000Base-X Half Duplex */
9437-#define PHY_M_AN_1000X_AFD BIT_5 /* Advertise 10000Base-X Full Duplex */
9438+/***** PHY_MARV_AUNE_LP 16 bit r/w Link Partner Ability Reg *****/
9439+#define PHY_M_AN_NXT_PG BIT_15S /* Request Next Page */
9440+#define PHY_M_AN_ACK BIT_14S /* (ro) Acknowledge Received */
9441+#define PHY_M_AN_RF BIT_13S /* Remote Fault */
9442+ /* Bit 12: reserved */
9443+#define PHY_M_AN_ASP BIT_11S /* Asymmetric Pause */
9444+#define PHY_M_AN_PC BIT_10S /* MAC Pause implemented */
9445+#define PHY_M_AN_100_T4 BIT_9S /* Not cap. 100Base-T4 (always 0) */
9446+#define PHY_M_AN_100_FD BIT_8S /* Advertise 100Base-TX Full Duplex */
9447+#define PHY_M_AN_100_HD BIT_7S /* Advertise 100Base-TX Half Duplex */
9448+#define PHY_M_AN_10_FD BIT_6S /* Advertise 10Base-TX Full Duplex */
9449+#define PHY_M_AN_10_HD BIT_5S /* Advertise 10Base-TX Half Duplex */
9450+#define PHY_M_AN_SEL_MSK (0x1f<<4) /* Bit 4.. 0: Selector Field Mask */
9451+
9452+/* special defines for FIBER (88E1040S only) */
9453+#define PHY_M_AN_ASP_X BIT_8S /* Asymmetric Pause */
9454+#define PHY_M_AN_PC_X BIT_7S /* MAC Pause implemented */
9455+#define PHY_M_AN_1000X_AHD BIT_6S /* Advertise 10000Base-X Half Duplex */
9456+#define PHY_M_AN_1000X_AFD BIT_5S /* Advertise 10000Base-X Full Duplex */
9457
9458 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
9459 #define PHY_M_P_NO_PAUSE_X (0<<7) /* Bit 8.. 7: no Pause Mode */
9460@@ -1111,105 +1132,168 @@
9461
9462 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
9463 #define PHY_M_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */
9464-#define PHY_M_1000C_MSE (1<<12) /* Bit 12: Manual Master/Slave Enable */
9465-#define PHY_M_1000C_MSC (1<<11) /* Bit 11: M/S Configuration (1=Master) */
9466-#define PHY_M_1000C_MPD (1<<10) /* Bit 10: Multi-Port Device */
9467-#define PHY_M_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */
9468-#define PHY_M_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */
9469+#define PHY_M_1000C_MSE BIT_12S /* Manual Master/Slave Enable */
9470+#define PHY_M_1000C_MSC BIT_11S /* M/S Configuration (1=Master) */
9471+#define PHY_M_1000C_MPD BIT_10S /* Multi-Port Device */
9472+#define PHY_M_1000C_AFD BIT_9S /* Advertise Full Duplex */
9473+#define PHY_M_1000C_AHD BIT_8S /* Advertise Half Duplex */
9474 /* Bit 7..0: reserved */
9475
9476 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
9477-#define PHY_M_PC_TX_FFD_MSK (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */
9478-#define PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */
9479-#define PHY_M_PC_ASS_CRS_TX (1<<11) /* Bit 11: Assert CRS on Transmit */
9480-#define PHY_M_PC_FL_GOOD (1<<10) /* Bit 10: Force Link Good */
9481-#define PHY_M_PC_EN_DET_MSK (3<<8) /* Bit 9.. 8: Energy Detect Mask */
9482-#define PHY_M_PC_ENA_EXT_D (1<<7) /* Bit 7: Enable Ext. Distance (10BT) */
9483-#define PHY_M_PC_MDIX_MSK (3<<5) /* Bit 6.. 5: MDI/MDIX Config. Mask */
9484-#define PHY_M_PC_DIS_125CLK (1<<4) /* Bit 4: Disable 125 CLK */
9485-#define PHY_M_PC_MAC_POW_UP (1<<3) /* Bit 3: MAC Power up */
9486-#define PHY_M_PC_SQE_T_ENA (1<<2) /* Bit 2: SQE Test Enabled */
9487-#define PHY_M_PC_POL_R_DIS (1<<1) /* Bit 1: Polarity Reversal Disabled */
9488-#define PHY_M_PC_DIS_JABBER (1<<0) /* Bit 0: Disable Jabber */
9489+#define PHY_M_PC_TX_FFD_MSK (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */
9490+#define PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */
9491+#define PHY_M_PC_ASS_CRS_TX BIT_11S /* Assert CRS on Transmit */
9492+#define PHY_M_PC_FL_GOOD BIT_10S /* Force Link Good */
9493+#define PHY_M_PC_EN_DET_MSK (3<<8) /* Bit 9.. 8: Energy Detect Mask */
9494+#define PHY_M_PC_ENA_EXT_D BIT_7S /* Enable Ext. Distance (10BT) */
9495+#define PHY_M_PC_MDIX_MSK (3<<5) /* Bit 6.. 5: MDI/MDIX Config. Mask */
9496+#define PHY_M_PC_DIS_125CLK BIT_4S /* Disable 125 CLK */
9497+#define PHY_M_PC_MAC_POW_UP BIT_3S /* MAC Power up */
9498+#define PHY_M_PC_SQE_T_ENA BIT_2S /* SQE Test Enabled */
9499+#define PHY_M_PC_POL_R_DIS BIT_1S /* Polarity Reversal Disabled */
9500+#define PHY_M_PC_DIS_JABBER BIT_0S /* Disable Jabber */
9501
9502 #define PHY_M_PC_EN_DET SHIFT8(2) /* Energy Detect (Mode 1) */
9503 #define PHY_M_PC_EN_DET_PLUS SHIFT8(3) /* Energy Detect Plus (Mode 2) */
9504
9505-#define PHY_M_PC_MDI_XMODE(x) SHIFT5(x)
9506-#define PHY_M_PC_MAN_MDI 0 /* 00 = Manual MDI configuration */
9507+#define PHY_M_PC_MDI_XMODE(x) (SHIFT5(x) & PHY_M_PC_MDIX_MSK)
9508+
9509+#define PHY_M_PC_MAN_MDI 0 /* 00 = Manual MDI configuration */
9510 #define PHY_M_PC_MAN_MDIX 1 /* 01 = Manual MDIX configuration */
9511 #define PHY_M_PC_ENA_AUTO 3 /* 11 = Enable Automatic Crossover */
9512
9513+/* for Yukon-2/-EC Ultra Gigabit Ethernet PHY (88E1112/88E1149 only) */
9514+#define PHY_M_PC_DIS_LINK_P BIT_15S /* Disable Link Pulses */
9515+#define PHY_M_PC_DSC_MSK (7<<12) /* Bit 14..12: Downshift Counter */
9516+#define PHY_M_PC_DOWN_S_ENA BIT_11S /* Downshift Enable */
9517+ /* !!! Errata in spec. (1 = disable) */
9518+
9519+#define PHY_M_PC_DSC(x) (SHIFT12(x) & PHY_M_PC_DSC_MSK)
9520+ /* 000=1x; 001=2x; 010=3x; 011=4x */
9521+ /* 100=5x; 101=6x; 110=7x; 111=8x */
9522+
9523+/* for Yukon-EC Ultra Gigabit Ethernet PHY (88E1149 only) */
9524+ /* Bit 4: reserved */
9525+#define PHY_M_PC_COP_TX_DIS BIT_3S /* Copper Transmitter Disable */
9526+#define PHY_M_PC_POW_D_ENA BIT_2S /* Power Down Enable */
9527+
9528+/* for 10/100 Fast Ethernet PHY (88E3082 only) */
9529+#define PHY_M_PC_ENA_DTE_DT BIT_15S /* Enable Data Terminal Equ. (DTE) Detect */
9530+#define PHY_M_PC_ENA_ENE_DT BIT_14S /* Enable Energy Detect (sense & pulse) */
9531+#define PHY_M_PC_DIS_NLP_CK BIT_13S /* Disable Normal Link Puls (NLP) Check */
9532+#define PHY_M_PC_ENA_LIP_NP BIT_12S /* Enable Link Partner Next Page Reg. */
9533+#define PHY_M_PC_DIS_NLP_GN BIT_11S /* Disable Normal Link Puls Generation */
9534+
9535+#define PHY_M_PC_DIS_SCRAMB BIT_9S /* Disable Scrambler */
9536+#define PHY_M_PC_DIS_FEFI BIT_8S /* Disable Far End Fault Indic. (FEFI) */
9537+
9538+#define PHY_M_PC_SH_TP_SEL BIT_6S /* Shielded Twisted Pair Select */
9539+#define PHY_M_PC_RX_FD_MSK (3<<2) /* Bit 3.. 2: Rx FIFO Depth Mask */
9540+
9541 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
9542-#define PHY_M_PS_SPEED_MSK (3<<14) /* Bit 15..14: Speed Mask */
9543-#define PHY_M_PS_SPEED_1000 (1<<15) /* 10 = 1000 Mbps */
9544-#define PHY_M_PS_SPEED_100 (1<<14) /* 01 = 100 Mbps */
9545-#define PHY_M_PS_SPEED_10 0 /* 00 = 10 Mbps */
9546-#define PHY_M_PS_FULL_DUP (1<<13) /* Bit 13: Full Duplex */
9547-#define PHY_M_PS_PAGE_REC (1<<12) /* Bit 12: Page Received */
9548-#define PHY_M_PS_SPDUP_RES (1<<11) /* Bit 11: Speed & Duplex Resolved */
9549-#define PHY_M_PS_LINK_UP (1<<10) /* Bit 10: Link Up */
9550-#define PHY_M_PS_CABLE_MSK (3<<7) /* Bit 9.. 7: Cable Length Mask */
9551-#define PHY_M_PS_MDI_X_STAT (1<<6) /* Bit 6: MDI Crossover Stat (1=MDIX) */
9552-#define PHY_M_PS_DOWNS_STAT (1<<5) /* Bit 5: Downshift Status (1=downsh.) */
9553-#define PHY_M_PS_ENDET_STAT (1<<4) /* Bit 4: Energy Detect Status (1=act) */
9554-#define PHY_M_PS_TX_P_EN (1<<3) /* Bit 3: Tx Pause Enabled */
9555-#define PHY_M_PS_RX_P_EN (1<<2) /* Bit 2: Rx Pause Enabled */
9556-#define PHY_M_PS_POL_REV (1<<1) /* Bit 1: Polarity Reversed */
9557-#define PHY_M_PC_JABBER (1<<0) /* Bit 0: Jabber */
9558+#define PHY_M_PS_SPEED_MSK (3<<14) /* Bit 15..14: Speed Mask */
9559+#define PHY_M_PS_SPEED_1000 BIT_15S /* 10 = 1000 Mbps */
9560+#define PHY_M_PS_SPEED_100 BIT_14S /* 01 = 100 Mbps */
9561+#define PHY_M_PS_SPEED_10 0 /* 00 = 10 Mbps */
9562+#define PHY_M_PS_FULL_DUP BIT_13S /* Full Duplex */
9563+#define PHY_M_PS_PAGE_REC BIT_12S /* Page Received */
9564+#define PHY_M_PS_SPDUP_RES BIT_11S /* Speed & Duplex Resolved */
9565+#define PHY_M_PS_LINK_UP BIT_10S /* Link Up */
9566+#define PHY_M_PS_CABLE_MSK (7<<7) /* Bit 9.. 7: Cable Length Mask */
9567+#define PHY_M_PS_MDI_X_STAT BIT_6S /* MDI Crossover Stat (1=MDIX) */
9568+#define PHY_M_PS_DOWNS_STAT BIT_5S /* Downshift Status (1=downsh.) */
9569+#define PHY_M_PS_ENDET_STAT BIT_4S /* Energy Detect Status (1=act) */
9570+#define PHY_M_PS_TX_P_EN BIT_3S /* Tx Pause Enabled */
9571+#define PHY_M_PS_RX_P_EN BIT_2S /* Rx Pause Enabled */
9572+#define PHY_M_PS_POL_REV BIT_1S /* Polarity Reversed */
9573+#define PHY_M_PS_JABBER BIT_0S /* Jabber */
9574
9575 #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
9576
9577+/* for 10/100 Fast Ethernet PHY (88E3082 only) */
9578+#define PHY_M_PS_DTE_DETECT BIT_15S /* Data Terminal Equipment (DTE) Detected */
9579+#define PHY_M_PS_RES_SPEED BIT_14S /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
9580+
9581 /***** PHY_MARV_INT_MASK 16 bit r/w Interrupt Mask Reg *****/
9582 /***** PHY_MARV_INT_STAT 16 bit r/o Interrupt Status Reg *****/
9583-#define PHY_M_IS_AN_ERROR (1<<15) /* Bit 15: Auto-Negotiation Error */
9584-#define PHY_M_IS_LSP_CHANGE (1<<14) /* Bit 14: Link Speed Changed */
9585-#define PHY_M_IS_DUP_CHANGE (1<<13) /* Bit 13: Duplex Mode Changed */
9586-#define PHY_M_IS_AN_PR (1<<12) /* Bit 12: Page Received */
9587-#define PHY_M_IS_AN_COMPL (1<<11) /* Bit 11: Auto-Negotiation Completed */
9588-#define PHY_M_IS_LST_CHANGE (1<<10) /* Bit 10: Link Status Changed */
9589-#define PHY_M_IS_SYMB_ERROR (1<<9) /* Bit 9: Symbol Error */
9590-#define PHY_M_IS_FALSE_CARR (1<<8) /* Bit 8: False Carrier */
9591-#define PHY_M_IS_FIFO_ERROR (1<<7) /* Bit 7: FIFO Overflow/Underrun Error */
9592-#define PHY_M_IS_MDI_CHANGE (1<<6) /* Bit 6: MDI Crossover Changed */
9593-#define PHY_M_IS_DOWNSH_DET (1<<5) /* Bit 5: Downshift Detected */
9594-#define PHY_M_IS_END_CHANGE (1<<4) /* Bit 4: Energy Detect Changed */
9595- /* Bit 3..2: reserved */
9596-#define PHY_M_IS_POL_CHANGE (1<<1) /* Bit 1: Polarity Changed */
9597-#define PHY_M_IS_JABBER (1<<0) /* Bit 0: Jabber */
9598+#define PHY_M_IS_AN_ERROR BIT_15S /* Auto-Negotiation Error */
9599+#define PHY_M_IS_LSP_CHANGE BIT_14S /* Link Speed Changed */
9600+#define PHY_M_IS_DUP_CHANGE BIT_13S /* Duplex Mode Changed */
9601+#define PHY_M_IS_AN_PR BIT_12S /* Page Received */
9602+#define PHY_M_IS_AN_COMPL BIT_11S /* Auto-Negotiation Completed */
9603+#define PHY_M_IS_LST_CHANGE BIT_10S /* Link Status Changed */
9604+#define PHY_M_IS_SYMB_ERROR BIT_9S /* Symbol Error */
9605+#define PHY_M_IS_FALSE_CARR BIT_8S /* False Carrier */
9606+#define PHY_M_IS_FIFO_ERROR BIT_7S /* FIFO Overflow/Underrun Error */
9607+#define PHY_M_IS_MDI_CHANGE BIT_6S /* MDI Crossover Changed */
9608+#define PHY_M_IS_DOWNSH_DET BIT_5S /* Downshift Detected */
9609+#define PHY_M_IS_END_CHANGE BIT_4S /* Energy Detect Changed */
9610+ /* Bit 3: reserved */
9611+#define PHY_M_IS_DTE_CHANGE BIT_2S /* DTE Power Det. Status Changed */
9612+ /* (88E1111 only) */
9613+#define PHY_M_IS_POL_CHANGE BIT_1S /* Polarity Changed */
9614+#define PHY_M_IS_JABBER BIT_0S /* Jabber */
9615
9616 #define PHY_M_DEF_MSK (PHY_M_IS_AN_ERROR | PHY_M_IS_AN_PR | \
9617- PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR)
9618+ PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR | \
9619+ PHY_M_IS_END_CHANGE)
9620
9621 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
9622-#define PHY_M_EC_M_DSC_MSK (3<<10) /* Bit 11..10: Master downshift counter */
9623-#define PHY_M_EC_S_DSC_MSK (3<<8) /* Bit 9.. 8: Slave downshift counter */
9624+#define PHY_M_EC_ENA_BC_EXT BIT_15S /* Enable Block Carr. Ext. (88E1111 only) */
9625+#define PHY_M_EC_ENA_LIN_LB BIT_14S /* Enable Line Loopback (88E1111 only) */
9626+ /* Bit 13: reserved */
9627+#define PHY_M_EC_DIS_LINK_P BIT_12S /* Disable Link Pulses (88E1111 only) */
9628+#define PHY_M_EC_M_DSC_MSK (3<<10) /* Bit 11..10: Master Downshift Counter */
9629+ /* (88E1040 Rev.C0 only) */
9630+#define PHY_M_EC_S_DSC_MSK (3<<8) /* Bit 9.. 8: Slave Downshift Counter */
9631+ /* (88E1040 Rev.C0 only) */
9632+#define PHY_M_EC_DSC_MSK_2 (7<<9) /* Bit 11.. 9: Downshift Counter */
9633+ /* (88E1040 Rev.D0 and higher) */
9634+#define PHY_M_EC_DOWN_S_ENA BIT_8S /* Downshift Enable (88E1040 Rev.D0 and */
9635+ /* 88E1111 !!! Errata in spec. (1=dis.) */
9636+#define PHY_M_EC_RX_TIM_CT BIT_7S /* RGMII Rx Timing Control*/
9637 #define PHY_M_EC_MAC_S_MSK (7<<4) /* Bit 6.. 4: Def. MAC interface speed */
9638-#define PHY_M_EC_FIB_AN_ENA (1<<3) /* Bit 3: Fiber Auto-Neg. Enable */
9639-
9640-#define PHY_M_EC_M_DSC(x) SHIFT10(x) /* 00=1x; 01=2x; 10=3x; 11=4x */
9641-#define PHY_M_EC_S_DSC(x) SHIFT8(x) /* 00=dis; 01=1x; 10=2x; 11=3x */
9642-#define PHY_M_EC_MAC_S(x) SHIFT4(x) /* 01X=0; 110=2.5; 111=25 (MHz) */
9643-
9644+#define PHY_M_EC_FIB_AN_ENA BIT_3S /* Fiber Auto-Neg. Enable 88E1040S only) */
9645+#define PHY_M_EC_DTE_D_ENA BIT_2S /* DTE Detect Enable (88E1111 only) */
9646+#define PHY_M_EC_TX_TIM_CT BIT_1S /* RGMII Tx Timing Control */
9647+#define PHY_M_EC_TRANS_DIS BIT_0S /* Transmitter Disable (88E1111 only) */
9648+
9649+#define PHY_M_EC_M_DSC(x) (SHIFT10(x) & PHY_M_EC_M_DSC_MSK)
9650+ /* 00=1x; 01=2x; 10=3x; 11=4x */
9651+#define PHY_M_EC_S_DSC(x) (SHIFT8(x) & PHY_M_EC_S_DSC_MSK)
9652+ /* 00=dis; 01=1x; 10=2x; 11=3x */
9653+#define PHY_M_EC_MAC_S(x) (SHIFT4(x) & PHY_M_EC_MAC_S_MSK)
9654+ /* 01X=0; 110=2.5; 111=25 (MHz) */
9655+
9656+#define PHY_M_EC_DSC_2(x) (SHIFT9(x) & PHY_M_EC_DSC_MSK_2)
9657+ /* 000=1x; 001=2x; 010=3x; 011=4x */
9658+ /* 100=5x; 101=6x; 110=7x; 111=8x */
9659 #define MAC_TX_CLK_0_MHZ 2
9660 #define MAC_TX_CLK_2_5_MHZ 6
9661 #define MAC_TX_CLK_25_MHZ 7
9662
9663 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
9664-#define PHY_M_LEDC_DIS_LED (1<<15) /* Bit 15: Disable LED */
9665-#define PHY_M_LEDC_PULS_MSK (7<<12) /* Bit 14..12: Pulse Stretch Mask */
9666-#define PHY_M_LEDC_F_INT (1<<11) /* Bit 11: Force Interrupt */
9667-#define PHY_M_LEDC_BL_R_MSK (7<<8) /* Bit 10.. 8: Blink Rate Mask */
9668- /* Bit 7.. 5: reserved */
9669-#define PHY_M_LEDC_LINK_MSK (3<<3) /* Bit 4.. 3: Link Control Mask */
9670-#define PHY_M_LEDC_DP_CTRL (1<<2) /* Bit 2: Duplex Control */
9671-#define PHY_M_LEDC_RX_CTRL (1<<1) /* Bit 1: Rx activity / Link */
9672-#define PHY_M_LEDC_TX_CTRL (1<<0) /* Bit 0: Tx activity / Link */
9673+#define PHY_M_LEDC_DIS_LED BIT_15S /* Disable LED */
9674+#define PHY_M_LEDC_PULS_MSK (7<<12) /* Bit 14..12: Pulse Stretch Mask */
9675+#define PHY_M_LEDC_F_INT BIT_11S /* Force Interrupt */
9676+#define PHY_M_LEDC_BL_R_MSK (7<<8) /* Bit 10.. 8: Blink Rate Mask */
9677+#define PHY_M_LEDC_DP_C_LSB BIT_7S /* Duplex Control (LSB, 88E1111 only) */
9678+#define PHY_M_LEDC_TX_C_LSB BIT_6S /* Tx Control (LSB, 88E1111 only) */
9679+#define PHY_M_LEDC_LK_C_MSK (7<<3) /* Bit 5.. 3: Link Control Mask */
9680+ /* (88E1111 only) */
9681+ /* Bit 7.. 5: reserved (88E1040 only) */
9682+#define PHY_M_LEDC_LINK_MSK (3<<3) /* Bit 4.. 3: Link Control Mask */
9683+ /* (88E1040 only) */
9684+#define PHY_M_LEDC_DP_CTRL BIT_2S /* Duplex Control */
9685+#define PHY_M_LEDC_DP_C_MSB BIT_2S /* Duplex Control (MSB, 88E1111 only) */
9686+#define PHY_M_LEDC_RX_CTRL BIT_1S /* Rx Activity / Link */
9687+#define PHY_M_LEDC_TX_CTRL BIT_0S /* Tx Activity / Link */
9688+#define PHY_M_LEDC_TX_C_MSB BIT_0S /* Tx Control (MSB, 88E1111 only) */
9689
9690-#define PHY_M_LED_PULS_DUR(x) SHIFT12(x) /* Pulse Stretch Duration */
9691+#define PHY_M_LED_PULS_DUR(x) (SHIFT12(x) & PHY_M_LEDC_PULS_MSK)
9692
9693-#define PULS_NO_STR 0 /* no pulse stretching */
9694-#define PULS_21MS 1 /* 21 ms to 42 ms */
9695+#define PULS_NO_STR 0 /* no pulse stretching */
9696+#define PULS_21MS 1 /* 21 ms to 42 ms */
9697 #define PULS_42MS 2 /* 42 ms to 84 ms */
9698 #define PULS_84MS 3 /* 84 ms to 170 ms */
9699 #define PULS_170MS 4 /* 170 ms to 340 ms */
9700@@ -1217,7 +1301,7 @@
9701 #define PULS_670MS 6 /* 670 ms to 1.3 s */
9702 #define PULS_1300MS 7 /* 1.3 s to 2.7 s */
9703
9704-#define PHY_M_LED_BLINK_RT(x) SHIFT8(x) /* Blink Rate */
9705+#define PHY_M_LED_BLINK_RT(x) (SHIFT8(x) & PHY_M_LEDC_BL_R_MSK)
9706
9707 #define BLINK_42MS 0 /* 42 ms */
9708 #define BLINK_84MS 1 /* 84 ms */
9709@@ -1227,6 +1311,8 @@
9710 /* values 5 - 7: reserved */
9711
9712 /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
9713+#define PHY_M_LED_MO_SGMII(x) SHIFT14(x) /* Bit 15..14: SGMII AN Timer */
9714+ /* Bit 13..12: reserved */
9715 #define PHY_M_LED_MO_DUP(x) SHIFT10(x) /* Bit 11..10: Duplex */
9716 #define PHY_M_LED_MO_10(x) SHIFT8(x) /* Bit 9.. 8: Link 10 */
9717 #define PHY_M_LED_MO_100(x) SHIFT6(x) /* Bit 7.. 6: Link 100 */
9718@@ -1240,30 +1326,35 @@
9719 #define MO_LED_ON 3
9720
9721 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
9722- /* Bit 15.. 7: reserved */
9723-#define PHY_M_EC2_FI_IMPED (1<<6) /* Bit 6: Fiber Input Impedance */
9724-#define PHY_M_EC2_FO_IMPED (1<<5) /* Bit 5: Fiber Output Impedance */
9725-#define PHY_M_EC2_FO_M_CLK (1<<4) /* Bit 4: Fiber Mode Clock Enable */
9726-#define PHY_M_EC2_FO_BOOST (1<<3) /* Bit 3: Fiber Output Boost */
9727+ /* Bit 15.. 7: reserved */
9728+#define PHY_M_EC2_FI_IMPED BIT_6S /* Fiber Input Impedance */
9729+#define PHY_M_EC2_FO_IMPED BIT_5S /* Fiber Output Impedance */
9730+#define PHY_M_EC2_FO_M_CLK BIT_4S /* Fiber Mode Clock Enable */
9731+#define PHY_M_EC2_FO_BOOST BIT_3S /* Fiber Output Boost */
9732 #define PHY_M_EC2_FO_AM_MSK 7 /* Bit 2.. 0: Fiber Output Amplitude */
9733
9734-/***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
9735-#define PHY_M_FC_AUTO_SEL (1<<15) /* Bit 15: Fiber/Copper Auto Sel. dis. */
9736-#define PHY_M_FC_AN_REG_ACC (1<<14) /* Bit 14: Fiber/Copper Autoneg. reg acc */
9737-#define PHY_M_FC_RESULUTION (1<<13) /* Bit 13: Fiber/Copper Resulution */
9738-#define PHY_M_SER_IF_AN_BP (1<<12) /* Bit 12: Ser IF autoneg. bypass enable */
9739-#define PHY_M_SER_IF_BP_ST (1<<11) /* Bit 11: Ser IF autoneg. bypass status */
9740-#define PHY_M_IRQ_POLARITY (1<<10) /* Bit 10: IRQ polarity */
9741- /* Bit 9..4: reserved */
9742-#define PHY_M_UNDOC1 (1<< 7) /* undocumented bit !! */
9743-#define PHY_M_MODE_MASK (0xf<<0)/* Bit 3..0: copy of HWCFG MODE[3:0] */
9744-
9745+/***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
9746+#define PHY_M_FC_AUTO_SEL BIT_15S /* Fiber/Copper Auto Sel. Dis. */
9747+#define PHY_M_FC_AN_REG_ACC BIT_14S /* Fiber/Copper AN Reg. Access */
9748+#define PHY_M_FC_RESOLUTION BIT_13S /* Fiber/Copper Resolution */
9749+#define PHY_M_SER_IF_AN_BP BIT_12S /* Ser. IF AN Bypass Enable */
9750+#define PHY_M_SER_IF_BP_ST BIT_11S /* Ser. IF AN Bypass Status */
9751+#define PHY_M_IRQ_POLARITY BIT_10S /* IRQ polarity */
9752+#define PHY_M_DIS_AUT_MED BIT_9S /* Disable Aut. Medium Reg. Selection */
9753+ /* (88E1111 only) */
9754+ /* Bit 9.. 4: reserved (88E1040 only) */
9755+#define PHY_M_UNDOC1 BIT_7S /* undocumented bit !! */
9756+#define PHY_M_DTE_POW_STAT BIT_4S /* DTE Power Status (88E1111 only) */
9757+#define PHY_M_MODE_MASK 0xf /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
9758
9759 /***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/
9760-#define PHY_M_CABD_ENA_TEST (1<<15) /* Bit 15: Enable Test */
9761-#define PHY_M_CABD_STAT_MSK (3<<13) /* Bit 14..13: Status */
9762- /* Bit 12.. 8: reserved */
9763-#define PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance */
9764+#define PHY_M_CABD_ENA_TEST BIT_15S /* Enable Test (Page 0) */
9765+#define PHY_M_CABD_DIS_WAIT BIT_15S /* Disable Waiting Period (Page 1) */
9766+ /* (88E1111 only) */
9767+#define PHY_M_CABD_STAT_MSK (3<<13) /* Bit 14..13: Status Mask */
9768+#define PHY_M_CABD_AMPL_MSK (0x1f<<8) /* Bit 12.. 8: Amplitude Mask */
9769+ /* (88E1111 only) */
9770+#define PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance Mask */
9771
9772 /* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */
9773 #define CABD_STAT_NORMAL 0
9774@@ -1271,6 +1362,79 @@
9775 #define CABD_STAT_OPEN 2
9776 #define CABD_STAT_FAIL 3
9777
9778+/* for 10/100 Fast Ethernet PHY (88E3082 only) */
9779+/***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
9780+ /* Bit 15..12: reserved (used internally) */
9781+#define PHY_M_FELP_LED2_MSK (0xf<<8) /* Bit 11.. 8: LED2 Mask (LINK) */
9782+#define PHY_M_FELP_LED1_MSK (0xf<<4) /* Bit 7.. 4: LED1 Mask (ACT) */
9783+#define PHY_M_FELP_LED0_MSK 0xf /* Bit 3.. 0: LED0 Mask (SPEED) */
9784+
9785+#define PHY_M_FELP_LED2_CTRL(x) (SHIFT8(x) & PHY_M_FELP_LED2_MSK)
9786+#define PHY_M_FELP_LED1_CTRL(x) (SHIFT4(x) & PHY_M_FELP_LED1_MSK)
9787+#define PHY_M_FELP_LED0_CTRL(x) (SHIFT0(x) & PHY_M_FELP_LED0_MSK)
9788+
9789+#define LED_PAR_CTRL_COLX 0x00
9790+#define LED_PAR_CTRL_ERROR 0x01
9791+#define LED_PAR_CTRL_DUPLEX 0x02
9792+#define LED_PAR_CTRL_DP_COL 0x03
9793+#define LED_PAR_CTRL_SPEED 0x04
9794+#define LED_PAR_CTRL_LINK 0x05
9795+#define LED_PAR_CTRL_TX 0x06
9796+#define LED_PAR_CTRL_RX 0x07
9797+#define LED_PAR_CTRL_ACT 0x08
9798+#define LED_PAR_CTRL_LNK_RX 0x09
9799+#define LED_PAR_CTRL_LNK_AC 0x0a
9800+#define LED_PAR_CTRL_ACT_BL 0x0b
9801+#define LED_PAR_CTRL_TX_BL 0x0c
9802+#define LED_PAR_CTRL_RX_BL 0x0d
9803+#define LED_PAR_CTRL_COL_BL 0x0e
9804+#define LED_PAR_CTRL_INACT 0x0f
9805+
9806+/***** PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
9807+#define PHY_M_FESC_DIS_WAIT BIT_2S /* Disable TDR Waiting Period */
9808+#define PHY_M_FESC_ENA_MCLK BIT_1S /* Enable MAC Rx Clock in sleep mode */
9809+#define PHY_M_FESC_SEL_CL_A BIT_0S /* Select Class A driver (100B-TX) */
9810+
9811+/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
9812+/***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/
9813+#define PHY_M_FIB_FORCE_LNK BIT_10S /* Force Link Good */
9814+#define PHY_M_FIB_SIGD_POL BIT_9S /* SIGDET Polarity */
9815+#define PHY_M_FIB_TX_DIS BIT_3S /* Transmitter Disable */
9816+
9817+/***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
9818+#define PHY_M_MAC_MD_MSK (7<<7) /* Bit 9.. 7: Mode Select Mask */
9819+#define PHY_M_MAC_GMIF_PUP BIT_3S /* GMII Power Up (88E1149 only) */
9820+
9821+#define PHY_M_MAC_MD_AUTO 3 /* Auto Copper/1000Base-X */
9822+#define PHY_M_MAC_MD_COPPER 5 /* Copper only */
9823+#define PHY_M_MAC_MD_1000BX 7 /* 1000Base-X only */
9824+#define PHY_M_MAC_MODE_SEL(x) (SHIFT7(x) & PHY_M_MAC_MD_MSK)
9825+
9826+/***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
9827+#define PHY_M_LEDC_LOS_MSK (0xf<<12) /* Bit 15..12: LOS LED Ctrl. Mask */
9828+#define PHY_M_LEDC_INIT_MSK (0xf<<8) /* Bit 11.. 8: INIT LED Ctrl. Mask */
9829+#define PHY_M_LEDC_STA1_MSK (0xf<<4) /* Bit 7.. 4: STAT1 LED Ctrl. Mask */
9830+#define PHY_M_LEDC_STA0_MSK 0xf /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
9831+
9832+#define PHY_M_LEDC_LOS_CTRL(x) (SHIFT12(x) & PHY_M_LEDC_LOS_MSK)
9833+#define PHY_M_LEDC_INIT_CTRL(x) (SHIFT8(x) & PHY_M_LEDC_INIT_MSK)
9834+#define PHY_M_LEDC_STA1_CTRL(x) (SHIFT4(x) & PHY_M_LEDC_STA1_MSK)
9835+#define PHY_M_LEDC_STA0_CTRL(x) (SHIFT0(x) & PHY_M_LEDC_STA0_MSK)
9836+
9837+/***** PHY_MARV_PHY_STAT (page 3) 16 bit r/w Polarity Control Reg. *****/
9838+#define PHY_M_POLC_LS1M_MSK (0xf<<12) /* Bit 15..12: LOS,STAT1 Mix % Mask */
9839+#define PHY_M_POLC_IS0M_MSK (0xf<<8) /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
9840+#define PHY_M_POLC_LOS_MSK (0x3<<6) /* Bit 7.. 6: LOS Pol. Ctrl. Mask */
9841+#define PHY_M_POLC_INIT_MSK (0x3<<4) /* Bit 5.. 4: INIT Pol. Ctrl. Mask */
9842+#define PHY_M_POLC_STA1_MSK (0x3<<2) /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */
9843+#define PHY_M_POLC_STA0_MSK 0x3 /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */
9844+
9845+#define PHY_M_POLC_LS1_P_MIX(x) (SHIFT12(x) & PHY_M_POLC_LS1M_MSK)
9846+#define PHY_M_POLC_IS0_P_MIX(x) (SHIFT8(x) & PHY_M_POLC_IS0M_MSK)
9847+#define PHY_M_POLC_LOS_CTRL(x) (SHIFT6(x) & PHY_M_POLC_LOS_MSK)
9848+#define PHY_M_POLC_INIT_CTRL(x) (SHIFT4(x) & PHY_M_POLC_INIT_MSK)
9849+#define PHY_M_POLC_STA1_CTRL(x) (SHIFT2(x) & PHY_M_POLC_STA1_MSK)
9850+#define PHY_M_POLC_STA0_CTRL(x) (SHIFT0(x) & PHY_M_POLC_STA0_MSK)
9851
9852 /*
9853 * GMAC registers
9854@@ -1431,141 +1595,159 @@
9855 */
9856
9857 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
9858-#define GM_GPSR_SPEED (1<<15) /* Bit 15: Port Speed (1 = 100 Mbps) */
9859-#define GM_GPSR_DUPLEX (1<<14) /* Bit 14: Duplex Mode (1 = Full) */
9860-#define GM_GPSR_FC_TX_DIS (1<<13) /* Bit 13: Tx Flow-Control Mode Disabled */
9861-#define GM_GPSR_LINK_UP (1<<12) /* Bit 12: Link Up Status */
9862-#define GM_GPSR_PAUSE (1<<11) /* Bit 11: Pause State */
9863-#define GM_GPSR_TX_ACTIVE (1<<10) /* Bit 10: Tx in Progress */
9864-#define GM_GPSR_EXC_COL (1<<9) /* Bit 9: Excessive Collisions Occured */
9865-#define GM_GPSR_LAT_COL (1<<8) /* Bit 8: Late Collisions Occured */
9866- /* Bit 7..6: reserved */
9867-#define GM_GPSR_PHY_ST_CH (1<<5) /* Bit 5: PHY Status Change */
9868-#define GM_GPSR_GIG_SPEED (1<<4) /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
9869-#define GM_GPSR_PART_MODE (1<<3) /* Bit 3: Partition mode */
9870-#define GM_GPSR_FC_RX_DIS (1<<2) /* Bit 2: Rx Flow-Control Mode Disabled */
9871-#define GM_GPSR_PROM_EN (1<<1) /* Bit 1: Promiscuous Mode Enabled */
9872- /* Bit 0: reserved */
9873-
9874+#define GM_GPSR_SPEED BIT_15S /* Port Speed (1 = 100 Mbps) */
9875+#define GM_GPSR_DUPLEX BIT_14S /* Duplex Mode (1 = Full) */
9876+#define GM_GPSR_FC_TX_DIS BIT_13S /* Tx Flow-Control Mode Disabled */
9877+#define GM_GPSR_LINK_UP BIT_12S /* Link Up Status */
9878+#define GM_GPSR_PAUSE BIT_11S /* Pause State */
9879+#define GM_GPSR_TX_ACTIVE BIT_10S /* Tx in Progress */
9880+#define GM_GPSR_EXC_COL BIT_9S /* Excessive Collisions Occured */
9881+#define GM_GPSR_LAT_COL BIT_8S /* Late Collisions Occured */
9882+ /* Bit 7.. 6: reserved */
9883+#define GM_GPSR_PHY_ST_CH BIT_5S /* PHY Status Change */
9884+#define GM_GPSR_GIG_SPEED BIT_4S /* Gigabit Speed (1 = 1000 Mbps) */
9885+#define GM_GPSR_PART_MODE BIT_3S /* Partition mode */
9886+#define GM_GPSR_FC_RX_DIS BIT_2S /* Rx Flow-Control Mode Disabled */
9887+ /* Bit 2.. 0: reserved */
9888+
9889 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
9890- /* Bit 15: reserved */
9891-#define GM_GPCR_PROM_ENA (1<<14) /* Bit 14: Enable Promiscuous Mode */
9892-#define GM_GPCR_FC_TX_DIS (1<<13) /* Bit 13: Disable Tx Flow-Control Mode */
9893-#define GM_GPCR_TX_ENA (1<<12) /* Bit 12: Enable Transmit */
9894-#define GM_GPCR_RX_ENA (1<<11) /* Bit 11: Enable Receive */
9895-#define GM_GPCR_BURST_ENA (1<<10) /* Bit 10: Enable Burst Mode */
9896-#define GM_GPCR_LOOP_ENA (1<<9) /* Bit 9: Enable MAC Loopback Mode */
9897-#define GM_GPCR_PART_ENA (1<<8) /* Bit 8: Enable Partition Mode */
9898-#define GM_GPCR_GIGS_ENA (1<<7) /* Bit 7: Gigabit Speed (1000 Mbps) */
9899-#define GM_GPCR_FL_PASS (1<<6) /* Bit 6: Force Link Pass */
9900-#define GM_GPCR_DUP_FULL (1<<5) /* Bit 5: Full Duplex Mode */
9901-#define GM_GPCR_FC_RX_DIS (1<<4) /* Bit 4: Disable Rx Flow-Control Mode */
9902-#define GM_GPCR_SPEED_100 (1<<3) /* Bit 3: Port Speed 100 Mbps */
9903-#define GM_GPCR_AU_DUP_DIS (1<<2) /* Bit 2: Disable Auto-Update Duplex */
9904-#define GM_GPCR_AU_FCT_DIS (1<<1) /* Bit 1: Disable Auto-Update Flow-C. */
9905-#define GM_GPCR_AU_SPD_DIS (1<<0) /* Bit 0: Disable Auto-Update Speed */
9906+#define GM_GPCR_RMII_PH_ENA BIT_15S /* Enable RMII for PHY (Yukon-FE only) */
9907+#define GM_GPCR_RMII_LB_ENA BIT_14S /* Enable RMII Loopback (Yukon-FE only) */
9908+#define GM_GPCR_FC_TX_DIS BIT_13S /* Disable Tx Flow-Control Mode */
9909+#define GM_GPCR_TX_ENA BIT_12S /* Enable Transmit */
9910+#define GM_GPCR_RX_ENA BIT_11S /* Enable Receive */
9911+ /* Bit 10: reserved */
9912+#define GM_GPCR_LOOP_ENA BIT_9S /* Enable MAC Loopback Mode */
9913+#define GM_GPCR_PART_ENA BIT_8S /* Enable Partition Mode */
9914+#define GM_GPCR_GIGS_ENA BIT_7S /* Gigabit Speed (1000 Mbps) */
9915+#define GM_GPCR_FL_PASS BIT_6S /* Force Link Pass */
9916+#define GM_GPCR_DUP_FULL BIT_5S /* Full Duplex Mode */
9917+#define GM_GPCR_FC_RX_DIS BIT_4S /* Disable Rx Flow-Control Mode */
9918+#define GM_GPCR_SPEED_100 BIT_3S /* Port Speed 100 Mbps */
9919+#define GM_GPCR_AU_DUP_DIS BIT_2S /* Disable Auto-Update Duplex */
9920+#define GM_GPCR_AU_FCT_DIS BIT_1S /* Disable Auto-Update Flow-C. */
9921+#define GM_GPCR_AU_SPD_DIS BIT_0S /* Disable Auto-Update Speed */
9922
9923 #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
9924 #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |\
9925 GM_GPCR_AU_SPD_DIS)
9926-
9927+
9928 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
9929-#define GM_TXCR_FORCE_JAM (1<<15) /* Bit 15: Force Jam / Flow-Control */
9930-#define GM_TXCR_CRC_DIS (1<<14) /* Bit 14: Disable insertion of CRC */
9931-#define GM_TXCR_PAD_DIS (1<<13) /* Bit 13: Disable padding of packets */
9932-#define GM_TXCR_COL_THR_MSK (7<<10) /* Bit 12..10: Collision Threshold */
9933+#define GM_TXCR_FORCE_JAM BIT_15S /* Force Jam / Flow-Control */
9934+#define GM_TXCR_CRC_DIS BIT_14S /* Disable insertion of CRC */
9935+#define GM_TXCR_PAD_DIS BIT_13S /* Disable padding of packets */
9936+#define GM_TXCR_COL_THR_MSK (7<<10) /* Bit 12..10: Collision Threshold Mask */
9937+ /* Bit 9.. 8: reserved */
9938+#define GM_TXCR_PAD_PAT_MSK 0xff /* Bit 7.. 0: Padding Pattern Mask */
9939+ /* (Yukon-2 only) */
9940
9941 #define TX_COL_THR(x) (SHIFT10(x) & GM_TXCR_COL_THR_MSK)
9942
9943 #define TX_COL_DEF 0x04
9944-
9945+
9946 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
9947-#define GM_RXCR_UCF_ENA (1<<15) /* Bit 15: Enable Unicast filtering */
9948-#define GM_RXCR_MCF_ENA (1<<14) /* Bit 14: Enable Multicast filtering */
9949-#define GM_RXCR_CRC_DIS (1<<13) /* Bit 13: Remove 4-byte CRC */
9950-#define GM_RXCR_PASS_FC (1<<12) /* Bit 12: Pass FC packets to FIFO */
9951-
9952+#define GM_RXCR_UCF_ENA BIT_15S /* Enable Unicast filtering */
9953+#define GM_RXCR_MCF_ENA BIT_14S /* Enable Multicast filtering */
9954+#define GM_RXCR_CRC_DIS BIT_13S /* Remove 4-byte CRC */
9955+#define GM_RXCR_PASS_FC BIT_12S /* Pass FC packets to FIFO (Yukon-1 only) */
9956+ /* Bit 11.. 0: reserved */
9957+
9958 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
9959-#define GM_TXPA_JAMLEN_MSK (0x03<<14) /* Bit 15..14: Jam Length */
9960-#define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13..9: Jam IPG */
9961-#define GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8..4: IPG Jam to Data */
9962- /* Bit 3..0: reserved */
9963+#define GM_TXPA_JAMLEN_MSK (3<<14) /* Bit 15..14: Jam Length Mask */
9964+#define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13.. 9: Jam IPG Mask */
9965+#define GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8.. 4: IPG Jam to Data Mask */
9966+#define GM_TXPA_BO_LIM_MSK 0x0f /* Bit 3.. 0: Backoff Limit Mask */
9967+ /* (Yukon-2 only) */
9968
9969 #define TX_JAM_LEN_VAL(x) (SHIFT14(x) & GM_TXPA_JAMLEN_MSK)
9970 #define TX_JAM_IPG_VAL(x) (SHIFT9(x) & GM_TXPA_JAMIPG_MSK)
9971 #define TX_IPG_JAM_DATA(x) (SHIFT4(x) & GM_TXPA_JAMDAT_MSK)
9972+#define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK)
9973
9974 #define TX_JAM_LEN_DEF 0x03
9975 #define TX_JAM_IPG_DEF 0x0b
9976 #define TX_IPG_JAM_DEF 0x1c
9977+#define TX_BOF_LIM_DEF 0x04
9978
9979 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
9980-#define GM_SMOD_DATABL_MSK (0x1f<<11) /* Bit 15..11: Data Blinder (r/o) */
9981-#define GM_SMOD_LIMIT_4 (1<<10) /* Bit 10: 4 consecutive Tx trials */
9982-#define GM_SMOD_VLAN_ENA (1<<9) /* Bit 9: Enable VLAN (Max. Frame Len) */
9983-#define GM_SMOD_JUMBO_ENA (1<<8) /* Bit 8: Enable Jumbo (Max. Frame Len) */
9984- /* Bit 7..5: reserved */
9985-#define GM_SMOD_IPG_MSK 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
9986-
9987+#define GM_SMOD_DATABL_MSK (0x1f<<11) /* Bit 15..11: Data Blinder */
9988+ /* r/o on Yukon, r/w on Yukon-EC */
9989+#define GM_SMOD_LIMIT_4 BIT_10S /* 4 consecutive Tx trials */
9990+#define GM_SMOD_VLAN_ENA BIT_9S /* Enable VLAN (Max. Frame Len) */
9991+#define GM_SMOD_JUMBO_ENA BIT_8S /* Enable Jumbo (Max. Frame Len) */
9992+ /* Bit 7.. 5: reserved */
9993+#define GM_SMOD_IPG_MSK 0x1f /* Bit 4.. 0: Inter-Packet Gap (IPG) */
9994+
9995 #define DATA_BLIND_VAL(x) (SHIFT11(x) & GM_SMOD_DATABL_MSK)
9996-#define DATA_BLIND_DEF 0x04
9997+#define IPG_DATA_VAL(x) ((x) & GM_SMOD_IPG_MSK)
9998
9999-#define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
10000+#define DATA_BLIND_DEF 0x04
10001 #define IPG_DATA_DEF 0x1e
10002
10003 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
10004 #define GM_SMI_CT_PHY_A_MSK (0x1f<<11) /* Bit 15..11: PHY Device Address */
10005 #define GM_SMI_CT_REG_A_MSK (0x1f<<6) /* Bit 10.. 6: PHY Register Address */
10006-#define GM_SMI_CT_OP_RD (1<<5) /* Bit 5: OpCode Read (0=Write)*/
10007-#define GM_SMI_CT_RD_VAL (1<<4) /* Bit 4: Read Valid (Read completed) */
10008-#define GM_SMI_CT_BUSY (1<<3) /* Bit 3: Busy (Operation in progress) */
10009- /* Bit 2..0: reserved */
10010-
10011+#define GM_SMI_CT_OP_RD BIT_5S /* OpCode Read (0=Write)*/
10012+#define GM_SMI_CT_RD_VAL BIT_4S /* Read Valid (Read completed) */
10013+#define GM_SMI_CT_BUSY BIT_3S /* Busy (Operation in progress) */
10014+ /* Bit 2.. 0: reserved */
10015+
10016 #define GM_SMI_CT_PHY_AD(x) (SHIFT11(x) & GM_SMI_CT_PHY_A_MSK)
10017 #define GM_SMI_CT_REG_AD(x) (SHIFT6(x) & GM_SMI_CT_REG_A_MSK)
10018
10019- /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
10020- /* Bit 15..6: reserved */
10021-#define GM_PAR_MIB_CLR (1<<5) /* Bit 5: Set MIB Clear Counter Mode */
10022-#define GM_PAR_MIB_TST (1<<4) /* Bit 4: MIB Load Counter (Test Mode) */
10023- /* Bit 3..0: reserved */
10024-
10025+/* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
10026+ /* Bit 15.. 6: reserved */
10027+#define GM_PAR_MIB_CLR BIT_5S /* Set MIB Clear Counter Mode */
10028+#define GM_PAR_MIB_TST BIT_4S /* MIB Load Counter (Test Mode) */
10029+ /* Bit 3.. 0: reserved */
10030+
10031 /* Receive Frame Status Encoding */
10032-#define GMR_FS_LEN (0xffffUL<<16) /* Bit 31..16: Rx Frame Length */
10033+#define GMR_FS_LEN_MSK (0xffffUL<<16) /* Bit 31..16: Rx Frame Length */
10034 /* Bit 15..14: reserved */
10035-#define GMR_FS_VLAN (1L<<13) /* Bit 13: VLAN Packet */
10036-#define GMR_FS_JABBER (1L<<12) /* Bit 12: Jabber Packet */
10037-#define GMR_FS_UN_SIZE (1L<<11) /* Bit 11: Undersize Packet */
10038-#define GMR_FS_MC (1L<<10) /* Bit 10: Multicast Packet */
10039-#define GMR_FS_BC (1L<<9) /* Bit 9: Broadcast Packet */
10040-#define GMR_FS_RX_OK (1L<<8) /* Bit 8: Receive OK (Good Packet) */
10041-#define GMR_FS_GOOD_FC (1L<<7) /* Bit 7: Good Flow-Control Packet */
10042-#define GMR_FS_BAD_FC (1L<<6) /* Bit 6: Bad Flow-Control Packet */
10043-#define GMR_FS_MII_ERR (1L<<5) /* Bit 5: MII Error */
10044-#define GMR_FS_LONG_ERR (1L<<4) /* Bit 4: Too Long Packet */
10045-#define GMR_FS_FRAGMENT (1L<<3) /* Bit 3: Fragment */
10046+#define GMR_FS_VLAN BIT_13 /* VLAN Packet */
10047+#define GMR_FS_JABBER BIT_12 /* Jabber Packet */
10048+#define GMR_FS_UN_SIZE BIT_11 /* Undersize Packet */
10049+#define GMR_FS_MC BIT_10 /* Multicast Packet */
10050+#define GMR_FS_BC BIT_9 /* Broadcast Packet */
10051+#define GMR_FS_RX_OK BIT_8 /* Receive OK (Good Packet) */
10052+#define GMR_FS_GOOD_FC BIT_7 /* Good Flow-Control Packet */
10053+#define GMR_FS_BAD_FC BIT_6 /* Bad Flow-Control Packet */
10054+#define GMR_FS_MII_ERR BIT_5 /* MII Error */
10055+#define GMR_FS_LONG_ERR BIT_4 /* Too Long Packet */
10056+#define GMR_FS_FRAGMENT BIT_3 /* Fragment */
10057 /* Bit 2: reserved */
10058-#define GMR_FS_CRC_ERR (1L<<1) /* Bit 1: CRC Error */
10059-#define GMR_FS_RX_FF_OV (1L<<0) /* Bit 0: Rx FIFO Overflow */
10060+#define GMR_FS_CRC_ERR BIT_1 /* CRC Error */
10061+#define GMR_FS_RX_FF_OV BIT_0 /* Rx FIFO Overflow */
10062+
10063+#define GMR_FS_LEN_SHIFT 16
10064
10065 /*
10066 * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR)
10067 */
10068-#define GMR_FS_ANY_ERR (GMR_FS_CRC_ERR | \
10069- GMR_FS_LONG_ERR | \
10070+#ifdef SK_DIAG
10071+#define GMR_FS_ANY_ERR ( \
10072+ GMR_FS_RX_FF_OV | \
10073+ GMR_FS_CRC_ERR | \
10074+ GMR_FS_FRAGMENT | \
10075 GMR_FS_MII_ERR | \
10076 GMR_FS_BAD_FC | \
10077 GMR_FS_GOOD_FC | \
10078 GMR_FS_JABBER)
10079-
10080-/* Rx GMAC FIFO Flush Mask (default) */
10081-#define RX_FF_FL_DEF_MSK (GMR_FS_CRC_ERR | \
10082+#else
10083+#define GMR_FS_ANY_ERR ( \
10084 GMR_FS_RX_FF_OV | \
10085+ GMR_FS_CRC_ERR | \
10086+ GMR_FS_FRAGMENT | \
10087+ GMR_FS_LONG_ERR | \
10088 GMR_FS_MII_ERR | \
10089 GMR_FS_BAD_FC | \
10090 GMR_FS_GOOD_FC | \
10091 GMR_FS_UN_SIZE | \
10092 GMR_FS_JABBER)
10093+#endif
10094+
10095+/* Rx GMAC FIFO Flush Mask (default) */
10096+#define RX_FF_FL_DEF_MSK GMR_FS_ANY_ERR
10097
10098 /* typedefs *******************************************************************/
10099
10100@@ -1577,3 +1759,4 @@
10101 #endif /* __cplusplus */
10102
10103 #endif /* __INC_XMAC_H */
10104+
10105diff -ruN linux/drivers/net/sk98lin/skaddr.c linux-new/drivers/net/sk98lin/skaddr.c
10106--- linux/drivers/net/sk98lin/skaddr.c 2007-01-02 23:21:17.000000000 +0100
10107+++ linux-new/drivers/net/sk98lin/skaddr.c 2006-10-13 10:18:34.000000000 +0200
10108@@ -2,16 +2,17 @@
10109 *
10110 * Name: skaddr.c
10111 * Project: Gigabit Ethernet Adapters, ADDR-Module
10112- * Version: $Revision$
10113- * Date: $Date$
10114+ * Version: $Revision$
10115+ * Date: $Date$
10116 * Purpose: Manage Addresses (Multicast and Unicast) and Promiscuous Mode.
10117 *
10118 ******************************************************************************/
10119
10120 /******************************************************************************
10121 *
10122+ * LICENSE:
10123 * (C)Copyright 1998-2002 SysKonnect GmbH.
10124- * (C)Copyright 2002-2003 Marvell.
10125+ * (C)Copyright 2002-2005 Marvell.
10126 *
10127 * This program is free software; you can redistribute it and/or modify
10128 * it under the terms of the GNU General Public License as published by
10129@@ -19,6 +20,7 @@
10130 * (at your option) any later version.
10131 *
10132 * The information in this file is provided "AS IS" without warranty.
10133+ * /LICENSE
10134 *
10135 ******************************************************************************/
10136
10137@@ -44,7 +46,7 @@
10138
10139 #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
10140 static const char SysKonnectFileId[] =
10141- "@(#) $Id$ (C) Marvell.";
10142+ "@(#) $Id$ (C) Marvell.";
10143 #endif /* DEBUG ||!LINT || !SK_SLIM */
10144
10145 #define __SKADDR_C
10146@@ -58,11 +60,10 @@
10147
10148 /* defines ********************************************************************/
10149
10150-
10151 #define XMAC_POLY 0xEDB88320UL /* CRC32-Poly - XMAC: Little Endian */
10152 #define GMAC_POLY 0x04C11DB7L /* CRC16-Poly - GMAC: Little Endian */
10153 #define HASH_BITS 6 /* #bits in hash */
10154-#define SK_MC_BIT 0x01
10155+#define SK_MC_BIT 0x01
10156
10157 /* Error numbers and messages. */
10158
10159@@ -79,7 +80,7 @@
10160
10161 /* 64-bit hash values with all bits set. */
10162
10163-static const SK_U16 OnesHash[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
10164+SK_U16 OnesHash[4] = {0xffff, 0xffff, 0xffff, 0xffff};
10165
10166 /* local variables ************************************************************/
10167
10168@@ -87,21 +88,6 @@
10169 static int Next0[SK_MAX_MACS] = {0};
10170 #endif /* DEBUG */
10171
10172-static int SkAddrGmacMcAdd(SK_AC *pAC, SK_IOC IoC, SK_U32 PortNumber,
10173- SK_MAC_ADDR *pMc, int Flags);
10174-static int SkAddrGmacMcClear(SK_AC *pAC, SK_IOC IoC, SK_U32 PortNumber,
10175- int Flags);
10176-static int SkAddrGmacMcUpdate(SK_AC *pAC, SK_IOC IoC, SK_U32 PortNumber);
10177-static int SkAddrGmacPromiscuousChange(SK_AC *pAC, SK_IOC IoC,
10178- SK_U32 PortNumber, int NewPromMode);
10179-static int SkAddrXmacMcAdd(SK_AC *pAC, SK_IOC IoC, SK_U32 PortNumber,
10180- SK_MAC_ADDR *pMc, int Flags);
10181-static int SkAddrXmacMcClear(SK_AC *pAC, SK_IOC IoC, SK_U32 PortNumber,
10182- int Flags);
10183-static int SkAddrXmacMcUpdate(SK_AC *pAC, SK_IOC IoC, SK_U32 PortNumber);
10184-static int SkAddrXmacPromiscuousChange(SK_AC *pAC, SK_IOC IoC,
10185- SK_U32 PortNumber, int NewPromMode);
10186-
10187 /* functions ******************************************************************/
10188
10189 /******************************************************************************
10190@@ -151,13 +137,12 @@
10191
10192 switch (Level) {
10193 case SK_INIT_DATA:
10194- SK_MEMSET((char *) &pAC->Addr, (SK_U8) 0,
10195- (SK_U16) sizeof(SK_ADDR));
10196+ SK_MEMSET((char *)&pAC->Addr, (SK_U8)0, (SK_U16)sizeof(SK_ADDR));
10197
10198 for (i = 0; i < SK_MAX_MACS; i++) {
10199 pAPort = &pAC->Addr.Port[i];
10200 pAPort->PromMode = SK_PROM_MODE_NONE;
10201-
10202+
10203 pAPort->FirstExactMatchRlmt = SK_ADDR_FIRST_MATCH_RLMT;
10204 pAPort->FirstExactMatchDrv = SK_ADDR_FIRST_MATCH_DRV;
10205 pAPort->NextExactMatchRlmt = SK_ADDR_FIRST_MATCH_RLMT;
10206@@ -174,7 +159,7 @@
10207 /* pAC->Addr.InitDone = SK_INIT_DATA; */
10208 break;
10209
10210- case SK_INIT_IO:
10211+ case SK_INIT_IO:
10212 #ifndef SK_NO_RLMT
10213 for (i = 0; i < SK_MAX_NETS; i++) {
10214 pAC->Addr.Net[i].ActivePort = pAC->Rlmt.Net[i].ActivePort;
10215@@ -188,7 +173,7 @@
10216 }
10217 }
10218 #endif /* DEBUG */
10219-
10220+
10221 /* Read permanent logical MAC address from Control Register File. */
10222 for (j = 0; j < SK_MAC_ADDR_LEN; j++) {
10223 InAddr = (SK_U8 *) &pAC->Addr.Net[0].PermanentMacAddress.a[j];
10224@@ -206,11 +191,11 @@
10225 pAC->Addr.Port[pAC->Addr.Net[0].ActivePort].Exact[0] =
10226 pAC->Addr.Net[0].CurrentMacAddress;
10227 #if SK_MAX_NETS > 1
10228- /* Set logical MAC address for net 2 to (log | 3). */
10229+ /* Set logical MAC address for net 2 to. */
10230 if (!pAC->Addr.Net[1].CurrentMacAddressSet) {
10231 pAC->Addr.Net[1].PermanentMacAddress =
10232 pAC->Addr.Net[0].PermanentMacAddress;
10233- pAC->Addr.Net[1].PermanentMacAddress.a[5] |= 3;
10234+ pAC->Addr.Net[1].PermanentMacAddress.a[5] += 1;
10235 /* Set the current logical MAC address to the permanent one. */
10236 pAC->Addr.Net[1].CurrentMacAddress =
10237 pAC->Addr.Net[1].PermanentMacAddress;
10238@@ -228,8 +213,8 @@
10239 pAC->Addr.Net[i].PermanentMacAddress.a[2],
10240 pAC->Addr.Net[i].PermanentMacAddress.a[3],
10241 pAC->Addr.Net[i].PermanentMacAddress.a[4],
10242- pAC->Addr.Net[i].PermanentMacAddress.a[5]))
10243-
10244+ pAC->Addr.Net[i].PermanentMacAddress.a[5]));
10245+
10246 SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_INIT,
10247 ("Logical MAC Address (Net%d): %02X %02X %02X %02X %02X %02X\n",
10248 i,
10249@@ -238,7 +223,7 @@
10250 pAC->Addr.Net[i].CurrentMacAddress.a[2],
10251 pAC->Addr.Net[i].CurrentMacAddress.a[3],
10252 pAC->Addr.Net[i].CurrentMacAddress.a[4],
10253- pAC->Addr.Net[i].CurrentMacAddress.a[5]))
10254+ pAC->Addr.Net[i].CurrentMacAddress.a[5]));
10255 }
10256 #endif /* DEBUG */
10257
10258@@ -281,8 +266,8 @@
10259 pAPort->PermanentMacAddress.a[2],
10260 pAPort->PermanentMacAddress.a[3],
10261 pAPort->PermanentMacAddress.a[4],
10262- pAPort->PermanentMacAddress.a[5]))
10263-
10264+ pAPort->PermanentMacAddress.a[5]));
10265+
10266 SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_INIT,
10267 ("SkAddrInit: Physical MAC Address: %02X %02X %02X %02X %02X %02X\n",
10268 pAPort->CurrentMacAddress.a[0],
10269@@ -290,7 +275,7 @@
10270 pAPort->CurrentMacAddress.a[2],
10271 pAPort->CurrentMacAddress.a[3],
10272 pAPort->CurrentMacAddress.a[4],
10273- pAPort->CurrentMacAddress.a[5]))
10274+ pAPort->CurrentMacAddress.a[5]));
10275 #endif /* DEBUG */
10276 }
10277 /* pAC->Addr.InitDone = SK_INIT_IO; */
10278@@ -314,7 +299,7 @@
10279 }
10280
10281 return (SK_ADDR_SUCCESS);
10282-
10283+
10284 } /* SkAddrInit */
10285
10286 #ifndef SK_SLIM
10287@@ -348,16 +333,20 @@
10288 int Flags) /* permanent/non-perm, sw-only */
10289 {
10290 int ReturnCode;
10291-
10292+
10293 if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
10294 return (SK_ADDR_ILLEGAL_PORT);
10295 }
10296-
10297+
10298 if (pAC->GIni.GIGenesis) {
10299+#ifdef GENESIS
10300 ReturnCode = SkAddrXmacMcClear(pAC, IoC, PortNumber, Flags);
10301+#endif
10302 }
10303 else {
10304+#ifdef YUKON
10305 ReturnCode = SkAddrGmacMcClear(pAC, IoC, PortNumber, Flags);
10306+#endif
10307 }
10308
10309 return (ReturnCode);
10310@@ -367,7 +356,7 @@
10311 #endif /* !SK_SLIM */
10312
10313 #ifndef SK_SLIM
10314-
10315+#ifdef GENESIS
10316 /******************************************************************************
10317 *
10318 * SkAddrXmacMcClear - clear the multicast table
10319@@ -387,7 +376,7 @@
10320 * SK_ADDR_SUCCESS
10321 * SK_ADDR_ILLEGAL_PORT
10322 */
10323-static int SkAddrXmacMcClear(
10324+int SkAddrXmacMcClear(
10325 SK_AC *pAC, /* adapter context */
10326 SK_IOC IoC, /* I/O context */
10327 SK_U32 PortNumber, /* Index of affected port */
10328@@ -417,13 +406,13 @@
10329 }
10330
10331 return (SK_ADDR_SUCCESS);
10332-
10333-} /* SkAddrXmacMcClear */
10334
10335+} /* SkAddrXmacMcClear */
10336+#endif /* GENESIS */
10337 #endif /* !SK_SLIM */
10338
10339 #ifndef SK_SLIM
10340-
10341+#ifdef YUKON
10342 /******************************************************************************
10343 *
10344 * SkAddrGmacMcClear - clear the multicast table
10345@@ -444,7 +433,7 @@
10346 * SK_ADDR_SUCCESS
10347 * SK_ADDR_ILLEGAL_PORT
10348 */
10349-static int SkAddrGmacMcClear(
10350+int SkAddrGmacMcClear(
10351 SK_AC *pAC, /* adapter context */
10352 SK_IOC IoC, /* I/O context */
10353 SK_U32 PortNumber, /* Index of affected port */
10354@@ -462,38 +451,37 @@
10355 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[4],
10356 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[5],
10357 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[6],
10358- pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7]))
10359+ pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7]));
10360 #endif /* DEBUG */
10361
10362 /* Clear InexactFilter */
10363 for (i = 0; i < 8; i++) {
10364 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] = 0;
10365 }
10366-
10367+
10368 if (Flags & SK_ADDR_PERMANENT) { /* permanent => RLMT */
10369-
10370+
10371 /* Copy DRV bits to InexactFilter. */
10372 for (i = 0; i < 8; i++) {
10373 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |=
10374 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[i];
10375-
10376+
10377 /* Clear InexactRlmtFilter. */
10378 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[i] = 0;
10379-
10380- }
10381+ }
10382 }
10383 else { /* not permanent => DRV */
10384-
10385+
10386 /* Copy RLMT bits to InexactFilter. */
10387 for (i = 0; i < 8; i++) {
10388 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |=
10389 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[i];
10390-
10391+
10392 /* Clear InexactDrvFilter. */
10393 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[i] = 0;
10394 }
10395 }
10396-
10397+
10398 #ifdef DEBUG
10399 SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
10400 ("GMAC InexactFilter (cleared): %02X %02X %02X %02X %02X %02X %02X %02X\n",
10401@@ -504,19 +492,20 @@
10402 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[4],
10403 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[5],
10404 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[6],
10405- pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7]))
10406+ pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7]));
10407 #endif /* DEBUG */
10408-
10409+
10410 if (!(Flags & SK_MC_SW_ONLY)) {
10411 (void) SkAddrGmacMcUpdate(pAC, IoC, PortNumber);
10412 }
10413-
10414+
10415 return (SK_ADDR_SUCCESS);
10416
10417 } /* SkAddrGmacMcClear */
10418+#endif /* YUKON */
10419
10420 #ifndef SK_ADDR_CHEAT
10421-
10422+#ifdef GENESIS
10423 /******************************************************************************
10424 *
10425 * SkXmacMcHash - hash multicast address
10426@@ -534,7 +523,7 @@
10427 * Returns:
10428 * Hash value of multicast address.
10429 */
10430-static SK_U32 SkXmacMcHash(
10431+SK_U32 SkXmacMcHash(
10432 unsigned char *pMc) /* Multicast address */
10433 {
10434 SK_U32 Idx;
10435@@ -553,8 +542,9 @@
10436 return (Crc & ((1 << HASH_BITS) - 1));
10437
10438 } /* SkXmacMcHash */
10439+#endif /* GENESIS */
10440
10441-
10442+#ifdef YUKON
10443 /******************************************************************************
10444 *
10445 * SkGmacMcHash - hash multicast address
10446@@ -572,7 +562,7 @@
10447 * Returns:
10448 * Hash value of multicast address.
10449 */
10450-static SK_U32 SkGmacMcHash(
10451+SK_U32 SkGmacMcHash(
10452 unsigned char *pMc) /* Multicast address */
10453 {
10454 SK_U32 Data;
10455@@ -585,7 +575,7 @@
10456 for (Byte = 0; Byte < 6; Byte++) {
10457 /* Get next byte. */
10458 Data = (SK_U32) pMc[Byte];
10459-
10460+
10461 /* Change bit order in byte. */
10462 TmpData = Data;
10463 for (Bit = 0; Bit < 8; Bit++) {
10464@@ -597,7 +587,7 @@
10465 }
10466 TmpData >>= 1;
10467 }
10468-
10469+
10470 Crc ^= (Data << 24);
10471 for (Bit = 0; Bit < 8; Bit++) {
10472 if (Crc & 0x80000000) {
10473@@ -608,11 +598,11 @@
10474 }
10475 }
10476 }
10477-
10478+
10479 return (Crc & ((1 << HASH_BITS) - 1));
10480
10481 } /* SkGmacMcHash */
10482-
10483+#endif /* YUKON */
10484 #endif /* !SK_ADDR_CHEAT */
10485
10486 /******************************************************************************
10487@@ -647,23 +637,27 @@
10488 int Flags) /* permanent/non-permanent */
10489 {
10490 int ReturnCode;
10491-
10492+
10493 if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
10494 return (SK_ADDR_ILLEGAL_PORT);
10495 }
10496-
10497+
10498 if (pAC->GIni.GIGenesis) {
10499+#ifdef GENESIS
10500 ReturnCode = SkAddrXmacMcAdd(pAC, IoC, PortNumber, pMc, Flags);
10501+#endif
10502 }
10503 else {
10504+#ifdef YUKON
10505 ReturnCode = SkAddrGmacMcAdd(pAC, IoC, PortNumber, pMc, Flags);
10506+#endif
10507 }
10508
10509 return (ReturnCode);
10510
10511 } /* SkAddrMcAdd */
10512
10513-
10514+#ifdef GENESIS
10515 /******************************************************************************
10516 *
10517 * SkAddrXmacMcAdd - add a multicast address to a port
10518@@ -687,7 +681,7 @@
10519 * SK_MC_ILLEGAL_ADDRESS
10520 * SK_MC_RLMT_OVERFLOW
10521 */
10522-static int SkAddrXmacMcAdd(
10523+int SkAddrXmacMcAdd(
10524 SK_AC *pAC, /* adapter context */
10525 SK_IOC IoC, /* I/O context */
10526 SK_U32 PortNumber, /* Port Number */
10527@@ -708,7 +702,7 @@
10528 return (SK_MC_RLMT_OVERFLOW);
10529 }
10530 #endif /* DEBUG */
10531-
10532+
10533 if (pAC->Addr.Port[PortNumber].NextExactMatchRlmt >
10534 SK_ADDR_LAST_MATCH_RLMT) {
10535 return (SK_MC_RLMT_OVERFLOW);
10536@@ -729,7 +723,7 @@
10537 return (SK_MC_RLMT_OVERFLOW);
10538 }
10539 #endif /* DEBUG */
10540-
10541+
10542 if (pAC->Addr.Port[PortNumber].NextExactMatchDrv <= SK_ADDR_LAST_MATCH_DRV) {
10543
10544 /* Set exact match entry. */
10545@@ -773,8 +767,9 @@
10546 }
10547
10548 } /* SkAddrXmacMcAdd */
10549+#endif /* GENESIS */
10550
10551-
10552+#ifdef YUKON
10553 /******************************************************************************
10554 *
10555 * SkAddrGmacMcAdd - add a multicast address to a port
10556@@ -793,7 +788,7 @@
10557 * SK_MC_FILTERING_INEXACT
10558 * SK_MC_ILLEGAL_ADDRESS
10559 */
10560-static int SkAddrGmacMcAdd(
10561+int SkAddrGmacMcAdd(
10562 SK_AC *pAC, /* adapter context */
10563 SK_IOC IoC, /* I/O context */
10564 SK_U32 PortNumber, /* Port Number */
10565@@ -804,28 +799,29 @@
10566 #ifndef SK_ADDR_CHEAT
10567 SK_U32 HashBit;
10568 #endif /* !defined(SK_ADDR_CHEAT) */
10569-
10570+
10571 if (!(pMc->a[0] & SK_MC_BIT)) {
10572 /* Hashing only possible with multicast addresses */
10573 return (SK_MC_ILLEGAL_ADDRESS);
10574 }
10575-
10576+
10577 #ifndef SK_ADDR_CHEAT
10578-
10579+
10580 /* Compute hash value of address. */
10581 HashBit = SkGmacMcHash(&pMc->a[0]);
10582-
10583+
10584 if (Flags & SK_ADDR_PERMANENT) { /* permanent => RLMT */
10585-
10586+
10587 /* Add bit to InexactRlmtFilter. */
10588 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[HashBit / 8] |=
10589 1 << (HashBit % 8);
10590-
10591+
10592 /* Copy bit to InexactFilter. */
10593 for (i = 0; i < 8; i++) {
10594 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |=
10595 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[i];
10596 }
10597+
10598 #ifdef DEBUG
10599 SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
10600 ("GMAC InexactRlmtFilter: %02X %02X %02X %02X %02X %02X %02X %02X\n",
10601@@ -836,20 +832,21 @@
10602 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[4],
10603 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[5],
10604 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[6],
10605- pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[7]))
10606+ pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[7]));
10607 #endif /* DEBUG */
10608 }
10609 else { /* not permanent => DRV */
10610-
10611+
10612 /* Add bit to InexactDrvFilter. */
10613 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[HashBit / 8] |=
10614 1 << (HashBit % 8);
10615-
10616+
10617 /* Copy bit to InexactFilter. */
10618 for (i = 0; i < 8; i++) {
10619 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |=
10620 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[i];
10621 }
10622+
10623 #ifdef DEBUG
10624 SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
10625 ("GMAC InexactDrvFilter: %02X %02X %02X %02X %02X %02X %02X %02X\n",
10626@@ -860,22 +857,22 @@
10627 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[4],
10628 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[5],
10629 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[6],
10630- pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[7]))
10631+ pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[7]));
10632 #endif /* DEBUG */
10633 }
10634-
10635+
10636 #else /* SK_ADDR_CHEAT */
10637-
10638+
10639 /* Set all bits in InexactFilter. */
10640 for (i = 0; i < 8; i++) {
10641 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] = 0xFF;
10642 }
10643 #endif /* SK_ADDR_CHEAT */
10644-
10645+
10646 return (SK_MC_FILTERING_INEXACT);
10647-
10648-} /* SkAddrGmacMcAdd */
10649
10650+} /* SkAddrGmacMcAdd */
10651+#endif /* YUKON */
10652 #endif /* !SK_SLIM */
10653
10654 /******************************************************************************
10655@@ -907,7 +904,8 @@
10656 SK_IOC IoC, /* I/O context */
10657 SK_U32 PortNumber) /* Port Number */
10658 {
10659- int ReturnCode = 0;
10660+ int ReturnCode = SK_ADDR_ILLEGAL_PORT;
10661+
10662 #if (!defined(SK_SLIM) || defined(DEBUG))
10663 if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
10664 return (SK_ADDR_ILLEGAL_PORT);
10665@@ -952,7 +950,7 @@
10666 * SK_MC_FILTERING_INEXACT
10667 * SK_ADDR_ILLEGAL_PORT
10668 */
10669-static int SkAddrXmacMcUpdate(
10670+int SkAddrXmacMcUpdate(
10671 SK_AC *pAC, /* adapter context */
10672 SK_IOC IoC, /* I/O context */
10673 SK_U32 PortNumber) /* Port Number */
10674@@ -963,13 +961,13 @@
10675 SK_ADDR_PORT *pAPort;
10676
10677 SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
10678- ("SkAddrXmacMcUpdate on Port %u.\n", PortNumber))
10679-
10680+ ("SkAddrXmacMcUpdate on Port %u.\n", PortNumber));
10681+
10682 pAPort = &pAC->Addr.Port[PortNumber];
10683
10684 #ifdef DEBUG
10685 SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
10686- ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber]))
10687+ ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber]));
10688 #endif /* DEBUG */
10689
10690 /* Start with 0 to also program the logical MAC address. */
10691@@ -981,7 +979,7 @@
10692
10693 /* Clear other permanent exact match addresses on XMAC */
10694 if (pAPort->NextExactMatchRlmt <= SK_ADDR_LAST_MATCH_RLMT) {
10695-
10696+
10697 SkXmClrExactAddr(pAC, IoC, PortNumber, pAPort->NextExactMatchRlmt,
10698 SK_ADDR_LAST_MATCH_RLMT);
10699 }
10700@@ -993,7 +991,7 @@
10701
10702 /* Clear other non-permanent exact match addresses on XMAC */
10703 if (pAPort->NextExactMatchDrv <= SK_ADDR_LAST_MATCH_DRV) {
10704-
10705+
10706 SkXmClrExactAddr(pAC, IoC, PortNumber, pAPort->NextExactMatchDrv,
10707 SK_ADDR_LAST_MATCH_DRV);
10708 }
10709@@ -1003,18 +1001,18 @@
10710 }
10711
10712 if (pAPort->PromMode & SK_PROM_MODE_ALL_MC) {
10713-
10714+
10715 /* Set all bits in 64-bit hash register. */
10716 XM_OUTHASH(IoC, PortNumber, XM_HSM, &OnesHash);
10717-
10718+
10719 /* Enable Hashing */
10720 SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
10721 }
10722 else if (Inexact != 0) {
10723-
10724+
10725 /* Set 64-bit hash register to InexactFilter. */
10726 XM_OUTHASH(IoC, PortNumber, XM_HSM, &pAPort->InexactFilter.Bytes[0]);
10727-
10728+
10729 /* Enable Hashing */
10730 SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
10731 }
10732@@ -1029,7 +1027,7 @@
10733
10734 /* Set port's current physical MAC address. */
10735 OutAddr = (SK_U16 *) &pAPort->CurrentMacAddress.a[0];
10736-
10737+
10738 XM_OUTADDR(IoC, PortNumber, XM_SA, OutAddr);
10739
10740 #ifdef xDEBUG
10741@@ -1039,9 +1037,9 @@
10742
10743 /* Get exact match address i from port PortNumber. */
10744 InAddr = (SK_U16 *) &InAddr8[0];
10745-
10746+
10747 XM_INADDR(IoC, PortNumber, XM_EXM(i), InAddr);
10748-
10749+
10750 SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
10751 ("SkAddrXmacMcUpdate: MC address %d on Port %u: ",
10752 "%02x %02x %02x %02x %02x %02x -- %02x %02x %02x %02x %02x %02x\n",
10753@@ -1058,7 +1056,7 @@
10754 pAPort->Exact[i].a[2],
10755 pAPort->Exact[i].a[3],
10756 pAPort->Exact[i].a[4],
10757- pAPort->Exact[i].a[5]))
10758+ pAPort->Exact[i].a[5]));
10759 }
10760 #endif /* DEBUG */
10761
10762@@ -1069,7 +1067,7 @@
10763 else {
10764 return (SK_MC_FILTERING_INEXACT);
10765 }
10766-
10767+
10768 } /* SkAddrXmacMcUpdate */
10769
10770 #endif /* GENESIS */
10771@@ -1097,7 +1095,7 @@
10772 * SK_MC_FILTERING_INEXACT
10773 * SK_ADDR_ILLEGAL_PORT
10774 */
10775-static int SkAddrGmacMcUpdate(
10776+int SkAddrGmacMcUpdate(
10777 SK_AC *pAC, /* adapter context */
10778 SK_IOC IoC, /* I/O context */
10779 SK_U32 PortNumber) /* Port Number */
10780@@ -1110,37 +1108,37 @@
10781 SK_ADDR_PORT *pAPort;
10782
10783 SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
10784- ("SkAddrGmacMcUpdate on Port %u.\n", PortNumber))
10785-
10786+ ("SkAddrGmacMcUpdate on Port %u.\n", PortNumber));
10787+
10788 pAPort = &pAC->Addr.Port[PortNumber];
10789
10790 #ifdef DEBUG
10791 SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
10792- ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber]))
10793+ ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber]));
10794 #endif /* DEBUG */
10795-
10796+
10797 #ifndef SK_SLIM
10798 for (Inexact = 0, i = 0; i < 8; i++) {
10799 Inexact |= pAPort->InexactFilter.Bytes[i];
10800 }
10801-
10802+
10803 /* Set 64-bit hash register to InexactFilter. */
10804 GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1,
10805 &pAPort->InexactFilter.Bytes[0]);
10806-
10807- if (pAPort->PromMode & SK_PROM_MODE_ALL_MC) {
10808-
10809+
10810+ if (pAPort->PromMode & SK_PROM_MODE_ALL_MC) {
10811+
10812 /* Set all bits in 64-bit hash register. */
10813 GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1, &OnesHash);
10814-
10815+
10816 /* Enable Hashing */
10817 SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
10818 }
10819- else {
10820+ else {
10821 /* Enable Hashing. */
10822 SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
10823 }
10824-
10825+
10826 if (pAPort->PromMode != SK_PROM_MODE_NONE) {
10827 (void) SkAddrGmacPromiscuousChange(pAC, IoC, PortNumber, pAPort->PromMode);
10828 }
10829@@ -1151,19 +1149,19 @@
10830
10831 /* Enable Hashing */
10832 SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
10833-
10834+
10835 (void) SkAddrGmacPromiscuousChange(pAC, IoC, PortNumber, pAPort->PromMode);
10836-
10837+
10838 #endif /* SK_SLIM */
10839-
10840+
10841 /* Set port's current physical MAC address. */
10842 OutAddr = (SK_U16 *) &pAPort->CurrentMacAddress.a[0];
10843 GM_OUTADDR(IoC, PortNumber, GM_SRC_ADDR_1L, OutAddr);
10844-
10845+
10846 /* Set port's current logical MAC address. */
10847 OutAddr = (SK_U16 *) &pAPort->Exact[0].a[0];
10848 GM_OUTADDR(IoC, PortNumber, GM_SRC_ADDR_2L, OutAddr);
10849-
10850+
10851 #ifdef DEBUG
10852 SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
10853 ("SkAddrGmacMcUpdate: Permanent Physical MAC Address: %02X %02X %02X %02X %02X %02X\n",
10854@@ -1172,8 +1170,8 @@
10855 pAPort->Exact[0].a[2],
10856 pAPort->Exact[0].a[3],
10857 pAPort->Exact[0].a[4],
10858- pAPort->Exact[0].a[5]))
10859-
10860+ pAPort->Exact[0].a[5]));
10861+
10862 SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
10863 ("SkAddrGmacMcUpdate: Physical MAC Address: %02X %02X %02X %02X %02X %02X\n",
10864 pAPort->CurrentMacAddress.a[0],
10865@@ -1181,9 +1179,9 @@
10866 pAPort->CurrentMacAddress.a[2],
10867 pAPort->CurrentMacAddress.a[3],
10868 pAPort->CurrentMacAddress.a[4],
10869- pAPort->CurrentMacAddress.a[5]))
10870+ pAPort->CurrentMacAddress.a[5]));
10871 #endif /* DEBUG */
10872-
10873+
10874 #ifndef SK_SLIM
10875 /* Determine return value. */
10876 if (Inexact == 0 && pAPort->PromMode == 0) {
10877@@ -1195,7 +1193,7 @@
10878 #else /* SK_SLIM */
10879 return (SK_MC_FILTERING_INEXACT);
10880 #endif /* SK_SLIM */
10881-
10882+
10883 } /* SkAddrGmacMcUpdate */
10884
10885 #endif /* YUKON */
10886@@ -1290,26 +1288,46 @@
10887 (void) SkAddrMcUpdate(pAC, IoC, PortNumber);
10888 }
10889 else if (Flags & SK_ADDR_PHYSICAL_ADDRESS) { /* Physical MAC address. */
10890- if (SK_ADDR_EQUAL(pNewAddr->a,
10891- pAC->Addr.Net[NetNumber].CurrentMacAddress.a)) {
10892- return (SK_ADDR_DUPLICATE_ADDRESS);
10893- }
10894-
10895 for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) {
10896 if (!pAC->Addr.Port[i].CurrentMacAddressSet) {
10897 return (SK_ADDR_TOO_EARLY);
10898 }
10899+ }
10900
10901+ /*
10902+ * In dual net mode it should be possible to set all MAC
10903+ * addresses independently. Therefore the equality checks
10904+ * against the locical address of the same port and the
10905+ * physical address of the other port are suppressed here.
10906+ */
10907+#ifndef SK_NO_RLMT
10908+ if (pAC->Rlmt.NumNets == 1) {
10909+#endif /* SK_NO_RLMT */
10910 if (SK_ADDR_EQUAL(pNewAddr->a,
10911- pAC->Addr.Port[i].CurrentMacAddress.a)) {
10912- if (i == PortNumber) {
10913- return (SK_ADDR_SUCCESS);
10914- }
10915- else {
10916- return (SK_ADDR_DUPLICATE_ADDRESS);
10917+ pAC->Addr.Net[NetNumber].CurrentMacAddress.a)) {
10918+ return (SK_ADDR_DUPLICATE_ADDRESS);
10919+ }
10920+
10921+ for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) {
10922+ if (SK_ADDR_EQUAL(pNewAddr->a,
10923+ pAC->Addr.Port[i].CurrentMacAddress.a)) {
10924+ if (i == PortNumber) {
10925+ return (SK_ADDR_SUCCESS);
10926+ }
10927+ else {
10928+ return (SK_ADDR_DUPLICATE_ADDRESS);
10929+ }
10930 }
10931 }
10932+#ifndef SK_NO_RLMT
10933 }
10934+ else {
10935+ if (SK_ADDR_EQUAL(pNewAddr->a,
10936+ pAC->Addr.Port[PortNumber].CurrentMacAddress.a)) {
10937+ return (SK_ADDR_SUCCESS);
10938+ }
10939+ }
10940+#endif /* SK_NO_RLMT */
10941
10942 pAC->Addr.Port[PortNumber].PreviousMacAddress =
10943 pAC->Addr.Port[PortNumber].CurrentMacAddress;
10944@@ -1340,18 +1358,32 @@
10945 pAC->Addr.Net[NetNumber].CurrentMacAddress.a)) {
10946 return (SK_ADDR_SUCCESS);
10947 }
10948-
10949+
10950 for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) {
10951 if (!pAC->Addr.Port[i].CurrentMacAddressSet) {
10952 return (SK_ADDR_TOO_EARLY);
10953 }
10954+ }
10955
10956- if (SK_ADDR_EQUAL(pNewAddr->a,
10957- pAC->Addr.Port[i].CurrentMacAddress.a)) {
10958- return (SK_ADDR_DUPLICATE_ADDRESS);
10959+ /*
10960+ * In dual net mode on Yukon-2 adapters the physical address
10961+ * of port 0 and the logical address of port 1 are equal - in
10962+ * this case the equality check of the physical address leads
10963+ * to an error and is suppressed here.
10964+ */
10965+#ifndef SK_NO_RLMT
10966+ if (pAC->Rlmt.NumNets == 1) {
10967+#endif /* SK_NO_RLMT */
10968+ for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) {
10969+ if (SK_ADDR_EQUAL(pNewAddr->a,
10970+ pAC->Addr.Port[i].CurrentMacAddress.a)) {
10971+ return (SK_ADDR_DUPLICATE_ADDRESS);
10972+ }
10973 }
10974+#ifndef SK_NO_RLMT
10975 }
10976-
10977+#endif /* SK_NO_RLMT */
10978+
10979 /*
10980 * In case that the physical and the logical MAC addresses are equal
10981 * we must also change the physical MAC address here.
10982@@ -1360,11 +1392,11 @@
10983 */
10984 if (SK_ADDR_EQUAL(pAC->Addr.Port[PortNumber].CurrentMacAddress.a,
10985 pAC->Addr.Port[PortNumber].Exact[0].a)) {
10986-
10987+
10988 pAC->Addr.Port[PortNumber].PreviousMacAddress =
10989 pAC->Addr.Port[PortNumber].CurrentMacAddress;
10990 pAC->Addr.Port[PortNumber].CurrentMacAddress = *pNewAddr;
10991-
10992+
10993 #ifndef SK_NO_RLMT
10994 /* Report address change to RLMT. */
10995 Para.Para32[0] = PortNumber;
10996@@ -1372,7 +1404,7 @@
10997 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_PORT_ADDR, Para);
10998 #endif /* !SK_NO_RLMT */
10999 }
11000-
11001+
11002 #ifndef SK_NO_RLMT
11003 /* Set PortNumber to number of net's active port. */
11004 PortNumber = pAC->Rlmt.Net[NetNumber].
11005@@ -1388,8 +1420,8 @@
11006 pAC->Addr.Net[NetNumber].PermanentMacAddress.a[2],
11007 pAC->Addr.Net[NetNumber].PermanentMacAddress.a[3],
11008 pAC->Addr.Net[NetNumber].PermanentMacAddress.a[4],
11009- pAC->Addr.Net[NetNumber].PermanentMacAddress.a[5]))
11010-
11011+ pAC->Addr.Net[NetNumber].PermanentMacAddress.a[5]));
11012+
11013 SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
11014 ("SkAddrOverride: New logical MAC Address: %02X %02X %02X %02X %02X %02X\n",
11015 pAC->Addr.Net[NetNumber].CurrentMacAddress.a[0],
11016@@ -1397,17 +1429,16 @@
11017 pAC->Addr.Net[NetNumber].CurrentMacAddress.a[2],
11018 pAC->Addr.Net[NetNumber].CurrentMacAddress.a[3],
11019 pAC->Addr.Net[NetNumber].CurrentMacAddress.a[4],
11020- pAC->Addr.Net[NetNumber].CurrentMacAddress.a[5]))
11021+ pAC->Addr.Net[NetNumber].CurrentMacAddress.a[5]));
11022 #endif /* DEBUG */
11023
11024- /* Write address to first exact match entry of active port. */
11025- (void) SkAddrMcUpdate(pAC, IoC, PortNumber);
11026+ /* Write address to first exact match entry of active port. */
11027+ (void)SkAddrMcUpdate(pAC, IoC, PortNumber);
11028 }
11029
11030 return (SK_ADDR_SUCCESS);
11031-
11032-} /* SkAddrOverride */
11033
11034+} /* SkAddrOverride */
11035
11036 #endif /* SK_NO_MAO */
11037
11038@@ -1439,7 +1470,8 @@
11039 SK_U32 PortNumber, /* port whose promiscuous mode changes */
11040 int NewPromMode) /* new promiscuous mode */
11041 {
11042- int ReturnCode = 0;
11043+ int ReturnCode = SK_ADDR_ILLEGAL_PORT;
11044+
11045 #if (!defined(SK_SLIM) || defined(DEBUG))
11046 if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
11047 return (SK_ADDR_ILLEGAL_PORT);
11048@@ -1483,7 +1515,7 @@
11049 * SK_ADDR_SUCCESS
11050 * SK_ADDR_ILLEGAL_PORT
11051 */
11052-static int SkAddrXmacPromiscuousChange(
11053+int SkAddrXmacPromiscuousChange(
11054 SK_AC *pAC, /* adapter context */
11055 SK_IOC IoC, /* I/O context */
11056 SK_U32 PortNumber, /* port whose promiscuous mode changes */
11057@@ -1504,17 +1536,18 @@
11058 /* Promiscuous mode! */
11059 CurPromMode |= SK_PROM_MODE_LLC;
11060 }
11061-
11062+
11063 for (Inexact = 0xFF, i = 0; i < 8; i++) {
11064 Inexact &= pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i];
11065 }
11066+
11067 if (Inexact == 0xFF) {
11068 CurPromMode |= (pAC->Addr.Port[PortNumber].PromMode & SK_PROM_MODE_ALL_MC);
11069 }
11070 else {
11071 /* Get InexactModeBit (bit XM_MD_ENA_HASH in mode register) */
11072 XM_IN16(IoC, PortNumber, XM_MODE, &LoMode);
11073-
11074+
11075 InexactModeBit = (LoMode & XM_MD_ENA_HASH) != 0;
11076
11077 /* Read 64-bit hash register from XMAC */
11078@@ -1537,7 +1570,7 @@
11079
11080 if ((NewPromMode & SK_PROM_MODE_ALL_MC) &&
11081 !(CurPromMode & SK_PROM_MODE_ALL_MC)) { /* All MC. */
11082-
11083+
11084 /* Set all bits in 64-bit hash register. */
11085 XM_OUTHASH(IoC, PortNumber, XM_HSM, &OnesHash);
11086
11087@@ -1573,9 +1606,9 @@
11088 /* Clear Promiscuous Mode */
11089 SkMacPromiscMode(pAC, IoC, (int) PortNumber, SK_FALSE);
11090 }
11091-
11092+
11093 return (SK_ADDR_SUCCESS);
11094-
11095+
11096 } /* SkAddrXmacPromiscuousChange */
11097
11098 #endif /* GENESIS */
11099@@ -1600,7 +1633,7 @@
11100 * SK_ADDR_SUCCESS
11101 * SK_ADDR_ILLEGAL_PORT
11102 */
11103-static int SkAddrGmacPromiscuousChange(
11104+int SkAddrGmacPromiscuousChange(
11105 SK_AC *pAC, /* adapter context */
11106 SK_IOC IoC, /* I/O context */
11107 SK_U32 PortNumber, /* port whose promiscuous mode changes */
11108@@ -1622,22 +1655,25 @@
11109 CurPromMode |= (pAC->Addr.Port[PortNumber].PromMode & SK_PROM_MODE_ALL_MC);
11110 }
11111
11112+ /* dummy read after GM_IN16() */
11113+ SK_IN16(IoC, B0_RAP, &ReceiveControl);
11114+
11115 pAC->Addr.Port[PortNumber].PromMode = NewPromMode;
11116
11117 if (NewPromMode == CurPromMode) {
11118 return (SK_ADDR_SUCCESS);
11119 }
11120-
11121+
11122 if ((NewPromMode & SK_PROM_MODE_ALL_MC) &&
11123 !(CurPromMode & SK_PROM_MODE_ALL_MC)) { /* All MC */
11124-
11125+
11126 /* Set all bits in 64-bit hash register. */
11127 GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1, &OnesHash);
11128-
11129+
11130 /* Enable Hashing */
11131 SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
11132 }
11133-
11134+
11135 if ((CurPromMode & SK_PROM_MODE_ALL_MC) &&
11136 !(NewPromMode & SK_PROM_MODE_ALL_MC)) { /* Norm. MC */
11137
11138@@ -1651,19 +1687,19 @@
11139
11140 if ((NewPromMode & SK_PROM_MODE_LLC) &&
11141 !(CurPromMode & SK_PROM_MODE_LLC)) { /* Prom. LLC */
11142-
11143+
11144 /* Set the MAC to Promiscuous Mode. */
11145 SkMacPromiscMode(pAC, IoC, (int) PortNumber, SK_TRUE);
11146 }
11147 else if ((CurPromMode & SK_PROM_MODE_LLC) &&
11148 !(NewPromMode & SK_PROM_MODE_LLC)) { /* Norm. LLC */
11149-
11150+
11151 /* Clear Promiscuous Mode. */
11152 SkMacPromiscMode(pAC, IoC, (int) PortNumber, SK_FALSE);
11153 }
11154
11155 return (SK_ADDR_SUCCESS);
11156-
11157+
11158 } /* SkAddrGmacPromiscuousChange */
11159
11160 #endif /* YUKON */
11161@@ -1735,33 +1771,33 @@
11162 pAC->Addr.Port[ToPortNumber].InexactFilter.Bytes[i];
11163 pAC->Addr.Port[ToPortNumber].InexactFilter.Bytes[i] = Byte;
11164 }
11165-
11166+
11167 i = pAC->Addr.Port[FromPortNumber].PromMode;
11168 pAC->Addr.Port[FromPortNumber].PromMode = pAC->Addr.Port[ToPortNumber].PromMode;
11169 pAC->Addr.Port[ToPortNumber].PromMode = i;
11170-
11171+
11172 if (pAC->GIni.GIGenesis) {
11173 DWord = pAC->Addr.Port[FromPortNumber].FirstExactMatchRlmt;
11174 pAC->Addr.Port[FromPortNumber].FirstExactMatchRlmt =
11175 pAC->Addr.Port[ToPortNumber].FirstExactMatchRlmt;
11176 pAC->Addr.Port[ToPortNumber].FirstExactMatchRlmt = DWord;
11177-
11178+
11179 DWord = pAC->Addr.Port[FromPortNumber].NextExactMatchRlmt;
11180 pAC->Addr.Port[FromPortNumber].NextExactMatchRlmt =
11181 pAC->Addr.Port[ToPortNumber].NextExactMatchRlmt;
11182 pAC->Addr.Port[ToPortNumber].NextExactMatchRlmt = DWord;
11183-
11184+
11185 DWord = pAC->Addr.Port[FromPortNumber].FirstExactMatchDrv;
11186 pAC->Addr.Port[FromPortNumber].FirstExactMatchDrv =
11187 pAC->Addr.Port[ToPortNumber].FirstExactMatchDrv;
11188 pAC->Addr.Port[ToPortNumber].FirstExactMatchDrv = DWord;
11189-
11190+
11191 DWord = pAC->Addr.Port[FromPortNumber].NextExactMatchDrv;
11192 pAC->Addr.Port[FromPortNumber].NextExactMatchDrv =
11193 pAC->Addr.Port[ToPortNumber].NextExactMatchDrv;
11194 pAC->Addr.Port[ToPortNumber].NextExactMatchDrv = DWord;
11195 }
11196-
11197+
11198 /* CAUTION: Solution works if only ports of one adapter are in use. */
11199 for (i = 0; (SK_U32) i < pAC->Rlmt.Net[pAC->Rlmt.Port[ToPortNumber].
11200 Net->NetNumber].NumPorts; i++) {
11201@@ -1772,12 +1808,12 @@
11202 /* 20001207 RA: Was "ToPortNumber;". */
11203 }
11204 }
11205-
11206+
11207 (void) SkAddrMcUpdate(pAC, IoC, FromPortNumber);
11208 (void) SkAddrMcUpdate(pAC, IoC, ToPortNumber);
11209
11210 return (SK_ADDR_SUCCESS);
11211-
11212+
11213 } /* SkAddrSwap */
11214
11215 #endif /* !SK_SLIM */
11216diff -ruN linux/drivers/net/sk98lin/skcsum.c linux-new/drivers/net/sk98lin/skcsum.c
11217--- linux/drivers/net/sk98lin/skcsum.c 1970-01-01 01:00:00.000000000 +0100
11218+++ linux-new/drivers/net/sk98lin/skcsum.c 2006-10-13 11:18:48.000000000 +0200
11219@@ -0,0 +1,873 @@
11220+/******************************************************************************
11221+ *
11222+ * Name: skcsum.c
11223+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
11224+ * Version: $Revision$
11225+ * Date: $Date$
11226+ * Purpose: Store/verify Internet checksum in send/receive packets.
11227+ *
11228+ ******************************************************************************/
11229+
11230+/******************************************************************************
11231+ *
11232+ * LICENSE:
11233+ * (C)Copyright 1998-2003 SysKonnect GmbH.
11234+ *
11235+ * This program is free software; you can redistribute it and/or modify
11236+ * it under the terms of the GNU General Public License as published by
11237+ * the Free Software Foundation; either version 2 of the License, or
11238+ * (at your option) any later version.
11239+ *
11240+ * The information in this file is provided "AS IS" without warranty.
11241+ * /LICENSE
11242+ *
11243+ ******************************************************************************/
11244+
11245+#ifdef SK_USE_CSUM /* Check if CSUM is to be used. */
11246+
11247+#ifndef lint
11248+static const char SysKonnectFileId[] =
11249+ "@(#) $Id$ (C) SysKonnect.";
11250+#endif /* !lint */
11251+
11252+/******************************************************************************
11253+ *
11254+ * Description:
11255+ *
11256+ * This is the "GEnesis" common module "CSUM".
11257+ *
11258+ * This module contains the code necessary to calculate, store, and verify the
11259+ * Internet Checksum of IP, TCP, and UDP frames.
11260+ *
11261+ * "GEnesis" is an abbreviation of "Gigabit Ethernet Network System in Silicon"
11262+ * and is the code name of this SysKonnect project.
11263+ *
11264+ * Compilation Options:
11265+ *
11266+ * SK_USE_CSUM - Define if CSUM is to be used. Otherwise, CSUM will be an
11267+ * empty module.
11268+ *
11269+ * SKCS_OVERWRITE_PROTO - Define to overwrite the default protocol id
11270+ * definitions. In this case, all SKCS_PROTO_xxx definitions must be made
11271+ * external.
11272+ *
11273+ * SKCS_OVERWRITE_STATUS - Define to overwrite the default return status
11274+ * definitions. In this case, all SKCS_STATUS_xxx definitions must be made
11275+ * external.
11276+ *
11277+ * Include File Hierarchy:
11278+ *
11279+ * "h/skdrv1st.h"
11280+ * "h/skcsum.h"
11281+ * "h/sktypes.h"
11282+ * "h/skqueue.h"
11283+ * "h/skdrv2nd.h"
11284+ *
11285+ ******************************************************************************/
11286+
11287+#include "h/skdrv1st.h"
11288+#include "h/skcsum.h"
11289+#include "h/skdrv2nd.h"
11290+
11291+/* defines ********************************************************************/
11292+
11293+/* The size of an Ethernet MAC header. */
11294+#define SKCS_ETHERNET_MAC_HEADER_SIZE (6+6+2)
11295+
11296+/* The size of the used topology's MAC header. */
11297+#define SKCS_MAC_HEADER_SIZE SKCS_ETHERNET_MAC_HEADER_SIZE
11298+
11299+/* The size of the IP header without any option fields. */
11300+#define SKCS_IP_HEADER_SIZE 20
11301+
11302+/*
11303+ * Field offsets within the IP header.
11304+ */
11305+
11306+/* "Internet Header Version" and "Length". */
11307+#define SKCS_OFS_IP_HEADER_VERSION_AND_LENGTH 0
11308+
11309+/* "Total Length". */
11310+#define SKCS_OFS_IP_TOTAL_LENGTH 2
11311+
11312+/* "Flags" "Fragment Offset". */
11313+#define SKCS_OFS_IP_FLAGS_AND_FRAGMENT_OFFSET 6
11314+
11315+/* "Next Level Protocol" identifier. */
11316+#define SKCS_OFS_IP_NEXT_LEVEL_PROTOCOL 9
11317+
11318+/* Source IP address. */
11319+#define SKCS_OFS_IP_SOURCE_ADDRESS 12
11320+
11321+/* Destination IP address. */
11322+#define SKCS_OFS_IP_DESTINATION_ADDRESS 16
11323+
11324+
11325+/*
11326+ * Field offsets within the UDP header.
11327+ */
11328+
11329+/* UDP checksum. */
11330+#define SKCS_OFS_UDP_CHECKSUM 6
11331+
11332+/* IP "Next Level Protocol" identifiers (see RFC 790). */
11333+#define SKCS_PROTO_ID_TCP 6 /* Transport Control Protocol */
11334+#define SKCS_PROTO_ID_UDP 17 /* User Datagram Protocol */
11335+
11336+/* IP "Don't Fragment" bit. */
11337+#define SKCS_IP_DONT_FRAGMENT SKCS_HTON16(0x4000)
11338+
11339+/* Add a byte offset to a pointer. */
11340+#define SKCS_IDX(pPtr, Ofs) ((void *) ((char *) (pPtr) + (Ofs)))
11341+
11342+/*
11343+ * Macros that convert host to network representation and vice versa, i.e.
11344+ * little/big endian conversion on little endian machines only.
11345+ */
11346+#ifdef SK_LITTLE_ENDIAN
11347+#define SKCS_HTON16(Val16) (((unsigned) (Val16) >> 8) | (((Val16) & 0xff) << 8))
11348+#endif /* SK_LITTLE_ENDIAN */
11349+#ifdef SK_BIG_ENDIAN
11350+#define SKCS_HTON16(Val16) (Val16)
11351+#endif /* SK_BIG_ENDIAN */
11352+#define SKCS_NTOH16(Val16) SKCS_HTON16(Val16)
11353+
11354+/* typedefs *******************************************************************/
11355+
11356+/* function prototypes ********************************************************/
11357+
11358+/******************************************************************************
11359+ *
11360+ * SkCsGetSendInfo - get checksum information for a send packet
11361+ *
11362+ * Description:
11363+ * Get all checksum information necessary to send a TCP or UDP packet. The
11364+ * function checks the IP header passed to it. If the high-level protocol
11365+ * is either TCP or UDP the pseudo header checksum is calculated and
11366+ * returned.
11367+ *
11368+ * The function returns the total length of the IP header (including any
11369+ * IP option fields), which is the same as the start offset of the IP data
11370+ * which in turn is the start offset of the TCP or UDP header.
11371+ *
11372+ * The function also returns the TCP or UDP pseudo header checksum, which
11373+ * should be used as the start value for the hardware checksum calculation.
11374+ * (Note that any actual pseudo header checksum can never calculate to
11375+ * zero.)
11376+ *
11377+ * Note:
11378+ * There is a bug in the GENESIS ASIC which may lead to wrong checksums.
11379+ *
11380+ * Arguments:
11381+ * pAc - A pointer to the adapter context struct.
11382+ *
11383+ * pIpHeader - Pointer to IP header. Must be at least the IP header *not*
11384+ * including any option fields, i.e. at least 20 bytes.
11385+ *
11386+ * Note: This pointer will be used to address 8-, 16-, and 32-bit
11387+ * variables with the respective alignment offsets relative to the pointer.
11388+ * Thus, the pointer should point to a 32-bit aligned address. If the
11389+ * target system cannot address 32-bit variables on non 32-bit aligned
11390+ * addresses, then the pointer *must* point to a 32-bit aligned address.
11391+ *
11392+ * pPacketInfo - A pointer to the packet information structure for this
11393+ * packet. Before calling this SkCsGetSendInfo(), the following field must
11394+ * be initialized:
11395+ *
11396+ * ProtocolFlags - Initialize with any combination of
11397+ * SKCS_PROTO_XXX bit flags. SkCsGetSendInfo() will only work on
11398+ * the protocols specified here. Any protocol(s) not specified
11399+ * here will be ignored.
11400+ *
11401+ * Note: Only one checksum can be calculated in hardware. Thus, if
11402+ * SKCS_PROTO_IP is specified in the 'ProtocolFlags',
11403+ * SkCsGetSendInfo() must calculate the IP header checksum in
11404+ * software. It might be a better idea to have the calling
11405+ * protocol stack calculate the IP header checksum.
11406+ *
11407+ * Returns: N/A
11408+ * On return, the following fields in 'pPacketInfo' may or may not have
11409+ * been filled with information, depending on the protocol(s) found in the
11410+ * packet:
11411+ *
11412+ * ProtocolFlags - Returns the SKCS_PROTO_XXX bit flags of the protocol(s)
11413+ * that were both requested by the caller and actually found in the packet.
11414+ * Protocol(s) not specified by the caller and/or not found in the packet
11415+ * will have their respective SKCS_PROTO_XXX bit flags reset.
11416+ *
11417+ * Note: For IP fragments, TCP and UDP packet information is ignored.
11418+ *
11419+ * IpHeaderLength - The total length in bytes of the complete IP header
11420+ * including any option fields is returned here. This is the start offset
11421+ * of the IP data, i.e. the TCP or UDP header if present.
11422+ *
11423+ * IpHeaderChecksum - If IP has been specified in the 'ProtocolFlags', the
11424+ * 16-bit Internet Checksum of the IP header is returned here. This value
11425+ * is to be stored into the packet's 'IP Header Checksum' field.
11426+ *
11427+ * PseudoHeaderChecksum - If this is a TCP or UDP packet and if TCP or UDP
11428+ * has been specified in the 'ProtocolFlags', the 16-bit Internet Checksum
11429+ * of the TCP or UDP pseudo header is returned here.
11430+ */
11431+void SkCsGetSendInfo(
11432+SK_AC *pAc, /* Adapter context struct. */
11433+void *pIpHeader, /* IP header. */
11434+SKCS_PACKET_INFO *pPacketInfo, /* Packet information struct. */
11435+int NetNumber) /* Net number */
11436+{
11437+ /* Internet Header Version found in IP header. */
11438+ unsigned InternetHeaderVersion;
11439+
11440+ /* Length of the IP header as found in IP header. */
11441+ unsigned IpHeaderLength;
11442+
11443+ /* Bit field specifiying the desired/found protocols. */
11444+ unsigned ProtocolFlags;
11445+
11446+ /* Next level protocol identifier found in IP header. */
11447+ unsigned NextLevelProtocol;
11448+
11449+ /* Length of IP data portion. */
11450+ unsigned IpDataLength;
11451+
11452+ /* TCP/UDP pseudo header checksum. */
11453+ unsigned long PseudoHeaderChecksum;
11454+
11455+ /* Pointer to next level protocol statistics structure. */
11456+ SKCS_PROTO_STATS *NextLevelProtoStats;
11457+
11458+ /* Temporary variable. */
11459+ unsigned Tmp;
11460+
11461+ Tmp = *(SK_U8 *)
11462+ SKCS_IDX(pIpHeader, SKCS_OFS_IP_HEADER_VERSION_AND_LENGTH);
11463+
11464+ /* Get the Internet Header Version (IHV). */
11465+ /* Note: The IHV is stored in the upper four bits. */
11466+
11467+ InternetHeaderVersion = Tmp >> 4;
11468+
11469+ /* Check the Internet Header Version. */
11470+ /* Note: We currently only support IP version 4. */
11471+
11472+ if (InternetHeaderVersion != 4) { /* IPv4? */
11473+ SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_TX,
11474+ ("Tx: Unknown Internet Header Version %u.\n",
11475+ InternetHeaderVersion));
11476+ pPacketInfo->ProtocolFlags = 0;
11477+ pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].TxUnableCts++;
11478+ return;
11479+ }
11480+
11481+ /* Get the IP header length (IHL). */
11482+ /*
11483+ * Note: The IHL is stored in the lower four bits as the number of
11484+ * 4-byte words.
11485+ */
11486+
11487+ IpHeaderLength = (Tmp & 0xf) * 4;
11488+ pPacketInfo->IpHeaderLength = IpHeaderLength;
11489+
11490+ /* Check the IP header length. */
11491+
11492+ /* 04-Aug-1998 sw - Really check the IHL? Necessary? */
11493+
11494+ if (IpHeaderLength < 5*4) {
11495+ SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_TX,
11496+ ("Tx: Invalid IP Header Length %u.\n", IpHeaderLength));
11497+ pPacketInfo->ProtocolFlags = 0;
11498+ pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].TxUnableCts++;
11499+ return;
11500+ }
11501+
11502+ /* This is an IPv4 frame with a header of valid length. */
11503+
11504+ pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].TxOkCts++;
11505+
11506+ /* Check if we should calculate the IP header checksum. */
11507+
11508+ ProtocolFlags = pPacketInfo->ProtocolFlags;
11509+
11510+ if (ProtocolFlags & SKCS_PROTO_IP) {
11511+ pPacketInfo->IpHeaderChecksum =
11512+ SkCsCalculateChecksum(pIpHeader, IpHeaderLength);
11513+ }
11514+
11515+ /* Get the next level protocol identifier. */
11516+
11517+ NextLevelProtocol =
11518+ *(SK_U8 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_NEXT_LEVEL_PROTOCOL);
11519+
11520+ /*
11521+ * Check if this is a TCP or UDP frame and if we should calculate the
11522+ * TCP/UDP pseudo header checksum.
11523+ *
11524+ * Also clear all protocol bit flags of protocols not present in the
11525+ * frame.
11526+ */
11527+
11528+ if ((ProtocolFlags & SKCS_PROTO_TCP) != 0 &&
11529+ NextLevelProtocol == SKCS_PROTO_ID_TCP) {
11530+ /* TCP/IP frame. */
11531+ ProtocolFlags &= SKCS_PROTO_TCP | SKCS_PROTO_IP;
11532+ NextLevelProtoStats =
11533+ &pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_TCP];
11534+ }
11535+ else if ((ProtocolFlags & SKCS_PROTO_UDP) != 0 &&
11536+ NextLevelProtocol == SKCS_PROTO_ID_UDP) {
11537+ /* UDP/IP frame. */
11538+ ProtocolFlags &= SKCS_PROTO_UDP | SKCS_PROTO_IP;
11539+ NextLevelProtoStats =
11540+ &pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_UDP];
11541+ }
11542+ else {
11543+ /*
11544+ * Either not a TCP or UDP frame and/or TCP/UDP processing not
11545+ * specified.
11546+ */
11547+ pPacketInfo->ProtocolFlags = ProtocolFlags & SKCS_PROTO_IP;
11548+ return;
11549+ }
11550+
11551+ /* Check if this is an IP fragment. */
11552+
11553+ /*
11554+ * Note: An IP fragment has a non-zero "Fragment Offset" field and/or
11555+ * the "More Fragments" bit set. Thus, if both the "Fragment Offset"
11556+ * and the "More Fragments" are zero, it is *not* a fragment. We can
11557+ * easily check both at the same time since they are in the same 16-bit
11558+ * word.
11559+ */
11560+
11561+ if ((*(SK_U16 *)
11562+ SKCS_IDX(pIpHeader, SKCS_OFS_IP_FLAGS_AND_FRAGMENT_OFFSET) &
11563+ ~SKCS_IP_DONT_FRAGMENT) != 0) {
11564+ /* IP fragment; ignore all other protocols. */
11565+ pPacketInfo->ProtocolFlags = ProtocolFlags & SKCS_PROTO_IP;
11566+ NextLevelProtoStats->TxUnableCts++;
11567+ return;
11568+ }
11569+
11570+ /*
11571+ * Calculate the TCP/UDP pseudo header checksum.
11572+ */
11573+
11574+ /* Get total length of IP header and data. */
11575+
11576+ IpDataLength =
11577+ *(SK_U16 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_TOTAL_LENGTH);
11578+
11579+ /* Get length of IP data portion. */
11580+
11581+ IpDataLength = SKCS_NTOH16(IpDataLength) - IpHeaderLength;
11582+
11583+ /* Calculate the sum of all pseudo header fields (16-bit). */
11584+
11585+ PseudoHeaderChecksum =
11586+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
11587+ SKCS_OFS_IP_SOURCE_ADDRESS + 0) +
11588+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
11589+ SKCS_OFS_IP_SOURCE_ADDRESS + 2) +
11590+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
11591+ SKCS_OFS_IP_DESTINATION_ADDRESS + 0) +
11592+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
11593+ SKCS_OFS_IP_DESTINATION_ADDRESS + 2) +
11594+ (unsigned long) SKCS_HTON16(NextLevelProtocol) +
11595+ (unsigned long) SKCS_HTON16(IpDataLength);
11596+
11597+ /* Add-in any carries. */
11598+
11599+ SKCS_OC_ADD(PseudoHeaderChecksum, PseudoHeaderChecksum, 0);
11600+
11601+ /* Add-in any new carry. */
11602+
11603+ SKCS_OC_ADD(pPacketInfo->PseudoHeaderChecksum, PseudoHeaderChecksum, 0);
11604+
11605+ pPacketInfo->ProtocolFlags = ProtocolFlags;
11606+ NextLevelProtoStats->TxOkCts++; /* Success. */
11607+} /* SkCsGetSendInfo */
11608+
11609+
11610+/******************************************************************************
11611+ *
11612+ * SkCsGetReceiveInfo - verify checksum information for a received packet
11613+ *
11614+ * Description:
11615+ * Verify a received frame's checksum. The function returns a status code
11616+ * reflecting the result of the verification.
11617+ *
11618+ * Note:
11619+ * Before calling this function you have to verify that the frame is
11620+ * not padded and Checksum1 and Checksum2 are bigger than 1.
11621+ *
11622+ * Arguments:
11623+ * pAc - Pointer to adapter context struct.
11624+ *
11625+ * pIpHeader - Pointer to IP header. Must be at least the length in bytes
11626+ * of the received IP header including any option fields. For UDP packets,
11627+ * 8 additional bytes are needed to access the UDP checksum.
11628+ *
11629+ * Note: The actual length of the IP header is stored in the lower four
11630+ * bits of the first octet of the IP header as the number of 4-byte words,
11631+ * so it must be multiplied by four to get the length in bytes. Thus, the
11632+ * maximum IP header length is 15 * 4 = 60 bytes.
11633+ *
11634+ * Checksum1 - The first 16-bit Internet Checksum calculated by the
11635+ * hardware starting at the offset returned by SkCsSetReceiveFlags().
11636+ *
11637+ * Checksum2 - The second 16-bit Internet Checksum calculated by the
11638+ * hardware starting at the offset returned by SkCsSetReceiveFlags().
11639+ *
11640+ * Returns:
11641+ * SKCS_STATUS_UNKNOWN_IP_VERSION - Not an IP v4 frame.
11642+ * SKCS_STATUS_IP_CSUM_ERROR - IP checksum error.
11643+ * SKCS_STATUS_IP_CSUM_ERROR_TCP - IP checksum error in TCP frame.
11644+ * SKCS_STATUS_IP_CSUM_ERROR_UDP - IP checksum error in UDP frame
11645+ * SKCS_STATUS_IP_FRAGMENT - IP fragment (IP checksum ok).
11646+ * SKCS_STATUS_IP_CSUM_OK - IP checksum ok (not a TCP or UDP frame).
11647+ * SKCS_STATUS_TCP_CSUM_ERROR - TCP checksum error (IP checksum ok).
11648+ * SKCS_STATUS_UDP_CSUM_ERROR - UDP checksum error (IP checksum ok).
11649+ * SKCS_STATUS_TCP_CSUM_OK - IP and TCP checksum ok.
11650+ * SKCS_STATUS_UDP_CSUM_OK - IP and UDP checksum ok.
11651+ * SKCS_STATUS_IP_CSUM_OK_NO_UDP - IP checksum OK and no UDP checksum.
11652+ *
11653+ * Note: If SKCS_OVERWRITE_STATUS is defined, the SKCS_STATUS_XXX values
11654+ * returned here can be defined in some header file by the module using CSUM.
11655+ * In this way, the calling module can assign return values for its own needs,
11656+ * e.g. by assigning bit flags to the individual protocols.
11657+ */
11658+SKCS_STATUS SkCsGetReceiveInfo(
11659+SK_AC *pAc, /* Adapter context struct. */
11660+void *pIpHeader, /* IP header. */
11661+unsigned Checksum1, /* Hardware checksum 1. */
11662+unsigned Checksum2, /* Hardware checksum 2. */
11663+int NetNumber) /* Net number */
11664+{
11665+ /* Internet Header Version found in IP header. */
11666+ unsigned InternetHeaderVersion;
11667+
11668+ /* Length of the IP header as found in IP header. */
11669+ unsigned IpHeaderLength;
11670+
11671+ /* Length of IP data portion. */
11672+ unsigned IpDataLength;
11673+
11674+ /* IP header checksum. */
11675+ unsigned IpHeaderChecksum;
11676+
11677+ /* IP header options checksum, if any. */
11678+ unsigned IpOptionsChecksum;
11679+
11680+ /* IP data checksum, i.e. TCP/UDP checksum. */
11681+ unsigned IpDataChecksum;
11682+
11683+ /* Next level protocol identifier found in IP header. */
11684+ unsigned NextLevelProtocol;
11685+
11686+ /* The checksum of the "next level protocol", i.e. TCP or UDP. */
11687+ unsigned long NextLevelProtocolChecksum;
11688+
11689+ /* Pointer to next level protocol statistics structure. */
11690+ SKCS_PROTO_STATS *NextLevelProtoStats;
11691+
11692+ /* Temporary variable. */
11693+ unsigned Tmp;
11694+
11695+ Tmp = *(SK_U8 *)
11696+ SKCS_IDX(pIpHeader, SKCS_OFS_IP_HEADER_VERSION_AND_LENGTH);
11697+
11698+ /* Get the Internet Header Version (IHV). */
11699+ /* Note: The IHV is stored in the upper four bits. */
11700+
11701+ InternetHeaderVersion = Tmp >> 4;
11702+
11703+ /* Check the Internet Header Version. */
11704+ /* Note: We currently only support IP version 4. */
11705+
11706+ if (InternetHeaderVersion != 4) { /* IPv4? */
11707+ SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_RX,
11708+ ("Rx: Unknown Internet Header Version %u.\n",
11709+ InternetHeaderVersion));
11710+ pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxUnableCts++;
11711+ return (SKCS_STATUS_UNKNOWN_IP_VERSION);
11712+ }
11713+
11714+ /* Get the IP header length (IHL). */
11715+ /*
11716+ * Note: The IHL is stored in the lower four bits as the number of
11717+ * 4-byte words.
11718+ */
11719+
11720+ IpHeaderLength = (Tmp & 0xf) * 4;
11721+
11722+ /* Check the IP header length. */
11723+
11724+ /* 04-Aug-1998 sw - Really check the IHL? Necessary? */
11725+
11726+ if (IpHeaderLength < 5*4) {
11727+ SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_RX,
11728+ ("Rx: Invalid IP Header Length %u.\n", IpHeaderLength));
11729+ pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxErrCts++;
11730+ return (SKCS_STATUS_IP_CSUM_ERROR);
11731+ }
11732+
11733+ /* This is an IPv4 frame with a header of valid length. */
11734+
11735+ /* Get the IP header and data checksum. */
11736+
11737+ IpDataChecksum = Checksum2;
11738+
11739+ /*
11740+ * The IP header checksum is calculated as follows:
11741+ *
11742+ * IpHeaderChecksum = Checksum1 - Checksum2
11743+ */
11744+
11745+ SKCS_OC_SUB(IpHeaderChecksum, Checksum1, Checksum2);
11746+
11747+ /* Check if any IP header options. */
11748+
11749+ if (IpHeaderLength > SKCS_IP_HEADER_SIZE) {
11750+
11751+ /* Get the IP options checksum. */
11752+
11753+ IpOptionsChecksum = SkCsCalculateChecksum(
11754+ SKCS_IDX(pIpHeader, SKCS_IP_HEADER_SIZE),
11755+ IpHeaderLength - SKCS_IP_HEADER_SIZE);
11756+
11757+ /* Adjust the IP header and IP data checksums. */
11758+
11759+ SKCS_OC_ADD(IpHeaderChecksum, IpHeaderChecksum, IpOptionsChecksum);
11760+
11761+ SKCS_OC_SUB(IpDataChecksum, IpDataChecksum, IpOptionsChecksum);
11762+ }
11763+
11764+ /*
11765+ * Check if the IP header checksum is ok.
11766+ *
11767+ * NOTE: We must check the IP header checksum even if the caller just wants
11768+ * us to check upper-layer checksums, because we cannot do any further
11769+ * processing of the packet without a valid IP checksum.
11770+ */
11771+
11772+ /* Get the next level protocol identifier. */
11773+
11774+ NextLevelProtocol = *(SK_U8 *)
11775+ SKCS_IDX(pIpHeader, SKCS_OFS_IP_NEXT_LEVEL_PROTOCOL);
11776+
11777+ if (IpHeaderChecksum != 0xffff) {
11778+ pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxErrCts++;
11779+ /* the NDIS tester wants to know the upper level protocol too */
11780+ if (NextLevelProtocol == SKCS_PROTO_ID_TCP) {
11781+ return(SKCS_STATUS_IP_CSUM_ERROR_TCP);
11782+ }
11783+ else if (NextLevelProtocol == SKCS_PROTO_ID_UDP) {
11784+ return(SKCS_STATUS_IP_CSUM_ERROR_UDP);
11785+ }
11786+ return (SKCS_STATUS_IP_CSUM_ERROR);
11787+ }
11788+
11789+ /*
11790+ * Check if this is a TCP or UDP frame and if we should calculate the
11791+ * TCP/UDP pseudo header checksum.
11792+ *
11793+ * Also clear all protocol bit flags of protocols not present in the
11794+ * frame.
11795+ */
11796+
11797+ if ((pAc->Csum.ReceiveFlags[NetNumber] & SKCS_PROTO_TCP) != 0 &&
11798+ NextLevelProtocol == SKCS_PROTO_ID_TCP) {
11799+ /* TCP/IP frame. */
11800+ NextLevelProtoStats =
11801+ &pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_TCP];
11802+ }
11803+ else if ((pAc->Csum.ReceiveFlags[NetNumber] & SKCS_PROTO_UDP) != 0 &&
11804+ NextLevelProtocol == SKCS_PROTO_ID_UDP) {
11805+ /* UDP/IP frame. */
11806+ NextLevelProtoStats =
11807+ &pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_UDP];
11808+ }
11809+ else {
11810+ /*
11811+ * Either not a TCP or UDP frame and/or TCP/UDP processing not
11812+ * specified.
11813+ */
11814+ return (SKCS_STATUS_IP_CSUM_OK);
11815+ }
11816+
11817+ /* Check if this is an IP fragment. */
11818+
11819+ /*
11820+ * Note: An IP fragment has a non-zero "Fragment Offset" field and/or
11821+ * the "More Fragments" bit set. Thus, if both the "Fragment Offset"
11822+ * and the "More Fragments" are zero, it is *not* a fragment. We can
11823+ * easily check both at the same time since they are in the same 16-bit
11824+ * word.
11825+ */
11826+
11827+ if ((*(SK_U16 *)
11828+ SKCS_IDX(pIpHeader, SKCS_OFS_IP_FLAGS_AND_FRAGMENT_OFFSET) &
11829+ ~SKCS_IP_DONT_FRAGMENT) != 0) {
11830+ /* IP fragment; ignore all other protocols. */
11831+ NextLevelProtoStats->RxUnableCts++;
11832+ return (SKCS_STATUS_IP_FRAGMENT);
11833+ }
11834+
11835+ /*
11836+ * 08-May-2000 ra
11837+ *
11838+ * From RFC 768 (UDP)
11839+ * If the computed checksum is zero, it is transmitted as all ones (the
11840+ * equivalent in one's complement arithmetic). An all zero transmitted
11841+ * checksum value means that the transmitter generated no checksum (for
11842+ * debugging or for higher level protocols that don't care).
11843+ */
11844+
11845+ if (NextLevelProtocol == SKCS_PROTO_ID_UDP &&
11846+ *(SK_U16*)SKCS_IDX(pIpHeader, IpHeaderLength + 6) == 0x0000) {
11847+
11848+ NextLevelProtoStats->RxOkCts++;
11849+
11850+ return (SKCS_STATUS_IP_CSUM_OK_NO_UDP);
11851+ }
11852+
11853+ /*
11854+ * Calculate the TCP/UDP checksum.
11855+ */
11856+
11857+ /* Get total length of IP header and data. */
11858+
11859+ IpDataLength =
11860+ *(SK_U16 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_TOTAL_LENGTH);
11861+
11862+ /* Get length of IP data portion. */
11863+
11864+ IpDataLength = SKCS_NTOH16(IpDataLength) - IpHeaderLength;
11865+
11866+ NextLevelProtocolChecksum =
11867+
11868+ /* Calculate the pseudo header checksum. */
11869+
11870+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
11871+ SKCS_OFS_IP_SOURCE_ADDRESS + 0) +
11872+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
11873+ SKCS_OFS_IP_SOURCE_ADDRESS + 2) +
11874+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
11875+ SKCS_OFS_IP_DESTINATION_ADDRESS + 0) +
11876+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
11877+ SKCS_OFS_IP_DESTINATION_ADDRESS + 2) +
11878+ (unsigned long) SKCS_HTON16(NextLevelProtocol) +
11879+ (unsigned long) SKCS_HTON16(IpDataLength) +
11880+
11881+ /* Add the TCP/UDP header checksum. */
11882+
11883+ (unsigned long) IpDataChecksum;
11884+
11885+ /* Add-in any carries. */
11886+
11887+ SKCS_OC_ADD(NextLevelProtocolChecksum, NextLevelProtocolChecksum, 0);
11888+
11889+ /* Add-in any new carry. */
11890+
11891+ SKCS_OC_ADD(NextLevelProtocolChecksum, NextLevelProtocolChecksum, 0);
11892+
11893+ /* Check if the TCP/UDP checksum is ok. */
11894+
11895+ if ((unsigned) NextLevelProtocolChecksum == 0xffff) {
11896+
11897+ /* TCP/UDP checksum ok. */
11898+
11899+ NextLevelProtoStats->RxOkCts++;
11900+
11901+ return (NextLevelProtocol == SKCS_PROTO_ID_TCP ?
11902+ SKCS_STATUS_TCP_CSUM_OK : SKCS_STATUS_UDP_CSUM_OK);
11903+ }
11904+
11905+ /* TCP/UDP checksum error. */
11906+
11907+ NextLevelProtoStats->RxErrCts++;
11908+
11909+ return (NextLevelProtocol == SKCS_PROTO_ID_TCP ?
11910+ SKCS_STATUS_TCP_CSUM_ERROR : SKCS_STATUS_UDP_CSUM_ERROR);
11911+} /* SkCsGetReceiveInfo */
11912+
11913+
11914+/******************************************************************************
11915+ *
11916+ * SkCsSetReceiveFlags - set checksum receive flags
11917+ *
11918+ * Description:
11919+ * Use this function to set the various receive flags. According to the
11920+ * protocol flags set by the caller, the start offsets within received
11921+ * packets of the two hardware checksums are returned. These offsets must
11922+ * be stored in all receive descriptors.
11923+ *
11924+ * Arguments:
11925+ * pAc - Pointer to adapter context struct.
11926+ *
11927+ * ReceiveFlags - Any combination of SK_PROTO_XXX flags of the protocols
11928+ * for which the caller wants checksum information on received frames.
11929+ *
11930+ * pChecksum1Offset - The start offset of the first receive descriptor
11931+ * hardware checksum to be calculated for received frames is returned
11932+ * here.
11933+ *
11934+ * pChecksum2Offset - The start offset of the second receive descriptor
11935+ * hardware checksum to be calculated for received frames is returned
11936+ * here.
11937+ *
11938+ * Returns: N/A
11939+ * Returns the two hardware checksum start offsets.
11940+ */
11941+void SkCsSetReceiveFlags(
11942+SK_AC *pAc, /* Adapter context struct. */
11943+unsigned ReceiveFlags, /* New receive flags. */
11944+unsigned *pChecksum1Offset, /* Offset for hardware checksum 1. */
11945+unsigned *pChecksum2Offset, /* Offset for hardware checksum 2. */
11946+int NetNumber)
11947+{
11948+ /* Save the receive flags. */
11949+
11950+ pAc->Csum.ReceiveFlags[NetNumber] = ReceiveFlags;
11951+
11952+ /* First checksum start offset is the IP header. */
11953+ *pChecksum1Offset = SKCS_MAC_HEADER_SIZE;
11954+
11955+ /*
11956+ * Second checksum start offset is the IP data. Note that this may vary
11957+ * if there are any IP header options in the actual packet.
11958+ */
11959+ *pChecksum2Offset = SKCS_MAC_HEADER_SIZE + SKCS_IP_HEADER_SIZE;
11960+} /* SkCsSetReceiveFlags */
11961+
11962+#ifndef SK_CS_CALCULATE_CHECKSUM
11963+
11964+/******************************************************************************
11965+ *
11966+ * SkCsCalculateChecksum - calculate checksum for specified data
11967+ *
11968+ * Description:
11969+ * Calculate and return the 16-bit Internet Checksum for the specified
11970+ * data.
11971+ *
11972+ * Arguments:
11973+ * pData - Pointer to data for which the checksum shall be calculated.
11974+ * Note: The pointer should be aligned on a 16-bit boundary.
11975+ *
11976+ * Length - Length in bytes of data to checksum.
11977+ *
11978+ * Returns:
11979+ * The 16-bit Internet Checksum for the specified data.
11980+ *
11981+ * Note: The checksum is calculated in the machine's natural byte order,
11982+ * i.e. little vs. big endian. Thus, the resulting checksum is different
11983+ * for the same input data on little and big endian machines.
11984+ *
11985+ * However, when written back to the network packet, the byte order is
11986+ * always in correct network order.
11987+ */
11988+unsigned SkCsCalculateChecksum(
11989+void *pData, /* Data to checksum. */
11990+unsigned Length) /* Length of data. */
11991+{
11992+ SK_U16 *pU16; /* Pointer to the data as 16-bit words. */
11993+ unsigned long Checksum; /* Checksum; must be at least 32 bits. */
11994+
11995+ /* Sum up all 16-bit words. */
11996+
11997+ pU16 = (SK_U16 *) pData;
11998+ for (Checksum = 0; Length > 1; Length -= 2) {
11999+ Checksum += *pU16++;
12000+ }
12001+
12002+ /* If this is an odd number of bytes, add-in the last byte. */
12003+
12004+ if (Length > 0) {
12005+#ifdef SK_BIG_ENDIAN
12006+ /* Add the last byte as the high byte. */
12007+ Checksum += ((unsigned) *(SK_U8 *) pU16) << 8;
12008+#else /* !SK_BIG_ENDIAN */
12009+ /* Add the last byte as the low byte. */
12010+ Checksum += *(SK_U8 *) pU16;
12011+#endif /* !SK_BIG_ENDIAN */
12012+ }
12013+
12014+ /* Add-in any carries. */
12015+
12016+ SKCS_OC_ADD(Checksum, Checksum, 0);
12017+
12018+ /* Add-in any new carry. */
12019+
12020+ SKCS_OC_ADD(Checksum, Checksum, 0);
12021+
12022+ /* Note: All bits beyond the 16-bit limit are now zero. */
12023+
12024+ return ((unsigned) Checksum);
12025+} /* SkCsCalculateChecksum */
12026+
12027+#endif /* SK_CS_CALCULATE_CHECKSUM */
12028+
12029+/******************************************************************************
12030+ *
12031+ * SkCsEvent - the CSUM event dispatcher
12032+ *
12033+ * Description:
12034+ * This is the event handler for the CSUM module.
12035+ *
12036+ * Arguments:
12037+ * pAc - Pointer to adapter context.
12038+ *
12039+ * Ioc - I/O context.
12040+ *
12041+ * Event - Event id.
12042+ *
12043+ * Param - Event dependent parameter.
12044+ *
12045+ * Returns:
12046+ * The 16-bit Internet Checksum for the specified data.
12047+ *
12048+ * Note: The checksum is calculated in the machine's natural byte order,
12049+ * i.e. little vs. big endian. Thus, the resulting checksum is different
12050+ * for the same input data on little and big endian machines.
12051+ *
12052+ * However, when written back to the network packet, the byte order is
12053+ * always in correct network order.
12054+ */
12055+int SkCsEvent(
12056+SK_AC *pAc, /* Pointer to adapter context. */
12057+SK_IOC Ioc, /* I/O context. */
12058+SK_U32 Event, /* Event id. */
12059+SK_EVPARA Param) /* Event dependent parameter. */
12060+{
12061+ int ProtoIndex;
12062+ int NetNumber;
12063+
12064+ switch (Event) {
12065+ /*
12066+ * Clear protocol statistics.
12067+ *
12068+ * Param - Protocol index, or -1 for all protocols.
12069+ * - Net number.
12070+ */
12071+ case SK_CSUM_EVENT_CLEAR_PROTO_STATS:
12072+
12073+ ProtoIndex = (int)Param.Para32[1];
12074+ NetNumber = (int)Param.Para32[0];
12075+ if (ProtoIndex < 0) { /* Clear for all protocols. */
12076+ if (NetNumber >= 0) {
12077+ SK_MEMSET(&pAc->Csum.ProtoStats[NetNumber][0], 0,
12078+ sizeof(pAc->Csum.ProtoStats[NetNumber]));
12079+ }
12080+ }
12081+ else { /* Clear for individual protocol. */
12082+ SK_MEMSET(&pAc->Csum.ProtoStats[NetNumber][ProtoIndex], 0,
12083+ sizeof(pAc->Csum.ProtoStats[NetNumber][ProtoIndex]));
12084+ }
12085+ break;
12086+ default:
12087+ break;
12088+ }
12089+ return (0); /* Success. */
12090+} /* SkCsEvent */
12091+
12092+#endif /* SK_USE_CSUM */
12093diff -ruN linux/drivers/net/sk98lin/skdim.c linux-new/drivers/net/sk98lin/skdim.c
12094--- linux/drivers/net/sk98lin/skdim.c 2007-01-02 23:21:17.000000000 +0100
12095+++ linux-new/drivers/net/sk98lin/skdim.c 2006-10-13 10:18:35.000000000 +0200
12096@@ -1,17 +1,25 @@
12097 /******************************************************************************
12098 *
12099- * Name: skdim.c
12100- * Project: GEnesis, PCI Gigabit Ethernet Adapter
12101- * Version: $Revision$
12102- * Date: $Date$
12103- * Purpose: All functions to maintain interrupt moderation
12104+ * Name: skdim.c
12105+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
12106+ * Version: $Revision$
12107+ * Date: $Date$
12108+ * Purpose: All functions regardig interrupt moderation
12109 *
12110 ******************************************************************************/
12111
12112 /******************************************************************************
12113 *
12114 * (C)Copyright 1998-2002 SysKonnect GmbH.
12115- * (C)Copyright 2002-2003 Marvell.
12116+ * (C)Copyright 2002-2005 Marvell.
12117+ *
12118+ * Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet
12119+ * Server Adapters.
12120+ *
12121+ * Author: Ralph Roesler (rroesler@syskonnect.de)
12122+ * Mirko Lindner (mlindner@syskonnect.de)
12123+ *
12124+ * Address all question to: linux@syskonnect.de
12125 *
12126 * This program is free software; you can redistribute it and/or modify
12127 * it under the terms of the GNU General Public License as published by
12128@@ -20,723 +28,367 @@
12129 *
12130 * The information in this file is provided "AS IS" without warranty.
12131 *
12132- ******************************************************************************/
12133+ *****************************************************************************/
12134
12135-/******************************************************************************
12136- *
12137- * Description:
12138- *
12139- * This module is intended to manage the dynamic interrupt moderation on both
12140- * GEnesis and Yukon adapters.
12141- *
12142- * Include File Hierarchy:
12143- *
12144- * "skdrv1st.h"
12145- * "skdrv2nd.h"
12146- *
12147- ******************************************************************************/
12148-
12149-#ifndef lint
12150-static const char SysKonnectFileId[] =
12151- "@(#) $Id$ (C) SysKonnect.";
12152-#endif
12153-
12154-#define __SKADDR_C
12155-
12156-#ifdef __cplusplus
12157-#error C++ is not yet supported.
12158-extern "C" {
12159-#endif
12160-
12161-/*******************************************************************************
12162-**
12163-** Includes
12164-**
12165-*******************************************************************************/
12166-
12167-#ifndef __INC_SKDRV1ST_H
12168 #include "h/skdrv1st.h"
12169-#endif
12170-
12171-#ifndef __INC_SKDRV2ND_H
12172 #include "h/skdrv2nd.h"
12173-#endif
12174
12175-#include <linux/kernel_stat.h>
12176-
12177-/*******************************************************************************
12178-**
12179-** Defines
12180-**
12181-*******************************************************************************/
12182-
12183-/*******************************************************************************
12184-**
12185-** Typedefs
12186-**
12187-*******************************************************************************/
12188+/******************************************************************************
12189+ *
12190+ * Local Function Prototypes
12191+ *
12192+ *****************************************************************************/
12193
12194-/*******************************************************************************
12195-**
12196-** Local function prototypes
12197-**
12198-*******************************************************************************/
12199-
12200-static unsigned int GetCurrentSystemLoad(SK_AC *pAC);
12201-static SK_U64 GetIsrCalls(SK_AC *pAC);
12202-static SK_BOOL IsIntModEnabled(SK_AC *pAC);
12203-static void SetCurrIntCtr(SK_AC *pAC);
12204-static void EnableIntMod(SK_AC *pAC);
12205-static void DisableIntMod(SK_AC *pAC);
12206-static void ResizeDimTimerDuration(SK_AC *pAC);
12207-static void DisplaySelectedModerationType(SK_AC *pAC);
12208-static void DisplaySelectedModerationMask(SK_AC *pAC);
12209-static void DisplayDescrRatio(SK_AC *pAC);
12210+static SK_U64 getIsrCalls(SK_AC *pAC);
12211+static SK_BOOL isIntModEnabled(SK_AC *pAC);
12212+static void setCurrIntCtr(SK_AC *pAC);
12213+static void enableIntMod(SK_AC *pAC);
12214+static void disableIntMod(SK_AC *pAC);
12215
12216-/*******************************************************************************
12217-**
12218-** Global variables
12219-**
12220-*******************************************************************************/
12221+#define M_DIMINFO pAC->DynIrqModInfo
12222
12223-/*******************************************************************************
12224-**
12225-** Local variables
12226-**
12227-*******************************************************************************/
12228+/******************************************************************************
12229+ *
12230+ * Global Functions
12231+ *
12232+ *****************************************************************************/
12233
12234-/*******************************************************************************
12235-**
12236-** Global functions
12237-**
12238-*******************************************************************************/
12239+/*****************************************************************************
12240+ *
12241+ * SkDimModerate - Moderates the IRQs depending on the current needs
12242+ *
12243+ * Description:
12244+ * Moderation of IRQs depends on the number of occurred IRQs with
12245+ * respect to the previous moderation cycle.
12246+ *
12247+ * Returns: N/A
12248+ *
12249+ */
12250+void SkDimModerate(
12251+SK_AC *pAC) /* pointer to adapter control context */
12252+{
12253+ SK_U64 IsrCalls = getIsrCalls(pAC);
12254+
12255+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==> SkDimModerate\n"));
12256+
12257+ if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
12258+ if (isIntModEnabled(pAC)) {
12259+ if (IsrCalls < M_DIMINFO.MaxModIntsPerSecLowerLimit) {
12260+ disableIntMod(pAC);
12261+ }
12262+ } else {
12263+ if (IsrCalls > M_DIMINFO.MaxModIntsPerSecUpperLimit) {
12264+ enableIntMod(pAC);
12265+ }
12266+ }
12267+ }
12268+ setCurrIntCtr(pAC);
12269
12270-/*******************************************************************************
12271-** Function : SkDimModerate
12272-** Description : Called in every ISR to check if moderation is to be applied
12273-** or not for the current number of interrupts
12274-** Programmer : Ralph Roesler
12275-** Last Modified: 22-mar-03
12276-** Returns : void (!)
12277-** Notes : -
12278-*******************************************************************************/
12279-
12280-void
12281-SkDimModerate(SK_AC *pAC) {
12282- unsigned int CurrSysLoad = 0; /* expressed in percent */
12283- unsigned int LoadIncrease = 0; /* expressed in percent */
12284- SK_U64 ThresholdInts = 0;
12285- SK_U64 IsrCallsPerSec = 0;
12286+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("<== SkDimModerate\n"));
12287+}
12288
12289-#define M_DIMINFO pAC->DynIrqModInfo
12290+/*****************************************************************************
12291+ *
12292+ * SkDimStartModerationTimer - Starts the moderation timer
12293+ *
12294+ * Description:
12295+ * Dynamic interrupt moderation is regularly checked using the
12296+ * so-called moderation timer. This timer is started with this function.
12297+ *
12298+ * Returns: N/A
12299+ */
12300+void SkDimStartModerationTimer(
12301+SK_AC *pAC) /* pointer to adapter control context */
12302+{
12303+ SK_EVPARA EventParam; /* Event struct for timer event */
12304+
12305+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
12306+ ("==> SkDimStartModerationTimer\n"));
12307
12308- if (!IsIntModEnabled(pAC)) {
12309- if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
12310- CurrSysLoad = GetCurrentSystemLoad(pAC);
12311- if (CurrSysLoad > 75) {
12312- /*
12313- ** More than 75% total system load! Enable the moderation
12314- ** to shield the system against too many interrupts.
12315- */
12316- EnableIntMod(pAC);
12317- } else if (CurrSysLoad > M_DIMINFO.PrevSysLoad) {
12318- LoadIncrease = (CurrSysLoad - M_DIMINFO.PrevSysLoad);
12319- if (LoadIncrease > ((M_DIMINFO.PrevSysLoad *
12320- C_INT_MOD_ENABLE_PERCENTAGE) / 100)) {
12321- if (CurrSysLoad > 10) {
12322- /*
12323- ** More than 50% increase with respect to the
12324- ** previous load of the system. Most likely this
12325- ** is due to our ISR-proc...
12326- */
12327- EnableIntMod(pAC);
12328- }
12329- }
12330- } else {
12331- /*
12332- ** Neither too much system load at all nor too much increase
12333- ** with respect to the previous system load. Hence, we can leave
12334- ** the ISR-handling like it is without enabling moderation.
12335- */
12336- }
12337- M_DIMINFO.PrevSysLoad = CurrSysLoad;
12338- }
12339- } else {
12340- if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
12341- ThresholdInts = ((M_DIMINFO.MaxModIntsPerSec *
12342- C_INT_MOD_DISABLE_PERCENTAGE) / 100);
12343- IsrCallsPerSec = GetIsrCalls(pAC);
12344- if (IsrCallsPerSec <= ThresholdInts) {
12345- /*
12346- ** The number of interrupts within the last second is
12347- ** lower than the disable_percentage of the desried
12348- ** maxrate. Therefore we can disable the moderation.
12349- */
12350- DisableIntMod(pAC);
12351- M_DIMINFO.MaxModIntsPerSec =
12352- (M_DIMINFO.MaxModIntsPerSecUpperLimit +
12353- M_DIMINFO.MaxModIntsPerSecLowerLimit) / 2;
12354- } else {
12355- /*
12356- ** The number of interrupts per sec is the same as expected.
12357- ** Evalulate the descriptor-ratio. If it has changed, a resize
12358- ** in the moderation timer might be useful
12359- */
12360- if (M_DIMINFO.AutoSizing) {
12361- ResizeDimTimerDuration(pAC);
12362- }
12363- }
12364- }
12365- }
12366-
12367- /*
12368- ** Some information to the log...
12369- */
12370- if (M_DIMINFO.DisplayStats) {
12371- DisplaySelectedModerationType(pAC);
12372- DisplaySelectedModerationMask(pAC);
12373- DisplayDescrRatio(pAC);
12374- }
12375+ if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
12376+ SK_MEMSET((char *) &EventParam, 0, sizeof(EventParam));
12377+ EventParam.Para32[0] = SK_DRV_MODERATION_TIMER;
12378+ SkTimerStart(pAC, pAC->IoBase,
12379+ &pAC->DynIrqModInfo.ModTimer,
12380+ pAC->DynIrqModInfo.DynIrqModSampleInterval * 1000000,
12381+ SKGE_DRV, SK_DRV_TIMER, EventParam);
12382+ }
12383
12384- M_DIMINFO.NbrProcessedDescr = 0;
12385- SetCurrIntCtr(pAC);
12386+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
12387+ ("<== SkDimStartModerationTimer\n"));
12388 }
12389
12390-/*******************************************************************************
12391-** Function : SkDimStartModerationTimer
12392-** Description : Starts the audit-timer for the dynamic interrupt moderation
12393-** Programmer : Ralph Roesler
12394-** Last Modified: 22-mar-03
12395-** Returns : void (!)
12396-** Notes : -
12397-*******************************************************************************/
12398-
12399-void
12400-SkDimStartModerationTimer(SK_AC *pAC) {
12401- SK_EVPARA EventParam; /* Event struct for timer event */
12402-
12403- SK_MEMSET((char *) &EventParam, 0, sizeof(EventParam));
12404- EventParam.Para32[0] = SK_DRV_MODERATION_TIMER;
12405- SkTimerStart(pAC, pAC->IoBase, &pAC->DynIrqModInfo.ModTimer,
12406- SK_DRV_MODERATION_TIMER_LENGTH,
12407- SKGE_DRV, SK_DRV_TIMER, EventParam);
12408-}
12409+/*****************************************************************************
12410+ *
12411+ * SkDimEnableModerationIfNeeded - Enables or disables any moderationtype
12412+ *
12413+ * Description:
12414+ * This function effectively initializes the IRQ moderation of a network
12415+ * adapter. Depending on the configuration, this might be either static
12416+ * or dynamic. If no moderation is configured, this function will do
12417+ * nothing.
12418+ *
12419+ * Returns: N/A
12420+ */
12421+void SkDimEnableModerationIfNeeded(
12422+SK_AC *pAC) /* pointer to adapter control context */
12423+{
12424+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
12425+ ("==> SkDimEnableModerationIfNeeded\n"));
12426+
12427+ if (M_DIMINFO.IntModTypeSelect != C_INT_MOD_NONE) {
12428+ if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_STATIC) {
12429+ enableIntMod(pAC);
12430+ } else { /* must be C_INT_MOD_DYNAMIC */
12431+ SkDimStartModerationTimer(pAC);
12432+ }
12433+ }
12434
12435-/*******************************************************************************
12436-** Function : SkDimEnableModerationIfNeeded
12437-** Description : Either enables or disables moderation
12438-** Programmer : Ralph Roesler
12439-** Last Modified: 22-mar-03
12440-** Returns : void (!)
12441-** Notes : This function is called when a particular adapter is opened
12442-** There is no Disable function, because when all interrupts
12443-** might be disable, the moderation timer has no meaning at all
12444-******************************************************************************/
12445-
12446-void
12447-SkDimEnableModerationIfNeeded(SK_AC *pAC) {
12448-
12449- if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_STATIC) {
12450- EnableIntMod(pAC); /* notification print in this function */
12451- } else if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
12452- SkDimStartModerationTimer(pAC);
12453- if (M_DIMINFO.DisplayStats) {
12454- printk("Dynamic moderation has been enabled\n");
12455- }
12456- } else {
12457- if (M_DIMINFO.DisplayStats) {
12458- printk("No moderation has been enabled\n");
12459- }
12460- }
12461+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
12462+ ("<== SkDimEnableModerationIfNeeded\n"));
12463 }
12464
12465-/*******************************************************************************
12466-** Function : SkDimDisplayModerationSettings
12467-** Description : Displays the current settings regarding interrupt moderation
12468-** Programmer : Ralph Roesler
12469-** Last Modified: 22-mar-03
12470-** Returns : void (!)
12471-** Notes : -
12472-*******************************************************************************/
12473-
12474-void
12475-SkDimDisplayModerationSettings(SK_AC *pAC) {
12476- DisplaySelectedModerationType(pAC);
12477- DisplaySelectedModerationMask(pAC);
12478-}
12479+/*****************************************************************************
12480+ *
12481+ * SkDimDisableModeration - disables moderation if it is enabled
12482+ *
12483+ * Description:
12484+ * Disabling of the moderation requires that is enabled already.
12485+ *
12486+ * Returns: N/A
12487+ */
12488+void SkDimDisableModeration(
12489+SK_AC *pAC, /* pointer to adapter control context */
12490+int CurrentModeration) /* type of current moderation */
12491+{
12492+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
12493+ ("==> SkDimDisableModeration\n"));
12494+
12495+ if (M_DIMINFO.IntModTypeSelect != C_INT_MOD_NONE) {
12496+ if (CurrentModeration == C_INT_MOD_STATIC) {
12497+ disableIntMod(pAC);
12498+ } else { /* must be C_INT_MOD_DYNAMIC */
12499+ SkTimerStop(pAC, pAC->IoBase, &M_DIMINFO.ModTimer);
12500+ disableIntMod(pAC);
12501+ }
12502+ }
12503
12504-/*******************************************************************************
12505-**
12506-** Local functions
12507-**
12508-*******************************************************************************/
12509+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
12510+ ("<== SkDimDisableModeration\n"));
12511+}
12512
12513-/*******************************************************************************
12514-** Function : GetCurrentSystemLoad
12515-** Description : Retrieves the current system load of the system. This load
12516-** is evaluated for all processors within the system.
12517-** Programmer : Ralph Roesler
12518-** Last Modified: 22-mar-03
12519-** Returns : unsigned int: load expressed in percentage
12520-** Notes : The possible range being returned is from 0 up to 100.
12521-** Whereas 0 means 'no load at all' and 100 'system fully loaded'
12522-** It is impossible to determine what actually causes the system
12523-** to be in 100%, but maybe that is due to too much interrupts.
12524-*******************************************************************************/
12525-
12526-static unsigned int
12527-GetCurrentSystemLoad(SK_AC *pAC) {
12528- unsigned long jif = jiffies;
12529- unsigned int UserTime = 0;
12530- unsigned int SystemTime = 0;
12531- unsigned int NiceTime = 0;
12532- unsigned int IdleTime = 0;
12533- unsigned int TotalTime = 0;
12534- unsigned int UsedTime = 0;
12535- unsigned int SystemLoad = 0;
12536+/******************************************************************************
12537+ *
12538+ * Local Functions
12539+ *
12540+ *****************************************************************************/
12541
12542- /* unsigned int NbrCpu = 0; */
12543+/*****************************************************************************
12544+ *
12545+ * getIsrCalls - evaluate the number of IRQs handled in mod interval
12546+ *
12547+ * Description:
12548+ * Depending on the selected moderation mask, this function will return
12549+ * the number of interrupts handled in the previous moderation interval.
12550+ * This evaluated number is based on the current number of interrupts
12551+ * stored in PNMI-context and the previous stored interrupts.
12552+ *
12553+ * Returns:
12554+ * the number of IRQs handled
12555+ */
12556+static SK_U64 getIsrCalls(
12557+SK_AC *pAC) /* pointer to adapter control context */
12558+{
12559+ SK_U64 RxPort0IntDiff = 0, RxPort1IntDiff = 0;
12560+ SK_U64 TxPort0IntDiff = 0, TxPort1IntDiff = 0;
12561+ SK_U64 StatusPort0IntDiff = 0, StatusPort1IntDiff = 0;
12562+
12563+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==>getIsrCalls\n"));
12564+
12565+ if (!CHIP_ID_YUKON_2(pAC)) {
12566+ if ((M_DIMINFO.MaskIrqModeration == IRQ_MASK_TX_ONLY) ||
12567+ (M_DIMINFO.MaskIrqModeration == IRQ_MASK_SP_TX)) {
12568+ if (pAC->GIni.GIMacsFound == 2) {
12569+ TxPort1IntDiff =
12570+ pAC->Pnmi.Port[1].TxIntrCts -
12571+ M_DIMINFO.PrevPort1TxIntrCts;
12572+ }
12573+ TxPort0IntDiff = pAC->Pnmi.Port[0].TxIntrCts -
12574+ M_DIMINFO.PrevPort0TxIntrCts;
12575+ } else if ((M_DIMINFO.MaskIrqModeration == IRQ_MASK_RX_ONLY) ||
12576+ (M_DIMINFO.MaskIrqModeration == IRQ_MASK_SP_RX)) {
12577+ if (pAC->GIni.GIMacsFound == 2) {
12578+ RxPort1IntDiff =
12579+ pAC->Pnmi.Port[1].RxIntrCts -
12580+ M_DIMINFO.PrevPort1RxIntrCts;
12581+ }
12582+ RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts -
12583+ M_DIMINFO.PrevPort0RxIntrCts;
12584+ } else {
12585+ if (pAC->GIni.GIMacsFound == 2) {
12586+ RxPort1IntDiff =
12587+ pAC->Pnmi.Port[1].RxIntrCts -
12588+ M_DIMINFO.PrevPort1RxIntrCts;
12589+ TxPort1IntDiff =
12590+ pAC->Pnmi.Port[1].TxIntrCts -
12591+ M_DIMINFO.PrevPort1TxIntrCts;
12592+ }
12593+ RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts -
12594+ M_DIMINFO.PrevPort0RxIntrCts;
12595+ TxPort0IntDiff = pAC->Pnmi.Port[0].TxIntrCts -
12596+ M_DIMINFO.PrevPort0TxIntrCts;
12597+ }
12598+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
12599+ ("==>getIsrCalls (!CHIP_ID_YUKON_2)\n"));
12600+ return (RxPort0IntDiff + RxPort1IntDiff +
12601+ TxPort0IntDiff + TxPort1IntDiff);
12602+ }
12603
12604 /*
12605- ** The following lines have been commented out, because
12606- ** from kernel 2.5.44 onwards, the kernel-owned structure
12607- **
12608- ** struct kernel_stat kstat
12609- **
12610- ** is not marked as an exported symbol in the file
12611+ ** We have a Yukon2 compliant chipset if we come up to here
12612 **
12613- ** kernel/ksyms.c
12614- **
12615- ** As a consequence, using this driver as KLM is not possible
12616- ** and any access of the structure kernel_stat via the
12617- ** dedicated macros kstat_cpu(i).cpustat.xxx is to be avoided.
12618- **
12619- ** The kstat-information might be added again in future
12620- ** versions of the 2.5.xx kernel, but for the time being,
12621- ** number of interrupts will serve as indication how much
12622- ** load we currently have...
12623- **
12624- ** for (NbrCpu = 0; NbrCpu < num_online_cpus(); NbrCpu++) {
12625- ** UserTime = UserTime + kstat_cpu(NbrCpu).cpustat.user;
12626- ** NiceTime = NiceTime + kstat_cpu(NbrCpu).cpustat.nice;
12627- ** SystemTime = SystemTime + kstat_cpu(NbrCpu).cpustat.system;
12628- ** }
12629+ if (pAC->GIni.GIMacsFound == 2) {
12630+ StatusPort1IntDiff = pAC->Pnmi.Port[1].StatusLeIntrCts -
12631+ M_DIMINFO.PrevPort1StatusIntrCts;
12632+ }
12633+ StatusPort0IntDiff = pAC->Pnmi.Port[0].StatusLeIntrCts -
12634+ M_DIMINFO.PrevPort0StatusIntrCts;
12635 */
12636- SK_U64 ThresholdInts = 0;
12637- SK_U64 IsrCallsPerSec = 0;
12638-
12639- ThresholdInts = ((M_DIMINFO.MaxModIntsPerSec *
12640- C_INT_MOD_ENABLE_PERCENTAGE) + 100);
12641- IsrCallsPerSec = GetIsrCalls(pAC);
12642- if (IsrCallsPerSec >= ThresholdInts) {
12643- /*
12644- ** We do not know how much the real CPU-load is!
12645- ** Return 80% as a default in order to activate DIM
12646- */
12647- SystemLoad = 80;
12648- return (SystemLoad);
12649- }
12650-
12651- UsedTime = UserTime + NiceTime + SystemTime;
12652-
12653- IdleTime = jif * num_online_cpus() - UsedTime;
12654- TotalTime = UsedTime + IdleTime;
12655-
12656- SystemLoad = ( 100 * (UsedTime - M_DIMINFO.PrevUsedTime) ) /
12657- (TotalTime - M_DIMINFO.PrevTotalTime);
12658+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
12659+ ("==>getIsrCalls (CHIP_ID_YUKON_2)\n"));
12660+ return (StatusPort0IntDiff + StatusPort1IntDiff);
12661+}
12662
12663- if (M_DIMINFO.DisplayStats) {
12664- printk("Current system load is: %u\n", SystemLoad);
12665+/*****************************************************************************
12666+ *
12667+ * setCurrIntCtr - stores the current number of interrupts
12668+ *
12669+ * Description:
12670+ * Stores the current number of occurred interrupts in the adapter
12671+ * context. This is needed to evaluate the umber of interrupts within
12672+ * the moderation interval.
12673+ *
12674+ * Returns: N/A
12675+ *
12676+ */
12677+static void setCurrIntCtr(
12678+SK_AC *pAC) /* pointer to adapter control context */
12679+{
12680+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==>setCurrIntCtr\n"));
12681+
12682+ if (!CHIP_ID_YUKON_2(pAC)) {
12683+ if (pAC->GIni.GIMacsFound == 2) {
12684+ M_DIMINFO.PrevPort1RxIntrCts = pAC->Pnmi.Port[1].RxIntrCts;
12685+ M_DIMINFO.PrevPort1TxIntrCts = pAC->Pnmi.Port[1].TxIntrCts;
12686+ }
12687+ M_DIMINFO.PrevPort0RxIntrCts = pAC->Pnmi.Port[0].RxIntrCts;
12688+ M_DIMINFO.PrevPort0TxIntrCts = pAC->Pnmi.Port[0].TxIntrCts;
12689+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
12690+ ("<== setCurrIntCtr (!CHIP_ID_YUKON_2)\n"));
12691+ return;
12692 }
12693
12694- M_DIMINFO.PrevTotalTime = TotalTime;
12695- M_DIMINFO.PrevUsedTime = UsedTime;
12696-
12697- return (SystemLoad);
12698+ /*
12699+ ** We have a Yukon2 compliant chipset if we come up to here
12700+ **
12701+ if (pAC->GIni.GIMacsFound == 2) {
12702+ M_DIMINFO.PrevPort1StatusIntrCts = pAC->Pnmi.Port[1].StatusLeIntrCts;
12703+ }
12704+ M_DIMINFO.PrevPort0StatusIntrCts = pAC->Pnmi.Port[0].StatusLeIntrCts;
12705+ */
12706+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
12707+ ("<== setCurrIntCtr (CHIP_ID_YUKON_2)\n"));
12708 }
12709
12710-/*******************************************************************************
12711-** Function : GetIsrCalls
12712-** Description : Depending on the selected moderation mask, this function will
12713-** return the number of interrupts handled in the previous time-
12714-** frame. This evaluated number is based on the current number
12715-** of interrupts stored in PNMI-context and the previous stored
12716-** interrupts.
12717-** Programmer : Ralph Roesler
12718-** Last Modified: 23-mar-03
12719-** Returns : int: the number of interrupts being executed in the last
12720-** timeframe
12721-** Notes : It makes only sense to call this function, when dynamic
12722-** interrupt moderation is applied
12723-*******************************************************************************/
12724-
12725-static SK_U64
12726-GetIsrCalls(SK_AC *pAC) {
12727- SK_U64 RxPort0IntDiff = 0;
12728- SK_U64 RxPort1IntDiff = 0;
12729- SK_U64 TxPort0IntDiff = 0;
12730- SK_U64 TxPort1IntDiff = 0;
12731-
12732- if (pAC->DynIrqModInfo.MaskIrqModeration == IRQ_MASK_TX_ONLY) {
12733- if (pAC->GIni.GIMacsFound == 2) {
12734- TxPort1IntDiff = pAC->Pnmi.Port[1].TxIntrCts -
12735- pAC->DynIrqModInfo.PrevPort1TxIntrCts;
12736- }
12737- TxPort0IntDiff = pAC->Pnmi.Port[0].TxIntrCts -
12738- pAC->DynIrqModInfo.PrevPort0TxIntrCts;
12739- } else if (pAC->DynIrqModInfo.MaskIrqModeration == IRQ_MASK_RX_ONLY) {
12740- if (pAC->GIni.GIMacsFound == 2) {
12741- RxPort1IntDiff = pAC->Pnmi.Port[1].RxIntrCts -
12742- pAC->DynIrqModInfo.PrevPort1RxIntrCts;
12743- }
12744- RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts -
12745- pAC->DynIrqModInfo.PrevPort0RxIntrCts;
12746- } else {
12747- if (pAC->GIni.GIMacsFound == 2) {
12748- RxPort1IntDiff = pAC->Pnmi.Port[1].RxIntrCts -
12749- pAC->DynIrqModInfo.PrevPort1RxIntrCts;
12750- TxPort1IntDiff = pAC->Pnmi.Port[1].TxIntrCts -
12751- pAC->DynIrqModInfo.PrevPort1TxIntrCts;
12752- }
12753- RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts -
12754- pAC->DynIrqModInfo.PrevPort0RxIntrCts;
12755- TxPort0IntDiff = pAC->Pnmi.Port[0].TxIntrCts -
12756- pAC->DynIrqModInfo.PrevPort0TxIntrCts;
12757- }
12758-
12759- return (RxPort0IntDiff + RxPort1IntDiff + TxPort0IntDiff + TxPort1IntDiff);
12760+/*****************************************************************************
12761+ *
12762+ * isIntModEnabled - returns the current state of interrupt moderation
12763+ *
12764+ * Description:
12765+ * This function retrieves the current value of the interrupt moderation
12766+ * command register. Its content determines whether any moderation is
12767+ * running or not.
12768+ *
12769+ * Returns:
12770+ * SK_TRUE : IRQ moderation is currently active
12771+ * SK_FALSE: No IRQ moderation is active
12772+ */
12773+static SK_BOOL isIntModEnabled(
12774+SK_AC *pAC) /* pointer to adapter control context */
12775+{
12776+ unsigned long CtrCmd;
12777+
12778+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==>isIntModEnabled\n"));
12779+
12780+ SK_IN32(pAC->IoBase, B2_IRQM_CTRL, &CtrCmd);
12781+ if ((CtrCmd & TIM_START) == TIM_START) {
12782+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
12783+ ("<== isIntModEnabled (SK_TRUE)\n"));
12784+ return SK_TRUE;
12785+ }
12786+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
12787+ ("<== isIntModEnabled (SK_FALSE)\n"));
12788+ return SK_FALSE;
12789 }
12790
12791-/*******************************************************************************
12792-** Function : GetRxCalls
12793-** Description : This function will return the number of times a receive inter-
12794-** rupt was processed. This is needed to evaluate any resizing
12795-** factor.
12796-** Programmer : Ralph Roesler
12797-** Last Modified: 23-mar-03
12798-** Returns : SK_U64: the number of RX-ints being processed
12799-** Notes : It makes only sense to call this function, when dynamic
12800-** interrupt moderation is applied
12801-*******************************************************************************/
12802-
12803-static SK_U64
12804-GetRxCalls(SK_AC *pAC) {
12805- SK_U64 RxPort0IntDiff = 0;
12806- SK_U64 RxPort1IntDiff = 0;
12807-
12808- if (pAC->GIni.GIMacsFound == 2) {
12809- RxPort1IntDiff = pAC->Pnmi.Port[1].RxIntrCts -
12810- pAC->DynIrqModInfo.PrevPort1RxIntrCts;
12811- }
12812- RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts -
12813- pAC->DynIrqModInfo.PrevPort0RxIntrCts;
12814-
12815- return (RxPort0IntDiff + RxPort1IntDiff);
12816-}
12817+/*****************************************************************************
12818+ *
12819+ * enableIntMod - enables the interrupt moderation
12820+ *
12821+ * Description:
12822+ * Enabling the interrupt moderation is done by putting the desired
12823+ * moderation interval in the B2_IRQM_INI register, specifying the
12824+ * desired maks in the B2_IRQM_MSK register and finally starting the
12825+ * IRQ moderation timer using the B2_IRQM_CTRL register.
12826+ *
12827+ * Returns: N/A
12828+ *
12829+ */
12830+static void enableIntMod(
12831+SK_AC *pAC) /* pointer to adapter control context */
12832+{
12833+ unsigned long ModBase;
12834+
12835+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==> enableIntMod\n"));
12836+
12837+ if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
12838+ ModBase = C_CLK_FREQ_GENESIS / M_DIMINFO.MaxModIntsPerSec;
12839+ } else if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) {
12840+ ModBase = C_CLK_FREQ_YUKON_EC / M_DIMINFO.MaxModIntsPerSec;
12841+ } else {
12842+ ModBase = C_CLK_FREQ_YUKON / M_DIMINFO.MaxModIntsPerSec;
12843+ }
12844
12845-/*******************************************************************************
12846-** Function : SetCurrIntCtr
12847-** Description : Will store the current number orf occured interrupts in the
12848-** adapter context. This is needed to evaluated the number of
12849-** interrupts within a current timeframe.
12850-** Programmer : Ralph Roesler
12851-** Last Modified: 23-mar-03
12852-** Returns : void (!)
12853-** Notes : -
12854-*******************************************************************************/
12855-
12856-static void
12857-SetCurrIntCtr(SK_AC *pAC) {
12858- if (pAC->GIni.GIMacsFound == 2) {
12859- pAC->DynIrqModInfo.PrevPort1RxIntrCts = pAC->Pnmi.Port[1].RxIntrCts;
12860- pAC->DynIrqModInfo.PrevPort1TxIntrCts = pAC->Pnmi.Port[1].TxIntrCts;
12861- }
12862- pAC->DynIrqModInfo.PrevPort0RxIntrCts = pAC->Pnmi.Port[0].RxIntrCts;
12863- pAC->DynIrqModInfo.PrevPort0TxIntrCts = pAC->Pnmi.Port[0].TxIntrCts;
12864-}
12865+ SK_OUT32(pAC->IoBase, B2_IRQM_INI, ModBase);
12866+ SK_OUT32(pAC->IoBase, B2_IRQM_MSK, M_DIMINFO.MaskIrqModeration);
12867+ SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_START);
12868
12869-/*******************************************************************************
12870-** Function : IsIntModEnabled()
12871-** Description : Retrieves the current value of the interrupts moderation
12872-** command register. Its content determines whether any
12873-** moderation is running or not.
12874-** Programmer : Ralph Roesler
12875-** Last Modified: 23-mar-03
12876-** Returns : SK_TRUE : if mod timer running
12877-** SK_FALSE : if no moderation is being performed
12878-** Notes : -
12879-*******************************************************************************/
12880-
12881-static SK_BOOL
12882-IsIntModEnabled(SK_AC *pAC) {
12883- unsigned long CtrCmd;
12884-
12885- SK_IN32(pAC->IoBase, B2_IRQM_CTRL, &CtrCmd);
12886- if ((CtrCmd & TIM_START) == TIM_START) {
12887- return SK_TRUE;
12888- } else {
12889- return SK_FALSE;
12890- }
12891+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("<== enableIntMod\n"));
12892 }
12893
12894-/*******************************************************************************
12895-** Function : EnableIntMod()
12896-** Description : Enables the interrupt moderation using the values stored in
12897-** in the pAC->DynIntMod data structure
12898-** Programmer : Ralph Roesler
12899-** Last Modified: 22-mar-03
12900-** Returns : -
12901-** Notes : -
12902-*******************************************************************************/
12903-
12904-static void
12905-EnableIntMod(SK_AC *pAC) {
12906- unsigned long ModBase;
12907-
12908- if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
12909- ModBase = C_CLK_FREQ_GENESIS / pAC->DynIrqModInfo.MaxModIntsPerSec;
12910- } else {
12911- ModBase = C_CLK_FREQ_YUKON / pAC->DynIrqModInfo.MaxModIntsPerSec;
12912- }
12913-
12914- SK_OUT32(pAC->IoBase, B2_IRQM_INI, ModBase);
12915- SK_OUT32(pAC->IoBase, B2_IRQM_MSK, pAC->DynIrqModInfo.MaskIrqModeration);
12916- SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_START);
12917- if (M_DIMINFO.DisplayStats) {
12918- printk("Enabled interrupt moderation (%i ints/sec)\n",
12919- M_DIMINFO.MaxModIntsPerSec);
12920- }
12921-}
12922+/*****************************************************************************
12923+ *
12924+ * disableIntMod - disables the interrupt moderation
12925+ *
12926+ * Description:
12927+ * Disabling the interrupt moderation is done by stopping the
12928+ * IRQ moderation timer using the B2_IRQM_CTRL register.
12929+ *
12930+ * Returns: N/A
12931+ *
12932+ */
12933+static void disableIntMod(
12934+SK_AC *pAC) /* pointer to adapter control context */
12935+{
12936+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==> disableIntMod\n"));
12937
12938-/*******************************************************************************
12939-** Function : DisableIntMod()
12940-** Description : Disables the interrupt moderation independent of what inter-
12941-** rupts are running or not
12942-** Programmer : Ralph Roesler
12943-** Last Modified: 23-mar-03
12944-** Returns : -
12945-** Notes : -
12946-*******************************************************************************/
12947-
12948-static void
12949-DisableIntMod(SK_AC *pAC) {
12950-
12951- SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_STOP);
12952- if (M_DIMINFO.DisplayStats) {
12953- printk("Disabled interrupt moderation\n");
12954- }
12955-}
12956+ SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_STOP);
12957
12958-/*******************************************************************************
12959-** Function : ResizeDimTimerDuration();
12960-** Description : Checks the current used descriptor ratio and resizes the
12961-** duration timer (longer/smaller) if possible.
12962-** Programmer : Ralph Roesler
12963-** Last Modified: 23-mar-03
12964-** Returns : -
12965-** Notes : There are both maximum and minimum timer duration value.
12966-** This function assumes that interrupt moderation is already
12967-** enabled!
12968-*******************************************************************************/
12969-
12970-static void
12971-ResizeDimTimerDuration(SK_AC *pAC) {
12972- SK_BOOL IncreaseTimerDuration;
12973- int TotalMaxNbrDescr;
12974- int UsedDescrRatio;
12975- int RatioDiffAbs;
12976- int RatioDiffRel;
12977- int NewMaxModIntsPerSec;
12978- int ModAdjValue;
12979- long ModBase;
12980-
12981- /*
12982- ** Check first if we are allowed to perform any modification
12983- */
12984- if (IsIntModEnabled(pAC)) {
12985- if (M_DIMINFO.IntModTypeSelect != C_INT_MOD_DYNAMIC) {
12986- return;
12987- } else {
12988- if (M_DIMINFO.ModJustEnabled) {
12989- M_DIMINFO.ModJustEnabled = SK_FALSE;
12990- return;
12991- }
12992- }
12993- }
12994-
12995- /*
12996- ** If we got until here, we have to evaluate the amount of the
12997- ** descriptor ratio change...
12998- */
12999- TotalMaxNbrDescr = pAC->RxDescrPerRing * GetRxCalls(pAC);
13000- UsedDescrRatio = (M_DIMINFO.NbrProcessedDescr * 100) / TotalMaxNbrDescr;
13001-
13002- if (UsedDescrRatio > M_DIMINFO.PrevUsedDescrRatio) {
13003- RatioDiffAbs = (UsedDescrRatio - M_DIMINFO.PrevUsedDescrRatio);
13004- RatioDiffRel = (RatioDiffAbs * 100) / UsedDescrRatio;
13005- M_DIMINFO.PrevUsedDescrRatio = UsedDescrRatio;
13006- IncreaseTimerDuration = SK_FALSE; /* in other words: DECREASE */
13007- } else if (UsedDescrRatio < M_DIMINFO.PrevUsedDescrRatio) {
13008- RatioDiffAbs = (M_DIMINFO.PrevUsedDescrRatio - UsedDescrRatio);
13009- RatioDiffRel = (RatioDiffAbs * 100) / M_DIMINFO.PrevUsedDescrRatio;
13010- M_DIMINFO.PrevUsedDescrRatio = UsedDescrRatio;
13011- IncreaseTimerDuration = SK_TRUE; /* in other words: INCREASE */
13012- } else {
13013- RatioDiffAbs = (M_DIMINFO.PrevUsedDescrRatio - UsedDescrRatio);
13014- RatioDiffRel = (RatioDiffAbs * 100) / M_DIMINFO.PrevUsedDescrRatio;
13015- M_DIMINFO.PrevUsedDescrRatio = UsedDescrRatio;
13016- IncreaseTimerDuration = SK_TRUE; /* in other words: INCREASE */
13017- }
13018-
13019- /*
13020- ** Now we can determine the change in percent
13021- */
13022- if ((RatioDiffRel >= 0) && (RatioDiffRel <= 5) ) {
13023- ModAdjValue = 1; /* 1% change - maybe some other value in future */
13024- } else if ((RatioDiffRel > 5) && (RatioDiffRel <= 10) ) {
13025- ModAdjValue = 1; /* 1% change - maybe some other value in future */
13026- } else if ((RatioDiffRel > 10) && (RatioDiffRel <= 15) ) {
13027- ModAdjValue = 1; /* 1% change - maybe some other value in future */
13028- } else {
13029- ModAdjValue = 1; /* 1% change - maybe some other value in future */
13030- }
13031-
13032- if (IncreaseTimerDuration) {
13033- NewMaxModIntsPerSec = M_DIMINFO.MaxModIntsPerSec +
13034- (M_DIMINFO.MaxModIntsPerSec * ModAdjValue) / 100;
13035- } else {
13036- NewMaxModIntsPerSec = M_DIMINFO.MaxModIntsPerSec -
13037- (M_DIMINFO.MaxModIntsPerSec * ModAdjValue) / 100;
13038- }
13039-
13040- /*
13041- ** Check if we exceed boundaries...
13042- */
13043- if ( (NewMaxModIntsPerSec > M_DIMINFO.MaxModIntsPerSecUpperLimit) ||
13044- (NewMaxModIntsPerSec < M_DIMINFO.MaxModIntsPerSecLowerLimit)) {
13045- if (M_DIMINFO.DisplayStats) {
13046- printk("Cannot change ModTim from %i to %i ints/sec\n",
13047- M_DIMINFO.MaxModIntsPerSec, NewMaxModIntsPerSec);
13048- }
13049- return;
13050- } else {
13051- if (M_DIMINFO.DisplayStats) {
13052- printk("Resized ModTim from %i to %i ints/sec\n",
13053- M_DIMINFO.MaxModIntsPerSec, NewMaxModIntsPerSec);
13054- }
13055- }
13056-
13057- M_DIMINFO.MaxModIntsPerSec = NewMaxModIntsPerSec;
13058-
13059- if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
13060- ModBase = C_CLK_FREQ_GENESIS / pAC->DynIrqModInfo.MaxModIntsPerSec;
13061- } else {
13062- ModBase = C_CLK_FREQ_YUKON / pAC->DynIrqModInfo.MaxModIntsPerSec;
13063- }
13064-
13065- /*
13066- ** We do not need to touch any other registers
13067- */
13068- SK_OUT32(pAC->IoBase, B2_IRQM_INI, ModBase);
13069+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("<== disableIntMod\n"));
13070 }
13071
13072 /*******************************************************************************
13073-** Function : DisplaySelectedModerationType()
13074-** Description : Displays what type of moderation we have
13075-** Programmer : Ralph Roesler
13076-** Last Modified: 23-mar-03
13077-** Returns : void!
13078-** Notes : -
13079-*******************************************************************************/
13080-
13081-static void
13082-DisplaySelectedModerationType(SK_AC *pAC) {
13083-
13084- if (pAC->DynIrqModInfo.DisplayStats) {
13085- if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_STATIC) {
13086- printk("Static int moderation runs with %i INTS/sec\n",
13087- pAC->DynIrqModInfo.MaxModIntsPerSec);
13088- } else if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
13089- if (IsIntModEnabled(pAC)) {
13090- printk("Dynamic int moderation runs with %i INTS/sec\n",
13091- pAC->DynIrqModInfo.MaxModIntsPerSec);
13092- } else {
13093- printk("Dynamic int moderation currently not applied\n");
13094- }
13095- } else {
13096- printk("No interrupt moderation selected!\n");
13097- }
13098- }
13099-}
13100-
13101-/*******************************************************************************
13102-** Function : DisplaySelectedModerationMask()
13103-** Description : Displays what interrupts are moderated
13104-** Programmer : Ralph Roesler
13105-** Last Modified: 23-mar-03
13106-** Returns : void!
13107-** Notes : -
13108-*******************************************************************************/
13109-
13110-static void
13111-DisplaySelectedModerationMask(SK_AC *pAC) {
13112-
13113- if (pAC->DynIrqModInfo.DisplayStats) {
13114- if (pAC->DynIrqModInfo.IntModTypeSelect != C_INT_MOD_NONE) {
13115- switch (pAC->DynIrqModInfo.MaskIrqModeration) {
13116- case IRQ_MASK_TX_ONLY:
13117- printk("Only Tx-interrupts are moderated\n");
13118- break;
13119- case IRQ_MASK_RX_ONLY:
13120- printk("Only Rx-interrupts are moderated\n");
13121- break;
13122- case IRQ_MASK_SP_ONLY:
13123- printk("Only special-interrupts are moderated\n");
13124- break;
13125- case IRQ_MASK_TX_RX:
13126- printk("Tx- and Rx-interrupts are moderated\n");
13127- break;
13128- case IRQ_MASK_SP_RX:
13129- printk("Special- and Rx-interrupts are moderated\n");
13130- break;
13131- case IRQ_MASK_SP_TX:
13132- printk("Special- and Tx-interrupts are moderated\n");
13133- break;
13134- case IRQ_MASK_RX_TX_SP:
13135- printk("All Rx-, Tx and special-interrupts are moderated\n");
13136- break;
13137- default:
13138- printk("Don't know what is moderated\n");
13139- break;
13140- }
13141- } else {
13142- printk("No specific interrupts masked for moderation\n");
13143- }
13144- }
13145-}
13146-
13147-/*******************************************************************************
13148-** Function : DisplayDescrRatio
13149-** Description : Like the name states...
13150-** Programmer : Ralph Roesler
13151-** Last Modified: 23-mar-03
13152-** Returns : void!
13153-** Notes : -
13154-*******************************************************************************/
13155-
13156-static void
13157-DisplayDescrRatio(SK_AC *pAC) {
13158- int TotalMaxNbrDescr = 0;
13159-
13160- if (pAC->DynIrqModInfo.DisplayStats) {
13161- TotalMaxNbrDescr = pAC->RxDescrPerRing * GetRxCalls(pAC);
13162- printk("Ratio descriptors: %i/%i\n",
13163- M_DIMINFO.NbrProcessedDescr, TotalMaxNbrDescr);
13164- }
13165-}
13166-
13167-/*******************************************************************************
13168-**
13169-** End of file
13170-**
13171-*******************************************************************************/
13172+ *
13173+ * End of file
13174+ *
13175+ ******************************************************************************/
13176diff -ruN linux/drivers/net/sk98lin/skethtool.c linux-new/drivers/net/sk98lin/skethtool.c
13177--- linux/drivers/net/sk98lin/skethtool.c 2007-01-02 23:21:17.000000000 +0100
13178+++ linux-new/drivers/net/sk98lin/skethtool.c 2006-10-13 11:18:50.000000000 +0200
13179@@ -2,8 +2,8 @@
13180 *
13181 * Name: skethtool.c
13182 * Project: GEnesis, PCI Gigabit Ethernet Adapter
13183- * Version: $Revision$
13184- * Date: $Date$
13185+ * Version: $Revision$
13186+ * Date: $Date$
13187 * Purpose: All functions regarding ethtool handling
13188 *
13189 ******************************************************************************/
13190@@ -11,7 +11,7 @@
13191 /******************************************************************************
13192 *
13193 * (C)Copyright 1998-2002 SysKonnect GmbH.
13194- * (C)Copyright 2002-2004 Marvell.
13195+ * (C)Copyright 2002-2005 Marvell.
13196 *
13197 * Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet
13198 * Server Adapters.
13199@@ -21,9 +21,6 @@
13200 *
13201 * Address all question to: linux@syskonnect.de
13202 *
13203- * The technical manual for the adapters is available from SysKonnect's
13204- * web pages: www.syskonnect.com
13205- *
13206 * This program is free software; you can redistribute it and/or modify
13207 * it under the terms of the GNU General Public License as published by
13208 * the Free Software Foundation; either version 2 of the License, or
13209@@ -36,10 +33,25 @@
13210 #include "h/skdrv1st.h"
13211 #include "h/skdrv2nd.h"
13212 #include "h/skversion.h"
13213-
13214 #include <linux/ethtool.h>
13215+#include <linux/module.h>
13216 #include <linux/timer.h>
13217-#include <linux/delay.h>
13218+
13219+/******************************************************************************
13220+ *
13221+ * Local Functions
13222+ *
13223+ *****************************************************************************/
13224+static void toggleLeds(unsigned long ptr);
13225+
13226+/******************************************************************************
13227+ *
13228+ * External Functions and Data
13229+ *
13230+ *****************************************************************************/
13231+
13232+extern void SkDimDisableModeration(SK_AC *pAC, int CurrentModeration);
13233+extern void SkDimEnableModerationIfNeeded(SK_AC *pAC);
13234
13235 /******************************************************************************
13236 *
13237@@ -47,6 +59,12 @@
13238 *
13239 *****************************************************************************/
13240
13241+#ifndef ETHT_STATSTRING_LEN
13242+#define ETHT_STATSTRING_LEN 32
13243+#endif
13244+
13245+#define SK98LIN_STAT(m) sizeof(((SK_AC *)0)->m),offsetof(SK_AC, m)
13246+
13247 #define SUPP_COPPER_ALL (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
13248 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
13249 SUPPORTED_1000baseT_Half| SUPPORTED_1000baseT_Full| \
13250@@ -65,59 +83,137 @@
13251 ADVERTISED_FIBRE | \
13252 ADVERTISED_Autoneg)
13253
13254+struct sk98lin_stats {
13255+ char stat_string[ETHT_STATSTRING_LEN];
13256+ int sizeof_stat;
13257+ int stat_offset;
13258+};
13259+
13260+static struct sk98lin_stats sk98lin_etht_stats_port0[] = {
13261+ { "rx_packets" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxOkCts) },
13262+ { "tx_packets" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxOkCts) },
13263+ { "rx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxOctetsOkCts) },
13264+ { "tx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxOctetsOkCts) },
13265+ { "rx_errors" , SK98LIN_STAT(PnmiStruct.InErrorsCts) },
13266+ { "tx_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxSingleCollisionCts) },
13267+ { "rx_dropped" , SK98LIN_STAT(PnmiStruct.RxNoBufCts) },
13268+ { "tx_dropped" , SK98LIN_STAT(PnmiStruct.TxNoBufCts) },
13269+ { "multicasts" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxMulticastOkCts) },
13270+ { "collisions" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxSingleCollisionCts) },
13271+ { "rx_length_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxRuntCts) },
13272+ { "rx_buffer_overflow_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxFifoOverflowCts) },
13273+ { "rx_crc_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxFcsCts) },
13274+ { "rx_frame_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxFramingCts) },
13275+ { "rx_too_short_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxShortsCts) },
13276+ { "rx_too_long_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxTooLongCts) },
13277+ { "rx_carrier_extension_errors", SK98LIN_STAT(PnmiStruct.Stat[0].StatRxCextCts) },
13278+ { "rx_symbol_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxSymbolCts) },
13279+ { "rx_llc_mac_size_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxIRLengthCts) },
13280+ { "rx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxCarrierCts) },
13281+ { "rx_jabber_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxJabberCts) },
13282+ { "rx_missed_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxMissedCts) },
13283+ { "tx_abort_collision_errors" , SK98LIN_STAT(stats.tx_aborted_errors) },
13284+ { "tx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxCarrierCts) },
13285+ { "tx_buffer_underrun_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxFifoUnderrunCts) },
13286+ { "tx_heartbeat_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxCarrierCts) } ,
13287+ { "tx_window_errors" , SK98LIN_STAT(stats.tx_window_errors) }
13288+};
13289+
13290+static struct sk98lin_stats sk98lin_etht_stats_port1[] = {
13291+ { "rx_packets" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxOkCts) },
13292+ { "tx_packets" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxOkCts) },
13293+ { "rx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxOctetsOkCts) },
13294+ { "tx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxOctetsOkCts) },
13295+ { "rx_errors" , SK98LIN_STAT(PnmiStruct.InErrorsCts) },
13296+ { "tx_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxSingleCollisionCts) },
13297+ { "rx_dropped" , SK98LIN_STAT(PnmiStruct.RxNoBufCts) },
13298+ { "tx_dropped" , SK98LIN_STAT(PnmiStruct.TxNoBufCts) },
13299+ { "multicasts" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxMulticastOkCts) },
13300+ { "collisions" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxSingleCollisionCts) },
13301+ { "rx_length_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxRuntCts) },
13302+ { "rx_buffer_overflow_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxFifoOverflowCts) },
13303+ { "rx_crc_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxFcsCts) },
13304+ { "rx_frame_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxFramingCts) },
13305+ { "rx_too_short_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxShortsCts) },
13306+ { "rx_too_long_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxTooLongCts) },
13307+ { "rx_carrier_extension_errors", SK98LIN_STAT(PnmiStruct.Stat[1].StatRxCextCts) },
13308+ { "rx_symbol_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxSymbolCts) },
13309+ { "rx_llc_mac_size_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxIRLengthCts) },
13310+ { "rx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxCarrierCts) },
13311+ { "rx_jabber_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxJabberCts) },
13312+ { "rx_missed_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxMissedCts) },
13313+ { "tx_abort_collision_errors" , SK98LIN_STAT(stats.tx_aborted_errors) },
13314+ { "tx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxCarrierCts) },
13315+ { "tx_buffer_underrun_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxFifoUnderrunCts) },
13316+ { "tx_heartbeat_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxCarrierCts) } ,
13317+ { "tx_window_errors" , SK98LIN_STAT(stats.tx_window_errors) }
13318+};
13319+
13320+static int DuplexAutoNegConfMap[9][3]= {
13321+ { -1 , -1 , -1 },
13322+ { 0 , -1 , -1 },
13323+ { SK_LMODE_HALF , DUPLEX_HALF, AUTONEG_DISABLE },
13324+ { SK_LMODE_FULL , DUPLEX_FULL, AUTONEG_DISABLE },
13325+ { SK_LMODE_AUTOHALF , DUPLEX_HALF, AUTONEG_ENABLE },
13326+ { SK_LMODE_AUTOFULL , DUPLEX_FULL, AUTONEG_ENABLE },
13327+ { SK_LMODE_AUTOBOTH , DUPLEX_FULL, AUTONEG_ENABLE },
13328+ { SK_LMODE_AUTOSENSE , -1 , -1 },
13329+ { SK_LMODE_INDETERMINATED, -1 , -1 }
13330+};
13331+
13332+static int SpeedConfMap[6][2] = {
13333+ { 0 , -1 },
13334+ { SK_LSPEED_AUTO , -1 },
13335+ { SK_LSPEED_10MBPS , SPEED_10 },
13336+ { SK_LSPEED_100MBPS , SPEED_100 },
13337+ { SK_LSPEED_1000MBPS , SPEED_1000 },
13338+ { SK_LSPEED_INDETERMINATED, -1 }
13339+};
13340+
13341+static int AdvSpeedMap[6][2] = {
13342+ { 0 , -1 },
13343+ { SK_LSPEED_AUTO , -1 },
13344+ { SK_LSPEED_10MBPS , ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full },
13345+ { SK_LSPEED_100MBPS , ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full },
13346+ { SK_LSPEED_1000MBPS , ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full},
13347+ { SK_LSPEED_INDETERMINATED, -1 }
13348+};
13349+
13350+#define SK98LIN_STATS_LEN sizeof(sk98lin_etht_stats_port0) / sizeof(struct sk98lin_stats)
13351+
13352+static int nbrBlinkQuarterSeconds;
13353+static int currentPortIndex;
13354+static SK_BOOL isLocateNICrunning = SK_FALSE;
13355+static SK_BOOL isDualNetCard = SK_FALSE;
13356+static SK_BOOL doSwitchLEDsOn = SK_FALSE;
13357+static SK_BOOL boardWasDown[2] = { SK_FALSE, SK_FALSE };
13358+static struct timer_list locateNICtimer;
13359
13360 /******************************************************************************
13361 *
13362- * Local Functions
13363+ * Ethtool Functions
13364 *
13365 *****************************************************************************/
13366
13367 /*****************************************************************************
13368 *
13369- * getSettings - retrieves the current settings of the selected adapter
13370+ * SkGeGetSettings - retrieves the current settings of the selected adapter
13371 *
13372 * Description:
13373 * The current configuration of the selected adapter is returned.
13374 * This configuration involves a)speed, b)duplex and c)autoneg plus
13375 * a number of other variables.
13376 *
13377- * Returns: always 0
13378+ * Returns: N/A
13379 *
13380 */
13381-static int getSettings(struct net_device *dev, struct ethtool_cmd *ecmd)
13382+int SkGeGetSettings(struct net_device *dev,
13383+ struct ethtool_cmd *ecmd)
13384 {
13385- const DEV_NET *pNet = netdev_priv(dev);
13386- int port = pNet->PortNr;
13387- const SK_AC *pAC = pNet->pAC;
13388- const SK_GEPORT *pPort = &pAC->GIni.GP[port];
13389-
13390- static int DuplexAutoNegConfMap[9][3]= {
13391- { -1 , -1 , -1 },
13392- { 0 , -1 , -1 },
13393- { SK_LMODE_HALF , DUPLEX_HALF, AUTONEG_DISABLE },
13394- { SK_LMODE_FULL , DUPLEX_FULL, AUTONEG_DISABLE },
13395- { SK_LMODE_AUTOHALF , DUPLEX_HALF, AUTONEG_ENABLE },
13396- { SK_LMODE_AUTOFULL , DUPLEX_FULL, AUTONEG_ENABLE },
13397- { SK_LMODE_AUTOBOTH , DUPLEX_FULL, AUTONEG_ENABLE },
13398- { SK_LMODE_AUTOSENSE , -1 , -1 },
13399- { SK_LMODE_INDETERMINATED, -1 , -1 }
13400- };
13401- static int SpeedConfMap[6][2] = {
13402- { 0 , -1 },
13403- { SK_LSPEED_AUTO , -1 },
13404- { SK_LSPEED_10MBPS , SPEED_10 },
13405- { SK_LSPEED_100MBPS , SPEED_100 },
13406- { SK_LSPEED_1000MBPS , SPEED_1000 },
13407- { SK_LSPEED_INDETERMINATED, -1 }
13408- };
13409- static int AdvSpeedMap[6][2] = {
13410- { 0 , -1 },
13411- { SK_LSPEED_AUTO , -1 },
13412- { SK_LSPEED_10MBPS , ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full },
13413- { SK_LSPEED_100MBPS , ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full },
13414- { SK_LSPEED_1000MBPS , ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full},
13415- { SK_LSPEED_INDETERMINATED, -1 }
13416- };
13417+ DEV_NET *pNet = (DEV_NET*) dev->priv;
13418+ SK_AC *pAC = pNet->pAC;
13419+ int port = pNet->PortNr;
13420+ SK_GEPORT *pPort = &pAC->GIni.GP[port];
13421
13422 ecmd->phy_address = port;
13423 ecmd->speed = SpeedConfMap[pPort->PLinkSpeedUsed][1];
13424@@ -137,12 +233,10 @@
13425 if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {
13426 ecmd->supported &= ~(SUPPORTED_1000baseT_Half);
13427 }
13428-#ifdef CHIP_ID_YUKON_FE
13429 if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) {
13430 ecmd->supported &= ~(SUPPORTED_1000baseT_Half);
13431 ecmd->supported &= ~(SUPPORTED_1000baseT_Full);
13432 }
13433-#endif
13434 }
13435 if (pAC->GIni.GP[0].PLinkSpeed != SK_LSPEED_AUTO) {
13436 ecmd->advertising = AdvSpeedMap[pPort->PLinkSpeed][1];
13437@@ -152,324 +246,416 @@
13438 } else {
13439 ecmd->advertising = ecmd->supported;
13440 }
13441-
13442- if (ecmd->autoneg == AUTONEG_ENABLE)
13443+ if (ecmd->autoneg == AUTONEG_ENABLE) {
13444 ecmd->advertising |= ADVERTISED_Autoneg;
13445+ } else {
13446+ ecmd->advertising = ADVERTISED_TP;
13447+ }
13448 } else {
13449 ecmd->port = PORT_FIBRE;
13450- ecmd->supported = SUPP_FIBRE_ALL;
13451- ecmd->advertising = ADV_FIBRE_ALL;
13452+ ecmd->supported = (SUPP_FIBRE_ALL);
13453+ ecmd->advertising = (ADV_FIBRE_ALL);
13454 }
13455- return 0;
13456+ return(0);
13457 }
13458
13459-/*
13460- * MIB infrastructure uses instance value starting at 1
13461- * based on board and port.
13462+
13463+
13464+/*****************************************************************************
13465+ *
13466+ * SkGeGetDrvInfo - returns generic driver and adapter information
13467+ *
13468+ * Description:
13469+ * Generic driver information is returned via this function, such as
13470+ * the name of the driver, its version and and firmware version.
13471+ * In addition to this, the location of the selected adapter is
13472+ * returned as a bus info string (e.g. '01:05.0').
13473+ *
13474+ * Returns: N/A
13475+ *
13476 */
13477-static inline u32 pnmiInstance(const DEV_NET *pNet)
13478+void SkGeGetDrvInfo(struct net_device *dev,
13479+ struct ethtool_drvinfo *ecmd)
13480 {
13481- return 1 + (pNet->pAC->RlmtNets == 2) + pNet->PortNr;
13482+ DEV_NET *pNet = (DEV_NET*) dev->priv;
13483+ SK_AC *pAC = pNet->pAC;
13484+ char versionString[32];
13485+
13486+ snprintf(versionString, 32, "%s (%s)", VER_STRING, PATCHLEVEL);
13487+ strncpy(ecmd->driver, DRIVER_FILE_NAME , 32);
13488+ strncpy(ecmd->version, versionString , 32);
13489+ strncpy(ecmd->fw_version, "N/A", 32);
13490+ strncpy(ecmd->bus_info, pci_name(pAC->PciDev), 32);
13491+
13492+ ecmd->n_stats = SK98LIN_STATS_LEN;
13493 }
13494
13495 /*****************************************************************************
13496 *
13497- * setSettings - configures the settings of a selected adapter
13498+ * SkGeGetWolSettings - retrieves the WOL settings of the
13499+ * selected adapter
13500 *
13501 * Description:
13502- * Possible settings that may be altered are a)speed, b)duplex or
13503- * c)autonegotiation.
13504+ * All current WOL settings of a selected adapter are placed in the
13505+ * passed ethtool_wolinfo structure and are returned to the caller.
13506+ *
13507+ * Returns: N/A
13508 *
13509- * Returns:
13510- * 0: everything fine, no error
13511- * <0: the return value is the error code of the failure
13512 */
13513-static int setSettings(struct net_device *dev, struct ethtool_cmd *ecmd)
13514+void SkGeGetWolSettings(struct net_device *dev,
13515+ struct ethtool_wolinfo *ecmd)
13516 {
13517- DEV_NET *pNet = netdev_priv(dev);
13518- SK_AC *pAC = pNet->pAC;
13519- u32 instance;
13520- char buf[4];
13521- int len = 1;
13522+ DEV_NET *pNet = (DEV_NET*) dev->priv;
13523+ SK_AC *pAC = pNet->pAC;
13524
13525- if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100
13526- && ecmd->speed != SPEED_1000)
13527- return -EINVAL;
13528+ ecmd->supported = pAC->WolInfo.SupportedWolOptions;
13529+ ecmd->wolopts = pAC->WolInfo.ConfiguredWolOptions;
13530+}
13531
13532- if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
13533- return -EINVAL;
13534+/*****************************************************************************
13535+ *
13536+ * SkGeGetPauseParam - retrieves the pause parameters
13537+ *
13538+ * Description:
13539+ * All current pause parameters of a selected adapter are placed
13540+ * in the passed ethtool_pauseparam structure and are returned.
13541+ *
13542+ * Returns: N/A
13543+ *
13544+ */
13545+void SkGeGetPauseParam(struct net_device *dev,
13546+ struct ethtool_pauseparam *ecmd)
13547+{
13548+ DEV_NET *pNet = (DEV_NET*) dev->priv;
13549+ SK_AC *pAC = pNet->pAC;
13550+ int port = pNet->PortNr;
13551+ SK_GEPORT *pPort = &pAC->GIni.GP[port];
13552+
13553+ /* Get the pause parameters */
13554+ ecmd->rx_pause = 0;
13555+ ecmd->tx_pause = 0;
13556+
13557+ if (pPort->PFlowCtrlMode == SK_FLOW_MODE_LOC_SEND) {
13558+ ecmd->tx_pause = 1;
13559+ }
13560+ if ((pPort->PFlowCtrlMode == SK_FLOW_MODE_SYMMETRIC) ||
13561+ (pPort->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM)) {
13562+ ecmd->tx_pause = 1;
13563+ ecmd->rx_pause = 1;
13564+ }
13565
13566- if (ecmd->autoneg != AUTONEG_DISABLE && ecmd->autoneg != AUTONEG_ENABLE)
13567- return -EINVAL;
13568+ if ((ecmd->rx_pause == 0) && (ecmd->tx_pause == 0)) {
13569+ ecmd->autoneg = SK_FALSE;
13570+ } else {
13571+ ecmd->autoneg = SK_TRUE;
13572+ }
13573+}
13574
13575- if (ecmd->autoneg == AUTONEG_DISABLE)
13576- *buf = (ecmd->duplex == DUPLEX_FULL)
13577- ? SK_LMODE_FULL : SK_LMODE_HALF;
13578- else
13579- *buf = (ecmd->duplex == DUPLEX_FULL)
13580- ? SK_LMODE_AUTOFULL : SK_LMODE_AUTOHALF;
13581-
13582- instance = pnmiInstance(pNet);
13583- if (SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_LINK_MODE,
13584- &buf, &len, instance, pNet->NetNr) != SK_PNMI_ERR_OK)
13585- return -EINVAL;
13586
13587- switch(ecmd->speed) {
13588- case SPEED_1000:
13589- *buf = SK_LSPEED_1000MBPS;
13590- break;
13591- case SPEED_100:
13592- *buf = SK_LSPEED_100MBPS;
13593- break;
13594- case SPEED_10:
13595- *buf = SK_LSPEED_10MBPS;
13596- }
13597+/*****************************************************************************
13598+ *
13599+ * SkGeGetCoalesce - retrieves the IRQ moderation settings
13600+ *
13601+ * Description:
13602+ * All current IRQ moderation settings of a selected adapter are placed
13603+ * in the passed ethtool_coalesce structure and are returned.
13604+ *
13605+ * Returns: N/A
13606+ *
13607+ */
13608+int SkGeGetCoalesce(struct net_device *dev,
13609+ struct ethtool_coalesce *ecmd)
13610+{
13611+ DEV_NET *pNet = (DEV_NET*) dev->priv;
13612+ SK_AC *pAC = pNet->pAC;
13613
13614- if (SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE,
13615- &buf, &len, instance, pNet->NetNr) != SK_PNMI_ERR_OK)
13616- return -EINVAL;
13617+ DIM_INFO *Info = &pAC->DynIrqModInfo;
13618+ SK_BOOL UseTxIrqModeration = SK_FALSE;
13619+ SK_BOOL UseRxIrqModeration = SK_FALSE;
13620+
13621+ if (Info->IntModTypeSelect != C_INT_MOD_NONE) {
13622+ if (CHIP_ID_YUKON_2(pAC)) {
13623+ UseRxIrqModeration = SK_TRUE;
13624+ UseTxIrqModeration = SK_TRUE;
13625+ } else {
13626+ if ((Info->MaskIrqModeration == IRQ_MASK_RX_ONLY) ||
13627+ (Info->MaskIrqModeration == IRQ_MASK_SP_RX) ||
13628+ (Info->MaskIrqModeration == IRQ_MASK_RX_TX_SP)) {
13629+ UseRxIrqModeration = SK_TRUE;
13630+ }
13631+ if ((Info->MaskIrqModeration == IRQ_MASK_TX_ONLY) ||
13632+ (Info->MaskIrqModeration == IRQ_MASK_SP_TX) ||
13633+ (Info->MaskIrqModeration == IRQ_MASK_RX_TX_SP)) {
13634+ UseTxIrqModeration = SK_TRUE;
13635+ }
13636+ }
13637
13638- return 0;
13639+ if (UseRxIrqModeration) {
13640+ ecmd->rx_coalesce_usecs = 1000000 / Info->MaxModIntsPerSec;
13641+ }
13642+ if (UseTxIrqModeration) {
13643+ ecmd->tx_coalesce_usecs = 1000000 / Info->MaxModIntsPerSec;
13644+ }
13645+ if (Info->IntModTypeSelect == C_INT_MOD_DYNAMIC) {
13646+ ecmd->rate_sample_interval = Info->DynIrqModSampleInterval;
13647+ if (UseRxIrqModeration) {
13648+ ecmd->use_adaptive_rx_coalesce = 1;
13649+ ecmd->rx_coalesce_usecs_low =
13650+ 1000000 / Info->MaxModIntsPerSecLowerLimit;
13651+ ecmd->rx_coalesce_usecs_high =
13652+ 1000000 / Info->MaxModIntsPerSecUpperLimit;
13653+ }
13654+ if (UseTxIrqModeration) {
13655+ ecmd->use_adaptive_tx_coalesce = 1;
13656+ ecmd->tx_coalesce_usecs_low =
13657+ 1000000 / Info->MaxModIntsPerSecLowerLimit;
13658+ ecmd->tx_coalesce_usecs_high =
13659+ 1000000 / Info->MaxModIntsPerSecUpperLimit;
13660+ }
13661+ }
13662+ }
13663+ return(0);
13664 }
13665
13666 /*****************************************************************************
13667 *
13668- * getDriverInfo - returns generic driver and adapter information
13669+ * SkGeGetRxCsum - retrieves the RxCsum parameters
13670 *
13671 * Description:
13672- * Generic driver information is returned via this function, such as
13673- * the name of the driver, its version and and firmware version.
13674- * In addition to this, the location of the selected adapter is
13675- * returned as a bus info string (e.g. '01:05.0').
13676- *
13677+ * All current RxCsum parameters of a selected adapter are placed
13678+ * in the passed net_device structure and are returned.
13679+ *
13680 * Returns: N/A
13681 *
13682 */
13683-static void getDriverInfo(struct net_device *dev, struct ethtool_drvinfo *info)
13684+SK_U32 SkGeGetRxCsum(struct net_device *dev)
13685 {
13686- const DEV_NET *pNet = netdev_priv(dev);
13687- const SK_AC *pAC = pNet->pAC;
13688- char vers[32];
13689-
13690- snprintf(vers, sizeof(vers)-1, VER_STRING "(v%d.%d)",
13691- (pAC->GIni.GIPciHwRev >> 4) & 0xf, pAC->GIni.GIPciHwRev & 0xf);
13692-
13693- strlcpy(info->driver, DRIVER_FILE_NAME, sizeof(info->driver));
13694- strcpy(info->version, vers);
13695- strcpy(info->fw_version, "N/A");
13696- strlcpy(info->bus_info, pci_name(pAC->PciDev), ETHTOOL_BUSINFO_LEN);
13697-}
13698-
13699-/*
13700- * Ethtool statistics support.
13701- */
13702-static const char StringsStats[][ETH_GSTRING_LEN] = {
13703- "rx_packets", "tx_packets",
13704- "rx_bytes", "tx_bytes",
13705- "rx_errors", "tx_errors",
13706- "rx_dropped", "tx_dropped",
13707- "multicasts", "collisions",
13708- "rx_length_errors", "rx_buffer_overflow_errors",
13709- "rx_crc_errors", "rx_frame_errors",
13710- "rx_too_short_errors", "rx_too_long_errors",
13711- "rx_carrier_extension_errors", "rx_symbol_errors",
13712- "rx_llc_mac_size_errors", "rx_carrier_errors",
13713- "rx_jabber_errors", "rx_missed_errors",
13714- "tx_abort_collision_errors", "tx_carrier_errors",
13715- "tx_buffer_underrun_errors", "tx_heartbeat_errors",
13716- "tx_window_errors",
13717-};
13718
13719-static int getStatsCount(struct net_device *dev)
13720-{
13721- return ARRAY_SIZE(StringsStats);
13722+ DEV_NET *pNet = (DEV_NET*) dev->priv;
13723+ SK_AC *pAC = pNet->pAC;
13724+ int port = pNet->PortNr;
13725+
13726+ return pAC->RxPort[port].UseRxCsum;
13727 }
13728
13729-static void getStrings(struct net_device *dev, u32 stringset, u8 *data)
13730+
13731+/*****************************************************************************
13732+ *
13733+ * SkGeGetStrings - retrieves the statistic strings
13734+ *
13735+ * Description:
13736+ * N/A
13737+ *
13738+ * Returns: N/A
13739+ *
13740+ */
13741+void SkGeGetStrings(struct net_device *dev,
13742+ u32 stringset,
13743+ u8 *strings)
13744 {
13745+ DEV_NET *pNet = (DEV_NET*) dev->priv;
13746+ int port = pNet->PortNr;
13747+ int i;
13748+
13749+ struct sk98lin_stats *sk98lin_etht_stats =
13750+ (port == 0) ? sk98lin_etht_stats_port0 : sk98lin_etht_stats_port1;
13751+
13752 switch(stringset) {
13753- case ETH_SS_STATS:
13754- memcpy(data, *StringsStats, sizeof(StringsStats));
13755- break;
13756+ case ETH_SS_STATS: {
13757+ for(i=0; i < SK98LIN_STATS_LEN; i++) {
13758+ memcpy(&strings[i * ETHT_STATSTRING_LEN],
13759+ &(sk98lin_etht_stats[i].stat_string),
13760+ ETHT_STATSTRING_LEN);
13761+ }
13762+ break;
13763+ }
13764 }
13765 }
13766
13767-static void getEthtoolStats(struct net_device *dev,
13768- struct ethtool_stats *stats, u64 *data)
13769-{
13770- const DEV_NET *pNet = netdev_priv(dev);
13771- const SK_AC *pAC = pNet->pAC;
13772- const SK_PNMI_STRUCT_DATA *pPnmiStruct = &pAC->PnmiStruct;
13773-
13774- *data++ = pPnmiStruct->Stat[0].StatRxOkCts;
13775- *data++ = pPnmiStruct->Stat[0].StatTxOkCts;
13776- *data++ = pPnmiStruct->Stat[0].StatRxOctetsOkCts;
13777- *data++ = pPnmiStruct->Stat[0].StatTxOctetsOkCts;
13778- *data++ = pPnmiStruct->InErrorsCts;
13779- *data++ = pPnmiStruct->Stat[0].StatTxSingleCollisionCts;
13780- *data++ = pPnmiStruct->RxNoBufCts;
13781- *data++ = pPnmiStruct->TxNoBufCts;
13782- *data++ = pPnmiStruct->Stat[0].StatRxMulticastOkCts;
13783- *data++ = pPnmiStruct->Stat[0].StatTxSingleCollisionCts;
13784- *data++ = pPnmiStruct->Stat[0].StatRxRuntCts;
13785- *data++ = pPnmiStruct->Stat[0].StatRxFifoOverflowCts;
13786- *data++ = pPnmiStruct->Stat[0].StatRxFcsCts;
13787- *data++ = pPnmiStruct->Stat[0].StatRxFramingCts;
13788- *data++ = pPnmiStruct->Stat[0].StatRxShortsCts;
13789- *data++ = pPnmiStruct->Stat[0].StatRxTooLongCts;
13790- *data++ = pPnmiStruct->Stat[0].StatRxCextCts;
13791- *data++ = pPnmiStruct->Stat[0].StatRxSymbolCts;
13792- *data++ = pPnmiStruct->Stat[0].StatRxIRLengthCts;
13793- *data++ = pPnmiStruct->Stat[0].StatRxCarrierCts;
13794- *data++ = pPnmiStruct->Stat[0].StatRxJabberCts;
13795- *data++ = pPnmiStruct->Stat[0].StatRxMissedCts;
13796- *data++ = pAC->stats.tx_aborted_errors;
13797- *data++ = pPnmiStruct->Stat[0].StatTxCarrierCts;
13798- *data++ = pPnmiStruct->Stat[0].StatTxFifoUnderrunCts;
13799- *data++ = pPnmiStruct->Stat[0].StatTxCarrierCts;
13800- *data++ = pAC->stats.tx_window_errors;
13801-}
13802-
13803
13804 /*****************************************************************************
13805 *
13806- * toggleLeds - Changes the LED state of an adapter
13807+ * SkGeGetStatsLen - retrieves the statistic count
13808 *
13809 * Description:
13810- * This function changes the current state of all LEDs of an adapter so
13811- * that it can be located by a user.
13812+ * N/A
13813 *
13814 * Returns: N/A
13815 *
13816 */
13817-static void toggleLeds(DEV_NET *pNet, int on)
13818+int SkGeGetStatsLen(struct net_device *dev)
13819 {
13820- SK_AC *pAC = pNet->pAC;
13821- int port = pNet->PortNr;
13822- void __iomem *io = pAC->IoBase;
13823-
13824- if (pAC->GIni.GIGenesis) {
13825- SK_OUT8(io, MR_ADDR(port,LNK_LED_REG),
13826- on ? SK_LNK_ON : SK_LNK_OFF);
13827- SkGeYellowLED(pAC, io,
13828- on ? (LED_ON >> 1) : (LED_OFF >> 1));
13829- SkGeXmitLED(pAC, io, MR_ADDR(port,RX_LED_INI),
13830- on ? SK_LED_TST : SK_LED_DIS);
13831-
13832- if (pAC->GIni.GP[port].PhyType == SK_PHY_BCOM)
13833- SkXmPhyWrite(pAC, io, port, PHY_BCOM_P_EXT_CTRL,
13834- on ? PHY_B_PEC_LED_ON : PHY_B_PEC_LED_OFF);
13835- else if (pAC->GIni.GP[port].PhyType == SK_PHY_LONE)
13836- SkXmPhyWrite(pAC, io, port, PHY_LONE_LED_CFG,
13837- on ? 0x0800 : PHY_L_LC_LEDT);
13838- else
13839- SkGeXmitLED(pAC, io, MR_ADDR(port,TX_LED_INI),
13840- on ? SK_LED_TST : SK_LED_DIS);
13841- } else {
13842- const u16 YukLedOn = (PHY_M_LED_MO_DUP(MO_LED_ON) |
13843- PHY_M_LED_MO_10(MO_LED_ON) |
13844- PHY_M_LED_MO_100(MO_LED_ON) |
13845- PHY_M_LED_MO_1000(MO_LED_ON) |
13846- PHY_M_LED_MO_RX(MO_LED_ON));
13847- const u16 YukLedOff = (PHY_M_LED_MO_DUP(MO_LED_OFF) |
13848- PHY_M_LED_MO_10(MO_LED_OFF) |
13849- PHY_M_LED_MO_100(MO_LED_OFF) |
13850- PHY_M_LED_MO_1000(MO_LED_OFF) |
13851- PHY_M_LED_MO_RX(MO_LED_OFF));
13852-
13853-
13854- SkGmPhyWrite(pAC,io,port,PHY_MARV_LED_CTRL,0);
13855- SkGmPhyWrite(pAC,io,port,PHY_MARV_LED_OVER,
13856- on ? YukLedOn : YukLedOff);
13857- }
13858+ return SK98LIN_STATS_LEN;
13859 }
13860
13861+
13862+
13863+
13864 /*****************************************************************************
13865 *
13866- * skGeBlinkTimer - Changes the LED state of an adapter
13867+ * SkGeGetEthStats - retrieves the card statistics
13868 *
13869 * Description:
13870- * This function changes the current state of all LEDs of an adapter so
13871- * that it can be located by a user. If the requested time interval for
13872- * this test has elapsed, this function cleans up everything that was
13873- * temporarily setup during the locate NIC test. This involves of course
13874- * also closing or opening any adapter so that the initial board state
13875- * is recovered.
13876+ * All current statistics of a selected adapter are placed
13877+ * in the passed ethtool_stats structure and are returned.
13878 *
13879 * Returns: N/A
13880 *
13881 */
13882-void SkGeBlinkTimer(unsigned long data)
13883+void SkGeGetEthStats(struct net_device *dev,
13884+ struct ethtool_stats *stats,
13885+ u64 *data)
13886 {
13887- struct net_device *dev = (struct net_device *) data;
13888- DEV_NET *pNet = netdev_priv(dev);
13889- SK_AC *pAC = pNet->pAC;
13890+ DEV_NET *pNet = (DEV_NET*) dev->priv;
13891+ SK_AC *pAC = pNet->pAC;
13892+ SK_U32 Size = sizeof(SK_PNMI_STRUCT_DATA);
13893+ SK_PNMI_STRUCT_DATA *pPnmiStruct = &pAC->PnmiStruct;
13894+ int port = pNet->PortNr;
13895+ int i;
13896
13897- toggleLeds(pNet, pAC->LedsOn);
13898+ struct sk98lin_stats *sk98lin_etht_stats =
13899+ (port == 0) ? sk98lin_etht_stats_port0 : sk98lin_etht_stats_port1;
13900
13901- pAC->LedsOn = !pAC->LedsOn;
13902- mod_timer(&pAC->BlinkTimer, jiffies + HZ/4);
13903+ if (netif_running(pAC->dev[port])) {
13904+ SkPnmiGetStruct(pAC, pAC->IoBase, pPnmiStruct, &Size, port);
13905+ }
13906+
13907+ for(i = 0; i < SK98LIN_STATS_LEN; i++) {
13908+ if (netif_running(pAC->dev[port])) {
13909+ data[i] = (sk98lin_etht_stats[i].sizeof_stat ==
13910+ sizeof(uint64_t)) ?
13911+ *(uint64_t *)((char *)pAC +
13912+ sk98lin_etht_stats[i].stat_offset) :
13913+ *(uint32_t *)((char *)pAC +
13914+ sk98lin_etht_stats[i].stat_offset);
13915+ } else {
13916+ data[i] = (sk98lin_etht_stats[i].sizeof_stat ==
13917+ sizeof(uint64_t)) ? (uint64_t) 0 : (uint32_t) 0;
13918+ }
13919+ }
13920 }
13921
13922+
13923 /*****************************************************************************
13924 *
13925- * locateDevice - start the locate NIC feature of the elected adapter
13926+ * SkGeSetSettings - configures the settings of a selected adapter
13927 *
13928 * Description:
13929- * This function is used if the user want to locate a particular NIC.
13930- * All LEDs are regularly switched on and off, so the NIC can easily
13931- * be identified.
13932- *
13933- * Returns:
13934- * ==0: everything fine, no error, locateNIC test was started
13935- * !=0: one locateNIC test runs already
13936+ * Possible settings that may be altered are a)speed, b)duplex or
13937+ * c)autonegotiation.
13938 *
13939+ * Returns:
13940+ * ==0: everything fine, no error
13941+ * !=0: the return value is the error code of the failure
13942 */
13943-static int locateDevice(struct net_device *dev, u32 data)
13944+int SkGeSetSettings(struct net_device *dev,
13945+ struct ethtool_cmd *ecmd)
13946 {
13947- DEV_NET *pNet = netdev_priv(dev);
13948- SK_AC *pAC = pNet->pAC;
13949+ DEV_NET *pNet = (DEV_NET*) dev->priv;
13950+ SK_AC *pAC = pNet->pAC;
13951+ int port = pNet->PortNr;
13952+
13953+ SK_U32 Instance;
13954+ char Buf[4];
13955+ unsigned int Len = 1;
13956+ int Ret;
13957
13958- if(!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
13959- data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
13960+ if (port == 0) {
13961+ Instance = (pAC->RlmtNets == 2) ? 1 : 2;
13962+ } else {
13963+ Instance = (pAC->RlmtNets == 2) ? 2 : 3;
13964+ }
13965
13966- /* start blinking */
13967- pAC->LedsOn = 0;
13968- mod_timer(&pAC->BlinkTimer, jiffies);
13969- msleep_interruptible(data * 1000);
13970- del_timer_sync(&pAC->BlinkTimer);
13971- toggleLeds(pNet, 0);
13972+ if (((ecmd->autoneg == AUTONEG_DISABLE) || (ecmd->autoneg == AUTONEG_ENABLE)) &&
13973+ ((ecmd->duplex == DUPLEX_FULL) || (ecmd->duplex == DUPLEX_HALF))) {
13974+ if (ecmd->autoneg == AUTONEG_DISABLE) {
13975+ if (ecmd->duplex == DUPLEX_FULL) {
13976+ *Buf = (char) SK_LMODE_FULL;
13977+ } else {
13978+ *Buf = (char) SK_LMODE_HALF;
13979+ }
13980+ } else {
13981+ /* Autoneg on. Enable autoparam */
13982+ *Buf = (char) SK_LMODE_AUTOBOTH;
13983+ }
13984
13985- return 0;
13986+ Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_LINK_MODE,
13987+ &Buf, &Len, Instance, pNet->NetNr);
13988+
13989+ if (Ret != SK_PNMI_ERR_OK) {
13990+ return -EINVAL;
13991+ }
13992+ } else if (ecmd->autoneg == AUTONEG_ENABLE) {
13993+ /* Set default values */
13994+ *Buf = (char) SK_LMODE_AUTOFULL;
13995+ Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_LINK_MODE,
13996+ &Buf, &Len, Instance, pNet->NetNr);
13997+ }
13998+
13999+ if ((ecmd->speed == SPEED_1000) ||
14000+ (ecmd->speed == SPEED_100) ||
14001+ (ecmd->speed == SPEED_10)) {
14002+
14003+ if (ecmd->autoneg == AUTONEG_ENABLE) {
14004+ *Buf = (char) SK_LSPEED_AUTO;
14005+ } else if (ecmd->speed == SPEED_1000) {
14006+ *Buf = (char) SK_LSPEED_1000MBPS;
14007+ } else if (ecmd->speed == SPEED_100) {
14008+ *Buf = (char) SK_LSPEED_100MBPS;
14009+ } else {
14010+ *Buf = (char) SK_LSPEED_10MBPS;
14011+ }
14012+
14013+ Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE,
14014+ &Buf, &Len, Instance, pNet->NetNr);
14015+
14016+ if (Ret != SK_PNMI_ERR_OK) {
14017+ return -EINVAL;
14018+ }
14019+ } else if (ecmd->autoneg == AUTONEG_ENABLE) {
14020+ *Buf = (char) SK_LSPEED_AUTO;
14021+ Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE,
14022+ &Buf, &Len, Instance, pNet->NetNr);
14023+ } else {
14024+ return -EINVAL;
14025+ }
14026+
14027+ return(0);
14028 }
14029
14030 /*****************************************************************************
14031 *
14032- * getPauseParams - retrieves the pause parameters
14033+ * SkGeSetWolSettings - configures the WOL settings of a selected adapter
14034 *
14035 * Description:
14036- * All current pause parameters of a selected adapter are placed
14037- * in the passed ethtool_pauseparam structure and are returned.
14038- *
14039- * Returns: N/A
14040+ * The WOL settings of a selected adapter are configured regarding
14041+ * the parameters in the passed ethtool_wolinfo structure.
14042+ * Note that currently only wake on magic packet is supported!
14043 *
14044+ * Returns:
14045+ * ==0: everything fine, no error
14046+ * !=0: the return value is the error code of the failure
14047 */
14048-static void getPauseParams(struct net_device *dev, struct ethtool_pauseparam *epause)
14049+int SkGeSetWolSettings(struct net_device *dev,
14050+ struct ethtool_wolinfo *ecmd)
14051 {
14052- DEV_NET *pNet = netdev_priv(dev);
14053- SK_AC *pAC = pNet->pAC;
14054- SK_GEPORT *pPort = &pAC->GIni.GP[pNet->PortNr];
14055+ DEV_NET *pNet = (DEV_NET*) dev->priv;
14056+ SK_AC *pAC = pNet->pAC;
14057
14058- epause->rx_pause = (pPort->PFlowCtrlMode == SK_FLOW_MODE_SYMMETRIC) ||
14059- (pPort->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM);
14060+ if (ecmd->wolopts != WAKE_MAGIC && ecmd->wolopts != 0)
14061+ return -EOPNOTSUPP;
14062
14063- epause->tx_pause = epause->rx_pause || (pPort->PFlowCtrlMode == SK_FLOW_MODE_LOC_SEND);
14064- epause->autoneg = epause->rx_pause || epause->tx_pause;
14065+ if (((ecmd->wolopts & WAKE_MAGIC) == WAKE_MAGIC) || (ecmd->wolopts == 0)) {
14066+ pAC->WolInfo.ConfiguredWolOptions = ecmd->wolopts;
14067+ return 0;
14068+ }
14069+ return -EFAULT;
14070 }
14071
14072+
14073 /*****************************************************************************
14074 *
14075- * setPauseParams - configures the pause parameters of an adapter
14076+ * SkGeSetPauseParam - configures the pause parameters of an adapter
14077 *
14078 * Description:
14079 * This function sets the Rx or Tx pause parameters
14080@@ -478,151 +664,598 @@
14081 * ==0: everything fine, no error
14082 * !=0: the return value is the error code of the failure
14083 */
14084-static int setPauseParams(struct net_device *dev , struct ethtool_pauseparam *epause)
14085+int SkGeSetPauseParam(struct net_device *dev,
14086+ struct ethtool_pauseparam *ecmd)
14087 {
14088- DEV_NET *pNet = netdev_priv(dev);
14089- SK_AC *pAC = pNet->pAC;
14090- SK_GEPORT *pPort = &pAC->GIni.GP[pNet->PortNr];
14091- u32 instance = pnmiInstance(pNet);
14092- struct ethtool_pauseparam old;
14093- u8 oldspeed = pPort->PLinkSpeedUsed;
14094- char buf[4];
14095- int len = 1;
14096- int ret;
14097+ DEV_NET *pNet = (DEV_NET*) dev->priv;
14098+ SK_AC *pAC = pNet->pAC;
14099+ int port = pNet->PortNr;
14100+ SK_GEPORT *pPort = &pAC->GIni.GP[port];
14101+ int PrevSpeedVal = pPort->PLinkSpeedUsed;
14102+ SK_U32 Instance;
14103+ char Buf[4];
14104+ int Ret;
14105+ SK_BOOL prevAutonegValue = SK_TRUE;
14106+ int prevTxPause = 0;
14107+ int prevRxPause = 0;
14108+ unsigned int Len = 1;
14109+
14110+
14111+ if (port == 0) {
14112+ Instance = (pAC->RlmtNets == 2) ? 1 : 2;
14113+ } else {
14114+ Instance = (pAC->RlmtNets == 2) ? 2 : 3;
14115+ }
14116
14117 /*
14118 ** we have to determine the current settings to see if
14119 ** the operator requested any modification of the flow
14120 ** control parameters...
14121 */
14122- getPauseParams(dev, &old);
14123+ if (pPort->PFlowCtrlMode == SK_FLOW_MODE_LOC_SEND) {
14124+ prevTxPause = 1;
14125+ }
14126+ if ((pPort->PFlowCtrlMode == SK_FLOW_MODE_SYMMETRIC) ||
14127+ (pPort->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM)) {
14128+ prevTxPause = 1;
14129+ prevRxPause = 1;
14130+ }
14131+
14132+ if ((prevRxPause == 0) && (prevTxPause == 0)) {
14133+ prevAutonegValue = SK_FALSE;
14134+ }
14135+
14136
14137 /*
14138 ** perform modifications regarding the changes
14139 ** requested by the operator
14140 */
14141- if (epause->autoneg != old.autoneg)
14142- *buf = epause->autoneg ? SK_FLOW_MODE_NONE : SK_FLOW_MODE_SYMMETRIC;
14143- else {
14144- if (epause->rx_pause && epause->tx_pause)
14145- *buf = SK_FLOW_MODE_SYMMETRIC;
14146- else if (epause->rx_pause && !epause->tx_pause)
14147- *buf = SK_FLOW_MODE_SYM_OR_REM;
14148- else if (!epause->rx_pause && epause->tx_pause)
14149- *buf = SK_FLOW_MODE_LOC_SEND;
14150- else
14151- *buf = SK_FLOW_MODE_NONE;
14152+ if (ecmd->autoneg != prevAutonegValue) {
14153+ if (ecmd->autoneg == AUTONEG_DISABLE) {
14154+ *Buf = (char) SK_FLOW_MODE_NONE;
14155+ } else {
14156+ *Buf = (char) SK_FLOW_MODE_SYMMETRIC;
14157+ }
14158+ } else {
14159+ if(ecmd->rx_pause && ecmd->tx_pause) {
14160+ *Buf = (char) SK_FLOW_MODE_SYMMETRIC;
14161+ } else if (ecmd->rx_pause && !ecmd->tx_pause) {
14162+ *Buf = (char) SK_FLOW_MODE_SYM_OR_REM;
14163+ } else if(!ecmd->rx_pause && ecmd->tx_pause) {
14164+ *Buf = (char) SK_FLOW_MODE_LOC_SEND;
14165+ } else {
14166+ *Buf = (char) SK_FLOW_MODE_NONE;
14167+ }
14168 }
14169
14170- ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_FLOWCTRL_MODE,
14171- &buf, &len, instance, pNet->NetNr);
14172+ Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_FLOWCTRL_MODE,
14173+ &Buf, &Len, Instance, pNet->NetNr);
14174
14175- if (ret != SK_PNMI_ERR_OK) {
14176+ if (Ret != SK_PNMI_ERR_OK) {
14177 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_CTRL,
14178- ("ethtool (sk98lin): error changing rx/tx pause (%i)\n", ret));
14179- goto err;
14180+ ("ethtool (sk98lin): error changing rx/tx pause (%i)\n", Ret));
14181+ } else {
14182+ Len = 1; /* set buffer length to correct value */
14183 }
14184
14185 /*
14186 ** It may be that autoneg has been disabled! Therefore
14187 ** set the speed to the previously used value...
14188 */
14189- if (!epause->autoneg) {
14190- len = 1;
14191- ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE,
14192- &oldspeed, &len, instance, pNet->NetNr);
14193- if (ret != SK_PNMI_ERR_OK)
14194- SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_CTRL,
14195- ("ethtool (sk98lin): error setting speed (%i)\n", ret));
14196+ *Buf = (char) PrevSpeedVal;
14197+
14198+ Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE,
14199+ &Buf, &Len, Instance, pNet->NetNr);
14200+
14201+ if (Ret != SK_PNMI_ERR_OK) {
14202+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_CTRL,
14203+ ("ethtool (sk98lin): error setting speed (%i)\n", Ret));
14204+ }
14205+ return 0;
14206+}
14207+
14208+
14209+/*****************************************************************************
14210+ *
14211+ * SkGeSetCoalesce - configures the IRQ moderation of an adapter
14212+ *
14213+ * Description:
14214+ * Depending on the desired IRQ moderation parameters, either a) static,
14215+ * b) dynamic or c) no moderation is configured.
14216+ *
14217+ * Returns:
14218+ * ==0: everything fine, no error
14219+ * !=0: the return value is the error code of the failure
14220+ *
14221+ * Notes:
14222+ * The supported timeframe for the coalesced interrupts ranges from
14223+ * 33.333us (30 IntsPerSec) down to 25us (40.000 IntsPerSec).
14224+ * Any requested value that is not in this range will abort the request!
14225+ */
14226+int SkGeSetCoalesce(struct net_device *dev,
14227+ struct ethtool_coalesce *ecmd)
14228+{
14229+ DEV_NET *pNet = (DEV_NET*) dev->priv;
14230+ SK_AC *pAC = pNet->pAC;
14231+ DIM_INFO *Info = &pAC->DynIrqModInfo;
14232+ int PrevModeration = Info->IntModTypeSelect;
14233+
14234+ Info->IntModTypeSelect = C_INT_MOD_NONE; /* initial default */
14235+
14236+ if ((ecmd->rx_coalesce_usecs) || (ecmd->tx_coalesce_usecs)) {
14237+ if (ecmd->rx_coalesce_usecs) {
14238+ if ((ecmd->rx_coalesce_usecs < 25) ||
14239+ (ecmd->rx_coalesce_usecs > 33333)) {
14240+ return -EINVAL;
14241+ }
14242+ }
14243+ if (ecmd->tx_coalesce_usecs) {
14244+ if ((ecmd->tx_coalesce_usecs < 25) ||
14245+ (ecmd->tx_coalesce_usecs > 33333)) {
14246+ return -EINVAL;
14247+ }
14248+ }
14249+ if (!CHIP_ID_YUKON_2(pAC)) {
14250+ if ((Info->MaskIrqModeration == IRQ_MASK_SP_RX) ||
14251+ (Info->MaskIrqModeration == IRQ_MASK_SP_TX) ||
14252+ (Info->MaskIrqModeration == IRQ_MASK_RX_TX_SP)) {
14253+ Info->MaskIrqModeration = IRQ_MASK_SP_ONLY;
14254+ }
14255+ }
14256+ Info->IntModTypeSelect = C_INT_MOD_STATIC;
14257+ if (ecmd->rx_coalesce_usecs) {
14258+ Info->MaxModIntsPerSec =
14259+ 1000000 / ecmd->rx_coalesce_usecs;
14260+ if (!CHIP_ID_YUKON_2(pAC)) {
14261+ if (Info->MaskIrqModeration == IRQ_MASK_TX_ONLY) {
14262+ Info->MaskIrqModeration = IRQ_MASK_TX_RX;
14263+ }
14264+ if (Info->MaskIrqModeration == IRQ_MASK_SP_ONLY) {
14265+ Info->MaskIrqModeration = IRQ_MASK_SP_RX;
14266+ }
14267+ if (Info->MaskIrqModeration == IRQ_MASK_SP_TX) {
14268+ Info->MaskIrqModeration = IRQ_MASK_RX_TX_SP;
14269+ }
14270+ } else {
14271+ Info->MaskIrqModeration = Y2_IRQ_MASK;
14272+ }
14273+ }
14274+ if (ecmd->tx_coalesce_usecs) {
14275+ Info->MaxModIntsPerSec =
14276+ 1000000 / ecmd->tx_coalesce_usecs;
14277+ if (!CHIP_ID_YUKON_2(pAC)) {
14278+ if (Info->MaskIrqModeration == IRQ_MASK_RX_ONLY) {
14279+ Info->MaskIrqModeration = IRQ_MASK_TX_RX;
14280+ }
14281+ if (Info->MaskIrqModeration == IRQ_MASK_SP_ONLY) {
14282+ Info->MaskIrqModeration = IRQ_MASK_SP_TX;
14283+ }
14284+ if (Info->MaskIrqModeration == IRQ_MASK_SP_RX) {
14285+ Info->MaskIrqModeration = IRQ_MASK_RX_TX_SP;
14286+ }
14287+ } else {
14288+ Info->MaskIrqModeration = Y2_IRQ_MASK;
14289+ }
14290+ }
14291+ }
14292+ if ((ecmd->rate_sample_interval) ||
14293+ (ecmd->rx_coalesce_usecs_low) ||
14294+ (ecmd->tx_coalesce_usecs_low) ||
14295+ (ecmd->rx_coalesce_usecs_high)||
14296+ (ecmd->tx_coalesce_usecs_high)) {
14297+ if (ecmd->rate_sample_interval) {
14298+ if ((ecmd->rate_sample_interval < 1) ||
14299+ (ecmd->rate_sample_interval > 10)) {
14300+ return -EINVAL;
14301+ }
14302+ }
14303+ if (ecmd->rx_coalesce_usecs_low) {
14304+ if ((ecmd->rx_coalesce_usecs_low < 25) ||
14305+ (ecmd->rx_coalesce_usecs_low > 33333)) {
14306+ return -EINVAL;
14307+ }
14308+ }
14309+ if (ecmd->rx_coalesce_usecs_high) {
14310+ if ((ecmd->rx_coalesce_usecs_high < 25) ||
14311+ (ecmd->rx_coalesce_usecs_high > 33333)) {
14312+ return -EINVAL;
14313+ }
14314+ }
14315+ if (ecmd->tx_coalesce_usecs_low) {
14316+ if ((ecmd->tx_coalesce_usecs_low < 25) ||
14317+ (ecmd->tx_coalesce_usecs_low > 33333)) {
14318+ return -EINVAL;
14319+ }
14320+ }
14321+ if (ecmd->tx_coalesce_usecs_high) {
14322+ if ((ecmd->tx_coalesce_usecs_high < 25) ||
14323+ (ecmd->tx_coalesce_usecs_high > 33333)) {
14324+ return -EINVAL;
14325+ }
14326+ }
14327+
14328+ Info->IntModTypeSelect = C_INT_MOD_DYNAMIC;
14329+ if (ecmd->rate_sample_interval) {
14330+ Info->DynIrqModSampleInterval =
14331+ ecmd->rate_sample_interval;
14332+ }
14333+ if (ecmd->rx_coalesce_usecs_low) {
14334+ Info->MaxModIntsPerSecLowerLimit =
14335+ 1000000 / ecmd->rx_coalesce_usecs_low;
14336+ }
14337+ if (ecmd->tx_coalesce_usecs_low) {
14338+ Info->MaxModIntsPerSecLowerLimit =
14339+ 1000000 / ecmd->tx_coalesce_usecs_low;
14340+ }
14341+ if (ecmd->rx_coalesce_usecs_high) {
14342+ Info->MaxModIntsPerSecUpperLimit =
14343+ 1000000 / ecmd->rx_coalesce_usecs_high;
14344+ }
14345+ if (ecmd->tx_coalesce_usecs_high) {
14346+ Info->MaxModIntsPerSecUpperLimit =
14347+ 1000000 / ecmd->tx_coalesce_usecs_high;
14348+ }
14349+ }
14350+
14351+ if ((PrevModeration == C_INT_MOD_NONE) &&
14352+ (Info->IntModTypeSelect != C_INT_MOD_NONE)) {
14353+ SkDimEnableModerationIfNeeded(pAC);
14354+ }
14355+ if (PrevModeration != C_INT_MOD_NONE) {
14356+ SkDimDisableModeration(pAC, PrevModeration);
14357+ if (Info->IntModTypeSelect != C_INT_MOD_NONE) {
14358+ SkDimEnableModerationIfNeeded(pAC);
14359+ }
14360 }
14361- err:
14362- return ret ? -EIO : 0;
14363+
14364+ return 0;
14365 }
14366
14367-/* Only Yukon supports checksum offload. */
14368-static int setScatterGather(struct net_device *dev, u32 data)
14369+
14370+/*****************************************************************************
14371+ *
14372+ * SkGeSetSG - set the SG parameters
14373+ *
14374+ * Description:
14375+ * This function sets the SG parameters
14376+ *
14377+ * Returns:
14378+ * ==0: everything fine, no error
14379+ * !=0: the return value is the error code of the failure
14380+ */
14381+int SkGeSetSG(struct net_device *dev,
14382+ u32 data)
14383 {
14384- DEV_NET *pNet = netdev_priv(dev);
14385- SK_AC *pAC = pNet->pAC;
14386+ DEV_NET *pNet = (DEV_NET*) dev->priv;
14387+ SK_AC *pAC = pNet->pAC;
14388
14389- if (pAC->GIni.GIChipId == CHIP_ID_GENESIS)
14390+ if (pAC->GIni.GIGenesis)
14391 return -EOPNOTSUPP;
14392+
14393 return ethtool_op_set_sg(dev, data);
14394 }
14395
14396-static int setTxCsum(struct net_device *dev, u32 data)
14397+
14398+
14399+
14400+/*****************************************************************************
14401+ *
14402+ * SkGeSetTxCsum - set the TxCsum parameters
14403+ *
14404+ * Description:
14405+ * This function sets the TxCsum parameters
14406+ *
14407+ * Returns:
14408+ * ==0: everything fine, no error
14409+ * !=0: the return value is the error code of the failure
14410+ */
14411+int SkGeSetTxCsum(struct net_device *dev,
14412+ u32 data)
14413 {
14414- DEV_NET *pNet = netdev_priv(dev);
14415- SK_AC *pAC = pNet->pAC;
14416+ DEV_NET *pNet = (DEV_NET*) dev->priv;
14417+ SK_AC *pAC = pNet->pAC;
14418
14419- if (pAC->GIni.GIChipId == CHIP_ID_GENESIS)
14420+ if (pAC->GIni.GIGenesis)
14421 return -EOPNOTSUPP;
14422
14423 return ethtool_op_set_tx_csum(dev, data);
14424 }
14425
14426-static u32 getRxCsum(struct net_device *dev)
14427+
14428+/*****************************************************************************
14429+ *
14430+ * SkGeSetRxCsum - set the SkGeSetRxCsum parameters
14431+ *
14432+ * Description:
14433+ * This function sets the RxCsum parameters
14434+ *
14435+ * Returns:
14436+ * ==0: everything fine, no error
14437+ * !=0: the return value is the error code of the failure
14438+ */
14439+int SkGeSetRxCsum(struct net_device *dev,
14440+ u32 data)
14441 {
14442- DEV_NET *pNet = netdev_priv(dev);
14443- SK_AC *pAC = pNet->pAC;
14444+ DEV_NET *pNet = (DEV_NET*) dev->priv;
14445+ SK_AC *pAC = pNet->pAC;
14446+ int port = pNet->PortNr;
14447+
14448+ if (pAC->GIni.GIGenesis && data)
14449+ return -EOPNOTSUPP;
14450
14451- return pAC->RxPort[pNet->PortNr].RxCsum;
14452+ pAC->RxPort[port].UseRxCsum = data;
14453+ return 0;
14454 }
14455
14456-static int setRxCsum(struct net_device *dev, u32 data)
14457+/*****************************************************************************
14458+ *
14459+ * SkGePhysId - start the locate NIC feature of the elected adapter
14460+ *
14461+ * Description:
14462+ * This function is used if the user want to locate a particular NIC.
14463+ * All LEDs are regularly switched on and off, so the NIC can easily
14464+ * be identified.
14465+ *
14466+ * Returns:
14467+ * ==0: everything fine, no error, locateNIC test was started
14468+ * !=0: one locateNIC test runs already
14469+ *
14470+ */
14471+int SkGePhysId(struct net_device *dev,
14472+ u32 data)
14473 {
14474- DEV_NET *pNet = netdev_priv(dev);
14475- SK_AC *pAC = pNet->pAC;
14476+ DEV_NET *pNet = (DEV_NET*) dev->priv;
14477+ SK_AC *pAC = pNet->pAC;
14478+ SK_IOC IoC = pAC->IoBase;
14479+ int port = pNet->PortNr;
14480+ struct SK_NET_DEVICE *pDev = pAC->dev[port];
14481+ int OtherPort = (port) ? 0 : 1;
14482+ struct SK_NET_DEVICE *pOtherDev = pAC->dev[OtherPort];
14483
14484- if (pAC->GIni.GIChipId == CHIP_ID_GENESIS)
14485- return -EOPNOTSUPP;
14486+ if (isLocateNICrunning) {
14487+ return -EFAULT;
14488+ }
14489+ isLocateNICrunning = SK_TRUE;
14490+ currentPortIndex = port;
14491+ isDualNetCard = (pDev != pOtherDev) ? SK_TRUE : SK_FALSE;
14492+ doSwitchLEDsOn = SK_FALSE;
14493+
14494+ if (netif_running(pAC->dev[port])) {
14495+ boardWasDown[0] = SK_FALSE;
14496+ } else {
14497+ (*pDev->open)(pDev);
14498+ boardWasDown[0] = SK_TRUE;
14499+ }
14500+
14501+ if (isDualNetCard) {
14502+ if (netif_running(pAC->dev[OtherPort])) {
14503+ boardWasDown[1] = SK_FALSE;
14504+ } else {
14505+ (*pOtherDev->open)(pOtherDev);
14506+ boardWasDown[1] = SK_TRUE;
14507+ }
14508+ }
14509+
14510+ if ( (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL) ||
14511+ (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) ) {
14512+ SkMacClearRst(pAC, IoC, port);
14513+ }
14514+
14515+
14516+ if ((data < 1) || (data > 30)) {
14517+ data = 3; /* three seconds default */
14518+ }
14519+ nbrBlinkQuarterSeconds = 4*data;
14520+
14521+ init_timer(&locateNICtimer);
14522+ locateNICtimer.function = toggleLeds;
14523+ locateNICtimer.data = (unsigned long) pNet;
14524+ locateNICtimer.expires = jiffies + HZ; /* initially 1sec */
14525+ add_timer(&locateNICtimer);
14526
14527- pAC->RxPort[pNet->PortNr].RxCsum = data != 0;
14528 return 0;
14529 }
14530
14531-static int getRegsLen(struct net_device *dev)
14532+/*****************************************************************************
14533+ *
14534+ * toggleLeds - Changes the LED state of an adapter
14535+ *
14536+ * Description:
14537+ * This function changes the current state of all LEDs of an adapter so
14538+ * that it can be located by a user. If the requested time interval for
14539+ * this test has elapsed, this function cleans up everything that was
14540+ * temporarily setup during the locate NIC test. This involves of course
14541+ * also closing or opening any adapter so that the initial board state
14542+ * is recovered.
14543+ *
14544+ * Returns: N/A
14545+ *
14546+ */
14547+static void toggleLeds(
14548+unsigned long ptr) /* holds the pointer to adapter control context */
14549+{
14550+ DEV_NET *pNet = (DEV_NET*) ptr;
14551+ SK_AC *pAC = pNet->pAC;
14552+ int port = pNet->PortNr;
14553+ SK_IOC IoC = pAC->IoBase;
14554+ struct SK_NET_DEVICE *pDev = pAC->dev[port];
14555+ int OtherPort = (port) ? 0 : 1;
14556+ struct SK_NET_DEVICE *pOtherDev = pAC->dev[OtherPort];
14557+ SK_U16 PageSelect;
14558+ SK_BOOL YukLedState;
14559+
14560+ SK_U16 YukLedOn = (PHY_M_LED_MO_DUP(MO_LED_ON) |
14561+ PHY_M_LED_MO_10(MO_LED_ON) |
14562+ PHY_M_LED_MO_100(MO_LED_ON) |
14563+ PHY_M_LED_MO_1000(MO_LED_ON) |
14564+ PHY_M_LED_MO_RX(MO_LED_ON));
14565+ SK_U16 YukLedOff = (PHY_M_LED_MO_DUP(MO_LED_OFF) |
14566+ PHY_M_LED_MO_10(MO_LED_OFF) |
14567+ PHY_M_LED_MO_100(MO_LED_OFF) |
14568+ PHY_M_LED_MO_1000(MO_LED_OFF) |
14569+ PHY_M_LED_MO_RX(MO_LED_OFF) |
14570+ PHY_M_LED_MO_TX(MO_LED_OFF));
14571+
14572+ nbrBlinkQuarterSeconds--;
14573+ if (nbrBlinkQuarterSeconds <= 0) {
14574+ /*
14575+ * We have to stop the device again in case the device has no
14576+ * been up.
14577+ */
14578+
14579+ if (!boardWasDown[0]) {
14580+ /*
14581+ * The board is already up as we bring it up in case it is not.
14582+ */
14583+ } else {
14584+ (*pDev->stop)(pDev);
14585+ }
14586+ if (isDualNetCard) {
14587+ if (!boardWasDown[1]) {
14588+ /*
14589+ * The board is already up as we bring it up in case it is not.
14590+ */
14591+ } else {
14592+ (*pOtherDev->stop)(pOtherDev);
14593+ }
14594+
14595+ }
14596+
14597+ isDualNetCard = SK_FALSE;
14598+ isLocateNICrunning = SK_FALSE;
14599+ return;
14600+ }
14601+ doSwitchLEDsOn = (doSwitchLEDsOn) ? SK_FALSE : SK_TRUE;
14602+
14603+ if (doSwitchLEDsOn) {
14604+ if (pAC->GIni.GIGenesis) {
14605+ SK_OUT8(IoC,MR_ADDR(port,LNK_LED_REG),(SK_U8)SK_LNK_ON);
14606+ SkGeYellowLED(pAC,IoC,LED_ON >> 1);
14607+ SkGeXmitLED(pAC,IoC,MR_ADDR(port,RX_LED_INI),SK_LED_TST);
14608+ if (pAC->GIni.GP[port].PhyType == SK_PHY_BCOM) {
14609+ SkXmPhyWrite(pAC,IoC,port,PHY_BCOM_P_EXT_CTRL,PHY_B_PEC_LED_ON);
14610+ } else if (pAC->GIni.GP[port].PhyType == SK_PHY_LONE) {
14611+ SkXmPhyWrite(pAC,IoC,port,PHY_LONE_LED_CFG,0x0800);
14612+ } else {
14613+ SkGeXmitLED(pAC,IoC,MR_ADDR(port,TX_LED_INI),SK_LED_TST);
14614+ }
14615+ } else {
14616+ if ( (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL) ||
14617+ (pAC->GIni.GIChipId == CHIP_ID_YUKON_2(pAC)) ||
14618+ (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) ) {
14619+
14620+ YukLedOn = 0;
14621+ YukLedState = 1;
14622+ YukLedOn |= PHY_M_LEDC_INIT_CTRL(YukLedState ? 9 : 8);
14623+ YukLedState = 1;
14624+ YukLedOn |= PHY_M_LEDC_STA1_CTRL(YukLedState ? 9 : 8);
14625+ YukLedState = 1;
14626+ YukLedOn |= PHY_M_LEDC_STA0_CTRL(YukLedState ? 9 : 8);
14627+ YukLedState = 1;
14628+ YukLedOn |= PHY_M_LEDC_LOS_CTRL(YukLedState ? 9 : 8);
14629+
14630+ /* save page register */
14631+ SkGmPhyRead(pAC, IoC, port, PHY_MARV_EXT_ADR, &PageSelect);
14632+
14633+ /* select page 3 for LED control */
14634+ SkGmPhyWrite(pAC, IoC, port, PHY_MARV_EXT_ADR, 3);
14635+
14636+ SkGmPhyWrite(pAC, IoC, port, PHY_MARV_PHY_CTRL, YukLedOn);
14637+
14638+ /* restore page register */
14639+ SkGmPhyWrite(pAC, IoC, port, PHY_MARV_EXT_ADR, PageSelect);
14640+ }
14641+ else {
14642+ SkGmPhyWrite(pAC,IoC,port,PHY_MARV_LED_OVER,YukLedOn);
14643+ }
14644+ }
14645+ } else {
14646+ if (pAC->GIni.GIGenesis) {
14647+
14648+ SK_OUT8(IoC,MR_ADDR(port,LNK_LED_REG),(SK_U8)SK_LNK_OFF);
14649+ SkGeYellowLED(pAC,IoC,LED_OFF >> 1);
14650+ SkGeXmitLED(pAC,IoC,MR_ADDR(port,RX_LED_INI),SK_LED_DIS);
14651+ if (pAC->GIni.GP[port].PhyType == SK_PHY_BCOM) {
14652+ SkXmPhyWrite(pAC,IoC,port,PHY_BCOM_P_EXT_CTRL,PHY_B_PEC_LED_OFF);
14653+ } else if (pAC->GIni.GP[port].PhyType == SK_PHY_LONE) {
14654+ SkXmPhyWrite(pAC,IoC,port,PHY_LONE_LED_CFG,PHY_L_LC_LEDT);
14655+ } else {
14656+ SkGeXmitLED(pAC,IoC,MR_ADDR(port,TX_LED_INI),SK_LED_DIS);
14657+ }
14658+ } else {
14659+ if ( (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL) ||
14660+ (pAC->GIni.GIChipId == CHIP_ID_YUKON_2(pAC)) ||
14661+ (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) ) {
14662+
14663+ YukLedOn = 0;
14664+ YukLedState = 1;
14665+ YukLedOn |= PHY_M_LEDC_INIT_CTRL(YukLedState ? 9 : 8);
14666+ YukLedState = 1;
14667+ YukLedOn |= PHY_M_LEDC_STA1_CTRL(YukLedState ? 9 : 8);
14668+ YukLedState = 1;
14669+ YukLedOn |= PHY_M_LEDC_STA0_CTRL(YukLedState ? 9 : 8);
14670+ YukLedState = 1;
14671+ YukLedOn |= PHY_M_LEDC_LOS_CTRL(YukLedState ? 9 : 8);
14672+
14673+ /* save page register */
14674+ SkGmPhyRead(pAC, IoC, port, PHY_MARV_EXT_ADR, &PageSelect);
14675+
14676+ /* select page 3 for LED control */
14677+ SkGmPhyWrite(pAC, IoC, port, PHY_MARV_EXT_ADR, 3);
14678+
14679+ SkGmPhyWrite(pAC, IoC, port, PHY_MARV_PHY_CTRL, YukLedOff);
14680+
14681+ /* restore page register */
14682+ SkGmPhyWrite(pAC, IoC, port, PHY_MARV_EXT_ADR, PageSelect);
14683+ }
14684+ else {
14685+ SkGmPhyWrite(pAC,IoC,port,PHY_MARV_LED_OVER,YukLedOff);
14686+ }
14687+ }
14688+ }
14689+
14690+ locateNICtimer.function = toggleLeds;
14691+ locateNICtimer.data = (unsigned long) pNet;
14692+ locateNICtimer.expires = jiffies + (HZ/4);
14693+ add_timer(&locateNICtimer);
14694+}
14695+
14696+#ifdef NETIF_F_TSO
14697+/*****************************************************************************
14698+ *
14699+ * SkGeSetTSO - set the TSO parameters
14700+ *
14701+ * Description:
14702+ * This function sets the TSO parameters
14703+ *
14704+ * Returns:
14705+ * ==0: everything fine, no error
14706+ * !=0: the return value is the error code of the failure
14707+ */
14708+int SkGeSetTSO(struct net_device *dev,
14709+ u32 data)
14710 {
14711- return 0x4000;
14712+ DEV_NET *pNet = (DEV_NET*) dev->priv;
14713+ SK_AC *pAC = pNet->pAC;
14714+
14715+ if (CHIP_ID_YUKON_2(pAC)) {
14716+ if (data) {
14717+ dev->features |= NETIF_F_TSO;
14718+ } else {
14719+ dev->features &= ~NETIF_F_TSO;
14720+ }
14721+ return 0;
14722+ }
14723+ return -EOPNOTSUPP;
14724+
14725 }
14726+#endif
14727
14728-/*
14729- * Returns copy of whole control register region
14730- * Note: skip RAM address register because accessing it will
14731- * cause bus hangs!
14732- */
14733-static void getRegs(struct net_device *dev, struct ethtool_regs *regs,
14734- void *p)
14735-{
14736- DEV_NET *pNet = netdev_priv(dev);
14737- const void __iomem *io = pNet->pAC->IoBase;
14738-
14739- regs->version = 1;
14740- memset(p, 0, regs->len);
14741- memcpy_fromio(p, io, B3_RAM_ADDR);
14742-
14743- memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
14744- regs->len - B3_RI_WTO_R1);
14745-}
14746-
14747-const struct ethtool_ops SkGeEthtoolOps = {
14748- .get_settings = getSettings,
14749- .set_settings = setSettings,
14750- .get_drvinfo = getDriverInfo,
14751- .get_strings = getStrings,
14752- .get_stats_count = getStatsCount,
14753- .get_ethtool_stats = getEthtoolStats,
14754- .phys_id = locateDevice,
14755- .get_pauseparam = getPauseParams,
14756- .set_pauseparam = setPauseParams,
14757- .get_link = ethtool_op_get_link,
14758- .get_perm_addr = ethtool_op_get_perm_addr,
14759- .get_sg = ethtool_op_get_sg,
14760- .set_sg = setScatterGather,
14761- .get_tx_csum = ethtool_op_get_tx_csum,
14762- .set_tx_csum = setTxCsum,
14763- .get_rx_csum = getRxCsum,
14764- .set_rx_csum = setRxCsum,
14765- .get_regs = getRegs,
14766- .get_regs_len = getRegsLen,
14767-};
14768+
14769+
14770+
14771+/*******************************************************************************
14772+ *
14773+ * End of file
14774+ *
14775+ ******************************************************************************/
14776diff -ruN linux/drivers/net/sk98lin/skfops.c linux-new/drivers/net/sk98lin/skfops.c
14777--- linux/drivers/net/sk98lin/skfops.c 1970-01-01 01:00:00.000000000 +0100
14778+++ linux-new/drivers/net/sk98lin/skfops.c 2006-10-13 11:18:48.000000000 +0200
14779@@ -0,0 +1,273 @@
14780+/******************************************************************************
14781+ *
14782+ * Name: skfops.c
14783+ * Project: Gigabit Ethernet Adapters, Common Modules
14784+ * Version: $Revision$
14785+ * Date: $Date$
14786+ * Purpose: Kernel mode file read functions.
14787+ *
14788+ ******************************************************************************/
14789+
14790+/******************************************************************************
14791+ *
14792+ * (C)Copyright 1998-2002 SysKonnect GmbH.
14793+ * (C)Copyright 2002-2003 Marvell.
14794+ *
14795+ * This program is free software; you can redistribute it and/or modify
14796+ * it under the terms of the GNU General Public License as published by
14797+ * the Free Software Foundation; either version 2 of the License, or
14798+ * (at your option) any later version.
14799+ *
14800+ * The information in this file is provided "AS IS" without warranty.
14801+ *
14802+ ******************************************************************************/
14803+
14804+/******************************************************************************
14805+ *
14806+ * Description:
14807+ *
14808+ * This module is intended to handle all file read functions
14809+ *
14810+ * Include File Hierarchy:
14811+ *
14812+ * "h/skdrv1st.h"
14813+ * "h/skdrv2nd.h"
14814+ *
14815+ ******************************************************************************/
14816+
14817+/*
14818+ Event queue and dispatcher
14819+*/
14820+#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
14821+static const char SysKonnectFileId[] =
14822+"$Header$" ;
14823+#endif
14824+
14825+#include "h/sktypes.h"
14826+#include "h/skdrv1st.h"
14827+#include "h/skdrv2nd.h"
14828+#include <linux/fs.h>
14829+#include <asm/uaccess.h>
14830+#include <asm/fcntl.h>
14831+
14832+
14833+/********************************************************
14834+ Local Variables
14835+********************************************************/
14836+
14837+
14838+
14839+/********************************************************
14840+ Global Variables
14841+********************************************************/
14842+
14843+
14844+
14845+/********************************************************
14846+ Local Functions
14847+********************************************************/
14848+
14849+/**
14850+ * @brief This function opens/create a file in kernel mode.
14851+ *
14852+ * @param filename Name of the file to be opened
14853+ * @param flags File flags
14854+ * @param mode File permissions
14855+ * @return file pointer if successful or NULL if failed.
14856+ */
14857+static struct file * sk_fopen(const char * filename,
14858+ unsigned int flags,
14859+ int mode)
14860+{
14861+ int orgfsuid, orgfsgid;
14862+ struct file * file_ret;
14863+
14864+ /* Save uid and gid used for filesystem access. */
14865+ orgfsuid = current->fsuid;
14866+ orgfsgid = current->fsgid;
14867+
14868+ /* Set user and group to 0 (root) */
14869+ current->fsuid = 0;
14870+ current->fsgid = 0;
14871+
14872+ /* Open the file in kernel mode */
14873+ file_ret = filp_open(filename, flags, mode);
14874+
14875+ /* Restore the uid and gid */
14876+ current->fsuid = orgfsuid;
14877+ current->fsgid = orgfsgid;
14878+
14879+ /* Check if the file was opened successfully
14880+ and return the file pointer of it was.
14881+ */
14882+ return ((IS_ERR(file_ret)) ? NULL : file_ret);
14883+}
14884+
14885+
14886+
14887+/**
14888+ * @brief This function closes a file in kernel mode.
14889+ *
14890+ * @param file_ptr File pointer
14891+ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
14892+ */
14893+static int sk_fclose(struct file * file_ptr)
14894+{
14895+ int orgfsuid, orgfsgid;
14896+ int file_ret;
14897+
14898+ if((NULL == file_ptr) || (IS_ERR(file_ptr)))
14899+ return -ENOENT;
14900+
14901+ /* Save uid and gid used for filesystem access. */
14902+ orgfsuid = current->fsuid;
14903+ orgfsgid = current->fsgid;
14904+
14905+ /* Set user and group to 0 (root) */
14906+ current->fsuid = 0;
14907+ current->fsgid = 0;
14908+
14909+ /* Close the file in kernel mode (user_id = 0) */
14910+ file_ret = filp_close(file_ptr, 0);
14911+
14912+ /* Restore the uid and gid */
14913+ current->fsuid = orgfsuid;
14914+ current->fsgid = orgfsgid;
14915+
14916+ return (file_ret);
14917+}
14918+
14919+
14920+
14921+/**
14922+ * @brief This function reads data from files in kernel mode.
14923+ *
14924+ * @param file_ptr File pointer
14925+ * @param buf Buffers to read data into
14926+ * @param len Length of buffer
14927+ * @return number of characters read
14928+ */
14929+static int sk_fread(struct file * file_ptr, char * buf, int len)
14930+{
14931+ int orgfsuid, orgfsgid;
14932+ int file_ret;
14933+ mm_segment_t orgfs;
14934+
14935+ /* Check if the file pointer is valid */
14936+ if((NULL == file_ptr) || (IS_ERR(file_ptr)))
14937+ return -ENOENT;
14938+
14939+ /* Check for a valid file read function */
14940+ if(file_ptr->f_op->read == NULL)
14941+ return -ENOSYS;
14942+
14943+ /* Check for access permissions */
14944+ if(((file_ptr->f_flags & O_ACCMODE) & (O_RDONLY | O_RDWR)) == 0)
14945+ return -EACCES;
14946+
14947+ /* Check if there is a valid length */
14948+ if(0 >= len)
14949+ return -EINVAL;
14950+
14951+ /* Save uid and gid used for filesystem access. */
14952+ orgfsuid = current->fsuid;
14953+ orgfsgid = current->fsgid;
14954+
14955+ /* Set user and group to 0 (root) */
14956+ current->fsuid = 0;
14957+ current->fsgid = 0;
14958+
14959+ /* Save FS register and set FS register to kernel
14960+ space, needed for read and write to accept
14961+ buffer in kernel space. */
14962+ orgfs = get_fs();
14963+
14964+ /* Set the FS register to KERNEL mode. */
14965+ set_fs(KERNEL_DS);
14966+
14967+ /* Read the actual data from the file */
14968+ file_ret = file_ptr->f_op->read(file_ptr, buf, len, &file_ptr->f_pos);
14969+
14970+ /* Restore the FS register */
14971+ set_fs(orgfs);
14972+
14973+ /* Restore the uid and gid */
14974+ current->fsuid = orgfsuid;
14975+ current->fsgid = orgfsgid;
14976+
14977+ return (file_ret);
14978+}
14979+
14980+
14981+
14982+/********************************************************
14983+ Global Functions
14984+********************************************************/
14985+
14986+/**
14987+ * @brief This function reads FW/Helper.
14988+ *
14989+ * @param name File name
14990+ * @param addr Pointer to buffer storing FW/Helper
14991+ * @param len Pointer to length of FW/Helper
14992+ * @return WLAN_STATUS_SUCCESS or WLAN_STATUS_FAILURE
14993+ */
14994+SK_BOOL fw_read( SK_AC *pAC, /* Pointer to adapter context */
14995+ char *name, SK_U8 **addr, SK_U32 *len )
14996+{
14997+ struct file *fp;
14998+ SK_BOOL ret;
14999+ SK_U8 *ptr;
15000+
15001+ fp = sk_fopen(name, O_RDWR, 0 );
15002+
15003+ if ( fp == NULL ) {
15004+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, ("fw_read: Could not open file:%s\n", name));
15005+ return SK_FALSE;
15006+ }
15007+
15008+ /*calculate file length*/
15009+ *len = fp->f_dentry->d_inode->i_size - fp->f_pos;
15010+
15011+ ptr = (SK_U8 *)kmalloc( *len, GFP_KERNEL );
15012+
15013+ if ( ptr == NULL ) {
15014+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, ("fw_read: vmalloc failure!\n"));
15015+ return SK_FALSE;
15016+ }
15017+ if(sk_fread(fp, ptr,*len) > 0) {
15018+ *addr = ptr;
15019+ ret = SK_TRUE;
15020+ } else {
15021+ kfree(ptr);
15022+ *addr = NULL;
15023+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, ("fw_read: failed to read file:%s\n", name));
15024+ ret = SK_FALSE;
15025+ }
15026+
15027+ sk_fclose( fp );
15028+ return ret;
15029+}
15030+
15031+
15032+/**
15033+ * @brief This function checks whether the file 'name' exists.
15034+ *
15035+ * @param name File name
15036+ * @return SK_TRUE or SK_FALSE
15037+ */
15038+SK_BOOL fw_file_exists( SK_AC *pAC, /* Pointer to adapter context */
15039+ char *name )
15040+{
15041+ struct file *fp;
15042+
15043+ fp = sk_fopen(name, O_RDONLY | O_LARGEFILE, 0 );
15044+
15045+ if ( fp == NULL ) {
15046+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, ("fw_file_exists: Could not open file:%s\n", name));
15047+ return SK_FALSE;
15048+ }
15049+ sk_fclose( fp );
15050+ return SK_TRUE;
15051+}
15052+
15053diff -ruN linux/drivers/net/sk98lin/skge.c linux-new/drivers/net/sk98lin/skge.c
15054--- linux/drivers/net/sk98lin/skge.c 2007-01-02 23:21:17.000000000 +0100
15055+++ linux-new/drivers/net/sk98lin/skge.c 2006-10-13 11:18:50.000000000 +0200
15056@@ -1,32 +1,26 @@
15057 /******************************************************************************
15058 *
15059- * Name: skge.c
15060- * Project: GEnesis, PCI Gigabit Ethernet Adapter
15061- * Version: $Revision$
15062- * Date: $Date$
15063- * Purpose: The main driver source module
15064+ * Name: skge.c
15065+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
15066+ * Version: $Revision$
15067+ * Date: $Date$
15068+ * Purpose: The main driver source module
15069 *
15070 ******************************************************************************/
15071
15072 /******************************************************************************
15073 *
15074 * (C)Copyright 1998-2002 SysKonnect GmbH.
15075- * (C)Copyright 2002-2003 Marvell.
15076+ * (C)Copyright 2002-2005 Marvell.
15077 *
15078 * Driver for Marvell Yukon chipset and SysKonnect Gigabit Ethernet
15079 * Server Adapters.
15080 *
15081- * Created 10-Feb-1999, based on Linux' acenic.c, 3c59x.c and
15082- * SysKonnects GEnesis Solaris driver
15083- * Author: Christoph Goos (cgoos@syskonnect.de)
15084- * Mirko Lindner (mlindner@syskonnect.de)
15085+ * Author: Mirko Lindner (mlindner@syskonnect.de)
15086+ * Ralph Roesler (rroesler@syskonnect.de)
15087 *
15088 * Address all question to: linux@syskonnect.de
15089 *
15090- * The technical manual for the adapters is available from SysKonnect's
15091- * web pages: www.syskonnect.com
15092- * Goto "Support" and search Knowledge Base for "manual".
15093- *
15094 * This program is free software; you can redistribute it and/or modify
15095 * it under the terms of the GNU General Public License as published by
15096 * the Free Software Foundation; either version 2 of the License, or
15097@@ -38,86 +32,55 @@
15098
15099 /******************************************************************************
15100 *
15101- * Possible compiler options (#define xxx / -Dxxx):
15102- *
15103- * debugging can be enable by changing SK_DEBUG_CHKMOD and
15104- * SK_DEBUG_CHKCAT in makefile (described there).
15105- *
15106- ******************************************************************************/
15107-
15108-/******************************************************************************
15109- *
15110 * Description:
15111 *
15112- * This is the main module of the Linux GE driver.
15113- *
15114- * All source files except skge.c, skdrv1st.h, skdrv2nd.h and sktypes.h
15115- * are part of SysKonnect's COMMON MODULES for the SK-98xx adapters.
15116- * Those are used for drivers on multiple OS', so some thing may seem
15117- * unnecessary complicated on Linux. Please do not try to 'clean up'
15118- * them without VERY good reasons, because this will make it more
15119- * difficult to keep the Linux driver in synchronisation with the
15120- * other versions.
15121- *
15122- * Include file hierarchy:
15123- *
15124- * <linux/module.h>
15125- *
15126- * "h/skdrv1st.h"
15127- * <linux/types.h>
15128- * <linux/kernel.h>
15129- * <linux/string.h>
15130- * <linux/errno.h>
15131- * <linux/ioport.h>
15132- * <linux/slab.h>
15133- * <linux/interrupt.h>
15134- * <linux/pci.h>
15135- * <linux/bitops.h>
15136- * <asm/byteorder.h>
15137- * <asm/io.h>
15138- * <linux/netdevice.h>
15139- * <linux/etherdevice.h>
15140- * <linux/skbuff.h>
15141- * those three depending on kernel version used:
15142- * <linux/bios32.h>
15143- * <linux/init.h>
15144- * <asm/uaccess.h>
15145- * <net/checksum.h>
15146- *
15147- * "h/skerror.h"
15148- * "h/skdebug.h"
15149- * "h/sktypes.h"
15150- * "h/lm80.h"
15151- * "h/xmac_ii.h"
15152- *
15153- * "h/skdrv2nd.h"
15154- * "h/skqueue.h"
15155- * "h/skgehwt.h"
15156- * "h/sktimer.h"
15157- * "h/ski2c.h"
15158- * "h/skgepnmi.h"
15159- * "h/skvpd.h"
15160- * "h/skgehw.h"
15161- * "h/skgeinit.h"
15162- * "h/skaddr.h"
15163- * "h/skgesirq.h"
15164- * "h/skrlmt.h"
15165+ * All source files in this sk98lin directory except of the sk98lin
15166+ * Linux specific files
15167+ *
15168+ * - skdim.c
15169+ * - skethtool.c
15170+ * - skge.c
15171+ * - skproc.c
15172+ * - sky2.c
15173+ * - Makefile
15174+ * - h/skdrv1st.h
15175+ * - h/skdrv2nd.h
15176+ * - h/sktypes.h
15177+ * - h/skversion.h
15178+ *
15179+ * are part of SysKonnect's common modules for the SK-9xxx adapters.
15180+ *
15181+ * Those common module files which are not Linux specific are used to
15182+ * build drivers on different OS' (e.g. Windows, MAC OS) so that those
15183+ * drivers are based on the same set of files
15184+ *
15185+ * At a first glance, this seems to complicate things unnescessarily on
15186+ * Linux, but please do not try to 'clean up' them without VERY good
15187+ * reasons, because this will make it more difficult to keep the sk98lin
15188+ * driver for Linux in synchronisation with the other drivers running on
15189+ * other operating systems.
15190 *
15191 ******************************************************************************/
15192
15193 #include "h/skversion.h"
15194
15195-#include <linux/in.h>
15196 #include <linux/module.h>
15197-#include <linux/moduleparam.h>
15198 #include <linux/init.h>
15199-#include <linux/dma-mapping.h>
15200-#include <linux/ip.h>
15201-#include <linux/mii.h>
15202-#include <linux/mm.h>
15203+#include <linux/ethtool.h>
15204+
15205+#ifdef CONFIG_PROC_FS
15206+#include <linux/proc_fs.h>
15207+#endif
15208
15209 #include "h/skdrv1st.h"
15210 #include "h/skdrv2nd.h"
15211+#include "h/skpcidevid.h"
15212+
15213+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
15214+#include <linux/moduleparam.h>
15215+#endif
15216+
15217+#define ENABLE_FUTURE_ETH
15218
15219 /*******************************************************************************
15220 *
15221@@ -128,62 +91,15 @@
15222 /* for debuging on x86 only */
15223 /* #define BREAKPOINT() asm(" int $3"); */
15224
15225-/* use the transmit hw checksum driver functionality */
15226-#define USE_SK_TX_CHECKSUM
15227-
15228-/* use the receive hw checksum driver functionality */
15229-#define USE_SK_RX_CHECKSUM
15230-
15231-/* use the scatter-gather functionality with sendfile() */
15232-#define SK_ZEROCOPY
15233-
15234-/* use of a transmit complete interrupt */
15235-#define USE_TX_COMPLETE
15236-
15237-/*
15238- * threshold for copying small receive frames
15239- * set to 0 to avoid copying, set to 9001 to copy all frames
15240- */
15241-#define SK_COPY_THRESHOLD 50
15242-
15243-/* number of adapters that can be configured via command line params */
15244-#define SK_MAX_CARD_PARAM 16
15245-
15246-
15247-
15248-/*
15249- * use those defines for a compile-in version of the driver instead
15250- * of command line parameters
15251- */
15252-// #define LINK_SPEED_A {"Auto", }
15253-// #define LINK_SPEED_B {"Auto", }
15254-// #define AUTO_NEG_A {"Sense", }
15255-// #define AUTO_NEG_B {"Sense", }
15256-// #define DUP_CAP_A {"Both", }
15257-// #define DUP_CAP_B {"Both", }
15258-// #define FLOW_CTRL_A {"SymOrRem", }
15259-// #define FLOW_CTRL_B {"SymOrRem", }
15260-// #define ROLE_A {"Auto", }
15261-// #define ROLE_B {"Auto", }
15262-// #define PREF_PORT {"A", }
15263-// #define CON_TYPE {"Auto", }
15264-// #define RLMT_MODE {"CheckLinkState", }
15265-
15266-#define DEV_KFREE_SKB(skb) dev_kfree_skb(skb)
15267-#define DEV_KFREE_SKB_IRQ(skb) dev_kfree_skb_irq(skb)
15268-#define DEV_KFREE_SKB_ANY(skb) dev_kfree_skb_any(skb)
15269-
15270
15271 /* Set blink mode*/
15272 #define OEM_CONFIG_VALUE ( SK_ACT_LED_BLINK | \
15273 SK_DUP_LED_NORMAL | \
15274 SK_LED_LINK100_ON)
15275
15276-
15277-/* Isr return value */
15278-#define SkIsrRetVar irqreturn_t
15279-#define SkIsrRetNone IRQ_NONE
15280-#define SkIsrRetHandled IRQ_HANDLED
15281+#define CLEAR_AND_START_RX(Port) SK_OUT8(pAC->IoBase, RxQueueAddr[(Port)]+Q_CSR, CSR_START | CSR_IRQ_CL_F)
15282+#define START_RX(Port) SK_OUT8(pAC->IoBase, RxQueueAddr[(Port)]+Q_CSR, CSR_START)
15283+#define CLEAR_TX_IRQ(Port,Prio) SK_OUT8(pAC->IoBase, TxQueueAddr[(Port)][(Prio)]+Q_CSR, CSR_IRQ_CL_F)
15284
15285
15286 /*******************************************************************************
15287@@ -192,14 +108,31 @@
15288 *
15289 ******************************************************************************/
15290
15291+static int __devinit sk98lin_init_device(struct pci_dev *pdev, const struct pci_device_id *ent);
15292+static void sk98lin_remove_device(struct pci_dev *pdev);
15293+#ifdef CONFIG_PM
15294+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
15295+static int sk98lin_suspend(struct pci_dev *pdev, pm_message_t state);
15296+#else
15297+static int sk98lin_suspend(struct pci_dev *pdev, SK_U32 state);
15298+#endif
15299+static int sk98lin_resume(struct pci_dev *pdev);
15300+static void SkEnableWOMagicPacket(SK_AC *pAC, SK_IOC IoC, SK_MAC_ADDR MacAddr);
15301+#endif
15302+#ifdef Y2_RECOVERY
15303+static void SkGeHandleKernelTimer(unsigned long ptr);
15304+void SkGeCheckTimer(DEV_NET *pNet);
15305+static SK_BOOL CheckRXCounters(DEV_NET *pNet);
15306+static void CheckRxPath(DEV_NET *pNet);
15307+#endif
15308 static void FreeResources(struct SK_NET_DEVICE *dev);
15309 static int SkGeBoardInit(struct SK_NET_DEVICE *dev, SK_AC *pAC);
15310 static SK_BOOL BoardAllocMem(SK_AC *pAC);
15311 static void BoardFreeMem(SK_AC *pAC);
15312 static void BoardInitMem(SK_AC *pAC);
15313-static void SetupRing(SK_AC*, void*, uintptr_t, RXD**, RXD**, RXD**, int*, SK_BOOL);
15314-static SkIsrRetVar SkGeIsr(int irq, void *dev_id);
15315-static SkIsrRetVar SkGeIsrOnePort(int irq, void *dev_id);
15316+static void SetupRing(SK_AC*, void*, uintptr_t, RXD**, RXD**, RXD**, int*, int*, SK_BOOL);
15317+static SkIsrRetVar SkGeIsr(int irq, void *dev_id);
15318+static SkIsrRetVar SkGeIsrOnePort(int irq, void *dev_id);
15319 static int SkGeOpen(struct SK_NET_DEVICE *dev);
15320 static int SkGeClose(struct SK_NET_DEVICE *dev);
15321 static int SkGeXmit(struct sk_buff *skb, struct SK_NET_DEVICE *dev);
15322@@ -208,128 +141,1103 @@
15323 static struct net_device_stats *SkGeStats(struct SK_NET_DEVICE *dev);
15324 static int SkGeIoctl(struct SK_NET_DEVICE *dev, struct ifreq *rq, int cmd);
15325 static void GetConfiguration(SK_AC*);
15326+static void ProductStr(SK_AC*);
15327 static int XmitFrame(SK_AC*, TX_PORT*, struct sk_buff*);
15328 static void FreeTxDescriptors(SK_AC*pAC, TX_PORT*);
15329 static void FillRxRing(SK_AC*, RX_PORT*);
15330 static SK_BOOL FillRxDescriptor(SK_AC*, RX_PORT*);
15331+#ifdef CONFIG_SK98LIN_NAPI
15332+static int SkGePoll(struct net_device *dev, int *budget);
15333+static void ReceiveIrq(SK_AC*, RX_PORT*, SK_BOOL, int*, int);
15334+#else
15335 static void ReceiveIrq(SK_AC*, RX_PORT*, SK_BOOL);
15336-static void ClearAndStartRx(SK_AC*, int);
15337-static void ClearTxIrq(SK_AC*, int, int);
15338+#endif
15339+#ifdef SK_POLL_CONTROLLER
15340+static void SkGeNetPoll(struct SK_NET_DEVICE *dev);
15341+#endif
15342 static void ClearRxRing(SK_AC*, RX_PORT*);
15343 static void ClearTxRing(SK_AC*, TX_PORT*);
15344 static int SkGeChangeMtu(struct SK_NET_DEVICE *dev, int new_mtu);
15345 static void PortReInitBmu(SK_AC*, int);
15346 static int SkGeIocMib(DEV_NET*, unsigned int, int);
15347 static int SkGeInitPCI(SK_AC *pAC);
15348-static void StartDrvCleanupTimer(SK_AC *pAC);
15349-static void StopDrvCleanupTimer(SK_AC *pAC);
15350+static SK_U32 ParseDeviceNbrFromSlotName(const char *SlotName);
15351+static int SkDrvInitAdapter(SK_AC *pAC, int devNbr);
15352+static int SkDrvDeInitAdapter(SK_AC *pAC, int devNbr);
15353+extern void SkLocalEventQueue( SK_AC *pAC,
15354+ SK_U32 Class,
15355+ SK_U32 Event,
15356+ SK_U32 Param1,
15357+ SK_U32 Param2,
15358+ SK_BOOL Flag);
15359+extern void SkLocalEventQueue64( SK_AC *pAC,
15360+ SK_U32 Class,
15361+ SK_U32 Event,
15362+ SK_U64 Param,
15363+ SK_BOOL Flag);
15364+
15365 static int XmitFrameSG(SK_AC*, TX_PORT*, struct sk_buff*);
15366
15367-#ifdef SK_DIAG_SUPPORT
15368-static SK_U32 ParseDeviceNbrFromSlotName(const char *SlotName);
15369-static int SkDrvInitAdapter(SK_AC *pAC, int devNbr);
15370-static int SkDrvDeInitAdapter(SK_AC *pAC, int devNbr);
15371-#endif
15372+/*******************************************************************************
15373+ *
15374+ * Extern Function Prototypes
15375+ *
15376+ ******************************************************************************/
15377+
15378+extern SK_BOOL SkY2AllocateResources(SK_AC *pAC);
15379+extern void SkY2FreeResources(SK_AC *pAC);
15380+extern void SkY2AllocateRxBuffers(SK_AC *pAC,SK_IOC IoC,int Port);
15381+extern void SkY2FreeRxBuffers(SK_AC *pAC,SK_IOC IoC,int Port);
15382+extern void SkY2FreeTxBuffers(SK_AC *pAC,SK_IOC IoC,int Port);
15383+extern SkIsrRetVar SkY2Isr(int irq,void *dev_id);
15384+extern int SkY2Xmit(struct sk_buff *skb,struct SK_NET_DEVICE *dev);
15385+extern void SkY2PortStop(SK_AC *pAC,SK_IOC IoC,int Port,int Dir,int RstMode);
15386+extern void SkY2PortStart(SK_AC *pAC,SK_IOC IoC,int Port);
15387+extern int SkY2RlmtSend(SK_AC *pAC,int PortNr,struct sk_buff *pMessage);
15388+extern void SkY2RestartStatusUnit(SK_AC *pAC);
15389+extern void FillReceiveTableYukon2(SK_AC *pAC,SK_IOC IoC,int Port);
15390+#ifdef CONFIG_SK98LIN_NAPI
15391+extern int SkY2Poll(struct net_device *dev, int *budget);
15392+#endif
15393+
15394+extern void SkDimEnableModerationIfNeeded(SK_AC *pAC);
15395+extern void SkDimStartModerationTimer(SK_AC *pAC);
15396+extern void SkDimModerate(SK_AC *pAC);
15397+
15398+#ifndef ENABLE_FUTURE_ETH
15399+extern int SkEthIoctl(struct net_device *netdev, struct ifreq *ifr);
15400+#else
15401+/* Ethtool functions */
15402+extern int SkGeGetSettings(struct net_device *dev, struct ethtool_cmd *ecmd);
15403+extern void SkGeGetDrvInfo(struct net_device *dev, struct ethtool_drvinfo *ecmd);
15404+extern void SkGeGetWolSettings(struct net_device *dev, struct ethtool_wolinfo *ecmd);
15405+extern void SkGeGetPauseParam(struct net_device *dev, struct ethtool_pauseparam *ecmd);
15406+extern int SkGeGetCoalesce(struct net_device *dev, struct ethtool_coalesce *ecmd);
15407+extern SK_U32 SkGeGetRxCsum(struct net_device *dev);
15408+extern void SkGeGetStrings(struct net_device *dev, u32 stringset, u8 *strings);
15409+extern int SkGeGetStatsLen(struct net_device *dev);
15410+extern void SkGeGetEthStats(struct net_device *dev, struct ethtool_stats *stats, u64 *data);
15411+extern int SkGeSetSettings(struct net_device *dev, struct ethtool_cmd *ecmd);
15412+extern int SkGeSetWolSettings(struct net_device *dev, struct ethtool_wolinfo *ewol);
15413+extern int SkGeSetPauseParam(struct net_device *dev, struct ethtool_pauseparam *ecmd);
15414+extern int SkGeSetCoalesce(struct net_device *dev, struct ethtool_coalesce *ecmd);
15415+extern int SkGeSetSG(struct net_device *dev, u32 data);
15416+extern int SkGeSetTxCsum(struct net_device *dev, u32 data);
15417+extern int SkGeSetRxCsum(struct net_device *dev, u32 data);
15418+extern int SkGePhysId(struct net_device *dev, u32 data);
15419+#endif
15420+
15421+#ifdef NETIF_F_TSO
15422+extern int SkGeSetTSO(struct net_device *netdev, u32 data);
15423+#endif
15424+
15425+#ifdef CONFIG_PROC_FS
15426+static const char SK_Root_Dir_entry[] = "sk98lin";
15427+static struct proc_dir_entry *pSkRootDir;
15428+extern struct file_operations sk_proc_fops;
15429+#endif
15430+
15431+#ifdef DEBUG
15432+static void DumpMsg(struct sk_buff*, char*);
15433+static void DumpData(char*, int);
15434+static void DumpLong(char*, int);
15435+#endif
15436+
15437+/* global variables *********************************************************/
15438+static const char *BootString = BOOT_STRING;
15439+struct SK_NET_DEVICE *SkGeRootDev = NULL;
15440+static SK_BOOL DoPrintInterfaceChange = SK_TRUE;
15441+
15442+/* local variables **********************************************************/
15443+static uintptr_t TxQueueAddr[SK_MAX_MACS][2] = {{0x680, 0x600},{0x780, 0x700}};
15444+static uintptr_t RxQueueAddr[SK_MAX_MACS] = {0x400, 0x480};
15445+static int sk98lin_max_boards_found = 0;
15446+static int is_closed = 0;
15447+
15448+#ifdef CONFIG_PROC_FS
15449+static struct proc_dir_entry *pSkRootDir;
15450+#endif
15451+
15452+
15453+
15454+#ifdef ENABLE_FUTURE_ETH
15455+static struct ethtool_ops sk98lin_ethtool_ops = {
15456+ .get_sg = ethtool_op_get_sg,
15457+ .get_link = ethtool_op_get_link,
15458+ .get_tx_csum = ethtool_op_get_tx_csum,
15459+ .get_tx_csum = ethtool_op_get_tx_csum,
15460+/* .get_perm_addr = ethtool_op_get_perm_addr, */
15461+ .get_settings = SkGeGetSettings,
15462+ .get_drvinfo = SkGeGetDrvInfo,
15463+ .get_wol = SkGeGetWolSettings,
15464+ .get_pauseparam = SkGeGetPauseParam,
15465+ .get_coalesce = SkGeGetCoalesce,
15466+ .get_rx_csum = SkGeGetRxCsum,
15467+ .get_strings = SkGeGetStrings,
15468+ .get_stats_count = SkGeGetStatsLen,
15469+ .get_ethtool_stats = SkGeGetEthStats,
15470+
15471+ .set_settings = SkGeSetSettings,
15472+ .set_wol = SkGeSetWolSettings,
15473+ .set_pauseparam = SkGeSetPauseParam,
15474+ .set_coalesce = SkGeSetCoalesce,
15475+ .set_sg = SkGeSetSG,
15476+ .set_tx_csum = SkGeSetTxCsum,
15477+ .set_rx_csum = SkGeSetRxCsum,
15478+
15479+ .phys_id = SkGePhysId,
15480+
15481+#ifdef NETIF_F_TSO
15482+ .get_tso = ethtool_op_get_tso,
15483+ .set_tso = SkGeSetTSO,
15484+#endif
15485+
15486+/* .get_regs_len = */
15487+/* .get_regs = */
15488+/* .get_msglevel = */
15489+/* .nway_reset = */
15490+/* .get_ringparam = */
15491+/* .set_msglevel = */
15492+/* .set_ringparam = */
15493+};
15494+#endif
15495+
15496+MODULE_DEVICE_TABLE(pci, sk98lin_pci_tbl);
15497+
15498+static struct pci_driver sk98lin_driver = {
15499+ .name = DRIVER_FILE_NAME,
15500+ .id_table = sk98lin_pci_tbl,
15501+ .probe = sk98lin_init_device,
15502+ .remove = __devexit_p(sk98lin_remove_device),
15503+#ifdef CONFIG_PM
15504+ .suspend = sk98lin_suspend,
15505+ .resume = sk98lin_resume
15506+#endif
15507+};
15508+
15509+
15510+/*****************************************************************************
15511+ *
15512+ * sk98lin_init_device - initialize the adapter
15513+ *
15514+ * Description:
15515+ * This function initializes the adapter. Resources for
15516+ * the adapter are allocated and the adapter is brought into Init 1
15517+ * state.
15518+ *
15519+ * Returns:
15520+ * 0, if everything is ok
15521+ * !=0, on error
15522+ */
15523+static int __devinit sk98lin_init_device(struct pci_dev *pdev,
15524+ const struct pci_device_id *ent)
15525+
15526+{
15527+ static SK_BOOL sk98lin_boot_string = SK_FALSE;
15528+ static SK_BOOL sk98lin_proc_entry = SK_FALSE;
15529+ static int sk98lin_boards_found = 0;
15530+ SK_AC *pAC;
15531+ DEV_NET *pNet = NULL;
15532+ struct SK_NET_DEVICE *dev = NULL;
15533+ int retval;
15534+#ifdef CONFIG_PROC_FS
15535+#endif
15536+ int pci_using_dac;
15537+
15538+ retval = pci_enable_device(pdev);
15539+ if (retval) {
15540+ printk(KERN_ERR "Cannot enable PCI device, "
15541+ "aborting.\n");
15542+ return retval;
15543+ }
15544+
15545+ dev = NULL;
15546+ pNet = NULL;
15547+
15548+ /* INSERT * We have to find the power-management capabilities */
15549+ /* Find power-management capability. */
15550+
15551+ pci_using_dac = 0; /* Set 32 bit DMA per default */
15552+ /* Configure DMA attributes. */
15553+ retval = pci_set_dma_mask(pdev, (u64) 0xffffffffffffffffULL);
15554+ if (!retval) {
15555+ pci_using_dac = 1;
15556+ } else {
15557+ retval = pci_set_dma_mask(pdev, (u64) 0xffffffff);
15558+ if (retval) {
15559+ printk(KERN_ERR "No usable DMA configuration, "
15560+ "aborting.\n");
15561+ return retval;
15562+ }
15563+ }
15564+
15565+
15566+ if ((dev = alloc_etherdev(sizeof(DEV_NET))) == NULL) {
15567+ printk(KERN_ERR "Unable to allocate etherdev "
15568+ "structure!\n");
15569+ return -ENODEV;
15570+ }
15571+
15572+ pNet = dev->priv;
15573+ pNet->pAC = kmalloc(sizeof(SK_AC), GFP_KERNEL);
15574+ if (pNet->pAC == NULL){
15575+ free_netdev(dev);
15576+ printk(KERN_ERR "Unable to allocate adapter "
15577+ "structure!\n");
15578+ return -ENODEV;
15579+ }
15580+
15581+ /* Print message */
15582+ if (!sk98lin_boot_string) {
15583+ /* set display flag to TRUE so that */
15584+ /* we only display this string ONCE */
15585+ sk98lin_boot_string = SK_TRUE;
15586+ printk("%s\n", BootString);
15587+ }
15588+
15589+ memset(pNet->pAC, 0, sizeof(SK_AC));
15590+ pAC = pNet->pAC;
15591+ pAC->PciDev = pdev;
15592+ pAC->PciDevId = pdev->device;
15593+ pAC->dev[0] = dev;
15594+ pAC->dev[1] = dev;
15595+ sprintf(pAC->Name, "SysKonnect SK-98xx");
15596+ pAC->CheckQueue = SK_FALSE;
15597+ pAC->InterfaceUp[0] = 0;
15598+ pAC->InterfaceUp[1] = 0;
15599+ dev->irq = pdev->irq;
15600+ retval = SkGeInitPCI(pAC);
15601+ if (retval) {
15602+ printk("SKGE: PCI setup failed: %i\n", retval);
15603+ free_netdev(dev);
15604+ return -ENODEV;
15605+ }
15606+
15607+ SET_MODULE_OWNER(dev);
15608+#ifdef ENABLE_FUTURE_ETH
15609+ SET_ETHTOOL_OPS(dev, &sk98lin_ethtool_ops);
15610+#endif
15611+
15612+ dev->open = &SkGeOpen;
15613+ dev->stop = &SkGeClose;
15614+ dev->get_stats = &SkGeStats;
15615+ dev->set_multicast_list = &SkGeSetRxMode;
15616+ dev->set_mac_address = &SkGeSetMacAddr;
15617+ dev->do_ioctl = &SkGeIoctl;
15618+ dev->change_mtu = &SkGeChangeMtu;
15619+ dev->flags &= ~IFF_RUNNING;
15620+#ifdef SK_POLL_CONTROLLER
15621+ dev->poll_controller = SkGeNetPoll;
15622+#endif
15623+ SET_NETDEV_DEV(dev, &pdev->dev);
15624+
15625+ pAC->Index = sk98lin_boards_found;
15626+
15627+ if (SkGeBoardInit(dev, pAC)) {
15628+ free_netdev(dev);
15629+ return -ENODEV;
15630+ } else {
15631+ ProductStr(pAC);
15632+ }
15633+
15634+ if (pci_using_dac)
15635+ dev->features |= NETIF_F_HIGHDMA;
15636+
15637+ /* shifter to later moment in time... */
15638+ if (CHIP_ID_YUKON_2(pAC)) {
15639+ dev->hard_start_xmit = &SkY2Xmit;
15640+#ifdef CONFIG_SK98LIN_NAPI
15641+ dev->poll = &SkY2Poll;
15642+ dev->weight = 64;
15643+#endif
15644+ } else {
15645+ dev->hard_start_xmit = &SkGeXmit;
15646+#ifdef CONFIG_SK98LIN_NAPI
15647+ dev->poll = &SkGePoll;
15648+ dev->weight = 64;
15649+#endif
15650+ }
15651+
15652+#ifdef NETIF_F_TSO
15653+#ifdef USE_SK_TSO_FEATURE
15654+ if ((CHIP_ID_YUKON_2(pAC)) &&
15655+ (pAC->GIni.GIChipId != CHIP_ID_YUKON_EC_U)) {
15656+ dev->features |= NETIF_F_TSO;
15657+ }
15658+#endif
15659+#endif
15660+#ifdef CONFIG_SK98LIN_ZEROCOPY
15661+ if (pAC->GIni.GIChipId != CHIP_ID_GENESIS)
15662+ dev->features |= NETIF_F_SG;
15663+#endif
15664+#ifdef USE_SK_TX_CHECKSUM
15665+ if (pAC->GIni.GIChipId != CHIP_ID_GENESIS)
15666+ dev->features |= NETIF_F_IP_CSUM;
15667+#endif
15668+#ifdef USE_SK_RX_CHECKSUM
15669+ pAC->RxPort[0].UseRxCsum = SK_TRUE;
15670+ if (pAC->GIni.GIMacsFound == 2 ) {
15671+ pAC->RxPort[1].UseRxCsum = SK_TRUE;
15672+ }
15673+#endif
15674+
15675+ /* Save the hardware revision */
15676+ pAC->HWRevision = (((pAC->GIni.GIPciHwRev >> 4) & 0x0F)*10) +
15677+ (pAC->GIni.GIPciHwRev & 0x0F);
15678+
15679+ /* Set driver globals */
15680+ pAC->Pnmi.pDriverFileName = DRIVER_FILE_NAME;
15681+ pAC->Pnmi.pDriverReleaseDate = DRIVER_REL_DATE;
15682+
15683+ SK_MEMSET(&(pAC->PnmiBackup), 0, sizeof(SK_PNMI_STRUCT_DATA));
15684+ SK_MEMCPY(&(pAC->PnmiBackup), &(pAC->PnmiStruct),
15685+ sizeof(SK_PNMI_STRUCT_DATA));
15686+
15687+ /* Register net device */
15688+ retval = register_netdev(dev);
15689+ if (retval) {
15690+ printk(KERN_ERR "SKGE: Could not register device.\n");
15691+ FreeResources(dev);
15692+ free_netdev(dev);
15693+ return retval;
15694+ }
15695+
15696+ /* Save initial device name */
15697+ strcpy(pNet->InitialDevName, dev->name);
15698+
15699+ /* Set network to off */
15700+ netif_stop_queue(dev);
15701+ netif_carrier_off(dev);
15702+
15703+ /* Print adapter specific string from vpd and config settings */
15704+ printk("%s: %s\n", pNet->InitialDevName, pAC->DeviceStr);
15705+ printk(" PrefPort:%c RlmtMode:%s\n",
15706+ 'A' + pAC->Rlmt.Net[0].Port[pAC->Rlmt.Net[0].PrefPort]->PortNumber,
15707+ (pAC->RlmtMode==0) ? "Check Link State" :
15708+ ((pAC->RlmtMode==1) ? "Check Link State" :
15709+ ((pAC->RlmtMode==3) ? "Check Local Port" :
15710+ ((pAC->RlmtMode==7) ? "Check Segmentation" :
15711+ ((pAC->RlmtMode==17) ? "Dual Check Link State" :"Error")))));
15712+
15713+ SkGeYellowLED(pAC, pAC->IoBase, 1);
15714+
15715+ memcpy((caddr_t) &dev->dev_addr,
15716+ (caddr_t) &pAC->Addr.Net[0].CurrentMacAddress, 6);
15717+
15718+ /* First adapter... Create proc and print message */
15719+#ifdef CONFIG_PROC_FS
15720+ if (!sk98lin_proc_entry) {
15721+ sk98lin_proc_entry = SK_TRUE;
15722+ SK_MEMCPY(&SK_Root_Dir_entry, BootString,
15723+ sizeof(SK_Root_Dir_entry) - 1);
15724+
15725+ /*Create proc (directory)*/
15726+ if(!pSkRootDir) {
15727+ pSkRootDir = proc_mkdir(SK_Root_Dir_entry, proc_net);
15728+ if (!pSkRootDir) {
15729+ printk(KERN_WARNING "%s: Unable to create /proc/net/%s",
15730+ dev->name, SK_Root_Dir_entry);
15731+ } else {
15732+ pSkRootDir->owner = THIS_MODULE;
15733+ }
15734+ }
15735+ }
15736+
15737+ /* Create proc file */
15738+ /* No further proc file creation here */
15739+
15740+#endif
15741+
15742+ pNet->PortNr = 0;
15743+ pNet->NetNr = 0;
15744+
15745+ sk98lin_boards_found++;
15746+ pci_set_drvdata(pdev, dev);
15747+
15748+ /* More then one port found */
15749+ if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
15750+ if ((dev = alloc_etherdev(sizeof(DEV_NET))) == 0) {
15751+ printk(KERN_ERR "Unable to allocate etherdev "
15752+ "structure!\n");
15753+ return -ENODEV;
15754+ }
15755+
15756+ pAC->dev[1] = dev;
15757+ pNet = dev->priv;
15758+ pNet->PortNr = 1;
15759+ pNet->NetNr = 1;
15760+ pNet->pAC = pAC;
15761+
15762+ if (CHIP_ID_YUKON_2(pAC)) {
15763+ dev->hard_start_xmit = &SkY2Xmit;
15764+#ifdef CONFIG_SK98LIN_NAPI
15765+ dev->poll = &SkY2Poll;
15766+ dev->weight = 64;
15767+#endif
15768+ } else {
15769+ dev->hard_start_xmit = &SkGeXmit;
15770+#ifdef CONFIG_SK98LIN_NAPI
15771+ dev->poll = &SkGePoll;
15772+ dev->weight = 64;
15773+#endif
15774+ }
15775+
15776+#ifdef ENABLE_FUTURE_ETH
15777+ SET_ETHTOOL_OPS(dev, &sk98lin_ethtool_ops);
15778+#endif
15779+
15780+ dev->open = &SkGeOpen;
15781+ dev->stop = &SkGeClose;
15782+ dev->get_stats = &SkGeStats;
15783+ dev->set_multicast_list = &SkGeSetRxMode;
15784+ dev->set_mac_address = &SkGeSetMacAddr;
15785+ dev->do_ioctl = &SkGeIoctl;
15786+ dev->change_mtu = &SkGeChangeMtu;
15787+ dev->flags &= ~IFF_RUNNING;
15788+#ifdef SK_POLL_CONTROLLER
15789+ dev->poll_controller = SkGeNetPoll;
15790+#endif
15791+
15792+#ifdef NETIF_F_TSO
15793+#ifdef USE_SK_TSO_FEATURE
15794+ if ((CHIP_ID_YUKON_2(pAC)) &&
15795+ (pAC->GIni.GIChipId != CHIP_ID_YUKON_EC_U)) {
15796+ dev->features |= NETIF_F_TSO;
15797+ }
15798+#endif
15799+#endif
15800+#ifdef CONFIG_SK98LIN_ZEROCOPY
15801+ /* Don't handle if Genesis chipset */
15802+ if (pAC->GIni.GIChipId != CHIP_ID_GENESIS)
15803+ dev->features |= NETIF_F_SG;
15804+#endif
15805+#ifdef USE_SK_TX_CHECKSUM
15806+ /* Don't handle if Genesis chipset */
15807+ if (pAC->GIni.GIChipId != CHIP_ID_GENESIS)
15808+ dev->features |= NETIF_F_IP_CSUM;
15809+#endif
15810+
15811+ if (register_netdev(dev)) {
15812+ printk(KERN_ERR "SKGE: Could not register device.\n");
15813+ free_netdev(dev);
15814+ pAC->dev[1] = pAC->dev[0];
15815+ } else {
15816+
15817+ /* Save initial device name */
15818+ strcpy(pNet->InitialDevName, dev->name);
15819+
15820+ /* Set network to off */
15821+ netif_stop_queue(dev);
15822+ netif_carrier_off(dev);
15823+
15824+
15825+#ifdef CONFIG_PROC_FS
15826+ /* No further proc file creation here */
15827+#endif
15828+
15829+ memcpy((caddr_t) &dev->dev_addr,
15830+ (caddr_t) &pAC->Addr.Net[1].CurrentMacAddress, 6);
15831+
15832+ printk("%s: %s\n", pNet->InitialDevName, pAC->DeviceStr);
15833+ printk(" PrefPort:B RlmtMode:Dual Check Link State\n");
15834+ }
15835+ }
15836+
15837+ pAC->Index = sk98lin_boards_found;
15838+ sk98lin_max_boards_found = sk98lin_boards_found;
15839+ return 0;
15840+}
15841+
15842+
15843+
15844+/*****************************************************************************
15845+ *
15846+ * SkGeInitPCI - Init the PCI resources
15847+ *
15848+ * Description:
15849+ * This function initialize the PCI resources and IO
15850+ *
15851+ * Returns: N/A
15852+ *
15853+ */
15854+static int SkGeInitPCI(SK_AC *pAC)
15855+{
15856+ struct SK_NET_DEVICE *dev = pAC->dev[0];
15857+ struct pci_dev *pdev = pAC->PciDev;
15858+ int retval;
15859+
15860+ if (pci_enable_device(pdev) != 0) {
15861+ return 1;
15862+ }
15863+
15864+ dev->mem_start = pci_resource_start (pdev, 0);
15865+ pci_set_master(pdev);
15866+
15867+ if (pci_request_regions(pdev, DRIVER_FILE_NAME) != 0) {
15868+ retval = 2;
15869+ goto out_disable;
15870+ }
15871+
15872+#ifdef SK_BIG_ENDIAN
15873+ /*
15874+ * On big endian machines, we use the adapter's aibility of
15875+ * reading the descriptors as big endian.
15876+ */
15877+ {
15878+ SK_U32 our2;
15879+ SkPciReadCfgDWord(pAC, PCI_OUR_REG_2, &our2);
15880+ our2 |= PCI_REV_DESC;
15881+ SkPciWriteCfgDWord(pAC, PCI_OUR_REG_2, our2);
15882+ }
15883+#endif
15884+
15885+ /*
15886+ * Remap the regs into kernel space.
15887+ */
15888+ pAC->IoBase = (char*)ioremap_nocache(dev->mem_start, 0x4000);
15889+
15890+ if (!pAC->IoBase){
15891+ retval = 3;
15892+ goto out_release;
15893+ }
15894+
15895+ return 0;
15896+
15897+ out_release:
15898+ pci_release_regions(pdev);
15899+ out_disable:
15900+ pci_disable_device(pdev);
15901+ return retval;
15902+}
15903+
15904+#ifdef CONFIG_PROC_FS
15905+/*****************************************************************************
15906+ *
15907+ * SkGeHandleProcfsTimer - Handle the procfs timer requests
15908+ *
15909+ * Description:
15910+ * Checks, if the device's name changed. If this is the case
15911+ * it deletes the old profs entry and creates a new one with
15912+ * the new name.
15913+ *
15914+ * Returns: N/A
15915+ *
15916+ */
15917+static void SkGeHandleProcfsTimer(unsigned long ptr)
15918+{
15919+ DEV_NET *pNet = (DEV_NET*) ptr;
15920+ struct proc_dir_entry *pProcFile;
15921+
15922+ /*
15923+ * If the current name and the last saved name of the device differ
15924+ * we need to update our procfs entry.
15925+ */
15926+ if ( (pSkRootDir) &&
15927+ (strcmp(pNet->CurrentName, pNet->pAC->dev[pNet->NetNr]->name) != 0) ) {
15928+
15929+ if (pNet->pAC->InterfaceUp[pNet->NetNr] == 1)
15930+ remove_proc_entry(pNet->CurrentName, pSkRootDir);
15931+
15932+ /*
15933+ * InterfaceUp only holds 1 if both the network interface is up and
15934+ * the corresponding procfs entry is done. Otherwise it is set to 0.
15935+ */
15936+ pNet->pAC->InterfaceUp[pNet->NetNr] = 0;
15937+
15938+ pProcFile = create_proc_entry(pNet->pAC->dev[pNet->NetNr]->name, S_IRUGO, pSkRootDir);
15939+ pProcFile->proc_fops = &sk_proc_fops;
15940+ pProcFile->data = pNet->pAC->dev[pNet->NetNr];
15941+
15942+ /*
15943+ * Remember, interface dev nr pNet->NetNr is up and procfs entry is created.
15944+ */
15945+ pNet->pAC->InterfaceUp[pNet->NetNr] = 1;
15946+
15947+ strcpy(pNet->CurrentName, pNet->pAC->dev[pNet->NetNr]->name);
15948+ }
15949+
15950+ /*
15951+ * Restart Procfs Timer
15952+ */
15953+ pNet->ProcfsTimer.expires = jiffies + HZ*5; /* 5 secs */
15954+ add_timer(&pNet->ProcfsTimer);
15955+}
15956+#endif
15957+
15958+#ifdef Y2_RECOVERY
15959+/*****************************************************************************
15960+ *
15961+ * SkGeHandleKernelTimer - Handle the kernel timer requests
15962+ *
15963+ * Description:
15964+ * If the requested time interval for the timer has elapsed,
15965+ * this function checks the link state.
15966+ *
15967+ * Returns: N/A
15968+ *
15969+ */
15970+static void SkGeHandleKernelTimer(
15971+unsigned long ptr) /* holds the pointer to adapter control context */
15972+{
15973+ DEV_NET *pNet = (DEV_NET*) ptr;
15974+ SkGeCheckTimer(pNet);
15975+}
15976+
15977+/*****************************************************************************
15978+ *
15979+ * sk98lin_check_timer - Resume the the card
15980+ *
15981+ * Description:
15982+ * This function checks the kernel timer
15983+ *
15984+ * Returns: N/A
15985+ *
15986+ */
15987+void SkGeCheckTimer(
15988+DEV_NET *pNet) /* holds the pointer to adapter control context */
15989+{
15990+ SK_AC *pAC = pNet->pAC;
15991+ SK_BOOL StartTimer = SK_TRUE;
15992+
15993+ if (pNet->InRecover)
15994+ return;
15995+ if (pNet->TimerExpired)
15996+ return;
15997+ pNet->TimerExpired = SK_TRUE;
15998+
15999+#define TXPORT pAC->TxPort[pNet->PortNr][TX_PRIO_LOW]
16000+#define RXPORT pAC->RxPort[pNet->PortNr]
16001+
16002+ if ( (CHIP_ID_YUKON_2(pAC)) &&
16003+ (netif_running(pAC->dev[pNet->PortNr]))) {
16004+
16005+#ifdef Y2_RX_CHECK
16006+ if (HW_FEATURE(pAC, HWF_WA_DEV_4167)) {
16007+ /* Checks the RX path */
16008+ CheckRxPath(pNet);
16009+ }
16010+#endif
16011+
16012+ /* Checkthe transmitter */
16013+ if (!(IS_Q_EMPTY(&TXPORT.TxAQ_working))) {
16014+ if (TXPORT.LastDone != TXPORT.TxALET.Done) {
16015+ TXPORT.LastDone = TXPORT.TxALET.Done;
16016+ pNet->TransmitTimeoutTimer = 0;
16017+ } else {
16018+ pNet->TransmitTimeoutTimer++;
16019+ if (pNet->TransmitTimeoutTimer >= 10) {
16020+ pNet->TransmitTimeoutTimer = 0;
16021+#ifdef CHECK_TRANSMIT_TIMEOUT
16022+ StartTimer = SK_FALSE;
16023+ SkLocalEventQueue(pAC, SKGE_DRV,
16024+ SK_DRV_RECOVER,pNet->PortNr,-1,SK_FALSE);
16025+#endif
16026+ }
16027+ }
16028+ }
16029+
16030+#ifdef CHECK_TRANSMIT_TIMEOUT
16031+// if (!timer_pending(&pNet->KernelTimer)) {
16032+ pNet->KernelTimer.expires = jiffies + (HZ/4); /* 100ms */
16033+ add_timer(&pNet->KernelTimer);
16034+ pNet->TimerExpired = SK_FALSE;
16035+// }
16036+#endif
16037+ }
16038+}
16039+
16040+
16041+/*****************************************************************************
16042+*
16043+* CheckRXCounters - Checks the the statistics for RX path hang
16044+*
16045+* Description:
16046+* This function is called periodical by a timer.
16047+*
16048+* Notes:
16049+*
16050+* Function Parameters:
16051+*
16052+* Returns:
16053+* Traffic status
16054+*
16055+*/
16056+static SK_BOOL CheckRXCounters(
16057+DEV_NET *pNet) /* holds the pointer to adapter control context */
16058+{
16059+ SK_AC *pAC = pNet->pAC;
16060+ SK_BOOL bStatus = SK_FALSE;
16061+
16062+ /* Variable used to store the MAC RX FIFO RP, RPLev*/
16063+ SK_U32 MACFifoRP = 0;
16064+ SK_U32 MACFifoRLev = 0;
16065+
16066+ /* Variable used to store the PCI RX FIFO RP, RPLev*/
16067+ SK_U32 RXFifoRP = 0;
16068+ SK_U8 RXFifoRLev = 0;
16069+
16070+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
16071+ ("==> CheckRXCounters()\n"));
16072+
16073+ /*Check if statistic counters hangs*/
16074+ if (pNet->LastJiffies == pAC->dev[pNet->PortNr]->last_rx) {
16075+ /* Now read the values of read pointer/level from MAC RX FIFO again */
16076+ SK_IN32(pAC->IoBase, MR_ADDR(pNet->PortNr, RX_GMF_RP), &MACFifoRP);
16077+ SK_IN32(pAC->IoBase, MR_ADDR(pNet->PortNr, RX_GMF_RLEV), &MACFifoRLev);
16078+
16079+ /* Now read the values of read pointer/level from RX FIFO again */
16080+ SK_IN8(pAC->IoBase, Q_ADDR(pAC->GIni.GP[pNet->PortNr].PRxQOff, Q_RX_RP), &RXFifoRP);
16081+ SK_IN8(pAC->IoBase, Q_ADDR(pAC->GIni.GP[pNet->PortNr].PRxQOff, Q_RX_RL), &RXFifoRLev);
16082+
16083+ /* Check if the MAC RX hang */
16084+ if ((MACFifoRP == pNet->PreviousMACFifoRP) &&
16085+ (pNet->PreviousMACFifoRP != 0) &&
16086+ (MACFifoRLev >= pNet->PreviousMACFifoRLev)){
16087+ bStatus = SK_TRUE;
16088+ }
16089+
16090+ /* Check if the PCI RX hang */
16091+ if ((RXFifoRP == pNet->PreviousRXFifoRP) &&
16092+ (pNet->PreviousRXFifoRP != 0) &&
16093+ (RXFifoRLev >= pNet->PreviousRXFifoRLev)){
16094+ /*Set the flag to indicate that the RX FIFO hangs*/
16095+ bStatus = SK_TRUE;
16096+ }
16097+ }
16098+
16099+ /* Store now the values of counters for next check */
16100+ pNet->LastJiffies = pAC->dev[pNet->PortNr]->last_rx;
16101+
16102+ /* Store the values of read pointer/level from MAC RX FIFO for next test */
16103+ pNet->PreviousMACFifoRP = MACFifoRP;
16104+ pNet->PreviousMACFifoRLev = MACFifoRLev;
16105+
16106+ /* Store the values of read pointer/level from RX FIFO for next test */
16107+ pNet->PreviousRXFifoRP = RXFifoRP;
16108+ pNet->PreviousRXFifoRLev = RXFifoRLev;
16109+
16110+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
16111+ ("<== CheckRXCounters()\n"));
16112+
16113+ return bStatus;
16114+}
16115+
16116+/*****************************************************************************
16117+*
16118+* CheckRxPath - Checks if the RX path
16119+*
16120+* Description:
16121+* This function is called periodical by a timer.
16122+*
16123+* Notes:
16124+*
16125+* Function Parameters:
16126+*
16127+* Returns:
16128+* None.
16129+*
16130+*/
16131+static void CheckRxPath(
16132+DEV_NET *pNet) /* holds the pointer to adapter control context */
16133+{
16134+ unsigned long Flags; /* for the spin locks */
16135+ /* Initialize the pAC structure.*/
16136+ SK_AC *pAC = pNet->pAC;
16137+
16138+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
16139+ ("==> CheckRxPath()\n"));
16140+
16141+ /*If the statistics are not changed then could be an RX problem */
16142+ if (CheckRXCounters(pNet)){
16143+ /*
16144+ * First we try the simple solution by resetting the Level Timer
16145+ */
16146+
16147+ /* Stop Level Timer of Status BMU */
16148+ SK_OUT8(pAC->IoBase, STAT_LEV_TIMER_CTRL, TIM_STOP);
16149+
16150+ /* Start Level Timer of Status BMU */
16151+ SK_OUT8(pAC->IoBase, STAT_LEV_TIMER_CTRL, TIM_START);
16152+
16153+ if (!CheckRXCounters(pNet)) {
16154+ return;
16155+ }
16156+
16157+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
16158+ SkLocalEventQueue(pAC, SKGE_DRV,
16159+ SK_DRV_RECOVER,pNet->PortNr,-1,SK_TRUE);
16160
16161-/*******************************************************************************
16162- *
16163- * Extern Function Prototypes
16164- *
16165- ******************************************************************************/
16166-extern void SkDimEnableModerationIfNeeded(SK_AC *pAC);
16167-extern void SkDimDisplayModerationSettings(SK_AC *pAC);
16168-extern void SkDimStartModerationTimer(SK_AC *pAC);
16169-extern void SkDimModerate(SK_AC *pAC);
16170-extern void SkGeBlinkTimer(unsigned long data);
16171+ /* Reset the fifo counters */
16172+ pNet->PreviousMACFifoRP = 0;
16173+ pNet->PreviousMACFifoRLev = 0;
16174+ pNet->PreviousRXFifoRP = 0;
16175+ pNet->PreviousRXFifoRLev = 0;
16176
16177-#ifdef DEBUG
16178-static void DumpMsg(struct sk_buff*, char*);
16179-static void DumpData(char*, int);
16180-static void DumpLong(char*, int);
16181-#endif
16182+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
16183+ }
16184
16185-/* global variables *********************************************************/
16186-static SK_BOOL DoPrintInterfaceChange = SK_TRUE;
16187-extern const struct ethtool_ops SkGeEthtoolOps;
16188+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
16189+ ("<== CheckRxPath()\n"));
16190+}
16191+
16192+
16193+
16194+#endif
16195
16196-/* local variables **********************************************************/
16197-static uintptr_t TxQueueAddr[SK_MAX_MACS][2] = {{0x680, 0x600},{0x780, 0x700}};
16198-static uintptr_t RxQueueAddr[SK_MAX_MACS] = {0x400, 0x480};
16199
16200+#ifdef CONFIG_PM
16201 /*****************************************************************************
16202 *
16203- * SkPciWriteCfgDWord - write a 32 bit value to pci config space
16204+ * sk98lin_resume - Resume the the card
16205 *
16206 * Description:
16207- * This routine writes a 32 bit value to the pci configuration
16208- * space.
16209+ * This function resumes the card into the D0 state
16210 *
16211- * Returns:
16212- * 0 - indicate everything worked ok.
16213- * != 0 - error indication
16214+ * Returns: N/A
16215+ *
16216 */
16217-static inline int SkPciWriteCfgDWord(
16218-SK_AC *pAC, /* Adapter Control structure pointer */
16219-int PciAddr, /* PCI register address */
16220-SK_U32 Val) /* pointer to store the read value */
16221+static int sk98lin_resume(
16222+struct pci_dev *pdev) /* the device that is to resume */
16223 {
16224- pci_write_config_dword(pAC->PciDev, PciAddr, Val);
16225- return(0);
16226-} /* SkPciWriteCfgDWord */
16227+ struct net_device *dev = pci_get_drvdata(pdev);
16228+ DEV_NET *pNet = (DEV_NET*) dev->priv;
16229+ SK_AC *pAC = pNet->pAC;
16230+ SK_U16 PmCtlSts;
16231+
16232+ /* Set the power state to D0 */
16233+ pci_set_power_state(pdev, 0);
16234+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
16235+ pci_restore_state(pdev);
16236+#else
16237+ pci_restore_state(pdev, pAC->PciState);
16238+#endif
16239
16240+ pci_enable_device(pdev);
16241+ pci_set_master(pdev);
16242+
16243+ pci_enable_wake(pdev, 3, 0);
16244+ pci_enable_wake(pdev, 4, 0);
16245+
16246+ SK_OUT8(pAC->IoBase, RX_GMF_CTRL_T, (SK_U8)GMF_RST_CLR);
16247+
16248+ /* Set the adapter power state to D0 */
16249+ SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);
16250+ PmCtlSts &= ~(PCI_PM_STATE_D3); /* reset all DState bits */
16251+ PmCtlSts |= PCI_PM_STATE_D0;
16252+ SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PmCtlSts);
16253+
16254+ /* Reinit the adapter and start the port again */
16255+ pAC->BoardLevel = SK_INIT_DATA;
16256+ SkDrvLeaveDiagMode(pAC);
16257+
16258+ if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) ||
16259+ (CHIP_ID_YUKON_2(pAC)) ) {
16260+ pAC->StatusLETable.Done = 0;
16261+ pAC->StatusLETable.Put = 0;
16262+ pAC->StatusLETable.HwPut = 0;
16263+ SkGeY2InitStatBmu(pAC, pAC->IoBase, &pAC->StatusLETable);
16264+ }
16265+
16266+ return 0;
16267+}
16268+
16269 /*****************************************************************************
16270 *
16271- * SkGeInitPCI - Init the PCI resources
16272+ * sk98lin_suspend - Suspend the card
16273 *
16274 * Description:
16275- * This function initialize the PCI resources and IO
16276+ * This function suspends the card into a defined state
16277+ *
16278+ * Returns: N/A
16279+ *
16280+ */
16281+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
16282+static int sk98lin_suspend(
16283+struct pci_dev *pdev, /* pointer to the device that is to suspend */
16284+pm_message_t state) /* what power state is desired by Linux? */
16285+#else
16286+static int sk98lin_suspend(
16287+struct pci_dev *pdev, /* pointer to the device that is to suspend */
16288+SK_U32 state) /* what power state is desired by Linux? */
16289+#endif
16290+{
16291+ struct net_device *dev = pci_get_drvdata(pdev);
16292+ DEV_NET *pNet = (DEV_NET*) dev->priv;
16293+ SK_AC *pAC = pNet->pAC;
16294+ SK_U16 PciPMControlStatus;
16295+ SK_U16 PciPMCapabilities;
16296+ SK_MAC_ADDR MacAddr;
16297+ int i;
16298+
16299+ /* GEnesis and first yukon revs do not support power management */
16300+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {
16301+ if (pAC->GIni.GIChipRev == 0) {
16302+ return 0; /* power management not supported */
16303+ }
16304+ }
16305+
16306+ if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
16307+ return 0; /* not supported for this chipset */
16308+ }
16309+
16310+ if (pAC->WolInfo.ConfiguredWolOptions == 0) {
16311+ return 0; /* WOL possible, but disabled via ethtool */
16312+ }
16313+
16314+ if(netif_running(dev)) {
16315+ netif_stop_queue(dev); /* stop device if running */
16316+ }
16317+
16318+ /* read the PM control/status register from the PCI config space */
16319+ SK_IN16(pAC->IoBase, PCI_C(pAC, PCI_PM_CTL_STS), &PciPMControlStatus);
16320+
16321+ /* read the power management capabilities from the config space */
16322+ SK_IN16(pAC->IoBase, PCI_C(pAC, PCI_PM_CAP_REG), &PciPMCapabilities);
16323+
16324+ /* Enable WakeUp with Magic Packet - get MAC address from adapter */
16325+ for (i = 0; i < SK_MAC_ADDR_LEN; i++) {
16326+ /* virtual address: will be used for data */
16327+ SK_IN8(pAC->IoBase, (B2_MAC_1 + i), &MacAddr.a[i]);
16328+ }
16329+
16330+ SkDrvEnterDiagMode(pAC);
16331+ SkEnableWOMagicPacket(pAC, pAC->IoBase, MacAddr);
16332+
16333+ pci_enable_wake(pdev, 3, 1);
16334+ pci_enable_wake(pdev, 4, 1); /* 4 == D3 cold */
16335+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
16336+ pci_save_state(pdev);
16337+#else
16338+ pci_save_state(pdev, pAC->PciState);
16339+#endif
16340+ pci_disable_device(pdev); // NEW
16341+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
16342+ pci_set_power_state(pdev, pci_choose_state(pdev, state)); /* set the state */
16343+#else
16344+ pci_set_power_state(pdev, state); /* set the state */
16345+#endif
16346+
16347+ return 0;
16348+}
16349+
16350+
16351+/******************************************************************************
16352+ *
16353+ * SkEnableWOMagicPacket - Enable Wake on Magic Packet on the adapter
16354+ *
16355+ * Context:
16356+ * init, pageable
16357+ * the adapter should be de-initialized before calling this function
16358 *
16359 * Returns:
16360- * 0 - indicate everything worked ok.
16361- * != 0 - error indication
16362+ * nothing
16363 */
16364-static __devinit int SkGeInitPCI(SK_AC *pAC)
16365-{
16366- struct SK_NET_DEVICE *dev = pAC->dev[0];
16367- struct pci_dev *pdev = pAC->PciDev;
16368- int retval;
16369
16370- dev->mem_start = pci_resource_start (pdev, 0);
16371- pci_set_master(pdev);
16372+static void SkEnableWOMagicPacket(
16373+SK_AC *pAC, /* Adapter Control Context */
16374+SK_IOC IoC, /* I/O control context */
16375+SK_MAC_ADDR MacAddr) /* MacAddr expected in magic packet */
16376+{
16377+ SK_U16 Word;
16378+ SK_U32 DWord;
16379+ int i;
16380+ int HwPortIndex;
16381+ int Port = 0;
16382+
16383+ /* use Port 0 as long as we do not have any dual port cards which support WOL */
16384+ HwPortIndex = 0;
16385+ DWord = 0;
16386
16387- retval = pci_request_regions(pdev, "sk98lin");
16388- if (retval)
16389- goto out;
16390+ SK_OUT16(IoC, 0x0004, 0x0002); /* clear S/W Reset */
16391+ SK_OUT16(IoC, 0x0f10, 0x0002); /* clear Link Reset */
16392
16393-#ifdef SK_BIG_ENDIAN
16394 /*
16395- * On big endian machines, we use the adapter's aibility of
16396- * reading the descriptors as big endian.
16397+ * PHY Configuration:
16398+ * Autonegotioation is enalbed, advertise 10 HD, 10 FD,
16399+ * 100 HD, and 100 FD.
16400 */
16401- {
16402- SK_U32 our2;
16403- SkPciReadCfgDWord(pAC, PCI_OUR_REG_2, &our2);
16404- our2 |= PCI_REV_DESC;
16405- SkPciWriteCfgDWord(pAC, PCI_OUR_REG_2, our2);
16406+ if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) ||
16407+ (pAC->GIni.GIChipId == CHIP_ID_YUKON) ||
16408+ (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) ||
16409+ (CHIP_ID_YUKON_2(pAC)) ) {
16410+
16411+ SK_OUT8(IoC, 0x0007, 0xa9); /* enable VAUX */
16412+
16413+ /* WA code for COMA mode */
16414+ /* Only for yukon plus based chipsets rev A3 */
16415+ if (pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3) {
16416+ SK_IN32(IoC, B2_GP_IO, &DWord);
16417+ DWord |= GP_DIR_9; /* set to output */
16418+ DWord &= ~GP_IO_9; /* clear PHY reset (active high) */
16419+ SK_OUT32(IoC, B2_GP_IO, DWord); /* clear PHY reset */
16420+ }
16421+
16422+ if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) ||
16423+ (pAC->GIni.GIChipId == CHIP_ID_YUKON)) {
16424+ SK_OUT32(IoC, 0x0f04, 0x01f04001); /* set PHY reset */
16425+ SK_OUT32(IoC, 0x0f04, 0x01f04002); /* clear PHY reset */
16426+ } else {
16427+ SK_OUT8(IoC, 0x0f04, 0x02); /* clear PHY reset */
16428+ }
16429+
16430+ SK_OUT8(IoC, 0x0f00, 0x02); /* clear MAC reset */
16431+ SkGmPhyWrite(pAC, IoC, Port, 4, 0x01e1); /* advertise 10/100 HD/FD */
16432+ SkGmPhyWrite(pAC, IoC, Port, 9, 0x0000); /* do not advertise 1000 HD/FD */
16433+ SkGmPhyWrite(pAC, IoC, Port, 00, 0xB300); /* 100 MBit, disable Autoneg */
16434+ } else if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) {
16435+ SK_OUT8(IoC, 0x0007, 0xa9); /* enable VAUX */
16436+ SK_OUT8(IoC, 0x0f04, 0x02); /* clear PHY reset */
16437+ SK_OUT8(IoC, 0x0f00, 0x02); /* clear MAC reset */
16438+ SkGmPhyWrite(pAC, IoC, Port, 16, 0x0130); /* Enable Automatic Crossover */
16439+ SkGmPhyWrite(pAC, IoC, Port, 00, 0xB300); /* 100 MBit, disable Autoneg */
16440 }
16441-#endif
16442+
16443
16444 /*
16445- * Remap the regs into kernel space.
16446+ * MAC Configuration:
16447+ * Set the MAC to 100 HD and enable the auto update features
16448+ * for Speed, Flow Control and Duplex Mode.
16449+ * If autonegotiation completes successfully the
16450+ * MAC takes the link parameters from the PHY.
16451+ * If the link partner doesn't support autonegotiation
16452+ * the MAC can receive magic packets if the link partner
16453+ * uses 100 HD.
16454 */
16455- pAC->IoBase = ioremap_nocache(dev->mem_start, 0x4000);
16456- if (!pAC->IoBase) {
16457- retval = -EIO;
16458- goto out_release;
16459+ SK_OUT16(IoC, 0x2804, 0x3832);
16460+
16461+
16462+ /*
16463+ * Set Up Magic Packet parameters
16464+ */
16465+ for (i = 0; i < 6; i+=2) { /* set up magic packet MAC address */
16466+ SK_IN16(IoC, 0x100 + i, &Word);
16467+ SK_OUT16(IoC, 0xf24 + i, Word);
16468 }
16469
16470- return 0;
16471+ SK_OUT16(IoC, 0x0f20, 0x0208); /* enable PME on magic packet */
16472+ /* and on wake up frame */
16473
16474- out_release:
16475- pci_release_regions(pdev);
16476- out:
16477- return retval;
16478-}
16479+ /*
16480+ * Set up PME generation
16481+ */
16482+ /* set PME legacy mode */
16483+ /* Only for PCI express based chipsets */
16484+ if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) ||
16485+ (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) ||
16486+ (CHIP_ID_YUKON_2(pAC))) {
16487+ SkPciReadCfgDWord(pAC, 0x40, &DWord);
16488+ DWord |= 0x8000;
16489+ SkPciWriteCfgDWord(pAC, 0x40, DWord);
16490+ }
16491+
16492+ SK_OUT8(IoC, RX_GMF_CTRL_T, (SK_U8)GMF_RST_SET);
16493+
16494+ /* clear PME status and switch adapter to DState */
16495+ SkPciReadCfgWord(pAC, 0x4c, &Word);
16496+ Word |= 0x103;
16497+ SkPciWriteCfgWord(pAC, 0x4c, Word);
16498+} /* SkEnableWOMagicPacket */
16499+#endif
16500
16501
16502 /*****************************************************************************
16503@@ -349,20 +1257,24 @@
16504 DEV_NET *pNet;
16505 SK_AC *pAC;
16506
16507- pNet = netdev_priv(dev);
16508- pAC = pNet->pAC;
16509- AllocFlag = pAC->AllocFlag;
16510- if (pAC->PciDev) {
16511- pci_release_regions(pAC->PciDev);
16512- }
16513- if (AllocFlag & SK_ALLOC_IRQ) {
16514- free_irq(dev->irq, dev);
16515- }
16516- if (pAC->IoBase) {
16517- iounmap(pAC->IoBase);
16518- }
16519- if (pAC->pDescrMem) {
16520- BoardFreeMem(pAC);
16521+ if (dev->priv) {
16522+ pNet = (DEV_NET*) dev->priv;
16523+ pAC = pNet->pAC;
16524+ AllocFlag = pAC->AllocFlag;
16525+ if (pAC->PciDev) {
16526+ pci_release_regions(pAC->PciDev);
16527+ }
16528+ if (AllocFlag & SK_ALLOC_IRQ) {
16529+ free_irq(dev->irq, dev);
16530+ }
16531+ if (pAC->IoBase) {
16532+ iounmap(pAC->IoBase);
16533+ }
16534+ if (CHIP_ID_YUKON_2(pAC)) {
16535+ SkY2FreeResources(pAC);
16536+ } else {
16537+ BoardFreeMem(pAC);
16538+ }
16539 }
16540
16541 } /* FreeResources */
16542@@ -371,6 +1283,8 @@
16543 MODULE_DESCRIPTION("SysKonnect SK-NET Gigabit Ethernet SK-98xx driver");
16544 MODULE_LICENSE("GPL");
16545
16546+MODULE_VERSION(DRV_VERSION);
16547+
16548 #ifdef LINK_SPEED_A
16549 static char *Speed_A[SK_MAX_CARD_PARAM] = LINK_SPEED;
16550 #else
16551@@ -452,9 +1366,11 @@
16552 static int IntsPerSec[SK_MAX_CARD_PARAM];
16553 static char *Moderation[SK_MAX_CARD_PARAM];
16554 static char *ModerationMask[SK_MAX_CARD_PARAM];
16555-static char *AutoSizing[SK_MAX_CARD_PARAM];
16556-static char *Stats[SK_MAX_CARD_PARAM];
16557
16558+static char *LowLatency[SK_MAX_CARD_PARAM];
16559+static char *BroadcastPrio[SK_MAX_CARD_PARAM];
16560+
16561+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
16562 module_param_array(Speed_A, charp, NULL, 0);
16563 module_param_array(Speed_B, charp, NULL, 0);
16564 module_param_array(AutoNeg_A, charp, NULL, 0);
16565@@ -471,9 +1387,129 @@
16566 /* used for interrupt moderation */
16567 module_param_array(IntsPerSec, int, NULL, 0);
16568 module_param_array(Moderation, charp, NULL, 0);
16569-module_param_array(Stats, charp, NULL, 0);
16570 module_param_array(ModerationMask, charp, NULL, 0);
16571-module_param_array(AutoSizing, charp, NULL, 0);
16572+module_param_array(LowLatency, charp, NULL, 0);
16573+module_param_array(BroadcastPrio, charp, NULL, 0);
16574+#else
16575+MODULE_PARM(Speed_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16576+MODULE_PARM(Speed_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16577+MODULE_PARM(AutoNeg_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16578+MODULE_PARM(AutoNeg_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16579+MODULE_PARM(DupCap_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16580+MODULE_PARM(DupCap_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16581+MODULE_PARM(FlowCtrl_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16582+MODULE_PARM(FlowCtrl_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16583+MODULE_PARM(Role_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16584+MODULE_PARM(Role_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16585+MODULE_PARM(ConType, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16586+MODULE_PARM(PrefPort, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16587+MODULE_PARM(RlmtMode, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16588+MODULE_PARM(IntsPerSec, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "i");
16589+MODULE_PARM(Moderation, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16590+MODULE_PARM(ModerationMask, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16591+MODULE_PARM(LowLatency, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16592+MODULE_PARM(BroadcastPrio, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16593+#endif
16594+
16595+
16596+/*****************************************************************************
16597+ *
16598+ * sk98lin_remove_device - device deinit function
16599+ *
16600+ * Description:
16601+ * Disable adapter if it is still running, free resources,
16602+ * free device struct.
16603+ *
16604+ * Returns: N/A
16605+ */
16606+
16607+static void sk98lin_remove_device(struct pci_dev *pdev)
16608+{
16609+DEV_NET *pNet;
16610+SK_AC *pAC;
16611+struct SK_NET_DEVICE *next;
16612+unsigned long Flags;
16613+struct net_device *dev = pci_get_drvdata(pdev);
16614+
16615+
16616+ /* Device not available. Return. */
16617+ if (!dev)
16618+ return;
16619+
16620+ pNet = (DEV_NET*) dev->priv;
16621+ pAC = pNet->pAC;
16622+ next = pAC->Next;
16623+
16624+#ifndef SK_ASF
16625+ netif_stop_queue(dev);
16626+#endif
16627+ SkGeYellowLED(pAC, pAC->IoBase, 0);
16628+
16629+ if(pAC->BoardLevel == SK_INIT_RUN) {
16630+ /* board is still alive */
16631+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
16632+#ifndef SK_ASF
16633+ SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP,
16634+ 0, -1, SK_FALSE);
16635+ SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP,
16636+ 1, -1, SK_TRUE);
16637+#endif
16638+
16639+ /* disable interrupts */
16640+ SK_OUT32(pAC->IoBase, B0_IMSK, 0);
16641+#ifdef SK_ASF
16642+ SkAsfDeInit(pAC, pAC->IoBase);
16643+#endif
16644+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
16645+ pAC->BoardLevel = SK_INIT_DATA;
16646+ /* We do NOT check here, if IRQ was pending, of course*/
16647+ }
16648+
16649+ if(pAC->BoardLevel == SK_INIT_IO) {
16650+ /* board is still alive */
16651+ SkGeDeInit(pAC, pAC->IoBase);
16652+ pAC->BoardLevel = SK_INIT_DATA;
16653+ }
16654+
16655+ if ((pAC->GIni.GIMacsFound == 2) && pAC->RlmtNets == 2){
16656+ unregister_netdev(pAC->dev[1]);
16657+ free_netdev(pAC->dev[1]);
16658+ }
16659+
16660+ FreeResources(dev);
16661+
16662+#ifdef CONFIG_PROC_FS
16663+ /* Remove the sk98lin procfs device entries */
16664+ if ((pAC->GIni.GIMacsFound == 2) && pAC->RlmtNets == 2){
16665+ if (pAC->InterfaceUp[1] == 1) {
16666+ remove_proc_entry(pAC->dev[1]->name, pSkRootDir);
16667+ }
16668+ }
16669+ if (pAC->InterfaceUp[0] == 1) {
16670+ remove_proc_entry(pAC->dev[0]->name, pSkRootDir);
16671+ }
16672+#endif
16673+
16674+ dev->get_stats = NULL;
16675+ /*
16676+ * otherwise unregister_netdev calls get_stats with
16677+ * invalid IO ... :-(
16678+ */
16679+ unregister_netdev(dev);
16680+ free_netdev(dev);
16681+ kfree(pAC);
16682+ sk98lin_max_boards_found--;
16683+
16684+#ifdef CONFIG_PROC_FS
16685+ /* Remove all Proc entries if last device */
16686+ if (sk98lin_max_boards_found == 0) {
16687+ /* clear proc-dir */
16688+ remove_proc_entry(pSkRootDir->name, proc_net);
16689+ }
16690+#endif
16691+
16692+}
16693+
16694
16695 /*****************************************************************************
16696 *
16697@@ -491,11 +1527,11 @@
16698 static int __devinit SkGeBoardInit(struct SK_NET_DEVICE *dev, SK_AC *pAC)
16699 {
16700 short i;
16701-unsigned long Flags;
16702 char *DescrString = "sk98lin: Driver for Linux"; /* this is given to PNMI */
16703 char *VerStr = VER_STRING;
16704 int Ret; /* return code of request_irq */
16705 SK_BOOL DualNet;
16706+unsigned long Flags; /* for the spin locks */
16707
16708 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
16709 ("IoBase: %08lX\n", (unsigned long)pAC->IoBase));
16710@@ -511,21 +1547,30 @@
16711 spin_lock_init(&pAC->TxPort[i][0].TxDesRingLock);
16712 spin_lock_init(&pAC->RxPort[i].RxDesRingLock);
16713 }
16714- spin_lock_init(&pAC->SlowPathLock);
16715
16716- /* setup phy_id blink timer */
16717- pAC->BlinkTimer.function = SkGeBlinkTimer;
16718- pAC->BlinkTimer.data = (unsigned long) dev;
16719- init_timer(&pAC->BlinkTimer);
16720+ spin_lock_init(&pAC->InitLock); /* Init lock */
16721+ spin_lock_init(&pAC->SlowPathLock);
16722+ spin_lock_init(&pAC->TxQueueLock); /* for Yukon2 chipsets */
16723+ spin_lock_init(&pAC->SetPutIndexLock); /* for Yukon2 chipsets */
16724
16725 /* level 0 init common modules here */
16726-
16727+
16728+#ifdef SK_ASF
16729+ spin_lock(&pAC->SlowPathLock);
16730+#endif
16731+#ifndef SK_ASF
16732 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
16733+#endif
16734 /* Does a RESET on board ...*/
16735 if (SkGeInit(pAC, pAC->IoBase, SK_INIT_DATA) != 0) {
16736 printk("HWInit (0) failed.\n");
16737+#ifdef SK_ASF
16738+ spin_unlock(&pAC->SlowPathLock);
16739+#endif
16740+#ifndef SK_ASF
16741 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
16742- return -EIO;
16743+#endif
16744+ return(-EAGAIN);
16745 }
16746 SkI2cInit( pAC, pAC->IoBase, SK_INIT_DATA);
16747 SkEventInit(pAC, pAC->IoBase, SK_INIT_DATA);
16748@@ -533,21 +1578,27 @@
16749 SkAddrInit( pAC, pAC->IoBase, SK_INIT_DATA);
16750 SkRlmtInit( pAC, pAC->IoBase, SK_INIT_DATA);
16751 SkTimerInit(pAC, pAC->IoBase, SK_INIT_DATA);
16752+#ifdef SK_ASF
16753+ SkAsfInit(pAC, pAC->IoBase, SK_INIT_DATA);
16754+#endif
16755
16756 pAC->BoardLevel = SK_INIT_DATA;
16757- pAC->RxBufSize = ETH_BUF_SIZE;
16758+ pAC->RxPort[0].RxBufSize = ETH_BUF_SIZE;
16759+ pAC->RxPort[1].RxBufSize = ETH_BUF_SIZE;
16760
16761 SK_PNMI_SET_DRIVER_DESCR(pAC, DescrString);
16762 SK_PNMI_SET_DRIVER_VER(pAC, VerStr);
16763
16764- spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
16765-
16766 /* level 1 init common modules here (HW init) */
16767- spin_lock_irqsave(&pAC->SlowPathLock, Flags);
16768 if (SkGeInit(pAC, pAC->IoBase, SK_INIT_IO) != 0) {
16769 printk("sk98lin: HWInit (1) failed.\n");
16770+#ifdef SK_ASF
16771+ spin_unlock(&pAC->SlowPathLock);
16772+#endif
16773+#ifndef SK_ASF
16774 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
16775- return -EIO;
16776+#endif
16777+ return(-EAGAIN);
16778 }
16779 SkI2cInit( pAC, pAC->IoBase, SK_INIT_IO);
16780 SkEventInit(pAC, pAC->IoBase, SK_INIT_IO);
16781@@ -555,46 +1606,101 @@
16782 SkAddrInit( pAC, pAC->IoBase, SK_INIT_IO);
16783 SkRlmtInit( pAC, pAC->IoBase, SK_INIT_IO);
16784 SkTimerInit(pAC, pAC->IoBase, SK_INIT_IO);
16785+#ifdef SK_ASF
16786+ SkAsfInit(pAC, pAC->IoBase, SK_INIT_IO);
16787+#endif
16788+#ifdef Y2_RECOVERY
16789+ /* mark entries invalid */
16790+ pAC->LastPort = 3;
16791+ pAC->LastOpc = 0xFF;
16792+#endif
16793
16794 /* Set chipset type support */
16795- pAC->ChipsetType = 0;
16796 if ((pAC->GIni.GIChipId == CHIP_ID_YUKON) ||
16797- (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE)) {
16798- pAC->ChipsetType = 1;
16799+ (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) ||
16800+ (pAC->GIni.GIChipId == CHIP_ID_YUKON_LP)) {
16801+ pAC->ChipsetType = 1; /* Yukon chipset (descriptor logic) */
16802+ } else if (CHIP_ID_YUKON_2(pAC)) {
16803+ pAC->ChipsetType = 2; /* Yukon2 chipset (list logic) */
16804+ } else {
16805+ pAC->ChipsetType = 0; /* Genesis chipset (descriptor logic) */
16806+ }
16807+
16808+ /* wake on lan support */
16809+ pAC->WolInfo.SupportedWolOptions = 0;
16810+#if defined (ETHTOOL_GWOL) && defined (ETHTOOL_SWOL)
16811+ if (pAC->GIni.GIChipId != CHIP_ID_GENESIS) {
16812+ pAC->WolInfo.SupportedWolOptions = WAKE_MAGIC;
16813+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {
16814+ if (pAC->GIni.GIChipRev == 0) {
16815+ pAC->WolInfo.SupportedWolOptions = 0;
16816+ }
16817+ }
16818 }
16819+#endif
16820+ pAC->WolInfo.ConfiguredWolOptions = pAC->WolInfo.SupportedWolOptions;
16821
16822 GetConfiguration(pAC);
16823 if (pAC->RlmtNets == 2) {
16824- pAC->GIni.GIPortUsage = SK_MUL_LINK;
16825+ pAC->GIni.GP[0].PPortUsage = SK_MUL_LINK;
16826+ pAC->GIni.GP[1].PPortUsage = SK_MUL_LINK;
16827 }
16828
16829 pAC->BoardLevel = SK_INIT_IO;
16830+#ifdef SK_ASF
16831+ spin_unlock(&pAC->SlowPathLock);
16832+#endif
16833+#ifndef SK_ASF
16834 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
16835+#endif
16836
16837- if (pAC->GIni.GIMacsFound == 2) {
16838- Ret = request_irq(dev->irq, SkGeIsr, IRQF_SHARED, "sk98lin", dev);
16839- } else if (pAC->GIni.GIMacsFound == 1) {
16840- Ret = request_irq(dev->irq, SkGeIsrOnePort, IRQF_SHARED,
16841- "sk98lin", dev);
16842- } else {
16843- printk(KERN_WARNING "sk98lin: Illegal number of ports: %d\n",
16844- pAC->GIni.GIMacsFound);
16845- return -EIO;
16846+ if (!CHIP_ID_YUKON_2(pAC)) {
16847+ if (pAC->GIni.GIMacsFound == 2) {
16848+ Ret = request_irq(dev->irq, SkGeIsr, IRQF_SHARED, "sk98lin", dev);
16849+ } else if (pAC->GIni.GIMacsFound == 1) {
16850+ Ret = request_irq(dev->irq, SkGeIsrOnePort, IRQF_SHARED, "sk98lin", dev);
16851+ } else {
16852+ printk(KERN_WARNING "sk98lin: Illegal number of ports: %d\n",
16853+ pAC->GIni.GIMacsFound);
16854+ return -EAGAIN;
16855+ }
16856+ }
16857+ else {
16858+ Ret = request_irq(dev->irq, SkY2Isr, IRQF_SHARED, "sk98lin", dev);
16859 }
16860
16861 if (Ret) {
16862 printk(KERN_WARNING "sk98lin: Requested IRQ %d is busy.\n",
16863- dev->irq);
16864- return Ret;
16865+ dev->irq);
16866+ return -EAGAIN;
16867 }
16868 pAC->AllocFlag |= SK_ALLOC_IRQ;
16869
16870- /* Alloc memory for this board (Mem for RxD/TxD) : */
16871- if(!BoardAllocMem(pAC)) {
16872- printk("No memory for descriptor rings.\n");
16873- return -ENOMEM;
16874+ /*
16875+ ** Alloc descriptor/LETable memory for this board (both RxD/TxD)
16876+ */
16877+ if (CHIP_ID_YUKON_2(pAC)) {
16878+ if (!SkY2AllocateResources(pAC)) {
16879+ printk("No memory for Yukon2 settings\n");
16880+ return(-EAGAIN);
16881+ }
16882+ } else {
16883+ if(!BoardAllocMem(pAC)) {
16884+ printk("No memory for descriptor rings.\n");
16885+ return(-EAGAIN);
16886+ }
16887 }
16888
16889+#ifdef SK_USE_CSUM
16890+ SkCsSetReceiveFlags(pAC,
16891+ SKCS_PROTO_IP | SKCS_PROTO_TCP | SKCS_PROTO_UDP,
16892+ &pAC->CsOfs1, &pAC->CsOfs2, 0);
16893+ pAC->CsOfs = (pAC->CsOfs2 << 16) | pAC->CsOfs1;
16894+#endif
16895+
16896+ /*
16897+ ** Function BoardInitMem() for Yukon dependent settings...
16898+ */
16899 BoardInitMem(pAC);
16900 /* tschilling: New common function with minimum size check. */
16901 DualNet = SK_FALSE;
16902@@ -606,11 +1712,22 @@
16903 pAC,
16904 pAC->ActivePort,
16905 DualNet)) {
16906- BoardFreeMem(pAC);
16907+ if (CHIP_ID_YUKON_2(pAC)) {
16908+ SkY2FreeResources(pAC);
16909+ } else {
16910+ BoardFreeMem(pAC);
16911+ }
16912+
16913 printk("sk98lin: SkGeInitAssignRamToQueues failed.\n");
16914- return -EIO;
16915+ return(-EAGAIN);
16916 }
16917
16918+ /*
16919+ * Register the device here
16920+ */
16921+ pAC->Next = SkGeRootDev;
16922+ SkGeRootDev = dev;
16923+
16924 return (0);
16925 } /* SkGeBoardInit */
16926
16927@@ -629,7 +1746,8 @@
16928 * SK_TRUE, if all memory could be allocated
16929 * SK_FALSE, if not
16930 */
16931-static __devinit SK_BOOL BoardAllocMem(SK_AC *pAC)
16932+static SK_BOOL BoardAllocMem(
16933+SK_AC *pAC)
16934 {
16935 caddr_t pDescrMem; /* pointer to descriptor memory area */
16936 size_t AllocLength; /* length of complete descriptor area */
16937@@ -699,16 +1817,20 @@
16938
16939 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
16940 ("BoardFreeMem\n"));
16941+
16942+ if (pAC->pDescrMem) {
16943+
16944 #if (BITS_PER_LONG == 32)
16945- AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound + 8;
16946+ AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound + 8;
16947 #else
16948- AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound
16949- + RX_RING_SIZE + 8;
16950+ AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound
16951+ + RX_RING_SIZE + 8;
16952 #endif
16953
16954- pci_free_consistent(pAC->PciDev, AllocLength,
16955+ pci_free_consistent(pAC->PciDev, AllocLength,
16956 pAC->pDescrMem, pAC->pDescrMemDMA);
16957- pAC->pDescrMem = NULL;
16958+ pAC->pDescrMem = NULL;
16959+ }
16960 } /* BoardFreeMem */
16961
16962
16963@@ -717,12 +1839,13 @@
16964 * BoardInitMem - initiate the descriptor rings
16965 *
16966 * Description:
16967- * This function sets the descriptor rings up in memory.
16968+ * This function sets the descriptor rings or LETables up in memory.
16969 * The adapter is initialized with the descriptor start addresses.
16970 *
16971 * Returns: N/A
16972 */
16973-static __devinit void BoardInitMem(SK_AC *pAC)
16974+static void BoardInitMem(
16975+SK_AC *pAC) /* pointer to adapter context */
16976 {
16977 int i; /* loop counter */
16978 int RxDescrSize; /* the size of a rx descriptor rounded up to alignment*/
16979@@ -731,34 +1854,37 @@
16980 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
16981 ("BoardInitMem\n"));
16982
16983- RxDescrSize = (((sizeof(RXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN;
16984- pAC->RxDescrPerRing = RX_RING_SIZE / RxDescrSize;
16985- TxDescrSize = (((sizeof(TXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN;
16986- pAC->TxDescrPerRing = TX_RING_SIZE / RxDescrSize;
16987+ if (!pAC->GIni.GIYukon2) {
16988+ RxDescrSize = (((sizeof(RXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN;
16989+ pAC->RxDescrPerRing = RX_RING_SIZE / RxDescrSize;
16990+ TxDescrSize = (((sizeof(TXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN;
16991+ pAC->TxDescrPerRing = TX_RING_SIZE / RxDescrSize;
16992
16993- for (i=0; i<pAC->GIni.GIMacsFound; i++) {
16994- SetupRing(
16995- pAC,
16996- pAC->TxPort[i][0].pTxDescrRing,
16997- pAC->TxPort[i][0].VTxDescrRing,
16998- (RXD**)&pAC->TxPort[i][0].pTxdRingHead,
16999- (RXD**)&pAC->TxPort[i][0].pTxdRingTail,
17000- (RXD**)&pAC->TxPort[i][0].pTxdRingPrev,
17001- &pAC->TxPort[i][0].TxdRingFree,
17002- SK_TRUE);
17003- SetupRing(
17004- pAC,
17005- pAC->RxPort[i].pRxDescrRing,
17006- pAC->RxPort[i].VRxDescrRing,
17007- &pAC->RxPort[i].pRxdRingHead,
17008- &pAC->RxPort[i].pRxdRingTail,
17009- &pAC->RxPort[i].pRxdRingPrev,
17010- &pAC->RxPort[i].RxdRingFree,
17011- SK_FALSE);
17012+ for (i=0; i<pAC->GIni.GIMacsFound; i++) {
17013+ SetupRing(
17014+ pAC,
17015+ pAC->TxPort[i][0].pTxDescrRing,
17016+ pAC->TxPort[i][0].VTxDescrRing,
17017+ (RXD**)&pAC->TxPort[i][0].pTxdRingHead,
17018+ (RXD**)&pAC->TxPort[i][0].pTxdRingTail,
17019+ (RXD**)&pAC->TxPort[i][0].pTxdRingPrev,
17020+ &pAC->TxPort[i][0].TxdRingFree,
17021+ &pAC->TxPort[i][0].TxdRingPrevFree,
17022+ SK_TRUE);
17023+ SetupRing(
17024+ pAC,
17025+ pAC->RxPort[i].pRxDescrRing,
17026+ pAC->RxPort[i].VRxDescrRing,
17027+ &pAC->RxPort[i].pRxdRingHead,
17028+ &pAC->RxPort[i].pRxdRingTail,
17029+ &pAC->RxPort[i].pRxdRingPrev,
17030+ &pAC->RxPort[i].RxdRingFree,
17031+ &pAC->RxPort[i].RxdRingFree,
17032+ SK_FALSE);
17033+ }
17034 }
17035 } /* BoardInitMem */
17036
17037-
17038 /*****************************************************************************
17039 *
17040 * SetupRing - create one descriptor ring
17041@@ -778,6 +1904,7 @@
17042 RXD **ppRingTail, /* address where the tail should be written */
17043 RXD **ppRingPrev, /* address where the tail should be written */
17044 int *pRingFree, /* address where the # of free descr. goes */
17045+int *pRingPrevFree, /* address where the # of free descr. goes */
17046 SK_BOOL IsTx) /* flag: is this a tx ring */
17047 {
17048 int i; /* loop counter */
17049@@ -810,7 +1937,7 @@
17050 /* set the pointers right */
17051 pDescr->VNextRxd = VNextDescr & 0xffffffffULL;
17052 pDescr->pNextRxd = pNextDescr;
17053- if (!IsTx) pDescr->TcpSumStarts = ETH_HLEN << 16 | ETH_HLEN;
17054+ pDescr->TcpSumStarts = pAC->CsOfs;
17055
17056 /* advance one step */
17057 pPrevDescr = pDescr;
17058@@ -820,11 +1947,12 @@
17059 }
17060 pPrevDescr->pNextRxd = (RXD*) pMemArea;
17061 pPrevDescr->VNextRxd = VMemArea;
17062- pDescr = (RXD*) pMemArea;
17063- *ppRingHead = (RXD*) pMemArea;
17064- *ppRingTail = *ppRingHead;
17065- *ppRingPrev = pPrevDescr;
17066- *pRingFree = DescrNum;
17067+ pDescr = (RXD*) pMemArea;
17068+ *ppRingHead = (RXD*) pMemArea;
17069+ *ppRingTail = *ppRingHead;
17070+ *ppRingPrev = pPrevDescr;
17071+ *pRingFree = DescrNum;
17072+ *pRingPrevFree = DescrNum;
17073 } /* SetupRing */
17074
17075
17076@@ -882,24 +2010,42 @@
17077 * Returns: N/A
17078 *
17079 */
17080-static SkIsrRetVar SkGeIsr(int irq, void *dev_id)
17081+static SkIsrRetVar SkGeIsr(int irq, void *dev_id)
17082 {
17083 struct SK_NET_DEVICE *dev = (struct SK_NET_DEVICE *)dev_id;
17084 DEV_NET *pNet;
17085 SK_AC *pAC;
17086 SK_U32 IntSrc; /* interrupts source register contents */
17087
17088- pNet = netdev_priv(dev);
17089+ pNet = (DEV_NET*) dev->priv;
17090 pAC = pNet->pAC;
17091
17092 /*
17093 * Check and process if its our interrupt
17094 */
17095 SK_IN32(pAC->IoBase, B0_SP_ISRC, &IntSrc);
17096- if (IntSrc == 0) {
17097+ if ((IntSrc == 0) && (!pNet->NetConsoleMode)) {
17098 return SkIsrRetNone;
17099 }
17100
17101+#ifdef CONFIG_SK98LIN_NAPI
17102+ if (netif_rx_schedule_prep(dev)) {
17103+ pAC->GIni.GIValIrqMask &= ~(NAPI_DRV_IRQS);
17104+ SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
17105+ __netif_rx_schedule(dev);
17106+ }
17107+
17108+#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
17109+ if (IntSrc & IS_XA1_F) {
17110+ CLEAR_TX_IRQ(0, TX_PRIO_LOW);
17111+ }
17112+ if (IntSrc & IS_XA2_F) {
17113+ CLEAR_TX_IRQ(1, TX_PRIO_LOW);
17114+ }
17115+#endif
17116+
17117+
17118+#else
17119 while (((IntSrc & IRQ_MASK) & ~SPECIAL_IRQS) != 0) {
17120 #if 0 /* software irq currently not used */
17121 if (IntSrc & IS_IRQ_SW) {
17122@@ -913,6 +2059,7 @@
17123 SK_DBGCAT_DRV_INT_SRC,
17124 ("EOF RX1 IRQ\n"));
17125 ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE);
17126+ CLEAR_AND_START_RX(0);
17127 SK_PNMI_CNT_RX_INTR(pAC, 0);
17128 }
17129 if (IntSrc & IS_R2_F) {
17130@@ -920,6 +2067,7 @@
17131 SK_DBGCAT_DRV_INT_SRC,
17132 ("EOF RX2 IRQ\n"));
17133 ReceiveIrq(pAC, &pAC->RxPort[1], SK_TRUE);
17134+ CLEAR_AND_START_RX(1);
17135 SK_PNMI_CNT_RX_INTR(pAC, 1);
17136 }
17137 #ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
17138@@ -927,6 +2075,7 @@
17139 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
17140 SK_DBGCAT_DRV_INT_SRC,
17141 ("EOF AS TX1 IRQ\n"));
17142+ CLEAR_TX_IRQ(0, TX_PRIO_LOW);
17143 SK_PNMI_CNT_TX_INTR(pAC, 0);
17144 spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
17145 FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]);
17146@@ -936,6 +2085,7 @@
17147 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
17148 SK_DBGCAT_DRV_INT_SRC,
17149 ("EOF AS TX2 IRQ\n"));
17150+ CLEAR_TX_IRQ(1, TX_PRIO_LOW);
17151 SK_PNMI_CNT_TX_INTR(pAC, 1);
17152 spin_lock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock);
17153 FreeTxDescriptors(pAC, &pAC->TxPort[1][TX_PRIO_LOW]);
17154@@ -946,38 +2096,42 @@
17155 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
17156 SK_DBGCAT_DRV_INT_SRC,
17157 ("EOF SY TX1 IRQ\n"));
17158+ CLEAR_TX_IRQ(0, TX_PRIO_HIGH);
17159 SK_PNMI_CNT_TX_INTR(pAC, 1);
17160 spin_lock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock);
17161 FreeTxDescriptors(pAC, 0, TX_PRIO_HIGH);
17162 spin_unlock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock);
17163- ClearTxIrq(pAC, 0, TX_PRIO_HIGH);
17164 }
17165 if (IntSrc & IS_XS2_F) {
17166 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
17167 SK_DBGCAT_DRV_INT_SRC,
17168 ("EOF SY TX2 IRQ\n"));
17169+ CLEAR_TX_IRQ(1, TX_PRIO_HIGH);
17170 SK_PNMI_CNT_TX_INTR(pAC, 1);
17171 spin_lock(&pAC->TxPort[1][TX_PRIO_HIGH].TxDesRingLock);
17172 FreeTxDescriptors(pAC, 1, TX_PRIO_HIGH);
17173 spin_unlock(&pAC->TxPort[1][TX_PRIO_HIGH].TxDesRingLock);
17174- ClearTxIrq(pAC, 1, TX_PRIO_HIGH);
17175 }
17176 #endif
17177 #endif
17178
17179- /* do all IO at once */
17180- if (IntSrc & IS_R1_F)
17181- ClearAndStartRx(pAC, 0);
17182- if (IntSrc & IS_R2_F)
17183- ClearAndStartRx(pAC, 1);
17184-#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
17185- if (IntSrc & IS_XA1_F)
17186- ClearTxIrq(pAC, 0, TX_PRIO_LOW);
17187- if (IntSrc & IS_XA2_F)
17188- ClearTxIrq(pAC, 1, TX_PRIO_LOW);
17189-#endif
17190 SK_IN32(pAC->IoBase, B0_ISRC, &IntSrc);
17191 } /* while (IntSrc & IRQ_MASK != 0) */
17192+#endif
17193+
17194+#ifndef CONFIG_SK98LIN_NAPI
17195+ /* Handle interrupts */
17196+ spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
17197+ FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]);
17198+ spin_unlock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
17199+ ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE);
17200+ START_RX(0);
17201+ spin_lock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock);
17202+ FreeTxDescriptors(pAC, &pAC->TxPort[1][TX_PRIO_LOW]);
17203+ spin_unlock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock);
17204+ ReceiveIrq(pAC, &pAC->RxPort[1], SK_TRUE);
17205+ START_RX(1);
17206+#endif
17207
17208 IntSrc &= pAC->GIni.GIValIrqMask;
17209 if ((IntSrc & SPECIAL_IRQS) || pAC->CheckQueue) {
17210@@ -990,19 +2144,9 @@
17211
17212 SkEventDispatcher(pAC, pAC->IoBase);
17213 spin_unlock(&pAC->SlowPathLock);
17214+ START_RX(0);
17215+ START_RX(1);
17216 }
17217- /*
17218- * do it all again is case we cleared an interrupt that
17219- * came in after handling the ring (OUTs may be delayed
17220- * in hardware buffers, but are through after IN)
17221- *
17222- * rroesler: has been commented out and shifted to
17223- * SkGeDrvEvent(), because it is timer
17224- * guarded now
17225- *
17226- ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE);
17227- ReceiveIrq(pAC, &pAC->RxPort[1], SK_TRUE);
17228- */
17229
17230 if (pAC->CheckQueue) {
17231 pAC->CheckQueue = SK_FALSE;
17232@@ -1014,7 +2158,8 @@
17233 /* IRQ is processed - Enable IRQs again*/
17234 SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
17235
17236- return SkIsrRetHandled;
17237+ return SkIsrRetHandled;
17238+
17239 } /* SkGeIsr */
17240
17241
17242@@ -1031,24 +2176,40 @@
17243 * Returns: N/A
17244 *
17245 */
17246-static SkIsrRetVar SkGeIsrOnePort(int irq, void *dev_id)
17247+static SkIsrRetVar SkGeIsrOnePort(int irq, void *dev_id)
17248 {
17249 struct SK_NET_DEVICE *dev = (struct SK_NET_DEVICE *)dev_id;
17250 DEV_NET *pNet;
17251 SK_AC *pAC;
17252 SK_U32 IntSrc; /* interrupts source register contents */
17253
17254- pNet = netdev_priv(dev);
17255+ pNet = (DEV_NET*) dev->priv;
17256 pAC = pNet->pAC;
17257
17258 /*
17259 * Check and process if its our interrupt
17260 */
17261 SK_IN32(pAC->IoBase, B0_SP_ISRC, &IntSrc);
17262- if (IntSrc == 0) {
17263+ if ((IntSrc == 0) && (!pNet->NetConsoleMode)) {
17264 return SkIsrRetNone;
17265+
17266 }
17267
17268+#ifdef CONFIG_SK98LIN_NAPI
17269+ if (netif_rx_schedule_prep(dev)) {
17270+ CLEAR_AND_START_RX(0);
17271+ CLEAR_TX_IRQ(0, TX_PRIO_LOW);
17272+ pAC->GIni.GIValIrqMask &= ~(NAPI_DRV_IRQS);
17273+ SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
17274+ __netif_rx_schedule(dev);
17275+ }
17276+
17277+#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
17278+ if (IntSrc & IS_XA1_F) {
17279+ CLEAR_TX_IRQ(0, TX_PRIO_LOW);
17280+ }
17281+#endif
17282+#else
17283 while (((IntSrc & IRQ_MASK) & ~SPECIAL_IRQS) != 0) {
17284 #if 0 /* software irq currently not used */
17285 if (IntSrc & IS_IRQ_SW) {
17286@@ -1062,6 +2223,7 @@
17287 SK_DBGCAT_DRV_INT_SRC,
17288 ("EOF RX1 IRQ\n"));
17289 ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE);
17290+ CLEAR_AND_START_RX(0);
17291 SK_PNMI_CNT_RX_INTR(pAC, 0);
17292 }
17293 #ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
17294@@ -1069,6 +2231,7 @@
17295 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
17296 SK_DBGCAT_DRV_INT_SRC,
17297 ("EOF AS TX1 IRQ\n"));
17298+ CLEAR_TX_IRQ(0, TX_PRIO_LOW);
17299 SK_PNMI_CNT_TX_INTR(pAC, 0);
17300 spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
17301 FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]);
17302@@ -1079,25 +2242,27 @@
17303 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
17304 SK_DBGCAT_DRV_INT_SRC,
17305 ("EOF SY TX1 IRQ\n"));
17306+ CLEAR_TX_IRQ(0, TX_PRIO_HIGH);
17307 SK_PNMI_CNT_TX_INTR(pAC, 0);
17308 spin_lock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock);
17309 FreeTxDescriptors(pAC, 0, TX_PRIO_HIGH);
17310 spin_unlock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock);
17311- ClearTxIrq(pAC, 0, TX_PRIO_HIGH);
17312 }
17313 #endif
17314 #endif
17315
17316- /* do all IO at once */
17317- if (IntSrc & IS_R1_F)
17318- ClearAndStartRx(pAC, 0);
17319-#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
17320- if (IntSrc & IS_XA1_F)
17321- ClearTxIrq(pAC, 0, TX_PRIO_LOW);
17322-#endif
17323 SK_IN32(pAC->IoBase, B0_ISRC, &IntSrc);
17324 } /* while (IntSrc & IRQ_MASK != 0) */
17325+#endif
17326
17327+#ifndef CONFIG_SK98LIN_NAPI
17328+ spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
17329+ FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]);
17330+ spin_unlock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
17331+ ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE);
17332+ START_RX(0);
17333+#endif
17334+
17335 IntSrc &= pAC->GIni.GIValIrqMask;
17336 if ((IntSrc & SPECIAL_IRQS) || pAC->CheckQueue) {
17337 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
17338@@ -1109,43 +2274,15 @@
17339
17340 SkEventDispatcher(pAC, pAC->IoBase);
17341 spin_unlock(&pAC->SlowPathLock);
17342+ START_RX(0);
17343 }
17344- /*
17345- * do it all again is case we cleared an interrupt that
17346- * came in after handling the ring (OUTs may be delayed
17347- * in hardware buffers, but are through after IN)
17348- *
17349- * rroesler: has been commented out and shifted to
17350- * SkGeDrvEvent(), because it is timer
17351- * guarded now
17352- *
17353- ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE);
17354- */
17355
17356 /* IRQ is processed - Enable IRQs again*/
17357 SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
17358
17359- return SkIsrRetHandled;
17360-} /* SkGeIsrOnePort */
17361+ return SkIsrRetHandled;
17362
17363-#ifdef CONFIG_NET_POLL_CONTROLLER
17364-/****************************************************************************
17365- *
17366- * SkGePollController - polling receive, for netconsole
17367- *
17368- * Description:
17369- * Polling receive - used by netconsole and other diagnostic tools
17370- * to allow network i/o with interrupts disabled.
17371- *
17372- * Returns: N/A
17373- */
17374-static void SkGePollController(struct net_device *dev)
17375-{
17376- disable_irq(dev->irq);
17377- SkGeIsr(dev->irq, dev);
17378- enable_irq(dev->irq);
17379-}
17380-#endif
17381+} /* SkGeIsrOnePort */
17382
17383 /****************************************************************************
17384 *
17385@@ -1164,27 +2301,34 @@
17386 * != 0 on error
17387 */
17388 static int SkGeOpen(
17389-struct SK_NET_DEVICE *dev)
17390+struct SK_NET_DEVICE *dev) /* the device that is to be opened */
17391 {
17392- DEV_NET *pNet;
17393- SK_AC *pAC;
17394- unsigned long Flags; /* for spin lock */
17395- int i;
17396- SK_EVPARA EvPara; /* an event parameter union */
17397+ DEV_NET *pNet = (DEV_NET*) dev->priv;
17398+ SK_AC *pAC = pNet->pAC;
17399+ unsigned long Flags; /* for the spin locks */
17400+ int CurrMac; /* loop ctr for ports */
17401+ unsigned long InitFlags;
17402+ struct proc_dir_entry *pProcFile;
17403
17404- pNet = netdev_priv(dev);
17405- pAC = pNet->pAC;
17406-
17407 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
17408 ("SkGeOpen: pAC=0x%lX:\n", (unsigned long)pAC));
17409
17410-#ifdef SK_DIAG_SUPPORT
17411+#ifdef SK_ASF
17412+ spin_lock(&pAC->InitLock);
17413+#endif
17414+#ifndef SK_ASF
17415+ spin_lock_irqsave(&pAC->InitLock, InitFlags);
17416+#endif
17417+
17418 if (pAC->DiagModeActive == DIAG_ACTIVE) {
17419 if (pAC->Pnmi.DiagAttached == SK_DIAG_RUNNING) {
17420 return (-1); /* still in use by diag; deny actions */
17421 }
17422 }
17423-#endif
17424+
17425+ if (!try_module_get(THIS_MODULE)) {
17426+ return (-1); /* increase of usage count not possible */
17427+ }
17428
17429 /* Set blink mode */
17430 if ((pAC->PciDev->vendor == 0x1186) || (pAC->PciDev->vendor == 0x11ab ))
17431@@ -1193,6 +2337,7 @@
17432 if (pAC->BoardLevel == SK_INIT_DATA) {
17433 /* level 1 init common modules here */
17434 if (SkGeInit(pAC, pAC->IoBase, SK_INIT_IO) != 0) {
17435+ module_put(THIS_MODULE); /* decrease usage count */
17436 printk("%s: HWInit (1) failed.\n", pAC->dev[pNet->PortNr]->name);
17437 return (-1);
17438 }
17439@@ -1202,12 +2347,21 @@
17440 SkAddrInit (pAC, pAC->IoBase, SK_INIT_IO);
17441 SkRlmtInit (pAC, pAC->IoBase, SK_INIT_IO);
17442 SkTimerInit (pAC, pAC->IoBase, SK_INIT_IO);
17443+#ifdef SK_ASF
17444+ SkAsfInit (pAC, pAC->IoBase, SK_INIT_IO);
17445+#endif
17446 pAC->BoardLevel = SK_INIT_IO;
17447+#ifdef Y2_RECOVERY
17448+ /* mark entries invalid */
17449+ pAC->LastPort = 3;
17450+ pAC->LastOpc = 0xFF;
17451+#endif
17452 }
17453
17454 if (pAC->BoardLevel != SK_INIT_RUN) {
17455 /* tschilling: Level 2 init modules here, check return value. */
17456 if (SkGeInit(pAC, pAC->IoBase, SK_INIT_RUN) != 0) {
17457+ module_put(THIS_MODULE); /* decrease usage count */
17458 printk("%s: HWInit (2) failed.\n", pAC->dev[pNet->PortNr]->name);
17459 return (-1);
17460 }
17461@@ -1217,47 +2371,122 @@
17462 SkAddrInit (pAC, pAC->IoBase, SK_INIT_RUN);
17463 SkRlmtInit (pAC, pAC->IoBase, SK_INIT_RUN);
17464 SkTimerInit (pAC, pAC->IoBase, SK_INIT_RUN);
17465+#ifdef SK_ASF
17466+ SkAsfInit (pAC, pAC->IoBase, SK_INIT_RUN);
17467+#endif
17468 pAC->BoardLevel = SK_INIT_RUN;
17469 }
17470
17471- for (i=0; i<pAC->GIni.GIMacsFound; i++) {
17472- /* Enable transmit descriptor polling. */
17473- SkGePollTxD(pAC, pAC->IoBase, i, SK_TRUE);
17474- FillRxRing(pAC, &pAC->RxPort[i]);
17475+ for (CurrMac=0; CurrMac<pAC->GIni.GIMacsFound; CurrMac++) {
17476+ if (!CHIP_ID_YUKON_2(pAC)) {
17477+ /* Enable transmit descriptor polling. */
17478+ SkGePollTxD(pAC, pAC->IoBase, CurrMac, SK_TRUE);
17479+ FillRxRing(pAC, &pAC->RxPort[CurrMac]);
17480+ SkMacRxTxEnable(pAC, pAC->IoBase, pNet->PortNr);
17481+ }
17482 }
17483- SkGeYellowLED(pAC, pAC->IoBase, 1);
17484
17485- StartDrvCleanupTimer(pAC);
17486+ SkGeYellowLED(pAC, pAC->IoBase, 1);
17487 SkDimEnableModerationIfNeeded(pAC);
17488- SkDimDisplayModerationSettings(pAC);
17489
17490- pAC->GIni.GIValIrqMask &= IRQ_MASK;
17491-
17492- /* enable Interrupts */
17493- SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
17494- SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK);
17495+ if (!CHIP_ID_YUKON_2(pAC)) {
17496+ /*
17497+ ** Has been setup already at SkGeInit(SK_INIT_IO),
17498+ ** but additional masking added for Genesis & Yukon
17499+ ** chipsets -> modify it...
17500+ */
17501+ pAC->GIni.GIValIrqMask &= IRQ_MASK;
17502+#ifndef USE_TX_COMPLETE
17503+ pAC->GIni.GIValIrqMask &= ~(TX_COMPL_IRQS);
17504+#endif
17505+ }
17506
17507 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
17508
17509 if ((pAC->RlmtMode != 0) && (pAC->MaxPorts == 0)) {
17510- EvPara.Para32[0] = pAC->RlmtNets;
17511- EvPara.Para32[1] = -1;
17512- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_SET_NETS,
17513- EvPara);
17514- EvPara.Para32[0] = pAC->RlmtMode;
17515- EvPara.Para32[1] = 0;
17516- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_MODE_CHANGE,
17517- EvPara);
17518+ SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_SET_NETS,
17519+ pAC->RlmtNets, -1, SK_FALSE);
17520+ SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_MODE_CHANGE,
17521+ pAC->RlmtMode, 0, SK_FALSE);
17522 }
17523
17524- EvPara.Para32[0] = pNet->NetNr;
17525- EvPara.Para32[1] = -1;
17526- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara);
17527- SkEventDispatcher(pAC, pAC->IoBase);
17528+ SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_START,
17529+ pNet->NetNr, -1, SK_TRUE);
17530 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
17531
17532+#ifdef Y2_RECOVERY
17533+ pNet->TimerExpired = SK_FALSE;
17534+ pNet->InRecover = SK_FALSE;
17535+ pNet->NetConsoleMode = SK_FALSE;
17536+
17537+ /* Initialize the kernel timer */
17538+ init_timer(&pNet->KernelTimer);
17539+ pNet->KernelTimer.function = SkGeHandleKernelTimer;
17540+ pNet->KernelTimer.data = (unsigned long) pNet;
17541+ pNet->KernelTimer.expires = jiffies + (HZ/4); /* initially 250ms */
17542+ add_timer(&pNet->KernelTimer);
17543+#endif
17544+#ifdef SK_ASF
17545+ /* Set OS Present Flag in ASF Status and Command Register */
17546+ SK_IN32( pAC->IoBase, REG_ASF_STATUS_CMD, &TmpVal32 );
17547+ TmpVal32 |= BIT_4;
17548+ SK_OUT32( pAC->IoBase, REG_ASF_STATUS_CMD, TmpVal32 );
17549+
17550+ YlciDisablePattern(pAC, pAC->IoBase, 0, 5); // Disable ARP pattern, OS is now responsible for ARP handling
17551+
17552+ if (pAC->AsfData.DualMode == SK_GEASF_Y2_DUALPORT) {
17553+ YlciDisablePattern(pAC, pAC->IoBase, 1, 5); // Disable ARP pattern, OS is now responsible for ARP handling
17554+ }
17555+
17556+ if (is_closed) {
17557+ Para.Para32[0] = pAC->ActivePort;
17558+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_NET_UP, Para);
17559+ }
17560+#endif
17561+
17562+ /* enable Interrupts */
17563+ SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
17564+ SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK);
17565+
17566 pAC->MaxPorts++;
17567
17568+ /* Set state to open */
17569+ is_closed = 0;
17570+
17571+ /* Initialize the procfs timer */
17572+ init_timer(&pNet->ProcfsTimer);
17573+ pNet->ProcfsTimer.function = SkGeHandleProcfsTimer;
17574+ pNet->ProcfsTimer.data = (unsigned long) pNet;
17575+ pNet->ProcfsTimer.expires = jiffies + HZ*5; /* initially 5 secs */
17576+ add_timer(&pNet->ProcfsTimer);
17577+
17578+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) {
17579+ SK_OUT8(pAC->IoBase, B0_POWER_CTRL, (SK_U8)(PC_VAUX_ENA | PC_VCC_ENA |
17580+ PC_VAUX_OFF | PC_VCC_ON));
17581+ }
17582+
17583+#ifdef SK_ASF
17584+ spin_unlock(&pAC->InitLock);
17585+#endif
17586+#ifndef SK_ASF
17587+ spin_unlock_irqrestore(&pAC->InitLock, InitFlags);
17588+#endif
17589+
17590+#ifdef CONFIG_PROC_FS
17591+ if ( (!pAC->InterfaceUp[pNet->NetNr]) &&
17592+ (pSkRootDir) ) {
17593+ pProcFile = create_proc_entry(pAC->dev[pNet->NetNr]->name, S_IRUGO, pSkRootDir);
17594+ pProcFile->proc_fops = &sk_proc_fops;
17595+ pProcFile->data = dev;
17596+
17597+ /*
17598+ * Remember, interface dev nr pNet->NetNr is up
17599+ */
17600+ pAC->InterfaceUp[pNet->NetNr] = 1;
17601+
17602+ strcpy(pNet->CurrentName, pNet->pAC->dev[pNet->NetNr]->name);
17603+ }
17604+#endif
17605
17606 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
17607 ("SkGeOpen suceeded\n"));
17608@@ -1278,32 +2507,44 @@
17609 * error code - on error
17610 */
17611 static int SkGeClose(
17612-struct SK_NET_DEVICE *dev)
17613+struct SK_NET_DEVICE *dev) /* the device that is to be closed */
17614 {
17615- DEV_NET *pNet;
17616- DEV_NET *newPtrNet;
17617- SK_AC *pAC;
17618-
17619- unsigned long Flags; /* for spin lock */
17620- int i;
17621- int PortIdx;
17622- SK_EVPARA EvPara;
17623-
17624+ DEV_NET *pNet = (DEV_NET*) dev->priv;
17625+ SK_AC *pAC = pNet->pAC;
17626+ DEV_NET *newPtrNet;
17627+ unsigned long Flags; /* for the spin locks */
17628+ unsigned long InitFlags; /* for the spin locks */
17629+ int CurrMac; /* loop ctr for the current MAC */
17630+ int PortIdx;
17631+#ifdef CONFIG_SK98LIN_NAPI
17632+ int WorkToDo = 1; /* min(*budget, dev->quota); */
17633+ int WorkDone = 0;
17634+#endif
17635 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
17636 ("SkGeClose: pAC=0x%lX ", (unsigned long)pAC));
17637+ spin_lock_irqsave(&pAC->InitLock, InitFlags);
17638+#ifdef SK_ASF
17639+ SkAsfDeInit(pAC, pAC->IoBase);
17640+#endif
17641
17642- pNet = netdev_priv(dev);
17643- pAC = pNet->pAC;
17644+#ifdef CONFIG_PROC_FS
17645+ del_timer(&pNet->ProcfsTimer);
17646+#endif
17647+
17648+#ifdef Y2_RECOVERY
17649+ pNet->InRecover = SK_TRUE;
17650+ del_timer(&pNet->KernelTimer);
17651+#endif
17652
17653-#ifdef SK_DIAG_SUPPORT
17654 if (pAC->DiagModeActive == DIAG_ACTIVE) {
17655 if (pAC->DiagFlowCtrl == SK_FALSE) {
17656+ module_put(THIS_MODULE);
17657 /*
17658 ** notify that the interface which has been closed
17659 ** by operator interaction must not be started up
17660 ** again when the DIAG has finished.
17661 */
17662- newPtrNet = netdev_priv(pAC->dev[0]);
17663+ newPtrNet = (DEV_NET *) pAC->dev[0]->priv;
17664 if (newPtrNet == pNet) {
17665 pAC->WasIfUp[0] = SK_FALSE;
17666 } else {
17667@@ -1314,17 +2555,19 @@
17668 pAC->DiagFlowCtrl = SK_FALSE;
17669 }
17670 }
17671-#endif
17672
17673+#ifdef SK_ASF
17674+ netif_stop_queue(dev);
17675+ netif_carrier_off(dev);
17676+#else
17677 netif_stop_queue(dev);
17678+#endif
17679
17680 if (pAC->RlmtNets == 1)
17681 PortIdx = pAC->ActivePort;
17682 else
17683 PortIdx = pNet->NetNr;
17684
17685- StopDrvCleanupTimer(pAC);
17686-
17687 /*
17688 * Clear multicast table, promiscuous mode ....
17689 */
17690@@ -1336,46 +2579,140 @@
17691 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
17692 /* disable interrupts */
17693 SK_OUT32(pAC->IoBase, B0_IMSK, 0);
17694- EvPara.Para32[0] = pNet->NetNr;
17695- EvPara.Para32[1] = -1;
17696- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
17697- SkEventDispatcher(pAC, pAC->IoBase);
17698- SK_OUT32(pAC->IoBase, B0_IMSK, 0);
17699+#ifndef SK_ASF
17700+ SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP,
17701+ pNet->NetNr, -1, SK_TRUE);
17702 /* stop the hardware */
17703- SkGeDeInit(pAC, pAC->IoBase);
17704- pAC->BoardLevel = SK_INIT_DATA;
17705+ SK_OUT32(pAC->IoBase, B0_IMSK, 0);
17706+#endif
17707+
17708+ if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 1)) {
17709+ /* RLMT check link state mode */
17710+ for (CurrMac=0; CurrMac<pAC->GIni.GIMacsFound; CurrMac++) {
17711+ if (CHIP_ID_YUKON_2(pAC)) {
17712+#ifdef SK_ASF
17713+ SkY2PortStop( pAC,
17714+ pAC->IoBase,
17715+ CurrMac,
17716+ SK_STOP_RX,
17717+ SK_HARD_RST);
17718+ SkY2PortStop( pAC,
17719+ pAC->IoBase,
17720+ CurrMac,
17721+ SK_STOP_TX,
17722+ SK_HARD_RST);
17723+#else
17724+ SkY2PortStop( pAC,
17725+ pAC->IoBase,
17726+ CurrMac,
17727+ SK_STOP_ALL,
17728+ SK_HARD_RST);
17729+#endif
17730+ } else {
17731+ SkGeStopPort( pAC,
17732+ pAC->IoBase,
17733+ CurrMac,
17734+ SK_STOP_ALL,
17735+ SK_HARD_RST);
17736+ }
17737+ } /* for */
17738+ } else {
17739+ /* Single link or single port */
17740+ if (CHIP_ID_YUKON_2(pAC)) {
17741+#ifdef SK_ASF
17742+ SkY2PortStop( pAC,
17743+ pAC->IoBase,
17744+ PortIdx,
17745+ SK_STOP_RX,
17746+ SK_HARD_RST);
17747+ SkY2PortStop( pAC,
17748+ pAC->IoBase,
17749+ PortIdx,
17750+ SK_STOP_TX,
17751+ SK_HARD_RST);
17752+#else
17753+ SkY2PortStop( pAC,
17754+ pAC->IoBase,
17755+ PortIdx,
17756+ SK_STOP_ALL,
17757+ SK_HARD_RST);
17758+#endif
17759+ } else {
17760+ SkGeStopPort( pAC,
17761+ pAC->IoBase,
17762+ PortIdx,
17763+ SK_STOP_ALL,
17764+ SK_HARD_RST);
17765+ }
17766+ }
17767 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
17768 } else {
17769-
17770 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
17771- EvPara.Para32[0] = pNet->NetNr;
17772- EvPara.Para32[1] = -1;
17773- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
17774- SkPnmiEvent(pAC, pAC->IoBase, SK_PNMI_EVT_XMAC_RESET, EvPara);
17775- SkEventDispatcher(pAC, pAC->IoBase);
17776+#ifdef SK_ASF
17777+ SkY2PortStop(pAC, pAC->IoBase, pNet->PortNr,
17778+ SK_STOP_RX, SK_HARD_RST);
17779+ SkY2PortStop(pAC, pAC->IoBase, pNet->PortNr,
17780+ SK_STOP_TX, SK_HARD_RST);
17781+#else
17782+ SkY2PortStop(pAC, pAC->IoBase, pNet->PortNr,
17783+ SK_STOP_ALL, SK_HARD_RST);
17784+#endif
17785 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
17786
17787 /* Stop port */
17788 spin_lock_irqsave(&pAC->TxPort[pNet->PortNr]
17789 [TX_PRIO_LOW].TxDesRingLock, Flags);
17790- SkGeStopPort(pAC, pAC->IoBase, pNet->PortNr,
17791- SK_STOP_ALL, SK_HARD_RST);
17792+ if (CHIP_ID_YUKON_2(pAC)) {
17793+ SkY2PortStop(pAC, pAC->IoBase, pNet->PortNr,
17794+ SK_STOP_ALL, SK_HARD_RST);
17795+ }
17796+ else {
17797+ SkGeStopPort(pAC, pAC->IoBase, pNet->PortNr,
17798+ SK_STOP_ALL, SK_HARD_RST);
17799+ }
17800 spin_unlock_irqrestore(&pAC->TxPort[pNet->PortNr]
17801 [TX_PRIO_LOW].TxDesRingLock, Flags);
17802 }
17803
17804 if (pAC->RlmtNets == 1) {
17805 /* clear all descriptor rings */
17806- for (i=0; i<pAC->GIni.GIMacsFound; i++) {
17807- ReceiveIrq(pAC, &pAC->RxPort[i], SK_TRUE);
17808- ClearRxRing(pAC, &pAC->RxPort[i]);
17809- ClearTxRing(pAC, &pAC->TxPort[i][TX_PRIO_LOW]);
17810+ for (CurrMac=0; CurrMac<pAC->GIni.GIMacsFound; CurrMac++) {
17811+ if (!CHIP_ID_YUKON_2(pAC)) {
17812+#ifdef CONFIG_SK98LIN_NAPI
17813+ WorkToDo = 1;
17814+ ReceiveIrq(pAC,&pAC->RxPort[CurrMac],
17815+ SK_TRUE,&WorkDone,WorkToDo);
17816+#else
17817+ ReceiveIrq(pAC,&pAC->RxPort[CurrMac],SK_TRUE);
17818+#endif
17819+ ClearRxRing(pAC, &pAC->RxPort[CurrMac]);
17820+ ClearTxRing(pAC, &pAC->TxPort[CurrMac][TX_PRIO_LOW]);
17821+ } else {
17822+ SkY2FreeRxBuffers(pAC, pAC->IoBase, CurrMac);
17823+ SkY2FreeTxBuffers(pAC, pAC->IoBase, CurrMac);
17824+ }
17825 }
17826 } else {
17827 /* clear port descriptor rings */
17828- ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE);
17829- ClearRxRing(pAC, &pAC->RxPort[pNet->PortNr]);
17830- ClearTxRing(pAC, &pAC->TxPort[pNet->PortNr][TX_PRIO_LOW]);
17831+ if (!CHIP_ID_YUKON_2(pAC)) {
17832+#ifdef CONFIG_SK98LIN_NAPI
17833+ WorkToDo = 1;
17834+ ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE, &WorkDone, WorkToDo);
17835+#else
17836+ ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE);
17837+#endif
17838+ ClearRxRing(pAC, &pAC->RxPort[pNet->PortNr]);
17839+ ClearTxRing(pAC, &pAC->TxPort[pNet->PortNr][TX_PRIO_LOW]);
17840+ }
17841+ else {
17842+ SkY2FreeRxBuffers(pAC, pAC->IoBase, pNet->PortNr);
17843+ SkY2FreeTxBuffers(pAC, pAC->IoBase, pNet->PortNr);
17844+ }
17845+ }
17846+
17847+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) {
17848+ SK_OUT8(pAC->IoBase, B0_POWER_CTRL, (SK_U8)(PC_VAUX_ENA | PC_VCC_ENA |
17849+ PC_VAUX_ON | PC_VCC_OFF));
17850 }
17851
17852 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
17853@@ -1386,6 +2723,13 @@
17854 sizeof(SK_PNMI_STRUCT_DATA));
17855
17856 pAC->MaxPorts--;
17857+ module_put(THIS_MODULE);
17858+
17859+#ifdef Y2_RECOVERY
17860+ pNet->InRecover = SK_FALSE;
17861+#endif
17862+ is_closed = 1;
17863+ spin_unlock_irqrestore(&pAC->InitLock, InitFlags);
17864
17865 return (0);
17866 } /* SkGeClose */
17867@@ -1412,7 +2756,7 @@
17868 SK_AC *pAC;
17869 int Rc; /* return code of XmitFrame */
17870
17871- pNet = netdev_priv(dev);
17872+ pNet = (DEV_NET*) dev->priv;
17873 pAC = pNet->pAC;
17874
17875 if ((!skb_shinfo(skb)->nr_frags) ||
17876@@ -1458,6 +2802,96 @@
17877 return (0);
17878 } /* SkGeXmit */
17879
17880+#ifdef CONFIG_SK98LIN_NAPI
17881+/*****************************************************************************
17882+ *
17883+ * SkGePoll - NAPI Rx polling callback for GEnesis and Yukon chipsets
17884+ *
17885+ * Description:
17886+ * Called by the Linux system in case NAPI polling is activated
17887+ *
17888+ * Returns:
17889+ * The number of work data still to be handled
17890+ */
17891+static int SkGePoll(struct net_device *dev, int *budget)
17892+{
17893+ SK_AC *pAC = ((DEV_NET*)(dev->priv))->pAC; /* pointer to adapter context */
17894+ int WorkToDo = min(*budget, dev->quota);
17895+ int WorkDone = 0;
17896+ unsigned long Flags;
17897+
17898+
17899+ if (pAC->dev[0] != pAC->dev[1]) {
17900+ spin_lock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock);
17901+ FreeTxDescriptors(pAC, &pAC->TxPort[1][TX_PRIO_LOW]);
17902+ spin_unlock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock);
17903+
17904+ ReceiveIrq(pAC, &pAC->RxPort[1], SK_TRUE, &WorkDone, WorkToDo);
17905+ CLEAR_AND_START_RX(1);
17906+ }
17907+ spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
17908+ FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]);
17909+ spin_unlock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
17910+
17911+ ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE, &WorkDone, WorkToDo);
17912+ CLEAR_AND_START_RX(0);
17913+
17914+ *budget -= WorkDone;
17915+ dev->quota -= WorkDone;
17916+
17917+ if(WorkDone < WorkToDo) {
17918+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
17919+ netif_rx_complete(dev);
17920+ pAC->GIni.GIValIrqMask |= (NAPI_DRV_IRQS);
17921+#ifndef USE_TX_COMPLETE
17922+ pAC->GIni.GIValIrqMask &= ~(TX_COMPL_IRQS);
17923+#endif
17924+ /* enable interrupts again */
17925+ SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
17926+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
17927+ }
17928+ return (WorkDone >= WorkToDo);
17929+} /* SkGePoll */
17930+#endif
17931+
17932+#ifdef SK_POLL_CONTROLLER
17933+/*****************************************************************************
17934+ *
17935+ * SkGeNetPoll - Polling "interrupt"
17936+ *
17937+ * Description:
17938+ * Polling 'interrupt' - used by things like netconsole and netdump
17939+ * to send skbs without having to re-enable interrupts.
17940+ * It's not called while the interrupt routine is executing.
17941+ */
17942+static void SkGeNetPoll(
17943+struct SK_NET_DEVICE *dev)
17944+{
17945+DEV_NET *pNet;
17946+SK_AC *pAC;
17947+
17948+ pNet = (DEV_NET*) dev->priv;
17949+ pAC = pNet->pAC;
17950+ pNet->NetConsoleMode = SK_TRUE;
17951+
17952+ /* Prevent any reconfiguration while handling
17953+ the 'interrupt' */
17954+ SK_OUT32(pAC->IoBase, B0_IMSK, 0);
17955+
17956+ if (!CHIP_ID_YUKON_2(pAC)) {
17957+ /* Handle the GENESIS Isr */
17958+ if (pAC->GIni.GIMacsFound == 2)
17959+ SkGeIsr(dev->irq, dev);
17960+ else
17961+ SkGeIsrOnePort(dev->irq, dev);
17962+ } else {
17963+ /* Handle the Yukon2 Isr */
17964+ SkY2Isr(dev->irq, dev);
17965+ }
17966+
17967+}
17968+#endif
17969+
17970
17971 /*****************************************************************************
17972 *
17973@@ -1482,7 +2916,7 @@
17974 * < 0 - on failure: other problems ( -> return failure to upper layers)
17975 */
17976 static int XmitFrame(
17977-SK_AC *pAC, /* pointer to adapter context */
17978+SK_AC *pAC, /* pointer to adapter context */
17979 TX_PORT *pTxPort, /* pointer to struct of port to send to */
17980 struct sk_buff *pMessage) /* pointer to send-message */
17981 {
17982@@ -1490,17 +2924,22 @@
17983 TXD *pOldTxd;
17984 unsigned long Flags;
17985 SK_U64 PhysAddr;
17986+ int Protocol;
17987+ int IpHeaderLength;
17988 int BytesSend = pMessage->len;
17989
17990 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, ("X"));
17991
17992 spin_lock_irqsave(&pTxPort->TxDesRingLock, Flags);
17993 #ifndef USE_TX_COMPLETE
17994- FreeTxDescriptors(pAC, pTxPort);
17995+ if ((pTxPort->TxdRingPrevFree - pTxPort->TxdRingFree) > 6) {
17996+ FreeTxDescriptors(pAC, pTxPort);
17997+ pTxPort->TxdRingPrevFree = pTxPort->TxdRingFree;
17998+ }
17999 #endif
18000 if (pTxPort->TxdRingFree == 0) {
18001 /*
18002- ** no enough free descriptors in ring at the moment.
18003+ ** not enough free descriptors in ring at the moment.
18004 ** Maybe free'ing some old one help?
18005 */
18006 FreeTxDescriptors(pAC, pTxPort);
18007@@ -1527,7 +2966,7 @@
18008 ** This is to resolve faulty padding by the HW with 0xaa bytes.
18009 */
18010 if (BytesSend < C_LEN_ETHERNET_MINSIZE) {
18011- if (skb_padto(pMessage, C_LEN_ETHERNET_MINSIZE)) {
18012+ if ((pMessage = skb_padto(pMessage, C_LEN_ETHERNET_MINSIZE)) == NULL) {
18013 spin_unlock_irqrestore(&pTxPort->TxDesRingLock, Flags);
18014 return 0;
18015 }
18016@@ -1561,11 +3000,9 @@
18017 pTxd->VDataHigh = (SK_U32) (PhysAddr >> 32);
18018 pTxd->pMBuf = pMessage;
18019
18020- if (pMessage->ip_summed == CHECKSUM_PARTIAL) {
18021- u16 hdrlen = pMessage->h.raw - pMessage->data;
18022- u16 offset = hdrlen + pMessage->csum_offset;
18023-
18024- if ((pMessage->h.ipiph->protocol == IPPROTO_UDP ) &&
18025+ if (pMessage->ip_summed == CHECKSUM_PARTIAL) {
18026+ Protocol = ((SK_U8)pMessage->data[C_OFFSET_IPPROTO] & 0xff);
18027+ if ((Protocol == C_PROTO_ID_UDP) &&
18028 (pAC->GIni.GIChipRev == 0) &&
18029 (pAC->GIni.GIChipId == CHIP_ID_YUKON)) {
18030 pTxd->TBControl = BMU_TCP_CHECK;
18031@@ -1573,9 +3010,14 @@
18032 pTxd->TBControl = BMU_UDP_CHECK;
18033 }
18034
18035- pTxd->TcpSumOfs = 0;
18036- pTxd->TcpSumSt = hdrlen;
18037- pTxd->TcpSumWr = offset;
18038+ IpHeaderLength = (SK_U8)pMessage->data[C_OFFSET_IPHEADER];
18039+ IpHeaderLength = (IpHeaderLength & 0xf) * 4;
18040+ pTxd->TcpSumOfs = 0; /* PH-Checksum already calculated */
18041+ pTxd->TcpSumSt = C_LEN_ETHERMAC_HEADER + IpHeaderLength +
18042+ (Protocol == C_PROTO_ID_UDP ?
18043+ C_OFFSET_UDPHEADER_UDPCS :
18044+ C_OFFSET_TCPHEADER_TCPCS);
18045+ pTxd->TcpSumWr = C_LEN_ETHERMAC_HEADER + IpHeaderLength;
18046
18047 pTxd->TBControl |= BMU_OWN | BMU_STF |
18048 BMU_SW | BMU_EOF |
18049@@ -1583,7 +3025,7 @@
18050 BMU_IRQ_EOF |
18051 #endif
18052 pMessage->len;
18053- } else {
18054+ } else {
18055 pTxd->TBControl = BMU_OWN | BMU_STF | BMU_CHECK |
18056 BMU_SW | BMU_EOF |
18057 #ifdef USE_TX_COMPLETE
18058@@ -1638,10 +3080,11 @@
18059 TXD *pTxdLst;
18060 int CurrFrag;
18061 int BytesSend;
18062+ int IpHeaderLength;
18063+ int Protocol;
18064 skb_frag_t *sk_frag;
18065 SK_U64 PhysAddr;
18066 unsigned long Flags;
18067- SK_U32 Control;
18068
18069 spin_lock_irqsave(&pTxPort->TxDesRingLock, Flags);
18070 #ifndef USE_TX_COMPLETE
18071@@ -1664,6 +3107,7 @@
18072 pTxdFst = pTxd;
18073 pTxdLst = pTxd;
18074 BytesSend = 0;
18075+ Protocol = 0;
18076
18077 /*
18078 ** Map the first fragment (header) into the DMA-space
18079@@ -1680,32 +3124,33 @@
18080 /*
18081 ** Does the HW need to evaluate checksum for TCP or UDP packets?
18082 */
18083- if (pMessage->ip_summed == CHECKSUM_PARTIAL) {
18084- u16 hdrlen = pMessage->h.raw - pMessage->data;
18085- u16 offset = hdrlen + pMessage->csum_offset;
18086-
18087- Control = BMU_STFWD;
18088-
18089+ if (pMessage->ip_summed == CHECKSUM_PARTIAL) {
18090+ pTxd->TBControl = BMU_STF | BMU_STFWD | skb_headlen(pMessage);
18091 /*
18092 ** We have to use the opcode for tcp here, because the
18093 ** opcode for udp is not working in the hardware yet
18094 ** (Revision 2.0)
18095 */
18096- if ((pMessage->h.ipiph->protocol == IPPROTO_UDP ) &&
18097+ Protocol = ((SK_U8)pMessage->data[C_OFFSET_IPPROTO] & 0xff);
18098+ if ((Protocol == C_PROTO_ID_UDP) &&
18099 (pAC->GIni.GIChipRev == 0) &&
18100 (pAC->GIni.GIChipId == CHIP_ID_YUKON)) {
18101- Control |= BMU_TCP_CHECK;
18102+ pTxd->TBControl |= BMU_TCP_CHECK;
18103 } else {
18104- Control |= BMU_UDP_CHECK;
18105+ pTxd->TBControl |= BMU_UDP_CHECK;
18106 }
18107
18108- pTxd->TcpSumOfs = 0;
18109- pTxd->TcpSumSt = hdrlen;
18110- pTxd->TcpSumWr = offset;
18111- } else
18112- Control = BMU_CHECK | BMU_SW;
18113-
18114- pTxd->TBControl = BMU_STF | Control | skb_headlen(pMessage);
18115+ IpHeaderLength = ((SK_U8)pMessage->data[C_OFFSET_IPHEADER] & 0xf)*4;
18116+ pTxd->TcpSumOfs = 0; /* PH-Checksum already claculated */
18117+ pTxd->TcpSumSt = C_LEN_ETHERMAC_HEADER + IpHeaderLength +
18118+ (Protocol == C_PROTO_ID_UDP ?
18119+ C_OFFSET_UDPHEADER_UDPCS :
18120+ C_OFFSET_TCPHEADER_TCPCS);
18121+ pTxd->TcpSumWr = C_LEN_ETHERMAC_HEADER + IpHeaderLength;
18122+ } else {
18123+ pTxd->TBControl = BMU_CHECK | BMU_SW | BMU_STF |
18124+ skb_headlen(pMessage);
18125+ }
18126
18127 pTxd = pTxd->pNextTxd;
18128 pTxPort->TxdRingFree--;
18129@@ -1729,18 +3174,40 @@
18130 pTxd->VDataHigh = (SK_U32) (PhysAddr >> 32);
18131 pTxd->pMBuf = pMessage;
18132
18133- pTxd->TBControl = Control | BMU_OWN | sk_frag->size;
18134+ /*
18135+ ** Does the HW need to evaluate checksum for TCP or UDP packets?
18136+ */
18137+ if (pMessage->ip_summed == CHECKSUM_PARTIAL) {
18138+ pTxd->TBControl = BMU_OWN | BMU_SW | BMU_STFWD;
18139+ /*
18140+ ** We have to use the opcode for tcp here because the
18141+ ** opcode for udp is not working in the hardware yet
18142+ ** (revision 2.0)
18143+ */
18144+ if ((Protocol == C_PROTO_ID_UDP) &&
18145+ (pAC->GIni.GIChipRev == 0) &&
18146+ (pAC->GIni.GIChipId == CHIP_ID_YUKON)) {
18147+ pTxd->TBControl |= BMU_TCP_CHECK;
18148+ } else {
18149+ pTxd->TBControl |= BMU_UDP_CHECK;
18150+ }
18151+ } else {
18152+ pTxd->TBControl = BMU_CHECK | BMU_SW | BMU_OWN;
18153+ }
18154
18155 /*
18156 ** Do we have the last fragment?
18157 */
18158 if( (CurrFrag+1) == skb_shinfo(pMessage)->nr_frags ) {
18159 #ifdef USE_TX_COMPLETE
18160- pTxd->TBControl |= BMU_EOF | BMU_IRQ_EOF;
18161+ pTxd->TBControl |= BMU_EOF | BMU_IRQ_EOF | sk_frag->size;
18162 #else
18163- pTxd->TBControl |= BMU_EOF;
18164+ pTxd->TBControl |= BMU_EOF | sk_frag->size;
18165 #endif
18166 pTxdFst->TBControl |= BMU_OWN | BMU_SW;
18167+
18168+ } else {
18169+ pTxd->TBControl |= sk_frag->size;
18170 }
18171 pTxdLst = pTxd;
18172 pTxd = pTxd->pNextTxd;
18173@@ -1894,7 +3361,7 @@
18174 SK_U16 Length; /* data fragment length */
18175 SK_U64 PhysAddr; /* physical address of a rx buffer */
18176
18177- pMsgBlock = alloc_skb(pAC->RxBufSize, GFP_ATOMIC);
18178+ pMsgBlock = alloc_skb(pRxPort->RxBufSize, GFP_ATOMIC);
18179 if (pMsgBlock == NULL) {
18180 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
18181 SK_DBGCAT_DRV_ENTRY,
18182@@ -1908,12 +3375,12 @@
18183 pRxd = pRxPort->pRxdRingTail;
18184 pRxPort->pRxdRingTail = pRxd->pNextRxd;
18185 pRxPort->RxdRingFree--;
18186- Length = pAC->RxBufSize;
18187+ Length = pRxPort->RxBufSize;
18188 PhysAddr = (SK_U64) pci_map_page(pAC->PciDev,
18189 virt_to_page(pMsgBlock->data),
18190 ((unsigned long) pMsgBlock->data &
18191 ~PAGE_MASK),
18192- pAC->RxBufSize - 2,
18193+ pRxPort->RxBufSize - 2,
18194 PCI_DMA_FROMDEVICE);
18195
18196 pRxd->VDataLow = (SK_U32) (PhysAddr & 0xffffffff);
18197@@ -1953,7 +3420,7 @@
18198 pRxd = pRxPort->pRxdRingTail;
18199 pRxPort->pRxdRingTail = pRxd->pNextRxd;
18200 pRxPort->RxdRingFree--;
18201- Length = pAC->RxBufSize;
18202+ Length = pRxPort->RxBufSize;
18203
18204 pRxd->VDataLow = PhysLow;
18205 pRxd->VDataHigh = PhysHigh;
18206@@ -1978,28 +3445,40 @@
18207 * Returns: N/A
18208 */
18209 static void ReceiveIrq(
18210- SK_AC *pAC, /* pointer to adapter context */
18211- RX_PORT *pRxPort, /* pointer to receive port struct */
18212- SK_BOOL SlowPathLock) /* indicates if SlowPathLock is needed */
18213-{
18214-RXD *pRxd; /* pointer to receive descriptors */
18215-SK_U32 Control; /* control field of descriptor */
18216-struct sk_buff *pMsg; /* pointer to message holding frame */
18217-struct sk_buff *pNewMsg; /* pointer to a new message for copying frame */
18218-int FrameLength; /* total length of received frame */
18219-SK_MBUF *pRlmtMbuf; /* ptr to a buffer for giving a frame to rlmt */
18220-SK_EVPARA EvPara; /* an event parameter union */
18221-unsigned long Flags; /* for spin lock */
18222-int PortIndex = pRxPort->PortIndex;
18223-unsigned int Offset;
18224-unsigned int NumBytes;
18225-unsigned int ForRlmt;
18226-SK_BOOL IsBc;
18227-SK_BOOL IsMc;
18228-SK_BOOL IsBadFrame; /* Bad frame */
18229-
18230-SK_U32 FrameStat;
18231-SK_U64 PhysAddr;
18232+#ifdef CONFIG_SK98LIN_NAPI
18233+SK_AC *pAC, /* pointer to adapter context */
18234+RX_PORT *pRxPort, /* pointer to receive port struct */
18235+SK_BOOL SlowPathLock, /* indicates if SlowPathLock is needed */
18236+int *WorkDone,
18237+int WorkToDo)
18238+#else
18239+SK_AC *pAC, /* pointer to adapter context */
18240+RX_PORT *pRxPort, /* pointer to receive port struct */
18241+SK_BOOL SlowPathLock) /* indicates if SlowPathLock is needed */
18242+#endif
18243+{
18244+ RXD *pRxd; /* pointer to receive descriptors */
18245+ struct sk_buff *pMsg; /* pointer to message holding frame */
18246+ struct sk_buff *pNewMsg; /* pointer to new message for frame copy */
18247+ SK_MBUF *pRlmtMbuf; /* ptr to buffer for giving frame to RLMT */
18248+ SK_EVPARA EvPara; /* an event parameter union */
18249+ SK_U32 Control; /* control field of descriptor */
18250+ unsigned long Flags; /* for spin lock handling */
18251+ int PortIndex = pRxPort->PortIndex;
18252+ int FrameLength; /* total length of received frame */
18253+ int IpFrameLength; /* IP length of the received frame */
18254+ unsigned int Offset;
18255+ unsigned int NumBytes;
18256+ unsigned int RlmtNotifier;
18257+ SK_BOOL IsBc; /* we received a broadcast packet */
18258+ SK_BOOL IsMc; /* we received a multicast packet */
18259+ SK_BOOL IsBadFrame; /* the frame received is bad! */
18260+ SK_U32 FrameStat;
18261+ unsigned short Csum1;
18262+ unsigned short Csum2;
18263+ unsigned short Type;
18264+ int Result;
18265+ SK_U64 PhysAddr;
18266
18267 rx_start:
18268 /* do forever; exit if BMU_OWN found */
18269@@ -2021,6 +3500,13 @@
18270
18271 Control = pRxd->RBControl;
18272
18273+#ifdef CONFIG_SK98LIN_NAPI
18274+ if (*WorkDone >= WorkToDo) {
18275+ break;
18276+ }
18277+ (*WorkDone)++;
18278+#endif
18279+
18280 /* check if this descriptor is ready */
18281 if ((Control & BMU_OWN) != 0) {
18282 /* this descriptor is not yet ready */
18283@@ -2029,11 +3515,10 @@
18284 FillRxRing(pAC, pRxPort);
18285 return;
18286 }
18287- pAC->DynIrqModInfo.NbrProcessedDescr++;
18288
18289 /* get length of frame and check it */
18290 FrameLength = Control & BMU_BBC;
18291- if (FrameLength > pAC->RxBufSize) {
18292+ if (FrameLength > pRxPort->RxBufSize) {
18293 goto rx_failed;
18294 }
18295
18296@@ -2048,8 +3533,8 @@
18297 FrameStat = pRxd->FrameStat;
18298
18299 /* check for frame length mismatch */
18300-#define XMR_FS_LEN_SHIFT 18
18301-#define GMR_FS_LEN_SHIFT 16
18302+#define XMR_FS_LEN_SHIFT 18
18303+#define GMR_FS_LEN_SHIFT 16
18304 if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
18305 if (FrameLength != (SK_U32) (FrameStat >> XMR_FS_LEN_SHIFT)) {
18306 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
18307@@ -2059,8 +3544,7 @@
18308 (SK_U32) (FrameStat >> XMR_FS_LEN_SHIFT)));
18309 goto rx_failed;
18310 }
18311- }
18312- else {
18313+ } else {
18314 if (FrameLength != (SK_U32) (FrameStat >> GMR_FS_LEN_SHIFT)) {
18315 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
18316 SK_DBGCAT_DRV_RX_PROGRESS,
18317@@ -2093,9 +3577,6 @@
18318 /* DumpMsg(pMsg, "Rx"); */
18319
18320 if ((Control & BMU_STAT_VAL) != BMU_STAT_VAL || (IsBadFrame)) {
18321-#if 0
18322- (FrameStat & (XMR_FS_ANY_ERR | XMR_FS_2L_VLAN)) != 0) {
18323-#endif
18324 /* there is a receive error in this frame */
18325 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
18326 SK_DBGCAT_DRV_RX_PROGRESS,
18327@@ -2103,6 +3584,20 @@
18328 "Control: %x\nRxStat: %x\n",
18329 Control, FrameStat));
18330
18331+ PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32;
18332+ PhysAddr |= (SK_U64) pRxd->VDataLow;
18333+
18334+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5)
18335+ pci_dma_sync_single(pAC->PciDev,
18336+ (dma_addr_t) PhysAddr,
18337+ FrameLength,
18338+ PCI_DMA_FROMDEVICE);
18339+#else
18340+ pci_dma_sync_single_for_cpu(pAC->PciDev,
18341+ (dma_addr_t) PhysAddr,
18342+ FrameLength,
18343+ PCI_DMA_FROMDEVICE);
18344+#endif
18345 ReQueueRxBuffer(pAC, pRxPort, pMsg,
18346 pRxd->VDataHigh, pRxd->VDataLow);
18347
18348@@ -2122,96 +3617,107 @@
18349 skb_put(pNewMsg, FrameLength);
18350 PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32;
18351 PhysAddr |= (SK_U64) pRxd->VDataLow;
18352-
18353- pci_dma_sync_single_for_cpu(pAC->PciDev,
18354- (dma_addr_t) PhysAddr,
18355- FrameLength,
18356- PCI_DMA_FROMDEVICE);
18357- memcpy(pNewMsg->data, pMsg, FrameLength);
18358-
18359+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5)
18360+ pci_dma_sync_single(pAC->PciDev,
18361+ (dma_addr_t) PhysAddr,
18362+ FrameLength,
18363+ PCI_DMA_FROMDEVICE);
18364+#else
18365 pci_dma_sync_single_for_device(pAC->PciDev,
18366- (dma_addr_t) PhysAddr,
18367- FrameLength,
18368- PCI_DMA_FROMDEVICE);
18369+ (dma_addr_t) PhysAddr,
18370+ FrameLength,
18371+ PCI_DMA_FROMDEVICE);
18372+#endif
18373+
18374+ eth_copy_and_sum(pNewMsg, pMsg->data,
18375+ FrameLength, 0);
18376 ReQueueRxBuffer(pAC, pRxPort, pMsg,
18377 pRxd->VDataHigh, pRxd->VDataLow);
18378
18379 pMsg = pNewMsg;
18380
18381- }
18382- else {
18383+ } else {
18384 /*
18385 * if large frame, or SKB allocation failed, pass
18386 * the SKB directly to the networking
18387 */
18388-
18389 PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32;
18390 PhysAddr |= (SK_U64) pRxd->VDataLow;
18391
18392 /* release the DMA mapping */
18393 pci_unmap_single(pAC->PciDev,
18394 PhysAddr,
18395- pAC->RxBufSize - 2,
18396+ pRxPort->RxBufSize - 2,
18397 PCI_DMA_FROMDEVICE);
18398+ skb_put(pMsg, FrameLength); /* set message len */
18399+ pMsg->ip_summed = CHECKSUM_NONE; /* initial default */
18400
18401- /* set length in message */
18402- skb_put(pMsg, FrameLength);
18403+ if (pRxPort->UseRxCsum) {
18404+ Type = ntohs(*((short*)&pMsg->data[12]));
18405+ if (Type == 0x800) {
18406+ IpFrameLength = (int) ntohs((unsigned short)
18407+ ((unsigned short *) pMsg->data)[8]);
18408+ if ((FrameLength - IpFrameLength) == 0xe) {
18409+ Csum1=le16_to_cpu(pRxd->TcpSums & 0xffff);
18410+ Csum2=le16_to_cpu((pRxd->TcpSums >> 16) & 0xffff);
18411+ if ((((Csum1 & 0xfffe) && (Csum2 & 0xfffe)) &&
18412+ (pAC->GIni.GIChipId == CHIP_ID_GENESIS)) ||
18413+ (pAC->ChipsetType)) {
18414+ Result = SkCsGetReceiveInfo(pAC, &pMsg->data[14],
18415+ Csum1, Csum2, PortIndex);
18416+ if ((Result == SKCS_STATUS_IP_FRAGMENT) ||
18417+ (Result == SKCS_STATUS_IP_CSUM_OK) ||
18418+ (Result == SKCS_STATUS_TCP_CSUM_OK) ||
18419+ (Result == SKCS_STATUS_UDP_CSUM_OK)) {
18420+ pMsg->ip_summed = CHECKSUM_UNNECESSARY;
18421+ } else if ((Result == SKCS_STATUS_TCP_CSUM_ERROR) ||
18422+ (Result == SKCS_STATUS_UDP_CSUM_ERROR) ||
18423+ (Result == SKCS_STATUS_IP_CSUM_ERROR_UDP) ||
18424+ (Result == SKCS_STATUS_IP_CSUM_ERROR_TCP) ||
18425+ (Result == SKCS_STATUS_IP_CSUM_ERROR)) {
18426+ /* HW Checksum error */
18427+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
18428+ SK_DBGCAT_DRV_RX_PROGRESS,
18429+ ("skge: CRC error. Frame dropped!\n"));
18430+ goto rx_failed;
18431+ } else {
18432+ pMsg->ip_summed = CHECKSUM_NONE;
18433+ }
18434+ }/* checksumControl calculation valid */
18435+ } /* Frame length check */
18436+ } /* IP frame */
18437+ } /* pRxPort->UseRxCsum */
18438 } /* frame > SK_COPY_TRESHOLD */
18439-
18440-#ifdef USE_SK_RX_CHECKSUM
18441- pMsg->csum = pRxd->TcpSums & 0xffff;
18442- pMsg->ip_summed = CHECKSUM_COMPLETE;
18443-#else
18444- pMsg->ip_summed = CHECKSUM_NONE;
18445-#endif
18446-
18447+
18448 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("V"));
18449- ForRlmt = SK_RLMT_RX_PROTOCOL;
18450-#if 0
18451- IsBc = (FrameStat & XMR_FS_BC)==XMR_FS_BC;
18452-#endif
18453+ RlmtNotifier = SK_RLMT_RX_PROTOCOL;
18454 SK_RLMT_PRE_LOOKAHEAD(pAC, PortIndex, FrameLength,
18455- IsBc, &Offset, &NumBytes);
18456+ IsBc, &Offset, &NumBytes);
18457 if (NumBytes != 0) {
18458-#if 0
18459- IsMc = (FrameStat & XMR_FS_MC)==XMR_FS_MC;
18460-#endif
18461- SK_RLMT_LOOKAHEAD(pAC, PortIndex,
18462- &pMsg->data[Offset],
18463- IsBc, IsMc, &ForRlmt);
18464+ SK_RLMT_LOOKAHEAD(pAC,PortIndex,&pMsg->data[Offset],
18465+ IsBc,IsMc,&RlmtNotifier);
18466 }
18467- if (ForRlmt == SK_RLMT_RX_PROTOCOL) {
18468- SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("W"));
18469+ if (RlmtNotifier == SK_RLMT_RX_PROTOCOL) {
18470+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("W"));
18471 /* send up only frames from active port */
18472- if ((PortIndex == pAC->ActivePort) ||
18473- (pAC->RlmtNets == 2)) {
18474- /* frame for upper layer */
18475+ if ((PortIndex == pAC->ActivePort)||(pAC->RlmtNets == 2)) {
18476 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("U"));
18477 #ifdef xDEBUG
18478 DumpMsg(pMsg, "Rx");
18479 #endif
18480- SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC,
18481- FrameLength, pRxPort->PortIndex);
18482-
18483- pMsg->dev = pAC->dev[pRxPort->PortIndex];
18484- pMsg->protocol = eth_type_trans(pMsg,
18485- pAC->dev[pRxPort->PortIndex]);
18486- netif_rx(pMsg);
18487- pAC->dev[pRxPort->PortIndex]->last_rx = jiffies;
18488- }
18489- else {
18490- /* drop frame */
18491+ SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC,FrameLength,PortIndex);
18492+ pMsg->dev = pAC->dev[PortIndex];
18493+ pMsg->protocol = eth_type_trans(pMsg,pAC->dev[PortIndex]);
18494+ netif_rx(pMsg); /* frame for upper layer */
18495+ pAC->dev[PortIndex]->last_rx = jiffies;
18496+ } else {
18497 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
18498- SK_DBGCAT_DRV_RX_PROGRESS,
18499- ("D"));
18500- DEV_KFREE_SKB(pMsg);
18501+ SK_DBGCAT_DRV_RX_PROGRESS,("D"));
18502+ DEV_KFREE_SKB(pMsg); /* drop frame */
18503 }
18504-
18505- } /* if not for rlmt */
18506- else {
18507- /* packet for rlmt */
18508+ } else { /* packet for RLMT stack */
18509 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
18510- SK_DBGCAT_DRV_RX_PROGRESS, ("R"));
18511+ SK_DBGCAT_DRV_RX_PROGRESS,("R"));
18512 pRlmtMbuf = SkDrvAllocRlmtMbuf(pAC,
18513 pAC->IoBase, FrameLength);
18514 if (pRlmtMbuf != NULL) {
18515@@ -2239,32 +3745,26 @@
18516 }
18517
18518 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
18519- SK_DBGCAT_DRV_RX_PROGRESS,
18520- ("Q"));
18521+ SK_DBGCAT_DRV_RX_PROGRESS,("Q"));
18522 }
18523- if ((pAC->dev[pRxPort->PortIndex]->flags &
18524- (IFF_PROMISC | IFF_ALLMULTI)) != 0 ||
18525- (ForRlmt & SK_RLMT_RX_PROTOCOL) ==
18526- SK_RLMT_RX_PROTOCOL) {
18527- pMsg->dev = pAC->dev[pRxPort->PortIndex];
18528- pMsg->protocol = eth_type_trans(pMsg,
18529- pAC->dev[pRxPort->PortIndex]);
18530+ if ((pAC->dev[PortIndex]->flags & (IFF_PROMISC | IFF_ALLMULTI)) ||
18531+ (RlmtNotifier & SK_RLMT_RX_PROTOCOL)) {
18532+ pMsg->dev = pAC->dev[PortIndex];
18533+ pMsg->protocol = eth_type_trans(pMsg,pAC->dev[PortIndex]);
18534+#ifdef CONFIG_SK98LIN_NAPI
18535+ netif_receive_skb(pMsg);
18536+#else
18537 netif_rx(pMsg);
18538- pAC->dev[pRxPort->PortIndex]->last_rx = jiffies;
18539- }
18540- else {
18541+#endif
18542+ pAC->dev[PortIndex]->last_rx = jiffies;
18543+ } else {
18544 DEV_KFREE_SKB(pMsg);
18545 }
18546-
18547- } /* if packet for rlmt */
18548+ } /* if packet for RLMT stack */
18549 } /* for ... scanning the RXD ring */
18550
18551 /* RXD ring is empty -> fill and restart */
18552 FillRxRing(pAC, pRxPort);
18553- /* do not start if called from Close */
18554- if (pAC->BoardLevel > SK_INIT_DATA) {
18555- ClearAndStartRx(pAC, PortIndex);
18556- }
18557 return;
18558
18559 rx_failed:
18560@@ -2278,7 +3778,7 @@
18561 PhysAddr |= (SK_U64) pRxd->VDataLow;
18562 pci_unmap_page(pAC->PciDev,
18563 PhysAddr,
18564- pAC->RxBufSize - 2,
18565+ pRxPort->RxBufSize - 2,
18566 PCI_DMA_FROMDEVICE);
18567 DEV_KFREE_SKB_IRQ(pRxd->pMBuf);
18568 pRxd->pMBuf = NULL;
18569@@ -2288,49 +3788,6 @@
18570
18571 } /* ReceiveIrq */
18572
18573-
18574-/*****************************************************************************
18575- *
18576- * ClearAndStartRx - give a start receive command to BMU, clear IRQ
18577- *
18578- * Description:
18579- * This function sends a start command and a clear interrupt
18580- * command for one receive queue to the BMU.
18581- *
18582- * Returns: N/A
18583- * none
18584- */
18585-static void ClearAndStartRx(
18586-SK_AC *pAC, /* pointer to the adapter context */
18587-int PortIndex) /* index of the receive port (XMAC) */
18588-{
18589- SK_OUT8(pAC->IoBase,
18590- RxQueueAddr[PortIndex]+Q_CSR,
18591- CSR_START | CSR_IRQ_CL_F);
18592-} /* ClearAndStartRx */
18593-
18594-
18595-/*****************************************************************************
18596- *
18597- * ClearTxIrq - give a clear transmit IRQ command to BMU
18598- *
18599- * Description:
18600- * This function sends a clear tx IRQ command for one
18601- * transmit queue to the BMU.
18602- *
18603- * Returns: N/A
18604- */
18605-static void ClearTxIrq(
18606-SK_AC *pAC, /* pointer to the adapter context */
18607-int PortIndex, /* index of the transmit port (XMAC) */
18608-int Prio) /* priority or normal queue */
18609-{
18610- SK_OUT8(pAC->IoBase,
18611- TxQueueAddr[PortIndex][Prio]+Q_CSR,
18612- CSR_IRQ_CL_F);
18613-} /* ClearTxIrq */
18614-
18615-
18616 /*****************************************************************************
18617 *
18618 * ClearRxRing - remove all buffers from the receive ring
18619@@ -2361,7 +3818,7 @@
18620 PhysAddr |= (SK_U64) pRxd->VDataLow;
18621 pci_unmap_page(pAC->PciDev,
18622 PhysAddr,
18623- pAC->RxBufSize - 2,
18624+ pRxPort->RxBufSize - 2,
18625 PCI_DMA_FROMDEVICE);
18626 DEV_KFREE_SKB(pRxd->pMBuf);
18627 pRxd->pMBuf = NULL;
18628@@ -2419,31 +3876,32 @@
18629 static int SkGeSetMacAddr(struct SK_NET_DEVICE *dev, void *p)
18630 {
18631
18632-DEV_NET *pNet = netdev_priv(dev);
18633+DEV_NET *pNet = (DEV_NET*) dev->priv;
18634 SK_AC *pAC = pNet->pAC;
18635+int Ret;
18636
18637 struct sockaddr *addr = p;
18638 unsigned long Flags;
18639
18640 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
18641 ("SkGeSetMacAddr starts now...\n"));
18642- if(netif_running(dev))
18643- return -EBUSY;
18644
18645 memcpy(dev->dev_addr, addr->sa_data,dev->addr_len);
18646
18647 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
18648
18649 if (pAC->RlmtNets == 2)
18650- SkAddrOverride(pAC, pAC->IoBase, pNet->NetNr,
18651+ Ret = SkAddrOverride(pAC, pAC->IoBase, pNet->NetNr,
18652 (SK_MAC_ADDR*)dev->dev_addr, SK_ADDR_VIRTUAL_ADDRESS);
18653 else
18654- SkAddrOverride(pAC, pAC->IoBase, pAC->ActivePort,
18655+ Ret = SkAddrOverride(pAC, pAC->IoBase, pAC->ActivePort,
18656 (SK_MAC_ADDR*)dev->dev_addr, SK_ADDR_VIRTUAL_ADDRESS);
18657-
18658-
18659
18660 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
18661+
18662+ if (Ret != SK_ADDR_OVERRIDE_SUCCESS)
18663+ return -EBUSY;
18664+
18665 return 0;
18666 } /* SkGeSetMacAddr */
18667
18668@@ -2476,7 +3934,7 @@
18669 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
18670 ("SkGeSetRxMode starts now... "));
18671
18672- pNet = netdev_priv(dev);
18673+ pNet = (DEV_NET*) dev->priv;
18674 pAC = pNet->pAC;
18675 if (pAC->RlmtNets == 1)
18676 PortIdx = pAC->ActivePort;
18677@@ -2525,6 +3983,45 @@
18678
18679 /*****************************************************************************
18680 *
18681+ * SkSetMtuBufferSize - set the MTU buffer to another value
18682+ *
18683+ * Description:
18684+ * This function sets the new buffers and is called whenever the MTU
18685+ * size is changed
18686+ *
18687+ * Returns:
18688+ * N/A
18689+ */
18690+
18691+static void SkSetMtuBufferSize(
18692+SK_AC *pAC, /* pointer to adapter context */
18693+int PortNr, /* Port number */
18694+int Mtu) /* pointer to tx prt struct */
18695+{
18696+ pAC->RxPort[PortNr].RxBufSize = Mtu + 32;
18697+
18698+ /* RxBufSize must be a multiple of 8 */
18699+ while (pAC->RxPort[PortNr].RxBufSize % 8) {
18700+ pAC->RxPort[PortNr].RxBufSize =
18701+ pAC->RxPort[PortNr].RxBufSize + 1;
18702+ }
18703+
18704+ if (Mtu > 1500) {
18705+ pAC->GIni.GP[PortNr].PPortUsage = SK_JUMBO_LINK;
18706+ } else {
18707+ if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
18708+ pAC->GIni.GP[PortNr].PPortUsage = SK_MUL_LINK;
18709+ } else {
18710+ pAC->GIni.GP[PortNr].PPortUsage = SK_RED_LINK;
18711+ }
18712+ }
18713+
18714+ return;
18715+}
18716+
18717+
18718+/*****************************************************************************
18719+ *
18720 * SkGeChangeMtu - set the MTU to another value
18721 *
18722 * Description:
18723@@ -2538,28 +4035,32 @@
18724 */
18725 static int SkGeChangeMtu(struct SK_NET_DEVICE *dev, int NewMtu)
18726 {
18727-DEV_NET *pNet;
18728-struct net_device *pOtherDev;
18729-SK_AC *pAC;
18730-unsigned long Flags;
18731-int i;
18732-SK_EVPARA EvPara;
18733+DEV_NET *pNet;
18734+SK_AC *pAC;
18735+unsigned long Flags;
18736+#ifdef CONFIG_SK98LIN_NAPI
18737+int WorkToDo = 1; // min(*budget, dev->quota);
18738+int WorkDone = 0;
18739+#endif
18740
18741 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
18742 ("SkGeChangeMtu starts now...\n"));
18743
18744- pNet = netdev_priv(dev);
18745+ pNet = (DEV_NET*) dev->priv;
18746 pAC = pNet->pAC;
18747
18748+ /* MTU size outside the spec */
18749 if ((NewMtu < 68) || (NewMtu > SK_JUMBO_MTU)) {
18750 return -EINVAL;
18751 }
18752
18753- if(pAC->BoardLevel != SK_INIT_RUN) {
18754+ /* MTU > 1500 on yukon FE not allowed */
18755+ if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_FE)
18756+ && (NewMtu > 1500)){
18757 return -EINVAL;
18758 }
18759
18760-#ifdef SK_DIAG_SUPPORT
18761+ /* Diag access active */
18762 if (pAC->DiagModeActive == DIAG_ACTIVE) {
18763 if (pAC->DiagFlowCtrl == SK_FALSE) {
18764 return -1; /* still in use, deny any actions of MTU */
18765@@ -2567,201 +4068,74 @@
18766 pAC->DiagFlowCtrl = SK_FALSE;
18767 }
18768 }
18769-#endif
18770-
18771- pOtherDev = pAC->dev[1 - pNet->NetNr];
18772-
18773- if ( netif_running(pOtherDev) && (pOtherDev->mtu > 1500)
18774- && (NewMtu <= 1500))
18775- return 0;
18776
18777- pAC->RxBufSize = NewMtu + 32;
18778 dev->mtu = NewMtu;
18779+ SkSetMtuBufferSize(pAC, pNet->PortNr, NewMtu);
18780
18781- SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
18782- ("New MTU: %d\n", NewMtu));
18783+ if(!netif_running(dev)) {
18784+ /* Preset MTU size if device not ready/running */
18785+ return 0;
18786+ }
18787
18788- /*
18789- ** Prevent any reconfiguration while changing the MTU
18790- ** by disabling any interrupts
18791- */
18792+ /* Prevent any reconfiguration while changing the MTU
18793+ by disabling any interrupts */
18794 SK_OUT32(pAC->IoBase, B0_IMSK, 0);
18795 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
18796
18797- /*
18798- ** Notify RLMT that any ports are to be stopped
18799- */
18800- EvPara.Para32[0] = 0;
18801- EvPara.Para32[1] = -1;
18802- if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
18803- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
18804- EvPara.Para32[0] = 1;
18805- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
18806- } else {
18807- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
18808- }
18809-
18810- /*
18811- ** After calling the SkEventDispatcher(), RLMT is aware about
18812- ** the stopped ports -> configuration can take place!
18813- */
18814- SkEventDispatcher(pAC, pAC->IoBase);
18815-
18816- for (i=0; i<pAC->GIni.GIMacsFound; i++) {
18817- spin_lock(&pAC->TxPort[i][TX_PRIO_LOW].TxDesRingLock);
18818- netif_stop_queue(pAC->dev[i]);
18819+ /* Notify RLMT that the port has to be stopped */
18820+ netif_stop_queue(dev);
18821+ SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP,
18822+ pNet->PortNr, -1, SK_TRUE);
18823+ spin_lock(&pAC->TxPort[pNet->PortNr][TX_PRIO_LOW].TxDesRingLock);
18824
18825- }
18826
18827- /*
18828- ** Depending on the desired MTU size change, a different number of
18829- ** RX buffers need to be allocated
18830- */
18831- if (NewMtu > 1500) {
18832- /*
18833- ** Use less rx buffers
18834- */
18835- for (i=0; i<pAC->GIni.GIMacsFound; i++) {
18836- if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
18837- pAC->RxPort[i].RxFillLimit = pAC->RxDescrPerRing -
18838- (pAC->RxDescrPerRing / 4);
18839- } else {
18840- if (i == pAC->ActivePort) {
18841- pAC->RxPort[i].RxFillLimit = pAC->RxDescrPerRing -
18842- (pAC->RxDescrPerRing / 4);
18843- } else {
18844- pAC->RxPort[i].RxFillLimit = pAC->RxDescrPerRing -
18845- (pAC->RxDescrPerRing / 10);
18846- }
18847- }
18848- }
18849+ /* Change RxFillLimit to 1 */
18850+ if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
18851+ pAC->RxPort[pNet->PortNr].RxFillLimit = 1;
18852 } else {
18853- /*
18854- ** Use the normal amount of rx buffers
18855- */
18856- for (i=0; i<pAC->GIni.GIMacsFound; i++) {
18857- if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
18858- pAC->RxPort[i].RxFillLimit = 1;
18859- } else {
18860- if (i == pAC->ActivePort) {
18861- pAC->RxPort[i].RxFillLimit = 1;
18862- } else {
18863- pAC->RxPort[i].RxFillLimit = pAC->RxDescrPerRing -
18864- (pAC->RxDescrPerRing / 4);
18865- }
18866- }
18867- }
18868+ pAC->RxPort[1 - pNet->PortNr].RxFillLimit = 1;
18869+ pAC->RxPort[pNet->PortNr].RxFillLimit = pAC->RxDescrPerRing -
18870+ (pAC->RxDescrPerRing / 4);
18871 }
18872-
18873- SkGeDeInit(pAC, pAC->IoBase);
18874
18875- /*
18876- ** enable/disable hardware support for long frames
18877- */
18878- if (NewMtu > 1500) {
18879-// pAC->JumboActivated = SK_TRUE; /* is never set back !!! */
18880- pAC->GIni.GIPortUsage = SK_JUMBO_LINK;
18881+ /* clear and reinit the rx rings here, because of new MTU size */
18882+ if (CHIP_ID_YUKON_2(pAC)) {
18883+ SkY2PortStop(pAC, pAC->IoBase, pNet->PortNr, SK_STOP_ALL, SK_SOFT_RST);
18884+ SkY2AllocateRxBuffers(pAC, pAC->IoBase, pNet->PortNr);
18885+ SkY2PortStart(pAC, pAC->IoBase, pNet->PortNr);
18886 } else {
18887- if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
18888- pAC->GIni.GIPortUsage = SK_MUL_LINK;
18889- } else {
18890- pAC->GIni.GIPortUsage = SK_RED_LINK;
18891- }
18892- }
18893+// SkGeStopPort(pAC, pAC->IoBase, pNet->PortNr, SK_STOP_ALL, SK_SOFT_RST);
18894+#ifdef CONFIG_SK98LIN_NAPI
18895+ WorkToDo = 1;
18896+ ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE, &WorkDone, WorkToDo);
18897+#else
18898+ ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE);
18899+#endif
18900+ ClearRxRing(pAC, &pAC->RxPort[pNet->PortNr]);
18901+ FillRxRing(pAC, &pAC->RxPort[pNet->PortNr]);
18902
18903- SkGeInit( pAC, pAC->IoBase, SK_INIT_IO);
18904- SkI2cInit( pAC, pAC->IoBase, SK_INIT_IO);
18905- SkEventInit(pAC, pAC->IoBase, SK_INIT_IO);
18906- SkPnmiInit( pAC, pAC->IoBase, SK_INIT_IO);
18907- SkAddrInit( pAC, pAC->IoBase, SK_INIT_IO);
18908- SkRlmtInit( pAC, pAC->IoBase, SK_INIT_IO);
18909- SkTimerInit(pAC, pAC->IoBase, SK_INIT_IO);
18910-
18911- /*
18912- ** tschilling:
18913- ** Speed and others are set back to default in level 1 init!
18914- */
18915- GetConfiguration(pAC);
18916-
18917- SkGeInit( pAC, pAC->IoBase, SK_INIT_RUN);
18918- SkI2cInit( pAC, pAC->IoBase, SK_INIT_RUN);
18919- SkEventInit(pAC, pAC->IoBase, SK_INIT_RUN);
18920- SkPnmiInit( pAC, pAC->IoBase, SK_INIT_RUN);
18921- SkAddrInit( pAC, pAC->IoBase, SK_INIT_RUN);
18922- SkRlmtInit( pAC, pAC->IoBase, SK_INIT_RUN);
18923- SkTimerInit(pAC, pAC->IoBase, SK_INIT_RUN);
18924+ /* Enable transmit descriptor polling */
18925+ SkGePollTxD(pAC, pAC->IoBase, pNet->PortNr, SK_TRUE);
18926+ FillRxRing(pAC, &pAC->RxPort[pNet->PortNr]);
18927+ }
18928
18929- /*
18930- ** clear and reinit the rx rings here
18931- */
18932- for (i=0; i<pAC->GIni.GIMacsFound; i++) {
18933- ReceiveIrq(pAC, &pAC->RxPort[i], SK_TRUE);
18934- ClearRxRing(pAC, &pAC->RxPort[i]);
18935- FillRxRing(pAC, &pAC->RxPort[i]);
18936+ netif_start_queue(pAC->dev[pNet->PortNr]);
18937
18938- /*
18939- ** Enable transmit descriptor polling
18940- */
18941- SkGePollTxD(pAC, pAC->IoBase, i, SK_TRUE);
18942- FillRxRing(pAC, &pAC->RxPort[i]);
18943- };
18944+ spin_unlock(&pAC->TxPort[pNet->PortNr][TX_PRIO_LOW].TxDesRingLock);
18945
18946- SkGeYellowLED(pAC, pAC->IoBase, 1);
18947- SkDimEnableModerationIfNeeded(pAC);
18948- SkDimDisplayModerationSettings(pAC);
18949
18950- netif_start_queue(pAC->dev[pNet->PortNr]);
18951- for (i=pAC->GIni.GIMacsFound-1; i>=0; i--) {
18952- spin_unlock(&pAC->TxPort[i][TX_PRIO_LOW].TxDesRingLock);
18953- }
18954+ /* Notify RLMT about the changing and restarting one (or more) ports */
18955+ SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_START,
18956+ pNet->PortNr, -1, SK_TRUE);
18957
18958- /*
18959- ** Enable Interrupts again
18960- */
18961+ /* Enable Interrupts again */
18962 SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
18963 SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK);
18964
18965- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara);
18966- SkEventDispatcher(pAC, pAC->IoBase);
18967-
18968- /*
18969- ** Notify RLMT about the changing and restarting one (or more) ports
18970- */
18971- if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
18972- EvPara.Para32[0] = pAC->RlmtNets;
18973- EvPara.Para32[1] = -1;
18974- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_SET_NETS, EvPara);
18975- EvPara.Para32[0] = pNet->PortNr;
18976- EvPara.Para32[1] = -1;
18977- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara);
18978-
18979- if (netif_running(pOtherDev)) {
18980- DEV_NET *pOtherNet = netdev_priv(pOtherDev);
18981- EvPara.Para32[0] = pOtherNet->PortNr;
18982- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara);
18983- }
18984- } else {
18985- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara);
18986- }
18987-
18988- SkEventDispatcher(pAC, pAC->IoBase);
18989 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
18990-
18991- /*
18992- ** While testing this driver with latest kernel 2.5 (2.5.70), it
18993- ** seems as if upper layers have a problem to handle a successful
18994- ** return value of '0'. If such a zero is returned, the complete
18995- ** system hangs for several minutes (!), which is in acceptable.
18996- **
18997- ** Currently it is not clear, what the exact reason for this problem
18998- ** is. The implemented workaround for 2.5 is to return the desired
18999- ** new MTU size if all needed changes for the new MTU size where
19000- ** performed. In kernels 2.2 and 2.4, a zero value is returned,
19001- ** which indicates the successful change of the mtu-size.
19002- */
19003- return NewMtu;
19004+ return 0;
19005
19006-} /* SkGeChangeMtu */
19007+}
19008
19009
19010 /*****************************************************************************
19011@@ -2777,125 +4151,67 @@
19012 */
19013 static struct net_device_stats *SkGeStats(struct SK_NET_DEVICE *dev)
19014 {
19015-DEV_NET *pNet = netdev_priv(dev);
19016-SK_AC *pAC = pNet->pAC;
19017-SK_PNMI_STRUCT_DATA *pPnmiStruct; /* structure for all Pnmi-Data */
19018-SK_PNMI_STAT *pPnmiStat; /* pointer to virtual XMAC stat. data */
19019-SK_PNMI_CONF *pPnmiConf; /* pointer to virtual link config. */
19020-unsigned int Size; /* size of pnmi struct */
19021-unsigned long Flags; /* for spin lock */
19022-
19023- SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
19024- ("SkGeStats starts now...\n"));
19025- pPnmiStruct = &pAC->PnmiStruct;
19026+ DEV_NET *pNet = (DEV_NET*) dev->priv;
19027+ SK_AC *pAC = pNet->pAC;
19028+ unsigned long LateCollisions, ExcessiveCollisions, RxTooLong;
19029+ unsigned long Flags; /* for spin lock */
19030+ SK_U32 MaxNumOidEntries, Oid, Len;
19031+ char Buf[8];
19032+ struct {
19033+ SK_U32 Oid;
19034+ unsigned long *pVar;
19035+ } Vars[] = {
19036+ { OID_SKGE_STAT_TX_LATE_COL, &LateCollisions },
19037+ { OID_SKGE_STAT_TX_EXCESS_COL, &ExcessiveCollisions },
19038+ { OID_SKGE_STAT_RX_TOO_LONG, &RxTooLong },
19039+ { OID_SKGE_STAT_RX, &pAC->stats.rx_packets },
19040+ { OID_SKGE_STAT_TX, &pAC->stats.tx_packets },
19041+ { OID_SKGE_STAT_RX_OCTETS, &pAC->stats.rx_bytes },
19042+ { OID_SKGE_STAT_TX_OCTETS, &pAC->stats.tx_bytes },
19043+ { OID_SKGE_RX_NO_BUF_CTS, &pAC->stats.rx_dropped },
19044+ { OID_SKGE_TX_NO_BUF_CTS, &pAC->stats.tx_dropped },
19045+ { OID_SKGE_STAT_RX_MULTICAST, &pAC->stats.multicast },
19046+ { OID_SKGE_STAT_RX_RUNT, &pAC->stats.rx_length_errors },
19047+ { OID_SKGE_STAT_RX_FCS, &pAC->stats.rx_crc_errors },
19048+ { OID_SKGE_STAT_RX_FRAMING, &pAC->stats.rx_frame_errors },
19049+ { OID_SKGE_STAT_RX_OVERFLOW, &pAC->stats.rx_over_errors },
19050+ { OID_SKGE_STAT_RX_MISSED, &pAC->stats.rx_missed_errors },
19051+ { OID_SKGE_STAT_TX_CARRIER, &pAC->stats.tx_carrier_errors },
19052+ { OID_SKGE_STAT_TX_UNDERRUN, &pAC->stats.tx_fifo_errors },
19053+ };
19054+
19055+ if ((pAC->DiagModeActive == DIAG_NOTACTIVE) &&
19056+ (pAC->BoardLevel == SK_INIT_RUN)) {
19057+ memset(&pAC->stats, 0x00, sizeof(pAC->stats)); /* clean first */
19058+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
19059
19060-#ifdef SK_DIAG_SUPPORT
19061- if ((pAC->DiagModeActive == DIAG_NOTACTIVE) &&
19062- (pAC->BoardLevel == SK_INIT_RUN)) {
19063-#endif
19064- SK_MEMSET(pPnmiStruct, 0, sizeof(SK_PNMI_STRUCT_DATA));
19065- spin_lock_irqsave(&pAC->SlowPathLock, Flags);
19066- Size = SK_PNMI_STRUCT_SIZE;
19067- SkPnmiGetStruct(pAC, pAC->IoBase, pPnmiStruct, &Size, pNet->NetNr);
19068- spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
19069-#ifdef SK_DIAG_SUPPORT
19070- }
19071-#endif
19072+ MaxNumOidEntries = sizeof(Vars) / sizeof(Vars[0]);
19073+ for (Oid = 0; Oid < MaxNumOidEntries; Oid++) {
19074+ if (SkPnmiGetVar(pAC,pAC->IoBase, Vars[Oid].Oid,
19075+ &Buf, &Len, 1, pNet->NetNr) != SK_PNMI_ERR_OK) {
19076+ memset(Buf, 0x00, sizeof(Buf));
19077+ }
19078+ *Vars[Oid].pVar = (unsigned long) (*((SK_U64 *) Buf));
19079+ }
19080+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
19081
19082- pPnmiStat = &pPnmiStruct->Stat[0];
19083- pPnmiConf = &pPnmiStruct->Conf[0];
19084+ pAC->stats.collisions = LateCollisions + ExcessiveCollisions;
19085+ pAC->stats.tx_errors = pAC->stats.tx_carrier_errors +
19086+ pAC->stats.tx_fifo_errors;
19087+ pAC->stats.rx_errors = pAC->stats.rx_length_errors +
19088+ pAC->stats.rx_crc_errors +
19089+ pAC->stats.rx_frame_errors +
19090+ pAC->stats.rx_over_errors +
19091+ pAC->stats.rx_missed_errors;
19092
19093- pAC->stats.rx_packets = (SK_U32) pPnmiStruct->RxDeliveredCts & 0xFFFFFFFF;
19094- pAC->stats.tx_packets = (SK_U32) pPnmiStat->StatTxOkCts & 0xFFFFFFFF;
19095- pAC->stats.rx_bytes = (SK_U32) pPnmiStruct->RxOctetsDeliveredCts;
19096- pAC->stats.tx_bytes = (SK_U32) pPnmiStat->StatTxOctetsOkCts;
19097-
19098- if (dev->mtu <= 1500) {
19099- pAC->stats.rx_errors = (SK_U32) pPnmiStruct->InErrorsCts & 0xFFFFFFFF;
19100- } else {
19101- pAC->stats.rx_errors = (SK_U32) ((pPnmiStruct->InErrorsCts -
19102- pPnmiStat->StatRxTooLongCts) & 0xFFFFFFFF);
19103+ if (dev->mtu > 1500) {
19104+ pAC->stats.rx_errors = pAC->stats.rx_errors - RxTooLong;
19105+ }
19106 }
19107
19108-
19109- if (pAC->GIni.GP[0].PhyType == SK_PHY_XMAC && pAC->HWRevision < 12)
19110- pAC->stats.rx_errors = pAC->stats.rx_errors - pPnmiStat->StatRxShortsCts;
19111-
19112- pAC->stats.tx_errors = (SK_U32) pPnmiStat->StatTxSingleCollisionCts & 0xFFFFFFFF;
19113- pAC->stats.rx_dropped = (SK_U32) pPnmiStruct->RxNoBufCts & 0xFFFFFFFF;
19114- pAC->stats.tx_dropped = (SK_U32) pPnmiStruct->TxNoBufCts & 0xFFFFFFFF;
19115- pAC->stats.multicast = (SK_U32) pPnmiStat->StatRxMulticastOkCts & 0xFFFFFFFF;
19116- pAC->stats.collisions = (SK_U32) pPnmiStat->StatTxSingleCollisionCts & 0xFFFFFFFF;
19117-
19118- /* detailed rx_errors: */
19119- pAC->stats.rx_length_errors = (SK_U32) pPnmiStat->StatRxRuntCts & 0xFFFFFFFF;
19120- pAC->stats.rx_over_errors = (SK_U32) pPnmiStat->StatRxFifoOverflowCts & 0xFFFFFFFF;
19121- pAC->stats.rx_crc_errors = (SK_U32) pPnmiStat->StatRxFcsCts & 0xFFFFFFFF;
19122- pAC->stats.rx_frame_errors = (SK_U32) pPnmiStat->StatRxFramingCts & 0xFFFFFFFF;
19123- pAC->stats.rx_fifo_errors = (SK_U32) pPnmiStat->StatRxFifoOverflowCts & 0xFFFFFFFF;
19124- pAC->stats.rx_missed_errors = (SK_U32) pPnmiStat->StatRxMissedCts & 0xFFFFFFFF;
19125-
19126- /* detailed tx_errors */
19127- pAC->stats.tx_aborted_errors = (SK_U32) 0;
19128- pAC->stats.tx_carrier_errors = (SK_U32) pPnmiStat->StatTxCarrierCts & 0xFFFFFFFF;
19129- pAC->stats.tx_fifo_errors = (SK_U32) pPnmiStat->StatTxFifoUnderrunCts & 0xFFFFFFFF;
19130- pAC->stats.tx_heartbeat_errors = (SK_U32) pPnmiStat->StatTxCarrierCts & 0xFFFFFFFF;
19131- pAC->stats.tx_window_errors = (SK_U32) 0;
19132-
19133 return(&pAC->stats);
19134 } /* SkGeStats */
19135
19136-/*
19137- * Basic MII register access
19138- */
19139-static int SkGeMiiIoctl(struct net_device *dev,
19140- struct mii_ioctl_data *data, int cmd)
19141-{
19142- DEV_NET *pNet = netdev_priv(dev);
19143- SK_AC *pAC = pNet->pAC;
19144- SK_IOC IoC = pAC->IoBase;
19145- int Port = pNet->PortNr;
19146- SK_GEPORT *pPrt = &pAC->GIni.GP[Port];
19147- unsigned long Flags;
19148- int err = 0;
19149- int reg = data->reg_num & 0x1f;
19150- SK_U16 val = data->val_in;
19151-
19152- if (!netif_running(dev))
19153- return -ENODEV; /* Phy still in reset */
19154-
19155- spin_lock_irqsave(&pAC->SlowPathLock, Flags);
19156- switch(cmd) {
19157- case SIOCGMIIPHY:
19158- data->phy_id = pPrt->PhyAddr;
19159-
19160- /* fallthru */
19161- case SIOCGMIIREG:
19162- if (pAC->GIni.GIGenesis)
19163- SkXmPhyRead(pAC, IoC, Port, reg, &val);
19164- else
19165- SkGmPhyRead(pAC, IoC, Port, reg, &val);
19166-
19167- data->val_out = val;
19168- break;
19169-
19170- case SIOCSMIIREG:
19171- if (!capable(CAP_NET_ADMIN))
19172- err = -EPERM;
19173-
19174- else if (pAC->GIni.GIGenesis)
19175- SkXmPhyWrite(pAC, IoC, Port, reg, val);
19176- else
19177- SkGmPhyWrite(pAC, IoC, Port, reg, val);
19178- break;
19179- default:
19180- err = -EOPNOTSUPP;
19181- }
19182- spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
19183- return err;
19184-}
19185-
19186-
19187 /*****************************************************************************
19188 *
19189 * SkGeIoctl - IO-control function
19190@@ -2903,41 +4219,43 @@
19191 * Description:
19192 * This function is called if an ioctl is issued on the device.
19193 * There are three subfunction for reading, writing and test-writing
19194- * the private MIB data structure (useful for SysKonnect-internal tools).
19195+ * the private MIB data structure (usefull for SysKonnect-internal tools).
19196 *
19197 * Returns:
19198 * 0, if everything is ok
19199 * !=0, on error
19200 */
19201-static int SkGeIoctl(struct SK_NET_DEVICE *dev, struct ifreq *rq, int cmd)
19202-{
19203-DEV_NET *pNet;
19204-SK_AC *pAC;
19205-void *pMemBuf;
19206-struct pci_dev *pdev = NULL;
19207-SK_GE_IOCTL Ioctl;
19208-unsigned int Err = 0;
19209-int Size = 0;
19210-int Ret = 0;
19211-unsigned int Length = 0;
19212-int HeaderLength = sizeof(SK_U32) + sizeof(SK_U32);
19213+static int SkGeIoctl(
19214+struct SK_NET_DEVICE *dev, /* the device the IOCTL is to be performed on */
19215+struct ifreq *rq, /* additional request structure containing data */
19216+int cmd) /* requested IOCTL command number */
19217+{
19218+ DEV_NET *pNet = (DEV_NET*) dev->priv;
19219+ SK_AC *pAC = pNet->pAC;
19220+ struct pci_dev *pdev = NULL;
19221+ void *pMemBuf;
19222+ SK_GE_IOCTL Ioctl;
19223+ unsigned long Flags; /* for spin lock */
19224+ unsigned int Err = 0;
19225+ unsigned int Length = 0;
19226+ int HeaderLength = sizeof(SK_U32) + sizeof(SK_U32);
19227+ int Size = 0;
19228+ int Ret = 0;
19229
19230 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
19231 ("SkGeIoctl starts now...\n"));
19232
19233- pNet = netdev_priv(dev);
19234- pAC = pNet->pAC;
19235-
19236- if (cmd == SIOCGMIIPHY || cmd == SIOCSMIIREG || cmd == SIOCGMIIREG)
19237- return SkGeMiiIoctl(dev, if_mii(rq), cmd);
19238-
19239 if(copy_from_user(&Ioctl, rq->ifr_data, sizeof(SK_GE_IOCTL))) {
19240 return -EFAULT;
19241 }
19242
19243 switch(cmd) {
19244- case SK_IOCTL_SETMIB:
19245- case SK_IOCTL_PRESETMIB:
19246+#ifndef ENABLE_FUTURE_ETH
19247+ case SIOCETHTOOL:
19248+ return SkEthIoctl(dev, rq );
19249+#endif
19250+ case SK_IOCTL_SETMIB: /* FALL THRU */
19251+ case SK_IOCTL_PRESETMIB: /* FALL THRU (if capable!) */
19252 if (!capable(CAP_NET_ADMIN)) return -EPERM;
19253 case SK_IOCTL_GETMIB:
19254 if(copy_from_user(&pAC->PnmiStruct, Ioctl.pData,
19255@@ -2964,6 +4282,7 @@
19256 if (NULL == (pMemBuf = kmalloc(Length, GFP_KERNEL))) {
19257 return -ENOMEM;
19258 }
19259+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
19260 if(copy_from_user(pMemBuf, Ioctl.pData, Length)) {
19261 Err = -EFAULT;
19262 goto fault_gen;
19263@@ -2982,10 +4301,10 @@
19264 goto fault_gen;
19265 }
19266 fault_gen:
19267+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
19268 kfree(pMemBuf); /* cleanup everything */
19269 break;
19270-#ifdef SK_DIAG_SUPPORT
19271- case SK_IOCTL_DIAG:
19272+ case SK_IOCTL_DIAG:
19273 if (!capable(CAP_NET_ADMIN)) return -EPERM;
19274 if (Ioctl.Len < (sizeof(pAC->PnmiStruct) + HeaderLength)) {
19275 Length = Ioctl.Len;
19276@@ -3022,7 +4341,6 @@
19277 fault_diag:
19278 kfree(pMemBuf); /* cleanup everything */
19279 break;
19280-#endif
19281 default:
19282 Err = -EOPNOTSUPP;
19283 }
19284@@ -3054,12 +4372,12 @@
19285 unsigned int Size, /* length of ioctl data */
19286 int mode) /* flag for set/preset */
19287 {
19288-unsigned long Flags; /* for spin lock */
19289-SK_AC *pAC;
19290+ SK_AC *pAC = pNet->pAC;
19291+ unsigned long Flags; /* for spin lock */
19292
19293 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
19294 ("SkGeIocMib starts now...\n"));
19295- pAC = pNet->pAC;
19296+
19297 /* access MIB */
19298 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
19299 switch(mode) {
19300@@ -3102,17 +4420,18 @@
19301 SK_I32 Port; /* preferred port */
19302 SK_BOOL AutoSet;
19303 SK_BOOL DupSet;
19304-int LinkSpeed = SK_LSPEED_AUTO; /* Link speed */
19305-int AutoNeg = 1; /* autoneg off (0) or on (1) */
19306-int DuplexCap = 0; /* 0=both,1=full,2=half */
19307-int FlowCtrl = SK_FLOW_MODE_SYM_OR_REM; /* FlowControl */
19308-int MSMode = SK_MS_MODE_AUTO; /* master/slave mode */
19309-
19310-SK_BOOL IsConTypeDefined = SK_TRUE;
19311-SK_BOOL IsLinkSpeedDefined = SK_TRUE;
19312-SK_BOOL IsFlowCtrlDefined = SK_TRUE;
19313-SK_BOOL IsRoleDefined = SK_TRUE;
19314-SK_BOOL IsModeDefined = SK_TRUE;
19315+int LinkSpeed = SK_LSPEED_AUTO; /* Link speed */
19316+int AutoNeg = 1; /* autoneg off (0) or on (1) */
19317+int DuplexCap = 0; /* 0=both,1=full,2=half */
19318+int FlowCtrl = SK_FLOW_MODE_SYM_OR_REM; /* FlowControl */
19319+int MSMode = SK_MS_MODE_AUTO; /* master/slave mode */
19320+int IrqModMaskOffset = 6; /* all ints moderated=default */
19321+
19322+SK_BOOL IsConTypeDefined = SK_TRUE;
19323+SK_BOOL IsLinkSpeedDefined = SK_TRUE;
19324+SK_BOOL IsFlowCtrlDefined = SK_TRUE;
19325+SK_BOOL IsRoleDefined = SK_TRUE;
19326+SK_BOOL IsModeDefined = SK_TRUE;
19327 /*
19328 * The two parameters AutoNeg. and DuplexCap. map to one configuration
19329 * parameter. The mapping is described by this table:
19330@@ -3130,6 +4449,15 @@
19331 {SK_LMODE_AUTOBOTH , SK_LMODE_AUTOFULL , SK_LMODE_AUTOHALF },
19332 {SK_LMODE_AUTOSENSE, SK_LMODE_AUTOSENSE, SK_LMODE_AUTOSENSE} };
19333
19334+SK_U32 IrqModMask[7][2] =
19335+ { { IRQ_MASK_RX_ONLY , Y2_DRIVER_IRQS },
19336+ { IRQ_MASK_TX_ONLY , Y2_DRIVER_IRQS },
19337+ { IRQ_MASK_SP_ONLY , Y2_SPECIAL_IRQS },
19338+ { IRQ_MASK_SP_RX , Y2_IRQ_MASK },
19339+ { IRQ_MASK_TX_RX , Y2_DRIVER_IRQS },
19340+ { IRQ_MASK_SP_TX , Y2_IRQ_MASK },
19341+ { IRQ_MASK_RX_TX_SP, Y2_IRQ_MASK } };
19342+
19343 #define DC_BOTH 0
19344 #define DC_FULL 1
19345 #define DC_HALF 2
19346@@ -3162,6 +4490,7 @@
19347 ** ConType DupCap AutoNeg FlowCtrl Role Speed
19348 ** ------- ------ ------- -------- ---------- -----
19349 ** Auto Both On SymOrRem Auto Auto
19350+ ** 1000FD Full Off None <ignored> 1000
19351 ** 100FD Full Off None <ignored> 100
19352 ** 100HD Half Off None <ignored> 100
19353 ** 10FD Full Off None <ignored> 10
19354@@ -3169,66 +4498,86 @@
19355 **
19356 ** This ConType parameter is used for all ports of the adapter!
19357 */
19358- if ( (ConType != NULL) &&
19359+ if ( (ConType != NULL) &&
19360 (pAC->Index < SK_MAX_CARD_PARAM) &&
19361 (ConType[pAC->Index] != NULL) ) {
19362
19363- /* Check chipset family */
19364- if ((!pAC->ChipsetType) &&
19365- (strcmp(ConType[pAC->Index],"Auto")!=0) &&
19366- (strcmp(ConType[pAC->Index],"")!=0)) {
19367- /* Set the speed parameter back */
19368- printk("sk98lin: Illegal value \"%s\" "
19369- "for ConType."
19370- " Using Auto.\n",
19371- ConType[pAC->Index]);
19372-
19373- sprintf(ConType[pAC->Index], "Auto");
19374- }
19375+ /* Check chipset family */
19376+ if ((!pAC->ChipsetType) &&
19377+ (strcmp(ConType[pAC->Index],"Auto")!=0) &&
19378+ (strcmp(ConType[pAC->Index],"")!=0)) {
19379+ /* Set the speed parameter back */
19380+ printk("sk98lin: Illegal value \"%s\" "
19381+ "for ConType."
19382+ " Using Auto.\n",
19383+ ConType[pAC->Index]);
19384+
19385+ ConType[pAC->Index] = "Auto";
19386+ }
19387+
19388+ if ((pAC->ChipsetType) &&
19389+ (pAC->GIni.GICopperType != SK_TRUE) &&
19390+ (strcmp(ConType[pAC->Index],"") != 0) &&
19391+ (strcmp(ConType[pAC->Index],"1000FD") != 0)) {
19392+ /* Set the speed parameter back */
19393+ printk("sk98lin: Illegal value \"%s\" "
19394+ "for ConType."
19395+ " Using Auto.\n",
19396+ ConType[pAC->Index]);
19397+ IsConTypeDefined = SK_FALSE;
19398+ ConType[pAC->Index] = "Auto";
19399+ }
19400
19401- if (strcmp(ConType[pAC->Index],"")==0) {
19402+ if (strcmp(ConType[pAC->Index],"")==0) {
19403 IsConTypeDefined = SK_FALSE; /* No ConType defined */
19404- } else if (strcmp(ConType[pAC->Index],"Auto")==0) {
19405+ } else if (strcmp(ConType[pAC->Index],"Auto")==0) {
19406 for (Port = 0; Port < SK_MAX_MACS; Port++) {
19407 M_CurrPort.PLinkModeConf = Capabilities[AN_ON][DC_BOTH];
19408 M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_SYM_OR_REM;
19409 M_CurrPort.PMSMode = SK_MS_MODE_AUTO;
19410 M_CurrPort.PLinkSpeed = SK_LSPEED_AUTO;
19411 }
19412- } else if (strcmp(ConType[pAC->Index],"100FD")==0) {
19413+ } else if (strcmp(ConType[pAC->Index],"1000FD")==0) {
19414+ for (Port = 0; Port < SK_MAX_MACS; Port++) {
19415+ M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_FULL];
19416+ M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE;
19417+ M_CurrPort.PMSMode = SK_MS_MODE_AUTO;
19418+ M_CurrPort.PLinkSpeed = SK_LSPEED_1000MBPS;
19419+ }
19420+ } else if (strcmp(ConType[pAC->Index],"100FD")==0) {
19421 for (Port = 0; Port < SK_MAX_MACS; Port++) {
19422 M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_FULL];
19423 M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE;
19424 M_CurrPort.PMSMode = SK_MS_MODE_AUTO;
19425 M_CurrPort.PLinkSpeed = SK_LSPEED_100MBPS;
19426 }
19427- } else if (strcmp(ConType[pAC->Index],"100HD")==0) {
19428+ } else if (strcmp(ConType[pAC->Index],"100HD")==0) {
19429 for (Port = 0; Port < SK_MAX_MACS; Port++) {
19430 M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_HALF];
19431 M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE;
19432 M_CurrPort.PMSMode = SK_MS_MODE_AUTO;
19433 M_CurrPort.PLinkSpeed = SK_LSPEED_100MBPS;
19434 }
19435- } else if (strcmp(ConType[pAC->Index],"10FD")==0) {
19436+ } else if (strcmp(ConType[pAC->Index],"10FD")==0) {
19437 for (Port = 0; Port < SK_MAX_MACS; Port++) {
19438 M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_FULL];
19439 M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE;
19440 M_CurrPort.PMSMode = SK_MS_MODE_AUTO;
19441 M_CurrPort.PLinkSpeed = SK_LSPEED_10MBPS;
19442 }
19443- } else if (strcmp(ConType[pAC->Index],"10HD")==0) {
19444+ } else if (strcmp(ConType[pAC->Index],"10HD")==0) {
19445 for (Port = 0; Port < SK_MAX_MACS; Port++) {
19446 M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_HALF];
19447 M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE;
19448 M_CurrPort.PMSMode = SK_MS_MODE_AUTO;
19449 M_CurrPort.PLinkSpeed = SK_LSPEED_10MBPS;
19450 }
19451- } else {
19452+ } else {
19453 printk("sk98lin: Illegal value \"%s\" for ConType\n",
19454 ConType[pAC->Index]);
19455 IsConTypeDefined = SK_FALSE; /* Wrong ConType defined */
19456 }
19457- } else {
19458+ } else {
19459 IsConTypeDefined = SK_FALSE; /* No ConType defined */
19460 }
19461
19462@@ -3247,14 +4596,30 @@
19463 } else if (strcmp(Speed_A[pAC->Index],"100")==0) {
19464 LinkSpeed = SK_LSPEED_100MBPS;
19465 } else if (strcmp(Speed_A[pAC->Index],"1000")==0) {
19466- LinkSpeed = SK_LSPEED_1000MBPS;
19467+ if ((pAC->PciDev->vendor == 0x11ab ) &&
19468+ (pAC->PciDev->device == 0x4350)) {
19469+ LinkSpeed = SK_LSPEED_100MBPS;
19470+ printk("sk98lin: Illegal value \"%s\" for Speed_A.\n"
19471+ "Gigabit speed not possible with this chip revision!",
19472+ Speed_A[pAC->Index]);
19473+ } else {
19474+ LinkSpeed = SK_LSPEED_1000MBPS;
19475+ }
19476 } else {
19477 printk("sk98lin: Illegal value \"%s\" for Speed_A\n",
19478 Speed_A[pAC->Index]);
19479 IsLinkSpeedDefined = SK_FALSE;
19480 }
19481 } else {
19482- IsLinkSpeedDefined = SK_FALSE;
19483+ if ((pAC->PciDev->vendor == 0x11ab ) &&
19484+ (pAC->PciDev->device == 0x4350)) {
19485+ /* Gigabit speed not supported
19486+ * Swith to speed 100
19487+ */
19488+ LinkSpeed = SK_LSPEED_100MBPS;
19489+ } else {
19490+ IsLinkSpeedDefined = SK_FALSE;
19491+ }
19492 }
19493
19494 /*
19495@@ -3349,9 +4714,6 @@
19496 }
19497
19498 if (!AutoSet && DupSet) {
19499- printk("sk98lin: Port A: Duplex setting not"
19500- " possible in\n default AutoNegotiation mode"
19501- " (Sense).\n Using AutoNegotiation On\n");
19502 AutoNeg = AN_ON;
19503 }
19504
19505@@ -3379,7 +4741,7 @@
19506 FlowCtrl = SK_FLOW_MODE_NONE;
19507 } else {
19508 printk("sk98lin: Illegal value \"%s\" for FlowCtrl_A\n",
19509- FlowCtrl_A[pAC->Index]);
19510+ FlowCtrl_A[pAC->Index]);
19511 IsFlowCtrlDefined = SK_FALSE;
19512 }
19513 } else {
19514@@ -3471,7 +4833,7 @@
19515 ** Decide whether to set new config value if somethig valid has
19516 ** been received.
19517 */
19518- if (IsLinkSpeedDefined) {
19519+ if (IsLinkSpeedDefined) {
19520 pAC->GIni.GP[1].PLinkSpeed = LinkSpeed;
19521 }
19522
19523@@ -3547,9 +4909,6 @@
19524 }
19525
19526 if (!AutoSet && DupSet) {
19527- printk("sk98lin: Port B: Duplex setting not"
19528- " possible in\n default AutoNegotiation mode"
19529- " (Sense).\n Using AutoNegotiation On\n");
19530 AutoNeg = AN_ON;
19531 }
19532
19533@@ -3662,11 +5021,15 @@
19534 }
19535
19536 pAC->RlmtNets = 1;
19537+ pAC->RlmtMode = 0;
19538
19539 if (RlmtMode != NULL && pAC->Index<SK_MAX_CARD_PARAM &&
19540 RlmtMode[pAC->Index] != NULL) {
19541 if (strcmp(RlmtMode[pAC->Index], "") == 0) {
19542- pAC->RlmtMode = 0;
19543+ if (pAC->GIni.GIMacsFound == 2) {
19544+ pAC->RlmtMode = SK_RLMT_CHECK_LINK;
19545+ pAC->RlmtNets = 2;
19546+ }
19547 } else if (strcmp(RlmtMode[pAC->Index], "CheckLinkState") == 0) {
19548 pAC->RlmtMode = SK_RLMT_CHECK_LINK;
19549 } else if (strcmp(RlmtMode[pAC->Index], "CheckLocalPort") == 0) {
19550@@ -3687,12 +5050,46 @@
19551 pAC->RlmtMode = 0;
19552 }
19553 } else {
19554- pAC->RlmtMode = 0;
19555+ if (pAC->GIni.GIMacsFound == 2) {
19556+ pAC->RlmtMode = SK_RLMT_CHECK_LINK;
19557+ pAC->RlmtNets = 2;
19558+ }
19559 }
19560-
19561+
19562+#ifdef SK_YUKON2
19563+ /*
19564+ ** use dualnet config per default
19565+ *
19566+ pAC->RlmtMode = SK_RLMT_CHECK_LINK;
19567+ pAC->RlmtNets = 2;
19568+ */
19569+#endif
19570+
19571+
19572+ /*
19573+ ** Check the LowLatance parameters
19574+ */
19575+ pAC->LowLatency = SK_FALSE;
19576+ if (LowLatency[pAC->Index] != NULL) {
19577+ if (strcmp(LowLatency[pAC->Index], "On") == 0) {
19578+ pAC->LowLatency = SK_TRUE;
19579+ }
19580+ }
19581+
19582+ /*
19583+ ** Check the BroadcastPrio parameters
19584+ */
19585+ pAC->Rlmt.Net[0].ChgBcPrio = SK_FALSE;
19586+ if (BroadcastPrio[pAC->Index] != NULL) {
19587+ if (strcmp(BroadcastPrio[pAC->Index], "On") == 0) {
19588+ pAC->Rlmt.Net[0].ChgBcPrio = SK_TRUE;
19589+ }
19590+ }
19591+
19592 /*
19593 ** Check the interrupt moderation parameters
19594 */
19595+ pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_NONE;
19596 if (Moderation[pAC->Index] != NULL) {
19597 if (strcmp(Moderation[pAC->Index], "") == 0) {
19598 pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_NONE;
19599@@ -3706,70 +5103,49 @@
19600 printk("sk98lin: Illegal value \"%s\" for Moderation.\n"
19601 " Disable interrupt moderation.\n",
19602 Moderation[pAC->Index]);
19603- pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_NONE;
19604- }
19605- } else {
19606- pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_NONE;
19607- }
19608-
19609- if (Stats[pAC->Index] != NULL) {
19610- if (strcmp(Stats[pAC->Index], "Yes") == 0) {
19611- pAC->DynIrqModInfo.DisplayStats = SK_TRUE;
19612- } else {
19613- pAC->DynIrqModInfo.DisplayStats = SK_FALSE;
19614 }
19615 } else {
19616- pAC->DynIrqModInfo.DisplayStats = SK_FALSE;
19617+/* Set interrupt moderation if wished */
19618+#ifdef CONFIG_SK98LIN_STATINT
19619+ pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_STATIC;
19620+#endif
19621 }
19622
19623 if (ModerationMask[pAC->Index] != NULL) {
19624 if (strcmp(ModerationMask[pAC->Index], "Rx") == 0) {
19625- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_ONLY;
19626+ IrqModMaskOffset = 0;
19627 } else if (strcmp(ModerationMask[pAC->Index], "Tx") == 0) {
19628- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_TX_ONLY;
19629+ IrqModMaskOffset = 1;
19630 } else if (strcmp(ModerationMask[pAC->Index], "Sp") == 0) {
19631- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_SP_ONLY;
19632+ IrqModMaskOffset = 2;
19633 } else if (strcmp(ModerationMask[pAC->Index], "RxSp") == 0) {
19634- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_SP_RX;
19635+ IrqModMaskOffset = 3;
19636 } else if (strcmp(ModerationMask[pAC->Index], "SpRx") == 0) {
19637- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_SP_RX;
19638+ IrqModMaskOffset = 3;
19639 } else if (strcmp(ModerationMask[pAC->Index], "RxTx") == 0) {
19640- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_TX_RX;
19641+ IrqModMaskOffset = 4;
19642 } else if (strcmp(ModerationMask[pAC->Index], "TxRx") == 0) {
19643- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_TX_RX;
19644+ IrqModMaskOffset = 4;
19645 } else if (strcmp(ModerationMask[pAC->Index], "TxSp") == 0) {
19646- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_SP_TX;
19647+ IrqModMaskOffset = 5;
19648 } else if (strcmp(ModerationMask[pAC->Index], "SpTx") == 0) {
19649- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_SP_TX;
19650- } else if (strcmp(ModerationMask[pAC->Index], "RxTxSp") == 0) {
19651- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP;
19652- } else if (strcmp(ModerationMask[pAC->Index], "RxSpTx") == 0) {
19653- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP;
19654- } else if (strcmp(ModerationMask[pAC->Index], "TxRxSp") == 0) {
19655- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP;
19656- } else if (strcmp(ModerationMask[pAC->Index], "TxSpRx") == 0) {
19657- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP;
19658- } else if (strcmp(ModerationMask[pAC->Index], "SpTxRx") == 0) {
19659- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP;
19660- } else if (strcmp(ModerationMask[pAC->Index], "SpRxTx") == 0) {
19661- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP;
19662- } else { /* some rubbish */
19663- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_ONLY;
19664- }
19665- } else { /* operator has stated nothing */
19666- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_TX_RX;
19667- }
19668-
19669- if (AutoSizing[pAC->Index] != NULL) {
19670- if (strcmp(AutoSizing[pAC->Index], "On") == 0) {
19671- pAC->DynIrqModInfo.AutoSizing = SK_FALSE;
19672- } else {
19673- pAC->DynIrqModInfo.AutoSizing = SK_FALSE;
19674+ IrqModMaskOffset = 5;
19675+ } else { /* some rubbish stated */
19676+ // IrqModMaskOffset = 6; ->has been initialized
19677+ // already at the begin of this function...
19678 }
19679- } else { /* operator has stated nothing */
19680- pAC->DynIrqModInfo.AutoSizing = SK_FALSE;
19681+ }
19682+ if (!CHIP_ID_YUKON_2(pAC)) {
19683+ pAC->DynIrqModInfo.MaskIrqModeration = IrqModMask[IrqModMaskOffset][0];
19684+ } else {
19685+ pAC->DynIrqModInfo.MaskIrqModeration = IrqModMask[IrqModMaskOffset][1];
19686 }
19687
19688+ if (!CHIP_ID_YUKON_2(pAC)) {
19689+ pAC->DynIrqModInfo.MaxModIntsPerSec = C_INTS_PER_SEC_DEFAULT;
19690+ } else {
19691+ pAC->DynIrqModInfo.MaxModIntsPerSec = C_Y2_INTS_PER_SEC_DEFAULT;
19692+ }
19693 if (IntsPerSec[pAC->Index] != 0) {
19694 if ((IntsPerSec[pAC->Index]< C_INT_MOD_IPS_LOWER_RANGE) ||
19695 (IntsPerSec[pAC->Index] > C_INT_MOD_IPS_UPPER_RANGE)) {
19696@@ -3778,28 +5154,25 @@
19697 IntsPerSec[pAC->Index],
19698 C_INT_MOD_IPS_LOWER_RANGE,
19699 C_INT_MOD_IPS_UPPER_RANGE,
19700- C_INTS_PER_SEC_DEFAULT);
19701- pAC->DynIrqModInfo.MaxModIntsPerSec = C_INTS_PER_SEC_DEFAULT;
19702+ pAC->DynIrqModInfo.MaxModIntsPerSec);
19703 } else {
19704 pAC->DynIrqModInfo.MaxModIntsPerSec = IntsPerSec[pAC->Index];
19705 }
19706- } else {
19707- pAC->DynIrqModInfo.MaxModIntsPerSec = C_INTS_PER_SEC_DEFAULT;
19708- }
19709+ }
19710
19711 /*
19712 ** Evaluate upper and lower moderation threshold
19713 */
19714 pAC->DynIrqModInfo.MaxModIntsPerSecUpperLimit =
19715 pAC->DynIrqModInfo.MaxModIntsPerSec +
19716- (pAC->DynIrqModInfo.MaxModIntsPerSec / 2);
19717+ (pAC->DynIrqModInfo.MaxModIntsPerSec / 5);
19718
19719 pAC->DynIrqModInfo.MaxModIntsPerSecLowerLimit =
19720 pAC->DynIrqModInfo.MaxModIntsPerSec -
19721- (pAC->DynIrqModInfo.MaxModIntsPerSec / 2);
19722-
19723- pAC->DynIrqModInfo.PrevTimeVal = jiffies; /* initial value */
19724+ (pAC->DynIrqModInfo.MaxModIntsPerSec / 5);
19725
19726+ pAC->DynIrqModInfo.DynIrqModSampleInterval =
19727+ SK_DRV_MODERATION_TIMER_LENGTH;
19728
19729 } /* GetConfiguration */
19730
19731@@ -3814,62 +5187,22 @@
19732 *
19733 * Returns: N/A
19734 */
19735-static inline int ProductStr(
19736- SK_AC *pAC, /* pointer to adapter context */
19737- char *DeviceStr, /* result string */
19738- int StrLen /* length of the string */
19739-)
19740+static void ProductStr(SK_AC *pAC)
19741 {
19742-char Keyword[] = VPD_NAME; /* vpd productname identifier */
19743-int ReturnCode; /* return code from vpd_read */
19744-unsigned long Flags;
19745+ char Default[] = "Generic Marvell Yukon chipset Ethernet device";
19746+ char Key[] = VPD_NAME; /* VPD productname key */
19747+ int StrLen = 80; /* stringlen */
19748+ unsigned long Flags;
19749
19750 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
19751- ReturnCode = VpdRead(pAC, pAC->IoBase, Keyword, DeviceStr, &StrLen);
19752+ if (VpdRead(pAC, pAC->IoBase, Key, pAC->DeviceStr, &StrLen)) {
19753+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ERROR,
19754+ ("Error reading VPD data: %d\n", ReturnCode));
19755+ strcpy(pAC->DeviceStr, Default);
19756+ }
19757 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
19758-
19759- return ReturnCode;
19760 } /* ProductStr */
19761
19762-/*****************************************************************************
19763- *
19764- * StartDrvCleanupTimer - Start timer to check for descriptors which
19765- * might be placed in descriptor ring, but
19766- * havent been handled up to now
19767- *
19768- * Description:
19769- * This function requests a HW-timer fo the Yukon card. The actions to
19770- * perform when this timer expires, are located in the SkDrvEvent().
19771- *
19772- * Returns: N/A
19773- */
19774-static void
19775-StartDrvCleanupTimer(SK_AC *pAC) {
19776- SK_EVPARA EventParam; /* Event struct for timer event */
19777-
19778- SK_MEMSET((char *) &EventParam, 0, sizeof(EventParam));
19779- EventParam.Para32[0] = SK_DRV_RX_CLEANUP_TIMER;
19780- SkTimerStart(pAC, pAC->IoBase, &pAC->DrvCleanupTimer,
19781- SK_DRV_RX_CLEANUP_TIMER_LENGTH,
19782- SKGE_DRV, SK_DRV_TIMER, EventParam);
19783-}
19784-
19785-/*****************************************************************************
19786- *
19787- * StopDrvCleanupTimer - Stop timer to check for descriptors
19788- *
19789- * Description:
19790- * This function requests a HW-timer fo the Yukon card. The actions to
19791- * perform when this timer expires, are located in the SkDrvEvent().
19792- *
19793- * Returns: N/A
19794- */
19795-static void
19796-StopDrvCleanupTimer(SK_AC *pAC) {
19797- SkTimerStop(pAC, pAC->IoBase, &pAC->DrvCleanupTimer);
19798- SK_MEMSET((char *) &pAC->DrvCleanupTimer, 0, sizeof(SK_TIMER));
19799-}
19800-
19801 /****************************************************************************/
19802 /* functions for common modules *********************************************/
19803 /****************************************************************************/
19804@@ -3958,7 +5291,9 @@
19805 SK_U64 SkOsGetTime(SK_AC *pAC)
19806 {
19807 SK_U64 PrivateJiffies;
19808+
19809 SkOsGetTimeCurrent(pAC, &PrivateJiffies);
19810+
19811 return PrivateJiffies;
19812 } /* SkOsGetTime */
19813
19814@@ -4031,6 +5366,28 @@
19815
19816 /*****************************************************************************
19817 *
19818+ * SkPciWriteCfgDWord - write a 32 bit value to pci config space
19819+ *
19820+ * Description:
19821+ * This routine writes a 32 bit value to the pci configuration
19822+ * space.
19823+ *
19824+ * Returns:
19825+ * 0 - indicate everything worked ok.
19826+ * != 0 - error indication
19827+ */
19828+int SkPciWriteCfgDWord(
19829+SK_AC *pAC, /* Adapter Control structure pointer */
19830+int PciAddr, /* PCI register address */
19831+SK_U32 Val) /* pointer to store the read value */
19832+{
19833+ pci_write_config_dword(pAC->PciDev, PciAddr, Val);
19834+ return(0);
19835+} /* SkPciWriteCfgDWord */
19836+
19837+
19838+/*****************************************************************************
19839+ *
19840 * SkPciWriteCfgWord - write a 16 bit value to pci config space
19841 *
19842 * Description:
19843@@ -4091,29 +5448,27 @@
19844 *
19845 */
19846 int SkDrvEvent(
19847-SK_AC *pAC, /* pointer to adapter context */
19848-SK_IOC IoC, /* io-context */
19849-SK_U32 Event, /* event-id */
19850-SK_EVPARA Param) /* event-parameter */
19851-{
19852-SK_MBUF *pRlmtMbuf; /* pointer to a rlmt-mbuf structure */
19853-struct sk_buff *pMsg; /* pointer to a message block */
19854-int FromPort; /* the port from which we switch away */
19855-int ToPort; /* the port we switch to */
19856-SK_EVPARA NewPara; /* parameter for further events */
19857-int Stat;
19858-unsigned long Flags;
19859-SK_BOOL DualNet;
19860+SK_AC *pAC, /* pointer to adapter context */
19861+SK_IOC IoC, /* IO control context */
19862+SK_U32 Event, /* event-id */
19863+SK_EVPARA Param) /* event-parameter */
19864+{
19865+ SK_MBUF *pRlmtMbuf; /* pointer to a rlmt-mbuf structure */
19866+ struct sk_buff *pMsg; /* pointer to a message block */
19867+ SK_BOOL DualNet;
19868+ SK_U32 Reason;
19869+ unsigned long Flags;
19870+ unsigned long InitFlags;
19871+ int FromPort; /* the port from which we switch away */
19872+ int ToPort; /* the port we switch to */
19873+ int Stat;
19874+ DEV_NET *pNet = NULL;
19875+#ifdef CONFIG_SK98LIN_NAPI
19876+ int WorkToDo = 1; /* min(*budget, dev->quota); */
19877+ int WorkDone = 0;
19878+#endif
19879
19880 switch (Event) {
19881- case SK_DRV_ADAP_FAIL:
19882- SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
19883- ("ADAPTER FAIL EVENT\n"));
19884- printk("%s: Adapter failed.\n", pAC->dev[0]->name);
19885- /* disable interrupts */
19886- SK_OUT32(pAC->IoBase, B0_IMSK, 0);
19887- /* cgoos */
19888- break;
19889 case SK_DRV_PORT_FAIL:
19890 FromPort = Param.Para32[0];
19891 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
19892@@ -4123,210 +5478,303 @@
19893 } else {
19894 printk("%s: Port B failed.\n", pAC->dev[1]->name);
19895 }
19896- /* cgoos */
19897 break;
19898- case SK_DRV_PORT_RESET: /* SK_U32 PortIdx */
19899- /* action list 4 */
19900+ case SK_DRV_PORT_RESET:
19901 FromPort = Param.Para32[0];
19902 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
19903 ("PORT RESET EVENT, Port: %d ", FromPort));
19904- NewPara.Para64 = FromPort;
19905- SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_XMAC_RESET, NewPara);
19906+ SkLocalEventQueue64(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET,
19907+ FromPort, SK_FALSE);
19908 spin_lock_irqsave(
19909 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
19910 Flags);
19911-
19912- SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_HARD_RST);
19913- netif_carrier_off(pAC->dev[Param.Para32[0]]);
19914+ if (CHIP_ID_YUKON_2(pAC)) {
19915+ SkY2PortStop(pAC, IoC, FromPort, SK_STOP_ALL, SK_HARD_RST);
19916+ } else {
19917+ SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_HARD_RST);
19918+ }
19919+ pAC->dev[Param.Para32[0]]->flags &= ~IFF_RUNNING;
19920 spin_unlock_irqrestore(
19921 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
19922 Flags);
19923
19924- /* clear rx ring from received frames */
19925- ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE);
19926-
19927- ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
19928+ if (!CHIP_ID_YUKON_2(pAC)) {
19929+#ifdef CONFIG_SK98LIN_NAPI
19930+ WorkToDo = 1;
19931+ ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE, &WorkDone, WorkToDo);
19932+#else
19933+ ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE);
19934+#endif
19935+ ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
19936+ }
19937 spin_lock_irqsave(
19938 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
19939 Flags);
19940-
19941- /* tschilling: Handling of return value inserted. */
19942- if (SkGeInitPort(pAC, IoC, FromPort)) {
19943- if (FromPort == 0) {
19944- printk("%s: SkGeInitPort A failed.\n", pAC->dev[0]->name);
19945+
19946+#ifdef USE_TIST_FOR_RESET
19947+ if (pAC->GIni.GIYukon2) {
19948+#ifdef Y2_RECOVERY
19949+ /* for Yukon II we want to have tist enabled all the time */
19950+ if (!SK_ADAPTER_WAITING_FOR_TIST(pAC)) {
19951+ Y2_ENABLE_TIST(pAC->IoBase);
19952+ }
19953+#else
19954+ /* make sure that we do not accept any status LEs from now on */
19955+ if (SK_ADAPTER_WAITING_FOR_TIST(pAC)) {
19956+#endif
19957+ /* port already waiting for tist */
19958+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
19959+ ("Port %c is now waiting for specific Tist\n",
19960+ 'A' + FromPort));
19961+ SK_SET_WAIT_BIT_FOR_PORT(
19962+ pAC,
19963+ SK_PSTATE_WAITING_FOR_SPECIFIC_TIST,
19964+ FromPort);
19965+ /* get current timestamp */
19966+ Y2_GET_TIST_LOW_VAL(pAC->IoBase, &pAC->MinTistLo);
19967+ pAC->MinTistHi = pAC->GIni.GITimeStampCnt;
19968+#ifndef Y2_RECOVERY
19969 } else {
19970- printk("%s: SkGeInitPort B failed.\n", pAC->dev[1]->name);
19971+ /* nobody is waiting yet */
19972+ SK_SET_WAIT_BIT_FOR_PORT(
19973+ pAC,
19974+ SK_PSTATE_WAITING_FOR_ANY_TIST,
19975+ FromPort);
19976+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
19977+ ("Port %c is now waiting for any Tist (0x%X)\n",
19978+ 'A' + FromPort, pAC->AdapterResetState));
19979+ /* start tist */
19980+ Y2_ENABLE_TIST(pAC-IoBase);
19981+ }
19982+#endif
19983+ }
19984+#endif
19985+
19986+#ifdef Y2_LE_CHECK
19987+ /* mark entries invalid */
19988+ pAC->LastPort = 3;
19989+ pAC->LastOpc = 0xFF;
19990+#endif
19991+ if (CHIP_ID_YUKON_2(pAC)) {
19992+ SkY2PortStart(pAC, IoC, FromPort);
19993+ } else {
19994+ /* tschilling: Handling of return value inserted. */
19995+ if (SkGeInitPort(pAC, IoC, FromPort)) {
19996+ if (FromPort == 0) {
19997+ printk("%s: SkGeInitPort A failed.\n", pAC->dev[0]->name);
19998+ } else {
19999+ printk("%s: SkGeInitPort B failed.\n", pAC->dev[1]->name);
20000+ }
20001 }
20002+ SkAddrMcUpdate(pAC,IoC, FromPort);
20003+ PortReInitBmu(pAC, FromPort);
20004+ SkGePollTxD(pAC, IoC, FromPort, SK_TRUE);
20005+ CLEAR_AND_START_RX(FromPort);
20006 }
20007- SkAddrMcUpdate(pAC,IoC, FromPort);
20008- PortReInitBmu(pAC, FromPort);
20009- SkGePollTxD(pAC, IoC, FromPort, SK_TRUE);
20010- ClearAndStartRx(pAC, FromPort);
20011 spin_unlock_irqrestore(
20012 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
20013 Flags);
20014 break;
20015- case SK_DRV_NET_UP: /* SK_U32 PortIdx */
20016- { struct net_device *dev = pAC->dev[Param.Para32[0]];
20017- /* action list 5 */
20018+ case SK_DRV_NET_UP:
20019+ spin_lock_irqsave(&pAC->InitLock, InitFlags);
20020 FromPort = Param.Para32[0];
20021 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
20022- ("NET UP EVENT, Port: %d ", Param.Para32[0]));
20023- /* Mac update */
20024- SkAddrMcUpdate(pAC,IoC, FromPort);
20025-
20026+ ("NET UP EVENT, Port: %d ", FromPort));
20027+ SkAddrMcUpdate(pAC,IoC, FromPort); /* Mac update */
20028 if (DoPrintInterfaceChange) {
20029- printk("%s: network connection up using"
20030- " port %c\n", pAC->dev[Param.Para32[0]]->name, 'A'+Param.Para32[0]);
20031+ printk("%s: network connection up using port %c\n",
20032+ pAC->dev[FromPort]->name, 'A'+FromPort);
20033
20034- /* tschilling: Values changed according to LinkSpeedUsed. */
20035- Stat = pAC->GIni.GP[FromPort].PLinkSpeedUsed;
20036- if (Stat == SK_LSPEED_STAT_10MBPS) {
20037- printk(" speed: 10\n");
20038- } else if (Stat == SK_LSPEED_STAT_100MBPS) {
20039- printk(" speed: 100\n");
20040- } else if (Stat == SK_LSPEED_STAT_1000MBPS) {
20041- printk(" speed: 1000\n");
20042- } else {
20043- printk(" speed: unknown\n");
20044- }
20045+ /* tschilling: Values changed according to LinkSpeedUsed. */
20046+ Stat = pAC->GIni.GP[FromPort].PLinkSpeedUsed;
20047+ if (Stat == SK_LSPEED_STAT_10MBPS) {
20048+ printk(" speed: 10\n");
20049+ } else if (Stat == SK_LSPEED_STAT_100MBPS) {
20050+ printk(" speed: 100\n");
20051+ } else if (Stat == SK_LSPEED_STAT_1000MBPS) {
20052+ printk(" speed: 1000\n");
20053+ } else {
20054+ printk(" speed: unknown\n");
20055+ }
20056
20057+ Stat = pAC->GIni.GP[FromPort].PLinkModeStatus;
20058+ if ((Stat == SK_LMODE_STAT_AUTOHALF) ||
20059+ (Stat == SK_LMODE_STAT_AUTOFULL)) {
20060+ printk(" autonegotiation: yes\n");
20061+ } else {
20062+ printk(" autonegotiation: no\n");
20063+ }
20064
20065- Stat = pAC->GIni.GP[FromPort].PLinkModeStatus;
20066- if (Stat == SK_LMODE_STAT_AUTOHALF ||
20067- Stat == SK_LMODE_STAT_AUTOFULL) {
20068- printk(" autonegotiation: yes\n");
20069- }
20070- else {
20071- printk(" autonegotiation: no\n");
20072- }
20073- if (Stat == SK_LMODE_STAT_AUTOHALF ||
20074- Stat == SK_LMODE_STAT_HALF) {
20075- printk(" duplex mode: half\n");
20076- }
20077- else {
20078- printk(" duplex mode: full\n");
20079- }
20080- Stat = pAC->GIni.GP[FromPort].PFlowCtrlStatus;
20081- if (Stat == SK_FLOW_STAT_REM_SEND ) {
20082- printk(" flowctrl: remote send\n");
20083- }
20084- else if (Stat == SK_FLOW_STAT_LOC_SEND ){
20085- printk(" flowctrl: local send\n");
20086- }
20087- else if (Stat == SK_FLOW_STAT_SYMMETRIC ){
20088- printk(" flowctrl: symmetric\n");
20089- }
20090- else {
20091- printk(" flowctrl: none\n");
20092- }
20093-
20094- /* tschilling: Check against CopperType now. */
20095- if ((pAC->GIni.GICopperType == SK_TRUE) &&
20096- (pAC->GIni.GP[FromPort].PLinkSpeedUsed ==
20097- SK_LSPEED_STAT_1000MBPS)) {
20098- Stat = pAC->GIni.GP[FromPort].PMSStatus;
20099- if (Stat == SK_MS_STAT_MASTER ) {
20100- printk(" role: master\n");
20101+ if ((Stat == SK_LMODE_STAT_AUTOHALF) ||
20102+ (Stat == SK_LMODE_STAT_HALF)) {
20103+ printk(" duplex mode: half\n");
20104+ } else {
20105+ printk(" duplex mode: full\n");
20106 }
20107- else if (Stat == SK_MS_STAT_SLAVE ) {
20108- printk(" role: slave\n");
20109+
20110+ Stat = pAC->GIni.GP[FromPort].PFlowCtrlStatus;
20111+ if (Stat == SK_FLOW_STAT_REM_SEND ) {
20112+ printk(" flowctrl: remote send\n");
20113+ } else if (Stat == SK_FLOW_STAT_LOC_SEND ) {
20114+ printk(" flowctrl: local send\n");
20115+ } else if (Stat == SK_FLOW_STAT_SYMMETRIC ) {
20116+ printk(" flowctrl: symmetric\n");
20117+ } else {
20118+ printk(" flowctrl: none\n");
20119 }
20120- else {
20121- printk(" role: ???\n");
20122+
20123+ /* tschilling: Check against CopperType now. */
20124+ if ((pAC->GIni.GICopperType == SK_TRUE) &&
20125+ (pAC->GIni.GP[FromPort].PLinkSpeedUsed ==
20126+ SK_LSPEED_STAT_1000MBPS)) {
20127+ Stat = pAC->GIni.GP[FromPort].PMSStatus;
20128+ if (Stat == SK_MS_STAT_MASTER ) {
20129+ printk(" role: master\n");
20130+ } else if (Stat == SK_MS_STAT_SLAVE ) {
20131+ printk(" role: slave\n");
20132+ } else {
20133+ printk(" role: ???\n");
20134+ }
20135 }
20136- }
20137
20138- /*
20139- Display dim (dynamic interrupt moderation)
20140- informations
20141- */
20142- if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_STATIC)
20143- printk(" irq moderation: static (%d ints/sec)\n",
20144+ /* Display interrupt moderation informations */
20145+ if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_STATIC) {
20146+ printk(" irq moderation: static (%d ints/sec)\n",
20147 pAC->DynIrqModInfo.MaxModIntsPerSec);
20148- else if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_DYNAMIC)
20149- printk(" irq moderation: dynamic (%d ints/sec)\n",
20150+ } else if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
20151+ printk(" irq moderation: dynamic (%d ints/sec)\n",
20152 pAC->DynIrqModInfo.MaxModIntsPerSec);
20153- else
20154- printk(" irq moderation: disabled\n");
20155+ } else {
20156+ printk(" irq moderation: disabled\n");
20157+ }
20158+
20159+#ifdef NETIF_F_TSO
20160+ if (CHIP_ID_YUKON_2(pAC)) {
20161+ if (pAC->dev[FromPort]->features & NETIF_F_TSO) {
20162+ printk(" tcp offload: enabled\n");
20163+ } else {
20164+ printk(" tcp offload: disabled\n");
20165+ }
20166+ }
20167+#endif
20168+
20169+ if (pAC->dev[FromPort]->features & NETIF_F_SG) {
20170+ printk(" scatter-gather: enabled\n");
20171+ } else {
20172+ printk(" scatter-gather: disabled\n");
20173+ }
20174
20175+ if (pAC->dev[FromPort]->features & NETIF_F_IP_CSUM) {
20176+ printk(" tx-checksum: enabled\n");
20177+ } else {
20178+ printk(" tx-checksum: disabled\n");
20179+ }
20180
20181- printk(" scatter-gather: %s\n",
20182- (dev->features & NETIF_F_SG) ? "enabled" : "disabled");
20183- printk(" tx-checksum: %s\n",
20184- (dev->features & NETIF_F_IP_CSUM) ? "enabled" : "disabled");
20185- printk(" rx-checksum: %s\n",
20186- pAC->RxPort[Param.Para32[0]].RxCsum ? "enabled" : "disabled");
20187+ if (pAC->RxPort[FromPort].UseRxCsum) {
20188+ printk(" rx-checksum: enabled\n");
20189+ } else {
20190+ printk(" rx-checksum: disabled\n");
20191+ }
20192+#ifdef CONFIG_SK98LIN_NAPI
20193+ printk(" rx-polling: enabled\n");
20194+#endif
20195+ if (pAC->LowLatency) {
20196+ printk(" low latency: enabled\n");
20197+ }
20198
20199+ if (pAC->Rlmt.Net[0].ChgBcPrio) {
20200+ printk(" broadcast prio: enabled\n");
20201+ }
20202+#ifdef SK_ASF
20203+ printk(" IPMI: enabled\n");
20204+#endif
20205 } else {
20206- DoPrintInterfaceChange = SK_TRUE;
20207- }
20208+ DoPrintInterfaceChange = SK_TRUE;
20209+ }
20210
20211- if ((Param.Para32[0] != pAC->ActivePort) &&
20212- (pAC->RlmtNets == 1)) {
20213- NewPara.Para32[0] = pAC->ActivePort;
20214- NewPara.Para32[1] = Param.Para32[0];
20215- SkEventQueue(pAC, SKGE_DRV, SK_DRV_SWITCH_INTERN,
20216- NewPara);
20217+ if ((FromPort != pAC->ActivePort)&&(pAC->RlmtNets == 1)) {
20218+ SkLocalEventQueue(pAC, SKGE_DRV, SK_DRV_SWITCH_INTERN,
20219+ pAC->ActivePort, FromPort, SK_FALSE);
20220 }
20221
20222 /* Inform the world that link protocol is up. */
20223- netif_carrier_on(dev);
20224+ netif_wake_queue(pAC->dev[FromPort]);
20225+ netif_carrier_on(pAC->dev[FromPort]);
20226+ pAC->dev[FromPort]->flags |= IFF_RUNNING;
20227+ spin_unlock_irqrestore(&pAC->InitLock, InitFlags);
20228 break;
20229- }
20230- case SK_DRV_NET_DOWN: /* SK_U32 Reason */
20231- /* action list 7 */
20232+ case SK_DRV_NET_DOWN:
20233+ Reason = Param.Para32[0];
20234+ FromPort = Param.Para32[1];
20235 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
20236 ("NET DOWN EVENT "));
20237+
20238+ /* Stop queue and carrier */
20239+ netif_stop_queue(pAC->dev[FromPort]);
20240+ netif_carrier_off(pAC->dev[FromPort]);
20241+
20242+ /* Print link change */
20243 if (DoPrintInterfaceChange) {
20244- printk("%s: network connection down\n",
20245- pAC->dev[Param.Para32[1]]->name);
20246+ if (pAC->dev[FromPort]->flags & IFF_RUNNING) {
20247+ printk("%s: network connection down\n",
20248+ pAC->dev[FromPort]->name);
20249+ }
20250 } else {
20251 DoPrintInterfaceChange = SK_TRUE;
20252 }
20253- netif_carrier_off(pAC->dev[Param.Para32[1]]);
20254+ pAC->dev[FromPort]->flags &= ~IFF_RUNNING;
20255 break;
20256- case SK_DRV_SWITCH_HARD: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */
20257- SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
20258- ("PORT SWITCH HARD "));
20259- case SK_DRV_SWITCH_SOFT: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */
20260- /* action list 6 */
20261- printk("%s: switching to port %c\n", pAC->dev[0]->name,
20262- 'A'+Param.Para32[1]);
20263- case SK_DRV_SWITCH_INTERN: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */
20264+ case SK_DRV_SWITCH_HARD: /* FALL THRU */
20265+ case SK_DRV_SWITCH_SOFT: /* FALL THRU */
20266+ case SK_DRV_SWITCH_INTERN:
20267 FromPort = Param.Para32[0];
20268- ToPort = Param.Para32[1];
20269+ ToPort = Param.Para32[1];
20270+ printk("%s: switching from port %c to port %c\n",
20271+ pAC->dev[0]->name, 'A'+FromPort, 'A'+ToPort);
20272 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
20273 ("PORT SWITCH EVENT, From: %d To: %d (Pref %d) ",
20274 FromPort, ToPort, pAC->Rlmt.Net[0].PrefPort));
20275- NewPara.Para64 = FromPort;
20276- SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_XMAC_RESET, NewPara);
20277- NewPara.Para64 = ToPort;
20278- SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_XMAC_RESET, NewPara);
20279+ SkLocalEventQueue64(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET,
20280+ FromPort, SK_FALSE);
20281+ SkLocalEventQueue64(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET,
20282+ ToPort, SK_FALSE);
20283 spin_lock_irqsave(
20284 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
20285 Flags);
20286 spin_lock(&pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock);
20287- SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST);
20288- SkGeStopPort(pAC, IoC, ToPort, SK_STOP_ALL, SK_SOFT_RST);
20289+ if (CHIP_ID_YUKON_2(pAC)) {
20290+ SkY2PortStop(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST);
20291+ SkY2PortStop(pAC, IoC, ToPort, SK_STOP_ALL, SK_SOFT_RST);
20292+ }
20293+ else {
20294+ SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST);
20295+ SkGeStopPort(pAC, IoC, ToPort, SK_STOP_ALL, SK_SOFT_RST);
20296+ }
20297 spin_unlock(&pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock);
20298 spin_unlock_irqrestore(
20299 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
20300 Flags);
20301
20302- ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE); /* clears rx ring */
20303- ReceiveIrq(pAC, &pAC->RxPort[ToPort], SK_FALSE); /* clears rx ring */
20304
20305- ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
20306- ClearTxRing(pAC, &pAC->TxPort[ToPort][TX_PRIO_LOW]);
20307+ if (!CHIP_ID_YUKON_2(pAC)) {
20308+#ifdef CONFIG_SK98LIN_NAPI
20309+ WorkToDo = 1;
20310+ ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE, &WorkDone, WorkToDo);
20311+ ReceiveIrq(pAC, &pAC->RxPort[ToPort], SK_FALSE, &WorkDone, WorkToDo);
20312+#else
20313+ ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE); /* clears rx ring */
20314+ ReceiveIrq(pAC, &pAC->RxPort[ToPort], SK_FALSE); /* clears rx ring */
20315+#endif
20316+ ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
20317+ ClearTxRing(pAC, &pAC->TxPort[ToPort][TX_PRIO_LOW]);
20318+ }
20319+
20320 spin_lock_irqsave(
20321 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
20322 Flags);
20323 spin_lock(&pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock);
20324 pAC->ActivePort = ToPort;
20325-#if 0
20326- SetQueueSizes(pAC);
20327-#else
20328+
20329 /* tschilling: New common function with minimum size check. */
20330 DualNet = SK_FALSE;
20331 if (pAC->RlmtNets == 2) {
20332@@ -4344,74 +5792,316 @@
20333 printk("SkGeInitAssignRamToQueues failed.\n");
20334 break;
20335 }
20336-#endif
20337- /* tschilling: Handling of return values inserted. */
20338- if (SkGeInitPort(pAC, IoC, FromPort) ||
20339- SkGeInitPort(pAC, IoC, ToPort)) {
20340- printk("%s: SkGeInitPort failed.\n", pAC->dev[0]->name);
20341+
20342+ if (!CHIP_ID_YUKON_2(pAC)) {
20343+ /* tschilling: Handling of return values inserted. */
20344+ if (SkGeInitPort(pAC, IoC, FromPort) ||
20345+ SkGeInitPort(pAC, IoC, ToPort)) {
20346+ printk("%s: SkGeInitPort failed.\n", pAC->dev[0]->name);
20347+ }
20348 }
20349- if (Event == SK_DRV_SWITCH_SOFT) {
20350- SkMacRxTxEnable(pAC, IoC, FromPort);
20351+ if (!CHIP_ID_YUKON_2(pAC)) {
20352+ if (Event == SK_DRV_SWITCH_SOFT) {
20353+ SkMacRxTxEnable(pAC, IoC, FromPort);
20354+ }
20355+ SkMacRxTxEnable(pAC, IoC, ToPort);
20356 }
20357- SkMacRxTxEnable(pAC, IoC, ToPort);
20358+
20359 SkAddrSwap(pAC, IoC, FromPort, ToPort);
20360 SkAddrMcUpdate(pAC, IoC, FromPort);
20361 SkAddrMcUpdate(pAC, IoC, ToPort);
20362- PortReInitBmu(pAC, FromPort);
20363- PortReInitBmu(pAC, ToPort);
20364- SkGePollTxD(pAC, IoC, FromPort, SK_TRUE);
20365- SkGePollTxD(pAC, IoC, ToPort, SK_TRUE);
20366- ClearAndStartRx(pAC, FromPort);
20367- ClearAndStartRx(pAC, ToPort);
20368+
20369+#ifdef USE_TIST_FOR_RESET
20370+ if (pAC->GIni.GIYukon2) {
20371+ /* make sure that we do not accept any status LEs from now on */
20372+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
20373+ ("both Ports now waiting for specific Tist\n"));
20374+ SK_SET_WAIT_BIT_FOR_PORT(
20375+ pAC,
20376+ SK_PSTATE_WAITING_FOR_ANY_TIST,
20377+ 0);
20378+ SK_SET_WAIT_BIT_FOR_PORT(
20379+ pAC,
20380+ SK_PSTATE_WAITING_FOR_ANY_TIST,
20381+ 1);
20382+
20383+ /* start tist */
20384+ Y2_ENABLE_TIST(pAC->IoBase);
20385+ }
20386+#endif
20387+ if (!CHIP_ID_YUKON_2(pAC)) {
20388+ PortReInitBmu(pAC, FromPort);
20389+ PortReInitBmu(pAC, ToPort);
20390+ SkGePollTxD(pAC, IoC, FromPort, SK_TRUE);
20391+ SkGePollTxD(pAC, IoC, ToPort, SK_TRUE);
20392+ CLEAR_AND_START_RX(FromPort);
20393+ CLEAR_AND_START_RX(ToPort);
20394+ } else {
20395+ SkY2PortStart(pAC, IoC, FromPort);
20396+ SkY2PortStart(pAC, IoC, ToPort);
20397+#ifdef SK_YUKON2
20398+ /* in yukon-II always port 0 has to be started first */
20399+ // SkY2PortStart(pAC, IoC, 0);
20400+ // SkY2PortStart(pAC, IoC, 1);
20401+#endif
20402+ }
20403 spin_unlock(&pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock);
20404 spin_unlock_irqrestore(
20405 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
20406 Flags);
20407 break;
20408 case SK_DRV_RLMT_SEND: /* SK_MBUF *pMb */
20409- SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
20410- ("RLS "));
20411+ SK_DBG_MSG(NULL,SK_DBGMOD_DRV,SK_DBGCAT_DRV_EVENT,("RLS "));
20412 pRlmtMbuf = (SK_MBUF*) Param.pParaPtr;
20413 pMsg = (struct sk_buff*) pRlmtMbuf->pOs;
20414 skb_put(pMsg, pRlmtMbuf->Length);
20415- if (XmitFrame(pAC, &pAC->TxPort[pRlmtMbuf->PortIdx][TX_PRIO_LOW],
20416- pMsg) < 0)
20417-
20418- DEV_KFREE_SKB_ANY(pMsg);
20419+ if (!CHIP_ID_YUKON_2(pAC)) {
20420+ if (XmitFrame(pAC, &pAC->TxPort[pRlmtMbuf->PortIdx][TX_PRIO_LOW],
20421+ pMsg) < 0) {
20422+ DEV_KFREE_SKB_ANY(pMsg);
20423+ }
20424+ } else {
20425+ if (SkY2RlmtSend(pAC, pRlmtMbuf->PortIdx, pMsg) < 0) {
20426+ DEV_KFREE_SKB_ANY(pMsg);
20427+ }
20428+ }
20429 break;
20430 case SK_DRV_TIMER:
20431 if (Param.Para32[0] == SK_DRV_MODERATION_TIMER) {
20432- /*
20433- ** expiration of the moderation timer implies that
20434- ** dynamic moderation is to be applied
20435- */
20436+ /* check what IRQs are to be moderated */
20437 SkDimStartModerationTimer(pAC);
20438 SkDimModerate(pAC);
20439- if (pAC->DynIrqModInfo.DisplayStats) {
20440- SkDimDisplayModerationSettings(pAC);
20441- }
20442- } else if (Param.Para32[0] == SK_DRV_RX_CLEANUP_TIMER) {
20443- /*
20444- ** check if we need to check for descriptors which
20445- ** haven't been handled the last millisecs
20446- */
20447- StartDrvCleanupTimer(pAC);
20448- if (pAC->GIni.GIMacsFound == 2) {
20449- ReceiveIrq(pAC, &pAC->RxPort[1], SK_FALSE);
20450- }
20451- ReceiveIrq(pAC, &pAC->RxPort[0], SK_FALSE);
20452 } else {
20453 printk("Expiration of unknown timer\n");
20454 }
20455 break;
20456+ case SK_DRV_ADAP_FAIL:
20457+#if (!defined (Y2_RECOVERY) && !defined (Y2_LE_CHECK))
20458+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
20459+ ("ADAPTER FAIL EVENT\n"));
20460+ printk("%s: Adapter failed.\n", pAC->dev[0]->name);
20461+ SK_OUT32(pAC->IoBase, B0_IMSK, 0); /* disable interrupts */
20462+ break;
20463+#endif
20464+
20465+#if (defined (Y2_RECOVERY) || defined (Y2_LE_CHECK))
20466+ case SK_DRV_RECOVER:
20467+ spin_lock_irqsave(&pAC->InitLock, InitFlags);
20468+ pNet = (DEV_NET *) pAC->dev[Param.Para32[0]]->priv;
20469+
20470+ /* Recover already in progress */
20471+ if (pNet->InRecover) {
20472+ break;
20473+ }
20474+
20475+ netif_stop_queue(pAC->dev[Param.Para32[0]]); /* stop device if running */
20476+ pNet->InRecover = SK_TRUE;
20477+
20478+ FromPort = Param.Para32[0];
20479+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
20480+ ("PORT RESET EVENT, Port: %d ", FromPort));
20481+
20482+ /* Disable interrupts */
20483+ SK_OUT32(pAC->IoBase, B0_IMSK, 0);
20484+ SK_OUT32(pAC->IoBase, B0_HWE_IMSK, 0);
20485+
20486+ SkLocalEventQueue64(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET,
20487+ FromPort, SK_FALSE);
20488+ spin_lock_irqsave(
20489+ &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
20490+ Flags);
20491+ if (CHIP_ID_YUKON_2(pAC)) {
20492+ SkY2PortStop(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST);
20493+ } else {
20494+ SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST);
20495+ }
20496+ pAC->dev[Param.Para32[0]]->flags &= ~IFF_RUNNING;
20497+ spin_unlock_irqrestore(
20498+ &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
20499+ Flags);
20500+
20501+ if (!CHIP_ID_YUKON_2(pAC)) {
20502+#ifdef CONFIG_SK98LIN_NAPI
20503+ WorkToDo = 1;
20504+ ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE, &WorkDone, WorkToDo);
20505+#else
20506+ ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE);
20507+#endif
20508+ ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
20509+ }
20510+ spin_lock_irqsave(
20511+ &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
20512+ Flags);
20513+
20514+#ifdef USE_TIST_FOR_RESET
20515+ if (pAC->GIni.GIYukon2) {
20516+#if 0
20517+ /* make sure that we do not accept any status LEs from now on */
20518+ Y2_ENABLE_TIST(pAC->IoBase);
20519+
20520+ /* get current timestamp */
20521+ Y2_GET_TIST_LOW_VAL(pAC->IoBase, &pAC->MinTistLo);
20522+ pAC->MinTistHi = pAC->GIni.GITimeStampCnt;
20523+
20524+ SK_SET_WAIT_BIT_FOR_PORT(
20525+ pAC,
20526+ SK_PSTATE_WAITING_FOR_SPECIFIC_TIST,
20527+ FromPort);
20528+#endif
20529+ SK_SET_WAIT_BIT_FOR_PORT(
20530+ pAC,
20531+ SK_PSTATE_WAITING_FOR_ANY_TIST,
20532+ FromPort);
20533+
20534+ /* start tist */
20535+ Y2_ENABLE_TIST(pAC->IoBase);
20536+ }
20537+#endif
20538+
20539+ /* Restart Receive BMU on Yukon-2 */
20540+ if (HW_FEATURE(pAC, HWF_WA_DEV_4167)) {
20541+ SkYuk2RestartRxBmu(pAC, IoC, FromPort);
20542+ }
20543+
20544+#ifdef Y2_LE_CHECK
20545+ /* mark entries invalid */
20546+ pAC->LastPort = 3;
20547+ pAC->LastOpc = 0xFF;
20548+#endif
20549+
20550+#endif
20551+ /* Restart ports but do not initialize PHY. */
20552+ if (CHIP_ID_YUKON_2(pAC)) {
20553+ SkY2PortStart(pAC, IoC, FromPort);
20554+ } else {
20555+ /* tschilling: Handling of return value inserted. */
20556+ if (SkGeInitPort(pAC, IoC, FromPort)) {
20557+ if (FromPort == 0) {
20558+ printk("%s: SkGeInitPort A failed.\n", pAC->dev[0]->name);
20559+ } else {
20560+ printk("%s: SkGeInitPort B failed.\n", pAC->dev[1]->name);
20561+ }
20562+ }
20563+ SkAddrMcUpdate(pAC,IoC, FromPort);
20564+ PortReInitBmu(pAC, FromPort);
20565+ SkGePollTxD(pAC, IoC, FromPort, SK_TRUE);
20566+ CLEAR_AND_START_RX(FromPort);
20567+ }
20568+ spin_unlock_irqrestore(
20569+ &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
20570+ Flags);
20571+
20572+ /* Map any waiting RX buffers to HW */
20573+ FillReceiveTableYukon2(pAC, pAC->IoBase, FromPort);
20574+
20575+ pNet->InRecover = SK_FALSE;
20576+ /* enable Interrupts */
20577+ SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
20578+ SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK);
20579+ netif_wake_queue(pAC->dev[FromPort]);
20580+ spin_unlock_irqrestore(&pAC->InitLock, InitFlags);
20581+ break;
20582 default:
20583 break;
20584 }
20585- SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
20586- ("END EVENT "));
20587-
20588- return (0);
20589-} /* SkDrvEvent */
20590+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
20591+ ("END EVENT "));
20592+
20593+ return (0);
20594+} /* SkDrvEvent */
20595+
20596+
20597+/******************************************************************************
20598+ *
20599+ * SkLocalEventQueue() - add event to queue
20600+ *
20601+ * Description:
20602+ * This function adds an event to the event queue and run the
20603+ * SkEventDispatcher. At least Init Level 1 is required to queue events,
20604+ * but will be scheduled add Init Level 2.
20605+ *
20606+ * returns:
20607+ * nothing
20608+ */
20609+void SkLocalEventQueue(
20610+SK_AC *pAC, /* Adapters context */
20611+SK_U32 Class, /* Event Class */
20612+SK_U32 Event, /* Event to be queued */
20613+SK_U32 Param1, /* Event parameter 1 */
20614+SK_U32 Param2, /* Event parameter 2 */
20615+SK_BOOL Dispatcher) /* Dispatcher flag:
20616+ * TRUE == Call SkEventDispatcher
20617+ * FALSE == Don't execute SkEventDispatcher
20618+ */
20619+{
20620+ SK_EVPARA EvPara;
20621+ EvPara.Para32[0] = Param1;
20622+ EvPara.Para32[1] = Param2;
20623+
20624+
20625+ if (Class == SKGE_PNMI) {
20626+ SkPnmiEvent( pAC,
20627+ pAC->IoBase,
20628+ Event,
20629+ EvPara);
20630+ } else {
20631+ SkEventQueue( pAC,
20632+ Class,
20633+ Event,
20634+ EvPara);
20635+ }
20636+
20637+ /* Run the dispatcher */
20638+ if (Dispatcher) {
20639+ SkEventDispatcher(pAC, pAC->IoBase);
20640+ }
20641+
20642+}
20643+
20644+/******************************************************************************
20645+ *
20646+ * SkLocalEventQueue64() - add event to queue (64bit version)
20647+ *
20648+ * Description:
20649+ * This function adds an event to the event queue and run the
20650+ * SkEventDispatcher. At least Init Level 1 is required to queue events,
20651+ * but will be scheduled add Init Level 2.
20652+ *
20653+ * returns:
20654+ * nothing
20655+ */
20656+void SkLocalEventQueue64(
20657+SK_AC *pAC, /* Adapters context */
20658+SK_U32 Class, /* Event Class */
20659+SK_U32 Event, /* Event to be queued */
20660+SK_U64 Param, /* Event parameter */
20661+SK_BOOL Dispatcher) /* Dispatcher flag:
20662+ * TRUE == Call SkEventDispatcher
20663+ * FALSE == Don't execute SkEventDispatcher
20664+ */
20665+{
20666+ SK_EVPARA EvPara;
20667+ EvPara.Para64 = Param;
20668+
20669+
20670+ if (Class == SKGE_PNMI) {
20671+ SkPnmiEvent( pAC,
20672+ pAC->IoBase,
20673+ Event,
20674+ EvPara);
20675+ } else {
20676+ SkEventQueue( pAC,
20677+ Class,
20678+ Event,
20679+ EvPara);
20680+ }
20681+
20682+ /* Run the dispatcher */
20683+ if (Dispatcher) {
20684+ SkEventDispatcher(pAC, pAC->IoBase);
20685+ }
20686+
20687+}
20688
20689
20690 /*****************************************************************************
20691@@ -4456,14 +6146,22 @@
20692 case SK_ERRCL_COMM:
20693 strcpy(ClassStr, "Communication error");
20694 break;
20695+ case SK_ERRCL_INFO:
20696+ strcpy(ClassStr, "Information");
20697+ break;
20698 }
20699- printk(KERN_INFO "%s: -- ERROR --\n Class: %s\n"
20700- " Nr: 0x%x\n Msg: %s\n", pAC->dev[0]->name,
20701- ClassStr, ErrNum, pErrorMsg);
20702
20703-} /* SkErrorLog */
20704+ if (ErrClass == SK_ERRCL_INFO) {
20705+ printk(KERN_INFO "%s: -- INFORMATION --\n"
20706+ " Msg: %s\n", pAC->dev[0]->name,
20707+ pErrorMsg);
20708+ } else {
20709+ printk(KERN_INFO "%s: -- ERROR --\n Class: %s\n"
20710+ " Nr: 0x%x\n Msg: %s\n", pAC->dev[0]->name,
20711+ ClassStr, ErrNum, pErrorMsg);
20712+ }
20713
20714-#ifdef SK_DIAG_SUPPORT
20715+} /* SkErrorLog */
20716
20717 /*****************************************************************************
20718 *
20719@@ -4479,8 +6177,11 @@
20720 int SkDrvEnterDiagMode(
20721 SK_AC *pAc) /* pointer to adapter context */
20722 {
20723- DEV_NET *pNet = netdev_priv(pAc->dev[0]);
20724- SK_AC *pAC = pNet->pAC;
20725+ SK_AC *pAC = NULL;
20726+ DEV_NET *pNet = NULL;
20727+
20728+ pNet = (DEV_NET *) pAc->dev[0]->priv;
20729+ pAC = pNet->pAC;
20730
20731 SK_MEMCPY(&(pAc->PnmiBackup), &(pAc->PnmiStruct),
20732 sizeof(SK_PNMI_STRUCT_DATA));
20733@@ -4495,8 +6196,9 @@
20734 } else {
20735 pAC->WasIfUp[0] = SK_FALSE;
20736 }
20737- if (pNet != netdev_priv(pAC->dev[1])) {
20738- pNet = netdev_priv(pAC->dev[1]);
20739+
20740+ if (pNet != (DEV_NET *) pAc->dev[1]->priv) {
20741+ pNet = (DEV_NET *) pAc->dev[1]->priv;
20742 if (netif_running(pAC->dev[1])) {
20743 pAC->WasIfUp[1] = SK_TRUE;
20744 pAC->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */
20745@@ -4529,16 +6231,16 @@
20746 sizeof(SK_PNMI_STRUCT_DATA));
20747 pAc->DiagModeActive = DIAG_NOTACTIVE;
20748 pAc->Pnmi.DiagAttached = SK_DIAG_IDLE;
20749- if (pAc->WasIfUp[0] == SK_TRUE) {
20750- pAc->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */
20751+ if (pAc->WasIfUp[0] == SK_TRUE) {
20752+ pAc->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */
20753 DoPrintInterfaceChange = SK_FALSE;
20754- SkDrvInitAdapter(pAc, 0); /* first device */
20755- }
20756- if (pAc->WasIfUp[1] == SK_TRUE) {
20757- pAc->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */
20758+ SkDrvInitAdapter(pAc, 0); /* first device */
20759+ }
20760+ if (pAc->WasIfUp[1] == SK_TRUE) {
20761+ pAc->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */
20762 DoPrintInterfaceChange = SK_FALSE;
20763- SkDrvInitAdapter(pAc, 1); /* second device */
20764- }
20765+ SkDrvInitAdapter(pAc, 1); /* second device */
20766+ }
20767 return(0);
20768 }
20769
20770@@ -4618,11 +6320,20 @@
20771
20772 dev = pAC->dev[devNbr];
20773
20774- /* On Linux 2.6 the network driver does NOT mess with reference
20775- ** counts. The driver MUST be able to be unloaded at any time
20776- ** due to the possibility of hotplug.
20777+ /*
20778+ ** Function SkGeClose() uses MOD_DEC_USE_COUNT (2.2/2.4)
20779+ ** or module_put() (2.6) to decrease the number of users for
20780+ ** a device, but if a device is to be put under control of
20781+ ** the DIAG, that count is OK already and does not need to
20782+ ** be adapted! Hence the opposite MOD_INC_USE_COUNT or
20783+ ** try_module_get() needs to be used again to correct that.
20784 */
20785+ if (!try_module_get(THIS_MODULE)) {
20786+ return (-1);
20787+ }
20788+
20789 if (SkGeClose(dev) != 0) {
20790+ module_put(THIS_MODULE);
20791 return (-1);
20792 }
20793 return (0);
20794@@ -4651,6 +6362,17 @@
20795
20796 if (SkGeOpen(dev) != 0) {
20797 return (-1);
20798+ } else {
20799+ /*
20800+ ** Function SkGeOpen() uses MOD_INC_USE_COUNT (2.2/2.4)
20801+ ** or try_module_get() (2.6) to increase the number of
20802+ ** users for a device, but if a device was just under
20803+ ** control of the DIAG, that count is OK already and
20804+ ** does not need to be adapted! Hence the opposite
20805+ ** MOD_DEC_USE_COUNT or module_put() needs to be used
20806+ ** again to correct that.
20807+ */
20808+ module_put(THIS_MODULE);
20809 }
20810
20811 /*
20812@@ -4663,14 +6385,25 @@
20813
20814 } /* SkDrvInitAdapter */
20815
20816-#endif
20817+static int __init sk98lin_init(void)
20818+{
20819+ return pci_module_init(&sk98lin_driver);
20820+}
20821+
20822+static void __exit sk98lin_cleanup(void)
20823+{
20824+ pci_unregister_driver(&sk98lin_driver);
20825+}
20826+
20827+module_init(sk98lin_init);
20828+module_exit(sk98lin_cleanup);
20829+
20830
20831 #ifdef DEBUG
20832 /****************************************************************************/
20833 /* "debug only" section *****************************************************/
20834 /****************************************************************************/
20835
20836-
20837 /*****************************************************************************
20838 *
20839 * DumpMsg - print a frame
20840@@ -4681,9 +6414,11 @@
20841 * Returns: N/A
20842 *
20843 */
20844-static void DumpMsg(struct sk_buff *skb, char *str)
20845+static void DumpMsg(
20846+struct sk_buff *skb, /* linux' socket buffer */
20847+char *str) /* additional msg string */
20848 {
20849- int msglen;
20850+ int msglen = (skb->len > 64) ? 64 : skb->len;
20851
20852 if (skb == NULL) {
20853 printk("DumpMsg(): NULL-Message\n");
20854@@ -4695,19 +6430,14 @@
20855 return;
20856 }
20857
20858- msglen = skb->len;
20859- if (msglen > 64)
20860- msglen = 64;
20861-
20862- printk("--- Begin of message from %s , len %d (from %d) ----\n", str, msglen, skb->len);
20863-
20864+ printk("DumpMsg: PhysPage: %p\n",
20865+ page_address(virt_to_page(skb->data)));
20866+ printk("--- Begin of message from %s , len %d (from %d) ----\n",
20867+ str, msglen, skb->len);
20868 DumpData((char *)skb->data, msglen);
20869-
20870 printk("------- End of message ---------\n");
20871 } /* DumpMsg */
20872
20873-
20874-
20875 /*****************************************************************************
20876 *
20877 * DumpData - print a data area
20878@@ -4719,23 +6449,22 @@
20879 * Returns: N/A
20880 *
20881 */
20882-static void DumpData(char *p, int size)
20883-{
20884-register int i;
20885-int haddr, addr;
20886-char hex_buffer[180];
20887-char asc_buffer[180];
20888-char HEXCHAR[] = "0123456789ABCDEF";
20889-
20890- addr = 0;
20891- haddr = 0;
20892- hex_buffer[0] = 0;
20893- asc_buffer[0] = 0;
20894+static void DumpData(
20895+char *p, /* pointer to area containing the data */
20896+int size) /* the size of that data area in bytes */
20897+{
20898+ register int i;
20899+ int haddr = 0, addr = 0;
20900+ char hex_buffer[180] = { '\0' };
20901+ char asc_buffer[180] = { '\0' };
20902+ char HEXCHAR[] = "0123456789ABCDEF";
20903+
20904 for (i=0; i < size; ) {
20905- if (*p >= '0' && *p <='z')
20906+ if (*p >= '0' && *p <='z') {
20907 asc_buffer[addr] = *p;
20908- else
20909+ } else {
20910 asc_buffer[addr] = '.';
20911+ }
20912 addr++;
20913 asc_buffer[addr] = 0;
20914 hex_buffer[haddr] = HEXCHAR[(*p & 0xf0) >> 4];
20915@@ -4761,27 +6490,24 @@
20916 * DumpLong - print a data area as long values
20917 *
20918 * Description:
20919- * This function prints a area of data to the system logfile/to the
20920+ * This function prints a long variable to the system logfile/to the
20921 * console.
20922 *
20923 * Returns: N/A
20924 *
20925 */
20926-static void DumpLong(char *pc, int size)
20927-{
20928-register int i;
20929-int haddr, addr;
20930-char hex_buffer[180];
20931-char asc_buffer[180];
20932-char HEXCHAR[] = "0123456789ABCDEF";
20933-long *p;
20934-int l;
20935-
20936- addr = 0;
20937- haddr = 0;
20938- hex_buffer[0] = 0;
20939- asc_buffer[0] = 0;
20940- p = (long*) pc;
20941+static void DumpLong(
20942+char *pc, /* location of the variable to print */
20943+int size) /* how large is the variable? */
20944+{
20945+ register int i;
20946+ int haddr = 0, addr = 0;
20947+ char hex_buffer[180] = { '\0' };
20948+ char asc_buffer[180] = { '\0' };
20949+ char HEXCHAR[] = "0123456789ABCDEF";
20950+ long *p = (long*) pc;
20951+ int l;
20952+
20953 for (i=0; i < size; ) {
20954 l = (long) *p;
20955 hex_buffer[haddr] = HEXCHAR[(l >> 28) & 0xf];
638cbd52 20956@@ -4815,389 +6541,9 @@
a3b93527 20957
20958 #endif
20959
20960-static int __devinit skge_probe_one(struct pci_dev *pdev,
20961- const struct pci_device_id *ent)
20962-{
20963- SK_AC *pAC;
20964- DEV_NET *pNet = NULL;
20965- struct net_device *dev = NULL;
20966- static int boards_found = 0;
20967- int error = -ENODEV;
20968- int using_dac = 0;
20969- char DeviceStr[80];
20970-
20971- if (pci_enable_device(pdev))
20972- goto out;
20973-
20974- /* Configure DMA attributes. */
20975- if (sizeof(dma_addr_t) > sizeof(u32) &&
20976- !(error = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
20977- using_dac = 1;
20978- error = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
20979- if (error < 0) {
20980- printk(KERN_ERR "sk98lin %s unable to obtain 64 bit DMA "
20981- "for consistent allocations\n", pci_name(pdev));
20982- goto out_disable_device;
20983- }
20984- } else {
20985- error = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
20986- if (error) {
20987- printk(KERN_ERR "sk98lin %s no usable DMA configuration\n",
20988- pci_name(pdev));
20989- goto out_disable_device;
20990- }
20991- }
20992-
20993- error = -ENOMEM;
20994- dev = alloc_etherdev(sizeof(DEV_NET));
20995- if (!dev) {
20996- printk(KERN_ERR "sk98lin: unable to allocate etherdev "
20997- "structure!\n");
20998- goto out_disable_device;
20999- }
21000-
21001- pNet = netdev_priv(dev);
21002- pNet->pAC = kzalloc(sizeof(SK_AC), GFP_KERNEL);
21003- if (!pNet->pAC) {
21004- printk(KERN_ERR "sk98lin: unable to allocate adapter "
21005- "structure!\n");
21006- goto out_free_netdev;
21007- }
21008-
21009- pAC = pNet->pAC;
21010- pAC->PciDev = pdev;
21011-
21012- pAC->dev[0] = dev;
21013- pAC->dev[1] = dev;
21014- pAC->CheckQueue = SK_FALSE;
21015-
21016- dev->irq = pdev->irq;
21017-
21018- error = SkGeInitPCI(pAC);
21019- if (error) {
21020- printk(KERN_ERR "sk98lin: PCI setup failed: %i\n", error);
21021- goto out_free_netdev;
21022- }
21023-
21024- SET_MODULE_OWNER(dev);
21025- dev->open = &SkGeOpen;
21026- dev->stop = &SkGeClose;
21027- dev->hard_start_xmit = &SkGeXmit;
21028- dev->get_stats = &SkGeStats;
21029- dev->set_multicast_list = &SkGeSetRxMode;
21030- dev->set_mac_address = &SkGeSetMacAddr;
21031- dev->do_ioctl = &SkGeIoctl;
21032- dev->change_mtu = &SkGeChangeMtu;
21033-#ifdef CONFIG_NET_POLL_CONTROLLER
21034- dev->poll_controller = &SkGePollController;
21035-#endif
21036- SET_NETDEV_DEV(dev, &pdev->dev);
21037- SET_ETHTOOL_OPS(dev, &SkGeEthtoolOps);
21038-
21039- /* Use only if yukon hardware */
21040- if (pAC->ChipsetType) {
21041-#ifdef USE_SK_TX_CHECKSUM
21042- dev->features |= NETIF_F_IP_CSUM;
21043-#endif
21044-#ifdef SK_ZEROCOPY
21045- dev->features |= NETIF_F_SG;
21046-#endif
21047-#ifdef USE_SK_RX_CHECKSUM
21048- pAC->RxPort[0].RxCsum = 1;
21049-#endif
21050- }
21051-
21052- if (using_dac)
21053- dev->features |= NETIF_F_HIGHDMA;
21054-
21055- pAC->Index = boards_found++;
21056-
21057- error = SkGeBoardInit(dev, pAC);
21058- if (error)
21059- goto out_free_netdev;
21060-
21061- /* Read Adapter name from VPD */
21062- if (ProductStr(pAC, DeviceStr, sizeof(DeviceStr)) != 0) {
21063- error = -EIO;
21064- printk(KERN_ERR "sk98lin: Could not read VPD data.\n");
21065- goto out_free_resources;
21066- }
21067-
21068- /* Register net device */
21069- error = register_netdev(dev);
21070- if (error) {
21071- printk(KERN_ERR "sk98lin: Could not register device.\n");
21072- goto out_free_resources;
21073- }
21074-
21075- /* Print adapter specific string from vpd */
21076- printk("%s: %s\n", dev->name, DeviceStr);
21077-
21078- /* Print configuration settings */
21079- printk(" PrefPort:%c RlmtMode:%s\n",
21080- 'A' + pAC->Rlmt.Net[0].Port[pAC->Rlmt.Net[0].PrefPort]->PortNumber,
21081- (pAC->RlmtMode==0) ? "Check Link State" :
21082- ((pAC->RlmtMode==1) ? "Check Link State" :
21083- ((pAC->RlmtMode==3) ? "Check Local Port" :
21084- ((pAC->RlmtMode==7) ? "Check Segmentation" :
21085- ((pAC->RlmtMode==17) ? "Dual Check Link State" :"Error")))));
21086-
21087- SkGeYellowLED(pAC, pAC->IoBase, 1);
21088-
21089- memcpy(&dev->dev_addr, &pAC->Addr.Net[0].CurrentMacAddress, 6);
21090- memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
21091-
21092- pNet->PortNr = 0;
21093- pNet->NetNr = 0;
21094-
21095- boards_found++;
21096-
21097- pci_set_drvdata(pdev, dev);
21098-
21099- /* More then one port found */
21100- if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
21101- dev = alloc_etherdev(sizeof(DEV_NET));
21102- if (!dev) {
21103- printk(KERN_ERR "sk98lin: unable to allocate etherdev "
21104- "structure!\n");
21105- goto single_port;
21106- }
21107-
21108- pNet = netdev_priv(dev);
21109- pNet->PortNr = 1;
21110- pNet->NetNr = 1;
21111- pNet->pAC = pAC;
21112-
21113- dev->open = &SkGeOpen;
21114- dev->stop = &SkGeClose;
21115- dev->hard_start_xmit = &SkGeXmit;
21116- dev->get_stats = &SkGeStats;
21117- dev->set_multicast_list = &SkGeSetRxMode;
21118- dev->set_mac_address = &SkGeSetMacAddr;
21119- dev->do_ioctl = &SkGeIoctl;
21120- dev->change_mtu = &SkGeChangeMtu;
21121- SET_NETDEV_DEV(dev, &pdev->dev);
21122- SET_ETHTOOL_OPS(dev, &SkGeEthtoolOps);
21123-
21124- if (pAC->ChipsetType) {
21125-#ifdef USE_SK_TX_CHECKSUM
21126- dev->features |= NETIF_F_IP_CSUM;
21127-#endif
21128-#ifdef SK_ZEROCOPY
21129- dev->features |= NETIF_F_SG;
21130-#endif
21131-#ifdef USE_SK_RX_CHECKSUM
21132- pAC->RxPort[1].RxCsum = 1;
21133-#endif
21134- }
21135-
21136- if (using_dac)
21137- dev->features |= NETIF_F_HIGHDMA;
21138-
21139- error = register_netdev(dev);
21140- if (error) {
21141- printk(KERN_ERR "sk98lin: Could not register device"
21142- " for second port. (%d)\n", error);
21143- free_netdev(dev);
21144- goto single_port;
21145- }
21146-
21147- pAC->dev[1] = dev;
21148- memcpy(&dev->dev_addr,
21149- &pAC->Addr.Net[1].CurrentMacAddress, 6);
21150- memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
21151-
21152- printk("%s: %s\n", dev->name, DeviceStr);
21153- printk(" PrefPort:B RlmtMode:Dual Check Link State\n");
21154- }
21155-
21156-single_port:
21157-
21158- /* Save the hardware revision */
21159- pAC->HWRevision = (((pAC->GIni.GIPciHwRev >> 4) & 0x0F)*10) +
21160- (pAC->GIni.GIPciHwRev & 0x0F);
21161-
21162- /* Set driver globals */
21163- pAC->Pnmi.pDriverFileName = DRIVER_FILE_NAME;
21164- pAC->Pnmi.pDriverReleaseDate = DRIVER_REL_DATE;
21165-
21166- memset(&pAC->PnmiBackup, 0, sizeof(SK_PNMI_STRUCT_DATA));
21167- memcpy(&pAC->PnmiBackup, &pAC->PnmiStruct, sizeof(SK_PNMI_STRUCT_DATA));
21168-
21169- return 0;
21170-
21171- out_free_resources:
21172- FreeResources(dev);
21173- out_free_netdev:
21174- free_netdev(dev);
21175- out_disable_device:
21176- pci_disable_device(pdev);
21177- out:
21178- return error;
21179-}
21180-
21181-static void __devexit skge_remove_one(struct pci_dev *pdev)
21182-{
21183- struct net_device *dev = pci_get_drvdata(pdev);
21184- DEV_NET *pNet = netdev_priv(dev);
21185- SK_AC *pAC = pNet->pAC;
21186- struct net_device *otherdev = pAC->dev[1];
21187-
21188- unregister_netdev(dev);
21189-
21190- SkGeYellowLED(pAC, pAC->IoBase, 0);
21191-
21192- if (pAC->BoardLevel == SK_INIT_RUN) {
21193- SK_EVPARA EvPara;
21194- unsigned long Flags;
21195-
21196- /* board is still alive */
21197- spin_lock_irqsave(&pAC->SlowPathLock, Flags);
21198- EvPara.Para32[0] = 0;
21199- EvPara.Para32[1] = -1;
21200- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
21201- EvPara.Para32[0] = 1;
21202- EvPara.Para32[1] = -1;
21203- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
21204- SkEventDispatcher(pAC, pAC->IoBase);
21205- /* disable interrupts */
21206- SK_OUT32(pAC->IoBase, B0_IMSK, 0);
21207- SkGeDeInit(pAC, pAC->IoBase);
21208- spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
21209- pAC->BoardLevel = SK_INIT_DATA;
21210- /* We do NOT check here, if IRQ was pending, of course*/
21211- }
21212-
21213- if (pAC->BoardLevel == SK_INIT_IO) {
21214- /* board is still alive */
21215- SkGeDeInit(pAC, pAC->IoBase);
21216- pAC->BoardLevel = SK_INIT_DATA;
21217- }
21218-
21219- FreeResources(dev);
21220- free_netdev(dev);
21221- if (otherdev != dev)
21222- free_netdev(otherdev);
21223- kfree(pAC);
21224-}
21225-
21226-#ifdef CONFIG_PM
21227-static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
21228-{
21229- struct net_device *dev = pci_get_drvdata(pdev);
21230- DEV_NET *pNet = netdev_priv(dev);
21231- SK_AC *pAC = pNet->pAC;
21232- struct net_device *otherdev = pAC->dev[1];
21233-
21234- if (netif_running(dev)) {
21235- netif_carrier_off(dev);
21236- DoPrintInterfaceChange = SK_FALSE;
21237- SkDrvDeInitAdapter(pAC, 0); /* performs SkGeClose */
21238- netif_device_detach(dev);
21239- }
21240- if (otherdev != dev) {
21241- if (netif_running(otherdev)) {
21242- netif_carrier_off(otherdev);
21243- DoPrintInterfaceChange = SK_FALSE;
21244- SkDrvDeInitAdapter(pAC, 1); /* performs SkGeClose */
21245- netif_device_detach(otherdev);
21246- }
21247- }
21248-
21249- pci_save_state(pdev);
21250- pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
21251- if (pAC->AllocFlag & SK_ALLOC_IRQ) {
21252- free_irq(dev->irq, dev);
21253- }
21254- pci_disable_device(pdev);
21255- pci_set_power_state(pdev, pci_choose_state(pdev, state));
21256-
21257- return 0;
21258-}
21259-
21260-static int skge_resume(struct pci_dev *pdev)
21261-{
21262- struct net_device *dev = pci_get_drvdata(pdev);
21263- DEV_NET *pNet = netdev_priv(dev);
21264- SK_AC *pAC = pNet->pAC;
21265- struct net_device *otherdev = pAC->dev[1];
21266- int ret;
21267-
21268- pci_set_power_state(pdev, PCI_D0);
21269- pci_restore_state(pdev);
21270- pci_enable_device(pdev);
21271- pci_set_master(pdev);
21272- if (pAC->GIni.GIMacsFound == 2)
21273- ret = request_irq(dev->irq, SkGeIsr, IRQF_SHARED, "sk98lin", dev);
21274- else
21275- ret = request_irq(dev->irq, SkGeIsrOnePort, IRQF_SHARED, "sk98lin", dev);
21276- if (ret) {
21277- printk(KERN_WARNING "sk98lin: unable to acquire IRQ %d\n", dev->irq);
21278- pAC->AllocFlag &= ~SK_ALLOC_IRQ;
21279- dev->irq = 0;
21280- pci_disable_device(pdev);
21281- return -EBUSY;
21282- }
21283-
21284- netif_device_attach(dev);
21285- if (netif_running(dev)) {
21286- DoPrintInterfaceChange = SK_FALSE;
21287- SkDrvInitAdapter(pAC, 0); /* first device */
21288- }
21289- if (otherdev != dev) {
21290- netif_device_attach(otherdev);
21291- if (netif_running(otherdev)) {
21292- DoPrintInterfaceChange = SK_FALSE;
21293- SkDrvInitAdapter(pAC, 1); /* second device */
21294- }
21295- }
21296-
21297- return 0;
21298-}
21299-#else
21300-#define skge_suspend NULL
21301-#define skge_resume NULL
21302-#endif
21303-
21304-static struct pci_device_id skge_pci_tbl[] = {
21305- { PCI_VENDOR_ID_3COM, 0x1700, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
21306- { PCI_VENDOR_ID_3COM, 0x80eb, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
21307- { PCI_VENDOR_ID_SYSKONNECT, 0x4300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
21308- { PCI_VENDOR_ID_SYSKONNECT, 0x4320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
21309-/* DLink card does not have valid VPD so this driver gags
21310- * { PCI_VENDOR_ID_DLINK, 0x4c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
21311- */
21312- { PCI_VENDOR_ID_MARVELL, 0x4320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
21313- { PCI_VENDOR_ID_MARVELL, 0x5005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
21314- { PCI_VENDOR_ID_CNET, 0x434e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
21315- { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
21316- { PCI_VENDOR_ID_LINKSYS, 0x1064, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
21317- { 0 }
21318-};
21319-
21320-MODULE_DEVICE_TABLE(pci, skge_pci_tbl);
21321-
21322-static struct pci_driver skge_driver = {
21323- .name = "sk98lin",
21324- .id_table = skge_pci_tbl,
21325- .probe = skge_probe_one,
21326- .remove = __devexit_p(skge_remove_one),
21327- .suspend = skge_suspend,
21328- .resume = skge_resume,
21329-};
21330-
21331-static int __init skge_init(void)
21332-{
638cbd52 21333- printk(KERN_NOTICE "sk98lin: driver has been replaced by the skge driver"
21334- " and is scheduled for removal\n");
21335-
a3b93527 21336- return pci_register_driver(&skge_driver);
21337-}
21338-
21339-static void __exit skge_exit(void)
21340-{
21341- pci_unregister_driver(&skge_driver);
21342-}
21343+/*******************************************************************************
21344+ *
21345+ * End of file
21346+ *
21347+ ******************************************************************************/
21348
21349-module_init(skge_init);
21350-module_exit(skge_exit);
21351diff -ruN linux/drivers/net/sk98lin/skgeasf.c linux-new/drivers/net/sk98lin/skgeasf.c
21352--- linux/drivers/net/sk98lin/skgeasf.c 1970-01-01 01:00:00.000000000 +0100
21353+++ linux-new/drivers/net/sk98lin/skgeasf.c 2006-10-13 11:18:48.000000000 +0200
21354@@ -0,0 +1,5434 @@
21355+/******************************************************************************
21356+ *
21357+ * Name: skgeasf.c
21358+ * Project: Gigabit Ethernet Adapters, Common Modules
21359+ * Version: $Revision$
21360+ * Date: $Date$
21361+ * Purpose: ASF Handler.
21362+ *
21363+ ******************************************************************************/
21364+
21365+/******************************************************************************
21366+ *
21367+ * (C)Copyright 1998-2002 SysKonnect GmbH.
21368+ * (C)Copyright 2002-2003 Marvell.
21369+ *
21370+ * This program is free software; you can redistribute it and/or modify
21371+ * it under the terms of the GNU General Public License as published by
21372+ * the Free Software Foundation; either version 2 of the License, or
21373+ * (at your option) any later version.
21374+ *
21375+ * The information in this file is provided "AS IS" without warranty.
21376+ *
21377+ ******************************************************************************/
21378+
21379+/******************************************************************************
21380+ *
21381+ * Description:
21382+ *
21383+ * This module is intended to handle all the asf functions
21384+ *
21385+ * Include File Hierarchy:
21386+ *
21387+ * "h/skdrv1st.h"
21388+ * "h/skdrv2nd.h"
21389+ *
21390+ ******************************************************************************/
21391+
21392+/*
21393+ Event queue and dispatcher
21394+*/
21395+#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
21396+static const char SysKonnectFileId[] =
21397+"$Header$" ;
21398+#endif
21399+
21400+#define __SKASF_C
21401+
21402+#ifdef __cplusplus
21403+extern "C" {
21404+#endif /* cplusplus */
21405+
21406+
21407+// #include <ntddk.h>
21408+// #include <wdm.h>
21409+
21410+
21411+#include "h/sktypes.h"
21412+#include "h/skdrv1st.h"
21413+#include "h/skdrv2nd.h"
21414+#include "h/skgeasf.h"
21415+#include "h/skgespi.h"
21416+#include "h/skfops.h"
21417+#include <acpi/acpi.h>
21418+
21419+//#include "h/yuk.h"
21420+//#include "h/skvpd.h"
21421+
21422+//#include <stdlib.h>
21423+
21424+static char *AsfFileName = "/etc/sk98lin/AcpiAsf.bin";
21425+static char *IpmiFileNameS1 = "/etc/sk98lin/ipmiyk2-s1.bin";
21426+static char *IpmiFileNameS2 = "/etc/sk98lin/ipmiyk2-s2.bin";
21427+// static char *SimuAsfTab = "/etc/sk98lin/AcpiAsf.bin";
21428+
21429+// ARP pattern 40 byte (5 bytes in mask)
21430+// this pattern length corresponds with YLCI_MACRXFIFOTHRES
21431+// Pattern mask for ARP Frames
21432+#ifdef ASF_ONLY_ARP_REQUEST
21433+static SK_U8 ARP_FRAME_PATTERN[] =
21434+{
21435+ /* MAC Header - 14 bytes */
21436+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*Dest MAC Addr */
21437+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*Src MAC Addr */
21438+ 0x08, 0x06, /*Frame Type */
21439+ /* ARP Header - 28 bytes */
21440+ 0x00, 0x01, /* hard type */
21441+ 0x08, 0x00, /* prot type */
21442+ 0x06, /* hard size */
21443+ 0x04, /* prot size */
21444+ 0x00, 0x01, /* op = request */
21445+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* senders mac */
21446+ 0x00, 0x00, 0x00, 0x00, /* senders ip */
21447+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* target mac */
21448+ 0x00, 0x00};
21449+static SK_U8 ARP_PATTERN_MASK[] = { 0x00, 0xF0, 0x3F, 0x00, 0x00 };
21450+#else
21451+static SK_U8 ARP_FRAME_PATTERN[] =
21452+{
21453+ /* MAC Header - 14 bytes */
21454+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*Dest MAC Addr */
21455+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*Src MAC Addr */
21456+ 0x08, 0x06, /*Frame Type */
21457+ /* ARP Header - 28 bytes */
21458+ 0x00, 0x01, /* hard type */
21459+ 0x08, 0x00, /* prot type */
21460+ 0x06, /* hard size */
21461+ 0x04, /* prot size */
21462+ 0x00, 0x00, /* op = request */
21463+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* senders mac */
21464+ 0x00, 0x00, 0x00, 0x00, /* senders ip */
21465+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* target mac */
21466+ 0x00, 0x00};
21467+static SK_U8 ARP_PATTERN_MASK[] = { 0x00, 0xF0, 0x00, 0x00, 0x00 };
21468+#endif
21469+
21470+// RSP pattern - 40 bytes (this makes 5 bytes in RSP_PATTERN_MASK)
21471+// this pattern length corresponds with YLCI_MACRXFIFOTHRES
21472+static SK_U8 RSP_FRAME_PATTERN[] =
21473+{ /* MAC Header (14 bytes) */
21474+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*Dest MAC Addr*/
21475+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*Src MAC Addr */
21476+ 0x08, 0x00, /*Frame Type */
21477+ /* IP Header (20 bytes) */
21478+ 0x45, 0x00, 0x00, 0x00, /* Version & Header Length */
21479+ 0x00, 0x00, 0x00, 0x00,
21480+ 0x00, 0x11, 0x00, 0x00, /* Protocol */
21481+ 0x00, 0x00, 0x00, 0x00, /*Src IP address*/
21482+ 0x00, 0x00, 0x00, 0x00, /*My IP address*/
21483+ /* part of UDP Header (6 bytes) */
21484+ 0x00, 0x00, /* src port */
21485+ 0x02, 0x98, /* dest. port */
21486+ 0x00, 0x00}; /* length */
21487+
21488+// Pattern mask for RSP Frames
21489+static SK_U8 RSP_PATTERN_MASK[] = { 0x00, 0x70, 0x80, 0x00, 0x30 };
21490+
21491+// RMCP pattern (unsecure port)
21492+// this pattern length corresponds with YLCI_MACRXFIFOTHRES
21493+static SK_U8 RMCP_FRAME_PATTERN[] =
21494+{ /* MAC Header */
21495+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*Dest MAC Addr*/
21496+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /*Src MAC Addr */
21497+ 0x08, 0x00, /*Frame Type */
21498+ /* IP Header */
21499+ 0x45, 0x00, 0x00, 0x00, /* Version & Header Length */
21500+ 0x00, 0x00, 0x00, 0x00,
21501+ 0x00, 0x11, 0x00, 0x00, /* Protocol */
21502+ 0x00, 0x00, 0x00, 0x00, /*Src IP address*/
21503+ 0x00, 0x00, 0x00, 0x00, /*My IP address*/
21504+ /* UDP Header */
21505+ 0x00, 0x00, /* src port */
21506+ 0x02, 0x6f, /* unsecure dest. port */
21507+ 0x00, 0x00};
21508+
21509+// Pattern mask for RMCP Frames
21510+static SK_U8 RMCP_PATTERN_MASK[] = { 0x00, 0x70, 0x80, 0x00, 0x30 };
21511+
21512+
21513+/*****************************************************************************
21514+*
21515+* SkAsfRestorePattern - interface function (global symbol)
21516+*
21517+* Description:
21518+* restores pattern for ASF and IPMI
21519+*
21520+* Returns:
21521+* Always 0
21522+*/
21523+
21524+int SkAsfRestorePattern (
21525+ SK_AC *pAC , /* Pointer to adapter context */
21526+ SK_IOC IoC) /* IO context handle */
21527+{
21528+ if (pAC->AsfData.OpMode == SK_GEASF_MODE_ASF) {
21529+
21530+ // asf mode -> we are running on
21531+ // yukon ec with only one port
21532+ AsfSetUpPattern(pAC, IoC, 0);
21533+
21534+ } else {
21535+ if (pAC->AsfData.OpMode == SK_GEASF_MODE_IPMI) {
21536+ // ipmi mode -> we are running on
21537+ // yukon 2 with at least one port
21538+ AsfSetUpPattern(pAC, IoC, 0); // port A
21539+
21540+ if (pAC->AsfData.DualMode == SK_GEASF_Y2_DUALPORT) {
21541+ AsfSetUpPattern(pAC, IoC, 1); // port B
21542+ }
21543+ }
21544+ }
21545+
21546+ return (SK_ASF_PNMI_ERR_OK);
21547+}
21548+
21549+/*****************************************************************************
21550+*
21551+* SkAsfInit - Init function of ASF
21552+*
21553+* Description:
21554+* SK_INIT_DATA: Initialises the data structures
21555+* SK_INIT_IO: Resets the XMAC statistics, determines the device and
21556+* connector type.
21557+* SK_INIT_RUN: Starts a timer event for port switch per hour
21558+* calculation.
21559+*
21560+* Returns:
21561+* Always 0
21562+*/
21563+int SkAsfInit(
21564+ SK_AC *pAC, /* Pointer to adapter context */
21565+ SK_IOC IoC, /* IO context handle */
21566+ int Level) /* Initialization level */
21567+{
21568+ SK_U32 TmpVal32;
21569+ SK_U32 FlashOffset = 0;
21570+ SK_U32 i;
21571+
21572+ SK_U32 FileLengthS1;
21573+ SK_U32 FileLengthS2;
21574+ char *FwFileNameS1 = NULL;
21575+ char *FwFileNameS2 = NULL;
21576+ SK_U8 *pAsfFwS1 = NULL;
21577+ SK_U8 *pAsfFwS2 = NULL;
21578+
21579+ SK_U8 FlashOk;
21580+ int RetCode;
21581+ SK_BOOL DoUpdate = SK_FALSE;
21582+ SK_U8 lRetCode;
21583+ SK_U32 FwImageCsOk;
21584+ SK_U32 FwFlashCsOk;
21585+ SK_U32 FwImageCs = 0;
21586+ SK_U32 FwFlashCs = 0;
21587+ SK_U32 FwCs;
21588+ SK_U32 *pTmp32;
21589+ SK_U8 *pHciRecBuf;
21590+ SK_EVPARA EventParam; /* Event struct for timer event */
21591+ unsigned long FlashSize;
21592+ unsigned long EraseOff = 0;
21593+ SK_U32 SpiRetVal;
21594+ SK_U8 Tmp1Val8, Tmp2Val8;
21595+ SK_BOOL YukonEcA1;
21596+ SK_U8 OldGuid[16];
21597+ SK_U8 AsfFlag = 0, IpmiFlag = 0;
21598+ SK_U8 AsfHintBit = 0, IpmiHintBit = 0, NoHintBit = 0;
21599+
21600+ RetCode = SK_ASF_PNMI_ERR_OK;
21601+
21602+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,
21603+ ("ASF: SkAsfInit: Called, level=%d sizof ASF-MIB:0x%x Bytes\n", Level, sizeof(STR_ASF_MIB) ) );
21604+
21605+ /* YukonEcA1 introduced by rschmidt */
21606+ YukonEcA1 = (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC && pAC->GIni.GIChipRev == CHIP_REV_YU_EC_A1);
21607+
21608+ switch(Level)
21609+ {
21610+ case SK_INIT_DATA:
21611+ /* Set structure to zero */
21612+ // This will be done in function "AsfReadConfiguration"
21613+ // SK_MEMSET((char *)&pAC->AsfData, 0, sizeof(pAC->AsfData));
21614+
21615+ pAC->AsfData.ActivePort = 0;
21616+ pAC->AsfData.OpMode = SK_GEASF_MODE_IPMI;
21617+ pAC->AsfData.ChipMode = SK_GEASF_CHIP_UNKNOWN;
21618+
21619+ pAC->AsfData.InitState = ASF_INIT_UNDEFINED;
21620+ break;
21621+
21622+ case SK_INIT_IO:
21623+ /* Set OS Present Flag in ASF Status and Command Register */
21624+#if (0)
21625+ SK_IN32( IoC, REG_ASF_STATUS_CMD, &TmpVal32 );
21626+ TmpVal32 |= BIT_4;
21627+ SK_OUT32( IoC, REG_ASF_STATUS_CMD, TmpVal32 );
21628+#endif
21629+
21630+#ifdef ASF_CHECK_HIDDEN_ID // here we will check hidden id _and_ chip id
21631+
21632+ /* check chip id */
21633+ SK_IN8( IoC, B2_CHIP_ID, &Tmp1Val8 );
21634+ switch(Tmp1Val8)
21635+ {
21636+ case CHIP_ID_YUKON_EC:
21637+ /* YUKON_EC */
21638+ /* chip-id is ok, check hidden id */
21639+ SK_IN8( IoC, B2_MAC_CFG, &Tmp2Val8 );
21640+ Tmp2Val8 &= 0x03;
21641+ if( (Tmp2Val8 != 1) && // 88E8052
21642+ (Tmp2Val8 != 3) ) { // 88E8050
21643+ RetCode = SK_ASF_PNMI_ERR_GENERAL;
21644+ } else {
21645+ pAC->AsfData.ChipMode = SK_GEASF_CHIP_EC;
21646+ }
21647+ break;
21648+ case CHIP_ID_YUKON_XL:
21649+ /* YUKON_2 */
21650+ /* chip-id is ok, check hidden id */
21651+ SK_IN8( IoC, B2_MAC_CFG, &Tmp2Val8 );
21652+ Tmp2Val8 &= 0x03;
21653+ if(Tmp2Val8 != 0) {
21654+ RetCode = SK_ASF_PNMI_ERR_GENERAL;
21655+ } else {
21656+ pAC->AsfData.ChipMode = SK_GEASF_CHIP_Y2;
21657+ }
21658+ break;
21659+ default:
21660+ /* Nothing to do. Chip id does not match */
21661+ RetCode = SK_ASF_PNMI_ERR_GENERAL;
21662+ break;
21663+ }
21664+
21665+ if (RetCode != SK_ASF_PNMI_ERR_OK) {
21666+
21667+ pAC->AsfData.InitState = ASF_INIT_ERROR_CHIP_ID;
21668+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, ("SkAsfInit: *** ASF/IPMI NOT SUPPORTED ***\n"));
21669+
21670+ /* hidden ID doesn't match (which card do we access?)
21671+ // do not set any registers
21672+
21673+ AsfDisable(pAC, IoC);
21674+
21675+ AsfResetCpu(IoC); // reset cpu
21676+
21677+ // disable all pattern for asf/ipmi
21678+ YlciDisablePattern(pAC, IoC, 0, 4);
21679+ YlciDisablePattern(pAC, IoC, 0, 5);
21680+ YlciDisablePattern(pAC, IoC, 0, 6);
21681+
21682+ if ( (CHIP_ID_YUKON_2(pAC)) && (pAC->GIni.GIMacsFound == 2) ) {
21683+ // do not forget the second link
21684+ // disable all pattern for asf/ipmi
21685+ YlciDisablePattern(pAC, IoC, 1, 4);
21686+ YlciDisablePattern(pAC, IoC, 1, 5);
21687+ YlciDisablePattern(pAC, IoC, 1, 6);
21688+ }
21689+ */
21690+ break;
21691+ }
21692+
21693+#endif
21694+ /* CHECK the ASF hint bits...
21695+ * all YukonII:
21696+ * Application Information Register auf 0x011e, Bit 7:6
21697+ *
21698+ * Kodierung:
21699+ * 0b00 kein "hint"; jetziger Zustand
21700+ * 0b01 customer wants ASF to be loaded
21701+ * 0b10 customer wants IPMI to be loaded
21702+ * 0b11 customer does not want ASF or IPMI to go in here
21703+ *
21704+ * Alle bisherigen EEPROM Versionen bringen 0b00.
21705+ */
21706+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, ("SkAsfInit: *** CHECK ASF hint bits ***\n"));
21707+ SK_IN32(IoC, B2_Y2_HW_RES, &TmpVal32);
21708+ switch(TmpVal32 & 0xc0) {
21709+ case 0xc0:
21710+ AsfHintBit = 0;
21711+ IpmiHintBit = 0;
21712+ NoHintBit = 1;
21713+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, ("SkAsfInit: *** ASF hint bits: NO ASF/IPMI ***\n"));
21714+ break;
21715+ case 0x40:
21716+ AsfHintBit = 1;
21717+ IpmiHintBit = 0;
21718+ NoHintBit = 0;
21719+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, ("SkAsfInit: *** ASF hint bits: ASF ***\n"));
21720+ break;
21721+ case 0x80:
21722+ AsfHintBit = 0;
21723+ IpmiHintBit = 1;
21724+ NoHintBit = 0;
21725+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, ("SkAsfInit: *** ASF hint bits: IPMI ***\n"));
21726+ break;
21727+ default:
21728+ AsfHintBit = 0;
21729+ IpmiHintBit = 0;
21730+ NoHintBit = 1;
21731+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, ("SkAsfInit: *** ASF hint bits: Default ASF/IPMI ***\n"));
21732+ break;
21733+ }
21734+
21735+ /* here we do not know which firmware we must load (ipmi or asf)... */
21736+ pAC->AsfData.OpMode = SK_GEASF_MODE_UNKNOWN;
21737+ AsfFlag = 0;
21738+ IpmiFlag = 0;
21739+
21740+ /* try to open the ASF binary */
21741+ if ( fw_file_exists(pAC, AsfFileName) ) {
21742+ /* here we have found the asf binary */
21743+
21744+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, ("SkAsfInit: *** ASF binary file found...\n"));
21745+ AsfFlag = 1;
21746+ FwFileNameS1 = AsfFileName;
21747+ FwFileNameS2 = NULL;
21748+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, ("*** AsfFlag = 1 ***\n"));
21749+ } else {
21750+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, ("SkAsfInit: *** ASF binary file _NOT_ found!\n"));
21751+ }
21752+
21753+ /* try to open IPMI binary */
21754+ if ( fw_file_exists(pAC, IpmiFileNameS1) &&
21755+ fw_file_exists(pAC, IpmiFileNameS2) ) {
21756+ /* here we have found the ipmi binary */
21757+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, ("SkAsfInit: *** IPMI binary file found...\n"));
21758+ IpmiFlag = 1;
21759+ FwFileNameS1 = IpmiFileNameS1;
21760+ FwFileNameS2 = IpmiFileNameS2;
21761+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, ("*** IpmiFlag = 1 ***\n"));
21762+ } else {
21763+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, ("SkAsfInit: *** IPMI binary file _NOT_ found!\n"));
21764+ }
21765+
21766+ /* set the operation mode */
21767+ if ( (AsfFlag == 1) && ( (AsfHintBit == 1) && (IpmiHintBit == 0) && (NoHintBit == 0) ) ) {
21768+ /* we are in the ASF mode */
21769+ if ( (pAC->AsfData.ChipMode == SK_GEASF_CHIP_EC) ||
21770+ (pAC->AsfData.ChipMode == SK_GEASF_CHIP_Y2) ) {
21771+ /* ASF can run on YukonEC and Yukon2 */
21772+ pAC->AsfData.OpMode = SK_GEASF_MODE_ASF;
21773+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, ("SkAsfInit: *** SK_GEASF_MODE_ASF ***\n"));
21774+ YlciDisablePattern(pAC, IoC, 0, 5); // Disable ARP pattern, OS is now responsible for ARP handling
21775+ }
21776+ } else {
21777+ /* are we in the ipmi mode ? */
21778+ if ( (IpmiFlag == 1) && ( (IpmiHintBit == 1) && (AsfHintBit == 0) && (NoHintBit == 0) ) ) {
21779+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, ("*** Ipmi bits OK - ChipMode: %x ***\n", pAC->AsfData.ChipMode));
21780+ if (pAC->AsfData.ChipMode == SK_GEASF_CHIP_Y2) {
21781+ /* IPMI can run only on Yukon2 */
21782+ pAC->AsfData.OpMode = SK_GEASF_MODE_IPMI;
21783+
21784+ /* set ASF enable bit in general register (0x0004)
21785+ * and set the AsfEnable byte in pAC structure
21786+ * (pAC->GIni.GIAsfEnabled = SK_TRUE)
21787+ */
21788+ AsfEnable(pAC, IoC);
21789+
21790+ /* check if we have a dual port adapter */
21791+ if ( (CHIP_ID_YUKON_2(pAC)) && (pAC->GIni.GIMacsFound == 2) ) {
21792+ pAC->AsfData.DualMode = SK_GEASF_Y2_DUALPORT;
21793+ } else {
21794+ pAC->AsfData.DualMode = SK_GEASF_Y2_SINGLEPORT;
21795+ }
21796+
21797+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,
21798+ ("SkAsfInit: *** SK_GEASF_MODE_IPMI (%d) ***\n", pAC->AsfData.DualMode));
21799+
21800+#if 0
21801+ /* Disable ARP pattern, OS is now responsible for ARP handling */
21802+ YlciDisablePattern(pAC, IoC, 0, 5);
21803+ // AsfSetUpPattern(pAC, IoC, 0);
21804+
21805+ if (pAC->AsfData.DualMode == SK_GEASF_Y2_DUALPORT) {
21806+ /* Disable ARP pattern, OS is now responsible for ARP handling */
21807+ YlciDisablePattern(pAC, IoC, 1, 5);
21808+ // AsfSetUpPattern(pAC, IoC, 1);
21809+ }
21810+#endif
21811+ }
21812+ }
21813+ }
21814+
21815+ if (pAC->AsfData.OpMode == SK_GEASF_MODE_UNKNOWN) {
21816+ if( (pAC->AsfData.ChipMode == SK_GEASF_CHIP_EC) && (AsfFlag == 1) && (NoHintBit == 1) ) {
21817+ /* ASF can run on YukonEC without hint bits */
21818+ pAC->AsfData.OpMode = SK_GEASF_MODE_ASF;
21819+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, ("SkAsfInit: *** SK_GEASF_MODE_ASF EC ***\n"));
21820+ YlciDisablePattern(pAC, IoC, 0, 5); // Disable ARP pattern, OS is now responsible for ARP handling
21821+ } else {
21822+ /* error - we could not find our operation mode! */
21823+ pAC->AsfData.InitState = ASF_INIT_ERROR_OPMODE;
21824+ RetCode = SK_ASF_PNMI_ERR_GENERAL;
21825+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL, ("SkAsfInit: *** ASF/IPMI UNKNOWN OPMODE ***\n"));
21826+
21827+ AsfDisable(pAC, IoC); // disable pattern matching for ASF/IPMI
21828+
21829+ AsfResetCpu(IoC); // reset cpu
21830+
21831+ /* disable all pattern for asf/ipmi */
21832+ YlciDisablePattern(pAC, IoC, 0, 4);
21833+ YlciDisablePattern(pAC, IoC, 0, 5);
21834+ YlciDisablePattern(pAC, IoC, 0, 6);
21835+
21836+ if ( (CHIP_ID_YUKON_2(pAC)) && (pAC->GIni.GIMacsFound == 2) ) {
21837+ /* do not forget the second link
21838+ * disable all pattern for asf/ipmi
21839+ */
21840+ YlciDisablePattern(pAC, IoC, 1, 4);
21841+ YlciDisablePattern(pAC, IoC, 1, 5);
21842+ YlciDisablePattern(pAC, IoC, 1, 6);
21843+ }
21844+ break; // leave "case SK_INIT_IO"
21845+ }
21846+ }
21847+
21848+ /* Send CheckAlive command to CPU */
21849+ if ( ((pAC->AsfData.OpMode == SK_GEASF_MODE_ASF) ||
21850+ (pAC->AsfData.OpMode == SK_GEASF_MODE_IPMI)) &&
21851+ (RetCode == SK_ASF_PNMI_ERR_OK) ) {
21852+
21853+ if( AsfCheckAliveCpu( pAC, IoC ) != 1 ) { // Not alive
21854+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,(" ******************************\n"));
21855+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("SkAsfInit: * CPU is NOT running ! *\n"));
21856+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,(" ******************************\n"));
21857+ pAC->AsfData.CpuAlive = 0;
21858+ } else {
21859+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,(" ******************************\n"));
21860+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,("SkAsfInit: * CPU is running *\n"));
21861+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,(" ******************************\n"));
21862+ pAC->AsfData.CpuAlive = 1;
21863+ }
21864+ }
21865+
21866+ /* START FLASH PROC */
21867+ /* Try to open the FW image file */
21868+ if (fw_read(pAC,FwFileNameS1,&pAsfFwS1,&FileLengthS1) &&
21869+ fw_read(pAC,FwFileNameS2,&pAsfFwS2,&FileLengthS2)) {
21870+ /* Set the flash offset to 128k */
21871+
21872+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,(" Flash files opened:\n"));
21873+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,(" %s: size: 0x%d offs:0x%x\n", FwFileNameS1, FileLengthS1, FlashOffset));
21874+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,(" %s: size: 0x%d offs:0x%x\n", FwFileNameS2, FileLengthS2, FlashOffset));
21875+
21876+ /* calculate CS of the FW image */
21877+ pTmp32 = (SK_U32 *) pAsfFwS1;
21878+ for( i=0, FwCs=0; i<ASF_FLASH_SIZE; i+=4 ) {
21879+ FwCs += *pTmp32;
21880+ pTmp32++;
21881+ }
21882+
21883+ pTmp32 = (SK_U32 *) pAsfFwS2;
21884+ for( i=0; i<ASF_FLASH_SIZE; i+=4 ) {
21885+ FwCs += *pTmp32;
21886+ pTmp32++;
21887+ }
21888+
21889+
21890+ if( FwCs == 0 ) { // CS == 0 => O.K.
21891+ FwImageCsOk = 1;
21892+ FwImageCs = *(pTmp32 - 1);
21893+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,(" FW Image Checksum O.K. \n"));
21894+ } else {
21895+ FwImageCsOk = 0;
21896+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,(" *** Error: FW Image Checksum:0x%x\n", FwCs));
21897+ }
21898+
21899+ pAC->AsfData.DriverVersion[0] = 'v';
21900+ pAC->AsfData.DriverVersion[1] = '1';
21901+ pAC->AsfData.DriverVersion[2] = '.';
21902+ pAC->AsfData.DriverVersion[3] = '1';
21903+ pAC->AsfData.DriverVersion[4] = '0';
21904+
21905+ for( i=0; i<5; i++ )
21906+ pAC->AsfData.FileFwVersion[i] = *(pAsfFwS2 + ASF_FLASH_OFFS_VER - 65536 + i);
21907+
21908+ pAC->AsfData.FileFwRev = *(pAsfFwS2 + ASF_FLASH_OFFS_REV - 65536);
21909+
21910+ SK_DBG_MSG(pAC, SK_DBGMOD_ASF, SK_DBGCAT_CTRL,(" FW Image:%c%c%c%c %c Driver:%c%c%c%c\n",
21911+ pAC->AsfData.FileFwVersion[1], pAC->AsfData.FileFwVersion[2],
21912+ pAC->AsfData.FileFwVersion[3], pAC->AsfData.FileFwVersion[4],
21913+ pAC->AsfData.FileFwRev,
21914+ pAC->AsfData.DriverVersion[1], pAC->AsfData.DriverVersion[2],
21915+ pAC->AsfData.DriverVersion[3], pAC->AsfData.DriverVersion[4] ));
21916+
21917+
21918+ /* check, whether the FW file version suits the driver version */
21919+ if( (pAC->AsfData.FileFwVersion[1] == pAC->AsfData.DriverVersion[1]) &&
21920+ (pAC->AsfData.FileFwVersion[3] == pAC->AsfData.DriverVersion[3]) &&
21921+ (pAC->AsfData.FileFwVersion[4] == pAC->AsfData.DriverVersion[4]) &&
21922+ (FwImageCsOk == 1) ) {
21923+
21924+ /* read the flash (upper 128k) */
21925