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581ca497 1diff -urN linux-2.6.17.orig/Documentation/networking/sk98lin.txt linux-2.6.17/Documentation/networking/sk98lin.txt
2--- linux-2.6.17.orig/Documentation/networking/sk98lin.txt 2006-06-22 13:17:15.000000000 +0200
3+++ linux-2.6.17/Documentation/networking/sk98lin.txt 2006-04-27 11:43:44.000000000 +0200
4@@ -1,38 +1,56 @@
5-(C)Copyright 1999-2004 Marvell(R).
6-All rights reserved
7-===========================================================================
8+(C)Copyright 1999-2006 Marvell(R).
9+All rights reserved.
10+================================================================================
11
12-sk98lin.txt created 13-Feb-2004
13+sk98lin.txt created 27-Apr-2006
14
15-Readme File for sk98lin v6.23
16-Marvell Yukon/SysKonnect SK-98xx Gigabit Ethernet Adapter family driver for LINUX
17+Readme File for sk98lin v8.32.2.3
18+Marvell Yukon/SysKonnect SK-98xx Gigabit Ethernet Adapter driver for LINUX
19
20 This file contains
21 1 Overview
22- 2 Required Files
23- 3 Installation
24- 3.1 Driver Installation
25- 3.2 Inclusion of adapter at system start
26- 4 Driver Parameters
27- 4.1 Per-Port Parameters
28- 4.2 Adapter Parameters
29- 5 Large Frame Support
30- 6 VLAN and Link Aggregation Support (IEEE 802.1, 802.1q, 802.3ad)
31- 7 Troubleshooting
32+ 2 Supported Functions
33+ 3 Required Files
34+ 4 Installation
35+ 4.1 Driver Installation
36+ 4.2 Inclusion of adapter at system start
37+ 5 Driver Parameters
38+ 5.1 Per-Port Parameters
39+ 5.2 Adapter Parameters
40+ 6 Ethtool Support
41+ 7 Large Frame Support
42+ 8 VLAN and Link Aggregation Support (IEEE 802.1, 802.1q, 802.3ad)
43+ 9 Wake on Lan support
44+10 Troubleshooting
45
46-===========================================================================
47+================================================================================
48
49
50 1 Overview
51 ===========
52
53-The sk98lin driver supports the Marvell Yukon and SysKonnect
54-SK-98xx/SK-95xx compliant Gigabit Ethernet Adapter on Linux. It has
55-been tested with Linux on Intel/x86 machines.
56+The sk98lin driver supports the Marvell Yukon, Yukon EC/FE, Yukon 2
57+and SysKonnect SK-98xx/SK-95xx compliant Gigabit Ethernet Adapter on Linux.
58+It has been tested with Linux on Intel/x86, x86_64 and IA64 machines.
59 ***
60
61+2 Supported Functions
62+======================
63+
64+The following functions are supported by the driver:
65
66-2 Required Files
67+ NOTE 1: The hardware support depends on the used card
68+
69+ - RX/TX HW Checksum
70+ - Hardware interrupt moderation (static/dynamic)
71+ - Transmit poll
72+ - Zerocopy/Scatter-Gather
73+ - Ethtool support
74+ - Wake on Lan (Magic Packet only) (From suspend and APM only)
75+ - DualNet
76+
77+
78+3 Required Files
79 =================
80
81 The linux kernel source.
82@@ -40,16 +58,14 @@
83 ***
84
85
86-3 Installation
87+4 Installation
88 ===============
89
90 It is recommended to download the latest version of the driver from the
91-SysKonnect web site www.syskonnect.com. If you have downloaded the latest
92-driver, the Linux kernel has to be patched before the driver can be
93-installed. For details on how to patch a Linux kernel, refer to the
94-patch.txt file.
95+SysKonnect web site www.syskonnect.com. For details on Installation
96+Instructions for sk98lin Driver, please refer to the README.txt file.
97
98-3.1 Driver Installation
99+4.1 Driver Installation
100 ------------------------
101
102 The following steps describe the actions that are required to install
103@@ -91,7 +107,7 @@
104 with (M)
105 5. Execute the command "make modules".
106 6. Execute the command "make modules_install".
107- The appropriate modules will be installed.
108+ The appropiate modules will be installed.
109 7. Reboot your system.
110
111
112@@ -110,13 +126,13 @@
113
114 NOTE 1: If you have more than one Marvell Yukon or SysKonnect SK-98xx
115 adapter installed, the adapters will be listed as 'eth0',
116- 'eth1', 'eth2', etc.
117- For each adapter, repeat steps 3 and 4 below.
118+ 'eth1', 'eth2', etc.
119+ For each adapter, repeat steps 3 and 4 below.
120
121 NOTE 2: If you have other Ethernet adapters installed, your Marvell
122 Yukon or SysKonnect SK-98xx adapter will be mapped to the
123- next available number, e.g. 'eth1'. The mapping is executed
124- automatically.
125+ next available number, e.g. 'eth1'. The mapping is executed
126+ automatically.
127 The module installation message (displayed either in a system
128 log file or on the console) prints a line for each adapter
129 found containing the corresponding 'ethX'.
130@@ -153,7 +169,7 @@
131 1. Execute the command "ifconfig eth0 down".
132 2. Execute the command "rmmod sk98lin".
133
134-3.2 Inclusion of adapter at system start
135+4.2 Inclusion of adapter at system start
136 -----------------------------------------
137
138 Since a large number of different Linux distributions are
139@@ -165,7 +181,8 @@
140
141 ***
142
143-4 Driver Parameters
144+
145+5 Driver Parameters
146 ====================
147
148 Parameters can be set at the command line after the module has been
149@@ -174,7 +191,7 @@
150 to the driver module.
151
152 If you use the kernel module loader, you can set driver parameters
153-in the file /etc/modprobe.conf (or /etc/modules.conf in 2.4 or earlier).
154+in the file /etc/modules.conf (or old name: /etc/conf.modules).
155 To set the driver parameters in this file, proceed as follows:
156
157 1. Insert a line of the form :
158@@ -208,7 +225,7 @@
159 more adapters, adjust this and recompile.
160
161
162-4.1 Per-Port Parameters
163+5.1 Per-Port Parameters
164 ------------------------
165
166 These settings are available for each port on the adapter.
167@@ -245,7 +262,7 @@
168 This parameters is only relevant if auto-negotiation for this port is
169 not set to "Sense". If auto-negotiation is set to "On", all three values
170 are possible. If it is set to "Off", only "Full" and "Half" are allowed.
171-This parameter is useful if your link partner does not support all
172+This parameter is usefull if your link partner does not support all
173 possible combinations.
174
175 Flow Control
176@@ -282,13 +299,13 @@
177 with this parameter.
178
179
180-4.2 Adapter Parameters
181+5.2 Adapter Parameters
182 -----------------------
183
184-Connection Type (SK-98xx V2.0 copper adapters only)
185+Connection Type (for copper adapters only)
186 ---------------
187 Parameter: ConType
188-Values: Auto, 100FD, 100HD, 10FD, 10HD
189+Values: Auto, 1000FD, 100FD, 100HD, 10FD, 10HD
190 Default: Auto
191
192 The parameter 'ConType' is a combination of all five per-port parameters
193@@ -302,6 +319,7 @@
194 ConType | DupCap AutoNeg FlowCtrl Role Speed
195 ----------+------------------------------------------------------
196 Auto | Both On SymOrRem Auto Auto
197+ 1000FD | Full Off None Auto (ignored) 1000
198 100FD | Full Off None Auto (ignored) 100
199 100HD | Half Off None Auto (ignored) 100
200 10FD | Full Off None Auto (ignored) 10
201@@ -379,7 +397,6 @@
202 is tremendous. On the other hand, selecting a very short moderation time might
203 compensate the use of any moderation being applied.
204
205-
206 Preferred Port
207 --------------
208 Parameter: PrefPort
209@@ -394,7 +411,7 @@
210 ------------------------------------------------
211 Parameter: RlmtMode
212 Values: CheckLinkState,CheckLocalPort, CheckSeg, DualNet
213-Default: CheckLinkState
214+Default: CheckLinkState (DualNet on dual port adapters)
215
216 RLMT monitors the status of the port. If the link of the active port
217 fails, RLMT switches immediately to the standby link. The virtual link is
218@@ -429,10 +446,94 @@
219 where a network path between the ports on one adapter exists.
220 Moreover, they are not designed to work where adapters are connected
221 back-to-back.
222+
223+LowLatency
224+----------
225+Parameter: LowLatency
226+Values: On, Off
227+Default: Off
228+
229+This is used to reduce the packet latency time of the adapter. Setting the
230+LowLatency parameter to 'On' forces the adapter to pass any received packet
231+immediately to upper network layers and to send out any transmit packet as
232+fast as possible.
233+
234+NOTE 1: The system load increases if LowLatency is set to 'On' and a lot
235+ of data packets are transmitted and received.
236+
237+NOTE 2: This parameter is only used on adapters which are based on
238+ PCI Express compatible chipsets.
239 ***
240
241
242-5 Large Frame Support
243+6 Ethtool Support
244+==================
245+
246+The sk98lin driver provides built-in ethtool support. The ethtool
247+can be used to display or modify interface specific configurations.
248+
249+Ethtool commands are invoked using a single parameter which reflects
250+the requested ethtool command plus an optional number of parameters
251+which belong to the desired command.
252+
253+It is not the intention of this section to explain the ethtool command
254+line tool and all its options. For further information refer to the
255+manpage of the ethtool. This sections describes only the sk98lin
256+driver supported ethtool commands.
257+
258+Pause Parameters
259+----------------
260+Query command: -a
261+Set command: -A [autoneg on|off] [rx on|off] [tx on|off]
262+Sample: ethtool -A eth0 rx off tx off
263+
264+Coalescing Parameters
265+---------------------
266+Query command: -c
267+Set command: -C [sample-interval I]
268+ [rx-usecs N] [tx-usecs N]
269+ [rx-usecs-low N] [tx-usecs-low N]
270+ [rx-usecs-high N] [tx-usecs-high N]
271+Parameter: I = Length of sample interval, in seconds
272+ (supported values range from 1...10)
273+ N = Length of coalescing interval, in microseconds
274+ (supported values range from 25...33,333)
275+Sample: ethtool -C eth2 rx-usecs 500 tx-usecs 500
276+
277+NOTE: The sk98lin driver does not support different settings
278+ for the rx and tx interrupt coalescing parameters.
279+
280+Driver Information
281+------------------
282+Query command: -i
283+Sample: ethtool -i eth1
284+
285+Checksumming Parameters
286+-----------------------
287+Query command: -k
288+Set command: -K [rx on|off] [tx on|off] [sg on|off]
289+Sample: ethtool -K eth0 sg off
290+
291+Locate NIC Command
292+------------------
293+Query command: -p [N]
294+Parameter: N = Amount of time to perform locate NIC command, in seconds
295+Sample: ethtool -p 10 eth1
296+
297+Driver-specific Statistics
298+--------------------------
299+Query command: -S
300+Sample: ethtool -S eth0
301+
302+Setting Parameters
303+------------------
304+Set command: -s [speed 10|100|1000] [duplex half|full]
305+ [autoneg on|off] [wol gd]
306+Sample: ethtool -s eth2 wol d
307+***
308+
309+
310+7 Large Frame Support
311 ======================
312
313 The driver supports large frames (also called jumbo frames). Using large
314@@ -444,10 +545,10 @@
315 ifconfig eth0 mtu 9000
316 This will only work if you have two adapters connected back-to-back
317 or if you use a switch that supports large frames. When using a switch,
318-it should be configured to allow large frames and auto-negotiation should
319-be set to OFF. The setting must be configured on all adapters that can be
320-reached by the large frames. If one adapter is not set to receive large
321-frames, it will simply drop them.
322+it should be configured to allow large frames. The setting must be
323+configured on all adapters that can be reached by the large frames.
324+If one adapter is not set to receive large frames, it will simply drop
325+them.
326
327 You can switch back to the standard ethernet frame size by executing the
328 following command:
329@@ -459,7 +560,7 @@
330 ***
331
332
333-6 VLAN and Link Aggregation Support (IEEE 802.1, 802.1q, 802.3ad)
334+8 VLAN and Link Aggregation Support (IEEE 802.1, 802.1q, 802.3ad)
335 ==================================================================
336
337 The Marvell Yukon/SysKonnect Linux drivers are able to support VLAN and
338@@ -477,8 +578,21 @@
339 cause problems when unloading the driver.
340
341
342-7 Troubleshooting
343-==================
344+9 Wake on Lan support
345+======================
346+
347+The sk98lin driver supports wake up from suspend mode with MagicPacket
348+on APM systems. Wake on Lan support is enabled by default. To disable it
349+please use the ethtool.
350+
351+NOTE 1: APM support has to be enabled in BIOS and in the kernel.
352+
353+NOTE 2: Refer to the kernel documentation for additional requirements
354+ regarding APM support.
355+
356+
357+10 Troubleshooting
358+===================
359
360 If any problems occur during the installation process, check the
361 following list:
362diff -urN linux-2.6.17.orig/drivers/net/Kconfig linux-2.6.17/drivers/net/Kconfig
363--- linux-2.6.17.orig/drivers/net/Kconfig 2006-06-22 13:17:16.000000000 +0200
364+++ linux-2.6.17/drivers/net/Kconfig 2006-06-22 13:21:21.000000000 +0200
365@@ -2182,17 +2182,26 @@
366 depends on PCI
367 ---help---
368 Say Y here if you have a Marvell Yukon or SysKonnect SK-98xx/SK-95xx
369- compliant Gigabit Ethernet Adapter.
370-
371- This driver supports the original Yukon chipset. A cleaner driver is
372- also available (skge) which seems to work better than this one.
373-
374- This driver does not support the newer Yukon2 chipset. A seperate
375- driver, sky2, is provided to support Yukon2-based adapters.
376-
377- The following adapters are supported by this driver:
378+ compliant Gigabit Ethernet Adapter. The following adapters are supported
379+ by this driver:
380 - 3Com 3C940 Gigabit LOM Ethernet Adapter
381 - 3Com 3C941 Gigabit LOM Ethernet Adapter
382+ - 88E8021 Marvell 1000 Mbit PCI-X, single Port Copper
383+ - 88E8021 Marvell 1000 Mbit PCI-X, single Port Fiber LX
384+ - 88E8021 Marvell 1000 Mbit PCI-X, single Port Fiber SX
385+ - 88E8022 Marvell 1000 Mbit PCI-X, dual Port Copper
386+ - 88E8022 Marvell 1000 Mbit PCI-X, dual Port Copper (Gateway)
387+ - 88E8022 Marvell 1000 Mbit PCI-X, dual Port Fiber LX
388+ - 88E8022 Marvell 1000 Mbit PCI-X, dual Port Fiber SX
389+ - 88E8061 Marvell 1000 Mbit PCI-E, single Port Copper
390+ - 88E8061 Marvell 1000 Mbit PCI-E, single Port Fiber LX
391+ - 88E8061 Marvell 1000 Mbit PCI-E, single Port Fiber SX
392+ - 88E8062 Marvell 1000 Mbit PCI-E, dual Port Copper
393+ - 88E8062 Marvell 1000 Mbit PCI-E, dual Port Copper (Gateway)
394+ - 88E8062 Marvell 1000 Mbit PCI-E, dual Port Fiber LX
395+ - 88E8062 Marvell 1000 Mbit PCI-E, dual Port Fiber SX
396+ - Abocom EFE3K - 10/100 Ethernet Expresscard
397+ - Abocom EGE5K - Giga Ethernet Expresscard
398 - Allied Telesyn AT-2970LX Gigabit Ethernet Adapter
399 - Allied Telesyn AT-2970LX/2SC Gigabit Ethernet Adapter
400 - Allied Telesyn AT-2970SX Gigabit Ethernet Adapter
401@@ -2202,31 +2211,83 @@
402 - Allied Telesyn AT-2971SX Gigabit Ethernet Adapter
403 - Allied Telesyn AT-2971T Gigabit Ethernet Adapter
404 - Belkin Gigabit Desktop Card 10/100/1000Base-T Adapter, Copper RJ-45
405+ - DGE-530T Gigabit Ethernet Adapter
406+ - DGE-560SX Single fiber Gigabit Ethernet Adapter
407+ - DGE-560T Gigabit Ethernet Adapter
408 - EG1032 v2 Instant Gigabit Network Adapter
409 - EG1064 v2 Instant Gigabit Network Adapter
410- - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Abit)
411- - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Albatron)
412- - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Asus)
413- - Marvell 88E8001 Gigabit LOM Ethernet Adapter (ECS)
414- - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Epox)
415- - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Foxconn)
416- - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Gigabyte)
417- - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Iwill)
418- - Marvell 88E8050 Gigabit LOM Ethernet Adapter (Intel)
419+ - Marvell 88E8001 Gigabit Ethernet Controller (Abit)
420+ - Marvell 88E8001 Gigabit Ethernet Controller (Albatron)
421+ - Marvell 88E8001 Gigabit Ethernet Controller (Asus)
422+ - Marvell 88E8001 Gigabit Ethernet Controller (Chaintech)
423+ - Marvell 88E8001 Gigabit Ethernet Controller (ECS)
424+ - Marvell 88E8001 Gigabit Ethernet Controller (Epox)
425+ - Marvell 88E8001 Gigabit Ethernet Controller (Foxconn)
426+ - Marvell 88E8001 Gigabit Ethernet Controller (Gigabyte)
427+ - Marvell 88E8001 Gigabit Ethernet Controller (Iwill)
428+ - Marvell 88E8035 Fast Ethernet Controller (LGE)
429+ - Marvell 88E8035 Fast Ethernet Controller (Toshiba)
430+ - Marvell 88E8036 Fast Ethernet Controller (Arima)
431+ - Marvell 88E8036 Fast Ethernet Controller (Compal)
432+ - Marvell 88E8036 Fast Ethernet Controller (Inventec)
433+ - Marvell 88E8036 Fast Ethernet Controller (LGE)
434+ - Marvell 88E8036 Fast Ethernet Controller (Mitac)
435+ - Marvell 88E8036 Fast Ethernet Controller (Panasonic)
436+ - Marvell 88E8036 Fast Ethernet Controller (Quanta)
437+ - Marvell 88E8036 Fast Ethernet Controller (Toshiba)
438+ - Marvell 88E8036 Fast Ethernet Controller (Wistron)
439+ - Marvell 88E8050 Gigabit Ethernet Controller (Gateway)
440+ - Marvell 88E8050 Gigabit Ethernet Controller (Intel)
441+ - Marvell 88E8052 Gigabit Ethernet Controller (ASRock)
442+ - Marvell 88E8052 Gigabit Ethernet Controller (Aopen)
443+ - Marvell 88E8052 Gigabit Ethernet Controller (Asus)
444+ - Marvell 88E8052 Gigabit Ethernet Controller (Gateway)
445+ - Marvell 88E8052 Gigabit Ethernet Controller (Gigabyte)
446+ - Marvell 88E8052 Gigabit Ethernet Controller (MSI)
447+ - Marvell 88E8052 Gigabit Ethernet Controller (Wistron)
448+ - Marvell 88E8053 Gigabit Ethernet Controller (ASRock)
449+ - Marvell 88E8053 Gigabit Ethernet Controller (Albatron)
450+ - Marvell 88E8053 Gigabit Ethernet Controller (Aopen)
451+ - Marvell 88E8053 Gigabit Ethernet Controller (Arima)
452+ - Marvell 88E8053 Gigabit Ethernet Controller (Asus)
453+ - Marvell 88E8053 Gigabit Ethernet Controller (Chaintech)
454+ - Marvell 88E8053 Gigabit Ethernet Controller (Clevo)
455+ - Marvell 88E8053 Gigabit Ethernet Controller (Compal)
456+ - Marvell 88E8053 Gigabit Ethernet Controller (DFI)
457+ - Marvell 88E8053 Gigabit Ethernet Controller (ECS)
458+ - Marvell 88E8053 Gigabit Ethernet Controller (Epox)
459+ - Marvell 88E8053 Gigabit Ethernet Controller (Gigabyte)
460+ - Marvell 88E8053 Gigabit Ethernet Controller (Inventec)
461+ - Marvell 88E8053 Gigabit Ethernet Controller (LGE)
462+ - Marvell 88E8053 Gigabit Ethernet Controller (MSI)
463+ - Marvell 88E8053 Gigabit Ethernet Controller (Mitac)
464+ - Marvell 88E8053 Gigabit Ethernet Controller (Panasonic)
465+ - Marvell 88E8053 Gigabit Ethernet Controller (Quanta)
466+ - Marvell 88E8053 Gigabit Ethernet Controller (SOYO)
467+ - Marvell 88E8053 Gigabit Ethernet Controller (Shuttle)
468+ - Marvell 88E8053 Gigabit Ethernet Controller (Toshiba)
469+ - Marvell 88E8053 Gigabit Ethernet Controller (Trigem)
470+ - Marvell RDK-8001
471 - Marvell RDK-8001 Adapter
472 - Marvell RDK-8002 Adapter
473+ - Marvell RDK-8003
474 - Marvell RDK-8003 Adapter
475 - Marvell RDK-8004 Adapter
476 - Marvell RDK-8006 Adapter
477 - Marvell RDK-8007 Adapter
478 - Marvell RDK-8008 Adapter
479 - Marvell RDK-8009 Adapter
480- - Marvell RDK-8010 Adapter
481+ - Marvell RDK-8010
482 - Marvell RDK-8011 Adapter
483 - Marvell RDK-8012 Adapter
484- - Marvell RDK-8052 Adapter
485- - Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Adapter (32 bit)
486- - Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Adapter (64 bit)
487+ - Marvell RDK-8035
488+ - Marvell RDK-8036
489+ - Marvell RDK-8052
490+ - Marvell RDK-8053
491+ - Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Controller (32 bit)
492+ - Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Controller (64 bit)
493+ - Marvell Yukon-EC Ultra, no ASF (Battery Power Service Support)
494+ - Marvell Yukon-FE Fast Ethernet, Reduced Battery Power Service Support)
495 - N-Way PCI-Bus Giga-Card 1000/100/10Mbps(L)
496 - SK-9521 10/100/1000Base-T Adapter
497 - SK-9521 V2.0 10/100/1000Base-T Adapter
498@@ -2246,21 +2307,36 @@
499 - SK-9871 Gigabit Ethernet Server Adapter (SK-NET GE-ZX)
500 - SK-9871 V2.0 Gigabit Ethernet 1000Base-ZX Adapter
501 - SK-9872 Gigabit Ethernet Server Adapter (SK-NET GE-ZX dual link)
502+ - SK-9S21 Server Adapter
503+ - SK-9S22 Server Adapter
504+ - SK-9S24 Server Adapter
505+ - SK-9S34 Server Adapter
506+ - SK-9S81 Server Adapter
507+ - SK-9S82 Server Adapter
508+ - SK-9S91 Server Adapter
509+ - SK-9S92 Server Adapter
510 - SMC EZ Card 1000 (SMC9452TXV.2)
511
512 The adapters support Jumbo Frames.
513 The dual link adapters support link-failover and dual port features.
514 Both Marvell Yukon and SysKonnect SK-98xx/SK-95xx adapters support
515 the scatter-gather functionality with sendfile(). Please refer to
516- <file:Documentation/networking/sk98lin.txt> for more information about
517+ Documentation/networking/sk98lin.txt for more information about
518 optional driver parameters.
519 Questions concerning this driver may be addressed to:
520- <linux@syskonnect.de>
521+ linux@syskonnect.de
522
523 If you want to compile this driver as a module ( = code which can be
524 inserted in and removed from the running kernel whenever you want),
525- say M here and read <file:Documentation/kbuild/modules.txt>. The module will
526- be called sk98lin. This is recommended.
527+ say M here and read Documentation/modules.txt. This is recommended.
528+ The module will be called sk98lin. This is recommended.
529+
530+config SK98LIN_NAPI
531+ bool "Use Rx polling (NAPI)"
532+ depends on SK98LIN
533+ help
534+ NAPI is a new driver API designed to reduce CPU and interrupt load
535+ when the driver is receiving lots of packets from the card.
536
537 config VIA_VELOCITY
538 tristate "VIA Velocity support"
539diff -urN linux-2.6.17.orig/drivers/net/sk98lin/Makefile linux-2.6.17/drivers/net/sk98lin/Makefile
540--- linux-2.6.17.orig/drivers/net/sk98lin/Makefile 2006-06-22 13:17:16.000000000 +0200
541+++ linux-2.6.17/drivers/net/sk98lin/Makefile 2006-04-27 11:43:45.000000000 +0200
542@@ -1,6 +1,59 @@
543+#******************************************************************************
544 #
545-# Makefile for the SysKonnect SK-98xx device driver.
546+# Name: skge.c
547+# Project: GEnesis, PCI Gigabit Ethernet Adapter
548+# Version: $Revision$
549+# Date: $Date$
550+# Purpose: The main driver source module
551 #
552+#******************************************************************************
553+
554+#******************************************************************************
555+#
556+# (C)Copyright 1998-2002 SysKonnect GmbH.
557+# (C)Copyright 2002-2005 Marvell.
558+#
559+# Makefile for Marvell Yukon chipset and SysKonnect Gigabit Ethernet
560+# Server Adapter driver. (Kernel 2.6)
561+#
562+# Author: Mirko Lindner (mlindner@syskonnect.de)
563+# Ralph Roesler (rroesler@syskonnect.de)
564+#
565+# Address all question to: linux@syskonnect.de
566+#
567+# This program is free software; you can redistribute it and/or modify
568+# it under the terms of the GNU General Public License as published by
569+# the Free Software Foundation; either version 2 of the License, or
570+# (at your option) any later version.
571+#
572+# The information in this file is provided "AS IS" without warranty.
573+#
574+#******************************************************************************
575+
576+#******************************************************************************
577+#
578+# History:
579+#
580+# $Log$
581+# Revision 1.9.2.1 2005/04/11 09:01:18 mlindner
582+# Fix: Copyright year changed
583+#
584+# Revision 1.9 2004/07/13 15:54:50 rroesler
585+# Add: file skethtool.c
586+# Fix: corrected header regarding copyright
587+# Fix: minor typos corrected
588+#
589+# Revision 1.8 2004/06/08 08:39:38 mlindner
590+# Fix: Add CONFIG_SK98LIN_ZEROCOPY as default
591+#
592+# Revision 1.7 2004/06/03 16:06:56 mlindner
593+# Fix: Added compile flag SK_DIAG_SUPPORT
594+#
595+# Revision 1.6 2004/06/02 08:02:59 mlindner
596+# Add: Changed header information and inserted a GPL statement
597+#
598+#
599+#******************************************************************************
600
601
602 #
603@@ -13,20 +66,24 @@
604 obj-$(CONFIG_SK98LIN) += sk98lin.o
605 sk98lin-objs := \
606 skge.o \
607+ sky2.o \
608 skethtool.o \
609+ sky2le.o \
610 skdim.o \
611 skaddr.o \
612 skgehwt.o \
613 skgeinit.o \
614 skgepnmi.o \
615 skgesirq.o \
616- ski2c.o \
617+ sktwsi.o \
618 sklm80.o \
619 skqueue.o \
620 skrlmt.o \
621 sktimer.o \
622 skvpd.o \
623- skxmac2.o
624+ skxmac2.o \
625+ skproc.o \
626+ skcsum.o
627
628 # DBGDEF = \
629 # -DDEBUG
630@@ -75,13 +132,11 @@
631 # SK_DBGCAT_DRV_INT_SRC 0x04000000 interrupts sources
632 # SK_DBGCAT_DRV_EVENT 0x08000000 driver events
633
634-EXTRA_CFLAGS += -Idrivers/net/sk98lin -DSK_DIAG_SUPPORT -DGENESIS -DYUKON $(DBGDEF) $(SKPARAM)
635+EXTRA_CFLAGS += -Idrivers/net/sk98lin -DSK_USE_CSUM -DSK_DIAG_SUPPORT \
636+ -DGENESIS -DYUKON -DYUK2 -DCONFIG_SK98LIN_ZEROCOPY \
637+ $(DBGDEF) $(SKPARAM)
638
639 clean:
640 rm -f core *.o *.a *.s
641
642
643-
644-
645-
646-
647diff -urN linux-2.6.17.orig/drivers/net/sk98lin/h/lm80.h linux-2.6.17/drivers/net/sk98lin/h/lm80.h
648--- linux-2.6.17.orig/drivers/net/sk98lin/h/lm80.h 2006-06-22 13:17:16.000000000 +0200
649+++ linux-2.6.17/drivers/net/sk98lin/h/lm80.h 2006-04-27 11:43:44.000000000 +0200
650@@ -2,8 +2,8 @@
651 *
652 * Name: lm80.h
653 * Project: Gigabit Ethernet Adapters, Common Modules
654- * Version: $Revision$
655- * Date: $Date$
656+ * Version: $Revision$
657+ * Date: $Date$
658 * Purpose: Contains all defines for the LM80 Chip
659 * (National Semiconductor).
660 *
661@@ -11,6 +11,7 @@
662
663 /******************************************************************************
664 *
665+ * LICENSE:
666 * (C)Copyright 1998-2002 SysKonnect.
667 * (C)Copyright 2002-2003 Marvell.
668 *
669@@ -20,6 +21,7 @@
670 * (at your option) any later version.
671 *
672 * The information in this file is provided "AS IS" without warranty.
673+ * /LICENSE
674 *
675 ******************************************************************************/
676
677diff -urN linux-2.6.17.orig/drivers/net/sk98lin/h/skaddr.h linux-2.6.17/drivers/net/sk98lin/h/skaddr.h
678--- linux-2.6.17.orig/drivers/net/sk98lin/h/skaddr.h 2006-06-22 13:17:16.000000000 +0200
679+++ linux-2.6.17/drivers/net/sk98lin/h/skaddr.h 2006-04-27 11:43:44.000000000 +0200
680@@ -2,14 +2,15 @@
681 *
682 * Name: skaddr.h
683 * Project: Gigabit Ethernet Adapters, ADDR-Modul
684- * Version: $Revision$
685- * Date: $Date$
686+ * Version: $Revision$
687+ * Date: $Date$
688 * Purpose: Header file for Address Management (MC, UC, Prom).
689 *
690 ******************************************************************************/
691
692 /******************************************************************************
693 *
694+ * LICENSE:
695 * (C)Copyright 1998-2002 SysKonnect GmbH.
696 * (C)Copyright 2002-2003 Marvell.
697 *
698@@ -19,6 +20,7 @@
699 * (at your option) any later version.
700 *
701 * The information in this file is provided "AS IS" without warranty.
702+ * /LICENSE
703 *
704 ******************************************************************************/
705
706@@ -236,6 +238,18 @@
707 SK_U32 PortNumber,
708 int Flags);
709
710+extern int SkAddrXmacMcClear(
711+ SK_AC *pAC,
712+ SK_IOC IoC,
713+ SK_U32 PortNumber,
714+ int Flags);
715+
716+extern int SkAddrGmacMcClear(
717+ SK_AC *pAC,
718+ SK_IOC IoC,
719+ SK_U32 PortNumber,
720+ int Flags);
721+
722 extern int SkAddrMcAdd(
723 SK_AC *pAC,
724 SK_IOC IoC,
725@@ -243,11 +257,41 @@
726 SK_MAC_ADDR *pMc,
727 int Flags);
728
729+extern int SkAddrXmacMcAdd(
730+ SK_AC *pAC,
731+ SK_IOC IoC,
732+ SK_U32 PortNumber,
733+ SK_MAC_ADDR *pMc,
734+ int Flags);
735+
736+extern SK_U32 SkXmacMcHash(
737+ unsigned char *pMc);
738+
739+extern int SkAddrGmacMcAdd(
740+ SK_AC *pAC,
741+ SK_IOC IoC,
742+ SK_U32 PortNumber,
743+ SK_MAC_ADDR *pMc,
744+ int Flags);
745+
746+extern SK_U32 SkGmacMcHash(
747+ unsigned char *pMc);
748+
749 extern int SkAddrMcUpdate(
750 SK_AC *pAC,
751 SK_IOC IoC,
752 SK_U32 PortNumber);
753
754+extern int SkAddrXmacMcUpdate(
755+ SK_AC *pAC,
756+ SK_IOC IoC,
757+ SK_U32 PortNumber);
758+
759+extern int SkAddrGmacMcUpdate(
760+ SK_AC *pAC,
761+ SK_IOC IoC,
762+ SK_U32 PortNumber);
763+
764 extern int SkAddrOverride(
765 SK_AC *pAC,
766 SK_IOC IoC,
767@@ -261,6 +305,18 @@
768 SK_U32 PortNumber,
769 int NewPromMode);
770
771+extern int SkAddrXmacPromiscuousChange(
772+ SK_AC *pAC,
773+ SK_IOC IoC,
774+ SK_U32 PortNumber,
775+ int NewPromMode);
776+
777+extern int SkAddrGmacPromiscuousChange(
778+ SK_AC *pAC,
779+ SK_IOC IoC,
780+ SK_U32 PortNumber,
781+ int NewPromMode);
782+
783 #ifndef SK_SLIM
784 extern int SkAddrSwap(
785 SK_AC *pAC,
786diff -urN linux-2.6.17.orig/drivers/net/sk98lin/h/skcsum.h linux-2.6.17/drivers/net/sk98lin/h/skcsum.h
787--- linux-2.6.17.orig/drivers/net/sk98lin/h/skcsum.h 2006-06-22 13:17:16.000000000 +0200
788+++ linux-2.6.17/drivers/net/sk98lin/h/skcsum.h 2006-04-27 11:43:44.000000000 +0200
789@@ -2,14 +2,15 @@
790 *
791 * Name: skcsum.h
792 * Project: GEnesis - SysKonnect SK-NET Gigabit Ethernet (SK-98xx)
793- * Version: $Revision$
794- * Date: $Date$
795+ * Version: $Revision$
796+ * Date: $Date$
797 * Purpose: Store/verify Internet checksum in send/receive packets.
798 *
799 ******************************************************************************/
800
801 /******************************************************************************
802 *
803+ * LICENSE:
804 * (C)Copyright 1998-2001 SysKonnect GmbH.
805 *
806 * This program is free software; you can redistribute it and/or modify
807@@ -18,6 +19,7 @@
808 * (at your option) any later version.
809 *
810 * The information in this file is provided "AS IS" without warranty.
811+ * /LICENSE
812 *
813 ******************************************************************************/
814
815@@ -157,9 +159,7 @@
816 typedef struct s_Csum {
817 /* Enabled receive SK_PROTO_XXX bit flags. */
818 unsigned ReceiveFlags[SK_MAX_NETS];
819-#ifdef TX_CSUM
820 unsigned TransmitFlags[SK_MAX_NETS];
821-#endif /* TX_CSUM */
822
823 /* The protocol statistics structure; one per supported protocol. */
824 SKCS_PROTO_STATS ProtoStats[SK_MAX_NETS][SKCS_NUM_PROTOCOLS];
825@@ -203,6 +203,12 @@
826 unsigned Checksum2,
827 int NetNumber);
828
829+extern void SkCsGetSendInfo(
830+ SK_AC *pAc,
831+ void *pIpHeader,
832+ SKCS_PACKET_INFO *pPacketInfo,
833+ int NetNumber);
834+
835 extern void SkCsSetReceiveFlags(
836 SK_AC *pAc,
837 unsigned ReceiveFlags,
838diff -urN linux-2.6.17.orig/drivers/net/sk98lin/h/skdebug.h linux-2.6.17/drivers/net/sk98lin/h/skdebug.h
839--- linux-2.6.17.orig/drivers/net/sk98lin/h/skdebug.h 2006-06-22 13:17:16.000000000 +0200
840+++ linux-2.6.17/drivers/net/sk98lin/h/skdebug.h 2006-04-27 11:43:44.000000000 +0200
841@@ -2,23 +2,24 @@
842 *
843 * Name: skdebug.h
844 * Project: Gigabit Ethernet Adapters, Common Modules
845- * Version: $Revision$
846- * Date: $Date$
847+ * Version: $Revision$
848+ * Date: $Date$
849 * Purpose: SK specific DEBUG support
850 *
851 ******************************************************************************/
852
853 /******************************************************************************
854 *
855+ * LICENSE:
856 * (C)Copyright 1998-2002 SysKonnect.
857- * (C)Copyright 2002-2003 Marvell.
858+ * (C)Copyright 2002-2005 Marvell.
859 *
860 * This program is free software; you can redistribute it and/or modify
861 * it under the terms of the GNU General Public License as published by
862 * the Free Software Foundation; either version 2 of the License, or
863 * (at your option) any later version.
864- *
865 * The information in this file is provided "AS IS" without warranty.
866+ * /LICENSE
867 *
868 ******************************************************************************/
869
870@@ -28,9 +29,9 @@
871 #ifdef DEBUG
872 #ifndef SK_DBG_MSG
873 #define SK_DBG_MSG(pAC,comp,cat,arg) \
874- if ( ((comp) & SK_DBG_CHKMOD(pAC)) && \
875- ((cat) & SK_DBG_CHKCAT(pAC)) ) { \
876- SK_DBG_PRINTF arg ; \
877+ if ( ((comp) & SK_DBG_CHKMOD(pAC)) && \
878+ ((cat) & SK_DBG_CHKCAT(pAC)) ) { \
879+ SK_DBG_PRINTF arg; \
880 }
881 #endif
882 #else
883@@ -58,6 +59,13 @@
884 #define SK_DBGMOD_ADDR 0x00000080L /* ADDR module */
885 #define SK_DBGMOD_PECP 0x00000100L /* PECP module */
886 #define SK_DBGMOD_POWM 0x00000200L /* Power Management module */
887+#ifdef SK_ASF
888+#define SK_DBGMOD_ASF 0x00000400L /* ASF module */
889+#endif
890+#ifdef SK_LBFO
891+#define SK_DBGMOD_LACP 0x00000800L /* link aggregation control protocol */
892+#define SK_DBGMOD_FD 0x00001000L /* frame distributor (link aggregation) */
893+#endif /* SK_LBFO */
894
895 /* Debug events */
896
897diff -urN linux-2.6.17.orig/drivers/net/sk98lin/h/skdrv1st.h linux-2.6.17/drivers/net/sk98lin/h/skdrv1st.h
898--- linux-2.6.17.orig/drivers/net/sk98lin/h/skdrv1st.h 2006-06-22 13:17:16.000000000 +0200
899+++ linux-2.6.17/drivers/net/sk98lin/h/skdrv1st.h 2006-04-27 11:43:45.000000000 +0200
900@@ -2,8 +2,8 @@
901 *
902 * Name: skdrv1st.h
903 * Project: GEnesis, PCI Gigabit Ethernet Adapter
904- * Version: $Revision$
905- * Date: $Date$
906+ * Version: $Revision$
907+ * Date: $Date$
908 * Purpose: First header file for driver and all other modules
909 *
910 ******************************************************************************/
911@@ -11,7 +11,7 @@
912 /******************************************************************************
913 *
914 * (C)Copyright 1998-2002 SysKonnect GmbH.
915- * (C)Copyright 2002-2003 Marvell.
916+ * (C)Copyright 2002-2005 Marvell.
917 *
918 * This program is free software; you can redistribute it and/or modify
919 * it under the terms of the GNU General Public License as published by
920@@ -22,23 +22,12 @@
921 *
922 ******************************************************************************/
923
924-/******************************************************************************
925- *
926- * Description:
927- *
928- * This is the first include file of the driver, which includes all
929- * neccessary system header files and some of the GEnesis header files.
930- * It also defines some basic items.
931- *
932- * Include File Hierarchy:
933- *
934- * see skge.c
935- *
936- ******************************************************************************/
937-
938 #ifndef __INC_SKDRV1ST_H
939 #define __INC_SKDRV1ST_H
940
941+/* Check kernel version */
942+#include <linux/version.h>
943+
944 typedef struct s_AC SK_AC;
945
946 /* Set card versions */
947@@ -55,6 +44,9 @@
948
949 #define SK_ADDR_EQUAL(a1,a2) (!memcmp(a1,a2,6))
950
951+#define SK_STRNCMP(s1,s2,len) strncmp(s1,s2,len)
952+#define SK_STRCPY(dest,src) strcpy(dest,src)
953+
954 #include <linux/types.h>
955 #include <linux/kernel.h>
956 #include <linux/string.h>
957@@ -63,10 +55,9 @@
958 #include <linux/slab.h>
959 #include <linux/interrupt.h>
960 #include <linux/pci.h>
961-#include <linux/bitops.h>
962 #include <asm/byteorder.h>
963+#include <asm/bitops.h>
964 #include <asm/io.h>
965-#include <asm/irq.h>
966 #include <linux/netdevice.h>
967 #include <linux/etherdevice.h>
968 #include <linux/skbuff.h>
969@@ -76,11 +67,7 @@
970 #include <net/checksum.h>
971
972 #define SK_CS_CALCULATE_CHECKSUM
973-#ifndef CONFIG_X86_64
974-#define SkCsCalculateChecksum(p,l) ((~ip_compute_csum(p, l)) & 0xffff)
975-#else
976-#define SkCsCalculateChecksum(p,l) ((~ip_fast_csum(p, l)) & 0xffff)
977-#endif
978+#define SkCsCalculateChecksum(p,l) (~csum_fold(csum_partial(p, l, 0)))
979
980 #include "h/sktypes.h"
981 #include "h/skerror.h"
982@@ -88,10 +75,15 @@
983 #include "h/lm80.h"
984 #include "h/xmac_ii.h"
985
986+#ifndef SK_BMU_RX_WM_PEX
987+#define SK_BMU_RX_WM_PEX 0x80
988+#endif
989+
990 #ifdef __LITTLE_ENDIAN
991 #define SK_LITTLE_ENDIAN
992 #else
993 #define SK_BIG_ENDIAN
994+#define SK_USE_REV_DESC
995 #endif
996
997 #define SK_NET_DEVICE net_device
998@@ -107,7 +99,7 @@
999 #define SK_MAX_MACS 2
1000 #define SK_MAX_NETS 2
1001
1002-#define SK_IOC char __iomem *
1003+#define SK_IOC char*
1004
1005 typedef struct s_DrvRlmtMbuf SK_MBUF;
1006
1007@@ -186,3 +178,8 @@
1008
1009 #endif
1010
1011+/*******************************************************************************
1012+ *
1013+ * End of file
1014+ *
1015+ ******************************************************************************/
1016diff -urN linux-2.6.17.orig/drivers/net/sk98lin/h/skdrv2nd.h linux-2.6.17/drivers/net/sk98lin/h/skdrv2nd.h
1017--- linux-2.6.17.orig/drivers/net/sk98lin/h/skdrv2nd.h 2006-06-22 13:17:16.000000000 +0200
1018+++ linux-2.6.17/drivers/net/sk98lin/h/skdrv2nd.h 2006-04-27 11:43:45.000000000 +0200
1019@@ -1,17 +1,17 @@
1020 /******************************************************************************
1021 *
1022- * Name: skdrv2nd.h
1023- * Project: GEnesis, PCI Gigabit Ethernet Adapter
1024- * Version: $Revision$
1025- * Date: $Date$
1026- * Purpose: Second header file for driver and all other modules
1027+ * Name: skdrv2nd.h
1028+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
1029+ * Version: $Revision$
1030+ * Date: $Date$
1031+ * Purpose: Second header file for driver and all other modules
1032 *
1033 ******************************************************************************/
1034
1035 /******************************************************************************
1036 *
1037 * (C)Copyright 1998-2002 SysKonnect GmbH.
1038- * (C)Copyright 2002-2003 Marvell.
1039+ * (C)Copyright 2002-2005 Marvell.
1040 *
1041 * This program is free software; you can redistribute it and/or modify
1042 * it under the terms of the GNU General Public License as published by
1043@@ -42,10 +42,11 @@
1044 #include "h/skqueue.h"
1045 #include "h/skgehwt.h"
1046 #include "h/sktimer.h"
1047-#include "h/ski2c.h"
1048+#include "h/sktwsi.h"
1049 #include "h/skgepnmi.h"
1050 #include "h/skvpd.h"
1051 #include "h/skgehw.h"
1052+#include "h/sky2le.h"
1053 #include "h/skgeinit.h"
1054 #include "h/skaddr.h"
1055 #include "h/skgesirq.h"
1056@@ -53,103 +54,191 @@
1057 #include "h/skrlmt.h"
1058 #include "h/skgedrv.h"
1059
1060+/* Defines for the poll cotroller */
1061+#define SK_NETDUMP_POLL
1062
1063-extern SK_MBUF *SkDrvAllocRlmtMbuf(SK_AC*, SK_IOC, unsigned);
1064-extern void SkDrvFreeRlmtMbuf(SK_AC*, SK_IOC, SK_MBUF*);
1065-extern SK_U64 SkOsGetTime(SK_AC*);
1066-extern int SkPciReadCfgDWord(SK_AC*, int, SK_U32*);
1067-extern int SkPciReadCfgWord(SK_AC*, int, SK_U16*);
1068-extern int SkPciReadCfgByte(SK_AC*, int, SK_U8*);
1069-extern int SkPciWriteCfgWord(SK_AC*, int, SK_U16);
1070-extern int SkPciWriteCfgByte(SK_AC*, int, SK_U8);
1071-extern int SkDrvEvent(SK_AC*, SK_IOC IoC, SK_U32, SK_EVPARA);
1072-
1073-#ifdef SK_DIAG_SUPPORT
1074-extern int SkDrvEnterDiagMode(SK_AC *pAc);
1075-extern int SkDrvLeaveDiagMode(SK_AC *pAc);
1076+#ifdef SK_NETDUMP_POLL
1077+#ifdef HAVE_POLL_CONTROLLER
1078+#define SK_POLL_CONTROLLER
1079+#define CONFIG_SK98LIN_NAPI
1080+#elif CONFIG_NET_POLL_CONTROLLER
1081+#define SK_POLL_CONTROLLER
1082+#define CONFIG_SK98LIN_NAPI
1083 #endif
1084+#endif
1085+
1086+
1087+/******************************************************************************
1088+ *
1089+ * Generic driver defines
1090+ *
1091+ ******************************************************************************/
1092+
1093+#define USE_TIST_FOR_RESET /* Use timestamp for reset */
1094+#define Y2_RECOVERY /* use specific recovery yukon2 functions */
1095+#define Y2_LE_CHECK /* activate check for LE order */
1096+#define Y2_SYNC_CHECK /* activate check for receiver in sync */
1097+#define SK_YUKON2 /* Enable Yukon2 dual net support */
1098+#define USE_SK_TX_CHECKSUM /* use the tx hw checksum driver functionality */
1099+#define USE_SK_RX_CHECKSUM /* use the rx hw checksum driver functionality */
1100+#define USE_SK_TSO_FEATURE /* use TCP segmentation offload if possible */
1101+#define SK_COPY_THRESHOLD 50 /* threshold for copying small RX frames;
1102+ * 0 avoids copying, 9001 copies all */
1103+#define SK_MAX_CARD_PARAM 16 /* number of adapters that can be configured via
1104+ * command line params */
1105+//#define USE_TX_COMPLETE /* use of a transmit complete interrupt */
1106+#define Y2_RX_CHECK /* RX Check timestamp */
1107+
1108+/*
1109+ * use those defines for a compile-in version of the driver instead
1110+ * of command line parameters
1111+ */
1112+// #define LINK_SPEED_A {"Auto",}
1113+// #define LINK_SPEED_B {"Auto",}
1114+// #define AUTO_NEG_A {"Sense",}
1115+// #define AUTO_NEG_B {"Sense"}
1116+// #define DUP_CAP_A {"Both",}
1117+// #define DUP_CAP_B {"Both",}
1118+// #define FLOW_CTRL_A {"SymOrRem",}
1119+// #define FLOW_CTRL_B {"SymOrRem",}
1120+// #define ROLE_A {"Auto",}
1121+// #define ROLE_B {"Auto",}
1122+// #define PREF_PORT {"A",}
1123+// #define CON_TYPE {"Auto",}
1124+// #define RLMT_MODE {"CheckLinkState",}
1125+
1126+#ifdef Y2_RECOVERY
1127+#define CHECK_TRANSMIT_TIMEOUT
1128+#define Y2_RESYNC_WATERMARK 1000000L
1129+#endif
1130+
1131+
1132+/******************************************************************************
1133+ *
1134+ * Generic ISR defines
1135+ *
1136+ ******************************************************************************/
1137+
1138+#define SkIsrRetVar irqreturn_t
1139+#define SkIsrRetNone IRQ_NONE
1140+#define SkIsrRetHandled IRQ_HANDLED
1141+
1142+#define DEV_KFREE_SKB(skb) dev_kfree_skb(skb)
1143+#define DEV_KFREE_SKB_IRQ(skb) dev_kfree_skb_irq(skb)
1144+#define DEV_KFREE_SKB_ANY(skb) dev_kfree_skb_any(skb)
1145+
1146+/******************************************************************************
1147+ *
1148+ * Global function prototypes
1149+ *
1150+ ******************************************************************************/
1151+
1152+extern SK_MBUF *SkDrvAllocRlmtMbuf(SK_AC*, SK_IOC, unsigned);
1153+extern void SkDrvFreeRlmtMbuf(SK_AC*, SK_IOC, SK_MBUF*);
1154+extern SK_U64 SkOsGetTime(SK_AC*);
1155+extern int SkPciReadCfgDWord(SK_AC*, int, SK_U32*);
1156+extern int SkPciReadCfgWord(SK_AC*, int, SK_U16*);
1157+extern int SkPciReadCfgByte(SK_AC*, int, SK_U8*);
1158+extern int SkPciWriteCfgDWord(SK_AC*, int, SK_U32);
1159+extern int SkPciWriteCfgWord(SK_AC*, int, SK_U16);
1160+extern int SkPciWriteCfgByte(SK_AC*, int, SK_U8);
1161+extern int SkDrvEvent(SK_AC*, SK_IOC IoC, SK_U32, SK_EVPARA);
1162+extern int SkDrvEnterDiagMode(SK_AC *pAc);
1163+extern int SkDrvLeaveDiagMode(SK_AC *pAc);
1164+
1165+/******************************************************************************
1166+ *
1167+ * Linux specific RLMT buffer structure (SK_MBUF typedef in skdrv1st)!
1168+ *
1169+ ******************************************************************************/
1170
1171 struct s_DrvRlmtMbuf {
1172- SK_MBUF *pNext; /* Pointer to next RLMT Mbuf. */
1173- SK_U8 *pData; /* Data buffer (virtually contig.). */
1174- unsigned Size; /* Data buffer size. */
1175- unsigned Length; /* Length of packet (<= Size). */
1176- SK_U32 PortIdx; /* Receiving/transmitting port. */
1177+ SK_MBUF *pNext; /* Pointer to next RLMT Mbuf. */
1178+ SK_U8 *pData; /* Data buffer (virtually contig.). */
1179+ unsigned Size; /* Data buffer size. */
1180+ unsigned Length; /* Length of packet (<= Size). */
1181+ SK_U32 PortIdx; /* Receiving/transmitting port. */
1182 #ifdef SK_RLMT_MBUF_PRIVATE
1183- SK_RLMT_MBUF Rlmt; /* Private part for RLMT. */
1184-#endif /* SK_RLMT_MBUF_PRIVATE */
1185- struct sk_buff *pOs; /* Pointer to message block */
1186+ SK_RLMT_MBUF Rlmt; /* Private part for RLMT. */
1187+#endif
1188+ struct sk_buff *pOs; /* Pointer to message block */
1189 };
1190
1191+/******************************************************************************
1192+ *
1193+ * Linux specific TIME defines
1194+ *
1195+ ******************************************************************************/
1196
1197-/*
1198- * Time macros
1199- */
1200 #if SK_TICKS_PER_SEC == 100
1201 #define SK_PNMI_HUNDREDS_SEC(t) (t)
1202 #else
1203-#define SK_PNMI_HUNDREDS_SEC(t) ((((unsigned long)t) * 100) / \
1204- (SK_TICKS_PER_SEC))
1205+#define SK_PNMI_HUNDREDS_SEC(t) ((((unsigned long)t)*100)/(SK_TICKS_PER_SEC))
1206 #endif
1207
1208-/*
1209- * New SkOsGetTime
1210- */
1211 #define SkOsGetTimeCurrent(pAC, pUsec) {\
1212+ static struct timeval prev_t; \
1213 struct timeval t;\
1214 do_gettimeofday(&t);\
1215- *pUsec = ((((t.tv_sec) * 1000000L)+t.tv_usec)/10000);\
1216+ if (prev_t.tv_sec == t.tv_sec) { \
1217+ if (prev_t.tv_usec > t.tv_usec) { \
1218+ t.tv_usec = prev_t.tv_usec; \
1219+ } else { \
1220+ prev_t.tv_usec = t.tv_usec; \
1221+ } \
1222+ } else { \
1223+ prev_t = t; \
1224+ } \
1225+ *pUsec = ((t.tv_sec*100L)+(t.tv_usec/10000));\
1226 }
1227
1228+/******************************************************************************
1229+ *
1230+ * Linux specific IOCTL defines and typedefs
1231+ *
1232+ ******************************************************************************/
1233
1234-/*
1235- * ioctl definitions
1236- */
1237-#define SK_IOCTL_BASE (SIOCDEVPRIVATE)
1238-#define SK_IOCTL_GETMIB (SK_IOCTL_BASE + 0)
1239-#define SK_IOCTL_SETMIB (SK_IOCTL_BASE + 1)
1240-#define SK_IOCTL_PRESETMIB (SK_IOCTL_BASE + 2)
1241-#define SK_IOCTL_GEN (SK_IOCTL_BASE + 3)
1242-#define SK_IOCTL_DIAG (SK_IOCTL_BASE + 4)
1243-
1244-typedef struct s_IOCTL SK_GE_IOCTL;
1245+#define SK_IOCTL_BASE (SIOCDEVPRIVATE)
1246+#define SK_IOCTL_GETMIB (SK_IOCTL_BASE + 0)
1247+#define SK_IOCTL_SETMIB (SK_IOCTL_BASE + 1)
1248+#define SK_IOCTL_PRESETMIB (SK_IOCTL_BASE + 2)
1249+#define SK_IOCTL_GEN (SK_IOCTL_BASE + 3)
1250+#define SK_IOCTL_DIAG (SK_IOCTL_BASE + 4)
1251
1252+typedef struct s_IOCTL SK_GE_IOCTL;
1253 struct s_IOCTL {
1254 char __user * pData;
1255 unsigned int Len;
1256 };
1257
1258+/******************************************************************************
1259+ *
1260+ * Generic sizes and length definitions
1261+ *
1262+ ******************************************************************************/
1263
1264-/*
1265- * define sizes of descriptor rings in bytes
1266- */
1267-
1268-#define TX_RING_SIZE (8*1024)
1269-#define RX_RING_SIZE (24*1024)
1270-
1271-/*
1272- * Buffer size for ethernet packets
1273- */
1274-#define ETH_BUF_SIZE 1540
1275-#define ETH_MAX_MTU 1514
1276-#define ETH_MIN_MTU 60
1277-#define ETH_MULTICAST_BIT 0x01
1278-#define SK_JUMBO_MTU 9000
1279-
1280-/*
1281- * transmit priority selects the queue: LOW=asynchron, HIGH=synchron
1282- */
1283-#define TX_PRIO_LOW 0
1284-#define TX_PRIO_HIGH 1
1285+#define TX_RING_SIZE (24*1024) /* GEnesis/Yukon */
1286+#define RX_RING_SIZE (24*1024) /* GEnesis/Yukon */
1287+#define RX_MAX_NBR_BUFFERS 128 /* Yukon-EC/-II */
1288+#define TX_MAX_NBR_BUFFERS 128 /* Yukon-EC/-II */
1289+#define MAXIMUM_LOW_ADDRESS 0xFFFFFFFF /* Max. low address */
1290+
1291+#define ETH_BUF_SIZE 1560 /* multiples of 8 bytes */
1292+#define ETH_MAX_MTU 1514
1293+#define ETH_MIN_MTU 60
1294+#define ETH_MULTICAST_BIT 0x01
1295+#define SK_JUMBO_MTU 9000
1296+
1297+#define TX_PRIO_LOW 0 /* asynchronous queue */
1298+#define TX_PRIO_HIGH 1 /* synchronous queue */
1299+#define DESCR_ALIGN 64 /* alignment of Rx/Tx descriptors */
1300
1301-/*
1302- * alignment of rx/tx descriptors
1303- */
1304-#define DESCR_ALIGN 64
1305+/******************************************************************************
1306+ *
1307+ * PNMI related definitions
1308+ *
1309+ ******************************************************************************/
1310
1311-/*
1312- * definitions for pnmi. TODO
1313- */
1314 #define SK_DRIVER_RESET(pAC, IoC) 0
1315 #define SK_DRIVER_SENDEVENT(pAC, IoC) 0
1316 #define SK_DRIVER_SELFTEST(pAC, IoC) 0
1317@@ -158,20 +247,16 @@
1318 #define SK_DRIVER_SET_MTU(pAc,IoC,i,v) 0
1319 #define SK_DRIVER_PRESET_MTU(pAc,IoC,i,v) 0
1320
1321-/*
1322-** Interim definition of SK_DRV_TIMER placed in this file until
1323-** common modules have boon finallized
1324-*/
1325-#define SK_DRV_TIMER 11
1326-#define SK_DRV_MODERATION_TIMER 1
1327-#define SK_DRV_MODERATION_TIMER_LENGTH 1000000 /* 1 second */
1328-#define SK_DRV_RX_CLEANUP_TIMER 2
1329-#define SK_DRV_RX_CLEANUP_TIMER_LENGTH 1000000 /* 100 millisecs */
1330
1331-/*
1332-** Definitions regarding transmitting frames
1333-** any calculating any checksum.
1334-*/
1335+/******************************************************************************
1336+ *
1337+ * Various offsets and sizes
1338+ *
1339+ ******************************************************************************/
1340+
1341+#define SK_DRV_MODERATION_TIMER 1 /* id */
1342+#define SK_DRV_MODERATION_TIMER_LENGTH 1 /* 1 second */
1343+
1344 #define C_LEN_ETHERMAC_HEADER_DEST_ADDR 6
1345 #define C_LEN_ETHERMAC_HEADER_SRC_ADDR 6
1346 #define C_LEN_ETHERMAC_HEADER_LENTYPE 2
1347@@ -197,112 +282,445 @@
1348 #define C_PROTO_ID_UDP 17 /* refer to RFC 790 or Stevens' */
1349 #define C_PROTO_ID_TCP 6 /* TCP/IP illustrated for details */
1350
1351-/* TX and RX descriptors *****************************************************/
1352+/******************************************************************************
1353+ *
1354+ * Tx and Rx descriptor definitions
1355+ *
1356+ ******************************************************************************/
1357
1358 typedef struct s_RxD RXD; /* the receive descriptor */
1359-
1360 struct s_RxD {
1361- volatile SK_U32 RBControl; /* Receive Buffer Control */
1362- SK_U32 VNextRxd; /* Next receive descriptor,low dword */
1363- SK_U32 VDataLow; /* Receive buffer Addr, low dword */
1364- SK_U32 VDataHigh; /* Receive buffer Addr, high dword */
1365- SK_U32 FrameStat; /* Receive Frame Status word */
1366- SK_U32 TimeStamp; /* Time stamp from XMAC */
1367- SK_U32 TcpSums; /* TCP Sum 2 / TCP Sum 1 */
1368- SK_U32 TcpSumStarts; /* TCP Sum Start 2 / TCP Sum Start 1 */
1369- RXD *pNextRxd; /* Pointer to next Rxd */
1370- struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */
1371+ volatile SK_U32 RBControl; /* Receive Buffer Control */
1372+ SK_U32 VNextRxd; /* Next receive descriptor,low dword */
1373+ SK_U32 VDataLow; /* Receive buffer Addr, low dword */
1374+ SK_U32 VDataHigh; /* Receive buffer Addr, high dword */
1375+ SK_U32 FrameStat; /* Receive Frame Status word */
1376+ SK_U32 TimeStamp; /* Time stamp from XMAC */
1377+ SK_U32 TcpSums; /* TCP Sum 2 / TCP Sum 1 */
1378+ SK_U32 TcpSumStarts; /* TCP Sum Start 2 / TCP Sum Start 1 */
1379+ RXD *pNextRxd; /* Pointer to next Rxd */
1380+ struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */
1381 };
1382
1383 typedef struct s_TxD TXD; /* the transmit descriptor */
1384-
1385 struct s_TxD {
1386- volatile SK_U32 TBControl; /* Transmit Buffer Control */
1387- SK_U32 VNextTxd; /* Next transmit descriptor,low dword */
1388- SK_U32 VDataLow; /* Transmit Buffer Addr, low dword */
1389- SK_U32 VDataHigh; /* Transmit Buffer Addr, high dword */
1390- SK_U32 FrameStat; /* Transmit Frame Status Word */
1391- SK_U32 TcpSumOfs; /* Reserved / TCP Sum Offset */
1392- SK_U16 TcpSumSt; /* TCP Sum Start */
1393- SK_U16 TcpSumWr; /* TCP Sum Write */
1394- SK_U32 TcpReserved; /* not used */
1395- TXD *pNextTxd; /* Pointer to next Txd */
1396- struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */
1397+ volatile SK_U32 TBControl; /* Transmit Buffer Control */
1398+ SK_U32 VNextTxd; /* Next transmit descriptor,low dword */
1399+ SK_U32 VDataLow; /* Transmit Buffer Addr, low dword */
1400+ SK_U32 VDataHigh; /* Transmit Buffer Addr, high dword */
1401+ SK_U32 FrameStat; /* Transmit Frame Status Word */
1402+ SK_U32 TcpSumOfs; /* Reserved / TCP Sum Offset */
1403+ SK_U16 TcpSumSt; /* TCP Sum Start */
1404+ SK_U16 TcpSumWr; /* TCP Sum Write */
1405+ SK_U32 TcpReserved; /* not used */
1406+ TXD *pNextTxd; /* Pointer to next Txd */
1407+ struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */
1408+};
1409+
1410+/******************************************************************************
1411+ *
1412+ * Generic Yukon-II defines
1413+ *
1414+ ******************************************************************************/
1415+
1416+#define LE_SIZE sizeof(SK_HWLE)
1417+#define MAX_NUM_FRAGS (MAX_SKB_FRAGS + 1)
1418+#define MIN_LEN_OF_LE_TAB 128
1419+#define MAX_LEN_OF_LE_TAB 4096
1420+#define MAX_UNUSED_RX_LE_WORKING 8
1421+#ifdef MAX_FRAG_OVERHEAD
1422+#undef MAX_FRAG_OVERHEAD
1423+#define MAX_FRAG_OVERHEAD 4
1424+#endif
1425+// as we have a maximum of 16 physical fragments,
1426+// maximum 1 ADDR64 per physical fragment
1427+// maximum 4 LEs for VLAN, Csum, LargeSend, Packet
1428+#define MIN_LE_FREE_REQUIRED ((16*2) + 4)
1429+#define IS_GMAC(pAc) (!pAc->GIni.GIGenesis)
1430+#ifdef USE_SYNC_TX_QUEUE
1431+#define TXS_MAX_LE 256
1432+#else /* !USE_SYNC_TX_QUEUE */
1433+#define TXS_MAX_LE 0
1434+#endif
1435+
1436+#define ETHER_MAC_HDR_LEN (6+6+2) // MAC SRC ADDR, MAC DST ADDR, TYPE
1437+#define IP_HDR_LEN 20
1438+#define TCP_CSUM_OFFS 0x10
1439+#define UDP_CSUM_OFFS 0x06
1440+#define TXA_MAX_LE 256
1441+#define RX_MAX_LE 256
1442+#define ST_MAX_LE (SK_MAX_MACS)*((3*RX_MAX_LE)+(TXA_MAX_LE)+(TXS_MAX_LE))
1443+
1444+#if (defined (Y2_RECOVERY) || defined (Y2_LE_CHECK))
1445+/* event for recovery from tx hang or rx out of sync */
1446+#define SK_DRV_RECOVER 17
1447+#endif
1448+/******************************************************************************
1449+ *
1450+ * Structures specific for Yukon-II
1451+ *
1452+ ******************************************************************************/
1453+
1454+typedef struct s_frag SK_FRAG;
1455+struct s_frag {
1456+ SK_FRAG *pNext;
1457+ char *pVirt;
1458+ SK_U64 pPhys;
1459+ unsigned int FragLen;
1460 };
1461
1462-/* Used interrupt bits in the interrupts source register *********************/
1463+typedef struct s_packet SK_PACKET;
1464+struct s_packet {
1465+ /* Common infos: */
1466+ SK_PACKET *pNext; /* pointer for packet queues */
1467+ unsigned int PacketLen; /* length of packet */
1468+ unsigned int NumFrags; /* nbr of fragments (for Rx always 1) */
1469+ SK_FRAG *pFrag; /* fragment list */
1470+ SK_FRAG FragArray[MAX_NUM_FRAGS]; /* TX fragment array */
1471+ unsigned int NextLE; /* next LE to use for the next packet */
1472+
1473+ /* Private infos: */
1474+ struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */
1475+};
1476+
1477+typedef struct s_queue SK_PKT_QUEUE;
1478+struct s_queue {
1479+ SK_PACKET *pHead;
1480+ SK_PACKET *pTail;
1481+ spinlock_t QueueLock; /* serialize packet accesses */
1482+};
1483+
1484+/*******************************************************************************
1485+ *
1486+ * Macros specific for Yukon-II queues
1487+ *
1488+ ******************************************************************************/
1489+
1490+#define IS_Q_EMPTY(pQueue) ((pQueue)->pHead != NULL) ? SK_FALSE : SK_TRUE
1491+#define IS_Q_LOCKED(pQueue) spin_is_locked(&((pQueue)->QueueLock))
1492+
1493+#define PLAIN_POP_FIRST_PKT_FROM_QUEUE(pQueue, pPacket) { \
1494+ if ((pQueue)->pHead != NULL) { \
1495+ (pPacket) = (pQueue)->pHead; \
1496+ (pQueue)->pHead = (pPacket)->pNext; \
1497+ if ((pQueue)->pHead == NULL) { \
1498+ (pQueue)->pTail = NULL; \
1499+ } \
1500+ (pPacket)->pNext = NULL; \
1501+ } else { \
1502+ (pPacket) = NULL; \
1503+ } \
1504+}
1505+
1506+#define PLAIN_PUSH_PKT_AS_FIRST_IN_QUEUE(pQueue, pPacket) { \
1507+ if ((pQueue)->pHead != NULL) { \
1508+ (pPacket)->pNext = (pQueue)->pHead; \
1509+ } else { \
1510+ (pPacket)->pNext = NULL; \
1511+ (pQueue)->pTail = (pPacket); \
1512+ } \
1513+ (pQueue)->pHead = (pPacket); \
1514+}
1515+
1516+#define PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(pQueue, pPacket) { \
1517+ (pPacket)->pNext = NULL; \
1518+ if ((pQueue)->pTail != NULL) { \
1519+ (pQueue)->pTail->pNext = (pPacket); \
1520+ } else { \
1521+ (pQueue)->pHead = (pPacket); \
1522+ } \
1523+ (pQueue)->pTail = (pPacket); \
1524+}
1525+
1526+#define PLAIN_PUSH_MULTIPLE_PKT_AS_LAST_IN_QUEUE(pQueue,pPktGrpStart,pPktGrpEnd) { \
1527+ if ((pPktGrpStart) != NULL) { \
1528+ if ((pQueue)->pTail != NULL) { \
1529+ (pQueue)->pTail->pNext = (pPktGrpStart); \
1530+ } else { \
1531+ (pQueue)->pHead = (pPktGrpStart); \
1532+ } \
1533+ (pQueue)->pTail = (pPktGrpEnd); \
1534+ } \
1535+}
1536+
1537+/* Required: 'Flags' */
1538+#define POP_FIRST_PKT_FROM_QUEUE(pQueue, pPacket) { \
1539+ spin_lock_irqsave(&((pQueue)->QueueLock), Flags); \
1540+ if ((pQueue)->pHead != NULL) { \
1541+ (pPacket) = (pQueue)->pHead; \
1542+ (pQueue)->pHead = (pPacket)->pNext; \
1543+ if ((pQueue)->pHead == NULL) { \
1544+ (pQueue)->pTail = NULL; \
1545+ } \
1546+ (pPacket)->pNext = NULL; \
1547+ } else { \
1548+ (pPacket) = NULL; \
1549+ } \
1550+ spin_unlock_irqrestore(&((pQueue)->QueueLock), Flags); \
1551+}
1552+
1553+/* Required: 'Flags' */
1554+#define PUSH_PKT_AS_FIRST_IN_QUEUE(pQueue, pPacket) { \
1555+ spin_lock_irqsave(&(pQueue)->QueueLock, Flags); \
1556+ if ((pQueue)->pHead != NULL) { \
1557+ (pPacket)->pNext = (pQueue)->pHead; \
1558+ } else { \
1559+ (pPacket)->pNext = NULL; \
1560+ (pQueue)->pTail = (pPacket); \
1561+ } \
1562+ (pQueue)->pHead = (pPacket); \
1563+ spin_unlock_irqrestore(&(pQueue)->QueueLock, Flags); \
1564+}
1565+
1566+/* Required: 'Flags' */
1567+#define PUSH_PKT_AS_LAST_IN_QUEUE(pQueue, pPacket) { \
1568+ (pPacket)->pNext = NULL; \
1569+ spin_lock_irqsave(&(pQueue)->QueueLock, Flags); \
1570+ if ((pQueue)->pTail != NULL) { \
1571+ (pQueue)->pTail->pNext = (pPacket); \
1572+ } else { \
1573+ (pQueue)->pHead = (pPacket); \
1574+ } \
1575+ (pQueue)->pTail = (pPacket); \
1576+ spin_unlock_irqrestore(&(pQueue)->QueueLock, Flags); \
1577+}
1578+
1579+/* Required: 'Flags' */
1580+#define PUSH_MULTIPLE_PKT_AS_LAST_IN_QUEUE(pQueue,pPktGrpStart,pPktGrpEnd) { \
1581+ if ((pPktGrpStart) != NULL) { \
1582+ spin_lock_irqsave(&(pQueue)->QueueLock, Flags); \
1583+ if ((pQueue)->pTail != NULL) { \
1584+ (pQueue)->pTail->pNext = (pPktGrpStart); \
1585+ } else { \
1586+ (pQueue)->pHead = (pPktGrpStart); \
1587+ } \
1588+ (pQueue)->pTail = (pPktGrpEnd); \
1589+ spin_unlock_irqrestore(&(pQueue)->QueueLock, Flags); \
1590+ } \
1591+}
1592+
1593+/*
1594+ *Check if the low address (32 bit) is near the 4G limit or over it.
1595+ * Set the high address to a wrong value.
1596+ * Doing so we force to write the ADDR64 LE.
1597+ */
1598+#define CHECK_LOW_ADDRESS( _HighAddress, _LowAddress , _Length) { \
1599+ if ((~0-_LowAddress) <_Length) { \
1600+ _HighAddress= MAXIMUM_LOW_ADDRESS; \
1601+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, \
1602+ ("High Address must be set for HW. LowAddr = %d Length = %d\n", \
1603+ _LowAddress, _Length)); \
1604+ } \
1605+}
1606+
1607+/*******************************************************************************
1608+ *
1609+ * Macros specific for Yukon-II queues (tist)
1610+ *
1611+ ******************************************************************************/
1612+
1613+#ifdef USE_TIST_FOR_RESET
1614+/* port is fully operational */
1615+#define SK_PSTATE_NOT_WAITING_FOR_TIST 0
1616+/* port in reset until any tist LE */
1617+#define SK_PSTATE_WAITING_FOR_ANY_TIST BIT_0
1618+/* port in reset until timer reaches pAC->MinTistLo */
1619+#define SK_PSTATE_WAITING_FOR_SPECIFIC_TIST BIT_1
1620+#define SK_PSTATE_PORT_SHIFT 4
1621+#define SK_PSTATE_PORT_MASK ((1 << SK_PSTATE_PORT_SHIFT) - 1)
1622+
1623+/* use this + Port to build OP_MOD_TXINDEX_NO_PORT_A|B */
1624+#define OP_MOD_TXINDEX 0x71
1625+/* opcode for a TX_INDEX LE in which Port A has to be ignored */
1626+#define OP_MOD_TXINDEX_NO_PORT_A 0x71
1627+/* opcode for a TX_INDEX LE in which Port B has to be ignored */
1628+#define OP_MOD_TXINDEX_NO_PORT_B 0x72
1629+/* opcode for LE to be ignored because port is still in reset */
1630+#define OP_MOD_LE 0x7F
1631+
1632+/* set tist wait mode Bit for port */
1633+#define SK_SET_WAIT_BIT_FOR_PORT(pAC, Bit, Port) \
1634+ { \
1635+ (pAC)->AdapterResetState |= ((Bit) << (SK_PSTATE_PORT_SHIFT * Port)); \
1636+ }
1637+
1638+/* reset tist waiting for specified port */
1639+#define SK_CLR_STATE_FOR_PORT(pAC, Port) \
1640+ { \
1641+ (pAC)->AdapterResetState &= \
1642+ ~(SK_PSTATE_PORT_MASK << (SK_PSTATE_PORT_SHIFT * Port)); \
1643+ }
1644+
1645+/* return SK_TRUE when port is in reset waiting for tist */
1646+#define SK_PORT_WAITING_FOR_TIST(pAC, Port) \
1647+ ((((pAC)->AdapterResetState >> (SK_PSTATE_PORT_SHIFT * Port)) & \
1648+ SK_PSTATE_PORT_MASK) != SK_PSTATE_NOT_WAITING_FOR_TIST)
1649+
1650+/* return SK_TRUE when port is in reset waiting for any tist */
1651+#define SK_PORT_WAITING_FOR_ANY_TIST(pAC, Port) \
1652+ ((((pAC)->AdapterResetState >> (SK_PSTATE_PORT_SHIFT * Port)) & \
1653+ SK_PSTATE_WAITING_FOR_ANY_TIST) == SK_PSTATE_WAITING_FOR_ANY_TIST)
1654+
1655+/* return SK_TRUE when port is in reset waiting for a specific tist */
1656+#define SK_PORT_WAITING_FOR_SPECIFIC_TIST(pAC, Port) \
1657+ ((((pAC)->AdapterResetState >> (SK_PSTATE_PORT_SHIFT * Port)) & \
1658+ SK_PSTATE_WAITING_FOR_SPECIFIC_TIST) == \
1659+ SK_PSTATE_WAITING_FOR_SPECIFIC_TIST)
1660+
1661+/* return whether adapter is expecting a tist LE */
1662+#define SK_ADAPTER_WAITING_FOR_TIST(pAC) ((pAC)->AdapterResetState != 0)
1663+
1664+/* enable timestamp timer and force creation of tist LEs */
1665+#define Y2_ENABLE_TIST(IoC) \
1666+ SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8) GMT_ST_START)
1667+
1668+/* disable timestamp timer and stop creation of tist LEs */
1669+#define Y2_DISABLE_TIST(IoC) \
1670+ SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8) GMT_ST_STOP)
1671+
1672+/* get current value of timestamp timer */
1673+#define Y2_GET_TIST_LOW_VAL(IoC, pVal) \
1674+ SK_IN32(IoC, GMAC_TI_ST_VAL, pVal)
1675
1676-#define DRIVER_IRQS ((IS_IRQ_SW) | \
1677- (IS_R1_F) |(IS_R2_F) | \
1678- (IS_XS1_F) |(IS_XA1_F) | \
1679- (IS_XS2_F) |(IS_XA2_F))
1680-
1681-#define SPECIAL_IRQS ((IS_HW_ERR) |(IS_I2C_READY) | \
1682- (IS_EXT_REG) |(IS_TIMINT) | \
1683- (IS_PA_TO_RX1) |(IS_PA_TO_RX2) | \
1684- (IS_PA_TO_TX1) |(IS_PA_TO_TX2) | \
1685- (IS_MAC1) |(IS_LNK_SYNC_M1)| \
1686- (IS_MAC2) |(IS_LNK_SYNC_M2)| \
1687- (IS_R1_C) |(IS_R2_C) | \
1688- (IS_XS1_C) |(IS_XA1_C) | \
1689- (IS_XS2_C) |(IS_XA2_C))
1690-
1691-#define IRQ_MASK ((IS_IRQ_SW) | \
1692- (IS_R1_B) |(IS_R1_F) |(IS_R2_B) |(IS_R2_F) | \
1693- (IS_XS1_B) |(IS_XS1_F) |(IS_XA1_B)|(IS_XA1_F)| \
1694- (IS_XS2_B) |(IS_XS2_F) |(IS_XA2_B)|(IS_XA2_F)| \
1695- (IS_HW_ERR) |(IS_I2C_READY)| \
1696- (IS_EXT_REG) |(IS_TIMINT) | \
1697- (IS_PA_TO_RX1) |(IS_PA_TO_RX2)| \
1698- (IS_PA_TO_TX1) |(IS_PA_TO_TX2)| \
1699- (IS_MAC1) |(IS_MAC2) | \
1700- (IS_R1_C) |(IS_R2_C) | \
1701- (IS_XS1_C) |(IS_XA1_C) | \
1702- (IS_XS2_C) |(IS_XA2_C))
1703+#endif
1704
1705-#define IRQ_HWE_MASK (IS_ERR_MSK) /* enable all HW irqs */
1706+
1707+/*******************************************************************************
1708+ *
1709+ * Used interrupt bits in the interrupts source register
1710+ *
1711+ ******************************************************************************/
1712+
1713+#define DRIVER_IRQS ((IS_IRQ_SW) | \
1714+ (IS_R1_F) | (IS_R2_F) | \
1715+ (IS_XS1_F) | (IS_XA1_F) | \
1716+ (IS_XS2_F) | (IS_XA2_F))
1717+
1718+#define TX_COMPL_IRQS ((IS_XS1_B) | (IS_XS1_F) | \
1719+ (IS_XA1_B) | (IS_XA1_F) | \
1720+ (IS_XS2_B) | (IS_XS2_F) | \
1721+ (IS_XA2_B) | (IS_XA2_F))
1722+
1723+#define NAPI_DRV_IRQS ((IS_R1_F) | (IS_R2_F) | \
1724+ (IS_XS1_F) | (IS_XA1_F)| \
1725+ (IS_XS2_F) | (IS_XA2_F))
1726+
1727+#define Y2_DRIVER_IRQS ((Y2_IS_STAT_BMU) | (Y2_IS_IRQ_SW) | (Y2_IS_POLL_CHK))
1728+
1729+#define SPECIAL_IRQS ((IS_HW_ERR) |(IS_I2C_READY) | \
1730+ (IS_EXT_REG) |(IS_TIMINT) | \
1731+ (IS_PA_TO_RX1) |(IS_PA_TO_RX2) | \
1732+ (IS_PA_TO_TX1) |(IS_PA_TO_TX2) | \
1733+ (IS_MAC1) |(IS_LNK_SYNC_M1)| \
1734+ (IS_MAC2) |(IS_LNK_SYNC_M2)| \
1735+ (IS_R1_C) |(IS_R2_C) | \
1736+ (IS_XS1_C) |(IS_XA1_C) | \
1737+ (IS_XS2_C) |(IS_XA2_C))
1738+
1739+#define Y2_SPECIAL_IRQS ((Y2_IS_HW_ERR) |(Y2_IS_ASF) | \
1740+ (Y2_IS_TWSI_RDY) |(Y2_IS_TIMINT) | \
1741+ (Y2_IS_IRQ_PHY2) |(Y2_IS_IRQ_MAC2) | \
1742+ (Y2_IS_CHK_RX2) |(Y2_IS_CHK_TXS2) | \
1743+ (Y2_IS_CHK_TXA2) |(Y2_IS_IRQ_PHY1) | \
1744+ (Y2_IS_IRQ_MAC1) |(Y2_IS_CHK_RX1) | \
1745+ (Y2_IS_CHK_TXS1) |(Y2_IS_CHK_TXA1))
1746+
1747+#define IRQ_MASK ((IS_IRQ_SW) | \
1748+ (IS_R1_F) |(IS_R2_F) | \
1749+ (IS_XS1_F) |(IS_XA1_F) | \
1750+ (IS_XS2_F) |(IS_XA2_F) | \
1751+ (IS_HW_ERR) |(IS_I2C_READY)| \
1752+ (IS_EXT_REG) |(IS_TIMINT) | \
1753+ (IS_PA_TO_RX1) |(IS_PA_TO_RX2)| \
1754+ (IS_PA_TO_TX1) |(IS_PA_TO_TX2)| \
1755+ (IS_MAC1) |(IS_MAC2) | \
1756+ (IS_R1_C) |(IS_R2_C) | \
1757+ (IS_XS1_C) |(IS_XA1_C) | \
1758+ (IS_XS2_C) |(IS_XA2_C))
1759+
1760+#define Y2_IRQ_MASK ((Y2_DRIVER_IRQS) | (Y2_SPECIAL_IRQS))
1761+
1762+#define IRQ_HWE_MASK (IS_ERR_MSK) /* enable all HW irqs */
1763+#define Y2_IRQ_HWE_MASK (Y2_HWE_ALL_MSK) /* enable all HW irqs */
1764
1765 typedef struct s_DevNet DEV_NET;
1766
1767 struct s_DevNet {
1768- int PortNr;
1769- int NetNr;
1770- SK_AC *pAC;
1771+ struct proc_dir_entry *proc;
1772+ int PortNr;
1773+ int NetNr;
1774+ char InitialDevName[20];
1775+ SK_BOOL NetConsoleMode;
1776+#ifdef Y2_RECOVERY
1777+ struct timer_list KernelTimer; /* Kernel timer struct */
1778+ int TransmitTimeoutTimer; /* Transmit timer */
1779+ SK_BOOL TimerExpired; /* Transmit timer */
1780+ SK_BOOL InRecover; /* Recover flag */
1781+#ifdef Y2_RX_CHECK
1782+ SK_U32 PreviousMACFifoRP; /* Backup of the FRP */
1783+ SK_U32 PreviousMACFifoRLev; /* Backup of the FRL */
1784+ SK_U32 PreviousRXFifoRP; /* Backup of the RX FRP */
1785+ SK_U8 PreviousRXFifoRLev; /* Backup of the RX FRL */
1786+ SK_U32 LastJiffies; /* Backup of the jiffies*/
1787+#endif
1788+#endif
1789+ SK_AC *pAC;
1790 };
1791
1792-typedef struct s_TxPort TX_PORT;
1793+/*******************************************************************************
1794+ *
1795+ * Rx/Tx Port structures
1796+ *
1797+ ******************************************************************************/
1798
1799-struct s_TxPort {
1800- /* the transmit descriptor rings */
1801- caddr_t pTxDescrRing; /* descriptor area memory */
1802- SK_U64 VTxDescrRing; /* descr. area bus virt. addr. */
1803- TXD *pTxdRingHead; /* Head of Tx rings */
1804- TXD *pTxdRingTail; /* Tail of Tx rings */
1805- TXD *pTxdRingPrev; /* descriptor sent previously */
1806- int TxdRingFree; /* # of free entrys */
1807- spinlock_t TxDesRingLock; /* serialize descriptor accesses */
1808- SK_IOC HwAddr; /* bmu registers address */
1809- int PortIndex; /* index number of port (0 or 1) */
1810+typedef struct s_TxPort TX_PORT;
1811+struct s_TxPort { /* the transmit descriptor rings */
1812+ caddr_t pTxDescrRing; /* descriptor area memory */
1813+ SK_U64 VTxDescrRing; /* descr. area bus virt. addr. */
1814+ TXD *pTxdRingHead; /* Head of Tx rings */
1815+ TXD *pTxdRingTail; /* Tail of Tx rings */
1816+ TXD *pTxdRingPrev; /* descriptor sent previously */
1817+ int TxdRingPrevFree;/* previously # of free entrys */
1818+ int TxdRingFree; /* # of free entrys */
1819+ spinlock_t TxDesRingLock; /* serialize descriptor accesses */
1820+ caddr_t HwAddr; /* bmu registers address */
1821+ int PortIndex; /* index number of port (0 or 1) */
1822+ SK_PACKET *TransmitPacketTable;
1823+ SK_LE_TABLE TxALET; /* tx (async) list element table */
1824+ SK_LE_TABLE TxSLET; /* tx (sync) list element table */
1825+ SK_PKT_QUEUE TxQ_free;
1826+ SK_PKT_QUEUE TxAQ_waiting;
1827+ SK_PKT_QUEUE TxSQ_waiting;
1828+ SK_PKT_QUEUE TxAQ_working;
1829+ SK_PKT_QUEUE TxSQ_working;
1830+ unsigned LastDone;
1831 };
1832
1833-typedef struct s_RxPort RX_PORT;
1834-
1835-struct s_RxPort {
1836- /* the receive descriptor rings */
1837- caddr_t pRxDescrRing; /* descriptor area memory */
1838- SK_U64 VRxDescrRing; /* descr. area bus virt. addr. */
1839- RXD *pRxdRingHead; /* Head of Rx rings */
1840- RXD *pRxdRingTail; /* Tail of Rx rings */
1841- RXD *pRxdRingPrev; /* descriptor given to BMU previously */
1842- int RxdRingFree; /* # of free entrys */
1843- int RxCsum; /* use receive checksum hardware */
1844- spinlock_t RxDesRingLock; /* serialize descriptor accesses */
1845- int RxFillLimit; /* limit for buffers in ring */
1846- SK_IOC HwAddr; /* bmu registers address */
1847- int PortIndex; /* index number of port (0 or 1) */
1848+typedef struct s_RxPort RX_PORT;
1849+struct s_RxPort { /* the receive descriptor rings */
1850+ caddr_t pRxDescrRing; /* descriptor area memory */
1851+ SK_U64 VRxDescrRing; /* descr. area bus virt. addr. */
1852+ RXD *pRxdRingHead; /* Head of Rx rings */
1853+ RXD *pRxdRingTail; /* Tail of Rx rings */
1854+ RXD *pRxdRingPrev; /* descr given to BMU previously */
1855+ int RxdRingFree; /* # of free entrys */
1856+ spinlock_t RxDesRingLock; /* serialize descriptor accesses */
1857+ int RxFillLimit; /* limit for buffers in ring */
1858+ caddr_t HwAddr; /* bmu registers address */
1859+ int PortIndex; /* index number of port (0 or 1) */
1860+ SK_BOOL UseRxCsum; /* use Rx checksumming (yes/no) */
1861+ SK_PACKET *ReceivePacketTable;
1862+ SK_LE_TABLE RxLET; /* rx list element table */
1863+ SK_PKT_QUEUE RxQ_working;
1864+ SK_PKT_QUEUE RxQ_waiting;
1865+ int RxBufSize;
1866 };
1867
1868-/* Definitions needed for interrupt moderation *******************************/
1869+/*******************************************************************************
1870+ *
1871+ * Interrupt masks used in combination with interrupt moderation
1872+ *
1873+ ******************************************************************************/
1874
1875 #define IRQ_EOF_AS_TX ((IS_XA1_F) | (IS_XA2_F))
1876 #define IRQ_EOF_SY_TX ((IS_XS1_F) | (IS_XS2_F))
1877@@ -314,134 +732,151 @@
1878 #define IRQ_MASK_SP_TX ((SPECIAL_IRQS) | (IRQ_MASK_TX_ONLY))
1879 #define IRQ_MASK_RX_TX_SP ((SPECIAL_IRQS) | (IRQ_MASK_TX_RX))
1880
1881-#define C_INT_MOD_NONE 1
1882-#define C_INT_MOD_STATIC 2
1883-#define C_INT_MOD_DYNAMIC 4
1884-
1885-#define C_CLK_FREQ_GENESIS 53215000 /* shorter: 53.125 MHz */
1886-#define C_CLK_FREQ_YUKON 78215000 /* shorter: 78.125 MHz */
1887-
1888-#define C_INTS_PER_SEC_DEFAULT 2000
1889-#define C_INT_MOD_ENABLE_PERCENTAGE 50 /* if higher 50% enable */
1890-#define C_INT_MOD_DISABLE_PERCENTAGE 50 /* if lower 50% disable */
1891-#define C_INT_MOD_IPS_LOWER_RANGE 30
1892-#define C_INT_MOD_IPS_UPPER_RANGE 40000
1893-
1894-
1895-typedef struct s_DynIrqModInfo DIM_INFO;
1896-struct s_DynIrqModInfo {
1897- unsigned long PrevTimeVal;
1898- unsigned int PrevSysLoad;
1899- unsigned int PrevUsedTime;
1900- unsigned int PrevTotalTime;
1901- int PrevUsedDescrRatio;
1902- int NbrProcessedDescr;
1903- SK_U64 PrevPort0RxIntrCts;
1904- SK_U64 PrevPort1RxIntrCts;
1905- SK_U64 PrevPort0TxIntrCts;
1906- SK_U64 PrevPort1TxIntrCts;
1907- SK_BOOL ModJustEnabled; /* Moderation just enabled yes/no */
1908-
1909- int MaxModIntsPerSec; /* Moderation Threshold */
1910- int MaxModIntsPerSecUpperLimit; /* Upper limit for DIM */
1911- int MaxModIntsPerSecLowerLimit; /* Lower limit for DIM */
1912-
1913- long MaskIrqModeration; /* ModIrqType (eg. 'TxRx') */
1914- SK_BOOL DisplayStats; /* Stats yes/no */
1915- SK_BOOL AutoSizing; /* Resize DIM-timer on/off */
1916- int IntModTypeSelect; /* EnableIntMod (eg. 'dynamic') */
1917+#define IRQ_MASK_Y2_TX_ONLY (Y2_IS_STAT_BMU)
1918+#define IRQ_MASK_Y2_RX_ONLY (Y2_IS_STAT_BMU)
1919+#define IRQ_MASK_Y2_SP_ONLY (SPECIAL_IRQS)
1920+#define IRQ_MASK_Y2_TX_RX ((IRQ_MASK_TX_ONLY)| (IRQ_MASK_RX_ONLY))
1921+#define IRQ_MASK_Y2_SP_RX ((SPECIAL_IRQS) | (IRQ_MASK_RX_ONLY))
1922+#define IRQ_MASK_Y2_SP_TX ((SPECIAL_IRQS) | (IRQ_MASK_TX_ONLY))
1923+#define IRQ_MASK_Y2_RX_TX_SP ((SPECIAL_IRQS) | (IRQ_MASK_TX_RX))
1924
1925- SK_TIMER ModTimer; /* just some timer */
1926-};
1927+/*******************************************************************************
1928+ *
1929+ * Defines and typedefs regarding interrupt moderation
1930+ *
1931+ ******************************************************************************/
1932
1933-typedef struct s_PerStrm PER_STRM;
1934+#define C_INT_MOD_NONE 1
1935+#define C_INT_MOD_STATIC 2
1936+#define C_INT_MOD_DYNAMIC 4
1937+
1938+#define C_CLK_FREQ_GENESIS 53215000 /* or: 53.125 MHz */
1939+#define C_CLK_FREQ_YUKON 78215000 /* or: 78.125 MHz */
1940+#define C_CLK_FREQ_YUKON_EC 125000000 /* or: 125.000 MHz */
1941+
1942+#define C_Y2_INTS_PER_SEC_DEFAULT 5000
1943+#define C_INTS_PER_SEC_DEFAULT 2000
1944+#define C_INT_MOD_IPS_LOWER_RANGE 30 /* in IRQs/second */
1945+#define C_INT_MOD_IPS_UPPER_RANGE 40000 /* in IRQs/second */
1946+
1947+typedef struct s_DynIrqModInfo {
1948+ SK_U64 PrevPort0RxIntrCts;
1949+ SK_U64 PrevPort1RxIntrCts;
1950+ SK_U64 PrevPort0TxIntrCts;
1951+ SK_U64 PrevPort1TxIntrCts;
1952+ SK_U64 PrevPort0StatusLeIntrCts;
1953+ SK_U64 PrevPort1StatusLeIntrCts;
1954+ int MaxModIntsPerSec; /* Moderation Threshold */
1955+ int MaxModIntsPerSecUpperLimit; /* Upper limit for DIM */
1956+ int MaxModIntsPerSecLowerLimit; /* Lower limit for DIM */
1957+ long MaskIrqModeration; /* IRQ Mask (eg. 'TxRx') */
1958+ int IntModTypeSelect; /* Type (eg. 'dynamic') */
1959+ int DynIrqModSampleInterval; /* expressed in seconds! */
1960+ SK_TIMER ModTimer; /* Timer for dynamic mod. */
1961+} DIM_INFO;
1962
1963-#define SK_ALLOC_IRQ 0x00000001
1964+/*******************************************************************************
1965+ *
1966+ * Defines and typedefs regarding wake-on-lan
1967+ *
1968+ ******************************************************************************/
1969+
1970+typedef struct s_WakeOnLanInfo {
1971+ SK_U32 SupportedWolOptions; /* e.g. WAKE_PHY... */
1972+ SK_U32 ConfiguredWolOptions; /* e.g. WAKE_PHY... */
1973+} WOL_INFO;
1974
1975-#ifdef SK_DIAG_SUPPORT
1976+#define SK_ALLOC_IRQ 0x00000001
1977 #define DIAG_ACTIVE 1
1978 #define DIAG_NOTACTIVE 0
1979-#endif
1980
1981 /****************************************************************************
1982+ *
1983 * Per board structure / Adapter Context structure:
1984- * Allocated within attach(9e) and freed within detach(9e).
1985- * Contains all 'per device' necessary handles, flags, locks etc.:
1986- */
1987+ * Contains all 'per device' necessary handles, flags, locks etc.:
1988+ *
1989+ ******************************************************************************/
1990+
1991 struct s_AC {
1992- SK_GEINIT GIni; /* GE init struct */
1993- SK_PNMI Pnmi; /* PNMI data struct */
1994- SK_VPD vpd; /* vpd data struct */
1995- SK_QUEUE Event; /* Event queue */
1996- SK_HWT Hwt; /* Hardware Timer control struct */
1997- SK_TIMCTRL Tim; /* Software Timer control struct */
1998- SK_I2C I2c; /* I2C relevant data structure */
1999- SK_ADDR Addr; /* for Address module */
2000- SK_CSUM Csum; /* for checksum module */
2001- SK_RLMT Rlmt; /* for rlmt module */
2002- spinlock_t SlowPathLock; /* Normal IRQ lock */
2003- struct timer_list BlinkTimer; /* for LED blinking */
2004- int LedsOn;
2005- SK_PNMI_STRUCT_DATA PnmiStruct; /* structure to get all Pnmi-Data */
2006- int RlmtMode; /* link check mode to set */
2007- int RlmtNets; /* Number of nets */
2008-
2009- SK_IOC IoBase; /* register set of adapter */
2010- int BoardLevel; /* level of active hw init (0-2) */
2011-
2012- SK_U32 AllocFlag; /* flag allocation of resources */
2013- struct pci_dev *PciDev; /* for access to pci config space */
2014- struct SK_NET_DEVICE *dev[2]; /* pointer to device struct */
2015-
2016- int RxBufSize; /* length of receive buffers */
2017- struct net_device_stats stats; /* linux 'netstat -i' statistics */
2018- int Index; /* internal board index number */
2019-
2020- /* adapter RAM sizes for queues of active port */
2021- int RxQueueSize; /* memory used for receive queue */
2022- int TxSQueueSize; /* memory used for sync. tx queue */
2023- int TxAQueueSize; /* memory used for async. tx queue */
2024-
2025- int PromiscCount; /* promiscuous mode counter */
2026- int AllMultiCount; /* allmulticast mode counter */
2027- int MulticCount; /* number of different MC */
2028- /* addresses for this board */
2029- /* (may be more than HW can)*/
2030-
2031- int HWRevision; /* Hardware revision */
2032- int ActivePort; /* the active XMAC port */
2033- int MaxPorts; /* number of activated ports */
2034- int TxDescrPerRing; /* # of descriptors per tx ring */
2035- int RxDescrPerRing; /* # of descriptors per rx ring */
2036-
2037- caddr_t pDescrMem; /* Pointer to the descriptor area */
2038- dma_addr_t pDescrMemDMA; /* PCI DMA address of area */
2039-
2040- /* the port structures with descriptor rings */
2041- TX_PORT TxPort[SK_MAX_MACS][2];
2042- RX_PORT RxPort[SK_MAX_MACS];
2043-
2044- SK_BOOL CheckQueue; /* check event queue soon */
2045- SK_TIMER DrvCleanupTimer;/* to check for pending descriptors */
2046- DIM_INFO DynIrqModInfo; /* all data related to DIM */
2047-
2048- /* Only for tests */
2049- int PortDown;
2050- int ChipsetType; /* Chipset family type
2051- * 0 == Genesis family support
2052- * 1 == Yukon family support
2053- */
2054-#ifdef SK_DIAG_SUPPORT
2055- SK_U32 DiagModeActive; /* is diag active? */
2056- SK_BOOL DiagFlowCtrl; /* for control purposes */
2057- SK_PNMI_STRUCT_DATA PnmiBackup; /* backup structure for all Pnmi-Data */
2058- SK_BOOL WasIfUp[SK_MAX_MACS]; /* for OpenClose while
2059- * DIAG is busy with NIC
2060- */
2061+ SK_GEINIT GIni; /* GE init struct */
2062+ SK_PNMI Pnmi; /* PNMI data struct */
2063+ SK_VPD vpd; /* vpd data struct */
2064+ SK_QUEUE Event; /* Event queue */
2065+ SK_HWT Hwt; /* Hardware Timer ctrl struct */
2066+ SK_TIMCTRL Tim; /* Software Timer ctrl struct */
2067+ SK_I2C I2c; /* I2C relevant data structure*/
2068+ SK_ADDR Addr; /* for Address module */
2069+ SK_CSUM Csum; /* for checksum module */
2070+ SK_RLMT Rlmt; /* for rlmt module */
2071+ spinlock_t SlowPathLock; /* Normal IRQ lock */
2072+ spinlock_t InitLock; /* Init lock */
2073+ spinlock_t TxQueueLock; /* TX Queue lock */
2074+ SK_PNMI_STRUCT_DATA PnmiStruct; /* struct for all Pnmi-Data */
2075+ int RlmtMode; /* link check mode to set */
2076+ int RlmtNets; /* Number of nets */
2077+ SK_IOC IoBase; /* register set of adapter */
2078+ int BoardLevel; /* level of hw init (0-2) */
2079+ char DeviceStr[80]; /* adapter string from vpd */
2080+ SK_U32 AllocFlag; /* alloc flag of resources */
2081+ struct pci_dev *PciDev; /* for access to pci cfg space*/
2082+ SK_U32 PciDevId; /* pci device id */
2083+ struct SK_NET_DEVICE *dev[2]; /* pointer to device struct */
2084+ char Name[30]; /* driver name */
2085+ struct SK_NET_DEVICE *Next; /* link all devs for cleanup */
2086+ struct net_device_stats stats; /* linux 'netstat -i' stats */
2087+ int Index; /* internal board idx number */
2088+ int RxQueueSize; /* memory used for RX queue */
2089+ int TxSQueueSize; /* memory used for TXS queue */
2090+ int TxAQueueSize; /* memory used for TXA queue */
2091+ int PromiscCount; /* promiscuous mode counter */
2092+ int AllMultiCount; /* allmulticast mode counter */
2093+ int MulticCount; /* number of MC addresses used*/
2094+ int HWRevision; /* Hardware revision */
2095+ int ActivePort; /* the active XMAC port */
2096+ int MaxPorts; /* number of activated ports */
2097+ int TxDescrPerRing;/* # of descriptors TX ring */
2098+ int RxDescrPerRing;/* # of descriptors RX ring */
2099+ caddr_t pDescrMem; /* Ptr to the descriptor area */
2100+ dma_addr_t pDescrMemDMA; /* PCI DMA address of area */
2101+ SK_U32 PciState[16]; /* PCI state */
2102+ TX_PORT TxPort[SK_MAX_MACS][2];
2103+ RX_PORT RxPort[SK_MAX_MACS];
2104+ SK_LE_TABLE StatusLETable;
2105+ unsigned SizeOfAlignedLETables;
2106+ spinlock_t SetPutIndexLock;
2107+ int MaxUnusedRxLeWorking;
2108+ unsigned int CsOfs1; /* for checksum calculation */
2109+ unsigned int CsOfs2; /* for checksum calculation */
2110+ SK_U32 CsOfs; /* for checksum calculation */
2111+ SK_BOOL CheckQueue; /* check event queue soon */
2112+ DIM_INFO DynIrqModInfo; /* all data related to IntMod */
2113+ WOL_INFO WolInfo; /* all info regarding WOL */
2114+ int ChipsetType; /* 0=GENESIS; 1=Yukon */
2115+ SK_BOOL LowLatency; /* LowLatency optimization on?*/
2116+ SK_U32 DiagModeActive;/* is diag active? */
2117+ SK_BOOL DiagFlowCtrl; /* for control purposes */
2118+ SK_PNMI_STRUCT_DATA PnmiBackup; /* backup structure for PNMI */
2119+ SK_BOOL WasIfUp[SK_MAX_MACS];
2120+#ifdef USE_TIST_FOR_RESET
2121+ int AdapterResetState;
2122+ SK_U32 MinTistLo;
2123+ SK_U32 MinTistHi;
2124+#endif
2125+#ifdef Y2_RECOVERY
2126+ int LastPort; /* port for curr. handled rx */
2127+ int LastOpc; /* last rx LEs opcode */
2128+#endif
2129+#ifdef Y2_SYNC_CHECK
2130+ unsigned long FramesWithoutSyncCheck; /* since last check */
2131 #endif
2132-
2133 };
2134
2135
2136-#endif /* __INC_SKDRV2ND_H */
2137
2138+#endif
2139+
2140+/*******************************************************************************
2141+ *
2142+ * End of file
2143+ *
2144+ ******************************************************************************/
2145diff -urN linux-2.6.17.orig/drivers/net/sk98lin/h/skerror.h linux-2.6.17/drivers/net/sk98lin/h/skerror.h
2146--- linux-2.6.17.orig/drivers/net/sk98lin/h/skerror.h 2006-06-22 13:17:16.000000000 +0200
2147+++ linux-2.6.17/drivers/net/sk98lin/h/skerror.h 2006-04-27 11:43:44.000000000 +0200
2148@@ -2,23 +2,24 @@
2149 *
2150 * Name: skerror.h
2151 * Project: Gigabit Ethernet Adapters, Common Modules
2152- * Version: $Revision$
2153- * Date: $Date$
2154+ * Version: $Revision$
2155+ * Date: $Date$
2156 * Purpose: SK specific Error log support
2157 *
2158 ******************************************************************************/
2159
2160 /******************************************************************************
2161 *
2162+ * LICENSE:
2163 * (C)Copyright 1998-2002 SysKonnect.
2164- * (C)Copyright 2002-2003 Marvell.
2165+ * (C)Copyright 2002-2004 Marvell.
2166 *
2167 * This program is free software; you can redistribute it and/or modify
2168 * it under the terms of the GNU General Public License as published by
2169 * the Free Software Foundation; either version 2 of the License, or
2170 * (at your option) any later version.
2171- *
2172 * The information in this file is provided "AS IS" without warranty.
2173+ * /LICENSE
2174 *
2175 ******************************************************************************/
2176
2177@@ -36,7 +37,6 @@
2178 #define SK_ERRCL_HW (1L<<4) /* Hardware Failure */
2179 #define SK_ERRCL_COMM (1L<<5) /* Communication error */
2180
2181-
2182 /*
2183 * Define Error Code Bases
2184 */
2185@@ -49,7 +49,9 @@
2186 #define SK_ERRBASE_I2C 700 /* Base Error number for I2C module */
2187 #define SK_ERRBASE_QUEUE 800 /* Base Error number for Scheduler */
2188 #define SK_ERRBASE_ADDR 900 /* Base Error number for Address module */
2189-#define SK_ERRBASE_PECP 1000 /* Base Error number for PECP */
2190+#define SK_ERRBASE_PECP 1000 /* Base Error number for PECP */
2191 #define SK_ERRBASE_DRV 1100 /* Base Error number for Driver */
2192+#define SK_ERRBASE_ASF 1200 /* Base Error number for ASF */
2193
2194 #endif /* _INC_SKERROR_H_ */
2195+
2196diff -urN linux-2.6.17.orig/drivers/net/sk98lin/h/skgedrv.h linux-2.6.17/drivers/net/sk98lin/h/skgedrv.h
2197--- linux-2.6.17.orig/drivers/net/sk98lin/h/skgedrv.h 2006-06-22 13:17:16.000000000 +0200
2198+++ linux-2.6.17/drivers/net/sk98lin/h/skgedrv.h 2006-04-27 11:43:44.000000000 +0200
2199@@ -2,23 +2,24 @@
2200 *
2201 * Name: skgedrv.h
2202 * Project: Gigabit Ethernet Adapters, Common Modules
2203- * Version: $Revision$
2204- * Date: $Date$
2205+ * Version: $Revision$
2206+ * Date: $Date$
2207 * Purpose: Interface with the driver
2208 *
2209 ******************************************************************************/
2210
2211 /******************************************************************************
2212 *
2213+ * LICENSE:
2214 * (C)Copyright 1998-2002 SysKonnect.
2215- * (C)Copyright 2002-2003 Marvell.
2216+ * (C)Copyright 2002-2006 Marvell.
2217 *
2218 * This program is free software; you can redistribute it and/or modify
2219 * it under the terms of the GNU General Public License as published by
2220 * the Free Software Foundation; either version 2 of the License, or
2221 * (at your option) any later version.
2222- *
2223 * The information in this file is provided "AS IS" without warranty.
2224+ * /LICENSE
2225 *
2226 ******************************************************************************/
2227
2228@@ -33,7 +34,7 @@
2229 * In case of the driver we put the definition of the events here.
2230 */
2231 #define SK_DRV_PORT_RESET 1 /* The port needs to be reset */
2232-#define SK_DRV_NET_UP 2 /* The net is operational */
2233+#define SK_DRV_NET_UP 2 /* The net is operational */
2234 #define SK_DRV_NET_DOWN 3 /* The net is down */
2235 #define SK_DRV_SWITCH_SOFT 4 /* Ports switch with both links connected */
2236 #define SK_DRV_SWITCH_HARD 5 /* Port switch due to link failure */
2237@@ -44,8 +45,11 @@
2238 #define SK_DRV_POWER_DOWN 10 /* Power down mode */
2239 #define SK_DRV_TIMER 11 /* Timer for free use */
2240 #ifdef SK_NO_RLMT
2241-#define SK_DRV_LINK_UP 12 /* Link Up event for driver */
2242+#define SK_DRV_LINK_UP 12 /* Link Up event for driver */
2243 #define SK_DRV_LINK_DOWN 13 /* Link Down event for driver */
2244 #endif
2245 #define SK_DRV_DOWNSHIFT_DET 14 /* Downshift 4-Pair / 2-Pair (YUKON only) */
2246+#define SK_DRV_RX_OVERFLOW 15 /* Receive Overflow */
2247+#define SK_DRV_LIPA_NOT_AN_ABLE 16 /* Link Partner not Auto-Negotiation able */
2248+#define SK_DRV_PEX_LINK_WIDTH 17 /* PEX negotiated Link width not maximum */
2249 #endif /* __INC_SKGEDRV_H_ */
2250diff -urN linux-2.6.17.orig/drivers/net/sk98lin/h/skgehw.h linux-2.6.17/drivers/net/sk98lin/h/skgehw.h
2251--- linux-2.6.17.orig/drivers/net/sk98lin/h/skgehw.h 2006-06-22 13:17:16.000000000 +0200
2252+++ linux-2.6.17/drivers/net/sk98lin/h/skgehw.h 2006-04-27 11:43:44.000000000 +0200
2253@@ -2,23 +2,24 @@
2254 *
2255 * Name: skgehw.h
2256 * Project: Gigabit Ethernet Adapters, Common Modules
2257- * Version: $Revision$
2258- * Date: $Date$
2259+ * Version: $Revision$
2260+ * Date: $Date$
2261 * Purpose: Defines and Macros for the Gigabit Ethernet Adapter Product Family
2262 *
2263 ******************************************************************************/
2264
2265 /******************************************************************************
2266 *
2267+ * LICENSE:
2268 * (C)Copyright 1998-2002 SysKonnect.
2269- * (C)Copyright 2002-2003 Marvell.
2270+ * (C)Copyright 2002-2006 Marvell.
2271 *
2272 * This program is free software; you can redistribute it and/or modify
2273 * it under the terms of the GNU General Public License as published by
2274 * the Free Software Foundation; either version 2 of the License, or
2275 * (at your option) any later version.
2276- *
2277 * The information in this file is provided "AS IS" without warranty.
2278+ * /LICENSE
2279 *
2280 ******************************************************************************/
2281
2282@@ -114,6 +115,16 @@
2283 #define SHIFT1(x) ((x) << 1)
2284 #define SHIFT0(x) ((x) << 0)
2285
2286+/* Macro for arbitrary alignment of a given pointer */
2287+#define ALIGN_ADDR( ADDRESS, GRANULARITY ) { \
2288+ SK_UPTR addr = (SK_UPTR)(ADDRESS); \
2289+ if (addr & ((GRANULARITY)-1)) { \
2290+ addr += (GRANULARITY); \
2291+ addr &= ~(SK_UPTR)((GRANULARITY)-1); \
2292+ ADDRESS = (void *)addr; \
2293+ }\
2294+}
2295+
2296 /*
2297 * Configuration Space header
2298 * Since this module is used for different OS', those may be
2299@@ -132,34 +143,81 @@
2300 #define PCI_BIST 0x0f /* 8 bit Built-in selftest */
2301 #define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */
2302 #define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */
2303- /* Byte 0x18..0x2b: reserved */
2304+ /* Bytes 0x18..0x2b: reserved */
2305 #define PCI_SUB_VID 0x2c /* 16 bit Subsystem Vendor ID */
2306 #define PCI_SUB_ID 0x2e /* 16 bit Subsystem ID */
2307 #define PCI_BASE_ROM 0x30 /* 32 bit Expansion ROM Base Address */
2308-#define PCI_CAP_PTR 0x34 /* 8 bit Capabilities Ptr */
2309- /* Byte 0x35..0x3b: reserved */
2310+#define PCI_CAP_PTR 0x34 /* 8 bit Capabilities Pointer */
2311+ /* Bytes 0x35..0x3b: reserved */
2312 #define PCI_IRQ_LINE 0x3c /* 8 bit Interrupt Line */
2313 #define PCI_IRQ_PIN 0x3d /* 8 bit Interrupt Pin */
2314 #define PCI_MIN_GNT 0x3e /* 8 bit Min_Gnt */
2315 #define PCI_MAX_LAT 0x3f /* 8 bit Max_Lat */
2316 /* Device Dependent Region */
2317-#define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */
2318-#define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */
2319+#define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */
2320+#define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */
2321 /* Power Management Region */
2322-#define PCI_PM_CAP_ID 0x48 /* 8 bit Power Management Cap. ID */
2323-#define PCI_PM_NITEM 0x49 /* 8 bit Next Item Ptr */
2324-#define PCI_PM_CAP_REG 0x4a /* 16 bit Power Management Capabilities */
2325-#define PCI_PM_CTL_STS 0x4c /* 16 bit Power Manag. Control/Status */
2326+#define PCI_PM_CAP_ID 0x48 /* 8 bit Power Management Cap. ID */
2327+#define PCI_PM_NITEM 0x49 /* 8 bit PM Next Item Pointer */
2328+#define PCI_PM_CAP_REG 0x4a /* 16 bit Power Management Capabilities */
2329+#define PCI_PM_CTL_STS 0x4c /* 16 bit Power Manag. Control/Status */
2330 /* Byte 0x4e: reserved */
2331-#define PCI_PM_DAT_REG 0x4f /* 8 bit Power Manag. Data Register */
2332+#define PCI_PM_DAT_REG 0x4f /* 8 bit Power Manag. Data Register */
2333 /* VPD Region */
2334-#define PCI_VPD_CAP_ID 0x50 /* 8 bit VPD Cap. ID */
2335-#define PCI_VPD_NITEM 0x51 /* 8 bit Next Item Ptr */
2336-#define PCI_VPD_ADR_REG 0x52 /* 16 bit VPD Address Register */
2337-#define PCI_VPD_DAT_REG 0x54 /* 32 bit VPD Data Register */
2338- /* Byte 0x58..0x59: reserved */
2339-#define PCI_SER_LD_CTRL 0x5a /* 16 bit SEEPROM Loader Ctrl (YUKON only) */
2340- /* Byte 0x5c..0xff: reserved */
2341+#define PCI_VPD_CAP_ID 0x50 /* 8 bit VPD Cap. ID */
2342+#define PCI_VPD_NITEM 0x51 /* 8 bit VPD Next Item Pointer */
2343+#define PCI_VPD_ADR_REG 0x52 /* 16 bit VPD Address Register */
2344+#define PCI_VPD_DAT_REG 0x54 /* 32 bit VPD Data Register */
2345+ /* Bytes 0x58..0x59: reserved */
2346+#define PCI_SER_LD_CTRL 0x5a /* 16 bit SEEPROM Loader Ctrl (YUKON only) */
2347+ /* Bytes 0x5c..0xfc: used by Yukon-2 */
2348+#define PCI_MSI_CAP_ID 0x5c /* 8 bit MSI Capability ID Register */
2349+#define PCI_MSI_NITEM 0x5d /* 8 bit MSI Next Item Pointer */
2350+#define PCI_MSI_CTRL 0x5e /* 16 bit MSI Message Control */
2351+#define PCI_MSI_ADR_LO 0x60 /* 32 bit MSI Message Address (Lower) */
2352+#define PCI_MSI_ADR_HI 0x64 /* 32 bit MSI Message Address (Upper) */
2353+#define PCI_MSI_DATA 0x68 /* 16 bit MSI Message Data */
2354+ /* Bytes 0x6a..0x6b: reserved */
2355+#define PCI_X_CAP_ID 0x6c /* 8 bit PCI-X Capability ID Register */
2356+#define PCI_X_NITEM 0x6d /* 8 bit PCI-X Next Item Pointer */
2357+#define PCI_X_COMMAND 0x6e /* 16 bit PCI-X Command */
2358+#define PCI_X_PE_STAT 0x70 /* 32 bit PCI-X / PE Status */
2359+#define PCI_CAL_CTRL 0x74 /* 16 bit PCI Calibration Control Register */
2360+#define PCI_CAL_STAT 0x76 /* 16 bit PCI Calibration Status Register */
2361+#define PCI_DISC_CNT 0x78 /* 16 bit PCI Discard Counter */
2362+#define PCI_RETRY_CNT 0x7a /* 8 bit PCI Retry Counter */
2363+ /* Byte 0x7b: reserved */
2364+#define PCI_OUR_STATUS 0x7c /* 32 bit Adapter Status Register */
2365+#define PCI_OUR_REG_3 0x80 /* 32 bit Our Register 3 (Yukon-ECU only) */
2366+#define PCI_OUR_REG_4 0x84 /* 32 bit Our Register 4 (Yukon-ECU only) */
2367+#define PCI_OUR_REG_5 0x88 /* 32 bit Our Register 5 (Yukon-ECU only) */
2368+ /* Bytes 0x8c..0xdf: reserved */
2369+
2370+/* PCI Express Capability */
2371+#define PEX_CAP_ID 0xe0 /* 8 bit PEX Capability ID */
2372+#define PEX_NITEM 0xe1 /* 8 bit PEX Next Item Pointer */
2373+#define PEX_CAP_REG 0xe2 /* 16 bit PEX Capability Register */
2374+#define PEX_DEV_CAP 0xe4 /* 32 bit PEX Device Capabilities */
2375+#define PEX_DEV_CTRL 0xe8 /* 16 bit PEX Device Control */
2376+#define PEX_DEV_STAT 0xea /* 16 bit PEX Device Status */
2377+#define PEX_LNK_CAP 0xec /* 32 bit PEX Link Capabilities */
2378+#define PEX_LNK_CTRL 0xf0 /* 16 bit PEX Link Control */
2379+#define PEX_LNK_STAT 0xf2 /* 16 bit PEX Link Status */
2380+ /* Bytes 0xf4..0xff: reserved */
2381+
2382+/* PCI Express Extended Capabilities */
2383+#define PEX_ADV_ERR_REP 0x100 /* 32 bit PEX Advanced Error Reporting */
2384+#define PEX_UNC_ERR_STAT 0x104 /* 32 bit PEX Uncorr. Errors Status */
2385+#define PEX_UNC_ERR_MASK 0x108 /* 32 bit PEX Uncorr. Errors Mask */
2386+#define PEX_UNC_ERR_SEV 0x10c /* 32 bit PEX Uncorr. Errors Severity */
2387+#define PEX_COR_ERR_STAT 0x110 /* 32 bit PEX Correc. Errors Status */
2388+#define PEX_COR_ERR_MASK 0x114 /* 32 bit PEX Correc. Errors Mask */
2389+#define PEX_ADV_ERR_CAP_C 0x118 /* 32 bit PEX Advanced Error Cap./Ctrl */
2390+#define PEX_HEADER_LOG 0x11c /* 4x32 bit PEX Header Log Register */
2391+
2392+/* PCI Express Ack Timer for 1x Link */
2393+#define PEX_ACK_LAT_TOX1 0x228 /* 16 bit PEX Ack Latency Timeout x1 */
2394+#define PEX_ACK_RPLY_TOX1 0x22a /* 16 bit PEX Ack Reply Timeout val x1 */
2395
2396 /*
2397 * I2C Address (PCI Config)
2398@@ -180,13 +238,13 @@
2399 #define PCI_ADSTEP BIT_7S /* Address Stepping */
2400 #define PCI_PERREN BIT_6S /* Parity Report Response enable */
2401 #define PCI_VGA_SNOOP BIT_5S /* VGA palette snoop */
2402-#define PCI_MWIEN BIT_4S /* Memory write an inv cycl ena */
2403+#define PCI_MWIEN BIT_4S /* Memory write an inv cycl enable */
2404 #define PCI_SCYCEN BIT_3S /* Special Cycle enable */
2405 #define PCI_BMEN BIT_2S /* Bus Master enable */
2406 #define PCI_MEMEN BIT_1S /* Memory Space Access enable */
2407 #define PCI_IOEN BIT_0S /* I/O Space Access enable */
2408
2409-#define PCI_COMMAND_VAL (PCI_FBTEN | PCI_SERREN | PCI_PERREN | PCI_MWIEN |\
2410+#define PCI_COMMAND_VAL (PCI_INT_DIS | PCI_SERREN | PCI_PERREN | \
2411 PCI_BMEN | PCI_MEMEN | PCI_IOEN)
2412
2413 /* PCI_STATUS 16 bit Status */
2414@@ -220,7 +278,7 @@
2415
2416 /* PCI_HEADER_T 8 bit Header Type */
2417 #define PCI_HD_MF_DEV BIT_7S /* 0= single, 1= multi-func dev */
2418-#define PCI_HD_TYPE 0x7f /* Bit 6..0: Header Layout 0= normal */
2419+#define PCI_HD_TYPE 0x7f /* Bit 6..0: Header Layout (0=normal) */
2420
2421 /* PCI_BIST 8 bit Built-in selftest */
2422 /* Built-in Self test not supported (optional) */
2423@@ -229,33 +287,42 @@
2424 #define PCI_MEMSIZE 0x4000L /* use 16 kB Memory Base */
2425 #define PCI_MEMBASE_MSK 0xffffc000L /* Bit 31..14: Memory Base Address */
2426 #define PCI_MEMSIZE_MSK 0x00003ff0L /* Bit 13.. 4: Memory Size Req. */
2427-#define PCI_PREFEN BIT_3 /* Prefetchable */
2428-#define PCI_MEM_TYP (3L<<2) /* Bit 2.. 1: Memory Type */
2429+#define PCI_PREFEN BIT_3 /* Prefetch enable */
2430+#define PCI_MEM_TYP_MSK (3L<<1) /* Bit 2.. 1: Memory Type Mask */
2431+#define PCI_MEMSPACE BIT_0 /* Memory Space Indicator */
2432+
2433 #define PCI_MEM32BIT (0L<<1) /* Base addr anywhere in 32 Bit range */
2434 #define PCI_MEM1M (1L<<1) /* Base addr below 1 MegaByte */
2435 #define PCI_MEM64BIT (2L<<1) /* Base addr anywhere in 64 Bit range */
2436-#define PCI_MEMSPACE BIT_0 /* Memory Space Indicator */
2437
2438 /* PCI_BASE_2ND 32 bit 2nd Base address */
2439 #define PCI_IOBASE 0xffffff00L /* Bit 31.. 8: I/O Base address */
2440 #define PCI_IOSIZE 0x000000fcL /* Bit 7.. 2: I/O Size Requirements */
2441- /* Bit 1: reserved */
2442+ /* Bit 1: reserved */
2443 #define PCI_IOSPACE BIT_0 /* I/O Space Indicator */
2444
2445 /* PCI_BASE_ROM 32 bit Expansion ROM Base Address */
2446 #define PCI_ROMBASE_MSK 0xfffe0000L /* Bit 31..17: ROM Base address */
2447 #define PCI_ROMBASE_SIZ (0x1cL<<14) /* Bit 16..14: Treat as Base or Size */
2448 #define PCI_ROMSIZE (0x38L<<11) /* Bit 13..11: ROM Size Requirements */
2449- /* Bit 10.. 1: reserved */
2450+ /* Bit 10.. 1: reserved */
2451 #define PCI_ROMEN BIT_0 /* Address Decode enable */
2452
2453 /* Device Dependent Region */
2454 /* PCI_OUR_REG_1 32 bit Our Register 1 */
2455- /* Bit 31..29: reserved */
2456+ /* Bit 31..29: reserved */
2457 #define PCI_PHY_COMA BIT_28 /* Set PHY to Coma Mode (YUKON only) */
2458 #define PCI_TEST_CAL BIT_27 /* Test PCI buffer calib. (YUKON only) */
2459 #define PCI_EN_CAL BIT_26 /* Enable PCI buffer calib. (YUKON only) */
2460 #define PCI_VIO BIT_25 /* PCI I/O Voltage, 0 = 3.3V, 1 = 5V */
2461+/* Yukon-2 */
2462+#define PCI_Y2_PIG_ENA BIT_31 /* Enable Plug-in-Go (YUKON-2) */
2463+#define PCI_Y2_DLL_DIS BIT_30 /* Disable PCI DLL (YUKON-2) */
2464+#define PCI_Y2_PHY2_COMA BIT_29 /* Set PHY 2 to Coma Mode (YUKON-2) */
2465+#define PCI_Y2_PHY1_COMA BIT_28 /* Set PHY 1 to Coma Mode (YUKON-2) */
2466+#define PCI_Y2_PHY2_POWD BIT_27 /* Set PHY 2 to Power Down (YUKON-2) */
2467+#define PCI_Y2_PHY1_POWD BIT_26 /* Set PHY 1 to Power Down (YUKON-2) */
2468+ /* Bit 25: reserved */
2469 #define PCI_DIS_BOOT BIT_24 /* Disable BOOT via ROM */
2470 #define PCI_EN_IO BIT_23 /* Mapping to I/O space */
2471 #define PCI_EN_FPROM BIT_22 /* Enable FLASH mapping to memory */
2472@@ -266,9 +333,10 @@
2473 #define PCI_PAGE_32K (1L<<20) /* 32 k pages */
2474 #define PCI_PAGE_64K (2L<<20) /* 64 k pages */
2475 #define PCI_PAGE_128K (3L<<20) /* 128 k pages */
2476- /* Bit 19: reserved */
2477-#define PCI_PAGEREG (7L<<16) /* Bit 18..16: Page Register */
2478+ /* Bit 19: reserved */
2479+#define PCI_PAGEREG (7L<<16) /* Bit 18..16: Page Register */
2480 #define PCI_NOTAR BIT_15 /* No turnaround cycle */
2481+#define PCI_PEX_LEGNAT BIT_15 /* PEX PM legacy/native mode (YUKON-2) */
2482 #define PCI_FORCE_BE BIT_14 /* Assert all BEs on MR */
2483 #define PCI_DIS_MRL BIT_13 /* Disable Mem Read Line */
2484 #define PCI_DIS_MRM BIT_12 /* Disable Mem Read Multiple */
2485@@ -278,13 +346,21 @@
2486 #define PCI_DIS_PCI_CLK BIT_8 /* Disable PCI clock driving */
2487 #define PCI_SKEW_DAS (0xfL<<4) /* Bit 7.. 4: Skew Ctrl, DAS Ext */
2488 #define PCI_SKEW_BASE 0xfL /* Bit 3.. 0: Skew Ctrl, Base */
2489+#define PCI_CLS_OPT BIT_3 /* Cache Line Size opt. PCI-X (YUKON-2) */
2490
2491+/* Yukon-EC Ultra only */
2492+ /* Bit 14..10: reserved */
2493+#define PCI_PHY_LNK_TIM_MSK (3L<<8) /* Bit 9.. 8: GPHY Link Trigger Timer */
2494+#define PCI_ENA_L1_EVENT BIT_7 /* Enable PEX L1 Event */
2495+#define PCI_ENA_GPHY_LNK BIT_6 /* Enable PEX L1 on GPHY Link down */
2496+#define PCI_FORCE_PEX_L1 BIT_5 /* Force to PEX L1 */
2497+ /* Bit 4.. 0: reserved */
2498
2499 /* PCI_OUR_REG_2 32 bit Our Register 2 */
2500 #define PCI_VPD_WR_THR (0xffL<<24) /* Bit 31..24: VPD Write Threshold */
2501 #define PCI_DEV_SEL (0x7fL<<17) /* Bit 23..17: EEPROM Device Select */
2502 #define PCI_VPD_ROM_SZ (7L<<14) /* Bit 16..14: VPD ROM Size */
2503- /* Bit 13..12: reserved */
2504+ /* Bit 13..12: reserved */
2505 #define PCI_PATCH_DIR (0xfL<<8) /* Bit 11.. 8: Ext Patches dir 3..0 */
2506 #define PCI_PATCH_DIR_3 BIT_11
2507 #define PCI_PATCH_DIR_2 BIT_10
2508@@ -296,22 +372,21 @@
2509 #define PCI_EXT_PATCH_1 BIT_5
2510 #define PCI_EXT_PATCH_0 BIT_4
2511 #define PCI_EN_DUMMY_RD BIT_3 /* Enable Dummy Read */
2512-#define PCI_REV_DESC BIT_2 /* Reverse Desc. Bytes */
2513- /* Bit 1: reserved */
2514+#define PCI_REV_DESC BIT_2 /* Reverse Descriptor Bytes */
2515+ /* Bit 1: reserved */
2516 #define PCI_USEDATA64 BIT_0 /* Use 64Bit Data bus ext */
2517
2518-
2519-/* Power Management Region */
2520+/* Power Management (PM) Region */
2521 /* PCI_PM_CAP_REG 16 bit Power Management Capabilities */
2522-#define PCI_PME_SUP_MSK (0x1f<<11) /* Bit 15..11: PM Event Support Mask */
2523-#define PCI_PME_D3C_SUP BIT_15S /* PME from D3cold Support (if Vaux) */
2524+#define PCI_PME_SUP_MSK (0x1f<<11) /* Bit 15..11: PM Event (PME) Supp. Mask */
2525+#define PCI_PME_D3C_SUP BIT_15S /* PME from D3cold Support (if VAUX) */
2526 #define PCI_PME_D3H_SUP BIT_14S /* PME from D3hot Support */
2527 #define PCI_PME_D2_SUP BIT_13S /* PME from D2 Support */
2528 #define PCI_PME_D1_SUP BIT_12S /* PME from D1 Support */
2529 #define PCI_PME_D0_SUP BIT_11S /* PME from D0 Support */
2530 #define PCI_PM_D2_SUP BIT_10S /* D2 Support in 33 MHz mode */
2531 #define PCI_PM_D1_SUP BIT_9S /* D1 Support */
2532- /* Bit 8.. 6: reserved */
2533+ /* Bit 8.. 6: reserved */
2534 #define PCI_PM_DSI BIT_5S /* Device Specific Initialization */
2535 #define PCI_PM_APS BIT_4S /* Auxialiary Power Source */
2536 #define PCI_PME_CLOCK BIT_3S /* PM Event Clock */
2537@@ -322,7 +397,7 @@
2538 #define PCI_PM_DAT_SCL (3<<13) /* Bit 14..13: Data Reg. scaling factor */
2539 #define PCI_PM_DAT_SEL (0xf<<9) /* Bit 12.. 9: PM data selector field */
2540 #define PCI_PME_EN BIT_8S /* Enable PME# generation (YUKON only) */
2541- /* Bit 7.. 2: reserved */
2542+ /* Bit 7.. 2: reserved */
2543 #define PCI_PM_STATE_MSK 3 /* Bit 1.. 0: Power Management State */
2544
2545 #define PCI_PM_STATE_D0 0 /* D0: Operational (default) */
2546@@ -333,7 +408,151 @@
2547 /* VPD Region */
2548 /* PCI_VPD_ADR_REG 16 bit VPD Address Register */
2549 #define PCI_VPD_FLAG BIT_15S /* starts VPD rd/wr cycle */
2550-#define PCI_VPD_ADR_MSK 0x7fffL /* Bit 14.. 0: VPD address mask */
2551+#define PCI_VPD_ADR_MSK 0x7fffL /* Bit 14.. 0: VPD Address Mask */
2552+
2553+/* PCI_OUR_STATUS 32 bit Adapter Status Register (Yukon-2) */
2554+#define PCI_OS_PCI64B BIT_31 /* Conventional PCI 64 bits Bus */
2555+#define PCI_OS_PCIX BIT_30 /* PCI-X Bus */
2556+#define PCI_OS_MODE_MSK (3L<<28) /* Bit 29..28: PCI-X Bus Mode Mask */
2557+#define PCI_OS_PCI66M BIT_27 /* PCI 66 MHz Bus */
2558+#define PCI_OS_PCI_X BIT_26 /* PCI/PCI-X Bus (0 = PEX) */
2559+#define PCI_OS_DLLE_MSK (3L<<24) /* Bit 25..24: DLL Status Indication */
2560+#define PCI_OS_DLLR_MSK (0xfL<<20) /* Bit 23..20: DLL Row Counters Values */
2561+#define PCI_OS_DLLC_MSK (0xfL<<16) /* Bit 19..16: DLL Col. Counters Values */
2562+ /* Bit 15.. 8: reserved */
2563+
2564+#define PCI_OS_SPEED(val) ((val & PCI_OS_MODE_MSK) >> 28) /* PCI-X Speed */
2565+/* possible values for the speed field of the register */
2566+#define PCI_OS_SPD_PCI 0 /* PCI Conventional Bus */
2567+#define PCI_OS_SPD_X66 1 /* PCI-X 66MHz Bus */
2568+#define PCI_OS_SPD_X100 2 /* PCI-X 100MHz Bus */
2569+#define PCI_OS_SPD_X133 3 /* PCI-X 133MHz Bus */
2570+
2571+/* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */
2572+ /* Bit 31..18: reserved */
2573+#define P_CLK_COR_REGS_D0_DIS BIT_17 /* Disable Clock Core Regs in D0 */
2574+#define P_CLK_PCI_REGS_D0_DIS BIT_16 /* Disable Clock PCI Regs in D0 */
2575+#define P_CLK_COR_YTB_ARB_DIS BIT_15 /* Disable Clock YTB Arbiter */
2576+#define P_CLK_MAC_LNK1_D3_DIS BIT_14 /* Disable Clock MAC Link1 in D3 */
2577+#define P_CLK_COR_LNK1_D0_DIS BIT_13 /* Disable Clock Core Link1 in D0 */
2578+#define P_CLK_MAC_LNK1_D0_DIS BIT_12 /* Disable Clock MAC Link1 in D0 */
2579+#define P_CLK_COR_LNK1_D3_DIS BIT_11 /* Disable Clock Core Link1 in D3 */
2580+#define P_CLK_PCI_MST_ARB_DIS BIT_10 /* Disable Clock PCI Master Arb. */
2581+#define P_CLK_COR_REGS_D3_DIS BIT_9 /* Disable Clock Core Regs in D3 */
2582+#define P_CLK_PCI_REGS_D3_DIS BIT_8 /* Disable Clock PCI Regs in D3 */
2583+#define P_CLK_REF_LNK1_GM_DIS BIT_7 /* Disable Clock Ref. Link1 GMAC */
2584+#define P_CLK_COR_LNK1_GM_DIS BIT_6 /* Disable Clock Core Link1 GMAC */
2585+#define P_CLK_PCI_COMMON_DIS BIT_5 /* Disable Clock PCI Common */
2586+#define P_CLK_COR_COMMON_DIS BIT_4 /* Disable Clock Core Common */
2587+#define P_CLK_PCI_LNK1_BMU_DIS BIT_3 /* Disable Clock PCI Link1 BMU */
2588+#define P_CLK_COR_LNK1_BMU_DIS BIT_2 /* Disable Clock Core Link1 BMU */
2589+#define P_CLK_PCI_LNK1_BIU_DIS BIT_1 /* Disable Clock PCI Link1 BIU */
2590+#define P_CLK_COR_LNK1_BIU_DIS BIT_0 /* Disable Clock Core Link1 BIU */
2591+
2592+/* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
2593+#define P_PEX_LTSSM_STAT_MSK (0x7fL<<25) /* Bit 31..25: PEX LTSSM Mask */
2594+ /* (Link Training & Status State Machine) */
2595+ /* Bit 24: reserved */
2596+#define P_TIMER_VALUE_MSK (0xffL<<16) /* Bit 23..16: Timer Value Mask */
2597+#define P_FORCE_ASPM_REQUEST BIT_15 /* Force ASPM Request (A1 only) */
2598+ /* (Active State Power Management) */
2599+ /* Bit 14..12: Force ASPM on Event */
2600+#define P_ASPM_GPHY_LINK_DOWN BIT_14 /* GPHY Link Down (A1 only) */
2601+#define P_ASPM_INT_FIFO_EMPTY BIT_13 /* Internal FIFO Empty (A1 only) */
2602+#define P_ASPM_CLKRUN_REQUEST BIT_12 /* CLKRUN Request (A1 only) */
2603+ /* Bit 11.. 8: reserved */
2604+#define P_ASPM_FORCE_ASPM_L1 BIT_7 /* Force ASPM L1 Enable (A1b only) */
2605+#define P_ASPM_FORCE_ASPM_L0S BIT_6 /* Force ASPM L0s Enable (A1b only) */
2606+#define P_ASPM_FORCE_CLKREQ_PIN BIT_5 /* Force CLKREQn pin low (A1b only) */
2607+#define P_ASPM_FORCE_CLKREQ_ENA BIT_4 /* Force CLKREQ Enable (A1b only) */
2608+#define P_ASPM_CLKREQ_PAD_CTL BIT_3 /* CLKREQ PAD Control (A1 only) */
2609+#define P_ASPM_A1_MODE_SELECT BIT_2 /* A1 Mode Select (A1 only) */
2610+#define P_CLK_GATE_PEX_UNIT_ENA BIT_1 /* Enable Gate PEX Unit Clock */
2611+#define P_CLK_GATE_ROOT_COR_ENA BIT_0 /* Enable Gate Root Core Clock */
2612+
2613+#define P_PEX_LTSSM_STAT(x) (SHIFT25(x) & P_PEX_LTSSM_STAT_MSK)
2614+#define P_PEX_LTSSM_L1_STAT 0x34
2615+#define P_PEX_LTSSM_DET_STAT 0x01
2616+
2617+#define P_ASPM_CONTROL_MSK (P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN | \
2618+ P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY)
2619+
2620+/* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */
2621+ /* Bit 31..27: reserved */
2622+ /* Bit 26..16: Release Clock on Event */
2623+#define P_REL_PCIE_RST_DE_ASS BIT_26 /* PCIe Reset De-Asserted */
2624+#define P_REL_GPHY_REC_PACKET BIT_25 /* GPHY Received Packet */
2625+#define P_REL_INT_FIFO_N_EMPTY BIT_24 /* Internal FIFO Not Empty */
2626+#define P_REL_MAIN_PWR_AVAIL BIT_23 /* Main Power Available */
2627+#define P_REL_CLKRUN_REQ_REL BIT_22 /* CLKRUN Request Release */
2628+#define P_REL_PCIE_RESET_ASS BIT_21 /* PCIe Reset Asserted */
2629+#define P_REL_PME_ASSERTED BIT_20 /* PME Asserted */
2630+#define P_REL_PCIE_EXIT_L1_ST BIT_19 /* PCIe Exit L1 State */
2631+#define P_REL_LOADER_NOT_FIN BIT_18 /* EPROM Loader Not Finished */
2632+#define P_REL_PCIE_RX_EX_IDLE BIT_17 /* PCIe Rx Exit Electrical Idle State */
2633+#define P_REL_GPHY_LINK_UP BIT_16 /* GPHY Link Up */
2634+ /* Bit 15..11: reserved */
2635+ /* Bit 10.. 0: Mask for Gate Clock */
2636+#define P_GAT_PCIE_RST_DE_ASS BIT_10 /* PCIe Reset De-Asserted */
2637+#define P_GAT_GPHY_N_REC_PACKET BIT_9 /* GPHY Not Received Packet */
2638+#define P_GAT_INT_FIFO_EMPTY BIT_8 /* Internal FIFO Empty */
2639+#define P_GAT_MAIN_PWR_N_AVAIL BIT_7 /* Main Power Not Available */
2640+#define P_GAT_CLKRUN_REQ_REL BIT_6 /* CLKRUN Not Requested */
2641+#define P_GAT_PCIE_RESET_ASS BIT_5 /* PCIe Reset Asserted */
2642+#define P_GAT_PME_DE_ASSERTED BIT_4 /* PME De-Asserted */
2643+#define P_GAT_PCIE_ENTER_L1_ST BIT_3 /* PCIe Enter L1 State */
2644+#define P_GAT_LOADER_FINISHED BIT_2 /* EPROM Loader Finished */
2645+#define P_GAT_PCIE_RX_EL_IDLE BIT_1 /* PCIe Rx Electrical Idle State */
2646+#define P_GAT_GPHY_LINK_DOWN BIT_0 /* GPHY Link Down */
2647+
2648+/* PEX_DEV_CTRL 16 bit PEX Device Control (Yukon-2) */
2649+ /* Bit 15 reserved */
2650+#define PEX_DC_MAX_RRS_MSK (7<<12) /* Bit 14..12: Max. Read Request Size */
2651+#define PEX_DC_EN_NO_SNOOP BIT_11S /* Enable No Snoop */
2652+#define PEX_DC_EN_AUX_POW BIT_10S /* Enable AUX Power */
2653+#define PEX_DC_EN_PHANTOM BIT_9S /* Enable Phantom Functions */
2654+#define PEX_DC_EN_EXT_TAG BIT_8S /* Enable Extended Tag Field */
2655+#define PEX_DC_MAX_PLS_MSK (7<<5) /* Bit 7.. 5: Max. Payload Size Mask */
2656+#define PEX_DC_EN_REL_ORD BIT_4S /* Enable Relaxed Ordering */
2657+#define PEX_DC_EN_UNS_RQ_RP BIT_3S /* Enable Unsupported Request Reporting */
2658+#define PEX_DC_EN_FAT_ER_RP BIT_2S /* Enable Fatal Error Reporting */
2659+#define PEX_DC_EN_NFA_ER_RP BIT_1S /* Enable Non-Fatal Error Reporting */
2660+#define PEX_DC_EN_COR_ER_RP BIT_0S /* Enable Correctable Error Reporting */
2661+
2662+#define PEX_DC_MAX_RD_RQ_SIZE(x) (SHIFT12(x) & PEX_DC_MAX_RRS_MSK)
2663+
2664+/* PEX_LNK_CAP 32 bit PEX Link Capabilities */
2665+#define PEX_CAP_MAX_WI_MSK (0x3f<<4) /* Bit 9.. 4: Max. Link Width Mask */
2666+#define PEX_CAP_MAX_SP_MSK 0x0f /* Bit 3.. 0: Max. Link Speed Mask */
2667+
2668+/* PEX_LNK_CTRL 16 bit PEX Link Control (Yukon-2) */
2669+#define PEX_LC_CLK_PM_ENA BIT_8S /* Enable Clock Power Management (CLKREQ) */
2670+
2671+/* PEX_LNK_STAT 16 bit PEX Link Status (Yukon-2) */
2672+ /* Bit 15..13 reserved */
2673+#define PEX_LS_SLOT_CLK_CFG BIT_12S /* Slot Clock Config */
2674+#define PEX_LS_LINK_TRAIN BIT_11S /* Link Training */
2675+#define PEX_LS_TRAIN_ERROR BIT_10S /* Training Error */
2676+#define PEX_LS_LINK_WI_MSK (0x3f<<4) /* Bit 9.. 4: Neg. Link Width Mask */
2677+#define PEX_LS_LINK_SP_MSK 0x0f /* Bit 3.. 0: Link Speed Mask */
2678+
2679+/* PEX_UNC_ERR_STAT 16 bit PEX Uncorrectable Errors Status (Yukon-2) */
2680+ /* Bit 31..21 reserved */
2681+#define PEX_UNSUP_REQ BIT_20 /* Unsupported Request Error */
2682+ /* ECRC Error (not supported) */
2683+#define PEX_MALFOR_TLP BIT_18 /* Malformed TLP */
2684+#define PEX_RX_OV BIT_17 /* Receiver Overflow (not supported) */
2685+#define PEX_UNEXP_COMP BIT_16 /* Unexpected Completion */
2686+ /* Completer Abort (not supported) */
2687+#define PEX_COMP_TO BIT_14 /* Completion Timeout */
2688+#define PEX_FLOW_CTRL_P BIT_13 /* Flow Control Protocol Error */
2689+#define PEX_POIS_TLP BIT_12 /* Poisoned TLP */
2690+ /* Bit 11.. 5: reserved */
2691+#define PEX_DATA_LINK_P BIT_4 /* Data Link Protocol Error */
2692+ /* Bit 3.. 1: reserved */
2693+ /* Training Error (not supported) */
2694+
2695+#define PEX_FATAL_ERRORS (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P)
2696
2697 /* Control Register File (Address Map) */
2698
2699@@ -342,15 +561,21 @@
2700 */
2701 #define B0_RAP 0x0000 /* 8 bit Register Address Port */
2702 /* 0x0001 - 0x0003: reserved */
2703-#define B0_CTST 0x0004 /* 16 bit Control/Status register */
2704-#define B0_LED 0x0006 /* 8 Bit LED register */
2705+#define B0_CTST 0x0004 /* 16 bit Control/Status Register */
2706+#define B0_LED 0x0006 /* 8 Bit LED Register */
2707 #define B0_POWER_CTRL 0x0007 /* 8 Bit Power Control reg (YUKON only) */
2708 #define B0_ISRC 0x0008 /* 32 bit Interrupt Source Register */
2709 #define B0_IMSK 0x000c /* 32 bit Interrupt Mask Register */
2710 #define B0_HWE_ISRC 0x0010 /* 32 bit HW Error Interrupt Src Reg */
2711 #define B0_HWE_IMSK 0x0014 /* 32 bit HW Error Interrupt Mask Reg */
2712-#define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg */
2713- /* 0x001c: reserved */
2714+#define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg 1 */
2715+
2716+/* Special ISR registers (Yukon-2 only) */
2717+#define B0_Y2_SP_ISRC2 0x001c /* 32 bit Special Interrupt Source Reg 2 */
2718+#define B0_Y2_SP_ISRC3 0x0020 /* 32 bit Special Interrupt Source Reg 3 */
2719+#define B0_Y2_SP_EISR 0x0024 /* 32 bit Enter ISR Register */
2720+#define B0_Y2_SP_LISR 0x0028 /* 32 bit Leave ISR Register */
2721+#define B0_Y2_SP_ICR 0x002c /* 32 bit Interrupt Control Register */
2722
2723 /* B0 XMAC 1 registers (GENESIS only) */
2724 #define B0_XM1_IMSK 0x0020 /* 16 bit r/w XMAC 1 Interrupt Mask Register*/
2725@@ -372,7 +597,7 @@
2726 #define B0_XM2_PHY_DATA 0x0054 /* 16 bit r/w XMAC 2 PHY Data Register */
2727 /* 0x0056 - 0x005f: reserved */
2728
2729-/* BMU Control Status Registers */
2730+/* BMU Control Status Registers (Yukon and Genesis) */
2731 #define B0_R1_CSR 0x0060 /* 32 bit BMU Ctrl/Stat Rx Queue 1 */
2732 #define B0_R2_CSR 0x0064 /* 32 bit BMU Ctrl/Stat Rx Queue 2 */
2733 #define B0_XS1_CSR 0x0068 /* 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
2734@@ -390,7 +615,7 @@
2735 /*
2736 * Bank 2
2737 */
2738-/* NA reg = 48 bit Network Address Register, 3x16 or 8x8 bit readable */
2739+/* NA reg = 48 bit Network Address Register, 3x16 or 6x8 bit readable */
2740 #define B2_MAC_1 0x0100 /* NA reg MAC Address 1 */
2741 /* 0x0106 - 0x0107: reserved */
2742 #define B2_MAC_2 0x0108 /* NA reg MAC Address 2 */
2743@@ -400,14 +625,23 @@
2744 #define B2_CONN_TYP 0x0118 /* 8 bit Connector type */
2745 #define B2_PMD_TYP 0x0119 /* 8 bit PMD type */
2746 #define B2_MAC_CFG 0x011a /* 8 bit MAC Configuration / Chip Revision */
2747-#define B2_CHIP_ID 0x011b /* 8 bit Chip Identification Number */
2748- /* Eprom registers are currently of no use */
2749+#define B2_CHIP_ID 0x011b /* 8 bit Chip Identification Number */
2750+ /* Eprom registers */
2751 #define B2_E_0 0x011c /* 8 bit EPROM Byte 0 (ext. SRAM size */
2752+/* Yukon and Genesis */
2753 #define B2_E_1 0x011d /* 8 bit EPROM Byte 1 (PHY type) */
2754 #define B2_E_2 0x011e /* 8 bit EPROM Byte 2 */
2755+/* Yukon-2 */
2756+#define B2_Y2_CLK_GATE 0x011d /* 8 bit Clock Gating (Yukon-2) */
2757+#define B2_Y2_HW_RES 0x011e /* 8 bit HW Resources (Yukon-2) */
2758+
2759 #define B2_E_3 0x011f /* 8 bit EPROM Byte 3 */
2760+
2761+/* Yukon and Genesis */
2762 #define B2_FAR 0x0120 /* 32 bit Flash-Prom Addr Reg/Cnt */
2763 #define B2_FDP 0x0124 /* 8 bit Flash-Prom Data Port */
2764+/* Yukon-2 */
2765+#define B2_Y2_CLK_CTRL 0x0120 /* 32 bit Core Clock Frequency Control */
2766 /* 0x0125 - 0x0127: reserved */
2767 #define B2_LD_CTRL 0x0128 /* 8 bit EPROM loader control register */
2768 #define B2_LD_TEST 0x0129 /* 8 bit EPROM loader test register */
2769@@ -439,6 +673,10 @@
2770 #define B2_BSC_CTRL 0x0178 /* 8 bit Blink Source Counter Control */
2771 #define B2_BSC_STAT 0x0179 /* 8 bit Blink Source Counter Status */
2772 #define B2_BSC_TST 0x017a /* 16 bit Blink Source Counter Test Reg */
2773+
2774+/* Yukon-2 */
2775+#define Y2_PEX_PHY_DATA 0x0170 /* 16 bit PEX PHY Data Register */
2776+#define Y2_PEX_PHY_ADDR 0x0172 /* 16 bit PEX PHY Address Register */
2777 /* 0x017c - 0x017f: reserved */
2778
2779 /*
2780@@ -448,9 +686,14 @@
2781 #define B3_RAM_ADDR 0x0180 /* 32 bit RAM Address, to read or write */
2782 #define B3_RAM_DATA_LO 0x0184 /* 32 bit RAM Data Word (low dWord) */
2783 #define B3_RAM_DATA_HI 0x0188 /* 32 bit RAM Data Word (high dWord) */
2784+#define B3_RAM_PARITY 0x018c /* 8 bit RAM Parity (Yukon-ECU A1) */
2785+
2786+#define SELECT_RAM_BUFFER(rb, addr) (addr | (rb << 6)) /* Yukon-2 only */
2787+
2788 /* 0x018c - 0x018f: reserved */
2789
2790 /* RAM Interface Registers */
2791+/* Yukon-2: use SELECT_RAM_BUFFER() to access the RAM buffer */
2792 /*
2793 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
2794 * not usable in SW. Please notice these are NOT real timeouts, these are
2795@@ -517,8 +760,8 @@
2796 /* 0x01ea - 0x01eb: reserved */
2797 #define B3_PA_TOVAL_TX2 0x01ec /* 16 bit Timeout Val Tx Path MAC 2 */
2798 /* 0x01ee - 0x01ef: reserved */
2799-#define B3_PA_CTRL 0x01f0 /* 16 bit Packet Arbiter Ctrl Register */
2800-#define B3_PA_TEST 0x01f2 /* 16 bit Packet Arbiter Test Register */
2801+#define B3_PA_CTRL 0x01f0 /* 16 bit Packet Arbiter Ctrl Register */
2802+#define B3_PA_TEST 0x01f2 /* 16 bit Packet Arbiter Test Register */
2803 /* 0x01f4 - 0x01ff: reserved */
2804
2805 /*
2806@@ -532,7 +775,16 @@
2807 #define TXA_CTRL 0x0210 /* 8 bit Tx Arbiter Control Register */
2808 #define TXA_TEST 0x0211 /* 8 bit Tx Arbiter Test Register */
2809 #define TXA_STAT 0x0212 /* 8 bit Tx Arbiter Status Register */
2810- /* 0x0213 - 0x027f: reserved */
2811+ /* 0x0213 - 0x021f: reserved */
2812+
2813+ /* RSS key registers for Yukon-2 Family */
2814+#define B4_RSS_KEY 0x0220 /* 4x32 bit RSS Key register (Yukon-2) */
2815+ /* RSS key register offsets */
2816+#define KEY_IDX_0 0 /* offset for location of KEY 0 */
2817+#define KEY_IDX_1 4 /* offset for location of KEY 1 */
2818+#define KEY_IDX_2 8 /* offset for location of KEY 2 */
2819+#define KEY_IDX_3 12 /* offset for location of KEY 3 */
2820+
2821 /* 0x0280 - 0x0292: MAC 2 */
2822 /* 0x0213 - 0x027f: reserved */
2823
2824@@ -556,10 +808,10 @@
2825
2826 /* Queue Register Offsets, use Q_ADDR() to access */
2827 #define Q_D 0x00 /* 8*32 bit Current Descriptor */
2828-#define Q_DA_L 0x20 /* 32 bit Current Descriptor Address Low dWord */
2829-#define Q_DA_H 0x24 /* 32 bit Current Descriptor Address High dWord */
2830-#define Q_AC_L 0x28 /* 32 bit Current Address Counter Low dWord */
2831-#define Q_AC_H 0x2c /* 32 bit Current Address Counter High dWord */
2832+#define Q_DA_L 0x20 /* 32 bit Current Descriptor Address Low DWord */
2833+#define Q_DA_H 0x24 /* 32 bit Current Descriptor Address High DWord */
2834+#define Q_AC_L 0x28 /* 32 bit Current Address Counter Low DWord */
2835+#define Q_AC_H 0x2c /* 32 bit Current Address Counter High DWord */
2836 #define Q_BC 0x30 /* 32 bit Current Byte Counter */
2837 #define Q_CSR 0x34 /* 32 bit BMU Control/Status Register */
2838 #define Q_F 0x38 /* 32 bit Flag Register */
2839@@ -570,8 +822,56 @@
2840 #define Q_T1_SV 0x3f /* 8 bit Test Register 1 Supervisor SM */
2841 #define Q_T2 0x40 /* 32 bit Test Register 2 */
2842 #define Q_T3 0x44 /* 32 bit Test Register 3 */
2843+
2844+/* Yukon-2 */
2845+#define Q_DONE 0x24 /* 16 bit Done Index */
2846+
2847+#define Q_WM 0x40 /* 16 bit FIFO Watermark */
2848+#define Q_AL 0x42 /* 8 bit FIFO Alignment */
2849+ /* 0x43: reserved */
2850+/* RX Queue */
2851+#define Q_RX_RSP 0x44 /* 16 bit FIFO Read Shadow Pointer */
2852+#define Q_RX_RSL 0x46 /* 8 bit FIFO Read Shadow Level */
2853+ /* 0x47: reserved */
2854+#define Q_RX_RP 0x48 /* 8 bit FIFO Read Pointer */
2855+ /* 0x49: reserved */
2856+#define Q_RX_RL 0x4a /* 8 bit FIFO Read Level */
2857+ /* 0x4b: reserved */
2858+#define Q_RX_WP 0x4c /* 8 bit FIFO Write Pointer */
2859+#define Q_RX_WSP 0x4d /* 8 bit FIFO Write Shadow Pointer */
2860+#define Q_RX_WL 0x4e /* 8 bit FIFO Write Level */
2861+#define Q_RX_WSL 0x4f /* 8 bit FIFO Write Shadow Level */
2862+/* TX Queue */
2863+#define Q_TX_WSP 0x44 /* 16 bit FIFO Write Shadow Pointer */
2864+#define Q_TX_WSL 0x46 /* 8 bit FIFO Write Shadow Level */
2865+ /* 0x47: reserved */
2866+#define Q_TX_WP 0x48 /* 8 bit FIFO Write Pointer */
2867+ /* 0x49: reserved */
2868+#define Q_TX_WL 0x4a /* 8 bit FIFO Write Level */
2869+ /* 0x4b: reserved */
2870+#define Q_TX_RP 0x4c /* 8 bit FIFO Read Pointer */
2871+ /* 0x4d: reserved */
2872+#define Q_TX_RL 0x4e /* 8 bit FIFO Read Level */
2873+ /* 0x4f: reserved */
2874+
2875 /* 0x48 - 0x7f: reserved */
2876
2877+/* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/
2878+#define Y2_B8_PREF_REGS 0x0450
2879+
2880+#define PREF_UNIT_CTRL_REG 0x00 /* 32 bit Prefetch Control register */
2881+#define PREF_UNIT_LAST_IDX_REG 0x04 /* 16 bit Last Index */
2882+#define PREF_UNIT_ADDR_LOW_REG 0x08 /* 32 bit List start addr, low part */
2883+#define PREF_UNIT_ADDR_HI_REG 0x0c /* 32 bit List start addr, high part*/
2884+#define PREF_UNIT_GET_IDX_REG 0x10 /* 16 bit Get Index */
2885+#define PREF_UNIT_PUT_IDX_REG 0x14 /* 16 bit Put Index */
2886+#define PREF_UNIT_FIFO_WP_REG 0x20 /* 8 bit FIFO write pointer */
2887+#define PREF_UNIT_FIFO_RP_REG 0x24 /* 8 bit FIFO read pointer */
2888+#define PREF_UNIT_FIFO_WM_REG 0x28 /* 8 bit FIFO watermark */
2889+#define PREF_UNIT_FIFO_LEV_REG 0x2c /* 8 bit FIFO level */
2890+
2891+#define PREF_UNIT_MASK_IDX 0x0fff
2892+
2893 /*
2894 * Bank 16 - 23
2895 */
2896@@ -583,17 +883,17 @@
2897 #define RB_END 0x04 /* 32 bit RAM Buffer End Address */
2898 #define RB_WP 0x08 /* 32 bit RAM Buffer Write Pointer */
2899 #define RB_RP 0x0c /* 32 bit RAM Buffer Read Pointer */
2900-#define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Pack */
2901-#define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Pack */
2902+#define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Packet */
2903+#define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Packet */
2904 #define RB_RX_UTHP 0x18 /* 32 bit Rx Upper Threshold, High Prio */
2905 #define RB_RX_LTHP 0x1c /* 32 bit Rx Lower Threshold, High Prio */
2906 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
2907 #define RB_PC 0x20 /* 32 bit RAM Buffer Packet Counter */
2908 #define RB_LEV 0x24 /* 32 bit RAM Buffer Level Register */
2909-#define RB_CTRL 0x28 /* 8 bit RAM Buffer Control Register */
2910+#define RB_CTRL 0x28 /* 32 bit RAM Buffer Control Register */
2911 #define RB_TST1 0x29 /* 8 bit RAM Buffer Test Register 1 */
2912-#define RB_TST2 0x2A /* 8 bit RAM Buffer Test Register 2 */
2913- /* 0x2c - 0x7f: reserved */
2914+#define RB_TST2 0x2a /* 8 bit RAM Buffer Test Register 2 */
2915+ /* 0x2b - 0x7f: reserved */
2916
2917 /*
2918 * Bank 24
2919@@ -603,7 +903,7 @@
2920 * use MR_ADDR() to access
2921 */
2922 #define RX_MFF_EA 0x0c00 /* 32 bit Receive MAC FIFO End Address */
2923-#define RX_MFF_WP 0x0c04 /* 32 bit Receive MAC FIFO Write Pointer */
2924+#define RX_MFF_WP 0x0c04 /* 32 bit Receive MAC FIFO Write Pointer */
2925 /* 0x0c08 - 0x0c0b: reserved */
2926 #define RX_MFF_RP 0x0c0c /* 32 bit Receive MAC FIFO Read Pointer */
2927 #define RX_MFF_PC 0x0c10 /* 32 bit Receive MAC FIFO Packet Cnt */
2928@@ -628,20 +928,23 @@
2929 #define LNK_LED_REG 0x0c3c /* 8 bit Link LED Register */
2930 /* 0x0c3d - 0x0c3f: reserved */
2931
2932-/* Receive GMAC FIFO (YUKON only), use MR_ADDR() to access */
2933+/* Receive GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
2934 #define RX_GMF_EA 0x0c40 /* 32 bit Rx GMAC FIFO End Address */
2935 #define RX_GMF_AF_THR 0x0c44 /* 32 bit Rx GMAC FIFO Almost Full Thresh. */
2936 #define RX_GMF_CTRL_T 0x0c48 /* 32 bit Rx GMAC FIFO Control/Test */
2937 #define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */
2938 #define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */
2939- /* 0x0c54 - 0x0c5f: reserved */
2940-#define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */
2941+#define RX_GMF_TR_THR 0x0c54 /* 32 bit Rx Truncation Threshold (Yukon-2) */
2942+#define RX_GMF_UP_THR 0x0c58 /* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */
2943+#define RX_GMF_LP_THR 0x0c5a /* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */
2944+#define RX_GMF_VLAN 0x0c5c /* 32 bit Rx VLAN Type Register (Yukon-2) */
2945+#define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */
2946 /* 0x0c64 - 0x0c67: reserved */
2947-#define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */
2948+#define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */
2949 /* 0x0c6c - 0x0c6f: reserved */
2950-#define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */
2951+#define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */
2952 /* 0x0c74 - 0x0c77: reserved */
2953-#define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */
2954+#define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */
2955 /* 0x0c7c - 0x0c7f: reserved */
2956
2957 /*
2958@@ -658,7 +961,7 @@
2959 * use MR_ADDR() to access
2960 */
2961 #define TX_MFF_EA 0x0d00 /* 32 bit Transmit MAC FIFO End Address */
2962-#define TX_MFF_WP 0x0d04 /* 32 bit Transmit MAC FIFO WR Pointer */
2963+#define TX_MFF_WP 0x0d04 /* 32 bit Transmit MAC FIFO WR Pointer */
2964 #define TX_MFF_WSP 0x0d08 /* 32 bit Transmit MAC FIFO WR Shadow Ptr */
2965 #define TX_MFF_RP 0x0d0c /* 32 bit Transmit MAC FIFO RD Pointer */
2966 #define TX_MFF_PC 0x0d10 /* 32 bit Transmit MAC FIFO Packet Cnt */
2967@@ -676,18 +979,19 @@
2968 #define TX_LED_TST 0x0d29 /* 8 bit Transmit LED Cnt Test Reg */
2969 /* 0x0d2a - 0x0d3f: reserved */
2970
2971-/* Transmit GMAC FIFO (YUKON only), use MR_ADDR() to access */
2972+/* Transmit GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
2973 #define TX_GMF_EA 0x0d40 /* 32 bit Tx GMAC FIFO End Address */
2974-#define TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
2975+#define TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh. */
2976 #define TX_GMF_CTRL_T 0x0d48 /* 32 bit Tx GMAC FIFO Control/Test */
2977- /* 0x0d4c - 0x0d5f: reserved */
2978-#define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */
2979-#define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
2980-#define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */
2981+ /* 0x0d4c - 0x0d5b: reserved */
2982+#define TX_GMF_VLAN 0x0d5c /* 32 bit Tx VLAN Type Register (Yukon-2) */
2983+#define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */
2984+#define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Pointer */
2985+#define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */
2986 /* 0x0d6c - 0x0d6f: reserved */
2987-#define TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */
2988-#define TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */
2989-#define TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */
2990+#define TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */
2991+#define TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */
2992+#define TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */
2993 /* 0x0d7c - 0x0d7f: reserved */
2994
2995 /*
2996@@ -713,12 +1017,84 @@
2997 #define GMAC_TI_ST_CTRL 0x0e18 /* 8 bit Time Stamp Timer Ctrl Reg */
2998 /* 0x0e19: reserved */
2999 #define GMAC_TI_ST_TST 0x0e1a /* 8 bit Time Stamp Timer Test Reg */
3000- /* 0x0e1b - 0x0e7f: reserved */
3001+ /* 0x0e1b - 0x0e1f: reserved */
3002+
3003+/* Polling Unit Registers (Yukon-2 only) */
3004+#define POLL_CTRL 0x0e20 /* 32 bit Polling Unit Control Reg */
3005+#define POLL_LAST_IDX 0x0e24 /* 16 bit Polling Unit List Last Index */
3006+ /* 0x0e26 - 0x0e27: reserved */
3007+#define POLL_LIST_ADDR_LO 0x0e28 /* 32 bit Poll. List Start Addr (low) */
3008+#define POLL_LIST_ADDR_HI 0x0e2c /* 32 bit Poll. List Start Addr (high) */
3009+ /* 0x0e30 - 0x0e3f: reserved */
3010+
3011+/* ASF Subsystem Registers (Yukon-2 only) */
3012+#define B28_Y2_SMB_CONFIG 0x0e40 /* 32 bit ASF SMBus Config Register */
3013+#define B28_Y2_SMB_CSD_REG 0x0e44 /* 32 bit ASF SMB Control/Status/Data */
3014+ /* 0x0e48 - 0x0e5f: reserved */
3015+#define B28_Y2_ASF_IRQ_V_BASE 0x0e60 /* 32 bit ASF IRQ Vector Base */
3016+ /* 0x0e64 - 0x0e67: reserved */
3017+#define B28_Y2_ASF_STAT_CMD 0x0e68 /* 32 bit ASF Status and Command Reg */
3018+#define B28_Y2_ASF_HOST_COM 0x0e6c /* 32 bit ASF Host Communication Reg */
3019+#define B28_Y2_DATA_REG_1 0x0e70 /* 32 bit ASF/Host Data Register 1 */
3020+#define B28_Y2_DATA_REG_2 0x0e74 /* 32 bit ASF/Host Data Register 2 */
3021+#define B28_Y2_DATA_REG_3 0x0e78 /* 32 bit ASF/Host Data Register 3 */
3022+#define B28_Y2_DATA_REG_4 0x0e7c /* 32 bit ASF/Host Data Register 4 */
3023
3024 /*
3025 * Bank 29
3026 */
3027- /* 0x0e80 - 0x0efc: reserved */
3028+
3029+/* Status BMU Registers (Yukon-2 only)*/
3030+#define STAT_CTRL 0x0e80 /* 32 bit Status BMU Control Reg */
3031+#define STAT_LAST_IDX 0x0e84 /* 16 bit Status BMU Last Index */
3032+ /* 0x0e85 - 0x0e86: reserved */
3033+#define STAT_LIST_ADDR_LO 0x0e88 /* 32 bit Status List Start Addr (low) */
3034+#define STAT_LIST_ADDR_HI 0x0e8c /* 32 bit Status List Start Addr (high) */
3035+#define STAT_TXA1_RIDX 0x0e90 /* 16 bit Status TxA1 Report Index Reg */
3036+#define STAT_TXS1_RIDX 0x0e92 /* 16 bit Status TxS1 Report Index Reg */
3037+#define STAT_TXA2_RIDX 0x0e94 /* 16 bit Status TxA2 Report Index Reg */
3038+#define STAT_TXS2_RIDX 0x0e96 /* 16 bit Status TxS2 Report Index Reg */
3039+#define STAT_TX_IDX_TH 0x0e98 /* 16 bit Status Tx Index Threshold Reg */
3040+ /* 0x0e9a - 0x0e9b: reserved */
3041+#define STAT_PUT_IDX 0x0e9c /* 16 bit Status Put Index Reg */
3042+ /* 0x0e9e - 0x0e9f: reserved */
3043+
3044+/* FIFO Control/Status Registers (Yukon-2 only) */
3045+#define STAT_FIFO_WP 0x0ea0 /* 8 bit Status FIFO Write Pointer Reg */
3046+ /* 0x0ea1 - 0x0ea3: reserved */
3047+#define STAT_FIFO_RP 0x0ea4 /* 8 bit Status FIFO Read Pointer Reg */
3048+ /* 0x0ea5: reserved */
3049+#define STAT_FIFO_RSP 0x0ea6 /* 8 bit Status FIFO Read Shadow Ptr */
3050+ /* 0x0ea7: reserved */
3051+#define STAT_FIFO_LEVEL 0x0ea8 /* 8 bit Status FIFO Level Reg */
3052+ /* 0x0ea9: reserved */
3053+#define STAT_FIFO_SHLVL 0x0eaa /* 8 bit Status FIFO Shadow Level Reg */
3054+ /* 0x0eab: reserved */
3055+#define STAT_FIFO_WM 0x0eac /* 8 bit Status FIFO Watermark Reg */
3056+#define STAT_FIFO_ISR_WM 0x0ead /* 8 bit Status FIFO ISR Watermark Reg */
3057+ /* 0x0eae - 0x0eaf: reserved */
3058+
3059+/* Level and ISR Timer Registers (Yukon-2 only) */
3060+#define STAT_LEV_TIMER_INI 0x0eb0 /* 32 bit Level Timer Init. Value Reg */
3061+#define STAT_LEV_TIMER_CNT 0x0eb4 /* 32 bit Level Timer Counter Reg */
3062+#define STAT_LEV_TIMER_CTRL 0x0eb8 /* 8 bit Level Timer Control Reg */
3063+#define STAT_LEV_TIMER_TEST 0x0eb9 /* 8 bit Level Timer Test Reg */
3064+ /* 0x0eba - 0x0ebf: reserved */
3065+#define STAT_TX_TIMER_INI 0x0ec0 /* 32 bit Tx Timer Init. Value Reg */
3066+#define STAT_TX_TIMER_CNT 0x0ec4 /* 32 bit Tx Timer Counter Reg */
3067+#define STAT_TX_TIMER_CTRL 0x0ec8 /* 8 bit Tx Timer Control Reg */
3068+#define STAT_TX_TIMER_TEST 0x0ec9 /* 8 bit Tx Timer Test Reg */
3069+ /* 0x0eca - 0x0ecf: reserved */
3070+#define STAT_ISR_TIMER_INI 0x0ed0 /* 32 bit ISR Timer Init. Value Reg */
3071+#define STAT_ISR_TIMER_CNT 0x0ed4 /* 32 bit ISR Timer Counter Reg */
3072+#define STAT_ISR_TIMER_CTRL 0x0ed8 /* 8 bit ISR Timer Control Reg */
3073+#define STAT_ISR_TIMER_TEST 0x0ed9 /* 8 bit ISR Timer Test Reg */
3074+ /* 0x0eda - 0x0eff: reserved */
3075+
3076+#define ST_LAST_IDX_MASK 0x007f /* Last Index Mask */
3077+#define ST_TXRP_IDX_MASK 0x0fff /* Tx Report Index Mask */
3078+#define ST_TXTH_IDX_MASK 0x0fff /* Tx Threshold Index Mask */
3079+#define ST_WM_IDX_MASK 0x3f /* FIFO Watermark Index Mask */
3080
3081 /*
3082 * Bank 30
3083@@ -742,11 +1118,9 @@
3084 #define WOL_MATCH_RES 0x0f23 /* 8 bit WOL Match Result Reg */
3085 #define WOL_MAC_ADDR_LO 0x0f24 /* 32 bit WOL MAC Address Low */
3086 #define WOL_MAC_ADDR_HI 0x0f28 /* 16 bit WOL MAC Address High */
3087-#define WOL_PATT_RPTR 0x0f2c /* 8 bit WOL Pattern Read Ptr */
3088-
3089-/* use this macro to access above registers */
3090-#define WOL_REG(Reg) ((Reg) + (pAC->GIni.GIWolOffs))
3091-
3092+#define WOL_PATT_PME 0x0f2a /* 8 bit WOL PME Match Enable (Yukon-2) */
3093+#define WOL_PATT_ASFM 0x0f2b /* 8 bit WOL ASF Match Enable (Yukon-2) */
3094+#define WOL_PATT_RPTR 0x0f2c /* 8 bit WOL Pattern Read Pointer */
3095
3096 /* WOL Pattern Length Registers (YUKON only) */
3097
3098@@ -764,11 +1138,22 @@
3099 */
3100 /* 0x0f80 - 0x0fff: reserved */
3101
3102+/* WOL registers link 2 */
3103+
3104+/* use this macro to access WOL registers */
3105+#define WOL_REG(Port, Reg) ((Reg) + ((Port)*0x80) + (pAC->GIni.GIWolOffs))
3106+
3107 /*
3108 * Bank 32 - 33
3109 */
3110 #define WOL_PATT_RAM_1 0x1000 /* WOL Pattern RAM Link 1 */
3111+#define WOL_PATT_RAM_2 0x1400 /* WOL Pattern RAM Link 2 */
3112+
3113+/* use this macro to retrieve the pattern ram base address */
3114+#define WOL_PATT_RAM_BASE(Port) (WOL_PATT_RAM_1 + (Port)*0x400)
3115
3116+/* offset to configuration space on Yukon-2 */
3117+#define Y2_CFG_SPC 0x1c00
3118 /*
3119 * Bank 0x22 - 0x3f
3120 */
3121@@ -800,13 +1185,27 @@
3122 */
3123 /* B0_RAP 8 bit Register Address Port */
3124 /* Bit 7: reserved */
3125-#define RAP_RAP 0x3f /* Bit 6..0: 0 = block 0,..,6f = block 6f */
3126+#define RAP_MSK 0x7f /* Bit 6..0: 0 = block 0,..,6f = block 6f */
3127+
3128+/* B0_CTST 24 bit Control/Status register */
3129+ /* Bit 23..18: reserved */
3130+#define Y2_VMAIN_AVAIL BIT_17 /* VMAIN available (YUKON-2 only) */
3131+#define Y2_VAUX_AVAIL BIT_16 /* VAUX available (YUKON-2 only) */
3132+#define Y2_HW_WOL_ON BIT_15S /* HW WOL On (Yukon-EC Ultra A1 only) */
3133+#define Y2_HW_WOL_OFF BIT_14S /* HW WOL Off (Yukon-EC Ultra A1 only) */
3134+#define Y2_ASF_ENABLE BIT_13S /* ASF Unit Enable (YUKON-2 only) */
3135+#define Y2_ASF_DISABLE BIT_12S /* ASF Unit Disable (YUKON-2 only) */
3136+#define Y2_CLK_RUN_ENA BIT_11S /* CLK_RUN Enable (YUKON-2 only) */
3137+#define Y2_CLK_RUN_DIS BIT_10S /* CLK_RUN Disable (YUKON-2 only) */
3138+#define Y2_LED_STAT_ON BIT_9S /* Status LED On (YUKON-2 only) */
3139+#define Y2_LED_STAT_OFF BIT_8S /* Status LED Off (YUKON-2 only) */
3140+ /* Bit 7.. 0: same as below */
3141
3142 /* B0_CTST 16 bit Control/Status register */
3143 /* Bit 15..14: reserved */
3144-#define CS_CLK_RUN_HOT BIT_13S /* CLK_RUN hot m. (YUKON-Lite only) */
3145-#define CS_CLK_RUN_RST BIT_12S /* CLK_RUN reset (YUKON-Lite only) */
3146-#define CS_CLK_RUN_ENA BIT_11S /* CLK_RUN enable (YUKON-Lite only) */
3147+#define CS_CLK_RUN_HOT BIT_13S /* CLK_RUN Hot m. (YUKON-Lite only) */
3148+#define CS_CLK_RUN_RST BIT_12S /* CLK_RUN Reset (YUKON-Lite only) */
3149+#define CS_CLK_RUN_ENA BIT_11S /* CLK_RUN Enable (YUKON-Lite only) */
3150 #define CS_VAUX_AVAIL BIT_10S /* VAUX available (YUKON only) */
3151 #define CS_BUS_CLOCK BIT_9S /* Bus Clock 0/1 = 33/66 MHz */
3152 #define CS_BUS_SLOT_SZ BIT_8S /* Slot Size 0/1 = 32/64 bit slot */
3153@@ -814,26 +1213,27 @@
3154 #define CS_CL_SW_IRQ BIT_6S /* Clear IRQ SW Request */
3155 #define CS_STOP_DONE BIT_5S /* Stop Master is finished */
3156 #define CS_STOP_MAST BIT_4S /* Command Bit to stop the master */
3157-#define CS_MRST_CLR BIT_3S /* Clear Master reset */
3158-#define CS_MRST_SET BIT_2S /* Set Master reset */
3159-#define CS_RST_CLR BIT_1S /* Clear Software reset */
3160-#define CS_RST_SET BIT_0S /* Set Software reset */
3161+#define CS_MRST_CLR BIT_3S /* Clear Master Reset */
3162+#define CS_MRST_SET BIT_2S /* Set Master Reset */
3163+#define CS_RST_CLR BIT_1S /* Clear Software Reset */
3164+#define CS_RST_SET BIT_0S /* Set Software Reset */
3165
3166-/* B0_LED 8 Bit LED register */
3167+/* B0_LED 8 Bit LED register (GENESIS only)*/
3168 /* Bit 7.. 2: reserved */
3169-#define LED_STAT_ON BIT_1S /* Status LED on */
3170-#define LED_STAT_OFF BIT_0S /* Status LED off */
3171+#define LED_STAT_ON BIT_1S /* Status LED On */
3172+#define LED_STAT_OFF BIT_0S /* Status LED Off */
3173
3174 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
3175 #define PC_VAUX_ENA BIT_7 /* Switch VAUX Enable */
3176-#define PC_VAUX_DIS BIT_6 /* Switch VAUX Disable */
3177-#define PC_VCC_ENA BIT_5 /* Switch VCC Enable */
3178-#define PC_VCC_DIS BIT_4 /* Switch VCC Disable */
3179-#define PC_VAUX_ON BIT_3 /* Switch VAUX On */
3180-#define PC_VAUX_OFF BIT_2 /* Switch VAUX Off */
3181-#define PC_VCC_ON BIT_1 /* Switch VCC On */
3182-#define PC_VCC_OFF BIT_0 /* Switch VCC Off */
3183+#define PC_VAUX_DIS BIT_6 /* Switch VAUX Disable */
3184+#define PC_VCC_ENA BIT_5 /* Switch VCC Enable */
3185+#define PC_VCC_DIS BIT_4 /* Switch VCC Disable */
3186+#define PC_VAUX_ON BIT_3 /* Switch VAUX On */
3187+#define PC_VAUX_OFF BIT_2 /* Switch VAUX Off */
3188+#define PC_VCC_ON BIT_1 /* Switch VCC On */
3189+#define PC_VCC_OFF BIT_0 /* Switch VCC Off */
3190
3191+/* Yukon and Genesis */
3192 /* B0_ISRC 32 bit Interrupt Source Register */
3193 /* B0_IMSK 32 bit Interrupt Mask Register */
3194 /* B0_SP_ISRC 32 bit Special Interrupt Source Reg */
3195@@ -879,12 +1279,58 @@
3196 #define IS_XA2_F BIT_1 /* Q_XA2 End of Frame */
3197 #define IS_XA2_C BIT_0 /* Q_XA2 Encoding Error */
3198
3199+/* Yukon-2 */
3200+/* B0_ISRC 32 bit Interrupt Source Register */
3201+/* B0_IMSK 32 bit Interrupt Mask Register */
3202+/* B0_SP_ISRC 32 bit Special Interrupt Source Reg */
3203+/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
3204+/* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */
3205+/* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */
3206+/* B0_Y2_SP_EISR 32 bit Enter ISR Reg */
3207+/* B0_Y2_SP_LISR 32 bit Leave ISR Reg */
3208+#define Y2_IS_PORT_MASK(Port, Mask) ((Mask) << (Port*8))
3209+#define Y2_IS_HW_ERR BIT_31 /* Interrupt HW Error */
3210+#define Y2_IS_STAT_BMU BIT_30 /* Status BMU Interrupt */
3211+#define Y2_IS_ASF BIT_29 /* ASF subsystem Interrupt */
3212+ /* Bit 28: reserved */
3213+#define Y2_IS_POLL_CHK BIT_27 /* Check IRQ from polling unit */
3214+#define Y2_IS_TWSI_RDY BIT_26 /* IRQ on end of TWSI Tx */
3215+#define Y2_IS_IRQ_SW BIT_25 /* SW forced IRQ */
3216+#define Y2_IS_TIMINT BIT_24 /* IRQ from Timer */
3217+ /* Bit 23..16 reserved */
3218+ /* Link 2 Interrupts */
3219+#define Y2_IS_IRQ_PHY2 BIT_12 /* Interrupt from PHY 2 */
3220+#define Y2_IS_IRQ_MAC2 BIT_11 /* Interrupt from MAC 2 */
3221+#define Y2_IS_CHK_RX2 BIT_10 /* Descriptor error Rx 2 */
3222+#define Y2_IS_CHK_TXS2 BIT_9 /* Descriptor error TXS 2 */
3223+#define Y2_IS_CHK_TXA2 BIT_8 /* Descriptor error TXA 2 */
3224+ /* Bit 7.. 5 reserved */
3225+ /* Link 1 interrupts */
3226+#define Y2_IS_IRQ_PHY1 BIT_4 /* Interrupt from PHY 1 */
3227+#define Y2_IS_IRQ_MAC1 BIT_3 /* Interrupt from MAC 1 */
3228+#define Y2_IS_CHK_RX1 BIT_2 /* Descriptor error Rx 1 */
3229+#define Y2_IS_CHK_TXS1 BIT_1 /* Descriptor error TXS 1 */
3230+#define Y2_IS_CHK_TXA1 BIT_0 /* Descriptor error TXA 1 */
3231+
3232+#define Y2_IS_L1_MASK 0x0000001fUL /* IRQ Mask for port 1 */
3233+
3234+#define Y2_IS_L2_MASK 0x00001f00UL /* IRQ Mask for port 2 */
3235+
3236+#define Y2_IS_ALL_MSK 0xef001f1fUL /* All Interrupt bits */
3237+
3238+/* B0_Y2_SP_ICR 32 bit Interrupt Control Register */
3239+ /* Bit 31.. 4: reserved */
3240+#define Y2_IC_ISR_MASK BIT_3 /* ISR mask flag */
3241+#define Y2_IC_ISR_STAT BIT_2 /* ISR status flag */
3242+#define Y2_IC_LEAVE_ISR BIT_1 /* Leave ISR */
3243+#define Y2_IC_ENTER_ISR BIT_0 /* Enter ISR */
3244
3245+/* Yukon and Genesis */
3246 /* B0_HWE_ISRC 32 bit HW Error Interrupt Src Reg */
3247 /* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */
3248 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
3249 #define IS_ERR_MSK 0x00000fffL /* All Error bits */
3250- /* Bit 31..14: reserved */
3251+ /* Bit 31..14: reserved */
3252 #define IS_IRQ_TIST_OV BIT_13 /* Time Stamp Timer Overflow (YUKON only) */
3253 #define IS_IRQ_SENSOR BIT_12 /* IRQ from Sensor (YUKON only) */
3254 #define IS_IRQ_MST_ERR BIT_11 /* IRQ master error detected */
3255@@ -900,6 +1346,43 @@
3256 #define IS_R1_PAR_ERR BIT_1 /* Queue R1 Parity Error */
3257 #define IS_R2_PAR_ERR BIT_0 /* Queue R2 Parity Error */
3258
3259+/* Yukon-2 */
3260+/* B0_HWE_ISRC 32 bit HW Error Interrupt Src Reg */
3261+/* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */
3262+/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
3263+ /* Bit: 31..30 reserved */
3264+#define Y2_IS_TIST_OV BIT_29 /* Time Stamp Timer overflow interrupt */
3265+#define Y2_IS_SENSOR BIT_28 /* Sensor interrupt */
3266+#define Y2_IS_MST_ERR BIT_27 /* Master error interrupt */
3267+#define Y2_IS_IRQ_STAT BIT_26 /* Status exception interrupt */
3268+#define Y2_IS_PCI_EXP BIT_25 /* PCI-Express interrupt */
3269+#define Y2_IS_PCI_NEXP BIT_24 /* Bus Abort detected */
3270+ /* Bit: 23..14 reserved */
3271+ /* Link 2 */
3272+#define Y2_IS_PAR_RD2 BIT_13 /* Read RAM parity error interrupt */
3273+#define Y2_IS_PAR_WR2 BIT_12 /* Write RAM parity error interrupt */
3274+#define Y2_IS_PAR_MAC2 BIT_11 /* MAC hardware fault interrupt */
3275+#define Y2_IS_PAR_RX2 BIT_10 /* Parity Error Rx Queue 2 */
3276+#define Y2_IS_TCP_TXS2 BIT_9 /* TCP length mismatch sync Tx queue IRQ */
3277+#define Y2_IS_TCP_TXA2 BIT_8 /* TCP length mismatch async Tx queue IRQ */
3278+ /* Bit: 9.. 6 reserved */
3279+ /* Link 1 */
3280+#define Y2_IS_PAR_RD1 BIT_5 /* Read RAM parity error interrupt */
3281+#define Y2_IS_PAR_WR1 BIT_4 /* Write RAM parity error interrupt */
3282+#define Y2_IS_PAR_MAC1 BIT_3 /* MAC hardware fault interrupt */
3283+#define Y2_IS_PAR_RX1 BIT_2 /* Parity Error Rx Queue 1 */
3284+#define Y2_IS_TCP_TXS1 BIT_1 /* TCP length mismatch sync Tx queue IRQ */
3285+#define Y2_IS_TCP_TXA1 BIT_0 /* TCP length mismatch async Tx queue IRQ */
3286+
3287+#define Y2_HWE_L1_MASK (Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |\
3288+ Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1)
3289+#define Y2_HWE_L2_MASK (Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |\
3290+ Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2)
3291+
3292+#define Y2_HWE_ALL_MSK (Y2_IS_TIST_OV | /* Y2_IS_SENSOR | */ Y2_IS_MST_ERR |\
3293+ Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP |\
3294+ Y2_HWE_L1_MASK | Y2_HWE_L2_MASK)
3295+
3296 /* B2_CONN_TYP 8 bit Connector type */
3297 /* B2_PMD_TYP 8 bit PMD type */
3298 /* Values of connector and PMD type comply to SysKonnect internal std */
3299@@ -908,19 +1391,75 @@
3300 #define CFG_CHIP_R_MSK (0xf<<4) /* Bit 7.. 4: Chip Revision */
3301 /* Bit 3.. 2: reserved */
3302 #define CFG_DIS_M2_CLK BIT_1S /* Disable Clock for 2nd MAC */
3303-#define CFG_SNG_MAC BIT_0S /* MAC Config: 0=2 MACs / 1=1 MAC*/
3304+#define CFG_SNG_MAC BIT_0S /* MAC Config: 0 = 2 MACs; 1 = 1 MAC */
3305
3306-/* B2_CHIP_ID 8 bit Chip Identification Number */
3307+/* B2_CHIP_ID 8 bit Chip Identification Number */
3308 #define CHIP_ID_GENESIS 0x0a /* Chip ID for GENESIS */
3309 #define CHIP_ID_YUKON 0xb0 /* Chip ID for YUKON */
3310 #define CHIP_ID_YUKON_LITE 0xb1 /* Chip ID for YUKON-Lite (Rev. A1-A3) */
3311 #define CHIP_ID_YUKON_LP 0xb2 /* Chip ID for YUKON-LP */
3312+#define CHIP_ID_YUKON_XL 0xb3 /* Chip ID for YUKON-2 XL */
3313+#define CHIP_ID_YUKON_EC_U 0xb4 /* Chip ID for YUKON-2 EC Ultra */
3314+#define CHIP_ID_YUKON_EC 0xb6 /* Chip ID for YUKON-2 EC */
3315+#define CHIP_ID_YUKON_FE 0xb7 /* Chip ID for YUKON-2 FE */
3316
3317 #define CHIP_REV_YU_LITE_A1 3 /* Chip Rev. for YUKON-Lite A1,A2 */
3318 #define CHIP_REV_YU_LITE_A3 7 /* Chip Rev. for YUKON-Lite A3 */
3319
3320+#define CHIP_REV_YU_XL_A0 0 /* Chip Rev. for Yukon-2 A0 */
3321+#define CHIP_REV_YU_XL_A1 1 /* Chip Rev. for Yukon-2 A1 */
3322+#define CHIP_REV_YU_XL_A2 2 /* Chip Rev. for Yukon-2 A2 */
3323+#define CHIP_REV_YU_XL_A3 3 /* Chip Rev. for Yukon-2 A3 */
3324+
3325+#define CHIP_REV_YU_EC_A1 0 /* Chip Rev. for Yukon-EC A0,A1 */
3326+#define CHIP_REV_YU_EC_A2 1 /* Chip Rev. for Yukon-EC A2 */
3327+#define CHIP_REV_YU_EC_A3 2 /* Chip Rev. for Yukon-EC A3 */
3328+
3329+#define CHIP_REV_YU_EC_U_A0 1 /* Chip Rev. for Yukon-EC Ultra A0 */
3330+#define CHIP_REV_YU_EC_U_A1 2 /* Chip Rev. for Yukon-EC Ultra A1 */
3331+
3332+/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
3333+#define Y2_STATUS_LNK2_INAC BIT_7S /* Status Link 2 inactiv (0 = activ) */
3334+#define Y2_CLK_GAT_LNK2_DIS BIT_6S /* Disable PHY clock for Link 2 */
3335+#define Y2_COR_CLK_LNK2_DIS BIT_5S /* Disable Core clock Link 2 */
3336+#define Y2_PCI_CLK_LNK2_DIS BIT_4S /* Disable PCI clock Link 2 */
3337+#define Y2_STATUS_LNK1_INAC BIT_3S /* Status Link 1 inactiv (0 = activ) */
3338+#define Y2_CLK_GAT_LNK1_DIS BIT_2S /* Disable PHY clock for Link 1 */
3339+#define Y2_COR_CLK_LNK1_DIS BIT_1S /* Disable Core clock Link 1 */
3340+#define Y2_PCI_CLK_LNK1_DIS BIT_0S /* Disable PCI clock Link 1 */
3341+
3342+/* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
3343+ /* Bit 7.. 6: reserved */
3344+#define CFG_PEX_PME_NATIVE BIT_5S /* PCI-E PME native mode select */
3345+#define CFG_LED_MODE_MSK (7<<2) /* Bit 4.. 2: LED Mode Mask */
3346+#define CFG_LINK_2_AVAIL BIT_1S /* Link 2 available */
3347+#define CFG_LINK_1_AVAIL BIT_0S /* Link 1 available */
3348+
3349+#define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2)
3350+#define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)
3351+
3352+#define CFG_LED_DUAL_ACT_LNK 1 /* Dual LED ACT/LNK mode */
3353+#define CFG_LED_LINK_MUX_P60 2 /* Link LED on pin 60 (Yukon-EC Ultra) */
3354+
3355+/* B2_E_3 8 bit lower 4 bits used for HW self test result */
3356+#define B2_E3_RES_MASK 0x0f
3357+
3358 /* B2_FAR 32 bit Flash-Prom Addr Reg/Cnt */
3359-#define FAR_ADDR 0x1ffffL /* Bit 16.. 0: FPROM Address mask */
3360+#define FAR_ADDR 0x1ffffL /* Bit 16.. 0: FPROM Address Mask */
3361+
3362+/* B2_Y2_CLK_CTRL 32 bit Core Clock Frequency Control Register (Yukon-2/EC) */
3363+ /* Bit 31..24: reserved */
3364+/* Yukon-EC/FE */
3365+#define Y2_CLK_DIV_VAL_MSK (0xffL<<16) /* Bit 23..16: Clock Divisor Value */
3366+#define Y2_CLK_DIV_VAL(x) (SHIFT16(x) & Y2_CLK_DIV_VAL_MSK)
3367+/* Yukon-2 */
3368+#define Y2_CLK_DIV_VAL2_MSK (7L<<21) /* Bit 23..21: Clock Divisor Value */
3369+#define Y2_CLK_SELECT2_MSK (0x1fL<<16) /* Bit 20..16: Clock Select */
3370+#define Y2_CLK_DIV_VAL_2(x) (SHIFT21(x) & Y2_CLK_DIV_VAL2_MSK)
3371+#define Y2_CLK_SEL_VAL_2(x) (SHIFT16(x) & Y2_CLK_SELECT2_MSK)
3372+ /* Bit 15.. 2: reserved */
3373+#define Y2_CLK_DIV_ENA BIT_1S /* Enable Core Clock Division */
3374+#define Y2_CLK_DIV_DIS BIT_0S /* Disable Core Clock Division */
3375
3376 /* B2_LD_CTRL 8 bit EPROM loader control register */
3377 /* Bits are currently reserved */
3378@@ -960,9 +1499,6 @@
3379 #define DPT_START BIT_1S /* Start Descriptor Poll Timer */
3380 #define DPT_STOP BIT_0S /* Stop Descriptor Poll Timer */
3381
3382-/* B2_E_3 8 bit lower 4 bits used for HW self test result */
3383-#define B2_E3_RES_MASK 0x0f
3384-
3385 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
3386 #define TST_FRC_DPERR_MR BIT_7S /* force DATAPERR on MST RD */
3387 #define TST_FRC_DPERR_MW BIT_6S /* force DATAPERR on MST WR */
3388@@ -975,14 +1511,14 @@
3389
3390 /* B2_TST_CTRL2 8 bit Test Control Register 2 */
3391 /* Bit 7.. 4: reserved */
3392- /* force the following error on the next master read/write */
3393+ /* force the following error on the next master read/write */
3394 #define TST_FRC_DPERR_MR64 BIT_3S /* DataPERR RD 64 */
3395 #define TST_FRC_DPERR_MW64 BIT_2S /* DataPERR WR 64 */
3396 #define TST_FRC_APERR_1M64 BIT_1S /* AddrPERR on 1. phase */
3397 #define TST_FRC_APERR_2M64 BIT_0S /* AddrPERR on 2. phase */
3398
3399 /* B2_GP_IO 32 bit General Purpose I/O Register */
3400- /* Bit 31..26: reserved */
3401+ /* Bit 31..26: reserved */
3402 #define GP_DIR_9 BIT_25 /* IO_9 direct, 0=In/1=Out */
3403 #define GP_DIR_8 BIT_24 /* IO_8 direct, 0=In/1=Out */
3404 #define GP_DIR_7 BIT_23 /* IO_7 direct, 0=In/1=Out */
3405@@ -1009,15 +1545,15 @@
3406 #define I2C_FLAG BIT_31 /* Start read/write if WR */
3407 #define I2C_ADDR (0x7fffL<<16) /* Bit 30..16: Addr to be RD/WR */
3408 #define I2C_DEV_SEL (0x7fL<<9) /* Bit 15.. 9: I2C Device Select */
3409- /* Bit 8.. 5: reserved */
3410+ /* Bit 8.. 5: reserved */
3411 #define I2C_BURST_LEN BIT_4 /* Burst Len, 1/4 bytes */
3412-#define I2C_DEV_SIZE (7<<1) /* Bit 3.. 1: I2C Device Size */
3413-#define I2C_025K_DEV (0<<1) /* 0: 256 Bytes or smal. */
3414-#define I2C_05K_DEV (1<<1) /* 1: 512 Bytes */
3415-#define I2C_1K_DEV (2<<1) /* 2: 1024 Bytes */
3416-#define I2C_2K_DEV (3<<1) /* 3: 2048 Bytes */
3417-#define I2C_4K_DEV (4<<1) /* 4: 4096 Bytes */
3418-#define I2C_8K_DEV (5<<1) /* 5: 8192 Bytes */
3419+#define I2C_DEV_SIZE (7<<1) /* Bit 3.. 1: I2C Device Size */
3420+#define I2C_025K_DEV (0<<1) /* 0: 256 Bytes or smaller */
3421+#define I2C_05K_DEV (1<<1) /* 1: 512 Bytes */
3422+#define I2C_1K_DEV (2<<1) /* 2: 1024 Bytes */
3423+#define I2C_2K_DEV (3<<1) /* 3: 2048 Bytes */
3424+#define I2C_4K_DEV (4<<1) /* 4: 4096 Bytes */
3425+#define I2C_8K_DEV (5<<1) /* 5: 8192 Bytes */
3426 #define I2C_16K_DEV (6<<1) /* 6: 16384 Bytes */
3427 #define I2C_32K_DEV (7<<1) /* 7: 32768 Bytes */
3428 #define I2C_STOP BIT_0 /* Interrupt I2C transfer */
3429@@ -1026,16 +1562,14 @@
3430 /* Bit 31.. 1 reserved */
3431 #define I2C_CLR_IRQ BIT_0 /* Clear I2C IRQ */
3432
3433-/* B2_I2C_SW 32 bit (8 bit access) I2C HW SW Port Register */
3434+/* B2_I2C_SW 32 bit (8 bit access) I2C SW Port Register */
3435 /* Bit 7.. 3: reserved */
3436 #define I2C_DATA_DIR BIT_2S /* direction of I2C_DATA */
3437-#define I2C_DATA BIT_1S /* I2C Data Port */
3438-#define I2C_CLK BIT_0S /* I2C Clock Port */
3439+#define I2C_DATA BIT_1S /* I2C Data Port */
3440+#define I2C_CLK BIT_0S /* I2C Clock Port */
3441
3442-/*
3443- * I2C Address
3444- */
3445-#define I2C_SENS_ADDR LM80_ADDR /* I2C Sensor Address, (Volt and Temp)*/
3446+/* I2C Address */
3447+#define I2C_SENS_ADDR LM80_ADDR /* I2C Sensor Address (Volt and Temp) */
3448
3449
3450 /* B2_BSC_CTRL 8 bit Blink Source Counter Control */
3451@@ -1052,16 +1586,20 @@
3452 #define BSC_T_OFF BIT_1S /* Test mode off */
3453 #define BSC_T_STEP BIT_0S /* Test step */
3454
3455+/* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */
3456+#define PEX_RD_ACCESS BIT_31 /* Access Mode Read = 1, Write = 0 */
3457+#define PEX_DB_ACCESS BIT_30 /* Access to debug register */
3458+
3459
3460 /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
3461 /* Bit 31..19: reserved */
3462 #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
3463
3464 /* RAM Interface Registers */
3465-/* B3_RI_CTRL 16 bit RAM Iface Control Register */
3466+/* B3_RI_CTRL 16 bit RAM Interface Control Register */
3467 /* Bit 15..10: reserved */
3468-#define RI_CLR_RD_PERR BIT_9S /* Clear IRQ RAM Read Parity Err */
3469-#define RI_CLR_WR_PERR BIT_8S /* Clear IRQ RAM Write Parity Err*/
3470+#define RI_CLR_RD_PERR BIT_9S /* Clear IRQ RAM Read Parity Err */
3471+#define RI_CLR_WR_PERR BIT_8S /* Clear IRQ RAM Write Parity Err */
3472 /* Bit 7.. 2: reserved */
3473 #define RI_RST_CLR BIT_1S /* Clear RAM Interface Reset */
3474 #define RI_RST_SET BIT_0S /* Set RAM Interface Reset */
3475@@ -1171,7 +1709,7 @@
3476 /* Bit 31..16: reserved */
3477 #define BC_MAX 0xffff /* Bit 15.. 0: Byte counter */
3478
3479-/* BMU Control Status Registers */
3480+/* BMU Control / Status Registers (Yukon and Genesis) */
3481 /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
3482 /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
3483 /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
3484@@ -1212,13 +1750,48 @@
3485 CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\
3486 CSR_TRANS_RUN)
3487
3488+/* Rx BMU Control / Status Registers (Yukon-2) */
3489+#define BMU_IDLE BIT_31 /* BMU Idle State */
3490+#define BMU_RX_TCP_PKT BIT_30 /* Rx TCP Packet (when RSS Hash enabled) */
3491+#define BMU_RX_IP_PKT BIT_29 /* Rx IP Packet (when RSS Hash enabled) */
3492+ /* Bit 28..16: reserved */
3493+#define BMU_ENA_RX_RSS_HASH BIT_15 /* Enable Rx RSS Hash */
3494+#define BMU_DIS_RX_RSS_HASH BIT_14 /* Disable Rx RSS Hash */
3495+#define BMU_ENA_RX_CHKSUM BIT_13 /* Enable Rx TCP/IP Checksum Check */
3496+#define BMU_DIS_RX_CHKSUM BIT_12 /* Disable Rx TCP/IP Checksum Check */
3497+#define BMU_CLR_IRQ_PAR BIT_11 /* Clear IRQ on Parity errors (Rx) */
3498+#define BMU_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segmen. error (Tx) */
3499+#define BMU_CLR_IRQ_CHK BIT_10 /* Clear IRQ Check */
3500+#define BMU_STOP BIT_9 /* Stop Rx/Tx Queue */
3501+#define BMU_START BIT_8 /* Start Rx/Tx Queue */
3502+#define BMU_FIFO_OP_ON BIT_7 /* FIFO Operational On */
3503+#define BMU_FIFO_OP_OFF BIT_6 /* FIFO Operational Off */
3504+#define BMU_FIFO_ENA BIT_5 /* Enable FIFO */
3505+#define BMU_FIFO_RST BIT_4 /* Reset FIFO */
3506+#define BMU_OP_ON BIT_3 /* BMU Operational On */
3507+#define BMU_OP_OFF BIT_2 /* BMU Operational Off */
3508+#define BMU_RST_CLR BIT_1 /* Clear BMU Reset (Enable) */
3509+#define BMU_RST_SET BIT_0 /* Set BMU Reset */
3510+
3511+#define BMU_CLR_RESET (BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR)
3512+#define BMU_OPER_INIT (BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START | \
3513+ BMU_FIFO_ENA | BMU_OP_ON)
3514+
3515+/* Tx BMU Control / Status Registers (Yukon-2) */
3516+ /* Bit 31: same as for Rx */
3517+ /* Bit 30..14: reserved */
3518+#define BMU_TX_IPIDINCR_ON BIT_13 /* Enable IP ID Increment */
3519+#define BMU_TX_IPIDINCR_OFF BIT_12 /* Disable IP ID Increment */
3520+#define BMU_TX_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segm. length mism. */
3521+ /* Bit 10..0: same as for Rx */
3522+
3523 /* Q_F 32 bit Flag Register */
3524 /* Bit 31..28: reserved */
3525 #define F_ALM_FULL BIT_27 /* Rx FIFO: almost full */
3526 #define F_EMPTY BIT_27 /* Tx FIFO: empty flag */
3527 #define F_FIFO_EOF BIT_26 /* Tag (EOF Flag) bit in FIFO */
3528 #define F_WM_REACHED BIT_25 /* Watermark reached */
3529- /* reserved */
3530+#define F_M_RX_RAM_DIS BIT_24 /* MAC Rx RAM Read Port disable */
3531 #define F_FIFO_LEVEL (0x1fL<<16) /* Bit 23..16: # of Qwords in FIFO */
3532 /* Bit 15..11: reserved */
3533 #define F_WATER_MARK 0x0007ffL /* Bit 10.. 0: Watermark */
3534@@ -1260,6 +1833,13 @@
3535 /* Bit 3: reserved */
3536 #define T3_VRAM_MSK 7 /* Bit 2.. 0: Virtual RAM Buffer Address */
3537
3538+/* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/
3539+/* PREF_UNIT_CTRL_REG 32 bit Prefetch Control register */
3540+#define PREF_UNIT_OP_ON BIT_3 /* prefetch unit operational */
3541+#define PREF_UNIT_OP_OFF BIT_2 /* prefetch unit not operational */
3542+#define PREF_UNIT_RST_CLR BIT_1 /* Clear Prefetch Unit Reset */
3543+#define PREF_UNIT_RST_SET BIT_0 /* Set Prefetch Unit Reset */
3544+
3545 /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
3546 /* RB_START 32 bit RAM Buffer Start Address */
3547 /* RB_END 32 bit RAM Buffer End Address */
3548@@ -1275,24 +1855,24 @@
3549 #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
3550
3551 /* RB_TST2 8 bit RAM Buffer Test Register 2 */
3552- /* Bit 7.. 4: reserved */
3553-#define RB_PC_DEC BIT_3S /* Packet Counter Decrem */
3554+ /* Bit 7.. 4: reserved */
3555+#define RB_PC_DEC BIT_3S /* Packet Counter Decrement */
3556 #define RB_PC_T_ON BIT_2S /* Packet Counter Test On */
3557-#define RB_PC_T_OFF BIT_1S /* Packet Counter Tst Off */
3558-#define RB_PC_INC BIT_0S /* Packet Counter Increm */
3559+#define RB_PC_T_OFF BIT_1S /* Packet Counter Test Off */
3560+#define RB_PC_INC BIT_0S /* Packet Counter Increment */
3561
3562 /* RB_TST1 8 bit RAM Buffer Test Register 1 */
3563 /* Bit 7: reserved */
3564 #define RB_WP_T_ON BIT_6S /* Write Pointer Test On */
3565 #define RB_WP_T_OFF BIT_5S /* Write Pointer Test Off */
3566-#define RB_WP_INC BIT_4S /* Write Pointer Increm */
3567+#define RB_WP_INC BIT_4S /* Write Pointer Increment */
3568 /* Bit 3: reserved */
3569 #define RB_RP_T_ON BIT_2S /* Read Pointer Test On */
3570 #define RB_RP_T_OFF BIT_1S /* Read Pointer Test Off */
3571-#define RB_RP_DEC BIT_0S /* Read Pointer Decrement */
3572+#define RB_RP_INC BIT_0S /* Read Pointer Increment */
3573
3574 /* RB_CTRL 8 bit RAM Buffer Control Register */
3575- /* Bit 7.. 6: reserved */
3576+ /* Bit 7.. 6: reserved */
3577 #define RB_ENA_STFWD BIT_5S /* Enable Store & Forward */
3578 #define RB_DIS_STFWD BIT_4S /* Disable Store & Forward */
3579 #define RB_ENA_OP_MD BIT_3S /* Enable Operation Mode */
3580@@ -1300,16 +1880,31 @@
3581 #define RB_RST_CLR BIT_1S /* Clear RAM Buf STM Reset */
3582 #define RB_RST_SET BIT_0S /* Set RAM Buf STM Reset */
3583
3584+/* Yukon-2 */
3585+ /* Bit 31..20: reserved */
3586+#define RB_CNT_DOWN BIT_19 /* Packet Counter Decrement */
3587+#define RB_CNT_TST_ON BIT_18 /* Packet Counter Test On */
3588+#define RB_CNT_TST_OFF BIT_17 /* Packet Counter Test Off */
3589+#define RB_CNT_UP BIT_16 /* Packet Counter Increment */
3590+ /* Bit 15: reserved */
3591+#define RB_WP_TST_ON BIT_14 /* Write Pointer Test On */
3592+#define RB_WP_TST_OFF BIT_13 /* Write Pointer Test Off */
3593+#define RB_WP_UP BIT_12 /* Write Pointer Increment */
3594+ /* Bit 11: reserved */
3595+#define RB_RP_TST_ON BIT_10 /* Read Pointer Test On */
3596+#define RB_RP_TST_OFF BIT_9 /* Read Pointer Test Off */
3597+#define RB_RP_UP BIT_8 /* Read Pointer Increment */
3598+
3599
3600 /* Receive and Transmit MAC FIFO Registers (GENESIS only) */
3601
3602 /* RX_MFF_EA 32 bit Receive MAC FIFO End Address */
3603-/* RX_MFF_WP 32 bit Receive MAC FIFO Write Pointer */
3604+/* RX_MFF_WP 32 bit Receive MAC FIFO Write Pointer */
3605 /* RX_MFF_RP 32 bit Receive MAC FIFO Read Pointer */
3606 /* RX_MFF_PC 32 bit Receive MAC FIFO Packet Counter */
3607 /* RX_MFF_LEV 32 bit Receive MAC FIFO Level */
3608 /* TX_MFF_EA 32 bit Transmit MAC FIFO End Address */
3609-/* TX_MFF_WP 32 bit Transmit MAC FIFO Write Pointer */
3610+/* TX_MFF_WP 32 bit Transmit MAC FIFO Write Pointer */
3611 /* TX_MFF_WSP 32 bit Transmit MAC FIFO WR Shadow Pointer */
3612 /* TX_MFF_RP 32 bit Transmit MAC FIFO Read Pointer */
3613 /* TX_MFF_PC 32 bit Transmit MAC FIFO Packet Cnt */
3614@@ -1359,9 +1954,9 @@
3615 /* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */
3616 /* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */
3617 /* Bit 7: reserved */
3618-#define MFF_WSP_T_ON BIT_6S /* Tx: Write Shadow Ptr TestOn */
3619-#define MFF_WSP_T_OFF BIT_5S /* Tx: Write Shadow Ptr TstOff */
3620-#define MFF_WSP_INC BIT_4S /* Tx: Write Shadow Ptr Increment */
3621+#define MFF_WSP_T_ON BIT_6S /* Tx: Write Shadow Pointer Test On */
3622+#define MFF_WSP_T_OFF BIT_5S /* Tx: Write Shadow Pointer Test Off */
3623+#define MFF_WSP_INC BIT_4S /* Tx: Write Shadow Pointer Increment */
3624 #define MFF_PC_DEC BIT_3S /* Packet Counter Decrement */
3625 #define MFF_PC_T_ON BIT_2S /* Packet Counter Test On */
3626 #define MFF_PC_T_OFF BIT_1S /* Packet Counter Test Off */
3627@@ -1372,7 +1967,7 @@
3628 /* Bit 7: reserved */
3629 #define MFF_WP_T_ON BIT_6S /* Write Pointer Test On */
3630 #define MFF_WP_T_OFF BIT_5S /* Write Pointer Test Off */
3631-#define MFF_WP_INC BIT_4S /* Write Pointer Increm */
3632+#define MFF_WP_INC BIT_4S /* Write Pointer Increment */
3633 /* Bit 3: reserved */
3634 #define MFF_RP_T_ON BIT_2S /* Read Pointer Test On */
3635 #define MFF_RP_T_OFF BIT_1S /* Read Pointer Test Off */
3636@@ -1391,12 +1986,16 @@
3637
3638 /* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */
3639 /* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */
3640+ /* Bit 7.. 3: reserved */
3641+#define LED_START BIT_2S /* Start Counter */
3642+#define LED_STOP BIT_1S /* Stop Counter */
3643+#define LED_STATE BIT_0S /* Rx/Tx: LED State, 1=LED On */
3644+
3645 /* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */
3646 /* Bit 7.. 3: reserved */
3647-#define LED_START BIT_2S /* Start Timer */
3648-#define LED_STOP BIT_1S /* Stop Timer */
3649-#define LED_STATE BIT_0S /* Rx/Tx: LED State, 1=LED on */
3650-#define LED_CLR_IRQ BIT_0S /* Lnk: Clear Link IRQ */
3651+#define LNK_START BIT_2S /* Start Counter */
3652+#define LNK_STOP BIT_1S /* Stop Counter */
3653+#define LNK_CLR_IRQ BIT_0S /* Clear Link IRQ */
3654
3655 /* RX_LED_TST 8 bit Receive LED Cnt Test Register */
3656 /* TX_LED_TST 8 bit Transmit LED Cnt Test Register */
3657@@ -1407,86 +2006,142 @@
3658 #define LED_T_STEP BIT_0S /* LED Counter Step */
3659
3660 /* LNK_LED_REG 8 bit Link LED Register */
3661- /* Bit 7.. 6: reserved */
3662+ /* Bit 7.. 6: reserved */
3663 #define LED_BLK_ON BIT_5S /* Link LED Blinking On */
3664 #define LED_BLK_OFF BIT_4S /* Link LED Blinking Off */
3665 #define LED_SYNC_ON BIT_3S /* Use Sync Wire to switch LED */
3666 #define LED_SYNC_OFF BIT_2S /* Disable Sync Wire Input */
3667-#define LED_ON BIT_1S /* switch LED on */
3668-#define LED_OFF BIT_0S /* switch LED off */
3669+#define LED_ON BIT_1S /* Switch LED On */
3670+#define LED_OFF BIT_0S /* Switch LED Off */
3671
3672 /* Receive and Transmit GMAC FIFO Registers (YUKON only) */
3673
3674 /* RX_GMF_EA 32 bit Rx GMAC FIFO End Address */
3675 /* RX_GMF_AF_THR 32 bit Rx GMAC FIFO Almost Full Thresh. */
3676-/* RX_GMF_WP 32 bit Rx GMAC FIFO Write Pointer */
3677-/* RX_GMF_WLEV 32 bit Rx GMAC FIFO Write Level */
3678-/* RX_GMF_RP 32 bit Rx GMAC FIFO Read Pointer */
3679-/* RX_GMF_RLEV 32 bit Rx GMAC FIFO Read Level */
3680+/* RX_GMF_WP 32 bit Rx GMAC FIFO Write Pointer */
3681+/* RX_GMF_WLEV 32 bit Rx GMAC FIFO Write Level */
3682+/* RX_GMF_RP 32 bit Rx GMAC FIFO Read Pointer */
3683+/* RX_GMF_RLEV 32 bit Rx GMAC FIFO Read Level */
3684 /* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */
3685 /* TX_GMF_AE_THR 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
3686-/* TX_GMF_WP 32 bit Tx GMAC FIFO Write Pointer */
3687-/* TX_GMF_WSP 32 bit Tx GMAC FIFO Write Shadow Ptr. */
3688-/* TX_GMF_WLEV 32 bit Tx GMAC FIFO Write Level */
3689-/* TX_GMF_RP 32 bit Tx GMAC FIFO Read Pointer */
3690-/* TX_GMF_RSTP 32 bit Tx GMAC FIFO Restart Pointer */
3691-/* TX_GMF_RLEV 32 bit Tx GMAC FIFO Read Level */
3692+/* TX_GMF_WP 32 bit Tx GMAC FIFO Write Pointer */
3693+/* TX_GMF_WSP 32 bit Tx GMAC FIFO Write Shadow Pointer */
3694+/* TX_GMF_WLEV 32 bit Tx GMAC FIFO Write Level */
3695+/* TX_GMF_RP 32 bit Tx GMAC FIFO Read Pointer */
3696+/* TX_GMF_RSTP 32 bit Tx GMAC FIFO Restart Pointer */
3697+/* TX_GMF_RLEV 32 bit Tx GMAC FIFO Read Level */
3698
3699 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
3700- /* Bits 31..15: reserved */
3701-#define GMF_WP_TST_ON BIT_14 /* Write Pointer Test On */
3702-#define GMF_WP_TST_OFF BIT_13 /* Write Pointer Test Off */
3703-#define GMF_WP_STEP BIT_12 /* Write Pointer Step/Increment */
3704+ /* Bit 31..28 reserved */
3705+#define RX_TRUNC_ON BIT_27 /* Enable Packet Truncation */
3706+#define RX_TRUNC_OFF BIT_26 /* Disable Packet Truncation */
3707+#define RX_VLAN_STRIP_ON BIT_25 /* Enable VLAN Stripping */
3708+#define RX_VLAN_STRIP_OFF BIT_24 /* Disable VLAN Stripping */
3709+ /* Bit 23..15 reserved */
3710+#define GMF_WP_TST_ON BIT_14 /* Write Pointer Test On */
3711+#define GMF_WP_TST_OFF BIT_13 /* Write Pointer Test Off */
3712+#define GMF_WP_STEP BIT_12 /* Write Pointer Step/Increment */
3713 /* Bit 11: reserved */
3714-#define GMF_RP_TST_ON BIT_10 /* Read Pointer Test On */
3715-#define GMF_RP_TST_OFF BIT_9 /* Read Pointer Test Off */
3716-#define GMF_RP_STEP BIT_8 /* Read Pointer Step/Increment */
3717-#define GMF_RX_F_FL_ON BIT_7 /* Rx FIFO Flush Mode On */
3718-#define GMF_RX_F_FL_OFF BIT_6 /* Rx FIFO Flush Mode Off */
3719-#define GMF_CLI_RX_FO BIT_5 /* Clear IRQ Rx FIFO Overrun */
3720-#define GMF_CLI_RX_FC BIT_4 /* Clear IRQ Rx Frame Complete */
3721-#define GMF_OPER_ON BIT_3 /* Operational Mode On */
3722-#define GMF_OPER_OFF BIT_2 /* Operational Mode Off */
3723-#define GMF_RST_CLR BIT_1 /* Clear GMAC FIFO Reset */
3724-#define GMF_RST_SET BIT_0 /* Set GMAC FIFO Reset */
3725-
3726-/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
3727- /* Bits 31..19: reserved */
3728-#define GMF_WSP_TST_ON BIT_18 /* Write Shadow Pointer Test On */
3729-#define GMF_WSP_TST_OFF BIT_17 /* Write Shadow Pointer Test Off */
3730-#define GMF_WSP_STEP BIT_16 /* Write Shadow Pointer Step/Increment */
3731- /* Bits 15..7: same as for RX_GMF_CTRL_T */
3732-#define GMF_CLI_TX_FU BIT_6 /* Clear IRQ Tx FIFO Underrun */
3733-#define GMF_CLI_TX_FC BIT_5 /* Clear IRQ Tx Frame Complete */
3734-#define GMF_CLI_TX_PE BIT_4 /* Clear IRQ Tx Parity Error */
3735+#define GMF_RP_TST_ON BIT_10 /* Read Pointer Test On */
3736+#define GMF_RP_TST_OFF BIT_9 /* Read Pointer Test Off */
3737+#define GMF_RP_STEP BIT_8 /* Read Pointer Step/Increment */
3738+#define GMF_RX_F_FL_ON BIT_7 /* Rx FIFO Flush Mode On */
3739+#define GMF_RX_F_FL_OFF BIT_6 /* Rx FIFO Flush Mode Off */
3740+#define GMF_CLI_RX_FO BIT_5 /* Clear IRQ Rx FIFO Overrun */
3741+#define GMF_CLI_RX_FC BIT_4 /* Clear IRQ Rx Frame Complete */
3742+#define GMF_OPER_ON BIT_3 /* Operational Mode On */
3743+#define GMF_OPER_OFF BIT_2 /* Operational Mode Off */
3744+#define GMF_RST_CLR BIT_1 /* Clear GMAC FIFO Reset */
3745+#define GMF_RST_SET BIT_0 /* Set GMAC FIFO Reset */
3746+
3747+/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test (YUKON and Yukon-2) */
3748+#define TX_STFW_DIS BIT_31 /* Disable Store & Forward (Yukon-EC Ultra) */
3749+#define TX_STFW_ENA BIT_30 /* Enable Store & Forward (Yukon-EC Ultra) */
3750+ /* Bits 29..26: reserved */
3751+#define TX_VLAN_TAG_ON BIT_25 /* Enable VLAN tagging */
3752+#define TX_VLAN_TAG_OFF BIT_24 /* Disable VLAN tagging */
3753+#define TX_PCI_JUM_ENA BIT_23 /* Enable PCI Jumbo Mode (Yukon-EC Ultra) */
3754+#define TX_PCI_JUM_DIS BIT_22 /* Disable PCI Jumbo Mode (Yukon-EC Ultra) */
3755+ /* Bits 21..19: reserved */
3756+#define GMF_WSP_TST_ON BIT_18 /* Write Shadow Pointer Test On */
3757+#define GMF_WSP_TST_OFF BIT_17 /* Write Shadow Pointer Test Off */
3758+#define GMF_WSP_STEP BIT_16 /* Write Shadow Pointer Step/Increment */
3759+ /* Bits 15..8: same as for RX_GMF_CTRL_T */
3760+ /* Bit 7: reserved */
3761+#define GMF_CLI_TX_FU BIT_6 /* Clear IRQ Tx FIFO Underrun */
3762+#define GMF_CLI_TX_FC BIT_5 /* Clear IRQ Tx Frame Complete */
3763+#define GMF_CLI_TX_PE BIT_4 /* Clear IRQ Tx Parity Error */
3764 /* Bits 3..0: same as for RX_GMF_CTRL_T */
3765
3766 #define GMF_RX_CTRL_DEF (GMF_OPER_ON | GMF_RX_F_FL_ON)
3767 #define GMF_TX_CTRL_DEF GMF_OPER_ON
3768
3769+#define RX_GMF_AF_THR_MIN 0x0c /* Rx GMAC FIFO Almost Full Thresh. min. */
3770 #define RX_GMF_FL_THR_DEF 0x0a /* Rx GMAC FIFO Flush Threshold default */
3771
3772 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
3773- /* Bit 7.. 3: reserved */
3774-#define GMT_ST_START BIT_2S /* Start Time Stamp Timer */
3775-#define GMT_ST_STOP BIT_1S /* Stop Time Stamp Timer */
3776-#define GMT_ST_CLR_IRQ BIT_0S /* Clear Time Stamp Timer IRQ */
3777-
3778+ /* Bit 7.. 3: reserved */
3779+#define GMT_ST_START BIT_2S /* Start Time Stamp Timer */
3780+#define GMT_ST_STOP BIT_1S /* Stop Time Stamp Timer */
3781+#define GMT_ST_CLR_IRQ BIT_0S /* Clear Time Stamp Timer IRQ */
3782+
3783+/* POLL_CTRL 32 bit Polling Unit control register (Yukon-2 only) */
3784+ /* Bit 31.. 6: reserved */
3785+#define PC_CLR_IRQ_CHK BIT_5 /* Clear IRQ Check */
3786+#define PC_POLL_RQ BIT_4 /* Poll Request Start */
3787+#define PC_POLL_OP_ON BIT_3 /* Operational Mode On */
3788+#define PC_POLL_OP_OFF BIT_2 /* Operational Mode Off */
3789+#define PC_POLL_RST_CLR BIT_1 /* Clear Polling Unit Reset (Enable) */
3790+#define PC_POLL_RST_SET BIT_0 /* Set Polling Unit Reset */
3791+
3792+
3793+/* The bit definition of the following registers is still missing! */
3794+/* B28_Y2_SMB_CONFIG 32 bit ASF SMBus Config Register */
3795+/* B28_Y2_SMB_CSD_REG 32 bit ASF SMB Control/Status/Data */
3796+/* B28_Y2_ASF_IRQ_V_BASE 32 bit ASF IRQ Vector Base */
3797+
3798+/* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */
3799+/* This register is used by the host driver software */
3800+ /* Bit 31.. 5 reserved */
3801+#define Y2_ASF_OS_PRES BIT_4S /* ASF operation system present */
3802+#define Y2_ASF_RESET BIT_3S /* ASF system in reset state */
3803+#define Y2_ASF_RUNNING BIT_2S /* ASF system operational */
3804+#define Y2_ASF_CLR_HSTI BIT_1S /* Clear ASF IRQ */
3805+#define Y2_ASF_IRQ BIT_0S /* Issue an IRQ to ASF system */
3806+
3807+#define Y2_ASF_UC_STATE (3<<2) /* ASF uC State */
3808+#define Y2_ASF_CLK_HALT 0 /* ASF system clock stopped */
3809+
3810+/* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */
3811+/* This register is used by the ASF firmware */
3812+ /* Bit 31.. 2 reserved */
3813+#define Y2_ASF_CLR_ASFI BIT_1 /* Clear host IRQ */
3814+#define Y2_ASF_HOST_IRQ BIT_0 /* Issue an IRQ to HOST system */
3815+
3816+
3817+/* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
3818+ /* Bit 7.. 5: reserved */
3819+#define SC_STAT_CLR_IRQ BIT_4 /* Status Burst IRQ clear */
3820+#define SC_STAT_OP_ON BIT_3 /* Operational Mode On */
3821+#define SC_STAT_OP_OFF BIT_2 /* Operational Mode Off */
3822+#define SC_STAT_RST_CLR BIT_1 /* Clear Status Unit Reset (Enable) */
3823+#define SC_STAT_RST_SET BIT_0 /* Set Status Unit Reset */
3824+
3825 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
3826 /* Bits 31.. 8: reserved */
3827-#define GMC_H_BURST_ON BIT_7 /* Half Duplex Burst Mode On */
3828-#define GMC_H_BURST_OFF BIT_6 /* Half Duplex Burst Mode Off */
3829-#define GMC_F_LOOPB_ON BIT_5 /* FIFO Loopback On */
3830-#define GMC_F_LOOPB_OFF BIT_4 /* FIFO Loopback Off */
3831-#define GMC_PAUSE_ON BIT_3 /* Pause On */
3832-#define GMC_PAUSE_OFF BIT_2 /* Pause Off */
3833-#define GMC_RST_CLR BIT_1 /* Clear GMAC Reset */
3834-#define GMC_RST_SET BIT_0 /* Set GMAC Reset */
3835+#define GMC_H_BURST_ON BIT_7 /* Half Duplex Burst Mode On */
3836+#define GMC_H_BURST_OFF BIT_6 /* Half Duplex Burst Mode Off */
3837+#define GMC_F_LOOPB_ON BIT_5 /* FIFO Loopback On */
3838+#define GMC_F_LOOPB_OFF BIT_4 /* FIFO Loopback Off */
3839+#define GMC_PAUSE_ON BIT_3 /* Pause On */
3840+#define GMC_PAUSE_OFF BIT_2 /* Pause Off */
3841+#define GMC_RST_CLR BIT_1 /* Clear GMAC Reset */
3842+#define GMC_RST_SET BIT_0 /* Set GMAC Reset */
3843
3844 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
3845 /* Bits 31..29: reserved */
3846 #define GPC_SEL_BDT BIT_28 /* Select Bi-Dir. Transfer for MDC/MDIO */
3847-#define GPC_INT_POL_HI BIT_27 /* IRQ Polarity is Active HIGH */
3848+#define GPC_INT_POL BIT_27 /* IRQ Polarity is Active Low */
3849 #define GPC_75_OHM BIT_26 /* Use 75 Ohm Termination instead of 50 */
3850 #define GPC_DIS_FC BIT_25 /* Disable Automatic Fiber/Copper Detection */
3851 #define GPC_DIS_SLEEP BIT_24 /* Disable Energy Detect */
3852@@ -1501,15 +2156,24 @@
3853 #define GPC_ANEG_2 BIT_15 /* ANEG[2] */
3854 #define GPC_ANEG_1 BIT_14 /* ANEG[1] */
3855 #define GPC_ENA_PAUSE BIT_13 /* Enable Pause (SYM_OR_REM) */
3856-#define GPC_PHYADDR_4 BIT_12 /* Bit 4 of Phy Addr */
3857-#define GPC_PHYADDR_3 BIT_11 /* Bit 3 of Phy Addr */
3858-#define GPC_PHYADDR_2 BIT_10 /* Bit 2 of Phy Addr */
3859-#define GPC_PHYADDR_1 BIT_9 /* Bit 1 of Phy Addr */
3860-#define GPC_PHYADDR_0 BIT_8 /* Bit 0 of Phy Addr */
3861+#define GPC_PHYADDR_4 BIT_12 /* Bit 4 of PHY Addr */
3862+#define GPC_PHYADDR_3 BIT_11 /* Bit 3 of PHY Addr */
3863+#define GPC_PHYADDR_2 BIT_10 /* Bit 2 of PHY Addr */
3864+#define GPC_PHYADDR_1 BIT_9 /* Bit 1 of PHY Addr */
3865+#define GPC_PHYADDR_0 BIT_8 /* Bit 0 of PHY Addr */
3866 /* Bits 7..2: reserved */
3867 #define GPC_RST_CLR BIT_1 /* Clear GPHY Reset */
3868 #define GPC_RST_SET BIT_0 /* Set GPHY Reset */
3869
3870+/* Yukon-EC Ultra only */
3871+#define GPC_LED_CONF_MSK (7<<6) /* Bit 8.. 6: GPHY LED Config */
3872+#define GPC_PD_125M_CLK_OFF BIT_5 /* Disable Power Down Clock 125 MHz */
3873+#define GPC_PD_125M_CLK_ON BIT_4 /* Enable Power Down Clock 125 MHz */
3874+#define GPC_DPLL_RST_SET BIT_3 /* Set GPHY's DPLL Reset */
3875+#define GPC_DPLL_RST_CLR BIT_2 /* Clear GPHY's DPLL Reset */
3876+ /* (DPLL = Digital Phase Lock Loop) */
3877+#define GPC_LED_CONF_VAL(x) (SHIFT6(x) & GPC_LED_CONF_MSK)
3878+
3879 #define GPC_HWCFG_GMII_COP (GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | \
3880 GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
3881
3882@@ -1540,20 +2204,20 @@
3883
3884 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
3885 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
3886-#define GM_IS_TX_CO_OV BIT_5 /* Transmit Counter Overflow IRQ */
3887-#define GM_IS_RX_CO_OV BIT_4 /* Receive Counter Overflow IRQ */
3888-#define GM_IS_TX_FF_UR BIT_3 /* Transmit FIFO Underrun */
3889-#define GM_IS_TX_COMPL BIT_2 /* Frame Transmission Complete */
3890-#define GM_IS_RX_FF_OR BIT_1 /* Receive FIFO Overrun */
3891-#define GM_IS_RX_COMPL BIT_0 /* Frame Reception Complete */
3892+#define GM_IS_RX_CO_OV BIT_5S /* Receive Counter Overflow IRQ */
3893+#define GM_IS_TX_CO_OV BIT_4S /* Transmit Counter Overflow IRQ */
3894+#define GM_IS_TX_FF_UR BIT_3S /* Transmit FIFO Underrun */
3895+#define GM_IS_TX_COMPL BIT_2S /* Frame Transmission Complete */
3896+#define GM_IS_RX_FF_OR BIT_1S /* Receive FIFO Overrun */
3897+#define GM_IS_RX_COMPL BIT_0S /* Frame Reception Complete */
3898
3899-#define GMAC_DEF_MSK (GM_IS_TX_CO_OV | GM_IS_RX_CO_OV | \
3900+#define GMAC_DEF_MSK (GM_IS_RX_CO_OV | GM_IS_TX_CO_OV | \
3901 GM_IS_TX_FF_UR)
3902
3903-/* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
3904+/* GMAC_LINK_CTRL 16 bit Link Control Reg (YUKON only) */
3905 /* Bits 15.. 2: reserved */
3906-#define GMLC_RST_CLR BIT_1S /* Clear GMAC Link Reset */
3907-#define GMLC_RST_SET BIT_0S /* Set GMAC Link Reset */
3908+#define GMLC_RST_CLR BIT_1S /* Clear Link Reset */
3909+#define GMLC_RST_SET BIT_0S /* Set Link Reset */
3910
3911
3912 /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
3913@@ -1579,15 +2243,19 @@
3914
3915 #define WOL_CTL_DEFAULT \
3916 (WOL_CTL_DIS_PME_ON_LINK_CHG | \
3917- WOL_CTL_DIS_PME_ON_PATTERN | \
3918- WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
3919- WOL_CTL_DIS_LINK_CHG_UNIT | \
3920- WOL_CTL_DIS_PATTERN_UNIT | \
3921- WOL_CTL_DIS_MAGIC_PKT_UNIT)
3922+ WOL_CTL_DIS_PME_ON_PATTERN | \
3923+ WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
3924+ WOL_CTL_DIS_LINK_CHG_UNIT | \
3925+ WOL_CTL_DIS_PATTERN_UNIT | \
3926+ WOL_CTL_DIS_MAGIC_PKT_UNIT)
3927
3928 /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
3929 #define WOL_CTL_PATT_ENA(x) (BIT_0 << (x))
3930
3931+/* WOL_PATT_PME 8 bit WOL PME Match Enable (Yukon-2) */
3932+#define WOL_PATT_FORCE_PME BIT_7 /* Generates a PME */
3933+#define WOL_PATT_MATCH_PME_ALL 0x7f
3934+
3935 #define SK_NUM_WOL_PATTERN 7
3936 #define SK_PATTERN_PER_WORD 4
3937 #define SK_BITMASK_PATTERN 7
3938@@ -1597,26 +2265,28 @@
3939 #define WOL_LENGTH_SHIFT 8
3940
3941
3942+/* typedefs ******************************************************************/
3943+
3944 /* Receive and Transmit Descriptors ******************************************/
3945
3946 /* Transmit Descriptor struct */
3947 typedef struct s_HwTxd {
3948 SK_U32 volatile TxCtrl; /* Transmit Buffer Control Field */
3949 SK_U32 TxNext; /* Physical Address Pointer to the next TxD */
3950- SK_U32 TxAdrLo; /* Physical Tx Buffer Address lower dword */
3951- SK_U32 TxAdrHi; /* Physical Tx Buffer Address upper dword */
3952+ SK_U32 TxAdrLo; /* Physical Tx Buffer Address lower DWord */
3953+ SK_U32 TxAdrHi; /* Physical Tx Buffer Address upper DWord */
3954 SK_U32 TxStat; /* Transmit Frame Status Word */
3955-#ifndef SK_USE_REV_DESC
3956+#ifndef SK_USE_REV_DESC
3957 SK_U16 TxTcpOffs; /* TCP Checksum Calculation Start Value */
3958 SK_U16 TxRes1; /* 16 bit reserved field */
3959 SK_U16 TxTcpWp; /* TCP Checksum Write Position */
3960 SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */
3961-#else /* SK_USE_REV_DESC */
3962+#else /* SK_USE_REV_DESC */
3963 SK_U16 TxRes1; /* 16 bit reserved field */
3964 SK_U16 TxTcpOffs; /* TCP Checksum Calculation Start Value */
3965 SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */
3966 SK_U16 TxTcpWp; /* TCP Checksum Write Position */
3967-#endif /* SK_USE_REV_DESC */
3968+#endif /* SK_USE_REV_DESC */
3969 SK_U32 TxRes2; /* 32 bit reserved field */
3970 } SK_HWTXD;
3971
3972@@ -1624,33 +2294,266 @@
3973 typedef struct s_HwRxd {
3974 SK_U32 volatile RxCtrl; /* Receive Buffer Control Field */
3975 SK_U32 RxNext; /* Physical Address Pointer to the next RxD */
3976- SK_U32 RxAdrLo; /* Physical Rx Buffer Address lower dword */
3977- SK_U32 RxAdrHi; /* Physical Rx Buffer Address upper dword */
3978+ SK_U32 RxAdrLo; /* Physical Rx Buffer Address lower DWord */
3979+ SK_U32 RxAdrHi; /* Physical Rx Buffer Address upper DWord */
3980 SK_U32 RxStat; /* Receive Frame Status Word */
3981 SK_U32 RxTiSt; /* Receive Time Stamp (from XMAC on GENESIS) */
3982-#ifndef SK_USE_REV_DESC
3983- SK_U16 RxTcpSum1; /* TCP Checksum 1 */
3984- SK_U16 RxTcpSum2; /* TCP Checksum 2 */
3985+#ifndef SK_USE_REV_DESC
3986+ SK_U16 RxTcpSum1; /* Rx TCP Checksum 1 */
3987+ SK_U16 RxTcpSum2; /* Rx TCP Checksum 2 */
3988 SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */
3989 SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */
3990-#else /* SK_USE_REV_DESC */
3991- SK_U16 RxTcpSum2; /* TCP Checksum 2 */
3992- SK_U16 RxTcpSum1; /* TCP Checksum 1 */
3993+#else /* SK_USE_REV_DESC */
3994+ SK_U16 RxTcpSum2; /* Rx TCP Checksum 2 */
3995+ SK_U16 RxTcpSum1; /* Rx TCP Checksum 1 */
3996 SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */
3997 SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */
3998-#endif /* SK_USE_REV_DESC */
3999+#endif /* SK_USE_REV_DESC */
4000 } SK_HWRXD;
4001
4002 /*
4003 * Drivers which use the reverse descriptor feature (PCI_OUR_REG_2)
4004 * should set the define SK_USE_REV_DESC.
4005- * Structures are 'normaly' not endianess dependent. But in
4006- * this case the SK_U16 fields are bound to bit positions inside the
4007- * descriptor. RxTcpSum1 e.g. must start at bit 0 within the 6.th DWord.
4008+ * Structures are 'normally' not endianess dependent. But in this case
4009+ * the SK_U16 fields are bound to bit positions inside the descriptor.
4010+ * RxTcpSum1 e.g. must start at bit 0 within the 7.th DWord.
4011 * The bit positions inside a DWord are of course endianess dependent and
4012- * swaps if the DWord is swapped by the hardware.
4013+ * swap if the DWord is swapped by the hardware.
4014 */
4015
4016+/* YUKON-2 descriptors ******************************************************/
4017+
4018+typedef struct _TxChksum {
4019+#ifndef SK_USE_REV_DESC
4020+ SK_U16 TxTcpWp; /* TCP Checksum Write Position */
4021+ SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */
4022+#else /* SK_USE_REV_DESC */
4023+ SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */
4024+ SK_U16 TxTcpWp; /* TCP Checksum Write Position */
4025+#endif /* SK_USE_REV_DESC */
4026+} SK_HWTXCS;
4027+
4028+typedef struct _LargeSend {
4029+#ifndef SK_USE_REV_DESC
4030+ SK_U16 Length; /* Large Send Segment Length */
4031+ SK_U16 Reserved; /* reserved */
4032+#else /* SK_USE_REV_DESC */
4033+ SK_U16 Reserved; /* reserved */
4034+ SK_U16 Length; /* Large Send Segment Length */
4035+#endif /* SK_USE_REV_DESC */
4036+} SK_HWTXLS;
4037+
4038+typedef union u_HwTxBuf {
4039+ SK_U16 BufLen; /* Tx Buffer Length */
4040+ SK_U16 VlanTag; /* VLAN Tag */
4041+ SK_U16 InitCsum; /* Init. Checksum */
4042+} SK_HWTXBUF;
4043+
4044+/* Tx List Element structure */
4045+typedef struct s_HwLeTx {
4046+ union {
4047+ SK_U32 BufAddr; /* Tx LE Buffer Address high/low */
4048+ SK_HWTXCS ChkSum; /* Tx LE TCP Checksum parameters */
4049+ SK_HWTXLS LargeSend;/* Large Send length */
4050+ } TxUn;
4051+#ifndef SK_USE_REV_DESC
4052+ SK_HWTXBUF Send;
4053+ SK_U8 ControlFlags; /* Tx LE Control field or Lock Number */
4054+ SK_U8 Opcode; /* Tx LE Opcode field */
4055+#else /* SK_USE_REV_DESC */
4056+ SK_U8 Opcode; /* Tx LE Opcode field */
4057+ SK_U8 ControlFlags; /* Tx LE Control field or Lock Number */
4058+ SK_HWTXBUF Send;
4059+#endif /* SK_USE_REV_DESC */
4060+} SK_HWLETX;
4061+
4062+typedef struct _RxChkSum{
4063+#ifndef SK_USE_REV_DESC
4064+ SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */
4065+ SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */
4066+#else /* SK_USE_REV_DESC */
4067+ SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */
4068+ SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */
4069+#endif /* SK_USE_REV_DESC */
4070+} SK_HWRXCS;
4071+
4072+/* Rx List Element structure */
4073+typedef struct s_HwLeRx {
4074+ union {
4075+ SK_U32 BufAddr; /* Rx LE Buffer Address high/low */
4076+ SK_HWRXCS ChkSum; /* Rx LE TCP Checksum parameters */
4077+ } RxUn;
4078+#ifndef SK_USE_REV_DESC
4079+ SK_U16 BufferLength; /* Rx LE Buffer Length field */
4080+ SK_U8 ControlFlags; /* Rx LE Control field */
4081+ SK_U8 Opcode; /* Rx LE Opcode field */
4082+#else /* SK_USE_REV_DESC */
4083+ SK_U8 Opcode; /* Rx LE Opcode field */
4084+ SK_U8 ControlFlags; /* Rx LE Control field */
4085+ SK_U16 BufferLength; /* Rx LE Buffer Length field */
4086+#endif /* SK_USE_REV_DESC */
4087+} SK_HWLERX;
4088+
4089+typedef struct s_StRxTCPChkSum {
4090+#ifndef SK_USE_REV_DESC
4091+ SK_U16 RxTCPSum1; /* Rx TCP Checksum 1 */
4092+ SK_U16 RxTCPSum2; /* Rx TCP Checksum 2 */
4093+#else /* SK_USE_REV_DESC */
4094+ SK_U16 RxTCPSum2; /* Rx TCP Checksum 2 */
4095+ SK_U16 RxTCPSum1; /* Rx TCP Checksum 1 */
4096+#endif /* SK_USE_REV_DESC */
4097+} SK_HWSTCS;
4098+
4099+typedef struct s_StRxRssFlags {
4100+#ifndef SK_USE_REV_DESC
4101+ SK_U8 FlagField; /* contains TCP and IP flags */
4102+ SK_U8 reserved; /* reserved */
4103+#else /* SK_USE_REV_DESC */
4104+ SK_U8 reserved; /* reserved */
4105+ SK_U8 FlagField; /* contains TCP and IP flags */
4106+#endif /* SK_USE_REV_DESC */
4107+} SK_HWSTRSS;
4108+
4109+/* bit definition of RSS LE bit 32/33 (SK_HWSTRSS.FlagField) */
4110+ /* bit 7..2 reserved */
4111+#define RSS_TCP_FLAG BIT_1S /* RSS value related to TCP area */
4112+#define RSS_IP_FLAG BIT_0S /* RSS value related to IP area */
4113+/* StRxRssValue is valid if at least RSS_IP_FLAG is set */
4114+/* For protocol errors or other protocols an empty RSS LE is generated */
4115+
4116+typedef union u_HwStBuf {
4117+ SK_U16 BufLen; /* Rx Buffer Length */
4118+ SK_U16 VlanTag; /* VLAN Tag */
4119+ SK_U16 StTxStatHi; /* Tx Queue Status (high) */
4120+ SK_HWSTRSS Rss; /* Flag Field for TCP and IP protocol */
4121+} SK_HWSTBUF;
4122+
4123+/* Status List Element structure */
4124+typedef struct s_HwLeSt {
4125+ union {
4126+ SK_U32 StRxStatWord; /* Rx Status Dword */
4127+ SK_U32 StRxTimeStamp; /* Rx Timestamp */
4128+ SK_HWSTCS StRxTCPCSum; /* Rx TCP Checksum */
4129+ SK_U32 StTxStatLow; /* Tx Queue Status (low) */
4130+ SK_U32 StRxRssValue; /* Rx RSS value */
4131+ } StUn;
4132+#ifndef SK_USE_REV_DESC
4133+ SK_HWSTBUF Stat;
4134+ SK_U8 Link; /* Status LE Link field */
4135+ SK_U8 Opcode; /* Status LE Opcode field */
4136+#else /* SK_USE_REV_DESC */
4137+ SK_U8 Opcode; /* Status LE Opcode field */
4138+ SK_U8 Link; /* Status LE Link field */
4139+ SK_HWSTBUF Stat;
4140+#endif /* SK_USE_REV_DESC */
4141+} SK_HWLEST;
4142+
4143+/* Special Action List Element */
4144+typedef struct s_HwLeSa {
4145+#ifndef SK_USE_REV_DESC
4146+ SK_U16 TxAIdxVld; /* Special Action LE TxA Put Index field */
4147+ SK_U16 TxSIdxVld; /* Special Action LE TxS Put Index field */
4148+ SK_U16 RxIdxVld; /* Special Action LE Rx Put Index field */
4149+ SK_U8 Link; /* Special Action LE Link field */
4150+ SK_U8 Opcode; /* Special Action LE Opcode field */
4151+#else /* SK_USE_REV_DESC */
4152+ SK_U16 TxSIdxVld; /* Special Action LE TxS Put Index field */
4153+ SK_U16 TxAIdxVld; /* Special Action LE TxA Put Index field */
4154+ SK_U8 Opcode; /* Special Action LE Opcode field */
4155+ SK_U8 Link; /* Special Action LE Link field */
4156+ SK_U16 RxIdxVld; /* Special Action LE Rx Put Index field */
4157+#endif /* SK_USE_REV_DESC */
4158+} SK_HWLESA;
4159+
4160+/* Common List Element union */
4161+typedef union u_HwLeTxRxSt {
4162+ /* Transmit List Element Structure */
4163+ SK_HWLETX Tx;
4164+ /* Receive List Element Structure */
4165+ SK_HWLERX Rx;
4166+ /* Status List Element Structure */
4167+ SK_HWLEST St;
4168+ /* Special Action List Element Structure */
4169+ SK_HWLESA Sa;
4170+ /* Full List Element */
4171+ SK_U64 Full;
4172+} SK_HWLE;
4173+
4174+/* mask and shift value to get Tx async queue status for port 1 */
4175+#define STLE_TXA1_MSKL 0x00000fff
4176+#define STLE_TXA1_SHIFTL 0
4177+
4178+/* mask and shift value to get Tx sync queue status for port 1 */
4179+#define STLE_TXS1_MSKL 0x00fff000
4180+#define STLE_TXS1_SHIFTL 12
4181+
4182+/* mask and shift value to get Tx async queue status for port 2 */
4183+#define STLE_TXA2_MSKL 0xff000000
4184+#define STLE_TXA2_SHIFTL 24
4185+#define STLE_TXA2_MSKH 0x000f
4186+/* this one shifts up */
4187+#define STLE_TXA2_SHIFTH 8
4188+
4189+/* mask and shift value to get Tx sync queue status for port 2 */
4190+#define STLE_TXS2_MSKL 0x00000000
4191+#define STLE_TXS2_SHIFTL 0
4192+#define STLE_TXS2_MSKH 0xfff0
4193+#define STLE_TXS2_SHIFTH 4
4194+
4195+/* YUKON-2 bit values */
4196+#define HW_OWNER BIT_7
4197+#define SW_OWNER 0
4198+
4199+#define PU_PUTIDX_VALID BIT_12
4200+
4201+/* YUKON-2 Control flags */
4202+#define UDPTCP BIT_0S
4203+#define CALSUM BIT_1S
4204+#define WR_SUM BIT_2S
4205+#define INIT_SUM BIT_3S
4206+#define LOCK_SUM BIT_4S
4207+#define INS_VLAN BIT_5S
4208+#define FRC_STAT BIT_6S
4209+#define EOP BIT_7S
4210+
4211+#define TX_LOCK BIT_8S
4212+#define BUF_SEND BIT_9S
4213+#define PACKET_SEND BIT_10S
4214+
4215+#define NO_WARNING BIT_14S
4216+#define NO_UPDATE BIT_15S
4217+
4218+/* YUKON-2 Rx/Tx opcodes defines */
4219+#define OP_TCPWRITE 0x11
4220+#define OP_TCPSTART 0x12
4221+#define OP_TCPINIT 0x14
4222+#define OP_TCPLCK 0x18
4223+#define OP_TCPCHKSUM OP_TCPSTART
4224+#define OP_TCPIS (OP_TCPINIT | OP_TCPSTART)
4225+#define OP_TCPLW (OP_TCPLCK | OP_TCPWRITE)
4226+#define OP_TCPLSW (OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE)
4227+#define OP_TCPLISW (OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE)
4228+#define OP_ADDR64 0x21
4229+#define OP_VLAN 0x22
4230+#define OP_ADDR64VLAN (OP_ADDR64 | OP_VLAN)
4231+#define OP_LRGLEN 0x24
4232+#define OP_LRGLENVLAN (OP_LRGLEN | OP_VLAN)
4233+#define OP_BUFFER 0x40
4234+#define OP_PACKET 0x41
4235+#define OP_LARGESEND 0x43
4236+
4237+/* YUKON-2 STATUS opcodes defines */
4238+#define OP_RXSTAT 0x60
4239+#define OP_RXTIMESTAMP 0x61
4240+#define OP_RXVLAN 0x62
4241+#define OP_RXCHKS 0x64
4242+#define OP_RXCHKSVLAN (OP_RXCHKS | OP_RXVLAN)
4243+#define OP_RXTIMEVLAN (OP_RXTIMESTAMP | OP_RXVLAN)
4244+#define OP_RSS_HASH 0x65
4245+#define OP_TXINDEXLE 0x68
4246+
4247+/* YUKON-2 SPECIAL opcodes defines */
4248+#define OP_PUTIDX 0x70
4249
4250 /* Descriptor Bit Definition */
4251 /* TxCtrl Transmit Buffer Control Field */
4252@@ -1685,6 +2588,10 @@
4253
4254 /* macros ********************************************************************/
4255
4256+/* Macro for accessing the key registers */
4257+#define RSS_KEY_ADDR(Port, KeyIndex) \
4258+ ((B4_RSS_KEY | ( ((Port) == 0) ? 0 : 0x80)) + (KeyIndex))
4259+
4260 /* Receive and Transmit Queues */
4261 #define Q_R1 0x0000 /* Receive Queue 1 */
4262 #define Q_R2 0x0080 /* Receive Queue 2 */
4263@@ -1693,6 +2600,10 @@
4264 #define Q_XS2 0x0300 /* Synchronous Transmit Queue 2 */
4265 #define Q_XA2 0x0380 /* Asynchronous Transmit Queue 2 */
4266
4267+#define Q_ASF_R1 0x100 /* ASF Rx Queue 1 */
4268+#define Q_ASF_R2 0x180 /* ASF Rx Queue 2 */
4269+#define Q_ASF_T1 0x140 /* ASF Tx Queue 1 */
4270+#define Q_ASF_T2 0x1c0 /* ASF Tx Queue 2 */
4271 /*
4272 * Macro Q_ADDR()
4273 *
4274@@ -1704,11 +2615,27 @@
4275 * Offs Queue register offset.
4276 * Values: Q_D, Q_DA_L ... Q_T2, Q_T3
4277 *
4278- * usage SK_IN32(pAC, Q_ADDR(Q_R2, Q_BC), pVal)
4279+ * usage SK_IN32(IoC, Q_ADDR(Q_R2, Q_BC), pVal)
4280 */
4281 #define Q_ADDR(Queue, Offs) (B8_Q_REGS + (Queue) + (Offs))
4282
4283 /*
4284+ * Macro Y2_PREF_Q_ADDR()
4285+ *
4286+ * Use this macro to access the Prefetch Units of the receive and
4287+ * transmit queues of Yukon-2.
4288+ *
4289+ * para:
4290+ * Queue Queue to access.
4291+ * Values: Q_R1, Q_R2, Q_XS1, Q_XA1, Q_XS2, Q_XA2,
4292+ * Offs Queue register offset.
4293+ * Values: PREF_UNIT_CTRL_REG ... PREF_UNIT_FIFO_LEV_REG
4294+ *
4295+ * usage SK_IN16(IoC, Y2_Q_ADDR(Q_R2, PREF_UNIT_GET_IDX_REG), pVal)
4296+ */
4297+#define Y2_PREF_Q_ADDR(Queue, Offs) (Y2_B8_PREF_REGS + (Queue) + (Offs))
4298+
4299+/*
4300 * Macro RB_ADDR()
4301 *
4302 * Use this macro to access the RAM Buffer Registers.
4303@@ -1719,14 +2646,14 @@
4304 * Offs Queue register offset.
4305 * Values: RB_START, RB_END ... RB_LEV, RB_CTRL
4306 *
4307- * usage SK_IN32(pAC, RB_ADDR(Q_R2, RB_RP), pVal)
4308+ * usage SK_IN32(IoC, RB_ADDR(Q_R2, RB_RP), pVal)
4309 */
4310 #define RB_ADDR(Queue, Offs) (B16_RAM_REGS + (Queue) + (Offs))
4311
4312
4313 /* MAC Related Registers */
4314-#define MAC_1 0 /* belongs to the port near the slot */
4315-#define MAC_2 1 /* belongs to the port far away from the slot */
4316+#define MAC_1 0 /* 1st port */
4317+#define MAC_2 1 /* 2nd port */
4318
4319 /*
4320 * Macro MR_ADDR()
4321@@ -1740,19 +2667,10 @@
4322 * Values: RX_MFF_EA, RX_MFF_WP ... LNK_LED_REG,
4323 * TX_MFF_EA, TX_MFF_WP ... TX_LED_TST
4324 *
4325- * usage SK_IN32(pAC, MR_ADDR(MAC_1, TX_MFF_EA), pVal)
4326+ * usage SK_IN32(IoC, MR_ADDR(MAC_1, TX_MFF_EA), pVal)
4327 */
4328 #define MR_ADDR(Mac, Offs) (((Mac) << 7) + (Offs))
4329
4330-#ifdef SK_LITTLE_ENDIAN
4331-#define XM_WORD_LO 0
4332-#define XM_WORD_HI 1
4333-#else /* !SK_LITTLE_ENDIAN */
4334-#define XM_WORD_LO 1
4335-#define XM_WORD_HI 0
4336-#endif /* !SK_LITTLE_ENDIAN */
4337-
4338-
4339 /*
4340 * macros to access the XMAC (GENESIS only)
4341 *
4342@@ -1777,22 +2695,31 @@
4343 #define XMA(Mac, Reg) \
4344 ((BASE_XMAC_1 + (Mac) * (BASE_XMAC_2 - BASE_XMAC_1)) | ((Reg) << 1))
4345
4346-#define XM_IN16(IoC, Mac, Reg, pVal) \
4347- SK_IN16((IoC), XMA((Mac), (Reg)), (pVal))
4348+#define XM_IN16(IoC, Mac, Reg, pVal) \
4349+ SK_IN16(IoC, XMA(Mac, Reg), pVal)
4350
4351-#define XM_OUT16(IoC, Mac, Reg, Val) \
4352- SK_OUT16((IoC), XMA((Mac), (Reg)), (Val))
4353+#define XM_OUT16(IoC, Mac, Reg, Val) \
4354+ SK_OUT16(IoC, XMA(Mac, Reg), Val)
4355
4356-#define XM_IN32(IoC, Mac, Reg, pVal) { \
4357- SK_IN16((IoC), XMA((Mac), (Reg)), \
4358- (SK_U16 SK_FAR*)&((SK_U16 SK_FAR*)(pVal))[XM_WORD_LO]); \
4359- SK_IN16((IoC), XMA((Mac), (Reg+2)), \
4360- (SK_U16 SK_FAR*)&((SK_U16 SK_FAR*)(pVal))[XM_WORD_HI]); \
4361+#ifdef SK_LITTLE_ENDIAN
4362+
4363+#define XM_IN32(IoC, Mac, Reg, pVal) { \
4364+ SK_IN16(IoC, XMA(Mac, Reg), (SK_U16 SK_FAR *)(pVal)); \
4365+ SK_IN16(IoC, XMA(Mac, (Reg) + 2), (SK_U16 SK_FAR *)(pVal) + 1); \
4366 }
4367
4368+#else /* !SK_LITTLE_ENDIAN */
4369+
4370+#define XM_IN32(IoC, Mac, Reg, pVal) { \
4371+ SK_IN16(IoC, XMA(Mac, Reg), (SK_U16 SK_FAR *)(pVal) + 1); \
4372+ SK_IN16(IoC, XMA(Mac, (Reg) + 2), (SK_U16 SK_FAR *)(pVal)); \
4373+}
4374+
4375+#endif /* !SK_LITTLE_ENDIAN */
4376+
4377 #define XM_OUT32(IoC, Mac, Reg, Val) { \
4378- SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16)((Val) & 0xffffL)); \
4379- SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16)(((Val) >> 16) & 0xffffL));\
4380+ SK_OUT16(IoC, XMA(Mac, Reg), (SK_U16)((Val) & 0xffffL)); \
4381+ SK_OUT16(IoC, XMA(Mac, (Reg) + 2), (SK_U16)(((Val) >> 16) & 0xffffL)); \
4382 }
4383
4384 /* Remember: we are always writing to / reading from LITTLE ENDIAN memory */
4385@@ -1802,13 +2729,13 @@
4386 SK_U8 *pByte; \
4387 pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \
4388 SK_IN16((IoC), XMA((Mac), (Reg)), &Word); \
4389- pByte[0] = (SK_U8)(Word & 0x00ff); \
4390+ pByte[0] = (SK_U8)(Word & 0x00ff); \
4391 pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \
4392- SK_IN16((IoC), XMA((Mac), (Reg+2)), &Word); \
4393- pByte[2] = (SK_U8)(Word & 0x00ff); \
4394+ SK_IN16((IoC), XMA((Mac), (Reg) + 2), &Word); \
4395+ pByte[2] = (SK_U8)(Word & 0x00ff); \
4396 pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \
4397- SK_IN16((IoC), XMA((Mac), (Reg+4)), &Word); \
4398- pByte[4] = (SK_U8)(Word & 0x00ff); \
4399+ SK_IN16((IoC), XMA((Mac), (Reg) + 4), &Word); \
4400+ pByte[4] = (SK_U8)(Word & 0x00ff); \
4401 pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \
4402 }
4403
4404@@ -1818,10 +2745,10 @@
4405 SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16) \
4406 (((SK_U16)(pByte[0]) & 0x00ff) | \
4407 (((SK_U16)(pByte[1]) << 8) & 0xff00))); \
4408- SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16) \
4409+ SK_OUT16((IoC), XMA((Mac), (Reg) + 2), (SK_U16) \
4410 (((SK_U16)(pByte[2]) & 0x00ff) | \
4411 (((SK_U16)(pByte[3]) << 8) & 0xff00))); \
4412- SK_OUT16((IoC), XMA((Mac), (Reg+4)), (SK_U16) \
4413+ SK_OUT16((IoC), XMA((Mac), (Reg) + 4), (SK_U16) \
4414 (((SK_U16)(pByte[4]) & 0x00ff) | \
4415 (((SK_U16)(pByte[5]) << 8) & 0xff00))); \
4416 }
4417@@ -1831,16 +2758,16 @@
4418 SK_U8 SK_FAR *pByte; \
4419 pByte = (SK_U8 SK_FAR *)&((SK_U8 SK_FAR *)(pVal))[0]; \
4420 SK_IN16((IoC), XMA((Mac), (Reg)), &Word); \
4421- pByte[0] = (SK_U8)(Word & 0x00ff); \
4422+ pByte[0] = (SK_U8)(Word & 0x00ff); \
4423 pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \
4424- SK_IN16((IoC), XMA((Mac), (Reg+2)), &Word); \
4425- pByte[2] = (SK_U8)(Word & 0x00ff); \
4426+ SK_IN16((IoC), XMA((Mac), (Reg) + 2), &Word); \
4427+ pByte[2] = (SK_U8)(Word & 0x00ff); \
4428 pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \
4429- SK_IN16((IoC), XMA((Mac), (Reg+4)), &Word); \
4430- pByte[4] = (SK_U8)(Word & 0x00ff); \
4431+ SK_IN16((IoC), XMA((Mac), (Reg) + 4), &Word); \
4432+ pByte[4] = (SK_U8)(Word & 0x00ff); \
4433 pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \
4434- SK_IN16((IoC), XMA((Mac), (Reg+6)), &Word); \
4435- pByte[6] = (SK_U8)(Word & 0x00ff); \
4436+ SK_IN16((IoC), XMA((Mac), (Reg) + 6), &Word); \
4437+ pByte[6] = (SK_U8)(Word & 0x00ff); \
4438 pByte[7] = (SK_U8)((Word >> 8) & 0x00ff); \
4439 }
4440
4441@@ -1850,13 +2777,13 @@
4442 SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16) \
4443 (((SK_U16)(pByte[0]) & 0x00ff)| \
4444 (((SK_U16)(pByte[1]) << 8) & 0xff00))); \
4445- SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16) \
4446+ SK_OUT16((IoC), XMA((Mac), (Reg) + 2), (SK_U16) \
4447 (((SK_U16)(pByte[2]) & 0x00ff)| \
4448 (((SK_U16)(pByte[3]) << 8) & 0xff00))); \
4449- SK_OUT16((IoC), XMA((Mac), (Reg+4)), (SK_U16) \
4450+ SK_OUT16((IoC), XMA((Mac), (Reg) + 4), (SK_U16) \
4451 (((SK_U16)(pByte[4]) & 0x00ff)| \
4452 (((SK_U16)(pByte[5]) << 8) & 0xff00))); \
4453- SK_OUT16((IoC), XMA((Mac), (Reg+6)), (SK_U16) \
4454+ SK_OUT16((IoC), XMA((Mac), (Reg) + 6), (SK_U16) \
4455 (((SK_U16)(pByte[6]) & 0x00ff)| \
4456 (((SK_U16)(pByte[7]) << 8) & 0xff00))); \
4457 }
4458@@ -1866,12 +2793,12 @@
4459 *
4460 * GM_IN16(), to read a 16 bit register (e.g. GM_GP_STAT)
4461 * GM_OUT16(), to write a 16 bit register (e.g. GM_GP_CTRL)
4462- * GM_IN32(), to read a 32 bit register (e.g. GM_)
4463- * GM_OUT32(), to write a 32 bit register (e.g. GM_)
4464+ * GM_IN32(), to read a 32 bit register (e.g. GM_RXF_UC_OK)
4465+ * GM_OUT32(), to write a 32 bit register
4466 * GM_INADDR(), to read a network address register (e.g. GM_SRC_ADDR_1L)
4467 * GM_OUTADDR(), to write a network address register (e.g. GM_SRC_ADDR_2L)
4468- * GM_INHASH(), to read the GM_MC_ADDR_H1 register
4469- * GM_OUTHASH() to write the GM_MC_ADDR_H1 register
4470+ * GM_INHASH(), to read the hash registers (e.g. GM_MC_ADDR_H1..4)
4471+ * GM_OUTHASH() to write the hash registers (e.g. GM_MC_ADDR_H1..4)
4472 *
4473 * para:
4474 * Mac GMAC to access values: MAC_1 or MAC_2
4475@@ -1885,22 +2812,31 @@
4476 #define GMA(Mac, Reg) \
4477 ((BASE_GMAC_1 + (Mac) * (BASE_GMAC_2 - BASE_GMAC_1)) | (Reg))
4478
4479-#define GM_IN16(IoC, Mac, Reg, pVal) \
4480- SK_IN16((IoC), GMA((Mac), (Reg)), (pVal))
4481+#define GM_IN16(IoC, Mac, Reg, pVal) \
4482+ SK_IN16(IoC, GMA(Mac, Reg), pVal)
4483
4484-#define GM_OUT16(IoC, Mac, Reg, Val) \
4485- SK_OUT16((IoC), GMA((Mac), (Reg)), (Val))
4486+#define GM_OUT16(IoC, Mac, Reg, Val) \
4487+ SK_OUT16(IoC, GMA(Mac, Reg), Val)
4488
4489-#define GM_IN32(IoC, Mac, Reg, pVal) { \
4490- SK_IN16((IoC), GMA((Mac), (Reg)), \
4491- (SK_U16 SK_FAR*)&((SK_U16 SK_FAR*)(pVal))[XM_WORD_LO]); \
4492- SK_IN16((IoC), GMA((Mac), (Reg+4)), \
4493- (SK_U16 SK_FAR*)&((SK_U16 SK_FAR*)(pVal))[XM_WORD_HI]); \
4494+#ifdef SK_LITTLE_ENDIAN
4495+
4496+#define GM_IN32(IoC, Mac, Reg, pVal) { \
4497+ SK_IN16(IoC, GMA(Mac, Reg), (SK_U16 SK_FAR *)(pVal)); \
4498+ SK_IN16((IoC), GMA(Mac, (Reg) + 4), (SK_U16 SK_FAR *)(pVal) + 1); \
4499 }
4500
4501+#else /* !SK_LITTLE_ENDIAN */
4502+
4503+#define GM_IN32(IoC, Mac, Reg, pVal) { \
4504+ SK_IN16(IoC, GMA(Mac, Reg), (SK_U16 SK_FAR *)(pVal) + 1); \
4505+ SK_IN16(IoC, GMA(Mac, (Reg) + 4), (SK_U16 SK_FAR *)(pVal)); \
4506+}
4507+
4508+#endif /* !SK_LITTLE_ENDIAN */
4509+
4510 #define GM_OUT32(IoC, Mac, Reg, Val) { \
4511- SK_OUT16((IoC), GMA((Mac), (Reg)), (SK_U16)((Val) & 0xffffL)); \
4512- SK_OUT16((IoC), GMA((Mac), (Reg+4)), (SK_U16)(((Val) >> 16) & 0xffffL));\
4513+ SK_OUT16(IoC, GMA(Mac, Reg), (SK_U16)((Val) & 0xffffL)); \
4514+ SK_OUT16(IoC, GMA(Mac, (Reg) + 4), (SK_U16)(((Val) >> 16) & 0xffffL)); \
4515 }
4516
4517 #define GM_INADDR(IoC, Mac, Reg, pVal) { \
4518@@ -1908,13 +2844,13 @@
4519 SK_U8 *pByte; \
4520 pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \
4521 SK_IN16((IoC), GMA((Mac), (Reg)), &Word); \
4522- pByte[0] = (SK_U8)(Word & 0x00ff); \
4523+ pByte[0] = (SK_U8)(Word & 0x00ff); \
4524 pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \
4525- SK_IN16((IoC), GMA((Mac), (Reg+4)), &Word); \
4526- pByte[2] = (SK_U8)(Word & 0x00ff); \
4527+ SK_IN16((IoC), GMA((Mac), (Reg) + 4), &Word); \
4528+ pByte[2] = (SK_U8)(Word & 0x00ff); \
4529 pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \
4530- SK_IN16((IoC), GMA((Mac), (Reg+8)), &Word); \
4531- pByte[4] = (SK_U8)(Word & 0x00ff); \
4532+ SK_IN16((IoC), GMA((Mac), (Reg) + 8), &Word); \
4533+ pByte[4] = (SK_U8)(Word & 0x00ff); \
4534 pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \
4535 }
4536
4537@@ -1924,10 +2860,10 @@
4538 SK_OUT16((IoC), GMA((Mac), (Reg)), (SK_U16) \
4539 (((SK_U16)(pByte[0]) & 0x00ff) | \
4540 (((SK_U16)(pByte[1]) << 8) & 0xff00))); \
4541- SK_OUT16((IoC), GMA((Mac), (Reg+4)), (SK_U16) \
4542+ SK_OUT16((IoC), GMA((Mac), (Reg) + 4), (SK_U16) \
4543 (((SK_U16)(pByte[2]) & 0x00ff) | \
4544 (((SK_U16)(pByte[3]) << 8) & 0xff00))); \
4545- SK_OUT16((IoC), GMA((Mac), (Reg+8)), (SK_U16) \
4546+ SK_OUT16((IoC), GMA((Mac), (Reg) + 8), (SK_U16) \
4547 (((SK_U16)(pByte[4]) & 0x00ff) | \
4548 (((SK_U16)(pByte[5]) << 8) & 0xff00))); \
4549 }
4550@@ -1937,16 +2873,16 @@
4551 SK_U8 *pByte; \
4552 pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \
4553 SK_IN16((IoC), GMA((Mac), (Reg)), &Word); \
4554- pByte[0] = (SK_U8)(Word & 0x00ff); \
4555+ pByte[0] = (SK_U8)(Word & 0x00ff); \
4556 pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \
4557- SK_IN16((IoC), GMA((Mac), (Reg+4)), &Word); \
4558- pByte[2] = (SK_U8)(Word & 0x00ff); \
4559+ SK_IN16((IoC), GMA((Mac), (Reg) + 4), &Word); \
4560+ pByte[2] = (SK_U8)(Word & 0x00ff); \
4561 pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \
4562- SK_IN16((IoC), GMA((Mac), (Reg+8)), &Word); \
4563- pByte[4] = (SK_U8)(Word & 0x00ff); \
4564+ SK_IN16((IoC), GMA((Mac), (Reg) + 8), &Word); \
4565+ pByte[4] = (SK_U8)(Word & 0x00ff); \
4566 pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \
4567- SK_IN16((IoC), GMA((Mac), (Reg+12)), &Word); \
4568- pByte[6] = (SK_U8)(Word & 0x00ff); \
4569+ SK_IN16((IoC), GMA((Mac), (Reg) + 12), &Word); \
4570+ pByte[6] = (SK_U8)(Word & 0x00ff); \
4571 pByte[7] = (SK_U8)((Word >> 8) & 0x00ff); \
4572 }
4573
4574@@ -1956,13 +2892,13 @@
4575 SK_OUT16((IoC), GMA((Mac), (Reg)), (SK_U16) \
4576 (((SK_U16)(pByte[0]) & 0x00ff)| \
4577 (((SK_U16)(pByte[1]) << 8) & 0xff00))); \
4578- SK_OUT16((IoC), GMA((Mac), (Reg+4)), (SK_U16) \
4579+ SK_OUT16((IoC), GMA((Mac), (Reg) + 4), (SK_U16) \
4580 (((SK_U16)(pByte[2]) & 0x00ff)| \
4581 (((SK_U16)(pByte[3]) << 8) & 0xff00))); \
4582- SK_OUT16((IoC), GMA((Mac), (Reg+8)), (SK_U16) \
4583+ SK_OUT16((IoC), GMA((Mac), (Reg) + 8), (SK_U16) \
4584 (((SK_U16)(pByte[4]) & 0x00ff)| \
4585 (((SK_U16)(pByte[5]) << 8) & 0xff00))); \
4586- SK_OUT16((IoC), GMA((Mac), (Reg+12)), (SK_U16) \
4587+ SK_OUT16((IoC), GMA((Mac), (Reg) + 12), (SK_U16) \
4588 (((SK_U16)(pByte[6]) & 0x00ff)| \
4589 (((SK_U16)(pByte[7]) << 8) & 0xff00))); \
4590 }
4591@@ -1980,8 +2916,8 @@
4592 #define SK_PHY_BCOM 1 /* Broadcom BCM5400 */
4593 #define SK_PHY_LONE 2 /* Level One LXT1000 */
4594 #define SK_PHY_NAT 3 /* National DP83891 */
4595-#define SK_PHY_MARV_COPPER 4 /* Marvell 88E1011S */
4596-#define SK_PHY_MARV_FIBER 5 /* Marvell 88E1011S working on fiber */
4597+#define SK_PHY_MARV_COPPER 4 /* Marvell 88E1040S */
4598+#define SK_PHY_MARV_FIBER 5 /* Marvell 88E1040S working on fiber */
4599
4600 /*
4601 * PHY addresses (bits 12..8 of PHY address reg)
4602@@ -2010,30 +2946,30 @@
4603 *
4604 * usage: PHY_READ(IoC, pPort, MAC_1, PHY_CTRL, Value);
4605 * Warning: a PHY_READ on an uninitialized PHY (PHY still in reset) never
4606- * comes back. This is checked in DEBUG mode.
4607+ * comes back. This is checked in DEBUG mode.
4608 */
4609 #ifndef DEBUG
4610 #define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) { \
4611- SK_U16 Mmu; \
4612+ SK_U16 Mmu; \
4613 \
4614 XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \
4615 XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
4616 if ((pPort)->PhyType != SK_PHY_XMAC) { \
4617- do { \
4618+ do { \
4619 XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
4620 } while ((Mmu & XM_MMU_PHY_RDY) == 0); \
4621 XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
4622- } \
4623+ } \
4624 }
4625 #else
4626 #define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) { \
4627- SK_U16 Mmu; \
4628+ SK_U16 Mmu; \
4629 int __i = 0; \
4630 \
4631 XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \
4632 XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
4633 if ((pPort)->PhyType != SK_PHY_XMAC) { \
4634- do { \
4635+ do { \
4636 XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
4637 __i++; \
4638 if (__i > 100000) { \
4639@@ -2044,7 +2980,7 @@
4640 } \
4641 } while ((Mmu & XM_MMU_PHY_RDY) == 0); \
4642 XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
4643- } \
4644+ } \
4645 }
4646 #endif /* DEBUG */
4647
4648@@ -2052,17 +2988,17 @@
4649 SK_U16 Mmu; \
4650 \
4651 if ((pPort)->PhyType != SK_PHY_XMAC) { \
4652- do { \
4653+ do { \
4654 XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
4655 } while ((Mmu & XM_MMU_PHY_BUSY) != 0); \
4656- } \
4657+ } \
4658 XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \
4659 XM_OUT16((IoC), (Mac), XM_PHY_DATA, (Val)); \
4660 if ((pPort)->PhyType != SK_PHY_XMAC) { \
4661- do { \
4662+ do { \
4663 XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
4664 } while ((Mmu & XM_MMU_PHY_BUSY) != 0); \
4665- } \
4666+ } \
4667 }
4668
4669 /*
4670@@ -2071,12 +3007,14 @@
4671 * Use this macro to access PCI config register from the I/O space.
4672 *
4673 * para:
4674+ * pAC Pointer to adapter context
4675 * Addr PCI configuration register to access.
4676 * Values: PCI_VENDOR_ID ... PCI_VPD_ADR_REG,
4677 *
4678- * usage SK_IN16(pAC, PCI_C(PCI_VENDOR_ID), pVal);
4679+ * usage SK_IN16(IoC, PCI_C(pAC, PCI_VENDOR_ID), pVal);
4680 */
4681-#define PCI_C(Addr) (B7_CFG_SPC + (Addr)) /* PCI Config Space */
4682+#define PCI_C(p, Addr) \
4683+ (((CHIP_ID_YUKON_2(p)) ? Y2_CFG_SPC : B7_CFG_SPC) + (Addr))
4684
4685 /*
4686 * Macro SK_HW_ADDR(Base, Addr)
4687@@ -2088,7 +3026,7 @@
4688 * Addr Address offset
4689 *
4690 * usage: May be used in SK_INxx and SK_OUTxx macros
4691- * #define SK_IN8(pAC, Addr, pVal) ...\
4692+ * #define SK_IN8(IoC, Addr, pVal) ...\
4693 * *pVal = (SK_U8)inp(SK_HW_ADDR(pAC->Hw.Iop, Addr)))
4694 */
4695 #ifdef SK_MEM_MAPPED_IO
4696@@ -2107,20 +3045,31 @@
4697 * para:
4698 * pAC Pointer to adapter context struct
4699 * IoC I/O context needed for SK I/O macros
4700- * Port Port number
4701+ * Port Port number
4702 * Mode Mode to set for this LED
4703 */
4704 #define SK_HWAC_LINK_LED(pAC, IoC, Port, Mode) \
4705 SK_OUT8(IoC, MR_ADDR(Port, LNK_LED_REG), Mode);
4706
4707+#define SK_SET_GP_IO(IoC, Bit) { \
4708+ SK_U32 DWord; \
4709+ SK_IN32(IoC, B2_GP_IO, &DWord); \
4710+ DWord |= ((GP_DIR_0 | GP_IO_0) << (Bit));\
4711+ SK_OUT32(IoC, B2_GP_IO, DWord); \
4712+}
4713
4714-/* typedefs *******************************************************************/
4715-
4716+#define SK_CLR_GP_IO(IoC, Bit) { \
4717+ SK_U32 DWord; \
4718+ SK_IN32(IoC, B2_GP_IO, &DWord); \
4719+ DWord &= ~((GP_DIR_0 | GP_IO_0) << (Bit));\
4720+ SK_OUT32(IoC, B2_GP_IO, DWord); \
4721+}
4722
4723-/* function prototypes ********************************************************/
4724+#define SK_GE_PCI_FIFO_SIZE 1600 /* PCI FIFO Size */
4725
4726 #ifdef __cplusplus
4727 }
4728 #endif /* __cplusplus */
4729
4730 #endif /* __INC_SKGEHW_H */
4731+
4732diff -urN linux-2.6.17.orig/drivers/net/sk98lin/h/skgehwt.h linux-2.6.17/drivers/net/sk98lin/h/skgehwt.h
4733--- linux-2.6.17.orig/drivers/net/sk98lin/h/skgehwt.h 2006-06-22 13:17:16.000000000 +0200
4734+++ linux-2.6.17/drivers/net/sk98lin/h/skgehwt.h 2006-04-27 11:43:44.000000000 +0200
4735@@ -2,8 +2,8 @@
4736 *
4737 * Name: skhwt.h
4738 * Project: Gigabit Ethernet Adapters, Event Scheduler Module
4739- * Version: $Revision$
4740- * Date: $Date$
4741+ * Version: $Revision$
4742+ * Date: $Date$
4743 * Purpose: Defines for the hardware timer functions
4744 *
4745 ******************************************************************************/
4746diff -urN linux-2.6.17.orig/drivers/net/sk98lin/h/skgei2c.h linux-2.6.17/drivers/net/sk98lin/h/skgei2c.h
4747--- linux-2.6.17.orig/drivers/net/sk98lin/h/skgei2c.h 2006-06-22 13:17:16.000000000 +0200
4748+++ linux-2.6.17/drivers/net/sk98lin/h/skgei2c.h 1970-01-01 01:00:00.000000000 +0100
4749@@ -1,210 +0,0 @@
4750-/******************************************************************************
4751- *
4752- * Name: skgei2c.h
4753- * Project: Gigabit Ethernet Adapters, TWSI-Module
4754- * Version: $Revision$
4755- * Date: $Date$
4756- * Purpose: Special defines for TWSI
4757- *
4758- ******************************************************************************/
4759-
4760-/******************************************************************************
4761- *
4762- * (C)Copyright 1998-2002 SysKonnect.
4763- * (C)Copyright 2002-2003 Marvell.
4764- *
4765- * This program is free software; you can redistribute it and/or modify
4766- * it under the terms of the GNU General Public License as published by
4767- * the Free Software Foundation; either version 2 of the License, or
4768- * (at your option) any later version.
4769- *
4770- * The information in this file is provided "AS IS" without warranty.
4771- *
4772- ******************************************************************************/
4773-
4774-/*
4775- * SKGEI2C.H contains all SK-98xx specific defines for the TWSI handling
4776- */
4777-
4778-#ifndef _INC_SKGEI2C_H_
4779-#define _INC_SKGEI2C_H_
4780-
4781-/*
4782- * Macros to access the B2_I2C_CTRL
4783- */
4784-#define SK_I2C_CTL(IoC, flag, dev, dev_size, reg, burst) \
4785- SK_OUT32(IoC, B2_I2C_CTRL,\
4786- (flag ? 0x80000000UL : 0x0L) | \
4787- (((SK_U32)reg << 16) & I2C_ADDR) | \
4788- (((SK_U32)dev << 9) & I2C_DEV_SEL) | \
4789- (dev_size & I2C_DEV_SIZE) | \
4790- ((burst << 4) & I2C_BURST_LEN))
4791-
4792-#define SK_I2C_STOP(IoC) { \
4793- SK_U32 I2cCtrl; \
4794- SK_IN32(IoC, B2_I2C_CTRL, &I2cCtrl); \
4795- SK_OUT32(IoC, B2_I2C_CTRL, I2cCtrl | I2C_STOP); \
4796-}
4797-
4798-#define SK_I2C_GET_CTL(IoC, pI2cCtrl) SK_IN32(IoC, B2_I2C_CTRL, pI2cCtrl)
4799-
4800-/*
4801- * Macros to access the TWSI SW Registers
4802- */
4803-#define SK_I2C_SET_BIT(IoC, SetBits) { \
4804- SK_U8 OrgBits; \
4805- SK_IN8(IoC, B2_I2C_SW, &OrgBits); \
4806- SK_OUT8(IoC, B2_I2C_SW, OrgBits | (SK_U8)(SetBits)); \
4807-}
4808-
4809-#define SK_I2C_CLR_BIT(IoC, ClrBits) { \
4810- SK_U8 OrgBits; \
4811- SK_IN8(IoC, B2_I2C_SW, &OrgBits); \
4812- SK_OUT8(IoC, B2_I2C_SW, OrgBits & ~((SK_U8)(ClrBits))); \
4813-}
4814-
4815-#define SK_I2C_GET_SW(IoC, pI2cSw) SK_IN8(IoC, B2_I2C_SW, pI2cSw)
4816-
4817-/*
4818- * define the possible sensor states
4819- */
4820-#define SK_SEN_IDLE 0 /* Idle: sensor not read */
4821-#define SK_SEN_VALUE 1 /* Value Read cycle */
4822-#define SK_SEN_VALEXT 2 /* Extended Value Read cycle */
4823-
4824-/*
4825- * Conversion factor to convert read Voltage sensor to milli Volt
4826- * Conversion factor to convert read Temperature sensor to 10th degree Celsius
4827- */
4828-#define SK_LM80_VT_LSB 22 /* 22mV LSB resolution */
4829-#define SK_LM80_TEMP_LSB 10 /* 1 degree LSB resolution */
4830-#define SK_LM80_TEMPEXT_LSB 5 /* 0.5 degree LSB resolution for ext. val. */
4831-
4832-/*
4833- * formula: counter = (22500*60)/(rpm * divisor * pulses/2)
4834- * assuming: 6500rpm, 4 pulses, divisor 1
4835- */
4836-#define SK_LM80_FAN_FAKTOR ((22500L*60)/(1*2))
4837-
4838-/*
4839- * Define sensor management data
4840- * Maximum is reached on Genesis copper dual port and Yukon-64
4841- * Board specific maximum is in pAC->I2c.MaxSens
4842- */
4843-#define SK_MAX_SENSORS 8 /* maximal no. of installed sensors */
4844-#define SK_MIN_SENSORS 5 /* minimal no. of installed sensors */
4845-
4846-/*
4847- * To watch the state machine (SM) use the timer in two ways
4848- * instead of one as hitherto
4849- */
4850-#define SK_TIMER_WATCH_SM 0 /* Watch the SM to finish in a spec. time */
4851-#define SK_TIMER_NEW_GAUGING 1 /* Start a new gauging when timer expires */
4852-
4853-/*
4854- * Defines for the individual thresholds
4855- */
4856-
4857-/* Temperature sensor */
4858-#define SK_SEN_TEMP_HIGH_ERR 800 /* Temperature High Err Threshold */
4859-#define SK_SEN_TEMP_HIGH_WARN 700 /* Temperature High Warn Threshold */
4860-#define SK_SEN_TEMP_LOW_WARN 100 /* Temperature Low Warn Threshold */
4861-#define SK_SEN_TEMP_LOW_ERR 0 /* Temperature Low Err Threshold */
4862-
4863-/* VCC which should be 5 V */
4864-#define SK_SEN_PCI_5V_HIGH_ERR 5588 /* Voltage PCI High Err Threshold */
4865-#define SK_SEN_PCI_5V_HIGH_WARN 5346 /* Voltage PCI High Warn Threshold */
4866-#define SK_SEN_PCI_5V_LOW_WARN 4664 /* Voltage PCI Low Warn Threshold */
4867-#define SK_SEN_PCI_5V_LOW_ERR 4422 /* Voltage PCI Low Err Threshold */
4868-
4869-/*
4870- * VIO may be 5 V or 3.3 V. Initialization takes two parts:
4871- * 1. Initialize lowest lower limit and highest higher limit.
4872- * 2. After the first value is read correct the upper or the lower limit to
4873- * the appropriate C constant.
4874- *
4875- * Warning limits are +-5% of the exepected voltage.
4876- * Error limits are +-10% of the expected voltage.
4877- */
4878-
4879-/* Bug fix AF: 16.Aug.2001: Correct the init base of LM80 sensor */
4880-
4881-#define SK_SEN_PCI_IO_5V_HIGH_ERR 5566 /* + 10% V PCI-IO High Err Threshold */
4882-#define SK_SEN_PCI_IO_5V_HIGH_WARN 5324 /* + 5% V PCI-IO High Warn Threshold */
4883- /* 5000 mVolt */
4884-#define SK_SEN_PCI_IO_5V_LOW_WARN 4686 /* - 5% V PCI-IO Low Warn Threshold */
4885-#define SK_SEN_PCI_IO_5V_LOW_ERR 4444 /* - 10% V PCI-IO Low Err Threshold */
4886-
4887-#define SK_SEN_PCI_IO_RANGE_LIMITER 4000 /* 4000 mV range delimiter */
4888-
4889-/* correction values for the second pass */
4890-#define SK_SEN_PCI_IO_3V3_HIGH_ERR 3850 /* + 15% V PCI-IO High Err Threshold */
4891-#define SK_SEN_PCI_IO_3V3_HIGH_WARN 3674 /* + 10% V PCI-IO High Warn Threshold */
4892- /* 3300 mVolt */
4893-#define SK_SEN_PCI_IO_3V3_LOW_WARN 2926 /* - 10% V PCI-IO Low Warn Threshold */
4894-#define SK_SEN_PCI_IO_3V3_LOW_ERR 2772 /* - 15% V PCI-IO Low Err Threshold */
4895-
4896-/*
4897- * VDD voltage
4898- */
4899-#define SK_SEN_VDD_HIGH_ERR 3630 /* Voltage ASIC High Err Threshold */
4900-#define SK_SEN_VDD_HIGH_WARN 3476 /* Voltage ASIC High Warn Threshold */
4901-#define SK_SEN_VDD_LOW_WARN 3146 /* Voltage ASIC Low Warn Threshold */
4902-#define SK_SEN_VDD_LOW_ERR 2970 /* Voltage ASIC Low Err Threshold */
4903-
4904-/*
4905- * PHY PLL 3V3 voltage
4906- */
4907-#define SK_SEN_PLL_3V3_HIGH_ERR 3630 /* Voltage PMA High Err Threshold */
4908-#define SK_SEN_PLL_3V3_HIGH_WARN 3476 /* Voltage PMA High Warn Threshold */
4909-#define SK_SEN_PLL_3V3_LOW_WARN 3146 /* Voltage PMA Low Warn Threshold */
4910-#define SK_SEN_PLL_3V3_LOW_ERR 2970 /* Voltage PMA Low Err Threshold */
4911-
4912-/*
4913- * VAUX (YUKON only)
4914- */
4915-#define SK_SEN_VAUX_3V3_HIGH_ERR 3630 /* Voltage VAUX High Err Threshold */
4916-#define SK_SEN_VAUX_3V3_HIGH_WARN 3476 /* Voltage VAUX High Warn Threshold */
4917-#define SK_SEN_VAUX_3V3_LOW_WARN 3146 /* Voltage VAUX Low Warn Threshold */
4918-#define SK_SEN_VAUX_3V3_LOW_ERR 2970 /* Voltage VAUX Low Err Threshold */
4919-#define SK_SEN_VAUX_0V_WARN_ERR 0 /* if VAUX not present */
4920-#define SK_SEN_VAUX_RANGE_LIMITER 1000 /* 1000 mV range delimiter */
4921-
4922-/*
4923- * PHY 2V5 voltage
4924- */
4925-#define SK_SEN_PHY_2V5_HIGH_ERR 2750 /* Voltage PHY High Err Threshold */
4926-#define SK_SEN_PHY_2V5_HIGH_WARN 2640 /* Voltage PHY High Warn Threshold */
4927-#define SK_SEN_PHY_2V5_LOW_WARN 2376 /* Voltage PHY Low Warn Threshold */
4928-#define SK_SEN_PHY_2V5_LOW_ERR 2222 /* Voltage PHY Low Err Threshold */
4929-
4930-/*
4931- * ASIC Core 1V5 voltage (YUKON only)
4932- */
4933-#define SK_SEN_CORE_1V5_HIGH_ERR 1650 /* Voltage ASIC Core High Err Threshold */
4934-#define SK_SEN_CORE_1V5_HIGH_WARN 1575 /* Voltage ASIC Core High Warn Threshold */
4935-#define SK_SEN_CORE_1V5_LOW_WARN 1425 /* Voltage ASIC Core Low Warn Threshold */
4936-#define SK_SEN_CORE_1V5_LOW_ERR 1350 /* Voltage ASIC Core Low Err Threshold */
4937-
4938-/*
4939- * FAN 1 speed
4940- */
4941-/* assuming: 6500rpm +-15%, 4 pulses,
4942- * warning at: 80 %
4943- * error at: 70 %
4944- * no upper limit
4945- */
4946-#define SK_SEN_FAN_HIGH_ERR 20000 /* FAN Speed High Err Threshold */
4947-#define SK_SEN_FAN_HIGH_WARN 20000 /* FAN Speed High Warn Threshold */
4948-#define SK_SEN_FAN_LOW_WARN 5200 /* FAN Speed Low Warn Threshold */
4949-#define SK_SEN_FAN_LOW_ERR 4550 /* FAN Speed Low Err Threshold */
4950-
4951-/*
4952- * Some Voltages need dynamic thresholds
4953- */
4954-#define SK_SEN_DYN_INIT_NONE 0 /* No dynamic init of thresholds */
4955-#define SK_SEN_DYN_INIT_PCI_IO 10 /* Init PCI-IO with new thresholds */
4956-#define SK_SEN_DYN_INIT_VAUX 11 /* Init VAUX with new thresholds */
4957-
4958-extern int SkLm80ReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen);
4959-#endif /* n_INC_SKGEI2C_H */
4960diff -urN linux-2.6.17.orig/drivers/net/sk98lin/h/skgeinit.h linux-2.6.17/drivers/net/sk98lin/h/skgeinit.h
4961--- linux-2.6.17.orig/drivers/net/sk98lin/h/skgeinit.h 2006-06-22 13:17:16.000000000 +0200
4962+++ linux-2.6.17/drivers/net/sk98lin/h/skgeinit.h 2006-04-27 11:43:44.000000000 +0200
4963@@ -2,23 +2,24 @@
4964 *
4965 * Name: skgeinit.h
4966 * Project: Gigabit Ethernet Adapters, Common Modules
4967- * Version: $Revision$
4968- * Date: $Date$
4969+ * Version: $Revision$
4970+ * Date: $Date$
4971 * Purpose: Structures and prototypes for the GE Init Module
4972 *
4973 ******************************************************************************/
4974
4975 /******************************************************************************
4976 *
4977+ * LICENSE:
4978 * (C)Copyright 1998-2002 SysKonnect.
4979- * (C)Copyright 2002-2003 Marvell.
4980+ * (C)Copyright 2002-2006 Marvell.
4981 *
4982 * This program is free software; you can redistribute it and/or modify
4983 * it under the terms of the GNU General Public License as published by
4984 * the Free Software Foundation; either version 2 of the License, or
4985 * (at your option) any later version.
4986- *
4987 * The information in this file is provided "AS IS" without warranty.
4988+ * /LICENSE
4989 *
4990 ******************************************************************************/
4991
4992@@ -60,14 +61,17 @@
4993 #define SK_XMIT_DUR 0x002faf08UL /* 50 ms */
4994 #define SK_BLK_DUR 0x01dcd650UL /* 500 ms */
4995
4996-#define SK_DPOLL_DEF 0x00ee6b28UL /* 250 ms at 62.5 MHz */
4997+#define SK_DPOLL_DEF 0x00ee6b28UL /* 250 ms at 62.5 MHz (Genesis) */
4998+#define SK_DPOLL_DEF_Y2 0x0000124fUL /* 75 us (Yukon-2) */
4999
5000 #define SK_DPOLL_MAX 0x00ffffffUL /* 268 ms at 62.5 MHz */
5001- /* 215 ms at 78.12 MHz */
5002+ /* 215 ms at 78.12 MHz (Yukon) */
5003
5004 #define SK_FACT_62 100 /* is given in percent */
5005-#define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */
5006+#define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */
5007 #define SK_FACT_78 125 /* on YUKON: 78.12 MHz */
5008+#define SK_FACT_100 161 /* on YUKON-FE: 100 MHz */
5009+#define SK_FACT_125 202 /* on YUKON-EC: 125 MHz */
5010
5011 /* Timeout values */
5012 #define SK_MAC_TO_53 72 /* MAC arbiter timeout */
5013@@ -82,11 +86,23 @@
5014 #define SK_RB_LLPP_S (10 * 1024) /* Lower Level for small Queues */
5015 #define SK_RB_LLPP_B (16 * 1024) /* Lower Level for big Queues */
5016
5017+/* Threshold values for Yukon-EC Ultra */
5018+#define SK_ECU_ULPP 0x0080 /* Upper Pause Threshold (multiples of 8) */
5019+#define SK_ECU_LLPP 0x0060 /* Lower Pause Threshold (multiples of 8) */
5020+#define SK_ECU_AE_THR 0x0180 /* Almost Empty Threshold */
5021+#define SK_ECU_TXFF_LEV 0x01a0 /* Tx BMU FIFO Level */
5022+
5023 #ifndef SK_BMU_RX_WM
5024-#define SK_BMU_RX_WM 0x600 /* BMU Rx Watermark */
5025+#define SK_BMU_RX_WM 0x600 /* BMU Rx Watermark */
5026 #endif
5027+
5028 #ifndef SK_BMU_TX_WM
5029-#define SK_BMU_TX_WM 0x600 /* BMU Tx Watermark */
5030+#define SK_BMU_TX_WM 0x600 /* BMU Tx Watermark */
5031+#endif
5032+
5033+/* performance sensitive drivers should set this define to 0x80 */
5034+#ifndef SK_BMU_RX_WM_PEX
5035+#define SK_BMU_RX_WM_PEX 0x600 /* BMU Rx Watermark for PEX */
5036 #endif
5037
5038 /* XMAC II Rx High Watermark */
5039@@ -98,37 +114,31 @@
5040 #define SK_XM_THR_MULL 0x01fb /* .. for multiple link usage */
5041 #define SK_XM_THR_JUMBO 0x03fc /* .. for jumbo frame usage */
5042
5043-/* values for GIPortUsage */
5044+/* values for PortUsage */
5045 #define SK_RED_LINK 1 /* redundant link usage */
5046 #define SK_MUL_LINK 2 /* multiple link usage */
5047 #define SK_JUMBO_LINK 3 /* driver uses jumbo frames */
5048
5049 /* Minimum RAM Buffer Rx Queue Size */
5050-#define SK_MIN_RXQ_SIZE 16 /* 16 kB */
5051+#define SK_MIN_RXQ_SIZE (((pAC)->GIni.GIYukon2) ? 10 : 16) /* 10/16 kB */
5052
5053 /* Minimum RAM Buffer Tx Queue Size */
5054-#define SK_MIN_TXQ_SIZE 16 /* 16 kB */
5055+#define SK_MIN_TXQ_SIZE (((pAC)->GIni.GIYukon2) ? 10 : 16) /* 10/16 kB */
5056
5057-/* Queue Size units */
5058-#define QZ_UNITS 0x7
5059+/* Queue Size units (Genesis/Yukon) */
5060+#define QZ_UNITS 7
5061 #define QZ_STEP 8
5062
5063+/* Queue Size units (Yukon-2) */
5064+#define QZ_STEP_Y2 1
5065+
5066 /* Percentage of queue size from whole memory */
5067 /* 80 % for receive */
5068-#define RAM_QUOTA_RX 80L
5069-/* 0% for sync transfer */
5070-#define RAM_QUOTA_SYNC 0L
5071+#define RAM_QUOTA_RX 80
5072+/* 0 % for sync transfer */
5073+#define RAM_QUOTA_SYNC 0
5074 /* the rest (20%) is taken for async transfer */
5075
5076-/* Get the rounded queue size in Bytes in 8k steps */
5077-#define ROUND_QUEUE_SIZE(SizeInBytes) \
5078- ((((unsigned long) (SizeInBytes) + (QZ_STEP*1024L)-1) / 1024) & \
5079- ~(QZ_STEP-1))
5080-
5081-/* Get the rounded queue size in KBytes in 8k steps */
5082-#define ROUND_QUEUE_SIZE_KB(Kilobytes) \
5083- ROUND_QUEUE_SIZE((Kilobytes) * 1024L)
5084-
5085 /* Types of RAM Buffer Queues */
5086 #define SK_RX_SRAM_Q 1 /* small receive queue */
5087 #define SK_RX_BRAM_Q 2 /* big receive queue */
5088@@ -167,11 +177,11 @@
5089
5090
5091 /* Link Speed Capabilities */
5092-#define SK_LSPEED_CAP_AUTO (1<<0) /* Automatic resolution */
5093-#define SK_LSPEED_CAP_10MBPS (1<<1) /* 10 Mbps */
5094-#define SK_LSPEED_CAP_100MBPS (1<<2) /* 100 Mbps */
5095-#define SK_LSPEED_CAP_1000MBPS (1<<3) /* 1000 Mbps */
5096-#define SK_LSPEED_CAP_INDETERMINATED (1<<4) /* indeterminated */
5097+#define SK_LSPEED_CAP_AUTO BIT_0S /* Automatic resolution */
5098+#define SK_LSPEED_CAP_10MBPS BIT_1S /* 10 Mbps */
5099+#define SK_LSPEED_CAP_100MBPS BIT_2S /* 100 Mbps */
5100+#define SK_LSPEED_CAP_1000MBPS BIT_3S /* 1000 Mbps */
5101+#define SK_LSPEED_CAP_INDETERMINATED BIT_4S /* indeterminated */
5102
5103 /* Link Speed Parameter */
5104 #define SK_LSPEED_AUTO 1 /* Automatic resolution */
5105@@ -189,11 +199,11 @@
5106
5107
5108 /* Link Capability Parameter */
5109-#define SK_LMODE_CAP_HALF (1<<0) /* Half Duplex Mode */
5110-#define SK_LMODE_CAP_FULL (1<<1) /* Full Duplex Mode */
5111-#define SK_LMODE_CAP_AUTOHALF (1<<2) /* AutoHalf Duplex Mode */
5112-#define SK_LMODE_CAP_AUTOFULL (1<<3) /* AutoFull Duplex Mode */
5113-#define SK_LMODE_CAP_INDETERMINATED (1<<4) /* indeterminated */
5114+#define SK_LMODE_CAP_HALF BIT_0S /* Half Duplex Mode */
5115+#define SK_LMODE_CAP_FULL BIT_1S /* Full Duplex Mode */
5116+#define SK_LMODE_CAP_AUTOHALF BIT_2S /* AutoHalf Duplex Mode */
5117+#define SK_LMODE_CAP_AUTOFULL BIT_3S /* AutoFull Duplex Mode */
5118+#define SK_LMODE_CAP_INDETERMINATED BIT_4S /* indeterminated */
5119
5120 /* Link Mode Current State */
5121 #define SK_LMODE_STAT_UNKNOWN 1 /* Unknown Duplex Mode */
5122@@ -204,7 +214,7 @@
5123 #define SK_LMODE_STAT_INDETERMINATED 6 /* indeterminated */
5124
5125 /* Flow Control Mode Parameter (and capabilities) */
5126-#define SK_FLOW_MODE_NONE 1 /* No Flow-Control */
5127+#define SK_FLOW_MODE_NONE 1 /* No Flow Control */
5128 #define SK_FLOW_MODE_LOC_SEND 2 /* Local station sends PAUSE */
5129 #define SK_FLOW_MODE_SYMMETRIC 3 /* Both stations may send PAUSE */
5130 #define SK_FLOW_MODE_SYM_OR_REM 4 /* Both stations may send PAUSE or
5131@@ -220,10 +230,10 @@
5132 #define SK_FLOW_STAT_INDETERMINATED 5 /* indeterminated */
5133
5134 /* Master/Slave Mode Capabilities */
5135-#define SK_MS_CAP_AUTO (1<<0) /* Automatic resolution */
5136-#define SK_MS_CAP_MASTER (1<<1) /* This station is master */
5137-#define SK_MS_CAP_SLAVE (1<<2) /* This station is slave */
5138-#define SK_MS_CAP_INDETERMINATED (1<<3) /* indeterminated */
5139+#define SK_MS_CAP_AUTO BIT_0S /* Automatic resolution */
5140+#define SK_MS_CAP_MASTER BIT_1S /* This station is master */
5141+#define SK_MS_CAP_SLAVE BIT_2S /* This station is slave */
5142+#define SK_MS_CAP_INDETERMINATED BIT_3S /* indeterminated */
5143
5144 /* Set Master/Slave Mode Parameter (and capabilities) */
5145 #define SK_MS_MODE_AUTO 1 /* Automatic resolution */
5146@@ -238,25 +248,25 @@
5147 #define SK_MS_STAT_FAULT 4 /* M/S resolution failed */
5148 #define SK_MS_STAT_INDETERMINATED 5 /* indeterminated */
5149
5150-/* parameter 'Mode' when calling SkXmSetRxCmd() */
5151-#define SK_STRIP_FCS_ON (1<<0) /* Enable FCS stripping of Rx frames */
5152-#define SK_STRIP_FCS_OFF (1<<1) /* Disable FCS stripping of Rx frames */
5153-#define SK_STRIP_PAD_ON (1<<2) /* Enable pad byte stripping of Rx fr */
5154-#define SK_STRIP_PAD_OFF (1<<3) /* Disable pad byte stripping of Rx fr */
5155-#define SK_LENERR_OK_ON (1<<4) /* Don't chk fr for in range len error */
5156-#define SK_LENERR_OK_OFF (1<<5) /* Check frames for in range len error */
5157-#define SK_BIG_PK_OK_ON (1<<6) /* Don't set Rx Error bit for big frames */
5158-#define SK_BIG_PK_OK_OFF (1<<7) /* Set Rx Error bit for big frames */
5159-#define SK_SELF_RX_ON (1<<8) /* Enable Rx of own packets */
5160-#define SK_SELF_RX_OFF (1<<9) /* Disable Rx of own packets */
5161+/* parameter 'Mode' when calling SkMacSetRxCmd() */
5162+#define SK_STRIP_FCS_ON BIT_0S /* Enable FCS stripping of Rx frames */
5163+#define SK_STRIP_FCS_OFF BIT_1S /* Disable FCS stripping of Rx frames */
5164+#define SK_STRIP_PAD_ON BIT_2S /* Enable pad byte stripping of Rx fr */
5165+#define SK_STRIP_PAD_OFF BIT_3S /* Disable pad byte stripping of Rx fr */
5166+#define SK_LENERR_OK_ON BIT_4S /* Don't chk fr for in range len error */
5167+#define SK_LENERR_OK_OFF BIT_5S /* Check frames for in range len error */
5168+#define SK_BIG_PK_OK_ON BIT_6S /* Don't set Rx Error bit for big frames */
5169+#define SK_BIG_PK_OK_OFF BIT_7S /* Set Rx Error bit for big frames */
5170+#define SK_SELF_RX_ON BIT_8S /* Enable Rx of own packets */
5171+#define SK_SELF_RX_OFF BIT_9S /* Disable Rx of own packets */
5172
5173 /* parameter 'Para' when calling SkMacSetRxTxEn() */
5174-#define SK_MAC_LOOPB_ON (1<<0) /* Enable MAC Loopback Mode */
5175-#define SK_MAC_LOOPB_OFF (1<<1) /* Disable MAC Loopback Mode */
5176-#define SK_PHY_LOOPB_ON (1<<2) /* Enable PHY Loopback Mode */
5177-#define SK_PHY_LOOPB_OFF (1<<3) /* Disable PHY Loopback Mode */
5178-#define SK_PHY_FULLD_ON (1<<4) /* Enable GMII Full Duplex */
5179-#define SK_PHY_FULLD_OFF (1<<5) /* Disable GMII Full Duplex */
5180+#define SK_MAC_LOOPB_ON BIT_0S /* Enable MAC Loopback Mode */
5181+#define SK_MAC_LOOPB_OFF BIT_1S /* Disable MAC Loopback Mode */
5182+#define SK_PHY_LOOPB_ON BIT_2S /* Enable PHY Loopback Mode */
5183+#define SK_PHY_LOOPB_OFF BIT_3S /* Disable PHY Loopback Mode */
5184+#define SK_PHY_FULLD_ON BIT_4S /* Enable GMII Full Duplex */
5185+#define SK_PHY_FULLD_OFF BIT_5S /* Disable GMII Full Duplex */
5186
5187 /* States of PState */
5188 #define SK_PRT_RESET 0 /* the port is reset */
5189@@ -266,18 +276,25 @@
5190
5191 /* PHY power down modes */
5192 #define PHY_PM_OPERATIONAL_MODE 0 /* PHY operational mode */
5193-#define PHY_PM_DEEP_SLEEP 1 /* coma mode --> minimal power */
5194+#define PHY_PM_DEEP_SLEEP 1 /* Coma mode --> minimal power */
5195 #define PHY_PM_IEEE_POWER_DOWN 2 /* IEEE 22.2.4.1.5 compl. power down */
5196-#define PHY_PM_ENERGY_DETECT 3 /* energy detect */
5197-#define PHY_PM_ENERGY_DETECT_PLUS 4 /* energy detect plus */
5198+#define PHY_PM_ENERGY_DETECT 3 /* Energy detect */
5199+#define PHY_PM_ENERGY_DETECT_PLUS 4 /* Energy detect plus */
5200+
5201+/* PCI Bus Types */
5202+#define SK_PCI_BUS BIT_0S /* normal PCI bus */
5203+#define SK_PCIX_BUS BIT_1S /* PCI-X bus */
5204+#define SK_PEX_BUS BIT_2S /* PCI-Express bus */
5205
5206 /* Default receive frame limit for Workaround of XMAC Errata */
5207 #define SK_DEF_RX_WA_LIM SK_CONSTU64(100)
5208
5209 /* values for GILedBlinkCtrl (LED Blink Control) */
5210-#define SK_ACT_LED_BLINK (1<<0) /* Active LED blinking */
5211-#define SK_DUP_LED_NORMAL (1<<1) /* Duplex LED normal */
5212-#define SK_LED_LINK100_ON (1<<2) /* Link 100M LED on */
5213+#define SK_ACT_LED_BLINK BIT_0S /* Active LED blinking */
5214+#define SK_DUP_LED_NORMAL BIT_1S /* Duplex LED normal */
5215+#define SK_LED_LINK100_ON BIT_2S /* Link 100M LED on */
5216+#define SK_DUAL_LED_ACT_LNK BIT_3S /* Dual LED ACT/LNK configuration */
5217+#define SK_LED_LINK_MUX_P60 BIT_4S /* Link LED muxed to pin 60 */
5218
5219 /* Link Partner Status */
5220 #define SK_LIPA_UNKNOWN 0 /* Link partner is in unknown state */
5221@@ -290,18 +307,174 @@
5222 /* Max. Auto-neg. timeouts before link detection in sense mode is reset */
5223 #define SK_MAX_ANEG_TO 10 /* Max. 10 times the sense mode is reset */
5224
5225+
5226+/******************************************************************************
5227+ *
5228+ * HW_FEATURE() macro
5229+ */
5230+
5231+/* DWORD 0: Features */
5232+#define HWF_FORCE_AUTO_NEG 0x04000000UL /* Force Auto-Negotiation */
5233+#define HWF_CLK_GATING_ENABLE 0x02000000UL /* Enable Clock Gating */
5234+#define HWF_RED_CORE_CLK_SUP 0x01000000UL /* Reduced Core Clock supp. */
5235+#define HWF_SYNC_TX_SUP 0x00800000UL /* Synch. Tx Queue available */
5236+#define HWF_SINGLE_PORT_DEVICE 0x00400000UL /* Device has only one LAN IF */
5237+#define HWF_JUMBO_FRAMES_SUP 0x00200000UL /* Jumbo Frames supported */
5238+#define HWF_TX_TCP_CSUM_SUP 0x00100000UL /* TCP Tx checksum supported */
5239+#define HWF_TX_UDP_CSUM_SUP 0x00080000UL /* UDP Tx checksum supported */
5240+#define HWF_RX_CSUM_SUP 0x00040000UL /* RX checksum supported */
5241+#define HWF_TCP_SEGM_SUP 0x00020000UL /* TCP segmentation supported */
5242+#define HWF_RSS_HASH_SUP 0x00010000UL /* RSS Hash supported */
5243+#define HWF_PORT_VLAN_SUP 0x00008000UL /* VLAN can be config per port*/
5244+#define HWF_ROLE_PARAM_SUP 0x00004000UL /* Role parameter supported */
5245+#define HWF_LOW_PMODE_SUP 0x00002000UL /* Low Power Mode supported */
5246+#define HWF_ENERGIE_DEMO_SUP 0x00001000UL /* Energy Detect mode supp. */
5247+#define HWF_SPEED1000_SUP 0x00000800UL /* Line Speed 1000 supported */
5248+#define HWF_SPEED100_SUP 0x00000400UL /* Line Speed 100 supported */
5249+#define HWF_SPEED10_SUP 0x00000200UL /* Line Speed 10 supported */
5250+#define HWF_AUTONEGSENSE_SUP 0x00000100UL /* Autoneg Sense supported */
5251+#define HWF_PHY_LOOPB_MD_SUP 0x00000080UL /* PHY loopback mode supp. */
5252+#define HWF_ASF_SUP 0x00000040UL /* ASF support possible */
5253+#define HWF_QS_STEPS_1KB 0x00000020UL /* The Rx/Tx queues can be */
5254+ /* configured with 1 kB res. */
5255+#define HWF_OWN_RAM_PER_PORT 0x00000010UL /* Each port has a separate */
5256+ /* RAM buffer */
5257+#define HWF_MIN_LED_IF 0x00000008UL /* Minimal LED interface */
5258+ /* (e.g. for Yukon-EC) */
5259+#define HWF_LIST_ELEMENTS_USED 0x00000004UL /* HW uses list elements */
5260+ /* (otherwise desc. are used) */
5261+#define HWF_GMAC_INSIDE 0x00000002UL /* Device contains GMAC */
5262+#define HWF_TWSI_PRESENT 0x00000001UL /* TWSI sensor bus present */
5263+
5264+/*-RMV- DWORD 1: Deviations */
5265+#define HWF_WA_DEV_4200 0x10200000UL /*-RMV- 4.200 (D3 Blue Screen)*/
5266+#define HWF_WA_DEV_4185CS 0x10100000UL /*-RMV- 4.185 (ECU 100 CS cal)*/
5267+#define HWF_WA_DEV_4185 0x10080000UL /*-RMV- 4.185 (ECU Tx h check)*/
5268+#define HWF_WA_DEV_4167 0x10040000UL /*-RMV- 4.167 (Rx OvSize Hang)*/
5269+#define HWF_WA_DEV_4152 0x10020000UL /*-RMV- 4.152 (RSS issue) */
5270+#define HWF_WA_DEV_4115 0x10010000UL /*-RMV- 4.115 (Rx MAC FIFO) */
5271+#define HWF_WA_DEV_4109 0x10008000UL /*-RMV- 4.109 (BIU hang) */
5272+#define HWF_WA_DEV_483 0x10004000UL /*-RMV- 4.83 (Rx TCP wrong) */
5273+#define HWF_WA_DEV_479 0x10002000UL /*-RMV- 4.79 (Rx BMU hang II) */
5274+#define HWF_WA_DEV_472 0x10001000UL /*-RMV- 4.72 (GPHY2 MDC clk) */
5275+#define HWF_WA_DEV_463 0x10000800UL /*-RMV- 4.63 (Rx BMU hang I) */
5276+#define HWF_WA_DEV_427 0x10000400UL /*-RMV- 4.27 (Tx Done Rep) */
5277+#define HWF_WA_DEV_42 0x10000200UL /*-RMV- 4.2 (pref unit burst) */
5278+#define HWF_WA_DEV_46 0x10000100UL /*-RMV- 4.6 (CPU crash II) */
5279+#define HWF_WA_DEV_43_418 0x10000080UL /*-RMV- 4.3 & 4.18 (PCI unexp */
5280+ /*-RMV- compl&Stat BMU deadl) */
5281+#define HWF_WA_DEV_420 0x10000040UL /*-RMV- 4.20 (Status BMU ov) */
5282+#define HWF_WA_DEV_423 0x10000020UL /*-RMV- 4.23 (TCP Segm Hang) */
5283+#define HWF_WA_DEV_424 0x10000010UL /*-RMV- 4.24 (MAC reg overwr) */
5284+#define HWF_WA_DEV_425 0x10000008UL /*-RMV- 4.25 (Magic packet */
5285+ /*-RMV- with odd offset) */
5286+#define HWF_WA_DEV_428 0x10000004UL /*-RMV- 4.28 (Poll-U &BigEndi)*/
5287+#define HWF_WA_FIFO_FLUSH_YLA0 0x10000002UL /*-RMV- dis Rx GMAC FIFO Flush*/
5288+ /*-RMV- for Yu-L Rev. A0 only */
5289+#define HWF_WA_COMA_MODE 0x10000001UL /*-RMV- Coma Mode WA req */
5290+
5291+/* DWORD 2: still unused */
5292+/* DWORD 3: still unused */
5293+
5294+
5295+/*
5296+ * HW_FEATURE() - returns whether the feature is serviced or not
5297+ */
5298+#define HW_FEATURE(pAC, ReqFeature) \
5299+ (((pAC)->GIni.HwF.Features[((ReqFeature) & 0x30000000UL) >> 28] &\
5300+ ((ReqFeature) & 0x0fffffffUL)) != 0)
5301+
5302+#define HW_FEAT_LIST 0
5303+#define HW_DEV_LIST 1
5304+
5305+#define SET_HW_FEATURE_MASK(pAC, List, OffMaskValue, OnMaskValue) { \
5306+ if ((List) == HW_FEAT_LIST || (List) == HW_DEV_LIST) { \
5307+ (pAC)->GIni.HwF.OffMask[List] = (OffMaskValue); \
5308+ (pAC)->GIni.HwF.OnMask[List] = (OnMaskValue); \
5309+ } \
5310+}
5311+
5312+/* driver access macros for GIni structure ***********************************/
5313+
5314+#define CHIP_ID_YUKON_2(pAC) ((pAC)->GIni.GIYukon2)
5315+
5316+#define HW_SYNC_TX_SUPPORTED(pAC) \
5317+ ((pAC)->GIni.GIChipId != CHIP_ID_YUKON_EC && \
5318+ (pAC)->GIni.GIChipId != CHIP_ID_YUKON_FE && \
5319+ (pAC)->GIni.GIChipId != CHIP_ID_YUKON_EC_U)
5320+
5321+#define HW_MS_TO_TICKS(pAC, MsTime) \
5322+ ((MsTime) * (62500L/100) * (pAC)->GIni.GIHstClkFact)
5323+
5324+#ifdef XXX
5325+/* still under construction */
5326+#define HW_IS_SINGLE_PORT(pAC) ((pAC)->GIni.GIMacsFound == 1)
5327+#define HW_NUMBER_OF_PORTS(pAC) ((pAC)->GIni.GIMacsFound)
5328+
5329+#define HW_TX_UDP_CSUM_SUPPORTED(pAC) \
5330+ ((((pAC)->GIni.GIChipId >= CHIP_ID_YUKON) && ((pAC)->GIni.GIChipRev != 0))
5331+
5332+#define HW_DEFAULT_LINESPEED(pAC) \
5333+ ((!(pAC)->GIni.GIGenesis && (pAC)->GIni.GICopperType) ? \
5334+ SK_LSPEED_AUTO : SK_LSPEED_1000MBPS)
5335+
5336+#define HW_ROLE_PARAM_SUPPORTED(pAC) ((pAC)->GIni.GICopperType)
5337+
5338+#define HW_SPEED1000_SUPPORTED(pAC, Port) \
5339+ ((pAC)->GIni.GP[Port].PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS)
5340+
5341+#define HW_SPEED100_SUPPORTED(pAC, Port) \
5342+ ((pAC)->GIni.GP[Port].PLinkSpeedCap & SK_LSPEED_CAP_100MBPS)
5343+
5344+#define HW_SPEED10_SUPPORTED(pAC, Port) \
5345+ ((pAC)->GIni.GP[Port].PLinkSpeedCap & SK_LSPEED_CAP_10MBPS)
5346+
5347+#define HW_AUTONEGSENSE_SUPPORTED(pAC) ((pAC)->GIni.GP[0].PhyType==SK_PHY_XMAC)
5348+
5349+#define HW_FREQ_TO_CARD_TICKS(pAC, AdapterClkSpeed, Freq) \
5350+ (((AdapterClkSpeed / 100) * (pAC)->GIni.GIHstClkFact) / Freq)
5351+
5352+#define HW_IS_LINK_UP(pAC, Port) ((pAC)->GIni.GP[Port].PHWLinkUp)
5353+#define HW_LINK_SPEED_USED(pAC, Port) ((pAC)->GIni.GP[Port].PLinkSpeedUsed)
5354+#define HW_RAM_SIZE(pAC) ((pAC)->GIni.GIRamSize)
5355+
5356+#define HW_PHY_LP_MODE_SUPPORTED(pAC) (pAC0->???
5357+#define HW_ASF_ACTIVE(pAC) ???
5358+#define RAWIO_OUT32(pAC, pAC->RegIrqMask, pAC->GIni.GIValIrqMask)...
5359+
5360+/* macro to check whether Tx checksum is supported */
5361+#define HW_TX_CSUM_SUPPORTED(pAC) ((pAC)->GIni.GIChipId != CHIP_ID_GENESIS)
5362+
5363+BMU_UDP_CHECK : BMU_TCP_CHECK;
5364+
5365+/* macro for - Own Bit mirrored to DWORD7 (Yukon LP receive descriptor) */
5366+#endif /* 0 */
5367+
5368+
5369 /* structures *****************************************************************/
5370
5371 /*
5372+ * HW Feature structure
5373+ */
5374+typedef struct s_HwFeatures {
5375+ SK_U32 Features[4]; /* Feature list */
5376+ SK_U32 OffMask[4]; /* Off Mask */
5377+ SK_U32 OnMask[4]; /* On Mask */
5378+} SK_HW_FEATURES;
5379+
5380+/*
5381 * MAC specific functions
5382 */
5383 typedef struct s_GeMacFunc {
5384- int (*pFnMacUpdateStats)(SK_AC *pAC, SK_IOC IoC, unsigned int Port);
5385- int (*pFnMacStatistic)(SK_AC *pAC, SK_IOC IoC, unsigned int Port,
5386- SK_U16 StatAddr, SK_U32 SK_FAR *pVal);
5387- int (*pFnMacResetCounter)(SK_AC *pAC, SK_IOC IoC, unsigned int Port);
5388- int (*pFnMacOverflow)(SK_AC *pAC, SK_IOC IoC, unsigned int Port,
5389- SK_U16 IStatus, SK_U64 SK_FAR *pVal);
5390+ int (*pFnMacUpdateStats)(SK_AC *, SK_IOC, unsigned int);
5391+ int (*pFnMacStatistic)(SK_AC *, SK_IOC, unsigned int, SK_U16, SK_U32 SK_FAR *);
5392+ int (*pFnMacResetCounter)(SK_AC *, SK_IOC, unsigned int);
5393+ int (*pFnMacOverflow)(SK_AC *, SK_IOC, unsigned int, SK_U16, SK_U64 SK_FAR *);
5394+ void (*pSkGeSirqIsr)(SK_AC *, SK_IOC, SK_U32);
5395+#ifdef SK_DIAG
5396+ int (*pFnMacPhyRead)(SK_AC *, SK_IOC, int, int, SK_U16 SK_FAR *);
5397+ int (*pFnMacPhyWrite)(SK_AC *, SK_IOC, int, int, SK_U16);
5398+#endif /* SK_DIAG */
5399 } SK_GEMACFUNC;
5400
5401 /*
5402@@ -311,7 +484,7 @@
5403 #ifndef SK_DIAG
5404 SK_TIMER PWaTimer; /* Workaround Timer */
5405 SK_TIMER HalfDupChkTimer;
5406-#endif /* SK_DIAG */
5407+#endif /* !SK_DIAG */
5408 SK_U32 PPrevShorts; /* Previous Short Counter checking */
5409 SK_U32 PPrevFcs; /* Previous FCS Error Counter checking */
5410 SK_U64 PPrevRx; /* Previous RxOk Counter checking */
5411@@ -335,6 +508,7 @@
5412 int PXaQOff; /* Asynchronous Tx Queue Address Offset */
5413 int PhyType; /* PHY used on this port */
5414 int PState; /* Port status (reset, stop, init, run) */
5415+ int PPortUsage; /* Driver Port Usage */
5416 SK_U16 PhyId1; /* PHY Id1 on this port */
5417 SK_U16 PhyAddr; /* MDIO/MDC PHY address */
5418 SK_U16 PIsave; /* Saved Interrupt status word */
5419@@ -348,7 +522,7 @@
5420 SK_U8 PLinkModeConf; /* Link Mode configured */
5421 SK_U8 PLinkMode; /* Link Mode currently used */
5422 SK_U8 PLinkModeStatus;/* Link Mode Status */
5423- SK_U8 PLinkSpeedCap; /* Link Speed Capabilities(10/100/1000 Mbps) */
5424+ SK_U8 PLinkSpeedCap; /* Link Speed Capabilities (10/100/1000 Mbps) */
5425 SK_U8 PLinkSpeed; /* configured Link Speed (10/100/1000 Mbps) */
5426 SK_U8 PLinkSpeedUsed; /* current Link Speed (10/100/1000 Mbps) */
5427 SK_U8 PFlowCtrlCap; /* Flow Control Capabilities */
5428@@ -367,7 +541,10 @@
5429 int PMacJamLen; /* MAC Jam length */
5430 int PMacJamIpgVal; /* MAC Jam IPG */
5431 int PMacJamIpgData; /* MAC IPG Jam to Data */
5432+ int PMacBackOffLim; /* MAC Back-off Limit */
5433+ int PMacDataBlind; /* MAC Data Blinder */
5434 int PMacIpgData; /* MAC Data IPG */
5435+ SK_U16 PMacAddr[3]; /* MAC address */
5436 SK_BOOL PMacLimit4; /* reset collision counter and backoff algorithm */
5437 } SK_GEPORT;
5438
5439@@ -379,27 +556,38 @@
5440 int GIChipId; /* Chip Identification Number */
5441 int GIChipRev; /* Chip Revision Number */
5442 SK_U8 GIPciHwRev; /* PCI HW Revision Number */
5443+ SK_U8 GIPciBus; /* PCI Bus Type (PCI / PCI-X / PCI-Express) */
5444+ SK_U8 GIPciMode; /* PCI / PCI-X Mode @ Clock */
5445+ SK_U8 GIPexWidth; /* PCI-Express Negotiated Link Width */
5446 SK_BOOL GIGenesis; /* Genesis adapter ? */
5447- SK_BOOL GIYukon; /* YUKON-A1/Bx chip */
5448+ SK_BOOL GIYukon; /* YUKON family (1 and 2) */
5449 SK_BOOL GIYukonLite; /* YUKON-Lite chip */
5450+ SK_BOOL GIYukon2; /* YUKON-2 chip (-XL, -EC or -FE) */
5451+ SK_U8 GIConTyp; /* Connector Type */
5452+ SK_U8 GIPmdTyp; /* PMD Type */
5453 SK_BOOL GICopperType; /* Copper Type adapter ? */
5454 SK_BOOL GIPciSlot64; /* 64-bit PCI Slot */
5455 SK_BOOL GIPciClock66; /* 66 MHz PCI Clock */
5456 SK_BOOL GIVauxAvail; /* VAUX available (YUKON) */
5457 SK_BOOL GIYukon32Bit; /* 32-Bit YUKON adapter */
5458+ SK_BOOL GIAsfEnabled; /* ASF subsystem enabled */
5459+ SK_BOOL GIAsfRunning; /* ASF subsystem running */
5460 SK_U16 GILedBlinkCtrl; /* LED Blink Control */
5461 int GIMacsFound; /* Number of MACs found on this adapter */
5462 int GIMacType; /* MAC Type used on this adapter */
5463- int GIHstClkFact; /* Host Clock Factor (62.5 / HstClk * 100) */
5464- int GIPortUsage; /* Driver Port Usage */
5465+ int GIChipCap; /* Adapter's Capabilities */
5466+ int GIHwResInfo; /* HW Resources / Application Information */
5467+ int GIHstClkFact; /* Host Clock Factor (HstClk / 62.5 * 100) */
5468 int GILevel; /* Initialization Level completed */
5469 int GIRamSize; /* The RAM size of the adapter in kB */
5470 int GIWolOffs; /* WOL Register Offset (HW-Bug in Rev. A) */
5471 SK_U32 GIRamOffs; /* RAM Address Offset for addr calculation */
5472 SK_U32 GIPollTimerVal; /* Descr. Poll Timer Init Val (HstClk ticks) */
5473 SK_U32 GIValIrqMask; /* Value for Interrupt Mask */
5474+ SK_U32 GIValHwIrqMask; /* Value for HWE Interrupt Mask */
5475 SK_U32 GITimeStampCnt; /* Time Stamp High Counter (YUKON only) */
5476 SK_GEPORT GP[SK_MAX_MACS];/* Port Dependent Information */
5477+ SK_HW_FEATURES HwF; /* HW Features struct */
5478 SK_GEMACFUNC GIFunc; /* MAC depedent functions */
5479 } SK_GEINIT;
5480
5481@@ -417,7 +605,7 @@
5482 #define SKERR_HWI_E005 (SKERR_HWI_E004+1)
5483 #define SKERR_HWI_E005MSG "SkGeInitPort(): cannot init running ports"
5484 #define SKERR_HWI_E006 (SKERR_HWI_E005+1)
5485-#define SKERR_HWI_E006MSG "SkGeMacInit(): PState does not match HW state"
5486+#define SKERR_HWI_E006MSG "SkGeInit() called with illegal Chip Id"
5487 #define SKERR_HWI_E007 (SKERR_HWI_E006+1)
5488 #define SKERR_HWI_E007MSG "SkXmInitDupMd() called with invalid Dup Mode"
5489 #define SKERR_HWI_E008 (SKERR_HWI_E007+1)
5490@@ -433,11 +621,11 @@
5491 #define SKERR_HWI_E013 (SKERR_HWI_E012+1)
5492 #define SKERR_HWI_E013MSG "SkGeInitPort(): cfg changed for running queue"
5493 #define SKERR_HWI_E014 (SKERR_HWI_E013+1)
5494-#define SKERR_HWI_E014MSG "SkGeInitPort(): unknown GIPortUsage specified"
5495+#define SKERR_HWI_E014MSG "SkGeInitPort(): unknown PortUsage specified"
5496 #define SKERR_HWI_E015 (SKERR_HWI_E014+1)
5497-#define SKERR_HWI_E015MSG "Illegal Link mode parameter"
5498+#define SKERR_HWI_E015MSG "Illegal Link Mode parameter"
5499 #define SKERR_HWI_E016 (SKERR_HWI_E015+1)
5500-#define SKERR_HWI_E016MSG "Illegal Flow control mode parameter"
5501+#define SKERR_HWI_E016MSG "Illegal Flow Control Mode parameter"
5502 #define SKERR_HWI_E017 (SKERR_HWI_E016+1)
5503 #define SKERR_HWI_E017MSG "Illegal value specified for GIPollTimerVal"
5504 #define SKERR_HWI_E018 (SKERR_HWI_E017+1)
5505@@ -447,15 +635,19 @@
5506 #define SKERR_HWI_E020 (SKERR_HWI_E019+1)
5507 #define SKERR_HWI_E020MSG "Illegal Master/Slave parameter"
5508 #define SKERR_HWI_E021 (SKERR_HWI_E020+1)
5509-#define SKERR_HWI_E021MSG "MacUpdateStats(): cannot update statistic counter"
5510-#define SKERR_HWI_E022 (SKERR_HWI_E021+1)
5511-#define SKERR_HWI_E022MSG "MacStatistic(): illegal statistic base address"
5512+#define SKERR_HWI_E021MSG "MacUpdateStats(): cannot update statistic counter"
5513+#define SKERR_HWI_E022 (SKERR_HWI_E021+1)
5514+#define SKERR_HWI_E022MSG "MacStatistic(): illegal statistic base address"
5515 #define SKERR_HWI_E023 (SKERR_HWI_E022+1)
5516 #define SKERR_HWI_E023MSG "SkGeInitPort(): Transmit Queue Size too small"
5517 #define SKERR_HWI_E024 (SKERR_HWI_E023+1)
5518 #define SKERR_HWI_E024MSG "FATAL: SkGeStopPort() does not terminate (Rx)"
5519 #define SKERR_HWI_E025 (SKERR_HWI_E024+1)
5520-#define SKERR_HWI_E025MSG ""
5521+#define SKERR_HWI_E025MSG "Link Partner not Auto-Neg. able"
5522+#define SKERR_HWI_E026 (SKERR_HWI_E025+1)
5523+#define SKERR_HWI_E026MSG "PEX negotiated Link width not max."
5524+#define SKERR_HWI_E027 (SKERR_HWI_E026+1)
5525+#define SKERR_HWI_E027MSG ""
5526
5527 /* function prototypes ********************************************************/
5528
5529@@ -464,6 +656,30 @@
5530 /*
5531 * public functions in skgeinit.c
5532 */
5533+extern void SkGePortVlan(
5534+ SK_AC *pAC,
5535+ SK_IOC IoC,
5536+ int Port,
5537+ SK_BOOL Enable);
5538+
5539+extern void SkGeRxRss(
5540+ SK_AC *pAC,
5541+ SK_IOC IoC,
5542+ int Port,
5543+ SK_BOOL Enable);
5544+
5545+extern void SkGeRxCsum(
5546+ SK_AC *pAC,
5547+ SK_IOC IoC,
5548+ int Port,
5549+ SK_BOOL Enable);
5550+
5551+extern void SkGePollRxD(
5552+ SK_AC *pAC,
5553+ SK_IOC IoC,
5554+ int Port,
5555+ SK_BOOL PollRxD);
5556+
5557 extern void SkGePollTxD(
5558 SK_AC *pAC,
5559 SK_IOC IoC,
5560@@ -516,11 +732,28 @@
5561 int Led,
5562 int Mode);
5563
5564+extern void SkGeInitRamIface(
5565+ SK_AC *pAC,
5566+ SK_IOC IoC);
5567+
5568 extern int SkGeInitAssignRamToQueues(
5569 SK_AC *pAC,
5570- int ActivePort,
5571+ int Port,
5572 SK_BOOL DualNet);
5573
5574+extern void DoInitRamQueue(
5575+ SK_AC *pAC,
5576+ SK_IOC IoC,
5577+ int QuIoOffs,
5578+ SK_U32 QuStartAddr,
5579+ SK_U32 QuEndAddr,
5580+ int QuType);
5581+
5582+extern int SkYuk2RestartRxBmu(
5583+ SK_AC *pAC,
5584+ SK_IOC IoC,
5585+ int Port);
5586+
5587 /*
5588 * public functions in skxmac2.c
5589 */
5590@@ -539,6 +772,11 @@
5591 SK_IOC IoC,
5592 int Port);
5593
5594+extern void SkMacClearRst(
5595+ SK_AC *pAC,
5596+ SK_IOC IoC,
5597+ int Port);
5598+
5599 extern void SkXmInitMac(
5600 SK_AC *pAC,
5601 SK_IOC IoC,
5602@@ -565,6 +803,11 @@
5603 SK_IOC IoC,
5604 int Port);
5605
5606+extern void SkMacFlushRxFifo(
5607+ SK_AC *pAC,
5608+ SK_IOC IoC,
5609+ int Port);
5610+
5611 extern void SkMacIrq(
5612 SK_AC *pAC,
5613 SK_IOC IoC,
5614@@ -581,7 +824,13 @@
5615 int Port,
5616 SK_U16 IStatus);
5617
5618-extern int SkMacRxTxEnable(
5619+extern void SkMacSetRxTxEn(
5620+ SK_AC *pAC,
5621+ SK_IOC IoC,
5622+ int Port,
5623+ int Para);
5624+
5625+extern int SkMacRxTxEnable(
5626 SK_AC *pAC,
5627 SK_IOC IoC,
5628 int Port);
5629@@ -598,28 +847,28 @@
5630 int Port,
5631 SK_BOOL Enable);
5632
5633-extern void SkXmPhyRead(
5634+extern int SkXmPhyRead(
5635 SK_AC *pAC,
5636 SK_IOC IoC,
5637 int Port,
5638 int Addr,
5639 SK_U16 SK_FAR *pVal);
5640
5641-extern void SkXmPhyWrite(
5642+extern int SkXmPhyWrite(
5643 SK_AC *pAC,
5644 SK_IOC IoC,
5645 int Port,
5646 int Addr,
5647 SK_U16 Val);
5648
5649-extern void SkGmPhyRead(
5650+extern int SkGmPhyRead(
5651 SK_AC *pAC,
5652 SK_IOC IoC,
5653 int Port,
5654 int Addr,
5655 SK_U16 SK_FAR *pVal);
5656
5657-extern void SkGmPhyWrite(
5658+extern int SkGmPhyWrite(
5659 SK_AC *pAC,
5660 SK_IOC IoC,
5661 int Port,
5662@@ -633,6 +882,16 @@
5663 int StartNum,
5664 int StopNum);
5665
5666+extern void SkXmInitDupMd(
5667+ SK_AC *pAC,
5668+ SK_IOC IoC,
5669+ int Port);
5670+
5671+extern void SkXmInitPauseMd(
5672+ SK_AC *pAC,
5673+ SK_IOC IoC,
5674+ int Port);
5675+
5676 extern void SkXmAutoNegLipaXmac(
5677 SK_AC *pAC,
5678 SK_IOC IoC,
5679@@ -677,7 +936,7 @@
5680 SK_AC *pAC,
5681 SK_IOC IoC,
5682 unsigned int Port,
5683- SK_U16 IStatus,
5684+ SK_U16 IStatus,
5685 SK_U64 SK_FAR *pStatus);
5686
5687 extern int SkGmOverflowStatus(
5688@@ -693,6 +952,19 @@
5689 int Port,
5690 SK_BOOL StartTest);
5691
5692+#ifdef SK_PHY_LP_MODE
5693+extern int SkGmEnterLowPowerMode(
5694+ SK_AC *pAC,
5695+ SK_IOC IoC,
5696+ int Port,
5697+ SK_U8 Mode);
5698+
5699+extern int SkGmLeaveLowPowerMode(
5700+ SK_AC *pAC,
5701+ SK_IOC IoC,
5702+ int Port);
5703+#endif /* SK_PHY_LP_MODE */
5704+
5705 #ifdef SK_DIAG
5706 extern void SkGePhyRead(
5707 SK_AC *pAC,
5708@@ -735,6 +1007,7 @@
5709 /*
5710 * public functions in skgeinit.c
5711 */
5712+extern void SkGePollRxD();
5713 extern void SkGePollTxD();
5714 extern void SkGeYellowLED();
5715 extern int SkGeCfgSync();
5716@@ -744,30 +1017,41 @@
5717 extern void SkGeDeInit();
5718 extern int SkGeInitPort();
5719 extern void SkGeXmitLED();
5720+extern void SkGeInitRamIface();
5721 extern int SkGeInitAssignRamToQueues();
5722+extern void SkGePortVlan();
5723+extern void SkGeRxCsum();
5724+extern void SkGeRxRss();
5725+extern void DoInitRamQueue();
5726+extern int SkYuk2RestartRxBmu();
5727
5728 /*
5729 * public functions in skxmac2.c
5730 */
5731-extern void SkMacRxTxDisable();
5732+extern void SkMacRxTxDisable();
5733 extern void SkMacSoftRst();
5734 extern void SkMacHardRst();
5735-extern void SkMacInitPhy();
5736-extern int SkMacRxTxEnable();
5737-extern void SkMacPromiscMode();
5738-extern void SkMacHashing();
5739-extern void SkMacIrqDisable();
5740+extern void SkMacClearRst();
5741+extern void SkMacInitPhy();
5742+extern int SkMacRxTxEnable();
5743+extern void SkMacPromiscMode();
5744+extern void SkMacHashing();
5745+extern void SkMacIrqDisable();
5746 extern void SkMacFlushTxFifo();
5747+extern void SkMacFlushRxFifo();
5748 extern void SkMacIrq();
5749 extern int SkMacAutoNegDone();
5750 extern void SkMacAutoNegLipaPhy();
5751+extern void SkMacSetRxTxEn();
5752 extern void SkXmInitMac();
5753-extern void SkXmPhyRead();
5754-extern void SkXmPhyWrite();
5755+extern int SkXmPhyRead();
5756+extern int SkXmPhyWrite();
5757 extern void SkGmInitMac();
5758-extern void SkGmPhyRead();
5759-extern void SkGmPhyWrite();
5760+extern int SkGmPhyRead();
5761+extern int SkGmPhyWrite();
5762 extern void SkXmClrExactAddr();
5763+extern void SkXmInitDupMd();
5764+extern void SkXmInitPauseMd();
5765 extern void SkXmAutoNegLipaXmac();
5766 extern int SkXmUpdateStats();
5767 extern int SkGmUpdateStats();
5768@@ -778,6 +1062,10 @@
5769 extern int SkXmOverflowStatus();
5770 extern int SkGmOverflowStatus();
5771 extern int SkGmCableDiagStatus();
5772+#ifdef SK_PHY_LP_MODE
5773+extern int SkGmEnterLowPowerMode();
5774+extern int SkGmLeaveLowPowerMode();
5775+#endif /* SK_PHY_LP_MODE */
5776
5777 #ifdef SK_DIAG
5778 extern void SkGePhyRead();
5779@@ -788,10 +1076,11 @@
5780 extern void SkXmSendCont();
5781 #endif /* SK_DIAG */
5782
5783-#endif /* SK_KR_PROTO */
5784+#endif /* SK_KR_PROTO */
5785
5786 #ifdef __cplusplus
5787 }
5788-#endif /* __cplusplus */
5789+#endif /* __cplusplus */
5790+
5791+#endif /* __INC_SKGEINIT_H_ */
5792
5793-#endif /* __INC_SKGEINIT_H_ */
5794diff -urN linux-2.6.17.orig/drivers/net/sk98lin/h/skgepnm2.h linux-2.6.17/drivers/net/sk98lin/h/skgepnm2.h
5795--- linux-2.6.17.orig/drivers/net/sk98lin/h/skgepnm2.h 2006-06-22 13:17:16.000000000 +0200
5796+++ linux-2.6.17/drivers/net/sk98lin/h/skgepnm2.h 2006-04-27 11:43:44.000000000 +0200
5797@@ -2,14 +2,15 @@
5798 *
5799 * Name: skgepnm2.h
5800 * Project: GEnesis, PCI Gigabit Ethernet Adapter
5801- * Version: $Revision$
5802- * Date: $Date$
5803+ * Version: $Revision$
5804+ * Date: $Date$
5805 * Purpose: Defines for Private Network Management Interface
5806 *
5807 ****************************************************************************/
5808
5809 /******************************************************************************
5810 *
5811+ * LICENSE:
5812 * (C)Copyright 1998-2002 SysKonnect GmbH.
5813 * (C)Copyright 2002-2003 Marvell.
5814 *
5815@@ -19,6 +20,7 @@
5816 * (at your option) any later version.
5817 *
5818 * The information in this file is provided "AS IS" without warranty.
5819+ * /LICENSE
5820 *
5821 ******************************************************************************/
5822
5823@@ -28,8 +30,13 @@
5824 /*
5825 * General definitions
5826 */
5827-#define SK_PNMI_CHIPSET_XMAC 1 /* XMAC11800FP */
5828-#define SK_PNMI_CHIPSET_YUKON 2 /* YUKON */
5829+#define SK_PNMI_CHIPSET_XMAC 1 /* XMAC11800FP */
5830+#define SK_PNMI_CHIPSET_YUKON 2 /* YUKON */
5831+#define SK_PNMI_CHIPSET_YUKON_LITE 3 /* YUKON-Lite (Rev. A1-A3) */
5832+#define SK_PNMI_CHIPSET_YUKON_LP 4 /* YUKON-LP */
5833+#define SK_PNMI_CHIPSET_YUKON_XL 5 /* YUKON-2 XL */
5834+#define SK_PNMI_CHIPSET_YUKON_EC 6 /* YUKON-2 EC */
5835+#define SK_PNMI_CHIPSET_YUKON_FE 7 /* YUKON-2 FE */
5836
5837 #define SK_PNMI_BUS_PCI 1 /* PCI bus*/
5838
5839@@ -70,9 +77,9 @@
5840 /*
5841 * VCT internal status values
5842 */
5843-#define SK_PNMI_VCT_PENDING 32
5844-#define SK_PNMI_VCT_TEST_DONE 64
5845-#define SK_PNMI_VCT_LINK 128
5846+#define SK_PNMI_VCT_PENDING 0x20
5847+#define SK_PNMI_VCT_TEST_DONE 0x40
5848+#define SK_PNMI_VCT_LINK 0x80
5849
5850 /*
5851 * Internal table definitions
5852@@ -323,7 +330,7 @@
5853 vSt, \
5854 pAC->Pnmi.MacUpdatedFlag, \
5855 pAC->Pnmi.RlmtUpdatedFlag, \
5856- pAC->Pnmi.SirqUpdatedFlag))}}
5857+ pAC->Pnmi.SirqUpdatedFlag));}}
5858
5859 #else /* !DEBUG */
5860
5861diff -urN linux-2.6.17.orig/drivers/net/sk98lin/h/skgepnmi.h linux-2.6.17/drivers/net/sk98lin/h/skgepnmi.h
5862--- linux-2.6.17.orig/drivers/net/sk98lin/h/skgepnmi.h 2006-06-22 13:17:16.000000000 +0200
5863+++ linux-2.6.17/drivers/net/sk98lin/h/skgepnmi.h 2006-04-27 11:43:44.000000000 +0200
5864@@ -1,15 +1,16 @@
5865 /*****************************************************************************
5866 *
5867 * Name: skgepnmi.h
5868- * Project: GEnesis, PCI Gigabit Ethernet Adapter
5869- * Version: $Revision$
5870- * Date: $Date$
5871+ * Project: Gigabit Ethernet Adapters, PNMI-Module
5872+ * Version: $Revision$
5873+ * Date: $Date$
5874 * Purpose: Defines for Private Network Management Interface
5875 *
5876 ****************************************************************************/
5877
5878 /******************************************************************************
5879 *
5880+ * LICENSE:
5881 * (C)Copyright 1998-2002 SysKonnect GmbH.
5882 * (C)Copyright 2002-2003 Marvell.
5883 *
5884@@ -19,6 +20,7 @@
5885 * (at your option) any later version.
5886 *
5887 * The information in this file is provided "AS IS" without warranty.
5888+ * /LICENSE
5889 *
5890 ******************************************************************************/
5891
5892@@ -31,7 +33,7 @@
5893 #include "h/sktypes.h"
5894 #include "h/skerror.h"
5895 #include "h/sktimer.h"
5896-#include "h/ski2c.h"
5897+#include "h/sktwsi.h"
5898 #include "h/skaddr.h"
5899 #include "h/skrlmt.h"
5900 #include "h/skvpd.h"
5901@@ -41,7 +43,6 @@
5902 */
5903 #define SK_PNMI_MDB_VERSION 0x00030001 /* 3.1 */
5904
5905-
5906 /*
5907 * Event definitions
5908 */
5909@@ -54,16 +55,13 @@
5910 #define SK_PNMI_EVT_UTILIZATION_TIMER 7 /* Timer event for Utiliza. */
5911 #define SK_PNMI_EVT_CLEAR_COUNTER 8 /* Clear statistic counters */
5912 #define SK_PNMI_EVT_XMAC_RESET 9 /* XMAC will be reset */
5913-
5914 #define SK_PNMI_EVT_RLMT_PORT_UP 10 /* Port came logically up */
5915 #define SK_PNMI_EVT_RLMT_PORT_DOWN 11 /* Port went logically down */
5916 #define SK_PNMI_EVT_RLMT_SEGMENTATION 13 /* Two SP root bridges found */
5917 #define SK_PNMI_EVT_RLMT_ACTIVE_DOWN 14 /* Port went logically down */
5918 #define SK_PNMI_EVT_RLMT_ACTIVE_UP 15 /* Port came logically up */
5919-#define SK_PNMI_EVT_RLMT_SET_NETS 16 /* 1. Parameter is number of nets
5920- 1 = single net; 2 = dual net */
5921-#define SK_PNMI_EVT_VCT_RESET 17 /* VCT port reset timer event started with SET. */
5922-
5923+#define SK_PNMI_EVT_RLMT_SET_NETS 16 /* Number of nets (1 or 2). */
5924+#define SK_PNMI_EVT_VCT_RESET 17 /* VCT port reset timer event started with SET. */
5925
5926 /*
5927 * Return values
5928@@ -78,7 +76,6 @@
5929 #define SK_PNMI_ERR_UNKNOWN_NET 7
5930 #define SK_PNMI_ERR_NOT_SUPPORTED 10
5931
5932-
5933 /*
5934 * Return values of driver reset function SK_DRIVER_RESET() and
5935 * driver event function SK_DRIVER_EVENT()
5936@@ -86,19 +83,17 @@
5937 #define SK_PNMI_ERR_OK 0
5938 #define SK_PNMI_ERR_FAIL 1
5939
5940-
5941 /*
5942 * Return values of driver test function SK_DRIVER_SELFTEST()
5943 */
5944 #define SK_PNMI_TST_UNKNOWN (1 << 0)
5945-#define SK_PNMI_TST_TRANCEIVER (1 << 1)
5946+#define SK_PNMI_TST_TRANCEIVER (1 << 1)
5947 #define SK_PNMI_TST_ASIC (1 << 2)
5948 #define SK_PNMI_TST_SENSOR (1 << 3)
5949-#define SK_PNMI_TST_POWERMGMT (1 << 4)
5950+#define SK_PNMI_TST_POWERMGMT (1 << 4)
5951 #define SK_PNMI_TST_PCI (1 << 5)
5952 #define SK_PNMI_TST_MAC (1 << 6)
5953
5954-
5955 /*
5956 * RLMT specific definitions
5957 */
5958@@ -223,7 +218,17 @@
5959 #define OID_SKGE_RLMT_PORT_NUMBER 0xFF010141
5960 #define OID_SKGE_RLMT_PORT_ACTIVE 0xFF010142
5961 #define OID_SKGE_RLMT_PORT_PREFERRED 0xFF010143
5962-#define OID_SKGE_INTERMEDIATE_SUPPORT 0xFF010160
5963+
5964+#define OID_SKGE_RLMT_MONITOR_NUMBER 0xFF010150
5965+#define OID_SKGE_RLMT_MONITOR_INDEX 0xFF010151
5966+#define OID_SKGE_RLMT_MONITOR_ADDR 0xFF010152
5967+#define OID_SKGE_RLMT_MONITOR_ERRS 0xFF010153
5968+#define OID_SKGE_RLMT_MONITOR_TIMESTAMP 0xFF010154
5969+#define OID_SKGE_RLMT_MONITOR_ADMIN 0xFF010155
5970+
5971+#define OID_SKGE_INTERMEDIATE_SUPPORT 0xFF010160
5972+#define OID_SKGE_SET_TEAM_MAC_ADDRESS 0xFF010161
5973+#define OID_SKGE_DEVICE_INFORMATION 0xFF010162
5974
5975 #define OID_SKGE_SPEED_CAP 0xFF010170
5976 #define OID_SKGE_SPEED_MODE 0xFF010171
5977@@ -322,13 +327,6 @@
5978 #define OID_SKGE_RLMT_TX_SP_REQ_CTS 0xFF020168
5979 #define OID_SKGE_RLMT_RX_SP_CTS 0xFF020169
5980
5981-#define OID_SKGE_RLMT_MONITOR_NUMBER 0xFF010150
5982-#define OID_SKGE_RLMT_MONITOR_INDEX 0xFF010151
5983-#define OID_SKGE_RLMT_MONITOR_ADDR 0xFF010152
5984-#define OID_SKGE_RLMT_MONITOR_ERRS 0xFF010153
5985-#define OID_SKGE_RLMT_MONITOR_TIMESTAMP 0xFF010154
5986-#define OID_SKGE_RLMT_MONITOR_ADMIN 0xFF010155
5987-
5988 #define OID_SKGE_TX_SW_QUEUE_LEN 0xFF020170
5989 #define OID_SKGE_TX_SW_QUEUE_MAX 0xFF020171
5990 #define OID_SKGE_TX_RETRY 0xFF020172
5991@@ -352,6 +350,7 @@
5992 #define OID_SKGE_VCT_GET 0xFF020200
5993 #define OID_SKGE_VCT_SET 0xFF020201
5994 #define OID_SKGE_VCT_STATUS 0xFF020202
5995+#define OID_SKGE_VCT_CAPABILITIES 0xFF020203
5996
5997 #ifdef SK_DIAG_SUPPORT
5998 /* Defines for driver DIAG mode. */
5999@@ -367,22 +366,79 @@
6000 #define OID_SKGE_PHY_TYPE 0xFF020215
6001 #define OID_SKGE_PHY_LP_MODE 0xFF020216
6002
6003+/*
6004+ * Added for new DualNet IM driver V2
6005+ * these OIDs should later be in pnmi.h
6006+ */
6007+#define OID_SKGE_MAC_COUNT 0xFF020217
6008+#define OID_SKGE_DUALNET_MODE 0xFF020218
6009+#define OID_SKGE_SET_TAGHEADER 0xFF020219
6010+
6011+#ifdef SK_ASF
6012+/* Defines for ASF */
6013+#define OID_SKGE_ASF 0xFF02021a
6014+#define OID_SKGE_ASF_STORE_CONFIG 0xFF02021b
6015+#define OID_SKGE_ASF_ENA 0xFF02021c
6016+#define OID_SKGE_ASF_RETRANS 0xFF02021d
6017+#define OID_SKGE_ASF_RETRANS_INT 0xFF02021e
6018+#define OID_SKGE_ASF_HB_ENA 0xFF02021f
6019+#define OID_SKGE_ASF_HB_INT 0xFF020220
6020+#define OID_SKGE_ASF_WD_ENA 0xFF020221
6021+#define OID_SKGE_ASF_WD_TIME 0xFF020222
6022+#define OID_SKGE_ASF_IP_SOURCE 0xFF020223
6023+#define OID_SKGE_ASF_MAC_SOURCE 0xFF020224
6024+#define OID_SKGE_ASF_IP_DEST 0xFF020225
6025+#define OID_SKGE_ASF_MAC_DEST 0xFF020226
6026+#define OID_SKGE_ASF_COMMUNITY_NAME 0xFF020227
6027+#define OID_SKGE_ASF_RSP_ENA 0xFF020228
6028+#define OID_SKGE_ASF_RETRANS_COUNT_MIN 0xFF020229
6029+#define OID_SKGE_ASF_RETRANS_COUNT_MAX 0xFF02022a
6030+#define OID_SKGE_ASF_RETRANS_INT_MIN 0xFF02022b
6031+#define OID_SKGE_ASF_RETRANS_INT_MAX 0xFF02022c
6032+#define OID_SKGE_ASF_HB_INT_MIN 0xFF02022d
6033+#define OID_SKGE_ASF_HB_INT_MAX 0xFF02022e
6034+#define OID_SKGE_ASF_WD_TIME_MIN 0xFF02022f
6035+#define OID_SKGE_ASF_WD_TIME_MAX 0xFF020230
6036+#define OID_SKGE_ASF_HB_CAP 0xFF020231
6037+#define OID_SKGE_ASF_WD_TIMER_RES 0xFF020232
6038+#define OID_SKGE_ASF_GUID 0xFF020233
6039+#define OID_SKGE_ASF_KEY_OP 0xFF020234
6040+#define OID_SKGE_ASF_KEY_ADM 0xFF020235
6041+#define OID_SKGE_ASF_KEY_GEN 0xFF020236
6042+#define OID_SKGE_ASF_CAP 0xFF020237
6043+#define OID_SKGE_ASF_PAR_1 0xFF020238
6044+#define OID_SKGE_ASF_OVERALL_OID 0xFF020239
6045+#endif /* SK_ASF */
6046+
6047+
6048+// Defined for yukon2 path only
6049+#define OID_SKGE_UPPER_MINIPORT 0xFF02023D
6050+
6051+
6052+#ifdef SK_ASF
6053+/* Defines for ASF */
6054+#define OID_SKGE_ASF_FWVER_OID 0xFF020240
6055+#define OID_SKGE_ASF_ACPI_OID 0xFF020241
6056+#define OID_SKGE_ASF_SMBUS_OID 0xFF020242
6057+#endif /* SK_ASF */
6058+
6059+
6060 /* VCT struct to store a backup copy of VCT data after a port reset. */
6061 typedef struct s_PnmiVct {
6062 SK_U8 VctStatus;
6063- SK_U8 PCableLen;
6064- SK_U32 PMdiPairLen[4];
6065- SK_U8 PMdiPairSts[4];
6066+ SK_U8 CableLen;
6067+ SK_U32 MdiPairLen[4];
6068+ SK_U8 MdiPairSts[4];
6069 } SK_PNMI_VCT;
6070
6071
6072 /* VCT status values (to be given to CPA via OID_SKGE_VCT_STATUS). */
6073-#define SK_PNMI_VCT_NONE 0
6074-#define SK_PNMI_VCT_OLD_VCT_DATA 1
6075-#define SK_PNMI_VCT_NEW_VCT_DATA 2
6076-#define SK_PNMI_VCT_OLD_DSP_DATA 4
6077-#define SK_PNMI_VCT_NEW_DSP_DATA 8
6078-#define SK_PNMI_VCT_RUNNING 16
6079+#define SK_PNMI_VCT_NONE 0x00
6080+#define SK_PNMI_VCT_OLD_VCT_DATA 0x01
6081+#define SK_PNMI_VCT_NEW_VCT_DATA 0x02
6082+#define SK_PNMI_VCT_OLD_DSP_DATA 0x04
6083+#define SK_PNMI_VCT_NEW_DSP_DATA 0x08
6084+#define SK_PNMI_VCT_RUNNING 0x10
6085
6086
6087 /* VCT cable test status. */
6088@@ -390,7 +446,12 @@
6089 #define SK_PNMI_VCT_SHORT_CABLE 1
6090 #define SK_PNMI_VCT_OPEN_CABLE 2
6091 #define SK_PNMI_VCT_TEST_FAIL 3
6092-#define SK_PNMI_VCT_IMPEDANCE_MISMATCH 4
6093+#define SK_PNMI_VCT_IMPEDANCE_MISMATCH 4
6094+#define SK_PNMI_VCT_NOT_PRESENT 5
6095+
6096+/* VCT capabilities (needed for OID_SKGE_VCT_CAPABILITIES. */
6097+#define SK_PNMI_VCT_SUPPORTED 1
6098+#define SK_PNMI_VCT_NOT_SUPPORTED 0
6099
6100 #define OID_SKGE_TRAP_SEN_WAR_LOW 500
6101 #define OID_SKGE_TRAP_SEN_WAR_UPP 501
6102@@ -419,7 +480,6 @@
6103 #define SK_SET_FULL_MIB 5
6104 #define SK_PRESET_FULL_MIB 6
6105
6106-
6107 /*
6108 * Define error numbers and messages for syslog
6109 */
6110@@ -452,7 +512,7 @@
6111 #define SK_PNMI_ERR014 (SK_ERRBASE_PNMI + 14)
6112 #define SK_PNMI_ERR014MSG "Vpd: Cannot read VPD keys"
6113 #define SK_PNMI_ERR015 (SK_ERRBASE_PNMI + 15)
6114-#define SK_PNMI_ERR015MSG "Vpd: Internal array for VPD keys to small"
6115+#define SK_PNMI_ERR015MSG "Vpd: Internal array for VPD keys too small"
6116 #define SK_PNMI_ERR016 (SK_ERRBASE_PNMI + 16)
6117 #define SK_PNMI_ERR016MSG "Vpd: Key string too long"
6118 #define SK_PNMI_ERR017 (SK_ERRBASE_PNMI + 17)
6119@@ -494,9 +554,9 @@
6120 #define SK_PNMI_ERR036 (SK_ERRBASE_PNMI + 36)
6121 #define SK_PNMI_ERR036MSG ""
6122 #define SK_PNMI_ERR037 (SK_ERRBASE_PNMI + 37)
6123-#define SK_PNMI_ERR037MSG "Rlmt: SK_RLMT_MODE_CHANGE event return not 0"
6124+#define SK_PNMI_ERR037MSG "Rlmt: SK_RLMT_MODE_CHANGE event returned not 0"
6125 #define SK_PNMI_ERR038 (SK_ERRBASE_PNMI + 38)
6126-#define SK_PNMI_ERR038MSG "Rlmt: SK_RLMT_PREFPORT_CHANGE event return not 0"
6127+#define SK_PNMI_ERR038MSG "Rlmt: SK_RLMT_PREFPORT_CHANGE event returned not 0"
6128 #define SK_PNMI_ERR039 (SK_ERRBASE_PNMI + 39)
6129 #define SK_PNMI_ERR039MSG "RlmtStat: Unknown OID"
6130 #define SK_PNMI_ERR040 (SK_ERRBASE_PNMI + 40)
6131@@ -514,9 +574,9 @@
6132 #define SK_PNMI_ERR046 (SK_ERRBASE_PNMI + 46)
6133 #define SK_PNMI_ERR046MSG "Monitor: Unknown OID"
6134 #define SK_PNMI_ERR047 (SK_ERRBASE_PNMI + 47)
6135-#define SK_PNMI_ERR047MSG "SirqUpdate: Event function returns not 0"
6136+#define SK_PNMI_ERR047MSG "SirqUpdate: Event function returned not 0"
6137 #define SK_PNMI_ERR048 (SK_ERRBASE_PNMI + 48)
6138-#define SK_PNMI_ERR048MSG "RlmtUpdate: Event function returns not 0"
6139+#define SK_PNMI_ERR048MSG "RlmtUpdate: Event function returned not 0"
6140 #define SK_PNMI_ERR049 (SK_ERRBASE_PNMI + 49)
6141 #define SK_PNMI_ERR049MSG "SkPnmiInit: Invalid size of 'CounterOffset' struct!!"
6142 #define SK_PNMI_ERR050 (SK_ERRBASE_PNMI + 50)
6143@@ -826,23 +886,25 @@
6144 } SK_PNMI_STRUCT_DATA;
6145
6146 #define SK_PNMI_STRUCT_SIZE (sizeof(SK_PNMI_STRUCT_DATA))
6147+
6148+/* The ReturnStatus field must be located before VpdFreeBytes! */
6149 #define SK_PNMI_MIN_STRUCT_SIZE ((unsigned int)(SK_UPTR)\
6150 &(((SK_PNMI_STRUCT_DATA *)0)->VpdFreeBytes))
6151- /*
6152- * ReturnStatus field
6153- * must be located
6154- * before VpdFreeBytes
6155- */
6156
6157 /*
6158 * Various definitions
6159 */
6160+#define SK_PNMI_EVT_TIMER_CHECK 28125000L /* 28125 ms */
6161+
6162+#define SK_PNMI_VCT_TIMER_CHECK 4000000L /* 4 sec. */
6163+
6164 #define SK_PNMI_MAX_PROTOS 3
6165
6166-#define SK_PNMI_CNT_NO 66 /* Must have the value of the enum
6167- * SK_PNMI_MAX_IDX. Define SK_PNMI_CHECK
6168- * for check while init phase 1
6169- */
6170+/*
6171+ * SK_PNMI_CNT_NO must have the value of the enum SK_PNMI_MAX_IDX.
6172+ * Define SK_PNMI_CHECK to check this during init level SK_INIT_IO.
6173+ */
6174+#define SK_PNMI_CNT_NO 66
6175
6176 /*
6177 * Estimate data structure
6178@@ -856,14 +918,6 @@
6179
6180
6181 /*
6182- * VCT timer data structure
6183- */
6184-typedef struct s_VctTimer {
6185- SK_TIMER VctTimer;
6186-} SK_PNMI_VCT_TIMER;
6187-
6188-
6189-/*
6190 * PNMI specific adapter context structure
6191 */
6192 typedef struct s_PnmiPort {
6193@@ -933,12 +987,13 @@
6194 unsigned int TrapQueueEnd;
6195 unsigned int TrapBufPad;
6196 unsigned int TrapUnique;
6197- SK_U8 VctStatus[SK_MAX_MACS];
6198- SK_PNMI_VCT VctBackup[SK_MAX_MACS];
6199- SK_PNMI_VCT_TIMER VctTimeout[SK_MAX_MACS];
6200+ SK_U8 VctStatus[SK_MAX_MACS];
6201+ SK_PNMI_VCT VctBackup[SK_MAX_MACS];
6202+ SK_TIMER VctTimeout[SK_MAX_MACS];
6203 #ifdef SK_DIAG_SUPPORT
6204 SK_U32 DiagAttached;
6205 #endif /* SK_DIAG_SUPPORT */
6206+ SK_BOOL VpdKeyReadError;
6207 } SK_PNMI;
6208
6209
6210@@ -946,6 +1001,10 @@
6211 * Function prototypes
6212 */
6213 extern int SkPnmiInit(SK_AC *pAC, SK_IOC IoC, int Level);
6214+extern int SkPnmiGetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void* pBuf,
6215+ unsigned int* pLen, SK_U32 Instance, SK_U32 NetIndex);
6216+extern int SkPnmiPreSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id,
6217+ void* pBuf, unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex);
6218 extern int SkPnmiSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void* pBuf,
6219 unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex);
6220 extern int SkPnmiGetStruct(SK_AC *pAC, SK_IOC IoC, void* pBuf,
6221diff -urN linux-2.6.17.orig/drivers/net/sk98lin/h/skgesirq.h linux-2.6.17/drivers/net/sk98lin/h/skgesirq.h
6222--- linux-2.6.17.orig/drivers/net/sk98lin/h/skgesirq.h 2006-06-22 13:17:16.000000000 +0200
6223+++ linux-2.6.17/drivers/net/sk98lin/h/skgesirq.h 2006-04-27 11:43:44.000000000 +0200
6224@@ -2,23 +2,24 @@
6225 *
6226 * Name: skgesirq.h
6227 * Project: Gigabit Ethernet Adapters, Common Modules
6228- * Version: $Revision$
6229- * Date: $Date$
6230- * Purpose: SK specific Gigabit Ethernet special IRQ functions
6231+ * Version: $Revision$
6232+ * Date: $Date$
6233+ * Purpose: Gigabit Ethernet special IRQ functions
6234 *
6235 ******************************************************************************/
6236
6237 /******************************************************************************
6238 *
6239+ * LICENSE:
6240 * (C)Copyright 1998-2002 SysKonnect.
6241- * (C)Copyright 2002-2003 Marvell.
6242+ * (C)Copyright 2002-2005 Marvell.
6243 *
6244 * This program is free software; you can redistribute it and/or modify
6245 * it under the terms of the GNU General Public License as published by
6246 * the Free Software Foundation; either version 2 of the License, or
6247 * (at your option) any later version.
6248- *
6249 * The information in this file is provided "AS IS" without warranty.
6250+ * /LICENSE
6251 *
6252 ******************************************************************************/
6253
6254@@ -26,9 +27,9 @@
6255 #define _INC_SKGESIRQ_H_
6256
6257 /* Define return codes of SkGePortCheckUp and CheckShort */
6258-#define SK_HW_PS_NONE 0 /* No action needed */
6259-#define SK_HW_PS_RESTART 1 /* Restart needed */
6260-#define SK_HW_PS_LINK 2 /* Link Up actions needed */
6261+#define SK_HW_PS_NONE 0 /* No action needed */
6262+#define SK_HW_PS_RESTART 1 /* Restart needed */
6263+#define SK_HW_PS_LINK 2 /* Link Up actions needed */
6264
6265 /*
6266 * Define the Event the special IRQ/INI module can handle
6267@@ -44,10 +45,10 @@
6268 #define SK_HWEV_SET_SPEED 9 /* Set Link Speed by PNMI */
6269 #define SK_HWEV_HALFDUP_CHK 10 /* Half Duplex Hangup Workaround */
6270
6271-#define SK_WA_ACT_TIME (5000000UL) /* 5 sec */
6272-#define SK_WA_INA_TIME (100000UL) /* 100 msec */
6273+#define SK_WA_ACT_TIME 1000000UL /* 1000 msec (1 sec) */
6274+#define SK_WA_INA_TIME 100000UL /* 100 msec */
6275
6276-#define SK_HALFDUP_CHK_TIME (10000UL) /* 10 msec */
6277+#define SK_HALFDUP_CHK_TIME 10000UL /* 10 msec */
6278
6279 /*
6280 * Define the error numbers and messages
6281@@ -75,9 +76,9 @@
6282 #define SKERR_SIRQ_E011 (SKERR_SIRQ_E010+1)
6283 #define SKERR_SIRQ_E011MSG "CHECK failure XA2"
6284 #define SKERR_SIRQ_E012 (SKERR_SIRQ_E011+1)
6285-#define SKERR_SIRQ_E012MSG "unexpected IRQ Master error"
6286+#define SKERR_SIRQ_E012MSG "Unexpected IRQ Master error"
6287 #define SKERR_SIRQ_E013 (SKERR_SIRQ_E012+1)
6288-#define SKERR_SIRQ_E013MSG "unexpected IRQ Status error"
6289+#define SKERR_SIRQ_E013MSG "Unexpected IRQ Status error"
6290 #define SKERR_SIRQ_E014 (SKERR_SIRQ_E013+1)
6291 #define SKERR_SIRQ_E014MSG "Parity error on RAM (read)"
6292 #define SKERR_SIRQ_E015 (SKERR_SIRQ_E014+1)
6293@@ -102,9 +103,35 @@
6294 #define SKERR_SIRQ_E024MSG "FIFO overflow error"
6295 #define SKERR_SIRQ_E025 (SKERR_SIRQ_E024+1)
6296 #define SKERR_SIRQ_E025MSG "2 Pair Downshift detected"
6297+#define SKERR_SIRQ_E026 (SKERR_SIRQ_E025+1)
6298+#define SKERR_SIRQ_E026MSG "Uncorrectable PCI Express error"
6299+#define SKERR_SIRQ_E027 (SKERR_SIRQ_E026+1)
6300+#define SKERR_SIRQ_E027MSG "PCI Bus Abort detected"
6301+#define SKERR_SIRQ_E028 (SKERR_SIRQ_E027+1)
6302+#define SKERR_SIRQ_E028MSG "Parity error on RAM 1 (read)"
6303+#define SKERR_SIRQ_E029 (SKERR_SIRQ_E028+1)
6304+#define SKERR_SIRQ_E029MSG "Parity error on RAM 1 (write)"
6305+#define SKERR_SIRQ_E030 (SKERR_SIRQ_E029+1)
6306+#define SKERR_SIRQ_E030MSG "Parity error on RAM 2 (read)"
6307+#define SKERR_SIRQ_E031 (SKERR_SIRQ_E030+1)
6308+#define SKERR_SIRQ_E031MSG "Parity error on RAM 2 (write)"
6309+#define SKERR_SIRQ_E032 (SKERR_SIRQ_E031+1)
6310+#define SKERR_SIRQ_E032MSG "TCP segmentation error async. queue 1"
6311+#define SKERR_SIRQ_E033 (SKERR_SIRQ_E032+1)
6312+#define SKERR_SIRQ_E033MSG "TCP segmentation error sync. queue 1"
6313+#define SKERR_SIRQ_E034 (SKERR_SIRQ_E033+1)
6314+#define SKERR_SIRQ_E034MSG "TCP segmentation error async. queue 2"
6315+#define SKERR_SIRQ_E035 (SKERR_SIRQ_E034+1)
6316+#define SKERR_SIRQ_E035MSG "TCP segmentation error sync. queue 2"
6317+#define SKERR_SIRQ_E036 (SKERR_SIRQ_E035+1)
6318+#define SKERR_SIRQ_E036MSG "CHECK failure polling unit"
6319
6320 extern void SkGeSirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus);
6321 extern int SkGeSirqEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Para);
6322+extern void SkHWLinkUp(SK_AC *pAC, SK_IOC IoC, int Port);
6323 extern void SkHWLinkDown(SK_AC *pAC, SK_IOC IoC, int Port);
6324+extern void SkGeYuSirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus);
6325+extern void SkYuk2SirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus);
6326
6327 #endif /* _INC_SKGESIRQ_H_ */
6328+
6329diff -urN linux-2.6.17.orig/drivers/net/sk98lin/h/skgetwsi.h linux-2.6.17/drivers/net/sk98lin/h/skgetwsi.h
6330--- linux-2.6.17.orig/drivers/net/sk98lin/h/skgetwsi.h 1970-01-01 01:00:00.000000000 +0100
6331+++ linux-2.6.17/drivers/net/sk98lin/h/skgetwsi.h 2006-04-27 11:43:44.000000000 +0200
6332@@ -0,0 +1,243 @@
6333+/******************************************************************************
6334+ *
6335+ * Name: skgetwsi.h
6336+ * Project: Gigabit Ethernet Adapters, TWSI-Module
6337+ * Version: $Revision$
6338+ * Date: $Date$
6339+ * Purpose: Special defines for TWSI
6340+ *
6341+ ******************************************************************************/
6342+
6343+/******************************************************************************
6344+ *
6345+ * LICENSE:
6346+ * (C)Copyright 1998-2002 SysKonnect.
6347+ * (C)Copyright 2002-2004 Marvell.
6348+ *
6349+ * This program is free software; you can redistribute it and/or modify
6350+ * it under the terms of the GNU General Public License as published by
6351+ * the Free Software Foundation; either version 2 of the License, or
6352+ * (at your option) any later version.
6353+ * The information in this file is provided "AS IS" without warranty.
6354+ * /LICENSE
6355+ *
6356+ ******************************************************************************/
6357+
6358+/*
6359+ * SKGETWSI.H contains all SK-98xx specific defines for the TWSI handling
6360+ */
6361+
6362+#ifndef _INC_SKGETWSI_H_
6363+#define _INC_SKGETWSI_H_
6364+
6365+/*
6366+ * Macros to access the B2_I2C_CTRL
6367+ */
6368+#define SK_I2C_CTL(IoC, flag, dev, dev_size, reg, burst) \
6369+ SK_OUT32(IoC, B2_I2C_CTRL,\
6370+ (flag ? 0x80000000UL : 0x0L) | \
6371+ (((SK_U32)reg << 16) & I2C_ADDR) | \
6372+ (((SK_U32)dev << 9) & I2C_DEV_SEL) | \
6373+ (dev_size & I2C_DEV_SIZE) | \
6374+ ((burst << 4) & I2C_BURST_LEN))
6375+
6376+#define SK_I2C_STOP(IoC) { \
6377+ SK_U32 I2cCtrl; \
6378+ SK_IN32(IoC, B2_I2C_CTRL, &I2cCtrl); \
6379+ SK_OUT32(IoC, B2_I2C_CTRL, I2cCtrl | I2C_STOP); \
6380+}
6381+
6382+#define SK_I2C_GET_CTL(IoC, pI2cCtrl) SK_IN32(IoC, B2_I2C_CTRL, pI2cCtrl)
6383+
6384+/*
6385+ * Macros to access the TWSI SW Registers
6386+ */
6387+#define SK_I2C_SET_BIT(IoC, SetBits) { \
6388+ SK_U8 OrgBits; \
6389+ SK_IN8(IoC, B2_I2C_SW, &OrgBits); \
6390+ SK_OUT8(IoC, B2_I2C_SW, OrgBits | (SK_U8)(SetBits)); \
6391+}
6392+
6393+#define SK_I2C_CLR_BIT(IoC, ClrBits) { \
6394+ SK_U8 OrgBits; \
6395+ SK_IN8(IoC, B2_I2C_SW, &OrgBits); \
6396+ SK_OUT8(IoC, B2_I2C_SW, OrgBits & ~((SK_U8)(ClrBits))); \
6397+}
6398+
6399+#define SK_I2C_GET_SW(IoC, pI2cSw) SK_IN8(IoC, B2_I2C_SW, pI2cSw)
6400+
6401+/*
6402+ * define the possible sensor states
6403+ */
6404+#define SK_SEN_IDLE 0 /* Idle: sensor not read */
6405+#define SK_SEN_VALUE 1 /* Value Read cycle */
6406+#define SK_SEN_VALEXT 2 /* Extended Value Read cycle */
6407+
6408+/*
6409+ * Conversion factor to convert read Voltage sensor to milli Volt
6410+ * Conversion factor to convert read Temperature sensor to 10th degree Celsius
6411+ */
6412+#define SK_LM80_VT_LSB 22 /* 22mV LSB resolution */
6413+#define SK_LM80_TEMP_LSB 10 /* 1 degree LSB resolution */
6414+#define SK_LM80_TEMPEXT_LSB 5 /* 0.5 degree LSB resolution for ext. val. */
6415+
6416+/*
6417+ * formula: counter = (22500*60)/(rpm * divisor * pulses/2)
6418+ * assuming: 6500rpm, 4 pulses, divisor 1
6419+ */
6420+#define SK_LM80_FAN_FAKTOR ((22500L*60)/(1*2))
6421+
6422+/*
6423+ * Define sensor management data
6424+ * Maximum is reached on Genesis copper dual port and Yukon-64
6425+ * Board specific maximum is in pAC->I2c.MaxSens
6426+ */
6427+#define SK_MAX_SENSORS 8 /* maximal no. of installed sensors */
6428+#define SK_MIN_SENSORS 5 /* minimal no. of installed sensors */
6429+
6430+/*
6431+ * To watch the state machine (SM) use the timer in two ways
6432+ * instead of one as hitherto
6433+ */
6434+#define SK_TIMER_WATCH_SM 0 /* Watch the SM to finish in a spec. time */
6435+#define SK_TIMER_NEW_GAUGING 1 /* Start a new gauging when timer expires */
6436+
6437+/*
6438+ * Defines for the individual thresholds
6439+ */
6440+
6441+#define C_PLUS_20 120 / 100
6442+#define C_PLUS_15 115 / 100
6443+#define C_PLUS_10 110 / 100
6444+#define C_PLUS_5 105 / 100
6445+#define C_MINUS_5 95 / 100
6446+#define C_MINUS_10 90 / 100
6447+#define C_MINUS_15 85 / 100
6448+
6449+/* Temperature sensor */
6450+#define SK_SEN_TEMP_HIGH_ERR 800 /* Temperature High Err Threshold */
6451+#define SK_SEN_TEMP_HIGH_WARN 700 /* Temperature High Warn Threshold */
6452+#define SK_SEN_TEMP_LOW_WARN 100 /* Temperature Low Warn Threshold */
6453+#define SK_SEN_TEMP_LOW_ERR 0 /* Temperature Low Err Threshold */
6454+
6455+/* VCC which should be 5 V */
6456+#define SK_SEN_PCI_5V_HIGH_ERR 5588 /* Voltage PCI High Err Threshold */
6457+#define SK_SEN_PCI_5V_HIGH_WARN 5346 /* Voltage PCI High Warn Threshold */
6458+#define SK_SEN_PCI_5V_LOW_WARN 4664 /* Voltage PCI Low Warn Threshold */
6459+#define SK_SEN_PCI_5V_LOW_ERR 4422 /* Voltage PCI Low Err Threshold */
6460+
6461+/*
6462+ * VIO may be 5 V or 3.3 V. Initialization takes two parts:
6463+ * 1. Initialize lowest lower limit and highest higher limit.
6464+ * 2. After the first value is read correct the upper or the lower limit to
6465+ * the appropriate C constant.
6466+ *
6467+ * Warning limits are +-5% of the exepected voltage.
6468+ * Error limits are +-10% of the expected voltage.
6469+ */
6470+
6471+/* Bug fix AF: 16.Aug.2001: Correct the init base of LM80 sensor */
6472+
6473+#define SK_SEN_PCI_IO_5V_HIGH_ERR 5566 /* + 10% V PCI-IO High Err Threshold */
6474+#define SK_SEN_PCI_IO_5V_HIGH_WARN 5324 /* + 5% V PCI-IO High Warn Threshold */
6475+ /* 5000 mVolt */
6476+#define SK_SEN_PCI_IO_5V_LOW_WARN 4686 /* - 5% V PCI-IO Low Warn Threshold */
6477+#define SK_SEN_PCI_IO_5V_LOW_ERR 4444 /* - 10% V PCI-IO Low Err Threshold */
6478+
6479+#define SK_SEN_PCI_IO_RANGE_LIMITER 4000 /* 4000 mV range delimiter */
6480+
6481+/* correction values for the second pass */
6482+#define SK_SEN_PCI_IO_3V3_HIGH_ERR 3850 /* + 15% V PCI-IO High Err Threshold */
6483+#define SK_SEN_PCI_IO_3V3_HIGH_WARN 3674 /* + 10% V PCI-IO High Warn Threshold */
6484+ /* 3300 mVolt */
6485+#define SK_SEN_PCI_IO_3V3_LOW_WARN 2926 /* - 10% V PCI-IO Low Warn Threshold */
6486+#define SK_SEN_PCI_IO_3V3_LOW_ERR 2772 /* - 15% V PCI-IO Low Err Threshold */
6487+
6488+/*
6489+ * VDD voltage
6490+ */
6491+#define SK_SEN_VDD_HIGH_ERR 3630 /* Voltage ASIC High Err Threshold */
6492+#define SK_SEN_VDD_HIGH_WARN 3476 /* Voltage ASIC High Warn Threshold */
6493+#define SK_SEN_VDD_LOW_WARN 3146 /* Voltage ASIC Low Warn Threshold */
6494+#define SK_SEN_VDD_LOW_ERR 2970 /* Voltage ASIC Low Err Threshold */
6495+
6496+/*
6497+ * PHY PLL 3V3 voltage
6498+ */
6499+#define SK_SEN_PLL_3V3_HIGH_ERR 3630 /* Voltage PMA High Err Threshold */
6500+#define SK_SEN_PLL_3V3_HIGH_WARN 3476 /* Voltage PMA High Warn Threshold */
6501+#define SK_SEN_PLL_3V3_LOW_WARN 3146 /* Voltage PMA Low Warn Threshold */
6502+#define SK_SEN_PLL_3V3_LOW_ERR 2970 /* Voltage PMA Low Err Threshold */
6503+
6504+/*
6505+ * VAUX (YUKON only)
6506+ */
6507+#define SK_SEN_VAUX_3V3_VAL 3300 /* Voltage VAUX 3.3 Volt */
6508+
6509+#define SK_SEN_VAUX_3V3_HIGH_ERR (SK_I32)(SK_SEN_VAUX_3V3_VAL * C_PLUS_10)
6510+#define SK_SEN_VAUX_3V3_HIGH_WARN (SK_I32)(SK_SEN_VAUX_3V3_VAL * C_PLUS_5)
6511+#define SK_SEN_VAUX_3V3_LOW_WARN (SK_I32)(SK_SEN_VAUX_3V3_VAL * C_MINUS_5)
6512+#define SK_SEN_VAUX_3V3_LOW_ERR (SK_I32)(SK_SEN_VAUX_3V3_VAL * C_MINUS_10)
6513+
6514+#define SK_SEN_VAUX_RANGE_LIMITER 1000 /* 1000 mV range delimiter */
6515+
6516+/*
6517+ * PHY 2V5 voltage
6518+ */
6519+#define SK_SEN_PHY_2V5_VAL 2500 /* Voltage PHY 2.5 Volt */
6520+
6521+#define SK_SEN_PHY_2V5_HIGH_ERR (SK_I32)(SK_SEN_PHY_2V5_VAL * C_PLUS_10)
6522+#define SK_SEN_PHY_2V5_HIGH_WARN (SK_I32)(SK_SEN_PHY_2V5_VAL * C_PLUS_5)
6523+#define SK_SEN_PHY_2V5_LOW_WARN (SK_I32)(SK_SEN_PHY_2V5_VAL * C_MINUS_5)
6524+#define SK_SEN_PHY_2V5_LOW_ERR (SK_I32)(SK_SEN_PHY_2V5_VAL * C_MINUS_10)
6525+
6526+/*
6527+ * ASIC Core 1V5 voltage (YUKON only)
6528+ */
6529+#define SK_SEN_CORE_1V5_VAL 1500 /* Voltage ASIC Core 1.5 Volt */
6530+
6531+#define SK_SEN_CORE_1V5_HIGH_ERR (SK_I32)(SK_SEN_CORE_1V5_VAL * C_PLUS_10)
6532+#define SK_SEN_CORE_1V5_HIGH_WARN (SK_I32)(SK_SEN_CORE_1V5_VAL * C_PLUS_5)
6533+#define SK_SEN_CORE_1V5_LOW_WARN (SK_I32)(SK_SEN_CORE_1V5_VAL * C_MINUS_5)
6534+#define SK_SEN_CORE_1V5_LOW_ERR (SK_I32)(SK_SEN_CORE_1V5_VAL * C_MINUS_10)
6535+
6536+/*
6537+ * ASIC Core 1V2 (1V3) voltage (YUKON-2 only)
6538+ */
6539+#define SK_SEN_CORE_1V2_VAL 1200 /* Voltage ASIC Core 1.2 Volt */
6540+
6541+#define SK_SEN_CORE_1V2_HIGH_ERR (SK_I32)(SK_SEN_CORE_1V2_VAL * C_PLUS_20)
6542+#define SK_SEN_CORE_1V2_HIGH_WARN (SK_I32)(SK_SEN_CORE_1V2_VAL * C_PLUS_15)
6543+#define SK_SEN_CORE_1V2_LOW_WARN (SK_I32)(SK_SEN_CORE_1V2_VAL * C_MINUS_5)
6544+#define SK_SEN_CORE_1V2_LOW_ERR (SK_I32)(SK_SEN_CORE_1V2_VAL * C_MINUS_10)
6545+
6546+#define SK_SEN_CORE_1V3_VAL 1300 /* Voltage ASIC Core 1.3 Volt */
6547+
6548+#define SK_SEN_CORE_1V3_HIGH_ERR (SK_I32)(SK_SEN_CORE_1V3_VAL * C_PLUS_15)
6549+#define SK_SEN_CORE_1V3_HIGH_WARN (SK_I32)(SK_SEN_CORE_1V3_VAL * C_PLUS_10)
6550+#define SK_SEN_CORE_1V3_LOW_WARN (SK_I32)(SK_SEN_CORE_1V3_VAL * C_MINUS_5)
6551+#define SK_SEN_CORE_1V3_LOW_ERR (SK_I32)(SK_SEN_CORE_1V3_VAL * C_MINUS_10)
6552+
6553+/*
6554+ * FAN 1 speed
6555+ */
6556+/* assuming: 6500rpm +-15%, 4 pulses,
6557+ * warning at: 80 %
6558+ * error at: 70 %
6559+ * no upper limit
6560+ */
6561+#define SK_SEN_FAN_HIGH_ERR 20000 /* FAN Speed High Err Threshold */
6562+#define SK_SEN_FAN_HIGH_WARN 20000 /* FAN Speed High Warn Threshold */
6563+#define SK_SEN_FAN_LOW_WARN 5200 /* FAN Speed Low Warn Threshold */
6564+#define SK_SEN_FAN_LOW_ERR 4550 /* FAN Speed Low Err Threshold */
6565+
6566+/*
6567+ * Some Voltages need dynamic thresholds
6568+ */
6569+#define SK_SEN_DYN_INIT_NONE 0 /* No dynamic init of thresholds */
6570+#define SK_SEN_DYN_INIT_PCI_IO 10 /* Init PCI-IO with new thresholds */
6571+#define SK_SEN_DYN_INIT_VAUX 11 /* Init VAUX with new thresholds */
6572+
6573+extern int SkLm80ReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen);
6574+#endif /* n_INC_SKGETWSI_H */
6575+
6576diff -urN linux-2.6.17.orig/drivers/net/sk98lin/h/ski2c.h linux-2.6.17/drivers/net/sk98lin/h/ski2c.h
6577--- linux-2.6.17.orig/drivers/net/sk98lin/h/ski2c.h 2006-06-22 13:17:16.000000000 +0200
6578+++ linux-2.6.17/drivers/net/sk98lin/h/ski2c.h 1970-01-01 01:00:00.000000000 +0100
6579@@ -1,174 +0,0 @@
6580-/******************************************************************************
6581- *
6582- * Name: ski2c.h
6583- * Project: Gigabit Ethernet Adapters, TWSI-Module
6584- * Version: $Revision$
6585- * Date: $Date$
6586- * Purpose: Defines to access Voltage and Temperature Sensor
6587- *
6588- ******************************************************************************/
6589-
6590-/******************************************************************************
6591- *
6592- * (C)Copyright 1998-2002 SysKonnect.
6593- * (C)Copyright 2002-2003 Marvell.
6594- *
6595- * This program is free software; you can redistribute it and/or modify
6596- * it under the terms of the GNU General Public License as published by
6597- * the Free Software Foundation; either version 2 of the License, or
6598- * (at your option) any later version.
6599- *
6600- * The information in this file is provided "AS IS" without warranty.
6601- *
6602- ******************************************************************************/
6603-
6604-/*
6605- * SKI2C.H contains all I2C specific defines
6606- */
6607-
6608-#ifndef _SKI2C_H_
6609-#define _SKI2C_H_
6610-
6611-typedef struct s_Sensor SK_SENSOR;
6612-
6613-#include "h/skgei2c.h"
6614-
6615-/*
6616- * Define the I2C events.
6617- */
6618-#define SK_I2CEV_IRQ 1 /* IRQ happened Event */
6619-#define SK_I2CEV_TIM 2 /* Timeout event */
6620-#define SK_I2CEV_CLEAR 3 /* Clear MIB Values */
6621-
6622-/*
6623- * Define READ and WRITE Constants.
6624- */
6625-#define I2C_READ 0
6626-#define I2C_WRITE 1
6627-#define I2C_BURST 1
6628-#define I2C_SINGLE 0
6629-
6630-#define SKERR_I2C_E001 (SK_ERRBASE_I2C+0)
6631-#define SKERR_I2C_E001MSG "Sensor index unknown"
6632-#define SKERR_I2C_E002 (SKERR_I2C_E001+1)
6633-#define SKERR_I2C_E002MSG "TWSI: transfer does not complete"
6634-#define SKERR_I2C_E003 (SKERR_I2C_E002+1)
6635-#define SKERR_I2C_E003MSG "LM80: NAK on device send"
6636-#define SKERR_I2C_E004 (SKERR_I2C_E003+1)
6637-#define SKERR_I2C_E004MSG "LM80: NAK on register send"
6638-#define SKERR_I2C_E005 (SKERR_I2C_E004+1)
6639-#define SKERR_I2C_E005MSG "LM80: NAK on device (2) send"
6640-#define SKERR_I2C_E006 (SKERR_I2C_E005+1)
6641-#define SKERR_I2C_E006MSG "Unknown event"
6642-#define SKERR_I2C_E007 (SKERR_I2C_E006+1)
6643-#define SKERR_I2C_E007MSG "LM80 read out of state"
6644-#define SKERR_I2C_E008 (SKERR_I2C_E007+1)
6645-#define SKERR_I2C_E008MSG "Unexpected sensor read completed"
6646-#define SKERR_I2C_E009 (SKERR_I2C_E008+1)
6647-#define SKERR_I2C_E009MSG "WARNING: temperature sensor out of range"
6648-#define SKERR_I2C_E010 (SKERR_I2C_E009+1)
6649-#define SKERR_I2C_E010MSG "WARNING: voltage sensor out of range"
6650-#define SKERR_I2C_E011 (SKERR_I2C_E010+1)
6651-#define SKERR_I2C_E011MSG "ERROR: temperature sensor out of range"
6652-#define SKERR_I2C_E012 (SKERR_I2C_E011+1)
6653-#define SKERR_I2C_E012MSG "ERROR: voltage sensor out of range"
6654-#define SKERR_I2C_E013 (SKERR_I2C_E012+1)
6655-#define SKERR_I2C_E013MSG "ERROR: couldn't init sensor"
6656-#define SKERR_I2C_E014 (SKERR_I2C_E013+1)
6657-#define SKERR_I2C_E014MSG "WARNING: fan sensor out of range"
6658-#define SKERR_I2C_E015 (SKERR_I2C_E014+1)
6659-#define SKERR_I2C_E015MSG "ERROR: fan sensor out of range"
6660-#define SKERR_I2C_E016 (SKERR_I2C_E015+1)
6661-#define SKERR_I2C_E016MSG "TWSI: active transfer does not complete"
6662-
6663-/*
6664- * Define Timeout values
6665- */
6666-#define SK_I2C_TIM_LONG 2000000L /* 2 seconds */
6667-#define SK_I2C_TIM_SHORT 100000L /* 100 milliseconds */
6668-#define SK_I2C_TIM_WATCH 1000000L /* 1 second */
6669-
6670-/*
6671- * Define trap and error log hold times
6672- */
6673-#ifndef SK_SEN_ERR_TR_HOLD
6674-#define SK_SEN_ERR_TR_HOLD (4*SK_TICKS_PER_SEC)
6675-#endif
6676-#ifndef SK_SEN_ERR_LOG_HOLD
6677-#define SK_SEN_ERR_LOG_HOLD (60*SK_TICKS_PER_SEC)
6678-#endif
6679-#ifndef SK_SEN_WARN_TR_HOLD
6680-#define SK_SEN_WARN_TR_HOLD (15*SK_TICKS_PER_SEC)
6681-#endif
6682-#ifndef SK_SEN_WARN_LOG_HOLD
6683-#define SK_SEN_WARN_LOG_HOLD (15*60*SK_TICKS_PER_SEC)
6684-#endif
6685-
6686-/*
6687- * Defines for SenType
6688- */
6689-#define SK_SEN_UNKNOWN 0
6690-#define SK_SEN_TEMP 1
6691-#define SK_SEN_VOLT 2
6692-#define SK_SEN_FAN 3
6693-
6694-/*
6695- * Define for the SenErrorFlag
6696- */
6697-#define SK_SEN_ERR_NOT_PRESENT 0 /* Error Flag: Sensor not present */
6698-#define SK_SEN_ERR_OK 1 /* Error Flag: O.K. */
6699-#define SK_SEN_ERR_WARN 2 /* Error Flag: Warning */
6700-#define SK_SEN_ERR_ERR 3 /* Error Flag: Error */
6701-#define SK_SEN_ERR_FAULTY 4 /* Error Flag: Faulty */
6702-
6703-/*
6704- * Define the Sensor struct
6705- */
6706-struct s_Sensor {
6707- char *SenDesc; /* Description */
6708- int SenType; /* Voltage or Temperature */
6709- SK_I32 SenValue; /* Current value of the sensor */
6710- SK_I32 SenThreErrHigh; /* High error Threshhold of this sensor */
6711- SK_I32 SenThreWarnHigh; /* High warning Threshhold of this sensor */
6712- SK_I32 SenThreErrLow; /* Lower error Threshold of the sensor */
6713- SK_I32 SenThreWarnLow; /* Lower warning Threshold of the sensor */
6714- int SenErrFlag; /* Sensor indicated an error */
6715- SK_BOOL SenInit; /* Is sensor initialized ? */
6716- SK_U64 SenErrCts; /* Error trap counter */
6717- SK_U64 SenWarnCts; /* Warning trap counter */
6718- SK_U64 SenBegErrTS; /* Begin error timestamp */
6719- SK_U64 SenBegWarnTS; /* Begin warning timestamp */
6720- SK_U64 SenLastErrTrapTS; /* Last error trap timestamp */
6721- SK_U64 SenLastErrLogTS; /* Last error log timestamp */
6722- SK_U64 SenLastWarnTrapTS; /* Last warning trap timestamp */
6723- SK_U64 SenLastWarnLogTS; /* Last warning log timestamp */
6724- int SenState; /* Sensor State (see HW specific include) */
6725- int (*SenRead)(SK_AC *pAC, SK_IOC IoC, struct s_Sensor *pSen);
6726- /* Sensors read function */
6727- SK_U16 SenReg; /* Register Address for this sensor */
6728- SK_U8 SenDev; /* Device Selection for this sensor */
6729-};
6730-
6731-typedef struct s_I2c {
6732- SK_SENSOR SenTable[SK_MAX_SENSORS]; /* Sensor Table */
6733- int CurrSens; /* Which sensor is currently queried */
6734- int MaxSens; /* Max. number of sensors */
6735- int TimerMode; /* Use the timer also to watch the state machine */
6736- int InitLevel; /* Initialized Level */
6737-#ifndef SK_DIAG
6738- int DummyReads; /* Number of non-checked dummy reads */
6739- SK_TIMER SenTimer; /* Sensors timer */
6740-#endif /* !SK_DIAG */
6741-} SK_I2C;
6742-
6743-extern int SkI2cInit(SK_AC *pAC, SK_IOC IoC, int Level);
6744-#ifdef SK_DIAG
6745-extern SK_U32 SkI2cRead(SK_AC *pAC, SK_IOC IoC, int Dev, int Size, int Reg,
6746- int Burst);
6747-#else /* !SK_DIAG */
6748-extern int SkI2cEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Para);
6749-extern void SkI2cWaitIrq(SK_AC *pAC, SK_IOC IoC);
6750-extern void SkI2cIsr(SK_AC *pAC, SK_IOC IoC);
6751-#endif /* !SK_DIAG */
6752-#endif /* n_SKI2C_H */
6753-
6754diff -urN linux-2.6.17.orig/drivers/net/sk98lin/h/skqueue.h linux-2.6.17/drivers/net/sk98lin/h/skqueue.h
6755--- linux-2.6.17.orig/drivers/net/sk98lin/h/skqueue.h 2006-06-22 13:17:16.000000000 +0200
6756+++ linux-2.6.17/drivers/net/sk98lin/h/skqueue.h 2006-04-27 11:43:44.000000000 +0200
6757@@ -2,8 +2,8 @@
6758 *
6759 * Name: skqueue.h
6760 * Project: Gigabit Ethernet Adapters, Event Scheduler Module
6761- * Version: $Revision$
6762- * Date: $Date$
6763+ * Version: $Revision$
6764+ * Date: $Date$
6765 * Purpose: Defines for the Event queue
6766 *
6767 ******************************************************************************/
6768@@ -45,6 +45,9 @@
6769 #define SKGE_RSF 11 /* RSF Aggregation Event Class */
6770 #define SKGE_MARKER 12 /* MARKER Aggregation Event Class */
6771 #define SKGE_FD 13 /* FD Distributor Event Class */
6772+#ifdef SK_ASF
6773+#define SKGE_ASF 14 /* ASF Event Class */
6774+#endif
6775
6776 /*
6777 * define event queue as circular buffer
6778@@ -90,5 +93,11 @@
6779 #define SKERR_Q_E001MSG "Event queue overflow"
6780 #define SKERR_Q_E002 (SKERR_Q_E001+1)
6781 #define SKERR_Q_E002MSG "Undefined event class"
6782+#define SKERR_Q_E003 (SKERR_Q_E001+2)
6783+#define SKERR_Q_E003MSG "Event queued in Init Level 0"
6784+#define SKERR_Q_E004 (SKERR_Q_E001+3)
6785+#define SKERR_Q_E004MSG "Error Reported from Event Fuction (Queue Blocked)"
6786+#define SKERR_Q_E005 (SKERR_Q_E001+4)
6787+#define SKERR_Q_E005MSG "Event scheduler called in Init Level 0 or 1"
6788 #endif /* _SKQUEUE_H_ */
6789
6790diff -urN linux-2.6.17.orig/drivers/net/sk98lin/h/skrlmt.h linux-2.6.17/drivers/net/sk98lin/h/skrlmt.h
6791--- linux-2.6.17.orig/drivers/net/sk98lin/h/skrlmt.h 2006-06-22 13:17:16.000000000 +0200
6792+++ linux-2.6.17/drivers/net/sk98lin/h/skrlmt.h 2006-04-27 11:43:44.000000000 +0200
6793@@ -2,14 +2,15 @@
6794 *
6795 * Name: skrlmt.h
6796 * Project: GEnesis, PCI Gigabit Ethernet Adapter
6797- * Version: $Revision$
6798- * Date: $Date$
6799+ * Version: $Revision$
6800+ * Date: $Date$
6801 * Purpose: Header file for Redundant Link ManagemenT.
6802 *
6803 ******************************************************************************/
6804
6805 /******************************************************************************
6806 *
6807+ * LICENSE:
6808 * (C)Copyright 1998-2002 SysKonnect GmbH.
6809 * (C)Copyright 2002-2003 Marvell.
6810 *
6811@@ -19,6 +20,7 @@
6812 * (at your option) any later version.
6813 *
6814 * The information in this file is provided "AS IS" without warranty.
6815+ * /LICENSE
6816 *
6817 ******************************************************************************/
6818
6819diff -urN linux-2.6.17.orig/drivers/net/sk98lin/h/sktimer.h linux-2.6.17/drivers/net/sk98lin/h/sktimer.h
6820--- linux-2.6.17.orig/drivers/net/sk98lin/h/sktimer.h 2006-06-22 13:17:16.000000000 +0200
6821+++ linux-2.6.17/drivers/net/sk98lin/h/sktimer.h 2006-04-27 11:43:44.000000000 +0200
6822@@ -2,8 +2,8 @@
6823 *
6824 * Name: sktimer.h
6825 * Project: Gigabit Ethernet Adapters, Event Scheduler Module
6826- * Version: $Revision$
6827- * Date: $Date$
6828+ * Version: $Revision$
6829+ * Date: $Date$
6830 * Purpose: Defines for the timer functions
6831 *
6832 ******************************************************************************/
6833diff -urN linux-2.6.17.orig/drivers/net/sk98lin/h/sktwsi.h linux-2.6.17/drivers/net/sk98lin/h/sktwsi.h
6834--- linux-2.6.17.orig/drivers/net/sk98lin/h/sktwsi.h 1970-01-01 01:00:00.000000000 +0100
6835+++ linux-2.6.17/drivers/net/sk98lin/h/sktwsi.h 2006-04-27 11:43:44.000000000 +0200
6836@@ -0,0 +1,179 @@
6837+/******************************************************************************
6838+ *
6839+ * Name: sktwsi.h
6840+ * Project: Gigabit Ethernet Adapters, TWSI-Module
6841+ * Version: $Revision$
6842+ * Date: $Date$
6843+ * Purpose: Defines to access Voltage and Temperature Sensor
6844+ *
6845+ ******************************************************************************/
6846+
6847+/******************************************************************************
6848+ *
6849+ * LICENSE:
6850+ * (C)Copyright 1998-2002 SysKonnect.
6851+ * (C)Copyright 2002-2003 Marvell.
6852+ *
6853+ * This program is free software; you can redistribute it and/or modify
6854+ * it under the terms of the GNU General Public License as published by
6855+ * the Free Software Foundation; either version 2 of the License, or
6856+ * (at your option) any later version.
6857+ *
6858+ * The information in this file is provided "AS IS" without warranty.
6859+ * /LICENSE
6860+ *
6861+ ******************************************************************************/
6862+
6863+/*
6864+ * SKTWSI.H contains all TWSI specific defines
6865+ */
6866+
6867+#ifndef _SKTWSI_H_
6868+#define _SKTWSI_H_
6869+
6870+typedef struct s_Sensor SK_SENSOR;
6871+
6872+#include "h/skgetwsi.h"
6873+
6874+/*
6875+ * Define the TWSI events.
6876+ */
6877+#define SK_I2CEV_IRQ 1 /* IRQ happened Event */
6878+#define SK_I2CEV_TIM 2 /* Timeout event */
6879+#define SK_I2CEV_CLEAR 3 /* Clear MIB Values */
6880+
6881+/*
6882+ * Define READ and WRITE Constants.
6883+ */
6884+#define I2C_READ 0
6885+#define I2C_WRITE 1
6886+#define I2C_BURST 1
6887+#define I2C_SINGLE 0
6888+
6889+#define SKERR_I2C_E001 (SK_ERRBASE_I2C+0)
6890+#define SKERR_I2C_E001MSG "Sensor index unknown"
6891+#define SKERR_I2C_E002 (SKERR_I2C_E001+1)
6892+#define SKERR_I2C_E002MSG "TWSI: transfer does not complete"
6893+#define SKERR_I2C_E003 (SKERR_I2C_E002+1)
6894+#define SKERR_I2C_E003MSG "LM80: NAK on device send"
6895+#define SKERR_I2C_E004 (SKERR_I2C_E003+1)
6896+#define SKERR_I2C_E004MSG "LM80: NAK on register send"
6897+#define SKERR_I2C_E005 (SKERR_I2C_E004+1)
6898+#define SKERR_I2C_E005MSG "LM80: NAK on device (2) send"
6899+#define SKERR_I2C_E006 (SKERR_I2C_E005+1)
6900+#define SKERR_I2C_E006MSG "Unknown event"
6901+#define SKERR_I2C_E007 (SKERR_I2C_E006+1)
6902+#define SKERR_I2C_E007MSG "LM80 read out of state"
6903+#define SKERR_I2C_E008 (SKERR_I2C_E007+1)
6904+#define SKERR_I2C_E008MSG "Unexpected sensor read completed"
6905+#define SKERR_I2C_E009 (SKERR_I2C_E008+1)
6906+#define SKERR_I2C_E009MSG "WARNING: temperature sensor out of range"
6907+#define SKERR_I2C_E010 (SKERR_I2C_E009+1)
6908+#define SKERR_I2C_E010MSG "WARNING: voltage sensor out of range"
6909+#define SKERR_I2C_E011 (SKERR_I2C_E010+1)
6910+#define SKERR_I2C_E011MSG "ERROR: temperature sensor out of range"
6911+#define SKERR_I2C_E012 (SKERR_I2C_E011+1)
6912+#define SKERR_I2C_E012MSG "ERROR: voltage sensor out of range"
6913+#define SKERR_I2C_E013 (SKERR_I2C_E012+1)
6914+#define SKERR_I2C_E013MSG "ERROR: couldn't init sensor"
6915+#define SKERR_I2C_E014 (SKERR_I2C_E013+1)
6916+#define SKERR_I2C_E014MSG "WARNING: fan sensor out of range"
6917+#define SKERR_I2C_E015 (SKERR_I2C_E014+1)
6918+#define SKERR_I2C_E015MSG "ERROR: fan sensor out of range"
6919+#define SKERR_I2C_E016 (SKERR_I2C_E015+1)
6920+#define SKERR_I2C_E016MSG "TWSI: active transfer does not complete"
6921+
6922+/*
6923+ * Define Timeout values
6924+ */
6925+#define SK_I2C_TIM_LONG 2000000L /* 2 seconds */
6926+#define SK_I2C_TIM_SHORT 100000L /* 100 milliseconds */
6927+#define SK_I2C_TIM_WATCH 1000000L /* 1 second */
6928+
6929+/*
6930+ * Define trap and error log hold times
6931+ */
6932+#ifndef SK_SEN_ERR_TR_HOLD
6933+#define SK_SEN_ERR_TR_HOLD (4*SK_TICKS_PER_SEC)
6934+#endif
6935+#ifndef SK_SEN_ERR_LOG_HOLD
6936+#define SK_SEN_ERR_LOG_HOLD (60*SK_TICKS_PER_SEC)
6937+#endif
6938+#ifndef SK_SEN_WARN_TR_HOLD
6939+#define SK_SEN_WARN_TR_HOLD (15*SK_TICKS_PER_SEC)
6940+#endif
6941+#ifndef SK_SEN_WARN_LOG_HOLD
6942+#define SK_SEN_WARN_LOG_HOLD (15*60*SK_TICKS_PER_SEC)
6943+#endif
6944+
6945+/*
6946+ * Defines for SenType
6947+ */
6948+#define SK_SEN_UNKNOWN 0
6949+#define SK_SEN_TEMP 1
6950+#define SK_SEN_VOLT 2
6951+#define SK_SEN_FAN 3
6952+
6953+/*
6954+ * Define for the SenErrorFlag
6955+ */
6956+#define SK_SEN_ERR_NOT_PRESENT 0 /* Error Flag: Sensor not present */
6957+#define SK_SEN_ERR_OK 1 /* Error Flag: O.K. */
6958+#define SK_SEN_ERR_WARN 2 /* Error Flag: Warning */
6959+#define SK_SEN_ERR_ERR 3 /* Error Flag: Error */
6960+#define SK_SEN_ERR_FAULTY 4 /* Error Flag: Faulty */
6961+
6962+/*
6963+ * Define the Sensor struct
6964+ */
6965+struct s_Sensor {
6966+ char *SenDesc; /* Description */
6967+ int SenType; /* Voltage or Temperature */
6968+ SK_I32 SenValue; /* Current value of the sensor */
6969+ SK_I32 SenThreErrHigh; /* High error Threshhold of this sensor */
6970+ SK_I32 SenThreWarnHigh; /* High warning Threshhold of this sensor */
6971+ SK_I32 SenThreErrLow; /* Lower error Threshold of the sensor */
6972+ SK_I32 SenThreWarnLow; /* Lower warning Threshold of the sensor */
6973+ int SenErrFlag; /* Sensor indicated an error */
6974+ SK_BOOL SenInit; /* Is sensor initialized ? */
6975+ SK_U64 SenErrCts; /* Error trap counter */
6976+ SK_U64 SenWarnCts; /* Warning trap counter */
6977+ SK_U64 SenBegErrTS; /* Begin error timestamp */
6978+ SK_U64 SenBegWarnTS; /* Begin warning timestamp */
6979+ SK_U64 SenLastErrTrapTS; /* Last error trap timestamp */
6980+ SK_U64 SenLastErrLogTS; /* Last error log timestamp */
6981+ SK_U64 SenLastWarnTrapTS; /* Last warning trap timestamp */
6982+ SK_U64 SenLastWarnLogTS; /* Last warning log timestamp */
6983+ int SenState; /* Sensor State (see HW specific include) */
6984+ int (*SenRead)(SK_AC *pAC, SK_IOC IoC, struct s_Sensor *pSen);
6985+ /* Sensors read function */
6986+ SK_U16 SenReg; /* Register Address for this sensor */
6987+ SK_U8 SenDev; /* Device Selection for this sensor */
6988+};
6989+
6990+typedef struct s_I2c {
6991+ SK_SENSOR SenTable[SK_MAX_SENSORS]; /* Sensor Table */
6992+ int CurrSens; /* Which sensor is currently queried */
6993+ int MaxSens; /* Max. number of sensors */
6994+ int TimerMode; /* Use the timer also to watch the state machine */
6995+ int InitLevel; /* Initialized Level */
6996+#ifndef SK_DIAG
6997+ int DummyReads; /* Number of non-checked dummy reads */
6998+ SK_TIMER SenTimer; /* Sensors timer */
6999+#endif /* !SK_DIAG */
7000+} SK_I2C;
7001+
7002+extern int SkI2cInit(SK_AC *pAC, SK_IOC IoC, int Level);
7003+extern int SkI2cWrite(SK_AC *pAC, SK_IOC IoC, SK_U32 Data, int Dev, int Size,
7004+ int Reg, int Burst);
7005+extern int SkI2cReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen);
7006+#ifdef SK_DIAG
7007+extern SK_U32 SkI2cRead(SK_AC *pAC, SK_IOC IoC, int Dev, int Size, int Reg,
7008+ int Burst);
7009+#else /* !SK_DIAG */
7010+extern int SkI2cEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Para);
7011+extern void SkI2cWaitIrq(SK_AC *pAC, SK_IOC IoC);
7012+extern void SkI2cIsr(SK_AC *pAC, SK_IOC IoC);
7013+#endif /* !SK_DIAG */
7014+#endif /* n_SKTWSI_H */
7015+
7016diff -urN linux-2.6.17.orig/drivers/net/sk98lin/h/sktypes.h linux-2.6.17/drivers/net/sk98lin/h/sktypes.h
7017--- linux-2.6.17.orig/drivers/net/sk98lin/h/sktypes.h 2006-06-22 13:17:16.000000000 +0200
7018+++ linux-2.6.17/drivers/net/sk98lin/h/sktypes.h 2006-04-27 11:43:44.000000000 +0200
7019@@ -2,8 +2,8 @@
7020 *
7021 * Name: sktypes.h
7022 * Project: GEnesis, PCI Gigabit Ethernet Adapter
7023- * Version: $Revision$
7024- * Date: $Date$
7025+ * Version: $Revision$
7026+ * Date: $Date$
7027 * Purpose: Define data types for Linux
7028 *
7029 ******************************************************************************/
7030@@ -11,7 +11,7 @@
7031 /******************************************************************************
7032 *
7033 * (C)Copyright 1998-2002 SysKonnect GmbH.
7034- * (C)Copyright 2002-2003 Marvell.
7035+ * (C)Copyright 2002-2005 Marvell.
7036 *
7037 * This program is free software; you can redistribute it and/or modify
7038 * it under the terms of the GNU General Public License as published by
7039@@ -22,48 +22,28 @@
7040 *
7041 ******************************************************************************/
7042
7043-/******************************************************************************
7044- *
7045- * Description:
7046- *
7047- * In this file, all data types that are needed by the common modules
7048- * are mapped to Linux data types.
7049- *
7050- *
7051- * Include File Hierarchy:
7052- *
7053- *
7054- ******************************************************************************/
7055-
7056 #ifndef __INC_SKTYPES_H
7057 #define __INC_SKTYPES_H
7058
7059-
7060-/* defines *******************************************************************/
7061-
7062-/*
7063- * Data types with a specific size. 'I' = signed, 'U' = unsigned.
7064- */
7065-#define SK_I8 s8
7066-#define SK_U8 u8
7067-#define SK_I16 s16
7068-#define SK_U16 u16
7069-#define SK_I32 s32
7070-#define SK_U32 u32
7071-#define SK_I64 s64
7072-#define SK_U64 u64
7073-
7074-#define SK_UPTR ulong /* casting pointer <-> integral */
7075-
7076-/*
7077-* Boolean type.
7078-*/
7079-#define SK_BOOL SK_U8
7080-#define SK_FALSE 0
7081-#define SK_TRUE (!SK_FALSE)
7082-
7083-/* typedefs *******************************************************************/
7084-
7085-/* function prototypes ********************************************************/
7086+#define SK_I8 s8 /* 8 bits (1 byte) signed */
7087+#define SK_U8 u8 /* 8 bits (1 byte) unsigned */
7088+#define SK_I16 s16 /* 16 bits (2 bytes) signed */
7089+#define SK_U16 u16 /* 16 bits (2 bytes) unsigned */
7090+#define SK_I32 s32 /* 32 bits (4 bytes) signed */
7091+#define SK_U32 u32 /* 32 bits (4 bytes) unsigned */
7092+#define SK_I64 s64 /* 64 bits (8 bytes) signed */
7093+#define SK_U64 u64 /* 64 bits (8 bytes) unsigned */
7094+
7095+#define SK_UPTR ulong /* casting pointer <-> integral */
7096+
7097+#define SK_BOOL SK_U8
7098+#define SK_FALSE 0
7099+#define SK_TRUE (!SK_FALSE)
7100
7101 #endif /* __INC_SKTYPES_H */
7102+
7103+/*******************************************************************************
7104+ *
7105+ * End of file
7106+ *
7107+ ******************************************************************************/
7108diff -urN linux-2.6.17.orig/drivers/net/sk98lin/h/skversion.h linux-2.6.17/drivers/net/sk98lin/h/skversion.h
7109--- linux-2.6.17.orig/drivers/net/sk98lin/h/skversion.h 2006-06-22 13:17:16.000000000 +0200
7110+++ linux-2.6.17/drivers/net/sk98lin/h/skversion.h 2006-04-27 11:43:44.000000000 +0200
7111@@ -1,17 +1,17 @@
7112 /******************************************************************************
7113 *
7114- * Name: version.h
7115+ * Name: skversion.h
7116 * Project: GEnesis, PCI Gigabit Ethernet Adapter
7117- * Version: $Revision$
7118- * Date: $Date$
7119- * Purpose: SK specific Error log support
7120+ * Version: $Revision$
7121+ * Date: $Date$
7122+ * Purpose: specific version strings and numbers
7123 *
7124 ******************************************************************************/
7125
7126 /******************************************************************************
7127 *
7128 * (C)Copyright 1998-2002 SysKonnect GmbH.
7129- * (C)Copyright 2002-2003 Marvell.
7130+ * (C)Copyright 2002-2005 Marvell.
7131 *
7132 * This program is free software; you can redistribute it and/or modify
7133 * it under the terms of the GNU General Public License as published by
7134@@ -22,17 +22,15 @@
7135 *
7136 ******************************************************************************/
7137
7138-#ifdef lint
7139-static const char SysKonnectFileId[] = "@(#) (C) SysKonnect GmbH.";
7140-static const char SysKonnectBuildNumber[] =
7141- "@(#)SK-BUILD: 6.23 PL: 01";
7142-#endif /* !defined(lint) */
7143-
7144-#define BOOT_STRING "sk98lin: Network Device Driver v6.23\n" \
7145- "(C)Copyright 1999-2004 Marvell(R)."
7146-
7147-#define VER_STRING "6.23"
7148-#define DRIVER_FILE_NAME "sk98lin"
7149-#define DRIVER_REL_DATE "Feb-13-2004"
7150-
7151+#define BOOT_STRING "sk98lin: Network Device Driver v8.32.2.3\n" \
7152+ "(C)Copyright 1999-2006 Marvell(R)."
7153+#define VER_STRING "8.32.2.3"
7154+#define PATCHLEVEL "02"
7155+#define DRIVER_FILE_NAME "sk98lin"
7156+#define DRIVER_REL_DATE "Apr-27-2006"
7157
7158+/*******************************************************************************
7159+ *
7160+ * End of file
7161+ *
7162+ ******************************************************************************/
7163diff -urN linux-2.6.17.orig/drivers/net/sk98lin/h/skvpd.h linux-2.6.17/drivers/net/sk98lin/h/skvpd.h
7164--- linux-2.6.17.orig/drivers/net/sk98lin/h/skvpd.h 2006-06-22 13:17:16.000000000 +0200
7165+++ linux-2.6.17/drivers/net/sk98lin/h/skvpd.h 2006-04-27 11:43:44.000000000 +0200
7166@@ -1,22 +1,22 @@
7167 /******************************************************************************
7168 *
7169 * Name: skvpd.h
7170- * Project: GEnesis, PCI Gigabit Ethernet Adapter
7171- * Version: $Revision$
7172- * Date: $Date$
7173+ * Project: Gigabit Ethernet Adapters, VPD-Module
7174+ * Version: $Revision$
7175+ * Date: $Date$
7176 * Purpose: Defines and Macros for VPD handling
7177 *
7178 ******************************************************************************/
7179
7180 /******************************************************************************
7181 *
7182- * (C)Copyright 1998-2003 SysKonnect GmbH.
7183+ * (C)Copyright 1998-2002 SysKonnect.
7184+ * (C)Copyright 2002-2004 Marvell.
7185 *
7186 * This program is free software; you can redistribute it and/or modify
7187 * it under the terms of the GNU General Public License as published by
7188 * the Free Software Foundation; either version 2 of the License, or
7189 * (at your option) any later version.
7190- *
7191 * The information in this file is provided "AS IS" without warranty.
7192 *
7193 ******************************************************************************/
7194@@ -31,7 +31,7 @@
7195 /*
7196 * Define Resource Type Identifiers and VPD keywords
7197 */
7198-#define RES_ID 0x82 /* Resource Type ID String (Product Name) */
7199+#define RES_ID 0x82 /* Resource Type ID String (Product Name) */
7200 #define RES_VPD_R 0x90 /* start of VPD read only area */
7201 #define RES_VPD_W 0x91 /* start of VPD read/write area */
7202 #define RES_END 0x78 /* Resource Type End Tag */
7203@@ -40,14 +40,16 @@
7204 #define VPD_NAME "Name" /* Product Name, VPD name of RES_ID */
7205 #endif /* VPD_NAME */
7206 #define VPD_PN "PN" /* Adapter Part Number */
7207-#define VPD_EC "EC" /* Adapter Engineering Level */
7208+#define VPD_EC "EC" /* Adapter Engineering Level */
7209 #define VPD_MN "MN" /* Manufacture ID */
7210 #define VPD_SN "SN" /* Serial Number */
7211 #define VPD_CP "CP" /* Extended Capability */
7212 #define VPD_RV "RV" /* Checksum and Reserved */
7213-#define VPD_YA "YA" /* Asset Tag Identifier */
7214+#define VPD_YA "YA" /* Asset Tag Identifier */
7215 #define VPD_VL "VL" /* First Error Log Message (SK specific) */
7216 #define VPD_VF "VF" /* Second Error Log Message (SK specific) */
7217+#define VPD_VB "VB" /* Boot Agent ROM Configuration (SK specific) */
7218+#define VPD_VE "VE" /* EFI UNDI Configuration (SK specific) */
7219 #define VPD_RW "RW" /* Remaining Read / Write Area */
7220
7221 /* 'type' values for vpd_setup_para() */
7222@@ -55,7 +57,7 @@
7223 #define VPD_RW_KEY 2 /* RW keys are "Yx", "Vx", and "RW" */
7224
7225 /* 'op' values for vpd_setup_para() */
7226-#define ADD_KEY 1 /* add the key at the pos "RV" or "RW" */
7227+#define ADD_KEY 1 /* add the key at the pos "RV" or "RW" */
7228 #define OWR_KEY 2 /* overwrite key if already exists */
7229
7230 /*
7231@@ -64,18 +66,18 @@
7232
7233 #define VPD_DEV_ID_GENESIS 0x4300
7234
7235-#define VPD_SIZE_YUKON 256
7236-#define VPD_SIZE_GENESIS 512
7237-#define VPD_SIZE 512
7238+#define VPD_SIZE_YUKON 256
7239+#define VPD_SIZE_GENESIS 512
7240+#define VPD_SIZE 512
7241 #define VPD_READ 0x0000
7242 #define VPD_WRITE 0x8000
7243
7244 #define VPD_STOP(pAC,IoC) VPD_OUT16(pAC,IoC,PCI_VPD_ADR_REG,VPD_WRITE)
7245
7246-#define VPD_GET_RES_LEN(p) ((unsigned int) \
7247- (* (SK_U8 *)&(p)[1]) |\
7248- ((* (SK_U8 *)&(p)[2]) << 8))
7249-#define VPD_GET_VPD_LEN(p) ((unsigned int)(* (SK_U8 *)&(p)[2]))
7250+#define VPD_GET_RES_LEN(p) ((unsigned int)\
7251+ (*(SK_U8 *)&(p)[1]) |\
7252+ ((*(SK_U8 *)&(p)[2]) << 8))
7253+#define VPD_GET_VPD_LEN(p) ((unsigned int)(*(SK_U8 *)&(p)[2]))
7254 #define VPD_GET_VAL(p) ((char *)&(p)[3])
7255
7256 #define VPD_MAX_LEN 50
7257@@ -126,62 +128,78 @@
7258 /*
7259 * System specific VPD macros
7260 */
7261-#ifndef SKDIAG
7262+#ifndef SK_DIAG
7263 #ifndef VPD_DO_IO
7264 #define VPD_OUT8(pAC,IoC,Addr,Val) (void)SkPciWriteCfgByte(pAC,Addr,Val)
7265 #define VPD_OUT16(pAC,IoC,Addr,Val) (void)SkPciWriteCfgWord(pAC,Addr,Val)
7266+#define VPD_OUT32(pAC,IoC,Addr,Val) (void)SkPciWriteCfgDWord(pAC,Addr,Val)
7267 #define VPD_IN8(pAC,IoC,Addr,pVal) (void)SkPciReadCfgByte(pAC,Addr,pVal)
7268 #define VPD_IN16(pAC,IoC,Addr,pVal) (void)SkPciReadCfgWord(pAC,Addr,pVal)
7269 #define VPD_IN32(pAC,IoC,Addr,pVal) (void)SkPciReadCfgDWord(pAC,Addr,pVal)
7270 #else /* VPD_DO_IO */
7271-#define VPD_OUT8(pAC,IoC,Addr,Val) SK_OUT8(IoC,PCI_C(Addr),Val)
7272-#define VPD_OUT16(pAC,IoC,Addr,Val) SK_OUT16(IoC,PCI_C(Addr),Val)
7273-#define VPD_IN8(pAC,IoC,Addr,pVal) SK_IN8(IoC,PCI_C(Addr),pVal)
7274-#define VPD_IN16(pAC,IoC,Addr,pVal) SK_IN16(IoC,PCI_C(Addr),pVal)
7275-#define VPD_IN32(pAC,IoC,Addr,pVal) SK_IN32(IoC,PCI_C(Addr),pVal)
7276+#define VPD_OUT8(pAC,IoC,Addr,Val) SK_OUT8(IoC,PCI_C(pAC,Addr),Val)
7277+#define VPD_OUT16(pAC,IoC,Addr,Val) SK_OUT16(IoC,PCI_C(pAC,Addr),Val)
7278+#define VPD_OUT32(pAC,IoC,Addr,Val) SK_OUT32(IoC,PCI_C(pAC,Addr),Val)
7279+#define VPD_IN8(pAC,IoC,Addr,pVal) SK_IN8(IoC,PCI_C(pAC,Addr),pVal)
7280+#define VPD_IN16(pAC,IoC,Addr,pVal) SK_IN16(IoC,PCI_C(pAC,Addr),pVal)
7281+#define VPD_IN32(pAC,IoC,Addr,pVal) SK_IN32(IoC,PCI_C(pAC,Addr),pVal)
7282 #endif /* VPD_DO_IO */
7283-#else /* SKDIAG */
7284+#else /* SK_DIAG */
7285 #define VPD_OUT8(pAC,Ioc,Addr,Val) { \
7286 if ((pAC)->DgT.DgUseCfgCycle) \
7287 SkPciWriteCfgByte(pAC,Addr,Val); \
7288 else \
7289- SK_OUT8(pAC,PCI_C(Addr),Val); \
7290+ SK_OUT8(pAC,PCI_C(pAC,Addr),Val); \
7291 }
7292 #define VPD_OUT16(pAC,Ioc,Addr,Val) { \
7293 if ((pAC)->DgT.DgUseCfgCycle) \
7294 SkPciWriteCfgWord(pAC,Addr,Val); \
7295 else \
7296- SK_OUT16(pAC,PCI_C(Addr),Val); \
7297+ SK_OUT16(pAC,PCI_C(pAC,Addr),Val); \
7298+ }
7299+#define VPD_OUT32(pAC,Ioc,Addr,Val) { \
7300+ if ((pAC)->DgT.DgUseCfgCycle) \
7301+ SkPciWriteCfgDWord(pAC,Addr,Val); \
7302+ else \
7303+ SK_OUT32(pAC,PCI_C(pAC,Addr),Val); \
7304 }
7305 #define VPD_IN8(pAC,Ioc,Addr,pVal) { \
7306- if ((pAC)->DgT.DgUseCfgCycle) \
7307+ if ((pAC)->DgT.DgUseCfgCycle) \
7308 SkPciReadCfgByte(pAC,Addr,pVal); \
7309 else \
7310- SK_IN8(pAC,PCI_C(Addr),pVal); \
7311+ SK_IN8(pAC,PCI_C(pAC,Addr),pVal); \
7312 }
7313 #define VPD_IN16(pAC,Ioc,Addr,pVal) { \
7314- if ((pAC)->DgT.DgUseCfgCycle) \
7315+ if ((pAC)->DgT.DgUseCfgCycle) \
7316 SkPciReadCfgWord(pAC,Addr,pVal); \
7317 else \
7318- SK_IN16(pAC,PCI_C(Addr),pVal); \
7319+ SK_IN16(pAC,PCI_C(pAC,Addr),pVal); \
7320 }
7321 #define VPD_IN32(pAC,Ioc,Addr,pVal) { \
7322 if ((pAC)->DgT.DgUseCfgCycle) \
7323 SkPciReadCfgDWord(pAC,Addr,pVal); \
7324 else \
7325- SK_IN32(pAC,PCI_C(Addr),pVal); \
7326+ SK_IN32(pAC,PCI_C(pAC,Addr),pVal); \
7327 }
7328-#endif /* nSKDIAG */
7329+#endif /* SK_DIAG */
7330
7331 /* function prototypes ********************************************************/
7332
7333 #ifndef SK_KR_PROTO
7334-#ifdef SKDIAG
7335+#ifdef SK_DIAG
7336 extern SK_U32 VpdReadDWord(
7337 SK_AC *pAC,
7338 SK_IOC IoC,
7339 int addr);
7340-#endif /* SKDIAG */
7341+#endif /* SK_DIAG */
7342+
7343+extern int VpdSetupPara(
7344+ SK_AC *pAC,
7345+ const char *key,
7346+ const char *buf,
7347+ int len,
7348+ int type,
7349+ int op);
7350
7351 extern SK_VPD_STATUS *VpdStat(
7352 SK_AC *pAC,
7353@@ -219,7 +237,17 @@
7354 SK_AC *pAC,
7355 SK_IOC IoC);
7356
7357-#ifdef SKDIAG
7358+extern void VpdErrLog(
7359+ SK_AC *pAC,
7360+ SK_IOC IoC,
7361+ char *msg);
7362+
7363+int VpdInit(
7364+ SK_AC *pAC,
7365+ SK_IOC IoC);
7366+
7367+#if defined(SK_DIAG) || defined(SK_ASF)
7368+
7369 extern int VpdReadBlock(
7370 SK_AC *pAC,
7371 SK_IOC IoC,
7372@@ -233,9 +261,12 @@
7373 char *buf,
7374 int addr,
7375 int len);
7376-#endif /* SKDIAG */
7377+
7378+#endif /* SK_DIAG || SK_ASF */
7379+
7380 #else /* SK_KR_PROTO */
7381 extern SK_U32 VpdReadDWord();
7382+extern int VpdSetupPara();
7383 extern SK_VPD_STATUS *VpdStat();
7384 extern int VpdKeys();
7385 extern int VpdRead();
7386@@ -243,6 +274,8 @@
7387 extern int VpdWrite();
7388 extern int VpdDelete();
7389 extern int VpdUpdate();
7390+extern void VpdErrLog();
7391 #endif /* SK_KR_PROTO */
7392
7393 #endif /* __INC_SKVPD_H_ */
7394+
7395diff -urN linux-2.6.17.orig/drivers/net/sk98lin/h/sky2le.h linux-2.6.17/drivers/net/sk98lin/h/sky2le.h
7396--- linux-2.6.17.orig/drivers/net/sk98lin/h/sky2le.h 1970-01-01 01:00:00.000000000 +0100
7397+++ linux-2.6.17/drivers/net/sk98lin/h/sky2le.h 2006-04-27 11:43:44.000000000 +0200
7398@@ -0,0 +1,893 @@
7399+/******************************************************************************
7400+ *
7401+ * Name: sky2le.h
7402+ * Project: Gigabit Ethernet Adapters, Common Modules
7403+ * Version: $Revision$
7404+ * Date: $Date$
7405+ * Purpose: Common list element definitions and access macros.
7406+ *
7407+ ******************************************************************************/
7408+
7409+/******************************************************************************
7410+ *
7411+ * LICENSE:
7412+ * (C)Copyright 2003-2004 Marvell
7413+ *
7414+ * This program is free software; you can redistribute it and/or modify
7415+ * it under the terms of the GNU General Public License as published by
7416+ * the Free Software Foundation; either version 2 of the License, or
7417+ * (at your option) any later version.
7418+ * The information in this file is provided "AS IS" without warranty.
7419+ * /LICENSE
7420+ *
7421+ ******************************************************************************/
7422+
7423+#ifndef __INC_SKY2LE_H
7424+#define __INC_SKY2LE_H
7425+
7426+#ifdef __cplusplus
7427+extern "C" {
7428+#endif /* __cplusplus */
7429+
7430+/* defines ********************************************************************/
7431+
7432+#define MIN_LEN_OF_LE_TAB 128
7433+#define MAX_LEN_OF_LE_TAB 4096
7434+#ifdef USE_POLLING_UNIT
7435+#define NUM_LE_POLLING_UNIT 2
7436+#endif
7437+#define MAX_FRAG_OVERHEAD 10
7438+
7439+/* Macro for aligning a given value */
7440+#define SK_ALIGN_SIZE(Value, Alignment, AlignedVal) { \
7441+ (AlignedVal) = (((Value) + (Alignment) - 1) & (~((Alignment) - 1)));\
7442+}
7443+
7444+/******************************************************************************
7445+ *
7446+ * LE2DWord() - Converts the given Little Endian value to machine order value
7447+ *
7448+ * Description:
7449+ * This function converts the Little Endian value received as an argument to
7450+ * the machine order value.
7451+ *
7452+ * Returns:
7453+ * The converted value
7454+ *
7455+ */
7456+
7457+#ifdef SK_LITTLE_ENDIAN
7458+
7459+#ifndef SK_USE_REV_DESC
7460+#define LE2DWord(value) (value)
7461+#else /* SK_USE_REV_DESC */
7462+#define LE2DWord(value) \
7463+ ((((value)<<24L) & 0xff000000L) + \
7464+ (((value)<< 8L) & 0x00ff0000L) + \
7465+ (((value)>> 8L) & 0x0000ff00L) + \
7466+ (((value)>>24L) & 0x000000ffL))
7467+#endif /* SK_USE_REV_DESC */
7468+
7469+#else /* !SK_LITTLE_ENDIAN */
7470+
7471+#ifndef SK_USE_REV_DESC
7472+#define LE2DWord(value) \
7473+ ((((value)<<24L) & 0xff000000L) + \
7474+ (((value)<< 8L) & 0x00ff0000L) + \
7475+ (((value)>> 8L) & 0x0000ff00L) + \
7476+ (((value)>>24L) & 0x000000ffL))
7477+#else /* SK_USE_REV_DESC */
7478+#define LE2DWord(value) (value)
7479+#endif /* SK_USE_REV_DESC */
7480+
7481+#endif /* !SK_LITTLE_ENDIAN */
7482+
7483+/******************************************************************************
7484+ *
7485+ * DWord2LE() - Converts the given value to a Little Endian value
7486+ *
7487+ * Description:
7488+ * This function converts the value received as an argument to a Little Endian
7489+ * value on Big Endian machines. If the machine running the code is Little
7490+ * Endian, then no conversion is done.
7491+ *
7492+ * Returns:
7493+ * The converted value
7494+ *
7495+ */
7496+
7497+#ifdef SK_LITTLE_ENDIAN
7498+
7499+#ifndef SK_USE_REV_DESC
7500+#define DWord2LE(value) (value)
7501+#else /* SK_USE_REV_DESC */
7502+#define DWord2LE(value) \
7503+ ((((value)<<24L) & 0xff000000L) + \
7504+ (((value)<< 8L) & 0x00ff0000L) + \
7505+ (((value)>> 8L) & 0x0000ff00L) + \
7506+ (((value)>>24L) & 0x000000ffL))
7507+#endif /* SK_USE_REV_DESC */
7508+
7509+#else /* !SK_LITTLE_ENDIAN */
7510+
7511+#ifndef SK_USE_REV_DESC
7512+#define DWord2LE(value) \
7513+ ((((value)<<24L) & 0xff000000L) + \
7514+ (((value)<< 8L) & 0x00ff0000L) + \
7515+ (((value)>> 8L) & 0x0000ff00L) + \
7516+ (((value)>>24L) & 0x000000ffL))
7517+#else /* SK_USE_REV_DESC */
7518+#define DWord2LE(value) (value)
7519+#endif /* SK_USE_REV_DESC */
7520+#endif /* !SK_LITTLE_ENDIAN */
7521+
7522+/******************************************************************************
7523+ *
7524+ * LE2Word() - Converts the given Little Endian value to machine order value
7525+ *
7526+ * Description:
7527+ * This function converts the Little Endian value received as an argument to
7528+ * the machine order value.
7529+ *
7530+ * Returns:
7531+ * The converted value
7532+ *
7533+ */
7534+
7535+#ifdef SK_LITTLE_ENDIAN
7536+#ifndef SK_USE_REV_DESC
7537+#define LE2Word(value) (value)
7538+#else /* SK_USE_REV_DESC */
7539+#define LE2Word(value) \
7540+ ((((value)<< 8L) & 0xff00) + \
7541+ (((value)>> 8L) & 0x00ff))
7542+#endif /* SK_USE_REV_DESC */
7543+
7544+#else /* !SK_LITTLE_ENDIAN */
7545+#ifndef SK_USE_REV_DESC
7546+#define LE2Word(value) \
7547+ ((((value)<< 8L) & 0xff00) + \
7548+ (((value)>> 8L) & 0x00ff))
7549+#else /* SK_USE_REV_DESC */
7550+#define LE2Word(value) (value)
7551+#endif /* SK_USE_REV_DESC */
7552+#endif /* !SK_LITTLE_ENDIAN */
7553+
7554+/******************************************************************************
7555+ *
7556+ * Word2LE() - Converts the given value to a Little Endian value
7557+ *
7558+ * Description:
7559+ * This function converts the value received as an argument to a Little Endian
7560+ * value on Big Endian machines. If the machine running the code is Little
7561+ * Endian, then no conversion is done.
7562+ *
7563+ * Returns:
7564+ * The converted value
7565+ *
7566+ */
7567+
7568+#ifdef SK_LITTLE_ENDIAN
7569+#ifndef SK_USE_REV_DESC
7570+#define Word2LE(value) (value)
7571+#else /* SK_USE_REV_DESC */
7572+#define Word2LE(value) \
7573+ ((((value)<< 8L) & 0xff00) + \
7574+ (((value)>> 8L) & 0x00ff))
7575+#endif /* SK_USE_REV_DESC */
7576+
7577+#else /* !SK_LITTLE_ENDIAN */
7578+#ifndef SK_USE_REV_DESC
7579+#define Word2LE(value) \
7580+ ((((value)<< 8L) & 0xff00) + \
7581+ (((value)>> 8L) & 0x00ff))
7582+#else /* SK_USE_REV_DESC */
7583+#define Word2LE(value) (value)
7584+#endif /* SK_USE_REV_DESC */
7585+#endif /* !SK_LITTLE_ENDIAN */
7586+
7587+/******************************************************************************
7588+ *
7589+ * Transmit list element macros
7590+ *
7591+ */
7592+
7593+#define TXLE_SET_ADDR(pLE, Addr) \
7594+ ((pLE)->Tx.TxUn.BufAddr = DWord2LE(Addr))
7595+#define TXLE_SET_LSLEN(pLE, Len) \
7596+ ((pLE)->Tx.TxUn.LargeSend.Length = Word2LE(Len))
7597+#define TXLE_SET_STACS(pLE, Start) \
7598+ ((pLE)->Tx.TxUn.ChkSum.TxTcpSp = Word2LE(Start))
7599+#define TXLE_SET_WRICS(pLE, Write) \
7600+ ((pLE)->Tx.TxUn.ChkSum.TxTcpWp = Word2LE(Write))
7601+#define TXLE_SET_INICS(pLE, Ini) ((pLE)->Tx.Send.InitCsum = Word2LE(Ini))
7602+#define TXLE_SET_LEN(pLE, Len) ((pLE)->Tx.Send.BufLen = Word2LE(Len))
7603+#define TXLE_SET_VLAN(pLE, Vlan) ((pLE)->Tx.Send.VlanTag = Word2LE(Vlan))
7604+#define TXLE_SET_LCKCS(pLE, Lock) ((pLE)->Tx.ControlFlags = (Lock))
7605+#define TXLE_SET_CTRL(pLE, Ctrl) ((pLE)->Tx.ControlFlags = (Ctrl))
7606+#define TXLE_SET_OPC(pLE, Opc) ((pLE)->Tx.Opcode = (Opc))
7607+
7608+#define TXLE_GET_ADDR(pLE) LE2DWord((pLE)->Tx.TxUn.BufAddr)
7609+#define TXLE_GET_LSLEN(pLE) LE2Word((pLE)->Tx.TxUn.LargeSend.Length)
7610+#define TXLE_GET_STACS(pLE) LE2Word((pLE)->Tx.TxUn.ChkSum.TxTcpSp)
7611+#define TXLE_GET_WRICS(pLE) LE2Word((pLE)->Tx.TxUn.ChkSum.TxTcpWp)
7612+#define TXLE_GET_INICS(pLE) LE2Word((pLE)->Tx.Send.InitCsum)
7613+#define TXLE_GET_LEN(pLE) LE2Word((pLE)->Tx.Send.BufLen)
7614+#define TXLE_GET_VLAN(pLE) LE2Word((pLE)->Tx.Send.VlanTag)
7615+#define TXLE_GET_LCKCS(pLE) ((pLE)->Tx.ControlFlags)
7616+#define TXLE_GET_CTRL(pLE) ((pLE)->Tx.ControlFlags)
7617+#define TXLE_GET_OPC(pLE) ((pLE)->Tx.Opcode)
7618+
7619+/******************************************************************************
7620+ *
7621+ * Receive list element macros
7622+ *
7623+ */
7624+
7625+#define RXLE_SET_ADDR(pLE, Addr) \
7626+ ((pLE)->Rx.RxUn.BufAddr = (SK_U32) DWord2LE(Addr))
7627+#define RXLE_SET_STACS2(pLE, Offs) \
7628+ ((pLE)->Rx.RxUn.ChkSum.RxTcpSp2 = Word2LE(Offs))
7629+#define RXLE_SET_STACS1(pLE, Offs) \
7630+ ((pLE)->Rx.RxUn.ChkSum.RxTcpSp1 = Word2LE(Offs))
7631+#define RXLE_SET_LEN(pLE, Len) ((pLE)->Rx.BufferLength = Word2LE(Len))
7632+#define RXLE_SET_CTRL(pLE, Ctrl) ((pLE)->Rx.ControlFlags = (Ctrl))
7633+#define RXLE_SET_OPC(pLE, Opc) ((pLE)->Rx.Opcode = (Opc))
7634+
7635+#define RXLE_GET_ADDR(pLE) LE2DWord((pLE)->Rx.RxUn.BufAddr)
7636+#define RXLE_GET_STACS2(pLE) LE2Word((pLE)->Rx.RxUn.ChkSum.RxTcpSp2)
7637+#define RXLE_GET_STACS1(pLE) LE2Word((pLE)->Rx.RxUn.ChkSum.RxTcpSp1)
7638+#define RXLE_GET_LEN(pLE) LE2Word((pLE)->Rx.BufferLength)
7639+#define RXLE_GET_CTRL(pLE) ((pLE)->Rx.ControlFlags)
7640+#define RXLE_GET_OPC(pLE) ((pLE)->Rx.Opcode)
7641+
7642+/******************************************************************************
7643+ *
7644+ * Status list element macros
7645+ *
7646+ */
7647+
7648+#define STLE_SET_OPC(pLE, Opc) ((pLE)->St.Opcode = (Opc))
7649+
7650+#define STLE_GET_FRSTATUS(pLE) LE2DWord((pLE)->St.StUn.StRxStatWord)
7651+#define STLE_GET_TIST(pLE) LE2DWord((pLE)->St.StUn.StRxTimeStamp)
7652+#define STLE_GET_TCP1(pLE) LE2Word((pLE)->St.StUn.StRxTCPCSum.RxTCPSum1)
7653+#define STLE_GET_TCP2(pLE) LE2Word((pLE)->St.StUn.StRxTCPCSum.RxTCPSum2)
7654+#define STLE_GET_LEN(pLE) LE2Word((pLE)->St.Stat.BufLen)
7655+#define STLE_GET_VLAN(pLE) LE2Word((pLE)->St.Stat.VlanTag)
7656+#define STLE_GET_LINK(pLE) ((pLE)->St.Link)
7657+#define STLE_GET_OPC(pLE) ((pLE)->St.Opcode)
7658+#define STLE_GET_DONE_IDX(pLE,LowVal,HighVal) { \
7659+ (LowVal) = LE2DWord((pLE)->St.StUn.StTxStatLow); \
7660+ (HighVal) = LE2Word((pLE)->St.Stat.StTxStatHi); \
7661+}
7662+
7663+#define STLE_GET_RSS(pLE) LE2DWord((pLE)->St.StUn.StRxRssValue)
7664+#define STLE_GET_IPBIT(pLE) ((pLE)->St.Stat.Rss.FlagField & RSS_IP_FLAG)
7665+#define STLE_GET_TCPBIT(pLE) ((pLE)->St.Stat.Rss.FlagField & RSS_TCP_FLAG)
7666+
7667+
7668+/* I always take both values as a paramter to avoid typos */
7669+#define STLE_GET_DONE_IDX_TXA1(LowVal,HighVal) \
7670+ (((LowVal) & STLE_TXA1_MSKL) >> STLE_TXA1_SHIFTL)
7671+#define STLE_GET_DONE_IDX_TXS1(LowVal,HighVal) \
7672+ ((LowVal & STLE_TXS1_MSKL) >> STLE_TXS1_SHIFTL)
7673+#define STLE_GET_DONE_IDX_TXA2(LowVal,HighVal) \
7674+ (((LowVal & STLE_TXA2_MSKL) >> STLE_TXA2_SHIFTL) + \
7675+ ((HighVal & STLE_TXA2_MSKH) << STLE_TXA2_SHIFTH))
7676+#define STLE_GET_DONE_IDX_TXS2(LowVal,HighVal) \
7677+ ((HighVal & STLE_TXS2_MSKH) >> STLE_TXS2_SHIFTH)
7678+
7679+
7680+#define SK_Y2_RXSTAT_CHECK_PKT(Len, RxStat, IsOk) { \
7681+ (IsOk) = (((RxStat) & GMR_FS_RX_OK) != 0) && \
7682+ (((RxStat) & GMR_FS_ANY_ERR) == 0); \
7683+ \
7684+ if ((IsOk) && ((SK_U16)(((RxStat) & GMR_FS_LEN_MSK) >> \
7685+ GMR_FS_LEN_SHIFT) != (Len))) { \
7686+ /* length in MAC status differs from length in LE */\
7687+ (IsOk) = SK_FALSE; \
7688+ } \
7689+}
7690+
7691+
7692+/******************************************************************************
7693+ *
7694+ * Polling unit list element macros
7695+ *
7696+ * NOTE: the Idx must be <= 0xfff and PU_PUTIDX_VALID makes them valid
7697+ *
7698+ */
7699+
7700+#ifdef USE_POLLING_UNIT
7701+
7702+#define POLE_SET_OPC(pLE, Opc) ((pLE)->Sa.Opcode = (Opc))
7703+#define POLE_SET_LINK(pLE, Port) ((pLE)->Sa.Link = (Port))
7704+#define POLE_SET_RXIDX(pLE, Idx) ((pLE)->Sa.RxIdxVld = Word2LE(Idx))
7705+#define POLE_SET_TXAIDX(pLE, Idx) ((pLE)->Sa.TxAIdxVld = Word2LE(Idx))
7706+#define POLE_SET_TXSIDX(pLE, Idx) ((pLE)->Sa.TxSIdxVld = Word2LE(Idx))
7707+
7708+#define POLE_GET_OPC(pLE) ((pLE)->Sa.Opcode)
7709+#define POLE_GET_LINK(pLE) ((pLE)->Sa.Link)
7710+#define POLE_GET_RXIDX(pLE) LE2Word((pLE)->Sa.RxIdxVld)
7711+#define POLE_GET_TXAIDX(pLE) LE2Word((pLE)->Sa.TxAIdxVld)
7712+#define POLE_GET_TXSIDX(pLE) LE2Word((pLE)->Sa.TxSIdxVld)
7713+
7714+#endif /* USE_POLLING_UNIT */
7715+
7716+/******************************************************************************
7717+ *
7718+ * Debug macros for list elements
7719+ *
7720+ */
7721+
7722+#ifdef DEBUG
7723+
7724+#define SK_DBG_DUMP_RX_LE(pLE) { \
7725+ SK_U8 Opcode; \
7726+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7727+ ("=== RX_LIST_ELEMENT @addr: %p cont: %02x %02x %02x %02x %02x %02x %02x %02x\n", \
7728+ pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\
7729+ ((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5], \
7730+ ((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7])); \
7731+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7732+ ("\t (16bit) %04x %04x %04x %04x\n", \
7733+ ((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2], \
7734+ ((SK_U16 *) pLE)[3])); \
7735+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7736+ ("\t (32bit) %08x %08x\n", \
7737+ ((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1])); \
7738+ Opcode = RXLE_GET_OPC(pLE); \
7739+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7740+ ("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == HW_OWNER) ? \
7741+ "Hardware" : "Software")); \
7742+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7743+ ("\tOpc: 0x%x ",Opcode)); \
7744+ switch (Opcode & (~HW_OWNER)) { \
7745+ case OP_BUFFER: \
7746+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7747+ ("\tOP_BUFFER\n")); \
7748+ break; \
7749+ case OP_PACKET: \
7750+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7751+ ("\tOP_PACKET\n")); \
7752+ break; \
7753+ case OP_ADDR64: \
7754+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7755+ ("\tOP_ADDR64\n")); \
7756+ break; \
7757+ case OP_TCPSTART: \
7758+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7759+ ("\tOP_TCPPAR\n")); \
7760+ break; \
7761+ case SW_OWNER: \
7762+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7763+ ("\tunused LE\n")); \
7764+ break; \
7765+ default: \
7766+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7767+ ("\tunknown Opcode!!!\n")); \
7768+ break; \
7769+ } \
7770+ if ((Opcode & OP_BUFFER) == OP_BUFFER) { \
7771+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7772+ ("\tControl: 0x%x\n", RXLE_GET_CTRL(pLE))); \
7773+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7774+ ("\tBufLen: 0x%x\n", RXLE_GET_LEN(pLE))); \
7775+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7776+ ("\tLowAddr: 0x%x\n", RXLE_GET_ADDR(pLE))); \
7777+ } \
7778+ if ((Opcode & OP_ADDR64) == OP_ADDR64) { \
7779+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7780+ ("\tHighAddr: 0x%x\n", RXLE_GET_ADDR(pLE))); \
7781+ } \
7782+ if ((Opcode & OP_TCPSTART) == OP_TCPSTART) { \
7783+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7784+ ("\tTCP Sum Start 1 : 0x%x\n", RXLE_GET_STACS1(pLE))); \
7785+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7786+ ("\tTCP Sum Start 2 : 0x%x\n", RXLE_GET_STACS2(pLE))); \
7787+ } \
7788+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7789+ ("=====================\n")); \
7790+}
7791+
7792+#define SK_DBG_DUMP_TX_LE(pLE) { \
7793+ SK_U8 Opcode; \
7794+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7795+ ("=== TX_LIST_ELEMENT @addr: %p cont: %02x %02x %02x %02x %02x %02x %02x %02x\n", \
7796+ pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\
7797+ ((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5], \
7798+ ((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7])); \
7799+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7800+ ("\t (16bit) %04x %04x %04x %04x\n", \
7801+ ((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2], \
7802+ ((SK_U16 *) pLE)[3])); \
7803+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7804+ ("\t (32bit) %08x %08x\n", \
7805+ ((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1])); \
7806+ Opcode = TXLE_GET_OPC(pLE); \
7807+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7808+ ("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == HW_OWNER) ? \
7809+ "Hardware" : "Software")); \
7810+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7811+ ("\tOpc: 0x%x ",Opcode)); \
7812+ switch (Opcode & (~HW_OWNER)) { \
7813+ case OP_TCPCHKSUM: \
7814+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7815+ ("\tOP_TCPCHKSUM\n")); \
7816+ break; \
7817+ case OP_TCPIS: \
7818+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7819+ ("\tOP_TCPIS\n")); \
7820+ break; \
7821+ case OP_TCPLCK: \
7822+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7823+ ("\tOP_TCPLCK\n")); \
7824+ break; \
7825+ case OP_TCPLW: \
7826+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7827+ ("\tOP_TCPLW\n")); \
7828+ break; \
7829+ case OP_TCPLSW: \
7830+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7831+ ("\tOP_TCPLSW\n")); \
7832+ break; \
7833+ case OP_TCPLISW: \
7834+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7835+ ("\tOP_TCPLISW\n")); \
7836+ break; \
7837+ case OP_ADDR64: \
7838+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7839+ ("\tOP_ADDR64\n")); \
7840+ break; \
7841+ case OP_VLAN: \
7842+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7843+ ("\tOP_VLAN\n")); \
7844+ break; \
7845+ case OP_ADDR64VLAN: \
7846+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7847+ ("\tOP_ADDR64VLAN\n")); \
7848+ break; \
7849+ case OP_LRGLEN: \
7850+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7851+ ("\tOP_LRGLEN\n")); \
7852+ break; \
7853+ case OP_LRGLENVLAN: \
7854+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7855+ ("\tOP_LRGLENVLAN\n")); \
7856+ break; \
7857+ case OP_BUFFER: \
7858+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7859+ ("\tOP_BUFFER\n")); \
7860+ break; \
7861+ case OP_PACKET: \
7862+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7863+ ("\tOP_PACKET\n")); \
7864+ break; \
7865+ case OP_LARGESEND: \
7866+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7867+ ("\tOP_LARGESEND\n")); \
7868+ break; \
7869+ case SW_OWNER: \
7870+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7871+ ("\tunused LE\n")); \
7872+ break; \
7873+ default: \
7874+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7875+ ("\tunknown Opcode!!!\n")); \
7876+ break; \
7877+ } \
7878+ if ((Opcode & OP_BUFFER) == OP_BUFFER) { \
7879+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7880+ ("\tControl: 0x%x\n", TXLE_GET_CTRL(pLE))); \
7881+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7882+ ("\tBufLen: 0x%x\n", TXLE_GET_LEN(pLE))); \
7883+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7884+ ("\tLowAddr: 0x%x\n", TXLE_GET_ADDR(pLE))); \
7885+ } \
7886+ if ((Opcode & OP_ADDR64) == OP_ADDR64) { \
7887+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7888+ ("\tHighAddr: 0x%x\n", TXLE_GET_ADDR(pLE))); \
7889+ } \
7890+ if ((Opcode & OP_VLAN) == OP_VLAN) { \
7891+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7892+ ("\tVLAN Id: 0x%x\n", TXLE_GET_VLAN(pLE))); \
7893+ } \
7894+ if ((Opcode & OP_LRGLEN) == OP_LRGLEN) { \
7895+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7896+ ("\tLarge send length: 0x%x\n", TXLE_GET_LSLEN(pLE))); \
7897+ } \
7898+ if ((Opcode &(~HW_OWNER)) <= OP_ADDR64) { \
7899+ if ((Opcode & OP_TCPWRITE) == OP_TCPWRITE) { \
7900+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7901+ ("\tTCP Sum Write: 0x%x\n", TXLE_GET_WRICS(pLE))); \
7902+ } \
7903+ if ((Opcode & OP_TCPSTART) == OP_TCPSTART) { \
7904+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7905+ ("\tTCP Sum Start: 0x%x\n", TXLE_GET_STACS(pLE))); \
7906+ } \
7907+ if ((Opcode & OP_TCPINIT) == OP_TCPINIT) { \
7908+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7909+ ("\tTCP Sum Init: 0x%x\n", TXLE_GET_INICS(pLE))); \
7910+ } \
7911+ if ((Opcode & OP_TCPLCK) == OP_TCPLCK) { \
7912+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7913+ ("\tTCP Sum Lock: 0x%x\n", TXLE_GET_LCKCS(pLE))); \
7914+ } \
7915+ } \
7916+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7917+ ("=====================\n")); \
7918+}
7919+
7920+#define SK_DBG_DUMP_ST_LE(pLE) { \
7921+ SK_U8 Opcode; \
7922+ SK_U16 HighVal; \
7923+ SK_U32 LowVal; \
7924+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7925+ ("=== ST_LIST_ELEMENT @addr: %p contains: %02x %02x %02x %02x %02x %02x %02x %02x\n",\
7926+ pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\
7927+ ((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5], \
7928+ ((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7])); \
7929+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7930+ ("\t (16bit) %04x %04x %04x %04x\n", \
7931+ ((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2], \
7932+ ((SK_U16 *) pLE)[3])); \
7933+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7934+ ("\t (32bit) %08x %08x\n", \
7935+ ((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1])); \
7936+ Opcode = STLE_GET_OPC(pLE); \
7937+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7938+ ("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == SW_OWNER) ? \
7939+ "Hardware" : "Software")); \
7940+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7941+ ("\tOpc: 0x%x", Opcode)); \
7942+ Opcode &= (~HW_OWNER); \
7943+ switch (Opcode) { \
7944+ case OP_RXSTAT: \
7945+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7946+ ("\tOP_RXSTAT\n")); \
7947+ break; \
7948+ case OP_RXTIMESTAMP: \
7949+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7950+ ("\tOP_RXTIMESTAMP\n")); \
7951+ break; \
7952+ case OP_RXVLAN: \
7953+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7954+ ("\tOP_RXVLAN\n")); \
7955+ break; \
7956+ case OP_RXCHKS: \
7957+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7958+ ("\tOP_RXCHKS\n")); \
7959+ break; \
7960+ case OP_RXCHKSVLAN: \
7961+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7962+ ("\tOP_RXCHKSVLAN\n")); \
7963+ break; \
7964+ case OP_RXTIMEVLAN: \
7965+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7966+ ("\tOP_RXTIMEVLAN\n")); \
7967+ break; \
7968+ case OP_RSS_HASH: \
7969+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7970+ ("\tOP_RSS_HASH\n")); \
7971+ break; \
7972+ case OP_TXINDEXLE: \
7973+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7974+ ("\tOP_TXINDEXLE\n")); \
7975+ break; \
7976+ case HW_OWNER: \
7977+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7978+ ("\tunused LE\n")); \
7979+ break; \
7980+ default: \
7981+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7982+ ("\tunknown status list element!!!\n")); \
7983+ break; \
7984+ } \
7985+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7986+ ("\tPort: %c\n", 'A' + STLE_GET_LINK(pLE))); \
7987+ if (Opcode == OP_RXSTAT) { \
7988+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7989+ ("\tFrameLen: 0x%x\n", STLE_GET_LEN(pLE))); \
7990+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7991+ ("\tFrameStat: 0x%x\n", STLE_GET_FRSTATUS(pLE))); \
7992+ } \
7993+ if ((Opcode & OP_RXVLAN) == OP_RXVLAN) { \
7994+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7995+ ("\tVLAN Id: 0x%x\n", STLE_GET_VLAN(pLE))); \
7996+ } \
7997+ if ((Opcode & OP_RXTIMESTAMP) == OP_RXTIMESTAMP) { \
7998+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
7999+ ("\tTimestamp: 0x%x\n", STLE_GET_TIST(pLE))); \
8000+ } \
8001+ if ((Opcode & OP_RXCHKS) == OP_RXCHKS) { \
8002+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8003+ ("\tTCP: 0x%x 0x%x\n", STLE_GET_TCP1(pLE), \
8004+ STLE_GET_TCP2(pLE))); \
8005+ } \
8006+ if (Opcode == OP_TXINDEXLE) { \
8007+ STLE_GET_DONE_IDX(pLE, LowVal, HighVal); \
8008+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8009+ ("\tTx Index TxA1: 0x%x\n", \
8010+ STLE_GET_DONE_IDX_TXA1(LowVal,HighVal))); \
8011+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8012+ ("\tTx Index TxS1: 0x%x\n", \
8013+ STLE_GET_DONE_IDX_TXS1(LowVal,HighVal))); \
8014+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8015+ ("\tTx Index TxA2: 0x%x\n", \
8016+ STLE_GET_DONE_IDX_TXA2(LowVal,HighVal))); \
8017+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8018+ ("\tTx Index TxS2: 0x%x\n", \
8019+ STLE_GET_DONE_IDX_TXS2(LowVal,HighVal))); \
8020+ } \
8021+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8022+ ("=====================\n")); \
8023+}
8024+
8025+#ifdef USE_POLLING_UNIT
8026+#define SK_DBG_DUMP_PO_LE(pLE) { \
8027+ SK_U8 Opcode; \
8028+ SK_U16 Idx; \
8029+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8030+ ("=== PO_LIST_ELEMENT @addr: %p cont: %02x %02x %02x %02x %02x %02x %02x %02x\n", \
8031+ pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\
8032+ ((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5], \
8033+ ((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7])); \
8034+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8035+ ("\t (16bit) %04x %04x %04x %04x\n", \
8036+ ((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2], \
8037+ ((SK_U16 *) pLE)[3])); \
8038+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8039+ ("\t (32bit) %08x %08x\n", \
8040+ ((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1])); \
8041+ Opcode = POLE_GET_OPC(pLE); \
8042+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8043+ ("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == HW_OWNER) ? \
8044+ "Hardware" : "Software")); \
8045+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8046+ ("\tOpc: 0x%x ",Opcode)); \
8047+ if ((Opcode & ~HW_OWNER) == OP_PUTIDX) { \
8048+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8049+ ("\tOP_PUTIDX\n")); \
8050+ } \
8051+ else { \
8052+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8053+ ("\tunknown Opcode!!!\n")); \
8054+ } \
8055+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8056+ ("\tPort %c\n", 'A' + POLE_GET_LINK(pLE))); \
8057+ Idx = POLE_GET_TXAIDX(pLE); \
8058+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8059+ ("\tTxA Index is 0x%X and %svalid\n", Idx, \
8060+ (Idx & PU_PUTIDX_VALID) ? "" : "not ")); \
8061+ Idx = POLE_GET_TXSIDX(pLE); \
8062+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8063+ ("\tTxS Index is 0x%X and %svalid\n", Idx, \
8064+ (Idx & PU_PUTIDX_VALID) ? "" : "not ")); \
8065+ Idx = POLE_GET_RXIDX(pLE); \
8066+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8067+ ("\tRx Index is 0x%X and %svalid\n", Idx, \
8068+ (Idx & PU_PUTIDX_VALID) ? "" : "not ")); \
8069+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
8070+ ("=====================\n")); \
8071+}
8072+#endif /* USE_POLLING_UNIT */
8073+
8074+#else /* !DEBUG */
8075+
8076+#define SK_DBG_DUMP_RX_LE(pLE)
8077+#define SK_DBG_DUMP_TX_LE(pLE)
8078+#define SK_DBG_DUMP_ST_LE(pLE)
8079+#define SK_DBG_DUMP_PO_LE(pLE)
8080+
8081+#endif /* !DEBUG */
8082+
8083+/******************************************************************************
8084+ *
8085+ * Macros for listelement tables
8086+ *
8087+ *
8088+ */
8089+
8090+#define LE_SIZE sizeof(SK_HWLE)
8091+#define LE_TAB_SIZE(NumElements) ((NumElements) * LE_SIZE)
8092+
8093+/* Number of unused list elements in table
8094+ * this macro always returns the number of free listelements - 1
8095+ * this way we want to guarantee that always one LE remains unused
8096+ */
8097+#define NUM_FREE_LE_IN_TABLE(pTable) \
8098+ ( ((pTable)->Put >= (pTable)->Done) ? \
8099+ (NUM_LE_IN_TABLE(pTable) - (pTable)->Put + (pTable)->Done - 1) :\
8100+ ((pTable)->Done - (pTable)->Put - 1) )
8101+
8102+/* total number of list elements in table */
8103+#define NUM_LE_IN_TABLE(pTable) ((pTable)->Num)
8104+
8105+/* get next unused Rx list element */
8106+#define GET_RX_LE(pLE, pTable) { \
8107+ pLE = &(pTable)->pLETab[(pTable)->Put]; \
8108+ (pTable)->Put = ((pTable)->Put + 1) & (NUM_LE_IN_TABLE(pTable) - 1);\
8109+}
8110+
8111+/* get next unused Tx list element */
8112+#define GET_TX_LE(pLE, pTable) GET_RX_LE(pLE, pTable)
8113+
8114+/* get next status list element expected to be finished by hw */
8115+#define GET_ST_LE(pLE, pTable) { \
8116+ pLE = &(pTable)->pLETab[(pTable)->Done]; \
8117+ (pTable)->Done = ((pTable)->Done +1) & (NUM_LE_IN_TABLE(pTable) - 1);\
8118+}
8119+
8120+#ifdef USE_POLLING_UNIT
8121+/* get next polling unit list element for port */
8122+#define GET_PO_LE(pLE, pTable, Port) { \
8123+ pLE = &(pTable)->pLETab[(Port)]; \
8124+}
8125+#endif /* USE_POLLING_UNIT */
8126+
8127+#define GET_PUT_IDX(pTable) ((pTable)->Put)
8128+
8129+#define UPDATE_HWPUT_IDX(pTable) {(pTable)->HwPut = (pTable)->Put; }
8130+
8131+/*
8132+ * get own bit of next status LE
8133+ * if the result is != 0 there has been at least one status LE finished
8134+ */
8135+#define OWN_OF_FIRST_LE(pTable) \
8136+ (STLE_GET_OPC(&(pTable)->pLETab[(pTable)->Done]) & HW_OWNER)
8137+
8138+#define SET_DONE_INDEX(pTable, Idx) (pTable)->Done = (Idx);
8139+
8140+#define GET_DONE_INDEX(pTable) ((pTable)->Done)
8141+
8142+#ifdef SAFE_BUT_SLOW
8143+
8144+/* check own bit of LE before current done idx */
8145+#define CHECK_STLE_OVERFLOW(pTable, IsOk) { \
8146+ unsigned i; \
8147+ if ((i = (pTable)->Done) == 0) { \
8148+ i = NUM_LE_IN_TABLE(pTable); \
8149+ } \
8150+ else { \
8151+ i = i - 1; \
8152+ } \
8153+ if (STLE_GET_OPC(&(pTable)->pLETab[i]) == HW_OWNER) { \
8154+ (IsOk) = SK_TRUE; \
8155+ } \
8156+ else { \
8157+ (IsOk) = SK_FALSE; \
8158+ } \
8159+ }
8160+
8161+
8162+/*
8163+ * for Yukon-2 the hardware is not polling the list elements, so it
8164+ * is not necessary to change the own-bit of Rx or Tx LEs before
8165+ * reusing them
8166+ * but it might make debugging easier if one simply can see whether
8167+ * a LE has been worked on
8168+ */
8169+
8170+#define CLEAR_LE_OWN(pTable, Idx) \
8171+ STLE_SET_OPC(&(pTable)->pLETab[(Idx)], SW_OWNER)
8172+
8173+/*
8174+ * clear all own bits starting from old done index up to the LE before
8175+ * the new done index
8176+ */
8177+#define CLEAR_LE_OWN_FROM_DONE_TO(pTable, To) { \
8178+ int i; \
8179+ i = (pTable)->Done; \
8180+ while (i != To) { \
8181+ CLEAR_LE_OWN(pTable, i); \
8182+ i = (i + 1) & (NUM_LE_IN_TABLE(pTable) - 1); \
8183+ } \
8184+ }
8185+
8186+#else /* !SAFE_BUT_SLOW */
8187+
8188+#define CHECK_STLE_OVERFLOW(pTable, IsOk)
8189+#define CLEAR_LE_OWN(pTable, Idx)
8190+#define CLEAR_LE_OWN_FROM_DONE_TO(pTable, To)
8191+
8192+#endif /* !SAFE_BUT_SLOW */
8193+
8194+
8195+/* typedefs *******************************************************************/
8196+
8197+typedef struct s_LetRxTx {
8198+ SK_U16 VlanId; /* VLAN Id given down last time */
8199+ SK_U16 TcpWp; /* TCP Checksum Write Position */
8200+ SK_U16 TcpSp1; /* TCP Checksum Calculation Start Position 1 */
8201+ SK_U16 TcpSp2; /* TCP Checksum Calculation Start Position 2 */
8202+ SK_U16 MssValue; /* Maximum Segment Size */
8203+ SK_U16 Reserved1; /* reserved word for furture extensions */
8204+ SK_U16 Reserved2; /* reserved word for furture extensions */
8205+ SK_U16 Reserved3; /* reserved word for furture extensions */
8206+} SK_LET_RX_TX;
8207+
8208+typedef struct s_LetStat {
8209+ SK_U32 RxTimeStamp; /* Receive Timestamp */
8210+ SK_U32 RssHashValue; /* RSS Hash Value */
8211+ SK_BOOL RssIsIp; /* RSS Hash Value: IP packet detected */
8212+ SK_BOOL RssIsTcp; /* RSS Hash Value: IP+TCP packet detected */
8213+ SK_U16 VlanId; /* VLAN Id given received by Status BMU */
8214+ SK_U16 TcpSum1; /* TCP checksum 1 (status BMU) */
8215+ SK_U16 TcpSum2; /* TCP checksum 2 (status BMU) */
8216+} SK_LET_STAT;
8217+
8218+typedef union s_LetBmuSpec {
8219+ SK_LET_RX_TX RxTx; /* Rx/Tx BMU specific variables */
8220+ SK_LET_STAT Stat; /* Status BMU specific variables */
8221+} SK_LET_BMU_S;
8222+
8223+typedef struct s_le_table {
8224+ /* all LE's between Done and HWPut are owned by the hardware */
8225+ /* all LE's between Put and Done can be used from Software */
8226+ /* all LE's between HWPut and Put are currently processed in DriverSend */
8227+ unsigned Done; /* done index - consumed from HW and available */
8228+ unsigned Put; /* put index - to be given to hardware */
8229+ unsigned HwPut; /* put index actually given to hardware */
8230+ unsigned Num; /* total number of list elements */
8231+ SK_HWLE *pLETab; /* virtual address of list element table */
8232+ SK_U32 pPhyLETABLow; /* physical address of list element table */
8233+ SK_U32 pPhyLETABHigh; /* physical address of list element table */
8234+ /* values to remember in order to save some LEs */
8235+ SK_U32 BufHighAddr; /* high addr given down last time */
8236+ SK_LET_BMU_S Bmu; /* contains BMU specific information */
8237+ SK_U32 private; /* driver private variable free usable */
8238+ SK_U16 TcpInitCsum; /* Init. Checksum */
8239+} SK_LE_TABLE;
8240+
8241+/* function prototypes ********************************************************/
8242+
8243+#ifndef SK_KR_PROTO
8244+
8245+/*
8246+ * public functions in sky2le.c
8247+ */
8248+extern void SkGeY2SetPutIndex(
8249+ SK_AC *pAC,
8250+ SK_IOC IoC,
8251+ SK_U32 StartAddrPrefetchUnit,
8252+ SK_LE_TABLE *pLETab);
8253+
8254+extern void SkGeY2InitPrefetchUnit(
8255+ SK_AC *pAC,
8256+ SK_IOC IoC,
8257+ unsigned int Queue,
8258+ SK_LE_TABLE *pLETab);
8259+
8260+extern void SkGeY2InitStatBmu(
8261+ SK_AC *pAC,
8262+ SK_IOC IoC,
8263+ SK_LE_TABLE *pLETab);
8264+
8265+extern void SkGeY2InitPollUnit(
8266+ SK_AC *pAC,
8267+ SK_IOC IoC,
8268+ SK_LE_TABLE *pLETab);
8269+
8270+extern void SkGeY2InitSingleLETable(
8271+ SK_AC *pAC,
8272+ SK_LE_TABLE *pLETab,
8273+ unsigned int NumLE,
8274+ void *pVMem,
8275+ SK_U32 PMemLowAddr,
8276+ SK_U32 PMemHighAddr);
8277+
8278+#else /* SK_KR_PROTO */
8279+extern void SkGeY2SetPutIndex();
8280+extern void SkGeY2InitPrefetchUnit();
8281+extern void SkGeY2InitStatBmu();
8282+extern void SkGeY2InitPollUnit();
8283+extern void SkGeY2InitSingleLETable();
8284+#endif /* SK_KR_PROTO */
8285+
8286+#ifdef __cplusplus
8287+}
8288+#endif /* __cplusplus */
8289+
8290+#endif /* __INC_SKY2LE_H */
8291+
8292diff -urN linux-2.6.17.orig/drivers/net/sk98lin/h/xmac_ii.h linux-2.6.17/drivers/net/sk98lin/h/xmac_ii.h
8293--- linux-2.6.17.orig/drivers/net/sk98lin/h/xmac_ii.h 2006-06-22 13:17:16.000000000 +0200
8294+++ linux-2.6.17/drivers/net/sk98lin/h/xmac_ii.h 2006-04-27 11:43:44.000000000 +0200
8295@@ -2,23 +2,24 @@
8296 *
8297 * Name: xmac_ii.h
8298 * Project: Gigabit Ethernet Adapters, Common Modules
8299- * Version: $Revision$
8300- * Date: $Date$
8301+ * Version: $Revision$
8302+ * Date: $Date$
8303 * Purpose: Defines and Macros for Gigabit Ethernet Controller
8304 *
8305 ******************************************************************************/
8306
8307 /******************************************************************************
8308 *
8309+ * LICENSE:
8310 * (C)Copyright 1998-2002 SysKonnect.
8311- * (C)Copyright 2002-2003 Marvell.
8312+ * (C)Copyright 2002-2006 Marvell.
8313 *
8314 * This program is free software; you can redistribute it and/or modify
8315 * it under the terms of the GNU General Public License as published by
8316 * the Free Software Foundation; either version 2 of the License, or
8317 * (at your option) any later version.
8318- *
8319 * The information in this file is provided "AS IS" without warranty.
8320+ * /LICENSE
8321 *
8322 ******************************************************************************/
8323
8324@@ -371,18 +372,18 @@
8325 /* Bit 16..6: reserved */
8326 #define XM_SC_SNP_RXC (1<<5) /* Bit 5: (sc) Snap Rx Counters */
8327 #define XM_SC_SNP_TXC (1<<4) /* Bit 4: (sc) Snap Tx Counters */
8328-#define XM_SC_CP_RXC (1<<3) /* Bit 3: Copy Rx Counters Continuously */
8329+#define XM_SC_CP_RXC (1<<3) /* Bit 3: Copy Rx Counters Continuously */
8330 #define XM_SC_CP_TXC (1<<2) /* Bit 2: Copy Tx Counters Continuously */
8331 #define XM_SC_CLR_RXC (1<<1) /* Bit 1: (sc) Clear Rx Counters */
8332-#define XM_SC_CLR_TXC (1<<0) /* Bit 0: (sc) Clear Tx Counters */
8333+#define XM_SC_CLR_TXC (1<<0) /* Bit 0: (sc) Clear Tx Counters */
8334
8335
8336 /* XM_RX_CNT_EV 32 bit r/o Rx Counter Event Register */
8337 /* XM_RX_EV_MSK 32 bit r/w Rx Counter Event Mask */
8338-#define XMR_MAX_SZ_OV (1UL<<31) /* Bit 31: 1024-MaxSize Rx Cnt Ov*/
8339-#define XMR_1023B_OV (1L<<30) /* Bit 30: 512-1023Byte Rx Cnt Ov*/
8340-#define XMR_511B_OV (1L<<29) /* Bit 29: 256-511 Byte Rx Cnt Ov*/
8341-#define XMR_255B_OV (1L<<28) /* Bit 28: 128-255 Byte Rx Cnt Ov*/
8342+#define XMR_MAX_SZ_OV (1UL<<31) /* Bit 31: 1024-MaxSize Rx Cnt Ov */
8343+#define XMR_1023B_OV (1L<<30) /* Bit 30: 512-1023Byte Rx Cnt Ov */
8344+#define XMR_511B_OV (1L<<29) /* Bit 29: 256-511 Byte Rx Cnt Ov */
8345+#define XMR_255B_OV (1L<<28) /* Bit 28: 128-255 Byte Rx Cnt Ov */
8346 #define XMR_127B_OV (1L<<27) /* Bit 27: 65-127 Byte Rx Cnt Ov */
8347 #define XMR_64B_OV (1L<<26) /* Bit 26: 64 Byte Rx Cnt Ov */
8348 #define XMR_UTIL_OV (1L<<25) /* Bit 25: Rx Util Cnt Overflow */
8349@@ -390,9 +391,9 @@
8350 #define XMR_CEX_ERR_OV (1L<<23) /* Bit 23: CEXT Err Cnt Ov */
8351 /* Bit 22: reserved */
8352 #define XMR_FCS_ERR_OV (1L<<21) /* Bit 21: Rx FCS Error Cnt Ov */
8353-#define XMR_LNG_ERR_OV (1L<<20) /* Bit 20: Rx too Long Err Cnt Ov*/
8354+#define XMR_LNG_ERR_OV (1L<<20) /* Bit 20: Rx too Long Err Cnt Ov */
8355 #define XMR_RUNT_OV (1L<<19) /* Bit 19: Runt Event Cnt Ov */
8356-#define XMR_SHT_ERR_OV (1L<<18) /* Bit 18: Rx Short Ev Err Cnt Ov*/
8357+#define XMR_SHT_ERR_OV (1L<<18) /* Bit 18: Rx Short Ev Err Cnt Ov */
8358 #define XMR_SYM_ERR_OV (1L<<17) /* Bit 17: Rx Sym Err Cnt Ov */
8359 /* Bit 16: reserved */
8360 #define XMR_CAR_ERR_OV (1L<<15) /* Bit 15: Rx Carr Ev Err Cnt Ov */
8361@@ -401,57 +402,57 @@
8362 #define XMR_FRA_ERR_OV (1L<<12) /* Bit 12: Rx Framing Err Cnt Ov */
8363 #define XMR_FMISS_OV (1L<<11) /* Bit 11: Rx Missed Ev Cnt Ov */
8364 #define XMR_BURST (1L<<10) /* Bit 10: Rx Burst Event Cnt Ov */
8365-#define XMR_INV_MOC (1L<<9) /* Bit 9: Rx with inv. MAC OC Ov*/
8366+#define XMR_INV_MOC (1L<<9) /* Bit 9: Rx with inv. MAC OC Ov */
8367 #define XMR_INV_MP (1L<<8) /* Bit 8: Rx inv Pause Frame Ov */
8368 #define XMR_MCTRL_OV (1L<<7) /* Bit 7: Rx MAC Ctrl-F Cnt Ov */
8369-#define XMR_MPAUSE_OV (1L<<6) /* Bit 6: Rx Pause MAC Ctrl-F Ov*/
8370-#define XMR_UC_OK_OV (1L<<5) /* Bit 5: Rx Unicast Frame CntOv*/
8371+#define XMR_MPAUSE_OV (1L<<6) /* Bit 6: Rx Pause MAC Ctrl-F Ov */
8372+#define XMR_UC_OK_OV (1L<<5) /* Bit 5: Rx Unicast Frame Cnt Ov */
8373 #define XMR_MC_OK_OV (1L<<4) /* Bit 4: Rx Multicast Cnt Ov */
8374 #define XMR_BC_OK_OV (1L<<3) /* Bit 3: Rx Broadcast Cnt Ov */
8375-#define XMR_OK_LO_OV (1L<<2) /* Bit 2: Octets Rx OK Low CntOv*/
8376-#define XMR_OK_HI_OV (1L<<1) /* Bit 1: Octets Rx OK Hi Cnt Ov*/
8377-#define XMR_OK_OV (1L<<0) /* Bit 0: Frames Received Ok Ov */
8378+#define XMR_OK_LO_OV (1L<<2) /* Bit 2: Octets Rx OK Low Cnt Ov */
8379+#define XMR_OK_HI_OV (1L<<1) /* Bit 1: Octets Rx OK High Cnt Ov */
8380+#define XMR_OK_OV (1L<<0) /* Bit 0: Frames Received OK Ov */
8381
8382 #define XMR_DEF_MSK (XMR_OK_LO_OV | XMR_OK_HI_OV)
8383
8384 /* XM_TX_CNT_EV 32 bit r/o Tx Counter Event Register */
8385 /* XM_TX_EV_MSK 32 bit r/w Tx Counter Event Mask */
8386 /* Bit 31..26: reserved */
8387-#define XMT_MAX_SZ_OV (1L<<25) /* Bit 25: 1024-MaxSize Tx Cnt Ov*/
8388-#define XMT_1023B_OV (1L<<24) /* Bit 24: 512-1023Byte Tx Cnt Ov*/
8389-#define XMT_511B_OV (1L<<23) /* Bit 23: 256-511 Byte Tx Cnt Ov*/
8390-#define XMT_255B_OV (1L<<22) /* Bit 22: 128-255 Byte Tx Cnt Ov*/
8391+#define XMT_MAX_SZ_OV (1L<<25) /* Bit 25: 1024-MaxSize Tx Cnt Ov */
8392+#define XMT_1023B_OV (1L<<24) /* Bit 24: 512-1023Byte Tx Cnt Ov */
8393+#define XMT_511B_OV (1L<<23) /* Bit 23: 256-511 Byte Tx Cnt Ov */
8394+#define XMT_255B_OV (1L<<22) /* Bit 22: 128-255 Byte Tx Cnt Ov */
8395 #define XMT_127B_OV (1L<<21) /* Bit 21: 65-127 Byte Tx Cnt Ov */
8396 #define XMT_64B_OV (1L<<20) /* Bit 20: 64 Byte Tx Cnt Ov */
8397 #define XMT_UTIL_OV (1L<<19) /* Bit 19: Tx Util Cnt Overflow */
8398 #define XMT_UTIL_UR (1L<<18) /* Bit 18: Tx Util Cnt Underrun */
8399-#define XMT_CS_ERR_OV (1L<<17) /* Bit 17: Tx Carr Sen Err Cnt Ov*/
8400+#define XMT_CS_ERR_OV (1L<<17) /* Bit 17: Tx Carr Sen Err Cnt Ov */
8401 #define XMT_FIFO_UR_OV (1L<<16) /* Bit 16: Tx FIFO Ur Ev Cnt Ov */
8402 #define XMT_EX_DEF_OV (1L<<15) /* Bit 15: Tx Ex Deferall Cnt Ov */
8403 #define XMT_DEF (1L<<14) /* Bit 14: Tx Deferred Cnt Ov */
8404 #define XMT_LAT_COL_OV (1L<<13) /* Bit 13: Tx Late Col Cnt Ov */
8405-#define XMT_ABO_COL_OV (1L<<12) /* Bit 12: Tx abo dueto Ex Col Ov*/
8406+#define XMT_ABO_COL_OV (1L<<12) /* Bit 12: Tx abo dueto Ex Col Ov */
8407 #define XMT_MUL_COL_OV (1L<<11) /* Bit 11: Tx Mult Col Cnt Ov */
8408 #define XMT_SNG_COL (1L<<10) /* Bit 10: Tx Single Col Cnt Ov */
8409-#define XMT_MCTRL_OV (1L<<9) /* Bit 9: Tx MAC Ctrl Counter Ov*/
8410-#define XMT_MPAUSE (1L<<8) /* Bit 8: Tx Pause MAC Ctrl-F Ov*/
8411+#define XMT_MCTRL_OV (1L<<9) /* Bit 9: Tx MAC Ctrl Counter Ov */
8412+#define XMT_MPAUSE (1L<<8) /* Bit 8: Tx Pause MAC Ctrl-F Ov */
8413 #define XMT_BURST (1L<<7) /* Bit 7: Tx Burst Event Cnt Ov */
8414 #define XMT_LONG (1L<<6) /* Bit 6: Tx Long Frame Cnt Ov */
8415 #define XMT_UC_OK_OV (1L<<5) /* Bit 5: Tx Unicast Cnt Ov */
8416 #define XMT_MC_OK_OV (1L<<4) /* Bit 4: Tx Multicast Cnt Ov */
8417 #define XMT_BC_OK_OV (1L<<3) /* Bit 3: Tx Broadcast Cnt Ov */
8418-#define XMT_OK_LO_OV (1L<<2) /* Bit 2: Octets Tx OK Low CntOv*/
8419-#define XMT_OK_HI_OV (1L<<1) /* Bit 1: Octets Tx OK Hi Cnt Ov*/
8420-#define XMT_OK_OV (1L<<0) /* Bit 0: Frames Tx Ok Ov */
8421+#define XMT_OK_LO_OV (1L<<2) /* Bit 2: Octets Tx OK Low Cnt Ov */
8422+#define XMT_OK_HI_OV (1L<<1) /* Bit 1: Octets Tx OK High Cnt Ov */
8423+#define XMT_OK_OV (1L<<0) /* Bit 0: Frames Tx OK Ov */
8424
8425 #define XMT_DEF_MSK (XMT_OK_LO_OV | XMT_OK_HI_OV)
8426
8427 /*
8428 * Receive Frame Status Encoding
8429 */
8430-#define XMR_FS_LEN (0x3fffUL<<18) /* Bit 31..18: Rx Frame Length */
8431-#define XMR_FS_2L_VLAN (1L<<17) /* Bit 17: tagged wh 2Lev VLAN ID*/
8432-#define XMR_FS_1L_VLAN (1L<<16) /* Bit 16: tagged wh 1Lev VLAN ID*/
8433+#define XMR_FS_LEN_MSK (0x3fffUL<<18) /* Bit 31..18: Rx Frame Length */
8434+#define XMR_FS_2L_VLAN (1L<<17) /* Bit 17: Tagged wh 2Lev VLAN ID */
8435+#define XMR_FS_1L_VLAN (1L<<16) /* Bit 16: Tagged wh 1Lev VLAN ID */
8436 #define XMR_FS_BC (1L<<15) /* Bit 15: Broadcast Frame */
8437 #define XMR_FS_MC (1L<<14) /* Bit 14: Multicast Frame */
8438 #define XMR_FS_UC (1L<<13) /* Bit 13: Unicast Frame */
8439@@ -469,6 +470,8 @@
8440 #define XMR_FS_ERR (1L<<1) /* Bit 1: Frame Error */
8441 #define XMR_FS_MCTRL (1L<<0) /* Bit 0: MAC Control Packet */
8442
8443+#define XMR_FS_LEN_SHIFT 18
8444+
8445 /*
8446 * XMR_FS_ERR will be set if
8447 * XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT,
8448@@ -488,7 +491,7 @@
8449 #define PHY_XMAC_ID0 0x02 /* 16 bit r/o PHY ID0 Register */
8450 #define PHY_XMAC_ID1 0x03 /* 16 bit r/o PHY ID1 Register */
8451 #define PHY_XMAC_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */
8452-#define PHY_XMAC_AUNE_LP 0x05 /* 16 bit r/o Link Partner Abi Reg */
8453+#define PHY_XMAC_AUNE_LP 0x05 /* 16 bit r/o Link Partner Ability Reg */
8454 #define PHY_XMAC_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */
8455 #define PHY_XMAC_NEPG 0x07 /* 16 bit r/w Next Page Register */
8456 #define PHY_XMAC_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */
8457@@ -505,12 +508,12 @@
8458 #define PHY_BCOM_ID0 0x02 /* 16 bit r/o PHY ID0 Register */
8459 #define PHY_BCOM_ID1 0x03 /* 16 bit r/o PHY ID1 Register */
8460 #define PHY_BCOM_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */
8461-#define PHY_BCOM_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */
8462+#define PHY_BCOM_AUNE_LP 0x05 /* 16 bit r/o Link Partner Ability Reg */
8463 #define PHY_BCOM_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */
8464 #define PHY_BCOM_NEPG 0x07 /* 16 bit r/w Next Page Register */
8465 #define PHY_BCOM_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */
8466 /* Broadcom-specific registers */
8467-#define PHY_BCOM_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Ctrl Reg */
8468+#define PHY_BCOM_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */
8469 #define PHY_BCOM_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */
8470 /* 0x0b - 0x0e: reserved */
8471 #define PHY_BCOM_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */
8472@@ -536,29 +539,37 @@
8473 #define PHY_MARV_ID0 0x02 /* 16 bit r/o PHY ID0 Register */
8474 #define PHY_MARV_ID1 0x03 /* 16 bit r/o PHY ID1 Register */
8475 #define PHY_MARV_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */
8476-#define PHY_MARV_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */
8477+#define PHY_MARV_AUNE_LP 0x05 /* 16 bit r/o Link Partner Ability Reg */
8478 #define PHY_MARV_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */
8479 #define PHY_MARV_NEPG 0x07 /* 16 bit r/w Next Page Register */
8480 #define PHY_MARV_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */
8481 /* Marvel-specific registers */
8482-#define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Ctrl Reg */
8483+#define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */
8484 #define PHY_MARV_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */
8485 /* 0x0b - 0x0e: reserved */
8486 #define PHY_MARV_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */
8487-#define PHY_MARV_PHY_CTRL 0x10 /* 16 bit r/w PHY Specific Ctrl Reg */
8488-#define PHY_MARV_PHY_STAT 0x11 /* 16 bit r/o PHY Specific Stat Reg */
8489+#define PHY_MARV_PHY_CTRL 0x10 /* 16 bit r/w PHY Specific Control Reg */
8490+#define PHY_MARV_PHY_STAT 0x11 /* 16 bit r/o PHY Specific Status Reg */
8491 #define PHY_MARV_INT_MASK 0x12 /* 16 bit r/w Interrupt Mask Reg */
8492 #define PHY_MARV_INT_STAT 0x13 /* 16 bit r/o Interrupt Status Reg */
8493 #define PHY_MARV_EXT_CTRL 0x14 /* 16 bit r/w Ext. PHY Specific Ctrl */
8494 #define PHY_MARV_RXE_CNT 0x15 /* 16 bit r/w Receive Error Counter */
8495 #define PHY_MARV_EXT_ADR 0x16 /* 16 bit r/w Ext. Ad. for Cable Diag. */
8496- /* 0x17: reserved */
8497+#define PHY_MARV_PORT_IRQ 0x17 /* 16 bit r/o Port 0 IRQ (88E1111 only) */
8498 #define PHY_MARV_LED_CTRL 0x18 /* 16 bit r/w LED Control Reg */
8499 #define PHY_MARV_LED_OVER 0x19 /* 16 bit r/w Manual LED Override Reg */
8500 #define PHY_MARV_EXT_CTRL_2 0x1a /* 16 bit r/w Ext. PHY Specific Ctrl 2 */
8501 #define PHY_MARV_EXT_P_STAT 0x1b /* 16 bit r/w Ext. PHY Spec. Stat Reg */
8502 #define PHY_MARV_CABLE_DIAG 0x1c /* 16 bit r/o Cable Diagnostic Reg */
8503- /* 0x1d - 0x1f: reserved */
8504+#define PHY_MARV_PAGE_ADDR 0x1d /* 16 bit r/w Extended Page Address Reg */
8505+#define PHY_MARV_PAGE_DATA 0x1e /* 16 bit r/w Extended Page Data Reg */
8506+
8507+/* for 10/100 Fast Ethernet PHY (88E3082 only) */
8508+#define PHY_MARV_FE_LED_PAR 0x16 /* 16 bit r/w LED Parallel Select Reg. */
8509+#define PHY_MARV_FE_LED_SER 0x17 /* 16 bit r/w LED Stream Select S. LED */
8510+#define PHY_MARV_FE_VCT_TX 0x1a /* 16 bit r/w VCT Reg. for TXP/N Pins */
8511+#define PHY_MARV_FE_VCT_RX 0x1b /* 16 bit r/o VCT Reg. for RXP/N Pins */
8512+#define PHY_MARV_FE_SPEC_2 0x1c /* 16 bit r/w Specific Control Reg. 2 */
8513
8514 /*----------------------------------------------------------------------------*/
8515 /*
8516@@ -569,14 +580,14 @@
8517 #define PHY_LONE_ID0 0x02 /* 16 bit r/o PHY ID0 Register */
8518 #define PHY_LONE_ID1 0x03 /* 16 bit r/o PHY ID1 Register */
8519 #define PHY_LONE_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */
8520-#define PHY_LONE_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */
8521+#define PHY_LONE_AUNE_LP 0x05 /* 16 bit r/o Link Partner Ability Reg */
8522 #define PHY_LONE_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */
8523 #define PHY_LONE_NEPG 0x07 /* 16 bit r/w Next Page Register */
8524 #define PHY_LONE_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */
8525 /* Level One-specific registers */
8526-#define PHY_LONE_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg*/
8527+#define PHY_LONE_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */
8528 #define PHY_LONE_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */
8529- /* 0x0b -0x0e: reserved */
8530+ /* 0x0b - 0x0e: reserved */
8531 #define PHY_LONE_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */
8532 #define PHY_LONE_PORT_CFG 0x10 /* 16 bit r/w Port Configuration Reg*/
8533 #define PHY_LONE_Q_STAT 0x11 /* 16 bit r/o Quick Status Reg */
8534@@ -585,7 +596,7 @@
8535 #define PHY_LONE_LED_CFG 0x14 /* 16 bit r/w LED Configuration Reg */
8536 #define PHY_LONE_PORT_CTRL 0x15 /* 16 bit r/w Port Control Reg */
8537 #define PHY_LONE_CIM 0x16 /* 16 bit r/o CIM Reg */
8538- /* 0x17 -0x1c: reserved */
8539+ /* 0x17 - 0x1c: reserved */
8540
8541 /*----------------------------------------------------------------------------*/
8542 /*
8543@@ -603,14 +614,14 @@
8544 /* National-specific registers */
8545 #define PHY_NAT_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */
8546 #define PHY_NAT_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */
8547- /* 0x0b -0x0e: reserved */
8548+ /* 0x0b - 0x0e: reserved */
8549 #define PHY_NAT_EXT_STAT 0x0f /* 16 bit r/o Extended Status Register */
8550 #define PHY_NAT_EXT_CTRL1 0x10 /* 16 bit r/o Extended Control Reg1 */
8551 #define PHY_NAT_Q_STAT1 0x11 /* 16 bit r/o Quick Status Reg1 */
8552 #define PHY_NAT_10B_OP 0x12 /* 16 bit r/o 10Base-T Operations Reg */
8553 #define PHY_NAT_EXT_CTRL2 0x13 /* 16 bit r/o Extended Control Reg1 */
8554 #define PHY_NAT_Q_STAT2 0x14 /* 16 bit r/o Quick Status Reg2 */
8555- /* 0x15 -0x18: reserved */
8556+ /* 0x15 - 0x18: reserved */
8557 #define PHY_NAT_PHY_ADDR 0x19 /* 16 bit r/o PHY Address Register */
8558
8559
8560@@ -618,7 +629,7 @@
8561
8562 /*
8563 * PHY bit definitions
8564- * Bits defined as PHY_X_..., PHY_B_..., PHY_L_... or PHY_N_... are
8565+ * Bits defined as PHY_X_..., PHY_B_..., PHY_L_..., PHY_N_... or PHY_M_... are
8566 * XMAC/Broadcom/LevelOne/National/Marvell-specific.
8567 * All other are general.
8568 */
8569@@ -629,14 +640,14 @@
8570 /***** PHY_LONE_CTRL 16 bit r/w PHY Control Register *****/
8571 #define PHY_CT_RESET (1<<15) /* Bit 15: (sc) clear all PHY related regs */
8572 #define PHY_CT_LOOP (1<<14) /* Bit 14: enable Loopback over PHY */
8573-#define PHY_CT_SPS_LSB (1<<13) /* Bit 13: (BC,L1) Speed select, lower bit */
8574+#define PHY_CT_SPS_LSB (1<<13) /* Bit 13: Speed select, lower bit */
8575 #define PHY_CT_ANE (1<<12) /* Bit 12: Auto-Negotiation Enabled */
8576-#define PHY_CT_PDOWN (1<<11) /* Bit 11: (BC,L1) Power Down Mode */
8577-#define PHY_CT_ISOL (1<<10) /* Bit 10: (BC,L1) Isolate Mode */
8578-#define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Auto-Negotiation */
8579+#define PHY_CT_PDOWN (1<<11) /* Bit 11: Power Down Mode */
8580+#define PHY_CT_ISOL (1<<10) /* Bit 10: Isolate Mode */
8581+#define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Auto-Negotiation */
8582 #define PHY_CT_DUP_MD (1<<8) /* Bit 8: Duplex Mode */
8583-#define PHY_CT_COL_TST (1<<7) /* Bit 7: (BC,L1) Collision Test enabled */
8584-#define PHY_CT_SPS_MSB (1<<6) /* Bit 6: (BC,L1) Speed select, upper bit */
8585+#define PHY_CT_COL_TST (1<<7) /* Bit 7: Collision Test enabled */
8586+#define PHY_CT_SPS_MSB (1<<6) /* Bit 6: Speed select, upper bit */
8587 /* Bit 5..0: reserved */
8588
8589 #define PHY_CT_SP1000 PHY_CT_SPS_MSB /* enable speed of 1000 Mbps */
8590@@ -649,25 +660,25 @@
8591 /***** PHY_MARV_STAT 16 bit r/w PHY Status Register *****/
8592 /***** PHY_LONE_STAT 16 bit r/w PHY Status Register *****/
8593 /* Bit 15..9: reserved */
8594- /* (BC/L1) 100/10 Mbps cap bits ignored*/
8595+ /* (BC/L1) 100/10 Mbps cap bits ignored */
8596 #define PHY_ST_EXT_ST (1<<8) /* Bit 8: Extended Status Present */
8597 /* Bit 7: reserved */
8598-#define PHY_ST_PRE_SUP (1<<6) /* Bit 6: (BC/L1) preamble suppression */
8599+#define PHY_ST_PRE_SUP (1<<6) /* Bit 6: Preamble Suppression */
8600 #define PHY_ST_AN_OVER (1<<5) /* Bit 5: Auto-Negotiation Over */
8601 #define PHY_ST_REM_FLT (1<<4) /* Bit 4: Remote Fault Condition Occured */
8602 #define PHY_ST_AN_CAP (1<<3) /* Bit 3: Auto-Negotiation Capability */
8603 #define PHY_ST_LSYNC (1<<2) /* Bit 2: Link Synchronized */
8604-#define PHY_ST_JAB_DET (1<<1) /* Bit 1: (BC/L1) Jabber Detected */
8605+#define PHY_ST_JAB_DET (1<<1) /* Bit 1: Jabber Detected */
8606 #define PHY_ST_EXT_REG (1<<0) /* Bit 0: Extended Register available */
8607
8608
8609-/***** PHY_XMAC_ID1 16 bit r/o PHY ID1 Register */
8610-/***** PHY_BCOM_ID1 16 bit r/o PHY ID1 Register */
8611-/***** PHY_MARV_ID1 16 bit r/o PHY ID1 Register */
8612-/***** PHY_LONE_ID1 16 bit r/o PHY ID1 Register */
8613+/***** PHY_XMAC_ID1 16 bit r/o PHY ID1 Register */
8614+/***** PHY_BCOM_ID1 16 bit r/o PHY ID1 Register */
8615+/***** PHY_MARV_ID1 16 bit r/o PHY ID1 Register */
8616+/***** PHY_LONE_ID1 16 bit r/o PHY ID1 Register */
8617 #define PHY_I1_OUI_MSK (0x3f<<10) /* Bit 15..10: Organization Unique ID */
8618 #define PHY_I1_MOD_NUM (0x3f<<4) /* Bit 9.. 4: Model Number */
8619-#define PHY_I1_REV_MSK 0x0f /* Bit 3.. 0: Revision Number */
8620+#define PHY_I1_REV_MSK 0xf /* Bit 3.. 0: Revision Number */
8621
8622 /* different Broadcom PHY Ids */
8623 #define PHY_BCOM_ID1_A1 0x6041
8624@@ -675,11 +686,21 @@
8625 #define PHY_BCOM_ID1_C0 0x6044
8626 #define PHY_BCOM_ID1_C5 0x6047
8627
8628+/* different Marvell PHY Ids */
8629+#define PHY_MARV_ID0_VAL 0x0141 /* Marvell Unique Identifier */
8630+
8631+#define PHY_MARV_ID1_B0 0x0C23 /* Yukon (PHY 88E1040 Rev.C0) */
8632+#define PHY_MARV_ID1_B2 0x0C25 /* Yukon-Plus (PHY 88E1040 Rev.D0) */
8633+#define PHY_MARV_ID1_C2 0x0CC2 /* Yukon-EC (PHY 88E1111 Rev.B1) */
8634+#define PHY_MARV_ID1_Y2 0x0C91 /* Yukon-XL (PHY 88E1112 Rev.B0) */
8635+#define PHY_MARV_ID1_FE 0x0C83 /* Yukon-FE (PHY 88E3082 Rev.A1) */
8636+#define PHY_MARV_ID1_ECU 0x0CB0 /* Yukon-ECU (PHY 88E1149 Rev.B2?) */
8637+
8638
8639 /***** PHY_XMAC_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
8640 /***** PHY_XMAC_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/
8641 #define PHY_AN_NXT_PG (1<<15) /* Bit 15: Request Next Page */
8642-#define PHY_X_AN_ACK (1<<14) /* Bit 14: (ro) Acknowledge Received */
8643+#define PHY_X_AN_ACK (1<<14) /* Bit 14: (ro) Acknowledge Received */
8644 #define PHY_X_AN_RFB (3<<12) /* Bit 13..12: Remote Fault Bits */
8645 /* Bit 11.. 9: reserved */
8646 #define PHY_X_AN_PAUSE (3<<7) /* Bit 8.. 7: Pause Bits */
8647@@ -738,7 +759,7 @@
8648 /* PHY_ANE_LP_NP (see XMAC) Bit 3: Link Partner can Next Page */
8649 /* PHY_ANE_LOC_NP (see XMAC) Bit 2: Local PHY can Next Page */
8650 /* PHY_ANE_RX_PG (see XMAC) Bit 1: Page Received */
8651-#define PHY_ANE_LP_CAP (1<<0) /* Bit 0: Link Partner Auto-Neg. Cap. */
8652+#define PHY_ANE_LP_CAP (1<<0) /* Bit 0: Link Partner Auto-Neg. Able */
8653
8654 /***** PHY_XMAC_NEPG 16 bit r/w Next Page Register *****/
8655 /***** PHY_BCOM_NEPG 16 bit r/w Next Page Register *****/
8656@@ -827,7 +848,7 @@
8657 #define PHY_B_PEC_BY_MLT3 (1<<8) /* Bit 8: Bypass MLT3 Encoder */
8658 #define PHY_B_PEC_BY_RXA (1<<7) /* Bit 7: Bypass Rx Alignm. */
8659 #define PHY_B_PEC_RES_SCR (1<<6) /* Bit 6: Reset Scrambler */
8660-#define PHY_B_PEC_EN_LTR (1<<5) /* Bit 5: Ena LED Traffic Mode */
8661+#define PHY_B_PEC_EN_LTR (1<<5) /* Bit 5: Enable LED Traffic Mode */
8662 #define PHY_B_PEC_LED_ON (1<<4) /* Bit 4: Force LED's on */
8663 #define PHY_B_PEC_LED_OFF (1<<3) /* Bit 3: Force LED's off */
8664 #define PHY_B_PEC_EX_IPG (1<<2) /* Bit 2: Extend Tx IPG Mode */
8665@@ -981,7 +1002,7 @@
8666 #define PHY_L_QS_DUP_MOD (1<<9) /* Bit 9: Full/Half Duplex */
8667 #define PHY_L_QS_AN (1<<8) /* Bit 8: AutoNeg is On */
8668 #define PHY_L_QS_AN_C (1<<7) /* Bit 7: AN is Complete */
8669-#define PHY_L_QS_LLE (7<<4) /* Bit 6: Line Length Estim. */
8670+#define PHY_L_QS_LLE (7<<4) /* Bit 6..4: Line Length Estim. */
8671 #define PHY_L_QS_PAUSE (1<<3) /* Bit 3: LP advertised Pause */
8672 #define PHY_L_QS_AS_PAUSE (1<<2) /* Bit 2: LP adv. asym. Pause */
8673 #define PHY_L_QS_ISOLATE (1<<1) /* Bit 1: CIM Isolated */
8674@@ -1029,9 +1050,8 @@
8675 /* Bit 9..0: not described */
8676
8677 /***** PHY_LONE_CIM 16 bit r/o CIM Reg *****/
8678-#define PHY_L_CIM_ISOL (255<<8)/* Bit 15..8: Isolate Count */
8679-#define PHY_L_CIM_FALSE_CAR (255<<0)/* Bit 7..0: False Carrier Count */
8680-
8681+#define PHY_L_CIM_ISOL (0xff<<8) /* Bit 15..8: Isolate Count */
8682+#define PHY_L_CIM_FALSE_CAR 0xff /* Bit 7..0: False Carrier Count */
8683
8684 /*
8685 * Pause Bits (PHY_L_AN_ASP and PHY_L_AN_PC) encoding
8686@@ -1041,7 +1061,6 @@
8687 #define PHY_L_P_ASYM_MD (2<<10) /* Bit 11..10: asymmetric Pause Mode */
8688 #define PHY_L_P_BOTH_MD (3<<10) /* Bit 11..10: both Pause Mode */
8689
8690-
8691 /*
8692 * National-Specific
8693 */
8694@@ -1085,23 +1104,25 @@
8695 * Marvell-Specific
8696 */
8697 /***** PHY_MARV_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
8698-/***** PHY_MARV_AUNE_LP 16 bit r/w Link Part Ability Reg *****/
8699-#define PHY_M_AN_NXT_PG BIT_15 /* Request Next Page */
8700-#define PHY_M_AN_ACK BIT_14 /* (ro) Acknowledge Received */
8701-#define PHY_M_AN_RF BIT_13 /* Remote Fault */
8702- /* Bit 12: reserved */
8703-#define PHY_M_AN_ASP BIT_11 /* Asymmetric Pause */
8704-#define PHY_M_AN_PC BIT_10 /* MAC Pause implemented */
8705-#define PHY_M_AN_100_FD BIT_8 /* Advertise 100Base-TX Full Duplex */
8706-#define PHY_M_AN_100_HD BIT_7 /* Advertise 100Base-TX Half Duplex */
8707-#define PHY_M_AN_10_FD BIT_6 /* Advertise 10Base-TX Full Duplex */
8708-#define PHY_M_AN_10_HD BIT_5 /* Advertise 10Base-TX Half Duplex */
8709-
8710-/* special defines for FIBER (88E1011S only) */
8711-#define PHY_M_AN_ASP_X BIT_8 /* Asymmetric Pause */
8712-#define PHY_M_AN_PC_X BIT_7 /* MAC Pause implemented */
8713-#define PHY_M_AN_1000X_AHD BIT_6 /* Advertise 10000Base-X Half Duplex */
8714-#define PHY_M_AN_1000X_AFD BIT_5 /* Advertise 10000Base-X Full Duplex */
8715+/***** PHY_MARV_AUNE_LP 16 bit r/w Link Partner Ability Reg *****/
8716+#define PHY_M_AN_NXT_PG BIT_15S /* Request Next Page */
8717+#define PHY_M_AN_ACK BIT_14S /* (ro) Acknowledge Received */
8718+#define PHY_M_AN_RF BIT_13S /* Remote Fault */
8719+ /* Bit 12: reserved */
8720+#define PHY_M_AN_ASP BIT_11S /* Asymmetric Pause */
8721+#define PHY_M_AN_PC BIT_10S /* MAC Pause implemented */
8722+#define PHY_M_AN_100_T4 BIT_9S /* Not cap. 100Base-T4 (always 0) */
8723+#define PHY_M_AN_100_FD BIT_8S /* Advertise 100Base-TX Full Duplex */
8724+#define PHY_M_AN_100_HD BIT_7S /* Advertise 100Base-TX Half Duplex */
8725+#define PHY_M_AN_10_FD BIT_6S /* Advertise 10Base-TX Full Duplex */
8726+#define PHY_M_AN_10_HD BIT_5S /* Advertise 10Base-TX Half Duplex */
8727+#define PHY_M_AN_SEL_MSK (0x1f<<4) /* Bit 4.. 0: Selector Field Mask */
8728+
8729+/* special defines for FIBER (88E1040S only) */
8730+#define PHY_M_AN_ASP_X BIT_8S /* Asymmetric Pause */
8731+#define PHY_M_AN_PC_X BIT_7S /* MAC Pause implemented */
8732+#define PHY_M_AN_1000X_AHD BIT_6S /* Advertise 10000Base-X Half Duplex */
8733+#define PHY_M_AN_1000X_AFD BIT_5S /* Advertise 10000Base-X Full Duplex */
8734
8735 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
8736 #define PHY_M_P_NO_PAUSE_X (0<<7) /* Bit 8.. 7: no Pause Mode */
8737@@ -1111,105 +1132,168 @@
8738
8739 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
8740 #define PHY_M_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */
8741-#define PHY_M_1000C_MSE (1<<12) /* Bit 12: Manual Master/Slave Enable */
8742-#define PHY_M_1000C_MSC (1<<11) /* Bit 11: M/S Configuration (1=Master) */
8743-#define PHY_M_1000C_MPD (1<<10) /* Bit 10: Multi-Port Device */
8744-#define PHY_M_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */
8745-#define PHY_M_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */
8746+#define PHY_M_1000C_MSE BIT_12S /* Manual Master/Slave Enable */
8747+#define PHY_M_1000C_MSC BIT_11S /* M/S Configuration (1=Master) */
8748+#define PHY_M_1000C_MPD BIT_10S /* Multi-Port Device */
8749+#define PHY_M_1000C_AFD BIT_9S /* Advertise Full Duplex */
8750+#define PHY_M_1000C_AHD BIT_8S /* Advertise Half Duplex */
8751 /* Bit 7..0: reserved */
8752
8753 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
8754-#define PHY_M_PC_TX_FFD_MSK (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */
8755-#define PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */
8756-#define PHY_M_PC_ASS_CRS_TX (1<<11) /* Bit 11: Assert CRS on Transmit */
8757-#define PHY_M_PC_FL_GOOD (1<<10) /* Bit 10: Force Link Good */
8758-#define PHY_M_PC_EN_DET_MSK (3<<8) /* Bit 9.. 8: Energy Detect Mask */
8759-#define PHY_M_PC_ENA_EXT_D (1<<7) /* Bit 7: Enable Ext. Distance (10BT) */
8760-#define PHY_M_PC_MDIX_MSK (3<<5) /* Bit 6.. 5: MDI/MDIX Config. Mask */
8761-#define PHY_M_PC_DIS_125CLK (1<<4) /* Bit 4: Disable 125 CLK */
8762-#define PHY_M_PC_MAC_POW_UP (1<<3) /* Bit 3: MAC Power up */
8763-#define PHY_M_PC_SQE_T_ENA (1<<2) /* Bit 2: SQE Test Enabled */
8764-#define PHY_M_PC_POL_R_DIS (1<<1) /* Bit 1: Polarity Reversal Disabled */
8765-#define PHY_M_PC_DIS_JABBER (1<<0) /* Bit 0: Disable Jabber */
8766+#define PHY_M_PC_TX_FFD_MSK (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */
8767+#define PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */
8768+#define PHY_M_PC_ASS_CRS_TX BIT_11S /* Assert CRS on Transmit */
8769+#define PHY_M_PC_FL_GOOD BIT_10S /* Force Link Good */
8770+#define PHY_M_PC_EN_DET_MSK (3<<8) /* Bit 9.. 8: Energy Detect Mask */
8771+#define PHY_M_PC_ENA_EXT_D BIT_7S /* Enable Ext. Distance (10BT) */
8772+#define PHY_M_PC_MDIX_MSK (3<<5) /* Bit 6.. 5: MDI/MDIX Config. Mask */
8773+#define PHY_M_PC_DIS_125CLK BIT_4S /* Disable 125 CLK */
8774+#define PHY_M_PC_MAC_POW_UP BIT_3S /* MAC Power up */
8775+#define PHY_M_PC_SQE_T_ENA BIT_2S /* SQE Test Enabled */
8776+#define PHY_M_PC_POL_R_DIS BIT_1S /* Polarity Reversal Disabled */
8777+#define PHY_M_PC_DIS_JABBER BIT_0S /* Disable Jabber */
8778
8779 #define PHY_M_PC_EN_DET SHIFT8(2) /* Energy Detect (Mode 1) */
8780 #define PHY_M_PC_EN_DET_PLUS SHIFT8(3) /* Energy Detect Plus (Mode 2) */
8781
8782-#define PHY_M_PC_MDI_XMODE(x) SHIFT5(x)
8783-#define PHY_M_PC_MAN_MDI 0 /* 00 = Manual MDI configuration */
8784+#define PHY_M_PC_MDI_XMODE(x) (SHIFT5(x) & PHY_M_PC_MDIX_MSK)
8785+
8786+#define PHY_M_PC_MAN_MDI 0 /* 00 = Manual MDI configuration */
8787 #define PHY_M_PC_MAN_MDIX 1 /* 01 = Manual MDIX configuration */
8788 #define PHY_M_PC_ENA_AUTO 3 /* 11 = Enable Automatic Crossover */
8789
8790+/* for Yukon-2/-EC Ultra Gigabit Ethernet PHY (88E1112/88E1149 only) */
8791+#define PHY_M_PC_DIS_LINK_P BIT_15S /* Disable Link Pulses */
8792+#define PHY_M_PC_DSC_MSK (7<<12) /* Bit 14..12: Downshift Counter */
8793+#define PHY_M_PC_DOWN_S_ENA BIT_11S /* Downshift Enable */
8794+ /* !!! Errata in spec. (1 = disable) */
8795+
8796+#define PHY_M_PC_DSC(x) (SHIFT12(x) & PHY_M_PC_DSC_MSK)
8797+ /* 000=1x; 001=2x; 010=3x; 011=4x */
8798+ /* 100=5x; 101=6x; 110=7x; 111=8x */
8799+
8800+/* for Yukon-EC Ultra Gigabit Ethernet PHY (88E1149 only) */
8801+ /* Bit 4: reserved */
8802+#define PHY_M_PC_COP_TX_DIS BIT_3S /* Copper Transmitter Disable */
8803+#define PHY_M_PC_POW_D_ENA BIT_2S /* Power Down Enable */
8804+
8805+/* for 10/100 Fast Ethernet PHY (88E3082 only) */
8806+#define PHY_M_PC_ENA_DTE_DT BIT_15S /* Enable Data Terminal Equ. (DTE) Detect */
8807+#define PHY_M_PC_ENA_ENE_DT BIT_14S /* Enable Energy Detect (sense & pulse) */
8808+#define PHY_M_PC_DIS_NLP_CK BIT_13S /* Disable Normal Link Puls (NLP) Check */
8809+#define PHY_M_PC_ENA_LIP_NP BIT_12S /* Enable Link Partner Next Page Reg. */
8810+#define PHY_M_PC_DIS_NLP_GN BIT_11S /* Disable Normal Link Puls Generation */
8811+
8812+#define PHY_M_PC_DIS_SCRAMB BIT_9S /* Disable Scrambler */
8813+#define PHY_M_PC_DIS_FEFI BIT_8S /* Disable Far End Fault Indic. (FEFI) */
8814+
8815+#define PHY_M_PC_SH_TP_SEL BIT_6S /* Shielded Twisted Pair Select */
8816+#define PHY_M_PC_RX_FD_MSK (3<<2) /* Bit 3.. 2: Rx FIFO Depth Mask */
8817+
8818 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
8819-#define PHY_M_PS_SPEED_MSK (3<<14) /* Bit 15..14: Speed Mask */
8820-#define PHY_M_PS_SPEED_1000 (1<<15) /* 10 = 1000 Mbps */
8821-#define PHY_M_PS_SPEED_100 (1<<14) /* 01 = 100 Mbps */
8822-#define PHY_M_PS_SPEED_10 0 /* 00 = 10 Mbps */
8823-#define PHY_M_PS_FULL_DUP (1<<13) /* Bit 13: Full Duplex */
8824-#define PHY_M_PS_PAGE_REC (1<<12) /* Bit 12: Page Received */
8825-#define PHY_M_PS_SPDUP_RES (1<<11) /* Bit 11: Speed & Duplex Resolved */
8826-#define PHY_M_PS_LINK_UP (1<<10) /* Bit 10: Link Up */
8827-#define PHY_M_PS_CABLE_MSK (3<<7) /* Bit 9.. 7: Cable Length Mask */
8828-#define PHY_M_PS_MDI_X_STAT (1<<6) /* Bit 6: MDI Crossover Stat (1=MDIX) */
8829-#define PHY_M_PS_DOWNS_STAT (1<<5) /* Bit 5: Downshift Status (1=downsh.) */
8830-#define PHY_M_PS_ENDET_STAT (1<<4) /* Bit 4: Energy Detect Status (1=act) */
8831-#define PHY_M_PS_TX_P_EN (1<<3) /* Bit 3: Tx Pause Enabled */
8832-#define PHY_M_PS_RX_P_EN (1<<2) /* Bit 2: Rx Pause Enabled */
8833-#define PHY_M_PS_POL_REV (1<<1) /* Bit 1: Polarity Reversed */
8834-#define PHY_M_PC_JABBER (1<<0) /* Bit 0: Jabber */
8835+#define PHY_M_PS_SPEED_MSK (3<<14) /* Bit 15..14: Speed Mask */
8836+#define PHY_M_PS_SPEED_1000 BIT_15S /* 10 = 1000 Mbps */
8837+#define PHY_M_PS_SPEED_100 BIT_14S /* 01 = 100 Mbps */
8838+#define PHY_M_PS_SPEED_10 0 /* 00 = 10 Mbps */
8839+#define PHY_M_PS_FULL_DUP BIT_13S /* Full Duplex */
8840+#define PHY_M_PS_PAGE_REC BIT_12S /* Page Received */
8841+#define PHY_M_PS_SPDUP_RES BIT_11S /* Speed & Duplex Resolved */
8842+#define PHY_M_PS_LINK_UP BIT_10S /* Link Up */
8843+#define PHY_M_PS_CABLE_MSK (7<<7) /* Bit 9.. 7: Cable Length Mask */
8844+#define PHY_M_PS_MDI_X_STAT BIT_6S /* MDI Crossover Stat (1=MDIX) */
8845+#define PHY_M_PS_DOWNS_STAT BIT_5S /* Downshift Status (1=downsh.) */
8846+#define PHY_M_PS_ENDET_STAT BIT_4S /* Energy Detect Status (1=act) */
8847+#define PHY_M_PS_TX_P_EN BIT_3S /* Tx Pause Enabled */
8848+#define PHY_M_PS_RX_P_EN BIT_2S /* Rx Pause Enabled */
8849+#define PHY_M_PS_POL_REV BIT_1S /* Polarity Reversed */
8850+#define PHY_M_PS_JABBER BIT_0S /* Jabber */
8851
8852 #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
8853
8854+/* for 10/100 Fast Ethernet PHY (88E3082 only) */
8855+#define PHY_M_PS_DTE_DETECT BIT_15S /* Data Terminal Equipment (DTE) Detected */
8856+#define PHY_M_PS_RES_SPEED BIT_14S /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
8857+
8858 /***** PHY_MARV_INT_MASK 16 bit r/w Interrupt Mask Reg *****/
8859 /***** PHY_MARV_INT_STAT 16 bit r/o Interrupt Status Reg *****/
8860-#define PHY_M_IS_AN_ERROR (1<<15) /* Bit 15: Auto-Negotiation Error */
8861-#define PHY_M_IS_LSP_CHANGE (1<<14) /* Bit 14: Link Speed Changed */
8862-#define PHY_M_IS_DUP_CHANGE (1<<13) /* Bit 13: Duplex Mode Changed */
8863-#define PHY_M_IS_AN_PR (1<<12) /* Bit 12: Page Received */
8864-#define PHY_M_IS_AN_COMPL (1<<11) /* Bit 11: Auto-Negotiation Completed */
8865-#define PHY_M_IS_LST_CHANGE (1<<10) /* Bit 10: Link Status Changed */
8866-#define PHY_M_IS_SYMB_ERROR (1<<9) /* Bit 9: Symbol Error */
8867-#define PHY_M_IS_FALSE_CARR (1<<8) /* Bit 8: False Carrier */
8868-#define PHY_M_IS_FIFO_ERROR (1<<7) /* Bit 7: FIFO Overflow/Underrun Error */
8869-#define PHY_M_IS_MDI_CHANGE (1<<6) /* Bit 6: MDI Crossover Changed */
8870-#define PHY_M_IS_DOWNSH_DET (1<<5) /* Bit 5: Downshift Detected */
8871-#define PHY_M_IS_END_CHANGE (1<<4) /* Bit 4: Energy Detect Changed */
8872- /* Bit 3..2: reserved */
8873-#define PHY_M_IS_POL_CHANGE (1<<1) /* Bit 1: Polarity Changed */
8874-#define PHY_M_IS_JABBER (1<<0) /* Bit 0: Jabber */
8875+#define PHY_M_IS_AN_ERROR BIT_15S /* Auto-Negotiation Error */
8876+#define PHY_M_IS_LSP_CHANGE BIT_14S /* Link Speed Changed */
8877+#define PHY_M_IS_DUP_CHANGE BIT_13S /* Duplex Mode Changed */
8878+#define PHY_M_IS_AN_PR BIT_12S /* Page Received */
8879+#define PHY_M_IS_AN_COMPL BIT_11S /* Auto-Negotiation Completed */
8880+#define PHY_M_IS_LST_CHANGE BIT_10S /* Link Status Changed */
8881+#define PHY_M_IS_SYMB_ERROR BIT_9S /* Symbol Error */
8882+#define PHY_M_IS_FALSE_CARR BIT_8S /* False Carrier */
8883+#define PHY_M_IS_FIFO_ERROR BIT_7S /* FIFO Overflow/Underrun Error */
8884+#define PHY_M_IS_MDI_CHANGE BIT_6S /* MDI Crossover Changed */
8885+#define PHY_M_IS_DOWNSH_DET BIT_5S /* Downshift Detected */
8886+#define PHY_M_IS_END_CHANGE BIT_4S /* Energy Detect Changed */
8887+ /* Bit 3: reserved */
8888+#define PHY_M_IS_DTE_CHANGE BIT_2S /* DTE Power Det. Status Changed */
8889+ /* (88E1111 only) */
8890+#define PHY_M_IS_POL_CHANGE BIT_1S /* Polarity Changed */
8891+#define PHY_M_IS_JABBER BIT_0S /* Jabber */
8892
8893 #define PHY_M_DEF_MSK (PHY_M_IS_AN_ERROR | PHY_M_IS_AN_PR | \
8894- PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR)
8895+ PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR | \
8896+ PHY_M_IS_END_CHANGE)
8897
8898 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
8899-#define PHY_M_EC_M_DSC_MSK (3<<10) /* Bit 11..10: Master downshift counter */
8900-#define PHY_M_EC_S_DSC_MSK (3<<8) /* Bit 9.. 8: Slave downshift counter */
8901+#define PHY_M_EC_ENA_BC_EXT BIT_15S /* Enable Block Carr. Ext. (88E1111 only) */
8902+#define PHY_M_EC_ENA_LIN_LB BIT_14S /* Enable Line Loopback (88E1111 only) */
8903+ /* Bit 13: reserved */
8904+#define PHY_M_EC_DIS_LINK_P BIT_12S /* Disable Link Pulses (88E1111 only) */
8905+#define PHY_M_EC_M_DSC_MSK (3<<10) /* Bit 11..10: Master Downshift Counter */
8906+ /* (88E1040 Rev.C0 only) */
8907+#define PHY_M_EC_S_DSC_MSK (3<<8) /* Bit 9.. 8: Slave Downshift Counter */
8908+ /* (88E1040 Rev.C0 only) */
8909+#define PHY_M_EC_DSC_MSK_2 (7<<9) /* Bit 11.. 9: Downshift Counter */
8910+ /* (88E1040 Rev.D0 and higher) */
8911+#define PHY_M_EC_DOWN_S_ENA BIT_8S /* Downshift Enable (88E1040 Rev.D0 and */
8912+ /* 88E1111 !!! Errata in spec. (1=dis.) */
8913+#define PHY_M_EC_RX_TIM_CT BIT_7S /* RGMII Rx Timing Control*/
8914 #define PHY_M_EC_MAC_S_MSK (7<<4) /* Bit 6.. 4: Def. MAC interface speed */
8915-#define PHY_M_EC_FIB_AN_ENA (1<<3) /* Bit 3: Fiber Auto-Neg. Enable */
8916-
8917-#define PHY_M_EC_M_DSC(x) SHIFT10(x) /* 00=1x; 01=2x; 10=3x; 11=4x */
8918-#define PHY_M_EC_S_DSC(x) SHIFT8(x) /* 00=dis; 01=1x; 10=2x; 11=3x */
8919-#define PHY_M_EC_MAC_S(x) SHIFT4(x) /* 01X=0; 110=2.5; 111=25 (MHz) */
8920-
8921+#define PHY_M_EC_FIB_AN_ENA BIT_3S /* Fiber Auto-Neg. Enable 88E1040S only) */
8922+#define PHY_M_EC_DTE_D_ENA BIT_2S /* DTE Detect Enable (88E1111 only) */
8923+#define PHY_M_EC_TX_TIM_CT BIT_1S /* RGMII Tx Timing Control */
8924+#define PHY_M_EC_TRANS_DIS BIT_0S /* Transmitter Disable (88E1111 only) */
8925+
8926+#define PHY_M_EC_M_DSC(x) (SHIFT10(x) & PHY_M_EC_M_DSC_MSK)
8927+ /* 00=1x; 01=2x; 10=3x; 11=4x */
8928+#define PHY_M_EC_S_DSC(x) (SHIFT8(x) & PHY_M_EC_S_DSC_MSK)
8929+ /* 00=dis; 01=1x; 10=2x; 11=3x */
8930+#define PHY_M_EC_MAC_S(x) (SHIFT4(x) & PHY_M_EC_MAC_S_MSK)
8931+ /* 01X=0; 110=2.5; 111=25 (MHz) */
8932+
8933+#define PHY_M_EC_DSC_2(x) (SHIFT9(x) & PHY_M_EC_DSC_MSK_2)
8934+ /* 000=1x; 001=2x; 010=3x; 011=4x */
8935+ /* 100=5x; 101=6x; 110=7x; 111=8x */
8936 #define MAC_TX_CLK_0_MHZ 2
8937 #define MAC_TX_CLK_2_5_MHZ 6
8938 #define MAC_TX_CLK_25_MHZ 7
8939
8940 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
8941-#define PHY_M_LEDC_DIS_LED (1<<15) /* Bit 15: Disable LED */
8942-#define PHY_M_LEDC_PULS_MSK (7<<12) /* Bit 14..12: Pulse Stretch Mask */
8943-#define PHY_M_LEDC_F_INT (1<<11) /* Bit 11: Force Interrupt */
8944-#define PHY_M_LEDC_BL_R_MSK (7<<8) /* Bit 10.. 8: Blink Rate Mask */
8945- /* Bit 7.. 5: reserved */
8946-#define PHY_M_LEDC_LINK_MSK (3<<3) /* Bit 4.. 3: Link Control Mask */
8947-#define PHY_M_LEDC_DP_CTRL (1<<2) /* Bit 2: Duplex Control */
8948-#define PHY_M_LEDC_RX_CTRL (1<<1) /* Bit 1: Rx activity / Link */
8949-#define PHY_M_LEDC_TX_CTRL (1<<0) /* Bit 0: Tx activity / Link */
8950+#define PHY_M_LEDC_DIS_LED BIT_15S /* Disable LED */
8951+#define PHY_M_LEDC_PULS_MSK (7<<12) /* Bit 14..12: Pulse Stretch Mask */
8952+#define PHY_M_LEDC_F_INT BIT_11S /* Force Interrupt */
8953+#define PHY_M_LEDC_BL_R_MSK (7<<8) /* Bit 10.. 8: Blink Rate Mask */
8954+#define PHY_M_LEDC_DP_C_LSB BIT_7S /* Duplex Control (LSB, 88E1111 only) */
8955+#define PHY_M_LEDC_TX_C_LSB BIT_6S /* Tx Control (LSB, 88E1111 only) */
8956+#define PHY_M_LEDC_LK_C_MSK (7<<3) /* Bit 5.. 3: Link Control Mask */
8957+ /* (88E1111 only) */
8958+ /* Bit 7.. 5: reserved (88E1040 only) */
8959+#define PHY_M_LEDC_LINK_MSK (3<<3) /* Bit 4.. 3: Link Control Mask */
8960+ /* (88E1040 only) */
8961+#define PHY_M_LEDC_DP_CTRL BIT_2S /* Duplex Control */
8962+#define PHY_M_LEDC_DP_C_MSB BIT_2S /* Duplex Control (MSB, 88E1111 only) */
8963+#define PHY_M_LEDC_RX_CTRL BIT_1S /* Rx Activity / Link */
8964+#define PHY_M_LEDC_TX_CTRL BIT_0S /* Tx Activity / Link */
8965+#define PHY_M_LEDC_TX_C_MSB BIT_0S /* Tx Control (MSB, 88E1111 only) */
8966
8967-#define PHY_M_LED_PULS_DUR(x) SHIFT12(x) /* Pulse Stretch Duration */
8968+#define PHY_M_LED_PULS_DUR(x) (SHIFT12(x) & PHY_M_LEDC_PULS_MSK)
8969
8970-#define PULS_NO_STR 0 /* no pulse stretching */
8971-#define PULS_21MS 1 /* 21 ms to 42 ms */
8972+#define PULS_NO_STR 0 /* no pulse stretching */
8973+#define PULS_21MS 1 /* 21 ms to 42 ms */
8974 #define PULS_42MS 2 /* 42 ms to 84 ms */
8975 #define PULS_84MS 3 /* 84 ms to 170 ms */
8976 #define PULS_170MS 4 /* 170 ms to 340 ms */
8977@@ -1217,7 +1301,7 @@
8978 #define PULS_670MS 6 /* 670 ms to 1.3 s */
8979 #define PULS_1300MS 7 /* 1.3 s to 2.7 s */
8980
8981-#define PHY_M_LED_BLINK_RT(x) SHIFT8(x) /* Blink Rate */
8982+#define PHY_M_LED_BLINK_RT(x) (SHIFT8(x) & PHY_M_LEDC_BL_R_MSK)
8983
8984 #define BLINK_42MS 0 /* 42 ms */
8985 #define BLINK_84MS 1 /* 84 ms */
8986@@ -1227,6 +1311,8 @@
8987 /* values 5 - 7: reserved */
8988
8989 /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
8990+#define PHY_M_LED_MO_SGMII(x) SHIFT14(x) /* Bit 15..14: SGMII AN Timer */
8991+ /* Bit 13..12: reserved */
8992 #define PHY_M_LED_MO_DUP(x) SHIFT10(x) /* Bit 11..10: Duplex */
8993 #define PHY_M_LED_MO_10(x) SHIFT8(x) /* Bit 9.. 8: Link 10 */
8994 #define PHY_M_LED_MO_100(x) SHIFT6(x) /* Bit 7.. 6: Link 100 */
8995@@ -1240,30 +1326,35 @@
8996 #define MO_LED_ON 3
8997
8998 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
8999- /* Bit 15.. 7: reserved */
9000-#define PHY_M_EC2_FI_IMPED (1<<6) /* Bit 6: Fiber Input Impedance */
9001-#define PHY_M_EC2_FO_IMPED (1<<5) /* Bit 5: Fiber Output Impedance */
9002-#define PHY_M_EC2_FO_M_CLK (1<<4) /* Bit 4: Fiber Mode Clock Enable */
9003-#define PHY_M_EC2_FO_BOOST (1<<3) /* Bit 3: Fiber Output Boost */
9004+ /* Bit 15.. 7: reserved */
9005+#define PHY_M_EC2_FI_IMPED BIT_6S /* Fiber Input Impedance */
9006+#define PHY_M_EC2_FO_IMPED BIT_5S /* Fiber Output Impedance */
9007+#define PHY_M_EC2_FO_M_CLK BIT_4S /* Fiber Mode Clock Enable */
9008+#define PHY_M_EC2_FO_BOOST BIT_3S /* Fiber Output Boost */
9009 #define PHY_M_EC2_FO_AM_MSK 7 /* Bit 2.. 0: Fiber Output Amplitude */
9010
9011-/***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
9012-#define PHY_M_FC_AUTO_SEL (1<<15) /* Bit 15: Fiber/Copper Auto Sel. dis. */
9013-#define PHY_M_FC_AN_REG_ACC (1<<14) /* Bit 14: Fiber/Copper Autoneg. reg acc */
9014-#define PHY_M_FC_RESULUTION (1<<13) /* Bit 13: Fiber/Copper Resulution */
9015-#define PHY_M_SER_IF_AN_BP (1<<12) /* Bit 12: Ser IF autoneg. bypass enable */
9016-#define PHY_M_SER_IF_BP_ST (1<<11) /* Bit 11: Ser IF autoneg. bypass status */
9017-#define PHY_M_IRQ_POLARITY (1<<10) /* Bit 10: IRQ polarity */
9018- /* Bit 9..4: reserved */
9019-#define PHY_M_UNDOC1 (1<< 7) /* undocumented bit !! */
9020-#define PHY_M_MODE_MASK (0xf<<0)/* Bit 3..0: copy of HWCFG MODE[3:0] */
9021-
9022+/***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
9023+#define PHY_M_FC_AUTO_SEL BIT_15S /* Fiber/Copper Auto Sel. Dis. */
9024+#define PHY_M_FC_AN_REG_ACC BIT_14S /* Fiber/Copper AN Reg. Access */
9025+#define PHY_M_FC_RESOLUTION BIT_13S /* Fiber/Copper Resolution */
9026+#define PHY_M_SER_IF_AN_BP BIT_12S /* Ser. IF AN Bypass Enable */
9027+#define PHY_M_SER_IF_BP_ST BIT_11S /* Ser. IF AN Bypass Status */
9028+#define PHY_M_IRQ_POLARITY BIT_10S /* IRQ polarity */
9029+#define PHY_M_DIS_AUT_MED BIT_9S /* Disable Aut. Medium Reg. Selection */
9030+ /* (88E1111 only) */
9031+ /* Bit 9.. 4: reserved (88E1040 only) */
9032+#define PHY_M_UNDOC1 BIT_7S /* undocumented bit !! */
9033+#define PHY_M_DTE_POW_STAT BIT_4S /* DTE Power Status (88E1111 only) */
9034+#define PHY_M_MODE_MASK 0xf /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
9035
9036 /***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/
9037-#define PHY_M_CABD_ENA_TEST (1<<15) /* Bit 15: Enable Test */
9038-#define PHY_M_CABD_STAT_MSK (3<<13) /* Bit 14..13: Status */
9039- /* Bit 12.. 8: reserved */
9040-#define PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance */
9041+#define PHY_M_CABD_ENA_TEST BIT_15S /* Enable Test (Page 0) */
9042+#define PHY_M_CABD_DIS_WAIT BIT_15S /* Disable Waiting Period (Page 1) */
9043+ /* (88E1111 only) */
9044+#define PHY_M_CABD_STAT_MSK (3<<13) /* Bit 14..13: Status Mask */
9045+#define PHY_M_CABD_AMPL_MSK (0x1f<<8) /* Bit 12.. 8: Amplitude Mask */
9046+ /* (88E1111 only) */
9047+#define PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance Mask */
9048
9049 /* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */
9050 #define CABD_STAT_NORMAL 0
9051@@ -1271,6 +1362,79 @@
9052 #define CABD_STAT_OPEN 2
9053 #define CABD_STAT_FAIL 3
9054
9055+/* for 10/100 Fast Ethernet PHY (88E3082 only) */
9056+/***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
9057+ /* Bit 15..12: reserved (used internally) */
9058+#define PHY_M_FELP_LED2_MSK (0xf<<8) /* Bit 11.. 8: LED2 Mask (LINK) */
9059+#define PHY_M_FELP_LED1_MSK (0xf<<4) /* Bit 7.. 4: LED1 Mask (ACT) */
9060+#define PHY_M_FELP_LED0_MSK 0xf /* Bit 3.. 0: LED0 Mask (SPEED) */
9061+
9062+#define PHY_M_FELP_LED2_CTRL(x) (SHIFT8(x) & PHY_M_FELP_LED2_MSK)
9063+#define PHY_M_FELP_LED1_CTRL(x) (SHIFT4(x) & PHY_M_FELP_LED1_MSK)
9064+#define PHY_M_FELP_LED0_CTRL(x) (SHIFT0(x) & PHY_M_FELP_LED0_MSK)
9065+
9066+#define LED_PAR_CTRL_COLX 0x00
9067+#define LED_PAR_CTRL_ERROR 0x01
9068+#define LED_PAR_CTRL_DUPLEX 0x02
9069+#define LED_PAR_CTRL_DP_COL 0x03
9070+#define LED_PAR_CTRL_SPEED 0x04
9071+#define LED_PAR_CTRL_LINK 0x05
9072+#define LED_PAR_CTRL_TX 0x06
9073+#define LED_PAR_CTRL_RX 0x07
9074+#define LED_PAR_CTRL_ACT 0x08
9075+#define LED_PAR_CTRL_LNK_RX 0x09
9076+#define LED_PAR_CTRL_LNK_AC 0x0a
9077+#define LED_PAR_CTRL_ACT_BL 0x0b
9078+#define LED_PAR_CTRL_TX_BL 0x0c
9079+#define LED_PAR_CTRL_RX_BL 0x0d
9080+#define LED_PAR_CTRL_COL_BL 0x0e
9081+#define LED_PAR_CTRL_INACT 0x0f
9082+
9083+/***** PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
9084+#define PHY_M_FESC_DIS_WAIT BIT_2S /* Disable TDR Waiting Period */
9085+#define PHY_M_FESC_ENA_MCLK BIT_1S /* Enable MAC Rx Clock in sleep mode */
9086+#define PHY_M_FESC_SEL_CL_A BIT_0S /* Select Class A driver (100B-TX) */
9087+
9088+/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
9089+/***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/
9090+#define PHY_M_FIB_FORCE_LNK BIT_10S /* Force Link Good */
9091+#define PHY_M_FIB_SIGD_POL BIT_9S /* SIGDET Polarity */
9092+#define PHY_M_FIB_TX_DIS BIT_3S /* Transmitter Disable */
9093+
9094+/***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
9095+#define PHY_M_MAC_MD_MSK (7<<7) /* Bit 9.. 7: Mode Select Mask */
9096+#define PHY_M_MAC_GMIF_PUP BIT_3S /* GMII Power Up (88E1149 only) */
9097+
9098+#define PHY_M_MAC_MD_AUTO 3 /* Auto Copper/1000Base-X */
9099+#define PHY_M_MAC_MD_COPPER 5 /* Copper only */
9100+#define PHY_M_MAC_MD_1000BX 7 /* 1000Base-X only */
9101+#define PHY_M_MAC_MODE_SEL(x) (SHIFT7(x) & PHY_M_MAC_MD_MSK)
9102+
9103+/***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
9104+#define PHY_M_LEDC_LOS_MSK (0xf<<12) /* Bit 15..12: LOS LED Ctrl. Mask */
9105+#define PHY_M_LEDC_INIT_MSK (0xf<<8) /* Bit 11.. 8: INIT LED Ctrl. Mask */
9106+#define PHY_M_LEDC_STA1_MSK (0xf<<4) /* Bit 7.. 4: STAT1 LED Ctrl. Mask */
9107+#define PHY_M_LEDC_STA0_MSK 0xf /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
9108+
9109+#define PHY_M_LEDC_LOS_CTRL(x) (SHIFT12(x) & PHY_M_LEDC_LOS_MSK)
9110+#define PHY_M_LEDC_INIT_CTRL(x) (SHIFT8(x) & PHY_M_LEDC_INIT_MSK)
9111+#define PHY_M_LEDC_STA1_CTRL(x) (SHIFT4(x) & PHY_M_LEDC_STA1_MSK)
9112+#define PHY_M_LEDC_STA0_CTRL(x) (SHIFT0(x) & PHY_M_LEDC_STA0_MSK)
9113+
9114+/***** PHY_MARV_PHY_STAT (page 3) 16 bit r/w Polarity Control Reg. *****/
9115+#define PHY_M_POLC_LS1M_MSK (0xf<<12) /* Bit 15..12: LOS,STAT1 Mix % Mask */
9116+#define PHY_M_POLC_IS0M_MSK (0xf<<8) /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
9117+#define PHY_M_POLC_LOS_MSK (0x3<<6) /* Bit 7.. 6: LOS Pol. Ctrl. Mask */
9118+#define PHY_M_POLC_INIT_MSK (0x3<<4) /* Bit 5.. 4: INIT Pol. Ctrl. Mask */
9119+#define PHY_M_POLC_STA1_MSK (0x3<<2) /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */
9120+#define PHY_M_POLC_STA0_MSK 0x3 /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */
9121+
9122+#define PHY_M_POLC_LS1_P_MIX(x) (SHIFT12(x) & PHY_M_POLC_LS1M_MSK)
9123+#define PHY_M_POLC_IS0_P_MIX(x) (SHIFT8(x) & PHY_M_POLC_IS0M_MSK)
9124+#define PHY_M_POLC_LOS_CTRL(x) (SHIFT6(x) & PHY_M_POLC_LOS_MSK)
9125+#define PHY_M_POLC_INIT_CTRL(x) (SHIFT4(x) & PHY_M_POLC_INIT_MSK)
9126+#define PHY_M_POLC_STA1_CTRL(x) (SHIFT2(x) & PHY_M_POLC_STA1_MSK)
9127+#define PHY_M_POLC_STA0_CTRL(x) (SHIFT0(x) & PHY_M_POLC_STA0_MSK)
9128
9129 /*
9130 * GMAC registers
9131@@ -1431,141 +1595,159 @@
9132 */
9133
9134 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
9135-#define GM_GPSR_SPEED (1<<15) /* Bit 15: Port Speed (1 = 100 Mbps) */
9136-#define GM_GPSR_DUPLEX (1<<14) /* Bit 14: Duplex Mode (1 = Full) */
9137-#define GM_GPSR_FC_TX_DIS (1<<13) /* Bit 13: Tx Flow-Control Mode Disabled */
9138-#define GM_GPSR_LINK_UP (1<<12) /* Bit 12: Link Up Status */
9139-#define GM_GPSR_PAUSE (1<<11) /* Bit 11: Pause State */
9140-#define GM_GPSR_TX_ACTIVE (1<<10) /* Bit 10: Tx in Progress */
9141-#define GM_GPSR_EXC_COL (1<<9) /* Bit 9: Excessive Collisions Occured */
9142-#define GM_GPSR_LAT_COL (1<<8) /* Bit 8: Late Collisions Occured */
9143- /* Bit 7..6: reserved */
9144-#define GM_GPSR_PHY_ST_CH (1<<5) /* Bit 5: PHY Status Change */
9145-#define GM_GPSR_GIG_SPEED (1<<4) /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
9146-#define GM_GPSR_PART_MODE (1<<3) /* Bit 3: Partition mode */
9147-#define GM_GPSR_FC_RX_DIS (1<<2) /* Bit 2: Rx Flow-Control Mode Disabled */
9148-#define GM_GPSR_PROM_EN (1<<1) /* Bit 1: Promiscuous Mode Enabled */
9149- /* Bit 0: reserved */
9150-
9151+#define GM_GPSR_SPEED BIT_15S /* Port Speed (1 = 100 Mbps) */
9152+#define GM_GPSR_DUPLEX BIT_14S /* Duplex Mode (1 = Full) */
9153+#define GM_GPSR_FC_TX_DIS BIT_13S /* Tx Flow-Control Mode Disabled */
9154+#define GM_GPSR_LINK_UP BIT_12S /* Link Up Status */
9155+#define GM_GPSR_PAUSE BIT_11S /* Pause State */
9156+#define GM_GPSR_TX_ACTIVE BIT_10S /* Tx in Progress */
9157+#define GM_GPSR_EXC_COL BIT_9S /* Excessive Collisions Occured */
9158+#define GM_GPSR_LAT_COL BIT_8S /* Late Collisions Occured */
9159+ /* Bit 7.. 6: reserved */
9160+#define GM_GPSR_PHY_ST_CH BIT_5S /* PHY Status Change */
9161+#define GM_GPSR_GIG_SPEED BIT_4S /* Gigabit Speed (1 = 1000 Mbps) */
9162+#define GM_GPSR_PART_MODE BIT_3S /* Partition mode */
9163+#define GM_GPSR_FC_RX_DIS BIT_2S /* Rx Flow-Control Mode Disabled */
9164+ /* Bit 2.. 0: reserved */
9165+
9166 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
9167- /* Bit 15: reserved */
9168-#define GM_GPCR_PROM_ENA (1<<14) /* Bit 14: Enable Promiscuous Mode */
9169-#define GM_GPCR_FC_TX_DIS (1<<13) /* Bit 13: Disable Tx Flow-Control Mode */
9170-#define GM_GPCR_TX_ENA (1<<12) /* Bit 12: Enable Transmit */
9171-#define GM_GPCR_RX_ENA (1<<11) /* Bit 11: Enable Receive */
9172-#define GM_GPCR_BURST_ENA (1<<10) /* Bit 10: Enable Burst Mode */
9173-#define GM_GPCR_LOOP_ENA (1<<9) /* Bit 9: Enable MAC Loopback Mode */
9174-#define GM_GPCR_PART_ENA (1<<8) /* Bit 8: Enable Partition Mode */
9175-#define GM_GPCR_GIGS_ENA (1<<7) /* Bit 7: Gigabit Speed (1000 Mbps) */
9176-#define GM_GPCR_FL_PASS (1<<6) /* Bit 6: Force Link Pass */
9177-#define GM_GPCR_DUP_FULL (1<<5) /* Bit 5: Full Duplex Mode */
9178-#define GM_GPCR_FC_RX_DIS (1<<4) /* Bit 4: Disable Rx Flow-Control Mode */
9179-#define GM_GPCR_SPEED_100 (1<<3) /* Bit 3: Port Speed 100 Mbps */
9180-#define GM_GPCR_AU_DUP_DIS (1<<2) /* Bit 2: Disable Auto-Update Duplex */
9181-#define GM_GPCR_AU_FCT_DIS (1<<1) /* Bit 1: Disable Auto-Update Flow-C. */
9182-#define GM_GPCR_AU_SPD_DIS (1<<0) /* Bit 0: Disable Auto-Update Speed */
9183+#define GM_GPCR_RMII_PH_ENA BIT_15S /* Enable RMII for PHY (Yukon-FE only) */
9184+#define GM_GPCR_RMII_LB_ENA BIT_14S /* Enable RMII Loopback (Yukon-FE only) */
9185+#define GM_GPCR_FC_TX_DIS BIT_13S /* Disable Tx Flow-Control Mode */
9186+#define GM_GPCR_TX_ENA BIT_12S /* Enable Transmit */
9187+#define GM_GPCR_RX_ENA BIT_11S /* Enable Receive */
9188+ /* Bit 10: reserved */
9189+#define GM_GPCR_LOOP_ENA BIT_9S /* Enable MAC Loopback Mode */
9190+#define GM_GPCR_PART_ENA BIT_8S /* Enable Partition Mode */
9191+#define GM_GPCR_GIGS_ENA BIT_7S /* Gigabit Speed (1000 Mbps) */
9192+#define GM_GPCR_FL_PASS BIT_6S /* Force Link Pass */
9193+#define GM_GPCR_DUP_FULL BIT_5S /* Full Duplex Mode */
9194+#define GM_GPCR_FC_RX_DIS BIT_4S /* Disable Rx Flow-Control Mode */
9195+#define GM_GPCR_SPEED_100 BIT_3S /* Port Speed 100 Mbps */
9196+#define GM_GPCR_AU_DUP_DIS BIT_2S /* Disable Auto-Update Duplex */
9197+#define GM_GPCR_AU_FCT_DIS BIT_1S /* Disable Auto-Update Flow-C. */
9198+#define GM_GPCR_AU_SPD_DIS BIT_0S /* Disable Auto-Update Speed */
9199
9200 #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
9201 #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |\
9202 GM_GPCR_AU_SPD_DIS)
9203-
9204+
9205 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
9206-#define GM_TXCR_FORCE_JAM (1<<15) /* Bit 15: Force Jam / Flow-Control */
9207-#define GM_TXCR_CRC_DIS (1<<14) /* Bit 14: Disable insertion of CRC */
9208-#define GM_TXCR_PAD_DIS (1<<13) /* Bit 13: Disable padding of packets */
9209-#define GM_TXCR_COL_THR_MSK (1<<10) /* Bit 12..10: Collision Threshold */
9210+#define GM_TXCR_FORCE_JAM BIT_15S /* Force Jam / Flow-Control */
9211+#define GM_TXCR_CRC_DIS BIT_14S /* Disable insertion of CRC */
9212+#define GM_TXCR_PAD_DIS BIT_13S /* Disable padding of packets */
9213+#define GM_TXCR_COL_THR_MSK (7<<10) /* Bit 12..10: Collision Threshold Mask */
9214+ /* Bit 9.. 8: reserved */
9215+#define GM_TXCR_PAD_PAT_MSK 0xff /* Bit 7.. 0: Padding Pattern Mask */
9216+ /* (Yukon-2 only) */
9217
9218 #define TX_COL_THR(x) (SHIFT10(x) & GM_TXCR_COL_THR_MSK)
9219
9220 #define TX_COL_DEF 0x04
9221-
9222+
9223 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
9224-#define GM_RXCR_UCF_ENA (1<<15) /* Bit 15: Enable Unicast filtering */
9225-#define GM_RXCR_MCF_ENA (1<<14) /* Bit 14: Enable Multicast filtering */
9226-#define GM_RXCR_CRC_DIS (1<<13) /* Bit 13: Remove 4-byte CRC */
9227-#define GM_RXCR_PASS_FC (1<<12) /* Bit 12: Pass FC packets to FIFO */
9228-
9229+#define GM_RXCR_UCF_ENA BIT_15S /* Enable Unicast filtering */
9230+#define GM_RXCR_MCF_ENA BIT_14S /* Enable Multicast filtering */
9231+#define GM_RXCR_CRC_DIS BIT_13S /* Remove 4-byte CRC */
9232+#define GM_RXCR_PASS_FC BIT_12S /* Pass FC packets to FIFO (Yukon-1 only) */
9233+ /* Bit 11.. 0: reserved */
9234+
9235 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
9236-#define GM_TXPA_JAMLEN_MSK (0x03<<14) /* Bit 15..14: Jam Length */
9237-#define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13..9: Jam IPG */
9238-#define GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8..4: IPG Jam to Data */
9239- /* Bit 3..0: reserved */
9240+#define GM_TXPA_JAMLEN_MSK (3<<14) /* Bit 15..14: Jam Length Mask */
9241+#define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13.. 9: Jam IPG Mask */
9242+#define GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8.. 4: IPG Jam to Data Mask */
9243+#define GM_TXPA_BO_LIM_MSK 0x0f /* Bit 3.. 0: Backoff Limit Mask */
9244+ /* (Yukon-2 only) */
9245
9246 #define TX_JAM_LEN_VAL(x) (SHIFT14(x) & GM_TXPA_JAMLEN_MSK)
9247 #define TX_JAM_IPG_VAL(x) (SHIFT9(x) & GM_TXPA_JAMIPG_MSK)
9248 #define TX_IPG_JAM_DATA(x) (SHIFT4(x) & GM_TXPA_JAMDAT_MSK)
9249+#define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK)
9250
9251 #define TX_JAM_LEN_DEF 0x03
9252 #define TX_JAM_IPG_DEF 0x0b
9253 #define TX_IPG_JAM_DEF 0x1c
9254+#define TX_BOF_LIM_DEF 0x04
9255
9256 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
9257-#define GM_SMOD_DATABL_MSK (0x1f<<11) /* Bit 15..11: Data Blinder (r/o) */
9258-#define GM_SMOD_LIMIT_4 (1<<10) /* Bit 10: 4 consecutive Tx trials */
9259-#define GM_SMOD_VLAN_ENA (1<<9) /* Bit 9: Enable VLAN (Max. Frame Len) */
9260-#define GM_SMOD_JUMBO_ENA (1<<8) /* Bit 8: Enable Jumbo (Max. Frame Len) */
9261- /* Bit 7..5: reserved */
9262-#define GM_SMOD_IPG_MSK 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
9263-
9264+#define GM_SMOD_DATABL_MSK (0x1f<<11) /* Bit 15..11: Data Blinder */
9265+ /* r/o on Yukon, r/w on Yukon-EC */
9266+#define GM_SMOD_LIMIT_4 BIT_10S /* 4 consecutive Tx trials */
9267+#define GM_SMOD_VLAN_ENA BIT_9S /* Enable VLAN (Max. Frame Len) */
9268+#define GM_SMOD_JUMBO_ENA BIT_8S /* Enable Jumbo (Max. Frame Len) */
9269+ /* Bit 7.. 5: reserved */
9270+#define GM_SMOD_IPG_MSK 0x1f /* Bit 4.. 0: Inter-Packet Gap (IPG) */
9271+
9272 #define DATA_BLIND_VAL(x) (SHIFT11(x) & GM_SMOD_DATABL_MSK)
9273-#define DATA_BLIND_DEF 0x04
9274+#define IPG_DATA_VAL(x) ((x) & GM_SMOD_IPG_MSK)
9275
9276-#define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
9277+#define DATA_BLIND_DEF 0x04
9278 #define IPG_DATA_DEF 0x1e
9279
9280 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
9281 #define GM_SMI_CT_PHY_A_MSK (0x1f<<11) /* Bit 15..11: PHY Device Address */
9282 #define GM_SMI_CT_REG_A_MSK (0x1f<<6) /* Bit 10.. 6: PHY Register Address */
9283-#define GM_SMI_CT_OP_RD (1<<5) /* Bit 5: OpCode Read (0=Write)*/
9284-#define GM_SMI_CT_RD_VAL (1<<4) /* Bit 4: Read Valid (Read completed) */
9285-#define GM_SMI_CT_BUSY (1<<3) /* Bit 3: Busy (Operation in progress) */
9286- /* Bit 2..0: reserved */
9287-
9288+#define GM_SMI_CT_OP_RD BIT_5S /* OpCode Read (0=Write)*/
9289+#define GM_SMI_CT_RD_VAL BIT_4S /* Read Valid (Read completed) */
9290+#define GM_SMI_CT_BUSY BIT_3S /* Busy (Operation in progress) */
9291+ /* Bit 2.. 0: reserved */
9292+
9293 #define GM_SMI_CT_PHY_AD(x) (SHIFT11(x) & GM_SMI_CT_PHY_A_MSK)
9294 #define GM_SMI_CT_REG_AD(x) (SHIFT6(x) & GM_SMI_CT_REG_A_MSK)
9295
9296- /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
9297- /* Bit 15..6: reserved */
9298-#define GM_PAR_MIB_CLR (1<<5) /* Bit 5: Set MIB Clear Counter Mode */
9299-#define GM_PAR_MIB_TST (1<<4) /* Bit 4: MIB Load Counter (Test Mode) */
9300- /* Bit 3..0: reserved */
9301-
9302+/* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
9303+ /* Bit 15.. 6: reserved */
9304+#define GM_PAR_MIB_CLR BIT_5S /* Set MIB Clear Counter Mode */
9305+#define GM_PAR_MIB_TST BIT_4S /* MIB Load Counter (Test Mode) */
9306+ /* Bit 3.. 0: reserved */
9307+
9308 /* Receive Frame Status Encoding */
9309-#define GMR_FS_LEN (0xffffUL<<16) /* Bit 31..16: Rx Frame Length */
9310+#define GMR_FS_LEN_MSK (0xffffUL<<16) /* Bit 31..16: Rx Frame Length */
9311 /* Bit 15..14: reserved */
9312-#define GMR_FS_VLAN (1L<<13) /* Bit 13: VLAN Packet */
9313-#define GMR_FS_JABBER (1L<<12) /* Bit 12: Jabber Packet */
9314-#define GMR_FS_UN_SIZE (1L<<11) /* Bit 11: Undersize Packet */
9315-#define GMR_FS_MC (1L<<10) /* Bit 10: Multicast Packet */
9316-#define GMR_FS_BC (1L<<9) /* Bit 9: Broadcast Packet */
9317-#define GMR_FS_RX_OK (1L<<8) /* Bit 8: Receive OK (Good Packet) */
9318-#define GMR_FS_GOOD_FC (1L<<7) /* Bit 7: Good Flow-Control Packet */
9319-#define GMR_FS_BAD_FC (1L<<6) /* Bit 6: Bad Flow-Control Packet */
9320-#define GMR_FS_MII_ERR (1L<<5) /* Bit 5: MII Error */
9321-#define GMR_FS_LONG_ERR (1L<<4) /* Bit 4: Too Long Packet */
9322-#define GMR_FS_FRAGMENT (1L<<3) /* Bit 3: Fragment */
9323+#define GMR_FS_VLAN BIT_13 /* VLAN Packet */
9324+#define GMR_FS_JABBER BIT_12 /* Jabber Packet */
9325+#define GMR_FS_UN_SIZE BIT_11 /* Undersize Packet */
9326+#define GMR_FS_MC BIT_10 /* Multicast Packet */
9327+#define GMR_FS_BC BIT_9 /* Broadcast Packet */
9328+#define GMR_FS_RX_OK BIT_8 /* Receive OK (Good Packet) */
9329+#define GMR_FS_GOOD_FC BIT_7 /* Good Flow-Control Packet */
9330+#define GMR_FS_BAD_FC BIT_6 /* Bad Flow-Control Packet */
9331+#define GMR_FS_MII_ERR BIT_5 /* MII Error */
9332+#define GMR_FS_LONG_ERR BIT_4 /* Too Long Packet */
9333+#define GMR_FS_FRAGMENT BIT_3 /* Fragment */
9334 /* Bit 2: reserved */
9335-#define GMR_FS_CRC_ERR (1L<<1) /* Bit 1: CRC Error */
9336-#define GMR_FS_RX_FF_OV (1L<<0) /* Bit 0: Rx FIFO Overflow */
9337+#define GMR_FS_CRC_ERR BIT_1 /* CRC Error */
9338+#define GMR_FS_RX_FF_OV BIT_0 /* Rx FIFO Overflow */
9339+
9340+#define GMR_FS_LEN_SHIFT 16
9341
9342 /*
9343 * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR)
9344 */
9345-#define GMR_FS_ANY_ERR (GMR_FS_CRC_ERR | \
9346- GMR_FS_LONG_ERR | \
9347+#ifdef SK_DIAG
9348+#define GMR_FS_ANY_ERR ( \
9349+ GMR_FS_RX_FF_OV | \
9350+ GMR_FS_CRC_ERR | \
9351+ GMR_FS_FRAGMENT | \
9352 GMR_FS_MII_ERR | \
9353 GMR_FS_BAD_FC | \
9354 GMR_FS_GOOD_FC | \
9355 GMR_FS_JABBER)
9356-
9357-/* Rx GMAC FIFO Flush Mask (default) */
9358-#define RX_FF_FL_DEF_MSK (GMR_FS_CRC_ERR | \
9359+#else
9360+#define GMR_FS_ANY_ERR ( \
9361 GMR_FS_RX_FF_OV | \
9362+ GMR_FS_CRC_ERR | \
9363+ GMR_FS_FRAGMENT | \
9364+ GMR_FS_LONG_ERR | \
9365 GMR_FS_MII_ERR | \
9366 GMR_FS_BAD_FC | \
9367 GMR_FS_GOOD_FC | \
9368 GMR_FS_UN_SIZE | \
9369 GMR_FS_JABBER)
9370+#endif
9371+
9372+/* Rx GMAC FIFO Flush Mask (default) */
9373+#define RX_FF_FL_DEF_MSK GMR_FS_ANY_ERR
9374
9375 /* typedefs *******************************************************************/
9376
9377@@ -1577,3 +1759,4 @@
9378 #endif /* __cplusplus */
9379
9380 #endif /* __INC_XMAC_H */
9381+
9382diff -urN linux-2.6.17.orig/drivers/net/sk98lin/skaddr.c linux-2.6.17/drivers/net/sk98lin/skaddr.c
9383--- linux-2.6.17.orig/drivers/net/sk98lin/skaddr.c 2006-06-22 13:17:16.000000000 +0200
9384+++ linux-2.6.17/drivers/net/sk98lin/skaddr.c 2006-04-27 11:43:44.000000000 +0200
9385@@ -2,16 +2,17 @@
9386 *
9387 * Name: skaddr.c
9388 * Project: Gigabit Ethernet Adapters, ADDR-Module
9389- * Version: $Revision$
9390- * Date: $Date$
9391+ * Version: $Revision$
9392+ * Date: $Date$
9393 * Purpose: Manage Addresses (Multicast and Unicast) and Promiscuous Mode.
9394 *
9395 ******************************************************************************/
9396
9397 /******************************************************************************
9398 *
9399+ * LICENSE:
9400 * (C)Copyright 1998-2002 SysKonnect GmbH.
9401- * (C)Copyright 2002-2003 Marvell.
9402+ * (C)Copyright 2002-2005 Marvell.
9403 *
9404 * This program is free software; you can redistribute it and/or modify
9405 * it under the terms of the GNU General Public License as published by
9406@@ -19,6 +20,7 @@
9407 * (at your option) any later version.
9408 *
9409 * The information in this file is provided "AS IS" without warranty.
9410+ * /LICENSE
9411 *
9412 ******************************************************************************/
9413
9414@@ -44,7 +46,7 @@
9415
9416 #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
9417 static const char SysKonnectFileId[] =
9418- "@(#) $Id$ (C) Marvell.";
9419+ "@(#) $Id$ (C) Marvell.";
9420 #endif /* DEBUG ||!LINT || !SK_SLIM */
9421
9422 #define __SKADDR_C
9423@@ -58,11 +60,10 @@
9424
9425 /* defines ********************************************************************/
9426
9427-
9428 #define XMAC_POLY 0xEDB88320UL /* CRC32-Poly - XMAC: Little Endian */
9429 #define GMAC_POLY 0x04C11DB7L /* CRC16-Poly - GMAC: Little Endian */
9430 #define HASH_BITS 6 /* #bits in hash */
9431-#define SK_MC_BIT 0x01
9432+#define SK_MC_BIT 0x01
9433
9434 /* Error numbers and messages. */
9435
9436@@ -79,7 +80,7 @@
9437
9438 /* 64-bit hash values with all bits set. */
9439
9440-static const SK_U16 OnesHash[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
9441+SK_U16 OnesHash[4] = {0xffff, 0xffff, 0xffff, 0xffff};
9442
9443 /* local variables ************************************************************/
9444
9445@@ -87,21 +88,6 @@
9446 static int Next0[SK_MAX_MACS] = {0};
9447 #endif /* DEBUG */
9448
9449-static int SkAddrGmacMcAdd(SK_AC *pAC, SK_IOC IoC, SK_U32 PortNumber,
9450- SK_MAC_ADDR *pMc, int Flags);
9451-static int SkAddrGmacMcClear(SK_AC *pAC, SK_IOC IoC, SK_U32 PortNumber,
9452- int Flags);
9453-static int SkAddrGmacMcUpdate(SK_AC *pAC, SK_IOC IoC, SK_U32 PortNumber);
9454-static int SkAddrGmacPromiscuousChange(SK_AC *pAC, SK_IOC IoC,
9455- SK_U32 PortNumber, int NewPromMode);
9456-static int SkAddrXmacMcAdd(SK_AC *pAC, SK_IOC IoC, SK_U32 PortNumber,
9457- SK_MAC_ADDR *pMc, int Flags);
9458-static int SkAddrXmacMcClear(SK_AC *pAC, SK_IOC IoC, SK_U32 PortNumber,
9459- int Flags);
9460-static int SkAddrXmacMcUpdate(SK_AC *pAC, SK_IOC IoC, SK_U32 PortNumber);
9461-static int SkAddrXmacPromiscuousChange(SK_AC *pAC, SK_IOC IoC,
9462- SK_U32 PortNumber, int NewPromMode);
9463-
9464 /* functions ******************************************************************/
9465
9466 /******************************************************************************
9467@@ -151,13 +137,12 @@
9468
9469 switch (Level) {
9470 case SK_INIT_DATA:
9471- SK_MEMSET((char *) &pAC->Addr, (SK_U8) 0,
9472- (SK_U16) sizeof(SK_ADDR));
9473+ SK_MEMSET((char *)&pAC->Addr, (SK_U8)0, (SK_U16)sizeof(SK_ADDR));
9474
9475 for (i = 0; i < SK_MAX_MACS; i++) {
9476 pAPort = &pAC->Addr.Port[i];
9477 pAPort->PromMode = SK_PROM_MODE_NONE;
9478-
9479+
9480 pAPort->FirstExactMatchRlmt = SK_ADDR_FIRST_MATCH_RLMT;
9481 pAPort->FirstExactMatchDrv = SK_ADDR_FIRST_MATCH_DRV;
9482 pAPort->NextExactMatchRlmt = SK_ADDR_FIRST_MATCH_RLMT;
9483@@ -174,7 +159,7 @@
9484 /* pAC->Addr.InitDone = SK_INIT_DATA; */
9485 break;
9486
9487- case SK_INIT_IO:
9488+ case SK_INIT_IO:
9489 #ifndef SK_NO_RLMT
9490 for (i = 0; i < SK_MAX_NETS; i++) {
9491 pAC->Addr.Net[i].ActivePort = pAC->Rlmt.Net[i].ActivePort;
9492@@ -188,7 +173,7 @@
9493 }
9494 }
9495 #endif /* DEBUG */
9496-
9497+
9498 /* Read permanent logical MAC address from Control Register File. */
9499 for (j = 0; j < SK_MAC_ADDR_LEN; j++) {
9500 InAddr = (SK_U8 *) &pAC->Addr.Net[0].PermanentMacAddress.a[j];
9501@@ -206,11 +191,11 @@
9502 pAC->Addr.Port[pAC->Addr.Net[0].ActivePort].Exact[0] =
9503 pAC->Addr.Net[0].CurrentMacAddress;
9504 #if SK_MAX_NETS > 1
9505- /* Set logical MAC address for net 2 to (log | 3). */
9506+ /* Set logical MAC address for net 2 to. */
9507 if (!pAC->Addr.Net[1].CurrentMacAddressSet) {
9508 pAC->Addr.Net[1].PermanentMacAddress =
9509 pAC->Addr.Net[0].PermanentMacAddress;
9510- pAC->Addr.Net[1].PermanentMacAddress.a[5] |= 3;
9511+ pAC->Addr.Net[1].PermanentMacAddress.a[5] += 1;
9512 /* Set the current logical MAC address to the permanent one. */
9513 pAC->Addr.Net[1].CurrentMacAddress =
9514 pAC->Addr.Net[1].PermanentMacAddress;
9515@@ -228,8 +213,8 @@
9516 pAC->Addr.Net[i].PermanentMacAddress.a[2],
9517 pAC->Addr.Net[i].PermanentMacAddress.a[3],
9518 pAC->Addr.Net[i].PermanentMacAddress.a[4],
9519- pAC->Addr.Net[i].PermanentMacAddress.a[5]))
9520-
9521+ pAC->Addr.Net[i].PermanentMacAddress.a[5]));
9522+
9523 SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_INIT,
9524 ("Logical MAC Address (Net%d): %02X %02X %02X %02X %02X %02X\n",
9525 i,
9526@@ -238,7 +223,7 @@
9527 pAC->Addr.Net[i].CurrentMacAddress.a[2],
9528 pAC->Addr.Net[i].CurrentMacAddress.a[3],
9529 pAC->Addr.Net[i].CurrentMacAddress.a[4],
9530- pAC->Addr.Net[i].CurrentMacAddress.a[5]))
9531+ pAC->Addr.Net[i].CurrentMacAddress.a[5]));
9532 }
9533 #endif /* DEBUG */
9534
9535@@ -281,8 +266,8 @@
9536 pAPort->PermanentMacAddress.a[2],
9537 pAPort->PermanentMacAddress.a[3],
9538 pAPort->PermanentMacAddress.a[4],
9539- pAPort->PermanentMacAddress.a[5]))
9540-
9541+ pAPort->PermanentMacAddress.a[5]));
9542+
9543 SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_INIT,
9544 ("SkAddrInit: Physical MAC Address: %02X %02X %02X %02X %02X %02X\n",
9545 pAPort->CurrentMacAddress.a[0],
9546@@ -290,7 +275,7 @@
9547 pAPort->CurrentMacAddress.a[2],
9548 pAPort->CurrentMacAddress.a[3],
9549 pAPort->CurrentMacAddress.a[4],
9550- pAPort->CurrentMacAddress.a[5]))
9551+ pAPort->CurrentMacAddress.a[5]));
9552 #endif /* DEBUG */
9553 }
9554 /* pAC->Addr.InitDone = SK_INIT_IO; */
9555@@ -314,7 +299,7 @@
9556 }
9557
9558 return (SK_ADDR_SUCCESS);
9559-
9560+
9561 } /* SkAddrInit */
9562
9563 #ifndef SK_SLIM
9564@@ -348,16 +333,20 @@
9565 int Flags) /* permanent/non-perm, sw-only */
9566 {
9567 int ReturnCode;
9568-
9569+
9570 if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
9571 return (SK_ADDR_ILLEGAL_PORT);
9572 }
9573-
9574+
9575 if (pAC->GIni.GIGenesis) {
9576+#ifdef GENESIS
9577 ReturnCode = SkAddrXmacMcClear(pAC, IoC, PortNumber, Flags);
9578+#endif
9579 }
9580 else {
9581+#ifdef YUKON
9582 ReturnCode = SkAddrGmacMcClear(pAC, IoC, PortNumber, Flags);
9583+#endif
9584 }
9585
9586 return (ReturnCode);
9587@@ -367,7 +356,7 @@
9588 #endif /* !SK_SLIM */
9589
9590 #ifndef SK_SLIM
9591-
9592+#ifdef GENESIS
9593 /******************************************************************************
9594 *
9595 * SkAddrXmacMcClear - clear the multicast table
9596@@ -387,7 +376,7 @@
9597 * SK_ADDR_SUCCESS
9598 * SK_ADDR_ILLEGAL_PORT
9599 */
9600-static int SkAddrXmacMcClear(
9601+int SkAddrXmacMcClear(
9602 SK_AC *pAC, /* adapter context */
9603 SK_IOC IoC, /* I/O context */
9604 SK_U32 PortNumber, /* Index of affected port */
9605@@ -417,13 +406,13 @@
9606 }
9607
9608 return (SK_ADDR_SUCCESS);
9609-
9610-} /* SkAddrXmacMcClear */
9611
9612+} /* SkAddrXmacMcClear */
9613+#endif /* GENESIS */
9614 #endif /* !SK_SLIM */
9615
9616 #ifndef SK_SLIM
9617-
9618+#ifdef YUKON
9619 /******************************************************************************
9620 *
9621 * SkAddrGmacMcClear - clear the multicast table
9622@@ -444,7 +433,7 @@
9623 * SK_ADDR_SUCCESS
9624 * SK_ADDR_ILLEGAL_PORT
9625 */
9626-static int SkAddrGmacMcClear(
9627+int SkAddrGmacMcClear(
9628 SK_AC *pAC, /* adapter context */
9629 SK_IOC IoC, /* I/O context */
9630 SK_U32 PortNumber, /* Index of affected port */
9631@@ -462,38 +451,37 @@
9632 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[4],
9633 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[5],
9634 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[6],
9635- pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7]))
9636+ pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7]));
9637 #endif /* DEBUG */
9638
9639 /* Clear InexactFilter */
9640 for (i = 0; i < 8; i++) {
9641 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] = 0;
9642 }
9643-
9644+
9645 if (Flags & SK_ADDR_PERMANENT) { /* permanent => RLMT */
9646-
9647+
9648 /* Copy DRV bits to InexactFilter. */
9649 for (i = 0; i < 8; i++) {
9650 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |=
9651 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[i];
9652-
9653+
9654 /* Clear InexactRlmtFilter. */
9655 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[i] = 0;
9656-
9657- }
9658+ }
9659 }
9660 else { /* not permanent => DRV */
9661-
9662+
9663 /* Copy RLMT bits to InexactFilter. */
9664 for (i = 0; i < 8; i++) {
9665 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |=
9666 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[i];
9667-
9668+
9669 /* Clear InexactDrvFilter. */
9670 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[i] = 0;
9671 }
9672 }
9673-
9674+
9675 #ifdef DEBUG
9676 SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
9677 ("GMAC InexactFilter (cleared): %02X %02X %02X %02X %02X %02X %02X %02X\n",
9678@@ -504,19 +492,20 @@
9679 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[4],
9680 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[5],
9681 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[6],
9682- pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7]))
9683+ pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7]));
9684 #endif /* DEBUG */
9685-
9686+
9687 if (!(Flags & SK_MC_SW_ONLY)) {
9688 (void) SkAddrGmacMcUpdate(pAC, IoC, PortNumber);
9689 }
9690-
9691+
9692 return (SK_ADDR_SUCCESS);
9693
9694 } /* SkAddrGmacMcClear */
9695+#endif /* YUKON */
9696
9697 #ifndef SK_ADDR_CHEAT
9698-
9699+#ifdef GENESIS
9700 /******************************************************************************
9701 *
9702 * SkXmacMcHash - hash multicast address
9703@@ -534,7 +523,7 @@
9704 * Returns:
9705 * Hash value of multicast address.
9706 */
9707-static SK_U32 SkXmacMcHash(
9708+SK_U32 SkXmacMcHash(
9709 unsigned char *pMc) /* Multicast address */
9710 {
9711 SK_U32 Idx;
9712@@ -553,8 +542,9 @@
9713 return (Crc & ((1 << HASH_BITS) - 1));
9714
9715 } /* SkXmacMcHash */
9716+#endif /* GENESIS */
9717
9718-
9719+#ifdef YUKON
9720 /******************************************************************************
9721 *
9722 * SkGmacMcHash - hash multicast address
9723@@ -572,7 +562,7 @@
9724 * Returns:
9725 * Hash value of multicast address.
9726 */
9727-static SK_U32 SkGmacMcHash(
9728+SK_U32 SkGmacMcHash(
9729 unsigned char *pMc) /* Multicast address */
9730 {
9731 SK_U32 Data;
9732@@ -585,7 +575,7 @@
9733 for (Byte = 0; Byte < 6; Byte++) {
9734 /* Get next byte. */
9735 Data = (SK_U32) pMc[Byte];
9736-
9737+
9738 /* Change bit order in byte. */
9739 TmpData = Data;
9740 for (Bit = 0; Bit < 8; Bit++) {
9741@@ -597,7 +587,7 @@
9742 }
9743 TmpData >>= 1;
9744 }
9745-
9746+
9747 Crc ^= (Data << 24);
9748 for (Bit = 0; Bit < 8; Bit++) {
9749 if (Crc & 0x80000000) {
9750@@ -608,11 +598,11 @@
9751 }
9752 }
9753 }
9754-
9755+
9756 return (Crc & ((1 << HASH_BITS) - 1));
9757
9758 } /* SkGmacMcHash */
9759-
9760+#endif /* YUKON */
9761 #endif /* !SK_ADDR_CHEAT */
9762
9763 /******************************************************************************
9764@@ -647,23 +637,27 @@
9765 int Flags) /* permanent/non-permanent */
9766 {
9767 int ReturnCode;
9768-
9769+
9770 if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
9771 return (SK_ADDR_ILLEGAL_PORT);
9772 }
9773-
9774+
9775 if (pAC->GIni.GIGenesis) {
9776+#ifdef GENESIS
9777 ReturnCode = SkAddrXmacMcAdd(pAC, IoC, PortNumber, pMc, Flags);
9778+#endif
9779 }
9780 else {
9781+#ifdef YUKON
9782 ReturnCode = SkAddrGmacMcAdd(pAC, IoC, PortNumber, pMc, Flags);
9783+#endif
9784 }
9785
9786 return (ReturnCode);
9787
9788 } /* SkAddrMcAdd */
9789
9790-
9791+#ifdef GENESIS
9792 /******************************************************************************
9793 *
9794 * SkAddrXmacMcAdd - add a multicast address to a port
9795@@ -687,7 +681,7 @@
9796 * SK_MC_ILLEGAL_ADDRESS
9797 * SK_MC_RLMT_OVERFLOW
9798 */
9799-static int SkAddrXmacMcAdd(
9800+int SkAddrXmacMcAdd(
9801 SK_AC *pAC, /* adapter context */
9802 SK_IOC IoC, /* I/O context */
9803 SK_U32 PortNumber, /* Port Number */
9804@@ -708,7 +702,7 @@
9805 return (SK_MC_RLMT_OVERFLOW);
9806 }
9807 #endif /* DEBUG */
9808-
9809+
9810 if (pAC->Addr.Port[PortNumber].NextExactMatchRlmt >
9811 SK_ADDR_LAST_MATCH_RLMT) {
9812 return (SK_MC_RLMT_OVERFLOW);
9813@@ -729,7 +723,7 @@
9814 return (SK_MC_RLMT_OVERFLOW);
9815 }
9816 #endif /* DEBUG */
9817-
9818+
9819 if (pAC->Addr.Port[PortNumber].NextExactMatchDrv <= SK_ADDR_LAST_MATCH_DRV) {
9820
9821 /* Set exact match entry. */
9822@@ -773,8 +767,9 @@
9823 }
9824
9825 } /* SkAddrXmacMcAdd */
9826+#endif /* GENESIS */
9827
9828-
9829+#ifdef YUKON
9830 /******************************************************************************
9831 *
9832 * SkAddrGmacMcAdd - add a multicast address to a port
9833@@ -793,7 +788,7 @@
9834 * SK_MC_FILTERING_INEXACT
9835 * SK_MC_ILLEGAL_ADDRESS
9836 */
9837-static int SkAddrGmacMcAdd(
9838+int SkAddrGmacMcAdd(
9839 SK_AC *pAC, /* adapter context */
9840 SK_IOC IoC, /* I/O context */
9841 SK_U32 PortNumber, /* Port Number */
9842@@ -804,28 +799,29 @@
9843 #ifndef SK_ADDR_CHEAT
9844 SK_U32 HashBit;
9845 #endif /* !defined(SK_ADDR_CHEAT) */
9846-
9847+
9848 if (!(pMc->a[0] & SK_MC_BIT)) {
9849 /* Hashing only possible with multicast addresses */
9850 return (SK_MC_ILLEGAL_ADDRESS);
9851 }
9852-
9853+
9854 #ifndef SK_ADDR_CHEAT
9855-
9856+
9857 /* Compute hash value of address. */
9858 HashBit = SkGmacMcHash(&pMc->a[0]);
9859-
9860+
9861 if (Flags & SK_ADDR_PERMANENT) { /* permanent => RLMT */
9862-
9863+
9864 /* Add bit to InexactRlmtFilter. */
9865 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[HashBit / 8] |=
9866 1 << (HashBit % 8);
9867-
9868+
9869 /* Copy bit to InexactFilter. */
9870 for (i = 0; i < 8; i++) {
9871 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |=
9872 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[i];
9873 }
9874+
9875 #ifdef DEBUG
9876 SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
9877 ("GMAC InexactRlmtFilter: %02X %02X %02X %02X %02X %02X %02X %02X\n",
9878@@ -836,20 +832,21 @@
9879 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[4],
9880 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[5],
9881 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[6],
9882- pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[7]))
9883+ pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[7]));
9884 #endif /* DEBUG */
9885 }
9886 else { /* not permanent => DRV */
9887-
9888+
9889 /* Add bit to InexactDrvFilter. */
9890 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[HashBit / 8] |=
9891 1 << (HashBit % 8);
9892-
9893+
9894 /* Copy bit to InexactFilter. */
9895 for (i = 0; i < 8; i++) {
9896 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |=
9897 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[i];
9898 }
9899+
9900 #ifdef DEBUG
9901 SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
9902 ("GMAC InexactDrvFilter: %02X %02X %02X %02X %02X %02X %02X %02X\n",
9903@@ -860,22 +857,22 @@
9904 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[4],
9905 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[5],
9906 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[6],
9907- pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[7]))
9908+ pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[7]));
9909 #endif /* DEBUG */
9910 }
9911-
9912+
9913 #else /* SK_ADDR_CHEAT */
9914-
9915+
9916 /* Set all bits in InexactFilter. */
9917 for (i = 0; i < 8; i++) {
9918 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] = 0xFF;
9919 }
9920 #endif /* SK_ADDR_CHEAT */
9921-
9922+
9923 return (SK_MC_FILTERING_INEXACT);
9924-
9925-} /* SkAddrGmacMcAdd */
9926
9927+} /* SkAddrGmacMcAdd */
9928+#endif /* YUKON */
9929 #endif /* !SK_SLIM */
9930
9931 /******************************************************************************
9932@@ -907,7 +904,8 @@
9933 SK_IOC IoC, /* I/O context */
9934 SK_U32 PortNumber) /* Port Number */
9935 {
9936- int ReturnCode = 0;
9937+ int ReturnCode = SK_ADDR_ILLEGAL_PORT;
9938+
9939 #if (!defined(SK_SLIM) || defined(DEBUG))
9940 if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
9941 return (SK_ADDR_ILLEGAL_PORT);
9942@@ -952,7 +950,7 @@
9943 * SK_MC_FILTERING_INEXACT
9944 * SK_ADDR_ILLEGAL_PORT
9945 */
9946-static int SkAddrXmacMcUpdate(
9947+int SkAddrXmacMcUpdate(
9948 SK_AC *pAC, /* adapter context */
9949 SK_IOC IoC, /* I/O context */
9950 SK_U32 PortNumber) /* Port Number */
9951@@ -963,13 +961,13 @@
9952 SK_ADDR_PORT *pAPort;
9953
9954 SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
9955- ("SkAddrXmacMcUpdate on Port %u.\n", PortNumber))
9956-
9957+ ("SkAddrXmacMcUpdate on Port %u.\n", PortNumber));
9958+
9959 pAPort = &pAC->Addr.Port[PortNumber];
9960
9961 #ifdef DEBUG
9962 SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
9963- ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber]))
9964+ ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber]));
9965 #endif /* DEBUG */
9966
9967 /* Start with 0 to also program the logical MAC address. */
9968@@ -981,7 +979,7 @@
9969
9970 /* Clear other permanent exact match addresses on XMAC */
9971 if (pAPort->NextExactMatchRlmt <= SK_ADDR_LAST_MATCH_RLMT) {
9972-
9973+
9974 SkXmClrExactAddr(pAC, IoC, PortNumber, pAPort->NextExactMatchRlmt,
9975 SK_ADDR_LAST_MATCH_RLMT);
9976 }
9977@@ -993,7 +991,7 @@
9978
9979 /* Clear other non-permanent exact match addresses on XMAC */
9980 if (pAPort->NextExactMatchDrv <= SK_ADDR_LAST_MATCH_DRV) {
9981-
9982+
9983 SkXmClrExactAddr(pAC, IoC, PortNumber, pAPort->NextExactMatchDrv,
9984 SK_ADDR_LAST_MATCH_DRV);
9985 }
9986@@ -1003,18 +1001,18 @@
9987 }
9988
9989 if (pAPort->PromMode & SK_PROM_MODE_ALL_MC) {
9990-
9991+
9992 /* Set all bits in 64-bit hash register. */
9993 XM_OUTHASH(IoC, PortNumber, XM_HSM, &OnesHash);
9994-
9995+
9996 /* Enable Hashing */
9997 SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
9998 }
9999 else if (Inexact != 0) {
10000-
10001+
10002 /* Set 64-bit hash register to InexactFilter. */
10003 XM_OUTHASH(IoC, PortNumber, XM_HSM, &pAPort->InexactFilter.Bytes[0]);
10004-
10005+
10006 /* Enable Hashing */
10007 SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
10008 }
10009@@ -1029,7 +1027,7 @@
10010
10011 /* Set port's current physical MAC address. */
10012 OutAddr = (SK_U16 *) &pAPort->CurrentMacAddress.a[0];
10013-
10014+
10015 XM_OUTADDR(IoC, PortNumber, XM_SA, OutAddr);
10016
10017 #ifdef xDEBUG
10018@@ -1039,9 +1037,9 @@
10019
10020 /* Get exact match address i from port PortNumber. */
10021 InAddr = (SK_U16 *) &InAddr8[0];
10022-
10023+
10024 XM_INADDR(IoC, PortNumber, XM_EXM(i), InAddr);
10025-
10026+
10027 SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
10028 ("SkAddrXmacMcUpdate: MC address %d on Port %u: ",
10029 "%02x %02x %02x %02x %02x %02x -- %02x %02x %02x %02x %02x %02x\n",
10030@@ -1058,7 +1056,7 @@
10031 pAPort->Exact[i].a[2],
10032 pAPort->Exact[i].a[3],
10033 pAPort->Exact[i].a[4],
10034- pAPort->Exact[i].a[5]))
10035+ pAPort->Exact[i].a[5]));
10036 }
10037 #endif /* DEBUG */
10038
10039@@ -1069,7 +1067,7 @@
10040 else {
10041 return (SK_MC_FILTERING_INEXACT);
10042 }
10043-
10044+
10045 } /* SkAddrXmacMcUpdate */
10046
10047 #endif /* GENESIS */
10048@@ -1097,7 +1095,7 @@
10049 * SK_MC_FILTERING_INEXACT
10050 * SK_ADDR_ILLEGAL_PORT
10051 */
10052-static int SkAddrGmacMcUpdate(
10053+int SkAddrGmacMcUpdate(
10054 SK_AC *pAC, /* adapter context */
10055 SK_IOC IoC, /* I/O context */
10056 SK_U32 PortNumber) /* Port Number */
10057@@ -1110,37 +1108,37 @@
10058 SK_ADDR_PORT *pAPort;
10059
10060 SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
10061- ("SkAddrGmacMcUpdate on Port %u.\n", PortNumber))
10062-
10063+ ("SkAddrGmacMcUpdate on Port %u.\n", PortNumber));
10064+
10065 pAPort = &pAC->Addr.Port[PortNumber];
10066
10067 #ifdef DEBUG
10068 SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
10069- ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber]))
10070+ ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber]));
10071 #endif /* DEBUG */
10072-
10073+
10074 #ifndef SK_SLIM
10075 for (Inexact = 0, i = 0; i < 8; i++) {
10076 Inexact |= pAPort->InexactFilter.Bytes[i];
10077 }
10078-
10079+
10080 /* Set 64-bit hash register to InexactFilter. */
10081 GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1,
10082 &pAPort->InexactFilter.Bytes[0]);
10083-
10084- if (pAPort->PromMode & SK_PROM_MODE_ALL_MC) {
10085-
10086+
10087+ if (pAPort->PromMode & SK_PROM_MODE_ALL_MC) {
10088+
10089 /* Set all bits in 64-bit hash register. */
10090 GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1, &OnesHash);
10091-
10092+
10093 /* Enable Hashing */
10094 SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
10095 }
10096- else {
10097+ else {
10098 /* Enable Hashing. */
10099 SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
10100 }
10101-
10102+
10103 if (pAPort->PromMode != SK_PROM_MODE_NONE) {
10104 (void) SkAddrGmacPromiscuousChange(pAC, IoC, PortNumber, pAPort->PromMode);
10105 }
10106@@ -1151,19 +1149,19 @@
10107
10108 /* Enable Hashing */
10109 SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
10110-
10111+
10112 (void) SkAddrGmacPromiscuousChange(pAC, IoC, PortNumber, pAPort->PromMode);
10113-
10114+
10115 #endif /* SK_SLIM */
10116-
10117+
10118 /* Set port's current physical MAC address. */
10119 OutAddr = (SK_U16 *) &pAPort->CurrentMacAddress.a[0];
10120 GM_OUTADDR(IoC, PortNumber, GM_SRC_ADDR_1L, OutAddr);
10121-
10122+
10123 /* Set port's current logical MAC address. */
10124 OutAddr = (SK_U16 *) &pAPort->Exact[0].a[0];
10125 GM_OUTADDR(IoC, PortNumber, GM_SRC_ADDR_2L, OutAddr);
10126-
10127+
10128 #ifdef DEBUG
10129 SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
10130 ("SkAddrGmacMcUpdate: Permanent Physical MAC Address: %02X %02X %02X %02X %02X %02X\n",
10131@@ -1172,8 +1170,8 @@
10132 pAPort->Exact[0].a[2],
10133 pAPort->Exact[0].a[3],
10134 pAPort->Exact[0].a[4],
10135- pAPort->Exact[0].a[5]))
10136-
10137+ pAPort->Exact[0].a[5]));
10138+
10139 SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
10140 ("SkAddrGmacMcUpdate: Physical MAC Address: %02X %02X %02X %02X %02X %02X\n",
10141 pAPort->CurrentMacAddress.a[0],
10142@@ -1181,9 +1179,9 @@
10143 pAPort->CurrentMacAddress.a[2],
10144 pAPort->CurrentMacAddress.a[3],
10145 pAPort->CurrentMacAddress.a[4],
10146- pAPort->CurrentMacAddress.a[5]))
10147+ pAPort->CurrentMacAddress.a[5]));
10148 #endif /* DEBUG */
10149-
10150+
10151 #ifndef SK_SLIM
10152 /* Determine return value. */
10153 if (Inexact == 0 && pAPort->PromMode == 0) {
10154@@ -1195,7 +1193,7 @@
10155 #else /* SK_SLIM */
10156 return (SK_MC_FILTERING_INEXACT);
10157 #endif /* SK_SLIM */
10158-
10159+
10160 } /* SkAddrGmacMcUpdate */
10161
10162 #endif /* YUKON */
10163@@ -1290,26 +1288,46 @@
10164 (void) SkAddrMcUpdate(pAC, IoC, PortNumber);
10165 }
10166 else if (Flags & SK_ADDR_PHYSICAL_ADDRESS) { /* Physical MAC address. */
10167- if (SK_ADDR_EQUAL(pNewAddr->a,
10168- pAC->Addr.Net[NetNumber].CurrentMacAddress.a)) {
10169- return (SK_ADDR_DUPLICATE_ADDRESS);
10170- }
10171-
10172 for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) {
10173 if (!pAC->Addr.Port[i].CurrentMacAddressSet) {
10174 return (SK_ADDR_TOO_EARLY);
10175 }
10176+ }
10177
10178+ /*
10179+ * In dual net mode it should be possible to set all MAC
10180+ * addresses independently. Therefore the equality checks
10181+ * against the locical address of the same port and the
10182+ * physical address of the other port are suppressed here.
10183+ */
10184+#ifndef SK_NO_RLMT
10185+ if (pAC->Rlmt.NumNets == 1) {
10186+#endif /* SK_NO_RLMT */
10187 if (SK_ADDR_EQUAL(pNewAddr->a,
10188- pAC->Addr.Port[i].CurrentMacAddress.a)) {
10189- if (i == PortNumber) {
10190- return (SK_ADDR_SUCCESS);
10191- }
10192- else {
10193- return (SK_ADDR_DUPLICATE_ADDRESS);
10194+ pAC->Addr.Net[NetNumber].CurrentMacAddress.a)) {
10195+ return (SK_ADDR_DUPLICATE_ADDRESS);
10196+ }
10197+
10198+ for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) {
10199+ if (SK_ADDR_EQUAL(pNewAddr->a,
10200+ pAC->Addr.Port[i].CurrentMacAddress.a)) {
10201+ if (i == PortNumber) {
10202+ return (SK_ADDR_SUCCESS);
10203+ }
10204+ else {
10205+ return (SK_ADDR_DUPLICATE_ADDRESS);
10206+ }
10207 }
10208 }
10209+#ifndef SK_NO_RLMT
10210 }
10211+ else {
10212+ if (SK_ADDR_EQUAL(pNewAddr->a,
10213+ pAC->Addr.Port[PortNumber].CurrentMacAddress.a)) {
10214+ return (SK_ADDR_SUCCESS);
10215+ }
10216+ }
10217+#endif /* SK_NO_RLMT */
10218
10219 pAC->Addr.Port[PortNumber].PreviousMacAddress =
10220 pAC->Addr.Port[PortNumber].CurrentMacAddress;
10221@@ -1340,18 +1358,32 @@
10222 pAC->Addr.Net[NetNumber].CurrentMacAddress.a)) {
10223 return (SK_ADDR_SUCCESS);
10224 }
10225-
10226+
10227 for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) {
10228 if (!pAC->Addr.Port[i].CurrentMacAddressSet) {
10229 return (SK_ADDR_TOO_EARLY);
10230 }
10231+ }
10232
10233- if (SK_ADDR_EQUAL(pNewAddr->a,
10234- pAC->Addr.Port[i].CurrentMacAddress.a)) {
10235- return (SK_ADDR_DUPLICATE_ADDRESS);
10236+ /*
10237+ * In dual net mode on Yukon-2 adapters the physical address
10238+ * of port 0 and the logical address of port 1 are equal - in
10239+ * this case the equality check of the physical address leads
10240+ * to an error and is suppressed here.
10241+ */
10242+#ifndef SK_NO_RLMT
10243+ if (pAC->Rlmt.NumNets == 1) {
10244+#endif /* SK_NO_RLMT */
10245+ for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) {
10246+ if (SK_ADDR_EQUAL(pNewAddr->a,
10247+ pAC->Addr.Port[i].CurrentMacAddress.a)) {
10248+ return (SK_ADDR_DUPLICATE_ADDRESS);
10249+ }
10250 }
10251+#ifndef SK_NO_RLMT
10252 }
10253-
10254+#endif /* SK_NO_RLMT */
10255+
10256 /*
10257 * In case that the physical and the logical MAC addresses are equal
10258 * we must also change the physical MAC address here.
10259@@ -1360,11 +1392,11 @@
10260 */
10261 if (SK_ADDR_EQUAL(pAC->Addr.Port[PortNumber].CurrentMacAddress.a,
10262 pAC->Addr.Port[PortNumber].Exact[0].a)) {
10263-
10264+
10265 pAC->Addr.Port[PortNumber].PreviousMacAddress =
10266 pAC->Addr.Port[PortNumber].CurrentMacAddress;
10267 pAC->Addr.Port[PortNumber].CurrentMacAddress = *pNewAddr;
10268-
10269+
10270 #ifndef SK_NO_RLMT
10271 /* Report address change to RLMT. */
10272 Para.Para32[0] = PortNumber;
10273@@ -1372,7 +1404,7 @@
10274 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_PORT_ADDR, Para);
10275 #endif /* !SK_NO_RLMT */
10276 }
10277-
10278+
10279 #ifndef SK_NO_RLMT
10280 /* Set PortNumber to number of net's active port. */
10281 PortNumber = pAC->Rlmt.Net[NetNumber].
10282@@ -1388,8 +1420,8 @@
10283 pAC->Addr.Net[NetNumber].PermanentMacAddress.a[2],
10284 pAC->Addr.Net[NetNumber].PermanentMacAddress.a[3],
10285 pAC->Addr.Net[NetNumber].PermanentMacAddress.a[4],
10286- pAC->Addr.Net[NetNumber].PermanentMacAddress.a[5]))
10287-
10288+ pAC->Addr.Net[NetNumber].PermanentMacAddress.a[5]));
10289+
10290 SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
10291 ("SkAddrOverride: New logical MAC Address: %02X %02X %02X %02X %02X %02X\n",
10292 pAC->Addr.Net[NetNumber].CurrentMacAddress.a[0],
10293@@ -1397,17 +1429,16 @@
10294 pAC->Addr.Net[NetNumber].CurrentMacAddress.a[2],
10295 pAC->Addr.Net[NetNumber].CurrentMacAddress.a[3],
10296 pAC->Addr.Net[NetNumber].CurrentMacAddress.a[4],
10297- pAC->Addr.Net[NetNumber].CurrentMacAddress.a[5]))
10298+ pAC->Addr.Net[NetNumber].CurrentMacAddress.a[5]));
10299 #endif /* DEBUG */
10300
10301- /* Write address to first exact match entry of active port. */
10302- (void) SkAddrMcUpdate(pAC, IoC, PortNumber);
10303+ /* Write address to first exact match entry of active port. */
10304+ (void)SkAddrMcUpdate(pAC, IoC, PortNumber);
10305 }
10306
10307 return (SK_ADDR_SUCCESS);
10308-
10309-} /* SkAddrOverride */
10310
10311+} /* SkAddrOverride */
10312
10313 #endif /* SK_NO_MAO */
10314
10315@@ -1439,7 +1470,8 @@
10316 SK_U32 PortNumber, /* port whose promiscuous mode changes */
10317 int NewPromMode) /* new promiscuous mode */
10318 {
10319- int ReturnCode = 0;
10320+ int ReturnCode = SK_ADDR_ILLEGAL_PORT;
10321+
10322 #if (!defined(SK_SLIM) || defined(DEBUG))
10323 if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
10324 return (SK_ADDR_ILLEGAL_PORT);
10325@@ -1483,7 +1515,7 @@
10326 * SK_ADDR_SUCCESS
10327 * SK_ADDR_ILLEGAL_PORT
10328 */
10329-static int SkAddrXmacPromiscuousChange(
10330+int SkAddrXmacPromiscuousChange(
10331 SK_AC *pAC, /* adapter context */
10332 SK_IOC IoC, /* I/O context */
10333 SK_U32 PortNumber, /* port whose promiscuous mode changes */
10334@@ -1504,17 +1536,18 @@
10335 /* Promiscuous mode! */
10336 CurPromMode |= SK_PROM_MODE_LLC;
10337 }
10338-
10339+
10340 for (Inexact = 0xFF, i = 0; i < 8; i++) {
10341 Inexact &= pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i];
10342 }
10343+
10344 if (Inexact == 0xFF) {
10345 CurPromMode |= (pAC->Addr.Port[PortNumber].PromMode & SK_PROM_MODE_ALL_MC);
10346 }
10347 else {
10348 /* Get InexactModeBit (bit XM_MD_ENA_HASH in mode register) */
10349 XM_IN16(IoC, PortNumber, XM_MODE, &LoMode);
10350-
10351+
10352 InexactModeBit = (LoMode & XM_MD_ENA_HASH) != 0;
10353
10354 /* Read 64-bit hash register from XMAC */
10355@@ -1537,7 +1570,7 @@
10356
10357 if ((NewPromMode & SK_PROM_MODE_ALL_MC) &&
10358 !(CurPromMode & SK_PROM_MODE_ALL_MC)) { /* All MC. */
10359-
10360+
10361 /* Set all bits in 64-bit hash register. */
10362 XM_OUTHASH(IoC, PortNumber, XM_HSM, &OnesHash);
10363
10364@@ -1573,9 +1606,9 @@
10365 /* Clear Promiscuous Mode */
10366 SkMacPromiscMode(pAC, IoC, (int) PortNumber, SK_FALSE);
10367 }
10368-
10369+
10370 return (SK_ADDR_SUCCESS);
10371-
10372+
10373 } /* SkAddrXmacPromiscuousChange */
10374
10375 #endif /* GENESIS */
10376@@ -1600,7 +1633,7 @@
10377 * SK_ADDR_SUCCESS
10378 * SK_ADDR_ILLEGAL_PORT
10379 */
10380-static int SkAddrGmacPromiscuousChange(
10381+int SkAddrGmacPromiscuousChange(
10382 SK_AC *pAC, /* adapter context */
10383 SK_IOC IoC, /* I/O context */
10384 SK_U32 PortNumber, /* port whose promiscuous mode changes */
10385@@ -1622,22 +1655,25 @@
10386 CurPromMode |= (pAC->Addr.Port[PortNumber].PromMode & SK_PROM_MODE_ALL_MC);
10387 }
10388
10389+ /* dummy read after GM_IN16() */
10390+ SK_IN16(IoC, B0_RAP, &ReceiveControl);
10391+
10392 pAC->Addr.Port[PortNumber].PromMode = NewPromMode;
10393
10394 if (NewPromMode == CurPromMode) {
10395 return (SK_ADDR_SUCCESS);
10396 }
10397-
10398+
10399 if ((NewPromMode & SK_PROM_MODE_ALL_MC) &&
10400 !(CurPromMode & SK_PROM_MODE_ALL_MC)) { /* All MC */
10401-
10402+
10403 /* Set all bits in 64-bit hash register. */
10404 GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1, &OnesHash);
10405-
10406+
10407 /* Enable Hashing */
10408 SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
10409 }
10410-
10411+
10412 if ((CurPromMode & SK_PROM_MODE_ALL_MC) &&
10413 !(NewPromMode & SK_PROM_MODE_ALL_MC)) { /* Norm. MC */
10414
10415@@ -1651,19 +1687,19 @@
10416
10417 if ((NewPromMode & SK_PROM_MODE_LLC) &&
10418 !(CurPromMode & SK_PROM_MODE_LLC)) { /* Prom. LLC */
10419-
10420+
10421 /* Set the MAC to Promiscuous Mode. */
10422 SkMacPromiscMode(pAC, IoC, (int) PortNumber, SK_TRUE);
10423 }
10424 else if ((CurPromMode & SK_PROM_MODE_LLC) &&
10425 !(NewPromMode & SK_PROM_MODE_LLC)) { /* Norm. LLC */
10426-
10427+
10428 /* Clear Promiscuous Mode. */
10429 SkMacPromiscMode(pAC, IoC, (int) PortNumber, SK_FALSE);
10430 }
10431
10432 return (SK_ADDR_SUCCESS);
10433-
10434+
10435 } /* SkAddrGmacPromiscuousChange */
10436
10437 #endif /* YUKON */
10438@@ -1735,33 +1771,33 @@
10439 pAC->Addr.Port[ToPortNumber].InexactFilter.Bytes[i];
10440 pAC->Addr.Port[ToPortNumber].InexactFilter.Bytes[i] = Byte;
10441 }
10442-
10443+
10444 i = pAC->Addr.Port[FromPortNumber].PromMode;
10445 pAC->Addr.Port[FromPortNumber].PromMode = pAC->Addr.Port[ToPortNumber].PromMode;
10446 pAC->Addr.Port[ToPortNumber].PromMode = i;
10447-
10448+
10449 if (pAC->GIni.GIGenesis) {
10450 DWord = pAC->Addr.Port[FromPortNumber].FirstExactMatchRlmt;
10451 pAC->Addr.Port[FromPortNumber].FirstExactMatchRlmt =
10452 pAC->Addr.Port[ToPortNumber].FirstExactMatchRlmt;
10453 pAC->Addr.Port[ToPortNumber].FirstExactMatchRlmt = DWord;
10454-
10455+
10456 DWord = pAC->Addr.Port[FromPortNumber].NextExactMatchRlmt;
10457 pAC->Addr.Port[FromPortNumber].NextExactMatchRlmt =
10458 pAC->Addr.Port[ToPortNumber].NextExactMatchRlmt;
10459 pAC->Addr.Port[ToPortNumber].NextExactMatchRlmt = DWord;
10460-
10461+
10462 DWord = pAC->Addr.Port[FromPortNumber].FirstExactMatchDrv;
10463 pAC->Addr.Port[FromPortNumber].FirstExactMatchDrv =
10464 pAC->Addr.Port[ToPortNumber].FirstExactMatchDrv;
10465 pAC->Addr.Port[ToPortNumber].FirstExactMatchDrv = DWord;
10466-
10467+
10468 DWord = pAC->Addr.Port[FromPortNumber].NextExactMatchDrv;
10469 pAC->Addr.Port[FromPortNumber].NextExactMatchDrv =
10470 pAC->Addr.Port[ToPortNumber].NextExactMatchDrv;
10471 pAC->Addr.Port[ToPortNumber].NextExactMatchDrv = DWord;
10472 }
10473-
10474+
10475 /* CAUTION: Solution works if only ports of one adapter are in use. */
10476 for (i = 0; (SK_U32) i < pAC->Rlmt.Net[pAC->Rlmt.Port[ToPortNumber].
10477 Net->NetNumber].NumPorts; i++) {
10478@@ -1772,12 +1808,12 @@
10479 /* 20001207 RA: Was "ToPortNumber;". */
10480 }
10481 }
10482-
10483+
10484 (void) SkAddrMcUpdate(pAC, IoC, FromPortNumber);
10485 (void) SkAddrMcUpdate(pAC, IoC, ToPortNumber);
10486
10487 return (SK_ADDR_SUCCESS);
10488-
10489+
10490 } /* SkAddrSwap */
10491
10492 #endif /* !SK_SLIM */
10493diff -urN linux-2.6.17.orig/drivers/net/sk98lin/skcsum.c linux-2.6.17/drivers/net/sk98lin/skcsum.c
10494--- linux-2.6.17.orig/drivers/net/sk98lin/skcsum.c 1970-01-01 01:00:00.000000000 +0100
10495+++ linux-2.6.17/drivers/net/sk98lin/skcsum.c 2006-04-27 11:43:44.000000000 +0200
10496@@ -0,0 +1,873 @@
10497+/******************************************************************************
10498+ *
10499+ * Name: skcsum.c
10500+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
10501+ * Version: $Revision$
10502+ * Date: $Date$
10503+ * Purpose: Store/verify Internet checksum in send/receive packets.
10504+ *
10505+ ******************************************************************************/
10506+
10507+/******************************************************************************
10508+ *
10509+ * LICENSE:
10510+ * (C)Copyright 1998-2003 SysKonnect GmbH.
10511+ *
10512+ * This program is free software; you can redistribute it and/or modify
10513+ * it under the terms of the GNU General Public License as published by
10514+ * the Free Software Foundation; either version 2 of the License, or
10515+ * (at your option) any later version.
10516+ *
10517+ * The information in this file is provided "AS IS" without warranty.
10518+ * /LICENSE
10519+ *
10520+ ******************************************************************************/
10521+
10522+#ifdef SK_USE_CSUM /* Check if CSUM is to be used. */
10523+
10524+#ifndef lint
10525+static const char SysKonnectFileId[] =
10526+ "@(#) $Id$ (C) SysKonnect.";
10527+#endif /* !lint */
10528+
10529+/******************************************************************************
10530+ *
10531+ * Description:
10532+ *
10533+ * This is the "GEnesis" common module "CSUM".
10534+ *
10535+ * This module contains the code necessary to calculate, store, and verify the
10536+ * Internet Checksum of IP, TCP, and UDP frames.
10537+ *
10538+ * "GEnesis" is an abbreviation of "Gigabit Ethernet Network System in Silicon"
10539+ * and is the code name of this SysKonnect project.
10540+ *
10541+ * Compilation Options:
10542+ *
10543+ * SK_USE_CSUM - Define if CSUM is to be used. Otherwise, CSUM will be an
10544+ * empty module.
10545+ *
10546+ * SKCS_OVERWRITE_PROTO - Define to overwrite the default protocol id
10547+ * definitions. In this case, all SKCS_PROTO_xxx definitions must be made
10548+ * external.
10549+ *
10550+ * SKCS_OVERWRITE_STATUS - Define to overwrite the default return status
10551+ * definitions. In this case, all SKCS_STATUS_xxx definitions must be made
10552+ * external.
10553+ *
10554+ * Include File Hierarchy:
10555+ *
10556+ * "h/skdrv1st.h"
10557+ * "h/skcsum.h"
10558+ * "h/sktypes.h"
10559+ * "h/skqueue.h"
10560+ * "h/skdrv2nd.h"
10561+ *
10562+ ******************************************************************************/
10563+
10564+#include "h/skdrv1st.h"
10565+#include "h/skcsum.h"
10566+#include "h/skdrv2nd.h"
10567+
10568+/* defines ********************************************************************/
10569+
10570+/* The size of an Ethernet MAC header. */
10571+#define SKCS_ETHERNET_MAC_HEADER_SIZE (6+6+2)
10572+
10573+/* The size of the used topology's MAC header. */
10574+#define SKCS_MAC_HEADER_SIZE SKCS_ETHERNET_MAC_HEADER_SIZE
10575+
10576+/* The size of the IP header without any option fields. */
10577+#define SKCS_IP_HEADER_SIZE 20
10578+
10579+/*
10580+ * Field offsets within the IP header.
10581+ */
10582+
10583+/* "Internet Header Version" and "Length". */
10584+#define SKCS_OFS_IP_HEADER_VERSION_AND_LENGTH 0
10585+
10586+/* "Total Length". */
10587+#define SKCS_OFS_IP_TOTAL_LENGTH 2
10588+
10589+/* "Flags" "Fragment Offset". */
10590+#define SKCS_OFS_IP_FLAGS_AND_FRAGMENT_OFFSET 6
10591+
10592+/* "Next Level Protocol" identifier. */
10593+#define SKCS_OFS_IP_NEXT_LEVEL_PROTOCOL 9
10594+
10595+/* Source IP address. */
10596+#define SKCS_OFS_IP_SOURCE_ADDRESS 12
10597+
10598+/* Destination IP address. */
10599+#define SKCS_OFS_IP_DESTINATION_ADDRESS 16
10600+
10601+
10602+/*
10603+ * Field offsets within the UDP header.
10604+ */
10605+
10606+/* UDP checksum. */
10607+#define SKCS_OFS_UDP_CHECKSUM 6
10608+
10609+/* IP "Next Level Protocol" identifiers (see RFC 790). */
10610+#define SKCS_PROTO_ID_TCP 6 /* Transport Control Protocol */
10611+#define SKCS_PROTO_ID_UDP 17 /* User Datagram Protocol */
10612+
10613+/* IP "Don't Fragment" bit. */
10614+#define SKCS_IP_DONT_FRAGMENT SKCS_HTON16(0x4000)
10615+
10616+/* Add a byte offset to a pointer. */
10617+#define SKCS_IDX(pPtr, Ofs) ((void *) ((char *) (pPtr) + (Ofs)))
10618+
10619+/*
10620+ * Macros that convert host to network representation and vice versa, i.e.
10621+ * little/big endian conversion on little endian machines only.
10622+ */
10623+#ifdef SK_LITTLE_ENDIAN
10624+#define SKCS_HTON16(Val16) (((unsigned) (Val16) >> 8) | (((Val16) & 0xff) << 8))
10625+#endif /* SK_LITTLE_ENDIAN */
10626+#ifdef SK_BIG_ENDIAN
10627+#define SKCS_HTON16(Val16) (Val16)
10628+#endif /* SK_BIG_ENDIAN */
10629+#define SKCS_NTOH16(Val16) SKCS_HTON16(Val16)
10630+
10631+/* typedefs *******************************************************************/
10632+
10633+/* function prototypes ********************************************************/
10634+
10635+/******************************************************************************
10636+ *
10637+ * SkCsGetSendInfo - get checksum information for a send packet
10638+ *
10639+ * Description:
10640+ * Get all checksum information necessary to send a TCP or UDP packet. The
10641+ * function checks the IP header passed to it. If the high-level protocol
10642+ * is either TCP or UDP the pseudo header checksum is calculated and
10643+ * returned.
10644+ *
10645+ * The function returns the total length of the IP header (including any
10646+ * IP option fields), which is the same as the start offset of the IP data
10647+ * which in turn is the start offset of the TCP or UDP header.
10648+ *
10649+ * The function also returns the TCP or UDP pseudo header checksum, which
10650+ * should be used as the start value for the hardware checksum calculation.
10651+ * (Note that any actual pseudo header checksum can never calculate to
10652+ * zero.)
10653+ *
10654+ * Note:
10655+ * There is a bug in the GENESIS ASIC which may lead to wrong checksums.
10656+ *
10657+ * Arguments:
10658+ * pAc - A pointer to the adapter context struct.
10659+ *
10660+ * pIpHeader - Pointer to IP header. Must be at least the IP header *not*
10661+ * including any option fields, i.e. at least 20 bytes.
10662+ *
10663+ * Note: This pointer will be used to address 8-, 16-, and 32-bit
10664+ * variables with the respective alignment offsets relative to the pointer.
10665+ * Thus, the pointer should point to a 32-bit aligned address. If the
10666+ * target system cannot address 32-bit variables on non 32-bit aligned
10667+ * addresses, then the pointer *must* point to a 32-bit aligned address.
10668+ *
10669+ * pPacketInfo - A pointer to the packet information structure for this
10670+ * packet. Before calling this SkCsGetSendInfo(), the following field must
10671+ * be initialized:
10672+ *
10673+ * ProtocolFlags - Initialize with any combination of
10674+ * SKCS_PROTO_XXX bit flags. SkCsGetSendInfo() will only work on
10675+ * the protocols specified here. Any protocol(s) not specified
10676+ * here will be ignored.
10677+ *
10678+ * Note: Only one checksum can be calculated in hardware. Thus, if
10679+ * SKCS_PROTO_IP is specified in the 'ProtocolFlags',
10680+ * SkCsGetSendInfo() must calculate the IP header checksum in
10681+ * software. It might be a better idea to have the calling
10682+ * protocol stack calculate the IP header checksum.
10683+ *
10684+ * Returns: N/A
10685+ * On return, the following fields in 'pPacketInfo' may or may not have
10686+ * been filled with information, depending on the protocol(s) found in the
10687+ * packet:
10688+ *
10689+ * ProtocolFlags - Returns the SKCS_PROTO_XXX bit flags of the protocol(s)
10690+ * that were both requested by the caller and actually found in the packet.
10691+ * Protocol(s) not specified by the caller and/or not found in the packet
10692+ * will have their respective SKCS_PROTO_XXX bit flags reset.
10693+ *
10694+ * Note: For IP fragments, TCP and UDP packet information is ignored.
10695+ *
10696+ * IpHeaderLength - The total length in bytes of the complete IP header
10697+ * including any option fields is returned here. This is the start offset
10698+ * of the IP data, i.e. the TCP or UDP header if present.
10699+ *
10700+ * IpHeaderChecksum - If IP has been specified in the 'ProtocolFlags', the
10701+ * 16-bit Internet Checksum of the IP header is returned here. This value
10702+ * is to be stored into the packet's 'IP Header Checksum' field.
10703+ *
10704+ * PseudoHeaderChecksum - If this is a TCP or UDP packet and if TCP or UDP
10705+ * has been specified in the 'ProtocolFlags', the 16-bit Internet Checksum
10706+ * of the TCP or UDP pseudo header is returned here.
10707+ */
10708+void SkCsGetSendInfo(
10709+SK_AC *pAc, /* Adapter context struct. */
10710+void *pIpHeader, /* IP header. */
10711+SKCS_PACKET_INFO *pPacketInfo, /* Packet information struct. */
10712+int NetNumber) /* Net number */
10713+{
10714+ /* Internet Header Version found in IP header. */
10715+ unsigned InternetHeaderVersion;
10716+
10717+ /* Length of the IP header as found in IP header. */
10718+ unsigned IpHeaderLength;
10719+
10720+ /* Bit field specifiying the desired/found protocols. */
10721+ unsigned ProtocolFlags;
10722+
10723+ /* Next level protocol identifier found in IP header. */
10724+ unsigned NextLevelProtocol;
10725+
10726+ /* Length of IP data portion. */
10727+ unsigned IpDataLength;
10728+
10729+ /* TCP/UDP pseudo header checksum. */
10730+ unsigned long PseudoHeaderChecksum;
10731+
10732+ /* Pointer to next level protocol statistics structure. */
10733+ SKCS_PROTO_STATS *NextLevelProtoStats;
10734+
10735+ /* Temporary variable. */
10736+ unsigned Tmp;
10737+
10738+ Tmp = *(SK_U8 *)
10739+ SKCS_IDX(pIpHeader, SKCS_OFS_IP_HEADER_VERSION_AND_LENGTH);
10740+
10741+ /* Get the Internet Header Version (IHV). */
10742+ /* Note: The IHV is stored in the upper four bits. */
10743+
10744+ InternetHeaderVersion = Tmp >> 4;
10745+
10746+ /* Check the Internet Header Version. */
10747+ /* Note: We currently only support IP version 4. */
10748+
10749+ if (InternetHeaderVersion != 4) { /* IPv4? */
10750+ SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_TX,
10751+ ("Tx: Unknown Internet Header Version %u.\n",
10752+ InternetHeaderVersion));
10753+ pPacketInfo->ProtocolFlags = 0;
10754+ pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].TxUnableCts++;
10755+ return;
10756+ }
10757+
10758+ /* Get the IP header length (IHL). */
10759+ /*
10760+ * Note: The IHL is stored in the lower four bits as the number of
10761+ * 4-byte words.
10762+ */
10763+
10764+ IpHeaderLength = (Tmp & 0xf) * 4;
10765+ pPacketInfo->IpHeaderLength = IpHeaderLength;
10766+
10767+ /* Check the IP header length. */
10768+
10769+ /* 04-Aug-1998 sw - Really check the IHL? Necessary? */
10770+
10771+ if (IpHeaderLength < 5*4) {
10772+ SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_TX,
10773+ ("Tx: Invalid IP Header Length %u.\n", IpHeaderLength));
10774+ pPacketInfo->ProtocolFlags = 0;
10775+ pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].TxUnableCts++;
10776+ return;
10777+ }
10778+
10779+ /* This is an IPv4 frame with a header of valid length. */
10780+
10781+ pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].TxOkCts++;
10782+
10783+ /* Check if we should calculate the IP header checksum. */
10784+
10785+ ProtocolFlags = pPacketInfo->ProtocolFlags;
10786+
10787+ if (ProtocolFlags & SKCS_PROTO_IP) {
10788+ pPacketInfo->IpHeaderChecksum =
10789+ SkCsCalculateChecksum(pIpHeader, IpHeaderLength);
10790+ }
10791+
10792+ /* Get the next level protocol identifier. */
10793+
10794+ NextLevelProtocol =
10795+ *(SK_U8 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_NEXT_LEVEL_PROTOCOL);
10796+
10797+ /*
10798+ * Check if this is a TCP or UDP frame and if we should calculate the
10799+ * TCP/UDP pseudo header checksum.
10800+ *
10801+ * Also clear all protocol bit flags of protocols not present in the
10802+ * frame.
10803+ */
10804+
10805+ if ((ProtocolFlags & SKCS_PROTO_TCP) != 0 &&
10806+ NextLevelProtocol == SKCS_PROTO_ID_TCP) {
10807+ /* TCP/IP frame. */
10808+ ProtocolFlags &= SKCS_PROTO_TCP | SKCS_PROTO_IP;
10809+ NextLevelProtoStats =
10810+ &pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_TCP];
10811+ }
10812+ else if ((ProtocolFlags & SKCS_PROTO_UDP) != 0 &&
10813+ NextLevelProtocol == SKCS_PROTO_ID_UDP) {
10814+ /* UDP/IP frame. */
10815+ ProtocolFlags &= SKCS_PROTO_UDP | SKCS_PROTO_IP;
10816+ NextLevelProtoStats =
10817+ &pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_UDP];
10818+ }
10819+ else {
10820+ /*
10821+ * Either not a TCP or UDP frame and/or TCP/UDP processing not
10822+ * specified.
10823+ */
10824+ pPacketInfo->ProtocolFlags = ProtocolFlags & SKCS_PROTO_IP;
10825+ return;
10826+ }
10827+
10828+ /* Check if this is an IP fragment. */
10829+
10830+ /*
10831+ * Note: An IP fragment has a non-zero "Fragment Offset" field and/or
10832+ * the "More Fragments" bit set. Thus, if both the "Fragment Offset"
10833+ * and the "More Fragments" are zero, it is *not* a fragment. We can
10834+ * easily check both at the same time since they are in the same 16-bit
10835+ * word.
10836+ */
10837+
10838+ if ((*(SK_U16 *)
10839+ SKCS_IDX(pIpHeader, SKCS_OFS_IP_FLAGS_AND_FRAGMENT_OFFSET) &
10840+ ~SKCS_IP_DONT_FRAGMENT) != 0) {
10841+ /* IP fragment; ignore all other protocols. */
10842+ pPacketInfo->ProtocolFlags = ProtocolFlags & SKCS_PROTO_IP;
10843+ NextLevelProtoStats->TxUnableCts++;
10844+ return;
10845+ }
10846+
10847+ /*
10848+ * Calculate the TCP/UDP pseudo header checksum.
10849+ */
10850+
10851+ /* Get total length of IP header and data. */
10852+
10853+ IpDataLength =
10854+ *(SK_U16 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_TOTAL_LENGTH);
10855+
10856+ /* Get length of IP data portion. */
10857+
10858+ IpDataLength = SKCS_NTOH16(IpDataLength) - IpHeaderLength;
10859+
10860+ /* Calculate the sum of all pseudo header fields (16-bit). */
10861+
10862+ PseudoHeaderChecksum =
10863+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
10864+ SKCS_OFS_IP_SOURCE_ADDRESS + 0) +
10865+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
10866+ SKCS_OFS_IP_SOURCE_ADDRESS + 2) +
10867+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
10868+ SKCS_OFS_IP_DESTINATION_ADDRESS + 0) +
10869+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
10870+ SKCS_OFS_IP_DESTINATION_ADDRESS + 2) +
10871+ (unsigned long) SKCS_HTON16(NextLevelProtocol) +
10872+ (unsigned long) SKCS_HTON16(IpDataLength);
10873+
10874+ /* Add-in any carries. */
10875+
10876+ SKCS_OC_ADD(PseudoHeaderChecksum, PseudoHeaderChecksum, 0);
10877+
10878+ /* Add-in any new carry. */
10879+
10880+ SKCS_OC_ADD(pPacketInfo->PseudoHeaderChecksum, PseudoHeaderChecksum, 0);
10881+
10882+ pPacketInfo->ProtocolFlags = ProtocolFlags;
10883+ NextLevelProtoStats->TxOkCts++; /* Success. */
10884+} /* SkCsGetSendInfo */
10885+
10886+
10887+/******************************************************************************
10888+ *
10889+ * SkCsGetReceiveInfo - verify checksum information for a received packet
10890+ *
10891+ * Description:
10892+ * Verify a received frame's checksum. The function returns a status code
10893+ * reflecting the result of the verification.
10894+ *
10895+ * Note:
10896+ * Before calling this function you have to verify that the frame is
10897+ * not padded and Checksum1 and Checksum2 are bigger than 1.
10898+ *
10899+ * Arguments:
10900+ * pAc - Pointer to adapter context struct.
10901+ *
10902+ * pIpHeader - Pointer to IP header. Must be at least the length in bytes
10903+ * of the received IP header including any option fields. For UDP packets,
10904+ * 8 additional bytes are needed to access the UDP checksum.
10905+ *
10906+ * Note: The actual length of the IP header is stored in the lower four
10907+ * bits of the first octet of the IP header as the number of 4-byte words,
10908+ * so it must be multiplied by four to get the length in bytes. Thus, the
10909+ * maximum IP header length is 15 * 4 = 60 bytes.
10910+ *
10911+ * Checksum1 - The first 16-bit Internet Checksum calculated by the
10912+ * hardware starting at the offset returned by SkCsSetReceiveFlags().
10913+ *
10914+ * Checksum2 - The second 16-bit Internet Checksum calculated by the
10915+ * hardware starting at the offset returned by SkCsSetReceiveFlags().
10916+ *
10917+ * Returns:
10918+ * SKCS_STATUS_UNKNOWN_IP_VERSION - Not an IP v4 frame.
10919+ * SKCS_STATUS_IP_CSUM_ERROR - IP checksum error.
10920+ * SKCS_STATUS_IP_CSUM_ERROR_TCP - IP checksum error in TCP frame.
10921+ * SKCS_STATUS_IP_CSUM_ERROR_UDP - IP checksum error in UDP frame
10922+ * SKCS_STATUS_IP_FRAGMENT - IP fragment (IP checksum ok).
10923+ * SKCS_STATUS_IP_CSUM_OK - IP checksum ok (not a TCP or UDP frame).
10924+ * SKCS_STATUS_TCP_CSUM_ERROR - TCP checksum error (IP checksum ok).
10925+ * SKCS_STATUS_UDP_CSUM_ERROR - UDP checksum error (IP checksum ok).
10926+ * SKCS_STATUS_TCP_CSUM_OK - IP and TCP checksum ok.
10927+ * SKCS_STATUS_UDP_CSUM_OK - IP and UDP checksum ok.
10928+ * SKCS_STATUS_IP_CSUM_OK_NO_UDP - IP checksum OK and no UDP checksum.
10929+ *
10930+ * Note: If SKCS_OVERWRITE_STATUS is defined, the SKCS_STATUS_XXX values
10931+ * returned here can be defined in some header file by the module using CSUM.
10932+ * In this way, the calling module can assign return values for its own needs,
10933+ * e.g. by assigning bit flags to the individual protocols.
10934+ */
10935+SKCS_STATUS SkCsGetReceiveInfo(
10936+SK_AC *pAc, /* Adapter context struct. */
10937+void *pIpHeader, /* IP header. */
10938+unsigned Checksum1, /* Hardware checksum 1. */
10939+unsigned Checksum2, /* Hardware checksum 2. */
10940+int NetNumber) /* Net number */
10941+{
10942+ /* Internet Header Version found in IP header. */
10943+ unsigned InternetHeaderVersion;
10944+
10945+ /* Length of the IP header as found in IP header. */
10946+ unsigned IpHeaderLength;
10947+
10948+ /* Length of IP data portion. */
10949+ unsigned IpDataLength;
10950+
10951+ /* IP header checksum. */
10952+ unsigned IpHeaderChecksum;
10953+
10954+ /* IP header options checksum, if any. */
10955+ unsigned IpOptionsChecksum;
10956+
10957+ /* IP data checksum, i.e. TCP/UDP checksum. */
10958+ unsigned IpDataChecksum;
10959+
10960+ /* Next level protocol identifier found in IP header. */
10961+ unsigned NextLevelProtocol;
10962+
10963+ /* The checksum of the "next level protocol", i.e. TCP or UDP. */
10964+ unsigned long NextLevelProtocolChecksum;
10965+
10966+ /* Pointer to next level protocol statistics structure. */
10967+ SKCS_PROTO_STATS *NextLevelProtoStats;
10968+
10969+ /* Temporary variable. */
10970+ unsigned Tmp;
10971+
10972+ Tmp = *(SK_U8 *)
10973+ SKCS_IDX(pIpHeader, SKCS_OFS_IP_HEADER_VERSION_AND_LENGTH);
10974+
10975+ /* Get the Internet Header Version (IHV). */
10976+ /* Note: The IHV is stored in the upper four bits. */
10977+
10978+ InternetHeaderVersion = Tmp >> 4;
10979+
10980+ /* Check the Internet Header Version. */
10981+ /* Note: We currently only support IP version 4. */
10982+
10983+ if (InternetHeaderVersion != 4) { /* IPv4? */
10984+ SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_RX,
10985+ ("Rx: Unknown Internet Header Version %u.\n",
10986+ InternetHeaderVersion));
10987+ pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxUnableCts++;
10988+ return (SKCS_STATUS_UNKNOWN_IP_VERSION);
10989+ }
10990+
10991+ /* Get the IP header length (IHL). */
10992+ /*
10993+ * Note: The IHL is stored in the lower four bits as the number of
10994+ * 4-byte words.
10995+ */
10996+
10997+ IpHeaderLength = (Tmp & 0xf) * 4;
10998+
10999+ /* Check the IP header length. */
11000+
11001+ /* 04-Aug-1998 sw - Really check the IHL? Necessary? */
11002+
11003+ if (IpHeaderLength < 5*4) {
11004+ SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_RX,
11005+ ("Rx: Invalid IP Header Length %u.\n", IpHeaderLength));
11006+ pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxErrCts++;
11007+ return (SKCS_STATUS_IP_CSUM_ERROR);
11008+ }
11009+
11010+ /* This is an IPv4 frame with a header of valid length. */
11011+
11012+ /* Get the IP header and data checksum. */
11013+
11014+ IpDataChecksum = Checksum2;
11015+
11016+ /*
11017+ * The IP header checksum is calculated as follows:
11018+ *
11019+ * IpHeaderChecksum = Checksum1 - Checksum2
11020+ */
11021+
11022+ SKCS_OC_SUB(IpHeaderChecksum, Checksum1, Checksum2);
11023+
11024+ /* Check if any IP header options. */
11025+
11026+ if (IpHeaderLength > SKCS_IP_HEADER_SIZE) {
11027+
11028+ /* Get the IP options checksum. */
11029+
11030+ IpOptionsChecksum = SkCsCalculateChecksum(
11031+ SKCS_IDX(pIpHeader, SKCS_IP_HEADER_SIZE),
11032+ IpHeaderLength - SKCS_IP_HEADER_SIZE);
11033+
11034+ /* Adjust the IP header and IP data checksums. */
11035+
11036+ SKCS_OC_ADD(IpHeaderChecksum, IpHeaderChecksum, IpOptionsChecksum);
11037+
11038+ SKCS_OC_SUB(IpDataChecksum, IpDataChecksum, IpOptionsChecksum);
11039+ }
11040+
11041+ /*
11042+ * Check if the IP header checksum is ok.
11043+ *
11044+ * NOTE: We must check the IP header checksum even if the caller just wants
11045+ * us to check upper-layer checksums, because we cannot do any further
11046+ * processing of the packet without a valid IP checksum.
11047+ */
11048+
11049+ /* Get the next level protocol identifier. */
11050+
11051+ NextLevelProtocol = *(SK_U8 *)
11052+ SKCS_IDX(pIpHeader, SKCS_OFS_IP_NEXT_LEVEL_PROTOCOL);
11053+
11054+ if (IpHeaderChecksum != 0xffff) {
11055+ pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxErrCts++;
11056+ /* the NDIS tester wants to know the upper level protocol too */
11057+ if (NextLevelProtocol == SKCS_PROTO_ID_TCP) {
11058+ return(SKCS_STATUS_IP_CSUM_ERROR_TCP);
11059+ }
11060+ else if (NextLevelProtocol == SKCS_PROTO_ID_UDP) {
11061+ return(SKCS_STATUS_IP_CSUM_ERROR_UDP);
11062+ }
11063+ return (SKCS_STATUS_IP_CSUM_ERROR);
11064+ }
11065+
11066+ /*
11067+ * Check if this is a TCP or UDP frame and if we should calculate the
11068+ * TCP/UDP pseudo header checksum.
11069+ *
11070+ * Also clear all protocol bit flags of protocols not present in the
11071+ * frame.
11072+ */
11073+
11074+ if ((pAc->Csum.ReceiveFlags[NetNumber] & SKCS_PROTO_TCP) != 0 &&
11075+ NextLevelProtocol == SKCS_PROTO_ID_TCP) {
11076+ /* TCP/IP frame. */
11077+ NextLevelProtoStats =
11078+ &pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_TCP];
11079+ }
11080+ else if ((pAc->Csum.ReceiveFlags[NetNumber] & SKCS_PROTO_UDP) != 0 &&
11081+ NextLevelProtocol == SKCS_PROTO_ID_UDP) {
11082+ /* UDP/IP frame. */
11083+ NextLevelProtoStats =
11084+ &pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_UDP];
11085+ }
11086+ else {
11087+ /*
11088+ * Either not a TCP or UDP frame and/or TCP/UDP processing not
11089+ * specified.
11090+ */
11091+ return (SKCS_STATUS_IP_CSUM_OK);
11092+ }
11093+
11094+ /* Check if this is an IP fragment. */
11095+
11096+ /*
11097+ * Note: An IP fragment has a non-zero "Fragment Offset" field and/or
11098+ * the "More Fragments" bit set. Thus, if both the "Fragment Offset"
11099+ * and the "More Fragments" are zero, it is *not* a fragment. We can
11100+ * easily check both at the same time since they are in the same 16-bit
11101+ * word.
11102+ */
11103+
11104+ if ((*(SK_U16 *)
11105+ SKCS_IDX(pIpHeader, SKCS_OFS_IP_FLAGS_AND_FRAGMENT_OFFSET) &
11106+ ~SKCS_IP_DONT_FRAGMENT) != 0) {
11107+ /* IP fragment; ignore all other protocols. */
11108+ NextLevelProtoStats->RxUnableCts++;
11109+ return (SKCS_STATUS_IP_FRAGMENT);
11110+ }
11111+
11112+ /*
11113+ * 08-May-2000 ra
11114+ *
11115+ * From RFC 768 (UDP)
11116+ * If the computed checksum is zero, it is transmitted as all ones (the
11117+ * equivalent in one's complement arithmetic). An all zero transmitted
11118+ * checksum value means that the transmitter generated no checksum (for
11119+ * debugging or for higher level protocols that don't care).
11120+ */
11121+
11122+ if (NextLevelProtocol == SKCS_PROTO_ID_UDP &&
11123+ *(SK_U16*)SKCS_IDX(pIpHeader, IpHeaderLength + 6) == 0x0000) {
11124+
11125+ NextLevelProtoStats->RxOkCts++;
11126+
11127+ return (SKCS_STATUS_IP_CSUM_OK_NO_UDP);
11128+ }
11129+
11130+ /*
11131+ * Calculate the TCP/UDP checksum.
11132+ */
11133+
11134+ /* Get total length of IP header and data. */
11135+
11136+ IpDataLength =
11137+ *(SK_U16 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_TOTAL_LENGTH);
11138+
11139+ /* Get length of IP data portion. */
11140+
11141+ IpDataLength = SKCS_NTOH16(IpDataLength) - IpHeaderLength;
11142+
11143+ NextLevelProtocolChecksum =
11144+
11145+ /* Calculate the pseudo header checksum. */
11146+
11147+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
11148+ SKCS_OFS_IP_SOURCE_ADDRESS + 0) +
11149+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
11150+ SKCS_OFS_IP_SOURCE_ADDRESS + 2) +
11151+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
11152+ SKCS_OFS_IP_DESTINATION_ADDRESS + 0) +
11153+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
11154+ SKCS_OFS_IP_DESTINATION_ADDRESS + 2) +
11155+ (unsigned long) SKCS_HTON16(NextLevelProtocol) +
11156+ (unsigned long) SKCS_HTON16(IpDataLength) +
11157+
11158+ /* Add the TCP/UDP header checksum. */
11159+
11160+ (unsigned long) IpDataChecksum;
11161+
11162+ /* Add-in any carries. */
11163+
11164+ SKCS_OC_ADD(NextLevelProtocolChecksum, NextLevelProtocolChecksum, 0);
11165+
11166+ /* Add-in any new carry. */
11167+
11168+ SKCS_OC_ADD(NextLevelProtocolChecksum, NextLevelProtocolChecksum, 0);
11169+
11170+ /* Check if the TCP/UDP checksum is ok. */
11171+
11172+ if ((unsigned) NextLevelProtocolChecksum == 0xffff) {
11173+
11174+ /* TCP/UDP checksum ok. */
11175+
11176+ NextLevelProtoStats->RxOkCts++;
11177+
11178+ return (NextLevelProtocol == SKCS_PROTO_ID_TCP ?
11179+ SKCS_STATUS_TCP_CSUM_OK : SKCS_STATUS_UDP_CSUM_OK);
11180+ }
11181+
11182+ /* TCP/UDP checksum error. */
11183+
11184+ NextLevelProtoStats->RxErrCts++;
11185+
11186+ return (NextLevelProtocol == SKCS_PROTO_ID_TCP ?
11187+ SKCS_STATUS_TCP_CSUM_ERROR : SKCS_STATUS_UDP_CSUM_ERROR);
11188+} /* SkCsGetReceiveInfo */
11189+
11190+
11191+/******************************************************************************
11192+ *
11193+ * SkCsSetReceiveFlags - set checksum receive flags
11194+ *
11195+ * Description:
11196+ * Use this function to set the various receive flags. According to the
11197+ * protocol flags set by the caller, the start offsets within received
11198+ * packets of the two hardware checksums are returned. These offsets must
11199+ * be stored in all receive descriptors.
11200+ *
11201+ * Arguments:
11202+ * pAc - Pointer to adapter context struct.
11203+ *
11204+ * ReceiveFlags - Any combination of SK_PROTO_XXX flags of the protocols
11205+ * for which the caller wants checksum information on received frames.
11206+ *
11207+ * pChecksum1Offset - The start offset of the first receive descriptor
11208+ * hardware checksum to be calculated for received frames is returned
11209+ * here.
11210+ *
11211+ * pChecksum2Offset - The start offset of the second receive descriptor
11212+ * hardware checksum to be calculated for received frames is returned
11213+ * here.
11214+ *
11215+ * Returns: N/A
11216+ * Returns the two hardware checksum start offsets.
11217+ */
11218+void SkCsSetReceiveFlags(
11219+SK_AC *pAc, /* Adapter context struct. */
11220+unsigned ReceiveFlags, /* New receive flags. */
11221+unsigned *pChecksum1Offset, /* Offset for hardware checksum 1. */
11222+unsigned *pChecksum2Offset, /* Offset for hardware checksum 2. */
11223+int NetNumber)
11224+{
11225+ /* Save the receive flags. */
11226+
11227+ pAc->Csum.ReceiveFlags[NetNumber] = ReceiveFlags;
11228+
11229+ /* First checksum start offset is the IP header. */
11230+ *pChecksum1Offset = SKCS_MAC_HEADER_SIZE;
11231+
11232+ /*
11233+ * Second checksum start offset is the IP data. Note that this may vary
11234+ * if there are any IP header options in the actual packet.
11235+ */
11236+ *pChecksum2Offset = SKCS_MAC_HEADER_SIZE + SKCS_IP_HEADER_SIZE;
11237+} /* SkCsSetReceiveFlags */
11238+
11239+#ifndef SK_CS_CALCULATE_CHECKSUM
11240+
11241+/******************************************************************************
11242+ *
11243+ * SkCsCalculateChecksum - calculate checksum for specified data
11244+ *
11245+ * Description:
11246+ * Calculate and return the 16-bit Internet Checksum for the specified
11247+ * data.
11248+ *
11249+ * Arguments:
11250+ * pData - Pointer to data for which the checksum shall be calculated.
11251+ * Note: The pointer should be aligned on a 16-bit boundary.
11252+ *
11253+ * Length - Length in bytes of data to checksum.
11254+ *
11255+ * Returns:
11256+ * The 16-bit Internet Checksum for the specified data.
11257+ *
11258+ * Note: The checksum is calculated in the machine's natural byte order,
11259+ * i.e. little vs. big endian. Thus, the resulting checksum is different
11260+ * for the same input data on little and big endian machines.
11261+ *
11262+ * However, when written back to the network packet, the byte order is
11263+ * always in correct network order.
11264+ */
11265+unsigned SkCsCalculateChecksum(
11266+void *pData, /* Data to checksum. */
11267+unsigned Length) /* Length of data. */
11268+{
11269+ SK_U16 *pU16; /* Pointer to the data as 16-bit words. */
11270+ unsigned long Checksum; /* Checksum; must be at least 32 bits. */
11271+
11272+ /* Sum up all 16-bit words. */
11273+
11274+ pU16 = (SK_U16 *) pData;
11275+ for (Checksum = 0; Length > 1; Length -= 2) {
11276+ Checksum += *pU16++;
11277+ }
11278+
11279+ /* If this is an odd number of bytes, add-in the last byte. */
11280+
11281+ if (Length > 0) {
11282+#ifdef SK_BIG_ENDIAN
11283+ /* Add the last byte as the high byte. */
11284+ Checksum += ((unsigned) *(SK_U8 *) pU16) << 8;
11285+#else /* !SK_BIG_ENDIAN */
11286+ /* Add the last byte as the low byte. */
11287+ Checksum += *(SK_U8 *) pU16;
11288+#endif /* !SK_BIG_ENDIAN */
11289+ }
11290+
11291+ /* Add-in any carries. */
11292+
11293+ SKCS_OC_ADD(Checksum, Checksum, 0);
11294+
11295+ /* Add-in any new carry. */
11296+
11297+ SKCS_OC_ADD(Checksum, Checksum, 0);
11298+
11299+ /* Note: All bits beyond the 16-bit limit are now zero. */
11300+
11301+ return ((unsigned) Checksum);
11302+} /* SkCsCalculateChecksum */
11303+
11304+#endif /* SK_CS_CALCULATE_CHECKSUM */
11305+
11306+/******************************************************************************
11307+ *
11308+ * SkCsEvent - the CSUM event dispatcher
11309+ *
11310+ * Description:
11311+ * This is the event handler for the CSUM module.
11312+ *
11313+ * Arguments:
11314+ * pAc - Pointer to adapter context.
11315+ *
11316+ * Ioc - I/O context.
11317+ *
11318+ * Event - Event id.
11319+ *
11320+ * Param - Event dependent parameter.
11321+ *
11322+ * Returns:
11323+ * The 16-bit Internet Checksum for the specified data.
11324+ *
11325+ * Note: The checksum is calculated in the machine's natural byte order,
11326+ * i.e. little vs. big endian. Thus, the resulting checksum is different
11327+ * for the same input data on little and big endian machines.
11328+ *
11329+ * However, when written back to the network packet, the byte order is
11330+ * always in correct network order.
11331+ */
11332+int SkCsEvent(
11333+SK_AC *pAc, /* Pointer to adapter context. */
11334+SK_IOC Ioc, /* I/O context. */
11335+SK_U32 Event, /* Event id. */
11336+SK_EVPARA Param) /* Event dependent parameter. */
11337+{
11338+ int ProtoIndex;
11339+ int NetNumber;
11340+
11341+ switch (Event) {
11342+ /*
11343+ * Clear protocol statistics.
11344+ *
11345+ * Param - Protocol index, or -1 for all protocols.
11346+ * - Net number.
11347+ */
11348+ case SK_CSUM_EVENT_CLEAR_PROTO_STATS:
11349+
11350+ ProtoIndex = (int)Param.Para32[1];
11351+ NetNumber = (int)Param.Para32[0];
11352+ if (ProtoIndex < 0) { /* Clear for all protocols. */
11353+ if (NetNumber >= 0) {
11354+ SK_MEMSET(&pAc->Csum.ProtoStats[NetNumber][0], 0,
11355+ sizeof(pAc->Csum.ProtoStats[NetNumber]));
11356+ }
11357+ }
11358+ else { /* Clear for individual protocol. */
11359+ SK_MEMSET(&pAc->Csum.ProtoStats[NetNumber][ProtoIndex], 0,
11360+ sizeof(pAc->Csum.ProtoStats[NetNumber][ProtoIndex]));
11361+ }
11362+ break;
11363+ default:
11364+ break;
11365+ }
11366+ return (0); /* Success. */
11367+} /* SkCsEvent */
11368+
11369+#endif /* SK_USE_CSUM */
11370diff -urN linux-2.6.17.orig/drivers/net/sk98lin/skdim.c linux-2.6.17/drivers/net/sk98lin/skdim.c
11371--- linux-2.6.17.orig/drivers/net/sk98lin/skdim.c 2006-06-22 13:17:16.000000000 +0200
11372+++ linux-2.6.17/drivers/net/sk98lin/skdim.c 2006-04-27 11:43:45.000000000 +0200
11373@@ -1,17 +1,25 @@
11374 /******************************************************************************
11375 *
11376- * Name: skdim.c
11377- * Project: GEnesis, PCI Gigabit Ethernet Adapter
11378- * Version: $Revision$
11379- * Date: $Date$
11380- * Purpose: All functions to maintain interrupt moderation
11381+ * Name: skdim.c
11382+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
11383+ * Version: $Revision$
11384+ * Date: $Date$
11385+ * Purpose: All functions regardig interrupt moderation
11386 *
11387 ******************************************************************************/
11388
11389 /******************************************************************************
11390 *
11391 * (C)Copyright 1998-2002 SysKonnect GmbH.
11392- * (C)Copyright 2002-2003 Marvell.
11393+ * (C)Copyright 2002-2005 Marvell.
11394+ *
11395+ * Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet
11396+ * Server Adapters.
11397+ *
11398+ * Author: Ralph Roesler (rroesler@syskonnect.de)
11399+ * Mirko Lindner (mlindner@syskonnect.de)
11400+ *
11401+ * Address all question to: linux@syskonnect.de
11402 *
11403 * This program is free software; you can redistribute it and/or modify
11404 * it under the terms of the GNU General Public License as published by
11405@@ -20,723 +28,367 @@
11406 *
11407 * The information in this file is provided "AS IS" without warranty.
11408 *
11409- ******************************************************************************/
11410+ *****************************************************************************/
11411
11412-/******************************************************************************
11413- *
11414- * Description:
11415- *
11416- * This module is intended to manage the dynamic interrupt moderation on both
11417- * GEnesis and Yukon adapters.
11418- *
11419- * Include File Hierarchy:
11420- *
11421- * "skdrv1st.h"
11422- * "skdrv2nd.h"
11423- *
11424- ******************************************************************************/
11425-
11426-#ifndef lint
11427-static const char SysKonnectFileId[] =
11428- "@(#) $Id$ (C) SysKonnect.";
11429-#endif
11430-
11431-#define __SKADDR_C
11432-
11433-#ifdef __cplusplus
11434-#error C++ is not yet supported.
11435-extern "C" {
11436-#endif
11437-
11438-/*******************************************************************************
11439-**
11440-** Includes
11441-**
11442-*******************************************************************************/
11443-
11444-#ifndef __INC_SKDRV1ST_H
11445 #include "h/skdrv1st.h"
11446-#endif
11447-
11448-#ifndef __INC_SKDRV2ND_H
11449 #include "h/skdrv2nd.h"
11450-#endif
11451
11452-#include <linux/kernel_stat.h>
11453-
11454-/*******************************************************************************
11455-**
11456-** Defines
11457-**
11458-*******************************************************************************/
11459-
11460-/*******************************************************************************
11461-**
11462-** Typedefs
11463-**
11464-*******************************************************************************/
11465+/******************************************************************************
11466+ *
11467+ * Local Function Prototypes
11468+ *
11469+ *****************************************************************************/
11470
11471-/*******************************************************************************
11472-**
11473-** Local function prototypes
11474-**
11475-*******************************************************************************/
11476-
11477-static unsigned int GetCurrentSystemLoad(SK_AC *pAC);
11478-static SK_U64 GetIsrCalls(SK_AC *pAC);
11479-static SK_BOOL IsIntModEnabled(SK_AC *pAC);
11480-static void SetCurrIntCtr(SK_AC *pAC);
11481-static void EnableIntMod(SK_AC *pAC);
11482-static void DisableIntMod(SK_AC *pAC);
11483-static void ResizeDimTimerDuration(SK_AC *pAC);
11484-static void DisplaySelectedModerationType(SK_AC *pAC);
11485-static void DisplaySelectedModerationMask(SK_AC *pAC);
11486-static void DisplayDescrRatio(SK_AC *pAC);
11487+static SK_U64 getIsrCalls(SK_AC *pAC);
11488+static SK_BOOL isIntModEnabled(SK_AC *pAC);
11489+static void setCurrIntCtr(SK_AC *pAC);
11490+static void enableIntMod(SK_AC *pAC);
11491+static void disableIntMod(SK_AC *pAC);
11492
11493-/*******************************************************************************
11494-**
11495-** Global variables
11496-**
11497-*******************************************************************************/
11498+#define M_DIMINFO pAC->DynIrqModInfo
11499
11500-/*******************************************************************************
11501-**
11502-** Local variables
11503-**
11504-*******************************************************************************/
11505+/******************************************************************************
11506+ *
11507+ * Global Functions
11508+ *
11509+ *****************************************************************************/
11510
11511-/*******************************************************************************
11512-**
11513-** Global functions
11514-**
11515-*******************************************************************************/
11516+/*****************************************************************************
11517+ *
11518+ * SkDimModerate - Moderates the IRQs depending on the current needs
11519+ *
11520+ * Description:
11521+ * Moderation of IRQs depends on the number of occurred IRQs with
11522+ * respect to the previous moderation cycle.
11523+ *
11524+ * Returns: N/A
11525+ *
11526+ */
11527+void SkDimModerate(
11528+SK_AC *pAC) /* pointer to adapter control context */
11529+{
11530+ SK_U64 IsrCalls = getIsrCalls(pAC);
11531+
11532+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==> SkDimModerate\n"));
11533+
11534+ if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
11535+ if (isIntModEnabled(pAC)) {
11536+ if (IsrCalls < M_DIMINFO.MaxModIntsPerSecLowerLimit) {
11537+ disableIntMod(pAC);
11538+ }
11539+ } else {
11540+ if (IsrCalls > M_DIMINFO.MaxModIntsPerSecUpperLimit) {
11541+ enableIntMod(pAC);
11542+ }
11543+ }
11544+ }
11545+ setCurrIntCtr(pAC);
11546
11547-/*******************************************************************************
11548-** Function : SkDimModerate
11549-** Description : Called in every ISR to check if moderation is to be applied
11550-** or not for the current number of interrupts
11551-** Programmer : Ralph Roesler
11552-** Last Modified: 22-mar-03
11553-** Returns : void (!)
11554-** Notes : -
11555-*******************************************************************************/
11556-
11557-void
11558-SkDimModerate(SK_AC *pAC) {
11559- unsigned int CurrSysLoad = 0; /* expressed in percent */
11560- unsigned int LoadIncrease = 0; /* expressed in percent */
11561- SK_U64 ThresholdInts = 0;
11562- SK_U64 IsrCallsPerSec = 0;
11563+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("<== SkDimModerate\n"));
11564+}
11565
11566-#define M_DIMINFO pAC->DynIrqModInfo
11567+/*****************************************************************************
11568+ *
11569+ * SkDimStartModerationTimer - Starts the moderation timer
11570+ *
11571+ * Description:
11572+ * Dynamic interrupt moderation is regularly checked using the
11573+ * so-called moderation timer. This timer is started with this function.
11574+ *
11575+ * Returns: N/A
11576+ */
11577+void SkDimStartModerationTimer(
11578+SK_AC *pAC) /* pointer to adapter control context */
11579+{
11580+ SK_EVPARA EventParam; /* Event struct for timer event */
11581+
11582+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11583+ ("==> SkDimStartModerationTimer\n"));
11584
11585- if (!IsIntModEnabled(pAC)) {
11586- if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
11587- CurrSysLoad = GetCurrentSystemLoad(pAC);
11588- if (CurrSysLoad > 75) {
11589- /*
11590- ** More than 75% total system load! Enable the moderation
11591- ** to shield the system against too many interrupts.
11592- */
11593- EnableIntMod(pAC);
11594- } else if (CurrSysLoad > M_DIMINFO.PrevSysLoad) {
11595- LoadIncrease = (CurrSysLoad - M_DIMINFO.PrevSysLoad);
11596- if (LoadIncrease > ((M_DIMINFO.PrevSysLoad *
11597- C_INT_MOD_ENABLE_PERCENTAGE) / 100)) {
11598- if (CurrSysLoad > 10) {
11599- /*
11600- ** More than 50% increase with respect to the
11601- ** previous load of the system. Most likely this
11602- ** is due to our ISR-proc...
11603- */
11604- EnableIntMod(pAC);
11605- }
11606- }
11607- } else {
11608- /*
11609- ** Neither too much system load at all nor too much increase
11610- ** with respect to the previous system load. Hence, we can leave
11611- ** the ISR-handling like it is without enabling moderation.
11612- */
11613- }
11614- M_DIMINFO.PrevSysLoad = CurrSysLoad;
11615- }
11616- } else {
11617- if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
11618- ThresholdInts = ((M_DIMINFO.MaxModIntsPerSec *
11619- C_INT_MOD_DISABLE_PERCENTAGE) / 100);
11620- IsrCallsPerSec = GetIsrCalls(pAC);
11621- if (IsrCallsPerSec <= ThresholdInts) {
11622- /*
11623- ** The number of interrupts within the last second is
11624- ** lower than the disable_percentage of the desried
11625- ** maxrate. Therefore we can disable the moderation.
11626- */
11627- DisableIntMod(pAC);
11628- M_DIMINFO.MaxModIntsPerSec =
11629- (M_DIMINFO.MaxModIntsPerSecUpperLimit +
11630- M_DIMINFO.MaxModIntsPerSecLowerLimit) / 2;
11631- } else {
11632- /*
11633- ** The number of interrupts per sec is the same as expected.
11634- ** Evalulate the descriptor-ratio. If it has changed, a resize
11635- ** in the moderation timer might be useful
11636- */
11637- if (M_DIMINFO.AutoSizing) {
11638- ResizeDimTimerDuration(pAC);
11639- }
11640- }
11641- }
11642- }
11643-
11644- /*
11645- ** Some information to the log...
11646- */
11647- if (M_DIMINFO.DisplayStats) {
11648- DisplaySelectedModerationType(pAC);
11649- DisplaySelectedModerationMask(pAC);
11650- DisplayDescrRatio(pAC);
11651- }
11652+ if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
11653+ SK_MEMSET((char *) &EventParam, 0, sizeof(EventParam));
11654+ EventParam.Para32[0] = SK_DRV_MODERATION_TIMER;
11655+ SkTimerStart(pAC, pAC->IoBase,
11656+ &pAC->DynIrqModInfo.ModTimer,
11657+ pAC->DynIrqModInfo.DynIrqModSampleInterval * 1000000,
11658+ SKGE_DRV, SK_DRV_TIMER, EventParam);
11659+ }
11660
11661- M_DIMINFO.NbrProcessedDescr = 0;
11662- SetCurrIntCtr(pAC);
11663+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11664+ ("<== SkDimStartModerationTimer\n"));
11665 }
11666
11667-/*******************************************************************************
11668-** Function : SkDimStartModerationTimer
11669-** Description : Starts the audit-timer for the dynamic interrupt moderation
11670-** Programmer : Ralph Roesler
11671-** Last Modified: 22-mar-03
11672-** Returns : void (!)
11673-** Notes : -
11674-*******************************************************************************/
11675-
11676-void
11677-SkDimStartModerationTimer(SK_AC *pAC) {
11678- SK_EVPARA EventParam; /* Event struct for timer event */
11679-
11680- SK_MEMSET((char *) &EventParam, 0, sizeof(EventParam));
11681- EventParam.Para32[0] = SK_DRV_MODERATION_TIMER;
11682- SkTimerStart(pAC, pAC->IoBase, &pAC->DynIrqModInfo.ModTimer,
11683- SK_DRV_MODERATION_TIMER_LENGTH,
11684- SKGE_DRV, SK_DRV_TIMER, EventParam);
11685-}
11686+/*****************************************************************************
11687+ *
11688+ * SkDimEnableModerationIfNeeded - Enables or disables any moderationtype
11689+ *
11690+ * Description:
11691+ * This function effectively initializes the IRQ moderation of a network
11692+ * adapter. Depending on the configuration, this might be either static
11693+ * or dynamic. If no moderation is configured, this function will do
11694+ * nothing.
11695+ *
11696+ * Returns: N/A
11697+ */
11698+void SkDimEnableModerationIfNeeded(
11699+SK_AC *pAC) /* pointer to adapter control context */
11700+{
11701+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11702+ ("==> SkDimEnableModerationIfNeeded\n"));
11703+
11704+ if (M_DIMINFO.IntModTypeSelect != C_INT_MOD_NONE) {
11705+ if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_STATIC) {
11706+ enableIntMod(pAC);
11707+ } else { /* must be C_INT_MOD_DYNAMIC */
11708+ SkDimStartModerationTimer(pAC);
11709+ }
11710+ }
11711
11712-/*******************************************************************************
11713-** Function : SkDimEnableModerationIfNeeded
11714-** Description : Either enables or disables moderation
11715-** Programmer : Ralph Roesler
11716-** Last Modified: 22-mar-03
11717-** Returns : void (!)
11718-** Notes : This function is called when a particular adapter is opened
11719-** There is no Disable function, because when all interrupts
11720-** might be disable, the moderation timer has no meaning at all
11721-******************************************************************************/
11722-
11723-void
11724-SkDimEnableModerationIfNeeded(SK_AC *pAC) {
11725-
11726- if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_STATIC) {
11727- EnableIntMod(pAC); /* notification print in this function */
11728- } else if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
11729- SkDimStartModerationTimer(pAC);
11730- if (M_DIMINFO.DisplayStats) {
11731- printk("Dynamic moderation has been enabled\n");
11732- }
11733- } else {
11734- if (M_DIMINFO.DisplayStats) {
11735- printk("No moderation has been enabled\n");
11736- }
11737- }
11738+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11739+ ("<== SkDimEnableModerationIfNeeded\n"));
11740 }
11741
11742-/*******************************************************************************
11743-** Function : SkDimDisplayModerationSettings
11744-** Description : Displays the current settings regaring interrupt moderation
11745-** Programmer : Ralph Roesler
11746-** Last Modified: 22-mar-03
11747-** Returns : void (!)
11748-** Notes : -
11749-*******************************************************************************/
11750-
11751-void
11752-SkDimDisplayModerationSettings(SK_AC *pAC) {
11753- DisplaySelectedModerationType(pAC);
11754- DisplaySelectedModerationMask(pAC);
11755-}
11756+/*****************************************************************************
11757+ *
11758+ * SkDimDisableModeration - disables moderation if it is enabled
11759+ *
11760+ * Description:
11761+ * Disabling of the moderation requires that is enabled already.
11762+ *
11763+ * Returns: N/A
11764+ */
11765+void SkDimDisableModeration(
11766+SK_AC *pAC, /* pointer to adapter control context */
11767+int CurrentModeration) /* type of current moderation */
11768+{
11769+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11770+ ("==> SkDimDisableModeration\n"));
11771+
11772+ if (M_DIMINFO.IntModTypeSelect != C_INT_MOD_NONE) {
11773+ if (CurrentModeration == C_INT_MOD_STATIC) {
11774+ disableIntMod(pAC);
11775+ } else { /* must be C_INT_MOD_DYNAMIC */
11776+ SkTimerStop(pAC, pAC->IoBase, &M_DIMINFO.ModTimer);
11777+ disableIntMod(pAC);
11778+ }
11779+ }
11780
11781-/*******************************************************************************
11782-**
11783-** Local functions
11784-**
11785-*******************************************************************************/
11786+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11787+ ("<== SkDimDisableModeration\n"));
11788+}
11789
11790-/*******************************************************************************
11791-** Function : GetCurrentSystemLoad
11792-** Description : Retrieves the current system load of the system. This load
11793-** is evaluated for all processors within the system.
11794-** Programmer : Ralph Roesler
11795-** Last Modified: 22-mar-03
11796-** Returns : unsigned int: load expressed in percentage
11797-** Notes : The possible range being returned is from 0 up to 100.
11798-** Whereas 0 means 'no load at all' and 100 'system fully loaded'
11799-** It is impossible to determine what actually causes the system
11800-** to be in 100%, but maybe that is due to too much interrupts.
11801-*******************************************************************************/
11802-
11803-static unsigned int
11804-GetCurrentSystemLoad(SK_AC *pAC) {
11805- unsigned long jif = jiffies;
11806- unsigned int UserTime = 0;
11807- unsigned int SystemTime = 0;
11808- unsigned int NiceTime = 0;
11809- unsigned int IdleTime = 0;
11810- unsigned int TotalTime = 0;
11811- unsigned int UsedTime = 0;
11812- unsigned int SystemLoad = 0;
11813+/******************************************************************************
11814+ *
11815+ * Local Functions
11816+ *
11817+ *****************************************************************************/
11818
11819- /* unsigned int NbrCpu = 0; */
11820+/*****************************************************************************
11821+ *
11822+ * getIsrCalls - evaluate the number of IRQs handled in mod interval
11823+ *
11824+ * Description:
11825+ * Depending on the selected moderation mask, this function will return
11826+ * the number of interrupts handled in the previous moderation interval.
11827+ * This evaluated number is based on the current number of interrupts
11828+ * stored in PNMI-context and the previous stored interrupts.
11829+ *
11830+ * Returns:
11831+ * the number of IRQs handled
11832+ */
11833+static SK_U64 getIsrCalls(
11834+SK_AC *pAC) /* pointer to adapter control context */
11835+{
11836+ SK_U64 RxPort0IntDiff = 0, RxPort1IntDiff = 0;
11837+ SK_U64 TxPort0IntDiff = 0, TxPort1IntDiff = 0;
11838+ SK_U64 StatusPort0IntDiff = 0, StatusPort1IntDiff = 0;
11839+
11840+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==>getIsrCalls\n"));
11841+
11842+ if (!CHIP_ID_YUKON_2(pAC)) {
11843+ if ((M_DIMINFO.MaskIrqModeration == IRQ_MASK_TX_ONLY) ||
11844+ (M_DIMINFO.MaskIrqModeration == IRQ_MASK_SP_TX)) {
11845+ if (pAC->GIni.GIMacsFound == 2) {
11846+ TxPort1IntDiff =
11847+ pAC->Pnmi.Port[1].TxIntrCts -
11848+ M_DIMINFO.PrevPort1TxIntrCts;
11849+ }
11850+ TxPort0IntDiff = pAC->Pnmi.Port[0].TxIntrCts -
11851+ M_DIMINFO.PrevPort0TxIntrCts;
11852+ } else if ((M_DIMINFO.MaskIrqModeration == IRQ_MASK_RX_ONLY) ||
11853+ (M_DIMINFO.MaskIrqModeration == IRQ_MASK_SP_RX)) {
11854+ if (pAC->GIni.GIMacsFound == 2) {
11855+ RxPort1IntDiff =
11856+ pAC->Pnmi.Port[1].RxIntrCts -
11857+ M_DIMINFO.PrevPort1RxIntrCts;
11858+ }
11859+ RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts -
11860+ M_DIMINFO.PrevPort0RxIntrCts;
11861+ } else {
11862+ if (pAC->GIni.GIMacsFound == 2) {
11863+ RxPort1IntDiff =
11864+ pAC->Pnmi.Port[1].RxIntrCts -
11865+ M_DIMINFO.PrevPort1RxIntrCts;
11866+ TxPort1IntDiff =
11867+ pAC->Pnmi.Port[1].TxIntrCts -
11868+ M_DIMINFO.PrevPort1TxIntrCts;
11869+ }
11870+ RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts -
11871+ M_DIMINFO.PrevPort0RxIntrCts;
11872+ TxPort0IntDiff = pAC->Pnmi.Port[0].TxIntrCts -
11873+ M_DIMINFO.PrevPort0TxIntrCts;
11874+ }
11875+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11876+ ("==>getIsrCalls (!CHIP_ID_YUKON_2)\n"));
11877+ return (RxPort0IntDiff + RxPort1IntDiff +
11878+ TxPort0IntDiff + TxPort1IntDiff);
11879+ }
11880
11881 /*
11882- ** The following lines have been commented out, because
11883- ** from kernel 2.5.44 onwards, the kernel-owned structure
11884- **
11885- ** struct kernel_stat kstat
11886- **
11887- ** is not marked as an exported symbol in the file
11888+ ** We have a Yukon2 compliant chipset if we come up to here
11889 **
11890- ** kernel/ksyms.c
11891- **
11892- ** As a consequence, using this driver as KLM is not possible
11893- ** and any access of the structure kernel_stat via the
11894- ** dedicated macros kstat_cpu(i).cpustat.xxx is to be avoided.
11895- **
11896- ** The kstat-information might be added again in future
11897- ** versions of the 2.5.xx kernel, but for the time being,
11898- ** number of interrupts will serve as indication how much
11899- ** load we currently have...
11900- **
11901- ** for (NbrCpu = 0; NbrCpu < num_online_cpus(); NbrCpu++) {
11902- ** UserTime = UserTime + kstat_cpu(NbrCpu).cpustat.user;
11903- ** NiceTime = NiceTime + kstat_cpu(NbrCpu).cpustat.nice;
11904- ** SystemTime = SystemTime + kstat_cpu(NbrCpu).cpustat.system;
11905- ** }
11906+ if (pAC->GIni.GIMacsFound == 2) {
11907+ StatusPort1IntDiff = pAC->Pnmi.Port[1].StatusLeIntrCts -
11908+ M_DIMINFO.PrevPort1StatusIntrCts;
11909+ }
11910+ StatusPort0IntDiff = pAC->Pnmi.Port[0].StatusLeIntrCts -
11911+ M_DIMINFO.PrevPort0StatusIntrCts;
11912 */
11913- SK_U64 ThresholdInts = 0;
11914- SK_U64 IsrCallsPerSec = 0;
11915-
11916- ThresholdInts = ((M_DIMINFO.MaxModIntsPerSec *
11917- C_INT_MOD_ENABLE_PERCENTAGE) + 100);
11918- IsrCallsPerSec = GetIsrCalls(pAC);
11919- if (IsrCallsPerSec >= ThresholdInts) {
11920- /*
11921- ** We do not know how much the real CPU-load is!
11922- ** Return 80% as a default in order to activate DIM
11923- */
11924- SystemLoad = 80;
11925- return (SystemLoad);
11926- }
11927-
11928- UsedTime = UserTime + NiceTime + SystemTime;
11929-
11930- IdleTime = jif * num_online_cpus() - UsedTime;
11931- TotalTime = UsedTime + IdleTime;
11932-
11933- SystemLoad = ( 100 * (UsedTime - M_DIMINFO.PrevUsedTime) ) /
11934- (TotalTime - M_DIMINFO.PrevTotalTime);
11935+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11936+ ("==>getIsrCalls (CHIP_ID_YUKON_2)\n"));
11937+ return (StatusPort0IntDiff + StatusPort1IntDiff);
11938+}
11939
11940- if (M_DIMINFO.DisplayStats) {
11941- printk("Current system load is: %u\n", SystemLoad);
11942+/*****************************************************************************
11943+ *
11944+ * setCurrIntCtr - stores the current number of interrupts
11945+ *
11946+ * Description:
11947+ * Stores the current number of occurred interrupts in the adapter
11948+ * context. This is needed to evaluate the umber of interrupts within
11949+ * the moderation interval.
11950+ *
11951+ * Returns: N/A
11952+ *
11953+ */
11954+static void setCurrIntCtr(
11955+SK_AC *pAC) /* pointer to adapter control context */
11956+{
11957+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==>setCurrIntCtr\n"));
11958+
11959+ if (!CHIP_ID_YUKON_2(pAC)) {
11960+ if (pAC->GIni.GIMacsFound == 2) {
11961+ M_DIMINFO.PrevPort1RxIntrCts = pAC->Pnmi.Port[1].RxIntrCts;
11962+ M_DIMINFO.PrevPort1TxIntrCts = pAC->Pnmi.Port[1].TxIntrCts;
11963+ }
11964+ M_DIMINFO.PrevPort0RxIntrCts = pAC->Pnmi.Port[0].RxIntrCts;
11965+ M_DIMINFO.PrevPort0TxIntrCts = pAC->Pnmi.Port[0].TxIntrCts;
11966+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11967+ ("<== setCurrIntCtr (!CHIP_ID_YUKON_2)\n"));
11968+ return;
11969 }
11970
11971- M_DIMINFO.PrevTotalTime = TotalTime;
11972- M_DIMINFO.PrevUsedTime = UsedTime;
11973-
11974- return (SystemLoad);
11975+ /*
11976+ ** We have a Yukon2 compliant chipset if we come up to here
11977+ **
11978+ if (pAC->GIni.GIMacsFound == 2) {
11979+ M_DIMINFO.PrevPort1StatusIntrCts = pAC->Pnmi.Port[1].StatusLeIntrCts;
11980+ }
11981+ M_DIMINFO.PrevPort0StatusIntrCts = pAC->Pnmi.Port[0].StatusLeIntrCts;
11982+ */
11983+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
11984+ ("<== setCurrIntCtr (CHIP_ID_YUKON_2)\n"));
11985 }
11986
11987-/*******************************************************************************
11988-** Function : GetIsrCalls
11989-** Description : Depending on the selected moderation mask, this function will
11990-** return the number of interrupts handled in the previous time-
11991-** frame. This evaluated number is based on the current number
11992-** of interrupts stored in PNMI-context and the previous stored
11993-** interrupts.
11994-** Programmer : Ralph Roesler
11995-** Last Modified: 23-mar-03
11996-** Returns : int: the number of interrupts being executed in the last
11997-** timeframe
11998-** Notes : It makes only sense to call this function, when dynamic
11999-** interrupt moderation is applied
12000-*******************************************************************************/
12001-
12002-static SK_U64
12003-GetIsrCalls(SK_AC *pAC) {
12004- SK_U64 RxPort0IntDiff = 0;
12005- SK_U64 RxPort1IntDiff = 0;
12006- SK_U64 TxPort0IntDiff = 0;
12007- SK_U64 TxPort1IntDiff = 0;
12008-
12009- if (pAC->DynIrqModInfo.MaskIrqModeration == IRQ_MASK_TX_ONLY) {
12010- if (pAC->GIni.GIMacsFound == 2) {
12011- TxPort1IntDiff = pAC->Pnmi.Port[1].TxIntrCts -
12012- pAC->DynIrqModInfo.PrevPort1TxIntrCts;
12013- }
12014- TxPort0IntDiff = pAC->Pnmi.Port[0].TxIntrCts -
12015- pAC->DynIrqModInfo.PrevPort0TxIntrCts;
12016- } else if (pAC->DynIrqModInfo.MaskIrqModeration == IRQ_MASK_RX_ONLY) {
12017- if (pAC->GIni.GIMacsFound == 2) {
12018- RxPort1IntDiff = pAC->Pnmi.Port[1].RxIntrCts -
12019- pAC->DynIrqModInfo.PrevPort1RxIntrCts;
12020- }
12021- RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts -
12022- pAC->DynIrqModInfo.PrevPort0RxIntrCts;
12023- } else {
12024- if (pAC->GIni.GIMacsFound == 2) {
12025- RxPort1IntDiff = pAC->Pnmi.Port[1].RxIntrCts -
12026- pAC->DynIrqModInfo.PrevPort1RxIntrCts;
12027- TxPort1IntDiff = pAC->Pnmi.Port[1].TxIntrCts -
12028- pAC->DynIrqModInfo.PrevPort1TxIntrCts;
12029- }
12030- RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts -
12031- pAC->DynIrqModInfo.PrevPort0RxIntrCts;
12032- TxPort0IntDiff = pAC->Pnmi.Port[0].TxIntrCts -
12033- pAC->DynIrqModInfo.PrevPort0TxIntrCts;
12034- }
12035-
12036- return (RxPort0IntDiff + RxPort1IntDiff + TxPort0IntDiff + TxPort1IntDiff);
12037+/*****************************************************************************
12038+ *
12039+ * isIntModEnabled - returns the current state of interrupt moderation
12040+ *
12041+ * Description:
12042+ * This function retrieves the current value of the interrupt moderation
12043+ * command register. Its content determines whether any moderation is
12044+ * running or not.
12045+ *
12046+ * Returns:
12047+ * SK_TRUE : IRQ moderation is currently active
12048+ * SK_FALSE: No IRQ moderation is active
12049+ */
12050+static SK_BOOL isIntModEnabled(
12051+SK_AC *pAC) /* pointer to adapter control context */
12052+{
12053+ unsigned long CtrCmd;
12054+
12055+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==>isIntModEnabled\n"));
12056+
12057+ SK_IN32(pAC->IoBase, B2_IRQM_CTRL, &CtrCmd);
12058+ if ((CtrCmd & TIM_START) == TIM_START) {
12059+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
12060+ ("<== isIntModEnabled (SK_TRUE)\n"));
12061+ return SK_TRUE;
12062+ }
12063+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
12064+ ("<== isIntModEnabled (SK_FALSE)\n"));
12065+ return SK_FALSE;
12066 }
12067
12068-/*******************************************************************************
12069-** Function : GetRxCalls
12070-** Description : This function will return the number of times a receive inter-
12071-** rupt was processed. This is needed to evaluate any resizing
12072-** factor.
12073-** Programmer : Ralph Roesler
12074-** Last Modified: 23-mar-03
12075-** Returns : SK_U64: the number of RX-ints being processed
12076-** Notes : It makes only sense to call this function, when dynamic
12077-** interrupt moderation is applied
12078-*******************************************************************************/
12079-
12080-static SK_U64
12081-GetRxCalls(SK_AC *pAC) {
12082- SK_U64 RxPort0IntDiff = 0;
12083- SK_U64 RxPort1IntDiff = 0;
12084-
12085- if (pAC->GIni.GIMacsFound == 2) {
12086- RxPort1IntDiff = pAC->Pnmi.Port[1].RxIntrCts -
12087- pAC->DynIrqModInfo.PrevPort1RxIntrCts;
12088- }
12089- RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts -
12090- pAC->DynIrqModInfo.PrevPort0RxIntrCts;
12091-
12092- return (RxPort0IntDiff + RxPort1IntDiff);
12093-}
12094+/*****************************************************************************
12095+ *
12096+ * enableIntMod - enables the interrupt moderation
12097+ *
12098+ * Description:
12099+ * Enabling the interrupt moderation is done by putting the desired
12100+ * moderation interval in the B2_IRQM_INI register, specifying the
12101+ * desired maks in the B2_IRQM_MSK register and finally starting the
12102+ * IRQ moderation timer using the B2_IRQM_CTRL register.
12103+ *
12104+ * Returns: N/A
12105+ *
12106+ */
12107+static void enableIntMod(
12108+SK_AC *pAC) /* pointer to adapter control context */
12109+{
12110+ unsigned long ModBase;
12111+
12112+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==> enableIntMod\n"));
12113+
12114+ if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
12115+ ModBase = C_CLK_FREQ_GENESIS / M_DIMINFO.MaxModIntsPerSec;
12116+ } else if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) {
12117+ ModBase = C_CLK_FREQ_YUKON_EC / M_DIMINFO.MaxModIntsPerSec;
12118+ } else {
12119+ ModBase = C_CLK_FREQ_YUKON / M_DIMINFO.MaxModIntsPerSec;
12120+ }
12121
12122-/*******************************************************************************
12123-** Function : SetCurrIntCtr
12124-** Description : Will store the current number orf occured interrupts in the
12125-** adapter context. This is needed to evaluated the number of
12126-** interrupts within a current timeframe.
12127-** Programmer : Ralph Roesler
12128-** Last Modified: 23-mar-03
12129-** Returns : void (!)
12130-** Notes : -
12131-*******************************************************************************/
12132-
12133-static void
12134-SetCurrIntCtr(SK_AC *pAC) {
12135- if (pAC->GIni.GIMacsFound == 2) {
12136- pAC->DynIrqModInfo.PrevPort1RxIntrCts = pAC->Pnmi.Port[1].RxIntrCts;
12137- pAC->DynIrqModInfo.PrevPort1TxIntrCts = pAC->Pnmi.Port[1].TxIntrCts;
12138- }
12139- pAC->DynIrqModInfo.PrevPort0RxIntrCts = pAC->Pnmi.Port[0].RxIntrCts;
12140- pAC->DynIrqModInfo.PrevPort0TxIntrCts = pAC->Pnmi.Port[0].TxIntrCts;
12141-}
12142+ SK_OUT32(pAC->IoBase, B2_IRQM_INI, ModBase);
12143+ SK_OUT32(pAC->IoBase, B2_IRQM_MSK, M_DIMINFO.MaskIrqModeration);
12144+ SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_START);
12145
12146-/*******************************************************************************
12147-** Function : IsIntModEnabled()
12148-** Description : Retrieves the current value of the interrupts moderation
12149-** command register. Its content determines whether any
12150-** moderation is running or not.
12151-** Programmer : Ralph Roesler
12152-** Last Modified: 23-mar-03
12153-** Returns : SK_TRUE : if mod timer running
12154-** SK_FALSE : if no moderation is being performed
12155-** Notes : -
12156-*******************************************************************************/
12157-
12158-static SK_BOOL
12159-IsIntModEnabled(SK_AC *pAC) {
12160- unsigned long CtrCmd;
12161-
12162- SK_IN32(pAC->IoBase, B2_IRQM_CTRL, &CtrCmd);
12163- if ((CtrCmd & TIM_START) == TIM_START) {
12164- return SK_TRUE;
12165- } else {
12166- return SK_FALSE;
12167- }
12168+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("<== enableIntMod\n"));
12169 }
12170
12171-/*******************************************************************************
12172-** Function : EnableIntMod()
12173-** Description : Enables the interrupt moderation using the values stored in
12174-** in the pAC->DynIntMod data structure
12175-** Programmer : Ralph Roesler
12176-** Last Modified: 22-mar-03
12177-** Returns : -
12178-** Notes : -
12179-*******************************************************************************/
12180-
12181-static void
12182-EnableIntMod(SK_AC *pAC) {
12183- unsigned long ModBase;
12184-
12185- if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
12186- ModBase = C_CLK_FREQ_GENESIS / pAC->DynIrqModInfo.MaxModIntsPerSec;
12187- } else {
12188- ModBase = C_CLK_FREQ_YUKON / pAC->DynIrqModInfo.MaxModIntsPerSec;
12189- }
12190-
12191- SK_OUT32(pAC->IoBase, B2_IRQM_INI, ModBase);
12192- SK_OUT32(pAC->IoBase, B2_IRQM_MSK, pAC->DynIrqModInfo.MaskIrqModeration);
12193- SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_START);
12194- if (M_DIMINFO.DisplayStats) {
12195- printk("Enabled interrupt moderation (%i ints/sec)\n",
12196- M_DIMINFO.MaxModIntsPerSec);
12197- }
12198-}
12199+/*****************************************************************************
12200+ *
12201+ * disableIntMod - disables the interrupt moderation
12202+ *
12203+ * Description:
12204+ * Disabling the interrupt moderation is done by stopping the
12205+ * IRQ moderation timer using the B2_IRQM_CTRL register.
12206+ *
12207+ * Returns: N/A
12208+ *
12209+ */
12210+static void disableIntMod(
12211+SK_AC *pAC) /* pointer to adapter control context */
12212+{
12213+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==> disableIntMod\n"));
12214
12215-/*******************************************************************************
12216-** Function : DisableIntMod()
12217-** Description : Disbles the interrupt moderation independent of what inter-
12218-** rupts are running or not
12219-** Programmer : Ralph Roesler
12220-** Last Modified: 23-mar-03
12221-** Returns : -
12222-** Notes : -
12223-*******************************************************************************/
12224-
12225-static void
12226-DisableIntMod(SK_AC *pAC) {
12227-
12228- SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_STOP);
12229- if (M_DIMINFO.DisplayStats) {
12230- printk("Disabled interrupt moderation\n");
12231- }
12232-}
12233+ SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_STOP);
12234
12235-/*******************************************************************************
12236-** Function : ResizeDimTimerDuration();
12237-** Description : Checks the current used descriptor ratio and resizes the
12238-** duration timer (longer/smaller) if possible.
12239-** Programmer : Ralph Roesler
12240-** Last Modified: 23-mar-03
12241-** Returns : -
12242-** Notes : There are both maximum and minimum timer duration value.
12243-** This function assumes that interrupt moderation is already
12244-** enabled!
12245-*******************************************************************************/
12246-
12247-static void
12248-ResizeDimTimerDuration(SK_AC *pAC) {
12249- SK_BOOL IncreaseTimerDuration;
12250- int TotalMaxNbrDescr;
12251- int UsedDescrRatio;
12252- int RatioDiffAbs;
12253- int RatioDiffRel;
12254- int NewMaxModIntsPerSec;
12255- int ModAdjValue;
12256- long ModBase;
12257-
12258- /*
12259- ** Check first if we are allowed to perform any modification
12260- */
12261- if (IsIntModEnabled(pAC)) {
12262- if (M_DIMINFO.IntModTypeSelect != C_INT_MOD_DYNAMIC) {
12263- return;
12264- } else {
12265- if (M_DIMINFO.ModJustEnabled) {
12266- M_DIMINFO.ModJustEnabled = SK_FALSE;
12267- return;
12268- }
12269- }
12270- }
12271-
12272- /*
12273- ** If we got until here, we have to evaluate the amount of the
12274- ** descriptor ratio change...
12275- */
12276- TotalMaxNbrDescr = pAC->RxDescrPerRing * GetRxCalls(pAC);
12277- UsedDescrRatio = (M_DIMINFO.NbrProcessedDescr * 100) / TotalMaxNbrDescr;
12278-
12279- if (UsedDescrRatio > M_DIMINFO.PrevUsedDescrRatio) {
12280- RatioDiffAbs = (UsedDescrRatio - M_DIMINFO.PrevUsedDescrRatio);
12281- RatioDiffRel = (RatioDiffAbs * 100) / UsedDescrRatio;
12282- M_DIMINFO.PrevUsedDescrRatio = UsedDescrRatio;
12283- IncreaseTimerDuration = SK_FALSE; /* in other words: DECREASE */
12284- } else if (UsedDescrRatio < M_DIMINFO.PrevUsedDescrRatio) {
12285- RatioDiffAbs = (M_DIMINFO.PrevUsedDescrRatio - UsedDescrRatio);
12286- RatioDiffRel = (RatioDiffAbs * 100) / M_DIMINFO.PrevUsedDescrRatio;
12287- M_DIMINFO.PrevUsedDescrRatio = UsedDescrRatio;
12288- IncreaseTimerDuration = SK_TRUE; /* in other words: INCREASE */
12289- } else {
12290- RatioDiffAbs = (M_DIMINFO.PrevUsedDescrRatio - UsedDescrRatio);
12291- RatioDiffRel = (RatioDiffAbs * 100) / M_DIMINFO.PrevUsedDescrRatio;
12292- M_DIMINFO.PrevUsedDescrRatio = UsedDescrRatio;
12293- IncreaseTimerDuration = SK_TRUE; /* in other words: INCREASE */
12294- }
12295-
12296- /*
12297- ** Now we can determine the change in percent
12298- */
12299- if ((RatioDiffRel >= 0) && (RatioDiffRel <= 5) ) {
12300- ModAdjValue = 1; /* 1% change - maybe some other value in future */
12301- } else if ((RatioDiffRel > 5) && (RatioDiffRel <= 10) ) {
12302- ModAdjValue = 1; /* 1% change - maybe some other value in future */
12303- } else if ((RatioDiffRel > 10) && (RatioDiffRel <= 15) ) {
12304- ModAdjValue = 1; /* 1% change - maybe some other value in future */
12305- } else {
12306- ModAdjValue = 1; /* 1% change - maybe some other value in future */
12307- }
12308-
12309- if (IncreaseTimerDuration) {
12310- NewMaxModIntsPerSec = M_DIMINFO.MaxModIntsPerSec +
12311- (M_DIMINFO.MaxModIntsPerSec * ModAdjValue) / 100;
12312- } else {
12313- NewMaxModIntsPerSec = M_DIMINFO.MaxModIntsPerSec -
12314- (M_DIMINFO.MaxModIntsPerSec * ModAdjValue) / 100;
12315- }
12316-
12317- /*
12318- ** Check if we exceed boundaries...
12319- */
12320- if ( (NewMaxModIntsPerSec > M_DIMINFO.MaxModIntsPerSecUpperLimit) ||
12321- (NewMaxModIntsPerSec < M_DIMINFO.MaxModIntsPerSecLowerLimit)) {
12322- if (M_DIMINFO.DisplayStats) {
12323- printk("Cannot change ModTim from %i to %i ints/sec\n",
12324- M_DIMINFO.MaxModIntsPerSec, NewMaxModIntsPerSec);
12325- }
12326- return;
12327- } else {
12328- if (M_DIMINFO.DisplayStats) {
12329- printk("Resized ModTim from %i to %i ints/sec\n",
12330- M_DIMINFO.MaxModIntsPerSec, NewMaxModIntsPerSec);
12331- }
12332- }
12333-
12334- M_DIMINFO.MaxModIntsPerSec = NewMaxModIntsPerSec;
12335-
12336- if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
12337- ModBase = C_CLK_FREQ_GENESIS / pAC->DynIrqModInfo.MaxModIntsPerSec;
12338- } else {
12339- ModBase = C_CLK_FREQ_YUKON / pAC->DynIrqModInfo.MaxModIntsPerSec;
12340- }
12341-
12342- /*
12343- ** We do not need to touch any other registers
12344- */
12345- SK_OUT32(pAC->IoBase, B2_IRQM_INI, ModBase);
12346+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("<== disableIntMod\n"));
12347 }
12348
12349 /*******************************************************************************
12350-** Function : DisplaySelectedModerationType()
12351-** Description : Displays what type of moderation we have
12352-** Programmer : Ralph Roesler
12353-** Last Modified: 23-mar-03
12354-** Returns : void!
12355-** Notes : -
12356-*******************************************************************************/
12357-
12358-static void
12359-DisplaySelectedModerationType(SK_AC *pAC) {
12360-
12361- if (pAC->DynIrqModInfo.DisplayStats) {
12362- if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_STATIC) {
12363- printk("Static int moderation runs with %i INTS/sec\n",
12364- pAC->DynIrqModInfo.MaxModIntsPerSec);
12365- } else if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
12366- if (IsIntModEnabled(pAC)) {
12367- printk("Dynamic int moderation runs with %i INTS/sec\n",
12368- pAC->DynIrqModInfo.MaxModIntsPerSec);
12369- } else {
12370- printk("Dynamic int moderation currently not applied\n");
12371- }
12372- } else {
12373- printk("No interrupt moderation selected!\n");
12374- }
12375- }
12376-}
12377-
12378-/*******************************************************************************
12379-** Function : DisplaySelectedModerationMask()
12380-** Description : Displays what interrupts are moderated
12381-** Programmer : Ralph Roesler
12382-** Last Modified: 23-mar-03
12383-** Returns : void!
12384-** Notes : -
12385-*******************************************************************************/
12386-
12387-static void
12388-DisplaySelectedModerationMask(SK_AC *pAC) {
12389-
12390- if (pAC->DynIrqModInfo.DisplayStats) {
12391- if (pAC->DynIrqModInfo.IntModTypeSelect != C_INT_MOD_NONE) {
12392- switch (pAC->DynIrqModInfo.MaskIrqModeration) {
12393- case IRQ_MASK_TX_ONLY:
12394- printk("Only Tx-interrupts are moderated\n");
12395- break;
12396- case IRQ_MASK_RX_ONLY:
12397- printk("Only Rx-interrupts are moderated\n");
12398- break;
12399- case IRQ_MASK_SP_ONLY:
12400- printk("Only special-interrupts are moderated\n");
12401- break;
12402- case IRQ_MASK_TX_RX:
12403- printk("Tx- and Rx-interrupts are moderated\n");
12404- break;
12405- case IRQ_MASK_SP_RX:
12406- printk("Special- and Rx-interrupts are moderated\n");
12407- break;
12408- case IRQ_MASK_SP_TX:
12409- printk("Special- and Tx-interrupts are moderated\n");
12410- break;
12411- case IRQ_MASK_RX_TX_SP:
12412- printk("All Rx-, Tx and special-interrupts are moderated\n");
12413- break;
12414- default:
12415- printk("Don't know what is moderated\n");
12416- break;
12417- }
12418- } else {
12419- printk("No specific interrupts masked for moderation\n");
12420- }
12421- }
12422-}
12423-
12424-/*******************************************************************************
12425-** Function : DisplayDescrRatio
12426-** Description : Like the name states...
12427-** Programmer : Ralph Roesler
12428-** Last Modified: 23-mar-03
12429-** Returns : void!
12430-** Notes : -
12431-*******************************************************************************/
12432-
12433-static void
12434-DisplayDescrRatio(SK_AC *pAC) {
12435- int TotalMaxNbrDescr = 0;
12436-
12437- if (pAC->DynIrqModInfo.DisplayStats) {
12438- TotalMaxNbrDescr = pAC->RxDescrPerRing * GetRxCalls(pAC);
12439- printk("Ratio descriptors: %i/%i\n",
12440- M_DIMINFO.NbrProcessedDescr, TotalMaxNbrDescr);
12441- }
12442-}
12443-
12444-/*******************************************************************************
12445-**
12446-** End of file
12447-**
12448-*******************************************************************************/
12449+ *
12450+ * End of file
12451+ *
12452+ ******************************************************************************/
12453diff -urN linux-2.6.17.orig/drivers/net/sk98lin/skethtool.c linux-2.6.17/drivers/net/sk98lin/skethtool.c
12454--- linux-2.6.17.orig/drivers/net/sk98lin/skethtool.c 2006-06-22 13:17:16.000000000 +0200
12455+++ linux-2.6.17/drivers/net/sk98lin/skethtool.c 2006-04-27 11:43:45.000000000 +0200
12456@@ -2,8 +2,8 @@
12457 *
12458 * Name: skethtool.c
12459 * Project: GEnesis, PCI Gigabit Ethernet Adapter
12460- * Version: $Revision$
12461- * Date: $Date$
12462+ * Version: $Revision$
12463+ * Date: $Date$
12464 * Purpose: All functions regarding ethtool handling
12465 *
12466 ******************************************************************************/
12467@@ -11,7 +11,7 @@
12468 /******************************************************************************
12469 *
12470 * (C)Copyright 1998-2002 SysKonnect GmbH.
12471- * (C)Copyright 2002-2004 Marvell.
12472+ * (C)Copyright 2002-2005 Marvell.
12473 *
12474 * Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet
12475 * Server Adapters.
12476@@ -21,9 +21,6 @@
12477 *
12478 * Address all question to: linux@syskonnect.de
12479 *
12480- * The technical manual for the adapters is available from SysKonnect's
12481- * web pages: www.syskonnect.com
12482- *
12483 * This program is free software; you can redistribute it and/or modify
12484 * it under the terms of the GNU General Public License as published by
12485 * the Free Software Foundation; either version 2 of the License, or
12486@@ -36,10 +33,18 @@
12487 #include "h/skdrv1st.h"
12488 #include "h/skdrv2nd.h"
12489 #include "h/skversion.h"
12490-
12491 #include <linux/ethtool.h>
12492+#include <linux/module.h>
12493 #include <linux/timer.h>
12494-#include <linux/delay.h>
12495+
12496+/******************************************************************************
12497+ *
12498+ * External Functions and Data
12499+ *
12500+ *****************************************************************************/
12501+
12502+extern void SkDimDisableModeration(SK_AC *pAC, int CurrentModeration);
12503+extern void SkDimEnableModerationIfNeeded(SK_AC *pAC);
12504
12505 /******************************************************************************
12506 *
12507@@ -47,6 +52,12 @@
12508 *
12509 *****************************************************************************/
12510
12511+#ifndef ETHT_STATSTRING_LEN
12512+#define ETHT_STATSTRING_LEN 32
12513+#endif
12514+
12515+#define SK98LIN_STAT(m) sizeof(((SK_AC *)0)->m),offsetof(SK_AC, m)
12516+
12517 #define SUPP_COPPER_ALL (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
12518 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
12519 SUPPORTED_1000baseT_Half| SUPPORTED_1000baseT_Full| \
12520@@ -65,6 +76,454 @@
12521 ADVERTISED_FIBRE | \
12522 ADVERTISED_Autoneg)
12523
12524+/******************************************************************************
12525+ *
12526+ * Local Function Prototypes
12527+ *
12528+ *****************************************************************************/
12529+
12530+#ifdef ETHTOOL_GSET
12531+static void getSettings(SK_AC *pAC, int port, struct ethtool_cmd *ecmd);
12532+#endif
12533+#ifdef ETHTOOL_SSET
12534+static int setSettings(SK_AC *pAC, int port, struct ethtool_cmd *ecmd);
12535+#endif
12536+#ifdef ETHTOOL_GPAUSEPARAM
12537+static void getPauseParams(SK_AC *pAC, int port, struct ethtool_pauseparam *epause);
12538+#endif
12539+#ifdef ETHTOOL_SPAUSEPARAM
12540+static int setPauseParams(SK_AC *pAC, int port, struct ethtool_pauseparam *epause);
12541+#endif
12542+#ifdef ETHTOOL_GDRVINFO
12543+static void getDriverInfo(SK_AC *pAC, int port, struct ethtool_drvinfo *edrvinfo);
12544+#endif
12545+#ifdef ETHTOOL_PHYS_ID
12546+static int startLocateNIC(SK_AC *pAC, int port, struct ethtool_value *blinkSecs);
12547+static void toggleLeds(unsigned long ptr);
12548+#endif
12549+#ifdef ETHTOOL_GCOALESCE
12550+static void getModerationParams(SK_AC *pAC, int port, struct ethtool_coalesce *ecoalesc);
12551+#endif
12552+#ifdef ETHTOOL_SCOALESCE
12553+static int setModerationParams(SK_AC *pAC, int port, struct ethtool_coalesce *ecoalesc);
12554+#endif
12555+#ifdef ETHTOOL_GWOL
12556+static void getWOLsettings(SK_AC *pAC, int port, struct ethtool_wolinfo *ewol);
12557+#endif
12558+#ifdef ETHTOOL_SWOL
12559+static int setWOLsettings(SK_AC *pAC, int port, struct ethtool_wolinfo *ewol);
12560+#endif
12561+
12562+static int getPortNumber(struct net_device *netdev, struct ifreq *ifr);
12563+
12564+/******************************************************************************
12565+ *
12566+ * Local Variables
12567+ *
12568+ *****************************************************************************/
12569+
12570+struct sk98lin_stats {
12571+ char stat_string[ETHT_STATSTRING_LEN];
12572+ int sizeof_stat;
12573+ int stat_offset;
12574+};
12575+
12576+static struct sk98lin_stats sk98lin_etht_stats_port0[] = {
12577+ { "rx_packets" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxOkCts) },
12578+ { "tx_packets" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxOkCts) },
12579+ { "rx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxOctetsOkCts) },
12580+ { "tx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxOctetsOkCts) },
12581+ { "rx_errors" , SK98LIN_STAT(PnmiStruct.InErrorsCts) },
12582+ { "tx_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxSingleCollisionCts) },
12583+ { "rx_dropped" , SK98LIN_STAT(PnmiStruct.RxNoBufCts) },
12584+ { "tx_dropped" , SK98LIN_STAT(PnmiStruct.TxNoBufCts) },
12585+ { "multicasts" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxMulticastOkCts) },
12586+ { "collisions" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxSingleCollisionCts) },
12587+ { "rx_length_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxRuntCts) },
12588+ { "rx_buffer_overflow_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxFifoOverflowCts) },
12589+ { "rx_crc_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxFcsCts) },
12590+ { "rx_frame_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxFramingCts) },
12591+ { "rx_too_short_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxShortsCts) },
12592+ { "rx_too_long_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxTooLongCts) },
12593+ { "rx_carrier_extension_errors", SK98LIN_STAT(PnmiStruct.Stat[0].StatRxCextCts) },
12594+ { "rx_symbol_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxSymbolCts) },
12595+ { "rx_llc_mac_size_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxIRLengthCts) },
12596+ { "rx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxCarrierCts) },
12597+ { "rx_jabber_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxJabberCts) },
12598+ { "rx_missed_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxMissedCts) },
12599+ { "tx_abort_collision_errors" , SK98LIN_STAT(stats.tx_aborted_errors) },
12600+ { "tx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxCarrierCts) },
12601+ { "tx_buffer_underrun_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxFifoUnderrunCts) },
12602+ { "tx_heartbeat_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxCarrierCts) } ,
12603+ { "tx_window_errors" , SK98LIN_STAT(stats.tx_window_errors) }
12604+};
12605+
12606+static struct sk98lin_stats sk98lin_etht_stats_port1[] = {
12607+ { "rx_packets" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxOkCts) },
12608+ { "tx_packets" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxOkCts) },
12609+ { "rx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxOctetsOkCts) },
12610+ { "tx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxOctetsOkCts) },
12611+ { "rx_errors" , SK98LIN_STAT(PnmiStruct.InErrorsCts) },
12612+ { "tx_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxSingleCollisionCts) },
12613+ { "rx_dropped" , SK98LIN_STAT(PnmiStruct.RxNoBufCts) },
12614+ { "tx_dropped" , SK98LIN_STAT(PnmiStruct.TxNoBufCts) },
12615+ { "multicasts" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxMulticastOkCts) },
12616+ { "collisions" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxSingleCollisionCts) },
12617+ { "rx_length_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxRuntCts) },
12618+ { "rx_buffer_overflow_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxFifoOverflowCts) },
12619+ { "rx_crc_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxFcsCts) },
12620+ { "rx_frame_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxFramingCts) },
12621+ { "rx_too_short_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxShortsCts) },
12622+ { "rx_too_long_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxTooLongCts) },
12623+ { "rx_carrier_extension_errors", SK98LIN_STAT(PnmiStruct.Stat[1].StatRxCextCts) },
12624+ { "rx_symbol_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxSymbolCts) },
12625+ { "rx_llc_mac_size_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxIRLengthCts) },
12626+ { "rx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxCarrierCts) },
12627+ { "rx_jabber_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxJabberCts) },
12628+ { "rx_missed_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxMissedCts) },
12629+ { "tx_abort_collision_errors" , SK98LIN_STAT(stats.tx_aborted_errors) },
12630+ { "tx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxCarrierCts) },
12631+ { "tx_buffer_underrun_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxFifoUnderrunCts) },
12632+ { "tx_heartbeat_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxCarrierCts) } ,
12633+ { "tx_window_errors" , SK98LIN_STAT(stats.tx_window_errors) }
12634+};
12635+
12636+#define SK98LIN_STATS_LEN sizeof(sk98lin_etht_stats_port0) / sizeof(struct sk98lin_stats)
12637+
12638+static int nbrBlinkQuarterSeconds;
12639+static int currentPortIndex;
12640+static SK_BOOL isLocateNICrunning = SK_FALSE;
12641+static SK_BOOL isDualNetCard = SK_FALSE;
12642+static SK_BOOL doSwitchLEDsOn = SK_FALSE;
12643+static SK_BOOL boardWasDown[2] = { SK_FALSE, SK_FALSE };
12644+static struct timer_list locateNICtimer;
12645+
12646+/******************************************************************************
12647+ *
12648+ * Global Functions
12649+ *
12650+ *****************************************************************************/
12651+
12652+/*****************************************************************************
12653+ *
12654+ * SkEthIoctl - IOCTL entry point for all ethtool queries
12655+ *
12656+ * Description:
12657+ * Any IOCTL request that has to deal with the ethtool command tool is
12658+ * dispatched via this function.
12659+ *
12660+ * Returns:
12661+ * ==0: everything fine, no error
12662+ * !=0: the return value is the error code of the failure
12663+ */
12664+int SkEthIoctl(
12665+struct net_device *netdev, /* the pointer to netdev structure */
12666+struct ifreq *ifr) /* what interface the request refers to? */
12667+{
12668+ DEV_NET *pNet = (DEV_NET*) netdev->priv;
12669+ SK_AC *pAC = pNet->pAC;
12670+ void *pAddr = ifr->ifr_data;
12671+ int port = getPortNumber(netdev, ifr);
12672+ SK_PNMI_STRUCT_DATA *pPnmiStruct = &pAC->PnmiStruct;
12673+ SK_U32 Size = sizeof(SK_PNMI_STRUCT_DATA);
12674+ SK_U32 cmd;
12675+ struct sk98lin_stats *sk98lin_etht_stats =
12676+ (port == 0) ? sk98lin_etht_stats_port0 : sk98lin_etht_stats_port1;
12677+
12678+ if (get_user(cmd, (uint32_t *) pAddr)) {
12679+ return -EFAULT;
12680+ }
12681+
12682+ switch(cmd) {
12683+#ifdef ETHTOOL_GSET
12684+ case ETHTOOL_GSET: {
12685+ struct ethtool_cmd ecmd = { ETHTOOL_GSET };
12686+ getSettings(pAC, port, &ecmd);
12687+ if(copy_to_user(pAddr, &ecmd, sizeof(ecmd))) {
12688+ return -EFAULT;
12689+ }
12690+ return 0;
12691+ }
12692+ break;
12693+#endif
12694+#ifdef ETHTOOL_SSET
12695+ case ETHTOOL_SSET: {
12696+ struct ethtool_cmd ecmd;
12697+ if(copy_from_user(&ecmd, pAddr, sizeof(ecmd))) {
12698+ return -EFAULT;
12699+ }
12700+ return setSettings(pAC, port, &ecmd);
12701+ }
12702+ break;
12703+#endif
12704+#ifdef ETHTOOL_GLINK
12705+ case ETHTOOL_GLINK: {
12706+ struct ethtool_value edata = { ETHTOOL_GLINK };
12707+ edata.data = netif_carrier_ok(netdev);
12708+ if (copy_to_user(pAddr, &edata, sizeof(edata)))
12709+ return -EFAULT;
12710+ return 0;
12711+ }
12712+#endif
12713+#ifdef ETHTOOL_GDRVINFO
12714+ case ETHTOOL_GDRVINFO: {
12715+ struct ethtool_drvinfo drvinfo = { ETHTOOL_GDRVINFO };
12716+ getDriverInfo(pAC, port, &drvinfo);
12717+ if(copy_to_user(pAddr, &drvinfo, sizeof(drvinfo))) {
12718+ return -EFAULT;
12719+ }
12720+ return 0;
12721+ }
12722+ break;
12723+#endif
12724+#ifdef ETHTOOL_GSTRINGS
12725+ case ETHTOOL_GSTRINGS: {
12726+ struct ethtool_gstrings gstrings = { ETHTOOL_GSTRINGS };
12727+ char *strings = NULL;
12728+ int err = 0;
12729+ if(copy_from_user(&gstrings, pAddr, sizeof(gstrings))) {
12730+ return -EFAULT;
12731+ }
12732+ switch(gstrings.string_set) {
12733+#ifdef ETHTOOL_GSTATS
12734+ case ETH_SS_STATS: {
12735+ int i;
12736+ gstrings.len = SK98LIN_STATS_LEN;
12737+ if ((strings = kmalloc(SK98LIN_STATS_LEN*ETHT_STATSTRING_LEN,GFP_KERNEL)) == NULL) {
12738+ return -ENOMEM;
12739+ }
12740+ for(i=0; i < SK98LIN_STATS_LEN; i++) {
12741+ memcpy(&strings[i * ETHT_STATSTRING_LEN],
12742+ &(sk98lin_etht_stats[i].stat_string),
12743+ ETHT_STATSTRING_LEN);
12744+ }
12745+ }
12746+ break;
12747+#endif
12748+ default:
12749+ return -EOPNOTSUPP;
12750+ }
12751+ if(copy_to_user(pAddr, &gstrings, sizeof(gstrings))) {
12752+ err = -EFAULT;
12753+ }
12754+ pAddr = (void *) ((unsigned long int) pAddr + offsetof(struct ethtool_gstrings, data));
12755+ if(!err && copy_to_user(pAddr, strings, gstrings.len * ETH_GSTRING_LEN)) {
12756+ err = -EFAULT;
12757+ }
12758+ kfree(strings);
12759+ return err;
12760+ }
12761+#endif
12762+#ifdef ETHTOOL_GSTATS
12763+ case ETHTOOL_GSTATS: {
12764+ struct {
12765+ struct ethtool_stats eth_stats;
12766+ uint64_t data[SK98LIN_STATS_LEN];
12767+ } stats = { {ETHTOOL_GSTATS, SK98LIN_STATS_LEN} };
12768+ int i;
12769+
12770+ if (netif_running(pAC->dev[port])) {
12771+ SkPnmiGetStruct(pAC, pAC->IoBase, pPnmiStruct, &Size, port);
12772+ }
12773+ for(i = 0; i < SK98LIN_STATS_LEN; i++) {
12774+ if (netif_running(pAC->dev[port])) {
12775+ stats.data[i] = (sk98lin_etht_stats[i].sizeof_stat ==
12776+ sizeof(uint64_t)) ?
12777+ *(uint64_t *)((char *)pAC +
12778+ sk98lin_etht_stats[i].stat_offset) :
12779+ *(uint32_t *)((char *)pAC +
12780+ sk98lin_etht_stats[i].stat_offset);
12781+ } else {
12782+ stats.data[i] = (sk98lin_etht_stats[i].sizeof_stat ==
12783+ sizeof(uint64_t)) ? (uint64_t) 0 : (uint32_t) 0;
12784+ }
12785+ }
12786+ if(copy_to_user(pAddr, &stats, sizeof(stats))) {
12787+ return -EFAULT;
12788+ }
12789+ return 0;
12790+ }
12791+#endif
12792+#ifdef ETHTOOL_PHYS_ID
12793+ case ETHTOOL_PHYS_ID: {
12794+ struct ethtool_value blinkSecs;
12795+ if(copy_from_user(&blinkSecs, pAddr, sizeof(blinkSecs))) {
12796+ return -EFAULT;
12797+ }
12798+ return startLocateNIC(pAC, port, &blinkSecs);
12799+ }
12800+#endif
12801+#ifdef ETHTOOL_GPAUSEPARAM
12802+ case ETHTOOL_GPAUSEPARAM: {
12803+ struct ethtool_pauseparam epause = { ETHTOOL_GPAUSEPARAM };
12804+ getPauseParams(pAC, port, &epause);
12805+ if(copy_to_user(pAddr, &epause, sizeof(epause))) {
12806+ return -EFAULT;
12807+ }
12808+ return 0;
12809+ }
12810+#endif
12811+#ifdef ETHTOOL_SPAUSEPARAM
12812+ case ETHTOOL_SPAUSEPARAM: {
12813+ struct ethtool_pauseparam epause;
12814+ if(copy_from_user(&epause, pAddr, sizeof(epause))) {
12815+ return -EFAULT;
12816+ }
12817+ return setPauseParams(pAC, port, &epause);
12818+ }
12819+#endif
12820+#ifdef ETHTOOL_GSG
12821+ case ETHTOOL_GSG: {
12822+ struct ethtool_value edata = { ETHTOOL_GSG };
12823+ edata.data = (netdev->features & NETIF_F_SG) != 0;
12824+ if (copy_to_user(pAddr, &edata, sizeof(edata))) {
12825+ return -EFAULT;
12826+ }
12827+ return 0;
12828+ }
12829+#endif
12830+#ifdef ETHTOOL_SSG
12831+ case ETHTOOL_SSG: {
12832+ struct ethtool_value edata;
12833+ if (copy_from_user(&edata, pAddr, sizeof(edata))) {
12834+ return -EFAULT;
12835+ }
12836+ if (pAC->ChipsetType) { /* Don't handle if Genesis */
12837+ if (edata.data) {
12838+ netdev->features |= NETIF_F_SG;
12839+ } else {
12840+ netdev->features &= ~NETIF_F_SG;
12841+ }
12842+ }
12843+ return 0;
12844+ }
12845+#endif
12846+#ifdef ETHTOOL_GRXCSUM
12847+ case ETHTOOL_GRXCSUM: {
12848+ struct ethtool_value edata = { ETHTOOL_GRXCSUM };
12849+ edata.data = pAC->RxPort[port].UseRxCsum;
12850+ if (copy_to_user(pAddr, &edata, sizeof(edata))) {
12851+ return -EFAULT;
12852+ }
12853+ return 0;
12854+ }
12855+#endif
12856+#ifdef ETHTOOL_SRXCSUM
12857+ case ETHTOOL_SRXCSUM: {
12858+ struct ethtool_value edata;
12859+ if (copy_from_user(&edata, pAddr, sizeof(edata))) {
12860+ return -EFAULT;
12861+ }
12862+ pAC->RxPort[port].UseRxCsum = edata.data;
12863+ return 0;
12864+ }
12865+#endif
12866+#ifdef ETHTOOL_GTXCSUM
12867+ case ETHTOOL_GTXCSUM: {
12868+ struct ethtool_value edata = { ETHTOOL_GTXCSUM };
12869+ edata.data = ((netdev->features & NETIF_F_IP_CSUM) != 0);
12870+ if (copy_to_user(pAddr, &edata, sizeof(edata))) {
12871+ return -EFAULT;
12872+ }
12873+ return 0;
12874+ }
12875+#endif
12876+#ifdef ETHTOOL_STXCSUM
12877+ case ETHTOOL_STXCSUM: {
12878+ struct ethtool_value edata;
12879+ if (copy_from_user(&edata, pAddr, sizeof(edata))) {
12880+ return -EFAULT;
12881+ }
12882+ if (pAC->ChipsetType) { /* Don't handle if Genesis */
12883+ if (edata.data) {
12884+ netdev->features |= NETIF_F_IP_CSUM;
12885+ } else {
12886+ netdev->features &= ~NETIF_F_IP_CSUM;
12887+ }
12888+ }
12889+ return 0;
12890+ }
12891+#endif
12892+#ifdef ETHTOOL_NWAY_RST
12893+ case ETHTOOL_NWAY_RST: {
12894+ if(netif_running(netdev)) {
12895+ (*netdev->stop)(netdev);
12896+ (*netdev->open)(netdev);
12897+ }
12898+ return 0;
12899+ }
12900+#endif
12901+#ifdef NETIF_F_TSO
12902+#ifdef ETHTOOL_GTSO
12903+ case ETHTOOL_GTSO: {
12904+ struct ethtool_value edata = { ETHTOOL_GTSO };
12905+ edata.data = (netdev->features & NETIF_F_TSO) != 0;
12906+ if (copy_to_user(pAddr, &edata, sizeof(edata))) {
12907+ return -EFAULT;
12908+ }
12909+ return 0;
12910+ }
12911+#endif
12912+#ifdef ETHTOOL_STSO
12913+ case ETHTOOL_STSO: {
12914+ struct ethtool_value edata;
12915+ if (CHIP_ID_YUKON_2(pAC)) {
12916+ if (copy_from_user(&edata, pAddr, sizeof(edata))) {
12917+ return -EFAULT;
12918+ }
12919+ if (edata.data) {
12920+ netdev->features |= NETIF_F_TSO;
12921+ } else {
12922+ netdev->features &= ~NETIF_F_TSO;
12923+ }
12924+ return 0;
12925+ }
12926+ return -EOPNOTSUPP;
12927+ }
12928+#endif
12929+#endif
12930+#ifdef ETHTOOL_GCOALESCE
12931+ case ETHTOOL_GCOALESCE: {
12932+ struct ethtool_coalesce ecoalesc = { ETHTOOL_GCOALESCE };
12933+ getModerationParams(pAC, port, &ecoalesc);
12934+ if(copy_to_user(pAddr, &ecoalesc, sizeof(ecoalesc))) {
12935+ return -EFAULT;
12936+ }
12937+ return 0;
12938+ }
12939+#endif
12940+#ifdef ETHTOOL_SCOALESCE
12941+ case ETHTOOL_SCOALESCE: {
12942+ struct ethtool_coalesce ecoalesc;
12943+ if(copy_from_user(&ecoalesc, pAddr, sizeof(ecoalesc))) {
12944+ return -EFAULT;
12945+ }
12946+ return setModerationParams(pAC, port, &ecoalesc);
12947+ }
12948+#endif
12949+#ifdef ETHTOOL_GWOL
12950+ case ETHTOOL_GWOL: {
12951+ struct ethtool_wolinfo ewol = { ETHTOOL_GWOL };
12952+ getWOLsettings(pAC, port, &ewol);
12953+ if(copy_to_user(pAddr, &ewol, sizeof(ewol))) {
12954+ return -EFAULT;
12955+ }
12956+ return 0;
12957+ }
12958+#endif
12959+#ifdef ETHTOOL_SWOL
12960+ case ETHTOOL_SWOL: {
12961+ struct ethtool_wolinfo ewol;
12962+ if(copy_from_user(&ewol, pAddr, sizeof(ewol))) {
12963+ return -EFAULT;
12964+ }
12965+ return setWOLsettings(pAC, port, &ewol);
12966+ }
12967+#endif
12968+ default:
12969+ return -EOPNOTSUPP;
12970+ }
12971+} /* SkEthIoctl() */
12972
12973 /******************************************************************************
12974 *
12975@@ -72,6 +531,7 @@
12976 *
12977 *****************************************************************************/
12978
12979+#ifdef ETHTOOL_GSET
12980 /*****************************************************************************
12981 *
12982 * getSettings - retrieves the current settings of the selected adapter
12983@@ -81,15 +541,15 @@
12984 * This configuration involves a)speed, b)duplex and c)autoneg plus
12985 * a number of other variables.
12986 *
12987- * Returns: always 0
12988+ * Returns: N/A
12989 *
12990 */
12991-static int getSettings(struct net_device *dev, struct ethtool_cmd *ecmd)
12992+static void getSettings(
12993+SK_AC *pAC, /* pointer to adapter control context */
12994+int port, /* the port of the selected adapter */
12995+struct ethtool_cmd *ecmd) /* mandatory command structure for results */
12996 {
12997- const DEV_NET *pNet = netdev_priv(dev);
12998- int port = pNet->PortNr;
12999- const SK_AC *pAC = pNet->pAC;
13000- const SK_GEPORT *pPort = &pAC->GIni.GP[port];
13001+ SK_GEPORT *pPort = &pAC->GIni.GP[port];
13002
13003 static int DuplexAutoNegConfMap[9][3]= {
13004 { -1 , -1 , -1 },
13005@@ -102,6 +562,7 @@
13006 { SK_LMODE_AUTOSENSE , -1 , -1 },
13007 { SK_LMODE_INDETERMINATED, -1 , -1 }
13008 };
13009+
13010 static int SpeedConfMap[6][2] = {
13011 { 0 , -1 },
13012 { SK_LSPEED_AUTO , -1 },
13013@@ -110,6 +571,7 @@
13014 { SK_LSPEED_1000MBPS , SPEED_1000 },
13015 { SK_LSPEED_INDETERMINATED, -1 }
13016 };
13017+
13018 static int AdvSpeedMap[6][2] = {
13019 { 0 , -1 },
13020 { SK_LSPEED_AUTO , -1 },
13021@@ -137,12 +599,10 @@
13022 if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {
13023 ecmd->supported &= ~(SUPPORTED_1000baseT_Half);
13024 }
13025-#ifdef CHIP_ID_YUKON_FE
13026 if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) {
13027 ecmd->supported &= ~(SUPPORTED_1000baseT_Half);
13028 ecmd->supported &= ~(SUPPORTED_1000baseT_Full);
13029 }
13030-#endif
13031 }
13032 if (pAC->GIni.GP[0].PLinkSpeed != SK_LSPEED_AUTO) {
13033 ecmd->advertising = AdvSpeedMap[pPort->PLinkSpeed][1];
13034@@ -152,26 +612,20 @@
13035 } else {
13036 ecmd->advertising = ecmd->supported;
13037 }
13038-
13039- if (ecmd->autoneg == AUTONEG_ENABLE)
13040+ if (ecmd->autoneg == AUTONEG_ENABLE) {
13041 ecmd->advertising |= ADVERTISED_Autoneg;
13042+ } else {
13043+ ecmd->advertising = ADVERTISED_TP;
13044+ }
13045 } else {
13046 ecmd->port = PORT_FIBRE;
13047- ecmd->supported = SUPP_FIBRE_ALL;
13048- ecmd->advertising = ADV_FIBRE_ALL;
13049+ ecmd->supported = (SUPP_FIBRE_ALL);
13050+ ecmd->advertising = (ADV_FIBRE_ALL);
13051 }
13052- return 0;
13053-}
13054-
13055-/*
13056- * MIB infrastructure uses instance value starting at 1
13057- * based on board and port.
13058- */
13059-static inline u32 pnmiInstance(const DEV_NET *pNet)
13060-{
13061- return 1 + (pNet->pAC->RlmtNets == 2) + pNet->PortNr;
13062 }
13063+#endif
13064
13065+#ifdef ETHTOOL_SSET
13066 /*****************************************************************************
13067 *
13068 * setSettings - configures the settings of a selected adapter
13069@@ -181,422 +635,722 @@
13070 * c)autonegotiation.
13071 *
13072 * Returns:
13073- * 0: everything fine, no error
13074- * <0: the return value is the error code of the failure
13075+ * ==0: everything fine, no error
13076+ * !=0: the return value is the error code of the failure
13077 */
13078-static int setSettings(struct net_device *dev, struct ethtool_cmd *ecmd)
13079+static int setSettings(
13080+SK_AC *pAC, /* pointer to adapter control context */
13081+int port, /* the port of the selected adapter */
13082+struct ethtool_cmd *ecmd) /* command structure containing settings */
13083 {
13084- DEV_NET *pNet = netdev_priv(dev);
13085- SK_AC *pAC = pNet->pAC;
13086- u32 instance;
13087- char buf[4];
13088- int len = 1;
13089+ DEV_NET *pNet = (DEV_NET *) pAC->dev[port]->priv;
13090+ SK_U32 Instance;
13091+ char Buf[4];
13092+ unsigned int Len = 1;
13093+ int Ret;
13094
13095- if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100
13096- && ecmd->speed != SPEED_1000)
13097- return -EINVAL;
13098-
13099- if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
13100- return -EINVAL;
13101+ if (port == 0) {
13102+ Instance = (pAC->RlmtNets == 2) ? 1 : 2;
13103+ } else {
13104+ Instance = (pAC->RlmtNets == 2) ? 2 : 3;
13105+ }
13106
13107- if (ecmd->autoneg != AUTONEG_DISABLE && ecmd->autoneg != AUTONEG_ENABLE)
13108- return -EINVAL;
13109+ if (((ecmd->autoneg == AUTONEG_DISABLE) || (ecmd->autoneg == AUTONEG_ENABLE)) &&
13110+ ((ecmd->duplex == DUPLEX_FULL) || (ecmd->duplex == DUPLEX_HALF))) {
13111+ if (ecmd->autoneg == AUTONEG_DISABLE) {
13112+ if (ecmd->duplex == DUPLEX_FULL) {
13113+ *Buf = (char) SK_LMODE_FULL;
13114+ } else {
13115+ *Buf = (char) SK_LMODE_HALF;
13116+ }
13117+ } else {
13118+ if (ecmd->duplex == DUPLEX_FULL) {
13119+ *Buf = (char) SK_LMODE_AUTOFULL;
13120+ } else {
13121+ *Buf = (char) SK_LMODE_AUTOHALF;
13122+ }
13123+ }
13124
13125- if (ecmd->autoneg == AUTONEG_DISABLE)
13126- *buf = (ecmd->duplex == DUPLEX_FULL)
13127- ? SK_LMODE_FULL : SK_LMODE_HALF;
13128- else
13129- *buf = (ecmd->duplex == DUPLEX_FULL)
13130- ? SK_LMODE_AUTOFULL : SK_LMODE_AUTOHALF;
13131+ Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_LINK_MODE,
13132+ &Buf, &Len, Instance, pNet->NetNr);
13133
13134- instance = pnmiInstance(pNet);
13135- if (SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_LINK_MODE,
13136- &buf, &len, instance, pNet->NetNr) != SK_PNMI_ERR_OK)
13137- return -EINVAL;
13138-
13139- switch(ecmd->speed) {
13140- case SPEED_1000:
13141- *buf = SK_LSPEED_1000MBPS;
13142- break;
13143- case SPEED_100:
13144- *buf = SK_LSPEED_100MBPS;
13145- break;
13146- case SPEED_10:
13147- *buf = SK_LSPEED_10MBPS;
13148+ if (Ret != SK_PNMI_ERR_OK) {
13149+ return -EINVAL;
13150+ }
13151+ } else if (ecmd->autoneg == AUTONEG_ENABLE) {
13152+ /* Set default values */
13153+ *Buf = (char) SK_LMODE_AUTOFULL;
13154+ Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_LINK_MODE,
13155+ &Buf, &Len, Instance, pNet->NetNr);
13156 }
13157
13158- if (SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE,
13159- &buf, &len, instance, pNet->NetNr) != SK_PNMI_ERR_OK)
13160+ if ((ecmd->speed == SPEED_1000) ||
13161+ (ecmd->speed == SPEED_100) ||
13162+ (ecmd->speed == SPEED_10)) {
13163+ if (ecmd->autoneg == AUTONEG_ENABLE) {
13164+ *Buf = (char) SK_LSPEED_AUTO;
13165+ } else if (ecmd->speed == SPEED_1000) {
13166+ *Buf = (char) SK_LSPEED_1000MBPS;
13167+ } else if (ecmd->speed == SPEED_100) {
13168+ *Buf = (char) SK_LSPEED_100MBPS;
13169+ } else {
13170+ *Buf = (char) SK_LSPEED_10MBPS;
13171+ }
13172+
13173+ Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE,
13174+ &Buf, &Len, Instance, pNet->NetNr);
13175+
13176+ if (Ret != SK_PNMI_ERR_OK) {
13177+ return -EINVAL;
13178+ }
13179+ } else if (ecmd->autoneg == AUTONEG_ENABLE) {
13180+ *Buf = (char) SK_LSPEED_AUTO;
13181+ Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE,
13182+ &Buf, &Len, Instance, pNet->NetNr);
13183+ } else {
13184 return -EINVAL;
13185+ }
13186
13187 return 0;
13188 }
13189+#endif
13190
13191+#ifdef ETHTOOL_GPAUSEPARAM
13192 /*****************************************************************************
13193 *
13194- * getDriverInfo - returns generic driver and adapter information
13195+ * getPauseParams - retrieves the pause parameters
13196 *
13197 * Description:
13198- * Generic driver information is returned via this function, such as
13199- * the name of the driver, its version and and firmware version.
13200- * In addition to this, the location of the selected adapter is
13201- * returned as a bus info string (e.g. '01:05.0').
13202- *
13203+ * All current pause parameters of a selected adapter are placed
13204+ * in the passed ethtool_pauseparam structure and are returned.
13205+ *
13206 * Returns: N/A
13207 *
13208 */
13209-static void getDriverInfo(struct net_device *dev, struct ethtool_drvinfo *info)
13210+static void getPauseParams(
13211+SK_AC *pAC, /* pointer to adapter control context */
13212+int port, /* the port of the selected adapter */
13213+struct ethtool_pauseparam *epause) /* pause parameter struct for result */
13214 {
13215- const DEV_NET *pNet = netdev_priv(dev);
13216- const SK_AC *pAC = pNet->pAC;
13217- char vers[32];
13218-
13219- snprintf(vers, sizeof(vers)-1, VER_STRING "(v%d.%d)",
13220- (pAC->GIni.GIPciHwRev >> 4) & 0xf, pAC->GIni.GIPciHwRev & 0xf);
13221-
13222- strlcpy(info->driver, DRIVER_FILE_NAME, sizeof(info->driver));
13223- strcpy(info->version, vers);
13224- strcpy(info->fw_version, "N/A");
13225- strlcpy(info->bus_info, pci_name(pAC->PciDev), ETHTOOL_BUSINFO_LEN);
13226-}
13227-
13228-/*
13229- * Ethtool statistics support.
13230- */
13231-static const char StringsStats[][ETH_GSTRING_LEN] = {
13232- "rx_packets", "tx_packets",
13233- "rx_bytes", "tx_bytes",
13234- "rx_errors", "tx_errors",
13235- "rx_dropped", "tx_dropped",
13236- "multicasts", "collisions",
13237- "rx_length_errors", "rx_buffer_overflow_errors",
13238- "rx_crc_errors", "rx_frame_errors",
13239- "rx_too_short_errors", "rx_too_long_errors",
13240- "rx_carrier_extension_errors", "rx_symbol_errors",
13241- "rx_llc_mac_size_errors", "rx_carrier_errors",
13242- "rx_jabber_errors", "rx_missed_errors",
13243- "tx_abort_collision_errors", "tx_carrier_errors",
13244- "tx_buffer_underrun_errors", "tx_heartbeat_errors",
13245- "tx_window_errors",
13246-};
13247+ SK_GEPORT *pPort = &pAC->GIni.GP[port];
13248
13249-static int getStatsCount(struct net_device *dev)
13250-{
13251- return ARRAY_SIZE(StringsStats);
13252-}
13253+ epause->rx_pause = 0;
13254+ epause->tx_pause = 0;
13255
13256-static void getStrings(struct net_device *dev, u32 stringset, u8 *data)
13257-{
13258- switch(stringset) {
13259- case ETH_SS_STATS:
13260- memcpy(data, *StringsStats, sizeof(StringsStats));
13261- break;
13262+ if (pPort->PFlowCtrlMode == SK_FLOW_MODE_LOC_SEND) {
13263+ epause->tx_pause = 1;
13264+ }
13265+ if ((pPort->PFlowCtrlMode == SK_FLOW_MODE_SYMMETRIC) ||
13266+ (pPort->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM)) {
13267+ epause->tx_pause = 1;
13268+ epause->rx_pause = 1;
13269 }
13270-}
13271
13272-static void getEthtoolStats(struct net_device *dev,
13273- struct ethtool_stats *stats, u64 *data)
13274-{
13275- const DEV_NET *pNet = netdev_priv(dev);
13276- const SK_AC *pAC = pNet->pAC;
13277- const SK_PNMI_STRUCT_DATA *pPnmiStruct = &pAC->PnmiStruct;
13278-
13279- *data++ = pPnmiStruct->Stat[0].StatRxOkCts;
13280- *data++ = pPnmiStruct->Stat[0].StatTxOkCts;
13281- *data++ = pPnmiStruct->Stat[0].StatRxOctetsOkCts;
13282- *data++ = pPnmiStruct->Stat[0].StatTxOctetsOkCts;
13283- *data++ = pPnmiStruct->InErrorsCts;
13284- *data++ = pPnmiStruct->Stat[0].StatTxSingleCollisionCts;
13285- *data++ = pPnmiStruct->RxNoBufCts;
13286- *data++ = pPnmiStruct->TxNoBufCts;
13287- *data++ = pPnmiStruct->Stat[0].StatRxMulticastOkCts;
13288- *data++ = pPnmiStruct->Stat[0].StatTxSingleCollisionCts;
13289- *data++ = pPnmiStruct->Stat[0].StatRxRuntCts;
13290- *data++ = pPnmiStruct->Stat[0].StatRxFifoOverflowCts;
13291- *data++ = pPnmiStruct->Stat[0].StatRxFcsCts;
13292- *data++ = pPnmiStruct->Stat[0].StatRxFramingCts;
13293- *data++ = pPnmiStruct->Stat[0].StatRxShortsCts;
13294- *data++ = pPnmiStruct->Stat[0].StatRxTooLongCts;
13295- *data++ = pPnmiStruct->Stat[0].StatRxCextCts;
13296- *data++ = pPnmiStruct->Stat[0].StatRxSymbolCts;
13297- *data++ = pPnmiStruct->Stat[0].StatRxIRLengthCts;
13298- *data++ = pPnmiStruct->Stat[0].StatRxCarrierCts;
13299- *data++ = pPnmiStruct->Stat[0].StatRxJabberCts;
13300- *data++ = pPnmiStruct->Stat[0].StatRxMissedCts;
13301- *data++ = pAC->stats.tx_aborted_errors;
13302- *data++ = pPnmiStruct->Stat[0].StatTxCarrierCts;
13303- *data++ = pPnmiStruct->Stat[0].StatTxFifoUnderrunCts;
13304- *data++ = pPnmiStruct->Stat[0].StatTxCarrierCts;
13305- *data++ = pAC->stats.tx_window_errors;
13306+ if ((epause->rx_pause == 0) && (epause->tx_pause == 0)) {
13307+ epause->autoneg = SK_FALSE;
13308+ } else {
13309+ epause->autoneg = SK_TRUE;
13310+ }
13311 }
13312+#endif
13313
13314-
13315+#ifdef ETHTOOL_SPAUSEPARAM
13316 /*****************************************************************************
13317 *
13318- * toggleLeds - Changes the LED state of an adapter
13319+ * setPauseParams - configures the pause parameters of an adapter
13320 *
13321 * Description:
13322- * This function changes the current state of all LEDs of an adapter so
13323- * that it can be located by a user.
13324- *
13325- * Returns: N/A
13326+ * This function sets the Rx or Tx pause parameters
13327 *
13328+ * Returns:
13329+ * ==0: everything fine, no error
13330+ * !=0: the return value is the error code of the failure
13331 */
13332-static void toggleLeds(DEV_NET *pNet, int on)
13333+static int setPauseParams(
13334+SK_AC *pAC, /* pointer to adapter control context */
13335+int port, /* the port of the selected adapter */
13336+struct ethtool_pauseparam *epause) /* pause parameter struct with params */
13337 {
13338- SK_AC *pAC = pNet->pAC;
13339- int port = pNet->PortNr;
13340- void __iomem *io = pAC->IoBase;
13341-
13342- if (pAC->GIni.GIGenesis) {
13343- SK_OUT8(io, MR_ADDR(port,LNK_LED_REG),
13344- on ? SK_LNK_ON : SK_LNK_OFF);
13345- SkGeYellowLED(pAC, io,
13346- on ? (LED_ON >> 1) : (LED_OFF >> 1));
13347- SkGeXmitLED(pAC, io, MR_ADDR(port,RX_LED_INI),
13348- on ? SK_LED_TST : SK_LED_DIS);
13349-
13350- if (pAC->GIni.GP[port].PhyType == SK_PHY_BCOM)
13351- SkXmPhyWrite(pAC, io, port, PHY_BCOM_P_EXT_CTRL,
13352- on ? PHY_B_PEC_LED_ON : PHY_B_PEC_LED_OFF);
13353- else if (pAC->GIni.GP[port].PhyType == SK_PHY_LONE)
13354- SkXmPhyWrite(pAC, io, port, PHY_LONE_LED_CFG,
13355- on ? 0x0800 : PHY_L_LC_LEDT);
13356- else
13357- SkGeXmitLED(pAC, io, MR_ADDR(port,TX_LED_INI),
13358- on ? SK_LED_TST : SK_LED_DIS);
13359+ SK_GEPORT *pPort = &pAC->GIni.GP[port];
13360+ DEV_NET *pNet = (DEV_NET *) pAC->dev[port]->priv;
13361+ int PrevSpeedVal = pPort->PLinkSpeedUsed;
13362+
13363+ SK_U32 Instance;
13364+ char Buf[4];
13365+ int Ret;
13366+ SK_BOOL prevAutonegValue = SK_TRUE;
13367+ int prevTxPause = 0;
13368+ int prevRxPause = 0;
13369+ unsigned int Len = 1;
13370+
13371+ if (port == 0) {
13372+ Instance = (pAC->RlmtNets == 2) ? 1 : 2;
13373+ } else {
13374+ Instance = (pAC->RlmtNets == 2) ? 2 : 3;
13375+ }
13376+
13377+ /*
13378+ ** we have to determine the current settings to see if
13379+ ** the operator requested any modification of the flow
13380+ ** control parameters...
13381+ */
13382+ if (pPort->PFlowCtrlMode == SK_FLOW_MODE_LOC_SEND) {
13383+ prevTxPause = 1;
13384+ }
13385+ if ((pPort->PFlowCtrlMode == SK_FLOW_MODE_SYMMETRIC) ||
13386+ (pPort->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM)) {
13387+ prevTxPause = 1;
13388+ prevRxPause = 1;
13389+ }
13390+
13391+ if ((prevRxPause == 0) && (prevTxPause == 0)) {
13392+ prevAutonegValue = SK_FALSE;
13393+ }
13394+
13395+
13396+ /*
13397+ ** perform modifications regarding the changes
13398+ ** requested by the operator
13399+ */
13400+ if (epause->autoneg != prevAutonegValue) {
13401+ if (epause->autoneg == AUTONEG_DISABLE) {
13402+ *Buf = (char) SK_FLOW_MODE_NONE;
13403+ } else {
13404+ *Buf = (char) SK_FLOW_MODE_SYMMETRIC;
13405+ }
13406 } else {
13407- const u16 YukLedOn = (PHY_M_LED_MO_DUP(MO_LED_ON) |
13408- PHY_M_LED_MO_10(MO_LED_ON) |
13409- PHY_M_LED_MO_100(MO_LED_ON) |
13410- PHY_M_LED_MO_1000(MO_LED_ON) |
13411- PHY_M_LED_MO_RX(MO_LED_ON));
13412- const u16 YukLedOff = (PHY_M_LED_MO_DUP(MO_LED_OFF) |
13413- PHY_M_LED_MO_10(MO_LED_OFF) |
13414- PHY_M_LED_MO_100(MO_LED_OFF) |
13415- PHY_M_LED_MO_1000(MO_LED_OFF) |
13416- PHY_M_LED_MO_RX(MO_LED_OFF));
13417-
13418+ if(epause->rx_pause && epause->tx_pause) {
13419+ *Buf = (char) SK_FLOW_MODE_SYMMETRIC;
13420+ } else if (epause->rx_pause && !epause->tx_pause) {
13421+ *Buf = (char) SK_FLOW_MODE_SYM_OR_REM;
13422+ } else if(!epause->rx_pause && epause->tx_pause) {
13423+ *Buf = (char) SK_FLOW_MODE_LOC_SEND;
13424+ } else {
13425+ *Buf = (char) SK_FLOW_MODE_NONE;
13426+ }
13427+ }
13428+
13429+ Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_FLOWCTRL_MODE,
13430+ &Buf, &Len, Instance, pNet->NetNr);
13431+
13432+ if (Ret != SK_PNMI_ERR_OK) {
13433+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_CTRL,
13434+ ("ethtool (sk98lin): error changing rx/tx pause (%i)\n", Ret));
13435+ } else {
13436+ Len = 1; /* set buffer length to correct value */
13437+ }
13438+
13439+ /*
13440+ ** It may be that autoneg has been disabled! Therefore
13441+ ** set the speed to the previously used value...
13442+ */
13443+ *Buf = (char) PrevSpeedVal;
13444
13445- SkGmPhyWrite(pAC,io,port,PHY_MARV_LED_CTRL,0);
13446- SkGmPhyWrite(pAC,io,port,PHY_MARV_LED_OVER,
13447- on ? YukLedOn : YukLedOff);
13448+ Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE,
13449+ &Buf, &Len, Instance, pNet->NetNr);
13450+
13451+ if (Ret != SK_PNMI_ERR_OK) {
13452+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_CTRL,
13453+ ("ethtool (sk98lin): error setting speed (%i)\n", Ret));
13454 }
13455+ return 0;
13456 }
13457+#endif
13458
13459+#ifdef ETHTOOL_GCOALESCE
13460 /*****************************************************************************
13461 *
13462- * skGeBlinkTimer - Changes the LED state of an adapter
13463+ * getModerationParams - retrieves the IRQ moderation settings
13464 *
13465 * Description:
13466- * This function changes the current state of all LEDs of an adapter so
13467- * that it can be located by a user. If the requested time interval for
13468- * this test has elapsed, this function cleans up everything that was
13469- * temporarily setup during the locate NIC test. This involves of course
13470- * also closing or opening any adapter so that the initial board state
13471- * is recovered.
13472+ * All current IRQ moderation settings of a selected adapter are placed
13473+ * in the passed ethtool_coalesce structure and are returned.
13474 *
13475 * Returns: N/A
13476 *
13477 */
13478-void SkGeBlinkTimer(unsigned long data)
13479+static void getModerationParams(
13480+SK_AC *pAC, /* pointer to adapter control context */
13481+int port, /* the port of the selected adapter */
13482+struct ethtool_coalesce *ecoalesc) /* IRQ moderation struct for results */
13483 {
13484- struct net_device *dev = (struct net_device *) data;
13485- DEV_NET *pNet = netdev_priv(dev);
13486- SK_AC *pAC = pNet->pAC;
13487-
13488- toggleLeds(pNet, pAC->LedsOn);
13489+ DIM_INFO *Info = &pAC->DynIrqModInfo;
13490+ SK_BOOL UseTxIrqModeration = SK_FALSE;
13491+ SK_BOOL UseRxIrqModeration = SK_FALSE;
13492+
13493+ if (Info->IntModTypeSelect != C_INT_MOD_NONE) {
13494+ if (CHIP_ID_YUKON_2(pAC)) {
13495+ UseRxIrqModeration = SK_TRUE;
13496+ UseTxIrqModeration = SK_TRUE;
13497+ } else {
13498+ if ((Info->MaskIrqModeration == IRQ_MASK_RX_ONLY) ||
13499+ (Info->MaskIrqModeration == IRQ_MASK_SP_RX) ||
13500+ (Info->MaskIrqModeration == IRQ_MASK_RX_TX_SP)) {
13501+ UseRxIrqModeration = SK_TRUE;
13502+ }
13503+ if ((Info->MaskIrqModeration == IRQ_MASK_TX_ONLY) ||
13504+ (Info->MaskIrqModeration == IRQ_MASK_SP_TX) ||
13505+ (Info->MaskIrqModeration == IRQ_MASK_RX_TX_SP)) {
13506+ UseTxIrqModeration = SK_TRUE;
13507+ }
13508+ }
13509
13510- pAC->LedsOn = !pAC->LedsOn;
13511- mod_timer(&pAC->BlinkTimer, jiffies + HZ/4);
13512+ if (UseRxIrqModeration) {
13513+ ecoalesc->rx_coalesce_usecs = 1000000 / Info->MaxModIntsPerSec;
13514+ }
13515+ if (UseTxIrqModeration) {
13516+ ecoalesc->tx_coalesce_usecs = 1000000 / Info->MaxModIntsPerSec;
13517+ }
13518+ if (Info->IntModTypeSelect == C_INT_MOD_DYNAMIC) {
13519+ ecoalesc->rate_sample_interval = Info->DynIrqModSampleInterval;
13520+ if (UseRxIrqModeration) {
13521+ ecoalesc->use_adaptive_rx_coalesce = 1;
13522+ ecoalesc->rx_coalesce_usecs_low =
13523+ 1000000 / Info->MaxModIntsPerSecLowerLimit;
13524+ ecoalesc->rx_coalesce_usecs_high =
13525+ 1000000 / Info->MaxModIntsPerSecUpperLimit;
13526+ }
13527+ if (UseTxIrqModeration) {
13528+ ecoalesc->use_adaptive_tx_coalesce = 1;
13529+ ecoalesc->tx_coalesce_usecs_low =
13530+ 1000000 / Info->MaxModIntsPerSecLowerLimit;
13531+ ecoalesc->tx_coalesce_usecs_high =
13532+ 1000000 / Info->MaxModIntsPerSecUpperLimit;
13533+ }
13534+ }
13535+ }
13536 }
13537+#endif
13538
13539+#ifdef ETHTOOL_SCOALESCE
13540 /*****************************************************************************
13541 *
13542- * locateDevice - start the locate NIC feature of the elected adapter
13543+ * setModerationParams - configures the IRQ moderation of an adapter
13544 *
13545 * Description:
13546- * This function is used if the user want to locate a particular NIC.
13547- * All LEDs are regularly switched on and off, so the NIC can easily
13548- * be identified.
13549+ * Depending on the desired IRQ moderation parameters, either a) static,
13550+ * b) dynamic or c) no moderation is configured.
13551 *
13552- * Returns:
13553- * ==0: everything fine, no error, locateNIC test was started
13554- * !=0: one locateNIC test runs already
13555+ * Returns:
13556+ * ==0: everything fine, no error
13557+ * !=0: the return value is the error code of the failure
13558 *
13559+ * Notes:
13560+ * The supported timeframe for the coalesced interrupts ranges from
13561+ * 33.333us (30 IntsPerSec) down to 25us (40.000 IntsPerSec).
13562+ * Any requested value that is not in this range will abort the request!
13563 */
13564-static int locateDevice(struct net_device *dev, u32 data)
13565+static int setModerationParams(
13566+SK_AC *pAC, /* pointer to adapter control context */
13567+int port, /* the port of the selected adapter */
13568+struct ethtool_coalesce *ecoalesc) /* IRQ moderation struct with params */
13569 {
13570- DEV_NET *pNet = netdev_priv(dev);
13571- SK_AC *pAC = pNet->pAC;
13572+ DIM_INFO *Info = &pAC->DynIrqModInfo;
13573+ int PrevModeration = Info->IntModTypeSelect;
13574
13575- if(!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
13576- data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
13577+ Info->IntModTypeSelect = C_INT_MOD_NONE; /* initial default */
13578
13579- /* start blinking */
13580- pAC->LedsOn = 0;
13581- mod_timer(&pAC->BlinkTimer, jiffies);
13582- msleep_interruptible(data * 1000);
13583- del_timer_sync(&pAC->BlinkTimer);
13584- toggleLeds(pNet, 0);
13585+ if ((ecoalesc->rx_coalesce_usecs) || (ecoalesc->tx_coalesce_usecs)) {
13586+ if (ecoalesc->rx_coalesce_usecs) {
13587+ if ((ecoalesc->rx_coalesce_usecs < 25) ||
13588+ (ecoalesc->rx_coalesce_usecs > 33333)) {
13589+ return -EINVAL;
13590+ }
13591+ }
13592+ if (ecoalesc->tx_coalesce_usecs) {
13593+ if ((ecoalesc->tx_coalesce_usecs < 25) ||
13594+ (ecoalesc->tx_coalesce_usecs > 33333)) {
13595+ return -EINVAL;
13596+ }
13597+ }
13598+ if (!CHIP_ID_YUKON_2(pAC)) {
13599+ if ((Info->MaskIrqModeration == IRQ_MASK_SP_RX) ||
13600+ (Info->MaskIrqModeration == IRQ_MASK_SP_TX) ||
13601+ (Info->MaskIrqModeration == IRQ_MASK_RX_TX_SP)) {
13602+ Info->MaskIrqModeration = IRQ_MASK_SP_ONLY;
13603+ }
13604+ }
13605+ Info->IntModTypeSelect = C_INT_MOD_STATIC;
13606+ if (ecoalesc->rx_coalesce_usecs) {
13607+ Info->MaxModIntsPerSec =
13608+ 1000000 / ecoalesc->rx_coalesce_usecs;
13609+ if (!CHIP_ID_YUKON_2(pAC)) {
13610+ if (Info->MaskIrqModeration == IRQ_MASK_TX_ONLY) {
13611+ Info->MaskIrqModeration = IRQ_MASK_TX_RX;
13612+ }
13613+ if (Info->MaskIrqModeration == IRQ_MASK_SP_ONLY) {
13614+ Info->MaskIrqModeration = IRQ_MASK_SP_RX;
13615+ }
13616+ if (Info->MaskIrqModeration == IRQ_MASK_SP_TX) {
13617+ Info->MaskIrqModeration = IRQ_MASK_RX_TX_SP;
13618+ }
13619+ } else {
13620+ Info->MaskIrqModeration = Y2_IRQ_MASK;
13621+ }
13622+ }
13623+ if (ecoalesc->tx_coalesce_usecs) {
13624+ Info->MaxModIntsPerSec =
13625+ 1000000 / ecoalesc->tx_coalesce_usecs;
13626+ if (!CHIP_ID_YUKON_2(pAC)) {
13627+ if (Info->MaskIrqModeration == IRQ_MASK_RX_ONLY) {
13628+ Info->MaskIrqModeration = IRQ_MASK_TX_RX;
13629+ }
13630+ if (Info->MaskIrqModeration == IRQ_MASK_SP_ONLY) {
13631+ Info->MaskIrqModeration = IRQ_MASK_SP_TX;
13632+ }
13633+ if (Info->MaskIrqModeration == IRQ_MASK_SP_RX) {
13634+ Info->MaskIrqModeration = IRQ_MASK_RX_TX_SP;
13635+ }
13636+ } else {
13637+ Info->MaskIrqModeration = Y2_IRQ_MASK;
13638+ }
13639+ }
13640+ }
13641+ if ((ecoalesc->rate_sample_interval) ||
13642+ (ecoalesc->rx_coalesce_usecs_low) ||
13643+ (ecoalesc->tx_coalesce_usecs_low) ||
13644+ (ecoalesc->rx_coalesce_usecs_high)||
13645+ (ecoalesc->tx_coalesce_usecs_high)) {
13646+ if (ecoalesc->rate_sample_interval) {
13647+ if ((ecoalesc->rate_sample_interval < 1) ||
13648+ (ecoalesc->rate_sample_interval > 10)) {
13649+ return -EINVAL;
13650+ }
13651+ }
13652+ if (ecoalesc->rx_coalesce_usecs_low) {
13653+ if ((ecoalesc->rx_coalesce_usecs_low < 25) ||
13654+ (ecoalesc->rx_coalesce_usecs_low > 33333)) {
13655+ return -EINVAL;
13656+ }
13657+ }
13658+ if (ecoalesc->rx_coalesce_usecs_high) {
13659+ if ((ecoalesc->rx_coalesce_usecs_high < 25) ||
13660+ (ecoalesc->rx_coalesce_usecs_high > 33333)) {
13661+ return -EINVAL;
13662+ }
13663+ }
13664+ if (ecoalesc->tx_coalesce_usecs_low) {
13665+ if ((ecoalesc->tx_coalesce_usecs_low < 25) ||
13666+ (ecoalesc->tx_coalesce_usecs_low > 33333)) {
13667+ return -EINVAL;
13668+ }
13669+ }
13670+ if (ecoalesc->tx_coalesce_usecs_high) {
13671+ if ((ecoalesc->tx_coalesce_usecs_high < 25) ||
13672+ (ecoalesc->tx_coalesce_usecs_high > 33333)) {
13673+ return -EINVAL;
13674+ }
13675+ }
13676
13677- return 0;
13678+ Info->IntModTypeSelect = C_INT_MOD_DYNAMIC;
13679+ if (ecoalesc->rate_sample_interval) {
13680+ Info->DynIrqModSampleInterval =
13681+ ecoalesc->rate_sample_interval;
13682+ }
13683+ if (ecoalesc->rx_coalesce_usecs_low) {
13684+ Info->MaxModIntsPerSecLowerLimit =
13685+ 1000000 / ecoalesc->rx_coalesce_usecs_low;
13686+ }
13687+ if (ecoalesc->tx_coalesce_usecs_low) {
13688+ Info->MaxModIntsPerSecLowerLimit =
13689+ 1000000 / ecoalesc->tx_coalesce_usecs_low;
13690+ }
13691+ if (ecoalesc->rx_coalesce_usecs_high) {
13692+ Info->MaxModIntsPerSecUpperLimit =
13693+ 1000000 / ecoalesc->rx_coalesce_usecs_high;
13694+ }
13695+ if (ecoalesc->tx_coalesce_usecs_high) {
13696+ Info->MaxModIntsPerSecUpperLimit =
13697+ 1000000 / ecoalesc->tx_coalesce_usecs_high;
13698+ }
13699+ }
13700+
13701+ if ((PrevModeration == C_INT_MOD_NONE) &&
13702+ (Info->IntModTypeSelect != C_INT_MOD_NONE)) {
13703+ SkDimEnableModerationIfNeeded(pAC);
13704+ }
13705+ if (PrevModeration != C_INT_MOD_NONE) {
13706+ SkDimDisableModeration(pAC, PrevModeration);
13707+ if (Info->IntModTypeSelect != C_INT_MOD_NONE) {
13708+ SkDimEnableModerationIfNeeded(pAC);
13709+ }
13710+ }
13711+
13712+ return 0;
13713 }
13714+#endif
13715
13716+#ifdef ETHTOOL_GWOL
13717 /*****************************************************************************
13718 *
13719- * getPauseParams - retrieves the pause parameters
13720+ * getWOLsettings - retrieves the WOL settings of the selected adapter
13721 *
13722 * Description:
13723- * All current pause parameters of a selected adapter are placed
13724- * in the passed ethtool_pauseparam structure and are returned.
13725+ * All current WOL settings of a selected adapter are placed in the
13726+ * passed ethtool_wolinfo structure and are returned to the caller.
13727 *
13728 * Returns: N/A
13729 *
13730 */
13731-static void getPauseParams(struct net_device *dev, struct ethtool_pauseparam *epause)
13732+static void getWOLsettings(
13733+SK_AC *pAC, /* pointer to adapter control context */
13734+int port, /* the port of the selected adapter */
13735+struct ethtool_wolinfo *ewol) /* mandatory WOL structure for results */
13736 {
13737- DEV_NET *pNet = netdev_priv(dev);
13738- SK_AC *pAC = pNet->pAC;
13739- SK_GEPORT *pPort = &pAC->GIni.GP[pNet->PortNr];
13740-
13741- epause->rx_pause = (pPort->PFlowCtrlMode == SK_FLOW_MODE_SYMMETRIC) ||
13742- (pPort->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM);
13743+ ewol->supported = pAC->WolInfo.SupportedWolOptions;
13744+ ewol->wolopts = pAC->WolInfo.ConfiguredWolOptions;
13745
13746- epause->tx_pause = epause->rx_pause || (pPort->PFlowCtrlMode == SK_FLOW_MODE_LOC_SEND);
13747- epause->autoneg = epause->rx_pause || epause->tx_pause;
13748+ return;
13749 }
13750+#endif
13751
13752+#ifdef ETHTOOL_SWOL
13753 /*****************************************************************************
13754 *
13755- * setPauseParams - configures the pause parameters of an adapter
13756+ * setWOLsettings - configures the WOL settings of a selected adapter
13757 *
13758 * Description:
13759- * This function sets the Rx or Tx pause parameters
13760+ * The WOL settings of a selected adapter are configured regarding
13761+ * the parameters in the passed ethtool_wolinfo structure.
13762+ * Note that currently only wake on magic packet is supported!
13763 *
13764 * Returns:
13765 * ==0: everything fine, no error
13766 * !=0: the return value is the error code of the failure
13767 */
13768-static int setPauseParams(struct net_device *dev , struct ethtool_pauseparam *epause)
13769+static int setWOLsettings(
13770+SK_AC *pAC, /* pointer to adapter control context */
13771+int port, /* the port of the selected adapter */
13772+struct ethtool_wolinfo *ewol) /* WOL structure containing settings */
13773 {
13774- DEV_NET *pNet = netdev_priv(dev);
13775- SK_AC *pAC = pNet->pAC;
13776- SK_GEPORT *pPort = &pAC->GIni.GP[pNet->PortNr];
13777- u32 instance = pnmiInstance(pNet);
13778- struct ethtool_pauseparam old;
13779- u8 oldspeed = pPort->PLinkSpeedUsed;
13780- char buf[4];
13781- int len = 1;
13782- int ret;
13783+ if (((ewol->wolopts & WAKE_MAGIC) == WAKE_MAGIC) || (ewol->wolopts == 0)) {
13784+ pAC->WolInfo.ConfiguredWolOptions = ewol->wolopts;
13785+ return 0;
13786+ }
13787+ return -EFAULT;
13788+}
13789+#endif
13790
13791- /*
13792- ** we have to determine the current settings to see if
13793- ** the operator requested any modification of the flow
13794- ** control parameters...
13795- */
13796- getPauseParams(dev, &old);
13797+#ifdef ETHTOOL_GDRVINFO
13798+/*****************************************************************************
13799+ *
13800+ * getDriverInfo - returns generic driver and adapter information
13801+ *
13802+ * Description:
13803+ * Generic driver information is returned via this function, such as
13804+ * the name of the driver, its version and and firmware version.
13805+ * In addition to this, the location of the selected adapter is
13806+ * returned as a bus info string (e.g. '01:05.0').
13807+ *
13808+ * Returns: N/A
13809+ *
13810+ */
13811+static void getDriverInfo(
13812+SK_AC *pAC, /* pointer to adapter control context */
13813+int port, /* the port of the selected adapter */
13814+struct ethtool_drvinfo *edrvinfo) /* mandatory info structure for results */
13815+{
13816+ char versionString[32];
13817
13818- /*
13819- ** perform modifications regarding the changes
13820- ** requested by the operator
13821- */
13822- if (epause->autoneg != old.autoneg)
13823- *buf = epause->autoneg ? SK_FLOW_MODE_NONE : SK_FLOW_MODE_SYMMETRIC;
13824- else {
13825- if (epause->rx_pause && epause->tx_pause)
13826- *buf = SK_FLOW_MODE_SYMMETRIC;
13827- else if (epause->rx_pause && !epause->tx_pause)
13828- *buf = SK_FLOW_MODE_SYM_OR_REM;
13829- else if (!epause->rx_pause && epause->tx_pause)
13830- *buf = SK_FLOW_MODE_LOC_SEND;
13831- else
13832- *buf = SK_FLOW_MODE_NONE;
13833+ snprintf(versionString, 32, "%s (%s)", VER_STRING, PATCHLEVEL);
13834+ strncpy(edrvinfo->driver, DRIVER_FILE_NAME , 32);
13835+ strncpy(edrvinfo->version, versionString , 32);
13836+ strncpy(edrvinfo->fw_version, "N/A", 32);
13837+ strncpy(edrvinfo->bus_info, pci_name(pAC->PciDev), 32);
13838+
13839+#ifdef ETHTOOL_GSTATS
13840+ edrvinfo->n_stats = SK98LIN_STATS_LEN;
13841+#endif
13842+}
13843+#endif
13844+
13845+#ifdef ETHTOOL_PHYS_ID
13846+/*****************************************************************************
13847+ *
13848+ * startLocateNIC - start the locate NIC feature of the elected adapter
13849+ *
13850+ * Description:
13851+ * This function is used if the user want to locate a particular NIC.
13852+ * All LEDs are regularly switched on and off, so the NIC can easily
13853+ * be identified.
13854+ *
13855+ * Returns:
13856+ * ==0: everything fine, no error, locateNIC test was started
13857+ * !=0: one locateNIC test runs already
13858+ *
13859+ */
13860+static int startLocateNIC(
13861+SK_AC *pAC, /* pointer to adapter control context */
13862+int port, /* the port of the selected adapter */
13863+struct ethtool_value *blinkSecs) /* how long the LEDs should blink in seconds */
13864+{
13865+ struct SK_NET_DEVICE *pDev = pAC->dev[port];
13866+ int OtherPort = (port) ? 0 : 1;
13867+ struct SK_NET_DEVICE *pOtherDev = pAC->dev[OtherPort];
13868+
13869+ if (isLocateNICrunning) {
13870+ return -EFAULT;
13871 }
13872+ isLocateNICrunning = SK_TRUE;
13873+ currentPortIndex = port;
13874+ isDualNetCard = (pDev != pOtherDev) ? SK_TRUE : SK_FALSE;
13875
13876- ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_FLOWCTRL_MODE,
13877- &buf, &len, instance, pNet->NetNr);
13878+ if (netif_running(pAC->dev[port])) {
13879+ boardWasDown[0] = SK_FALSE;
13880+ } else {
13881+ (*pDev->open)(pDev);
13882+ boardWasDown[0] = SK_TRUE;
13883+ }
13884
13885- if (ret != SK_PNMI_ERR_OK) {
13886- SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_CTRL,
13887- ("ethtool (sk98lin): error changing rx/tx pause (%i)\n", ret));
13888- goto err;
13889+ if (isDualNetCard) {
13890+ if (netif_running(pAC->dev[OtherPort])) {
13891+ boardWasDown[1] = SK_FALSE;
13892+ } else {
13893+ (*pOtherDev->open)(pOtherDev);
13894+ boardWasDown[1] = SK_TRUE;
13895+ }
13896 }
13897
13898- /*
13899- ** It may be that autoneg has been disabled! Therefore
13900- ** set the speed to the previously used value...
13901- */
13902- if (!epause->autoneg) {
13903- len = 1;
13904- ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE,
13905- &oldspeed, &len, instance, pNet->NetNr);
13906- if (ret != SK_PNMI_ERR_OK)
13907- SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_CTRL,
13908- ("ethtool (sk98lin): error setting speed (%i)\n", ret));
13909+ if ((blinkSecs->data < 1) || (blinkSecs->data > 30)) {
13910+ blinkSecs->data = 3; /* three seconds default */
13911 }
13912- err:
13913- return ret ? -EIO : 0;
13914-}
13915+ nbrBlinkQuarterSeconds = 4*blinkSecs->data;
13916
13917-/* Only Yukon supports checksum offload. */
13918-static int setScatterGather(struct net_device *dev, u32 data)
13919-{
13920- DEV_NET *pNet = netdev_priv(dev);
13921- SK_AC *pAC = pNet->pAC;
13922+ init_timer(&locateNICtimer);
13923+ locateNICtimer.function = toggleLeds;
13924+ locateNICtimer.data = (unsigned long) pAC;
13925+ locateNICtimer.expires = jiffies + HZ; /* initially 1sec */
13926+ add_timer(&locateNICtimer);
13927
13928- if (pAC->GIni.GIChipId == CHIP_ID_GENESIS)
13929- return -EOPNOTSUPP;
13930- return ethtool_op_set_sg(dev, data);
13931+ return 0;
13932 }
13933
13934-static int setTxCsum(struct net_device *dev, u32 data)
13935+/*****************************************************************************
13936+ *
13937+ * toggleLeds - Changes the LED state of an adapter
13938+ *
13939+ * Description:
13940+ * This function changes the current state of all LEDs of an adapter so
13941+ * that it can be located by a user. If the requested time interval for
13942+ * this test has elapsed, this function cleans up everything that was
13943+ * temporarily setup during the locate NIC test. This involves of course
13944+ * also closing or opening any adapter so that the initial board state
13945+ * is recovered.
13946+ *
13947+ * Returns: N/A
13948+ *
13949+ */
13950+static void toggleLeds(
13951+unsigned long ptr) /* holds the pointer to adapter control context */
13952 {
13953- DEV_NET *pNet = netdev_priv(dev);
13954- SK_AC *pAC = pNet->pAC;
13955-
13956- if (pAC->GIni.GIChipId == CHIP_ID_GENESIS)
13957- return -EOPNOTSUPP;
13958+ SK_AC *pAC = (SK_AC *) ptr;
13959+ int port = currentPortIndex;
13960+ SK_IOC IoC = pAC->IoBase;
13961+ struct SK_NET_DEVICE *pDev = pAC->dev[port];
13962+ int OtherPort = (port) ? 0 : 1;
13963+ struct SK_NET_DEVICE *pOtherDev = pAC->dev[OtherPort];
13964+
13965+ SK_U16 YukLedOn = (PHY_M_LED_MO_DUP(MO_LED_ON) |
13966+ PHY_M_LED_MO_10(MO_LED_ON) |
13967+ PHY_M_LED_MO_100(MO_LED_ON) |
13968+ PHY_M_LED_MO_1000(MO_LED_ON) |
13969+ PHY_M_LED_MO_RX(MO_LED_ON));
13970+ SK_U16 YukLedOff = (PHY_M_LED_MO_DUP(MO_LED_OFF) |
13971+ PHY_M_LED_MO_10(MO_LED_OFF) |
13972+ PHY_M_LED_MO_100(MO_LED_OFF) |
13973+ PHY_M_LED_MO_1000(MO_LED_OFF) |
13974+ PHY_M_LED_MO_RX(MO_LED_OFF));
13975+
13976+ nbrBlinkQuarterSeconds--;
13977+ if (nbrBlinkQuarterSeconds <= 0) {
13978+ (*pDev->stop)(pDev);
13979+ if (isDualNetCard) {
13980+ (*pOtherDev->stop)(pOtherDev);
13981+ }
13982
13983- return ethtool_op_set_tx_csum(dev, data);
13984-}
13985+ if (!boardWasDown[0]) {
13986+ (*pDev->open)(pDev);
13987+ }
13988+ if (isDualNetCard) {
13989+ (*pOtherDev->open)(pOtherDev);
13990+ }
13991+ isDualNetCard = SK_FALSE;
13992+ isLocateNICrunning = SK_FALSE;
13993+ return;
13994+ }
13995
13996-static u32 getRxCsum(struct net_device *dev)
13997-{
13998- DEV_NET *pNet = netdev_priv(dev);
13999- SK_AC *pAC = pNet->pAC;
14000+ doSwitchLEDsOn = (doSwitchLEDsOn) ? SK_FALSE : SK_TRUE;
14001+ if (doSwitchLEDsOn) {
14002+ if (pAC->GIni.GIGenesis) {
14003+ SK_OUT8(IoC,MR_ADDR(port,LNK_LED_REG),(SK_U8)SK_LNK_ON);
14004+ SkGeYellowLED(pAC,IoC,LED_ON >> 1);
14005+ SkGeXmitLED(pAC,IoC,MR_ADDR(port,RX_LED_INI),SK_LED_TST);
14006+ if (pAC->GIni.GP[port].PhyType == SK_PHY_BCOM) {
14007+ SkXmPhyWrite(pAC,IoC,port,PHY_BCOM_P_EXT_CTRL,PHY_B_PEC_LED_ON);
14008+ } else if (pAC->GIni.GP[port].PhyType == SK_PHY_LONE) {
14009+ SkXmPhyWrite(pAC,IoC,port,PHY_LONE_LED_CFG,0x0800);
14010+ } else {
14011+ SkGeXmitLED(pAC,IoC,MR_ADDR(port,TX_LED_INI),SK_LED_TST);
14012+ }
14013+ } else {
14014+ SkGmPhyWrite(pAC,IoC,port,PHY_MARV_LED_CTRL,0);
14015+ SkGmPhyWrite(pAC,IoC,port,PHY_MARV_LED_OVER,YukLedOn);
14016+ }
14017+ } else {
14018+ if (pAC->GIni.GIGenesis) {
14019+ SK_OUT8(IoC,MR_ADDR(port,LNK_LED_REG),(SK_U8)SK_LNK_OFF);
14020+ SkGeYellowLED(pAC,IoC,LED_OFF >> 1);
14021+ SkGeXmitLED(pAC,IoC,MR_ADDR(port,RX_LED_INI),SK_LED_DIS);
14022+ if (pAC->GIni.GP[port].PhyType == SK_PHY_BCOM) {
14023+ SkXmPhyWrite(pAC,IoC,port,PHY_BCOM_P_EXT_CTRL,PHY_B_PEC_LED_OFF);
14024+ } else if (pAC->GIni.GP[port].PhyType == SK_PHY_LONE) {
14025+ SkXmPhyWrite(pAC,IoC,port,PHY_LONE_LED_CFG,PHY_L_LC_LEDT);
14026+ } else {
14027+ SkGeXmitLED(pAC,IoC,MR_ADDR(port,TX_LED_INI),SK_LED_DIS);
14028+ }
14029+ } else {
14030+ SkGmPhyWrite(pAC,IoC,port,PHY_MARV_LED_CTRL,0);
14031+ SkGmPhyWrite(pAC,IoC,port,PHY_MARV_LED_OVER,YukLedOff);
14032+ }
14033+ }
14034
14035- return pAC->RxPort[pNet->PortNr].RxCsum;
14036-}
14037+ locateNICtimer.function = toggleLeds;
14038+ locateNICtimer.data = (unsigned long) pAC;
14039+ locateNICtimer.expires = jiffies + (HZ/4); /* 250ms */
14040+ add_timer(&locateNICtimer);
14041+}
14042+#endif
14043
14044-static int setRxCsum(struct net_device *dev, u32 data)
14045+/*****************************************************************************
14046+ *
14047+ * getPortNumber - evaluates the port number of an interface
14048+ *
14049+ * Description:
14050+ * It may be that the current interface refers to one which is located
14051+ * on a dual net adapter. Hence, this function will return the correct
14052+ * port for further use.
14053+ *
14054+ * Returns:
14055+ * the port number that corresponds to the selected adapter
14056+ *
14057+ */
14058+static int getPortNumber(
14059+struct net_device *netdev, /* the pointer to netdev structure */
14060+struct ifreq *ifr) /* what interface the request refers to? */
14061 {
14062- DEV_NET *pNet = netdev_priv(dev);
14063- SK_AC *pAC = pNet->pAC;
14064-
14065- if (pAC->GIni.GIChipId == CHIP_ID_GENESIS)
14066- return -EOPNOTSUPP;
14067+ DEV_NET *pNet = (DEV_NET*) netdev->priv;
14068+ SK_AC *pAC = pNet->pAC;
14069
14070- pAC->RxPort[pNet->PortNr].RxCsum = data != 0;
14071+ if (pAC->dev[1] != pAC->dev[0]) {
14072+ if (!strcmp(pAC->dev[1]->name, ifr->ifr_name)) {
14073+ return 1; /* port index 1 */
14074+ }
14075+ }
14076 return 0;
14077 }
14078
14079-struct ethtool_ops SkGeEthtoolOps = {
14080- .get_settings = getSettings,
14081- .set_settings = setSettings,
14082- .get_drvinfo = getDriverInfo,
14083- .get_strings = getStrings,
14084- .get_stats_count = getStatsCount,
14085- .get_ethtool_stats = getEthtoolStats,
14086- .phys_id = locateDevice,
14087- .get_pauseparam = getPauseParams,
14088- .set_pauseparam = setPauseParams,
14089- .get_link = ethtool_op_get_link,
14090- .get_perm_addr = ethtool_op_get_perm_addr,
14091- .get_sg = ethtool_op_get_sg,
14092- .set_sg = setScatterGather,
14093- .get_tx_csum = ethtool_op_get_tx_csum,
14094- .set_tx_csum = setTxCsum,
14095- .get_rx_csum = getRxCsum,
14096- .set_rx_csum = setRxCsum,
14097-};
14098+/*******************************************************************************
14099+ *
14100+ * End of file
14101+ *
14102+ ******************************************************************************/
14103diff -urN linux-2.6.17.orig/drivers/net/sk98lin/skge.c linux-2.6.17/drivers/net/sk98lin/skge.c
14104--- linux-2.6.17.orig/drivers/net/sk98lin/skge.c 2006-06-22 13:17:16.000000000 +0200
14105+++ linux-2.6.17/drivers/net/sk98lin/skge.c 2006-04-27 11:43:45.000000000 +0200
14106@@ -1,32 +1,26 @@
14107 /******************************************************************************
14108 *
14109- * Name: skge.c
14110- * Project: GEnesis, PCI Gigabit Ethernet Adapter
14111- * Version: $Revision$
14112- * Date: $Date$
14113- * Purpose: The main driver source module
14114+ * Name: skge.c
14115+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
14116+ * Version: $Revision$
14117+ * Date: $Date$
14118+ * Purpose: The main driver source module
14119 *
14120 ******************************************************************************/
14121
14122 /******************************************************************************
14123 *
14124 * (C)Copyright 1998-2002 SysKonnect GmbH.
14125- * (C)Copyright 2002-2003 Marvell.
14126+ * (C)Copyright 2002-2005 Marvell.
14127 *
14128 * Driver for Marvell Yukon chipset and SysKonnect Gigabit Ethernet
14129 * Server Adapters.
14130 *
14131- * Created 10-Feb-1999, based on Linux' acenic.c, 3c59x.c and
14132- * SysKonnects GEnesis Solaris driver
14133- * Author: Christoph Goos (cgoos@syskonnect.de)
14134- * Mirko Lindner (mlindner@syskonnect.de)
14135+ * Author: Mirko Lindner (mlindner@syskonnect.de)
14136+ * Ralph Roesler (rroesler@syskonnect.de)
14137 *
14138 * Address all question to: linux@syskonnect.de
14139 *
14140- * The technical manual for the adapters is available from SysKonnect's
14141- * web pages: www.syskonnect.com
14142- * Goto "Support" and search Knowledge Base for "manual".
14143- *
14144 * This program is free software; you can redistribute it and/or modify
14145 * it under the terms of the GNU General Public License as published by
14146 * the Free Software Foundation; either version 2 of the License, or
14147@@ -38,85 +32,53 @@
14148
14149 /******************************************************************************
14150 *
14151- * Possible compiler options (#define xxx / -Dxxx):
14152- *
14153- * debugging can be enable by changing SK_DEBUG_CHKMOD and
14154- * SK_DEBUG_CHKCAT in makefile (described there).
14155- *
14156- ******************************************************************************/
14157-
14158-/******************************************************************************
14159- *
14160 * Description:
14161 *
14162- * This is the main module of the Linux GE driver.
14163- *
14164- * All source files except skge.c, skdrv1st.h, skdrv2nd.h and sktypes.h
14165- * are part of SysKonnect's COMMON MODULES for the SK-98xx adapters.
14166- * Those are used for drivers on multiple OS', so some thing may seem
14167- * unnecessary complicated on Linux. Please do not try to 'clean up'
14168- * them without VERY good reasons, because this will make it more
14169- * difficult to keep the Linux driver in synchronisation with the
14170- * other versions.
14171- *
14172- * Include file hierarchy:
14173- *
14174- * <linux/module.h>
14175- *
14176- * "h/skdrv1st.h"
14177- * <linux/types.h>
14178- * <linux/kernel.h>
14179- * <linux/string.h>
14180- * <linux/errno.h>
14181- * <linux/ioport.h>
14182- * <linux/slab.h>
14183- * <linux/interrupt.h>
14184- * <linux/pci.h>
14185- * <linux/bitops.h>
14186- * <asm/byteorder.h>
14187- * <asm/io.h>
14188- * <linux/netdevice.h>
14189- * <linux/etherdevice.h>
14190- * <linux/skbuff.h>
14191- * those three depending on kernel version used:
14192- * <linux/bios32.h>
14193- * <linux/init.h>
14194- * <asm/uaccess.h>
14195- * <net/checksum.h>
14196- *
14197- * "h/skerror.h"
14198- * "h/skdebug.h"
14199- * "h/sktypes.h"
14200- * "h/lm80.h"
14201- * "h/xmac_ii.h"
14202- *
14203- * "h/skdrv2nd.h"
14204- * "h/skqueue.h"
14205- * "h/skgehwt.h"
14206- * "h/sktimer.h"
14207- * "h/ski2c.h"
14208- * "h/skgepnmi.h"
14209- * "h/skvpd.h"
14210- * "h/skgehw.h"
14211- * "h/skgeinit.h"
14212- * "h/skaddr.h"
14213- * "h/skgesirq.h"
14214- * "h/skrlmt.h"
14215+ * All source files in this sk98lin directory except of the sk98lin
14216+ * Linux specific files
14217+ *
14218+ * - skdim.c
14219+ * - skethtool.c
14220+ * - skge.c
14221+ * - skproc.c
14222+ * - sky2.c
14223+ * - Makefile
14224+ * - h/skdrv1st.h
14225+ * - h/skdrv2nd.h
14226+ * - h/sktypes.h
14227+ * - h/skversion.h
14228+ *
14229+ * are part of SysKonnect's common modules for the SK-9xxx adapters.
14230+ *
14231+ * Those common module files which are not Linux specific are used to
14232+ * build drivers on different OS' (e.g. Windows, MAC OS) so that those
14233+ * drivers are based on the same set of files
14234+ *
14235+ * At a first glance, this seems to complicate things unnescessarily on
14236+ * Linux, but please do not try to 'clean up' them without VERY good
14237+ * reasons, because this will make it more difficult to keep the sk98lin
14238+ * driver for Linux in synchronisation with the other drivers running on
14239+ * other operating systems.
14240 *
14241 ******************************************************************************/
14242
14243 #include "h/skversion.h"
14244
14245-#include <linux/in.h>
14246 #include <linux/module.h>
14247-#include <linux/moduleparam.h>
14248 #include <linux/init.h>
14249-#include <linux/dma-mapping.h>
14250-#include <linux/ip.h>
14251+#include <linux/ethtool.h>
14252+
14253+#ifdef CONFIG_PROC_FS
14254+#include <linux/proc_fs.h>
14255+#endif
14256
14257 #include "h/skdrv1st.h"
14258 #include "h/skdrv2nd.h"
14259
14260+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
14261+#include <linux/moduleparam.h>
14262+#endif
14263+
14264 /*******************************************************************************
14265 *
14266 * Defines
14267@@ -126,62 +88,14 @@
14268 /* for debuging on x86 only */
14269 /* #define BREAKPOINT() asm(" int $3"); */
14270
14271-/* use the transmit hw checksum driver functionality */
14272-#define USE_SK_TX_CHECKSUM
14273-
14274-/* use the receive hw checksum driver functionality */
14275-#define USE_SK_RX_CHECKSUM
14276-
14277-/* use the scatter-gather functionality with sendfile() */
14278-#define SK_ZEROCOPY
14279-
14280-/* use of a transmit complete interrupt */
14281-#define USE_TX_COMPLETE
14282-
14283-/*
14284- * threshold for copying small receive frames
14285- * set to 0 to avoid copying, set to 9001 to copy all frames
14286- */
14287-#define SK_COPY_THRESHOLD 50
14288-
14289-/* number of adapters that can be configured via command line params */
14290-#define SK_MAX_CARD_PARAM 16
14291-
14292-
14293-
14294-/*
14295- * use those defines for a compile-in version of the driver instead
14296- * of command line parameters
14297- */
14298-// #define LINK_SPEED_A {"Auto", }
14299-// #define LINK_SPEED_B {"Auto", }
14300-// #define AUTO_NEG_A {"Sense", }
14301-// #define AUTO_NEG_B {"Sense", }
14302-// #define DUP_CAP_A {"Both", }
14303-// #define DUP_CAP_B {"Both", }
14304-// #define FLOW_CTRL_A {"SymOrRem", }
14305-// #define FLOW_CTRL_B {"SymOrRem", }
14306-// #define ROLE_A {"Auto", }
14307-// #define ROLE_B {"Auto", }
14308-// #define PREF_PORT {"A", }
14309-// #define CON_TYPE {"Auto", }
14310-// #define RLMT_MODE {"CheckLinkState", }
14311-
14312-#define DEV_KFREE_SKB(skb) dev_kfree_skb(skb)
14313-#define DEV_KFREE_SKB_IRQ(skb) dev_kfree_skb_irq(skb)
14314-#define DEV_KFREE_SKB_ANY(skb) dev_kfree_skb_any(skb)
14315-
14316
14317 /* Set blink mode*/
14318 #define OEM_CONFIG_VALUE ( SK_ACT_LED_BLINK | \
14319 SK_DUP_LED_NORMAL | \
14320 SK_LED_LINK100_ON)
14321
14322-
14323-/* Isr return value */
14324-#define SkIsrRetVar irqreturn_t
14325-#define SkIsrRetNone IRQ_NONE
14326-#define SkIsrRetHandled IRQ_HANDLED
14327+#define CLEAR_AND_START_RX(Port) SK_OUT8(pAC->IoBase, RxQueueAddr[(Port)]+Q_CSR, CSR_START | CSR_IRQ_CL_F)
14328+#define CLEAR_TX_IRQ(Port,Prio) SK_OUT8(pAC->IoBase, TxQueueAddr[(Port)][(Prio)]+Q_CSR, CSR_IRQ_CL_F)
14329
14330
14331 /*******************************************************************************
14332@@ -190,12 +104,25 @@
14333 *
14334 ******************************************************************************/
14335
14336+static int __devinit sk98lin_init_device(struct pci_dev *pdev, const struct pci_device_id *ent);
14337+static void sk98lin_remove_device(struct pci_dev *pdev);
14338+#ifdef CONFIG_PM
14339+static int sk98lin_suspend(struct pci_dev *pdev, u32 state);
14340+static int sk98lin_resume(struct pci_dev *pdev);
14341+static void SkEnableWOMagicPacket(SK_AC *pAC, SK_IOC IoC, SK_MAC_ADDR MacAddr);
14342+#endif
14343+#ifdef Y2_RECOVERY
14344+static void SkGeHandleKernelTimer(unsigned long ptr);
14345+void SkGeCheckTimer(DEV_NET *pNet);
14346+static SK_BOOL CheckRXCounters(DEV_NET *pNet);
14347+static void CheckRxPath(DEV_NET *pNet);
14348+#endif
14349 static void FreeResources(struct SK_NET_DEVICE *dev);
14350 static int SkGeBoardInit(struct SK_NET_DEVICE *dev, SK_AC *pAC);
14351 static SK_BOOL BoardAllocMem(SK_AC *pAC);
14352 static void BoardFreeMem(SK_AC *pAC);
14353 static void BoardInitMem(SK_AC *pAC);
14354-static void SetupRing(SK_AC*, void*, uintptr_t, RXD**, RXD**, RXD**, int*, SK_BOOL);
14355+static void SetupRing(SK_AC*, void*, uintptr_t, RXD**, RXD**, RXD**, int*, int*, SK_BOOL);
14356 static SkIsrRetVar SkGeIsr(int irq, void *dev_id, struct pt_regs *ptregs);
14357 static SkIsrRetVar SkGeIsrOnePort(int irq, void *dev_id, struct pt_regs *ptregs);
14358 static int SkGeOpen(struct SK_NET_DEVICE *dev);
14359@@ -206,39 +133,76 @@
14360 static struct net_device_stats *SkGeStats(struct SK_NET_DEVICE *dev);
14361 static int SkGeIoctl(struct SK_NET_DEVICE *dev, struct ifreq *rq, int cmd);
14362 static void GetConfiguration(SK_AC*);
14363+static void ProductStr(SK_AC*);
14364 static int XmitFrame(SK_AC*, TX_PORT*, struct sk_buff*);
14365 static void FreeTxDescriptors(SK_AC*pAC, TX_PORT*);
14366 static void FillRxRing(SK_AC*, RX_PORT*);
14367 static SK_BOOL FillRxDescriptor(SK_AC*, RX_PORT*);
14368+#ifdef CONFIG_SK98LIN_NAPI
14369+static int SkGePoll(struct net_device *dev, int *budget);
14370+static void ReceiveIrq(SK_AC*, RX_PORT*, SK_BOOL, int*, int);
14371+#else
14372 static void ReceiveIrq(SK_AC*, RX_PORT*, SK_BOOL);
14373-static void ClearAndStartRx(SK_AC*, int);
14374-static void ClearTxIrq(SK_AC*, int, int);
14375+#endif
14376+#ifdef SK_POLL_CONTROLLER
14377+static void SkGeNetPoll(struct SK_NET_DEVICE *dev);
14378+#endif
14379 static void ClearRxRing(SK_AC*, RX_PORT*);
14380 static void ClearTxRing(SK_AC*, TX_PORT*);
14381 static int SkGeChangeMtu(struct SK_NET_DEVICE *dev, int new_mtu);
14382 static void PortReInitBmu(SK_AC*, int);
14383 static int SkGeIocMib(DEV_NET*, unsigned int, int);
14384 static int SkGeInitPCI(SK_AC *pAC);
14385-static void StartDrvCleanupTimer(SK_AC *pAC);
14386-static void StopDrvCleanupTimer(SK_AC *pAC);
14387-static int XmitFrameSG(SK_AC*, TX_PORT*, struct sk_buff*);
14388-
14389-#ifdef SK_DIAG_SUPPORT
14390 static SK_U32 ParseDeviceNbrFromSlotName(const char *SlotName);
14391 static int SkDrvInitAdapter(SK_AC *pAC, int devNbr);
14392 static int SkDrvDeInitAdapter(SK_AC *pAC, int devNbr);
14393-#endif
14394+extern void SkLocalEventQueue( SK_AC *pAC,
14395+ SK_U32 Class,
14396+ SK_U32 Event,
14397+ SK_U32 Param1,
14398+ SK_U32 Param2,
14399+ SK_BOOL Flag);
14400+extern void SkLocalEventQueue64( SK_AC *pAC,
14401+ SK_U32 Class,
14402+ SK_U32 Event,
14403+ SK_U64 Param,
14404+ SK_BOOL Flag);
14405+
14406+static int XmitFrameSG(SK_AC*, TX_PORT*, struct sk_buff*);
14407
14408 /*******************************************************************************
14409 *
14410 * Extern Function Prototypes
14411 *
14412 ******************************************************************************/
14413+
14414+extern SK_BOOL SkY2AllocateResources(SK_AC *pAC);
14415+extern void SkY2FreeResources(SK_AC *pAC);
14416+extern void SkY2AllocateRxBuffers(SK_AC *pAC,SK_IOC IoC,int Port);
14417+extern void SkY2FreeRxBuffers(SK_AC *pAC,SK_IOC IoC,int Port);
14418+extern void SkY2FreeTxBuffers(SK_AC *pAC,SK_IOC IoC,int Port);
14419+extern SkIsrRetVar SkY2Isr(int irq,void *dev_id,struct pt_regs *ptregs);
14420+extern int SkY2Xmit(struct sk_buff *skb,struct SK_NET_DEVICE *dev);
14421+extern void SkY2PortStop(SK_AC *pAC,SK_IOC IoC,int Port,int Dir,int RstMode);
14422+extern void SkY2PortStart(SK_AC *pAC,SK_IOC IoC,int Port);
14423+extern int SkY2RlmtSend(SK_AC *pAC,int PortNr,struct sk_buff *pMessage);
14424+extern void SkY2RestartStatusUnit(SK_AC *pAC);
14425+extern void FillReceiveTableYukon2(SK_AC *pAC,SK_IOC IoC,int Port);
14426+#ifdef CONFIG_SK98LIN_NAPI
14427+extern int SkY2Poll(struct net_device *dev, int *budget);
14428+#endif
14429+
14430 extern void SkDimEnableModerationIfNeeded(SK_AC *pAC);
14431-extern void SkDimDisplayModerationSettings(SK_AC *pAC);
14432 extern void SkDimStartModerationTimer(SK_AC *pAC);
14433 extern void SkDimModerate(SK_AC *pAC);
14434-extern void SkGeBlinkTimer(unsigned long data);
14435+
14436+extern int SkEthIoctl(struct net_device *netdev, struct ifreq *ifr);
14437+
14438+#ifdef CONFIG_PROC_FS
14439+static const char SK_Root_Dir_entry[] = "sk98lin";
14440+static struct proc_dir_entry *pSkRootDir;
14441+extern struct file_operations sk_proc_fops;
14442+#endif
14443
14444 #ifdef DEBUG
14445 static void DumpMsg(struct sk_buff*, char*);
14446@@ -247,33 +211,448 @@
14447 #endif
14448
14449 /* global variables *********************************************************/
14450+static const char *BootString = BOOT_STRING;
14451+struct SK_NET_DEVICE *SkGeRootDev = NULL;
14452 static SK_BOOL DoPrintInterfaceChange = SK_TRUE;
14453-extern struct ethtool_ops SkGeEthtoolOps;
14454
14455 /* local variables **********************************************************/
14456 static uintptr_t TxQueueAddr[SK_MAX_MACS][2] = {{0x680, 0x600},{0x780, 0x700}};
14457 static uintptr_t RxQueueAddr[SK_MAX_MACS] = {0x400, 0x480};
14458+static int sk98lin_max_boards_found = 0;
14459+
14460+#ifdef CONFIG_PROC_FS
14461+static struct proc_dir_entry *pSkRootDir;
14462+#endif
14463+
14464+
14465+
14466+static struct pci_device_id sk98lin_pci_tbl[] __devinitdata = {
14467+/* { pci_vendor_id, pci_device_id, * SAMPLE ENTRY! *
14468+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, */
14469+ { 0x10b7, 0x1700, /* 3Com (10b7), Gigabit Ethernet Adapter */
14470+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14471+ { 0x10b7, 0x80eb, /* 3Com (10b7), 3Com 3C940B Gigabit LOM Ethernet Adapter */
14472+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14473+ { 0x1148, 0x4300, /* SysKonnect (1148), SK-98xx Gigabit Ethernet Server Adapter */
14474+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14475+ { 0x1148, 0x4320, /* SysKonnect (1148), SK-98xx V2.0 Gigabit Ethernet Adapter */
14476+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14477+ { 0x1148, 0x9000, /* SysKonnect (1148), SK-9Sxx 10/100/1000Base-T Server Adapter */
14478+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14479+ { 0x1148, 0x9E00, /* SysKonnect (1148), SK-9Exx 10/100/1000Base-T Adapter */
14480+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14481+ { 0x1186, 0x4b00, /* D-Link (1186), Gigabit Ethernet Adapter */
14482+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14483+ { 0x1186, 0x4b01, /* D-Link (1186), Gigabit Ethernet Adapter */
14484+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14485+ { 0x1186, 0x4b02, /* D-Link (1186), Gigabit Ethernet Adapter */
14486+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14487+ { 0x1186, 0x4c00, /* D-Link (1186), Gigabit Ethernet Adapter */
14488+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14489+ { 0x11ab, 0x4320, /* Marvell (11ab), Gigabit Ethernet Controller */
14490+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14491+ { 0x11ab, 0x4340, /* Marvell (11ab), Gigabit Ethernet Controller */
14492+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14493+ { 0x11ab, 0x4341, /* Marvell (11ab), Gigabit Ethernet Controller */
14494+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14495+ { 0x11ab, 0x4342, /* Marvell (11ab), Gigabit Ethernet Controller */
14496+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14497+ { 0x11ab, 0x4343, /* Marvell (11ab), Gigabit Ethernet Controller */
14498+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14499+ { 0x11ab, 0x4344, /* Marvell (11ab), Gigabit Ethernet Controller */
14500+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14501+ { 0x11ab, 0x4345, /* Marvell (11ab), Gigabit Ethernet Controller */
14502+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14503+ { 0x11ab, 0x4346, /* Marvell (11ab), Gigabit Ethernet Controller */
14504+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14505+ { 0x11ab, 0x4347, /* Marvell (11ab), Gigabit Ethernet Controller */
14506+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14507+ { 0x11ab, 0x4350, /* Marvell (11ab), Fast Ethernet Controller */
14508+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14509+ { 0x11ab, 0x4351, /* Marvell (11ab), Fast Ethernet Controller */
14510+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14511+ { 0x11ab, 0x4352, /* Marvell (11ab), Fast Ethernet Controller */
14512+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14513+ { 0x11ab, 0x4356, /* Marvell (11ab), Gigabit Ethernet Controller */
14514+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14515+ { 0x11ab, 0x4360, /* Marvell (11ab), Gigabit Ethernet Controller */
14516+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14517+ { 0x11ab, 0x4361, /* Marvell (11ab), Gigabit Ethernet Controller */
14518+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14519+ { 0x11ab, 0x4362, /* Marvell (11ab), Gigabit Ethernet Controller */
14520+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14521+ { 0x11ab, 0x4363, /* Marvell (11ab), Marvell */
14522+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14523+ { 0x11ab, 0x4364, /* Marvell (11ab), Gigabit Ethernet Controller */
14524+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14525+ { 0x11ab, 0x4366, /* Marvell (11ab), Gigabit Ethernet Controller */
14526+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14527+ { 0x11ab, 0x4367, /* Marvell (11ab), Gigabit Ethernet Controller */
14528+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14529+ { 0x11ab, 0x4368, /* Marvell (11ab), Gigabit Ethernet Controller */
14530+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14531+ { 0x11ab, 0x5005, /* Marvell (11ab), Belkin */
14532+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14533+ { 0x1371, 0x434e, /* CNet (1371), GigaCard Network Adapter */
14534+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14535+ { 0x1737, 0x1032, /* Linksys (1737), Gigabit Network Adapter */
14536+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14537+ { 0x1737, 0x1064, /* Linksys (1737), Gigabit Network Adapter */
14538+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
14539+ { 0, }
14540+};
14541+
14542+MODULE_DEVICE_TABLE(pci, sk98lin_pci_tbl);
14543+
14544+static struct pci_driver sk98lin_driver = {
14545+ .name = DRIVER_FILE_NAME,
14546+ .id_table = sk98lin_pci_tbl,
14547+ .probe = sk98lin_init_device,
14548+ .remove = __devexit_p(sk98lin_remove_device),
14549+#ifdef CONFIG_PM
14550+ .suspend = sk98lin_suspend,
14551+ .resume = sk98lin_resume
14552+#endif
14553+};
14554+
14555
14556 /*****************************************************************************
14557 *
14558- * SkPciWriteCfgDWord - write a 32 bit value to pci config space
14559+ * sk98lin_init_device - initialize the adapter
14560 *
14561 * Description:
14562- * This routine writes a 32 bit value to the pci configuration
14563- * space.
14564+ * This function initializes the adapter. Resources for
14565+ * the adapter are allocated and the adapter is brought into Init 1
14566+ * state.
14567 *
14568 * Returns:
14569- * 0 - indicate everything worked ok.
14570- * != 0 - error indication
14571+ * 0, if everything is ok
14572+ * !=0, on error
14573 */
14574-static inline int SkPciWriteCfgDWord(
14575-SK_AC *pAC, /* Adapter Control structure pointer */
14576-int PciAddr, /* PCI register address */
14577-SK_U32 Val) /* pointer to store the read value */
14578+static int __devinit sk98lin_init_device(struct pci_dev *pdev,
14579+ const struct pci_device_id *ent)
14580+
14581 {
14582- pci_write_config_dword(pAC->PciDev, PciAddr, Val);
14583- return(0);
14584-} /* SkPciWriteCfgDWord */
14585+ static SK_BOOL sk98lin_boot_string = SK_FALSE;
14586+ static SK_BOOL sk98lin_proc_entry = SK_FALSE;
14587+ static int sk98lin_boards_found = 0;
14588+ SK_AC *pAC;
14589+ DEV_NET *pNet = NULL;
14590+ struct SK_NET_DEVICE *dev = NULL;
14591+ int retval;
14592+#ifdef CONFIG_PROC_FS
14593+ struct proc_dir_entry *pProcFile;
14594+#endif
14595+ int pci_using_dac;
14596+
14597+ retval = pci_enable_device(pdev);
14598+ if (retval) {
14599+ printk(KERN_ERR "Cannot enable PCI device, "
14600+ "aborting.\n");
14601+ return retval;
14602+ }
14603+
14604+ dev = NULL;
14605+ pNet = NULL;
14606+
14607+
14608+ /* INSERT * We have to find the power-management capabilities */
14609+ /* Find power-management capability. */
14610+
14611+ pci_using_dac = 0; /* Set 32 bit DMA per default */
14612+ /* Configure DMA attributes. */
14613+ retval = pci_set_dma_mask(pdev, (u64) 0xffffffffffffffffULL);
14614+ if (!retval) {
14615+ pci_using_dac = 1;
14616+ } else {
14617+ retval = pci_set_dma_mask(pdev, (u64) 0xffffffff);
14618+ if (retval) {
14619+ printk(KERN_ERR "No usable DMA configuration, "
14620+ "aborting.\n");
14621+ return retval;
14622+ }
14623+ }
14624+
14625+
14626+ if ((dev = alloc_etherdev(sizeof(DEV_NET))) == NULL) {
14627+ printk(KERN_ERR "Unable to allocate etherdev "
14628+ "structure!\n");
14629+ return -ENODEV;
14630+ }
14631+
14632+ pNet = dev->priv;
14633+ pNet->pAC = kmalloc(sizeof(SK_AC), GFP_KERNEL);
14634+ if (pNet->pAC == NULL){
14635+ free_netdev(dev);
14636+ printk(KERN_ERR "Unable to allocate adapter "
14637+ "structure!\n");
14638+ return -ENODEV;
14639+ }
14640+
14641+
14642+ /* Print message */
14643+ if (!sk98lin_boot_string) {
14644+ /* set display flag to TRUE so that */
14645+ /* we only display this string ONCE */
14646+ sk98lin_boot_string = SK_TRUE;
14647+ printk("%s\n", BootString);
14648+ }
14649+
14650+ memset(pNet->pAC, 0, sizeof(SK_AC));
14651+ pAC = pNet->pAC;
14652+ pAC->PciDev = pdev;
14653+ pAC->PciDevId = pdev->device;
14654+ pAC->dev[0] = dev;
14655+ pAC->dev[1] = dev;
14656+ sprintf(pAC->Name, "SysKonnect SK-98xx");
14657+ pAC->CheckQueue = SK_FALSE;
14658+
14659+ dev->irq = pdev->irq;
14660+ retval = SkGeInitPCI(pAC);
14661+ if (retval) {
14662+ printk("SKGE: PCI setup failed: %i\n", retval);
14663+ free_netdev(dev);
14664+ return -ENODEV;
14665+ }
14666+
14667+ SET_MODULE_OWNER(dev);
14668+
14669+ dev->open = &SkGeOpen;
14670+ dev->stop = &SkGeClose;
14671+ dev->get_stats = &SkGeStats;
14672+ dev->set_multicast_list = &SkGeSetRxMode;
14673+ dev->set_mac_address = &SkGeSetMacAddr;
14674+ dev->do_ioctl = &SkGeIoctl;
14675+ dev->change_mtu = &SkGeChangeMtu;
14676+ dev->flags &= ~IFF_RUNNING;
14677+#ifdef SK_POLL_CONTROLLER
14678+ dev->poll_controller = SkGeNetPoll;
14679+#endif
14680+ SET_NETDEV_DEV(dev, &pdev->dev);
14681+
14682+ pAC->Index = sk98lin_boards_found;
14683+
14684+ if (SkGeBoardInit(dev, pAC)) {
14685+ free_netdev(dev);
14686+ return -ENODEV;
14687+ } else {
14688+ ProductStr(pAC);
14689+ }
14690+
14691+ if (pci_using_dac)
14692+ dev->features |= NETIF_F_HIGHDMA;
14693+
14694+ /* shifter to later moment in time... */
14695+ if (CHIP_ID_YUKON_2(pAC)) {
14696+ dev->hard_start_xmit = &SkY2Xmit;
14697+#ifdef CONFIG_SK98LIN_NAPI
14698+ dev->poll = &SkY2Poll;
14699+ dev->weight = 64;
14700+#endif
14701+ } else {
14702+ dev->hard_start_xmit = &SkGeXmit;
14703+#ifdef CONFIG_SK98LIN_NAPI
14704+ dev->poll = &SkGePoll;
14705+ dev->weight = 64;
14706+#endif
14707+ }
14708+
14709+#ifdef NETIF_F_TSO
14710+#ifdef USE_SK_TSO_FEATURE
14711+ if ((CHIP_ID_YUKON_2(pAC)) &&
14712+ (pAC->GIni.GIChipId != CHIP_ID_YUKON_EC_U)) {
14713+ dev->features |= NETIF_F_TSO;
14714+ }
14715+#endif
14716+#endif
14717+#ifdef CONFIG_SK98LIN_ZEROCOPY
14718+ if (pAC->GIni.GIChipId != CHIP_ID_GENESIS)
14719+ dev->features |= NETIF_F_SG;
14720+#endif
14721+#ifdef USE_SK_TX_CHECKSUM
14722+ if (pAC->GIni.GIChipId != CHIP_ID_GENESIS)
14723+ dev->features |= NETIF_F_IP_CSUM;
14724+#endif
14725+#ifdef USE_SK_RX_CHECKSUM
14726+ pAC->RxPort[0].UseRxCsum = SK_TRUE;
14727+ if (pAC->GIni.GIMacsFound == 2 ) {
14728+ pAC->RxPort[1].UseRxCsum = SK_TRUE;
14729+ }
14730+#endif
14731+
14732+ /* Save the hardware revision */
14733+ pAC->HWRevision = (((pAC->GIni.GIPciHwRev >> 4) & 0x0F)*10) +
14734+ (pAC->GIni.GIPciHwRev & 0x0F);
14735+
14736+ /* Set driver globals */
14737+ pAC->Pnmi.pDriverFileName = DRIVER_FILE_NAME;
14738+ pAC->Pnmi.pDriverReleaseDate = DRIVER_REL_DATE;
14739+
14740+ SK_MEMSET(&(pAC->PnmiBackup), 0, sizeof(SK_PNMI_STRUCT_DATA));
14741+ SK_MEMCPY(&(pAC->PnmiBackup), &(pAC->PnmiStruct),
14742+ sizeof(SK_PNMI_STRUCT_DATA));
14743+
14744+ /* Register net device */
14745+ retval = register_netdev(dev);
14746+ if (retval) {
14747+ printk(KERN_ERR "SKGE: Could not register device.\n");
14748+ FreeResources(dev);
14749+ free_netdev(dev);
14750+ return retval;
14751+ }
14752+
14753+ /* Save initial device name */
14754+ strcpy(pNet->InitialDevName, dev->name);
14755+
14756+ /* Set network to off */
14757+ netif_stop_queue(dev);
14758+ netif_carrier_off(dev);
14759+
14760+ /* Print adapter specific string from vpd and config settings */
14761+ printk("%s: %s\n", pNet->InitialDevName, pAC->DeviceStr);
14762+ printk(" PrefPort:%c RlmtMode:%s\n",
14763+ 'A' + pAC->Rlmt.Net[0].Port[pAC->Rlmt.Net[0].PrefPort]->PortNumber,
14764+ (pAC->RlmtMode==0) ? "Check Link State" :
14765+ ((pAC->RlmtMode==1) ? "Check Link State" :
14766+ ((pAC->RlmtMode==3) ? "Check Local Port" :
14767+ ((pAC->RlmtMode==7) ? "Check Segmentation" :
14768+ ((pAC->RlmtMode==17) ? "Dual Check Link State" :"Error")))));
14769+
14770+ SkGeYellowLED(pAC, pAC->IoBase, 1);
14771+
14772+ memcpy((caddr_t) &dev->dev_addr,
14773+ (caddr_t) &pAC->Addr.Net[0].CurrentMacAddress, 6);
14774+
14775+ /* First adapter... Create proc and print message */
14776+#ifdef CONFIG_PROC_FS
14777+ if (!sk98lin_proc_entry) {
14778+ sk98lin_proc_entry = SK_TRUE;
14779+ SK_MEMCPY(&SK_Root_Dir_entry, BootString,
14780+ sizeof(SK_Root_Dir_entry) - 1);
14781+
14782+ /*Create proc (directory)*/
14783+ if(!pSkRootDir) {
14784+ pSkRootDir = proc_mkdir(SK_Root_Dir_entry, proc_net);
14785+ if (!pSkRootDir) {
14786+ printk(KERN_WARNING "%s: Unable to create /proc/net/%s",
14787+ dev->name, SK_Root_Dir_entry);
14788+ } else {
14789+ pSkRootDir->owner = THIS_MODULE;
14790+ }
14791+ }
14792+ }
14793+
14794+ /* Create proc file */
14795+ if (pSkRootDir &&
14796+ (pProcFile = create_proc_entry(pNet->InitialDevName, S_IRUGO,
14797+ pSkRootDir))) {
14798+ pProcFile->proc_fops = &sk_proc_fops;
14799+ pProcFile->data = dev;
14800+ }
14801+
14802+#endif
14803+
14804+ pNet->PortNr = 0;
14805+ pNet->NetNr = 0;
14806+
14807+ sk98lin_boards_found++;
14808+ pci_set_drvdata(pdev, dev);
14809+
14810+ /* More then one port found */
14811+ if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
14812+ if ((dev = alloc_etherdev(sizeof(DEV_NET))) == 0) {
14813+ printk(KERN_ERR "Unable to allocate etherdev "
14814+ "structure!\n");
14815+ return -ENODEV;
14816+ }
14817+
14818+ pAC->dev[1] = dev;
14819+ pNet = dev->priv;
14820+ pNet->PortNr = 1;
14821+ pNet->NetNr = 1;
14822+ pNet->pAC = pAC;
14823+
14824+ if (CHIP_ID_YUKON_2(pAC)) {
14825+ dev->hard_start_xmit = &SkY2Xmit;
14826+#ifdef CONFIG_SK98LIN_NAPI
14827+ dev->poll = &SkY2Poll;
14828+ dev->weight = 64;
14829+#endif
14830+ } else {
14831+ dev->hard_start_xmit = &SkGeXmit;
14832+#ifdef CONFIG_SK98LIN_NAPI
14833+ dev->poll = &SkGePoll;
14834+ dev->weight = 64;
14835+#endif
14836+ }
14837+ dev->open = &SkGeOpen;
14838+ dev->stop = &SkGeClose;
14839+ dev->get_stats = &SkGeStats;
14840+ dev->set_multicast_list = &SkGeSetRxMode;
14841+ dev->set_mac_address = &SkGeSetMacAddr;
14842+ dev->do_ioctl = &SkGeIoctl;
14843+ dev->change_mtu = &SkGeChangeMtu;
14844+ dev->flags &= ~IFF_RUNNING;
14845+#ifdef SK_POLL_CONTROLLER
14846+ dev->poll_controller = SkGeNetPoll;
14847+#endif
14848+
14849+#ifdef NETIF_F_TSO
14850+#ifdef USE_SK_TSO_FEATURE
14851+ if ((CHIP_ID_YUKON_2(pAC)) &&
14852+ (pAC->GIni.GIChipId != CHIP_ID_YUKON_EC_U)) {
14853+ dev->features |= NETIF_F_TSO;
14854+ }
14855+#endif
14856+#endif
14857+#ifdef CONFIG_SK98LIN_ZEROCOPY
14858+ /* Don't handle if Genesis chipset */
14859+ if (pAC->GIni.GIChipId != CHIP_ID_GENESIS)
14860+ dev->features |= NETIF_F_SG;
14861+#endif
14862+#ifdef USE_SK_TX_CHECKSUM
14863+ /* Don't handle if Genesis chipset */
14864+ if (pAC->GIni.GIChipId != CHIP_ID_GENESIS)
14865+ dev->features |= NETIF_F_IP_CSUM;
14866+#endif
14867+
14868+ if (register_netdev(dev)) {
14869+ printk(KERN_ERR "SKGE: Could not register device.\n");
14870+ free_netdev(dev);
14871+ pAC->dev[1] = pAC->dev[0];
14872+ } else {
14873+
14874+ /* Save initial device name */
14875+ strcpy(pNet->InitialDevName, dev->name);
14876+
14877+ /* Set network to off */
14878+ netif_stop_queue(dev);
14879+ netif_carrier_off(dev);
14880+
14881+
14882+#ifdef CONFIG_PROC_FS
14883+ if (pSkRootDir
14884+ && (pProcFile = create_proc_entry(pNet->InitialDevName,
14885+ S_IRUGO, pSkRootDir))) {
14886+ pProcFile->proc_fops = &sk_proc_fops;
14887+ pProcFile->data = dev;
14888+ }
14889+#endif
14890+
14891+ memcpy((caddr_t) &dev->dev_addr,
14892+ (caddr_t) &pAC->Addr.Net[1].CurrentMacAddress, 6);
14893+
14894+ printk("%s: %s\n", pNet->InitialDevName, pAC->DeviceStr);
14895+ printk(" PrefPort:B RlmtMode:Dual Check Link State\n");
14896+ }
14897+ }
14898+
14899+ pAC->Index = sk98lin_boards_found;
14900+ sk98lin_max_boards_found = sk98lin_boards_found;
14901+ return 0;
14902+}
14903+
14904+
14905
14906 /*****************************************************************************
14907 *
14908@@ -282,22 +661,26 @@
14909 * Description:
14910 * This function initialize the PCI resources and IO
14911 *
14912- * Returns:
14913- * 0 - indicate everything worked ok.
14914- * != 0 - error indication
14915+ * Returns: N/A
14916+ *
14917 */
14918-static __devinit int SkGeInitPCI(SK_AC *pAC)
14919+int SkGeInitPCI(SK_AC *pAC)
14920 {
14921 struct SK_NET_DEVICE *dev = pAC->dev[0];
14922 struct pci_dev *pdev = pAC->PciDev;
14923 int retval;
14924
14925+ if (pci_enable_device(pdev) != 0) {
14926+ return 1;
14927+ }
14928+
14929 dev->mem_start = pci_resource_start (pdev, 0);
14930 pci_set_master(pdev);
14931
14932- retval = pci_request_regions(pdev, "sk98lin");
14933- if (retval)
14934- goto out;
14935+ if (pci_request_regions(pdev, DRIVER_FILE_NAME) != 0) {
14936+ retval = 2;
14937+ goto out_disable;
14938+ }
14939
14940 #ifdef SK_BIG_ENDIAN
14941 /*
14942@@ -315,9 +698,10 @@
14943 /*
14944 * Remap the regs into kernel space.
14945 */
14946- pAC->IoBase = ioremap_nocache(dev->mem_start, 0x4000);
14947- if (!pAC->IoBase) {
14948- retval = -EIO;
14949+ pAC->IoBase = (char*)ioremap_nocache(dev->mem_start, 0x4000);
14950+
14951+ if (!pAC->IoBase){
14952+ retval = 3;
14953 goto out_release;
14954 }
14955
14956@@ -325,10 +709,476 @@
14957
14958 out_release:
14959 pci_release_regions(pdev);
14960- out:
14961+ out_disable:
14962+ pci_disable_device(pdev);
14963 return retval;
14964 }
14965
14966+#ifdef Y2_RECOVERY
14967+/*****************************************************************************
14968+ *
14969+ * SkGeHandleKernelTimer - Handle the kernel timer requests
14970+ *
14971+ * Description:
14972+ * If the requested time interval for the timer has elapsed,
14973+ * this function checks the link state.
14974+ *
14975+ * Returns: N/A
14976+ *
14977+ */
14978+static void SkGeHandleKernelTimer(
14979+unsigned long ptr) /* holds the pointer to adapter control context */
14980+{
14981+ DEV_NET *pNet = (DEV_NET*) ptr;
14982+ SkGeCheckTimer(pNet);
14983+}
14984+
14985+/*****************************************************************************
14986+ *
14987+ * sk98lin_check_timer - Resume the the card
14988+ *
14989+ * Description:
14990+ * This function checks the kernel timer
14991+ *
14992+ * Returns: N/A
14993+ *
14994+ */
14995+void SkGeCheckTimer(
14996+DEV_NET *pNet) /* holds the pointer to adapter control context */
14997+{
14998+ SK_AC *pAC = pNet->pAC;
14999+ SK_BOOL StartTimer = SK_TRUE;
15000+
15001+ if (pNet->InRecover)
15002+ return;
15003+ if (pNet->TimerExpired)
15004+ return;
15005+ pNet->TimerExpired = SK_TRUE;
15006+
15007+#define TXPORT pAC->TxPort[pNet->PortNr][TX_PRIO_LOW]
15008+#define RXPORT pAC->RxPort[pNet->PortNr]
15009+
15010+ if ( (CHIP_ID_YUKON_2(pAC)) &&
15011+ (netif_running(pAC->dev[pNet->PortNr]))) {
15012+
15013+#ifdef Y2_RX_CHECK
15014+ if (HW_FEATURE(pAC, HWF_WA_DEV_4167)) {
15015+ /* Checks the RX path */
15016+ CheckRxPath(pNet);
15017+ }
15018+#endif
15019+
15020+ /* Checkthe transmitter */
15021+ if (!(IS_Q_EMPTY(&TXPORT.TxAQ_working))) {
15022+ if (TXPORT.LastDone != TXPORT.TxALET.Done) {
15023+ TXPORT.LastDone = TXPORT.TxALET.Done;
15024+ pNet->TransmitTimeoutTimer = 0;
15025+ } else {
15026+ pNet->TransmitTimeoutTimer++;
15027+ if (pNet->TransmitTimeoutTimer >= 10) {
15028+ pNet->TransmitTimeoutTimer = 0;
15029+#ifdef CHECK_TRANSMIT_TIMEOUT
15030+ StartTimer = SK_FALSE;
15031+ SkLocalEventQueue(pAC, SKGE_DRV,
15032+ SK_DRV_RECOVER,pNet->PortNr,-1,SK_FALSE);
15033+#endif
15034+ }
15035+ }
15036+ }
15037+
15038+#ifdef CHECK_TRANSMIT_TIMEOUT
15039+// if (!timer_pending(&pNet->KernelTimer)) {
15040+ pNet->KernelTimer.expires = jiffies + (HZ/4); /* 100ms */
15041+ add_timer(&pNet->KernelTimer);
15042+ pNet->TimerExpired = SK_FALSE;
15043+// }
15044+#endif
15045+ }
15046+}
15047+
15048+
15049+/*****************************************************************************
15050+*
15051+* CheckRXCounters - Checks the the statistics for RX path hang
15052+*
15053+* Description:
15054+* This function is called periodical by a timer.
15055+*
15056+* Notes:
15057+*
15058+* Function Parameters:
15059+*
15060+* Returns:
15061+* Traffic status
15062+*
15063+*/
15064+static SK_BOOL CheckRXCounters(
15065+DEV_NET *pNet) /* holds the pointer to adapter control context */
15066+{
15067+ SK_AC *pAC = pNet->pAC;
15068+ SK_BOOL bStatus = SK_FALSE;
15069+
15070+ /* Variable used to store the MAC RX FIFO RP, RPLev*/
15071+ SK_U32 MACFifoRP = 0;
15072+ SK_U32 MACFifoRLev = 0;
15073+
15074+ /* Variable used to store the PCI RX FIFO RP, RPLev*/
15075+ SK_U32 RXFifoRP = 0;
15076+ SK_U8 RXFifoRLev = 0;
15077+
15078+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
15079+ ("==> CheckRXCounters()\n"));
15080+
15081+ /*Check if statistic counters hangs*/
15082+ if (pNet->LastJiffies == pAC->dev[pNet->PortNr]->last_rx) {
15083+ /* Now read the values of read pointer/level from MAC RX FIFO again */
15084+ SK_IN32(pAC->IoBase, MR_ADDR(pNet->PortNr, RX_GMF_RP), &MACFifoRP);
15085+ SK_IN32(pAC->IoBase, MR_ADDR(pNet->PortNr, RX_GMF_RLEV), &MACFifoRLev);
15086+
15087+ /* Now read the values of read pointer/level from RX FIFO again */
15088+ SK_IN8(pAC->IoBase, Q_ADDR(pAC->GIni.GP[pNet->PortNr].PRxQOff, Q_RX_RP), &RXFifoRP);
15089+ SK_IN8(pAC->IoBase, Q_ADDR(pAC->GIni.GP[pNet->PortNr].PRxQOff, Q_RX_RL), &RXFifoRLev);
15090+
15091+ /* Check if the MAC RX hang */
15092+ if ((MACFifoRP == pNet->PreviousMACFifoRP) &&
15093+ (pNet->PreviousMACFifoRP != 0) &&
15094+ (MACFifoRLev >= pNet->PreviousMACFifoRLev)){
15095+ bStatus = SK_TRUE;
15096+ }
15097+
15098+ /* Check if the PCI RX hang */
15099+ if ((RXFifoRP == pNet->PreviousRXFifoRP) &&
15100+ (pNet->PreviousRXFifoRP != 0) &&
15101+ (RXFifoRLev >= pNet->PreviousRXFifoRLev)){
15102+ /*Set the flag to indicate that the RX FIFO hangs*/
15103+ bStatus = SK_TRUE;
15104+ }
15105+ }
15106+
15107+ /* Store now the values of counters for next check */
15108+ pNet->LastJiffies = pAC->dev[pNet->PortNr]->last_rx;
15109+
15110+ /* Store the values of read pointer/level from MAC RX FIFO for next test */
15111+ pNet->PreviousMACFifoRP = MACFifoRP;
15112+ pNet->PreviousMACFifoRLev = MACFifoRLev;
15113+
15114+ /* Store the values of read pointer/level from RX FIFO for next test */
15115+ pNet->PreviousRXFifoRP = RXFifoRP;
15116+ pNet->PreviousRXFifoRLev = RXFifoRLev;
15117+
15118+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
15119+ ("<== CheckRXCounters()\n"));
15120+
15121+ return bStatus;
15122+}
15123+
15124+/*****************************************************************************
15125+*
15126+* CheckRxPath - Checks if the RX path
15127+*
15128+* Description:
15129+* This function is called periodical by a timer.
15130+*
15131+* Notes:
15132+*
15133+* Function Parameters:
15134+*
15135+* Returns:
15136+* None.
15137+*
15138+*/
15139+static void CheckRxPath(
15140+DEV_NET *pNet) /* holds the pointer to adapter control context */
15141+{
15142+ unsigned long Flags; /* for the spin locks */
15143+ /* Initialize the pAC structure.*/
15144+ SK_AC *pAC = pNet->pAC;
15145+
15146+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
15147+ ("==> CheckRxPath()\n"));
15148+
15149+ /*If the statistics are not changed then could be an RX problem */
15150+ if (CheckRXCounters(pNet)){
15151+ /*
15152+ * First we try the simple solution by resetting the Level Timer
15153+ */
15154+
15155+ /* Stop Level Timer of Status BMU */
15156+ SK_OUT8(pAC->IoBase, STAT_LEV_TIMER_CTRL, TIM_STOP);
15157+
15158+ /* Start Level Timer of Status BMU */
15159+ SK_OUT8(pAC->IoBase, STAT_LEV_TIMER_CTRL, TIM_START);
15160+
15161+ if (!CheckRXCounters(pNet)) {
15162+ return;
15163+ }
15164+
15165+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
15166+ SkLocalEventQueue(pAC, SKGE_DRV,
15167+ SK_DRV_RECOVER,pNet->PortNr,-1,SK_TRUE);
15168+
15169+ /* Reset the fifo counters */
15170+ pNet->PreviousMACFifoRP = 0;
15171+ pNet->PreviousMACFifoRLev = 0;
15172+ pNet->PreviousRXFifoRP = 0;
15173+ pNet->PreviousRXFifoRLev = 0;
15174+
15175+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
15176+ }
15177+
15178+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
15179+ ("<== CheckRxPath()\n"));
15180+}
15181+
15182+
15183+
15184+#endif
15185+
15186+
15187+#ifdef CONFIG_PM
15188+/*****************************************************************************
15189+ *
15190+ * sk98lin_resume - Resume the the card
15191+ *
15192+ * Description:
15193+ * This function resumes the card into the D0 state
15194+ *
15195+ * Returns: N/A
15196+ *
15197+ */
15198+static int sk98lin_resume(
15199+struct pci_dev *pdev) /* the device that is to resume */
15200+{
15201+ struct net_device *dev = pci_get_drvdata(pdev);
15202+ DEV_NET *pNet = (DEV_NET*) dev->priv;
15203+ SK_AC *pAC = pNet->pAC;
15204+ SK_U16 PmCtlSts;
15205+
15206+ /* Set the power state to D0 */
15207+ pci_set_power_state(pdev, 0);
15208+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
15209+ pci_restore_state(pdev);
15210+#else
15211+ pci_restore_state(pdev, pAC->PciState);
15212+#endif
15213+
15214+ pci_enable_device(pdev);
15215+ pci_set_master(pdev);
15216+
15217+ pci_enable_wake(pdev, 3, 0);
15218+ pci_enable_wake(pdev, 4, 0);
15219+
15220+ SK_OUT8(pAC->IoBase, RX_GMF_CTRL_T, (SK_U8)GMF_RST_CLR);
15221+
15222+ /* Set the adapter power state to D0 */
15223+ SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);
15224+ PmCtlSts &= ~(PCI_PM_STATE_D3); /* reset all DState bits */
15225+ PmCtlSts |= PCI_PM_STATE_D0;
15226+ SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PmCtlSts);
15227+
15228+ /* Reinit the adapter and start the port again */
15229+ pAC->BoardLevel = SK_INIT_DATA;
15230+ SkDrvLeaveDiagMode(pAC);
15231+
15232+ if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) ||
15233+ (CHIP_ID_YUKON_2(pAC)) ) {
15234+ pAC->StatusLETable.Done = 0;
15235+ pAC->StatusLETable.Put = 0;
15236+ pAC->StatusLETable.HwPut = 0;
15237+ SkGeY2InitStatBmu(pAC, pAC->IoBase, &pAC->StatusLETable);
15238+ }
15239+
15240+ return 0;
15241+}
15242+
15243+/*****************************************************************************
15244+ *
15245+ * sk98lin_suspend - Suspend the card
15246+ *
15247+ * Description:
15248+ * This function suspends the card into a defined state
15249+ *
15250+ * Returns: N/A
15251+ *
15252+ */
15253+static int sk98lin_suspend(
15254+struct pci_dev *pdev, /* pointer to the device that is to suspend */
15255+u32 state) /* what power state is desired by Linux? */
15256+{
15257+ struct net_device *dev = pci_get_drvdata(pdev);
15258+ DEV_NET *pNet = (DEV_NET*) dev->priv;
15259+ SK_AC *pAC = pNet->pAC;
15260+ SK_U16 PciPMControlStatus;
15261+ SK_U16 PciPMCapabilities;
15262+ SK_MAC_ADDR MacAddr;
15263+ int i;
15264+
15265+ /* GEnesis and first yukon revs do not support power management */
15266+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {
15267+ if (pAC->GIni.GIChipRev == 0) {
15268+ return 0; /* power management not supported */
15269+ }
15270+ }
15271+
15272+ if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
15273+ return 0; /* not supported for this chipset */
15274+ }
15275+
15276+ if (pAC->WolInfo.ConfiguredWolOptions == 0) {
15277+ return 0; /* WOL possible, but disabled via ethtool */
15278+ }
15279+
15280+ if(netif_running(dev)) {
15281+ netif_stop_queue(dev); /* stop device if running */
15282+ }
15283+
15284+ /* read the PM control/status register from the PCI config space */
15285+ SK_IN16(pAC->IoBase, PCI_C(pAC, PCI_PM_CTL_STS), &PciPMControlStatus);
15286+
15287+ /* read the power management capabilities from the config space */
15288+ SK_IN16(pAC->IoBase, PCI_C(pAC, PCI_PM_CAP_REG), &PciPMCapabilities);
15289+
15290+ /* Enable WakeUp with Magic Packet - get MAC address from adapter */
15291+ for (i = 0; i < SK_MAC_ADDR_LEN; i++) {
15292+ /* virtual address: will be used for data */
15293+ SK_IN8(pAC->IoBase, (B2_MAC_1 + i), &MacAddr.a[i]);
15294+ }
15295+
15296+ SkDrvEnterDiagMode(pAC);
15297+ SkEnableWOMagicPacket(pAC, pAC->IoBase, MacAddr);
15298+
15299+ pci_enable_wake(pdev, 3, 1);
15300+ pci_enable_wake(pdev, 4, 1); /* 4 == D3 cold */
15301+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
15302+ pci_save_state(pdev);
15303+#else
15304+ pci_save_state(pdev, pAC->PciState);
15305+#endif
15306+ pci_disable_device(pdev); // NEW
15307+ pci_set_power_state(pdev, state); /* set the state */
15308+
15309+ return 0;
15310+}
15311+
15312+
15313+/******************************************************************************
15314+ *
15315+ * SkEnableWOMagicPacket - Enable Wake on Magic Packet on the adapter
15316+ *
15317+ * Context:
15318+ * init, pageable
15319+ * the adapter should be de-initialized before calling this function
15320+ *
15321+ * Returns:
15322+ * nothing
15323+ */
15324+
15325+static void SkEnableWOMagicPacket(
15326+SK_AC *pAC, /* Adapter Control Context */
15327+SK_IOC IoC, /* I/O control context */
15328+SK_MAC_ADDR MacAddr) /* MacAddr expected in magic packet */
15329+{
15330+ SK_U16 Word;
15331+ SK_U32 DWord;
15332+ int i;
15333+ int HwPortIndex;
15334+ int Port = 0;
15335+
15336+ /* use Port 0 as long as we do not have any dual port cards which support WOL */
15337+ HwPortIndex = 0;
15338+ DWord = 0;
15339+
15340+ SK_OUT16(IoC, 0x0004, 0x0002); /* clear S/W Reset */
15341+ SK_OUT16(IoC, 0x0f10, 0x0002); /* clear Link Reset */
15342+
15343+ /*
15344+ * PHY Configuration:
15345+ * Autonegotioation is enalbed, advertise 10 HD, 10 FD,
15346+ * 100 HD, and 100 FD.
15347+ */
15348+ if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) ||
15349+ (pAC->GIni.GIChipId == CHIP_ID_YUKON) ||
15350+ (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) ||
15351+ (CHIP_ID_YUKON_2(pAC)) ) {
15352+
15353+ SK_OUT8(IoC, 0x0007, 0xa9); /* enable VAUX */
15354+
15355+ /* WA code for COMA mode */
15356+ /* Only for yukon plus based chipsets rev A3 */
15357+ if (pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3) {
15358+ SK_IN32(IoC, B2_GP_IO, &DWord);
15359+ DWord |= GP_DIR_9; /* set to output */
15360+ DWord &= ~GP_IO_9; /* clear PHY reset (active high) */
15361+ SK_OUT32(IoC, B2_GP_IO, DWord); /* clear PHY reset */
15362+ }
15363+
15364+ if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) ||
15365+ (pAC->GIni.GIChipId == CHIP_ID_YUKON)) {
15366+ SK_OUT32(IoC, 0x0f04, 0x01f04001); /* set PHY reset */
15367+ SK_OUT32(IoC, 0x0f04, 0x01f04002); /* clear PHY reset */
15368+ } else {
15369+ SK_OUT8(IoC, 0x0f04, 0x02); /* clear PHY reset */
15370+ }
15371+
15372+ SK_OUT8(IoC, 0x0f00, 0x02); /* clear MAC reset */
15373+ SkGmPhyWrite(pAC, IoC, Port, 4, 0x01e1); /* advertise 10/100 HD/FD */
15374+ SkGmPhyWrite(pAC, IoC, Port, 9, 0x0000); /* do not advertise 1000 HD/FD */
15375+ SkGmPhyWrite(pAC, IoC, Port, 00, 0xB300); /* 100 MBit, disable Autoneg */
15376+ } else if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) {
15377+ SK_OUT8(IoC, 0x0007, 0xa9); /* enable VAUX */
15378+ SK_OUT8(IoC, 0x0f04, 0x02); /* clear PHY reset */
15379+ SK_OUT8(IoC, 0x0f00, 0x02); /* clear MAC reset */
15380+ SkGmPhyWrite(pAC, IoC, Port, 16, 0x0130); /* Enable Automatic Crossover */
15381+ SkGmPhyWrite(pAC, IoC, Port, 00, 0xB300); /* 100 MBit, disable Autoneg */
15382+ }
15383+
15384+
15385+ /*
15386+ * MAC Configuration:
15387+ * Set the MAC to 100 HD and enable the auto update features
15388+ * for Speed, Flow Control and Duplex Mode.
15389+ * If autonegotiation completes successfully the
15390+ * MAC takes the link parameters from the PHY.
15391+ * If the link partner doesn't support autonegotiation
15392+ * the MAC can receive magic packets if the link partner
15393+ * uses 100 HD.
15394+ */
15395+ SK_OUT16(IoC, 0x2804, 0x3832);
15396+
15397+
15398+ /*
15399+ * Set Up Magic Packet parameters
15400+ */
15401+ for (i = 0; i < 6; i+=2) { /* set up magic packet MAC address */
15402+ SK_IN16(IoC, 0x100 + i, &Word);
15403+ SK_OUT16(IoC, 0xf24 + i, Word);
15404+ }
15405+
15406+ SK_OUT16(IoC, 0x0f20, 0x0208); /* enable PME on magic packet */
15407+ /* and on wake up frame */
15408+
15409+ /*
15410+ * Set up PME generation
15411+ */
15412+ /* set PME legacy mode */
15413+ /* Only for PCI express based chipsets */
15414+ if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) ||
15415+ (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) ||
15416+ (CHIP_ID_YUKON_2(pAC))) {
15417+ SkPciReadCfgDWord(pAC, 0x40, &DWord);
15418+ DWord |= 0x8000;
15419+ SkPciWriteCfgDWord(pAC, 0x40, DWord);
15420+ }
15421+
15422+ SK_OUT8(IoC, RX_GMF_CTRL_T, (SK_U8)GMF_RST_SET);
15423+
15424+ /* clear PME status and switch adapter to DState */
15425+ SkPciReadCfgWord(pAC, 0x4c, &Word);
15426+ Word |= 0x103;
15427+ SkPciWriteCfgWord(pAC, 0x4c, Word);
15428+} /* SkEnableWOMagicPacket */
15429+#endif
15430+
15431
15432 /*****************************************************************************
15433 *
15434@@ -347,20 +1197,24 @@
15435 DEV_NET *pNet;
15436 SK_AC *pAC;
15437
15438- pNet = netdev_priv(dev);
15439- pAC = pNet->pAC;
15440- AllocFlag = pAC->AllocFlag;
15441- if (pAC->PciDev) {
15442- pci_release_regions(pAC->PciDev);
15443- }
15444- if (AllocFlag & SK_ALLOC_IRQ) {
15445- free_irq(dev->irq, dev);
15446- }
15447- if (pAC->IoBase) {
15448- iounmap(pAC->IoBase);
15449- }
15450- if (pAC->pDescrMem) {
15451- BoardFreeMem(pAC);
15452+ if (dev->priv) {
15453+ pNet = (DEV_NET*) dev->priv;
15454+ pAC = pNet->pAC;
15455+ AllocFlag = pAC->AllocFlag;
15456+ if (pAC->PciDev) {
15457+ pci_release_regions(pAC->PciDev);
15458+ }
15459+ if (AllocFlag & SK_ALLOC_IRQ) {
15460+ free_irq(dev->irq, dev);
15461+ }
15462+ if (pAC->IoBase) {
15463+ iounmap(pAC->IoBase);
15464+ }
15465+ if (CHIP_ID_YUKON_2(pAC)) {
15466+ SkY2FreeResources(pAC);
15467+ } else {
15468+ BoardFreeMem(pAC);
15469+ }
15470 }
15471
15472 } /* FreeResources */
15473@@ -369,6 +1223,7 @@
15474 MODULE_DESCRIPTION("SysKonnect SK-NET Gigabit Ethernet SK-98xx driver");
15475 MODULE_LICENSE("GPL");
15476
15477+
15478 #ifdef LINK_SPEED_A
15479 static char *Speed_A[SK_MAX_CARD_PARAM] = LINK_SPEED;
15480 #else
15481@@ -447,31 +1302,140 @@
15482 static char *RlmtMode[SK_MAX_CARD_PARAM] = {"", };
15483 #endif
15484
15485-static int IntsPerSec[SK_MAX_CARD_PARAM];
15486-static char *Moderation[SK_MAX_CARD_PARAM];
15487-static char *ModerationMask[SK_MAX_CARD_PARAM];
15488-static char *AutoSizing[SK_MAX_CARD_PARAM];
15489-static char *Stats[SK_MAX_CARD_PARAM];
15490+static int IntsPerSec[SK_MAX_CARD_PARAM];
15491+static char *Moderation[SK_MAX_CARD_PARAM];
15492+static char *ModerationMask[SK_MAX_CARD_PARAM];
15493+
15494+static char *LowLatency[SK_MAX_CARD_PARAM];
15495+
15496+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
15497+module_param_array(Speed_A, charp, NULL, 0);
15498+module_param_array(Speed_B, charp, NULL, 0);
15499+module_param_array(AutoNeg_A, charp, NULL, 0);
15500+module_param_array(AutoNeg_B, charp, NULL, 0);
15501+module_param_array(DupCap_A, charp, NULL, 0);
15502+module_param_array(DupCap_B, charp, NULL, 0);
15503+module_param_array(FlowCtrl_A, charp, NULL, 0);
15504+module_param_array(FlowCtrl_B, charp, NULL, 0);
15505+module_param_array(Role_A, charp, NULL, 0);
15506+module_param_array(Role_B, charp, NULL, 0);
15507+module_param_array(ConType, charp, NULL, 0);
15508+module_param_array(PrefPort, charp, NULL, 0);
15509+module_param_array(RlmtMode, charp, NULL, 0);
15510+/* used for interrupt moderation */
15511+module_param_array(IntsPerSec, int, NULL, 0);
15512+module_param_array(Moderation, charp, NULL, 0);
15513+module_param_array(ModerationMask, charp, NULL, 0);
15514+module_param_array(LowLatency, charp, NULL, 0);
15515+#else
15516+MODULE_PARM(Speed_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15517+MODULE_PARM(Speed_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15518+MODULE_PARM(AutoNeg_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15519+MODULE_PARM(AutoNeg_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15520+MODULE_PARM(DupCap_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15521+MODULE_PARM(DupCap_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15522+MODULE_PARM(FlowCtrl_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15523+MODULE_PARM(FlowCtrl_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15524+MODULE_PARM(Role_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15525+MODULE_PARM(Role_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15526+MODULE_PARM(ConType, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15527+MODULE_PARM(PrefPort, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15528+MODULE_PARM(RlmtMode, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15529+MODULE_PARM(IntsPerSec, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "i");
15530+MODULE_PARM(Moderation, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15531+MODULE_PARM(ModerationMask, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15532+MODULE_PARM(LowLatency, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
15533+#endif
15534+
15535+
15536+/*****************************************************************************
15537+ *
15538+ * sk98lin_remove_device - device deinit function
15539+ *
15540+ * Description:
15541+ * Disable adapter if it is still running, free resources,
15542+ * free device struct.
15543+ *
15544+ * Returns: N/A
15545+ */
15546+
15547+static void sk98lin_remove_device(struct pci_dev *pdev)
15548+{
15549+DEV_NET *pNet;
15550+SK_AC *pAC;
15551+struct SK_NET_DEVICE *next;
15552+unsigned long Flags;
15553+struct net_device *dev = pci_get_drvdata(pdev);
15554+
15555+
15556+ /* Device not available. Return. */
15557+ if (!dev)
15558+ return;
15559+
15560+ pNet = (DEV_NET*) dev->priv;
15561+ pAC = pNet->pAC;
15562+ next = pAC->Next;
15563+
15564+ netif_stop_queue(dev);
15565+ SkGeYellowLED(pAC, pAC->IoBase, 0);
15566+
15567+ if(pAC->BoardLevel == SK_INIT_RUN) {
15568+ /* board is still alive */
15569+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
15570+ SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP,
15571+ 0, -1, SK_FALSE);
15572+ SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP,
15573+ 1, -1, SK_TRUE);
15574+
15575+ /* disable interrupts */
15576+ SK_OUT32(pAC->IoBase, B0_IMSK, 0);
15577+ SkGeDeInit(pAC, pAC->IoBase);
15578+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
15579+ pAC->BoardLevel = SK_INIT_DATA;
15580+ /* We do NOT check here, if IRQ was pending, of course*/
15581+ }
15582+
15583+ if(pAC->BoardLevel == SK_INIT_IO) {
15584+ /* board is still alive */
15585+ SkGeDeInit(pAC, pAC->IoBase);
15586+ pAC->BoardLevel = SK_INIT_DATA;
15587+ }
15588+
15589+ if ((pAC->GIni.GIMacsFound == 2) && pAC->RlmtNets == 2){
15590+ unregister_netdev(pAC->dev[1]);
15591+ free_netdev(pAC->dev[1]);
15592+ }
15593+
15594+ FreeResources(dev);
15595+
15596+#ifdef CONFIG_PROC_FS
15597+ /* Remove the sk98lin procfs device entries */
15598+ if ((pAC->GIni.GIMacsFound == 2) && pAC->RlmtNets == 2){
15599+ remove_proc_entry(pAC->dev[1]->name, pSkRootDir);
15600+ }
15601+ remove_proc_entry(pNet->InitialDevName, pSkRootDir);
15602+#endif
15603+
15604+ dev->get_stats = NULL;
15605+ /*
15606+ * otherwise unregister_netdev calls get_stats with
15607+ * invalid IO ... :-(
15608+ */
15609+ unregister_netdev(dev);
15610+ free_netdev(dev);
15611+ kfree(pAC);
15612+ sk98lin_max_boards_found--;
15613+
15614+#ifdef CONFIG_PROC_FS
15615+ /* Remove all Proc entries if last device */
15616+ if (sk98lin_max_boards_found == 0) {
15617+ /* clear proc-dir */
15618+ remove_proc_entry(pSkRootDir->name, proc_net);
15619+ }
15620+#endif
15621+
15622+}
15623
15624-module_param_array(Speed_A, charp, NULL, 0);
15625-module_param_array(Speed_B, charp, NULL, 0);
15626-module_param_array(AutoNeg_A, charp, NULL, 0);
15627-module_param_array(AutoNeg_B, charp, NULL, 0);
15628-module_param_array(DupCap_A, charp, NULL, 0);
15629-module_param_array(DupCap_B, charp, NULL, 0);
15630-module_param_array(FlowCtrl_A, charp, NULL, 0);
15631-module_param_array(FlowCtrl_B, charp, NULL, 0);
15632-module_param_array(Role_A, charp, NULL, 0);
15633-module_param_array(Role_B, charp, NULL, 0);
15634-module_param_array(ConType, charp, NULL, 0);
15635-module_param_array(PrefPort, charp, NULL, 0);
15636-module_param_array(RlmtMode, charp, NULL, 0);
15637-/* used for interrupt moderation */
15638-module_param_array(IntsPerSec, int, NULL, 0);
15639-module_param_array(Moderation, charp, NULL, 0);
15640-module_param_array(Stats, charp, NULL, 0);
15641-module_param_array(ModerationMask, charp, NULL, 0);
15642-module_param_array(AutoSizing, charp, NULL, 0);
15643
15644 /*****************************************************************************
15645 *
15646@@ -486,7 +1450,7 @@
15647 * 0, if everything is ok
15648 * !=0, on error
15649 */
15650-static int __devinit SkGeBoardInit(struct SK_NET_DEVICE *dev, SK_AC *pAC)
15651+static int __init SkGeBoardInit(struct SK_NET_DEVICE *dev, SK_AC *pAC)
15652 {
15653 short i;
15654 unsigned long Flags;
15655@@ -509,12 +1473,11 @@
15656 spin_lock_init(&pAC->TxPort[i][0].TxDesRingLock);
15657 spin_lock_init(&pAC->RxPort[i].RxDesRingLock);
15658 }
15659- spin_lock_init(&pAC->SlowPathLock);
15660
15661- /* setup phy_id blink timer */
15662- pAC->BlinkTimer.function = SkGeBlinkTimer;
15663- pAC->BlinkTimer.data = (unsigned long) dev;
15664- init_timer(&pAC->BlinkTimer);
15665+ spin_lock_init(&pAC->InitLock); /* Init lock */
15666+ spin_lock_init(&pAC->SlowPathLock);
15667+ spin_lock_init(&pAC->TxQueueLock); /* for Yukon2 chipsets */
15668+ spin_lock_init(&pAC->SetPutIndexLock); /* for Yukon2 chipsets */
15669
15670 /* level 0 init common modules here */
15671
15672@@ -523,7 +1486,7 @@
15673 if (SkGeInit(pAC, pAC->IoBase, SK_INIT_DATA) != 0) {
15674 printk("HWInit (0) failed.\n");
15675 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
15676- return -EIO;
15677+ return(-EAGAIN);
15678 }
15679 SkI2cInit( pAC, pAC->IoBase, SK_INIT_DATA);
15680 SkEventInit(pAC, pAC->IoBase, SK_INIT_DATA);
15681@@ -533,19 +1496,17 @@
15682 SkTimerInit(pAC, pAC->IoBase, SK_INIT_DATA);
15683
15684 pAC->BoardLevel = SK_INIT_DATA;
15685- pAC->RxBufSize = ETH_BUF_SIZE;
15686+ pAC->RxPort[0].RxBufSize = ETH_BUF_SIZE;
15687+ pAC->RxPort[1].RxBufSize = ETH_BUF_SIZE;
15688
15689 SK_PNMI_SET_DRIVER_DESCR(pAC, DescrString);
15690 SK_PNMI_SET_DRIVER_VER(pAC, VerStr);
15691
15692- spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
15693-
15694 /* level 1 init common modules here (HW init) */
15695- spin_lock_irqsave(&pAC->SlowPathLock, Flags);
15696 if (SkGeInit(pAC, pAC->IoBase, SK_INIT_IO) != 0) {
15697 printk("sk98lin: HWInit (1) failed.\n");
15698 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
15699- return -EIO;
15700+ return(-EAGAIN);
15701 }
15702 SkI2cInit( pAC, pAC->IoBase, SK_INIT_IO);
15703 SkEventInit(pAC, pAC->IoBase, SK_INIT_IO);
15704@@ -553,46 +1514,93 @@
15705 SkAddrInit( pAC, pAC->IoBase, SK_INIT_IO);
15706 SkRlmtInit( pAC, pAC->IoBase, SK_INIT_IO);
15707 SkTimerInit(pAC, pAC->IoBase, SK_INIT_IO);
15708+#ifdef Y2_RECOVERY
15709+ /* mark entries invalid */
15710+ pAC->LastPort = 3;
15711+ pAC->LastOpc = 0xFF;
15712+#endif
15713
15714 /* Set chipset type support */
15715- pAC->ChipsetType = 0;
15716 if ((pAC->GIni.GIChipId == CHIP_ID_YUKON) ||
15717- (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE)) {
15718- pAC->ChipsetType = 1;
15719+ (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) ||
15720+ (pAC->GIni.GIChipId == CHIP_ID_YUKON_LP)) {
15721+ pAC->ChipsetType = 1; /* Yukon chipset (descriptor logic) */
15722+ } else if (CHIP_ID_YUKON_2(pAC)) {
15723+ pAC->ChipsetType = 2; /* Yukon2 chipset (list logic) */
15724+ } else {
15725+ pAC->ChipsetType = 0; /* Genesis chipset (descriptor logic) */
15726+ }
15727+
15728+ /* wake on lan support */
15729+ pAC->WolInfo.SupportedWolOptions = 0;
15730+#if defined (ETHTOOL_GWOL) && defined (ETHTOOL_SWOL)
15731+ if (pAC->GIni.GIChipId != CHIP_ID_GENESIS) {
15732+ pAC->WolInfo.SupportedWolOptions = WAKE_MAGIC;
15733+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {
15734+ if (pAC->GIni.GIChipRev == 0) {
15735+ pAC->WolInfo.SupportedWolOptions = 0;
15736+ }
15737+ }
15738 }
15739+#endif
15740+ pAC->WolInfo.ConfiguredWolOptions = pAC->WolInfo.SupportedWolOptions;
15741
15742 GetConfiguration(pAC);
15743 if (pAC->RlmtNets == 2) {
15744- pAC->GIni.GIPortUsage = SK_MUL_LINK;
15745+ pAC->GIni.GP[0].PPortUsage = SK_MUL_LINK;
15746+ pAC->GIni.GP[1].PPortUsage = SK_MUL_LINK;
15747 }
15748
15749 pAC->BoardLevel = SK_INIT_IO;
15750 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
15751
15752- if (pAC->GIni.GIMacsFound == 2) {
15753- Ret = request_irq(dev->irq, SkGeIsr, SA_SHIRQ, "sk98lin", dev);
15754- } else if (pAC->GIni.GIMacsFound == 1) {
15755- Ret = request_irq(dev->irq, SkGeIsrOnePort, SA_SHIRQ,
15756- "sk98lin", dev);
15757- } else {
15758- printk(KERN_WARNING "sk98lin: Illegal number of ports: %d\n",
15759- pAC->GIni.GIMacsFound);
15760- return -EIO;
15761+ if (!CHIP_ID_YUKON_2(pAC)) {
15762+ if (pAC->GIni.GIMacsFound == 2) {
15763+ Ret = request_irq(dev->irq, SkGeIsr, SA_SHIRQ, dev->name, dev);
15764+ } else if (pAC->GIni.GIMacsFound == 1) {
15765+ Ret = request_irq(dev->irq, SkGeIsrOnePort, SA_SHIRQ, dev->name, dev);
15766+ } else {
15767+ printk(KERN_WARNING "sk98lin: Illegal number of ports: %d\n",
15768+ pAC->GIni.GIMacsFound);
15769+ return -EAGAIN;
15770+ }
15771+ }
15772+ else {
15773+ Ret = request_irq(dev->irq, SkY2Isr, SA_SHIRQ, dev->name, dev);
15774 }
15775
15776 if (Ret) {
15777 printk(KERN_WARNING "sk98lin: Requested IRQ %d is busy.\n",
15778- dev->irq);
15779- return Ret;
15780+ dev->irq);
15781+ return -EAGAIN;
15782 }
15783 pAC->AllocFlag |= SK_ALLOC_IRQ;
15784
15785- /* Alloc memory for this board (Mem for RxD/TxD) : */
15786- if(!BoardAllocMem(pAC)) {
15787- printk("No memory for descriptor rings.\n");
15788- return -ENOMEM;
15789+ /*
15790+ ** Alloc descriptor/LETable memory for this board (both RxD/TxD)
15791+ */
15792+ if (CHIP_ID_YUKON_2(pAC)) {
15793+ if (!SkY2AllocateResources(pAC)) {
15794+ printk("No memory for Yukon2 settings\n");
15795+ return(-EAGAIN);
15796+ }
15797+ } else {
15798+ if(!BoardAllocMem(pAC)) {
15799+ printk("No memory for descriptor rings.\n");
15800+ return(-EAGAIN);
15801+ }
15802 }
15803
15804+#ifdef SK_USE_CSUM
15805+ SkCsSetReceiveFlags(pAC,
15806+ SKCS_PROTO_IP | SKCS_PROTO_TCP | SKCS_PROTO_UDP,
15807+ &pAC->CsOfs1, &pAC->CsOfs2, 0);
15808+ pAC->CsOfs = (pAC->CsOfs2 << 16) | pAC->CsOfs1;
15809+#endif
15810+
15811+ /*
15812+ ** Function BoardInitMem() for Yukon dependent settings...
15813+ */
15814 BoardInitMem(pAC);
15815 /* tschilling: New common function with minimum size check. */
15816 DualNet = SK_FALSE;
15817@@ -604,11 +1612,22 @@
15818 pAC,
15819 pAC->ActivePort,
15820 DualNet)) {
15821- BoardFreeMem(pAC);
15822+ if (CHIP_ID_YUKON_2(pAC)) {
15823+ SkY2FreeResources(pAC);
15824+ } else {
15825+ BoardFreeMem(pAC);
15826+ }
15827+
15828 printk("sk98lin: SkGeInitAssignRamToQueues failed.\n");
15829- return -EIO;
15830+ return(-EAGAIN);
15831 }
15832
15833+ /*
15834+ * Register the device here
15835+ */
15836+ pAC->Next = SkGeRootDev;
15837+ SkGeRootDev = dev;
15838+
15839 return (0);
15840 } /* SkGeBoardInit */
15841
15842@@ -627,7 +1646,8 @@
15843 * SK_TRUE, if all memory could be allocated
15844 * SK_FALSE, if not
15845 */
15846-static __devinit SK_BOOL BoardAllocMem(SK_AC *pAC)
15847+static SK_BOOL BoardAllocMem(
15848+SK_AC *pAC)
15849 {
15850 caddr_t pDescrMem; /* pointer to descriptor memory area */
15851 size_t AllocLength; /* length of complete descriptor area */
15852@@ -697,16 +1717,20 @@
15853
15854 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
15855 ("BoardFreeMem\n"));
15856+
15857+ if (pAC->pDescrMem) {
15858+
15859 #if (BITS_PER_LONG == 32)
15860- AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound + 8;
15861+ AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound + 8;
15862 #else
15863- AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound
15864- + RX_RING_SIZE + 8;
15865+ AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound
15866+ + RX_RING_SIZE + 8;
15867 #endif
15868
15869- pci_free_consistent(pAC->PciDev, AllocLength,
15870+ pci_free_consistent(pAC->PciDev, AllocLength,
15871 pAC->pDescrMem, pAC->pDescrMemDMA);
15872- pAC->pDescrMem = NULL;
15873+ pAC->pDescrMem = NULL;
15874+ }
15875 } /* BoardFreeMem */
15876
15877
15878@@ -715,12 +1739,13 @@
15879 * BoardInitMem - initiate the descriptor rings
15880 *
15881 * Description:
15882- * This function sets the descriptor rings up in memory.
15883+ * This function sets the descriptor rings or LETables up in memory.
15884 * The adapter is initialized with the descriptor start addresses.
15885 *
15886 * Returns: N/A
15887 */
15888-static __devinit void BoardInitMem(SK_AC *pAC)
15889+static void BoardInitMem(
15890+SK_AC *pAC) /* pointer to adapter context */
15891 {
15892 int i; /* loop counter */
15893 int RxDescrSize; /* the size of a rx descriptor rounded up to alignment*/
15894@@ -729,34 +1754,37 @@
15895 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
15896 ("BoardInitMem\n"));
15897
15898- RxDescrSize = (((sizeof(RXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN;
15899- pAC->RxDescrPerRing = RX_RING_SIZE / RxDescrSize;
15900- TxDescrSize = (((sizeof(TXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN;
15901- pAC->TxDescrPerRing = TX_RING_SIZE / RxDescrSize;
15902+ if (!pAC->GIni.GIYukon2) {
15903+ RxDescrSize = (((sizeof(RXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN;
15904+ pAC->RxDescrPerRing = RX_RING_SIZE / RxDescrSize;
15905+ TxDescrSize = (((sizeof(TXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN;
15906+ pAC->TxDescrPerRing = TX_RING_SIZE / RxDescrSize;
15907
15908- for (i=0; i<pAC->GIni.GIMacsFound; i++) {
15909- SetupRing(
15910- pAC,
15911- pAC->TxPort[i][0].pTxDescrRing,
15912- pAC->TxPort[i][0].VTxDescrRing,
15913- (RXD**)&pAC->TxPort[i][0].pTxdRingHead,
15914- (RXD**)&pAC->TxPort[i][0].pTxdRingTail,
15915- (RXD**)&pAC->TxPort[i][0].pTxdRingPrev,
15916- &pAC->TxPort[i][0].TxdRingFree,
15917- SK_TRUE);
15918- SetupRing(
15919- pAC,
15920- pAC->RxPort[i].pRxDescrRing,
15921- pAC->RxPort[i].VRxDescrRing,
15922- &pAC->RxPort[i].pRxdRingHead,
15923- &pAC->RxPort[i].pRxdRingTail,
15924- &pAC->RxPort[i].pRxdRingPrev,
15925- &pAC->RxPort[i].RxdRingFree,
15926- SK_FALSE);
15927+ for (i=0; i<pAC->GIni.GIMacsFound; i++) {
15928+ SetupRing(
15929+ pAC,
15930+ pAC->TxPort[i][0].pTxDescrRing,
15931+ pAC->TxPort[i][0].VTxDescrRing,
15932+ (RXD**)&pAC->TxPort[i][0].pTxdRingHead,
15933+ (RXD**)&pAC->TxPort[i][0].pTxdRingTail,
15934+ (RXD**)&pAC->TxPort[i][0].pTxdRingPrev,
15935+ &pAC->TxPort[i][0].TxdRingFree,
15936+ &pAC->TxPort[i][0].TxdRingPrevFree,
15937+ SK_TRUE);
15938+ SetupRing(
15939+ pAC,
15940+ pAC->RxPort[i].pRxDescrRing,
15941+ pAC->RxPort[i].VRxDescrRing,
15942+ &pAC->RxPort[i].pRxdRingHead,
15943+ &pAC->RxPort[i].pRxdRingTail,
15944+ &pAC->RxPort[i].pRxdRingPrev,
15945+ &pAC->RxPort[i].RxdRingFree,
15946+ &pAC->RxPort[i].RxdRingFree,
15947+ SK_FALSE);
15948+ }
15949 }
15950 } /* BoardInitMem */
15951
15952-
15953 /*****************************************************************************
15954 *
15955 * SetupRing - create one descriptor ring
15956@@ -776,6 +1804,7 @@
15957 RXD **ppRingTail, /* address where the tail should be written */
15958 RXD **ppRingPrev, /* address where the tail should be written */
15959 int *pRingFree, /* address where the # of free descr. goes */
15960+int *pRingPrevFree, /* address where the # of free descr. goes */
15961 SK_BOOL IsTx) /* flag: is this a tx ring */
15962 {
15963 int i; /* loop counter */
15964@@ -808,7 +1837,7 @@
15965 /* set the pointers right */
15966 pDescr->VNextRxd = VNextDescr & 0xffffffffULL;
15967 pDescr->pNextRxd = pNextDescr;
15968- if (!IsTx) pDescr->TcpSumStarts = ETH_HLEN << 16 | ETH_HLEN;
15969+ pDescr->TcpSumStarts = pAC->CsOfs;
15970
15971 /* advance one step */
15972 pPrevDescr = pDescr;
15973@@ -818,11 +1847,12 @@
15974 }
15975 pPrevDescr->pNextRxd = (RXD*) pMemArea;
15976 pPrevDescr->VNextRxd = VMemArea;
15977- pDescr = (RXD*) pMemArea;
15978- *ppRingHead = (RXD*) pMemArea;
15979- *ppRingTail = *ppRingHead;
15980- *ppRingPrev = pPrevDescr;
15981- *pRingFree = DescrNum;
15982+ pDescr = (RXD*) pMemArea;
15983+ *ppRingHead = (RXD*) pMemArea;
15984+ *ppRingTail = *ppRingHead;
15985+ *ppRingPrev = pPrevDescr;
15986+ *pRingFree = DescrNum;
15987+ *pRingPrevFree = DescrNum;
15988 } /* SetupRing */
15989
15990
15991@@ -887,17 +1917,35 @@
15992 SK_AC *pAC;
15993 SK_U32 IntSrc; /* interrupts source register contents */
15994
15995- pNet = netdev_priv(dev);
15996+ pNet = (DEV_NET*) dev->priv;
15997 pAC = pNet->pAC;
15998
15999 /*
16000 * Check and process if its our interrupt
16001 */
16002 SK_IN32(pAC->IoBase, B0_SP_ISRC, &IntSrc);
16003- if (IntSrc == 0) {
16004+ if ((IntSrc == 0) && (!pNet->NetConsoleMode)) {
16005 return SkIsrRetNone;
16006 }
16007
16008+#ifdef CONFIG_SK98LIN_NAPI
16009+ if (netif_rx_schedule_prep(dev)) {
16010+ pAC->GIni.GIValIrqMask &= ~(NAPI_DRV_IRQS);
16011+ SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
16012+ __netif_rx_schedule(dev);
16013+ }
16014+
16015+#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
16016+ if (IntSrc & IS_XA1_F) {
16017+ CLEAR_TX_IRQ(0, TX_PRIO_LOW);
16018+ }
16019+ if (IntSrc & IS_XA2_F) {
16020+ CLEAR_TX_IRQ(1, TX_PRIO_LOW);
16021+ }
16022+#endif
16023+
16024+
16025+#else
16026 while (((IntSrc & IRQ_MASK) & ~SPECIAL_IRQS) != 0) {
16027 #if 0 /* software irq currently not used */
16028 if (IntSrc & IS_IRQ_SW) {
16029@@ -911,6 +1959,7 @@
16030 SK_DBGCAT_DRV_INT_SRC,
16031 ("EOF RX1 IRQ\n"));
16032 ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE);
16033+ CLEAR_AND_START_RX(0);
16034 SK_PNMI_CNT_RX_INTR(pAC, 0);
16035 }
16036 if (IntSrc & IS_R2_F) {
16037@@ -918,6 +1967,7 @@
16038 SK_DBGCAT_DRV_INT_SRC,
16039 ("EOF RX2 IRQ\n"));
16040 ReceiveIrq(pAC, &pAC->RxPort[1], SK_TRUE);
16041+ CLEAR_AND_START_RX(1);
16042 SK_PNMI_CNT_RX_INTR(pAC, 1);
16043 }
16044 #ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
16045@@ -925,6 +1975,7 @@
16046 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
16047 SK_DBGCAT_DRV_INT_SRC,
16048 ("EOF AS TX1 IRQ\n"));
16049+ CLEAR_TX_IRQ(0, TX_PRIO_LOW);
16050 SK_PNMI_CNT_TX_INTR(pAC, 0);
16051 spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
16052 FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]);
16053@@ -934,6 +1985,7 @@
16054 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
16055 SK_DBGCAT_DRV_INT_SRC,
16056 ("EOF AS TX2 IRQ\n"));
16057+ CLEAR_TX_IRQ(1, TX_PRIO_LOW);
16058 SK_PNMI_CNT_TX_INTR(pAC, 1);
16059 spin_lock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock);
16060 FreeTxDescriptors(pAC, &pAC->TxPort[1][TX_PRIO_LOW]);
16061@@ -944,38 +1996,28 @@
16062 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
16063 SK_DBGCAT_DRV_INT_SRC,
16064 ("EOF SY TX1 IRQ\n"));
16065+ CLEAR_TX_IRQ(0, TX_PRIO_HIGH);
16066 SK_PNMI_CNT_TX_INTR(pAC, 1);
16067 spin_lock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock);
16068 FreeTxDescriptors(pAC, 0, TX_PRIO_HIGH);
16069 spin_unlock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock);
16070- ClearTxIrq(pAC, 0, TX_PRIO_HIGH);
16071 }
16072 if (IntSrc & IS_XS2_F) {
16073 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
16074 SK_DBGCAT_DRV_INT_SRC,
16075 ("EOF SY TX2 IRQ\n"));
16076+ CLEAR_TX_IRQ(1, TX_PRIO_HIGH);
16077 SK_PNMI_CNT_TX_INTR(pAC, 1);
16078 spin_lock(&pAC->TxPort[1][TX_PRIO_HIGH].TxDesRingLock);
16079 FreeTxDescriptors(pAC, 1, TX_PRIO_HIGH);
16080 spin_unlock(&pAC->TxPort[1][TX_PRIO_HIGH].TxDesRingLock);
16081- ClearTxIrq(pAC, 1, TX_PRIO_HIGH);
16082 }
16083 #endif
16084 #endif
16085
16086- /* do all IO at once */
16087- if (IntSrc & IS_R1_F)
16088- ClearAndStartRx(pAC, 0);
16089- if (IntSrc & IS_R2_F)
16090- ClearAndStartRx(pAC, 1);
16091-#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
16092- if (IntSrc & IS_XA1_F)
16093- ClearTxIrq(pAC, 0, TX_PRIO_LOW);
16094- if (IntSrc & IS_XA2_F)
16095- ClearTxIrq(pAC, 1, TX_PRIO_LOW);
16096-#endif
16097 SK_IN32(pAC->IoBase, B0_ISRC, &IntSrc);
16098 } /* while (IntSrc & IRQ_MASK != 0) */
16099+#endif
16100
16101 IntSrc &= pAC->GIni.GIValIrqMask;
16102 if ((IntSrc & SPECIAL_IRQS) || pAC->CheckQueue) {
16103@@ -989,18 +2031,12 @@
16104 SkEventDispatcher(pAC, pAC->IoBase);
16105 spin_unlock(&pAC->SlowPathLock);
16106 }
16107- /*
16108- * do it all again is case we cleared an interrupt that
16109- * came in after handling the ring (OUTs may be delayed
16110- * in hardware buffers, but are through after IN)
16111- *
16112- * rroesler: has been commented out and shifted to
16113- * SkGeDrvEvent(), because it is timer
16114- * guarded now
16115- *
16116+
16117+#ifndef CONFIG_SK98LIN_NAPI
16118+ /* Handle interrupts */
16119 ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE);
16120 ReceiveIrq(pAC, &pAC->RxPort[1], SK_TRUE);
16121- */
16122+#endif
16123
16124 if (pAC->CheckQueue) {
16125 pAC->CheckQueue = SK_FALSE;
16126@@ -1036,17 +2072,32 @@
16127 SK_AC *pAC;
16128 SK_U32 IntSrc; /* interrupts source register contents */
16129
16130- pNet = netdev_priv(dev);
16131+ pNet = (DEV_NET*) dev->priv;
16132 pAC = pNet->pAC;
16133
16134 /*
16135 * Check and process if its our interrupt
16136 */
16137 SK_IN32(pAC->IoBase, B0_SP_ISRC, &IntSrc);
16138- if (IntSrc == 0) {
16139+ if ((IntSrc == 0) && (!pNet->NetConsoleMode)) {
16140 return SkIsrRetNone;
16141 }
16142
16143+#ifdef CONFIG_SK98LIN_NAPI
16144+ if (netif_rx_schedule_prep(dev)) {
16145+ CLEAR_AND_START_RX(0);
16146+ CLEAR_TX_IRQ(0, TX_PRIO_LOW);
16147+ pAC->GIni.GIValIrqMask &= ~(NAPI_DRV_IRQS);
16148+ SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
16149+ __netif_rx_schedule(dev);
16150+ }
16151+
16152+#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
16153+ if (IntSrc & IS_XA1_F) {
16154+ CLEAR_TX_IRQ(0, TX_PRIO_LOW);
16155+ }
16156+#endif
16157+#else
16158 while (((IntSrc & IRQ_MASK) & ~SPECIAL_IRQS) != 0) {
16159 #if 0 /* software irq currently not used */
16160 if (IntSrc & IS_IRQ_SW) {
16161@@ -1060,6 +2111,7 @@
16162 SK_DBGCAT_DRV_INT_SRC,
16163 ("EOF RX1 IRQ\n"));
16164 ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE);
16165+ CLEAR_AND_START_RX(0);
16166 SK_PNMI_CNT_RX_INTR(pAC, 0);
16167 }
16168 #ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
16169@@ -1067,6 +2119,7 @@
16170 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
16171 SK_DBGCAT_DRV_INT_SRC,
16172 ("EOF AS TX1 IRQ\n"));
16173+ CLEAR_TX_IRQ(0, TX_PRIO_LOW);
16174 SK_PNMI_CNT_TX_INTR(pAC, 0);
16175 spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
16176 FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]);
16177@@ -1077,24 +2130,18 @@
16178 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
16179 SK_DBGCAT_DRV_INT_SRC,
16180 ("EOF SY TX1 IRQ\n"));
16181+ CLEAR_TX_IRQ(0, TX_PRIO_HIGH);
16182 SK_PNMI_CNT_TX_INTR(pAC, 0);
16183 spin_lock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock);
16184 FreeTxDescriptors(pAC, 0, TX_PRIO_HIGH);
16185 spin_unlock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock);
16186- ClearTxIrq(pAC, 0, TX_PRIO_HIGH);
16187 }
16188 #endif
16189 #endif
16190
16191- /* do all IO at once */
16192- if (IntSrc & IS_R1_F)
16193- ClearAndStartRx(pAC, 0);
16194-#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
16195- if (IntSrc & IS_XA1_F)
16196- ClearTxIrq(pAC, 0, TX_PRIO_LOW);
16197-#endif
16198 SK_IN32(pAC->IoBase, B0_ISRC, &IntSrc);
16199 } /* while (IntSrc & IRQ_MASK != 0) */
16200+#endif
16201
16202 IntSrc &= pAC->GIni.GIValIrqMask;
16203 if ((IntSrc & SPECIAL_IRQS) || pAC->CheckQueue) {
16204@@ -1108,17 +2155,10 @@
16205 SkEventDispatcher(pAC, pAC->IoBase);
16206 spin_unlock(&pAC->SlowPathLock);
16207 }
16208- /*
16209- * do it all again is case we cleared an interrupt that
16210- * came in after handling the ring (OUTs may be delayed
16211- * in hardware buffers, but are through after IN)
16212- *
16213- * rroesler: has been commented out and shifted to
16214- * SkGeDrvEvent(), because it is timer
16215- * guarded now
16216- *
16217+
16218+#ifndef CONFIG_SK98LIN_NAPI
16219 ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE);
16220- */
16221+#endif
16222
16223 /* IRQ is processed - Enable IRQs again*/
16224 SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
16225@@ -1126,25 +2166,6 @@
16226 return SkIsrRetHandled;
16227 } /* SkGeIsrOnePort */
16228
16229-#ifdef CONFIG_NET_POLL_CONTROLLER
16230-/****************************************************************************
16231- *
16232- * SkGePollController - polling receive, for netconsole
16233- *
16234- * Description:
16235- * Polling receive - used by netconsole and other diagnostic tools
16236- * to allow network i/o with interrupts disabled.
16237- *
16238- * Returns: N/A
16239- */
16240-static void SkGePollController(struct net_device *dev)
16241-{
16242- disable_irq(dev->irq);
16243- SkGeIsr(dev->irq, dev, NULL);
16244- enable_irq(dev->irq);
16245-}
16246-#endif
16247-
16248 /****************************************************************************
16249 *
16250 * SkGeOpen - handle start of initialized adapter
16251@@ -1162,27 +2183,27 @@
16252 * != 0 on error
16253 */
16254 static int SkGeOpen(
16255-struct SK_NET_DEVICE *dev)
16256+struct SK_NET_DEVICE *dev) /* the device that is to be opened */
16257 {
16258- DEV_NET *pNet;
16259- SK_AC *pAC;
16260- unsigned long Flags; /* for spin lock */
16261- int i;
16262- SK_EVPARA EvPara; /* an event parameter union */
16263+ DEV_NET *pNet = (DEV_NET*) dev->priv;
16264+ SK_AC *pAC = pNet->pAC;
16265+ unsigned long Flags; /* for the spin locks */
16266+ unsigned long InitFlags; /* for the spin locks */
16267+ int CurrMac; /* loop ctr for ports */
16268
16269- pNet = netdev_priv(dev);
16270- pAC = pNet->pAC;
16271-
16272 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
16273 ("SkGeOpen: pAC=0x%lX:\n", (unsigned long)pAC));
16274+ spin_lock_irqsave(&pAC->InitLock, InitFlags);
16275
16276-#ifdef SK_DIAG_SUPPORT
16277 if (pAC->DiagModeActive == DIAG_ACTIVE) {
16278 if (pAC->Pnmi.DiagAttached == SK_DIAG_RUNNING) {
16279 return (-1); /* still in use by diag; deny actions */
16280 }
16281 }
16282-#endif
16283+
16284+ if (!try_module_get(THIS_MODULE)) {
16285+ return (-1); /* increase of usage count not possible */
16286+ }
16287
16288 /* Set blink mode */
16289 if ((pAC->PciDev->vendor == 0x1186) || (pAC->PciDev->vendor == 0x11ab ))
16290@@ -1191,6 +2212,7 @@
16291 if (pAC->BoardLevel == SK_INIT_DATA) {
16292 /* level 1 init common modules here */
16293 if (SkGeInit(pAC, pAC->IoBase, SK_INIT_IO) != 0) {
16294+ module_put(THIS_MODULE); /* decrease usage count */
16295 printk("%s: HWInit (1) failed.\n", pAC->dev[pNet->PortNr]->name);
16296 return (-1);
16297 }
16298@@ -1201,11 +2223,17 @@
16299 SkRlmtInit (pAC, pAC->IoBase, SK_INIT_IO);
16300 SkTimerInit (pAC, pAC->IoBase, SK_INIT_IO);
16301 pAC->BoardLevel = SK_INIT_IO;
16302+#ifdef Y2_RECOVERY
16303+ /* mark entries invalid */
16304+ pAC->LastPort = 3;
16305+ pAC->LastOpc = 0xFF;
16306+#endif
16307 }
16308
16309 if (pAC->BoardLevel != SK_INIT_RUN) {
16310 /* tschilling: Level 2 init modules here, check return value. */
16311 if (SkGeInit(pAC, pAC->IoBase, SK_INIT_RUN) != 0) {
16312+ module_put(THIS_MODULE); /* decrease usage count */
16313 printk("%s: HWInit (2) failed.\n", pAC->dev[pNet->PortNr]->name);
16314 return (-1);
16315 }
16316@@ -1218,44 +2246,62 @@
16317 pAC->BoardLevel = SK_INIT_RUN;
16318 }
16319
16320- for (i=0; i<pAC->GIni.GIMacsFound; i++) {
16321- /* Enable transmit descriptor polling. */
16322- SkGePollTxD(pAC, pAC->IoBase, i, SK_TRUE);
16323- FillRxRing(pAC, &pAC->RxPort[i]);
16324+ for (CurrMac=0; CurrMac<pAC->GIni.GIMacsFound; CurrMac++) {
16325+ if (!CHIP_ID_YUKON_2(pAC)) {
16326+ /* Enable transmit descriptor polling. */
16327+ SkGePollTxD(pAC, pAC->IoBase, CurrMac, SK_TRUE);
16328+ FillRxRing(pAC, &pAC->RxPort[CurrMac]);
16329+ SkMacRxTxEnable(pAC, pAC->IoBase, pNet->PortNr);
16330+ }
16331 }
16332- SkGeYellowLED(pAC, pAC->IoBase, 1);
16333
16334- StartDrvCleanupTimer(pAC);
16335+ SkGeYellowLED(pAC, pAC->IoBase, 1);
16336 SkDimEnableModerationIfNeeded(pAC);
16337- SkDimDisplayModerationSettings(pAC);
16338
16339- pAC->GIni.GIValIrqMask &= IRQ_MASK;
16340-
16341- /* enable Interrupts */
16342- SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
16343- SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK);
16344+ if (!CHIP_ID_YUKON_2(pAC)) {
16345+ /*
16346+ ** Has been setup already at SkGeInit(SK_INIT_IO),
16347+ ** but additional masking added for Genesis & Yukon
16348+ ** chipsets -> modify it...
16349+ */
16350+ pAC->GIni.GIValIrqMask &= IRQ_MASK;
16351+#ifndef USE_TX_COMPLETE
16352+ pAC->GIni.GIValIrqMask &= ~(TX_COMPL_IRQS);
16353+#endif
16354+ }
16355
16356 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
16357
16358 if ((pAC->RlmtMode != 0) && (pAC->MaxPorts == 0)) {
16359- EvPara.Para32[0] = pAC->RlmtNets;
16360- EvPara.Para32[1] = -1;
16361- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_SET_NETS,
16362- EvPara);
16363- EvPara.Para32[0] = pAC->RlmtMode;
16364- EvPara.Para32[1] = 0;
16365- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_MODE_CHANGE,
16366- EvPara);
16367+ SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_SET_NETS,
16368+ pAC->RlmtNets, -1, SK_FALSE);
16369+ SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_MODE_CHANGE,
16370+ pAC->RlmtMode, 0, SK_FALSE);
16371 }
16372
16373- EvPara.Para32[0] = pNet->NetNr;
16374- EvPara.Para32[1] = -1;
16375- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara);
16376- SkEventDispatcher(pAC, pAC->IoBase);
16377+ SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_START,
16378+ pNet->NetNr, -1, SK_TRUE);
16379 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
16380
16381- pAC->MaxPorts++;
16382+#ifdef Y2_RECOVERY
16383+ pNet->TimerExpired = SK_FALSE;
16384+ pNet->InRecover = SK_FALSE;
16385+ pNet->NetConsoleMode = SK_FALSE;
16386+
16387+ /* Initialize the kernel timer */
16388+ init_timer(&pNet->KernelTimer);
16389+ pNet->KernelTimer.function = SkGeHandleKernelTimer;
16390+ pNet->KernelTimer.data = (unsigned long) pNet;
16391+ pNet->KernelTimer.expires = jiffies + (HZ/4); /* initially 250ms */
16392+ add_timer(&pNet->KernelTimer);
16393+#endif
16394+
16395+ /* enable Interrupts */
16396+ SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
16397+ SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK);
16398
16399+ pAC->MaxPorts++;
16400+ spin_unlock_irqrestore(&pAC->InitLock, InitFlags);
16401
16402 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
16403 ("SkGeOpen suceeded\n"));
16404@@ -1276,32 +2322,37 @@
16405 * error code - on error
16406 */
16407 static int SkGeClose(
16408-struct SK_NET_DEVICE *dev)
16409+struct SK_NET_DEVICE *dev) /* the device that is to be closed */
16410 {
16411- DEV_NET *pNet;
16412- DEV_NET *newPtrNet;
16413- SK_AC *pAC;
16414-
16415- unsigned long Flags; /* for spin lock */
16416- int i;
16417- int PortIdx;
16418- SK_EVPARA EvPara;
16419-
16420+ DEV_NET *pNet = (DEV_NET*) dev->priv;
16421+ SK_AC *pAC = pNet->pAC;
16422+ DEV_NET *newPtrNet;
16423+ unsigned long Flags; /* for the spin locks */
16424+ unsigned long InitFlags; /* for the spin locks */
16425+ int CurrMac; /* loop ctr for the current MAC */
16426+ int PortIdx;
16427+#ifdef CONFIG_SK98LIN_NAPI
16428+ int WorkToDo = 1; /* min(*budget, dev->quota); */
16429+ int WorkDone = 0;
16430+#endif
16431 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
16432 ("SkGeClose: pAC=0x%lX ", (unsigned long)pAC));
16433+ spin_lock_irqsave(&pAC->InitLock, InitFlags);
16434
16435- pNet = netdev_priv(dev);
16436- pAC = pNet->pAC;
16437+#ifdef Y2_RECOVERY
16438+ pNet->InRecover = SK_TRUE;
16439+ del_timer(&pNet->KernelTimer);
16440+#endif
16441
16442-#ifdef SK_DIAG_SUPPORT
16443 if (pAC->DiagModeActive == DIAG_ACTIVE) {
16444 if (pAC->DiagFlowCtrl == SK_FALSE) {
16445+ module_put(THIS_MODULE);
16446 /*
16447 ** notify that the interface which has been closed
16448 ** by operator interaction must not be started up
16449 ** again when the DIAG has finished.
16450 */
16451- newPtrNet = netdev_priv(pAC->dev[0]);
16452+ newPtrNet = (DEV_NET *) pAC->dev[0]->priv;
16453 if (newPtrNet == pNet) {
16454 pAC->WasIfUp[0] = SK_FALSE;
16455 } else {
16456@@ -1312,7 +2363,6 @@
16457 pAC->DiagFlowCtrl = SK_FALSE;
16458 }
16459 }
16460-#endif
16461
16462 netif_stop_queue(dev);
16463
16464@@ -1321,8 +2371,6 @@
16465 else
16466 PortIdx = pNet->NetNr;
16467
16468- StopDrvCleanupTimer(pAC);
16469-
16470 /*
16471 * Clear multicast table, promiscuous mode ....
16472 */
16473@@ -1334,46 +2382,101 @@
16474 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
16475 /* disable interrupts */
16476 SK_OUT32(pAC->IoBase, B0_IMSK, 0);
16477- EvPara.Para32[0] = pNet->NetNr;
16478- EvPara.Para32[1] = -1;
16479- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
16480- SkEventDispatcher(pAC, pAC->IoBase);
16481+ SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP,
16482+ pNet->NetNr, -1, SK_TRUE);
16483 SK_OUT32(pAC->IoBase, B0_IMSK, 0);
16484 /* stop the hardware */
16485- SkGeDeInit(pAC, pAC->IoBase);
16486- pAC->BoardLevel = SK_INIT_DATA;
16487+
16488+
16489+ if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 1)) {
16490+ /* RLMT check link state mode */
16491+ for (CurrMac=0; CurrMac<pAC->GIni.GIMacsFound; CurrMac++) {
16492+ if (CHIP_ID_YUKON_2(pAC))
16493+ SkY2PortStop( pAC,
16494+ pAC->IoBase,
16495+ CurrMac,
16496+ SK_STOP_ALL,
16497+ SK_HARD_RST);
16498+ else
16499+ SkGeStopPort( pAC,
16500+ pAC->IoBase,
16501+ CurrMac,
16502+ SK_STOP_ALL,
16503+ SK_HARD_RST);
16504+ } /* for */
16505+ } else {
16506+ /* Single link or single port */
16507+ if (CHIP_ID_YUKON_2(pAC))
16508+ SkY2PortStop( pAC,
16509+ pAC->IoBase,
16510+ PortIdx,
16511+ SK_STOP_ALL,
16512+ SK_HARD_RST);
16513+ else
16514+ SkGeStopPort( pAC,
16515+ pAC->IoBase,
16516+ PortIdx,
16517+ SK_STOP_ALL,
16518+ SK_HARD_RST);
16519+ }
16520 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
16521 } else {
16522-
16523 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
16524- EvPara.Para32[0] = pNet->NetNr;
16525- EvPara.Para32[1] = -1;
16526- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
16527- SkPnmiEvent(pAC, pAC->IoBase, SK_PNMI_EVT_XMAC_RESET, EvPara);
16528- SkEventDispatcher(pAC, pAC->IoBase);
16529+ SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP,
16530+ pNet->NetNr, -1, SK_FALSE);
16531+ SkLocalEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET,
16532+ pNet->NetNr, -1, SK_TRUE);
16533 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
16534
16535 /* Stop port */
16536 spin_lock_irqsave(&pAC->TxPort[pNet->PortNr]
16537 [TX_PRIO_LOW].TxDesRingLock, Flags);
16538- SkGeStopPort(pAC, pAC->IoBase, pNet->PortNr,
16539- SK_STOP_ALL, SK_HARD_RST);
16540+ if (CHIP_ID_YUKON_2(pAC)) {
16541+ SkY2PortStop(pAC, pAC->IoBase, pNet->PortNr,
16542+ SK_STOP_ALL, SK_HARD_RST);
16543+ }
16544+ else {
16545+ SkGeStopPort(pAC, pAC->IoBase, pNet->PortNr,
16546+ SK_STOP_ALL, SK_HARD_RST);
16547+ }
16548 spin_unlock_irqrestore(&pAC->TxPort[pNet->PortNr]
16549 [TX_PRIO_LOW].TxDesRingLock, Flags);
16550 }
16551
16552 if (pAC->RlmtNets == 1) {
16553 /* clear all descriptor rings */
16554- for (i=0; i<pAC->GIni.GIMacsFound; i++) {
16555- ReceiveIrq(pAC, &pAC->RxPort[i], SK_TRUE);
16556- ClearRxRing(pAC, &pAC->RxPort[i]);
16557- ClearTxRing(pAC, &pAC->TxPort[i][TX_PRIO_LOW]);
16558+ for (CurrMac=0; CurrMac<pAC->GIni.GIMacsFound; CurrMac++) {
16559+ if (!CHIP_ID_YUKON_2(pAC)) {
16560+#ifdef CONFIG_SK98LIN_NAPI
16561+ WorkToDo = 1;
16562+ ReceiveIrq(pAC,&pAC->RxPort[CurrMac],
16563+ SK_TRUE,&WorkDone,WorkToDo);
16564+#else
16565+ ReceiveIrq(pAC,&pAC->RxPort[CurrMac],SK_TRUE);
16566+#endif
16567+ ClearRxRing(pAC, &pAC->RxPort[CurrMac]);
16568+ ClearTxRing(pAC, &pAC->TxPort[CurrMac][TX_PRIO_LOW]);
16569+ } else {
16570+ SkY2FreeRxBuffers(pAC, pAC->IoBase, CurrMac);
16571+ SkY2FreeTxBuffers(pAC, pAC->IoBase, CurrMac);
16572+ }
16573 }
16574 } else {
16575 /* clear port descriptor rings */
16576- ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE);
16577- ClearRxRing(pAC, &pAC->RxPort[pNet->PortNr]);
16578- ClearTxRing(pAC, &pAC->TxPort[pNet->PortNr][TX_PRIO_LOW]);
16579+ if (!CHIP_ID_YUKON_2(pAC)) {
16580+#ifdef CONFIG_SK98LIN_NAPI
16581+ WorkToDo = 1;
16582+ ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE, &WorkDone, WorkToDo);
16583+#else
16584+ ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE);
16585+#endif
16586+ ClearRxRing(pAC, &pAC->RxPort[pNet->PortNr]);
16587+ ClearTxRing(pAC, &pAC->TxPort[pNet->PortNr][TX_PRIO_LOW]);
16588+ }
16589+ else {
16590+ SkY2FreeRxBuffers(pAC, pAC->IoBase, pNet->PortNr);
16591+ SkY2FreeTxBuffers(pAC, pAC->IoBase, pNet->PortNr);
16592+ }
16593 }
16594
16595 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
16596@@ -1384,6 +2487,12 @@
16597 sizeof(SK_PNMI_STRUCT_DATA));
16598
16599 pAC->MaxPorts--;
16600+ module_put(THIS_MODULE);
16601+
16602+#ifdef Y2_RECOVERY
16603+ pNet->InRecover = SK_FALSE;
16604+#endif
16605+ spin_unlock_irqrestore(&pAC->InitLock, InitFlags);
16606
16607 return (0);
16608 } /* SkGeClose */
16609@@ -1410,7 +2519,7 @@
16610 SK_AC *pAC;
16611 int Rc; /* return code of XmitFrame */
16612
16613- pNet = netdev_priv(dev);
16614+ pNet = (DEV_NET*) dev->priv;
16615 pAC = pNet->pAC;
16616
16617 if ((!skb_shinfo(skb)->nr_frags) ||
16618@@ -1442,9 +2551,11 @@
16619 }
16620
16621 /* Transmitter out of resources? */
16622+#ifdef USE_TX_COMPLETE
16623 if (Rc <= 0) {
16624 netif_stop_queue(dev);
16625 }
16626+#endif
16627
16628 /* If not taken, give buffer ownership back to the
16629 * queueing layer.
16630@@ -1456,6 +2567,96 @@
16631 return (0);
16632 } /* SkGeXmit */
16633
16634+#ifdef CONFIG_SK98LIN_NAPI
16635+/*****************************************************************************
16636+ *
16637+ * SkGePoll - NAPI Rx polling callback for GEnesis and Yukon chipsets
16638+ *
16639+ * Description:
16640+ * Called by the Linux system in case NAPI polling is activated
16641+ *
16642+ * Returns:
16643+ * The number of work data still to be handled
16644+ */
16645+static int SkGePoll(struct net_device *dev, int *budget)
16646+{
16647+ SK_AC *pAC = ((DEV_NET*)(dev->priv))->pAC; /* pointer to adapter context */
16648+ int WorkToDo = min(*budget, dev->quota);
16649+ int WorkDone = 0;
16650+ unsigned long Flags;
16651+
16652+
16653+ if (pAC->dev[0] != pAC->dev[1]) {
16654+ spin_lock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock);
16655+ FreeTxDescriptors(pAC, &pAC->TxPort[1][TX_PRIO_LOW]);
16656+ spin_unlock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock);
16657+
16658+ ReceiveIrq(pAC, &pAC->RxPort[1], SK_TRUE, &WorkDone, WorkToDo);
16659+ CLEAR_AND_START_RX(1);
16660+ }
16661+ spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
16662+ FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]);
16663+ spin_unlock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
16664+
16665+ ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE, &WorkDone, WorkToDo);
16666+ CLEAR_AND_START_RX(0);
16667+
16668+ *budget -= WorkDone;
16669+ dev->quota -= WorkDone;
16670+
16671+ if(WorkDone < WorkToDo) {
16672+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
16673+ netif_rx_complete(dev);
16674+ pAC->GIni.GIValIrqMask |= (NAPI_DRV_IRQS);
16675+#ifndef USE_TX_COMPLETE
16676+ pAC->GIni.GIValIrqMask &= ~(TX_COMPL_IRQS);
16677+#endif
16678+ /* enable interrupts again */
16679+ SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
16680+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
16681+ }
16682+ return (WorkDone >= WorkToDo);
16683+} /* SkGePoll */
16684+#endif
16685+
16686+#ifdef SK_POLL_CONTROLLER
16687+/*****************************************************************************
16688+ *
16689+ * SkGeNetPoll - Polling "interrupt"
16690+ *
16691+ * Description:
16692+ * Polling 'interrupt' - used by things like netconsole and netdump
16693+ * to send skbs without having to re-enable interrupts.
16694+ * It's not called while the interrupt routine is executing.
16695+ */
16696+static void SkGeNetPoll(
16697+struct SK_NET_DEVICE *dev)
16698+{
16699+DEV_NET *pNet;
16700+SK_AC *pAC;
16701+
16702+ pNet = (DEV_NET*) dev->priv;
16703+ pAC = pNet->pAC;
16704+ pNet->NetConsoleMode = SK_TRUE;
16705+
16706+ /* Prevent any reconfiguration while handling
16707+ the 'interrupt' */
16708+ SK_OUT32(pAC->IoBase, B0_IMSK, 0);
16709+
16710+ if (!CHIP_ID_YUKON_2(pAC)) {
16711+ /* Handle the GENESIS Isr */
16712+ if (pAC->GIni.GIMacsFound == 2)
16713+ SkGeIsr(dev->irq, dev, NULL);
16714+ else
16715+ SkGeIsrOnePort(dev->irq, dev, NULL);
16716+ } else {
16717+ /* Handle the Yukon2 Isr */
16718+ SkY2Isr(dev->irq, dev, NULL);
16719+ }
16720+
16721+}
16722+#endif
16723+
16724
16725 /*****************************************************************************
16726 *
16727@@ -1480,7 +2681,7 @@
16728 * < 0 - on failure: other problems ( -> return failure to upper layers)
16729 */
16730 static int XmitFrame(
16731-SK_AC *pAC, /* pointer to adapter context */
16732+SK_AC *pAC, /* pointer to adapter context */
16733 TX_PORT *pTxPort, /* pointer to struct of port to send to */
16734 struct sk_buff *pMessage) /* pointer to send-message */
16735 {
16736@@ -1488,17 +2689,22 @@
16737 TXD *pOldTxd;
16738 unsigned long Flags;
16739 SK_U64 PhysAddr;
16740+ int Protocol;
16741+ int IpHeaderLength;
16742 int BytesSend = pMessage->len;
16743
16744 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, ("X"));
16745
16746 spin_lock_irqsave(&pTxPort->TxDesRingLock, Flags);
16747 #ifndef USE_TX_COMPLETE
16748- FreeTxDescriptors(pAC, pTxPort);
16749+ if ((pTxPort->TxdRingPrevFree - pTxPort->TxdRingFree) > 6) {
16750+ FreeTxDescriptors(pAC, pTxPort);
16751+ pTxPort->TxdRingPrevFree = pTxPort->TxdRingFree;
16752+ }
16753 #endif
16754 if (pTxPort->TxdRingFree == 0) {
16755 /*
16756- ** no enough free descriptors in ring at the moment.
16757+ ** not enough free descriptors in ring at the moment.
16758 ** Maybe free'ing some old one help?
16759 */
16760 FreeTxDescriptors(pAC, pTxPort);
16761@@ -1560,10 +2766,8 @@
16762 pTxd->pMBuf = pMessage;
16763
16764 if (pMessage->ip_summed == CHECKSUM_HW) {
16765- u16 hdrlen = pMessage->h.raw - pMessage->data;
16766- u16 offset = hdrlen + pMessage->csum;
16767-
16768- if ((pMessage->h.ipiph->protocol == IPPROTO_UDP ) &&
16769+ Protocol = ((SK_U8)pMessage->data[C_OFFSET_IPPROTO] & 0xff);
16770+ if ((Protocol == C_PROTO_ID_UDP) &&
16771 (pAC->GIni.GIChipRev == 0) &&
16772 (pAC->GIni.GIChipId == CHIP_ID_YUKON)) {
16773 pTxd->TBControl = BMU_TCP_CHECK;
16774@@ -1571,9 +2775,14 @@
16775 pTxd->TBControl = BMU_UDP_CHECK;
16776 }
16777
16778- pTxd->TcpSumOfs = 0;
16779- pTxd->TcpSumSt = hdrlen;
16780- pTxd->TcpSumWr = offset;
16781+ IpHeaderLength = (SK_U8)pMessage->data[C_OFFSET_IPHEADER];
16782+ IpHeaderLength = (IpHeaderLength & 0xf) * 4;
16783+ pTxd->TcpSumOfs = 0; /* PH-Checksum already calculated */
16784+ pTxd->TcpSumSt = C_LEN_ETHERMAC_HEADER + IpHeaderLength +
16785+ (Protocol == C_PROTO_ID_UDP ?
16786+ C_OFFSET_UDPHEADER_UDPCS :
16787+ C_OFFSET_TCPHEADER_TCPCS);
16788+ pTxd->TcpSumWr = C_LEN_ETHERMAC_HEADER + IpHeaderLength;
16789
16790 pTxd->TBControl |= BMU_OWN | BMU_STF |
16791 BMU_SW | BMU_EOF |
16792@@ -1581,7 +2790,7 @@
16793 BMU_IRQ_EOF |
16794 #endif
16795 pMessage->len;
16796- } else {
16797+ } else {
16798 pTxd->TBControl = BMU_OWN | BMU_STF | BMU_CHECK |
16799 BMU_SW | BMU_EOF |
16800 #ifdef USE_TX_COMPLETE
16801@@ -1636,10 +2845,11 @@
16802 TXD *pTxdLst;
16803 int CurrFrag;
16804 int BytesSend;
16805+ int IpHeaderLength;
16806+ int Protocol;
16807 skb_frag_t *sk_frag;
16808 SK_U64 PhysAddr;
16809 unsigned long Flags;
16810- SK_U32 Control;
16811
16812 spin_lock_irqsave(&pTxPort->TxDesRingLock, Flags);
16813 #ifndef USE_TX_COMPLETE
16814@@ -1662,6 +2872,7 @@
16815 pTxdFst = pTxd;
16816 pTxdLst = pTxd;
16817 BytesSend = 0;
16818+ Protocol = 0;
16819
16820 /*
16821 ** Map the first fragment (header) into the DMA-space
16822@@ -1679,31 +2890,32 @@
16823 ** Does the HW need to evaluate checksum for TCP or UDP packets?
16824 */
16825 if (pMessage->ip_summed == CHECKSUM_HW) {
16826- u16 hdrlen = pMessage->h.raw - pMessage->data;
16827- u16 offset = hdrlen + pMessage->csum;
16828-
16829- Control = BMU_STFWD;
16830-
16831+ pTxd->TBControl = BMU_STF | BMU_STFWD | skb_headlen(pMessage);
16832 /*
16833 ** We have to use the opcode for tcp here, because the
16834 ** opcode for udp is not working in the hardware yet
16835 ** (Revision 2.0)
16836 */
16837- if ((pMessage->h.ipiph->protocol == IPPROTO_UDP ) &&
16838+ Protocol = ((SK_U8)pMessage->data[C_OFFSET_IPPROTO] & 0xff);
16839+ if ((Protocol == C_PROTO_ID_UDP) &&
16840 (pAC->GIni.GIChipRev == 0) &&
16841 (pAC->GIni.GIChipId == CHIP_ID_YUKON)) {
16842- Control |= BMU_TCP_CHECK;
16843+ pTxd->TBControl |= BMU_TCP_CHECK;
16844 } else {
16845- Control |= BMU_UDP_CHECK;
16846+ pTxd->TBControl |= BMU_UDP_CHECK;
16847 }
16848
16849- pTxd->TcpSumOfs = 0;
16850- pTxd->TcpSumSt = hdrlen;
16851- pTxd->TcpSumWr = offset;
16852- } else
16853- Control = BMU_CHECK | BMU_SW;
16854-
16855- pTxd->TBControl = BMU_STF | Control | skb_headlen(pMessage);
16856+ IpHeaderLength = ((SK_U8)pMessage->data[C_OFFSET_IPHEADER] & 0xf)*4;
16857+ pTxd->TcpSumOfs = 0; /* PH-Checksum already claculated */
16858+ pTxd->TcpSumSt = C_LEN_ETHERMAC_HEADER + IpHeaderLength +
16859+ (Protocol == C_PROTO_ID_UDP ?
16860+ C_OFFSET_UDPHEADER_UDPCS :
16861+ C_OFFSET_TCPHEADER_TCPCS);
16862+ pTxd->TcpSumWr = C_LEN_ETHERMAC_HEADER + IpHeaderLength;
16863+ } else {
16864+ pTxd->TBControl = BMU_CHECK | BMU_SW | BMU_STF |
16865+ skb_headlen(pMessage);
16866+ }
16867
16868 pTxd = pTxd->pNextTxd;
16869 pTxPort->TxdRingFree--;
16870@@ -1727,18 +2939,40 @@
16871 pTxd->VDataHigh = (SK_U32) (PhysAddr >> 32);
16872 pTxd->pMBuf = pMessage;
16873
16874- pTxd->TBControl = Control | BMU_OWN | sk_frag->size;
16875+ /*
16876+ ** Does the HW need to evaluate checksum for TCP or UDP packets?
16877+ */
16878+ if (pMessage->ip_summed == CHECKSUM_HW) {
16879+ pTxd->TBControl = BMU_OWN | BMU_SW | BMU_STFWD;
16880+ /*
16881+ ** We have to use the opcode for tcp here because the
16882+ ** opcode for udp is not working in the hardware yet
16883+ ** (revision 2.0)
16884+ */
16885+ if ((Protocol == C_PROTO_ID_UDP) &&
16886+ (pAC->GIni.GIChipRev == 0) &&
16887+ (pAC->GIni.GIChipId == CHIP_ID_YUKON)) {
16888+ pTxd->TBControl |= BMU_TCP_CHECK;
16889+ } else {
16890+ pTxd->TBControl |= BMU_UDP_CHECK;
16891+ }
16892+ } else {
16893+ pTxd->TBControl = BMU_CHECK | BMU_SW | BMU_OWN;
16894+ }
16895
16896 /*
16897 ** Do we have the last fragment?
16898 */
16899 if( (CurrFrag+1) == skb_shinfo(pMessage)->nr_frags ) {
16900 #ifdef USE_TX_COMPLETE
16901- pTxd->TBControl |= BMU_EOF | BMU_IRQ_EOF;
16902+ pTxd->TBControl |= BMU_EOF | BMU_IRQ_EOF | sk_frag->size;
16903 #else
16904- pTxd->TBControl |= BMU_EOF;
16905+ pTxd->TBControl |= BMU_EOF | sk_frag->size;
16906 #endif
16907 pTxdFst->TBControl |= BMU_OWN | BMU_SW;
16908+
16909+ } else {
16910+ pTxd->TBControl |= sk_frag->size;
16911 }
16912 pTxdLst = pTxd;
16913 pTxd = pTxd->pNextTxd;
16914@@ -1892,7 +3126,7 @@
16915 SK_U16 Length; /* data fragment length */
16916 SK_U64 PhysAddr; /* physical address of a rx buffer */
16917
16918- pMsgBlock = alloc_skb(pAC->RxBufSize, GFP_ATOMIC);
16919+ pMsgBlock = alloc_skb(pRxPort->RxBufSize, GFP_ATOMIC);
16920 if (pMsgBlock == NULL) {
16921 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
16922 SK_DBGCAT_DRV_ENTRY,
16923@@ -1906,12 +3140,12 @@
16924 pRxd = pRxPort->pRxdRingTail;
16925 pRxPort->pRxdRingTail = pRxd->pNextRxd;
16926 pRxPort->RxdRingFree--;
16927- Length = pAC->RxBufSize;
16928+ Length = pRxPort->RxBufSize;
16929 PhysAddr = (SK_U64) pci_map_page(pAC->PciDev,
16930 virt_to_page(pMsgBlock->data),
16931 ((unsigned long) pMsgBlock->data &
16932 ~PAGE_MASK),
16933- pAC->RxBufSize - 2,
16934+ pRxPort->RxBufSize - 2,
16935 PCI_DMA_FROMDEVICE);
16936
16937 pRxd->VDataLow = (SK_U32) (PhysAddr & 0xffffffff);
16938@@ -1951,7 +3185,7 @@
16939 pRxd = pRxPort->pRxdRingTail;
16940 pRxPort->pRxdRingTail = pRxd->pNextRxd;
16941 pRxPort->RxdRingFree--;
16942- Length = pAC->RxBufSize;
16943+ Length = pRxPort->RxBufSize;
16944
16945 pRxd->VDataLow = PhysLow;
16946 pRxd->VDataHigh = PhysHigh;
16947@@ -1976,28 +3210,40 @@
16948 * Returns: N/A
16949 */
16950 static void ReceiveIrq(
16951- SK_AC *pAC, /* pointer to adapter context */
16952- RX_PORT *pRxPort, /* pointer to receive port struct */
16953- SK_BOOL SlowPathLock) /* indicates if SlowPathLock is needed */
16954-{
16955-RXD *pRxd; /* pointer to receive descriptors */
16956-SK_U32 Control; /* control field of descriptor */
16957-struct sk_buff *pMsg; /* pointer to message holding frame */
16958-struct sk_buff *pNewMsg; /* pointer to a new message for copying frame */
16959-int FrameLength; /* total length of received frame */
16960-SK_MBUF *pRlmtMbuf; /* ptr to a buffer for giving a frame to rlmt */
16961-SK_EVPARA EvPara; /* an event parameter union */
16962-unsigned long Flags; /* for spin lock */
16963-int PortIndex = pRxPort->PortIndex;
16964-unsigned int Offset;
16965-unsigned int NumBytes;
16966-unsigned int ForRlmt;
16967-SK_BOOL IsBc;
16968-SK_BOOL IsMc;
16969-SK_BOOL IsBadFrame; /* Bad frame */
16970-
16971-SK_U32 FrameStat;
16972-SK_U64 PhysAddr;
16973+#ifdef CONFIG_SK98LIN_NAPI
16974+SK_AC *pAC, /* pointer to adapter context */
16975+RX_PORT *pRxPort, /* pointer to receive port struct */
16976+SK_BOOL SlowPathLock, /* indicates if SlowPathLock is needed */
16977+int *WorkDone,
16978+int WorkToDo)
16979+#else
16980+SK_AC *pAC, /* pointer to adapter context */
16981+RX_PORT *pRxPort, /* pointer to receive port struct */
16982+SK_BOOL SlowPathLock) /* indicates if SlowPathLock is needed */
16983+#endif
16984+{
16985+ RXD *pRxd; /* pointer to receive descriptors */
16986+ struct sk_buff *pMsg; /* pointer to message holding frame */
16987+ struct sk_buff *pNewMsg; /* pointer to new message for frame copy */
16988+ SK_MBUF *pRlmtMbuf; /* ptr to buffer for giving frame to RLMT */
16989+ SK_EVPARA EvPara; /* an event parameter union */
16990+ SK_U32 Control; /* control field of descriptor */
16991+ unsigned long Flags; /* for spin lock handling */
16992+ int PortIndex = pRxPort->PortIndex;
16993+ int FrameLength; /* total length of received frame */
16994+ int IpFrameLength; /* IP length of the received frame */
16995+ unsigned int Offset;
16996+ unsigned int NumBytes;
16997+ unsigned int RlmtNotifier;
16998+ SK_BOOL IsBc; /* we received a broadcast packet */
16999+ SK_BOOL IsMc; /* we received a multicast packet */
17000+ SK_BOOL IsBadFrame; /* the frame received is bad! */
17001+ SK_U32 FrameStat;
17002+ unsigned short Csum1;
17003+ unsigned short Csum2;
17004+ unsigned short Type;
17005+ int Result;
17006+ SK_U64 PhysAddr;
17007
17008 rx_start:
17009 /* do forever; exit if BMU_OWN found */
17010@@ -2019,6 +3265,13 @@
17011
17012 Control = pRxd->RBControl;
17013
17014+#ifdef CONFIG_SK98LIN_NAPI
17015+ if (*WorkDone >= WorkToDo) {
17016+ break;
17017+ }
17018+ (*WorkDone)++;
17019+#endif
17020+
17021 /* check if this descriptor is ready */
17022 if ((Control & BMU_OWN) != 0) {
17023 /* this descriptor is not yet ready */
17024@@ -2027,11 +3280,10 @@
17025 FillRxRing(pAC, pRxPort);
17026 return;
17027 }
17028- pAC->DynIrqModInfo.NbrProcessedDescr++;
17029
17030 /* get length of frame and check it */
17031 FrameLength = Control & BMU_BBC;
17032- if (FrameLength > pAC->RxBufSize) {
17033+ if (FrameLength > pRxPort->RxBufSize) {
17034 goto rx_failed;
17035 }
17036
17037@@ -2046,8 +3298,8 @@
17038 FrameStat = pRxd->FrameStat;
17039
17040 /* check for frame length mismatch */
17041-#define XMR_FS_LEN_SHIFT 18
17042-#define GMR_FS_LEN_SHIFT 16
17043+#define XMR_FS_LEN_SHIFT 18
17044+#define GMR_FS_LEN_SHIFT 16
17045 if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
17046 if (FrameLength != (SK_U32) (FrameStat >> XMR_FS_LEN_SHIFT)) {
17047 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
17048@@ -2057,8 +3309,7 @@
17049 (SK_U32) (FrameStat >> XMR_FS_LEN_SHIFT)));
17050 goto rx_failed;
17051 }
17052- }
17053- else {
17054+ } else {
17055 if (FrameLength != (SK_U32) (FrameStat >> GMR_FS_LEN_SHIFT)) {
17056 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
17057 SK_DBGCAT_DRV_RX_PROGRESS,
17058@@ -2091,9 +3342,6 @@
17059 /* DumpMsg(pMsg, "Rx"); */
17060
17061 if ((Control & BMU_STAT_VAL) != BMU_STAT_VAL || (IsBadFrame)) {
17062-#if 0
17063- (FrameStat & (XMR_FS_ANY_ERR | XMR_FS_2L_VLAN)) != 0) {
17064-#endif
17065 /* there is a receive error in this frame */
17066 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
17067 SK_DBGCAT_DRV_RX_PROGRESS,
17068@@ -2101,6 +3349,20 @@
17069 "Control: %x\nRxStat: %x\n",
17070 Control, FrameStat));
17071
17072+ PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32;
17073+ PhysAddr |= (SK_U64) pRxd->VDataLow;
17074+
17075+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5)
17076+ pci_dma_sync_single(pAC->PciDev,
17077+ (dma_addr_t) PhysAddr,
17078+ FrameLength,
17079+ PCI_DMA_FROMDEVICE);
17080+#else
17081+ pci_dma_sync_single_for_cpu(pAC->PciDev,
17082+ (dma_addr_t) PhysAddr,
17083+ FrameLength,
17084+ PCI_DMA_FROMDEVICE);
17085+#endif
17086 ReQueueRxBuffer(pAC, pRxPort, pMsg,
17087 pRxd->VDataHigh, pRxd->VDataLow);
17088
17089@@ -2118,98 +3380,109 @@
17090 /* use new skb and copy data */
17091 skb_reserve(pNewMsg, 2);
17092 skb_put(pNewMsg, FrameLength);
17093- PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32;
17094- PhysAddr |= (SK_U64) pRxd->VDataLow;
17095-
17096- pci_dma_sync_single_for_cpu(pAC->PciDev,
17097- (dma_addr_t) PhysAddr,
17098- FrameLength,
17099- PCI_DMA_FROMDEVICE);
17100- memcpy(pNewMsg->data, pMsg, FrameLength);
17101-
17102+ PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32;
17103+ PhysAddr |= (SK_U64) pRxd->VDataLow;
17104+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5)
17105+ pci_dma_sync_single(pAC->PciDev,
17106+ (dma_addr_t) PhysAddr,
17107+ FrameLength,
17108+ PCI_DMA_FROMDEVICE);
17109+#else
17110 pci_dma_sync_single_for_device(pAC->PciDev,
17111- (dma_addr_t) PhysAddr,
17112- FrameLength,
17113- PCI_DMA_FROMDEVICE);
17114+ (dma_addr_t) PhysAddr,
17115+ FrameLength,
17116+ PCI_DMA_FROMDEVICE);
17117+#endif
17118+
17119+ eth_copy_and_sum(pNewMsg, pMsg->data,
17120+ FrameLength, 0);
17121 ReQueueRxBuffer(pAC, pRxPort, pMsg,
17122 pRxd->VDataHigh, pRxd->VDataLow);
17123
17124 pMsg = pNewMsg;
17125
17126- }
17127- else {
17128+ } else {
17129 /*
17130 * if large frame, or SKB allocation failed, pass
17131 * the SKB directly to the networking
17132 */
17133-
17134 PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32;
17135 PhysAddr |= (SK_U64) pRxd->VDataLow;
17136
17137 /* release the DMA mapping */
17138 pci_unmap_single(pAC->PciDev,
17139 PhysAddr,
17140- pAC->RxBufSize - 2,
17141+ pRxPort->RxBufSize - 2,
17142 PCI_DMA_FROMDEVICE);
17143+ skb_put(pMsg, FrameLength); /* set message len */
17144+ pMsg->ip_summed = CHECKSUM_NONE; /* initial default */
17145
17146- /* set length in message */
17147- skb_put(pMsg, FrameLength);
17148+ if (pRxPort->UseRxCsum) {
17149+ Type = ntohs(*((short*)&pMsg->data[12]));
17150+ if (Type == 0x800) {
17151+ IpFrameLength = (int) ntohs((unsigned short)
17152+ ((unsigned short *) pMsg->data)[8]);
17153+ if ((FrameLength - IpFrameLength) == 0xe) {
17154+ Csum1=le16_to_cpu(pRxd->TcpSums & 0xffff);
17155+ Csum2=le16_to_cpu((pRxd->TcpSums >> 16) & 0xffff);
17156+ if ((((Csum1 & 0xfffe) && (Csum2 & 0xfffe)) &&
17157+ (pAC->GIni.GIChipId == CHIP_ID_GENESIS)) ||
17158+ (pAC->ChipsetType)) {
17159+ Result = SkCsGetReceiveInfo(pAC, &pMsg->data[14],
17160+ Csum1, Csum2, PortIndex);
17161+ if ((Result == SKCS_STATUS_IP_FRAGMENT) ||
17162+ (Result == SKCS_STATUS_IP_CSUM_OK) ||
17163+ (Result == SKCS_STATUS_TCP_CSUM_OK) ||
17164+ (Result == SKCS_STATUS_UDP_CSUM_OK)) {
17165+ pMsg->ip_summed = CHECKSUM_UNNECESSARY;
17166+ } else if ((Result == SKCS_STATUS_TCP_CSUM_ERROR) ||
17167+ (Result == SKCS_STATUS_UDP_CSUM_ERROR) ||
17168+ (Result == SKCS_STATUS_IP_CSUM_ERROR_UDP) ||
17169+ (Result == SKCS_STATUS_IP_CSUM_ERROR_TCP) ||
17170+ (Result == SKCS_STATUS_IP_CSUM_ERROR)) {
17171+ /* HW Checksum error */
17172+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
17173+ SK_DBGCAT_DRV_RX_PROGRESS,
17174+ ("skge: CRC error. Frame dropped!\n"));
17175+ goto rx_failed;
17176+ } else {
17177+ pMsg->ip_summed = CHECKSUM_NONE;
17178+ }
17179+ }/* checksumControl calculation valid */
17180+ } /* Frame length check */
17181+ } /* IP frame */
17182+ } /* pRxPort->UseRxCsum */
17183 } /* frame > SK_COPY_TRESHOLD */
17184-
17185-#ifdef USE_SK_RX_CHECKSUM
17186- pMsg->csum = pRxd->TcpSums & 0xffff;
17187- pMsg->ip_summed = CHECKSUM_HW;
17188-#else
17189- pMsg->ip_summed = CHECKSUM_NONE;
17190-#endif
17191-
17192+
17193 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("V"));
17194- ForRlmt = SK_RLMT_RX_PROTOCOL;
17195-#if 0
17196- IsBc = (FrameStat & XMR_FS_BC)==XMR_FS_BC;
17197-#endif
17198+ RlmtNotifier = SK_RLMT_RX_PROTOCOL;
17199 SK_RLMT_PRE_LOOKAHEAD(pAC, PortIndex, FrameLength,
17200- IsBc, &Offset, &NumBytes);
17201+ IsBc, &Offset, &NumBytes);
17202 if (NumBytes != 0) {
17203-#if 0
17204- IsMc = (FrameStat & XMR_FS_MC)==XMR_FS_MC;
17205-#endif
17206- SK_RLMT_LOOKAHEAD(pAC, PortIndex,
17207- &pMsg->data[Offset],
17208- IsBc, IsMc, &ForRlmt);
17209+ SK_RLMT_LOOKAHEAD(pAC,PortIndex,&pMsg->data[Offset],
17210+ IsBc,IsMc,&RlmtNotifier);
17211 }
17212- if (ForRlmt == SK_RLMT_RX_PROTOCOL) {
17213- SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("W"));
17214+ if (RlmtNotifier == SK_RLMT_RX_PROTOCOL) {
17215+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("W"));
17216 /* send up only frames from active port */
17217- if ((PortIndex == pAC->ActivePort) ||
17218- (pAC->RlmtNets == 2)) {
17219- /* frame for upper layer */
17220+ if ((PortIndex == pAC->ActivePort)||(pAC->RlmtNets == 2)) {
17221 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("U"));
17222 #ifdef xDEBUG
17223 DumpMsg(pMsg, "Rx");
17224 #endif
17225- SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC,
17226- FrameLength, pRxPort->PortIndex);
17227-
17228- pMsg->dev = pAC->dev[pRxPort->PortIndex];
17229- pMsg->protocol = eth_type_trans(pMsg,
17230- pAC->dev[pRxPort->PortIndex]);
17231- netif_rx(pMsg);
17232- pAC->dev[pRxPort->PortIndex]->last_rx = jiffies;
17233- }
17234- else {
17235- /* drop frame */
17236+ SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC,FrameLength,PortIndex);
17237+ pMsg->dev = pAC->dev[PortIndex];
17238+ pMsg->protocol = eth_type_trans(pMsg,pAC->dev[PortIndex]);
17239+ netif_rx(pMsg); /* frame for upper layer */
17240+ pAC->dev[PortIndex]->last_rx = jiffies;
17241+ } else {
17242 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
17243- SK_DBGCAT_DRV_RX_PROGRESS,
17244- ("D"));
17245- DEV_KFREE_SKB(pMsg);
17246+ SK_DBGCAT_DRV_RX_PROGRESS,("D"));
17247+ DEV_KFREE_SKB(pMsg); /* drop frame */
17248 }
17249-
17250- } /* if not for rlmt */
17251- else {
17252- /* packet for rlmt */
17253+ } else { /* packet for RLMT stack */
17254 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
17255- SK_DBGCAT_DRV_RX_PROGRESS, ("R"));
17256+ SK_DBGCAT_DRV_RX_PROGRESS,("R"));
17257 pRlmtMbuf = SkDrvAllocRlmtMbuf(pAC,
17258 pAC->IoBase, FrameLength);
17259 if (pRlmtMbuf != NULL) {
17260@@ -2237,32 +3510,22 @@
17261 }
17262
17263 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
17264- SK_DBGCAT_DRV_RX_PROGRESS,
17265- ("Q"));
17266+ SK_DBGCAT_DRV_RX_PROGRESS,("Q"));
17267 }
17268- if ((pAC->dev[pRxPort->PortIndex]->flags &
17269- (IFF_PROMISC | IFF_ALLMULTI)) != 0 ||
17270- (ForRlmt & SK_RLMT_RX_PROTOCOL) ==
17271- SK_RLMT_RX_PROTOCOL) {
17272- pMsg->dev = pAC->dev[pRxPort->PortIndex];
17273- pMsg->protocol = eth_type_trans(pMsg,
17274- pAC->dev[pRxPort->PortIndex]);
17275+ if ((pAC->dev[PortIndex]->flags & (IFF_PROMISC | IFF_ALLMULTI)) ||
17276+ (RlmtNotifier & SK_RLMT_RX_PROTOCOL)) {
17277+ pMsg->dev = pAC->dev[PortIndex];
17278+ pMsg->protocol = eth_type_trans(pMsg,pAC->dev[PortIndex]);
17279 netif_rx(pMsg);
17280- pAC->dev[pRxPort->PortIndex]->last_rx = jiffies;
17281- }
17282- else {
17283+ pAC->dev[PortIndex]->last_rx = jiffies;
17284+ } else {
17285 DEV_KFREE_SKB(pMsg);
17286 }
17287-
17288- } /* if packet for rlmt */
17289+ } /* if packet for RLMT stack */
17290 } /* for ... scanning the RXD ring */
17291
17292 /* RXD ring is empty -> fill and restart */
17293 FillRxRing(pAC, pRxPort);
17294- /* do not start if called from Close */
17295- if (pAC->BoardLevel > SK_INIT_DATA) {
17296- ClearAndStartRx(pAC, PortIndex);
17297- }
17298 return;
17299
17300 rx_failed:
17301@@ -2276,7 +3539,7 @@
17302 PhysAddr |= (SK_U64) pRxd->VDataLow;
17303 pci_unmap_page(pAC->PciDev,
17304 PhysAddr,
17305- pAC->RxBufSize - 2,
17306+ pRxPort->RxBufSize - 2,
17307 PCI_DMA_FROMDEVICE);
17308 DEV_KFREE_SKB_IRQ(pRxd->pMBuf);
17309 pRxd->pMBuf = NULL;
17310@@ -2286,49 +3549,6 @@
17311
17312 } /* ReceiveIrq */
17313
17314-
17315-/*****************************************************************************
17316- *
17317- * ClearAndStartRx - give a start receive command to BMU, clear IRQ
17318- *
17319- * Description:
17320- * This function sends a start command and a clear interrupt
17321- * command for one receive queue to the BMU.
17322- *
17323- * Returns: N/A
17324- * none
17325- */
17326-static void ClearAndStartRx(
17327-SK_AC *pAC, /* pointer to the adapter context */
17328-int PortIndex) /* index of the receive port (XMAC) */
17329-{
17330- SK_OUT8(pAC->IoBase,
17331- RxQueueAddr[PortIndex]+Q_CSR,
17332- CSR_START | CSR_IRQ_CL_F);
17333-} /* ClearAndStartRx */
17334-
17335-
17336-/*****************************************************************************
17337- *
17338- * ClearTxIrq - give a clear transmit IRQ command to BMU
17339- *
17340- * Description:
17341- * This function sends a clear tx IRQ command for one
17342- * transmit queue to the BMU.
17343- *
17344- * Returns: N/A
17345- */
17346-static void ClearTxIrq(
17347-SK_AC *pAC, /* pointer to the adapter context */
17348-int PortIndex, /* index of the transmit port (XMAC) */
17349-int Prio) /* priority or normal queue */
17350-{
17351- SK_OUT8(pAC->IoBase,
17352- TxQueueAddr[PortIndex][Prio]+Q_CSR,
17353- CSR_IRQ_CL_F);
17354-} /* ClearTxIrq */
17355-
17356-
17357 /*****************************************************************************
17358 *
17359 * ClearRxRing - remove all buffers from the receive ring
17360@@ -2359,7 +3579,7 @@
17361 PhysAddr |= (SK_U64) pRxd->VDataLow;
17362 pci_unmap_page(pAC->PciDev,
17363 PhysAddr,
17364- pAC->RxBufSize - 2,
17365+ pRxPort->RxBufSize - 2,
17366 PCI_DMA_FROMDEVICE);
17367 DEV_KFREE_SKB(pRxd->pMBuf);
17368 pRxd->pMBuf = NULL;
17369@@ -2417,31 +3637,32 @@
17370 static int SkGeSetMacAddr(struct SK_NET_DEVICE *dev, void *p)
17371 {
17372
17373-DEV_NET *pNet = netdev_priv(dev);
17374+DEV_NET *pNet = (DEV_NET*) dev->priv;
17375 SK_AC *pAC = pNet->pAC;
17376+int Ret;
17377
17378 struct sockaddr *addr = p;
17379 unsigned long Flags;
17380
17381 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
17382 ("SkGeSetMacAddr starts now...\n"));
17383- if(netif_running(dev))
17384- return -EBUSY;
17385
17386 memcpy(dev->dev_addr, addr->sa_data,dev->addr_len);
17387
17388 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
17389
17390 if (pAC->RlmtNets == 2)
17391- SkAddrOverride(pAC, pAC->IoBase, pNet->NetNr,
17392+ Ret = SkAddrOverride(pAC, pAC->IoBase, pNet->NetNr,
17393 (SK_MAC_ADDR*)dev->dev_addr, SK_ADDR_VIRTUAL_ADDRESS);
17394 else
17395- SkAddrOverride(pAC, pAC->IoBase, pAC->ActivePort,
17396+ Ret = SkAddrOverride(pAC, pAC->IoBase, pAC->ActivePort,
17397 (SK_MAC_ADDR*)dev->dev_addr, SK_ADDR_VIRTUAL_ADDRESS);
17398-
17399-
17400
17401 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
17402+
17403+ if (Ret != SK_ADDR_OVERRIDE_SUCCESS)
17404+ return -EBUSY;
17405+
17406 return 0;
17407 } /* SkGeSetMacAddr */
17408
17409@@ -2474,7 +3695,7 @@
17410 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
17411 ("SkGeSetRxMode starts now... "));
17412
17413- pNet = netdev_priv(dev);
17414+ pNet = (DEV_NET*) dev->priv;
17415 pAC = pNet->pAC;
17416 if (pAC->RlmtNets == 1)
17417 PortIdx = pAC->ActivePort;
17418@@ -2523,6 +3744,45 @@
17419
17420 /*****************************************************************************
17421 *
17422+ * SkSetMtuBufferSize - set the MTU buffer to another value
17423+ *
17424+ * Description:
17425+ * This function sets the new buffers and is called whenever the MTU
17426+ * size is changed
17427+ *
17428+ * Returns:
17429+ * N/A
17430+ */
17431+
17432+static void SkSetMtuBufferSize(
17433+SK_AC *pAC, /* pointer to adapter context */
17434+int PortNr, /* Port number */
17435+int Mtu) /* pointer to tx prt struct */
17436+{
17437+ pAC->RxPort[PortNr].RxBufSize = Mtu + 32;
17438+
17439+ /* RxBufSize must be a multiple of 8 */
17440+ while (pAC->RxPort[PortNr].RxBufSize % 8) {
17441+ pAC->RxPort[PortNr].RxBufSize =
17442+ pAC->RxPort[PortNr].RxBufSize + 1;
17443+ }
17444+
17445+ if (Mtu > 1500) {
17446+ pAC->GIni.GP[PortNr].PPortUsage = SK_JUMBO_LINK;
17447+ } else {
17448+ if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
17449+ pAC->GIni.GP[PortNr].PPortUsage = SK_MUL_LINK;
17450+ } else {
17451+ pAC->GIni.GP[PortNr].PPortUsage = SK_RED_LINK;
17452+ }
17453+ }
17454+
17455+ return;
17456+}
17457+
17458+
17459+/*****************************************************************************
17460+ *
17461 * SkGeChangeMtu - set the MTU to another value
17462 *
17463 * Description:
17464@@ -2536,28 +3796,32 @@
17465 */
17466 static int SkGeChangeMtu(struct SK_NET_DEVICE *dev, int NewMtu)
17467 {
17468-DEV_NET *pNet;
17469-struct net_device *pOtherDev;
17470-SK_AC *pAC;
17471-unsigned long Flags;
17472-int i;
17473-SK_EVPARA EvPara;
17474+DEV_NET *pNet;
17475+SK_AC *pAC;
17476+unsigned long Flags;
17477+#ifdef CONFIG_SK98LIN_NAPI
17478+int WorkToDo = 1; // min(*budget, dev->quota);
17479+int WorkDone = 0;
17480+#endif
17481
17482 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
17483 ("SkGeChangeMtu starts now...\n"));
17484
17485- pNet = netdev_priv(dev);
17486+ pNet = (DEV_NET*) dev->priv;
17487 pAC = pNet->pAC;
17488
17489+ /* MTU size outside the spec */
17490 if ((NewMtu < 68) || (NewMtu > SK_JUMBO_MTU)) {
17491 return -EINVAL;
17492 }
17493
17494- if(pAC->BoardLevel != SK_INIT_RUN) {
17495+ /* MTU > 1500 on yukon ulra not allowed */
17496+ if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U)
17497+ && (NewMtu > 1500)){
17498 return -EINVAL;
17499 }
17500
17501-#ifdef SK_DIAG_SUPPORT
17502+ /* Diag access active */
17503 if (pAC->DiagModeActive == DIAG_ACTIVE) {
17504 if (pAC->DiagFlowCtrl == SK_FALSE) {
17505 return -1; /* still in use, deny any actions of MTU */
17506@@ -2565,201 +3829,74 @@
17507 pAC->DiagFlowCtrl = SK_FALSE;
17508 }
17509 }
17510-#endif
17511
17512- pOtherDev = pAC->dev[1 - pNet->NetNr];
17513-
17514- if ( netif_running(pOtherDev) && (pOtherDev->mtu > 1500)
17515- && (NewMtu <= 1500))
17516- return 0;
17517-
17518- pAC->RxBufSize = NewMtu + 32;
17519 dev->mtu = NewMtu;
17520+ SkSetMtuBufferSize(pAC, pNet->PortNr, NewMtu);
17521
17522- SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
17523- ("New MTU: %d\n", NewMtu));
17524+ if(!netif_running(dev)) {
17525+ /* Preset MTU size if device not ready/running */
17526+ return 0;
17527+ }
17528
17529- /*
17530- ** Prevent any reconfiguration while changing the MTU
17531- ** by disabling any interrupts
17532- */
17533+ /* Prevent any reconfiguration while changing the MTU
17534+ by disabling any interrupts */
17535 SK_OUT32(pAC->IoBase, B0_IMSK, 0);
17536 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
17537
17538- /*
17539- ** Notify RLMT that any ports are to be stopped
17540- */
17541- EvPara.Para32[0] = 0;
17542- EvPara.Para32[1] = -1;
17543- if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
17544- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
17545- EvPara.Para32[0] = 1;
17546- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
17547- } else {
17548- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
17549- }
17550-
17551- /*
17552- ** After calling the SkEventDispatcher(), RLMT is aware about
17553- ** the stopped ports -> configuration can take place!
17554- */
17555- SkEventDispatcher(pAC, pAC->IoBase);
17556-
17557- for (i=0; i<pAC->GIni.GIMacsFound; i++) {
17558- spin_lock(&pAC->TxPort[i][TX_PRIO_LOW].TxDesRingLock);
17559- netif_stop_queue(pAC->dev[i]);
17560+ /* Notify RLMT that the port has to be stopped */
17561+ netif_stop_queue(dev);
17562+ SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP,
17563+ pNet->PortNr, -1, SK_TRUE);
17564+ spin_lock(&pAC->TxPort[pNet->PortNr][TX_PRIO_LOW].TxDesRingLock);
17565
17566- }
17567
17568- /*
17569- ** Depending on the desired MTU size change, a different number of
17570- ** RX buffers need to be allocated
17571- */
17572- if (NewMtu > 1500) {
17573- /*
17574- ** Use less rx buffers
17575- */
17576- for (i=0; i<pAC->GIni.GIMacsFound; i++) {
17577- if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
17578- pAC->RxPort[i].RxFillLimit = pAC->RxDescrPerRing -
17579- (pAC->RxDescrPerRing / 4);
17580- } else {
17581- if (i == pAC->ActivePort) {
17582- pAC->RxPort[i].RxFillLimit = pAC->RxDescrPerRing -
17583- (pAC->RxDescrPerRing / 4);
17584- } else {
17585- pAC->RxPort[i].RxFillLimit = pAC->RxDescrPerRing -
17586- (pAC->RxDescrPerRing / 10);
17587- }
17588- }
17589- }
17590+ /* Change RxFillLimit to 1 */
17591+ if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
17592+ pAC->RxPort[pNet->PortNr].RxFillLimit = 1;
17593 } else {
17594- /*
17595- ** Use the normal amount of rx buffers
17596- */
17597- for (i=0; i<pAC->GIni.GIMacsFound; i++) {
17598- if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
17599- pAC->RxPort[i].RxFillLimit = 1;
17600- } else {
17601- if (i == pAC->ActivePort) {
17602- pAC->RxPort[i].RxFillLimit = 1;
17603- } else {
17604- pAC->RxPort[i].RxFillLimit = pAC->RxDescrPerRing -
17605- (pAC->RxDescrPerRing / 4);
17606- }
17607- }
17608- }
17609+ pAC->RxPort[1 - pNet->PortNr].RxFillLimit = 1;
17610+ pAC->RxPort[pNet->PortNr].RxFillLimit = pAC->RxDescrPerRing -
17611+ (pAC->RxDescrPerRing / 4);
17612 }
17613-
17614- SkGeDeInit(pAC, pAC->IoBase);
17615
17616- /*
17617- ** enable/disable hardware support for long frames
17618- */
17619- if (NewMtu > 1500) {
17620-// pAC->JumboActivated = SK_TRUE; /* is never set back !!! */
17621- pAC->GIni.GIPortUsage = SK_JUMBO_LINK;
17622+ /* clear and reinit the rx rings here, because of new MTU size */
17623+ if (CHIP_ID_YUKON_2(pAC)) {
17624+ SkY2PortStop(pAC, pAC->IoBase, pNet->PortNr, SK_STOP_ALL, SK_SOFT_RST);
17625+ SkY2AllocateRxBuffers(pAC, pAC->IoBase, pNet->PortNr);
17626+ SkY2PortStart(pAC, pAC->IoBase, pNet->PortNr);
17627 } else {
17628- if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
17629- pAC->GIni.GIPortUsage = SK_MUL_LINK;
17630- } else {
17631- pAC->GIni.GIPortUsage = SK_RED_LINK;
17632- }
17633- }
17634+// SkGeStopPort(pAC, pAC->IoBase, pNet->PortNr, SK_STOP_ALL, SK_SOFT_RST);
17635+#ifdef CONFIG_SK98LIN_NAPI
17636+ WorkToDo = 1;
17637+ ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE, &WorkDone, WorkToDo);
17638+#else
17639+ ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE);
17640+#endif
17641+ ClearRxRing(pAC, &pAC->RxPort[pNet->PortNr]);
17642+ FillRxRing(pAC, &pAC->RxPort[pNet->PortNr]);
17643
17644- SkGeInit( pAC, pAC->IoBase, SK_INIT_IO);
17645- SkI2cInit( pAC, pAC->IoBase, SK_INIT_IO);
17646- SkEventInit(pAC, pAC->IoBase, SK_INIT_IO);
17647- SkPnmiInit( pAC, pAC->IoBase, SK_INIT_IO);
17648- SkAddrInit( pAC, pAC->IoBase, SK_INIT_IO);
17649- SkRlmtInit( pAC, pAC->IoBase, SK_INIT_IO);
17650- SkTimerInit(pAC, pAC->IoBase, SK_INIT_IO);
17651-
17652- /*
17653- ** tschilling:
17654- ** Speed and others are set back to default in level 1 init!
17655- */
17656- GetConfiguration(pAC);
17657-
17658- SkGeInit( pAC, pAC->IoBase, SK_INIT_RUN);
17659- SkI2cInit( pAC, pAC->IoBase, SK_INIT_RUN);
17660- SkEventInit(pAC, pAC->IoBase, SK_INIT_RUN);
17661- SkPnmiInit( pAC, pAC->IoBase, SK_INIT_RUN);
17662- SkAddrInit( pAC, pAC->IoBase, SK_INIT_RUN);
17663- SkRlmtInit( pAC, pAC->IoBase, SK_INIT_RUN);
17664- SkTimerInit(pAC, pAC->IoBase, SK_INIT_RUN);
17665+ /* Enable transmit descriptor polling */
17666+ SkGePollTxD(pAC, pAC->IoBase, pNet->PortNr, SK_TRUE);
17667+ FillRxRing(pAC, &pAC->RxPort[pNet->PortNr]);
17668+ }
17669
17670- /*
17671- ** clear and reinit the rx rings here
17672- */
17673- for (i=0; i<pAC->GIni.GIMacsFound; i++) {
17674- ReceiveIrq(pAC, &pAC->RxPort[i], SK_TRUE);
17675- ClearRxRing(pAC, &pAC->RxPort[i]);
17676- FillRxRing(pAC, &pAC->RxPort[i]);
17677+ netif_start_queue(pAC->dev[pNet->PortNr]);
17678
17679- /*
17680- ** Enable transmit descriptor polling
17681- */
17682- SkGePollTxD(pAC, pAC->IoBase, i, SK_TRUE);
17683- FillRxRing(pAC, &pAC->RxPort[i]);
17684- };
17685+ spin_unlock(&pAC->TxPort[pNet->PortNr][TX_PRIO_LOW].TxDesRingLock);
17686
17687- SkGeYellowLED(pAC, pAC->IoBase, 1);
17688- SkDimEnableModerationIfNeeded(pAC);
17689- SkDimDisplayModerationSettings(pAC);
17690
17691- netif_start_queue(pAC->dev[pNet->PortNr]);
17692- for (i=pAC->GIni.GIMacsFound-1; i>=0; i--) {
17693- spin_unlock(&pAC->TxPort[i][TX_PRIO_LOW].TxDesRingLock);
17694- }
17695+ /* Notify RLMT about the changing and restarting one (or more) ports */
17696+ SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_START,
17697+ pNet->PortNr, -1, SK_TRUE);
17698
17699- /*
17700- ** Enable Interrupts again
17701- */
17702+ /* Enable Interrupts again */
17703 SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
17704 SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK);
17705
17706- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara);
17707- SkEventDispatcher(pAC, pAC->IoBase);
17708-
17709- /*
17710- ** Notify RLMT about the changing and restarting one (or more) ports
17711- */
17712- if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
17713- EvPara.Para32[0] = pAC->RlmtNets;
17714- EvPara.Para32[1] = -1;
17715- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_SET_NETS, EvPara);
17716- EvPara.Para32[0] = pNet->PortNr;
17717- EvPara.Para32[1] = -1;
17718- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara);
17719-
17720- if (netif_running(pOtherDev)) {
17721- DEV_NET *pOtherNet = netdev_priv(pOtherDev);
17722- EvPara.Para32[0] = pOtherNet->PortNr;
17723- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara);
17724- }
17725- } else {
17726- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara);
17727- }
17728-
17729- SkEventDispatcher(pAC, pAC->IoBase);
17730 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
17731-
17732- /*
17733- ** While testing this driver with latest kernel 2.5 (2.5.70), it
17734- ** seems as if upper layers have a problem to handle a successful
17735- ** return value of '0'. If such a zero is returned, the complete
17736- ** system hangs for several minutes (!), which is in acceptable.
17737- **
17738- ** Currently it is not clear, what the exact reason for this problem
17739- ** is. The implemented workaround for 2.5 is to return the desired
17740- ** new MTU size if all needed changes for the new MTU size where
17741- ** performed. In kernels 2.2 and 2.4, a zero value is returned,
17742- ** which indicates the successful change of the mtu-size.
17743- */
17744- return NewMtu;
17745+ return 0;
17746
17747-} /* SkGeChangeMtu */
17748+}
17749
17750
17751 /*****************************************************************************
17752@@ -2775,75 +3912,67 @@
17753 */
17754 static struct net_device_stats *SkGeStats(struct SK_NET_DEVICE *dev)
17755 {
17756-DEV_NET *pNet = netdev_priv(dev);
17757-SK_AC *pAC = pNet->pAC;
17758-SK_PNMI_STRUCT_DATA *pPnmiStruct; /* structure for all Pnmi-Data */
17759-SK_PNMI_STAT *pPnmiStat; /* pointer to virtual XMAC stat. data */
17760-SK_PNMI_CONF *pPnmiConf; /* pointer to virtual link config. */
17761-unsigned int Size; /* size of pnmi struct */
17762-unsigned long Flags; /* for spin lock */
17763-
17764- SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
17765- ("SkGeStats starts now...\n"));
17766- pPnmiStruct = &pAC->PnmiStruct;
17767+ DEV_NET *pNet = (DEV_NET*) dev->priv;
17768+ SK_AC *pAC = pNet->pAC;
17769+ unsigned long LateCollisions, ExcessiveCollisions, RxTooLong;
17770+ unsigned long Flags; /* for spin lock */
17771+ SK_U32 MaxNumOidEntries, Oid, Len;
17772+ char Buf[8];
17773+ struct {
17774+ SK_U32 Oid;
17775+ unsigned long *pVar;
17776+ } Vars[] = {
17777+ { OID_SKGE_STAT_TX_LATE_COL, &LateCollisions },
17778+ { OID_SKGE_STAT_TX_EXCESS_COL, &ExcessiveCollisions },
17779+ { OID_SKGE_STAT_RX_TOO_LONG, &RxTooLong },
17780+ { OID_SKGE_STAT_RX, &pAC->stats.rx_packets },
17781+ { OID_SKGE_STAT_TX, &pAC->stats.tx_packets },
17782+ { OID_SKGE_STAT_RX_OCTETS, &pAC->stats.rx_bytes },
17783+ { OID_SKGE_STAT_TX_OCTETS, &pAC->stats.tx_bytes },
17784+ { OID_SKGE_RX_NO_BUF_CTS, &pAC->stats.rx_dropped },
17785+ { OID_SKGE_TX_NO_BUF_CTS, &pAC->stats.tx_dropped },
17786+ { OID_SKGE_STAT_RX_MULTICAST, &pAC->stats.multicast },
17787+ { OID_SKGE_STAT_RX_RUNT, &pAC->stats.rx_length_errors },
17788+ { OID_SKGE_STAT_RX_FCS, &pAC->stats.rx_crc_errors },
17789+ { OID_SKGE_STAT_RX_FRAMING, &pAC->stats.rx_frame_errors },
17790+ { OID_SKGE_STAT_RX_OVERFLOW, &pAC->stats.rx_over_errors },
17791+ { OID_SKGE_STAT_RX_MISSED, &pAC->stats.rx_missed_errors },
17792+ { OID_SKGE_STAT_TX_CARRIER, &pAC->stats.tx_carrier_errors },
17793+ { OID_SKGE_STAT_TX_UNDERRUN, &pAC->stats.tx_fifo_errors },
17794+ };
17795+
17796+ if ((pAC->DiagModeActive == DIAG_NOTACTIVE) &&
17797+ (pAC->BoardLevel == SK_INIT_RUN)) {
17798+ memset(&pAC->stats, 0x00, sizeof(pAC->stats)); /* clean first */
17799+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
17800
17801-#ifdef SK_DIAG_SUPPORT
17802- if ((pAC->DiagModeActive == DIAG_NOTACTIVE) &&
17803- (pAC->BoardLevel == SK_INIT_RUN)) {
17804-#endif
17805- SK_MEMSET(pPnmiStruct, 0, sizeof(SK_PNMI_STRUCT_DATA));
17806- spin_lock_irqsave(&pAC->SlowPathLock, Flags);
17807- Size = SK_PNMI_STRUCT_SIZE;
17808- SkPnmiGetStruct(pAC, pAC->IoBase, pPnmiStruct, &Size, pNet->NetNr);
17809- spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
17810-#ifdef SK_DIAG_SUPPORT
17811- }
17812-#endif
17813+ MaxNumOidEntries = sizeof(Vars) / sizeof(Vars[0]);
17814+ for (Oid = 0; Oid < MaxNumOidEntries; Oid++) {
17815+ if (SkPnmiGetVar(pAC,pAC->IoBase, Vars[Oid].Oid,
17816+ &Buf, &Len, 1, pNet->NetNr) != SK_PNMI_ERR_OK) {
17817+ memset(Buf, 0x00, sizeof(Buf));
17818+ }
17819+ *Vars[Oid].pVar = (unsigned long) (*((SK_U64 *) Buf));
17820+ }
17821+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
17822
17823- pPnmiStat = &pPnmiStruct->Stat[0];
17824- pPnmiConf = &pPnmiStruct->Conf[0];
17825+ pAC->stats.collisions = LateCollisions + ExcessiveCollisions;
17826+ pAC->stats.tx_errors = pAC->stats.tx_carrier_errors +
17827+ pAC->stats.tx_fifo_errors;
17828+ pAC->stats.rx_errors = pAC->stats.rx_length_errors +
17829+ pAC->stats.rx_crc_errors +
17830+ pAC->stats.rx_frame_errors +
17831+ pAC->stats.rx_over_errors +
17832+ pAC->stats.rx_missed_errors;
17833
17834- pAC->stats.rx_packets = (SK_U32) pPnmiStruct->RxDeliveredCts & 0xFFFFFFFF;
17835- pAC->stats.tx_packets = (SK_U32) pPnmiStat->StatTxOkCts & 0xFFFFFFFF;
17836- pAC->stats.rx_bytes = (SK_U32) pPnmiStruct->RxOctetsDeliveredCts;
17837- pAC->stats.tx_bytes = (SK_U32) pPnmiStat->StatTxOctetsOkCts;
17838-
17839- if (dev->mtu <= 1500) {
17840- pAC->stats.rx_errors = (SK_U32) pPnmiStruct->InErrorsCts & 0xFFFFFFFF;
17841- } else {
17842- pAC->stats.rx_errors = (SK_U32) ((pPnmiStruct->InErrorsCts -
17843- pPnmiStat->StatRxTooLongCts) & 0xFFFFFFFF);
17844+ if (dev->mtu > 1500) {
17845+ pAC->stats.rx_errors = pAC->stats.rx_errors - RxTooLong;
17846+ }
17847 }
17848
17849-
17850- if (pAC->GIni.GP[0].PhyType == SK_PHY_XMAC && pAC->HWRevision < 12)
17851- pAC->stats.rx_errors = pAC->stats.rx_errors - pPnmiStat->StatRxShortsCts;
17852-
17853- pAC->stats.tx_errors = (SK_U32) pPnmiStat->StatTxSingleCollisionCts & 0xFFFFFFFF;
17854- pAC->stats.rx_dropped = (SK_U32) pPnmiStruct->RxNoBufCts & 0xFFFFFFFF;
17855- pAC->stats.tx_dropped = (SK_U32) pPnmiStruct->TxNoBufCts & 0xFFFFFFFF;
17856- pAC->stats.multicast = (SK_U32) pPnmiStat->StatRxMulticastOkCts & 0xFFFFFFFF;
17857- pAC->stats.collisions = (SK_U32) pPnmiStat->StatTxSingleCollisionCts & 0xFFFFFFFF;
17858-
17859- /* detailed rx_errors: */
17860- pAC->stats.rx_length_errors = (SK_U32) pPnmiStat->StatRxRuntCts & 0xFFFFFFFF;
17861- pAC->stats.rx_over_errors = (SK_U32) pPnmiStat->StatRxFifoOverflowCts & 0xFFFFFFFF;
17862- pAC->stats.rx_crc_errors = (SK_U32) pPnmiStat->StatRxFcsCts & 0xFFFFFFFF;
17863- pAC->stats.rx_frame_errors = (SK_U32) pPnmiStat->StatRxFramingCts & 0xFFFFFFFF;
17864- pAC->stats.rx_fifo_errors = (SK_U32) pPnmiStat->StatRxFifoOverflowCts & 0xFFFFFFFF;
17865- pAC->stats.rx_missed_errors = (SK_U32) pPnmiStat->StatRxMissedCts & 0xFFFFFFFF;
17866-
17867- /* detailed tx_errors */
17868- pAC->stats.tx_aborted_errors = (SK_U32) 0;
17869- pAC->stats.tx_carrier_errors = (SK_U32) pPnmiStat->StatTxCarrierCts & 0xFFFFFFFF;
17870- pAC->stats.tx_fifo_errors = (SK_U32) pPnmiStat->StatTxFifoUnderrunCts & 0xFFFFFFFF;
17871- pAC->stats.tx_heartbeat_errors = (SK_U32) pPnmiStat->StatTxCarrierCts & 0xFFFFFFFF;
17872- pAC->stats.tx_window_errors = (SK_U32) 0;
17873-
17874 return(&pAC->stats);
17875 } /* SkGeStats */
17876
17877-
17878 /*****************************************************************************
17879 *
17880 * SkGeIoctl - IO-control function
17881@@ -2851,38 +3980,41 @@
17882 * Description:
17883 * This function is called if an ioctl is issued on the device.
17884 * There are three subfunction for reading, writing and test-writing
17885- * the private MIB data structure (useful for SysKonnect-internal tools).
17886+ * the private MIB data structure (usefull for SysKonnect-internal tools).
17887 *
17888 * Returns:
17889 * 0, if everything is ok
17890 * !=0, on error
17891 */
17892-static int SkGeIoctl(struct SK_NET_DEVICE *dev, struct ifreq *rq, int cmd)
17893-{
17894-DEV_NET *pNet;
17895-SK_AC *pAC;
17896-void *pMemBuf;
17897-struct pci_dev *pdev = NULL;
17898-SK_GE_IOCTL Ioctl;
17899-unsigned int Err = 0;
17900-int Size = 0;
17901-int Ret = 0;
17902-unsigned int Length = 0;
17903-int HeaderLength = sizeof(SK_U32) + sizeof(SK_U32);
17904+static int SkGeIoctl(
17905+struct SK_NET_DEVICE *dev, /* the device the IOCTL is to be performed on */
17906+struct ifreq *rq, /* additional request structure containing data */
17907+int cmd) /* requested IOCTL command number */
17908+{
17909+ DEV_NET *pNet = (DEV_NET*) dev->priv;
17910+ SK_AC *pAC = pNet->pAC;
17911+ struct pci_dev *pdev = NULL;
17912+ void *pMemBuf;
17913+ SK_GE_IOCTL Ioctl;
17914+ unsigned long Flags; /* for spin lock */
17915+ unsigned int Err = 0;
17916+ unsigned int Length = 0;
17917+ int HeaderLength = sizeof(SK_U32) + sizeof(SK_U32);
17918+ int Size = 0;
17919+ int Ret = 0;
17920
17921 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
17922 ("SkGeIoctl starts now...\n"));
17923
17924- pNet = netdev_priv(dev);
17925- pAC = pNet->pAC;
17926-
17927 if(copy_from_user(&Ioctl, rq->ifr_data, sizeof(SK_GE_IOCTL))) {
17928 return -EFAULT;
17929 }
17930
17931 switch(cmd) {
17932- case SK_IOCTL_SETMIB:
17933- case SK_IOCTL_PRESETMIB:
17934+ case SIOCETHTOOL:
17935+ return SkEthIoctl(dev, rq);
17936+ case SK_IOCTL_SETMIB: /* FALL THRU */
17937+ case SK_IOCTL_PRESETMIB: /* FALL THRU (if capable!) */
17938 if (!capable(CAP_NET_ADMIN)) return -EPERM;
17939 case SK_IOCTL_GETMIB:
17940 if(copy_from_user(&pAC->PnmiStruct, Ioctl.pData,
17941@@ -2909,6 +4041,7 @@
17942 if (NULL == (pMemBuf = kmalloc(Length, GFP_KERNEL))) {
17943 return -ENOMEM;
17944 }
17945+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
17946 if(copy_from_user(pMemBuf, Ioctl.pData, Length)) {
17947 Err = -EFAULT;
17948 goto fault_gen;
17949@@ -2927,10 +4060,10 @@
17950 goto fault_gen;
17951 }
17952 fault_gen:
17953+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
17954 kfree(pMemBuf); /* cleanup everything */
17955 break;
17956-#ifdef SK_DIAG_SUPPORT
17957- case SK_IOCTL_DIAG:
17958+ case SK_IOCTL_DIAG:
17959 if (!capable(CAP_NET_ADMIN)) return -EPERM;
17960 if (Ioctl.Len < (sizeof(pAC->PnmiStruct) + HeaderLength)) {
17961 Length = Ioctl.Len;
17962@@ -2967,7 +4100,6 @@
17963 fault_diag:
17964 kfree(pMemBuf); /* cleanup everything */
17965 break;
17966-#endif
17967 default:
17968 Err = -EOPNOTSUPP;
17969 }
17970@@ -2999,12 +4131,12 @@
17971 unsigned int Size, /* length of ioctl data */
17972 int mode) /* flag for set/preset */
17973 {
17974-unsigned long Flags; /* for spin lock */
17975-SK_AC *pAC;
17976+ SK_AC *pAC = pNet->pAC;
17977+ unsigned long Flags; /* for spin lock */
17978
17979 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
17980 ("SkGeIocMib starts now...\n"));
17981- pAC = pNet->pAC;
17982+
17983 /* access MIB */
17984 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
17985 switch(mode) {
17986@@ -3047,17 +4179,18 @@
17987 SK_I32 Port; /* preferred port */
17988 SK_BOOL AutoSet;
17989 SK_BOOL DupSet;
17990-int LinkSpeed = SK_LSPEED_AUTO; /* Link speed */
17991-int AutoNeg = 1; /* autoneg off (0) or on (1) */
17992-int DuplexCap = 0; /* 0=both,1=full,2=half */
17993-int FlowCtrl = SK_FLOW_MODE_SYM_OR_REM; /* FlowControl */
17994-int MSMode = SK_MS_MODE_AUTO; /* master/slave mode */
17995-
17996-SK_BOOL IsConTypeDefined = SK_TRUE;
17997-SK_BOOL IsLinkSpeedDefined = SK_TRUE;
17998-SK_BOOL IsFlowCtrlDefined = SK_TRUE;
17999-SK_BOOL IsRoleDefined = SK_TRUE;
18000-SK_BOOL IsModeDefined = SK_TRUE;
18001+int LinkSpeed = SK_LSPEED_AUTO; /* Link speed */
18002+int AutoNeg = 1; /* autoneg off (0) or on (1) */
18003+int DuplexCap = 0; /* 0=both,1=full,2=half */
18004+int FlowCtrl = SK_FLOW_MODE_SYM_OR_REM; /* FlowControl */
18005+int MSMode = SK_MS_MODE_AUTO; /* master/slave mode */
18006+int IrqModMaskOffset = 6; /* all ints moderated=default */
18007+
18008+SK_BOOL IsConTypeDefined = SK_TRUE;
18009+SK_BOOL IsLinkSpeedDefined = SK_TRUE;
18010+SK_BOOL IsFlowCtrlDefined = SK_TRUE;
18011+SK_BOOL IsRoleDefined = SK_TRUE;
18012+SK_BOOL IsModeDefined = SK_TRUE;
18013 /*
18014 * The two parameters AutoNeg. and DuplexCap. map to one configuration
18015 * parameter. The mapping is described by this table:
18016@@ -3075,6 +4208,15 @@
18017 {SK_LMODE_AUTOBOTH , SK_LMODE_AUTOFULL , SK_LMODE_AUTOHALF },
18018 {SK_LMODE_AUTOSENSE, SK_LMODE_AUTOSENSE, SK_LMODE_AUTOSENSE} };
18019
18020+SK_U32 IrqModMask[7][2] =
18021+ { { IRQ_MASK_RX_ONLY , Y2_DRIVER_IRQS },
18022+ { IRQ_MASK_TX_ONLY , Y2_DRIVER_IRQS },
18023+ { IRQ_MASK_SP_ONLY , Y2_SPECIAL_IRQS },
18024+ { IRQ_MASK_SP_RX , Y2_IRQ_MASK },
18025+ { IRQ_MASK_TX_RX , Y2_DRIVER_IRQS },
18026+ { IRQ_MASK_SP_TX , Y2_IRQ_MASK },
18027+ { IRQ_MASK_RX_TX_SP, Y2_IRQ_MASK } };
18028+
18029 #define DC_BOTH 0
18030 #define DC_FULL 1
18031 #define DC_HALF 2
18032@@ -3107,6 +4249,7 @@
18033 ** ConType DupCap AutoNeg FlowCtrl Role Speed
18034 ** ------- ------ ------- -------- ---------- -----
18035 ** Auto Both On SymOrRem Auto Auto
18036+ ** 1000FD Full Off None <ignored> 1000
18037 ** 100FD Full Off None <ignored> 100
18038 ** 100HD Half Off None <ignored> 100
18039 ** 10FD Full Off None <ignored> 10
18040@@ -3114,66 +4257,84 @@
18041 **
18042 ** This ConType parameter is used for all ports of the adapter!
18043 */
18044- if ( (ConType != NULL) &&
18045+ if ( (ConType != NULL) &&
18046 (pAC->Index < SK_MAX_CARD_PARAM) &&
18047 (ConType[pAC->Index] != NULL) ) {
18048
18049- /* Check chipset family */
18050- if ((!pAC->ChipsetType) &&
18051- (strcmp(ConType[pAC->Index],"Auto")!=0) &&
18052- (strcmp(ConType[pAC->Index],"")!=0)) {
18053- /* Set the speed parameter back */
18054- printk("sk98lin: Illegal value \"%s\" "
18055- "for ConType."
18056- " Using Auto.\n",
18057- ConType[pAC->Index]);
18058+ /* Check chipset family */
18059+ if ((!pAC->ChipsetType) &&
18060+ (strcmp(ConType[pAC->Index],"Auto")!=0) &&
18061+ (strcmp(ConType[pAC->Index],"")!=0)) {
18062+ /* Set the speed parameter back */
18063+ printk("sk98lin: Illegal value \"%s\" "
18064+ "for ConType."
18065+ " Using Auto.\n",
18066+ ConType[pAC->Index]);
18067+
18068+ sprintf(ConType[pAC->Index], "Auto");
18069+ }
18070+
18071+ if ((pAC->GIni.GICopperType != SK_TRUE) &&
18072+ (strcmp(ConType[pAC->Index],"1000FD") != 0)) {
18073+ /* Set the speed parameter back */
18074+ printk("sk98lin: Illegal value \"%s\" "
18075+ "for ConType."
18076+ " Using Auto.\n",
18077+ ConType[pAC->Index]);
18078
18079- sprintf(ConType[pAC->Index], "Auto");
18080- }
18081+ sprintf(ConType[pAC->Index], "Auto");
18082+ }
18083
18084- if (strcmp(ConType[pAC->Index],"")==0) {
18085+ if (strcmp(ConType[pAC->Index],"")==0) {
18086 IsConTypeDefined = SK_FALSE; /* No ConType defined */
18087- } else if (strcmp(ConType[pAC->Index],"Auto")==0) {
18088+ } else if (strcmp(ConType[pAC->Index],"Auto")==0) {
18089 for (Port = 0; Port < SK_MAX_MACS; Port++) {
18090 M_CurrPort.PLinkModeConf = Capabilities[AN_ON][DC_BOTH];
18091 M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_SYM_OR_REM;
18092 M_CurrPort.PMSMode = SK_MS_MODE_AUTO;
18093 M_CurrPort.PLinkSpeed = SK_LSPEED_AUTO;
18094 }
18095- } else if (strcmp(ConType[pAC->Index],"100FD")==0) {
18096+ } else if (strcmp(ConType[pAC->Index],"1000FD")==0) {
18097+ for (Port = 0; Port < SK_MAX_MACS; Port++) {
18098+ M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_FULL];
18099+ M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE;
18100+ M_CurrPort.PMSMode = SK_MS_MODE_AUTO;
18101+ M_CurrPort.PLinkSpeed = SK_LSPEED_1000MBPS;
18102+ }
18103+ } else if (strcmp(ConType[pAC->Index],"100FD")==0) {
18104 for (Port = 0; Port < SK_MAX_MACS; Port++) {
18105 M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_FULL];
18106 M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE;
18107 M_CurrPort.PMSMode = SK_MS_MODE_AUTO;
18108 M_CurrPort.PLinkSpeed = SK_LSPEED_100MBPS;
18109 }
18110- } else if (strcmp(ConType[pAC->Index],"100HD")==0) {
18111+ } else if (strcmp(ConType[pAC->Index],"100HD")==0) {
18112 for (Port = 0; Port < SK_MAX_MACS; Port++) {
18113 M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_HALF];
18114 M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE;
18115 M_CurrPort.PMSMode = SK_MS_MODE_AUTO;
18116 M_CurrPort.PLinkSpeed = SK_LSPEED_100MBPS;
18117 }
18118- } else if (strcmp(ConType[pAC->Index],"10FD")==0) {
18119+ } else if (strcmp(ConType[pAC->Index],"10FD")==0) {
18120 for (Port = 0; Port < SK_MAX_MACS; Port++) {
18121 M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_FULL];
18122 M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE;
18123 M_CurrPort.PMSMode = SK_MS_MODE_AUTO;
18124 M_CurrPort.PLinkSpeed = SK_LSPEED_10MBPS;
18125 }
18126- } else if (strcmp(ConType[pAC->Index],"10HD")==0) {
18127+ } else if (strcmp(ConType[pAC->Index],"10HD")==0) {
18128 for (Port = 0; Port < SK_MAX_MACS; Port++) {
18129 M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_HALF];
18130 M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE;
18131 M_CurrPort.PMSMode = SK_MS_MODE_AUTO;
18132 M_CurrPort.PLinkSpeed = SK_LSPEED_10MBPS;
18133 }
18134- } else {
18135+ } else {
18136 printk("sk98lin: Illegal value \"%s\" for ConType\n",
18137 ConType[pAC->Index]);
18138 IsConTypeDefined = SK_FALSE; /* Wrong ConType defined */
18139 }
18140- } else {
18141+ } else {
18142 IsConTypeDefined = SK_FALSE; /* No ConType defined */
18143 }
18144
18145@@ -3192,14 +4353,30 @@
18146 } else if (strcmp(Speed_A[pAC->Index],"100")==0) {
18147 LinkSpeed = SK_LSPEED_100MBPS;
18148 } else if (strcmp(Speed_A[pAC->Index],"1000")==0) {
18149- LinkSpeed = SK_LSPEED_1000MBPS;
18150+ if ((pAC->PciDev->vendor == 0x11ab ) &&
18151+ (pAC->PciDev->device == 0x4350)) {
18152+ LinkSpeed = SK_LSPEED_100MBPS;
18153+ printk("sk98lin: Illegal value \"%s\" for Speed_A.\n"
18154+ "Gigabit speed not possible with this chip revision!",
18155+ Speed_A[pAC->Index]);
18156+ } else {
18157+ LinkSpeed = SK_LSPEED_1000MBPS;
18158+ }
18159 } else {
18160 printk("sk98lin: Illegal value \"%s\" for Speed_A\n",
18161 Speed_A[pAC->Index]);
18162 IsLinkSpeedDefined = SK_FALSE;
18163 }
18164 } else {
18165- IsLinkSpeedDefined = SK_FALSE;
18166+ if ((pAC->PciDev->vendor == 0x11ab ) &&
18167+ (pAC->PciDev->device == 0x4350)) {
18168+ /* Gigabit speed not supported
18169+ * Swith to speed 100
18170+ */
18171+ LinkSpeed = SK_LSPEED_100MBPS;
18172+ } else {
18173+ IsLinkSpeedDefined = SK_FALSE;
18174+ }
18175 }
18176
18177 /*
18178@@ -3294,9 +4471,6 @@
18179 }
18180
18181 if (!AutoSet && DupSet) {
18182- printk("sk98lin: Port A: Duplex setting not"
18183- " possible in\n default AutoNegotiation mode"
18184- " (Sense).\n Using AutoNegotiation On\n");
18185 AutoNeg = AN_ON;
18186 }
18187
18188@@ -3324,7 +4498,7 @@
18189 FlowCtrl = SK_FLOW_MODE_NONE;
18190 } else {
18191 printk("sk98lin: Illegal value \"%s\" for FlowCtrl_A\n",
18192- FlowCtrl_A[pAC->Index]);
18193+ FlowCtrl_A[pAC->Index]);
18194 IsFlowCtrlDefined = SK_FALSE;
18195 }
18196 } else {
18197@@ -3416,7 +4590,7 @@
18198 ** Decide whether to set new config value if somethig valid has
18199 ** been received.
18200 */
18201- if (IsLinkSpeedDefined) {
18202+ if (IsLinkSpeedDefined) {
18203 pAC->GIni.GP[1].PLinkSpeed = LinkSpeed;
18204 }
18205
18206@@ -3492,9 +4666,6 @@
18207 }
18208
18209 if (!AutoSet && DupSet) {
18210- printk("sk98lin: Port B: Duplex setting not"
18211- " possible in\n default AutoNegotiation mode"
18212- " (Sense).\n Using AutoNegotiation On\n");
18213 AutoNeg = AN_ON;
18214 }
18215
18216@@ -3607,11 +4778,15 @@
18217 }
18218
18219 pAC->RlmtNets = 1;
18220+ pAC->RlmtMode = 0;
18221
18222 if (RlmtMode != NULL && pAC->Index<SK_MAX_CARD_PARAM &&
18223 RlmtMode[pAC->Index] != NULL) {
18224 if (strcmp(RlmtMode[pAC->Index], "") == 0) {
18225- pAC->RlmtMode = 0;
18226+ if (pAC->GIni.GIMacsFound == 2) {
18227+ pAC->RlmtMode = SK_RLMT_CHECK_LINK;
18228+ pAC->RlmtNets = 2;
18229+ }
18230 } else if (strcmp(RlmtMode[pAC->Index], "CheckLinkState") == 0) {
18231 pAC->RlmtMode = SK_RLMT_CHECK_LINK;
18232 } else if (strcmp(RlmtMode[pAC->Index], "CheckLocalPort") == 0) {
18233@@ -3632,12 +4807,37 @@
18234 pAC->RlmtMode = 0;
18235 }
18236 } else {
18237- pAC->RlmtMode = 0;
18238+ if (pAC->GIni.GIMacsFound == 2) {
18239+ pAC->RlmtMode = SK_RLMT_CHECK_LINK;
18240+ pAC->RlmtNets = 2;
18241+ }
18242 }
18243-
18244+
18245+#ifdef SK_YUKON2
18246+ /*
18247+ ** use dualnet config per default
18248+ *
18249+ pAC->RlmtMode = SK_RLMT_CHECK_LINK;
18250+ pAC->RlmtNets = 2;
18251+ */
18252+#endif
18253+
18254+
18255+ /*
18256+ ** Check the LowLatance parameters
18257+ */
18258+ pAC->LowLatency = SK_FALSE;
18259+ if (LowLatency[pAC->Index] != NULL) {
18260+ if (strcmp(LowLatency[pAC->Index], "On") == 0) {
18261+ pAC->LowLatency = SK_TRUE;
18262+ }
18263+ }
18264+
18265+
18266 /*
18267 ** Check the interrupt moderation parameters
18268 */
18269+ pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_NONE;
18270 if (Moderation[pAC->Index] != NULL) {
18271 if (strcmp(Moderation[pAC->Index], "") == 0) {
18272 pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_NONE;
18273@@ -3651,70 +4851,49 @@
18274 printk("sk98lin: Illegal value \"%s\" for Moderation.\n"
18275 " Disable interrupt moderation.\n",
18276 Moderation[pAC->Index]);
18277- pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_NONE;
18278- }
18279- } else {
18280- pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_NONE;
18281- }
18282-
18283- if (Stats[pAC->Index] != NULL) {
18284- if (strcmp(Stats[pAC->Index], "Yes") == 0) {
18285- pAC->DynIrqModInfo.DisplayStats = SK_TRUE;
18286- } else {
18287- pAC->DynIrqModInfo.DisplayStats = SK_FALSE;
18288 }
18289 } else {
18290- pAC->DynIrqModInfo.DisplayStats = SK_FALSE;
18291+/* Set interrupt moderation if wished */
18292+#ifdef CONFIG_SK98LIN_STATINT
18293+ pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_STATIC;
18294+#endif
18295 }
18296
18297 if (ModerationMask[pAC->Index] != NULL) {
18298 if (strcmp(ModerationMask[pAC->Index], "Rx") == 0) {
18299- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_ONLY;
18300+ IrqModMaskOffset = 0;
18301 } else if (strcmp(ModerationMask[pAC->Index], "Tx") == 0) {
18302- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_TX_ONLY;
18303+ IrqModMaskOffset = 1;
18304 } else if (strcmp(ModerationMask[pAC->Index], "Sp") == 0) {
18305- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_SP_ONLY;
18306+ IrqModMaskOffset = 2;
18307 } else if (strcmp(ModerationMask[pAC->Index], "RxSp") == 0) {
18308- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_SP_RX;
18309+ IrqModMaskOffset = 3;
18310 } else if (strcmp(ModerationMask[pAC->Index], "SpRx") == 0) {
18311- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_SP_RX;
18312+ IrqModMaskOffset = 3;
18313 } else if (strcmp(ModerationMask[pAC->Index], "RxTx") == 0) {
18314- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_TX_RX;
18315+ IrqModMaskOffset = 4;
18316 } else if (strcmp(ModerationMask[pAC->Index], "TxRx") == 0) {
18317- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_TX_RX;
18318+ IrqModMaskOffset = 4;
18319 } else if (strcmp(ModerationMask[pAC->Index], "TxSp") == 0) {
18320- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_SP_TX;
18321+ IrqModMaskOffset = 5;
18322 } else if (strcmp(ModerationMask[pAC->Index], "SpTx") == 0) {
18323- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_SP_TX;
18324- } else if (strcmp(ModerationMask[pAC->Index], "RxTxSp") == 0) {
18325- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP;
18326- } else if (strcmp(ModerationMask[pAC->Index], "RxSpTx") == 0) {
18327- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP;
18328- } else if (strcmp(ModerationMask[pAC->Index], "TxRxSp") == 0) {
18329- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP;
18330- } else if (strcmp(ModerationMask[pAC->Index], "TxSpRx") == 0) {
18331- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP;
18332- } else if (strcmp(ModerationMask[pAC->Index], "SpTxRx") == 0) {
18333- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP;
18334- } else if (strcmp(ModerationMask[pAC->Index], "SpRxTx") == 0) {
18335- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP;
18336- } else { /* some rubbish */
18337- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_ONLY;
18338- }
18339- } else { /* operator has stated nothing */
18340- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_TX_RX;
18341- }
18342-
18343- if (AutoSizing[pAC->Index] != NULL) {
18344- if (strcmp(AutoSizing[pAC->Index], "On") == 0) {
18345- pAC->DynIrqModInfo.AutoSizing = SK_FALSE;
18346- } else {
18347- pAC->DynIrqModInfo.AutoSizing = SK_FALSE;
18348+ IrqModMaskOffset = 5;
18349+ } else { /* some rubbish stated */
18350+ // IrqModMaskOffset = 6; ->has been initialized
18351+ // already at the begin of this function...
18352 }
18353- } else { /* operator has stated nothing */
18354- pAC->DynIrqModInfo.AutoSizing = SK_FALSE;
18355+ }
18356+ if (!CHIP_ID_YUKON_2(pAC)) {
18357+ pAC->DynIrqModInfo.MaskIrqModeration = IrqModMask[IrqModMaskOffset][0];
18358+ } else {
18359+ pAC->DynIrqModInfo.MaskIrqModeration = IrqModMask[IrqModMaskOffset][1];
18360 }
18361
18362+ if (!CHIP_ID_YUKON_2(pAC)) {
18363+ pAC->DynIrqModInfo.MaxModIntsPerSec = C_INTS_PER_SEC_DEFAULT;
18364+ } else {
18365+ pAC->DynIrqModInfo.MaxModIntsPerSec = C_Y2_INTS_PER_SEC_DEFAULT;
18366+ }
18367 if (IntsPerSec[pAC->Index] != 0) {
18368 if ((IntsPerSec[pAC->Index]< C_INT_MOD_IPS_LOWER_RANGE) ||
18369 (IntsPerSec[pAC->Index] > C_INT_MOD_IPS_UPPER_RANGE)) {
18370@@ -3723,28 +4902,25 @@
18371 IntsPerSec[pAC->Index],
18372 C_INT_MOD_IPS_LOWER_RANGE,
18373 C_INT_MOD_IPS_UPPER_RANGE,
18374- C_INTS_PER_SEC_DEFAULT);
18375- pAC->DynIrqModInfo.MaxModIntsPerSec = C_INTS_PER_SEC_DEFAULT;
18376+ pAC->DynIrqModInfo.MaxModIntsPerSec);
18377 } else {
18378 pAC->DynIrqModInfo.MaxModIntsPerSec = IntsPerSec[pAC->Index];
18379 }
18380- } else {
18381- pAC->DynIrqModInfo.MaxModIntsPerSec = C_INTS_PER_SEC_DEFAULT;
18382- }
18383+ }
18384
18385 /*
18386 ** Evaluate upper and lower moderation threshold
18387 */
18388 pAC->DynIrqModInfo.MaxModIntsPerSecUpperLimit =
18389 pAC->DynIrqModInfo.MaxModIntsPerSec +
18390- (pAC->DynIrqModInfo.MaxModIntsPerSec / 2);
18391+ (pAC->DynIrqModInfo.MaxModIntsPerSec / 5);
18392
18393 pAC->DynIrqModInfo.MaxModIntsPerSecLowerLimit =
18394 pAC->DynIrqModInfo.MaxModIntsPerSec -
18395- (pAC->DynIrqModInfo.MaxModIntsPerSec / 2);
18396-
18397- pAC->DynIrqModInfo.PrevTimeVal = jiffies; /* initial value */
18398+ (pAC->DynIrqModInfo.MaxModIntsPerSec / 5);
18399
18400+ pAC->DynIrqModInfo.DynIrqModSampleInterval =
18401+ SK_DRV_MODERATION_TIMER_LENGTH;
18402
18403 } /* GetConfiguration */
18404
18405@@ -3759,62 +4935,22 @@
18406 *
18407 * Returns: N/A
18408 */
18409-static inline int ProductStr(
18410- SK_AC *pAC, /* pointer to adapter context */
18411- char *DeviceStr, /* result string */
18412- int StrLen /* length of the string */
18413-)
18414+static void ProductStr(SK_AC *pAC)
18415 {
18416-char Keyword[] = VPD_NAME; /* vpd productname identifier */
18417-int ReturnCode; /* return code from vpd_read */
18418-unsigned long Flags;
18419+ char Default[] = "Generic Marvell Yukon chipset Ethernet device";
18420+ char Key[] = VPD_NAME; /* VPD productname key */
18421+ int StrLen = 80; /* stringlen */
18422+ unsigned long Flags;
18423
18424 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
18425- ReturnCode = VpdRead(pAC, pAC->IoBase, Keyword, DeviceStr, &StrLen);
18426+ if (VpdRead(pAC, pAC->IoBase, Key, pAC->DeviceStr, &StrLen)) {
18427+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ERROR,
18428+ ("Error reading VPD data: %d\n", ReturnCode));
18429+ strcpy(pAC->DeviceStr, Default);
18430+ }
18431 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
18432-
18433- return ReturnCode;
18434 } /* ProductStr */
18435
18436-/*****************************************************************************
18437- *
18438- * StartDrvCleanupTimer - Start timer to check for descriptors which
18439- * might be placed in descriptor ring, but
18440- * havent been handled up to now
18441- *
18442- * Description:
18443- * This function requests a HW-timer fo the Yukon card. The actions to
18444- * perform when this timer expires, are located in the SkDrvEvent().
18445- *
18446- * Returns: N/A
18447- */
18448-static void
18449-StartDrvCleanupTimer(SK_AC *pAC) {
18450- SK_EVPARA EventParam; /* Event struct for timer event */
18451-
18452- SK_MEMSET((char *) &EventParam, 0, sizeof(EventParam));
18453- EventParam.Para32[0] = SK_DRV_RX_CLEANUP_TIMER;
18454- SkTimerStart(pAC, pAC->IoBase, &pAC->DrvCleanupTimer,
18455- SK_DRV_RX_CLEANUP_TIMER_LENGTH,
18456- SKGE_DRV, SK_DRV_TIMER, EventParam);
18457-}
18458-
18459-/*****************************************************************************
18460- *
18461- * StopDrvCleanupTimer - Stop timer to check for descriptors
18462- *
18463- * Description:
18464- * This function requests a HW-timer fo the Yukon card. The actions to
18465- * perform when this timer expires, are located in the SkDrvEvent().
18466- *
18467- * Returns: N/A
18468- */
18469-static void
18470-StopDrvCleanupTimer(SK_AC *pAC) {
18471- SkTimerStop(pAC, pAC->IoBase, &pAC->DrvCleanupTimer);
18472- SK_MEMSET((char *) &pAC->DrvCleanupTimer, 0, sizeof(SK_TIMER));
18473-}
18474-
18475 /****************************************************************************/
18476 /* functions for common modules *********************************************/
18477 /****************************************************************************/
18478@@ -3903,7 +5039,9 @@
18479 SK_U64 SkOsGetTime(SK_AC *pAC)
18480 {
18481 SK_U64 PrivateJiffies;
18482+
18483 SkOsGetTimeCurrent(pAC, &PrivateJiffies);
18484+
18485 return PrivateJiffies;
18486 } /* SkOsGetTime */
18487
18488@@ -3976,6 +5114,28 @@
18489
18490 /*****************************************************************************
18491 *
18492+ * SkPciWriteCfgDWord - write a 32 bit value to pci config space
18493+ *
18494+ * Description:
18495+ * This routine writes a 32 bit value to the pci configuration
18496+ * space.
18497+ *
18498+ * Returns:
18499+ * 0 - indicate everything worked ok.
18500+ * != 0 - error indication
18501+ */
18502+int SkPciWriteCfgDWord(
18503+SK_AC *pAC, /* Adapter Control structure pointer */
18504+int PciAddr, /* PCI register address */
18505+SK_U32 Val) /* pointer to store the read value */
18506+{
18507+ pci_write_config_dword(pAC->PciDev, PciAddr, Val);
18508+ return(0);
18509+} /* SkPciWriteCfgDWord */
18510+
18511+
18512+/*****************************************************************************
18513+ *
18514 * SkPciWriteCfgWord - write a 16 bit value to pci config space
18515 *
18516 * Description:
18517@@ -4036,29 +5196,27 @@
18518 *
18519 */
18520 int SkDrvEvent(
18521-SK_AC *pAC, /* pointer to adapter context */
18522-SK_IOC IoC, /* io-context */
18523-SK_U32 Event, /* event-id */
18524-SK_EVPARA Param) /* event-parameter */
18525-{
18526-SK_MBUF *pRlmtMbuf; /* pointer to a rlmt-mbuf structure */
18527-struct sk_buff *pMsg; /* pointer to a message block */
18528-int FromPort; /* the port from which we switch away */
18529-int ToPort; /* the port we switch to */
18530-SK_EVPARA NewPara; /* parameter for further events */
18531-int Stat;
18532-unsigned long Flags;
18533-SK_BOOL DualNet;
18534+SK_AC *pAC, /* pointer to adapter context */
18535+SK_IOC IoC, /* IO control context */
18536+SK_U32 Event, /* event-id */
18537+SK_EVPARA Param) /* event-parameter */
18538+{
18539+ SK_MBUF *pRlmtMbuf; /* pointer to a rlmt-mbuf structure */
18540+ struct sk_buff *pMsg; /* pointer to a message block */
18541+ SK_BOOL DualNet;
18542+ SK_U32 Reason;
18543+ unsigned long Flags;
18544+ unsigned long InitFlags;
18545+ int FromPort; /* the port from which we switch away */
18546+ int ToPort; /* the port we switch to */
18547+ int Stat;
18548+ DEV_NET *pNet = NULL;
18549+#ifdef CONFIG_SK98LIN_NAPI
18550+ int WorkToDo = 1; /* min(*budget, dev->quota); */
18551+ int WorkDone = 0;
18552+#endif
18553
18554 switch (Event) {
18555- case SK_DRV_ADAP_FAIL:
18556- SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18557- ("ADAPTER FAIL EVENT\n"));
18558- printk("%s: Adapter failed.\n", pAC->dev[0]->name);
18559- /* disable interrupts */
18560- SK_OUT32(pAC->IoBase, B0_IMSK, 0);
18561- /* cgoos */
18562- break;
18563 case SK_DRV_PORT_FAIL:
18564 FromPort = Param.Para32[0];
18565 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18566@@ -4068,210 +5226,296 @@
18567 } else {
18568 printk("%s: Port B failed.\n", pAC->dev[1]->name);
18569 }
18570- /* cgoos */
18571 break;
18572- case SK_DRV_PORT_RESET: /* SK_U32 PortIdx */
18573- /* action list 4 */
18574+ case SK_DRV_PORT_RESET:
18575 FromPort = Param.Para32[0];
18576 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18577 ("PORT RESET EVENT, Port: %d ", FromPort));
18578- NewPara.Para64 = FromPort;
18579- SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_XMAC_RESET, NewPara);
18580+ SkLocalEventQueue64(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET,
18581+ FromPort, SK_FALSE);
18582 spin_lock_irqsave(
18583 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18584 Flags);
18585-
18586- SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_HARD_RST);
18587- netif_carrier_off(pAC->dev[Param.Para32[0]]);
18588+ if (CHIP_ID_YUKON_2(pAC)) {
18589+ SkY2PortStop(pAC, IoC, FromPort, SK_STOP_ALL, SK_HARD_RST);
18590+ } else {
18591+ SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_HARD_RST);
18592+ }
18593+ pAC->dev[Param.Para32[0]]->flags &= ~IFF_RUNNING;
18594 spin_unlock_irqrestore(
18595 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18596 Flags);
18597
18598- /* clear rx ring from received frames */
18599- ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE);
18600-
18601- ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
18602+ if (!CHIP_ID_YUKON_2(pAC)) {
18603+#ifdef CONFIG_SK98LIN_NAPI
18604+ WorkToDo = 1;
18605+ ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE, &WorkDone, WorkToDo);
18606+#else
18607+ ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE);
18608+#endif
18609+ ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
18610+ }
18611 spin_lock_irqsave(
18612 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18613 Flags);
18614-
18615- /* tschilling: Handling of return value inserted. */
18616- if (SkGeInitPort(pAC, IoC, FromPort)) {
18617- if (FromPort == 0) {
18618- printk("%s: SkGeInitPort A failed.\n", pAC->dev[0]->name);
18619+
18620+#ifdef USE_TIST_FOR_RESET
18621+ if (pAC->GIni.GIYukon2) {
18622+#ifdef Y2_RECOVERY
18623+ /* for Yukon II we want to have tist enabled all the time */
18624+ if (!SK_ADAPTER_WAITING_FOR_TIST(pAC)) {
18625+ Y2_ENABLE_TIST(pAC->IoBase);
18626+ }
18627+#else
18628+ /* make sure that we do not accept any status LEs from now on */
18629+ if (SK_ADAPTER_WAITING_FOR_TIST(pAC)) {
18630+#endif
18631+ /* port already waiting for tist */
18632+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
18633+ ("Port %c is now waiting for specific Tist\n",
18634+ 'A' + FromPort));
18635+ SK_SET_WAIT_BIT_FOR_PORT(
18636+ pAC,
18637+ SK_PSTATE_WAITING_FOR_SPECIFIC_TIST,
18638+ FromPort);
18639+ /* get current timestamp */
18640+ Y2_GET_TIST_LOW_VAL(pAC->IoBase, &pAC->MinTistLo);
18641+ pAC->MinTistHi = pAC->GIni.GITimeStampCnt;
18642+#ifndef Y2_RECOVERY
18643 } else {
18644- printk("%s: SkGeInitPort B failed.\n", pAC->dev[1]->name);
18645+ /* nobody is waiting yet */
18646+ SK_SET_WAIT_BIT_FOR_PORT(
18647+ pAC,
18648+ SK_PSTATE_WAITING_FOR_ANY_TIST,
18649+ FromPort);
18650+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
18651+ ("Port %c is now waiting for any Tist (0x%X)\n",
18652+ 'A' + FromPort, pAC->AdapterResetState));
18653+ /* start tist */
18654+ Y2_ENABLE_TIST(pAC-IoBase);
18655+ }
18656+#endif
18657+ }
18658+#endif
18659+
18660+#ifdef Y2_LE_CHECK
18661+ /* mark entries invalid */
18662+ pAC->LastPort = 3;
18663+ pAC->LastOpc = 0xFF;
18664+#endif
18665+ if (CHIP_ID_YUKON_2(pAC)) {
18666+ SkY2PortStart(pAC, IoC, FromPort);
18667+ } else {
18668+ /* tschilling: Handling of return value inserted. */
18669+ if (SkGeInitPort(pAC, IoC, FromPort)) {
18670+ if (FromPort == 0) {
18671+ printk("%s: SkGeInitPort A failed.\n", pAC->dev[0]->name);
18672+ } else {
18673+ printk("%s: SkGeInitPort B failed.\n", pAC->dev[1]->name);
18674+ }
18675 }
18676+ SkAddrMcUpdate(pAC,IoC, FromPort);
18677+ PortReInitBmu(pAC, FromPort);
18678+ SkGePollTxD(pAC, IoC, FromPort, SK_TRUE);
18679+ CLEAR_AND_START_RX(FromPort);
18680 }
18681- SkAddrMcUpdate(pAC,IoC, FromPort);
18682- PortReInitBmu(pAC, FromPort);
18683- SkGePollTxD(pAC, IoC, FromPort, SK_TRUE);
18684- ClearAndStartRx(pAC, FromPort);
18685 spin_unlock_irqrestore(
18686 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18687 Flags);
18688 break;
18689- case SK_DRV_NET_UP: /* SK_U32 PortIdx */
18690- { struct net_device *dev = pAC->dev[Param.Para32[0]];
18691- /* action list 5 */
18692+ case SK_DRV_NET_UP:
18693+ spin_lock_irqsave(&pAC->InitLock, InitFlags);
18694 FromPort = Param.Para32[0];
18695 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18696- ("NET UP EVENT, Port: %d ", Param.Para32[0]));
18697- /* Mac update */
18698- SkAddrMcUpdate(pAC,IoC, FromPort);
18699-
18700+ ("NET UP EVENT, Port: %d ", FromPort));
18701+ SkAddrMcUpdate(pAC,IoC, FromPort); /* Mac update */
18702 if (DoPrintInterfaceChange) {
18703- printk("%s: network connection up using"
18704- " port %c\n", pAC->dev[Param.Para32[0]]->name, 'A'+Param.Para32[0]);
18705+ printk("%s: network connection up using port %c\n",
18706+ pAC->dev[FromPort]->name, 'A'+FromPort);
18707
18708- /* tschilling: Values changed according to LinkSpeedUsed. */
18709- Stat = pAC->GIni.GP[FromPort].PLinkSpeedUsed;
18710- if (Stat == SK_LSPEED_STAT_10MBPS) {
18711- printk(" speed: 10\n");
18712- } else if (Stat == SK_LSPEED_STAT_100MBPS) {
18713- printk(" speed: 100\n");
18714- } else if (Stat == SK_LSPEED_STAT_1000MBPS) {
18715- printk(" speed: 1000\n");
18716- } else {
18717- printk(" speed: unknown\n");
18718- }
18719+ /* tschilling: Values changed according to LinkSpeedUsed. */
18720+ Stat = pAC->GIni.GP[FromPort].PLinkSpeedUsed;
18721+ if (Stat == SK_LSPEED_STAT_10MBPS) {
18722+ printk(" speed: 10\n");
18723+ } else if (Stat == SK_LSPEED_STAT_100MBPS) {
18724+ printk(" speed: 100\n");
18725+ } else if (Stat == SK_LSPEED_STAT_1000MBPS) {
18726+ printk(" speed: 1000\n");
18727+ } else {
18728+ printk(" speed: unknown\n");
18729+ }
18730
18731+ Stat = pAC->GIni.GP[FromPort].PLinkModeStatus;
18732+ if ((Stat == SK_LMODE_STAT_AUTOHALF) ||
18733+ (Stat == SK_LMODE_STAT_AUTOFULL)) {
18734+ printk(" autonegotiation: yes\n");
18735+ } else {
18736+ printk(" autonegotiation: no\n");
18737+ }
18738
18739- Stat = pAC->GIni.GP[FromPort].PLinkModeStatus;
18740- if (Stat == SK_LMODE_STAT_AUTOHALF ||
18741- Stat == SK_LMODE_STAT_AUTOFULL) {
18742- printk(" autonegotiation: yes\n");
18743- }
18744- else {
18745- printk(" autonegotiation: no\n");
18746- }
18747- if (Stat == SK_LMODE_STAT_AUTOHALF ||
18748- Stat == SK_LMODE_STAT_HALF) {
18749- printk(" duplex mode: half\n");
18750- }
18751- else {
18752- printk(" duplex mode: full\n");
18753- }
18754- Stat = pAC->GIni.GP[FromPort].PFlowCtrlStatus;
18755- if (Stat == SK_FLOW_STAT_REM_SEND ) {
18756- printk(" flowctrl: remote send\n");
18757- }
18758- else if (Stat == SK_FLOW_STAT_LOC_SEND ){
18759- printk(" flowctrl: local send\n");
18760- }
18761- else if (Stat == SK_FLOW_STAT_SYMMETRIC ){
18762- printk(" flowctrl: symmetric\n");
18763- }
18764- else {
18765- printk(" flowctrl: none\n");
18766- }
18767-
18768- /* tschilling: Check against CopperType now. */
18769- if ((pAC->GIni.GICopperType == SK_TRUE) &&
18770- (pAC->GIni.GP[FromPort].PLinkSpeedUsed ==
18771- SK_LSPEED_STAT_1000MBPS)) {
18772- Stat = pAC->GIni.GP[FromPort].PMSStatus;
18773- if (Stat == SK_MS_STAT_MASTER ) {
18774- printk(" role: master\n");
18775+ if ((Stat == SK_LMODE_STAT_AUTOHALF) ||
18776+ (Stat == SK_LMODE_STAT_HALF)) {
18777+ printk(" duplex mode: half\n");
18778+ } else {
18779+ printk(" duplex mode: full\n");
18780 }
18781- else if (Stat == SK_MS_STAT_SLAVE ) {
18782- printk(" role: slave\n");
18783+
18784+ Stat = pAC->GIni.GP[FromPort].PFlowCtrlStatus;
18785+ if (Stat == SK_FLOW_STAT_REM_SEND ) {
18786+ printk(" flowctrl: remote send\n");
18787+ } else if (Stat == SK_FLOW_STAT_LOC_SEND ) {
18788+ printk(" flowctrl: local send\n");
18789+ } else if (Stat == SK_FLOW_STAT_SYMMETRIC ) {
18790+ printk(" flowctrl: symmetric\n");
18791+ } else {
18792+ printk(" flowctrl: none\n");
18793 }
18794- else {
18795- printk(" role: ???\n");
18796+
18797+ /* tschilling: Check against CopperType now. */
18798+ if ((pAC->GIni.GICopperType == SK_TRUE) &&
18799+ (pAC->GIni.GP[FromPort].PLinkSpeedUsed ==
18800+ SK_LSPEED_STAT_1000MBPS)) {
18801+ Stat = pAC->GIni.GP[FromPort].PMSStatus;
18802+ if (Stat == SK_MS_STAT_MASTER ) {
18803+ printk(" role: master\n");
18804+ } else if (Stat == SK_MS_STAT_SLAVE ) {
18805+ printk(" role: slave\n");
18806+ } else {
18807+ printk(" role: ???\n");
18808+ }
18809 }
18810- }
18811
18812- /*
18813- Display dim (dynamic interrupt moderation)
18814- informations
18815- */
18816- if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_STATIC)
18817- printk(" irq moderation: static (%d ints/sec)\n",
18818+ /* Display interrupt moderation informations */
18819+ if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_STATIC) {
18820+ printk(" irq moderation: static (%d ints/sec)\n",
18821 pAC->DynIrqModInfo.MaxModIntsPerSec);
18822- else if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_DYNAMIC)
18823- printk(" irq moderation: dynamic (%d ints/sec)\n",
18824+ } else if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
18825+ printk(" irq moderation: dynamic (%d ints/sec)\n",
18826 pAC->DynIrqModInfo.MaxModIntsPerSec);
18827- else
18828- printk(" irq moderation: disabled\n");
18829+ } else {
18830+ printk(" irq moderation: disabled\n");
18831+ }
18832+
18833+#ifdef NETIF_F_TSO
18834+ if (CHIP_ID_YUKON_2(pAC)) {
18835+ if (pAC->dev[FromPort]->features & NETIF_F_TSO) {
18836+ printk(" tcp offload: enabled\n");
18837+ } else {
18838+ printk(" tcp offload: disabled\n");
18839+ }
18840+ }
18841+#endif
18842
18843+ if (pAC->dev[FromPort]->features & NETIF_F_SG) {
18844+ printk(" scatter-gather: enabled\n");
18845+ } else {
18846+ printk(" scatter-gather: disabled\n");
18847+ }
18848
18849- printk(" scatter-gather: %s\n",
18850- (dev->features & NETIF_F_SG) ? "enabled" : "disabled");
18851- printk(" tx-checksum: %s\n",
18852- (dev->features & NETIF_F_IP_CSUM) ? "enabled" : "disabled");
18853- printk(" rx-checksum: %s\n",
18854- pAC->RxPort[Param.Para32[0]].RxCsum ? "enabled" : "disabled");
18855+ if (pAC->dev[FromPort]->features & NETIF_F_IP_CSUM) {
18856+ printk(" tx-checksum: enabled\n");
18857+ } else {
18858+ printk(" tx-checksum: disabled\n");
18859+ }
18860
18861+ if (pAC->RxPort[FromPort].UseRxCsum) {
18862+ printk(" rx-checksum: enabled\n");
18863+ } else {
18864+ printk(" rx-checksum: disabled\n");
18865+ }
18866+#ifdef CONFIG_SK98LIN_NAPI
18867+ printk(" rx-polling: enabled\n");
18868+#endif
18869+ if (pAC->LowLatency) {
18870+ printk(" low latency: enabled\n");
18871+ }
18872 } else {
18873- DoPrintInterfaceChange = SK_TRUE;
18874- }
18875+ DoPrintInterfaceChange = SK_TRUE;
18876+ }
18877
18878- if ((Param.Para32[0] != pAC->ActivePort) &&
18879- (pAC->RlmtNets == 1)) {
18880- NewPara.Para32[0] = pAC->ActivePort;
18881- NewPara.Para32[1] = Param.Para32[0];
18882- SkEventQueue(pAC, SKGE_DRV, SK_DRV_SWITCH_INTERN,
18883- NewPara);
18884+ if ((FromPort != pAC->ActivePort)&&(pAC->RlmtNets == 1)) {
18885+ SkLocalEventQueue(pAC, SKGE_DRV, SK_DRV_SWITCH_INTERN,
18886+ pAC->ActivePort, FromPort, SK_FALSE);
18887 }
18888
18889 /* Inform the world that link protocol is up. */
18890- netif_carrier_on(dev);
18891+ netif_wake_queue(pAC->dev[FromPort]);
18892+ netif_carrier_on(pAC->dev[FromPort]);
18893+ pAC->dev[FromPort]->flags |= IFF_RUNNING;
18894+ spin_unlock_irqrestore(&pAC->InitLock, InitFlags);
18895 break;
18896- }
18897- case SK_DRV_NET_DOWN: /* SK_U32 Reason */
18898- /* action list 7 */
18899+ case SK_DRV_NET_DOWN:
18900+ Reason = Param.Para32[0];
18901+ FromPort = Param.Para32[1];
18902 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18903 ("NET DOWN EVENT "));
18904+
18905+ /* Stop queue and carrier */
18906+ netif_stop_queue(pAC->dev[FromPort]);
18907+ netif_carrier_off(pAC->dev[FromPort]);
18908+
18909+ /* Print link change */
18910 if (DoPrintInterfaceChange) {
18911- printk("%s: network connection down\n",
18912- pAC->dev[Param.Para32[1]]->name);
18913+ if (pAC->dev[FromPort]->flags & IFF_RUNNING) {
18914+ printk("%s: network connection down\n",
18915+ pAC->dev[FromPort]->name);
18916+ }
18917 } else {
18918 DoPrintInterfaceChange = SK_TRUE;
18919 }
18920- netif_carrier_off(pAC->dev[Param.Para32[1]]);
18921+ pAC->dev[FromPort]->flags &= ~IFF_RUNNING;
18922 break;
18923- case SK_DRV_SWITCH_HARD: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */
18924- SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18925- ("PORT SWITCH HARD "));
18926- case SK_DRV_SWITCH_SOFT: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */
18927- /* action list 6 */
18928- printk("%s: switching to port %c\n", pAC->dev[0]->name,
18929- 'A'+Param.Para32[1]);
18930- case SK_DRV_SWITCH_INTERN: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */
18931+ case SK_DRV_SWITCH_HARD: /* FALL THRU */
18932+ case SK_DRV_SWITCH_SOFT: /* FALL THRU */
18933+ case SK_DRV_SWITCH_INTERN:
18934 FromPort = Param.Para32[0];
18935- ToPort = Param.Para32[1];
18936+ ToPort = Param.Para32[1];
18937+ printk("%s: switching from port %c to port %c\n",
18938+ pAC->dev[0]->name, 'A'+FromPort, 'A'+ToPort);
18939 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
18940 ("PORT SWITCH EVENT, From: %d To: %d (Pref %d) ",
18941 FromPort, ToPort, pAC->Rlmt.Net[0].PrefPort));
18942- NewPara.Para64 = FromPort;
18943- SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_XMAC_RESET, NewPara);
18944- NewPara.Para64 = ToPort;
18945- SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_XMAC_RESET, NewPara);
18946+ SkLocalEventQueue64(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET,
18947+ FromPort, SK_FALSE);
18948+ SkLocalEventQueue64(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET,
18949+ ToPort, SK_FALSE);
18950 spin_lock_irqsave(
18951 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18952 Flags);
18953 spin_lock(&pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock);
18954- SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST);
18955- SkGeStopPort(pAC, IoC, ToPort, SK_STOP_ALL, SK_SOFT_RST);
18956+ if (CHIP_ID_YUKON_2(pAC)) {
18957+ SkY2PortStop(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST);
18958+ SkY2PortStop(pAC, IoC, ToPort, SK_STOP_ALL, SK_SOFT_RST);
18959+ }
18960+ else {
18961+ SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST);
18962+ SkGeStopPort(pAC, IoC, ToPort, SK_STOP_ALL, SK_SOFT_RST);
18963+ }
18964 spin_unlock(&pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock);
18965 spin_unlock_irqrestore(
18966 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18967 Flags);
18968
18969- ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE); /* clears rx ring */
18970- ReceiveIrq(pAC, &pAC->RxPort[ToPort], SK_FALSE); /* clears rx ring */
18971
18972- ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
18973- ClearTxRing(pAC, &pAC->TxPort[ToPort][TX_PRIO_LOW]);
18974+ if (!CHIP_ID_YUKON_2(pAC)) {
18975+#ifdef CONFIG_SK98LIN_NAPI
18976+ WorkToDo = 1;
18977+ ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE, &WorkDone, WorkToDo);
18978+ ReceiveIrq(pAC, &pAC->RxPort[ToPort], SK_FALSE, &WorkDone, WorkToDo);
18979+#else
18980+ ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE); /* clears rx ring */
18981+ ReceiveIrq(pAC, &pAC->RxPort[ToPort], SK_FALSE); /* clears rx ring */
18982+#endif
18983+ ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
18984+ ClearTxRing(pAC, &pAC->TxPort[ToPort][TX_PRIO_LOW]);
18985+ }
18986+
18987 spin_lock_irqsave(
18988 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
18989 Flags);
18990 spin_lock(&pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock);
18991 pAC->ActivePort = ToPort;
18992-#if 0
18993- SetQueueSizes(pAC);
18994-#else
18995+
18996 /* tschilling: New common function with minimum size check. */
18997 DualNet = SK_FALSE;
18998 if (pAC->RlmtNets == 2) {
18999@@ -4289,74 +5533,316 @@
19000 printk("SkGeInitAssignRamToQueues failed.\n");
19001 break;
19002 }
19003-#endif
19004- /* tschilling: Handling of return values inserted. */
19005- if (SkGeInitPort(pAC, IoC, FromPort) ||
19006- SkGeInitPort(pAC, IoC, ToPort)) {
19007- printk("%s: SkGeInitPort failed.\n", pAC->dev[0]->name);
19008+
19009+ if (!CHIP_ID_YUKON_2(pAC)) {
19010+ /* tschilling: Handling of return values inserted. */
19011+ if (SkGeInitPort(pAC, IoC, FromPort) ||
19012+ SkGeInitPort(pAC, IoC, ToPort)) {
19013+ printk("%s: SkGeInitPort failed.\n", pAC->dev[0]->name);
19014+ }
19015 }
19016- if (Event == SK_DRV_SWITCH_SOFT) {
19017- SkMacRxTxEnable(pAC, IoC, FromPort);
19018+ if (!CHIP_ID_YUKON_2(pAC)) {
19019+ if (Event == SK_DRV_SWITCH_SOFT) {
19020+ SkMacRxTxEnable(pAC, IoC, FromPort);
19021+ }
19022+ SkMacRxTxEnable(pAC, IoC, ToPort);
19023 }
19024- SkMacRxTxEnable(pAC, IoC, ToPort);
19025+
19026 SkAddrSwap(pAC, IoC, FromPort, ToPort);
19027 SkAddrMcUpdate(pAC, IoC, FromPort);
19028 SkAddrMcUpdate(pAC, IoC, ToPort);
19029- PortReInitBmu(pAC, FromPort);
19030- PortReInitBmu(pAC, ToPort);
19031- SkGePollTxD(pAC, IoC, FromPort, SK_TRUE);
19032- SkGePollTxD(pAC, IoC, ToPort, SK_TRUE);
19033- ClearAndStartRx(pAC, FromPort);
19034- ClearAndStartRx(pAC, ToPort);
19035+
19036+#ifdef USE_TIST_FOR_RESET
19037+ if (pAC->GIni.GIYukon2) {
19038+ /* make sure that we do not accept any status LEs from now on */
19039+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
19040+ ("both Ports now waiting for specific Tist\n"));
19041+ SK_SET_WAIT_BIT_FOR_PORT(
19042+ pAC,
19043+ SK_PSTATE_WAITING_FOR_ANY_TIST,
19044+ 0);
19045+ SK_SET_WAIT_BIT_FOR_PORT(
19046+ pAC,
19047+ SK_PSTATE_WAITING_FOR_ANY_TIST,
19048+ 1);
19049+
19050+ /* start tist */
19051+ Y2_ENABLE_TIST(pAC->IoBase);
19052+ }
19053+#endif
19054+ if (!CHIP_ID_YUKON_2(pAC)) {
19055+ PortReInitBmu(pAC, FromPort);
19056+ PortReInitBmu(pAC, ToPort);
19057+ SkGePollTxD(pAC, IoC, FromPort, SK_TRUE);
19058+ SkGePollTxD(pAC, IoC, ToPort, SK_TRUE);
19059+ CLEAR_AND_START_RX(FromPort);
19060+ CLEAR_AND_START_RX(ToPort);
19061+ } else {
19062+ SkY2PortStart(pAC, IoC, FromPort);
19063+ SkY2PortStart(pAC, IoC, ToPort);
19064+#ifdef SK_YUKON2
19065+ /* in yukon-II always port 0 has to be started first */
19066+ // SkY2PortStart(pAC, IoC, 0);
19067+ // SkY2PortStart(pAC, IoC, 1);
19068+#endif
19069+ }
19070 spin_unlock(&pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock);
19071 spin_unlock_irqrestore(
19072 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
19073 Flags);
19074 break;
19075 case SK_DRV_RLMT_SEND: /* SK_MBUF *pMb */
19076- SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
19077- ("RLS "));
19078+ SK_DBG_MSG(NULL,SK_DBGMOD_DRV,SK_DBGCAT_DRV_EVENT,("RLS "));
19079 pRlmtMbuf = (SK_MBUF*) Param.pParaPtr;
19080 pMsg = (struct sk_buff*) pRlmtMbuf->pOs;
19081 skb_put(pMsg, pRlmtMbuf->Length);
19082- if (XmitFrame(pAC, &pAC->TxPort[pRlmtMbuf->PortIdx][TX_PRIO_LOW],
19083- pMsg) < 0)
19084+ if (!CHIP_ID_YUKON_2(pAC)) {
19085+ if (XmitFrame(pAC, &pAC->TxPort[pRlmtMbuf->PortIdx][TX_PRIO_LOW],
19086+ pMsg) < 0) {
19087+ DEV_KFREE_SKB_ANY(pMsg);
19088+ }
19089+ } else {
19090+ if (SkY2RlmtSend(pAC, pRlmtMbuf->PortIdx, pMsg) < 0) {
19091+ DEV_KFREE_SKB_ANY(pMsg);
19092+ }
19093+ }
19094+ break;
19095+ case SK_DRV_TIMER:
19096+ if (Param.Para32[0] == SK_DRV_MODERATION_TIMER) {
19097+ /* check what IRQs are to be moderated */
19098+ SkDimStartModerationTimer(pAC);
19099+ SkDimModerate(pAC);
19100+ } else {
19101+ printk("Expiration of unknown timer\n");
19102+ }
19103+ break;
19104+ case SK_DRV_ADAP_FAIL:
19105+#if (!defined (Y2_RECOVERY) && !defined (Y2_LE_CHECK))
19106+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
19107+ ("ADAPTER FAIL EVENT\n"));
19108+ printk("%s: Adapter failed.\n", pAC->dev[0]->name);
19109+ SK_OUT32(pAC->IoBase, B0_IMSK, 0); /* disable interrupts */
19110+ break;
19111+#endif
19112+
19113+#if (defined (Y2_RECOVERY) || defined (Y2_LE_CHECK))
19114+ case SK_DRV_RECOVER:
19115+ spin_lock_irqsave(&pAC->InitLock, InitFlags);
19116+ pNet = (DEV_NET *) pAC->dev[Param.Para32[0]]->priv;
19117+
19118+ /* Recover already in progress */
19119+ if (pNet->InRecover) {
19120+ break;
19121+ }
19122+
19123+ netif_stop_queue(pAC->dev[Param.Para32[0]]); /* stop device if running */
19124+ pNet->InRecover = SK_TRUE;
19125+
19126+ FromPort = Param.Para32[0];
19127+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
19128+ ("PORT RESET EVENT, Port: %d ", FromPort));
19129+
19130+ /* Disable interrupts */
19131+ SK_OUT32(pAC->IoBase, B0_IMSK, 0);
19132+ SK_OUT32(pAC->IoBase, B0_HWE_IMSK, 0);
19133+
19134+ SkLocalEventQueue64(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET,
19135+ FromPort, SK_FALSE);
19136+ spin_lock_irqsave(
19137+ &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
19138+ Flags);
19139+ if (CHIP_ID_YUKON_2(pAC)) {
19140+ SkY2PortStop(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST);
19141+ } else {
19142+ SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST);
19143+ }
19144+ pAC->dev[Param.Para32[0]]->flags &= ~IFF_RUNNING;
19145+ spin_unlock_irqrestore(
19146+ &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
19147+ Flags);
19148+
19149+ if (!CHIP_ID_YUKON_2(pAC)) {
19150+#ifdef CONFIG_SK98LIN_NAPI
19151+ WorkToDo = 1;
19152+ ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE, &WorkDone, WorkToDo);
19153+#else
19154+ ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE);
19155+#endif
19156+ ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
19157+ }
19158+ spin_lock_irqsave(
19159+ &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
19160+ Flags);
19161+
19162+#ifdef USE_TIST_FOR_RESET
19163+ if (pAC->GIni.GIYukon2) {
19164+#if 0
19165+ /* make sure that we do not accept any status LEs from now on */
19166+ Y2_ENABLE_TIST(pAC->IoBase);
19167+
19168+ /* get current timestamp */
19169+ Y2_GET_TIST_LOW_VAL(pAC->IoBase, &pAC->MinTistLo);
19170+ pAC->MinTistHi = pAC->GIni.GITimeStampCnt;
19171+
19172+ SK_SET_WAIT_BIT_FOR_PORT(
19173+ pAC,
19174+ SK_PSTATE_WAITING_FOR_SPECIFIC_TIST,
19175+ FromPort);
19176+#endif
19177+ SK_SET_WAIT_BIT_FOR_PORT(
19178+ pAC,
19179+ SK_PSTATE_WAITING_FOR_ANY_TIST,
19180+ FromPort);
19181+
19182+ /* start tist */
19183+ Y2_ENABLE_TIST(pAC->IoBase);
19184+ }
19185+#endif
19186+
19187+ /* Restart Receive BMU on Yukon-2 */
19188+ if (HW_FEATURE(pAC, HWF_WA_DEV_4167)) {
19189+ SkYuk2RestartRxBmu(pAC, IoC, FromPort);
19190+ }
19191+
19192+#ifdef Y2_LE_CHECK
19193+ /* mark entries invalid */
19194+ pAC->LastPort = 3;
19195+ pAC->LastOpc = 0xFF;
19196+#endif
19197+
19198+#endif
19199+ /* Restart ports but do not initialize PHY. */
19200+ if (CHIP_ID_YUKON_2(pAC)) {
19201+ SkY2PortStart(pAC, IoC, FromPort);
19202+ } else {
19203+ /* tschilling: Handling of return value inserted. */
19204+ if (SkGeInitPort(pAC, IoC, FromPort)) {
19205+ if (FromPort == 0) {
19206+ printk("%s: SkGeInitPort A failed.\n", pAC->dev[0]->name);
19207+ } else {
19208+ printk("%s: SkGeInitPort B failed.\n", pAC->dev[1]->name);
19209+ }
19210+ }
19211+ SkAddrMcUpdate(pAC,IoC, FromPort);
19212+ PortReInitBmu(pAC, FromPort);
19213+ SkGePollTxD(pAC, IoC, FromPort, SK_TRUE);
19214+ CLEAR_AND_START_RX(FromPort);
19215+ }
19216+ spin_unlock_irqrestore(
19217+ &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
19218+ Flags);
19219+
19220+ /* Map any waiting RX buffers to HW */
19221+ FillReceiveTableYukon2(pAC, pAC->IoBase, FromPort);
19222+
19223+ pNet->InRecover = SK_FALSE;
19224+ /* enable Interrupts */
19225+ SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
19226+ SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK);
19227+ netif_wake_queue(pAC->dev[FromPort]);
19228+ spin_unlock_irqrestore(&pAC->InitLock, InitFlags);
19229+ break;
19230+ default:
19231+ break;
19232+ }
19233+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
19234+ ("END EVENT "));
19235+
19236+ return (0);
19237+} /* SkDrvEvent */
19238+
19239+
19240+/******************************************************************************
19241+ *
19242+ * SkLocalEventQueue() - add event to queue
19243+ *
19244+ * Description:
19245+ * This function adds an event to the event queue and run the
19246+ * SkEventDispatcher. At least Init Level 1 is required to queue events,
19247+ * but will be scheduled add Init Level 2.
19248+ *
19249+ * returns:
19250+ * nothing
19251+ */
19252+void SkLocalEventQueue(
19253+SK_AC *pAC, /* Adapters context */
19254+SK_U32 Class, /* Event Class */
19255+SK_U32 Event, /* Event to be queued */
19256+SK_U32 Param1, /* Event parameter 1 */
19257+SK_U32 Param2, /* Event parameter 2 */
19258+SK_BOOL Dispatcher) /* Dispatcher flag:
19259+ * TRUE == Call SkEventDispatcher
19260+ * FALSE == Don't execute SkEventDispatcher
19261+ */
19262+{
19263+ SK_EVPARA EvPara;
19264+ EvPara.Para32[0] = Param1;
19265+ EvPara.Para32[1] = Param2;
19266+
19267+
19268+ if (Class == SKGE_PNMI) {
19269+ SkPnmiEvent( pAC,
19270+ pAC->IoBase,
19271+ Event,
19272+ EvPara);
19273+ } else {
19274+ SkEventQueue( pAC,
19275+ Class,
19276+ Event,
19277+ EvPara);
19278+ }
19279+
19280+ /* Run the dispatcher */
19281+ if (Dispatcher) {
19282+ SkEventDispatcher(pAC, pAC->IoBase);
19283+ }
19284+
19285+}
19286+
19287+/******************************************************************************
19288+ *
19289+ * SkLocalEventQueue64() - add event to queue (64bit version)
19290+ *
19291+ * Description:
19292+ * This function adds an event to the event queue and run the
19293+ * SkEventDispatcher. At least Init Level 1 is required to queue events,
19294+ * but will be scheduled add Init Level 2.
19295+ *
19296+ * returns:
19297+ * nothing
19298+ */
19299+void SkLocalEventQueue64(
19300+SK_AC *pAC, /* Adapters context */
19301+SK_U32 Class, /* Event Class */
19302+SK_U32 Event, /* Event to be queued */
19303+SK_U64 Param, /* Event parameter */
19304+SK_BOOL Dispatcher) /* Dispatcher flag:
19305+ * TRUE == Call SkEventDispatcher
19306+ * FALSE == Don't execute SkEventDispatcher
19307+ */
19308+{
19309+ SK_EVPARA EvPara;
19310+ EvPara.Para64 = Param;
19311+
19312+
19313+ if (Class == SKGE_PNMI) {
19314+ SkPnmiEvent( pAC,
19315+ pAC->IoBase,
19316+ Event,
19317+ EvPara);
19318+ } else {
19319+ SkEventQueue( pAC,
19320+ Class,
19321+ Event,
19322+ EvPara);
19323+ }
19324
19325- DEV_KFREE_SKB_ANY(pMsg);
19326- break;
19327- case SK_DRV_TIMER:
19328- if (Param.Para32[0] == SK_DRV_MODERATION_TIMER) {
19329- /*
19330- ** expiration of the moderation timer implies that
19331- ** dynamic moderation is to be applied
19332- */
19333- SkDimStartModerationTimer(pAC);
19334- SkDimModerate(pAC);
19335- if (pAC->DynIrqModInfo.DisplayStats) {
19336- SkDimDisplayModerationSettings(pAC);
19337- }
19338- } else if (Param.Para32[0] == SK_DRV_RX_CLEANUP_TIMER) {
19339- /*
19340- ** check if we need to check for descriptors which
19341- ** haven't been handled the last millisecs
19342- */
19343- StartDrvCleanupTimer(pAC);
19344- if (pAC->GIni.GIMacsFound == 2) {
19345- ReceiveIrq(pAC, &pAC->RxPort[1], SK_FALSE);
19346- }
19347- ReceiveIrq(pAC, &pAC->RxPort[0], SK_FALSE);
19348- } else {
19349- printk("Expiration of unknown timer\n");
19350- }
19351- break;
19352- default:
19353- break;
19354+ /* Run the dispatcher */
19355+ if (Dispatcher) {
19356+ SkEventDispatcher(pAC, pAC->IoBase);
19357 }
19358- SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
19359- ("END EVENT "));
19360-
19361- return (0);
19362-} /* SkDrvEvent */
19363+
19364+}
19365
19366
19367 /*****************************************************************************
19368@@ -4408,8 +5894,6 @@
19369
19370 } /* SkErrorLog */
19371
19372-#ifdef SK_DIAG_SUPPORT
19373-
19374 /*****************************************************************************
19375 *
19376 * SkDrvEnterDiagMode - handles DIAG attach request
19377@@ -4424,8 +5908,11 @@
19378 int SkDrvEnterDiagMode(
19379 SK_AC *pAc) /* pointer to adapter context */
19380 {
19381- DEV_NET *pNet = netdev_priv(pAc->dev[0]);
19382- SK_AC *pAC = pNet->pAC;
19383+ SK_AC *pAC = NULL;
19384+ DEV_NET *pNet = NULL;
19385+
19386+ pNet = (DEV_NET *) pAc->dev[0]->priv;
19387+ pAC = pNet->pAC;
19388
19389 SK_MEMCPY(&(pAc->PnmiBackup), &(pAc->PnmiStruct),
19390 sizeof(SK_PNMI_STRUCT_DATA));
19391@@ -4440,8 +5927,9 @@
19392 } else {
19393 pAC->WasIfUp[0] = SK_FALSE;
19394 }
19395- if (pNet != netdev_priv(pAC->dev[1])) {
19396- pNet = netdev_priv(pAC->dev[1]);
19397+
19398+ if (pNet != (DEV_NET *) pAc->dev[1]->priv) {
19399+ pNet = (DEV_NET *) pAc->dev[1]->priv;
19400 if (netif_running(pAC->dev[1])) {
19401 pAC->WasIfUp[1] = SK_TRUE;
19402 pAC->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */
19403@@ -4474,16 +5962,16 @@
19404 sizeof(SK_PNMI_STRUCT_DATA));
19405 pAc->DiagModeActive = DIAG_NOTACTIVE;
19406 pAc->Pnmi.DiagAttached = SK_DIAG_IDLE;
19407- if (pAc->WasIfUp[0] == SK_TRUE) {
19408- pAc->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */
19409+ if (pAc->WasIfUp[0] == SK_TRUE) {
19410+ pAc->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */
19411 DoPrintInterfaceChange = SK_FALSE;
19412- SkDrvInitAdapter(pAc, 0); /* first device */
19413- }
19414- if (pAc->WasIfUp[1] == SK_TRUE) {
19415- pAc->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */
19416+ SkDrvInitAdapter(pAc, 0); /* first device */
19417+ }
19418+ if (pAc->WasIfUp[1] == SK_TRUE) {
19419+ pAc->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */
19420 DoPrintInterfaceChange = SK_FALSE;
19421- SkDrvInitAdapter(pAc, 1); /* second device */
19422- }
19423+ SkDrvInitAdapter(pAc, 1); /* second device */
19424+ }
19425 return(0);
19426 }
19427
19428@@ -4563,11 +6051,20 @@
19429
19430 dev = pAC->dev[devNbr];
19431
19432- /* On Linux 2.6 the network driver does NOT mess with reference
19433- ** counts. The driver MUST be able to be unloaded at any time
19434- ** due to the possibility of hotplug.
19435+ /*
19436+ ** Function SkGeClose() uses MOD_DEC_USE_COUNT (2.2/2.4)
19437+ ** or module_put() (2.6) to decrease the number of users for
19438+ ** a device, but if a device is to be put under control of
19439+ ** the DIAG, that count is OK already and does not need to
19440+ ** be adapted! Hence the opposite MOD_INC_USE_COUNT or
19441+ ** try_module_get() needs to be used again to correct that.
19442 */
19443+ if (!try_module_get(THIS_MODULE)) {
19444+ return (-1);
19445+ }
19446+
19447 if (SkGeClose(dev) != 0) {
19448+ module_put(THIS_MODULE);
19449 return (-1);
19450 }
19451 return (0);
19452@@ -4596,6 +6093,17 @@
19453
19454 if (SkGeOpen(dev) != 0) {
19455 return (-1);
19456+ } else {
19457+ /*
19458+ ** Function SkGeOpen() uses MOD_INC_USE_COUNT (2.2/2.4)
19459+ ** or try_module_get() (2.6) to increase the number of
19460+ ** users for a device, but if a device was just under
19461+ ** control of the DIAG, that count is OK already and
19462+ ** does not need to be adapted! Hence the opposite
19463+ ** MOD_DEC_USE_COUNT or module_put() needs to be used
19464+ ** again to correct that.
19465+ */
19466+ module_put(THIS_MODULE);
19467 }
19468
19469 /*
19470@@ -4608,14 +6116,25 @@
19471
19472 } /* SkDrvInitAdapter */
19473
19474-#endif
19475+static int __init sk98lin_init(void)
19476+{
19477+ return pci_module_init(&sk98lin_driver);
19478+}
19479+
19480+static void __exit sk98lin_cleanup(void)
19481+{
19482+ pci_unregister_driver(&sk98lin_driver);
19483+}
19484+
19485+module_init(sk98lin_init);
19486+module_exit(sk98lin_cleanup);
19487+
19488
19489 #ifdef DEBUG
19490 /****************************************************************************/
19491 /* "debug only" section *****************************************************/
19492 /****************************************************************************/
19493
19494-
19495 /*****************************************************************************
19496 *
19497 * DumpMsg - print a frame
19498@@ -4626,9 +6145,11 @@
19499 * Returns: N/A
19500 *
19501 */
19502-static void DumpMsg(struct sk_buff *skb, char *str)
19503+static void DumpMsg(
19504+struct sk_buff *skb, /* linux' socket buffer */
19505+char *str) /* additional msg string */
19506 {
19507- int msglen;
19508+ int msglen = (skb->len > 64) ? 64 : skb->len;
19509
19510 if (skb == NULL) {
19511 printk("DumpMsg(): NULL-Message\n");
19512@@ -4640,19 +6161,14 @@
19513 return;
19514 }
19515
19516- msglen = skb->len;
19517- if (msglen > 64)
19518- msglen = 64;
19519-
19520- printk("--- Begin of message from %s , len %d (from %d) ----\n", str, msglen, skb->len);
19521-
19522+ printk("DumpMsg: PhysPage: %p\n",
19523+ page_address(virt_to_page(skb->data)));
19524+ printk("--- Begin of message from %s , len %d (from %d) ----\n",
19525+ str, msglen, skb->len);
19526 DumpData((char *)skb->data, msglen);
19527-
19528 printk("------- End of message ---------\n");
19529 } /* DumpMsg */
19530
19531-
19532-
19533 /*****************************************************************************
19534 *
19535 * DumpData - print a data area
19536@@ -4664,23 +6180,22 @@
19537 * Returns: N/A
19538 *
19539 */
19540-static void DumpData(char *p, int size)
19541-{
19542-register int i;
19543-int haddr, addr;
19544-char hex_buffer[180];
19545-char asc_buffer[180];
19546-char HEXCHAR[] = "0123456789ABCDEF";
19547-
19548- addr = 0;
19549- haddr = 0;
19550- hex_buffer[0] = 0;
19551- asc_buffer[0] = 0;
19552+static void DumpData(
19553+char *p, /* pointer to area containing the data */
19554+int size) /* the size of that data area in bytes */
19555+{
19556+ register int i;
19557+ int haddr = 0, addr = 0;
19558+ char hex_buffer[180] = { '\0' };
19559+ char asc_buffer[180] = { '\0' };
19560+ char HEXCHAR[] = "0123456789ABCDEF";
19561+
19562 for (i=0; i < size; ) {
19563- if (*p >= '0' && *p <='z')
19564+ if (*p >= '0' && *p <='z') {
19565 asc_buffer[addr] = *p;
19566- else
19567+ } else {
19568 asc_buffer[addr] = '.';
19569+ }
19570 addr++;
19571 asc_buffer[addr] = 0;
19572 hex_buffer[haddr] = HEXCHAR[(*p & 0xf0) >> 4];
19573@@ -4706,27 +6221,24 @@
19574 * DumpLong - print a data area as long values
19575 *
19576 * Description:
19577- * This function prints a area of data to the system logfile/to the
19578+ * This function prints a long variable to the system logfile/to the
19579 * console.
19580 *
19581 * Returns: N/A
19582 *
19583 */
19584-static void DumpLong(char *pc, int size)
19585-{
19586-register int i;
19587-int haddr, addr;
19588-char hex_buffer[180];
19589-char asc_buffer[180];
19590-char HEXCHAR[] = "0123456789ABCDEF";
19591-long *p;
19592-int l;
19593-
19594- addr = 0;
19595- haddr = 0;
19596- hex_buffer[0] = 0;
19597- asc_buffer[0] = 0;
19598- p = (long*) pc;
19599+static void DumpLong(
19600+char *pc, /* location of the variable to print */
19601+int size) /* how large is the variable? */
19602+{
19603+ register int i;
19604+ int haddr = 0, addr = 0;
19605+ char hex_buffer[180] = { '\0' };
19606+ char asc_buffer[180] = { '\0' };
19607+ char HEXCHAR[] = "0123456789ABCDEF";
19608+ long *p = (long*) pc;
19609+ int l;
19610+
19611 for (i=0; i < size; ) {
19612 l = (long) *p;
19613 hex_buffer[haddr] = HEXCHAR[(l >> 28) & 0xf];
19614@@ -4760,386 +6272,9 @@
19615
19616 #endif
19617
19618-static int __devinit skge_probe_one(struct pci_dev *pdev,
19619- const struct pci_device_id *ent)
19620-{
19621- SK_AC *pAC;
19622- DEV_NET *pNet = NULL;
19623- struct net_device *dev = NULL;
19624- static int boards_found = 0;
19625- int error = -ENODEV;
19626- int using_dac = 0;
19627- char DeviceStr[80];
19628-
19629- if (pci_enable_device(pdev))
19630- goto out;
19631-
19632- /* Configure DMA attributes. */
19633- if (sizeof(dma_addr_t) > sizeof(u32) &&
19634- !(error = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
19635- using_dac = 1;
19636- error = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
19637- if (error < 0) {
19638- printk(KERN_ERR "sk98lin %s unable to obtain 64 bit DMA "
19639- "for consistent allocations\n", pci_name(pdev));
19640- goto out_disable_device;
19641- }
19642- } else {
19643- error = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
19644- if (error) {
19645- printk(KERN_ERR "sk98lin %s no usable DMA configuration\n",
19646- pci_name(pdev));
19647- goto out_disable_device;
19648- }
19649- }
19650-
19651- error = -ENOMEM;
19652- dev = alloc_etherdev(sizeof(DEV_NET));
19653- if (!dev) {
19654- printk(KERN_ERR "sk98lin: unable to allocate etherdev "
19655- "structure!\n");
19656- goto out_disable_device;
19657- }
19658-
19659- pNet = netdev_priv(dev);
19660- pNet->pAC = kzalloc(sizeof(SK_AC), GFP_KERNEL);
19661- if (!pNet->pAC) {
19662- printk(KERN_ERR "sk98lin: unable to allocate adapter "
19663- "structure!\n");
19664- goto out_free_netdev;
19665- }
19666-
19667- pAC = pNet->pAC;
19668- pAC->PciDev = pdev;
19669-
19670- pAC->dev[0] = dev;
19671- pAC->dev[1] = dev;
19672- pAC->CheckQueue = SK_FALSE;
19673-
19674- dev->irq = pdev->irq;
19675-
19676- error = SkGeInitPCI(pAC);
19677- if (error) {
19678- printk(KERN_ERR "sk98lin: PCI setup failed: %i\n", error);
19679- goto out_free_netdev;
19680- }
19681-
19682- SET_MODULE_OWNER(dev);
19683- dev->open = &SkGeOpen;
19684- dev->stop = &SkGeClose;
19685- dev->hard_start_xmit = &SkGeXmit;
19686- dev->get_stats = &SkGeStats;
19687- dev->set_multicast_list = &SkGeSetRxMode;
19688- dev->set_mac_address = &SkGeSetMacAddr;
19689- dev->do_ioctl = &SkGeIoctl;
19690- dev->change_mtu = &SkGeChangeMtu;
19691-#ifdef CONFIG_NET_POLL_CONTROLLER
19692- dev->poll_controller = &SkGePollController;
19693-#endif
19694- SET_NETDEV_DEV(dev, &pdev->dev);
19695- SET_ETHTOOL_OPS(dev, &SkGeEthtoolOps);
19696-
19697- /* Use only if yukon hardware */
19698- if (pAC->ChipsetType) {
19699-#ifdef USE_SK_TX_CHECKSUM
19700- dev->features |= NETIF_F_IP_CSUM;
19701-#endif
19702-#ifdef SK_ZEROCOPY
19703- dev->features |= NETIF_F_SG;
19704-#endif
19705-#ifdef USE_SK_RX_CHECKSUM
19706- pAC->RxPort[0].RxCsum = 1;
19707-#endif
19708- }
19709-
19710- if (using_dac)
19711- dev->features |= NETIF_F_HIGHDMA;
19712-
19713- pAC->Index = boards_found++;
19714-
19715- error = SkGeBoardInit(dev, pAC);
19716- if (error)
19717- goto out_free_netdev;
19718-
19719- /* Read Adapter name from VPD */
19720- if (ProductStr(pAC, DeviceStr, sizeof(DeviceStr)) != 0) {
19721- error = -EIO;
19722- printk(KERN_ERR "sk98lin: Could not read VPD data.\n");
19723- goto out_free_resources;
19724- }
19725-
19726- /* Register net device */
19727- error = register_netdev(dev);
19728- if (error) {
19729- printk(KERN_ERR "sk98lin: Could not register device.\n");
19730- goto out_free_resources;
19731- }
19732-
19733- /* Print adapter specific string from vpd */
19734- printk("%s: %s\n", dev->name, DeviceStr);
19735-
19736- /* Print configuration settings */
19737- printk(" PrefPort:%c RlmtMode:%s\n",
19738- 'A' + pAC->Rlmt.Net[0].Port[pAC->Rlmt.Net[0].PrefPort]->PortNumber,
19739- (pAC->RlmtMode==0) ? "Check Link State" :
19740- ((pAC->RlmtMode==1) ? "Check Link State" :
19741- ((pAC->RlmtMode==3) ? "Check Local Port" :
19742- ((pAC->RlmtMode==7) ? "Check Segmentation" :
19743- ((pAC->RlmtMode==17) ? "Dual Check Link State" :"Error")))));
19744-
19745- SkGeYellowLED(pAC, pAC->IoBase, 1);
19746-
19747- memcpy(&dev->dev_addr, &pAC->Addr.Net[0].CurrentMacAddress, 6);
19748- memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
19749-
19750- pNet->PortNr = 0;
19751- pNet->NetNr = 0;
19752-
19753- boards_found++;
19754-
19755- pci_set_drvdata(pdev, dev);
19756-
19757- /* More then one port found */
19758- if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
19759- dev = alloc_etherdev(sizeof(DEV_NET));
19760- if (!dev) {
19761- printk(KERN_ERR "sk98lin: unable to allocate etherdev "
19762- "structure!\n");
19763- goto single_port;
19764- }
19765-
19766- pNet = netdev_priv(dev);
19767- pNet->PortNr = 1;
19768- pNet->NetNr = 1;
19769- pNet->pAC = pAC;
19770-
19771- dev->open = &SkGeOpen;
19772- dev->stop = &SkGeClose;
19773- dev->hard_start_xmit = &SkGeXmit;
19774- dev->get_stats = &SkGeStats;
19775- dev->set_multicast_list = &SkGeSetRxMode;
19776- dev->set_mac_address = &SkGeSetMacAddr;
19777- dev->do_ioctl = &SkGeIoctl;
19778- dev->change_mtu = &SkGeChangeMtu;
19779- SET_NETDEV_DEV(dev, &pdev->dev);
19780- SET_ETHTOOL_OPS(dev, &SkGeEthtoolOps);
19781-
19782- if (pAC->ChipsetType) {
19783-#ifdef USE_SK_TX_CHECKSUM
19784- dev->features |= NETIF_F_IP_CSUM;
19785-#endif
19786-#ifdef SK_ZEROCOPY
19787- dev->features |= NETIF_F_SG;
19788-#endif
19789-#ifdef USE_SK_RX_CHECKSUM
19790- pAC->RxPort[1].RxCsum = 1;
19791-#endif
19792- }
19793-
19794- if (using_dac)
19795- dev->features |= NETIF_F_HIGHDMA;
19796-
19797- error = register_netdev(dev);
19798- if (error) {
19799- printk(KERN_ERR "sk98lin: Could not register device"
19800- " for second port. (%d)\n", error);
19801- free_netdev(dev);
19802- goto single_port;
19803- }
19804-
19805- pAC->dev[1] = dev;
19806- memcpy(&dev->dev_addr,
19807- &pAC->Addr.Net[1].CurrentMacAddress, 6);
19808- memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
19809-
19810- printk("%s: %s\n", dev->name, DeviceStr);
19811- printk(" PrefPort:B RlmtMode:Dual Check Link State\n");
19812- }
19813-
19814-single_port:
19815-
19816- /* Save the hardware revision */
19817- pAC->HWRevision = (((pAC->GIni.GIPciHwRev >> 4) & 0x0F)*10) +
19818- (pAC->GIni.GIPciHwRev & 0x0F);
19819-
19820- /* Set driver globals */
19821- pAC->Pnmi.pDriverFileName = DRIVER_FILE_NAME;
19822- pAC->Pnmi.pDriverReleaseDate = DRIVER_REL_DATE;
19823-
19824- memset(&pAC->PnmiBackup, 0, sizeof(SK_PNMI_STRUCT_DATA));
19825- memcpy(&pAC->PnmiBackup, &pAC->PnmiStruct, sizeof(SK_PNMI_STRUCT_DATA));
19826-
19827- return 0;
19828-
19829- out_free_resources:
19830- FreeResources(dev);
19831- out_free_netdev:
19832- free_netdev(dev);
19833- out_disable_device:
19834- pci_disable_device(pdev);
19835- out:
19836- return error;
19837-}
19838-
19839-static void __devexit skge_remove_one(struct pci_dev *pdev)
19840-{
19841- struct net_device *dev = pci_get_drvdata(pdev);
19842- DEV_NET *pNet = netdev_priv(dev);
19843- SK_AC *pAC = pNet->pAC;
19844- struct net_device *otherdev = pAC->dev[1];
19845-
19846- unregister_netdev(dev);
19847-
19848- SkGeYellowLED(pAC, pAC->IoBase, 0);
19849-
19850- if (pAC->BoardLevel == SK_INIT_RUN) {
19851- SK_EVPARA EvPara;
19852- unsigned long Flags;
19853-
19854- /* board is still alive */
19855- spin_lock_irqsave(&pAC->SlowPathLock, Flags);
19856- EvPara.Para32[0] = 0;
19857- EvPara.Para32[1] = -1;
19858- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
19859- EvPara.Para32[0] = 1;
19860- EvPara.Para32[1] = -1;
19861- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
19862- SkEventDispatcher(pAC, pAC->IoBase);
19863- /* disable interrupts */
19864- SK_OUT32(pAC->IoBase, B0_IMSK, 0);
19865- SkGeDeInit(pAC, pAC->IoBase);
19866- spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
19867- pAC->BoardLevel = SK_INIT_DATA;
19868- /* We do NOT check here, if IRQ was pending, of course*/
19869- }
19870-
19871- if (pAC->BoardLevel == SK_INIT_IO) {
19872- /* board is still alive */
19873- SkGeDeInit(pAC, pAC->IoBase);
19874- pAC->BoardLevel = SK_INIT_DATA;
19875- }
19876-
19877- FreeResources(dev);
19878- free_netdev(dev);
19879- if (otherdev != dev)
19880- free_netdev(otherdev);
19881- kfree(pAC);
19882-}
19883-
19884-#ifdef CONFIG_PM
19885-static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
19886-{
19887- struct net_device *dev = pci_get_drvdata(pdev);
19888- DEV_NET *pNet = netdev_priv(dev);
19889- SK_AC *pAC = pNet->pAC;
19890- struct net_device *otherdev = pAC->dev[1];
19891-
19892- if (netif_running(dev)) {
19893- netif_carrier_off(dev);
19894- DoPrintInterfaceChange = SK_FALSE;
19895- SkDrvDeInitAdapter(pAC, 0); /* performs SkGeClose */
19896- netif_device_detach(dev);
19897- }
19898- if (otherdev != dev) {
19899- if (netif_running(otherdev)) {
19900- netif_carrier_off(otherdev);
19901- DoPrintInterfaceChange = SK_FALSE;
19902- SkDrvDeInitAdapter(pAC, 1); /* performs SkGeClose */
19903- netif_device_detach(otherdev);
19904- }
19905- }
19906-
19907- pci_save_state(pdev);
19908- pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
19909- if (pAC->AllocFlag & SK_ALLOC_IRQ) {
19910- free_irq(dev->irq, dev);
19911- }
19912- pci_disable_device(pdev);
19913- pci_set_power_state(pdev, pci_choose_state(pdev, state));
19914-
19915- return 0;
19916-}
19917-
19918-static int skge_resume(struct pci_dev *pdev)
19919-{
19920- struct net_device *dev = pci_get_drvdata(pdev);
19921- DEV_NET *pNet = netdev_priv(dev);
19922- SK_AC *pAC = pNet->pAC;
19923- struct net_device *otherdev = pAC->dev[1];
19924- int ret;
19925-
19926- pci_set_power_state(pdev, PCI_D0);
19927- pci_restore_state(pdev);
19928- pci_enable_device(pdev);
19929- pci_set_master(pdev);
19930- if (pAC->GIni.GIMacsFound == 2)
19931- ret = request_irq(dev->irq, SkGeIsr, SA_SHIRQ, "sk98lin", dev);
19932- else
19933- ret = request_irq(dev->irq, SkGeIsrOnePort, SA_SHIRQ, "sk98lin", dev);
19934- if (ret) {
19935- printk(KERN_WARNING "sk98lin: unable to acquire IRQ %d\n", dev->irq);
19936- pAC->AllocFlag &= ~SK_ALLOC_IRQ;
19937- dev->irq = 0;
19938- pci_disable_device(pdev);
19939- return -EBUSY;
19940- }
19941-
19942- netif_device_attach(dev);
19943- if (netif_running(dev)) {
19944- DoPrintInterfaceChange = SK_FALSE;
19945- SkDrvInitAdapter(pAC, 0); /* first device */
19946- }
19947- if (otherdev != dev) {
19948- netif_device_attach(otherdev);
19949- if (netif_running(otherdev)) {
19950- DoPrintInterfaceChange = SK_FALSE;
19951- SkDrvInitAdapter(pAC, 1); /* second device */
19952- }
19953- }
19954-
19955- return 0;
19956-}
19957-#else
19958-#define skge_suspend NULL
19959-#define skge_resume NULL
19960-#endif
19961-
19962-static struct pci_device_id skge_pci_tbl[] = {
19963- { PCI_VENDOR_ID_3COM, 0x1700, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
19964- { PCI_VENDOR_ID_3COM, 0x80eb, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
19965- { PCI_VENDOR_ID_SYSKONNECT, 0x4300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
19966- { PCI_VENDOR_ID_SYSKONNECT, 0x4320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
19967-/* DLink card does not have valid VPD so this driver gags
19968- * { PCI_VENDOR_ID_DLINK, 0x4c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
19969- */
19970- { PCI_VENDOR_ID_MARVELL, 0x4320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
19971- { PCI_VENDOR_ID_MARVELL, 0x5005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
19972- { PCI_VENDOR_ID_CNET, 0x434e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
19973- { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
19974- { PCI_VENDOR_ID_LINKSYS, 0x1064, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
19975- { 0 }
19976-};
19977-
19978-MODULE_DEVICE_TABLE(pci, skge_pci_tbl);
19979-
19980-static struct pci_driver skge_driver = {
19981- .name = "sk98lin",
19982- .id_table = skge_pci_tbl,
19983- .probe = skge_probe_one,
19984- .remove = __devexit_p(skge_remove_one),
19985- .suspend = skge_suspend,
19986- .resume = skge_resume,
19987-};
19988-
19989-static int __init skge_init(void)
19990-{
19991- return pci_module_init(&skge_driver);
19992-}
19993-
19994-static void __exit skge_exit(void)
19995-{
19996- pci_unregister_driver(&skge_driver);
19997-}
19998+/*******************************************************************************
19999+ *
20000+ * End of file
20001+ *
20002+ ******************************************************************************/
20003
20004-module_init(skge_init);
20005-module_exit(skge_exit);
20006diff -urN linux-2.6.17.orig/drivers/net/sk98lin/skgehwt.c linux-2.6.17/drivers/net/sk98lin/skgehwt.c
20007--- linux-2.6.17.orig/drivers/net/sk98lin/skgehwt.c 2006-06-22 13:17:16.000000000 +0200
20008+++ linux-2.6.17/drivers/net/sk98lin/skgehwt.c 2006-04-27 11:43:44.000000000 +0200
20009@@ -2,8 +2,8 @@
20010 *
20011 * Name: skgehwt.c
20012 * Project: Gigabit Ethernet Adapters, Event Scheduler Module
20013- * Version: $Revision$
20014- * Date: $Date$
20015+ * Version: $Revision$
20016+ * Date: $Date$
20017 * Purpose: Hardware Timer
20018 *
20019 ******************************************************************************/
20020@@ -11,7 +11,7 @@
20021 /******************************************************************************
20022 *
20023 * (C)Copyright 1998-2002 SysKonnect GmbH.
20024- * (C)Copyright 2002-2003 Marvell.
20025+ * (C)Copyright 2002-2004 Marvell.
20026 *
20027 * This program is free software; you can redistribute it and/or modify
20028 * it under the terms of the GNU General Public License as published by
20029@@ -27,7 +27,7 @@
20030 */
20031 #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
20032 static const char SysKonnectFileId[] =
20033- "@(#) $Id$ (C) Marvell.";
20034+ "@(#) $Id$ (C) Marvell.";
20035 #endif
20036
20037 #include "h/skdrv1st.h" /* Driver Specific Definitions */
20038@@ -44,10 +44,10 @@
20039 /*
20040 * Prototypes of local functions.
20041 */
20042-#define SK_HWT_MAX (65000)
20043+#define SK_HWT_MAX 65000UL * 160 /* ca. 10 sec. */
20044
20045 /* correction factor */
20046-#define SK_HWT_FAC (1000 * (SK_U32)pAC->GIni.GIHstClkFact / 100)
20047+#define SK_HWT_FAC (10 * (SK_U32)pAC->GIni.GIHstClkFact / 16)
20048
20049 /*
20050 * Initialize hardware timer.
20051@@ -73,29 +73,21 @@
20052 void SkHwtStart(
20053 SK_AC *pAC, /* Adapters context */
20054 SK_IOC Ioc, /* IoContext */
20055-SK_U32 Time) /* Time in units of 16us to load the timer with. */
20056+SK_U32 Time) /* Time in usec to load the timer */
20057 {
20058- SK_U32 Cnt;
20059-
20060 if (Time > SK_HWT_MAX)
20061 Time = SK_HWT_MAX;
20062
20063 pAC->Hwt.TStart = Time;
20064 pAC->Hwt.TStop = 0L;
20065
20066- Cnt = Time;
20067-
20068- /*
20069- * if time < 16 us
20070- * time = 16 us
20071- */
20072- if (!Cnt) {
20073- Cnt++;
20074+ if (!Time) {
20075+ Time = 1L;
20076 }
20077
20078- SK_OUT32(Ioc, B2_TI_INI, Cnt * SK_HWT_FAC);
20079-
20080- SK_OUT16(Ioc, B2_TI_CTRL, TIM_START); /* Start timer. */
20081+ SK_OUT32(Ioc, B2_TI_INI, Time * SK_HWT_FAC);
20082+
20083+ SK_OUT16(Ioc, B2_TI_CTRL, TIM_START); /* Start timer */
20084
20085 pAC->Hwt.TActive = SK_TRUE;
20086 }
20087@@ -109,13 +101,12 @@
20088 SK_IOC Ioc) /* IoContext */
20089 {
20090 SK_OUT16(Ioc, B2_TI_CTRL, TIM_STOP);
20091-
20092+
20093 SK_OUT16(Ioc, B2_TI_CTRL, TIM_CLR_IRQ);
20094
20095 pAC->Hwt.TActive = SK_FALSE;
20096 }
20097
20098-
20099 /*
20100 * Stop hardware timer and read time elapsed since last start.
20101 *
20102@@ -129,6 +120,9 @@
20103 {
20104 SK_U32 TRead;
20105 SK_U32 IStatus;
20106+ SK_U32 TimerInt;
20107+
20108+ TimerInt = CHIP_ID_YUKON_2(pAC) ? Y2_IS_TIMINT : IS_TIMINT;
20109
20110 if (pAC->Hwt.TActive) {
20111
20112@@ -139,15 +133,15 @@
20113
20114 SK_IN32(Ioc, B0_ISRC, &IStatus);
20115
20116- /* Check if timer expired (or wraped around) */
20117- if ((TRead > pAC->Hwt.TStart) || (IStatus & IS_TIMINT)) {
20118-
20119+ /* Check if timer expired (or wrapped around) */
20120+ if ((TRead > pAC->Hwt.TStart) || ((IStatus & TimerInt) != 0)) {
20121+
20122 SkHwtStop(pAC, Ioc);
20123-
20124+
20125 pAC->Hwt.TStop = pAC->Hwt.TStart;
20126 }
20127 else {
20128-
20129+
20130 pAC->Hwt.TStop = pAC->Hwt.TStart - TRead;
20131 }
20132 }
20133@@ -162,9 +156,9 @@
20134 SK_IOC Ioc) /* IoContext */
20135 {
20136 SkHwtStop(pAC, Ioc);
20137-
20138+
20139 pAC->Hwt.TStop = pAC->Hwt.TStart;
20140-
20141+
20142 SkTimerDone(pAC, Ioc);
20143 }
20144
20145diff -urN linux-2.6.17.orig/drivers/net/sk98lin/skgeinit.c linux-2.6.17/drivers/net/sk98lin/skgeinit.c
20146--- linux-2.6.17.orig/drivers/net/sk98lin/skgeinit.c 2006-06-22 13:17:16.000000000 +0200
20147+++ linux-2.6.17/drivers/net/sk98lin/skgeinit.c 2006-04-27 11:43:44.000000000 +0200
20148@@ -2,23 +2,24 @@
20149 *
20150 * Name: skgeinit.c
20151 * Project: Gigabit Ethernet Adapters, Common Modules
20152- * Version: $Revision$
20153- * Date: $Date$
20154+ * Version: $Revision$
20155+ * Date: $Date$
20156 * Purpose: Contains functions to initialize the adapter
20157 *
20158 ******************************************************************************/
20159
20160 /******************************************************************************
20161 *
20162+ * LICENSE:
20163 * (C)Copyright 1998-2002 SysKonnect.
20164- * (C)Copyright 2002-2003 Marvell.
20165+ * (C)Copyright 2002-2006 Marvell.
20166 *
20167 * This program is free software; you can redistribute it and/or modify
20168 * it under the terms of the GNU General Public License as published by
20169 * the Free Software Foundation; either version 2 of the License, or
20170 * (at your option) any later version.
20171- *
20172 * The information in this file is provided "AS IS" without warranty.
20173+ * /LICENSE
20174 *
20175 ******************************************************************************/
20176
20177@@ -31,7 +32,7 @@
20178
20179 #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
20180 static const char SysKonnectFileId[] =
20181- "@(#) $Id$ (C) Marvell.";
20182+ "@(#) $Id$ (C) Marvell.";
20183 #endif
20184
20185 struct s_QOffTab {
20186@@ -39,6 +40,7 @@
20187 int XsQOff; /* Sync Tx Queue Address Offset */
20188 int XaQOff; /* Async Tx Queue Address Offset */
20189 };
20190+
20191 static struct s_QOffTab QOffTab[] = {
20192 {Q_R1, Q_XS1, Q_XA1}, {Q_R2, Q_XS2, Q_XA2}
20193 };
20194@@ -57,6 +59,125 @@
20195 #endif
20196 };
20197
20198+#ifndef SK_SLIM
20199+/******************************************************************************
20200+ *
20201+ * SkGePortVlan() - Enable / Disable VLAN support
20202+ *
20203+ * Description:
20204+ * Enable or disable the VLAN support of the selected port.
20205+ * The new configuration is *not* saved over any SkGeStopPort() and
20206+ * SkGeInitPort() calls.
20207+ * Currently this function is only supported on Yukon-2/EC adapters.
20208+ *
20209+ * Returns:
20210+ * nothing
20211+ */
20212+void SkGePortVlan(
20213+SK_AC *pAC, /* Adapter Context */
20214+SK_IOC IoC, /* I/O Context */
20215+int Port, /* Port number */
20216+SK_BOOL Enable) /* Flag */
20217+{
20218+ SK_U32 RxCtrl;
20219+ SK_U32 TxCtrl;
20220+
20221+ if (CHIP_ID_YUKON_2(pAC)) {
20222+ if (Enable) {
20223+ RxCtrl = RX_VLAN_STRIP_ON;
20224+ TxCtrl = TX_VLAN_TAG_ON;
20225+ }
20226+ else {
20227+ RxCtrl = RX_VLAN_STRIP_OFF;
20228+ TxCtrl = TX_VLAN_TAG_OFF;
20229+ }
20230+
20231+ SK_OUT32(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), RxCtrl);
20232+ SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), TxCtrl);
20233+ }
20234+} /* SkGePortVlan */
20235+
20236+
20237+/******************************************************************************
20238+ *
20239+ * SkGeRxRss() - Enable / Disable RSS Hash Calculation
20240+ *
20241+ * Description:
20242+ * Enable or disable the RSS hash calculation of the selected port.
20243+ * The new configuration is *not* saved over any SkGeStopPort() and
20244+ * SkGeInitPort() calls.
20245+ * Currently this function is only supported on Yukon-2/EC adapters.
20246+ *
20247+ * Returns:
20248+ * nothing
20249+ */
20250+void SkGeRxRss(
20251+SK_AC *pAC, /* Adapter Context */
20252+SK_IOC IoC, /* I/O Context */
20253+int Port, /* Port number */
20254+SK_BOOL Enable) /* Flag */
20255+{
20256+ if (CHIP_ID_YUKON_2(pAC)) {
20257+ SK_OUT32(IoC, Q_ADDR(pAC->GIni.GP[Port].PRxQOff, Q_CSR),
20258+ Enable ? BMU_ENA_RX_RSS_HASH : BMU_DIS_RX_RSS_HASH);
20259+ }
20260+} /* SkGeRxRss */
20261+
20262+
20263+/******************************************************************************
20264+ *
20265+ * SkGeRxCsum() - Enable / Disable Receive Checksum
20266+ *
20267+ * Description:
20268+ * Enable or disable the checksum of the selected port.
20269+ * The new configuration is *not* saved over any SkGeStopPort() and
20270+ * SkGeInitPort() calls.
20271+ * Currently this function is only supported on Yukon-2/EC adapters.
20272+ *
20273+ * Returns:
20274+ * nothing
20275+ */
20276+void SkGeRxCsum(
20277+SK_AC *pAC, /* Adapter Context */
20278+SK_IOC IoC, /* I/O Context */
20279+int Port, /* Port number */
20280+SK_BOOL Enable) /* Flag */
20281+{
20282+ if (CHIP_ID_YUKON_2(pAC)) {
20283+ SK_OUT32(IoC, Q_ADDR(pAC->GIni.GP[Port].PRxQOff, Q_CSR),
20284+ Enable ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
20285+ }
20286+} /* SkGeRxCsum */
20287+#endif /* !SK_SLIM */
20288+
20289+/******************************************************************************
20290+ *
20291+ * SkGePollRxD() - Enable / Disable Descriptor Polling of RxD Ring
20292+ *
20293+ * Description:
20294+ * Enable or disable the descriptor polling of the receive descriptor
20295+ * ring (RxD) for port 'Port'.
20296+ * The new configuration is *not* saved over any SkGeStopPort() and
20297+ * SkGeInitPort() calls.
20298+ *
20299+ * Returns:
20300+ * nothing
20301+ */
20302+void SkGePollRxD(
20303+SK_AC *pAC, /* Adapter Context */
20304+SK_IOC IoC, /* I/O Context */
20305+int Port, /* Port Index (MAC_1 + n) */
20306+SK_BOOL PollRxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */
20307+{
20308+ SK_GEPORT *pPrt;
20309+
20310+ pPrt = &pAC->GIni.GP[Port];
20311+
20312+ SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), (SK_U32)((PollRxD) ?
20313+ CSR_ENA_POL : CSR_DIS_POL));
20314+} /* SkGePollRxD */
20315+
20316+
20317 /******************************************************************************
20318 *
20319 * SkGePollTxD() - Enable / Disable Descriptor Polling of TxD Rings
20320@@ -71,8 +192,8 @@
20321 * nothing
20322 */
20323 void SkGePollTxD(
20324-SK_AC *pAC, /* adapter context */
20325-SK_IOC IoC, /* IO context */
20326+SK_AC *pAC, /* Adapter Context */
20327+SK_IOC IoC, /* I/O Context */
20328 int Port, /* Port Index (MAC_1 + n) */
20329 SK_BOOL PollTxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */
20330 {
20331@@ -86,13 +207,13 @@
20332 if (pPrt->PXSQSize != 0) {
20333 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), DWord);
20334 }
20335-
20336+
20337 if (pPrt->PXAQSize != 0) {
20338 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), DWord);
20339 }
20340 } /* SkGePollTxD */
20341
20342-
20343+#ifndef SK_SLIM
20344 /******************************************************************************
20345 *
20346 * SkGeYellowLED() - Switch the yellow LED on or off.
20347@@ -107,20 +228,30 @@
20348 * nothing
20349 */
20350 void SkGeYellowLED(
20351-SK_AC *pAC, /* adapter context */
20352-SK_IOC IoC, /* IO context */
20353+SK_AC *pAC, /* Adapter Context */
20354+SK_IOC IoC, /* I/O Context */
20355 int State) /* yellow LED state, 0 = OFF, 0 != ON */
20356 {
20357+ int LedReg;
20358+
20359+ if (CHIP_ID_YUKON_2(pAC)) {
20360+ /* different mapping on Yukon-2 */
20361+ LedReg = B0_CTST + 1;
20362+ }
20363+ else {
20364+ LedReg = B0_LED;
20365+ }
20366+
20367 if (State == 0) {
20368- /* Switch yellow LED OFF */
20369- SK_OUT8(IoC, B0_LED, LED_STAT_OFF);
20370+ /* Switch state LED OFF */
20371+ SK_OUT8(IoC, LedReg, LED_STAT_OFF);
20372 }
20373 else {
20374- /* Switch yellow LED ON */
20375- SK_OUT8(IoC, B0_LED, LED_STAT_ON);
20376+ /* Switch state LED ON */
20377+ SK_OUT8(IoC, LedReg, LED_STAT_ON);
20378 }
20379 } /* SkGeYellowLED */
20380-
20381+#endif /* !SK_SLIM */
20382
20383 #if (!defined(SK_SLIM) || defined(GENESIS))
20384 /******************************************************************************
20385@@ -141,8 +272,8 @@
20386 * nothing
20387 */
20388 void SkGeXmitLED(
20389-SK_AC *pAC, /* adapter context */
20390-SK_IOC IoC, /* IO context */
20391+SK_AC *pAC, /* Adapter Context */
20392+SK_IOC IoC, /* I/O Context */
20393 int Led, /* offset to the LED Init Value register */
20394 int Mode) /* Mode may be SK_LED_DIS, SK_LED_ENA, SK_LED_TST */
20395 {
20396@@ -167,18 +298,17 @@
20397 */
20398 SK_OUT32(IoC, Led + XMIT_LED_CNT, 0);
20399 SK_OUT8(IoC, Led + XMIT_LED_TST, LED_T_OFF);
20400- break;
20401 }
20402-
20403+
20404 /*
20405- * 1000BT: The Transmit LED is driven by the PHY.
20406+ * 1000BT: the Transmit LED is driven by the PHY.
20407 * But the default LED configuration is used for
20408 * Level One and Broadcom PHYs.
20409- * (Broadcom: It may be that PHY_B_PEC_EN_LTR has to be set.)
20410- * (In this case it has to be added here. But we will see. XXX)
20411+ * (Broadcom: It may be that PHY_B_PEC_EN_LTR has to be set.
20412+ * In this case it has to be added here.)
20413 */
20414 } /* SkGeXmitLED */
20415-#endif /* !SK_SLIM || GENESIS */
20416+#endif /* !SK_SLIM || GENESIS */
20417
20418
20419 /******************************************************************************
20420@@ -199,7 +329,7 @@
20421 * 1: configuration error
20422 */
20423 static int DoCalcAddr(
20424-SK_AC *pAC, /* adapter context */
20425+SK_AC *pAC, /* Adapter Context */
20426 SK_GEPORT SK_FAR *pPrt, /* port index */
20427 int QuSize, /* size of the queue to configure in kB */
20428 SK_U32 SK_FAR *StartVal, /* start value for address calculation */
20429@@ -236,12 +366,35 @@
20430
20431 /******************************************************************************
20432 *
20433+ * SkGeRoundQueueSize() - Round the given queue size to the adpaters QZ units
20434+ *
20435+ * Description:
20436+ * This function rounds the given queue size in kBs to adapter specific
20437+ * queue size units (Genesis and Yukon: 8 kB, Yukon-2/EC: 1 kB).
20438+ *
20439+ * Returns:
20440+ * the rounded queue size in kB
20441+ */
20442+static int SkGeRoundQueueSize(
20443+SK_AC *pAC, /* Adapter Context */
20444+int QueueSizeKB) /* Queue size in kB */
20445+{
20446+ int QueueSizeSteps;
20447+
20448+ QueueSizeSteps = (CHIP_ID_YUKON_2(pAC)) ? QZ_STEP_Y2 : QZ_STEP;
20449+
20450+ return((QueueSizeKB + QueueSizeSteps - 1) & ~(QueueSizeSteps - 1));
20451+} /* SkGeRoundQueueSize */
20452+
20453+
20454+/******************************************************************************
20455+ *
20456 * SkGeInitAssignRamToQueues() - allocate default queue sizes
20457 *
20458 * Description:
20459 * This function assigns the memory to the different queues and ports.
20460 * When DualNet is set to SK_TRUE all ports get the same amount of memory.
20461- * Otherwise the first port gets most of the memory and all the
20462+ * Otherwise the first port gets most of the memory and all the
20463 * other ports just the required minimum.
20464 * This function can only be called when pAC->GIni.GIRamSize and
20465 * pAC->GIni.GIMacsFound have been initialized, usually this happens
20466@@ -254,102 +407,146 @@
20467 */
20468
20469 int SkGeInitAssignRamToQueues(
20470-SK_AC *pAC, /* Adapter context */
20471+SK_AC *pAC, /* Adapter Context */
20472 int ActivePort, /* Active Port in RLMT mode */
20473-SK_BOOL DualNet) /* adapter context */
20474+SK_BOOL DualNet) /* Dual Net active */
20475 {
20476 int i;
20477 int UsedKilobytes; /* memory already assigned */
20478 int ActivePortKilobytes; /* memory available for active port */
20479- SK_GEPORT *pGePort;
20480-
20481- UsedKilobytes = 0;
20482+ int MinQueueSize; /* min. memory for queues */
20483+ int TotalRamSize; /* total memory for queues */
20484+ SK_BOOL DualPortYukon2;
20485+ SK_GEPORT *pPrt;
20486
20487 if (ActivePort >= pAC->GIni.GIMacsFound) {
20488+
20489 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
20490 ("SkGeInitAssignRamToQueues: ActivePort (%d) invalid\n",
20491 ActivePort));
20492 return(1);
20493 }
20494- if (((pAC->GIni.GIMacsFound * (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE)) +
20495- ((RAM_QUOTA_SYNC == 0) ? 0 : SK_MIN_TXQ_SIZE)) > pAC->GIni.GIRamSize) {
20496+
20497+ DualPortYukon2 = (CHIP_ID_YUKON_2(pAC) && pAC->GIni.GIMacsFound == 2);
20498+
20499+ TotalRamSize = pAC->GIni.GIRamSize;
20500+
20501+ if (DualPortYukon2) {
20502+ TotalRamSize *= 2;
20503+ }
20504+
20505+ MinQueueSize = SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE;
20506+
20507+ if (MinQueueSize > pAC->GIni.GIRamSize) {
20508+ MinQueueSize = pAC->GIni.GIRamSize;
20509+ }
20510+
20511+ if ((pAC->GIni.GIMacsFound * MinQueueSize +
20512+ RAM_QUOTA_SYNC * SK_MIN_TXQ_SIZE) > TotalRamSize) {
20513+
20514 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
20515 ("SkGeInitAssignRamToQueues: Not enough memory (%d)\n",
20516- pAC->GIni.GIRamSize));
20517+ TotalRamSize));
20518 return(2);
20519 }
20520
20521 if (DualNet) {
20522 /* every port gets the same amount of memory */
20523- ActivePortKilobytes = pAC->GIni.GIRamSize / pAC->GIni.GIMacsFound;
20524+ ActivePortKilobytes = TotalRamSize / pAC->GIni.GIMacsFound;
20525+
20526 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
20527
20528- pGePort = &pAC->GIni.GP[i];
20529-
20530+ pPrt = &pAC->GIni.GP[i];
20531+
20532+ if (DualPortYukon2) {
20533+ ActivePortKilobytes = pAC->GIni.GIRamSize;
20534+ }
20535 /* take away the minimum memory for active queues */
20536- ActivePortKilobytes -= (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE);
20537+ ActivePortKilobytes -= MinQueueSize;
20538
20539 /* receive queue gets the minimum + 80% of the rest */
20540- pGePort->PRxQSize = (int) (ROUND_QUEUE_SIZE_KB((
20541- ActivePortKilobytes * (unsigned long) RAM_QUOTA_RX) / 100))
20542+ pPrt->PRxQSize = SkGeRoundQueueSize(pAC,
20543+ (int)((long)ActivePortKilobytes * RAM_QUOTA_RX) / 100)
20544 + SK_MIN_RXQ_SIZE;
20545
20546- ActivePortKilobytes -= (pGePort->PRxQSize - SK_MIN_RXQ_SIZE);
20547+ ActivePortKilobytes -= (pPrt->PRxQSize - SK_MIN_RXQ_SIZE);
20548
20549 /* synchronous transmit queue */
20550- pGePort->PXSQSize = 0;
20551+ pPrt->PXSQSize = 0;
20552
20553 /* asynchronous transmit queue */
20554- pGePort->PXAQSize = (int) ROUND_QUEUE_SIZE_KB(ActivePortKilobytes +
20555- SK_MIN_TXQ_SIZE);
20556+ pPrt->PXAQSize = SkGeRoundQueueSize(pAC,
20557+ ActivePortKilobytes + SK_MIN_TXQ_SIZE);
20558 }
20559 }
20560- else {
20561- /* Rlmt Mode or single link adapter */
20562+ else { /* RLMT Mode or single link adapter */
20563+
20564+ UsedKilobytes = 0;
20565
20566- /* Set standby queue size defaults for all standby ports */
20567+ /* set standby queue size defaults for all standby ports */
20568 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
20569
20570 if (i != ActivePort) {
20571- pGePort = &pAC->GIni.GP[i];
20572+ pPrt = &pAC->GIni.GP[i];
20573
20574- pGePort->PRxQSize = SK_MIN_RXQ_SIZE;
20575- pGePort->PXAQSize = SK_MIN_TXQ_SIZE;
20576- pGePort->PXSQSize = 0;
20577+ if (DualPortYukon2) {
20578+ pPrt->PRxQSize = SkGeRoundQueueSize(pAC,
20579+ (int)((long)(pAC->GIni.GIRamSize - MinQueueSize) *
20580+ RAM_QUOTA_RX) / 100) + SK_MIN_RXQ_SIZE;
20581+
20582+ pPrt->PXAQSize = pAC->GIni.GIRamSize - pPrt->PRxQSize;
20583+ }
20584+ else {
20585+ pPrt->PRxQSize = SK_MIN_RXQ_SIZE;
20586+ pPrt->PXAQSize = SK_MIN_TXQ_SIZE;
20587+ }
20588+ pPrt->PXSQSize = 0;
20589
20590 /* Count used RAM */
20591- UsedKilobytes += pGePort->PRxQSize + pGePort->PXAQSize;
20592+ UsedKilobytes += pPrt->PRxQSize + pPrt->PXAQSize;
20593 }
20594 }
20595 /* what's left? */
20596- ActivePortKilobytes = pAC->GIni.GIRamSize - UsedKilobytes;
20597+ ActivePortKilobytes = TotalRamSize - UsedKilobytes;
20598
20599 /* assign it to the active port */
20600 /* first take away the minimum memory */
20601- ActivePortKilobytes -= (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE);
20602- pGePort = &pAC->GIni.GP[ActivePort];
20603+ ActivePortKilobytes -= MinQueueSize;
20604+ pPrt = &pAC->GIni.GP[ActivePort];
20605+
20606+ /* receive queue gets 80% of the rest */
20607+ pPrt->PRxQSize = SkGeRoundQueueSize(pAC,
20608+ (int)((long)ActivePortKilobytes * RAM_QUOTA_RX) / 100);
20609
20610- /* receive queue get's the minimum + 80% of the rest */
20611- pGePort->PRxQSize = (int) (ROUND_QUEUE_SIZE_KB((ActivePortKilobytes *
20612- (unsigned long) RAM_QUOTA_RX) / 100)) + SK_MIN_RXQ_SIZE;
20613+ ActivePortKilobytes -= pPrt->PRxQSize;
20614
20615- ActivePortKilobytes -= (pGePort->PRxQSize - SK_MIN_RXQ_SIZE);
20616+ /* add the minimum memory for Rx queue */
20617+ pPrt->PRxQSize += MinQueueSize/2;
20618
20619 /* synchronous transmit queue */
20620- pGePort->PXSQSize = 0;
20621+ pPrt->PXSQSize = 0;
20622
20623- /* asynchronous transmit queue */
20624- pGePort->PXAQSize = (int) ROUND_QUEUE_SIZE_KB(ActivePortKilobytes) +
20625- SK_MIN_TXQ_SIZE;
20626+ /* asynchronous transmit queue gets 20% of the rest */
20627+ pPrt->PXAQSize = SkGeRoundQueueSize(pAC, ActivePortKilobytes) +
20628+ /* add the minimum memory for Tx queue */
20629+ MinQueueSize/2;
20630 }
20631-#ifdef VCPU
20632- VCPUprintf(0, "PRxQSize=%u, PXSQSize=%u, PXAQSize=%u\n",
20633- pGePort->PRxQSize, pGePort->PXSQSize, pGePort->PXAQSize);
20634-#endif /* VCPU */
20635+
20636+#ifdef DEBUG
20637+ for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
20638+
20639+ pPrt = &pAC->GIni.GP[i];
20640+
20641+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
20642+ ("Port %d: RxQSize=%u, TxAQSize=%u, TxSQSize=%u\n",
20643+ i, pPrt->PRxQSize, pPrt->PXAQSize, pPrt->PXSQSize));
20644+ }
20645+#endif /* DEBUG */
20646
20647 return(0);
20648 } /* SkGeInitAssignRamToQueues */
20649
20650+
20651 /******************************************************************************
20652 *
20653 * SkGeCheckQSize() - Checks the Adapters Queue Size Configuration
20654@@ -360,12 +557,12 @@
20655 * used ports.
20656 * This requirements must be fullfilled to have a valid configuration:
20657 * - The size of all queues must not exceed GIRamSize.
20658- * - The queue sizes must be specified in units of 8 kB.
20659+ * - The queue sizes must be specified in units of 8 kB (Genesis & Yukon).
20660 * - The size of Rx queues of available ports must not be
20661- * smaller than 16 kB.
20662+ * smaller than 16 kB (Genesis & Yukon) resp. 10 kB (Yukon-2).
20663 * - The size of at least one Tx queue (synch. or asynch.)
20664- * of available ports must not be smaller than 16 kB
20665- * when Jumbo Frames are used.
20666+ * of available ports must not be smaller than 16 kB (Genesis & Yukon),
20667+ * resp. 10 kB (Yukon-2) when Jumbo Frames are used.
20668 * - The RAM start and end addresses must not be changed
20669 * for ports which are already initialized.
20670 * Furthermore SkGeCheckQSize() defines the Start and End Addresses
20671@@ -376,7 +573,7 @@
20672 * 1: Queue Size Configuration invalid
20673 */
20674 static int SkGeCheckQSize(
20675-SK_AC *pAC, /* adapter context */
20676+SK_AC *pAC, /* Adapter Context */
20677 int Port) /* port index */
20678 {
20679 SK_GEPORT *pPrt;
20680@@ -386,55 +583,68 @@
20681 SK_U32 StartAddr;
20682 #ifndef SK_SLIM
20683 int UsedMem; /* total memory used (max. found ports) */
20684-#endif
20685+#endif
20686
20687 Rtv = 0;
20688-
20689+
20690 #ifndef SK_SLIM
20691
20692 UsedMem = 0;
20693+
20694 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
20695 pPrt = &pAC->GIni.GP[i];
20696
20697- if ((pPrt->PRxQSize & QZ_UNITS) != 0 ||
20698- (pPrt->PXSQSize & QZ_UNITS) != 0 ||
20699- (pPrt->PXAQSize & QZ_UNITS) != 0) {
20700+ if (CHIP_ID_YUKON_2(pAC)) {
20701+ UsedMem = 0;
20702+ }
20703+ else if (((pPrt->PRxQSize & QZ_UNITS) != 0 ||
20704+ (pPrt->PXSQSize & QZ_UNITS) != 0 ||
20705+ (pPrt->PXAQSize & QZ_UNITS) != 0)) {
20706
20707 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG);
20708 return(1);
20709 }
20710
20711- if (i == Port && pPrt->PRxQSize < SK_MIN_RXQ_SIZE) {
20712+#ifndef SK_DIAG
20713+ if (i == Port && pAC->GIni.GIRamSize > SK_MIN_RXQ_SIZE &&
20714+ pPrt->PRxQSize < SK_MIN_RXQ_SIZE) {
20715 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E011, SKERR_HWI_E011MSG);
20716 return(1);
20717 }
20718-
20719+
20720 /*
20721 * the size of at least one Tx queue (synch. or asynch.) has to be > 0.
20722 * if Jumbo Frames are used, this size has to be >= 16 kB.
20723 */
20724 if ((i == Port && pPrt->PXSQSize == 0 && pPrt->PXAQSize == 0) ||
20725- (pAC->GIni.GIPortUsage == SK_JUMBO_LINK &&
20726- ((pPrt->PXSQSize > 0 && pPrt->PXSQSize < SK_MIN_TXQ_SIZE) ||
20727+ (pPrt->PPortUsage == SK_JUMBO_LINK &&
20728+ ((pPrt->PXSQSize > 0 && pPrt->PXSQSize < SK_MIN_TXQ_SIZE) ||
20729 (pPrt->PXAQSize > 0 && pPrt->PXAQSize < SK_MIN_TXQ_SIZE)))) {
20730 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E023, SKERR_HWI_E023MSG);
20731 return(1);
20732 }
20733-
20734+#endif /* !SK_DIAG */
20735+
20736 UsedMem += pPrt->PRxQSize + pPrt->PXSQSize + pPrt->PXAQSize;
20737+
20738+ if (UsedMem > pAC->GIni.GIRamSize) {
20739+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG);
20740+ return(1);
20741+ }
20742 }
20743-
20744- if (UsedMem > pAC->GIni.GIRamSize) {
20745- SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG);
20746- return(1);
20747- }
20748-#endif /* !SK_SLIM */
20749+
20750+#endif /* !SK_SLIM */
20751
20752 /* Now start address calculation */
20753 StartAddr = pAC->GIni.GIRamOffs;
20754 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
20755+
20756 pPrt = &pAC->GIni.GP[i];
20757
20758+ if (CHIP_ID_YUKON_2(pAC)) {
20759+ StartAddr = 0;
20760+ }
20761+
20762 /* Calculate/Check values for the receive queue */
20763 Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PRxQSize, &StartAddr,
20764 &pPrt->PRxQRamStart, &pPrt->PRxQRamEnd);
20765@@ -474,8 +684,8 @@
20766 * nothing
20767 */
20768 static void SkGeInitMacArb(
20769-SK_AC *pAC, /* adapter context */
20770-SK_IOC IoC) /* IO context */
20771+SK_AC *pAC, /* Adapter Context */
20772+SK_IOC IoC) /* I/O Context */
20773 {
20774 /* release local reset */
20775 SK_OUT16(IoC, B3_MA_TO_CTRL, MA_RST_CLR);
20776@@ -514,8 +724,8 @@
20777 * nothing
20778 */
20779 static void SkGeInitPktArb(
20780-SK_AC *pAC, /* adapter context */
20781-SK_IOC IoC) /* IO context */
20782+SK_AC *pAC, /* Adapter Context */
20783+SK_IOC IoC) /* I/O Context */
20784 {
20785 /* release local reset */
20786 SK_OUT16(IoC, B3_PA_CTRL, PA_RST_CLR);
20787@@ -531,7 +741,8 @@
20788 * NOTE: the packet arbiter timeout interrupt is needed for
20789 * half duplex hangup workaround
20790 */
20791- if (pAC->GIni.GIPortUsage != SK_JUMBO_LINK) {
20792+ if (pAC->GIni.GP[MAC_1].PPortUsage != SK_JUMBO_LINK &&
20793+ pAC->GIni.GP[MAC_2].PPortUsage != SK_JUMBO_LINK) {
20794 if (pAC->GIni.GIMacsFound == 1) {
20795 SK_OUT16(IoC, B3_PA_CTRL, PA_ENA_TO_TX1);
20796 }
20797@@ -554,14 +765,11 @@
20798 * nothing
20799 */
20800 static void SkGeInitMacFifo(
20801-SK_AC *pAC, /* adapter context */
20802-SK_IOC IoC, /* IO context */
20803+SK_AC *pAC, /* Adapter Context */
20804+SK_IOC IoC, /* I/O Context */
20805 int Port) /* Port Index (MAC_1 + n) */
20806 {
20807 SK_U16 Word;
20808-#ifdef VCPU
20809- SK_U32 DWord;
20810-#endif /* VCPU */
20811 /*
20812 * For each FIFO:
20813 * - release local reset
20814@@ -569,63 +777,107 @@
20815 * - setup defaults for the control register
20816 * - enable the FIFO
20817 */
20818-
20819+
20820 #ifdef GENESIS
20821 if (pAC->GIni.GIGenesis) {
20822- /* Configure Rx MAC FIFO */
20823+ /* configure Rx MAC FIFO */
20824 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_CLR);
20825 SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_RX_CTRL_DEF);
20826 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
20827-
20828- /* Configure Tx MAC FIFO */
20829+
20830+ /* configure Tx MAC FIFO */
20831 SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_RST_CLR);
20832 SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
20833 SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
20834-
20835- /* Enable frame flushing if jumbo frames used */
20836- if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
20837+
20838+ /* enable frame flushing if jumbo frames used */
20839+ if (pAC->GIni.GP[Port].PPortUsage == SK_JUMBO_LINK) {
20840 SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
20841 }
20842 }
20843 #endif /* GENESIS */
20844-
20845+
20846 #ifdef YUKON
20847 if (pAC->GIni.GIYukon) {
20848- /* set Rx GMAC FIFO Flush Mask */
20849- SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), (SK_U16)RX_FF_FL_DEF_MSK);
20850-
20851+
20852 Word = (SK_U16)GMF_RX_CTRL_DEF;
20853
20854 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
20855- if (pAC->GIni.GIYukonLite && pAC->GIni.GIChipId == CHIP_ID_YUKON) {
20856+ if (pAC->GIni.GIYukonLite /* && pAC->GIni.GIChipId == CHIP_ID_YUKON */) {
20857
20858 Word &= ~GMF_RX_F_FL_ON;
20859 }
20860-
20861- /* Configure Rx MAC FIFO */
20862+
20863+ /* configure Rx GMAC FIFO */
20864 SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR);
20865 SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), Word);
20866-
20867- /* set Rx GMAC FIFO Flush Threshold (default: 0x0a -> 56 bytes) */
20868- SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
20869-
20870- /* Configure Tx MAC FIFO */
20871+
20872+ Word = RX_FF_FL_DEF_MSK;
20873+
20874+#ifndef SK_DIAG
20875+ if (HW_FEATURE(pAC, HWF_WA_DEV_4115)) {
20876+ /*
20877+ * Flushing must be enabled (needed for ASF see dev. #4.29),
20878+ * but the flushing mask should be disabled (see dev. #4.115)
20879+ */
20880+ Word = 0;
20881+ }
20882+#endif /* !SK_DIAG */
20883+
20884+ /* set Rx GMAC FIFO Flush Mask (after clearing reset) */
20885+ SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), Word);
20886+
20887+ /* default: 0x0a -> 56 bytes on Yukon-1 and 64 bytes on Yukon-2 */
20888+ Word = (SK_U16)RX_GMF_FL_THR_DEF;
20889+
20890+ if (CHIP_ID_YUKON_2(pAC)) {
20891+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC &&
20892+ pAC->GIni.GIAsfEnabled) {
20893+ /* WA for dev. #4.30 (reduce to 0x08 -> 48 bytes) */
20894+ Word -= 2;
20895+ }
20896+ }
20897+ else {
20898+ /*
20899+ * because Pause Packet Truncation in GMAC is not working
20900+ * we have to increase the Flush Threshold to 64 bytes
20901+ * in order to flush pause packets in Rx FIFO on Yukon-1
20902+ */
20903+ Word++;
20904+ }
20905+
20906+ /* set Rx GMAC FIFO Flush Threshold (after clearing reset) */
20907+ SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), Word);
20908+
20909+ /* configure Tx GMAC FIFO */
20910 SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR);
20911 SK_OUT16(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U16)GMF_TX_CTRL_DEF);
20912-
20913-#ifdef VCPU
20914- SK_IN32(IoC, MR_ADDR(Port, RX_GMF_AF_THR), &DWord);
20915- SK_IN32(IoC, MR_ADDR(Port, TX_GMF_AE_THR), &DWord);
20916-#endif /* VCPU */
20917-
20918- /* set Tx GMAC FIFO Almost Empty Threshold */
20919-/* SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_AE_THR), 0); */
20920+
20921+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) {
20922+ /* set Rx Pause Threshold */
20923+ SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_LP_THR), (SK_U16)SK_ECU_LLPP);
20924+ SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_UP_THR), (SK_U16)SK_ECU_ULPP);
20925+
20926+ if (pAC->GIni.GP[Port].PPortUsage == SK_JUMBO_LINK) {
20927+ /* set Tx GMAC FIFO Almost Empty Threshold */
20928+ SK_OUT16(IoC, MR_ADDR(Port, TX_GMF_AE_THR),
20929+ (SK_U16)SK_ECU_AE_THR);
20930+ /* disable Store & Forward mode for TX */
20931+ SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), TX_STFW_DIS);
20932+ }
20933+#ifdef TEST_ONLY
20934+ else {
20935+ /* enable Store & Forward mode for TX */
20936+ SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), TX_STFW_ENA);
20937+ }
20938+#endif /* TEST_ONLY */
20939+ }
20940 }
20941 #endif /* YUKON */
20942
20943 } /* SkGeInitMacFifo */
20944
20945-#ifdef SK_LNK_SYNC_CNT
20946+#ifdef SK_LNK_SYNC_CNT
20947 /******************************************************************************
20948 *
20949 * SkGeLoadLnkSyncCnt() - Load the Link Sync Counter and starts counting
20950@@ -646,8 +898,8 @@
20951 * nothing
20952 */
20953 void SkGeLoadLnkSyncCnt(
20954-SK_AC *pAC, /* adapter context */
20955-SK_IOC IoC, /* IO context */
20956+SK_AC *pAC, /* Adapter Context */
20957+SK_IOC IoC, /* I/O Context */
20958 int Port, /* Port Index (MAC_1 + n) */
20959 SK_U32 CntVal) /* Counter value */
20960 {
20961@@ -657,7 +909,7 @@
20962 SK_BOOL IrqPend;
20963
20964 /* stop counter */
20965- SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_STOP);
20966+ SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LNK_STOP);
20967
20968 /*
20969 * ASIC problem:
20970@@ -670,6 +922,7 @@
20971 IrqPend = SK_FALSE;
20972 SK_IN32(IoC, B0_ISRC, &ISrc);
20973 SK_IN32(IoC, B0_IMSK, &OrgIMsk);
20974+
20975 if (Port == MAC_1) {
20976 NewIMsk = OrgIMsk & ~IS_LNK_SYNC_M1;
20977 if ((ISrc & IS_LNK_SYNC_M1) != 0) {
20978@@ -682,6 +935,7 @@
20979 IrqPend = SK_TRUE;
20980 }
20981 }
20982+
20983 if (!IrqPend) {
20984 SK_OUT32(IoC, B0_IMSK, NewIMsk);
20985 }
20986@@ -690,15 +944,17 @@
20987 SK_OUT32(IoC, MR_ADDR(Port, LNK_SYNC_INI), CntVal);
20988
20989 /* start counter */
20990- SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_START);
20991+ SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LNK_START);
20992
20993 if (!IrqPend) {
20994- /* clear the unexpected IRQ, and restore the interrupt mask */
20995- SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_CLR_IRQ);
20996+ /* clear the unexpected IRQ */
20997+ SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LNK_CLR_IRQ);
20998+
20999+ /* restore the interrupt mask */
21000 SK_OUT32(IoC, B0_IMSK, OrgIMsk);
21001 }
21002 } /* SkGeLoadLnkSyncCnt*/
21003-#endif /* SK_LNK_SYNC_CNT */
21004+#endif /* SK_LNK_SYNC_CNT */
21005
21006 #if defined(SK_DIAG) || defined(SK_CFG_SYNC)
21007 /******************************************************************************
21008@@ -730,8 +986,8 @@
21009 * synchronous queue is configured
21010 */
21011 int SkGeCfgSync(
21012-SK_AC *pAC, /* adapter context */
21013-SK_IOC IoC, /* IO context */
21014+SK_AC *pAC, /* Adapter Context */
21015+SK_IOC IoC, /* I/O Context */
21016 int Port, /* Port Index (MAC_1 + n) */
21017 SK_U32 IntTime, /* Interval Timer Value in units of 8ns */
21018 SK_U32 LimCount, /* Number of bytes to transfer during IntTime */
21019@@ -749,16 +1005,16 @@
21020 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG);
21021 return(1);
21022 }
21023-
21024+
21025 if (pAC->GIni.GP[Port].PXSQSize == 0) {
21026 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E009, SKERR_HWI_E009MSG);
21027 return(2);
21028 }
21029-
21030+
21031 /* calculate register values */
21032 IntTime = (IntTime / 2) * pAC->GIni.GIHstClkFact / 100;
21033 LimCount = LimCount / 8;
21034-
21035+
21036 if (IntTime > TXA_MAX_VAL || LimCount > TXA_MAX_VAL) {
21037 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG);
21038 return(1);
21039@@ -776,13 +1032,13 @@
21040 */
21041 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
21042 TXA_ENA_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
21043-
21044+
21045 SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), IntTime);
21046 SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), LimCount);
21047-
21048+
21049 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
21050 (SK_U8)(SyncMode & (TXA_ENA_ALLOC | TXA_DIS_ALLOC)));
21051-
21052+
21053 if (IntTime != 0 || LimCount != 0) {
21054 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_DIS_FSYNC | TXA_START_RC);
21055 }
21056@@ -803,10 +1059,10 @@
21057 * Returns:
21058 * nothing
21059 */
21060-static void DoInitRamQueue(
21061-SK_AC *pAC, /* adapter context */
21062-SK_IOC IoC, /* IO context */
21063-int QuIoOffs, /* Queue IO Address Offset */
21064+void DoInitRamQueue(
21065+SK_AC *pAC, /* Adapter Context */
21066+SK_IOC IoC, /* I/O Context */
21067+int QuIoOffs, /* Queue I/O Address Offset */
21068 SK_U32 QuStartAddr, /* Queue Start Address */
21069 SK_U32 QuEndAddr, /* Queue End Address */
21070 int QuType) /* Queue Type (SK_RX_SRAM_Q|SK_RX_BRAM_Q|SK_TX_RAM_Q) */
21071@@ -839,8 +1095,7 @@
21072
21073 /* continue with SK_RX_BRAM_Q */
21074 case SK_RX_BRAM_Q:
21075- /* write threshold for Rx Queue */
21076-
21077+ /* write threshold for Rx Queue (Pause packets) */
21078 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RX_UTPP), RxUpThresVal);
21079 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RX_LTPP), RxLoThresVal);
21080
21081@@ -854,7 +1109,8 @@
21082 * or YUKON is used ((GMAC Tx FIFO is only 1 kB)
21083 * we NEED Store & Forward of the RAM buffer.
21084 */
21085- if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK ||
21086+ if (pAC->GIni.GP[MAC_1].PPortUsage == SK_JUMBO_LINK ||
21087+ pAC->GIni.GP[MAC_2].PPortUsage == SK_JUMBO_LINK ||
21088 pAC->GIni.GIYukon) {
21089 /* enable Store & Forward Mode for the Tx Side */
21090 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_ENA_STFWD);
21091@@ -883,8 +1139,8 @@
21092 * nothing
21093 */
21094 static void SkGeInitRamBufs(
21095-SK_AC *pAC, /* adapter context */
21096-SK_IOC IoC, /* IO context */
21097+SK_AC *pAC, /* Adapter Context */
21098+SK_IOC IoC, /* I/O Context */
21099 int Port) /* Port Index (MAC_1 + n) */
21100 {
21101 SK_GEPORT *pPrt;
21102@@ -892,8 +1148,8 @@
21103
21104 pPrt = &pAC->GIni.GP[Port];
21105
21106- if (pPrt->PRxQSize == SK_MIN_RXQ_SIZE) {
21107- RxQType = SK_RX_SRAM_Q; /* small Rx Queue */
21108+ if (pPrt->PRxQSize <= SK_MIN_RXQ_SIZE) {
21109+ RxQType = SK_RX_SRAM_Q; /* small Rx Queue */
21110 }
21111 else {
21112 RxQType = SK_RX_BRAM_Q; /* big Rx Queue */
21113@@ -901,10 +1157,10 @@
21114
21115 DoInitRamQueue(pAC, IoC, pPrt->PRxQOff, pPrt->PRxQRamStart,
21116 pPrt->PRxQRamEnd, RxQType);
21117-
21118+
21119 DoInitRamQueue(pAC, IoC, pPrt->PXsQOff, pPrt->PXsQRamStart,
21120 pPrt->PXsQRamEnd, SK_TX_RAM_Q);
21121-
21122+
21123 DoInitRamQueue(pAC, IoC, pPrt->PXaQOff, pPrt->PXaQRamStart,
21124 pPrt->PXaQRamEnd, SK_TX_RAM_Q);
21125
21126@@ -924,27 +1180,38 @@
21127 * Returns:
21128 * nothing
21129 */
21130-static void SkGeInitRamIface(
21131-SK_AC *pAC, /* adapter context */
21132-SK_IOC IoC) /* IO context */
21133+void SkGeInitRamIface(
21134+SK_AC *pAC, /* Adapter Context */
21135+SK_IOC IoC) /* I/O Context */
21136 {
21137- /* release local reset */
21138- SK_OUT16(IoC, B3_RI_CTRL, RI_RST_CLR);
21139+ int i;
21140+ int RamBuffers;
21141
21142- /* configure timeout values */
21143- SK_OUT8(IoC, B3_RI_WTO_R1, SK_RI_TO_53);
21144- SK_OUT8(IoC, B3_RI_WTO_XA1, SK_RI_TO_53);
21145- SK_OUT8(IoC, B3_RI_WTO_XS1, SK_RI_TO_53);
21146- SK_OUT8(IoC, B3_RI_RTO_R1, SK_RI_TO_53);
21147- SK_OUT8(IoC, B3_RI_RTO_XA1, SK_RI_TO_53);
21148- SK_OUT8(IoC, B3_RI_RTO_XS1, SK_RI_TO_53);
21149- SK_OUT8(IoC, B3_RI_WTO_R2, SK_RI_TO_53);
21150- SK_OUT8(IoC, B3_RI_WTO_XA2, SK_RI_TO_53);
21151- SK_OUT8(IoC, B3_RI_WTO_XS2, SK_RI_TO_53);
21152- SK_OUT8(IoC, B3_RI_RTO_R2, SK_RI_TO_53);
21153- SK_OUT8(IoC, B3_RI_RTO_XA2, SK_RI_TO_53);
21154- SK_OUT8(IoC, B3_RI_RTO_XS2, SK_RI_TO_53);
21155+ if (CHIP_ID_YUKON_2(pAC)) {
21156+ RamBuffers = pAC->GIni.GIMacsFound;
21157+ }
21158+ else {
21159+ RamBuffers = 1;
21160+ }
21161+
21162+ for (i = 0; i < RamBuffers; i++) {
21163+ /* release local reset */
21164+ SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_CTRL), (SK_U8)RI_RST_CLR);
21165
21166+ /* configure timeout values */
21167+ SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
21168+ SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
21169+ SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
21170+ SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
21171+ SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
21172+ SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
21173+ SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
21174+ SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
21175+ SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
21176+ SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
21177+ SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
21178+ SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
21179+ }
21180 } /* SkGeInitRamIface */
21181
21182
21183@@ -959,41 +1226,91 @@
21184 * nothing
21185 */
21186 static void SkGeInitBmu(
21187-SK_AC *pAC, /* adapter context */
21188-SK_IOC IoC, /* IO context */
21189+SK_AC *pAC, /* Adapter Context */
21190+SK_IOC IoC, /* I/O Context */
21191 int Port) /* Port Index (MAC_1 + n) */
21192 {
21193 SK_GEPORT *pPrt;
21194- SK_U32 RxWm;
21195- SK_U32 TxWm;
21196+ SK_U16 RxWm;
21197+ SK_U16 TxWm;
21198
21199 pPrt = &pAC->GIni.GP[Port];
21200
21201 RxWm = SK_BMU_RX_WM;
21202 TxWm = SK_BMU_TX_WM;
21203-
21204- if (!pAC->GIni.GIPciSlot64 && !pAC->GIni.GIPciClock66) {
21205- /* for better performance */
21206- RxWm /= 2;
21207- TxWm /= 2;
21208- }
21209
21210- /* Rx Queue: Release all local resets and set the watermark */
21211- SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_CLR_RESET);
21212- SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_F), RxWm);
21213+ if (CHIP_ID_YUKON_2(pAC)) {
21214
21215- /*
21216- * Tx Queue: Release all local resets if the queue is used !
21217- * set watermark
21218- */
21219- if (pPrt->PXSQSize != 0) {
21220- SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_CLR_RESET);
21221- SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_F), TxWm);
21222+ if (pAC->GIni.GIPciBus == SK_PEX_BUS) {
21223+ /* for better performance set it to 128 */
21224+ RxWm = SK_BMU_RX_WM_PEX;
21225+ }
21226+
21227+ /* Rx Queue: Release all local resets and set the watermark */
21228+ SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), BMU_CLR_RESET);
21229+ SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), BMU_OPER_INIT);
21230+ SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), BMU_FIFO_OP_ON);
21231+
21232+ SK_OUT16(IoC, Q_ADDR(pPrt->PRxQOff, Q_WM), RxWm);
21233+
21234+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U &&
21235+ pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A1) {
21236+ /* MAC Rx RAM Read is controlled by hardware */
21237+ SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_F), F_M_RX_RAM_DIS);
21238+ }
21239+
21240+ /*
21241+ * Tx Queue: Release all local resets if the queue is used !
21242+ * set watermark
21243+ */
21244+ if (pPrt->PXSQSize != 0 && HW_SYNC_TX_SUPPORTED(pAC)) {
21245+ /* Yukon-EC doesn't have a synchronous Tx queue */
21246+ SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), BMU_CLR_RESET);
21247+ SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), BMU_OPER_INIT);
21248+ SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), BMU_FIFO_OP_ON);
21249+
21250+ SK_OUT16(IoC, Q_ADDR(pPrt->PXsQOff, Q_WM), TxWm);
21251+ }
21252+
21253+ if (pPrt->PXAQSize != 0) {
21254+
21255+ SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), BMU_CLR_RESET);
21256+ SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), BMU_OPER_INIT);
21257+ SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), BMU_FIFO_OP_ON);
21258+
21259+ SK_OUT16(IoC, Q_ADDR(pPrt->PXaQOff, Q_WM), TxWm);
21260+
21261+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U &&
21262+ pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A0) {
21263+ /* fix for Yukon-EC Ultra: set BMU FIFO level */
21264+ SK_OUT16(IoC, Q_ADDR(pPrt->PXaQOff, Q_AL), SK_ECU_TXFF_LEV);
21265+ }
21266+ }
21267 }
21268-
21269- if (pPrt->PXAQSize != 0) {
21270- SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_CLR_RESET);
21271- SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_F), TxWm);
21272+ else {
21273+ if (!pAC->GIni.GIPciSlot64 && !pAC->GIni.GIPciClock66) {
21274+ /* for better performance */
21275+ RxWm /= 2;
21276+ TxWm /= 2;
21277+ }
21278+
21279+ /* Rx Queue: Release all local resets and set the watermark */
21280+ SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_CLR_RESET);
21281+ SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_F), RxWm);
21282+
21283+ /*
21284+ * Tx Queue: Release all local resets if the queue is used !
21285+ * set watermark
21286+ */
21287+ if (pPrt->PXSQSize != 0) {
21288+ SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_CLR_RESET);
21289+ SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_F), TxWm);
21290+ }
21291+
21292+ if (pPrt->PXAQSize != 0) {
21293+ SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_CLR_RESET);
21294+ SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_F), TxWm);
21295+ }
21296 }
21297 /*
21298 * Do NOT enable the descriptor poll timers here, because
21299@@ -1017,22 +1334,31 @@
21300 */
21301 static SK_U32 TestStopBit(
21302 SK_AC *pAC, /* Adapter Context */
21303-SK_IOC IoC, /* IO Context */
21304-int QuIoOffs) /* Queue IO Address Offset */
21305+SK_IOC IoC, /* I/O Context */
21306+int QuIoOffs) /* Queue I/O Address Offset */
21307 {
21308 SK_U32 QuCsr; /* CSR contents */
21309
21310 SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
21311-
21312- if ((QuCsr & (CSR_STOP | CSR_SV_IDLE)) == 0) {
21313- /* Stop Descriptor overridden by start command */
21314- SK_OUT32(IoC, Q_ADDR(QuIoOffs, Q_CSR), CSR_STOP);
21315-
21316- SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
21317- }
21318-
21319- return(QuCsr);
21320-} /* TestStopBit */
21321+
21322+ if (CHIP_ID_YUKON_2(pAC)) {
21323+ if ((QuCsr & (BMU_STOP | BMU_IDLE)) == 0) {
21324+ /* Stop Descriptor overridden by start command */
21325+ SK_OUT32(IoC, Q_ADDR(QuIoOffs, Q_CSR), BMU_STOP);
21326+
21327+ SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
21328+ }
21329+ }
21330+ else {
21331+ if ((QuCsr & (CSR_STOP | CSR_SV_IDLE)) == 0) {
21332+ /* Stop Descriptor overridden by start command */
21333+ SK_OUT32(IoC, Q_ADDR(QuIoOffs, Q_CSR), CSR_STOP);
21334+
21335+ SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
21336+ }
21337+ }
21338+ return(QuCsr);
21339+} /* TestStopBit */
21340
21341
21342 /******************************************************************************
21343@@ -1054,8 +1380,8 @@
21344 * has to be stopped once before.
21345 * SK_STOP_ALL SK_STOP_TX + SK_STOP_RX
21346 *
21347- * RstMode = SK_SOFT_RST Resets the MAC. The PHY is still alive.
21348- * SK_HARD_RST Resets the MAC and the PHY.
21349+ * RstMode = SK_SOFT_RST Resets the MAC, the PHY is still alive.
21350+ * SK_HARD_RST Resets the MAC and the PHY.
21351 *
21352 * Example:
21353 * 1) A Link Down event was signaled for a port. Therefore the activity
21354@@ -1114,56 +1440,82 @@
21355 * SWITCH_PORT.
21356 */
21357 void SkGeStopPort(
21358-SK_AC *pAC, /* adapter context */
21359-SK_IOC IoC, /* I/O context */
21360-int Port, /* port to stop (MAC_1 + n) */
21361+SK_AC *pAC, /* Adapter Context */
21362+SK_IOC IoC, /* I/O Context */
21363+int Port, /* Port to stop (MAC_1 + n) */
21364 int Dir, /* Direction to Stop (SK_STOP_RX, SK_STOP_TX, SK_STOP_ALL) */
21365 int RstMode)/* Reset Mode (SK_SOFT_RST, SK_HARD_RST) */
21366 {
21367-#ifndef SK_DIAG
21368- SK_EVPARA Para;
21369-#endif /* !SK_DIAG */
21370 SK_GEPORT *pPrt;
21371- SK_U32 DWord;
21372+ SK_U32 RxCsr;
21373 SK_U32 XsCsr;
21374 SK_U32 XaCsr;
21375 SK_U64 ToutStart;
21376+ SK_U32 CsrStart;
21377+ SK_U32 CsrStop;
21378+ SK_U32 CsrIdle;
21379+ SK_U32 CsrTest;
21380+ SK_U8 rsl; /* FIFO read shadow level */
21381+ SK_U8 rl; /* FIFO read level */
21382 int i;
21383 int ToutCnt;
21384
21385 pPrt = &pAC->GIni.GP[Port];
21386
21387+ /* set the proper values of Q_CSR register layout depending on the chip */
21388+ if (CHIP_ID_YUKON_2(pAC)) {
21389+ CsrStart = BMU_START;
21390+ CsrStop = BMU_STOP;
21391+ CsrIdle = BMU_IDLE;
21392+ CsrTest = BMU_IDLE;
21393+ }
21394+ else {
21395+ CsrStart = CSR_START;
21396+ CsrStop = CSR_STOP;
21397+ CsrIdle = CSR_SV_IDLE;
21398+ CsrTest = CSR_SV_IDLE | CSR_STOP;
21399+ }
21400+
21401 if ((Dir & SK_STOP_TX) != 0) {
21402- /* disable receiver and transmitter */
21403- SkMacRxTxDisable(pAC, IoC, Port);
21404-
21405+
21406+ if (!pAC->GIni.GIAsfEnabled) {
21407+ /* disable receiver and transmitter */
21408+ SkMacRxTxDisable(pAC, IoC, Port);
21409+ }
21410+
21411 /* stop both transmit queues */
21412+ SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CsrStop);
21413+ SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CsrStop);
21414 /*
21415 * If the BMU is in the reset state CSR_STOP will terminate
21416 * immediately.
21417 */
21418- SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_STOP);
21419- SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_STOP);
21420
21421 ToutStart = SkOsGetTime(pAC);
21422 ToutCnt = 0;
21423 do {
21424- /*
21425- * Clear packet arbiter timeout to make sure
21426- * this loop will terminate.
21427- */
21428- SK_OUT16(IoC, B3_PA_CTRL, (SK_U16)((Port == MAC_1) ?
21429- PA_CLR_TO_TX1 : PA_CLR_TO_TX2));
21430-
21431- /*
21432- * If the transfer stucks at the MAC the STOP command will not
21433- * terminate if we don't flush the XMAC's transmit FIFO !
21434- */
21435- SkMacFlushTxFifo(pAC, IoC, Port);
21436+#ifdef GENESIS
21437+ if (pAC->GIni.GIGenesis) {
21438+ /* clear Tx packet arbiter timeout IRQ */
21439+ SK_OUT16(IoC, B3_PA_CTRL, (SK_U16)((Port == MAC_1) ?
21440+ PA_CLR_TO_TX1 : PA_CLR_TO_TX2));
21441+ /*
21442+ * If the transfer stucks at the XMAC the STOP command will not
21443+ * terminate if we don't flush the XMAC's transmit FIFO !
21444+ */
21445+ SkMacFlushTxFifo(pAC, IoC, Port);
21446+ }
21447+#endif /* GENESIS */
21448
21449- XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff);
21450 XaCsr = TestStopBit(pAC, IoC, pPrt->PXaQOff);
21451
21452+ if (HW_SYNC_TX_SUPPORTED(pAC)) {
21453+ XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff);
21454+ }
21455+ else {
21456+ XsCsr = XaCsr;
21457+ }
21458+
21459 if (SkOsGetTime(pAC) - ToutStart > (SK_TICKS_PER_SEC / 18)) {
21460 /*
21461 * Timeout of 1/18 second reached.
21462@@ -1171,67 +1523,115 @@
21463 */
21464 ToutCnt++;
21465 if (ToutCnt > 1) {
21466- /* Might be a problem when the driver event handler
21467- * calls StopPort again. XXX.
21468+ /*
21469+ * If BMU stop doesn't terminate, we assume that
21470+ * we have a stable state and can reset the BMU,
21471+ * the Prefetch Unit, and RAM buffer now.
21472 */
21473-
21474- /* Fatal Error, Loop aborted */
21475- SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E018,
21476- SKERR_HWI_E018MSG);
21477-#ifndef SK_DIAG
21478- Para.Para64 = Port;
21479- SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
21480-#endif /* !SK_DIAG */
21481- return;
21482+ break; /* ===> leave do/while loop here */
21483 }
21484 /*
21485- * Cache incoherency workaround: Assume a start command
21486+ * Cache incoherency workaround: assume a start command
21487 * has been lost while sending the frame.
21488 */
21489 ToutStart = SkOsGetTime(pAC);
21490
21491- if ((XsCsr & CSR_STOP) != 0) {
21492- SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_START);
21493+ if ((XsCsr & CsrStop) != 0) {
21494+ SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CsrStart);
21495 }
21496- if ((XaCsr & CSR_STOP) != 0) {
21497- SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_START);
21498+
21499+ if ((XaCsr & CsrStop) != 0) {
21500+ SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CsrStart);
21501 }
21502- }
21503
21504+ /*
21505+ * After the previous operations the X(s|a)Csr does no
21506+ * longer contain the proper values
21507+ */
21508+ XaCsr = TestStopBit(pAC, IoC, pPrt->PXaQOff);
21509+
21510+ if (HW_SYNC_TX_SUPPORTED(pAC)) {
21511+ XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff);
21512+ }
21513+ else {
21514+ XsCsr = XaCsr;
21515+ }
21516+ }
21517 /*
21518 * Because of the ASIC problem report entry from 21.08.1998 it is
21519 * required to wait until CSR_STOP is reset and CSR_SV_IDLE is set.
21520+ * (valid for GENESIS only)
21521 */
21522- } while ((XsCsr & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE ||
21523- (XaCsr & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE);
21524+ } while (((XsCsr & CsrTest) != CsrIdle ||
21525+ (XaCsr & CsrTest) != CsrIdle));
21526+
21527+ if (pAC->GIni.GIAsfEnabled) {
21528
21529- /* Reset the MAC depending on the RstMode */
21530- if (RstMode == SK_SOFT_RST) {
21531- SkMacSoftRst(pAC, IoC, Port);
21532+ pPrt->PState = (RstMode == SK_SOFT_RST) ? SK_PRT_STOP :
21533+ SK_PRT_RESET;
21534 }
21535 else {
21536- SkMacHardRst(pAC, IoC, Port);
21537+ /* Reset the MAC depending on the RstMode */
21538+ if (RstMode == SK_SOFT_RST) {
21539+
21540+ SkMacSoftRst(pAC, IoC, Port);
21541+ }
21542+ else {
21543+#ifdef SK_DIAG
21544+ if (HW_FEATURE(pAC, HWF_WA_DEV_472) && Port == MAC_1 &&
21545+ pAC->GIni.GP[MAC_2].PState == SK_PRT_RUN) {
21546+
21547+ pAC->GIni.GP[MAC_1].PState = SK_PRT_RESET;
21548+
21549+ /* set GPHY Control reset */
21550+ SK_OUT8(IoC, MR_ADDR(MAC_1, GPHY_CTRL), (SK_U8)GPC_RST_SET);
21551+ }
21552+ else {
21553+
21554+ SkMacHardRst(pAC, IoC, Port);
21555+ }
21556+#else /* !SK_DIAG */
21557+ SkMacHardRst(pAC, IoC, Port);
21558+#endif /* !SK_DIAG */
21559+ }
21560 }
21561-
21562- /* Disable Force Sync bit and Enable Alloc bit */
21563+
21564+ /* disable Force Sync bit and Enable Alloc bit */
21565 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
21566 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
21567-
21568+
21569 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
21570 SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), 0L);
21571 SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), 0L);
21572
21573 /* Perform a local reset of the port's Tx path */
21574+ if (CHIP_ID_YUKON_2(pAC)) {
21575+ /* Reset the PCI FIFO of the async Tx queue */
21576+ SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR),
21577+ BMU_RST_SET | BMU_FIFO_RST);
21578+
21579+ /* Reset the PCI FIFO of the sync Tx queue */
21580+ SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR),
21581+ BMU_RST_SET | BMU_FIFO_RST);
21582+
21583+ /* Reset the Tx prefetch units */
21584+ SK_OUT32(IoC, Y2_PREF_Q_ADDR(pPrt->PXaQOff, PREF_UNIT_CTRL_REG),
21585+ PREF_UNIT_RST_SET);
21586+ SK_OUT32(IoC, Y2_PREF_Q_ADDR(pPrt->PXsQOff, PREF_UNIT_CTRL_REG),
21587+ PREF_UNIT_RST_SET);
21588+ }
21589+ else {
21590+ /* Reset the PCI FIFO of the async Tx queue */
21591+ SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_SET_RESET);
21592+ /* Reset the PCI FIFO of the sync Tx queue */
21593+ SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_SET_RESET);
21594+ }
21595
21596- /* Reset the PCI FIFO of the async Tx queue */
21597- SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_SET_RESET);
21598- /* Reset the PCI FIFO of the sync Tx queue */
21599- SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_SET_RESET);
21600 /* Reset the RAM Buffer async Tx queue */
21601 SK_OUT8(IoC, RB_ADDR(pPrt->PXaQOff, RB_CTRL), RB_RST_SET);
21602 /* Reset the RAM Buffer sync Tx queue */
21603 SK_OUT8(IoC, RB_ADDR(pPrt->PXsQOff, RB_CTRL), RB_RST_SET);
21604-
21605+
21606 /* Reset Tx MAC FIFO */
21607 #ifdef GENESIS
21608 if (pAC->GIni.GIGenesis) {
21609@@ -1243,74 +1643,132 @@
21610 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_DIS);
21611 }
21612 #endif /* GENESIS */
21613-
21614+
21615 #ifdef YUKON
21616 if (pAC->GIni.GIYukon) {
21617- /* Reset TX MAC FIFO */
21618- SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_SET);
21619+ /* do the reset only if ASF is not enabled */
21620+ if (!pAC->GIni.GIAsfEnabled) {
21621+ /* Reset Tx MAC FIFO */
21622+ SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_SET);
21623+ }
21624+
21625+ /* set Pause Off */
21626+ SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_PAUSE_OFF);
21627 }
21628 #endif /* YUKON */
21629 }
21630
21631 if ((Dir & SK_STOP_RX) != 0) {
21632- /*
21633- * The RX Stop Command will not terminate if no buffers
21634- * are queued in the RxD ring. But it will always reach
21635- * the Idle state. Therefore we can use this feature to
21636- * stop the transfer of received packets.
21637- */
21638- /* stop the port's receive queue */
21639- SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_STOP);
21640-
21641- i = 100;
21642- do {
21643+
21644+ if (CHIP_ID_YUKON_2(pAC)) {
21645 /*
21646- * Clear packet arbiter timeout to make sure
21647- * this loop will terminate
21648+ * The RX Stop command will not work for Yukon-2 if the BMU does not
21649+ * reach the end of packet and since we can't make sure that we have
21650+ * incoming data, we must reset the BMU while it is not during a DMA
21651+ * transfer. Since it is possible that the RX path is still active,
21652+ * the RX RAM buffer will be stopped first, so any possible incoming
21653+ * data will not trigger a DMA. After the RAM buffer is stopped, the
21654+ * BMU is polled until any DMA in progress is ended and only then it
21655+ * will be reset.
21656 */
21657- SK_OUT16(IoC, B3_PA_CTRL, (SK_U16)((Port == MAC_1) ?
21658- PA_CLR_TO_RX1 : PA_CLR_TO_RX2));
21659
21660- DWord = TestStopBit(pAC, IoC, pPrt->PRxQOff);
21661+ /* disable the RAM Buffer receive queue */
21662+ SK_OUT8(IoC, RB_ADDR(pPrt->PRxQOff, RB_CTRL), RB_DIS_OP_MD);
21663
21664- /* timeout if i==0 (bug fix for #10748) */
21665- if (--i == 0) {
21666- SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E024,
21667- SKERR_HWI_E024MSG);
21668- break;
21669+ i = 0xffff;
21670+ while (--i) {
21671+ SK_IN8(IoC, RB_ADDR(pPrt->PRxQOff, Q_RX_RSL), &rsl);
21672+ SK_IN8(IoC, RB_ADDR(pPrt->PRxQOff, Q_RX_RL), &rl);
21673+
21674+ if (rsl == rl) {
21675+ break;
21676+ }
21677 }
21678+
21679 /*
21680- * because of the ASIC problem report entry from 21.08.98
21681- * it is required to wait until CSR_STOP is reset and
21682- * CSR_SV_IDLE is set.
21683+ * If the Rx side is blocked, the above loop cannot terminate.
21684+ * But, if there was any traffic it should be terminated, now.
21685+ * However, stop the Rx BMU and the Prefetch Unit !
21686 */
21687- } while ((DWord & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE);
21688+ SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR),
21689+ BMU_RST_SET | BMU_FIFO_RST);
21690+ /* reset the Rx prefetch unit */
21691+ SK_OUT32(IoC, Y2_PREF_Q_ADDR(pPrt->PRxQOff, PREF_UNIT_CTRL_REG),
21692+ PREF_UNIT_RST_SET);
21693+ }
21694+ else {
21695+ /*
21696+ * The RX Stop Command will not terminate if no buffers
21697+ * are queued in the RxD ring. But it will always reach
21698+ * the Idle state. Therefore we can use this feature to
21699+ * stop the transfer of received packets.
21700+ */
21701+ /* stop the port's receive queue */
21702+ SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CsrStop);
21703+
21704+ i = 100;
21705+ do {
21706+#ifdef GENESIS
21707+ if (pAC->GIni.GIGenesis) {
21708+ /* clear Rx packet arbiter timeout IRQ */
21709+ SK_OUT16(IoC, B3_PA_CTRL, (SK_U16)((Port == MAC_1) ?
21710+ PA_CLR_TO_RX1 : PA_CLR_TO_RX2));
21711+ }
21712+#endif /* GENESIS */
21713
21714- /* The path data transfer activity is fully stopped now */
21715+ RxCsr = TestStopBit(pAC, IoC, pPrt->PRxQOff);
21716
21717- /* Perform a local reset of the port's Rx path */
21718+ /* timeout if i==0 (bug fix for #10748) */
21719+ if (--i == 0) {
21720+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E024,
21721+ SKERR_HWI_E024MSG);
21722+ break;
21723+ }
21724+ /*
21725+ * Because of the ASIC problem report entry from 21.08.1998 it is
21726+ * required to wait until CSR_STOP is reset and CSR_SV_IDLE is set.
21727+ * (valid for GENESIS only)
21728+ */
21729+ } while ((RxCsr & CsrTest) != CsrIdle);
21730+ /* The path data transfer activity is fully stopped now */
21731+
21732+ /* Perform a local reset of the port's Rx path */
21733+ /* Reset the PCI FIFO of the Rx queue */
21734+ SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_SET_RESET);
21735+ }
21736
21737- /* Reset the PCI FIFO of the Rx queue */
21738- SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_SET_RESET);
21739 /* Reset the RAM Buffer receive queue */
21740 SK_OUT8(IoC, RB_ADDR(pPrt->PRxQOff, RB_CTRL), RB_RST_SET);
21741
21742 /* Reset Rx MAC FIFO */
21743 #ifdef GENESIS
21744 if (pAC->GIni.GIGenesis) {
21745-
21746+
21747 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_SET);
21748
21749 /* switch Rx LED off, stop the LED counter */
21750 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, RX_LED_INI), SK_LED_DIS);
21751 }
21752 #endif /* GENESIS */
21753-
21754+
21755 #ifdef YUKON
21756- if (pAC->GIni.GIYukon) {
21757+ if (pAC->GIni.GIYukon && !pAC->GIni.GIAsfEnabled) {
21758 /* Reset Rx MAC FIFO */
21759 SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_RST_SET);
21760 }
21761+
21762+#ifndef NDIS_MINIPORT_DRIVER /* temp. ifndef, remove after PM module rework*/
21763+ /* WA for Dev. #4.169 */
21764+ if ((pAC->GIni.GIChipId == CHIP_ID_YUKON ||
21765+ pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) &&
21766+ RstMode == SK_HARD_RST) {
21767+ /* set Link Control reset */
21768+ SK_OUT8(IoC, MR_ADDR(Port, GMAC_LINK_CTRL), (SK_U8)GMLC_RST_SET);
21769+
21770+ /* clear Link Control reset */
21771+ SK_OUT8(IoC, MR_ADDR(Port, GMAC_LINK_CTRL), (SK_U8)GMLC_RST_CLR);
21772+ }
21773+#endif /* !NDIS_MINIPORT */
21774 #endif /* YUKON */
21775 }
21776 } /* SkGeStopPort */
21777@@ -1327,8 +1785,8 @@
21778 * nothing
21779 */
21780 static void SkGeInit0(
21781-SK_AC *pAC, /* adapter context */
21782-SK_IOC IoC) /* IO context */
21783+SK_AC *pAC, /* Adapter Context */
21784+SK_IOC IoC) /* I/O Context */
21785 {
21786 int i;
21787 SK_GEPORT *pPrt;
21788@@ -1337,6 +1795,7 @@
21789 pPrt = &pAC->GIni.GP[i];
21790
21791 pPrt->PState = SK_PRT_RESET;
21792+ pPrt->PPortUsage = SK_RED_LINK;
21793 pPrt->PRxQOff = QOffTab[i].RxQOff;
21794 pPrt->PXsQOff = QOffTab[i].XsQOff;
21795 pPrt->PXaQOff = QOffTab[i].XaQOff;
21796@@ -1365,22 +1824,225 @@
21797 pPrt->PLipaAutoNeg = (SK_U8)SK_LIPA_UNKNOWN;
21798 pPrt->PAutoNegFail = SK_FALSE;
21799 pPrt->PHWLinkUp = SK_FALSE;
21800- pPrt->PLinkBroken = SK_TRUE; /* See WA code */
21801+ pPrt->PLinkBroken = SK_TRUE; /* See WA code */
21802 pPrt->PPhyPowerState = PHY_PM_OPERATIONAL_MODE;
21803 pPrt->PMacColThres = TX_COL_DEF;
21804 pPrt->PMacJamLen = TX_JAM_LEN_DEF;
21805 pPrt->PMacJamIpgVal = TX_JAM_IPG_DEF;
21806 pPrt->PMacJamIpgData = TX_IPG_JAM_DEF;
21807+ pPrt->PMacBackOffLim = TX_BOF_LIM_DEF;
21808+ pPrt->PMacDataBlind = DATA_BLIND_DEF;
21809 pPrt->PMacIpgData = IPG_DATA_DEF;
21810 pPrt->PMacLimit4 = SK_FALSE;
21811 }
21812
21813- pAC->GIni.GIPortUsage = SK_RED_LINK;
21814 pAC->GIni.GILedBlinkCtrl = (SK_U16)OemConfig.Value;
21815- pAC->GIni.GIValIrqMask = IS_ALL_MSK;
21816+ pAC->GIni.GIChipCap = 0;
21817+
21818+ for (i = 0; i < 4; i++) {
21819+ pAC->GIni.HwF.Features[i]= 0x00000000;
21820+ pAC->GIni.HwF.OnMask[i] = 0x00000000;
21821+ pAC->GIni.HwF.OffMask[i] = 0x00000000;
21822+ }
21823
21824 } /* SkGeInit0*/
21825
21826+#ifdef SK_PCI_RESET
21827+/******************************************************************************
21828+ *
21829+ * SkGePciReset() - Reset PCI interface
21830+ *
21831+ * Description:
21832+ * o Read PCI configuration.
21833+ * o Change power state to 3.
21834+ * o Change power state to 0.
21835+ * o Restore PCI configuration.
21836+ *
21837+ * Returns:
21838+ * 0: Success.
21839+ * 1: Power state could not be changed to 3.
21840+ */
21841+static int SkGePciReset(
21842+SK_AC *pAC, /* Adapter Context */
21843+SK_IOC IoC) /* I/O Context */
21844+{
21845+ int i;
21846+ SK_U16 PmCtlSts;
21847+ SK_U32 Bp1;
21848+ SK_U32 Bp2;
21849+ SK_U16 PciCmd;
21850+ SK_U8 Cls;
21851+ SK_U8 Lat;
21852+ SK_U8 ConfigSpace[PCI_CFG_SIZE];
21853+
21854+ /*
21855+ * Note: Switching to D3 state is like a software reset.
21856+ * Switching from D3 to D0 is a hardware reset.
21857+ * We have to save and restore the configuration space.
21858+ */
21859+ for (i = 0; i < PCI_CFG_SIZE; i++) {
21860+ SkPciReadCfgDWord(pAC, i*4, &ConfigSpace[i]);
21861+ }
21862+
21863+ /* We know the RAM Interface Arbiter is enabled. */
21864+ SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D3);
21865+ SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);
21866+
21867+ if ((PmCtlSts & PCI_PM_STATE_MSK) != PCI_PM_STATE_D3) {
21868+ return(1);
21869+ }
21870+
21871+ /* Return to D0 state. */
21872+ SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D0);
21873+
21874+ /* Check for D0 state. */
21875+ SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);
21876+
21877+ if ((PmCtlSts & PCI_PM_STATE_MSK) != PCI_PM_STATE_D0) {
21878+ return(1);
21879+ }
21880+
21881+ /* Check PCI Config Registers. */
21882+ SkPciReadCfgWord(pAC, PCI_COMMAND, &PciCmd);
21883+ SkPciReadCfgByte(pAC, PCI_CACHE_LSZ, &Cls);
21884+ SkPciReadCfgDWord(pAC, PCI_BASE_1ST, &Bp1);
21885+
21886+ /*
21887+ * Compute the location in PCI config space of BAR2
21888+ * relativ to the location of BAR1
21889+ */
21890+ if ((Bp1 & PCI_MEM_TYP_MSK) == PCI_MEM64BIT) {
21891+ /* BAR1 is 64 bits wide */
21892+ i = 8;
21893+ }
21894+ else {
21895+ i = 4;
21896+ }
21897+
21898+ SkPciReadCfgDWord(pAC, PCI_BASE_1ST + i, &Bp2);
21899+ SkPciReadCfgByte(pAC, PCI_LAT_TIM, &Lat);
21900+
21901+ if (PciCmd != 0 || Cls != 0 || (Bp1 & 0xfffffff0L) != 0 || Bp2 != 1 ||
21902+ Lat != 0) {
21903+ return(1);
21904+ }
21905+
21906+ /* Restore PCI Config Space. */
21907+ for (i = 0; i < PCI_CFG_SIZE; i++) {
21908+ SkPciWriteCfgDWord(pAC, i*4, ConfigSpace[i]);
21909+ }
21910+
21911+ return(0);
21912+} /* SkGePciReset */
21913+#endif /* SK_PCI_RESET */
21914+
21915+
21916+#ifndef SK_SLIM
21917+/******************************************************************************
21918+ *
21919+ * SkGeSetUpSupFeatures() - Collect Feature List for HW_FEATURE Macro
21920+ *
21921+ * Description:
21922+ * This function collects the available features and required
21923+ * deviation services of the Adapter and provides these
21924+ * information in the GIHwF struct. This information is used as
21925+ * default value and may be overritten by the driver using the
21926+ * SET_HW_FEATURE_MASK() macro in its Init0 phase.
21927+ *
21928+ * Notice:
21929+ * Using the On and Off mask: Never switch on the same bit in both
21930+ * masks simultaneously. However, if doing the Off mask will win.
21931+ *
21932+ * Returns:
21933+ * nothing
21934+ */
21935+static void SkGeSetUpSupFeatures(
21936+SK_AC *pAC, /* Adapter Context */
21937+SK_IOC IoC) /* I/O Context */
21938+{
21939+ int i;
21940+ SK_U16 Word;
21941+
21942+ switch (pAC->GIni.GIChipId) {
21943+ case CHIP_ID_YUKON_EC:
21944+ if (pAC->GIni.GIChipRev == CHIP_REV_YU_EC_A1) {
21945+ /* A0/A1 */
21946+ pAC->GIni.HwF.Features[HW_DEV_LIST] =
21947+ HWF_WA_DEV_42 | HWF_WA_DEV_46 | HWF_WA_DEV_43_418 |
21948+ HWF_WA_DEV_420 | HWF_WA_DEV_423 |
21949+ HWF_WA_DEV_424 | HWF_WA_DEV_425 | HWF_WA_DEV_427 |
21950+ HWF_WA_DEV_428 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
21951+ HWF_WA_DEV_4152| HWF_WA_DEV_4167;
21952+ }
21953+ else {
21954+ /* A2/A3 */
21955+ pAC->GIni.HwF.Features[HW_DEV_LIST] =
21956+ HWF_WA_DEV_424 | HWF_WA_DEV_425 | HWF_WA_DEV_427 |
21957+ HWF_WA_DEV_428 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
21958+ HWF_WA_DEV_4152| HWF_WA_DEV_4167;
21959+ }
21960+ break;
21961+ case CHIP_ID_YUKON_FE:
21962+ pAC->GIni.HwF.Features[HW_DEV_LIST] =
21963+ HWF_WA_DEV_427 | HWF_WA_DEV_4109 |
21964+ HWF_WA_DEV_4152| HWF_WA_DEV_4167;
21965+ break;
21966+ case CHIP_ID_YUKON_XL:
21967+ switch (pAC->GIni.GIChipRev) {
21968+ case CHIP_REV_YU_XL_A0: /* still needed for Diag */
21969+ pAC->GIni.HwF.Features[HW_DEV_LIST] =
21970+ HWF_WA_DEV_427 | HWF_WA_DEV_463 | HWF_WA_DEV_472 |
21971+ HWF_WA_DEV_479 | HWF_WA_DEV_483 | HWF_WA_DEV_4115 |
21972+ HWF_WA_DEV_4152| HWF_WA_DEV_4167;
21973+ break;
21974+
21975+ case CHIP_REV_YU_XL_A1:
21976+ pAC->GIni.HwF.Features[HW_DEV_LIST] =
21977+ HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
21978+ HWF_WA_DEV_4115| HWF_WA_DEV_4152| HWF_WA_DEV_4167;
21979+ break;
21980+
21981+ case CHIP_REV_YU_XL_A2:
21982+ pAC->GIni.HwF.Features[HW_DEV_LIST] =
21983+ HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
21984+ HWF_WA_DEV_4115 | HWF_WA_DEV_4167;
21985+ break;
21986+
21987+ case CHIP_REV_YU_XL_A3:
21988+ pAC->GIni.HwF.Features[HW_DEV_LIST] =
21989+ HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
21990+ HWF_WA_DEV_4115;
21991+ break;
21992+ }
21993+ break;
21994+ case CHIP_ID_YUKON_EC_U:
21995+ if (pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A0) {
21996+ pAC->GIni.HwF.Features[HW_DEV_LIST] =
21997+ HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109;
21998+ }
21999+ else if (pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A1) {
22000+ pAC->GIni.HwF.Features[HW_DEV_LIST] =
22001+ HWF_WA_DEV_427 | HWF_WA_DEV_4109 | HWF_WA_DEV_4185;
22002+
22003+ /* check for Rev. A1 */
22004+ SK_IN16(IoC, Q_ADDR(Q_XA1, Q_WM), &Word);
22005+
22006+ if (Word == 0) {
22007+ pAC->GIni.HwF.Features[HW_DEV_LIST] |=
22008+ HWF_WA_DEV_4185CS | HWF_WA_DEV_4200;
22009+ }
22010+ }
22011+ break;
22012+ }
22013+
22014+ for (i = 0; i < 4; i++) {
22015+ pAC->GIni.HwF.Features[i] =
22016+ (pAC->GIni.HwF.Features[i] | pAC->GIni.HwF.OnMask[i]) &
22017+ ~pAC->GIni.HwF.OffMask[i];
22018+ }
22019+} /* SkGeSetUpSupFeatures */
22020+#endif /* !SK_SLIM */
22021+
22022
22023 /******************************************************************************
22024 *
22025@@ -1404,76 +2066,253 @@
22026 * 6: HW self test failed
22027 */
22028 static int SkGeInit1(
22029-SK_AC *pAC, /* adapter context */
22030-SK_IOC IoC) /* IO context */
22031+SK_AC *pAC, /* Adapter Context */
22032+SK_IOC IoC) /* I/O Context */
22033 {
22034 SK_U8 Byte;
22035 SK_U16 Word;
22036- SK_U16 CtrlStat;
22037+ SK_U32 CtrlStat;
22038+ SK_U32 VauxAvail;
22039 SK_U32 DWord;
22040+ SK_U32 Our1;
22041+ SK_U32 PowerDownBit;
22042+ SK_BOOL FiberType;
22043+ SK_GEPORT *pPrt;
22044 int RetVal;
22045- int i;
22046+ int i, j;
22047
22048 RetVal = 0;
22049
22050- /* save CLK_RUN bits (YUKON-Lite) */
22051- SK_IN16(IoC, B0_CTST, &CtrlStat);
22052+ /* save CLK_RUN & ASF_ENABLE bits (YUKON-Lite, YUKON-EC) */
22053+ SK_IN32(IoC, B0_CTST, &CtrlStat);
22054
22055- /* do the SW-reset */
22056- SK_OUT8(IoC, B0_CTST, CS_RST_SET);
22057+#ifdef SK_PCI_RESET
22058+ (void)SkGePciReset(pAC, IoC);
22059+#endif /* SK_PCI_RESET */
22060
22061 /* release the SW-reset */
22062+ /* Important: SW-reset has to be cleared here, to ensure
22063+ * the CHIP_ID can be read IO-mapped based, too -
22064+ * remember the RAP register can only be written if
22065+ * SW-reset is cleared.
22066+ */
22067 SK_OUT8(IoC, B0_CTST, CS_RST_CLR);
22068
22069+ /* read Chip Identification Number */
22070+ SK_IN8(IoC, B2_CHIP_ID, &Byte);
22071+ pAC->GIni.GIChipId = Byte;
22072+
22073+ pAC->GIni.GIAsfEnabled = SK_FALSE;
22074+
22075+ /* ASF support only for Yukon-2 */
22076+ if ((pAC->GIni.GIChipId >= CHIP_ID_YUKON_XL) &&
22077+ (pAC->GIni.GIChipId <= CHIP_ID_YUKON_EC)) {
22078+#ifdef SK_ASF
22079+ if ((CtrlStat & Y2_ASF_ENABLE) != 0) {
22080+ /* do the SW-reset only if ASF is not enabled */
22081+ pAC->GIni.GIAsfEnabled = SK_TRUE;
22082+ }
22083+#else /* !SK_ASF */
22084+
22085+ SK_IN8(IoC, B28_Y2_ASF_STAT_CMD, &Byte);
22086+
22087+ pAC->GIni.GIAsfRunning = Byte & Y2_ASF_RUNNING;
22088+
22089+ /* put ASF system in reset state */
22090+ SK_OUT8(IoC, B28_Y2_ASF_STAT_CMD, (SK_U8)Y2_ASF_RESET);
22091+
22092+ /* disable ASF Unit */
22093+ SK_OUT16(IoC, B0_CTST, Y2_ASF_DISABLE);
22094+#endif /* !SK_ASF */
22095+ }
22096+
22097+ if (!pAC->GIni.GIAsfEnabled) {
22098+ /* Yukon-2: required for Diag and Power Management */
22099+ /* set the SW-reset */
22100+ SK_OUT8(IoC, B0_CTST, CS_RST_SET);
22101+
22102+ /* release the SW-reset */
22103+ SK_OUT8(IoC, B0_CTST, CS_RST_CLR);
22104+ }
22105+
22106+ /* enable Config Write */
22107+ SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
22108+
22109 /* reset all error bits in the PCI STATUS register */
22110 /*
22111 * Note: PCI Cfg cycles cannot be used, because they are not
22112 * available on some platforms after 'boot time'.
22113 */
22114- SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);
22115-
22116- SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
22117- SK_OUT16(IoC, PCI_C(PCI_STATUS), (SK_U16)(Word | PCI_ERRBITS));
22118- SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
22119+ SK_IN16(IoC, PCI_C(pAC, PCI_STATUS), &Word);
22120+
22121+ SK_OUT16(IoC, PCI_C(pAC, PCI_STATUS), Word | (SK_U16)PCI_ERRBITS);
22122
22123 /* release Master Reset */
22124 SK_OUT8(IoC, B0_CTST, CS_MRST_CLR);
22125
22126 #ifdef CLK_RUN
22127 CtrlStat |= CS_CLK_RUN_ENA;
22128-#endif /* CLK_RUN */
22129
22130 /* restore CLK_RUN bits */
22131 SK_OUT16(IoC, B0_CTST, (SK_U16)(CtrlStat &
22132 (CS_CLK_RUN_HOT | CS_CLK_RUN_RST | CS_CLK_RUN_ENA)));
22133+#endif /* CLK_RUN */
22134+
22135+ if ((pAC->GIni.GIChipId >= CHIP_ID_YUKON_XL) &&
22136+ (pAC->GIni.GIChipId <= CHIP_ID_YUKON_FE)) {
22137+
22138+ pAC->GIni.GIYukon2 = SK_TRUE;
22139+ pAC->GIni.GIValIrqMask = Y2_IS_ALL_MSK;
22140+ pAC->GIni.GIValHwIrqMask = Y2_HWE_ALL_MSK;
22141+
22142+ VauxAvail = Y2_VAUX_AVAIL;
22143+
22144+ SK_IN32(IoC, PCI_C(pAC, PCI_OUR_STATUS), &DWord);
22145+
22146+ if ((DWord & PCI_OS_PCI_X) != 0) {
22147+#ifndef SK_SLIM
22148+ /* this is a PCI / PCI-X bus */
22149+ if ((DWord & PCI_OS_PCIX) != 0) {
22150+ /* this is a PCI-X bus */
22151+ pAC->GIni.GIPciBus = SK_PCIX_BUS;
22152+
22153+ /* PCI-X is always 64-bit wide */
22154+ pAC->GIni.GIPciSlot64 = SK_TRUE;
22155+
22156+ pAC->GIni.GIPciMode = (SK_U8)(PCI_OS_SPEED(DWord));
22157+ }
22158+ else {
22159+ /* this is a conventional PCI bus */
22160+ pAC->GIni.GIPciBus = SK_PCI_BUS;
22161+
22162+ SK_IN16(IoC, PCI_C(pAC, PCI_OUR_REG_2), &Word);
22163+
22164+ /* check if 64-bit width is used */
22165+ pAC->GIni.GIPciSlot64 = (SK_BOOL)
22166+ (((DWord & PCI_OS_PCI64B) != 0) &&
22167+ ((Word & PCI_USEDATA64) != 0));
22168+
22169+ /* check if 66 MHz PCI Clock is active */
22170+ pAC->GIni.GIPciClock66 = (SK_BOOL)((DWord & PCI_OS_PCI66M) != 0);
22171+ }
22172+#endif /* !SK_SLIM */
22173+ }
22174+ else {
22175+ /* this is a PEX bus */
22176+ pAC->GIni.GIPciBus = SK_PEX_BUS;
22177+
22178+ /* clear any PEX errors */
22179+ SK_OUT32(IoC, PCI_C(pAC, PEX_UNC_ERR_STAT), 0xffffffffUL);
22180+
22181+ SK_IN32(IoC, PCI_C(pAC, PEX_UNC_ERR_STAT), &DWord);
22182+
22183+ if ((DWord & PEX_RX_OV) != 0) {
22184+ /* Dev #4.205 occured */
22185+ pAC->GIni.GIValHwIrqMask &= ~Y2_IS_PCI_EXP;
22186+ pAC->GIni.GIValIrqMask &= ~Y2_IS_HW_ERR;
22187+ }
22188+
22189+ SK_IN16(IoC, PCI_C(pAC, PEX_LNK_STAT), &Word);
22190+
22191+ pAC->GIni.GIPexWidth = (SK_U8)((Word & PEX_LS_LINK_WI_MSK) >> 4);
22192+ }
22193+ /*
22194+ * Yukon-2 chips family has a different way of providing
22195+ * the number of MACs available
22196+ */
22197+ pAC->GIni.GIMacsFound = 1;
22198+
22199+ /* get HW Resources */
22200+ SK_IN8(IoC, B2_Y2_HW_RES, &Byte);
22201+
22202+ if (CHIP_ID_YUKON_2(pAC)) {
22203+ /*
22204+ * OEM config value is overwritten and should not
22205+ * be used for Yukon-2
22206+ */
22207+ pAC->GIni.GILedBlinkCtrl |= SK_ACT_LED_BLINK;
22208+
22209+#ifndef SK_SLIM
22210+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) {
22211+ /* LED Configuration is stored in GPIO */
22212+ SK_IN8(IoC, B2_GP_IO, &Byte);
22213+
22214+ if (CFG_LED_MODE(Byte) == CFG_LED_LINK_MUX_P60) {
22215+
22216+ pAC->GIni.GILedBlinkCtrl |= SK_LED_LINK_MUX_P60;
22217+ }
22218+ }
22219+#endif /* !SK_SLIM */
22220+
22221+ if (CFG_LED_MODE(Byte) == CFG_LED_DUAL_ACT_LNK) {
22222+
22223+ pAC->GIni.GILedBlinkCtrl |= SK_DUAL_LED_ACT_LNK;
22224+ }
22225+ }
22226+
22227+ /* save HW Resources / Application Information */
22228+ pAC->GIni.GIHwResInfo = Byte;
22229+
22230+ if ((Byte & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
22231+
22232+ SK_IN8(IoC, B2_Y2_CLK_GATE, &Byte);
22233+
22234+ if (!(Byte & Y2_STATUS_LNK2_INAC)) {
22235+ /* Link 2 activ */
22236+ pAC->GIni.GIMacsFound++;
22237+ }
22238+ }
22239+
22240+#ifdef VCPU
22241+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL) {
22242+ /* temporary WA for reported number of links */
22243+ pAC->GIni.GIMacsFound = 2;
22244+ }
22245+#endif /* VCPU */
22246+
22247+ /* read Chip Revision */
22248+ SK_IN8(IoC, B2_MAC_CFG, &Byte);
22249+
22250+ pAC->GIni.GIChipCap = Byte & 0x0f;
22251+ }
22252+ else {
22253+ pAC->GIni.GIYukon2 = SK_FALSE;
22254+ pAC->GIni.GIValIrqMask = IS_ALL_MSK;
22255+ pAC->GIni.GIValHwIrqMask = 0; /* not activated */
22256+
22257+ VauxAvail = CS_VAUX_AVAIL;
22258+
22259+ /* read number of MACs and Chip Revision */
22260+ SK_IN8(IoC, B2_MAC_CFG, &Byte);
22261+
22262+ pAC->GIni.GIMacsFound = (Byte & CFG_SNG_MAC) ? 1 : 2;
22263+ }
22264
22265- /* read Chip Identification Number */
22266- SK_IN8(IoC, B2_CHIP_ID, &Byte);
22267- pAC->GIni.GIChipId = Byte;
22268-
22269- /* read number of MACs */
22270- SK_IN8(IoC, B2_MAC_CFG, &Byte);
22271- pAC->GIni.GIMacsFound = (Byte & CFG_SNG_MAC) ? 1 : 2;
22272-
22273 /* get Chip Revision Number */
22274 pAC->GIni.GIChipRev = (SK_U8)((Byte & CFG_CHIP_R_MSK) >> 4);
22275
22276- /* get diff. PCI parameters */
22277- SK_IN16(IoC, B0_CTST, &CtrlStat);
22278-
22279+#ifndef SK_DIAG
22280+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL &&
22281+ pAC->GIni.GIChipRev == CHIP_REV_YU_XL_A0) {
22282+ /* Yukon-2 Chip Rev. A0 */
22283+ return(6);
22284+ }
22285+#endif /* !SK_DIAG */
22286+
22287 /* read the adapters RAM size */
22288 SK_IN8(IoC, B2_E_0, &Byte);
22289-
22290+
22291 pAC->GIni.GIGenesis = SK_FALSE;
22292 pAC->GIni.GIYukon = SK_FALSE;
22293 pAC->GIni.GIYukonLite = SK_FALSE;
22294+ pAC->GIni.GIVauxAvail = SK_FALSE;
22295
22296 #ifdef GENESIS
22297 if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
22298
22299 pAC->GIni.GIGenesis = SK_TRUE;
22300
22301- if (Byte == (SK_U8)3) {
22302+ if (Byte == (SK_U8)3) {
22303 /* special case: 4 x 64k x 36, offset = 0x80000 */
22304 pAC->GIni.GIRamSize = 1024;
22305 pAC->GIni.GIRamOffs = (SK_U32)512 * 1024;
22306@@ -1482,57 +2321,83 @@
22307 pAC->GIni.GIRamSize = (int)Byte * 512;
22308 pAC->GIni.GIRamOffs = 0;
22309 }
22310- /* all GE adapters work with 53.125 MHz host clock */
22311+ /* all GENESIS adapters work with 53.125 MHz host clock */
22312 pAC->GIni.GIHstClkFact = SK_FACT_53;
22313-
22314+
22315 /* set Descr. Poll Timer Init Value to 250 ms */
22316 pAC->GIni.GIPollTimerVal =
22317 SK_DPOLL_DEF * (SK_U32)pAC->GIni.GIHstClkFact / 100;
22318 }
22319 #endif /* GENESIS */
22320-
22321+
22322 #ifdef YUKON
22323 if (pAC->GIni.GIChipId != CHIP_ID_GENESIS) {
22324-
22325+
22326 pAC->GIni.GIYukon = SK_TRUE;
22327-
22328+
22329 pAC->GIni.GIRamSize = (Byte == (SK_U8)0) ? 128 : (int)Byte * 4;
22330-
22331+
22332+#ifndef SK_SLIM
22333 pAC->GIni.GIRamOffs = 0;
22334-
22335- /* WA for chip Rev. A */
22336+
22337+ /* WA for Yukon chip Rev. A */
22338 pAC->GIni.GIWolOffs = (pAC->GIni.GIChipId == CHIP_ID_YUKON &&
22339 pAC->GIni.GIChipRev == 0) ? WOL_REG_OFFS : 0;
22340-
22341+
22342 /* get PM Capabilities of PCI config space */
22343- SK_IN16(IoC, PCI_C(PCI_PM_CAP_REG), &Word);
22344+ SK_IN16(IoC, PCI_C(pAC, PCI_PM_CAP_REG), &Word);
22345
22346 /* check if VAUX is available */
22347- if (((CtrlStat & CS_VAUX_AVAIL) != 0) &&
22348+ if (((CtrlStat & VauxAvail) != 0) &&
22349 /* check also if PME from D3cold is set */
22350 ((Word & PCI_PME_D3C_SUP) != 0)) {
22351 /* set entry in GE init struct */
22352 pAC->GIni.GIVauxAvail = SK_TRUE;
22353 }
22354-
22355- if (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) {
22356- /* this is Rev. A1 */
22357- pAC->GIni.GIYukonLite = SK_TRUE;
22358- }
22359- else {
22360- /* save Flash-Address Register */
22361- SK_IN32(IoC, B2_FAR, &DWord);
22362+#endif /* !SK_SLIM */
22363
22364- /* test Flash-Address Register */
22365- SK_OUT8(IoC, B2_FAR + 3, 0xff);
22366- SK_IN8(IoC, B2_FAR + 3, &Byte);
22367+ if (!CHIP_ID_YUKON_2(pAC)) {
22368
22369- if (Byte != 0) {
22370- /* this is Rev. A0 */
22371+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) {
22372+ /* this is Rev. A1 */
22373 pAC->GIni.GIYukonLite = SK_TRUE;
22374+ }
22375+#ifndef SK_SLIM
22376+ else {
22377+ /* save Flash-Address Register */
22378+ SK_IN32(IoC, B2_FAR, &DWord);
22379+
22380+ /* test Flash-Address Register */
22381+ SK_OUT8(IoC, B2_FAR + 3, 0xff);
22382+ SK_IN8(IoC, B2_FAR + 3, &Byte);
22383+
22384+ if (Byte != 0) {
22385+ /* this is Rev. A0 */
22386+ pAC->GIni.GIYukonLite = SK_TRUE;
22387+
22388+ /* restore Flash-Address Register */
22389+ SK_OUT32(IoC, B2_FAR, DWord);
22390+ }
22391+ }
22392+#endif /* !SK_SLIM */
22393+ }
22394+ else {
22395+ /* Check for CLS = 0 (dev. #4.55) */
22396+ if (pAC->GIni.GIPciBus != SK_PEX_BUS) {
22397+ /* PCI and PCI-X */
22398+ SK_IN8(IoC, PCI_C(pAC, PCI_CACHE_LSZ), &Byte);
22399+
22400+ if (Byte == 0) {
22401+ /* set CLS to 2 if configured to 0 */
22402+ SK_OUT8(IoC, PCI_C(pAC, PCI_CACHE_LSZ), 2);
22403+ }
22404
22405- /* restore Flash-Address Register */
22406- SK_OUT32(IoC, B2_FAR, DWord);
22407+ if (pAC->GIni.GIPciBus == SK_PCIX_BUS) {
22408+ /* set Cache Line Size opt. */
22409+ SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_1), &DWord);
22410+ DWord |= PCI_CLS_OPT;
22411+ SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_1), DWord);
22412+ }
22413 }
22414 }
22415
22416@@ -1540,138 +2405,282 @@
22417 SK_OUT8(IoC, B0_POWER_CTRL, (SK_U8)(PC_VAUX_ENA | PC_VCC_ENA |
22418 PC_VAUX_OFF | PC_VCC_ON));
22419
22420- /* read the Interrupt source */
22421- SK_IN32(IoC, B0_ISRC, &DWord);
22422-
22423- if ((DWord & IS_HW_ERR) != 0) {
22424- /* read the HW Error Interrupt source */
22425- SK_IN32(IoC, B0_HWE_ISRC, &DWord);
22426-
22427- if ((DWord & IS_IRQ_SENSOR) != 0) {
22428- /* disable HW Error IRQ */
22429- pAC->GIni.GIValIrqMask &= ~IS_HW_ERR;
22430+ Byte = 0;
22431+
22432+ if (CHIP_ID_YUKON_2(pAC)) {
22433+ switch (pAC->GIni.GIChipId) {
22434+ /* PEX adapters work with different host clock */
22435+ case CHIP_ID_YUKON_EC:
22436+ case CHIP_ID_YUKON_EC_U:
22437+ /* Yukon-EC works with 125 MHz host clock */
22438+ pAC->GIni.GIHstClkFact = SK_FACT_125;
22439+ break;
22440+ case CHIP_ID_YUKON_FE:
22441+ /* Yukon-FE works with 100 MHz host clock */
22442+ pAC->GIni.GIHstClkFact = SK_FACT_100;
22443+ break;
22444+ case CHIP_ID_YUKON_XL:
22445+ /* all Yukon-2 adapters work with 156 MHz host clock */
22446+ pAC->GIni.GIHstClkFact = 2 * SK_FACT_78;
22447+
22448+ if (pAC->GIni.GIChipRev > CHIP_REV_YU_XL_A1) {
22449+ /* enable bits are inverted */
22450+ Byte = (SK_U8)(Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
22451+ Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
22452+ Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
22453+ }
22454+ break;
22455+ default:
22456+ SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E006,
22457+ SKERR_HWI_E006MSG);
22458+ }
22459+
22460+ pAC->GIni.GIPollTimerVal =
22461+ SK_DPOLL_DEF_Y2 * (SK_U32)pAC->GIni.GIHstClkFact / 100;
22462+
22463+ /* set power down bit */
22464+ PowerDownBit = PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD;
22465+
22466+ /* disable Core Clock Division, set Clock Select to 0 (Yukon-2) */
22467+ SK_OUT32(IoC, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
22468+
22469+ /* enable MAC/PHY, PCI and Core Clock for both Links */
22470+ SK_OUT8(IoC, B2_Y2_CLK_GATE, Byte);
22471+ }
22472+ else {
22473+ /* YUKON adapters work with 78 MHz host clock */
22474+ pAC->GIni.GIHstClkFact = SK_FACT_78;
22475+
22476+ pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX; /* 215 ms */
22477+
22478+ /* read the Interrupt source */
22479+ SK_IN32(IoC, B0_ISRC, &DWord);
22480+
22481+ if ((DWord & IS_HW_ERR) != 0) {
22482+ /* read the HW Error Interrupt source */
22483+ SK_IN32(IoC, B0_HWE_ISRC, &DWord);
22484+
22485+ if ((DWord & IS_IRQ_SENSOR) != 0) {
22486+ /* disable HW Error IRQ */
22487+ pAC->GIni.GIValIrqMask &= ~IS_HW_ERR;
22488+ }
22489 }
22490+ /* set power down bit */
22491+ PowerDownBit = PCI_PHY_COMA;
22492 }
22493-
22494- for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
22495- /* set GMAC Link Control reset */
22496- SK_OUT16(IoC, MR_ADDR(i, GMAC_LINK_CTRL), GMLC_RST_SET);
22497
22498- /* clear GMAC Link Control reset */
22499- SK_OUT16(IoC, MR_ADDR(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
22500+ SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_1), &Our1);
22501+
22502+ Our1 &= ~PowerDownBit;
22503+
22504+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL &&
22505+ pAC->GIni.GIChipRev > CHIP_REV_YU_XL_A1) {
22506+ /* deassert Low Power for 1st PHY */
22507+ Our1 |= PCI_Y2_PHY1_COMA;
22508+
22509+ if (pAC->GIni.GIMacsFound > 1) {
22510+ /* deassert Low Power for 2nd PHY */
22511+ Our1 |= PCI_Y2_PHY2_COMA;
22512+ }
22513+ }
22514+ else if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) {
22515+ /* enable HW WOL */
22516+ SK_OUT16(IoC, B0_CTST, (SK_U16)Y2_HW_WOL_ON);
22517+
22518+ /* enable all clocks */
22519+ SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_3), 0);
22520+
22521+ SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_4), &DWord);
22522+
22523+ DWord &= P_ASPM_CONTROL_MSK;
22524+ /* set all bits to 0 except bits 15..12 */
22525+ SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_4), DWord);
22526+
22527+ /* set to default value */
22528+ SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_5), 0);
22529+ }
22530+
22531+ /* release PHY from PowerDown/COMA Mode */
22532+ SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_1), Our1);
22533+
22534+ if (!pAC->GIni.GIAsfEnabled) {
22535+
22536+ for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
22537+ /* set Link Control reset */
22538+ SK_OUT8(IoC, MR_ADDR(i, GMAC_LINK_CTRL), (SK_U8)GMLC_RST_SET);
22539+
22540+ /* clear Link Control reset */
22541+ SK_OUT8(IoC, MR_ADDR(i, GMAC_LINK_CTRL), (SK_U8)GMLC_RST_CLR);
22542+ }
22543 }
22544- /* all YU chips work with 78.125 MHz host clock */
22545- pAC->GIni.GIHstClkFact = SK_FACT_78;
22546-
22547- pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX; /* 215 ms */
22548 }
22549 #endif /* YUKON */
22550
22551- /* check if 64-bit PCI Slot is present */
22552- pAC->GIni.GIPciSlot64 = (SK_BOOL)((CtrlStat & CS_BUS_SLOT_SZ) != 0);
22553-
22554- /* check if 66 MHz PCI Clock is active */
22555- pAC->GIni.GIPciClock66 = (SK_BOOL)((CtrlStat & CS_BUS_CLOCK) != 0);
22556+ SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
22557+
22558+#ifndef SK_SLIM
22559+ if (!CHIP_ID_YUKON_2(pAC)) {
22560+ /* this is a conventional PCI bus */
22561+ pAC->GIni.GIPciBus = SK_PCI_BUS;
22562+
22563+ /* check if 64-bit PCI Slot is present */
22564+ pAC->GIni.GIPciSlot64 = (SK_BOOL)((CtrlStat & CS_BUS_SLOT_SZ) != 0);
22565+
22566+ /* check if 66 MHz PCI Clock is active */
22567+ pAC->GIni.GIPciClock66 = (SK_BOOL)((CtrlStat & CS_BUS_CLOCK) != 0);
22568+ }
22569
22570 /* read PCI HW Revision Id. */
22571- SK_IN8(IoC, PCI_C(PCI_REV_ID), &Byte);
22572+ SK_IN8(IoC, PCI_C(pAC, PCI_REV_ID), &Byte);
22573 pAC->GIni.GIPciHwRev = Byte;
22574
22575+ /* read connector type */
22576+ SK_IN8(IoC, B2_CONN_TYP, &pAC->GIni.GIConTyp);
22577+#endif /* !SK_SLIM */
22578+
22579 /* read the PMD type */
22580 SK_IN8(IoC, B2_PMD_TYP, &Byte);
22581- pAC->GIni.GICopperType = (SK_U8)(Byte == 'T');
22582
22583- /* read the PHY type */
22584+ pAC->GIni.GIPmdTyp = Byte;
22585+
22586+ FiberType = (Byte == 'L' || Byte == 'S' || Byte == 'P');
22587+
22588+ pAC->GIni.GICopperType = (SK_BOOL)(Byte == 'T' || Byte == '1' ||
22589+ (pAC->GIni.GIYukon2 && !FiberType));
22590+
22591+ /* read the PHY type (Yukon and Genesis) */
22592 SK_IN8(IoC, B2_E_1, &Byte);
22593
22594 Byte &= 0x0f; /* the PHY type is stored in the lower nibble */
22595 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
22596-
22597+
22598+ pPrt = &pAC->GIni.GP[i];
22599+
22600+ /* get the MAC addresses */
22601+ for (j = 0; j < 3; j++) {
22602+ SK_IN16(IoC, B2_MAC_1 + i * 8 + j * 2, &pPrt->PMacAddr[j]);
22603+ }
22604+
22605 #ifdef GENESIS
22606 if (pAC->GIni.GIGenesis) {
22607 switch (Byte) {
22608 case SK_PHY_XMAC:
22609- pAC->GIni.GP[i].PhyAddr = PHY_ADDR_XMAC;
22610+ pPrt->PhyAddr = PHY_ADDR_XMAC;
22611 break;
22612 case SK_PHY_BCOM:
22613- pAC->GIni.GP[i].PhyAddr = PHY_ADDR_BCOM;
22614- pAC->GIni.GP[i].PMSCap = (SK_U8)(SK_MS_CAP_AUTO |
22615+ pPrt->PhyAddr = PHY_ADDR_BCOM;
22616+ pPrt->PMSCap = (SK_U8)(SK_MS_CAP_AUTO |
22617 SK_MS_CAP_MASTER | SK_MS_CAP_SLAVE);
22618 break;
22619 #ifdef OTHER_PHY
22620 case SK_PHY_LONE:
22621- pAC->GIni.GP[i].PhyAddr = PHY_ADDR_LONE;
22622+ pPrt->PhyAddr = PHY_ADDR_LONE;
22623 break;
22624 case SK_PHY_NAT:
22625- pAC->GIni.GP[i].PhyAddr = PHY_ADDR_NAT;
22626+ pPrt->PhyAddr = PHY_ADDR_NAT;
22627 break;
22628 #endif /* OTHER_PHY */
22629 default:
22630 /* ERROR: unexpected PHY type detected */
22631 RetVal = 5;
22632- break;
22633 }
22634 }
22635 #endif /* GENESIS */
22636-
22637+
22638 #ifdef YUKON
22639 if (pAC->GIni.GIYukon) {
22640-
22641- if (Byte < (SK_U8)SK_PHY_MARV_COPPER) {
22642+
22643+ if (((Byte < (SK_U8)SK_PHY_MARV_COPPER) || pAC->GIni.GIYukon2) &&
22644+ !FiberType) {
22645 /* if this field is not initialized */
22646 Byte = (SK_U8)SK_PHY_MARV_COPPER;
22647-
22648+
22649 pAC->GIni.GICopperType = SK_TRUE;
22650 }
22651-
22652- pAC->GIni.GP[i].PhyAddr = PHY_ADDR_MARV;
22653-
22654+
22655+ pPrt->PhyAddr = PHY_ADDR_MARV;
22656+
22657 if (pAC->GIni.GICopperType) {
22658
22659- pAC->GIni.GP[i].PLinkSpeedCap = (SK_U8)(SK_LSPEED_CAP_AUTO |
22660- SK_LSPEED_CAP_10MBPS | SK_LSPEED_CAP_100MBPS |
22661- SK_LSPEED_CAP_1000MBPS);
22662-
22663- pAC->GIni.GP[i].PLinkSpeed = (SK_U8)SK_LSPEED_AUTO;
22664-
22665- pAC->GIni.GP[i].PMSCap = (SK_U8)(SK_MS_CAP_AUTO |
22666+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE ||
22667+ (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC &&
22668+ pAC->GIni.GIChipCap == 2)) {
22669+
22670+ pPrt->PLinkSpeedCap = (SK_U8)(SK_LSPEED_CAP_100MBPS |
22671+ SK_LSPEED_CAP_10MBPS);
22672+
22673+ pAC->GIni.GIRamSize = 4;
22674+ }
22675+ else {
22676+ pPrt->PLinkSpeedCap = (SK_U8)(SK_LSPEED_CAP_1000MBPS |
22677+ SK_LSPEED_CAP_100MBPS | SK_LSPEED_CAP_10MBPS |
22678+ SK_LSPEED_CAP_AUTO);
22679+ }
22680+
22681+ pPrt->PLinkSpeed = (SK_U8)SK_LSPEED_AUTO;
22682+
22683+ pPrt->PMSCap = (SK_U8)(SK_MS_CAP_AUTO |
22684 SK_MS_CAP_MASTER | SK_MS_CAP_SLAVE);
22685 }
22686 else {
22687 Byte = (SK_U8)SK_PHY_MARV_FIBER;
22688 }
22689 }
22690+
22691+ /* clear TWSI IRQ */
22692+ SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
22693+
22694 #endif /* YUKON */
22695-
22696- pAC->GIni.GP[i].PhyType = (int)Byte;
22697-
22698+
22699+ pPrt->PhyType = (int)Byte;
22700+
22701 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
22702- ("PHY type: %d PHY addr: %04x\n", Byte,
22703- pAC->GIni.GP[i].PhyAddr));
22704+ ("PHY type: %d PHY addr: %04x\n",
22705+ Byte, pPrt->PhyAddr));
22706 }
22707-
22708+
22709 /* get MAC Type & set function pointers dependent on */
22710 #ifdef GENESIS
22711 if (pAC->GIni.GIGenesis) {
22712-
22713+
22714 pAC->GIni.GIMacType = SK_MAC_XMAC;
22715
22716 pAC->GIni.GIFunc.pFnMacUpdateStats = SkXmUpdateStats;
22717 pAC->GIni.GIFunc.pFnMacStatistic = SkXmMacStatistic;
22718 pAC->GIni.GIFunc.pFnMacResetCounter = SkXmResetCounter;
22719 pAC->GIni.GIFunc.pFnMacOverflow = SkXmOverflowStatus;
22720+#ifdef SK_DIAG
22721+ pAC->GIni.GIFunc.pFnMacPhyRead = SkXmPhyRead;
22722+ pAC->GIni.GIFunc.pFnMacPhyWrite = SkXmPhyWrite;
22723+#else /* SK_DIAG */
22724+ pAC->GIni.GIFunc.pSkGeSirqIsr = SkGeYuSirqIsr;
22725+#endif /* !SK_DIAG */
22726 }
22727 #endif /* GENESIS */
22728-
22729+
22730 #ifdef YUKON
22731 if (pAC->GIni.GIYukon) {
22732-
22733+
22734+#ifndef SK_SLIM
22735 pAC->GIni.GIMacType = SK_MAC_GMAC;
22736
22737 pAC->GIni.GIFunc.pFnMacUpdateStats = SkGmUpdateStats;
22738 pAC->GIni.GIFunc.pFnMacStatistic = SkGmMacStatistic;
22739 pAC->GIni.GIFunc.pFnMacResetCounter = SkGmResetCounter;
22740 pAC->GIni.GIFunc.pFnMacOverflow = SkGmOverflowStatus;
22741+#endif /* !SK_SLIM */
22742+
22743+#ifdef SK_DIAG
22744+ pAC->GIni.GIFunc.pFnMacPhyRead = SkGmPhyRead;
22745+ pAC->GIni.GIFunc.pFnMacPhyWrite = SkGmPhyWrite;
22746+#else /* SK_DIAG */
22747+ if (CHIP_ID_YUKON_2(pAC)) {
22748+ pAC->GIni.GIFunc.pSkGeSirqIsr = SkYuk2SirqIsr;
22749+ }
22750+ else {
22751+ pAC->GIni.GIFunc.pSkGeSirqIsr = SkGeYuSirqIsr;
22752+ }
22753+#endif /* !SK_DIAG */
22754
22755 #ifdef SPECIAL_HANDLING
22756 if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {
22757@@ -1684,7 +2693,13 @@
22758 #endif
22759 }
22760 #endif /* YUKON */
22761-
22762+
22763+#ifndef SK_SLIM
22764+
22765+ SkGeSetUpSupFeatures(pAC, IoC);
22766+
22767+#endif /* !SK_SLIM */
22768+
22769 return(RetVal);
22770 } /* SkGeInit1 */
22771
22772@@ -1705,9 +2720,15 @@
22773 * nothing
22774 */
22775 static void SkGeInit2(
22776-SK_AC *pAC, /* adapter context */
22777-SK_IOC IoC) /* IO context */
22778+SK_AC *pAC, /* Adapter Context */
22779+SK_IOC IoC) /* I/O Context */
22780 {
22781+#ifdef YUKON
22782+ SK_U16 Word;
22783+#if (!defined(SK_SLIM) && !defined(SK_DIAG))
22784+ SK_EVPARA Para;
22785+#endif /* !SK_SLIM && !SK_DIAG */
22786+#endif /* YUKON */
22787 #ifdef GENESIS
22788 SK_U32 DWord;
22789 #endif /* GENESIS */
22790@@ -1741,13 +2762,13 @@
22791 SkGeInitPktArb(pAC, IoC);
22792 }
22793 #endif /* GENESIS */
22794-
22795-#ifdef YUKON
22796+
22797+#ifdef xSK_DIAG
22798 if (pAC->GIni.GIYukon) {
22799 /* start Time Stamp Timer */
22800 SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8)GMT_ST_START);
22801 }
22802-#endif /* YUKON */
22803+#endif /* SK_DIAG */
22804
22805 /* enable the Tx Arbiters */
22806 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
22807@@ -1757,8 +2778,62 @@
22808 /* enable the RAM Interface Arbiter */
22809 SkGeInitRamIface(pAC, IoC);
22810
22811+#ifdef YUKON
22812+ if (CHIP_ID_YUKON_2(pAC)) {
22813+
22814+ if (pAC->GIni.GIPciBus == SK_PEX_BUS) {
22815+
22816+ SK_IN16(IoC, PCI_C(pAC, PEX_DEV_CTRL), &Word);
22817+
22818+ /* change Max. Read Request Size to 2048 bytes */
22819+ Word &= ~PEX_DC_MAX_RRS_MSK;
22820+ Word |= PEX_DC_MAX_RD_RQ_SIZE(4);
22821+
22822+ SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
22823+
22824+ SK_OUT16(IoC, PCI_C(pAC, PEX_DEV_CTRL), Word);
22825+
22826+#ifdef REPLAY_TIMER
22827+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) {
22828+ /* PEX Ack Reply Timeout to 40 us */
22829+ SK_OUT16(IoC, PCI_C(pAC, PEX_ACK_RPLY_TOX1), 0x2710);
22830+ }
22831+#endif
22832+
22833+ SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
22834+
22835+#if (!defined(SK_SLIM) && !defined(SK_DIAG))
22836+ SK_IN16(IoC, PCI_C(pAC, PEX_LNK_CAP), &Word);
22837+
22838+ Word = (Word & PEX_CAP_MAX_WI_MSK) >> 4;
22839+
22840+ /* compare PEX Negotiated Link Width against max. capabil */
22841+ if (pAC->GIni.GIPexWidth != (SK_U8)Word) {
22842+
22843+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
22844+ ("PEX negotiated Link width is: %d, exp.: %d\n",
22845+ pAC->GIni.GIPexWidth, Word));
22846+
22847+#ifndef NDIS_MINIPORT_DRIVER
22848+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E026,
22849+ SKERR_HWI_E026MSG);
22850+#endif
22851+ Para.Para64 = 0;
22852+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_PEX_LINK_WIDTH, Para);
22853+ }
22854+#endif /* !SK_SLIM && !SK_DIAG */
22855+ }
22856+
22857+ /*
22858+ * Writing the HW Error Mask Reg. will not generate an IRQ
22859+ * as long as the B0_IMSK is not set by the driver.
22860+ */
22861+ SK_OUT32(IoC, B0_HWE_IMSK, pAC->GIni.GIValHwIrqMask);
22862+ }
22863+#endif /* YUKON */
22864 } /* SkGeInit2 */
22865
22866+
22867 /******************************************************************************
22868 *
22869 * SkGeInit() - Initialize the GE Adapter with the specified level.
22870@@ -1780,7 +2855,7 @@
22871 * if Number of MACs > SK_MAX_MACS
22872 *
22873 * After returning from Level 0 the adapter
22874- * may be accessed with IO operations.
22875+ * may be accessed with I/O operations.
22876 *
22877 * Level 2: start the Blink Source Counter
22878 *
22879@@ -1789,14 +2864,14 @@
22880 * 1: Number of MACs exceeds SK_MAX_MACS (after level 1)
22881 * 2: Adapter not present or not accessible
22882 * 3: Illegal initialization level
22883- * 4: Initialization Level 1 Call missing
22884+ * 4: Initialization level 1 call missing
22885 * 5: Unexpected PHY type detected
22886 * 6: HW self test failed
22887 */
22888 int SkGeInit(
22889-SK_AC *pAC, /* adapter context */
22890-SK_IOC IoC, /* IO context */
22891-int Level) /* initialization level */
22892+SK_AC *pAC, /* Adapter Context */
22893+SK_IOC IoC, /* I/O Context */
22894+int Level) /* Initialization Level */
22895 {
22896 int RetVal; /* return value */
22897 SK_U32 DWord;
22898@@ -1811,7 +2886,7 @@
22899 SkGeInit0(pAC, IoC);
22900 pAC->GIni.GILevel = SK_INIT_DATA;
22901 break;
22902-
22903+
22904 case SK_INIT_IO:
22905 /* Initialization Level 1 */
22906 RetVal = SkGeInit1(pAC, IoC);
22907@@ -1823,22 +2898,24 @@
22908 SK_OUT32(IoC, B2_IRQM_INI, SK_TEST_VAL);
22909 SK_IN32(IoC, B2_IRQM_INI, &DWord);
22910 SK_OUT32(IoC, B2_IRQM_INI, 0L);
22911-
22912+
22913 if (DWord != SK_TEST_VAL) {
22914 RetVal = 2;
22915 break;
22916 }
22917
22918+#ifdef DEBUG
22919 /* check if the number of GIMacsFound matches SK_MAX_MACS */
22920 if (pAC->GIni.GIMacsFound > SK_MAX_MACS) {
22921 RetVal = 1;
22922 break;
22923 }
22924+#endif /* DEBUG */
22925
22926 /* Level 1 successfully passed */
22927 pAC->GIni.GILevel = SK_INIT_IO;
22928 break;
22929-
22930+
22931 case SK_INIT_RUN:
22932 /* Initialization Level 2 */
22933 if (pAC->GIni.GILevel != SK_INIT_IO) {
22934@@ -1848,12 +2925,13 @@
22935 RetVal = 4;
22936 break;
22937 }
22938+
22939 SkGeInit2(pAC, IoC);
22940
22941 /* Level 2 successfully passed */
22942 pAC->GIni.GILevel = SK_INIT_RUN;
22943 break;
22944-
22945+
22946 default:
22947 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E003, SKERR_HWI_E003MSG);
22948 RetVal = 3;
22949@@ -1876,40 +2954,82 @@
22950 * nothing
22951 */
22952 void SkGeDeInit(
22953-SK_AC *pAC, /* adapter context */
22954-SK_IOC IoC) /* IO context */
22955+SK_AC *pAC, /* Adapter Context */
22956+SK_IOC IoC) /* I/O Context */
22957 {
22958 int i;
22959 SK_U16 Word;
22960
22961+#ifdef SK_PHY_LP_MODE_DEEP_SLEEP
22962+ SK_U16 PmCtlSts;
22963+#endif
22964+
22965 #if (!defined(SK_SLIM) && !defined(VCPU))
22966 /* ensure I2C is ready */
22967 SkI2cWaitIrq(pAC, IoC);
22968-#endif
22969+#endif
22970
22971- /* stop all current transfer activity */
22972- for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
22973- if (pAC->GIni.GP[i].PState != SK_PRT_STOP &&
22974- pAC->GIni.GP[i].PState != SK_PRT_RESET) {
22975+#ifdef SK_PHY_LP_MODE_DEEP_SLEEP
22976+ /*
22977+ * for power saving purposes within mobile environments
22978+ * we set the PHY to coma mode.
22979+ */
22980+#ifdef XXX
22981+ if (pAC->GIni.GIVauxAvail) {
22982+ /* switch power to VAUX */
22983+ SK_OUT8(IoC, B0_POWER_CTRL, (SK_U8)(PC_VAUX_ENA | PC_VCC_ENA |
22984+ PC_VAUX_ON | PC_VCC_OFF));
22985+ }
22986+#endif /* XXX */
22987+
22988+ if (CHIP_ID_YUKON_2(pAC) && /* pAC->GIni.GIMacsFound == 1 && */
22989+ !pAC->GIni.GIAsfEnabled
22990+#ifdef XXX
22991+ || (pAC->GIni.GIYukonLite && pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3)
22992+#endif /* XXX */
22993+ ) {
22994+
22995+ /* flag for SkGmEnterLowPowerMode() that the call was from here */
22996+ pAC->GIni.GILevel = SK_INIT_IO;
22997+
22998+ /* for all ports switch PHY to coma mode */
22999+ for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
23000+
23001+ (void)SkGmEnterLowPowerMode(pAC, IoC, i, PHY_PM_DEEP_SLEEP);
23002+ }
23003+ }
23004+#else /* !SK_PHY_LP_MODE_DEEP_SLEEP */
23005
23006- SkGeStopPort(pAC, IoC, i, SK_STOP_ALL, SK_HARD_RST);
23007+ if (!pAC->GIni.GIAsfEnabled) {
23008+ /* stop all current transfer activity */
23009+ for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
23010+ if (pAC->GIni.GP[i].PState != SK_PRT_STOP &&
23011+ pAC->GIni.GP[i].PState != SK_PRT_RESET) {
23012+
23013+ SkGeStopPort(pAC, IoC, i, SK_STOP_ALL, SK_HARD_RST);
23014+ }
23015 }
23016 }
23017
23018- /* Reset all bits in the PCI STATUS register */
23019+ /* reset all bits in the PCI STATUS register */
23020 /*
23021 * Note: PCI Cfg cycles cannot be used, because they are not
23022 * available on some platforms after 'boot time'.
23023 */
23024- SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);
23025-
23026+ SK_IN16(IoC, PCI_C(pAC, PCI_STATUS), &Word);
23027+
23028 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
23029- SK_OUT16(IoC, PCI_C(PCI_STATUS), (SK_U16)(Word | PCI_ERRBITS));
23030+
23031+ SK_OUT16(IoC, PCI_C(pAC, PCI_STATUS), Word | (SK_U16)PCI_ERRBITS);
23032+
23033 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
23034
23035- /* do the reset, all LEDs are switched off now */
23036- SK_OUT8(IoC, B0_CTST, CS_RST_SET);
23037-
23038+ if (!pAC->GIni.GIAsfEnabled) {
23039+ /* set the SW-reset */
23040+ SK_OUT8(IoC, B0_CTST, CS_RST_SET);
23041+ }
23042+#endif /* !SK_PHY_LP_MODE_DEEP_SLEEP */
23043+
23044 pAC->GIni.GILevel = SK_INIT_DATA;
23045 } /* SkGeDeInit */
23046
23047@@ -1943,8 +3063,8 @@
23048 * 2: The port has to be stopped before it can be initialized again.
23049 */
23050 int SkGeInitPort(
23051-SK_AC *pAC, /* adapter context */
23052-SK_IOC IoC, /* IO context */
23053+SK_AC *pAC, /* Adapter Context */
23054+SK_IOC IoC, /* I/O Context */
23055 int Port) /* Port to configure */
23056 {
23057 SK_GEPORT *pPrt;
23058@@ -1955,8 +3075,8 @@
23059 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E004, SKERR_HWI_E004MSG);
23060 return(1);
23061 }
23062-
23063- if (pPrt->PState == SK_PRT_INIT || pPrt->PState == SK_PRT_RUN) {
23064+
23065+ if (pPrt->PState >= SK_PRT_INIT) {
23066 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E005, SKERR_HWI_E005MSG);
23067 return(2);
23068 }
23069@@ -1967,35 +3087,35 @@
23070 if (pAC->GIni.GIGenesis) {
23071 /* initialize Rx, Tx and Link LED */
23072 /*
23073- * If 1000BT Phy needs LED initialization than swap
23074+ * If 1000BT PHY needs LED initialization than swap
23075 * LED and XMAC initialization order
23076 */
23077 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_ENA);
23078 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, RX_LED_INI), SK_LED_ENA);
23079 /* The Link LED is initialized by RLMT or Diagnostics itself */
23080-
23081+
23082 SkXmInitMac(pAC, IoC, Port);
23083 }
23084 #endif /* GENESIS */
23085-
23086+
23087 #ifdef YUKON
23088 if (pAC->GIni.GIYukon) {
23089
23090 SkGmInitMac(pAC, IoC, Port);
23091 }
23092 #endif /* YUKON */
23093-
23094+
23095 /* do NOT initialize the Link Sync Counter */
23096
23097 SkGeInitMacFifo(pAC, IoC, Port);
23098-
23099+
23100 SkGeInitRamBufs(pAC, IoC, Port);
23101-
23102+
23103 if (pPrt->PXSQSize != 0) {
23104 /* enable Force Sync bit if synchronous queue available */
23105 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_ENA_FSYNC);
23106 }
23107-
23108+
23109 SkGeInitBmu(pAC, IoC, Port);
23110
23111 /* mark port as initialized */
23112@@ -2003,3 +3123,215 @@
23113
23114 return(0);
23115 } /* SkGeInitPort */
23116+
23117+
23118+#if (defined(YUK2) && !defined(SK_SLIM))
23119+/******************************************************************************
23120+ *
23121+ * SkGeRamWrite() - Writes One quadword to RAM
23122+ *
23123+ * Returns:
23124+ * 0
23125+ */
23126+static void SkGeRamWrite(
23127+SK_AC *pAC, /* Adapter Context */
23128+SK_IOC IoC, /* I/O Context */
23129+SK_U32 Addr, /* Address to be written to (in quadwords) */
23130+SK_U32 LowDword, /* Lower Dword to be written */
23131+SK_U32 HighDword, /* Upper Dword to be written */
23132+int Port) /* Select RAM buffer (Yukon-2 has 2 RAM buffers) */
23133+{
23134+ SK_OUT32(IoC, SELECT_RAM_BUFFER(Port, B3_RAM_ADDR), Addr);
23135+
23136+ /* Write Access is initiated by writing the upper Dword */
23137+ SK_OUT32(IoC, SELECT_RAM_BUFFER(Port, B3_RAM_DATA_LO), LowDword);
23138+ SK_OUT32(IoC, SELECT_RAM_BUFFER(Port, B3_RAM_DATA_HI), HighDword);
23139+}
23140+
23141+/******************************************************************************
23142+ *
23143+ * SkYuk2RestartRxBmu() - Restart Receive BMU on Yukon-2
23144+ *
23145+ * return:
23146+ * 0 o.k.
23147+ * 1 timeout
23148+ */
23149+int SkYuk2RestartRxBmu(
23150+SK_AC *pAC, /* Adapter Context */
23151+SK_IOC IoC, /* I/O Context */
23152+int Port) /* Port Index (MAC_1 + n) */
23153+{
23154+ SK_U16 Word;
23155+ SK_U16 MacCtrl;
23156+ SK_U16 RxCtrl;
23157+ SK_U16 FlushMask;
23158+ SK_U16 FlushTrsh;
23159+ SK_U32 RamAdr;
23160+ SK_U32 StartTime;
23161+ SK_U32 CurrTime;
23162+ SK_U32 Delta;
23163+ SK_U32 TimeOut;
23164+ SK_GEPORT *pPrt; /* GIni Port struct pointer */
23165+ int Rtv;
23166+ SK_U16 WordBuffer[4]; /* Buffer to handle MAC address */
23167+
23168+ Rtv = 0;
23169+
23170+ pPrt = &pAC->GIni.GP[Port];
23171+
23172+/*
23173+ 1. save Rx MAC FIFO Flush Mask and Rx MAC FIFO Flush Threshold
23174+ 2. save GMAC Rx Control Register
23175+ 3. re-initialize MAC Rx FIFO, Rx RAM Buffer Queue, PCI Rx FIFO,
23176+ Rx BMU and Rx Prefetch Unit of the link.
23177+ 4. set Rx MAC FIFO Flush Mask to 0xffff
23178+ set Rx MAC FIFO Flush Threshold to a high value, e.g. 0x20
23179+ 5. set GMAC to loopback mode and switch GMAC back to Rx/Tx enable
23180+ 6. clear Rx/Tx Frame Complete IRQ in Rx/T MAC FIFO Control Register
23181+ 7. send one packet with a size of 64bytes (size below flush threshold)
23182+ from TXA RAM Buffer Queue to set the rx_sop flop:
23183+ - set TxAQ Write Pointer to (packet size in qwords + 2)
23184+ - set TxAQ Level to (packet size in qwords + 2)
23185+ - write Internal Status Word 1 and 2 to TxAQ RAM Buffer Queue QWord 0,1
23186+ according to figure 61 on page 330 of Yukon-2 Spec.
23187+ - write MAC header with Destination Address = own MAC address to
23188+ TxAQ RAM Buffer Queue QWords 2 and 3
23189+ - set TxAQ Packet Counter to 1 -> packet is transmitted immediately
23190+ 8. poll GMAC IRQ Source Register for IRQ Rx/Tx Frame Complete
23191+ 9. restore GMAC Rx Control Register
23192+10. restore Rx MAC FIFO Flush Mask and Rx MAC FIFO Flush Threshold
23193+11. set GMAC back to GMII mode
23194+*/
23195+
23196+ /* save Rx GMAC FIFO Flush Mask */
23197+ SK_IN16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), &FlushMask);
23198+
23199+ /* save Rx GMAC FIFO Flush Threshold */
23200+ SK_IN16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), &FlushTrsh);
23201+
23202+ /* save GMAC Rx Control Register */
23203+ GM_IN16(IoC, Port, GM_RX_CTRL, &RxCtrl);
23204+
23205+ /* configure the GMAC FIFOs */
23206+ SkGeInitMacFifo(pAC, IoC, Port);
23207+
23208+ SkGeInitRamBufs(pAC, IoC, Port);
23209+
23210+ SkGeInitBmu(pAC, IoC, Port);
23211+
23212+ /* configure Rx GMAC FIFO */
23213+ SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), GMF_RX_CTRL_DEF);
23214+
23215+ /* set Rx GMAC FIFO Flush Mask */
23216+ SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), 0xffff);
23217+
23218+ /* set Rx GMAC FIFO Flush Threshold */
23219+ SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), 0x20);
23220+
23221+ /* set to promiscuous mode */
23222+ Word = RxCtrl & ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
23223+
23224+ /* set GMAC Rx Control Register */
23225+ GM_OUT16(IoC, Port, GM_RX_CTRL, Word);
23226+
23227+ /* get General Purpose Control */
23228+ GM_IN16(IoC, Port, GM_GP_CTRL, &MacCtrl);
23229+
23230+ /* enable MAC Loopback Mode*/
23231+ GM_OUT16(IoC, Port, GM_GP_CTRL, MacCtrl | GM_GPCR_LOOP_ENA);
23232+
23233+ /* enable MAC Loopback Mode and Rx/Tx */
23234+ GM_OUT16(IoC, Port, GM_GP_CTRL, MacCtrl | GM_GPCR_LOOP_ENA |
23235+ GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
23236+
23237+ /* clear GMAC IRQ Rx Frame Complete */
23238+ SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_CLI_RX_FC);
23239+
23240+ /* clear GMAC IRQ Tx Frame Complete */
23241+ SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_CLI_TX_FC);
23242+
23243+ /* send one packet with a size of 64bytes from RAM buffer*/
23244+
23245+ RamAdr = pPrt->PXaQRamStart / 8;
23246+
23247+ SK_OUT32(IoC, RB_ADDR(pPrt->PXaQOff, RB_WP), RamAdr + 10);
23248+
23249+ SK_OUT32(IoC, RB_ADDR(pPrt->PXaQOff, RB_LEV), 10);
23250+
23251+ /* write 1st status quad word (packet end address in RAM, packet length */
23252+ SkGeRamWrite(pAC, IoC, RamAdr, (RamAdr + 9) << 16, 64, Port);
23253+
23254+ /* write 2nd status quad word */
23255+ SkGeRamWrite(pAC, IoC, RamAdr + 1, 0, 0, Port);
23256+
23257+ WordBuffer[0] = pPrt->PMacAddr[0];
23258+ WordBuffer[1] = pPrt->PMacAddr[1];
23259+ WordBuffer[2] = pPrt->PMacAddr[2];
23260+ WordBuffer[3] = pPrt->PMacAddr[0];
23261+
23262+ /* write DA to MAC header */
23263+ SkGeRamWrite(pAC, IoC, RamAdr + 2, *(SK_U32 *)&WordBuffer[0],
23264+ *(SK_U32 *)&WordBuffer[2], Port);
23265+
23266+ WordBuffer[0] = pPrt->PMacAddr[1];
23267+ WordBuffer[1] = pPrt->PMacAddr[2];
23268+ WordBuffer[2] = 0x3200; /* len / type field (big endian) */
23269+ WordBuffer[3] = 0x00;
23270+
23271+ SkGeRamWrite(pAC, IoC, RamAdr + 3, *(SK_U32 *)&WordBuffer[0],
23272+ *(SK_U32 *)&WordBuffer[2], Port);
23273+
23274+ SkGeRamWrite(pAC, IoC, RamAdr + 4, 0x4c56524d, /* "MRVL" */
23275+ 0x00464d2d, Port); /* "-MF" */
23276+
23277+ SkGeRamWrite(pAC, IoC, RamAdr + 5, 0x00000000, 0x00000000, Port);
23278+ SkGeRamWrite(pAC, IoC, RamAdr + 6, 0x00000000, 0x00000000, Port);
23279+ SkGeRamWrite(pAC, IoC, RamAdr + 7, 0x00000000, 0x00000000, Port);
23280+ SkGeRamWrite(pAC, IoC, RamAdr + 8, 0x00000000, 0x00000000, Port);
23281+ SkGeRamWrite(pAC, IoC, RamAdr + 9, 0x00000000, 0x00000000, Port);
23282+
23283+ SK_OUT32(IoC, RB_ADDR(pPrt->PXaQOff, RB_PC), 1);
23284+
23285+ SK_IN32(IoC, GMAC_TI_ST_VAL, &StartTime);
23286+
23287+ /* set timeout to 10 ms */
23288+ TimeOut = HW_MS_TO_TICKS(pAC, 10);
23289+
23290+ do {
23291+ SK_IN32(IoC, GMAC_TI_ST_VAL, &CurrTime);
23292+
23293+ if (CurrTime >= StartTime) {
23294+ Delta = CurrTime - StartTime;
23295+ }
23296+ else {
23297+ Delta = CurrTime + ~StartTime + 1;
23298+ }
23299+
23300+ if (Delta > TimeOut) {
23301+ Rtv = 1;
23302+ break;
23303+ }
23304+
23305+ /* read the GMAC Interrupt source register */
23306+ SK_IN16(IoC, MR_ADDR(Port, GMAC_IRQ_SRC), &Word);
23307+
23308+ } while ((Word & (GM_IS_TX_COMPL | GM_IS_RX_COMPL)) !=
23309+ (GM_IS_TX_COMPL | GM_IS_RX_COMPL));
23310+
23311+ /* disable MAC Loopback Mode and Rx/Tx */
23312+ GM_OUT16(IoC, Port, GM_GP_CTRL, MacCtrl);
23313+
23314+ /* restore GMAC Rx Control Register */
23315+ GM_OUT16(IoC, Port, GM_RX_CTRL, RxCtrl);
23316+
23317+ /* restore Rx GMAC FIFO Flush Mask */
23318+ SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), FlushMask);
23319+
23320+ /* restore Rx GMAC FIFO Flush Threshold */
23321+ SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), FlushTrsh);
23322+
23323+ return(Rtv);
23324+
23325+} /* SkYuk2RestartRxBmu */
23326+#endif /* YUK2 && !SK_SLIM */
23327+
23328diff -urN linux-2.6.17.orig/drivers/net/sk98lin/skgemib.c linux-2.6.17/drivers/net/sk98lin/skgemib.c
23329--- linux-2.6.17.orig/drivers/net/sk98lin/skgemib.c 2006-06-22 13:17:16.000000000 +0200
23330+++ linux-2.6.17/drivers/net/sk98lin/skgemib.c 2006-04-27 11:43:44.000000000 +0200
23331@@ -2,14 +2,15 @@
23332 *
23333 * Name: skgemib.c
23334 * Project: GEnesis, PCI Gigabit Ethernet Adapter
23335- * Version: $Revision$
23336- * Date: $Date$
23337+ * Version: $Revision$
23338+ * Date: $Date$
23339 * Purpose: Private Network Management Interface Management Database
23340 *
23341 ****************************************************************************/
23342
23343 /******************************************************************************
23344 *
23345+ * LICENSE:
23346 * (C)Copyright 1998-2002 SysKonnect GmbH.
23347 * (C)Copyright 2002-2003 Marvell.
23348 *
23349@@ -19,6 +20,7 @@
23350 * (at your option) any later version.
23351 *
23352 * The information in this file is provided "AS IS" without warranty.
23353+ * /LICENSE
23354 *
23355 ******************************************************************************/
23356
23357@@ -80,6 +82,12 @@
23358 unsigned int TableIndex, SK_U32 NetIndex);
23359 #endif /* SK_DIAG_SUPPORT */
23360
23361+#ifdef SK_ASF
23362+PNMI_STATIC int Asf(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
23363+ char *pBuf, unsigned int *pLen, SK_U32 Instance,
23364+ unsigned int TableIndex, SK_U32 NetIndex);
23365+#endif /* SK_ASF */
23366+
23367
23368 /* defines *******************************************************************/
23369 #define ID_TABLE_SIZE (sizeof(IdTable)/sizeof(IdTable[0]))
23370@@ -251,6 +259,183 @@
23371 0,
23372 SK_PNMI_RW, DiagActions, 0},
23373 #endif /* SK_DIAG_SUPPORT */
23374+#ifdef SK_ASF
23375+ {OID_SKGE_ASF,
23376+ 0,
23377+ 0,
23378+ 0,
23379+ SK_PNMI_RW, Asf, 0},
23380+ {OID_SKGE_ASF_STORE_CONFIG,
23381+ 0,
23382+ 0,
23383+ 0,
23384+ SK_PNMI_RW, Asf, 0},
23385+ {OID_SKGE_ASF_ENA,
23386+ 0,
23387+ 0,
23388+ 0,
23389+ SK_PNMI_RW, Asf, 0},
23390+ {OID_SKGE_ASF_RETRANS,
23391+ 0,
23392+ 0,
23393+ 0,
23394+ SK_PNMI_RW, Asf, 0},
23395+ {OID_SKGE_ASF_RETRANS_INT,
23396+ 0,
23397+ 0,
23398+ 0,
23399+ SK_PNMI_RW, Asf, 0},
23400+ {OID_SKGE_ASF_HB_ENA,
23401+ 0,
23402+ 0,
23403+ 0,
23404+ SK_PNMI_RW, Asf, 0},
23405+ {OID_SKGE_ASF_HB_INT,
23406+ 0,
23407+ 0,
23408+ 0,
23409+ SK_PNMI_RW, Asf, 0},
23410+ {OID_SKGE_ASF_WD_ENA,
23411+ 0,
23412+ 0,
23413+ 0,
23414+ SK_PNMI_RW, Asf, 0},
23415+ {OID_SKGE_ASF_WD_TIME,
23416+ 0,
23417+ 0,
23418+ 0,
23419+ SK_PNMI_RW, Asf, 0},
23420+ {OID_SKGE_ASF_IP_SOURCE,
23421+ 0,
23422+ 0,
23423+ 0,
23424+ SK_PNMI_RW, Asf, 0},
23425+ {OID_SKGE_ASF_MAC_SOURCE,
23426+ 0,
23427+ 0,
23428+ 0,
23429+ SK_PNMI_RW, Asf, 0},
23430+ {OID_SKGE_ASF_IP_DEST,
23431+ 0,
23432+ 0,
23433+ 0,
23434+ SK_PNMI_RW, Asf, 0},
23435+ {OID_SKGE_ASF_MAC_DEST,
23436+ 0,
23437+ 0,
23438+ 0,
23439+ SK_PNMI_RW, Asf, 0},
23440+ {OID_SKGE_ASF_COMMUNITY_NAME,
23441+ 0,
23442+ 0,
23443+ 0,
23444+ SK_PNMI_RW, Asf, 0},
23445+ {OID_SKGE_ASF_RSP_ENA,
23446+ 0,
23447+ 0,
23448+ 0,
23449+ SK_PNMI_RW, Asf, 0},
23450+ {OID_SKGE_ASF_RETRANS_COUNT_MIN,
23451+ 0,
23452+ 0,
23453+ 0,
23454+ SK_PNMI_RW, Asf, 0},
23455+ {OID_SKGE_ASF_RETRANS_COUNT_MAX,
23456+ 0,
23457+ 0,
23458+ 0,
23459+ SK_PNMI_RW, Asf, 0},
23460+ {OID_SKGE_ASF_RETRANS_INT_MIN,
23461+ 0,
23462+ 0,
23463+ 0,
23464+ SK_PNMI_RW, Asf, 0},
23465+ {OID_SKGE_ASF_RETRANS_INT_MAX,
23466+ 0,
23467+ 0,
23468+ 0,
23469+ SK_PNMI_RW, Asf, 0},
23470+ {OID_SKGE_ASF_HB_INT_MIN,
23471+ 0,
23472+ 0,
23473+ 0,
23474+ SK_PNMI_RW, Asf, 0},
23475+ {OID_SKGE_ASF_HB_INT_MAX,
23476+ 0,
23477+ 0,
23478+ 0,
23479+ SK_PNMI_RW, Asf, 0},
23480+ {OID_SKGE_ASF_WD_TIME_MIN,
23481+ 0,
23482+ 0,
23483+ 0,
23484+ SK_PNMI_RW, Asf, 0},
23485+ {OID_SKGE_ASF_WD_TIME_MAX,
23486+ 0,
23487+ 0,
23488+ 0,
23489+ SK_PNMI_RW, Asf, 0},
23490+ {OID_SKGE_ASF_HB_CAP,
23491+ 0,
23492+ 0,
23493+ 0,
23494+ SK_PNMI_RW, Asf, 0},
23495+ {OID_SKGE_ASF_WD_TIMER_RES,
23496+ 0,
23497+ 0,
23498+ 0,
23499+ SK_PNMI_RW, Asf, 0},
23500+ {OID_SKGE_ASF_GUID,
23501+ 0,
23502+ 0,
23503+ 0,
23504+ SK_PNMI_RW, Asf, 0},
23505+ {OID_SKGE_ASF_KEY_OP,
23506+ 0,
23507+ 0,
23508+ 0,
23509+ SK_PNMI_RW, Asf, 0},
23510+ {OID_SKGE_ASF_KEY_ADM,
23511+ 0,
23512+ 0,
23513+ 0,
23514+ SK_PNMI_RW, Asf, 0},
23515+ {OID_SKGE_ASF_KEY_GEN,
23516+ 0,
23517+ 0,
23518+ 0,
23519+ SK_PNMI_RW, Asf, 0},
23520+ {OID_SKGE_ASF_CAP,
23521+ 0,
23522+ 0,
23523+ 0,
23524+ SK_PNMI_RW, Asf, 0},
23525+ {OID_SKGE_ASF_PAR_1,
23526+ 0,
23527+ 0,
23528+ 0,
23529+ SK_PNMI_RW, Asf, 0},
23530+ {OID_SKGE_ASF_OVERALL_OID,
23531+ 0,
23532+ 0,
23533+ 0,
23534+ SK_PNMI_RW, Asf, 0},
23535+ {OID_SKGE_ASF_FWVER_OID,
23536+ 0,
23537+ 0,
23538+ 0,
23539+ SK_PNMI_RO, Asf, 0},
23540+ {OID_SKGE_ASF_ACPI_OID,
23541+ 0,
23542+ 0,
23543+ 0,
23544+ SK_PNMI_RO, Asf, 0},
23545+ {OID_SKGE_ASF_SMBUS_OID,
23546+ 0,
23547+ 0,
23548+ 0,
23549+ SK_PNMI_RO, Asf, 0},
23550+#endif /* SK_ASF */
23551 {OID_SKGE_MDB_VERSION,
23552 1,
23553 0,
23554@@ -871,6 +1056,13 @@
23555 sizeof(SK_PNMI_CONF),
23556 SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyType),
23557 SK_PNMI_RO, MacPrivateConf, 0},
23558+#ifdef SK_PHY_LP_MODE
23559+ {OID_SKGE_PHY_LP_MODE,
23560+ SK_PNMI_MAC_ENTRIES,
23561+ sizeof(SK_PNMI_CONF),
23562+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyMode),
23563+ SK_PNMI_RW, MacPrivateConf, 0},
23564+#endif
23565 {OID_SKGE_LINK_CAP,
23566 SK_PNMI_MAC_ENTRIES,
23567 sizeof(SK_PNMI_CONF),
23568@@ -1066,6 +1258,11 @@
23569 0,
23570 0,
23571 SK_PNMI_RO, Vct, 0},
23572+ {OID_SKGE_VCT_CAPABILITIES,
23573+ 0,
23574+ 0,
23575+ 0,
23576+ SK_PNMI_RO, Vct, 0},
23577 {OID_SKGE_BOARDLEVEL,
23578 0,
23579 0,
23580diff -urN linux-2.6.17.orig/drivers/net/sk98lin/skgepnmi.c linux-2.6.17/drivers/net/sk98lin/skgepnmi.c
23581--- linux-2.6.17.orig/drivers/net/sk98lin/skgepnmi.c 2006-06-22 13:17:16.000000000 +0200
23582+++ linux-2.6.17/drivers/net/sk98lin/skgepnmi.c 2006-04-27 11:43:44.000000000 +0200
23583@@ -1,15 +1,16 @@
23584 /*****************************************************************************
23585 *
23586 * Name: skgepnmi.c
23587- * Project: GEnesis, PCI Gigabit Ethernet Adapter
23588- * Version: $Revision$
23589- * Date: $Date$
23590+ * Project: Gigabit Ethernet Adapters, PNMI-Module
23591+ * Version: $Revision$
23592+ * Date: $Date$
23593 * Purpose: Private Network Management Interface
23594 *
23595 ****************************************************************************/
23596
23597 /******************************************************************************
23598 *
23599+ * LICENSE:
23600 * (C)Copyright 1998-2002 SysKonnect GmbH.
23601 * (C)Copyright 2002-2003 Marvell.
23602 *
23603@@ -19,14 +20,14 @@
23604 * (at your option) any later version.
23605 *
23606 * The information in this file is provided "AS IS" without warranty.
23607+ * /LICENSE
23608 *
23609 ******************************************************************************/
23610
23611-
23612-#ifndef _lint
23613+#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
23614 static const char SysKonnectFileId[] =
23615- "@(#) $Id$ (C) Marvell.";
23616-#endif /* !_lint */
23617+ "@(#) $Id$ (C) Marvell.";
23618+#endif
23619
23620 #include "h/skdrv1st.h"
23621 #include "h/sktypes.h"
23622@@ -38,12 +39,14 @@
23623 #include "h/skcsum.h"
23624 #include "h/skvpd.h"
23625 #include "h/skgehw.h"
23626+#include "h/sky2le.h"
23627 #include "h/skgeinit.h"
23628 #include "h/skdrv2nd.h"
23629 #include "h/skgepnm2.h"
23630 #ifdef SK_POWER_MGMT
23631 #include "h/skgepmgt.h"
23632-#endif
23633+#endif /* SK_POWER_MGMT */
23634+
23635 /* defines *******************************************************************/
23636
23637 #ifndef DEBUG
23638@@ -53,23 +56,6 @@
23639 #endif /* DEBUG */
23640
23641 /*
23642- * Public Function prototypes
23643- */
23644-int SkPnmiInit(SK_AC *pAC, SK_IOC IoC, int level);
23645-int SkPnmiSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void *pBuf,
23646- unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex);
23647-int SkPnmiGetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf,
23648- unsigned int *pLen, SK_U32 NetIndex);
23649-int SkPnmiPreSetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf,
23650- unsigned int *pLen, SK_U32 NetIndex);
23651-int SkPnmiSetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf,
23652- unsigned int *pLen, SK_U32 NetIndex);
23653-int SkPnmiEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Param);
23654-int SkPnmiGenIoctl(SK_AC *pAC, SK_IOC IoC, void * pBuf,
23655- unsigned int * pLen, SK_U32 NetIndex);
23656-
23657-
23658-/*
23659 * Private Function prototypes
23660 */
23661
23662@@ -105,9 +91,8 @@
23663 PNMI_STATIC int RlmtUpdate(SK_AC *pAC, SK_IOC IoC, SK_U32 NetIndex);
23664 PNMI_STATIC int SirqUpdate(SK_AC *pAC, SK_IOC IoC);
23665 PNMI_STATIC void VirtualConf(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, char *pBuf);
23666-PNMI_STATIC int Vct(SK_AC *pAC, SK_IOC IoC, int Action, SK_U32 Id, char *pBuf,
23667- unsigned int *pLen, SK_U32 Instance, unsigned int TableIndex, SK_U32 NetIndex);
23668 PNMI_STATIC void CheckVctStatus(SK_AC *, SK_IOC, char *, SK_U32, SK_U32);
23669+PNMI_STATIC void VctGetResults(SK_AC *, SK_IOC, SK_U32);
23670
23671 /*
23672 * Table to correlate OID with handler function and index to
23673@@ -349,17 +334,13 @@
23674 * Always 0
23675 */
23676 int SkPnmiInit(
23677-SK_AC *pAC, /* Pointer to adapter context */
23678-SK_IOC IoC, /* IO context handle */
23679-int Level) /* Initialization level */
23680+SK_AC *pAC, /* Pointer to adapter context */
23681+SK_IOC IoC, /* IO context handle */
23682+int Level) /* Initialization level */
23683 {
23684 unsigned int PortMax; /* Number of ports */
23685 unsigned int PortIndex; /* Current port index in loop */
23686- SK_U16 Val16; /* Multiple purpose 16 bit variable */
23687- SK_U8 Val8; /* Mulitple purpose 8 bit variable */
23688- SK_EVPARA EventParam; /* Event struct for timer event */
23689- SK_PNMI_VCT *pVctBackupData;
23690-
23691+ SK_EVPARA EventParam; /* Event struct for timer event */
23692
23693 SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
23694 ("PNMI: SkPnmiInit: Called, level=%d\n", Level));
23695@@ -368,13 +349,19 @@
23696
23697 case SK_INIT_DATA:
23698 SK_MEMSET((char *)&pAC->Pnmi, 0, sizeof(pAC->Pnmi));
23699+
23700 pAC->Pnmi.TrapBufFree = SK_PNMI_TRAP_QUEUE_LEN;
23701 pAC->Pnmi.StartUpTime = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC));
23702 pAC->Pnmi.RlmtChangeThreshold = SK_PNMI_DEF_RLMT_CHG_THRES;
23703+
23704 for (PortIndex = 0; PortIndex < SK_MAX_MACS; PortIndex ++) {
23705
23706 pAC->Pnmi.Port[PortIndex].ActiveFlag = SK_FALSE;
23707 pAC->Pnmi.DualNetActiveFlag = SK_FALSE;
23708+
23709+ /* Initialize DSP variables for Vct() to 0xff => Never written! */
23710+ pAC->GIni.GP[PortIndex].PCableLen = 0xff;
23711+ pAC->Pnmi.VctBackup[PortIndex].CableLen = 0xff;
23712 }
23713
23714 #ifdef SK_PNMI_CHECK
23715@@ -404,51 +391,36 @@
23716 break;
23717
23718 case SK_INIT_IO:
23719- /*
23720- * Reset MAC counters
23721- */
23722+
23723+ /* Reset MAC counters. */
23724 PortMax = pAC->GIni.GIMacsFound;
23725
23726 for (PortIndex = 0; PortIndex < PortMax; PortIndex ++) {
23727
23728 pAC->GIni.GIFunc.pFnMacResetCounter(pAC, IoC, PortIndex);
23729 }
23730-
23731- /* Initialize DSP variables for Vct() to 0xff => Never written! */
23732- for (PortIndex = 0; PortIndex < PortMax; PortIndex ++) {
23733- pAC->GIni.GP[PortIndex].PCableLen = 0xff;
23734- pVctBackupData = &pAC->Pnmi.VctBackup[PortIndex];
23735- pVctBackupData->PCableLen = 0xff;
23736- }
23737-
23738- /*
23739- * Get pci bus speed
23740- */
23741- SK_IN16(IoC, B0_CTST, &Val16);
23742- if ((Val16 & CS_BUS_CLOCK) == 0) {
23743
23744- pAC->Pnmi.PciBusSpeed = 33;
23745+ /* Get PCI bus speed. */
23746+ if (pAC->GIni.GIPciClock66) {
23747+
23748+ pAC->Pnmi.PciBusSpeed = 66;
23749 }
23750 else {
23751- pAC->Pnmi.PciBusSpeed = 66;
23752+ pAC->Pnmi.PciBusSpeed = 33;
23753 }
23754
23755- /*
23756- * Get pci bus width
23757- */
23758- SK_IN16(IoC, B0_CTST, &Val16);
23759- if ((Val16 & CS_BUS_SLOT_SZ) == 0) {
23760+ /* Get PCI bus width. */
23761+ if (pAC->GIni.GIPciSlot64) {
23762
23763- pAC->Pnmi.PciBusWidth = 32;
23764+ pAC->Pnmi.PciBusWidth = 64;
23765 }
23766 else {
23767- pAC->Pnmi.PciBusWidth = 64;
23768+ pAC->Pnmi.PciBusWidth = 32;
23769 }
23770
23771- /*
23772- * Get chipset
23773- */
23774+ /* Get chipset. */
23775 switch (pAC->GIni.GIChipId) {
23776+
23777 case CHIP_ID_GENESIS:
23778 pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_XMAC;
23779 break;
23780@@ -457,57 +429,51 @@
23781 pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON;
23782 break;
23783
23784+ case CHIP_ID_YUKON_LITE:
23785+ pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_LITE;
23786+ break;
23787+
23788+ case CHIP_ID_YUKON_LP:
23789+ pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_LP;
23790+ break;
23791+
23792+ case CHIP_ID_YUKON_XL:
23793+ pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_XL;
23794+ break;
23795+
23796+ case CHIP_ID_YUKON_EC:
23797+ pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_EC;
23798+ break;
23799+
23800+ case CHIP_ID_YUKON_FE:
23801+ pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_FE;
23802+ break;
23803+
23804 default:
23805 break;
23806 }
23807
23808- /*
23809- * Get PMD and DeviceType
23810- */
23811- SK_IN8(IoC, B2_PMD_TYP, &Val8);
23812- switch (Val8) {
23813+ /* Get PMD and Device Type. */
23814+ switch (pAC->GIni.GIPmdTyp) {
23815+
23816 case 'S':
23817 pAC->Pnmi.PMD = 3;
23818- if (pAC->GIni.GIMacsFound > 1) {
23819-
23820- pAC->Pnmi.DeviceType = 0x00020002;
23821- }
23822- else {
23823- pAC->Pnmi.DeviceType = 0x00020001;
23824- }
23825+ pAC->Pnmi.DeviceType = 0x00020001;
23826 break;
23827
23828 case 'L':
23829 pAC->Pnmi.PMD = 2;
23830- if (pAC->GIni.GIMacsFound > 1) {
23831-
23832- pAC->Pnmi.DeviceType = 0x00020004;
23833- }
23834- else {
23835- pAC->Pnmi.DeviceType = 0x00020003;
23836- }
23837+ pAC->Pnmi.DeviceType = 0x00020003;
23838 break;
23839
23840 case 'C':
23841 pAC->Pnmi.PMD = 4;
23842- if (pAC->GIni.GIMacsFound > 1) {
23843-
23844- pAC->Pnmi.DeviceType = 0x00020006;
23845- }
23846- else {
23847- pAC->Pnmi.DeviceType = 0x00020005;
23848- }
23849+ pAC->Pnmi.DeviceType = 0x00020005;
23850 break;
23851
23852 case 'T':
23853 pAC->Pnmi.PMD = 5;
23854- if (pAC->GIni.GIMacsFound > 1) {
23855-
23856- pAC->Pnmi.DeviceType = 0x00020008;
23857- }
23858- else {
23859- pAC->Pnmi.DeviceType = 0x00020007;
23860- }
23861+ pAC->Pnmi.DeviceType = 0x00020007;
23862 break;
23863
23864 default :
23865@@ -516,11 +482,14 @@
23866 break;
23867 }
23868
23869- /*
23870- * Get connector
23871- */
23872- SK_IN8(IoC, B2_CONN_TYP, &Val8);
23873- switch (Val8) {
23874+ if (pAC->GIni.GIMacsFound > 1) {
23875+
23876+ pAC->Pnmi.DeviceType++;
23877+ }
23878+
23879+ /* Get connector type. */
23880+ switch (pAC->GIni.GIConTyp) {
23881+
23882 case 'C':
23883 pAC->Pnmi.Connector = 2;
23884 break;
23885@@ -548,17 +517,17 @@
23886 break;
23887
23888 case SK_INIT_RUN:
23889- /*
23890- * Start timer for RLMT change counter
23891- */
23892+
23893+ /* Start timer for RLMT change counter. */
23894 SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
23895+
23896 SkTimerStart(pAC, IoC, &pAC->Pnmi.RlmtChangeEstimate.EstTimer,
23897- 28125000, SKGE_PNMI, SK_PNMI_EVT_CHG_EST_TIMER,
23898+ SK_PNMI_EVT_TIMER_CHECK, SKGE_PNMI, SK_PNMI_EVT_CHG_EST_TIMER,
23899 EventParam);
23900 break;
23901
23902 default:
23903- break; /* Nothing todo */
23904+ break; /* Nothing to do. */
23905 }
23906
23907 return (0);
23908@@ -583,7 +552,7 @@
23909 * exist (e.g. port instance 3 on a two port
23910 * adapter.
23911 */
23912-static int SkPnmiGetVar(
23913+int SkPnmiGetVar(
23914 SK_AC *pAC, /* Pointer to adapter context */
23915 SK_IOC IoC, /* IO context handle */
23916 SK_U32 Id, /* Object ID that is to be processed */
23917@@ -607,7 +576,7 @@
23918 * Description:
23919 * Calls a general sub-function for all this stuff. The preset does
23920 * the same as a set, but returns just before finally setting the
23921- * new value. This is useful to check if a set might be successfull.
23922+ * new value. This is usefull to check if a set might be successfull.
23923 * If the instance -1 is passed, an array of values is supposed and
23924 * all instances of the OID will be set.
23925 *
23926@@ -625,7 +594,7 @@
23927 * exist (e.g. port instance 3 on a two port
23928 * adapter.
23929 */
23930-static int SkPnmiPreSetVar(
23931+int SkPnmiPreSetVar(
23932 SK_AC *pAC, /* Pointer to adapter context */
23933 SK_IOC IoC, /* IO context handle */
23934 SK_U32 Id, /* Object ID that is to be processed */
23935@@ -638,7 +607,6 @@
23936 ("PNMI: SkPnmiPreSetVar: Called, Id=0x%x, BufLen=%d, Instance=%d, NetIndex=%d\n",
23937 Id, *pLen, Instance, NetIndex));
23938
23939-
23940 return (PnmiVar(pAC, IoC, SK_PNMI_PRESET, Id, (char *)pBuf, pLen,
23941 Instance, NetIndex));
23942 }
23943@@ -650,7 +618,7 @@
23944 * Description:
23945 * Calls a general sub-function for all this stuff. The preset does
23946 * the same as a set, but returns just before finally setting the
23947- * new value. This is useful to check if a set might be successfull.
23948+ * new value. This is usefull to check if a set might be successfull.
23949 * If the instance -1 is passed, an array of values is supposed and
23950 * all instances of the OID will be set.
23951 *
23952@@ -720,7 +688,6 @@
23953 unsigned int TmpLen;
23954 char KeyArr[SK_PNMI_VPD_ENTRIES][SK_PNMI_VPD_KEY_SIZE];
23955
23956-
23957 SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
23958 ("PNMI: SkPnmiGetStruct: Called, BufLen=%d, NetIndex=%d\n",
23959 *pLen, NetIndex));
23960@@ -729,22 +696,19 @@
23961
23962 if (*pLen >= SK_PNMI_MIN_STRUCT_SIZE) {
23963
23964- SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_TOO_SHORT,
23965- (SK_U32)(-1));
23966+ SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_TOO_SHORT, (SK_U32)(-1));
23967 }
23968
23969 *pLen = SK_PNMI_STRUCT_SIZE;
23970 return (SK_PNMI_ERR_TOO_SHORT);
23971 }
23972
23973- /*
23974- * Check NetIndex
23975- */
23976+ /* Check NetIndex. */
23977 if (NetIndex >= pAC->Rlmt.NumNets) {
23978 return (SK_PNMI_ERR_UNKNOWN_NET);
23979 }
23980
23981- /* Update statistic */
23982+ /* Update statistics. */
23983 SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On call");
23984
23985 if ((Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1)) !=
23986@@ -769,35 +733,37 @@
23987 return (Ret);
23988 }
23989
23990- /*
23991- * Increment semaphores to indicate that an update was
23992- * already done
23993- */
23994+ /* Increment semaphores to indicate that an update was already done. */
23995 pAC->Pnmi.MacUpdatedFlag ++;
23996 pAC->Pnmi.RlmtUpdatedFlag ++;
23997 pAC->Pnmi.SirqUpdatedFlag ++;
23998
23999- /* Get vpd keys for instance calculation */
24000- Ret = GetVpdKeyArr(pAC, IoC, &KeyArr[0][0], sizeof(KeyArr), &TmpLen);
24001- if (Ret != SK_PNMI_ERR_OK) {
24002+ /*
24003+ * Get VPD keys for instance calculation.
24004+ * Please read comment in Vpd().
24005+ */
24006+ if (pAC->Pnmi.VpdKeyReadError == SK_FALSE) {
24007+ Ret = GetVpdKeyArr(pAC, IoC, &KeyArr[0][0], sizeof(KeyArr), &TmpLen);
24008+ if (Ret != SK_PNMI_ERR_OK) {
24009
24010- pAC->Pnmi.MacUpdatedFlag --;
24011- pAC->Pnmi.RlmtUpdatedFlag --;
24012- pAC->Pnmi.SirqUpdatedFlag --;
24013+ pAC->Pnmi.MacUpdatedFlag --;
24014+ pAC->Pnmi.RlmtUpdatedFlag --;
24015+ pAC->Pnmi.SirqUpdatedFlag --;
24016
24017- SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On return");
24018- SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1));
24019- *pLen = SK_PNMI_MIN_STRUCT_SIZE;
24020- return (SK_PNMI_ERR_GENERAL);
24021+ SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On return");
24022+ SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1));
24023+ *pLen = SK_PNMI_MIN_STRUCT_SIZE;
24024+ return (SK_PNMI_ERR_GENERAL);
24025+ }
24026 }
24027
24028- /* Retrieve values */
24029+ /* Retrieve values. */
24030 SK_MEMSET((char *)pBuf, 0, SK_PNMI_STRUCT_SIZE);
24031+
24032 for (TableIndex = 0; TableIndex < ID_TABLE_SIZE; TableIndex ++) {
24033
24034 InstanceNo = IdTable[TableIndex].InstanceNo;
24035- for (InstanceCnt = 1; InstanceCnt <= InstanceNo;
24036- InstanceCnt ++) {
24037+ for (InstanceCnt = 1; InstanceCnt <= InstanceNo; InstanceCnt ++) {
24038
24039 DstOffset = IdTable[TableIndex].Offset +
24040 (InstanceCnt - 1) *
24041@@ -866,7 +832,7 @@
24042 * Description:
24043 * Calls a general sub-function for all this set stuff. The preset does
24044 * the same as a set, but returns just before finally setting the
24045- * new value. This is useful to check if a set might be successfull.
24046+ * new value. This is usefull to check if a set might be successfull.
24047 * The sub-function runs through the IdTable, checks which OIDs are able
24048 * to set, and calls the handler function of the OID to perform the
24049 * preset. The return value of the function will also be stored in
24050@@ -994,7 +960,6 @@
24051 unsigned int PhysPortIndex;
24052 unsigned int MaxNetNumber;
24053 int CounterIndex;
24054- int Ret;
24055 SK_U16 MacStatus;
24056 SK_U64 OverflowStatus;
24057 SK_U64 Mask;
24058@@ -1008,12 +973,7 @@
24059 SK_U64 Delta;
24060 SK_PNMI_ESTIMATE *pEst;
24061 SK_U32 NetIndex;
24062- SK_GEPORT *pPrt;
24063- SK_PNMI_VCT *pVctBackupData;
24064 SK_U32 RetCode;
24065- int i;
24066- SK_U32 CableLength;
24067-
24068
24069 #ifdef DEBUG
24070 if (Event != SK_PNMI_EVT_XMAC_RESET) {
24071@@ -1044,9 +1004,7 @@
24072 #endif /* DEBUG */
24073 OverflowStatus = 0;
24074
24075- /*
24076- * Check which source caused an overflow interrupt.
24077- */
24078+ /* Check which source caused an overflow interrupt. */
24079 if ((pAC->GIni.GIFunc.pFnMacOverflow(pAC, IoC, PhysPortIndex,
24080 MacStatus, &OverflowStatus) != 0) ||
24081 (OverflowStatus == 0)) {
24082@@ -1064,7 +1022,6 @@
24083
24084 Mask = (SK_U64)1 << CounterIndex;
24085 if ((OverflowStatus & Mask) == 0) {
24086-
24087 continue;
24088 }
24089
24090@@ -1096,9 +1053,7 @@
24091 case SK_PNMI_HRX_IRLENGTH:
24092 case SK_PNMI_HRX_RESERVED:
24093
24094- /*
24095- * the following counters aren't be handled (id > 63)
24096- */
24097+ /* The following counters aren't be handled (id > 63). */
24098 case SK_PNMI_HTX_SYNC:
24099 case SK_PNMI_HTX_SYNC_OCTET:
24100 break;
24101@@ -1185,7 +1140,7 @@
24102 if ((unsigned int)Param.Para64 >= (unsigned int)pAC->I2c.MaxSens) {
24103
24104 SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
24105- ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_SEN_ERR_UPP parameter wrong, SensorIndex=%d\n",
24106+ ("PNMI: ERR: SK_PNMI_EVT_SEN_ERR_UPP parameter wrong, SensorIndex=%d\n",
24107 (unsigned int)Param.Para64));
24108 return (0);
24109 }
24110@@ -1204,16 +1159,14 @@
24111 case SK_PNMI_EVT_CHG_EST_TIMER:
24112 /*
24113 * Calculate port switch average on a per hour basis
24114- * Time interval for check : 28125 ms
24115+ * Time interval for check : 28125 ms (SK_PNMI_EVT_TIMER_CHECK)
24116 * Number of values for average : 8
24117 *
24118 * Be careful in changing these values, on change check
24119 * - typedef of SK_PNMI_ESTIMATE (Size of EstValue
24120 * array one less than value number)
24121 * - Timer initialization SkTimerStart() in SkPnmiInit
24122- * - Delta value below must be multiplicated with
24123- * power of 2
24124- *
24125+ * - Delta value below must be multiplicated with power of 2
24126 */
24127 pEst = &pAC->Pnmi.RlmtChangeEstimate;
24128 CounterIndex = pEst->EstValueIndex + 1;
24129@@ -1236,7 +1189,7 @@
24130 Delta = NewestValue - OldestValue;
24131 }
24132 else {
24133- /* Overflow situation */
24134+ /* Overflow situation. */
24135 Delta = (SK_U64)(0 - OldestValue) + NewestValue;
24136 }
24137
24138@@ -1262,8 +1215,9 @@
24139 }
24140
24141 SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
24142+
24143 SkTimerStart(pAC, IoC, &pAC->Pnmi.RlmtChangeEstimate.EstTimer,
24144- 28125000, SKGE_PNMI, SK_PNMI_EVT_CHG_EST_TIMER,
24145+ SK_PNMI_EVT_TIMER_CHECK, SKGE_PNMI, SK_PNMI_EVT_CHG_EST_TIMER,
24146 EventParam);
24147 break;
24148
24149@@ -1307,29 +1261,25 @@
24150 (unsigned int)Param.Para64));
24151 return (0);
24152 }
24153-#endif
24154+#endif /* DEBUG */
24155+
24156 PhysPortIndex = (unsigned int)Param.Para64;
24157
24158- /*
24159- * Update XMAC statistic to get fresh values
24160- */
24161- Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1);
24162- if (Ret != SK_PNMI_ERR_OK) {
24163+ /* Update XMAC statistic to get fresh values. */
24164+ if (MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1) !=
24165+ SK_PNMI_ERR_OK) {
24166
24167 SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return");
24168 return (0);
24169 }
24170- /*
24171- * Increment semaphore to indicate that an update was
24172- * already done
24173- */
24174+
24175+ /* Increment semaphore to indicate that an update was already done. */
24176 pAC->Pnmi.MacUpdatedFlag ++;
24177
24178 for (CounterIndex = 0; CounterIndex < SK_PNMI_MAX_IDX;
24179 CounterIndex ++) {
24180
24181 if (!StatAddr[CounterIndex][MacType].GetOffset) {
24182-
24183 continue;
24184 }
24185
24186@@ -1362,14 +1312,15 @@
24187 QueueRlmtPortTrap(pAC, OID_SKGE_TRAP_RLMT_PORT_UP, PhysPortIndex);
24188 (void)SK_DRIVER_SENDEVENT(pAC, IoC);
24189
24190- /* Bugfix for XMAC errata (#10620)*/
24191+ /* Bugfix for XMAC errata (#10620). */
24192 if (MacType == SK_MAC_XMAC) {
24193- /* Add incremental difference to offset (#10620)*/
24194+ /* Add incremental difference to offset (#10620). */
24195 (void)pAC->GIni.GIFunc.pFnMacStatistic(pAC, IoC, PhysPortIndex,
24196 XM_RXE_SHT_ERR, &Val32);
24197
24198 Value = (((SK_U64)pAC->Pnmi.Port[PhysPortIndex].
24199 CounterHigh[SK_PNMI_HRX_SHORTS] << 32) | (SK_U64)Val32);
24200+
24201 pAC->Pnmi.Port[PhysPortIndex].CounterOffset[SK_PNMI_HRX_SHORTS] +=
24202 Value - pAC->Pnmi.Port[PhysPortIndex].RxShortZeroMark;
24203 }
24204@@ -1399,7 +1350,7 @@
24205 QueueRlmtPortTrap(pAC, OID_SKGE_TRAP_RLMT_PORT_DOWN, PhysPortIndex);
24206 (void)SK_DRIVER_SENDEVENT(pAC, IoC);
24207
24208- /* Bugfix #10620 - get zero level for incremental difference */
24209+ /* Bugfix #10620 - get zero level for incremental difference. */
24210 if (MacType == SK_MAC_XMAC) {
24211
24212 (void)pAC->GIni.GIFunc.pFnMacStatistic(pAC, IoC, PhysPortIndex,
24213@@ -1431,17 +1382,13 @@
24214 }
24215 #endif /* DEBUG */
24216
24217- /*
24218- * For now, ignore event if NetIndex != 0.
24219- */
24220+ /* For now, ignore event if NetIndex != 0. */
24221 if (Param.Para32[1] != 0) {
24222
24223 return (0);
24224 }
24225
24226- /*
24227- * Nothing to do if port is already inactive
24228- */
24229+ /* Nothing to do if port is already inactive. */
24230 if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
24231
24232 return (0);
24233@@ -1472,7 +1419,6 @@
24234 CounterIndex ++) {
24235
24236 if (!StatAddr[CounterIndex][MacType].GetOffset) {
24237-
24238 continue;
24239 }
24240
24241@@ -1481,9 +1427,7 @@
24242 pAC->Pnmi.VirtualCounterOffset[CounterIndex] += Value;
24243 }
24244
24245- /*
24246- * Set port to inactive
24247- */
24248+ /* Set port to inactive. */
24249 pAC->Pnmi.Port[PhysPortIndex].ActiveFlag = SK_FALSE;
24250
24251 pAC->Pnmi.MacUpdatedFlag --;
24252@@ -1509,25 +1453,19 @@
24253 }
24254 #endif /* DEBUG */
24255
24256- /*
24257- * For now, ignore event if NetIndex != 0.
24258- */
24259+ /* For now, ignore event if NetIndex != 0. */
24260 if (Param.Para32[1] != 0) {
24261
24262 return (0);
24263 }
24264
24265- /*
24266- * Nothing to do if port is already active
24267- */
24268+ /* Nothing to do if port is already inactive. */
24269 if (pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
24270
24271 return (0);
24272 }
24273
24274- /*
24275- * Statistic maintenance
24276- */
24277+ /* Statistic maintenance. */
24278 pAC->Pnmi.RlmtChangeCts ++;
24279 pAC->Pnmi.RlmtChangeTime = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC));
24280
24281@@ -1561,7 +1499,6 @@
24282 CounterIndex ++) {
24283
24284 if (!StatAddr[CounterIndex][MacType].GetOffset) {
24285-
24286 continue;
24287 }
24288
24289@@ -1570,16 +1507,14 @@
24290 pAC->Pnmi.VirtualCounterOffset[CounterIndex] -= Value;
24291 }
24292
24293- /* Set port to active */
24294+ /* Set port to active. */
24295 pAC->Pnmi.Port[PhysPortIndex].ActiveFlag = SK_TRUE;
24296
24297 pAC->Pnmi.MacUpdatedFlag --;
24298 break;
24299
24300 case SK_PNMI_EVT_RLMT_SEGMENTATION:
24301- /*
24302- * Para.Para32[0] contains the NetIndex.
24303- */
24304+ /* Para.Para32[0] contains the NetIndex. */
24305
24306 /*
24307 * Store a trap message in the trap buffer and generate an event for
24308@@ -1594,71 +1529,53 @@
24309 * Param.Para32[0] contains the number of Nets.
24310 * Param.Para32[1] is reserved, contains -1.
24311 */
24312- /*
24313- * Check number of nets
24314- */
24315+ /* Check number of nets. */
24316 MaxNetNumber = pAC->GIni.GIMacsFound;
24317- if (((unsigned int)Param.Para32[0] < 1)
24318- || ((unsigned int)Param.Para32[0] > MaxNetNumber)) {
24319+
24320+ if (((unsigned int)Param.Para32[0] < 1) ||
24321+ ((unsigned int)Param.Para32[0] > MaxNetNumber)) {
24322+
24323 return (SK_PNMI_ERR_UNKNOWN_NET);
24324 }
24325
24326- if ((unsigned int)Param.Para32[0] == 1) { /* single net mode */
24327+ if ((unsigned int)Param.Para32[0] == 1) { /* SingleNet mode. */
24328 pAC->Pnmi.DualNetActiveFlag = SK_FALSE;
24329 }
24330- else { /* dual net mode */
24331+ else { /* DualNet mode. */
24332 pAC->Pnmi.DualNetActiveFlag = SK_TRUE;
24333 }
24334 break;
24335
24336 case SK_PNMI_EVT_VCT_RESET:
24337 PhysPortIndex = Param.Para32[0];
24338- pPrt = &pAC->GIni.GP[PhysPortIndex];
24339- pVctBackupData = &pAC->Pnmi.VctBackup[PhysPortIndex];
24340
24341 if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_PENDING) {
24342+
24343 RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_FALSE);
24344+
24345 if (RetCode == 2) {
24346 /*
24347 * VCT test is still running.
24348 * Start VCT timer counter again.
24349 */
24350- SK_MEMSET((char *) &Param, 0, sizeof(Param));
24351+ SK_MEMSET((char *)&Param, 0, sizeof(Param));
24352+
24353 Param.Para32[0] = PhysPortIndex;
24354 Param.Para32[1] = -1;
24355- SkTimerStart(pAC, IoC,
24356- &pAC->Pnmi.VctTimeout[PhysPortIndex].VctTimer,
24357- 4000000, SKGE_PNMI, SK_PNMI_EVT_VCT_RESET, Param);
24358+
24359+ SkTimerStart(pAC, IoC, &pAC->Pnmi.VctTimeout[PhysPortIndex],
24360+ SK_PNMI_VCT_TIMER_CHECK, SKGE_PNMI, SK_PNMI_EVT_VCT_RESET, Param);
24361+
24362 break;
24363 }
24364- pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_PENDING;
24365- pAC->Pnmi.VctStatus[PhysPortIndex] |=
24366- (SK_PNMI_VCT_NEW_VCT_DATA | SK_PNMI_VCT_TEST_DONE);
24367
24368- /* Copy results for later use to PNMI struct. */
24369- for (i = 0; i < 4; i++) {
24370- if (pPrt->PMdiPairSts[i] == SK_PNMI_VCT_NORMAL_CABLE) {
24371- if ((pPrt->PMdiPairLen[i] > 35) &&
24372- (pPrt->PMdiPairLen[i] < 0xff)) {
24373- pPrt->PMdiPairSts[i] = SK_PNMI_VCT_IMPEDANCE_MISMATCH;
24374- }
24375- }
24376- if ((pPrt->PMdiPairLen[i] > 35) &&
24377- (pPrt->PMdiPairLen[i] != 0xff)) {
24378- CableLength = 1000 *
24379- (((175 * pPrt->PMdiPairLen[i]) / 210) - 28);
24380- }
24381- else {
24382- CableLength = 0;
24383- }
24384- pVctBackupData->PMdiPairLen[i] = CableLength;
24385- pVctBackupData->PMdiPairSts[i] = pPrt->PMdiPairSts[i];
24386- }
24387+ VctGetResults(pAC, IoC, PhysPortIndex);
24388
24389- Param.Para32[0] = PhysPortIndex;
24390- Param.Para32[1] = -1;
24391- SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Param);
24392- SkEventDispatcher(pAC, IoC);
24393+ EventParam.Para32[0] = PhysPortIndex;
24394+ EventParam.Para32[1] = -1;
24395+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, EventParam);
24396+
24397+ /* SkEventDispatcher(pAC, IoC); */
24398 }
24399
24400 break;
24401@@ -1706,14 +1623,13 @@
24402 unsigned int TableIndex;
24403 int Ret;
24404
24405-
24406 if ((TableIndex = LookupId(Id)) == (unsigned int)(-1)) {
24407
24408 *pLen = 0;
24409 return (SK_PNMI_ERR_UNKNOWN_OID);
24410 }
24411
24412- /* Check NetIndex */
24413+ /* Check NetIndex. */
24414 if (NetIndex >= pAC->Rlmt.NumNets) {
24415 return (SK_PNMI_ERR_UNKNOWN_NET);
24416 }
24417@@ -1763,22 +1679,20 @@
24418 SK_U32 Instance;
24419 SK_U32 Id;
24420
24421-
24422- /* Check if the passed buffer has the right size */
24423+ /* Check if the passed buffer has the right size. */
24424 if (*pLen < SK_PNMI_STRUCT_SIZE) {
24425
24426- /* Check if we can return the error within the buffer */
24427+ /* Check if we can return the error within the buffer. */
24428 if (*pLen >= SK_PNMI_MIN_STRUCT_SIZE) {
24429
24430- SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_TOO_SHORT,
24431- (SK_U32)(-1));
24432+ SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_TOO_SHORT, (SK_U32)(-1));
24433 }
24434
24435 *pLen = SK_PNMI_STRUCT_SIZE;
24436 return (SK_PNMI_ERR_TOO_SHORT);
24437 }
24438
24439- /* Check NetIndex */
24440+ /* Check NetIndex. */
24441 if (NetIndex >= pAC->Rlmt.NumNets) {
24442 return (SK_PNMI_ERR_UNKNOWN_NET);
24443 }
24444@@ -1806,12 +1720,11 @@
24445 pAC->Pnmi.RlmtUpdatedFlag ++;
24446 pAC->Pnmi.SirqUpdatedFlag ++;
24447
24448- /* Preset/Set values */
24449+ /* PRESET/SET values. */
24450 for (TableIndex = 0; TableIndex < ID_TABLE_SIZE; TableIndex ++) {
24451
24452 if ((IdTable[TableIndex].Access != SK_PNMI_RW) &&
24453 (IdTable[TableIndex].Access != SK_PNMI_WO)) {
24454-
24455 continue;
24456 }
24457
24458@@ -1822,8 +1735,7 @@
24459 InstanceCnt ++) {
24460
24461 DstOffset = IdTable[TableIndex].Offset +
24462- (InstanceCnt - 1) *
24463- IdTable[TableIndex].StructSize;
24464+ (InstanceCnt - 1) * IdTable[TableIndex].StructSize;
24465
24466 /*
24467 * Because VPD multiple instance variables are
24468@@ -1833,9 +1745,7 @@
24469 */
24470 Instance = (SK_U32)InstanceCnt;
24471
24472- /*
24473- * Evaluate needed buffer length
24474- */
24475+ /* Evaluate needed buffer length. */
24476 Len = 0;
24477 Ret = IdTable[TableIndex].Func(pAC, IoC,
24478 SK_PNMI_GET, IdTable[TableIndex].Id,
24479@@ -1851,8 +1761,7 @@
24480 pAC->Pnmi.SirqUpdatedFlag --;
24481
24482 SK_PNMI_CHECKFLAGS("PnmiStruct: On return");
24483- SK_PNMI_SET_STAT(pBuf,
24484- SK_PNMI_ERR_GENERAL, DstOffset);
24485+ SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_GENERAL, DstOffset);
24486 *pLen = SK_PNMI_MIN_STRUCT_SIZE;
24487 return (SK_PNMI_ERR_GENERAL);
24488 }
24489@@ -1874,7 +1783,7 @@
24490 }
24491 }
24492
24493- /* Call the OID handler function */
24494+ /* Call the OID handler function. */
24495 Ret = IdTable[TableIndex].Func(pAC, IoC, Action,
24496 IdTable[TableIndex].Id, pBuf + DstOffset,
24497 &Len, Instance, TableIndex, NetIndex);
24498@@ -1885,8 +1794,7 @@
24499 pAC->Pnmi.SirqUpdatedFlag --;
24500
24501 SK_PNMI_CHECKFLAGS("PnmiStruct: On return");
24502- SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_BAD_VALUE,
24503- DstOffset);
24504+ SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_BAD_VALUE, DstOffset);
24505 *pLen = SK_PNMI_MIN_STRUCT_SIZE;
24506 return (SK_PNMI_ERR_BAD_VALUE);
24507 }
24508@@ -1920,7 +1828,7 @@
24509
24510 if (IdTable[i].Id == Id) {
24511
24512- return i;
24513+ return (i);
24514 }
24515 }
24516
24517@@ -1961,16 +1869,13 @@
24518 {
24519 if (Id != OID_SKGE_ALL_DATA) {
24520
24521- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR003,
24522- SK_PNMI_ERR003MSG);
24523+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR003, SK_PNMI_ERR003MSG);
24524
24525 *pLen = 0;
24526 return (SK_PNMI_ERR_GENERAL);
24527 }
24528
24529- /*
24530- * Check instance. We only handle single instance variables
24531- */
24532+ /* Check instance. We only handle single instance variables. */
24533 if (Instance != (SK_U32)(-1) && Instance != 1) {
24534
24535 *pLen = 0;
24536@@ -2029,10 +1934,7 @@
24537 int Ret;
24538 SK_U32 ActionOp;
24539
24540-
24541- /*
24542- * Check instance. We only handle single instance variables
24543- */
24544+ /* Check instance. We only handle single instance variables. */
24545 if (Instance != (SK_U32)(-1) && Instance != 1) {
24546
24547 *pLen = 0;
24548@@ -2045,10 +1947,10 @@
24549 return (SK_PNMI_ERR_TOO_SHORT);
24550 }
24551
24552- /* Check if a get should be performed */
24553+ /* Check if a GET should be performed. */
24554 if (Action == SK_PNMI_GET) {
24555
24556- /* A get is easy. We always return the same value */
24557+ /* A GET is easy. We always return the same value. */
24558 ActionOp = (SK_U32)SK_PNMI_ACT_IDLE;
24559 SK_PNMI_STORE_U32(pBuf, ActionOp);
24560 *pLen = sizeof(SK_U32);
24561@@ -2056,13 +1958,13 @@
24562 return (SK_PNMI_ERR_OK);
24563 }
24564
24565- /* Continue with PRESET/SET action */
24566+ /* Continue with PRESET/SET action. */
24567 if (*pLen > sizeof(SK_U32)) {
24568
24569 return (SK_PNMI_ERR_BAD_VALUE);
24570 }
24571
24572- /* Check if the command is a known one */
24573+ /* Check if the command is a known one. */
24574 SK_PNMI_READ_U32(pBuf, ActionOp);
24575 if (*pLen > sizeof(SK_U32) ||
24576 (ActionOp != SK_PNMI_ACT_IDLE &&
24577@@ -2074,7 +1976,7 @@
24578 return (SK_PNMI_ERR_BAD_VALUE);
24579 }
24580
24581- /* A preset ends here */
24582+ /* A PRESET ends here. */
24583 if (Action == SK_PNMI_PRESET) {
24584
24585 return (SK_PNMI_ERR_OK);
24586@@ -2083,19 +1985,15 @@
24587 switch (ActionOp) {
24588
24589 case SK_PNMI_ACT_IDLE:
24590- /* Nothing to do */
24591+ /* Nothing to do. */
24592 break;
24593
24594 case SK_PNMI_ACT_RESET:
24595- /*
24596- * Perform a driver reset or something that comes near
24597- * to this.
24598- */
24599+ /* Perform a driver reset or something that comes near to this. */
24600 Ret = SK_DRIVER_RESET(pAC, IoC);
24601 if (Ret != 0) {
24602
24603- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR005,
24604- SK_PNMI_ERR005MSG);
24605+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR005, SK_PNMI_ERR005MSG);
24606
24607 return (SK_PNMI_ERR_GENERAL);
24608 }
24609@@ -2112,13 +2010,12 @@
24610 break;
24611
24612 case SK_PNMI_ACT_RESETCNT:
24613- /* Set all counters and timestamps to zero */
24614+ /* Set all counters and timestamps to zero. */
24615 ResetCounter(pAC, IoC, NetIndex);
24616 break;
24617
24618 default:
24619- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR006,
24620- SK_PNMI_ERR006MSG);
24621+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR006, SK_PNMI_ERR006MSG);
24622
24623 return (SK_PNMI_ERR_GENERAL);
24624 }
24625@@ -2162,25 +2059,21 @@
24626 SK_U32 StatVal32;
24627 SK_BOOL Is64BitReq = SK_FALSE;
24628
24629- /*
24630- * Only the active Mac is returned
24631- */
24632+ /* Only the active MAC is returned. */
24633 if (Instance != (SK_U32)(-1) && Instance != 1) {
24634
24635 *pLen = 0;
24636 return (SK_PNMI_ERR_UNKNOWN_INST);
24637 }
24638
24639- /*
24640- * Check action type
24641- */
24642+ /* Check action type. */
24643 if (Action != SK_PNMI_GET) {
24644
24645 *pLen = 0;
24646 return (SK_PNMI_ERR_READ_ONLY);
24647 }
24648
24649- /* Check length */
24650+ /* Check length. */
24651 switch (Id) {
24652
24653 case OID_802_3_PERMANENT_ADDRESS:
24654@@ -2201,12 +2094,12 @@
24655
24656 #else /* SK_NDIS_64BIT_CTR */
24657
24658- /* for compatibility, at least 32bit are required for OID */
24659+ /* For compatibility, at least 32 bits are required for OID. */
24660 if (*pLen < sizeof(SK_U32)) {
24661 /*
24662- * but indicate handling for 64bit values,
24663- * if insufficient space is provided
24664- */
24665+ * Indicate handling for 64 bit values,
24666+ * if insufficient space is provided.
24667+ */
24668 *pLen = sizeof(SK_U64);
24669 return (SK_PNMI_ERR_TOO_SHORT);
24670 }
24671@@ -2222,16 +2115,14 @@
24672 * to indicate that an update was already done.
24673 */
24674 Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1);
24675- if ( Ret != SK_PNMI_ERR_OK) {
24676+ if (Ret != SK_PNMI_ERR_OK) {
24677
24678 *pLen = 0;
24679 return (Ret);
24680 }
24681 pAC->Pnmi.MacUpdatedFlag ++;
24682
24683- /*
24684- * Get value (MAC Index 0 identifies the virtual MAC)
24685- */
24686+ /* Get value (MAC index 0 identifies the virtual MAC). */
24687 switch (Id) {
24688
24689 case OID_802_3_PERMANENT_ADDRESS:
24690@@ -2247,7 +2138,7 @@
24691 default:
24692 StatVal = GetStatVal(pAC, IoC, 0, IdTable[TableIndex].Param, NetIndex);
24693
24694- /* by default 32bit values are evaluated */
24695+ /* By default 32 bit values are evaluated. */
24696 if (!Is64BitReq) {
24697 StatVal32 = (SK_U32)StatVal;
24698 SK_PNMI_STORE_U32(pBuf, StatVal32);
24699@@ -2301,21 +2192,19 @@
24700 int MacType;
24701 int Ret;
24702 SK_U64 StatVal;
24703-
24704-
24705
24706- /* Calculate instance if wished. MAC index 0 is the virtual MAC */
24707+ /* Calculate instance if wished. MAC index 0 is the virtual MAC. */
24708 PhysPortMax = pAC->GIni.GIMacsFound;
24709 LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax);
24710
24711 MacType = pAC->GIni.GIMacType;
24712
24713- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* Dual net mode */
24714+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* DualNet mode. */
24715 LogPortMax--;
24716 }
24717
24718- if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried */
24719- /* Check instance range */
24720+ if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried. */
24721+ /* Check instance range. */
24722 if ((Instance < 1) || (Instance > LogPortMax)) {
24723
24724 *pLen = 0;
24725@@ -2325,20 +2214,20 @@
24726 Limit = LogPortIndex + 1;
24727 }
24728
24729- else { /* Instance == (SK_U32)(-1), get all Instances of that OID */
24730+ else { /* Instance == (SK_U32)(-1), get all Instances of that OID. */
24731
24732 LogPortIndex = 0;
24733 Limit = LogPortMax;
24734 }
24735
24736- /* Check action */
24737+ /* Check action. */
24738 if (Action != SK_PNMI_GET) {
24739
24740 *pLen = 0;
24741 return (SK_PNMI_ERR_READ_ONLY);
24742 }
24743
24744- /* Check length */
24745+ /* Check length. */
24746 if (*pLen < (Limit - LogPortIndex) * sizeof(SK_U64)) {
24747
24748 *pLen = (Limit - LogPortIndex) * sizeof(SK_U64);
24749@@ -2357,7 +2246,7 @@
24750 }
24751 pAC->Pnmi.MacUpdatedFlag ++;
24752
24753- /* Get value */
24754+ /* Get value. */
24755 Offset = 0;
24756 for (; LogPortIndex < Limit; LogPortIndex ++) {
24757
24758@@ -2463,19 +2352,16 @@
24759 unsigned int Limit;
24760 unsigned int Offset = 0;
24761
24762- /*
24763- * Calculate instance if wished. MAC index 0 is the virtual
24764- * MAC.
24765- */
24766+ /* Calculate instance if wished. MAC index 0 is the virtual MAC. */
24767 PhysPortMax = pAC->GIni.GIMacsFound;
24768 LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax);
24769
24770- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* Dual net mode */
24771+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* DualNet mode. */
24772 LogPortMax--;
24773 }
24774
24775- if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried */
24776- /* Check instance range */
24777+ if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried. */
24778+ /* Check instance range. */
24779 if ((Instance < 1) || (Instance > LogPortMax)) {
24780
24781 *pLen = 0;
24782@@ -2484,27 +2370,23 @@
24783 LogPortIndex = SK_PNMI_PORT_INST2LOG(Instance);
24784 Limit = LogPortIndex + 1;
24785 }
24786- else { /* Instance == (SK_U32)(-1), get all Instances of that OID */
24787+ else { /* Instance == (SK_U32)(-1), get all Instances of that OID. */
24788
24789 LogPortIndex = 0;
24790 Limit = LogPortMax;
24791 }
24792
24793- /*
24794- * Perform Action
24795- */
24796+ /* Perform action. */
24797 if (Action == SK_PNMI_GET) {
24798
24799- /* Check length */
24800+ /* Check length. */
24801 if (*pLen < (Limit - LogPortIndex) * 6) {
24802
24803 *pLen = (Limit - LogPortIndex) * 6;
24804 return (SK_PNMI_ERR_TOO_SHORT);
24805 }
24806
24807- /*
24808- * Get value
24809- */
24810+ /* Get value. */
24811 for (; LogPortIndex < Limit; LogPortIndex ++) {
24812
24813 switch (Id) {
24814@@ -2528,8 +2410,7 @@
24815 &pAC->Addr.Net[NetIndex].PermanentMacAddress);
24816 }
24817 else {
24818- PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
24819- pAC, LogPortIndex);
24820+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);
24821
24822 CopyMac(pBuf + Offset,
24823 &pAC->Addr.Port[PhysPortIndex].PermanentMacAddress);
24824@@ -2538,8 +2419,7 @@
24825 break;
24826
24827 default:
24828- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR008,
24829- SK_PNMI_ERR008MSG);
24830+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR008, SK_PNMI_ERR008MSG);
24831
24832 *pLen = 0;
24833 return (SK_PNMI_ERR_GENERAL);
24834@@ -2550,8 +2430,8 @@
24835 }
24836 else {
24837 /*
24838- * The logical MAC address may not be changed only
24839- * the physical ones
24840+ * The logical MAC address may not be changed,
24841+ * only the physical ones.
24842 */
24843 if (Id == OID_SKGE_PHYS_FAC_ADDR) {
24844
24845@@ -2559,19 +2439,16 @@
24846 return (SK_PNMI_ERR_READ_ONLY);
24847 }
24848
24849- /*
24850- * Only the current address may be changed
24851- */
24852+ /* Only the current address may be changed. */
24853 if (Id != OID_SKGE_PHYS_CUR_ADDR) {
24854
24855- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR009,
24856- SK_PNMI_ERR009MSG);
24857+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR009, SK_PNMI_ERR009MSG);
24858
24859 *pLen = 0;
24860 return (SK_PNMI_ERR_GENERAL);
24861 }
24862
24863- /* Check length */
24864+ /* Check length. */
24865 if (*pLen < (Limit - LogPortIndex) * 6) {
24866
24867 *pLen = (Limit - LogPortIndex) * 6;
24868@@ -2583,32 +2460,26 @@
24869 return (SK_PNMI_ERR_BAD_VALUE);
24870 }
24871
24872- /*
24873- * Check Action
24874- */
24875+ /* Check action. */
24876 if (Action == SK_PNMI_PRESET) {
24877
24878 *pLen = 0;
24879 return (SK_PNMI_ERR_OK);
24880 }
24881
24882- /*
24883- * Set OID_SKGE_MAC_CUR_ADDR
24884- */
24885+ /* Set OID_SKGE_MAC_CUR_ADDR. */
24886 for (; LogPortIndex < Limit; LogPortIndex ++, Offset += 6) {
24887
24888 /*
24889 * A set to virtual port and set of broadcast
24890- * address will be ignored
24891+ * address will be ignored.
24892 */
24893 if (LogPortIndex == 0 || SK_MEMCMP(pBuf + Offset,
24894 "\xff\xff\xff\xff\xff\xff", 6) == 0) {
24895-
24896 continue;
24897 }
24898
24899- PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC,
24900- LogPortIndex);
24901+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);
24902
24903 Ret = SkAddrOverride(pAC, IoC, PhysPortIndex,
24904 (SK_MAC_ADDR *)(pBuf + Offset),
24905@@ -2661,10 +2532,7 @@
24906 unsigned int Offset = 0;
24907 SK_U64 StatVal;
24908
24909-
24910- /*
24911- * Calculate instance if wished
24912- */
24913+ /* Calculate instance if wished. */
24914 if (Instance != (SK_U32)(-1)) {
24915
24916 if ((Instance < 1) || (Instance > SKCS_NUM_PROTOCOLS)) {
24917@@ -2680,25 +2548,21 @@
24918 Limit = SKCS_NUM_PROTOCOLS;
24919 }
24920
24921- /*
24922- * Check action
24923- */
24924+ /* Check action. */
24925 if (Action != SK_PNMI_GET) {
24926
24927 *pLen = 0;
24928 return (SK_PNMI_ERR_READ_ONLY);
24929 }
24930
24931- /* Check length */
24932+ /* Check length. */
24933 if (*pLen < (Limit - Index) * sizeof(SK_U64)) {
24934
24935 *pLen = (Limit - Index) * sizeof(SK_U64);
24936 return (SK_PNMI_ERR_TOO_SHORT);
24937 }
24938
24939- /*
24940- * Get value
24941- */
24942+ /* Get value. */
24943 for (; Index < Limit; Index ++) {
24944
24945 switch (Id) {
24946@@ -2724,8 +2588,7 @@
24947 break;
24948
24949 default:
24950- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR010,
24951- SK_PNMI_ERR010MSG);
24952+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR010, SK_PNMI_ERR010MSG);
24953
24954 *pLen = 0;
24955 return (SK_PNMI_ERR_GENERAL);
24956@@ -2735,9 +2598,7 @@
24957 Offset += sizeof(SK_U64);
24958 }
24959
24960- /*
24961- * Store used buffer space
24962- */
24963+ /* Store used buffer space. */
24964 *pLen = Offset;
24965
24966 return (SK_PNMI_ERR_OK);
24967@@ -2780,10 +2641,7 @@
24968 SK_U32 Val32;
24969 SK_U64 Val64;
24970
24971-
24972- /*
24973- * Calculate instance if wished
24974- */
24975+ /* Calculate instance if wished. */
24976 if ((Instance != (SK_U32)(-1))) {
24977
24978 if ((Instance < 1) || (Instance > (SK_U32)pAC->I2c.MaxSens)) {
24979@@ -2800,16 +2658,14 @@
24980 Limit = (unsigned int) pAC->I2c.MaxSens;
24981 }
24982
24983- /*
24984- * Check action
24985- */
24986+ /* Check action. */
24987 if (Action != SK_PNMI_GET) {
24988
24989 *pLen = 0;
24990 return (SK_PNMI_ERR_READ_ONLY);
24991 }
24992
24993- /* Check length */
24994+ /* Check length. */
24995 switch (Id) {
24996
24997 case OID_SKGE_SENSOR_VALUE:
24998@@ -2868,38 +2724,33 @@
24999 break;
25000
25001 default:
25002- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR012,
25003- SK_PNMI_ERR012MSG);
25004+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR012, SK_PNMI_ERR012MSG);
25005
25006 *pLen = 0;
25007 return (SK_PNMI_ERR_GENERAL);
25008
25009 }
25010
25011- /*
25012- * Get value
25013- */
25014+ /* Get value. */
25015 for (Offset = 0; Index < Limit; Index ++) {
25016
25017 switch (Id) {
25018
25019 case OID_SKGE_SENSOR_INDEX:
25020 *(pBuf + Offset) = (char)Index;
25021- Offset += sizeof(char);
25022+ Offset ++;
25023 break;
25024
25025 case OID_SKGE_SENSOR_DESCR:
25026 Len = SK_STRLEN(pAC->I2c.SenTable[Index].SenDesc);
25027- SK_MEMCPY(pBuf + Offset + 1,
25028- pAC->I2c.SenTable[Index].SenDesc, Len);
25029+ SK_MEMCPY(pBuf + Offset + 1, pAC->I2c.SenTable[Index].SenDesc, Len);
25030 *(pBuf + Offset) = (char)Len;
25031 Offset += Len + 1;
25032 break;
25033
25034 case OID_SKGE_SENSOR_TYPE:
25035- *(pBuf + Offset) =
25036- (char)pAC->I2c.SenTable[Index].SenType;
25037- Offset += sizeof(char);
25038+ *(pBuf + Offset) = (char)pAC->I2c.SenTable[Index].SenType;
25039+ Offset ++;
25040 break;
25041
25042 case OID_SKGE_SENSOR_VALUE:
25043@@ -2936,9 +2787,8 @@
25044 break;
25045
25046 case OID_SKGE_SENSOR_STATUS:
25047- *(pBuf + Offset) =
25048- (char)pAC->I2c.SenTable[Index].SenErrFlag;
25049- Offset += sizeof(char);
25050+ *(pBuf + Offset) = (char)pAC->I2c.SenTable[Index].SenErrFlag;
25051+ Offset ++;
25052 break;
25053
25054 case OID_SKGE_SENSOR_WAR_CTS:
25055@@ -2975,9 +2825,7 @@
25056 }
25057 }
25058
25059- /*
25060- * Store used buffer space
25061- */
25062+ /* Store used buffer space. */
25063 *pLen = Offset;
25064
25065 return (SK_PNMI_ERR_OK);
25066@@ -3032,8 +2880,29 @@
25067 SK_U32 Val32;
25068
25069 /*
25070- * Get array of all currently stored VPD keys
25071- */
25072+ * VpdKeyReadError will be set in GetVpdKeyArr() if an error occurs.
25073+ * Due to the fact that some drivers use SkPnmiGetStruct() to retrieve
25074+ * all statistical data, an error in GetVpdKeyArr() will generate a PNMI
25075+ * error and terminate SkPnmiGetStruct() without filling in statistical
25076+ * data into the PNMI struct. In this case the driver will get no values
25077+ * for statistical purposes (netstat, ifconfig etc.). GetVpdKeyArr() is
25078+ * the first function to be called in SkPnmiGetStruct(), so any error
25079+ * will terminate SkPnmiGetStruct() immediately. Hence, VpdKeyReadError will
25080+ * be set during the first call to GetVpdKeyArr() to make successful calls
25081+ * to SkPnmiGetStruct() possible. But there is another point to consider:
25082+ * When filling in the statistical data into the PNMI struct, the VPD
25083+ * handler Vpd() will also be called. If GetVpdKeyArr() in Vpd() would
25084+ * return with SK_PNMI_ERR_GENERAL, SkPnmiGetStruct() would fail again.
25085+ * For this reason VpdKeyReadError is checked here and, if set, Vpd()
25086+ * will return without doing anything and the return value SK_PNMI_ERR_OK.
25087+ * Therefore SkPnmiGetStruct() is able to continue and fill in all other
25088+ * statistical data.
25089+ */
25090+ if (pAC->Pnmi.VpdKeyReadError == SK_TRUE) {
25091+ return (SK_PNMI_ERR_OK);
25092+ }
25093+
25094+ /* Get array of all currently stored VPD keys. */
25095 Ret = GetVpdKeyArr(pAC, IoC, &KeyArr[0][0], sizeof(KeyArr), &KeyNo);
25096 if (Ret != SK_PNMI_ERR_OK) {
25097 *pLen = 0;
25098@@ -3078,34 +2947,32 @@
25099 }
25100 }
25101
25102- /*
25103- * Get value, if a query should be performed
25104- */
25105+ /* Get value, if a query should be performed. */
25106 if (Action == SK_PNMI_GET) {
25107
25108 switch (Id) {
25109
25110 case OID_SKGE_VPD_FREE_BYTES:
25111- /* Check length of buffer */
25112+ /* Check length of buffer. */
25113 if (*pLen < sizeof(SK_U32)) {
25114
25115 *pLen = sizeof(SK_U32);
25116 return (SK_PNMI_ERR_TOO_SHORT);
25117 }
25118- /* Get number of free bytes */
25119+ /* Get number of free bytes. */
25120 pVpdStatus = VpdStat(pAC, IoC);
25121 if (pVpdStatus == NULL) {
25122
25123- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR017,
25124- SK_PNMI_ERR017MSG);
25125+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
25126+ (SK_PNMI_ERR017MSG));
25127
25128 *pLen = 0;
25129 return (SK_PNMI_ERR_GENERAL);
25130 }
25131 if ((pVpdStatus->vpd_status & VPD_VALID) == 0) {
25132
25133- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR018,
25134- SK_PNMI_ERR018MSG);
25135+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
25136+ (SK_PNMI_ERR018MSG));
25137
25138 *pLen = 0;
25139 return (SK_PNMI_ERR_GENERAL);
25140@@ -3117,7 +2984,7 @@
25141 break;
25142
25143 case OID_SKGE_VPD_ENTRIES_LIST:
25144- /* Check length */
25145+ /* Check length. */
25146 for (Len = 0, Index = 0; Index < KeyNo; Index ++) {
25147
25148 Len += SK_STRLEN(KeyArr[Index]) + 1;
25149@@ -3128,7 +2995,7 @@
25150 return (SK_PNMI_ERR_TOO_SHORT);
25151 }
25152
25153- /* Get value */
25154+ /* Get value. */
25155 *(pBuf) = (char)Len - 1;
25156 for (Offset = 1, Index = 0; Index < KeyNo; Index ++) {
25157
25158@@ -3147,7 +3014,7 @@
25159 break;
25160
25161 case OID_SKGE_VPD_ENTRIES_NUMBER:
25162- /* Check length */
25163+ /* Check length. */
25164 if (*pLen < sizeof(SK_U32)) {
25165
25166 *pLen = sizeof(SK_U32);
25167@@ -3160,7 +3027,7 @@
25168 break;
25169
25170 case OID_SKGE_VPD_KEY:
25171- /* Check buffer length, if it is large enough */
25172+ /* Check buffer length, if it is large enough. */
25173 for (Len = 0, Index = FirstIndex;
25174 Index < LastIndex; Index ++) {
25175
25176@@ -3176,32 +3043,28 @@
25177 * Get the key to an intermediate buffer, because
25178 * we have to prepend a length byte.
25179 */
25180- for (Offset = 0, Index = FirstIndex;
25181- Index < LastIndex; Index ++) {
25182+ for (Offset = 0, Index = FirstIndex; Index < LastIndex; Index ++) {
25183
25184 Len = SK_STRLEN(KeyArr[Index]);
25185
25186 *(pBuf + Offset) = (char)Len;
25187- SK_MEMCPY(pBuf + Offset + 1, KeyArr[Index],
25188- Len);
25189+ SK_MEMCPY(pBuf + Offset + 1, KeyArr[Index], Len);
25190 Offset += Len + 1;
25191 }
25192 *pLen = Offset;
25193 break;
25194
25195 case OID_SKGE_VPD_VALUE:
25196- /* Check the buffer length if it is large enough */
25197- for (Offset = 0, Index = FirstIndex;
25198- Index < LastIndex; Index ++) {
25199+ /* Check the buffer length if it is large enough. */
25200+ for (Offset = 0, Index = FirstIndex; Index < LastIndex; Index ++) {
25201
25202 BufLen = 256;
25203 if (VpdRead(pAC, IoC, KeyArr[Index], Buf,
25204 (int *)&BufLen) > 0 ||
25205 BufLen >= SK_PNMI_VPD_DATALEN) {
25206
25207- SK_ERR_LOG(pAC, SK_ERRCL_SW,
25208- SK_PNMI_ERR021,
25209- SK_PNMI_ERR021MSG);
25210+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
25211+ (SK_PNMI_ERR021MSG));
25212
25213 return (SK_PNMI_ERR_GENERAL);
25214 }
25215@@ -3217,17 +3080,15 @@
25216 * Get the value to an intermediate buffer, because
25217 * we have to prepend a length byte.
25218 */
25219- for (Offset = 0, Index = FirstIndex;
25220- Index < LastIndex; Index ++) {
25221+ for (Offset = 0, Index = FirstIndex; Index < LastIndex; Index ++) {
25222
25223 BufLen = 256;
25224 if (VpdRead(pAC, IoC, KeyArr[Index], Buf,
25225 (int *)&BufLen) > 0 ||
25226 BufLen >= SK_PNMI_VPD_DATALEN) {
25227
25228- SK_ERR_LOG(pAC, SK_ERRCL_SW,
25229- SK_PNMI_ERR022,
25230- SK_PNMI_ERR022MSG);
25231+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
25232+ (SK_PNMI_ERR022MSG));
25233
25234 *pLen = 0;
25235 return (SK_PNMI_ERR_GENERAL);
25236@@ -3247,8 +3108,7 @@
25237 return (SK_PNMI_ERR_TOO_SHORT);
25238 }
25239
25240- for (Offset = 0, Index = FirstIndex;
25241- Index < LastIndex; Index ++) {
25242+ for (Offset = 0, Index = FirstIndex; Index < LastIndex; Index ++) {
25243
25244 if (VpdMayWrite(KeyArr[Index])) {
25245
25246@@ -3274,15 +3134,15 @@
25247 break;
25248
25249 default:
25250- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR023,
25251- SK_PNMI_ERR023MSG);
25252+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
25253+ (SK_PNMI_ERR023MSG));
25254
25255 *pLen = 0;
25256 return (SK_PNMI_ERR_GENERAL);
25257 }
25258 }
25259 else {
25260- /* The only OID which can be set is VPD_ACTION */
25261+ /* The only OID which can be set is VPD_ACTION. */
25262 if (Id != OID_SKGE_VPD_ACTION) {
25263
25264 if (Id == OID_SKGE_VPD_FREE_BYTES ||
25265@@ -3296,8 +3156,8 @@
25266 return (SK_PNMI_ERR_READ_ONLY);
25267 }
25268
25269- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR024,
25270- SK_PNMI_ERR024MSG);
25271+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
25272+ (SK_PNMI_ERR024MSG));
25273
25274 *pLen = 0;
25275 return (SK_PNMI_ERR_GENERAL);
25276@@ -3313,14 +3173,11 @@
25277 return (SK_PNMI_ERR_TOO_SHORT);
25278 }
25279
25280- /*
25281- * The first byte contains the VPD action type we should
25282- * perform.
25283- */
25284+ /* The first byte contains the VPD action type we should perform. */
25285 switch (*pBuf) {
25286
25287 case SK_PNMI_VPD_IGNORE:
25288- /* Nothing to do */
25289+ /* Nothing to do. */
25290 break;
25291
25292 case SK_PNMI_VPD_CREATE:
25293@@ -3352,13 +3209,13 @@
25294 SK_MEMCPY(Buf, pBuf + 4, Offset);
25295 Buf[Offset] = 0;
25296
25297- /* A preset ends here */
25298+ /* A PRESET ends here. */
25299 if (Action == SK_PNMI_PRESET) {
25300
25301 return (SK_PNMI_ERR_OK);
25302 }
25303
25304- /* Write the new entry or modify an existing one */
25305+ /* Write the new entry or modify an existing one .*/
25306 Ret = VpdWrite(pAC, IoC, KeyStr, Buf);
25307 if (Ret == SK_PNMI_VPD_NOWRITE ) {
25308
25309@@ -3367,8 +3224,8 @@
25310 }
25311 else if (Ret != SK_PNMI_VPD_OK) {
25312
25313- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR025,
25314- SK_PNMI_ERR025MSG);
25315+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
25316+ (SK_PNMI_ERR025MSG));
25317
25318 *pLen = 0;
25319 return (SK_PNMI_ERR_GENERAL);
25320@@ -3381,8 +3238,8 @@
25321 Ret = VpdUpdate(pAC, IoC);
25322 if (Ret != SK_PNMI_VPD_OK) {
25323
25324- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR026,
25325- SK_PNMI_ERR026MSG);
25326+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
25327+ (SK_PNMI_ERR026MSG));
25328
25329 *pLen = 0;
25330 return (SK_PNMI_ERR_GENERAL);
25331@@ -3390,7 +3247,7 @@
25332 break;
25333
25334 case SK_PNMI_VPD_DELETE:
25335- /* Check if the buffer size is plausible */
25336+ /* Check if the buffer size is plausible. */
25337 if (*pLen < 3) {
25338
25339 *pLen = 3;
25340@@ -3405,7 +3262,7 @@
25341 KeyStr[1] = pBuf[2];
25342 KeyStr[2] = 0;
25343
25344- /* Find the passed key in the array */
25345+ /* Find the passed key in the array. */
25346 for (Index = 0; Index < KeyNo; Index ++) {
25347
25348 if (SK_STRCMP(KeyStr, KeyArr[Index]) == 0) {
25349@@ -3413,6 +3270,7 @@
25350 break;
25351 }
25352 }
25353+
25354 /*
25355 * If we cannot find the key it is wrong, so we
25356 * return an appropriate error value.
25357@@ -3428,12 +3286,12 @@
25358 return (SK_PNMI_ERR_OK);
25359 }
25360
25361- /* Ok, you wanted it and you will get it */
25362+ /* Ok, you wanted it and you will get it. */
25363 Ret = VpdDelete(pAC, IoC, KeyStr);
25364 if (Ret != SK_PNMI_VPD_OK) {
25365
25366- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR027,
25367- SK_PNMI_ERR027MSG);
25368+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
25369+ (SK_PNMI_ERR027MSG));
25370
25371 *pLen = 0;
25372 return (SK_PNMI_ERR_GENERAL);
25373@@ -3446,8 +3304,8 @@
25374 Ret = VpdUpdate(pAC, IoC);
25375 if (Ret != SK_PNMI_VPD_OK) {
25376
25377- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR028,
25378- SK_PNMI_ERR028MSG);
25379+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
25380+ (SK_PNMI_ERR028MSG));
25381
25382 *pLen = 0;
25383 return (SK_PNMI_ERR_GENERAL);
25384@@ -3501,23 +3359,21 @@
25385 SK_U32 Val32;
25386 SK_U64 Val64;
25387 SK_U64 Val64RxHwErrs = 0;
25388+ SK_U64 Val64RxRunt = 0;
25389+ SK_U64 Val64RxFcs = 0;
25390 SK_U64 Val64TxHwErrs = 0;
25391 SK_BOOL Is64BitReq = SK_FALSE;
25392 char Buf[256];
25393 int MacType;
25394
25395- /*
25396- * Check instance. We only handle single instance variables.
25397- */
25398+ /* Check instance. We only handle single instance variables. */
25399 if (Instance != (SK_U32)(-1) && Instance != 1) {
25400
25401 *pLen = 0;
25402 return (SK_PNMI_ERR_UNKNOWN_INST);
25403 }
25404
25405- /*
25406- * Check action. We only allow get requests.
25407- */
25408+ /* Check action. We only allow get requests. */
25409 if (Action != SK_PNMI_GET) {
25410
25411 *pLen = 0;
25412@@ -3526,9 +3382,7 @@
25413
25414 MacType = pAC->GIni.GIMacType;
25415
25416- /*
25417- * Check length for the various supported OIDs
25418- */
25419+ /* Check length for the various supported OIDs. */
25420 switch (Id) {
25421
25422 case OID_GEN_XMIT_ERROR:
25423@@ -3542,14 +3396,12 @@
25424
25425 #else /* SK_NDIS_64BIT_CTR */
25426
25427- /*
25428- * for compatibility, at least 32bit are required for oid
25429- */
25430+ /* For compatibility, at least 32bit are required for OID. */
25431 if (*pLen < sizeof(SK_U32)) {
25432 /*
25433- * but indicate handling for 64bit values,
25434- * if insufficient space is provided
25435- */
25436+ * Indicate handling for 64bit values,
25437+ * if insufficient space is provided.
25438+ */
25439 *pLen = sizeof(SK_U64);
25440 return (SK_PNMI_ERR_TOO_SHORT);
25441 }
25442@@ -3620,11 +3472,11 @@
25443 break;
25444
25445 default:
25446- /* Checked later */
25447+ /* Checked later. */
25448 break;
25449 }
25450
25451- /* Update statistic */
25452+ /* Update statistics. */
25453 if (Id == OID_SKGE_RX_HW_ERROR_CTS ||
25454 Id == OID_SKGE_TX_HW_ERROR_CTS ||
25455 Id == OID_SKGE_IN_ERRORS_CTS ||
25456@@ -3632,7 +3484,8 @@
25457 Id == OID_GEN_XMIT_ERROR ||
25458 Id == OID_GEN_RCV_ERROR) {
25459
25460- /* Force the XMAC to update its statistic counters and
25461+ /*
25462+ * Force the XMAC to update its statistic counters and
25463 * Increment semaphore to indicate that an update was
25464 * already done.
25465 */
25466@@ -3663,14 +3516,29 @@
25467 GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_IRLENGTH, NetIndex) +
25468 GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_SYMBOL, NetIndex) +
25469 GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_SHORTS, NetIndex) +
25470- GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_RUNT, NetIndex) +
25471 GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_TOO_LONG, NetIndex) +
25472- GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_FCS, NetIndex) +
25473 GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_CEXT, NetIndex);
25474- break;
25475
25476- case OID_SKGE_TX_HW_ERROR_CTS:
25477- case OID_SKGE_OUT_ERROR_CTS:
25478+
25479+ /*
25480+ * In some cases the runt and fcs counters are incremented when collisions
25481+ * occur. We have to correct those counters here.
25482+ */
25483+ Val64RxRunt = GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_RUNT, NetIndex);
25484+ Val64RxFcs = GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_FCS, NetIndex);
25485+
25486+ if (Val64RxRunt > Val64RxFcs) {
25487+ Val64RxRunt -= Val64RxFcs;
25488+ Val64RxHwErrs += Val64RxRunt;
25489+ }
25490+ else {
25491+ Val64RxFcs -= Val64RxRunt;
25492+ Val64RxHwErrs += Val64RxFcs;
25493+ }
25494+ break;
25495+
25496+ case OID_SKGE_TX_HW_ERROR_CTS:
25497+ case OID_SKGE_OUT_ERROR_CTS:
25498 case OID_GEN_XMIT_ERROR:
25499 Val64TxHwErrs =
25500 GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_EXCESS_COL, NetIndex) +
25501@@ -3681,9 +3549,7 @@
25502 }
25503 }
25504
25505- /*
25506- * Retrieve value
25507- */
25508+ /* Retrieve value. */
25509 switch (Id) {
25510
25511 case OID_SKGE_SUPPORTED_LIST:
25512@@ -3693,11 +3559,11 @@
25513 *pLen = Len;
25514 return (SK_PNMI_ERR_TOO_SHORT);
25515 }
25516- for (Offset = 0, Index = 0; Offset < Len;
25517- Offset += sizeof(SK_U32), Index ++) {
25518+ for (Offset = 0, Index = 0; Offset < Len; Index ++) {
25519
25520 Val32 = (SK_U32)IdTable[Index].Id;
25521 SK_PNMI_STORE_U32(pBuf + Offset, Val32);
25522+ Offset += sizeof(SK_U32);
25523 }
25524 *pLen = Len;
25525 break;
25526@@ -3723,8 +3589,7 @@
25527 case OID_SKGE_DRIVER_DESCR:
25528 if (pAC->Pnmi.pDriverDescription == NULL) {
25529
25530- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR007,
25531- SK_PNMI_ERR007MSG);
25532+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR007, SK_PNMI_ERR007MSG);
25533
25534 *pLen = 0;
25535 return (SK_PNMI_ERR_GENERAL);
25536@@ -3733,8 +3598,7 @@
25537 Len = SK_STRLEN(pAC->Pnmi.pDriverDescription) + 1;
25538 if (Len > SK_PNMI_STRINGLEN1) {
25539
25540- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR029,
25541- SK_PNMI_ERR029MSG);
25542+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR029, SK_PNMI_ERR029MSG);
25543
25544 *pLen = 0;
25545 return (SK_PNMI_ERR_GENERAL);
25546@@ -3753,8 +3617,7 @@
25547 case OID_SKGE_DRIVER_VERSION:
25548 if (pAC->Pnmi.pDriverVersion == NULL) {
25549
25550- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR030,
25551- SK_PNMI_ERR030MSG);
25552+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR030, SK_PNMI_ERR030MSG);
25553
25554 *pLen = 0;
25555 return (SK_PNMI_ERR_GENERAL);
25556@@ -3763,8 +3626,7 @@
25557 Len = SK_STRLEN(pAC->Pnmi.pDriverVersion) + 1;
25558 if (Len > SK_PNMI_STRINGLEN1) {
25559
25560- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR031,
25561- SK_PNMI_ERR031MSG);
25562+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR031, SK_PNMI_ERR031MSG);
25563
25564 *pLen = 0;
25565 return (SK_PNMI_ERR_GENERAL);
25566@@ -3783,8 +3645,7 @@
25567 case OID_SKGE_DRIVER_RELDATE:
25568 if (pAC->Pnmi.pDriverReleaseDate == NULL) {
25569
25570- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR030,
25571- SK_PNMI_ERR053MSG);
25572+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR053, SK_PNMI_ERR053MSG);
25573
25574 *pLen = 0;
25575 return (SK_PNMI_ERR_GENERAL);
25576@@ -3793,8 +3654,7 @@
25577 Len = SK_STRLEN(pAC->Pnmi.pDriverReleaseDate) + 1;
25578 if (Len > SK_PNMI_STRINGLEN1) {
25579
25580- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR031,
25581- SK_PNMI_ERR054MSG);
25582+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR054, SK_PNMI_ERR054MSG);
25583
25584 *pLen = 0;
25585 return (SK_PNMI_ERR_GENERAL);
25586@@ -3813,8 +3673,7 @@
25587 case OID_SKGE_DRIVER_FILENAME:
25588 if (pAC->Pnmi.pDriverFileName == NULL) {
25589
25590- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR030,
25591- SK_PNMI_ERR055MSG);
25592+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR055, SK_PNMI_ERR055MSG);
25593
25594 *pLen = 0;
25595 return (SK_PNMI_ERR_GENERAL);
25596@@ -3823,8 +3682,7 @@
25597 Len = SK_STRLEN(pAC->Pnmi.pDriverFileName) + 1;
25598 if (Len > SK_PNMI_STRINGLEN1) {
25599
25600- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR031,
25601- SK_PNMI_ERR056MSG);
25602+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR056, SK_PNMI_ERR056MSG);
25603
25604 *pLen = 0;
25605 return (SK_PNMI_ERR_GENERAL);
25606@@ -3846,12 +3704,16 @@
25607 * query may move to the initialisation routine. But
25608 * the VPD data is cached and therefore a call here
25609 * will not make much difference.
25610+ * Please read comment in Vpd().
25611 */
25612+ if (pAC->Pnmi.VpdKeyReadError == SK_TRUE) {
25613+ return (SK_PNMI_ERR_OK);
25614+ }
25615+
25616 Len = 256;
25617 if (VpdRead(pAC, IoC, VPD_NAME, Buf, (int *)&Len) > 0) {
25618
25619- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR032,
25620- SK_PNMI_ERR032MSG);
25621+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR032, SK_PNMI_ERR032MSG);
25622
25623 *pLen = 0;
25624 return (SK_PNMI_ERR_GENERAL);
25625@@ -3859,8 +3721,7 @@
25626 Len ++;
25627 if (Len > SK_PNMI_STRINGLEN1) {
25628
25629- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR033,
25630- SK_PNMI_ERR033MSG);
25631+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR033, SK_PNMI_ERR033MSG);
25632
25633 *pLen = 0;
25634 return (SK_PNMI_ERR_GENERAL);
25635@@ -3876,7 +3737,6 @@
25636 break;
25637
25638 case OID_SKGE_HW_VERSION:
25639- /* Oh, I love to do some string manipulation */
25640 if (*pLen < 5) {
25641
25642 *pLen = 5;
25643@@ -3885,9 +3745,9 @@
25644 Val8 = (SK_U8)pAC->GIni.GIPciHwRev;
25645 pBuf[0] = 4;
25646 pBuf[1] = 'v';
25647- pBuf[2] = (char)(0x30 | ((Val8 >> 4) & 0x0F));
25648+ pBuf[2] = (char)('0' | ((Val8 >> 4) & 0x0f));
25649 pBuf[3] = '.';
25650- pBuf[4] = (char)(0x30 | (Val8 & 0x0F));
25651+ pBuf[4] = (char)('0' | (Val8 & 0x0f));
25652 *pLen = 5;
25653 break;
25654
25655@@ -3910,12 +3770,12 @@
25656 break;
25657
25658 case OID_SKGE_VAUXAVAIL:
25659- *pBuf = (char) pAC->GIni.GIVauxAvail;
25660+ *pBuf = (char)pAC->GIni.GIVauxAvail;
25661 *pLen = sizeof(char);
25662 break;
25663
25664 case OID_SKGE_BUS_TYPE:
25665- *pBuf = (char) SK_PNMI_BUS_PCI;
25666+ *pBuf = (char)SK_PNMI_BUS_PCI;
25667 *pLen = sizeof(char);
25668 break;
25669
25670@@ -3964,31 +3824,31 @@
25671 break;
25672
25673 case OID_SKGE_RLMT_MONITOR_NUMBER:
25674-/* XXX Not yet implemented by RLMT therefore we return zero elements */
25675+ /* Not yet implemented by RLMT, therefore we return zero elements. */
25676 Val32 = 0;
25677 SK_PNMI_STORE_U32(pBuf, Val32);
25678 *pLen = sizeof(SK_U32);
25679 break;
25680
25681 case OID_SKGE_TX_SW_QUEUE_LEN:
25682- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25683+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25684 if (MacType == SK_MAC_XMAC) {
25685- /* Dual net mode */
25686+ /* DualNet mode. */
25687 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25688 Val64 = pAC->Pnmi.BufPort[NetIndex].TxSwQueueLen;
25689 }
25690- /* Single net mode */
25691+ /* SingleNet mode. */
25692 else {
25693 Val64 = pAC->Pnmi.BufPort[0].TxSwQueueLen +
25694 pAC->Pnmi.BufPort[1].TxSwQueueLen;
25695 }
25696 }
25697 else {
25698- /* Dual net mode */
25699+ /* DualNet mode. */
25700 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25701 Val64 = pAC->Pnmi.Port[NetIndex].TxSwQueueLen;
25702 }
25703- /* Single net mode */
25704+ /* SingleNet mode. */
25705 else {
25706 Val64 = pAC->Pnmi.Port[0].TxSwQueueLen +
25707 pAC->Pnmi.Port[1].TxSwQueueLen;
25708@@ -4000,24 +3860,24 @@
25709
25710
25711 case OID_SKGE_TX_SW_QUEUE_MAX:
25712- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25713+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25714 if (MacType == SK_MAC_XMAC) {
25715- /* Dual net mode */
25716+ /* DualNet mode. */
25717 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25718 Val64 = pAC->Pnmi.BufPort[NetIndex].TxSwQueueMax;
25719 }
25720- /* Single net mode */
25721+ /* SingleNet mode. */
25722 else {
25723 Val64 = pAC->Pnmi.BufPort[0].TxSwQueueMax +
25724 pAC->Pnmi.BufPort[1].TxSwQueueMax;
25725 }
25726 }
25727 else {
25728- /* Dual net mode */
25729+ /* DualNet mode. */
25730 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25731 Val64 = pAC->Pnmi.Port[NetIndex].TxSwQueueMax;
25732 }
25733- /* Single net mode */
25734+ /* SingleNet mode. */
25735 else {
25736 Val64 = pAC->Pnmi.Port[0].TxSwQueueMax +
25737 pAC->Pnmi.Port[1].TxSwQueueMax;
25738@@ -4028,24 +3888,24 @@
25739 break;
25740
25741 case OID_SKGE_TX_RETRY:
25742- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25743+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25744 if (MacType == SK_MAC_XMAC) {
25745- /* Dual net mode */
25746+ /* DualNet mode. */
25747 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25748 Val64 = pAC->Pnmi.BufPort[NetIndex].TxRetryCts;
25749 }
25750- /* Single net mode */
25751+ /* SingleNet mode. */
25752 else {
25753 Val64 = pAC->Pnmi.BufPort[0].TxRetryCts +
25754 pAC->Pnmi.BufPort[1].TxRetryCts;
25755 }
25756 }
25757 else {
25758- /* Dual net mode */
25759+ /* DualNet mode. */
25760 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25761 Val64 = pAC->Pnmi.Port[NetIndex].TxRetryCts;
25762 }
25763- /* Single net mode */
25764+ /* SingleNet mode. */
25765 else {
25766 Val64 = pAC->Pnmi.Port[0].TxRetryCts +
25767 pAC->Pnmi.Port[1].TxRetryCts;
25768@@ -4056,24 +3916,24 @@
25769 break;
25770
25771 case OID_SKGE_RX_INTR_CTS:
25772- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25773+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25774 if (MacType == SK_MAC_XMAC) {
25775- /* Dual net mode */
25776+ /* DualNet mode. */
25777 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25778 Val64 = pAC->Pnmi.BufPort[NetIndex].RxIntrCts;
25779 }
25780- /* Single net mode */
25781+ /* SingleNet mode. */
25782 else {
25783 Val64 = pAC->Pnmi.BufPort[0].RxIntrCts +
25784 pAC->Pnmi.BufPort[1].RxIntrCts;
25785 }
25786 }
25787 else {
25788- /* Dual net mode */
25789+ /* DualNet mode. */
25790 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25791 Val64 = pAC->Pnmi.Port[NetIndex].RxIntrCts;
25792 }
25793- /* Single net mode */
25794+ /* SingleNet mode. */
25795 else {
25796 Val64 = pAC->Pnmi.Port[0].RxIntrCts +
25797 pAC->Pnmi.Port[1].RxIntrCts;
25798@@ -4084,24 +3944,24 @@
25799 break;
25800
25801 case OID_SKGE_TX_INTR_CTS:
25802- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25803+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25804 if (MacType == SK_MAC_XMAC) {
25805- /* Dual net mode */
25806+ /* DualNet mode. */
25807 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25808 Val64 = pAC->Pnmi.BufPort[NetIndex].TxIntrCts;
25809 }
25810- /* Single net mode */
25811+ /* SingleNet mode. */
25812 else {
25813 Val64 = pAC->Pnmi.BufPort[0].TxIntrCts +
25814 pAC->Pnmi.BufPort[1].TxIntrCts;
25815 }
25816 }
25817 else {
25818- /* Dual net mode */
25819+ /* DualNet mode. */
25820 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25821 Val64 = pAC->Pnmi.Port[NetIndex].TxIntrCts;
25822 }
25823- /* Single net mode */
25824+ /* SingleNet mode. */
25825 else {
25826 Val64 = pAC->Pnmi.Port[0].TxIntrCts +
25827 pAC->Pnmi.Port[1].TxIntrCts;
25828@@ -4112,24 +3972,24 @@
25829 break;
25830
25831 case OID_SKGE_RX_NO_BUF_CTS:
25832- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25833+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25834 if (MacType == SK_MAC_XMAC) {
25835- /* Dual net mode */
25836+ /* DualNet mode. */
25837 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25838 Val64 = pAC->Pnmi.BufPort[NetIndex].RxNoBufCts;
25839 }
25840- /* Single net mode */
25841+ /* SingleNet mode. */
25842 else {
25843 Val64 = pAC->Pnmi.BufPort[0].RxNoBufCts +
25844 pAC->Pnmi.BufPort[1].RxNoBufCts;
25845 }
25846 }
25847 else {
25848- /* Dual net mode */
25849+ /* DualNet mode. */
25850 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25851 Val64 = pAC->Pnmi.Port[NetIndex].RxNoBufCts;
25852 }
25853- /* Single net mode */
25854+ /* SingleNet mode. */
25855 else {
25856 Val64 = pAC->Pnmi.Port[0].RxNoBufCts +
25857 pAC->Pnmi.Port[1].RxNoBufCts;
25858@@ -4140,24 +4000,24 @@
25859 break;
25860
25861 case OID_SKGE_TX_NO_BUF_CTS:
25862- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25863+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25864 if (MacType == SK_MAC_XMAC) {
25865- /* Dual net mode */
25866+ /* DualNet mode. */
25867 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25868 Val64 = pAC->Pnmi.BufPort[NetIndex].TxNoBufCts;
25869 }
25870- /* Single net mode */
25871+ /* SingleNet mode. */
25872 else {
25873 Val64 = pAC->Pnmi.BufPort[0].TxNoBufCts +
25874 pAC->Pnmi.BufPort[1].TxNoBufCts;
25875 }
25876 }
25877 else {
25878- /* Dual net mode */
25879+ /* DualNet mode. */
25880 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25881 Val64 = pAC->Pnmi.Port[NetIndex].TxNoBufCts;
25882 }
25883- /* Single net mode */
25884+ /* SingleNet mode. */
25885 else {
25886 Val64 = pAC->Pnmi.Port[0].TxNoBufCts +
25887 pAC->Pnmi.Port[1].TxNoBufCts;
25888@@ -4168,24 +4028,24 @@
25889 break;
25890
25891 case OID_SKGE_TX_USED_DESCR_NO:
25892- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25893+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25894 if (MacType == SK_MAC_XMAC) {
25895- /* Dual net mode */
25896+ /* DualNet mode. */
25897 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25898 Val64 = pAC->Pnmi.BufPort[NetIndex].TxUsedDescrNo;
25899 }
25900- /* Single net mode */
25901+ /* SingleNet mode. */
25902 else {
25903 Val64 = pAC->Pnmi.BufPort[0].TxUsedDescrNo +
25904 pAC->Pnmi.BufPort[1].TxUsedDescrNo;
25905 }
25906 }
25907 else {
25908- /* Dual net mode */
25909+ /* DualNet mode. */
25910 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25911 Val64 = pAC->Pnmi.Port[NetIndex].TxUsedDescrNo;
25912 }
25913- /* Single net mode */
25914+ /* SingleNet mode. */
25915 else {
25916 Val64 = pAC->Pnmi.Port[0].TxUsedDescrNo +
25917 pAC->Pnmi.Port[1].TxUsedDescrNo;
25918@@ -4196,24 +4056,24 @@
25919 break;
25920
25921 case OID_SKGE_RX_DELIVERED_CTS:
25922- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25923+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25924 if (MacType == SK_MAC_XMAC) {
25925- /* Dual net mode */
25926+ /* DualNet mode. */
25927 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25928 Val64 = pAC->Pnmi.BufPort[NetIndex].RxDeliveredCts;
25929 }
25930- /* Single net mode */
25931+ /* SingleNet mode. */
25932 else {
25933 Val64 = pAC->Pnmi.BufPort[0].RxDeliveredCts +
25934 pAC->Pnmi.BufPort[1].RxDeliveredCts;
25935 }
25936 }
25937 else {
25938- /* Dual net mode */
25939+ /* DualNet mode. */
25940 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25941 Val64 = pAC->Pnmi.Port[NetIndex].RxDeliveredCts;
25942 }
25943- /* Single net mode */
25944+ /* SingleNet mode. */
25945 else {
25946 Val64 = pAC->Pnmi.Port[0].RxDeliveredCts +
25947 pAC->Pnmi.Port[1].RxDeliveredCts;
25948@@ -4224,24 +4084,24 @@
25949 break;
25950
25951 case OID_SKGE_RX_OCTETS_DELIV_CTS:
25952- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25953+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25954 if (MacType == SK_MAC_XMAC) {
25955- /* Dual net mode */
25956+ /* DualNet mode. */
25957 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25958 Val64 = pAC->Pnmi.BufPort[NetIndex].RxOctetsDeliveredCts;
25959 }
25960- /* Single net mode */
25961+ /* SingleNet mode. */
25962 else {
25963 Val64 = pAC->Pnmi.BufPort[0].RxOctetsDeliveredCts +
25964 pAC->Pnmi.BufPort[1].RxOctetsDeliveredCts;
25965 }
25966 }
25967 else {
25968- /* Dual net mode */
25969+ /* DualNet mode. */
25970 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25971 Val64 = pAC->Pnmi.Port[NetIndex].RxOctetsDeliveredCts;
25972 }
25973- /* Single net mode */
25974+ /* SingleNet mode. */
25975 else {
25976 Val64 = pAC->Pnmi.Port[0].RxOctetsDeliveredCts +
25977 pAC->Pnmi.Port[1].RxOctetsDeliveredCts;
25978@@ -4262,13 +4122,13 @@
25979 break;
25980
25981 case OID_SKGE_IN_ERRORS_CTS:
25982- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
25983+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
25984 if (MacType == SK_MAC_XMAC) {
25985- /* Dual net mode */
25986+ /* DualNet mode. */
25987 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
25988 Val64 = Val64RxHwErrs + pAC->Pnmi.BufPort[NetIndex].RxNoBufCts;
25989 }
25990- /* Single net mode */
25991+ /* SingleNet mode. */
25992 else {
25993 Val64 = Val64RxHwErrs +
25994 pAC->Pnmi.BufPort[0].RxNoBufCts +
25995@@ -4276,11 +4136,11 @@
25996 }
25997 }
25998 else {
25999- /* Dual net mode */
26000+ /* DualNet mode. */
26001 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
26002 Val64 = Val64RxHwErrs + pAC->Pnmi.Port[NetIndex].RxNoBufCts;
26003 }
26004- /* Single net mode */
26005+ /* SingleNet mode. */
26006 else {
26007 Val64 = Val64RxHwErrs +
26008 pAC->Pnmi.Port[0].RxNoBufCts +
26009@@ -4292,13 +4152,13 @@
26010 break;
26011
26012 case OID_SKGE_OUT_ERROR_CTS:
26013- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
26014+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
26015 if (MacType == SK_MAC_XMAC) {
26016- /* Dual net mode */
26017+ /* DualNet mode. */
26018 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
26019 Val64 = Val64TxHwErrs + pAC->Pnmi.BufPort[NetIndex].TxNoBufCts;
26020 }
26021- /* Single net mode */
26022+ /* SingleNet mode. */
26023 else {
26024 Val64 = Val64TxHwErrs +
26025 pAC->Pnmi.BufPort[0].TxNoBufCts +
26026@@ -4306,11 +4166,11 @@
26027 }
26028 }
26029 else {
26030- /* Dual net mode */
26031+ /* DualNet mode. */
26032 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
26033 Val64 = Val64TxHwErrs + pAC->Pnmi.Port[NetIndex].TxNoBufCts;
26034 }
26035- /* Single net mode */
26036+ /* SingleNet mode. */
26037 else {
26038 Val64 = Val64TxHwErrs +
26039 pAC->Pnmi.Port[0].TxNoBufCts +
26040@@ -4322,24 +4182,24 @@
26041 break;
26042
26043 case OID_SKGE_ERR_RECOVERY_CTS:
26044- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
26045+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
26046 if (MacType == SK_MAC_XMAC) {
26047- /* Dual net mode */
26048+ /* DualNet mode. */
26049 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
26050 Val64 = pAC->Pnmi.BufPort[NetIndex].ErrRecoveryCts;
26051 }
26052- /* Single net mode */
26053+ /* SingleNet mode. */
26054 else {
26055 Val64 = pAC->Pnmi.BufPort[0].ErrRecoveryCts +
26056 pAC->Pnmi.BufPort[1].ErrRecoveryCts;
26057 }
26058 }
26059 else {
26060- /* Dual net mode */
26061+ /* DualNet mode. */
26062 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
26063 Val64 = pAC->Pnmi.Port[NetIndex].ErrRecoveryCts;
26064 }
26065- /* Single net mode */
26066+ /* SingleNet mode. */
26067 else {
26068 Val64 = pAC->Pnmi.Port[0].ErrRecoveryCts +
26069 pAC->Pnmi.Port[1].ErrRecoveryCts;
26070@@ -4363,7 +4223,7 @@
26071 break;
26072
26073 case OID_GEN_RCV_ERROR:
26074- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
26075+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
26076 if (MacType == SK_MAC_XMAC) {
26077 Val64 = Val64RxHwErrs + pAC->Pnmi.BufPort[NetIndex].RxNoBufCts;
26078 }
26079@@ -4372,7 +4232,7 @@
26080 }
26081
26082 /*
26083- * by default 32bit values are evaluated
26084+ * By default 32bit values are evaluated.
26085 */
26086 if (!Is64BitReq) {
26087 Val32 = (SK_U32)Val64;
26088@@ -4386,7 +4246,7 @@
26089 break;
26090
26091 case OID_GEN_XMIT_ERROR:
26092- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
26093+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
26094 if (MacType == SK_MAC_XMAC) {
26095 Val64 = Val64TxHwErrs + pAC->Pnmi.BufPort[NetIndex].TxNoBufCts;
26096 }
26097@@ -4395,7 +4255,7 @@
26098 }
26099
26100 /*
26101- * by default 32bit values are evaluated
26102+ * By default 32bit values are evaluated.
26103 */
26104 if (!Is64BitReq) {
26105 Val32 = (SK_U32)Val64;
26106@@ -4409,16 +4269,19 @@
26107 break;
26108
26109 case OID_GEN_RCV_NO_BUFFER:
26110- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
26111+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
26112 if (MacType == SK_MAC_XMAC) {
26113- Val64 = pAC->Pnmi.BufPort[NetIndex].RxNoBufCts;
26114+ Val64 = pAC->Pnmi.BufPort[NetIndex].RxNoBufCts +
26115+ GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_OVERFLOW, NetIndex);
26116+
26117 }
26118 else {
26119- Val64 = pAC->Pnmi.Port[NetIndex].RxNoBufCts;
26120+ Val64 = pAC->Pnmi.Port[NetIndex].RxNoBufCts +
26121+ GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_OVERFLOW, NetIndex);
26122 }
26123
26124 /*
26125- * by default 32bit values are evaluated
26126+ * By default 32bit values are evaluated.
26127 */
26128 if (!Is64BitReq) {
26129 Val32 = (SK_U32)Val64;
26130@@ -4438,8 +4301,7 @@
26131 break;
26132
26133 default:
26134- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR034,
26135- SK_PNMI_ERR034MSG);
26136+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR034, SK_PNMI_ERR034MSG);
26137
26138 *pLen = 0;
26139 return (SK_PNMI_ERR_GENERAL);
26140@@ -4496,25 +4358,17 @@
26141 SK_U32 Val32;
26142 SK_U64 Val64;
26143
26144-
26145- /*
26146- * Check instance. Only single instance OIDs are allowed here.
26147- */
26148+ /* Check instance. Only single instance OIDs are allowed here. */
26149 if (Instance != (SK_U32)(-1) && Instance != 1) {
26150
26151 *pLen = 0;
26152 return (SK_PNMI_ERR_UNKNOWN_INST);
26153 }
26154
26155- /*
26156- * Perform the requested action.
26157- */
26158+ /* Perform the requested action. */
26159 if (Action == SK_PNMI_GET) {
26160
26161- /*
26162- * Check if the buffer length is large enough.
26163- */
26164-
26165+ /* Check if the buffer length is large enough. */
26166 switch (Id) {
26167
26168 case OID_SKGE_RLMT_MODE:
26169@@ -4547,8 +4401,7 @@
26170 break;
26171
26172 default:
26173- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR035,
26174- SK_PNMI_ERR035MSG);
26175+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR035, SK_PNMI_ERR035MSG);
26176
26177 *pLen = 0;
26178 return (SK_PNMI_ERR_GENERAL);
26179@@ -4567,9 +4420,7 @@
26180 }
26181 pAC->Pnmi.RlmtUpdatedFlag ++;
26182
26183- /*
26184- * Retrieve Value
26185- */
26186+ /* Retrieve value. */
26187 switch (Id) {
26188
26189 case OID_SKGE_RLMT_MODE:
26190@@ -4647,17 +4498,17 @@
26191 pAC->Pnmi.RlmtUpdatedFlag --;
26192 }
26193 else {
26194- /* Perform a preset or set */
26195+ /* Perform a PRESET or SET. */
26196 switch (Id) {
26197
26198 case OID_SKGE_RLMT_MODE:
26199- /* Check if the buffer length is plausible */
26200+ /* Check if the buffer length is plausible. */
26201 if (*pLen < sizeof(char)) {
26202
26203 *pLen = sizeof(char);
26204 return (SK_PNMI_ERR_TOO_SHORT);
26205 }
26206- /* Check if the value range is correct */
26207+ /* Check if the value range is correct. */
26208 if (*pLen != sizeof(char) ||
26209 (*pBuf & SK_PNMI_RLMT_MODE_CHK_LINK) == 0 ||
26210 *(SK_U8 *)pBuf > 15) {
26211@@ -4665,21 +4516,21 @@
26212 *pLen = 0;
26213 return (SK_PNMI_ERR_BAD_VALUE);
26214 }
26215- /* The preset ends here */
26216+ /* The PRESET ends here. */
26217 if (Action == SK_PNMI_PRESET) {
26218
26219 *pLen = 0;
26220 return (SK_PNMI_ERR_OK);
26221 }
26222- /* Send an event to RLMT to change the mode */
26223+ /* Send an event to RLMT to change the mode. */
26224 SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
26225+
26226 EventParam.Para32[0] |= (SK_U32)(*pBuf);
26227 EventParam.Para32[1] = 0;
26228 if (SkRlmtEvent(pAC, IoC, SK_RLMT_MODE_CHANGE,
26229 EventParam) > 0) {
26230
26231- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR037,
26232- SK_PNMI_ERR037MSG);
26233+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR037, SK_PNMI_ERR037MSG);
26234
26235 *pLen = 0;
26236 return (SK_PNMI_ERR_GENERAL);
26237@@ -4687,20 +4538,25 @@
26238 break;
26239
26240 case OID_SKGE_RLMT_PORT_PREFERRED:
26241- /* Check if the buffer length is plausible */
26242+ /* PRESET/SET action makes no sense in Dual Net mode. */
26243+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
26244+ break;
26245+ }
26246+
26247+ /* Check if the buffer length is plausible. */
26248 if (*pLen < sizeof(char)) {
26249
26250 *pLen = sizeof(char);
26251 return (SK_PNMI_ERR_TOO_SHORT);
26252 }
26253- /* Check if the value range is correct */
26254+ /* Check if the value range is correct. */
26255 if (*pLen != sizeof(char) || *(SK_U8 *)pBuf >
26256 (SK_U8)pAC->GIni.GIMacsFound) {
26257
26258 *pLen = 0;
26259 return (SK_PNMI_ERR_BAD_VALUE);
26260 }
26261- /* The preset ends here */
26262+ /* The PRESET ends here. */
26263 if (Action == SK_PNMI_PRESET) {
26264
26265 *pLen = 0;
26266@@ -4713,13 +4569,13 @@
26267 * make the decision which is the preferred port.
26268 */
26269 SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
26270+
26271 EventParam.Para32[0] = (SK_U32)(*pBuf) - 1;
26272 EventParam.Para32[1] = NetIndex;
26273 if (SkRlmtEvent(pAC, IoC, SK_RLMT_PREFPORT_CHANGE,
26274 EventParam) > 0) {
26275
26276- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR038,
26277- SK_PNMI_ERR038MSG);
26278+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR038, SK_PNMI_ERR038MSG);
26279
26280 *pLen = 0;
26281 return (SK_PNMI_ERR_GENERAL);
26282@@ -4727,22 +4583,20 @@
26283 break;
26284
26285 case OID_SKGE_RLMT_CHANGE_THRES:
26286- /* Check if the buffer length is plausible */
26287+ /* Check if the buffer length is plausible. */
26288 if (*pLen < sizeof(SK_U64)) {
26289
26290 *pLen = sizeof(SK_U64);
26291 return (SK_PNMI_ERR_TOO_SHORT);
26292 }
26293- /*
26294- * There are not many restrictions to the
26295- * value range.
26296- */
26297+
26298+ /* There are not many restrictions to the value range. */
26299 if (*pLen != sizeof(SK_U64)) {
26300
26301 *pLen = 0;
26302 return (SK_PNMI_ERR_BAD_VALUE);
26303 }
26304- /* A preset ends here */
26305+ /* The PRESET ends here. */
26306 if (Action == SK_PNMI_PRESET) {
26307
26308 *pLen = 0;
26309@@ -4757,7 +4611,7 @@
26310 break;
26311
26312 default:
26313- /* The other OIDs are not be able for set */
26314+ /* The other OIDs are not be able for set. */
26315 *pLen = 0;
26316 return (SK_PNMI_ERR_READ_ONLY);
26317 }
26318@@ -4802,54 +4656,49 @@
26319 SK_U32 Val32;
26320 SK_U64 Val64;
26321
26322- /*
26323- * Calculate the port indexes from the instance.
26324- */
26325+
26326+ /* Calculate the port indexes from the instance. */
26327 PhysPortMax = pAC->GIni.GIMacsFound;
26328
26329 if ((Instance != (SK_U32)(-1))) {
26330- /* Check instance range */
26331+ /* Check instance range. */
26332 if ((Instance < 1) || (Instance > PhysPortMax)) {
26333
26334 *pLen = 0;
26335 return (SK_PNMI_ERR_UNKNOWN_INST);
26336 }
26337
26338- /* Single net mode */
26339+ /* SingleNet mode. */
26340 PhysPortIndex = Instance - 1;
26341
26342- /* Dual net mode */
26343+ /* DualNet mode. */
26344 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
26345 PhysPortIndex = NetIndex;
26346 }
26347
26348- /* Both net modes */
26349+ /* Both net modes. */
26350 Limit = PhysPortIndex + 1;
26351 }
26352 else {
26353- /* Single net mode */
26354+ /* SingleNet mode. */
26355 PhysPortIndex = 0;
26356 Limit = PhysPortMax;
26357
26358- /* Dual net mode */
26359+ /* DualNet mode. */
26360 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
26361 PhysPortIndex = NetIndex;
26362 Limit = PhysPortIndex + 1;
26363 }
26364 }
26365
26366- /*
26367- * Currently only get requests are allowed.
26368- */
26369+ /* Currently only GET requests are allowed. */
26370 if (Action != SK_PNMI_GET) {
26371
26372 *pLen = 0;
26373 return (SK_PNMI_ERR_READ_ONLY);
26374 }
26375
26376- /*
26377- * Check if the buffer length is large enough.
26378- */
26379+ /* Check if the buffer length is large enough. */
26380 switch (Id) {
26381
26382 case OID_SKGE_RLMT_PORT_INDEX:
26383@@ -4873,8 +4722,7 @@
26384 break;
26385
26386 default:
26387- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR039,
26388- SK_PNMI_ERR039MSG);
26389+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR039, SK_PNMI_ERR039MSG);
26390
26391 *pLen = 0;
26392 return (SK_PNMI_ERR_GENERAL);
26393@@ -4892,9 +4740,7 @@
26394 }
26395 pAC->Pnmi.RlmtUpdatedFlag ++;
26396
26397- /*
26398- * Get value
26399- */
26400+ /* Get value. */
26401 Offset = 0;
26402 for (; PhysPortIndex < Limit; PhysPortIndex ++) {
26403
26404@@ -5007,19 +4853,21 @@
26405 int Ret;
26406 SK_EVPARA EventParam;
26407 SK_U32 Val32;
26408+#ifdef SK_PHY_LP_MODE
26409+ SK_U8 CurrentPhyPowerState;
26410+#endif /* SK_PHY_LP_MODE */
26411
26412- /*
26413- * Calculate instance if wished. MAC index 0 is the virtual MAC.
26414- */
26415+
26416+ /* Calculate instance if wished. MAC index 0 is the virtual MAC. */
26417 PhysPortMax = pAC->GIni.GIMacsFound;
26418 LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax);
26419
26420- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* Dual net mode */
26421+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* DualNet mode. */
26422 LogPortMax--;
26423 }
26424
26425- if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried */
26426- /* Check instance range */
26427+ if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried. */
26428+ /* Check instance range. */
26429 if ((Instance < 1) || (Instance > LogPortMax)) {
26430
26431 *pLen = 0;
26432@@ -5029,18 +4877,16 @@
26433 Limit = LogPortIndex + 1;
26434 }
26435
26436- else { /* Instance == (SK_U32)(-1), get all Instances of that OID */
26437+ else { /* Instance == (SK_U32)(-1), get all Instances of that OID. */
26438
26439 LogPortIndex = 0;
26440 Limit = LogPortMax;
26441 }
26442
26443- /*
26444- * Perform action
26445- */
26446+ /* Perform action. */
26447 if (Action == SK_PNMI_GET) {
26448
26449- /* Check length */
26450+ /* Check length. */
26451 switch (Id) {
26452
26453 case OID_SKGE_PMD:
26454@@ -5058,6 +4904,9 @@
26455 case OID_SKGE_SPEED_CAP:
26456 case OID_SKGE_SPEED_MODE:
26457 case OID_SKGE_SPEED_STATUS:
26458+#ifdef SK_PHY_LP_MODE
26459+ case OID_SKGE_PHY_LP_MODE:
26460+#endif
26461 if (*pLen < (Limit - LogPortIndex) * sizeof(SK_U8)) {
26462
26463 *pLen = (Limit - LogPortIndex) * sizeof(SK_U8);
26464@@ -5075,8 +4924,7 @@
26465 break;
26466
26467 default:
26468- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR041,
26469- SK_PNMI_ERR041MSG);
26470+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR041, SK_PNMI_ERR041MSG);
26471 *pLen = 0;
26472 return (SK_PNMI_ERR_GENERAL);
26473 }
26474@@ -5092,9 +4940,7 @@
26475 }
26476 pAC->Pnmi.SirqUpdatedFlag ++;
26477
26478- /*
26479- * Get value
26480- */
26481+ /* Get value. */
26482 Offset = 0;
26483 for (; LogPortIndex < Limit; LogPortIndex ++) {
26484
26485@@ -5104,85 +4950,99 @@
26486
26487 case OID_SKGE_PMD:
26488 *pBufPtr = pAC->Pnmi.PMD;
26489- Offset += sizeof(char);
26490+ Offset ++;
26491 break;
26492
26493 case OID_SKGE_CONNECTOR:
26494 *pBufPtr = pAC->Pnmi.Connector;
26495- Offset += sizeof(char);
26496+ Offset ++;
26497 break;
26498
26499 case OID_SKGE_PHY_TYPE:
26500- if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26501+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26502 if (LogPortIndex == 0) {
26503 continue;
26504 }
26505- else {
26506- /* Get value for physical ports */
26507- PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26508- pAC, LogPortIndex);
26509- Val32 = pAC->GIni.GP[PhysPortIndex].PhyType;
26510- SK_PNMI_STORE_U32(pBufPtr, Val32);
26511- }
26512+ /* Get value for physical port. */
26513+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);
26514+ Val32 = pAC->GIni.GP[PhysPortIndex].PhyType;
26515 }
26516- else { /* DualNetMode */
26517+ else { /* DualNet mode. */
26518
26519 Val32 = pAC->GIni.GP[NetIndex].PhyType;
26520- SK_PNMI_STORE_U32(pBufPtr, Val32);
26521 }
26522+ SK_PNMI_STORE_U32(pBufPtr, Val32);
26523 Offset += sizeof(SK_U32);
26524 break;
26525
26526+#ifdef SK_PHY_LP_MODE
26527+ case OID_SKGE_PHY_LP_MODE:
26528+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26529+ if (LogPortIndex == 0) {
26530+ continue;
26531+ }
26532+ /* Get value for physical port. */
26533+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);
26534+ *pBufPtr = (SK_U8)pAC->GIni.GP[PhysPortIndex].PPhyPowerState;
26535+ }
26536+ else { /* DualNet mode. */
26537+
26538+ *pBufPtr = (SK_U8)pAC->GIni.GP[NetIndex].PPhyPowerState;
26539+ }
26540+ Offset += sizeof(SK_U8);
26541+ break;
26542+#endif
26543+
26544 case OID_SKGE_LINK_CAP:
26545- if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26546+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26547 if (LogPortIndex == 0) {
26548- /* Get value for virtual port */
26549+ /* Get value for virtual port. */
26550 VirtualConf(pAC, IoC, Id, pBufPtr);
26551 }
26552 else {
26553- /* Get value for physical ports */
26554+ /* Get value for physical port. */
26555 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26556 pAC, LogPortIndex);
26557
26558 *pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkCap;
26559 }
26560 }
26561- else { /* DualNetMode */
26562+ else { /* DualNet mode. */
26563
26564 *pBufPtr = pAC->GIni.GP[NetIndex].PLinkCap;
26565 }
26566- Offset += sizeof(char);
26567+ Offset ++;
26568 break;
26569
26570 case OID_SKGE_LINK_MODE:
26571- if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26572+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26573 if (LogPortIndex == 0) {
26574- /* Get value for virtual port */
26575+ /* Get value for virtual port. */
26576 VirtualConf(pAC, IoC, Id, pBufPtr);
26577 }
26578 else {
26579- /* Get value for physical ports */
26580+ /* Get value for physical port. */
26581 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26582 pAC, LogPortIndex);
26583
26584 *pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkModeConf;
26585 }
26586 }
26587- else { /* DualNetMode */
26588+ else { /* DualNet mode. */
26589
26590 *pBufPtr = pAC->GIni.GP[NetIndex].PLinkModeConf;
26591 }
26592- Offset += sizeof(char);
26593+ Offset ++;
26594 break;
26595
26596 case OID_SKGE_LINK_MODE_STATUS:
26597- if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26598+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26599 if (LogPortIndex == 0) {
26600- /* Get value for virtual port */
26601+ /* Get value for virtual port. */
26602 VirtualConf(pAC, IoC, Id, pBufPtr);
26603 }
26604 else {
26605- /* Get value for physical port */
26606+ /* Get value for physical port. */
26607 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26608 pAC, LogPortIndex);
26609
26610@@ -5190,147 +5050,147 @@
26611 CalculateLinkModeStatus(pAC, IoC, PhysPortIndex);
26612 }
26613 }
26614- else { /* DualNetMode */
26615+ else { /* DualNet mode. */
26616
26617 *pBufPtr = CalculateLinkModeStatus(pAC, IoC, NetIndex);
26618 }
26619- Offset += sizeof(char);
26620+ Offset ++;
26621 break;
26622
26623 case OID_SKGE_LINK_STATUS:
26624- if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26625+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26626 if (LogPortIndex == 0) {
26627- /* Get value for virtual port */
26628+ /* Get value for virtual port. */
26629 VirtualConf(pAC, IoC, Id, pBufPtr);
26630 }
26631 else {
26632- /* Get value for physical ports */
26633+ /* Get value for physical port. */
26634 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26635 pAC, LogPortIndex);
26636
26637 *pBufPtr = CalculateLinkStatus(pAC, IoC, PhysPortIndex);
26638 }
26639 }
26640- else { /* DualNetMode */
26641+ else { /* DualNet mode. */
26642
26643 *pBufPtr = CalculateLinkStatus(pAC, IoC, NetIndex);
26644 }
26645- Offset += sizeof(char);
26646+ Offset ++;
26647 break;
26648
26649 case OID_SKGE_FLOWCTRL_CAP:
26650- if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26651+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26652 if (LogPortIndex == 0) {
26653- /* Get value for virtual port */
26654+ /* Get value for virtual port. */
26655 VirtualConf(pAC, IoC, Id, pBufPtr);
26656 }
26657 else {
26658- /* Get value for physical ports */
26659+ /* Get value for physical port. */
26660 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26661 pAC, LogPortIndex);
26662
26663 *pBufPtr = pAC->GIni.GP[PhysPortIndex].PFlowCtrlCap;
26664 }
26665 }
26666- else { /* DualNetMode */
26667+ else { /* DualNet mode. */
26668
26669 *pBufPtr = pAC->GIni.GP[NetIndex].PFlowCtrlCap;
26670 }
26671- Offset += sizeof(char);
26672+ Offset ++;
26673 break;
26674
26675 case OID_SKGE_FLOWCTRL_MODE:
26676- if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26677+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26678 if (LogPortIndex == 0) {
26679- /* Get value for virtual port */
26680+ /* Get value for virtual port. */
26681 VirtualConf(pAC, IoC, Id, pBufPtr);
26682 }
26683 else {
26684- /* Get value for physical port */
26685+ /* Get value for physical port. */
26686 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26687 pAC, LogPortIndex);
26688
26689 *pBufPtr = pAC->GIni.GP[PhysPortIndex].PFlowCtrlMode;
26690 }
26691 }
26692- else { /* DualNetMode */
26693+ else { /* DualNet mode. */
26694
26695 *pBufPtr = pAC->GIni.GP[NetIndex].PFlowCtrlMode;
26696 }
26697- Offset += sizeof(char);
26698+ Offset ++;
26699 break;
26700
26701 case OID_SKGE_FLOWCTRL_STATUS:
26702- if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26703+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26704 if (LogPortIndex == 0) {
26705- /* Get value for virtual port */
26706+ /* Get value for virtual port. */
26707 VirtualConf(pAC, IoC, Id, pBufPtr);
26708 }
26709 else {
26710- /* Get value for physical port */
26711+ /* Get value for physical port. */
26712 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26713 pAC, LogPortIndex);
26714
26715 *pBufPtr = pAC->GIni.GP[PhysPortIndex].PFlowCtrlStatus;
26716 }
26717 }
26718- else { /* DualNetMode */
26719+ else { /* DualNet mode. */
26720
26721 *pBufPtr = pAC->GIni.GP[NetIndex].PFlowCtrlStatus;
26722 }
26723- Offset += sizeof(char);
26724+ Offset ++;
26725 break;
26726
26727 case OID_SKGE_PHY_OPERATION_CAP:
26728- if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26729+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet Mode. */
26730 if (LogPortIndex == 0) {
26731- /* Get value for virtual port */
26732+ /* Get value for virtual port. */
26733 VirtualConf(pAC, IoC, Id, pBufPtr);
26734 }
26735 else {
26736- /* Get value for physical ports */
26737+ /* Get value for physical port. */
26738 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26739 pAC, LogPortIndex);
26740
26741 *pBufPtr = pAC->GIni.GP[PhysPortIndex].PMSCap;
26742 }
26743 }
26744- else { /* DualNetMode */
26745+ else { /* DualNet mode. */
26746
26747 *pBufPtr = pAC->GIni.GP[NetIndex].PMSCap;
26748 }
26749- Offset += sizeof(char);
26750+ Offset ++;
26751 break;
26752
26753 case OID_SKGE_PHY_OPERATION_MODE:
26754- if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26755+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26756 if (LogPortIndex == 0) {
26757- /* Get value for virtual port */
26758+ /* Get value for virtual port. */
26759 VirtualConf(pAC, IoC, Id, pBufPtr);
26760 }
26761 else {
26762- /* Get value for physical port */
26763+ /* Get value for physical port. */
26764 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26765 pAC, LogPortIndex);
26766
26767 *pBufPtr = pAC->GIni.GP[PhysPortIndex].PMSMode;
26768 }
26769 }
26770- else { /* DualNetMode */
26771+ else { /* DualNet mode. */
26772
26773 *pBufPtr = pAC->GIni.GP[NetIndex].PMSMode;
26774 }
26775- Offset += sizeof(char);
26776+ Offset ++;
26777 break;
26778
26779 case OID_SKGE_PHY_OPERATION_STATUS:
26780- if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26781+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26782 if (LogPortIndex == 0) {
26783- /* Get value for virtual port */
26784+ /* Get value for virtual port. */
26785 VirtualConf(pAC, IoC, Id, pBufPtr);
26786 }
26787 else {
26788- /* Get value for physical port */
26789+ /* Get value for physical port. */
26790 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26791 pAC, LogPortIndex);
26792
26793@@ -5341,70 +5201,70 @@
26794
26795 *pBufPtr = pAC->GIni.GP[NetIndex].PMSStatus;
26796 }
26797- Offset += sizeof(char);
26798+ Offset ++;
26799 break;
26800
26801 case OID_SKGE_SPEED_CAP:
26802- if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26803+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26804 if (LogPortIndex == 0) {
26805- /* Get value for virtual port */
26806+ /* Get value for virtual port. */
26807 VirtualConf(pAC, IoC, Id, pBufPtr);
26808 }
26809 else {
26810- /* Get value for physical ports */
26811+ /* Get value for physical port. */
26812 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26813 pAC, LogPortIndex);
26814
26815 *pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkSpeedCap;
26816 }
26817 }
26818- else { /* DualNetMode */
26819+ else { /* DualNet mode. */
26820
26821 *pBufPtr = pAC->GIni.GP[NetIndex].PLinkSpeedCap;
26822 }
26823- Offset += sizeof(char);
26824+ Offset ++;
26825 break;
26826
26827 case OID_SKGE_SPEED_MODE:
26828- if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26829+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26830 if (LogPortIndex == 0) {
26831- /* Get value for virtual port */
26832+ /* Get value for virtual port. */
26833 VirtualConf(pAC, IoC, Id, pBufPtr);
26834 }
26835 else {
26836- /* Get value for physical port */
26837+ /* Get value for physical port. */
26838 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26839 pAC, LogPortIndex);
26840
26841 *pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkSpeed;
26842 }
26843 }
26844- else { /* DualNetMode */
26845+ else { /* DualNet mode. */
26846
26847 *pBufPtr = pAC->GIni.GP[NetIndex].PLinkSpeed;
26848 }
26849- Offset += sizeof(char);
26850+ Offset ++;
26851 break;
26852
26853 case OID_SKGE_SPEED_STATUS:
26854- if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
26855+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26856 if (LogPortIndex == 0) {
26857- /* Get value for virtual port */
26858+ /* Get value for virtual port. */
26859 VirtualConf(pAC, IoC, Id, pBufPtr);
26860 }
26861 else {
26862- /* Get value for physical port */
26863+ /* Get value for physical port. */
26864 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
26865 pAC, LogPortIndex);
26866
26867 *pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkSpeedUsed;
26868 }
26869 }
26870- else { /* DualNetMode */
26871+ else { /* DualNet mode. */
26872
26873 *pBufPtr = pAC->GIni.GP[NetIndex].PLinkSpeedUsed;
26874 }
26875- Offset += sizeof(char);
26876+ Offset ++;
26877 break;
26878
26879 case OID_SKGE_MTU:
26880@@ -5449,38 +5309,41 @@
26881 }
26882 break;
26883
26884- case OID_SKGE_MTU:
26885- if (*pLen < sizeof(SK_U32)) {
26886+#ifdef SK_PHY_LP_MODE
26887+ case OID_SKGE_PHY_LP_MODE:
26888+ if (*pLen < Limit - LogPortIndex) {
26889
26890- *pLen = sizeof(SK_U32);
26891+ *pLen = Limit - LogPortIndex;
26892 return (SK_PNMI_ERR_TOO_SHORT);
26893 }
26894- if (*pLen != sizeof(SK_U32)) {
26895+ break;
26896+#endif /* SK_PHY_LP_MODE */
26897
26898- *pLen = 0;
26899- return (SK_PNMI_ERR_BAD_VALUE);
26900+ case OID_SKGE_MTU:
26901+ if (*pLen < (Limit - LogPortIndex) * sizeof(SK_U32)) {
26902+
26903+ *pLen = (Limit - LogPortIndex) * sizeof(SK_U32);
26904+ return (SK_PNMI_ERR_TOO_SHORT);
26905 }
26906 break;
26907-
26908+
26909 default:
26910 *pLen = 0;
26911 return (SK_PNMI_ERR_READ_ONLY);
26912 }
26913
26914- /*
26915- * Perform preset or set
26916- */
26917+ /* Perform PRESET or SET. */
26918 Offset = 0;
26919 for (; LogPortIndex < Limit; LogPortIndex ++) {
26920
26921+ Val8 = *(pBuf + Offset);
26922+
26923 switch (Id) {
26924
26925 case OID_SKGE_LINK_MODE:
26926- /* Check the value range */
26927- Val8 = *(pBuf + Offset);
26928+ /* Check the value range. */
26929 if (Val8 == 0) {
26930-
26931- Offset += sizeof(char);
26932+ Offset++;
26933 break;
26934 }
26935 if (Val8 < SK_LMODE_HALF ||
26936@@ -5491,51 +5354,68 @@
26937 return (SK_PNMI_ERR_BAD_VALUE);
26938 }
26939
26940- /* The preset ends here */
26941+ /* The PRESET ends here. */
26942 if (Action == SK_PNMI_PRESET) {
26943
26944 return (SK_PNMI_ERR_OK);
26945 }
26946
26947- if (LogPortIndex == 0) {
26948-
26949- /*
26950- * The virtual port consists of all currently
26951- * active ports. Find them and send an event
26952- * with the new link mode to SIRQ.
26953- */
26954- for (PhysPortIndex = 0;
26955- PhysPortIndex < PhysPortMax;
26956- PhysPortIndex ++) {
26957-
26958- if (!pAC->Pnmi.Port[PhysPortIndex].
26959- ActiveFlag) {
26960-
26961- continue;
26962- }
26963+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
26964+ if (LogPortIndex == 0) {
26965+ /*
26966+ * The virtual port consists of all currently
26967+ * active ports. Find them and send an event
26968+ * with the new link mode to SIRQ.
26969+ */
26970+ for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;
26971+ PhysPortIndex ++) {
26972
26973- EventParam.Para32[0] = PhysPortIndex;
26974+ if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
26975+ continue;
26976+ }
26977+
26978+ EventParam.Para32[0] = PhysPortIndex;
26979+ EventParam.Para32[1] = (SK_U32)Val8;
26980+ if (SkGeSirqEvent(pAC, IoC,
26981+ SK_HWEV_SET_LMODE,
26982+ EventParam) > 0) {
26983+
26984+ SK_ERR_LOG(pAC, SK_ERRCL_SW,
26985+ SK_PNMI_ERR043,
26986+ SK_PNMI_ERR043MSG);
26987+
26988+ *pLen = 0;
26989+ return (SK_PNMI_ERR_GENERAL);
26990+ }
26991+ } /* for */
26992+ }
26993+ else {
26994+ /*
26995+ * Send an event with the new link mode to
26996+ * the SIRQ module.
26997+ */
26998+ EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
26999+ pAC, LogPortIndex);
27000 EventParam.Para32[1] = (SK_U32)Val8;
27001- if (SkGeSirqEvent(pAC, IoC,
27002- SK_HWEV_SET_LMODE,
27003+ if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_LMODE,
27004 EventParam) > 0) {
27005-
27006+
27007 SK_ERR_LOG(pAC, SK_ERRCL_SW,
27008 SK_PNMI_ERR043,
27009 SK_PNMI_ERR043MSG);
27010-
27011+
27012 *pLen = 0;
27013 return (SK_PNMI_ERR_GENERAL);
27014 }
27015 }
27016 }
27017- else {
27018+ else { /* DualNet mode. */
27019+
27020 /*
27021 * Send an event with the new link mode to
27022 * the SIRQ module.
27023 */
27024- EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
27025- pAC, LogPortIndex);
27026+ EventParam.Para32[0] = NetIndex;
27027 EventParam.Para32[1] = (SK_U32)Val8;
27028 if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_LMODE,
27029 EventParam) > 0) {
27030@@ -5548,15 +5428,13 @@
27031 return (SK_PNMI_ERR_GENERAL);
27032 }
27033 }
27034- Offset += sizeof(char);
27035+ Offset++;
27036 break;
27037
27038 case OID_SKGE_FLOWCTRL_MODE:
27039- /* Check the value range */
27040- Val8 = *(pBuf + Offset);
27041+ /* Check the value range. */
27042 if (Val8 == 0) {
27043-
27044- Offset += sizeof(char);
27045+ Offset++;
27046 break;
27047 }
27048 if (Val8 < SK_FLOW_MODE_NONE ||
27049@@ -5567,30 +5445,48 @@
27050 return (SK_PNMI_ERR_BAD_VALUE);
27051 }
27052
27053- /* The preset ends here */
27054+ /* The PRESET ends here. */
27055 if (Action == SK_PNMI_PRESET) {
27056
27057 return (SK_PNMI_ERR_OK);
27058 }
27059
27060- if (LogPortIndex == 0) {
27061+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
27062+ if (LogPortIndex == 0) {
27063+ /*
27064+ * The virtual port consists of all currently
27065+ * active ports. Find them and send an event
27066+ * with the new flow control mode to SIRQ.
27067+ */
27068+ for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;
27069+ PhysPortIndex ++) {
27070
27071- /*
27072- * The virtual port consists of all currently
27073- * active ports. Find them and send an event
27074- * with the new flow control mode to SIRQ.
27075- */
27076- for (PhysPortIndex = 0;
27077- PhysPortIndex < PhysPortMax;
27078- PhysPortIndex ++) {
27079+ if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
27080+ continue;
27081+ }
27082
27083- if (!pAC->Pnmi.Port[PhysPortIndex].
27084- ActiveFlag) {
27085+ EventParam.Para32[0] = PhysPortIndex;
27086+ EventParam.Para32[1] = (SK_U32)Val8;
27087+ if (SkGeSirqEvent(pAC, IoC,
27088+ SK_HWEV_SET_FLOWMODE,
27089+ EventParam) > 0) {
27090+
27091+ SK_ERR_LOG(pAC, SK_ERRCL_SW,
27092+ SK_PNMI_ERR044,
27093+ SK_PNMI_ERR044MSG);
27094
27095- continue;
27096+ *pLen = 0;
27097+ return (SK_PNMI_ERR_GENERAL);
27098+ }
27099 }
27100-
27101- EventParam.Para32[0] = PhysPortIndex;
27102+ }
27103+ else {
27104+ /*
27105+ * Send an event with the new flow control
27106+ * mode to the SIRQ module.
27107+ */
27108+ EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
27109+ pAC, LogPortIndex);
27110 EventParam.Para32[1] = (SK_U32)Val8;
27111 if (SkGeSirqEvent(pAC, IoC,
27112 SK_HWEV_SET_FLOWMODE,
27113@@ -5605,17 +5501,16 @@
27114 }
27115 }
27116 }
27117- else {
27118+ else { /* DualNet mode. */
27119+
27120 /*
27121- * Send an event with the new flow control
27122- * mode to the SIRQ module.
27123+ * Send an event with the new link mode to
27124+ * the SIRQ module.
27125 */
27126- EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
27127- pAC, LogPortIndex);
27128+ EventParam.Para32[0] = NetIndex;
27129 EventParam.Para32[1] = (SK_U32)Val8;
27130- if (SkGeSirqEvent(pAC, IoC,
27131- SK_HWEV_SET_FLOWMODE, EventParam)
27132- > 0) {
27133+ if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_FLOWMODE,
27134+ EventParam) > 0) {
27135
27136 SK_ERR_LOG(pAC, SK_ERRCL_SW,
27137 SK_PNMI_ERR044,
27138@@ -5625,15 +5520,14 @@
27139 return (SK_PNMI_ERR_GENERAL);
27140 }
27141 }
27142- Offset += sizeof(char);
27143+ Offset++;
27144 break;
27145
27146 case OID_SKGE_PHY_OPERATION_MODE :
27147- /* Check the value range */
27148- Val8 = *(pBuf + Offset);
27149+ /* Check the value range. */
27150 if (Val8 == 0) {
27151- /* mode of this port remains unchanged */
27152- Offset += sizeof(char);
27153+ /* Mode of this port remains unchanged. */
27154+ Offset++;
27155 break;
27156 }
27157 if (Val8 < SK_MS_MODE_AUTO ||
27158@@ -5644,34 +5538,51 @@
27159 return (SK_PNMI_ERR_BAD_VALUE);
27160 }
27161
27162- /* The preset ends here */
27163+ /* The PRESET ends here. */
27164 if (Action == SK_PNMI_PRESET) {
27165
27166 return (SK_PNMI_ERR_OK);
27167 }
27168
27169- if (LogPortIndex == 0) {
27170+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
27171+ if (LogPortIndex == 0) {
27172+ /*
27173+ * The virtual port consists of all currently
27174+ * active ports. Find them and send an event
27175+ * with new master/slave (role) mode to SIRQ.
27176+ */
27177+ for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;
27178+ PhysPortIndex ++) {
27179
27180- /*
27181- * The virtual port consists of all currently
27182- * active ports. Find them and send an event
27183- * with new master/slave (role) mode to SIRQ.
27184- */
27185- for (PhysPortIndex = 0;
27186- PhysPortIndex < PhysPortMax;
27187- PhysPortIndex ++) {
27188+ if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
27189+ continue;
27190+ }
27191
27192- if (!pAC->Pnmi.Port[PhysPortIndex].
27193- ActiveFlag) {
27194+ EventParam.Para32[0] = PhysPortIndex;
27195+ EventParam.Para32[1] = (SK_U32)Val8;
27196+ if (SkGeSirqEvent(pAC, IoC,
27197+ SK_HWEV_SET_ROLE,
27198+ EventParam) > 0) {
27199+
27200+ SK_ERR_LOG(pAC, SK_ERRCL_SW,
27201+ SK_PNMI_ERR042,
27202+ SK_PNMI_ERR042MSG);
27203
27204- continue;
27205+ *pLen = 0;
27206+ return (SK_PNMI_ERR_GENERAL);
27207+ }
27208 }
27209-
27210- EventParam.Para32[0] = PhysPortIndex;
27211+ }
27212+ else {
27213+ /*
27214+ * Send an event with the new master/slave
27215+ * (role) mode to the SIRQ module.
27216+ */
27217+ EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
27218+ pAC, LogPortIndex);
27219 EventParam.Para32[1] = (SK_U32)Val8;
27220 if (SkGeSirqEvent(pAC, IoC,
27221- SK_HWEV_SET_ROLE,
27222- EventParam) > 0) {
27223+ SK_HWEV_SET_ROLE, EventParam) > 0) {
27224
27225 SK_ERR_LOG(pAC, SK_ERRCL_SW,
27226 SK_PNMI_ERR042,
27227@@ -5682,16 +5593,16 @@
27228 }
27229 }
27230 }
27231- else {
27232+ else { /* DualNet mode. */
27233+
27234 /*
27235- * Send an event with the new master/slave
27236- * (role) mode to the SIRQ module.
27237+ * Send an event with the new link mode to
27238+ * the SIRQ module.
27239 */
27240- EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
27241- pAC, LogPortIndex);
27242+ EventParam.Para32[0] = NetIndex;
27243 EventParam.Para32[1] = (SK_U32)Val8;
27244- if (SkGeSirqEvent(pAC, IoC,
27245- SK_HWEV_SET_ROLE, EventParam) > 0) {
27246+ if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_ROLE,
27247+ EventParam) > 0) {
27248
27249 SK_ERR_LOG(pAC, SK_ERRCL_SW,
27250 SK_PNMI_ERR042,
27251@@ -5701,16 +5612,13 @@
27252 return (SK_PNMI_ERR_GENERAL);
27253 }
27254 }
27255-
27256- Offset += sizeof(char);
27257+ Offset++;
27258 break;
27259
27260 case OID_SKGE_SPEED_MODE:
27261- /* Check the value range */
27262- Val8 = *(pBuf + Offset);
27263+ /* Check the value range. */
27264 if (Val8 == 0) {
27265-
27266- Offset += sizeof(char);
27267+ Offset++;
27268 break;
27269 }
27270 if (Val8 < (SK_LSPEED_AUTO) ||
27271@@ -5721,29 +5629,49 @@
27272 return (SK_PNMI_ERR_BAD_VALUE);
27273 }
27274
27275- /* The preset ends here */
27276+ /* The PRESET ends here. */
27277 if (Action == SK_PNMI_PRESET) {
27278
27279 return (SK_PNMI_ERR_OK);
27280 }
27281
27282- if (LogPortIndex == 0) {
27283+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
27284+ if (LogPortIndex == 0) {
27285
27286- /*
27287- * The virtual port consists of all currently
27288- * active ports. Find them and send an event
27289- * with the new flow control mode to SIRQ.
27290- */
27291- for (PhysPortIndex = 0;
27292- PhysPortIndex < PhysPortMax;
27293- PhysPortIndex ++) {
27294+ /*
27295+ * The virtual port consists of all currently
27296+ * active ports. Find them and send an event
27297+ * with the new flow control mode to SIRQ.
27298+ */
27299+ for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;
27300+ PhysPortIndex ++) {
27301
27302- if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
27303+ if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
27304+ continue;
27305+ }
27306
27307- continue;
27308- }
27309+ EventParam.Para32[0] = PhysPortIndex;
27310+ EventParam.Para32[1] = (SK_U32)Val8;
27311+ if (SkGeSirqEvent(pAC, IoC,
27312+ SK_HWEV_SET_SPEED,
27313+ EventParam) > 0) {
27314+
27315+ SK_ERR_LOG(pAC, SK_ERRCL_SW,
27316+ SK_PNMI_ERR045,
27317+ SK_PNMI_ERR045MSG);
27318
27319- EventParam.Para32[0] = PhysPortIndex;
27320+ *pLen = 0;
27321+ return (SK_PNMI_ERR_GENERAL);
27322+ }
27323+ }
27324+ }
27325+ else {
27326+ /*
27327+ * Send an event with the new flow control
27328+ * mode to the SIRQ module.
27329+ */
27330+ EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
27331+ pAC, LogPortIndex);
27332 EventParam.Para32[1] = (SK_U32)Val8;
27333 if (SkGeSirqEvent(pAC, IoC,
27334 SK_HWEV_SET_SPEED,
27335@@ -5758,16 +5686,15 @@
27336 }
27337 }
27338 }
27339- else {
27340+ else { /* DualNet mode. */
27341+
27342 /*
27343- * Send an event with the new flow control
27344- * mode to the SIRQ module.
27345+ * Send an event with the new link mode to
27346+ * the SIRQ module.
27347 */
27348- EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
27349- pAC, LogPortIndex);
27350+ EventParam.Para32[0] = NetIndex;
27351 EventParam.Para32[1] = (SK_U32)Val8;
27352- if (SkGeSirqEvent(pAC, IoC,
27353- SK_HWEV_SET_SPEED,
27354+ if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_SPEED,
27355 EventParam) > 0) {
27356
27357 SK_ERR_LOG(pAC, SK_ERRCL_SW,
27358@@ -5778,23 +5705,25 @@
27359 return (SK_PNMI_ERR_GENERAL);
27360 }
27361 }
27362- Offset += sizeof(char);
27363+ Offset++;
27364 break;
27365
27366- case OID_SKGE_MTU :
27367- /* Check the value range */
27368- Val32 = *(SK_U32*)(pBuf + Offset);
27369+ case OID_SKGE_MTU:
27370+ /* Check the value range. */
27371+ SK_PNMI_READ_U32((pBuf + Offset), Val32);
27372+
27373 if (Val32 == 0) {
27374- /* mtu of this port remains unchanged */
27375+ /* MTU of this port remains unchanged. */
27376 Offset += sizeof(SK_U32);
27377 break;
27378 }
27379+
27380 if (SK_DRIVER_PRESET_MTU(pAC, IoC, NetIndex, Val32) != 0) {
27381 *pLen = 0;
27382 return (SK_PNMI_ERR_BAD_VALUE);
27383 }
27384
27385- /* The preset ends here */
27386+ /* The PRESET ends here. */
27387 if (Action == SK_PNMI_PRESET) {
27388 return (SK_PNMI_ERR_OK);
27389 }
27390@@ -5805,7 +5734,70 @@
27391
27392 Offset += sizeof(SK_U32);
27393 break;
27394-
27395+
27396+#ifdef SK_PHY_LP_MODE
27397+ case OID_SKGE_PHY_LP_MODE:
27398+ /* The PRESET ends here. */
27399+ if (Action == SK_PNMI_PRESET) {
27400+
27401+ return (SK_PNMI_ERR_OK);
27402+ }
27403+
27404+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */
27405+ if (LogPortIndex == 0) {
27406+ Offset = 0;
27407+ continue;
27408+ }
27409+ }
27410+ /* Set value for physical port. */
27411+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);
27412+ CurrentPhyPowerState = pAC->GIni.GP[PhysPortIndex].PPhyPowerState;
27413+
27414+ switch (Val8) {
27415+ case PHY_PM_OPERATIONAL_MODE:
27416+ /* If LowPowerMode is active, we can leave it. */
27417+ if (CurrentPhyPowerState) {
27418+
27419+ Val32 = SkGmLeaveLowPowerMode(pAC, IoC, PhysPortIndex);
27420+
27421+ if ((CurrentPhyPowerState == PHY_PM_DEEP_SLEEP) ||
27422+ (CurrentPhyPowerState == PHY_PM_IEEE_POWER_DOWN)) {
27423+
27424+ SkDrvInitAdapter(pAC);
27425+ }
27426+ break;
27427+ }
27428+ else {
27429+ *pLen = 0;
27430+ return (SK_PNMI_ERR_GENERAL);
27431+ }
27432+ case PHY_PM_DEEP_SLEEP:
27433+ case PHY_PM_IEEE_POWER_DOWN:
27434+ /* If no LowPowerMode is active, we can enter it. */
27435+ if (!CurrentPhyPowerState) {
27436+ SkDrvDeInitAdapter(pAC);
27437+ }
27438+
27439+ case PHY_PM_ENERGY_DETECT:
27440+ case PHY_PM_ENERGY_DETECT_PLUS:
27441+ /* If no LowPowerMode is active, we can enter it. */
27442+ if (!CurrentPhyPowerState) {
27443+
27444+ Val32 = SkGmEnterLowPowerMode(pAC, IoC, PhysPortIndex, *pBuf);
27445+ break;
27446+ }
27447+ else {
27448+ *pLen = 0;
27449+ return (SK_PNMI_ERR_GENERAL);
27450+ }
27451+ default:
27452+ *pLen = 0;
27453+ return (SK_PNMI_ERR_BAD_VALUE);
27454+ }
27455+ Offset++;
27456+ break;
27457+#endif /* SK_PHY_LP_MODE */
27458+
27459 default:
27460 SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR,
27461 ("MacPrivateConf: Unknown OID should be handled before set"));
27462@@ -5854,14 +5846,11 @@
27463 unsigned int Limit;
27464 unsigned int Offset;
27465 unsigned int Entries;
27466-
27467
27468- /*
27469- * Calculate instance if wished.
27470- */
27471- /* XXX Not yet implemented. Return always an empty table. */
27472+ /* Not implemented yet. Return always an empty table. */
27473 Entries = 0;
27474
27475+ /* Calculate instance if wished. */
27476 if ((Instance != (SK_U32)(-1))) {
27477
27478 if ((Instance < 1) || (Instance > Entries)) {
27479@@ -5878,12 +5867,10 @@
27480 Limit = Entries;
27481 }
27482
27483- /*
27484- * Get/Set value
27485- */
27486+ /* GET/SET value. */
27487 if (Action == SK_PNMI_GET) {
27488
27489- for (Offset=0; Index < Limit; Index ++) {
27490+ for (Offset = 0; Index < Limit; Index ++) {
27491
27492 switch (Id) {
27493
27494@@ -5905,32 +5892,29 @@
27495 *pLen = Offset;
27496 }
27497 else {
27498- /* Only MONITOR_ADMIN can be set */
27499+ /* Only MONITOR_ADMIN can be set. */
27500 if (Id != OID_SKGE_RLMT_MONITOR_ADMIN) {
27501
27502 *pLen = 0;
27503 return (SK_PNMI_ERR_READ_ONLY);
27504 }
27505
27506- /* Check if the length is plausible */
27507+ /* Check if the length is plausible. */
27508 if (*pLen < (Limit - Index)) {
27509
27510 return (SK_PNMI_ERR_TOO_SHORT);
27511 }
27512- /* Okay, we have a wide value range */
27513+ /* Okay, we have a wide value range. */
27514 if (*pLen != (Limit - Index)) {
27515
27516 *pLen = 0;
27517 return (SK_PNMI_ERR_BAD_VALUE);
27518 }
27519-/*
27520- for (Offset=0; Index < Limit; Index ++) {
27521- }
27522-*/
27523-/*
27524- * XXX Not yet implemented. Return always BAD_VALUE, because the table
27525- * is empty.
27526- */
27527+
27528+ /*
27529+ * Not yet implemented. Return always BAD_VALUE,
27530+ * because the table is empty.
27531+ */
27532 *pLen = 0;
27533 return (SK_PNMI_ERR_BAD_VALUE);
27534 }
27535@@ -5971,14 +5955,12 @@
27536 PortActiveFlag = SK_FALSE;
27537 PhysPortMax = pAC->GIni.GIMacsFound;
27538
27539- for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;
27540- PhysPortIndex ++) {
27541+ for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax; PhysPortIndex ++) {
27542
27543 pPrt = &pAC->GIni.GP[PhysPortIndex];
27544
27545- /* Check if the physical port is active */
27546+ /* Check if the physical port is active. */
27547 if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
27548-
27549 continue;
27550 }
27551
27552@@ -5987,12 +5969,13 @@
27553 switch (Id) {
27554
27555 case OID_SKGE_PHY_TYPE:
27556- /* Check if it is the first active port */
27557+ /* Check if it is the first active port. */
27558 if (*pBuf == 0) {
27559 Val32 = pPrt->PhyType;
27560 SK_PNMI_STORE_U32(pBuf, Val32);
27561 continue;
27562 }
27563+ break;
27564
27565 case OID_SKGE_LINK_CAP:
27566
27567@@ -6006,7 +5989,7 @@
27568 break;
27569
27570 case OID_SKGE_LINK_MODE:
27571- /* Check if it is the first active port */
27572+ /* Check if it is the first active port. */
27573 if (*pBuf == 0) {
27574
27575 *pBuf = pPrt->PLinkModeConf;
27576@@ -6014,9 +5997,8 @@
27577 }
27578
27579 /*
27580- * If we find an active port with a different link
27581- * mode than the first one we return a value that
27582- * indicates that the link mode is indeterminated.
27583+ * If we find an active port with a different link mode
27584+ * than the first one we return indeterminated.
27585 */
27586 if (*pBuf != pPrt->PLinkModeConf) {
27587
27588@@ -6025,10 +6007,10 @@
27589 break;
27590
27591 case OID_SKGE_LINK_MODE_STATUS:
27592- /* Get the link mode of the physical port */
27593+ /* Get the link mode of the physical port. */
27594 Val8 = CalculateLinkModeStatus(pAC, IoC, PhysPortIndex);
27595
27596- /* Check if it is the first active port */
27597+ /* Check if it is the first active port. */
27598 if (*pBuf == 0) {
27599
27600 *pBuf = Val8;
27601@@ -6036,10 +6018,8 @@
27602 }
27603
27604 /*
27605- * If we find an active port with a different link
27606- * mode status than the first one we return a value
27607- * that indicates that the link mode status is
27608- * indeterminated.
27609+ * If we find an active port with a different link mode status
27610+ * than the first one we return indeterminated.
27611 */
27612 if (*pBuf != Val8) {
27613
27614@@ -6048,10 +6028,10 @@
27615 break;
27616
27617 case OID_SKGE_LINK_STATUS:
27618- /* Get the link status of the physical port */
27619+ /* Get the link status of the physical port. */
27620 Val8 = CalculateLinkStatus(pAC, IoC, PhysPortIndex);
27621
27622- /* Check if it is the first active port */
27623+ /* Check if it is the first active port. */
27624 if (*pBuf == 0) {
27625
27626 *pBuf = Val8;
27627@@ -6059,10 +6039,8 @@
27628 }
27629
27630 /*
27631- * If we find an active port with a different link
27632- * status than the first one, we return a value
27633- * that indicates that the link status is
27634- * indeterminated.
27635+ * If we find an active port with a different link status
27636+ * than the first one we return indeterminated.
27637 */
27638 if (*pBuf != Val8) {
27639
27640@@ -6071,7 +6049,7 @@
27641 break;
27642
27643 case OID_SKGE_FLOWCTRL_CAP:
27644- /* Check if it is the first active port */
27645+ /* Check if it is the first active port. */
27646 if (*pBuf == 0) {
27647
27648 *pBuf = pPrt->PFlowCtrlCap;
27649@@ -6086,7 +6064,7 @@
27650 break;
27651
27652 case OID_SKGE_FLOWCTRL_MODE:
27653- /* Check if it is the first active port */
27654+ /* Check if it is the first active port. */
27655 if (*pBuf == 0) {
27656
27657 *pBuf = pPrt->PFlowCtrlMode;
27658@@ -6094,9 +6072,8 @@
27659 }
27660
27661 /*
27662- * If we find an active port with a different flow
27663- * control mode than the first one, we return a value
27664- * that indicates that the mode is indeterminated.
27665+ * If we find an active port with a different flow-control mode
27666+ * than the first one we return indeterminated.
27667 */
27668 if (*pBuf != pPrt->PFlowCtrlMode) {
27669
27670@@ -6105,7 +6082,7 @@
27671 break;
27672
27673 case OID_SKGE_FLOWCTRL_STATUS:
27674- /* Check if it is the first active port */
27675+ /* Check if it is the first active port. */
27676 if (*pBuf == 0) {
27677
27678 *pBuf = pPrt->PFlowCtrlStatus;
27679@@ -6113,10 +6090,8 @@
27680 }
27681
27682 /*
27683- * If we find an active port with a different flow
27684- * control status than the first one, we return a
27685- * value that indicates that the status is
27686- * indeterminated.
27687+ * If we find an active port with a different flow-control status
27688+ * than the first one we return indeterminated.
27689 */
27690 if (*pBuf != pPrt->PFlowCtrlStatus) {
27691
27692@@ -6125,7 +6100,7 @@
27693 break;
27694
27695 case OID_SKGE_PHY_OPERATION_CAP:
27696- /* Check if it is the first active port */
27697+ /* Check if it is the first active port. */
27698 if (*pBuf == 0) {
27699
27700 *pBuf = pPrt->PMSCap;
27701@@ -6140,7 +6115,7 @@
27702 break;
27703
27704 case OID_SKGE_PHY_OPERATION_MODE:
27705- /* Check if it is the first active port */
27706+ /* Check if it is the first active port. */
27707 if (*pBuf == 0) {
27708
27709 *pBuf = pPrt->PMSMode;
27710@@ -6148,9 +6123,8 @@
27711 }
27712
27713 /*
27714- * If we find an active port with a different master/
27715- * slave mode than the first one, we return a value
27716- * that indicates that the mode is indeterminated.
27717+ * If we find an active port with a different master/slave mode
27718+ * than the first one we return indeterminated.
27719 */
27720 if (*pBuf != pPrt->PMSMode) {
27721
27722@@ -6159,7 +6133,7 @@
27723 break;
27724
27725 case OID_SKGE_PHY_OPERATION_STATUS:
27726- /* Check if it is the first active port */
27727+ /* Check if it is the first active port. */
27728 if (*pBuf == 0) {
27729
27730 *pBuf = pPrt->PMSStatus;
27731@@ -6167,10 +6141,8 @@
27732 }
27733
27734 /*
27735- * If we find an active port with a different master/
27736- * slave status than the first one, we return a
27737- * value that indicates that the status is
27738- * indeterminated.
27739+ * If we find an active port with a different master/slave status
27740+ * than the first one we return indeterminated.
27741 */
27742 if (*pBuf != pPrt->PMSStatus) {
27743
27744@@ -6179,7 +6151,7 @@
27745 break;
27746
27747 case OID_SKGE_SPEED_MODE:
27748- /* Check if it is the first active port */
27749+ /* Check if it is the first active port. */
27750 if (*pBuf == 0) {
27751
27752 *pBuf = pPrt->PLinkSpeed;
27753@@ -6187,9 +6159,8 @@
27754 }
27755
27756 /*
27757- * If we find an active port with a different flow
27758- * control mode than the first one, we return a value
27759- * that indicates that the mode is indeterminated.
27760+ * If we find an active port with a different link speed
27761+ * than the first one we return indeterminated.
27762 */
27763 if (*pBuf != pPrt->PLinkSpeed) {
27764
27765@@ -6198,7 +6169,7 @@
27766 break;
27767
27768 case OID_SKGE_SPEED_STATUS:
27769- /* Check if it is the first active port */
27770+ /* Check if it is the first active port. */
27771 if (*pBuf == 0) {
27772
27773 *pBuf = pPrt->PLinkSpeedUsed;
27774@@ -6206,10 +6177,8 @@
27775 }
27776
27777 /*
27778- * If we find an active port with a different flow
27779- * control status than the first one, we return a
27780- * value that indicates that the status is
27781- * indeterminated.
27782+ * If we find an active port with a different link speed used
27783+ * than the first one we return indeterminated.
27784 */
27785 if (*pBuf != pPrt->PLinkSpeedUsed) {
27786
27787@@ -6219,9 +6188,7 @@
27788 }
27789 }
27790
27791- /*
27792- * If no port is active return an indeterminated answer
27793- */
27794+ /* If no port is active return an indeterminated answer. */
27795 if (!PortActiveFlag) {
27796
27797 switch (Id) {
27798@@ -6324,7 +6291,7 @@
27799 *
27800 * Description:
27801 * The COMMON module only tells us if the mode is half or full duplex.
27802- * But in the decade of auto sensing it is useful for the user to
27803+ * But in the decade of auto sensing it is usefull for the user to
27804 * know if the mode was negotiated or forced. Therefore we have a
27805 * look to the mode, which was last used by the negotiation process.
27806 *
27807@@ -6338,16 +6305,15 @@
27808 {
27809 SK_U8 Result;
27810
27811- /* Get the current mode, which can be full or half duplex */
27812+ /* Get the current mode, which can be full or half duplex. */
27813 Result = pAC->GIni.GP[PhysPortIndex].PLinkModeStatus;
27814
27815- /* Check if no valid mode could be found (link is down) */
27816+ /* Check if no valid mode could be found (link is down). */
27817 if (Result < SK_LMODE_STAT_HALF) {
27818
27819 Result = SK_LMODE_STAT_UNKNOWN;
27820 }
27821 else if (pAC->GIni.GP[PhysPortIndex].PLinkMode >= SK_LMODE_AUTOHALF) {
27822-
27823 /*
27824 * Auto-negotiation was used to bring up the link. Change
27825 * the already found duplex status that it indicates
27826@@ -6392,22 +6358,22 @@
27827 int Index;
27828 int Ret;
27829
27830-
27831 SK_MEMSET(pKeyArr, 0, KeyArrLen);
27832
27833- /*
27834- * Get VPD key list
27835- */
27836- Ret = VpdKeys(pAC, IoC, (char *)&BufKeys, (int *)&BufKeysLen,
27837+ /* Get VPD key list. */
27838+ Ret = VpdKeys(pAC, IoC, BufKeys, (int *)&BufKeysLen,
27839 (int *)pKeyNo);
27840+
27841 if (Ret > 0) {
27842
27843- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR014,
27844- SK_PNMI_ERR014MSG);
27845+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
27846+ (SK_PNMI_ERR014MSG));
27847
27848+ /* Please read comment in Vpd(). */
27849+ pAC->Pnmi.VpdKeyReadError = SK_TRUE;
27850 return (SK_PNMI_ERR_GENERAL);
27851 }
27852- /* If no keys are available return now */
27853+ /* If no keys are available return now. */
27854 if (*pKeyNo == 0 || BufKeysLen == 0) {
27855
27856 return (SK_PNMI_ERR_OK);
27857@@ -6415,12 +6381,12 @@
27858 /*
27859 * If the key list is too long for us trunc it and give a
27860 * errorlog notification. This case should not happen because
27861- * the maximum number of keys is limited due to RAM limitations
27862+ * the maximum number of keys is limited due to RAM limitations.
27863 */
27864 if (*pKeyNo > SK_PNMI_VPD_ENTRIES) {
27865
27866- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR015,
27867- SK_PNMI_ERR015MSG);
27868+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
27869+ (SK_PNMI_ERR015MSG));
27870
27871 *pKeyNo = SK_PNMI_VPD_ENTRIES;
27872 }
27873@@ -6433,14 +6399,14 @@
27874 Offset ++) {
27875
27876 if (BufKeys[Offset] != 0) {
27877-
27878 continue;
27879 }
27880
27881 if (Offset - StartOffset > SK_PNMI_VPD_KEY_SIZE) {
27882
27883- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR016,
27884- SK_PNMI_ERR016MSG);
27885+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
27886+ (SK_PNMI_ERR016MSG));
27887+
27888 return (SK_PNMI_ERR_GENERAL);
27889 }
27890
27891@@ -6451,7 +6417,7 @@
27892 StartOffset = Offset + 1;
27893 }
27894
27895- /* Last key not zero terminated? Get it anyway */
27896+ /* Last key not zero terminated? Get it anyway. */
27897 if (StartOffset < Offset) {
27898
27899 SK_STRNCPY(pKeyArr + Index * SK_PNMI_VPD_KEY_SIZE,
27900@@ -6480,19 +6446,18 @@
27901 {
27902 SK_EVPARA EventParam;
27903
27904-
27905 /* Was the module already updated during the current PNMI call? */
27906 if (pAC->Pnmi.SirqUpdatedFlag > 0) {
27907
27908 return (SK_PNMI_ERR_OK);
27909 }
27910
27911- /* Send an synchronuous update event to the module */
27912+ /* Send an synchronuous update event to the module. */
27913 SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
27914- if (SkGeSirqEvent(pAC, IoC, SK_HWEV_UPDATE_STAT, EventParam) > 0) {
27915+
27916+ if (SkGeSirqEvent(pAC, IoC, SK_HWEV_UPDATE_STAT, EventParam)) {
27917
27918- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR047,
27919- SK_PNMI_ERR047MSG);
27920+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR047, SK_PNMI_ERR047MSG);
27921
27922 return (SK_PNMI_ERR_GENERAL);
27923 }
27924@@ -6520,21 +6485,19 @@
27925 {
27926 SK_EVPARA EventParam;
27927
27928-
27929 /* Was the module already updated during the current PNMI call? */
27930 if (pAC->Pnmi.RlmtUpdatedFlag > 0) {
27931
27932 return (SK_PNMI_ERR_OK);
27933 }
27934
27935- /* Send an synchronuous update event to the module */
27936+ /* Send an synchronuous update event to the module. */
27937 SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
27938 EventParam.Para32[0] = NetIndex;
27939 EventParam.Para32[1] = (SK_U32)-1;
27940 if (SkRlmtEvent(pAC, IoC, SK_RLMT_STATS_UPDATE, EventParam) > 0) {
27941
27942- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR048,
27943- SK_PNMI_ERR048MSG);
27944+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR048, SK_PNMI_ERR048MSG);
27945
27946 return (SK_PNMI_ERR_GENERAL);
27947 }
27948@@ -6572,20 +6535,20 @@
27949 return (SK_PNMI_ERR_OK);
27950 }
27951
27952- /* Send an update command to all MACs specified */
27953+ /* Send an update command to all MACs specified. */
27954 for (MacIndex = FirstMac; MacIndex <= LastMac; MacIndex ++) {
27955
27956 /*
27957 * 2002-09-13 pweber: Freeze the current SW counters.
27958 * (That should be done as close as
27959 * possible to the update of the
27960- * HW counters)
27961+ * HW counters).
27962 */
27963 if (pAC->GIni.GIMacType == SK_MAC_XMAC) {
27964 pAC->Pnmi.BufPort[MacIndex] = pAC->Pnmi.Port[MacIndex];
27965 }
27966
27967- /* 2002-09-13 pweber: Update the HW counter */
27968+ /* 2002-09-13 pweber: Update the HW counter. */
27969 if (pAC->GIni.GIFunc.pFnMacUpdateStats(pAC, IoC, MacIndex) != 0) {
27970
27971 return (SK_PNMI_ERR_GENERAL);
27972@@ -6623,19 +6586,19 @@
27973 SK_U64 Val = 0;
27974
27975
27976- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* Dual net mode */
27977+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* DualNet mode. */
27978
27979 PhysPortIndex = NetIndex;
27980
27981 Val = GetPhysStatVal(pAC, IoC, PhysPortIndex, StatIndex);
27982 }
27983- else { /* Single Net mode */
27984+ else { /* SingleNet mode. */
27985
27986 if (LogPortIndex == 0) {
27987
27988 PhysPortMax = pAC->GIni.GIMacsFound;
27989
27990- /* Add counter of all active ports */
27991+ /* Add counter of all active ports. */
27992 for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;
27993 PhysPortIndex ++) {
27994
27995@@ -6645,11 +6608,11 @@
27996 }
27997 }
27998
27999- /* Correct value because of port switches */
28000+ /* Correct value because of port switches. */
28001 Val += pAC->Pnmi.VirtualCounterOffset[StatIndex];
28002 }
28003 else {
28004- /* Get counter value of physical port */
28005+ /* Get counter value of physical port. */
28006 PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);
28007
28008 Val = GetPhysStatVal(pAC, IoC, PhysPortIndex, StatIndex);
28009@@ -6695,7 +6658,7 @@
28010
28011 MacType = pAC->GIni.GIMacType;
28012
28013- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
28014+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */
28015 if (MacType == SK_MAC_XMAC) {
28016 pPnmiPrt = &pAC->Pnmi.BufPort[PhysPortIndex];
28017 }
28018@@ -6763,7 +6726,7 @@
28019 case SK_PNMI_HTX_BURST:
28020 case SK_PNMI_HTX_EXCESS_DEF:
28021 case SK_PNMI_HTX_CARRIER:
28022- /* Not supported by GMAC */
28023+ /* Not supported by GMAC. */
28024 if (MacType == SK_MAC_GMAC) {
28025 return (Val);
28026 }
28027@@ -6775,7 +6738,7 @@
28028 break;
28029
28030 case SK_PNMI_HTX_MACC:
28031- /* GMAC only supports PAUSE MAC control frames */
28032+ /* GMAC only supports PAUSE MAC control frames. */
28033 if (MacType == SK_MAC_GMAC) {
28034 HelpIndex = SK_PNMI_HTX_PMACC;
28035 }
28036@@ -6792,7 +6755,7 @@
28037
28038 case SK_PNMI_HTX_COL:
28039 case SK_PNMI_HRX_UNDERSIZE:
28040- /* Not supported by XMAC */
28041+ /* Not supported by XMAC. */
28042 if (MacType == SK_MAC_XMAC) {
28043 return (Val);
28044 }
28045@@ -6804,7 +6767,7 @@
28046 break;
28047
28048 case SK_PNMI_HTX_DEFFERAL:
28049- /* Not supported by GMAC */
28050+ /* Not supported by GMAC. */
28051 if (MacType == SK_MAC_GMAC) {
28052 return (Val);
28053 }
28054@@ -6822,7 +6785,7 @@
28055 HighVal = 0;
28056 }
28057 else {
28058- /* Otherwise get contents of hardware register */
28059+ /* Otherwise get contents of hardware register. */
28060 (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
28061 StatAddr[StatIndex][MacType].Reg,
28062 &LowVal);
28063@@ -6831,7 +6794,7 @@
28064 break;
28065
28066 case SK_PNMI_HRX_BADOCTET:
28067- /* Not supported by XMAC */
28068+ /* Not supported by XMAC. */
28069 if (MacType == SK_MAC_XMAC) {
28070 return (Val);
28071 }
28072@@ -6850,7 +6813,7 @@
28073 return (Val);
28074
28075 case SK_PNMI_HRX_LONGFRAMES:
28076- /* For XMAC the SW counter is managed by PNMI */
28077+ /* For XMAC the SW counter is managed by PNMI. */
28078 if (MacType == SK_MAC_XMAC) {
28079 return (pPnmiPrt->StatRxLongFrameCts);
28080 }
28081@@ -6870,7 +6833,7 @@
28082 Val = (((SK_U64)HighVal << 32) | (SK_U64)LowVal);
28083
28084 if (MacType == SK_MAC_GMAC) {
28085- /* For GMAC the SW counter is additionally managed by PNMI */
28086+ /* For GMAC the SW counter is additionally managed by PNMI. */
28087 Val += pPnmiPrt->StatRxFrameTooLongCts;
28088 }
28089 else {
28090@@ -6888,20 +6851,19 @@
28091 break;
28092
28093 case SK_PNMI_HRX_SHORTS:
28094- /* Not supported by GMAC */
28095+ /* Not supported by GMAC. */
28096 if (MacType == SK_MAC_GMAC) {
28097 /* GM_RXE_FRAG?? */
28098 return (Val);
28099 }
28100
28101 /*
28102- * XMAC counts short frame errors even if link down (#10620)
28103- *
28104- * If link-down the counter remains constant
28105+ * XMAC counts short frame errors even if link down (#10620).
28106+ * If the link is down, the counter remains constant.
28107 */
28108 if (pPrt->PLinkModeStatus != SK_LMODE_STAT_UNKNOWN) {
28109
28110- /* Otherwise get incremental difference */
28111+ /* Otherwise get incremental difference. */
28112 (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
28113 StatAddr[StatIndex][MacType].Reg,
28114 &LowVal);
28115@@ -6924,7 +6886,7 @@
28116 case SK_PNMI_HRX_IRLENGTH:
28117 case SK_PNMI_HRX_SYMBOL:
28118 case SK_PNMI_HRX_CEXT:
28119- /* Not supported by GMAC */
28120+ /* Not supported by GMAC. */
28121 if (MacType == SK_MAC_GMAC) {
28122 return (Val);
28123 }
28124@@ -6936,7 +6898,7 @@
28125 break;
28126
28127 case SK_PNMI_HRX_PMACC_ERR:
28128- /* For GMAC the SW counter is managed by PNMI */
28129+ /* For GMAC the SW counter is managed by PNMI. */
28130 if (MacType == SK_MAC_GMAC) {
28131 return (pPnmiPrt->StatRxPMaccErr);
28132 }
28133@@ -6947,13 +6909,13 @@
28134 HighVal = pPnmiPrt->CounterHigh[StatIndex];
28135 break;
28136
28137- /* SW counter managed by PNMI */
28138+ /* SW counter managed by PNMI. */
28139 case SK_PNMI_HTX_SYNC:
28140 LowVal = (SK_U32)pPnmiPrt->StatSyncCts;
28141 HighVal = (SK_U32)(pPnmiPrt->StatSyncCts >> 32);
28142 break;
28143
28144- /* SW counter managed by PNMI */
28145+ /* SW counter managed by PNMI. */
28146 case SK_PNMI_HTX_SYNC_OCTET:
28147 LowVal = (SK_U32)pPnmiPrt->StatSyncOctetsCts;
28148 HighVal = (SK_U32)(pPnmiPrt->StatSyncOctetsCts >> 32);
28149@@ -6961,17 +6923,19 @@
28150
28151 case SK_PNMI_HRX_FCS:
28152 /*
28153- * Broadcom filters FCS errors and counts it in
28154- * Receive Error Counter register
28155+ * Broadcom filters FCS errors and counts them in
28156+ * Receive Error Counter register.
28157 */
28158 if (pPrt->PhyType == SK_PHY_BCOM) {
28159- /* do not read while not initialized (PHY_READ hangs!)*/
28160+#ifdef GENESIS
28161+ /* Do not read while not initialized (PHY_READ hangs!). */
28162 if (pPrt->PState != SK_PRT_RESET) {
28163 SkXmPhyRead(pAC, IoC, PhysPortIndex, PHY_BCOM_RE_CTR, &Word);
28164
28165 LowVal = Word;
28166 }
28167 HighVal = pPnmiPrt->CounterHigh[StatIndex];
28168+#endif /* GENESIS */
28169 }
28170 else {
28171 (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
28172@@ -6991,7 +6955,7 @@
28173
28174 Val = (((SK_U64)HighVal << 32) | (SK_U64)LowVal);
28175
28176- /* Correct value because of possible XMAC reset. XMAC Errata #2 */
28177+ /* Correct value because of possible XMAC reset (XMAC Errata #2). */
28178 Val += pPnmiPrt->CounterOffset[StatIndex];
28179
28180 return (Val);
28181@@ -7016,22 +6980,21 @@
28182 unsigned int PhysPortIndex;
28183 SK_EVPARA EventParam;
28184
28185-
28186 SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
28187
28188- /* Notify sensor module */
28189+ /* Notify sensor module. */
28190 SkEventQueue(pAC, SKGE_I2C, SK_I2CEV_CLEAR, EventParam);
28191
28192- /* Notify RLMT module */
28193+ /* Notify RLMT module. */
28194 EventParam.Para32[0] = NetIndex;
28195 EventParam.Para32[1] = (SK_U32)-1;
28196 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STATS_CLEAR, EventParam);
28197 EventParam.Para32[1] = 0;
28198
28199- /* Notify SIRQ module */
28200+ /* Notify SIRQ module. */
28201 SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_CLEAR_STAT, EventParam);
28202
28203- /* Notify CSUM module */
28204+ /* Notify CSUM module. */
28205 #ifdef SK_USE_CSUM
28206 EventParam.Para32[0] = NetIndex;
28207 EventParam.Para32[1] = (SK_U32)-1;
28208@@ -7039,7 +7002,7 @@
28209 EventParam);
28210 #endif /* SK_USE_CSUM */
28211
28212- /* Clear XMAC statistic */
28213+ /* Clear XMAC statistics. */
28214 for (PhysPortIndex = 0; PhysPortIndex <
28215 (unsigned int)pAC->GIni.GIMacsFound; PhysPortIndex ++) {
28216
28217@@ -7066,13 +7029,13 @@
28218 PhysPortIndex].StatRxPMaccErr));
28219 }
28220
28221- /*
28222- * Clear local statistics
28223- */
28224+ /* Clear local statistics. */
28225 SK_MEMSET((char *)&pAC->Pnmi.VirtualCounterOffset, 0,
28226 sizeof(pAC->Pnmi.VirtualCounterOffset));
28227+
28228 pAC->Pnmi.RlmtChangeCts = 0;
28229 pAC->Pnmi.RlmtChangeTime = 0;
28230+
28231 SK_MEMSET((char *)&pAC->Pnmi.RlmtChangeEstimate.EstValue[0], 0,
28232 sizeof(pAC->Pnmi.RlmtChangeEstimate.EstValue));
28233 pAC->Pnmi.RlmtChangeEstimate.EstValueIndex = 0;
28234@@ -7109,23 +7072,21 @@
28235 SK_U32 TrapId, /* SNMP ID of the trap */
28236 unsigned int Size) /* Space needed for trap entry */
28237 {
28238- unsigned int BufPad = pAC->Pnmi.TrapBufPad;
28239- unsigned int BufFree = pAC->Pnmi.TrapBufFree;
28240- unsigned int Beg = pAC->Pnmi.TrapQueueBeg;
28241- unsigned int End = pAC->Pnmi.TrapQueueEnd;
28242+ unsigned int BufPad = pAC->Pnmi.TrapBufPad;
28243+ unsigned int BufFree = pAC->Pnmi.TrapBufFree;
28244+ unsigned int Beg = pAC->Pnmi.TrapQueueBeg;
28245+ unsigned int End = pAC->Pnmi.TrapQueueEnd;
28246 char *pBuf = &pAC->Pnmi.TrapBuf[0];
28247 int Wrap;
28248- unsigned int NeededSpace;
28249- unsigned int EntrySize;
28250+ unsigned int NeededSpace;
28251+ unsigned int EntrySize;
28252 SK_U32 Val32;
28253 SK_U64 Val64;
28254
28255-
28256- /* Last byte of entry will get a copy of the entry length */
28257+ /* Last byte of entry will get a copy of the entry length. */
28258 Size ++;
28259
28260- /*
28261- * Calculate needed buffer space */
28262+ /* Calculate needed buffer space. */
28263 if (Beg >= Size) {
28264
28265 NeededSpace = Size;
28266@@ -7140,7 +7101,7 @@
28267 * Check if enough buffer space is provided. Otherwise
28268 * free some entries. Leave one byte space between begin
28269 * and end of buffer to make it possible to detect whether
28270- * the buffer is full or empty
28271+ * the buffer is full or empty.
28272 */
28273 while (BufFree < NeededSpace + 1) {
28274
28275@@ -7179,13 +7140,13 @@
28276 }
28277 BufFree -= NeededSpace;
28278
28279- /* Save the current offsets */
28280+ /* Save the current offsets. */
28281 pAC->Pnmi.TrapQueueBeg = Beg;
28282 pAC->Pnmi.TrapQueueEnd = End;
28283 pAC->Pnmi.TrapBufPad = BufPad;
28284 pAC->Pnmi.TrapBufFree = BufFree;
28285
28286- /* Initialize the trap entry */
28287+ /* Initialize the trap entry. */
28288 *(pBuf + Beg + Size - 1) = (char)Size;
28289 *(pBuf + Beg) = (char)Size;
28290 Val32 = (pAC->Pnmi.TrapUnique) ++;
28291@@ -7220,7 +7181,6 @@
28292 unsigned int Len;
28293 unsigned int DstOff = 0;
28294
28295-
28296 while (Trap != End) {
28297
28298 Len = (unsigned int)*(pBuf + Trap);
28299@@ -7265,7 +7225,6 @@
28300 unsigned int Entries = 0;
28301 unsigned int TotalLen = 0;
28302
28303-
28304 while (Trap != End) {
28305
28306 Len = (unsigned int)*(pBuf + Trap);
28307@@ -7322,14 +7281,14 @@
28308 unsigned int DescrLen;
28309 SK_U32 Val32;
28310
28311-
28312- /* Get trap buffer entry */
28313+ /* Get trap buffer entry. */
28314 DescrLen = SK_STRLEN(pAC->I2c.SenTable[SensorIndex].SenDesc);
28315+
28316 pBuf = GetTrapEntry(pAC, TrapId,
28317 SK_PNMI_TRAP_SENSOR_LEN_BASE + DescrLen);
28318 Offset = SK_PNMI_TRAP_SIMPLE_LEN;
28319
28320- /* Store additionally sensor trap related data */
28321+ /* Store additionally sensor trap related data. */
28322 Val32 = OID_SKGE_SENSOR_INDEX;
28323 SK_PNMI_STORE_U32(pBuf + Offset, Val32);
28324 *(pBuf + Offset + 4) = 4;
28325@@ -7374,7 +7333,6 @@
28326 char *pBuf;
28327 SK_U32 Val32;
28328
28329-
28330 pBuf = GetTrapEntry(pAC, OID_SKGE_TRAP_RLMT_CHANGE_PORT,
28331 SK_PNMI_TRAP_RLMT_CHANGE_LEN);
28332
28333@@ -7402,7 +7360,6 @@
28334 char *pBuf;
28335 SK_U32 Val32;
28336
28337-
28338 pBuf = GetTrapEntry(pAC, TrapId, SK_PNMI_TRAP_RLMT_PORT_LEN);
28339
28340 Val32 = OID_SKGE_RLMT_PORT_INDEX;
28341@@ -7422,12 +7379,11 @@
28342 * Nothing
28343 */
28344 PNMI_STATIC void CopyMac(
28345-char *pDst, /* Pointer to destination buffer */
28346+char *pDst, /* Pointer to destination buffer */
28347 SK_MAC_ADDR *pMac) /* Pointer of Source */
28348 {
28349 int i;
28350
28351-
28352 for (i = 0; i < sizeof(SK_MAC_ADDR); i ++) {
28353
28354 *(pDst + i) = pMac->a[i];
28355@@ -7465,19 +7421,22 @@
28356 SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */
28357 {
28358
28359+ int i;
28360+ unsigned int HwPortIndex;
28361+
28362 SK_U32 RetCode = SK_PNMI_ERR_GENERAL;
28363
28364- /*
28365- * Check instance. We only handle single instance variables
28366- */
28367- if (Instance != (SK_U32)(-1) && Instance != 1) {
28368+ /* Check instance. We only handle single instance variables. */
28369+ if ((Instance != (SK_U32)(-1))) {
28370
28371 *pLen = 0;
28372 return (SK_PNMI_ERR_UNKNOWN_INST);
28373 }
28374+
28375+ /* Get hardware port index */
28376+ HwPortIndex = NetIndex;
28377
28378-
28379- /* Check length */
28380+ /* Check length. */
28381 switch (Id) {
28382
28383 case OID_PNP_CAPABILITIES:
28384@@ -7515,14 +7474,10 @@
28385 break;
28386 }
28387
28388- /*
28389- * Perform action
28390- */
28391+ /* Perform action. */
28392 if (Action == SK_PNMI_GET) {
28393
28394- /*
28395- * Get value
28396- */
28397+ /* Get value. */
28398 switch (Id) {
28399
28400 case OID_PNP_CAPABILITIES:
28401@@ -7530,18 +7485,21 @@
28402 break;
28403
28404 case OID_PNP_QUERY_POWER:
28405- /* The Windows DDK describes: An OID_PNP_QUERY_POWER requests
28406- the miniport to indicate whether it can transition its NIC
28407- to the low-power state.
28408- A miniport driver must always return NDIS_STATUS_SUCCESS
28409- to a query of OID_PNP_QUERY_POWER. */
28410+ /*
28411+ * The Windows DDK describes: An OID_PNP_QUERY_POWER requests
28412+ * the miniport to indicate whether it can transition its NIC
28413+ * to the low-power state.
28414+ * A miniport driver must always return NDIS_STATUS_SUCCESS
28415+ * to a query of OID_PNP_QUERY_POWER.
28416+ */
28417 *pLen = sizeof(SK_DEVICE_POWER_STATE);
28418 RetCode = SK_PNMI_ERR_OK;
28419 break;
28420
28421- /* NDIS handles these OIDs as write-only.
28422+ /*
28423+ * NDIS handles these OIDs as write-only.
28424 * So in case of get action the buffer with written length = 0
28425- * is returned
28426+ * is returned.
28427 */
28428 case OID_PNP_SET_POWER:
28429 case OID_PNP_ADD_WAKE_UP_PATTERN:
28430@@ -7551,7 +7509,7 @@
28431 break;
28432
28433 case OID_PNP_ENABLE_WAKE_UP:
28434- RetCode = SkPowerGetEnableWakeUp(pAC, IoC, pBuf, pLen);
28435+ RetCode = SkPowerGetEnableWakeUp(pAC, IoC, HwPortIndex, pBuf, pLen);
28436 break;
28437
28438 default:
28439@@ -7562,31 +7520,49 @@
28440 return (RetCode);
28441 }
28442
28443-
28444- /*
28445- * Perform preset or set
28446- */
28447+ /* Perform PRESET or SET. */
28448
28449- /* POWER module does not support PRESET action */
28450+ /* The POWER module does not support PRESET action. */
28451 if (Action == SK_PNMI_PRESET) {
28452+
28453 return (SK_PNMI_ERR_OK);
28454 }
28455
28456+ /* */
28457+ i= HwPortIndex;
28458+
28459 switch (Id) {
28460 case OID_PNP_SET_POWER:
28461- RetCode = SkPowerSetPower(pAC, IoC, pBuf, pLen);
28462+ /* Dual net mode? */
28463+ for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
28464+ if (RetCode = SkPowerSetPower(pAC, IoC, i, pBuf, pLen)) {
28465+ break;
28466+ }
28467+ }
28468 break;
28469
28470 case OID_PNP_ADD_WAKE_UP_PATTERN:
28471- RetCode = SkPowerAddWakeUpPattern(pAC, IoC, pBuf, pLen);
28472+ for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
28473+ if (RetCode = SkPowerAddWakeUpPattern(pAC, IoC, i, pBuf, pLen)) {
28474+ break;
28475+ }
28476+ }
28477 break;
28478
28479 case OID_PNP_REMOVE_WAKE_UP_PATTERN:
28480- RetCode = SkPowerRemoveWakeUpPattern(pAC, IoC, pBuf, pLen);
28481+ for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
28482+ if (RetCode = SkPowerRemoveWakeUpPattern(pAC, IoC, i, pBuf, pLen)) {
28483+ break;
28484+ }
28485+ }
28486 break;
28487
28488 case OID_PNP_ENABLE_WAKE_UP:
28489- RetCode = SkPowerSetEnableWakeUp(pAC, IoC, pBuf, pLen);
28490+ for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
28491+ if (RetCode = SkPowerSetEnableWakeUp(pAC, IoC, i, pBuf, pLen)) {
28492+ break;
28493+ }
28494+ }
28495 break;
28496
28497 default:
28498@@ -7600,7 +7576,7 @@
28499 #ifdef SK_DIAG_SUPPORT
28500 /*****************************************************************************
28501 *
28502- * DiagActions - OID handler function of Diagnostic driver
28503+ * DiagActions - OID handler function of Diagnostic driver
28504 *
28505 * Description:
28506 * The code is simple. No description necessary.
28507@@ -7627,22 +7603,17 @@
28508 unsigned int TableIndex, /* Index to the Id table */
28509 SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */
28510 {
28511-
28512 SK_U32 DiagStatus;
28513 SK_U32 RetCode = SK_PNMI_ERR_GENERAL;
28514
28515- /*
28516- * Check instance. We only handle single instance variables.
28517- */
28518+ /* Check instance. We only handle single instance variables. */
28519 if (Instance != (SK_U32)(-1) && Instance != 1) {
28520
28521 *pLen = 0;
28522 return (SK_PNMI_ERR_UNKNOWN_INST);
28523 }
28524
28525- /*
28526- * Check length.
28527- */
28528+ /* Check length. */
28529 switch (Id) {
28530
28531 case OID_SKGE_DIAG_MODE:
28532@@ -7660,10 +7631,9 @@
28533 }
28534
28535 /* Perform action. */
28536-
28537- /* GET value. */
28538 if (Action == SK_PNMI_GET) {
28539
28540+ /* Get value. */
28541 switch (Id) {
28542
28543 case OID_SKGE_DIAG_MODE:
28544@@ -7678,14 +7648,15 @@
28545 RetCode = SK_PNMI_ERR_GENERAL;
28546 break;
28547 }
28548- return (RetCode);
28549+ return (RetCode);
28550 }
28551
28552 /* From here SET or PRESET value. */
28553
28554 /* PRESET value is not supported. */
28555 if (Action == SK_PNMI_PRESET) {
28556- return (SK_PNMI_ERR_OK);
28557+
28558+ return (SK_PNMI_ERR_OK);
28559 }
28560
28561 /* SET value. */
28562@@ -7697,7 +7668,7 @@
28563
28564 /* Attach the DIAG to this adapter. */
28565 case SK_DIAG_ATTACHED:
28566- /* Check if we come from running */
28567+ /* Check if we come from running. */
28568 if (pAC->Pnmi.DiagAttached == SK_DIAG_RUNNING) {
28569
28570 RetCode = SkDrvLeaveDiagMode(pAC);
28571@@ -7732,7 +7703,7 @@
28572 /* If DiagMode is not active, we can enter it. */
28573 if (!pAC->DiagModeActive) {
28574
28575- RetCode = SkDrvEnterDiagMode(pAC);
28576+ RetCode = SkDrvEnterDiagMode(pAC);
28577 }
28578 else {
28579
28580@@ -7751,7 +7722,7 @@
28581 break;
28582
28583 case SK_DIAG_IDLE:
28584- /* Check if we come from running */
28585+ /* Check if we come from running. */
28586 if (pAC->Pnmi.DiagAttached == SK_DIAG_RUNNING) {
28587
28588 RetCode = SkDrvLeaveDiagMode(pAC);
28589@@ -7797,7 +7768,7 @@
28590
28591 /*****************************************************************************
28592 *
28593- * Vct - OID handler function of OIDs
28594+ * Vct - OID handler function of OIDs for Virtual Cable Tester (VCT)
28595 *
28596 * Description:
28597 * The code is simple. No description necessary.
28598@@ -7833,153 +7804,150 @@
28599 SK_U32 PhysPortIndex;
28600 SK_U32 Limit;
28601 SK_U32 Offset;
28602- SK_BOOL Link;
28603- SK_U32 RetCode = SK_PNMI_ERR_GENERAL;
28604- int i;
28605+ SK_U32 RetCode;
28606+ int i;
28607 SK_EVPARA Para;
28608- SK_U32 CableLength;
28609-
28610- /*
28611- * Calculate the port indexes from the instance.
28612- */
28613+
28614+ RetCode = SK_PNMI_ERR_GENERAL;
28615+
28616+ /* Calculate the port indexes from the instance. */
28617 PhysPortMax = pAC->GIni.GIMacsFound;
28618 LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax);
28619-
28620+
28621 /* Dual net mode? */
28622 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
28623 LogPortMax--;
28624 }
28625-
28626+
28627 if ((Instance != (SK_U32) (-1))) {
28628- /* Check instance range. */
28629- if ((Instance < 2) || (Instance > LogPortMax)) {
28630- *pLen = 0;
28631- return (SK_PNMI_ERR_UNKNOWN_INST);
28632- }
28633-
28634+ /*
28635+ * Get one instance of that OID, so check the instance range:
28636+ * There is no virtual port with an Instance == 1, so we get
28637+ * the values from one physical port only.
28638+ */
28639 if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
28640 PhysPortIndex = NetIndex;
28641 }
28642 else {
28643+ if ((Instance < 2) || (Instance > LogPortMax)) {
28644+ *pLen = 0;
28645+ return (SK_PNMI_ERR_UNKNOWN_INST);
28646+ }
28647 PhysPortIndex = Instance - 2;
28648 }
28649 Limit = PhysPortIndex + 1;
28650 }
28651 else {
28652 /*
28653- * Instance == (SK_U32) (-1), get all Instances of that OID.
28654- *
28655- * Not implemented yet. May be used in future releases.
28656+ * Instance == (SK_U32) (-1), so get all instances of that OID.
28657+ * There is no virtual port with an Instance == 1, so we get
28658+ * the values from all physical ports.
28659 */
28660 PhysPortIndex = 0;
28661 Limit = PhysPortMax;
28662 }
28663-
28664- pPrt = &pAC->GIni.GP[PhysPortIndex];
28665- if (pPrt->PHWLinkUp) {
28666- Link = SK_TRUE;
28667- }
28668- else {
28669- Link = SK_FALSE;
28670- }
28671-
28672- /* Check MAC type */
28673- if (pPrt->PhyType != SK_PHY_MARV_COPPER) {
28674+
28675+ /* Check MAC type. */
28676+ if ((Id != OID_SKGE_VCT_CAPABILITIES) &&
28677+ (pAC->GIni.GP[PhysPortIndex].PhyType != SK_PHY_MARV_COPPER)) {
28678 *pLen = 0;
28679- return (SK_PNMI_ERR_GENERAL);
28680+ return (SK_PNMI_ERR_NOT_SUPPORTED);
28681 }
28682-
28683- /* Initialize backup data pointer. */
28684- pVctBackupData = &pAC->Pnmi.VctBackup[PhysPortIndex];
28685-
28686- /* Check action type */
28687+
28688+ /* Check action type. */
28689 if (Action == SK_PNMI_GET) {
28690- /* Check length */
28691+ /* Check length. */
28692 switch (Id) {
28693-
28694+
28695 case OID_SKGE_VCT_GET:
28696 if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_PNMI_VCT)) {
28697 *pLen = (Limit - PhysPortIndex) * sizeof(SK_PNMI_VCT);
28698 return (SK_PNMI_ERR_TOO_SHORT);
28699 }
28700 break;
28701-
28702+
28703 case OID_SKGE_VCT_STATUS:
28704+ case OID_SKGE_VCT_CAPABILITIES:
28705 if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U8)) {
28706 *pLen = (Limit - PhysPortIndex) * sizeof(SK_U8);
28707 return (SK_PNMI_ERR_TOO_SHORT);
28708 }
28709 break;
28710-
28711+
28712 default:
28713 *pLen = 0;
28714 return (SK_PNMI_ERR_GENERAL);
28715 }
28716-
28717- /* Get value */
28718+
28719+ /* Get value. */
28720 Offset = 0;
28721 for (; PhysPortIndex < Limit; PhysPortIndex++) {
28722+
28723+ pPrt = &pAC->GIni.GP[PhysPortIndex];
28724+
28725 switch (Id) {
28726-
28727+
28728 case OID_SKGE_VCT_GET:
28729- if ((Link == SK_FALSE) &&
28730+ if (!pPrt->PHWLinkUp &&
28731 (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_PENDING)) {
28732+
28733 RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_FALSE);
28734+
28735 if (RetCode == 0) {
28736- pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_PENDING;
28737- pAC->Pnmi.VctStatus[PhysPortIndex] |=
28738- (SK_PNMI_VCT_NEW_VCT_DATA | SK_PNMI_VCT_TEST_DONE);
28739-
28740- /* Copy results for later use to PNMI struct. */
28741- for (i = 0; i < 4; i++) {
28742- if (pPrt->PMdiPairSts[i] == SK_PNMI_VCT_NORMAL_CABLE) {
28743- if ((pPrt->PMdiPairLen[i] > 35) && (pPrt->PMdiPairLen[i] < 0xff)) {
28744- pPrt->PMdiPairSts[i] = SK_PNMI_VCT_IMPEDANCE_MISMATCH;
28745- }
28746- }
28747- if ((pPrt->PMdiPairLen[i] > 35) && (pPrt->PMdiPairLen[i] != 0xff)) {
28748- CableLength = 1000 * (((175 * pPrt->PMdiPairLen[i]) / 210) - 28);
28749- }
28750- else {
28751- CableLength = 0;
28752- }
28753- pVctBackupData->PMdiPairLen[i] = CableLength;
28754- pVctBackupData->PMdiPairSts[i] = pPrt->PMdiPairSts[i];
28755- }
28756+
28757+ /* VCT test is finished, so save the data. */
28758+ VctGetResults(pAC, IoC, PhysPortIndex);
28759
28760 Para.Para32[0] = PhysPortIndex;
28761 Para.Para32[1] = -1;
28762 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Para);
28763- SkEventDispatcher(pAC, IoC);
28764- }
28765- else {
28766- ; /* VCT test is running. */
28767+
28768+ /* SkEventDispatcher(pAC, IoC); */
28769 }
28770 }
28771-
28772+
28773+ /* Initialize backup data pointer. */
28774+ pVctBackupData = &pAC->Pnmi.VctBackup[PhysPortIndex];
28775+
28776 /* Get all results. */
28777 CheckVctStatus(pAC, IoC, pBuf, Offset, PhysPortIndex);
28778- Offset += sizeof(SK_U8);
28779+
28780+ Offset++;
28781 *(pBuf + Offset) = pPrt->PCableLen;
28782- Offset += sizeof(SK_U8);
28783+ Offset++;
28784 for (i = 0; i < 4; i++) {
28785- SK_PNMI_STORE_U32((pBuf + Offset), pVctBackupData->PMdiPairLen[i]);
28786+
28787+ SK_PNMI_STORE_U32((pBuf + Offset), pVctBackupData->MdiPairLen[i]);
28788 Offset += sizeof(SK_U32);
28789 }
28790 for (i = 0; i < 4; i++) {
28791- *(pBuf + Offset) = pVctBackupData->PMdiPairSts[i];
28792- Offset += sizeof(SK_U8);
28793+
28794+ *(pBuf + Offset) = pVctBackupData->MdiPairSts[i];
28795+ Offset++;
28796 }
28797-
28798+
28799 RetCode = SK_PNMI_ERR_OK;
28800 break;
28801-
28802+
28803 case OID_SKGE_VCT_STATUS:
28804 CheckVctStatus(pAC, IoC, pBuf, Offset, PhysPortIndex);
28805- Offset += sizeof(SK_U8);
28806+
28807+ Offset++;
28808 RetCode = SK_PNMI_ERR_OK;
28809 break;
28810-
28811+
28812+ case OID_SKGE_VCT_CAPABILITIES:
28813+ if (pPrt->PhyType != SK_PHY_MARV_COPPER) {
28814+ *(pBuf + Offset) = SK_PNMI_VCT_NOT_SUPPORTED;
28815+ }
28816+ else {
28817+ *(pBuf + Offset) = SK_PNMI_VCT_SUPPORTED;
28818+ }
28819+ Offset++;
28820+
28821+ RetCode = SK_PNMI_ERR_OK;
28822+ break;
28823+
28824 default:
28825 *pLen = 0;
28826 return (SK_PNMI_ERR_GENERAL);
28827@@ -7987,15 +7955,15 @@
28828 } /* for */
28829 *pLen = Offset;
28830 return (RetCode);
28831-
28832+
28833 } /* if SK_PNMI_GET */
28834-
28835+
28836 /*
28837 * From here SET or PRESET action. Check if the passed
28838 * buffer length is plausible.
28839 */
28840-
28841- /* Check length */
28842+
28843+ /* Check length. */
28844 switch (Id) {
28845 case OID_SKGE_VCT_SET:
28846 if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U32)) {
28847@@ -8003,42 +7971,45 @@
28848 return (SK_PNMI_ERR_TOO_SHORT);
28849 }
28850 break;
28851-
28852+
28853 default:
28854 *pLen = 0;
28855 return (SK_PNMI_ERR_GENERAL);
28856 }
28857-
28858- /*
28859- * Perform preset or set.
28860- */
28861-
28862+
28863+ /* Perform PRESET or SET. */
28864+
28865 /* VCT does not support PRESET action. */
28866 if (Action == SK_PNMI_PRESET) {
28867+
28868 return (SK_PNMI_ERR_OK);
28869 }
28870-
28871+
28872 Offset = 0;
28873 for (; PhysPortIndex < Limit; PhysPortIndex++) {
28874+
28875+ pPrt = &pAC->GIni.GP[PhysPortIndex];
28876+
28877 switch (Id) {
28878 case OID_SKGE_VCT_SET: /* Start VCT test. */
28879- if (Link == SK_FALSE) {
28880+ if (!pPrt->PHWLinkUp) {
28881 SkGeStopPort(pAC, IoC, PhysPortIndex, SK_STOP_ALL, SK_SOFT_RST);
28882-
28883+
28884 RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_TRUE);
28885+
28886 if (RetCode == 0) { /* RetCode: 0 => Start! */
28887 pAC->Pnmi.VctStatus[PhysPortIndex] |= SK_PNMI_VCT_PENDING;
28888- pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_NEW_VCT_DATA;
28889- pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_LINK;
28890-
28891- /*
28892- * Start VCT timer counter.
28893- */
28894- SK_MEMSET((char *) &Para, 0, sizeof(Para));
28895+ pAC->Pnmi.VctStatus[PhysPortIndex] &=
28896+ ~(SK_PNMI_VCT_NEW_VCT_DATA | SK_PNMI_VCT_LINK);
28897+
28898+ /* Start VCT timer counter. */
28899+ SK_MEMSET((char *)&Para, 0, sizeof(Para));
28900 Para.Para32[0] = PhysPortIndex;
28901 Para.Para32[1] = -1;
28902- SkTimerStart(pAC, IoC, &pAC->Pnmi.VctTimeout[PhysPortIndex].VctTimer,
28903- 4000000, SKGE_PNMI, SK_PNMI_EVT_VCT_RESET, Para);
28904+
28905+ SkTimerStart(pAC, IoC, &pAC->Pnmi.VctTimeout[PhysPortIndex],
28906+ SK_PNMI_VCT_TIMER_CHECK, SKGE_PNMI, SK_PNMI_EVT_VCT_RESET, Para);
28907+
28908 SK_PNMI_STORE_U32((pBuf + Offset), RetCode);
28909 RetCode = SK_PNMI_ERR_OK;
28910 }
28911@@ -8054,7 +8025,7 @@
28912 }
28913 Offset += sizeof(SK_U32);
28914 break;
28915-
28916+
28917 default:
28918 *pLen = 0;
28919 return (SK_PNMI_ERR_GENERAL);
28920@@ -8066,6 +8037,65 @@
28921 } /* Vct */
28922
28923
28924+PNMI_STATIC void VctGetResults(
28925+SK_AC *pAC,
28926+SK_IOC IoC,
28927+SK_U32 Port)
28928+{
28929+ SK_GEPORT *pPrt;
28930+ int i;
28931+ SK_U8 PairLen;
28932+ SK_U8 PairSts;
28933+ SK_U32 MinLength;
28934+ SK_U32 CableLength;
28935+
28936+ pPrt = &pAC->GIni.GP[Port];
28937+
28938+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) {
28939+ MinLength = 25;
28940+ }
28941+ else {
28942+ MinLength = 35;
28943+ }
28944+
28945+ /* Copy results for later use to PNMI struct. */
28946+ for (i = 0; i < 4; i++) {
28947+
28948+ PairLen = pPrt->PMdiPairLen[i];
28949+
28950+ if (((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) == 0) && (i > 1)) {
28951+ PairSts = SK_PNMI_VCT_NOT_PRESENT;
28952+ }
28953+ else {
28954+ PairSts = pPrt->PMdiPairSts[i];
28955+ }
28956+
28957+ if ((PairSts == SK_PNMI_VCT_NORMAL_CABLE) &&
28958+ (PairLen > 28) && (PairLen < 0xff)) {
28959+
28960+ PairSts = SK_PNMI_VCT_IMPEDANCE_MISMATCH;
28961+ }
28962+
28963+ /* Ignore values <= MinLength, the linear factor is 4/5. */
28964+ if ((PairLen > MinLength) && (PairLen < 0xff)) {
28965+
28966+ CableLength = 1000UL * (PairLen - MinLength) * 4 / 5;
28967+ }
28968+ else {
28969+ /* No cable or short cable. */
28970+ CableLength = 0;
28971+ }
28972+
28973+ pAC->Pnmi.VctBackup[Port].MdiPairLen[i] = CableLength;
28974+ pAC->Pnmi.VctBackup[Port].MdiPairSts[i] = PairSts;
28975+ }
28976+
28977+ pAC->Pnmi.VctStatus[Port] &= ~SK_PNMI_VCT_PENDING;
28978+ pAC->Pnmi.VctStatus[Port] |= (SK_PNMI_VCT_NEW_VCT_DATA |
28979+ SK_PNMI_VCT_TEST_DONE);
28980+
28981+} /* GetVctResults */
28982+
28983 PNMI_STATIC void CheckVctStatus(
28984 SK_AC *pAC,
28985 SK_IOC IoC,
28986@@ -8075,54 +8105,57 @@
28987 {
28988 SK_GEPORT *pPrt;
28989 SK_PNMI_VCT *pVctData;
28990+ SK_U8 VctStatus;
28991 SK_U32 RetCode;
28992-
28993+
28994 pPrt = &pAC->GIni.GP[PhysPortIndex];
28995-
28996+
28997 pVctData = (SK_PNMI_VCT *) (pBuf + Offset);
28998 pVctData->VctStatus = SK_PNMI_VCT_NONE;
28999-
29000+
29001+ VctStatus = pAC->Pnmi.VctStatus[PhysPortIndex];
29002+
29003 if (!pPrt->PHWLinkUp) {
29004-
29005+
29006 /* Was a VCT test ever made before? */
29007- if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_TEST_DONE) {
29008- if ((pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_LINK)) {
29009+ if (VctStatus & SK_PNMI_VCT_TEST_DONE) {
29010+ if (VctStatus & SK_PNMI_VCT_LINK) {
29011 pVctData->VctStatus |= SK_PNMI_VCT_OLD_VCT_DATA;
29012 }
29013 else {
29014 pVctData->VctStatus |= SK_PNMI_VCT_NEW_VCT_DATA;
29015 }
29016 }
29017-
29018+
29019 /* Check VCT test status. */
29020 RetCode = SkGmCableDiagStatus(pAC,IoC, PhysPortIndex, SK_FALSE);
29021+
29022 if (RetCode == 2) { /* VCT test is running. */
29023 pVctData->VctStatus |= SK_PNMI_VCT_RUNNING;
29024 }
29025 else { /* VCT data was copied to pAC here. Check PENDING state. */
29026- if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_PENDING) {
29027+ if (VctStatus & SK_PNMI_VCT_PENDING) {
29028 pVctData->VctStatus |= SK_PNMI_VCT_NEW_VCT_DATA;
29029 }
29030 }
29031-
29032+
29033 if (pPrt->PCableLen != 0xff) { /* Old DSP value. */
29034 pVctData->VctStatus |= SK_PNMI_VCT_OLD_DSP_DATA;
29035 }
29036 }
29037 else {
29038-
29039 /* Was a VCT test ever made before? */
29040- if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_TEST_DONE) {
29041+ if (VctStatus & SK_PNMI_VCT_TEST_DONE) {
29042 pVctData->VctStatus &= ~SK_PNMI_VCT_NEW_VCT_DATA;
29043 pVctData->VctStatus |= SK_PNMI_VCT_OLD_VCT_DATA;
29044 }
29045-
29046+
29047 /* DSP only valid in 100/1000 modes. */
29048- if (pAC->GIni.GP[PhysPortIndex].PLinkSpeedUsed !=
29049- SK_LSPEED_STAT_10MBPS) {
29050+ if (pPrt->PLinkSpeedUsed != SK_LSPEED_STAT_10MBPS) {
29051 pVctData->VctStatus |= SK_PNMI_VCT_NEW_DSP_DATA;
29052 }
29053 }
29054+
29055 } /* CheckVctStatus */
29056
29057
29058@@ -8165,29 +8198,29 @@
29059 ReturnCode = SK_PNMI_ERR_GENERAL;
29060
29061 SK_MEMCPY(&Mode, pBuf, sizeof(SK_I32));
29062- SK_MEMCPY(&Oid, (char *) pBuf + sizeof(SK_I32), sizeof(SK_U32));
29063+ SK_MEMCPY(&Oid, (char *)pBuf + sizeof(SK_I32), sizeof(SK_U32));
29064 HeaderLength = sizeof(SK_I32) + sizeof(SK_U32);
29065 *pLen = *pLen - HeaderLength;
29066- SK_MEMCPY((char *) pBuf + sizeof(SK_I32), (char *) pBuf + HeaderLength, *pLen);
29067+ SK_MEMCPY((char *)pBuf + sizeof(SK_I32), (char *)pBuf + HeaderLength, *pLen);
29068
29069 switch(Mode) {
29070 case SK_GET_SINGLE_VAR:
29071- ReturnCode = SkPnmiGetVar(pAC, IoC, Oid,
29072- (char *) pBuf + sizeof(SK_I32), pLen,
29073+ ReturnCode = SkPnmiGetVar(pAC, IoC, Oid,
29074+ (char *)pBuf + sizeof(SK_I32), pLen,
29075 ((SK_U32) (-1)), NetIndex);
29076 SK_PNMI_STORE_U32(pBuf, ReturnCode);
29077 *pLen = *pLen + sizeof(SK_I32);
29078 break;
29079 case SK_PRESET_SINGLE_VAR:
29080- ReturnCode = SkPnmiPreSetVar(pAC, IoC, Oid,
29081- (char *) pBuf + sizeof(SK_I32), pLen,
29082+ ReturnCode = SkPnmiPreSetVar(pAC, IoC, Oid,
29083+ (char *)pBuf + sizeof(SK_I32), pLen,
29084 ((SK_U32) (-1)), NetIndex);
29085 SK_PNMI_STORE_U32(pBuf, ReturnCode);
29086 *pLen = *pLen + sizeof(SK_I32);
29087 break;
29088 case SK_SET_SINGLE_VAR:
29089- ReturnCode = SkPnmiSetVar(pAC, IoC, Oid,
29090- (char *) pBuf + sizeof(SK_I32), pLen,
29091+ ReturnCode = SkPnmiSetVar(pAC, IoC, Oid,
29092+ (char *)pBuf + sizeof(SK_I32), pLen,
29093 ((SK_U32) (-1)), NetIndex);
29094 SK_PNMI_STORE_U32(pBuf, ReturnCode);
29095 *pLen = *pLen + sizeof(SK_I32);
29096@@ -8208,3 +8241,86 @@
29097 return (ReturnCode);
29098
29099 } /* SkGeIocGen */
29100+
29101+#ifdef SK_ASF
29102+/*****************************************************************************
29103+ *
29104+ * Asf
29105+ *
29106+ * Description:
29107+ * The code is simple. No description necessary.
29108+ *
29109+ * Returns:
29110+ * SK_PNMI_ERR_OK The request was successfully performed.
29111+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.
29112+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
29113+ * the correct data (e.g. a 32bit value is
29114+ * needed, but a 16 bit value was passed).
29115+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
29116+ * exist (e.g. port instance 3 on a two port
29117+ * adapter.
29118+ */
29119+
29120+PNMI_STATIC int Asf(
29121+SK_AC *pAC, /* Pointer to adapter context */
29122+SK_IOC IoC, /* IO context handle */
29123+int Action, /* GET/PRESET/SET action */
29124+SK_U32 Id, /* Object ID that is to be processed */
29125+char *pBuf, /* Buffer used for the management data transfer */
29126+unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */
29127+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
29128+unsigned int TableIndex, /* Index to the Id table */
29129+SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */
29130+{
29131+ SK_U32 RetCode = SK_PNMI_ERR_GENERAL;
29132+
29133+ /*
29134+ * Check instance. We only handle single instance variables.
29135+ */
29136+ if (Instance != (SK_U32)(-1) && Instance != 1) {
29137+
29138+ *pLen = 0;
29139+ return (SK_PNMI_ERR_UNKNOWN_INST);
29140+ }
29141+
29142+ /* Perform action. */
29143+ /* GET value. */
29144+ if (Action == SK_PNMI_GET) {
29145+ switch (Id) {
29146+ case OID_SKGE_ASF:
29147+ RetCode = SkAsfGet(pAC, IoC, (SK_U8 *) pBuf, pLen);
29148+ break;
29149+ default:
29150+ RetCode = SkAsfGetOid( pAC, IoC, Id, Instance, (SK_U8 *) pBuf, pLen );
29151+ break;
29152+ }
29153+
29154+ return (RetCode);
29155+ }
29156+
29157+ /* PRESET value. */
29158+ if (Action == SK_PNMI_PRESET) {
29159+ switch (Id) {
29160+ case OID_SKGE_ASF:
29161+ RetCode = SkAsfPreSet(pAC, IoC, (SK_U8 *) pBuf, pLen);
29162+ break;
29163+ default:
29164+ RetCode = SkAsfPreSetOid( pAC, IoC, Id, Instance, (SK_U8 *) pBuf, pLen );
29165+ break;
29166+ }
29167+ }
29168+
29169+ /* SET value. */
29170+ if (Action == SK_PNMI_SET) {
29171+ switch (Id) {
29172+ case OID_SKGE_ASF:
29173+ RetCode = SkAsfSet(pAC, IoC, (SK_U8 *) pBuf, pLen);
29174+ break;
29175+ default:
29176+ RetCode = SkAsfSetOid( pAC, IoC, Id, Instance, (SK_U8 *) pBuf, pLen );
29177+ break;
29178+ }
29179+ }
29180+ return (RetCode);
29181+}
29182+#endif /* SK_ASF */
29183diff -urN linux-2.6.17.orig/drivers/net/sk98lin/skgesirq.c linux-2.6.17/drivers/net/sk98lin/skgesirq.c
29184--- linux-2.6.17.orig/drivers/net/sk98lin/skgesirq.c 2006-06-22 13:17:16.000000000 +0200
29185+++ linux-2.6.17/drivers/net/sk98lin/skgesirq.c 2006-04-27 11:43:44.000000000 +0200
29186@@ -2,23 +2,24 @@
29187 *
29188 * Name: skgesirq.c
29189 * Project: Gigabit Ethernet Adapters, Common Modules
29190- * Version: $Revision$
29191- * Date: $Date$
29192+ * Version: $Revision$
29193+ * Date: $Date$
29194 * Purpose: Special IRQ module
29195 *
29196 ******************************************************************************/
29197
29198 /******************************************************************************
29199 *
29200+ * LICENSE:
29201 * (C)Copyright 1998-2002 SysKonnect.
29202- * (C)Copyright 2002-2003 Marvell.
29203+ * (C)Copyright 2002-2006 Marvell.
29204 *
29205 * This program is free software; you can redistribute it and/or modify
29206 * it under the terms of the GNU General Public License as published by
29207 * the Free Software Foundation; either version 2 of the License, or
29208 * (at your option) any later version.
29209- *
29210 * The information in this file is provided "AS IS" without warranty.
29211+ * /LICENSE
29212 *
29213 ******************************************************************************/
29214
29215@@ -38,7 +39,7 @@
29216 * right after this ISR.
29217 *
29218 * The Interrupt source register of the adapter is NOT read by this module.
29219- * SO if the drivers implementor needs a while loop around the
29220+ * SO if the drivers implementor needs a while loop around the
29221 * slow data paths interrupt bits, he needs to call the SkGeSirqIsr() for
29222 * each loop entered.
29223 *
29224@@ -46,11 +47,6 @@
29225 *
29226 */
29227
29228-#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
29229-static const char SysKonnectFileId[] =
29230- "@(#) $Id$ (C) Marvell.";
29231-#endif
29232-
29233 #include "h/skdrv1st.h" /* Driver Specific Definitions */
29234 #ifndef SK_SLIM
29235 #include "h/skgepnmi.h" /* PNMI Definitions */
29236@@ -58,6 +54,13 @@
29237 #endif
29238 #include "h/skdrv2nd.h" /* Adapter Control and Driver specific Def. */
29239
29240+/* local variables ************************************************************/
29241+
29242+#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
29243+static const char SysKonnectFileId[] =
29244+ "@(#) $Id$ (C) Marvell.";
29245+#endif
29246+
29247 /* local function prototypes */
29248 #ifdef GENESIS
29249 static int SkGePortCheckUpXmac(SK_AC*, SK_IOC, int, SK_BOOL);
29250@@ -86,7 +89,7 @@
29251 XM_RXF_511B,
29252 XM_RXF_1023B,
29253 XM_RXF_MAX_SZ
29254-} ;
29255+};
29256 #endif /* GENESIS */
29257
29258 #ifdef __C2MAN__
29259@@ -109,8 +112,8 @@
29260 * Returns: N/A
29261 */
29262 static void SkHWInitDefSense(
29263-SK_AC *pAC, /* adapter context */
29264-SK_IOC IoC, /* IO context */
29265+SK_AC *pAC, /* Adapter Context */
29266+SK_IOC IoC, /* I/O context */
29267 int Port) /* Port Index (MAC_1 + n) */
29268 {
29269 SK_GEPORT *pPrt; /* GIni Port struct pointer */
29270@@ -119,7 +122,7 @@
29271
29272 pPrt->PAutoNegTimeOut = 0;
29273
29274- if (pPrt->PLinkModeConf != SK_LMODE_AUTOSENSE) {
29275+ if (pPrt->PLinkModeConf != (SK_U8)SK_LMODE_AUTOSENSE) {
29276 pPrt->PLinkMode = pPrt->PLinkModeConf;
29277 return;
29278 }
29279@@ -145,8 +148,8 @@
29280 *
29281 */
29282 static SK_U8 SkHWSenseGetNext(
29283-SK_AC *pAC, /* adapter context */
29284-SK_IOC IoC, /* IO context */
29285+SK_AC *pAC, /* Adapter Context */
29286+SK_IOC IoC, /* I/O context */
29287 int Port) /* Port Index (MAC_1 + n) */
29288 {
29289 SK_GEPORT *pPrt; /* GIni Port struct pointer */
29290@@ -155,18 +158,18 @@
29291
29292 pPrt->PAutoNegTimeOut = 0;
29293
29294- if (pPrt->PLinkModeConf != (SK_U8)SK_LMODE_AUTOSENSE) {
29295+ if (pPrt->PLinkModeConf != (SK_U8)SK_LMODE_AUTOSENSE) {
29296 /* Leave all as configured */
29297 return(pPrt->PLinkModeConf);
29298 }
29299
29300- if (pPrt->PLinkMode == (SK_U8)SK_LMODE_AUTOFULL) {
29301+ if (pPrt->PLinkMode == (SK_U8)SK_LMODE_AUTOFULL) {
29302 /* Return next mode AUTOBOTH */
29303- return ((SK_U8)SK_LMODE_AUTOBOTH);
29304+ return((SK_U8)SK_LMODE_AUTOBOTH);
29305 }
29306
29307 /* Return default autofull */
29308- return ((SK_U8)SK_LMODE_AUTOFULL);
29309+ return((SK_U8)SK_LMODE_AUTOFULL);
29310 } /* SkHWSenseGetNext */
29311
29312
29313@@ -179,8 +182,8 @@
29314 * Returns: N/A
29315 */
29316 static void SkHWSenseSetNext(
29317-SK_AC *pAC, /* adapter context */
29318-SK_IOC IoC, /* IO context */
29319+SK_AC *pAC, /* Adapter Context */
29320+SK_IOC IoC, /* I/O context */
29321 int Port, /* Port Index (MAC_1 + n) */
29322 SK_U8 NewMode) /* New Mode to be written in sense mode */
29323 {
29324@@ -190,7 +193,7 @@
29325
29326 pPrt->PAutoNegTimeOut = 0;
29327
29328- if (pPrt->PLinkModeConf != (SK_U8)SK_LMODE_AUTOSENSE) {
29329+ if (pPrt->PLinkModeConf != (SK_U8)SK_LMODE_AUTOSENSE) {
29330 return;
29331 }
29332
29333@@ -214,8 +217,8 @@
29334 * Returns: N/A
29335 */
29336 void SkHWLinkDown(
29337-SK_AC *pAC, /* adapter context */
29338-SK_IOC IoC, /* IO context */
29339+SK_AC *pAC, /* Adapter Context */
29340+SK_IOC IoC, /* I/O context */
29341 int Port) /* Port Index (MAC_1 + n) */
29342 {
29343 SK_GEPORT *pPrt; /* GIni Port struct pointer */
29344@@ -227,26 +230,28 @@
29345
29346 /* Disable Receiver and Transmitter */
29347 SkMacRxTxDisable(pAC, IoC, Port);
29348-
29349+
29350 /* Init default sense mode */
29351 SkHWInitDefSense(pAC, IoC, Port);
29352
29353- if (pPrt->PHWLinkUp == SK_FALSE) {
29354+ if (!pPrt->PHWLinkUp) {
29355 return;
29356 }
29357
29358- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
29359+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
29360 ("Link down Port %d\n", Port));
29361
29362 /* Set Link to DOWN */
29363 pPrt->PHWLinkUp = SK_FALSE;
29364
29365+#ifndef SK_SLIM
29366 /* Reset Port stati */
29367- pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN;
29368- pPrt->PFlowCtrlStatus = (SK_U8)SK_FLOW_STAT_NONE;
29369+ pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN;
29370+ pPrt->PFlowCtrlStatus = (SK_U8)SK_FLOW_STAT_NONE;
29371 pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_INDETERMINATED;
29372+#endif /* !SK_SLIM */
29373
29374- /* Re-init Phy especially when the AutoSense default is set now */
29375+ /* Re-init PHY especially when the AutoSense default is set now */
29376 SkMacInitPhy(pAC, IoC, Port, SK_FALSE);
29377
29378 /* GP0: used for workaround of Rev. C Errata 2 */
29379@@ -265,9 +270,9 @@
29380 *
29381 * Returns: N/A
29382 */
29383-static void SkHWLinkUp(
29384-SK_AC *pAC, /* adapter context */
29385-SK_IOC IoC, /* IO context */
29386+void SkHWLinkUp(
29387+SK_AC *pAC, /* Adapter Context */
29388+SK_IOC IoC, /* I/O context */
29389 int Port) /* Port Index (MAC_1 + n) */
29390 {
29391 SK_GEPORT *pPrt; /* GIni Port struct pointer */
29392@@ -280,12 +285,14 @@
29393 }
29394
29395 pPrt->PHWLinkUp = SK_TRUE;
29396+
29397+#ifndef SK_SLIM
29398 pPrt->PAutoNegFail = SK_FALSE;
29399- pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN;
29400+ pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN;
29401
29402- if (pPrt->PLinkMode != (SK_U8)SK_LMODE_AUTOHALF &&
29403- pPrt->PLinkMode != (SK_U8)SK_LMODE_AUTOFULL &&
29404- pPrt->PLinkMode != (SK_U8)SK_LMODE_AUTOBOTH) {
29405+ if (pPrt->PLinkMode != (SK_U8)SK_LMODE_AUTOHALF &&
29406+ pPrt->PLinkMode != (SK_U8)SK_LMODE_AUTOFULL &&
29407+ pPrt->PLinkMode != (SK_U8)SK_LMODE_AUTOBOTH) {
29408 /* Link is up and no Auto-negotiation should be done */
29409
29410 /* Link speed should be the configured one */
29411@@ -293,7 +300,9 @@
29412 case SK_LSPEED_AUTO:
29413 /* default is 1000 Mbps */
29414 case SK_LSPEED_1000MBPS:
29415- pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_1000MBPS;
29416+ pPrt->PLinkSpeedUsed = (SK_U8)
29417+ ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) ?
29418+ SK_LSPEED_STAT_1000MBPS : SK_LSPEED_STAT_100MBPS;
29419 break;
29420 case SK_LSPEED_100MBPS:
29421 pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_100MBPS;
29422@@ -304,19 +313,19 @@
29423 }
29424
29425 /* Set Link Mode Status */
29426- if (pPrt->PLinkMode == SK_LMODE_FULL) {
29427- pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_FULL;
29428- }
29429- else {
29430- pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_HALF;
29431- }
29432+ pPrt->PLinkModeStatus = (SK_U8)
29433+ ((pPrt->PLinkMode == (SK_U8)SK_LMODE_FULL) ?
29434+ SK_LMODE_STAT_FULL : SK_LMODE_STAT_HALF);
29435
29436 /* No flow control without auto-negotiation */
29437- pPrt->PFlowCtrlStatus = (SK_U8)SK_FLOW_STAT_NONE;
29438+ pPrt->PFlowCtrlStatus = (SK_U8)SK_FLOW_STAT_NONE;
29439+#endif /* !SK_SLIM */
29440
29441 /* enable Rx/Tx */
29442- (void)SkMacRxTxEnable(pAC, IoC, Port);
29443+ (void)SkMacRxTxEnable(pAC, IoC, Port);
29444+#ifndef SK_SLIM
29445 }
29446+#endif /* !SK_SLIM */
29447 } /* SkHWLinkUp */
29448
29449
29450@@ -329,14 +338,16 @@
29451 * Returns: N/A
29452 */
29453 static void SkMacParity(
29454-SK_AC *pAC, /* adapter context */
29455-SK_IOC IoC, /* IO context */
29456-int Port) /* Port Index of the port failed */
29457+SK_AC *pAC, /* Adapter Context */
29458+SK_IOC IoC, /* I/O context */
29459+int Port) /* Port Index (MAC_1 + n) */
29460 {
29461 SK_EVPARA Para;
29462 SK_GEPORT *pPrt; /* GIni Port struct pointer */
29463 SK_U32 TxMax; /* Tx Max Size Counter */
29464
29465+ TxMax = 0;
29466+
29467 pPrt = &pAC->GIni.GP[Port];
29468
29469 /* Clear IRQ Tx Parity Error */
29470@@ -346,7 +357,7 @@
29471 SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_CLR_PERR);
29472 }
29473 #endif /* GENESIS */
29474-
29475+
29476 #ifdef YUKON
29477 if (pAC->GIni.GIYukon) {
29478 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
29479@@ -355,7 +366,7 @@
29480 pAC->GIni.GIChipRev == 0) ? GMF_CLI_TX_FC : GMF_CLI_TX_PE));
29481 }
29482 #endif /* YUKON */
29483-
29484+
29485 if (pPrt->PCheckPar) {
29486
29487 if (Port == MAC_1) {
29488@@ -366,7 +377,7 @@
29489 }
29490 Para.Para64 = Port;
29491 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
29492-
29493+
29494 Para.Para32[0] = Port;
29495 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
29496
29497@@ -378,18 +389,18 @@
29498 if (pAC->GIni.GIGenesis) {
29499 /* Snap statistic counters */
29500 (void)SkXmUpdateStats(pAC, IoC, Port);
29501-
29502+
29503 (void)SkXmMacStatistic(pAC, IoC, Port, XM_TXF_MAX_SZ, &TxMax);
29504 }
29505 #endif /* GENESIS */
29506-
29507+
29508 #ifdef YUKON
29509 if (pAC->GIni.GIYukon) {
29510
29511 (void)SkGmMacStatistic(pAC, IoC, Port, GM_TXF_1518B, &TxMax);
29512 }
29513 #endif /* YUKON */
29514-
29515+
29516 if (TxMax > 0) {
29517 /* From now on check the parity */
29518 pPrt->PCheckPar = SK_TRUE;
29519@@ -399,15 +410,15 @@
29520
29521 /******************************************************************************
29522 *
29523- * SkGeHwErr() - Hardware Error service routine
29524+ * SkGeYuHwErr() - Hardware Error service routine (Genesis and Yukon)
29525 *
29526 * Description: handles all HW Error interrupts
29527 *
29528 * Returns: N/A
29529 */
29530-static void SkGeHwErr(
29531-SK_AC *pAC, /* adapter context */
29532-SK_IOC IoC, /* IO context */
29533+static void SkGeYuHwErr(
29534+SK_AC *pAC, /* Adapter Context */
29535+SK_IOC IoC, /* I/O context */
29536 SK_U32 HwStatus) /* Interrupt status word */
29537 {
29538 SK_EVPARA Para;
29539@@ -423,10 +434,10 @@
29540 }
29541
29542 /* Reset all bits in the PCI STATUS register */
29543- SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);
29544-
29545+ SK_IN16(IoC, PCI_C(pAC, PCI_STATUS), &Word);
29546+
29547 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
29548- SK_OUT16(IoC, PCI_C(PCI_STATUS), (SK_U16)(Word | PCI_ERRBITS));
29549+ SK_OUT16(IoC, PCI_C(pAC, PCI_STATUS), (SK_U16)(Word | PCI_ERRBITS));
29550 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
29551
29552 Para.Para64 = 0;
29553@@ -461,7 +472,7 @@
29554 }
29555 }
29556 #endif /* GENESIS */
29557-
29558+
29559 #ifdef YUKON
29560 if (pAC->GIni.GIYukon) {
29561 /* This is necessary only for Rx timing measurements */
29562@@ -484,14 +495,18 @@
29563 #endif /* YUKON */
29564
29565 if ((HwStatus & IS_RAM_RD_PAR) != 0) {
29566+
29567 SK_OUT16(IoC, B3_RI_CTRL, RI_CLR_RD_PERR);
29568+
29569 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E014, SKERR_SIRQ_E014MSG);
29570 Para.Para64 = 0;
29571 SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
29572 }
29573
29574 if ((HwStatus & IS_RAM_WR_PAR) != 0) {
29575+
29576 SK_OUT16(IoC, B3_RI_CTRL, RI_CLR_WR_PERR);
29577+
29578 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E015, SKERR_SIRQ_E015MSG);
29579 Para.Para64 = 0;
29580 SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
29581@@ -512,7 +527,7 @@
29582 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E018, SKERR_SIRQ_E018MSG);
29583 Para.Para64 = MAC_1;
29584 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
29585-
29586+
29587 Para.Para32[0] = MAC_1;
29588 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
29589 }
29590@@ -524,37 +539,297 @@
29591 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E019, SKERR_SIRQ_E019MSG);
29592 Para.Para64 = MAC_2;
29593 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
29594-
29595+
29596 Para.Para32[0] = MAC_2;
29597 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
29598 }
29599-} /* SkGeHwErr */
29600+} /* SkGeYuHwErr */
29601+
29602+#ifdef YUK2
29603+/******************************************************************************
29604+ *
29605+ * SkYuk2HwPortErr() - Service HW Errors for specified port (Yukon-2 only)
29606+ *
29607+ * Description: handles the HW Error interrupts for a specific port.
29608+ *
29609+ * Returns: N/A
29610+ */
29611+static void SkYuk2HwPortErr(
29612+SK_AC *pAC, /* Adapter Context */
29613+SK_IOC IoC, /* I/O Context */
29614+SK_U32 HwStatus, /* Interrupt status word */
29615+int Port) /* Port Index (MAC_1 + n) */
29616+{
29617+ SK_EVPARA Para;
29618+ int Queue;
29619+
29620+ if (Port == MAC_2) {
29621+ HwStatus >>= 8;
29622+ }
29623+
29624+ if ((HwStatus & Y2_HWE_L1_MASK) == 0) {
29625+ return;
29626+ }
29627+
29628+ if ((HwStatus & Y2_IS_PAR_RD1) != 0) {
29629+ /* Clear IRQ */
29630+ SK_OUT16(IoC, SELECT_RAM_BUFFER(Port, B3_RI_CTRL), RI_CLR_RD_PERR);
29631+
29632+ if (Port == MAC_1) {
29633+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E028, SKERR_SIRQ_E028MSG);
29634+ }
29635+ else {
29636+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E030, SKERR_SIRQ_E030MSG);
29637+ }
29638+ }
29639
29640+ if ((HwStatus & Y2_IS_PAR_WR1) != 0) {
29641+ /* Clear IRQ */
29642+ SK_OUT16(IoC, SELECT_RAM_BUFFER(Port, B3_RI_CTRL), RI_CLR_WR_PERR);
29643+
29644+ if (Port == MAC_1) {
29645+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E029, SKERR_SIRQ_E029MSG);
29646+ }
29647+ else {
29648+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E031, SKERR_SIRQ_E031MSG);
29649+ }
29650+ }
29651+
29652+ if ((HwStatus & Y2_IS_PAR_MAC1) != 0) {
29653+ /* Clear IRQ */
29654+ SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
29655+
29656+ if (Port == MAC_1) {
29657+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E016, SKERR_SIRQ_E016MSG);
29658+ }
29659+ else {
29660+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E017, SKERR_SIRQ_E017MSG);
29661+ }
29662+ }
29663+
29664+ if ((HwStatus & Y2_IS_PAR_RX1) != 0) {
29665+ if (Port == MAC_1) {
29666+ Queue = Q_R1;
29667+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E018, SKERR_SIRQ_E018MSG);
29668+ }
29669+ else {
29670+ Queue = Q_R2;
29671+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E019, SKERR_SIRQ_E019MSG);
29672+ }
29673+ /* Clear IRQ */
29674+ SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_PAR);
29675+ }
29676+
29677+ if ((HwStatus & Y2_IS_TCP_TXS1) != 0) {
29678+ if (Port == MAC_1) {
29679+ Queue = Q_XS1;
29680+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E033, SKERR_SIRQ_E033MSG);
29681+ }
29682+ else {
29683+ Queue = Q_XS2;
29684+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E035, SKERR_SIRQ_E035MSG);
29685+ }
29686+ /* Clear IRQ */
29687+ SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_TCP);
29688+ }
29689+
29690+ if ((HwStatus & Y2_IS_TCP_TXA1) != 0) {
29691+ if (Port == MAC_1) {
29692+ Queue = Q_XA1;
29693+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E032, SKERR_SIRQ_E032MSG);
29694+ }
29695+ else {
29696+ Queue = Q_XA2;
29697+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E034, SKERR_SIRQ_E034MSG);
29698+ }
29699+ /* Clear IRQ */
29700+ SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_TCP);
29701+ }
29702+
29703+ Para.Para64 = Port;
29704+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
29705+
29706+ Para.Para32[0] = Port;
29707+ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
29708+
29709+} /* SkYuk2HwPortErr */
29710
29711 /******************************************************************************
29712 *
29713- * SkGeSirqIsr() - Special Interrupt Service Routine
29714+ * SkYuk2HwErr() - Hardware Error service routine (Yukon-2 only)
29715 *
29716- * Description: handles all non data transfer specific interrupts (slow path)
29717+ * Description: handles all HW Error interrupts
29718+ *
29719+ * Returns: N/A
29720+ */
29721+static void SkYuk2HwErr(
29722+SK_AC *pAC, /* Adapter Context */
29723+SK_IOC IoC, /* I/O Context */
29724+SK_U32 HwStatus) /* Interrupt status word */
29725+{
29726+ SK_EVPARA Para;
29727+ SK_U16 Word;
29728+ SK_U32 DWord;
29729+ SK_U32 TlpHead[4];
29730+ int i;
29731+
29732+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
29733+ ("HW-Error Status: 0x%08lX\n", HwStatus));
29734+
29735+ /* This is necessary only for Rx timing measurements */
29736+ if ((HwStatus & Y2_IS_TIST_OV) != 0) {
29737+ /* increment Time Stamp Timer counter (high) */
29738+ pAC->GIni.GITimeStampCnt++;
29739+
29740+ /* Clear Time Stamp Timer IRQ */
29741+ SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8)GMT_ST_CLR_IRQ);
29742+ }
29743+
29744+ /* Evaluate Y2_IS_PCI_NEXP before Y2_IS_MST_ERR or Y2_IS_IRQ_STAT */
29745+ if ((HwStatus & Y2_IS_PCI_NEXP) != 0) {
29746+ /*
29747+ * This error is also mapped either to Master Abort (Y2_IS_MST_ERR)
29748+ * or Target Abort (Y2_IS_IRQ_STAT) bit and can only be cleared there.
29749+ * Therefore handle this event just by printing an error log entry.
29750+ */
29751+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E027, SKERR_SIRQ_E027MSG);
29752+ }
29753+
29754+ if ((HwStatus & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) {
29755+ /* PCI Errors occured */
29756+ if ((HwStatus & Y2_IS_IRQ_STAT) != 0) {
29757+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E013, SKERR_SIRQ_E013MSG);
29758+ }
29759+ else {
29760+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E012, SKERR_SIRQ_E012MSG);
29761+ }
29762+
29763+ /* Reset all bits in the PCI STATUS register */
29764+ SK_IN16(IoC, PCI_C(pAC, PCI_STATUS), &Word);
29765+
29766+ SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
29767+ SK_OUT16(IoC, PCI_C(pAC, PCI_STATUS), (SK_U16)(Word | PCI_ERRBITS));
29768+ SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
29769+
29770+ Para.Para64 = 0;
29771+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
29772+ }
29773+
29774+ /* check for PCI-Express Uncorrectable Error */
29775+ if ((HwStatus & Y2_IS_PCI_EXP) != 0) {
29776+ /*
29777+ * On PCI-Express bus bridges are called root complexes (RC).
29778+ * PCI-Express errors are recognized by the root complex too,
29779+ * which requests the system to handle the problem. After error
29780+ * occurence it may be that no access to the adapter may be performed
29781+ * any longer.
29782+ */
29783+
29784+ /* Get uncorrectable error status */
29785+ SK_IN32(IoC, PCI_C(pAC, PEX_UNC_ERR_STAT), &DWord);
29786+
29787+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
29788+ ("PEX Uncorr.Error Status: 0x%08lX\n", DWord));
29789+
29790+ if (DWord != PEX_UNSUP_REQ) {
29791+ /* ignore Unsupported Request Errors */
29792+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E026, SKERR_SIRQ_E026MSG);
29793+ }
29794+
29795+ if ((DWord & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) {
29796+ /*
29797+ * Stop only, if the uncorrectable error is fatal or
29798+ * Poisoned TLP occured
29799+ */
29800+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, ("Header Log:"));
29801+
29802+ for (i = 0; i < 4; i++) {
29803+ /* get TLP Header from Log Registers */
29804+ SK_IN32(IoC, PCI_C(pAC, PEX_HEADER_LOG + i*4), &TlpHead[i]);
29805+
29806+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
29807+ (" 0x%08lX", TlpHead[i]));
29808+ }
29809+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, ("\n"));
29810+
29811+ /* check for vendor defined broadcast message */
29812+ if (TlpHead[0] == 0x73004001 && (SK_U8)TlpHead[1] == 0x7f) {
29813+
29814+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
29815+ ("Vendor defined broadcast message\n"));
29816+ }
29817+ else {
29818+ Para.Para64 = 0;
29819+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
29820+
29821+ pAC->GIni.GIValHwIrqMask &= ~Y2_IS_PCI_EXP;
29822+ /* Rewrite HW IRQ mask */
29823+ SK_OUT32(IoC, B0_HWE_IMSK, pAC->GIni.GIValHwIrqMask);
29824+ }
29825+ }
29826+
29827+ /* clear any PEX errors */
29828+ SK_OUT32(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
29829+ SK_OUT32(IoC, PCI_C(pAC, PEX_UNC_ERR_STAT), 0xffffffffUL);
29830+ SK_OUT32(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
29831+
29832+ SK_IN32(IoC, PCI_C(pAC, PEX_UNC_ERR_STAT), &DWord);
29833+
29834+ if ((DWord & PEX_RX_OV) != 0) {
29835+ /* Dev #4.205 occured */
29836+ pAC->GIni.GIValHwIrqMask &= ~Y2_IS_PCI_EXP;
29837+ pAC->GIni.GIValIrqMask &= ~Y2_IS_HW_ERR;
29838+ }
29839+ }
29840+
29841+ for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
29842+
29843+ SkYuk2HwPortErr(pAC, IoC, HwStatus, i);
29844+ }
29845+
29846+} /* SkYuk2HwErr */
29847+#endif /* YUK2 */
29848+
29849+/******************************************************************************
29850+ *
29851+ * SkGeSirqIsr() - Wrapper for Special Interrupt Service Routine
29852+ *
29853+ * Description: calls the preselected special ISR (slow path)
29854 *
29855 * Returns: N/A
29856 */
29857 void SkGeSirqIsr(
29858-SK_AC *pAC, /* adapter context */
29859-SK_IOC IoC, /* IO context */
29860+SK_AC *pAC, /* Adapter Context */
29861+SK_IOC IoC, /* I/O context */
29862+SK_U32 Istatus) /* Interrupt status word */
29863+{
29864+ pAC->GIni.GIFunc.pSkGeSirqIsr(pAC, IoC, Istatus);
29865+}
29866+
29867+/******************************************************************************
29868+ *
29869+ * SkGeYuSirqIsr() - Special Interrupt Service Routine
29870+ *
29871+ * Description: handles all non data transfer specific interrupts (slow path)
29872+ *
29873+ * Returns: N/A
29874+ */
29875+void SkGeYuSirqIsr(
29876+SK_AC *pAC, /* Adapter Context */
29877+SK_IOC IoC, /* I/O Context */
29878 SK_U32 Istatus) /* Interrupt status word */
29879 {
29880 SK_EVPARA Para;
29881 SK_U32 RegVal32; /* Read register value */
29882 SK_GEPORT *pPrt; /* GIni Port struct pointer */
29883- SK_U16 PhyInt;
29884+ SK_U16 PhyInt;
29885 int i;
29886
29887 if (((Istatus & IS_HW_ERR) & pAC->GIni.GIValIrqMask) != 0) {
29888 /* read the HW Error Interrupt source */
29889 SK_IN32(IoC, B0_HWE_ISRC, &RegVal32);
29890-
29891- SkGeHwErr(pAC, IoC, RegVal32);
29892+
29893+ SkGeYuHwErr(pAC, IoC, RegVal32);
29894 }
29895
29896 /*
29897@@ -569,7 +844,7 @@
29898 }
29899
29900 if (((Istatus & (IS_PA_TO_RX2 | IS_PA_TO_TX2)) != 0) &&
29901- pAC->GIni.GP[MAC_2].PState == SK_PRT_RESET) {
29902+ pAC->GIni.GP[MAC_2].PState == SK_PRT_RESET) {
29903 /* MAC 2 was not initialized but Packet timeout occured */
29904 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E005,
29905 SKERR_SIRQ_E005MSG);
29906@@ -590,8 +865,8 @@
29907 }
29908
29909 if ((Istatus & IS_PA_TO_TX1) != 0) {
29910-
29911- pPrt = &pAC->GIni.GP[0];
29912+
29913+ pPrt = &pAC->GIni.GP[MAC_1];
29914
29915 /* May be a normal situation in a server with a slow network */
29916 SK_OUT16(IoC, B3_PA_CTRL, PA_CLR_TO_TX1);
29917@@ -612,17 +887,18 @@
29918 * we ignore those
29919 */
29920 pPrt->HalfDupTimerActive = SK_TRUE;
29921+
29922 /* Snap statistic counters */
29923 (void)SkXmUpdateStats(pAC, IoC, 0);
29924
29925 (void)SkXmMacStatistic(pAC, IoC, 0, XM_TXO_OK_HI, &RegVal32);
29926
29927 pPrt->LastOctets = (SK_U64)RegVal32 << 32;
29928-
29929+
29930 (void)SkXmMacStatistic(pAC, IoC, 0, XM_TXO_OK_LO, &RegVal32);
29931
29932 pPrt->LastOctets += RegVal32;
29933-
29934+
29935 Para.Para32[0] = 0;
29936 SkTimerStart(pAC, IoC, &pPrt->HalfDupChkTimer, SK_HALFDUP_CHK_TIME,
29937 SKGE_HWAC, SK_HWEV_HALFDUP_CHK, Para);
29938@@ -632,8 +908,8 @@
29939 }
29940
29941 if ((Istatus & IS_PA_TO_TX2) != 0) {
29942-
29943- pPrt = &pAC->GIni.GP[1];
29944+
29945+ pPrt = &pAC->GIni.GP[MAC_2];
29946
29947 /* May be a normal situation in a server with a slow network */
29948 SK_OUT16(IoC, B3_PA_CTRL, PA_CLR_TO_TX2);
29949@@ -645,17 +921,18 @@
29950 pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOHALF) &&
29951 !pPrt->HalfDupTimerActive) {
29952 pPrt->HalfDupTimerActive = SK_TRUE;
29953+
29954 /* Snap statistic counters */
29955 (void)SkXmUpdateStats(pAC, IoC, 1);
29956
29957 (void)SkXmMacStatistic(pAC, IoC, 1, XM_TXO_OK_HI, &RegVal32);
29958
29959 pPrt->LastOctets = (SK_U64)RegVal32 << 32;
29960-
29961+
29962 (void)SkXmMacStatistic(pAC, IoC, 1, XM_TXO_OK_LO, &RegVal32);
29963
29964 pPrt->LastOctets += RegVal32;
29965-
29966+
29967 Para.Para32[0] = 1;
29968 SkTimerStart(pAC, IoC, &pPrt->HalfDupChkTimer, SK_HALFDUP_CHK_TIME,
29969 SKGE_HWAC, SK_HWEV_HALFDUP_CHK, Para);
29970@@ -668,6 +945,7 @@
29971 if ((Istatus & IS_R1_C) != 0) {
29972 /* Clear IRQ */
29973 SK_OUT32(IoC, B0_R1_CSR, CSR_IRQ_CL_C);
29974+
29975 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E006,
29976 SKERR_SIRQ_E006MSG);
29977 Para.Para64 = MAC_1;
29978@@ -679,6 +957,7 @@
29979 if ((Istatus & IS_R2_C) != 0) {
29980 /* Clear IRQ */
29981 SK_OUT32(IoC, B0_R2_CSR, CSR_IRQ_CL_C);
29982+
29983 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E007,
29984 SKERR_SIRQ_E007MSG);
29985 Para.Para64 = MAC_2;
29986@@ -690,6 +969,7 @@
29987 if ((Istatus & IS_XS1_C) != 0) {
29988 /* Clear IRQ */
29989 SK_OUT32(IoC, B0_XS1_CSR, CSR_IRQ_CL_C);
29990+
29991 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E008,
29992 SKERR_SIRQ_E008MSG);
29993 Para.Para64 = MAC_1;
29994@@ -701,6 +981,7 @@
29995 if ((Istatus & IS_XA1_C) != 0) {
29996 /* Clear IRQ */
29997 SK_OUT32(IoC, B0_XA1_CSR, CSR_IRQ_CL_C);
29998+
29999 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E009,
30000 SKERR_SIRQ_E009MSG);
30001 Para.Para64 = MAC_1;
30002@@ -712,6 +993,7 @@
30003 if ((Istatus & IS_XS2_C) != 0) {
30004 /* Clear IRQ */
30005 SK_OUT32(IoC, B0_XS2_CSR, CSR_IRQ_CL_C);
30006+
30007 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E010,
30008 SKERR_SIRQ_E010MSG);
30009 Para.Para64 = MAC_2;
30010@@ -723,6 +1005,7 @@
30011 if ((Istatus & IS_XA2_C) != 0) {
30012 /* Clear IRQ */
30013 SK_OUT32(IoC, B0_XA2_CSR, CSR_IRQ_CL_C);
30014+
30015 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E011,
30016 SKERR_SIRQ_E011MSG);
30017 Para.Para64 = MAC_2;
30018@@ -735,39 +1018,37 @@
30019 if ((Istatus & IS_EXT_REG) != 0) {
30020 /* Test IRQs from PHY */
30021 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
30022-
30023+
30024 pPrt = &pAC->GIni.GP[i];
30025-
30026+
30027 if (pPrt->PState == SK_PRT_RESET) {
30028 continue;
30029 }
30030-
30031+
30032 #ifdef GENESIS
30033 if (pAC->GIni.GIGenesis) {
30034-
30035+
30036 switch (pPrt->PhyType) {
30037-
30038+
30039 case SK_PHY_XMAC:
30040 break;
30041-
30042+
30043 case SK_PHY_BCOM:
30044 SkXmPhyRead(pAC, IoC, i, PHY_BCOM_INT_STAT, &PhyInt);
30045-
30046+
30047 if ((PhyInt & ~PHY_B_DEF_MSK) != 0) {
30048 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
30049- ("Port %d Bcom Int: 0x%04X\n",
30050- i, PhyInt));
30051+ ("Port %d PHY Int: 0x%04X\n", i, PhyInt));
30052 SkPhyIsrBcom(pAC, IoC, i, PhyInt);
30053 }
30054 break;
30055 #ifdef OTHER_PHY
30056 case SK_PHY_LONE:
30057 SkXmPhyRead(pAC, IoC, i, PHY_LONE_INT_STAT, &PhyInt);
30058-
30059+
30060 if ((PhyInt & PHY_L_DEF_MSK) != 0) {
30061 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
30062- ("Port %d Lone Int: %x\n",
30063- i, PhyInt));
30064+ ("Port %d PHY Int: 0x%04X\n", i, PhyInt));
30065 SkPhyIsrLone(pAC, IoC, i, PhyInt);
30066 }
30067 break;
30068@@ -775,7 +1056,7 @@
30069 }
30070 }
30071 #endif /* GENESIS */
30072-
30073+
30074 #ifdef YUKON
30075 if (pAC->GIni.GIYukon) {
30076 /* Read PHY Interrupt Status */
30077@@ -783,8 +1064,7 @@
30078
30079 if ((PhyInt & PHY_M_DEF_MSK) != 0) {
30080 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
30081- ("Port %d Marv Int: 0x%04X\n",
30082- i, PhyInt));
30083+ ("Port %d PHY Int: 0x%04X\n", i, PhyInt));
30084 SkPhyIsrGmac(pAC, IoC, i, PhyInt);
30085 }
30086 }
30087@@ -792,13 +1072,13 @@
30088 }
30089 }
30090
30091- /* I2C Ready interrupt */
30092+ /* TWSI Ready interrupt */
30093 if ((Istatus & IS_I2C_READY) != 0) {
30094 #ifdef SK_SLIM
30095- SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
30096-#else
30097+ SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
30098+#else
30099 SkI2cIsr(pAC, IoC);
30100-#endif
30101+#endif
30102 }
30103
30104 /* SW forced interrupt */
30105@@ -813,7 +1093,7 @@
30106 * us only a link going down.
30107 */
30108 /* clear interrupt */
30109- SK_OUT8(IoC, MR_ADDR(MAC_1, LNK_SYNC_CTRL), LED_CLR_IRQ);
30110+ SK_OUT8(IoC, MR_ADDR(MAC_1, LNK_SYNC_CTRL), LNK_CLR_IRQ);
30111 }
30112
30113 /* Check MAC after link sync counter */
30114@@ -828,7 +1108,7 @@
30115 * us only a link going down.
30116 */
30117 /* clear interrupt */
30118- SK_OUT8(IoC, MR_ADDR(MAC_2, LNK_SYNC_CTRL), LED_CLR_IRQ);
30119+ SK_OUT8(IoC, MR_ADDR(MAC_2, LNK_SYNC_CTRL), LNK_CLR_IRQ);
30120 }
30121
30122 /* Check MAC after link sync counter */
30123@@ -844,13 +1124,201 @@
30124 /* read the HW Error Interrupt source */
30125 SK_IN32(IoC, B0_HWE_ISRC, &RegVal32);
30126
30127- SkGeHwErr(pAC, IoC, RegVal32);
30128+ SkGeYuHwErr(pAC, IoC, RegVal32);
30129 }
30130
30131 SkHwtIsr(pAC, IoC);
30132 }
30133
30134-} /* SkGeSirqIsr */
30135+} /* SkGeYuSirqIsr */
30136+
30137+#ifdef YUK2
30138+/******************************************************************************
30139+ *
30140+ * SkYuk2PortSirq() - Service HW Errors for specified port (Yukon-2 only)
30141+ *
30142+ * Description: handles the HW Error interrupts for a specific port.
30143+ *
30144+ * Returns: N/A
30145+ */
30146+static void SkYuk2PortSirq(
30147+SK_AC *pAC, /* Adapter Context */
30148+SK_IOC IoC, /* I/O Context */
30149+SK_U32 IStatus, /* Interrupt status word */
30150+int Port) /* Port Index (MAC_1 + n) */
30151+{
30152+ SK_EVPARA Para;
30153+ int Queue;
30154+ SK_U16 PhyInt;
30155+
30156+ if (Port == MAC_2) {
30157+ IStatus >>= 8;
30158+ }
30159+
30160+ /* Interrupt from PHY */
30161+ if ((IStatus & Y2_IS_IRQ_PHY1) != 0) {
30162+ /* Read PHY Interrupt Status */
30163+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_INT_STAT, &PhyInt);
30164+
30165+ if ((PhyInt & PHY_M_DEF_MSK) != 0) {
30166+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
30167+ ("Port %d PHY Int: 0x%04X\n", Port, PhyInt));
30168+ SkPhyIsrGmac(pAC, IoC, Port, PhyInt);
30169+ }
30170+ }
30171+
30172+ /* Interrupt from MAC */
30173+ if ((IStatus & Y2_IS_IRQ_MAC1) != 0) {
30174+ SkMacIrq(pAC, IoC, Port);
30175+ }
30176+
30177+ if ((IStatus & (Y2_IS_CHK_RX1 | Y2_IS_CHK_TXS1 | Y2_IS_CHK_TXA1)) != 0) {
30178+ if ((IStatus & Y2_IS_CHK_RX1) != 0) {
30179+ if (Port == MAC_1) {
30180+ Queue = Q_R1;
30181+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E006,
30182+ SKERR_SIRQ_E006MSG);
30183+ }
30184+ else {
30185+ Queue = Q_R2;
30186+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E007,
30187+ SKERR_SIRQ_E007MSG);
30188+ }
30189+ /* Clear IRQ */
30190+ SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_CHK);
30191+ }
30192+
30193+ if ((IStatus & Y2_IS_CHK_TXS1) != 0) {
30194+ if (Port == MAC_1) {
30195+ Queue = Q_XS1;
30196+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E008,
30197+ SKERR_SIRQ_E008MSG);
30198+ }
30199+ else {
30200+ Queue = Q_XS2;
30201+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E010,
30202+ SKERR_SIRQ_E010MSG);
30203+ }
30204+ /* Clear IRQ */
30205+ SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_CHK);
30206+ }
30207+
30208+ if ((IStatus & Y2_IS_CHK_TXA1) != 0) {
30209+ if (Port == MAC_1) {
30210+ Queue = Q_XA1;
30211+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E009,
30212+ SKERR_SIRQ_E009MSG);
30213+ }
30214+ else {
30215+ Queue = Q_XA2;
30216+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E011,
30217+ SKERR_SIRQ_E011MSG);
30218+ }
30219+ /* Clear IRQ */
30220+ SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_CHK);
30221+ }
30222+
30223+ Para.Para64 = Port;
30224+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
30225+
30226+ Para.Para32[0] = Port;
30227+ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
30228+ }
30229+} /* SkYuk2PortSirq */
30230+#endif /* YUK2 */
30231+
30232+/******************************************************************************
30233+ *
30234+ * SkYuk2SirqIsr() - Special Interrupt Service Routine (Yukon-2 only)
30235+ *
30236+ * Description: handles all non data transfer specific interrupts (slow path)
30237+ *
30238+ * Returns: N/A
30239+ */
30240+void SkYuk2SirqIsr(
30241+SK_AC *pAC, /* Adapter Context */
30242+SK_IOC IoC, /* I/O Context */
30243+SK_U32 Istatus) /* Interrupt status word */
30244+{
30245+#ifdef YUK2
30246+ SK_EVPARA Para;
30247+ SK_U32 RegVal32; /* Read register value */
30248+ SK_U8 Value;
30249+
30250+ /* HW Error indicated ? */
30251+ if (((Istatus & Y2_IS_HW_ERR) & pAC->GIni.GIValIrqMask) != 0) {
30252+ /* read the HW Error Interrupt source */
30253+ SK_IN32(IoC, B0_HWE_ISRC, &RegVal32);
30254+
30255+ SkYuk2HwErr(pAC, IoC, RegVal32);
30256+ }
30257+
30258+ /* Interrupt from ASF Subsystem */
30259+ if ((Istatus & Y2_IS_ASF) != 0) {
30260+ /* clear IRQ */
30261+ /* later on clearing should be done in ASF ISR handler */
30262+ SK_IN8(IoC, B28_Y2_ASF_STAT_CMD, &Value);
30263+ Value |= Y2_ASF_CLR_HSTI;
30264+ SK_OUT8(IoC, B28_Y2_ASF_STAT_CMD, Value);
30265+ /* Call IRQ handler in ASF Module */
30266+ /* TBD */
30267+ }
30268+
30269+ /* Check IRQ from polling unit */
30270+ if ((Istatus & Y2_IS_POLL_CHK) != 0) {
30271+ /* Clear IRQ */
30272+ SK_OUT32(IoC, POLL_CTRL, PC_CLR_IRQ_CHK);
30273+
30274+ SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E036,
30275+ SKERR_SIRQ_E036MSG);
30276+ Para.Para64 = 0;
30277+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
30278+ }
30279+
30280+ /* TWSI Ready interrupt */
30281+ if ((Istatus & Y2_IS_TWSI_RDY) != 0) {
30282+#ifdef SK_SLIM
30283+ SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
30284+#else
30285+ SkI2cIsr(pAC, IoC);
30286+#endif
30287+ }
30288+
30289+ /* SW forced interrupt */
30290+ if ((Istatus & Y2_IS_IRQ_SW) != 0) {
30291+ /* clear the software IRQ */
30292+ SK_OUT8(IoC, B0_CTST, CS_CL_SW_IRQ);
30293+ }
30294+
30295+ if ((Istatus & Y2_IS_L1_MASK) != 0) {
30296+ SkYuk2PortSirq(pAC, IoC, Istatus, MAC_1);
30297+ }
30298+
30299+ if ((Istatus & Y2_IS_L2_MASK) != 0) {
30300+ SkYuk2PortSirq(pAC, IoC, Istatus, MAC_2);
30301+ }
30302+
30303+ /* Timer interrupt (served last) */
30304+ if ((Istatus & Y2_IS_TIMINT) != 0) {
30305+
30306+ if (((Istatus & Y2_IS_HW_ERR) & ~pAC->GIni.GIValIrqMask) != 0) {
30307+ /* read the HW Error Interrupt source */
30308+ SK_IN32(IoC, B0_HWE_ISRC, &RegVal32);
30309+
30310+ /* otherwise we would generate error log entries periodically */
30311+ RegVal32 &= pAC->GIni.GIValHwIrqMask;
30312+ if (RegVal32 != 0) {
30313+ SkYuk2HwErr(pAC, IoC, RegVal32);
30314+ }
30315+ }
30316+
30317+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
30318+ ("Timer Int: 0x%08lX\n", Istatus));
30319+ SkHwtIsr(pAC, IoC);
30320+ }
30321+#endif /* YUK2 */
30322+
30323+} /* SkYuk2SirqIsr */
30324
30325
30326 #ifdef GENESIS
30327@@ -864,8 +1332,8 @@
30328 */
30329 static int SkGePortCheckShorts(
30330 SK_AC *pAC, /* Adapter Context */
30331-SK_IOC IoC, /* IO Context */
30332-int Port) /* Which port should be checked */
30333+SK_IOC IoC, /* I/O Context */
30334+int Port) /* Port Index (MAC_1 + n) */
30335 {
30336 SK_U32 Shorts; /* Short Event Counter */
30337 SK_U32 CheckShorts; /* Check value for Short Event Counter */
30338@@ -893,9 +1361,9 @@
30339 RxCts = 0;
30340
30341 for (i = 0; i < sizeof(SkGeRxRegs)/sizeof(SkGeRxRegs[0]); i++) {
30342-
30343+
30344 (void)SkXmMacStatistic(pAC, IoC, Port, SkGeRxRegs[i], &RxTmp);
30345-
30346+
30347 RxCts += (SK_U64)RxTmp;
30348 }
30349
30350@@ -912,11 +1380,11 @@
30351 CheckShorts = 2;
30352
30353 (void)SkXmMacStatistic(pAC, IoC, Port, XM_RXF_FCS_ERR, &FcsErrCts);
30354-
30355- if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE &&
30356- pPrt->PLipaAutoNeg == SK_LIPA_UNKNOWN &&
30357- (pPrt->PLinkMode == SK_LMODE_HALF ||
30358- pPrt->PLinkMode == SK_LMODE_FULL)) {
30359+
30360+ if (pPrt->PLinkModeConf == (SK_U8)SK_LMODE_AUTOSENSE &&
30361+ pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_UNKNOWN &&
30362+ (pPrt->PLinkMode == (SK_U8)SK_LMODE_HALF ||
30363+ pPrt->PLinkMode == (SK_U8)SK_LMODE_FULL)) {
30364 /*
30365 * This is autosensing and we are in the fallback
30366 * manual full/half duplex mode.
30367@@ -925,16 +1393,16 @@
30368 /* Nothing received, restart link */
30369 pPrt->PPrevFcs = FcsErrCts;
30370 pPrt->PPrevShorts = Shorts;
30371-
30372+
30373 return(SK_HW_PS_RESTART);
30374 }
30375 else {
30376- pPrt->PLipaAutoNeg = SK_LIPA_MANUAL;
30377+ pPrt->PLipaAutoNeg = (SK_U8)SK_LIPA_MANUAL;
30378 }
30379 }
30380
30381 if (((RxCts - pPrt->PPrevRx) > pPrt->PRxLim) ||
30382- (!(FcsErrCts - pPrt->PPrevFcs))) {
30383+ (!(FcsErrCts - pPrt->PPrevFcs))) {
30384 /*
30385 * Note: The compare with zero above has to be done the way shown,
30386 * otherwise the Linux driver will have a problem.
30387@@ -979,29 +1447,25 @@
30388 */
30389 static int SkGePortCheckUp(
30390 SK_AC *pAC, /* Adapter Context */
30391-SK_IOC IoC, /* IO Context */
30392-int Port) /* Which port should be checked */
30393+SK_IOC IoC, /* I/O Context */
30394+int Port) /* Port Index (MAC_1 + n) */
30395 {
30396 SK_GEPORT *pPrt; /* GIni Port struct pointer */
30397 SK_BOOL AutoNeg; /* Is Auto-negotiation used ? */
30398 int Rtv; /* Return value */
30399
30400 Rtv = SK_HW_PS_NONE;
30401-
30402+
30403 pPrt = &pAC->GIni.GP[Port];
30404
30405- if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
30406- AutoNeg = SK_FALSE;
30407- }
30408- else {
30409- AutoNeg = SK_TRUE;
30410- }
30411+ AutoNeg = pPrt->PLinkMode != SK_LMODE_HALF &&
30412+ pPrt->PLinkMode != SK_LMODE_FULL;
30413
30414 #ifdef GENESIS
30415 if (pAC->GIni.GIGenesis) {
30416
30417 switch (pPrt->PhyType) {
30418-
30419+
30420 case SK_PHY_XMAC:
30421 Rtv = SkGePortCheckUpXmac(pAC, IoC, Port, AutoNeg);
30422 break;
30423@@ -1019,15 +1483,15 @@
30424 }
30425 }
30426 #endif /* GENESIS */
30427-
30428+
30429 #ifdef YUKON
30430 if (pAC->GIni.GIYukon) {
30431-
30432+
30433 Rtv = SkGePortCheckUpGmac(pAC, IoC, Port, AutoNeg);
30434 }
30435 #endif /* YUKON */
30436
30437- return(Rtv);
30438+ return(Rtv);
30439 } /* SkGePortCheckUp */
30440
30441
30442@@ -1043,8 +1507,8 @@
30443 */
30444 static int SkGePortCheckUpXmac(
30445 SK_AC *pAC, /* Adapter Context */
30446-SK_IOC IoC, /* IO Context */
30447-int Port, /* Which port should be checked */
30448+SK_IOC IoC, /* I/O Context */
30449+int Port, /* Port Index (MAC_1 + n) */
30450 SK_BOOL AutoNeg) /* Is Auto-negotiation used ? */
30451 {
30452 SK_U32 Shorts; /* Short Event Counter */
30453@@ -1082,7 +1546,7 @@
30454 XM_IN16(IoC, Port, XM_ISRC, &Isrc);
30455 IsrcSum |= Isrc;
30456 SkXmAutoNegLipaXmac(pAC, IoC, Port, IsrcSum);
30457-
30458+
30459 if ((Isrc & XM_IS_INP_ASS) == 0) {
30460 /* It has been in sync since last time */
30461 /* Restart the PORT */
30462@@ -1101,14 +1565,14 @@
30463 * Link Restart Workaround:
30464 * it may be possible that the other Link side
30465 * restarts its link as well an we detect
30466- * another LinkBroken. To prevent this
30467+ * another PLinkBroken. To prevent this
30468 * happening we check for a maximum number
30469 * of consecutive restart. If those happens,
30470 * we do NOT restart the active link and
30471 * check whether the link is now o.k.
30472 */
30473 pPrt->PLinkResCt++;
30474-
30475+
30476 pPrt->PAutoNegTimeOut = 0;
30477
30478 if (pPrt->PLinkResCt < SK_MAX_LRESTART) {
30479@@ -1116,13 +1580,13 @@
30480 }
30481
30482 pPrt->PLinkResCt = 0;
30483-
30484+
30485 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30486 ("Do NOT restart on Port %d %x %x\n", Port, Isrc, IsrcSum));
30487 }
30488 else {
30489 pPrt->PIsave = (SK_U16)(IsrcSum & XM_IS_AND);
30490-
30491+
30492 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30493 ("Save Sync/nosync Port %d %x %x\n", Port, Isrc, IsrcSum));
30494
30495@@ -1149,7 +1613,7 @@
30496 if ((Isrc & XM_IS_INP_ASS) != 0) {
30497 pPrt->PLinkBroken = SK_TRUE;
30498 /* Re-Init Link partner Autoneg flag */
30499- pPrt->PLipaAutoNeg = SK_LIPA_UNKNOWN;
30500+ pPrt->PLipaAutoNeg = (SK_U8)SK_LIPA_UNKNOWN;
30501 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
30502 ("Link broken Port %d\n", Port));
30503
30504@@ -1162,7 +1626,7 @@
30505 }
30506 else {
30507 SkXmAutoNegLipaXmac(pAC, IoC, Port, Isrc);
30508-
30509+
30510 if (SkGePortCheckShorts(pAC, IoC, Port) == SK_HW_PS_RESTART) {
30511 return(SK_HW_PS_RESTART);
30512 }
30513@@ -1178,7 +1642,7 @@
30514 IsrcSum |= Isrc;
30515
30516 SkXmAutoNegLipaXmac(pAC, IoC, Port, IsrcSum);
30517-
30518+
30519 if ((GpReg & XM_GP_INP_ASS) != 0 || (IsrcSum & XM_IS_INP_ASS) != 0) {
30520 if ((GpReg & XM_GP_INP_ASS) == 0) {
30521 /* Save Auto-negotiation Done interrupt only if link is in sync */
30522@@ -1194,20 +1658,26 @@
30523 }
30524
30525 if (AutoNeg) {
30526+ /* Auto-Negotiation Done ? */
30527 if ((IsrcSum & XM_IS_AND) != 0) {
30528+
30529 SkHWLinkUp(pAC, IoC, Port);
30530+
30531 Done = SkMacAutoNegDone(pAC, IoC, Port);
30532+
30533 if (Done != SK_AND_OK) {
30534 /* Get PHY parameters, for debugging only */
30535 SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_AUNE_LP, &LpAb);
30536 SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_RES_ABI, &ResAb);
30537- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30538+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
30539 ("AutoNeg FAIL Port %d (LpAb %x, ResAb %x)\n",
30540- Port, LpAb, ResAb));
30541-
30542+ Port, LpAb, ResAb));
30543+
30544 /* Try next possible mode */
30545 NextMode = SkHWSenseGetNext(pAC, IoC, Port);
30546+
30547 SkHWLinkDown(pAC, IoC, Port);
30548+
30549 if (Done == SK_AND_DUP_CAP) {
30550 /* GoTo next mode */
30551 SkHWSenseSetNext(pAC, IoC, Port, NextMode);
30552@@ -1220,42 +1690,41 @@
30553 * (clear Page Received bit if set)
30554 */
30555 SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_AUNE_EXP, &ExtStat);
30556-
30557+
30558 return(SK_HW_PS_LINK);
30559 }
30560-
30561+
30562 /* AutoNeg not done, but HW link is up. Check for timeouts */
30563- pPrt->PAutoNegTimeOut++;
30564- if (pPrt->PAutoNegTimeOut >= SK_AND_MAX_TO) {
30565+ if (pPrt->PAutoNegTimeOut++ >= SK_AND_MAX_TO) {
30566 /* Increase the Timeout counter */
30567 pPrt->PAutoNegTOCt++;
30568
30569 /* Timeout occured */
30570 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
30571 ("AutoNeg timeout Port %d\n", Port));
30572- if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE &&
30573- pPrt->PLipaAutoNeg != SK_LIPA_AUTO) {
30574+ if (pPrt->PLinkModeConf == (SK_U8)SK_LMODE_AUTOSENSE &&
30575+ pPrt->PLipaAutoNeg != (SK_U8)SK_LIPA_AUTO) {
30576 /* Set Link manually up */
30577 SkHWSenseSetNext(pAC, IoC, Port, SK_LMODE_FULL);
30578 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
30579 ("Set manual full duplex Port %d\n", Port));
30580 }
30581
30582- if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE &&
30583- pPrt->PLipaAutoNeg == SK_LIPA_AUTO &&
30584+ if (pPrt->PLinkModeConf == (SK_U8)SK_LMODE_AUTOSENSE &&
30585+ pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_AUTO &&
30586 pPrt->PAutoNegTOCt >= SK_MAX_ANEG_TO) {
30587 /*
30588 * This is rather complicated.
30589 * we need to check here whether the LIPA_AUTO
30590 * we saw before is false alert. We saw at one
30591- * switch ( SR8800) that on boot time it sends
30592+ * switch (SR8800) that on boot time it sends
30593 * just one auto-neg packet and does no further
30594 * auto-negotiation.
30595 * Solution: we restart the autosensing after
30596 * a few timeouts.
30597 */
30598 pPrt->PAutoNegTOCt = 0;
30599- pPrt->PLipaAutoNeg = SK_LIPA_UNKNOWN;
30600+ pPrt->PLipaAutoNeg = (SK_U8)SK_LIPA_UNKNOWN;
30601 SkHWInitDefSense(pAC, IoC, Port);
30602 }
30603
30604@@ -1266,18 +1735,18 @@
30605 else {
30606 /* Link is up and we don't need more */
30607 #ifdef DEBUG
30608- if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) {
30609- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30610+ if (pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_AUTO) {
30611+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
30612 ("ERROR: Lipa auto detected on port %d\n", Port));
30613 }
30614 #endif /* DEBUG */
30615 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
30616 ("Link sync(GP), Port %d\n", Port));
30617 SkHWLinkUp(pAC, IoC, Port);
30618-
30619+
30620 /*
30621- * Link sync (GP) and so assume a good connection. But if not received
30622- * a bunch of frames received in a time slot (maybe broken tx cable)
30623+ * Link sync (GP) and so assume a good connection. But if no
30624+ * bunch of frames received in a time slot (maybe broken Tx cable)
30625 * the port is restart.
30626 */
30627 return(SK_HW_PS_LINK);
30628@@ -1298,14 +1767,14 @@
30629 */
30630 static int SkGePortCheckUpBcom(
30631 SK_AC *pAC, /* Adapter Context */
30632-SK_IOC IoC, /* IO Context */
30633-int Port, /* Which port should be checked */
30634+SK_IOC IoC, /* I/O Context */
30635+int Port, /* Port Index (MAC_1 + n) */
30636 SK_BOOL AutoNeg) /* Is Auto-negotiation used ? */
30637 {
30638 SK_GEPORT *pPrt; /* GIni Port struct pointer */
30639 int Done;
30640 SK_U16 Isrc; /* Interrupt source register */
30641- SK_U16 PhyStat; /* Phy Status Register */
30642+ SK_U16 PhyStat; /* PHY Status Register */
30643 SK_U16 ResAb; /* Master/Slave resolution */
30644 SK_U16 Ctrl; /* Broadcom control flags */
30645 #ifdef DEBUG
30646@@ -1318,74 +1787,6 @@
30647 /* Check for No HCD Link events (#10523) */
30648 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_STAT, &Isrc);
30649
30650-#ifdef xDEBUG
30651- if ((Isrc & ~(PHY_B_IS_HCT | PHY_B_IS_LCT) ==
30652- (PHY_B_IS_SCR_S_ER | PHY_B_IS_RRS_CHANGE | PHY_B_IS_LRS_CHANGE)) {
30653-
30654- SK_U32 Stat1, Stat2, Stat3;
30655-
30656- Stat1 = 0;
30657- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_MASK, &Stat1);
30658- CMSMPrintString(
30659- pAC->pConfigTable,
30660- MSG_TYPE_RUNTIME_INFO,
30661- "CheckUp1 - Stat: %x, Mask: %x",
30662- (void *)Isrc,
30663- (void *)Stat1);
30664-
30665- Stat1 = 0;
30666- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_CTRL, &Stat1);
30667- Stat2 = 0;
30668- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_STAT, &Stat2);
30669- Stat1 = Stat1 << 16 | Stat2;
30670- Stat2 = 0;
30671- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_ADV, &Stat2);
30672- Stat3 = 0;
30673- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &Stat3);
30674- Stat2 = Stat2 << 16 | Stat3;
30675- CMSMPrintString(
30676- pAC->pConfigTable,
30677- MSG_TYPE_RUNTIME_INFO,
30678- "Ctrl/Stat: %x, AN Adv/LP: %x",
30679- (void *)Stat1,
30680- (void *)Stat2);
30681-
30682- Stat1 = 0;
30683- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_EXP, &Stat1);
30684- Stat2 = 0;
30685- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_EXT_STAT, &Stat2);
30686- Stat1 = Stat1 << 16 | Stat2;
30687- Stat2 = 0;
30688- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_CTRL, &Stat2);
30689- Stat3 = 0;
30690- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &Stat3);
30691- Stat2 = Stat2 << 16 | Stat3;
30692- CMSMPrintString(
30693- pAC->pConfigTable,
30694- MSG_TYPE_RUNTIME_INFO,
30695- "AN Exp/IEEE Ext: %x, 1000T Ctrl/Stat: %x",
30696- (void *)Stat1,
30697- (void *)Stat2);
30698-
30699- Stat1 = 0;
30700- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_CTRL, &Stat1);
30701- Stat2 = 0;
30702- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_STAT, &Stat2);
30703- Stat1 = Stat1 << 16 | Stat2;
30704- Stat2 = 0;
30705- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &Stat2);
30706- Stat3 = 0;
30707- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_STAT, &Stat3);
30708- Stat2 = Stat2 << 16 | Stat3;
30709- CMSMPrintString(
30710- pAC->pConfigTable,
30711- MSG_TYPE_RUNTIME_INFO,
30712- "PHY Ext Ctrl/Stat: %x, Aux Ctrl/Stat: %x",
30713- (void *)Stat1,
30714- (void *)Stat2);
30715- }
30716-#endif /* DEBUG */
30717-
30718 if ((Isrc & (PHY_B_IS_NO_HDCL /* | PHY_B_IS_NO_HDC */)) != 0) {
30719 /*
30720 * Workaround BCom Errata:
30721@@ -1398,14 +1799,6 @@
30722 (SK_U16)(Ctrl & ~PHY_CT_LOOP));
30723 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30724 ("No HCD Link event, Port %d\n", Port));
30725-#ifdef xDEBUG
30726- CMSMPrintString(
30727- pAC->pConfigTable,
30728- MSG_TYPE_RUNTIME_INFO,
30729- "No HCD link event, port %d.",
30730- (void *)Port,
30731- (void *)NULL);
30732-#endif /* DEBUG */
30733 }
30734
30735 /* Not obsolete: link status bit is latched to 0 and autoclearing! */
30736@@ -1415,72 +1808,6 @@
30737 return(SK_HW_PS_NONE);
30738 }
30739
30740-#ifdef xDEBUG
30741- {
30742- SK_U32 Stat1, Stat2, Stat3;
30743-
30744- Stat1 = 0;
30745- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_MASK, &Stat1);
30746- CMSMPrintString(
30747- pAC->pConfigTable,
30748- MSG_TYPE_RUNTIME_INFO,
30749- "CheckUp1a - Stat: %x, Mask: %x",
30750- (void *)Isrc,
30751- (void *)Stat1);
30752-
30753- Stat1 = 0;
30754- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_CTRL, &Stat1);
30755- Stat2 = 0;
30756- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_STAT, &PhyStat);
30757- Stat1 = Stat1 << 16 | PhyStat;
30758- Stat2 = 0;
30759- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_ADV, &Stat2);
30760- Stat3 = 0;
30761- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &Stat3);
30762- Stat2 = Stat2 << 16 | Stat3;
30763- CMSMPrintString(
30764- pAC->pConfigTable,
30765- MSG_TYPE_RUNTIME_INFO,
30766- "Ctrl/Stat: %x, AN Adv/LP: %x",
30767- (void *)Stat1,
30768- (void *)Stat2);
30769-
30770- Stat1 = 0;
30771- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_EXP, &Stat1);
30772- Stat2 = 0;
30773- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_EXT_STAT, &Stat2);
30774- Stat1 = Stat1 << 16 | Stat2;
30775- Stat2 = 0;
30776- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_CTRL, &Stat2);
30777- Stat3 = 0;
30778- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &ResAb);
30779- Stat2 = Stat2 << 16 | ResAb;
30780- CMSMPrintString(
30781- pAC->pConfigTable,
30782- MSG_TYPE_RUNTIME_INFO,
30783- "AN Exp/IEEE Ext: %x, 1000T Ctrl/Stat: %x",
30784- (void *)Stat1,
30785- (void *)Stat2);
30786-
30787- Stat1 = 0;
30788- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_CTRL, &Stat1);
30789- Stat2 = 0;
30790- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_STAT, &Stat2);
30791- Stat1 = Stat1 << 16 | Stat2;
30792- Stat2 = 0;
30793- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &Stat2);
30794- Stat3 = 0;
30795- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_STAT, &Stat3);
30796- Stat2 = Stat2 << 16 | Stat3;
30797- CMSMPrintString(
30798- pAC->pConfigTable,
30799- MSG_TYPE_RUNTIME_INFO,
30800- "PHY Ext Ctrl/Stat: %x, Aux Ctrl/Stat: %x",
30801- (void *)Stat1,
30802- (void *)Stat2);
30803- }
30804-#endif /* DEBUG */
30805-
30806 /*
30807 * Here we usually can check whether the link is in sync and
30808 * auto-negotiation is done.
30809@@ -1489,7 +1816,7 @@
30810 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_STAT, &PhyStat);
30811
30812 SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat);
30813-
30814+
30815 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30816 ("CheckUp Port %d, PhyStat: 0x%04X\n", Port, PhyStat));
30817
30818@@ -1497,88 +1824,62 @@
30819
30820 if ((ResAb & PHY_B_1000S_MSF) != 0) {
30821 /* Error */
30822- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30823- ("Master/Slave Fault port %d\n", Port));
30824-
30825+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
30826+ ("Master/Slave Fault, ResAb: 0x%04X\n", ResAb));
30827+
30828 pPrt->PAutoNegFail = SK_TRUE;
30829 pPrt->PMSStatus = SK_MS_STAT_FAULT;
30830-
30831+
30832 return(SK_HW_PS_RESTART);
30833 }
30834
30835 if ((PhyStat & PHY_ST_LSYNC) == 0) {
30836 return(SK_HW_PS_NONE);
30837 }
30838-
30839+
30840 pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
30841 SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE;
30842-
30843+
30844 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30845 ("Port %d, ResAb: 0x%04X\n", Port, ResAb));
30846
30847 if (AutoNeg) {
30848+ /* Auto-Negotiation Over ? */
30849 if ((PhyStat & PHY_ST_AN_OVER) != 0) {
30850-
30851+
30852 SkHWLinkUp(pAC, IoC, Port);
30853-
30854+
30855 Done = SkMacAutoNegDone(pAC, IoC, Port);
30856-
30857+
30858 if (Done != SK_AND_OK) {
30859 #ifdef DEBUG
30860 /* Get PHY parameters, for debugging only */
30861 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &LpAb);
30862 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &ExtStat);
30863- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30864+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
30865 ("AutoNeg FAIL Port %d (LpAb %x, 1000TStat %x)\n",
30866 Port, LpAb, ExtStat));
30867 #endif /* DEBUG */
30868 return(SK_HW_PS_RESTART);
30869 }
30870 else {
30871-#ifdef xDEBUG
30872- /* Dummy read ISR to prevent extra link downs/ups */
30873- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_STAT, &ExtStat);
30874-
30875- if ((ExtStat & ~(PHY_B_IS_HCT | PHY_B_IS_LCT)) != 0) {
30876- CMSMPrintString(
30877- pAC->pConfigTable,
30878- MSG_TYPE_RUNTIME_INFO,
30879- "CheckUp2 - Stat: %x",
30880- (void *)ExtStat,
30881- (void *)NULL);
30882- }
30883-#endif /* DEBUG */
30884 return(SK_HW_PS_LINK);
30885 }
30886 }
30887 }
30888 else { /* !AutoNeg */
30889- /* Link is up and we don't need more. */
30890+ /* Link is up and we don't need more */
30891 #ifdef DEBUG
30892- if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) {
30893- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30894+ if (pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_AUTO) {
30895+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
30896 ("ERROR: Lipa auto detected on port %d\n", Port));
30897 }
30898 #endif /* DEBUG */
30899
30900-#ifdef xDEBUG
30901- /* Dummy read ISR to prevent extra link downs/ups */
30902- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_STAT, &ExtStat);
30903-
30904- if ((ExtStat & ~(PHY_B_IS_HCT | PHY_B_IS_LCT)) != 0) {
30905- CMSMPrintString(
30906- pAC->pConfigTable,
30907- MSG_TYPE_RUNTIME_INFO,
30908- "CheckUp3 - Stat: %x",
30909- (void *)ExtStat,
30910- (void *)NULL);
30911- }
30912-#endif /* DEBUG */
30913-
30914 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
30915 ("Link sync(GP), Port %d\n", Port));
30916 SkHWLinkUp(pAC, IoC, Port);
30917-
30918+
30919 return(SK_HW_PS_LINK);
30920 }
30921
30922@@ -1599,17 +1900,18 @@
30923 */
30924 static int SkGePortCheckUpGmac(
30925 SK_AC *pAC, /* Adapter Context */
30926-SK_IOC IoC, /* IO Context */
30927-int Port, /* Which port should be checked */
30928+SK_IOC IoC, /* I/O Context */
30929+int Port, /* Port Index (MAC_1 + n) */
30930 SK_BOOL AutoNeg) /* Is Auto-negotiation used ? */
30931 {
30932 SK_GEPORT *pPrt; /* GIni Port struct pointer */
30933 int Done;
30934- SK_U16 PhyIsrc; /* PHY Interrupt source */
30935- SK_U16 PhyStat; /* PPY Status */
30936+ SK_U16 PhyStat; /* PHY Status */
30937 SK_U16 PhySpecStat;/* PHY Specific Status */
30938 SK_U16 ResAb; /* Master/Slave resolution */
30939+#ifndef SK_SLIM
30940 SK_EVPARA Para;
30941+#endif /* !SK_SLIM */
30942 #ifdef DEBUG
30943 SK_U16 Word; /* I/O helper */
30944 #endif /* DEBUG */
30945@@ -1626,107 +1928,145 @@
30946 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30947 ("CheckUp Port %d, PhyStat: 0x%04X\n", Port, PhyStat));
30948
30949- /* Read PHY Interrupt Status */
30950- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_INT_STAT, &PhyIsrc);
30951+ SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat);
30952
30953- if ((PhyIsrc & PHY_M_IS_AN_COMPL) != 0) {
30954- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30955- ("Auto-Negotiation Completed, PhyIsrc: 0x%04X\n", PhyIsrc));
30956- }
30957+ if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
30958
30959- if ((PhyIsrc & PHY_M_IS_LSP_CHANGE) != 0) {
30960- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30961- ("Link Speed Changed, PhyIsrc: 0x%04X\n", PhyIsrc));
30962- }
30963+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_STAT, &ResAb);
30964
30965- SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat);
30966-
30967- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_STAT, &ResAb);
30968+ if ((ResAb & PHY_B_1000S_MSF) != 0) {
30969+ /* Error */
30970+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
30971+ ("Master/Slave Fault, ResAb: 0x%04X\n", ResAb));
30972
30973- if ((ResAb & PHY_B_1000S_MSF) != 0) {
30974- /* Error */
30975- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30976- ("Master/Slave Fault port %d\n", Port));
30977-
30978- pPrt->PAutoNegFail = SK_TRUE;
30979- pPrt->PMSStatus = SK_MS_STAT_FAULT;
30980-
30981- return(SK_HW_PS_RESTART);
30982+ pPrt->PAutoNegFail = SK_TRUE;
30983+ pPrt->PMSStatus = SK_MS_STAT_FAULT;
30984+
30985+ return(SK_HW_PS_RESTART);
30986+ }
30987 }
30988
30989 /* Read PHY Specific Status */
30990 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &PhySpecStat);
30991-
30992+
30993 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
30994 ("Phy1000BT: 0x%04X, PhySpecStat: 0x%04X\n", ResAb, PhySpecStat));
30995
30996-#ifdef DEBUG
30997+#if (defined(DEBUG) && !defined(SK_SLIM))
30998+ /* Read PHY Auto-Negotiation Expansion */
30999 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_EXP, &Word);
31000
31001- if ((PhyIsrc & PHY_M_IS_AN_PR) != 0 || (Word & PHY_ANE_RX_PG) != 0 ||
31002- (PhySpecStat & PHY_M_PS_PAGE_REC) != 0) {
31003+ if (pAC->GIni.GICopperType && (Word & PHY_ANE_LP_CAP) == 0) {
31004+
31005+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
31006+ ("Link Partner not Auto-Neg. able, AN Exp.: 0x%04X\n", Word));
31007+ }
31008+
31009+ if ((Word & PHY_ANE_RX_PG) != 0 ||
31010+ (PhySpecStat & PHY_M_PS_PAGE_REC) != 0) {
31011 /* Read PHY Next Page Link Partner */
31012 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_NEPG_LP, &Word);
31013
31014 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
31015- ("Page Received, NextPage: 0x%04X\n", Word));
31016+ ("Page received, NextPage: 0x%04X\n", Word));
31017 }
31018-#endif /* DEBUG */
31019+#endif /* DEBUG && !SK_SLIM */
31020
31021 if ((PhySpecStat & PHY_M_PS_LINK_UP) == 0) {
31022+ /* Link down */
31023 return(SK_HW_PS_NONE);
31024 }
31025-
31026- if ((PhySpecStat & PHY_M_PS_DOWNS_STAT) != 0 ||
31027- (PhyIsrc & PHY_M_IS_DOWNSH_DET) != 0) {
31028- /* Downshift detected */
31029- SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E025, SKERR_SIRQ_E025MSG);
31030-
31031- Para.Para64 = Port;
31032- SkEventQueue(pAC, SKGE_DRV, SK_DRV_DOWNSHIFT_DET, Para);
31033-
31034- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
31035- ("Downshift detected, PhyIsrc: 0x%04X\n", PhyIsrc));
31036+
31037+#ifdef XXX
31038+ SK_U16 PhyInt;
31039+ /* Read PHY Interrupt Status */
31040+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_INT_STAT, &PhyInt);
31041+
31042+ /* cross check that the link is really up */
31043+ if ((PhyInt & PHY_M_IS_LST_CHANGE) == 0) {
31044+ /* Link Status unchanged */
31045+ return(SK_HW_PS_NONE);
31046 }
31047+#endif /* XXX */
31048+
31049+#ifndef SK_SLIM
31050+ if (pAC->GIni.GICopperType) {
31051+
31052+ if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
31053+
31054+ if ((PhySpecStat & PHY_M_PS_DOWNS_STAT) != 0) {
31055+ /* Downshift detected */
31056+ Para.Para64 = Port;
31057+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_DOWNSHIFT_DET, Para);
31058+
31059+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
31060+ ("Downshift detected, PhySpecStat: 0x%04X\n", PhySpecStat));
31061+
31062+ SK_ERR_LOG(pAC, SK_ERRCL_CONFIG, SKERR_SIRQ_E025,
31063+ SKERR_SIRQ_E025MSG);
31064+ }
31065+
31066+ pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
31067+ SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE;
31068+ }
31069+
31070+ if ((PhySpecStat & PHY_M_PS_MDI_X_STAT) != 0) {
31071+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
31072+ ("MDI Xover detected, PhyStat: 0x%04X\n", PhySpecStat));
31073+ }
31074+
31075+ /* on PHY 88E1112 & 88E1145 cable length is in Reg. 26, Page 5 */
31076+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL ||
31077+ pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) {
31078+ /* select page 5 to access VCT DSP distance register */
31079+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 5);
31080+
31081+ /* get VCT DSP distance */
31082+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL_2, &PhySpecStat);
31083+
31084+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0);
31085+
31086+ pPrt->PCableLen = (SK_U8)(PhySpecStat & PHY_M_EC2_FO_AM_MSK);
31087+ }
31088+ else {
31089+ pPrt->PCableLen = (SK_U8)((PhySpecStat & PHY_M_PS_CABLE_MSK) >> 7);
31090+ }
31091+ }
31092+#endif /* !SK_SLIM */
31093
31094- pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
31095- SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE;
31096-
31097- pPrt->PCableLen = (SK_U8)((PhySpecStat & PHY_M_PS_CABLE_MSK) >> 7);
31098-
31099 if (AutoNeg) {
31100- /* Auto-Negotiation Over ? */
31101+ /* Auto-Negotiation Complete ? */
31102 if ((PhyStat & PHY_ST_AN_OVER) != 0) {
31103-
31104+
31105 SkHWLinkUp(pAC, IoC, Port);
31106-
31107+
31108 Done = SkMacAutoNegDone(pAC, IoC, Port);
31109-
31110+
31111 if (Done != SK_AND_OK) {
31112 return(SK_HW_PS_RESTART);
31113 }
31114-
31115+
31116 return(SK_HW_PS_LINK);
31117 }
31118 }
31119 else { /* !AutoNeg */
31120- /* Link is up and we don't need more */
31121-#ifdef DEBUG
31122- if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) {
31123- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
31124+#if (defined(DEBUG) && !defined(SK_SLIM))
31125+ if (pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_AUTO) {
31126+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
31127 ("ERROR: Lipa auto detected on port %d\n", Port));
31128 }
31129-#endif /* DEBUG */
31130+#endif /* DEBUG && !SK_SLIM */
31131
31132 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
31133 ("Link sync, Port %d\n", Port));
31134 SkHWLinkUp(pAC, IoC, Port);
31135-
31136+
31137 return(SK_HW_PS_LINK);
31138 }
31139
31140 return(SK_HW_PS_NONE);
31141 } /* SkGePortCheckUpGmac */
31142+
31143 #endif /* YUKON */
31144
31145
31146@@ -1742,8 +2082,8 @@
31147 */
31148 static int SkGePortCheckUpLone(
31149 SK_AC *pAC, /* Adapter Context */
31150-SK_IOC IoC, /* IO Context */
31151-int Port, /* Which port should be checked */
31152+SK_IOC IoC, /* I/O Context */
31153+int Port, /* Port Index (MAC_1 + n) */
31154 SK_BOOL AutoNeg) /* Is Auto-negotiation used ? */
31155 {
31156 SK_GEPORT *pPrt; /* GIni Port struct pointer */
31157@@ -1751,7 +2091,7 @@
31158 SK_U16 Isrc; /* Interrupt source register */
31159 SK_U16 LpAb; /* Link Partner Ability */
31160 SK_U16 ExtStat; /* Extended Status Register */
31161- SK_U16 PhyStat; /* Phy Status Register */
31162+ SK_U16 PhyStat; /* PHY Status Register */
31163 SK_U16 StatSum;
31164 SK_U8 NextMode; /* Next AutoSensing Mode */
31165
31166@@ -1772,7 +2112,7 @@
31167 StatSum |= PhyStat;
31168
31169 SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat);
31170-
31171+
31172 if ((PhyStat & PHY_ST_LSYNC) == 0) {
31173 /* Save Auto-negotiation Done bit */
31174 pPrt->PIsave = (SK_U16)(StatSum & PHY_ST_AN_OVER);
31175@@ -1786,20 +2126,26 @@
31176 }
31177
31178 if (AutoNeg) {
31179+ /* Auto-Negotiation Over ? */
31180 if ((StatSum & PHY_ST_AN_OVER) != 0) {
31181+
31182 SkHWLinkUp(pAC, IoC, Port);
31183+
31184 Done = SkMacAutoNegDone(pAC, IoC, Port);
31185+
31186 if (Done != SK_AND_OK) {
31187 /* Get PHY parameters, for debugging only */
31188 SkXmPhyRead(pAC, IoC, Port, PHY_LONE_AUNE_LP, &LpAb);
31189 SkXmPhyRead(pAC, IoC, Port, PHY_LONE_1000T_STAT, &ExtStat);
31190- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
31191+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
31192 ("AutoNeg FAIL Port %d (LpAb %x, 1000TStat %x)\n",
31193 Port, LpAb, ExtStat));
31194-
31195+
31196 /* Try next possible mode */
31197 NextMode = SkHWSenseGetNext(pAC, IoC, Port);
31198+
31199 SkHWLinkDown(pAC, IoC, Port);
31200+
31201 if (Done == SK_AND_DUP_CAP) {
31202 /* GoTo next mode */
31203 SkHWSenseSetNext(pAC, IoC, Port, NextMode);
31204@@ -1817,15 +2163,14 @@
31205 return(SK_HW_PS_LINK);
31206 }
31207 }
31208-
31209+
31210 /* AutoNeg not done, but HW link is up. Check for timeouts */
31211- pPrt->PAutoNegTimeOut++;
31212- if (pPrt->PAutoNegTimeOut >= SK_AND_MAX_TO) {
31213+ if (pPrt->PAutoNegTimeOut++ >= SK_AND_MAX_TO) {
31214 /* Timeout occured */
31215 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
31216 ("AutoNeg timeout Port %d\n", Port));
31217- if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE &&
31218- pPrt->PLipaAutoNeg != SK_LIPA_AUTO) {
31219+ if (pPrt->PLinkModeConf == (SK_U8)SK_LMODE_AUTOSENSE &&
31220+ pPrt->PLipaAutoNeg != (SK_U8)SK_LIPA_AUTO) {
31221 /* Set Link manually up */
31222 SkHWSenseSetNext(pAC, IoC, Port, SK_LMODE_FULL);
31223 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
31224@@ -1839,8 +2184,8 @@
31225 else {
31226 /* Link is up and we don't need more */
31227 #ifdef DEBUG
31228- if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) {
31229- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
31230+ if (pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_AUTO) {
31231+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
31232 ("ERROR: Lipa auto detected on port %d\n", Port));
31233 }
31234 #endif /* DEBUG */
31235@@ -1850,11 +2195,12 @@
31236 * extra link down/ups
31237 */
31238 SkXmPhyRead(pAC, IoC, Port, PHY_LONE_INT_STAT, &ExtStat);
31239-
31240+
31241 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
31242 ("Link sync(GP), Port %d\n", Port));
31243+
31244 SkHWLinkUp(pAC, IoC, Port);
31245-
31246+
31247 return(SK_HW_PS_LINK);
31248 }
31249
31250@@ -1873,8 +2219,8 @@
31251 */
31252 static int SkGePortCheckUpNat(
31253 SK_AC *pAC, /* Adapter Context */
31254-SK_IOC IoC, /* IO Context */
31255-int Port, /* Which port should be checked */
31256+SK_IOC IoC, /* I/O Context */
31257+int Port, /* Port Index (MAC_1 + n) */
31258 SK_BOOL AutoNeg) /* Is Auto-negotiation used ? */
31259 {
31260 /* todo: National */
31261@@ -1893,38 +2239,40 @@
31262 */
31263 int SkGeSirqEvent(
31264 SK_AC *pAC, /* Adapter Context */
31265-SK_IOC IoC, /* Io Context */
31266+SK_IOC IoC, /* I/O Context */
31267 SK_U32 Event, /* Module specific Event */
31268 SK_EVPARA Para) /* Event specific Parameter */
31269 {
31270 SK_GEPORT *pPrt; /* GIni Port struct pointer */
31271- SK_U32 Port;
31272+ int Port;
31273 SK_U32 Val32;
31274 int PortStat;
31275+#ifndef SK_SLIM
31276 SK_U8 Val8;
31277+#endif
31278 #ifdef GENESIS
31279 SK_U64 Octets;
31280 #endif /* GENESIS */
31281
31282- Port = Para.Para32[0];
31283+ Port = (int)Para.Para32[0];
31284 pPrt = &pAC->GIni.GP[Port];
31285
31286 switch (Event) {
31287 case SK_HWEV_WATIM:
31288 if (pPrt->PState == SK_PRT_RESET) {
31289-
31290+
31291 PortStat = SK_HW_PS_NONE;
31292 }
31293 else {
31294 /* Check whether port came up */
31295- PortStat = SkGePortCheckUp(pAC, IoC, (int)Port);
31296+ PortStat = SkGePortCheckUp(pAC, IoC, Port);
31297 }
31298
31299 switch (PortStat) {
31300 case SK_HW_PS_RESTART:
31301 if (pPrt->PHWLinkUp) {
31302 /* Set Link to down */
31303- SkHWLinkDown(pAC, IoC, (int)Port);
31304+ SkHWLinkDown(pAC, IoC, Port);
31305
31306 /*
31307 * Signal directly to RLMT to ensure correct
31308@@ -1942,22 +2290,28 @@
31309 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_UP, Para);
31310 break;
31311 }
31312-
31313+
31314 /* Start again the check Timer */
31315 if (pPrt->PHWLinkUp) {
31316+
31317 Val32 = SK_WA_ACT_TIME;
31318 }
31319 else {
31320 Val32 = SK_WA_INA_TIME;
31321- }
31322
31323- /* Todo: still needed for non-XMAC PHYs??? */
31324+ if (pAC->GIni.GIYukon) {
31325+ Val32 *= 5;
31326+ }
31327+ }
31328 /* Start workaround Errata #2 timer */
31329 SkTimerStart(pAC, IoC, &pPrt->PWaTimer, Val32,
31330 SKGE_HWAC, SK_HWEV_WATIM, Para);
31331+
31332 break;
31333
31334 case SK_HWEV_PORT_START:
31335+
31336+#ifndef SK_SLIM
31337 if (pPrt->PHWLinkUp) {
31338 /*
31339 * Signal directly to RLMT to ensure correct
31340@@ -1965,8 +2319,9 @@
31341 */
31342 SkRlmtEvent(pAC, IoC, SK_RLMT_LINK_DOWN, Para);
31343 }
31344+#endif /* !SK_SLIM */
31345
31346- SkHWLinkDown(pAC, IoC, (int)Port);
31347+ SkHWLinkDown(pAC, IoC, Port);
31348
31349 /* Schedule Port RESET */
31350 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Para);
31351@@ -1974,9 +2329,11 @@
31352 /* Start workaround Errata #2 timer */
31353 SkTimerStart(pAC, IoC, &pPrt->PWaTimer, SK_WA_INA_TIME,
31354 SKGE_HWAC, SK_HWEV_WATIM, Para);
31355+
31356 break;
31357
31358 case SK_HWEV_PORT_STOP:
31359+#ifndef SK_SLIM
31360 if (pPrt->PHWLinkUp) {
31361 /*
31362 * Signal directly to RLMT to ensure correct
31363@@ -1984,20 +2341,22 @@
31364 */
31365 SkRlmtEvent(pAC, IoC, SK_RLMT_LINK_DOWN, Para);
31366 }
31367+#endif /* !SK_SLIM */
31368
31369 /* Stop Workaround Timer */
31370 SkTimerStop(pAC, IoC, &pPrt->PWaTimer);
31371
31372- SkHWLinkDown(pAC, IoC, (int)Port);
31373+ SkHWLinkDown(pAC, IoC, Port);
31374 break;
31375
31376+#ifndef SK_SLIM
31377 case SK_HWEV_UPDATE_STAT:
31378 /* We do NOT need to update any statistics */
31379 break;
31380
31381 case SK_HWEV_CLEAR_STAT:
31382 /* We do NOT need to clear any statistics */
31383- for (Port = 0; Port < (SK_U32)pAC->GIni.GIMacsFound; Port++) {
31384+ for (Port = 0; Port < pAC->GIni.GIMacsFound; Port++) {
31385 pPrt->PPrevRx = 0;
31386 pPrt->PPrevFcs = 0;
31387 pPrt->PPrevShorts = 0;
31388@@ -2058,6 +2417,7 @@
31389 SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_START, Para);
31390 }
31391 break;
31392+#endif /* !SK_SLIM */
31393
31394 #ifdef GENESIS
31395 case SK_HWEV_HALFDUP_CHK:
31396@@ -2069,17 +2429,18 @@
31397 pPrt->HalfDupTimerActive = SK_FALSE;
31398 if (pPrt->PLinkModeStatus == SK_LMODE_STAT_HALF ||
31399 pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOHALF) {
31400+
31401 /* Snap statistic counters */
31402 (void)SkXmUpdateStats(pAC, IoC, Port);
31403
31404 (void)SkXmMacStatistic(pAC, IoC, Port, XM_TXO_OK_HI, &Val32);
31405
31406 Octets = (SK_U64)Val32 << 32;
31407-
31408+
31409 (void)SkXmMacStatistic(pAC, IoC, Port, XM_TXO_OK_LO, &Val32);
31410
31411 Octets += Val32;
31412-
31413+
31414 if (pPrt->LastOctets == Octets) {
31415 /* Tx hanging, a FIFO flush restarts it */
31416 SkMacFlushTxFifo(pAC, IoC, Port);
31417@@ -2088,7 +2449,7 @@
31418 }
31419 break;
31420 #endif /* GENESIS */
31421-
31422+
31423 default:
31424 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_SIRQ_E001, SKERR_SIRQ_E001MSG);
31425 break;
31426@@ -2109,8 +2470,8 @@
31427 */
31428 static void SkPhyIsrBcom(
31429 SK_AC *pAC, /* Adapter Context */
31430-SK_IOC IoC, /* Io Context */
31431-int Port, /* Port Num = PHY Num */
31432+SK_IOC IoC, /* I/O Context */
31433+int Port, /* Port Index (MAC_1 + n) */
31434 SK_U16 IStatus) /* Interrupt Status */
31435 {
31436 SK_GEPORT *pPrt; /* GIni Port struct pointer */
31437@@ -2123,7 +2484,7 @@
31438 SK_ERR_LOG(pAC, SK_ERRCL_HW | SK_ERRCL_INIT, SKERR_SIRQ_E022,
31439 SKERR_SIRQ_E022MSG);
31440 }
31441-
31442+
31443 if ((IStatus & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) != 0) {
31444
31445 SkHWLinkDown(pAC, IoC, Port);
31446@@ -2152,47 +2513,83 @@
31447 */
31448 static void SkPhyIsrGmac(
31449 SK_AC *pAC, /* Adapter Context */
31450-SK_IOC IoC, /* Io Context */
31451-int Port, /* Port Num = PHY Num */
31452+SK_IOC IoC, /* I/O Context */
31453+int Port, /* Port Index (MAC_1 + n) */
31454 SK_U16 IStatus) /* Interrupt Status */
31455 {
31456- SK_GEPORT *pPrt; /* GIni Port struct pointer */
31457+ SK_GEPORT *pPrt; /* GIni Port struct pointer */
31458 SK_EVPARA Para;
31459+#ifdef XXX
31460 SK_U16 Word;
31461+#endif /* XXX */
31462
31463 pPrt = &pAC->GIni.GP[Port];
31464
31465- if ((IStatus & (PHY_M_IS_AN_PR | PHY_M_IS_LST_CHANGE)) != 0) {
31466-
31467- SkHWLinkDown(pAC, IoC, Port);
31468+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
31469+ ("Port %d PHY IRQ, PhyIsrc: 0x%04X\n", Port, IStatus));
31470
31471- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_ADV, &Word);
31472+ if ((IStatus & PHY_M_IS_LST_CHANGE) != 0) {
31473
31474 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
31475- ("AutoNeg.Adv: 0x%04X\n", Word));
31476-
31477- /* Set Auto-negotiation advertisement */
31478- if (pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM) {
31479- /* restore Asymmetric Pause bit */
31480- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_AUNE_ADV,
31481- (SK_U16)(Word | PHY_M_AN_ASP));
31482- }
31483-
31484+ ("Link Status changed\n"));
31485+
31486 Para.Para32[0] = (SK_U32)Port;
31487- /* Signal to RLMT */
31488- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
31489+
31490+ if (pPrt->PHWLinkUp) {
31491+
31492+ SkHWLinkDown(pAC, IoC, Port);
31493+
31494+#ifdef XXX
31495+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_ADV, &Word);
31496+
31497+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
31498+ ("AutoNeg.Adv: 0x%04X\n", Word));
31499+
31500+ /* Set Auto-negotiation advertisement */
31501+ if (pAC->GIni.GIChipId != CHIP_ID_YUKON_FE &&
31502+ pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM) {
31503+ /* restore Asymmetric Pause bit */
31504+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_AUNE_ADV,
31505+ (SK_U16)(Word | PHY_M_AN_ASP));
31506+ }
31507+#endif /* XXX */
31508+
31509+ /* Signal to RLMT */
31510+ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
31511+ }
31512+ else {
31513+ if ((IStatus & PHY_M_IS_AN_COMPL) != 0) {
31514+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
31515+ ("Auto-Negotiation completed\n"));
31516+ }
31517+
31518+ if ((IStatus & PHY_M_IS_LSP_CHANGE) != 0) {
31519+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
31520+ ("Link Speed changed\n"));
31521+ }
31522+
31523+ SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_WATIM, Para);
31524+ }
31525 }
31526-
31527+
31528 if ((IStatus & PHY_M_IS_AN_ERROR) != 0) {
31529- /* Auto-Negotiation Error */
31530- SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E023, SKERR_SIRQ_E023MSG);
31531+ /* the copper PHY makes 1 retry */
31532+ if (pAC->GIni.GICopperType) {
31533+ /* not logged as error, it might be the first attempt */
31534+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
31535+ ("Auto-Negotiation Error\n"));
31536+ }
31537+ else {
31538+ /* Auto-Negotiation Error */
31539+ SK_ERR_LOG(pAC, SK_ERRCL_CONFIG, SKERR_SIRQ_E023, SKERR_SIRQ_E023MSG);
31540+ }
31541 }
31542-
31543+
31544 if ((IStatus & PHY_M_IS_FIFO_ERROR) != 0) {
31545 /* FIFO Overflow/Underrun Error */
31546 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E024, SKERR_SIRQ_E024MSG);
31547 }
31548-
31549+
31550 } /* SkPhyIsrGmac */
31551 #endif /* YUKON */
31552
31553@@ -2208,14 +2605,14 @@
31554 */
31555 static void SkPhyIsrLone(
31556 SK_AC *pAC, /* Adapter Context */
31557-SK_IOC IoC, /* Io Context */
31558-int Port, /* Port Num = PHY Num */
31559+SK_IOC IoC, /* I/O Context */
31560+int Port, /* Port Index (MAC_1 + n) */
31561 SK_U16 IStatus) /* Interrupt Status */
31562 {
31563 SK_EVPARA Para;
31564
31565 if (IStatus & (PHY_L_IS_DUP | PHY_L_IS_ISOL)) {
31566-
31567+
31568 SkHWLinkDown(pAC, IoC, Port);
31569
31570 Para.Para32[0] = (SK_U32)Port;
31571@@ -2227,3 +2624,4 @@
31572 #endif /* OTHER_PHY */
31573
31574 /* End of File */
31575+
31576diff -urN linux-2.6.17.orig/drivers/net/sk98lin/ski2c.c linux-2.6.17/drivers/net/sk98lin/ski2c.c
31577--- linux-2.6.17.orig/drivers/net/sk98lin/ski2c.c 2006-06-22 13:17:16.000000000 +0200
31578+++ linux-2.6.17/drivers/net/sk98lin/ski2c.c 1970-01-01 01:00:00.000000000 +0100
31579@@ -1,1296 +0,0 @@
31580-/******************************************************************************
31581- *
31582- * Name: ski2c.c
31583- * Project: Gigabit Ethernet Adapters, TWSI-Module
31584- * Version: $Revision$
31585- * Date: $Date$
31586- * Purpose: Functions to access Voltage and Temperature Sensor
31587- *
31588- ******************************************************************************/
31589-
31590-/******************************************************************************
31591- *
31592- * (C)Copyright 1998-2002 SysKonnect.
31593- * (C)Copyright 2002-2003 Marvell.
31594- *
31595- * This program is free software; you can redistribute it and/or modify
31596- * it under the terms of the GNU General Public License as published by
31597- * the Free Software Foundation; either version 2 of the License, or
31598- * (at your option) any later version.
31599- *
31600- * The information in this file is provided "AS IS" without warranty.
31601- *
31602- ******************************************************************************/
31603-
31604-/*
31605- * I2C Protocol
31606- */
31607-#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
31608-static const char SysKonnectFileId[] =
31609- "@(#) $Id$ (C) Marvell. ";
31610-#endif
31611-
31612-#include "h/skdrv1st.h" /* Driver Specific Definitions */
31613-#include "h/lm80.h"
31614-#include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */
31615-
31616-#ifdef __C2MAN__
31617-/*
31618- I2C protocol implementation.
31619-
31620- General Description:
31621-
31622- The I2C protocol is used for the temperature sensors and for
31623- the serial EEPROM which hold the configuration.
31624-
31625- This file covers functions that allow to read write and do
31626- some bulk requests a specified I2C address.
31627-
31628- The Genesis has 2 I2C buses. One for the EEPROM which holds
31629- the VPD Data and one for temperature and voltage sensor.
31630- The following picture shows the I2C buses, I2C devices and
31631- their control registers.
31632-
31633- Note: The VPD functions are in skvpd.c
31634-.
31635-. PCI Config I2C Bus for VPD Data:
31636-.
31637-. +------------+
31638-. | VPD EEPROM |
31639-. +------------+
31640-. |
31641-. | <-- I2C
31642-. |
31643-. +-----------+-----------+
31644-. | |
31645-. +-----------------+ +-----------------+
31646-. | PCI_VPD_ADR_REG | | PCI_VPD_DAT_REG |
31647-. +-----------------+ +-----------------+
31648-.
31649-.
31650-. I2C Bus for LM80 sensor:
31651-.
31652-. +-----------------+
31653-. | Temperature and |
31654-. | Voltage Sensor |
31655-. | LM80 |
31656-. +-----------------+
31657-. |
31658-. |
31659-. I2C --> |
31660-. |
31661-. +----+
31662-. +-------------->| OR |<--+
31663-. | +----+ |
31664-. +------+------+ |
31665-. | | |
31666-. +--------+ +--------+ +----------+
31667-. | B2_I2C | | B2_I2C | | B2_I2C |
31668-. | _CTRL | | _DATA | | _SW |
31669-. +--------+ +--------+ +----------+
31670-.
31671- The I2C bus may be driven by the B2_I2C_SW or by the B2_I2C_CTRL
31672- and B2_I2C_DATA registers.
31673- For driver software it is recommended to use the I2C control and
31674- data register, because I2C bus timing is done by the ASIC and
31675- an interrupt may be received when the I2C request is completed.
31676-
31677- Clock Rate Timing: MIN MAX generated by
31678- VPD EEPROM: 50 kHz 100 kHz HW
31679- LM80 over I2C Ctrl/Data reg. 50 kHz 100 kHz HW
31680- LM80 over B2_I2C_SW register 0 400 kHz SW
31681-
31682- Note: The clock generated by the hardware is dependend on the
31683- PCI clock. If the PCI bus clock is 33 MHz, the I2C/VPD
31684- clock is 50 kHz.
31685- */
31686-intro()
31687-{}
31688-#endif
31689-
31690-#ifdef SK_DIAG
31691-/*
31692- * I2C Fast Mode timing values used by the LM80.
31693- * If new devices are added to the I2C bus the timing values have to be checked.
31694- */
31695-#ifndef I2C_SLOW_TIMING
31696-#define T_CLK_LOW 1300L /* clock low time in ns */
31697-#define T_CLK_HIGH 600L /* clock high time in ns */
31698-#define T_DATA_IN_SETUP 100L /* data in Set-up Time */
31699-#define T_START_HOLD 600L /* start condition hold time */
31700-#define T_START_SETUP 600L /* start condition Set-up time */
31701-#define T_STOP_SETUP 600L /* stop condition Set-up time */
31702-#define T_BUS_IDLE 1300L /* time the bus must free after Tx */
31703-#define T_CLK_2_DATA_OUT 900L /* max. clock low to data output valid */
31704-#else /* I2C_SLOW_TIMING */
31705-/* I2C Standard Mode Timing */
31706-#define T_CLK_LOW 4700L /* clock low time in ns */
31707-#define T_CLK_HIGH 4000L /* clock high time in ns */
31708-#define T_DATA_IN_SETUP 250L /* data in Set-up Time */
31709-#define T_START_HOLD 4000L /* start condition hold time */
31710-#define T_START_SETUP 4700L /* start condition Set-up time */
31711-#define T_STOP_SETUP 4000L /* stop condition Set-up time */
31712-#define T_BUS_IDLE 4700L /* time the bus must free after Tx */
31713-#endif /* !I2C_SLOW_TIMING */
31714-
31715-#define NS2BCLK(x) (((x)*125)/10000)
31716-
31717-/*
31718- * I2C Wire Operations
31719- *
31720- * About I2C_CLK_LOW():
31721- *
31722- * The Data Direction bit (I2C_DATA_DIR) has to be set to input when setting
31723- * clock to low, to prevent the ASIC and the I2C data client from driving the
31724- * serial data line simultaneously (ASIC: last bit of a byte = '1', I2C client
31725- * send an 'ACK'). See also Concentrator Bugreport No. 10192.
31726- */
31727-#define I2C_DATA_HIGH(IoC) SK_I2C_SET_BIT(IoC, I2C_DATA)
31728-#define I2C_DATA_LOW(IoC) SK_I2C_CLR_BIT(IoC, I2C_DATA)
31729-#define I2C_DATA_OUT(IoC) SK_I2C_SET_BIT(IoC, I2C_DATA_DIR)
31730-#define I2C_DATA_IN(IoC) SK_I2C_CLR_BIT(IoC, I2C_DATA_DIR | I2C_DATA)
31731-#define I2C_CLK_HIGH(IoC) SK_I2C_SET_BIT(IoC, I2C_CLK)
31732-#define I2C_CLK_LOW(IoC) SK_I2C_CLR_BIT(IoC, I2C_CLK | I2C_DATA_DIR)
31733-#define I2C_START_COND(IoC) SK_I2C_CLR_BIT(IoC, I2C_CLK)
31734-
31735-#define NS2CLKT(x) ((x*125L)/10000)
31736-
31737-/*--------------- I2C Interface Register Functions --------------- */
31738-
31739-/*
31740- * sending one bit
31741- */
31742-void SkI2cSndBit(
31743-SK_IOC IoC, /* I/O Context */
31744-SK_U8 Bit) /* Bit to send */
31745-{
31746- I2C_DATA_OUT(IoC);
31747- if (Bit) {
31748- I2C_DATA_HIGH(IoC);
31749- }
31750- else {
31751- I2C_DATA_LOW(IoC);
31752- }
31753- SkDgWaitTime(IoC, NS2BCLK(T_DATA_IN_SETUP));
31754- I2C_CLK_HIGH(IoC);
31755- SkDgWaitTime(IoC, NS2BCLK(T_CLK_HIGH));
31756- I2C_CLK_LOW(IoC);
31757-} /* SkI2cSndBit*/
31758-
31759-
31760-/*
31761- * Signal a start to the I2C Bus.
31762- *
31763- * A start is signaled when data goes to low in a high clock cycle.
31764- *
31765- * Ends with Clock Low.
31766- *
31767- * Status: not tested
31768- */
31769-void SkI2cStart(
31770-SK_IOC IoC) /* I/O Context */
31771-{
31772- /* Init data and Clock to output lines */
31773- /* Set Data high */
31774- I2C_DATA_OUT(IoC);
31775- I2C_DATA_HIGH(IoC);
31776- /* Set Clock high */
31777- I2C_CLK_HIGH(IoC);
31778-
31779- SkDgWaitTime(IoC, NS2BCLK(T_START_SETUP));
31780-
31781- /* Set Data Low */
31782- I2C_DATA_LOW(IoC);
31783-
31784- SkDgWaitTime(IoC, NS2BCLK(T_START_HOLD));
31785-
31786- /* Clock low without Data to Input */
31787- I2C_START_COND(IoC);
31788-
31789- SkDgWaitTime(IoC, NS2BCLK(T_CLK_LOW));
31790-} /* SkI2cStart */
31791-
31792-
31793-void SkI2cStop(
31794-SK_IOC IoC) /* I/O Context */
31795-{
31796- /* Init data and Clock to output lines */
31797- /* Set Data low */
31798- I2C_DATA_OUT(IoC);
31799- I2C_DATA_LOW(IoC);
31800-
31801- SkDgWaitTime(IoC, NS2BCLK(T_CLK_2_DATA_OUT));
31802-
31803- /* Set Clock high */
31804- I2C_CLK_HIGH(IoC);
31805-
31806- SkDgWaitTime(IoC, NS2BCLK(T_STOP_SETUP));
31807-
31808- /*
31809- * Set Data High: Do it by setting the Data Line to Input.
31810- * Because of a pull up resistor the Data Line
31811- * floods to high.
31812- */
31813- I2C_DATA_IN(IoC);
31814-
31815- /*
31816- * When I2C activity is stopped
31817- * o DATA should be set to input and
31818- * o CLOCK should be set to high!
31819- */
31820- SkDgWaitTime(IoC, NS2BCLK(T_BUS_IDLE));
31821-} /* SkI2cStop */
31822-
31823-
31824-/*
31825- * Receive just one bit via the I2C bus.
31826- *
31827- * Note: Clock must be set to LOW before calling this function.
31828- *
31829- * Returns The received bit.
31830- */
31831-int SkI2cRcvBit(
31832-SK_IOC IoC) /* I/O Context */
31833-{
31834- int Bit;
31835- SK_U8 I2cSwCtrl;
31836-
31837- /* Init data as input line */
31838- I2C_DATA_IN(IoC);
31839-
31840- SkDgWaitTime(IoC, NS2BCLK(T_CLK_2_DATA_OUT));
31841-
31842- I2C_CLK_HIGH(IoC);
31843-
31844- SkDgWaitTime(IoC, NS2BCLK(T_CLK_HIGH));
31845-
31846- SK_I2C_GET_SW(IoC, &I2cSwCtrl);
31847-
31848- Bit = (I2cSwCtrl & I2C_DATA) ? 1 : 0;
31849-
31850- I2C_CLK_LOW(IoC);
31851- SkDgWaitTime(IoC, NS2BCLK(T_CLK_LOW-T_CLK_2_DATA_OUT));
31852-
31853- return(Bit);
31854-} /* SkI2cRcvBit */
31855-
31856-
31857-/*
31858- * Receive an ACK.
31859- *
31860- * returns 0 If acknowledged
31861- * 1 in case of an error
31862- */
31863-int SkI2cRcvAck(
31864-SK_IOC IoC) /* I/O Context */
31865-{
31866- /*
31867- * Received bit must be zero.
31868- */
31869- return(SkI2cRcvBit(IoC) != 0);
31870-} /* SkI2cRcvAck */
31871-
31872-
31873-/*
31874- * Send an NACK.
31875- */
31876-void SkI2cSndNAck(
31877-SK_IOC IoC) /* I/O Context */
31878-{
31879- /*
31880- * Received bit must be zero.
31881- */
31882- SkI2cSndBit(IoC, 1);
31883-} /* SkI2cSndNAck */
31884-
31885-
31886-/*
31887- * Send an ACK.
31888- */
31889-void SkI2cSndAck(
31890-SK_IOC IoC) /* I/O Context */
31891-{
31892- /*
31893- * Received bit must be zero.
31894- */
31895- SkI2cSndBit(IoC, 0);
31896-} /* SkI2cSndAck */
31897-
31898-
31899-/*
31900- * Send one byte to the I2C device and wait for ACK.
31901- *
31902- * Return acknowleged status.
31903- */
31904-int SkI2cSndByte(
31905-SK_IOC IoC, /* I/O Context */
31906-int Byte) /* byte to send */
31907-{
31908- int i;
31909-
31910- for (i = 0; i < 8; i++) {
31911- if (Byte & (1<<(7-i))) {
31912- SkI2cSndBit(IoC, 1);
31913- }
31914- else {
31915- SkI2cSndBit(IoC, 0);
31916- }
31917- }
31918-
31919- return(SkI2cRcvAck(IoC));
31920-} /* SkI2cSndByte */
31921-
31922-
31923-/*
31924- * Receive one byte and ack it.
31925- *
31926- * Return byte.
31927- */
31928-int SkI2cRcvByte(
31929-SK_IOC IoC, /* I/O Context */
31930-int Last) /* Last Byte Flag */
31931-{
31932- int i;
31933- int Byte = 0;
31934-
31935- for (i = 0; i < 8; i++) {
31936- Byte <<= 1;
31937- Byte |= SkI2cRcvBit(IoC);
31938- }
31939-
31940- if (Last) {
31941- SkI2cSndNAck(IoC);
31942- }
31943- else {
31944- SkI2cSndAck(IoC);
31945- }
31946-
31947- return(Byte);
31948-} /* SkI2cRcvByte */
31949-
31950-
31951-/*
31952- * Start dialog and send device address
31953- *
31954- * Return 0 if acknowleged, 1 in case of an error
31955- */
31956-int SkI2cSndDev(
31957-SK_IOC IoC, /* I/O Context */
31958-int Addr, /* Device Address */
31959-int Rw) /* Read / Write Flag */
31960-{
31961- SkI2cStart(IoC);
31962- Rw = ~Rw;
31963- Rw &= I2C_WRITE;
31964- return(SkI2cSndByte(IoC, (Addr<<1) | Rw));
31965-} /* SkI2cSndDev */
31966-
31967-#endif /* SK_DIAG */
31968-
31969-/*----------------- I2C CTRL Register Functions ----------*/
31970-
31971-/*
31972- * waits for a completion of an I2C transfer
31973- *
31974- * returns 0: success, transfer completes
31975- * 1: error, transfer does not complete, I2C transfer
31976- * killed, wait loop terminated.
31977- */
31978-static int SkI2cWait(
31979-SK_AC *pAC, /* Adapter Context */
31980-SK_IOC IoC, /* I/O Context */
31981-int Event) /* complete event to wait for (I2C_READ or I2C_WRITE) */
31982-{
31983- SK_U64 StartTime;
31984- SK_U64 CurrentTime;
31985- SK_U32 I2cCtrl;
31986-
31987- StartTime = SkOsGetTime(pAC);
31988-
31989- do {
31990- CurrentTime = SkOsGetTime(pAC);
31991-
31992- if (CurrentTime - StartTime > SK_TICKS_PER_SEC / 8) {
31993-
31994- SK_I2C_STOP(IoC);
31995-#ifndef SK_DIAG
31996- SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E002, SKERR_I2C_E002MSG);
31997-#endif /* !SK_DIAG */
31998- return(1);
31999- }
32000-
32001- SK_I2C_GET_CTL(IoC, &I2cCtrl);
32002-
32003-#ifdef xYUKON_DBG
32004- printf("StartTime=%lu, CurrentTime=%lu\n",
32005- StartTime, CurrentTime);
32006- if (kbhit()) {
32007- return(1);
32008- }
32009-#endif /* YUKON_DBG */
32010-
32011- } while ((I2cCtrl & I2C_FLAG) == (SK_U32)Event << 31);
32012-
32013- return(0);
32014-} /* SkI2cWait */
32015-
32016-
32017-/*
32018- * waits for a completion of an I2C transfer
32019- *
32020- * Returns
32021- * Nothing
32022- */
32023-void SkI2cWaitIrq(
32024-SK_AC *pAC, /* Adapter Context */
32025-SK_IOC IoC) /* I/O Context */
32026-{
32027- SK_SENSOR *pSen;
32028- SK_U64 StartTime;
32029- SK_U32 IrqSrc;
32030-
32031- pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
32032-
32033- if (pSen->SenState == SK_SEN_IDLE) {
32034- return;
32035- }
32036-
32037- StartTime = SkOsGetTime(pAC);
32038-
32039- do {
32040- if (SkOsGetTime(pAC) - StartTime > SK_TICKS_PER_SEC / 8) {
32041-
32042- SK_I2C_STOP(IoC);
32043-#ifndef SK_DIAG
32044- SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E016, SKERR_I2C_E016MSG);
32045-#endif /* !SK_DIAG */
32046- return;
32047- }
32048-
32049- SK_IN32(IoC, B0_ISRC, &IrqSrc);
32050-
32051- } while ((IrqSrc & IS_I2C_READY) == 0);
32052-
32053- pSen->SenState = SK_SEN_IDLE;
32054- return;
32055-} /* SkI2cWaitIrq */
32056-
32057-/*
32058- * writes a single byte or 4 bytes into the I2C device
32059- *
32060- * returns 0: success
32061- * 1: error
32062- */
32063-static int SkI2cWrite(
32064-SK_AC *pAC, /* Adapter Context */
32065-SK_IOC IoC, /* I/O Context */
32066-SK_U32 I2cData, /* I2C Data to write */
32067-int I2cDev, /* I2C Device Address */
32068-int I2cDevSize, /* I2C Device Size (e.g. I2C_025K_DEV or I2C_2K_DEV) */
32069-int I2cReg, /* I2C Device Register Address */
32070-int I2cBurst) /* I2C Burst Flag */
32071-{
32072- SK_OUT32(IoC, B2_I2C_DATA, I2cData);
32073-
32074- SK_I2C_CTL(IoC, I2C_WRITE, I2cDev, I2cDevSize, I2cReg, I2cBurst);
32075-
32076- return(SkI2cWait(pAC, IoC, I2C_WRITE));
32077-} /* SkI2cWrite*/
32078-
32079-
32080-#ifdef SK_DIAG
32081-/*
32082- * reads a single byte or 4 bytes from the I2C device
32083- *
32084- * returns the word read
32085- */
32086-SK_U32 SkI2cRead(
32087-SK_AC *pAC, /* Adapter Context */
32088-SK_IOC IoC, /* I/O Context */
32089-int I2cDev, /* I2C Device Address */
32090-int I2cDevSize, /* I2C Device Size (e.g. I2C_025K_DEV or I2C_2K_DEV) */
32091-int I2cReg, /* I2C Device Register Address */
32092-int I2cBurst) /* I2C Burst Flag */
32093-{
32094- SK_U32 Data;
32095-
32096- SK_OUT32(IoC, B2_I2C_DATA, 0);
32097- SK_I2C_CTL(IoC, I2C_READ, I2cDev, I2cDevSize, I2cReg, I2cBurst);
32098-
32099- if (SkI2cWait(pAC, IoC, I2C_READ) != 0) {
32100- w_print("%s\n", SKERR_I2C_E002MSG);
32101- }
32102-
32103- SK_IN32(IoC, B2_I2C_DATA, &Data);
32104-
32105- return(Data);
32106-} /* SkI2cRead */
32107-#endif /* SK_DIAG */
32108-
32109-
32110-/*
32111- * read a sensor's value
32112- *
32113- * This function reads a sensor's value from the I2C sensor chip. The sensor
32114- * is defined by its index into the sensors database in the struct pAC points
32115- * to.
32116- * Returns
32117- * 1 if the read is completed
32118- * 0 if the read must be continued (I2C Bus still allocated)
32119- */
32120-static int SkI2cReadSensor(
32121-SK_AC *pAC, /* Adapter Context */
32122-SK_IOC IoC, /* I/O Context */
32123-SK_SENSOR *pSen) /* Sensor to be read */
32124-{
32125- if (pSen->SenRead != NULL) {
32126- return((*pSen->SenRead)(pAC, IoC, pSen));
32127- }
32128- else {
32129- return(0); /* no success */
32130- }
32131-} /* SkI2cReadSensor */
32132-
32133-/*
32134- * Do the Init state 0 initialization
32135- */
32136-static int SkI2cInit0(
32137-SK_AC *pAC) /* Adapter Context */
32138-{
32139- int i;
32140-
32141- /* Begin with first sensor */
32142- pAC->I2c.CurrSens = 0;
32143-
32144- /* Begin with timeout control for state machine */
32145- pAC->I2c.TimerMode = SK_TIMER_WATCH_SM;
32146-
32147- /* Set sensor number to zero */
32148- pAC->I2c.MaxSens = 0;
32149-
32150-#ifndef SK_DIAG
32151- /* Initialize Number of Dummy Reads */
32152- pAC->I2c.DummyReads = SK_MAX_SENSORS;
32153-#endif
32154-
32155- for (i = 0; i < SK_MAX_SENSORS; i++) {
32156- pAC->I2c.SenTable[i].SenDesc = "unknown";
32157- pAC->I2c.SenTable[i].SenType = SK_SEN_UNKNOWN;
32158- pAC->I2c.SenTable[i].SenThreErrHigh = 0;
32159- pAC->I2c.SenTable[i].SenThreErrLow = 0;
32160- pAC->I2c.SenTable[i].SenThreWarnHigh = 0;
32161- pAC->I2c.SenTable[i].SenThreWarnLow = 0;
32162- pAC->I2c.SenTable[i].SenReg = LM80_FAN2_IN;
32163- pAC->I2c.SenTable[i].SenInit = SK_SEN_DYN_INIT_NONE;
32164- pAC->I2c.SenTable[i].SenValue = 0;
32165- pAC->I2c.SenTable[i].SenErrFlag = SK_SEN_ERR_NOT_PRESENT;
32166- pAC->I2c.SenTable[i].SenErrCts = 0;
32167- pAC->I2c.SenTable[i].SenBegErrTS = 0;
32168- pAC->I2c.SenTable[i].SenState = SK_SEN_IDLE;
32169- pAC->I2c.SenTable[i].SenRead = NULL;
32170- pAC->I2c.SenTable[i].SenDev = 0;
32171- }
32172-
32173- /* Now we are "INIT data"ed */
32174- pAC->I2c.InitLevel = SK_INIT_DATA;
32175- return(0);
32176-} /* SkI2cInit0*/
32177-
32178-
32179-/*
32180- * Do the init state 1 initialization
32181- *
32182- * initialize the following register of the LM80:
32183- * Configuration register:
32184- * - START, noINT, activeLOW, noINT#Clear, noRESET, noCI, noGPO#, noINIT
32185- *
32186- * Interrupt Mask Register 1:
32187- * - all interrupts are Disabled (0xff)
32188- *
32189- * Interrupt Mask Register 2:
32190- * - all interrupts are Disabled (0xff) Interrupt modi doesn't matter.
32191- *
32192- * Fan Divisor/RST_OUT register:
32193- * - Divisors set to 1 (bits 00), all others 0s.
32194- *
32195- * OS# Configuration/Temperature resolution Register:
32196- * - all 0s
32197- *
32198- */
32199-static int SkI2cInit1(
32200-SK_AC *pAC, /* Adapter Context */
32201-SK_IOC IoC) /* I/O Context */
32202-{
32203- int i;
32204- SK_U8 I2cSwCtrl;
32205- SK_GEPORT *pPrt; /* GIni Port struct pointer */
32206-
32207- if (pAC->I2c.InitLevel != SK_INIT_DATA) {
32208- /* ReInit not needed in I2C module */
32209- return(0);
32210- }
32211-
32212- /* Set the Direction of I2C-Data Pin to IN */
32213- SK_I2C_CLR_BIT(IoC, I2C_DATA_DIR | I2C_DATA);
32214- /* Check for 32-Bit Yukon with Low at I2C-Data Pin */
32215- SK_I2C_GET_SW(IoC, &I2cSwCtrl);
32216-
32217- if ((I2cSwCtrl & I2C_DATA) == 0) {
32218- /* this is a 32-Bit board */
32219- pAC->GIni.GIYukon32Bit = SK_TRUE;
32220- return(0);
32221- }
32222-
32223- /* Check for 64 Bit Yukon without sensors */
32224- if (SkI2cWrite(pAC, IoC, 0, LM80_ADDR, I2C_025K_DEV, LM80_CFG, 0) != 0) {
32225- return(0);
32226- }
32227-
32228- (void)SkI2cWrite(pAC, IoC, 0xffUL, LM80_ADDR, I2C_025K_DEV, LM80_IMSK_1, 0);
32229-
32230- (void)SkI2cWrite(pAC, IoC, 0xffUL, LM80_ADDR, I2C_025K_DEV, LM80_IMSK_2, 0);
32231-
32232- (void)SkI2cWrite(pAC, IoC, 0, LM80_ADDR, I2C_025K_DEV, LM80_FAN_CTRL, 0);
32233-
32234- (void)SkI2cWrite(pAC, IoC, 0, LM80_ADDR, I2C_025K_DEV, LM80_TEMP_CTRL, 0);
32235-
32236- (void)SkI2cWrite(pAC, IoC, (SK_U32)LM80_CFG_START, LM80_ADDR, I2C_025K_DEV,
32237- LM80_CFG, 0);
32238-
32239- /*
32240- * MaxSens has to be updated here, because PhyType is not
32241- * set when performing Init Level 0
32242- */
32243- pAC->I2c.MaxSens = 5;
32244-
32245- pPrt = &pAC->GIni.GP[0];
32246-
32247- if (pAC->GIni.GIGenesis) {
32248- if (pPrt->PhyType == SK_PHY_BCOM) {
32249- if (pAC->GIni.GIMacsFound == 1) {
32250- pAC->I2c.MaxSens += 1;
32251- }
32252- else {
32253- pAC->I2c.MaxSens += 3;
32254- }
32255- }
32256- }
32257- else {
32258- pAC->I2c.MaxSens += 3;
32259- }
32260-
32261- for (i = 0; i < pAC->I2c.MaxSens; i++) {
32262- switch (i) {
32263- case 0:
32264- pAC->I2c.SenTable[i].SenDesc = "Temperature";
32265- pAC->I2c.SenTable[i].SenType = SK_SEN_TEMP;
32266- pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_TEMP_HIGH_ERR;
32267- pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_TEMP_HIGH_WARN;
32268- pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_TEMP_LOW_WARN;
32269- pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_TEMP_LOW_ERR;
32270- pAC->I2c.SenTable[i].SenReg = LM80_TEMP_IN;
32271- break;
32272- case 1:
32273- pAC->I2c.SenTable[i].SenDesc = "Voltage PCI";
32274- pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
32275- pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PCI_5V_HIGH_ERR;
32276- pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PCI_5V_HIGH_WARN;
32277- pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PCI_5V_LOW_WARN;
32278- pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PCI_5V_LOW_ERR;
32279- pAC->I2c.SenTable[i].SenReg = LM80_VT0_IN;
32280- break;
32281- case 2:
32282- pAC->I2c.SenTable[i].SenDesc = "Voltage PCI-IO";
32283- pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
32284- pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PCI_IO_5V_HIGH_ERR;
32285- pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PCI_IO_5V_HIGH_WARN;
32286- pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PCI_IO_3V3_LOW_WARN;
32287- pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PCI_IO_3V3_LOW_ERR;
32288- pAC->I2c.SenTable[i].SenReg = LM80_VT1_IN;
32289- pAC->I2c.SenTable[i].SenInit = SK_SEN_DYN_INIT_PCI_IO;
32290- break;
32291- case 3:
32292- pAC->I2c.SenTable[i].SenDesc = "Voltage ASIC";
32293- pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
32294- pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_VDD_HIGH_ERR;
32295- pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_VDD_HIGH_WARN;
32296- pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_VDD_LOW_WARN;
32297- pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_VDD_LOW_ERR;
32298- pAC->I2c.SenTable[i].SenReg = LM80_VT2_IN;
32299- break;
32300- case 4:
32301- if (pAC->GIni.GIGenesis) {
32302- if (pPrt->PhyType == SK_PHY_BCOM) {
32303- pAC->I2c.SenTable[i].SenDesc = "Voltage PHY A PLL";
32304- pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR;
32305- pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN;
32306- pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN;
32307- pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR;
32308- }
32309- else {
32310- pAC->I2c.SenTable[i].SenDesc = "Voltage PMA";
32311- pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR;
32312- pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN;
32313- pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN;
32314- pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR;
32315- }
32316- }
32317- else {
32318- pAC->I2c.SenTable[i].SenDesc = "Voltage VAUX";
32319- pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_VAUX_3V3_HIGH_ERR;
32320- pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_VAUX_3V3_HIGH_WARN;
32321- if (pAC->GIni.GIVauxAvail) {
32322- pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_VAUX_3V3_LOW_WARN;
32323- pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_VAUX_3V3_LOW_ERR;
32324- }
32325- else {
32326- pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_VAUX_0V_WARN_ERR;
32327- pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_VAUX_0V_WARN_ERR;
32328- }
32329- }
32330- pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
32331- pAC->I2c.SenTable[i].SenReg = LM80_VT3_IN;
32332- break;
32333- case 5:
32334- if (pAC->GIni.GIGenesis) {
32335- pAC->I2c.SenTable[i].SenDesc = "Voltage PHY 2V5";
32336- pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PHY_2V5_HIGH_ERR;
32337- pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PHY_2V5_HIGH_WARN;
32338- pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PHY_2V5_LOW_WARN;
32339- pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PHY_2V5_LOW_ERR;
32340- }
32341- else {
32342- pAC->I2c.SenTable[i].SenDesc = "Voltage Core 1V5";
32343- pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_CORE_1V5_HIGH_ERR;
32344- pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_CORE_1V5_HIGH_WARN;
32345- pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_CORE_1V5_LOW_WARN;
32346- pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_CORE_1V5_LOW_ERR;
32347- }
32348- pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
32349- pAC->I2c.SenTable[i].SenReg = LM80_VT4_IN;
32350- break;
32351- case 6:
32352- if (pAC->GIni.GIGenesis) {
32353- pAC->I2c.SenTable[i].SenDesc = "Voltage PHY B PLL";
32354- }
32355- else {
32356- pAC->I2c.SenTable[i].SenDesc = "Voltage PHY 3V3";
32357- }
32358- pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
32359- pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR;
32360- pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN;
32361- pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN;
32362- pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR;
32363- pAC->I2c.SenTable[i].SenReg = LM80_VT5_IN;
32364- break;
32365- case 7:
32366- if (pAC->GIni.GIGenesis) {
32367- pAC->I2c.SenTable[i].SenDesc = "Speed Fan";
32368- pAC->I2c.SenTable[i].SenType = SK_SEN_FAN;
32369- pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_FAN_HIGH_ERR;
32370- pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_FAN_HIGH_WARN;
32371- pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_FAN_LOW_WARN;
32372- pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_FAN_LOW_ERR;
32373- pAC->I2c.SenTable[i].SenReg = LM80_FAN2_IN;
32374- }
32375- else {
32376- pAC->I2c.SenTable[i].SenDesc = "Voltage PHY 2V5";
32377- pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
32378- pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PHY_2V5_HIGH_ERR;
32379- pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PHY_2V5_HIGH_WARN;
32380- pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PHY_2V5_LOW_WARN;
32381- pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PHY_2V5_LOW_ERR;
32382- pAC->I2c.SenTable[i].SenReg = LM80_VT6_IN;
32383- }
32384- break;
32385- default:
32386- SK_ERR_LOG(pAC, SK_ERRCL_INIT | SK_ERRCL_SW,
32387- SKERR_I2C_E001, SKERR_I2C_E001MSG);
32388- break;
32389- }
32390-
32391- pAC->I2c.SenTable[i].SenValue = 0;
32392- pAC->I2c.SenTable[i].SenErrFlag = SK_SEN_ERR_OK;
32393- pAC->I2c.SenTable[i].SenErrCts = 0;
32394- pAC->I2c.SenTable[i].SenBegErrTS = 0;
32395- pAC->I2c.SenTable[i].SenState = SK_SEN_IDLE;
32396- pAC->I2c.SenTable[i].SenRead = SkLm80ReadSensor;
32397- pAC->I2c.SenTable[i].SenDev = LM80_ADDR;
32398- }
32399-
32400-#ifndef SK_DIAG
32401- pAC->I2c.DummyReads = pAC->I2c.MaxSens;
32402-#endif /* !SK_DIAG */
32403-
32404- /* Clear I2C IRQ */
32405- SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
32406-
32407- /* Now we are I/O initialized */
32408- pAC->I2c.InitLevel = SK_INIT_IO;
32409- return(0);
32410-} /* SkI2cInit1 */
32411-
32412-
32413-/*
32414- * Init level 2: Start first sensor read.
32415- */
32416-static int SkI2cInit2(
32417-SK_AC *pAC, /* Adapter Context */
32418-SK_IOC IoC) /* I/O Context */
32419-{
32420- int ReadComplete;
32421- SK_SENSOR *pSen;
32422-
32423- if (pAC->I2c.InitLevel != SK_INIT_IO) {
32424- /* ReInit not needed in I2C module */
32425- /* Init0 and Init2 not permitted */
32426- return(0);
32427- }
32428-
32429- pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
32430- ReadComplete = SkI2cReadSensor(pAC, IoC, pSen);
32431-
32432- if (ReadComplete) {
32433- SK_ERR_LOG(pAC, SK_ERRCL_INIT, SKERR_I2C_E008, SKERR_I2C_E008MSG);
32434- }
32435-
32436- /* Now we are correctly initialized */
32437- pAC->I2c.InitLevel = SK_INIT_RUN;
32438-
32439- return(0);
32440-} /* SkI2cInit2*/
32441-
32442-
32443-/*
32444- * Initialize I2C devices
32445- *
32446- * Get the first voltage value and discard it.
32447- * Go into temperature read mode. A default pointer is not set.
32448- *
32449- * The things to be done depend on the init level in the parameter list:
32450- * Level 0:
32451- * Initialize only the data structures. Do NOT access hardware.
32452- * Level 1:
32453- * Initialize hardware through SK_IN / SK_OUT commands. Do NOT use interrupts.
32454- * Level 2:
32455- * Everything is possible. Interrupts may be used from now on.
32456- *
32457- * return:
32458- * 0 = success
32459- * other = error.
32460- */
32461-int SkI2cInit(
32462-SK_AC *pAC, /* Adapter Context */
32463-SK_IOC IoC, /* I/O Context needed in levels 1 and 2 */
32464-int Level) /* Init Level */
32465-{
32466-
32467- switch (Level) {
32468- case SK_INIT_DATA:
32469- return(SkI2cInit0(pAC));
32470- case SK_INIT_IO:
32471- return(SkI2cInit1(pAC, IoC));
32472- case SK_INIT_RUN:
32473- return(SkI2cInit2(pAC, IoC));
32474- default:
32475- break;
32476- }
32477-
32478- return(0);
32479-} /* SkI2cInit */
32480-
32481-
32482-#ifndef SK_DIAG
32483-
32484-/*
32485- * Interrupt service function for the I2C Interface
32486- *
32487- * Clears the Interrupt source
32488- *
32489- * Reads the register and check it for sending a trap.
32490- *
32491- * Starts the timer if necessary.
32492- */
32493-void SkI2cIsr(
32494-SK_AC *pAC, /* Adapter Context */
32495-SK_IOC IoC) /* I/O Context */
32496-{
32497- SK_EVPARA Para;
32498-
32499- /* Clear I2C IRQ */
32500- SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
32501-
32502- Para.Para64 = 0;
32503- SkEventQueue(pAC, SKGE_I2C, SK_I2CEV_IRQ, Para);
32504-} /* SkI2cIsr */
32505-
32506-
32507-/*
32508- * Check this sensors Value against the threshold and send events.
32509- */
32510-static void SkI2cCheckSensor(
32511-SK_AC *pAC, /* Adapter Context */
32512-SK_SENSOR *pSen)
32513-{
32514- SK_EVPARA ParaLocal;
32515- SK_BOOL TooHigh; /* Is sensor too high? */
32516- SK_BOOL TooLow; /* Is sensor too low? */
32517- SK_U64 CurrTime; /* Current Time */
32518- SK_BOOL DoTrapSend; /* We need to send a trap */
32519- SK_BOOL DoErrLog; /* We need to log the error */
32520- SK_BOOL IsError; /* We need to log the error */
32521-
32522- /* Check Dummy Reads first */
32523- if (pAC->I2c.DummyReads > 0) {
32524- pAC->I2c.DummyReads--;
32525- return;
32526- }
32527-
32528- /* Get the current time */
32529- CurrTime = SkOsGetTime(pAC);
32530-
32531- /* Set para to the most useful setting: The current sensor. */
32532- ParaLocal.Para64 = (SK_U64)pAC->I2c.CurrSens;
32533-
32534- /* Check the Value against the thresholds. First: Error Thresholds */
32535- TooHigh = (pSen->SenValue > pSen->SenThreErrHigh);
32536- TooLow = (pSen->SenValue < pSen->SenThreErrLow);
32537-
32538- IsError = SK_FALSE;
32539- if (TooHigh || TooLow) {
32540- /* Error condition is satisfied */
32541- DoTrapSend = SK_TRUE;
32542- DoErrLog = SK_TRUE;
32543-
32544- /* Now error condition is satisfied */
32545- IsError = SK_TRUE;
32546-
32547- if (pSen->SenErrFlag == SK_SEN_ERR_ERR) {
32548- /* This state is the former one */
32549-
32550- /* So check first whether we have to send a trap */
32551- if (pSen->SenLastErrTrapTS + SK_SEN_ERR_TR_HOLD >
32552- CurrTime) {
32553- /*
32554- * Do NOT send the Trap. The hold back time
32555- * has to run out first.
32556- */
32557- DoTrapSend = SK_FALSE;
32558- }
32559-
32560- /* Check now whether we have to log an Error */
32561- if (pSen->SenLastErrLogTS + SK_SEN_ERR_LOG_HOLD >
32562- CurrTime) {
32563- /*
32564- * Do NOT log the error. The hold back time
32565- * has to run out first.
32566- */
32567- DoErrLog = SK_FALSE;
32568- }
32569- }
32570- else {
32571- /* We came from a different state -> Set Begin Time Stamp */
32572- pSen->SenBegErrTS = CurrTime;
32573- pSen->SenErrFlag = SK_SEN_ERR_ERR;
32574- }
32575-
32576- if (DoTrapSend) {
32577- /* Set current Time */
32578- pSen->SenLastErrTrapTS = CurrTime;
32579- pSen->SenErrCts++;
32580-
32581- /* Queue PNMI Event */
32582- SkEventQueue(pAC, SKGE_PNMI, (TooHigh ?
32583- SK_PNMI_EVT_SEN_ERR_UPP :
32584- SK_PNMI_EVT_SEN_ERR_LOW),
32585- ParaLocal);
32586- }
32587-
32588- if (DoErrLog) {
32589- /* Set current Time */
32590- pSen->SenLastErrLogTS = CurrTime;
32591-
32592- if (pSen->SenType == SK_SEN_TEMP) {
32593- SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E011, SKERR_I2C_E011MSG);
32594- }
32595- else if (pSen->SenType == SK_SEN_VOLT) {
32596- SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E012, SKERR_I2C_E012MSG);
32597- }
32598- else {
32599- SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E015, SKERR_I2C_E015MSG);
32600- }
32601- }
32602- }
32603-
32604- /* Check the Value against the thresholds */
32605- /* 2nd: Warning thresholds */
32606- TooHigh = (pSen->SenValue > pSen->SenThreWarnHigh);
32607- TooLow = (pSen->SenValue < pSen->SenThreWarnLow);
32608-
32609- if (!IsError && (TooHigh || TooLow)) {
32610- /* Error condition is satisfied */
32611- DoTrapSend = SK_TRUE;
32612- DoErrLog = SK_TRUE;
32613-
32614- if (pSen->SenErrFlag == SK_SEN_ERR_WARN) {
32615- /* This state is the former one */
32616-
32617- /* So check first whether we have to send a trap */
32618- if (pSen->SenLastWarnTrapTS + SK_SEN_WARN_TR_HOLD > CurrTime) {
32619- /*
32620- * Do NOT send the Trap. The hold back time
32621- * has to run out first.
32622- */
32623- DoTrapSend = SK_FALSE;
32624- }
32625-
32626- /* Check now whether we have to log an Error */
32627- if (pSen->SenLastWarnLogTS + SK_SEN_WARN_LOG_HOLD > CurrTime) {
32628- /*
32629- * Do NOT log the error. The hold back time
32630- * has to run out first.
32631- */
32632- DoErrLog = SK_FALSE;
32633- }
32634- }
32635- else {
32636- /* We came from a different state -> Set Begin Time Stamp */
32637- pSen->SenBegWarnTS = CurrTime;
32638- pSen->SenErrFlag = SK_SEN_ERR_WARN;
32639- }
32640-
32641- if (DoTrapSend) {
32642- /* Set current Time */
32643- pSen->SenLastWarnTrapTS = CurrTime;
32644- pSen->SenWarnCts++;
32645-
32646- /* Queue PNMI Event */
32647- SkEventQueue(pAC, SKGE_PNMI, (TooHigh ?
32648- SK_PNMI_EVT_SEN_WAR_UPP :
32649- SK_PNMI_EVT_SEN_WAR_LOW),
32650- ParaLocal);
32651- }
32652-
32653- if (DoErrLog) {
32654- /* Set current Time */
32655- pSen->SenLastWarnLogTS = CurrTime;
32656-
32657- if (pSen->SenType == SK_SEN_TEMP) {
32658- SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E009, SKERR_I2C_E009MSG);
32659- }
32660- else if (pSen->SenType == SK_SEN_VOLT) {
32661- SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E010, SKERR_I2C_E010MSG);
32662- }
32663- else {
32664- SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E014, SKERR_I2C_E014MSG);
32665- }
32666- }
32667- }
32668-
32669- /* Check for NO error at all */
32670- if (!IsError && !TooHigh && !TooLow) {
32671- /* Set o.k. Status if no error and no warning condition */
32672- pSen->SenErrFlag = SK_SEN_ERR_OK;
32673- }
32674-
32675- /* End of check against the thresholds */
32676-
32677- /* Bug fix AF: 16.Aug.2001: Correct the init base
32678- * of LM80 sensor.
32679- */
32680- if (pSen->SenInit == SK_SEN_DYN_INIT_PCI_IO) {
32681-
32682- pSen->SenInit = SK_SEN_DYN_INIT_NONE;
32683-
32684- if (pSen->SenValue > SK_SEN_PCI_IO_RANGE_LIMITER) {
32685- /* 5V PCI-IO Voltage */
32686- pSen->SenThreWarnLow = SK_SEN_PCI_IO_5V_LOW_WARN;
32687- pSen->SenThreErrLow = SK_SEN_PCI_IO_5V_LOW_ERR;
32688- }
32689- else {
32690- /* 3.3V PCI-IO Voltage */
32691- pSen->SenThreWarnHigh = SK_SEN_PCI_IO_3V3_HIGH_WARN;
32692- pSen->SenThreErrHigh = SK_SEN_PCI_IO_3V3_HIGH_ERR;
32693- }
32694- }
32695-
32696-#ifdef TEST_ONLY
32697- /* Dynamic thresholds also for VAUX of LM80 sensor */
32698- if (pSen->SenInit == SK_SEN_DYN_INIT_VAUX) {
32699-
32700- pSen->SenInit = SK_SEN_DYN_INIT_NONE;
32701-
32702- /* 3.3V VAUX Voltage */
32703- if (pSen->SenValue > SK_SEN_VAUX_RANGE_LIMITER) {
32704- pSen->SenThreWarnLow = SK_SEN_VAUX_3V3_LOW_WARN;
32705- pSen->SenThreErrLow = SK_SEN_VAUX_3V3_LOW_ERR;
32706- }
32707- /* 0V VAUX Voltage */
32708- else {
32709- pSen->SenThreWarnHigh = SK_SEN_VAUX_0V_WARN_ERR;
32710- pSen->SenThreErrHigh = SK_SEN_VAUX_0V_WARN_ERR;
32711- }
32712- }
32713-
32714- /*
32715- * Check initialization state:
32716- * The VIO Thresholds need adaption
32717- */
32718- if (!pSen->SenInit && pSen->SenReg == LM80_VT1_IN &&
32719- pSen->SenValue > SK_SEN_WARNLOW2C &&
32720- pSen->SenValue < SK_SEN_WARNHIGH2) {
32721- pSen->SenThreErrLow = SK_SEN_ERRLOW2C;
32722- pSen->SenThreWarnLow = SK_SEN_WARNLOW2C;
32723- pSen->SenInit = SK_TRUE;
32724- }
32725-
32726- if (!pSen->SenInit && pSen->SenReg == LM80_VT1_IN &&
32727- pSen->SenValue > SK_SEN_WARNLOW2 &&
32728- pSen->SenValue < SK_SEN_WARNHIGH2C) {
32729- pSen->SenThreErrHigh = SK_SEN_ERRHIGH2C;
32730- pSen->SenThreWarnHigh = SK_SEN_WARNHIGH2C;
32731- pSen->SenInit = SK_TRUE;
32732- }
32733-#endif
32734-
32735- if (pSen->SenInit != SK_SEN_DYN_INIT_NONE) {
32736- SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E013, SKERR_I2C_E013MSG);
32737- }
32738-} /* SkI2cCheckSensor */
32739-
32740-
32741-/*
32742- * The only Event to be served is the timeout event
32743- *
32744- */
32745-int SkI2cEvent(
32746-SK_AC *pAC, /* Adapter Context */
32747-SK_IOC IoC, /* I/O Context */
32748-SK_U32 Event, /* Module specific Event */
32749-SK_EVPARA Para) /* Event specific Parameter */
32750-{
32751- int ReadComplete;
32752- SK_SENSOR *pSen;
32753- SK_U32 Time;
32754- SK_EVPARA ParaLocal;
32755- int i;
32756-
32757- /* New case: no sensors */
32758- if (pAC->I2c.MaxSens == 0) {
32759- return(0);
32760- }
32761-
32762- switch (Event) {
32763- case SK_I2CEV_IRQ:
32764- pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
32765- ReadComplete = SkI2cReadSensor(pAC, IoC, pSen);
32766-
32767- if (ReadComplete) {
32768- /* Check sensor against defined thresholds */
32769- SkI2cCheckSensor(pAC, pSen);
32770-
32771- /* Increment Current sensor and set appropriate Timeout */
32772- pAC->I2c.CurrSens++;
32773- if (pAC->I2c.CurrSens >= pAC->I2c.MaxSens) {
32774- pAC->I2c.CurrSens = 0;
32775- Time = SK_I2C_TIM_LONG;
32776- }
32777- else {
32778- Time = SK_I2C_TIM_SHORT;
32779- }
32780-
32781- /* Start Timer */
32782- ParaLocal.Para64 = (SK_U64)0;
32783-
32784- pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING;
32785-
32786- SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time,
32787- SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
32788- }
32789- else {
32790- /* Start Timer */
32791- ParaLocal.Para64 = (SK_U64)0;
32792-
32793- pAC->I2c.TimerMode = SK_TIMER_WATCH_SM;
32794-
32795- SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, SK_I2C_TIM_WATCH,
32796- SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
32797- }
32798- break;
32799- case SK_I2CEV_TIM:
32800- if (pAC->I2c.TimerMode == SK_TIMER_NEW_GAUGING) {
32801-
32802- ParaLocal.Para64 = (SK_U64)0;
32803- SkTimerStop(pAC, IoC, &pAC->I2c.SenTimer);
32804-
32805- pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
32806- ReadComplete = SkI2cReadSensor(pAC, IoC, pSen);
32807-
32808- if (ReadComplete) {
32809- /* Check sensor against defined thresholds */
32810- SkI2cCheckSensor(pAC, pSen);
32811-
32812- /* Increment Current sensor and set appropriate Timeout */
32813- pAC->I2c.CurrSens++;
32814- if (pAC->I2c.CurrSens == pAC->I2c.MaxSens) {
32815- pAC->I2c.CurrSens = 0;
32816- Time = SK_I2C_TIM_LONG;
32817- }
32818- else {
32819- Time = SK_I2C_TIM_SHORT;
32820- }
32821-
32822- /* Start Timer */
32823- ParaLocal.Para64 = (SK_U64)0;
32824-
32825- pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING;
32826-
32827- SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time,
32828- SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
32829- }
32830- }
32831- else {
32832- pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
32833- pSen->SenErrFlag = SK_SEN_ERR_FAULTY;
32834- SK_I2C_STOP(IoC);
32835-
32836- /* Increment Current sensor and set appropriate Timeout */
32837- pAC->I2c.CurrSens++;
32838- if (pAC->I2c.CurrSens == pAC->I2c.MaxSens) {
32839- pAC->I2c.CurrSens = 0;
32840- Time = SK_I2C_TIM_LONG;
32841- }
32842- else {
32843- Time = SK_I2C_TIM_SHORT;
32844- }
32845-
32846- /* Start Timer */
32847- ParaLocal.Para64 = (SK_U64)0;
32848-
32849- pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING;
32850-
32851- SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time,
32852- SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
32853- }
32854- break;
32855- case SK_I2CEV_CLEAR:
32856- for (i = 0; i < SK_MAX_SENSORS; i++) {
32857- pAC->I2c.SenTable[i].SenErrFlag = SK_SEN_ERR_OK;
32858- pAC->I2c.SenTable[i].SenErrCts = 0;
32859- pAC->I2c.SenTable[i].SenWarnCts = 0;
32860- pAC->I2c.SenTable[i].SenBegErrTS = 0;
32861- pAC->I2c.SenTable[i].SenBegWarnTS = 0;
32862- pAC->I2c.SenTable[i].SenLastErrTrapTS = (SK_U64)0;
32863- pAC->I2c.SenTable[i].SenLastErrLogTS = (SK_U64)0;
32864- pAC->I2c.SenTable[i].SenLastWarnTrapTS = (SK_U64)0;
32865- pAC->I2c.SenTable[i].SenLastWarnLogTS = (SK_U64)0;
32866- }
32867- break;
32868- default:
32869- SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E006, SKERR_I2C_E006MSG);
32870- }
32871-
32872- return(0);
32873-} /* SkI2cEvent*/
32874-
32875-#endif /* !SK_DIAG */
32876diff -urN linux-2.6.17.orig/drivers/net/sk98lin/sklm80.c linux-2.6.17/drivers/net/sk98lin/sklm80.c
32877--- linux-2.6.17.orig/drivers/net/sk98lin/sklm80.c 2006-06-22 13:17:16.000000000 +0200
32878+++ linux-2.6.17/drivers/net/sk98lin/sklm80.c 2006-04-27 11:43:44.000000000 +0200
32879@@ -2,14 +2,15 @@
32880 *
32881 * Name: sklm80.c
32882 * Project: Gigabit Ethernet Adapters, TWSI-Module
32883- * Version: $Revision$
32884- * Date: $Date$
32885+ * Version: $Revision$
32886+ * Date: $Date$
32887 * Purpose: Functions to access Voltage and Temperature Sensor (LM80)
32888 *
32889 ******************************************************************************/
32890
32891 /******************************************************************************
32892 *
32893+ * LICENSE:
32894 * (C)Copyright 1998-2002 SysKonnect.
32895 * (C)Copyright 2002-2003 Marvell.
32896 *
32897@@ -19,6 +20,7 @@
32898 * (at your option) any later version.
32899 *
32900 * The information in this file is provided "AS IS" without warranty.
32901+ * /LICENSE
32902 *
32903 ******************************************************************************/
32904
32905@@ -27,24 +29,96 @@
32906 */
32907 #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
32908 static const char SysKonnectFileId[] =
32909- "@(#) $Id$ (C) Marvell. ";
32910+ "@(#) $Id$ (C) Marvell. ";
32911 #endif
32912
32913 #include "h/skdrv1st.h" /* Driver Specific Definitions */
32914 #include "h/lm80.h"
32915 #include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */
32916
32917+#ifdef SK_DIAG
32918+#define BREAK_OR_WAIT(pAC,IoC,Event) SkI2cWait(pAC,IoC,Event)
32919+#else /* nSK_DIAG */
32920 #define BREAK_OR_WAIT(pAC,IoC,Event) break
32921+#endif /* nSK_DIAG */
32922+
32923+#ifdef SK_DIAG
32924+/*
32925+ * read the register 'Reg' from the device 'Dev'
32926+ *
32927+ * return read error -1
32928+ * success the read value
32929+ */
32930+int SkLm80RcvReg(
32931+SK_IOC IoC, /* Adapter Context */
32932+int Dev, /* I2C device address */
32933+int Reg) /* register to read */
32934+{
32935+ int Val = 0;
32936+ int TempExt;
32937+
32938+ /* Signal device number */
32939+ if (SkI2cSndDev(IoC, Dev, I2C_WRITE)) {
32940+ return(-1);
32941+ }
32942+
32943+ if (SkI2cSndByte(IoC, Reg)) {
32944+ return(-1);
32945+ }
32946+
32947+ /* repeat start */
32948+ if (SkI2cSndDev(IoC, Dev, I2C_READ)) {
32949+ return(-1);
32950+ }
32951+
32952+ switch (Reg) {
32953+ case LM80_TEMP_IN:
32954+ Val = (int)SkI2cRcvByte(IoC, 1);
32955+
32956+ /* First: correct the value: it might be negative */
32957+ if ((Val & 0x80) != 0) {
32958+ /* Value is negative */
32959+ Val = Val - 256;
32960+ }
32961+ Val = Val * SK_LM80_TEMP_LSB;
32962+ SkI2cStop(IoC);
32963+
32964+ TempExt = (int)SkLm80RcvReg(IoC, LM80_ADDR, LM80_TEMP_CTRL);
32965+
32966+ if (Val > 0) {
32967+ Val += ((TempExt >> 7) * SK_LM80_TEMPEXT_LSB);
32968+ }
32969+ else {
32970+ Val -= ((TempExt >> 7) * SK_LM80_TEMPEXT_LSB);
32971+ }
32972+ return(Val);
32973+ break;
32974+ case LM80_VT0_IN:
32975+ case LM80_VT1_IN:
32976+ case LM80_VT2_IN:
32977+ case LM80_VT3_IN:
32978+ Val = (int)SkI2cRcvByte(IoC, 1) * SK_LM80_VT_LSB;
32979+ break;
32980+
32981+ default:
32982+ Val = (int)SkI2cRcvByte(IoC, 1);
32983+ break;
32984+ }
32985+
32986+ SkI2cStop(IoC);
32987+ return(Val);
32988+}
32989+#endif /* SK_DIAG */
32990
32991 /*
32992 * read a sensors value (LM80 specific)
32993 *
32994- * This function reads a sensors value from the I2C sensor chip LM80.
32995+ * This function reads a sensors value from the TWSI sensor chip LM80.
32996 * The sensor is defined by its index into the sensors database in the struct
32997 * pAC points to.
32998 *
32999 * Returns 1 if the read is completed
33000- * 0 if the read must be continued (I2C Bus still allocated)
33001+ * 0 if the read must be continued (TWSI Bus still allocated)
33002 */
33003 int SkLm80ReadSensor(
33004 SK_AC *pAC, /* Adapter Context */
33005diff -urN linux-2.6.17.orig/drivers/net/sk98lin/skproc.c linux-2.6.17/drivers/net/sk98lin/skproc.c
33006--- linux-2.6.17.orig/drivers/net/sk98lin/skproc.c 1970-01-01 01:00:00.000000000 +0100
33007+++ linux-2.6.17/drivers/net/sk98lin/skproc.c 2006-04-27 11:43:45.000000000 +0200
33008@@ -0,0 +1,477 @@
33009+/******************************************************************************
33010+ *
33011+ * Name: skproc.c
33012+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
33013+ * Version: $Revision$
33014+ * Date: $Date$
33015+ * Purpose: Functions to display statictic data
33016+ *
33017+ ******************************************************************************/
33018+
33019+/******************************************************************************
33020+ *
33021+ * (C)Copyright 1998-2002 SysKonnect GmbH.
33022+ * (C)Copyright 2002-2005 Marvell.
33023+ *
33024+ * Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet
33025+ * Server Adapters.
33026+ *
33027+ * Author: Ralph Roesler (rroesler@syskonnect.de)
33028+ * Mirko Lindner (mlindner@syskonnect.de)
33029+ *
33030+ * Address all question to: linux@syskonnect.de
33031+ *
33032+ * This program is free software; you can redistribute it and/or modify
33033+ * it under the terms of the GNU General Public License as published by
33034+ * the Free Software Foundation; either version 2 of the License, or
33035+ * (at your option) any later version.
33036+ *
33037+ * The information in this file is provided "AS IS" without warranty.
33038+ *
33039+ *****************************************************************************/
33040+
33041+#include <linux/proc_fs.h>
33042+#include <linux/seq_file.h>
33043+
33044+#include "h/skdrv1st.h"
33045+#include "h/skdrv2nd.h"
33046+#include "h/skversion.h"
33047+
33048+extern struct SK_NET_DEVICE *SkGeRootDev;
33049+
33050+/******************************************************************************
33051+ *
33052+ * Local Function Prototypes and Local Variables
33053+ *
33054+ *****************************************************************************/
33055+
33056+static int sk_proc_print(void *writePtr, char *format, ...);
33057+static void sk_gen_browse(void *buffer);
33058+static int len;
33059+
33060+static int sk_seq_show(struct seq_file *seq, void *v);
33061+static int sk_proc_open(struct inode *inode, struct file *file);
33062+struct file_operations sk_proc_fops = {
33063+ .owner = THIS_MODULE,
33064+ .open = sk_proc_open,
33065+ .read = seq_read,
33066+ .llseek = seq_lseek,
33067+ .release = single_release,
33068+};
33069+struct net_device *currDev = NULL;
33070+
33071+/*****************************************************************************
33072+ *
33073+ * sk_gen_browse -generic print "summaries" entry
33074+ *
33075+ * Description:
33076+ * This function fills the proc entry with statistic data about
33077+ * the ethernet device.
33078+ *
33079+ * Returns: N/A
33080+ *
33081+ */
33082+static void sk_gen_browse(
33083+void *buffer) /* buffer where the statistics will be stored in */
33084+{
33085+ struct SK_NET_DEVICE *SkgeProcDev = SkGeRootDev;
33086+ struct SK_NET_DEVICE *next;
33087+ SK_BOOL DisableStatistic = 0;
33088+ SK_PNMI_STRUCT_DATA *pPnmiStruct;
33089+ SK_PNMI_STAT *pPnmiStat;
33090+ unsigned long Flags;
33091+ unsigned int Size;
33092+ DEV_NET *pNet;
33093+ SK_AC *pAC;
33094+ char sens_msg[50];
33095+ int card_type;
33096+ int MaxSecurityCount = 0;
33097+ int t;
33098+ int i;
33099+
33100+ while (SkgeProcDev) {
33101+ MaxSecurityCount++;
33102+ if (MaxSecurityCount > 100) {
33103+ printk("Max limit for sk_proc_read security counter!\n");
33104+ return;
33105+ }
33106+ pNet = (DEV_NET*) SkgeProcDev->priv;
33107+ pAC = pNet->pAC;
33108+ next = pAC->Next;
33109+ pPnmiStruct = &pAC->PnmiStruct;
33110+ /* NetIndex in GetStruct is now required, zero is only dummy */
33111+
33112+ for (t=pAC->GIni.GIMacsFound; t > 0; t--) {
33113+ if ((pAC->GIni.GIMacsFound == 2) && pAC->RlmtNets == 1)
33114+ t--;
33115+
33116+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
33117+ Size = SK_PNMI_STRUCT_SIZE;
33118+ DisableStatistic = 0;
33119+ if (pAC->BoardLevel == SK_INIT_DATA) {
33120+ SK_MEMCPY(&(pAC->PnmiStruct), &(pAC->PnmiBackup), sizeof(SK_PNMI_STRUCT_DATA));
33121+ if (pAC->DiagModeActive == DIAG_NOTACTIVE) {
33122+ pAC->Pnmi.DiagAttached = SK_DIAG_IDLE;
33123+ }
33124+ } else {
33125+ SkPnmiGetStruct(pAC, pAC->IoBase, pPnmiStruct, &Size, t-1);
33126+ }
33127+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
33128+ if (strcmp(pAC->dev[t-1]->name, currDev->name) == 0) {
33129+ if (!pAC->GIni.GIYukon32Bit)
33130+ card_type = 64;
33131+ else
33132+ card_type = 32;
33133+
33134+ pPnmiStat = &pPnmiStruct->Stat[0];
33135+ len = sk_proc_print(buffer,
33136+ "\nDetailed statistic for device %s\n",
33137+ pAC->dev[t-1]->name);
33138+ len += sk_proc_print(buffer,
33139+ "=======================================\n");
33140+
33141+ /* Board statistics */
33142+ len += sk_proc_print(buffer,
33143+ "\nBoard statistics\n\n");
33144+ len += sk_proc_print(buffer,
33145+ "Card name %s\n",
33146+ pAC->DeviceStr);
33147+ len += sk_proc_print(buffer,
33148+ "Vendor/Device ID %x/%x\n",
33149+ pAC->PciDev->vendor,
33150+ pAC->PciDev->device);
33151+ len += sk_proc_print(buffer,
33152+ "Card type (Bit) %d\n",
33153+ card_type);
33154+
33155+ len += sk_proc_print(buffer,
33156+ "Active Port %c\n",
33157+ 'A' + pAC->Rlmt.Net[t-1].Port[pAC->Rlmt.
33158+ Net[t-1].PrefPort]->PortNumber);
33159+ len += sk_proc_print(buffer,
33160+ "Preferred Port %c\n",
33161+ 'A' + pAC->Rlmt.Net[t-1].Port[pAC->Rlmt.
33162+ Net[t-1].PrefPort]->PortNumber);
33163+
33164+ if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_STATIC) {
33165+ len += sk_proc_print(buffer,
33166+ "Interrupt Moderation static (%d ints/sec)\n",
33167+ pAC->DynIrqModInfo.MaxModIntsPerSec);
33168+ } else if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
33169+ len += sk_proc_print(buffer,
33170+ "Interrupt Moderation dynamic (%d ints/sec)\n",
33171+ pAC->DynIrqModInfo.MaxModIntsPerSec);
33172+ } else {
33173+ len += sk_proc_print(buffer,
33174+ "Interrupt Moderation disabled\n");
33175+ }
33176+
33177+ if (pAC->GIni.GIPciBus == SK_PEX_BUS) {
33178+ len += sk_proc_print(buffer,
33179+ "Bus type PCI-Express\n");
33180+ len += sk_proc_print(buffer,
33181+ "Bus width (Lanes) %d\n",
33182+ pAC->GIni.GIPexWidth);
33183+ } else {
33184+ if (pAC->GIni.GIPciBus == SK_PCIX_BUS) {
33185+ len += sk_proc_print(buffer,
33186+ "Bus type PCI-X\n");
33187+ if (pAC->GIni.GIPciMode == PCI_OS_SPD_X133) {
33188+ len += sk_proc_print(buffer,
33189+ "Bus speed (MHz) 133\n");
33190+ } else if (pAC->GIni.GIPciMode == PCI_OS_SPD_X100) {
33191+ len += sk_proc_print(buffer,
33192+ "Bus speed (MHz) 100\n");
33193+ } else if (pAC->GIni.GIPciMode == PCI_OS_SPD_X66) {
33194+ len += sk_proc_print(buffer,
33195+ "Bus speed (MHz) 66\n");
33196+ } else {
33197+ len += sk_proc_print(buffer,
33198+ "Bus speed (MHz) 33\n");
33199+ }
33200+ } else {
33201+ len += sk_proc_print(buffer,
33202+ "Bus type PCI\n");
33203+ len += sk_proc_print(buffer,
33204+ "Bus speed (MHz) %d\n",
33205+ pPnmiStruct->BusSpeed);
33206+ }
33207+ len += sk_proc_print(buffer,
33208+ "Bus width (Bit) %d\n",
33209+ pPnmiStruct->BusWidth);
33210+ }
33211+
33212+ len += sk_proc_print(buffer,
33213+ "Driver version %s (%s)\n",
33214+ VER_STRING, PATCHLEVEL);
33215+ len += sk_proc_print(buffer,
33216+ "Driver release date %s\n",
33217+ pAC->Pnmi.pDriverReleaseDate);
33218+ len += sk_proc_print(buffer,
33219+ "Hardware revision v%d.%d\n",
33220+ (pAC->GIni.GIPciHwRev >> 4) & 0x0F,
33221+ pAC->GIni.GIPciHwRev & 0x0F);
33222+
33223+ if (!netif_running(pAC->dev[t-1])) {
33224+ len += sk_proc_print(buffer,
33225+ "\n Device %s is down.\n"
33226+ " Therefore no statistics are available.\n"
33227+ " After bringing the device up (ifconfig)"
33228+ " statistics will\n"
33229+ " be displayed.\n",
33230+ pAC->dev[t-1]->name);
33231+ DisableStatistic = 1;
33232+ }
33233+
33234+ /* Display only if statistic info available */
33235+ /* Print sensor informations */
33236+ if (!DisableStatistic) {
33237+ for (i=0; i < pAC->I2c.MaxSens; i ++) {
33238+ /* Check type */
33239+ switch (pAC->I2c.SenTable[i].SenType) {
33240+ case 1:
33241+ strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc);
33242+ strcat(sens_msg, " (C)");
33243+ len += sk_proc_print(buffer,
33244+ "%-25s %d.%02d\n",
33245+ sens_msg,
33246+ pAC->I2c.SenTable[i].SenValue / 10,
33247+ pAC->I2c.SenTable[i].SenValue %
33248+ 10);
33249+
33250+ strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc);
33251+ strcat(sens_msg, " (F)");
33252+ len += sk_proc_print(buffer,
33253+ "%-25s %d.%02d\n",
33254+ sens_msg,
33255+ ((((pAC->I2c.SenTable[i].SenValue)
33256+ *10)*9)/5 + 3200)/100,
33257+ ((((pAC->I2c.SenTable[i].SenValue)
33258+ *10)*9)/5 + 3200) % 10);
33259+ break;
33260+ case 2:
33261+ strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc);
33262+ strcat(sens_msg, " (V)");
33263+ len += sk_proc_print(buffer,
33264+ "%-25s %d.%03d\n",
33265+ sens_msg,
33266+ pAC->I2c.SenTable[i].SenValue / 1000,
33267+ pAC->I2c.SenTable[i].SenValue % 1000);
33268+ break;
33269+ case 3:
33270+ strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc);
33271+ strcat(sens_msg, " (rpm)");
33272+ len += sk_proc_print(buffer,
33273+ "%-25s %d\n",
33274+ sens_msg,
33275+ pAC->I2c.SenTable[i].SenValue);
33276+ break;
33277+ default:
33278+ break;
33279+ }
33280+ }
33281+
33282+ /*Receive statistics */
33283+ len += sk_proc_print(buffer,
33284+ "\nReceive statistics\n\n");
33285+
33286+ len += sk_proc_print(buffer,
33287+ "Received bytes %Lu\n",
33288+ (unsigned long long) pPnmiStat->StatRxOctetsOkCts);
33289+ len += sk_proc_print(buffer,
33290+ "Received packets %Lu\n",
33291+ (unsigned long long) pPnmiStat->StatRxOkCts);
33292+#if 0
33293+ if (pAC->GIni.GP[0].PhyType == SK_PHY_XMAC &&
33294+ pAC->HWRevision < 12) {
33295+ pPnmiStruct->InErrorsCts = pPnmiStruct->InErrorsCts -
33296+ pPnmiStat->StatRxShortsCts;
33297+ pPnmiStat->StatRxShortsCts = 0;
33298+ }
33299+#endif
33300+ if (pAC->dev[t-1]->mtu > 1500)
33301+ pPnmiStruct->InErrorsCts = pPnmiStruct->InErrorsCts -
33302+ pPnmiStat->StatRxTooLongCts;
33303+
33304+ len += sk_proc_print(buffer,
33305+ "Receive errors %Lu\n",
33306+ (unsigned long long) pPnmiStruct->InErrorsCts);
33307+ len += sk_proc_print(buffer,
33308+ "Receive dropped %Lu\n",
33309+ (unsigned long long) pPnmiStruct->RxNoBufCts);
33310+ len += sk_proc_print(buffer,
33311+ "Received multicast %Lu\n",
33312+ (unsigned long long) pPnmiStat->StatRxMulticastOkCts);
33313+#ifdef ADVANCED_STATISTIC_OUTPUT
33314+ len += sk_proc_print(buffer,
33315+ "Receive error types\n");
33316+ len += sk_proc_print(buffer,
33317+ " length %Lu\n",
33318+ (unsigned long long) pPnmiStat->StatRxRuntCts);
33319+ len += sk_proc_print(buffer,
33320+ " buffer overflow %Lu\n",
33321+ (unsigned long long) pPnmiStat->StatRxFifoOverflowCts);
33322+ len += sk_proc_print(buffer,
33323+ " bad crc %Lu\n",
33324+ (unsigned long long) pPnmiStat->StatRxFcsCts);
33325+ len += sk_proc_print(buffer,
33326+ " framing %Lu\n",
33327+ (unsigned long long) pPnmiStat->StatRxFramingCts);
33328+ len += sk_proc_print(buffer,
33329+ " missed frames %Lu\n",
33330+ (unsigned long long) pPnmiStat->StatRxMissedCts);
33331+
33332+ if (pAC->dev[t-1]->mtu > 1500)
33333+ pPnmiStat->StatRxTooLongCts = 0;
33334+
33335+ len += sk_proc_print(buffer,
33336+ " too long %Lu\n",
33337+ (unsigned long long) pPnmiStat->StatRxTooLongCts);
33338+ len += sk_proc_print(buffer,
33339+ " carrier extension %Lu\n",
33340+ (unsigned long long) pPnmiStat->StatRxCextCts);
33341+ len += sk_proc_print(buffer,
33342+ " too short %Lu\n",
33343+ (unsigned long long) pPnmiStat->StatRxShortsCts);
33344+ len += sk_proc_print(buffer,
33345+ " symbol %Lu\n",
33346+ (unsigned long long) pPnmiStat->StatRxSymbolCts);
33347+ len += sk_proc_print(buffer,
33348+ " LLC MAC size %Lu\n",
33349+ (unsigned long long) pPnmiStat->StatRxIRLengthCts);
33350+ len += sk_proc_print(buffer,
33351+ " carrier event %Lu\n",
33352+ (unsigned long long) pPnmiStat->StatRxCarrierCts);
33353+ len += sk_proc_print(buffer,
33354+ " jabber %Lu\n",
33355+ (unsigned long long) pPnmiStat->StatRxJabberCts);
33356+#endif
33357+
33358+ /*Transmit statistics */
33359+ len += sk_proc_print(buffer,
33360+ "\nTransmit statistics\n\n");
33361+
33362+ len += sk_proc_print(buffer,
33363+ "Transmitted bytes %Lu\n",
33364+ (unsigned long long) pPnmiStat->StatTxOctetsOkCts);
33365+ len += sk_proc_print(buffer,
33366+ "Transmitted packets %Lu\n",
33367+ (unsigned long long) pPnmiStat->StatTxOkCts);
33368+ len += sk_proc_print(buffer,
33369+ "Transmit errors %Lu\n",
33370+ (unsigned long long) pPnmiStat->StatTxSingleCollisionCts);
33371+ len += sk_proc_print(buffer,
33372+ "Transmit dropped %Lu\n",
33373+ (unsigned long long) pPnmiStruct->TxNoBufCts);
33374+ len += sk_proc_print(buffer,
33375+ "Transmit collisions %Lu\n",
33376+ (unsigned long long) pPnmiStat->StatTxSingleCollisionCts);
33377+#ifdef ADVANCED_STATISTIC_OUTPUT
33378+ len += sk_proc_print(buffer,
33379+ "Transmit error types\n");
33380+ len += sk_proc_print(buffer,
33381+ " excessive collision %ld\n",
33382+ pAC->stats.tx_aborted_errors);
33383+ len += sk_proc_print(buffer,
33384+ " carrier %Lu\n",
33385+ (unsigned long long) pPnmiStat->StatTxCarrierCts);
33386+ len += sk_proc_print(buffer,
33387+ " fifo underrun %Lu\n",
33388+ (unsigned long long) pPnmiStat->StatTxFifoUnderrunCts);
33389+ len += sk_proc_print(buffer,
33390+ " heartbeat %Lu\n",
33391+ (unsigned long long) pPnmiStat->StatTxCarrierCts);
33392+ len += sk_proc_print(buffer,
33393+ " window %ld\n",
33394+ pAC->stats.tx_window_errors);
33395+#endif
33396+ } /* if (!DisableStatistic) */
33397+
33398+ } /* if (strcmp(pACname, currDeviceName) == 0) */
33399+ }
33400+ SkgeProcDev = next;
33401+ }
33402+}
33403+
33404+/*****************************************************************************
33405+ *
33406+ * sk_proc_print - generic line print
33407+ *
33408+ * Description:
33409+ * This function fills the proc entry with statistic data about the
33410+ * ethernet device.
33411+ *
33412+ * Returns:
33413+ * the number of bytes written
33414+ *
33415+ */
33416+static int sk_proc_print(
33417+void *writePtr, /* the buffer pointer */
33418+char *format, /* the format of the string */
33419+...) /* variable list of arguments */
33420+{
33421+#define MAX_LEN_SINGLE_LINE 256
33422+ char str[MAX_LEN_SINGLE_LINE];
33423+ va_list a_start;
33424+ int lenght = 0;
33425+
33426+ struct seq_file *seq = (struct seq_file *) writePtr;
33427+
33428+ SK_MEMSET(str, 0, MAX_LEN_SINGLE_LINE);
33429+
33430+ va_start(a_start, format);
33431+ vsprintf(str, format, a_start);
33432+ va_end(a_start);
33433+
33434+ lenght = strlen(str);
33435+
33436+ seq_printf(seq, str);
33437+ return lenght;
33438+}
33439+
33440+/*****************************************************************************
33441+ *
33442+ * sk_seq_show - show proc information of a particular adapter
33443+ *
33444+ * Description:
33445+ * This function fills the proc entry with statistic data about the
33446+ * ethernet device. It invokes the generic sk_gen_browse() to print
33447+ * out all items one per one.
33448+ *
33449+ * Returns:
33450+ * the number of bytes written
33451+ *
33452+ */
33453+static int sk_seq_show(
33454+struct seq_file *seq, /* the sequence pointer */
33455+void *v) /* additional pointer */
33456+{
33457+ void *castedBuffer = (void *) seq;
33458+ currDev = seq->private;
33459+ sk_gen_browse(castedBuffer);
33460+ return 0;
33461+}
33462+
33463+/*****************************************************************************
33464+ *
33465+ * sk_proc_open - register the show function when proc is open'ed
33466+ *
33467+ * Description:
33468+ * This function is called whenever a sk98lin proc file is queried.
33469+ *
33470+ * Returns:
33471+ * the return value of single_open()
33472+ *
33473+ */
33474+static int sk_proc_open(
33475+struct inode *inode, /* the inode of the file */
33476+struct file *file) /* the file pointer itself */
33477+{
33478+ return single_open(file, sk_seq_show, PDE(inode)->data);
33479+}
33480+
33481+/*******************************************************************************
33482+ *
33483+ * End of file
33484+ *
33485+ ******************************************************************************/
33486diff -urN linux-2.6.17.orig/drivers/net/sk98lin/skqueue.c linux-2.6.17/drivers/net/sk98lin/skqueue.c
33487--- linux-2.6.17.orig/drivers/net/sk98lin/skqueue.c 2006-06-22 13:17:16.000000000 +0200
33488+++ linux-2.6.17/drivers/net/sk98lin/skqueue.c 2006-04-27 11:43:44.000000000 +0200
33489@@ -2,8 +2,8 @@
33490 *
33491 * Name: skqueue.c
33492 * Project: Gigabit Ethernet Adapters, Event Scheduler Module
33493- * Version: $Revision$
33494- * Date: $Date$
33495+ * Version: $Revision$
33496+ * Date: $Date$
33497 * Purpose: Management of an event queue.
33498 *
33499 ******************************************************************************/
33500@@ -28,7 +28,7 @@
33501 */
33502 #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
33503 static const char SysKonnectFileId[] =
33504- "@(#) $Id$ (C) Marvell.";
33505+ "@(#) $Id$ (C) Marvell.";
33506 #endif
33507
33508 #include "h/skdrv1st.h" /* Driver Specific Definitions */
33509@@ -48,10 +48,16 @@
33510
33511 #define PRINTF(a,b,c)
33512
33513-/*
33514- * init event queue management
33515+/******************************************************************************
33516+ *
33517+ * SkEventInit() - init event queue management
33518 *
33519- * Must be called during init level 0.
33520+ * Description:
33521+ * This function initializes event queue management.
33522+ * It must be called during init level 0.
33523+ *
33524+ * Returns:
33525+ * nothing
33526 */
33527 void SkEventInit(
33528 SK_AC *pAC, /* Adapter context */
33529@@ -67,8 +73,17 @@
33530 }
33531 }
33532
33533-/*
33534- * add event to queue
33535+/******************************************************************************
33536+ *
33537+ * SkEventQueue() - add event to queue
33538+ *
33539+ * Description:
33540+ * This function adds an event to the event queue.
33541+ * At least Init Level 1 is required to queue events,
33542+ * but will be scheduled add Init Level 2.
33543+ *
33544+ * returns:
33545+ * nothing
33546 */
33547 void SkEventQueue(
33548 SK_AC *pAC, /* Adapters context */
33549@@ -76,26 +91,45 @@
33550 SK_U32 Event, /* Event to be queued */
33551 SK_EVPARA Para) /* Event parameter */
33552 {
33553- pAC->Event.EvPut->Class = Class;
33554- pAC->Event.EvPut->Event = Event;
33555- pAC->Event.EvPut->Para = Para;
33556+
33557+ if (pAC->GIni.GILevel == SK_INIT_DATA) {
33558+ SK_ERR_LOG(pAC, SK_ERRCL_NORES, SKERR_Q_E003, SKERR_Q_E003MSG);
33559+ }
33560+ else {
33561+ pAC->Event.EvPut->Class = Class;
33562+ pAC->Event.EvPut->Event = Event;
33563+ pAC->Event.EvPut->Para = Para;
33564
33565- if (++pAC->Event.EvPut == &pAC->Event.EvQueue[SK_MAX_EVENT])
33566- pAC->Event.EvPut = pAC->Event.EvQueue;
33567+ if (++pAC->Event.EvPut == &pAC->Event.EvQueue[SK_MAX_EVENT])
33568+ pAC->Event.EvPut = pAC->Event.EvQueue;
33569
33570- if (pAC->Event.EvPut == pAC->Event.EvGet) {
33571- SK_ERR_LOG(pAC, SK_ERRCL_NORES, SKERR_Q_E001, SKERR_Q_E001MSG);
33572+ if (pAC->Event.EvPut == pAC->Event.EvGet) {
33573+ SK_ERR_LOG(pAC, SK_ERRCL_NORES, SKERR_Q_E001, SKERR_Q_E001MSG);
33574+ }
33575 }
33576 }
33577
33578-/*
33579- * event dispatcher
33580- * while event queue is not empty
33581- * get event from queue
33582- * send command to state machine
33583- * end
33584- * return error reported by individual Event function
33585- * 0 if no error occured.
33586+/******************************************************************************
33587+ *
33588+ * SkEventDispatcher() - Event Dispatcher
33589+ *
33590+ * Description:
33591+ * The event dispatcher performs the following operations:
33592+ * o while event queue is not empty
33593+ * - get event from queue
33594+ * - send event to state machine
33595+ * end
33596+ *
33597+ * CAUTION:
33598+ * The event functions MUST report an error if performing a reinitialization
33599+ * of the event queue, e.g. performing level Init 0..2 while in dispatcher
33600+ * call!
33601+ * ANY OTHER return value delays scheduling the other events in the
33602+ * queue. In this case the event blocks the queue until
33603+ * the error condition is cleared!
33604+ *
33605+ * Returns:
33606+ * The return value error reported by individual event function
33607 */
33608 int SkEventDispatcher(
33609 SK_AC *pAC, /* Adapters Context */
33610@@ -105,6 +139,10 @@
33611 SK_U32 Class;
33612 int Rtv;
33613
33614+ if (pAC->GIni.GILevel != SK_INIT_RUN) {
33615+ SK_ERR_LOG(pAC, SK_ERRCL_NORES, SKERR_Q_E005, SKERR_Q_E005MSG);
33616+ }
33617+
33618 pEv = pAC->Event.EvGet;
33619
33620 PRINTF("dispatch get %x put %x\n", pEv, pAC->Event.ev_put);
33621@@ -152,6 +190,11 @@
33622 Rtv = SkFdEvent(pAC, Ioc, pEv->Event, pEv->Para);
33623 break;
33624 #endif /* SK_USE_LAC_EV */
33625+#ifdef SK_ASF
33626+ case SKGE_ASF :
33627+ Rtv = SkAsfEvent(pAC,Ioc,pEv->Event,pEv->Para);
33628+ break ;
33629+#endif
33630 #ifdef SK_USE_CSUM
33631 case SKGE_CSUM :
33632 Rtv = SkCsEvent(pAC, Ioc, pEv->Event, pEv->Para);
33633@@ -163,6 +206,20 @@
33634 }
33635
33636 if (Rtv != 0) {
33637+ /*
33638+ * Special Case: See CAUTION statement above.
33639+ * We assume the event queue is reset.
33640+ */
33641+ if (pAC->Event.EvGet != pAC->Event.EvQueue &&
33642+ pAC->Event.EvGet != pEv) {
33643+ /*
33644+ * Create an error log entry if the
33645+ * event queue isn't reset.
33646+ * In this case it may be blocked.
33647+ */
33648+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_Q_E004, SKERR_Q_E004MSG);
33649+ }
33650+
33651 return(Rtv);
33652 }
33653
33654diff -urN linux-2.6.17.orig/drivers/net/sk98lin/skrlmt.c linux-2.6.17/drivers/net/sk98lin/skrlmt.c
33655--- linux-2.6.17.orig/drivers/net/sk98lin/skrlmt.c 2006-06-22 13:17:16.000000000 +0200
33656+++ linux-2.6.17/drivers/net/sk98lin/skrlmt.c 2006-04-27 11:43:44.000000000 +0200
33657@@ -2,14 +2,15 @@
33658 *
33659 * Name: skrlmt.c
33660 * Project: GEnesis, PCI Gigabit Ethernet Adapter
33661- * Version: $Revision$
33662- * Date: $Date$
33663+ * Version: $Revision$
33664+ * Date: $Date$
33665 * Purpose: Manage links on SK-NET Adapters, esp. redundant ones.
33666 *
33667 ******************************************************************************/
33668
33669 /******************************************************************************
33670 *
33671+ * LICENSE:
33672 * (C)Copyright 1998-2002 SysKonnect GmbH.
33673 * (C)Copyright 2002-2003 Marvell.
33674 *
33675@@ -19,6 +20,7 @@
33676 * (at your option) any later version.
33677 *
33678 * The information in this file is provided "AS IS" without warranty.
33679+ * /LICENSE
33680 *
33681 ******************************************************************************/
33682
33683@@ -39,7 +41,7 @@
33684
33685 #ifndef lint
33686 static const char SysKonnectFileId[] =
33687- "@(#) $Id$ (C) Marvell.";
33688+ "@(#) $Id$ (C) Marvell.";
33689 #endif /* !defined(lint) */
33690
33691 #define __SKRLMT_C
33692@@ -282,6 +284,7 @@
33693
33694 SK_MAC_ADDR SkRlmtMcAddr = {{0x01, 0x00, 0x5A, 0x52, 0x4C, 0x4D}};
33695 SK_MAC_ADDR BridgeMcAddr = {{0x01, 0x80, 0xC2, 0x00, 0x00, 0x00}};
33696+SK_MAC_ADDR BcAddr = {{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}};
33697
33698 /* local variables ************************************************************/
33699
33700@@ -349,7 +352,7 @@
33701 SK_BOOL PhysicalAMacAddressSet;
33702
33703 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_INIT,
33704- ("RLMT Init level %d.\n", Level))
33705+ ("RLMT Init level %d.\n", Level));
33706
33707 switch (Level) {
33708 case SK_INIT_DATA: /* Initialize data structures. */
33709@@ -389,7 +392,7 @@
33710
33711 case SK_INIT_IO: /* GIMacsFound first available here. */
33712 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_INIT,
33713- ("RLMT: %d MACs were detected.\n", pAC->GIni.GIMacsFound))
33714+ ("RLMT: %d MACs were detected.\n", pAC->GIni.GIMacsFound));
33715
33716 pAC->Rlmt.Net[0].NumPorts = pAC->GIni.GIMacsFound;
33717
33718@@ -511,7 +514,7 @@
33719 }
33720
33721 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33722- ("SkRlmtBuildCheckChain.\n"))
33723+ ("SkRlmtBuildCheckChain.\n"));
33724
33725 NumMacsUp = 0;
33726
33727@@ -557,7 +560,7 @@
33728 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33729 ("Port %d checks %d other ports: %2X.\n", i,
33730 pAC->Rlmt.Net[NetIdx].Port[i]->PortsChecked,
33731- pAC->Rlmt.Net[NetIdx].Port[i]->PortCheck[0].CheckAddr.a[5]))
33732+ pAC->Rlmt.Net[NetIdx].Port[i]->PortCheck[0].CheckAddr.a[5]));
33733 }
33734 #endif /* DEBUG */
33735
33736@@ -603,7 +606,7 @@
33737 if ((CheckSrc == 0) || (CheckDest == 0)) {
33738 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_ERR,
33739 ("SkRlmtBuildPacket: Invalid %s%saddr.\n",
33740- (CheckSrc == 0 ? "Src" : ""), (CheckDest == 0 ? "Dest" : "")))
33741+ (CheckSrc == 0 ? "Src" : ""), (CheckDest == 0 ? "Dest" : "")));
33742 }
33743 #endif
33744
33745@@ -795,7 +798,7 @@
33746
33747 SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para);
33748 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_TX,
33749- ("SkRlmtSend: BPDU Packet on Port %u.\n", PortNumber))
33750+ ("SkRlmtSend: BPDU Packet on Port %u.\n", PortNumber));
33751 }
33752 }
33753 return;
33754@@ -834,7 +837,7 @@
33755 * Bring it up.
33756 */
33757 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33758- ("SkRlmtPacketReceive: Received on PortDown.\n"))
33759+ ("SkRlmtPacketReceive: Received on PortDown.\n"));
33760
33761 pRPort->PortState = SK_RLMT_PS_GOING_UP;
33762 pRPort->GuTimeStamp = SkOsGetTime(pAC);
33763@@ -848,7 +851,7 @@
33764 } /* PortDown && !SuspectTx */
33765 else if (pRPort->CheckingState & SK_RLMT_PCS_RX) {
33766 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33767- ("SkRlmtPacketReceive: Stop bringing port down.\n"))
33768+ ("SkRlmtPacketReceive: Stop bringing port down.\n"));
33769 SkTimerStop(pAC, IoC, &pRPort->DownRxTimer);
33770 pRPort->CheckingState &= ~SK_RLMT_PCS_RX;
33771 /* pAC->Rlmt.CheckSwitch = SK_TRUE; */
33772@@ -895,7 +898,7 @@
33773 pRPort = &pAC->Rlmt.Port[PortNumber];
33774
33775 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33776- ("SkRlmtPacketReceive: PortNumber == %d.\n", PortNumber))
33777+ ("SkRlmtPacketReceive: PortNumber == %d.\n", PortNumber));
33778
33779 pRPacket = (SK_RLMT_PACKET*)pMb->pData;
33780 pSPacket = (SK_SPTREE_PACKET*)pRPacket;
33781@@ -916,7 +919,7 @@
33782
33783 /* Not sent to current MAC or registered MC address => Trash it. */
33784 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33785- ("SkRlmtPacketReceive: Not for me.\n"))
33786+ ("SkRlmtPacketReceive: Not for me.\n"));
33787
33788 SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
33789 return;
33790@@ -954,7 +957,7 @@
33791 pRPacket->Indicator[5] == SK_RLMT_INDICATOR5 &&
33792 pRPacket->Indicator[6] == SK_RLMT_INDICATOR6) {
33793 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33794- ("SkRlmtPacketReceive: Duplicate MAC Address.\n"))
33795+ ("SkRlmtPacketReceive: Duplicate MAC Address.\n"));
33796
33797 /* Error Log entry. */
33798 SK_ERR_LOG(pAC, SK_ERRCL_COMM, SKERR_RLMT_E006, SKERR_RLMT_E006_MSG);
33799@@ -962,7 +965,7 @@
33800 else {
33801 /* Simply trash it. */
33802 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33803- ("SkRlmtPacketReceive: Sent by me.\n"))
33804+ ("SkRlmtPacketReceive: Sent by me.\n"));
33805 }
33806
33807 SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
33808@@ -1006,7 +1009,7 @@
33809 #endif /* 0 */
33810
33811 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33812- ("SkRlmtPacketReceive: Announce.\n"))
33813+ ("SkRlmtPacketReceive: Announce.\n"));
33814
33815 SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
33816 break;
33817@@ -1014,7 +1017,7 @@
33818 case SK_PACKET_ALIVE:
33819 if (pRPacket->SSap & LLC_COMMAND_RESPONSE_BIT) {
33820 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33821- ("SkRlmtPacketReceive: Alive Reply.\n"))
33822+ ("SkRlmtPacketReceive: Alive Reply.\n"));
33823
33824 if (!(pAC->Addr.Port[PortNumber].PromMode & SK_PROM_MODE_LLC) ||
33825 SK_ADDR_EQUAL(
33826@@ -1045,7 +1048,7 @@
33827 }
33828 else { /* Alive Request Packet. */
33829 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33830- ("SkRlmtPacketReceive: Alive Request.\n"))
33831+ ("SkRlmtPacketReceive: Alive Request.\n"));
33832
33833 pRPort->RxHelloCts++;
33834
33835@@ -1064,7 +1067,7 @@
33836
33837 case SK_PACKET_CHECK_TX:
33838 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33839- ("SkRlmtPacketReceive: Check your tx line.\n"))
33840+ ("SkRlmtPacketReceive: Check your tx line.\n"));
33841
33842 /* A port checking us requests us to check our tx line. */
33843 pRPort->CheckingState |= SK_RLMT_PCS_TX;
33844@@ -1087,7 +1090,7 @@
33845
33846 case SK_PACKET_ADDR_CHANGED:
33847 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33848- ("SkRlmtPacketReceive: Address Change.\n"))
33849+ ("SkRlmtPacketReceive: Address Change.\n"));
33850
33851 /* Build the check chain. */
33852 SkRlmtBuildCheckChain(pAC, pRPort->Net->NetNumber);
33853@@ -1096,7 +1099,7 @@
33854
33855 default:
33856 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33857- ("SkRlmtPacketReceive: Unknown RLMT packet.\n"))
33858+ ("SkRlmtPacketReceive: Unknown RLMT packet.\n"));
33859
33860 /* RA;:;: ??? */
33861 SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
33862@@ -1106,7 +1109,7 @@
33863 pSPacket->Ctrl == SK_RLMT_SPT_CTRL &&
33864 (pSPacket->SSap & ~LLC_COMMAND_RESPONSE_BIT) == SK_RLMT_SPT_SSAP) {
33865 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33866- ("SkRlmtPacketReceive: BPDU Packet.\n"))
33867+ ("SkRlmtPacketReceive: BPDU Packet.\n"));
33868
33869 /* Spanning Tree packet. */
33870 pRPort->RxSpHelloCts++;
33871@@ -1138,7 +1141,7 @@
33872 pRPort->Root.Id[0], pRPort->Root.Id[1],
33873 pRPort->Root.Id[2], pRPort->Root.Id[3],
33874 pRPort->Root.Id[4], pRPort->Root.Id[5],
33875- pRPort->Root.Id[6], pRPort->Root.Id[7]))
33876+ pRPort->Root.Id[6], pRPort->Root.Id[7]));
33877 }
33878
33879 SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
33880@@ -1149,7 +1152,7 @@
33881 }
33882 else {
33883 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
33884- ("SkRlmtPacketReceive: Unknown Packet Type.\n"))
33885+ ("SkRlmtPacketReceive: Unknown Packet Type.\n"));
33886
33887 /* Unknown packet. */
33888 SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
33889@@ -1231,7 +1234,7 @@
33890 if ((pRPort->PacketsPerTimeSlot - pRPort->BpduPacketsPerTimeSlot) == 0) {
33891 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33892 ("SkRlmtCheckPort %d: No (%d) receives in last time slot.\n",
33893- PortNumber, pRPort->PacketsPerTimeSlot))
33894+ PortNumber, pRPort->PacketsPerTimeSlot));
33895
33896 /*
33897 * Check segmentation if there was no receive at least twice
33898@@ -1248,7 +1251,7 @@
33899
33900 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33901 ("SkRlmtCheckPort: PortsSuspect %d, PcsRx %d.\n",
33902- pRPort->PortsSuspect, pRPort->CheckingState & SK_RLMT_PCS_RX))
33903+ pRPort->PortsSuspect, pRPort->CheckingState & SK_RLMT_PCS_RX));
33904
33905 if (pRPort->PortState != SK_RLMT_PS_DOWN) {
33906 NewTimeout = TO_SHORTEN(pAC->Rlmt.Port[PortNumber].Net->TimeoutValue);
33907@@ -1294,7 +1297,7 @@
33908 ("SkRlmtCheckPort %d: %d (%d) receives in last time slot.\n",
33909 PortNumber,
33910 pRPort->PacketsPerTimeSlot - pRPort->BpduPacketsPerTimeSlot,
33911- pRPort->PacketsPerTimeSlot))
33912+ pRPort->PacketsPerTimeSlot));
33913
33914 SkRlmtPortReceives(pAC, IoC, PortNumber);
33915 if (pAC->Rlmt.CheckSwitch) {
33916@@ -1344,7 +1347,7 @@
33917 i,
33918 pAC->Rlmt.Port[i].PortDown, pAC->Rlmt.Port[i].PortNoRx,
33919 *((SK_U32*)(&pAC->Rlmt.Port[i].BcTimeStamp) + OFFS_HI32),
33920- *((SK_U32*)(&pAC->Rlmt.Port[i].BcTimeStamp) + OFFS_LO32)))
33921+ *((SK_U32*)(&pAC->Rlmt.Port[i].BcTimeStamp) + OFFS_LO32)));
33922
33923 if (!pAC->Rlmt.Port[i].PortDown && !pAC->Rlmt.Port[i].PortNoRx) {
33924 if (!PortFound || pAC->Rlmt.Port[i].BcTimeStamp > BcTimeStamp) {
33925@@ -1357,7 +1360,7 @@
33926
33927 if (PortFound) {
33928 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33929- ("Port %d received the last broadcast.\n", *pSelect))
33930+ ("Port %d received the last broadcast.\n", *pSelect));
33931
33932 /* Look if another port's time stamp is similar. */
33933 for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) {
33934@@ -1372,7 +1375,7 @@
33935 PortFound = SK_FALSE;
33936
33937 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33938- ("Port %d received a broadcast at a similar time.\n", i))
33939+ ("Port %d received a broadcast at a similar time.\n", i));
33940 break;
33941 }
33942 }
33943@@ -1384,7 +1387,7 @@
33944 ("SK_RLMT_SELECT_BCRX found Port %d receiving the substantially "
33945 "latest broadcast (%u).\n",
33946 *pSelect,
33947- BcTimeStamp - pAC->Rlmt.Port[1 - *pSelect].BcTimeStamp))
33948+ BcTimeStamp - pAC->Rlmt.Port[1 - *pSelect].BcTimeStamp));
33949 }
33950 #endif /* DEBUG */
33951
33952@@ -1433,7 +1436,7 @@
33953 PortFound = SK_TRUE;
33954 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33955 ("SK_RLMT_SELECT_NOTSUSPECT found Port %d up and not check RX.\n",
33956- *pSelect))
33957+ *pSelect));
33958 break;
33959 }
33960 }
33961@@ -1482,7 +1485,7 @@
33962 }
33963 PortFound = SK_TRUE;
33964 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33965- ("SK_RLMT_SELECT_UP found Port %d up.\n", *pSelect))
33966+ ("SK_RLMT_SELECT_UP found Port %d up.\n", *pSelect));
33967 break;
33968 }
33969 }
33970@@ -1543,7 +1546,7 @@
33971 }
33972
33973 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33974- ("SK_RLMT_SELECT_GOINGUP found Port %d going up.\n", *pSelect))
33975+ ("SK_RLMT_SELECT_GOINGUP found Port %d going up.\n", *pSelect));
33976 return (SK_TRUE);
33977 } /* SkRlmtSelectGoingUp */
33978
33979@@ -1589,7 +1592,7 @@
33980 }
33981 PortFound = SK_TRUE;
33982 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
33983- ("SK_RLMT_SELECT_DOWN found Port %d down.\n", *pSelect))
33984+ ("SK_RLMT_SELECT_DOWN found Port %d down.\n", *pSelect));
33985 break;
33986 }
33987 }
33988@@ -1679,16 +1682,19 @@
33989 Para.Para32[1] = NetIdx;
33990 SkEventQueue(pAC, SKGE_DRV, SK_DRV_NET_UP, Para);
33991
33992- if ((pAC->Rlmt.Net[NetIdx].RlmtMode & SK_RLMT_TRANSPARENT) == 0 &&
33993- (Para.pParaPtr = SkRlmtBuildPacket(pAC, IoC,
33994- pAC->Rlmt.Net[NetIdx].Port[i]->PortNumber,
33995- SK_PACKET_ANNOUNCE, &pAC->Addr.Net[NetIdx].
33996- CurrentMacAddress, &SkRlmtMcAddr)) != NULL) {
33997- /*
33998- * Send announce packet to RLMT multicast address to force
33999- * switches to learn the new location of the logical MAC address.
34000- */
34001- SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para);
34002+ if (pAC->Rlmt.NumNets == 1) {
34003+ if ((pAC->Rlmt.Net[NetIdx].RlmtMode & SK_RLMT_TRANSPARENT) == 0 &&
34004+ (Para.pParaPtr = SkRlmtBuildPacket(pAC, IoC,
34005+ pAC->Rlmt.Net[NetIdx].Port[i]->PortNumber,
34006+ SK_PACKET_ANNOUNCE, &pAC->Addr.Net[NetIdx].
34007+ CurrentMacAddress, &SkRlmtMcAddr)) != NULL) {
34008+
34009+ /*
34010+ * Send announce packet to RLMT multicast address to force
34011+ * switches to learn the new location of the logical MAC address.
34012+ */
34013+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para);
34014+ }
34015 }
34016 }
34017 else {
34018@@ -1787,7 +1793,7 @@
34019
34020 if (Para.Para32[1] != Active) {
34021 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34022- ("Active: %d, Para1: %d.\n", Active, Para.Para32[1]))
34023+ ("Active: %d, Para1: %d.\n", Active, Para.Para32[1]));
34024 pAC->Rlmt.Net[NetIdx].ActivePort = Para.Para32[1];
34025 Para.Para32[0] = pAC->Rlmt.Net[NetIdx].
34026 Port[Para.Para32[0]]->PortNumber;
34027@@ -1867,7 +1873,7 @@
34028 pNet->Port[i]->Root.Id[0], pNet->Port[i]->Root.Id[1],
34029 pNet->Port[i]->Root.Id[2], pNet->Port[i]->Root.Id[3],
34030 pNet->Port[i]->Root.Id[4], pNet->Port[i]->Root.Id[5],
34031- pNet->Port[i]->Root.Id[6], pNet->Port[i]->Root.Id[7]))
34032+ pNet->Port[i]->Root.Id[6], pNet->Port[i]->Root.Id[7]));
34033
34034 if (!pNet->RootIdSet) {
34035 pNet->Root = pNet->Port[i]->Root;
34036@@ -1962,13 +1968,13 @@
34037 SK_U32 i;
34038
34039 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34040- ("SK_RLMT_PORTSTART_TIMEOUT Port %d Event BEGIN.\n", Para.Para32[0]))
34041+ ("SK_RLMT_PORTSTART_TIMEOUT Port %d Event BEGIN.\n", Para.Para32[0]));
34042
34043 if (Para.Para32[1] != (SK_U32)-1) {
34044 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34045- ("Bad Parameter.\n"))
34046+ ("Bad Parameter.\n"));
34047 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34048- ("SK_RLMT_PORTSTART_TIMEOUT Event EMPTY.\n"))
34049+ ("SK_RLMT_PORTSTART_TIMEOUT Event EMPTY.\n"));
34050 return;
34051 }
34052
34053@@ -1989,7 +1995,7 @@
34054 }
34055
34056 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34057- ("SK_RLMT_PORTSTART_TIMEOUT Event END.\n"))
34058+ ("SK_RLMT_PORTSTART_TIMEOUT Event END.\n"));
34059 } /* SkRlmtEvtPortStartTim */
34060
34061
34062@@ -2017,21 +2023,21 @@
34063 SK_EVPARA Para2;
34064
34065 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34066- ("SK_RLMT_LINK_UP Port %d Event BEGIN.\n", Para.Para32[0]))
34067+ ("SK_RLMT_LINK_UP Port %d Event BEGIN.\n", Para.Para32[0]));
34068
34069 pRPort = &pAC->Rlmt.Port[Para.Para32[0]];
34070 if (!pRPort->PortStarted) {
34071 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_RLMT_E008, SKERR_RLMT_E008_MSG);
34072
34073 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34074- ("SK_RLMT_LINK_UP Event EMPTY.\n"))
34075+ ("SK_RLMT_LINK_UP Event EMPTY.\n"));
34076 return;
34077 }
34078
34079 if (!pRPort->LinkDown) {
34080 /* RA;:;: Any better solution? */
34081 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34082- ("SK_RLMT_LINK_UP Event EMPTY.\n"))
34083+ ("SK_RLMT_LINK_UP Event EMPTY.\n"));
34084 return;
34085 }
34086
34087@@ -2081,16 +2087,19 @@
34088 Para2.Para32[1] = (SK_U32)-1;
34089 SkTimerStart(pAC, IoC, &pRPort->UpTimer, SK_RLMT_PORTUP_TIM_VAL,
34090 SKGE_RLMT, SK_RLMT_PORTUP_TIM, Para2);
34091-
34092+
34093 /* Later: if (pAC->Rlmt.RlmtMode & SK_RLMT_CHECK_LOC_LINK) && */
34094- if ((pRPort->Net->RlmtMode & SK_RLMT_TRANSPARENT) == 0 &&
34095- (pRPort->Net->RlmtMode & SK_RLMT_CHECK_LINK) != 0 &&
34096- (Para2.pParaPtr =
34097- SkRlmtBuildPacket(pAC, IoC, Para.Para32[0], SK_PACKET_ANNOUNCE,
34098- &pAC->Addr.Port[Para.Para32[0]].CurrentMacAddress, &SkRlmtMcAddr)
34099- ) != NULL) {
34100- /* Send "new" packet to RLMT multicast address. */
34101- SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para2);
34102+ if (pAC->Rlmt.NumNets == 1) {
34103+ if ((pRPort->Net->RlmtMode & SK_RLMT_TRANSPARENT) == 0 &&
34104+ (pRPort->Net->RlmtMode & SK_RLMT_CHECK_LINK) != 0 &&
34105+ (Para2.pParaPtr =
34106+ SkRlmtBuildPacket(pAC, IoC, Para.Para32[0], SK_PACKET_ANNOUNCE,
34107+ &pAC->Addr.Port[Para.Para32[0]].CurrentMacAddress, &SkRlmtMcAddr)
34108+ ) != NULL) {
34109+
34110+ /* Send "new" packet to RLMT multicast address. */
34111+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para2);
34112+ }
34113 }
34114
34115 if (pRPort->Net->RlmtMode & SK_RLMT_CHECK_SEG) {
34116@@ -2109,7 +2118,7 @@
34117 }
34118
34119 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34120- ("SK_RLMT_LINK_UP Event END.\n"))
34121+ ("SK_RLMT_LINK_UP Event END.\n"));
34122 } /* SkRlmtEvtLinkUp */
34123
34124
34125@@ -2135,20 +2144,20 @@
34126 SK_RLMT_PORT *pRPort;
34127
34128 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34129- ("SK_RLMT_PORTUP_TIM Port %d Event BEGIN.\n", Para.Para32[0]))
34130+ ("SK_RLMT_PORTUP_TIM Port %d Event BEGIN.\n", Para.Para32[0]));
34131
34132 if (Para.Para32[1] != (SK_U32)-1) {
34133 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34134- ("Bad Parameter.\n"))
34135+ ("Bad Parameter.\n"));
34136 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34137- ("SK_RLMT_PORTUP_TIM Event EMPTY.\n"))
34138+ ("SK_RLMT_PORTUP_TIM Event EMPTY.\n"));
34139 return;
34140 }
34141
34142 pRPort = &pAC->Rlmt.Port[Para.Para32[0]];
34143 if (pRPort->LinkDown || (pRPort->PortState == SK_RLMT_PS_UP)) {
34144 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34145- ("SK_RLMT_PORTUP_TIM Port %d Event EMPTY.\n", Para.Para32[0]))
34146+ ("SK_RLMT_PORTUP_TIM Port %d Event EMPTY.\n", Para.Para32[0]));
34147 return;
34148 }
34149
34150@@ -2163,7 +2172,7 @@
34151 }
34152
34153 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34154- ("SK_RLMT_PORTUP_TIM Event END.\n"))
34155+ ("SK_RLMT_PORTUP_TIM Event END.\n"));
34156 } /* SkRlmtEvtPortUpTim */
34157
34158
34159@@ -2191,13 +2200,13 @@
34160
34161 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34162 ("SK_RLMT_PORTDOWN* Port %d Event (%d) BEGIN.\n",
34163- Para.Para32[0], Event))
34164+ Para.Para32[0], Event));
34165
34166 if (Para.Para32[1] != (SK_U32)-1) {
34167 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34168- ("Bad Parameter.\n"))
34169+ ("Bad Parameter.\n"));
34170 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34171- ("SK_RLMT_PORTDOWN* Event EMPTY.\n"))
34172+ ("SK_RLMT_PORTDOWN* Event EMPTY.\n"));
34173 return;
34174 }
34175
34176@@ -2205,7 +2214,7 @@
34177 if (!pRPort->PortStarted || (Event == SK_RLMT_PORTDOWN_TX_TIM &&
34178 !(pRPort->CheckingState & SK_RLMT_PCS_TX))) {
34179 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34180- ("SK_RLMT_PORTDOWN* Event (%d) EMPTY.\n", Event))
34181+ ("SK_RLMT_PORTDOWN* Event (%d) EMPTY.\n", Event));
34182 return;
34183 }
34184
34185@@ -2242,7 +2251,7 @@
34186 }
34187
34188 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34189- ("SK_RLMT_PORTDOWN* Event (%d) END.\n", Event))
34190+ ("SK_RLMT_PORTDOWN* Event (%d) END.\n", Event));
34191 } /* SkRlmtEvtPortDownX */
34192
34193
34194@@ -2269,7 +2278,7 @@
34195
34196 pRPort = &pAC->Rlmt.Port[Para.Para32[0]];
34197 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34198- ("SK_RLMT_LINK_DOWN Port %d Event BEGIN.\n", Para.Para32[0]))
34199+ ("SK_RLMT_LINK_DOWN Port %d Event BEGIN.\n", Para.Para32[0]));
34200
34201 if (!pAC->Rlmt.Port[Para.Para32[0]].LinkDown) {
34202 pRPort->Net->LinksUp--;
34203@@ -2288,7 +2297,7 @@
34204 }
34205
34206 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34207- ("SK_RLMT_LINK_DOWN Event END.\n"))
34208+ ("SK_RLMT_LINK_DOWN Event END.\n"));
34209 } /* SkRlmtEvtLinkDown */
34210
34211
34212@@ -2317,13 +2326,13 @@
34213 SK_MAC_ADDR *pNewMacAddr;
34214
34215 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34216- ("SK_RLMT_PORT_ADDR Port %d Event BEGIN.\n", Para.Para32[0]))
34217+ ("SK_RLMT_PORT_ADDR Port %d Event BEGIN.\n", Para.Para32[0]));
34218
34219 if (Para.Para32[1] != (SK_U32)-1) {
34220 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34221- ("Bad Parameter.\n"))
34222+ ("Bad Parameter.\n"));
34223 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34224- ("SK_RLMT_PORT_ADDR Event EMPTY.\n"))
34225+ ("SK_RLMT_PORT_ADDR Event EMPTY.\n"));
34226 return;
34227 }
34228
34229@@ -2347,7 +2356,7 @@
34230 }
34231
34232 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34233- ("SK_RLMT_PORT_ADDR Event END.\n"))
34234+ ("SK_RLMT_PORT_ADDR Event END.\n"));
34235 } /* SkRlmtEvtPortAddr */
34236
34237
34238@@ -2375,35 +2384,35 @@
34239 SK_U32 PortNumber;
34240
34241 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34242- ("SK_RLMT_START Net %d Event BEGIN.\n", Para.Para32[0]))
34243+ ("SK_RLMT_START Net %d Event BEGIN.\n", Para.Para32[0]));
34244
34245 if (Para.Para32[1] != (SK_U32)-1) {
34246 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34247- ("Bad Parameter.\n"))
34248+ ("Bad Parameter.\n"));
34249 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34250- ("SK_RLMT_START Event EMPTY.\n"))
34251+ ("SK_RLMT_START Event EMPTY.\n"));
34252 return;
34253 }
34254
34255 if (Para.Para32[0] >= pAC->Rlmt.NumNets) {
34256 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34257- ("Bad NetNumber %d.\n", Para.Para32[0]))
34258+ ("Bad NetNumber %d.\n", Para.Para32[0]));
34259 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34260- ("SK_RLMT_START Event EMPTY.\n"))
34261+ ("SK_RLMT_START Event EMPTY.\n"));
34262 return;
34263 }
34264
34265 if (pAC->Rlmt.Net[Para.Para32[0]].RlmtState != SK_RLMT_RS_INIT) {
34266 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34267- ("SK_RLMT_START Event EMPTY.\n"))
34268+ ("SK_RLMT_START Event EMPTY.\n"));
34269 return;
34270 }
34271
34272 if (pAC->Rlmt.NetsStarted >= pAC->Rlmt.NumNets) {
34273 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34274- ("All nets should have been started.\n"))
34275+ ("All nets should have been started.\n"));
34276 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34277- ("SK_RLMT_START Event EMPTY.\n"))
34278+ ("SK_RLMT_START Event EMPTY.\n"));
34279 return;
34280 }
34281
34282@@ -2437,7 +2446,7 @@
34283 pAC->Rlmt.NetsStarted++;
34284
34285 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34286- ("SK_RLMT_START Event END.\n"))
34287+ ("SK_RLMT_START Event END.\n"));
34288 } /* SkRlmtEvtStart */
34289
34290
34291@@ -2465,35 +2474,35 @@
34292 SK_U32 i;
34293
34294 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34295- ("SK_RLMT_STOP Net %d Event BEGIN.\n", Para.Para32[0]))
34296+ ("SK_RLMT_STOP Net %d Event BEGIN.\n", Para.Para32[0]));
34297
34298 if (Para.Para32[1] != (SK_U32)-1) {
34299 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34300- ("Bad Parameter.\n"))
34301+ ("Bad Parameter.\n"));
34302 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34303- ("SK_RLMT_STOP Event EMPTY.\n"))
34304+ ("SK_RLMT_STOP Event EMPTY.\n"));
34305 return;
34306 }
34307
34308 if (Para.Para32[0] >= pAC->Rlmt.NumNets) {
34309 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34310- ("Bad NetNumber %d.\n", Para.Para32[0]))
34311+ ("Bad NetNumber %d.\n", Para.Para32[0]));
34312 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34313- ("SK_RLMT_STOP Event EMPTY.\n"))
34314+ ("SK_RLMT_STOP Event EMPTY.\n"));
34315 return;
34316 }
34317
34318 if (pAC->Rlmt.Net[Para.Para32[0]].RlmtState == SK_RLMT_RS_INIT) {
34319 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34320- ("SK_RLMT_STOP Event EMPTY.\n"))
34321+ ("SK_RLMT_STOP Event EMPTY.\n"));
34322 return;
34323 }
34324
34325 if (pAC->Rlmt.NetsStarted == 0) {
34326 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34327- ("All nets are stopped.\n"))
34328+ ("All nets are stopped.\n"));
34329 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34330- ("SK_RLMT_STOP Event EMPTY.\n"))
34331+ ("SK_RLMT_STOP Event EMPTY.\n"));
34332 return;
34333 }
34334
34335@@ -2528,7 +2537,7 @@
34336 pAC->Rlmt.NetsStarted--;
34337
34338 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34339- ("SK_RLMT_STOP Event END.\n"))
34340+ ("SK_RLMT_STOP Event END.\n"));
34341 } /* SkRlmtEvtStop */
34342
34343
34344@@ -2558,13 +2567,13 @@
34345 SK_U32 i;
34346
34347 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34348- ("SK_RLMT_TIM Event BEGIN.\n"))
34349+ ("SK_RLMT_TIM Event BEGIN.\n"));
34350
34351 if (Para.Para32[1] != (SK_U32)-1) {
34352 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34353- ("Bad Parameter.\n"))
34354+ ("Bad Parameter.\n"));
34355 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34356- ("SK_RLMT_TIM Event EMPTY.\n"))
34357+ ("SK_RLMT_TIM Event EMPTY.\n"));
34358 return;
34359 }
34360
34361@@ -2636,7 +2645,7 @@
34362 }
34363
34364 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34365- ("SK_RLMT_TIM Event END.\n"))
34366+ ("SK_RLMT_TIM Event END.\n"));
34367 } /* SkRlmtEvtTim */
34368
34369
34370@@ -2664,13 +2673,13 @@
34371 #endif /* DEBUG */
34372
34373 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34374- ("SK_RLMT_SEG_TIM Event BEGIN.\n"))
34375+ ("SK_RLMT_SEG_TIM Event BEGIN.\n"));
34376
34377 if (Para.Para32[1] != (SK_U32)-1) {
34378 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34379- ("Bad Parameter.\n"))
34380+ ("Bad Parameter.\n"));
34381 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34382- ("SK_RLMT_SEG_TIM Event EMPTY.\n"))
34383+ ("SK_RLMT_SEG_TIM Event EMPTY.\n"));
34384 return;
34385 }
34386
34387@@ -2694,7 +2703,7 @@
34388 InAddr8[3], InAddr8[4], InAddr8[5],
34389 pAPort->Exact[k].a[0], pAPort->Exact[k].a[1],
34390 pAPort->Exact[k].a[2], pAPort->Exact[k].a[3],
34391- pAPort->Exact[k].a[4], pAPort->Exact[k].a[5]))
34392+ pAPort->Exact[k].a[4], pAPort->Exact[k].a[5]));
34393 }
34394 }
34395 #endif /* xDEBUG */
34396@@ -2702,7 +2711,7 @@
34397 SkRlmtCheckSeg(pAC, IoC, Para.Para32[0]);
34398
34399 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34400- ("SK_RLMT_SEG_TIM Event END.\n"))
34401+ ("SK_RLMT_SEG_TIM Event END.\n"));
34402 } /* SkRlmtEvtSegTim */
34403
34404
34405@@ -2731,18 +2740,18 @@
34406
34407
34408 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34409- ("SK_RLMT_PACKET_RECEIVED Event BEGIN.\n"))
34410+ ("SK_RLMT_PACKET_RECEIVED Event BEGIN.\n"));
34411
34412 /* Should we ignore frames during port switching? */
34413
34414 #ifdef DEBUG
34415 pMb = Para.pParaPtr;
34416 if (pMb == NULL) {
34417- SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, ("No mbuf.\n"))
34418+ SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, ("No mbuf.\n"));
34419 }
34420 else if (pMb->pNext != NULL) {
34421 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34422- ("More than one mbuf or pMb->pNext not set.\n"))
34423+ ("More than one mbuf or pMb->pNext not set.\n"));
34424 }
34425 #endif /* DEBUG */
34426
34427@@ -2760,7 +2769,7 @@
34428 }
34429
34430 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34431- ("SK_RLMT_PACKET_RECEIVED Event END.\n"))
34432+ ("SK_RLMT_PACKET_RECEIVED Event END.\n"));
34433 } /* SkRlmtEvtPacketRx */
34434
34435
34436@@ -2787,21 +2796,21 @@
34437 SK_RLMT_PORT *pRPort;
34438
34439 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34440- ("SK_RLMT_STATS_CLEAR Event BEGIN.\n"))
34441+ ("SK_RLMT_STATS_CLEAR Event BEGIN.\n"));
34442
34443 if (Para.Para32[1] != (SK_U32)-1) {
34444 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34445- ("Bad Parameter.\n"))
34446+ ("Bad Parameter.\n"));
34447 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34448- ("SK_RLMT_STATS_CLEAR Event EMPTY.\n"))
34449+ ("SK_RLMT_STATS_CLEAR Event EMPTY.\n"));
34450 return;
34451 }
34452
34453 if (Para.Para32[0] >= pAC->Rlmt.NumNets) {
34454 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34455- ("Bad NetNumber %d.\n", Para.Para32[0]))
34456+ ("Bad NetNumber %d.\n", Para.Para32[0]));
34457 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34458- ("SK_RLMT_STATS_CLEAR Event EMPTY.\n"))
34459+ ("SK_RLMT_STATS_CLEAR Event EMPTY.\n"));
34460 return;
34461 }
34462
34463@@ -2816,7 +2825,7 @@
34464 }
34465
34466 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34467- ("SK_RLMT_STATS_CLEAR Event END.\n"))
34468+ ("SK_RLMT_STATS_CLEAR Event END.\n"));
34469 } /* SkRlmtEvtStatsClear */
34470
34471
34472@@ -2840,28 +2849,28 @@
34473 SK_EVPARA Para) /* SK_U32 NetNumber; SK_U32 -1 */
34474 {
34475 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34476- ("SK_RLMT_STATS_UPDATE Event BEGIN.\n"))
34477+ ("SK_RLMT_STATS_UPDATE Event BEGIN.\n"));
34478
34479 if (Para.Para32[1] != (SK_U32)-1) {
34480 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34481- ("Bad Parameter.\n"))
34482+ ("Bad Parameter.\n"));
34483 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34484- ("SK_RLMT_STATS_UPDATE Event EMPTY.\n"))
34485+ ("SK_RLMT_STATS_UPDATE Event EMPTY.\n"));
34486 return;
34487 }
34488
34489 if (Para.Para32[0] >= pAC->Rlmt.NumNets) {
34490 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34491- ("Bad NetNumber %d.\n", Para.Para32[0]))
34492+ ("Bad NetNumber %d.\n", Para.Para32[0]));
34493 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34494- ("SK_RLMT_STATS_UPDATE Event EMPTY.\n"))
34495+ ("SK_RLMT_STATS_UPDATE Event EMPTY.\n"));
34496 return;
34497 }
34498
34499 /* Update statistics - currently always up-to-date. */
34500
34501 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34502- ("SK_RLMT_STATS_UPDATE Event END.\n"))
34503+ ("SK_RLMT_STATS_UPDATE Event END.\n"));
34504 } /* SkRlmtEvtStatsUpdate */
34505
34506
34507@@ -2885,13 +2894,13 @@
34508 SK_EVPARA Para) /* SK_U32 PortIndex; SK_U32 NetNumber */
34509 {
34510 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34511- ("SK_RLMT_PREFPORT_CHANGE to Port %d Event BEGIN.\n", Para.Para32[0]))
34512+ ("SK_RLMT_PREFPORT_CHANGE to Port %d Event BEGIN.\n", Para.Para32[0]));
34513
34514 if (Para.Para32[1] >= pAC->Rlmt.NumNets) {
34515 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34516- ("Bad NetNumber %d.\n", Para.Para32[1]))
34517+ ("Bad NetNumber %d.\n", Para.Para32[1]));
34518 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34519- ("SK_RLMT_PREFPORT_CHANGE Event EMPTY.\n"))
34520+ ("SK_RLMT_PREFPORT_CHANGE Event EMPTY.\n"));
34521 return;
34522 }
34523
34524@@ -2904,7 +2913,7 @@
34525 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_RLMT_E010, SKERR_RLMT_E010_MSG);
34526
34527 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34528- ("SK_RLMT_PREFPORT_CHANGE Event EMPTY.\n"))
34529+ ("SK_RLMT_PREFPORT_CHANGE Event EMPTY.\n"));
34530 return;
34531 }
34532
34533@@ -2918,7 +2927,7 @@
34534 }
34535
34536 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34537- ("SK_RLMT_PREFPORT_CHANGE Event END.\n"))
34538+ ("SK_RLMT_PREFPORT_CHANGE Event END.\n"));
34539 } /* SkRlmtEvtPrefportChange */
34540
34541
34542@@ -2944,37 +2953,37 @@
34543 int i;
34544
34545 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34546- ("SK_RLMT_SET_NETS Event BEGIN.\n"))
34547+ ("SK_RLMT_SET_NETS Event BEGIN.\n"));
34548
34549 if (Para.Para32[1] != (SK_U32)-1) {
34550 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34551- ("Bad Parameter.\n"))
34552+ ("Bad Parameter.\n"));
34553 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34554- ("SK_RLMT_SET_NETS Event EMPTY.\n"))
34555+ ("SK_RLMT_SET_NETS Event EMPTY.\n"));
34556 return;
34557 }
34558
34559 if (Para.Para32[0] == 0 || Para.Para32[0] > SK_MAX_NETS ||
34560 Para.Para32[0] > (SK_U32)pAC->GIni.GIMacsFound) {
34561 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34562- ("Bad number of nets: %d.\n", Para.Para32[0]))
34563+ ("Bad number of nets: %d.\n", Para.Para32[0]));
34564 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34565- ("SK_RLMT_SET_NETS Event EMPTY.\n"))
34566+ ("SK_RLMT_SET_NETS Event EMPTY.\n"));
34567 return;
34568 }
34569
34570 if (Para.Para32[0] == pAC->Rlmt.NumNets) { /* No change. */
34571 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34572- ("SK_RLMT_SET_NETS Event EMPTY.\n"))
34573+ ("SK_RLMT_SET_NETS Event EMPTY.\n"));
34574 return;
34575 }
34576
34577 /* Entering and leaving dual mode only allowed while nets are stopped. */
34578 if (pAC->Rlmt.NetsStarted > 0) {
34579 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34580- ("Changing dual mode only allowed while all nets are stopped.\n"))
34581+ ("Changing dual mode only allowed while all nets are stopped.\n"));
34582 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34583- ("SK_RLMT_SET_NETS Event EMPTY.\n"))
34584+ ("SK_RLMT_SET_NETS Event EMPTY.\n"));
34585 return;
34586 }
34587
34588@@ -3005,9 +3014,10 @@
34589 SkEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_RLMT_SET_NETS, Para);
34590
34591 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34592- ("RLMT: Changed to one net with two ports.\n"))
34593+ ("RLMT: Changed to one net with two ports.\n"));
34594 }
34595 else if (Para.Para32[0] == 2) {
34596+ pAC->Rlmt.RlmtOff = SK_TRUE;
34597 pAC->Rlmt.Port[1].Net= &pAC->Rlmt.Net[1];
34598 pAC->Rlmt.Net[1].NumPorts = pAC->GIni.GIMacsFound - 1;
34599 pAC->Rlmt.Net[0].NumPorts =
34600@@ -3034,19 +3044,19 @@
34601 SkEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_RLMT_SET_NETS, Para);
34602
34603 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34604- ("RLMT: Changed to two nets with one port each.\n"))
34605+ ("RLMT: Changed to two nets with one port each.\n"));
34606 }
34607 else {
34608 /* Not implemented for more than two nets. */
34609 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34610- ("SetNets not implemented for more than two nets.\n"))
34611+ ("SetNets not implemented for more than two nets.\n"));
34612 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34613- ("SK_RLMT_SET_NETS Event EMPTY.\n"))
34614+ ("SK_RLMT_SET_NETS Event EMPTY.\n"));
34615 return;
34616 }
34617
34618 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34619- ("SK_RLMT_SET_NETS Event END.\n"))
34620+ ("SK_RLMT_SET_NETS Event END.\n"));
34621 } /* SkRlmtSetNets */
34622
34623
34624@@ -3074,13 +3084,13 @@
34625 SK_U32 PrevRlmtMode;
34626
34627 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34628- ("SK_RLMT_MODE_CHANGE Event BEGIN.\n"))
34629+ ("SK_RLMT_MODE_CHANGE Event BEGIN.\n"));
34630
34631 if (Para.Para32[1] >= pAC->Rlmt.NumNets) {
34632 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34633- ("Bad NetNumber %d.\n", Para.Para32[1]))
34634+ ("Bad NetNumber %d.\n", Para.Para32[1]));
34635 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34636- ("SK_RLMT_MODE_CHANGE Event EMPTY.\n"))
34637+ ("SK_RLMT_MODE_CHANGE Event EMPTY.\n"));
34638 return;
34639 }
34640
34641@@ -3090,9 +3100,9 @@
34642 Para.Para32[0] != SK_RLMT_MODE_CLS) {
34643 pAC->Rlmt.Net[Para.Para32[1]].RlmtMode = SK_RLMT_MODE_CLS;
34644 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34645- ("Forced RLMT mode to CLS on single port net.\n"))
34646+ ("Forced RLMT mode to CLS on single port net.\n"));
34647 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34648- ("SK_RLMT_MODE_CHANGE Event EMPTY.\n"))
34649+ ("SK_RLMT_MODE_CHANGE Event EMPTY.\n"));
34650 return;
34651 }
34652
34653@@ -3158,7 +3168,7 @@
34654 } /* SK_RLMT_CHECK_SEG bit changed. */
34655
34656 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34657- ("SK_RLMT_MODE_CHANGE Event END.\n"))
34658+ ("SK_RLMT_MODE_CHANGE Event END.\n"));
34659 } /* SkRlmtEvtModeChange */
34660
34661
34662@@ -3244,7 +3254,7 @@
34663
34664 default: /* Create error log entry. */
34665 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
34666- ("Unknown RLMT Event %d.\n", Event))
34667+ ("Unknown RLMT Event %d.\n", Event));
34668 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_RLMT_E003, SKERR_RLMT_E003_MSG);
34669 break;
34670 } /* switch() */
34671diff -urN linux-2.6.17.orig/drivers/net/sk98lin/sktimer.c linux-2.6.17/drivers/net/sk98lin/sktimer.c
34672--- linux-2.6.17.orig/drivers/net/sk98lin/sktimer.c 2006-06-22 13:17:16.000000000 +0200
34673+++ linux-2.6.17/drivers/net/sk98lin/sktimer.c 2006-04-27 11:43:44.000000000 +0200
34674@@ -2,8 +2,8 @@
34675 *
34676 * Name: sktimer.c
34677 * Project: Gigabit Ethernet Adapters, Event Scheduler Module
34678- * Version: $Revision$
34679- * Date: $Date$
34680+ * Version: $Revision$
34681+ * Date: $Date$
34682 * Purpose: High level timer functions.
34683 *
34684 ******************************************************************************/
34685@@ -11,7 +11,7 @@
34686 /******************************************************************************
34687 *
34688 * (C)Copyright 1998-2002 SysKonnect GmbH.
34689- * (C)Copyright 2002-2003 Marvell.
34690+ * (C)Copyright 2002-2004 Marvell.
34691 *
34692 * This program is free software; you can redistribute it and/or modify
34693 * it under the terms of the GNU General Public License as published by
34694@@ -22,13 +22,12 @@
34695 *
34696 ******************************************************************************/
34697
34698-
34699 /*
34700 * Event queue and dispatcher
34701 */
34702 #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
34703 static const char SysKonnectFileId[] =
34704- "@(#) $Id$ (C) Marvell.";
34705+ "@(#) $Id$ (C) Marvell.";
34706 #endif
34707
34708 #include "h/skdrv1st.h" /* Driver Specific Definitions */
34709@@ -62,7 +61,7 @@
34710 {
34711 switch (Level) {
34712 case SK_INIT_DATA:
34713- pAC->Tim.StQueue = NULL;
34714+ pAC->Tim.StQueue = 0;
34715 break;
34716 case SK_INIT_IO:
34717 SkHwtInit(pAC, Ioc);
34718@@ -85,22 +84,20 @@
34719 SK_TIMER **ppTimPrev;
34720 SK_TIMER *pTm;
34721
34722- /*
34723- * remove timer from queue
34724- */
34725+ /* remove timer from queue */
34726 pTimer->TmActive = SK_FALSE;
34727-
34728+
34729 if (pAC->Tim.StQueue == pTimer && !pTimer->TmNext) {
34730 SkHwtStop(pAC, Ioc);
34731 }
34732-
34733+
34734 for (ppTimPrev = &pAC->Tim.StQueue; (pTm = *ppTimPrev);
34735 ppTimPrev = &pTm->TmNext ) {
34736-
34737+
34738 if (pTm == pTimer) {
34739 /*
34740 * Timer found in queue
34741- * - dequeue it and
34742+ * - dequeue it
34743 * - correct delta of the next timer
34744 */
34745 *ppTimPrev = pTm->TmNext;
34746@@ -121,7 +118,7 @@
34747 SK_AC *pAC, /* Adapters context */
34748 SK_IOC Ioc, /* IoContext */
34749 SK_TIMER *pTimer, /* Timer Pointer to be started */
34750-SK_U32 Time, /* Time value */
34751+SK_U32 Time, /* Time Value (in microsec.) */
34752 SK_U32 Class, /* Event Class for this timer */
34753 SK_U32 Event, /* Event Value for this timer */
34754 SK_EVPARA Para) /* Event Parameter for this timer */
34755@@ -130,11 +127,6 @@
34756 SK_TIMER *pTm;
34757 SK_U32 Delta;
34758
34759- Time /= 16; /* input is uS, clock ticks are 16uS */
34760-
34761- if (!Time)
34762- Time = 1;
34763-
34764 SkTimerStop(pAC, Ioc, pTimer);
34765
34766 pTimer->TmClass = Class;
34767@@ -143,31 +135,26 @@
34768 pTimer->TmActive = SK_TRUE;
34769
34770 if (!pAC->Tim.StQueue) {
34771- /* First Timer to be started */
34772+ /* first Timer to be started */
34773 pAC->Tim.StQueue = pTimer;
34774- pTimer->TmNext = NULL;
34775+ pTimer->TmNext = 0;
34776 pTimer->TmDelta = Time;
34777-
34778+
34779 SkHwtStart(pAC, Ioc, Time);
34780-
34781+
34782 return;
34783 }
34784
34785- /*
34786- * timer correction
34787- */
34788+ /* timer correction */
34789 timer_done(pAC, Ioc, 0);
34790
34791- /*
34792- * find position in queue
34793- */
34794+ /* find position in queue */
34795 Delta = 0;
34796 for (ppTimPrev = &pAC->Tim.StQueue; (pTm = *ppTimPrev);
34797 ppTimPrev = &pTm->TmNext ) {
34798-
34799+
34800 if (Delta + pTm->TmDelta > Time) {
34801- /* Position found */
34802- /* Here the timer needs to be inserted. */
34803+ /* the timer needs to be inserted here */
34804 break;
34805 }
34806 Delta += pTm->TmDelta;
34807@@ -179,9 +166,7 @@
34808 pTimer->TmDelta = Time - Delta;
34809
34810 if (pTm) {
34811- /* There is a next timer
34812- * -> correct its Delta value.
34813- */
34814+ /* there is a next timer: correct its Delta value */
34815 pTm->TmDelta -= pTimer->TmDelta;
34816 }
34817
34818@@ -210,7 +195,7 @@
34819 int Done = 0;
34820
34821 Delta = SkHwtRead(pAC, Ioc);
34822-
34823+
34824 ppLast = &pAC->Tim.StQueue;
34825 pTm = pAC->Tim.StQueue;
34826 while (pTm && !Done) {
34827@@ -228,13 +213,13 @@
34828 Done = 1;
34829 }
34830 }
34831- *ppLast = NULL;
34832+ *ppLast = 0;
34833 /*
34834 * pTm points to the first Timer that did not run out.
34835 * StQueue points to the first Timer that run out.
34836 */
34837
34838- for ( pTComp = pAC->Tim.StQueue; pTComp; pTComp = pTComp->TmNext) {
34839+ for (pTComp = pAC->Tim.StQueue; pTComp; pTComp = pTComp->TmNext) {
34840 SkEventQueue(pAC,pTComp->TmClass, pTComp->TmEvent, pTComp->TmPara);
34841 }
34842
34843diff -urN linux-2.6.17.orig/drivers/net/sk98lin/sktwsi.c linux-2.6.17/drivers/net/sk98lin/sktwsi.c
34844--- linux-2.6.17.orig/drivers/net/sk98lin/sktwsi.c 1970-01-01 01:00:00.000000000 +0100
34845+++ linux-2.6.17/drivers/net/sk98lin/sktwsi.c 2006-04-27 11:43:44.000000000 +0200
34846@@ -0,0 +1,1361 @@
34847+/******************************************************************************
34848+ *
34849+ * Name: sktwsi.c
34850+ * Project: Gigabit Ethernet Adapters, TWSI-Module
34851+ * Version: $Revision$
34852+ * Date: $Date$
34853+ * Purpose: Functions to access Voltage and Temperature Sensor
34854+ *
34855+ ******************************************************************************/
34856+
34857+/******************************************************************************
34858+ *
34859+ * LICENSE:
34860+ * (C)Copyright 1998-2002 SysKonnect.
34861+ * (C)Copyright 2002-2005 Marvell.
34862+ *
34863+ * This program is free software; you can redistribute it and/or modify
34864+ * it under the terms of the GNU General Public License as published by
34865+ * the Free Software Foundation; either version 2 of the License, or
34866+ * (at your option) any later version.
34867+ * The information in this file is provided "AS IS" without warranty.
34868+ * /LICENSE
34869+ *
34870+ ******************************************************************************/
34871+
34872+/*
34873+ * TWSI Protocol
34874+ */
34875+#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
34876+static const char SysKonnectFileId[] =
34877+ "@(#) $Id$ (C) Marvell.";
34878+#endif
34879+
34880+#include "h/skdrv1st.h" /* Driver Specific Definitions */
34881+#include "h/lm80.h"
34882+#include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */
34883+
34884+#ifdef __C2MAN__
34885+/*
34886+ TWSI protocol implementation.
34887+
34888+ General Description:
34889+
34890+ The TWSI protocol is used for the temperature sensors and for
34891+ the serial EEPROM which hold the configuration.
34892+
34893+ This file covers functions that allow to read write and do
34894+ some bulk requests a specified TWSI address.
34895+
34896+ The Genesis has 2 TWSI buses. One for the EEPROM which holds
34897+ the VPD Data and one for temperature and voltage sensor.
34898+ The following picture shows the TWSI buses, TWSI devices and
34899+ their control registers.
34900+
34901+ Note: The VPD functions are in skvpd.c
34902+.
34903+. PCI Config TWSI Bus for VPD Data:
34904+.
34905+. +------------+
34906+. | VPD EEPROM |
34907+. +------------+
34908+. |
34909+. | <-- TWSI
34910+. |
34911+. +-----------+-----------+
34912+. | |
34913+. +-----------------+ +-----------------+
34914+. | PCI_VPD_ADR_REG | | PCI_VPD_DAT_REG |
34915+. +-----------------+ +-----------------+
34916+.
34917+.
34918+. TWSI Bus for LM80 sensor:
34919+.
34920+. +-----------------+
34921+. | Temperature and |
34922+. | Voltage Sensor |
34923+. | LM80 |
34924+. +-----------------+
34925+. |
34926+. |
34927+. TWSI --> |
34928+. |
34929+. +----+
34930+. +-------------->| OR |<--+
34931+. | +----+ |
34932+. +------+------+ |
34933+. | | |
34934+. +--------+ +--------+ +----------+
34935+. | B2_I2C | | B2_I2C | | B2_I2C |
34936+. | _CTRL | | _DATA | | _SW |
34937+. +--------+ +--------+ +----------+
34938+.
34939+ The TWSI bus may be driven by the B2_I2C_SW or by the B2_I2C_CTRL
34940+ and B2_I2C_DATA registers.
34941+ For driver software it is recommended to use the TWSI control and
34942+ data register, because TWSI bus timing is done by the ASIC and
34943+ an interrupt may be received when the TWSI request is completed.
34944+
34945+ Clock Rate Timing: MIN MAX generated by
34946+ VPD EEPROM: 50 kHz 100 kHz HW
34947+ LM80 over TWSI Ctrl/Data reg. 50 kHz 100 kHz HW
34948+ LM80 over B2_I2C_SW register 0 400 kHz SW
34949+
34950+ Note: The clock generated by the hardware is dependend on the
34951+ PCI clock. If the PCI bus clock is 33 MHz, the I2C/VPD
34952+ clock is 50 kHz.
34953+ */
34954+intro()
34955+{}
34956+#endif
34957+
34958+#ifdef SK_DIAG
34959+/*
34960+ * TWSI Fast Mode timing values used by the LM80.
34961+ * If new devices are added to the TWSI bus the timing values have to be checked.
34962+ */
34963+#ifndef I2C_SLOW_TIMING
34964+#define T_CLK_LOW 1300L /* clock low time in ns */
34965+#define T_CLK_HIGH 600L /* clock high time in ns */
34966+#define T_DATA_IN_SETUP 100L /* data in Set-up Time */
34967+#define T_START_HOLD 600L /* start condition hold time */
34968+#define T_START_SETUP 600L /* start condition Set-up time */
34969+#define T_STOP_SETUP 600L /* stop condition Set-up time */
34970+#define T_BUS_IDLE 1300L /* time the bus must free after Tx */
34971+#define T_CLK_2_DATA_OUT 900L /* max. clock low to data output valid */
34972+#else /* I2C_SLOW_TIMING */
34973+/* TWSI Standard Mode Timing */
34974+#define T_CLK_LOW 4700L /* clock low time in ns */
34975+#define T_CLK_HIGH 4000L /* clock high time in ns */
34976+#define T_DATA_IN_SETUP 250L /* data in Set-up Time */
34977+#define T_START_HOLD 4000L /* start condition hold time */
34978+#define T_START_SETUP 4700L /* start condition Set-up time */
34979+#define T_STOP_SETUP 4000L /* stop condition Set-up time */
34980+#define T_BUS_IDLE 4700L /* time the bus must free after Tx */
34981+#endif /* !I2C_SLOW_TIMING */
34982+
34983+#define NS2BCLK(x) (((x)*125)/10000)
34984+
34985+/*
34986+ * TWSI Wire Operations
34987+ *
34988+ * About I2C_CLK_LOW():
34989+ *
34990+ * The Data Direction bit (I2C_DATA_DIR) has to be set to input when setting
34991+ * clock to low, to prevent the ASIC and the TWSI data client from driving the
34992+ * serial data line simultaneously (ASIC: last bit of a byte = '1', TWSI client
34993+ * send an 'ACK'). See also Concentrator Bugreport No. 10192.
34994+ */
34995+#define I2C_DATA_HIGH(IoC) SK_I2C_SET_BIT(IoC, I2C_DATA)
34996+#define I2C_DATA_LOW(IoC) SK_I2C_CLR_BIT(IoC, I2C_DATA)
34997+#define I2C_DATA_OUT(IoC) SK_I2C_SET_BIT(IoC, I2C_DATA_DIR)
34998+#define I2C_DATA_IN(IoC) SK_I2C_CLR_BIT(IoC, I2C_DATA_DIR | I2C_DATA)
34999+#define I2C_CLK_HIGH(IoC) SK_I2C_SET_BIT(IoC, I2C_CLK)
35000+#define I2C_CLK_LOW(IoC) SK_I2C_CLR_BIT(IoC, I2C_CLK | I2C_DATA_DIR)
35001+#define I2C_START_COND(IoC) SK_I2C_CLR_BIT(IoC, I2C_CLK)
35002+
35003+#define NS2CLKT(x) ((x*125L)/10000)
35004+
35005+/*--------------- TWSI Interface Register Functions --------------- */
35006+
35007+/*
35008+ * sending one bit
35009+ */
35010+void SkI2cSndBit(
35011+SK_IOC IoC, /* I/O Context */
35012+SK_U8 Bit) /* Bit to send */
35013+{
35014+ I2C_DATA_OUT(IoC);
35015+ if (Bit) {
35016+ I2C_DATA_HIGH(IoC);
35017+ }
35018+ else {
35019+ I2C_DATA_LOW(IoC);
35020+ }
35021+ SkDgWaitTime(IoC, NS2BCLK(T_DATA_IN_SETUP));
35022+ I2C_CLK_HIGH(IoC);
35023+ SkDgWaitTime(IoC, NS2BCLK(T_CLK_HIGH));
35024+ I2C_CLK_LOW(IoC);
35025+} /* SkI2cSndBit*/
35026+
35027+
35028+/*
35029+ * Signal a start to the TWSI Bus.
35030+ *
35031+ * A start is signaled when data goes to low in a high clock cycle.
35032+ *
35033+ * Ends with Clock Low.
35034+ *
35035+ * Status: not tested
35036+ */
35037+void SkI2cStart(
35038+SK_IOC IoC) /* I/O Context */
35039+{
35040+ /* Init data and Clock to output lines */
35041+ /* Set Data high */
35042+ I2C_DATA_OUT(IoC);
35043+ I2C_DATA_HIGH(IoC);
35044+ /* Set Clock high */
35045+ I2C_CLK_HIGH(IoC);
35046+
35047+ SkDgWaitTime(IoC, NS2BCLK(T_START_SETUP));
35048+
35049+ /* Set Data Low */
35050+ I2C_DATA_LOW(IoC);
35051+
35052+ SkDgWaitTime(IoC, NS2BCLK(T_START_HOLD));
35053+
35054+ /* Clock low without Data to Input */
35055+ I2C_START_COND(IoC);
35056+
35057+ SkDgWaitTime(IoC, NS2BCLK(T_CLK_LOW));
35058+} /* SkI2cStart */
35059+
35060+
35061+void SkI2cStop(
35062+SK_IOC IoC) /* I/O Context */
35063+{
35064+ /* Init data and Clock to output lines */
35065+ /* Set Data low */
35066+ I2C_DATA_OUT(IoC);
35067+ I2C_DATA_LOW(IoC);
35068+
35069+ SkDgWaitTime(IoC, NS2BCLK(T_CLK_2_DATA_OUT));
35070+
35071+ /* Set Clock high */
35072+ I2C_CLK_HIGH(IoC);
35073+
35074+ SkDgWaitTime(IoC, NS2BCLK(T_STOP_SETUP));
35075+
35076+ /*
35077+ * Set Data High: Do it by setting the Data Line to Input.
35078+ * Because of a pull up resistor the Data Line
35079+ * floods to high.
35080+ */
35081+ I2C_DATA_IN(IoC);
35082+
35083+ /*
35084+ * When TWSI activity is stopped
35085+ * o DATA should be set to input and
35086+ * o CLOCK should be set to high!
35087+ */
35088+ SkDgWaitTime(IoC, NS2BCLK(T_BUS_IDLE));
35089+} /* SkI2cStop */
35090+
35091+
35092+/*
35093+ * Receive just one bit via the TWSI bus.
35094+ *
35095+ * Note: Clock must be set to LOW before calling this function.
35096+ *
35097+ * Returns The received bit.
35098+ */
35099+int SkI2cRcvBit(
35100+SK_IOC IoC) /* I/O Context */
35101+{
35102+ int Bit;
35103+ SK_U8 I2cSwCtrl;
35104+
35105+ /* Init data as input line */
35106+ I2C_DATA_IN(IoC);
35107+
35108+ SkDgWaitTime(IoC, NS2BCLK(T_CLK_2_DATA_OUT));
35109+
35110+ I2C_CLK_HIGH(IoC);
35111+
35112+ SkDgWaitTime(IoC, NS2BCLK(T_CLK_HIGH));
35113+
35114+ SK_I2C_GET_SW(IoC, &I2cSwCtrl);
35115+
35116+ Bit = (I2cSwCtrl & I2C_DATA) ? 1 : 0;
35117+
35118+ I2C_CLK_LOW(IoC);
35119+ SkDgWaitTime(IoC, NS2BCLK(T_CLK_LOW-T_CLK_2_DATA_OUT));
35120+
35121+ return(Bit);
35122+} /* SkI2cRcvBit */
35123+
35124+
35125+/*
35126+ * Receive an ACK.
35127+ *
35128+ * returns 0 If acknowledged
35129+ * 1 in case of an error
35130+ */
35131+int SkI2cRcvAck(
35132+SK_IOC IoC) /* I/O Context */
35133+{
35134+ /*
35135+ * Received bit must be zero.
35136+ */
35137+ return(SkI2cRcvBit(IoC) != 0);
35138+} /* SkI2cRcvAck */
35139+
35140+
35141+/*
35142+ * Send an NACK.
35143+ */
35144+void SkI2cSndNAck(
35145+SK_IOC IoC) /* I/O Context */
35146+{
35147+ /*
35148+ * Received bit must be zero.
35149+ */
35150+ SkI2cSndBit(IoC, 1);
35151+} /* SkI2cSndNAck */
35152+
35153+
35154+/*
35155+ * Send an ACK.
35156+ */
35157+void SkI2cSndAck(
35158+SK_IOC IoC) /* I/O Context */
35159+{
35160+ /*
35161+ * Received bit must be zero.
35162+ */
35163+ SkI2cSndBit(IoC, 0);
35164+} /* SkI2cSndAck */
35165+
35166+
35167+/*
35168+ * Send one byte to the TWSI device and wait for ACK.
35169+ *
35170+ * Return acknowleged status.
35171+ */
35172+int SkI2cSndByte(
35173+SK_IOC IoC, /* I/O Context */
35174+int Byte) /* byte to send */
35175+{
35176+ int i;
35177+
35178+ for (i = 0; i < 8; i++) {
35179+ if (Byte & (1<<(7-i))) {
35180+ SkI2cSndBit(IoC, 1);
35181+ }
35182+ else {
35183+ SkI2cSndBit(IoC, 0);
35184+ }
35185+ }
35186+
35187+ return(SkI2cRcvAck(IoC));
35188+} /* SkI2cSndByte */
35189+
35190+
35191+/*
35192+ * Receive one byte and ack it.
35193+ *
35194+ * Return byte.
35195+ */
35196+int SkI2cRcvByte(
35197+SK_IOC IoC, /* I/O Context */
35198+int Last) /* Last Byte Flag */
35199+{
35200+ int i;
35201+ int Byte = 0;
35202+
35203+ for (i = 0; i < 8; i++) {
35204+ Byte <<= 1;
35205+ Byte |= SkI2cRcvBit(IoC);
35206+ }
35207+
35208+ if (Last) {
35209+ SkI2cSndNAck(IoC);
35210+ }
35211+ else {
35212+ SkI2cSndAck(IoC);
35213+ }
35214+
35215+ return(Byte);
35216+} /* SkI2cRcvByte */
35217+
35218+
35219+/*
35220+ * Start dialog and send device address
35221+ *
35222+ * Return 0 if acknowleged, 1 in case of an error
35223+ */
35224+int SkI2cSndDev(
35225+SK_IOC IoC, /* I/O Context */
35226+int Addr, /* Device Address */
35227+int Rw) /* Read / Write Flag */
35228+{
35229+ SkI2cStart(IoC);
35230+ Rw = ~Rw;
35231+ Rw &= I2C_WRITE;
35232+ return(SkI2cSndByte(IoC, (Addr << 1) | Rw));
35233+} /* SkI2cSndDev */
35234+
35235+#endif /* SK_DIAG */
35236+
35237+/*----------------- TWSI CTRL Register Functions ----------*/
35238+
35239+/*
35240+ * waits for a completion of a TWSI transfer
35241+ *
35242+ * returns 0: success, transfer completes
35243+ * 1: error, transfer does not complete, TWSI transfer
35244+ * killed, wait loop terminated.
35245+ */
35246+int SkI2cWait(
35247+SK_AC *pAC, /* Adapter Context */
35248+SK_IOC IoC, /* I/O Context */
35249+int Event) /* complete event to wait for (I2C_READ or I2C_WRITE) */
35250+{
35251+ SK_U64 StartTime;
35252+ SK_U64 CurrentTime;
35253+ SK_U32 I2cCtrl;
35254+
35255+ StartTime = SkOsGetTime(pAC);
35256+
35257+ do {
35258+ CurrentTime = SkOsGetTime(pAC);
35259+
35260+ if (CurrentTime - StartTime > SK_TICKS_PER_SEC / 8) {
35261+
35262+ SK_I2C_STOP(IoC);
35263+#ifndef SK_DIAG
35264+ if (pAC->I2c.InitLevel > SK_INIT_DATA) {
35265+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E002, SKERR_I2C_E002MSG);
35266+ }
35267+#endif /* !SK_DIAG */
35268+ return(1);
35269+ }
35270+
35271+ SK_I2C_GET_CTL(IoC, &I2cCtrl);
35272+
35273+#ifdef xYUKON_DBG
35274+ printf("StartTime=%lu, CurrentTime=%lu\n",
35275+ StartTime, CurrentTime);
35276+ if (kbhit()) {
35277+ return(1);
35278+ }
35279+#endif /* YUKON_DBG */
35280+
35281+ } while ((I2cCtrl & I2C_FLAG) == (SK_U32)Event << 31);
35282+
35283+ return(0);
35284+} /* SkI2cWait */
35285+
35286+
35287+/*
35288+ * waits for a completion of a TWSI transfer
35289+ *
35290+ * Returns
35291+ * Nothing
35292+ */
35293+void SkI2cWaitIrq(
35294+SK_AC *pAC, /* Adapter Context */
35295+SK_IOC IoC) /* I/O Context */
35296+{
35297+ SK_SENSOR *pSen;
35298+ SK_U64 StartTime;
35299+ SK_U32 IrqSrc;
35300+ SK_U32 IsTwsiReadyBit;
35301+
35302+ pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
35303+
35304+ if (pSen->SenState == SK_SEN_IDLE) {
35305+ return;
35306+ }
35307+
35308+ IsTwsiReadyBit = CHIP_ID_YUKON_2(pAC) ? Y2_IS_TWSI_RDY : IS_I2C_READY;
35309+
35310+ StartTime = SkOsGetTime(pAC);
35311+
35312+ do {
35313+ if (SkOsGetTime(pAC) - StartTime > SK_TICKS_PER_SEC / 8) {
35314+
35315+ SK_I2C_STOP(IoC);
35316+#ifndef SK_DIAG
35317+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E016, SKERR_I2C_E016MSG);
35318+#endif /* !SK_DIAG */
35319+ return;
35320+ }
35321+
35322+ SK_IN32(IoC, B0_ISRC, &IrqSrc);
35323+
35324+ } while ((IrqSrc & IsTwsiReadyBit) == 0);
35325+
35326+ pSen->SenState = SK_SEN_IDLE;
35327+ return;
35328+} /* SkI2cWaitIrq */
35329+
35330+/*
35331+ * writes a single byte or 4 bytes into the TWSI device
35332+ *
35333+ * returns 0: success
35334+ * 1: error
35335+ */
35336+int SkI2cWrite(
35337+SK_AC *pAC, /* Adapter Context */
35338+SK_IOC IoC, /* I/O Context */
35339+SK_U32 I2cData, /* TWSI Data to write */
35340+int I2cDev, /* TWSI Device Address */
35341+int I2cDevSize, /* TWSI Device Size (e.g. I2C_025K_DEV or I2C_2K_DEV) */
35342+int I2cReg, /* TWSI Device Register Address */
35343+int I2cBurst) /* TWSI Burst Flag */
35344+{
35345+ SK_OUT32(IoC, B2_I2C_DATA, I2cData);
35346+
35347+ SK_I2C_CTL(IoC, I2C_WRITE, I2cDev, I2cDevSize, I2cReg, I2cBurst);
35348+
35349+ return(SkI2cWait(pAC, IoC, I2C_WRITE));
35350+} /* SkI2cWrite*/
35351+
35352+
35353+#ifdef SK_DIAG
35354+/*
35355+ * reads a single byte or 4 bytes from the TWSI device
35356+ *
35357+ * returns the word read
35358+ */
35359+SK_U32 SkI2cRead(
35360+SK_AC *pAC, /* Adapter Context */
35361+SK_IOC IoC, /* I/O Context */
35362+int I2cDev, /* TWSI Device Address */
35363+int I2cDevSize, /* TWSI Device Size (e.g. I2C_025K_DEV or I2C_2K_DEV) */
35364+int I2cReg, /* TWSI Device Register Address */
35365+int I2cBurst) /* TWSI Burst Flag */
35366+{
35367+ SK_U32 Data;
35368+
35369+ SK_OUT32(IoC, B2_I2C_DATA, 0);
35370+
35371+ SK_I2C_CTL(IoC, I2C_READ, I2cDev, I2cDevSize, I2cReg, I2cBurst);
35372+
35373+ if (SkI2cWait(pAC, IoC, I2C_READ) != 0) {
35374+ w_print("%s\n", SKERR_I2C_E002MSG);
35375+ }
35376+
35377+ SK_IN32(IoC, B2_I2C_DATA, &Data);
35378+
35379+ return(Data);
35380+} /* SkI2cRead */
35381+#endif /* SK_DIAG */
35382+
35383+
35384+/*
35385+ * read a sensor's value
35386+ *
35387+ * This function reads a sensor's value from the TWSI sensor chip. The sensor
35388+ * is defined by its index into the sensors database in the struct pAC points
35389+ * to.
35390+ * Returns
35391+ * 1 if the read is completed
35392+ * 0 if the read must be continued (TWSI Bus still allocated)
35393+ */
35394+int SkI2cReadSensor(
35395+SK_AC *pAC, /* Adapter Context */
35396+SK_IOC IoC, /* I/O Context */
35397+SK_SENSOR *pSen) /* Sensor to be read */
35398+{
35399+ if (pSen->SenRead != NULL) {
35400+ return((*pSen->SenRead)(pAC, IoC, pSen));
35401+ }
35402+
35403+ return(0); /* no success */
35404+} /* SkI2cReadSensor */
35405+
35406+/*
35407+ * Do the Init state 0 initialization
35408+ */
35409+static int SkI2cInit0(
35410+SK_AC *pAC) /* Adapter Context */
35411+{
35412+ int i;
35413+ SK_SENSOR *pSen;
35414+
35415+ /* Begin with first sensor */
35416+ pAC->I2c.CurrSens = 0;
35417+
35418+ /* Begin with timeout control for state machine */
35419+ pAC->I2c.TimerMode = SK_TIMER_WATCH_SM;
35420+
35421+ /* Set sensor number to zero */
35422+ pAC->I2c.MaxSens = 0;
35423+
35424+#ifndef SK_DIAG
35425+ /* Initialize Number of Dummy Reads */
35426+ pAC->I2c.DummyReads = SK_MAX_SENSORS;
35427+#endif /* !SK_DIAG */
35428+
35429+ for (i = 0; i < SK_MAX_SENSORS; i++) {
35430+ pSen = &pAC->I2c.SenTable[i];
35431+
35432+ pSen->SenDesc = "unknown";
35433+ pSen->SenType = SK_SEN_UNKNOWN;
35434+ pSen->SenThreErrHigh = 0;
35435+ pSen->SenThreErrLow = 0;
35436+ pSen->SenThreWarnHigh = 0;
35437+ pSen->SenThreWarnLow = 0;
35438+ pSen->SenReg = LM80_FAN2_IN;
35439+ pSen->SenInit = SK_SEN_DYN_INIT_NONE;
35440+ pSen->SenValue = 0;
35441+ pSen->SenErrFlag = SK_SEN_ERR_NOT_PRESENT;
35442+ pSen->SenErrCts = 0;
35443+ pSen->SenBegErrTS = 0;
35444+ pSen->SenState = SK_SEN_IDLE;
35445+ pSen->SenRead = NULL;
35446+ pSen->SenDev = 0;
35447+ }
35448+
35449+ /* Now we are "INIT data"ed */
35450+ pAC->I2c.InitLevel = SK_INIT_DATA;
35451+ return(0);
35452+} /* SkI2cInit0*/
35453+
35454+
35455+/*
35456+ * Do the init state 1 initialization
35457+ *
35458+ * initialize the following register of the LM80:
35459+ * Configuration register:
35460+ * - START, noINT, activeLOW, noINT#Clear, noRESET, noCI, noGPO#, noINIT
35461+ *
35462+ * Interrupt Mask Register 1:
35463+ * - all interrupts are Disabled (0xff)
35464+ *
35465+ * Interrupt Mask Register 2:
35466+ * - all interrupts are Disabled (0xff) Interrupt modi doesn't matter.
35467+ *
35468+ * Fan Divisor/RST_OUT register:
35469+ * - Divisors set to 1 (bits 00), all others 0s.
35470+ *
35471+ * OS# Configuration/Temperature resolution Register:
35472+ * - all 0s
35473+ *
35474+ */
35475+static int SkI2cInit1(
35476+SK_AC *pAC, /* Adapter Context */
35477+SK_IOC IoC) /* I/O Context */
35478+{
35479+ int i;
35480+ SK_U8 I2cSwCtrl;
35481+ SK_GEPORT *pPrt; /* GIni Port struct pointer */
35482+ SK_SENSOR *pSen;
35483+
35484+ if (pAC->I2c.InitLevel != SK_INIT_DATA) {
35485+ /* Re-init not needed in TWSI module */
35486+ return(0);
35487+ }
35488+
35489+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC ||
35490+ pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) {
35491+ /* No sensors on Yukon-EC and Yukon-FE */
35492+ return(0);
35493+ }
35494+
35495+ /* Set the Direction of TWSI-Data Pin to IN */
35496+ SK_I2C_CLR_BIT(IoC, I2C_DATA_DIR | I2C_DATA);
35497+
35498+ /* Check for 32-Bit Yukon with Low at TWSI-Data Pin */
35499+ SK_I2C_GET_SW(IoC, &I2cSwCtrl);
35500+
35501+ if ((I2cSwCtrl & I2C_DATA) == 0) {
35502+ /* this is a 32-Bit board */
35503+ pAC->GIni.GIYukon32Bit = SK_TRUE;
35504+ return(0);
35505+ }
35506+
35507+ /* Check for 64 Bit Yukon without sensors */
35508+ if (SkI2cWrite(pAC, IoC, 0, LM80_ADDR, I2C_025K_DEV, LM80_CFG, 0) != 0) {
35509+ return(0);
35510+ }
35511+
35512+ (void)SkI2cWrite(pAC, IoC, 0xffUL, LM80_ADDR, I2C_025K_DEV, LM80_IMSK_1, 0);
35513+
35514+ (void)SkI2cWrite(pAC, IoC, 0xffUL, LM80_ADDR, I2C_025K_DEV, LM80_IMSK_2, 0);
35515+
35516+ (void)SkI2cWrite(pAC, IoC, 0, LM80_ADDR, I2C_025K_DEV, LM80_FAN_CTRL, 0);
35517+
35518+ (void)SkI2cWrite(pAC, IoC, 0, LM80_ADDR, I2C_025K_DEV, LM80_TEMP_CTRL, 0);
35519+
35520+ (void)SkI2cWrite(pAC, IoC, (SK_U32)LM80_CFG_START, LM80_ADDR, I2C_025K_DEV,
35521+ LM80_CFG, 0);
35522+
35523+ /*
35524+ * MaxSens has to be updated here, because PhyType is not
35525+ * set when performing Init Level 0
35526+ */
35527+ pAC->I2c.MaxSens = 5;
35528+
35529+ pPrt = &pAC->GIni.GP[0];
35530+
35531+ if (pAC->GIni.GIGenesis) {
35532+ if (pPrt->PhyType == SK_PHY_BCOM) {
35533+ if (pAC->GIni.GIMacsFound == 1) {
35534+ pAC->I2c.MaxSens += 1;
35535+ }
35536+ else {
35537+ pAC->I2c.MaxSens += 3;
35538+ }
35539+ }
35540+ }
35541+ else {
35542+ pAC->I2c.MaxSens += 3;
35543+ }
35544+
35545+ for (i = 0; i < pAC->I2c.MaxSens; i++) {
35546+ pSen = &pAC->I2c.SenTable[i];
35547+ switch (i) {
35548+ case 0:
35549+ pSen->SenDesc = "Temperature";
35550+ pSen->SenType = SK_SEN_TEMP;
35551+ pSen->SenThreErrHigh = SK_SEN_TEMP_HIGH_ERR;
35552+ pSen->SenThreWarnHigh = SK_SEN_TEMP_HIGH_WARN;
35553+ pSen->SenThreWarnLow = SK_SEN_TEMP_LOW_WARN;
35554+ pSen->SenThreErrLow = SK_SEN_TEMP_LOW_ERR;
35555+ pSen->SenReg = LM80_TEMP_IN;
35556+ break;
35557+ case 1:
35558+ pSen->SenDesc = "Voltage PCI";
35559+ pSen->SenType = SK_SEN_VOLT;
35560+ pSen->SenThreErrHigh = SK_SEN_PCI_5V_HIGH_ERR;
35561+ pSen->SenThreWarnHigh = SK_SEN_PCI_5V_HIGH_WARN;
35562+ if (pAC->GIni.GIPciBus != SK_PEX_BUS) {
35563+ pSen->SenThreWarnLow = SK_SEN_PCI_5V_LOW_WARN;
35564+ pSen->SenThreErrLow = SK_SEN_PCI_5V_LOW_ERR;
35565+ }
35566+ else {
35567+ pSen->SenThreWarnLow = 0;
35568+ pSen->SenThreErrLow = 0;
35569+ }
35570+ pSen->SenReg = LM80_VT0_IN;
35571+ break;
35572+ case 2:
35573+ pSen->SenDesc = "Voltage PCI-IO";
35574+ pSen->SenType = SK_SEN_VOLT;
35575+ pSen->SenThreErrHigh = SK_SEN_PCI_IO_5V_HIGH_ERR;
35576+ pSen->SenThreWarnHigh = SK_SEN_PCI_IO_5V_HIGH_WARN;
35577+ if (pAC->GIni.GIPciBus != SK_PEX_BUS) {
35578+ pSen->SenThreWarnLow = SK_SEN_PCI_IO_3V3_LOW_WARN;
35579+ pSen->SenThreErrLow = SK_SEN_PCI_IO_3V3_LOW_ERR;
35580+ }
35581+ else {
35582+ pSen->SenThreWarnLow = 0;
35583+ pSen->SenThreErrLow = 0;
35584+ }
35585+ pSen->SenReg = LM80_VT1_IN;
35586+ pSen->SenInit = SK_SEN_DYN_INIT_PCI_IO;
35587+ break;
35588+ case 3:
35589+ if (pAC->GIni.GIGenesis) {
35590+ pSen->SenDesc = "Voltage ASIC";
35591+ }
35592+ else {
35593+ pSen->SenDesc = "Voltage VMAIN";
35594+ }
35595+ pSen->SenType = SK_SEN_VOLT;
35596+ pSen->SenThreErrHigh = SK_SEN_VDD_HIGH_ERR;
35597+ pSen->SenThreWarnHigh = SK_SEN_VDD_HIGH_WARN;
35598+ pSen->SenThreWarnLow = SK_SEN_VDD_LOW_WARN;
35599+ pSen->SenThreErrLow = SK_SEN_VDD_LOW_ERR;
35600+ pSen->SenReg = LM80_VT2_IN;
35601+ break;
35602+ case 4:
35603+ if (pAC->GIni.GIGenesis) {
35604+ if (pPrt->PhyType == SK_PHY_BCOM) {
35605+ pSen->SenDesc = "Voltage PHY A PLL";
35606+ pSen->SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR;
35607+ pSen->SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN;
35608+ pSen->SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN;
35609+ pSen->SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR;
35610+ }
35611+ else {
35612+ pSen->SenDesc = "Voltage PMA";
35613+ pSen->SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR;
35614+ pSen->SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN;
35615+ pSen->SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN;
35616+ pSen->SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR;
35617+ }
35618+ }
35619+ else {
35620+ pSen->SenDesc = "Voltage VAUX";
35621+ pSen->SenThreErrHigh = SK_SEN_VAUX_3V3_HIGH_ERR;
35622+ pSen->SenThreWarnHigh = SK_SEN_VAUX_3V3_HIGH_WARN;
35623+ if (pAC->GIni.GIVauxAvail) {
35624+ pSen->SenThreWarnLow = SK_SEN_VAUX_3V3_LOW_WARN;
35625+ pSen->SenThreErrLow = SK_SEN_VAUX_3V3_LOW_ERR;
35626+ }
35627+ else {
35628+ pSen->SenThreErrLow = 0;
35629+ pSen->SenThreWarnLow = 0;
35630+ }
35631+ }
35632+ pSen->SenType = SK_SEN_VOLT;
35633+ pSen->SenReg = LM80_VT3_IN;
35634+ break;
35635+ case 5:
35636+ if (CHIP_ID_YUKON_2(pAC)) {
35637+ if (pAC->GIni.GIChipRev == CHIP_REV_YU_XL_A0) {
35638+ pSen->SenDesc = "Voltage Core 1V3";
35639+ pSen->SenThreErrHigh = SK_SEN_CORE_1V3_HIGH_ERR;
35640+ pSen->SenThreWarnHigh = SK_SEN_CORE_1V3_HIGH_WARN;
35641+ pSen->SenThreWarnLow = SK_SEN_CORE_1V3_LOW_WARN;
35642+ pSen->SenThreErrLow = SK_SEN_CORE_1V3_LOW_ERR;
35643+ }
35644+ else {
35645+ pSen->SenDesc = "Voltage Core 1V2";
35646+ pSen->SenThreErrHigh = SK_SEN_CORE_1V2_HIGH_ERR;
35647+ pSen->SenThreWarnHigh = SK_SEN_CORE_1V2_HIGH_WARN;
35648+ pSen->SenThreWarnLow = SK_SEN_CORE_1V2_LOW_WARN;
35649+ pSen->SenThreErrLow = SK_SEN_CORE_1V2_LOW_ERR;
35650+ }
35651+ }
35652+ else {
35653+ if (pAC->GIni.GIGenesis) {
35654+ pSen->SenDesc = "Voltage PHY 2V5";
35655+ pSen->SenThreErrHigh = SK_SEN_PHY_2V5_HIGH_ERR;
35656+ pSen->SenThreWarnHigh = SK_SEN_PHY_2V5_HIGH_WARN;
35657+ pSen->SenThreWarnLow = SK_SEN_PHY_2V5_LOW_WARN;
35658+ pSen->SenThreErrLow = SK_SEN_PHY_2V5_LOW_ERR;
35659+ }
35660+ else {
35661+ pSen->SenDesc = "Voltage Core 1V5";
35662+ pSen->SenThreErrHigh = SK_SEN_CORE_1V5_HIGH_ERR;
35663+ pSen->SenThreWarnHigh = SK_SEN_CORE_1V5_HIGH_WARN;
35664+ pSen->SenThreWarnLow = SK_SEN_CORE_1V5_LOW_WARN;
35665+ pSen->SenThreErrLow = SK_SEN_CORE_1V5_LOW_ERR;
35666+ }
35667+ }
35668+ pSen->SenType = SK_SEN_VOLT;
35669+ pSen->SenReg = LM80_VT4_IN;
35670+ break;
35671+ case 6:
35672+ if (CHIP_ID_YUKON_2(pAC)) {
35673+ pSen->SenDesc = "Voltage PHY 1V5";
35674+ pSen->SenThreErrHigh = SK_SEN_CORE_1V5_HIGH_ERR;
35675+ pSen->SenThreWarnHigh = SK_SEN_CORE_1V5_HIGH_WARN;
35676+ if (pAC->GIni.GIPciBus == SK_PEX_BUS) {
35677+ pSen->SenThreWarnLow = SK_SEN_CORE_1V5_LOW_WARN;
35678+ pSen->SenThreErrLow = SK_SEN_CORE_1V5_LOW_ERR;
35679+ }
35680+ else {
35681+ pSen->SenThreWarnLow = 0;
35682+ pSen->SenThreErrLow = 0;
35683+ }
35684+ }
35685+ else {
35686+ if (pAC->GIni.GIGenesis) {
35687+ pSen->SenDesc = "Voltage PHY B PLL";
35688+ }
35689+ else {
35690+ pSen->SenDesc = "Voltage PHY 3V3";
35691+ }
35692+ pSen->SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR;
35693+ pSen->SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN;
35694+ pSen->SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN;
35695+ pSen->SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR;
35696+ }
35697+ pSen->SenType = SK_SEN_VOLT;
35698+ pSen->SenReg = LM80_VT5_IN;
35699+ break;
35700+ case 7:
35701+ if (pAC->GIni.GIGenesis) {
35702+ pSen->SenDesc = "Speed Fan";
35703+ pSen->SenType = SK_SEN_FAN;
35704+ pSen->SenThreErrHigh = SK_SEN_FAN_HIGH_ERR;
35705+ pSen->SenThreWarnHigh = SK_SEN_FAN_HIGH_WARN;
35706+ pSen->SenThreWarnLow = SK_SEN_FAN_LOW_WARN;
35707+ pSen->SenThreErrLow = SK_SEN_FAN_LOW_ERR;
35708+ pSen->SenReg = LM80_FAN2_IN;
35709+ }
35710+ else {
35711+ pSen->SenDesc = "Voltage PHY 2V5";
35712+ pSen->SenType = SK_SEN_VOLT;
35713+ pSen->SenThreErrHigh = SK_SEN_PHY_2V5_HIGH_ERR;
35714+ pSen->SenThreWarnHigh = SK_SEN_PHY_2V5_HIGH_WARN;
35715+ pSen->SenThreWarnLow = SK_SEN_PHY_2V5_LOW_WARN;
35716+ pSen->SenThreErrLow = SK_SEN_PHY_2V5_LOW_ERR;
35717+ pSen->SenReg = LM80_VT6_IN;
35718+ }
35719+ break;
35720+ default:
35721+ SK_ERR_LOG(pAC, SK_ERRCL_INIT | SK_ERRCL_SW,
35722+ SKERR_I2C_E001, SKERR_I2C_E001MSG);
35723+ break;
35724+ }
35725+
35726+ pSen->SenValue = 0;
35727+ pSen->SenErrFlag = SK_SEN_ERR_OK;
35728+ pSen->SenErrCts = 0;
35729+ pSen->SenBegErrTS = 0;
35730+ pSen->SenState = SK_SEN_IDLE;
35731+ if (pSen->SenThreWarnLow != 0) {
35732+ pSen->SenRead = SkLm80ReadSensor;
35733+ }
35734+ pSen->SenDev = LM80_ADDR;
35735+ }
35736+
35737+#ifndef SK_DIAG
35738+ pAC->I2c.DummyReads = pAC->I2c.MaxSens;
35739+#endif /* !SK_DIAG */
35740+
35741+ /* Clear TWSI IRQ */
35742+ SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
35743+
35744+ /* Now we are I/O initialized */
35745+ pAC->I2c.InitLevel = SK_INIT_IO;
35746+ return(0);
35747+} /* SkI2cInit1 */
35748+
35749+
35750+/*
35751+ * Init level 2: Start first sensor read.
35752+ */
35753+static int SkI2cInit2(
35754+SK_AC *pAC, /* Adapter Context */
35755+SK_IOC IoC) /* I/O Context */
35756+{
35757+ int ReadComplete;
35758+ SK_SENSOR *pSen;
35759+
35760+ if (pAC->I2c.InitLevel != SK_INIT_IO) {
35761+ /* ReInit not needed in TWSI module */
35762+ /* Init0 and Init2 not permitted */
35763+ return(0);
35764+ }
35765+
35766+ pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
35767+
35768+ ReadComplete = SkI2cReadSensor(pAC, IoC, pSen);
35769+
35770+ if (ReadComplete) {
35771+ SK_ERR_LOG(pAC, SK_ERRCL_INIT, SKERR_I2C_E008, SKERR_I2C_E008MSG);
35772+ }
35773+
35774+ /* Now we are correctly initialized */
35775+ pAC->I2c.InitLevel = SK_INIT_RUN;
35776+
35777+ return(0);
35778+} /* SkI2cInit2*/
35779+
35780+
35781+/*
35782+ * Initialize TWSI devices
35783+ *
35784+ * Get the first voltage value and discard it.
35785+ * Go into temperature read mode. A default pointer is not set.
35786+ *
35787+ * The things to be done depend on the init level in the parameter list:
35788+ * Level 0:
35789+ * Initialize only the data structures. Do NOT access hardware.
35790+ * Level 1:
35791+ * Initialize hardware through SK_IN / SK_OUT commands. Do NOT use interrupts.
35792+ * Level 2:
35793+ * Everything is possible. Interrupts may be used from now on.
35794+ *
35795+ * return:
35796+ * 0 = success
35797+ * other = error.
35798+ */
35799+int SkI2cInit(
35800+SK_AC *pAC, /* Adapter Context */
35801+SK_IOC IoC, /* I/O Context needed in levels 1 and 2 */
35802+int Level) /* Init Level */
35803+{
35804+
35805+ switch (Level) {
35806+ case SK_INIT_DATA:
35807+ return(SkI2cInit0(pAC));
35808+ case SK_INIT_IO:
35809+ return(SkI2cInit1(pAC, IoC));
35810+ case SK_INIT_RUN:
35811+ return(SkI2cInit2(pAC, IoC));
35812+ default:
35813+ break;
35814+ }
35815+
35816+ return(0);
35817+} /* SkI2cInit */
35818+
35819+
35820+#ifndef SK_DIAG
35821+/*
35822+ * Interrupt service function for the TWSI Interface
35823+ *
35824+ * Clears the Interrupt source
35825+ *
35826+ * Reads the register and check it for sending a trap.
35827+ *
35828+ * Starts the timer if necessary.
35829+ */
35830+void SkI2cIsr(
35831+SK_AC *pAC, /* Adapter Context */
35832+SK_IOC IoC) /* I/O Context */
35833+{
35834+ SK_EVPARA Para;
35835+
35836+ /* Clear TWSI IRQ */
35837+ SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
35838+
35839+ Para.Para64 = 0;
35840+ SkEventQueue(pAC, SKGE_I2C, SK_I2CEV_IRQ, Para);
35841+} /* SkI2cIsr */
35842+
35843+
35844+/*
35845+ * Check this sensors Value against the threshold and send events.
35846+ */
35847+static void SkI2cCheckSensor(
35848+SK_AC *pAC, /* Adapter Context */
35849+SK_SENSOR *pSen)
35850+{
35851+ SK_EVPARA ParaLocal;
35852+ SK_BOOL TooHigh; /* Is sensor too high? */
35853+ SK_BOOL TooLow; /* Is sensor too low? */
35854+ SK_U64 CurrTime; /* Current Time */
35855+ SK_BOOL DoTrapSend; /* We need to send a trap */
35856+ SK_BOOL DoErrLog; /* We need to log the error */
35857+ SK_BOOL IsError; /* Error occured */
35858+
35859+ /* Check Dummy Reads first */
35860+ if (pAC->I2c.DummyReads > 0) {
35861+ pAC->I2c.DummyReads--;
35862+ return;
35863+ }
35864+
35865+ /* Get the current time */
35866+ CurrTime = SkOsGetTime(pAC);
35867+
35868+ /* Set para to the most useful setting: The current sensor. */
35869+ ParaLocal.Para64 = (SK_U64)pAC->I2c.CurrSens;
35870+
35871+ /* Check the Value against the thresholds. First: Error Thresholds */
35872+ TooHigh = pSen->SenValue > pSen->SenThreErrHigh;
35873+ TooLow = pSen->SenValue < pSen->SenThreErrLow;
35874+
35875+ IsError = SK_FALSE;
35876+
35877+ if (TooHigh || TooLow) {
35878+ /* Error condition is satisfied */
35879+ DoTrapSend = SK_TRUE;
35880+ DoErrLog = SK_TRUE;
35881+
35882+ /* Now error condition is satisfied */
35883+ IsError = SK_TRUE;
35884+
35885+ if (pSen->SenErrFlag == SK_SEN_ERR_ERR) {
35886+ /* This state is the former one */
35887+
35888+ /* So check first whether we have to send a trap */
35889+ if (pSen->SenLastErrTrapTS + SK_SEN_ERR_TR_HOLD > CurrTime) {
35890+ /*
35891+ * Do NOT send the Trap. The hold back time
35892+ * has to run out first.
35893+ */
35894+ DoTrapSend = SK_FALSE;
35895+ }
35896+
35897+ /* Check now whether we have to log an Error */
35898+ if (pSen->SenLastErrLogTS + SK_SEN_ERR_LOG_HOLD > CurrTime) {
35899+ /*
35900+ * Do NOT log the error. The hold back time
35901+ * has to run out first.
35902+ */
35903+ DoErrLog = SK_FALSE;
35904+ }
35905+ }
35906+ else {
35907+ /* We came from a different state -> Set Begin Time Stamp */
35908+ pSen->SenBegErrTS = CurrTime;
35909+ pSen->SenErrFlag = SK_SEN_ERR_ERR;
35910+ }
35911+
35912+ if (DoTrapSend) {
35913+ /* Set current Time */
35914+ pSen->SenLastErrTrapTS = CurrTime;
35915+ pSen->SenErrCts++;
35916+
35917+ /* Queue PNMI Event */
35918+ SkEventQueue(pAC, SKGE_PNMI, TooHigh ?
35919+ SK_PNMI_EVT_SEN_ERR_UPP : SK_PNMI_EVT_SEN_ERR_LOW,
35920+ ParaLocal);
35921+ }
35922+
35923+ if (DoErrLog) {
35924+ /* Set current Time */
35925+ pSen->SenLastErrLogTS = CurrTime;
35926+
35927+ if (pSen->SenType == SK_SEN_TEMP) {
35928+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E011, SKERR_I2C_E011MSG);
35929+ }
35930+ else if (pSen->SenType == SK_SEN_VOLT) {
35931+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E012, SKERR_I2C_E012MSG);
35932+ }
35933+ else {
35934+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E015, SKERR_I2C_E015MSG);
35935+ }
35936+ }
35937+ }
35938+
35939+ /* Check the Value against the thresholds */
35940+ /* 2nd: Warning thresholds */
35941+ TooHigh = pSen->SenValue > pSen->SenThreWarnHigh;
35942+ TooLow = pSen->SenValue < pSen->SenThreWarnLow;
35943+
35944+ if (!IsError && (TooHigh || TooLow)) {
35945+ /* Error condition is satisfied */
35946+ DoTrapSend = SK_TRUE;
35947+ DoErrLog = SK_TRUE;
35948+
35949+ if (pSen->SenErrFlag == SK_SEN_ERR_WARN) {
35950+ /* This state is the former one */
35951+
35952+ /* So check first whether we have to send a trap */
35953+ if (pSen->SenLastWarnTrapTS + SK_SEN_WARN_TR_HOLD > CurrTime) {
35954+ /*
35955+ * Do NOT send the Trap. The hold back time
35956+ * has to run out first.
35957+ */
35958+ DoTrapSend = SK_FALSE;
35959+ }
35960+
35961+ /* Check now whether we have to log an Error */
35962+ if (pSen->SenLastWarnLogTS + SK_SEN_WARN_LOG_HOLD > CurrTime) {
35963+ /*
35964+ * Do NOT log the error. The hold back time
35965+ * has to run out first.
35966+ */
35967+ DoErrLog = SK_FALSE;
35968+ }
35969+ }
35970+ else {
35971+ /* We came from a different state -> Set Begin Time Stamp */
35972+ pSen->SenBegWarnTS = CurrTime;
35973+ pSen->SenErrFlag = SK_SEN_ERR_WARN;
35974+ }
35975+
35976+ if (DoTrapSend) {
35977+ /* Set current Time */
35978+ pSen->SenLastWarnTrapTS = CurrTime;
35979+ pSen->SenWarnCts++;
35980+
35981+ /* Queue PNMI Event */
35982+ SkEventQueue(pAC, SKGE_PNMI, TooHigh ?
35983+ SK_PNMI_EVT_SEN_WAR_UPP : SK_PNMI_EVT_SEN_WAR_LOW, ParaLocal);
35984+ }
35985+
35986+ if (DoErrLog) {
35987+ /* Set current Time */
35988+ pSen->SenLastWarnLogTS = CurrTime;
35989+
35990+ if (pSen->SenType == SK_SEN_TEMP) {
35991+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E009, SKERR_I2C_E009MSG);
35992+ }
35993+ else if (pSen->SenType == SK_SEN_VOLT) {
35994+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E010, SKERR_I2C_E010MSG);
35995+ }
35996+ else {
35997+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E014, SKERR_I2C_E014MSG);
35998+ }
35999+ }
36000+ }
36001+
36002+ /* Check for NO error at all */
36003+ if (!IsError && !TooHigh && !TooLow) {
36004+ /* Set o.k. Status if no error and no warning condition */
36005+ pSen->SenErrFlag = SK_SEN_ERR_OK;
36006+ }
36007+
36008+ /* End of check against the thresholds */
36009+
36010+ if (pSen->SenInit == SK_SEN_DYN_INIT_PCI_IO) {
36011+ /* Bug fix AF: 16.Aug.2001: Correct the init base of LM80 sensor */
36012+ pSen->SenInit = SK_SEN_DYN_INIT_NONE;
36013+
36014+ if (pSen->SenValue > SK_SEN_PCI_IO_RANGE_LIMITER) {
36015+ /* 5V PCI-IO Voltage */
36016+ pSen->SenThreWarnLow = SK_SEN_PCI_IO_5V_LOW_WARN;
36017+ pSen->SenThreErrLow = SK_SEN_PCI_IO_5V_LOW_ERR;
36018+ }
36019+ else {
36020+ /* 3.3V PCI-IO Voltage */
36021+ pSen->SenThreWarnHigh = SK_SEN_PCI_IO_3V3_HIGH_WARN;
36022+ pSen->SenThreErrHigh = SK_SEN_PCI_IO_3V3_HIGH_ERR;
36023+ }
36024+ }
36025+
36026+#ifdef TEST_ONLY
36027+ /* Dynamic thresholds also for VAUX of LM80 sensor */
36028+ if (pSen->SenInit == SK_SEN_DYN_INIT_VAUX) {
36029+
36030+ pSen->SenInit = SK_SEN_DYN_INIT_NONE;
36031+
36032+ /* 3.3V VAUX Voltage */
36033+ if (pSen->SenValue > SK_SEN_VAUX_RANGE_LIMITER) {
36034+ pSen->SenThreWarnLow = SK_SEN_VAUX_3V3_LOW_WARN;
36035+ pSen->SenThreErrLow = SK_SEN_VAUX_3V3_LOW_ERR;
36036+ }
36037+ /* 0V VAUX Voltage */
36038+ else {
36039+ pSen->SenThreWarnHigh = SK_SEN_VAUX_0V_WARN_ERR;
36040+ pSen->SenThreErrHigh = SK_SEN_VAUX_0V_WARN_ERR;
36041+ }
36042+ }
36043+
36044+ /* Check initialization state: the VIO Thresholds need adaption */
36045+ if (!pSen->SenInit && pSen->SenReg == LM80_VT1_IN &&
36046+ pSen->SenValue > SK_SEN_WARNLOW2C &&
36047+ pSen->SenValue < SK_SEN_WARNHIGH2) {
36048+
36049+ pSen->SenThreErrLow = SK_SEN_ERRLOW2C;
36050+ pSen->SenThreWarnLow = SK_SEN_WARNLOW2C;
36051+ pSen->SenInit = SK_TRUE;
36052+ }
36053+
36054+ if (!pSen->SenInit && pSen->SenReg == LM80_VT1_IN &&
36055+ pSen->SenValue > SK_SEN_WARNLOW2 &&
36056+ pSen->SenValue < SK_SEN_WARNHIGH2C) {
36057+
36058+ pSen->SenThreErrHigh = SK_SEN_ERRHIGH2C;
36059+ pSen->SenThreWarnHigh = SK_SEN_WARNHIGH2C;
36060+ pSen->SenInit = SK_TRUE;
36061+ }
36062+#endif
36063+
36064+ if (pSen->SenInit != SK_SEN_DYN_INIT_NONE) {
36065+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E013, SKERR_I2C_E013MSG);
36066+ }
36067+} /* SkI2cCheckSensor */
36068+
36069+
36070+/*
36071+ * The only Event to be served is the timeout event
36072+ *
36073+ */
36074+int SkI2cEvent(
36075+SK_AC *pAC, /* Adapter Context */
36076+SK_IOC IoC, /* I/O Context */
36077+SK_U32 Event, /* Module specific Event */
36078+SK_EVPARA Para) /* Event specific Parameter */
36079+{
36080+ int ReadComplete;
36081+ SK_SENSOR *pSen;
36082+ SK_U32 Time;
36083+ SK_EVPARA ParaLocal;
36084+ int i;
36085+
36086+ /* New case: no sensors */
36087+ if (pAC->I2c.MaxSens == 0) {
36088+ return(0);
36089+ }
36090+
36091+ switch (Event) {
36092+ case SK_I2CEV_IRQ:
36093+ pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
36094+ ReadComplete = SkI2cReadSensor(pAC, IoC, pSen);
36095+
36096+ if (ReadComplete) {
36097+ /* Check sensor against defined thresholds */
36098+ SkI2cCheckSensor(pAC, pSen);
36099+
36100+ /* Increment Current sensor and set appropriate Timeout */
36101+ pAC->I2c.CurrSens++;
36102+ if (pAC->I2c.CurrSens >= pAC->I2c.MaxSens) {
36103+ pAC->I2c.CurrSens = 0;
36104+ Time = SK_I2C_TIM_LONG;
36105+ }
36106+ else {
36107+ Time = SK_I2C_TIM_SHORT;
36108+ }
36109+
36110+ /* Start Timer */
36111+ ParaLocal.Para64 = (SK_U64)0;
36112+
36113+ pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING;
36114+
36115+ SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time,
36116+ SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
36117+ }
36118+ else {
36119+ /* Start Timer */
36120+ ParaLocal.Para64 = (SK_U64)0;
36121+
36122+ pAC->I2c.TimerMode = SK_TIMER_WATCH_SM;
36123+
36124+ SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, SK_I2C_TIM_WATCH,
36125+ SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
36126+ }
36127+ break;
36128+ case SK_I2CEV_TIM:
36129+ if (pAC->I2c.TimerMode == SK_TIMER_NEW_GAUGING) {
36130+
36131+ ParaLocal.Para64 = (SK_U64)0;
36132+ SkTimerStop(pAC, IoC, &pAC->I2c.SenTimer);
36133+
36134+ pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
36135+ ReadComplete = SkI2cReadSensor(pAC, IoC, pSen);
36136+
36137+ if (ReadComplete) {
36138+ /* Check sensor against defined thresholds */
36139+ SkI2cCheckSensor(pAC, pSen);
36140+
36141+ /* Increment Current sensor and set appropriate Timeout */
36142+ pAC->I2c.CurrSens++;
36143+ if (pAC->I2c.CurrSens == pAC->I2c.MaxSens) {
36144+ pAC->I2c.CurrSens = 0;
36145+ Time = SK_I2C_TIM_LONG;
36146+ }
36147+ else {
36148+ Time = SK_I2C_TIM_SHORT;
36149+ }
36150+
36151+ /* Start Timer */
36152+ ParaLocal.Para64 = (SK_U64)0;
36153+
36154+ pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING;
36155+
36156+ SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time,
36157+ SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
36158+ }
36159+ }
36160+ else {
36161+ pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
36162+ pSen->SenErrFlag = SK_SEN_ERR_FAULTY;
36163+ SK_I2C_STOP(IoC);
36164+
36165+ /* Increment Current sensor and set appropriate Timeout */
36166+ pAC->I2c.CurrSens++;
36167+ if (pAC->I2c.CurrSens == pAC->I2c.MaxSens) {
36168+ pAC->I2c.CurrSens = 0;
36169+ Time = SK_I2C_TIM_LONG;
36170+ }
36171+ else {
36172+ Time = SK_I2C_TIM_SHORT;
36173+ }
36174+
36175+ /* Start Timer */
36176+ ParaLocal.Para64 = (SK_U64)0;
36177+
36178+ pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING;
36179+
36180+ SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time,
36181+ SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
36182+ }
36183+ break;
36184+ case SK_I2CEV_CLEAR:
36185+ for (i = 0; i < SK_MAX_SENSORS; i++) {
36186+ pSen = &pAC->I2c.SenTable[i];
36187+
36188+ pSen->SenErrFlag = SK_SEN_ERR_OK;
36189+ pSen->SenErrCts = 0;
36190+ pSen->SenWarnCts = 0;
36191+ pSen->SenBegErrTS = 0;
36192+ pSen->SenBegWarnTS = 0;
36193+ pSen->SenLastErrTrapTS = (SK_U64)0;
36194+ pSen->SenLastErrLogTS = (SK_U64)0;
36195+ pSen->SenLastWarnTrapTS = (SK_U64)0;
36196+ pSen->SenLastWarnLogTS = (SK_U64)0;
36197+ }
36198+ break;
36199+ default:
36200+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E006, SKERR_I2C_E006MSG);
36201+ }
36202+
36203+ return(0);
36204+} /* SkI2cEvent*/
36205+
36206+#endif /* !SK_DIAG */
36207+
36208diff -urN linux-2.6.17.orig/drivers/net/sk98lin/skvpd.c linux-2.6.17/drivers/net/sk98lin/skvpd.c
36209--- linux-2.6.17.orig/drivers/net/sk98lin/skvpd.c 2006-06-22 13:17:16.000000000 +0200
36210+++ linux-2.6.17/drivers/net/sk98lin/skvpd.c 2006-04-27 11:43:44.000000000 +0200
36211@@ -1,22 +1,22 @@
36212 /******************************************************************************
36213 *
36214 * Name: skvpd.c
36215- * Project: GEnesis, PCI Gigabit Ethernet Adapter
36216- * Version: $Revision$
36217- * Date: $Date$
36218- * Purpose: Shared software to read and write VPD data
36219+ * Project: Gigabit Ethernet Adapters, VPD-Module
36220+ * Version: $Revision$
36221+ * Date: $Date$
36222+ * Purpose: Shared software to read and write VPD
36223 *
36224 ******************************************************************************/
36225
36226 /******************************************************************************
36227 *
36228- * (C)Copyright 1998-2003 SysKonnect GmbH.
36229+ * (C)Copyright 1998-2002 SysKonnect.
36230+ * (C)Copyright 2002-2004 Marvell.
36231 *
36232 * This program is free software; you can redistribute it and/or modify
36233 * it under the terms of the GNU General Public License as published by
36234 * the Free Software Foundation; either version 2 of the License, or
36235 * (at your option) any later version.
36236- *
36237 * The information in this file is provided "AS IS" without warranty.
36238 *
36239 ******************************************************************************/
36240@@ -25,7 +25,7 @@
36241 Please refer skvpd.txt for infomation how to include this module
36242 */
36243 static const char SysKonnectFileId[] =
36244- "@(#)$Id$ (C) SK";
36245+ "@(#) $Id$ (C) Marvell.";
36246
36247 #include "h/skdrv1st.h"
36248 #include "h/sktypes.h"
36249@@ -59,9 +59,10 @@
36250 SK_U64 start_time;
36251 SK_U16 state;
36252
36253- SK_DBG_MSG(pAC,SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
36254+ SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
36255 ("VPD wait for %s\n", event?"Write":"Read"));
36256 start_time = SkOsGetTime(pAC);
36257+
36258 do {
36259 if (SkOsGetTime(pAC) - start_time > SK_TICKS_PER_SEC) {
36260
36261@@ -81,17 +82,18 @@
36262 ("ERROR:VPD wait timeout\n"));
36263 return(1);
36264 }
36265-
36266+
36267 VPD_IN16(pAC, IoC, PCI_VPD_ADR_REG, &state);
36268-
36269+
36270 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
36271 ("state = %x, event %x\n",state,event));
36272- } while((int)(state & PCI_VPD_FLAG) == event);
36273+ } while ((int)(state & PCI_VPD_FLAG) == event);
36274
36275 return(0);
36276 }
36277
36278-#ifdef SKDIAG
36279+
36280+#ifdef SK_DIAG
36281
36282 /*
36283 * Read the dword at address 'addr' from the VPD EEPROM.
36284@@ -124,13 +126,71 @@
36285 Rtv = 0;
36286
36287 VPD_IN32(pAC, IoC, PCI_VPD_DAT_REG, &Rtv);
36288-
36289+
36290 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
36291 ("VPD read dword data = 0x%x\n",Rtv));
36292 return(Rtv);
36293 }
36294+#endif /* SK_DIAG */
36295+
36296+
36297+#ifdef XXX
36298+/*
36299+ Write the dword 'data' at address 'addr' into the VPD EEPROM, and
36300+ verify that the data is written.
36301+
36302+ Needed Time:
36303+
36304+. MIN MAX
36305+. -------------------------------------------------------------------
36306+. write 1.8 ms 3.6 ms
36307+. internal write cyles 0.7 ms 7.0 ms
36308+. -------------------------------------------------------------------
36309+. over all program time 2.5 ms 10.6 ms
36310+. read 1.3 ms 2.6 ms
36311+. -------------------------------------------------------------------
36312+. over all 3.8 ms 13.2 ms
36313+.
36314+
36315+ Returns 0: success
36316+ 1: error, I2C transfer does not terminate
36317+ 2: error, data verify error
36318+
36319+ */
36320+static int VpdWriteDWord(
36321+SK_AC *pAC, /* pAC pointer */
36322+SK_IOC IoC, /* IO Context */
36323+int addr, /* VPD address */
36324+SK_U32 data) /* VPD data to write */
36325+{
36326+ /* start VPD write */
36327+ /* Don't swap here, it's a data stream of bytes */
36328+ SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
36329+ ("VPD write dword at addr 0x%x, data = 0x%x\n",addr,data));
36330+ VPD_OUT32(pAC, IoC, PCI_VPD_DAT_REG, (SK_U32)data);
36331+ /* But do it here */
36332+ addr |= VPD_WRITE;
36333+
36334+ VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, (SK_U16)(addr | VPD_WRITE));
36335+
36336+ /* this may take up to 10,6 ms */
36337+ if (VpdWait(pAC, IoC, VPD_WRITE)) {
36338+ SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36339+ ("Write Timed Out\n"));
36340+ return(1);
36341+ };
36342+
36343+ /* verify data */
36344+ if (VpdReadDWord(pAC, IoC, addr) != data) {
36345+ SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
36346+ ("Data Verify Error\n"));
36347+ return(2);
36348+ }
36349+ return(0);
36350+} /* VpdWriteDWord */
36351+
36352+#endif /* XXX */
36353
36354-#endif /* SKDIAG */
36355
36356 /*
36357 * Read one Stream of 'len' bytes of VPD data, starting at 'addr' from
36358@@ -156,7 +216,7 @@
36359 pComp = (SK_U8 *) buf;
36360
36361 for (i = 0; i < Len; i++, buf++) {
36362- if ((i%sizeof(SK_U32)) == 0) {
36363+ if ((i % SZ_LONG) == 0) {
36364 /*
36365 * At the begin of each cycle read the Data Reg
36366 * So it is initialized even if only a few bytes
36367@@ -174,14 +234,13 @@
36368 }
36369 }
36370
36371- /* Write current Byte */
36372- VPD_OUT8(pAC, IoC, PCI_VPD_DAT_REG + (i%sizeof(SK_U32)),
36373- *(SK_U8*)buf);
36374+ /* Write current byte */
36375+ VPD_OUT8(pAC, IoC, PCI_VPD_DAT_REG + (i % SZ_LONG), *(SK_U8*)buf);
36376
36377- if (((i%sizeof(SK_U32)) == 3) || (i == (Len - 1))) {
36378+ if (((i % SZ_LONG) == 3) || (i == (Len - 1))) {
36379 /* New Address needs to be written to VPD_ADDR reg */
36380 AdrReg = (SK_U16) Addr;
36381- Addr += sizeof(SK_U32);
36382+ Addr += SZ_LONG;
36383 AdrReg |= VPD_WRITE; /* WRITE operation */
36384
36385 VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, AdrReg);
36386@@ -191,7 +250,7 @@
36387 if (Rtv != 0) {
36388 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36389 ("Write Timed Out\n"));
36390- return(i - (i%sizeof(SK_U32)));
36391+ return(i - (i % SZ_LONG));
36392 }
36393
36394 /*
36395@@ -206,18 +265,18 @@
36396 if (Rtv != 0) {
36397 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36398 ("Verify Timed Out\n"));
36399- return(i - (i%sizeof(SK_U32)));
36400+ return(i - (i % SZ_LONG));
36401 }
36402
36403- for (j = 0; j <= (int)(i%sizeof(SK_U32)); j++, pComp++) {
36404-
36405+ for (j = 0; j <= (int)(i % SZ_LONG); j++, pComp++) {
36406+
36407 VPD_IN8(pAC, IoC, PCI_VPD_DAT_REG + j, &Data);
36408-
36409+
36410 if (Data != *pComp) {
36411 /* Verify Error */
36412 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36413 ("WriteStream Verify Error\n"));
36414- return(i - (i%sizeof(SK_U32)) + j);
36415+ return(i - (i % SZ_LONG) + j);
36416 }
36417 }
36418 }
36419@@ -225,7 +284,7 @@
36420
36421 return(Len);
36422 }
36423-
36424+
36425
36426 /*
36427 * Read one Stream of 'len' bytes of VPD data, starting at 'addr' from
36428@@ -245,10 +304,10 @@
36429 int Rtv;
36430
36431 for (i = 0; i < Len; i++, buf++) {
36432- if ((i%sizeof(SK_U32)) == 0) {
36433+ if ((i % SZ_LONG) == 0) {
36434 /* New Address needs to be written to VPD_ADDR reg */
36435 AdrReg = (SK_U16) Addr;
36436- Addr += sizeof(SK_U32);
36437+ Addr += SZ_LONG;
36438 AdrReg &= ~VPD_WRITE; /* READ operation */
36439
36440 VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, AdrReg);
36441@@ -259,13 +318,13 @@
36442 return(i);
36443 }
36444 }
36445- VPD_IN8(pAC, IoC, PCI_VPD_DAT_REG + (i%sizeof(SK_U32)),
36446- (SK_U8 *)buf);
36447+ VPD_IN8(pAC, IoC, PCI_VPD_DAT_REG + (i % SZ_LONG), (SK_U8 *)buf);
36448 }
36449
36450 return(Len);
36451 }
36452
36453+
36454 /*
36455 * Read ore writes 'len' bytes of VPD data, starting at 'addr' from
36456 * or to the I2C EEPROM.
36457@@ -291,14 +350,14 @@
36458 return(0);
36459
36460 vpd_rom_size = pAC->vpd.rom_size;
36461-
36462+
36463 if (addr > vpd_rom_size - 4) {
36464 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
36465 ("Address error: 0x%x, exp. < 0x%x\n",
36466 addr, vpd_rom_size - 4));
36467 return(0);
36468 }
36469-
36470+
36471 if (addr + len > vpd_rom_size) {
36472 len = vpd_rom_size - addr;
36473 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36474@@ -315,8 +374,8 @@
36475 return(Rtv);
36476 }
36477
36478-#ifdef SKDIAG
36479
36480+#if defined (SK_DIAG) || defined (SK_ASF)
36481 /*
36482 * Read 'len' bytes of VPD data, starting at 'addr'.
36483 *
36484@@ -332,6 +391,7 @@
36485 return(VpdTransferBlock(pAC, IoC, buf, addr, len, VPD_READ));
36486 }
36487
36488+
36489 /*
36490 * Write 'len' bytes of *but to the VPD EEPROM, starting at 'addr'.
36491 *
36492@@ -346,18 +406,27 @@
36493 {
36494 return(VpdTransferBlock(pAC, IoC, buf, addr, len, VPD_WRITE));
36495 }
36496-#endif /* SKDIAG */
36497+#endif /* SK_DIAG */
36498
36499-/*
36500- * (re)initialize the VPD buffer
36501+
36502+/******************************************************************************
36503 *
36504- * Reads the VPD data from the EEPROM into the VPD buffer.
36505- * Get the remaining read only and read / write space.
36506+ * VpdInit() - (re)initialize the VPD buffer
36507 *
36508- * return 0: success
36509- * 1: fatal VPD error
36510+ * Description:
36511+ * Reads the VPD data from the EEPROM into the VPD buffer.
36512+ * Get the remaining read only and read / write space.
36513+ *
36514+ * Note:
36515+ * This is a local function and should be used locally only.
36516+ * However, the ASF module needs to use this function also.
36517+ * Therfore it has been published.
36518+ *
36519+ * Returns:
36520+ * 0: success
36521+ * 1: fatal VPD error
36522 */
36523-static int VpdInit(
36524+int VpdInit(
36525 SK_AC *pAC, /* Adapters context */
36526 SK_IOC IoC) /* IO Context */
36527 {
36528@@ -368,14 +437,14 @@
36529 SK_U16 dev_id;
36530 SK_U32 our_reg2;
36531
36532- SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_INIT, ("VpdInit .. "));
36533-
36534+ SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_INIT, ("VpdInit ... "));
36535+
36536 VPD_IN16(pAC, IoC, PCI_DEVICE_ID, &dev_id);
36537-
36538+
36539 VPD_IN32(pAC, IoC, PCI_OUR_REG_2, &our_reg2);
36540-
36541+
36542 pAC->vpd.rom_size = 256 << ((our_reg2 & PCI_VPD_ROM_SZ) >> 14);
36543-
36544+
36545 /*
36546 * this function might get used before the hardware is initialized
36547 * therefore we cannot always trust in GIChipId
36548@@ -406,19 +475,15 @@
36549 ("Block Read Error\n"));
36550 return(1);
36551 }
36552-
36553+
36554 pAC->vpd.vpd_size = vpd_size;
36555
36556 /* Asus K8V Se Deluxe bugfix. Correct VPD content */
36557- /* MBo April 2004 */
36558- if (((unsigned char)pAC->vpd.vpd_buf[0x3f] == 0x38) &&
36559- ((unsigned char)pAC->vpd.vpd_buf[0x40] == 0x3c) &&
36560- ((unsigned char)pAC->vpd.vpd_buf[0x41] == 0x45)) {
36561- printk("sk98lin: Asus mainboard with buggy VPD? "
36562- "Correcting data.\n");
36563- pAC->vpd.vpd_buf[0x40] = 0x38;
36564- }
36565+ i = 62;
36566+ if (!SK_STRNCMP(pAC->vpd.vpd_buf + i, " 8<E", 4)) {
36567
36568+ pAC->vpd.vpd_buf[i + 2] = '8';
36569+ }
36570
36571 /* find the end tag of the RO area */
36572 if (!(r = vpd_find_para(pAC, VPD_RV, &rp))) {
36573@@ -426,9 +491,9 @@
36574 ("Encoding Error: RV Tag not found\n"));
36575 return(1);
36576 }
36577-
36578+
36579 if (r->p_val + r->p_len > pAC->vpd.vpd_buf + vpd_size/2) {
36580- SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
36581+ SK_DBG_MSG(pAC, SK_DBGMOD_VPD,SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
36582 ("Encoding Error: Invalid VPD struct size\n"));
36583 return(1);
36584 }
36585@@ -438,7 +503,7 @@
36586 for (i = 0, x = 0; (unsigned)i <= (unsigned)vpd_size/2 - r->p_len; i++) {
36587 x += pAC->vpd.vpd_buf[i];
36588 }
36589-
36590+
36591 if (x != 0) {
36592 /* checksum error */
36593 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
36594@@ -452,7 +517,7 @@
36595 ("Encoding Error: RV Tag not found\n"));
36596 return(1);
36597 }
36598-
36599+
36600 if (r->p_val < pAC->vpd.vpd_buf + vpd_size/2) {
36601 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
36602 ("Encoding Error: Invalid VPD struct size\n"));
36603@@ -472,6 +537,7 @@
36604 return(0);
36605 }
36606
36607+
36608 /*
36609 * find the Keyword 'key' in the VPD buffer and fills the
36610 * parameter struct 'p' with it's values
36611@@ -482,7 +548,7 @@
36612 static SK_VPD_PARA *vpd_find_para(
36613 SK_AC *pAC, /* common data base */
36614 const char *key, /* keyword to find (e.g. "MN") */
36615-SK_VPD_PARA *p) /* parameter description struct */
36616+SK_VPD_PARA *p) /* parameter description struct */
36617 {
36618 char *v ; /* points to VPD buffer */
36619 int max; /* Maximum Number of Iterations */
36620@@ -497,10 +563,10 @@
36621 if (*v != (char)RES_ID) {
36622 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
36623 ("Error: 0x%x missing\n", RES_ID));
36624- return NULL;
36625+ return(0);
36626 }
36627
36628- if (strcmp(key, VPD_NAME) == 0) {
36629+ if (SK_STRCMP(key, VPD_NAME) == 0) {
36630 p->p_len = VPD_GET_RES_LEN(v);
36631 p->p_val = VPD_GET_VAL(v);
36632 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
36633@@ -510,7 +576,7 @@
36634
36635 v += 3 + VPD_GET_RES_LEN(v) + 3;
36636 for (;; ) {
36637- if (SK_MEMCMP(key,v,2) == 0) {
36638+ if (SK_MEMCMP(key, v, 2) == 0) {
36639 p->p_len = VPD_GET_VPD_LEN(v);
36640 p->p_val = VPD_GET_VAL(v);
36641 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
36642@@ -520,11 +586,11 @@
36643
36644 /* exit when reaching the "RW" Tag or the maximum of itera. */
36645 max--;
36646- if (SK_MEMCMP(VPD_RW,v,2) == 0 || max == 0) {
36647+ if (SK_MEMCMP(VPD_RW, v, 2) == 0 || max == 0) {
36648 break;
36649 }
36650
36651- if (SK_MEMCMP(VPD_RV,v,2) == 0) {
36652+ if (SK_MEMCMP(VPD_RV, v, 2) == 0) {
36653 v += 3 + VPD_GET_VPD_LEN(v) + 3; /* skip VPD-W */
36654 }
36655 else {
36656@@ -541,9 +607,10 @@
36657 ("Key/Len Encoding error\n"));
36658 }
36659 #endif /* DEBUG */
36660- return NULL;
36661+ return(0);
36662 }
36663
36664+
36665 /*
36666 * Move 'n' bytes. Begin with the last byte if 'n' is > 0,
36667 * Start with the last byte if n is < 0.
36668@@ -578,6 +645,7 @@
36669 }
36670 }
36671
36672+
36673 /*
36674 * setup the VPD keyword 'key' at 'ip'.
36675 *
36676@@ -594,10 +662,11 @@
36677 p = (SK_VPD_KEY *) ip;
36678 p->p_key[0] = key[0];
36679 p->p_key[1] = key[1];
36680- p->p_len = (unsigned char) len;
36681- SK_MEMCPY(&p->p_val,buf,len);
36682+ p->p_len = (unsigned char)len;
36683+ SK_MEMCPY(&p->p_val, buf, len);
36684 }
36685
36686+
36687 /*
36688 * Setup the VPD end tag "RV" / "RW".
36689 * Also correct the remaining space variables vpd_free_ro / vpd_free_rw.
36690@@ -623,7 +692,7 @@
36691
36692 if (p->p_key[0] != 'R' || (p->p_key[1] != 'V' && p->p_key[1] != 'W')) {
36693 /* something wrong here, encoding error */
36694- SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
36695+ SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
36696 ("Encoding Error: invalid end tag\n"));
36697 return(1);
36698 }
36699@@ -655,6 +724,7 @@
36700 return(0);
36701 }
36702
36703+
36704 /*
36705 * Insert a VPD keyword into the VPD buffer.
36706 *
36707@@ -669,7 +739,7 @@
36708 * 6: fatal VPD error
36709 *
36710 */
36711-static int VpdSetupPara(
36712+int VpdSetupPara(
36713 SK_AC *pAC, /* common data base */
36714 const char *key, /* keyword to insert */
36715 const char *buf, /* buffer with the keyword value */
36716@@ -688,11 +758,11 @@
36717
36718 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
36719 ("VPD setup para key = %s, val = %s\n",key,buf));
36720-
36721+
36722 vpd_size = pAC->vpd.vpd_size;
36723
36724 rtv = 0;
36725- ip = NULL;
36726+ ip = 0;
36727 if (type == VPD_RW_KEY) {
36728 /* end tag is "RW" */
36729 free = pAC->vpd.v.vpd_free_rw;
36730@@ -816,18 +886,18 @@
36731 }
36732 }
36733
36734- if ((signed)strlen(VPD_NAME) + 1 <= *len) {
36735+ if ((signed)SK_STRLEN(VPD_NAME) + 1 <= *len) {
36736 v = pAC->vpd.vpd_buf;
36737- strcpy(buf,VPD_NAME);
36738- n = strlen(VPD_NAME) + 1;
36739+ SK_STRCPY(buf, VPD_NAME);
36740+ n = SK_STRLEN(VPD_NAME) + 1;
36741 buf += n;
36742 *elements = 1;
36743 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX,
36744- ("'%c%c' ",v[0],v[1]));
36745+ ("'%c%c' ", v[0], v[1]));
36746 }
36747 else {
36748 *len = 0;
36749- SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR,
36750+ SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36751 ("buffer overflow\n"));
36752 return(2);
36753 }
36754@@ -835,17 +905,17 @@
36755 v += 3 + VPD_GET_RES_LEN(v) + 3;
36756 for (;; ) {
36757 /* exit when reaching the "RW" Tag */
36758- if (SK_MEMCMP(VPD_RW,v,2) == 0) {
36759+ if (SK_MEMCMP(VPD_RW, v, 2) == 0) {
36760 break;
36761 }
36762
36763- if (SK_MEMCMP(VPD_RV,v,2) == 0) {
36764+ if (SK_MEMCMP(VPD_RV, v, 2) == 0) {
36765 v += 3 + VPD_GET_VPD_LEN(v) + 3; /* skip VPD-W */
36766 continue;
36767 }
36768
36769 if (n+3 <= *len) {
36770- SK_MEMCPY(buf,v,2);
36771+ SK_MEMCPY(buf, v, 2);
36772 buf += 2;
36773 *buf++ = '\0';
36774 n += 3;
36775@@ -932,13 +1002,14 @@
36776 {
36777 if ((*key != 'Y' && *key != 'V') ||
36778 key[1] < '0' || key[1] > 'Z' ||
36779- (key[1] > '9' && key[1] < 'A') || strlen(key) != 2) {
36780+ (key[1] > '9' && key[1] < 'A') || SK_STRLEN(key) != 2) {
36781
36782 return(SK_FALSE);
36783 }
36784 return(SK_TRUE);
36785 }
36786
36787+
36788 /*
36789 * Read the contents of the VPD EEPROM and copy it to the VPD
36790 * buffer if not already done. Insert/overwrite the keyword 'key'
36791@@ -967,7 +1038,7 @@
36792
36793 if ((*key != 'Y' && *key != 'V') ||
36794 key[1] < '0' || key[1] > 'Z' ||
36795- (key[1] > '9' && key[1] < 'A') || strlen(key) != 2) {
36796+ (key[1] > '9' && key[1] < 'A') || SK_STRLEN(key) != 2) {
36797
36798 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36799 ("illegal key tag, keyword not written\n"));
36800@@ -983,13 +1054,13 @@
36801 }
36802
36803 rtv = 0;
36804- len = strlen(buf);
36805+ len = SK_STRLEN(buf);
36806 if (len > VPD_MAX_LEN) {
36807 /* cut it */
36808 len = VPD_MAX_LEN;
36809 rtv = 2;
36810 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36811- ("keyword too long, cut after %d bytes\n",VPD_MAX_LEN));
36812+ ("keyword too long, cut after %d bytes\n", VPD_MAX_LEN));
36813 }
36814 if ((rtv2 = VpdSetupPara(pAC, key, buf, len, VPD_RW_KEY, OWR_KEY)) != 0) {
36815 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36816@@ -1000,6 +1071,7 @@
36817 return(rtv);
36818 }
36819
36820+
36821 /*
36822 * Read the contents of the VPD EEPROM and copy it to the
36823 * VPD buffer if not already done. Remove the VPD keyword
36824@@ -1023,7 +1095,7 @@
36825
36826 vpd_size = pAC->vpd.vpd_size;
36827
36828- SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_TX,("VPD delete key %s\n",key));
36829+ SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX, ("VPD delete key %s\n", key));
36830 if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) {
36831 if (VpdInit(pAC, IoC) != 0) {
36832 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36833@@ -1060,6 +1132,7 @@
36834 return(0);
36835 }
36836
36837+
36838 /*
36839 * If the VPD buffer contains valid data write the VPD
36840 * read/write area back to the VPD EEPROM.
36841@@ -1089,3 +1162,49 @@
36842 return(0);
36843 }
36844
36845+
36846+/*
36847+ * Read the contents of the VPD EEPROM and copy it to the VPD buffer
36848+ * if not already done. If the keyword "VF" is not present it will be
36849+ * created and the error log message will be stored to this keyword.
36850+ * If "VF" is not present the error log message will be stored to the
36851+ * keyword "VL". "VL" will created or overwritten if "VF" is present.
36852+ * The VPD read/write area is saved to the VPD EEPROM.
36853+ *
36854+ * returns nothing, errors will be ignored.
36855+ */
36856+void VpdErrLog(
36857+SK_AC *pAC, /* common data base */
36858+SK_IOC IoC, /* IO Context */
36859+char *msg) /* error log message */
36860+{
36861+ SK_VPD_PARA *v, vf; /* VF */
36862+ int len;
36863+
36864+ SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX,
36865+ ("VPD error log msg %s\n", msg));
36866+ if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) {
36867+ if (VpdInit(pAC, IoC) != 0) {
36868+ SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
36869+ ("VPD init error\n"));
36870+ return;
36871+ }
36872+ }
36873+
36874+ len = SK_STRLEN(msg);
36875+ if (len > VPD_MAX_LEN) {
36876+ /* cut it */
36877+ len = VPD_MAX_LEN;
36878+ }
36879+ if ((v = vpd_find_para(pAC, VPD_VF, &vf)) != NULL) {
36880+ SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX, ("overwrite VL\n"));
36881+ (void)VpdSetupPara(pAC, VPD_VL, msg, len, VPD_RW_KEY, OWR_KEY);
36882+ }
36883+ else {
36884+ SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX, ("write VF\n"));
36885+ (void)VpdSetupPara(pAC, VPD_VF, msg, len, VPD_RW_KEY, ADD_KEY);
36886+ }
36887+
36888+ (void)VpdUpdate(pAC, IoC);
36889+}
36890+
36891diff -urN linux-2.6.17.orig/drivers/net/sk98lin/skxmac2.c linux-2.6.17/drivers/net/sk98lin/skxmac2.c
36892--- linux-2.6.17.orig/drivers/net/sk98lin/skxmac2.c 2006-06-22 13:17:16.000000000 +0200
36893+++ linux-2.6.17/drivers/net/sk98lin/skxmac2.c 2006-04-27 11:43:44.000000000 +0200
36894@@ -2,23 +2,24 @@
36895 *
36896 * Name: skxmac2.c
36897 * Project: Gigabit Ethernet Adapters, Common Modules
36898- * Version: $Revision$
36899- * Date: $Date$
36900+ * Version: $Revision$
36901+ * Date: $Date$
36902 * Purpose: Contains functions to initialize the MACs and PHYs
36903 *
36904 ******************************************************************************/
36905
36906 /******************************************************************************
36907 *
36908+ * LICENSE:
36909 * (C)Copyright 1998-2002 SysKonnect.
36910- * (C)Copyright 2002-2003 Marvell.
36911+ * (C)Copyright 2002-2006 Marvell.
36912 *
36913 * This program is free software; you can redistribute it and/or modify
36914 * it under the terms of the GNU General Public License as published by
36915 * the Free Software Foundation; either version 2 of the License, or
36916 * (at your option) any later version.
36917- *
36918 * The information in this file is provided "AS IS" without warranty.
36919+ * /LICENSE
36920 *
36921 ******************************************************************************/
36922
36923@@ -29,7 +30,7 @@
36924
36925 /* BCOM PHY magic pattern list */
36926 typedef struct s_PhyHack {
36927- int PhyReg; /* Phy register */
36928+ int PhyReg; /* PHY register */
36929 SK_U16 PhyVal; /* Value to write */
36930 } BCOM_HACK;
36931
36932@@ -37,17 +38,17 @@
36933
36934 #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
36935 static const char SysKonnectFileId[] =
36936- "@(#) $Id$ (C) Marvell.";
36937+ "@(#) $Id$ (C) Marvell.";
36938 #endif
36939
36940 #ifdef GENESIS
36941-static BCOM_HACK BcomRegA1Hack[] = {
36942+BCOM_HACK BcomRegA1Hack[] = {
36943 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
36944 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
36945 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
36946 { 0, 0 }
36947 };
36948-static BCOM_HACK BcomRegC0Hack[] = {
36949+BCOM_HACK BcomRegC0Hack[] = {
36950 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 }, { 0x17, 0x0013 },
36951 { 0x15, 0x0A04 }, { 0x18, 0x0420 },
36952 { 0, 0 }
36953@@ -83,7 +84,7 @@
36954 * Returns:
36955 * nothing
36956 */
36957-void SkXmPhyRead(
36958+int SkXmPhyRead(
36959 SK_AC *pAC, /* Adapter Context */
36960 SK_IOC IoC, /* I/O Context */
36961 int Port, /* Port Index (MAC_1 + n) */
36962@@ -94,13 +95,13 @@
36963 SK_GEPORT *pPrt;
36964
36965 pPrt = &pAC->GIni.GP[Port];
36966-
36967+
36968 /* write the PHY register's address */
36969 XM_OUT16(IoC, Port, XM_PHY_ADDR, PhyReg | pPrt->PhyAddr);
36970-
36971+
36972 /* get the PHY register's value */
36973 XM_IN16(IoC, Port, XM_PHY_DATA, pVal);
36974-
36975+
36976 if (pPrt->PhyType != SK_PHY_XMAC) {
36977 do {
36978 XM_IN16(IoC, Port, XM_MMU_CMD, &Mmu);
36979@@ -110,6 +111,8 @@
36980 /* get the PHY register's value */
36981 XM_IN16(IoC, Port, XM_PHY_DATA, pVal);
36982 }
36983+
36984+ return(0);
36985 } /* SkXmPhyRead */
36986
36987
36988@@ -122,7 +125,7 @@
36989 * Returns:
36990 * nothing
36991 */
36992-void SkXmPhyWrite(
36993+int SkXmPhyWrite(
36994 SK_AC *pAC, /* Adapter Context */
36995 SK_IOC IoC, /* I/O Context */
36996 int Port, /* Port Index (MAC_1 + n) */
36997@@ -133,26 +136,28 @@
36998 SK_GEPORT *pPrt;
36999
37000 pPrt = &pAC->GIni.GP[Port];
37001-
37002+
37003 if (pPrt->PhyType != SK_PHY_XMAC) {
37004 do {
37005 XM_IN16(IoC, Port, XM_MMU_CMD, &Mmu);
37006 /* wait until 'Busy' is cleared */
37007 } while ((Mmu & XM_MMU_PHY_BUSY) != 0);
37008 }
37009-
37010+
37011 /* write the PHY register's address */
37012 XM_OUT16(IoC, Port, XM_PHY_ADDR, PhyReg | pPrt->PhyAddr);
37013-
37014+
37015 /* write the PHY register's value */
37016 XM_OUT16(IoC, Port, XM_PHY_DATA, Val);
37017-
37018+
37019 if (pPrt->PhyType != SK_PHY_XMAC) {
37020 do {
37021 XM_IN16(IoC, Port, XM_MMU_CMD, &Mmu);
37022 /* wait until 'Busy' is cleared */
37023 } while ((Mmu & XM_MMU_PHY_BUSY) != 0);
37024 }
37025+
37026+ return(0);
37027 } /* SkXmPhyWrite */
37028 #endif /* GENESIS */
37029
37030@@ -165,63 +170,97 @@
37031 * Description: reads a 16-bit word from GPHY through MDIO
37032 *
37033 * Returns:
37034- * nothing
37035+ * 0 o.k.
37036+ * 1 error during MDIO read
37037+ * 2 timeout
37038 */
37039-void SkGmPhyRead(
37040+int SkGmPhyRead(
37041 SK_AC *pAC, /* Adapter Context */
37042 SK_IOC IoC, /* I/O Context */
37043 int Port, /* Port Index (MAC_1 + n) */
37044 int PhyReg, /* Register Address (Offset) */
37045 SK_U16 SK_FAR *pVal) /* Pointer to Value */
37046 {
37047+ SK_U16 Word;
37048 SK_U16 Ctrl;
37049 SK_GEPORT *pPrt;
37050-#ifdef VCPU
37051- u_long SimCyle;
37052- u_long SimLowTime;
37053-
37054- VCPUgetTime(&SimCyle, &SimLowTime);
37055- VCPUprintf(0, "SkGmPhyRead(%u), SimCyle=%u, SimLowTime=%u\n",
37056- PhyReg, SimCyle, SimLowTime);
37057-#endif /* VCPU */
37058-
37059+ SK_U32 StartTime;
37060+ SK_U32 CurrTime;
37061+ SK_U32 Delta;
37062+ SK_U32 TimeOut;
37063+ int Rtv;
37064+
37065+ Rtv = 0;
37066+
37067+ *pVal = 0xffff;
37068+
37069 pPrt = &pAC->GIni.GP[Port];
37070-
37071+
37072 /* set PHY-Register offset and 'Read' OpCode (= 1) */
37073- *pVal = (SK_U16)(GM_SMI_CT_PHY_AD(pPrt->PhyAddr) |
37074+ Word = (SK_U16)(GM_SMI_CT_PHY_AD(pPrt->PhyAddr) |
37075 GM_SMI_CT_REG_AD(PhyReg) | GM_SMI_CT_OP_RD);
37076
37077- GM_OUT16(IoC, Port, GM_SMI_CTRL, *pVal);
37078+ GM_OUT16(IoC, Port, GM_SMI_CTRL, Word);
37079
37080- GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);
37081-
37082 /* additional check for MDC/MDIO activity */
37083- if ((Ctrl & GM_SMI_CT_BUSY) == 0) {
37084- *pVal = 0;
37085- return;
37086+ GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);
37087+
37088+ if (Ctrl == 0xffff || (Ctrl & GM_SMI_CT_OP_RD) == 0) {
37089+
37090+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
37091+ ("PHY read impossible on Port %d (Ctrl=0x%04x)\n", Port, Ctrl));
37092+
37093+ return(1);
37094 }
37095
37096- *pVal |= GM_SMI_CT_BUSY;
37097-
37098- do {
37099+ Word |= GM_SMI_CT_BUSY;
37100+
37101+ SK_IN32(IoC, GMAC_TI_ST_VAL, &StartTime);
37102+
37103+ /* set timeout to 10 ms */
37104+ TimeOut = HW_MS_TO_TICKS(pAC, 10);
37105+
37106+ do { /* wait until 'Busy' is cleared and 'ReadValid' is set */
37107 #ifdef VCPU
37108 VCPUwaitTime(1000);
37109 #endif /* VCPU */
37110
37111+ SK_IN32(IoC, GMAC_TI_ST_VAL, &CurrTime);
37112+
37113+ if (CurrTime >= StartTime) {
37114+ Delta = CurrTime - StartTime;
37115+ }
37116+ else {
37117+ Delta = CurrTime + ~StartTime + 1;
37118+ }
37119+
37120+ if (Delta > TimeOut) {
37121+
37122+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
37123+ ("PHY read timeout on Port %d (Ctrl=0x%04x)\n", Port, Ctrl));
37124+ Rtv = 2;
37125+ break;
37126+ }
37127+
37128 GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);
37129
37130- /* wait until 'ReadValid' is set */
37131- } while (Ctrl == *pVal);
37132-
37133- /* get the PHY register's value */
37134+ /* Error on reading SMI Control Register */
37135+ if (Ctrl == 0xffff) {
37136+ return(1);
37137+ }
37138+
37139+ } while ((Ctrl ^ Word) != (GM_SMI_CT_RD_VAL | GM_SMI_CT_BUSY));
37140+
37141 GM_IN16(IoC, Port, GM_SMI_DATA, pVal);
37142
37143-#ifdef VCPU
37144- VCPUgetTime(&SimCyle, &SimLowTime);
37145- VCPUprintf(0, "VCPUgetTime(), SimCyle=%u, SimLowTime=%u\n",
37146- SimCyle, SimLowTime);
37147-#endif /* VCPU */
37148+ /* dummy read after GM_IN16() */
37149+ SK_IN32(IoC, GMAC_TI_ST_VAL, &CurrTime);
37150
37151+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
37152+ ("SkGmPhyRead Port:%d, Reg=%d, Val = 0x%04X\n",
37153+ Port, PhyReg, *pVal));
37154+
37155+ return(Rtv);
37156 } /* SkGmPhyRead */
37157
37158
37159@@ -232,9 +271,11 @@
37160 * Description: writes a 16-bit word to GPHY through MDIO
37161 *
37162 * Returns:
37163- * nothing
37164+ * 0 o.k.
37165+ * 1 error during MDIO read
37166+ * 2 timeout
37167 */
37168-void SkGmPhyWrite(
37169+int SkGmPhyWrite(
37170 SK_AC *pAC, /* Adapter Context */
37171 SK_IOC IoC, /* I/O Context */
37172 int Port, /* Port Index (MAC_1 + n) */
37173@@ -243,54 +284,78 @@
37174 {
37175 SK_U16 Ctrl;
37176 SK_GEPORT *pPrt;
37177-#ifdef VCPU
37178- SK_U32 DWord;
37179- u_long SimCyle;
37180- u_long SimLowTime;
37181-
37182- VCPUgetTime(&SimCyle, &SimLowTime);
37183- VCPUprintf(0, "SkGmPhyWrite(Reg=%u, Val=0x%04x), SimCyle=%u, SimLowTime=%u\n",
37184- PhyReg, Val, SimCyle, SimLowTime);
37185-#endif /* VCPU */
37186-
37187+ SK_U32 StartTime;
37188+ SK_U32 CurrTime;
37189+ SK_U32 Delta;
37190+ SK_U32 TimeOut;
37191+
37192+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
37193+ ("SkGmPhyWrite Port:%d, Reg=%d, Val = 0x%04X\n",
37194+ Port, PhyReg, Val));
37195+
37196 pPrt = &pAC->GIni.GP[Port];
37197-
37198+
37199 /* write the PHY register's value */
37200 GM_OUT16(IoC, Port, GM_SMI_DATA, Val);
37201-
37202- /* set PHY-Register offset and 'Write' OpCode (= 0) */
37203- Val = GM_SMI_CT_PHY_AD(pPrt->PhyAddr) | GM_SMI_CT_REG_AD(PhyReg);
37204
37205- GM_OUT16(IoC, Port, GM_SMI_CTRL, Val);
37206-
37207- GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);
37208-
37209+#ifdef DEBUG
37210 /* additional check for MDC/MDIO activity */
37211- if ((Ctrl & GM_SMI_CT_BUSY) == 0) {
37212- return;
37213+ GM_IN16(IoC, Port, GM_SMI_DATA, &Ctrl);
37214+
37215+ if (Ctrl != Val) {
37216+
37217+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
37218+ ("PHY write impossible on Port %d (Val=0x%04x)\n", Port, Ctrl));
37219+
37220+ return(1);
37221 }
37222-
37223- Val |= GM_SMI_CT_BUSY;
37224+#endif /* DEBUG */
37225
37226- do {
37227-#ifdef VCPU
37228- /* read Timer value */
37229- SK_IN32(IoC, B2_TI_VAL, &DWord);
37230+ /* set PHY-Register offset and 'Write' OpCode (= 0) */
37231+ Ctrl = (SK_U16)(GM_SMI_CT_PHY_AD(pPrt->PhyAddr) |
37232+ GM_SMI_CT_REG_AD(PhyReg));
37233
37234+ GM_OUT16(IoC, Port, GM_SMI_CTRL, Ctrl);
37235+
37236+ SK_IN32(IoC, GMAC_TI_ST_VAL, &StartTime);
37237+
37238+ /* set timeout to 10 ms */
37239+ TimeOut = HW_MS_TO_TICKS(pAC, 10);
37240+
37241+ do { /* wait until 'Busy' is cleared */
37242+#ifdef VCPU
37243 VCPUwaitTime(1000);
37244 #endif /* VCPU */
37245
37246+ SK_IN32(IoC, GMAC_TI_ST_VAL, &CurrTime);
37247+
37248+ if (CurrTime >= StartTime) {
37249+ Delta = CurrTime - StartTime;
37250+ }
37251+ else {
37252+ Delta = CurrTime + ~StartTime + 1;
37253+ }
37254+
37255+ if (Delta > TimeOut) {
37256+
37257+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
37258+ ("PHY write timeout on Port %d (Ctrl=0x%04x)\n", Port, Ctrl));
37259+ return(2);
37260+ }
37261+
37262 GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);
37263
37264- /* wait until 'Busy' is cleared */
37265- } while (Ctrl == Val);
37266-
37267-#ifdef VCPU
37268- VCPUgetTime(&SimCyle, &SimLowTime);
37269- VCPUprintf(0, "VCPUgetTime(), SimCyle=%u, SimLowTime=%u\n",
37270- SimCyle, SimLowTime);
37271-#endif /* VCPU */
37272+ /* Error on reading SMI Control Register */
37273+ if (Ctrl == 0xffff) {
37274+ return(1);
37275+ }
37276
37277+ } while ((Ctrl & GM_SMI_CT_BUSY) != 0);
37278+
37279+ /* dummy read after GM_IN16() */
37280+ SK_IN32(IoC, GMAC_TI_ST_VAL, &CurrTime);
37281+
37282+ return(0);
37283 } /* SkGmPhyWrite */
37284 #endif /* YUKON */
37285
37286@@ -312,16 +377,8 @@
37287 int PhyReg, /* Register Address (Offset) */
37288 SK_U16 *pVal) /* Pointer to Value */
37289 {
37290- void (*r_func)(SK_AC *pAC, SK_IOC IoC, int Port, int Reg, SK_U16 *pVal);
37291
37292- if (pAC->GIni.GIGenesis) {
37293- r_func = SkXmPhyRead;
37294- }
37295- else {
37296- r_func = SkGmPhyRead;
37297- }
37298-
37299- r_func(pAC, IoC, Port, PhyReg, pVal);
37300+ pAC->GIni.GIFunc.pFnMacPhyRead(pAC, IoC, Port, PhyReg, pVal);
37301 } /* SkGePhyRead */
37302
37303
37304@@ -341,16 +398,8 @@
37305 int PhyReg, /* Register Address (Offset) */
37306 SK_U16 Val) /* Value */
37307 {
37308- void (*w_func)(SK_AC *pAC, SK_IOC IoC, int Port, int Reg, SK_U16 Val);
37309
37310- if (pAC->GIni.GIGenesis) {
37311- w_func = SkXmPhyWrite;
37312- }
37313- else {
37314- w_func = SkGmPhyWrite;
37315- }
37316-
37317- w_func(pAC, IoC, Port, PhyReg, Val);
37318+ pAC->GIni.GIFunc.pFnMacPhyWrite(pAC, IoC, Port, PhyReg, Val);
37319 } /* SkGePhyWrite */
37320 #endif /* SK_DIAG */
37321
37322@@ -360,15 +409,15 @@
37323 * SkMacPromiscMode() - Enable / Disable Promiscuous Mode
37324 *
37325 * Description:
37326- * enables / disables promiscuous mode by setting Mode Register (XMAC) or
37327- * Receive Control Register (GMAC) dep. on board type
37328+ * enables / disables promiscuous mode by setting Mode Register (XMAC) or
37329+ * Receive Control Register (GMAC) dep. on board type
37330 *
37331 * Returns:
37332 * nothing
37333 */
37334 void SkMacPromiscMode(
37335-SK_AC *pAC, /* adapter context */
37336-SK_IOC IoC, /* IO context */
37337+SK_AC *pAC, /* Adapter Context */
37338+SK_IOC IoC, /* I/O Context */
37339 int Port, /* Port Index (MAC_1 + n) */
37340 SK_BOOL Enable) /* Enable / Disable */
37341 {
37342@@ -377,11 +426,11 @@
37343 #endif
37344 #ifdef GENESIS
37345 SK_U32 MdReg;
37346-#endif
37347+#endif
37348
37349 #ifdef GENESIS
37350 if (pAC->GIni.GIGenesis) {
37351-
37352+
37353 XM_IN32(IoC, Port, XM_MODE, &MdReg);
37354 /* enable or disable promiscuous mode */
37355 if (Enable) {
37356@@ -394,12 +443,12 @@
37357 XM_OUT32(IoC, Port, XM_MODE, MdReg);
37358 }
37359 #endif /* GENESIS */
37360-
37361+
37362 #ifdef YUKON
37363 if (pAC->GIni.GIYukon) {
37364-
37365+
37366 GM_IN16(IoC, Port, GM_RX_CTRL, &RcReg);
37367-
37368+
37369 /* enable or disable unicast and multicast filtering */
37370 if (Enable) {
37371 RcReg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
37372@@ -420,28 +469,28 @@
37373 * SkMacHashing() - Enable / Disable Hashing
37374 *
37375 * Description:
37376- * enables / disables hashing by setting Mode Register (XMAC) or
37377- * Receive Control Register (GMAC) dep. on board type
37378+ * enables / disables hashing by setting Mode Register (XMAC) or
37379+ * Receive Control Register (GMAC) dep. on board type
37380 *
37381 * Returns:
37382 * nothing
37383 */
37384 void SkMacHashing(
37385-SK_AC *pAC, /* adapter context */
37386-SK_IOC IoC, /* IO context */
37387+SK_AC *pAC, /* Adapter Context */
37388+SK_IOC IoC, /* I/O Context */
37389 int Port, /* Port Index (MAC_1 + n) */
37390 SK_BOOL Enable) /* Enable / Disable */
37391 {
37392 #ifdef YUKON
37393 SK_U16 RcReg;
37394-#endif
37395+#endif
37396 #ifdef GENESIS
37397 SK_U32 MdReg;
37398 #endif
37399
37400 #ifdef GENESIS
37401 if (pAC->GIni.GIGenesis) {
37402-
37403+
37404 XM_IN32(IoC, Port, XM_MODE, &MdReg);
37405 /* enable or disable hashing */
37406 if (Enable) {
37407@@ -454,12 +503,12 @@
37408 XM_OUT32(IoC, Port, XM_MODE, MdReg);
37409 }
37410 #endif /* GENESIS */
37411-
37412+
37413 #ifdef YUKON
37414 if (pAC->GIni.GIYukon) {
37415-
37416+
37417 GM_IN16(IoC, Port, GM_RX_CTRL, &RcReg);
37418-
37419+
37420 /* enable or disable multicast filtering */
37421 if (Enable) {
37422 RcReg |= GM_RXCR_MCF_ENA;
37423@@ -487,8 +536,8 @@
37424 * - don't set XMR_FS_ERR in status SK_LENERR_OK_ON/OFF
37425 * for inrange length error frames
37426 * - don't set XMR_FS_ERR in status SK_BIG_PK_OK_ON/OFF
37427- * for frames > 1514 bytes
37428- * - enable Rx of own packets SK_SELF_RX_ON/OFF
37429+ * for frames > 1514 bytes
37430+ * - enable Rx of own packets SK_SELF_RX_ON/OFF
37431 *
37432 * for incoming packets may be enabled/disabled by this function.
37433 * Additional modes may be added later.
37434@@ -499,11 +548,11 @@
37435 * nothing
37436 */
37437 static void SkXmSetRxCmd(
37438-SK_AC *pAC, /* adapter context */
37439-SK_IOC IoC, /* IO context */
37440+SK_AC *pAC, /* Adapter Context */
37441+SK_IOC IoC, /* I/O Context */
37442 int Port, /* Port Index (MAC_1 + n) */
37443 int Mode) /* Mode is SK_STRIP_FCS_ON/OFF, SK_STRIP_PAD_ON/OFF,
37444- SK_LENERR_OK_ON/OFF, or SK_BIG_PK_OK_ON/OFF */
37445+ SK_LENERR_OK_ON/OFF, or SK_BIG_PK_OK_ON/OFF */
37446 {
37447 SK_U16 OldRxCmd;
37448 SK_U16 RxCmd;
37449@@ -511,7 +560,7 @@
37450 XM_IN16(IoC, Port, XM_RX_CMD, &OldRxCmd);
37451
37452 RxCmd = OldRxCmd;
37453-
37454+
37455 switch (Mode & (SK_STRIP_FCS_ON | SK_STRIP_FCS_OFF)) {
37456 case SK_STRIP_FCS_ON:
37457 RxCmd |= XM_RX_STRIP_FCS;
37458@@ -572,8 +621,8 @@
37459 * The features
37460 * - FCS (CRC) stripping, SK_STRIP_FCS_ON/OFF
37461 * - don't set GMR_FS_LONG_ERR SK_BIG_PK_OK_ON/OFF
37462- * for frames > 1514 bytes
37463- * - enable Rx of own packets SK_SELF_RX_ON/OFF
37464+ * for frames > 1514 bytes
37465+ * - enable Rx of own packets SK_SELF_RX_ON/OFF
37466 *
37467 * for incoming packets may be enabled/disabled by this function.
37468 * Additional modes may be added later.
37469@@ -584,20 +633,17 @@
37470 * nothing
37471 */
37472 static void SkGmSetRxCmd(
37473-SK_AC *pAC, /* adapter context */
37474-SK_IOC IoC, /* IO context */
37475+SK_AC *pAC, /* Adapter Context */
37476+SK_IOC IoC, /* I/O Context */
37477 int Port, /* Port Index (MAC_1 + n) */
37478 int Mode) /* Mode is SK_STRIP_FCS_ON/OFF, SK_STRIP_PAD_ON/OFF,
37479- SK_LENERR_OK_ON/OFF, or SK_BIG_PK_OK_ON/OFF */
37480+ SK_LENERR_OK_ON/OFF, or SK_BIG_PK_OK_ON/OFF */
37481 {
37482- SK_U16 OldRxCmd;
37483 SK_U16 RxCmd;
37484
37485 if ((Mode & (SK_STRIP_FCS_ON | SK_STRIP_FCS_OFF)) != 0) {
37486-
37487- GM_IN16(IoC, Port, GM_RX_CTRL, &OldRxCmd);
37488
37489- RxCmd = OldRxCmd;
37490+ GM_IN16(IoC, Port, GM_RX_CTRL, &RxCmd);
37491
37492 if ((Mode & SK_STRIP_FCS_ON) != 0) {
37493 RxCmd |= GM_RXCR_CRC_DIS;
37494@@ -605,17 +651,13 @@
37495 else {
37496 RxCmd &= ~GM_RXCR_CRC_DIS;
37497 }
37498- /* Write the new mode to the Rx control register if required */
37499- if (OldRxCmd != RxCmd) {
37500- GM_OUT16(IoC, Port, GM_RX_CTRL, RxCmd);
37501- }
37502+ /* Write the new mode to the Rx Control register */
37503+ GM_OUT16(IoC, Port, GM_RX_CTRL, RxCmd);
37504 }
37505
37506 if ((Mode & (SK_BIG_PK_OK_ON | SK_BIG_PK_OK_OFF)) != 0) {
37507-
37508- GM_IN16(IoC, Port, GM_SERIAL_MODE, &OldRxCmd);
37509
37510- RxCmd = OldRxCmd;
37511+ GM_IN16(IoC, Port, GM_SERIAL_MODE, &RxCmd);
37512
37513 if ((Mode & SK_BIG_PK_OK_ON) != 0) {
37514 RxCmd |= GM_SMOD_JUMBO_ENA;
37515@@ -623,10 +665,8 @@
37516 else {
37517 RxCmd &= ~GM_SMOD_JUMBO_ENA;
37518 }
37519- /* Write the new mode to the Rx control register if required */
37520- if (OldRxCmd != RxCmd) {
37521- GM_OUT16(IoC, Port, GM_SERIAL_MODE, RxCmd);
37522- }
37523+ /* Write the new mode to the Serial Mode register */
37524+ GM_OUT16(IoC, Port, GM_SERIAL_MODE, RxCmd);
37525 }
37526 } /* SkGmSetRxCmd */
37527
37528@@ -641,17 +681,17 @@
37529 * nothing
37530 */
37531 void SkMacSetRxCmd(
37532-SK_AC *pAC, /* adapter context */
37533-SK_IOC IoC, /* IO context */
37534+SK_AC *pAC, /* Adapter Context */
37535+SK_IOC IoC, /* I/O Context */
37536 int Port, /* Port Index (MAC_1 + n) */
37537 int Mode) /* Rx Mode */
37538 {
37539 if (pAC->GIni.GIGenesis) {
37540-
37541+
37542 SkXmSetRxCmd(pAC, IoC, Port, Mode);
37543 }
37544 else {
37545-
37546+
37547 SkGmSetRxCmd(pAC, IoC, Port, Mode);
37548 }
37549
37550@@ -668,15 +708,15 @@
37551 * nothing
37552 */
37553 void SkMacCrcGener(
37554-SK_AC *pAC, /* adapter context */
37555-SK_IOC IoC, /* IO context */
37556+SK_AC *pAC, /* Adapter Context */
37557+SK_IOC IoC, /* I/O Context */
37558 int Port, /* Port Index (MAC_1 + n) */
37559 SK_BOOL Enable) /* Enable / Disable */
37560 {
37561 SK_U16 Word;
37562
37563 if (pAC->GIni.GIGenesis) {
37564-
37565+
37566 XM_IN16(IoC, Port, XM_TX_CMD, &Word);
37567
37568 if (Enable) {
37569@@ -689,9 +729,9 @@
37570 XM_OUT16(IoC, Port, XM_TX_CMD, Word);
37571 }
37572 else {
37573-
37574+
37575 GM_IN16(IoC, Port, GM_TX_CTRL, &Word);
37576-
37577+
37578 if (Enable) {
37579 Word &= ~GM_TXCR_CRC_DIS;
37580 }
37581@@ -721,14 +761,14 @@
37582 * nothing
37583 */
37584 void SkXmClrExactAddr(
37585-SK_AC *pAC, /* adapter context */
37586-SK_IOC IoC, /* IO context */
37587+SK_AC *pAC, /* Adapter Context */
37588+SK_IOC IoC, /* I/O Context */
37589 int Port, /* Port Index (MAC_1 + n) */
37590 int StartNum, /* Begin with this Address Register Index (0..15) */
37591 int StopNum) /* Stop after finished with this Register Idx (0..15) */
37592 {
37593 int i;
37594- SK_U16 ZeroAddr[3] = {0x0000, 0x0000, 0x0000};
37595+ SK_U16 ZeroAddr[3] = {0, 0, 0};
37596
37597 if ((unsigned)StartNum > 15 || (unsigned)StopNum > 15 ||
37598 StartNum > StopNum) {
37599@@ -738,7 +778,7 @@
37600 }
37601
37602 for (i = StartNum; i <= StopNum; i++) {
37603- XM_OUTADDR(IoC, Port, XM_EXM(i), &ZeroAddr[0]);
37604+ XM_OUTADDR(IoC, Port, XM_EXM(i), ZeroAddr);
37605 }
37606 } /* SkXmClrExactAddr */
37607 #endif /* GENESIS */
37608@@ -755,21 +795,21 @@
37609 * nothing
37610 */
37611 void SkMacFlushTxFifo(
37612-SK_AC *pAC, /* adapter context */
37613-SK_IOC IoC, /* IO context */
37614+SK_AC *pAC, /* Adapter Context */
37615+SK_IOC IoC, /* I/O Context */
37616 int Port) /* Port Index (MAC_1 + n) */
37617 {
37618 #ifdef GENESIS
37619 SK_U32 MdReg;
37620
37621 if (pAC->GIni.GIGenesis) {
37622-
37623+
37624 XM_IN32(IoC, Port, XM_MODE, &MdReg);
37625
37626 XM_OUT32(IoC, Port, XM_MODE, MdReg | XM_MD_FTF);
37627 }
37628 #endif /* GENESIS */
37629-
37630+
37631 #ifdef YUKON
37632 if (pAC->GIni.GIYukon) {
37633 /* no way to flush the FIFO we have to issue a reset */
37634@@ -790,9 +830,9 @@
37635 * Returns:
37636 * nothing
37637 */
37638-static void SkMacFlushRxFifo(
37639-SK_AC *pAC, /* adapter context */
37640-SK_IOC IoC, /* IO context */
37641+void SkMacFlushRxFifo(
37642+SK_AC *pAC, /* Adapter Context */
37643+SK_IOC IoC, /* I/O Context */
37644 int Port) /* Port Index (MAC_1 + n) */
37645 {
37646 #ifdef GENESIS
37647@@ -805,7 +845,7 @@
37648 XM_OUT32(IoC, Port, XM_MODE, MdReg | XM_MD_FRF);
37649 }
37650 #endif /* GENESIS */
37651-
37652+
37653 #ifdef YUKON
37654 if (pAC->GIni.GIYukon) {
37655 /* no way to flush the FIFO we have to issue a reset */
37656@@ -853,23 +893,23 @@
37657 * nothing
37658 */
37659 static void SkXmSoftRst(
37660-SK_AC *pAC, /* adapter context */
37661-SK_IOC IoC, /* IO context */
37662+SK_AC *pAC, /* Adapter Context */
37663+SK_IOC IoC, /* I/O Context */
37664 int Port) /* Port Index (MAC_1 + n) */
37665 {
37666- SK_U16 ZeroAddr[4] = {0x0000, 0x0000, 0x0000, 0x0000};
37667-
37668+ SK_U16 ZeroAddr[4] = {0, 0, 0, 0};
37669+
37670 /* reset the statistics module */
37671 XM_OUT32(IoC, Port, XM_GP_PORT, XM_GP_RES_STAT);
37672
37673 /* disable all XMAC IRQs */
37674 XM_OUT16(IoC, Port, XM_IMSK, 0xffff);
37675-
37676+
37677 XM_OUT32(IoC, Port, XM_MODE, 0); /* clear Mode Reg */
37678-
37679+
37680 XM_OUT16(IoC, Port, XM_TX_CMD, 0); /* reset TX CMD Reg */
37681 XM_OUT16(IoC, Port, XM_RX_CMD, 0); /* reset RX CMD Reg */
37682-
37683+
37684 /* disable all PHY IRQs */
37685 switch (pAC->GIni.GP[Port].PhyType) {
37686 case SK_PHY_BCOM:
37687@@ -887,13 +927,13 @@
37688 }
37689
37690 /* clear the Hash Register */
37691- XM_OUTHASH(IoC, Port, XM_HSM, &ZeroAddr);
37692+ XM_OUTHASH(IoC, Port, XM_HSM, ZeroAddr);
37693
37694 /* clear the Exact Match Address registers */
37695 SkXmClrExactAddr(pAC, IoC, Port, 0, 15);
37696-
37697+
37698 /* clear the Source Check Address registers */
37699- XM_OUTHASH(IoC, Port, XM_SRC_CHK, &ZeroAddr);
37700+ XM_OUTHASH(IoC, Port, XM_SRC_CHK, ZeroAddr);
37701
37702 } /* SkXmSoftRst */
37703
37704@@ -916,8 +956,8 @@
37705 * nothing
37706 */
37707 static void SkXmHardRst(
37708-SK_AC *pAC, /* adapter context */
37709-SK_IOC IoC, /* IO context */
37710+SK_AC *pAC, /* Adapter Context */
37711+SK_IOC IoC, /* I/O Context */
37712 int Port) /* Port Index (MAC_1 + n) */
37713 {
37714 SK_U32 Reg;
37715@@ -940,19 +980,19 @@
37716 }
37717
37718 SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
37719-
37720+
37721 SK_IN16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), &Word);
37722-
37723+
37724 } while ((Word & MFF_SET_MAC_RST) == 0);
37725 }
37726
37727 /* For external PHYs there must be special handling */
37728 if (pAC->GIni.GP[Port].PhyType != SK_PHY_XMAC) {
37729-
37730+
37731 SK_IN32(IoC, B2_GP_IO, &Reg);
37732-
37733+
37734 if (Port == 0) {
37735- Reg |= GP_DIR_0; /* set to output */
37736+ Reg |= GP_DIR_0; /* set to output */
37737 Reg &= ~GP_IO_0; /* set PHY reset (active low) */
37738 }
37739 else {
37740@@ -978,12 +1018,12 @@
37741 * nothing
37742 */
37743 static void SkXmClearRst(
37744-SK_AC *pAC, /* adapter context */
37745-SK_IOC IoC, /* IO context */
37746+SK_AC *pAC, /* Adapter Context */
37747+SK_IOC IoC, /* I/O Context */
37748 int Port) /* Port Index (MAC_1 + n) */
37749 {
37750 SK_U32 DWord;
37751-
37752+
37753 /* clear HW reset */
37754 SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
37755
37756@@ -1000,7 +1040,7 @@
37757 /* Clear PHY reset */
37758 SK_OUT32(IoC, B2_GP_IO, DWord);
37759
37760- /* Enable GMII interface */
37761+ /* enable GMII interface */
37762 XM_OUT16(IoC, Port, XM_HW_CFG, XM_HW_GMII_MD);
37763 }
37764 } /* SkXmClearRst */
37765@@ -1020,29 +1060,28 @@
37766 * nothing
37767 */
37768 static void SkGmSoftRst(
37769-SK_AC *pAC, /* adapter context */
37770-SK_IOC IoC, /* IO context */
37771+SK_AC *pAC, /* Adapter Context */
37772+SK_IOC IoC, /* I/O Context */
37773 int Port) /* Port Index (MAC_1 + n) */
37774 {
37775- SK_U16 EmptyHash[4] = {0x0000, 0x0000, 0x0000, 0x0000};
37776- SK_U16 RxCtrl;
37777+ SK_U16 EmptyHash[4] = { 0x0000, 0x0000, 0x0000, 0x0000 };
37778+ SK_U16 RxCtrl;
37779
37780 /* reset the statistics module */
37781
37782 /* disable all GMAC IRQs */
37783- SK_OUT8(IoC, GMAC_IRQ_MSK, 0);
37784-
37785+ SK_OUT8(IoC, MR_ADDR(Port, GMAC_IRQ_MSK), 0);
37786+
37787 /* disable all PHY IRQs */
37788 SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, 0);
37789-
37790+
37791 /* clear the Hash Register */
37792 GM_OUTHASH(IoC, Port, GM_MC_ADDR_H1, EmptyHash);
37793
37794- /* Enable Unicast and Multicast filtering */
37795+ /* enable Unicast and Multicast filtering */
37796 GM_IN16(IoC, Port, GM_RX_CTRL, &RxCtrl);
37797-
37798- GM_OUT16(IoC, Port, GM_RX_CTRL,
37799- (SK_U16)(RxCtrl | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA));
37800+
37801+ GM_OUT16(IoC, Port, GM_RX_CTRL, RxCtrl | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
37802
37803 } /* SkGmSoftRst */
37804
37805@@ -1057,16 +1096,16 @@
37806 * nothing
37807 */
37808 static void SkGmHardRst(
37809-SK_AC *pAC, /* adapter context */
37810-SK_IOC IoC, /* IO context */
37811+SK_AC *pAC, /* Adapter Context */
37812+SK_IOC IoC, /* I/O Context */
37813 int Port) /* Port Index (MAC_1 + n) */
37814 {
37815 SK_U32 DWord;
37816-
37817+
37818 /* WA code for COMA mode */
37819 if (pAC->GIni.GIYukonLite &&
37820 pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3) {
37821-
37822+
37823 SK_IN32(IoC, B2_GP_IO, &DWord);
37824
37825 DWord |= (GP_DIR_9 | GP_IO_9);
37826@@ -1076,10 +1115,10 @@
37827 }
37828
37829 /* set GPHY Control reset */
37830- SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), GPC_RST_SET);
37831+ SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_SET);
37832
37833 /* set GMAC Control reset */
37834- SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_RST_SET);
37835+ SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_SET);
37836
37837 } /* SkGmHardRst */
37838
37839@@ -1094,24 +1133,24 @@
37840 * nothing
37841 */
37842 static void SkGmClearRst(
37843-SK_AC *pAC, /* adapter context */
37844-SK_IOC IoC, /* IO context */
37845+SK_AC *pAC, /* Adapter Context */
37846+SK_IOC IoC, /* I/O Context */
37847 int Port) /* Port Index (MAC_1 + n) */
37848 {
37849 SK_U32 DWord;
37850-
37851-#ifdef XXX
37852- /* clear GMAC Control reset */
37853- SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_RST_CLR);
37854+#ifdef SK_DIAG
37855+ SK_U16 PhyId0;
37856+ SK_U16 PhyId1;
37857+#endif /* SK_DIAG */
37858
37859- /* set GMAC Control reset */
37860- SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_RST_SET);
37861-#endif /* XXX */
37862+#if defined(SK_DIAG) || defined(DEBUG)
37863+ SK_U16 Word;
37864+#endif /* SK_DIAG || DEBUG */
37865
37866 /* WA code for COMA mode */
37867 if (pAC->GIni.GIYukonLite &&
37868 pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3) {
37869-
37870+
37871 SK_IN32(IoC, B2_GP_IO, &DWord);
37872
37873 DWord |= GP_DIR_9; /* set to output */
37874@@ -1121,30 +1160,87 @@
37875 SK_OUT32(IoC, B2_GP_IO, DWord);
37876 }
37877
37878- /* set HWCFG_MODE */
37879- DWord = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
37880- GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE |
37881- (pAC->GIni.GICopperType ? GPC_HWCFG_GMII_COP :
37882- GPC_HWCFG_GMII_FIB);
37883+#ifdef VCPU
37884+ /* set MAC Reset before PHY reset is set */
37885+ SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_SET);
37886+#endif /* VCPU */
37887
37888- /* set GPHY Control reset */
37889- SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), DWord | GPC_RST_SET);
37890+ if (CHIP_ID_YUKON_2(pAC)) {
37891+ /* set GPHY Control reset */
37892+ SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_SET);
37893
37894- /* release GPHY Control reset */
37895- SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), DWord | GPC_RST_CLR);
37896+ /* release GPHY Control reset */
37897+ SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_CLR);
37898+
37899+#ifdef DEBUG
37900+ /* additional check for PEX */
37901+ SK_IN16(IoC, GPHY_CTRL, &Word);
37902+
37903+ if (pAC->GIni.GIPciBus == SK_PEX_BUS && Word != GPC_RST_CLR) {
37904+
37905+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
37906+ ("Error on PEX-bus after GPHY reset\n"));
37907+ }
37908+#endif /* DEBUG */
37909+ }
37910+ else {
37911+ /* set HWCFG_MODE */
37912+ DWord = GPC_INT_POL | GPC_DIS_FC | GPC_DIS_SLEEP |
37913+ GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE |
37914+ (pAC->GIni.GICopperType ? GPC_HWCFG_GMII_COP :
37915+ GPC_HWCFG_GMII_FIB);
37916+
37917+ /* set GPHY Control reset */
37918+ SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), DWord | GPC_RST_SET);
37919+
37920+ /* release GPHY Control reset */
37921+ SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), DWord | GPC_RST_CLR);
37922+ }
37923
37924 #ifdef VCPU
37925+ /* wait for internal initialization of GPHY */
37926+ VCPUprintf(0, "Waiting until PHY %d is ready to initialize\n", Port);
37927+ VCpuWait(10000);
37928+
37929+ /* release GMAC reset */
37930+ SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_CLR);
37931+
37932+ /* wait for stable GMAC clock */
37933 VCpuWait(9000);
37934 #endif /* VCPU */
37935
37936 /* clear GMAC Control reset */
37937- SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
37938+ SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_CLR);
37939+
37940+#ifdef SK_DIAG
37941+ if (HW_FEATURE(pAC, HWF_WA_DEV_472) && Port == MAC_2) {
37942+
37943+ /* clear GMAC 1 Control reset */
37944+ SK_OUT8(IoC, MR_ADDR(MAC_1, GMAC_CTRL), (SK_U8)GMC_RST_CLR);
37945+
37946+ do {
37947+ /* set GMAC 2 Control reset */
37948+ SK_OUT8(IoC, MR_ADDR(MAC_2, GMAC_CTRL), (SK_U8)GMC_RST_SET);
37949+
37950+ /* clear GMAC 2 Control reset */
37951+ SK_OUT8(IoC, MR_ADDR(MAC_2, GMAC_CTRL), (SK_U8)GMC_RST_CLR);
37952+
37953+ SkGmPhyRead(pAC, IoC, MAC_2, PHY_MARV_ID0, &PhyId0);
37954+
37955+ SkGmPhyRead(pAC, IoC, MAC_2, PHY_MARV_ID1, &PhyId1);
37956+
37957+ SkGmPhyRead(pAC, IoC, MAC_2, PHY_MARV_INT_MASK, &Word);
37958+
37959+ } while (Word != 0 || PhyId0 != PHY_MARV_ID0_VAL ||
37960+ PhyId1 != PHY_MARV_ID1_Y2);
37961+ }
37962+#endif /* SK_DIAG */
37963
37964 #ifdef VCPU
37965 VCpuWait(2000);
37966-
37967+
37968 SK_IN32(IoC, MR_ADDR(Port, GPHY_CTRL), &DWord);
37969-
37970+
37971 SK_IN32(IoC, B0_ISRC, &DWord);
37972 #endif /* VCPU */
37973
37974@@ -1162,37 +1258,33 @@
37975 * nothing
37976 */
37977 void SkMacSoftRst(
37978-SK_AC *pAC, /* adapter context */
37979-SK_IOC IoC, /* IO context */
37980+SK_AC *pAC, /* Adapter Context */
37981+SK_IOC IoC, /* I/O Context */
37982 int Port) /* Port Index (MAC_1 + n) */
37983 {
37984- SK_GEPORT *pPrt;
37985-
37986- pPrt = &pAC->GIni.GP[Port];
37987-
37988 /* disable receiver and transmitter */
37989 SkMacRxTxDisable(pAC, IoC, Port);
37990
37991 #ifdef GENESIS
37992 if (pAC->GIni.GIGenesis) {
37993-
37994+
37995 SkXmSoftRst(pAC, IoC, Port);
37996 }
37997 #endif /* GENESIS */
37998-
37999+
38000 #ifdef YUKON
38001 if (pAC->GIni.GIYukon) {
38002-
38003+
38004 SkGmSoftRst(pAC, IoC, Port);
38005 }
38006 #endif /* YUKON */
38007
38008 /* flush the MAC's Rx and Tx FIFOs */
38009 SkMacFlushTxFifo(pAC, IoC, Port);
38010-
38011+
38012 SkMacFlushRxFifo(pAC, IoC, Port);
38013
38014- pPrt->PState = SK_PRT_STOP;
38015+ pAC->GIni.GP[Port].PState = SK_PRT_STOP;
38016
38017 } /* SkMacSoftRst */
38018
38019@@ -1207,29 +1299,63 @@
38020 * nothing
38021 */
38022 void SkMacHardRst(
38023-SK_AC *pAC, /* adapter context */
38024-SK_IOC IoC, /* IO context */
38025+SK_AC *pAC, /* Adapter Context */
38026+SK_IOC IoC, /* I/O Context */
38027 int Port) /* Port Index (MAC_1 + n) */
38028 {
38029-
38030+
38031 #ifdef GENESIS
38032 if (pAC->GIni.GIGenesis) {
38033-
38034+
38035 SkXmHardRst(pAC, IoC, Port);
38036 }
38037 #endif /* GENESIS */
38038-
38039+
38040 #ifdef YUKON
38041 if (pAC->GIni.GIYukon) {
38042-
38043+
38044 SkGmHardRst(pAC, IoC, Port);
38045 }
38046 #endif /* YUKON */
38047
38048+ pAC->GIni.GP[Port].PHWLinkUp = SK_FALSE;
38049+
38050 pAC->GIni.GP[Port].PState = SK_PRT_RESET;
38051
38052 } /* SkMacHardRst */
38053
38054+#ifndef SK_SLIM
38055+/******************************************************************************
38056+ *
38057+ * SkMacClearRst() - Clear the MAC reset
38058+ *
38059+ * Description: calls a clear MAC reset routine dep. on board type
38060+ *
38061+ * Returns:
38062+ * nothing
38063+ */
38064+void SkMacClearRst(
38065+SK_AC *pAC, /* Adapter Context */
38066+SK_IOC IoC, /* I/O Context */
38067+int Port) /* Port Index (MAC_1 + n) */
38068+{
38069+
38070+#ifdef GENESIS
38071+ if (pAC->GIni.GIGenesis) {
38072+
38073+ SkXmClearRst(pAC, IoC, Port);
38074+ }
38075+#endif /* GENESIS */
38076+
38077+#ifdef YUKON
38078+ if (pAC->GIni.GIYukon) {
38079+
38080+ SkGmClearRst(pAC, IoC, Port);
38081+ }
38082+#endif /* YUKON */
38083+
38084+} /* SkMacClearRst */
38085+#endif /* !SK_SLIM */
38086
38087 #ifdef GENESIS
38088 /******************************************************************************
38089@@ -1247,8 +1373,8 @@
38090 * nothing
38091 */
38092 void SkXmInitMac(
38093-SK_AC *pAC, /* adapter context */
38094-SK_IOC IoC, /* IO context */
38095+SK_AC *pAC, /* Adapter Context */
38096+SK_IOC IoC, /* I/O Context */
38097 int Port) /* Port Index (MAC_1 + n) */
38098 {
38099 SK_GEPORT *pPrt;
38100@@ -1258,13 +1384,13 @@
38101 pPrt = &pAC->GIni.GP[Port];
38102
38103 if (pPrt->PState == SK_PRT_STOP) {
38104- /* Port State: SK_PRT_STOP */
38105 /* Verify that the reset bit is cleared */
38106 SK_IN16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), &SWord);
38107
38108 if ((SWord & MFF_SET_MAC_RST) != 0) {
38109 /* PState does not match HW state */
38110- SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E006, SKERR_HWI_E006MSG);
38111+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
38112+ ("SkXmInitMac: PState does not match HW state"));
38113 /* Correct it */
38114 pPrt->PState = SK_PRT_RESET;
38115 }
38116@@ -1283,7 +1409,7 @@
38117 * Must be done AFTER first access to BCOM chip.
38118 */
38119 XM_IN16(IoC, Port, XM_MMU_CMD, &SWord);
38120-
38121+
38122 XM_OUT16(IoC, Port, XM_MMU_CMD, SWord | XM_MMU_NO_PRE);
38123
38124 if (pPrt->PhyId1 == PHY_BCOM_ID1_C0) {
38125@@ -1316,7 +1442,7 @@
38126 * Disable Power Management after reset.
38127 */
38128 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &SWord);
38129-
38130+
38131 SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUX_CTRL,
38132 (SK_U16)(SWord | PHY_B_AC_DIS_PM));
38133
38134@@ -1325,19 +1451,13 @@
38135
38136 /* Dummy read the Interrupt source register */
38137 XM_IN16(IoC, Port, XM_ISRC, &SWord);
38138-
38139+
38140 /*
38141 * The auto-negotiation process starts immediately after
38142 * clearing the reset. The auto-negotiation process should be
38143 * started by the SIRQ, therefore stop it here immediately.
38144 */
38145 SkMacInitPhy(pAC, IoC, Port, SK_FALSE);
38146-
38147-#ifdef TEST_ONLY
38148- /* temp. code: enable signal detect */
38149- /* WARNING: do not override GMII setting above */
38150- XM_OUT16(IoC, Port, XM_HW_CFG, XM_HW_COM4SIG);
38151-#endif
38152 }
38153
38154 /*
38155@@ -1351,7 +1471,7 @@
38156 * independent. Remember this when changing.
38157 */
38158 SK_IN16(IoC, (B2_MAC_2 + Port * 8 + i * 2), &SWord);
38159-
38160+
38161 XM_OUT16(IoC, Port, (XM_SA + i * 2), SWord);
38162 }
38163
38164@@ -1369,7 +1489,7 @@
38165 SWord = SK_XM_THR_SL; /* for single port */
38166
38167 if (pAC->GIni.GIMacsFound > 1) {
38168- switch (pAC->GIni.GIPortUsage) {
38169+ switch (pPrt->PPortUsage) {
38170 case SK_RED_LINK:
38171 SWord = SK_XM_THR_REDL; /* redundant link */
38172 break;
38173@@ -1392,7 +1512,7 @@
38174 /* setup register defaults for the Rx Command Register */
38175 SWord = XM_RX_STRIP_FCS | XM_RX_LENERR_OK;
38176
38177- if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
38178+ if (pPrt->PPortUsage == SK_JUMBO_LINK) {
38179 SWord |= XM_RX_BIG_PK_OK;
38180 }
38181
38182@@ -1404,7 +1524,7 @@
38183 */
38184 SWord |= XM_RX_DIS_CEXT;
38185 }
38186-
38187+
38188 XM_OUT16(IoC, Port, XM_RX_CMD, SWord);
38189
38190 /*
38191@@ -1461,8 +1581,8 @@
38192 * nothing
38193 */
38194 void SkGmInitMac(
38195-SK_AC *pAC, /* adapter context */
38196-SK_IOC IoC, /* IO context */
38197+SK_AC *pAC, /* Adapter Context */
38198+SK_IOC IoC, /* I/O Context */
38199 int Port) /* Port Index (MAC_1 + n) */
38200 {
38201 SK_GEPORT *pPrt;
38202@@ -1473,26 +1593,41 @@
38203 pPrt = &pAC->GIni.GP[Port];
38204
38205 if (pPrt->PState == SK_PRT_STOP) {
38206- /* Port State: SK_PRT_STOP */
38207 /* Verify that the reset bit is cleared */
38208 SK_IN32(IoC, MR_ADDR(Port, GMAC_CTRL), &DWord);
38209-
38210+
38211 if ((DWord & GMC_RST_SET) != 0) {
38212 /* PState does not match HW state */
38213- SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E006, SKERR_HWI_E006MSG);
38214+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38215+ ("SkGmInitMac: PState does not match HW state"));
38216 /* Correct it */
38217 pPrt->PState = SK_PRT_RESET;
38218 }
38219+ else {
38220+ /* enable PHY interrupts */
38221+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK,
38222+ (SK_U16)PHY_M_DEF_MSK);
38223+ }
38224 }
38225
38226 if (pPrt->PState == SK_PRT_RESET) {
38227-
38228+
38229 SkGmHardRst(pAC, IoC, Port);
38230
38231 SkGmClearRst(pAC, IoC, Port);
38232-
38233+
38234+#ifndef SK_SLIM
38235+ if (HW_FEATURE(pAC, HWF_FORCE_AUTO_NEG) &&
38236+ pPrt->PLinkModeConf < SK_LMODE_AUTOHALF) {
38237+ /* Force Auto-Negotiation */
38238+ pPrt->PLinkMode = (pPrt->PLinkModeConf == SK_LMODE_FULL) ?
38239+ SK_LMODE_AUTOBOTH : SK_LMODE_AUTOHALF;
38240+ }
38241+#endif /* !SK_SLIM */
38242+
38243 /* Auto-negotiation ? */
38244- if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
38245+ if (pPrt->PLinkMode == SK_LMODE_HALF ||
38246+ pPrt->PLinkMode == SK_LMODE_FULL) {
38247 /* Auto-negotiation disabled */
38248
38249 /* get General Purpose Control */
38250@@ -1500,10 +1635,10 @@
38251
38252 /* disable auto-update for speed, duplex and flow-control */
38253 SWord |= GM_GPCR_AU_ALL_DIS;
38254-
38255+
38256 /* setup General Purpose Control Register */
38257 GM_OUT16(IoC, Port, GM_GP_CTRL, SWord);
38258-
38259+
38260 SWord = GM_GPCR_AU_ALL_DIS;
38261 }
38262 else {
38263@@ -1514,7 +1649,10 @@
38264 switch (pPrt->PLinkSpeed) {
38265 case SK_LSPEED_AUTO:
38266 case SK_LSPEED_1000MBPS:
38267- SWord |= GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100;
38268+ if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
38269+
38270+ SWord |= GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100;
38271+ }
38272 break;
38273 case SK_LSPEED_100MBPS:
38274 SWord |= GM_GPCR_SPEED_100;
38275@@ -1532,8 +1670,6 @@
38276 /* flow-control settings */
38277 switch (pPrt->PFlowCtrlMode) {
38278 case SK_FLOW_MODE_NONE:
38279- /* set Pause Off */
38280- SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_PAUSE_OFF);
38281 /* disable Tx & Rx flow-control */
38282 SWord |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
38283 break;
38284@@ -1551,24 +1687,22 @@
38285 GM_OUT16(IoC, Port, GM_GP_CTRL, SWord);
38286
38287 /* dummy read the Interrupt Source Register */
38288- SK_IN16(IoC, GMAC_IRQ_SRC, &SWord);
38289-
38290+ SK_IN16(IoC, MR_ADDR(Port, GMAC_IRQ_SRC), &SWord);
38291+
38292 #ifndef VCPU
38293- /* read Id from PHY */
38294- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_ID1, &pPrt->PhyId1);
38295-
38296 SkGmInitPhyMarv(pAC, IoC, Port, SK_FALSE);
38297-#endif /* VCPU */
38298+#endif /* !VCPU */
38299 }
38300
38301 (void)SkGmResetCounter(pAC, IoC, Port);
38302
38303 /* setup Transmit Control Register */
38304- GM_OUT16(IoC, Port, GM_TX_CTRL, TX_COL_THR(pPrt->PMacColThres));
38305+ GM_OUT16(IoC, Port, GM_TX_CTRL, (SK_U16)TX_COL_THR(pPrt->PMacColThres));
38306
38307 /* setup Receive Control Register */
38308- GM_OUT16(IoC, Port, GM_RX_CTRL, GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA |
38309- GM_RXCR_CRC_DIS);
38310+ SWord = GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA | GM_RXCR_CRC_DIS;
38311+
38312+ GM_OUT16(IoC, Port, GM_RX_CTRL, SWord);
38313
38314 /* setup Transmit Flow Control Register */
38315 GM_OUT16(IoC, Port, GM_TX_FLOW_CTRL, 0xffff);
38316@@ -1578,31 +1712,29 @@
38317 GM_IN16(IoC, Port, GM_TX_PARAM, &SWord);
38318 #endif /* VCPU */
38319
38320- SWord = TX_JAM_LEN_VAL(pPrt->PMacJamLen) |
38321- TX_JAM_IPG_VAL(pPrt->PMacJamIpgVal) |
38322- TX_IPG_JAM_DATA(pPrt->PMacJamIpgData);
38323-
38324+ SWord = (SK_U16)(TX_JAM_LEN_VAL(pPrt->PMacJamLen) |
38325+ TX_JAM_IPG_VAL(pPrt->PMacJamIpgVal) |
38326+ TX_IPG_JAM_DATA(pPrt->PMacJamIpgData) |
38327+ TX_BACK_OFF_LIM(pPrt->PMacBackOffLim));
38328+
38329 GM_OUT16(IoC, Port, GM_TX_PARAM, SWord);
38330
38331 /* configure the Serial Mode Register */
38332-#ifdef VCPU
38333- GM_IN16(IoC, Port, GM_SERIAL_MODE, &SWord);
38334-#endif /* VCPU */
38335-
38336- SWord = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(pPrt->PMacIpgData);
38337+ SWord = (SK_U16)(DATA_BLIND_VAL(pPrt->PMacDataBlind) |
38338+ GM_SMOD_VLAN_ENA | IPG_DATA_VAL(pPrt->PMacIpgData));
38339
38340 if (pPrt->PMacLimit4) {
38341 /* reset of collision counter after 4 consecutive collisions */
38342 SWord |= GM_SMOD_LIMIT_4;
38343 }
38344
38345- if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
38346+ if (pPrt->PPortUsage == SK_JUMBO_LINK) {
38347 /* enable jumbo mode (Max. Frame Length = 9018) */
38348 SWord |= GM_SMOD_JUMBO_ENA;
38349 }
38350-
38351+
38352 GM_OUT16(IoC, Port, GM_SERIAL_MODE, SWord);
38353-
38354+
38355 /*
38356 * configure the GMACs Station Addresses
38357 * in PROM you can find our addresses at:
38358@@ -1631,17 +1763,17 @@
38359 else {
38360 GM_OUT16(IoC, Port, (GM_SRC_ADDR_1L + i * 4), SWord);
38361 }
38362-#else
38363+#else
38364 GM_OUT16(IoC, Port, (GM_SRC_ADDR_1L + i * 4), SWord);
38365 #endif /* WA_DEV_16 */
38366-
38367+
38368 /* virtual address: will be used for data */
38369 SK_IN16(IoC, (B2_MAC_1 + Port * 8 + i * 2), &SWord);
38370
38371 GM_OUT16(IoC, Port, (GM_SRC_ADDR_2L + i * 4), SWord);
38372-
38373+
38374 /* reset Multicast filtering Hash registers 1-3 */
38375- GM_OUT16(IoC, Port, GM_MC_ADDR_H1 + 4*i, 0);
38376+ GM_OUT16(IoC, Port, GM_MC_ADDR_H1 + i * 4, 0);
38377 }
38378
38379 /* reset Multicast filtering Hash register 4 */
38380@@ -1652,18 +1784,6 @@
38381 GM_OUT16(IoC, Port, GM_RX_IRQ_MSK, 0);
38382 GM_OUT16(IoC, Port, GM_TR_IRQ_MSK, 0);
38383
38384-#if defined(SK_DIAG) || defined(DEBUG)
38385- /* read General Purpose Status */
38386- GM_IN16(IoC, Port, GM_GP_STAT, &SWord);
38387-
38388- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38389- ("MAC Stat Reg.=0x%04X\n", SWord));
38390-#endif /* SK_DIAG || DEBUG */
38391-
38392-#ifdef SK_DIAG
38393- c_print("MAC Stat Reg=0x%04X\n", SWord);
38394-#endif /* SK_DIAG */
38395-
38396 } /* SkGmInitMac */
38397 #endif /* YUKON */
38398
38399@@ -1681,9 +1801,9 @@
38400 * Returns:
38401 * nothing
38402 */
38403-static void SkXmInitDupMd(
38404-SK_AC *pAC, /* adapter context */
38405-SK_IOC IoC, /* IO context */
38406+void SkXmInitDupMd(
38407+SK_AC *pAC, /* Adapter Context */
38408+SK_IOC IoC, /* I/O Context */
38409 int Port) /* Port Index (MAC_1 + n) */
38410 {
38411 switch (pAC->GIni.GP[Port].PLinkModeStatus) {
38412@@ -1729,9 +1849,9 @@
38413 * Returns:
38414 * nothing
38415 */
38416-static void SkXmInitPauseMd(
38417-SK_AC *pAC, /* adapter context */
38418-SK_IOC IoC, /* IO context */
38419+void SkXmInitPauseMd(
38420+SK_AC *pAC, /* Adapter Context */
38421+SK_IOC IoC, /* I/O Context */
38422 int Port) /* Port Index (MAC_1 + n) */
38423 {
38424 SK_GEPORT *pPrt;
38425@@ -1741,11 +1861,11 @@
38426 pPrt = &pAC->GIni.GP[Port];
38427
38428 XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
38429-
38430+
38431 if (pPrt->PFlowCtrlStatus == SK_FLOW_STAT_NONE ||
38432 pPrt->PFlowCtrlStatus == SK_FLOW_STAT_LOC_SEND) {
38433
38434- /* Disable Pause Frame Reception */
38435+ /* disable Pause Frame Reception */
38436 Word |= XM_MMU_IGN_PF;
38437 }
38438 else {
38439@@ -1753,10 +1873,10 @@
38440 * enabling pause frame reception is required for 1000BT
38441 * because the XMAC is not reset if the link is going down
38442 */
38443- /* Enable Pause Frame Reception */
38444+ /* enable Pause Frame Reception */
38445 Word &= ~XM_MMU_IGN_PF;
38446- }
38447-
38448+ }
38449+
38450 XM_OUT16(IoC, Port, XM_MMU_CMD, Word);
38451
38452 XM_IN32(IoC, Port, XM_MODE, &DWord);
38453@@ -1779,10 +1899,10 @@
38454 /* remember this value is defined in big endian (!) */
38455 XM_OUT16(IoC, Port, XM_MAC_PTIME, 0xffff);
38456
38457- /* Set Pause Mode in Mode Register */
38458+ /* set Pause Mode in Mode Register */
38459 DWord |= XM_PAUSE_MODE;
38460
38461- /* Set Pause Mode in MAC Rx FIFO */
38462+ /* set Pause Mode in MAC Rx FIFO */
38463 SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
38464 }
38465 else {
38466@@ -1790,22 +1910,22 @@
38467 * disable pause frame generation is required for 1000BT
38468 * because the XMAC is not reset if the link is going down
38469 */
38470- /* Disable Pause Mode in Mode Register */
38471+ /* disable Pause Mode in Mode Register */
38472 DWord &= ~XM_PAUSE_MODE;
38473
38474- /* Disable Pause Mode in MAC Rx FIFO */
38475+ /* disable Pause Mode in MAC Rx FIFO */
38476 SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
38477 }
38478-
38479+
38480 XM_OUT32(IoC, Port, XM_MODE, DWord);
38481 } /* SkXmInitPauseMd*/
38482
38483
38484 /******************************************************************************
38485 *
38486- * SkXmInitPhyXmac() - Initialize the XMAC Phy registers
38487+ * SkXmInitPhyXmac() - Initialize the XMAC PHY registers
38488 *
38489- * Description: initializes all the XMACs Phy registers
38490+ * Description: initializes all the XMACs PHY registers
38491 *
38492 * Note:
38493 *
38494@@ -1813,22 +1933,22 @@
38495 * nothing
38496 */
38497 static void SkXmInitPhyXmac(
38498-SK_AC *pAC, /* adapter context */
38499-SK_IOC IoC, /* IO context */
38500+SK_AC *pAC, /* Adapter Context */
38501+SK_IOC IoC, /* I/O Context */
38502 int Port, /* Port Index (MAC_1 + n) */
38503-SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */
38504+SK_BOOL DoLoop) /* Should a PHY LoopBack be set-up? */
38505 {
38506 SK_GEPORT *pPrt;
38507 SK_U16 Ctrl;
38508
38509 pPrt = &pAC->GIni.GP[Port];
38510 Ctrl = 0;
38511-
38512+
38513 /* Auto-negotiation ? */
38514 if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
38515 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38516 ("InitPhyXmac: no auto-negotiation Port %d\n", Port));
38517- /* Set DuplexMode in Config register */
38518+ /* set DuplexMode in Config register */
38519 if (pPrt->PLinkMode == SK_LMODE_FULL) {
38520 Ctrl |= PHY_CT_DUP_MD;
38521 }
38522@@ -1841,9 +1961,9 @@
38523 else {
38524 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38525 ("InitPhyXmac: with auto-negotiation Port %d\n", Port));
38526- /* Set Auto-negotiation advertisement */
38527+ /* set Auto-negotiation advertisement */
38528
38529- /* Set Full/half duplex capabilities */
38530+ /* set Full/half duplex capabilities */
38531 switch (pPrt->PLinkMode) {
38532 case SK_LMODE_AUTOHALF:
38533 Ctrl |= PHY_X_AN_HD;
38534@@ -1859,7 +1979,7 @@
38535 SKERR_HWI_E015MSG);
38536 }
38537
38538- /* Set Flow-control capabilities */
38539+ /* set Flow-control capabilities */
38540 switch (pPrt->PFlowCtrlMode) {
38541 case SK_FLOW_MODE_NONE:
38542 Ctrl |= PHY_X_P_NO_PAUSE;
38543@@ -1886,20 +2006,20 @@
38544 }
38545
38546 if (DoLoop) {
38547- /* Set the Phy Loopback bit, too */
38548+ /* set the PHY Loopback bit, too */
38549 Ctrl |= PHY_CT_LOOP;
38550 }
38551
38552- /* Write to the Phy control register */
38553+ /* Write to the PHY control register */
38554 SkXmPhyWrite(pAC, IoC, Port, PHY_XMAC_CTRL, Ctrl);
38555 } /* SkXmInitPhyXmac */
38556
38557
38558 /******************************************************************************
38559 *
38560- * SkXmInitPhyBcom() - Initialize the Broadcom Phy registers
38561+ * SkXmInitPhyBcom() - Initialize the Broadcom PHY registers
38562 *
38563- * Description: initializes all the Broadcom Phy registers
38564+ * Description: initializes all the Broadcom PHY registers
38565 *
38566 * Note:
38567 *
38568@@ -1907,10 +2027,10 @@
38569 * nothing
38570 */
38571 static void SkXmInitPhyBcom(
38572-SK_AC *pAC, /* adapter context */
38573-SK_IOC IoC, /* IO context */
38574+SK_AC *pAC, /* Adapter Context */
38575+SK_IOC IoC, /* I/O Context */
38576 int Port, /* Port Index (MAC_1 + n) */
38577-SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */
38578+SK_BOOL DoLoop) /* Should a PHY LoopBack be set-up? */
38579 {
38580 SK_GEPORT *pPrt;
38581 SK_U16 Ctrl1;
38582@@ -1930,7 +2050,7 @@
38583 /* manually Master/Slave ? */
38584 if (pPrt->PMSMode != SK_MS_MODE_AUTO) {
38585 Ctrl2 |= PHY_B_1000C_MSE;
38586-
38587+
38588 if (pPrt->PMSMode == SK_MS_MODE_MASTER) {
38589 Ctrl2 |= PHY_B_1000C_MSC;
38590 }
38591@@ -1939,7 +2059,7 @@
38592 if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
38593 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38594 ("InitPhyBcom: no auto-negotiation Port %d\n", Port));
38595- /* Set DuplexMode in Config register */
38596+ /* set DuplexMode in Config register */
38597 if (pPrt->PLinkMode == SK_LMODE_FULL) {
38598 Ctrl1 |= PHY_CT_DUP_MD;
38599 }
38600@@ -1957,7 +2077,7 @@
38601 else {
38602 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38603 ("InitPhyBcom: with auto-negotiation Port %d\n", Port));
38604- /* Set Auto-negotiation advertisement */
38605+ /* set Auto-negotiation advertisement */
38606
38607 /*
38608 * Workaround BCOM Errata #1 for the C5 type.
38609@@ -1965,8 +2085,8 @@
38610 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
38611 */
38612 Ctrl2 |= PHY_B_1000C_RD;
38613-
38614- /* Set Full/half duplex capabilities */
38615+
38616+ /* set Full/half duplex capabilities */
38617 switch (pPrt->PLinkMode) {
38618 case SK_LMODE_AUTOHALF:
38619 Ctrl2 |= PHY_B_1000C_AHD;
38620@@ -1982,7 +2102,7 @@
38621 SKERR_HWI_E015MSG);
38622 }
38623
38624- /* Set Flow-control capabilities */
38625+ /* set Flow-control capabilities */
38626 switch (pPrt->PFlowCtrlMode) {
38627 case SK_FLOW_MODE_NONE:
38628 Ctrl3 |= PHY_B_P_NO_PAUSE;
38629@@ -2004,27 +2124,27 @@
38630 /* Restart Auto-negotiation */
38631 Ctrl1 |= PHY_CT_ANE | PHY_CT_RE_CFG;
38632 }
38633-
38634+
38635 /* Initialize LED register here? */
38636 /* No. Please do it in SkDgXmitLed() (if required) and swap
38637- init order of LEDs and XMAC. (MAl) */
38638-
38639+ init order of LEDs and XMAC. (MAl) */
38640+
38641 /* Write 1000Base-T Control Register */
38642 SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_1000T_CTRL, Ctrl2);
38643 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38644- ("Set 1000B-T Ctrl Reg=0x%04X\n", Ctrl2));
38645-
38646+ ("Set 1000B-T Ctrl Reg = 0x%04X\n", Ctrl2));
38647+
38648 /* Write AutoNeg Advertisement Register */
38649 SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUNE_ADV, Ctrl3);
38650 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38651- ("Set Auto-Neg.Adv.Reg=0x%04X\n", Ctrl3));
38652-
38653+ ("Set Auto-Neg.Adv.Reg = 0x%04X\n", Ctrl3));
38654+
38655 if (DoLoop) {
38656- /* Set the Phy Loopback bit, too */
38657+ /* set the PHY Loopback bit, too */
38658 Ctrl1 |= PHY_CT_LOOP;
38659 }
38660
38661- if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
38662+ if (pPrt->PPortUsage == SK_JUMBO_LINK) {
38663 /* configure FIFO to high latency for transmission of ext. packets */
38664 Ctrl4 |= PHY_B_PEC_HIGH_LA;
38665
38666@@ -2036,20 +2156,534 @@
38667
38668 /* Configure LED Traffic Mode and Jumbo Frame usage if specified */
38669 SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_P_EXT_CTRL, Ctrl4);
38670-
38671- /* Write to the Phy control register */
38672+
38673+ /* Write to the PHY control register */
38674 SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_CTRL, Ctrl1);
38675 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38676- ("PHY Control Reg=0x%04X\n", Ctrl1));
38677+ ("PHY Control Reg = 0x%04X\n", Ctrl1));
38678 } /* SkXmInitPhyBcom */
38679 #endif /* GENESIS */
38680
38681+
38682 #ifdef YUKON
38683+#ifdef SK_PHY_LP_MODE
38684+/******************************************************************************
38685+ *
38686+ * SkGmEnterLowPowerMode()
38687+ *
38688+ * Description:
38689+ * This function sets the Marvell Alaska PHY to the low power mode
38690+ * given by parameter mode.
38691+ * The following low power modes are available:
38692+ *
38693+ * - COMA Mode (Deep Sleep):
38694+ * The PHY cannot wake up on its own.
38695+ *
38696+ * - IEEE 22.2.4.1.5 compatible power down mode
38697+ * The PHY cannot wake up on its own.
38698+ *
38699+ * - energy detect mode
38700+ * The PHY can wake up on its own by detecting activity
38701+ * on the CAT 5 cable.
38702+ *
38703+ * - energy detect plus mode
38704+ * The PHY can wake up on its own by detecting activity
38705+ * on the CAT 5 cable.
38706+ * Connected devices can be woken up by sending normal link
38707+ * pulses every second.
38708+ *
38709+ * Note:
38710+ *
38711+ * Returns:
38712+ * 0: ok
38713+ * 1: error
38714+ */
38715+int SkGmEnterLowPowerMode(
38716+SK_AC *pAC, /* Adapter Context */
38717+SK_IOC IoC, /* I/O Context */
38718+int Port, /* Port Index (e.g. MAC_1) */
38719+SK_U8 Mode) /* low power mode */
38720+{
38721+ SK_U8 LastMode;
38722+ SK_U8 Byte;
38723+ SK_U16 Word;
38724+ SK_U16 ClkDiv;
38725+ SK_U32 DWord;
38726+ SK_U32 PowerDownBit;
38727+ int ChipId;
38728+ int Ret = 0;
38729+
38730+ if (!(CHIP_ID_YUKON_2(pAC) || (pAC->GIni.GIYukonLite &&
38731+ pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3))) {
38732+
38733+ return(1);
38734+ }
38735+
38736+ /* save current power mode */
38737+ LastMode = pAC->GIni.GP[Port].PPhyPowerState;
38738+ pAC->GIni.GP[Port].PPhyPowerState = Mode;
38739+
38740+ ChipId = pAC->GIni.GIChipId;
38741+
38742+ SK_DBG_MSG(pAC, SK_DBGMOD_POWM, SK_DBGCAT_CTRL,
38743+ ("SkGmEnterLowPowerMode: %u\n", Mode));
38744+
38745+ /* release GPHY Control reset */
38746+ SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_CLR);
38747+
38748+ /* release GMAC reset */
38749+ SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_CLR);
38750+
38751+ if (ChipId == CHIP_ID_YUKON_EC_U) {
38752+ /* select page 2 to access MAC control register */
38753+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 2);
38754+
38755+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
38756+ /* allow GMII Power Down */
38757+ Word &= ~PHY_M_MAC_GMIF_PUP;
38758+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
38759+
38760+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0);
38761+ }
38762+
38763+ switch (Mode) {
38764+ /* COMA mode (deep sleep) */
38765+ case PHY_PM_DEEP_SLEEP:
38766+ /* setup General Purpose Control Register */
38767+ GM_OUT16(IoC, Port, GM_GP_CTRL, GM_GPCR_FL_PASS |
38768+ GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
38769+
38770+ if (CHIP_ID_YUKON_2(pAC)) {
38771+ /* set power down bit */
38772+ PowerDownBit = (Port == MAC_1) ? PCI_Y2_PHY1_POWD :
38773+ PCI_Y2_PHY2_POWD;
38774+
38775+ if (ChipId != CHIP_ID_YUKON_EC) {
38776+
38777+ if (ChipId == CHIP_ID_YUKON_EC_U) {
38778+
38779+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
38780+ /* enable Power Down */
38781+ Word |= PHY_M_PC_POW_D_ENA;
38782+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
38783+ }
38784+
38785+ /* set IEEE compatible Power Down Mode (dev. #4.99) */
38786+ Ret = SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PHY_CT_PDOWN);
38787+ }
38788+ }
38789+ else {
38790+ /* apply COMA mode workaround */
38791+ (void)SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_ADDR, 0x001f);
38792+
38793+ Ret = SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xfff3);
38794+
38795+ PowerDownBit = PCI_PHY_COMA;
38796+ }
38797+
38798+ SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
38799+
38800+ SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_1), &DWord);
38801+
38802+ /* set PHY to PowerDown/COMA Mode */
38803+ SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_1), DWord | PowerDownBit);
38804+
38805+ /* check if this routine was called from a for() loop */
38806+ if (pAC->GIni.GIMacsFound == 1 || Port == MAC_2) {
38807+
38808+ /* ASF system clock stopped */
38809+ SK_OUT8(IoC, B28_Y2_ASF_STAT_CMD, (SK_U8)Y2_ASF_CLK_HALT);
38810+
38811+ if (ChipId == CHIP_ID_YUKON_EC_U) {
38812+ /* set GPHY Control reset */
38813+ SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_SET);
38814+
38815+ /* additional power saving measurements */
38816+ SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_4), &DWord);
38817+
38818+ /* set gating core clock for LTSSM in L1 state */
38819+ DWord |= (P_PEX_LTSSM_STAT(P_PEX_LTSSM_L1_STAT) |
38820+ /* auto clock gated scheme controlled by CLKREQ */
38821+ P_ASPM_A1_MODE_SELECT |
38822+ /* enable Gate Root Core Clock */
38823+ P_CLK_GATE_ROOT_COR_ENA);
38824+
38825+ if (HW_FEATURE(pAC, HWF_WA_DEV_4200)) {
38826+ /* enable Clock Power Management (CLKREQ) */
38827+ SK_IN16(IoC, PCI_C(pAC, PEX_LNK_CTRL), &Word);
38828+ Word |= PEX_LC_CLK_PM_ENA;
38829+ SK_OUT16(IoC, PCI_C(pAC, PEX_LNK_CTRL), Word);
38830+ }
38831+ else {
38832+ /* force CLKREQ Enable in Our4 (A1b only) */
38833+ DWord |= P_ASPM_FORCE_CLKREQ_ENA;
38834+ }
38835+
38836+ SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_4), DWord);
38837+
38838+ /* set Mask Register for Release/Gate Clock */
38839+ SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_5),
38840+ P_REL_PCIE_EXIT_L1_ST | P_GAT_PCIE_ENTER_L1_ST |
38841+ P_REL_PCIE_RX_EX_IDLE | P_GAT_PCIE_RX_EL_IDLE |
38842+ P_REL_GPHY_LINK_UP | P_GAT_GPHY_LINK_DOWN);
38843+ }
38844+
38845+ if (HW_FEATURE(pAC, HWF_RED_CORE_CLK_SUP)) {
38846+ /* divide clock by 4 only for Yukon-EC */
38847+ ClkDiv = (ChipId == CHIP_ID_YUKON_EC) ? 1 : 0;
38848+
38849+ /* on Yukon-2 clock select value is 31 */
38850+ DWord = (ChipId == CHIP_ID_YUKON_XL) ?
38851+ (Y2_CLK_DIV_VAL_2(0) | Y2_CLK_SEL_VAL_2(31)) :
38852+ Y2_CLK_DIV_VAL(ClkDiv);
38853+
38854+ /* check for Yukon-2 dual port PCI-Express adapter */
38855+ if (!(pAC->GIni.GIMacsFound == 2 &&
38856+ pAC->GIni.GIPciBus == SK_PEX_BUS)) {
38857+ /* enable Core Clock Division */
38858+ DWord |= Y2_CLK_DIV_ENA;
38859+ }
38860+
38861+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38862+ ("Set Core Clock: 0x%08X\n", DWord));
38863+
38864+ /* reduce Core Clock Frequency */
38865+ SK_OUT32(IoC, B2_Y2_CLK_CTRL, DWord);
38866+ }
38867+
38868+ if (HW_FEATURE(pAC, HWF_CLK_GATING_ENABLE)) {
38869+ /* check for Yukon-2 Rev. A2 */
38870+ if (ChipId == CHIP_ID_YUKON_XL &&
38871+ pAC->GIni.GIChipRev > CHIP_REV_YU_XL_A1) {
38872+ /* enable bits are inverted */
38873+ Byte = 0;
38874+ }
38875+ else {
38876+ Byte = (SK_U8)(Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
38877+ Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
38878+ Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
38879+ }
38880+
38881+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38882+ ("Set Clock Gating: 0x%02X\n", Byte));
38883+
38884+ /* disable MAC/PHY, PCI and Core Clock for both Links */
38885+ SK_OUT8(IoC, B2_Y2_CLK_GATE, Byte);
38886+ }
38887+
38888+ if (pAC->GIni.GIVauxAvail) {
38889+ /* switch power to VAUX */
38890+ SK_OUT8(IoC, B0_POWER_CTRL, (SK_U8)(PC_VAUX_ENA | PC_VCC_ENA |
38891+ PC_VAUX_ON | PC_VCC_OFF));
38892+ }
38893+#ifdef DEBUG
38894+ SK_IN32(IoC, B0_CTST, &DWord);
38895+
38896+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
38897+ ("Ctrl/Stat & Switch: 0x%08x\n", DWord));
38898+#endif /* DEBUG */
38899+
38900+ if (pAC->GIni.GILevel != SK_INIT_IO &&
38901+ pAC->GIni.GIMacsFound == 1 &&
38902+ pAC->GIni.GIPciBus == SK_PEX_BUS) {
38903+
38904+ if (ChipId == CHIP_ID_YUKON_EC_U) {
38905+
38906+#ifdef PCI_E_L1_STATE
38907+ SK_IN16(IoC, PCI_C(pAC, PCI_OUR_REG_1), &Word);
38908+ /* force to PCIe L1 */
38909+ Word |= (SK_U16)PCI_FORCE_PEX_L1;
38910+ SK_OUT16(IoC, PCI_C(pAC, PCI_OUR_REG_1), Word);
38911+#endif /* PCI_E_L1_STATE */
38912+ }
38913+ else {
38914+ /* switch to D1 state */
38915+ SK_OUT8(IoC, PCI_C(pAC, PCI_PM_CTL_STS), PCI_PM_STATE_D1);
38916+ }
38917+ }
38918+ }
38919+
38920+ break;
38921+
38922+ /* IEEE 22.2.4.1.5 compatible power down mode */
38923+ case PHY_PM_IEEE_POWER_DOWN:
38924+
38925+ Ret = SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
38926+
38927+ if (!CHIP_ID_YUKON_2(pAC)) {
38928+ /* disable MAC 125 MHz clock */
38929+ Word |= PHY_M_PC_DIS_125CLK;
38930+ Word &= ~PHY_M_PC_MAC_POW_UP;
38931+ }
38932+
38933+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
38934+
38935+ /* these register changes must be followed by a software reset */
38936+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word);
38937+
38938+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word | PHY_CT_RESET);
38939+
38940+ /* switch IEEE compatible power down mode on */
38941+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word | PHY_CT_PDOWN);
38942+
38943+ break;
38944+
38945+ /* energy detect and energy detect plus mode */
38946+ case PHY_PM_ENERGY_DETECT:
38947+ case PHY_PM_ENERGY_DETECT_PLUS:
38948+
38949+ Ret = SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
38950+
38951+ /* disable Polarity Reversal */
38952+ Word |= PHY_M_PC_POL_R_DIS;
38953+
38954+ if (!CHIP_ID_YUKON_2(pAC)) {
38955+ /* disable MAC 125 MHz clock */
38956+ Word |= PHY_M_PC_DIS_125CLK;
38957+ }
38958+
38959+ if (ChipId == CHIP_ID_YUKON_FE) {
38960+ /* enable Energy Detect (sense & pulse) */
38961+ Word |= PHY_M_PC_ENA_ENE_DT;
38962+ }
38963+ else {
38964+ /* clear energy detect mode bits */
38965+ Word &= ~PHY_M_PC_EN_DET_MSK;
38966+
38967+ Word |= (Mode == PHY_PM_ENERGY_DETECT) ? PHY_M_PC_EN_DET :
38968+ PHY_M_PC_EN_DET_PLUS;
38969+ }
38970+
38971+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
38972+
38973+ /* these register changes must be followed by a software reset */
38974+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word);
38975+ Word |= PHY_CT_RESET;
38976+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word);
38977+
38978+ if (ChipId == CHIP_ID_YUKON_EC_U) {
38979+ /* additional power saving measurements */
38980+ SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_4), &DWord);
38981+
38982+ /* set gating core clock for LTSSM in L1 state */
38983+ DWord |= (P_PEX_LTSSM_STAT(P_PEX_LTSSM_L1_STAT) |
38984+ /* Enable Gate Root Core Clock */
38985+ P_CLK_GATE_ROOT_COR_ENA);
38986+
38987+ SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_4), DWord);
38988+
38989+ /* set Mask Register for Release/Gate Clock */
38990+ SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_5),
38991+ P_REL_PCIE_EXIT_L1_ST | P_GAT_PCIE_ENTER_L1_ST |
38992+ P_REL_PCIE_RX_EX_IDLE | P_GAT_PCIE_RX_EL_IDLE |
38993+ P_REL_GPHY_LINK_UP | P_GAT_GPHY_LINK_DOWN);
38994+
38995+#ifdef PCI_E_L1_STATE
38996+ SK_IN16(IoC, PCI_C(pAC, PCI_OUR_REG_1), &Word);
38997+ /* enable PCIe L1 on GPHY link down */
38998+ Word |= (SK_U16)PCI_ENA_GPHY_LNK;
38999+ SK_OUT16(IoC, PCI_C(pAC, PCI_OUR_REG_1), Word);
39000+#endif /* PCI_E_L1_STATE */
39001+ }
39002+
39003+ break;
39004+
39005+ /* don't change current power mode */
39006+ default:
39007+ pAC->GIni.GP[Port].PPhyPowerState = LastMode;
39008+ Ret = 1;
39009+ }
39010+
39011+ return(Ret);
39012+
39013+} /* SkGmEnterLowPowerMode */
39014+
39015+/******************************************************************************
39016+ *
39017+ * SkGmLeaveLowPowerMode()
39018+ *
39019+ * Description:
39020+ * Leave the current low power mode and switch to normal mode
39021+ *
39022+ * Note:
39023+ *
39024+ * Returns:
39025+ * 0: ok
39026+ * 1: error
39027+ */
39028+int SkGmLeaveLowPowerMode(
39029+SK_AC *pAC, /* Adapter Context */
39030+SK_IOC IoC, /* I/O Context */
39031+int Port) /* Port Index (e.g. MAC_1) */
39032+{
39033+ SK_U32 DWord;
39034+ SK_U32 PowerDownBit;
39035+ SK_U16 Word;
39036+ SK_U8 LastMode;
39037+ int ChipId;
39038+ int Ret = 0;
39039+
39040+ if (!(CHIP_ID_YUKON_2(pAC) || (pAC->GIni.GIYukonLite &&
39041+ pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3))) {
39042+
39043+ return(1);
39044+ }
39045+
39046+ /* save current power mode */
39047+ LastMode = pAC->GIni.GP[Port].PPhyPowerState;
39048+ pAC->GIni.GP[Port].PPhyPowerState = PHY_PM_OPERATIONAL_MODE;
39049+
39050+ ChipId = pAC->GIni.GIChipId;
39051+
39052+ SK_DBG_MSG(pAC, SK_DBGMOD_POWM, SK_DBGCAT_CTRL,
39053+ ("SkGmLeaveLowPowerMode: %u\n", LastMode));
39054+
39055+ switch (LastMode) {
39056+ /* COMA mode (deep sleep) */
39057+ case PHY_PM_DEEP_SLEEP:
39058+
39059+ if (ChipId == CHIP_ID_YUKON_EC_U) {
39060+#ifdef PCI_E_L1_STATE
39061+ /* set to default value (leave PCIe L1) */
39062+ SkPciWriteCfgWord(pAC, PCI_OUR_REG_1, 0);
39063+#endif /* PCI_E_L1_STATE */
39064+
39065+ SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_4), &DWord);
39066+
39067+ DWord &= P_ASPM_CONTROL_MSK;
39068+ /* set all bits to 0 except bits 15..12 */
39069+ SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_4), DWord);
39070+
39071+ /* set to default value */
39072+ SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_5), 0);
39073+ }
39074+ else {
39075+ SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &Word);
39076+
39077+ /* reset all DState bits */
39078+ Word &= ~PCI_PM_STATE_MSK;
39079+
39080+ /* switch to D0 state */
39081+ SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, Word);
39082+ }
39083+
39084+ SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
39085+
39086+ if (CHIP_ID_YUKON_2(pAC)) {
39087+ /* disable Core Clock Division */
39088+ SK_OUT32(IoC, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
39089+
39090+ /* set power down bit */
39091+ PowerDownBit = (Port == MAC_1) ? PCI_Y2_PHY1_POWD :
39092+ PCI_Y2_PHY2_POWD;
39093+ }
39094+ else {
39095+ PowerDownBit = PCI_PHY_COMA;
39096+ }
39097+
39098+ SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_1), &DWord);
39099+
39100+ /* Release PHY from PowerDown/COMA Mode */
39101+ SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_1), DWord & ~PowerDownBit);
39102+
39103+ SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
39104+
39105+ if (CHIP_ID_YUKON_2(pAC)) {
39106+
39107+ if (ChipId == CHIP_ID_YUKON_FE) {
39108+ /* release IEEE compatible Power Down Mode */
39109+ Ret = SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PHY_CT_ANE);
39110+ }
39111+ else if (ChipId == CHIP_ID_YUKON_EC_U) {
39112+ /* release GPHY Control reset */
39113+ SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_CLR);
39114+ }
39115+ }
39116+ else {
39117+ SK_IN32(IoC, B2_GP_IO, &DWord);
39118+
39119+ /* set to output */
39120+ DWord |= (GP_DIR_9 | GP_IO_9);
39121+
39122+ /* set PHY reset */
39123+ SK_OUT32(IoC, B2_GP_IO, DWord);
39124+
39125+ DWord &= ~GP_IO_9; /* clear PHY reset (active high) */
39126+
39127+ /* clear PHY reset */
39128+ SK_OUT32(IoC, B2_GP_IO, DWord);
39129+ }
39130+
39131+ break;
39132+
39133+ /* IEEE 22.2.4.1.5 compatible power down mode */
39134+ case PHY_PM_IEEE_POWER_DOWN:
39135+
39136+ if (ChipId != CHIP_ID_YUKON_XL) {
39137+
39138+ Ret = SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
39139+ Word &= ~PHY_M_PC_DIS_125CLK; /* enable MAC 125 MHz clock */
39140+ Word |= PHY_M_PC_MAC_POW_UP; /* set MAC power up */
39141+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
39142+
39143+ /* these register changes must be followed by a software reset */
39144+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word);
39145+ Word |= PHY_CT_RESET;
39146+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word);
39147+ }
39148+
39149+ /* switch IEEE compatible power down mode off */
39150+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word);
39151+ Word &= ~PHY_CT_PDOWN;
39152+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word);
39153+
39154+ break;
39155+
39156+ /* energy detect and energy detect plus mode */
39157+ case PHY_PM_ENERGY_DETECT:
39158+ case PHY_PM_ENERGY_DETECT_PLUS:
39159+
39160+ if (ChipId != CHIP_ID_YUKON_XL) {
39161+
39162+ Ret = SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
39163+
39164+ if (ChipId == CHIP_ID_YUKON_FE) {
39165+ /* disable Energy Detect */
39166+ Word &= ~PHY_M_PC_ENA_ENE_DT;
39167+ }
39168+ else {
39169+ /* disable energy detect mode & enable MAC 125 MHz clock */
39170+ Word &= ~(PHY_M_PC_EN_DET_MSK | PHY_M_PC_DIS_125CLK);
39171+ }
39172+
39173+ /* enable Polarity Reversal */
39174+ Word &= ~PHY_M_PC_POL_R_DIS;
39175+
39176+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
39177+
39178+ /* these register changes must be followed by a software reset */
39179+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word);
39180+ Word |= PHY_CT_RESET;
39181+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word);
39182+ }
39183+ break;
39184+
39185+ /* don't change current power mode */
39186+ default:
39187+ pAC->GIni.GP[Port].PPhyPowerState = LastMode;
39188+ Ret = 1;
39189+ }
39190+
39191+ return(Ret);
39192+
39193+} /* SkGmLeaveLowPowerMode */
39194+#endif /* SK_PHY_LP_MODE */
39195+
39196 /******************************************************************************
39197 *
39198- * SkGmInitPhyMarv() - Initialize the Marvell Phy registers
39199+ * SkGmInitPhyMarv() - Initialize the Marvell PHY registers
39200 *
39201- * Description: initializes all the Marvell Phy registers
39202+ * Description: initializes all the Marvell PHY registers
39203 *
39204 * Note:
39205 *
39206@@ -2057,107 +2691,247 @@
39207 * nothing
39208 */
39209 static void SkGmInitPhyMarv(
39210-SK_AC *pAC, /* adapter context */
39211-SK_IOC IoC, /* IO context */
39212+SK_AC *pAC, /* Adapter Context */
39213+SK_IOC IoC, /* I/O Context */
39214 int Port, /* Port Index (MAC_1 + n) */
39215-SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */
39216+SK_BOOL DoLoop) /* Should a PHY LoopBack be set-up? */
39217 {
39218 SK_GEPORT *pPrt;
39219+ SK_BOOL AutoNeg;
39220 SK_U16 PhyCtrl;
39221 SK_U16 C1000BaseT;
39222 SK_U16 AutoNegAdv;
39223+ SK_U8 PauseMode;
39224+ int ChipId;
39225+ int Mode;
39226+#ifndef VCPU
39227+ SK_U16 Word;
39228+ SK_U16 PageReg;
39229+#ifndef SK_SLIM
39230+ SK_U16 LoopSpeed;
39231+#endif /* !SK_SLIM */
39232 SK_U16 ExtPhyCtrl;
39233+ SK_U16 BlinkCtrl;
39234 SK_U16 LedCtrl;
39235- SK_BOOL AutoNeg;
39236+ SK_U16 LedConf;
39237+ SK_U16 LedOver;
39238+#ifndef SK_DIAG
39239+ SK_EVPARA Para;
39240+#endif /* !SK_DIAG */
39241 #if defined(SK_DIAG) || defined(DEBUG)
39242 SK_U16 PhyStat;
39243 SK_U16 PhyStat1;
39244 SK_U16 PhySpecStat;
39245 #endif /* SK_DIAG || DEBUG */
39246+#endif /* !VCPU */
39247+
39248+ /* set Pause On */
39249+ PauseMode = (SK_U8)GMC_PAUSE_ON;
39250
39251 pPrt = &pAC->GIni.GP[Port];
39252
39253+ ChipId = pAC->GIni.GIChipId;
39254+
39255 /* Auto-negotiation ? */
39256- if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
39257- AutoNeg = SK_FALSE;
39258+ AutoNeg = pPrt->PLinkMode != SK_LMODE_HALF &&
39259+ pPrt->PLinkMode != SK_LMODE_FULL;
39260+
39261+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39262+ ("InitPhyMarv: Port %d, Auto-neg. %s, LMode %d, LSpeed %d, FlowC %d\n",
39263+ Port, AutoNeg ? "ON" : "OFF",
39264+ pPrt->PLinkMode, pPrt->PLinkSpeed, pPrt->PFlowCtrlMode));
39265+
39266+#ifndef VCPU
39267+ /* read Id from PHY */
39268+ if (SkGmPhyRead(pAC, IoC, Port, PHY_MARV_ID1, &pPrt->PhyId1) != 0) {
39269+
39270+#ifndef SK_DIAG
39271+ Para.Para64 = Port;
39272+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
39273+#endif /* !SK_DIAG */
39274+
39275+ return;
39276 }
39277- else {
39278- AutoNeg = SK_TRUE;
39279+
39280+ if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
39281+
39282+#ifndef SK_SLIM
39283+ if (DoLoop) {
39284+ /* special setup for PHY 88E1112 */
39285+ if (ChipId == CHIP_ID_YUKON_XL) {
39286+
39287+ LoopSpeed = pPrt->PLinkSpeed;
39288+
39289+ if (LoopSpeed == SK_LSPEED_AUTO) {
39290+ /* force 1000 Mbps */
39291+ LoopSpeed = SK_LSPEED_1000MBPS;
39292+ }
39293+ LoopSpeed += 2;
39294+
39295+ /* save page register */
39296+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_ADR, &PageReg);
39297+
39298+ /* select page 2 to access MAC control register */
39299+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 2);
39300+
39301+ /* set MAC interface speed */
39302+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, LoopSpeed << 4);
39303+
39304+ /* restore page register */
39305+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, PageReg);
39306+
39307+ /* disable link pulses */
39308+ Word = PHY_M_PC_DIS_LINK_P;
39309+ }
39310+ else {
39311+ /* set 'MAC Power up'-bit, set Manual MDI configuration */
39312+ Word = PHY_M_PC_MAC_POW_UP;
39313+ }
39314+
39315+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
39316+ }
39317+ else
39318+#endif /* !SK_SLIM */
39319+ if (AutoNeg && pPrt->PLinkSpeed == SK_LSPEED_AUTO &&
39320+ !(ChipId == CHIP_ID_YUKON_XL || ChipId == CHIP_ID_YUKON_EC_U)) {
39321+ /* Read Ext. PHY Specific Control */
39322+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl);
39323+
39324+ ExtPhyCtrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
39325+ PHY_M_EC_MAC_S_MSK);
39326+
39327+ ExtPhyCtrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
39328+
39329+ /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
39330+ if (pAC->GIni.GIYukonLite || ChipId == CHIP_ID_YUKON_EC) {
39331+ /* set downshift counter to 3x and enable downshift */
39332+ ExtPhyCtrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
39333+ }
39334+ else {
39335+ /* set master & slave downshift counter to 1x */
39336+ ExtPhyCtrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
39337+ }
39338+
39339+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_CTRL, ExtPhyCtrl);
39340+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39341+ ("Set Ext. PHY Ctrl = 0x%04X\n", ExtPhyCtrl));
39342+ }
39343 }
39344-
39345- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39346- ("InitPhyMarv: Port %d, auto-negotiation %s\n",
39347- Port, AutoNeg ? "ON" : "OFF"));
39348
39349-#ifdef VCPU
39350- VCPUprintf(0, "SkGmInitPhyMarv(), Port=%u, DoLoop=%u\n",
39351- Port, DoLoop);
39352-#else /* VCPU */
39353- if (DoLoop) {
39354- /* Set 'MAC Power up'-bit, set Manual MDI configuration */
39355- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL,
39356- PHY_M_PC_MAC_POW_UP);
39357+ if (CHIP_ID_YUKON_2(pAC)) {
39358+ /* Read PHY Specific Control */
39359+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &PhyCtrl);
39360+
39361+ if (!DoLoop && pAC->GIni.GICopperType) {
39362+
39363+ if (ChipId == CHIP_ID_YUKON_FE) {
39364+ /* enable Automatic Crossover (!!! Bits 5..4) */
39365+ PhyCtrl |= (SK_U16)(PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1);
39366+ }
39367+ else {
39368+#ifndef SK_DIAG
39369+ /* disable Energy Detect Mode */
39370+ PhyCtrl &= ~PHY_M_PC_EN_DET_MSK;
39371+#endif /* !SK_DIAG */
39372+
39373+ /* enable Automatic Crossover */
39374+ PhyCtrl |= (SK_U16)PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
39375+
39376+ /* downshift on PHY 88E1112 and 88E1149 is changed */
39377+ if (AutoNeg && pPrt->PLinkSpeed == SK_LSPEED_AUTO &&
39378+ (ChipId == CHIP_ID_YUKON_XL ||
39379+ ChipId == CHIP_ID_YUKON_EC_U)) {
39380+ /* set downshift counter to 3x and enable downshift */
39381+ PhyCtrl &= ~PHY_M_PC_DSC_MSK;
39382+ PhyCtrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
39383+ }
39384+ }
39385+ }
39386+ /* workaround for deviation #4.88 (CRC errors) */
39387+ else {
39388+ /* disable Automatic Crossover */
39389+ PhyCtrl &= ~PHY_M_PC_MDIX_MSK;
39390+ }
39391+
39392+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, PhyCtrl);
39393 }
39394- else if (AutoNeg && pPrt->PLinkSpeed == SK_LSPEED_AUTO) {
39395- /* Read Ext. PHY Specific Control */
39396- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl);
39397-
39398- ExtPhyCtrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
39399- PHY_M_EC_MAC_S_MSK);
39400-
39401- ExtPhyCtrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ) |
39402- PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
39403-
39404- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_CTRL, ExtPhyCtrl);
39405- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39406- ("Set Ext. PHY Ctrl=0x%04X\n", ExtPhyCtrl));
39407+
39408+ /* special setup for PHY 88E1112 Fiber */
39409+ if (ChipId == CHIP_ID_YUKON_XL && !pAC->GIni.GICopperType) {
39410+ /* select 1000BASE-X only mode in MAC Specific Ctrl Reg. */
39411+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 2);
39412+
39413+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
39414+
39415+ Word &= ~PHY_M_MAC_MD_MSK;
39416+ Word |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
39417+
39418+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
39419+
39420+ /* select page 1 to access Fiber registers */
39421+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 1);
39422+
39423+ if (pAC->GIni.GIPmdTyp == 'P') {
39424+ /* for SFP-module set SIGDET polarity to low */
39425+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
39426+
39427+ Word |= PHY_M_FIB_SIGD_POL;
39428+
39429+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
39430+ }
39431 }
39432
39433 /* Read PHY Control */
39434 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &PhyCtrl);
39435
39436+#ifndef SK_SLIM
39437 if (!AutoNeg) {
39438- /* Disable Auto-negotiation */
39439+ /* disable Auto-negotiation */
39440 PhyCtrl &= ~PHY_CT_ANE;
39441 }
39442+#endif /* !SK_SLIM */
39443
39444 PhyCtrl |= PHY_CT_RESET;
39445- /* Assert software reset */
39446+ /* assert software reset */
39447 SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PhyCtrl);
39448-#endif /* VCPU */
39449+#endif /* !VCPU */
39450
39451 PhyCtrl = 0 /* PHY_CT_COL_TST */;
39452 C1000BaseT = 0;
39453 AutoNegAdv = PHY_SEL_TYPE;
39454
39455+#ifndef SK_SLIM
39456 /* manually Master/Slave ? */
39457 if (pPrt->PMSMode != SK_MS_MODE_AUTO) {
39458 /* enable Manual Master/Slave */
39459 C1000BaseT |= PHY_M_1000C_MSE;
39460-
39461+
39462 if (pPrt->PMSMode == SK_MS_MODE_MASTER) {
39463 C1000BaseT |= PHY_M_1000C_MSC; /* set it to Master */
39464 }
39465 }
39466-
39467+#endif /* !SK_SLIM */
39468+
39469 /* Auto-negotiation ? */
39470 if (!AutoNeg) {
39471-
39472+
39473+#ifndef SK_SLIM
39474 if (pPrt->PLinkMode == SK_LMODE_FULL) {
39475- /* Set Full Duplex Mode */
39476+ /* set Full Duplex Mode */
39477 PhyCtrl |= PHY_CT_DUP_MD;
39478 }
39479
39480- /* Set Master/Slave manually if not already done */
39481+ /* set Master/Slave manually if not already done */
39482 if (pPrt->PMSMode == SK_MS_MODE_AUTO) {
39483 C1000BaseT |= PHY_M_1000C_MSE; /* set it to Slave */
39484 }
39485
39486- /* Set Speed */
39487+ /* set Speed */
39488 switch (pPrt->PLinkSpeed) {
39489 case SK_LSPEED_AUTO:
39490 case SK_LSPEED_1000MBPS:
39491- PhyCtrl |= PHY_CT_SP1000;
39492+ PhyCtrl |= (((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) ?
39493+ PHY_CT_SP1000 : PHY_CT_SP100);
39494 break;
39495 case SK_LSPEED_100MBPS:
39496 PhyCtrl |= PHY_CT_SP100;
39497@@ -2169,38 +2943,67 @@
39498 SKERR_HWI_E019MSG);
39499 }
39500
39501+ if ((pPrt->PFlowCtrlMode == SK_FLOW_STAT_NONE) ||
39502+ /* disable Pause also for 10/100 Mbps in half duplex mode */
39503+ ((ChipId != CHIP_ID_YUKON_EC_U) &&
39504+ (pPrt->PLinkMode == SK_LMODE_HALF) &&
39505+ ((pPrt->PLinkSpeed == SK_LSPEED_STAT_100MBPS) ||
39506+ (pPrt->PLinkSpeed == SK_LSPEED_STAT_10MBPS)))) {
39507+
39508+ /* set Pause Off */
39509+ PauseMode = (SK_U8)GMC_PAUSE_OFF;
39510+ }
39511+
39512+ SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), PauseMode);
39513+
39514 if (!DoLoop) {
39515+ /* assert software reset */
39516 PhyCtrl |= PHY_CT_RESET;
39517 }
39518+#endif /* !SK_SLIM */
39519 }
39520 else {
39521- /* Set Auto-negotiation advertisement */
39522-
39523+ /* set Auto-negotiation advertisement */
39524+
39525 if (pAC->GIni.GICopperType) {
39526- /* Set Speed capabilities */
39527+ /* set Speed capabilities */
39528 switch (pPrt->PLinkSpeed) {
39529 case SK_LSPEED_AUTO:
39530- C1000BaseT |= PHY_M_1000C_AHD | PHY_M_1000C_AFD;
39531+ if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
39532+ C1000BaseT |= PHY_M_1000C_AFD;
39533+#ifdef xSK_DIAG
39534+ C1000BaseT |= PHY_M_1000C_AHD;
39535+#endif /* SK_DIAG */
39536+ }
39537 AutoNegAdv |= PHY_M_AN_100_FD | PHY_M_AN_100_HD |
39538 PHY_M_AN_10_FD | PHY_M_AN_10_HD;
39539 break;
39540 case SK_LSPEED_1000MBPS:
39541- C1000BaseT |= PHY_M_1000C_AHD | PHY_M_1000C_AFD;
39542+ if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
39543+ C1000BaseT |= PHY_M_1000C_AFD;
39544+#ifdef xSK_DIAG
39545+ C1000BaseT |= PHY_M_1000C_AHD;
39546+#endif /* SK_DIAG */
39547+ }
39548 break;
39549 case SK_LSPEED_100MBPS:
39550- AutoNegAdv |= PHY_M_AN_100_FD | PHY_M_AN_100_HD |
39551- /* advertise 10Base-T also */
39552- PHY_M_AN_10_FD | PHY_M_AN_10_HD;
39553+ if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_100MBPS) != 0) {
39554+ AutoNegAdv |= PHY_M_AN_100_FD | PHY_M_AN_100_HD |
39555+ /* advertise 10Base-T also */
39556+ PHY_M_AN_10_FD | PHY_M_AN_10_HD;
39557+ }
39558 break;
39559 case SK_LSPEED_10MBPS:
39560- AutoNegAdv |= PHY_M_AN_10_FD | PHY_M_AN_10_HD;
39561+ if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_10MBPS) != 0) {
39562+ AutoNegAdv |= PHY_M_AN_10_FD | PHY_M_AN_10_HD;
39563+ }
39564 break;
39565 default:
39566 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E019,
39567 SKERR_HWI_E019MSG);
39568 }
39569
39570- /* Set Full/half duplex capabilities */
39571+ /* set Full/half duplex capabilities */
39572 switch (pPrt->PLinkMode) {
39573 case SK_LMODE_AUTOHALF:
39574 C1000BaseT &= ~PHY_M_1000C_AFD;
39575@@ -2216,8 +3019,8 @@
39576 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E015,
39577 SKERR_HWI_E015MSG);
39578 }
39579-
39580- /* Set Flow-control capabilities */
39581+
39582+ /* set Flow-control capabilities */
39583 switch (pPrt->PFlowCtrlMode) {
39584 case SK_FLOW_MODE_NONE:
39585 AutoNegAdv |= PHY_B_P_NO_PAUSE;
39586@@ -2236,9 +3039,9 @@
39587 SKERR_HWI_E016MSG);
39588 }
39589 }
39590- else { /* special defines for FIBER (88E1011S only) */
39591-
39592- /* Set Full/half duplex capabilities */
39593+ else { /* special defines for FIBER (88E1040S only) */
39594+
39595+ /* set Full/half duplex capabilities */
39596 switch (pPrt->PLinkMode) {
39597 case SK_LMODE_AUTOHALF:
39598 AutoNegAdv |= PHY_M_AN_1000X_AHD;
39599@@ -2253,8 +3056,8 @@
39600 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E015,
39601 SKERR_HWI_E015MSG);
39602 }
39603-
39604- /* Set Flow-control capabilities */
39605+
39606+ /* set Flow-control capabilities */
39607 switch (pPrt->PFlowCtrlMode) {
39608 case SK_FLOW_MODE_NONE:
39609 AutoNegAdv |= PHY_M_P_NO_PAUSE_X;
39610@@ -2279,138 +3082,242 @@
39611 PhyCtrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
39612 }
39613 }
39614-
39615+
39616 #ifdef VCPU
39617 /*
39618 * E-mail from Gu Lin (08-03-2002):
39619 */
39620-
39621+
39622 /* Program PHY register 30 as 16'h0708 for simulation speed up */
39623 SkGmPhyWrite(pAC, IoC, Port, 30, 0x0700 /* 0x0708 */);
39624-
39625+
39626 VCpuWait(2000);
39627
39628-#else /* VCPU */
39629-
39630- /* Write 1000Base-T Control Register */
39631- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_1000T_CTRL, C1000BaseT);
39632- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39633- ("Set 1000B-T Ctrl =0x%04X\n", C1000BaseT));
39634-
39635+#else /* !VCPU */
39636+
39637+ if (ChipId != CHIP_ID_YUKON_FE) {
39638+ /* Write 1000Base-T Control Register */
39639+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_1000T_CTRL, C1000BaseT);
39640+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39641+ ("Set 1000B-T Ctrl = 0x%04X\n", C1000BaseT));
39642+ }
39643+
39644 /* Write AutoNeg Advertisement Register */
39645 SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_AUNE_ADV, AutoNegAdv);
39646 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39647- ("Set Auto-Neg.Adv.=0x%04X\n", AutoNegAdv));
39648-#endif /* VCPU */
39649-
39650+ ("Set Auto-Neg.Adv. = 0x%04X\n", AutoNegAdv));
39651+#endif /* !VCPU */
39652+
39653+#ifndef SK_SLIM
39654 if (DoLoop) {
39655- /* Set the PHY Loopback bit */
39656+ /* set the PHY Loopback bit */
39657 PhyCtrl |= PHY_CT_LOOP;
39658-
39659-#ifdef XXX
39660- /* Program PHY register 16 as 16'h0400 to force link good */
39661- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, PHY_M_PC_FL_GOOD);
39662-#endif /* XXX */
39663-
39664-#ifndef VCPU
39665- if (pPrt->PLinkSpeed != SK_LSPEED_AUTO) {
39666- /* Write Ext. PHY Specific Control */
39667- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_CTRL,
39668- (SK_U16)((pPrt->PLinkSpeed + 2) << 4));
39669- }
39670-#endif /* VCPU */
39671- }
39672-#ifdef TEST_ONLY
39673- else if (pPrt->PLinkSpeed == SK_LSPEED_10MBPS) {
39674- /* Write PHY Specific Control */
39675- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL,
39676- PHY_M_PC_EN_DET_MSK);
39677 }
39678-#endif
39679+#endif /* !SK_SLIM */
39680
39681 /* Write to the PHY Control register */
39682 SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PhyCtrl);
39683 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39684- ("Set PHY Ctrl Reg.=0x%04X\n", PhyCtrl));
39685+ ("Set PHY Ctrl Reg. = 0x%04X\n", PhyCtrl));
39686
39687 #ifdef VCPU
39688 VCpuWait(2000);
39689-#else
39690+#else /* !VCPU */
39691+
39692+ LedCtrl = PHY_M_LED_PULS_DUR(PULS_170MS);
39693+
39694+ LedOver = 0;
39695+
39696+ BlinkCtrl = pAC->GIni.GILedBlinkCtrl;
39697+
39698+ if ((BlinkCtrl & SK_ACT_LED_BLINK) != 0) {
39699+
39700+ if (ChipId == CHIP_ID_YUKON_FE) {
39701+ /* on 88E3082 these bits are at 11..9 (shifted left) */
39702+ LedCtrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
39703+
39704+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_FE_LED_PAR, &Word);
39705+
39706+ /* delete ACT LED control bits */
39707+ Word &= ~PHY_M_FELP_LED1_MSK;
39708+ /* change ACT LED control to blink mode */
39709+ Word |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
39710+
39711+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_FE_LED_PAR, Word);
39712+ }
39713+ else if (ChipId == CHIP_ID_YUKON_XL || ChipId == CHIP_ID_YUKON_EC_U) {
39714+ /* save page register */
39715+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_ADR, &PageReg);
39716+
39717+ /* select page 3 to access LED control register */
39718+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 3);
39719+
39720+ LedConf = PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
39721+ PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
39722+ PHY_M_LEDC_STA0_CTRL(7); /* 1000 Mbps */
39723
39724- LedCtrl = PHY_M_LED_PULS_DUR(PULS_170MS) | PHY_M_LED_BLINK_RT(BLINK_84MS);
39725+ Mode = 7; /* 10 Mbps: On */
39726
39727- if ((pAC->GIni.GILedBlinkCtrl & SK_ACT_LED_BLINK) != 0) {
39728- LedCtrl |= PHY_M_LEDC_RX_CTRL | PHY_M_LEDC_TX_CTRL;
39729+ if (ChipId == CHIP_ID_YUKON_XL) {
39730+ /* set Polarity Control register */
39731+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_STAT, (SK_U16)
39732+ (PHY_M_POLC_LS1_P_MIX(4) | PHY_M_POLC_IS0_P_MIX(4) |
39733+ PHY_M_POLC_LOS_CTRL(2) | PHY_M_POLC_INIT_CTRL(2) |
39734+ PHY_M_POLC_STA1_CTRL(2) | PHY_M_POLC_STA0_CTRL(2)));
39735+ }
39736+ else if (ChipId == CHIP_ID_YUKON_EC_U) {
39737+ /* check for LINK_LED mux */
39738+ if ((BlinkCtrl & SK_LED_LINK_MUX_P60) != 0) {
39739+
39740+ SK_IN16(pAC, GPHY_CTRL, &Word);
39741+
39742+ Word |= GPC_LED_CONF_VAL(4);
39743+
39744+ /* set GPHY LED Config */
39745+ SK_OUT16(pAC, GPHY_CTRL, Word);
39746+ }
39747+ else {
39748+ Mode = 8; /* Forced Off */
39749+ }
39750+
39751+ /* set Blink Rate in LED Timer Control Register */
39752+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK,
39753+ LedCtrl | (SK_U16)PHY_M_LED_BLINK_RT(BLINK_84MS));
39754+ }
39755+
39756+ LedConf |= PHY_M_LEDC_INIT_CTRL(Mode);
39757+
39758+ /* set LED Function Control register */
39759+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, LedConf);
39760+
39761+#if (defined(SK_DIAG) || (defined(DEBUG) && !defined(SK_SLIM)))
39762+ /* select page 6 to access Packet Generation register */
39763+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 6);
39764+
39765+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &PhyCtrl);
39766+
39767+ PhyCtrl |= BIT_4S; /* enable CRC checker */
39768+
39769+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, PhyCtrl);
39770+#endif /* SK_DIAG || (DEBUG && !SK_SLIM) */
39771+
39772+ /* restore page register */
39773+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, PageReg);
39774+ }
39775+ else {
39776+ /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
39777+ LedCtrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
39778+
39779+ /* on PHY 88E1111 there is a change for LED control */
39780+ if (ChipId == CHIP_ID_YUKON_EC &&
39781+ (BlinkCtrl & SK_DUAL_LED_ACT_LNK) != 0) {
39782+ /* Yukon-EC needs setting of 2 bits: 0,6=11) */
39783+ LedCtrl |= PHY_M_LEDC_TX_C_LSB;
39784+ }
39785+ /* turn off the Rx LED (LED_RX) */
39786+ LedOver |= PHY_M_LED_MO_RX(MO_LED_OFF);
39787+ }
39788 }
39789
39790- if ((pAC->GIni.GILedBlinkCtrl & SK_DUP_LED_NORMAL) != 0) {
39791+ if ((BlinkCtrl & SK_DUP_LED_NORMAL) != 0) {
39792+ /* disable blink mode (LED_DUPLEX) on collisions */
39793 LedCtrl |= PHY_M_LEDC_DP_CTRL;
39794 }
39795-
39796- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_LED_CTRL, LedCtrl);
39797
39798- if ((pAC->GIni.GILedBlinkCtrl & SK_LED_LINK100_ON) != 0) {
39799- /* only in forced 100 Mbps mode */
39800- if (!AutoNeg && pPrt->PLinkSpeed == SK_LSPEED_100MBPS) {
39801+ if (ChipId == CHIP_ID_YUKON_EC_U) {
39802+ if (pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A1) {
39803+ /* apply fixes in PHY AFE */
39804+ SkGmPhyWrite(pAC, IoC, Port, 22, 255);
39805+ /* increase differential signal amplitude in 10BASE-T */
39806+ SkGmPhyWrite(pAC, IoC, Port, 24, 0xaa99);
39807+ SkGmPhyWrite(pAC, IoC, Port, 23, 0x2011);
39808+
39809+ /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
39810+ SkGmPhyWrite(pAC, IoC, Port, 24, 0xa204);
39811+ SkGmPhyWrite(pAC, IoC, Port, 23, 0x2002);
39812+
39813+ /* set page register to 0 */
39814+ SkGmPhyWrite(pAC, IoC, Port, 22, 0);
39815+ }
39816+ }
39817+ else {
39818+ /* no effect on Yukon-XL */
39819+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_LED_CTRL, LedCtrl);
39820+
39821+#ifndef SK_SLIM
39822+ if ((BlinkCtrl & SK_LED_LINK100_ON) != 0) {
39823+ /* only in forced 100 Mbps mode */
39824+ if (!AutoNeg && pPrt->PLinkSpeed == SK_LSPEED_100MBPS) {
39825+ /* turn on 100 Mbps LED (LED_LINK100) */
39826+ LedOver |= PHY_M_LED_MO_100(MO_LED_ON);
39827+ }
39828+ }
39829+#endif /* !SK_SLIM */
39830
39831- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_LED_OVER,
39832- PHY_M_LED_MO_100(MO_LED_ON));
39833+ if (LedOver != 0) {
39834+ /* set Manual LED Override */
39835+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_LED_OVER, LedOver);
39836 }
39837 }
39838
39839 #ifdef SK_DIAG
39840- c_print("Set PHY Ctrl=0x%04X\n", PhyCtrl);
39841- c_print("Set 1000 B-T=0x%04X\n", C1000BaseT);
39842- c_print("Set Auto-Neg=0x%04X\n", AutoNegAdv);
39843- c_print("Set Ext Ctrl=0x%04X\n", ExtPhyCtrl);
39844+ c_print("Set PHY Ctrl = 0x%04X\n", PhyCtrl);
39845+ c_print("Set 1000 B-T = 0x%04X\n", C1000BaseT);
39846+ c_print("Set Auto-Neg = 0x%04X\n", AutoNegAdv);
39847+ c_print("Set Ext Ctrl = 0x%04X\n", ExtPhyCtrl);
39848 #endif /* SK_DIAG */
39849
39850-#if defined(SK_DIAG) || defined(DEBUG)
39851+#if (defined(SK_DIAG) || (defined(DEBUG) && !defined(SK_SLIM)))
39852 /* Read PHY Control */
39853 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &PhyCtrl);
39854 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39855- ("PHY Ctrl Reg.=0x%04X\n", PhyCtrl));
39856-
39857- /* Read 1000Base-T Control Register */
39858- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_CTRL, &C1000BaseT);
39859- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39860- ("1000B-T Ctrl =0x%04X\n", C1000BaseT));
39861-
39862+ ("PHY Ctrl Reg. = 0x%04X\n", PhyCtrl));
39863+
39864 /* Read AutoNeg Advertisement Register */
39865 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_ADV, &AutoNegAdv);
39866 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39867- ("Auto-Neg.Adv.=0x%04X\n", AutoNegAdv));
39868-
39869- /* Read Ext. PHY Specific Control */
39870- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl);
39871- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39872- ("Ext. PHY Ctrl=0x%04X\n", ExtPhyCtrl));
39873-
39874+ ("Auto-Neg.Adv. = 0x%04X\n", AutoNegAdv));
39875+
39876+ if (ChipId != CHIP_ID_YUKON_FE) {
39877+ /* Read 1000Base-T Control Register */
39878+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_CTRL, &C1000BaseT);
39879+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39880+ ("1000B-T Ctrl = 0x%04X\n", C1000BaseT));
39881+
39882+ /* Read Ext. PHY Specific Control */
39883+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl);
39884+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39885+ ("Ext. PHY Ctrl = 0x%04X\n", ExtPhyCtrl));
39886+ }
39887+
39888 /* Read PHY Status */
39889 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_STAT, &PhyStat);
39890 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39891- ("PHY Stat Reg.=0x%04X\n", PhyStat));
39892+ ("PHY Stat Reg. = 0x%04X\n", PhyStat));
39893+
39894 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_STAT, &PhyStat1);
39895 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39896- ("PHY Stat Reg.=0x%04X\n", PhyStat1));
39897-
39898+ ("PHY Stat Reg. = 0x%04X\n", PhyStat1));
39899+
39900 /* Read PHY Specific Status */
39901 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &PhySpecStat);
39902 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39903- ("PHY Spec Stat=0x%04X\n", PhySpecStat));
39904-#endif /* SK_DIAG || DEBUG */
39905+ ("PHY Spec Stat = 0x%04X\n", PhySpecStat));
39906+#endif /* SK_DIAG || (DEBUG && !SK_SLIM) */
39907
39908 #ifdef SK_DIAG
39909- c_print("PHY Ctrl Reg=0x%04X\n", PhyCtrl);
39910- c_print("PHY 1000 Reg=0x%04X\n", C1000BaseT);
39911- c_print("PHY AnAd Reg=0x%04X\n", AutoNegAdv);
39912- c_print("Ext Ctrl Reg=0x%04X\n", ExtPhyCtrl);
39913- c_print("PHY Stat Reg=0x%04X\n", PhyStat);
39914- c_print("PHY Stat Reg=0x%04X\n", PhyStat1);
39915- c_print("PHY Spec Reg=0x%04X\n", PhySpecStat);
39916+ c_print("PHY Ctrl Reg = 0x%04X\n", PhyCtrl);
39917+ c_print("PHY 1000 Reg = 0x%04X\n", C1000BaseT);
39918+ c_print("PHY AnAd Reg = 0x%04X\n", AutoNegAdv);
39919+ c_print("Ext Ctrl Reg = 0x%04X\n", ExtPhyCtrl);
39920+ c_print("PHY Stat Reg = 0x%04X\n", PhyStat);
39921+ c_print("PHY Stat Reg = 0x%04X\n", PhyStat1);
39922+ c_print("PHY Spec Reg = 0x%04X\n", PhySpecStat);
39923 #endif /* SK_DIAG */
39924
39925-#endif /* VCPU */
39926+ /* enable PHY interrupts */
39927+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, (SK_U16)PHY_M_DEF_MSK);
39928+#endif /* !VCPU */
39929
39930 } /* SkGmInitPhyMarv */
39931 #endif /* YUKON */
39932@@ -2419,9 +3326,9 @@
39933 #ifdef OTHER_PHY
39934 /******************************************************************************
39935 *
39936- * SkXmInitPhyLone() - Initialize the Level One Phy registers
39937+ * SkXmInitPhyLone() - Initialize the Level One PHY registers
39938 *
39939- * Description: initializes all the Level One Phy registers
39940+ * Description: initializes all the Level One PHY registers
39941 *
39942 * Note:
39943 *
39944@@ -2429,10 +3336,10 @@
39945 * nothing
39946 */
39947 static void SkXmInitPhyLone(
39948-SK_AC *pAC, /* adapter context */
39949-SK_IOC IoC, /* IO context */
39950+SK_AC *pAC, /* Adapter Context */
39951+SK_IOC IoC, /* I/O Context */
39952 int Port, /* Port Index (MAC_1 + n) */
39953-SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */
39954+SK_BOOL DoLoop) /* Should a PHY LoopBack be set-up? */
39955 {
39956 SK_GEPORT *pPrt;
39957 SK_U16 Ctrl1;
39958@@ -2448,7 +3355,7 @@
39959 /* manually Master/Slave ? */
39960 if (pPrt->PMSMode != SK_MS_MODE_AUTO) {
39961 Ctrl2 |= PHY_L_1000C_MSE;
39962-
39963+
39964 if (pPrt->PMSMode == SK_MS_MODE_MASTER) {
39965 Ctrl2 |= PHY_L_1000C_MSC;
39966 }
39967@@ -2461,7 +3368,7 @@
39968 */
39969 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39970 ("InitPhyLone: no auto-negotiation Port %d\n", Port));
39971- /* Set DuplexMode in Config register */
39972+ /* set DuplexMode in Config register */
39973 if (pPrt->PLinkMode == SK_LMODE_FULL) {
39974 Ctrl1 |= PHY_CT_DUP_MD;
39975 }
39976@@ -2470,7 +3377,6 @@
39977 if (pPrt->PMSMode == SK_MS_MODE_AUTO) {
39978 Ctrl2 |= PHY_L_1000C_MSE; /* set it to Slave */
39979 }
39980-
39981 /*
39982 * Do NOT enable Auto-negotiation here. This would hold
39983 * the link down because no IDLES are transmitted
39984@@ -2479,9 +3385,9 @@
39985 else {
39986 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
39987 ("InitPhyLone: with auto-negotiation Port %d\n", Port));
39988- /* Set Auto-negotiation advertisement */
39989+ /* set Auto-negotiation advertisement */
39990
39991- /* Set Full/half duplex capabilities */
39992+ /* set Full/half duplex capabilities */
39993 switch (pPrt->PLinkMode) {
39994 case SK_LMODE_AUTOHALF:
39995 Ctrl2 |= PHY_L_1000C_AHD;
39996@@ -2497,7 +3403,7 @@
39997 SKERR_HWI_E015MSG);
39998 }
39999
40000- /* Set Flow-control capabilities */
40001+ /* set Flow-control capabilities */
40002 switch (pPrt->PFlowCtrlMode) {
40003 case SK_FLOW_MODE_NONE:
40004 Ctrl3 |= PHY_L_P_NO_PAUSE;
40005@@ -2519,34 +3425,34 @@
40006 /* Restart Auto-negotiation */
40007 Ctrl1 = PHY_CT_ANE | PHY_CT_RE_CFG;
40008 }
40009-
40010+
40011 /* Write 1000Base-T Control Register */
40012 SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_1000T_CTRL, Ctrl2);
40013 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40014- ("1000B-T Ctrl Reg=0x%04X\n", Ctrl2));
40015-
40016+ ("1000B-T Ctrl Reg = 0x%04X\n", Ctrl2));
40017+
40018 /* Write AutoNeg Advertisement Register */
40019 SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_AUNE_ADV, Ctrl3);
40020 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40021- ("Auto-Neg.Adv.Reg=0x%04X\n", Ctrl3));
40022+ ("Auto-Neg.Adv.Reg = 0x%04X\n", Ctrl3));
40023
40024 if (DoLoop) {
40025- /* Set the Phy Loopback bit, too */
40026+ /* set the PHY Loopback bit, too */
40027 Ctrl1 |= PHY_CT_LOOP;
40028 }
40029
40030- /* Write to the Phy control register */
40031+ /* Write to the PHY control register */
40032 SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_CTRL, Ctrl1);
40033 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40034- ("PHY Control Reg=0x%04X\n", Ctrl1));
40035+ ("PHY Control Reg = 0x%04X\n", Ctrl1));
40036 } /* SkXmInitPhyLone */
40037
40038
40039 /******************************************************************************
40040 *
40041- * SkXmInitPhyNat() - Initialize the National Phy registers
40042+ * SkXmInitPhyNat() - Initialize the National PHY registers
40043 *
40044- * Description: initializes all the National Phy registers
40045+ * Description: initializes all the National PHY registers
40046 *
40047 * Note:
40048 *
40049@@ -2554,10 +3460,10 @@
40050 * nothing
40051 */
40052 static void SkXmInitPhyNat(
40053-SK_AC *pAC, /* adapter context */
40054-SK_IOC IoC, /* IO context */
40055+SK_AC *pAC, /* Adapter Context */
40056+SK_IOC IoC, /* I/O Context */
40057 int Port, /* Port Index (MAC_1 + n) */
40058-SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */
40059+SK_BOOL DoLoop) /* Should a PHY LoopBack be set-up? */
40060 {
40061 /* todo: National */
40062 } /* SkXmInitPhyNat */
40063@@ -2576,10 +3482,10 @@
40064 * nothing
40065 */
40066 void SkMacInitPhy(
40067-SK_AC *pAC, /* adapter context */
40068-SK_IOC IoC, /* IO context */
40069+SK_AC *pAC, /* Adapter Context */
40070+SK_IOC IoC, /* I/O Context */
40071 int Port, /* Port Index (MAC_1 + n) */
40072-SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */
40073+SK_BOOL DoLoop) /* Should a PHY LoopBack be set-up? */
40074 {
40075 SK_GEPORT *pPrt;
40076
40077@@ -2587,7 +3493,7 @@
40078
40079 #ifdef GENESIS
40080 if (pAC->GIni.GIGenesis) {
40081-
40082+
40083 switch (pPrt->PhyType) {
40084 case SK_PHY_XMAC:
40085 SkXmInitPhyXmac(pAC, IoC, Port, DoLoop);
40086@@ -2606,10 +3512,10 @@
40087 }
40088 }
40089 #endif /* GENESIS */
40090-
40091+
40092 #ifdef YUKON
40093 if (pAC->GIni.GIYukon) {
40094-
40095+
40096 SkGmInitPhyMarv(pAC, IoC, Port, DoLoop);
40097 }
40098 #endif /* YUKON */
40099@@ -2627,17 +3533,17 @@
40100 *
40101 * Returns:
40102 * SK_AND_OK o.k.
40103- * SK_AND_DUP_CAP Duplex capability error happened
40104- * SK_AND_OTHER Other error happened
40105+ * SK_AND_DUP_CAP Duplex capability error happened
40106+ * SK_AND_OTHER Other error happened
40107 */
40108 static int SkXmAutoNegDoneXmac(
40109-SK_AC *pAC, /* adapter context */
40110-SK_IOC IoC, /* IO context */
40111+SK_AC *pAC, /* Adapter Context */
40112+SK_IOC IoC, /* I/O Context */
40113 int Port) /* Port Index (MAC_1 + n) */
40114 {
40115 SK_GEPORT *pPrt;
40116 SK_U16 ResAb; /* Resolved Ability */
40117- SK_U16 LPAb; /* Link Partner Ability */
40118+ SK_U16 LinkPartAb; /* Link Partner Ability */
40119
40120 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40121 ("AutoNegDoneXmac, Port %d\n", Port));
40122@@ -2645,15 +3551,15 @@
40123 pPrt = &pAC->GIni.GP[Port];
40124
40125 /* Get PHY parameters */
40126- SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_AUNE_LP, &LPAb);
40127+ SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_AUNE_LP, &LinkPartAb);
40128 SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_RES_ABI, &ResAb);
40129
40130- if ((LPAb & PHY_X_AN_RFB) != 0) {
40131+ if ((LinkPartAb & PHY_X_AN_RFB) != 0) {
40132 /* At least one of the remote fault bit is set */
40133- /* Error */
40134- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40135+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
40136 ("AutoNegFail: Remote fault bit set Port %d\n", Port));
40137 pPrt->PAutoNegFail = SK_TRUE;
40138+
40139 return(SK_AND_OTHER);
40140 }
40141
40142@@ -2666,9 +3572,10 @@
40143 }
40144 else {
40145 /* Error */
40146- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40147+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
40148 ("AutoNegFail: Duplex mode mismatch Port %d\n", Port));
40149 pPrt->PAutoNegFail = SK_TRUE;
40150+
40151 return(SK_AND_DUP_CAP);
40152 }
40153
40154@@ -2676,25 +3583,26 @@
40155 /* We are NOT using chapter 4.23 of the Xaqti manual */
40156 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
40157 if ((pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYMMETRIC ||
40158- pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM) &&
40159- (LPAb & PHY_X_P_SYM_MD) != 0) {
40160+ pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM) &&
40161+ (LinkPartAb & PHY_X_P_SYM_MD) != 0) {
40162 /* Symmetric PAUSE */
40163 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC;
40164 }
40165 else if (pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM &&
40166- (LPAb & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD) {
40167- /* Enable PAUSE receive, disable PAUSE transmit */
40168+ (LinkPartAb & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD) {
40169+ /* enable PAUSE receive, disable PAUSE transmit */
40170 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND;
40171 }
40172 else if (pPrt->PFlowCtrlMode == SK_FLOW_MODE_LOC_SEND &&
40173- (LPAb & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD) {
40174- /* Disable PAUSE receive, enable PAUSE transmit */
40175+ (LinkPartAb & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD) {
40176+ /* disable PAUSE receive, enable PAUSE transmit */
40177 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND;
40178 }
40179 else {
40180 /* PAUSE mismatch -> no PAUSE */
40181 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
40182 }
40183+
40184 pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_1000MBPS;
40185
40186 return(SK_AND_OK);
40187@@ -2710,41 +3618,40 @@
40188 *
40189 * Returns:
40190 * SK_AND_OK o.k.
40191- * SK_AND_DUP_CAP Duplex capability error happened
40192- * SK_AND_OTHER Other error happened
40193+ * SK_AND_DUP_CAP Duplex capability error happened
40194+ * SK_AND_OTHER Other error happened
40195 */
40196 static int SkXmAutoNegDoneBcom(
40197-SK_AC *pAC, /* adapter context */
40198-SK_IOC IoC, /* IO context */
40199+SK_AC *pAC, /* Adapter Context */
40200+SK_IOC IoC, /* I/O Context */
40201 int Port) /* Port Index (MAC_1 + n) */
40202 {
40203 SK_GEPORT *pPrt;
40204- SK_U16 LPAb; /* Link Partner Ability */
40205- SK_U16 AuxStat; /* Auxiliary Status */
40206-
40207 #ifdef TEST_ONLY
40208-01-Sep-2000 RA;:;:
40209 SK_U16 ResAb; /* Resolved Ability */
40210-#endif /* 0 */
40211+#endif
40212+ SK_U16 LinkPartAb; /* Link Partner Ability */
40213+ SK_U16 AuxStat; /* Auxiliary Status */
40214+
40215
40216 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40217 ("AutoNegDoneBcom, Port %d\n", Port));
40218 pPrt = &pAC->GIni.GP[Port];
40219
40220 /* Get PHY parameters */
40221- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &LPAb);
40222+ SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &LinkPartAb);
40223 #ifdef TEST_ONLY
40224-01-Sep-2000 RA;:;:
40225 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &ResAb);
40226-#endif /* 0 */
40227-
40228+#endif
40229+
40230 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_STAT, &AuxStat);
40231
40232- if ((LPAb & PHY_B_AN_RF) != 0) {
40233+ if ((LinkPartAb & PHY_B_AN_RF) != 0) {
40234 /* Remote fault bit is set: Error */
40235- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40236+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
40237 ("AutoNegFail: Remote fault bit set Port %d\n", Port));
40238 pPrt->PAutoNegFail = SK_TRUE;
40239+
40240 return(SK_AND_OTHER);
40241 }
40242
40243@@ -2757,26 +3664,26 @@
40244 }
40245 else {
40246 /* Error */
40247- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40248+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
40249 ("AutoNegFail: Duplex mode mismatch Port %d\n", Port));
40250 pPrt->PAutoNegFail = SK_TRUE;
40251+
40252 return(SK_AND_DUP_CAP);
40253 }
40254-
40255+
40256 #ifdef TEST_ONLY
40257-01-Sep-2000 RA;:;:
40258 /* Check Master/Slave resolution */
40259 if ((ResAb & PHY_B_1000S_MSF) != 0) {
40260- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40261+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
40262 ("Master/Slave Fault Port %d\n", Port));
40263 pPrt->PAutoNegFail = SK_TRUE;
40264 pPrt->PMSStatus = SK_MS_STAT_FAULT;
40265 return(SK_AND_OTHER);
40266 }
40267-
40268+
40269 pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
40270 SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE;
40271-#endif /* 0 */
40272+#endif
40273
40274 /* Check PAUSE mismatch ??? */
40275 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
40276@@ -2785,17 +3692,18 @@
40277 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC;
40278 }
40279 else if ((AuxStat & PHY_B_AS_PAUSE_MSK) == PHY_B_AS_PRR) {
40280- /* Enable PAUSE receive, disable PAUSE transmit */
40281+ /* enable PAUSE receive, disable PAUSE transmit */
40282 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND;
40283 }
40284 else if ((AuxStat & PHY_B_AS_PAUSE_MSK) == PHY_B_AS_PRT) {
40285- /* Disable PAUSE receive, enable PAUSE transmit */
40286+ /* disable PAUSE receive, enable PAUSE transmit */
40287 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND;
40288 }
40289 else {
40290 /* PAUSE mismatch -> no PAUSE */
40291 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
40292 }
40293+
40294 pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_1000MBPS;
40295
40296 return(SK_AND_OK);
40297@@ -2813,99 +3721,181 @@
40298 *
40299 * Returns:
40300 * SK_AND_OK o.k.
40301- * SK_AND_DUP_CAP Duplex capability error happened
40302- * SK_AND_OTHER Other error happened
40303+ * SK_AND_DUP_CAP Duplex capability error happened
40304+ * SK_AND_OTHER Other error happened
40305 */
40306 static int SkGmAutoNegDoneMarv(
40307-SK_AC *pAC, /* adapter context */
40308-SK_IOC IoC, /* IO context */
40309+SK_AC *pAC, /* Adapter Context */
40310+SK_IOC IoC, /* I/O Context */
40311 int Port) /* Port Index (MAC_1 + n) */
40312 {
40313 SK_GEPORT *pPrt;
40314- SK_U16 LPAb; /* Link Partner Ability */
40315 SK_U16 ResAb; /* Resolved Ability */
40316 SK_U16 AuxStat; /* Auxiliary Status */
40317+ SK_U8 PauseMode; /* Pause Mode */
40318+#ifndef SK_SLIM
40319+ SK_U16 LinkPartAb; /* Link Partner Ability */
40320+#ifndef SK_DIAG
40321+ SK_EVPARA Para;
40322+#endif /* !SK_DIAG */
40323+#endif /* !SK_SLIM */
40324+
40325+ /* set Pause On */
40326+ PauseMode = (SK_U8)GMC_PAUSE_ON;
40327
40328 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40329 ("AutoNegDoneMarv, Port %d\n", Port));
40330+
40331 pPrt = &pAC->GIni.GP[Port];
40332
40333 /* Get PHY parameters */
40334- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_LP, &LPAb);
40335+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_LP, &LinkPartAb);
40336 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40337- ("Link P.Abil.=0x%04X\n", LPAb));
40338-
40339- if ((LPAb & PHY_M_AN_RF) != 0) {
40340- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40341+ ("Link P.Abil. = 0x%04X\n", LinkPartAb));
40342+
40343+ if ((LinkPartAb & PHY_M_AN_RF) != 0) {
40344+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
40345 ("AutoNegFail: Remote fault bit set Port %d\n", Port));
40346 pPrt->PAutoNegFail = SK_TRUE;
40347+
40348 return(SK_AND_OTHER);
40349 }
40350
40351- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_STAT, &ResAb);
40352-
40353- /* Check Master/Slave resolution */
40354- if ((ResAb & PHY_B_1000S_MSF) != 0) {
40355- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40356- ("Master/Slave Fault Port %d\n", Port));
40357- pPrt->PAutoNegFail = SK_TRUE;
40358- pPrt->PMSStatus = SK_MS_STAT_FAULT;
40359- return(SK_AND_OTHER);
40360+#ifndef SK_SLIM
40361+ if (pAC->GIni.GICopperType) {
40362+ /* Read PHY Auto-Negotiation Expansion */
40363+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_EXP, &LinkPartAb);
40364+
40365+ if ((LinkPartAb & PHY_ANE_LP_CAP) == 0) {
40366+
40367+#ifndef SK_DIAG
40368+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40369+ ("Link Partner not Auto-Neg. able, AN Exp.: 0x%04X\n",
40370+ LinkPartAb));
40371+
40372+#ifndef NDIS_MINIPORT_DRIVER
40373+ SK_ERR_LOG(pAC, SK_ERRCL_CONFIG, SKERR_HWI_E025, SKERR_HWI_E025MSG);
40374+#endif
40375+
40376+ Para.Para64 = Port;
40377+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_LIPA_NOT_AN_ABLE, Para);
40378+#else
40379+ c_print("Link Partner not Auto-Neg. able, AN Exp.: 0x%04X\n",
40380+ LinkPartAb);
40381+#endif /* !SK_DIAG */
40382+
40383+ if (HW_FEATURE(pAC, HWF_FORCE_AUTO_NEG) &&
40384+ pPrt->PLinkModeConf < SK_LMODE_AUTOHALF) {
40385+ /* set used link speed */
40386+ pPrt->PLinkSpeedUsed = pPrt->PLinkSpeed;
40387+
40388+ /* Set Link Mode Status */
40389+ pPrt->PLinkModeStatus = (pPrt->PLinkModeConf == SK_LMODE_FULL) ?
40390+ SK_LMODE_STAT_FULL : SK_LMODE_STAT_HALF;
40391+
40392+ return(SK_AND_OK);
40393+ }
40394+ }
40395 }
40396-
40397- pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
40398- (SK_U8)SK_MS_STAT_MASTER : (SK_U8)SK_MS_STAT_SLAVE;
40399-
40400+#endif /* !SK_SLIM */
40401+
40402+ if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
40403+
40404+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_STAT, &ResAb);
40405+
40406+ /* Check Master/Slave resolution */
40407+ if ((ResAb & PHY_B_1000S_MSF) != 0) {
40408+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
40409+ ("Master/Slave Fault Port %d\n", Port));
40410+ pPrt->PAutoNegFail = SK_TRUE;
40411+ pPrt->PMSStatus = SK_MS_STAT_FAULT;
40412+ return(SK_AND_OTHER);
40413+ }
40414+
40415+ pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
40416+ (SK_U8)SK_MS_STAT_MASTER : (SK_U8)SK_MS_STAT_SLAVE;
40417+ }
40418+
40419 /* Read PHY Specific Status */
40420 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &AuxStat);
40421-
40422+
40423 /* Check Speed & Duplex resolved */
40424 if ((AuxStat & PHY_M_PS_SPDUP_RES) == 0) {
40425- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40426+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
40427 ("AutoNegFail: Speed & Duplex not resolved, Port %d\n", Port));
40428 pPrt->PAutoNegFail = SK_TRUE;
40429 pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN;
40430+
40431 return(SK_AND_DUP_CAP);
40432 }
40433-
40434- if ((AuxStat & PHY_M_PS_FULL_DUP) != 0) {
40435- pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_AUTOFULL;
40436- }
40437- else {
40438- pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_AUTOHALF;
40439- }
40440-
40441- /* Check PAUSE mismatch ??? */
40442- /* We are using IEEE 802.3z/D5.0 Table 37-4 */
40443- if ((AuxStat & PHY_M_PS_PAUSE_MSK) == PHY_M_PS_PAUSE_MSK) {
40444- /* Symmetric PAUSE */
40445- pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC;
40446- }
40447- else if ((AuxStat & PHY_M_PS_PAUSE_MSK) == PHY_M_PS_RX_P_EN) {
40448- /* Enable PAUSE receive, disable PAUSE transmit */
40449- pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND;
40450- }
40451- else if ((AuxStat & PHY_M_PS_PAUSE_MSK) == PHY_M_PS_TX_P_EN) {
40452- /* Disable PAUSE receive, enable PAUSE transmit */
40453- pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND;
40454+
40455+ pPrt->PLinkModeStatus = (SK_U8)(((AuxStat & PHY_M_PS_FULL_DUP) != 0) ?
40456+ SK_LMODE_STAT_AUTOFULL : SK_LMODE_STAT_AUTOHALF);
40457+
40458+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) {
40459+ /* set used link speed */
40460+ pPrt->PLinkSpeedUsed = (SK_U8)(((AuxStat & PHY_M_PS_SPEED_100) != 0) ?
40461+ SK_LSPEED_STAT_100MBPS : SK_LSPEED_STAT_10MBPS);
40462 }
40463 else {
40464- /* PAUSE mismatch -> no PAUSE */
40465- pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
40466+ /* set used link speed */
40467+ switch ((unsigned)(AuxStat & PHY_M_PS_SPEED_MSK)) {
40468+ case (unsigned)PHY_M_PS_SPEED_1000:
40469+ pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_1000MBPS;
40470+ break;
40471+ case PHY_M_PS_SPEED_100:
40472+ pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_100MBPS;
40473+ break;
40474+ default:
40475+ pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_10MBPS;
40476+ }
40477+
40478+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL ||
40479+ pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) {
40480+ /* Tx & Rx Pause Enabled bits are at 9..8 */
40481+ AuxStat >>= 6;
40482+
40483+ if (!pAC->GIni.GICopperType) {
40484+ /* always 1000 Mbps on fiber */
40485+ pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_1000MBPS;
40486+ }
40487+ }
40488+
40489+ AuxStat &= PHY_M_PS_PAUSE_MSK;
40490+ /* We are using IEEE 802.3z/D5.0 Table 37-4 */
40491+ if (AuxStat == PHY_M_PS_PAUSE_MSK) {
40492+ /* Symmetric PAUSE */
40493+ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC;
40494+ }
40495+ else if (AuxStat == PHY_M_PS_RX_P_EN) {
40496+ /* enable PAUSE receive, disable PAUSE transmit */
40497+ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND;
40498+ }
40499+ else if (AuxStat == PHY_M_PS_TX_P_EN) {
40500+ /* disable PAUSE receive, enable PAUSE transmit */
40501+ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND;
40502+ }
40503+ else {
40504+ /* PAUSE mismatch -> no PAUSE */
40505+ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
40506+ }
40507 }
40508-
40509- /* set used link speed */
40510- switch ((unsigned)(AuxStat & PHY_M_PS_SPEED_MSK)) {
40511- case (unsigned)PHY_M_PS_SPEED_1000:
40512- pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_1000MBPS;
40513- break;
40514- case PHY_M_PS_SPEED_100:
40515- pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_100MBPS;
40516- break;
40517- default:
40518- pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_10MBPS;
40519+
40520+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40521+ ("LinkSpeedUsed = %d\n", pPrt->PLinkSpeedUsed));
40522+
40523+ if ((pPrt->PFlowCtrlStatus == SK_FLOW_STAT_NONE) ||
40524+ /* disable Pause also for 10/100 Mbps in half duplex mode */
40525+ ((pAC->GIni.GIChipId != CHIP_ID_YUKON_EC_U) &&
40526+ (pPrt->PLinkSpeedUsed < (SK_U8)SK_LSPEED_STAT_1000MBPS) &&
40527+ pPrt->PLinkModeStatus == (SK_U8)SK_LMODE_STAT_AUTOHALF)) {
40528+
40529+ /* set Pause Off */
40530+ PauseMode = (SK_U8)GMC_PAUSE_OFF;
40531 }
40532
40533+ SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), PauseMode);
40534+
40535 return(SK_AND_OK);
40536 } /* SkGmAutoNegDoneMarv */
40537 #endif /* YUKON */
40538@@ -2921,17 +3911,17 @@
40539 *
40540 * Returns:
40541 * SK_AND_OK o.k.
40542- * SK_AND_DUP_CAP Duplex capability error happened
40543- * SK_AND_OTHER Other error happened
40544+ * SK_AND_DUP_CAP Duplex capability error happened
40545+ * SK_AND_OTHER Other error happened
40546 */
40547 static int SkXmAutoNegDoneLone(
40548-SK_AC *pAC, /* adapter context */
40549-SK_IOC IoC, /* IO context */
40550+SK_AC *pAC, /* Adapter Context */
40551+SK_IOC IoC, /* I/O Context */
40552 int Port) /* Port Index (MAC_1 + n) */
40553 {
40554 SK_GEPORT *pPrt;
40555 SK_U16 ResAb; /* Resolved Ability */
40556- SK_U16 LPAb; /* Link Partner Ability */
40557+ SK_U16 LinkPartAb; /* Link Partner Ability */
40558 SK_U16 QuickStat; /* Auxiliary Status */
40559
40560 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40561@@ -2939,16 +3929,16 @@
40562 pPrt = &pAC->GIni.GP[Port];
40563
40564 /* Get PHY parameters */
40565- SkXmPhyRead(pAC, IoC, Port, PHY_LONE_AUNE_LP, &LPAb);
40566+ SkXmPhyRead(pAC, IoC, Port, PHY_LONE_AUNE_LP, &LinkPartAb);
40567 SkXmPhyRead(pAC, IoC, Port, PHY_LONE_1000T_STAT, &ResAb);
40568 SkXmPhyRead(pAC, IoC, Port, PHY_LONE_Q_STAT, &QuickStat);
40569
40570- if ((LPAb & PHY_L_AN_RF) != 0) {
40571+ if ((LinkPartAb & PHY_L_AN_RF) != 0) {
40572 /* Remote fault bit is set */
40573- /* Error */
40574- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40575+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
40576 ("AutoNegFail: Remote fault bit set Port %d\n", Port));
40577 pPrt->PAutoNegFail = SK_TRUE;
40578+
40579 return(SK_AND_OTHER);
40580 }
40581
40582@@ -2959,28 +3949,25 @@
40583 else {
40584 pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_AUTOHALF;
40585 }
40586-
40587+
40588 /* Check Master/Slave resolution */
40589 if ((ResAb & PHY_L_1000S_MSF) != 0) {
40590 /* Error */
40591- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40592+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
40593 ("Master/Slave Fault Port %d\n", Port));
40594 pPrt->PAutoNegFail = SK_TRUE;
40595 pPrt->PMSStatus = SK_MS_STAT_FAULT;
40596 return(SK_AND_OTHER);
40597 }
40598- else if (ResAb & PHY_L_1000S_MSR) {
40599- pPrt->PMSStatus = SK_MS_STAT_MASTER;
40600- }
40601- else {
40602- pPrt->PMSStatus = SK_MS_STAT_SLAVE;
40603- }
40604+
40605+ pPrt->PMSStatus = ((ResAb & PHY_L_1000S_MSR) != 0) ?
40606+ (SK_U8)SK_MS_STAT_MASTER : (SK_U8)SK_MS_STAT_SLAVE;
40607
40608 /* Check PAUSE mismatch */
40609 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
40610 /* we must manually resolve the abilities here */
40611 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
40612-
40613+
40614 switch (pPrt->PFlowCtrlMode) {
40615 case SK_FLOW_MODE_NONE:
40616 /* default */
40617@@ -2988,7 +3975,7 @@
40618 case SK_FLOW_MODE_LOC_SEND:
40619 if ((QuickStat & (PHY_L_QS_PAUSE | PHY_L_QS_AS_PAUSE)) ==
40620 (PHY_L_QS_PAUSE | PHY_L_QS_AS_PAUSE)) {
40621- /* Disable PAUSE receive, enable PAUSE transmit */
40622+ /* disable PAUSE receive, enable PAUSE transmit */
40623 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND;
40624 }
40625 break;
40626@@ -3001,7 +3988,7 @@
40627 case SK_FLOW_MODE_SYM_OR_REM:
40628 if ((QuickStat & (PHY_L_QS_PAUSE | PHY_L_QS_AS_PAUSE)) ==
40629 PHY_L_QS_AS_PAUSE) {
40630- /* Enable PAUSE receive, disable PAUSE transmit */
40631+ /* enable PAUSE receive, disable PAUSE transmit */
40632 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND;
40633 }
40634 else if ((QuickStat & PHY_L_QS_PAUSE) != 0) {
40635@@ -3013,103 +4000,238 @@
40636 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E016,
40637 SKERR_HWI_E016MSG);
40638 }
40639-
40640- return(SK_AND_OK);
40641-} /* SkXmAutoNegDoneLone */
40642+
40643+ return(SK_AND_OK);
40644+} /* SkXmAutoNegDoneLone */
40645+
40646+
40647+/******************************************************************************
40648+ *
40649+ * SkXmAutoNegDoneNat() - Auto-negotiation handling
40650+ *
40651+ * Description:
40652+ * This function handles the auto-negotiation if the Done bit is set.
40653+ *
40654+ * Returns:
40655+ * SK_AND_OK o.k.
40656+ * SK_AND_DUP_CAP Duplex capability error happened
40657+ * SK_AND_OTHER Other error happened
40658+ */
40659+static int SkXmAutoNegDoneNat(
40660+SK_AC *pAC, /* Adapter Context */
40661+SK_IOC IoC, /* I/O Context */
40662+int Port) /* Port Index (MAC_1 + n) */
40663+{
40664+/* todo: National */
40665+ return(SK_AND_OK);
40666+} /* SkXmAutoNegDoneNat */
40667+#endif /* OTHER_PHY */
40668+
40669+
40670+/******************************************************************************
40671+ *
40672+ * SkMacAutoNegDone() - Auto-negotiation handling
40673+ *
40674+ * Description: calls the auto-negotiation done routines dep. on board type
40675+ *
40676+ * Returns:
40677+ * SK_AND_OK o.k.
40678+ * SK_AND_DUP_CAP Duplex capability error happened
40679+ * SK_AND_OTHER Other error happened
40680+ */
40681+int SkMacAutoNegDone(
40682+SK_AC *pAC, /* Adapter Context */
40683+SK_IOC IoC, /* I/O Context */
40684+int Port) /* Port Index (MAC_1 + n) */
40685+{
40686+ SK_GEPORT *pPrt;
40687+ int Rtv;
40688+
40689+ Rtv = SK_AND_OK;
40690+
40691+ pPrt = &pAC->GIni.GP[Port];
40692+
40693+#ifdef GENESIS
40694+ if (pAC->GIni.GIGenesis) {
40695+
40696+ switch (pPrt->PhyType) {
40697+
40698+ case SK_PHY_XMAC:
40699+ Rtv = SkXmAutoNegDoneXmac(pAC, IoC, Port);
40700+ break;
40701+ case SK_PHY_BCOM:
40702+ Rtv = SkXmAutoNegDoneBcom(pAC, IoC, Port);
40703+ break;
40704+#ifdef OTHER_PHY
40705+ case SK_PHY_LONE:
40706+ Rtv = SkXmAutoNegDoneLone(pAC, IoC, Port);
40707+ break;
40708+ case SK_PHY_NAT:
40709+ Rtv = SkXmAutoNegDoneNat(pAC, IoC, Port);
40710+ break;
40711+#endif /* OTHER_PHY */
40712+ default:
40713+ return(SK_AND_OTHER);
40714+ }
40715+ }
40716+#endif /* GENESIS */
40717+
40718+#ifdef YUKON
40719+ if (pAC->GIni.GIYukon) {
40720+
40721+ Rtv = SkGmAutoNegDoneMarv(pAC, IoC, Port);
40722+ }
40723+#endif /* YUKON */
40724+
40725+ if (Rtv != SK_AND_OK) {
40726+ return(Rtv);
40727+ }
40728+
40729+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40730+ ("AutoNeg done Port %d\n", Port));
40731+
40732+ /* We checked everything and may now enable the link */
40733+ pPrt->PAutoNegFail = SK_FALSE;
40734+
40735+ SkMacRxTxEnable(pAC, IoC, Port);
40736+
40737+ return(SK_AND_OK);
40738+} /* SkMacAutoNegDone */
40739+
40740+
40741+#ifndef SK_SLIM
40742+#ifdef GENESIS
40743+/******************************************************************************
40744+ *
40745+ * SkXmSetRxTxEn() - Special Set Rx/Tx Enable and some features in XMAC
40746+ *
40747+ * Description:
40748+ * sets MAC or PHY LoopBack and Duplex Mode in the MMU Command Reg.
40749+ * enables Rx/Tx
40750+ *
40751+ * Returns: N/A
40752+ */
40753+static void SkXmSetRxTxEn(
40754+SK_AC *pAC, /* Adapter Context */
40755+SK_IOC IoC, /* I/O Context */
40756+int Port, /* Port Index (MAC_1 + n) */
40757+int Para) /* Parameter to set: MAC or PHY LoopBack, Duplex Mode */
40758+{
40759+ SK_U16 Word;
40760+
40761+ XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
40762+
40763+ switch (Para & (SK_MAC_LOOPB_ON | SK_MAC_LOOPB_OFF)) {
40764+ case SK_MAC_LOOPB_ON:
40765+ Word |= XM_MMU_MAC_LB;
40766+ break;
40767+ case SK_MAC_LOOPB_OFF:
40768+ Word &= ~XM_MMU_MAC_LB;
40769+ break;
40770+ }
40771+
40772+ switch (Para & (SK_PHY_LOOPB_ON | SK_PHY_LOOPB_OFF)) {
40773+ case SK_PHY_LOOPB_ON:
40774+ Word |= XM_MMU_GMII_LOOP;
40775+ break;
40776+ case SK_PHY_LOOPB_OFF:
40777+ Word &= ~XM_MMU_GMII_LOOP;
40778+ break;
40779+ }
40780+
40781+ switch (Para & (SK_PHY_FULLD_ON | SK_PHY_FULLD_OFF)) {
40782+ case SK_PHY_FULLD_ON:
40783+ Word |= XM_MMU_GMII_FD;
40784+ break;
40785+ case SK_PHY_FULLD_OFF:
40786+ Word &= ~XM_MMU_GMII_FD;
40787+ break;
40788+ }
40789+
40790+ XM_OUT16(IoC, Port, XM_MMU_CMD, Word | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
40791+
40792+ /* dummy read to ensure writing */
40793+ XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
40794+
40795+} /* SkXmSetRxTxEn */
40796+#endif /* GENESIS */
40797
40798
40799+#ifdef YUKON
40800 /******************************************************************************
40801 *
40802- * SkXmAutoNegDoneNat() - Auto-negotiation handling
40803+ * SkGmSetRxTxEn() - Special Set Rx/Tx Enable and some features in GMAC
40804 *
40805 * Description:
40806- * This function handles the auto-negotiation if the Done bit is set.
40807+ * sets MAC LoopBack and Duplex Mode in the General Purpose Control Reg.
40808+ * enables Rx/Tx
40809 *
40810- * Returns:
40811- * SK_AND_OK o.k.
40812- * SK_AND_DUP_CAP Duplex capability error happened
40813- * SK_AND_OTHER Other error happened
40814+ * Returns: N/A
40815 */
40816-static int SkXmAutoNegDoneNat(
40817-SK_AC *pAC, /* adapter context */
40818-SK_IOC IoC, /* IO context */
40819-int Port) /* Port Index (MAC_1 + n) */
40820+static void SkGmSetRxTxEn(
40821+SK_AC *pAC, /* Adapter Context */
40822+SK_IOC IoC, /* I/O Context */
40823+int Port, /* Port Index (MAC_1 + n) */
40824+int Para) /* Parameter to set: MAC LoopBack, Duplex Mode */
40825 {
40826-/* todo: National */
40827- return(SK_AND_OK);
40828-} /* SkXmAutoNegDoneNat */
40829-#endif /* OTHER_PHY */
40830+ SK_U16 Ctrl;
40831+
40832+ GM_IN16(IoC, Port, GM_GP_CTRL, &Ctrl);
40833+
40834+ switch (Para & (SK_MAC_LOOPB_ON | SK_MAC_LOOPB_OFF)) {
40835+ case SK_MAC_LOOPB_ON:
40836+ Ctrl |= GM_GPCR_LOOP_ENA;
40837+ break;
40838+ case SK_MAC_LOOPB_OFF:
40839+ Ctrl &= ~GM_GPCR_LOOP_ENA;
40840+ break;
40841+ }
40842+
40843+ switch (Para & (SK_PHY_FULLD_ON | SK_PHY_FULLD_OFF)) {
40844+ case SK_PHY_FULLD_ON:
40845+ Ctrl |= GM_GPCR_DUP_FULL;
40846+ break;
40847+ case SK_PHY_FULLD_OFF:
40848+ Ctrl &= ~GM_GPCR_DUP_FULL;
40849+ break;
40850+ }
40851+
40852+ GM_OUT16(IoC, Port, GM_GP_CTRL, Ctrl | GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
40853+
40854+} /* SkGmSetRxTxEn */
40855+#endif /* YUKON */
40856
40857
40858 /******************************************************************************
40859 *
40860- * SkMacAutoNegDone() - Auto-negotiation handling
40861+ * SkMacSetRxTxEn() - Special Set Rx/Tx Enable and parameters
40862 *
40863- * Description: calls the auto-negotiation done routines dep. on board type
40864+ * Description: calls the Special Set Rx/Tx Enable routines dep. on board type
40865 *
40866- * Returns:
40867- * SK_AND_OK o.k.
40868- * SK_AND_DUP_CAP Duplex capability error happened
40869- * SK_AND_OTHER Other error happened
40870+ * Returns: N/A
40871 */
40872-int SkMacAutoNegDone(
40873-SK_AC *pAC, /* adapter context */
40874-SK_IOC IoC, /* IO context */
40875-int Port) /* Port Index (MAC_1 + n) */
40876+void SkMacSetRxTxEn(
40877+SK_AC *pAC, /* Adapter Context */
40878+SK_IOC IoC, /* I/O Context */
40879+int Port, /* Port Index (MAC_1 + n) */
40880+int Para)
40881 {
40882- SK_GEPORT *pPrt;
40883- int Rtv;
40884-
40885- Rtv = SK_AND_OK;
40886-
40887- pPrt = &pAC->GIni.GP[Port];
40888-
40889 #ifdef GENESIS
40890 if (pAC->GIni.GIGenesis) {
40891-
40892- switch (pPrt->PhyType) {
40893-
40894- case SK_PHY_XMAC:
40895- Rtv = SkXmAutoNegDoneXmac(pAC, IoC, Port);
40896- break;
40897- case SK_PHY_BCOM:
40898- Rtv = SkXmAutoNegDoneBcom(pAC, IoC, Port);
40899- break;
40900-#ifdef OTHER_PHY
40901- case SK_PHY_LONE:
40902- Rtv = SkXmAutoNegDoneLone(pAC, IoC, Port);
40903- break;
40904- case SK_PHY_NAT:
40905- Rtv = SkXmAutoNegDoneNat(pAC, IoC, Port);
40906- break;
40907-#endif /* OTHER_PHY */
40908- default:
40909- return(SK_AND_OTHER);
40910- }
40911+
40912+ SkXmSetRxTxEn(pAC, IoC, Port, Para);
40913 }
40914 #endif /* GENESIS */
40915-
40916+
40917 #ifdef YUKON
40918 if (pAC->GIni.GIYukon) {
40919-
40920- Rtv = SkGmAutoNegDoneMarv(pAC, IoC, Port);
40921+
40922+ SkGmSetRxTxEn(pAC, IoC, Port, Para);
40923 }
40924 #endif /* YUKON */
40925-
40926- if (Rtv != SK_AND_OK) {
40927- return(Rtv);
40928- }
40929-
40930- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
40931- ("AutoNeg done Port %d\n", Port));
40932-
40933- /* We checked everything and may now enable the link */
40934- pPrt->PAutoNegFail = SK_FALSE;
40935
40936- SkMacRxTxEnable(pAC, IoC, Port);
40937-
40938- return(SK_AND_OK);
40939-} /* SkMacAutoNegDone */
40940+} /* SkMacSetRxTxEn */
40941+#endif /* !SK_SLIM */
40942
40943
40944 /******************************************************************************
40945@@ -3123,8 +4245,8 @@
40946 * != 0 Error happened
40947 */
40948 int SkMacRxTxEnable(
40949-SK_AC *pAC, /* adapter context */
40950-SK_IOC IoC, /* IO context */
40951+SK_AC *pAC, /* Adapter Context */
40952+SK_IOC IoC, /* I/O Context */
40953 int Port) /* Port Index (MAC_1 + n) */
40954 {
40955 SK_GEPORT *pPrt;
40956@@ -3142,9 +4264,9 @@
40957 }
40958
40959 if ((pPrt->PLinkMode == SK_LMODE_AUTOHALF ||
40960- pPrt->PLinkMode == SK_LMODE_AUTOFULL ||
40961- pPrt->PLinkMode == SK_LMODE_AUTOBOTH) &&
40962- pPrt->PAutoNegFail) {
40963+ pPrt->PLinkMode == SK_LMODE_AUTOFULL ||
40964+ pPrt->PLinkMode == SK_LMODE_AUTOBOTH) &&
40965+ pPrt->PAutoNegFail) {
40966 /* Auto-negotiation is not done or failed */
40967 return(0);
40968 }
40969@@ -3153,9 +4275,9 @@
40970 if (pAC->GIni.GIGenesis) {
40971 /* set Duplex Mode and Pause Mode */
40972 SkXmInitDupMd(pAC, IoC, Port);
40973-
40974+
40975 SkXmInitPauseMd(pAC, IoC, Port);
40976-
40977+
40978 /*
40979 * Initialize the Interrupt Mask Register. Default IRQs are...
40980 * - Link Asynchronous Event
40981@@ -3171,23 +4293,24 @@
40982 /* add IRQ for Receive FIFO Overflow */
40983 IntMask &= ~XM_IS_RXF_OV;
40984 #endif /* DEBUG */
40985-
40986+
40987 if (pPrt->PhyType != SK_PHY_XMAC) {
40988 /* disable GP0 interrupt bit */
40989 IntMask |= XM_IS_INP_ASS;
40990 }
40991+
40992 XM_OUT16(IoC, Port, XM_IMSK, IntMask);
40993-
40994+
40995 /* get MMU Command Reg. */
40996 XM_IN16(IoC, Port, XM_MMU_CMD, &Reg);
40997-
40998+
40999 if (pPrt->PhyType != SK_PHY_XMAC &&
41000 (pPrt->PLinkModeStatus == SK_LMODE_STAT_FULL ||
41001 pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOFULL)) {
41002 /* set to Full Duplex */
41003 Reg |= XM_MMU_GMII_FD;
41004 }
41005-
41006+
41007 switch (pPrt->PhyType) {
41008 case SK_PHY_BCOM:
41009 /*
41010@@ -3197,7 +4320,7 @@
41011 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &SWord);
41012 SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUX_CTRL,
41013 (SK_U16)(SWord & ~PHY_B_AC_DIS_PM));
41014- SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_INT_MASK,
41015+ SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_INT_MASK,
41016 (SK_U16)PHY_B_DEF_MSK);
41017 break;
41018 #ifdef OTHER_PHY
41019@@ -3211,12 +4334,12 @@
41020 break;
41021 #endif /* OTHER_PHY */
41022 }
41023-
41024+
41025 /* enable Rx/Tx */
41026 XM_OUT16(IoC, Port, XM_MMU_CMD, Reg | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
41027 }
41028 #endif /* GENESIS */
41029-
41030+
41031 #ifdef YUKON
41032 if (pAC->GIni.GIYukon) {
41033 /*
41034@@ -3227,34 +4350,46 @@
41035 */
41036 IntMask = GMAC_DEF_MSK;
41037
41038-#ifdef DEBUG
41039+#if (defined(DEBUG) || defined(YUK2)) && (!defined(SK_SLIM))
41040 /* add IRQ for Receive FIFO Overrun */
41041 IntMask |= GM_IS_RX_FF_OR;
41042-#endif /* DEBUG */
41043-
41044- SK_OUT8(IoC, GMAC_IRQ_MSK, (SK_U8)IntMask);
41045-
41046+#endif
41047+
41048+ SK_OUT8(IoC, MR_ADDR(Port, GMAC_IRQ_MSK), (SK_U8)IntMask);
41049+
41050 /* get General Purpose Control */
41051 GM_IN16(IoC, Port, GM_GP_CTRL, &Reg);
41052-
41053+
41054 if (pPrt->PLinkModeStatus == SK_LMODE_STAT_FULL ||
41055 pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOFULL) {
41056 /* set to Full Duplex */
41057 Reg |= GM_GPCR_DUP_FULL;
41058+
41059+#ifndef SK_SLIM
41060+ if (HW_FEATURE(pAC, HWF_FORCE_AUTO_NEG) &&
41061+ pPrt->PLinkModeConf < SK_LMODE_AUTOHALF) {
41062+ /* disable auto-update for speed, duplex and flow-control */
41063+ Reg |= GM_GPCR_AU_ALL_DIS;
41064+ }
41065+#endif /* !SK_SLIM */
41066 }
41067-
41068- /* enable Rx/Tx */
41069- GM_OUT16(IoC, Port, GM_GP_CTRL, (SK_U16)(Reg | GM_GPCR_RX_ENA |
41070- GM_GPCR_TX_ENA));
41071
41072-#ifndef VCPU
41073- /* Enable all PHY interrupts */
41074- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK,
41075- (SK_U16)PHY_M_DEF_MSK);
41076-#endif /* VCPU */
41077+ /* WA for dev. #4.209 */
41078+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U &&
41079+ pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A1) {
41080+ /* enable/disable Store & Forward mode for TX */
41081+ SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_CTRL_T),
41082+ pPrt->PLinkSpeedUsed != (SK_U8)SK_LSPEED_STAT_1000MBPS ?
41083+ TX_STFW_ENA : TX_STFW_DIS);
41084+ }
41085+
41086+ /* enable Rx/Tx */
41087+ GM_OUT16(IoC, Port, GM_GP_CTRL, Reg | GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
41088 }
41089 #endif /* YUKON */
41090-
41091+
41092+ pAC->GIni.GP[Port].PState = SK_PRT_RUN;
41093+
41094 return(0);
41095
41096 } /* SkMacRxTxEnable */
41097@@ -3270,33 +4405,33 @@
41098 */
41099 void SkMacRxTxDisable(
41100 SK_AC *pAC, /* Adapter Context */
41101-SK_IOC IoC, /* IO context */
41102+SK_IOC IoC, /* I/O Context */
41103 int Port) /* Port Index (MAC_1 + n) */
41104 {
41105 SK_U16 Word;
41106
41107 #ifdef GENESIS
41108 if (pAC->GIni.GIGenesis) {
41109-
41110+
41111 XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
41112-
41113- XM_OUT16(IoC, Port, XM_MMU_CMD, Word & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
41114-
41115+
41116+ Word &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
41117+
41118+ XM_OUT16(IoC, Port, XM_MMU_CMD, Word);
41119+
41120 /* dummy read to ensure writing */
41121 XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
41122 }
41123 #endif /* GENESIS */
41124-
41125+
41126 #ifdef YUKON
41127 if (pAC->GIni.GIYukon) {
41128-
41129+
41130 GM_IN16(IoC, Port, GM_GP_CTRL, &Word);
41131
41132- GM_OUT16(IoC, Port, GM_GP_CTRL, (SK_U16)(Word & ~(GM_GPCR_RX_ENA |
41133- GM_GPCR_TX_ENA)));
41134+ Word &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
41135
41136- /* dummy read to ensure writing */
41137- GM_IN16(IoC, Port, GM_GP_CTRL, &Word);
41138+ GM_OUT16(IoC, Port, GM_GP_CTRL, Word);
41139 }
41140 #endif /* YUKON */
41141
41142@@ -3313,7 +4448,7 @@
41143 */
41144 void SkMacIrqDisable(
41145 SK_AC *pAC, /* Adapter Context */
41146-SK_IOC IoC, /* IO context */
41147+SK_IOC IoC, /* I/O Context */
41148 int Port) /* Port Index (MAC_1 + n) */
41149 {
41150 SK_GEPORT *pPrt;
41151@@ -3325,18 +4460,18 @@
41152
41153 #ifdef GENESIS
41154 if (pAC->GIni.GIGenesis) {
41155-
41156+
41157 /* disable all XMAC IRQs */
41158- XM_OUT16(IoC, Port, XM_IMSK, 0xffff);
41159-
41160- /* Disable all PHY interrupts */
41161+ XM_OUT16(IoC, Port, XM_IMSK, 0xffff);
41162+
41163+ /* disable all PHY interrupts */
41164 switch (pPrt->PhyType) {
41165 case SK_PHY_BCOM:
41166 /* Make sure that PHY is initialized */
41167 if (pPrt->PState != SK_PRT_RESET) {
41168 /* NOT allowed if BCOM is in RESET state */
41169 /* Workaround BCOM Errata (#10523) all BCom */
41170- /* Disable Power Management if link is down */
41171+ /* disable Power Management if link is down */
41172 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &Word);
41173 SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUX_CTRL,
41174 (SK_U16)(Word | PHY_B_AC_DIS_PM));
41175@@ -3355,16 +4490,16 @@
41176 }
41177 }
41178 #endif /* GENESIS */
41179-
41180+
41181 #ifdef YUKON
41182 if (pAC->GIni.GIYukon) {
41183 /* disable all GMAC IRQs */
41184- SK_OUT8(IoC, GMAC_IRQ_MSK, 0);
41185-
41186+ SK_OUT8(IoC, MR_ADDR(Port, GMAC_IRQ_MSK), 0);
41187+
41188 #ifndef VCPU
41189- /* Disable all PHY interrupts */
41190+ /* disable all PHY interrupts */
41191 SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, 0);
41192-#endif /* VCPU */
41193+#endif /* !VCPU */
41194 }
41195 #endif /* YUKON */
41196
41197@@ -3376,29 +4511,72 @@
41198 *
41199 * SkXmSendCont() - Enable / Disable Send Continuous Mode
41200 *
41201- * Description: enable / disable Send Continuous Mode on XMAC
41202+ * Description: enable / disable Send Continuous Mode on XMAC resp.
41203+ * Packet Generation on GPHY
41204 *
41205 * Returns:
41206 * nothing
41207 */
41208 void SkXmSendCont(
41209-SK_AC *pAC, /* adapter context */
41210-SK_IOC IoC, /* IO context */
41211+SK_AC *pAC, /* Adapter Context */
41212+SK_IOC IoC, /* I/O Context */
41213 int Port, /* Port Index (MAC_1 + n) */
41214 SK_BOOL Enable) /* Enable / Disable */
41215 {
41216+ SK_U16 Reg;
41217+ SK_U16 Save;
41218 SK_U32 MdReg;
41219
41220- XM_IN32(IoC, Port, XM_MODE, &MdReg);
41221+ if (pAC->GIni.GIGenesis) {
41222+ XM_IN32(IoC, Port, XM_MODE, &MdReg);
41223
41224- if (Enable) {
41225- MdReg |= XM_MD_TX_CONT;
41226+ if (Enable) {
41227+ MdReg |= XM_MD_TX_CONT;
41228+ }
41229+ else {
41230+ MdReg &= ~XM_MD_TX_CONT;
41231+ }
41232+ /* setup Mode Register */
41233+ XM_OUT32(IoC, Port, XM_MODE, MdReg);
41234 }
41235 else {
41236- MdReg &= ~XM_MD_TX_CONT;
41237+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) {
41238+ /* select page 18 */
41239+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_ADDR, 18);
41240+
41241+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PAGE_DATA, &Reg);
41242+
41243+ Reg &= ~0x003c; /* clear bits 5..2 */
41244+
41245+ if (Enable) {
41246+ /* enable packet generation, 1518 byte length */
41247+ Reg |= (BIT_5S | BIT_3S);
41248+ }
41249+
41250+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, Reg);
41251+ }
41252+ else if (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL) {
41253+ /* save page register */
41254+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_ADR, &Save);
41255+
41256+ /* select page 6 to access Packet Generation register */
41257+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 6);
41258+
41259+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Reg);
41260+
41261+ Reg &= ~0x003f; /* clear bits 5..0 */
41262+
41263+ if (Enable) {
41264+ /* enable packet generation, 1518 byte length */
41265+ Reg |= (BIT_3S | BIT_1S);
41266+ }
41267+
41268+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Reg);
41269+
41270+ /* restore page register */
41271+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, Save);
41272+ }
41273 }
41274- /* setup Mode Register */
41275- XM_OUT32(IoC, Port, XM_MODE, MdReg);
41276
41277 } /* SkXmSendCont */
41278
41279@@ -3413,8 +4591,8 @@
41280 * nothing
41281 */
41282 void SkMacTimeStamp(
41283-SK_AC *pAC, /* adapter context */
41284-SK_IOC IoC, /* IO context */
41285+SK_AC *pAC, /* Adapter Context */
41286+SK_IOC IoC, /* I/O Context */
41287 int Port, /* Port Index (MAC_1 + n) */
41288 SK_BOOL Enable) /* Enable / Disable */
41289 {
41290@@ -3459,8 +4637,8 @@
41291 * is set true.
41292 */
41293 void SkXmAutoNegLipaXmac(
41294-SK_AC *pAC, /* adapter context */
41295-SK_IOC IoC, /* IO context */
41296+SK_AC *pAC, /* Adapter Context */
41297+SK_IOC IoC, /* I/O Context */
41298 int Port, /* Port Index (MAC_1 + n) */
41299 SK_U16 IStatus) /* Interrupt Status word to analyse */
41300 {
41301@@ -3472,8 +4650,9 @@
41302 (IStatus & (XM_IS_LIPA_RC | XM_IS_RX_PAGE | XM_IS_AND)) != 0) {
41303
41304 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
41305- ("AutoNegLipa: AutoNeg detected on Port %d, IStatus=0x%04X\n",
41306+ ("AutoNegLipa: AutoNeg detected on Port %d, IStatus = 0x%04X\n",
41307 Port, IStatus));
41308+
41309 pPrt->PLipaAutoNeg = SK_LIPA_AUTO;
41310 }
41311 } /* SkXmAutoNegLipaXmac */
41312@@ -3489,8 +4668,8 @@
41313 * is set true.
41314 */
41315 void SkMacAutoNegLipaPhy(
41316-SK_AC *pAC, /* adapter context */
41317-SK_IOC IoC, /* IO context */
41318+SK_AC *pAC, /* Adapter Context */
41319+SK_IOC IoC, /* I/O Context */
41320 int Port, /* Port Index (MAC_1 + n) */
41321 SK_U16 PhyStat) /* PHY Status word to analyse */
41322 {
41323@@ -3502,8 +4681,9 @@
41324 (PhyStat & PHY_ST_AN_OVER) != 0) {
41325
41326 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
41327- ("AutoNegLipa: AutoNeg detected on Port %d, PhyStat=0x%04X\n",
41328+ ("AutoNegLipa: AutoNeg detected on Port %d, PhyStat = 0x%04X\n",
41329 Port, PhyStat));
41330+
41331 pPrt->PLipaAutoNeg = SK_LIPA_AUTO;
41332 }
41333 } /* SkMacAutoNegLipaPhy */
41334@@ -3518,7 +4698,7 @@
41335 *
41336 * Note:
41337 * With an external PHY, some interrupt bits are not meaningfull any more:
41338- * - LinkAsyncEvent (bit #14) XM_IS_LNK_AE
41339+ * - LinkAsyncEvent (bit #14) XM_IS_LNK_AE
41340 * - LinkPartnerReqConfig (bit #10) XM_IS_LIPA_RC
41341 * - Page Received (bit #9) XM_IS_RX_PAGE
41342 * - NextPageLoadedForXmt (bit #8) XM_IS_TX_PAGE
41343@@ -3530,22 +4710,23 @@
41344 * nothing
41345 */
41346 static void SkXmIrq(
41347-SK_AC *pAC, /* adapter context */
41348-SK_IOC IoC, /* IO context */
41349+SK_AC *pAC, /* Adapter Context */
41350+SK_IOC IoC, /* I/O Context */
41351 int Port) /* Port Index (MAC_1 + n) */
41352 {
41353 SK_GEPORT *pPrt;
41354- SK_EVPARA Para;
41355 SK_U16 IStatus; /* Interrupt status read from the XMAC */
41356 SK_U16 IStatus2;
41357 #ifdef SK_SLIM
41358- SK_U64 OverflowStatus;
41359-#endif
41360+ SK_U64 OverflowStatus;
41361+#else
41362+ SK_EVPARA Para;
41363+#endif /* SK_SLIM */
41364
41365 pPrt = &pAC->GIni.GP[Port];
41366-
41367+
41368 XM_IN16(IoC, Port, XM_ISRC, &IStatus);
41369-
41370+
41371 /* LinkPartner Auto-negable? */
41372 if (pPrt->PhyType == SK_PHY_XMAC) {
41373 SkXmAutoNegLipaXmac(pAC, IoC, Port, IStatus);
41374@@ -3556,7 +4737,7 @@
41375 XM_IS_RX_PAGE | XM_IS_TX_PAGE |
41376 XM_IS_AND | XM_IS_INP_ASS);
41377 }
41378-
41379+
41380 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
41381 ("XmacIrq Port %d Isr 0x%04X\n", Port, IStatus));
41382
41383@@ -3666,49 +4847,55 @@
41384 * nothing
41385 */
41386 static void SkGmIrq(
41387-SK_AC *pAC, /* adapter context */
41388-SK_IOC IoC, /* IO context */
41389+SK_AC *pAC, /* Adapter Context */
41390+SK_IOC IoC, /* I/O Context */
41391 int Port) /* Port Index (MAC_1 + n) */
41392 {
41393 SK_GEPORT *pPrt;
41394 SK_U8 IStatus; /* Interrupt status */
41395 #ifdef SK_SLIM
41396- SK_U64 OverflowStatus;
41397+ SK_U64 OverflowStatus;
41398 #else
41399 SK_EVPARA Para;
41400-#endif
41401+#endif /* SK_SLIM */
41402
41403 pPrt = &pAC->GIni.GP[Port];
41404-
41405- SK_IN8(IoC, GMAC_IRQ_SRC, &IStatus);
41406-
41407+
41408+ SK_IN8(IoC, MR_ADDR(Port, GMAC_IRQ_SRC), &IStatus);
41409+
41410 #ifdef XXX
41411 /* LinkPartner Auto-negable? */
41412 SkMacAutoNegLipaPhy(pAC, IoC, Port, IStatus);
41413 #endif /* XXX */
41414-
41415+
41416 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
41417- ("GmacIrq Port %d Isr 0x%04X\n", Port, IStatus));
41418+ ("GmacIrq Port %d Isr 0x%02X\n", Port, IStatus));
41419
41420 /* Combined Tx & Rx Counter Overflow SIRQ Event */
41421 if (IStatus & (GM_IS_RX_CO_OV | GM_IS_TX_CO_OV)) {
41422 /* these IRQs will be cleared by reading GMACs register */
41423 #ifdef SK_SLIM
41424- SkGmOverflowStatus(pAC, IoC, Port, IStatus, &OverflowStatus);
41425+ SkGmOverflowStatus(pAC, IoC, Port, (SK_U16)IStatus, &OverflowStatus);
41426 #else
41427 Para.Para32[0] = (SK_U32)Port;
41428 Para.Para32[1] = (SK_U32)IStatus;
41429 SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_SIRQ_OVERFLOW, Para);
41430-#endif
41431+#endif /* SK_SLIM */
41432 }
41433
41434+#ifndef SK_SLIM
41435 if (IStatus & GM_IS_RX_FF_OR) {
41436 /* clear GMAC Rx FIFO Overrun IRQ */
41437 SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_CLI_RX_FO);
41438+
41439+ Para.Para64 = Port;
41440+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_RX_OVERFLOW, Para);
41441+
41442 #ifdef DEBUG
41443 pPrt->PRxOverCnt++;
41444 #endif /* DEBUG */
41445 }
41446+#endif /* !SK_SLIM */
41447
41448 if (IStatus & GM_IS_TX_FF_UR) {
41449 /* clear GMAC Tx FIFO Underrun IRQ */
41450@@ -3738,8 +4925,8 @@
41451 * nothing
41452 */
41453 void SkMacIrq(
41454-SK_AC *pAC, /* adapter context */
41455-SK_IOC IoC, /* IO context */
41456+SK_AC *pAC, /* Adapter Context */
41457+SK_IOC IoC, /* I/O Context */
41458 int Port) /* Port Index (MAC_1 + n) */
41459 {
41460 #ifdef GENESIS
41461@@ -3748,7 +4935,7 @@
41462 SkXmIrq(pAC, IoC, Port);
41463 }
41464 #endif /* GENESIS */
41465-
41466+
41467 #ifdef YUKON
41468 if (pAC->GIni.GIYukon) {
41469 /* IRQ from GMAC */
41470@@ -3775,8 +4962,8 @@
41471 * 1: something went wrong
41472 */
41473 int SkXmUpdateStats(
41474-SK_AC *pAC, /* adapter context */
41475-SK_IOC IoC, /* IO context */
41476+SK_AC *pAC, /* Adapter Context */
41477+SK_IOC IoC, /* I/O Context */
41478 unsigned int Port) /* Port Index (MAC_1 + n) */
41479 {
41480 SK_GEPORT *pPrt;
41481@@ -3798,7 +4985,7 @@
41482 do {
41483
41484 XM_IN16(IoC, Port, XM_STAT_CMD, &StatReg);
41485-
41486+
41487 if (++WaitIndex > 10) {
41488
41489 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E021, SKERR_HWI_E021MSG);
41490@@ -3806,7 +4993,7 @@
41491 return(1);
41492 }
41493 } while ((StatReg & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) != 0);
41494-
41495+
41496 return(0);
41497 } /* SkXmUpdateStats */
41498
41499@@ -3825,19 +5012,19 @@
41500 * 1: something went wrong
41501 */
41502 int SkXmMacStatistic(
41503-SK_AC *pAC, /* adapter context */
41504-SK_IOC IoC, /* IO context */
41505+SK_AC *pAC, /* Adapter Context */
41506+SK_IOC IoC, /* I/O Context */
41507 unsigned int Port, /* Port Index (MAC_1 + n) */
41508 SK_U16 StatAddr, /* MIB counter base address */
41509-SK_U32 SK_FAR *pVal) /* ptr to return statistic value */
41510+SK_U32 SK_FAR *pVal) /* Pointer to return statistic value */
41511 {
41512 if ((StatAddr < XM_TXF_OK) || (StatAddr > XM_RXF_MAX_SZ)) {
41513-
41514+
41515 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E022, SKERR_HWI_E022MSG);
41516-
41517+
41518 return(1);
41519 }
41520-
41521+
41522 XM_IN32(IoC, Port, StatAddr, pVal);
41523
41524 return(0);
41525@@ -3856,12 +5043,12 @@
41526 * 1: something went wrong
41527 */
41528 int SkXmResetCounter(
41529-SK_AC *pAC, /* adapter context */
41530-SK_IOC IoC, /* IO context */
41531+SK_AC *pAC, /* Adapter Context */
41532+SK_IOC IoC, /* I/O Context */
41533 unsigned int Port) /* Port Index (MAC_1 + n) */
41534 {
41535 XM_OUT16(IoC, Port, XM_STAT_CMD, XM_SC_CLR_RXC | XM_SC_CLR_TXC);
41536- /* Clear two times according to Errata #3 */
41537+ /* Clear two times according to XMAC Errata #3 */
41538 XM_OUT16(IoC, Port, XM_STAT_CMD, XM_SC_CLR_RXC | XM_SC_CLR_TXC);
41539
41540 return(0);
41541@@ -3888,11 +5075,11 @@
41542 * 1: something went wrong
41543 */
41544 int SkXmOverflowStatus(
41545-SK_AC *pAC, /* adapter context */
41546-SK_IOC IoC, /* IO context */
41547+SK_AC *pAC, /* Adapter Context */
41548+SK_IOC IoC, /* I/O Context */
41549 unsigned int Port, /* Port Index (MAC_1 + n) */
41550-SK_U16 IStatus, /* Interupt Status from MAC */
41551-SK_U64 SK_FAR *pStatus) /* ptr for return overflow status value */
41552+SK_U16 IStatus, /* Interrupt Status from MAC */
41553+SK_U64 SK_FAR *pStatus) /* Pointer for return overflow status value */
41554 {
41555 SK_U64 Status; /* Overflow status */
41556 SK_U32 RegVal;
41557@@ -3904,7 +5091,7 @@
41558 XM_IN32(IoC, Port, XM_RX_CNT_EV, &RegVal);
41559 Status |= (SK_U64)RegVal << 32;
41560 }
41561-
41562+
41563 if ((IStatus & XM_IS_TXC_OV) != 0) {
41564
41565 XM_IN32(IoC, Port, XM_TX_CNT_EV, &RegVal);
41566@@ -3931,8 +5118,8 @@
41567 * 1: something went wrong
41568 */
41569 int SkGmUpdateStats(
41570-SK_AC *pAC, /* adapter context */
41571-SK_IOC IoC, /* IO context */
41572+SK_AC *pAC, /* Adapter Context */
41573+SK_IOC IoC, /* I/O Context */
41574 unsigned int Port) /* Port Index (MAC_1 + n) */
41575 {
41576 return(0);
41577@@ -3953,24 +5140,27 @@
41578 * 1: something went wrong
41579 */
41580 int SkGmMacStatistic(
41581-SK_AC *pAC, /* adapter context */
41582-SK_IOC IoC, /* IO context */
41583+SK_AC *pAC, /* Adapter Context */
41584+SK_IOC IoC, /* I/O Context */
41585 unsigned int Port, /* Port Index (MAC_1 + n) */
41586 SK_U16 StatAddr, /* MIB counter base address */
41587-SK_U32 SK_FAR *pVal) /* ptr to return statistic value */
41588+SK_U32 SK_FAR *pVal) /* Pointer to return statistic value */
41589 {
41590
41591 if ((StatAddr < GM_RXF_UC_OK) || (StatAddr > GM_TXE_FIFO_UR)) {
41592-
41593+
41594 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E022, SKERR_HWI_E022MSG);
41595-
41596- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
41597+
41598+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
41599 ("SkGmMacStat: wrong MIB counter 0x%04X\n", StatAddr));
41600 return(1);
41601 }
41602-
41603+
41604 GM_IN32(IoC, Port, StatAddr, pVal);
41605
41606+ /* dummy read after GM_IN32() */
41607+ SK_IN16(IoC, B0_RAP, &StatAddr);
41608+
41609 return(0);
41610 } /* SkGmMacStatistic */
41611
41612@@ -3987,11 +5177,11 @@
41613 * 1: something went wrong
41614 */
41615 int SkGmResetCounter(
41616-SK_AC *pAC, /* adapter context */
41617-SK_IOC IoC, /* IO context */
41618+SK_AC *pAC, /* Adapter Context */
41619+SK_IOC IoC, /* I/O Context */
41620 unsigned int Port) /* Port Index (MAC_1 + n) */
41621 {
41622- SK_U16 Reg; /* Phy Address Register */
41623+ SK_U16 Reg; /* PHY Address Register */
41624 SK_U16 Word;
41625 int i;
41626
41627@@ -3999,16 +5189,16 @@
41628
41629 /* set MIB Clear Counter Mode */
41630 GM_OUT16(IoC, Port, GM_PHY_ADDR, Reg | GM_PAR_MIB_CLR);
41631-
41632+
41633 /* read all MIB Counters with Clear Mode set */
41634 for (i = 0; i < GM_MIB_CNT_SIZE; i++) {
41635 /* the reset is performed only when the lower 16 bits are read */
41636 GM_IN16(IoC, Port, GM_MIB_CNT_BASE + 8*i, &Word);
41637 }
41638-
41639+
41640 /* clear MIB Clear Counter Mode */
41641 GM_OUT16(IoC, Port, GM_PHY_ADDR, Reg);
41642-
41643+
41644 return(0);
41645 } /* SkGmResetCounter */
41646
41647@@ -4022,48 +5212,62 @@
41648 * resulting counter overflow status is written to <pStatus>, whereas the
41649 * the following bit coding is used:
41650 * 63:56 - unused
41651- * 55:48 - TxRx interrupt register bit7:0
41652- * 32:47 - Rx interrupt register
41653+ * 55:48 - TxRx interrupt register bit 7:0
41654+ * 47:32 - Rx interrupt register
41655 * 31:24 - unused
41656- * 23:16 - TxRx interrupt register bit15:8
41657- * 15:0 - Tx interrupt register
41658+ * 23:16 - TxRx interrupt register bit 15:8
41659+ * 15: 0 - Tx interrupt register
41660 *
41661 * Returns:
41662 * 0: success
41663 * 1: something went wrong
41664 */
41665 int SkGmOverflowStatus(
41666-SK_AC *pAC, /* adapter context */
41667-SK_IOC IoC, /* IO context */
41668+SK_AC *pAC, /* Adapter Context */
41669+SK_IOC IoC, /* I/O Context */
41670 unsigned int Port, /* Port Index (MAC_1 + n) */
41671-SK_U16 IStatus, /* Interupt Status from MAC */
41672-SK_U64 SK_FAR *pStatus) /* ptr for return overflow status value */
41673+SK_U16 IStatus, /* Interrupt Status from MAC */
41674+SK_U64 SK_FAR *pStatus) /* Pointer for return overflow status value */
41675 {
41676- SK_U64 Status; /* Overflow status */
41677 SK_U16 RegVal;
41678+#ifndef SK_SLIM
41679+ SK_U64 Status; /* Overflow status */
41680
41681 Status = 0;
41682+#endif /* !SK_SLIM */
41683
41684 if ((IStatus & GM_IS_RX_CO_OV) != 0) {
41685 /* this register is self-clearing after read */
41686 GM_IN16(IoC, Port, GM_RX_IRQ_SRC, &RegVal);
41687+
41688+#ifndef SK_SLIM
41689 Status |= (SK_U64)RegVal << 32;
41690+#endif /* !SK_SLIM */
41691 }
41692-
41693+
41694 if ((IStatus & GM_IS_TX_CO_OV) != 0) {
41695 /* this register is self-clearing after read */
41696 GM_IN16(IoC, Port, GM_TX_IRQ_SRC, &RegVal);
41697+
41698+#ifndef SK_SLIM
41699 Status |= (SK_U64)RegVal;
41700+#endif /* !SK_SLIM */
41701 }
41702-
41703+
41704 /* this register is self-clearing after read */
41705 GM_IN16(IoC, Port, GM_TR_IRQ_SRC, &RegVal);
41706+
41707+#ifndef SK_SLIM
41708 /* Rx overflow interrupt register bits (LoByte)*/
41709 Status |= (SK_U64)((SK_U8)RegVal) << 48;
41710 /* Tx overflow interrupt register bits (HiByte)*/
41711 Status |= (SK_U64)(RegVal >> 8) << 16;
41712
41713 *pStatus = Status;
41714+#endif /* !SK_SLIM */
41715+
41716+ /* dummy read after GM_IN16() */
41717+ SK_IN16(IoC, B0_RAP, &RegVal);
41718
41719 return(0);
41720 } /* SkGmOverflowStatus */
41721@@ -4079,60 +5283,124 @@
41722 * gets the results if 'StartTest' is true
41723 *
41724 * NOTE: this test is meaningful only when link is down
41725- *
41726+ *
41727 * Returns:
41728 * 0: success
41729 * 1: no YUKON copper
41730 * 2: test in progress
41731 */
41732 int SkGmCableDiagStatus(
41733-SK_AC *pAC, /* adapter context */
41734-SK_IOC IoC, /* IO context */
41735+SK_AC *pAC, /* Adapter Context */
41736+SK_IOC IoC, /* I/O Context */
41737 int Port, /* Port Index (MAC_1 + n) */
41738 SK_BOOL StartTest) /* flag for start / get result */
41739 {
41740 int i;
41741+ int CableDiagOffs;
41742+ int MdiPairs;
41743+ int Rtv;
41744+ SK_BOOL FastEthernet;
41745+ SK_BOOL Yukon2;
41746 SK_U16 RegVal;
41747 SK_GEPORT *pPrt;
41748
41749 pPrt = &pAC->GIni.GP[Port];
41750
41751 if (pPrt->PhyType != SK_PHY_MARV_COPPER) {
41752-
41753+
41754 return(1);
41755 }
41756
41757+ Yukon2 = pAC->GIni.GIChipId == CHIP_ID_YUKON_XL ||
41758+ pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U;
41759+
41760+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) {
41761+
41762+ CableDiagOffs = PHY_MARV_FE_VCT_TX;
41763+ FastEthernet = SK_TRUE;
41764+ MdiPairs = 2;
41765+ }
41766+ else {
41767+ CableDiagOffs = Yukon2 ? PHY_MARV_PHY_CTRL : PHY_MARV_CABLE_DIAG;
41768+ FastEthernet = SK_FALSE;
41769+ MdiPairs = 4;
41770+ }
41771+
41772 if (StartTest) {
41773+
41774+ /* set to RESET to avoid PortCheckUp */
41775+ pPrt->PState = SK_PRT_RESET;
41776+
41777 /* only start the cable test */
41778- if ((pPrt->PhyId1 & PHY_I1_REV_MSK) < 4) {
41779- /* apply TDR workaround from Marvell */
41780- SkGmPhyWrite(pAC, IoC, Port, 29, 0x001e);
41781-
41782- SkGmPhyWrite(pAC, IoC, Port, 30, 0xcc00);
41783- SkGmPhyWrite(pAC, IoC, Port, 30, 0xc800);
41784- SkGmPhyWrite(pAC, IoC, Port, 30, 0xc400);
41785- SkGmPhyWrite(pAC, IoC, Port, 30, 0xc000);
41786- SkGmPhyWrite(pAC, IoC, Port, 30, 0xc100);
41787+ if (!FastEthernet) {
41788+
41789+ if ((((pPrt->PhyId1 & PHY_I1_MOD_NUM) >> 4) == 2) &&
41790+ ((pPrt->PhyId1 & PHY_I1_REV_MSK) < 4)) {
41791+ /* apply TDR workaround for model 2, rev. < 4 */
41792+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_ADDR, 0x001e);
41793+
41794+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xcc00);
41795+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xc800);
41796+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xc400);
41797+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xc000);
41798+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xc100);
41799+ }
41800+
41801+#ifdef YUKON_DBG
41802+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) {
41803+ /* set address to 1 for page 1 */
41804+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 1);
41805+
41806+ /* disable waiting period */
41807+ SkGmPhyWrite(pAC, IoC, Port, CableDiagOffs,
41808+ PHY_M_CABD_DIS_WAIT);
41809+ }
41810+#endif
41811+ if (Yukon2) {
41812+ /* set address to 5 for page 5 */
41813+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 5);
41814+
41815+#ifdef YUKON_DBG
41816+ /* disable waiting period */
41817+ SkGmPhyWrite(pAC, IoC, Port, CableDiagOffs + 1,
41818+ PHY_M_CABD_DIS_WAIT);
41819+#endif
41820+ }
41821+ else {
41822+ /* set address to 0 for MDI[0] (Page 0) */
41823+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0);
41824+ }
41825 }
41826+ else {
41827+ RegVal = PHY_CT_RESET | PHY_CT_SP100;
41828
41829- /* set address to 0 for MDI[0] */
41830- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0);
41831+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, RegVal);
41832
41833- /* Read Cable Diagnostic Reg */
41834- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CABLE_DIAG, &RegVal);
41835+#ifdef xYUKON_DBG
41836+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_FE_SPEC_2, &RegVal);
41837+ /* disable waiting period */
41838+ RegVal |= PHY_M_FESC_DIS_WAIT;
41839+
41840+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_FE_SPEC_2, RegVal);
41841+#endif
41842+ }
41843
41844 /* start Cable Diagnostic Test */
41845- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CABLE_DIAG,
41846- (SK_U16)(RegVal | PHY_M_CABD_ENA_TEST));
41847-
41848+ SkGmPhyWrite(pAC, IoC, Port, CableDiagOffs, PHY_M_CABD_ENA_TEST);
41849+
41850 return(0);
41851 }
41852-
41853+
41854 /* Read Cable Diagnostic Reg */
41855- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CABLE_DIAG, &RegVal);
41856+ Rtv = SkGmPhyRead(pAC, IoC, Port, CableDiagOffs, &RegVal);
41857+
41858+ if (Rtv == 2) {
41859+ /* PHY read timeout */
41860+ return(3);
41861+ }
41862
41863 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
41864- ("PHY Cable Diag.=0x%04X\n", RegVal));
41865+ ("PHY Cable Diag. = 0x%04X\n", RegVal));
41866
41867 if ((RegVal & PHY_M_CABD_ENA_TEST) != 0) {
41868 /* test is running */
41869@@ -4140,16 +5408,24 @@
41870 }
41871
41872 /* get the test results */
41873- for (i = 0; i < 4; i++) {
41874- /* set address to i for MDI[i] */
41875- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, (SK_U16)i);
41876+ for (i = 0; i < MdiPairs; i++) {
41877+
41878+ if (!FastEthernet && !Yukon2) {
41879+ /* set address to i for MDI[i] */
41880+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, (SK_U16)i);
41881+ }
41882
41883 /* get Cable Diagnostic values */
41884- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CABLE_DIAG, &RegVal);
41885+ SkGmPhyRead(pAC, IoC, Port, CableDiagOffs, &RegVal);
41886
41887 pPrt->PMdiPairLen[i] = (SK_U8)(RegVal & PHY_M_CABD_DIST_MSK);
41888
41889 pPrt->PMdiPairSts[i] = (SK_U8)((RegVal & PHY_M_CABD_STAT_MSK) >> 13);
41890+
41891+ if (FastEthernet || Yukon2) {
41892+ /* get next register */
41893+ CableDiagOffs++;
41894+ }
41895 }
41896
41897 return(0);
41898@@ -4158,3 +5434,4 @@
41899 #endif /* YUKON */
41900
41901 /* End of file */
41902+
41903diff -urN linux-2.6.17.orig/drivers/net/sk98lin/sky2.c linux-2.6.17/drivers/net/sk98lin/sky2.c
41904--- linux-2.6.17.orig/drivers/net/sk98lin/sky2.c 1970-01-01 01:00:00.000000000 +0100
41905+++ linux-2.6.17/drivers/net/sk98lin/sky2.c 2006-04-27 11:43:45.000000000 +0200
41906@@ -0,0 +1,2721 @@
41907+/******************************************************************************
41908+ *
41909+ * Name: sky2.c
41910+ * Project: Yukon2 specific functions and implementations
41911+ * Version: $Revision$
41912+ * Date: $Date$
41913+ * Purpose: The main driver source module
41914+ *
41915+ *****************************************************************************/
41916+
41917+/******************************************************************************
41918+ *
41919+ * (C)Copyright 1998-2002 SysKonnect GmbH.
41920+ * (C)Copyright 2002-2005 Marvell.
41921+ *
41922+ * Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet
41923+ * Server Adapters.
41924+ *
41925+ * Author: Ralph Roesler (rroesler@syskonnect.de)
41926+ * Mirko Lindner (mlindner@syskonnect.de)
41927+ *
41928+ * Address all question to: linux@syskonnect.de
41929+ *
41930+ * This program is free software; you can redistribute it and/or modify
41931+ * it under the terms of the GNU General Public License as published by
41932+ * the Free Software Foundation; either version 2 of the License, or
41933+ * (at your option) any later version.
41934+ *
41935+ * The information in this file is provided "AS IS" without warranty.
41936+ *
41937+ *****************************************************************************/
41938+
41939+#include "h/skdrv1st.h"
41940+#include "h/skdrv2nd.h"
41941+#include <linux/tcp.h>
41942+
41943+/******************************************************************************
41944+ *
41945+ * Local Function Prototypes
41946+ *
41947+ *****************************************************************************/
41948+
41949+static void InitPacketQueues(SK_AC *pAC,int Port);
41950+static void GiveTxBufferToHw(SK_AC *pAC,SK_IOC IoC,int Port);
41951+static void GiveRxBufferToHw(SK_AC *pAC,SK_IOC IoC,int Port,SK_PACKET *pPacket);
41952+static SK_BOOL HandleReceives(SK_AC *pAC,int Port,SK_U16 Len,SK_U32 FrameStatus,SK_U16 Tcp1,SK_U16 Tcp2,SK_U32 Tist,SK_U16 Vlan);
41953+static void CheckForSendComplete(SK_AC *pAC,SK_IOC IoC,int Port,SK_PKT_QUEUE *pPQ,SK_LE_TABLE *pLETab,unsigned int Done);
41954+static void UnmapAndFreeTxPktBuffer(SK_AC *pAC,SK_PACKET *pSkPacket,int TxPort);
41955+static SK_BOOL AllocateAndInitLETables(SK_AC *pAC);
41956+static SK_BOOL AllocatePacketBuffersYukon2(SK_AC *pAC);
41957+static void FreeLETables(SK_AC *pAC);
41958+static void FreePacketBuffers(SK_AC *pAC);
41959+static SK_BOOL AllocAndMapRxBuffer(SK_AC *pAC,SK_PACKET *pSkPacket,int Port);
41960+#ifdef CONFIG_SK98LIN_NAPI
41961+static SK_BOOL HandleStatusLEs(SK_AC *pAC,int *WorkDone,int WorkToDo);
41962+#else
41963+static SK_BOOL HandleStatusLEs(SK_AC *pAC);
41964+#endif
41965+
41966+extern void SkGeCheckTimer (DEV_NET *pNet);
41967+extern void SkLocalEventQueue( SK_AC *pAC,
41968+ SK_U32 Class,
41969+ SK_U32 Event,
41970+ SK_U32 Param1,
41971+ SK_U32 Param2,
41972+ SK_BOOL Flag);
41973+extern void SkLocalEventQueue64( SK_AC *pAC,
41974+ SK_U32 Class,
41975+ SK_U32 Event,
41976+ SK_U64 Param,
41977+ SK_BOOL Flag);
41978+
41979+/******************************************************************************
41980+ *
41981+ * Local Variables
41982+ *
41983+ *****************************************************************************/
41984+
41985+#define MAX_NBR_RX_BUFFERS_IN_HW 0x15
41986+static SK_U8 NbrRxBuffersInHW;
41987+#define FLUSH_OPC(le)
41988+
41989+/******************************************************************************
41990+ *
41991+ * Global Functions
41992+ *
41993+ *****************************************************************************/
41994+
41995+int SkY2Xmit( struct sk_buff *skb, struct SK_NET_DEVICE *dev);
41996+void FillReceiveTableYukon2(SK_AC *pAC,SK_IOC IoC,int Port);
41997+
41998+/*****************************************************************************
41999+ *
42000+ * SkY2RestartStatusUnit - restarts teh status unit
42001+ *
42002+ * Description:
42003+ * Reenables the status unit after any De-Init (e.g. when altering
42004+ * the sie of the MTU via 'ifconfig a.b.c.d mtu xxx')
42005+ *
42006+ * Returns: N/A
42007+ */
42008+void SkY2RestartStatusUnit(
42009+SK_AC *pAC) /* pointer to adapter control context */
42010+{
42011+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42012+ ("==> SkY2RestartStatusUnit\n"));
42013+
42014+ /*
42015+ ** It might be that the TX timer is not started. Therefore
42016+ ** it is initialized here -> to be more investigated!
42017+ */
42018+ SK_OUT32(pAC->IoBase, STAT_TX_TIMER_INI, HW_MS_TO_TICKS(pAC,10));
42019+
42020+ pAC->StatusLETable.Done = 0;
42021+ pAC->StatusLETable.Put = 0;
42022+ pAC->StatusLETable.HwPut = 0;
42023+ SkGeY2InitStatBmu(pAC, pAC->IoBase, &pAC->StatusLETable);
42024+
42025+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42026+ ("<== SkY2RestartStatusUnit\n"));
42027+}
42028+
42029+/*****************************************************************************
42030+ *
42031+ * SkY2RlmtSend - sends out a single RLMT notification
42032+ *
42033+ * Description:
42034+ * This function sends out an RLMT frame
42035+ *
42036+ * Returns:
42037+ * > 0 - on succes: the number of bytes in the message
42038+ * = 0 - on resource shortage: this frame sent or dropped, now
42039+ * the ring is full ( -> set tbusy)
42040+ * < 0 - on failure: other problems ( -> return failure to upper layers)
42041+ */
42042+int SkY2RlmtSend (
42043+SK_AC *pAC, /* pointer to adapter control context */
42044+int PortNr, /* index of port the packet(s) shall be send to */
42045+struct sk_buff *pMessage) /* pointer to send-message */
42046+{
42047+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42048+ ("=== SkY2RlmtSend\n"));
42049+#if 0
42050+ return -1; // temporarily do not send out RLMT frames
42051+#endif
42052+ skb_shinfo(pMessage)->nr_frags = (2*MAX_SKB_FRAGS) + PortNr;
42053+ return(SkY2Xmit(pMessage, pAC->dev[PortNr])); // SkY2Xmit needs device
42054+}
42055+
42056+/*****************************************************************************
42057+ *
42058+ * SkY2AllocateResources - Allocates all required resources for Yukon2
42059+ *
42060+ * Description:
42061+ * This function allocates all memory needed for the Yukon2.
42062+ * It maps also RX buffers to the LETables and initializes the
42063+ * status list element table.
42064+ *
42065+ * Returns:
42066+ * SK_TRUE, if all resources could be allocated and setup succeeded
42067+ * SK_FALSE, if an error
42068+ */
42069+SK_BOOL SkY2AllocateResources (
42070+SK_AC *pAC) /* pointer to adapter control context */
42071+{
42072+ int CurrMac;
42073+
42074+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
42075+ ("==> SkY2AllocateResources\n"));
42076+
42077+ /*
42078+ ** Initialize the packet queue variables first
42079+ */
42080+ for (CurrMac = 0; CurrMac < pAC->GIni.GIMacsFound; CurrMac++) {
42081+ InitPacketQueues(pAC, CurrMac);
42082+ }
42083+
42084+ /*
42085+ ** Get sufficient memory for the LETables
42086+ */
42087+ if (!AllocateAndInitLETables(pAC)) {
42088+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
42089+ SK_DBGCAT_INIT | SK_DBGCAT_DRV_ERROR,
42090+ ("No memory for LETable.\n"));
42091+ return(SK_FALSE);
42092+ }
42093+
42094+ /*
42095+ ** Allocate and intialize memory for both RX and TX
42096+ ** packet and fragment buffers. On an error, free
42097+ ** previously allocated LETable memory and quit.
42098+ */
42099+ if (!AllocatePacketBuffersYukon2(pAC)) {
42100+ FreeLETables(pAC);
42101+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
42102+ SK_DBGCAT_INIT | SK_DBGCAT_DRV_ERROR,
42103+ ("No memory for Packetbuffers.\n"));
42104+ return(SK_FALSE);
42105+ }
42106+
42107+ /*
42108+ ** Rx and Tx LE tables will be initialized in SkGeOpen()
42109+ **
42110+ ** It might be that the TX timer is not started. Therefore
42111+ ** it is initialized here -> to be more investigated!
42112+ */
42113+ SK_OUT32(pAC->IoBase, STAT_TX_TIMER_INI, HW_MS_TO_TICKS(pAC,10));
42114+ SkGeY2InitStatBmu(pAC, pAC->IoBase, &pAC->StatusLETable);
42115+
42116+ pAC->MaxUnusedRxLeWorking = MAX_UNUSED_RX_LE_WORKING;
42117+
42118+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
42119+ ("<== SkY2AllocateResources\n"));
42120+
42121+ return (SK_TRUE);
42122+}
42123+
42124+/*****************************************************************************
42125+ *
42126+ * SkY2FreeResources - Frees previously allocated resources of Yukon2
42127+ *
42128+ * Description:
42129+ * This function frees all previously allocated memory of the Yukon2.
42130+ *
42131+ * Returns: N/A
42132+ */
42133+void SkY2FreeResources (
42134+SK_AC *pAC) /* pointer to adapter control context */
42135+{
42136+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42137+ ("==> SkY2FreeResources\n"));
42138+
42139+ FreeLETables(pAC);
42140+ FreePacketBuffers(pAC);
42141+
42142+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42143+ ("<== SkY2FreeResources\n"));
42144+}
42145+
42146+/*****************************************************************************
42147+ *
42148+ * SkY2AllocateRxBuffers - Allocates the receive buffers for a port
42149+ *
42150+ * Description:
42151+ * This function allocated all the RX buffers of the Yukon2.
42152+ *
42153+ * Returns: N/A
42154+ */
42155+void SkY2AllocateRxBuffers (
42156+SK_AC *pAC, /* pointer to adapter control context */
42157+SK_IOC IoC, /* I/O control context */
42158+int Port) /* port index of RX */
42159+{
42160+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
42161+ ("==> SkY2AllocateRxBuffers (Port %c)\n", Port));
42162+
42163+ FillReceiveTableYukon2(pAC, IoC, Port);
42164+
42165+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
42166+ ("<== SkY2AllocateRxBuffers\n"));
42167+}
42168+
42169+/*****************************************************************************
42170+ *
42171+ * SkY2FreeRxBuffers - Free's all allocates RX buffers of
42172+ *
42173+ * Description:
42174+ * This function frees all RX buffers of the Yukon2 for a single port
42175+ *
42176+ * Returns: N/A
42177+ */
42178+void SkY2FreeRxBuffers (
42179+SK_AC *pAC, /* pointer to adapter control context */
42180+SK_IOC IoC, /* I/O control context */
42181+int Port) /* port index of RX */
42182+{
42183+ SK_PACKET *pSkPacket;
42184+ unsigned long Flags; /* for POP/PUSH macros */
42185+
42186+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42187+ ("==> SkY2FreeRxBuffers (Port %c)\n", Port));
42188+
42189+ if (pAC->RxPort[Port].ReceivePacketTable != NULL) {
42190+ POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_working, pSkPacket);
42191+ while (pSkPacket != NULL) {
42192+ if ((pSkPacket->pFrag) != NULL) {
42193+ pci_unmap_page(pAC->PciDev,
42194+ (dma_addr_t) pSkPacket->pFrag->pPhys,
42195+ pSkPacket->pFrag->FragLen - 2,
42196+ PCI_DMA_FROMDEVICE);
42197+
42198+ /* wipe out any rubbish data that may interfere */
42199+ skb_shinfo(pSkPacket->pMBuf)->nr_frags = 0;
42200+ skb_shinfo(pSkPacket->pMBuf)->frag_list = NULL;
42201+ DEV_KFREE_SKB_ANY(pSkPacket->pMBuf);
42202+ pSkPacket->pMBuf = NULL;
42203+ pSkPacket->pFrag->pPhys = (SK_U64) 0;
42204+ pSkPacket->pFrag->pVirt = NULL;
42205+ }
42206+ PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pSkPacket);
42207+ POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_working, pSkPacket);
42208+ }
42209+ }
42210+
42211+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42212+ ("<== SkY2FreeRxBuffers\n"));
42213+}
42214+
42215+/*****************************************************************************
42216+ *
42217+ * SkY2FreeTxBuffers - Free's any currently maintained Tx buffer
42218+ *
42219+ * Description:
42220+ * This function frees the TX buffers of the Yukon2 for a single port
42221+ * which might be in use by a transmit action
42222+ *
42223+ * Returns: N/A
42224+ */
42225+void SkY2FreeTxBuffers (
42226+SK_AC *pAC, /* pointer to adapter control context */
42227+SK_IOC IoC, /* I/O control context */
42228+int Port) /* port index of TX */
42229+{
42230+ SK_PACKET *pSkPacket;
42231+ SK_FRAG *pSkFrag;
42232+ unsigned long Flags;
42233+
42234+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42235+ ("==> SkY2FreeTxBuffers (Port %c)\n", Port));
42236+
42237+ if (pAC->TxPort[Port][0].TransmitPacketTable != NULL) {
42238+ POP_FIRST_PKT_FROM_QUEUE(&pAC->TxPort[Port][0].TxAQ_working, pSkPacket);
42239+ while (pSkPacket != NULL) {
42240+ if ((pSkFrag = pSkPacket->pFrag) != NULL) {
42241+ UnmapAndFreeTxPktBuffer(pAC, pSkPacket, Port);
42242+ }
42243+ PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->TxPort[Port][0].TxQ_free, pSkPacket);
42244+ POP_FIRST_PKT_FROM_QUEUE(&pAC->TxPort[Port][0].TxAQ_working, pSkPacket);
42245+ }
42246+#if USE_SYNC_TX_QUEUE
42247+ POP_FIRST_PKT_FROM_QUEUE(&pAC->TxPort[Port][0].TxSQ_working, pSkPacket);
42248+ while (pSkPacket != NULL) {
42249+ if ((pSkFrag = pSkPacket->pFrag) != NULL) {
42250+ UnmapAndFreeTxPktBuffer(pAC, pSkPacket, Port);
42251+ }
42252+ PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->TxPort[Port][0].TxQ_free, pSkPacket);
42253+ POP_FIRST_PKT_FROM_QUEUE(&pAC->TxPort[Port][0].TxSQ_working, pSkPacket);
42254+ }
42255+#endif
42256+ }
42257+
42258+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42259+ ("<== SkY2FreeTxBuffers\n"));
42260+}
42261+
42262+/*****************************************************************************
42263+ *
42264+ * SkY2Isr - handle a receive IRQ for all yukon2 cards
42265+ *
42266+ * Description:
42267+ * This function is called when a receive IRQ is set. (only for yukon2)
42268+ * HandleReceives does the deferred processing of all outstanding
42269+ * interrupt operations.
42270+ *
42271+ * Returns: N/A
42272+ */
42273+SkIsrRetVar SkY2Isr (
42274+int irq, /* the irq we have received (might be shared!) */
42275+void *dev_id, /* current device id */
42276+struct pt_regs *ptregs) /* not used by our driver */
42277+{
42278+ struct SK_NET_DEVICE *dev = (struct SK_NET_DEVICE *)dev_id;
42279+ DEV_NET *pNet = (DEV_NET*) dev->priv;
42280+ SK_AC *pAC = pNet->pAC;
42281+ SK_U32 IntSrc;
42282+ unsigned long Flags;
42283+#ifndef CONFIG_SK98LIN_NAPI
42284+ SK_BOOL handledStatLE = SK_FALSE;
42285+#else
42286+ SK_BOOL SetIntMask = SK_FALSE;
42287+#endif
42288+
42289+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
42290+ ("==> SkY2Isr\n"));
42291+
42292+ SK_IN32(pAC->IoBase, B0_Y2_SP_ISRC2, &IntSrc);
42293+
42294+ if ((IntSrc == 0) && (!pNet->NetConsoleMode)){
42295+ SK_OUT32(pAC->IoBase, B0_Y2_SP_ICR, 2);
42296+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
42297+ ("No Interrupt\n ==> SkY2Isr\n"));
42298+ return SkIsrRetNone;
42299+
42300+ }
42301+
42302+#ifdef Y2_RECOVERY
42303+ if (pNet->InRecover) {
42304+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
42305+ ("Already in recover\n ==> SkY2Isr\n"));
42306+ SK_OUT32(pAC->IoBase, B0_Y2_SP_ICR, 2);
42307+ return SkIsrRetNone;
42308+ }
42309+#endif
42310+
42311+#ifdef CONFIG_SK98LIN_NAPI
42312+ if (netif_rx_schedule_prep(pAC->dev[0])) {
42313+ pAC->GIni.GIValIrqMask &= ~(Y2_IS_STAT_BMU);
42314+ SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
42315+ SetIntMask = SK_TRUE;
42316+ __netif_rx_schedule(pAC->dev[0]);
42317+ }
42318+
42319+ if (netif_rx_schedule_prep(pAC->dev[1])) {
42320+ if (!SetIntMask) {
42321+ pAC->GIni.GIValIrqMask &= ~(Y2_IS_STAT_BMU);
42322+ SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
42323+ }
42324+ __netif_rx_schedule(pAC->dev[1]);
42325+ }
42326+#else
42327+ handledStatLE = HandleStatusLEs(pAC);
42328+#endif
42329+
42330+ /*
42331+ ** Check for Special Interrupts
42332+ */
42333+ if ((IntSrc & ~Y2_IS_STAT_BMU) || pAC->CheckQueue || pNet->TimerExpired) {
42334+ pAC->CheckQueue = SK_FALSE;
42335+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
42336+ SkGeSirqIsr(pAC, pAC->IoBase, IntSrc);
42337+ SkEventDispatcher(pAC, pAC->IoBase);
42338+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
42339+ }
42340+
42341+ /* Speed enhancement for a2 chipsets */
42342+ if (HW_FEATURE(pAC, HWF_WA_DEV_42)) {
42343+ spin_lock_irqsave(&pAC->SetPutIndexLock, Flags);
42344+ SkGeY2SetPutIndex(pAC, pAC->IoBase, Y2_PREF_Q_ADDR(Q_XA1,0), &pAC->TxPort[0][0].TxALET);
42345+ SkGeY2SetPutIndex(pAC, pAC->IoBase, Y2_PREF_Q_ADDR(Q_R1,0), &pAC->RxPort[0].RxLET);
42346+ spin_unlock_irqrestore(&pAC->SetPutIndexLock, Flags);
42347+ }
42348+
42349+ /*
42350+ ** Reenable interrupts and signal end of ISR
42351+ */
42352+ SK_OUT32(pAC->IoBase, B0_Y2_SP_ICR, 2);
42353+
42354+ /*
42355+ ** Stop and restart TX timer in case a Status LE was handled
42356+ */
42357+#ifndef CONFIG_SK98LIN_NAPI
42358+ if ((HW_FEATURE(pAC, HWF_WA_DEV_43_418)) && (handledStatLE)) {
42359+ SK_OUT8(pAC->IoBase, STAT_TX_TIMER_CTRL, TIM_STOP);
42360+ SK_OUT8(pAC->IoBase, STAT_TX_TIMER_CTRL, TIM_START);
42361+ }
42362+#endif
42363+
42364+ if (!(IS_Q_EMPTY(&(pAC->TxPort[0][TX_PRIO_LOW].TxAQ_waiting)))) {
42365+ GiveTxBufferToHw(pAC, pAC->IoBase, 0);
42366+ }
42367+ if (!(IS_Q_EMPTY(&(pAC->TxPort[1][TX_PRIO_LOW].TxAQ_waiting)))) {
42368+ GiveTxBufferToHw(pAC, pAC->IoBase, 1);
42369+ }
42370+
42371+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
42372+ ("<== SkY2Isr\n"));
42373+
42374+ return SkIsrRetHandled;
42375+} /* SkY2Isr */
42376+
42377+/*****************************************************************************
42378+ *
42379+ * SkY2Xmit - Linux frame transmit function for Yukon2
42380+ *
42381+ * Description:
42382+ * The system calls this function to send frames onto the wire.
42383+ * It puts the frame in the tx descriptor ring. If the ring is
42384+ * full then, the 'tbusy' flag is set.
42385+ *
42386+ * Returns:
42387+ * 0, if everything is ok
42388+ * !=0, on error
42389+ *
42390+ * WARNING:
42391+ * returning 1 in 'tbusy' case caused system crashes (double
42392+ * allocated skb's) !!!
42393+ */
42394+int SkY2Xmit(
42395+struct sk_buff *skb, /* socket buffer to be sent */
42396+struct SK_NET_DEVICE *dev) /* via which device? */
42397+{
42398+ DEV_NET *pNet = (DEV_NET*) dev->priv;
42399+ SK_AC *pAC = pNet->pAC;
42400+ SK_U8 FragIdx = 0;
42401+ SK_PACKET *pSkPacket;
42402+ SK_FRAG *PrevFrag;
42403+ SK_FRAG *CurrFrag;
42404+ SK_PKT_QUEUE *pWorkQueue; /* corresponding TX queue */
42405+ SK_PKT_QUEUE *pWaitQueue;
42406+ SK_PKT_QUEUE *pFreeQueue;
42407+ SK_LE_TABLE *pLETab; /* corresponding LETable */
42408+ skb_frag_t *sk_frag;
42409+ SK_U64 PhysAddr;
42410+ unsigned long Flags;
42411+ unsigned int Port;
42412+ int CurrFragCtr;
42413+
42414+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
42415+ ("==> SkY2Xmit\n"));
42416+
42417+ /*
42418+ ** Get port and return if no free packet is available
42419+ */
42420+ if (skb_shinfo(skb)->nr_frags > MAX_SKB_FRAGS) {
42421+ Port = skb_shinfo(skb)->nr_frags - (2*MAX_SKB_FRAGS);
42422+ skb_shinfo(skb)->nr_frags = 0;
42423+ } else {
42424+ Port = (pAC->RlmtNets == 2) ? pNet->PortNr : pAC->ActivePort;
42425+ }
42426+
42427+ if (IS_Q_EMPTY(&(pAC->TxPort[Port][TX_PRIO_LOW].TxQ_free))) {
42428+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
42429+ SK_DBGCAT_DRV_TX_PROGRESS | SK_DBGCAT_DRV_ERROR,
42430+ ("Not free packets available for send\n"));
42431+ return 1; /* zero bytes sent! */
42432+ }
42433+
42434+ /*
42435+ ** Put any new packet to be sent in the waiting queue and
42436+ ** handle also any possible fragment of that packet.
42437+ */
42438+ pWorkQueue = &(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_working);
42439+ pWaitQueue = &(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting);
42440+ pFreeQueue = &(pAC->TxPort[Port][TX_PRIO_LOW].TxQ_free);
42441+ pLETab = &(pAC->TxPort[Port][TX_PRIO_LOW].TxALET);
42442+
42443+ /*
42444+ ** Normal send operations require only one fragment, because
42445+ ** only one sk_buff data area is passed.
42446+ ** In contradiction to this, scatter-gather (zerocopy) send
42447+ ** operations might pass one or more additional fragments
42448+ ** where each fragment needs a separate fragment info packet.
42449+ */
42450+ if (((skb_shinfo(skb)->nr_frags + 1) * MAX_FRAG_OVERHEAD) >
42451+ NUM_FREE_LE_IN_TABLE(pLETab)) {
42452+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
42453+ SK_DBGCAT_DRV_TX_PROGRESS | SK_DBGCAT_DRV_ERROR,
42454+ ("Not enough LE available for send\n"));
42455+ return 1; /* zero bytes sent! */
42456+ }
42457+
42458+ if ((skb_shinfo(skb)->nr_frags + 1) > MAX_NUM_FRAGS) {
42459+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
42460+ SK_DBGCAT_DRV_TX_PROGRESS | SK_DBGCAT_DRV_ERROR,
42461+ ("Not even one fragment available for send\n"));
42462+ return 1; /* zero bytes sent! */
42463+ }
42464+
42465+ /*
42466+ ** Get first packet from free packet queue
42467+ */
42468+ POP_FIRST_PKT_FROM_QUEUE(pFreeQueue, pSkPacket);
42469+ if(pSkPacket == NULL) {
42470+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
42471+ SK_DBGCAT_DRV_TX_PROGRESS | SK_DBGCAT_DRV_ERROR,
42472+ ("Could not obtain free packet used for xmit\n"));
42473+ return 1; /* zero bytes sent! */
42474+ }
42475+
42476+ pSkPacket->pFrag = &(pSkPacket->FragArray[FragIdx]);
42477+
42478+ /*
42479+ ** map the sk_buff to be available for the adapter
42480+ */
42481+ PhysAddr = (SK_U64) pci_map_page(pAC->PciDev,
42482+ virt_to_page(skb->data),
42483+ ((unsigned long) skb->data & ~PAGE_MASK),
42484+ skb_headlen(skb),
42485+ PCI_DMA_TODEVICE);
42486+ pSkPacket->pMBuf = skb;
42487+ pSkPacket->pFrag->pPhys = PhysAddr;
42488+ pSkPacket->pFrag->FragLen = skb_headlen(skb);
42489+ pSkPacket->pFrag->pNext = NULL; /* initial has no next default */
42490+ pSkPacket->NumFrags = skb_shinfo(skb)->nr_frags + 1;
42491+
42492+ PrevFrag = pSkPacket->pFrag;
42493+
42494+ /*
42495+ ** Each scatter-gather fragment need to be mapped...
42496+ */
42497+ for ( CurrFragCtr = 0;
42498+ CurrFragCtr < skb_shinfo(skb)->nr_frags;
42499+ CurrFragCtr++) {
42500+ FragIdx++;
42501+ sk_frag = &skb_shinfo(skb)->frags[CurrFragCtr];
42502+ CurrFrag = &(pSkPacket->FragArray[FragIdx]);
42503+
42504+ /*
42505+ ** map the sk_buff to be available for the adapter
42506+ */
42507+ PhysAddr = (SK_U64) pci_map_page(pAC->PciDev,
42508+ sk_frag->page,
42509+ sk_frag->page_offset,
42510+ sk_frag->size,
42511+ PCI_DMA_TODEVICE);
42512+
42513+ CurrFrag->pPhys = PhysAddr;
42514+ CurrFrag->FragLen = sk_frag->size;
42515+ CurrFrag->pNext = NULL;
42516+
42517+ /*
42518+ ** Add the new fragment to the list of fragments
42519+ */
42520+ PrevFrag->pNext = CurrFrag;
42521+ PrevFrag = CurrFrag;
42522+ }
42523+
42524+ /*
42525+ ** Add packet to waiting packets queue
42526+ */
42527+ PUSH_PKT_AS_LAST_IN_QUEUE(pWaitQueue, pSkPacket);
42528+ GiveTxBufferToHw(pAC, pAC->IoBase, Port);
42529+ dev->trans_start = jiffies;
42530+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
42531+ ("<== SkY2Xmit(return 0)\n"));
42532+ return (0);
42533+} /* SkY2Xmit */
42534+
42535+#ifdef CONFIG_SK98LIN_NAPI
42536+/*****************************************************************************
42537+ *
42538+ * SkY2Poll - NAPI Rx polling callback for Yukon2 chipsets
42539+ *
42540+ * Description:
42541+ * Called by the Linux system in case NAPI polling is activated
42542+ *
42543+ * Returns
42544+ * The number of work data still to be handled
42545+ *
42546+ * Notes
42547+ * The slowpath lock needs to be set because HW accesses may
42548+ * interfere with slowpath events (e.g. TWSI)
42549+ */
42550+int SkY2Poll(
42551+struct net_device *dev, /* device that needs to be polled */
42552+int *budget) /* how many budget do we have? */
42553+{
42554+ SK_AC *pAC = ((DEV_NET*)(dev->priv))->pAC;
42555+ int WorkToDo = min(*budget, dev->quota);
42556+ int WorkDone = 0;
42557+ SK_BOOL handledStatLE = SK_FALSE;
42558+ unsigned long Flags;
42559+
42560+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
42561+ handledStatLE = HandleStatusLEs(pAC, &WorkDone, WorkToDo);
42562+
42563+ *budget -= WorkDone;
42564+ dev->quota -= WorkDone;
42565+
42566+ if(WorkDone < WorkToDo) {
42567+ netif_rx_complete(dev);
42568+ pAC->GIni.GIValIrqMask |= (Y2_IS_STAT_BMU);
42569+ SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
42570+ if ((HW_FEATURE(pAC, HWF_WA_DEV_43_418)) && (handledStatLE)) {
42571+ SK_OUT8(pAC->IoBase, STAT_TX_TIMER_CTRL, TIM_STOP);
42572+ SK_OUT8(pAC->IoBase, STAT_TX_TIMER_CTRL, TIM_START);
42573+ }
42574+ }
42575+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
42576+ return (WorkDone >= WorkToDo);
42577+} /* SkY2Poll */
42578+#endif
42579+
42580+/******************************************************************************
42581+ *
42582+ * SkY2PortStop - stop a port on Yukon2
42583+ *
42584+ * Description:
42585+ * This function stops a port of the Yukon2 chip. This stop
42586+ * stop needs to be performed in a specific order:
42587+ *
42588+ * a) Stop the Prefetch unit
42589+ * b) Stop the Port (MAC, PHY etc.)
42590+ *
42591+ * Returns: N/A
42592+ */
42593+void SkY2PortStop(
42594+SK_AC *pAC, /* adapter control context */
42595+SK_IOC IoC, /* I/O control context (address of adapter registers) */
42596+int Port, /* port to stop (MAC_1 + n) */
42597+int Dir, /* StopDirection (SK_STOP_RX, SK_STOP_TX, SK_STOP_ALL) */
42598+int RstMode) /* Reset Mode (SK_SOFT_RST, SK_HARD_RST) */
42599+{
42600+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42601+ ("==> SkY2PortStop (Port %c)\n", 'A' + Port));
42602+
42603+ /*
42604+ ** Stop the HW
42605+ */
42606+ SkGeStopPort(pAC, IoC, Port, Dir, RstMode);
42607+
42608+ /*
42609+ ** Move any TX packet from work queues into the free queue again
42610+ ** and initialize the TX LETable variables
42611+ */
42612+ SkY2FreeTxBuffers(pAC, pAC->IoBase, Port);
42613+ pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Bmu.RxTx.TcpWp = 0;
42614+ pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Bmu.RxTx.MssValue = 0;
42615+ pAC->TxPort[Port][TX_PRIO_LOW].TxALET.BufHighAddr = 0;
42616+ pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Done = 0;
42617+ pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Put = 0;
42618+ // pAC->GIni.GP[Port].PState = SK_PRT_STOP;
42619+
42620+ /*
42621+ ** Move any RX packet from work queue into the waiting queue
42622+ ** and initialize the RX LETable variables
42623+ */
42624+ SkY2FreeRxBuffers(pAC, pAC->IoBase, Port);
42625+ pAC->RxPort[Port].RxLET.BufHighAddr = 0;
42626+
42627+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42628+ ("<== SkY2PortStop()\n"));
42629+}
42630+
42631+/******************************************************************************
42632+ *
42633+ * SkY2PortStart - start a port on Yukon2
42634+ *
42635+ * Description:
42636+ * This function starts a port of the Yukon2 chip. This start
42637+ * action needs to be performed in a specific order:
42638+ *
42639+ * a) Initialize the LET indices (PUT/GET to 0)
42640+ * b) Initialize the LET in HW (enables also prefetch unit)
42641+ * c) Move all RX buffers from waiting queue to working queue
42642+ * which involves also setting up of RX list elements
42643+ * d) Initialize the FIFO settings of Yukon2 (Watermark etc.)
42644+ * e) Initialize the Port (MAC, PHY etc.)
42645+ * f) Initialize the MC addresses
42646+ *
42647+ * Returns: N/A
42648+ */
42649+void SkY2PortStart(
42650+SK_AC *pAC, /* adapter control context */
42651+SK_IOC IoC, /* I/O control context (address of adapter registers) */
42652+int Port) /* port to start */
42653+{
42654+ // SK_GEPORT *pPrt = &pAC->GIni.GP[Port];
42655+ SK_HWLE *pLE;
42656+ SK_U32 DWord;
42657+ SK_U32 PrefetchReg; /* register for Put index */
42658+
42659+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42660+ ("==> SkY2PortStart (Port %c)\n", 'A' + Port));
42661+
42662+ /*
42663+ ** Initialize the LET indices
42664+ */
42665+ pAC->RxPort[Port].RxLET.Done = 0;
42666+ pAC->RxPort[Port].RxLET.Put = 0;
42667+ pAC->RxPort[Port].RxLET.HwPut = 0;
42668+ pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Done = 0;
42669+ pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Put = 0;
42670+ pAC->TxPort[Port][TX_PRIO_LOW].TxALET.HwPut = 0;
42671+ if (HW_SYNC_TX_SUPPORTED(pAC)) {
42672+ pAC->TxPort[Port][TX_PRIO_LOW].TxSLET.Done = 0;
42673+ pAC->TxPort[Port][TX_PRIO_LOW].TxSLET.Put = 0;
42674+ pAC->TxPort[Port][TX_PRIO_LOW].TxSLET.HwPut = 0;
42675+ }
42676+
42677+ if (HW_FEATURE(pAC, HWF_WA_DEV_420)) {
42678+ /*
42679+ ** It might be that we have to limit the RX buffers
42680+ ** effectively passed to HW. Initialize the start
42681+ ** value in that case...
42682+ */
42683+ NbrRxBuffersInHW = 0;
42684+ }
42685+
42686+ /*
42687+ ** TODO on dual net adapters we need to check if
42688+ ** StatusLETable need to be set...
42689+ **
42690+ ** pAC->StatusLETable.Done = 0;
42691+ ** pAC->StatusLETable.Put = 0;
42692+ ** pAC->StatusLETable.HwPut = 0;
42693+ ** SkGeY2InitPrefetchUnit(pAC, pAC->IoBase, Q_ST, &pAC->StatusLETable);
42694+ */
42695+
42696+ /*
42697+ ** Initialize the LET in HW (enables also prefetch unit)
42698+ */
42699+ SkGeY2InitPrefetchUnit(pAC, IoC,(Port == 0) ? Q_R1 : Q_R2,
42700+ &pAC->RxPort[Port].RxLET);
42701+ SkGeY2InitPrefetchUnit( pAC, IoC,(Port == 0) ? Q_XA1 : Q_XA2,
42702+ &pAC->TxPort[Port][TX_PRIO_LOW].TxALET);
42703+ if (HW_SYNC_TX_SUPPORTED(pAC)) {
42704+ SkGeY2InitPrefetchUnit( pAC, IoC, (Port == 0) ? Q_XS1 : Q_XS2,
42705+ &pAC->TxPort[Port][TX_PRIO_HIGH].TxSLET);
42706+ }
42707+
42708+
42709+ /*
42710+ ** Using new values for the watermarks and the timer for
42711+ ** low latency optimization
42712+ */
42713+ if (pAC->LowLatency) {
42714+ SK_OUT8(IoC, STAT_FIFO_WM, 1);
42715+ SK_OUT8(IoC, STAT_FIFO_ISR_WM, 1);
42716+ SK_OUT32(IoC, STAT_LEV_TIMER_INI, 50);
42717+ SK_OUT32(IoC, STAT_ISR_TIMER_INI, 10);
42718+ }
42719+
42720+
42721+ /*
42722+ ** Initialize the Port (MAC, PHY etc.)
42723+ */
42724+ if (SkGeInitPort(pAC, IoC, Port)) {
42725+ if (Port == 0) {
42726+ printk("%s: SkGeInitPort A failed.\n",pAC->dev[0]->name);
42727+ } else {
42728+ printk("%s: SkGeInitPort B failed.\n",pAC->dev[1]->name);
42729+ }
42730+ }
42731+
42732+ if (IS_GMAC(pAC)) {
42733+ /* disable Rx GMAC FIFO Flush Mode */
42734+ SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8) GMF_RX_F_FL_OFF);
42735+ }
42736+
42737+ /*
42738+ ** Initialize the MC addresses
42739+ */
42740+ SkAddrMcUpdate(pAC,IoC, Port);
42741+
42742+ SkMacRxTxEnable(pAC, IoC,Port);
42743+
42744+ if (pAC->RxPort[Port].UseRxCsum) {
42745+ SkGeRxCsum(pAC, IoC, Port, SK_TRUE);
42746+
42747+ GET_RX_LE(pLE, &pAC->RxPort[Port].RxLET);
42748+ RXLE_SET_STACS1(pLE, pAC->CsOfs1);
42749+ RXLE_SET_STACS2(pLE, pAC->CsOfs2);
42750+ RXLE_SET_CTRL(pLE, 0);
42751+
42752+ RXLE_SET_OPC(pLE, OP_TCPSTART | HW_OWNER);
42753+ FLUSH_OPC(pLE);
42754+ if (Port == 0) {
42755+ PrefetchReg=Y2_PREF_Q_ADDR(Q_R1,PREF_UNIT_PUT_IDX_REG);
42756+ } else {
42757+ PrefetchReg=Y2_PREF_Q_ADDR(Q_R2,PREF_UNIT_PUT_IDX_REG);
42758+ }
42759+ DWord = GET_PUT_IDX(&pAC->RxPort[Port].RxLET);
42760+ SK_OUT32(IoC, PrefetchReg, DWord);
42761+ UPDATE_HWPUT_IDX(&pAC->RxPort[Port].RxLET);
42762+ }
42763+
42764+ pAC->GIni.GP[Port].PState = SK_PRT_RUN;
42765+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
42766+ ("<== SkY2PortStart()\n"));
42767+}
42768+
42769+/******************************************************************************
42770+ *
42771+ * Local Functions
42772+ *
42773+ *****************************************************************************/
42774+
42775+/*****************************************************************************
42776+ *
42777+ * InitPacketQueues - initialize SW settings of packet queues
42778+ *
42779+ * Description:
42780+ * This function will initialize the packet queues for a port.
42781+ *
42782+ * Returns: N/A
42783+ */
42784+static void InitPacketQueues(
42785+SK_AC *pAC, /* pointer to adapter control context */
42786+int Port) /* index of port to be initialized */
42787+{
42788+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
42789+ ("==> InitPacketQueues(Port %c)\n", 'A' + Port));
42790+
42791+ pAC->RxPort[Port].RxQ_working.pHead = NULL;
42792+ pAC->RxPort[Port].RxQ_working.pTail = NULL;
42793+ spin_lock_init(&pAC->RxPort[Port].RxQ_working.QueueLock);
42794+
42795+ pAC->RxPort[Port].RxQ_waiting.pHead = NULL;
42796+ pAC->RxPort[Port].RxQ_waiting.pTail = NULL;
42797+ spin_lock_init(&pAC->RxPort[Port].RxQ_waiting.QueueLock);
42798+
42799+ pAC->TxPort[Port][TX_PRIO_LOW].TxQ_free.pHead = NULL;
42800+ pAC->TxPort[Port][TX_PRIO_LOW].TxQ_free.pTail = NULL;
42801+ spin_lock_init(&pAC->TxPort[Port][TX_PRIO_LOW].TxQ_free.QueueLock);
42802+
42803+ pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_working.pHead = NULL;
42804+ pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_working.pTail = NULL;
42805+ spin_lock_init(&pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_working.QueueLock);
42806+
42807+ pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting.pHead = NULL;
42808+ pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting.pTail = NULL;
42809+ spin_lock_init(&pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting.QueueLock);
42810+
42811+#if USE_SYNC_TX_QUEUE
42812+ pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_working.pHead = NULL;
42813+ pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_working.pTail = NULL;
42814+ spin_lock_init(&pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_working.QueueLock);
42815+
42816+ pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_waiting.pHead = NULL;
42817+ pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_waiting.pTail = NULL;
42818+ spin_lock_init(&pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_waiting.QueueLock);
42819+#endif
42820+
42821+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
42822+ ("<== InitPacketQueues(Port %c)\n", 'A' + Port));
42823+} /* InitPacketQueues */
42824+
42825+/*****************************************************************************
42826+ *
42827+ * GiveTxBufferToHw - commits a previously allocated DMA area to HW
42828+ *
42829+ * Description:
42830+ * This functions gives transmit buffers to HW. If no list elements
42831+ * are available the buffers will be queued.
42832+ *
42833+ * Notes:
42834+ * This function can run only once in a system at one time.
42835+ *
42836+ * Returns: N/A
42837+ */
42838+static void GiveTxBufferToHw(
42839+SK_AC *pAC, /* pointer to adapter control context */
42840+SK_IOC IoC, /* I/O control context (address of registers) */
42841+int Port) /* port index for which the buffer is used */
42842+{
42843+ SK_HWLE *pLE;
42844+ SK_PACKET *pSkPacket;
42845+ SK_FRAG *pFrag;
42846+ SK_PKT_QUEUE *pWorkQueue; /* corresponding TX queue */
42847+ SK_PKT_QUEUE *pWaitQueue;
42848+ SK_LE_TABLE *pLETab; /* corresponding LETable */
42849+ SK_BOOL SetOpcodePacketFlag;
42850+ SK_U32 HighAddress;
42851+ SK_U32 LowAddress;
42852+ SK_U16 TcpSumStart;
42853+ SK_U16 TcpSumWrite;
42854+ SK_U8 OpCode;
42855+ SK_U8 Ctrl;
42856+ unsigned long Flags;
42857+ unsigned long LockFlag;
42858+ int Protocol;
42859+#ifdef NETIF_F_TSO
42860+ SK_U16 Mss;
42861+ int TcpOptLen;
42862+ int IpTcpLen;
42863+#endif
42864+
42865+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
42866+ ("==> GiveTxBufferToHw\n"));
42867+
42868+ if (IS_Q_EMPTY(&(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting))) {
42869+ return;
42870+ }
42871+
42872+ spin_lock_irqsave(&pAC->TxQueueLock, LockFlag);
42873+
42874+ /*
42875+ ** Initialize queue settings
42876+ */
42877+ pWorkQueue = &(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_working);
42878+ pWaitQueue = &(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting);
42879+ pLETab = &(pAC->TxPort[Port][TX_PRIO_LOW].TxALET);
42880+
42881+ POP_FIRST_PKT_FROM_QUEUE(pWaitQueue, pSkPacket);
42882+ while (pSkPacket != NULL) {
42883+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
42884+ ("\tWe have a packet to send %p\n", pSkPacket));
42885+
42886+ /*
42887+ ** the first frag of a packet gets opcode OP_PACKET
42888+ */
42889+ SetOpcodePacketFlag = SK_TRUE;
42890+ pFrag = pSkPacket->pFrag;
42891+
42892+ /*
42893+ ** fill list elements with data from fragments
42894+ */
42895+ while (pFrag != NULL) {
42896+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
42897+ ("\tGet LE\n"));
42898+#ifdef NETIF_F_TSO
42899+ Mss = skb_shinfo(pSkPacket->pMBuf)->tso_size;
42900+ if (Mss) {
42901+ TcpOptLen = ((pSkPacket->pMBuf->h.th->doff - 5) * 4);
42902+ IpTcpLen = ((pSkPacket->pMBuf->nh.iph->ihl * 4) +
42903+ sizeof(struct tcphdr));
42904+ Mss += (TcpOptLen + IpTcpLen + C_LEN_ETHERMAC_HEADER);
42905+ }
42906+ if (pLETab->Bmu.RxTx.MssValue != Mss) {
42907+ pLETab->Bmu.RxTx.MssValue = Mss;
42908+ /* Take a new LE for TSO from the table */
42909+ GET_TX_LE(pLE, pLETab);
42910+
42911+#if 0
42912+ if(pSkPacket->VlanId) {
42913+ TXLE_SET_OPC(pLE, OP_LRGLENVLAN | HW_OWNER);
42914+ TXLE_SET_VLAN(pLE, pSkPacket->VlanId);
42915+ pSkPacket->VlanId = 0;
42916+ Ctrl |= INS_VLAN;
42917+ } else {
42918+#endif
42919+ TXLE_SET_OPC(pLE, OP_LRGLEN | HW_OWNER);
42920+#if 0
42921+ }
42922+#endif
42923+ /* set maximum segment size for new packet */
42924+ TXLE_SET_LSLEN(pLE, pLETab->Bmu.RxTx.MssValue);
42925+ FLUSH_OPC(pLE) ;
42926+ }
42927+#endif
42928+ GET_TX_LE(pLE, pLETab);
42929+ Ctrl = 0;
42930+
42931+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
42932+ ("\tGot empty LE %p idx %d\n", pLE, GET_PUT_IDX(pLETab)));
42933+
42934+ SK_DBG_DUMP_TX_LE(pLE);
42935+
42936+ LowAddress = (SK_U32) (pFrag->pPhys & 0xffffffff);
42937+ HighAddress = (SK_U32) (pFrag->pPhys >> 32);
42938+
42939+ if (HighAddress != pLETab->BufHighAddr) {
42940+ /* set opcode high part of the address in one LE */
42941+ OpCode = OP_ADDR64 | HW_OWNER;
42942+
42943+ /* Set now the 32 high bits of the address */
42944+ TXLE_SET_ADDR( pLE, HighAddress);
42945+
42946+ /* Set the opcode into the LE */
42947+ TXLE_SET_OPC(pLE, OpCode);
42948+
42949+ /* Flush the LE to memory */
42950+ FLUSH_OPC(pLE);
42951+
42952+ /* remember the HighAddress we gave to the Hardware */
42953+ pLETab->BufHighAddr = HighAddress;
42954+
42955+ /* get a new LE because we filled one with high address */
42956+ GET_TX_LE(pLE, pLETab);
42957+ }
42958+
42959+ /*
42960+ ** TCP checksum offload
42961+ */
42962+ if ((pSkPacket->pMBuf->ip_summed == CHECKSUM_HW) &&
42963+ (SetOpcodePacketFlag == SK_TRUE)) {
42964+ Protocol = ((SK_U8)pSkPacket->pMBuf->data[C_OFFSET_IPPROTO] & 0xff);
42965+ /* if (Protocol & C_PROTO_ID_IP) { Ctrl = 0; } */
42966+ if (Protocol & C_PROTO_ID_TCP) {
42967+ Ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
42968+ /* TCP Checksum Calculation Start Position */
42969+ TcpSumStart = C_LEN_ETHERMAC_HEADER + IP_HDR_LEN;
42970+ /* TCP Checksum Write Position */
42971+ TcpSumWrite = TcpSumStart + TCP_CSUM_OFFS;
42972+ } else {
42973+ Ctrl = UDPTCP | CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
42974+ /* TCP Checksum Calculation Start Position */
42975+ TcpSumStart = ETHER_MAC_HDR_LEN + IP_HDR_LEN;
42976+ /* UDP Checksum Write Position */
42977+ TcpSumWrite = TcpSumStart + UDP_CSUM_OFFS;
42978+ }
42979+
42980+ if ((Ctrl) && (pLETab->Bmu.RxTx.TcpWp != TcpSumWrite)) {
42981+ /* Update the last value of the write position */
42982+ pLETab->Bmu.RxTx.TcpWp = TcpSumWrite;
42983+
42984+ /* Set the Lock field for this LE: */
42985+ /* Checksum calculation for one packet only */
42986+ TXLE_SET_LCKCS(pLE, 1);
42987+
42988+ /* Set the start position for checksum. */
42989+ TXLE_SET_STACS(pLE, TcpSumStart);
42990+
42991+ /* Set the position where the checksum will be writen */
42992+ TXLE_SET_WRICS(pLE, TcpSumWrite);
42993+
42994+ /* Set the initial value for checksum */
42995+ /* PseudoHeader CS passed from Linux -> 0! */
42996+ TXLE_SET_INICS(pLE, 0);
42997+
42998+ /* Set the opcode for tcp checksum */
42999+ TXLE_SET_OPC(pLE, OP_TCPLISW | HW_OWNER);
43000+
43001+ /* Flush the LE to memory */
43002+ FLUSH_OPC(pLE);
43003+
43004+ /* get a new LE because we filled one with data for checksum */
43005+ GET_TX_LE(pLE, pLETab);
43006+ }
43007+ } /* end TCP offload handling */
43008+
43009+ TXLE_SET_ADDR(pLE, LowAddress);
43010+ TXLE_SET_LEN(pLE, pFrag->FragLen);
43011+
43012+ if (SetOpcodePacketFlag){
43013+#ifdef NETIF_F_TSO
43014+ if (Mss) {
43015+ OpCode = OP_LARGESEND | HW_OWNER;
43016+ } else {
43017+#endif
43018+ OpCode = OP_PACKET| HW_OWNER;
43019+#ifdef NETIF_F_TSO
43020+ }
43021+#endif
43022+ SetOpcodePacketFlag = SK_FALSE;
43023+ } else {
43024+ /* Follow packet in a sequence has always OP_BUFFER */
43025+ OpCode = OP_BUFFER | HW_OWNER;
43026+ }
43027+
43028+ /* Check if the low address is near the upper limit. */
43029+ CHECK_LOW_ADDRESS(pLETab->BufHighAddr, LowAddress, pFrag->FragLen);
43030+
43031+ pFrag = pFrag->pNext;
43032+ if (pFrag == NULL) {
43033+ /* mark last fragment */
43034+ Ctrl |= EOP;
43035+ }
43036+ TXLE_SET_CTRL(pLE, Ctrl);
43037+ TXLE_SET_OPC(pLE, OpCode);
43038+ FLUSH_OPC(pLE);
43039+
43040+ SK_DBG_DUMP_TX_LE(pLE);
43041+ }
43042+
43043+ /*
43044+ ** Remember next LE for tx complete
43045+ */
43046+ pSkPacket->NextLE = GET_PUT_IDX(pLETab);
43047+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43048+ ("\tNext LE for pkt %p is %d\n", pSkPacket, pSkPacket->NextLE));
43049+
43050+ /*
43051+ ** Add packet to working packets queue
43052+ */
43053+ PUSH_PKT_AS_LAST_IN_QUEUE(pWorkQueue, pSkPacket);
43054+
43055+ /*
43056+ ** give transmit start command
43057+ */
43058+ if (HW_FEATURE(pAC, HWF_WA_DEV_42)) {
43059+ spin_lock(&pAC->SetPutIndexLock);
43060+ SkGeY2SetPutIndex(pAC, pAC->IoBase, Y2_PREF_Q_ADDR(Q_XA1,0), &pAC->TxPort[0][0].TxALET);
43061+ spin_unlock(&pAC->SetPutIndexLock);
43062+ } else {
43063+ /* write put index */
43064+ if (Port == 0) {
43065+ SK_OUT32(pAC->IoBase,
43066+ Y2_PREF_Q_ADDR(Q_XA1,PREF_UNIT_PUT_IDX_REG),
43067+ GET_PUT_IDX(&pAC->TxPort[0][0].TxALET));
43068+ UPDATE_HWPUT_IDX(&pAC->TxPort[0][0].TxALET);
43069+ } else {
43070+ SK_OUT32(pAC->IoBase,
43071+ Y2_PREF_Q_ADDR(Q_XA2, PREF_UNIT_PUT_IDX_REG),
43072+ GET_PUT_IDX(&pAC->TxPort[1][0].TxALET));
43073+ UPDATE_HWPUT_IDX(&pAC->TxPort[1][0].TxALET);
43074+ }
43075+ }
43076+
43077+ if (IS_Q_EMPTY(&(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting))) {
43078+ break; /* get out of while */
43079+ }
43080+ POP_FIRST_PKT_FROM_QUEUE(pWaitQueue, pSkPacket);
43081+ } /* while (pSkPacket != NULL) */
43082+
43083+ spin_unlock_irqrestore(&pAC->TxQueueLock, LockFlag);
43084+
43085+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43086+ ("<== GiveTxBufferToHw\n"));
43087+ return;
43088+} /* GiveTxBufferToHw */
43089+
43090+/***********************************************************************
43091+ *
43092+ * GiveRxBufferToHw - commits a previously allocated DMA area to HW
43093+ *
43094+ * Description:
43095+ * This functions gives receive buffers to HW. If no list elements
43096+ * are available the buffers will be queued.
43097+ *
43098+ * Notes:
43099+ * This function can run only once in a system at one time.
43100+ *
43101+ * Returns: N/A
43102+ */
43103+static void GiveRxBufferToHw(
43104+SK_AC *pAC, /* pointer to adapter control context */
43105+SK_IOC IoC, /* I/O control context (address of registers) */
43106+int Port, /* port index for which the buffer is used */
43107+SK_PACKET *pPacket) /* receive buffer(s) */
43108+{
43109+ SK_HWLE *pLE;
43110+ SK_LE_TABLE *pLETab;
43111+ SK_BOOL Done = SK_FALSE; /* at least on LE changed? */
43112+ SK_U32 LowAddress;
43113+ SK_U32 HighAddress;
43114+ SK_U32 PrefetchReg; /* register for Put index */
43115+ unsigned NumFree;
43116+ unsigned Required;
43117+ unsigned long Flags;
43118+
43119+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43120+ ("==> GiveRxBufferToHw(Port %c, Packet %p)\n", 'A' + Port, pPacket));
43121+
43122+ pLETab = &pAC->RxPort[Port].RxLET;
43123+
43124+ if (Port == 0) {
43125+ PrefetchReg = Y2_PREF_Q_ADDR(Q_R1, PREF_UNIT_PUT_IDX_REG);
43126+ } else {
43127+ PrefetchReg = Y2_PREF_Q_ADDR(Q_R2, PREF_UNIT_PUT_IDX_REG);
43128+ }
43129+
43130+ if (pPacket != NULL) {
43131+ /*
43132+ ** For the time being, we have only one packet passed
43133+ ** to this function which might be changed in future!
43134+ */
43135+ PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket);
43136+ }
43137+
43138+ /*
43139+ ** now pPacket contains the very first waiting packet
43140+ */
43141+ POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket);
43142+ while (pPacket != NULL) {
43143+ if (HW_FEATURE(pAC, HWF_WA_DEV_420)) {
43144+ if (NbrRxBuffersInHW >= MAX_NBR_RX_BUFFERS_IN_HW) {
43145+ PUSH_PKT_AS_FIRST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket);
43146+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43147+ ("<== GiveRxBufferToHw()\n"));
43148+ return;
43149+ }
43150+ NbrRxBuffersInHW++;
43151+ }
43152+
43153+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43154+ ("Try to add packet %p\n", pPacket));
43155+
43156+ /*
43157+ ** Check whether we have enough listelements:
43158+ **
43159+ ** we have to take into account that each fragment
43160+ ** may need an additional list element for the high
43161+ ** part of the address here I simplified it by
43162+ ** using MAX_FRAG_OVERHEAD maybe it's worth to split
43163+ ** this constant for Rx and Tx or to calculate the
43164+ ** real number of needed LE's
43165+ */
43166+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43167+ ("\tNum %d Put %d Done %d Free %d %d\n",
43168+ pLETab->Num, pLETab->Put, pLETab->Done,
43169+ NUM_FREE_LE_IN_TABLE(pLETab),
43170+ (NUM_FREE_LE_IN_TABLE(pLETab))));
43171+
43172+ Required = pPacket->NumFrags + MAX_FRAG_OVERHEAD;
43173+ NumFree = NUM_FREE_LE_IN_TABLE(pLETab);
43174+ if (NumFree) {
43175+ NumFree--;
43176+ }
43177+
43178+ if (Required > NumFree ) {
43179+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
43180+ SK_DBGCAT_DRV_RX_PROGRESS | SK_DBGCAT_DRV_ERROR,
43181+ ("\tOut of LEs have %d need %d\n",
43182+ NumFree, Required));
43183+
43184+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43185+ ("\tWaitQueue starts with packet %p\n", pPacket));
43186+ PUSH_PKT_AS_FIRST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket);
43187+ if (Done) {
43188+ /*
43189+ ** write Put index to BMU or Polling Unit and make the LE's
43190+ ** available for the hardware
43191+ */
43192+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43193+ ("\tWrite new Put Idx\n"));
43194+
43195+ SK_OUT32(IoC, PrefetchReg, GET_PUT_IDX(pLETab));
43196+ UPDATE_HWPUT_IDX(pLETab);
43197+ }
43198+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43199+ ("<== GiveRxBufferToHw()\n"));
43200+ return;
43201+ } else {
43202+ if (!AllocAndMapRxBuffer(pAC, pPacket, Port)) {
43203+ /*
43204+ ** Failure while allocating sk_buff might
43205+ ** be due to temporary short of resources
43206+ ** Maybe next time buffers are available.
43207+ ** Until this, the packet remains in the
43208+ ** RX waiting queue...
43209+ */
43210+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
43211+ SK_DBGCAT_DRV_RX_PROGRESS | SK_DBGCAT_DRV_ERROR,
43212+ ("Failed to allocate Rx buffer\n"));
43213+
43214+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43215+ ("WaitQueue starts with packet %p\n", pPacket));
43216+ PUSH_PKT_AS_FIRST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket);
43217+ if (Done) {
43218+ /*
43219+ ** write Put index to BMU or Polling
43220+ ** Unit and make the LE's
43221+ ** available for the hardware
43222+ */
43223+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43224+ ("\tWrite new Put Idx\n"));
43225+
43226+ SK_OUT32(IoC, PrefetchReg, GET_PUT_IDX(pLETab));
43227+ UPDATE_HWPUT_IDX(pLETab);
43228+ }
43229+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43230+ ("<== GiveRxBufferToHw()\n"));
43231+ return;
43232+ }
43233+ }
43234+ Done = SK_TRUE;
43235+
43236+ LowAddress = (SK_U32) (pPacket->pFrag->pPhys & 0xffffffff);
43237+ HighAddress = (SK_U32) (pPacket->pFrag->pPhys >> 32);
43238+ if (HighAddress != pLETab->BufHighAddr) {
43239+ /* get a new LE for high address */
43240+ GET_RX_LE(pLE, pLETab);
43241+
43242+ /* Set now the 32 high bits of the address */
43243+ RXLE_SET_ADDR(pLE, HighAddress);
43244+
43245+ /* Set the control bits of the address */
43246+ RXLE_SET_CTRL(pLE, 0);
43247+
43248+ /* Set the opcode into the LE */
43249+ RXLE_SET_OPC(pLE, (OP_ADDR64 | HW_OWNER));
43250+
43251+ /* Flush the LE to memory */
43252+ FLUSH_OPC(pLE);
43253+
43254+ /* remember the HighAddress we gave to the Hardware */
43255+ pLETab->BufHighAddr = HighAddress;
43256+ }
43257+
43258+ /*
43259+ ** Fill data into listelement
43260+ */
43261+ GET_RX_LE(pLE, pLETab);
43262+ RXLE_SET_ADDR(pLE, LowAddress);
43263+ RXLE_SET_LEN(pLE, pPacket->pFrag->FragLen);
43264+ RXLE_SET_CTRL(pLE, 0);
43265+ RXLE_SET_OPC(pLE, (OP_PACKET | HW_OWNER));
43266+ FLUSH_OPC(pLE);
43267+
43268+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43269+ ("=== LE filled\n"));
43270+
43271+ SK_DBG_DUMP_RX_LE(pLE);
43272+
43273+ /*
43274+ ** Remember next LE for rx complete
43275+ */
43276+ pPacket->NextLE = GET_PUT_IDX(pLETab);
43277+
43278+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43279+ ("\tPackets Next LE is %d\n", pPacket->NextLE));
43280+
43281+ /*
43282+ ** Add packet to working receive buffer queue and get
43283+ ** any next packet out of the waiting queue
43284+ */
43285+ PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_working, pPacket);
43286+ if (IS_Q_EMPTY(&(pAC->RxPort[Port].RxQ_waiting))) {
43287+ break; /* get out of while processing */
43288+ }
43289+ POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket);
43290+ }
43291+
43292+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43293+ ("\tWaitQueue is empty\n"));
43294+
43295+ if (Done) {
43296+ /*
43297+ ** write Put index to BMU or Polling Unit and make the LE's
43298+ ** available for the hardware
43299+ */
43300+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43301+ ("\tWrite new Put Idx\n"));
43302+
43303+ /* Speed enhancement for a2 chipsets */
43304+ if (HW_FEATURE(pAC, HWF_WA_DEV_42)) {
43305+ spin_lock_irqsave(&pAC->SetPutIndexLock, Flags);
43306+ SkGeY2SetPutIndex(pAC, pAC->IoBase, Y2_PREF_Q_ADDR(Q_R1,0), pLETab);
43307+ spin_unlock_irqrestore(&pAC->SetPutIndexLock, Flags);
43308+ } else {
43309+ /* write put index */
43310+ if (Port == 0) {
43311+ SK_OUT32(IoC,
43312+ Y2_PREF_Q_ADDR(Q_R1, PREF_UNIT_PUT_IDX_REG),
43313+ GET_PUT_IDX(pLETab));
43314+ } else {
43315+ SK_OUT32(IoC,
43316+ Y2_PREF_Q_ADDR(Q_R2, PREF_UNIT_PUT_IDX_REG),
43317+ GET_PUT_IDX(pLETab));
43318+ }
43319+
43320+ /* Update put index */
43321+ UPDATE_HWPUT_IDX(pLETab);
43322+ }
43323+ }
43324+
43325+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43326+ ("<== GiveRxBufferToHw()\n"));
43327+} /* GiveRxBufferToHw */
43328+
43329+/***********************************************************************
43330+ *
43331+ * FillReceiveTableYukon2 - map any waiting RX buffers to HW
43332+ *
43333+ * Description:
43334+ * If the list element table contains more empty elements than
43335+ * specified this function tries to refill them.
43336+ *
43337+ * Notes:
43338+ * This function can run only once per port in a system at one time.
43339+ *
43340+ * Returns: N/A
43341+ */
43342+void FillReceiveTableYukon2(
43343+SK_AC *pAC, /* pointer to adapter control context */
43344+SK_IOC IoC, /* I/O control context */
43345+int Port) /* port index of RX */
43346+{
43347+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43348+ ("==> FillReceiveTableYukon2 (Port %c)\n", 'A' + Port));
43349+
43350+ if (NUM_FREE_LE_IN_TABLE(&pAC->RxPort[Port].RxLET) >
43351+ pAC->MaxUnusedRxLeWorking) {
43352+
43353+ /*
43354+ ** Give alle waiting receive buffers down
43355+ ** The queue holds all RX packets that
43356+ ** need a fresh allocation of the sk_buff.
43357+ */
43358+ if (pAC->RxPort[Port].RxQ_waiting.pHead != NULL) {
43359+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43360+ ("Waiting queue is not empty -> give it to HW"));
43361+ GiveRxBufferToHw(pAC, IoC, Port, NULL);
43362+ }
43363+ }
43364+
43365+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43366+ ("<== FillReceiveTableYukon2 ()\n"));
43367+} /* FillReceiveTableYukon2 */
43368+
43369+/******************************************************************************
43370+ *
43371+ *
43372+ * HandleReceives - will pass any ready RX packet to kernel
43373+ *
43374+ * Description:
43375+ * This functions handles a received packet. It checks wether it is
43376+ * valid, updates the receive list element table and gives the receive
43377+ * buffer to Linux
43378+ *
43379+ * Notes:
43380+ * This function can run only once per port at one time in the system.
43381+ *
43382+ * Returns: N/A
43383+ */
43384+static SK_BOOL HandleReceives(
43385+SK_AC *pAC, /* adapter control context */
43386+int Port, /* port on which a packet has been received */
43387+SK_U16 Len, /* number of bytes which was actually received */
43388+SK_U32 FrameStatus, /* MAC frame status word */
43389+SK_U16 Tcp1, /* first hw checksum */
43390+SK_U16 Tcp2, /* second hw checksum */
43391+SK_U32 Tist, /* timestamp */
43392+SK_U16 Vlan) /* Vlan Id */
43393+{
43394+
43395+ SK_PACKET *pSkPacket;
43396+ SK_LE_TABLE *pLETab;
43397+ SK_MBUF *pRlmtMbuf; /* buffer for giving RLMT frame */
43398+ struct sk_buff *pMsg; /* ptr to message holding frame */
43399+#ifdef __ia64__
43400+ struct sk_buff *pNewMsg; /* used when IP aligning */
43401+#endif
43402+
43403+#ifdef CONFIG_SK98LIN_NAPI
43404+ SK_BOOL SlowPathLock = SK_FALSE;
43405+#else
43406+ SK_BOOL SlowPathLock = SK_TRUE;
43407+#endif
43408+ SK_BOOL IsGoodPkt;
43409+ SK_BOOL IsBc;
43410+ SK_BOOL IsMc;
43411+ SK_EVPARA EvPara; /* an event parameter union */
43412+ SK_I16 LenToFree; /* must be signed integer */
43413+
43414+ unsigned long Flags; /* for spin lock */
43415+ unsigned int RlmtNotifier;
43416+ unsigned short Type;
43417+ int IpFrameLength;
43418+ int FrameLength; /* total length of recvd frame */
43419+ int HeaderLength;
43420+ int NumBytes;
43421+ int Result;
43422+ int Offset = 0;
43423+
43424+#ifdef Y2_SYNC_CHECK
43425+ SK_U16 MyTcp;
43426+#endif
43427+
43428+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43429+ ("==> HandleReceives (Port %c)\n", 'A' + Port));
43430+
43431+ /*
43432+ ** initialize vars for selected port
43433+ */
43434+ pLETab = &pAC->RxPort[Port].RxLET;
43435+
43436+ /*
43437+ ** check whether we want to receive this packet
43438+ */
43439+ SK_Y2_RXSTAT_CHECK_PKT(Len, FrameStatus, IsGoodPkt);
43440+
43441+ /*
43442+ ** Remember length to free (in case of RxBuffer overruns;
43443+ ** unlikely, but might happen once in a while)
43444+ */
43445+ LenToFree = (SK_I16) Len;
43446+
43447+ /*
43448+ ** maybe we put these two checks into the SK_RXDESC_CHECK_PKT macro too
43449+ */
43450+ if (Len > pAC->RxPort[Port].RxBufSize) {
43451+ IsGoodPkt = SK_FALSE;
43452+ }
43453+
43454+ /*
43455+ ** take first receive buffer out of working queue
43456+ */
43457+ POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_working, pSkPacket);
43458+ if (pSkPacket == NULL) {
43459+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
43460+ SK_DBGCAT_DRV_ERROR,
43461+ ("Packet not available. NULL pointer.\n"));
43462+ return(SK_TRUE);
43463+ }
43464+
43465+ if (HW_FEATURE(pAC, HWF_WA_DEV_420)) {
43466+ NbrRxBuffersInHW--;
43467+ }
43468+
43469+ /*
43470+ ** Verify the received length of the frame! Note that having
43471+ ** multiple RxBuffers being aware of one single receive packet
43472+ ** (one packet spread over multiple RxBuffers) is not supported
43473+ ** by this driver!
43474+ */
43475+ if ((Len > pAC->RxPort[Port].RxBufSize) ||
43476+ (Len > (SK_U16) pSkPacket->PacketLen)) {
43477+ IsGoodPkt = SK_FALSE;
43478+ }
43479+
43480+ /*
43481+ ** Reset own bit in LE's between old and new Done index
43482+ ** This is not really necessary but makes debugging easier
43483+ */
43484+ CLEAR_LE_OWN_FROM_DONE_TO(pLETab, pSkPacket->NextLE);
43485+
43486+ /*
43487+ ** Free the list elements for new Rx buffers
43488+ */
43489+ SET_DONE_INDEX(pLETab, pSkPacket->NextLE);
43490+ pMsg = pSkPacket->pMBuf;
43491+ FrameLength = Len;
43492+
43493+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43494+ ("Received frame of length %d on port %d\n",FrameLength, Port));
43495+
43496+ if (!IsGoodPkt) {
43497+ /*
43498+ ** release the DMA mapping
43499+ */
43500+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5)
43501+ pci_dma_sync_single(pAC->PciDev,
43502+ (dma_addr_t) pSkPacket->pFrag->pPhys,
43503+ pSkPacket->pFrag->FragLen,
43504+ PCI_DMA_FROMDEVICE);
43505+
43506+#else
43507+ pci_dma_sync_single_for_cpu(pAC->PciDev,
43508+ (dma_addr_t) pSkPacket->pFrag->pPhys,
43509+ pSkPacket->pFrag->FragLen,
43510+ PCI_DMA_FROMDEVICE);
43511+#endif
43512+
43513+ DEV_KFREE_SKB_ANY(pSkPacket->pMBuf);
43514+ PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pSkPacket);
43515+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43516+ ("<== HandleReceives (Port %c)\n", 'A' + Port));
43517+
43518+ /*
43519+ ** Sanity check for RxBuffer overruns...
43520+ */
43521+ LenToFree = LenToFree - (pSkPacket->pFrag->FragLen);
43522+ while (LenToFree > 0) {
43523+ POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_working, pSkPacket);
43524+ if (HW_FEATURE(pAC, HWF_WA_DEV_420)) {
43525+ NbrRxBuffersInHW--;
43526+ }
43527+ CLEAR_LE_OWN_FROM_DONE_TO(pLETab, pSkPacket->NextLE);
43528+ SET_DONE_INDEX(pLETab, pSkPacket->NextLE);
43529+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5)
43530+ pci_dma_sync_single(pAC->PciDev,
43531+ (dma_addr_t) pSkPacket->pFrag->pPhys,
43532+ pSkPacket->pFrag->FragLen,
43533+ PCI_DMA_FROMDEVICE);
43534+#else
43535+ pci_dma_sync_single_for_device(pAC->PciDev,
43536+ (dma_addr_t) pSkPacket->pFrag->pPhys,
43537+ pSkPacket->pFrag->FragLen,
43538+ PCI_DMA_FROMDEVICE);
43539+#endif
43540+
43541+ DEV_KFREE_SKB_ANY(pSkPacket->pMBuf);
43542+ PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pSkPacket);
43543+ LenToFree = LenToFree - ((SK_I16)(pSkPacket->pFrag->FragLen));
43544+
43545+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
43546+ SK_DBGCAT_DRV_RX_PROGRESS | SK_DBGCAT_DRV_ERROR,
43547+ ("<==HandleReceives (Port %c) drop faulty len pkt(2)\n",'A'+Port));
43548+ }
43549+ return(SK_TRUE);
43550+ } else {
43551+ /*
43552+ ** Release the DMA mapping
43553+ */
43554+ pci_unmap_single(pAC->PciDev,
43555+ pSkPacket->pFrag->pPhys,
43556+ pAC->RxPort[Port].RxBufSize,
43557+ PCI_DMA_FROMDEVICE);
43558+
43559+ skb_put(pMsg, FrameLength); /* set message len */
43560+ pMsg->ip_summed = CHECKSUM_NONE; /* initial default */
43561+
43562+#ifdef Y2_SYNC_CHECK
43563+ pAC->FramesWithoutSyncCheck++;
43564+ if (pAC->FramesWithoutSyncCheck > Y2_RESYNC_WATERMARK) {
43565+ if ((Tcp1 != 1) || (Tcp2 != 0)) {
43566+ pAC->FramesWithoutSyncCheck = 0;
43567+ MyTcp = (SK_U16) SkCsCalculateChecksum(
43568+ &pMsg->data[14],
43569+ FrameLength - 14);
43570+ if (MyTcp != Tcp1) {
43571+ /* Queue port reset event */
43572+ SkLocalEventQueue(pAC, SKGE_DRV,
43573+ SK_DRV_RECOVER,Port,-1,SK_FALSE);
43574+ }
43575+ }
43576+ }
43577+#endif
43578+
43579+ if (pAC->RxPort[Port].UseRxCsum) {
43580+ Type = ntohs(*((short*)&pMsg->data[12]));
43581+ if (Type == 0x800) {
43582+ *((char *)&(IpFrameLength)) = pMsg->data[16];
43583+ *(((char *)&(IpFrameLength))+1) = pMsg->data[17];
43584+ IpFrameLength = ntohs(IpFrameLength);
43585+ HeaderLength = FrameLength - IpFrameLength;
43586+ if (HeaderLength == 0xe) {
43587+ Result =
43588+ SkCsGetReceiveInfo(pAC,&pMsg->data[14],Tcp1,Tcp2, Port);
43589+ if ((Result == SKCS_STATUS_IP_FRAGMENT) ||
43590+ (Result == SKCS_STATUS_IP_CSUM_OK) ||
43591+ (Result == SKCS_STATUS_TCP_CSUM_OK) ||
43592+ (Result == SKCS_STATUS_UDP_CSUM_OK)) {
43593+ pMsg->ip_summed = CHECKSUM_UNNECESSARY;
43594+ } else if ((Result == SKCS_STATUS_TCP_CSUM_ERROR) ||
43595+ (Result == SKCS_STATUS_UDP_CSUM_ERROR) ||
43596+ (Result == SKCS_STATUS_IP_CSUM_ERROR_UDP) ||
43597+ (Result == SKCS_STATUS_IP_CSUM_ERROR_TCP) ||
43598+ (Result == SKCS_STATUS_IP_CSUM_ERROR)) {
43599+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
43600+ SK_DBGCAT_DRV_RX_PROGRESS | SK_DBGCAT_DRV_ERROR,
43601+ ("skge: CRC error. Frame dropped!\n"));
43602+ DEV_KFREE_SKB_ANY(pMsg);
43603+ PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pSkPacket);
43604+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_RX_PROGRESS,
43605+ ("<==HandleReceives(Port %c)\n",'A'+Port));
43606+ return(SK_TRUE);
43607+ } else {
43608+ pMsg->ip_summed = CHECKSUM_NONE;
43609+ }
43610+ } /* end if (HeaderLength == valid) */
43611+ } /* end if (Type == 0x800) -> IP frame */
43612+ } /* end if (pRxPort->UseRxCsum) */
43613+
43614+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
43615+ SK_DBGCAT_DRV_RX_PROGRESS,("V"));
43616+ RlmtNotifier = SK_RLMT_RX_PROTOCOL;
43617+
43618+ IsBc = (FrameStatus & GMR_FS_BC) ? SK_TRUE : SK_FALSE;
43619+ SK_RLMT_PRE_LOOKAHEAD(pAC,Port,FrameLength,
43620+ IsBc,&Offset,&NumBytes);
43621+ if (NumBytes != 0) {
43622+ IsMc = (FrameStatus & GMR_FS_MC) ? SK_TRUE : SK_FALSE;
43623+ SK_RLMT_LOOKAHEAD(pAC,Port,&pMsg->data[Offset],
43624+ IsBc,IsMc,&RlmtNotifier);
43625+ }
43626+
43627+ if (RlmtNotifier == SK_RLMT_RX_PROTOCOL) {
43628+ SK_DBG_MSG(NULL,SK_DBGMOD_DRV,
43629+ SK_DBGCAT_DRV_RX_PROGRESS,("W"));
43630+ if ((Port == pAC->ActivePort)||(pAC->RlmtNets == 2)) {
43631+ /* send up only frames from active port */
43632+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
43633+ SK_DBGCAT_DRV_RX_PROGRESS,("U"));
43634+#ifdef xDEBUG
43635+ DumpMsg(pMsg, "Rx");
43636+#endif
43637+ SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC,
43638+ FrameLength, Port);
43639+#ifdef __ia64__
43640+ pNewMsg = alloc_skb(pMsg->len, GFP_ATOMIC);
43641+ skb_reserve(pNewMsg, 2); /* to align IP */
43642+ SK_MEMCPY(pNewMsg->data,pMsg->data,pMsg->len);
43643+ pNewMsg->ip_summed = pMsg->ip_summed;
43644+ skb_put(pNewMsg, pMsg->len);
43645+ DEV_KFREE_SKB_ANY(pMsg);
43646+ pMsg = pNewMsg;
43647+#endif
43648+ pMsg->dev = pAC->dev[Port];
43649+ pMsg->protocol = eth_type_trans(pMsg,
43650+ pAC->dev[Port]);
43651+ netif_rx(pMsg);
43652+ pAC->dev[Port]->last_rx = jiffies;
43653+ } else { /* drop frame */
43654+ SK_DBG_MSG(NULL,SK_DBGMOD_DRV,
43655+ SK_DBGCAT_DRV_RX_PROGRESS,("D"));
43656+ DEV_KFREE_SKB_ANY(pMsg);
43657+ }
43658+ } else { /* This is an RLMT-packet! */
43659+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
43660+ SK_DBGCAT_DRV_RX_PROGRESS,("R"));
43661+ pRlmtMbuf = SkDrvAllocRlmtMbuf(pAC,
43662+ pAC->IoBase, FrameLength);
43663+ if (pRlmtMbuf != NULL) {
43664+ pRlmtMbuf->pNext = NULL;
43665+ pRlmtMbuf->Length = FrameLength;
43666+ pRlmtMbuf->PortIdx = Port;
43667+ EvPara.pParaPtr = pRlmtMbuf;
43668+ SK_MEMCPY((char*)(pRlmtMbuf->pData),
43669+ (char*)(pMsg->data),FrameLength);
43670+
43671+ if (SlowPathLock == SK_TRUE) {
43672+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
43673+ SkEventQueue(pAC, SKGE_RLMT,
43674+ SK_RLMT_PACKET_RECEIVED,
43675+ EvPara);
43676+ pAC->CheckQueue = SK_TRUE;
43677+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
43678+ } else {
43679+ SkEventQueue(pAC, SKGE_RLMT,
43680+ SK_RLMT_PACKET_RECEIVED,
43681+ EvPara);
43682+ pAC->CheckQueue = SK_TRUE;
43683+ }
43684+
43685+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
43686+ SK_DBGCAT_DRV_RX_PROGRESS,("Q"));
43687+ }
43688+ if (pAC->dev[Port]->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
43689+#ifdef __ia64__
43690+ pNewMsg = alloc_skb(pMsg->len, GFP_ATOMIC);
43691+ skb_reserve(pNewMsg, 2); /* to align IP */
43692+ SK_MEMCPY(pNewMsg->data,pMsg->data,pMsg->len);
43693+ pNewMsg->ip_summed = pMsg->ip_summed;
43694+ pNewMsg->len = pMsg->len;
43695+ DEV_KFREE_SKB_ANY(pMsg);
43696+ pMsg = pNewMsg;
43697+#endif
43698+ pMsg->dev = pAC->dev[Port];
43699+ pMsg->protocol = eth_type_trans(pMsg,pAC->dev[Port]);
43700+ netif_rx(pMsg);
43701+ pAC->dev[Port]->last_rx = jiffies;
43702+ } else {
43703+ DEV_KFREE_SKB_ANY(pMsg);
43704+ }
43705+ } /* if packet for rlmt */
43706+ PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pSkPacket);
43707+ } /* end if-else (IsGoodPkt) */
43708+
43709+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
43710+ ("<== HandleReceives (Port %c)\n", 'A' + Port));
43711+ return(SK_TRUE);
43712+
43713+} /* HandleReceives */
43714+
43715+/***********************************************************************
43716+ *
43717+ * CheckForSendComplete - Frees any freeable Tx bufffer
43718+ *
43719+ * Description:
43720+ * This function checks the queues of a port for completed send
43721+ * packets and returns these packets back to the OS.
43722+ *
43723+ * Notes:
43724+ * This function can run simultaneously for both ports if
43725+ * the OS function OSReturnPacket() can handle this,
43726+ *
43727+ * Such a send complete does not mean, that the packet is really
43728+ * out on the wire. We just know that the adapter has copied it
43729+ * into its internal memory and the buffer in the systems memory
43730+ * is no longer needed.
43731+ *
43732+ * Returns: N/A
43733+ */
43734+static void CheckForSendComplete(
43735+SK_AC *pAC, /* pointer to adapter control context */
43736+SK_IOC IoC, /* I/O control context */
43737+int Port, /* port index */
43738+SK_PKT_QUEUE *pPQ, /* tx working packet queue to check */
43739+SK_LE_TABLE *pLETab, /* corresponding list element table */
43740+unsigned int Done) /* done index reported for this LET */
43741+{
43742+ SK_PACKET *pSkPacket;
43743+ SK_PKT_QUEUE SendCmplPktQ = { NULL, NULL, SPIN_LOCK_UNLOCKED };
43744+ SK_BOOL DoWakeQueue = SK_FALSE;
43745+ unsigned long Flags;
43746+ unsigned Put;
43747+
43748+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43749+ ("==> CheckForSendComplete(Port %c)\n", 'A' + Port));
43750+
43751+ /*
43752+ ** Reset own bit in LE's between old and new Done index
43753+ ** This is not really necessairy but makes debugging easier
43754+ */
43755+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43756+ ("Clear Own Bits in TxTable from %d to %d\n",
43757+ pLETab->Done, (Done == 0) ?
43758+ NUM_LE_IN_TABLE(pLETab) :
43759+ (Done - 1)));
43760+
43761+ spin_lock_irqsave(&(pPQ->QueueLock), Flags);
43762+
43763+ CLEAR_LE_OWN_FROM_DONE_TO(pLETab, Done);
43764+
43765+ Put = GET_PUT_IDX(pLETab);
43766+
43767+ /*
43768+ ** Check whether some packets have been completed
43769+ */
43770+ PLAIN_POP_FIRST_PKT_FROM_QUEUE(pPQ, pSkPacket);
43771+ while (pSkPacket != NULL) {
43772+
43773+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43774+ ("Check Completion of Tx packet %p\n", pSkPacket));
43775+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43776+ ("Put %d NewDone %d NextLe of Packet %d\n", Put, Done,
43777+ pSkPacket->NextLE));
43778+
43779+ if ((Put > Done) &&
43780+ ((pSkPacket->NextLE > Put) || (pSkPacket->NextLE <= Done))) {
43781+ PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(&SendCmplPktQ, pSkPacket);
43782+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43783+ ("Packet finished (a)\n"));
43784+ } else if ((Done > Put) &&
43785+ (pSkPacket->NextLE > Put) && (pSkPacket->NextLE <= Done)) {
43786+ PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(&SendCmplPktQ, pSkPacket);
43787+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43788+ ("Packet finished (b)\n"));
43789+ } else if ((Done == TXA_MAX_LE-1) && (Put == 0) && (pSkPacket->NextLE == 0)) {
43790+ PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(&SendCmplPktQ, pSkPacket);
43791+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43792+ ("Packet finished (b)\n"));
43793+ DoWakeQueue = SK_TRUE;
43794+ } else if (Done == Put) {
43795+ /* all packets have been sent */
43796+ PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(&SendCmplPktQ, pSkPacket);
43797+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43798+ ("Packet finished (c)\n"));
43799+ } else {
43800+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43801+ ("Packet not yet finished\n"));
43802+ PLAIN_PUSH_PKT_AS_FIRST_IN_QUEUE(pPQ, pSkPacket);
43803+ break;
43804+ }
43805+ PLAIN_POP_FIRST_PKT_FROM_QUEUE(pPQ, pSkPacket);
43806+ }
43807+ spin_unlock_irqrestore(&(pPQ->QueueLock), Flags);
43808+
43809+ /*
43810+ ** Set new done index in list element table
43811+ */
43812+ SET_DONE_INDEX(pLETab, Done);
43813+
43814+ /*
43815+ ** All TX packets that are send complete should be added to
43816+ ** the free queue again for new sents to come
43817+ */
43818+ pSkPacket = SendCmplPktQ.pHead;
43819+ while (pSkPacket != NULL) {
43820+ while (pSkPacket->pFrag != NULL) {
43821+ pci_unmap_page(pAC->PciDev,
43822+ (dma_addr_t) pSkPacket->pFrag->pPhys,
43823+ pSkPacket->pFrag->FragLen,
43824+ PCI_DMA_FROMDEVICE);
43825+ pSkPacket->pFrag = pSkPacket->pFrag->pNext;
43826+ }
43827+
43828+ DEV_KFREE_SKB_ANY(pSkPacket->pMBuf);
43829+ pSkPacket->pMBuf = NULL;
43830+ pSkPacket = pSkPacket->pNext; /* get next packet */
43831+ }
43832+
43833+ /*
43834+ ** Append the available TX packets back to free queue
43835+ */
43836+ if (SendCmplPktQ.pHead != NULL) {
43837+ spin_lock_irqsave(&(pAC->TxPort[Port][0].TxQ_free.QueueLock), Flags);
43838+ if (pAC->TxPort[Port][0].TxQ_free.pTail != NULL) {
43839+ pAC->TxPort[Port][0].TxQ_free.pTail->pNext = SendCmplPktQ.pHead;
43840+ pAC->TxPort[Port][0].TxQ_free.pTail = SendCmplPktQ.pTail;
43841+ if (pAC->TxPort[Port][0].TxQ_free.pHead->pNext == NULL) {
43842+ netif_wake_queue(pAC->dev[Port]);
43843+ }
43844+ } else {
43845+ pAC->TxPort[Port][0].TxQ_free.pHead = SendCmplPktQ.pHead;
43846+ pAC->TxPort[Port][0].TxQ_free.pTail = SendCmplPktQ.pTail;
43847+ netif_wake_queue(pAC->dev[Port]);
43848+ }
43849+ if (Done == Put) {
43850+ netif_wake_queue(pAC->dev[Port]);
43851+ }
43852+ if (DoWakeQueue) {
43853+ netif_wake_queue(pAC->dev[Port]);
43854+ DoWakeQueue = SK_FALSE;
43855+ }
43856+ spin_unlock_irqrestore(&pAC->TxPort[Port][0].TxQ_free.QueueLock, Flags);
43857+ }
43858+
43859+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43860+ ("<== CheckForSendComplete()\n"));
43861+
43862+ return;
43863+} /* CheckForSendComplete */
43864+
43865+/*****************************************************************************
43866+ *
43867+ * UnmapAndFreeTxPktBuffer
43868+ *
43869+ * Description:
43870+ * This function free any allocated space of receive buffers
43871+ *
43872+ * Arguments:
43873+ * pAC - A pointer to the adapter context struct.
43874+ *
43875+ */
43876+static void UnmapAndFreeTxPktBuffer(
43877+SK_AC *pAC, /* pointer to adapter context */
43878+SK_PACKET *pSkPacket, /* pointer to port struct of ring to fill */
43879+int TxPort) /* TX port index */
43880+{
43881+ SK_FRAG *pFrag = pSkPacket->pFrag;
43882+
43883+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43884+ ("--> UnmapAndFreeTxPktBuffer\n"));
43885+
43886+ while (pFrag != NULL) {
43887+ pci_unmap_page(pAC->PciDev,
43888+ (dma_addr_t) pFrag->pPhys,
43889+ pFrag->FragLen,
43890+ PCI_DMA_FROMDEVICE);
43891+ pFrag = pFrag->pNext;
43892+ }
43893+
43894+ DEV_KFREE_SKB_ANY(pSkPacket->pMBuf);
43895+ pSkPacket->pMBuf = NULL;
43896+
43897+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
43898+ ("<-- UnmapAndFreeTxPktBuffer\n"));
43899+}
43900+
43901+/*****************************************************************************
43902+ *
43903+ * HandleStatusLEs
43904+ *
43905+ * Description:
43906+ * This function checks for any new status LEs that may have been
43907+ * received. Those status LEs may either be Rx or Tx ones.
43908+ *
43909+ * Returns: N/A
43910+ */
43911+static SK_BOOL HandleStatusLEs(
43912+#ifdef CONFIG_SK98LIN_NAPI
43913+SK_AC *pAC, /* pointer to adapter context */
43914+int *WorkDone, /* Done counter needed for NAPI */
43915+int WorkToDo) /* ToDo counter for NAPI */
43916+#else
43917+SK_AC *pAC) /* pointer to adapter context */
43918+#endif
43919+{
43920+ int DoneTxA[SK_MAX_MACS];
43921+ int DoneTxS[SK_MAX_MACS];
43922+ int Port;
43923+ SK_BOOL handledStatLE = SK_FALSE;
43924+ SK_BOOL NewDone = SK_FALSE;
43925+ SK_HWLE *pLE;
43926+ SK_U16 HighVal;
43927+ SK_U32 LowVal;
43928+ SK_U8 OpCode;
43929+ int i;
43930+
43931+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
43932+ ("==> HandleStatusLEs\n"));
43933+
43934+ do {
43935+ if (OWN_OF_FIRST_LE(&pAC->StatusLETable) != HW_OWNER)
43936+ break;
43937+
43938+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
43939+ ("Check next Own Bit of ST-LE[%d]: 0x%li \n",
43940+ (pAC->StatusLETable.Done + 1) % NUM_LE_IN_TABLE(&pAC->StatusLETable),
43941+ OWN_OF_FIRST_LE(&pAC->StatusLETable)));
43942+
43943+ while (OWN_OF_FIRST_LE(&pAC->StatusLETable) == HW_OWNER) {
43944+ GET_ST_LE(pLE, &pAC->StatusLETable);
43945+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
43946+ ("Working on finished status LE[%d]:\n",
43947+ GET_DONE_INDEX(&pAC->StatusLETable)));
43948+ SK_DBG_DUMP_ST_LE(pLE);
43949+ handledStatLE = SK_TRUE;
43950+ OpCode = STLE_GET_OPC(pLE) & ~HW_OWNER;
43951+ Port = STLE_GET_LINK(pLE);
43952+
43953+#ifdef USE_TIST_FOR_RESET
43954+ if (SK_ADAPTER_WAITING_FOR_TIST(pAC)) {
43955+ /* do we just have a tist LE ? */
43956+ if ((OpCode & OP_RXTIMESTAMP) == OP_RXTIMESTAMP) {
43957+ for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
43958+ if (SK_PORT_WAITING_FOR_ANY_TIST(pAC, i)) {
43959+ /* if a port is waiting for any tist it is done */
43960+ SK_CLR_STATE_FOR_PORT(pAC, i);
43961+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
43962+ ("Got any Tist on port %c (now 0x%X!!!)\n",
43963+ 'A' + i, pAC->AdapterResetState));
43964+ }
43965+ if (SK_PORT_WAITING_FOR_SPECIFIC_TIST(pAC, i)) {
43966+ Y2_GET_TIST_LOW_VAL(pAC->IoBase, &LowVal);
43967+ if ((pAC->MinTistHi != pAC->GIni.GITimeStampCnt) ||
43968+ (pAC->MinTistLo < LowVal)) {
43969+ /* time is up now */
43970+ SK_CLR_STATE_FOR_PORT(pAC, i);
43971+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
43972+ ("Got expected Tist on Port %c (now 0x%X)!!!\n",
43973+ 'A' + i, pAC->AdapterResetState));
43974+#ifdef Y2_SYNC_CHECK
43975+ pAC->FramesWithoutSyncCheck =
43976+ Y2_RESYNC_WATERMARK;
43977+#endif
43978+ } else {
43979+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
43980+ ("Got Tist %l:%l on Port %c but still waiting\n",
43981+ pAC->GIni.GITimeStampCnt, pAC->MinTistLo,
43982+ 'A' + i));
43983+ }
43984+ }
43985+ }
43986+#ifndef Y2_RECOVERY
43987+ if (!SK_ADAPTER_WAITING_FOR_TIST(pAC)) {
43988+ /* nobody needs tist anymore - turn it off */
43989+ Y2_DISABLE_TIST(pAC->IoBase);
43990+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
43991+ ("Turn off Tist !!!\n"));
43992+ }
43993+#endif
43994+ } else if (OpCode == OP_TXINDEXLE) {
43995+ /*
43996+ * change OpCode to notify the folowing code
43997+ * to ignore the done index from this LE
43998+ * unfortunately tist LEs will be generated only
43999+ * for RxStat LEs
44000+ * so in order to get a safe Done index for a
44001+ * port currently waiting for a tist we have to
44002+ * get the done index directly from the BMU
44003+ */
44004+ OpCode = OP_MOD_TXINDEX;
44005+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
44006+ ("Mark unusable TX_INDEX LE!!!\n"));
44007+ } else {
44008+ if (SK_PORT_WAITING_FOR_TIST(pAC, Port)) {
44009+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
44010+ ("Ignore LE 0x%X on Port %c!!!\n",
44011+ OpCode, 'A' + Port));
44012+ OpCode = OP_MOD_LE;
44013+#ifdef Y2_LE_CHECK
44014+ /* mark entries invalid */
44015+ pAC->LastOpc = 0xFF;
44016+ pAC->LastPort = 3;
44017+#endif
44018+ }
44019+ }
44020+ } /* if (SK_ADAPTER_WAITING_FOR_TIST(pAC)) */
44021+#endif
44022+
44023+
44024+
44025+
44026+
44027+#ifdef Y2_LE_CHECK
44028+ if (pAC->LastOpc != 0xFF) {
44029+ /* last opc is valid
44030+ * check if current opcode follows last opcode
44031+ */
44032+ if ((((OpCode & OP_RXTIMESTAMP) == OP_RXTIMESTAMP) && (pAC->LastOpc != OP_RXSTAT)) ||
44033+ (((OpCode & OP_RXCHKS) == OP_RXCHKS) && (pAC->LastOpc != OP_RXTIMESTAMP)) ||
44034+ ((OpCode == OP_RXSTAT) && (pAC->LastOpc != OP_RXCHKS))) {
44035+
44036+ /* opcode sequence broken
44037+ * current LE is invalid
44038+ */
44039+
44040+ if (pAC->LastOpc == OP_RXTIMESTAMP) {
44041+ /* force invalid checksum */
44042+ pLE->St.StUn.StRxTCPCSum.RxTCPSum1 = 1;
44043+ pLE->St.StUn.StRxTCPCSum.RxTCPSum2 = 0;
44044+ OpCode = pAC->LastOpc = OP_RXCHKS;
44045+ Port = pAC->LastPort;
44046+ } else if (pAC->LastOpc == OP_RXCHKS) {
44047+ /* force invalid frame */
44048+ Port = pAC->LastPort;
44049+ pLE->St.Stat.BufLen = 64;
44050+ pLE->St.StUn.StRxStatWord = GMR_FS_CRC_ERR;
44051+ OpCode = pAC->LastOpc = OP_RXSTAT;
44052+#ifdef Y2_SYNC_CHECK
44053+ /* force rx sync check */
44054+ pAC->FramesWithoutSyncCheck = Y2_RESYNC_WATERMARK;
44055+#endif
44056+ } else if (pAC->LastOpc == OP_RXSTAT) {
44057+ /* create dont care tist */
44058+ pLE->St.StUn.StRxTimeStamp = 0;
44059+ OpCode = pAC->LastOpc = OP_RXTIMESTAMP;
44060+ /* dont know the port yet */
44061+ } else {
44062+#ifdef DEBUG
44063+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
44064+ ("Unknown LastOpc %X for Timestamp on port %c.\n",
44065+ pAC->LastOpc, Port));
44066+#endif
44067+ }
44068+ }
44069+ }
44070+#endif
44071+
44072+ switch (OpCode) {
44073+ case OP_RXSTAT:
44074+#ifdef Y2_RECOVERY
44075+ pAC->LastOpc = OP_RXSTAT;
44076+#endif
44077+ /*
44078+ ** This is always the last Status LE belonging
44079+ ** to a received packet -> handle it...
44080+ */
44081+ if ((Port != 0) && (Port != 1)) {
44082+ /* Unknown port */
44083+ panic("sk98lin: Unknown port %d\n",
44084+ Port);
44085+ }
44086+
44087+ HandleReceives(
44088+ pAC,
44089+ Port,
44090+ STLE_GET_LEN(pLE),
44091+ STLE_GET_FRSTATUS(pLE),
44092+ pAC->StatusLETable.Bmu.Stat.TcpSum1,
44093+ pAC->StatusLETable.Bmu.Stat.TcpSum2,
44094+ pAC->StatusLETable.Bmu.Stat.RxTimeStamp,
44095+ pAC->StatusLETable.Bmu.Stat.VlanId);
44096+#ifdef CONFIG_SK98LIN_NAPI
44097+ if (*WorkDone >= WorkToDo) {
44098+ break;
44099+ }
44100+ (*WorkDone)++;
44101+#endif
44102+ break;
44103+ case OP_RXVLAN:
44104+ /* this value will be used for next RXSTAT */
44105+ pAC->StatusLETable.Bmu.Stat.VlanId = STLE_GET_VLAN(pLE);
44106+ break;
44107+ case OP_RXTIMEVLAN:
44108+ /* this value will be used for next RXSTAT */
44109+ pAC->StatusLETable.Bmu.Stat.VlanId = STLE_GET_VLAN(pLE);
44110+ /* fall through */
44111+ case OP_RXTIMESTAMP:
44112+ /* this value will be used for next RXSTAT */
44113+ pAC->StatusLETable.Bmu.Stat.RxTimeStamp = STLE_GET_TIST(pLE);
44114+#ifdef Y2_RECOVERY
44115+ pAC->LastOpc = OP_RXTIMESTAMP;
44116+ pAC->LastPort = Port;
44117+#endif
44118+ break;
44119+ case OP_RXCHKSVLAN:
44120+ /* this value will be used for next RXSTAT */
44121+ pAC->StatusLETable.Bmu.Stat.VlanId = STLE_GET_VLAN(pLE);
44122+ /* fall through */
44123+ case OP_RXCHKS:
44124+ /* this value will be used for next RXSTAT */
44125+ pAC->StatusLETable.Bmu.Stat.TcpSum1 = STLE_GET_TCP1(pLE);
44126+ pAC->StatusLETable.Bmu.Stat.TcpSum2 = STLE_GET_TCP2(pLE);
44127+#ifdef Y2_RECOVERY
44128+ pAC->LastPort = Port;
44129+ pAC->LastOpc = OP_RXCHKS;
44130+#endif
44131+ break;
44132+ case OP_RSS_HASH:
44133+ /* this value will be used for next RXSTAT */
44134+#if 0
44135+ pAC->StatusLETable.Bmu.Stat.RssHashValue = STLE_GET_RSS(pLE);
44136+#endif
44137+ break;
44138+ case OP_TXINDEXLE:
44139+ /*
44140+ ** :;:; TODO
44141+ ** it would be possible to check for which queues
44142+ ** the index has been changed and call
44143+ ** CheckForSendComplete() only for such queues
44144+ */
44145+ STLE_GET_DONE_IDX(pLE,LowVal,HighVal);
44146+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
44147+ ("LowVal: 0x%x HighVal: 0x%x\n", LowVal, HighVal));
44148+
44149+ /*
44150+ ** It would be possible to check whether we really
44151+ ** need the values for second port or sync queue,
44152+ ** but I think checking whether we need them is
44153+ ** more expensive than the calculation
44154+ */
44155+ DoneTxA[0] = STLE_GET_DONE_IDX_TXA1(LowVal,HighVal);
44156+ DoneTxS[0] = STLE_GET_DONE_IDX_TXS1(LowVal,HighVal);
44157+ DoneTxA[1] = STLE_GET_DONE_IDX_TXA2(LowVal,HighVal);
44158+ DoneTxS[1] = STLE_GET_DONE_IDX_TXS2(LowVal,HighVal);
44159+
44160+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
44161+ ("DoneTxa1 0x%x DoneTxS1: 0x%x DoneTxa2 0x%x DoneTxS2: 0x%x\n",
44162+ DoneTxA[0], DoneTxS[0], DoneTxA[1], DoneTxS[1]));
44163+
44164+ NewDone = SK_TRUE;
44165+ break;
44166+#ifdef USE_TIST_FOR_RESET
44167+ case OP_MOD_TXINDEX:
44168+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
44169+ ("OP_MOD_TXINDEX\n"));
44170+ SK_IN16(pAC->IoBase, Q_ADDR(Q_XA1, Q_DONE), &DoneTxA[0]);
44171+ if (pAC->GIni.GIMacsFound > 1) {
44172+ SK_IN16(pAC->IoBase, Q_ADDR(Q_XA2, Q_DONE), &DoneTxA[1]);
44173+ }
44174+ NewDone = SK_TRUE;
44175+ break;
44176+ case OP_MOD_LE:
44177+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
44178+ ("Ignore marked LE on port in Reset\n"));
44179+ break;
44180+#endif
44181+
44182+ default:
44183+ /*
44184+ ** Have to handle the illegal Opcode in Status LE
44185+ */
44186+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
44187+ ("Unexpected OpCode\n"));
44188+ break;
44189+ }
44190+
44191+#ifdef Y2_RECOVERY
44192+ OpCode = STLE_GET_OPC(pLE) & ~HW_OWNER;
44193+ STLE_SET_OPC(pLE, OpCode);
44194+#else
44195+ /*
44196+ ** Reset own bit we have to do this in order to detect a overflow
44197+ */
44198+ STLE_SET_OPC(pLE, SW_OWNER);
44199+#endif
44200+ } /* while (OWN_OF_FIRST_LE(&pAC->StatusLETable) == HW_OWNER) */
44201+
44202+ /*
44203+ ** Now handle any new transmit complete
44204+ */
44205+ if (NewDone) {
44206+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
44207+ ("Done Index for Tx BMU has been changed\n"));
44208+ for (Port = 0; Port < pAC->GIni.GIMacsFound; Port++) {
44209+ /*
44210+ ** Do we have a new Done idx ?
44211+ */
44212+ if (DoneTxA[Port] != GET_DONE_INDEX(&pAC->TxPort[Port][0].TxALET)) {
44213+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
44214+ ("Check TxA%d\n", Port + 1));
44215+ CheckForSendComplete(pAC, pAC->IoBase, Port,
44216+ &(pAC->TxPort[Port][0].TxAQ_working),
44217+ &pAC->TxPort[Port][0].TxALET,
44218+ DoneTxA[Port]);
44219+ } else {
44220+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
44221+ ("No changes for TxA%d\n", Port + 1));
44222+ }
44223+#if USE_SYNC_TX_QUEUE
44224+ if (HW_SYNC_TX_SUPPORTED(pAC)) {
44225+ /*
44226+ ** Do we have a new Done idx ?
44227+ */
44228+ if (DoneTxS[Port] !=
44229+ GET_DONE_INDEX(&pAC->TxPort[Port][0].TxSLET)) {
44230+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
44231+ SK_DBGCAT_DRV_INT_SRC,
44232+ ("Check TxS%d\n", Port));
44233+ CheckForSendComplete(pAC, pAC->IoBase, Port,
44234+ &(pAC->TxPort[Port][0].TxSQ_working),
44235+ &pAC->TxPort[Port][0].TxSLET,
44236+ DoneTxS[Port]);
44237+ } else {
44238+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
44239+ SK_DBGCAT_DRV_INT_SRC,
44240+ ("No changes for TxS%d\n", Port));
44241+ }
44242+ }
44243+#endif
44244+ }
44245+ }
44246+ NewDone = SK_FALSE;
44247+
44248+ /*
44249+ ** Check whether we have to refill our RX table
44250+ */
44251+ if (HW_FEATURE(pAC, HWF_WA_DEV_420)) {
44252+ if (NbrRxBuffersInHW < MAX_NBR_RX_BUFFERS_IN_HW) {
44253+ for (Port = 0; Port < pAC->GIni.GIMacsFound; Port++) {
44254+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
44255+ ("Check for refill of RxBuffers on Port %c\n", 'A' + Port));
44256+ FillReceiveTableYukon2(pAC, pAC->IoBase, Port);
44257+ }
44258+ }
44259+ } else {
44260+ for (Port = 0; Port < pAC->GIni.GIMacsFound; Port++) {
44261+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
44262+ ("Check for refill of RxBuffers on Port %c\n", 'A' + Port));
44263+ if (NUM_FREE_LE_IN_TABLE(&pAC->RxPort[Port].RxLET) >= 64) {
44264+ FillReceiveTableYukon2(pAC, pAC->IoBase, Port);
44265+ }
44266+ }
44267+ }
44268+#ifdef CONFIG_SK98LIN_NAPI
44269+ if (*WorkDone >= WorkToDo) {
44270+ break;
44271+ }
44272+#endif
44273+ } while (OWN_OF_FIRST_LE(&pAC->StatusLETable) == HW_OWNER);
44274+
44275+ /*
44276+ ** Clear status BMU
44277+ */
44278+ if (handledStatLE)
44279+ SK_OUT32(pAC->IoBase, STAT_CTRL, SC_STAT_CLR_IRQ);
44280+
44281+ return(handledStatLE);
44282+} /* HandleStatusLEs */
44283+
44284+/*****************************************************************************
44285+ *
44286+ * AllocateAndInitLETables - allocate memory for the LETable and init
44287+ *
44288+ * Description:
44289+ * This function will allocate space for the LETable and will also
44290+ * initialize them. The size of the tables must have been specified
44291+ * before.
44292+ *
44293+ * Arguments:
44294+ * pAC - A pointer to the adapter context struct.
44295+ *
44296+ * Returns:
44297+ * SK_TRUE - all LETables initialized
44298+ * SK_FALSE - failed
44299+ */
44300+static SK_BOOL AllocateAndInitLETables(
44301+SK_AC *pAC) /* pointer to adapter context */
44302+{
44303+ char *pVirtMemAddr;
44304+ dma_addr_t pPhysMemAddr = 0;
44305+ SK_U32 CurrMac;
44306+ unsigned Size;
44307+ unsigned Aligned;
44308+ unsigned Alignment;
44309+
44310+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
44311+ ("==> AllocateAndInitLETables()\n"));
44312+
44313+ /*
44314+ ** Determine how much memory we need with respect to alignment
44315+ */
44316+ Alignment = MAX_LEN_OF_LE_TAB;
44317+ Size = 0;
44318+ for (CurrMac = 0; CurrMac < pAC->GIni.GIMacsFound; CurrMac++) {
44319+ SK_ALIGN_SIZE(LE_TAB_SIZE(RX_MAX_LE), Alignment, Aligned);
44320+ Size += Aligned;
44321+ SK_ALIGN_SIZE(LE_TAB_SIZE(TXA_MAX_LE), Alignment, Aligned);
44322+ Size += Aligned;
44323+ SK_ALIGN_SIZE(LE_TAB_SIZE(TXS_MAX_LE), Alignment, Aligned);
44324+ Size += Aligned;
44325+ }
44326+ SK_ALIGN_SIZE(LE_TAB_SIZE(ST_MAX_LE), Alignment, Aligned);
44327+ Size += Aligned;
44328+ Size += Alignment;
44329+ pAC->SizeOfAlignedLETables = Size;
44330+
44331+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
44332+ ("Need %08x bytes in total\n", Size));
44333+
44334+ /*
44335+ ** Allocate the memory
44336+ */
44337+ pVirtMemAddr = pci_alloc_consistent(pAC->PciDev, Size, &pPhysMemAddr);
44338+ if (pVirtMemAddr == NULL) {
44339+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
44340+ SK_DBGCAT_INIT | SK_DBGCAT_DRV_ERROR,
44341+ ("AllocateAndInitLETables: kernel malloc failed!\n"));
44342+ return (SK_FALSE);
44343+ }
44344+
44345+ /*
44346+ ** Initialize the memory
44347+ */
44348+ SK_MEMSET(pVirtMemAddr, 0, Size);
44349+ ALIGN_ADDR(pVirtMemAddr, Alignment); /* Macro defined in skgew.h */
44350+
44351+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
44352+ ("Virtual address of LETab is %8p!\n", pVirtMemAddr));
44353+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
44354+ ("Phys address of LETab is %8p!\n", (void *) pPhysMemAddr));
44355+
44356+ for (CurrMac = 0; CurrMac < pAC->GIni.GIMacsFound; CurrMac++) {
44357+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
44358+ ("RxLeTable for Port %c", 'A' + CurrMac));
44359+ SkGeY2InitSingleLETable(
44360+ pAC,
44361+ &pAC->RxPort[CurrMac].RxLET,
44362+ RX_MAX_LE,
44363+ pVirtMemAddr,
44364+ (SK_U32) (pPhysMemAddr & 0xffffffff),
44365+ (SK_U32) (((SK_U64) pPhysMemAddr) >> 32));
44366+
44367+ SK_ALIGN_SIZE(LE_TAB_SIZE(RX_MAX_LE), Alignment, Aligned);
44368+ pVirtMemAddr += Aligned;
44369+ pPhysMemAddr += Aligned;
44370+
44371+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
44372+ ("TxALeTable for Port %c", 'A' + CurrMac));
44373+ SkGeY2InitSingleLETable(
44374+ pAC,
44375+ &pAC->TxPort[CurrMac][0].TxALET,
44376+ TXA_MAX_LE,
44377+ pVirtMemAddr,
44378+ (SK_U32) (pPhysMemAddr & 0xffffffff),
44379+ (SK_U32) (((SK_U64) pPhysMemAddr) >> 32));
44380+
44381+ SK_ALIGN_SIZE(LE_TAB_SIZE(TXA_MAX_LE), Alignment, Aligned);
44382+ pVirtMemAddr += Aligned;
44383+ pPhysMemAddr += Aligned;
44384+
44385+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
44386+ ("TxSLeTable for Port %c", 'A' + CurrMac));
44387+ SkGeY2InitSingleLETable(
44388+ pAC,
44389+ &pAC->TxPort[CurrMac][0].TxSLET,
44390+ TXS_MAX_LE,
44391+ pVirtMemAddr,
44392+ (SK_U32) (pPhysMemAddr & 0xffffffff),
44393+ (SK_U32) (((SK_U64) pPhysMemAddr) >> 32));
44394+
44395+ SK_ALIGN_SIZE(LE_TAB_SIZE(TXS_MAX_LE), Alignment, Aligned);
44396+ pVirtMemAddr += Aligned;
44397+ pPhysMemAddr += Aligned;
44398+ }
44399+
44400+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,("StLeTable"));
44401+
44402+ SkGeY2InitSingleLETable(
44403+ pAC,
44404+ &pAC->StatusLETable,
44405+ ST_MAX_LE,
44406+ pVirtMemAddr,
44407+ (SK_U32) (pPhysMemAddr & 0xffffffff),
44408+ (SK_U32) (((SK_U64) pPhysMemAddr) >> 32));
44409+
44410+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
44411+ ("<== AllocateAndInitLETables(OK)\n"));
44412+ return(SK_TRUE);
44413+} /* AllocateAndInitLETables */
44414+
44415+/*****************************************************************************
44416+ *
44417+ * AllocatePacketBuffersYukon2 - allocate packet and fragment buffers
44418+ *
44419+ * Description:
44420+ * This function will allocate space for the packets and fragments
44421+ *
44422+ * Arguments:
44423+ * pAC - A pointer to the adapter context struct.
44424+ *
44425+ * Returns:
44426+ * SK_TRUE - Memory was allocated correctly
44427+ * SK_FALSE - An error occured
44428+ */
44429+static SK_BOOL AllocatePacketBuffersYukon2(
44430+SK_AC *pAC) /* pointer to adapter context */
44431+{
44432+ SK_PACKET *pRxPacket;
44433+ SK_PACKET *pTxPacket;
44434+ SK_U32 CurrBuff;
44435+ SK_U32 CurrMac;
44436+ unsigned long Flags; /* needed for POP/PUSH functions */
44437+
44438+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
44439+ ("==> AllocatePacketBuffersYukon2()"));
44440+
44441+ for (CurrMac = 0; CurrMac < pAC->GIni.GIMacsFound; CurrMac++) {
44442+ /*
44443+ ** Allocate RX packet space, initialize the packets and
44444+ ** add them to the RX waiting queue. Waiting queue means
44445+ ** that packet and fragment are initialized, but no sk_buff
44446+ ** has been assigned to it yet.
44447+ */
44448+ pAC->RxPort[CurrMac].ReceivePacketTable =
44449+ kmalloc((RX_MAX_NBR_BUFFERS * sizeof(SK_PACKET)), GFP_KERNEL);
44450+
44451+ if (pAC->RxPort[CurrMac].ReceivePacketTable == NULL) {
44452+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_INIT | SK_DBGCAT_DRV_ERROR,
44453+ ("AllocatePacketBuffersYukon2: no mem RxPkts (port %i)",CurrMac));
44454+ break;
44455+ } else {
44456+ SK_MEMSET(pAC->RxPort[CurrMac].ReceivePacketTable, 0,
44457+ (RX_MAX_NBR_BUFFERS * sizeof(SK_PACKET)));
44458+
44459+ pRxPacket = pAC->RxPort[CurrMac].ReceivePacketTable;
44460+
44461+ for (CurrBuff=0;CurrBuff<RX_MAX_NBR_BUFFERS;CurrBuff++) {
44462+ pRxPacket->pFrag = &(pRxPacket->FragArray[0]);
44463+ pRxPacket->NumFrags = 1;
44464+ PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[CurrMac].RxQ_waiting, pRxPacket);
44465+ pRxPacket++;
44466+ }
44467+ }
44468+
44469+ /*
44470+ ** Allocate TX packet space, initialize the packets and
44471+ ** add them to the TX free queue. Free queue means that
44472+ ** packet is available and initialized, but no fragment
44473+ ** has been assigned to it. (Must be done at TX side)
44474+ */
44475+ pAC->TxPort[CurrMac][0].TransmitPacketTable =
44476+ kmalloc((TX_MAX_NBR_BUFFERS * sizeof(SK_PACKET)), GFP_KERNEL);
44477+
44478+ if (pAC->TxPort[CurrMac][0].TransmitPacketTable == NULL) {
44479+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_INIT | SK_DBGCAT_DRV_ERROR,
44480+ ("AllocatePacketBuffersYukon2: no mem TxPkts (port %i)",CurrMac));
44481+ kfree(pAC->RxPort[CurrMac].ReceivePacketTable);
44482+ return(SK_FALSE);
44483+ } else {
44484+ SK_MEMSET(pAC->TxPort[CurrMac][0].TransmitPacketTable, 0,
44485+ (TX_MAX_NBR_BUFFERS * sizeof(SK_PACKET)));
44486+
44487+ pTxPacket = pAC->TxPort[CurrMac][0].TransmitPacketTable;
44488+
44489+ for (CurrBuff=0;CurrBuff<TX_MAX_NBR_BUFFERS;CurrBuff++) {
44490+ PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->TxPort[CurrMac][0].TxQ_free, pTxPacket);
44491+ pTxPacket++;
44492+ }
44493+ }
44494+ } /* end for (CurrMac = 0; CurrMac < pAC->GIni.GIMacsFound; CurrMac++) */
44495+
44496+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
44497+ ("<== AllocatePacketBuffersYukon2 (OK)\n"));
44498+ return(SK_TRUE);
44499+
44500+} /* AllocatePacketBuffersYukon2 */
44501+
44502+/*****************************************************************************
44503+ *
44504+ * FreeLETables - release allocated memory of LETables
44505+ *
44506+ * Description:
44507+ * This function will free all resources of the LETables
44508+ *
44509+ * Arguments:
44510+ * pAC - A pointer to the adapter context struct.
44511+ *
44512+ * Returns: N/A
44513+ */
44514+static void FreeLETables(
44515+SK_AC *pAC) /* pointer to adapter control context */
44516+{
44517+ dma_addr_t pPhysMemAddr;
44518+ char *pVirtMemAddr;
44519+
44520+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
44521+ ("==> FreeLETables()\n"));
44522+
44523+ /*
44524+ ** The RxLETable is the first of all LET.
44525+ ** Therefore we can use its address for the input
44526+ ** of the free function.
44527+ */
44528+ pVirtMemAddr = (char *) pAC->RxPort[0].RxLET.pLETab;
44529+ pPhysMemAddr = (((SK_U64) pAC->RxPort[0].RxLET.pPhyLETABHigh << (SK_U64) 32) |
44530+ ((SK_U64) pAC->RxPort[0].RxLET.pPhyLETABLow));
44531+
44532+ /* free continuous memory */
44533+ pci_free_consistent(pAC->PciDev, pAC->SizeOfAlignedLETables,
44534+ pVirtMemAddr, pPhysMemAddr);
44535+
44536+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
44537+ ("<== FreeLETables()\n"));
44538+} /* FreeLETables */
44539+
44540+/*****************************************************************************
44541+ *
44542+ * FreePacketBuffers - free's all packet buffers of an adapter
44543+ *
44544+ * Description:
44545+ * This function will free all previously allocated memory of the
44546+ * packet buffers.
44547+ *
44548+ * Arguments:
44549+ * pAC - A pointer to the adapter context struct.
44550+ *
44551+ * Returns: N/A
44552+ */
44553+static void FreePacketBuffers(
44554+SK_AC *pAC) /* pointer to adapter control context */
44555+{
44556+ int Port;
44557+
44558+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
44559+ ("==> FreePacketBuffers()\n"));
44560+
44561+ for (Port = 0; Port < pAC->GIni.GIMacsFound; Port++) {
44562+ kfree(pAC->RxPort[Port].ReceivePacketTable);
44563+ kfree(pAC->TxPort[Port][0].TransmitPacketTable);
44564+ }
44565+
44566+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
44567+ ("<== FreePacketBuffers()\n"));
44568+} /* FreePacketBuffers */
44569+
44570+/*****************************************************************************
44571+ *
44572+ * AllocAndMapRxBuffer - fill one buffer into the receive packet/fragment
44573+ *
44574+ * Description:
44575+ * The function allocates a new receive buffer and assigns it to the
44576+ * the passsed receive packet/fragment
44577+ *
44578+ * Returns:
44579+ * SK_TRUE - a buffer was allocated and assigned
44580+ * SK_FALSE - a buffer could not be added
44581+ */
44582+static SK_BOOL AllocAndMapRxBuffer(
44583+SK_AC *pAC, /* pointer to the adapter control context */
44584+SK_PACKET *pSkPacket, /* pointer to packet that is to fill */
44585+int Port) /* port the packet belongs to */
44586+{
44587+ struct sk_buff *pMsgBlock; /* pointer to a new message block */
44588+ SK_U64 PhysAddr; /* physical address of a rx buffer */
44589+
44590+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
44591+ ("--> AllocAndMapRxBuffer (Port: %i)\n", Port));
44592+
44593+ pMsgBlock = alloc_skb(pAC->RxPort[Port].RxBufSize, GFP_ATOMIC);
44594+ if (pMsgBlock == NULL) {
44595+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
44596+ SK_DBGCAT_DRV_RX_PROGRESS | SK_DBGCAT_DRV_ERROR,
44597+ ("%s: Allocation of rx buffer failed !\n",
44598+ pAC->dev[Port]->name));
44599+ SK_PNMI_CNT_NO_RX_BUF(pAC, pAC->RxPort[Port].PortIndex);
44600+ return(SK_FALSE);
44601+ }
44602+ skb_reserve(pMsgBlock, 8);
44603+
44604+ PhysAddr = (SK_U64) pci_map_page(pAC->PciDev,
44605+ virt_to_page(pMsgBlock->data),
44606+ ((unsigned long) pMsgBlock->data &
44607+ ~PAGE_MASK),
44608+ pAC->RxPort[Port].RxBufSize,
44609+ PCI_DMA_FROMDEVICE);
44610+
44611+ pSkPacket->pFrag->pVirt = pMsgBlock->data;
44612+ pSkPacket->pFrag->pPhys = PhysAddr;
44613+ pSkPacket->pFrag->FragLen = pAC->RxPort[Port].RxBufSize; /* for correct unmap */
44614+ pSkPacket->pMBuf = pMsgBlock;
44615+ pSkPacket->PacketLen = pAC->RxPort[Port].RxBufSize;
44616+
44617+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
44618+ ("<-- AllocAndMapRxBuffer\n"));
44619+
44620+ return (SK_TRUE);
44621+} /* AllocAndMapRxBuffer */
44622+
44623+/*******************************************************************************
44624+ *
44625+ * End of file
44626+ *
44627+ ******************************************************************************/
44628diff -urN linux-2.6.17.orig/drivers/net/sk98lin/sky2le.c linux-2.6.17/drivers/net/sk98lin/sky2le.c
44629--- linux-2.6.17.orig/drivers/net/sk98lin/sky2le.c 1970-01-01 01:00:00.000000000 +0100
44630+++ linux-2.6.17/drivers/net/sk98lin/sky2le.c 2006-04-27 11:43:44.000000000 +0200
44631@@ -0,0 +1,507 @@
44632+/*****************************************************************************
44633+ *
44634+ * Name: sky2le.c
44635+ * Project: Gigabit Ethernet Adapters, Common Modules
44636+ * Version: $Revision$
44637+ * Date: $Date$
44638+ * Purpose: Functions for handling List Element Tables
44639+ *
44640+ *****************************************************************************/
44641+
44642+/******************************************************************************
44643+ *
44644+ * LICENSE:
44645+ * (C)Copyright 2002-2006 Marvell.
44646+ *
44647+ * This program is free software; you can redistribute it and/or modify
44648+ * it under the terms of the GNU General Public License as published by
44649+ * the Free Software Foundation; either version 2 of the License, or
44650+ * (at your option) any later version.
44651+ * The information in this file is provided "AS IS" without warranty.
44652+ * /LICENSE
44653+ *
44654+ ******************************************************************************/
44655+
44656+/*****************************************************************************
44657+ *
44658+ * Description:
44659+ *
44660+ * This module contains the code necessary for handling List Elements.
44661+ *
44662+ * Supported Gigabit Ethernet Chipsets:
44663+ * Yukon-2 (PCI, PCI-X, PCI-Express)
44664+ *
44665+ * Include File Hierarchy:
44666+ *
44667+ *
44668+ *****************************************************************************/
44669+#include "h/skdrv1st.h"
44670+#include "h/skdrv2nd.h"
44671+
44672+/* defines *******************************************************************/
44673+/* typedefs ******************************************************************/
44674+/* global variables **********************************************************/
44675+/* local variables ***********************************************************/
44676+
44677+#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
44678+static const char SysKonnectFileId[] =
44679+ "@(#) $Id$ (C) Marvell.";
44680+#endif /* DEBUG || (!LINT && !SK_SLIM) */
44681+
44682+/* function prototypes *******************************************************/
44683+
44684+/*****************************************************************************
44685+ *
44686+ * SkGeY2InitSingleLETable() - initializes a list element table
44687+ *
44688+ * Description:
44689+ * This function will initialize the selected list element table.
44690+ * Should be called once during DriverInit. No InitLevel required.
44691+ *
44692+ * Arguments:
44693+ * pAC - pointer to the adapter context struct.
44694+ * pLETab - pointer to list element table structure
44695+ * NumLE - number of list elements in this table
44696+ * pVMem - virtual address of memory allocated for this LE table
44697+ * PMemLowAddr - physical address of memory to be used for the LE table
44698+ * PMemHighAddr
44699+ *
44700+ * Returns:
44701+ * nothing
44702+ */
44703+void SkGeY2InitSingleLETable(
44704+SK_AC *pAC, /* pointer to adapter context */
44705+SK_LE_TABLE *pLETab, /* pointer to list element table to be initialized */
44706+unsigned int NumLE, /* number of list elements to be filled in tab */
44707+void *pVMem, /* virtual address of memory used for list elements */
44708+SK_U32 PMemLowAddr, /* physical addr of mem used for LE */
44709+SK_U32 PMemHighAddr)
44710+{
44711+ unsigned int i;
44712+
44713+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44714+ ("==> SkGeY2InitSingleLETable()\n"));
44715+
44716+#ifdef DEBUG
44717+ if (NumLE != 2) { /* not table for polling unit */
44718+ if ((NumLE % MIN_LEN_OF_LE_TAB) != 0 || NumLE > MAX_LEN_OF_LE_TAB) {
44719+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
44720+ ("ERROR: Illegal number of list elements %d\n", NumLE));
44721+ }
44722+ }
44723+#endif /* DEBUG */
44724+
44725+ /* special case: unused list element table */
44726+ if (NumLE == 0) {
44727+ PMemLowAddr = 0;
44728+ PMemHighAddr = 0;
44729+ pVMem = 0;
44730+ }
44731+
44732+ /*
44733+ * in order to get the best possible performance the macros to access
44734+ * list elements use & instead of %
44735+ * this requires the length of LE tables to be a power of 2
44736+ */
44737+
44738+ /*
44739+ * this code guarantees that we use the next power of 2 below the
44740+ * value specified for NumLe - this way some LEs in the table may
44741+ * not be used but the macros work correctly
44742+ * this code does not check for bad values below 128 because in such a
44743+ * case we cannot do anything here
44744+ */
44745+
44746+ if ((NumLE != 2) && (NumLE != 0)) {
44747+ /* no check for polling unit and unused sync Tx */
44748+ i = MIN_LEN_OF_LE_TAB;
44749+ while (NumLE > i) {
44750+ i *= 2;
44751+ if (i > MAX_LEN_OF_LE_TAB) {
44752+ break;
44753+ }
44754+ }
44755+ if (NumLE != i) {
44756+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
44757+ ("ERROR: Illegal number of list elements %d adjusted to %d\n",
44758+ NumLE, (i / 2)));
44759+ NumLE = i / 2;
44760+ }
44761+ }
44762+
44763+ /* set addresses */
44764+ pLETab->pPhyLETABLow = PMemLowAddr;
44765+ pLETab->pPhyLETABHigh = PMemHighAddr;
44766+ pLETab->pLETab = pVMem;
44767+
44768+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44769+ ("contains %d LEs", NumLE));
44770+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44771+ (" and starts at virt %08lx and phys %08lx:%08lx\n",
44772+ pVMem, PMemHighAddr, PMemLowAddr));
44773+
44774+ /* initialize indexes */
44775+ pLETab->Done = 0;
44776+ pLETab->Put = 0;
44777+ pLETab->HwPut = 0;
44778+ /* initialize size */
44779+ pLETab->Num = NumLE;
44780+
44781+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44782+ ("<== SkGeY2InitSingleLETable()\n"));
44783+} /* SkGeY2InitSingleLETable */
44784+
44785+/*****************************************************************************
44786+ *
44787+ * SkGeY2InitPrefetchUnit() - Initialize a Prefetch Unit
44788+ *
44789+ * Description:
44790+ * Calling this function requires an already configured list element
44791+ * table. The prefetch unit to be configured is specified in the parameter
44792+ * 'Queue'. The function is able to initialze the prefetch units of
44793+ * the following queues: Q_R1, Q_R2, Q_XS1, Q_XS2, Q_XA1, Q_XA2.
44794+ * The funcution should be called before SkGeInitPort().
44795+ *
44796+ * Arguments:
44797+ * pAC - pointer to the adapter context struct.
44798+ * IoC - I/O context.
44799+ * Queue - I/O offset of queue e.g. Q_XA1.
44800+ * pLETab - pointer to list element table to be initialized
44801+ *
44802+ * Returns: N/A
44803+ */
44804+void SkGeY2InitPrefetchUnit(
44805+SK_AC *pAC, /* pointer to adapter context */
44806+SK_IOC IoC, /* I/O context */
44807+unsigned int Queue, /* Queue offset for finding the right registers */
44808+SK_LE_TABLE *pLETab) /* pointer to list element table to be initialized */
44809+{
44810+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44811+ ("==> SkGeY2InitPrefetchUnit()\n"));
44812+
44813+#ifdef DEBUG
44814+ if (Queue != Q_R1 && Queue != Q_R2 && Queue != Q_XS1 &&
44815+ Queue != Q_XS2 && Queue != Q_XA1 && Queue != Q_XA2) {
44816+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
44817+ ("ERROR: Illegal queue identifier %x\n", Queue));
44818+ }
44819+#endif /* DEBUG */
44820+
44821+ /* disable the prefetch unit */
44822+ SK_OUT32(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_CTRL_REG), PREF_UNIT_RST_SET);
44823+ SK_OUT32(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_CTRL_REG), PREF_UNIT_RST_CLR);
44824+
44825+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44826+ ("Base address: %08lx:%08lx\n", pLETab->pPhyLETABHigh,
44827+ pLETab->pPhyLETABLow));
44828+
44829+ /* Set the list base address high part*/
44830+ SK_OUT32(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_ADDR_HI_REG),
44831+ pLETab->pPhyLETABHigh);
44832+
44833+ /* Set the list base address low part */
44834+ SK_OUT32(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_ADDR_LOW_REG),
44835+ pLETab->pPhyLETABLow);
44836+
44837+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44838+ ("Last index: %d\n", pLETab->Num-1));
44839+
44840+ /* Set the list last index */
44841+ SK_OUT16(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_LAST_IDX_REG),
44842+ (SK_U16)(pLETab->Num - 1));
44843+
44844+ /* turn on prefetch unit */
44845+ SK_OUT32(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_CTRL_REG), PREF_UNIT_OP_ON);
44846+
44847+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44848+ ("<== SkGeY2InitPrefetchUnit()\n"));
44849+} /* SkGeY2InitPrefetchUnit */
44850+
44851+
44852+/*****************************************************************************
44853+ *
44854+ * SkGeY2InitStatBmu() - Initialize the Status BMU
44855+ *
44856+ * Description:
44857+ * Calling this function requires an already configured list element
44858+ * table. Ensure the status BMU is only initialized once during
44859+ * DriverInit - InitLevel2 required.
44860+ *
44861+ * Arguments:
44862+ * pAC - pointer to the adapter context struct.
44863+ * IoC - I/O context.
44864+ * pLETab - pointer to status LE table to be initialized
44865+ *
44866+ * Returns: N/A
44867+ */
44868+void SkGeY2InitStatBmu(
44869+SK_AC *pAC, /* pointer to adapter context */
44870+SK_IOC IoC, /* I/O context */
44871+SK_LE_TABLE *pLETab) /* pointer to status LE table */
44872+{
44873+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44874+ ("==> SkGeY2InitStatBmu()\n"));
44875+
44876+ /* disable the prefetch unit */
44877+ SK_OUT32(IoC, STAT_CTRL, SC_STAT_RST_SET);
44878+ SK_OUT32(IoC, STAT_CTRL, SC_STAT_RST_CLR);
44879+
44880+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44881+ ("Base address Low: %08lX\n", pLETab->pPhyLETABLow));
44882+
44883+ /* Set the list base address */
44884+ SK_OUT32(IoC, STAT_LIST_ADDR_LO, pLETab->pPhyLETABLow);
44885+
44886+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44887+ ("Base address High: %08lX\n", pLETab->pPhyLETABHigh));
44888+
44889+ SK_OUT32(IoC, STAT_LIST_ADDR_HI, pLETab->pPhyLETABHigh);
44890+
44891+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44892+ ("Last index: %d\n", pLETab->Num - 1));
44893+
44894+ /* Set the list last index */
44895+ SK_OUT16(IoC, STAT_LAST_IDX, (SK_U16)(pLETab->Num - 1));
44896+
44897+ if (HW_FEATURE(pAC, HWF_WA_DEV_43_418)) {
44898+
44899+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44900+ ("Set Tx index threshold\n"));
44901+ /* WA for dev. #4.3 */
44902+ SK_OUT16(IoC, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK);
44903+
44904+ /* set Status-FIFO watermark */
44905+ SK_OUT8(IoC, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
44906+
44907+ /* set Status-FIFO ISR watermark */
44908+ SK_OUT8(IoC, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
44909+
44910+ /* WA for dev. #4.3 and #4.18 */
44911+ /* set Status-FIFO Tx timer init value */
44912+ SK_OUT32(IoC, STAT_TX_TIMER_INI, HW_MS_TO_TICKS(pAC, 10));
44913+ }
44914+ else {
44915+ /*
44916+ * Further settings may be added if required...
44917+ * 1) Status-FIFO watermark (STAT_FIFO_WM, STAT_FIFO_ISR_WM)
44918+ * 2) Status-FIFO timer values (STAT_TX_TIMER_INI,
44919+ * STAT_LEV_TIMER_INI and STAT_ISR_TIMER_INI)
44920+ * but tests shows that the default values give the best results,
44921+ * therefore the defaults are used.
44922+ */
44923+
44924+ /*
44925+ * Theses settings should avoid the temporary hang of the status BMU.
44926+ * May be not all required... still under investigation...
44927+ */
44928+ SK_OUT16(IoC, STAT_TX_IDX_TH, 0x000a);
44929+
44930+ /* set Status-FIFO watermark */
44931+ SK_OUT8(IoC, STAT_FIFO_WM, 0x10);
44932+
44933+ /* set Status-FIFO ISR watermark */
44934+ SK_OUT8(IoC, STAT_FIFO_ISR_WM,
44935+ HW_FEATURE(pAC, HWF_WA_DEV_4109) ? 0x10 : 0x04);
44936+
44937+ /* set ISR Timer Init Value to 400 (3.2 us on Yukon-EC) */
44938+ SK_OUT32(IoC, STAT_ISR_TIMER_INI, 0x0190);
44939+ }
44940+
44941+ /* start Status-FIFO timer */
44942+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44943+ ("Start Status FiFo timer\n"));
44944+
44945+ /* enable the prefetch unit */
44946+ /* operational bit not functional for Yukon-EC, but fixed in Yukon-2 */
44947+ SK_OUT32(IoC, STAT_CTRL, SC_STAT_OP_ON);
44948+
44949+ /* start Status-FIFO timer */
44950+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44951+ ("Start Status FiFo timer\n"));
44952+
44953+ SK_OUT8(IoC, STAT_TX_TIMER_CTRL, TIM_START);
44954+ SK_OUT8(IoC, STAT_LEV_TIMER_CTRL, TIM_START);
44955+ SK_OUT8(IoC, STAT_ISR_TIMER_CTRL, TIM_START);
44956+
44957+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44958+ ("<== SkGeY2InitStatBmu()\n"));
44959+} /* SkGeY2InitStatBmu */
44960+
44961+#ifdef USE_POLLING_UNIT
44962+/*****************************************************************************
44963+ *
44964+ * SkGeY2InitPollUnit() - Initialize the Polling Unit
44965+ *
44966+ * Description:
44967+ * This function will write the data of one polling LE table into the
44968+ * adapter.
44969+ *
44970+ * Arguments:
44971+ * pAC - pointer to the adapter context struct.
44972+ * IoC - I/O context.
44973+ * pLETab - pointer to polling LE table to be initialized
44974+ *
44975+ * Returns: N/A
44976+ */
44977+void SkGeY2InitPollUnit(
44978+SK_AC *pAC, /* pointer to adapter context */
44979+SK_IOC IoC, /* I/O context */
44980+SK_LE_TABLE *pLETab) /* pointer to polling LE table */
44981+{
44982+ SK_HWLE *pLE;
44983+ int i;
44984+#ifdef VCPU
44985+ VCPU_VARS();
44986+#endif /* VCPU */
44987+
44988+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
44989+ ("==> SkGeY2InitPollUnit()\n"));
44990+
44991+#ifdef VCPU
44992+ for (i = 0; i < SK_MAX_MACS; i++) {
44993+ GET_PO_LE(pLE, pLETab, i);
44994+ VCPU_START_AND_COPY_LE();
44995+ /* initialize polling LE but leave indexes invalid */
44996+ POLE_SET_OPC(pLE, OP_PUTIDX | HW_OWNER);
44997+ POLE_SET_LINK(pLE, i);
44998+ POLE_SET_RXIDX(pLE, 0);
44999+ POLE_SET_TXAIDX(pLE, 0);
45000+ POLE_SET_TXSIDX(pLE, 0);
45001+ VCPU_WRITE_LE();
45002+ SK_DBG_DUMP_PO_LE(pLE);
45003+ }
45004+#endif /* VCPU */
45005+
45006+ /* disable the polling unit */
45007+ SK_OUT32(IoC, POLL_CTRL, PC_POLL_RST_SET);
45008+ SK_OUT32(IoC, POLL_CTRL, PC_POLL_RST_CLR);
45009+
45010+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
45011+ ("Base address Low: %08lX\n", pLETab->pPhyLETABLow));
45012+
45013+ /* Set the list base address */
45014+ SK_OUT32(IoC, POLL_LIST_ADDR_LO, pLETab->pPhyLETABLow);
45015+
45016+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
45017+ ("Base address High: %08lX\n", pLETab->pPhyLETABHigh));
45018+
45019+ SK_OUT32(IoC, POLL_LIST_ADDR_HI, pLETab->pPhyLETABHigh);
45020+
45021+ /* we don't need to write the last index - it is hardwired to 1 */
45022+
45023+ /* enable the prefetch unit */
45024+ SK_OUT32(IoC, POLL_CTRL, PC_POLL_OP_ON);
45025+
45026+ /*
45027+ * now we have to start the descriptor poll timer because it triggers
45028+ * the polling unit
45029+ */
45030+
45031+ /*
45032+ * still playing with the value (timer runs at 125 MHz)
45033+ * descriptor poll timer is enabled by GeInit
45034+ */
45035+ SK_OUT32(IoC, B28_DPT_INI,
45036+ (SK_DPOLL_DEF_Y2 * (SK_U32)pAC->GIni.GIHstClkFact / 100));
45037+
45038+ SK_OUT8(IoC, B28_DPT_CTRL, TIM_START);
45039+
45040+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
45041+ ("<== SkGeY2InitPollUnit()\n"));
45042+} /* SkGeY2InitPollUnit */
45043+#endif /* USE_POLLING_UNIT */
45044+
45045+
45046+/******************************************************************************
45047+ *
45048+ * SkGeY2SetPutIndex
45049+ *
45050+ * Description:
45051+ * This function is writing the Done index of a transmit
45052+ * list element table.
45053+ *
45054+ * Notes:
45055+ * Dev. Issue 4.2
45056+ *
45057+ * Returns: N/A
45058+ */
45059+void SkGeY2SetPutIndex(
45060+SK_AC *pAC, /* pointer to adapter context */
45061+SK_IOC IoC, /* pointer to the IO context */
45062+SK_U32 StartAddrPrefetchUnit, /* start address of the prefetch unit */
45063+SK_LE_TABLE *pLETab) /* list element table to work with */
45064+{
45065+ unsigned int Put;
45066+ SK_U16 EndOfListIndex;
45067+ SK_U16 HwGetIndex;
45068+ SK_U16 HwPutIndex;
45069+
45070+ /* set put index we would like to write */
45071+ Put = GET_PUT_IDX(pLETab);
45072+
45073+ /*
45074+ * in this case we wrap around
45075+ * new put is lower than last put given to HW
45076+ */
45077+ if (Put < pLETab->HwPut) {
45078+
45079+ /* set put index = last index of list */
45080+ EndOfListIndex = (NUM_LE_IN_TABLE(pLETab)-1);
45081+
45082+ /* read get index of hw prefetch unit */
45083+ SK_IN16(IoC, (StartAddrPrefetchUnit + PREF_UNIT_GET_IDX_REG),
45084+ &HwGetIndex);
45085+
45086+ /* read put index of hw prefetch unit */
45087+ SK_IN16(IoC, (StartAddrPrefetchUnit + PREF_UNIT_PUT_IDX_REG),
45088+ &HwPutIndex);
45089+
45090+ /* prefetch unit reached end of list */
45091+ /* prefetch unit reached first list element */
45092+ if (HwGetIndex == 0) {
45093+ /* restore watermark */
45094+ SK_OUT8(IoC, StartAddrPrefetchUnit + PREF_UNIT_FIFO_WM_REG, 0xe0U);
45095+ /* write put index */
45096+ SK_OUT16(IoC, StartAddrPrefetchUnit + PREF_UNIT_PUT_IDX_REG,
45097+ (SK_U16)Put);
45098+
45099+ /* remember put index we wrote to hw */
45100+ pLETab->HwPut = Put;
45101+ }
45102+ else if (HwGetIndex == EndOfListIndex) {
45103+ /* set watermark to one list element */
45104+ SK_OUT8(IoC, StartAddrPrefetchUnit + PREF_UNIT_FIFO_WM_REG, 8);
45105+ /* set put index to first list element */
45106+ SK_OUT16(IoC, StartAddrPrefetchUnit + PREF_UNIT_PUT_IDX_REG, 0);
45107+ }
45108+ /* prefetch unit did not reach end of list yet */
45109+ /* and we did not write put index to end of list yet */
45110+ else if ((HwPutIndex != EndOfListIndex) &&
45111+ (HwGetIndex != EndOfListIndex)) {
45112+ /* write put index */
45113+ SK_OUT16(IoC, StartAddrPrefetchUnit + PREF_UNIT_PUT_IDX_REG,
45114+ EndOfListIndex);
45115+ }
45116+ else {
45117+ /* do nothing */
45118+ }
45119+ }
45120+ else {
45121+#ifdef XXX /* leads in to problems in the Windows Driver */
45122+ if (Put != pLETab->HwPut) {
45123+ /* write put index */
45124+ SK_OUT16(IoC, StartAddrPrefetchUnit + PREF_UNIT_PUT_IDX_REG,
45125+ (SK_U16)Put);
45126+ /* update put index */
45127+ UPDATE_HWPUT_IDX(pLETab);
45128+ }
45129+#else
45130+ /* write put index */
45131+ SK_OUT16(IoC, StartAddrPrefetchUnit + PREF_UNIT_PUT_IDX_REG,
45132+ (SK_U16)Put);
45133+ /* update put index */
45134+ UPDATE_HWPUT_IDX(pLETab);
45135+#endif
45136+ }
45137+} /* SkGeY2SetPutIndex */
45138+
The Linux kernel (the core of the Linux operating system)
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