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[packages/kernel.git] / linux-2.6-sk98lin-8.31.2.3.patch
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5902d8ee 1diff -ruN linux/drivers/net/sk98lin/Makefile linux-new/drivers/net/sk98lin/Makefile
2--- linux/drivers/net/sk98lin/Makefile 2006-04-11 19:19:28.000000000 +0200
3+++ linux-new/drivers/net/sk98lin/Makefile 2006-04-12 18:59:11.861752000 +0200
4@@ -1,6 +1,59 @@
5+#******************************************************************************
6 #
7-# Makefile for the SysKonnect SK-98xx device driver.
8+# Name: skge.c
9+# Project: GEnesis, PCI Gigabit Ethernet Adapter
10+# Version: $Revision$
11+# Date: $Date$
12+# Purpose: The main driver source module
13 #
14+#******************************************************************************
15+
16+#******************************************************************************
17+#
18+# (C)Copyright 1998-2002 SysKonnect GmbH.
19+# (C)Copyright 2002-2005 Marvell.
20+#
21+# Makefile for Marvell Yukon chipset and SysKonnect Gigabit Ethernet
22+# Server Adapter driver. (Kernel 2.6)
23+#
24+# Author: Mirko Lindner (mlindner@syskonnect.de)
25+# Ralph Roesler (rroesler@syskonnect.de)
26+#
27+# Address all question to: linux@syskonnect.de
28+#
29+# This program is free software; you can redistribute it and/or modify
30+# it under the terms of the GNU General Public License as published by
31+# the Free Software Foundation; either version 2 of the License, or
32+# (at your option) any later version.
33+#
34+# The information in this file is provided "AS IS" without warranty.
35+#
36+#******************************************************************************
37+
38+#******************************************************************************
39+#
40+# History:
41+#
42+# $Log$
43+# Revision 1.9.2.1 2005/04/11 09:01:18 mlindner
44+# Fix: Copyright year changed
45+#
46+# Revision 1.9 2004/07/13 15:54:50 rroesler
47+# Add: file skethtool.c
48+# Fix: corrected header regarding copyright
49+# Fix: minor typos corrected
50+#
51+# Revision 1.8 2004/06/08 08:39:38 mlindner
52+# Fix: Add CONFIG_SK98LIN_ZEROCOPY as default
53+#
54+# Revision 1.7 2004/06/03 16:06:56 mlindner
55+# Fix: Added compile flag SK_DIAG_SUPPORT
56+#
57+# Revision 1.6 2004/06/02 08:02:59 mlindner
58+# Add: Changed header information and inserted a GPL statement
59+#
60+#
61+#******************************************************************************
62
63
64 #
65@@ -13,20 +66,24 @@
66 obj-$(CONFIG_SK98LIN) += sk98lin.o
67 sk98lin-objs := \
68 skge.o \
69+ sky2.o \
70 skethtool.o \
71+ sky2le.o \
72 skdim.o \
73 skaddr.o \
74 skgehwt.o \
75 skgeinit.o \
76 skgepnmi.o \
77 skgesirq.o \
78- ski2c.o \
79+ sktwsi.o \
80 sklm80.o \
81 skqueue.o \
82 skrlmt.o \
83 sktimer.o \
84 skvpd.o \
85- skxmac2.o
86+ skxmac2.o \
87+ skproc.o \
88+ skcsum.o
89
90 # DBGDEF = \
91 # -DDEBUG
92@@ -75,13 +132,11 @@
93 # SK_DBGCAT_DRV_INT_SRC 0x04000000 interrupts sources
94 # SK_DBGCAT_DRV_EVENT 0x08000000 driver events
95
96-EXTRA_CFLAGS += -Idrivers/net/sk98lin -DSK_DIAG_SUPPORT -DGENESIS -DYUKON $(DBGDEF) $(SKPARAM)
97+EXTRA_CFLAGS += -Idrivers/net/sk98lin -DSK_USE_CSUM -DSK_DIAG_SUPPORT \
98+ -DGENESIS -DYUKON -DYUK2 -DCONFIG_SK98LIN_ZEROCOPY \
99+ $(DBGDEF) $(SKPARAM)
100
101 clean:
102 rm -f core *.o *.a *.s
103
104
105-
106-
107-
108-
109diff -ruN linux/drivers/net/sk98lin/h/lm80.h linux-new/drivers/net/sk98lin/h/lm80.h
110--- linux/drivers/net/sk98lin/h/lm80.h 2006-04-11 19:19:28.000000000 +0200
111+++ linux-new/drivers/net/sk98lin/h/lm80.h 2006-01-18 14:37:24.000000000 +0100
112@@ -2,8 +2,8 @@
113 *
114 * Name: lm80.h
115 * Project: Gigabit Ethernet Adapters, Common Modules
116- * Version: $Revision$
117- * Date: $Date$
118+ * Version: $Revision$
119+ * Date: $Date$
120 * Purpose: Contains all defines for the LM80 Chip
121 * (National Semiconductor).
122 *
123@@ -11,6 +11,7 @@
124
125 /******************************************************************************
126 *
127+ * LICENSE:
128 * (C)Copyright 1998-2002 SysKonnect.
129 * (C)Copyright 2002-2003 Marvell.
130 *
131@@ -20,6 +21,7 @@
132 * (at your option) any later version.
133 *
134 * The information in this file is provided "AS IS" without warranty.
135+ * /LICENSE
136 *
137 ******************************************************************************/
138
139diff -ruN linux/drivers/net/sk98lin/h/skaddr.h linux-new/drivers/net/sk98lin/h/skaddr.h
140--- linux/drivers/net/sk98lin/h/skaddr.h 2006-04-11 19:19:28.000000000 +0200
141+++ linux-new/drivers/net/sk98lin/h/skaddr.h 2006-01-18 14:37:24.000000000 +0100
142@@ -2,8 +2,8 @@
143 *
144 * Name: skaddr.h
145 * Project: Gigabit Ethernet Adapters, ADDR-Modul
146- * Version: $Revision$
147- * Date: $Date$
148+ * Version: $Revision$
149+ * Date: $Date$
150 * Purpose: Header file for Address Management (MC, UC, Prom).
151 *
152 ******************************************************************************/
153diff -ruN linux/drivers/net/sk98lin/h/skcsum.h linux-new/drivers/net/sk98lin/h/skcsum.h
154--- linux/drivers/net/sk98lin/h/skcsum.h 2006-04-11 19:19:28.000000000 +0200
155+++ linux-new/drivers/net/sk98lin/h/skcsum.h 2006-01-18 14:37:24.000000000 +0100
156@@ -2,8 +2,8 @@
157 *
158 * Name: skcsum.h
159 * Project: GEnesis - SysKonnect SK-NET Gigabit Ethernet (SK-98xx)
160- * Version: $Revision$
161- * Date: $Date$
162+ * Version: $Revision$
163+ * Date: $Date$
164 * Purpose: Store/verify Internet checksum in send/receive packets.
165 *
166 ******************************************************************************/
167@@ -157,9 +157,7 @@
168 typedef struct s_Csum {
169 /* Enabled receive SK_PROTO_XXX bit flags. */
170 unsigned ReceiveFlags[SK_MAX_NETS];
171-#ifdef TX_CSUM
172 unsigned TransmitFlags[SK_MAX_NETS];
173-#endif /* TX_CSUM */
174
175 /* The protocol statistics structure; one per supported protocol. */
176 SKCS_PROTO_STATS ProtoStats[SK_MAX_NETS][SKCS_NUM_PROTOCOLS];
177diff -ruN linux/drivers/net/sk98lin/h/skdebug.h linux-new/drivers/net/sk98lin/h/skdebug.h
178--- linux/drivers/net/sk98lin/h/skdebug.h 2006-04-11 19:19:28.000000000 +0200
179+++ linux-new/drivers/net/sk98lin/h/skdebug.h 2006-01-18 14:37:24.000000000 +0100
180@@ -2,23 +2,24 @@
181 *
182 * Name: skdebug.h
183 * Project: Gigabit Ethernet Adapters, Common Modules
184- * Version: $Revision$
185- * Date: $Date$
186+ * Version: $Revision$
187+ * Date: $Date$
188 * Purpose: SK specific DEBUG support
189 *
190 ******************************************************************************/
191
192 /******************************************************************************
193 *
194+ * LICENSE:
195 * (C)Copyright 1998-2002 SysKonnect.
196- * (C)Copyright 2002-2003 Marvell.
197+ * (C)Copyright 2002-2005 Marvell.
198 *
199 * This program is free software; you can redistribute it and/or modify
200 * it under the terms of the GNU General Public License as published by
201 * the Free Software Foundation; either version 2 of the License, or
202 * (at your option) any later version.
203- *
204 * The information in this file is provided "AS IS" without warranty.
205+ * /LICENSE
206 *
207 ******************************************************************************/
208
209@@ -28,9 +29,9 @@
210 #ifdef DEBUG
211 #ifndef SK_DBG_MSG
212 #define SK_DBG_MSG(pAC,comp,cat,arg) \
213- if ( ((comp) & SK_DBG_CHKMOD(pAC)) && \
214- ((cat) & SK_DBG_CHKCAT(pAC)) ) { \
215- SK_DBG_PRINTF arg ; \
216+ if ( ((comp) & SK_DBG_CHKMOD(pAC)) && \
217+ ((cat) & SK_DBG_CHKCAT(pAC)) ) { \
218+ SK_DBG_PRINTF arg; \
219 }
220 #endif
221 #else
222@@ -58,6 +59,13 @@
223 #define SK_DBGMOD_ADDR 0x00000080L /* ADDR module */
224 #define SK_DBGMOD_PECP 0x00000100L /* PECP module */
225 #define SK_DBGMOD_POWM 0x00000200L /* Power Management module */
226+#ifdef SK_ASF
227+#define SK_DBGMOD_ASF 0x00000400L /* ASF module */
228+#endif
229+#ifdef SK_LBFO
230+#define SK_DBGMOD_LACP 0x00000800L /* link aggregation control protocol */
231+#define SK_DBGMOD_FD 0x00001000L /* frame distributor (link aggregation) */
232+#endif /* SK_LBFO */
233
234 /* Debug events */
235
236diff -ruN linux/drivers/net/sk98lin/h/skdrv1st.h linux-new/drivers/net/sk98lin/h/skdrv1st.h
237--- linux/drivers/net/sk98lin/h/skdrv1st.h 2006-04-11 19:19:28.000000000 +0200
238+++ linux-new/drivers/net/sk98lin/h/skdrv1st.h 2006-01-18 14:37:24.000000000 +0100
239@@ -2,8 +2,8 @@
240 *
241 * Name: skdrv1st.h
242 * Project: GEnesis, PCI Gigabit Ethernet Adapter
243- * Version: $Revision$
244- * Date: $Date$
245+ * Version: $Revision$
246+ * Date: $Date$
247 * Purpose: First header file for driver and all other modules
248 *
249 ******************************************************************************/
250@@ -11,7 +11,7 @@
251 /******************************************************************************
252 *
253 * (C)Copyright 1998-2002 SysKonnect GmbH.
254- * (C)Copyright 2002-2003 Marvell.
255+ * (C)Copyright 2002-2005 Marvell.
256 *
257 * This program is free software; you can redistribute it and/or modify
258 * it under the terms of the GNU General Public License as published by
259@@ -22,23 +22,12 @@
260 *
261 ******************************************************************************/
262
263-/******************************************************************************
264- *
265- * Description:
266- *
267- * This is the first include file of the driver, which includes all
268- * neccessary system header files and some of the GEnesis header files.
269- * It also defines some basic items.
270- *
271- * Include File Hierarchy:
272- *
273- * see skge.c
274- *
275- ******************************************************************************/
276-
277 #ifndef __INC_SKDRV1ST_H
278 #define __INC_SKDRV1ST_H
279
280+/* Check kernel version */
281+#include <linux/version.h>
282+
283 typedef struct s_AC SK_AC;
284
285 /* Set card versions */
286@@ -55,6 +44,9 @@
287
288 #define SK_ADDR_EQUAL(a1,a2) (!memcmp(a1,a2,6))
289
290+#define SK_STRNCMP(s1,s2,len) strncmp(s1,s2,len)
291+#define SK_STRCPY(dest,src) strcpy(dest,src)
292+
293 #include <linux/types.h>
294 #include <linux/kernel.h>
295 #include <linux/string.h>
296@@ -63,10 +55,9 @@
297 #include <linux/slab.h>
298 #include <linux/interrupt.h>
299 #include <linux/pci.h>
300-#include <linux/bitops.h>
301 #include <asm/byteorder.h>
302+#include <asm/bitops.h>
303 #include <asm/io.h>
304-#include <asm/irq.h>
305 #include <linux/netdevice.h>
306 #include <linux/etherdevice.h>
307 #include <linux/skbuff.h>
308@@ -76,11 +67,7 @@
309 #include <net/checksum.h>
310
311 #define SK_CS_CALCULATE_CHECKSUM
312-#ifndef CONFIG_X86_64
313-#define SkCsCalculateChecksum(p,l) ((~ip_compute_csum(p, l)) & 0xffff)
314-#else
315-#define SkCsCalculateChecksum(p,l) ((~ip_fast_csum(p, l)) & 0xffff)
316-#endif
317+#define SkCsCalculateChecksum(p,l) (~csum_fold(csum_partial(p, l, 0)))
318
319 #include "h/sktypes.h"
320 #include "h/skerror.h"
321@@ -88,10 +75,15 @@
322 #include "h/lm80.h"
323 #include "h/xmac_ii.h"
324
325+#ifndef SK_BMU_RX_WM_PEX
326+#define SK_BMU_RX_WM_PEX 0x80
327+#endif
328+
329 #ifdef __LITTLE_ENDIAN
330 #define SK_LITTLE_ENDIAN
331 #else
332 #define SK_BIG_ENDIAN
333+#define SK_USE_REV_DESC
334 #endif
335
336 #define SK_NET_DEVICE net_device
337@@ -107,7 +99,7 @@
338 #define SK_MAX_MACS 2
339 #define SK_MAX_NETS 2
340
341-#define SK_IOC char __iomem *
342+#define SK_IOC char*
343
344 typedef struct s_DrvRlmtMbuf SK_MBUF;
345
346@@ -186,3 +178,8 @@
347
348 #endif
349
350+/*******************************************************************************
351+ *
352+ * End of file
353+ *
354+ ******************************************************************************/
355diff -ruN linux/drivers/net/sk98lin/h/skdrv2nd.h linux-new/drivers/net/sk98lin/h/skdrv2nd.h
356--- linux/drivers/net/sk98lin/h/skdrv2nd.h 2006-04-11 19:19:28.000000000 +0200
357+++ linux-new/drivers/net/sk98lin/h/skdrv2nd.h 2006-01-18 14:37:24.000000000 +0100
358@@ -1,17 +1,17 @@
359 /******************************************************************************
360 *
361- * Name: skdrv2nd.h
362- * Project: GEnesis, PCI Gigabit Ethernet Adapter
363- * Version: $Revision$
364- * Date: $Date$
365- * Purpose: Second header file for driver and all other modules
366+ * Name: skdrv2nd.h
367+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
368+ * Version: $Revision$
369+ * Date: $Date$
370+ * Purpose: Second header file for driver and all other modules
371 *
372 ******************************************************************************/
373
374 /******************************************************************************
375 *
376 * (C)Copyright 1998-2002 SysKonnect GmbH.
377- * (C)Copyright 2002-2003 Marvell.
378+ * (C)Copyright 2002-2005 Marvell.
379 *
380 * This program is free software; you can redistribute it and/or modify
381 * it under the terms of the GNU General Public License as published by
382@@ -42,10 +42,11 @@
383 #include "h/skqueue.h"
384 #include "h/skgehwt.h"
385 #include "h/sktimer.h"
386-#include "h/ski2c.h"
387+#include "h/sktwsi.h"
388 #include "h/skgepnmi.h"
389 #include "h/skvpd.h"
390 #include "h/skgehw.h"
391+#include "h/sky2le.h"
392 #include "h/skgeinit.h"
393 #include "h/skaddr.h"
394 #include "h/skgesirq.h"
395@@ -53,103 +54,191 @@
396 #include "h/skrlmt.h"
397 #include "h/skgedrv.h"
398
399+/* Defines for the poll cotroller */
400+#define SK_NETDUMP_POLL
401
402-extern SK_MBUF *SkDrvAllocRlmtMbuf(SK_AC*, SK_IOC, unsigned);
403-extern void SkDrvFreeRlmtMbuf(SK_AC*, SK_IOC, SK_MBUF*);
404-extern SK_U64 SkOsGetTime(SK_AC*);
405-extern int SkPciReadCfgDWord(SK_AC*, int, SK_U32*);
406-extern int SkPciReadCfgWord(SK_AC*, int, SK_U16*);
407-extern int SkPciReadCfgByte(SK_AC*, int, SK_U8*);
408-extern int SkPciWriteCfgWord(SK_AC*, int, SK_U16);
409-extern int SkPciWriteCfgByte(SK_AC*, int, SK_U8);
410-extern int SkDrvEvent(SK_AC*, SK_IOC IoC, SK_U32, SK_EVPARA);
411-
412-#ifdef SK_DIAG_SUPPORT
413-extern int SkDrvEnterDiagMode(SK_AC *pAc);
414-extern int SkDrvLeaveDiagMode(SK_AC *pAc);
415+#ifdef SK_NETDUMP_POLL
416+#ifdef HAVE_POLL_CONTROLLER
417+#define SK_POLL_CONTROLLER
418+#define CONFIG_SK98LIN_NAPI
419+#elif CONFIG_NET_POLL_CONTROLLER
420+#define SK_POLL_CONTROLLER
421+#define CONFIG_SK98LIN_NAPI
422 #endif
423+#endif
424+
425+
426+/******************************************************************************
427+ *
428+ * Generic driver defines
429+ *
430+ ******************************************************************************/
431+
432+#define USE_TIST_FOR_RESET /* Use timestamp for reset */
433+#define Y2_RECOVERY /* use specific recovery yukon2 functions */
434+#define Y2_LE_CHECK /* activate check for LE order */
435+#define Y2_SYNC_CHECK /* activate check for receiver in sync */
436+#define SK_YUKON2 /* Enable Yukon2 dual net support */
437+#define USE_SK_TX_CHECKSUM /* use the tx hw checksum driver functionality */
438+#define USE_SK_RX_CHECKSUM /* use the rx hw checksum driver functionality */
439+#define USE_SK_TSO_FEATURE /* use TCP segmentation offload if possible */
440+#define SK_COPY_THRESHOLD 50 /* threshold for copying small RX frames;
441+ * 0 avoids copying, 9001 copies all */
442+#define SK_MAX_CARD_PARAM 16 /* number of adapters that can be configured via
443+ * command line params */
444+//#define USE_TX_COMPLETE /* use of a transmit complete interrupt */
445+#define Y2_RX_CHECK /* RX Check timestamp */
446+
447+/*
448+ * use those defines for a compile-in version of the driver instead
449+ * of command line parameters
450+ */
451+// #define LINK_SPEED_A {"Auto",}
452+// #define LINK_SPEED_B {"Auto",}
453+// #define AUTO_NEG_A {"Sense",}
454+// #define AUTO_NEG_B {"Sense"}
455+// #define DUP_CAP_A {"Both",}
456+// #define DUP_CAP_B {"Both",}
457+// #define FLOW_CTRL_A {"SymOrRem",}
458+// #define FLOW_CTRL_B {"SymOrRem",}
459+// #define ROLE_A {"Auto",}
460+// #define ROLE_B {"Auto",}
461+// #define PREF_PORT {"A",}
462+// #define CON_TYPE {"Auto",}
463+// #define RLMT_MODE {"CheckLinkState",}
464+
465+#ifdef Y2_RECOVERY
466+#define CHECK_TRANSMIT_TIMEOUT
467+#define Y2_RESYNC_WATERMARK 1000000L
468+#endif
469+
470+
471+/******************************************************************************
472+ *
473+ * Generic ISR defines
474+ *
475+ ******************************************************************************/
476+
477+#define SkIsrRetVar irqreturn_t
478+#define SkIsrRetNone IRQ_NONE
479+#define SkIsrRetHandled IRQ_HANDLED
480+
481+#define DEV_KFREE_SKB(skb) dev_kfree_skb(skb)
482+#define DEV_KFREE_SKB_IRQ(skb) dev_kfree_skb_irq(skb)
483+#define DEV_KFREE_SKB_ANY(skb) dev_kfree_skb_any(skb)
484+
485+/******************************************************************************
486+ *
487+ * Global function prototypes
488+ *
489+ ******************************************************************************/
490+
491+extern SK_MBUF *SkDrvAllocRlmtMbuf(SK_AC*, SK_IOC, unsigned);
492+extern void SkDrvFreeRlmtMbuf(SK_AC*, SK_IOC, SK_MBUF*);
493+extern SK_U64 SkOsGetTime(SK_AC*);
494+extern int SkPciReadCfgDWord(SK_AC*, int, SK_U32*);
495+extern int SkPciReadCfgWord(SK_AC*, int, SK_U16*);
496+extern int SkPciReadCfgByte(SK_AC*, int, SK_U8*);
497+extern int SkPciWriteCfgDWord(SK_AC*, int, SK_U32);
498+extern int SkPciWriteCfgWord(SK_AC*, int, SK_U16);
499+extern int SkPciWriteCfgByte(SK_AC*, int, SK_U8);
500+extern int SkDrvEvent(SK_AC*, SK_IOC IoC, SK_U32, SK_EVPARA);
501+extern int SkDrvEnterDiagMode(SK_AC *pAc);
502+extern int SkDrvLeaveDiagMode(SK_AC *pAc);
503+
504+/******************************************************************************
505+ *
506+ * Linux specific RLMT buffer structure (SK_MBUF typedef in skdrv1st)!
507+ *
508+ ******************************************************************************/
509
510 struct s_DrvRlmtMbuf {
511- SK_MBUF *pNext; /* Pointer to next RLMT Mbuf. */
512- SK_U8 *pData; /* Data buffer (virtually contig.). */
513- unsigned Size; /* Data buffer size. */
514- unsigned Length; /* Length of packet (<= Size). */
515- SK_U32 PortIdx; /* Receiving/transmitting port. */
516+ SK_MBUF *pNext; /* Pointer to next RLMT Mbuf. */
517+ SK_U8 *pData; /* Data buffer (virtually contig.). */
518+ unsigned Size; /* Data buffer size. */
519+ unsigned Length; /* Length of packet (<= Size). */
520+ SK_U32 PortIdx; /* Receiving/transmitting port. */
521 #ifdef SK_RLMT_MBUF_PRIVATE
522- SK_RLMT_MBUF Rlmt; /* Private part for RLMT. */
523-#endif /* SK_RLMT_MBUF_PRIVATE */
524- struct sk_buff *pOs; /* Pointer to message block */
525+ SK_RLMT_MBUF Rlmt; /* Private part for RLMT. */
526+#endif
527+ struct sk_buff *pOs; /* Pointer to message block */
528 };
529
530+/******************************************************************************
531+ *
532+ * Linux specific TIME defines
533+ *
534+ ******************************************************************************/
535
536-/*
537- * Time macros
538- */
539 #if SK_TICKS_PER_SEC == 100
540 #define SK_PNMI_HUNDREDS_SEC(t) (t)
541 #else
542-#define SK_PNMI_HUNDREDS_SEC(t) ((((unsigned long)t) * 100) / \
543- (SK_TICKS_PER_SEC))
544+#define SK_PNMI_HUNDREDS_SEC(t) ((((unsigned long)t)*100)/(SK_TICKS_PER_SEC))
545 #endif
546
547-/*
548- * New SkOsGetTime
549- */
550 #define SkOsGetTimeCurrent(pAC, pUsec) {\
551+ static struct timeval prev_t; \
552 struct timeval t;\
553 do_gettimeofday(&t);\
554- *pUsec = ((((t.tv_sec) * 1000000L)+t.tv_usec)/10000);\
555+ if (prev_t.tv_sec == t.tv_sec) { \
556+ if (prev_t.tv_usec > t.tv_usec) { \
557+ t.tv_usec = prev_t.tv_usec; \
558+ } else { \
559+ prev_t.tv_usec = t.tv_usec; \
560+ } \
561+ } else { \
562+ prev_t = t; \
563+ } \
564+ *pUsec = ((t.tv_sec*100L)+(t.tv_usec/10000));\
565 }
566
567+/******************************************************************************
568+ *
569+ * Linux specific IOCTL defines and typedefs
570+ *
571+ ******************************************************************************/
572
573-/*
574- * ioctl definitions
575- */
576-#define SK_IOCTL_BASE (SIOCDEVPRIVATE)
577-#define SK_IOCTL_GETMIB (SK_IOCTL_BASE + 0)
578-#define SK_IOCTL_SETMIB (SK_IOCTL_BASE + 1)
579-#define SK_IOCTL_PRESETMIB (SK_IOCTL_BASE + 2)
580-#define SK_IOCTL_GEN (SK_IOCTL_BASE + 3)
581-#define SK_IOCTL_DIAG (SK_IOCTL_BASE + 4)
582-
583-typedef struct s_IOCTL SK_GE_IOCTL;
584+#define SK_IOCTL_BASE (SIOCDEVPRIVATE)
585+#define SK_IOCTL_GETMIB (SK_IOCTL_BASE + 0)
586+#define SK_IOCTL_SETMIB (SK_IOCTL_BASE + 1)
587+#define SK_IOCTL_PRESETMIB (SK_IOCTL_BASE + 2)
588+#define SK_IOCTL_GEN (SK_IOCTL_BASE + 3)
589+#define SK_IOCTL_DIAG (SK_IOCTL_BASE + 4)
590
591+typedef struct s_IOCTL SK_GE_IOCTL;
592 struct s_IOCTL {
593 char __user * pData;
594 unsigned int Len;
595 };
596
597+/******************************************************************************
598+ *
599+ * Generic sizes and length definitions
600+ *
601+ ******************************************************************************/
602
603-/*
604- * define sizes of descriptor rings in bytes
605- */
606-
607-#define TX_RING_SIZE (8*1024)
608-#define RX_RING_SIZE (24*1024)
609-
610-/*
611- * Buffer size for ethernet packets
612- */
613-#define ETH_BUF_SIZE 1540
614-#define ETH_MAX_MTU 1514
615-#define ETH_MIN_MTU 60
616-#define ETH_MULTICAST_BIT 0x01
617-#define SK_JUMBO_MTU 9000
618-
619-/*
620- * transmit priority selects the queue: LOW=asynchron, HIGH=synchron
621- */
622-#define TX_PRIO_LOW 0
623-#define TX_PRIO_HIGH 1
624+#define TX_RING_SIZE (24*1024) /* GEnesis/Yukon */
625+#define RX_RING_SIZE (24*1024) /* GEnesis/Yukon */
626+#define RX_MAX_NBR_BUFFERS 128 /* Yukon-EC/-II */
627+#define TX_MAX_NBR_BUFFERS 128 /* Yukon-EC/-II */
628+#define MAXIMUM_LOW_ADDRESS 0xFFFFFFFF /* Max. low address */
629+
630+#define ETH_BUF_SIZE 1560 /* multiples of 8 bytes */
631+#define ETH_MAX_MTU 1514
632+#define ETH_MIN_MTU 60
633+#define ETH_MULTICAST_BIT 0x01
634+#define SK_JUMBO_MTU 9000
635+
636+#define TX_PRIO_LOW 0 /* asynchronous queue */
637+#define TX_PRIO_HIGH 1 /* synchronous queue */
638+#define DESCR_ALIGN 64 /* alignment of Rx/Tx descriptors */
639
640-/*
641- * alignment of rx/tx descriptors
642- */
643-#define DESCR_ALIGN 64
644+/******************************************************************************
645+ *
646+ * PNMI related definitions
647+ *
648+ ******************************************************************************/
649
650-/*
651- * definitions for pnmi. TODO
652- */
653 #define SK_DRIVER_RESET(pAC, IoC) 0
654 #define SK_DRIVER_SENDEVENT(pAC, IoC) 0
655 #define SK_DRIVER_SELFTEST(pAC, IoC) 0
656@@ -158,20 +247,16 @@
657 #define SK_DRIVER_SET_MTU(pAc,IoC,i,v) 0
658 #define SK_DRIVER_PRESET_MTU(pAc,IoC,i,v) 0
659
660-/*
661-** Interim definition of SK_DRV_TIMER placed in this file until
662-** common modules have boon finallized
663-*/
664-#define SK_DRV_TIMER 11
665-#define SK_DRV_MODERATION_TIMER 1
666-#define SK_DRV_MODERATION_TIMER_LENGTH 1000000 /* 1 second */
667-#define SK_DRV_RX_CLEANUP_TIMER 2
668-#define SK_DRV_RX_CLEANUP_TIMER_LENGTH 1000000 /* 100 millisecs */
669
670-/*
671-** Definitions regarding transmitting frames
672-** any calculating any checksum.
673-*/
674+/******************************************************************************
675+ *
676+ * Various offsets and sizes
677+ *
678+ ******************************************************************************/
679+
680+#define SK_DRV_MODERATION_TIMER 1 /* id */
681+#define SK_DRV_MODERATION_TIMER_LENGTH 1 /* 1 second */
682+
683 #define C_LEN_ETHERMAC_HEADER_DEST_ADDR 6
684 #define C_LEN_ETHERMAC_HEADER_SRC_ADDR 6
685 #define C_LEN_ETHERMAC_HEADER_LENTYPE 2
686@@ -197,112 +282,445 @@
687 #define C_PROTO_ID_UDP 17 /* refer to RFC 790 or Stevens' */
688 #define C_PROTO_ID_TCP 6 /* TCP/IP illustrated for details */
689
690-/* TX and RX descriptors *****************************************************/
691+/******************************************************************************
692+ *
693+ * Tx and Rx descriptor definitions
694+ *
695+ ******************************************************************************/
696
697 typedef struct s_RxD RXD; /* the receive descriptor */
698-
699 struct s_RxD {
700- volatile SK_U32 RBControl; /* Receive Buffer Control */
701- SK_U32 VNextRxd; /* Next receive descriptor,low dword */
702- SK_U32 VDataLow; /* Receive buffer Addr, low dword */
703- SK_U32 VDataHigh; /* Receive buffer Addr, high dword */
704- SK_U32 FrameStat; /* Receive Frame Status word */
705- SK_U32 TimeStamp; /* Time stamp from XMAC */
706- SK_U32 TcpSums; /* TCP Sum 2 / TCP Sum 1 */
707- SK_U32 TcpSumStarts; /* TCP Sum Start 2 / TCP Sum Start 1 */
708- RXD *pNextRxd; /* Pointer to next Rxd */
709- struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */
710+ volatile SK_U32 RBControl; /* Receive Buffer Control */
711+ SK_U32 VNextRxd; /* Next receive descriptor,low dword */
712+ SK_U32 VDataLow; /* Receive buffer Addr, low dword */
713+ SK_U32 VDataHigh; /* Receive buffer Addr, high dword */
714+ SK_U32 FrameStat; /* Receive Frame Status word */
715+ SK_U32 TimeStamp; /* Time stamp from XMAC */
716+ SK_U32 TcpSums; /* TCP Sum 2 / TCP Sum 1 */
717+ SK_U32 TcpSumStarts; /* TCP Sum Start 2 / TCP Sum Start 1 */
718+ RXD *pNextRxd; /* Pointer to next Rxd */
719+ struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */
720 };
721
722 typedef struct s_TxD TXD; /* the transmit descriptor */
723-
724 struct s_TxD {
725- volatile SK_U32 TBControl; /* Transmit Buffer Control */
726- SK_U32 VNextTxd; /* Next transmit descriptor,low dword */
727- SK_U32 VDataLow; /* Transmit Buffer Addr, low dword */
728- SK_U32 VDataHigh; /* Transmit Buffer Addr, high dword */
729- SK_U32 FrameStat; /* Transmit Frame Status Word */
730- SK_U32 TcpSumOfs; /* Reserved / TCP Sum Offset */
731- SK_U16 TcpSumSt; /* TCP Sum Start */
732- SK_U16 TcpSumWr; /* TCP Sum Write */
733- SK_U32 TcpReserved; /* not used */
734- TXD *pNextTxd; /* Pointer to next Txd */
735- struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */
736+ volatile SK_U32 TBControl; /* Transmit Buffer Control */
737+ SK_U32 VNextTxd; /* Next transmit descriptor,low dword */
738+ SK_U32 VDataLow; /* Transmit Buffer Addr, low dword */
739+ SK_U32 VDataHigh; /* Transmit Buffer Addr, high dword */
740+ SK_U32 FrameStat; /* Transmit Frame Status Word */
741+ SK_U32 TcpSumOfs; /* Reserved / TCP Sum Offset */
742+ SK_U16 TcpSumSt; /* TCP Sum Start */
743+ SK_U16 TcpSumWr; /* TCP Sum Write */
744+ SK_U32 TcpReserved; /* not used */
745+ TXD *pNextTxd; /* Pointer to next Txd */
746+ struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */
747+};
748+
749+/******************************************************************************
750+ *
751+ * Generic Yukon-II defines
752+ *
753+ ******************************************************************************/
754+
755+#define LE_SIZE sizeof(SK_HWLE)
756+#define MAX_NUM_FRAGS (MAX_SKB_FRAGS + 1)
757+#define MIN_LEN_OF_LE_TAB 128
758+#define MAX_LEN_OF_LE_TAB 4096
759+#define MAX_UNUSED_RX_LE_WORKING 8
760+#ifdef MAX_FRAG_OVERHEAD
761+#undef MAX_FRAG_OVERHEAD
762+#define MAX_FRAG_OVERHEAD 4
763+#endif
764+// as we have a maximum of 16 physical fragments,
765+// maximum 1 ADDR64 per physical fragment
766+// maximum 4 LEs for VLAN, Csum, LargeSend, Packet
767+#define MIN_LE_FREE_REQUIRED ((16*2) + 4)
768+#define IS_GMAC(pAc) (!pAc->GIni.GIGenesis)
769+#ifdef USE_SYNC_TX_QUEUE
770+#define TXS_MAX_LE 256
771+#else /* !USE_SYNC_TX_QUEUE */
772+#define TXS_MAX_LE 0
773+#endif
774+
775+#define ETHER_MAC_HDR_LEN (6+6+2) // MAC SRC ADDR, MAC DST ADDR, TYPE
776+#define IP_HDR_LEN 20
777+#define TCP_CSUM_OFFS 0x10
778+#define UDP_CSUM_OFFS 0x06
779+#define TXA_MAX_LE 256
780+#define RX_MAX_LE 256
781+#define ST_MAX_LE (SK_MAX_MACS)*((3*RX_MAX_LE)+(TXA_MAX_LE)+(TXS_MAX_LE))
782+
783+#if (defined (Y2_RECOVERY) || defined (Y2_LE_CHECK))
784+/* event for recovery from tx hang or rx out of sync */
785+#define SK_DRV_RECOVER 17
786+#endif
787+/******************************************************************************
788+ *
789+ * Structures specific for Yukon-II
790+ *
791+ ******************************************************************************/
792+
793+typedef struct s_frag SK_FRAG;
794+struct s_frag {
795+ SK_FRAG *pNext;
796+ char *pVirt;
797+ SK_U64 pPhys;
798+ unsigned int FragLen;
799 };
800
801-/* Used interrupt bits in the interrupts source register *********************/
802+typedef struct s_packet SK_PACKET;
803+struct s_packet {
804+ /* Common infos: */
805+ SK_PACKET *pNext; /* pointer for packet queues */
806+ unsigned int PacketLen; /* length of packet */
807+ unsigned int NumFrags; /* nbr of fragments (for Rx always 1) */
808+ SK_FRAG *pFrag; /* fragment list */
809+ SK_FRAG FragArray[MAX_NUM_FRAGS]; /* TX fragment array */
810+ unsigned int NextLE; /* next LE to use for the next packet */
811+
812+ /* Private infos: */
813+ struct sk_buff *pMBuf; /* Pointer to Linux' socket buffer */
814+};
815+
816+typedef struct s_queue SK_PKT_QUEUE;
817+struct s_queue {
818+ SK_PACKET *pHead;
819+ SK_PACKET *pTail;
820+ spinlock_t QueueLock; /* serialize packet accesses */
821+};
822+
823+/*******************************************************************************
824+ *
825+ * Macros specific for Yukon-II queues
826+ *
827+ ******************************************************************************/
828+
829+#define IS_Q_EMPTY(pQueue) ((pQueue)->pHead != NULL) ? SK_FALSE : SK_TRUE
830+#define IS_Q_LOCKED(pQueue) spin_is_locked(&((pQueue)->QueueLock))
831+
832+#define PLAIN_POP_FIRST_PKT_FROM_QUEUE(pQueue, pPacket) { \
833+ if ((pQueue)->pHead != NULL) { \
834+ (pPacket) = (pQueue)->pHead; \
835+ (pQueue)->pHead = (pPacket)->pNext; \
836+ if ((pQueue)->pHead == NULL) { \
837+ (pQueue)->pTail = NULL; \
838+ } \
839+ (pPacket)->pNext = NULL; \
840+ } else { \
841+ (pPacket) = NULL; \
842+ } \
843+}
844+
845+#define PLAIN_PUSH_PKT_AS_FIRST_IN_QUEUE(pQueue, pPacket) { \
846+ if ((pQueue)->pHead != NULL) { \
847+ (pPacket)->pNext = (pQueue)->pHead; \
848+ } else { \
849+ (pPacket)->pNext = NULL; \
850+ (pQueue)->pTail = (pPacket); \
851+ } \
852+ (pQueue)->pHead = (pPacket); \
853+}
854+
855+#define PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(pQueue, pPacket) { \
856+ (pPacket)->pNext = NULL; \
857+ if ((pQueue)->pTail != NULL) { \
858+ (pQueue)->pTail->pNext = (pPacket); \
859+ } else { \
860+ (pQueue)->pHead = (pPacket); \
861+ } \
862+ (pQueue)->pTail = (pPacket); \
863+}
864+
865+#define PLAIN_PUSH_MULTIPLE_PKT_AS_LAST_IN_QUEUE(pQueue,pPktGrpStart,pPktGrpEnd) { \
866+ if ((pPktGrpStart) != NULL) { \
867+ if ((pQueue)->pTail != NULL) { \
868+ (pQueue)->pTail->pNext = (pPktGrpStart); \
869+ } else { \
870+ (pQueue)->pHead = (pPktGrpStart); \
871+ } \
872+ (pQueue)->pTail = (pPktGrpEnd); \
873+ } \
874+}
875+
876+/* Required: 'Flags' */
877+#define POP_FIRST_PKT_FROM_QUEUE(pQueue, pPacket) { \
878+ spin_lock_irqsave(&((pQueue)->QueueLock), Flags); \
879+ if ((pQueue)->pHead != NULL) { \
880+ (pPacket) = (pQueue)->pHead; \
881+ (pQueue)->pHead = (pPacket)->pNext; \
882+ if ((pQueue)->pHead == NULL) { \
883+ (pQueue)->pTail = NULL; \
884+ } \
885+ (pPacket)->pNext = NULL; \
886+ } else { \
887+ (pPacket) = NULL; \
888+ } \
889+ spin_unlock_irqrestore(&((pQueue)->QueueLock), Flags); \
890+}
891+
892+/* Required: 'Flags' */
893+#define PUSH_PKT_AS_FIRST_IN_QUEUE(pQueue, pPacket) { \
894+ spin_lock_irqsave(&(pQueue)->QueueLock, Flags); \
895+ if ((pQueue)->pHead != NULL) { \
896+ (pPacket)->pNext = (pQueue)->pHead; \
897+ } else { \
898+ (pPacket)->pNext = NULL; \
899+ (pQueue)->pTail = (pPacket); \
900+ } \
901+ (pQueue)->pHead = (pPacket); \
902+ spin_unlock_irqrestore(&(pQueue)->QueueLock, Flags); \
903+}
904+
905+/* Required: 'Flags' */
906+#define PUSH_PKT_AS_LAST_IN_QUEUE(pQueue, pPacket) { \
907+ (pPacket)->pNext = NULL; \
908+ spin_lock_irqsave(&(pQueue)->QueueLock, Flags); \
909+ if ((pQueue)->pTail != NULL) { \
910+ (pQueue)->pTail->pNext = (pPacket); \
911+ } else { \
912+ (pQueue)->pHead = (pPacket); \
913+ } \
914+ (pQueue)->pTail = (pPacket); \
915+ spin_unlock_irqrestore(&(pQueue)->QueueLock, Flags); \
916+}
917+
918+/* Required: 'Flags' */
919+#define PUSH_MULTIPLE_PKT_AS_LAST_IN_QUEUE(pQueue,pPktGrpStart,pPktGrpEnd) { \
920+ if ((pPktGrpStart) != NULL) { \
921+ spin_lock_irqsave(&(pQueue)->QueueLock, Flags); \
922+ if ((pQueue)->pTail != NULL) { \
923+ (pQueue)->pTail->pNext = (pPktGrpStart); \
924+ } else { \
925+ (pQueue)->pHead = (pPktGrpStart); \
926+ } \
927+ (pQueue)->pTail = (pPktGrpEnd); \
928+ spin_unlock_irqrestore(&(pQueue)->QueueLock, Flags); \
929+ } \
930+}
931+
932+/*
933+ *Check if the low address (32 bit) is near the 4G limit or over it.
934+ * Set the high address to a wrong value.
935+ * Doing so we force to write the ADDR64 LE.
936+ */
937+#define CHECK_LOW_ADDRESS( _HighAddress, _LowAddress , _Length) { \
938+ if ((~0-_LowAddress) <_Length) { \
939+ _HighAddress= MAXIMUM_LOW_ADDRESS; \
940+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, \
941+ ("High Address must be set for HW. LowAddr = %d Length = %d\n", \
942+ _LowAddress, _Length)); \
943+ } \
944+}
945+
946+/*******************************************************************************
947+ *
948+ * Macros specific for Yukon-II queues (tist)
949+ *
950+ ******************************************************************************/
951+
952+#ifdef USE_TIST_FOR_RESET
953+/* port is fully operational */
954+#define SK_PSTATE_NOT_WAITING_FOR_TIST 0
955+/* port in reset until any tist LE */
956+#define SK_PSTATE_WAITING_FOR_ANY_TIST BIT_0
957+/* port in reset until timer reaches pAC->MinTistLo */
958+#define SK_PSTATE_WAITING_FOR_SPECIFIC_TIST BIT_1
959+#define SK_PSTATE_PORT_SHIFT 4
960+#define SK_PSTATE_PORT_MASK ((1 << SK_PSTATE_PORT_SHIFT) - 1)
961+
962+/* use this + Port to build OP_MOD_TXINDEX_NO_PORT_A|B */
963+#define OP_MOD_TXINDEX 0x71
964+/* opcode for a TX_INDEX LE in which Port A has to be ignored */
965+#define OP_MOD_TXINDEX_NO_PORT_A 0x71
966+/* opcode for a TX_INDEX LE in which Port B has to be ignored */
967+#define OP_MOD_TXINDEX_NO_PORT_B 0x72
968+/* opcode for LE to be ignored because port is still in reset */
969+#define OP_MOD_LE 0x7F
970+
971+/* set tist wait mode Bit for port */
972+#define SK_SET_WAIT_BIT_FOR_PORT(pAC, Bit, Port) \
973+ { \
974+ (pAC)->AdapterResetState |= ((Bit) << (SK_PSTATE_PORT_SHIFT * Port)); \
975+ }
976+
977+/* reset tist waiting for specified port */
978+#define SK_CLR_STATE_FOR_PORT(pAC, Port) \
979+ { \
980+ (pAC)->AdapterResetState &= \
981+ ~(SK_PSTATE_PORT_MASK << (SK_PSTATE_PORT_SHIFT * Port)); \
982+ }
983+
984+/* return SK_TRUE when port is in reset waiting for tist */
985+#define SK_PORT_WAITING_FOR_TIST(pAC, Port) \
986+ ((((pAC)->AdapterResetState >> (SK_PSTATE_PORT_SHIFT * Port)) & \
987+ SK_PSTATE_PORT_MASK) != SK_PSTATE_NOT_WAITING_FOR_TIST)
988+
989+/* return SK_TRUE when port is in reset waiting for any tist */
990+#define SK_PORT_WAITING_FOR_ANY_TIST(pAC, Port) \
991+ ((((pAC)->AdapterResetState >> (SK_PSTATE_PORT_SHIFT * Port)) & \
992+ SK_PSTATE_WAITING_FOR_ANY_TIST) == SK_PSTATE_WAITING_FOR_ANY_TIST)
993+
994+/* return SK_TRUE when port is in reset waiting for a specific tist */
995+#define SK_PORT_WAITING_FOR_SPECIFIC_TIST(pAC, Port) \
996+ ((((pAC)->AdapterResetState >> (SK_PSTATE_PORT_SHIFT * Port)) & \
997+ SK_PSTATE_WAITING_FOR_SPECIFIC_TIST) == \
998+ SK_PSTATE_WAITING_FOR_SPECIFIC_TIST)
999+
1000+/* return whether adapter is expecting a tist LE */
1001+#define SK_ADAPTER_WAITING_FOR_TIST(pAC) ((pAC)->AdapterResetState != 0)
1002+
1003+/* enable timestamp timer and force creation of tist LEs */
1004+#define Y2_ENABLE_TIST(IoC) \
1005+ SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8) GMT_ST_START)
1006+
1007+/* disable timestamp timer and stop creation of tist LEs */
1008+#define Y2_DISABLE_TIST(IoC) \
1009+ SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8) GMT_ST_STOP)
1010+
1011+/* get current value of timestamp timer */
1012+#define Y2_GET_TIST_LOW_VAL(IoC, pVal) \
1013+ SK_IN32(IoC, GMAC_TI_ST_VAL, pVal)
1014
1015-#define DRIVER_IRQS ((IS_IRQ_SW) | \
1016- (IS_R1_F) |(IS_R2_F) | \
1017- (IS_XS1_F) |(IS_XA1_F) | \
1018- (IS_XS2_F) |(IS_XA2_F))
1019-
1020-#define SPECIAL_IRQS ((IS_HW_ERR) |(IS_I2C_READY) | \
1021- (IS_EXT_REG) |(IS_TIMINT) | \
1022- (IS_PA_TO_RX1) |(IS_PA_TO_RX2) | \
1023- (IS_PA_TO_TX1) |(IS_PA_TO_TX2) | \
1024- (IS_MAC1) |(IS_LNK_SYNC_M1)| \
1025- (IS_MAC2) |(IS_LNK_SYNC_M2)| \
1026- (IS_R1_C) |(IS_R2_C) | \
1027- (IS_XS1_C) |(IS_XA1_C) | \
1028- (IS_XS2_C) |(IS_XA2_C))
1029-
1030-#define IRQ_MASK ((IS_IRQ_SW) | \
1031- (IS_R1_B) |(IS_R1_F) |(IS_R2_B) |(IS_R2_F) | \
1032- (IS_XS1_B) |(IS_XS1_F) |(IS_XA1_B)|(IS_XA1_F)| \
1033- (IS_XS2_B) |(IS_XS2_F) |(IS_XA2_B)|(IS_XA2_F)| \
1034- (IS_HW_ERR) |(IS_I2C_READY)| \
1035- (IS_EXT_REG) |(IS_TIMINT) | \
1036- (IS_PA_TO_RX1) |(IS_PA_TO_RX2)| \
1037- (IS_PA_TO_TX1) |(IS_PA_TO_TX2)| \
1038- (IS_MAC1) |(IS_MAC2) | \
1039- (IS_R1_C) |(IS_R2_C) | \
1040- (IS_XS1_C) |(IS_XA1_C) | \
1041- (IS_XS2_C) |(IS_XA2_C))
1042+#endif
1043
1044-#define IRQ_HWE_MASK (IS_ERR_MSK) /* enable all HW irqs */
1045+
1046+/*******************************************************************************
1047+ *
1048+ * Used interrupt bits in the interrupts source register
1049+ *
1050+ ******************************************************************************/
1051+
1052+#define DRIVER_IRQS ((IS_IRQ_SW) | \
1053+ (IS_R1_F) | (IS_R2_F) | \
1054+ (IS_XS1_F) | (IS_XA1_F) | \
1055+ (IS_XS2_F) | (IS_XA2_F))
1056+
1057+#define TX_COMPL_IRQS ((IS_XS1_B) | (IS_XS1_F) | \
1058+ (IS_XA1_B) | (IS_XA1_F) | \
1059+ (IS_XS2_B) | (IS_XS2_F) | \
1060+ (IS_XA2_B) | (IS_XA2_F))
1061+
1062+#define NAPI_DRV_IRQS ((IS_R1_F) | (IS_R2_F) | \
1063+ (IS_XS1_F) | (IS_XA1_F)| \
1064+ (IS_XS2_F) | (IS_XA2_F))
1065+
1066+#define Y2_DRIVER_IRQS ((Y2_IS_STAT_BMU) | (Y2_IS_IRQ_SW) | (Y2_IS_POLL_CHK))
1067+
1068+#define SPECIAL_IRQS ((IS_HW_ERR) |(IS_I2C_READY) | \
1069+ (IS_EXT_REG) |(IS_TIMINT) | \
1070+ (IS_PA_TO_RX1) |(IS_PA_TO_RX2) | \
1071+ (IS_PA_TO_TX1) |(IS_PA_TO_TX2) | \
1072+ (IS_MAC1) |(IS_LNK_SYNC_M1)| \
1073+ (IS_MAC2) |(IS_LNK_SYNC_M2)| \
1074+ (IS_R1_C) |(IS_R2_C) | \
1075+ (IS_XS1_C) |(IS_XA1_C) | \
1076+ (IS_XS2_C) |(IS_XA2_C))
1077+
1078+#define Y2_SPECIAL_IRQS ((Y2_IS_HW_ERR) |(Y2_IS_ASF) | \
1079+ (Y2_IS_TWSI_RDY) |(Y2_IS_TIMINT) | \
1080+ (Y2_IS_IRQ_PHY2) |(Y2_IS_IRQ_MAC2) | \
1081+ (Y2_IS_CHK_RX2) |(Y2_IS_CHK_TXS2) | \
1082+ (Y2_IS_CHK_TXA2) |(Y2_IS_IRQ_PHY1) | \
1083+ (Y2_IS_IRQ_MAC1) |(Y2_IS_CHK_RX1) | \
1084+ (Y2_IS_CHK_TXS1) |(Y2_IS_CHK_TXA1))
1085+
1086+#define IRQ_MASK ((IS_IRQ_SW) | \
1087+ (IS_R1_F) |(IS_R2_F) | \
1088+ (IS_XS1_F) |(IS_XA1_F) | \
1089+ (IS_XS2_F) |(IS_XA2_F) | \
1090+ (IS_HW_ERR) |(IS_I2C_READY)| \
1091+ (IS_EXT_REG) |(IS_TIMINT) | \
1092+ (IS_PA_TO_RX1) |(IS_PA_TO_RX2)| \
1093+ (IS_PA_TO_TX1) |(IS_PA_TO_TX2)| \
1094+ (IS_MAC1) |(IS_MAC2) | \
1095+ (IS_R1_C) |(IS_R2_C) | \
1096+ (IS_XS1_C) |(IS_XA1_C) | \
1097+ (IS_XS2_C) |(IS_XA2_C))
1098+
1099+#define Y2_IRQ_MASK ((Y2_DRIVER_IRQS) | (Y2_SPECIAL_IRQS))
1100+
1101+#define IRQ_HWE_MASK (IS_ERR_MSK) /* enable all HW irqs */
1102+#define Y2_IRQ_HWE_MASK (Y2_HWE_ALL_MSK) /* enable all HW irqs */
1103
1104 typedef struct s_DevNet DEV_NET;
1105
1106 struct s_DevNet {
1107- int PortNr;
1108- int NetNr;
1109- SK_AC *pAC;
1110+ struct proc_dir_entry *proc;
1111+ int PortNr;
1112+ int NetNr;
1113+ char InitialDevName[20];
1114+ SK_BOOL NetConsoleMode;
1115+#ifdef Y2_RECOVERY
1116+ struct timer_list KernelTimer; /* Kernel timer struct */
1117+ int TransmitTimeoutTimer; /* Transmit timer */
1118+ SK_BOOL TimerExpired; /* Transmit timer */
1119+ SK_BOOL InRecover; /* Recover flag */
1120+#ifdef Y2_RX_CHECK
1121+ SK_U32 PreviousMACFifoRP; /* Backup of the FRP */
1122+ SK_U32 PreviousMACFifoRLev; /* Backup of the FRL */
1123+ SK_U32 PreviousRXFifoRP; /* Backup of the RX FRP */
1124+ SK_U8 PreviousRXFifoRLev; /* Backup of the RX FRL */
1125+ SK_U32 LastJiffies; /* Backup of the jiffies*/
1126+#endif
1127+#endif
1128+ SK_AC *pAC;
1129 };
1130
1131-typedef struct s_TxPort TX_PORT;
1132+/*******************************************************************************
1133+ *
1134+ * Rx/Tx Port structures
1135+ *
1136+ ******************************************************************************/
1137
1138-struct s_TxPort {
1139- /* the transmit descriptor rings */
1140- caddr_t pTxDescrRing; /* descriptor area memory */
1141- SK_U64 VTxDescrRing; /* descr. area bus virt. addr. */
1142- TXD *pTxdRingHead; /* Head of Tx rings */
1143- TXD *pTxdRingTail; /* Tail of Tx rings */
1144- TXD *pTxdRingPrev; /* descriptor sent previously */
1145- int TxdRingFree; /* # of free entrys */
1146- spinlock_t TxDesRingLock; /* serialize descriptor accesses */
1147- SK_IOC HwAddr; /* bmu registers address */
1148- int PortIndex; /* index number of port (0 or 1) */
1149+typedef struct s_TxPort TX_PORT;
1150+struct s_TxPort { /* the transmit descriptor rings */
1151+ caddr_t pTxDescrRing; /* descriptor area memory */
1152+ SK_U64 VTxDescrRing; /* descr. area bus virt. addr. */
1153+ TXD *pTxdRingHead; /* Head of Tx rings */
1154+ TXD *pTxdRingTail; /* Tail of Tx rings */
1155+ TXD *pTxdRingPrev; /* descriptor sent previously */
1156+ int TxdRingPrevFree;/* previously # of free entrys */
1157+ int TxdRingFree; /* # of free entrys */
1158+ spinlock_t TxDesRingLock; /* serialize descriptor accesses */
1159+ caddr_t HwAddr; /* bmu registers address */
1160+ int PortIndex; /* index number of port (0 or 1) */
1161+ SK_PACKET *TransmitPacketTable;
1162+ SK_LE_TABLE TxALET; /* tx (async) list element table */
1163+ SK_LE_TABLE TxSLET; /* tx (sync) list element table */
1164+ SK_PKT_QUEUE TxQ_free;
1165+ SK_PKT_QUEUE TxAQ_waiting;
1166+ SK_PKT_QUEUE TxSQ_waiting;
1167+ SK_PKT_QUEUE TxAQ_working;
1168+ SK_PKT_QUEUE TxSQ_working;
1169+ unsigned LastDone;
1170 };
1171
1172-typedef struct s_RxPort RX_PORT;
1173-
1174-struct s_RxPort {
1175- /* the receive descriptor rings */
1176- caddr_t pRxDescrRing; /* descriptor area memory */
1177- SK_U64 VRxDescrRing; /* descr. area bus virt. addr. */
1178- RXD *pRxdRingHead; /* Head of Rx rings */
1179- RXD *pRxdRingTail; /* Tail of Rx rings */
1180- RXD *pRxdRingPrev; /* descriptor given to BMU previously */
1181- int RxdRingFree; /* # of free entrys */
1182- int RxCsum; /* use receive checksum hardware */
1183- spinlock_t RxDesRingLock; /* serialize descriptor accesses */
1184- int RxFillLimit; /* limit for buffers in ring */
1185- SK_IOC HwAddr; /* bmu registers address */
1186- int PortIndex; /* index number of port (0 or 1) */
1187+typedef struct s_RxPort RX_PORT;
1188+struct s_RxPort { /* the receive descriptor rings */
1189+ caddr_t pRxDescrRing; /* descriptor area memory */
1190+ SK_U64 VRxDescrRing; /* descr. area bus virt. addr. */
1191+ RXD *pRxdRingHead; /* Head of Rx rings */
1192+ RXD *pRxdRingTail; /* Tail of Rx rings */
1193+ RXD *pRxdRingPrev; /* descr given to BMU previously */
1194+ int RxdRingFree; /* # of free entrys */
1195+ spinlock_t RxDesRingLock; /* serialize descriptor accesses */
1196+ int RxFillLimit; /* limit for buffers in ring */
1197+ caddr_t HwAddr; /* bmu registers address */
1198+ int PortIndex; /* index number of port (0 or 1) */
1199+ SK_BOOL UseRxCsum; /* use Rx checksumming (yes/no) */
1200+ SK_PACKET *ReceivePacketTable;
1201+ SK_LE_TABLE RxLET; /* rx list element table */
1202+ SK_PKT_QUEUE RxQ_working;
1203+ SK_PKT_QUEUE RxQ_waiting;
1204+ int RxBufSize;
1205 };
1206
1207-/* Definitions needed for interrupt moderation *******************************/
1208+/*******************************************************************************
1209+ *
1210+ * Interrupt masks used in combination with interrupt moderation
1211+ *
1212+ ******************************************************************************/
1213
1214 #define IRQ_EOF_AS_TX ((IS_XA1_F) | (IS_XA2_F))
1215 #define IRQ_EOF_SY_TX ((IS_XS1_F) | (IS_XS2_F))
1216@@ -314,134 +732,151 @@
1217 #define IRQ_MASK_SP_TX ((SPECIAL_IRQS) | (IRQ_MASK_TX_ONLY))
1218 #define IRQ_MASK_RX_TX_SP ((SPECIAL_IRQS) | (IRQ_MASK_TX_RX))
1219
1220-#define C_INT_MOD_NONE 1
1221-#define C_INT_MOD_STATIC 2
1222-#define C_INT_MOD_DYNAMIC 4
1223-
1224-#define C_CLK_FREQ_GENESIS 53215000 /* shorter: 53.125 MHz */
1225-#define C_CLK_FREQ_YUKON 78215000 /* shorter: 78.125 MHz */
1226-
1227-#define C_INTS_PER_SEC_DEFAULT 2000
1228-#define C_INT_MOD_ENABLE_PERCENTAGE 50 /* if higher 50% enable */
1229-#define C_INT_MOD_DISABLE_PERCENTAGE 50 /* if lower 50% disable */
1230-#define C_INT_MOD_IPS_LOWER_RANGE 30
1231-#define C_INT_MOD_IPS_UPPER_RANGE 40000
1232-
1233-
1234-typedef struct s_DynIrqModInfo DIM_INFO;
1235-struct s_DynIrqModInfo {
1236- unsigned long PrevTimeVal;
1237- unsigned int PrevSysLoad;
1238- unsigned int PrevUsedTime;
1239- unsigned int PrevTotalTime;
1240- int PrevUsedDescrRatio;
1241- int NbrProcessedDescr;
1242- SK_U64 PrevPort0RxIntrCts;
1243- SK_U64 PrevPort1RxIntrCts;
1244- SK_U64 PrevPort0TxIntrCts;
1245- SK_U64 PrevPort1TxIntrCts;
1246- SK_BOOL ModJustEnabled; /* Moderation just enabled yes/no */
1247-
1248- int MaxModIntsPerSec; /* Moderation Threshold */
1249- int MaxModIntsPerSecUpperLimit; /* Upper limit for DIM */
1250- int MaxModIntsPerSecLowerLimit; /* Lower limit for DIM */
1251-
1252- long MaskIrqModeration; /* ModIrqType (eg. 'TxRx') */
1253- SK_BOOL DisplayStats; /* Stats yes/no */
1254- SK_BOOL AutoSizing; /* Resize DIM-timer on/off */
1255- int IntModTypeSelect; /* EnableIntMod (eg. 'dynamic') */
1256+#define IRQ_MASK_Y2_TX_ONLY (Y2_IS_STAT_BMU)
1257+#define IRQ_MASK_Y2_RX_ONLY (Y2_IS_STAT_BMU)
1258+#define IRQ_MASK_Y2_SP_ONLY (SPECIAL_IRQS)
1259+#define IRQ_MASK_Y2_TX_RX ((IRQ_MASK_TX_ONLY)| (IRQ_MASK_RX_ONLY))
1260+#define IRQ_MASK_Y2_SP_RX ((SPECIAL_IRQS) | (IRQ_MASK_RX_ONLY))
1261+#define IRQ_MASK_Y2_SP_TX ((SPECIAL_IRQS) | (IRQ_MASK_TX_ONLY))
1262+#define IRQ_MASK_Y2_RX_TX_SP ((SPECIAL_IRQS) | (IRQ_MASK_TX_RX))
1263
1264- SK_TIMER ModTimer; /* just some timer */
1265-};
1266+/*******************************************************************************
1267+ *
1268+ * Defines and typedefs regarding interrupt moderation
1269+ *
1270+ ******************************************************************************/
1271
1272-typedef struct s_PerStrm PER_STRM;
1273+#define C_INT_MOD_NONE 1
1274+#define C_INT_MOD_STATIC 2
1275+#define C_INT_MOD_DYNAMIC 4
1276+
1277+#define C_CLK_FREQ_GENESIS 53215000 /* or: 53.125 MHz */
1278+#define C_CLK_FREQ_YUKON 78215000 /* or: 78.125 MHz */
1279+#define C_CLK_FREQ_YUKON_EC 125000000 /* or: 125.000 MHz */
1280+
1281+#define C_Y2_INTS_PER_SEC_DEFAULT 5000
1282+#define C_INTS_PER_SEC_DEFAULT 2000
1283+#define C_INT_MOD_IPS_LOWER_RANGE 30 /* in IRQs/second */
1284+#define C_INT_MOD_IPS_UPPER_RANGE 40000 /* in IRQs/second */
1285+
1286+typedef struct s_DynIrqModInfo {
1287+ SK_U64 PrevPort0RxIntrCts;
1288+ SK_U64 PrevPort1RxIntrCts;
1289+ SK_U64 PrevPort0TxIntrCts;
1290+ SK_U64 PrevPort1TxIntrCts;
1291+ SK_U64 PrevPort0StatusLeIntrCts;
1292+ SK_U64 PrevPort1StatusLeIntrCts;
1293+ int MaxModIntsPerSec; /* Moderation Threshold */
1294+ int MaxModIntsPerSecUpperLimit; /* Upper limit for DIM */
1295+ int MaxModIntsPerSecLowerLimit; /* Lower limit for DIM */
1296+ long MaskIrqModeration; /* IRQ Mask (eg. 'TxRx') */
1297+ int IntModTypeSelect; /* Type (eg. 'dynamic') */
1298+ int DynIrqModSampleInterval; /* expressed in seconds! */
1299+ SK_TIMER ModTimer; /* Timer for dynamic mod. */
1300+} DIM_INFO;
1301
1302-#define SK_ALLOC_IRQ 0x00000001
1303+/*******************************************************************************
1304+ *
1305+ * Defines and typedefs regarding wake-on-lan
1306+ *
1307+ ******************************************************************************/
1308+
1309+typedef struct s_WakeOnLanInfo {
1310+ SK_U32 SupportedWolOptions; /* e.g. WAKE_PHY... */
1311+ SK_U32 ConfiguredWolOptions; /* e.g. WAKE_PHY... */
1312+} WOL_INFO;
1313
1314-#ifdef SK_DIAG_SUPPORT
1315+#define SK_ALLOC_IRQ 0x00000001
1316 #define DIAG_ACTIVE 1
1317 #define DIAG_NOTACTIVE 0
1318-#endif
1319
1320 /****************************************************************************
1321+ *
1322 * Per board structure / Adapter Context structure:
1323- * Allocated within attach(9e) and freed within detach(9e).
1324- * Contains all 'per device' necessary handles, flags, locks etc.:
1325- */
1326+ * Contains all 'per device' necessary handles, flags, locks etc.:
1327+ *
1328+ ******************************************************************************/
1329+
1330 struct s_AC {
1331- SK_GEINIT GIni; /* GE init struct */
1332- SK_PNMI Pnmi; /* PNMI data struct */
1333- SK_VPD vpd; /* vpd data struct */
1334- SK_QUEUE Event; /* Event queue */
1335- SK_HWT Hwt; /* Hardware Timer control struct */
1336- SK_TIMCTRL Tim; /* Software Timer control struct */
1337- SK_I2C I2c; /* I2C relevant data structure */
1338- SK_ADDR Addr; /* for Address module */
1339- SK_CSUM Csum; /* for checksum module */
1340- SK_RLMT Rlmt; /* for rlmt module */
1341- spinlock_t SlowPathLock; /* Normal IRQ lock */
1342- struct timer_list BlinkTimer; /* for LED blinking */
1343- int LedsOn;
1344- SK_PNMI_STRUCT_DATA PnmiStruct; /* structure to get all Pnmi-Data */
1345- int RlmtMode; /* link check mode to set */
1346- int RlmtNets; /* Number of nets */
1347-
1348- SK_IOC IoBase; /* register set of adapter */
1349- int BoardLevel; /* level of active hw init (0-2) */
1350-
1351- SK_U32 AllocFlag; /* flag allocation of resources */
1352- struct pci_dev *PciDev; /* for access to pci config space */
1353- struct SK_NET_DEVICE *dev[2]; /* pointer to device struct */
1354-
1355- int RxBufSize; /* length of receive buffers */
1356- struct net_device_stats stats; /* linux 'netstat -i' statistics */
1357- int Index; /* internal board index number */
1358-
1359- /* adapter RAM sizes for queues of active port */
1360- int RxQueueSize; /* memory used for receive queue */
1361- int TxSQueueSize; /* memory used for sync. tx queue */
1362- int TxAQueueSize; /* memory used for async. tx queue */
1363-
1364- int PromiscCount; /* promiscuous mode counter */
1365- int AllMultiCount; /* allmulticast mode counter */
1366- int MulticCount; /* number of different MC */
1367- /* addresses for this board */
1368- /* (may be more than HW can)*/
1369-
1370- int HWRevision; /* Hardware revision */
1371- int ActivePort; /* the active XMAC port */
1372- int MaxPorts; /* number of activated ports */
1373- int TxDescrPerRing; /* # of descriptors per tx ring */
1374- int RxDescrPerRing; /* # of descriptors per rx ring */
1375-
1376- caddr_t pDescrMem; /* Pointer to the descriptor area */
1377- dma_addr_t pDescrMemDMA; /* PCI DMA address of area */
1378-
1379- /* the port structures with descriptor rings */
1380- TX_PORT TxPort[SK_MAX_MACS][2];
1381- RX_PORT RxPort[SK_MAX_MACS];
1382-
1383- SK_BOOL CheckQueue; /* check event queue soon */
1384- SK_TIMER DrvCleanupTimer;/* to check for pending descriptors */
1385- DIM_INFO DynIrqModInfo; /* all data related to DIM */
1386-
1387- /* Only for tests */
1388- int PortDown;
1389- int ChipsetType; /* Chipset family type
1390- * 0 == Genesis family support
1391- * 1 == Yukon family support
1392- */
1393-#ifdef SK_DIAG_SUPPORT
1394- SK_U32 DiagModeActive; /* is diag active? */
1395- SK_BOOL DiagFlowCtrl; /* for control purposes */
1396- SK_PNMI_STRUCT_DATA PnmiBackup; /* backup structure for all Pnmi-Data */
1397- SK_BOOL WasIfUp[SK_MAX_MACS]; /* for OpenClose while
1398- * DIAG is busy with NIC
1399- */
1400+ SK_GEINIT GIni; /* GE init struct */
1401+ SK_PNMI Pnmi; /* PNMI data struct */
1402+ SK_VPD vpd; /* vpd data struct */
1403+ SK_QUEUE Event; /* Event queue */
1404+ SK_HWT Hwt; /* Hardware Timer ctrl struct */
1405+ SK_TIMCTRL Tim; /* Software Timer ctrl struct */
1406+ SK_I2C I2c; /* I2C relevant data structure*/
1407+ SK_ADDR Addr; /* for Address module */
1408+ SK_CSUM Csum; /* for checksum module */
1409+ SK_RLMT Rlmt; /* for rlmt module */
1410+ spinlock_t SlowPathLock; /* Normal IRQ lock */
1411+ spinlock_t InitLock; /* Init lock */
1412+ spinlock_t TxQueueLock; /* TX Queue lock */
1413+ SK_PNMI_STRUCT_DATA PnmiStruct; /* struct for all Pnmi-Data */
1414+ int RlmtMode; /* link check mode to set */
1415+ int RlmtNets; /* Number of nets */
1416+ SK_IOC IoBase; /* register set of adapter */
1417+ int BoardLevel; /* level of hw init (0-2) */
1418+ char DeviceStr[80]; /* adapter string from vpd */
1419+ SK_U32 AllocFlag; /* alloc flag of resources */
1420+ struct pci_dev *PciDev; /* for access to pci cfg space*/
1421+ SK_U32 PciDevId; /* pci device id */
1422+ struct SK_NET_DEVICE *dev[2]; /* pointer to device struct */
1423+ char Name[30]; /* driver name */
1424+ struct SK_NET_DEVICE *Next; /* link all devs for cleanup */
1425+ struct net_device_stats stats; /* linux 'netstat -i' stats */
1426+ int Index; /* internal board idx number */
1427+ int RxQueueSize; /* memory used for RX queue */
1428+ int TxSQueueSize; /* memory used for TXS queue */
1429+ int TxAQueueSize; /* memory used for TXA queue */
1430+ int PromiscCount; /* promiscuous mode counter */
1431+ int AllMultiCount; /* allmulticast mode counter */
1432+ int MulticCount; /* number of MC addresses used*/
1433+ int HWRevision; /* Hardware revision */
1434+ int ActivePort; /* the active XMAC port */
1435+ int MaxPorts; /* number of activated ports */
1436+ int TxDescrPerRing;/* # of descriptors TX ring */
1437+ int RxDescrPerRing;/* # of descriptors RX ring */
1438+ caddr_t pDescrMem; /* Ptr to the descriptor area */
1439+ dma_addr_t pDescrMemDMA; /* PCI DMA address of area */
1440+ SK_U32 PciState[16]; /* PCI state */
1441+ TX_PORT TxPort[SK_MAX_MACS][2];
1442+ RX_PORT RxPort[SK_MAX_MACS];
1443+ SK_LE_TABLE StatusLETable;
1444+ unsigned SizeOfAlignedLETables;
1445+ spinlock_t SetPutIndexLock;
1446+ int MaxUnusedRxLeWorking;
1447+ unsigned int CsOfs1; /* for checksum calculation */
1448+ unsigned int CsOfs2; /* for checksum calculation */
1449+ SK_U32 CsOfs; /* for checksum calculation */
1450+ SK_BOOL CheckQueue; /* check event queue soon */
1451+ DIM_INFO DynIrqModInfo; /* all data related to IntMod */
1452+ WOL_INFO WolInfo; /* all info regarding WOL */
1453+ int ChipsetType; /* 0=GENESIS; 1=Yukon */
1454+ SK_BOOL LowLatency; /* LowLatency optimization on?*/
1455+ SK_U32 DiagModeActive;/* is diag active? */
1456+ SK_BOOL DiagFlowCtrl; /* for control purposes */
1457+ SK_PNMI_STRUCT_DATA PnmiBackup; /* backup structure for PNMI */
1458+ SK_BOOL WasIfUp[SK_MAX_MACS];
1459+#ifdef USE_TIST_FOR_RESET
1460+ int AdapterResetState;
1461+ SK_U32 MinTistLo;
1462+ SK_U32 MinTistHi;
1463+#endif
1464+#ifdef Y2_RECOVERY
1465+ int LastPort; /* port for curr. handled rx */
1466+ int LastOpc; /* last rx LEs opcode */
1467+#endif
1468+#ifdef Y2_SYNC_CHECK
1469+ unsigned long FramesWithoutSyncCheck; /* since last check */
1470 #endif
1471-
1472 };
1473
1474
1475-#endif /* __INC_SKDRV2ND_H */
1476
1477+#endif
1478+
1479+/*******************************************************************************
1480+ *
1481+ * End of file
1482+ *
1483+ ******************************************************************************/
1484diff -ruN linux/drivers/net/sk98lin/h/skerror.h linux-new/drivers/net/sk98lin/h/skerror.h
1485--- linux/drivers/net/sk98lin/h/skerror.h 2006-04-11 19:19:28.000000000 +0200
1486+++ linux-new/drivers/net/sk98lin/h/skerror.h 2006-01-18 14:37:24.000000000 +0100
1487@@ -2,23 +2,24 @@
1488 *
1489 * Name: skerror.h
1490 * Project: Gigabit Ethernet Adapters, Common Modules
1491- * Version: $Revision$
1492- * Date: $Date$
1493+ * Version: $Revision$
1494+ * Date: $Date$
1495 * Purpose: SK specific Error log support
1496 *
1497 ******************************************************************************/
1498
1499 /******************************************************************************
1500 *
1501+ * LICENSE:
1502 * (C)Copyright 1998-2002 SysKonnect.
1503- * (C)Copyright 2002-2003 Marvell.
1504+ * (C)Copyright 2002-2004 Marvell.
1505 *
1506 * This program is free software; you can redistribute it and/or modify
1507 * it under the terms of the GNU General Public License as published by
1508 * the Free Software Foundation; either version 2 of the License, or
1509 * (at your option) any later version.
1510- *
1511 * The information in this file is provided "AS IS" without warranty.
1512+ * /LICENSE
1513 *
1514 ******************************************************************************/
1515
1516@@ -36,7 +37,6 @@
1517 #define SK_ERRCL_HW (1L<<4) /* Hardware Failure */
1518 #define SK_ERRCL_COMM (1L<<5) /* Communication error */
1519
1520-
1521 /*
1522 * Define Error Code Bases
1523 */
1524@@ -49,7 +49,9 @@
1525 #define SK_ERRBASE_I2C 700 /* Base Error number for I2C module */
1526 #define SK_ERRBASE_QUEUE 800 /* Base Error number for Scheduler */
1527 #define SK_ERRBASE_ADDR 900 /* Base Error number for Address module */
1528-#define SK_ERRBASE_PECP 1000 /* Base Error number for PECP */
1529+#define SK_ERRBASE_PECP 1000 /* Base Error number for PECP */
1530 #define SK_ERRBASE_DRV 1100 /* Base Error number for Driver */
1531+#define SK_ERRBASE_ASF 1200 /* Base Error number for ASF */
1532
1533 #endif /* _INC_SKERROR_H_ */
1534+
1535diff -ruN linux/drivers/net/sk98lin/h/skgedrv.h linux-new/drivers/net/sk98lin/h/skgedrv.h
1536--- linux/drivers/net/sk98lin/h/skgedrv.h 2006-04-11 19:19:28.000000000 +0200
1537+++ linux-new/drivers/net/sk98lin/h/skgedrv.h 2006-01-18 14:37:24.000000000 +0100
1538@@ -2,23 +2,24 @@
1539 *
1540 * Name: skgedrv.h
1541 * Project: Gigabit Ethernet Adapters, Common Modules
1542- * Version: $Revision$
1543- * Date: $Date$
1544+ * Version: $Revision$
1545+ * Date: $Date$
1546 * Purpose: Interface with the driver
1547 *
1548 ******************************************************************************/
1549
1550 /******************************************************************************
1551 *
1552+ * LICENSE:
1553 * (C)Copyright 1998-2002 SysKonnect.
1554- * (C)Copyright 2002-2003 Marvell.
1555+ * (C)Copyright 2002-2005 Marvell.
1556 *
1557 * This program is free software; you can redistribute it and/or modify
1558 * it under the terms of the GNU General Public License as published by
1559 * the Free Software Foundation; either version 2 of the License, or
1560 * (at your option) any later version.
1561- *
1562 * The information in this file is provided "AS IS" without warranty.
1563+ * /LICENSE
1564 *
1565 ******************************************************************************/
1566
1567@@ -33,7 +34,7 @@
1568 * In case of the driver we put the definition of the events here.
1569 */
1570 #define SK_DRV_PORT_RESET 1 /* The port needs to be reset */
1571-#define SK_DRV_NET_UP 2 /* The net is operational */
1572+#define SK_DRV_NET_UP 2 /* The net is operational */
1573 #define SK_DRV_NET_DOWN 3 /* The net is down */
1574 #define SK_DRV_SWITCH_SOFT 4 /* Ports switch with both links connected */
1575 #define SK_DRV_SWITCH_HARD 5 /* Port switch due to link failure */
1576@@ -44,8 +45,9 @@
1577 #define SK_DRV_POWER_DOWN 10 /* Power down mode */
1578 #define SK_DRV_TIMER 11 /* Timer for free use */
1579 #ifdef SK_NO_RLMT
1580-#define SK_DRV_LINK_UP 12 /* Link Up event for driver */
1581+#define SK_DRV_LINK_UP 12 /* Link Up event for driver */
1582 #define SK_DRV_LINK_DOWN 13 /* Link Down event for driver */
1583 #endif
1584 #define SK_DRV_DOWNSHIFT_DET 14 /* Downshift 4-Pair / 2-Pair (YUKON only) */
1585+#define SK_DRV_RX_OVERFLOW 15 /* Receive Overflow */
1586 #endif /* __INC_SKGEDRV_H_ */
1587diff -ruN linux/drivers/net/sk98lin/h/skgehw.h linux-new/drivers/net/sk98lin/h/skgehw.h
1588--- linux/drivers/net/sk98lin/h/skgehw.h 2006-04-11 19:19:28.000000000 +0200
1589+++ linux-new/drivers/net/sk98lin/h/skgehw.h 2006-01-18 14:37:24.000000000 +0100
1590@@ -2,23 +2,24 @@
1591 *
1592 * Name: skgehw.h
1593 * Project: Gigabit Ethernet Adapters, Common Modules
1594- * Version: $Revision$
1595- * Date: $Date$
1596+ * Version: $Revision$
1597+ * Date: $Date$
1598 * Purpose: Defines and Macros for the Gigabit Ethernet Adapter Product Family
1599 *
1600 ******************************************************************************/
1601
1602 /******************************************************************************
1603 *
1604+ * LICENSE:
1605 * (C)Copyright 1998-2002 SysKonnect.
1606- * (C)Copyright 2002-2003 Marvell.
1607+ * (C)Copyright 2002-2005 Marvell.
1608 *
1609 * This program is free software; you can redistribute it and/or modify
1610 * it under the terms of the GNU General Public License as published by
1611 * the Free Software Foundation; either version 2 of the License, or
1612 * (at your option) any later version.
1613- *
1614 * The information in this file is provided "AS IS" without warranty.
1615+ * /LICENSE
1616 *
1617 ******************************************************************************/
1618
1619@@ -114,6 +115,16 @@
1620 #define SHIFT1(x) ((x) << 1)
1621 #define SHIFT0(x) ((x) << 0)
1622
1623+/* Macro for arbitrary alignment of a given pointer */
1624+#define ALIGN_ADDR( ADDRESS, GRANULARITY ) { \
1625+ SK_UPTR addr = (SK_UPTR)(ADDRESS); \
1626+ if (addr & ((GRANULARITY)-1)) { \
1627+ addr += (GRANULARITY); \
1628+ addr &= ~(SK_UPTR)((GRANULARITY)-1); \
1629+ ADDRESS = (void *)addr; \
1630+ }\
1631+}
1632+
1633 /*
1634 * Configuration Space header
1635 * Since this module is used for different OS', those may be
1636@@ -132,34 +143,81 @@
1637 #define PCI_BIST 0x0f /* 8 bit Built-in selftest */
1638 #define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */
1639 #define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */
1640- /* Byte 0x18..0x2b: reserved */
1641+ /* Bytes 0x18..0x2b: reserved */
1642 #define PCI_SUB_VID 0x2c /* 16 bit Subsystem Vendor ID */
1643 #define PCI_SUB_ID 0x2e /* 16 bit Subsystem ID */
1644 #define PCI_BASE_ROM 0x30 /* 32 bit Expansion ROM Base Address */
1645-#define PCI_CAP_PTR 0x34 /* 8 bit Capabilities Ptr */
1646- /* Byte 0x35..0x3b: reserved */
1647+#define PCI_CAP_PTR 0x34 /* 8 bit Capabilities Pointer */
1648+ /* Bytes 0x35..0x3b: reserved */
1649 #define PCI_IRQ_LINE 0x3c /* 8 bit Interrupt Line */
1650 #define PCI_IRQ_PIN 0x3d /* 8 bit Interrupt Pin */
1651 #define PCI_MIN_GNT 0x3e /* 8 bit Min_Gnt */
1652 #define PCI_MAX_LAT 0x3f /* 8 bit Max_Lat */
1653 /* Device Dependent Region */
1654-#define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */
1655-#define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */
1656+#define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */
1657+#define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */
1658 /* Power Management Region */
1659-#define PCI_PM_CAP_ID 0x48 /* 8 bit Power Management Cap. ID */
1660-#define PCI_PM_NITEM 0x49 /* 8 bit Next Item Ptr */
1661-#define PCI_PM_CAP_REG 0x4a /* 16 bit Power Management Capabilities */
1662-#define PCI_PM_CTL_STS 0x4c /* 16 bit Power Manag. Control/Status */
1663+#define PCI_PM_CAP_ID 0x48 /* 8 bit Power Management Cap. ID */
1664+#define PCI_PM_NITEM 0x49 /* 8 bit PM Next Item Pointer */
1665+#define PCI_PM_CAP_REG 0x4a /* 16 bit Power Management Capabilities */
1666+#define PCI_PM_CTL_STS 0x4c /* 16 bit Power Manag. Control/Status */
1667 /* Byte 0x4e: reserved */
1668-#define PCI_PM_DAT_REG 0x4f /* 8 bit Power Manag. Data Register */
1669+#define PCI_PM_DAT_REG 0x4f /* 8 bit Power Manag. Data Register */
1670 /* VPD Region */
1671-#define PCI_VPD_CAP_ID 0x50 /* 8 bit VPD Cap. ID */
1672-#define PCI_VPD_NITEM 0x51 /* 8 bit Next Item Ptr */
1673-#define PCI_VPD_ADR_REG 0x52 /* 16 bit VPD Address Register */
1674-#define PCI_VPD_DAT_REG 0x54 /* 32 bit VPD Data Register */
1675- /* Byte 0x58..0x59: reserved */
1676-#define PCI_SER_LD_CTRL 0x5a /* 16 bit SEEPROM Loader Ctrl (YUKON only) */
1677- /* Byte 0x5c..0xff: reserved */
1678+#define PCI_VPD_CAP_ID 0x50 /* 8 bit VPD Cap. ID */
1679+#define PCI_VPD_NITEM 0x51 /* 8 bit VPD Next Item Pointer */
1680+#define PCI_VPD_ADR_REG 0x52 /* 16 bit VPD Address Register */
1681+#define PCI_VPD_DAT_REG 0x54 /* 32 bit VPD Data Register */
1682+ /* Bytes 0x58..0x59: reserved */
1683+#define PCI_SER_LD_CTRL 0x5a /* 16 bit SEEPROM Loader Ctrl (YUKON only) */
1684+ /* Bytes 0x5c..0xfc: used by Yukon-2 */
1685+#define PCI_MSI_CAP_ID 0x5c /* 8 bit MSI Capability ID Register */
1686+#define PCI_MSI_NITEM 0x5d /* 8 bit MSI Next Item Pointer */
1687+#define PCI_MSI_CTRL 0x5e /* 16 bit MSI Message Control */
1688+#define PCI_MSI_ADR_LO 0x60 /* 32 bit MSI Message Address (Lower) */
1689+#define PCI_MSI_ADR_HI 0x64 /* 32 bit MSI Message Address (Upper) */
1690+#define PCI_MSI_DATA 0x68 /* 16 bit MSI Message Data */
1691+ /* Bytes 0x6a..0x6b: reserved */
1692+#define PCI_X_CAP_ID 0x6c /* 8 bit PCI-X Capability ID Register */
1693+#define PCI_X_NITEM 0x6d /* 8 bit PCI-X Next Item Pointer */
1694+#define PCI_X_COMMAND 0x6e /* 16 bit PCI-X Command */
1695+#define PCI_X_PE_STAT 0x70 /* 32 bit PCI-X / PE Status */
1696+#define PCI_CAL_CTRL 0x74 /* 16 bit PCI Calibration Control Register */
1697+#define PCI_CAL_STAT 0x76 /* 16 bit PCI Calibration Status Register */
1698+#define PCI_DISC_CNT 0x78 /* 16 bit PCI Discard Counter */
1699+#define PCI_RETRY_CNT 0x7a /* 8 bit PCI Retry Counter */
1700+ /* Byte 0x7b: reserved */
1701+#define PCI_OUR_STATUS 0x7c /* 32 bit Adapter Status Register */
1702+#define PCI_OUR_REG_3 0x80 /* 32 bit Our Register 3 (Yukon-ECU only) */
1703+#define PCI_OUR_REG_4 0x84 /* 32 bit Our Register 4 (Yukon-ECU only) */
1704+#define PCI_OUR_REG_5 0x88 /* 32 bit Our Register 5 (Yukon-ECU only) */
1705+ /* Bytes 0x8c..0xdf: reserved */
1706+
1707+/* PCI Express Capability */
1708+#define PEX_CAP_ID 0xe0 /* 8 bit PEX Capability ID */
1709+#define PEX_NITEM 0xe1 /* 8 bit PEX Next Item Pointer */
1710+#define PEX_CAP_REG 0xe2 /* 16 bit PEX Capability Register */
1711+#define PEX_DEV_CAP 0xe4 /* 32 bit PEX Device Capabilities */
1712+#define PEX_DEV_CTRL 0xe8 /* 16 bit PEX Device Control */
1713+#define PEX_DEV_STAT 0xea /* 16 bit PEX Device Status */
1714+#define PEX_LNK_CAP 0xec /* 32 bit PEX Link Capabilities */
1715+#define PEX_LNK_CTRL 0xf0 /* 16 bit PEX Link Control */
1716+#define PEX_LNK_STAT 0xf2 /* 16 bit PEX Link Status */
1717+ /* Bytes 0xf4..0xff: reserved */
1718+
1719+/* PCI Express Extended Capabilities */
1720+#define PEX_ADV_ERR_REP 0x100 /* 32 bit PEX Advanced Error Reporting */
1721+#define PEX_UNC_ERR_STAT 0x104 /* 32 bit PEX Uncorr. Errors Status */
1722+#define PEX_UNC_ERR_MASK 0x108 /* 32 bit PEX Uncorr. Errors Mask */
1723+#define PEX_UNC_ERR_SEV 0x10c /* 32 bit PEX Uncorr. Errors Severity */
1724+#define PEX_COR_ERR_STAT 0x110 /* 32 bit PEX Correc. Errors Status */
1725+#define PEX_COR_ERR_MASK 0x114 /* 32 bit PEX Correc. Errors Mask */
1726+#define PEX_ADV_ERR_CAP_C 0x118 /* 32 bit PEX Advanced Error Cap./Ctrl */
1727+#define PEX_HEADER_LOG 0x11c /* 4x32 bit PEX Header Log Register */
1728+
1729+/* PCI Express Ack Timer for 1x Link */
1730+#define PEX_ACK_LAT_TOX1 0x228 /* 16 bit PEX Ack Latency Timeout x1 */
1731+#define PEX_ACK_RPLY_TOX1 0x22a /* 16 bit PEX Ack Reply Timeout val x1 */
1732
1733 /*
1734 * I2C Address (PCI Config)
1735@@ -180,13 +238,13 @@
1736 #define PCI_ADSTEP BIT_7S /* Address Stepping */
1737 #define PCI_PERREN BIT_6S /* Parity Report Response enable */
1738 #define PCI_VGA_SNOOP BIT_5S /* VGA palette snoop */
1739-#define PCI_MWIEN BIT_4S /* Memory write an inv cycl ena */
1740+#define PCI_MWIEN BIT_4S /* Memory write an inv cycl enable */
1741 #define PCI_SCYCEN BIT_3S /* Special Cycle enable */
1742 #define PCI_BMEN BIT_2S /* Bus Master enable */
1743 #define PCI_MEMEN BIT_1S /* Memory Space Access enable */
1744 #define PCI_IOEN BIT_0S /* I/O Space Access enable */
1745
1746-#define PCI_COMMAND_VAL (PCI_FBTEN | PCI_SERREN | PCI_PERREN | PCI_MWIEN |\
1747+#define PCI_COMMAND_VAL (PCI_INT_DIS | PCI_SERREN | PCI_PERREN | \
1748 PCI_BMEN | PCI_MEMEN | PCI_IOEN)
1749
1750 /* PCI_STATUS 16 bit Status */
1751@@ -220,7 +278,7 @@
1752
1753 /* PCI_HEADER_T 8 bit Header Type */
1754 #define PCI_HD_MF_DEV BIT_7S /* 0= single, 1= multi-func dev */
1755-#define PCI_HD_TYPE 0x7f /* Bit 6..0: Header Layout 0= normal */
1756+#define PCI_HD_TYPE 0x7f /* Bit 6..0: Header Layout (0=normal) */
1757
1758 /* PCI_BIST 8 bit Built-in selftest */
1759 /* Built-in Self test not supported (optional) */
1760@@ -229,33 +287,42 @@
1761 #define PCI_MEMSIZE 0x4000L /* use 16 kB Memory Base */
1762 #define PCI_MEMBASE_MSK 0xffffc000L /* Bit 31..14: Memory Base Address */
1763 #define PCI_MEMSIZE_MSK 0x00003ff0L /* Bit 13.. 4: Memory Size Req. */
1764-#define PCI_PREFEN BIT_3 /* Prefetchable */
1765-#define PCI_MEM_TYP (3L<<2) /* Bit 2.. 1: Memory Type */
1766+#define PCI_PREFEN BIT_3 /* Prefetch enable */
1767+#define PCI_MEM_TYP_MSK (3L<<1) /* Bit 2.. 1: Memory Type Mask */
1768+#define PCI_MEMSPACE BIT_0 /* Memory Space Indicator */
1769+
1770 #define PCI_MEM32BIT (0L<<1) /* Base addr anywhere in 32 Bit range */
1771 #define PCI_MEM1M (1L<<1) /* Base addr below 1 MegaByte */
1772 #define PCI_MEM64BIT (2L<<1) /* Base addr anywhere in 64 Bit range */
1773-#define PCI_MEMSPACE BIT_0 /* Memory Space Indicator */
1774
1775 /* PCI_BASE_2ND 32 bit 2nd Base address */
1776 #define PCI_IOBASE 0xffffff00L /* Bit 31.. 8: I/O Base address */
1777 #define PCI_IOSIZE 0x000000fcL /* Bit 7.. 2: I/O Size Requirements */
1778- /* Bit 1: reserved */
1779+ /* Bit 1: reserved */
1780 #define PCI_IOSPACE BIT_0 /* I/O Space Indicator */
1781
1782 /* PCI_BASE_ROM 32 bit Expansion ROM Base Address */
1783 #define PCI_ROMBASE_MSK 0xfffe0000L /* Bit 31..17: ROM Base address */
1784 #define PCI_ROMBASE_SIZ (0x1cL<<14) /* Bit 16..14: Treat as Base or Size */
1785 #define PCI_ROMSIZE (0x38L<<11) /* Bit 13..11: ROM Size Requirements */
1786- /* Bit 10.. 1: reserved */
1787+ /* Bit 10.. 1: reserved */
1788 #define PCI_ROMEN BIT_0 /* Address Decode enable */
1789
1790 /* Device Dependent Region */
1791 /* PCI_OUR_REG_1 32 bit Our Register 1 */
1792- /* Bit 31..29: reserved */
1793+ /* Bit 31..29: reserved */
1794 #define PCI_PHY_COMA BIT_28 /* Set PHY to Coma Mode (YUKON only) */
1795 #define PCI_TEST_CAL BIT_27 /* Test PCI buffer calib. (YUKON only) */
1796 #define PCI_EN_CAL BIT_26 /* Enable PCI buffer calib. (YUKON only) */
1797 #define PCI_VIO BIT_25 /* PCI I/O Voltage, 0 = 3.3V, 1 = 5V */
1798+/* Yukon-2 */
1799+#define PCI_Y2_PIG_ENA BIT_31 /* Enable Plug-in-Go (YUKON-2) */
1800+#define PCI_Y2_DLL_DIS BIT_30 /* Disable PCI DLL (YUKON-2) */
1801+#define PCI_Y2_PHY2_COMA BIT_29 /* Set PHY 2 to Coma Mode (YUKON-2) */
1802+#define PCI_Y2_PHY1_COMA BIT_28 /* Set PHY 1 to Coma Mode (YUKON-2) */
1803+#define PCI_Y2_PHY2_POWD BIT_27 /* Set PHY 2 to Power Down (YUKON-2) */
1804+#define PCI_Y2_PHY1_POWD BIT_26 /* Set PHY 1 to Power Down (YUKON-2) */
1805+ /* Bit 25: reserved */
1806 #define PCI_DIS_BOOT BIT_24 /* Disable BOOT via ROM */
1807 #define PCI_EN_IO BIT_23 /* Mapping to I/O space */
1808 #define PCI_EN_FPROM BIT_22 /* Enable FLASH mapping to memory */
1809@@ -266,9 +333,10 @@
1810 #define PCI_PAGE_32K (1L<<20) /* 32 k pages */
1811 #define PCI_PAGE_64K (2L<<20) /* 64 k pages */
1812 #define PCI_PAGE_128K (3L<<20) /* 128 k pages */
1813- /* Bit 19: reserved */
1814-#define PCI_PAGEREG (7L<<16) /* Bit 18..16: Page Register */
1815+ /* Bit 19: reserved */
1816+#define PCI_PAGEREG (7L<<16) /* Bit 18..16: Page Register */
1817 #define PCI_NOTAR BIT_15 /* No turnaround cycle */
1818+#define PCI_PEX_LEGNAT BIT_15 /* PEX PM legacy/native mode (YUKON-2) */
1819 #define PCI_FORCE_BE BIT_14 /* Assert all BEs on MR */
1820 #define PCI_DIS_MRL BIT_13 /* Disable Mem Read Line */
1821 #define PCI_DIS_MRM BIT_12 /* Disable Mem Read Multiple */
1822@@ -278,13 +346,21 @@
1823 #define PCI_DIS_PCI_CLK BIT_8 /* Disable PCI clock driving */
1824 #define PCI_SKEW_DAS (0xfL<<4) /* Bit 7.. 4: Skew Ctrl, DAS Ext */
1825 #define PCI_SKEW_BASE 0xfL /* Bit 3.. 0: Skew Ctrl, Base */
1826+#define PCI_CLS_OPT BIT_3 /* Cache Line Size opt. PCI-X (YUKON-2) */
1827
1828+/* Yukon-EC Ultra only */
1829+ /* Bit 14..10: reserved */
1830+#define PCI_PHY_LNK_TIM_MSK (3L<<8) /* Bit 9.. 8: GPHY Link Trigger Timer */
1831+#define PCI_ENA_L1_EVENT BIT_7 /* Enable PEX L1 Event */
1832+#define PCI_ENA_GPHY_LNK BIT_6 /* Enable PEX L1 on GPHY Link down */
1833+#define PCI_FORCE_PEX_L1 BIT_5 /* Force to PEX L1 */
1834+ /* Bit 4.. 0: reserved */
1835
1836 /* PCI_OUR_REG_2 32 bit Our Register 2 */
1837 #define PCI_VPD_WR_THR (0xffL<<24) /* Bit 31..24: VPD Write Threshold */
1838 #define PCI_DEV_SEL (0x7fL<<17) /* Bit 23..17: EEPROM Device Select */
1839 #define PCI_VPD_ROM_SZ (7L<<14) /* Bit 16..14: VPD ROM Size */
1840- /* Bit 13..12: reserved */
1841+ /* Bit 13..12: reserved */
1842 #define PCI_PATCH_DIR (0xfL<<8) /* Bit 11.. 8: Ext Patches dir 3..0 */
1843 #define PCI_PATCH_DIR_3 BIT_11
1844 #define PCI_PATCH_DIR_2 BIT_10
1845@@ -296,22 +372,21 @@
1846 #define PCI_EXT_PATCH_1 BIT_5
1847 #define PCI_EXT_PATCH_0 BIT_4
1848 #define PCI_EN_DUMMY_RD BIT_3 /* Enable Dummy Read */
1849-#define PCI_REV_DESC BIT_2 /* Reverse Desc. Bytes */
1850- /* Bit 1: reserved */
1851+#define PCI_REV_DESC BIT_2 /* Reverse Descriptor Bytes */
1852+ /* Bit 1: reserved */
1853 #define PCI_USEDATA64 BIT_0 /* Use 64Bit Data bus ext */
1854
1855-
1856-/* Power Management Region */
1857+/* Power Management (PM) Region */
1858 /* PCI_PM_CAP_REG 16 bit Power Management Capabilities */
1859-#define PCI_PME_SUP_MSK (0x1f<<11) /* Bit 15..11: PM Event Support Mask */
1860-#define PCI_PME_D3C_SUP BIT_15S /* PME from D3cold Support (if Vaux) */
1861+#define PCI_PME_SUP_MSK (0x1f<<11) /* Bit 15..11: PM Event (PME) Supp. Mask */
1862+#define PCI_PME_D3C_SUP BIT_15S /* PME from D3cold Support (if VAUX) */
1863 #define PCI_PME_D3H_SUP BIT_14S /* PME from D3hot Support */
1864 #define PCI_PME_D2_SUP BIT_13S /* PME from D2 Support */
1865 #define PCI_PME_D1_SUP BIT_12S /* PME from D1 Support */
1866 #define PCI_PME_D0_SUP BIT_11S /* PME from D0 Support */
1867 #define PCI_PM_D2_SUP BIT_10S /* D2 Support in 33 MHz mode */
1868 #define PCI_PM_D1_SUP BIT_9S /* D1 Support */
1869- /* Bit 8.. 6: reserved */
1870+ /* Bit 8.. 6: reserved */
1871 #define PCI_PM_DSI BIT_5S /* Device Specific Initialization */
1872 #define PCI_PM_APS BIT_4S /* Auxialiary Power Source */
1873 #define PCI_PME_CLOCK BIT_3S /* PM Event Clock */
1874@@ -322,7 +397,7 @@
1875 #define PCI_PM_DAT_SCL (3<<13) /* Bit 14..13: Data Reg. scaling factor */
1876 #define PCI_PM_DAT_SEL (0xf<<9) /* Bit 12.. 9: PM data selector field */
1877 #define PCI_PME_EN BIT_8S /* Enable PME# generation (YUKON only) */
1878- /* Bit 7.. 2: reserved */
1879+ /* Bit 7.. 2: reserved */
1880 #define PCI_PM_STATE_MSK 3 /* Bit 1.. 0: Power Management State */
1881
1882 #define PCI_PM_STATE_D0 0 /* D0: Operational (default) */
1883@@ -333,7 +408,144 @@
1884 /* VPD Region */
1885 /* PCI_VPD_ADR_REG 16 bit VPD Address Register */
1886 #define PCI_VPD_FLAG BIT_15S /* starts VPD rd/wr cycle */
1887-#define PCI_VPD_ADR_MSK 0x7fffL /* Bit 14.. 0: VPD address mask */
1888+#define PCI_VPD_ADR_MSK 0x7fffL /* Bit 14.. 0: VPD Address Mask */
1889+
1890+/* PCI_OUR_STATUS 32 bit Adapter Status Register (Yukon-2) */
1891+#define PCI_OS_PCI64B BIT_31 /* Conventional PCI 64 bits Bus */
1892+#define PCI_OS_PCIX BIT_30 /* PCI-X Bus */
1893+#define PCI_OS_MODE_MSK (3L<<28) /* Bit 29..28: PCI-X Bus Mode Mask */
1894+#define PCI_OS_PCI66M BIT_27 /* PCI 66 MHz Bus */
1895+#define PCI_OS_PCI_X BIT_26 /* PCI/PCI-X Bus (0 = PEX) */
1896+#define PCI_OS_DLLE_MSK (3L<<24) /* Bit 25..24: DLL Status Indication */
1897+#define PCI_OS_DLLR_MSK (0xfL<<20) /* Bit 23..20: DLL Row Counters Values */
1898+#define PCI_OS_DLLC_MSK (0xfL<<16) /* Bit 19..16: DLL Col. Counters Values */
1899+ /* Bit 15.. 8: reserved */
1900+
1901+#define PCI_OS_SPEED(val) ((val & PCI_OS_MODE_MSK) >> 28) /* PCI-X Speed */
1902+/* possible values for the speed field of the register */
1903+#define PCI_OS_SPD_PCI 0 /* PCI Conventional Bus */
1904+#define PCI_OS_SPD_X66 1 /* PCI-X 66MHz Bus */
1905+#define PCI_OS_SPD_X100 2 /* PCI-X 100MHz Bus */
1906+#define PCI_OS_SPD_X133 3 /* PCI-X 133MHz Bus */
1907+
1908+/* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */
1909+ /* Bit 31..18: reserved */
1910+#define P_CLK_COR_REGS_D0_DIS BIT_17 /* Disable Clock Core Regs in D0 */
1911+#define P_CLK_PCI_REGS_D0_DIS BIT_16 /* Disable Clock PCI Regs in D0 */
1912+#define P_CLK_COR_YTB_ARB_DIS BIT_15 /* Disable Clock YTB Arbiter */
1913+#define P_CLK_MAC_LNK1_D3_DIS BIT_14 /* Disable Clock MAC Link1 in D3 */
1914+#define P_CLK_COR_LNK1_D0_DIS BIT_13 /* Disable Clock Core Link1 in D0 */
1915+#define P_CLK_MAC_LNK1_D0_DIS BIT_12 /* Disable Clock MAC Link1 in D0 */
1916+#define P_CLK_COR_LNK1_D3_DIS BIT_11 /* Disable Clock Core Link1 in D3 */
1917+#define P_CLK_PCI_MST_ARB_DIS BIT_10 /* Disable Clock PCI Master Arb. */
1918+#define P_CLK_COR_REGS_D3_DIS BIT_9 /* Disable Clock Core Regs in D3 */
1919+#define P_CLK_PCI_REGS_D3_DIS BIT_8 /* Disable Clock PCI Regs in D3 */
1920+#define P_CLK_REF_LNK1_GM_DIS BIT_7 /* Disable Clock Ref. Link1 GMAC */
1921+#define P_CLK_COR_LNK1_GM_DIS BIT_6 /* Disable Clock Core Link1 GMAC */
1922+#define P_CLK_PCI_COMMON_DIS BIT_5 /* Disable Clock PCI Common */
1923+#define P_CLK_COR_COMMON_DIS BIT_4 /* Disable Clock Core Common */
1924+#define P_CLK_PCI_LNK1_BMU_DIS BIT_3 /* Disable Clock PCI Link1 BMU */
1925+#define P_CLK_COR_LNK1_BMU_DIS BIT_2 /* Disable Clock Core Link1 BMU */
1926+#define P_CLK_PCI_LNK1_BIU_DIS BIT_1 /* Disable Clock PCI Link1 BIU */
1927+#define P_CLK_COR_LNK1_BIU_DIS BIT_0 /* Disable Clock Core Link1 BIU */
1928+
1929+/* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
1930+#define P_PEX_LTSSM_STAT_MSK (0x7fL<<25) /* Bit 31..25: PEX LTSSM Mask */
1931+ /* (Link Training & Status State Machine) */
1932+ /* Bit 24: reserved */
1933+#define P_TIMER_VALUE_MSK (0xffL<<16) /* Bit 23..16: Timer Value Mask */
1934+#define P_FORCE_ASPM_REQUEST BIT_15 /* Force ASPM Request (A1 only) */
1935+ /* (Active State Power Management) */
1936+ /* Bit 14..12: Force ASPM on Event */
1937+#define P_ASPM_GPHY_LINK_DOWN BIT_14 /* GPHY Link Down (A1 only) */
1938+#define P_ASPM_INT_FIFO_EMPTY BIT_13 /* Internal FIFO Empty (A1 only) */
1939+#define P_ASPM_CLKRUN_REQUEST BIT_12 /* CLKRUN Request (A1 only) */
1940+ /* Bit 11.. 4: reserved */
1941+#define P_ASPM_FORCE_CLKREQ_ENA BIT_4 /* Force CLKREQ Enable (A1b only) */
1942+#define P_ASPM_CLKREQ_PAD_CTL BIT_3 /* CLKREQ PAD Control (A1 only) */
1943+#define P_ASPM_A1_MODE_SELECT BIT_2 /* A1 Mode Select (A1 only) */
1944+#define P_CLK_GATE_PEX_UNIT_ENA BIT_1 /* Enable Gate PEX Unit Clock */
1945+#define P_CLK_GATE_ROOT_COR_ENA BIT_0 /* Enable Gate Root Core Clock */
1946+
1947+#define P_PEX_LTSSM_STAT(x) (SHIFT25(x) & P_PEX_LTSSM_STAT_MSK)
1948+#define P_PEX_LTSSM_L1_STAT 0x34
1949+#define P_PEX_LTSSM_DET_STAT 0x01
1950+
1951+#define P_ASPM_CONTROL_MSK (P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN | \
1952+ P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY)
1953+
1954+/* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */
1955+ /* Bit 31..27: reserved */
1956+ /* Bit 26..16: Release Clock on Event */
1957+#define P_REL_PCIE_RST_DE_ASS BIT_26 /* PCIe Reset De-Asserted */
1958+#define P_REL_GPHY_REC_PACKET BIT_25 /* GPHY Received Packet */
1959+#define P_REL_INT_FIFO_N_EMPTY BIT_24 /* Internal FIFO Not Empty */
1960+#define P_REL_MAIN_PWR_AVAIL BIT_23 /* Main Power Available */
1961+#define P_REL_CLKRUN_REQ_REL BIT_22 /* CLKRUN Request Release */
1962+#define P_REL_PCIE_RESET_ASS BIT_21 /* PCIe Reset Asserted */
1963+#define P_REL_PME_ASSERTED BIT_20 /* PME Asserted */
1964+#define P_REL_PCIE_EXIT_L1_ST BIT_19 /* PCIe Exit L1 State */
1965+#define P_REL_LOADER_NOT_FIN BIT_18 /* EPROM Loader Not Finished */
1966+#define P_REL_PCIE_RX_EX_IDLE BIT_17 /* PCIe Rx Exit Electrical Idle State */
1967+#define P_REL_GPHY_LINK_UP BIT_16 /* GPHY Link Up */
1968+ /* Bit 15..11: reserved */
1969+ /* Bit 10.. 0: Mask for Gate Clock */
1970+#define P_GAT_PCIE_RST_DE_ASS BIT_10 /* PCIe Reset De-Asserted */
1971+#define P_GAT_GPHY_N_REC_PACKET BIT_9 /* GPHY Not Received Packet */
1972+#define P_GAT_INT_FIFO_EMPTY BIT_8 /* Internal FIFO Empty */
1973+#define P_GAT_MAIN_PWR_N_AVAIL BIT_7 /* Main Power Not Available */
1974+#define P_GAT_CLKRUN_REQ_REL BIT_6 /* CLKRUN Not Requested */
1975+#define P_GAT_PCIE_RESET_ASS BIT_5 /* PCIe Reset Asserted */
1976+#define P_GAT_PME_DE_ASSERTED BIT_4 /* PME De-Asserted */
1977+#define P_GAT_PCIE_ENTER_L1_ST BIT_3 /* PCIe Enter L1 State */
1978+#define P_GAT_LOADER_FINISHED BIT_2 /* EPROM Loader Finished */
1979+#define P_GAT_PCIE_RX_EL_IDLE BIT_1 /* PCIe Rx Electrical Idle State */
1980+#define P_GAT_GPHY_LINK_DOWN BIT_0 /* GPHY Link Down */
1981+
1982+/* PEX_DEV_CTRL 16 bit PEX Device Control (Yukon-2) */
1983+ /* Bit 15 reserved */
1984+#define PEX_DC_MAX_RRS_MSK (7<<12) /* Bit 14..12: Max. Read Request Size */
1985+#define PEX_DC_EN_NO_SNOOP BIT_11S /* Enable No Snoop */
1986+#define PEX_DC_EN_AUX_POW BIT_10S /* Enable AUX Power */
1987+#define PEX_DC_EN_PHANTOM BIT_9S /* Enable Phantom Functions */
1988+#define PEX_DC_EN_EXT_TAG BIT_8S /* Enable Extended Tag Field */
1989+#define PEX_DC_MAX_PLS_MSK (7<<5) /* Bit 7.. 5: Max. Payload Size Mask */
1990+#define PEX_DC_EN_REL_ORD BIT_4S /* Enable Relaxed Ordering */
1991+#define PEX_DC_EN_UNS_RQ_RP BIT_3S /* Enable Unsupported Request Reporting */
1992+#define PEX_DC_EN_FAT_ER_RP BIT_2S /* Enable Fatal Error Reporting */
1993+#define PEX_DC_EN_NFA_ER_RP BIT_1S /* Enable Non-Fatal Error Reporting */
1994+#define PEX_DC_EN_COR_ER_RP BIT_0S /* Enable Correctable Error Reporting */
1995+
1996+#define PEX_DC_MAX_RD_RQ_SIZE(x) (SHIFT12(x) & PEX_DC_MAX_RRS_MSK)
1997+
1998+/* PEX_LNK_CTRL 16 bit PEX Link Control (Yukon-2) */
1999+#define PEX_LC_CLK_PM_ENA BIT_8S /* Enable Clock Power Management (CLKREQ) */
2000+
2001+/* PEX_LNK_STAT 16 bit PEX Link Status (Yukon-2) */
2002+ /* Bit 15..13 reserved */
2003+#define PEX_LS_SLOT_CLK_CFG BIT_12S /* Slot Clock Config */
2004+#define PEX_LS_LINK_TRAIN BIT_11S /* Link Training */
2005+#define PEX_LS_TRAIN_ERROR BIT_10S /* Training Error */
2006+#define PEX_LS_LINK_WI_MSK (0x3f<<4) /* Bit 9.. 4: Neg. Link Width Mask */
2007+#define PEX_LS_LINK_SP_MSK 0x0f /* Bit 3.. 0: Link Speed Mask */
2008+
2009+/* PEX_UNC_ERR_STAT 16 bit PEX Uncorrectable Errors Status (Yukon-2) */
2010+ /* Bit 31..21 reserved */
2011+#define PEX_UNSUP_REQ BIT_20 /* Unsupported Request Error */
2012+ /* ECRC Error (not supported) */
2013+#define PEX_MALFOR_TLP BIT_18 /* Malformed TLP */
2014+ /* Receiver Overflow (not supported) */
2015+#define PEX_UNEXP_COMP BIT_16 /* Unexpected Completion */
2016+ /* Completer Abort (not supported) */
2017+#define PEX_COMP_TO BIT_14 /* Completion Timeout */
2018+#define PEX_FLOW_CTRL_P BIT_13 /* Flow Control Protocol Error */
2019+#define PEX_POIS_TLP BIT_12 /* Poisoned TLP */
2020+ /* Bit 11.. 5: reserved */
2021+#define PEX_DATA_LINK_P BIT_4 /* Data Link Protocol Error */
2022+ /* Bit 3.. 1: reserved */
2023+ /* Training Error (not supported) */
2024+
2025+#define PEX_FATAL_ERRORS (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P)
2026
2027 /* Control Register File (Address Map) */
2028
2029@@ -349,8 +561,14 @@
2030 #define B0_IMSK 0x000c /* 32 bit Interrupt Mask Register */
2031 #define B0_HWE_ISRC 0x0010 /* 32 bit HW Error Interrupt Src Reg */
2032 #define B0_HWE_IMSK 0x0014 /* 32 bit HW Error Interrupt Mask Reg */
2033-#define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg */
2034- /* 0x001c: reserved */
2035+#define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg 1 */
2036+
2037+/* Special ISR registers (Yukon-2 only) */
2038+#define B0_Y2_SP_ISRC2 0x001c /* 32 bit Special Interrupt Source Reg 2 */
2039+#define B0_Y2_SP_ISRC3 0x0020 /* 32 bit Special Interrupt Source Reg 3 */
2040+#define B0_Y2_SP_EISR 0x0024 /* 32 bit Enter ISR Reg */
2041+#define B0_Y2_SP_LISR 0x0028 /* 32 bit Leave ISR Reg */
2042+#define B0_Y2_SP_ICR 0x002c /* 32 bit Interrupt Control Reg */
2043
2044 /* B0 XMAC 1 registers (GENESIS only) */
2045 #define B0_XM1_IMSK 0x0020 /* 16 bit r/w XMAC 1 Interrupt Mask Register*/
2046@@ -372,7 +590,7 @@
2047 #define B0_XM2_PHY_DATA 0x0054 /* 16 bit r/w XMAC 2 PHY Data Register */
2048 /* 0x0056 - 0x005f: reserved */
2049
2050-/* BMU Control Status Registers */
2051+/* BMU Control Status Registers (Yukon and Genesis) */
2052 #define B0_R1_CSR 0x0060 /* 32 bit BMU Ctrl/Stat Rx Queue 1 */
2053 #define B0_R2_CSR 0x0064 /* 32 bit BMU Ctrl/Stat Rx Queue 2 */
2054 #define B0_XS1_CSR 0x0068 /* 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
2055@@ -390,7 +608,7 @@
2056 /*
2057 * Bank 2
2058 */
2059-/* NA reg = 48 bit Network Address Register, 3x16 or 8x8 bit readable */
2060+/* NA reg = 48 bit Network Address Register, 3x16 or 6x8 bit readable */
2061 #define B2_MAC_1 0x0100 /* NA reg MAC Address 1 */
2062 /* 0x0106 - 0x0107: reserved */
2063 #define B2_MAC_2 0x0108 /* NA reg MAC Address 2 */
2064@@ -400,14 +618,23 @@
2065 #define B2_CONN_TYP 0x0118 /* 8 bit Connector type */
2066 #define B2_PMD_TYP 0x0119 /* 8 bit PMD type */
2067 #define B2_MAC_CFG 0x011a /* 8 bit MAC Configuration / Chip Revision */
2068-#define B2_CHIP_ID 0x011b /* 8 bit Chip Identification Number */
2069- /* Eprom registers are currently of no use */
2070+#define B2_CHIP_ID 0x011b /* 8 bit Chip Identification Number */
2071+ /* Eprom registers */
2072 #define B2_E_0 0x011c /* 8 bit EPROM Byte 0 (ext. SRAM size */
2073+/* Yukon and Genesis */
2074 #define B2_E_1 0x011d /* 8 bit EPROM Byte 1 (PHY type) */
2075 #define B2_E_2 0x011e /* 8 bit EPROM Byte 2 */
2076+/* Yukon-2 */
2077+#define B2_Y2_CLK_GATE 0x011d /* 8 bit Clock Gating (Yukon-2) */
2078+#define B2_Y2_HW_RES 0x011e /* 8 bit HW Resources (Yukon-2) */
2079+
2080 #define B2_E_3 0x011f /* 8 bit EPROM Byte 3 */
2081+
2082+/* Yukon and Genesis */
2083 #define B2_FAR 0x0120 /* 32 bit Flash-Prom Addr Reg/Cnt */
2084 #define B2_FDP 0x0124 /* 8 bit Flash-Prom Data Port */
2085+/* Yukon-2 */
2086+#define B2_Y2_CLK_CTRL 0x0120 /* 32 bit Core Clock Frequency Control */
2087 /* 0x0125 - 0x0127: reserved */
2088 #define B2_LD_CTRL 0x0128 /* 8 bit EPROM loader control register */
2089 #define B2_LD_TEST 0x0129 /* 8 bit EPROM loader test register */
2090@@ -439,6 +666,10 @@
2091 #define B2_BSC_CTRL 0x0178 /* 8 bit Blink Source Counter Control */
2092 #define B2_BSC_STAT 0x0179 /* 8 bit Blink Source Counter Status */
2093 #define B2_BSC_TST 0x017a /* 16 bit Blink Source Counter Test Reg */
2094+
2095+/* Yukon-2 */
2096+#define Y2_PEX_PHY_DATA 0x0170 /* 16 bit PEX PHY Data Register */
2097+#define Y2_PEX_PHY_ADDR 0x0172 /* 16 bit PEX PHY Address Register */
2098 /* 0x017c - 0x017f: reserved */
2099
2100 /*
2101@@ -448,9 +679,14 @@
2102 #define B3_RAM_ADDR 0x0180 /* 32 bit RAM Address, to read or write */
2103 #define B3_RAM_DATA_LO 0x0184 /* 32 bit RAM Data Word (low dWord) */
2104 #define B3_RAM_DATA_HI 0x0188 /* 32 bit RAM Data Word (high dWord) */
2105+#define B3_RAM_PARITY 0x018c /* 8 bit RAM Parity (Yukon-ECU A1) */
2106+
2107+#define SELECT_RAM_BUFFER(rb, addr) (addr | (rb << 6)) /* Yukon-2 only */
2108+
2109 /* 0x018c - 0x018f: reserved */
2110
2111 /* RAM Interface Registers */
2112+/* Yukon-2: use SELECT_RAM_BUFFER() to access the RAM buffer */
2113 /*
2114 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
2115 * not usable in SW. Please notice these are NOT real timeouts, these are
2116@@ -517,8 +753,8 @@
2117 /* 0x01ea - 0x01eb: reserved */
2118 #define B3_PA_TOVAL_TX2 0x01ec /* 16 bit Timeout Val Tx Path MAC 2 */
2119 /* 0x01ee - 0x01ef: reserved */
2120-#define B3_PA_CTRL 0x01f0 /* 16 bit Packet Arbiter Ctrl Register */
2121-#define B3_PA_TEST 0x01f2 /* 16 bit Packet Arbiter Test Register */
2122+#define B3_PA_CTRL 0x01f0 /* 16 bit Packet Arbiter Ctrl Register */
2123+#define B3_PA_TEST 0x01f2 /* 16 bit Packet Arbiter Test Register */
2124 /* 0x01f4 - 0x01ff: reserved */
2125
2126 /*
2127@@ -532,7 +768,16 @@
2128 #define TXA_CTRL 0x0210 /* 8 bit Tx Arbiter Control Register */
2129 #define TXA_TEST 0x0211 /* 8 bit Tx Arbiter Test Register */
2130 #define TXA_STAT 0x0212 /* 8 bit Tx Arbiter Status Register */
2131- /* 0x0213 - 0x027f: reserved */
2132+ /* 0x0213 - 0x021f: reserved */
2133+
2134+ /* RSS key registers for Yukon-2 Family */
2135+#define B4_RSS_KEY 0x0220 /* 4x32 bit RSS Key register (Yukon-2) */
2136+ /* RSS key register offsets */
2137+#define KEY_IDX_0 0 /* offset for location of KEY 0 */
2138+#define KEY_IDX_1 4 /* offset for location of KEY 1 */
2139+#define KEY_IDX_2 8 /* offset for location of KEY 2 */
2140+#define KEY_IDX_3 12 /* offset for location of KEY 3 */
2141+
2142 /* 0x0280 - 0x0292: MAC 2 */
2143 /* 0x0213 - 0x027f: reserved */
2144
2145@@ -556,10 +801,10 @@
2146
2147 /* Queue Register Offsets, use Q_ADDR() to access */
2148 #define Q_D 0x00 /* 8*32 bit Current Descriptor */
2149-#define Q_DA_L 0x20 /* 32 bit Current Descriptor Address Low dWord */
2150-#define Q_DA_H 0x24 /* 32 bit Current Descriptor Address High dWord */
2151-#define Q_AC_L 0x28 /* 32 bit Current Address Counter Low dWord */
2152-#define Q_AC_H 0x2c /* 32 bit Current Address Counter High dWord */
2153+#define Q_DA_L 0x20 /* 32 bit Current Descriptor Address Low DWord */
2154+#define Q_DA_H 0x24 /* 32 bit Current Descriptor Address High DWord */
2155+#define Q_AC_L 0x28 /* 32 bit Current Address Counter Low DWord */
2156+#define Q_AC_H 0x2c /* 32 bit Current Address Counter High DWord */
2157 #define Q_BC 0x30 /* 32 bit Current Byte Counter */
2158 #define Q_CSR 0x34 /* 32 bit BMU Control/Status Register */
2159 #define Q_F 0x38 /* 32 bit Flag Register */
2160@@ -570,8 +815,56 @@
2161 #define Q_T1_SV 0x3f /* 8 bit Test Register 1 Supervisor SM */
2162 #define Q_T2 0x40 /* 32 bit Test Register 2 */
2163 #define Q_T3 0x44 /* 32 bit Test Register 3 */
2164+
2165+/* Yukon-2 */
2166+#define Q_DONE 0x24 /* 16 bit Done Index */
2167+
2168+#define Q_WM 0x40 /* 16 bit FIFO Watermark */
2169+#define Q_AL 0x42 /* 8 bit FIFO Alignment */
2170+ /* 0x43: reserved */
2171+/* RX Queue */
2172+#define Q_RX_RSP 0x44 /* 16 bit FIFO Read Shadow Pointer */
2173+#define Q_RX_RSL 0x46 /* 8 bit FIFO Read Shadow Level */
2174+ /* 0x47: reserved */
2175+#define Q_RX_RP 0x48 /* 8 bit FIFO Read Pointer */
2176+ /* 0x49: reserved */
2177+#define Q_RX_RL 0x4a /* 8 bit FIFO Read Level */
2178+ /* 0x4b: reserved */
2179+#define Q_RX_WP 0x4c /* 8 bit FIFO Write Pointer */
2180+#define Q_RX_WSP 0x4d /* 8 bit FIFO Write Shadow Pointer */
2181+#define Q_RX_WL 0x4e /* 8 bit FIFO Write Level */
2182+#define Q_RX_WSL 0x4f /* 8 bit FIFO Write Shadow Level */
2183+/* TX Queue */
2184+#define Q_TX_WSP 0x44 /* 16 bit FIFO Write Shadow Pointer */
2185+#define Q_TX_WSL 0x46 /* 8 bit FIFO Write Shadow Level */
2186+ /* 0x47: reserved */
2187+#define Q_TX_WP 0x48 /* 8 bit FIFO Write Pointer */
2188+ /* 0x49: reserved */
2189+#define Q_TX_WL 0x4a /* 8 bit FIFO Write Level */
2190+ /* 0x4b: reserved */
2191+#define Q_TX_RP 0x4c /* 8 bit FIFO Read Pointer */
2192+ /* 0x4d: reserved */
2193+#define Q_TX_RL 0x4e /* 8 bit FIFO Read Level */
2194+ /* 0x4f: reserved */
2195+
2196 /* 0x48 - 0x7f: reserved */
2197
2198+/* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/
2199+#define Y2_B8_PREF_REGS 0x0450
2200+
2201+#define PREF_UNIT_CTRL_REG 0x00 /* 32 bit Prefetch Control register */
2202+#define PREF_UNIT_LAST_IDX_REG 0x04 /* 16 bit Last Index */
2203+#define PREF_UNIT_ADDR_LOW_REG 0x08 /* 32 bit List start addr, low part */
2204+#define PREF_UNIT_ADDR_HI_REG 0x0c /* 32 bit List start addr, high part*/
2205+#define PREF_UNIT_GET_IDX_REG 0x10 /* 16 bit Get Index */
2206+#define PREF_UNIT_PUT_IDX_REG 0x14 /* 16 bit Put Index */
2207+#define PREF_UNIT_FIFO_WP_REG 0x20 /* 8 bit FIFO write pointer */
2208+#define PREF_UNIT_FIFO_RP_REG 0x24 /* 8 bit FIFO read pointer */
2209+#define PREF_UNIT_FIFO_WM_REG 0x28 /* 8 bit FIFO watermark */
2210+#define PREF_UNIT_FIFO_LEV_REG 0x2c /* 8 bit FIFO level */
2211+
2212+#define PREF_UNIT_MASK_IDX 0x0fff
2213+
2214 /*
2215 * Bank 16 - 23
2216 */
2217@@ -583,17 +876,17 @@
2218 #define RB_END 0x04 /* 32 bit RAM Buffer End Address */
2219 #define RB_WP 0x08 /* 32 bit RAM Buffer Write Pointer */
2220 #define RB_RP 0x0c /* 32 bit RAM Buffer Read Pointer */
2221-#define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Pack */
2222-#define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Pack */
2223+#define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Packet */
2224+#define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Packet */
2225 #define RB_RX_UTHP 0x18 /* 32 bit Rx Upper Threshold, High Prio */
2226 #define RB_RX_LTHP 0x1c /* 32 bit Rx Lower Threshold, High Prio */
2227 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
2228 #define RB_PC 0x20 /* 32 bit RAM Buffer Packet Counter */
2229 #define RB_LEV 0x24 /* 32 bit RAM Buffer Level Register */
2230-#define RB_CTRL 0x28 /* 8 bit RAM Buffer Control Register */
2231+#define RB_CTRL 0x28 /* 32 bit RAM Buffer Control Register */
2232 #define RB_TST1 0x29 /* 8 bit RAM Buffer Test Register 1 */
2233-#define RB_TST2 0x2A /* 8 bit RAM Buffer Test Register 2 */
2234- /* 0x2c - 0x7f: reserved */
2235+#define RB_TST2 0x2a /* 8 bit RAM Buffer Test Register 2 */
2236+ /* 0x2b - 0x7f: reserved */
2237
2238 /*
2239 * Bank 24
2240@@ -603,7 +896,7 @@
2241 * use MR_ADDR() to access
2242 */
2243 #define RX_MFF_EA 0x0c00 /* 32 bit Receive MAC FIFO End Address */
2244-#define RX_MFF_WP 0x0c04 /* 32 bit Receive MAC FIFO Write Pointer */
2245+#define RX_MFF_WP 0x0c04 /* 32 bit Receive MAC FIFO Write Pointer */
2246 /* 0x0c08 - 0x0c0b: reserved */
2247 #define RX_MFF_RP 0x0c0c /* 32 bit Receive MAC FIFO Read Pointer */
2248 #define RX_MFF_PC 0x0c10 /* 32 bit Receive MAC FIFO Packet Cnt */
2249@@ -628,20 +921,23 @@
2250 #define LNK_LED_REG 0x0c3c /* 8 bit Link LED Register */
2251 /* 0x0c3d - 0x0c3f: reserved */
2252
2253-/* Receive GMAC FIFO (YUKON only), use MR_ADDR() to access */
2254+/* Receive GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
2255 #define RX_GMF_EA 0x0c40 /* 32 bit Rx GMAC FIFO End Address */
2256 #define RX_GMF_AF_THR 0x0c44 /* 32 bit Rx GMAC FIFO Almost Full Thresh. */
2257 #define RX_GMF_CTRL_T 0x0c48 /* 32 bit Rx GMAC FIFO Control/Test */
2258 #define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */
2259 #define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */
2260- /* 0x0c54 - 0x0c5f: reserved */
2261-#define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */
2262+#define RX_GMF_TR_THR 0x0c54 /* 32 bit Rx Truncation Threshold (Yukon-2) */
2263+#define RX_GMF_UP_THR 0x0c58 /* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */
2264+#define RX_GMF_LP_THR 0x0c5a /* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */
2265+#define RX_GMF_VLAN 0x0c5c /* 32 bit Rx VLAN Type Register (Yukon-2) */
2266+#define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */
2267 /* 0x0c64 - 0x0c67: reserved */
2268-#define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */
2269+#define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */
2270 /* 0x0c6c - 0x0c6f: reserved */
2271-#define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */
2272+#define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */
2273 /* 0x0c74 - 0x0c77: reserved */
2274-#define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */
2275+#define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */
2276 /* 0x0c7c - 0x0c7f: reserved */
2277
2278 /*
2279@@ -658,7 +954,7 @@
2280 * use MR_ADDR() to access
2281 */
2282 #define TX_MFF_EA 0x0d00 /* 32 bit Transmit MAC FIFO End Address */
2283-#define TX_MFF_WP 0x0d04 /* 32 bit Transmit MAC FIFO WR Pointer */
2284+#define TX_MFF_WP 0x0d04 /* 32 bit Transmit MAC FIFO WR Pointer */
2285 #define TX_MFF_WSP 0x0d08 /* 32 bit Transmit MAC FIFO WR Shadow Ptr */
2286 #define TX_MFF_RP 0x0d0c /* 32 bit Transmit MAC FIFO RD Pointer */
2287 #define TX_MFF_PC 0x0d10 /* 32 bit Transmit MAC FIFO Packet Cnt */
2288@@ -676,18 +972,19 @@
2289 #define TX_LED_TST 0x0d29 /* 8 bit Transmit LED Cnt Test Reg */
2290 /* 0x0d2a - 0x0d3f: reserved */
2291
2292-/* Transmit GMAC FIFO (YUKON only), use MR_ADDR() to access */
2293+/* Transmit GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
2294 #define TX_GMF_EA 0x0d40 /* 32 bit Tx GMAC FIFO End Address */
2295-#define TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
2296+#define TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh. */
2297 #define TX_GMF_CTRL_T 0x0d48 /* 32 bit Tx GMAC FIFO Control/Test */
2298- /* 0x0d4c - 0x0d5f: reserved */
2299-#define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */
2300-#define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
2301-#define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */
2302+ /* 0x0d4c - 0x0d5b: reserved */
2303+#define TX_GMF_VLAN 0x0d5c /* 32 bit Tx VLAN Type Register (Yukon-2) */
2304+#define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */
2305+#define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Pointer */
2306+#define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */
2307 /* 0x0d6c - 0x0d6f: reserved */
2308-#define TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */
2309-#define TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */
2310-#define TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */
2311+#define TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */
2312+#define TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */
2313+#define TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */
2314 /* 0x0d7c - 0x0d7f: reserved */
2315
2316 /*
2317@@ -713,12 +1010,84 @@
2318 #define GMAC_TI_ST_CTRL 0x0e18 /* 8 bit Time Stamp Timer Ctrl Reg */
2319 /* 0x0e19: reserved */
2320 #define GMAC_TI_ST_TST 0x0e1a /* 8 bit Time Stamp Timer Test Reg */
2321- /* 0x0e1b - 0x0e7f: reserved */
2322+ /* 0x0e1b - 0x0e1f: reserved */
2323+
2324+/* Polling Unit Registers (Yukon-2 only) */
2325+#define POLL_CTRL 0x0e20 /* 32 bit Polling Unit Control Reg */
2326+#define POLL_LAST_IDX 0x0e24 /* 16 bit Polling Unit List Last Index */
2327+ /* 0x0e26 - 0x0e27: reserved */
2328+#define POLL_LIST_ADDR_LO 0x0e28 /* 32 bit Poll. List Start Addr (low) */
2329+#define POLL_LIST_ADDR_HI 0x0e2c /* 32 bit Poll. List Start Addr (high) */
2330+ /* 0x0e30 - 0x0e3f: reserved */
2331+
2332+/* ASF Subsystem Registers (Yukon-2 only) */
2333+#define B28_Y2_SMB_CONFIG 0x0e40 /* 32 bit ASF SMBus Config Register */
2334+#define B28_Y2_SMB_CSD_REG 0x0e44 /* 32 bit ASF SMB Control/Status/Data */
2335+ /* 0x0e48 - 0x0e5f: reserved */
2336+#define B28_Y2_ASF_IRQ_V_BASE 0x0e60 /* 32 bit ASF IRQ Vector Base */
2337+ /* 0x0e64 - 0x0e67: reserved */
2338+#define B28_Y2_ASF_STAT_CMD 0x0e68 /* 32 bit ASF Status and Command Reg */
2339+#define B28_Y2_ASF_HOST_COM 0x0e6c /* 32 bit ASF Host Communication Reg */
2340+#define B28_Y2_DATA_REG_1 0x0e70 /* 32 bit ASF/Host Data Register 1 */
2341+#define B28_Y2_DATA_REG_2 0x0e74 /* 32 bit ASF/Host Data Register 2 */
2342+#define B28_Y2_DATA_REG_3 0x0e78 /* 32 bit ASF/Host Data Register 3 */
2343+#define B28_Y2_DATA_REG_4 0x0e7c /* 32 bit ASF/Host Data Register 4 */
2344
2345 /*
2346 * Bank 29
2347 */
2348- /* 0x0e80 - 0x0efc: reserved */
2349+
2350+/* Status BMU Registers (Yukon-2 only)*/
2351+#define STAT_CTRL 0x0e80 /* 32 bit Status BMU Control Reg */
2352+#define STAT_LAST_IDX 0x0e84 /* 16 bit Status BMU Last Index */
2353+ /* 0x0e85 - 0x0e86: reserved */
2354+#define STAT_LIST_ADDR_LO 0x0e88 /* 32 bit Status List Start Addr (low) */
2355+#define STAT_LIST_ADDR_HI 0x0e8c /* 32 bit Status List Start Addr (high) */
2356+#define STAT_TXA1_RIDX 0x0e90 /* 16 bit Status TxA1 Report Index Reg */
2357+#define STAT_TXS1_RIDX 0x0e92 /* 16 bit Status TxS1 Report Index Reg */
2358+#define STAT_TXA2_RIDX 0x0e94 /* 16 bit Status TxA2 Report Index Reg */
2359+#define STAT_TXS2_RIDX 0x0e96 /* 16 bit Status TxS2 Report Index Reg */
2360+#define STAT_TX_IDX_TH 0x0e98 /* 16 bit Status Tx Index Threshold Reg */
2361+ /* 0x0e9a - 0x0e9b: reserved */
2362+#define STAT_PUT_IDX 0x0e9c /* 16 bit Status Put Index Reg */
2363+ /* 0x0e9e - 0x0e9f: reserved */
2364+
2365+/* FIFO Control/Status Registers (Yukon-2 only) */
2366+#define STAT_FIFO_WP 0x0ea0 /* 8 bit Status FIFO Write Pointer Reg */
2367+ /* 0x0ea1 - 0x0ea3: reserved */
2368+#define STAT_FIFO_RP 0x0ea4 /* 8 bit Status FIFO Read Pointer Reg */
2369+ /* 0x0ea5: reserved */
2370+#define STAT_FIFO_RSP 0x0ea6 /* 8 bit Status FIFO Read Shadow Ptr */
2371+ /* 0x0ea7: reserved */
2372+#define STAT_FIFO_LEVEL 0x0ea8 /* 8 bit Status FIFO Level Reg */
2373+ /* 0x0ea9: reserved */
2374+#define STAT_FIFO_SHLVL 0x0eaa /* 8 bit Status FIFO Shadow Level Reg */
2375+ /* 0x0eab: reserved */
2376+#define STAT_FIFO_WM 0x0eac /* 8 bit Status FIFO Watermark Reg */
2377+#define STAT_FIFO_ISR_WM 0x0ead /* 8 bit Status FIFO ISR Watermark Reg */
2378+ /* 0x0eae - 0x0eaf: reserved */
2379+
2380+/* Level and ISR Timer Registers (Yukon-2 only) */
2381+#define STAT_LEV_TIMER_INI 0x0eb0 /* 32 bit Level Timer Init. Value Reg */
2382+#define STAT_LEV_TIMER_CNT 0x0eb4 /* 32 bit Level Timer Counter Reg */
2383+#define STAT_LEV_TIMER_CTRL 0x0eb8 /* 8 bit Level Timer Control Reg */
2384+#define STAT_LEV_TIMER_TEST 0x0eb9 /* 8 bit Level Timer Test Reg */
2385+ /* 0x0eba - 0x0ebf: reserved */
2386+#define STAT_TX_TIMER_INI 0x0ec0 /* 32 bit Tx Timer Init. Value Reg */
2387+#define STAT_TX_TIMER_CNT 0x0ec4 /* 32 bit Tx Timer Counter Reg */
2388+#define STAT_TX_TIMER_CTRL 0x0ec8 /* 8 bit Tx Timer Control Reg */
2389+#define STAT_TX_TIMER_TEST 0x0ec9 /* 8 bit Tx Timer Test Reg */
2390+ /* 0x0eca - 0x0ecf: reserved */
2391+#define STAT_ISR_TIMER_INI 0x0ed0 /* 32 bit ISR Timer Init. Value Reg */
2392+#define STAT_ISR_TIMER_CNT 0x0ed4 /* 32 bit ISR Timer Counter Reg */
2393+#define STAT_ISR_TIMER_CTRL 0x0ed8 /* 8 bit ISR Timer Control Reg */
2394+#define STAT_ISR_TIMER_TEST 0x0ed9 /* 8 bit ISR Timer Test Reg */
2395+ /* 0x0eda - 0x0eff: reserved */
2396+
2397+#define ST_LAST_IDX_MASK 0x007f /* Last Index Mask */
2398+#define ST_TXRP_IDX_MASK 0x0fff /* Tx Report Index Mask */
2399+#define ST_TXTH_IDX_MASK 0x0fff /* Tx Threshold Index Mask */
2400+#define ST_WM_IDX_MASK 0x3f /* FIFO Watermark Index Mask */
2401
2402 /*
2403 * Bank 30
2404@@ -742,11 +1111,9 @@
2405 #define WOL_MATCH_RES 0x0f23 /* 8 bit WOL Match Result Reg */
2406 #define WOL_MAC_ADDR_LO 0x0f24 /* 32 bit WOL MAC Address Low */
2407 #define WOL_MAC_ADDR_HI 0x0f28 /* 16 bit WOL MAC Address High */
2408-#define WOL_PATT_RPTR 0x0f2c /* 8 bit WOL Pattern Read Ptr */
2409-
2410-/* use this macro to access above registers */
2411-#define WOL_REG(Reg) ((Reg) + (pAC->GIni.GIWolOffs))
2412-
2413+#define WOL_PATT_PME 0x0f2a /* 8 bit WOL PME Match Enable (Yukon-2) */
2414+#define WOL_PATT_ASFM 0x0f2b /* 8 bit WOL ASF Match Enable (Yukon-2) */
2415+#define WOL_PATT_RPTR 0x0f2c /* 8 bit WOL Pattern Read Pointer */
2416
2417 /* WOL Pattern Length Registers (YUKON only) */
2418
2419@@ -764,11 +1131,22 @@
2420 */
2421 /* 0x0f80 - 0x0fff: reserved */
2422
2423+/* WOL registers link 2 */
2424+
2425+/* use this macro to access WOL registers */
2426+#define WOL_REG(Port, Reg) ((Reg) + ((Port)*0x80) + (pAC->GIni.GIWolOffs))
2427+
2428 /*
2429 * Bank 32 - 33
2430 */
2431 #define WOL_PATT_RAM_1 0x1000 /* WOL Pattern RAM Link 1 */
2432+#define WOL_PATT_RAM_2 0x1400 /* WOL Pattern RAM Link 2 */
2433+
2434+/* use this macro to retrieve the pattern ram base address */
2435+#define WOL_PATT_RAM_BASE(Port) (WOL_PATT_RAM_1 + (Port)*0x400)
2436
2437+/* offset to configuration space on Yukon-2 */
2438+#define Y2_CFG_SPC 0x1c00
2439 /*
2440 * Bank 0x22 - 0x3f
2441 */
2442@@ -800,13 +1178,27 @@
2443 */
2444 /* B0_RAP 8 bit Register Address Port */
2445 /* Bit 7: reserved */
2446-#define RAP_RAP 0x3f /* Bit 6..0: 0 = block 0,..,6f = block 6f */
2447+#define RAP_MSK 0x7f /* Bit 6..0: 0 = block 0,..,6f = block 6f */
2448+
2449+/* B0_CTST 24 bit Control/Status register */
2450+ /* Bit 23..18: reserved */
2451+#define Y2_VMAIN_AVAIL BIT_17 /* VMAIN available (YUKON-2 only) */
2452+#define Y2_VAUX_AVAIL BIT_16 /* VAUX available (YUKON-2 only) */
2453+#define Y2_HW_WOL_ON BIT_15S /* HW WOL On (Yukon-EC Ultra A1 only) */
2454+#define Y2_HW_WOL_OFF BIT_14S /* HW WOL Off (Yukon-EC Ultra A1 only) */
2455+#define Y2_ASF_ENABLE BIT_13S /* ASF Unit Enable (YUKON-2 only) */
2456+#define Y2_ASF_DISABLE BIT_12S /* ASF Unit Disable (YUKON-2 only) */
2457+#define Y2_CLK_RUN_ENA BIT_11S /* CLK_RUN Enable (YUKON-2 only) */
2458+#define Y2_CLK_RUN_DIS BIT_10S /* CLK_RUN Disable (YUKON-2 only) */
2459+#define Y2_LED_STAT_ON BIT_9S /* Status LED On (YUKON-2 only) */
2460+#define Y2_LED_STAT_OFF BIT_8S /* Status LED Off (YUKON-2 only) */
2461+ /* Bit 7.. 0: same as below */
2462
2463 /* B0_CTST 16 bit Control/Status register */
2464 /* Bit 15..14: reserved */
2465-#define CS_CLK_RUN_HOT BIT_13S /* CLK_RUN hot m. (YUKON-Lite only) */
2466-#define CS_CLK_RUN_RST BIT_12S /* CLK_RUN reset (YUKON-Lite only) */
2467-#define CS_CLK_RUN_ENA BIT_11S /* CLK_RUN enable (YUKON-Lite only) */
2468+#define CS_CLK_RUN_HOT BIT_13S /* CLK_RUN Hot m. (YUKON-Lite only) */
2469+#define CS_CLK_RUN_RST BIT_12S /* CLK_RUN Reset (YUKON-Lite only) */
2470+#define CS_CLK_RUN_ENA BIT_11S /* CLK_RUN Enable (YUKON-Lite only) */
2471 #define CS_VAUX_AVAIL BIT_10S /* VAUX available (YUKON only) */
2472 #define CS_BUS_CLOCK BIT_9S /* Bus Clock 0/1 = 33/66 MHz */
2473 #define CS_BUS_SLOT_SZ BIT_8S /* Slot Size 0/1 = 32/64 bit slot */
2474@@ -814,26 +1206,27 @@
2475 #define CS_CL_SW_IRQ BIT_6S /* Clear IRQ SW Request */
2476 #define CS_STOP_DONE BIT_5S /* Stop Master is finished */
2477 #define CS_STOP_MAST BIT_4S /* Command Bit to stop the master */
2478-#define CS_MRST_CLR BIT_3S /* Clear Master reset */
2479-#define CS_MRST_SET BIT_2S /* Set Master reset */
2480-#define CS_RST_CLR BIT_1S /* Clear Software reset */
2481-#define CS_RST_SET BIT_0S /* Set Software reset */
2482+#define CS_MRST_CLR BIT_3S /* Clear Master Reset */
2483+#define CS_MRST_SET BIT_2S /* Set Master Reset */
2484+#define CS_RST_CLR BIT_1S /* Clear Software Reset */
2485+#define CS_RST_SET BIT_0S /* Set Software Reset */
2486
2487-/* B0_LED 8 Bit LED register */
2488+/* B0_LED 8 Bit LED register (GENESIS only)*/
2489 /* Bit 7.. 2: reserved */
2490-#define LED_STAT_ON BIT_1S /* Status LED on */
2491-#define LED_STAT_OFF BIT_0S /* Status LED off */
2492+#define LED_STAT_ON BIT_1S /* Status LED On */
2493+#define LED_STAT_OFF BIT_0S /* Status LED Off */
2494
2495 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
2496 #define PC_VAUX_ENA BIT_7 /* Switch VAUX Enable */
2497-#define PC_VAUX_DIS BIT_6 /* Switch VAUX Disable */
2498-#define PC_VCC_ENA BIT_5 /* Switch VCC Enable */
2499-#define PC_VCC_DIS BIT_4 /* Switch VCC Disable */
2500-#define PC_VAUX_ON BIT_3 /* Switch VAUX On */
2501-#define PC_VAUX_OFF BIT_2 /* Switch VAUX Off */
2502-#define PC_VCC_ON BIT_1 /* Switch VCC On */
2503-#define PC_VCC_OFF BIT_0 /* Switch VCC Off */
2504+#define PC_VAUX_DIS BIT_6 /* Switch VAUX Disable */
2505+#define PC_VCC_ENA BIT_5 /* Switch VCC Enable */
2506+#define PC_VCC_DIS BIT_4 /* Switch VCC Disable */
2507+#define PC_VAUX_ON BIT_3 /* Switch VAUX On */
2508+#define PC_VAUX_OFF BIT_2 /* Switch VAUX Off */
2509+#define PC_VCC_ON BIT_1 /* Switch VCC On */
2510+#define PC_VCC_OFF BIT_0 /* Switch VCC Off */
2511
2512+/* Yukon and Genesis */
2513 /* B0_ISRC 32 bit Interrupt Source Register */
2514 /* B0_IMSK 32 bit Interrupt Mask Register */
2515 /* B0_SP_ISRC 32 bit Special Interrupt Source Reg */
2516@@ -879,12 +1272,51 @@
2517 #define IS_XA2_F BIT_1 /* Q_XA2 End of Frame */
2518 #define IS_XA2_C BIT_0 /* Q_XA2 Encoding Error */
2519
2520+/* Yukon-2 */
2521+/* B0_ISRC 32 bit Interrupt Source Register */
2522+/* B0_IMSK 32 bit Interrupt Mask Register */
2523+/* B0_SP_ISRC 32 bit Special Interrupt Source Reg */
2524+/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
2525+/* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */
2526+/* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */
2527+/* B0_Y2_SP_EISR 32 bit Enter ISR Reg */
2528+/* B0_Y2_SP_LISR 32 bit Leave ISR Reg */
2529+#define Y2_IS_PORT_MASK(Port, Mask) ((Mask) << (Port*8))
2530+#define Y2_IS_HW_ERR BIT_31 /* Interrupt HW Error */
2531+#define Y2_IS_STAT_BMU BIT_30 /* Status BMU Interrupt */
2532+#define Y2_IS_ASF BIT_29 /* ASF subsystem Interrupt */
2533+ /* Bit 28: reserved */
2534+#define Y2_IS_POLL_CHK BIT_27 /* Check IRQ from polling unit */
2535+#define Y2_IS_TWSI_RDY BIT_26 /* IRQ on end of TWSI Tx */
2536+#define Y2_IS_IRQ_SW BIT_25 /* SW forced IRQ */
2537+#define Y2_IS_TIMINT BIT_24 /* IRQ from Timer */
2538+ /* Bit 23..16 reserved */
2539+ /* Link 2 Interrupts */
2540+#define Y2_IS_IRQ_PHY2 BIT_12 /* Interrupt from PHY 2 */
2541+#define Y2_IS_IRQ_MAC2 BIT_11 /* Interrupt from MAC 2 */
2542+#define Y2_IS_CHK_RX2 BIT_10 /* Descriptor error Rx 2 */
2543+#define Y2_IS_CHK_TXS2 BIT_9 /* Descriptor error TXS 2 */
2544+#define Y2_IS_CHK_TXA2 BIT_8 /* Descriptor error TXA 2 */
2545+ /* Bit 7.. 5 reserved */
2546+ /* Link 1 interrupts */
2547+#define Y2_IS_IRQ_PHY1 BIT_4 /* Interrupt from PHY 1 */
2548+#define Y2_IS_IRQ_MAC1 BIT_3 /* Interrupt from MAC 1 */
2549+#define Y2_IS_CHK_RX1 BIT_2 /* Descriptor error Rx 1 */
2550+#define Y2_IS_CHK_TXS1 BIT_1 /* Descriptor error TXS 1 */
2551+#define Y2_IS_CHK_TXA1 BIT_0 /* Descriptor error TXA 1 */
2552+
2553+#define Y2_IS_L1_MASK 0x0000001fUL /* IRQ Mask for port 1 */
2554+
2555+#define Y2_IS_L2_MASK 0x00001f00UL /* IRQ Mask for port 2 */
2556+
2557+#define Y2_IS_ALL_MSK 0xef001f1fUL /* All Interrupt bits */
2558
2559+/* Yukon and Genesis */
2560 /* B0_HWE_ISRC 32 bit HW Error Interrupt Src Reg */
2561 /* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */
2562 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
2563 #define IS_ERR_MSK 0x00000fffL /* All Error bits */
2564- /* Bit 31..14: reserved */
2565+ /* Bit 31..14: reserved */
2566 #define IS_IRQ_TIST_OV BIT_13 /* Time Stamp Timer Overflow (YUKON only) */
2567 #define IS_IRQ_SENSOR BIT_12 /* IRQ from Sensor (YUKON only) */
2568 #define IS_IRQ_MST_ERR BIT_11 /* IRQ master error detected */
2569@@ -900,6 +1332,43 @@
2570 #define IS_R1_PAR_ERR BIT_1 /* Queue R1 Parity Error */
2571 #define IS_R2_PAR_ERR BIT_0 /* Queue R2 Parity Error */
2572
2573+/* Yukon-2 */
2574+/* B0_HWE_ISRC 32 bit HW Error Interrupt Src Reg */
2575+/* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */
2576+/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
2577+ /* Bit: 31..30 reserved */
2578+#define Y2_IS_TIST_OV BIT_29 /* Time Stamp Timer overflow interrupt */
2579+#define Y2_IS_SENSOR BIT_28 /* Sensor interrupt */
2580+#define Y2_IS_MST_ERR BIT_27 /* Master error interrupt */
2581+#define Y2_IS_IRQ_STAT BIT_26 /* Status exception interrupt */
2582+#define Y2_IS_PCI_EXP BIT_25 /* PCI-Express interrupt */
2583+#define Y2_IS_PCI_NEXP BIT_24 /* Bus Abort detected */
2584+ /* Bit: 23..14 reserved */
2585+ /* Link 2 */
2586+#define Y2_IS_PAR_RD2 BIT_13 /* Read RAM parity error interrupt */
2587+#define Y2_IS_PAR_WR2 BIT_12 /* Write RAM parity error interrupt */
2588+#define Y2_IS_PAR_MAC2 BIT_11 /* MAC hardware fault interrupt */
2589+#define Y2_IS_PAR_RX2 BIT_10 /* Parity Error Rx Queue 2 */
2590+#define Y2_IS_TCP_TXS2 BIT_9 /* TCP length mismatch sync Tx queue IRQ */
2591+#define Y2_IS_TCP_TXA2 BIT_8 /* TCP length mismatch async Tx queue IRQ */
2592+ /* Bit: 9.. 6 reserved */
2593+ /* Link 1 */
2594+#define Y2_IS_PAR_RD1 BIT_5 /* Read RAM parity error interrupt */
2595+#define Y2_IS_PAR_WR1 BIT_4 /* Write RAM parity error interrupt */
2596+#define Y2_IS_PAR_MAC1 BIT_3 /* MAC hardware fault interrupt */
2597+#define Y2_IS_PAR_RX1 BIT_2 /* Parity Error Rx Queue 1 */
2598+#define Y2_IS_TCP_TXS1 BIT_1 /* TCP length mismatch sync Tx queue IRQ */
2599+#define Y2_IS_TCP_TXA1 BIT_0 /* TCP length mismatch async Tx queue IRQ */
2600+
2601+#define Y2_HWE_L1_MASK (Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |\
2602+ Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1)
2603+#define Y2_HWE_L2_MASK (Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |\
2604+ Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2)
2605+
2606+#define Y2_HWE_ALL_MSK (Y2_IS_TIST_OV | /* Y2_IS_SENSOR | */ Y2_IS_MST_ERR |\
2607+ Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP |\
2608+ Y2_HWE_L1_MASK | Y2_HWE_L2_MASK)
2609+
2610 /* B2_CONN_TYP 8 bit Connector type */
2611 /* B2_PMD_TYP 8 bit PMD type */
2612 /* Values of connector and PMD type comply to SysKonnect internal std */
2613@@ -908,19 +1377,74 @@
2614 #define CFG_CHIP_R_MSK (0xf<<4) /* Bit 7.. 4: Chip Revision */
2615 /* Bit 3.. 2: reserved */
2616 #define CFG_DIS_M2_CLK BIT_1S /* Disable Clock for 2nd MAC */
2617-#define CFG_SNG_MAC BIT_0S /* MAC Config: 0=2 MACs / 1=1 MAC*/
2618+#define CFG_SNG_MAC BIT_0S /* MAC Config: 0 = 2 MACs; 1 = 1 MAC */
2619
2620-/* B2_CHIP_ID 8 bit Chip Identification Number */
2621+/* B2_CHIP_ID 8 bit Chip Identification Number */
2622 #define CHIP_ID_GENESIS 0x0a /* Chip ID for GENESIS */
2623 #define CHIP_ID_YUKON 0xb0 /* Chip ID for YUKON */
2624 #define CHIP_ID_YUKON_LITE 0xb1 /* Chip ID for YUKON-Lite (Rev. A1-A3) */
2625 #define CHIP_ID_YUKON_LP 0xb2 /* Chip ID for YUKON-LP */
2626+#define CHIP_ID_YUKON_XL 0xb3 /* Chip ID for YUKON-2 XL */
2627+#define CHIP_ID_YUKON_EC_U 0xb4 /* Chip ID for YUKON-2 EC Ultra */
2628+#define CHIP_ID_YUKON_EC 0xb6 /* Chip ID for YUKON-2 EC */
2629+#define CHIP_ID_YUKON_FE 0xb7 /* Chip ID for YUKON-2 FE */
2630
2631 #define CHIP_REV_YU_LITE_A1 3 /* Chip Rev. for YUKON-Lite A1,A2 */
2632 #define CHIP_REV_YU_LITE_A3 7 /* Chip Rev. for YUKON-Lite A3 */
2633
2634+#define CHIP_REV_YU_XL_A0 0 /* Chip Rev. for Yukon-2 A0 */
2635+#define CHIP_REV_YU_XL_A1 1 /* Chip Rev. for Yukon-2 A1 */
2636+#define CHIP_REV_YU_XL_A2 2 /* Chip Rev. for Yukon-2 A2 */
2637+#define CHIP_REV_YU_XL_A3 3 /* Chip Rev. for Yukon-2 A3 */
2638+
2639+#define CHIP_REV_YU_EC_A1 0 /* Chip Rev. for Yukon-EC A0,A1 */
2640+#define CHIP_REV_YU_EC_A2 1 /* Chip Rev. for Yukon-EC A2 */
2641+#define CHIP_REV_YU_EC_A3 2 /* Chip Rev. for Yukon-EC A3 */
2642+
2643+#define CHIP_REV_YU_EC_U_A0 1 /* Chip Rev. for Yukon-EC Ultra A0 */
2644+#define CHIP_REV_YU_EC_U_A1 2 /* Chip Rev. for Yukon-EC Ultra A1 */
2645+
2646+/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
2647+#define Y2_STATUS_LNK2_INAC BIT_7S /* Status Link 2 inactiv (0 = activ) */
2648+#define Y2_CLK_GAT_LNK2_DIS BIT_6S /* Disable PHY clock for Link 2 */
2649+#define Y2_COR_CLK_LNK2_DIS BIT_5S /* Disable Core clock Link 2 */
2650+#define Y2_PCI_CLK_LNK2_DIS BIT_4S /* Disable PCI clock Link 2 */
2651+#define Y2_STATUS_LNK1_INAC BIT_3S /* Status Link 1 inactiv (0 = activ) */
2652+#define Y2_CLK_GAT_LNK1_DIS BIT_2S /* Disable PHY clock for Link 1 */
2653+#define Y2_COR_CLK_LNK1_DIS BIT_1S /* Disable Core clock Link 1 */
2654+#define Y2_PCI_CLK_LNK1_DIS BIT_0S /* Disable PCI clock Link 1 */
2655+
2656+/* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
2657+ /* Bit 7.. 5: reserved */
2658+#define CFG_LED_MODE_MSK (7<<2) /* Bit 4.. 2: LED Mode Mask */
2659+#define CFG_LINK_2_AVAIL BIT_1S /* Link 2 available */
2660+#define CFG_LINK_1_AVAIL BIT_0S /* Link 1 available */
2661+
2662+#define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2)
2663+#define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)
2664+
2665+#define CFG_LED_SING_ACT_LNK 0 /* Single LED ACT/LNK mode */
2666+#define CFG_LED_DUAL_ACT_LNK 1 /* Dual LED ACT/LNK mode */
2667+
2668+/* B2_E_3 8 bit lower 4 bits used for HW self test result */
2669+#define B2_E3_RES_MASK 0x0f
2670+
2671 /* B2_FAR 32 bit Flash-Prom Addr Reg/Cnt */
2672-#define FAR_ADDR 0x1ffffL /* Bit 16.. 0: FPROM Address mask */
2673+#define FAR_ADDR 0x1ffffL /* Bit 16.. 0: FPROM Address Mask */
2674+
2675+/* B2_Y2_CLK_CTRL 32 bit Core Clock Frequency Control Register (Yukon-2/EC) */
2676+ /* Bit 31..24: reserved */
2677+/* Yukon-EC/FE */
2678+#define Y2_CLK_DIV_VAL_MSK (0xffL<<16) /* Bit 23..16: Clock Divisor Value */
2679+#define Y2_CLK_DIV_VAL(x) (SHIFT16(x) & Y2_CLK_DIV_VAL_MSK)
2680+/* Yukon-2 */
2681+#define Y2_CLK_DIV_VAL2_MSK (7L<<21) /* Bit 23..21: Clock Divisor Value */
2682+#define Y2_CLK_SELECT2_MSK (0x1fL<<16) /* Bit 20..16: Clock Select */
2683+#define Y2_CLK_DIV_VAL_2(x) (SHIFT21(x) & Y2_CLK_DIV_VAL2_MSK)
2684+#define Y2_CLK_SEL_VAL_2(x) (SHIFT16(x) & Y2_CLK_SELECT2_MSK)
2685+ /* Bit 15.. 2: reserved */
2686+#define Y2_CLK_DIV_ENA BIT_1S /* Enable Core Clock Division */
2687+#define Y2_CLK_DIV_DIS BIT_0S /* Disable Core Clock Division */
2688
2689 /* B2_LD_CTRL 8 bit EPROM loader control register */
2690 /* Bits are currently reserved */
2691@@ -960,9 +1484,6 @@
2692 #define DPT_START BIT_1S /* Start Descriptor Poll Timer */
2693 #define DPT_STOP BIT_0S /* Stop Descriptor Poll Timer */
2694
2695-/* B2_E_3 8 bit lower 4 bits used for HW self test result */
2696-#define B2_E3_RES_MASK 0x0f
2697-
2698 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
2699 #define TST_FRC_DPERR_MR BIT_7S /* force DATAPERR on MST RD */
2700 #define TST_FRC_DPERR_MW BIT_6S /* force DATAPERR on MST WR */
2701@@ -975,14 +1496,14 @@
2702
2703 /* B2_TST_CTRL2 8 bit Test Control Register 2 */
2704 /* Bit 7.. 4: reserved */
2705- /* force the following error on the next master read/write */
2706+ /* force the following error on the next master read/write */
2707 #define TST_FRC_DPERR_MR64 BIT_3S /* DataPERR RD 64 */
2708 #define TST_FRC_DPERR_MW64 BIT_2S /* DataPERR WR 64 */
2709 #define TST_FRC_APERR_1M64 BIT_1S /* AddrPERR on 1. phase */
2710 #define TST_FRC_APERR_2M64 BIT_0S /* AddrPERR on 2. phase */
2711
2712 /* B2_GP_IO 32 bit General Purpose I/O Register */
2713- /* Bit 31..26: reserved */
2714+ /* Bit 31..26: reserved */
2715 #define GP_DIR_9 BIT_25 /* IO_9 direct, 0=In/1=Out */
2716 #define GP_DIR_8 BIT_24 /* IO_8 direct, 0=In/1=Out */
2717 #define GP_DIR_7 BIT_23 /* IO_7 direct, 0=In/1=Out */
2718@@ -1009,15 +1530,15 @@
2719 #define I2C_FLAG BIT_31 /* Start read/write if WR */
2720 #define I2C_ADDR (0x7fffL<<16) /* Bit 30..16: Addr to be RD/WR */
2721 #define I2C_DEV_SEL (0x7fL<<9) /* Bit 15.. 9: I2C Device Select */
2722- /* Bit 8.. 5: reserved */
2723+ /* Bit 8.. 5: reserved */
2724 #define I2C_BURST_LEN BIT_4 /* Burst Len, 1/4 bytes */
2725-#define I2C_DEV_SIZE (7<<1) /* Bit 3.. 1: I2C Device Size */
2726-#define I2C_025K_DEV (0<<1) /* 0: 256 Bytes or smal. */
2727-#define I2C_05K_DEV (1<<1) /* 1: 512 Bytes */
2728-#define I2C_1K_DEV (2<<1) /* 2: 1024 Bytes */
2729-#define I2C_2K_DEV (3<<1) /* 3: 2048 Bytes */
2730-#define I2C_4K_DEV (4<<1) /* 4: 4096 Bytes */
2731-#define I2C_8K_DEV (5<<1) /* 5: 8192 Bytes */
2732+#define I2C_DEV_SIZE (7<<1) /* Bit 3.. 1: I2C Device Size */
2733+#define I2C_025K_DEV (0<<1) /* 0: 256 Bytes or smaller */
2734+#define I2C_05K_DEV (1<<1) /* 1: 512 Bytes */
2735+#define I2C_1K_DEV (2<<1) /* 2: 1024 Bytes */
2736+#define I2C_2K_DEV (3<<1) /* 3: 2048 Bytes */
2737+#define I2C_4K_DEV (4<<1) /* 4: 4096 Bytes */
2738+#define I2C_8K_DEV (5<<1) /* 5: 8192 Bytes */
2739 #define I2C_16K_DEV (6<<1) /* 6: 16384 Bytes */
2740 #define I2C_32K_DEV (7<<1) /* 7: 32768 Bytes */
2741 #define I2C_STOP BIT_0 /* Interrupt I2C transfer */
2742@@ -1026,16 +1547,14 @@
2743 /* Bit 31.. 1 reserved */
2744 #define I2C_CLR_IRQ BIT_0 /* Clear I2C IRQ */
2745
2746-/* B2_I2C_SW 32 bit (8 bit access) I2C HW SW Port Register */
2747+/* B2_I2C_SW 32 bit (8 bit access) I2C SW Port Register */
2748 /* Bit 7.. 3: reserved */
2749 #define I2C_DATA_DIR BIT_2S /* direction of I2C_DATA */
2750-#define I2C_DATA BIT_1S /* I2C Data Port */
2751-#define I2C_CLK BIT_0S /* I2C Clock Port */
2752+#define I2C_DATA BIT_1S /* I2C Data Port */
2753+#define I2C_CLK BIT_0S /* I2C Clock Port */
2754
2755-/*
2756- * I2C Address
2757- */
2758-#define I2C_SENS_ADDR LM80_ADDR /* I2C Sensor Address, (Volt and Temp)*/
2759+/* I2C Address */
2760+#define I2C_SENS_ADDR LM80_ADDR /* I2C Sensor Address (Volt and Temp) */
2761
2762
2763 /* B2_BSC_CTRL 8 bit Blink Source Counter Control */
2764@@ -1052,16 +1571,20 @@
2765 #define BSC_T_OFF BIT_1S /* Test mode off */
2766 #define BSC_T_STEP BIT_0S /* Test step */
2767
2768+/* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */
2769+#define PEX_RD_ACCESS BIT_31 /* Access Mode Read = 1, Write = 0 */
2770+#define PEX_DB_ACCESS BIT_30 /* Access to debug register */
2771+
2772
2773 /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
2774 /* Bit 31..19: reserved */
2775 #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
2776
2777 /* RAM Interface Registers */
2778-/* B3_RI_CTRL 16 bit RAM Iface Control Register */
2779+/* B3_RI_CTRL 16 bit RAM Interface Control Register */
2780 /* Bit 15..10: reserved */
2781-#define RI_CLR_RD_PERR BIT_9S /* Clear IRQ RAM Read Parity Err */
2782-#define RI_CLR_WR_PERR BIT_8S /* Clear IRQ RAM Write Parity Err*/
2783+#define RI_CLR_RD_PERR BIT_9S /* Clear IRQ RAM Read Parity Err */
2784+#define RI_CLR_WR_PERR BIT_8S /* Clear IRQ RAM Write Parity Err */
2785 /* Bit 7.. 2: reserved */
2786 #define RI_RST_CLR BIT_1S /* Clear RAM Interface Reset */
2787 #define RI_RST_SET BIT_0S /* Set RAM Interface Reset */
2788@@ -1171,7 +1694,7 @@
2789 /* Bit 31..16: reserved */
2790 #define BC_MAX 0xffff /* Bit 15.. 0: Byte counter */
2791
2792-/* BMU Control Status Registers */
2793+/* BMU Control / Status Registers (Yukon and Genesis) */
2794 /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
2795 /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
2796 /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
2797@@ -1212,13 +1735,48 @@
2798 CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\
2799 CSR_TRANS_RUN)
2800
2801+/* Rx BMU Control / Status Registers (Yukon-2) */
2802+#define BMU_IDLE BIT_31 /* BMU Idle State */
2803+#define BMU_RX_TCP_PKT BIT_30 /* Rx TCP Packet (when RSS Hash enabled) */
2804+#define BMU_RX_IP_PKT BIT_29 /* Rx IP Packet (when RSS Hash enabled) */
2805+ /* Bit 28..16: reserved */
2806+#define BMU_ENA_RX_RSS_HASH BIT_15 /* Enable Rx RSS Hash */
2807+#define BMU_DIS_RX_RSS_HASH BIT_14 /* Disable Rx RSS Hash */
2808+#define BMU_ENA_RX_CHKSUM BIT_13 /* Enable Rx TCP/IP Checksum Check */
2809+#define BMU_DIS_RX_CHKSUM BIT_12 /* Disable Rx TCP/IP Checksum Check */
2810+#define BMU_CLR_IRQ_PAR BIT_11 /* Clear IRQ on Parity errors (Rx) */
2811+#define BMU_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segmen. error (Tx) */
2812+#define BMU_CLR_IRQ_CHK BIT_10 /* Clear IRQ Check */
2813+#define BMU_STOP BIT_9 /* Stop Rx/Tx Queue */
2814+#define BMU_START BIT_8 /* Start Rx/Tx Queue */
2815+#define BMU_FIFO_OP_ON BIT_7 /* FIFO Operational On */
2816+#define BMU_FIFO_OP_OFF BIT_6 /* FIFO Operational Off */
2817+#define BMU_FIFO_ENA BIT_5 /* Enable FIFO */
2818+#define BMU_FIFO_RST BIT_4 /* Reset FIFO */
2819+#define BMU_OP_ON BIT_3 /* BMU Operational On */
2820+#define BMU_OP_OFF BIT_2 /* BMU Operational Off */
2821+#define BMU_RST_CLR BIT_1 /* Clear BMU Reset (Enable) */
2822+#define BMU_RST_SET BIT_0 /* Set BMU Reset */
2823+
2824+#define BMU_CLR_RESET (BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR)
2825+#define BMU_OPER_INIT (BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START | \
2826+ BMU_FIFO_ENA | BMU_OP_ON)
2827+
2828+/* Tx BMU Control / Status Registers (Yukon-2) */
2829+ /* Bit 31: same as for Rx */
2830+ /* Bit 30..14: reserved */
2831+#define BMU_TX_IPIDINCR_ON BIT_13 /* Enable IP ID Increment */
2832+#define BMU_TX_IPIDINCR_OFF BIT_12 /* Disable IP ID Increment */
2833+#define BMU_TX_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segm. length mism. */
2834+ /* Bit 10..0: same as for Rx */
2835+
2836 /* Q_F 32 bit Flag Register */
2837 /* Bit 31..28: reserved */
2838 #define F_ALM_FULL BIT_27 /* Rx FIFO: almost full */
2839 #define F_EMPTY BIT_27 /* Tx FIFO: empty flag */
2840 #define F_FIFO_EOF BIT_26 /* Tag (EOF Flag) bit in FIFO */
2841 #define F_WM_REACHED BIT_25 /* Watermark reached */
2842- /* reserved */
2843+#define F_M_RX_RAM_DIS BIT_24 /* MAC Rx RAM Read Port disable */
2844 #define F_FIFO_LEVEL (0x1fL<<16) /* Bit 23..16: # of Qwords in FIFO */
2845 /* Bit 15..11: reserved */
2846 #define F_WATER_MARK 0x0007ffL /* Bit 10.. 0: Watermark */
2847@@ -1260,6 +1818,13 @@
2848 /* Bit 3: reserved */
2849 #define T3_VRAM_MSK 7 /* Bit 2.. 0: Virtual RAM Buffer Address */
2850
2851+/* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/
2852+/* PREF_UNIT_CTRL_REG 32 bit Prefetch Control register */
2853+#define PREF_UNIT_OP_ON BIT_3 /* prefetch unit operational */
2854+#define PREF_UNIT_OP_OFF BIT_2 /* prefetch unit not operational */
2855+#define PREF_UNIT_RST_CLR BIT_1 /* Clear Prefetch Unit Reset */
2856+#define PREF_UNIT_RST_SET BIT_0 /* Set Prefetch Unit Reset */
2857+
2858 /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
2859 /* RB_START 32 bit RAM Buffer Start Address */
2860 /* RB_END 32 bit RAM Buffer End Address */
2861@@ -1275,24 +1840,24 @@
2862 #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
2863
2864 /* RB_TST2 8 bit RAM Buffer Test Register 2 */
2865- /* Bit 7.. 4: reserved */
2866-#define RB_PC_DEC BIT_3S /* Packet Counter Decrem */
2867+ /* Bit 7.. 4: reserved */
2868+#define RB_PC_DEC BIT_3S /* Packet Counter Decrement */
2869 #define RB_PC_T_ON BIT_2S /* Packet Counter Test On */
2870-#define RB_PC_T_OFF BIT_1S /* Packet Counter Tst Off */
2871-#define RB_PC_INC BIT_0S /* Packet Counter Increm */
2872+#define RB_PC_T_OFF BIT_1S /* Packet Counter Test Off */
2873+#define RB_PC_INC BIT_0S /* Packet Counter Increment */
2874
2875 /* RB_TST1 8 bit RAM Buffer Test Register 1 */
2876 /* Bit 7: reserved */
2877 #define RB_WP_T_ON BIT_6S /* Write Pointer Test On */
2878 #define RB_WP_T_OFF BIT_5S /* Write Pointer Test Off */
2879-#define RB_WP_INC BIT_4S /* Write Pointer Increm */
2880+#define RB_WP_INC BIT_4S /* Write Pointer Increment */
2881 /* Bit 3: reserved */
2882 #define RB_RP_T_ON BIT_2S /* Read Pointer Test On */
2883 #define RB_RP_T_OFF BIT_1S /* Read Pointer Test Off */
2884-#define RB_RP_DEC BIT_0S /* Read Pointer Decrement */
2885+#define RB_RP_INC BIT_0S /* Read Pointer Increment */
2886
2887 /* RB_CTRL 8 bit RAM Buffer Control Register */
2888- /* Bit 7.. 6: reserved */
2889+ /* Bit 7.. 6: reserved */
2890 #define RB_ENA_STFWD BIT_5S /* Enable Store & Forward */
2891 #define RB_DIS_STFWD BIT_4S /* Disable Store & Forward */
2892 #define RB_ENA_OP_MD BIT_3S /* Enable Operation Mode */
2893@@ -1300,16 +1865,31 @@
2894 #define RB_RST_CLR BIT_1S /* Clear RAM Buf STM Reset */
2895 #define RB_RST_SET BIT_0S /* Set RAM Buf STM Reset */
2896
2897+/* Yukon-2 */
2898+ /* Bit 31..20: reserved */
2899+#define RB_CNT_DOWN BIT_19 /* Packet Counter Decrement */
2900+#define RB_CNT_TST_ON BIT_18 /* Packet Counter Test On */
2901+#define RB_CNT_TST_OFF BIT_17 /* Packet Counter Test Off */
2902+#define RB_CNT_UP BIT_16 /* Packet Counter Increment */
2903+ /* Bit 15: reserved */
2904+#define RB_WP_TST_ON BIT_14 /* Write Pointer Test On */
2905+#define RB_WP_TST_OFF BIT_13 /* Write Pointer Test Off */
2906+#define RB_WP_UP BIT_12 /* Write Pointer Increment */
2907+ /* Bit 11: reserved */
2908+#define RB_RP_TST_ON BIT_10 /* Read Pointer Test On */
2909+#define RB_RP_TST_OFF BIT_9 /* Read Pointer Test Off */
2910+#define RB_RP_UP BIT_8 /* Read Pointer Increment */
2911+
2912
2913 /* Receive and Transmit MAC FIFO Registers (GENESIS only) */
2914
2915 /* RX_MFF_EA 32 bit Receive MAC FIFO End Address */
2916-/* RX_MFF_WP 32 bit Receive MAC FIFO Write Pointer */
2917+/* RX_MFF_WP 32 bit Receive MAC FIFO Write Pointer */
2918 /* RX_MFF_RP 32 bit Receive MAC FIFO Read Pointer */
2919 /* RX_MFF_PC 32 bit Receive MAC FIFO Packet Counter */
2920 /* RX_MFF_LEV 32 bit Receive MAC FIFO Level */
2921 /* TX_MFF_EA 32 bit Transmit MAC FIFO End Address */
2922-/* TX_MFF_WP 32 bit Transmit MAC FIFO Write Pointer */
2923+/* TX_MFF_WP 32 bit Transmit MAC FIFO Write Pointer */
2924 /* TX_MFF_WSP 32 bit Transmit MAC FIFO WR Shadow Pointer */
2925 /* TX_MFF_RP 32 bit Transmit MAC FIFO Read Pointer */
2926 /* TX_MFF_PC 32 bit Transmit MAC FIFO Packet Cnt */
2927@@ -1359,9 +1939,9 @@
2928 /* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */
2929 /* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */
2930 /* Bit 7: reserved */
2931-#define MFF_WSP_T_ON BIT_6S /* Tx: Write Shadow Ptr TestOn */
2932-#define MFF_WSP_T_OFF BIT_5S /* Tx: Write Shadow Ptr TstOff */
2933-#define MFF_WSP_INC BIT_4S /* Tx: Write Shadow Ptr Increment */
2934+#define MFF_WSP_T_ON BIT_6S /* Tx: Write Shadow Pointer Test On */
2935+#define MFF_WSP_T_OFF BIT_5S /* Tx: Write Shadow Pointer Test Off */
2936+#define MFF_WSP_INC BIT_4S /* Tx: Write Shadow Pointer Increment */
2937 #define MFF_PC_DEC BIT_3S /* Packet Counter Decrement */
2938 #define MFF_PC_T_ON BIT_2S /* Packet Counter Test On */
2939 #define MFF_PC_T_OFF BIT_1S /* Packet Counter Test Off */
2940@@ -1372,7 +1952,7 @@
2941 /* Bit 7: reserved */
2942 #define MFF_WP_T_ON BIT_6S /* Write Pointer Test On */
2943 #define MFF_WP_T_OFF BIT_5S /* Write Pointer Test Off */
2944-#define MFF_WP_INC BIT_4S /* Write Pointer Increm */
2945+#define MFF_WP_INC BIT_4S /* Write Pointer Increment */
2946 /* Bit 3: reserved */
2947 #define MFF_RP_T_ON BIT_2S /* Read Pointer Test On */
2948 #define MFF_RP_T_OFF BIT_1S /* Read Pointer Test Off */
2949@@ -1391,12 +1971,16 @@
2950
2951 /* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */
2952 /* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */
2953+ /* Bit 7.. 3: reserved */
2954+#define LED_START BIT_2S /* Start Counter */
2955+#define LED_STOP BIT_1S /* Stop Counter */
2956+#define LED_STATE BIT_0S /* Rx/Tx: LED State, 1=LED On */
2957+
2958 /* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */
2959 /* Bit 7.. 3: reserved */
2960-#define LED_START BIT_2S /* Start Timer */
2961-#define LED_STOP BIT_1S /* Stop Timer */
2962-#define LED_STATE BIT_0S /* Rx/Tx: LED State, 1=LED on */
2963-#define LED_CLR_IRQ BIT_0S /* Lnk: Clear Link IRQ */
2964+#define LNK_START BIT_2S /* Start Counter */
2965+#define LNK_STOP BIT_1S /* Stop Counter */
2966+#define LNK_CLR_IRQ BIT_0S /* Clear Link IRQ */
2967
2968 /* RX_LED_TST 8 bit Receive LED Cnt Test Register */
2969 /* TX_LED_TST 8 bit Transmit LED Cnt Test Register */
2970@@ -1407,86 +1991,142 @@
2971 #define LED_T_STEP BIT_0S /* LED Counter Step */
2972
2973 /* LNK_LED_REG 8 bit Link LED Register */
2974- /* Bit 7.. 6: reserved */
2975+ /* Bit 7.. 6: reserved */
2976 #define LED_BLK_ON BIT_5S /* Link LED Blinking On */
2977 #define LED_BLK_OFF BIT_4S /* Link LED Blinking Off */
2978 #define LED_SYNC_ON BIT_3S /* Use Sync Wire to switch LED */
2979 #define LED_SYNC_OFF BIT_2S /* Disable Sync Wire Input */
2980-#define LED_ON BIT_1S /* switch LED on */
2981-#define LED_OFF BIT_0S /* switch LED off */
2982+#define LED_ON BIT_1S /* Switch LED On */
2983+#define LED_OFF BIT_0S /* Switch LED Off */
2984
2985 /* Receive and Transmit GMAC FIFO Registers (YUKON only) */
2986
2987 /* RX_GMF_EA 32 bit Rx GMAC FIFO End Address */
2988 /* RX_GMF_AF_THR 32 bit Rx GMAC FIFO Almost Full Thresh. */
2989-/* RX_GMF_WP 32 bit Rx GMAC FIFO Write Pointer */
2990-/* RX_GMF_WLEV 32 bit Rx GMAC FIFO Write Level */
2991-/* RX_GMF_RP 32 bit Rx GMAC FIFO Read Pointer */
2992-/* RX_GMF_RLEV 32 bit Rx GMAC FIFO Read Level */
2993+/* RX_GMF_WP 32 bit Rx GMAC FIFO Write Pointer */
2994+/* RX_GMF_WLEV 32 bit Rx GMAC FIFO Write Level */
2995+/* RX_GMF_RP 32 bit Rx GMAC FIFO Read Pointer */
2996+/* RX_GMF_RLEV 32 bit Rx GMAC FIFO Read Level */
2997 /* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */
2998 /* TX_GMF_AE_THR 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
2999-/* TX_GMF_WP 32 bit Tx GMAC FIFO Write Pointer */
3000-/* TX_GMF_WSP 32 bit Tx GMAC FIFO Write Shadow Ptr. */
3001-/* TX_GMF_WLEV 32 bit Tx GMAC FIFO Write Level */
3002-/* TX_GMF_RP 32 bit Tx GMAC FIFO Read Pointer */
3003-/* TX_GMF_RSTP 32 bit Tx GMAC FIFO Restart Pointer */
3004-/* TX_GMF_RLEV 32 bit Tx GMAC FIFO Read Level */
3005+/* TX_GMF_WP 32 bit Tx GMAC FIFO Write Pointer */
3006+/* TX_GMF_WSP 32 bit Tx GMAC FIFO Write Shadow Pointer */
3007+/* TX_GMF_WLEV 32 bit Tx GMAC FIFO Write Level */
3008+/* TX_GMF_RP 32 bit Tx GMAC FIFO Read Pointer */
3009+/* TX_GMF_RSTP 32 bit Tx GMAC FIFO Restart Pointer */
3010+/* TX_GMF_RLEV 32 bit Tx GMAC FIFO Read Level */
3011
3012 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
3013- /* Bits 31..15: reserved */
3014-#define GMF_WP_TST_ON BIT_14 /* Write Pointer Test On */
3015-#define GMF_WP_TST_OFF BIT_13 /* Write Pointer Test Off */
3016-#define GMF_WP_STEP BIT_12 /* Write Pointer Step/Increment */
3017+ /* Bit 31..28 reserved */
3018+#define RX_TRUNC_ON BIT_27 /* Enable Packet Truncation */
3019+#define RX_TRUNC_OFF BIT_26 /* Disable Packet Truncation */
3020+#define RX_VLAN_STRIP_ON BIT_25 /* Enable VLAN Stripping */
3021+#define RX_VLAN_STRIP_OFF BIT_24 /* Disable VLAN Stripping */
3022+ /* Bit 23..15 reserved */
3023+#define GMF_WP_TST_ON BIT_14 /* Write Pointer Test On */
3024+#define GMF_WP_TST_OFF BIT_13 /* Write Pointer Test Off */
3025+#define GMF_WP_STEP BIT_12 /* Write Pointer Step/Increment */
3026 /* Bit 11: reserved */
3027-#define GMF_RP_TST_ON BIT_10 /* Read Pointer Test On */
3028-#define GMF_RP_TST_OFF BIT_9 /* Read Pointer Test Off */
3029-#define GMF_RP_STEP BIT_8 /* Read Pointer Step/Increment */
3030-#define GMF_RX_F_FL_ON BIT_7 /* Rx FIFO Flush Mode On */
3031-#define GMF_RX_F_FL_OFF BIT_6 /* Rx FIFO Flush Mode Off */
3032-#define GMF_CLI_RX_FO BIT_5 /* Clear IRQ Rx FIFO Overrun */
3033-#define GMF_CLI_RX_FC BIT_4 /* Clear IRQ Rx Frame Complete */
3034-#define GMF_OPER_ON BIT_3 /* Operational Mode On */
3035-#define GMF_OPER_OFF BIT_2 /* Operational Mode Off */
3036-#define GMF_RST_CLR BIT_1 /* Clear GMAC FIFO Reset */
3037-#define GMF_RST_SET BIT_0 /* Set GMAC FIFO Reset */
3038-
3039-/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
3040- /* Bits 31..19: reserved */
3041-#define GMF_WSP_TST_ON BIT_18 /* Write Shadow Pointer Test On */
3042-#define GMF_WSP_TST_OFF BIT_17 /* Write Shadow Pointer Test Off */
3043-#define GMF_WSP_STEP BIT_16 /* Write Shadow Pointer Step/Increment */
3044- /* Bits 15..7: same as for RX_GMF_CTRL_T */
3045-#define GMF_CLI_TX_FU BIT_6 /* Clear IRQ Tx FIFO Underrun */
3046-#define GMF_CLI_TX_FC BIT_5 /* Clear IRQ Tx Frame Complete */
3047-#define GMF_CLI_TX_PE BIT_4 /* Clear IRQ Tx Parity Error */
3048+#define GMF_RP_TST_ON BIT_10 /* Read Pointer Test On */
3049+#define GMF_RP_TST_OFF BIT_9 /* Read Pointer Test Off */
3050+#define GMF_RP_STEP BIT_8 /* Read Pointer Step/Increment */
3051+#define GMF_RX_F_FL_ON BIT_7 /* Rx FIFO Flush Mode On */
3052+#define GMF_RX_F_FL_OFF BIT_6 /* Rx FIFO Flush Mode Off */
3053+#define GMF_CLI_RX_FO BIT_5 /* Clear IRQ Rx FIFO Overrun */
3054+#define GMF_CLI_RX_FC BIT_4 /* Clear IRQ Rx Frame Complete */
3055+#define GMF_OPER_ON BIT_3 /* Operational Mode On */
3056+#define GMF_OPER_OFF BIT_2 /* Operational Mode Off */
3057+#define GMF_RST_CLR BIT_1 /* Clear GMAC FIFO Reset */
3058+#define GMF_RST_SET BIT_0 /* Set GMAC FIFO Reset */
3059+
3060+/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test (YUKON and Yukon-2) */
3061+#define TX_STFW_DIS BIT_31 /* Disable Store & Forward (Yukon-EC Ultra) */
3062+#define TX_STFW_ENA BIT_30 /* Enable Store & Forward (Yukon-EC Ultra) */
3063+ /* Bits 29..26: reserved */
3064+#define TX_VLAN_TAG_ON BIT_25 /* Enable VLAN tagging */
3065+#define TX_VLAN_TAG_OFF BIT_24 /* Disable VLAN tagging */
3066+#define TX_PCI_JUM_ENA BIT_23 /* Enable PCI Jumbo Mode (Yukon-EC Ultra) */
3067+#define TX_PCI_JUM_DIS BIT_22 /* Disable PCI Jumbo Mode (Yukon-EC Ultra) */
3068+ /* Bits 21..19: reserved */
3069+#define GMF_WSP_TST_ON BIT_18 /* Write Shadow Pointer Test On */
3070+#define GMF_WSP_TST_OFF BIT_17 /* Write Shadow Pointer Test Off */
3071+#define GMF_WSP_STEP BIT_16 /* Write Shadow Pointer Step/Increment */
3072+ /* Bits 15..8: same as for RX_GMF_CTRL_T */
3073+ /* Bit 7: reserved */
3074+#define GMF_CLI_TX_FU BIT_6 /* Clear IRQ Tx FIFO Underrun */
3075+#define GMF_CLI_TX_FC BIT_5 /* Clear IRQ Tx Frame Complete */
3076+#define GMF_CLI_TX_PE BIT_4 /* Clear IRQ Tx Parity Error */
3077 /* Bits 3..0: same as for RX_GMF_CTRL_T */
3078
3079 #define GMF_RX_CTRL_DEF (GMF_OPER_ON | GMF_RX_F_FL_ON)
3080 #define GMF_TX_CTRL_DEF GMF_OPER_ON
3081
3082+#define RX_GMF_AF_THR_MIN 0x0c /* Rx GMAC FIFO Almost Full Thresh. min. */
3083 #define RX_GMF_FL_THR_DEF 0x0a /* Rx GMAC FIFO Flush Threshold default */
3084
3085 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
3086- /* Bit 7.. 3: reserved */
3087-#define GMT_ST_START BIT_2S /* Start Time Stamp Timer */
3088-#define GMT_ST_STOP BIT_1S /* Stop Time Stamp Timer */
3089-#define GMT_ST_CLR_IRQ BIT_0S /* Clear Time Stamp Timer IRQ */
3090-
3091+ /* Bit 7.. 3: reserved */
3092+#define GMT_ST_START BIT_2S /* Start Time Stamp Timer */
3093+#define GMT_ST_STOP BIT_1S /* Stop Time Stamp Timer */
3094+#define GMT_ST_CLR_IRQ BIT_0S /* Clear Time Stamp Timer IRQ */
3095+
3096+/* POLL_CTRL 32 bit Polling Unit control register (Yukon-2 only) */
3097+ /* Bit 31.. 6: reserved */
3098+#define PC_CLR_IRQ_CHK BIT_5 /* Clear IRQ Check */
3099+#define PC_POLL_RQ BIT_4 /* Poll Request Start */
3100+#define PC_POLL_OP_ON BIT_3 /* Operational Mode On */
3101+#define PC_POLL_OP_OFF BIT_2 /* Operational Mode Off */
3102+#define PC_POLL_RST_CLR BIT_1 /* Clear Polling Unit Reset (Enable) */
3103+#define PC_POLL_RST_SET BIT_0 /* Set Polling Unit Reset */
3104+
3105+
3106+/* The bit definition of the following registers is still missing! */
3107+/* B28_Y2_SMB_CONFIG 32 bit ASF SMBus Config Register */
3108+/* B28_Y2_SMB_CSD_REG 32 bit ASF SMB Control/Status/Data */
3109+/* B28_Y2_ASF_IRQ_V_BASE 32 bit ASF IRQ Vector Base */
3110+
3111+/* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */
3112+/* This register is used by the host driver software */
3113+ /* Bit 31.. 5 reserved */
3114+#define Y2_ASF_OS_PRES BIT_4S /* ASF operation system present */
3115+#define Y2_ASF_RESET BIT_3S /* ASF system in reset state */
3116+#define Y2_ASF_RUNNING BIT_2S /* ASF system operational */
3117+#define Y2_ASF_CLR_HSTI BIT_1S /* Clear ASF IRQ */
3118+#define Y2_ASF_IRQ BIT_0S /* Issue an IRQ to ASF system */
3119+
3120+#define Y2_ASF_UC_STATE (3<<2) /* ASF uC State */
3121+#define Y2_ASF_CLK_HALT 0 /* ASF system clock stopped */
3122+
3123+/* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */
3124+/* This register is used by the ASF firmware */
3125+ /* Bit 31.. 2 reserved */
3126+#define Y2_ASF_CLR_ASFI BIT_1 /* Clear host IRQ */
3127+#define Y2_ASF_HOST_IRQ BIT_0 /* Issue an IRQ to HOST system */
3128+
3129+
3130+/* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
3131+ /* Bit 7.. 5: reserved */
3132+#define SC_STAT_CLR_IRQ BIT_4 /* Status Burst IRQ clear */
3133+#define SC_STAT_OP_ON BIT_3 /* Operational Mode On */
3134+#define SC_STAT_OP_OFF BIT_2 /* Operational Mode Off */
3135+#define SC_STAT_RST_CLR BIT_1 /* Clear Status Unit Reset (Enable) */
3136+#define SC_STAT_RST_SET BIT_0 /* Set Status Unit Reset */
3137+
3138 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
3139 /* Bits 31.. 8: reserved */
3140-#define GMC_H_BURST_ON BIT_7 /* Half Duplex Burst Mode On */
3141-#define GMC_H_BURST_OFF BIT_6 /* Half Duplex Burst Mode Off */
3142-#define GMC_F_LOOPB_ON BIT_5 /* FIFO Loopback On */
3143-#define GMC_F_LOOPB_OFF BIT_4 /* FIFO Loopback Off */
3144-#define GMC_PAUSE_ON BIT_3 /* Pause On */
3145-#define GMC_PAUSE_OFF BIT_2 /* Pause Off */
3146-#define GMC_RST_CLR BIT_1 /* Clear GMAC Reset */
3147-#define GMC_RST_SET BIT_0 /* Set GMAC Reset */
3148+#define GMC_H_BURST_ON BIT_7 /* Half Duplex Burst Mode On */
3149+#define GMC_H_BURST_OFF BIT_6 /* Half Duplex Burst Mode Off */
3150+#define GMC_F_LOOPB_ON BIT_5 /* FIFO Loopback On */
3151+#define GMC_F_LOOPB_OFF BIT_4 /* FIFO Loopback Off */
3152+#define GMC_PAUSE_ON BIT_3 /* Pause On */
3153+#define GMC_PAUSE_OFF BIT_2 /* Pause Off */
3154+#define GMC_RST_CLR BIT_1 /* Clear GMAC Reset */
3155+#define GMC_RST_SET BIT_0 /* Set GMAC Reset */
3156
3157 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
3158 /* Bits 31..29: reserved */
3159 #define GPC_SEL_BDT BIT_28 /* Select Bi-Dir. Transfer for MDC/MDIO */
3160-#define GPC_INT_POL_HI BIT_27 /* IRQ Polarity is Active HIGH */
3161+#define GPC_INT_POL BIT_27 /* IRQ Polarity is Active Low */
3162 #define GPC_75_OHM BIT_26 /* Use 75 Ohm Termination instead of 50 */
3163 #define GPC_DIS_FC BIT_25 /* Disable Automatic Fiber/Copper Detection */
3164 #define GPC_DIS_SLEEP BIT_24 /* Disable Energy Detect */
3165@@ -1510,6 +2150,13 @@
3166 #define GPC_RST_CLR BIT_1 /* Clear GPHY Reset */
3167 #define GPC_RST_SET BIT_0 /* Set GPHY Reset */
3168
3169+/* Yukon-EC Ultra only */
3170+#define GPC_PD_125M_CLK_OFF BIT_5 /* Disable Power Down Clock 125 MHz */
3171+#define GPC_PD_125M_CLK_ON BIT_4 /* Enable Power Down Clock 125 MHz */
3172+#define GPC_DPLL_RST_SET BIT_3 /* Set GPHY's DPLL Reset */
3173+#define GPC_DPLL_RST_CLR BIT_2 /* Clear GPHY's DPLL Reset */
3174+ /* (DPLL = Digital Phase Lock Loop) */
3175+
3176 #define GPC_HWCFG_GMII_COP (GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | \
3177 GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
3178
3179@@ -1540,14 +2187,14 @@
3180
3181 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
3182 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
3183-#define GM_IS_TX_CO_OV BIT_5 /* Transmit Counter Overflow IRQ */
3184-#define GM_IS_RX_CO_OV BIT_4 /* Receive Counter Overflow IRQ */
3185-#define GM_IS_TX_FF_UR BIT_3 /* Transmit FIFO Underrun */
3186-#define GM_IS_TX_COMPL BIT_2 /* Frame Transmission Complete */
3187-#define GM_IS_RX_FF_OR BIT_1 /* Receive FIFO Overrun */
3188-#define GM_IS_RX_COMPL BIT_0 /* Frame Reception Complete */
3189+#define GM_IS_RX_CO_OV BIT_5S /* Receive Counter Overflow IRQ */
3190+#define GM_IS_TX_CO_OV BIT_4S /* Transmit Counter Overflow IRQ */
3191+#define GM_IS_TX_FF_UR BIT_3S /* Transmit FIFO Underrun */
3192+#define GM_IS_TX_COMPL BIT_2S /* Frame Transmission Complete */
3193+#define GM_IS_RX_FF_OR BIT_1S /* Receive FIFO Overrun */
3194+#define GM_IS_RX_COMPL BIT_0S /* Frame Reception Complete */
3195
3196-#define GMAC_DEF_MSK (GM_IS_TX_CO_OV | GM_IS_RX_CO_OV | \
3197+#define GMAC_DEF_MSK (GM_IS_RX_CO_OV | GM_IS_TX_CO_OV | \
3198 GM_IS_TX_FF_UR)
3199
3200 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
3201@@ -1579,15 +2226,19 @@
3202
3203 #define WOL_CTL_DEFAULT \
3204 (WOL_CTL_DIS_PME_ON_LINK_CHG | \
3205- WOL_CTL_DIS_PME_ON_PATTERN | \
3206- WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
3207- WOL_CTL_DIS_LINK_CHG_UNIT | \
3208- WOL_CTL_DIS_PATTERN_UNIT | \
3209- WOL_CTL_DIS_MAGIC_PKT_UNIT)
3210+ WOL_CTL_DIS_PME_ON_PATTERN | \
3211+ WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
3212+ WOL_CTL_DIS_LINK_CHG_UNIT | \
3213+ WOL_CTL_DIS_PATTERN_UNIT | \
3214+ WOL_CTL_DIS_MAGIC_PKT_UNIT)
3215
3216 /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
3217 #define WOL_CTL_PATT_ENA(x) (BIT_0 << (x))
3218
3219+/* WOL_PATT_PME 8 bit WOL PME Match Enable (Yukon-2) */
3220+#define WOL_PATT_FORCE_PME BIT_7 /* Generates a PME */
3221+#define WOL_PATT_MATCH_PME_ALL 0x7f
3222+
3223 #define SK_NUM_WOL_PATTERN 7
3224 #define SK_PATTERN_PER_WORD 4
3225 #define SK_BITMASK_PATTERN 7
3226@@ -1597,26 +2248,28 @@
3227 #define WOL_LENGTH_SHIFT 8
3228
3229
3230+/* typedefs ******************************************************************/
3231+
3232 /* Receive and Transmit Descriptors ******************************************/
3233
3234 /* Transmit Descriptor struct */
3235 typedef struct s_HwTxd {
3236 SK_U32 volatile TxCtrl; /* Transmit Buffer Control Field */
3237 SK_U32 TxNext; /* Physical Address Pointer to the next TxD */
3238- SK_U32 TxAdrLo; /* Physical Tx Buffer Address lower dword */
3239- SK_U32 TxAdrHi; /* Physical Tx Buffer Address upper dword */
3240+ SK_U32 TxAdrLo; /* Physical Tx Buffer Address lower DWord */
3241+ SK_U32 TxAdrHi; /* Physical Tx Buffer Address upper DWord */
3242 SK_U32 TxStat; /* Transmit Frame Status Word */
3243-#ifndef SK_USE_REV_DESC
3244+#ifndef SK_USE_REV_DESC
3245 SK_U16 TxTcpOffs; /* TCP Checksum Calculation Start Value */
3246 SK_U16 TxRes1; /* 16 bit reserved field */
3247 SK_U16 TxTcpWp; /* TCP Checksum Write Position */
3248 SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */
3249-#else /* SK_USE_REV_DESC */
3250+#else /* SK_USE_REV_DESC */
3251 SK_U16 TxRes1; /* 16 bit reserved field */
3252 SK_U16 TxTcpOffs; /* TCP Checksum Calculation Start Value */
3253 SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */
3254 SK_U16 TxTcpWp; /* TCP Checksum Write Position */
3255-#endif /* SK_USE_REV_DESC */
3256+#endif /* SK_USE_REV_DESC */
3257 SK_U32 TxRes2; /* 32 bit reserved field */
3258 } SK_HWTXD;
3259
3260@@ -1624,33 +2277,266 @@
3261 typedef struct s_HwRxd {
3262 SK_U32 volatile RxCtrl; /* Receive Buffer Control Field */
3263 SK_U32 RxNext; /* Physical Address Pointer to the next RxD */
3264- SK_U32 RxAdrLo; /* Physical Rx Buffer Address lower dword */
3265- SK_U32 RxAdrHi; /* Physical Rx Buffer Address upper dword */
3266+ SK_U32 RxAdrLo; /* Physical Rx Buffer Address lower DWord */
3267+ SK_U32 RxAdrHi; /* Physical Rx Buffer Address upper DWord */
3268 SK_U32 RxStat; /* Receive Frame Status Word */
3269 SK_U32 RxTiSt; /* Receive Time Stamp (from XMAC on GENESIS) */
3270-#ifndef SK_USE_REV_DESC
3271- SK_U16 RxTcpSum1; /* TCP Checksum 1 */
3272- SK_U16 RxTcpSum2; /* TCP Checksum 2 */
3273+#ifndef SK_USE_REV_DESC
3274+ SK_U16 RxTcpSum1; /* Rx TCP Checksum 1 */
3275+ SK_U16 RxTcpSum2; /* Rx TCP Checksum 2 */
3276 SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */
3277 SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */
3278-#else /* SK_USE_REV_DESC */
3279- SK_U16 RxTcpSum2; /* TCP Checksum 2 */
3280- SK_U16 RxTcpSum1; /* TCP Checksum 1 */
3281+#else /* SK_USE_REV_DESC */
3282+ SK_U16 RxTcpSum2; /* Rx TCP Checksum 2 */
3283+ SK_U16 RxTcpSum1; /* Rx TCP Checksum 1 */
3284 SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */
3285 SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */
3286-#endif /* SK_USE_REV_DESC */
3287+#endif /* SK_USE_REV_DESC */
3288 } SK_HWRXD;
3289
3290 /*
3291 * Drivers which use the reverse descriptor feature (PCI_OUR_REG_2)
3292 * should set the define SK_USE_REV_DESC.
3293- * Structures are 'normaly' not endianess dependent. But in
3294- * this case the SK_U16 fields are bound to bit positions inside the
3295- * descriptor. RxTcpSum1 e.g. must start at bit 0 within the 6.th DWord.
3296+ * Structures are 'normally' not endianess dependent. But in this case
3297+ * the SK_U16 fields are bound to bit positions inside the descriptor.
3298+ * RxTcpSum1 e.g. must start at bit 0 within the 7.th DWord.
3299 * The bit positions inside a DWord are of course endianess dependent and
3300- * swaps if the DWord is swapped by the hardware.
3301+ * swap if the DWord is swapped by the hardware.
3302 */
3303
3304+/* YUKON-2 descriptors ******************************************************/
3305+
3306+typedef struct _TxChksum {
3307+#ifndef SK_USE_REV_DESC
3308+ SK_U16 TxTcpWp; /* TCP Checksum Write Position */
3309+ SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */
3310+#else /* SK_USE_REV_DESC */
3311+ SK_U16 TxTcpSp; /* TCP Checksum Calculation Start Position */
3312+ SK_U16 TxTcpWp; /* TCP Checksum Write Position */
3313+#endif /* SK_USE_REV_DESC */
3314+} SK_HWTXCS;
3315+
3316+typedef struct _LargeSend {
3317+#ifndef SK_USE_REV_DESC
3318+ SK_U16 Length; /* Large Send Segment Length */
3319+ SK_U16 Reserved; /* reserved */
3320+#else /* SK_USE_REV_DESC */
3321+ SK_U16 Reserved; /* reserved */
3322+ SK_U16 Length; /* Large Send Segment Length */
3323+#endif /* SK_USE_REV_DESC */
3324+} SK_HWTXLS;
3325+
3326+typedef union u_HwTxBuf {
3327+ SK_U16 BufLen; /* Tx Buffer Length */
3328+ SK_U16 VlanTag; /* VLAN Tag */
3329+ SK_U16 InitCsum; /* Init. Checksum */
3330+} SK_HWTXBUF;
3331+
3332+/* Tx List Element structure */
3333+typedef struct s_HwLeTx {
3334+ union {
3335+ SK_U32 BufAddr; /* Tx LE Buffer Address high/low */
3336+ SK_HWTXCS ChkSum; /* Tx LE TCP Checksum parameters */
3337+ SK_HWTXLS LargeSend;/* Large Send length */
3338+ } TxUn;
3339+#ifndef SK_USE_REV_DESC
3340+ SK_HWTXBUF Send;
3341+ SK_U8 ControlFlags; /* Tx LE Control field or Lock Number */
3342+ SK_U8 Opcode; /* Tx LE Opcode field */
3343+#else /* SK_USE_REV_DESC */
3344+ SK_U8 Opcode; /* Tx LE Opcode field */
3345+ SK_U8 ControlFlags; /* Tx LE Control field or Lock Number */
3346+ SK_HWTXBUF Send;
3347+#endif /* SK_USE_REV_DESC */
3348+} SK_HWLETX;
3349+
3350+typedef struct _RxChkSum{
3351+#ifndef SK_USE_REV_DESC
3352+ SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */
3353+ SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */
3354+#else /* SK_USE_REV_DESC */
3355+ SK_U16 RxTcpSp2; /* TCP Checksum Calculation Start Position 2 */
3356+ SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */
3357+#endif /* SK_USE_REV_DESC */
3358+} SK_HWRXCS;
3359+
3360+/* Rx List Element structure */
3361+typedef struct s_HwLeRx {
3362+ union {
3363+ SK_U32 BufAddr; /* Rx LE Buffer Address high/low */
3364+ SK_HWRXCS ChkSum; /* Rx LE TCP Checksum parameters */
3365+ } RxUn;
3366+#ifndef SK_USE_REV_DESC
3367+ SK_U16 BufferLength; /* Rx LE Buffer Length field */
3368+ SK_U8 ControlFlags; /* Rx LE Control field */
3369+ SK_U8 Opcode; /* Rx LE Opcode field */
3370+#else /* SK_USE_REV_DESC */
3371+ SK_U8 Opcode; /* Rx LE Opcode field */
3372+ SK_U8 ControlFlags; /* Rx LE Control field */
3373+ SK_U16 BufferLength; /* Rx LE Buffer Length field */
3374+#endif /* SK_USE_REV_DESC */
3375+} SK_HWLERX;
3376+
3377+typedef struct s_StRxTCPChkSum {
3378+#ifndef SK_USE_REV_DESC
3379+ SK_U16 RxTCPSum1; /* Rx TCP Checksum 1 */
3380+ SK_U16 RxTCPSum2; /* Rx TCP Checksum 2 */
3381+#else /* SK_USE_REV_DESC */
3382+ SK_U16 RxTCPSum2; /* Rx TCP Checksum 2 */
3383+ SK_U16 RxTCPSum1; /* Rx TCP Checksum 1 */
3384+#endif /* SK_USE_REV_DESC */
3385+} SK_HWSTCS;
3386+
3387+typedef struct s_StRxRssFlags {
3388+#ifndef SK_USE_REV_DESC
3389+ SK_U8 FlagField; /* contains TCP and IP flags */
3390+ SK_U8 reserved; /* reserved */
3391+#else /* SK_USE_REV_DESC */
3392+ SK_U8 reserved; /* reserved */
3393+ SK_U8 FlagField; /* contains TCP and IP flags */
3394+#endif /* SK_USE_REV_DESC */
3395+} SK_HWSTRSS;
3396+
3397+/* bit definition of RSS LE bit 32/33 (SK_HWSTRSS.FlagField) */
3398+ /* bit 7..2 reserved */
3399+#define RSS_TCP_FLAG BIT_1S /* RSS value related to TCP area */
3400+#define RSS_IP_FLAG BIT_0S /* RSS value related to IP area */
3401+/* StRxRssValue is valid if at least RSS_IP_FLAG is set */
3402+/* For protocol errors or other protocols an empty RSS LE is generated */
3403+
3404+typedef union u_HwStBuf {
3405+ SK_U16 BufLen; /* Rx Buffer Length */
3406+ SK_U16 VlanTag; /* VLAN Tag */
3407+ SK_U16 StTxStatHi; /* Tx Queue Status (high) */
3408+ SK_HWSTRSS Rss; /* Flag Field for TCP and IP protocol */
3409+} SK_HWSTBUF;
3410+
3411+/* Status List Element structure */
3412+typedef struct s_HwLeSt {
3413+ union {
3414+ SK_U32 StRxStatWord; /* Rx Status Dword */
3415+ SK_U32 StRxTimeStamp; /* Rx Timestamp */
3416+ SK_HWSTCS StRxTCPCSum; /* Rx TCP Checksum */
3417+ SK_U32 StTxStatLow; /* Tx Queue Status (low) */
3418+ SK_U32 StRxRssValue; /* Rx RSS value */
3419+ } StUn;
3420+#ifndef SK_USE_REV_DESC
3421+ SK_HWSTBUF Stat;
3422+ SK_U8 Link; /* Status LE Link field */
3423+ SK_U8 Opcode; /* Status LE Opcode field */
3424+#else /* SK_USE_REV_DESC */
3425+ SK_U8 Opcode; /* Status LE Opcode field */
3426+ SK_U8 Link; /* Status LE Link field */
3427+ SK_HWSTBUF Stat;
3428+#endif /* SK_USE_REV_DESC */
3429+} SK_HWLEST;
3430+
3431+/* Special Action List Element */
3432+typedef struct s_HwLeSa {
3433+#ifndef SK_USE_REV_DESC
3434+ SK_U16 TxAIdxVld; /* Special Action LE TxA Put Index field */
3435+ SK_U16 TxSIdxVld; /* Special Action LE TxS Put Index field */
3436+ SK_U16 RxIdxVld; /* Special Action LE Rx Put Index field */
3437+ SK_U8 Link; /* Special Action LE Link field */
3438+ SK_U8 Opcode; /* Special Action LE Opcode field */
3439+#else /* SK_USE_REV_DESC */
3440+ SK_U16 TxSIdxVld; /* Special Action LE TxS Put Index field */
3441+ SK_U16 TxAIdxVld; /* Special Action LE TxA Put Index field */
3442+ SK_U8 Opcode; /* Special Action LE Opcode field */
3443+ SK_U8 Link; /* Special Action LE Link field */
3444+ SK_U16 RxIdxVld; /* Special Action LE Rx Put Index field */
3445+#endif /* SK_USE_REV_DESC */
3446+} SK_HWLESA;
3447+
3448+/* Common List Element union */
3449+typedef union u_HwLeTxRxSt {
3450+ /* Transmit List Element Structure */
3451+ SK_HWLETX Tx;
3452+ /* Receive List Element Structure */
3453+ SK_HWLERX Rx;
3454+ /* Status List Element Structure */
3455+ SK_HWLEST St;
3456+ /* Special Action List Element Structure */
3457+ SK_HWLESA Sa;
3458+ /* Full List Element */
3459+ SK_U64 Full;
3460+} SK_HWLE;
3461+
3462+/* mask and shift value to get Tx async queue status for port 1 */
3463+#define STLE_TXA1_MSKL 0x00000fff
3464+#define STLE_TXA1_SHIFTL 0
3465+
3466+/* mask and shift value to get Tx sync queue status for port 1 */
3467+#define STLE_TXS1_MSKL 0x00fff000
3468+#define STLE_TXS1_SHIFTL 12
3469+
3470+/* mask and shift value to get Tx async queue status for port 2 */
3471+#define STLE_TXA2_MSKL 0xff000000
3472+#define STLE_TXA2_SHIFTL 24
3473+#define STLE_TXA2_MSKH 0x000f
3474+/* this one shifts up */
3475+#define STLE_TXA2_SHIFTH 8
3476+
3477+/* mask and shift value to get Tx sync queue status for port 2 */
3478+#define STLE_TXS2_MSKL 0x00000000
3479+#define STLE_TXS2_SHIFTL 0
3480+#define STLE_TXS2_MSKH 0xfff0
3481+#define STLE_TXS2_SHIFTH 4
3482+
3483+/* YUKON-2 bit values */
3484+#define HW_OWNER BIT_7
3485+#define SW_OWNER 0
3486+
3487+#define PU_PUTIDX_VALID BIT_12
3488+
3489+/* YUKON-2 Control flags */
3490+#define UDPTCP BIT_0S
3491+#define CALSUM BIT_1S
3492+#define WR_SUM BIT_2S
3493+#define INIT_SUM BIT_3S
3494+#define LOCK_SUM BIT_4S
3495+#define INS_VLAN BIT_5S
3496+#define FRC_STAT BIT_6S
3497+#define EOP BIT_7S
3498+
3499+#define TX_LOCK BIT_8S
3500+#define BUF_SEND BIT_9S
3501+#define PACKET_SEND BIT_10S
3502+
3503+#define NO_WARNING BIT_14S
3504+#define NO_UPDATE BIT_15S
3505+
3506+/* YUKON-2 Rx/Tx opcodes defines */
3507+#define OP_TCPWRITE 0x11
3508+#define OP_TCPSTART 0x12
3509+#define OP_TCPINIT 0x14
3510+#define OP_TCPLCK 0x18
3511+#define OP_TCPCHKSUM OP_TCPSTART
3512+#define OP_TCPIS (OP_TCPINIT | OP_TCPSTART)
3513+#define OP_TCPLW (OP_TCPLCK | OP_TCPWRITE)
3514+#define OP_TCPLSW (OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE)
3515+#define OP_TCPLISW (OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE)
3516+#define OP_ADDR64 0x21
3517+#define OP_VLAN 0x22
3518+#define OP_ADDR64VLAN (OP_ADDR64 | OP_VLAN)
3519+#define OP_LRGLEN 0x24
3520+#define OP_LRGLENVLAN (OP_LRGLEN | OP_VLAN)
3521+#define OP_BUFFER 0x40
3522+#define OP_PACKET 0x41
3523+#define OP_LARGESEND 0x43
3524+
3525+/* YUKON-2 STATUS opcodes defines */
3526+#define OP_RXSTAT 0x60
3527+#define OP_RXTIMESTAMP 0x61
3528+#define OP_RXVLAN 0x62
3529+#define OP_RXCHKS 0x64
3530+#define OP_RXCHKSVLAN (OP_RXCHKS | OP_RXVLAN)
3531+#define OP_RXTIMEVLAN (OP_RXTIMESTAMP | OP_RXVLAN)
3532+#define OP_RSS_HASH 0x65
3533+#define OP_TXINDEXLE 0x68
3534+
3535+/* YUKON-2 SPECIAL opcodes defines */
3536+#define OP_PUTIDX 0x70
3537
3538 /* Descriptor Bit Definition */
3539 /* TxCtrl Transmit Buffer Control Field */
3540@@ -1685,6 +2571,10 @@
3541
3542 /* macros ********************************************************************/
3543
3544+/* Macro for accessing the key registers */
3545+#define RSS_KEY_ADDR(Port, KeyIndex) \
3546+ ((B4_RSS_KEY | ( ((Port) == 0) ? 0 : 0x80)) + (KeyIndex))
3547+
3548 /* Receive and Transmit Queues */
3549 #define Q_R1 0x0000 /* Receive Queue 1 */
3550 #define Q_R2 0x0080 /* Receive Queue 2 */
3551@@ -1693,6 +2583,10 @@
3552 #define Q_XS2 0x0300 /* Synchronous Transmit Queue 2 */
3553 #define Q_XA2 0x0380 /* Asynchronous Transmit Queue 2 */
3554
3555+#define Q_ASF_R1 0x100 /* ASF Rx Queue 1 */
3556+#define Q_ASF_R2 0x180 /* ASF Rx Queue 2 */
3557+#define Q_ASF_T1 0x140 /* ASF Tx Queue 1 */
3558+#define Q_ASF_T2 0x1c0 /* ASF Tx Queue 2 */
3559 /*
3560 * Macro Q_ADDR()
3561 *
3562@@ -1704,11 +2598,27 @@
3563 * Offs Queue register offset.
3564 * Values: Q_D, Q_DA_L ... Q_T2, Q_T3
3565 *
3566- * usage SK_IN32(pAC, Q_ADDR(Q_R2, Q_BC), pVal)
3567+ * usage SK_IN32(IoC, Q_ADDR(Q_R2, Q_BC), pVal)
3568 */
3569 #define Q_ADDR(Queue, Offs) (B8_Q_REGS + (Queue) + (Offs))
3570
3571 /*
3572+ * Macro Y2_PREF_Q_ADDR()
3573+ *
3574+ * Use this macro to access the Prefetch Units of the receive and
3575+ * transmit queues of Yukon-2.
3576+ *
3577+ * para:
3578+ * Queue Queue to access.
3579+ * Values: Q_R1, Q_R2, Q_XS1, Q_XA1, Q_XS2, Q_XA2,
3580+ * Offs Queue register offset.
3581+ * Values: PREF_UNIT_CTRL_REG ... PREF_UNIT_FIFO_LEV_REG
3582+ *
3583+ * usage SK_IN16(IoC, Y2_Q_ADDR(Q_R2, PREF_UNIT_GET_IDX_REG), pVal)
3584+ */
3585+#define Y2_PREF_Q_ADDR(Queue, Offs) (Y2_B8_PREF_REGS + (Queue) + (Offs))
3586+
3587+/*
3588 * Macro RB_ADDR()
3589 *
3590 * Use this macro to access the RAM Buffer Registers.
3591@@ -1719,14 +2629,14 @@
3592 * Offs Queue register offset.
3593 * Values: RB_START, RB_END ... RB_LEV, RB_CTRL
3594 *
3595- * usage SK_IN32(pAC, RB_ADDR(Q_R2, RB_RP), pVal)
3596+ * usage SK_IN32(IoC, RB_ADDR(Q_R2, RB_RP), pVal)
3597 */
3598 #define RB_ADDR(Queue, Offs) (B16_RAM_REGS + (Queue) + (Offs))
3599
3600
3601 /* MAC Related Registers */
3602-#define MAC_1 0 /* belongs to the port near the slot */
3603-#define MAC_2 1 /* belongs to the port far away from the slot */
3604+#define MAC_1 0 /* 1st port */
3605+#define MAC_2 1 /* 2nd port */
3606
3607 /*
3608 * Macro MR_ADDR()
3609@@ -1740,19 +2650,10 @@
3610 * Values: RX_MFF_EA, RX_MFF_WP ... LNK_LED_REG,
3611 * TX_MFF_EA, TX_MFF_WP ... TX_LED_TST
3612 *
3613- * usage SK_IN32(pAC, MR_ADDR(MAC_1, TX_MFF_EA), pVal)
3614+ * usage SK_IN32(IoC, MR_ADDR(MAC_1, TX_MFF_EA), pVal)
3615 */
3616 #define MR_ADDR(Mac, Offs) (((Mac) << 7) + (Offs))
3617
3618-#ifdef SK_LITTLE_ENDIAN
3619-#define XM_WORD_LO 0
3620-#define XM_WORD_HI 1
3621-#else /* !SK_LITTLE_ENDIAN */
3622-#define XM_WORD_LO 1
3623-#define XM_WORD_HI 0
3624-#endif /* !SK_LITTLE_ENDIAN */
3625-
3626-
3627 /*
3628 * macros to access the XMAC (GENESIS only)
3629 *
3630@@ -1777,22 +2678,31 @@
3631 #define XMA(Mac, Reg) \
3632 ((BASE_XMAC_1 + (Mac) * (BASE_XMAC_2 - BASE_XMAC_1)) | ((Reg) << 1))
3633
3634-#define XM_IN16(IoC, Mac, Reg, pVal) \
3635- SK_IN16((IoC), XMA((Mac), (Reg)), (pVal))
3636+#define XM_IN16(IoC, Mac, Reg, pVal) \
3637+ SK_IN16(IoC, XMA(Mac, Reg), pVal)
3638+
3639+#define XM_OUT16(IoC, Mac, Reg, Val) \
3640+ SK_OUT16(IoC, XMA(Mac, Reg), Val)
3641+
3642+#ifdef SK_LITTLE_ENDIAN
3643
3644-#define XM_OUT16(IoC, Mac, Reg, Val) \
3645- SK_OUT16((IoC), XMA((Mac), (Reg)), (Val))
3646+#define XM_IN32(IoC, Mac, Reg, pVal) { \
3647+ SK_IN16(IoC, XMA(Mac, Reg), (SK_U16 SK_FAR *)(pVal)); \
3648+ SK_IN16(IoC, XMA(Mac, (Reg) + 2), (SK_U16 SK_FAR *)(pVal) + 1); \
3649+}
3650+
3651+#else /* !SK_LITTLE_ENDIAN */
3652
3653-#define XM_IN32(IoC, Mac, Reg, pVal) { \
3654- SK_IN16((IoC), XMA((Mac), (Reg)), \
3655- (SK_U16 SK_FAR*)&((SK_U16 SK_FAR*)(pVal))[XM_WORD_LO]); \
3656- SK_IN16((IoC), XMA((Mac), (Reg+2)), \
3657- (SK_U16 SK_FAR*)&((SK_U16 SK_FAR*)(pVal))[XM_WORD_HI]); \
3658+#define XM_IN32(IoC, Mac, Reg, pVal) { \
3659+ SK_IN16(IoC, XMA(Mac, Reg), (SK_U16 SK_FAR *)(pVal) + 1); \
3660+ SK_IN16(IoC, XMA(Mac, (Reg) + 2), (SK_U16 SK_FAR *)(pVal)); \
3661 }
3662
3663+#endif /* !SK_LITTLE_ENDIAN */
3664+
3665 #define XM_OUT32(IoC, Mac, Reg, Val) { \
3666- SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16)((Val) & 0xffffL)); \
3667- SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16)(((Val) >> 16) & 0xffffL));\
3668+ SK_OUT16(IoC, XMA(Mac, Reg), (SK_U16)((Val) & 0xffffL)); \
3669+ SK_OUT16(IoC, XMA(Mac, (Reg) + 2), (SK_U16)(((Val) >> 16) & 0xffffL)); \
3670 }
3671
3672 /* Remember: we are always writing to / reading from LITTLE ENDIAN memory */
3673@@ -1802,13 +2712,13 @@
3674 SK_U8 *pByte; \
3675 pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \
3676 SK_IN16((IoC), XMA((Mac), (Reg)), &Word); \
3677- pByte[0] = (SK_U8)(Word & 0x00ff); \
3678+ pByte[0] = (SK_U8)(Word & 0x00ff); \
3679 pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \
3680- SK_IN16((IoC), XMA((Mac), (Reg+2)), &Word); \
3681- pByte[2] = (SK_U8)(Word & 0x00ff); \
3682+ SK_IN16((IoC), XMA((Mac), (Reg) + 2), &Word); \
3683+ pByte[2] = (SK_U8)(Word & 0x00ff); \
3684 pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \
3685- SK_IN16((IoC), XMA((Mac), (Reg+4)), &Word); \
3686- pByte[4] = (SK_U8)(Word & 0x00ff); \
3687+ SK_IN16((IoC), XMA((Mac), (Reg) + 4), &Word); \
3688+ pByte[4] = (SK_U8)(Word & 0x00ff); \
3689 pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \
3690 }
3691
3692@@ -1818,10 +2728,10 @@
3693 SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16) \
3694 (((SK_U16)(pByte[0]) & 0x00ff) | \
3695 (((SK_U16)(pByte[1]) << 8) & 0xff00))); \
3696- SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16) \
3697+ SK_OUT16((IoC), XMA((Mac), (Reg) + 2), (SK_U16) \
3698 (((SK_U16)(pByte[2]) & 0x00ff) | \
3699 (((SK_U16)(pByte[3]) << 8) & 0xff00))); \
3700- SK_OUT16((IoC), XMA((Mac), (Reg+4)), (SK_U16) \
3701+ SK_OUT16((IoC), XMA((Mac), (Reg) + 4), (SK_U16) \
3702 (((SK_U16)(pByte[4]) & 0x00ff) | \
3703 (((SK_U16)(pByte[5]) << 8) & 0xff00))); \
3704 }
3705@@ -1831,16 +2741,16 @@
3706 SK_U8 SK_FAR *pByte; \
3707 pByte = (SK_U8 SK_FAR *)&((SK_U8 SK_FAR *)(pVal))[0]; \
3708 SK_IN16((IoC), XMA((Mac), (Reg)), &Word); \
3709- pByte[0] = (SK_U8)(Word & 0x00ff); \
3710+ pByte[0] = (SK_U8)(Word & 0x00ff); \
3711 pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \
3712- SK_IN16((IoC), XMA((Mac), (Reg+2)), &Word); \
3713- pByte[2] = (SK_U8)(Word & 0x00ff); \
3714+ SK_IN16((IoC), XMA((Mac), (Reg) + 2), &Word); \
3715+ pByte[2] = (SK_U8)(Word & 0x00ff); \
3716 pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \
3717- SK_IN16((IoC), XMA((Mac), (Reg+4)), &Word); \
3718- pByte[4] = (SK_U8)(Word & 0x00ff); \
3719+ SK_IN16((IoC), XMA((Mac), (Reg) + 4), &Word); \
3720+ pByte[4] = (SK_U8)(Word & 0x00ff); \
3721 pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \
3722- SK_IN16((IoC), XMA((Mac), (Reg+6)), &Word); \
3723- pByte[6] = (SK_U8)(Word & 0x00ff); \
3724+ SK_IN16((IoC), XMA((Mac), (Reg) + 6), &Word); \
3725+ pByte[6] = (SK_U8)(Word & 0x00ff); \
3726 pByte[7] = (SK_U8)((Word >> 8) & 0x00ff); \
3727 }
3728
3729@@ -1850,13 +2760,13 @@
3730 SK_OUT16((IoC), XMA((Mac), (Reg)), (SK_U16) \
3731 (((SK_U16)(pByte[0]) & 0x00ff)| \
3732 (((SK_U16)(pByte[1]) << 8) & 0xff00))); \
3733- SK_OUT16((IoC), XMA((Mac), (Reg+2)), (SK_U16) \
3734+ SK_OUT16((IoC), XMA((Mac), (Reg) + 2), (SK_U16) \
3735 (((SK_U16)(pByte[2]) & 0x00ff)| \
3736 (((SK_U16)(pByte[3]) << 8) & 0xff00))); \
3737- SK_OUT16((IoC), XMA((Mac), (Reg+4)), (SK_U16) \
3738+ SK_OUT16((IoC), XMA((Mac), (Reg) + 4), (SK_U16) \
3739 (((SK_U16)(pByte[4]) & 0x00ff)| \
3740 (((SK_U16)(pByte[5]) << 8) & 0xff00))); \
3741- SK_OUT16((IoC), XMA((Mac), (Reg+6)), (SK_U16) \
3742+ SK_OUT16((IoC), XMA((Mac), (Reg) + 6), (SK_U16) \
3743 (((SK_U16)(pByte[6]) & 0x00ff)| \
3744 (((SK_U16)(pByte[7]) << 8) & 0xff00))); \
3745 }
3746@@ -1866,7 +2776,7 @@
3747 *
3748 * GM_IN16(), to read a 16 bit register (e.g. GM_GP_STAT)
3749 * GM_OUT16(), to write a 16 bit register (e.g. GM_GP_CTRL)
3750- * GM_IN32(), to read a 32 bit register (e.g. GM_)
3751+ * GM_IN32(), to read a 32 bit register (e.g. GM_RXF_UC_OK)
3752 * GM_OUT32(), to write a 32 bit register (e.g. GM_)
3753 * GM_INADDR(), to read a network address register (e.g. GM_SRC_ADDR_1L)
3754 * GM_OUTADDR(), to write a network address register (e.g. GM_SRC_ADDR_2L)
3755@@ -1885,22 +2795,31 @@
3756 #define GMA(Mac, Reg) \
3757 ((BASE_GMAC_1 + (Mac) * (BASE_GMAC_2 - BASE_GMAC_1)) | (Reg))
3758
3759-#define GM_IN16(IoC, Mac, Reg, pVal) \
3760- SK_IN16((IoC), GMA((Mac), (Reg)), (pVal))
3761+#define GM_IN16(IoC, Mac, Reg, pVal) \
3762+ SK_IN16(IoC, GMA(Mac, Reg), pVal)
3763+
3764+#define GM_OUT16(IoC, Mac, Reg, Val) \
3765+ SK_OUT16(IoC, GMA(Mac, Reg), Val)
3766+
3767+#ifdef SK_LITTLE_ENDIAN
3768+
3769+#define GM_IN32(IoC, Mac, Reg, pVal) { \
3770+ SK_IN16(IoC, GMA(Mac, Reg), (SK_U16 SK_FAR *)(pVal)); \
3771+ SK_IN16((IoC), GMA(Mac, (Reg) + 4), (SK_U16 SK_FAR *)(pVal) + 1); \
3772+}
3773
3774-#define GM_OUT16(IoC, Mac, Reg, Val) \
3775- SK_OUT16((IoC), GMA((Mac), (Reg)), (Val))
3776+#else /* !SK_LITTLE_ENDIAN */
3777
3778-#define GM_IN32(IoC, Mac, Reg, pVal) { \
3779- SK_IN16((IoC), GMA((Mac), (Reg)), \
3780- (SK_U16 SK_FAR*)&((SK_U16 SK_FAR*)(pVal))[XM_WORD_LO]); \
3781- SK_IN16((IoC), GMA((Mac), (Reg+4)), \
3782- (SK_U16 SK_FAR*)&((SK_U16 SK_FAR*)(pVal))[XM_WORD_HI]); \
3783+#define GM_IN32(IoC, Mac, Reg, pVal) { \
3784+ SK_IN16(IoC, GMA(Mac, Reg), (SK_U16 SK_FAR *)(pVal) + 1); \
3785+ SK_IN16(IoC, GMA(Mac, (Reg) + 4), (SK_U16 SK_FAR *)(pVal)); \
3786 }
3787
3788+#endif /* !SK_LITTLE_ENDIAN */
3789+
3790 #define GM_OUT32(IoC, Mac, Reg, Val) { \
3791- SK_OUT16((IoC), GMA((Mac), (Reg)), (SK_U16)((Val) & 0xffffL)); \
3792- SK_OUT16((IoC), GMA((Mac), (Reg+4)), (SK_U16)(((Val) >> 16) & 0xffffL));\
3793+ SK_OUT16(IoC, GMA(Mac, Reg), (SK_U16)((Val) & 0xffffL)); \
3794+ SK_OUT16(IoC, GMA(Mac, (Reg) + 4), (SK_U16)(((Val) >> 16) & 0xffffL)); \
3795 }
3796
3797 #define GM_INADDR(IoC, Mac, Reg, pVal) { \
3798@@ -1908,13 +2827,13 @@
3799 SK_U8 *pByte; \
3800 pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \
3801 SK_IN16((IoC), GMA((Mac), (Reg)), &Word); \
3802- pByte[0] = (SK_U8)(Word & 0x00ff); \
3803+ pByte[0] = (SK_U8)(Word & 0x00ff); \
3804 pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \
3805- SK_IN16((IoC), GMA((Mac), (Reg+4)), &Word); \
3806- pByte[2] = (SK_U8)(Word & 0x00ff); \
3807+ SK_IN16((IoC), GMA((Mac), (Reg) + 4), &Word); \
3808+ pByte[2] = (SK_U8)(Word & 0x00ff); \
3809 pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \
3810- SK_IN16((IoC), GMA((Mac), (Reg+8)), &Word); \
3811- pByte[4] = (SK_U8)(Word & 0x00ff); \
3812+ SK_IN16((IoC), GMA((Mac), (Reg) + 8), &Word); \
3813+ pByte[4] = (SK_U8)(Word & 0x00ff); \
3814 pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \
3815 }
3816
3817@@ -1924,10 +2843,10 @@
3818 SK_OUT16((IoC), GMA((Mac), (Reg)), (SK_U16) \
3819 (((SK_U16)(pByte[0]) & 0x00ff) | \
3820 (((SK_U16)(pByte[1]) << 8) & 0xff00))); \
3821- SK_OUT16((IoC), GMA((Mac), (Reg+4)), (SK_U16) \
3822+ SK_OUT16((IoC), GMA((Mac), (Reg) + 4), (SK_U16) \
3823 (((SK_U16)(pByte[2]) & 0x00ff) | \
3824 (((SK_U16)(pByte[3]) << 8) & 0xff00))); \
3825- SK_OUT16((IoC), GMA((Mac), (Reg+8)), (SK_U16) \
3826+ SK_OUT16((IoC), GMA((Mac), (Reg) + 8), (SK_U16) \
3827 (((SK_U16)(pByte[4]) & 0x00ff) | \
3828 (((SK_U16)(pByte[5]) << 8) & 0xff00))); \
3829 }
3830@@ -1937,16 +2856,16 @@
3831 SK_U8 *pByte; \
3832 pByte = (SK_U8 *)&((SK_U8 *)(pVal))[0]; \
3833 SK_IN16((IoC), GMA((Mac), (Reg)), &Word); \
3834- pByte[0] = (SK_U8)(Word & 0x00ff); \
3835+ pByte[0] = (SK_U8)(Word & 0x00ff); \
3836 pByte[1] = (SK_U8)((Word >> 8) & 0x00ff); \
3837- SK_IN16((IoC), GMA((Mac), (Reg+4)), &Word); \
3838- pByte[2] = (SK_U8)(Word & 0x00ff); \
3839+ SK_IN16((IoC), GMA((Mac), (Reg) + 4), &Word); \
3840+ pByte[2] = (SK_U8)(Word & 0x00ff); \
3841 pByte[3] = (SK_U8)((Word >> 8) & 0x00ff); \
3842- SK_IN16((IoC), GMA((Mac), (Reg+8)), &Word); \
3843- pByte[4] = (SK_U8)(Word & 0x00ff); \
3844+ SK_IN16((IoC), GMA((Mac), (Reg) + 8), &Word); \
3845+ pByte[4] = (SK_U8)(Word & 0x00ff); \
3846 pByte[5] = (SK_U8)((Word >> 8) & 0x00ff); \
3847- SK_IN16((IoC), GMA((Mac), (Reg+12)), &Word); \
3848- pByte[6] = (SK_U8)(Word & 0x00ff); \
3849+ SK_IN16((IoC), GMA((Mac), (Reg) + 12), &Word); \
3850+ pByte[6] = (SK_U8)(Word & 0x00ff); \
3851 pByte[7] = (SK_U8)((Word >> 8) & 0x00ff); \
3852 }
3853
3854@@ -1956,13 +2875,13 @@
3855 SK_OUT16((IoC), GMA((Mac), (Reg)), (SK_U16) \
3856 (((SK_U16)(pByte[0]) & 0x00ff)| \
3857 (((SK_U16)(pByte[1]) << 8) & 0xff00))); \
3858- SK_OUT16((IoC), GMA((Mac), (Reg+4)), (SK_U16) \
3859+ SK_OUT16((IoC), GMA((Mac), (Reg) + 4), (SK_U16) \
3860 (((SK_U16)(pByte[2]) & 0x00ff)| \
3861 (((SK_U16)(pByte[3]) << 8) & 0xff00))); \
3862- SK_OUT16((IoC), GMA((Mac), (Reg+8)), (SK_U16) \
3863+ SK_OUT16((IoC), GMA((Mac), (Reg) + 8), (SK_U16) \
3864 (((SK_U16)(pByte[4]) & 0x00ff)| \
3865 (((SK_U16)(pByte[5]) << 8) & 0xff00))); \
3866- SK_OUT16((IoC), GMA((Mac), (Reg+12)), (SK_U16) \
3867+ SK_OUT16((IoC), GMA((Mac), (Reg) + 12), (SK_U16) \
3868 (((SK_U16)(pByte[6]) & 0x00ff)| \
3869 (((SK_U16)(pByte[7]) << 8) & 0xff00))); \
3870 }
3871@@ -1980,8 +2899,8 @@
3872 #define SK_PHY_BCOM 1 /* Broadcom BCM5400 */
3873 #define SK_PHY_LONE 2 /* Level One LXT1000 */
3874 #define SK_PHY_NAT 3 /* National DP83891 */
3875-#define SK_PHY_MARV_COPPER 4 /* Marvell 88E1011S */
3876-#define SK_PHY_MARV_FIBER 5 /* Marvell 88E1011S working on fiber */
3877+#define SK_PHY_MARV_COPPER 4 /* Marvell 88E1040S */
3878+#define SK_PHY_MARV_FIBER 5 /* Marvell 88E1040S working on fiber */
3879
3880 /*
3881 * PHY addresses (bits 12..8 of PHY address reg)
3882@@ -2010,30 +2929,30 @@
3883 *
3884 * usage: PHY_READ(IoC, pPort, MAC_1, PHY_CTRL, Value);
3885 * Warning: a PHY_READ on an uninitialized PHY (PHY still in reset) never
3886- * comes back. This is checked in DEBUG mode.
3887+ * comes back. This is checked in DEBUG mode.
3888 */
3889 #ifndef DEBUG
3890 #define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) { \
3891- SK_U16 Mmu; \
3892+ SK_U16 Mmu; \
3893 \
3894 XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \
3895 XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
3896 if ((pPort)->PhyType != SK_PHY_XMAC) { \
3897- do { \
3898+ do { \
3899 XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
3900 } while ((Mmu & XM_MMU_PHY_RDY) == 0); \
3901 XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
3902- } \
3903+ } \
3904 }
3905 #else
3906 #define PHY_READ(IoC, pPort, Mac, PhyReg, pVal) { \
3907- SK_U16 Mmu; \
3908+ SK_U16 Mmu; \
3909 int __i = 0; \
3910 \
3911 XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \
3912 XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
3913 if ((pPort)->PhyType != SK_PHY_XMAC) { \
3914- do { \
3915+ do { \
3916 XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
3917 __i++; \
3918 if (__i > 100000) { \
3919@@ -2044,7 +2963,7 @@
3920 } \
3921 } while ((Mmu & XM_MMU_PHY_RDY) == 0); \
3922 XM_IN16((IoC), (Mac), XM_PHY_DATA, (pVal)); \
3923- } \
3924+ } \
3925 }
3926 #endif /* DEBUG */
3927
3928@@ -2052,17 +2971,17 @@
3929 SK_U16 Mmu; \
3930 \
3931 if ((pPort)->PhyType != SK_PHY_XMAC) { \
3932- do { \
3933+ do { \
3934 XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
3935 } while ((Mmu & XM_MMU_PHY_BUSY) != 0); \
3936- } \
3937+ } \
3938 XM_OUT16((IoC), (Mac), XM_PHY_ADDR, (PhyReg) | (pPort)->PhyAddr); \
3939 XM_OUT16((IoC), (Mac), XM_PHY_DATA, (Val)); \
3940 if ((pPort)->PhyType != SK_PHY_XMAC) { \
3941- do { \
3942+ do { \
3943 XM_IN16((IoC), (Mac), XM_MMU_CMD, &Mmu); \
3944 } while ((Mmu & XM_MMU_PHY_BUSY) != 0); \
3945- } \
3946+ } \
3947 }
3948
3949 /*
3950@@ -2071,12 +2990,14 @@
3951 * Use this macro to access PCI config register from the I/O space.
3952 *
3953 * para:
3954+ * pAC Pointer to adapter context
3955 * Addr PCI configuration register to access.
3956 * Values: PCI_VENDOR_ID ... PCI_VPD_ADR_REG,
3957 *
3958- * usage SK_IN16(pAC, PCI_C(PCI_VENDOR_ID), pVal);
3959+ * usage SK_IN16(IoC, PCI_C(pAC, PCI_VENDOR_ID), pVal);
3960 */
3961-#define PCI_C(Addr) (B7_CFG_SPC + (Addr)) /* PCI Config Space */
3962+#define PCI_C(p, Addr) \
3963+ (((CHIP_ID_YUKON_2(p)) ? Y2_CFG_SPC : B7_CFG_SPC) + (Addr))
3964
3965 /*
3966 * Macro SK_HW_ADDR(Base, Addr)
3967@@ -2088,7 +3009,7 @@
3968 * Addr Address offset
3969 *
3970 * usage: May be used in SK_INxx and SK_OUTxx macros
3971- * #define SK_IN8(pAC, Addr, pVal) ...\
3972+ * #define SK_IN8(IoC, Addr, pVal) ...\
3973 * *pVal = (SK_U8)inp(SK_HW_ADDR(pAC->Hw.Iop, Addr)))
3974 */
3975 #ifdef SK_MEM_MAPPED_IO
3976@@ -2107,20 +3028,31 @@
3977 * para:
3978 * pAC Pointer to adapter context struct
3979 * IoC I/O context needed for SK I/O macros
3980- * Port Port number
3981+ * Port Port number
3982 * Mode Mode to set for this LED
3983 */
3984 #define SK_HWAC_LINK_LED(pAC, IoC, Port, Mode) \
3985 SK_OUT8(IoC, MR_ADDR(Port, LNK_LED_REG), Mode);
3986
3987+#define SK_SET_GP_IO(IoC, Bit) { \
3988+ SK_U32 DWord; \
3989+ SK_IN32(IoC, B2_GP_IO, &DWord); \
3990+ DWord |= ((GP_DIR_0 | GP_IO_0) << (Bit));\
3991+ SK_OUT32(IoC, B2_GP_IO, DWord); \
3992+}
3993
3994-/* typedefs *******************************************************************/
3995-
3996+#define SK_CLR_GP_IO(IoC, Bit) { \
3997+ SK_U32 DWord; \
3998+ SK_IN32(IoC, B2_GP_IO, &DWord); \
3999+ DWord &= ~((GP_DIR_0 | GP_IO_0) << (Bit));\
4000+ SK_OUT32(IoC, B2_GP_IO, DWord); \
4001+}
4002
4003-/* function prototypes ********************************************************/
4004+#define SK_GE_PCI_FIFO_SIZE 1600 /* PCI FIFO Size */
4005
4006 #ifdef __cplusplus
4007 }
4008 #endif /* __cplusplus */
4009
4010 #endif /* __INC_SKGEHW_H */
4011+
4012diff -ruN linux/drivers/net/sk98lin/h/skgehwt.h linux-new/drivers/net/sk98lin/h/skgehwt.h
4013--- linux/drivers/net/sk98lin/h/skgehwt.h 2006-04-11 19:19:28.000000000 +0200
4014+++ linux-new/drivers/net/sk98lin/h/skgehwt.h 2006-01-18 14:37:24.000000000 +0100
4015@@ -2,8 +2,8 @@
4016 *
4017 * Name: skhwt.h
4018 * Project: Gigabit Ethernet Adapters, Event Scheduler Module
4019- * Version: $Revision$
4020- * Date: $Date$
4021+ * Version: $Revision$
4022+ * Date: $Date$
4023 * Purpose: Defines for the hardware timer functions
4024 *
4025 ******************************************************************************/
4026diff -ruN linux/drivers/net/sk98lin/h/skgei2c.h linux-new/drivers/net/sk98lin/h/skgei2c.h
4027--- linux/drivers/net/sk98lin/h/skgei2c.h 2006-04-11 19:19:28.000000000 +0200
4028+++ linux-new/drivers/net/sk98lin/h/skgei2c.h 1970-01-01 01:00:00.000000000 +0100
4029@@ -1,210 +0,0 @@
4030-/******************************************************************************
4031- *
4032- * Name: skgei2c.h
4033- * Project: Gigabit Ethernet Adapters, TWSI-Module
4034- * Version: $Revision$
4035- * Date: $Date$
4036- * Purpose: Special defines for TWSI
4037- *
4038- ******************************************************************************/
4039-
4040-/******************************************************************************
4041- *
4042- * (C)Copyright 1998-2002 SysKonnect.
4043- * (C)Copyright 2002-2003 Marvell.
4044- *
4045- * This program is free software; you can redistribute it and/or modify
4046- * it under the terms of the GNU General Public License as published by
4047- * the Free Software Foundation; either version 2 of the License, or
4048- * (at your option) any later version.
4049- *
4050- * The information in this file is provided "AS IS" without warranty.
4051- *
4052- ******************************************************************************/
4053-
4054-/*
4055- * SKGEI2C.H contains all SK-98xx specific defines for the TWSI handling
4056- */
4057-
4058-#ifndef _INC_SKGEI2C_H_
4059-#define _INC_SKGEI2C_H_
4060-
4061-/*
4062- * Macros to access the B2_I2C_CTRL
4063- */
4064-#define SK_I2C_CTL(IoC, flag, dev, dev_size, reg, burst) \
4065- SK_OUT32(IoC, B2_I2C_CTRL,\
4066- (flag ? 0x80000000UL : 0x0L) | \
4067- (((SK_U32)reg << 16) & I2C_ADDR) | \
4068- (((SK_U32)dev << 9) & I2C_DEV_SEL) | \
4069- (dev_size & I2C_DEV_SIZE) | \
4070- ((burst << 4) & I2C_BURST_LEN))
4071-
4072-#define SK_I2C_STOP(IoC) { \
4073- SK_U32 I2cCtrl; \
4074- SK_IN32(IoC, B2_I2C_CTRL, &I2cCtrl); \
4075- SK_OUT32(IoC, B2_I2C_CTRL, I2cCtrl | I2C_STOP); \
4076-}
4077-
4078-#define SK_I2C_GET_CTL(IoC, pI2cCtrl) SK_IN32(IoC, B2_I2C_CTRL, pI2cCtrl)
4079-
4080-/*
4081- * Macros to access the TWSI SW Registers
4082- */
4083-#define SK_I2C_SET_BIT(IoC, SetBits) { \
4084- SK_U8 OrgBits; \
4085- SK_IN8(IoC, B2_I2C_SW, &OrgBits); \
4086- SK_OUT8(IoC, B2_I2C_SW, OrgBits | (SK_U8)(SetBits)); \
4087-}
4088-
4089-#define SK_I2C_CLR_BIT(IoC, ClrBits) { \
4090- SK_U8 OrgBits; \
4091- SK_IN8(IoC, B2_I2C_SW, &OrgBits); \
4092- SK_OUT8(IoC, B2_I2C_SW, OrgBits & ~((SK_U8)(ClrBits))); \
4093-}
4094-
4095-#define SK_I2C_GET_SW(IoC, pI2cSw) SK_IN8(IoC, B2_I2C_SW, pI2cSw)
4096-
4097-/*
4098- * define the possible sensor states
4099- */
4100-#define SK_SEN_IDLE 0 /* Idle: sensor not read */
4101-#define SK_SEN_VALUE 1 /* Value Read cycle */
4102-#define SK_SEN_VALEXT 2 /* Extended Value Read cycle */
4103-
4104-/*
4105- * Conversion factor to convert read Voltage sensor to milli Volt
4106- * Conversion factor to convert read Temperature sensor to 10th degree Celsius
4107- */
4108-#define SK_LM80_VT_LSB 22 /* 22mV LSB resolution */
4109-#define SK_LM80_TEMP_LSB 10 /* 1 degree LSB resolution */
4110-#define SK_LM80_TEMPEXT_LSB 5 /* 0.5 degree LSB resolution for ext. val. */
4111-
4112-/*
4113- * formula: counter = (22500*60)/(rpm * divisor * pulses/2)
4114- * assuming: 6500rpm, 4 pulses, divisor 1
4115- */
4116-#define SK_LM80_FAN_FAKTOR ((22500L*60)/(1*2))
4117-
4118-/*
4119- * Define sensor management data
4120- * Maximum is reached on Genesis copper dual port and Yukon-64
4121- * Board specific maximum is in pAC->I2c.MaxSens
4122- */
4123-#define SK_MAX_SENSORS 8 /* maximal no. of installed sensors */
4124-#define SK_MIN_SENSORS 5 /* minimal no. of installed sensors */
4125-
4126-/*
4127- * To watch the state machine (SM) use the timer in two ways
4128- * instead of one as hitherto
4129- */
4130-#define SK_TIMER_WATCH_SM 0 /* Watch the SM to finish in a spec. time */
4131-#define SK_TIMER_NEW_GAUGING 1 /* Start a new gauging when timer expires */
4132-
4133-/*
4134- * Defines for the individual thresholds
4135- */
4136-
4137-/* Temperature sensor */
4138-#define SK_SEN_TEMP_HIGH_ERR 800 /* Temperature High Err Threshold */
4139-#define SK_SEN_TEMP_HIGH_WARN 700 /* Temperature High Warn Threshold */
4140-#define SK_SEN_TEMP_LOW_WARN 100 /* Temperature Low Warn Threshold */
4141-#define SK_SEN_TEMP_LOW_ERR 0 /* Temperature Low Err Threshold */
4142-
4143-/* VCC which should be 5 V */
4144-#define SK_SEN_PCI_5V_HIGH_ERR 5588 /* Voltage PCI High Err Threshold */
4145-#define SK_SEN_PCI_5V_HIGH_WARN 5346 /* Voltage PCI High Warn Threshold */
4146-#define SK_SEN_PCI_5V_LOW_WARN 4664 /* Voltage PCI Low Warn Threshold */
4147-#define SK_SEN_PCI_5V_LOW_ERR 4422 /* Voltage PCI Low Err Threshold */
4148-
4149-/*
4150- * VIO may be 5 V or 3.3 V. Initialization takes two parts:
4151- * 1. Initialize lowest lower limit and highest higher limit.
4152- * 2. After the first value is read correct the upper or the lower limit to
4153- * the appropriate C constant.
4154- *
4155- * Warning limits are +-5% of the exepected voltage.
4156- * Error limits are +-10% of the expected voltage.
4157- */
4158-
4159-/* Bug fix AF: 16.Aug.2001: Correct the init base of LM80 sensor */
4160-
4161-#define SK_SEN_PCI_IO_5V_HIGH_ERR 5566 /* + 10% V PCI-IO High Err Threshold */
4162-#define SK_SEN_PCI_IO_5V_HIGH_WARN 5324 /* + 5% V PCI-IO High Warn Threshold */
4163- /* 5000 mVolt */
4164-#define SK_SEN_PCI_IO_5V_LOW_WARN 4686 /* - 5% V PCI-IO Low Warn Threshold */
4165-#define SK_SEN_PCI_IO_5V_LOW_ERR 4444 /* - 10% V PCI-IO Low Err Threshold */
4166-
4167-#define SK_SEN_PCI_IO_RANGE_LIMITER 4000 /* 4000 mV range delimiter */
4168-
4169-/* correction values for the second pass */
4170-#define SK_SEN_PCI_IO_3V3_HIGH_ERR 3850 /* + 15% V PCI-IO High Err Threshold */
4171-#define SK_SEN_PCI_IO_3V3_HIGH_WARN 3674 /* + 10% V PCI-IO High Warn Threshold */
4172- /* 3300 mVolt */
4173-#define SK_SEN_PCI_IO_3V3_LOW_WARN 2926 /* - 10% V PCI-IO Low Warn Threshold */
4174-#define SK_SEN_PCI_IO_3V3_LOW_ERR 2772 /* - 15% V PCI-IO Low Err Threshold */
4175-
4176-/*
4177- * VDD voltage
4178- */
4179-#define SK_SEN_VDD_HIGH_ERR 3630 /* Voltage ASIC High Err Threshold */
4180-#define SK_SEN_VDD_HIGH_WARN 3476 /* Voltage ASIC High Warn Threshold */
4181-#define SK_SEN_VDD_LOW_WARN 3146 /* Voltage ASIC Low Warn Threshold */
4182-#define SK_SEN_VDD_LOW_ERR 2970 /* Voltage ASIC Low Err Threshold */
4183-
4184-/*
4185- * PHY PLL 3V3 voltage
4186- */
4187-#define SK_SEN_PLL_3V3_HIGH_ERR 3630 /* Voltage PMA High Err Threshold */
4188-#define SK_SEN_PLL_3V3_HIGH_WARN 3476 /* Voltage PMA High Warn Threshold */
4189-#define SK_SEN_PLL_3V3_LOW_WARN 3146 /* Voltage PMA Low Warn Threshold */
4190-#define SK_SEN_PLL_3V3_LOW_ERR 2970 /* Voltage PMA Low Err Threshold */
4191-
4192-/*
4193- * VAUX (YUKON only)
4194- */
4195-#define SK_SEN_VAUX_3V3_HIGH_ERR 3630 /* Voltage VAUX High Err Threshold */
4196-#define SK_SEN_VAUX_3V3_HIGH_WARN 3476 /* Voltage VAUX High Warn Threshold */
4197-#define SK_SEN_VAUX_3V3_LOW_WARN 3146 /* Voltage VAUX Low Warn Threshold */
4198-#define SK_SEN_VAUX_3V3_LOW_ERR 2970 /* Voltage VAUX Low Err Threshold */
4199-#define SK_SEN_VAUX_0V_WARN_ERR 0 /* if VAUX not present */
4200-#define SK_SEN_VAUX_RANGE_LIMITER 1000 /* 1000 mV range delimiter */
4201-
4202-/*
4203- * PHY 2V5 voltage
4204- */
4205-#define SK_SEN_PHY_2V5_HIGH_ERR 2750 /* Voltage PHY High Err Threshold */
4206-#define SK_SEN_PHY_2V5_HIGH_WARN 2640 /* Voltage PHY High Warn Threshold */
4207-#define SK_SEN_PHY_2V5_LOW_WARN 2376 /* Voltage PHY Low Warn Threshold */
4208-#define SK_SEN_PHY_2V5_LOW_ERR 2222 /* Voltage PHY Low Err Threshold */
4209-
4210-/*
4211- * ASIC Core 1V5 voltage (YUKON only)
4212- */
4213-#define SK_SEN_CORE_1V5_HIGH_ERR 1650 /* Voltage ASIC Core High Err Threshold */
4214-#define SK_SEN_CORE_1V5_HIGH_WARN 1575 /* Voltage ASIC Core High Warn Threshold */
4215-#define SK_SEN_CORE_1V5_LOW_WARN 1425 /* Voltage ASIC Core Low Warn Threshold */
4216-#define SK_SEN_CORE_1V5_LOW_ERR 1350 /* Voltage ASIC Core Low Err Threshold */
4217-
4218-/*
4219- * FAN 1 speed
4220- */
4221-/* assuming: 6500rpm +-15%, 4 pulses,
4222- * warning at: 80 %
4223- * error at: 70 %
4224- * no upper limit
4225- */
4226-#define SK_SEN_FAN_HIGH_ERR 20000 /* FAN Speed High Err Threshold */
4227-#define SK_SEN_FAN_HIGH_WARN 20000 /* FAN Speed High Warn Threshold */
4228-#define SK_SEN_FAN_LOW_WARN 5200 /* FAN Speed Low Warn Threshold */
4229-#define SK_SEN_FAN_LOW_ERR 4550 /* FAN Speed Low Err Threshold */
4230-
4231-/*
4232- * Some Voltages need dynamic thresholds
4233- */
4234-#define SK_SEN_DYN_INIT_NONE 0 /* No dynamic init of thresholds */
4235-#define SK_SEN_DYN_INIT_PCI_IO 10 /* Init PCI-IO with new thresholds */
4236-#define SK_SEN_DYN_INIT_VAUX 11 /* Init VAUX with new thresholds */
4237-
4238-extern int SkLm80ReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen);
4239-#endif /* n_INC_SKGEI2C_H */
4240diff -ruN linux/drivers/net/sk98lin/h/skgeinit.h linux-new/drivers/net/sk98lin/h/skgeinit.h
4241--- linux/drivers/net/sk98lin/h/skgeinit.h 2006-04-11 19:19:28.000000000 +0200
4242+++ linux-new/drivers/net/sk98lin/h/skgeinit.h 2006-01-18 14:37:24.000000000 +0100
4243@@ -2,23 +2,24 @@
4244 *
4245 * Name: skgeinit.h
4246 * Project: Gigabit Ethernet Adapters, Common Modules
4247- * Version: $Revision$
4248- * Date: $Date$
4249+ * Version: $Revision$
4250+ * Date: $Date$
4251 * Purpose: Structures and prototypes for the GE Init Module
4252 *
4253 ******************************************************************************/
4254
4255 /******************************************************************************
4256 *
4257+ * LICENSE:
4258 * (C)Copyright 1998-2002 SysKonnect.
4259- * (C)Copyright 2002-2003 Marvell.
4260+ * (C)Copyright 2002-2005 Marvell.
4261 *
4262 * This program is free software; you can redistribute it and/or modify
4263 * it under the terms of the GNU General Public License as published by
4264 * the Free Software Foundation; either version 2 of the License, or
4265 * (at your option) any later version.
4266- *
4267 * The information in this file is provided "AS IS" without warranty.
4268+ * /LICENSE
4269 *
4270 ******************************************************************************/
4271
4272@@ -60,14 +61,17 @@
4273 #define SK_XMIT_DUR 0x002faf08UL /* 50 ms */
4274 #define SK_BLK_DUR 0x01dcd650UL /* 500 ms */
4275
4276-#define SK_DPOLL_DEF 0x00ee6b28UL /* 250 ms at 62.5 MHz */
4277+#define SK_DPOLL_DEF 0x00ee6b28UL /* 250 ms at 62.5 MHz (Genesis) */
4278+#define SK_DPOLL_DEF_Y2 0x0000124fUL /* 75 us (Yukon-2) */
4279
4280 #define SK_DPOLL_MAX 0x00ffffffUL /* 268 ms at 62.5 MHz */
4281- /* 215 ms at 78.12 MHz */
4282+ /* 215 ms at 78.12 MHz (Yukon) */
4283
4284 #define SK_FACT_62 100 /* is given in percent */
4285-#define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */
4286+#define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */
4287 #define SK_FACT_78 125 /* on YUKON: 78.12 MHz */
4288+#define SK_FACT_100 161 /* on YUKON-FE: 100 MHz */
4289+#define SK_FACT_125 202 /* on YUKON-EC: 125 MHz */
4290
4291 /* Timeout values */
4292 #define SK_MAC_TO_53 72 /* MAC arbiter timeout */
4293@@ -82,11 +86,23 @@
4294 #define SK_RB_LLPP_S (10 * 1024) /* Lower Level for small Queues */
4295 #define SK_RB_LLPP_B (16 * 1024) /* Lower Level for big Queues */
4296
4297+/* Threshold values for Yukon-EC Ultra */
4298+#define SK_ECU_ULPP 0x0080 /* Upper Pause Threshold (multiples of 8) */
4299+#define SK_ECU_LLPP 0x0060 /* Lower Pause Threshold (multiples of 8) */
4300+#define SK_ECU_AE_THR 0x0180 /* Almost Empty Threshold */
4301+#define SK_ECU_TXFF_LEV 0x01a0 /* Tx BMU FIFO Level */
4302+
4303 #ifndef SK_BMU_RX_WM
4304-#define SK_BMU_RX_WM 0x600 /* BMU Rx Watermark */
4305+#define SK_BMU_RX_WM 0x600 /* BMU Rx Watermark */
4306 #endif
4307+
4308 #ifndef SK_BMU_TX_WM
4309-#define SK_BMU_TX_WM 0x600 /* BMU Tx Watermark */
4310+#define SK_BMU_TX_WM 0x600 /* BMU Tx Watermark */
4311+#endif
4312+
4313+/* performance sensitive drivers should set this define to 0x80 */
4314+#ifndef SK_BMU_RX_WM_PEX
4315+#define SK_BMU_RX_WM_PEX 0x600 /* BMU Rx Watermark for PEX */
4316 #endif
4317
4318 /* XMAC II Rx High Watermark */
4319@@ -98,37 +114,31 @@
4320 #define SK_XM_THR_MULL 0x01fb /* .. for multiple link usage */
4321 #define SK_XM_THR_JUMBO 0x03fc /* .. for jumbo frame usage */
4322
4323-/* values for GIPortUsage */
4324+/* values for PortUsage */
4325 #define SK_RED_LINK 1 /* redundant link usage */
4326 #define SK_MUL_LINK 2 /* multiple link usage */
4327 #define SK_JUMBO_LINK 3 /* driver uses jumbo frames */
4328
4329 /* Minimum RAM Buffer Rx Queue Size */
4330-#define SK_MIN_RXQ_SIZE 16 /* 16 kB */
4331+#define SK_MIN_RXQ_SIZE (((pAC)->GIni.GIYukon2) ? 10 : 16) /* 10/16 kB */
4332
4333 /* Minimum RAM Buffer Tx Queue Size */
4334-#define SK_MIN_TXQ_SIZE 16 /* 16 kB */
4335+#define SK_MIN_TXQ_SIZE (((pAC)->GIni.GIYukon2) ? 10 : 16) /* 10/16 kB */
4336
4337-/* Queue Size units */
4338-#define QZ_UNITS 0x7
4339+/* Queue Size units (Genesis/Yukon) */
4340+#define QZ_UNITS 7
4341 #define QZ_STEP 8
4342
4343+/* Queue Size units (Yukon-2) */
4344+#define QZ_STEP_Y2 1
4345+
4346 /* Percentage of queue size from whole memory */
4347 /* 80 % for receive */
4348-#define RAM_QUOTA_RX 80L
4349-/* 0% for sync transfer */
4350-#define RAM_QUOTA_SYNC 0L
4351+#define RAM_QUOTA_RX 80
4352+/* 0 % for sync transfer */
4353+#define RAM_QUOTA_SYNC 0
4354 /* the rest (20%) is taken for async transfer */
4355
4356-/* Get the rounded queue size in Bytes in 8k steps */
4357-#define ROUND_QUEUE_SIZE(SizeInBytes) \
4358- ((((unsigned long) (SizeInBytes) + (QZ_STEP*1024L)-1) / 1024) & \
4359- ~(QZ_STEP-1))
4360-
4361-/* Get the rounded queue size in KBytes in 8k steps */
4362-#define ROUND_QUEUE_SIZE_KB(Kilobytes) \
4363- ROUND_QUEUE_SIZE((Kilobytes) * 1024L)
4364-
4365 /* Types of RAM Buffer Queues */
4366 #define SK_RX_SRAM_Q 1 /* small receive queue */
4367 #define SK_RX_BRAM_Q 2 /* big receive queue */
4368@@ -167,11 +177,11 @@
4369
4370
4371 /* Link Speed Capabilities */
4372-#define SK_LSPEED_CAP_AUTO (1<<0) /* Automatic resolution */
4373-#define SK_LSPEED_CAP_10MBPS (1<<1) /* 10 Mbps */
4374-#define SK_LSPEED_CAP_100MBPS (1<<2) /* 100 Mbps */
4375-#define SK_LSPEED_CAP_1000MBPS (1<<3) /* 1000 Mbps */
4376-#define SK_LSPEED_CAP_INDETERMINATED (1<<4) /* indeterminated */
4377+#define SK_LSPEED_CAP_AUTO BIT_0S /* Automatic resolution */
4378+#define SK_LSPEED_CAP_10MBPS BIT_1S /* 10 Mbps */
4379+#define SK_LSPEED_CAP_100MBPS BIT_2S /* 100 Mbps */
4380+#define SK_LSPEED_CAP_1000MBPS BIT_3S /* 1000 Mbps */
4381+#define SK_LSPEED_CAP_INDETERMINATED BIT_4S /* indeterminated */
4382
4383 /* Link Speed Parameter */
4384 #define SK_LSPEED_AUTO 1 /* Automatic resolution */
4385@@ -189,11 +199,11 @@
4386
4387
4388 /* Link Capability Parameter */
4389-#define SK_LMODE_CAP_HALF (1<<0) /* Half Duplex Mode */
4390-#define SK_LMODE_CAP_FULL (1<<1) /* Full Duplex Mode */
4391-#define SK_LMODE_CAP_AUTOHALF (1<<2) /* AutoHalf Duplex Mode */
4392-#define SK_LMODE_CAP_AUTOFULL (1<<3) /* AutoFull Duplex Mode */
4393-#define SK_LMODE_CAP_INDETERMINATED (1<<4) /* indeterminated */
4394+#define SK_LMODE_CAP_HALF BIT_0S /* Half Duplex Mode */
4395+#define SK_LMODE_CAP_FULL BIT_1S /* Full Duplex Mode */
4396+#define SK_LMODE_CAP_AUTOHALF BIT_2S /* AutoHalf Duplex Mode */
4397+#define SK_LMODE_CAP_AUTOFULL BIT_3S /* AutoFull Duplex Mode */
4398+#define SK_LMODE_CAP_INDETERMINATED BIT_4S /* indeterminated */
4399
4400 /* Link Mode Current State */
4401 #define SK_LMODE_STAT_UNKNOWN 1 /* Unknown Duplex Mode */
4402@@ -220,10 +230,10 @@
4403 #define SK_FLOW_STAT_INDETERMINATED 5 /* indeterminated */
4404
4405 /* Master/Slave Mode Capabilities */
4406-#define SK_MS_CAP_AUTO (1<<0) /* Automatic resolution */
4407-#define SK_MS_CAP_MASTER (1<<1) /* This station is master */
4408-#define SK_MS_CAP_SLAVE (1<<2) /* This station is slave */
4409-#define SK_MS_CAP_INDETERMINATED (1<<3) /* indeterminated */
4410+#define SK_MS_CAP_AUTO BIT_0S /* Automatic resolution */
4411+#define SK_MS_CAP_MASTER BIT_1S /* This station is master */
4412+#define SK_MS_CAP_SLAVE BIT_2S /* This station is slave */
4413+#define SK_MS_CAP_INDETERMINATED BIT_3S /* indeterminated */
4414
4415 /* Set Master/Slave Mode Parameter (and capabilities) */
4416 #define SK_MS_MODE_AUTO 1 /* Automatic resolution */
4417@@ -238,25 +248,25 @@
4418 #define SK_MS_STAT_FAULT 4 /* M/S resolution failed */
4419 #define SK_MS_STAT_INDETERMINATED 5 /* indeterminated */
4420
4421-/* parameter 'Mode' when calling SkXmSetRxCmd() */
4422-#define SK_STRIP_FCS_ON (1<<0) /* Enable FCS stripping of Rx frames */
4423-#define SK_STRIP_FCS_OFF (1<<1) /* Disable FCS stripping of Rx frames */
4424-#define SK_STRIP_PAD_ON (1<<2) /* Enable pad byte stripping of Rx fr */
4425-#define SK_STRIP_PAD_OFF (1<<3) /* Disable pad byte stripping of Rx fr */
4426-#define SK_LENERR_OK_ON (1<<4) /* Don't chk fr for in range len error */
4427-#define SK_LENERR_OK_OFF (1<<5) /* Check frames for in range len error */
4428-#define SK_BIG_PK_OK_ON (1<<6) /* Don't set Rx Error bit for big frames */
4429-#define SK_BIG_PK_OK_OFF (1<<7) /* Set Rx Error bit for big frames */
4430-#define SK_SELF_RX_ON (1<<8) /* Enable Rx of own packets */
4431-#define SK_SELF_RX_OFF (1<<9) /* Disable Rx of own packets */
4432+/* parameter 'Mode' when calling SkMacSetRxCmd() */
4433+#define SK_STRIP_FCS_ON BIT_0S /* Enable FCS stripping of Rx frames */
4434+#define SK_STRIP_FCS_OFF BIT_1S /* Disable FCS stripping of Rx frames */
4435+#define SK_STRIP_PAD_ON BIT_2S /* Enable pad byte stripping of Rx fr */
4436+#define SK_STRIP_PAD_OFF BIT_3S /* Disable pad byte stripping of Rx fr */
4437+#define SK_LENERR_OK_ON BIT_4S /* Don't chk fr for in range len error */
4438+#define SK_LENERR_OK_OFF BIT_5S /* Check frames for in range len error */
4439+#define SK_BIG_PK_OK_ON BIT_6S /* Don't set Rx Error bit for big frames */
4440+#define SK_BIG_PK_OK_OFF BIT_7S /* Set Rx Error bit for big frames */
4441+#define SK_SELF_RX_ON BIT_8S /* Enable Rx of own packets */
4442+#define SK_SELF_RX_OFF BIT_9S /* Disable Rx of own packets */
4443
4444 /* parameter 'Para' when calling SkMacSetRxTxEn() */
4445-#define SK_MAC_LOOPB_ON (1<<0) /* Enable MAC Loopback Mode */
4446-#define SK_MAC_LOOPB_OFF (1<<1) /* Disable MAC Loopback Mode */
4447-#define SK_PHY_LOOPB_ON (1<<2) /* Enable PHY Loopback Mode */
4448-#define SK_PHY_LOOPB_OFF (1<<3) /* Disable PHY Loopback Mode */
4449-#define SK_PHY_FULLD_ON (1<<4) /* Enable GMII Full Duplex */
4450-#define SK_PHY_FULLD_OFF (1<<5) /* Disable GMII Full Duplex */
4451+#define SK_MAC_LOOPB_ON BIT_0S /* Enable MAC Loopback Mode */
4452+#define SK_MAC_LOOPB_OFF BIT_1S /* Disable MAC Loopback Mode */
4453+#define SK_PHY_LOOPB_ON BIT_2S /* Enable PHY Loopback Mode */
4454+#define SK_PHY_LOOPB_OFF BIT_3S /* Disable PHY Loopback Mode */
4455+#define SK_PHY_FULLD_ON BIT_4S /* Enable GMII Full Duplex */
4456+#define SK_PHY_FULLD_OFF BIT_5S /* Disable GMII Full Duplex */
4457
4458 /* States of PState */
4459 #define SK_PRT_RESET 0 /* the port is reset */
4460@@ -266,18 +276,24 @@
4461
4462 /* PHY power down modes */
4463 #define PHY_PM_OPERATIONAL_MODE 0 /* PHY operational mode */
4464-#define PHY_PM_DEEP_SLEEP 1 /* coma mode --> minimal power */
4465+#define PHY_PM_DEEP_SLEEP 1 /* Coma mode --> minimal power */
4466 #define PHY_PM_IEEE_POWER_DOWN 2 /* IEEE 22.2.4.1.5 compl. power down */
4467-#define PHY_PM_ENERGY_DETECT 3 /* energy detect */
4468-#define PHY_PM_ENERGY_DETECT_PLUS 4 /* energy detect plus */
4469+#define PHY_PM_ENERGY_DETECT 3 /* Energy detect */
4470+#define PHY_PM_ENERGY_DETECT_PLUS 4 /* Energy detect plus */
4471+
4472+/* PCI Bus Types */
4473+#define SK_PCI_BUS BIT_0S /* normal PCI bus */
4474+#define SK_PCIX_BUS BIT_1S /* PCI-X bus */
4475+#define SK_PEX_BUS BIT_2S /* PCI-Express bus */
4476
4477 /* Default receive frame limit for Workaround of XMAC Errata */
4478 #define SK_DEF_RX_WA_LIM SK_CONSTU64(100)
4479
4480 /* values for GILedBlinkCtrl (LED Blink Control) */
4481-#define SK_ACT_LED_BLINK (1<<0) /* Active LED blinking */
4482-#define SK_DUP_LED_NORMAL (1<<1) /* Duplex LED normal */
4483-#define SK_LED_LINK100_ON (1<<2) /* Link 100M LED on */
4484+#define SK_ACT_LED_BLINK BIT_0S /* Active LED blinking */
4485+#define SK_DUP_LED_NORMAL BIT_1S /* Duplex LED normal */
4486+#define SK_LED_LINK100_ON BIT_2S /* Link 100M LED on */
4487+#define SK_DUAL_LED_ACT_LNK BIT_3S /* Dual LED ACT/LNK configuration */
4488
4489 /* Link Partner Status */
4490 #define SK_LIPA_UNKNOWN 0 /* Link partner is in unknown state */
4491@@ -290,18 +306,173 @@
4492 /* Max. Auto-neg. timeouts before link detection in sense mode is reset */
4493 #define SK_MAX_ANEG_TO 10 /* Max. 10 times the sense mode is reset */
4494
4495+
4496+/******************************************************************************
4497+ *
4498+ * HW_FEATURE() macro
4499+ */
4500+
4501+/* DWORD 0: Features */
4502+#define HWF_CLK_GATING_ENABLE 0x02000000UL /* Enable Clock Gating */
4503+#define HWF_RED_CORE_CLK_SUP 0x01000000UL /* Reduced Core Clock supp. */
4504+#define HWF_SYNC_TX_SUP 0x00800000UL /* Synch. Tx Queue available */
4505+#define HWF_SINGLE_PORT_DEVICE 0x00400000UL /* Device has only one LAN IF */
4506+#define HWF_JUMBO_FRAMES_SUP 0x00200000UL /* Jumbo Frames supported */
4507+#define HWF_TX_TCP_CSUM_SUP 0x00100000UL /* TCP Tx checksum supported */
4508+#define HWF_TX_UDP_CSUM_SUP 0x00080000UL /* UDP Tx checksum supported */
4509+#define HWF_RX_CSUM_SUP 0x00040000UL /* RX checksum supported */
4510+#define HWF_TCP_SEGM_SUP 0x00020000UL /* TCP segmentation supported */
4511+#define HWF_RSS_HASH_SUP 0x00010000UL /* RSS Hash supported */
4512+#define HWF_PORT_VLAN_SUP 0x00008000UL /* VLAN can be config per port*/
4513+#define HWF_ROLE_PARAM_SUP 0x00004000UL /* Role parameter supported */
4514+#define HWF_LOW_PMODE_SUP 0x00002000UL /* Low Power Mode supported */
4515+#define HWF_ENERGIE_DEMO_SUP 0x00001000UL /* Energy Detect mode supp. */
4516+#define HWF_SPEED1000_SUP 0x00000800UL /* Line Speed 1000 supported */
4517+#define HWF_SPEED100_SUP 0x00000400UL /* Line Speed 100 supported */
4518+#define HWF_SPEED10_SUP 0x00000200UL /* Line Speed 10 supported */
4519+#define HWF_AUTONEGSENSE_SUP 0x00000100UL /* Autoneg Sense supported */
4520+#define HWF_PHY_LOOPB_MD_SUP 0x00000080UL /* PHY loopback mode supp. */
4521+#define HWF_ASF_SUP 0x00000040UL /* ASF support possible */
4522+#define HWF_QS_STEPS_1KB 0x00000020UL /* The Rx/Tx queues can be */
4523+ /* configured with 1 kB res. */
4524+#define HWF_OWN_RAM_PER_PORT 0x00000010UL /* Each port has a separate */
4525+ /* RAM buffer */
4526+#define HWF_MIN_LED_IF 0x00000008UL /* Minimal LED interface */
4527+ /* (e.g. for Yukon-EC) */
4528+#define HWF_LIST_ELEMENTS_USED 0x00000004UL /* HW uses list elements */
4529+ /* (otherwise desc. are used) */
4530+#define HWF_GMAC_INSIDE 0x00000002UL /* Device contains GMAC */
4531+#define HWF_TWSI_PRESENT 0x00000001UL /* TWSI sensor bus present */
4532+
4533+/*-RMV- DWORD 1: Deviations */
4534+#define HWF_WA_DEV_4200 0x10200000UL /*-RMV- 4.200 (D3 Blue Screen)*/
4535+#define HWF_WA_DEV_4185CS 0x10100000UL /*-RMV- 4.185 (ECU 100 CS cal)*/
4536+#define HWF_WA_DEV_4185 0x10080000UL /*-RMV- 4.185 (ECU Tx h check)*/
4537+#define HWF_WA_DEV_4167 0x10040000UL /*-RMV- 4.167 (Rx OvSize Hang)*/
4538+#define HWF_WA_DEV_4152 0x10020000UL /*-RMV- 4.152 (RSS issue) */
4539+#define HWF_WA_DEV_4115 0x10010000UL /*-RMV- 4.115 (Rx MAC FIFO) */
4540+#define HWF_WA_DEV_4109 0x10008000UL /*-RMV- 4.109 (BIU hang) */
4541+#define HWF_WA_DEV_483 0x10004000UL /*-RMV- 4.83 (Rx TCP wrong) */
4542+#define HWF_WA_DEV_479 0x10002000UL /*-RMV- 4.79 (Rx BMU hang II) */
4543+#define HWF_WA_DEV_472 0x10001000UL /*-RMV- 4.72 (GPHY2 MDC clk) */
4544+#define HWF_WA_DEV_463 0x10000800UL /*-RMV- 4.63 (Rx BMU hang I) */
4545+#define HWF_WA_DEV_427 0x10000400UL /*-RMV- 4.27 (Tx Done Rep) */
4546+#define HWF_WA_DEV_42 0x10000200UL /*-RMV- 4.2 (pref unit burst) */
4547+#define HWF_WA_DEV_46 0x10000100UL /*-RMV- 4.6 (CPU crash II) */
4548+#define HWF_WA_DEV_43_418 0x10000080UL /*-RMV- 4.3 & 4.18 (PCI unexp */
4549+ /*-RMV- compl&Stat BMU deadl) */
4550+#define HWF_WA_DEV_420 0x10000040UL /*-RMV- 4.20 (Status BMU ov) */
4551+#define HWF_WA_DEV_423 0x10000020UL /*-RMV- 4.23 (TCP Segm Hang) */
4552+#define HWF_WA_DEV_424 0x10000010UL /*-RMV- 4.24 (MAC reg overwr) */
4553+#define HWF_WA_DEV_425 0x10000008UL /*-RMV- 4.25 (Magic packet */
4554+ /*-RMV- with odd offset) */
4555+#define HWF_WA_DEV_428 0x10000004UL /*-RMV- 4.28 (Poll-U &BigEndi)*/
4556+#define HWF_WA_FIFO_FLUSH_YLA0 0x10000002UL /*-RMV- dis Rx GMAC FIFO Flush*/
4557+ /*-RMV- for Yu-L Rev. A0 only */
4558+#define HWF_WA_COMA_MODE 0x10000001UL /*-RMV- Coma Mode WA req */
4559+
4560+/* DWORD 2: still unused */
4561+/* DWORD 3: still unused */
4562+
4563+
4564+/*
4565+ * HW_FEATURE() - returns whether the feature is serviced or not
4566+ */
4567+#define HW_FEATURE(pAC, ReqFeature) \
4568+ (((pAC)->GIni.HwF.Features[((ReqFeature) & 0x30000000UL) >> 28] &\
4569+ ((ReqFeature) & 0x0fffffffUL)) != 0)
4570+
4571+#define HW_FEAT_LIST 0
4572+#define HW_DEV_LIST 1
4573+
4574+#define SET_HW_FEATURE_MASK(pAC, List, OffMaskValue, OnMaskValue) { \
4575+ if ((List) == HW_FEAT_LIST || (List) == HW_DEV_LIST) { \
4576+ (pAC)->GIni.HwF.OffMask[List] = (OffMaskValue); \
4577+ (pAC)->GIni.HwF.OnMask[List] = (OnMaskValue); \
4578+ } \
4579+}
4580+
4581+/* driver access macros for GIni structure ***********************************/
4582+
4583+#define CHIP_ID_YUKON_2(pAC) ((pAC)->GIni.GIYukon2)
4584+
4585+#define HW_SYNC_TX_SUPPORTED(pAC) \
4586+ ((pAC)->GIni.GIChipId != CHIP_ID_YUKON_EC && \
4587+ (pAC)->GIni.GIChipId != CHIP_ID_YUKON_FE && \
4588+ (pAC)->GIni.GIChipId != CHIP_ID_YUKON_EC_U)
4589+
4590+#define HW_MS_TO_TICKS(pAC, MsTime) \
4591+ ((MsTime) * (62500L/100) * (pAC)->GIni.GIHstClkFact)
4592+
4593+#ifdef XXX
4594+/* still under construction */
4595+#define HW_IS_SINGLE_PORT(pAC) ((pAC)->GIni.GIMacsFound == 1)
4596+#define HW_NUMBER_OF_PORTS(pAC) ((pAC)->GIni.GIMacsFound)
4597+
4598+#define HW_TX_UDP_CSUM_SUPPORTED(pAC) \
4599+ ((((pAC)->GIni.GIChipId >= CHIP_ID_YUKON) && ((pAC)->GIni.GIChipRev != 0))
4600+
4601+#define HW_DEFAULT_LINESPEED(pAC) \
4602+ ((!(pAC)->GIni.GIGenesis && (pAC)->GIni.GICopperType) ? \
4603+ SK_LSPEED_AUTO : SK_LSPEED_1000MBPS)
4604+
4605+#define HW_ROLE_PARAM_SUPPORTED(pAC) ((pAC)->GIni.GICopperType)
4606+
4607+#define HW_SPEED1000_SUPPORTED(pAC, Port) \
4608+ ((pAC)->GIni.GP[Port].PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS)
4609+
4610+#define HW_SPEED100_SUPPORTED(pAC, Port) \
4611+ ((pAC)->GIni.GP[Port].PLinkSpeedCap & SK_LSPEED_CAP_100MBPS)
4612+
4613+#define HW_SPEED10_SUPPORTED(pAC, Port) \
4614+ ((pAC)->GIni.GP[Port].PLinkSpeedCap & SK_LSPEED_CAP_10MBPS)
4615+
4616+#define HW_AUTONEGSENSE_SUPPORTED(pAC) ((pAC)->GIni.GP[0].PhyType==SK_PHY_XMAC)
4617+
4618+#define HW_FREQ_TO_CARD_TICKS(pAC, AdapterClkSpeed, Freq) \
4619+ (((AdapterClkSpeed / 100) * (pAC)->GIni.GIHstClkFact) / Freq)
4620+
4621+#define HW_IS_LINK_UP(pAC, Port) ((pAC)->GIni.GP[Port].PHWLinkUp)
4622+#define HW_LINK_SPEED_USED(pAC, Port) ((pAC)->GIni.GP[Port].PLinkSpeedUsed)
4623+#define HW_RAM_SIZE(pAC) ((pAC)->GIni.GIRamSize)
4624+
4625+#define HW_PHY_LP_MODE_SUPPORTED(pAC) (pAC0->???
4626+#define HW_ASF_ACTIVE(pAC) ???
4627+#define RAWIO_OUT32(pAC, pAC->RegIrqMask, pAC->GIni.GIValIrqMask)...
4628+
4629+/* macro to check whether Tx checksum is supported */
4630+#define HW_TX_CSUM_SUPPORTED(pAC) ((pAC)->GIni.GIChipId != CHIP_ID_GENESIS)
4631+
4632+BMU_UDP_CHECK : BMU_TCP_CHECK;
4633+
4634+/* macro for - Own Bit mirrored to DWORD7 (Yukon LP receive descriptor) */
4635+#endif /* 0 */
4636+
4637+
4638 /* structures *****************************************************************/
4639
4640 /*
4641+ * HW Feature structure
4642+ */
4643+typedef struct s_HwFeatures {
4644+ SK_U32 Features[4]; /* Feature list */
4645+ SK_U32 OffMask[4]; /* Off Mask */
4646+ SK_U32 OnMask[4]; /* On Mask */
4647+} SK_HW_FEATURES;
4648+
4649+/*
4650 * MAC specific functions
4651 */
4652 typedef struct s_GeMacFunc {
4653- int (*pFnMacUpdateStats)(SK_AC *pAC, SK_IOC IoC, unsigned int Port);
4654- int (*pFnMacStatistic)(SK_AC *pAC, SK_IOC IoC, unsigned int Port,
4655- SK_U16 StatAddr, SK_U32 SK_FAR *pVal);
4656- int (*pFnMacResetCounter)(SK_AC *pAC, SK_IOC IoC, unsigned int Port);
4657- int (*pFnMacOverflow)(SK_AC *pAC, SK_IOC IoC, unsigned int Port,
4658- SK_U16 IStatus, SK_U64 SK_FAR *pVal);
4659+ int (*pFnMacUpdateStats)(SK_AC *, SK_IOC, unsigned int);
4660+ int (*pFnMacStatistic)(SK_AC *, SK_IOC, unsigned int, SK_U16, SK_U32 SK_FAR *);
4661+ int (*pFnMacResetCounter)(SK_AC *, SK_IOC, unsigned int);
4662+ int (*pFnMacOverflow)(SK_AC *, SK_IOC, unsigned int, SK_U16, SK_U64 SK_FAR *);
4663+ void (*pSkGeSirqIsr)(SK_AC *, SK_IOC, SK_U32);
4664+#ifdef SK_DIAG
4665+ int (*pFnMacPhyRead)(SK_AC *, SK_IOC, int, int, SK_U16 SK_FAR *);
4666+ int (*pFnMacPhyWrite)(SK_AC *, SK_IOC, int, int, SK_U16);
4667+#endif /* SK_DIAG */
4668 } SK_GEMACFUNC;
4669
4670 /*
4671@@ -311,7 +482,7 @@
4672 #ifndef SK_DIAG
4673 SK_TIMER PWaTimer; /* Workaround Timer */
4674 SK_TIMER HalfDupChkTimer;
4675-#endif /* SK_DIAG */
4676+#endif /* !SK_DIAG */
4677 SK_U32 PPrevShorts; /* Previous Short Counter checking */
4678 SK_U32 PPrevFcs; /* Previous FCS Error Counter checking */
4679 SK_U64 PPrevRx; /* Previous RxOk Counter checking */
4680@@ -335,6 +506,7 @@
4681 int PXaQOff; /* Asynchronous Tx Queue Address Offset */
4682 int PhyType; /* PHY used on this port */
4683 int PState; /* Port status (reset, stop, init, run) */
4684+ int PPortUsage; /* Driver Port Usage */
4685 SK_U16 PhyId1; /* PHY Id1 on this port */
4686 SK_U16 PhyAddr; /* MDIO/MDC PHY address */
4687 SK_U16 PIsave; /* Saved Interrupt status word */
4688@@ -367,7 +539,10 @@
4689 int PMacJamLen; /* MAC Jam length */
4690 int PMacJamIpgVal; /* MAC Jam IPG */
4691 int PMacJamIpgData; /* MAC IPG Jam to Data */
4692+ int PMacBackOffLim; /* MAC Back-off Limit */
4693+ int PMacDataBlind; /* MAC Data Blinder */
4694 int PMacIpgData; /* MAC Data IPG */
4695+ SK_U16 PMacAddr[3]; /* MAC address */
4696 SK_BOOL PMacLimit4; /* reset collision counter and backoff algorithm */
4697 } SK_GEPORT;
4698
4699@@ -379,27 +554,37 @@
4700 int GIChipId; /* Chip Identification Number */
4701 int GIChipRev; /* Chip Revision Number */
4702 SK_U8 GIPciHwRev; /* PCI HW Revision Number */
4703+ SK_U8 GIPciBus; /* PCI Bus Type (PCI / PCI-X / PCI-Express) */
4704+ SK_U8 GIPciMode; /* PCI / PCI-X Mode @ Clock */
4705+ SK_U8 GIPexWidth; /* PCI-Express Negotiated Link Width */
4706 SK_BOOL GIGenesis; /* Genesis adapter ? */
4707- SK_BOOL GIYukon; /* YUKON-A1/Bx chip */
4708+ SK_BOOL GIYukon; /* YUKON family (1 and 2) */
4709 SK_BOOL GIYukonLite; /* YUKON-Lite chip */
4710+ SK_BOOL GIYukon2; /* YUKON-2 chip (-XL, -EC or -FE) */
4711+ SK_U8 GIConTyp; /* Connector Type */
4712+ SK_U8 GIPmdTyp; /* PMD Type */
4713 SK_BOOL GICopperType; /* Copper Type adapter ? */
4714 SK_BOOL GIPciSlot64; /* 64-bit PCI Slot */
4715 SK_BOOL GIPciClock66; /* 66 MHz PCI Clock */
4716 SK_BOOL GIVauxAvail; /* VAUX available (YUKON) */
4717 SK_BOOL GIYukon32Bit; /* 32-Bit YUKON adapter */
4718+ SK_BOOL GIAsfEnabled; /* ASF subsystem enabled */
4719+ SK_BOOL GIAsfRunning; /* ASF subsystem running */
4720 SK_U16 GILedBlinkCtrl; /* LED Blink Control */
4721 int GIMacsFound; /* Number of MACs found on this adapter */
4722 int GIMacType; /* MAC Type used on this adapter */
4723- int GIHstClkFact; /* Host Clock Factor (62.5 / HstClk * 100) */
4724- int GIPortUsage; /* Driver Port Usage */
4725+ int GIChipCap; /* Adapter's Capabilities */
4726+ int GIHstClkFact; /* Host Clock Factor (HstClk / 62.5 * 100) */
4727 int GILevel; /* Initialization Level completed */
4728 int GIRamSize; /* The RAM size of the adapter in kB */
4729 int GIWolOffs; /* WOL Register Offset (HW-Bug in Rev. A) */
4730 SK_U32 GIRamOffs; /* RAM Address Offset for addr calculation */
4731 SK_U32 GIPollTimerVal; /* Descr. Poll Timer Init Val (HstClk ticks) */
4732 SK_U32 GIValIrqMask; /* Value for Interrupt Mask */
4733+ SK_U32 GIValHwIrqMask; /* Value for Interrupt Mask */
4734 SK_U32 GITimeStampCnt; /* Time Stamp High Counter (YUKON only) */
4735 SK_GEPORT GP[SK_MAX_MACS];/* Port Dependent Information */
4736+ SK_HW_FEATURES HwF; /* HW Features struct */
4737 SK_GEMACFUNC GIFunc; /* MAC depedent functions */
4738 } SK_GEINIT;
4739
4740@@ -417,7 +602,7 @@
4741 #define SKERR_HWI_E005 (SKERR_HWI_E004+1)
4742 #define SKERR_HWI_E005MSG "SkGeInitPort(): cannot init running ports"
4743 #define SKERR_HWI_E006 (SKERR_HWI_E005+1)
4744-#define SKERR_HWI_E006MSG "SkGeMacInit(): PState does not match HW state"
4745+#define SKERR_HWI_E006MSG "SkGeInit() called with illegal Chip Id"
4746 #define SKERR_HWI_E007 (SKERR_HWI_E006+1)
4747 #define SKERR_HWI_E007MSG "SkXmInitDupMd() called with invalid Dup Mode"
4748 #define SKERR_HWI_E008 (SKERR_HWI_E007+1)
4749@@ -433,11 +618,11 @@
4750 #define SKERR_HWI_E013 (SKERR_HWI_E012+1)
4751 #define SKERR_HWI_E013MSG "SkGeInitPort(): cfg changed for running queue"
4752 #define SKERR_HWI_E014 (SKERR_HWI_E013+1)
4753-#define SKERR_HWI_E014MSG "SkGeInitPort(): unknown GIPortUsage specified"
4754+#define SKERR_HWI_E014MSG "SkGeInitPort(): unknown PortUsage specified"
4755 #define SKERR_HWI_E015 (SKERR_HWI_E014+1)
4756-#define SKERR_HWI_E015MSG "Illegal Link mode parameter"
4757+#define SKERR_HWI_E015MSG "Illegal Link Mode parameter"
4758 #define SKERR_HWI_E016 (SKERR_HWI_E015+1)
4759-#define SKERR_HWI_E016MSG "Illegal Flow control mode parameter"
4760+#define SKERR_HWI_E016MSG "Illegal Flow Control Mode parameter"
4761 #define SKERR_HWI_E017 (SKERR_HWI_E016+1)
4762 #define SKERR_HWI_E017MSG "Illegal value specified for GIPollTimerVal"
4763 #define SKERR_HWI_E018 (SKERR_HWI_E017+1)
4764@@ -447,9 +632,9 @@
4765 #define SKERR_HWI_E020 (SKERR_HWI_E019+1)
4766 #define SKERR_HWI_E020MSG "Illegal Master/Slave parameter"
4767 #define SKERR_HWI_E021 (SKERR_HWI_E020+1)
4768-#define SKERR_HWI_E021MSG "MacUpdateStats(): cannot update statistic counter"
4769-#define SKERR_HWI_E022 (SKERR_HWI_E021+1)
4770-#define SKERR_HWI_E022MSG "MacStatistic(): illegal statistic base address"
4771+#define SKERR_HWI_E021MSG "MacUpdateStats(): cannot update statistic counter"
4772+#define SKERR_HWI_E022 (SKERR_HWI_E021+1)
4773+#define SKERR_HWI_E022MSG "MacStatistic(): illegal statistic base address"
4774 #define SKERR_HWI_E023 (SKERR_HWI_E022+1)
4775 #define SKERR_HWI_E023MSG "SkGeInitPort(): Transmit Queue Size too small"
4776 #define SKERR_HWI_E024 (SKERR_HWI_E023+1)
4777@@ -464,6 +649,24 @@
4778 /*
4779 * public functions in skgeinit.c
4780 */
4781+extern void SkGePortVlan(
4782+ SK_AC *pAC,
4783+ SK_IOC IoC,
4784+ int Port,
4785+ SK_BOOL Enable);
4786+
4787+extern void SkGeRxRss(
4788+ SK_AC *pAC,
4789+ SK_IOC IoC,
4790+ int Port,
4791+ SK_BOOL Enable);
4792+
4793+extern void SkGeRxCsum(
4794+ SK_AC *pAC,
4795+ SK_IOC IoC,
4796+ int Port,
4797+ SK_BOOL Enable);
4798+
4799 extern void SkGePollRxD(
4800 SK_AC *pAC,
4801 SK_IOC IoC,
4802@@ -528,9 +731,14 @@
4803
4804 extern int SkGeInitAssignRamToQueues(
4805 SK_AC *pAC,
4806- int ActivePort,
4807+ int Port,
4808 SK_BOOL DualNet);
4809
4810+extern int SkYuk2RestartRxBmu(
4811+ SK_AC *pAC,
4812+ SK_IOC IoC,
4813+ int Port);
4814+
4815 /*
4816 * public functions in skxmac2.c
4817 */
4818@@ -601,13 +809,13 @@
4819 int Port,
4820 SK_U16 IStatus);
4821
4822-extern void SkMacSetRxTxEn(
4823+extern void SkMacSetRxTxEn(
4824 SK_AC *pAC,
4825 SK_IOC IoC,
4826 int Port,
4827 int Para);
4828
4829-extern int SkMacRxTxEnable(
4830+extern int SkMacRxTxEnable(
4831 SK_AC *pAC,
4832 SK_IOC IoC,
4833 int Port);
4834@@ -624,28 +832,28 @@
4835 int Port,
4836 SK_BOOL Enable);
4837
4838-extern void SkXmPhyRead(
4839+extern int SkXmPhyRead(
4840 SK_AC *pAC,
4841 SK_IOC IoC,
4842 int Port,
4843 int Addr,
4844 SK_U16 SK_FAR *pVal);
4845
4846-extern void SkXmPhyWrite(
4847+extern int SkXmPhyWrite(
4848 SK_AC *pAC,
4849 SK_IOC IoC,
4850 int Port,
4851 int Addr,
4852 SK_U16 Val);
4853
4854-extern void SkGmPhyRead(
4855+extern int SkGmPhyRead(
4856 SK_AC *pAC,
4857 SK_IOC IoC,
4858 int Port,
4859 int Addr,
4860 SK_U16 SK_FAR *pVal);
4861
4862-extern void SkGmPhyWrite(
4863+extern int SkGmPhyWrite(
4864 SK_AC *pAC,
4865 SK_IOC IoC,
4866 int Port,
4867@@ -713,7 +921,7 @@
4868 SK_AC *pAC,
4869 SK_IOC IoC,
4870 unsigned int Port,
4871- SK_U16 IStatus,
4872+ SK_U16 IStatus,
4873 SK_U64 SK_FAR *pStatus);
4874
4875 extern int SkGmOverflowStatus(
4876@@ -729,6 +937,7 @@
4877 int Port,
4878 SK_BOOL StartTest);
4879
4880+#ifdef SK_PHY_LP_MODE
4881 extern int SkGmEnterLowPowerMode(
4882 SK_AC *pAC,
4883 SK_IOC IoC,
4884@@ -739,6 +948,7 @@
4885 SK_AC *pAC,
4886 SK_IOC IoC,
4887 int Port);
4888+#endif /* SK_PHY_LP_MODE */
4889
4890 #ifdef SK_DIAG
4891 extern void SkGePhyRead(
4892@@ -794,31 +1004,35 @@
4893 extern void SkGeXmitLED();
4894 extern void SkGeInitRamIface();
4895 extern int SkGeInitAssignRamToQueues();
4896+extern void SkGePortVlan();
4897+extern void SkGeRxCsum();
4898+extern void SkGeRxRss();
4899+extern int SkYuk2RestartRxBmu();
4900
4901 /*
4902 * public functions in skxmac2.c
4903 */
4904-extern void SkMacRxTxDisable();
4905+extern void SkMacRxTxDisable();
4906 extern void SkMacSoftRst();
4907 extern void SkMacHardRst();
4908 extern void SkMacClearRst();
4909-extern void SkMacInitPhy();
4910-extern int SkMacRxTxEnable();
4911-extern void SkMacPromiscMode();
4912-extern void SkMacHashing();
4913-extern void SkMacIrqDisable();
4914+extern void SkMacInitPhy();
4915+extern int SkMacRxTxEnable();
4916+extern void SkMacPromiscMode();
4917+extern void SkMacHashing();
4918+extern void SkMacIrqDisable();
4919 extern void SkMacFlushTxFifo();
4920 extern void SkMacFlushRxFifo();
4921 extern void SkMacIrq();
4922 extern int SkMacAutoNegDone();
4923 extern void SkMacAutoNegLipaPhy();
4924-extern void SkMacSetRxTxEn();
4925+extern void SkMacSetRxTxEn();
4926 extern void SkXmInitMac();
4927-extern void SkXmPhyRead();
4928-extern void SkXmPhyWrite();
4929+extern int SkXmPhyRead();
4930+extern int SkXmPhyWrite();
4931 extern void SkGmInitMac();
4932-extern void SkGmPhyRead();
4933-extern void SkGmPhyWrite();
4934+extern int SkGmPhyRead();
4935+extern int SkGmPhyWrite();
4936 extern void SkXmClrExactAddr();
4937 extern void SkXmInitDupMd();
4938 extern void SkXmInitPauseMd();
4939@@ -832,8 +1046,10 @@
4940 extern int SkXmOverflowStatus();
4941 extern int SkGmOverflowStatus();
4942 extern int SkGmCableDiagStatus();
4943+#ifdef SK_PHY_LP_MODE
4944 extern int SkGmEnterLowPowerMode();
4945 extern int SkGmLeaveLowPowerMode();
4946+#endif /* SK_PHY_LP_MODE */
4947
4948 #ifdef SK_DIAG
4949 extern void SkGePhyRead();
4950@@ -844,10 +1060,11 @@
4951 extern void SkXmSendCont();
4952 #endif /* SK_DIAG */
4953
4954-#endif /* SK_KR_PROTO */
4955+#endif /* SK_KR_PROTO */
4956
4957 #ifdef __cplusplus
4958 }
4959 #endif /* __cplusplus */
4960
4961 #endif /* __INC_SKGEINIT_H_ */
4962+
4963diff -ruN linux/drivers/net/sk98lin/h/skgepnm2.h linux-new/drivers/net/sk98lin/h/skgepnm2.h
4964--- linux/drivers/net/sk98lin/h/skgepnm2.h 2006-04-11 19:19:28.000000000 +0200
4965+++ linux-new/drivers/net/sk98lin/h/skgepnm2.h 2006-01-18 14:37:24.000000000 +0100
4966@@ -1,334 +1,339 @@
4967-/*****************************************************************************
4968- *
4969- * Name: skgepnm2.h
4970- * Project: GEnesis, PCI Gigabit Ethernet Adapter
4971- * Version: $Revision$
4972- * Date: $Date$
4973- * Purpose: Defines for Private Network Management Interface
4974- *
4975- ****************************************************************************/
4976-
4977-/******************************************************************************
4978- *
4979- * (C)Copyright 1998-2002 SysKonnect GmbH.
4980- * (C)Copyright 2002-2003 Marvell.
4981- *
4982- * This program is free software; you can redistribute it and/or modify
4983- * it under the terms of the GNU General Public License as published by
4984- * the Free Software Foundation; either version 2 of the License, or
4985- * (at your option) any later version.
4986- *
4987- * The information in this file is provided "AS IS" without warranty.
4988- *
4989- ******************************************************************************/
4990-
4991-#ifndef _SKGEPNM2_H_
4992-#define _SKGEPNM2_H_
4993-
4994-/*
4995- * General definitions
4996- */
4997-#define SK_PNMI_CHIPSET_XMAC 1 /* XMAC11800FP */
4998-#define SK_PNMI_CHIPSET_YUKON 2 /* YUKON */
4999-
5000-#define SK_PNMI_BUS_PCI 1 /* PCI bus*/
5001-
5002-/*
5003- * Actions
5004- */
5005-#define SK_PNMI_ACT_IDLE 1
5006-#define SK_PNMI_ACT_RESET 2
5007-#define SK_PNMI_ACT_SELFTEST 3
5008-#define SK_PNMI_ACT_RESETCNT 4
5009-
5010-/*
5011- * VPD releated defines
5012- */
5013-
5014-#define SK_PNMI_VPD_RW 1
5015-#define SK_PNMI_VPD_RO 2
5016-
5017-#define SK_PNMI_VPD_OK 0
5018-#define SK_PNMI_VPD_NOTFOUND 1
5019-#define SK_PNMI_VPD_CUT 2
5020-#define SK_PNMI_VPD_TIMEOUT 3
5021-#define SK_PNMI_VPD_FULL 4
5022-#define SK_PNMI_VPD_NOWRITE 5
5023-#define SK_PNMI_VPD_FATAL 6
5024-
5025-#define SK_PNMI_VPD_IGNORE 0
5026-#define SK_PNMI_VPD_CREATE 1
5027-#define SK_PNMI_VPD_DELETE 2
5028-
5029-
5030-/*
5031- * RLMT related defines
5032- */
5033-#define SK_PNMI_DEF_RLMT_CHG_THRES 240 /* 4 changes per minute */
5034-
5035-
5036-/*
5037- * VCT internal status values
5038- */
5039-#define SK_PNMI_VCT_PENDING 32
5040-#define SK_PNMI_VCT_TEST_DONE 64
5041-#define SK_PNMI_VCT_LINK 128
5042-
5043-/*
5044- * Internal table definitions
5045- */
5046-#define SK_PNMI_GET 0
5047-#define SK_PNMI_PRESET 1
5048-#define SK_PNMI_SET 2
5049-
5050-#define SK_PNMI_RO 0
5051-#define SK_PNMI_RW 1
5052-#define SK_PNMI_WO 2
5053-
5054-typedef struct s_OidTabEntry {
5055- SK_U32 Id;
5056- SK_U32 InstanceNo;
5057- unsigned int StructSize;
5058- unsigned int Offset;
5059- int Access;
5060- int (* Func)(SK_AC *pAc, SK_IOC pIo, int action,
5061- SK_U32 Id, char* pBuf, unsigned int* pLen,
5062- SK_U32 Instance, unsigned int TableIndex,
5063- SK_U32 NetNumber);
5064- SK_U16 Param;
5065-} SK_PNMI_TAB_ENTRY;
5066-
5067-
5068-/*
5069- * Trap lengths
5070- */
5071-#define SK_PNMI_TRAP_SIMPLE_LEN 17
5072-#define SK_PNMI_TRAP_SENSOR_LEN_BASE 46
5073-#define SK_PNMI_TRAP_RLMT_CHANGE_LEN 23
5074-#define SK_PNMI_TRAP_RLMT_PORT_LEN 23
5075-
5076-/*
5077- * Number of MAC types supported
5078- */
5079-#define SK_PNMI_MAC_TYPES (SK_MAC_GMAC + 1)
5080-
5081-/*
5082- * MAC statistic data list (overall set for MAC types used)
5083- */
5084-enum SK_MACSTATS {
5085- SK_PNMI_HTX = 0,
5086- SK_PNMI_HTX_OCTET,
5087- SK_PNMI_HTX_OCTETHIGH = SK_PNMI_HTX_OCTET,
5088- SK_PNMI_HTX_OCTETLOW,
5089- SK_PNMI_HTX_BROADCAST,
5090- SK_PNMI_HTX_MULTICAST,
5091- SK_PNMI_HTX_UNICAST,
5092- SK_PNMI_HTX_BURST,
5093- SK_PNMI_HTX_PMACC,
5094- SK_PNMI_HTX_MACC,
5095- SK_PNMI_HTX_COL,
5096- SK_PNMI_HTX_SINGLE_COL,
5097- SK_PNMI_HTX_MULTI_COL,
5098- SK_PNMI_HTX_EXCESS_COL,
5099- SK_PNMI_HTX_LATE_COL,
5100- SK_PNMI_HTX_DEFFERAL,
5101- SK_PNMI_HTX_EXCESS_DEF,
5102- SK_PNMI_HTX_UNDERRUN,
5103- SK_PNMI_HTX_CARRIER,
5104- SK_PNMI_HTX_UTILUNDER,
5105- SK_PNMI_HTX_UTILOVER,
5106- SK_PNMI_HTX_64,
5107- SK_PNMI_HTX_127,
5108- SK_PNMI_HTX_255,
5109- SK_PNMI_HTX_511,
5110- SK_PNMI_HTX_1023,
5111- SK_PNMI_HTX_MAX,
5112- SK_PNMI_HTX_LONGFRAMES,
5113- SK_PNMI_HTX_SYNC,
5114- SK_PNMI_HTX_SYNC_OCTET,
5115- SK_PNMI_HTX_RESERVED,
5116-
5117- SK_PNMI_HRX,
5118- SK_PNMI_HRX_OCTET,
5119- SK_PNMI_HRX_OCTETHIGH = SK_PNMI_HRX_OCTET,
5120- SK_PNMI_HRX_OCTETLOW,
5121- SK_PNMI_HRX_BADOCTET,
5122- SK_PNMI_HRX_BADOCTETHIGH = SK_PNMI_HRX_BADOCTET,
5123- SK_PNMI_HRX_BADOCTETLOW,
5124- SK_PNMI_HRX_BROADCAST,
5125- SK_PNMI_HRX_MULTICAST,
5126- SK_PNMI_HRX_UNICAST,
5127- SK_PNMI_HRX_PMACC,
5128- SK_PNMI_HRX_MACC,
5129- SK_PNMI_HRX_PMACC_ERR,
5130- SK_PNMI_HRX_MACC_UNKWN,
5131- SK_PNMI_HRX_BURST,
5132- SK_PNMI_HRX_MISSED,
5133- SK_PNMI_HRX_FRAMING,
5134- SK_PNMI_HRX_UNDERSIZE,
5135- SK_PNMI_HRX_OVERFLOW,
5136- SK_PNMI_HRX_JABBER,
5137- SK_PNMI_HRX_CARRIER,
5138- SK_PNMI_HRX_IRLENGTH,
5139- SK_PNMI_HRX_SYMBOL,
5140- SK_PNMI_HRX_SHORTS,
5141- SK_PNMI_HRX_RUNT,
5142- SK_PNMI_HRX_TOO_LONG,
5143- SK_PNMI_HRX_FCS,
5144- SK_PNMI_HRX_CEXT,
5145- SK_PNMI_HRX_UTILUNDER,
5146- SK_PNMI_HRX_UTILOVER,
5147- SK_PNMI_HRX_64,
5148- SK_PNMI_HRX_127,
5149- SK_PNMI_HRX_255,
5150- SK_PNMI_HRX_511,
5151- SK_PNMI_HRX_1023,
5152- SK_PNMI_HRX_MAX,
5153- SK_PNMI_HRX_LONGFRAMES,
5154-
5155- SK_PNMI_HRX_RESERVED,
5156-
5157- SK_PNMI_MAX_IDX /* NOTE: Ensure SK_PNMI_CNT_NO is set to this value */
5158-};
5159-
5160-/*
5161- * MAC specific data
5162- */
5163-typedef struct s_PnmiStatAddr {
5164- SK_U16 Reg; /* MAC register containing the value */
5165- SK_BOOL GetOffset; /* TRUE: Offset managed by PNMI (call GetStatVal())*/
5166-} SK_PNMI_STATADDR;
5167-
5168-
5169-/*
5170- * SK_PNMI_STRUCT_DATA copy offset evaluation macros
5171- */
5172-#define SK_PNMI_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_STRUCT_DATA *)0)->e))
5173-#define SK_PNMI_MAI_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_STRUCT_DATA *)0)->e))
5174-#define SK_PNMI_VPD_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_VPD *)0)->e))
5175-#define SK_PNMI_SEN_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_SENSOR *)0)->e))
5176-#define SK_PNMI_CHK_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_CHECKSUM *)0)->e))
5177-#define SK_PNMI_STA_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_STAT *)0)->e))
5178-#define SK_PNMI_CNF_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_CONF *)0)->e))
5179-#define SK_PNMI_RLM_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_RLMT *)0)->e))
5180-#define SK_PNMI_MON_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_RLMT_MONITOR *)0)->e))
5181-#define SK_PNMI_TRP_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_TRAP *)0)->e))
5182-
5183-#define SK_PNMI_SET_STAT(b,s,o) {SK_U32 Val32; char *pVal; \
5184- Val32 = (s); \
5185- pVal = (char *)(b) + ((SK_U32)(SK_UPTR) \
5186- &(((SK_PNMI_STRUCT_DATA *)0)-> \
5187- ReturnStatus.ErrorStatus)); \
5188- SK_PNMI_STORE_U32(pVal, Val32); \
5189- Val32 = (o); \
5190- pVal = (char *)(b) + ((SK_U32)(SK_UPTR) \
5191- &(((SK_PNMI_STRUCT_DATA *)0)-> \
5192- ReturnStatus.ErrorOffset)); \
5193- SK_PNMI_STORE_U32(pVal, Val32);}
5194-
5195-/*
5196- * Time macros
5197- */
5198-#ifndef SK_PNMI_HUNDREDS_SEC
5199-#if SK_TICKS_PER_SEC == 100
5200-#define SK_PNMI_HUNDREDS_SEC(t) (t)
5201-#else
5202-#define SK_PNMI_HUNDREDS_SEC(t) (((t) * 100) / (SK_TICKS_PER_SEC))
5203-#endif /* !SK_TICKS_PER_SEC */
5204-#endif /* !SK_PNMI_HUNDREDS_SEC */
5205-
5206-/*
5207- * Macros to work around alignment problems
5208- */
5209-#ifndef SK_PNMI_STORE_U16
5210-#define SK_PNMI_STORE_U16(p,v) {*(char *)(p) = *((char *)&(v)); \
5211- *((char *)(p) + 1) = \
5212- *(((char *)&(v)) + 1);}
5213-#endif
5214-
5215-#ifndef SK_PNMI_STORE_U32
5216-#define SK_PNMI_STORE_U32(p,v) {*(char *)(p) = *((char *)&(v)); \
5217- *((char *)(p) + 1) = \
5218- *(((char *)&(v)) + 1); \
5219- *((char *)(p) + 2) = \
5220- *(((char *)&(v)) + 2); \
5221- *((char *)(p) + 3) = \
5222- *(((char *)&(v)) + 3);}
5223-#endif
5224-
5225-#ifndef SK_PNMI_STORE_U64
5226-#define SK_PNMI_STORE_U64(p,v) {*(char *)(p) = *((char *)&(v)); \
5227- *((char *)(p) + 1) = \
5228- *(((char *)&(v)) + 1); \
5229- *((char *)(p) + 2) = \
5230- *(((char *)&(v)) + 2); \
5231- *((char *)(p) + 3) = \
5232- *(((char *)&(v)) + 3); \
5233- *((char *)(p) + 4) = \
5234- *(((char *)&(v)) + 4); \
5235- *((char *)(p) + 5) = \
5236- *(((char *)&(v)) + 5); \
5237- *((char *)(p) + 6) = \
5238- *(((char *)&(v)) + 6); \
5239- *((char *)(p) + 7) = \
5240- *(((char *)&(v)) + 7);}
5241-#endif
5242-
5243-#ifndef SK_PNMI_READ_U16
5244-#define SK_PNMI_READ_U16(p,v) {*((char *)&(v)) = *(char *)(p); \
5245- *(((char *)&(v)) + 1) = \
5246- *((char *)(p) + 1);}
5247-#endif
5248-
5249-#ifndef SK_PNMI_READ_U32
5250-#define SK_PNMI_READ_U32(p,v) {*((char *)&(v)) = *(char *)(p); \
5251- *(((char *)&(v)) + 1) = \
5252- *((char *)(p) + 1); \
5253- *(((char *)&(v)) + 2) = \
5254- *((char *)(p) + 2); \
5255- *(((char *)&(v)) + 3) = \
5256- *((char *)(p) + 3);}
5257-#endif
5258-
5259-#ifndef SK_PNMI_READ_U64
5260-#define SK_PNMI_READ_U64(p,v) {*((char *)&(v)) = *(char *)(p); \
5261- *(((char *)&(v)) + 1) = \
5262- *((char *)(p) + 1); \
5263- *(((char *)&(v)) + 2) = \
5264- *((char *)(p) + 2); \
5265- *(((char *)&(v)) + 3) = \
5266- *((char *)(p) + 3); \
5267- *(((char *)&(v)) + 4) = \
5268- *((char *)(p) + 4); \
5269- *(((char *)&(v)) + 5) = \
5270- *((char *)(p) + 5); \
5271- *(((char *)&(v)) + 6) = \
5272- *((char *)(p) + 6); \
5273- *(((char *)&(v)) + 7) = \
5274- *((char *)(p) + 7);}
5275-#endif
5276-
5277-/*
5278- * Macros for Debug
5279- */
5280-#ifdef DEBUG
5281-
5282-#define SK_PNMI_CHECKFLAGS(vSt) {if (pAC->Pnmi.MacUpdatedFlag > 0 || \
5283- pAC->Pnmi.RlmtUpdatedFlag > 0 || \
5284- pAC->Pnmi.SirqUpdatedFlag > 0) { \
5285- SK_DBG_MSG(pAC, \
5286- SK_DBGMOD_PNMI, \
5287- SK_DBGCAT_CTRL, \
5288- ("PNMI: ERR: %s MacUFlag=%d, RlmtUFlag=%d, SirqUFlag=%d\n", \
5289- vSt, \
5290- pAC->Pnmi.MacUpdatedFlag, \
5291- pAC->Pnmi.RlmtUpdatedFlag, \
5292- pAC->Pnmi.SirqUpdatedFlag))}}
5293-
5294-#else /* !DEBUG */
5295-
5296-#define SK_PNMI_CHECKFLAGS(vSt) /* Nothing */
5297-
5298-#endif /* !DEBUG */
5299-
5300-#endif /* _SKGEPNM2_H_ */
5301+/*****************************************************************************\r
5302+ *\r
5303+ * Name: skgepnm2.h\r
5304+ * Project: GEnesis, PCI Gigabit Ethernet Adapter\r
5305+ * Version: $Revision$\r
5306+ * Date: $Date$\r
5307+ * Purpose: Defines for Private Network Management Interface\r
5308+ *\r
5309+ ****************************************************************************/\r
5310+\r
5311+/******************************************************************************\r
5312+ *\r
5313+ * (C)Copyright 1998-2002 SysKonnect GmbH.\r
5314+ * (C)Copyright 2002-2003 Marvell.\r
5315+ *\r
5316+ * This program is free software; you can redistribute it and/or modify\r
5317+ * it under the terms of the GNU General Public License as published by\r
5318+ * the Free Software Foundation; either version 2 of the License, or\r
5319+ * (at your option) any later version.\r
5320+ *\r
5321+ * The information in this file is provided "AS IS" without warranty.\r
5322+ *\r
5323+ ******************************************************************************/\r
5324+\r
5325+#ifndef _SKGEPNM2_H_\r
5326+#define _SKGEPNM2_H_\r
5327+\r
5328+/*\r
5329+ * General definitions\r
5330+ */\r
5331+#define SK_PNMI_CHIPSET_XMAC 1 /* XMAC11800FP */\r
5332+#define SK_PNMI_CHIPSET_YUKON 2 /* YUKON */\r
5333+#define SK_PNMI_CHIPSET_YUKON_LITE 3 /* YUKON-Lite (Rev. A1-A3) */\r
5334+#define SK_PNMI_CHIPSET_YUKON_LP 4 /* YUKON-LP */\r
5335+#define SK_PNMI_CHIPSET_YUKON_XL 5 /* YUKON-2 XL */\r
5336+#define SK_PNMI_CHIPSET_YUKON_EC 6 /* YUKON-2 EC */\r
5337+#define SK_PNMI_CHIPSET_YUKON_FE 7 /* YUKON-2 FE */\r
5338+\r
5339+#define SK_PNMI_BUS_PCI 1 /* PCI bus*/\r
5340+\r
5341+/*\r
5342+ * Actions\r
5343+ */\r
5344+#define SK_PNMI_ACT_IDLE 1\r
5345+#define SK_PNMI_ACT_RESET 2\r
5346+#define SK_PNMI_ACT_SELFTEST 3\r
5347+#define SK_PNMI_ACT_RESETCNT 4\r
5348+\r
5349+/*\r
5350+ * VPD releated defines\r
5351+ */\r
5352+\r
5353+#define SK_PNMI_VPD_RW 1\r
5354+#define SK_PNMI_VPD_RO 2\r
5355+\r
5356+#define SK_PNMI_VPD_OK 0\r
5357+#define SK_PNMI_VPD_NOTFOUND 1\r
5358+#define SK_PNMI_VPD_CUT 2\r
5359+#define SK_PNMI_VPD_TIMEOUT 3\r
5360+#define SK_PNMI_VPD_FULL 4\r
5361+#define SK_PNMI_VPD_NOWRITE 5\r
5362+#define SK_PNMI_VPD_FATAL 6\r
5363+\r
5364+#define SK_PNMI_VPD_IGNORE 0\r
5365+#define SK_PNMI_VPD_CREATE 1\r
5366+#define SK_PNMI_VPD_DELETE 2\r
5367+\r
5368+\r
5369+/*\r
5370+ * RLMT related defines\r
5371+ */\r
5372+#define SK_PNMI_DEF_RLMT_CHG_THRES 240 /* 4 changes per minute */\r
5373+\r
5374+\r
5375+/*\r
5376+ * VCT internal status values\r
5377+ */\r
5378+#define SK_PNMI_VCT_PENDING 0x20\r
5379+#define SK_PNMI_VCT_TEST_DONE 0x40\r
5380+#define SK_PNMI_VCT_LINK 0x80\r
5381+\r
5382+/*\r
5383+ * Internal table definitions\r
5384+ */\r
5385+#define SK_PNMI_GET 0\r
5386+#define SK_PNMI_PRESET 1\r
5387+#define SK_PNMI_SET 2\r
5388+\r
5389+#define SK_PNMI_RO 0\r
5390+#define SK_PNMI_RW 1\r
5391+#define SK_PNMI_WO 2\r
5392+\r
5393+typedef struct s_OidTabEntry {\r
5394+ SK_U32 Id;\r
5395+ SK_U32 InstanceNo;\r
5396+ unsigned int StructSize;\r
5397+ unsigned int Offset;\r
5398+ int Access;\r
5399+ int (* Func)(SK_AC *pAc, SK_IOC pIo, int action,\r
5400+ SK_U32 Id, char* pBuf, unsigned int* pLen,\r
5401+ SK_U32 Instance, unsigned int TableIndex,\r
5402+ SK_U32 NetNumber);\r
5403+ SK_U16 Param;\r
5404+} SK_PNMI_TAB_ENTRY;\r
5405+\r
5406+\r
5407+/*\r
5408+ * Trap lengths\r
5409+ */\r
5410+#define SK_PNMI_TRAP_SIMPLE_LEN 17\r
5411+#define SK_PNMI_TRAP_SENSOR_LEN_BASE 46\r
5412+#define SK_PNMI_TRAP_RLMT_CHANGE_LEN 23\r
5413+#define SK_PNMI_TRAP_RLMT_PORT_LEN 23\r
5414+\r
5415+/*\r
5416+ * Number of MAC types supported\r
5417+ */\r
5418+#define SK_PNMI_MAC_TYPES (SK_MAC_GMAC + 1)\r
5419+\r
5420+/*\r
5421+ * MAC statistic data list (overall set for MAC types used)\r
5422+ */\r
5423+enum SK_MACSTATS {\r
5424+ SK_PNMI_HTX = 0,\r
5425+ SK_PNMI_HTX_OCTET,\r
5426+ SK_PNMI_HTX_OCTETHIGH = SK_PNMI_HTX_OCTET,\r
5427+ SK_PNMI_HTX_OCTETLOW,\r
5428+ SK_PNMI_HTX_BROADCAST,\r
5429+ SK_PNMI_HTX_MULTICAST,\r
5430+ SK_PNMI_HTX_UNICAST,\r
5431+ SK_PNMI_HTX_BURST,\r
5432+ SK_PNMI_HTX_PMACC,\r
5433+ SK_PNMI_HTX_MACC,\r
5434+ SK_PNMI_HTX_COL,\r
5435+ SK_PNMI_HTX_SINGLE_COL,\r
5436+ SK_PNMI_HTX_MULTI_COL,\r
5437+ SK_PNMI_HTX_EXCESS_COL,\r
5438+ SK_PNMI_HTX_LATE_COL,\r
5439+ SK_PNMI_HTX_DEFFERAL,\r
5440+ SK_PNMI_HTX_EXCESS_DEF,\r
5441+ SK_PNMI_HTX_UNDERRUN,\r
5442+ SK_PNMI_HTX_CARRIER,\r
5443+ SK_PNMI_HTX_UTILUNDER,\r
5444+ SK_PNMI_HTX_UTILOVER,\r
5445+ SK_PNMI_HTX_64,\r
5446+ SK_PNMI_HTX_127,\r
5447+ SK_PNMI_HTX_255,\r
5448+ SK_PNMI_HTX_511,\r
5449+ SK_PNMI_HTX_1023,\r
5450+ SK_PNMI_HTX_MAX,\r
5451+ SK_PNMI_HTX_LONGFRAMES,\r
5452+ SK_PNMI_HTX_SYNC,\r
5453+ SK_PNMI_HTX_SYNC_OCTET,\r
5454+ SK_PNMI_HTX_RESERVED,\r
5455+ \r
5456+ SK_PNMI_HRX,\r
5457+ SK_PNMI_HRX_OCTET,\r
5458+ SK_PNMI_HRX_OCTETHIGH = SK_PNMI_HRX_OCTET,\r
5459+ SK_PNMI_HRX_OCTETLOW,\r
5460+ SK_PNMI_HRX_BADOCTET,\r
5461+ SK_PNMI_HRX_BADOCTETHIGH = SK_PNMI_HRX_BADOCTET,\r
5462+ SK_PNMI_HRX_BADOCTETLOW,\r
5463+ SK_PNMI_HRX_BROADCAST,\r
5464+ SK_PNMI_HRX_MULTICAST,\r
5465+ SK_PNMI_HRX_UNICAST,\r
5466+ SK_PNMI_HRX_PMACC,\r
5467+ SK_PNMI_HRX_MACC,\r
5468+ SK_PNMI_HRX_PMACC_ERR,\r
5469+ SK_PNMI_HRX_MACC_UNKWN,\r
5470+ SK_PNMI_HRX_BURST,\r
5471+ SK_PNMI_HRX_MISSED,\r
5472+ SK_PNMI_HRX_FRAMING,\r
5473+ SK_PNMI_HRX_UNDERSIZE,\r
5474+ SK_PNMI_HRX_OVERFLOW,\r
5475+ SK_PNMI_HRX_JABBER,\r
5476+ SK_PNMI_HRX_CARRIER,\r
5477+ SK_PNMI_HRX_IRLENGTH,\r
5478+ SK_PNMI_HRX_SYMBOL,\r
5479+ SK_PNMI_HRX_SHORTS,\r
5480+ SK_PNMI_HRX_RUNT,\r
5481+ SK_PNMI_HRX_TOO_LONG,\r
5482+ SK_PNMI_HRX_FCS,\r
5483+ SK_PNMI_HRX_CEXT,\r
5484+ SK_PNMI_HRX_UTILUNDER,\r
5485+ SK_PNMI_HRX_UTILOVER,\r
5486+ SK_PNMI_HRX_64,\r
5487+ SK_PNMI_HRX_127,\r
5488+ SK_PNMI_HRX_255,\r
5489+ SK_PNMI_HRX_511,\r
5490+ SK_PNMI_HRX_1023,\r
5491+ SK_PNMI_HRX_MAX,\r
5492+ SK_PNMI_HRX_LONGFRAMES,\r
5493+ \r
5494+ SK_PNMI_HRX_RESERVED,\r
5495+ \r
5496+ SK_PNMI_MAX_IDX /* NOTE: Ensure SK_PNMI_CNT_NO is set to this value */\r
5497+};\r
5498+\r
5499+/*\r
5500+ * MAC specific data\r
5501+ */\r
5502+typedef struct s_PnmiStatAddr {\r
5503+ SK_U16 Reg; /* MAC register containing the value */\r
5504+ SK_BOOL GetOffset; /* TRUE: Offset managed by PNMI (call GetStatVal())*/\r
5505+} SK_PNMI_STATADDR;\r
5506+\r
5507+\r
5508+/*\r
5509+ * SK_PNMI_STRUCT_DATA copy offset evaluation macros\r
5510+ */\r
5511+#define SK_PNMI_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_STRUCT_DATA *)0)->e))\r
5512+#define SK_PNMI_MAI_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_STRUCT_DATA *)0)->e))\r
5513+#define SK_PNMI_VPD_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_VPD *)0)->e))\r
5514+#define SK_PNMI_SEN_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_SENSOR *)0)->e))\r
5515+#define SK_PNMI_CHK_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_CHECKSUM *)0)->e))\r
5516+#define SK_PNMI_STA_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_STAT *)0)->e))\r
5517+#define SK_PNMI_CNF_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_CONF *)0)->e))\r
5518+#define SK_PNMI_RLM_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_RLMT *)0)->e))\r
5519+#define SK_PNMI_MON_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_RLMT_MONITOR *)0)->e))\r
5520+#define SK_PNMI_TRP_OFF(e) ((SK_U32)(SK_UPTR)&(((SK_PNMI_TRAP *)0)->e))\r
5521+\r
5522+#define SK_PNMI_SET_STAT(b,s,o) {SK_U32 Val32; char *pVal; \\r
5523+ Val32 = (s); \\r
5524+ pVal = (char *)(b) + ((SK_U32)(SK_UPTR) \\r
5525+ &(((SK_PNMI_STRUCT_DATA *)0)-> \\r
5526+ ReturnStatus.ErrorStatus)); \\r
5527+ SK_PNMI_STORE_U32(pVal, Val32); \\r
5528+ Val32 = (o); \\r
5529+ pVal = (char *)(b) + ((SK_U32)(SK_UPTR) \\r
5530+ &(((SK_PNMI_STRUCT_DATA *)0)-> \\r
5531+ ReturnStatus.ErrorOffset)); \\r
5532+ SK_PNMI_STORE_U32(pVal, Val32);}\r
5533+\r
5534+/*\r
5535+ * Time macros\r
5536+ */\r
5537+#ifndef SK_PNMI_HUNDREDS_SEC\r
5538+#if SK_TICKS_PER_SEC == 100\r
5539+#define SK_PNMI_HUNDREDS_SEC(t) (t)\r
5540+#else\r
5541+#define SK_PNMI_HUNDREDS_SEC(t) (((t) * 100) / (SK_TICKS_PER_SEC))\r
5542+#endif /* !SK_TICKS_PER_SEC */\r
5543+#endif /* !SK_PNMI_HUNDREDS_SEC */\r
5544+\r
5545+/*\r
5546+ * Macros to work around alignment problems\r
5547+ */\r
5548+#ifndef SK_PNMI_STORE_U16\r
5549+#define SK_PNMI_STORE_U16(p,v) {*(char *)(p) = *((char *)&(v)); \\r
5550+ *((char *)(p) + 1) = \\r
5551+ *(((char *)&(v)) + 1);}\r
5552+#endif\r
5553+\r
5554+#ifndef SK_PNMI_STORE_U32\r
5555+#define SK_PNMI_STORE_U32(p,v) {*(char *)(p) = *((char *)&(v)); \\r
5556+ *((char *)(p) + 1) = \\r
5557+ *(((char *)&(v)) + 1); \\r
5558+ *((char *)(p) + 2) = \\r
5559+ *(((char *)&(v)) + 2); \\r
5560+ *((char *)(p) + 3) = \\r
5561+ *(((char *)&(v)) + 3);}\r
5562+#endif\r
5563+\r
5564+#ifndef SK_PNMI_STORE_U64\r
5565+#define SK_PNMI_STORE_U64(p,v) {*(char *)(p) = *((char *)&(v)); \\r
5566+ *((char *)(p) + 1) = \\r
5567+ *(((char *)&(v)) + 1); \\r
5568+ *((char *)(p) + 2) = \\r
5569+ *(((char *)&(v)) + 2); \\r
5570+ *((char *)(p) + 3) = \\r
5571+ *(((char *)&(v)) + 3); \\r
5572+ *((char *)(p) + 4) = \\r
5573+ *(((char *)&(v)) + 4); \\r
5574+ *((char *)(p) + 5) = \\r
5575+ *(((char *)&(v)) + 5); \\r
5576+ *((char *)(p) + 6) = \\r
5577+ *(((char *)&(v)) + 6); \\r
5578+ *((char *)(p) + 7) = \\r
5579+ *(((char *)&(v)) + 7);}\r
5580+#endif\r
5581+\r
5582+#ifndef SK_PNMI_READ_U16\r
5583+#define SK_PNMI_READ_U16(p,v) {*((char *)&(v)) = *(char *)(p); \\r
5584+ *(((char *)&(v)) + 1) = \\r
5585+ *((char *)(p) + 1);}\r
5586+#endif\r
5587+\r
5588+#ifndef SK_PNMI_READ_U32\r
5589+#define SK_PNMI_READ_U32(p,v) {*((char *)&(v)) = *(char *)(p); \\r
5590+ *(((char *)&(v)) + 1) = \\r
5591+ *((char *)(p) + 1); \\r
5592+ *(((char *)&(v)) + 2) = \\r
5593+ *((char *)(p) + 2); \\r
5594+ *(((char *)&(v)) + 3) = \\r
5595+ *((char *)(p) + 3);}\r
5596+#endif\r
5597+\r
5598+#ifndef SK_PNMI_READ_U64\r
5599+#define SK_PNMI_READ_U64(p,v) {*((char *)&(v)) = *(char *)(p); \\r
5600+ *(((char *)&(v)) + 1) = \\r
5601+ *((char *)(p) + 1); \\r
5602+ *(((char *)&(v)) + 2) = \\r
5603+ *((char *)(p) + 2); \\r
5604+ *(((char *)&(v)) + 3) = \\r
5605+ *((char *)(p) + 3); \\r
5606+ *(((char *)&(v)) + 4) = \\r
5607+ *((char *)(p) + 4); \\r
5608+ *(((char *)&(v)) + 5) = \\r
5609+ *((char *)(p) + 5); \\r
5610+ *(((char *)&(v)) + 6) = \\r
5611+ *((char *)(p) + 6); \\r
5612+ *(((char *)&(v)) + 7) = \\r
5613+ *((char *)(p) + 7);}\r
5614+#endif\r
5615+\r
5616+/*\r
5617+ * Macros for Debug\r
5618+ */\r
5619+#ifdef DEBUG\r
5620+\r
5621+#define SK_PNMI_CHECKFLAGS(vSt) {if (pAC->Pnmi.MacUpdatedFlag > 0 || \\r
5622+ pAC->Pnmi.RlmtUpdatedFlag > 0 || \\r
5623+ pAC->Pnmi.SirqUpdatedFlag > 0) { \\r
5624+ SK_DBG_MSG(pAC, \\r
5625+ SK_DBGMOD_PNMI, \\r
5626+ SK_DBGCAT_CTRL, \\r
5627+ ("PNMI: ERR: %s MacUFlag=%d, RlmtUFlag=%d, SirqUFlag=%d\n", \\r
5628+ vSt, \\r
5629+ pAC->Pnmi.MacUpdatedFlag, \\r
5630+ pAC->Pnmi.RlmtUpdatedFlag, \\r
5631+ pAC->Pnmi.SirqUpdatedFlag));}}\r
5632+\r
5633+#else /* !DEBUG */\r
5634+\r
5635+#define SK_PNMI_CHECKFLAGS(vSt) /* Nothing */\r
5636+\r
5637+#endif /* !DEBUG */\r
5638+\r
5639+#endif /* _SKGEPNM2_H_ */\r
5640diff -ruN linux/drivers/net/sk98lin/h/skgepnmi.h linux-new/drivers/net/sk98lin/h/skgepnmi.h
5641--- linux/drivers/net/sk98lin/h/skgepnmi.h 2006-04-11 19:19:28.000000000 +0200
5642+++ linux-new/drivers/net/sk98lin/h/skgepnmi.h 2006-01-18 14:37:24.000000000 +0100
5643@@ -1,966 +1,1019 @@
5644-/*****************************************************************************
5645- *
5646- * Name: skgepnmi.h
5647- * Project: GEnesis, PCI Gigabit Ethernet Adapter
5648- * Version: $Revision$
5649- * Date: $Date$
5650- * Purpose: Defines for Private Network Management Interface
5651- *
5652- ****************************************************************************/
5653-
5654-/******************************************************************************
5655- *
5656- * (C)Copyright 1998-2002 SysKonnect GmbH.
5657- * (C)Copyright 2002-2003 Marvell.
5658- *
5659- * This program is free software; you can redistribute it and/or modify
5660- * it under the terms of the GNU General Public License as published by
5661- * the Free Software Foundation; either version 2 of the License, or
5662- * (at your option) any later version.
5663- *
5664- * The information in this file is provided "AS IS" without warranty.
5665- *
5666- ******************************************************************************/
5667-
5668-#ifndef _SKGEPNMI_H_
5669-#define _SKGEPNMI_H_
5670-
5671-/*
5672- * Include dependencies
5673- */
5674-#include "h/sktypes.h"
5675-#include "h/skerror.h"
5676-#include "h/sktimer.h"
5677-#include "h/ski2c.h"
5678-#include "h/skaddr.h"
5679-#include "h/skrlmt.h"
5680-#include "h/skvpd.h"
5681-
5682-/*
5683- * Management Database Version
5684- */
5685-#define SK_PNMI_MDB_VERSION 0x00030001 /* 3.1 */
5686-
5687-
5688-/*
5689- * Event definitions
5690- */
5691-#define SK_PNMI_EVT_SIRQ_OVERFLOW 1 /* Counter overflow */
5692-#define SK_PNMI_EVT_SEN_WAR_LOW 2 /* Lower war thres exceeded */
5693-#define SK_PNMI_EVT_SEN_WAR_UPP 3 /* Upper war thres exceeded */
5694-#define SK_PNMI_EVT_SEN_ERR_LOW 4 /* Lower err thres exceeded */
5695-#define SK_PNMI_EVT_SEN_ERR_UPP 5 /* Upper err thres exceeded */
5696-#define SK_PNMI_EVT_CHG_EST_TIMER 6 /* Timer event for RLMT Chg */
5697-#define SK_PNMI_EVT_UTILIZATION_TIMER 7 /* Timer event for Utiliza. */
5698-#define SK_PNMI_EVT_CLEAR_COUNTER 8 /* Clear statistic counters */
5699-#define SK_PNMI_EVT_XMAC_RESET 9 /* XMAC will be reset */
5700-
5701-#define SK_PNMI_EVT_RLMT_PORT_UP 10 /* Port came logically up */
5702-#define SK_PNMI_EVT_RLMT_PORT_DOWN 11 /* Port went logically down */
5703-#define SK_PNMI_EVT_RLMT_SEGMENTATION 13 /* Two SP root bridges found */
5704-#define SK_PNMI_EVT_RLMT_ACTIVE_DOWN 14 /* Port went logically down */
5705-#define SK_PNMI_EVT_RLMT_ACTIVE_UP 15 /* Port came logically up */
5706-#define SK_PNMI_EVT_RLMT_SET_NETS 16 /* 1. Parameter is number of nets
5707- 1 = single net; 2 = dual net */
5708-#define SK_PNMI_EVT_VCT_RESET 17 /* VCT port reset timer event started with SET. */
5709-
5710-
5711-/*
5712- * Return values
5713- */
5714-#define SK_PNMI_ERR_OK 0
5715-#define SK_PNMI_ERR_GENERAL 1
5716-#define SK_PNMI_ERR_TOO_SHORT 2
5717-#define SK_PNMI_ERR_BAD_VALUE 3
5718-#define SK_PNMI_ERR_READ_ONLY 4
5719-#define SK_PNMI_ERR_UNKNOWN_OID 5
5720-#define SK_PNMI_ERR_UNKNOWN_INST 6
5721-#define SK_PNMI_ERR_UNKNOWN_NET 7
5722-#define SK_PNMI_ERR_NOT_SUPPORTED 10
5723-
5724-
5725-/*
5726- * Return values of driver reset function SK_DRIVER_RESET() and
5727- * driver event function SK_DRIVER_EVENT()
5728- */
5729-#define SK_PNMI_ERR_OK 0
5730-#define SK_PNMI_ERR_FAIL 1
5731-
5732-
5733-/*
5734- * Return values of driver test function SK_DRIVER_SELFTEST()
5735- */
5736-#define SK_PNMI_TST_UNKNOWN (1 << 0)
5737-#define SK_PNMI_TST_TRANCEIVER (1 << 1)
5738-#define SK_PNMI_TST_ASIC (1 << 2)
5739-#define SK_PNMI_TST_SENSOR (1 << 3)
5740-#define SK_PNMI_TST_POWERMGMT (1 << 4)
5741-#define SK_PNMI_TST_PCI (1 << 5)
5742-#define SK_PNMI_TST_MAC (1 << 6)
5743-
5744-
5745-/*
5746- * RLMT specific definitions
5747- */
5748-#define SK_PNMI_RLMT_STATUS_STANDBY 1
5749-#define SK_PNMI_RLMT_STATUS_ACTIVE 2
5750-#define SK_PNMI_RLMT_STATUS_ERROR 3
5751-
5752-#define SK_PNMI_RLMT_LSTAT_PHY_DOWN 1
5753-#define SK_PNMI_RLMT_LSTAT_AUTONEG 2
5754-#define SK_PNMI_RLMT_LSTAT_LOG_DOWN 3
5755-#define SK_PNMI_RLMT_LSTAT_LOG_UP 4
5756-#define SK_PNMI_RLMT_LSTAT_INDETERMINATED 5
5757-
5758-#define SK_PNMI_RLMT_MODE_CHK_LINK (SK_RLMT_CHECK_LINK)
5759-#define SK_PNMI_RLMT_MODE_CHK_RX (SK_RLMT_CHECK_LOC_LINK)
5760-#define SK_PNMI_RLMT_MODE_CHK_SPT (SK_RLMT_CHECK_SEG)
5761-/* #define SK_PNMI_RLMT_MODE_CHK_EX */
5762-
5763-/*
5764- * OID definition
5765- */
5766-#ifndef _NDIS_ /* Check, whether NDIS already included OIDs */
5767-
5768-#define OID_GEN_XMIT_OK 0x00020101
5769-#define OID_GEN_RCV_OK 0x00020102
5770-#define OID_GEN_XMIT_ERROR 0x00020103
5771-#define OID_GEN_RCV_ERROR 0x00020104
5772-#define OID_GEN_RCV_NO_BUFFER 0x00020105
5773-
5774-/* #define OID_GEN_DIRECTED_BYTES_XMIT 0x00020201 */
5775-#define OID_GEN_DIRECTED_FRAMES_XMIT 0x00020202
5776-/* #define OID_GEN_MULTICAST_BYTES_XMIT 0x00020203 */
5777-#define OID_GEN_MULTICAST_FRAMES_XMIT 0x00020204
5778-/* #define OID_GEN_BROADCAST_BYTES_XMIT 0x00020205 */
5779-#define OID_GEN_BROADCAST_FRAMES_XMIT 0x00020206
5780-/* #define OID_GEN_DIRECTED_BYTES_RCV 0x00020207 */
5781-#define OID_GEN_DIRECTED_FRAMES_RCV 0x00020208
5782-/* #define OID_GEN_MULTICAST_BYTES_RCV 0x00020209 */
5783-#define OID_GEN_MULTICAST_FRAMES_RCV 0x0002020A
5784-/* #define OID_GEN_BROADCAST_BYTES_RCV 0x0002020B */
5785-#define OID_GEN_BROADCAST_FRAMES_RCV 0x0002020C
5786-#define OID_GEN_RCV_CRC_ERROR 0x0002020D
5787-#define OID_GEN_TRANSMIT_QUEUE_LENGTH 0x0002020E
5788-
5789-#define OID_802_3_PERMANENT_ADDRESS 0x01010101
5790-#define OID_802_3_CURRENT_ADDRESS 0x01010102
5791-/* #define OID_802_3_MULTICAST_LIST 0x01010103 */
5792-/* #define OID_802_3_MAXIMUM_LIST_SIZE 0x01010104 */
5793-/* #define OID_802_3_MAC_OPTIONS 0x01010105 */
5794-
5795-#define OID_802_3_RCV_ERROR_ALIGNMENT 0x01020101
5796-#define OID_802_3_XMIT_ONE_COLLISION 0x01020102
5797-#define OID_802_3_XMIT_MORE_COLLISIONS 0x01020103
5798-#define OID_802_3_XMIT_DEFERRED 0x01020201
5799-#define OID_802_3_XMIT_MAX_COLLISIONS 0x01020202
5800-#define OID_802_3_RCV_OVERRUN 0x01020203
5801-#define OID_802_3_XMIT_UNDERRUN 0x01020204
5802-#define OID_802_3_XMIT_TIMES_CRS_LOST 0x01020206
5803-#define OID_802_3_XMIT_LATE_COLLISIONS 0x01020207
5804-
5805-/*
5806- * PnP and PM OIDs
5807- */
5808-#ifdef SK_POWER_MGMT
5809-#define OID_PNP_CAPABILITIES 0xFD010100
5810-#define OID_PNP_SET_POWER 0xFD010101
5811-#define OID_PNP_QUERY_POWER 0xFD010102
5812-#define OID_PNP_ADD_WAKE_UP_PATTERN 0xFD010103
5813-#define OID_PNP_REMOVE_WAKE_UP_PATTERN 0xFD010104
5814-#define OID_PNP_ENABLE_WAKE_UP 0xFD010106
5815-#endif /* SK_POWER_MGMT */
5816-
5817-#endif /* _NDIS_ */
5818-
5819-#define OID_SKGE_MDB_VERSION 0xFF010100
5820-#define OID_SKGE_SUPPORTED_LIST 0xFF010101
5821-#define OID_SKGE_VPD_FREE_BYTES 0xFF010102
5822-#define OID_SKGE_VPD_ENTRIES_LIST 0xFF010103
5823-#define OID_SKGE_VPD_ENTRIES_NUMBER 0xFF010104
5824-#define OID_SKGE_VPD_KEY 0xFF010105
5825-#define OID_SKGE_VPD_VALUE 0xFF010106
5826-#define OID_SKGE_VPD_ACCESS 0xFF010107
5827-#define OID_SKGE_VPD_ACTION 0xFF010108
5828-
5829-#define OID_SKGE_PORT_NUMBER 0xFF010110
5830-#define OID_SKGE_DEVICE_TYPE 0xFF010111
5831-#define OID_SKGE_DRIVER_DESCR 0xFF010112
5832-#define OID_SKGE_DRIVER_VERSION 0xFF010113
5833-#define OID_SKGE_HW_DESCR 0xFF010114
5834-#define OID_SKGE_HW_VERSION 0xFF010115
5835-#define OID_SKGE_CHIPSET 0xFF010116
5836-#define OID_SKGE_ACTION 0xFF010117
5837-#define OID_SKGE_RESULT 0xFF010118
5838-#define OID_SKGE_BUS_TYPE 0xFF010119
5839-#define OID_SKGE_BUS_SPEED 0xFF01011A
5840-#define OID_SKGE_BUS_WIDTH 0xFF01011B
5841-/* 0xFF01011C unused */
5842-#define OID_SKGE_DIAG_ACTION 0xFF01011D
5843-#define OID_SKGE_DIAG_RESULT 0xFF01011E
5844-#define OID_SKGE_MTU 0xFF01011F
5845-#define OID_SKGE_PHYS_CUR_ADDR 0xFF010120
5846-#define OID_SKGE_PHYS_FAC_ADDR 0xFF010121
5847-#define OID_SKGE_PMD 0xFF010122
5848-#define OID_SKGE_CONNECTOR 0xFF010123
5849-#define OID_SKGE_LINK_CAP 0xFF010124
5850-#define OID_SKGE_LINK_MODE 0xFF010125
5851-#define OID_SKGE_LINK_MODE_STATUS 0xFF010126
5852-#define OID_SKGE_LINK_STATUS 0xFF010127
5853-#define OID_SKGE_FLOWCTRL_CAP 0xFF010128
5854-#define OID_SKGE_FLOWCTRL_MODE 0xFF010129
5855-#define OID_SKGE_FLOWCTRL_STATUS 0xFF01012A
5856-#define OID_SKGE_PHY_OPERATION_CAP 0xFF01012B
5857-#define OID_SKGE_PHY_OPERATION_MODE 0xFF01012C
5858-#define OID_SKGE_PHY_OPERATION_STATUS 0xFF01012D
5859-#define OID_SKGE_MULTICAST_LIST 0xFF01012E
5860-#define OID_SKGE_CURRENT_PACKET_FILTER 0xFF01012F
5861-
5862-#define OID_SKGE_TRAP 0xFF010130
5863-#define OID_SKGE_TRAP_NUMBER 0xFF010131
5864-
5865-#define OID_SKGE_RLMT_MODE 0xFF010140
5866-#define OID_SKGE_RLMT_PORT_NUMBER 0xFF010141
5867-#define OID_SKGE_RLMT_PORT_ACTIVE 0xFF010142
5868-#define OID_SKGE_RLMT_PORT_PREFERRED 0xFF010143
5869-#define OID_SKGE_INTERMEDIATE_SUPPORT 0xFF010160
5870-
5871-#define OID_SKGE_SPEED_CAP 0xFF010170
5872-#define OID_SKGE_SPEED_MODE 0xFF010171
5873-#define OID_SKGE_SPEED_STATUS 0xFF010172
5874-
5875-#define OID_SKGE_BOARDLEVEL 0xFF010180
5876-
5877-#define OID_SKGE_SENSOR_NUMBER 0xFF020100
5878-#define OID_SKGE_SENSOR_INDEX 0xFF020101
5879-#define OID_SKGE_SENSOR_DESCR 0xFF020102
5880-#define OID_SKGE_SENSOR_TYPE 0xFF020103
5881-#define OID_SKGE_SENSOR_VALUE 0xFF020104
5882-#define OID_SKGE_SENSOR_WAR_THRES_LOW 0xFF020105
5883-#define OID_SKGE_SENSOR_WAR_THRES_UPP 0xFF020106
5884-#define OID_SKGE_SENSOR_ERR_THRES_LOW 0xFF020107
5885-#define OID_SKGE_SENSOR_ERR_THRES_UPP 0xFF020108
5886-#define OID_SKGE_SENSOR_STATUS 0xFF020109
5887-#define OID_SKGE_SENSOR_WAR_CTS 0xFF02010A
5888-#define OID_SKGE_SENSOR_ERR_CTS 0xFF02010B
5889-#define OID_SKGE_SENSOR_WAR_TIME 0xFF02010C
5890-#define OID_SKGE_SENSOR_ERR_TIME 0xFF02010D
5891-
5892-#define OID_SKGE_CHKSM_NUMBER 0xFF020110
5893-#define OID_SKGE_CHKSM_RX_OK_CTS 0xFF020111
5894-#define OID_SKGE_CHKSM_RX_UNABLE_CTS 0xFF020112
5895-#define OID_SKGE_CHKSM_RX_ERR_CTS 0xFF020113
5896-#define OID_SKGE_CHKSM_TX_OK_CTS 0xFF020114
5897-#define OID_SKGE_CHKSM_TX_UNABLE_CTS 0xFF020115
5898-
5899-#define OID_SKGE_STAT_TX 0xFF020120
5900-#define OID_SKGE_STAT_TX_OCTETS 0xFF020121
5901-#define OID_SKGE_STAT_TX_BROADCAST 0xFF020122
5902-#define OID_SKGE_STAT_TX_MULTICAST 0xFF020123
5903-#define OID_SKGE_STAT_TX_UNICAST 0xFF020124
5904-#define OID_SKGE_STAT_TX_LONGFRAMES 0xFF020125
5905-#define OID_SKGE_STAT_TX_BURST 0xFF020126
5906-#define OID_SKGE_STAT_TX_PFLOWC 0xFF020127
5907-#define OID_SKGE_STAT_TX_FLOWC 0xFF020128
5908-#define OID_SKGE_STAT_TX_SINGLE_COL 0xFF020129
5909-#define OID_SKGE_STAT_TX_MULTI_COL 0xFF02012A
5910-#define OID_SKGE_STAT_TX_EXCESS_COL 0xFF02012B
5911-#define OID_SKGE_STAT_TX_LATE_COL 0xFF02012C
5912-#define OID_SKGE_STAT_TX_DEFFERAL 0xFF02012D
5913-#define OID_SKGE_STAT_TX_EXCESS_DEF 0xFF02012E
5914-#define OID_SKGE_STAT_TX_UNDERRUN 0xFF02012F
5915-#define OID_SKGE_STAT_TX_CARRIER 0xFF020130
5916-/* #define OID_SKGE_STAT_TX_UTIL 0xFF020131 */
5917-#define OID_SKGE_STAT_TX_64 0xFF020132
5918-#define OID_SKGE_STAT_TX_127 0xFF020133
5919-#define OID_SKGE_STAT_TX_255 0xFF020134
5920-#define OID_SKGE_STAT_TX_511 0xFF020135
5921-#define OID_SKGE_STAT_TX_1023 0xFF020136
5922-#define OID_SKGE_STAT_TX_MAX 0xFF020137
5923-#define OID_SKGE_STAT_TX_SYNC 0xFF020138
5924-#define OID_SKGE_STAT_TX_SYNC_OCTETS 0xFF020139
5925-#define OID_SKGE_STAT_RX 0xFF02013A
5926-#define OID_SKGE_STAT_RX_OCTETS 0xFF02013B
5927-#define OID_SKGE_STAT_RX_BROADCAST 0xFF02013C
5928-#define OID_SKGE_STAT_RX_MULTICAST 0xFF02013D
5929-#define OID_SKGE_STAT_RX_UNICAST 0xFF02013E
5930-#define OID_SKGE_STAT_RX_PFLOWC 0xFF02013F
5931-#define OID_SKGE_STAT_RX_FLOWC 0xFF020140
5932-#define OID_SKGE_STAT_RX_PFLOWC_ERR 0xFF020141
5933-#define OID_SKGE_STAT_RX_FLOWC_UNKWN 0xFF020142
5934-#define OID_SKGE_STAT_RX_BURST 0xFF020143
5935-#define OID_SKGE_STAT_RX_MISSED 0xFF020144
5936-#define OID_SKGE_STAT_RX_FRAMING 0xFF020145
5937-#define OID_SKGE_STAT_RX_OVERFLOW 0xFF020146
5938-#define OID_SKGE_STAT_RX_JABBER 0xFF020147
5939-#define OID_SKGE_STAT_RX_CARRIER 0xFF020148
5940-#define OID_SKGE_STAT_RX_IR_LENGTH 0xFF020149
5941-#define OID_SKGE_STAT_RX_SYMBOL 0xFF02014A
5942-#define OID_SKGE_STAT_RX_SHORTS 0xFF02014B
5943-#define OID_SKGE_STAT_RX_RUNT 0xFF02014C
5944-#define OID_SKGE_STAT_RX_CEXT 0xFF02014D
5945-#define OID_SKGE_STAT_RX_TOO_LONG 0xFF02014E
5946-#define OID_SKGE_STAT_RX_FCS 0xFF02014F
5947-/* #define OID_SKGE_STAT_RX_UTIL 0xFF020150 */
5948-#define OID_SKGE_STAT_RX_64 0xFF020151
5949-#define OID_SKGE_STAT_RX_127 0xFF020152
5950-#define OID_SKGE_STAT_RX_255 0xFF020153
5951-#define OID_SKGE_STAT_RX_511 0xFF020154
5952-#define OID_SKGE_STAT_RX_1023 0xFF020155
5953-#define OID_SKGE_STAT_RX_MAX 0xFF020156
5954-#define OID_SKGE_STAT_RX_LONGFRAMES 0xFF020157
5955-
5956-#define OID_SKGE_RLMT_CHANGE_CTS 0xFF020160
5957-#define OID_SKGE_RLMT_CHANGE_TIME 0xFF020161
5958-#define OID_SKGE_RLMT_CHANGE_ESTIM 0xFF020162
5959-#define OID_SKGE_RLMT_CHANGE_THRES 0xFF020163
5960-
5961-#define OID_SKGE_RLMT_PORT_INDEX 0xFF020164
5962-#define OID_SKGE_RLMT_STATUS 0xFF020165
5963-#define OID_SKGE_RLMT_TX_HELLO_CTS 0xFF020166
5964-#define OID_SKGE_RLMT_RX_HELLO_CTS 0xFF020167
5965-#define OID_SKGE_RLMT_TX_SP_REQ_CTS 0xFF020168
5966-#define OID_SKGE_RLMT_RX_SP_CTS 0xFF020169
5967-
5968-#define OID_SKGE_RLMT_MONITOR_NUMBER 0xFF010150
5969-#define OID_SKGE_RLMT_MONITOR_INDEX 0xFF010151
5970-#define OID_SKGE_RLMT_MONITOR_ADDR 0xFF010152
5971-#define OID_SKGE_RLMT_MONITOR_ERRS 0xFF010153
5972-#define OID_SKGE_RLMT_MONITOR_TIMESTAMP 0xFF010154
5973-#define OID_SKGE_RLMT_MONITOR_ADMIN 0xFF010155
5974-
5975-#define OID_SKGE_TX_SW_QUEUE_LEN 0xFF020170
5976-#define OID_SKGE_TX_SW_QUEUE_MAX 0xFF020171
5977-#define OID_SKGE_TX_RETRY 0xFF020172
5978-#define OID_SKGE_RX_INTR_CTS 0xFF020173
5979-#define OID_SKGE_TX_INTR_CTS 0xFF020174
5980-#define OID_SKGE_RX_NO_BUF_CTS 0xFF020175
5981-#define OID_SKGE_TX_NO_BUF_CTS 0xFF020176
5982-#define OID_SKGE_TX_USED_DESCR_NO 0xFF020177
5983-#define OID_SKGE_RX_DELIVERED_CTS 0xFF020178
5984-#define OID_SKGE_RX_OCTETS_DELIV_CTS 0xFF020179
5985-#define OID_SKGE_RX_HW_ERROR_CTS 0xFF02017A
5986-#define OID_SKGE_TX_HW_ERROR_CTS 0xFF02017B
5987-#define OID_SKGE_IN_ERRORS_CTS 0xFF02017C
5988-#define OID_SKGE_OUT_ERROR_CTS 0xFF02017D
5989-#define OID_SKGE_ERR_RECOVERY_CTS 0xFF02017E
5990-#define OID_SKGE_SYSUPTIME 0xFF02017F
5991-
5992-#define OID_SKGE_ALL_DATA 0xFF020190
5993-
5994-/* Defines for VCT. */
5995-#define OID_SKGE_VCT_GET 0xFF020200
5996-#define OID_SKGE_VCT_SET 0xFF020201
5997-#define OID_SKGE_VCT_STATUS 0xFF020202
5998-
5999-#ifdef SK_DIAG_SUPPORT
6000-/* Defines for driver DIAG mode. */
6001-#define OID_SKGE_DIAG_MODE 0xFF020204
6002-#endif /* SK_DIAG_SUPPORT */
6003-
6004-/* New OIDs */
6005-#define OID_SKGE_DRIVER_RELDATE 0xFF020210
6006-#define OID_SKGE_DRIVER_FILENAME 0xFF020211
6007-#define OID_SKGE_CHIPID 0xFF020212
6008-#define OID_SKGE_RAMSIZE 0xFF020213
6009-#define OID_SKGE_VAUXAVAIL 0xFF020214
6010-#define OID_SKGE_PHY_TYPE 0xFF020215
6011-#define OID_SKGE_PHY_LP_MODE 0xFF020216
6012-
6013-/* VCT struct to store a backup copy of VCT data after a port reset. */
6014-typedef struct s_PnmiVct {
6015- SK_U8 VctStatus;
6016- SK_U8 PCableLen;
6017- SK_U32 PMdiPairLen[4];
6018- SK_U8 PMdiPairSts[4];
6019-} SK_PNMI_VCT;
6020-
6021-
6022-/* VCT status values (to be given to CPA via OID_SKGE_VCT_STATUS). */
6023-#define SK_PNMI_VCT_NONE 0
6024-#define SK_PNMI_VCT_OLD_VCT_DATA 1
6025-#define SK_PNMI_VCT_NEW_VCT_DATA 2
6026-#define SK_PNMI_VCT_OLD_DSP_DATA 4
6027-#define SK_PNMI_VCT_NEW_DSP_DATA 8
6028-#define SK_PNMI_VCT_RUNNING 16
6029-
6030-
6031-/* VCT cable test status. */
6032-#define SK_PNMI_VCT_NORMAL_CABLE 0
6033-#define SK_PNMI_VCT_SHORT_CABLE 1
6034-#define SK_PNMI_VCT_OPEN_CABLE 2
6035-#define SK_PNMI_VCT_TEST_FAIL 3
6036-#define SK_PNMI_VCT_IMPEDANCE_MISMATCH 4
6037-
6038-#define OID_SKGE_TRAP_SEN_WAR_LOW 500
6039-#define OID_SKGE_TRAP_SEN_WAR_UPP 501
6040-#define OID_SKGE_TRAP_SEN_ERR_LOW 502
6041-#define OID_SKGE_TRAP_SEN_ERR_UPP 503
6042-#define OID_SKGE_TRAP_RLMT_CHANGE_THRES 520
6043-#define OID_SKGE_TRAP_RLMT_CHANGE_PORT 521
6044-#define OID_SKGE_TRAP_RLMT_PORT_DOWN 522
6045-#define OID_SKGE_TRAP_RLMT_PORT_UP 523
6046-#define OID_SKGE_TRAP_RLMT_SEGMENTATION 524
6047-
6048-#ifdef SK_DIAG_SUPPORT
6049-/* Defines for driver DIAG mode. */
6050-#define SK_DIAG_ATTACHED 2
6051-#define SK_DIAG_RUNNING 1
6052-#define SK_DIAG_IDLE 0
6053-#endif /* SK_DIAG_SUPPORT */
6054-
6055-/*
6056- * Generic PNMI IOCTL subcommand definitions.
6057- */
6058-#define SK_GET_SINGLE_VAR 1
6059-#define SK_SET_SINGLE_VAR 2
6060-#define SK_PRESET_SINGLE_VAR 3
6061-#define SK_GET_FULL_MIB 4
6062-#define SK_SET_FULL_MIB 5
6063-#define SK_PRESET_FULL_MIB 6
6064-
6065-
6066-/*
6067- * Define error numbers and messages for syslog
6068- */
6069-#define SK_PNMI_ERR001 (SK_ERRBASE_PNMI + 1)
6070-#define SK_PNMI_ERR001MSG "SkPnmiGetStruct: Unknown OID"
6071-#define SK_PNMI_ERR002 (SK_ERRBASE_PNMI + 2)
6072-#define SK_PNMI_ERR002MSG "SkPnmiGetStruct: Cannot read VPD keys"
6073-#define SK_PNMI_ERR003 (SK_ERRBASE_PNMI + 3)
6074-#define SK_PNMI_ERR003MSG "OidStruct: Called with wrong OID"
6075-#define SK_PNMI_ERR004 (SK_ERRBASE_PNMI + 4)
6076-#define SK_PNMI_ERR004MSG "OidStruct: Called with wrong action"
6077-#define SK_PNMI_ERR005 (SK_ERRBASE_PNMI + 5)
6078-#define SK_PNMI_ERR005MSG "Perform: Cannot reset driver"
6079-#define SK_PNMI_ERR006 (SK_ERRBASE_PNMI + 6)
6080-#define SK_PNMI_ERR006MSG "Perform: Unknown OID action command"
6081-#define SK_PNMI_ERR007 (SK_ERRBASE_PNMI + 7)
6082-#define SK_PNMI_ERR007MSG "General: Driver description not initialized"
6083-#define SK_PNMI_ERR008 (SK_ERRBASE_PNMI + 8)
6084-#define SK_PNMI_ERR008MSG "Addr: Tried to get unknown OID"
6085-#define SK_PNMI_ERR009 (SK_ERRBASE_PNMI + 9)
6086-#define SK_PNMI_ERR009MSG "Addr: Unknown OID"
6087-#define SK_PNMI_ERR010 (SK_ERRBASE_PNMI + 10)
6088-#define SK_PNMI_ERR010MSG "CsumStat: Unknown OID"
6089-#define SK_PNMI_ERR011 (SK_ERRBASE_PNMI + 11)
6090-#define SK_PNMI_ERR011MSG "SensorStat: Sensor descr string too long"
6091-#define SK_PNMI_ERR012 (SK_ERRBASE_PNMI + 12)
6092-#define SK_PNMI_ERR012MSG "SensorStat: Unknown OID"
6093-#define SK_PNMI_ERR013 (SK_ERRBASE_PNMI + 13)
6094-#define SK_PNMI_ERR013MSG ""
6095-#define SK_PNMI_ERR014 (SK_ERRBASE_PNMI + 14)
6096-#define SK_PNMI_ERR014MSG "Vpd: Cannot read VPD keys"
6097-#define SK_PNMI_ERR015 (SK_ERRBASE_PNMI + 15)
6098-#define SK_PNMI_ERR015MSG "Vpd: Internal array for VPD keys to small"
6099-#define SK_PNMI_ERR016 (SK_ERRBASE_PNMI + 16)
6100-#define SK_PNMI_ERR016MSG "Vpd: Key string too long"
6101-#define SK_PNMI_ERR017 (SK_ERRBASE_PNMI + 17)
6102-#define SK_PNMI_ERR017MSG "Vpd: Invalid VPD status pointer"
6103-#define SK_PNMI_ERR018 (SK_ERRBASE_PNMI + 18)
6104-#define SK_PNMI_ERR018MSG "Vpd: VPD data not valid"
6105-#define SK_PNMI_ERR019 (SK_ERRBASE_PNMI + 19)
6106-#define SK_PNMI_ERR019MSG "Vpd: VPD entries list string too long"
6107-#define SK_PNMI_ERR021 (SK_ERRBASE_PNMI + 21)
6108-#define SK_PNMI_ERR021MSG "Vpd: VPD data string too long"
6109-#define SK_PNMI_ERR022 (SK_ERRBASE_PNMI + 22)
6110-#define SK_PNMI_ERR022MSG "Vpd: VPD data string too long should be errored before"
6111-#define SK_PNMI_ERR023 (SK_ERRBASE_PNMI + 23)
6112-#define SK_PNMI_ERR023MSG "Vpd: Unknown OID in get action"
6113-#define SK_PNMI_ERR024 (SK_ERRBASE_PNMI + 24)
6114-#define SK_PNMI_ERR024MSG "Vpd: Unknown OID in preset/set action"
6115-#define SK_PNMI_ERR025 (SK_ERRBASE_PNMI + 25)
6116-#define SK_PNMI_ERR025MSG "Vpd: Cannot write VPD after modify entry"
6117-#define SK_PNMI_ERR026 (SK_ERRBASE_PNMI + 26)
6118-#define SK_PNMI_ERR026MSG "Vpd: Cannot update VPD"
6119-#define SK_PNMI_ERR027 (SK_ERRBASE_PNMI + 27)
6120-#define SK_PNMI_ERR027MSG "Vpd: Cannot delete VPD entry"
6121-#define SK_PNMI_ERR028 (SK_ERRBASE_PNMI + 28)
6122-#define SK_PNMI_ERR028MSG "Vpd: Cannot update VPD after delete entry"
6123-#define SK_PNMI_ERR029 (SK_ERRBASE_PNMI + 29)
6124-#define SK_PNMI_ERR029MSG "General: Driver description string too long"
6125-#define SK_PNMI_ERR030 (SK_ERRBASE_PNMI + 30)
6126-#define SK_PNMI_ERR030MSG "General: Driver version not initialized"
6127-#define SK_PNMI_ERR031 (SK_ERRBASE_PNMI + 31)
6128-#define SK_PNMI_ERR031MSG "General: Driver version string too long"
6129-#define SK_PNMI_ERR032 (SK_ERRBASE_PNMI + 32)
6130-#define SK_PNMI_ERR032MSG "General: Cannot read VPD Name for HW descr"
6131-#define SK_PNMI_ERR033 (SK_ERRBASE_PNMI + 33)
6132-#define SK_PNMI_ERR033MSG "General: HW description string too long"
6133-#define SK_PNMI_ERR034 (SK_ERRBASE_PNMI + 34)
6134-#define SK_PNMI_ERR034MSG "General: Unknown OID"
6135-#define SK_PNMI_ERR035 (SK_ERRBASE_PNMI + 35)
6136-#define SK_PNMI_ERR035MSG "Rlmt: Unknown OID"
6137-#define SK_PNMI_ERR036 (SK_ERRBASE_PNMI + 36)
6138-#define SK_PNMI_ERR036MSG ""
6139-#define SK_PNMI_ERR037 (SK_ERRBASE_PNMI + 37)
6140-#define SK_PNMI_ERR037MSG "Rlmt: SK_RLMT_MODE_CHANGE event return not 0"
6141-#define SK_PNMI_ERR038 (SK_ERRBASE_PNMI + 38)
6142-#define SK_PNMI_ERR038MSG "Rlmt: SK_RLMT_PREFPORT_CHANGE event return not 0"
6143-#define SK_PNMI_ERR039 (SK_ERRBASE_PNMI + 39)
6144-#define SK_PNMI_ERR039MSG "RlmtStat: Unknown OID"
6145-#define SK_PNMI_ERR040 (SK_ERRBASE_PNMI + 40)
6146-#define SK_PNMI_ERR040MSG "PowerManagement: Unknown OID"
6147-#define SK_PNMI_ERR041 (SK_ERRBASE_PNMI + 41)
6148-#define SK_PNMI_ERR041MSG "MacPrivateConf: Unknown OID"
6149-#define SK_PNMI_ERR042 (SK_ERRBASE_PNMI + 42)
6150-#define SK_PNMI_ERR042MSG "MacPrivateConf: SK_HWEV_SET_ROLE returned not 0"
6151-#define SK_PNMI_ERR043 (SK_ERRBASE_PNMI + 43)
6152-#define SK_PNMI_ERR043MSG "MacPrivateConf: SK_HWEV_SET_LMODE returned not 0"
6153-#define SK_PNMI_ERR044 (SK_ERRBASE_PNMI + 44)
6154-#define SK_PNMI_ERR044MSG "MacPrivateConf: SK_HWEV_SET_FLOWMODE returned not 0"
6155-#define SK_PNMI_ERR045 (SK_ERRBASE_PNMI + 45)
6156-#define SK_PNMI_ERR045MSG "MacPrivateConf: SK_HWEV_SET_SPEED returned not 0"
6157-#define SK_PNMI_ERR046 (SK_ERRBASE_PNMI + 46)
6158-#define SK_PNMI_ERR046MSG "Monitor: Unknown OID"
6159-#define SK_PNMI_ERR047 (SK_ERRBASE_PNMI + 47)
6160-#define SK_PNMI_ERR047MSG "SirqUpdate: Event function returns not 0"
6161-#define SK_PNMI_ERR048 (SK_ERRBASE_PNMI + 48)
6162-#define SK_PNMI_ERR048MSG "RlmtUpdate: Event function returns not 0"
6163-#define SK_PNMI_ERR049 (SK_ERRBASE_PNMI + 49)
6164-#define SK_PNMI_ERR049MSG "SkPnmiInit: Invalid size of 'CounterOffset' struct!!"
6165-#define SK_PNMI_ERR050 (SK_ERRBASE_PNMI + 50)
6166-#define SK_PNMI_ERR050MSG "SkPnmiInit: Invalid size of 'StatAddr' table!!"
6167-#define SK_PNMI_ERR051 (SK_ERRBASE_PNMI + 51)
6168-#define SK_PNMI_ERR051MSG "SkPnmiEvent: Port switch suspicious"
6169-#define SK_PNMI_ERR052 (SK_ERRBASE_PNMI + 52)
6170-#define SK_PNMI_ERR052MSG ""
6171-#define SK_PNMI_ERR053 (SK_ERRBASE_PNMI + 53)
6172-#define SK_PNMI_ERR053MSG "General: Driver release date not initialized"
6173-#define SK_PNMI_ERR054 (SK_ERRBASE_PNMI + 54)
6174-#define SK_PNMI_ERR054MSG "General: Driver release date string too long"
6175-#define SK_PNMI_ERR055 (SK_ERRBASE_PNMI + 55)
6176-#define SK_PNMI_ERR055MSG "General: Driver file name not initialized"
6177-#define SK_PNMI_ERR056 (SK_ERRBASE_PNMI + 56)
6178-#define SK_PNMI_ERR056MSG "General: Driver file name string too long"
6179-
6180-/*
6181- * Management counter macros called by the driver
6182- */
6183-#define SK_PNMI_SET_DRIVER_DESCR(pAC,v) ((pAC)->Pnmi.pDriverDescription = \
6184- (char *)(v))
6185-
6186-#define SK_PNMI_SET_DRIVER_VER(pAC,v) ((pAC)->Pnmi.pDriverVersion = \
6187- (char *)(v))
6188-
6189-#define SK_PNMI_SET_DRIVER_RELDATE(pAC,v) ((pAC)->Pnmi.pDriverReleaseDate = \
6190- (char *)(v))
6191-
6192-#define SK_PNMI_SET_DRIVER_FILENAME(pAC,v) ((pAC)->Pnmi.pDriverFileName = \
6193- (char *)(v))
6194-
6195-#define SK_PNMI_CNT_TX_QUEUE_LEN(pAC,v,p) \
6196- { \
6197- (pAC)->Pnmi.Port[p].TxSwQueueLen = (SK_U64)(v); \
6198- if ((pAC)->Pnmi.Port[p].TxSwQueueLen > (pAC)->Pnmi.Port[p].TxSwQueueMax) { \
6199- (pAC)->Pnmi.Port[p].TxSwQueueMax = (pAC)->Pnmi.Port[p].TxSwQueueLen; \
6200- } \
6201- }
6202-#define SK_PNMI_CNT_TX_RETRY(pAC,p) (((pAC)->Pnmi.Port[p].TxRetryCts)++)
6203-#define SK_PNMI_CNT_RX_INTR(pAC,p) (((pAC)->Pnmi.Port[p].RxIntrCts)++)
6204-#define SK_PNMI_CNT_TX_INTR(pAC,p) (((pAC)->Pnmi.Port[p].TxIntrCts)++)
6205-#define SK_PNMI_CNT_NO_RX_BUF(pAC,p) (((pAC)->Pnmi.Port[p].RxNoBufCts)++)
6206-#define SK_PNMI_CNT_NO_TX_BUF(pAC,p) (((pAC)->Pnmi.Port[p].TxNoBufCts)++)
6207-#define SK_PNMI_CNT_USED_TX_DESCR(pAC,v,p) \
6208- ((pAC)->Pnmi.Port[p].TxUsedDescrNo=(SK_U64)(v));
6209-#define SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC,v,p) \
6210- { \
6211- ((pAC)->Pnmi.Port[p].RxDeliveredCts)++; \
6212- (pAC)->Pnmi.Port[p].RxOctetsDeliveredCts += (SK_U64)(v); \
6213- }
6214-#define SK_PNMI_CNT_ERR_RECOVERY(pAC,p) (((pAC)->Pnmi.Port[p].ErrRecoveryCts)++);
6215-
6216-#define SK_PNMI_CNT_SYNC_OCTETS(pAC,p,v) \
6217- { \
6218- if ((p) < SK_MAX_MACS) { \
6219- ((pAC)->Pnmi.Port[p].StatSyncCts)++; \
6220- (pAC)->Pnmi.Port[p].StatSyncOctetsCts += (SK_U64)(v); \
6221- } \
6222- }
6223-
6224-#define SK_PNMI_CNT_RX_LONGFRAMES(pAC,p) \
6225- { \
6226- if ((p) < SK_MAX_MACS) { \
6227- ((pAC)->Pnmi.Port[p].StatRxLongFrameCts++); \
6228- } \
6229- }
6230-
6231-#define SK_PNMI_CNT_RX_FRAMETOOLONG(pAC,p) \
6232- { \
6233- if ((p) < SK_MAX_MACS) { \
6234- ((pAC)->Pnmi.Port[p].StatRxFrameTooLongCts++); \
6235- } \
6236- }
6237-
6238-#define SK_PNMI_CNT_RX_PMACC_ERR(pAC,p) \
6239- { \
6240- if ((p) < SK_MAX_MACS) { \
6241- ((pAC)->Pnmi.Port[p].StatRxPMaccErr++); \
6242- } \
6243- }
6244-
6245-/*
6246- * Conversion Macros
6247- */
6248-#define SK_PNMI_PORT_INST2LOG(i) ((unsigned int)(i) - 1)
6249-#define SK_PNMI_PORT_LOG2INST(l) ((unsigned int)(l) + 1)
6250-#define SK_PNMI_PORT_PHYS2LOG(p) ((unsigned int)(p) + 1)
6251-#define SK_PNMI_PORT_LOG2PHYS(pAC,l) ((unsigned int)(l) - 1)
6252-#define SK_PNMI_PORT_PHYS2INST(pAC,p) \
6253- (pAC->Pnmi.DualNetActiveFlag ? 2 : ((unsigned int)(p) + 2))
6254-#define SK_PNMI_PORT_INST2PHYS(pAC,i) ((unsigned int)(i) - 2)
6255-
6256-/*
6257- * Structure definition for SkPnmiGetStruct and SkPnmiSetStruct
6258- */
6259-#define SK_PNMI_VPD_KEY_SIZE 5
6260-#define SK_PNMI_VPD_BUFSIZE (VPD_SIZE)
6261-#define SK_PNMI_VPD_ENTRIES (VPD_SIZE / 4)
6262-#define SK_PNMI_VPD_DATALEN 128 /* Number of data bytes */
6263-
6264-#define SK_PNMI_MULTICAST_LISTLEN 64
6265-#define SK_PNMI_SENSOR_ENTRIES (SK_MAX_SENSORS)
6266-#define SK_PNMI_CHECKSUM_ENTRIES 3
6267-#define SK_PNMI_MAC_ENTRIES (SK_MAX_MACS + 1)
6268-#define SK_PNMI_MONITOR_ENTRIES 20
6269-#define SK_PNMI_TRAP_ENTRIES 10
6270-#define SK_PNMI_TRAPLEN 128
6271-#define SK_PNMI_STRINGLEN1 80
6272-#define SK_PNMI_STRINGLEN2 25
6273-#define SK_PNMI_TRAP_QUEUE_LEN 512
6274-
6275-typedef struct s_PnmiVpd {
6276- char VpdKey[SK_PNMI_VPD_KEY_SIZE];
6277- char VpdValue[SK_PNMI_VPD_DATALEN];
6278- SK_U8 VpdAccess;
6279- SK_U8 VpdAction;
6280-} SK_PNMI_VPD;
6281-
6282-typedef struct s_PnmiSensor {
6283- SK_U8 SensorIndex;
6284- char SensorDescr[SK_PNMI_STRINGLEN2];
6285- SK_U8 SensorType;
6286- SK_U32 SensorValue;
6287- SK_U32 SensorWarningThresholdLow;
6288- SK_U32 SensorWarningThresholdHigh;
6289- SK_U32 SensorErrorThresholdLow;
6290- SK_U32 SensorErrorThresholdHigh;
6291- SK_U8 SensorStatus;
6292- SK_U64 SensorWarningCts;
6293- SK_U64 SensorErrorCts;
6294- SK_U64 SensorWarningTimestamp;
6295- SK_U64 SensorErrorTimestamp;
6296-} SK_PNMI_SENSOR;
6297-
6298-typedef struct s_PnmiChecksum {
6299- SK_U64 ChecksumRxOkCts;
6300- SK_U64 ChecksumRxUnableCts;
6301- SK_U64 ChecksumRxErrCts;
6302- SK_U64 ChecksumTxOkCts;
6303- SK_U64 ChecksumTxUnableCts;
6304-} SK_PNMI_CHECKSUM;
6305-
6306-typedef struct s_PnmiStat {
6307- SK_U64 StatTxOkCts;
6308- SK_U64 StatTxOctetsOkCts;
6309- SK_U64 StatTxBroadcastOkCts;
6310- SK_U64 StatTxMulticastOkCts;
6311- SK_U64 StatTxUnicastOkCts;
6312- SK_U64 StatTxLongFramesCts;
6313- SK_U64 StatTxBurstCts;
6314- SK_U64 StatTxPauseMacCtrlCts;
6315- SK_U64 StatTxMacCtrlCts;
6316- SK_U64 StatTxSingleCollisionCts;
6317- SK_U64 StatTxMultipleCollisionCts;
6318- SK_U64 StatTxExcessiveCollisionCts;
6319- SK_U64 StatTxLateCollisionCts;
6320- SK_U64 StatTxDeferralCts;
6321- SK_U64 StatTxExcessiveDeferralCts;
6322- SK_U64 StatTxFifoUnderrunCts;
6323- SK_U64 StatTxCarrierCts;
6324- SK_U64 Dummy1; /* StatTxUtilization */
6325- SK_U64 StatTx64Cts;
6326- SK_U64 StatTx127Cts;
6327- SK_U64 StatTx255Cts;
6328- SK_U64 StatTx511Cts;
6329- SK_U64 StatTx1023Cts;
6330- SK_U64 StatTxMaxCts;
6331- SK_U64 StatTxSyncCts;
6332- SK_U64 StatTxSyncOctetsCts;
6333- SK_U64 StatRxOkCts;
6334- SK_U64 StatRxOctetsOkCts;
6335- SK_U64 StatRxBroadcastOkCts;
6336- SK_U64 StatRxMulticastOkCts;
6337- SK_U64 StatRxUnicastOkCts;
6338- SK_U64 StatRxLongFramesCts;
6339- SK_U64 StatRxPauseMacCtrlCts;
6340- SK_U64 StatRxMacCtrlCts;
6341- SK_U64 StatRxPauseMacCtrlErrorCts;
6342- SK_U64 StatRxMacCtrlUnknownCts;
6343- SK_U64 StatRxBurstCts;
6344- SK_U64 StatRxMissedCts;
6345- SK_U64 StatRxFramingCts;
6346- SK_U64 StatRxFifoOverflowCts;
6347- SK_U64 StatRxJabberCts;
6348- SK_U64 StatRxCarrierCts;
6349- SK_U64 StatRxIRLengthCts;
6350- SK_U64 StatRxSymbolCts;
6351- SK_U64 StatRxShortsCts;
6352- SK_U64 StatRxRuntCts;
6353- SK_U64 StatRxCextCts;
6354- SK_U64 StatRxTooLongCts;
6355- SK_U64 StatRxFcsCts;
6356- SK_U64 Dummy2; /* StatRxUtilization */
6357- SK_U64 StatRx64Cts;
6358- SK_U64 StatRx127Cts;
6359- SK_U64 StatRx255Cts;
6360- SK_U64 StatRx511Cts;
6361- SK_U64 StatRx1023Cts;
6362- SK_U64 StatRxMaxCts;
6363-} SK_PNMI_STAT;
6364-
6365-typedef struct s_PnmiConf {
6366- char ConfMacCurrentAddr[6];
6367- char ConfMacFactoryAddr[6];
6368- SK_U8 ConfPMD;
6369- SK_U8 ConfConnector;
6370- SK_U32 ConfPhyType;
6371- SK_U32 ConfPhyMode;
6372- SK_U8 ConfLinkCapability;
6373- SK_U8 ConfLinkMode;
6374- SK_U8 ConfLinkModeStatus;
6375- SK_U8 ConfLinkStatus;
6376- SK_U8 ConfFlowCtrlCapability;
6377- SK_U8 ConfFlowCtrlMode;
6378- SK_U8 ConfFlowCtrlStatus;
6379- SK_U8 ConfPhyOperationCapability;
6380- SK_U8 ConfPhyOperationMode;
6381- SK_U8 ConfPhyOperationStatus;
6382- SK_U8 ConfSpeedCapability;
6383- SK_U8 ConfSpeedMode;
6384- SK_U8 ConfSpeedStatus;
6385-} SK_PNMI_CONF;
6386-
6387-typedef struct s_PnmiRlmt {
6388- SK_U32 RlmtIndex;
6389- SK_U32 RlmtStatus;
6390- SK_U64 RlmtTxHelloCts;
6391- SK_U64 RlmtRxHelloCts;
6392- SK_U64 RlmtTxSpHelloReqCts;
6393- SK_U64 RlmtRxSpHelloCts;
6394-} SK_PNMI_RLMT;
6395-
6396-typedef struct s_PnmiRlmtMonitor {
6397- SK_U32 RlmtMonitorIndex;
6398- char RlmtMonitorAddr[6];
6399- SK_U64 RlmtMonitorErrorCts;
6400- SK_U64 RlmtMonitorTimestamp;
6401- SK_U8 RlmtMonitorAdmin;
6402-} SK_PNMI_RLMT_MONITOR;
6403-
6404-typedef struct s_PnmiRequestStatus {
6405- SK_U32 ErrorStatus;
6406- SK_U32 ErrorOffset;
6407-} SK_PNMI_REQUEST_STATUS;
6408-
6409-typedef struct s_PnmiStrucData {
6410- SK_U32 MgmtDBVersion;
6411- SK_PNMI_REQUEST_STATUS ReturnStatus;
6412- SK_U32 VpdFreeBytes;
6413- char VpdEntriesList[SK_PNMI_VPD_ENTRIES * SK_PNMI_VPD_KEY_SIZE];
6414- SK_U32 VpdEntriesNumber;
6415- SK_PNMI_VPD Vpd[SK_PNMI_VPD_ENTRIES];
6416- SK_U32 PortNumber;
6417- SK_U32 DeviceType;
6418- char DriverDescr[SK_PNMI_STRINGLEN1];
6419- char DriverVersion[SK_PNMI_STRINGLEN2];
6420- char DriverReleaseDate[SK_PNMI_STRINGLEN1];
6421- char DriverFileName[SK_PNMI_STRINGLEN1];
6422- char HwDescr[SK_PNMI_STRINGLEN1];
6423- char HwVersion[SK_PNMI_STRINGLEN2];
6424- SK_U16 Chipset;
6425- SK_U32 ChipId;
6426- SK_U8 VauxAvail;
6427- SK_U32 RamSize;
6428- SK_U32 MtuSize;
6429- SK_U32 Action;
6430- SK_U32 TestResult;
6431- SK_U8 BusType;
6432- SK_U8 BusSpeed;
6433- SK_U8 BusWidth;
6434- SK_U8 SensorNumber;
6435- SK_PNMI_SENSOR Sensor[SK_PNMI_SENSOR_ENTRIES];
6436- SK_U8 ChecksumNumber;
6437- SK_PNMI_CHECKSUM Checksum[SK_PNMI_CHECKSUM_ENTRIES];
6438- SK_PNMI_STAT Stat[SK_PNMI_MAC_ENTRIES];
6439- SK_PNMI_CONF Conf[SK_PNMI_MAC_ENTRIES];
6440- SK_U8 RlmtMode;
6441- SK_U32 RlmtPortNumber;
6442- SK_U8 RlmtPortActive;
6443- SK_U8 RlmtPortPreferred;
6444- SK_U64 RlmtChangeCts;
6445- SK_U64 RlmtChangeTime;
6446- SK_U64 RlmtChangeEstimate;
6447- SK_U64 RlmtChangeThreshold;
6448- SK_PNMI_RLMT Rlmt[SK_MAX_MACS];
6449- SK_U32 RlmtMonitorNumber;
6450- SK_PNMI_RLMT_MONITOR RlmtMonitor[SK_PNMI_MONITOR_ENTRIES];
6451- SK_U32 TrapNumber;
6452- SK_U8 Trap[SK_PNMI_TRAP_QUEUE_LEN];
6453- SK_U64 TxSwQueueLen;
6454- SK_U64 TxSwQueueMax;
6455- SK_U64 TxRetryCts;
6456- SK_U64 RxIntrCts;
6457- SK_U64 TxIntrCts;
6458- SK_U64 RxNoBufCts;
6459- SK_U64 TxNoBufCts;
6460- SK_U64 TxUsedDescrNo;
6461- SK_U64 RxDeliveredCts;
6462- SK_U64 RxOctetsDeliveredCts;
6463- SK_U64 RxHwErrorsCts;
6464- SK_U64 TxHwErrorsCts;
6465- SK_U64 InErrorsCts;
6466- SK_U64 OutErrorsCts;
6467- SK_U64 ErrRecoveryCts;
6468- SK_U64 SysUpTime;
6469-} SK_PNMI_STRUCT_DATA;
6470-
6471-#define SK_PNMI_STRUCT_SIZE (sizeof(SK_PNMI_STRUCT_DATA))
6472-#define SK_PNMI_MIN_STRUCT_SIZE ((unsigned int)(SK_UPTR)\
6473- &(((SK_PNMI_STRUCT_DATA *)0)->VpdFreeBytes))
6474- /*
6475- * ReturnStatus field
6476- * must be located
6477- * before VpdFreeBytes
6478- */
6479-
6480-/*
6481- * Various definitions
6482- */
6483-#define SK_PNMI_MAX_PROTOS 3
6484-
6485-#define SK_PNMI_CNT_NO 66 /* Must have the value of the enum
6486- * SK_PNMI_MAX_IDX. Define SK_PNMI_CHECK
6487- * for check while init phase 1
6488- */
6489-
6490-/*
6491- * Estimate data structure
6492- */
6493-typedef struct s_PnmiEstimate {
6494- unsigned int EstValueIndex;
6495- SK_U64 EstValue[7];
6496- SK_U64 Estimate;
6497- SK_TIMER EstTimer;
6498-} SK_PNMI_ESTIMATE;
6499-
6500-
6501-/*
6502- * VCT timer data structure
6503- */
6504-typedef struct s_VctTimer {
6505- SK_TIMER VctTimer;
6506-} SK_PNMI_VCT_TIMER;
6507-
6508-
6509-/*
6510- * PNMI specific adapter context structure
6511- */
6512-typedef struct s_PnmiPort {
6513- SK_U64 StatSyncCts;
6514- SK_U64 StatSyncOctetsCts;
6515- SK_U64 StatRxLongFrameCts;
6516- SK_U64 StatRxFrameTooLongCts;
6517- SK_U64 StatRxPMaccErr;
6518- SK_U64 TxSwQueueLen;
6519- SK_U64 TxSwQueueMax;
6520- SK_U64 TxRetryCts;
6521- SK_U64 RxIntrCts;
6522- SK_U64 TxIntrCts;
6523- SK_U64 RxNoBufCts;
6524- SK_U64 TxNoBufCts;
6525- SK_U64 TxUsedDescrNo;
6526- SK_U64 RxDeliveredCts;
6527- SK_U64 RxOctetsDeliveredCts;
6528- SK_U64 RxHwErrorsCts;
6529- SK_U64 TxHwErrorsCts;
6530- SK_U64 InErrorsCts;
6531- SK_U64 OutErrorsCts;
6532- SK_U64 ErrRecoveryCts;
6533- SK_U64 RxShortZeroMark;
6534- SK_U64 CounterOffset[SK_PNMI_CNT_NO];
6535- SK_U32 CounterHigh[SK_PNMI_CNT_NO];
6536- SK_BOOL ActiveFlag;
6537- SK_U8 Align[3];
6538-} SK_PNMI_PORT;
6539-
6540-
6541-typedef struct s_PnmiData {
6542- SK_PNMI_PORT Port [SK_MAX_MACS];
6543- SK_PNMI_PORT BufPort [SK_MAX_MACS]; /* 2002-09-13 pweber */
6544- SK_U64 VirtualCounterOffset[SK_PNMI_CNT_NO];
6545- SK_U32 TestResult;
6546- char HwVersion[10];
6547- SK_U16 Align01;
6548-
6549- char *pDriverDescription;
6550- char *pDriverVersion;
6551- char *pDriverReleaseDate;
6552- char *pDriverFileName;
6553-
6554- int MacUpdatedFlag;
6555- int RlmtUpdatedFlag;
6556- int SirqUpdatedFlag;
6557-
6558- SK_U64 RlmtChangeCts;
6559- SK_U64 RlmtChangeTime;
6560- SK_PNMI_ESTIMATE RlmtChangeEstimate;
6561- SK_U64 RlmtChangeThreshold;
6562-
6563- SK_U64 StartUpTime;
6564- SK_U32 DeviceType;
6565- char PciBusSpeed;
6566- char PciBusWidth;
6567- char Chipset;
6568- char PMD;
6569- char Connector;
6570- SK_BOOL DualNetActiveFlag;
6571- SK_U16 Align02;
6572-
6573- char TrapBuf[SK_PNMI_TRAP_QUEUE_LEN];
6574- unsigned int TrapBufFree;
6575- unsigned int TrapQueueBeg;
6576- unsigned int TrapQueueEnd;
6577- unsigned int TrapBufPad;
6578- unsigned int TrapUnique;
6579- SK_U8 VctStatus[SK_MAX_MACS];
6580- SK_PNMI_VCT VctBackup[SK_MAX_MACS];
6581- SK_PNMI_VCT_TIMER VctTimeout[SK_MAX_MACS];
6582-#ifdef SK_DIAG_SUPPORT
6583- SK_U32 DiagAttached;
6584-#endif /* SK_DIAG_SUPPORT */
6585-} SK_PNMI;
6586-
6587-
6588-/*
6589- * Function prototypes
6590- */
6591-extern int SkPnmiInit(SK_AC *pAC, SK_IOC IoC, int Level);
6592-extern int SkPnmiGetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void* pBuf,
6593- unsigned int* pLen, SK_U32 Instance, SK_U32 NetIndex);
6594-extern int SkPnmiPreSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id,
6595- void* pBuf, unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex);
6596-extern int SkPnmiSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void* pBuf,
6597- unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex);
6598-extern int SkPnmiGetStruct(SK_AC *pAC, SK_IOC IoC, void* pBuf,
6599- unsigned int *pLen, SK_U32 NetIndex);
6600-extern int SkPnmiPreSetStruct(SK_AC *pAC, SK_IOC IoC, void* pBuf,
6601- unsigned int *pLen, SK_U32 NetIndex);
6602-extern int SkPnmiSetStruct(SK_AC *pAC, SK_IOC IoC, void* pBuf,
6603- unsigned int *pLen, SK_U32 NetIndex);
6604-extern int SkPnmiEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event,
6605- SK_EVPARA Param);
6606-extern int SkPnmiGenIoctl(SK_AC *pAC, SK_IOC IoC, void * pBuf,
6607- unsigned int * pLen, SK_U32 NetIndex);
6608-
6609-#endif
6610+/*****************************************************************************\r
6611+ *\r
6612+ * Name: skgepnmi.h\r
6613+ * Project: Gigabit Ethernet Adapters, PNMI-Module\r
6614+ * Version: $Revision$\r
6615+ * Date: $Date$\r
6616+ * Purpose: Defines for Private Network Management Interface\r
6617+ *\r
6618+ ****************************************************************************/\r
6619+\r
6620+/******************************************************************************\r
6621+ *\r
6622+ * (C)Copyright 1998-2002 SysKonnect GmbH.\r
6623+ * (C)Copyright 2002-2003 Marvell.\r
6624+ *\r
6625+ * This program is free software; you can redistribute it and/or modify\r
6626+ * it under the terms of the GNU General Public License as published by\r
6627+ * the Free Software Foundation; either version 2 of the License, or\r
6628+ * (at your option) any later version.\r
6629+ *\r
6630+ * The information in this file is provided "AS IS" without warranty.\r
6631+ *\r
6632+ ******************************************************************************/\r
6633+\r
6634+#ifndef _SKGEPNMI_H_\r
6635+#define _SKGEPNMI_H_\r
6636+\r
6637+/*\r
6638+ * Include dependencies\r
6639+ */\r
6640+#include "h/sktypes.h"\r
6641+#include "h/skerror.h"\r
6642+#include "h/sktimer.h"\r
6643+#include "h/sktwsi.h"\r
6644+#include "h/skaddr.h"\r
6645+#include "h/skrlmt.h"\r
6646+#include "h/skvpd.h"\r
6647+\r
6648+/*\r
6649+ * Management Database Version\r
6650+ */\r
6651+#define SK_PNMI_MDB_VERSION 0x00030001 /* 3.1 */\r
6652+\r
6653+/*\r
6654+ * Event definitions\r
6655+ */\r
6656+#define SK_PNMI_EVT_SIRQ_OVERFLOW 1 /* Counter overflow */\r
6657+#define SK_PNMI_EVT_SEN_WAR_LOW 2 /* Lower war thres exceeded */\r
6658+#define SK_PNMI_EVT_SEN_WAR_UPP 3 /* Upper war thres exceeded */\r
6659+#define SK_PNMI_EVT_SEN_ERR_LOW 4 /* Lower err thres exceeded */\r
6660+#define SK_PNMI_EVT_SEN_ERR_UPP 5 /* Upper err thres exceeded */\r
6661+#define SK_PNMI_EVT_CHG_EST_TIMER 6 /* Timer event for RLMT Chg */\r
6662+#define SK_PNMI_EVT_UTILIZATION_TIMER 7 /* Timer event for Utiliza. */\r
6663+#define SK_PNMI_EVT_CLEAR_COUNTER 8 /* Clear statistic counters */\r
6664+#define SK_PNMI_EVT_XMAC_RESET 9 /* XMAC will be reset */\r
6665+#define SK_PNMI_EVT_RLMT_PORT_UP 10 /* Port came logically up */\r
6666+#define SK_PNMI_EVT_RLMT_PORT_DOWN 11 /* Port went logically down */\r
6667+#define SK_PNMI_EVT_RLMT_SEGMENTATION 13 /* Two SP root bridges found */\r
6668+#define SK_PNMI_EVT_RLMT_ACTIVE_DOWN 14 /* Port went logically down */\r
6669+#define SK_PNMI_EVT_RLMT_ACTIVE_UP 15 /* Port came logically up */\r
6670+#define SK_PNMI_EVT_RLMT_SET_NETS 16 /* Number of nets (1 or 2). */\r
6671+#define SK_PNMI_EVT_VCT_RESET 17 /* VCT port reset timer event started with SET. */\r
6672+\r
6673+/*\r
6674+ * Return values\r
6675+ */\r
6676+#define SK_PNMI_ERR_OK 0\r
6677+#define SK_PNMI_ERR_GENERAL 1\r
6678+#define SK_PNMI_ERR_TOO_SHORT 2\r
6679+#define SK_PNMI_ERR_BAD_VALUE 3\r
6680+#define SK_PNMI_ERR_READ_ONLY 4\r
6681+#define SK_PNMI_ERR_UNKNOWN_OID 5\r
6682+#define SK_PNMI_ERR_UNKNOWN_INST 6\r
6683+#define SK_PNMI_ERR_UNKNOWN_NET 7\r
6684+#define SK_PNMI_ERR_NOT_SUPPORTED 10\r
6685+\r
6686+/*\r
6687+ * Return values of driver reset function SK_DRIVER_RESET() and\r
6688+ * driver event function SK_DRIVER_EVENT()\r
6689+ */\r
6690+#define SK_PNMI_ERR_OK 0\r
6691+#define SK_PNMI_ERR_FAIL 1\r
6692+\r
6693+/*\r
6694+ * Return values of driver test function SK_DRIVER_SELFTEST()\r
6695+ */\r
6696+#define SK_PNMI_TST_UNKNOWN (1 << 0)\r
6697+#define SK_PNMI_TST_TRANCEIVER (1 << 1)\r
6698+#define SK_PNMI_TST_ASIC (1 << 2)\r
6699+#define SK_PNMI_TST_SENSOR (1 << 3)\r
6700+#define SK_PNMI_TST_POWERMGMT (1 << 4)\r
6701+#define SK_PNMI_TST_PCI (1 << 5)\r
6702+#define SK_PNMI_TST_MAC (1 << 6)\r
6703+\r
6704+/*\r
6705+ * RLMT specific definitions\r
6706+ */\r
6707+#define SK_PNMI_RLMT_STATUS_STANDBY 1\r
6708+#define SK_PNMI_RLMT_STATUS_ACTIVE 2\r
6709+#define SK_PNMI_RLMT_STATUS_ERROR 3\r
6710+\r
6711+#define SK_PNMI_RLMT_LSTAT_PHY_DOWN 1\r
6712+#define SK_PNMI_RLMT_LSTAT_AUTONEG 2\r
6713+#define SK_PNMI_RLMT_LSTAT_LOG_DOWN 3\r
6714+#define SK_PNMI_RLMT_LSTAT_LOG_UP 4\r
6715+#define SK_PNMI_RLMT_LSTAT_INDETERMINATED 5\r
6716+\r
6717+#define SK_PNMI_RLMT_MODE_CHK_LINK (SK_RLMT_CHECK_LINK)\r
6718+#define SK_PNMI_RLMT_MODE_CHK_RX (SK_RLMT_CHECK_LOC_LINK)\r
6719+#define SK_PNMI_RLMT_MODE_CHK_SPT (SK_RLMT_CHECK_SEG)\r
6720+/* #define SK_PNMI_RLMT_MODE_CHK_EX */\r
6721+\r
6722+/*\r
6723+ * OID definition\r
6724+ */\r
6725+#ifndef _NDIS_ /* Check, whether NDIS already included OIDs */\r
6726+\r
6727+#define OID_GEN_XMIT_OK 0x00020101\r
6728+#define OID_GEN_RCV_OK 0x00020102\r
6729+#define OID_GEN_XMIT_ERROR 0x00020103\r
6730+#define OID_GEN_RCV_ERROR 0x00020104\r
6731+#define OID_GEN_RCV_NO_BUFFER 0x00020105\r
6732+\r
6733+/* #define OID_GEN_DIRECTED_BYTES_XMIT 0x00020201 */\r
6734+#define OID_GEN_DIRECTED_FRAMES_XMIT 0x00020202\r
6735+/* #define OID_GEN_MULTICAST_BYTES_XMIT 0x00020203 */\r
6736+#define OID_GEN_MULTICAST_FRAMES_XMIT 0x00020204\r
6737+/* #define OID_GEN_BROADCAST_BYTES_XMIT 0x00020205 */\r
6738+#define OID_GEN_BROADCAST_FRAMES_XMIT 0x00020206\r
6739+/* #define OID_GEN_DIRECTED_BYTES_RCV 0x00020207 */\r
6740+#define OID_GEN_DIRECTED_FRAMES_RCV 0x00020208\r
6741+/* #define OID_GEN_MULTICAST_BYTES_RCV 0x00020209 */\r
6742+#define OID_GEN_MULTICAST_FRAMES_RCV 0x0002020A\r
6743+/* #define OID_GEN_BROADCAST_BYTES_RCV 0x0002020B */\r
6744+#define OID_GEN_BROADCAST_FRAMES_RCV 0x0002020C\r
6745+#define OID_GEN_RCV_CRC_ERROR 0x0002020D\r
6746+#define OID_GEN_TRANSMIT_QUEUE_LENGTH 0x0002020E\r
6747+\r
6748+#define OID_802_3_PERMANENT_ADDRESS 0x01010101\r
6749+#define OID_802_3_CURRENT_ADDRESS 0x01010102\r
6750+/* #define OID_802_3_MULTICAST_LIST 0x01010103 */\r
6751+/* #define OID_802_3_MAXIMUM_LIST_SIZE 0x01010104 */\r
6752+/* #define OID_802_3_MAC_OPTIONS 0x01010105 */\r
6753+ \r
6754+#define OID_802_3_RCV_ERROR_ALIGNMENT 0x01020101\r
6755+#define OID_802_3_XMIT_ONE_COLLISION 0x01020102\r
6756+#define OID_802_3_XMIT_MORE_COLLISIONS 0x01020103\r
6757+#define OID_802_3_XMIT_DEFERRED 0x01020201\r
6758+#define OID_802_3_XMIT_MAX_COLLISIONS 0x01020202\r
6759+#define OID_802_3_RCV_OVERRUN 0x01020203\r
6760+#define OID_802_3_XMIT_UNDERRUN 0x01020204\r
6761+#define OID_802_3_XMIT_TIMES_CRS_LOST 0x01020206\r
6762+#define OID_802_3_XMIT_LATE_COLLISIONS 0x01020207\r
6763+\r
6764+/*\r
6765+ * PnP and PM OIDs\r
6766+ */\r
6767+#ifdef SK_POWER_MGMT\r
6768+#define OID_PNP_CAPABILITIES 0xFD010100\r
6769+#define OID_PNP_SET_POWER 0xFD010101\r
6770+#define OID_PNP_QUERY_POWER 0xFD010102\r
6771+#define OID_PNP_ADD_WAKE_UP_PATTERN 0xFD010103\r
6772+#define OID_PNP_REMOVE_WAKE_UP_PATTERN 0xFD010104\r
6773+#define OID_PNP_ENABLE_WAKE_UP 0xFD010106\r
6774+#endif /* SK_POWER_MGMT */\r
6775+\r
6776+#endif /* _NDIS_ */\r
6777+\r
6778+#define OID_SKGE_MDB_VERSION 0xFF010100\r
6779+#define OID_SKGE_SUPPORTED_LIST 0xFF010101\r
6780+#define OID_SKGE_VPD_FREE_BYTES 0xFF010102\r
6781+#define OID_SKGE_VPD_ENTRIES_LIST 0xFF010103\r
6782+#define OID_SKGE_VPD_ENTRIES_NUMBER 0xFF010104\r
6783+#define OID_SKGE_VPD_KEY 0xFF010105\r
6784+#define OID_SKGE_VPD_VALUE 0xFF010106\r
6785+#define OID_SKGE_VPD_ACCESS 0xFF010107\r
6786+#define OID_SKGE_VPD_ACTION 0xFF010108\r
6787+ \r
6788+#define OID_SKGE_PORT_NUMBER 0xFF010110\r
6789+#define OID_SKGE_DEVICE_TYPE 0xFF010111\r
6790+#define OID_SKGE_DRIVER_DESCR 0xFF010112\r
6791+#define OID_SKGE_DRIVER_VERSION 0xFF010113\r
6792+#define OID_SKGE_HW_DESCR 0xFF010114\r
6793+#define OID_SKGE_HW_VERSION 0xFF010115\r
6794+#define OID_SKGE_CHIPSET 0xFF010116\r
6795+#define OID_SKGE_ACTION 0xFF010117\r
6796+#define OID_SKGE_RESULT 0xFF010118\r
6797+#define OID_SKGE_BUS_TYPE 0xFF010119\r
6798+#define OID_SKGE_BUS_SPEED 0xFF01011A\r
6799+#define OID_SKGE_BUS_WIDTH 0xFF01011B\r
6800+/* 0xFF01011C unused */\r
6801+#define OID_SKGE_DIAG_ACTION 0xFF01011D\r
6802+#define OID_SKGE_DIAG_RESULT 0xFF01011E\r
6803+#define OID_SKGE_MTU 0xFF01011F\r
6804+#define OID_SKGE_PHYS_CUR_ADDR 0xFF010120\r
6805+#define OID_SKGE_PHYS_FAC_ADDR 0xFF010121\r
6806+#define OID_SKGE_PMD 0xFF010122\r
6807+#define OID_SKGE_CONNECTOR 0xFF010123\r
6808+#define OID_SKGE_LINK_CAP 0xFF010124\r
6809+#define OID_SKGE_LINK_MODE 0xFF010125\r
6810+#define OID_SKGE_LINK_MODE_STATUS 0xFF010126\r
6811+#define OID_SKGE_LINK_STATUS 0xFF010127\r
6812+#define OID_SKGE_FLOWCTRL_CAP 0xFF010128\r
6813+#define OID_SKGE_FLOWCTRL_MODE 0xFF010129\r
6814+#define OID_SKGE_FLOWCTRL_STATUS 0xFF01012A\r
6815+#define OID_SKGE_PHY_OPERATION_CAP 0xFF01012B\r
6816+#define OID_SKGE_PHY_OPERATION_MODE 0xFF01012C\r
6817+#define OID_SKGE_PHY_OPERATION_STATUS 0xFF01012D\r
6818+#define OID_SKGE_MULTICAST_LIST 0xFF01012E\r
6819+#define OID_SKGE_CURRENT_PACKET_FILTER 0xFF01012F\r
6820+\r
6821+#define OID_SKGE_TRAP 0xFF010130\r
6822+#define OID_SKGE_TRAP_NUMBER 0xFF010131\r
6823+\r
6824+#define OID_SKGE_RLMT_MODE 0xFF010140\r
6825+#define OID_SKGE_RLMT_PORT_NUMBER 0xFF010141\r
6826+#define OID_SKGE_RLMT_PORT_ACTIVE 0xFF010142\r
6827+#define OID_SKGE_RLMT_PORT_PREFERRED 0xFF010143\r
6828+\r
6829+#define OID_SKGE_RLMT_MONITOR_NUMBER 0xFF010150\r
6830+#define OID_SKGE_RLMT_MONITOR_INDEX 0xFF010151\r
6831+#define OID_SKGE_RLMT_MONITOR_ADDR 0xFF010152\r
6832+#define OID_SKGE_RLMT_MONITOR_ERRS 0xFF010153\r
6833+#define OID_SKGE_RLMT_MONITOR_TIMESTAMP 0xFF010154\r
6834+#define OID_SKGE_RLMT_MONITOR_ADMIN 0xFF010155\r
6835+\r
6836+#define OID_SKGE_INTERMEDIATE_SUPPORT 0xFF010160\r
6837+#define OID_SKGE_SET_TEAM_MAC_ADDRESS 0xFF010161\r
6838+#define OID_SKGE_DEVICE_INFORMATION 0xFF010162\r
6839+\r
6840+#define OID_SKGE_SPEED_CAP 0xFF010170\r
6841+#define OID_SKGE_SPEED_MODE 0xFF010171\r
6842+#define OID_SKGE_SPEED_STATUS 0xFF010172\r
6843+\r
6844+#define OID_SKGE_BOARDLEVEL 0xFF010180\r
6845+\r
6846+#define OID_SKGE_SENSOR_NUMBER 0xFF020100 \r
6847+#define OID_SKGE_SENSOR_INDEX 0xFF020101\r
6848+#define OID_SKGE_SENSOR_DESCR 0xFF020102\r
6849+#define OID_SKGE_SENSOR_TYPE 0xFF020103\r
6850+#define OID_SKGE_SENSOR_VALUE 0xFF020104\r
6851+#define OID_SKGE_SENSOR_WAR_THRES_LOW 0xFF020105\r
6852+#define OID_SKGE_SENSOR_WAR_THRES_UPP 0xFF020106\r
6853+#define OID_SKGE_SENSOR_ERR_THRES_LOW 0xFF020107\r
6854+#define OID_SKGE_SENSOR_ERR_THRES_UPP 0xFF020108\r
6855+#define OID_SKGE_SENSOR_STATUS 0xFF020109\r
6856+#define OID_SKGE_SENSOR_WAR_CTS 0xFF02010A\r
6857+#define OID_SKGE_SENSOR_ERR_CTS 0xFF02010B\r
6858+#define OID_SKGE_SENSOR_WAR_TIME 0xFF02010C\r
6859+#define OID_SKGE_SENSOR_ERR_TIME 0xFF02010D\r
6860+\r
6861+#define OID_SKGE_CHKSM_NUMBER 0xFF020110\r
6862+#define OID_SKGE_CHKSM_RX_OK_CTS 0xFF020111\r
6863+#define OID_SKGE_CHKSM_RX_UNABLE_CTS 0xFF020112\r
6864+#define OID_SKGE_CHKSM_RX_ERR_CTS 0xFF020113\r
6865+#define OID_SKGE_CHKSM_TX_OK_CTS 0xFF020114\r
6866+#define OID_SKGE_CHKSM_TX_UNABLE_CTS 0xFF020115\r
6867+\r
6868+#define OID_SKGE_STAT_TX 0xFF020120\r
6869+#define OID_SKGE_STAT_TX_OCTETS 0xFF020121\r
6870+#define OID_SKGE_STAT_TX_BROADCAST 0xFF020122\r
6871+#define OID_SKGE_STAT_TX_MULTICAST 0xFF020123\r
6872+#define OID_SKGE_STAT_TX_UNICAST 0xFF020124\r
6873+#define OID_SKGE_STAT_TX_LONGFRAMES 0xFF020125\r
6874+#define OID_SKGE_STAT_TX_BURST 0xFF020126\r
6875+#define OID_SKGE_STAT_TX_PFLOWC 0xFF020127\r
6876+#define OID_SKGE_STAT_TX_FLOWC 0xFF020128\r
6877+#define OID_SKGE_STAT_TX_SINGLE_COL 0xFF020129\r
6878+#define OID_SKGE_STAT_TX_MULTI_COL 0xFF02012A\r
6879+#define OID_SKGE_STAT_TX_EXCESS_COL 0xFF02012B\r
6880+#define OID_SKGE_STAT_TX_LATE_COL 0xFF02012C\r
6881+#define OID_SKGE_STAT_TX_DEFFERAL 0xFF02012D\r
6882+#define OID_SKGE_STAT_TX_EXCESS_DEF 0xFF02012E\r
6883+#define OID_SKGE_STAT_TX_UNDERRUN 0xFF02012F\r
6884+#define OID_SKGE_STAT_TX_CARRIER 0xFF020130\r
6885+/* #define OID_SKGE_STAT_TX_UTIL 0xFF020131 */\r
6886+#define OID_SKGE_STAT_TX_64 0xFF020132\r
6887+#define OID_SKGE_STAT_TX_127 0xFF020133\r
6888+#define OID_SKGE_STAT_TX_255 0xFF020134\r
6889+#define OID_SKGE_STAT_TX_511 0xFF020135\r
6890+#define OID_SKGE_STAT_TX_1023 0xFF020136\r
6891+#define OID_SKGE_STAT_TX_MAX 0xFF020137\r
6892+#define OID_SKGE_STAT_TX_SYNC 0xFF020138\r
6893+#define OID_SKGE_STAT_TX_SYNC_OCTETS 0xFF020139\r
6894+#define OID_SKGE_STAT_RX 0xFF02013A\r
6895+#define OID_SKGE_STAT_RX_OCTETS 0xFF02013B\r
6896+#define OID_SKGE_STAT_RX_BROADCAST 0xFF02013C\r
6897+#define OID_SKGE_STAT_RX_MULTICAST 0xFF02013D\r
6898+#define OID_SKGE_STAT_RX_UNICAST 0xFF02013E\r
6899+#define OID_SKGE_STAT_RX_PFLOWC 0xFF02013F\r
6900+#define OID_SKGE_STAT_RX_FLOWC 0xFF020140\r
6901+#define OID_SKGE_STAT_RX_PFLOWC_ERR 0xFF020141\r
6902+#define OID_SKGE_STAT_RX_FLOWC_UNKWN 0xFF020142\r
6903+#define OID_SKGE_STAT_RX_BURST 0xFF020143\r
6904+#define OID_SKGE_STAT_RX_MISSED 0xFF020144\r
6905+#define OID_SKGE_STAT_RX_FRAMING 0xFF020145\r
6906+#define OID_SKGE_STAT_RX_OVERFLOW 0xFF020146\r
6907+#define OID_SKGE_STAT_RX_JABBER 0xFF020147\r
6908+#define OID_SKGE_STAT_RX_CARRIER 0xFF020148\r
6909+#define OID_SKGE_STAT_RX_IR_LENGTH 0xFF020149\r
6910+#define OID_SKGE_STAT_RX_SYMBOL 0xFF02014A\r
6911+#define OID_SKGE_STAT_RX_SHORTS 0xFF02014B\r
6912+#define OID_SKGE_STAT_RX_RUNT 0xFF02014C\r
6913+#define OID_SKGE_STAT_RX_CEXT 0xFF02014D\r
6914+#define OID_SKGE_STAT_RX_TOO_LONG 0xFF02014E\r
6915+#define OID_SKGE_STAT_RX_FCS 0xFF02014F\r
6916+/* #define OID_SKGE_STAT_RX_UTIL 0xFF020150 */\r
6917+#define OID_SKGE_STAT_RX_64 0xFF020151\r
6918+#define OID_SKGE_STAT_RX_127 0xFF020152\r
6919+#define OID_SKGE_STAT_RX_255 0xFF020153\r
6920+#define OID_SKGE_STAT_RX_511 0xFF020154\r
6921+#define OID_SKGE_STAT_RX_1023 0xFF020155\r
6922+#define OID_SKGE_STAT_RX_MAX 0xFF020156\r
6923+#define OID_SKGE_STAT_RX_LONGFRAMES 0xFF020157\r
6924+\r
6925+#define OID_SKGE_RLMT_CHANGE_CTS 0xFF020160\r
6926+#define OID_SKGE_RLMT_CHANGE_TIME 0xFF020161\r
6927+#define OID_SKGE_RLMT_CHANGE_ESTIM 0xFF020162\r
6928+#define OID_SKGE_RLMT_CHANGE_THRES 0xFF020163\r
6929+\r
6930+#define OID_SKGE_RLMT_PORT_INDEX 0xFF020164\r
6931+#define OID_SKGE_RLMT_STATUS 0xFF020165\r
6932+#define OID_SKGE_RLMT_TX_HELLO_CTS 0xFF020166\r
6933+#define OID_SKGE_RLMT_RX_HELLO_CTS 0xFF020167\r
6934+#define OID_SKGE_RLMT_TX_SP_REQ_CTS 0xFF020168\r
6935+#define OID_SKGE_RLMT_RX_SP_CTS 0xFF020169\r
6936+\r
6937+#define OID_SKGE_TX_SW_QUEUE_LEN 0xFF020170\r
6938+#define OID_SKGE_TX_SW_QUEUE_MAX 0xFF020171\r
6939+#define OID_SKGE_TX_RETRY 0xFF020172\r
6940+#define OID_SKGE_RX_INTR_CTS 0xFF020173\r
6941+#define OID_SKGE_TX_INTR_CTS 0xFF020174\r
6942+#define OID_SKGE_RX_NO_BUF_CTS 0xFF020175\r
6943+#define OID_SKGE_TX_NO_BUF_CTS 0xFF020176\r
6944+#define OID_SKGE_TX_USED_DESCR_NO 0xFF020177\r
6945+#define OID_SKGE_RX_DELIVERED_CTS 0xFF020178\r
6946+#define OID_SKGE_RX_OCTETS_DELIV_CTS 0xFF020179\r
6947+#define OID_SKGE_RX_HW_ERROR_CTS 0xFF02017A\r
6948+#define OID_SKGE_TX_HW_ERROR_CTS 0xFF02017B\r
6949+#define OID_SKGE_IN_ERRORS_CTS 0xFF02017C\r
6950+#define OID_SKGE_OUT_ERROR_CTS 0xFF02017D\r
6951+#define OID_SKGE_ERR_RECOVERY_CTS 0xFF02017E\r
6952+#define OID_SKGE_SYSUPTIME 0xFF02017F\r
6953+\r
6954+#define OID_SKGE_ALL_DATA 0xFF020190\r
6955+\r
6956+/* Defines for VCT. */\r
6957+#define OID_SKGE_VCT_GET 0xFF020200\r
6958+#define OID_SKGE_VCT_SET 0xFF020201\r
6959+#define OID_SKGE_VCT_STATUS 0xFF020202\r
6960+#define OID_SKGE_VCT_CAPABILITIES 0xFF020203\r
6961+\r
6962+#ifdef SK_DIAG_SUPPORT\r
6963+/* Defines for driver DIAG mode. */\r
6964+#define OID_SKGE_DIAG_MODE 0xFF020204\r
6965+#endif /* SK_DIAG_SUPPORT */\r
6966+\r
6967+/* New OIDs */\r
6968+#define OID_SKGE_DRIVER_RELDATE 0xFF020210\r
6969+#define OID_SKGE_DRIVER_FILENAME 0xFF020211\r
6970+#define OID_SKGE_CHIPID 0xFF020212\r
6971+#define OID_SKGE_RAMSIZE 0xFF020213\r
6972+#define OID_SKGE_VAUXAVAIL 0xFF020214\r
6973+#define OID_SKGE_PHY_TYPE 0xFF020215\r
6974+#define OID_SKGE_PHY_LP_MODE 0xFF020216\r
6975+\r
6976+/*\r
6977+ * Added for new DualNet IM driver V2\r
6978+ * these OIDs should later be in pnmi.h\r
6979+ */\r
6980+#define OID_SKGE_MAC_COUNT 0xFF020217\r
6981+#define OID_SKGE_DUALNET_MODE 0xFF020218\r
6982+#define OID_SKGE_SET_TAGHEADER 0xFF020219\r
6983+\r
6984+#ifdef SK_ASF\r
6985+/* Defines for ASF */\r
6986+#define OID_SKGE_ASF 0xFF02021a\r
6987+#define OID_SKGE_ASF_STORE_CONFIG 0xFF02021b\r
6988+#define OID_SKGE_ASF_ENA 0xFF02021c\r
6989+#define OID_SKGE_ASF_RETRANS 0xFF02021d\r
6990+#define OID_SKGE_ASF_RETRANS_INT 0xFF02021e\r
6991+#define OID_SKGE_ASF_HB_ENA 0xFF02021f\r
6992+#define OID_SKGE_ASF_HB_INT 0xFF020220\r
6993+#define OID_SKGE_ASF_WD_ENA 0xFF020221\r
6994+#define OID_SKGE_ASF_WD_TIME 0xFF020222\r
6995+#define OID_SKGE_ASF_IP_SOURCE 0xFF020223\r
6996+#define OID_SKGE_ASF_MAC_SOURCE 0xFF020224\r
6997+#define OID_SKGE_ASF_IP_DEST 0xFF020225\r
6998+#define OID_SKGE_ASF_MAC_DEST 0xFF020226\r
6999+#define OID_SKGE_ASF_COMMUNITY_NAME 0xFF020227\r
7000+#define OID_SKGE_ASF_RSP_ENA 0xFF020228 \r
7001+#define OID_SKGE_ASF_RETRANS_COUNT_MIN 0xFF020229\r
7002+#define OID_SKGE_ASF_RETRANS_COUNT_MAX 0xFF02022a\r
7003+#define OID_SKGE_ASF_RETRANS_INT_MIN 0xFF02022b\r
7004+#define OID_SKGE_ASF_RETRANS_INT_MAX 0xFF02022c\r
7005+#define OID_SKGE_ASF_HB_INT_MIN 0xFF02022d\r
7006+#define OID_SKGE_ASF_HB_INT_MAX 0xFF02022e\r
7007+#define OID_SKGE_ASF_WD_TIME_MIN 0xFF02022f\r
7008+#define OID_SKGE_ASF_WD_TIME_MAX 0xFF020230\r
7009+#define OID_SKGE_ASF_HB_CAP 0xFF020231\r
7010+#define OID_SKGE_ASF_WD_TIMER_RES 0xFF020232\r
7011+#define OID_SKGE_ASF_GUID 0xFF020233\r
7012+#define OID_SKGE_ASF_KEY_OP 0xFF020234\r
7013+#define OID_SKGE_ASF_KEY_ADM 0xFF020235\r
7014+#define OID_SKGE_ASF_KEY_GEN 0xFF020236\r
7015+#define OID_SKGE_ASF_CAP 0xFF020237\r
7016+#define OID_SKGE_ASF_PAR_1 0xFF020238\r
7017+#define OID_SKGE_ASF_OVERALL_OID 0xFF020239\r
7018+#endif /* SK_ASF */\r
7019+\r
7020+\r
7021+// Defined for yukon2 path only \r
7022+#define OID_SKGE_UPPER_MINIPORT 0xFF02023D\r
7023+\r
7024+\r
7025+#ifdef SK_ASF\r
7026+/* Defines for ASF */\r
7027+#define OID_SKGE_ASF_FWVER_OID 0xFF020240\r
7028+#define OID_SKGE_ASF_ACPI_OID 0xFF020241\r
7029+#define OID_SKGE_ASF_SMBUS_OID 0xFF020242\r
7030+#endif /* SK_ASF */\r
7031+\r
7032+\r
7033+/* VCT struct to store a backup copy of VCT data after a port reset. */\r
7034+typedef struct s_PnmiVct {\r
7035+ SK_U8 VctStatus;\r
7036+ SK_U8 CableLen;\r
7037+ SK_U32 MdiPairLen[4];\r
7038+ SK_U8 MdiPairSts[4];\r
7039+} SK_PNMI_VCT;\r
7040+\r
7041+\r
7042+/* VCT status values (to be given to CPA via OID_SKGE_VCT_STATUS). */\r
7043+#define SK_PNMI_VCT_NONE 0x00\r
7044+#define SK_PNMI_VCT_OLD_VCT_DATA 0x01\r
7045+#define SK_PNMI_VCT_NEW_VCT_DATA 0x02\r
7046+#define SK_PNMI_VCT_OLD_DSP_DATA 0x04\r
7047+#define SK_PNMI_VCT_NEW_DSP_DATA 0x08\r
7048+#define SK_PNMI_VCT_RUNNING 0x10\r
7049+\r
7050+\r
7051+/* VCT cable test status. */\r
7052+#define SK_PNMI_VCT_NORMAL_CABLE 0\r
7053+#define SK_PNMI_VCT_SHORT_CABLE 1\r
7054+#define SK_PNMI_VCT_OPEN_CABLE 2\r
7055+#define SK_PNMI_VCT_TEST_FAIL 3\r
7056+#define SK_PNMI_VCT_IMPEDANCE_MISMATCH 4\r
7057+#define SK_PNMI_VCT_NOT_PRESENT 5\r
7058+\r
7059+/* VCT capabilities (needed for OID_SKGE_VCT_CAPABILITIES. */\r
7060+#define SK_PNMI_VCT_SUPPORTED 1\r
7061+#define SK_PNMI_VCT_NOT_SUPPORTED 0\r
7062+\r
7063+#define OID_SKGE_TRAP_SEN_WAR_LOW 500\r
7064+#define OID_SKGE_TRAP_SEN_WAR_UPP 501\r
7065+#define OID_SKGE_TRAP_SEN_ERR_LOW 502\r
7066+#define OID_SKGE_TRAP_SEN_ERR_UPP 503\r
7067+#define OID_SKGE_TRAP_RLMT_CHANGE_THRES 520\r
7068+#define OID_SKGE_TRAP_RLMT_CHANGE_PORT 521\r
7069+#define OID_SKGE_TRAP_RLMT_PORT_DOWN 522\r
7070+#define OID_SKGE_TRAP_RLMT_PORT_UP 523\r
7071+#define OID_SKGE_TRAP_RLMT_SEGMENTATION 524\r
7072+\r
7073+#ifdef SK_DIAG_SUPPORT\r
7074+/* Defines for driver DIAG mode. */\r
7075+#define SK_DIAG_ATTACHED 2\r
7076+#define SK_DIAG_RUNNING 1\r
7077+#define SK_DIAG_IDLE 0\r
7078+#endif /* SK_DIAG_SUPPORT */\r
7079+\r
7080+/*\r
7081+ * Generic PNMI IOCTL subcommand definitions.\r
7082+ */\r
7083+#define SK_GET_SINGLE_VAR 1\r
7084+#define SK_SET_SINGLE_VAR 2\r
7085+#define SK_PRESET_SINGLE_VAR 3\r
7086+#define SK_GET_FULL_MIB 4\r
7087+#define SK_SET_FULL_MIB 5\r
7088+#define SK_PRESET_FULL_MIB 6\r
7089+\r
7090+/*\r
7091+ * Define error numbers and messages for syslog\r
7092+ */\r
7093+#define SK_PNMI_ERR001 (SK_ERRBASE_PNMI + 1)\r
7094+#define SK_PNMI_ERR001MSG "SkPnmiGetStruct: Unknown OID"\r
7095+#define SK_PNMI_ERR002 (SK_ERRBASE_PNMI + 2)\r
7096+#define SK_PNMI_ERR002MSG "SkPnmiGetStruct: Cannot read VPD keys"\r
7097+#define SK_PNMI_ERR003 (SK_ERRBASE_PNMI + 3)\r
7098+#define SK_PNMI_ERR003MSG "OidStruct: Called with wrong OID"\r
7099+#define SK_PNMI_ERR004 (SK_ERRBASE_PNMI + 4)\r
7100+#define SK_PNMI_ERR004MSG "OidStruct: Called with wrong action"\r
7101+#define SK_PNMI_ERR005 (SK_ERRBASE_PNMI + 5)\r
7102+#define SK_PNMI_ERR005MSG "Perform: Cannot reset driver"\r
7103+#define SK_PNMI_ERR006 (SK_ERRBASE_PNMI + 6)\r
7104+#define SK_PNMI_ERR006MSG "Perform: Unknown OID action command"\r
7105+#define SK_PNMI_ERR007 (SK_ERRBASE_PNMI + 7)\r
7106+#define SK_PNMI_ERR007MSG "General: Driver description not initialized"\r
7107+#define SK_PNMI_ERR008 (SK_ERRBASE_PNMI + 8)\r
7108+#define SK_PNMI_ERR008MSG "Addr: Tried to get unknown OID"\r
7109+#define SK_PNMI_ERR009 (SK_ERRBASE_PNMI + 9)\r
7110+#define SK_PNMI_ERR009MSG "Addr: Unknown OID"\r
7111+#define SK_PNMI_ERR010 (SK_ERRBASE_PNMI + 10)\r
7112+#define SK_PNMI_ERR010MSG "CsumStat: Unknown OID"\r
7113+#define SK_PNMI_ERR011 (SK_ERRBASE_PNMI + 11)\r
7114+#define SK_PNMI_ERR011MSG "SensorStat: Sensor descr string too long"\r
7115+#define SK_PNMI_ERR012 (SK_ERRBASE_PNMI + 12)\r
7116+#define SK_PNMI_ERR012MSG "SensorStat: Unknown OID"\r
7117+#define SK_PNMI_ERR013 (SK_ERRBASE_PNMI + 13)\r
7118+#define SK_PNMI_ERR013MSG ""\r
7119+#define SK_PNMI_ERR014 (SK_ERRBASE_PNMI + 14)\r
7120+#define SK_PNMI_ERR014MSG "Vpd: Cannot read VPD keys"\r
7121+#define SK_PNMI_ERR015 (SK_ERRBASE_PNMI + 15)\r
7122+#define SK_PNMI_ERR015MSG "Vpd: Internal array for VPD keys too small"\r
7123+#define SK_PNMI_ERR016 (SK_ERRBASE_PNMI + 16)\r
7124+#define SK_PNMI_ERR016MSG "Vpd: Key string too long"\r
7125+#define SK_PNMI_ERR017 (SK_ERRBASE_PNMI + 17)\r
7126+#define SK_PNMI_ERR017MSG "Vpd: Invalid VPD status pointer"\r
7127+#define SK_PNMI_ERR018 (SK_ERRBASE_PNMI + 18)\r
7128+#define SK_PNMI_ERR018MSG "Vpd: VPD data not valid"\r
7129+#define SK_PNMI_ERR019 (SK_ERRBASE_PNMI + 19)\r
7130+#define SK_PNMI_ERR019MSG "Vpd: VPD entries list string too long"\r
7131+#define SK_PNMI_ERR021 (SK_ERRBASE_PNMI + 21)\r
7132+#define SK_PNMI_ERR021MSG "Vpd: VPD data string too long"\r
7133+#define SK_PNMI_ERR022 (SK_ERRBASE_PNMI + 22)\r
7134+#define SK_PNMI_ERR022MSG "Vpd: VPD data string too long should be errored before"\r
7135+#define SK_PNMI_ERR023 (SK_ERRBASE_PNMI + 23)\r
7136+#define SK_PNMI_ERR023MSG "Vpd: Unknown OID in get action"\r
7137+#define SK_PNMI_ERR024 (SK_ERRBASE_PNMI + 24)\r
7138+#define SK_PNMI_ERR024MSG "Vpd: Unknown OID in preset/set action"\r
7139+#define SK_PNMI_ERR025 (SK_ERRBASE_PNMI + 25)\r
7140+#define SK_PNMI_ERR025MSG "Vpd: Cannot write VPD after modify entry"\r
7141+#define SK_PNMI_ERR026 (SK_ERRBASE_PNMI + 26)\r
7142+#define SK_PNMI_ERR026MSG "Vpd: Cannot update VPD"\r
7143+#define SK_PNMI_ERR027 (SK_ERRBASE_PNMI + 27)\r
7144+#define SK_PNMI_ERR027MSG "Vpd: Cannot delete VPD entry"\r
7145+#define SK_PNMI_ERR028 (SK_ERRBASE_PNMI + 28)\r
7146+#define SK_PNMI_ERR028MSG "Vpd: Cannot update VPD after delete entry"\r
7147+#define SK_PNMI_ERR029 (SK_ERRBASE_PNMI + 29)\r
7148+#define SK_PNMI_ERR029MSG "General: Driver description string too long"\r
7149+#define SK_PNMI_ERR030 (SK_ERRBASE_PNMI + 30)\r
7150+#define SK_PNMI_ERR030MSG "General: Driver version not initialized"\r
7151+#define SK_PNMI_ERR031 (SK_ERRBASE_PNMI + 31)\r
7152+#define SK_PNMI_ERR031MSG "General: Driver version string too long"\r
7153+#define SK_PNMI_ERR032 (SK_ERRBASE_PNMI + 32)\r
7154+#define SK_PNMI_ERR032MSG "General: Cannot read VPD Name for HW descr"\r
7155+#define SK_PNMI_ERR033 (SK_ERRBASE_PNMI + 33)\r
7156+#define SK_PNMI_ERR033MSG "General: HW description string too long"\r
7157+#define SK_PNMI_ERR034 (SK_ERRBASE_PNMI + 34)\r
7158+#define SK_PNMI_ERR034MSG "General: Unknown OID"\r
7159+#define SK_PNMI_ERR035 (SK_ERRBASE_PNMI + 35)\r
7160+#define SK_PNMI_ERR035MSG "Rlmt: Unknown OID"\r
7161+#define SK_PNMI_ERR036 (SK_ERRBASE_PNMI + 36)\r
7162+#define SK_PNMI_ERR036MSG ""\r
7163+#define SK_PNMI_ERR037 (SK_ERRBASE_PNMI + 37)\r
7164+#define SK_PNMI_ERR037MSG "Rlmt: SK_RLMT_MODE_CHANGE event returned not 0"\r
7165+#define SK_PNMI_ERR038 (SK_ERRBASE_PNMI + 38)\r
7166+#define SK_PNMI_ERR038MSG "Rlmt: SK_RLMT_PREFPORT_CHANGE event returned not 0"\r
7167+#define SK_PNMI_ERR039 (SK_ERRBASE_PNMI + 39)\r
7168+#define SK_PNMI_ERR039MSG "RlmtStat: Unknown OID"\r
7169+#define SK_PNMI_ERR040 (SK_ERRBASE_PNMI + 40)\r
7170+#define SK_PNMI_ERR040MSG "PowerManagement: Unknown OID"\r
7171+#define SK_PNMI_ERR041 (SK_ERRBASE_PNMI + 41)\r
7172+#define SK_PNMI_ERR041MSG "MacPrivateConf: Unknown OID"\r
7173+#define SK_PNMI_ERR042 (SK_ERRBASE_PNMI + 42)\r
7174+#define SK_PNMI_ERR042MSG "MacPrivateConf: SK_HWEV_SET_ROLE returned not 0"\r
7175+#define SK_PNMI_ERR043 (SK_ERRBASE_PNMI + 43)\r
7176+#define SK_PNMI_ERR043MSG "MacPrivateConf: SK_HWEV_SET_LMODE returned not 0"\r
7177+#define SK_PNMI_ERR044 (SK_ERRBASE_PNMI + 44)\r
7178+#define SK_PNMI_ERR044MSG "MacPrivateConf: SK_HWEV_SET_FLOWMODE returned not 0"\r
7179+#define SK_PNMI_ERR045 (SK_ERRBASE_PNMI + 45)\r
7180+#define SK_PNMI_ERR045MSG "MacPrivateConf: SK_HWEV_SET_SPEED returned not 0"\r
7181+#define SK_PNMI_ERR046 (SK_ERRBASE_PNMI + 46)\r
7182+#define SK_PNMI_ERR046MSG "Monitor: Unknown OID"\r
7183+#define SK_PNMI_ERR047 (SK_ERRBASE_PNMI + 47)\r
7184+#define SK_PNMI_ERR047MSG "SirqUpdate: Event function returned not 0"\r
7185+#define SK_PNMI_ERR048 (SK_ERRBASE_PNMI + 48)\r
7186+#define SK_PNMI_ERR048MSG "RlmtUpdate: Event function returned not 0"\r
7187+#define SK_PNMI_ERR049 (SK_ERRBASE_PNMI + 49)\r
7188+#define SK_PNMI_ERR049MSG "SkPnmiInit: Invalid size of 'CounterOffset' struct!!"\r
7189+#define SK_PNMI_ERR050 (SK_ERRBASE_PNMI + 50)\r
7190+#define SK_PNMI_ERR050MSG "SkPnmiInit: Invalid size of 'StatAddr' table!!"\r
7191+#define SK_PNMI_ERR051 (SK_ERRBASE_PNMI + 51)\r
7192+#define SK_PNMI_ERR051MSG "SkPnmiEvent: Port switch suspicious"\r
7193+#define SK_PNMI_ERR052 (SK_ERRBASE_PNMI + 52)\r
7194+#define SK_PNMI_ERR052MSG ""\r
7195+#define SK_PNMI_ERR053 (SK_ERRBASE_PNMI + 53)\r
7196+#define SK_PNMI_ERR053MSG "General: Driver release date not initialized"\r
7197+#define SK_PNMI_ERR054 (SK_ERRBASE_PNMI + 54)\r
7198+#define SK_PNMI_ERR054MSG "General: Driver release date string too long"\r
7199+#define SK_PNMI_ERR055 (SK_ERRBASE_PNMI + 55)\r
7200+#define SK_PNMI_ERR055MSG "General: Driver file name not initialized"\r
7201+#define SK_PNMI_ERR056 (SK_ERRBASE_PNMI + 56)\r
7202+#define SK_PNMI_ERR056MSG "General: Driver file name string too long"\r
7203+\r
7204+/*\r
7205+ * Management counter macros called by the driver\r
7206+ */\r
7207+#define SK_PNMI_SET_DRIVER_DESCR(pAC,v) ((pAC)->Pnmi.pDriverDescription = \\r
7208+ (char *)(v))\r
7209+\r
7210+#define SK_PNMI_SET_DRIVER_VER(pAC,v) ((pAC)->Pnmi.pDriverVersion = \\r
7211+ (char *)(v))\r
7212+\r
7213+#define SK_PNMI_SET_DRIVER_RELDATE(pAC,v) ((pAC)->Pnmi.pDriverReleaseDate = \\r
7214+ (char *)(v))\r
7215+\r
7216+#define SK_PNMI_SET_DRIVER_FILENAME(pAC,v) ((pAC)->Pnmi.pDriverFileName = \\r
7217+ (char *)(v))\r
7218+\r
7219+#define SK_PNMI_CNT_TX_QUEUE_LEN(pAC,v,p) \\r
7220+ { \\r
7221+ (pAC)->Pnmi.Port[p].TxSwQueueLen = (SK_U64)(v); \\r
7222+ if ((pAC)->Pnmi.Port[p].TxSwQueueLen > (pAC)->Pnmi.Port[p].TxSwQueueMax) { \\r
7223+ (pAC)->Pnmi.Port[p].TxSwQueueMax = (pAC)->Pnmi.Port[p].TxSwQueueLen; \\r
7224+ } \\r
7225+ }\r
7226+#define SK_PNMI_CNT_TX_RETRY(pAC,p) (((pAC)->Pnmi.Port[p].TxRetryCts)++)\r
7227+#define SK_PNMI_CNT_RX_INTR(pAC,p) (((pAC)->Pnmi.Port[p].RxIntrCts)++)\r
7228+#define SK_PNMI_CNT_TX_INTR(pAC,p) (((pAC)->Pnmi.Port[p].TxIntrCts)++)\r
7229+#define SK_PNMI_CNT_NO_RX_BUF(pAC,p) (((pAC)->Pnmi.Port[p].RxNoBufCts)++)\r
7230+#define SK_PNMI_CNT_NO_TX_BUF(pAC,p) (((pAC)->Pnmi.Port[p].TxNoBufCts)++)\r
7231+#define SK_PNMI_CNT_USED_TX_DESCR(pAC,v,p) \\r
7232+ ((pAC)->Pnmi.Port[p].TxUsedDescrNo=(SK_U64)(v));\r
7233+#define SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC,v,p) \\r
7234+ { \\r
7235+ ((pAC)->Pnmi.Port[p].RxDeliveredCts)++; \\r
7236+ (pAC)->Pnmi.Port[p].RxOctetsDeliveredCts += (SK_U64)(v); \\r
7237+ }\r
7238+#define SK_PNMI_CNT_ERR_RECOVERY(pAC,p) (((pAC)->Pnmi.Port[p].ErrRecoveryCts)++);\r
7239+\r
7240+#define SK_PNMI_CNT_SYNC_OCTETS(pAC,p,v) \\r
7241+ { \\r
7242+ if ((p) < SK_MAX_MACS) { \\r
7243+ ((pAC)->Pnmi.Port[p].StatSyncCts)++; \\r
7244+ (pAC)->Pnmi.Port[p].StatSyncOctetsCts += (SK_U64)(v); \\r
7245+ } \\r
7246+ }\r
7247+\r
7248+#define SK_PNMI_CNT_RX_LONGFRAMES(pAC,p) \\r
7249+ { \\r
7250+ if ((p) < SK_MAX_MACS) { \\r
7251+ ((pAC)->Pnmi.Port[p].StatRxLongFrameCts++); \\r
7252+ } \\r
7253+ }\r
7254+\r
7255+#define SK_PNMI_CNT_RX_FRAMETOOLONG(pAC,p) \\r
7256+ { \\r
7257+ if ((p) < SK_MAX_MACS) { \\r
7258+ ((pAC)->Pnmi.Port[p].StatRxFrameTooLongCts++); \\r
7259+ } \\r
7260+ }\r
7261+\r
7262+#define SK_PNMI_CNT_RX_PMACC_ERR(pAC,p) \\r
7263+ { \\r
7264+ if ((p) < SK_MAX_MACS) { \\r
7265+ ((pAC)->Pnmi.Port[p].StatRxPMaccErr++); \\r
7266+ } \\r
7267+ }\r
7268+\r
7269+/*\r
7270+ * Conversion Macros\r
7271+ */\r
7272+#define SK_PNMI_PORT_INST2LOG(i) ((unsigned int)(i) - 1)\r
7273+#define SK_PNMI_PORT_LOG2INST(l) ((unsigned int)(l) + 1)\r
7274+#define SK_PNMI_PORT_PHYS2LOG(p) ((unsigned int)(p) + 1)\r
7275+#define SK_PNMI_PORT_LOG2PHYS(pAC,l) ((unsigned int)(l) - 1)\r
7276+#define SK_PNMI_PORT_PHYS2INST(pAC,p) \\r
7277+ (pAC->Pnmi.DualNetActiveFlag ? 2 : ((unsigned int)(p) + 2))\r
7278+#define SK_PNMI_PORT_INST2PHYS(pAC,i) ((unsigned int)(i) - 2)\r
7279+\r
7280+/*\r
7281+ * Structure definition for SkPnmiGetStruct and SkPnmiSetStruct\r
7282+ */\r
7283+#define SK_PNMI_VPD_KEY_SIZE 5\r
7284+#define SK_PNMI_VPD_BUFSIZE (VPD_SIZE)\r
7285+#define SK_PNMI_VPD_ENTRIES (VPD_SIZE / 4)\r
7286+#define SK_PNMI_VPD_DATALEN 128 /* Number of data bytes */\r
7287+\r
7288+#define SK_PNMI_MULTICAST_LISTLEN 64\r
7289+#define SK_PNMI_SENSOR_ENTRIES (SK_MAX_SENSORS)\r
7290+#define SK_PNMI_CHECKSUM_ENTRIES 3\r
7291+#define SK_PNMI_MAC_ENTRIES (SK_MAX_MACS + 1)\r
7292+#define SK_PNMI_MONITOR_ENTRIES 20\r
7293+#define SK_PNMI_TRAP_ENTRIES 10\r
7294+#define SK_PNMI_TRAPLEN 128\r
7295+#define SK_PNMI_STRINGLEN1 80\r
7296+#define SK_PNMI_STRINGLEN2 25\r
7297+#define SK_PNMI_TRAP_QUEUE_LEN 512\r
7298+\r
7299+typedef struct s_PnmiVpd {\r
7300+ char VpdKey[SK_PNMI_VPD_KEY_SIZE];\r
7301+ char VpdValue[SK_PNMI_VPD_DATALEN];\r
7302+ SK_U8 VpdAccess;\r
7303+ SK_U8 VpdAction;\r
7304+} SK_PNMI_VPD;\r
7305+\r
7306+typedef struct s_PnmiSensor {\r
7307+ SK_U8 SensorIndex;\r
7308+ char SensorDescr[SK_PNMI_STRINGLEN2];\r
7309+ SK_U8 SensorType;\r
7310+ SK_U32 SensorValue;\r
7311+ SK_U32 SensorWarningThresholdLow;\r
7312+ SK_U32 SensorWarningThresholdHigh;\r
7313+ SK_U32 SensorErrorThresholdLow;\r
7314+ SK_U32 SensorErrorThresholdHigh;\r
7315+ SK_U8 SensorStatus;\r
7316+ SK_U64 SensorWarningCts;\r
7317+ SK_U64 SensorErrorCts;\r
7318+ SK_U64 SensorWarningTimestamp;\r
7319+ SK_U64 SensorErrorTimestamp;\r
7320+} SK_PNMI_SENSOR;\r
7321+\r
7322+typedef struct s_PnmiChecksum {\r
7323+ SK_U64 ChecksumRxOkCts;\r
7324+ SK_U64 ChecksumRxUnableCts;\r
7325+ SK_U64 ChecksumRxErrCts;\r
7326+ SK_U64 ChecksumTxOkCts;\r
7327+ SK_U64 ChecksumTxUnableCts;\r
7328+} SK_PNMI_CHECKSUM;\r
7329+\r
7330+typedef struct s_PnmiStat {\r
7331+ SK_U64 StatTxOkCts;\r
7332+ SK_U64 StatTxOctetsOkCts;\r
7333+ SK_U64 StatTxBroadcastOkCts;\r
7334+ SK_U64 StatTxMulticastOkCts;\r
7335+ SK_U64 StatTxUnicastOkCts;\r
7336+ SK_U64 StatTxLongFramesCts;\r
7337+ SK_U64 StatTxBurstCts;\r
7338+ SK_U64 StatTxPauseMacCtrlCts;\r
7339+ SK_U64 StatTxMacCtrlCts;\r
7340+ SK_U64 StatTxSingleCollisionCts;\r
7341+ SK_U64 StatTxMultipleCollisionCts;\r
7342+ SK_U64 StatTxExcessiveCollisionCts;\r
7343+ SK_U64 StatTxLateCollisionCts;\r
7344+ SK_U64 StatTxDeferralCts;\r
7345+ SK_U64 StatTxExcessiveDeferralCts;\r
7346+ SK_U64 StatTxFifoUnderrunCts;\r
7347+ SK_U64 StatTxCarrierCts;\r
7348+ SK_U64 Dummy1; /* StatTxUtilization */\r
7349+ SK_U64 StatTx64Cts;\r
7350+ SK_U64 StatTx127Cts;\r
7351+ SK_U64 StatTx255Cts;\r
7352+ SK_U64 StatTx511Cts;\r
7353+ SK_U64 StatTx1023Cts;\r
7354+ SK_U64 StatTxMaxCts;\r
7355+ SK_U64 StatTxSyncCts;\r
7356+ SK_U64 StatTxSyncOctetsCts;\r
7357+ SK_U64 StatRxOkCts;\r
7358+ SK_U64 StatRxOctetsOkCts;\r
7359+ SK_U64 StatRxBroadcastOkCts;\r
7360+ SK_U64 StatRxMulticastOkCts;\r
7361+ SK_U64 StatRxUnicastOkCts;\r
7362+ SK_U64 StatRxLongFramesCts;\r
7363+ SK_U64 StatRxPauseMacCtrlCts;\r
7364+ SK_U64 StatRxMacCtrlCts;\r
7365+ SK_U64 StatRxPauseMacCtrlErrorCts;\r
7366+ SK_U64 StatRxMacCtrlUnknownCts;\r
7367+ SK_U64 StatRxBurstCts;\r
7368+ SK_U64 StatRxMissedCts;\r
7369+ SK_U64 StatRxFramingCts;\r
7370+ SK_U64 StatRxFifoOverflowCts;\r
7371+ SK_U64 StatRxJabberCts;\r
7372+ SK_U64 StatRxCarrierCts;\r
7373+ SK_U64 StatRxIRLengthCts;\r
7374+ SK_U64 StatRxSymbolCts;\r
7375+ SK_U64 StatRxShortsCts;\r
7376+ SK_U64 StatRxRuntCts;\r
7377+ SK_U64 StatRxCextCts;\r
7378+ SK_U64 StatRxTooLongCts;\r
7379+ SK_U64 StatRxFcsCts;\r
7380+ SK_U64 Dummy2; /* StatRxUtilization */\r
7381+ SK_U64 StatRx64Cts;\r
7382+ SK_U64 StatRx127Cts;\r
7383+ SK_U64 StatRx255Cts;\r
7384+ SK_U64 StatRx511Cts;\r
7385+ SK_U64 StatRx1023Cts;\r
7386+ SK_U64 StatRxMaxCts;\r
7387+} SK_PNMI_STAT;\r
7388+\r
7389+typedef struct s_PnmiConf {\r
7390+ char ConfMacCurrentAddr[6];\r
7391+ char ConfMacFactoryAddr[6];\r
7392+ SK_U8 ConfPMD;\r
7393+ SK_U8 ConfConnector;\r
7394+ SK_U32 ConfPhyType;\r
7395+ SK_U32 ConfPhyMode;\r
7396+ SK_U8 ConfLinkCapability;\r
7397+ SK_U8 ConfLinkMode;\r
7398+ SK_U8 ConfLinkModeStatus;\r
7399+ SK_U8 ConfLinkStatus;\r
7400+ SK_U8 ConfFlowCtrlCapability;\r
7401+ SK_U8 ConfFlowCtrlMode;\r
7402+ SK_U8 ConfFlowCtrlStatus;\r
7403+ SK_U8 ConfPhyOperationCapability;\r
7404+ SK_U8 ConfPhyOperationMode;\r
7405+ SK_U8 ConfPhyOperationStatus;\r
7406+ SK_U8 ConfSpeedCapability;\r
7407+ SK_U8 ConfSpeedMode;\r
7408+ SK_U8 ConfSpeedStatus;\r
7409+} SK_PNMI_CONF;\r
7410+\r
7411+typedef struct s_PnmiRlmt {\r
7412+ SK_U32 RlmtIndex;\r
7413+ SK_U32 RlmtStatus;\r
7414+ SK_U64 RlmtTxHelloCts;\r
7415+ SK_U64 RlmtRxHelloCts;\r
7416+ SK_U64 RlmtTxSpHelloReqCts;\r
7417+ SK_U64 RlmtRxSpHelloCts;\r
7418+} SK_PNMI_RLMT;\r
7419+\r
7420+typedef struct s_PnmiRlmtMonitor {\r
7421+ SK_U32 RlmtMonitorIndex;\r
7422+ char RlmtMonitorAddr[6];\r
7423+ SK_U64 RlmtMonitorErrorCts;\r
7424+ SK_U64 RlmtMonitorTimestamp;\r
7425+ SK_U8 RlmtMonitorAdmin;\r
7426+} SK_PNMI_RLMT_MONITOR;\r
7427+\r
7428+typedef struct s_PnmiRequestStatus {\r
7429+ SK_U32 ErrorStatus;\r
7430+ SK_U32 ErrorOffset;\r
7431+} SK_PNMI_REQUEST_STATUS;\r
7432+\r
7433+typedef struct s_PnmiStrucData {\r
7434+ SK_U32 MgmtDBVersion;\r
7435+ SK_PNMI_REQUEST_STATUS ReturnStatus;\r
7436+ SK_U32 VpdFreeBytes;\r
7437+ char VpdEntriesList[SK_PNMI_VPD_ENTRIES * SK_PNMI_VPD_KEY_SIZE];\r
7438+ SK_U32 VpdEntriesNumber;\r
7439+ SK_PNMI_VPD Vpd[SK_PNMI_VPD_ENTRIES];\r
7440+ SK_U32 PortNumber;\r
7441+ SK_U32 DeviceType;\r
7442+ char DriverDescr[SK_PNMI_STRINGLEN1];\r
7443+ char DriverVersion[SK_PNMI_STRINGLEN2];\r
7444+ char DriverReleaseDate[SK_PNMI_STRINGLEN1];\r
7445+ char DriverFileName[SK_PNMI_STRINGLEN1];\r
7446+ char HwDescr[SK_PNMI_STRINGLEN1];\r
7447+ char HwVersion[SK_PNMI_STRINGLEN2];\r
7448+ SK_U16 Chipset;\r
7449+ SK_U32 ChipId;\r
7450+ SK_U8 VauxAvail;\r
7451+ SK_U32 RamSize;\r
7452+ SK_U32 MtuSize;\r
7453+ SK_U32 Action;\r
7454+ SK_U32 TestResult;\r
7455+ SK_U8 BusType;\r
7456+ SK_U8 BusSpeed;\r
7457+ SK_U8 BusWidth;\r
7458+ SK_U8 SensorNumber;\r
7459+ SK_PNMI_SENSOR Sensor[SK_PNMI_SENSOR_ENTRIES];\r
7460+ SK_U8 ChecksumNumber;\r
7461+ SK_PNMI_CHECKSUM Checksum[SK_PNMI_CHECKSUM_ENTRIES];\r
7462+ SK_PNMI_STAT Stat[SK_PNMI_MAC_ENTRIES];\r
7463+ SK_PNMI_CONF Conf[SK_PNMI_MAC_ENTRIES];\r
7464+ SK_U8 RlmtMode;\r
7465+ SK_U32 RlmtPortNumber;\r
7466+ SK_U8 RlmtPortActive;\r
7467+ SK_U8 RlmtPortPreferred;\r
7468+ SK_U64 RlmtChangeCts;\r
7469+ SK_U64 RlmtChangeTime;\r
7470+ SK_U64 RlmtChangeEstimate;\r
7471+ SK_U64 RlmtChangeThreshold;\r
7472+ SK_PNMI_RLMT Rlmt[SK_MAX_MACS];\r
7473+ SK_U32 RlmtMonitorNumber;\r
7474+ SK_PNMI_RLMT_MONITOR RlmtMonitor[SK_PNMI_MONITOR_ENTRIES];\r
7475+ SK_U32 TrapNumber;\r
7476+ SK_U8 Trap[SK_PNMI_TRAP_QUEUE_LEN];\r
7477+ SK_U64 TxSwQueueLen;\r
7478+ SK_U64 TxSwQueueMax;\r
7479+ SK_U64 TxRetryCts;\r
7480+ SK_U64 RxIntrCts;\r
7481+ SK_U64 TxIntrCts;\r
7482+ SK_U64 RxNoBufCts;\r
7483+ SK_U64 TxNoBufCts;\r
7484+ SK_U64 TxUsedDescrNo;\r
7485+ SK_U64 RxDeliveredCts;\r
7486+ SK_U64 RxOctetsDeliveredCts;\r
7487+ SK_U64 RxHwErrorsCts;\r
7488+ SK_U64 TxHwErrorsCts;\r
7489+ SK_U64 InErrorsCts;\r
7490+ SK_U64 OutErrorsCts;\r
7491+ SK_U64 ErrRecoveryCts;\r
7492+ SK_U64 SysUpTime;\r
7493+} SK_PNMI_STRUCT_DATA;\r
7494+\r
7495+#define SK_PNMI_STRUCT_SIZE (sizeof(SK_PNMI_STRUCT_DATA))\r
7496+\r
7497+/* The ReturnStatus field must be located before VpdFreeBytes! */\r
7498+#define SK_PNMI_MIN_STRUCT_SIZE ((unsigned int)(SK_UPTR)\\r
7499+ &(((SK_PNMI_STRUCT_DATA *)0)->VpdFreeBytes))\r
7500+\r
7501+/*\r
7502+ * Various definitions\r
7503+ */\r
7504+#define SK_PNMI_EVT_TIMER_CHECK 28125000L /* 28125 ms */\r
7505+\r
7506+#define SK_PNMI_VCT_TIMER_CHECK 4000000L /* 4 sec. */\r
7507+\r
7508+#define SK_PNMI_MAX_PROTOS 3\r
7509+\r
7510+/*\r
7511+ * SK_PNMI_CNT_NO must have the value of the enum SK_PNMI_MAX_IDX.\r
7512+ * Define SK_PNMI_CHECK to check this during init level SK_INIT_IO.\r
7513+ */\r
7514+#define SK_PNMI_CNT_NO 66\r
7515+\r
7516+/*\r
7517+ * Estimate data structure\r
7518+ */\r
7519+typedef struct s_PnmiEstimate {\r
7520+ unsigned int EstValueIndex;\r
7521+ SK_U64 EstValue[7];\r
7522+ SK_U64 Estimate;\r
7523+ SK_TIMER EstTimer;\r
7524+} SK_PNMI_ESTIMATE;\r
7525+\r
7526+\r
7527+/*\r
7528+ * PNMI specific adapter context structure\r
7529+ */\r
7530+typedef struct s_PnmiPort {\r
7531+ SK_U64 StatSyncCts;\r
7532+ SK_U64 StatSyncOctetsCts;\r
7533+ SK_U64 StatRxLongFrameCts;\r
7534+ SK_U64 StatRxFrameTooLongCts;\r
7535+ SK_U64 StatRxPMaccErr;\r
7536+ SK_U64 TxSwQueueLen;\r
7537+ SK_U64 TxSwQueueMax;\r
7538+ SK_U64 TxRetryCts;\r
7539+ SK_U64 RxIntrCts;\r
7540+ SK_U64 TxIntrCts;\r
7541+ SK_U64 RxNoBufCts;\r
7542+ SK_U64 TxNoBufCts;\r
7543+ SK_U64 TxUsedDescrNo;\r
7544+ SK_U64 RxDeliveredCts;\r
7545+ SK_U64 RxOctetsDeliveredCts;\r
7546+ SK_U64 RxHwErrorsCts;\r
7547+ SK_U64 TxHwErrorsCts;\r
7548+ SK_U64 InErrorsCts;\r
7549+ SK_U64 OutErrorsCts;\r
7550+ SK_U64 ErrRecoveryCts;\r
7551+ SK_U64 RxShortZeroMark;\r
7552+ SK_U64 CounterOffset[SK_PNMI_CNT_NO];\r
7553+ SK_U32 CounterHigh[SK_PNMI_CNT_NO];\r
7554+ SK_BOOL ActiveFlag;\r
7555+ SK_U8 Align[3];\r
7556+} SK_PNMI_PORT;\r
7557+\r
7558+\r
7559+typedef struct s_PnmiData {\r
7560+ SK_PNMI_PORT Port [SK_MAX_MACS];\r
7561+ SK_PNMI_PORT BufPort [SK_MAX_MACS]; /* 2002-09-13 pweber */\r
7562+ SK_U64 VirtualCounterOffset[SK_PNMI_CNT_NO];\r
7563+ SK_U32 TestResult;\r
7564+ char HwVersion[10];\r
7565+ SK_U16 Align01;\r
7566+\r
7567+ char *pDriverDescription;\r
7568+ char *pDriverVersion;\r
7569+ char *pDriverReleaseDate;\r
7570+ char *pDriverFileName;\r
7571+\r
7572+ int MacUpdatedFlag;\r
7573+ int RlmtUpdatedFlag;\r
7574+ int SirqUpdatedFlag;\r
7575+\r
7576+ SK_U64 RlmtChangeCts;\r
7577+ SK_U64 RlmtChangeTime;\r
7578+ SK_PNMI_ESTIMATE RlmtChangeEstimate;\r
7579+ SK_U64 RlmtChangeThreshold;\r
7580+\r
7581+ SK_U64 StartUpTime;\r
7582+ SK_U32 DeviceType;\r
7583+ char PciBusSpeed;\r
7584+ char PciBusWidth;\r
7585+ char Chipset;\r
7586+ char PMD;\r
7587+ char Connector;\r
7588+ SK_BOOL DualNetActiveFlag;\r
7589+ SK_U16 Align02;\r
7590+\r
7591+ char TrapBuf[SK_PNMI_TRAP_QUEUE_LEN];\r
7592+ unsigned int TrapBufFree;\r
7593+ unsigned int TrapQueueBeg;\r
7594+ unsigned int TrapQueueEnd;\r
7595+ unsigned int TrapBufPad;\r
7596+ unsigned int TrapUnique;\r
7597+ SK_U8 VctStatus[SK_MAX_MACS];\r
7598+ SK_PNMI_VCT VctBackup[SK_MAX_MACS];\r
7599+ SK_TIMER VctTimeout[SK_MAX_MACS];\r
7600+#ifdef SK_DIAG_SUPPORT\r
7601+ SK_U32 DiagAttached;\r
7602+#endif /* SK_DIAG_SUPPORT */\r
7603+ SK_BOOL VpdKeyReadError;\r
7604+} SK_PNMI;\r
7605+\r
7606+\r
7607+/*\r
7608+ * Function prototypes\r
7609+ */\r
7610+extern int SkPnmiInit(SK_AC *pAC, SK_IOC IoC, int Level);\r
7611+extern int SkPnmiGetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void* pBuf,\r
7612+ unsigned int* pLen, SK_U32 Instance, SK_U32 NetIndex);\r
7613+extern int SkPnmiPreSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id,\r
7614+ void* pBuf, unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex);\r
7615+extern int SkPnmiSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void* pBuf,\r
7616+ unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex);\r
7617+extern int SkPnmiGetStruct(SK_AC *pAC, SK_IOC IoC, void* pBuf,\r
7618+ unsigned int *pLen, SK_U32 NetIndex);\r
7619+extern int SkPnmiPreSetStruct(SK_AC *pAC, SK_IOC IoC, void* pBuf,\r
7620+ unsigned int *pLen, SK_U32 NetIndex);\r
7621+extern int SkPnmiSetStruct(SK_AC *pAC, SK_IOC IoC, void* pBuf,\r
7622+ unsigned int *pLen, SK_U32 NetIndex);\r
7623+extern int SkPnmiEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event,\r
7624+ SK_EVPARA Param);\r
7625+extern int SkPnmiGenIoctl(SK_AC *pAC, SK_IOC IoC, void * pBuf,\r
7626+ unsigned int * pLen, SK_U32 NetIndex);\r
7627+\r
7628+#endif\r
7629diff -ruN linux/drivers/net/sk98lin/h/skgesirq.h linux-new/drivers/net/sk98lin/h/skgesirq.h
7630--- linux/drivers/net/sk98lin/h/skgesirq.h 2006-04-11 19:19:28.000000000 +0200
7631+++ linux-new/drivers/net/sk98lin/h/skgesirq.h 2006-01-18 14:37:24.000000000 +0100
7632@@ -2,23 +2,24 @@
7633 *
7634 * Name: skgesirq.h
7635 * Project: Gigabit Ethernet Adapters, Common Modules
7636- * Version: $Revision$
7637- * Date: $Date$
7638- * Purpose: SK specific Gigabit Ethernet special IRQ functions
7639+ * Version: $Revision$
7640+ * Date: $Date$
7641+ * Purpose: Gigabit Ethernet special IRQ functions
7642 *
7643 ******************************************************************************/
7644
7645 /******************************************************************************
7646 *
7647+ * LICENSE:
7648 * (C)Copyright 1998-2002 SysKonnect.
7649- * (C)Copyright 2002-2003 Marvell.
7650+ * (C)Copyright 2002-2005 Marvell.
7651 *
7652 * This program is free software; you can redistribute it and/or modify
7653 * it under the terms of the GNU General Public License as published by
7654 * the Free Software Foundation; either version 2 of the License, or
7655 * (at your option) any later version.
7656- *
7657 * The information in this file is provided "AS IS" without warranty.
7658+ * /LICENSE
7659 *
7660 ******************************************************************************/
7661
7662@@ -26,9 +27,9 @@
7663 #define _INC_SKGESIRQ_H_
7664
7665 /* Define return codes of SkGePortCheckUp and CheckShort */
7666-#define SK_HW_PS_NONE 0 /* No action needed */
7667-#define SK_HW_PS_RESTART 1 /* Restart needed */
7668-#define SK_HW_PS_LINK 2 /* Link Up actions needed */
7669+#define SK_HW_PS_NONE 0 /* No action needed */
7670+#define SK_HW_PS_RESTART 1 /* Restart needed */
7671+#define SK_HW_PS_LINK 2 /* Link Up actions needed */
7672
7673 /*
7674 * Define the Event the special IRQ/INI module can handle
7675@@ -44,10 +45,10 @@
7676 #define SK_HWEV_SET_SPEED 9 /* Set Link Speed by PNMI */
7677 #define SK_HWEV_HALFDUP_CHK 10 /* Half Duplex Hangup Workaround */
7678
7679-#define SK_WA_ACT_TIME (5000000UL) /* 5 sec */
7680-#define SK_WA_INA_TIME (100000UL) /* 100 msec */
7681+#define SK_WA_ACT_TIME 1000000UL /* 1000 msec (1 sec) */
7682+#define SK_WA_INA_TIME 100000UL /* 100 msec */
7683
7684-#define SK_HALFDUP_CHK_TIME (10000UL) /* 10 msec */
7685+#define SK_HALFDUP_CHK_TIME 10000UL /* 10 msec */
7686
7687 /*
7688 * Define the error numbers and messages
7689@@ -75,9 +76,9 @@
7690 #define SKERR_SIRQ_E011 (SKERR_SIRQ_E010+1)
7691 #define SKERR_SIRQ_E011MSG "CHECK failure XA2"
7692 #define SKERR_SIRQ_E012 (SKERR_SIRQ_E011+1)
7693-#define SKERR_SIRQ_E012MSG "unexpected IRQ Master error"
7694+#define SKERR_SIRQ_E012MSG "Unexpected IRQ Master error"
7695 #define SKERR_SIRQ_E013 (SKERR_SIRQ_E012+1)
7696-#define SKERR_SIRQ_E013MSG "unexpected IRQ Status error"
7697+#define SKERR_SIRQ_E013MSG "Unexpected IRQ Status error"
7698 #define SKERR_SIRQ_E014 (SKERR_SIRQ_E013+1)
7699 #define SKERR_SIRQ_E014MSG "Parity error on RAM (read)"
7700 #define SKERR_SIRQ_E015 (SKERR_SIRQ_E014+1)
7701@@ -102,10 +103,35 @@
7702 #define SKERR_SIRQ_E024MSG "FIFO overflow error"
7703 #define SKERR_SIRQ_E025 (SKERR_SIRQ_E024+1)
7704 #define SKERR_SIRQ_E025MSG "2 Pair Downshift detected"
7705+#define SKERR_SIRQ_E026 (SKERR_SIRQ_E025+1)
7706+#define SKERR_SIRQ_E026MSG "Uncorrectable PCI Express error"
7707+#define SKERR_SIRQ_E027 (SKERR_SIRQ_E026+1)
7708+#define SKERR_SIRQ_E027MSG "PCI Bus Abort detected"
7709+#define SKERR_SIRQ_E028 (SKERR_SIRQ_E027+1)
7710+#define SKERR_SIRQ_E028MSG "Parity error on RAM 1 (read)"
7711+#define SKERR_SIRQ_E029 (SKERR_SIRQ_E028+1)
7712+#define SKERR_SIRQ_E029MSG "Parity error on RAM 1 (write)"
7713+#define SKERR_SIRQ_E030 (SKERR_SIRQ_E029+1)
7714+#define SKERR_SIRQ_E030MSG "Parity error on RAM 2 (read)"
7715+#define SKERR_SIRQ_E031 (SKERR_SIRQ_E030+1)
7716+#define SKERR_SIRQ_E031MSG "Parity error on RAM 2 (write)"
7717+#define SKERR_SIRQ_E032 (SKERR_SIRQ_E031+1)
7718+#define SKERR_SIRQ_E032MSG "TCP segmentation error async. queue 1"
7719+#define SKERR_SIRQ_E033 (SKERR_SIRQ_E032+1)
7720+#define SKERR_SIRQ_E033MSG "TCP segmentation error sync. queue 1"
7721+#define SKERR_SIRQ_E034 (SKERR_SIRQ_E033+1)
7722+#define SKERR_SIRQ_E034MSG "TCP segmentation error async. queue 2"
7723+#define SKERR_SIRQ_E035 (SKERR_SIRQ_E034+1)
7724+#define SKERR_SIRQ_E035MSG "TCP segmentation error sync. queue 2"
7725+#define SKERR_SIRQ_E036 (SKERR_SIRQ_E035+1)
7726+#define SKERR_SIRQ_E036MSG "CHECK failure polling unit"
7727
7728 extern void SkGeSirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus);
7729 extern int SkGeSirqEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Para);
7730 extern void SkHWLinkUp(SK_AC *pAC, SK_IOC IoC, int Port);
7731 extern void SkHWLinkDown(SK_AC *pAC, SK_IOC IoC, int Port);
7732+extern void SkGeYuSirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus);
7733+extern void SkYuk2SirqIsr(SK_AC *pAC, SK_IOC IoC, SK_U32 Istatus);
7734
7735 #endif /* _INC_SKGESIRQ_H_ */
7736+
7737diff -ruN linux/drivers/net/sk98lin/h/skgetwsi.h linux-new/drivers/net/sk98lin/h/skgetwsi.h
7738--- linux/drivers/net/sk98lin/h/skgetwsi.h 1970-01-01 01:00:00.000000000 +0100
7739+++ linux-new/drivers/net/sk98lin/h/skgetwsi.h 2006-01-18 14:37:24.000000000 +0100
7740@@ -0,0 +1,241 @@
7741+/******************************************************************************
7742+ *
7743+ * Name: skgetwsi.h
7744+ * Project: Gigabit Ethernet Adapters, TWSI-Module
7745+ * Version: $Revision$
7746+ * Date: $Date$
7747+ * Purpose: Special defines for TWSI
7748+ *
7749+ ******************************************************************************/
7750+
7751+/******************************************************************************
7752+ *
7753+ * (C)Copyright 1998-2002 SysKonnect.
7754+ * (C)Copyright 2002-2004 Marvell.
7755+ *
7756+ * This program is free software; you can redistribute it and/or modify
7757+ * it under the terms of the GNU General Public License as published by
7758+ * the Free Software Foundation; either version 2 of the License, or
7759+ * (at your option) any later version.
7760+ * The information in this file is provided "AS IS" without warranty.
7761+ *
7762+ ******************************************************************************/
7763+
7764+/*
7765+ * SKGETWSI.H contains all SK-98xx specific defines for the TWSI handling
7766+ */
7767+
7768+#ifndef _INC_SKGETWSI_H_
7769+#define _INC_SKGETWSI_H_
7770+
7771+/*
7772+ * Macros to access the B2_I2C_CTRL
7773+ */
7774+#define SK_I2C_CTL(IoC, flag, dev, dev_size, reg, burst) \
7775+ SK_OUT32(IoC, B2_I2C_CTRL,\
7776+ (flag ? 0x80000000UL : 0x0L) | \
7777+ (((SK_U32)reg << 16) & I2C_ADDR) | \
7778+ (((SK_U32)dev << 9) & I2C_DEV_SEL) | \
7779+ (dev_size & I2C_DEV_SIZE) | \
7780+ ((burst << 4) & I2C_BURST_LEN))
7781+
7782+#define SK_I2C_STOP(IoC) { \
7783+ SK_U32 I2cCtrl; \
7784+ SK_IN32(IoC, B2_I2C_CTRL, &I2cCtrl); \
7785+ SK_OUT32(IoC, B2_I2C_CTRL, I2cCtrl | I2C_STOP); \
7786+}
7787+
7788+#define SK_I2C_GET_CTL(IoC, pI2cCtrl) SK_IN32(IoC, B2_I2C_CTRL, pI2cCtrl)
7789+
7790+/*
7791+ * Macros to access the TWSI SW Registers
7792+ */
7793+#define SK_I2C_SET_BIT(IoC, SetBits) { \
7794+ SK_U8 OrgBits; \
7795+ SK_IN8(IoC, B2_I2C_SW, &OrgBits); \
7796+ SK_OUT8(IoC, B2_I2C_SW, OrgBits | (SK_U8)(SetBits)); \
7797+}
7798+
7799+#define SK_I2C_CLR_BIT(IoC, ClrBits) { \
7800+ SK_U8 OrgBits; \
7801+ SK_IN8(IoC, B2_I2C_SW, &OrgBits); \
7802+ SK_OUT8(IoC, B2_I2C_SW, OrgBits & ~((SK_U8)(ClrBits))); \
7803+}
7804+
7805+#define SK_I2C_GET_SW(IoC, pI2cSw) SK_IN8(IoC, B2_I2C_SW, pI2cSw)
7806+
7807+/*
7808+ * define the possible sensor states
7809+ */
7810+#define SK_SEN_IDLE 0 /* Idle: sensor not read */
7811+#define SK_SEN_VALUE 1 /* Value Read cycle */
7812+#define SK_SEN_VALEXT 2 /* Extended Value Read cycle */
7813+
7814+/*
7815+ * Conversion factor to convert read Voltage sensor to milli Volt
7816+ * Conversion factor to convert read Temperature sensor to 10th degree Celsius
7817+ */
7818+#define SK_LM80_VT_LSB 22 /* 22mV LSB resolution */
7819+#define SK_LM80_TEMP_LSB 10 /* 1 degree LSB resolution */
7820+#define SK_LM80_TEMPEXT_LSB 5 /* 0.5 degree LSB resolution for ext. val. */
7821+
7822+/*
7823+ * formula: counter = (22500*60)/(rpm * divisor * pulses/2)
7824+ * assuming: 6500rpm, 4 pulses, divisor 1
7825+ */
7826+#define SK_LM80_FAN_FAKTOR ((22500L*60)/(1*2))
7827+
7828+/*
7829+ * Define sensor management data
7830+ * Maximum is reached on Genesis copper dual port and Yukon-64
7831+ * Board specific maximum is in pAC->I2c.MaxSens
7832+ */
7833+#define SK_MAX_SENSORS 8 /* maximal no. of installed sensors */
7834+#define SK_MIN_SENSORS 5 /* minimal no. of installed sensors */
7835+
7836+/*
7837+ * To watch the state machine (SM) use the timer in two ways
7838+ * instead of one as hitherto
7839+ */
7840+#define SK_TIMER_WATCH_SM 0 /* Watch the SM to finish in a spec. time */
7841+#define SK_TIMER_NEW_GAUGING 1 /* Start a new gauging when timer expires */
7842+
7843+/*
7844+ * Defines for the individual thresholds
7845+ */
7846+
7847+#define C_PLUS_20 120 / 100
7848+#define C_PLUS_15 115 / 100
7849+#define C_PLUS_10 110 / 100
7850+#define C_PLUS_5 105 / 100
7851+#define C_MINUS_5 95 / 100
7852+#define C_MINUS_10 90 / 100
7853+#define C_MINUS_15 85 / 100
7854+
7855+/* Temperature sensor */
7856+#define SK_SEN_TEMP_HIGH_ERR 800 /* Temperature High Err Threshold */
7857+#define SK_SEN_TEMP_HIGH_WARN 700 /* Temperature High Warn Threshold */
7858+#define SK_SEN_TEMP_LOW_WARN 100 /* Temperature Low Warn Threshold */
7859+#define SK_SEN_TEMP_LOW_ERR 0 /* Temperature Low Err Threshold */
7860+
7861+/* VCC which should be 5 V */
7862+#define SK_SEN_PCI_5V_HIGH_ERR 5588 /* Voltage PCI High Err Threshold */
7863+#define SK_SEN_PCI_5V_HIGH_WARN 5346 /* Voltage PCI High Warn Threshold */
7864+#define SK_SEN_PCI_5V_LOW_WARN 4664 /* Voltage PCI Low Warn Threshold */
7865+#define SK_SEN_PCI_5V_LOW_ERR 4422 /* Voltage PCI Low Err Threshold */
7866+
7867+/*
7868+ * VIO may be 5 V or 3.3 V. Initialization takes two parts:
7869+ * 1. Initialize lowest lower limit and highest higher limit.
7870+ * 2. After the first value is read correct the upper or the lower limit to
7871+ * the appropriate C constant.
7872+ *
7873+ * Warning limits are +-5% of the exepected voltage.
7874+ * Error limits are +-10% of the expected voltage.
7875+ */
7876+
7877+/* Bug fix AF: 16.Aug.2001: Correct the init base of LM80 sensor */
7878+
7879+#define SK_SEN_PCI_IO_5V_HIGH_ERR 5566 /* + 10% V PCI-IO High Err Threshold */
7880+#define SK_SEN_PCI_IO_5V_HIGH_WARN 5324 /* + 5% V PCI-IO High Warn Threshold */
7881+ /* 5000 mVolt */
7882+#define SK_SEN_PCI_IO_5V_LOW_WARN 4686 /* - 5% V PCI-IO Low Warn Threshold */
7883+#define SK_SEN_PCI_IO_5V_LOW_ERR 4444 /* - 10% V PCI-IO Low Err Threshold */
7884+
7885+#define SK_SEN_PCI_IO_RANGE_LIMITER 4000 /* 4000 mV range delimiter */
7886+
7887+/* correction values for the second pass */
7888+#define SK_SEN_PCI_IO_3V3_HIGH_ERR 3850 /* + 15% V PCI-IO High Err Threshold */
7889+#define SK_SEN_PCI_IO_3V3_HIGH_WARN 3674 /* + 10% V PCI-IO High Warn Threshold */
7890+ /* 3300 mVolt */
7891+#define SK_SEN_PCI_IO_3V3_LOW_WARN 2926 /* - 10% V PCI-IO Low Warn Threshold */
7892+#define SK_SEN_PCI_IO_3V3_LOW_ERR 2772 /* - 15% V PCI-IO Low Err Threshold */
7893+
7894+/*
7895+ * VDD voltage
7896+ */
7897+#define SK_SEN_VDD_HIGH_ERR 3630 /* Voltage ASIC High Err Threshold */
7898+#define SK_SEN_VDD_HIGH_WARN 3476 /* Voltage ASIC High Warn Threshold */
7899+#define SK_SEN_VDD_LOW_WARN 3146 /* Voltage ASIC Low Warn Threshold */
7900+#define SK_SEN_VDD_LOW_ERR 2970 /* Voltage ASIC Low Err Threshold */
7901+
7902+/*
7903+ * PHY PLL 3V3 voltage
7904+ */
7905+#define SK_SEN_PLL_3V3_HIGH_ERR 3630 /* Voltage PMA High Err Threshold */
7906+#define SK_SEN_PLL_3V3_HIGH_WARN 3476 /* Voltage PMA High Warn Threshold */
7907+#define SK_SEN_PLL_3V3_LOW_WARN 3146 /* Voltage PMA Low Warn Threshold */
7908+#define SK_SEN_PLL_3V3_LOW_ERR 2970 /* Voltage PMA Low Err Threshold */
7909+
7910+/*
7911+ * VAUX (YUKON only)
7912+ */
7913+#define SK_SEN_VAUX_3V3_VAL 3300 /* Voltage VAUX 3.3 Volt */
7914+
7915+#define SK_SEN_VAUX_3V3_HIGH_ERR (SK_I32)(SK_SEN_VAUX_3V3_VAL * C_PLUS_10)
7916+#define SK_SEN_VAUX_3V3_HIGH_WARN (SK_I32)(SK_SEN_VAUX_3V3_VAL * C_PLUS_5)
7917+#define SK_SEN_VAUX_3V3_LOW_WARN (SK_I32)(SK_SEN_VAUX_3V3_VAL * C_MINUS_5)
7918+#define SK_SEN_VAUX_3V3_LOW_ERR (SK_I32)(SK_SEN_VAUX_3V3_VAL * C_MINUS_10)
7919+
7920+#define SK_SEN_VAUX_RANGE_LIMITER 1000 /* 1000 mV range delimiter */
7921+
7922+/*
7923+ * PHY 2V5 voltage
7924+ */
7925+#define SK_SEN_PHY_2V5_VAL 2500 /* Voltage PHY 2.5 Volt */
7926+
7927+#define SK_SEN_PHY_2V5_HIGH_ERR (SK_I32)(SK_SEN_PHY_2V5_VAL * C_PLUS_10)
7928+#define SK_SEN_PHY_2V5_HIGH_WARN (SK_I32)(SK_SEN_PHY_2V5_VAL * C_PLUS_5)
7929+#define SK_SEN_PHY_2V5_LOW_WARN (SK_I32)(SK_SEN_PHY_2V5_VAL * C_MINUS_5)
7930+#define SK_SEN_PHY_2V5_LOW_ERR (SK_I32)(SK_SEN_PHY_2V5_VAL * C_MINUS_10)
7931+
7932+/*
7933+ * ASIC Core 1V5 voltage (YUKON only)
7934+ */
7935+#define SK_SEN_CORE_1V5_VAL 1500 /* Voltage ASIC Core 1.5 Volt */
7936+
7937+#define SK_SEN_CORE_1V5_HIGH_ERR (SK_I32)(SK_SEN_CORE_1V5_VAL * C_PLUS_10)
7938+#define SK_SEN_CORE_1V5_HIGH_WARN (SK_I32)(SK_SEN_CORE_1V5_VAL * C_PLUS_5)
7939+#define SK_SEN_CORE_1V5_LOW_WARN (SK_I32)(SK_SEN_CORE_1V5_VAL * C_MINUS_5)
7940+#define SK_SEN_CORE_1V5_LOW_ERR (SK_I32)(SK_SEN_CORE_1V5_VAL * C_MINUS_10)
7941+
7942+/*
7943+ * ASIC Core 1V2 (1V3) voltage (YUKON-2 only)
7944+ */
7945+#define SK_SEN_CORE_1V2_VAL 1200 /* Voltage ASIC Core 1.2 Volt */
7946+
7947+#define SK_SEN_CORE_1V2_HIGH_ERR (SK_I32)(SK_SEN_CORE_1V2_VAL * C_PLUS_20)
7948+#define SK_SEN_CORE_1V2_HIGH_WARN (SK_I32)(SK_SEN_CORE_1V2_VAL * C_PLUS_15)
7949+#define SK_SEN_CORE_1V2_LOW_WARN (SK_I32)(SK_SEN_CORE_1V2_VAL * C_MINUS_5)
7950+#define SK_SEN_CORE_1V2_LOW_ERR (SK_I32)(SK_SEN_CORE_1V2_VAL * C_MINUS_10)
7951+
7952+#define SK_SEN_CORE_1V3_VAL 1300 /* Voltage ASIC Core 1.3 Volt */
7953+
7954+#define SK_SEN_CORE_1V3_HIGH_ERR (SK_I32)(SK_SEN_CORE_1V3_VAL * C_PLUS_15)
7955+#define SK_SEN_CORE_1V3_HIGH_WARN (SK_I32)(SK_SEN_CORE_1V3_VAL * C_PLUS_10)
7956+#define SK_SEN_CORE_1V3_LOW_WARN (SK_I32)(SK_SEN_CORE_1V3_VAL * C_MINUS_5)
7957+#define SK_SEN_CORE_1V3_LOW_ERR (SK_I32)(SK_SEN_CORE_1V3_VAL * C_MINUS_10)
7958+
7959+/*
7960+ * FAN 1 speed
7961+ */
7962+/* assuming: 6500rpm +-15%, 4 pulses,
7963+ * warning at: 80 %
7964+ * error at: 70 %
7965+ * no upper limit
7966+ */
7967+#define SK_SEN_FAN_HIGH_ERR 20000 /* FAN Speed High Err Threshold */
7968+#define SK_SEN_FAN_HIGH_WARN 20000 /* FAN Speed High Warn Threshold */
7969+#define SK_SEN_FAN_LOW_WARN 5200 /* FAN Speed Low Warn Threshold */
7970+#define SK_SEN_FAN_LOW_ERR 4550 /* FAN Speed Low Err Threshold */
7971+
7972+/*
7973+ * Some Voltages need dynamic thresholds
7974+ */
7975+#define SK_SEN_DYN_INIT_NONE 0 /* No dynamic init of thresholds */
7976+#define SK_SEN_DYN_INIT_PCI_IO 10 /* Init PCI-IO with new thresholds */
7977+#define SK_SEN_DYN_INIT_VAUX 11 /* Init VAUX with new thresholds */
7978+
7979+extern int SkLm80ReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen);
7980+#endif /* n_INC_SKGETWSI_H */
7981+
7982diff -ruN linux/drivers/net/sk98lin/h/ski2c.h linux-new/drivers/net/sk98lin/h/ski2c.h
7983--- linux/drivers/net/sk98lin/h/ski2c.h 2006-04-11 19:19:28.000000000 +0200
7984+++ linux-new/drivers/net/sk98lin/h/ski2c.h 1970-01-01 01:00:00.000000000 +0100
7985@@ -1,177 +0,0 @@
7986-/******************************************************************************
7987- *
7988- * Name: ski2c.h
7989- * Project: Gigabit Ethernet Adapters, TWSI-Module
7990- * Version: $Revision$
7991- * Date: $Date$
7992- * Purpose: Defines to access Voltage and Temperature Sensor
7993- *
7994- ******************************************************************************/
7995-
7996-/******************************************************************************
7997- *
7998- * (C)Copyright 1998-2002 SysKonnect.
7999- * (C)Copyright 2002-2003 Marvell.
8000- *
8001- * This program is free software; you can redistribute it and/or modify
8002- * it under the terms of the GNU General Public License as published by
8003- * the Free Software Foundation; either version 2 of the License, or
8004- * (at your option) any later version.
8005- *
8006- * The information in this file is provided "AS IS" without warranty.
8007- *
8008- ******************************************************************************/
8009-
8010-/*
8011- * SKI2C.H contains all I2C specific defines
8012- */
8013-
8014-#ifndef _SKI2C_H_
8015-#define _SKI2C_H_
8016-
8017-typedef struct s_Sensor SK_SENSOR;
8018-
8019-#include "h/skgei2c.h"
8020-
8021-/*
8022- * Define the I2C events.
8023- */
8024-#define SK_I2CEV_IRQ 1 /* IRQ happened Event */
8025-#define SK_I2CEV_TIM 2 /* Timeout event */
8026-#define SK_I2CEV_CLEAR 3 /* Clear MIB Values */
8027-
8028-/*
8029- * Define READ and WRITE Constants.
8030- */
8031-#define I2C_READ 0
8032-#define I2C_WRITE 1
8033-#define I2C_BURST 1
8034-#define I2C_SINGLE 0
8035-
8036-#define SKERR_I2C_E001 (SK_ERRBASE_I2C+0)
8037-#define SKERR_I2C_E001MSG "Sensor index unknown"
8038-#define SKERR_I2C_E002 (SKERR_I2C_E001+1)
8039-#define SKERR_I2C_E002MSG "TWSI: transfer does not complete"
8040-#define SKERR_I2C_E003 (SKERR_I2C_E002+1)
8041-#define SKERR_I2C_E003MSG "LM80: NAK on device send"
8042-#define SKERR_I2C_E004 (SKERR_I2C_E003+1)
8043-#define SKERR_I2C_E004MSG "LM80: NAK on register send"
8044-#define SKERR_I2C_E005 (SKERR_I2C_E004+1)
8045-#define SKERR_I2C_E005MSG "LM80: NAK on device (2) send"
8046-#define SKERR_I2C_E006 (SKERR_I2C_E005+1)
8047-#define SKERR_I2C_E006MSG "Unknown event"
8048-#define SKERR_I2C_E007 (SKERR_I2C_E006+1)
8049-#define SKERR_I2C_E007MSG "LM80 read out of state"
8050-#define SKERR_I2C_E008 (SKERR_I2C_E007+1)
8051-#define SKERR_I2C_E008MSG "Unexpected sensor read completed"
8052-#define SKERR_I2C_E009 (SKERR_I2C_E008+1)
8053-#define SKERR_I2C_E009MSG "WARNING: temperature sensor out of range"
8054-#define SKERR_I2C_E010 (SKERR_I2C_E009+1)
8055-#define SKERR_I2C_E010MSG "WARNING: voltage sensor out of range"
8056-#define SKERR_I2C_E011 (SKERR_I2C_E010+1)
8057-#define SKERR_I2C_E011MSG "ERROR: temperature sensor out of range"
8058-#define SKERR_I2C_E012 (SKERR_I2C_E011+1)
8059-#define SKERR_I2C_E012MSG "ERROR: voltage sensor out of range"
8060-#define SKERR_I2C_E013 (SKERR_I2C_E012+1)
8061-#define SKERR_I2C_E013MSG "ERROR: couldn't init sensor"
8062-#define SKERR_I2C_E014 (SKERR_I2C_E013+1)
8063-#define SKERR_I2C_E014MSG "WARNING: fan sensor out of range"
8064-#define SKERR_I2C_E015 (SKERR_I2C_E014+1)
8065-#define SKERR_I2C_E015MSG "ERROR: fan sensor out of range"
8066-#define SKERR_I2C_E016 (SKERR_I2C_E015+1)
8067-#define SKERR_I2C_E016MSG "TWSI: active transfer does not complete"
8068-
8069-/*
8070- * Define Timeout values
8071- */
8072-#define SK_I2C_TIM_LONG 2000000L /* 2 seconds */
8073-#define SK_I2C_TIM_SHORT 100000L /* 100 milliseconds */
8074-#define SK_I2C_TIM_WATCH 1000000L /* 1 second */
8075-
8076-/*
8077- * Define trap and error log hold times
8078- */
8079-#ifndef SK_SEN_ERR_TR_HOLD
8080-#define SK_SEN_ERR_TR_HOLD (4*SK_TICKS_PER_SEC)
8081-#endif
8082-#ifndef SK_SEN_ERR_LOG_HOLD
8083-#define SK_SEN_ERR_LOG_HOLD (60*SK_TICKS_PER_SEC)
8084-#endif
8085-#ifndef SK_SEN_WARN_TR_HOLD
8086-#define SK_SEN_WARN_TR_HOLD (15*SK_TICKS_PER_SEC)
8087-#endif
8088-#ifndef SK_SEN_WARN_LOG_HOLD
8089-#define SK_SEN_WARN_LOG_HOLD (15*60*SK_TICKS_PER_SEC)
8090-#endif
8091-
8092-/*
8093- * Defines for SenType
8094- */
8095-#define SK_SEN_UNKNOWN 0
8096-#define SK_SEN_TEMP 1
8097-#define SK_SEN_VOLT 2
8098-#define SK_SEN_FAN 3
8099-
8100-/*
8101- * Define for the SenErrorFlag
8102- */
8103-#define SK_SEN_ERR_NOT_PRESENT 0 /* Error Flag: Sensor not present */
8104-#define SK_SEN_ERR_OK 1 /* Error Flag: O.K. */
8105-#define SK_SEN_ERR_WARN 2 /* Error Flag: Warning */
8106-#define SK_SEN_ERR_ERR 3 /* Error Flag: Error */
8107-#define SK_SEN_ERR_FAULTY 4 /* Error Flag: Faulty */
8108-
8109-/*
8110- * Define the Sensor struct
8111- */
8112-struct s_Sensor {
8113- char *SenDesc; /* Description */
8114- int SenType; /* Voltage or Temperature */
8115- SK_I32 SenValue; /* Current value of the sensor */
8116- SK_I32 SenThreErrHigh; /* High error Threshhold of this sensor */
8117- SK_I32 SenThreWarnHigh; /* High warning Threshhold of this sensor */
8118- SK_I32 SenThreErrLow; /* Lower error Threshold of the sensor */
8119- SK_I32 SenThreWarnLow; /* Lower warning Threshold of the sensor */
8120- int SenErrFlag; /* Sensor indicated an error */
8121- SK_BOOL SenInit; /* Is sensor initialized ? */
8122- SK_U64 SenErrCts; /* Error trap counter */
8123- SK_U64 SenWarnCts; /* Warning trap counter */
8124- SK_U64 SenBegErrTS; /* Begin error timestamp */
8125- SK_U64 SenBegWarnTS; /* Begin warning timestamp */
8126- SK_U64 SenLastErrTrapTS; /* Last error trap timestamp */
8127- SK_U64 SenLastErrLogTS; /* Last error log timestamp */
8128- SK_U64 SenLastWarnTrapTS; /* Last warning trap timestamp */
8129- SK_U64 SenLastWarnLogTS; /* Last warning log timestamp */
8130- int SenState; /* Sensor State (see HW specific include) */
8131- int (*SenRead)(SK_AC *pAC, SK_IOC IoC, struct s_Sensor *pSen);
8132- /* Sensors read function */
8133- SK_U16 SenReg; /* Register Address for this sensor */
8134- SK_U8 SenDev; /* Device Selection for this sensor */
8135-};
8136-
8137-typedef struct s_I2c {
8138- SK_SENSOR SenTable[SK_MAX_SENSORS]; /* Sensor Table */
8139- int CurrSens; /* Which sensor is currently queried */
8140- int MaxSens; /* Max. number of sensors */
8141- int TimerMode; /* Use the timer also to watch the state machine */
8142- int InitLevel; /* Initialized Level */
8143-#ifndef SK_DIAG
8144- int DummyReads; /* Number of non-checked dummy reads */
8145- SK_TIMER SenTimer; /* Sensors timer */
8146-#endif /* !SK_DIAG */
8147-} SK_I2C;
8148-
8149-extern int SkI2cInit(SK_AC *pAC, SK_IOC IoC, int Level);
8150-extern int SkI2cWrite(SK_AC *pAC, SK_IOC IoC, SK_U32 Data, int Dev, int Size,
8151- int Reg, int Burst);
8152-extern int SkI2cReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen);
8153-#ifdef SK_DIAG
8154-extern SK_U32 SkI2cRead(SK_AC *pAC, SK_IOC IoC, int Dev, int Size, int Reg,
8155- int Burst);
8156-#else /* !SK_DIAG */
8157-extern int SkI2cEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Para);
8158-extern void SkI2cWaitIrq(SK_AC *pAC, SK_IOC IoC);
8159-extern void SkI2cIsr(SK_AC *pAC, SK_IOC IoC);
8160-#endif /* !SK_DIAG */
8161-#endif /* n_SKI2C_H */
8162-
8163diff -ruN linux/drivers/net/sk98lin/h/skqueue.h linux-new/drivers/net/sk98lin/h/skqueue.h
8164--- linux/drivers/net/sk98lin/h/skqueue.h 2006-04-11 19:19:28.000000000 +0200
8165+++ linux-new/drivers/net/sk98lin/h/skqueue.h 2006-01-18 14:37:24.000000000 +0100
8166@@ -2,8 +2,8 @@
8167 *
8168 * Name: skqueue.h
8169 * Project: Gigabit Ethernet Adapters, Event Scheduler Module
8170- * Version: $Revision$
8171- * Date: $Date$
8172+ * Version: $Revision$
8173+ * Date: $Date$
8174 * Purpose: Defines for the Event queue
8175 *
8176 ******************************************************************************/
8177@@ -45,6 +45,9 @@
8178 #define SKGE_RSF 11 /* RSF Aggregation Event Class */
8179 #define SKGE_MARKER 12 /* MARKER Aggregation Event Class */
8180 #define SKGE_FD 13 /* FD Distributor Event Class */
8181+#ifdef SK_ASF
8182+#define SKGE_ASF 14 /* ASF Event Class */
8183+#endif
8184
8185 /*
8186 * define event queue as circular buffer
8187@@ -90,5 +93,11 @@
8188 #define SKERR_Q_E001MSG "Event queue overflow"
8189 #define SKERR_Q_E002 (SKERR_Q_E001+1)
8190 #define SKERR_Q_E002MSG "Undefined event class"
8191+#define SKERR_Q_E003 (SKERR_Q_E001+2)
8192+#define SKERR_Q_E003MSG "Event queued in Init Level 0"
8193+#define SKERR_Q_E004 (SKERR_Q_E001+3)
8194+#define SKERR_Q_E004MSG "Error Reported from Event Fuction (Queue Blocked)"
8195+#define SKERR_Q_E005 (SKERR_Q_E001+4)
8196+#define SKERR_Q_E005MSG "Event scheduler called in Init Level 0 or 1"
8197 #endif /* _SKQUEUE_H_ */
8198
8199diff -ruN linux/drivers/net/sk98lin/h/skrlmt.h linux-new/drivers/net/sk98lin/h/skrlmt.h
8200--- linux/drivers/net/sk98lin/h/skrlmt.h 2006-04-11 19:19:28.000000000 +0200
8201+++ linux-new/drivers/net/sk98lin/h/skrlmt.h 2006-01-18 14:37:24.000000000 +0100
8202@@ -2,8 +2,8 @@
8203 *
8204 * Name: skrlmt.h
8205 * Project: GEnesis, PCI Gigabit Ethernet Adapter
8206- * Version: $Revision$
8207- * Date: $Date$
8208+ * Version: $Revision$
8209+ * Date: $Date$
8210 * Purpose: Header file for Redundant Link ManagemenT.
8211 *
8212 ******************************************************************************/
8213diff -ruN linux/drivers/net/sk98lin/h/sktimer.h linux-new/drivers/net/sk98lin/h/sktimer.h
8214--- linux/drivers/net/sk98lin/h/sktimer.h 2006-04-11 19:19:28.000000000 +0200
8215+++ linux-new/drivers/net/sk98lin/h/sktimer.h 2006-01-18 14:37:24.000000000 +0100
8216@@ -2,8 +2,8 @@
8217 *
8218 * Name: sktimer.h
8219 * Project: Gigabit Ethernet Adapters, Event Scheduler Module
8220- * Version: $Revision$
8221- * Date: $Date$
8222+ * Version: $Revision$
8223+ * Date: $Date$
8224 * Purpose: Defines for the timer functions
8225 *
8226 ******************************************************************************/
8227diff -ruN linux/drivers/net/sk98lin/h/sktwsi.h linux-new/drivers/net/sk98lin/h/sktwsi.h
8228--- linux/drivers/net/sk98lin/h/sktwsi.h 1970-01-01 01:00:00.000000000 +0100
8229+++ linux-new/drivers/net/sk98lin/h/sktwsi.h 2006-01-18 14:37:24.000000000 +0100
8230@@ -0,0 +1,177 @@
8231+/******************************************************************************
8232+ *
8233+ * Name: sktwsi.h
8234+ * Project: Gigabit Ethernet Adapters, TWSI-Module
8235+ * Version: $Revision$
8236+ * Date: $Date$
8237+ * Purpose: Defines to access Voltage and Temperature Sensor
8238+ *
8239+ ******************************************************************************/
8240+
8241+/******************************************************************************
8242+ *
8243+ * (C)Copyright 1998-2002 SysKonnect.
8244+ * (C)Copyright 2002-2003 Marvell.
8245+ *
8246+ * This program is free software; you can redistribute it and/or modify
8247+ * it under the terms of the GNU General Public License as published by
8248+ * the Free Software Foundation; either version 2 of the License, or
8249+ * (at your option) any later version.
8250+ *
8251+ * The information in this file is provided "AS IS" without warranty.
8252+ *
8253+ ******************************************************************************/
8254+
8255+/*
8256+ * SKTWSI.H contains all TWSI specific defines
8257+ */
8258+
8259+#ifndef _SKTWSI_H_
8260+#define _SKTWSI_H_
8261+
8262+typedef struct s_Sensor SK_SENSOR;
8263+
8264+#include "h/skgetwsi.h"
8265+
8266+/*
8267+ * Define the TWSI events.
8268+ */
8269+#define SK_I2CEV_IRQ 1 /* IRQ happened Event */
8270+#define SK_I2CEV_TIM 2 /* Timeout event */
8271+#define SK_I2CEV_CLEAR 3 /* Clear MIB Values */
8272+
8273+/*
8274+ * Define READ and WRITE Constants.
8275+ */
8276+#define I2C_READ 0
8277+#define I2C_WRITE 1
8278+#define I2C_BURST 1
8279+#define I2C_SINGLE 0
8280+
8281+#define SKERR_I2C_E001 (SK_ERRBASE_I2C+0)
8282+#define SKERR_I2C_E001MSG "Sensor index unknown"
8283+#define SKERR_I2C_E002 (SKERR_I2C_E001+1)
8284+#define SKERR_I2C_E002MSG "TWSI: transfer does not complete"
8285+#define SKERR_I2C_E003 (SKERR_I2C_E002+1)
8286+#define SKERR_I2C_E003MSG "LM80: NAK on device send"
8287+#define SKERR_I2C_E004 (SKERR_I2C_E003+1)
8288+#define SKERR_I2C_E004MSG "LM80: NAK on register send"
8289+#define SKERR_I2C_E005 (SKERR_I2C_E004+1)
8290+#define SKERR_I2C_E005MSG "LM80: NAK on device (2) send"
8291+#define SKERR_I2C_E006 (SKERR_I2C_E005+1)
8292+#define SKERR_I2C_E006MSG "Unknown event"
8293+#define SKERR_I2C_E007 (SKERR_I2C_E006+1)
8294+#define SKERR_I2C_E007MSG "LM80 read out of state"
8295+#define SKERR_I2C_E008 (SKERR_I2C_E007+1)
8296+#define SKERR_I2C_E008MSG "Unexpected sensor read completed"
8297+#define SKERR_I2C_E009 (SKERR_I2C_E008+1)
8298+#define SKERR_I2C_E009MSG "WARNING: temperature sensor out of range"
8299+#define SKERR_I2C_E010 (SKERR_I2C_E009+1)
8300+#define SKERR_I2C_E010MSG "WARNING: voltage sensor out of range"
8301+#define SKERR_I2C_E011 (SKERR_I2C_E010+1)
8302+#define SKERR_I2C_E011MSG "ERROR: temperature sensor out of range"
8303+#define SKERR_I2C_E012 (SKERR_I2C_E011+1)
8304+#define SKERR_I2C_E012MSG "ERROR: voltage sensor out of range"
8305+#define SKERR_I2C_E013 (SKERR_I2C_E012+1)
8306+#define SKERR_I2C_E013MSG "ERROR: couldn't init sensor"
8307+#define SKERR_I2C_E014 (SKERR_I2C_E013+1)
8308+#define SKERR_I2C_E014MSG "WARNING: fan sensor out of range"
8309+#define SKERR_I2C_E015 (SKERR_I2C_E014+1)
8310+#define SKERR_I2C_E015MSG "ERROR: fan sensor out of range"
8311+#define SKERR_I2C_E016 (SKERR_I2C_E015+1)
8312+#define SKERR_I2C_E016MSG "TWSI: active transfer does not complete"
8313+
8314+/*
8315+ * Define Timeout values
8316+ */
8317+#define SK_I2C_TIM_LONG 2000000L /* 2 seconds */
8318+#define SK_I2C_TIM_SHORT 100000L /* 100 milliseconds */
8319+#define SK_I2C_TIM_WATCH 1000000L /* 1 second */
8320+
8321+/*
8322+ * Define trap and error log hold times
8323+ */
8324+#ifndef SK_SEN_ERR_TR_HOLD
8325+#define SK_SEN_ERR_TR_HOLD (4*SK_TICKS_PER_SEC)
8326+#endif
8327+#ifndef SK_SEN_ERR_LOG_HOLD
8328+#define SK_SEN_ERR_LOG_HOLD (60*SK_TICKS_PER_SEC)
8329+#endif
8330+#ifndef SK_SEN_WARN_TR_HOLD
8331+#define SK_SEN_WARN_TR_HOLD (15*SK_TICKS_PER_SEC)
8332+#endif
8333+#ifndef SK_SEN_WARN_LOG_HOLD
8334+#define SK_SEN_WARN_LOG_HOLD (15*60*SK_TICKS_PER_SEC)
8335+#endif
8336+
8337+/*
8338+ * Defines for SenType
8339+ */
8340+#define SK_SEN_UNKNOWN 0
8341+#define SK_SEN_TEMP 1
8342+#define SK_SEN_VOLT 2
8343+#define SK_SEN_FAN 3
8344+
8345+/*
8346+ * Define for the SenErrorFlag
8347+ */
8348+#define SK_SEN_ERR_NOT_PRESENT 0 /* Error Flag: Sensor not present */
8349+#define SK_SEN_ERR_OK 1 /* Error Flag: O.K. */
8350+#define SK_SEN_ERR_WARN 2 /* Error Flag: Warning */
8351+#define SK_SEN_ERR_ERR 3 /* Error Flag: Error */
8352+#define SK_SEN_ERR_FAULTY 4 /* Error Flag: Faulty */
8353+
8354+/*
8355+ * Define the Sensor struct
8356+ */
8357+struct s_Sensor {
8358+ char *SenDesc; /* Description */
8359+ int SenType; /* Voltage or Temperature */
8360+ SK_I32 SenValue; /* Current value of the sensor */
8361+ SK_I32 SenThreErrHigh; /* High error Threshhold of this sensor */
8362+ SK_I32 SenThreWarnHigh; /* High warning Threshhold of this sensor */
8363+ SK_I32 SenThreErrLow; /* Lower error Threshold of the sensor */
8364+ SK_I32 SenThreWarnLow; /* Lower warning Threshold of the sensor */
8365+ int SenErrFlag; /* Sensor indicated an error */
8366+ SK_BOOL SenInit; /* Is sensor initialized ? */
8367+ SK_U64 SenErrCts; /* Error trap counter */
8368+ SK_U64 SenWarnCts; /* Warning trap counter */
8369+ SK_U64 SenBegErrTS; /* Begin error timestamp */
8370+ SK_U64 SenBegWarnTS; /* Begin warning timestamp */
8371+ SK_U64 SenLastErrTrapTS; /* Last error trap timestamp */
8372+ SK_U64 SenLastErrLogTS; /* Last error log timestamp */
8373+ SK_U64 SenLastWarnTrapTS; /* Last warning trap timestamp */
8374+ SK_U64 SenLastWarnLogTS; /* Last warning log timestamp */
8375+ int SenState; /* Sensor State (see HW specific include) */
8376+ int (*SenRead)(SK_AC *pAC, SK_IOC IoC, struct s_Sensor *pSen);
8377+ /* Sensors read function */
8378+ SK_U16 SenReg; /* Register Address for this sensor */
8379+ SK_U8 SenDev; /* Device Selection for this sensor */
8380+};
8381+
8382+typedef struct s_I2c {
8383+ SK_SENSOR SenTable[SK_MAX_SENSORS]; /* Sensor Table */
8384+ int CurrSens; /* Which sensor is currently queried */
8385+ int MaxSens; /* Max. number of sensors */
8386+ int TimerMode; /* Use the timer also to watch the state machine */
8387+ int InitLevel; /* Initialized Level */
8388+#ifndef SK_DIAG
8389+ int DummyReads; /* Number of non-checked dummy reads */
8390+ SK_TIMER SenTimer; /* Sensors timer */
8391+#endif /* !SK_DIAG */
8392+} SK_I2C;
8393+
8394+extern int SkI2cInit(SK_AC *pAC, SK_IOC IoC, int Level);
8395+extern int SkI2cWrite(SK_AC *pAC, SK_IOC IoC, SK_U32 Data, int Dev, int Size,
8396+ int Reg, int Burst);
8397+extern int SkI2cReadSensor(SK_AC *pAC, SK_IOC IoC, SK_SENSOR *pSen);
8398+#ifdef SK_DIAG
8399+extern SK_U32 SkI2cRead(SK_AC *pAC, SK_IOC IoC, int Dev, int Size, int Reg,
8400+ int Burst);
8401+#else /* !SK_DIAG */
8402+extern int SkI2cEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Para);
8403+extern void SkI2cWaitIrq(SK_AC *pAC, SK_IOC IoC);
8404+extern void SkI2cIsr(SK_AC *pAC, SK_IOC IoC);
8405+#endif /* !SK_DIAG */
8406+#endif /* n_SKTWSI_H */
8407+
8408diff -ruN linux/drivers/net/sk98lin/h/sktypes.h linux-new/drivers/net/sk98lin/h/sktypes.h
8409--- linux/drivers/net/sk98lin/h/sktypes.h 2006-04-11 19:19:28.000000000 +0200
8410+++ linux-new/drivers/net/sk98lin/h/sktypes.h 2006-01-18 14:37:24.000000000 +0100
8411@@ -2,8 +2,8 @@
8412 *
8413 * Name: sktypes.h
8414 * Project: GEnesis, PCI Gigabit Ethernet Adapter
8415- * Version: $Revision$
8416- * Date: $Date$
8417+ * Version: $Revision$
8418+ * Date: $Date$
8419 * Purpose: Define data types for Linux
8420 *
8421 ******************************************************************************/
8422@@ -11,7 +11,7 @@
8423 /******************************************************************************
8424 *
8425 * (C)Copyright 1998-2002 SysKonnect GmbH.
8426- * (C)Copyright 2002-2003 Marvell.
8427+ * (C)Copyright 2002-2005 Marvell.
8428 *
8429 * This program is free software; you can redistribute it and/or modify
8430 * it under the terms of the GNU General Public License as published by
8431@@ -22,48 +22,28 @@
8432 *
8433 ******************************************************************************/
8434
8435-/******************************************************************************
8436- *
8437- * Description:
8438- *
8439- * In this file, all data types that are needed by the common modules
8440- * are mapped to Linux data types.
8441- *
8442- *
8443- * Include File Hierarchy:
8444- *
8445- *
8446- ******************************************************************************/
8447-
8448 #ifndef __INC_SKTYPES_H
8449 #define __INC_SKTYPES_H
8450
8451-
8452-/* defines *******************************************************************/
8453-
8454-/*
8455- * Data types with a specific size. 'I' = signed, 'U' = unsigned.
8456- */
8457-#define SK_I8 s8
8458-#define SK_U8 u8
8459-#define SK_I16 s16
8460-#define SK_U16 u16
8461-#define SK_I32 s32
8462-#define SK_U32 u32
8463-#define SK_I64 s64
8464-#define SK_U64 u64
8465-
8466-#define SK_UPTR ulong /* casting pointer <-> integral */
8467-
8468-/*
8469-* Boolean type.
8470-*/
8471-#define SK_BOOL SK_U8
8472-#define SK_FALSE 0
8473-#define SK_TRUE (!SK_FALSE)
8474-
8475-/* typedefs *******************************************************************/
8476-
8477-/* function prototypes ********************************************************/
8478+#define SK_I8 s8 /* 8 bits (1 byte) signed */
8479+#define SK_U8 u8 /* 8 bits (1 byte) unsigned */
8480+#define SK_I16 s16 /* 16 bits (2 bytes) signed */
8481+#define SK_U16 u16 /* 16 bits (2 bytes) unsigned */
8482+#define SK_I32 s32 /* 32 bits (4 bytes) signed */
8483+#define SK_U32 u32 /* 32 bits (4 bytes) unsigned */
8484+#define SK_I64 s64 /* 64 bits (8 bytes) signed */
8485+#define SK_U64 u64 /* 64 bits (8 bytes) unsigned */
8486+
8487+#define SK_UPTR ulong /* casting pointer <-> integral */
8488+
8489+#define SK_BOOL SK_U8
8490+#define SK_FALSE 0
8491+#define SK_TRUE (!SK_FALSE)
8492
8493 #endif /* __INC_SKTYPES_H */
8494+
8495+/*******************************************************************************
8496+ *
8497+ * End of file
8498+ *
8499+ ******************************************************************************/
8500diff -ruN linux/drivers/net/sk98lin/h/skversion.h linux-new/drivers/net/sk98lin/h/skversion.h
8501--- linux/drivers/net/sk98lin/h/skversion.h 2006-04-11 19:19:28.000000000 +0200
8502+++ linux-new/drivers/net/sk98lin/h/skversion.h 2006-01-18 14:37:24.000000000 +0100
8503@@ -1,17 +1,17 @@
8504 /******************************************************************************
8505 *
8506- * Name: version.h
8507+ * Name: skversion.h
8508 * Project: GEnesis, PCI Gigabit Ethernet Adapter
8509- * Version: $Revision$
8510- * Date: $Date$
8511- * Purpose: SK specific Error log support
8512+ * Version: $Revision$
8513+ * Date: $Date$
8514+ * Purpose: specific version strings and numbers
8515 *
8516 ******************************************************************************/
8517
8518 /******************************************************************************
8519 *
8520 * (C)Copyright 1998-2002 SysKonnect GmbH.
8521- * (C)Copyright 2002-2003 Marvell.
8522+ * (C)Copyright 2002-2005 Marvell.
8523 *
8524 * This program is free software; you can redistribute it and/or modify
8525 * it under the terms of the GNU General Public License as published by
8526@@ -22,17 +22,15 @@
8527 *
8528 ******************************************************************************/
8529
8530-#ifdef lint
8531-static const char SysKonnectFileId[] = "@(#) (C) SysKonnect GmbH.";
8532-static const char SysKonnectBuildNumber[] =
8533- "@(#)SK-BUILD: 6.23 PL: 01";
8534-#endif /* !defined(lint) */
8535-
8536-#define BOOT_STRING "sk98lin: Network Device Driver v6.23\n" \
8537- "(C)Copyright 1999-2004 Marvell(R)."
8538-
8539-#define VER_STRING "6.23"
8540-#define DRIVER_FILE_NAME "sk98lin"
8541-#define DRIVER_REL_DATE "Feb-13-2004"
8542-
8543+#define BOOT_STRING "sk98lin: Network Device Driver v8.31.2.3\n" \
8544+ "(C)Copyright 1999-2006 Marvell(R)."
8545+#define VER_STRING "8.31.2.3"
8546+#define PATCHLEVEL "02"
8547+#define DRIVER_FILE_NAME "sk98lin"
8548+#define DRIVER_REL_DATE "Jan-18-2006"
8549
8550+/*******************************************************************************
8551+ *
8552+ * End of file
8553+ *
8554+ ******************************************************************************/
8555diff -ruN linux/drivers/net/sk98lin/h/skvpd.h linux-new/drivers/net/sk98lin/h/skvpd.h
8556--- linux/drivers/net/sk98lin/h/skvpd.h 2006-04-11 19:19:28.000000000 +0200
8557+++ linux-new/drivers/net/sk98lin/h/skvpd.h 2006-01-18 14:37:24.000000000 +0100
8558@@ -1,22 +1,22 @@
8559 /******************************************************************************
8560 *
8561 * Name: skvpd.h
8562- * Project: GEnesis, PCI Gigabit Ethernet Adapter
8563- * Version: $Revision$
8564- * Date: $Date$
8565+ * Project: Gigabit Ethernet Adapters, VPD-Module
8566+ * Version: $Revision$
8567+ * Date: $Date$
8568 * Purpose: Defines and Macros for VPD handling
8569 *
8570 ******************************************************************************/
8571
8572 /******************************************************************************
8573 *
8574- * (C)Copyright 1998-2003 SysKonnect GmbH.
8575+ * (C)Copyright 1998-2002 SysKonnect.
8576+ * (C)Copyright 2002-2004 Marvell.
8577 *
8578 * This program is free software; you can redistribute it and/or modify
8579 * it under the terms of the GNU General Public License as published by
8580 * the Free Software Foundation; either version 2 of the License, or
8581 * (at your option) any later version.
8582- *
8583 * The information in this file is provided "AS IS" without warranty.
8584 *
8585 ******************************************************************************/
8586@@ -31,7 +31,7 @@
8587 /*
8588 * Define Resource Type Identifiers and VPD keywords
8589 */
8590-#define RES_ID 0x82 /* Resource Type ID String (Product Name) */
8591+#define RES_ID 0x82 /* Resource Type ID String (Product Name) */
8592 #define RES_VPD_R 0x90 /* start of VPD read only area */
8593 #define RES_VPD_W 0x91 /* start of VPD read/write area */
8594 #define RES_END 0x78 /* Resource Type End Tag */
8595@@ -40,14 +40,16 @@
8596 #define VPD_NAME "Name" /* Product Name, VPD name of RES_ID */
8597 #endif /* VPD_NAME */
8598 #define VPD_PN "PN" /* Adapter Part Number */
8599-#define VPD_EC "EC" /* Adapter Engineering Level */
8600+#define VPD_EC "EC" /* Adapter Engineering Level */
8601 #define VPD_MN "MN" /* Manufacture ID */
8602 #define VPD_SN "SN" /* Serial Number */
8603 #define VPD_CP "CP" /* Extended Capability */
8604 #define VPD_RV "RV" /* Checksum and Reserved */
8605-#define VPD_YA "YA" /* Asset Tag Identifier */
8606+#define VPD_YA "YA" /* Asset Tag Identifier */
8607 #define VPD_VL "VL" /* First Error Log Message (SK specific) */
8608 #define VPD_VF "VF" /* Second Error Log Message (SK specific) */
8609+#define VPD_VB "VB" /* Boot Agent ROM Configuration (SK specific) */
8610+#define VPD_VE "VE" /* EFI UNDI Configuration (SK specific) */
8611 #define VPD_RW "RW" /* Remaining Read / Write Area */
8612
8613 /* 'type' values for vpd_setup_para() */
8614@@ -55,7 +57,7 @@
8615 #define VPD_RW_KEY 2 /* RW keys are "Yx", "Vx", and "RW" */
8616
8617 /* 'op' values for vpd_setup_para() */
8618-#define ADD_KEY 1 /* add the key at the pos "RV" or "RW" */
8619+#define ADD_KEY 1 /* add the key at the pos "RV" or "RW" */
8620 #define OWR_KEY 2 /* overwrite key if already exists */
8621
8622 /*
8623@@ -64,18 +66,18 @@
8624
8625 #define VPD_DEV_ID_GENESIS 0x4300
8626
8627-#define VPD_SIZE_YUKON 256
8628-#define VPD_SIZE_GENESIS 512
8629-#define VPD_SIZE 512
8630+#define VPD_SIZE_YUKON 256
8631+#define VPD_SIZE_GENESIS 512
8632+#define VPD_SIZE 512
8633 #define VPD_READ 0x0000
8634 #define VPD_WRITE 0x8000
8635
8636 #define VPD_STOP(pAC,IoC) VPD_OUT16(pAC,IoC,PCI_VPD_ADR_REG,VPD_WRITE)
8637
8638-#define VPD_GET_RES_LEN(p) ((unsigned int) \
8639- (* (SK_U8 *)&(p)[1]) |\
8640- ((* (SK_U8 *)&(p)[2]) << 8))
8641-#define VPD_GET_VPD_LEN(p) ((unsigned int)(* (SK_U8 *)&(p)[2]))
8642+#define VPD_GET_RES_LEN(p) ((unsigned int)\
8643+ (*(SK_U8 *)&(p)[1]) |\
8644+ ((*(SK_U8 *)&(p)[2]) << 8))
8645+#define VPD_GET_VPD_LEN(p) ((unsigned int)(*(SK_U8 *)&(p)[2]))
8646 #define VPD_GET_VAL(p) ((char *)&(p)[3])
8647
8648 #define VPD_MAX_LEN 50
8649@@ -126,62 +128,70 @@
8650 /*
8651 * System specific VPD macros
8652 */
8653-#ifndef SKDIAG
8654+#ifndef SK_DIAG
8655 #ifndef VPD_DO_IO
8656 #define VPD_OUT8(pAC,IoC,Addr,Val) (void)SkPciWriteCfgByte(pAC,Addr,Val)
8657 #define VPD_OUT16(pAC,IoC,Addr,Val) (void)SkPciWriteCfgWord(pAC,Addr,Val)
8658+#define VPD_OUT32(pAC,IoC,Addr,Val) (void)SkPciWriteCfgDWord(pAC,Addr,Val)
8659 #define VPD_IN8(pAC,IoC,Addr,pVal) (void)SkPciReadCfgByte(pAC,Addr,pVal)
8660 #define VPD_IN16(pAC,IoC,Addr,pVal) (void)SkPciReadCfgWord(pAC,Addr,pVal)
8661 #define VPD_IN32(pAC,IoC,Addr,pVal) (void)SkPciReadCfgDWord(pAC,Addr,pVal)
8662 #else /* VPD_DO_IO */
8663-#define VPD_OUT8(pAC,IoC,Addr,Val) SK_OUT8(IoC,PCI_C(Addr),Val)
8664-#define VPD_OUT16(pAC,IoC,Addr,Val) SK_OUT16(IoC,PCI_C(Addr),Val)
8665-#define VPD_IN8(pAC,IoC,Addr,pVal) SK_IN8(IoC,PCI_C(Addr),pVal)
8666-#define VPD_IN16(pAC,IoC,Addr,pVal) SK_IN16(IoC,PCI_C(Addr),pVal)
8667-#define VPD_IN32(pAC,IoC,Addr,pVal) SK_IN32(IoC,PCI_C(Addr),pVal)
8668+#define VPD_OUT8(pAC,IoC,Addr,Val) SK_OUT8(IoC,PCI_C(pAC,Addr),Val)
8669+#define VPD_OUT16(pAC,IoC,Addr,Val) SK_OUT16(IoC,PCI_C(pAC,Addr),Val)
8670+#define VPD_OUT32(pAC,IoC,Addr,Val) SK_OUT32(IoC,PCI_C(pAC,Addr),Val)
8671+#define VPD_IN8(pAC,IoC,Addr,pVal) SK_IN8(IoC,PCI_C(pAC,Addr),pVal)
8672+#define VPD_IN16(pAC,IoC,Addr,pVal) SK_IN16(IoC,PCI_C(pAC,Addr),pVal)
8673+#define VPD_IN32(pAC,IoC,Addr,pVal) SK_IN32(IoC,PCI_C(pAC,Addr),pVal)
8674 #endif /* VPD_DO_IO */
8675-#else /* SKDIAG */
8676+#else /* SK_DIAG */
8677 #define VPD_OUT8(pAC,Ioc,Addr,Val) { \
8678 if ((pAC)->DgT.DgUseCfgCycle) \
8679 SkPciWriteCfgByte(pAC,Addr,Val); \
8680 else \
8681- SK_OUT8(pAC,PCI_C(Addr),Val); \
8682+ SK_OUT8(pAC,PCI_C(pAC,Addr),Val); \
8683 }
8684 #define VPD_OUT16(pAC,Ioc,Addr,Val) { \
8685 if ((pAC)->DgT.DgUseCfgCycle) \
8686 SkPciWriteCfgWord(pAC,Addr,Val); \
8687 else \
8688- SK_OUT16(pAC,PCI_C(Addr),Val); \
8689+ SK_OUT16(pAC,PCI_C(pAC,Addr),Val); \
8690+ }
8691+#define VPD_OUT32(pAC,Ioc,Addr,Val) { \
8692+ if ((pAC)->DgT.DgUseCfgCycle) \
8693+ SkPciWriteCfgDWord(pAC,Addr,Val); \
8694+ else \
8695+ SK_OUT32(pAC,PCI_C(pAC,Addr),Val); \
8696 }
8697 #define VPD_IN8(pAC,Ioc,Addr,pVal) { \
8698- if ((pAC)->DgT.DgUseCfgCycle) \
8699+ if ((pAC)->DgT.DgUseCfgCycle) \
8700 SkPciReadCfgByte(pAC,Addr,pVal); \
8701 else \
8702- SK_IN8(pAC,PCI_C(Addr),pVal); \
8703+ SK_IN8(pAC,PCI_C(pAC,Addr),pVal); \
8704 }
8705 #define VPD_IN16(pAC,Ioc,Addr,pVal) { \
8706- if ((pAC)->DgT.DgUseCfgCycle) \
8707+ if ((pAC)->DgT.DgUseCfgCycle) \
8708 SkPciReadCfgWord(pAC,Addr,pVal); \
8709 else \
8710- SK_IN16(pAC,PCI_C(Addr),pVal); \
8711+ SK_IN16(pAC,PCI_C(pAC,Addr),pVal); \
8712 }
8713 #define VPD_IN32(pAC,Ioc,Addr,pVal) { \
8714 if ((pAC)->DgT.DgUseCfgCycle) \
8715 SkPciReadCfgDWord(pAC,Addr,pVal); \
8716 else \
8717- SK_IN32(pAC,PCI_C(Addr),pVal); \
8718+ SK_IN32(pAC,PCI_C(pAC,Addr),pVal); \
8719 }
8720-#endif /* nSKDIAG */
8721+#endif /* SK_DIAG */
8722
8723 /* function prototypes ********************************************************/
8724
8725 #ifndef SK_KR_PROTO
8726-#ifdef SKDIAG
8727+#ifdef SK_DIAG
8728 extern SK_U32 VpdReadDWord(
8729 SK_AC *pAC,
8730 SK_IOC IoC,
8731 int addr);
8732-#endif /* SKDIAG */
8733+#endif /* SK_DIAG */
8734
8735 extern int VpdSetupPara(
8736 SK_AC *pAC,
8737@@ -232,7 +242,12 @@
8738 SK_IOC IoC,
8739 char *msg);
8740
8741-#ifdef SKDIAG
8742+int VpdInit(
8743+ SK_AC *pAC,
8744+ SK_IOC IoC);
8745+
8746+#if defined(SK_DIAG) || defined(SK_ASF)
8747+
8748 extern int VpdReadBlock(
8749 SK_AC *pAC,
8750 SK_IOC IoC,
8751@@ -246,7 +261,9 @@
8752 char *buf,
8753 int addr,
8754 int len);
8755-#endif /* SKDIAG */
8756+
8757+#endif /* SK_DIAG || SK_ASF */
8758+
8759 #else /* SK_KR_PROTO */
8760 extern SK_U32 VpdReadDWord();
8761 extern int VpdSetupPara();
8762@@ -261,3 +278,4 @@
8763 #endif /* SK_KR_PROTO */
8764
8765 #endif /* __INC_SKVPD_H_ */
8766+
8767diff -ruN linux/drivers/net/sk98lin/h/sky2le.h linux-new/drivers/net/sk98lin/h/sky2le.h
8768--- linux/drivers/net/sk98lin/h/sky2le.h 1970-01-01 01:00:00.000000000 +0100
8769+++ linux-new/drivers/net/sk98lin/h/sky2le.h 2006-01-18 14:37:24.000000000 +0100
8770@@ -0,0 +1,893 @@
8771+/******************************************************************************
8772+ *
8773+ * Name: sky2le.h
8774+ * Project: Gigabit Ethernet Adapters, Common Modules
8775+ * Version: $Revision$
8776+ * Date: $Date$
8777+ * Purpose: Common list element definitions and access macros.
8778+ *
8779+ ******************************************************************************/
8780+
8781+/******************************************************************************
8782+ *
8783+ * LICENSE:
8784+ * (C)Copyright 2003-2004 Marvell
8785+ *
8786+ * This program is free software; you can redistribute it and/or modify
8787+ * it under the terms of the GNU General Public License as published by
8788+ * the Free Software Foundation; either version 2 of the License, or
8789+ * (at your option) any later version.
8790+ * The information in this file is provided "AS IS" without warranty.
8791+ * /LICENSE
8792+ *
8793+ ******************************************************************************/
8794+
8795+#ifndef __INC_SKY2LE_H
8796+#define __INC_SKY2LE_H
8797+
8798+#ifdef __cplusplus
8799+extern "C" {
8800+#endif /* __cplusplus */
8801+
8802+/* defines ********************************************************************/
8803+
8804+#define MIN_LEN_OF_LE_TAB 128
8805+#define MAX_LEN_OF_LE_TAB 4096
8806+#ifdef USE_POLLING_UNIT
8807+#define NUM_LE_POLLING_UNIT 2
8808+#endif
8809+#define MAX_FRAG_OVERHEAD 10
8810+
8811+/* Macro for aligning a given value */
8812+#define SK_ALIGN_SIZE(Value, Alignment, AlignedVal) { \
8813+ (AlignedVal) = (((Value) + (Alignment) - 1) & (~((Alignment) - 1)));\
8814+}
8815+
8816+/******************************************************************************
8817+ *
8818+ * LE2DWord() - Converts the given Little Endian value to machine order value
8819+ *
8820+ * Description:
8821+ * This function converts the Little Endian value received as an argument to
8822+ * the machine order value.
8823+ *
8824+ * Returns:
8825+ * The converted value
8826+ *
8827+ */
8828+
8829+#ifdef SK_LITTLE_ENDIAN
8830+
8831+#ifndef SK_USE_REV_DESC
8832+#define LE2DWord(value) (value)
8833+#else /* SK_USE_REV_DESC */
8834+#define LE2DWord(value) \
8835+ ((((value)<<24L) & 0xff000000L) + \
8836+ (((value)<< 8L) & 0x00ff0000L) + \
8837+ (((value)>> 8L) & 0x0000ff00L) + \
8838+ (((value)>>24L) & 0x000000ffL))
8839+#endif /* SK_USE_REV_DESC */
8840+
8841+#else /* !SK_LITTLE_ENDIAN */
8842+
8843+#ifndef SK_USE_REV_DESC
8844+#define LE2DWord(value) \
8845+ ((((value)<<24L) & 0xff000000L) + \
8846+ (((value)<< 8L) & 0x00ff0000L) + \
8847+ (((value)>> 8L) & 0x0000ff00L) + \
8848+ (((value)>>24L) & 0x000000ffL))
8849+#else /* SK_USE_REV_DESC */
8850+#define LE2DWord(value) (value)
8851+#endif /* SK_USE_REV_DESC */
8852+
8853+#endif /* !SK_LITTLE_ENDIAN */
8854+
8855+/******************************************************************************
8856+ *
8857+ * DWord2LE() - Converts the given value to a Little Endian value
8858+ *
8859+ * Description:
8860+ * This function converts the value received as an argument to a Little Endian
8861+ * value on Big Endian machines. If the machine running the code is Little
8862+ * Endian, then no conversion is done.
8863+ *
8864+ * Returns:
8865+ * The converted value
8866+ *
8867+ */
8868+
8869+#ifdef SK_LITTLE_ENDIAN
8870+
8871+#ifndef SK_USE_REV_DESC
8872+#define DWord2LE(value) (value)
8873+#else /* SK_USE_REV_DESC */
8874+#define DWord2LE(value) \
8875+ ((((value)<<24L) & 0xff000000L) + \
8876+ (((value)<< 8L) & 0x00ff0000L) + \
8877+ (((value)>> 8L) & 0x0000ff00L) + \
8878+ (((value)>>24L) & 0x000000ffL))
8879+#endif /* SK_USE_REV_DESC */
8880+
8881+#else /* !SK_LITTLE_ENDIAN */
8882+
8883+#ifndef SK_USE_REV_DESC
8884+#define DWord2LE(value) \
8885+ ((((value)<<24L) & 0xff000000L) + \
8886+ (((value)<< 8L) & 0x00ff0000L) + \
8887+ (((value)>> 8L) & 0x0000ff00L) + \
8888+ (((value)>>24L) & 0x000000ffL))
8889+#else /* SK_USE_REV_DESC */
8890+#define DWord2LE(value) (value)
8891+#endif /* SK_USE_REV_DESC */
8892+#endif /* !SK_LITTLE_ENDIAN */
8893+
8894+/******************************************************************************
8895+ *
8896+ * LE2Word() - Converts the given Little Endian value to machine order value
8897+ *
8898+ * Description:
8899+ * This function converts the Little Endian value received as an argument to
8900+ * the machine order value.
8901+ *
8902+ * Returns:
8903+ * The converted value
8904+ *
8905+ */
8906+
8907+#ifdef SK_LITTLE_ENDIAN
8908+#ifndef SK_USE_REV_DESC
8909+#define LE2Word(value) (value)
8910+#else /* SK_USE_REV_DESC */
8911+#define LE2Word(value) \
8912+ ((((value)<< 8L) & 0xff00) + \
8913+ (((value)>> 8L) & 0x00ff))
8914+#endif /* SK_USE_REV_DESC */
8915+
8916+#else /* !SK_LITTLE_ENDIAN */
8917+#ifndef SK_USE_REV_DESC
8918+#define LE2Word(value) \
8919+ ((((value)<< 8L) & 0xff00) + \
8920+ (((value)>> 8L) & 0x00ff))
8921+#else /* SK_USE_REV_DESC */
8922+#define LE2Word(value) (value)
8923+#endif /* SK_USE_REV_DESC */
8924+#endif /* !SK_LITTLE_ENDIAN */
8925+
8926+/******************************************************************************
8927+ *
8928+ * Word2LE() - Converts the given value to a Little Endian value
8929+ *
8930+ * Description:
8931+ * This function converts the value received as an argument to a Little Endian
8932+ * value on Big Endian machines. If the machine running the code is Little
8933+ * Endian, then no conversion is done.
8934+ *
8935+ * Returns:
8936+ * The converted value
8937+ *
8938+ */
8939+
8940+#ifdef SK_LITTLE_ENDIAN
8941+#ifndef SK_USE_REV_DESC
8942+#define Word2LE(value) (value)
8943+#else /* SK_USE_REV_DESC */
8944+#define Word2LE(value) \
8945+ ((((value)<< 8L) & 0xff00) + \
8946+ (((value)>> 8L) & 0x00ff))
8947+#endif /* SK_USE_REV_DESC */
8948+
8949+#else /* !SK_LITTLE_ENDIAN */
8950+#ifndef SK_USE_REV_DESC
8951+#define Word2LE(value) \
8952+ ((((value)<< 8L) & 0xff00) + \
8953+ (((value)>> 8L) & 0x00ff))
8954+#else /* SK_USE_REV_DESC */
8955+#define Word2LE(value) (value)
8956+#endif /* SK_USE_REV_DESC */
8957+#endif /* !SK_LITTLE_ENDIAN */
8958+
8959+/******************************************************************************
8960+ *
8961+ * Transmit list element macros
8962+ *
8963+ */
8964+
8965+#define TXLE_SET_ADDR(pLE, Addr) \
8966+ ((pLE)->Tx.TxUn.BufAddr = DWord2LE(Addr))
8967+#define TXLE_SET_LSLEN(pLE, Len) \
8968+ ((pLE)->Tx.TxUn.LargeSend.Length = Word2LE(Len))
8969+#define TXLE_SET_STACS(pLE, Start) \
8970+ ((pLE)->Tx.TxUn.ChkSum.TxTcpSp = Word2LE(Start))
8971+#define TXLE_SET_WRICS(pLE, Write) \
8972+ ((pLE)->Tx.TxUn.ChkSum.TxTcpWp = Word2LE(Write))
8973+#define TXLE_SET_INICS(pLE, Ini) ((pLE)->Tx.Send.InitCsum = Word2LE(Ini))
8974+#define TXLE_SET_LEN(pLE, Len) ((pLE)->Tx.Send.BufLen = Word2LE(Len))
8975+#define TXLE_SET_VLAN(pLE, Vlan) ((pLE)->Tx.Send.VlanTag = Word2LE(Vlan))
8976+#define TXLE_SET_LCKCS(pLE, Lock) ((pLE)->Tx.ControlFlags = (Lock))
8977+#define TXLE_SET_CTRL(pLE, Ctrl) ((pLE)->Tx.ControlFlags = (Ctrl))
8978+#define TXLE_SET_OPC(pLE, Opc) ((pLE)->Tx.Opcode = (Opc))
8979+
8980+#define TXLE_GET_ADDR(pLE) LE2DWord((pLE)->Tx.TxUn.BufAddr)
8981+#define TXLE_GET_LSLEN(pLE) LE2Word((pLE)->Tx.TxUn.LargeSend.Length)
8982+#define TXLE_GET_STACS(pLE) LE2Word((pLE)->Tx.TxUn.ChkSum.TxTcpSp)
8983+#define TXLE_GET_WRICS(pLE) LE2Word((pLE)->Tx.TxUn.ChkSum.TxTcpWp)
8984+#define TXLE_GET_INICS(pLE) LE2Word((pLE)->Tx.Send.InitCsum)
8985+#define TXLE_GET_LEN(pLE) LE2Word((pLE)->Tx.Send.BufLen)
8986+#define TXLE_GET_VLAN(pLE) LE2Word((pLE)->Tx.Send.VlanTag)
8987+#define TXLE_GET_LCKCS(pLE) ((pLE)->Tx.ControlFlags)
8988+#define TXLE_GET_CTRL(pLE) ((pLE)->Tx.ControlFlags)
8989+#define TXLE_GET_OPC(pLE) ((pLE)->Tx.Opcode)
8990+
8991+/******************************************************************************
8992+ *
8993+ * Receive list element macros
8994+ *
8995+ */
8996+
8997+#define RXLE_SET_ADDR(pLE, Addr) \
8998+ ((pLE)->Rx.RxUn.BufAddr = (SK_U32) DWord2LE(Addr))
8999+#define RXLE_SET_STACS2(pLE, Offs) \
9000+ ((pLE)->Rx.RxUn.ChkSum.RxTcpSp2 = Word2LE(Offs))
9001+#define RXLE_SET_STACS1(pLE, Offs) \
9002+ ((pLE)->Rx.RxUn.ChkSum.RxTcpSp1 = Word2LE(Offs))
9003+#define RXLE_SET_LEN(pLE, Len) ((pLE)->Rx.BufferLength = Word2LE(Len))
9004+#define RXLE_SET_CTRL(pLE, Ctrl) ((pLE)->Rx.ControlFlags = (Ctrl))
9005+#define RXLE_SET_OPC(pLE, Opc) ((pLE)->Rx.Opcode = (Opc))
9006+
9007+#define RXLE_GET_ADDR(pLE) LE2DWord((pLE)->Rx.RxUn.BufAddr)
9008+#define RXLE_GET_STACS2(pLE) LE2Word((pLE)->Rx.RxUn.ChkSum.RxTcpSp2)
9009+#define RXLE_GET_STACS1(pLE) LE2Word((pLE)->Rx.RxUn.ChkSum.RxTcpSp1)
9010+#define RXLE_GET_LEN(pLE) LE2Word((pLE)->Rx.BufferLength)
9011+#define RXLE_GET_CTRL(pLE) ((pLE)->Rx.ControlFlags)
9012+#define RXLE_GET_OPC(pLE) ((pLE)->Rx.Opcode)
9013+
9014+/******************************************************************************
9015+ *
9016+ * Status list element macros
9017+ *
9018+ */
9019+
9020+#define STLE_SET_OPC(pLE, Opc) ((pLE)->St.Opcode = (Opc))
9021+
9022+#define STLE_GET_FRSTATUS(pLE) LE2DWord((pLE)->St.StUn.StRxStatWord)
9023+#define STLE_GET_TIST(pLE) LE2DWord((pLE)->St.StUn.StRxTimeStamp)
9024+#define STLE_GET_TCP1(pLE) LE2Word((pLE)->St.StUn.StRxTCPCSum.RxTCPSum1)
9025+#define STLE_GET_TCP2(pLE) LE2Word((pLE)->St.StUn.StRxTCPCSum.RxTCPSum2)
9026+#define STLE_GET_LEN(pLE) LE2Word((pLE)->St.Stat.BufLen)
9027+#define STLE_GET_VLAN(pLE) LE2Word((pLE)->St.Stat.VlanTag)
9028+#define STLE_GET_LINK(pLE) ((pLE)->St.Link)
9029+#define STLE_GET_OPC(pLE) ((pLE)->St.Opcode)
9030+#define STLE_GET_DONE_IDX(pLE,LowVal,HighVal) { \
9031+ (LowVal) = LE2DWord((pLE)->St.StUn.StTxStatLow); \
9032+ (HighVal) = LE2Word((pLE)->St.Stat.StTxStatHi); \
9033+}
9034+
9035+#define STLE_GET_RSS(pLE) LE2DWord((pLE)->St.StUn.StRxRssValue)
9036+#define STLE_GET_IPBIT(pLE) ((pLE)->St.Stat.Rss.FlagField & RSS_IP_FLAG)
9037+#define STLE_GET_TCPBIT(pLE) ((pLE)->St.Stat.Rss.FlagField & RSS_TCP_FLAG)
9038+
9039+
9040+/* I always take both values as a paramter to avoid typos */
9041+#define STLE_GET_DONE_IDX_TXA1(LowVal,HighVal) \
9042+ (((LowVal) & STLE_TXA1_MSKL) >> STLE_TXA1_SHIFTL)
9043+#define STLE_GET_DONE_IDX_TXS1(LowVal,HighVal) \
9044+ ((LowVal & STLE_TXS1_MSKL) >> STLE_TXS1_SHIFTL)
9045+#define STLE_GET_DONE_IDX_TXA2(LowVal,HighVal) \
9046+ (((LowVal & STLE_TXA2_MSKL) >> STLE_TXA2_SHIFTL) + \
9047+ ((HighVal & STLE_TXA2_MSKH) << STLE_TXA2_SHIFTH))
9048+#define STLE_GET_DONE_IDX_TXS2(LowVal,HighVal) \
9049+ ((HighVal & STLE_TXS2_MSKH) >> STLE_TXS2_SHIFTH)
9050+
9051+
9052+#define SK_Y2_RXSTAT_CHECK_PKT(Len, RxStat, IsOk) { \
9053+ (IsOk) = (((RxStat) & GMR_FS_RX_OK) != 0) && \
9054+ (((RxStat) & GMR_FS_ANY_ERR) == 0); \
9055+ \
9056+ if ((IsOk) && ((SK_U16)(((RxStat) & GMR_FS_LEN_MSK) >> \
9057+ GMR_FS_LEN_SHIFT) != (Len))) { \
9058+ /* length in MAC status differs from length in LE */\
9059+ (IsOk) = SK_FALSE; \
9060+ } \
9061+}
9062+
9063+
9064+/******************************************************************************
9065+ *
9066+ * Polling unit list element macros
9067+ *
9068+ * NOTE: the Idx must be <= 0xfff and PU_PUTIDX_VALID makes them valid
9069+ *
9070+ */
9071+
9072+#ifdef USE_POLLING_UNIT
9073+
9074+#define POLE_SET_OPC(pLE, Opc) ((pLE)->Sa.Opcode = (Opc))
9075+#define POLE_SET_LINK(pLE, Port) ((pLE)->Sa.Link = (Port))
9076+#define POLE_SET_RXIDX(pLE, Idx) ((pLE)->Sa.RxIdxVld = Word2LE(Idx))
9077+#define POLE_SET_TXAIDX(pLE, Idx) ((pLE)->Sa.TxAIdxVld = Word2LE(Idx))
9078+#define POLE_SET_TXSIDX(pLE, Idx) ((pLE)->Sa.TxSIdxVld = Word2LE(Idx))
9079+
9080+#define POLE_GET_OPC(pLE) ((pLE)->Sa.Opcode)
9081+#define POLE_GET_LINK(pLE) ((pLE)->Sa.Link)
9082+#define POLE_GET_RXIDX(pLE) LE2Word((pLE)->Sa.RxIdxVld)
9083+#define POLE_GET_TXAIDX(pLE) LE2Word((pLE)->Sa.TxAIdxVld)
9084+#define POLE_GET_TXSIDX(pLE) LE2Word((pLE)->Sa.TxSIdxVld)
9085+
9086+#endif /* USE_POLLING_UNIT */
9087+
9088+/******************************************************************************
9089+ *
9090+ * Debug macros for list elements
9091+ *
9092+ */
9093+
9094+#ifdef DEBUG
9095+
9096+#define SK_DBG_DUMP_RX_LE(pLE) { \
9097+ SK_U8 Opcode; \
9098+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9099+ ("=== RX_LIST_ELEMENT @addr: %p cont: %02x %02x %02x %02x %02x %02x %02x %02x\n", \
9100+ pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\
9101+ ((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5], \
9102+ ((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7])); \
9103+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9104+ ("\t (16bit) %04x %04x %04x %04x\n", \
9105+ ((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2], \
9106+ ((SK_U16 *) pLE)[3])); \
9107+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9108+ ("\t (32bit) %08x %08x\n", \
9109+ ((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1])); \
9110+ Opcode = RXLE_GET_OPC(pLE); \
9111+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9112+ ("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == HW_OWNER) ? \
9113+ "Hardware" : "Software")); \
9114+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9115+ ("\tOpc: 0x%x ",Opcode)); \
9116+ switch (Opcode & (~HW_OWNER)) { \
9117+ case OP_BUFFER: \
9118+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9119+ ("\tOP_BUFFER\n")); \
9120+ break; \
9121+ case OP_PACKET: \
9122+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9123+ ("\tOP_PACKET\n")); \
9124+ break; \
9125+ case OP_ADDR64: \
9126+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9127+ ("\tOP_ADDR64\n")); \
9128+ break; \
9129+ case OP_TCPSTART: \
9130+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9131+ ("\tOP_TCPPAR\n")); \
9132+ break; \
9133+ case SW_OWNER: \
9134+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9135+ ("\tunused LE\n")); \
9136+ break; \
9137+ default: \
9138+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9139+ ("\tunknown Opcode!!!\n")); \
9140+ break; \
9141+ } \
9142+ if ((Opcode & OP_BUFFER) == OP_BUFFER) { \
9143+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9144+ ("\tControl: 0x%x\n", RXLE_GET_CTRL(pLE))); \
9145+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9146+ ("\tBufLen: 0x%x\n", RXLE_GET_LEN(pLE))); \
9147+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9148+ ("\tLowAddr: 0x%x\n", RXLE_GET_ADDR(pLE))); \
9149+ } \
9150+ if ((Opcode & OP_ADDR64) == OP_ADDR64) { \
9151+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9152+ ("\tHighAddr: 0x%x\n", RXLE_GET_ADDR(pLE))); \
9153+ } \
9154+ if ((Opcode & OP_TCPSTART) == OP_TCPSTART) { \
9155+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9156+ ("\tTCP Sum Start 1 : 0x%x\n", RXLE_GET_STACS1(pLE))); \
9157+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9158+ ("\tTCP Sum Start 2 : 0x%x\n", RXLE_GET_STACS2(pLE))); \
9159+ } \
9160+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9161+ ("=====================\n")); \
9162+}
9163+
9164+#define SK_DBG_DUMP_TX_LE(pLE) { \
9165+ SK_U8 Opcode; \
9166+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9167+ ("=== TX_LIST_ELEMENT @addr: %p cont: %02x %02x %02x %02x %02x %02x %02x %02x\n", \
9168+ pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\
9169+ ((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5], \
9170+ ((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7])); \
9171+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9172+ ("\t (16bit) %04x %04x %04x %04x\n", \
9173+ ((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2], \
9174+ ((SK_U16 *) pLE)[3])); \
9175+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9176+ ("\t (32bit) %08x %08x\n", \
9177+ ((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1])); \
9178+ Opcode = TXLE_GET_OPC(pLE); \
9179+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9180+ ("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == HW_OWNER) ? \
9181+ "Hardware" : "Software")); \
9182+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9183+ ("\tOpc: 0x%x ",Opcode)); \
9184+ switch (Opcode & (~HW_OWNER)) { \
9185+ case OP_TCPCHKSUM: \
9186+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9187+ ("\tOP_TCPCHKSUM\n")); \
9188+ break; \
9189+ case OP_TCPIS: \
9190+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9191+ ("\tOP_TCPIS\n")); \
9192+ break; \
9193+ case OP_TCPLCK: \
9194+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9195+ ("\tOP_TCPLCK\n")); \
9196+ break; \
9197+ case OP_TCPLW: \
9198+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9199+ ("\tOP_TCPLW\n")); \
9200+ break; \
9201+ case OP_TCPLSW: \
9202+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9203+ ("\tOP_TCPLSW\n")); \
9204+ break; \
9205+ case OP_TCPLISW: \
9206+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9207+ ("\tOP_TCPLISW\n")); \
9208+ break; \
9209+ case OP_ADDR64: \
9210+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9211+ ("\tOP_ADDR64\n")); \
9212+ break; \
9213+ case OP_VLAN: \
9214+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9215+ ("\tOP_VLAN\n")); \
9216+ break; \
9217+ case OP_ADDR64VLAN: \
9218+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9219+ ("\tOP_ADDR64VLAN\n")); \
9220+ break; \
9221+ case OP_LRGLEN: \
9222+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9223+ ("\tOP_LRGLEN\n")); \
9224+ break; \
9225+ case OP_LRGLENVLAN: \
9226+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9227+ ("\tOP_LRGLENVLAN\n")); \
9228+ break; \
9229+ case OP_BUFFER: \
9230+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9231+ ("\tOP_BUFFER\n")); \
9232+ break; \
9233+ case OP_PACKET: \
9234+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9235+ ("\tOP_PACKET\n")); \
9236+ break; \
9237+ case OP_LARGESEND: \
9238+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9239+ ("\tOP_LARGESEND\n")); \
9240+ break; \
9241+ case SW_OWNER: \
9242+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9243+ ("\tunused LE\n")); \
9244+ break; \
9245+ default: \
9246+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9247+ ("\tunknown Opcode!!!\n")); \
9248+ break; \
9249+ } \
9250+ if ((Opcode & OP_BUFFER) == OP_BUFFER) { \
9251+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9252+ ("\tControl: 0x%x\n", TXLE_GET_CTRL(pLE))); \
9253+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9254+ ("\tBufLen: 0x%x\n", TXLE_GET_LEN(pLE))); \
9255+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9256+ ("\tLowAddr: 0x%x\n", TXLE_GET_ADDR(pLE))); \
9257+ } \
9258+ if ((Opcode & OP_ADDR64) == OP_ADDR64) { \
9259+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9260+ ("\tHighAddr: 0x%x\n", TXLE_GET_ADDR(pLE))); \
9261+ } \
9262+ if ((Opcode & OP_VLAN) == OP_VLAN) { \
9263+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9264+ ("\tVLAN Id: 0x%x\n", TXLE_GET_VLAN(pLE))); \
9265+ } \
9266+ if ((Opcode & OP_LRGLEN) == OP_LRGLEN) { \
9267+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9268+ ("\tLarge send length: 0x%x\n", TXLE_GET_LSLEN(pLE))); \
9269+ } \
9270+ if ((Opcode &(~HW_OWNER)) <= OP_ADDR64) { \
9271+ if ((Opcode & OP_TCPWRITE) == OP_TCPWRITE) { \
9272+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9273+ ("\tTCP Sum Write: 0x%x\n", TXLE_GET_WRICS(pLE))); \
9274+ } \
9275+ if ((Opcode & OP_TCPSTART) == OP_TCPSTART) { \
9276+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9277+ ("\tTCP Sum Start: 0x%x\n", TXLE_GET_STACS(pLE))); \
9278+ } \
9279+ if ((Opcode & OP_TCPINIT) == OP_TCPINIT) { \
9280+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9281+ ("\tTCP Sum Init: 0x%x\n", TXLE_GET_INICS(pLE))); \
9282+ } \
9283+ if ((Opcode & OP_TCPLCK) == OP_TCPLCK) { \
9284+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9285+ ("\tTCP Sum Lock: 0x%x\n", TXLE_GET_LCKCS(pLE))); \
9286+ } \
9287+ } \
9288+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9289+ ("=====================\n")); \
9290+}
9291+
9292+#define SK_DBG_DUMP_ST_LE(pLE) { \
9293+ SK_U8 Opcode; \
9294+ SK_U16 HighVal; \
9295+ SK_U32 LowVal; \
9296+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9297+ ("=== ST_LIST_ELEMENT @addr: %p contains: %02x %02x %02x %02x %02x %02x %02x %02x\n",\
9298+ pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\
9299+ ((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5], \
9300+ ((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7])); \
9301+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9302+ ("\t (16bit) %04x %04x %04x %04x\n", \
9303+ ((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2], \
9304+ ((SK_U16 *) pLE)[3])); \
9305+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9306+ ("\t (32bit) %08x %08x\n", \
9307+ ((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1])); \
9308+ Opcode = STLE_GET_OPC(pLE); \
9309+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9310+ ("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == SW_OWNER) ? \
9311+ "Hardware" : "Software")); \
9312+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9313+ ("\tOpc: 0x%x", Opcode)); \
9314+ Opcode &= (~HW_OWNER); \
9315+ switch (Opcode) { \
9316+ case OP_RXSTAT: \
9317+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9318+ ("\tOP_RXSTAT\n")); \
9319+ break; \
9320+ case OP_RXTIMESTAMP: \
9321+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9322+ ("\tOP_RXTIMESTAMP\n")); \
9323+ break; \
9324+ case OP_RXVLAN: \
9325+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9326+ ("\tOP_RXVLAN\n")); \
9327+ break; \
9328+ case OP_RXCHKS: \
9329+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9330+ ("\tOP_RXCHKS\n")); \
9331+ break; \
9332+ case OP_RXCHKSVLAN: \
9333+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9334+ ("\tOP_RXCHKSVLAN\n")); \
9335+ break; \
9336+ case OP_RXTIMEVLAN: \
9337+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9338+ ("\tOP_RXTIMEVLAN\n")); \
9339+ break; \
9340+ case OP_RSS_HASH: \
9341+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9342+ ("\tOP_RSS_HASH\n")); \
9343+ break; \
9344+ case OP_TXINDEXLE: \
9345+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9346+ ("\tOP_TXINDEXLE\n")); \
9347+ break; \
9348+ case HW_OWNER: \
9349+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9350+ ("\tunused LE\n")); \
9351+ break; \
9352+ default: \
9353+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9354+ ("\tunknown status list element!!!\n")); \
9355+ break; \
9356+ } \
9357+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9358+ ("\tPort: %c\n", 'A' + STLE_GET_LINK(pLE))); \
9359+ if (Opcode == OP_RXSTAT) { \
9360+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9361+ ("\tFrameLen: 0x%x\n", STLE_GET_LEN(pLE))); \
9362+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9363+ ("\tFrameStat: 0x%x\n", STLE_GET_FRSTATUS(pLE))); \
9364+ } \
9365+ if ((Opcode & OP_RXVLAN) == OP_RXVLAN) { \
9366+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9367+ ("\tVLAN Id: 0x%x\n", STLE_GET_VLAN(pLE))); \
9368+ } \
9369+ if ((Opcode & OP_RXTIMESTAMP) == OP_RXTIMESTAMP) { \
9370+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9371+ ("\tTimestamp: 0x%x\n", STLE_GET_TIST(pLE))); \
9372+ } \
9373+ if ((Opcode & OP_RXCHKS) == OP_RXCHKS) { \
9374+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9375+ ("\tTCP: 0x%x 0x%x\n", STLE_GET_TCP1(pLE), \
9376+ STLE_GET_TCP2(pLE))); \
9377+ } \
9378+ if (Opcode == OP_TXINDEXLE) { \
9379+ STLE_GET_DONE_IDX(pLE, LowVal, HighVal); \
9380+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9381+ ("\tTx Index TxA1: 0x%x\n", \
9382+ STLE_GET_DONE_IDX_TXA1(LowVal,HighVal))); \
9383+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9384+ ("\tTx Index TxS1: 0x%x\n", \
9385+ STLE_GET_DONE_IDX_TXS1(LowVal,HighVal))); \
9386+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9387+ ("\tTx Index TxA2: 0x%x\n", \
9388+ STLE_GET_DONE_IDX_TXA2(LowVal,HighVal))); \
9389+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9390+ ("\tTx Index TxS2: 0x%x\n", \
9391+ STLE_GET_DONE_IDX_TXS2(LowVal,HighVal))); \
9392+ } \
9393+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9394+ ("=====================\n")); \
9395+}
9396+
9397+#ifdef USE_POLLING_UNIT
9398+#define SK_DBG_DUMP_PO_LE(pLE) { \
9399+ SK_U8 Opcode; \
9400+ SK_U16 Idx; \
9401+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9402+ ("=== PO_LIST_ELEMENT @addr: %p cont: %02x %02x %02x %02x %02x %02x %02x %02x\n", \
9403+ pLE, ((SK_U8 *) pLE)[0], ((SK_U8 *) pLE)[1], ((SK_U8 *) pLE)[2],\
9404+ ((SK_U8 *) pLE)[3], ((SK_U8 *) pLE)[4], ((SK_U8 *) pLE)[5], \
9405+ ((SK_U8 *) pLE)[6], ((SK_U8 *) pLE)[7])); \
9406+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9407+ ("\t (16bit) %04x %04x %04x %04x\n", \
9408+ ((SK_U16 *) pLE)[0], ((SK_U16 *) pLE)[1], ((SK_U16 *) pLE)[2], \
9409+ ((SK_U16 *) pLE)[3])); \
9410+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9411+ ("\t (32bit) %08x %08x\n", \
9412+ ((SK_U32 *) pLE)[0], ((SK_U32 *) pLE)[1])); \
9413+ Opcode = POLE_GET_OPC(pLE); \
9414+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9415+ ("\tOwn belongs to %s\n", ((Opcode & HW_OWNER) == HW_OWNER) ? \
9416+ "Hardware" : "Software")); \
9417+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9418+ ("\tOpc: 0x%x ",Opcode)); \
9419+ if ((Opcode & ~HW_OWNER) == OP_PUTIDX) { \
9420+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9421+ ("\tOP_PUTIDX\n")); \
9422+ } \
9423+ else { \
9424+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9425+ ("\tunknown Opcode!!!\n")); \
9426+ } \
9427+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9428+ ("\tPort %c\n", 'A' + POLE_GET_LINK(pLE))); \
9429+ Idx = POLE_GET_TXAIDX(pLE); \
9430+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9431+ ("\tTxA Index is 0x%X and %svalid\n", Idx, \
9432+ (Idx & PU_PUTIDX_VALID) ? "" : "not ")); \
9433+ Idx = POLE_GET_TXSIDX(pLE); \
9434+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9435+ ("\tTxS Index is 0x%X and %svalid\n", Idx, \
9436+ (Idx & PU_PUTIDX_VALID) ? "" : "not ")); \
9437+ Idx = POLE_GET_RXIDX(pLE); \
9438+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9439+ ("\tRx Index is 0x%X and %svalid\n", Idx, \
9440+ (Idx & PU_PUTIDX_VALID) ? "" : "not ")); \
9441+ SK_DBG_MSG(pAc, SK_DBGMOD_HWM, SK_DBGCAT_INIT, \
9442+ ("=====================\n")); \
9443+}
9444+#endif /* USE_POLLING_UNIT */
9445+
9446+#else /* !DEBUG */
9447+
9448+#define SK_DBG_DUMP_RX_LE(pLE)
9449+#define SK_DBG_DUMP_TX_LE(pLE)
9450+#define SK_DBG_DUMP_ST_LE(pLE)
9451+#define SK_DBG_DUMP_PO_LE(pLE)
9452+
9453+#endif /* !DEBUG */
9454+
9455+/******************************************************************************
9456+ *
9457+ * Macros for listelement tables
9458+ *
9459+ *
9460+ */
9461+
9462+#define LE_SIZE sizeof(SK_HWLE)
9463+#define LE_TAB_SIZE(NumElements) ((NumElements) * LE_SIZE)
9464+
9465+/* Number of unused list elements in table
9466+ * this macro always returns the number of free listelements - 1
9467+ * this way we want to guarantee that always one LE remains unused
9468+ */
9469+#define NUM_FREE_LE_IN_TABLE(pTable) \
9470+ ( ((pTable)->Put >= (pTable)->Done) ? \
9471+ (NUM_LE_IN_TABLE(pTable) - (pTable)->Put + (pTable)->Done - 1) :\
9472+ ((pTable)->Done - (pTable)->Put - 1) )
9473+
9474+/* total number of list elements in table */
9475+#define NUM_LE_IN_TABLE(pTable) ((pTable)->Num)
9476+
9477+/* get next unused Rx list element */
9478+#define GET_RX_LE(pLE, pTable) { \
9479+ pLE = &(pTable)->pLETab[(pTable)->Put]; \
9480+ (pTable)->Put = ((pTable)->Put + 1) & (NUM_LE_IN_TABLE(pTable) - 1);\
9481+}
9482+
9483+/* get next unused Tx list element */
9484+#define GET_TX_LE(pLE, pTable) GET_RX_LE(pLE, pTable)
9485+
9486+/* get next status list element expected to be finished by hw */
9487+#define GET_ST_LE(pLE, pTable) { \
9488+ pLE = &(pTable)->pLETab[(pTable)->Done]; \
9489+ (pTable)->Done = ((pTable)->Done +1) & (NUM_LE_IN_TABLE(pTable) - 1);\
9490+}
9491+
9492+#ifdef USE_POLLING_UNIT
9493+/* get next polling unit list element for port */
9494+#define GET_PO_LE(pLE, pTable, Port) { \
9495+ pLE = &(pTable)->pLETab[(Port)]; \
9496+}
9497+#endif /* USE_POLLING_UNIT */
9498+
9499+#define GET_PUT_IDX(pTable) ((pTable)->Put)
9500+
9501+#define UPDATE_HWPUT_IDX(pTable) {(pTable)->HwPut = (pTable)->Put; }
9502+
9503+/*
9504+ * get own bit of next status LE
9505+ * if the result is != 0 there has been at least one status LE finished
9506+ */
9507+#define OWN_OF_FIRST_LE(pTable) \
9508+ (STLE_GET_OPC(&(pTable)->pLETab[(pTable)->Done]) & HW_OWNER)
9509+
9510+#define SET_DONE_INDEX(pTable, Idx) (pTable)->Done = (Idx);
9511+
9512+#define GET_DONE_INDEX(pTable) ((pTable)->Done)
9513+
9514+#ifdef SAFE_BUT_SLOW
9515+
9516+/* check own bit of LE before current done idx */
9517+#define CHECK_STLE_OVERFLOW(pTable, IsOk) { \
9518+ unsigned i; \
9519+ if ((i = (pTable)->Done) == 0) { \
9520+ i = NUM_LE_IN_TABLE(pTable); \
9521+ } \
9522+ else { \
9523+ i = i - 1; \
9524+ } \
9525+ if (STLE_GET_OPC(&(pTable)->pLETab[i]) == HW_OWNER) { \
9526+ (IsOk) = SK_TRUE; \
9527+ } \
9528+ else { \
9529+ (IsOk) = SK_FALSE; \
9530+ } \
9531+ }
9532+
9533+
9534+/*
9535+ * for Yukon-2 the hardware is not polling the list elements, so it
9536+ * is not necessary to change the own-bit of Rx or Tx LEs before
9537+ * reusing them
9538+ * but it might make debugging easier if one simply can see whether
9539+ * a LE has been worked on
9540+ */
9541+
9542+#define CLEAR_LE_OWN(pTable, Idx) \
9543+ STLE_SET_OPC(&(pTable)->pLETab[(Idx)], SW_OWNER)
9544+
9545+/*
9546+ * clear all own bits starting from old done index up to the LE before
9547+ * the new done index
9548+ */
9549+#define CLEAR_LE_OWN_FROM_DONE_TO(pTable, To) { \
9550+ int i; \
9551+ i = (pTable)->Done; \
9552+ while (i != To) { \
9553+ CLEAR_LE_OWN(pTable, i); \
9554+ i = (i + 1) & (NUM_LE_IN_TABLE(pTable) - 1); \
9555+ } \
9556+ }
9557+
9558+#else /* !SAFE_BUT_SLOW */
9559+
9560+#define CHECK_STLE_OVERFLOW(pTable, IsOk)
9561+#define CLEAR_LE_OWN(pTable, Idx)
9562+#define CLEAR_LE_OWN_FROM_DONE_TO(pTable, To)
9563+
9564+#endif /* !SAFE_BUT_SLOW */
9565+
9566+
9567+/* typedefs *******************************************************************/
9568+
9569+typedef struct s_LetRxTx {
9570+ SK_U16 VlanId; /* VLAN Id given down last time */
9571+ SK_U16 TcpWp; /* TCP Checksum Write Position */
9572+ SK_U16 TcpSp1; /* TCP Checksum Calculation Start Position 1 */
9573+ SK_U16 TcpSp2; /* TCP Checksum Calculation Start Position 2 */
9574+ SK_U16 MssValue; /* Maximum Segment Size */
9575+ SK_U16 Reserved1; /* reserved word for furture extensions */
9576+ SK_U16 Reserved2; /* reserved word for furture extensions */
9577+ SK_U16 Reserved3; /* reserved word for furture extensions */
9578+} SK_LET_RX_TX;
9579+
9580+typedef struct s_LetStat {
9581+ SK_U32 RxTimeStamp; /* Receive Timestamp */
9582+ SK_U32 RssHashValue; /* RSS Hash Value */
9583+ SK_BOOL RssIsIp; /* RSS Hash Value: IP packet detected */
9584+ SK_BOOL RssIsTcp; /* RSS Hash Value: IP+TCP packet detected */
9585+ SK_U16 VlanId; /* VLAN Id given received by Status BMU */
9586+ SK_U16 TcpSum1; /* TCP checksum 1 (status BMU) */
9587+ SK_U16 TcpSum2; /* TCP checksum 2 (status BMU) */
9588+} SK_LET_STAT;
9589+
9590+typedef union s_LetBmuSpec {
9591+ SK_LET_RX_TX RxTx; /* Rx/Tx BMU specific variables */
9592+ SK_LET_STAT Stat; /* Status BMU specific variables */
9593+} SK_LET_BMU_S;
9594+
9595+typedef struct s_le_table {
9596+ /* all LE's between Done and HWPut are owned by the hardware */
9597+ /* all LE's between Put and Done can be used from Software */
9598+ /* all LE's between HWPut and Put are currently processed in DriverSend */
9599+ unsigned Done; /* done index - consumed from HW and available */
9600+ unsigned Put; /* put index - to be given to hardware */
9601+ unsigned HwPut; /* put index actually given to hardware */
9602+ unsigned Num; /* total number of list elements */
9603+ SK_HWLE *pLETab; /* virtual address of list element table */
9604+ SK_U32 pPhyLETABLow; /* physical address of list element table */
9605+ SK_U32 pPhyLETABHigh; /* physical address of list element table */
9606+ /* values to remember in order to save some LEs */
9607+ SK_U32 BufHighAddr; /* high addr given down last time */
9608+ SK_LET_BMU_S Bmu; /* contains BMU specific information */
9609+ SK_U32 private; /* driver private variable free usable */
9610+ SK_U16 TcpInitCsum; /* Init. Checksum */
9611+} SK_LE_TABLE;
9612+
9613+/* function prototypes ********************************************************/
9614+
9615+#ifndef SK_KR_PROTO
9616+
9617+/*
9618+ * public functions in sky2le.c
9619+ */
9620+extern void SkGeY2SetPutIndex(
9621+ SK_AC *pAC,
9622+ SK_IOC IoC,
9623+ SK_U32 StartAddrPrefetchUnit,
9624+ SK_LE_TABLE *pLETab);
9625+
9626+extern void SkGeY2InitPrefetchUnit(
9627+ SK_AC *pAC,
9628+ SK_IOC IoC,
9629+ unsigned int Queue,
9630+ SK_LE_TABLE *pLETab);
9631+
9632+extern void SkGeY2InitStatBmu(
9633+ SK_AC *pAC,
9634+ SK_IOC IoC,
9635+ SK_LE_TABLE *pLETab);
9636+
9637+extern void SkGeY2InitPollUnit(
9638+ SK_AC *pAC,
9639+ SK_IOC IoC,
9640+ SK_LE_TABLE *pLETab);
9641+
9642+extern void SkGeY2InitSingleLETable(
9643+ SK_AC *pAC,
9644+ SK_LE_TABLE *pLETab,
9645+ unsigned int NumLE,
9646+ void *pVMem,
9647+ SK_U32 PMemLowAddr,
9648+ SK_U32 PMemHighAddr);
9649+
9650+#else /* SK_KR_PROTO */
9651+extern void SkGeY2SetPutIndex();
9652+extern void SkGeY2InitPrefetchUnit();
9653+extern void SkGeY2InitStatBmu();
9654+extern void SkGeY2InitPollUnit();
9655+extern void SkGeY2InitSingleLETable();
9656+#endif /* SK_KR_PROTO */
9657+
9658+#ifdef __cplusplus
9659+}
9660+#endif /* __cplusplus */
9661+
9662+#endif /* __INC_SKY2LE_H */
9663+
9664diff -ruN linux/drivers/net/sk98lin/h/xmac_ii.h linux-new/drivers/net/sk98lin/h/xmac_ii.h
9665--- linux/drivers/net/sk98lin/h/xmac_ii.h 2006-04-11 19:19:28.000000000 +0200
9666+++ linux-new/drivers/net/sk98lin/h/xmac_ii.h 2006-01-18 14:37:24.000000000 +0100
9667@@ -2,23 +2,24 @@
9668 *
9669 * Name: xmac_ii.h
9670 * Project: Gigabit Ethernet Adapters, Common Modules
9671- * Version: $Revision$
9672- * Date: $Date$
9673+ * Version: $Revision$
9674+ * Date: $Date$
9675 * Purpose: Defines and Macros for Gigabit Ethernet Controller
9676 *
9677 ******************************************************************************/
9678
9679 /******************************************************************************
9680 *
9681+ * LICENSE:
9682 * (C)Copyright 1998-2002 SysKonnect.
9683- * (C)Copyright 2002-2003 Marvell.
9684+ * (C)Copyright 2002-2005 Marvell.
9685 *
9686 * This program is free software; you can redistribute it and/or modify
9687 * it under the terms of the GNU General Public License as published by
9688 * the Free Software Foundation; either version 2 of the License, or
9689 * (at your option) any later version.
9690- *
9691 * The information in this file is provided "AS IS" without warranty.
9692+ * /LICENSE
9693 *
9694 ******************************************************************************/
9695
9696@@ -371,18 +372,18 @@
9697 /* Bit 16..6: reserved */
9698 #define XM_SC_SNP_RXC (1<<5) /* Bit 5: (sc) Snap Rx Counters */
9699 #define XM_SC_SNP_TXC (1<<4) /* Bit 4: (sc) Snap Tx Counters */
9700-#define XM_SC_CP_RXC (1<<3) /* Bit 3: Copy Rx Counters Continuously */
9701+#define XM_SC_CP_RXC (1<<3) /* Bit 3: Copy Rx Counters Continuously */
9702 #define XM_SC_CP_TXC (1<<2) /* Bit 2: Copy Tx Counters Continuously */
9703 #define XM_SC_CLR_RXC (1<<1) /* Bit 1: (sc) Clear Rx Counters */
9704-#define XM_SC_CLR_TXC (1<<0) /* Bit 0: (sc) Clear Tx Counters */
9705+#define XM_SC_CLR_TXC (1<<0) /* Bit 0: (sc) Clear Tx Counters */
9706
9707
9708 /* XM_RX_CNT_EV 32 bit r/o Rx Counter Event Register */
9709 /* XM_RX_EV_MSK 32 bit r/w Rx Counter Event Mask */
9710-#define XMR_MAX_SZ_OV (1UL<<31) /* Bit 31: 1024-MaxSize Rx Cnt Ov*/
9711-#define XMR_1023B_OV (1L<<30) /* Bit 30: 512-1023Byte Rx Cnt Ov*/
9712-#define XMR_511B_OV (1L<<29) /* Bit 29: 256-511 Byte Rx Cnt Ov*/
9713-#define XMR_255B_OV (1L<<28) /* Bit 28: 128-255 Byte Rx Cnt Ov*/
9714+#define XMR_MAX_SZ_OV (1UL<<31) /* Bit 31: 1024-MaxSize Rx Cnt Ov */
9715+#define XMR_1023B_OV (1L<<30) /* Bit 30: 512-1023Byte Rx Cnt Ov */
9716+#define XMR_511B_OV (1L<<29) /* Bit 29: 256-511 Byte Rx Cnt Ov */
9717+#define XMR_255B_OV (1L<<28) /* Bit 28: 128-255 Byte Rx Cnt Ov */
9718 #define XMR_127B_OV (1L<<27) /* Bit 27: 65-127 Byte Rx Cnt Ov */
9719 #define XMR_64B_OV (1L<<26) /* Bit 26: 64 Byte Rx Cnt Ov */
9720 #define XMR_UTIL_OV (1L<<25) /* Bit 25: Rx Util Cnt Overflow */
9721@@ -390,9 +391,9 @@
9722 #define XMR_CEX_ERR_OV (1L<<23) /* Bit 23: CEXT Err Cnt Ov */
9723 /* Bit 22: reserved */
9724 #define XMR_FCS_ERR_OV (1L<<21) /* Bit 21: Rx FCS Error Cnt Ov */
9725-#define XMR_LNG_ERR_OV (1L<<20) /* Bit 20: Rx too Long Err Cnt Ov*/
9726+#define XMR_LNG_ERR_OV (1L<<20) /* Bit 20: Rx too Long Err Cnt Ov */
9727 #define XMR_RUNT_OV (1L<<19) /* Bit 19: Runt Event Cnt Ov */
9728-#define XMR_SHT_ERR_OV (1L<<18) /* Bit 18: Rx Short Ev Err Cnt Ov*/
9729+#define XMR_SHT_ERR_OV (1L<<18) /* Bit 18: Rx Short Ev Err Cnt Ov */
9730 #define XMR_SYM_ERR_OV (1L<<17) /* Bit 17: Rx Sym Err Cnt Ov */
9731 /* Bit 16: reserved */
9732 #define XMR_CAR_ERR_OV (1L<<15) /* Bit 15: Rx Carr Ev Err Cnt Ov */
9733@@ -401,57 +402,57 @@
9734 #define XMR_FRA_ERR_OV (1L<<12) /* Bit 12: Rx Framing Err Cnt Ov */
9735 #define XMR_FMISS_OV (1L<<11) /* Bit 11: Rx Missed Ev Cnt Ov */
9736 #define XMR_BURST (1L<<10) /* Bit 10: Rx Burst Event Cnt Ov */
9737-#define XMR_INV_MOC (1L<<9) /* Bit 9: Rx with inv. MAC OC Ov*/
9738+#define XMR_INV_MOC (1L<<9) /* Bit 9: Rx with inv. MAC OC Ov */
9739 #define XMR_INV_MP (1L<<8) /* Bit 8: Rx inv Pause Frame Ov */
9740 #define XMR_MCTRL_OV (1L<<7) /* Bit 7: Rx MAC Ctrl-F Cnt Ov */
9741-#define XMR_MPAUSE_OV (1L<<6) /* Bit 6: Rx Pause MAC Ctrl-F Ov*/
9742-#define XMR_UC_OK_OV (1L<<5) /* Bit 5: Rx Unicast Frame CntOv*/
9743+#define XMR_MPAUSE_OV (1L<<6) /* Bit 6: Rx Pause MAC Ctrl-F Ov */
9744+#define XMR_UC_OK_OV (1L<<5) /* Bit 5: Rx Unicast Frame Cnt Ov */
9745 #define XMR_MC_OK_OV (1L<<4) /* Bit 4: Rx Multicast Cnt Ov */
9746 #define XMR_BC_OK_OV (1L<<3) /* Bit 3: Rx Broadcast Cnt Ov */
9747-#define XMR_OK_LO_OV (1L<<2) /* Bit 2: Octets Rx OK Low CntOv*/
9748-#define XMR_OK_HI_OV (1L<<1) /* Bit 1: Octets Rx OK Hi Cnt Ov*/
9749-#define XMR_OK_OV (1L<<0) /* Bit 0: Frames Received Ok Ov */
9750+#define XMR_OK_LO_OV (1L<<2) /* Bit 2: Octets Rx OK Low Cnt Ov */
9751+#define XMR_OK_HI_OV (1L<<1) /* Bit 1: Octets Rx OK High Cnt Ov */
9752+#define XMR_OK_OV (1L<<0) /* Bit 0: Frames Received OK Ov */
9753
9754 #define XMR_DEF_MSK (XMR_OK_LO_OV | XMR_OK_HI_OV)
9755
9756 /* XM_TX_CNT_EV 32 bit r/o Tx Counter Event Register */
9757 /* XM_TX_EV_MSK 32 bit r/w Tx Counter Event Mask */
9758 /* Bit 31..26: reserved */
9759-#define XMT_MAX_SZ_OV (1L<<25) /* Bit 25: 1024-MaxSize Tx Cnt Ov*/
9760-#define XMT_1023B_OV (1L<<24) /* Bit 24: 512-1023Byte Tx Cnt Ov*/
9761-#define XMT_511B_OV (1L<<23) /* Bit 23: 256-511 Byte Tx Cnt Ov*/
9762-#define XMT_255B_OV (1L<<22) /* Bit 22: 128-255 Byte Tx Cnt Ov*/
9763+#define XMT_MAX_SZ_OV (1L<<25) /* Bit 25: 1024-MaxSize Tx Cnt Ov */
9764+#define XMT_1023B_OV (1L<<24) /* Bit 24: 512-1023Byte Tx Cnt Ov */
9765+#define XMT_511B_OV (1L<<23) /* Bit 23: 256-511 Byte Tx Cnt Ov */
9766+#define XMT_255B_OV (1L<<22) /* Bit 22: 128-255 Byte Tx Cnt Ov */
9767 #define XMT_127B_OV (1L<<21) /* Bit 21: 65-127 Byte Tx Cnt Ov */
9768 #define XMT_64B_OV (1L<<20) /* Bit 20: 64 Byte Tx Cnt Ov */
9769 #define XMT_UTIL_OV (1L<<19) /* Bit 19: Tx Util Cnt Overflow */
9770 #define XMT_UTIL_UR (1L<<18) /* Bit 18: Tx Util Cnt Underrun */
9771-#define XMT_CS_ERR_OV (1L<<17) /* Bit 17: Tx Carr Sen Err Cnt Ov*/
9772+#define XMT_CS_ERR_OV (1L<<17) /* Bit 17: Tx Carr Sen Err Cnt Ov */
9773 #define XMT_FIFO_UR_OV (1L<<16) /* Bit 16: Tx FIFO Ur Ev Cnt Ov */
9774 #define XMT_EX_DEF_OV (1L<<15) /* Bit 15: Tx Ex Deferall Cnt Ov */
9775 #define XMT_DEF (1L<<14) /* Bit 14: Tx Deferred Cnt Ov */
9776 #define XMT_LAT_COL_OV (1L<<13) /* Bit 13: Tx Late Col Cnt Ov */
9777-#define XMT_ABO_COL_OV (1L<<12) /* Bit 12: Tx abo dueto Ex Col Ov*/
9778+#define XMT_ABO_COL_OV (1L<<12) /* Bit 12: Tx abo dueto Ex Col Ov */
9779 #define XMT_MUL_COL_OV (1L<<11) /* Bit 11: Tx Mult Col Cnt Ov */
9780 #define XMT_SNG_COL (1L<<10) /* Bit 10: Tx Single Col Cnt Ov */
9781-#define XMT_MCTRL_OV (1L<<9) /* Bit 9: Tx MAC Ctrl Counter Ov*/
9782-#define XMT_MPAUSE (1L<<8) /* Bit 8: Tx Pause MAC Ctrl-F Ov*/
9783+#define XMT_MCTRL_OV (1L<<9) /* Bit 9: Tx MAC Ctrl Counter Ov */
9784+#define XMT_MPAUSE (1L<<8) /* Bit 8: Tx Pause MAC Ctrl-F Ov */
9785 #define XMT_BURST (1L<<7) /* Bit 7: Tx Burst Event Cnt Ov */
9786 #define XMT_LONG (1L<<6) /* Bit 6: Tx Long Frame Cnt Ov */
9787 #define XMT_UC_OK_OV (1L<<5) /* Bit 5: Tx Unicast Cnt Ov */
9788 #define XMT_MC_OK_OV (1L<<4) /* Bit 4: Tx Multicast Cnt Ov */
9789 #define XMT_BC_OK_OV (1L<<3) /* Bit 3: Tx Broadcast Cnt Ov */
9790-#define XMT_OK_LO_OV (1L<<2) /* Bit 2: Octets Tx OK Low CntOv*/
9791-#define XMT_OK_HI_OV (1L<<1) /* Bit 1: Octets Tx OK Hi Cnt Ov*/
9792-#define XMT_OK_OV (1L<<0) /* Bit 0: Frames Tx Ok Ov */
9793+#define XMT_OK_LO_OV (1L<<2) /* Bit 2: Octets Tx OK Low Cnt Ov */
9794+#define XMT_OK_HI_OV (1L<<1) /* Bit 1: Octets Tx OK High Cnt Ov */
9795+#define XMT_OK_OV (1L<<0) /* Bit 0: Frames Tx OK Ov */
9796
9797 #define XMT_DEF_MSK (XMT_OK_LO_OV | XMT_OK_HI_OV)
9798
9799 /*
9800 * Receive Frame Status Encoding
9801 */
9802-#define XMR_FS_LEN (0x3fffUL<<18) /* Bit 31..18: Rx Frame Length */
9803-#define XMR_FS_2L_VLAN (1L<<17) /* Bit 17: tagged wh 2Lev VLAN ID*/
9804-#define XMR_FS_1L_VLAN (1L<<16) /* Bit 16: tagged wh 1Lev VLAN ID*/
9805+#define XMR_FS_LEN_MSK (0x3fffUL<<18) /* Bit 31..18: Rx Frame Length */
9806+#define XMR_FS_2L_VLAN (1L<<17) /* Bit 17: Tagged wh 2Lev VLAN ID */
9807+#define XMR_FS_1L_VLAN (1L<<16) /* Bit 16: Tagged wh 1Lev VLAN ID */
9808 #define XMR_FS_BC (1L<<15) /* Bit 15: Broadcast Frame */
9809 #define XMR_FS_MC (1L<<14) /* Bit 14: Multicast Frame */
9810 #define XMR_FS_UC (1L<<13) /* Bit 13: Unicast Frame */
9811@@ -469,6 +470,8 @@
9812 #define XMR_FS_ERR (1L<<1) /* Bit 1: Frame Error */
9813 #define XMR_FS_MCTRL (1L<<0) /* Bit 0: MAC Control Packet */
9814
9815+#define XMR_FS_LEN_SHIFT 18
9816+
9817 /*
9818 * XMR_FS_ERR will be set if
9819 * XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT,
9820@@ -488,7 +491,7 @@
9821 #define PHY_XMAC_ID0 0x02 /* 16 bit r/o PHY ID0 Register */
9822 #define PHY_XMAC_ID1 0x03 /* 16 bit r/o PHY ID1 Register */
9823 #define PHY_XMAC_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */
9824-#define PHY_XMAC_AUNE_LP 0x05 /* 16 bit r/o Link Partner Abi Reg */
9825+#define PHY_XMAC_AUNE_LP 0x05 /* 16 bit r/o Link Partner Ability Reg */
9826 #define PHY_XMAC_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */
9827 #define PHY_XMAC_NEPG 0x07 /* 16 bit r/w Next Page Register */
9828 #define PHY_XMAC_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */
9829@@ -510,7 +513,7 @@
9830 #define PHY_BCOM_NEPG 0x07 /* 16 bit r/w Next Page Register */
9831 #define PHY_BCOM_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */
9832 /* Broadcom-specific registers */
9833-#define PHY_BCOM_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Ctrl Reg */
9834+#define PHY_BCOM_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */
9835 #define PHY_BCOM_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */
9836 /* 0x0b - 0x0e: reserved */
9837 #define PHY_BCOM_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */
9838@@ -541,24 +544,32 @@
9839 #define PHY_MARV_NEPG 0x07 /* 16 bit r/w Next Page Register */
9840 #define PHY_MARV_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */
9841 /* Marvel-specific registers */
9842-#define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Ctrl Reg */
9843+#define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */
9844 #define PHY_MARV_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */
9845 /* 0x0b - 0x0e: reserved */
9846 #define PHY_MARV_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */
9847-#define PHY_MARV_PHY_CTRL 0x10 /* 16 bit r/w PHY Specific Ctrl Reg */
9848-#define PHY_MARV_PHY_STAT 0x11 /* 16 bit r/o PHY Specific Stat Reg */
9849+#define PHY_MARV_PHY_CTRL 0x10 /* 16 bit r/w PHY Specific Control Reg */
9850+#define PHY_MARV_PHY_STAT 0x11 /* 16 bit r/o PHY Specific Status Reg */
9851 #define PHY_MARV_INT_MASK 0x12 /* 16 bit r/w Interrupt Mask Reg */
9852 #define PHY_MARV_INT_STAT 0x13 /* 16 bit r/o Interrupt Status Reg */
9853 #define PHY_MARV_EXT_CTRL 0x14 /* 16 bit r/w Ext. PHY Specific Ctrl */
9854 #define PHY_MARV_RXE_CNT 0x15 /* 16 bit r/w Receive Error Counter */
9855 #define PHY_MARV_EXT_ADR 0x16 /* 16 bit r/w Ext. Ad. for Cable Diag. */
9856- /* 0x17: reserved */
9857+#define PHY_MARV_PORT_IRQ 0x17 /* 16 bit r/o Port 0 IRQ (88E1111 only) */
9858 #define PHY_MARV_LED_CTRL 0x18 /* 16 bit r/w LED Control Reg */
9859 #define PHY_MARV_LED_OVER 0x19 /* 16 bit r/w Manual LED Override Reg */
9860 #define PHY_MARV_EXT_CTRL_2 0x1a /* 16 bit r/w Ext. PHY Specific Ctrl 2 */
9861 #define PHY_MARV_EXT_P_STAT 0x1b /* 16 bit r/w Ext. PHY Spec. Stat Reg */
9862 #define PHY_MARV_CABLE_DIAG 0x1c /* 16 bit r/o Cable Diagnostic Reg */
9863- /* 0x1d - 0x1f: reserved */
9864+#define PHY_MARV_PAGE_ADDR 0x1d /* 16 bit r/w Extended Page Address Reg */
9865+#define PHY_MARV_PAGE_DATA 0x1e /* 16 bit r/w Extended Page Data Reg */
9866+
9867+/* for 10/100 Fast Ethernet PHY (88E3082 only) */
9868+#define PHY_MARV_FE_LED_PAR 0x16 /* 16 bit r/w LED Parallel Select Reg. */
9869+#define PHY_MARV_FE_LED_SER 0x17 /* 16 bit r/w LED Stream Select S. LED */
9870+#define PHY_MARV_FE_VCT_TX 0x1a /* 16 bit r/w VCT Reg. for TXP/N Pins */
9871+#define PHY_MARV_FE_VCT_RX 0x1b /* 16 bit r/o VCT Reg. for RXP/N Pins */
9872+#define PHY_MARV_FE_SPEC_2 0x1c /* 16 bit r/w Specific Control Reg. 2 */
9873
9874 /*----------------------------------------------------------------------------*/
9875 /*
9876@@ -574,9 +585,9 @@
9877 #define PHY_LONE_NEPG 0x07 /* 16 bit r/w Next Page Register */
9878 #define PHY_LONE_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */
9879 /* Level One-specific registers */
9880-#define PHY_LONE_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg*/
9881+#define PHY_LONE_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */
9882 #define PHY_LONE_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */
9883- /* 0x0b -0x0e: reserved */
9884+ /* 0x0b - 0x0e: reserved */
9885 #define PHY_LONE_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */
9886 #define PHY_LONE_PORT_CFG 0x10 /* 16 bit r/w Port Configuration Reg*/
9887 #define PHY_LONE_Q_STAT 0x11 /* 16 bit r/o Quick Status Reg */
9888@@ -585,7 +596,7 @@
9889 #define PHY_LONE_LED_CFG 0x14 /* 16 bit r/w LED Configuration Reg */
9890 #define PHY_LONE_PORT_CTRL 0x15 /* 16 bit r/w Port Control Reg */
9891 #define PHY_LONE_CIM 0x16 /* 16 bit r/o CIM Reg */
9892- /* 0x17 -0x1c: reserved */
9893+ /* 0x17 - 0x1c: reserved */
9894
9895 /*----------------------------------------------------------------------------*/
9896 /*
9897@@ -603,14 +614,14 @@
9898 /* National-specific registers */
9899 #define PHY_NAT_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */
9900 #define PHY_NAT_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */
9901- /* 0x0b -0x0e: reserved */
9902+ /* 0x0b - 0x0e: reserved */
9903 #define PHY_NAT_EXT_STAT 0x0f /* 16 bit r/o Extended Status Register */
9904 #define PHY_NAT_EXT_CTRL1 0x10 /* 16 bit r/o Extended Control Reg1 */
9905 #define PHY_NAT_Q_STAT1 0x11 /* 16 bit r/o Quick Status Reg1 */
9906 #define PHY_NAT_10B_OP 0x12 /* 16 bit r/o 10Base-T Operations Reg */
9907 #define PHY_NAT_EXT_CTRL2 0x13 /* 16 bit r/o Extended Control Reg1 */
9908 #define PHY_NAT_Q_STAT2 0x14 /* 16 bit r/o Quick Status Reg2 */
9909- /* 0x15 -0x18: reserved */
9910+ /* 0x15 - 0x18: reserved */
9911 #define PHY_NAT_PHY_ADDR 0x19 /* 16 bit r/o PHY Address Register */
9912
9913
9914@@ -618,7 +629,7 @@
9915
9916 /*
9917 * PHY bit definitions
9918- * Bits defined as PHY_X_..., PHY_B_..., PHY_L_... or PHY_N_... are
9919+ * Bits defined as PHY_X_..., PHY_B_..., PHY_L_..., PHY_N_... or PHY_M_... are
9920 * XMAC/Broadcom/LevelOne/National/Marvell-specific.
9921 * All other are general.
9922 */
9923@@ -629,14 +640,14 @@
9924 /***** PHY_LONE_CTRL 16 bit r/w PHY Control Register *****/
9925 #define PHY_CT_RESET (1<<15) /* Bit 15: (sc) clear all PHY related regs */
9926 #define PHY_CT_LOOP (1<<14) /* Bit 14: enable Loopback over PHY */
9927-#define PHY_CT_SPS_LSB (1<<13) /* Bit 13: (BC,L1) Speed select, lower bit */
9928+#define PHY_CT_SPS_LSB (1<<13) /* Bit 13: Speed select, lower bit */
9929 #define PHY_CT_ANE (1<<12) /* Bit 12: Auto-Negotiation Enabled */
9930-#define PHY_CT_PDOWN (1<<11) /* Bit 11: (BC,L1) Power Down Mode */
9931-#define PHY_CT_ISOL (1<<10) /* Bit 10: (BC,L1) Isolate Mode */
9932-#define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Auto-Negotiation */
9933+#define PHY_CT_PDOWN (1<<11) /* Bit 11: Power Down Mode */
9934+#define PHY_CT_ISOL (1<<10) /* Bit 10: Isolate Mode */
9935+#define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Auto-Negotiation */
9936 #define PHY_CT_DUP_MD (1<<8) /* Bit 8: Duplex Mode */
9937-#define PHY_CT_COL_TST (1<<7) /* Bit 7: (BC,L1) Collision Test enabled */
9938-#define PHY_CT_SPS_MSB (1<<6) /* Bit 6: (BC,L1) Speed select, upper bit */
9939+#define PHY_CT_COL_TST (1<<7) /* Bit 7: Collision Test enabled */
9940+#define PHY_CT_SPS_MSB (1<<6) /* Bit 6: Speed select, upper bit */
9941 /* Bit 5..0: reserved */
9942
9943 #define PHY_CT_SP1000 PHY_CT_SPS_MSB /* enable speed of 1000 Mbps */
9944@@ -649,25 +660,25 @@
9945 /***** PHY_MARV_STAT 16 bit r/w PHY Status Register *****/
9946 /***** PHY_LONE_STAT 16 bit r/w PHY Status Register *****/
9947 /* Bit 15..9: reserved */
9948- /* (BC/L1) 100/10 Mbps cap bits ignored*/
9949+ /* (BC/L1) 100/10 Mbps cap bits ignored */
9950 #define PHY_ST_EXT_ST (1<<8) /* Bit 8: Extended Status Present */
9951 /* Bit 7: reserved */
9952-#define PHY_ST_PRE_SUP (1<<6) /* Bit 6: (BC/L1) preamble suppression */
9953+#define PHY_ST_PRE_SUP (1<<6) /* Bit 6: Preamble Suppression */
9954 #define PHY_ST_AN_OVER (1<<5) /* Bit 5: Auto-Negotiation Over */
9955 #define PHY_ST_REM_FLT (1<<4) /* Bit 4: Remote Fault Condition Occured */
9956 #define PHY_ST_AN_CAP (1<<3) /* Bit 3: Auto-Negotiation Capability */
9957 #define PHY_ST_LSYNC (1<<2) /* Bit 2: Link Synchronized */
9958-#define PHY_ST_JAB_DET (1<<1) /* Bit 1: (BC/L1) Jabber Detected */
9959+#define PHY_ST_JAB_DET (1<<1) /* Bit 1: Jabber Detected */
9960 #define PHY_ST_EXT_REG (1<<0) /* Bit 0: Extended Register available */
9961
9962
9963-/***** PHY_XMAC_ID1 16 bit r/o PHY ID1 Register */
9964-/***** PHY_BCOM_ID1 16 bit r/o PHY ID1 Register */
9965-/***** PHY_MARV_ID1 16 bit r/o PHY ID1 Register */
9966-/***** PHY_LONE_ID1 16 bit r/o PHY ID1 Register */
9967+/***** PHY_XMAC_ID1 16 bit r/o PHY ID1 Register */
9968+/***** PHY_BCOM_ID1 16 bit r/o PHY ID1 Register */
9969+/***** PHY_MARV_ID1 16 bit r/o PHY ID1 Register */
9970+/***** PHY_LONE_ID1 16 bit r/o PHY ID1 Register */
9971 #define PHY_I1_OUI_MSK (0x3f<<10) /* Bit 15..10: Organization Unique ID */
9972 #define PHY_I1_MOD_NUM (0x3f<<4) /* Bit 9.. 4: Model Number */
9973-#define PHY_I1_REV_MSK 0x0f /* Bit 3.. 0: Revision Number */
9974+#define PHY_I1_REV_MSK 0xf /* Bit 3.. 0: Revision Number */
9975
9976 /* different Broadcom PHY Ids */
9977 #define PHY_BCOM_ID1_A1 0x6041
9978@@ -675,11 +686,21 @@
9979 #define PHY_BCOM_ID1_C0 0x6044
9980 #define PHY_BCOM_ID1_C5 0x6047
9981
9982+/* different Marvell PHY Ids */
9983+#define PHY_MARV_ID0_VAL 0x0141 /* Marvell Unique Identifier */
9984+
9985+#define PHY_MARV_ID1_B0 0x0C23 /* Yukon (PHY 88E1040 Rev.C0) */
9986+#define PHY_MARV_ID1_B2 0x0C25 /* Yukon-Plus (PHY 88E1040 Rev.D0) */
9987+#define PHY_MARV_ID1_C2 0x0CC2 /* Yukon-EC (PHY 88E1111 Rev.B1) */
9988+#define PHY_MARV_ID1_Y2 0x0C91 /* Yukon-XL (PHY 88E1112 Rev.B0) */
9989+#define PHY_MARV_ID1_FE 0x0C83 /* Yukon-FE (PHY 88E3082 Rev.A1) */
9990+#define PHY_MARV_ID1_ECU 0x0CB0 /* Yukon-ECU (PHY 88E1149 Rev.B2?) */
9991+
9992
9993 /***** PHY_XMAC_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
9994 /***** PHY_XMAC_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/
9995 #define PHY_AN_NXT_PG (1<<15) /* Bit 15: Request Next Page */
9996-#define PHY_X_AN_ACK (1<<14) /* Bit 14: (ro) Acknowledge Received */
9997+#define PHY_X_AN_ACK (1<<14) /* Bit 14: (ro) Acknowledge Received */
9998 #define PHY_X_AN_RFB (3<<12) /* Bit 13..12: Remote Fault Bits */
9999 /* Bit 11.. 9: reserved */
10000 #define PHY_X_AN_PAUSE (3<<7) /* Bit 8.. 7: Pause Bits */
10001@@ -827,7 +848,7 @@
10002 #define PHY_B_PEC_BY_MLT3 (1<<8) /* Bit 8: Bypass MLT3 Encoder */
10003 #define PHY_B_PEC_BY_RXA (1<<7) /* Bit 7: Bypass Rx Alignm. */
10004 #define PHY_B_PEC_RES_SCR (1<<6) /* Bit 6: Reset Scrambler */
10005-#define PHY_B_PEC_EN_LTR (1<<5) /* Bit 5: Ena LED Traffic Mode */
10006+#define PHY_B_PEC_EN_LTR (1<<5) /* Bit 5: Enable LED Traffic Mode */
10007 #define PHY_B_PEC_LED_ON (1<<4) /* Bit 4: Force LED's on */
10008 #define PHY_B_PEC_LED_OFF (1<<3) /* Bit 3: Force LED's off */
10009 #define PHY_B_PEC_EX_IPG (1<<2) /* Bit 2: Extend Tx IPG Mode */
10010@@ -981,7 +1002,7 @@
10011 #define PHY_L_QS_DUP_MOD (1<<9) /* Bit 9: Full/Half Duplex */
10012 #define PHY_L_QS_AN (1<<8) /* Bit 8: AutoNeg is On */
10013 #define PHY_L_QS_AN_C (1<<7) /* Bit 7: AN is Complete */
10014-#define PHY_L_QS_LLE (7<<4) /* Bit 6: Line Length Estim. */
10015+#define PHY_L_QS_LLE (7<<4) /* Bit 6..4: Line Length Estim. */
10016 #define PHY_L_QS_PAUSE (1<<3) /* Bit 3: LP advertised Pause */
10017 #define PHY_L_QS_AS_PAUSE (1<<2) /* Bit 2: LP adv. asym. Pause */
10018 #define PHY_L_QS_ISOLATE (1<<1) /* Bit 1: CIM Isolated */
10019@@ -1029,9 +1050,8 @@
10020 /* Bit 9..0: not described */
10021
10022 /***** PHY_LONE_CIM 16 bit r/o CIM Reg *****/
10023-#define PHY_L_CIM_ISOL (255<<8)/* Bit 15..8: Isolate Count */
10024-#define PHY_L_CIM_FALSE_CAR (255<<0)/* Bit 7..0: False Carrier Count */
10025-
10026+#define PHY_L_CIM_ISOL (0xff<<8) /* Bit 15..8: Isolate Count */
10027+#define PHY_L_CIM_FALSE_CAR 0xff /* Bit 7..0: False Carrier Count */
10028
10029 /*
10030 * Pause Bits (PHY_L_AN_ASP and PHY_L_AN_PC) encoding
10031@@ -1041,7 +1061,6 @@
10032 #define PHY_L_P_ASYM_MD (2<<10) /* Bit 11..10: asymmetric Pause Mode */
10033 #define PHY_L_P_BOTH_MD (3<<10) /* Bit 11..10: both Pause Mode */
10034
10035-
10036 /*
10037 * National-Specific
10038 */
10039@@ -1086,22 +1105,24 @@
10040 */
10041 /***** PHY_MARV_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
10042 /***** PHY_MARV_AUNE_LP 16 bit r/w Link Part Ability Reg *****/
10043-#define PHY_M_AN_NXT_PG BIT_15 /* Request Next Page */
10044-#define PHY_M_AN_ACK BIT_14 /* (ro) Acknowledge Received */
10045-#define PHY_M_AN_RF BIT_13 /* Remote Fault */
10046- /* Bit 12: reserved */
10047-#define PHY_M_AN_ASP BIT_11 /* Asymmetric Pause */
10048-#define PHY_M_AN_PC BIT_10 /* MAC Pause implemented */
10049-#define PHY_M_AN_100_FD BIT_8 /* Advertise 100Base-TX Full Duplex */
10050-#define PHY_M_AN_100_HD BIT_7 /* Advertise 100Base-TX Half Duplex */
10051-#define PHY_M_AN_10_FD BIT_6 /* Advertise 10Base-TX Full Duplex */
10052-#define PHY_M_AN_10_HD BIT_5 /* Advertise 10Base-TX Half Duplex */
10053-
10054-/* special defines for FIBER (88E1011S only) */
10055-#define PHY_M_AN_ASP_X BIT_8 /* Asymmetric Pause */
10056-#define PHY_M_AN_PC_X BIT_7 /* MAC Pause implemented */
10057-#define PHY_M_AN_1000X_AHD BIT_6 /* Advertise 10000Base-X Half Duplex */
10058-#define PHY_M_AN_1000X_AFD BIT_5 /* Advertise 10000Base-X Full Duplex */
10059+#define PHY_M_AN_NXT_PG BIT_15S /* Request Next Page */
10060+#define PHY_M_AN_ACK BIT_14S /* (ro) Acknowledge Received */
10061+#define PHY_M_AN_RF BIT_13S /* Remote Fault */
10062+ /* Bit 12: reserved */
10063+#define PHY_M_AN_ASP BIT_11S /* Asymmetric Pause */
10064+#define PHY_M_AN_PC BIT_10S /* MAC Pause implemented */
10065+#define PHY_M_AN_100_T4 BIT_9S /* Not cap. 100Base-T4 (always 0) */
10066+#define PHY_M_AN_100_FD BIT_8S /* Advertise 100Base-TX Full Duplex */
10067+#define PHY_M_AN_100_HD BIT_7S /* Advertise 100Base-TX Half Duplex */
10068+#define PHY_M_AN_10_FD BIT_6S /* Advertise 10Base-TX Full Duplex */
10069+#define PHY_M_AN_10_HD BIT_5S /* Advertise 10Base-TX Half Duplex */
10070+#define PHY_M_AN_SEL_MSK (0x1f<<4) /* Bit 4.. 0: Selector Field Mask */
10071+
10072+/* special defines for FIBER (88E1040S only) */
10073+#define PHY_M_AN_ASP_X BIT_8S /* Asymmetric Pause */
10074+#define PHY_M_AN_PC_X BIT_7S /* MAC Pause implemented */
10075+#define PHY_M_AN_1000X_AHD BIT_6S /* Advertise 10000Base-X Half Duplex */
10076+#define PHY_M_AN_1000X_AFD BIT_5S /* Advertise 10000Base-X Full Duplex */
10077
10078 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
10079 #define PHY_M_P_NO_PAUSE_X (0<<7) /* Bit 8.. 7: no Pause Mode */
10080@@ -1111,105 +1132,167 @@
10081
10082 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
10083 #define PHY_M_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */
10084-#define PHY_M_1000C_MSE (1<<12) /* Bit 12: Manual Master/Slave Enable */
10085-#define PHY_M_1000C_MSC (1<<11) /* Bit 11: M/S Configuration (1=Master) */
10086-#define PHY_M_1000C_MPD (1<<10) /* Bit 10: Multi-Port Device */
10087-#define PHY_M_1000C_AFD (1<<9) /* Bit 9: Advertise Full Duplex */
10088-#define PHY_M_1000C_AHD (1<<8) /* Bit 8: Advertise Half Duplex */
10089+#define PHY_M_1000C_MSE BIT_12S /* Manual Master/Slave Enable */
10090+#define PHY_M_1000C_MSC BIT_11S /* M/S Configuration (1=Master) */
10091+#define PHY_M_1000C_MPD BIT_10S /* Multi-Port Device */
10092+#define PHY_M_1000C_AFD BIT_9S /* Advertise Full Duplex */
10093+#define PHY_M_1000C_AHD BIT_8S /* Advertise Half Duplex */
10094 /* Bit 7..0: reserved */
10095
10096 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
10097-#define PHY_M_PC_TX_FFD_MSK (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */
10098-#define PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */
10099-#define PHY_M_PC_ASS_CRS_TX (1<<11) /* Bit 11: Assert CRS on Transmit */
10100-#define PHY_M_PC_FL_GOOD (1<<10) /* Bit 10: Force Link Good */
10101-#define PHY_M_PC_EN_DET_MSK (3<<8) /* Bit 9.. 8: Energy Detect Mask */
10102-#define PHY_M_PC_ENA_EXT_D (1<<7) /* Bit 7: Enable Ext. Distance (10BT) */
10103-#define PHY_M_PC_MDIX_MSK (3<<5) /* Bit 6.. 5: MDI/MDIX Config. Mask */
10104-#define PHY_M_PC_DIS_125CLK (1<<4) /* Bit 4: Disable 125 CLK */
10105-#define PHY_M_PC_MAC_POW_UP (1<<3) /* Bit 3: MAC Power up */
10106-#define PHY_M_PC_SQE_T_ENA (1<<2) /* Bit 2: SQE Test Enabled */
10107-#define PHY_M_PC_POL_R_DIS (1<<1) /* Bit 1: Polarity Reversal Disabled */
10108-#define PHY_M_PC_DIS_JABBER (1<<0) /* Bit 0: Disable Jabber */
10109+#define PHY_M_PC_TX_FFD_MSK (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */
10110+#define PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */
10111+#define PHY_M_PC_ASS_CRS_TX BIT_11S /* Assert CRS on Transmit */
10112+#define PHY_M_PC_FL_GOOD BIT_10S /* Force Link Good */
10113+#define PHY_M_PC_EN_DET_MSK (3<<8) /* Bit 9.. 8: Energy Detect Mask */
10114+#define PHY_M_PC_ENA_EXT_D BIT_7S /* Enable Ext. Distance (10BT) */
10115+#define PHY_M_PC_MDIX_MSK (3<<5) /* Bit 6.. 5: MDI/MDIX Config. Mask */
10116+#define PHY_M_PC_DIS_125CLK BIT_4S /* Disable 125 CLK */
10117+#define PHY_M_PC_MAC_POW_UP BIT_3S /* MAC Power up */
10118+#define PHY_M_PC_SQE_T_ENA BIT_2S /* SQE Test Enabled */
10119+#define PHY_M_PC_POL_R_DIS BIT_1S /* Polarity Reversal Disabled */
10120+#define PHY_M_PC_DIS_JABBER BIT_0S /* Disable Jabber */
10121
10122 #define PHY_M_PC_EN_DET SHIFT8(2) /* Energy Detect (Mode 1) */
10123 #define PHY_M_PC_EN_DET_PLUS SHIFT8(3) /* Energy Detect Plus (Mode 2) */
10124
10125-#define PHY_M_PC_MDI_XMODE(x) SHIFT5(x)
10126-#define PHY_M_PC_MAN_MDI 0 /* 00 = Manual MDI configuration */
10127+#define PHY_M_PC_MDI_XMODE(x) (SHIFT5(x) & PHY_M_PC_MDIX_MSK)
10128+
10129+#define PHY_M_PC_MAN_MDI 0 /* 00 = Manual MDI configuration */
10130 #define PHY_M_PC_MAN_MDIX 1 /* 01 = Manual MDIX configuration */
10131 #define PHY_M_PC_ENA_AUTO 3 /* 11 = Enable Automatic Crossover */
10132
10133+/* for Yukon-2/-EC Ultra Gigabit Ethernet PHY (88E1112/88E1149 only) */
10134+#define PHY_M_PC_DIS_LINK_P BIT_15S /* Disable Link Pulses */
10135+#define PHY_M_PC_DSC_MSK (7<<12) /* Bit 14..12: Downshift Counter */
10136+#define PHY_M_PC_DOWN_S_ENA BIT_11S /* Downshift Enable */
10137+ /* !!! Errata in spec. (1 = disable) */
10138+
10139+#define PHY_M_PC_DSC(x) (SHIFT12(x) & PHY_M_PC_DSC_MSK)
10140+ /* 000=1x; 001=2x; 010=3x; 011=4x */
10141+ /* 100=5x; 101=6x; 110=7x; 111=8x */
10142+
10143+/* for Yukon-EC Ultra Gigabit Ethernet PHY (88E1149 only) */
10144+ /* Bit 4: reserved */
10145+#define PHY_M_PC_COP_TX_DIS BIT_3S /* Copper Transmitter Disable */
10146+#define PHY_M_PC_POW_D_ENA BIT_2S /* Power Down Enable */
10147+
10148+/* for 10/100 Fast Ethernet PHY (88E3082 only) */
10149+#define PHY_M_PC_ENA_DTE_DT BIT_15S /* Enable Data Terminal Equ. (DTE) Detect */
10150+#define PHY_M_PC_ENA_ENE_DT BIT_14S /* Enable Energy Detect (sense & pulse) */
10151+#define PHY_M_PC_DIS_NLP_CK BIT_13S /* Disable Normal Link Puls (NLP) Check */
10152+#define PHY_M_PC_ENA_LIP_NP BIT_12S /* Enable Link Partner Next Page Reg. */
10153+#define PHY_M_PC_DIS_NLP_GN BIT_11S /* Disable Normal Link Puls Generation */
10154+
10155+#define PHY_M_PC_DIS_SCRAMB BIT_9S /* Disable Scrambler */
10156+#define PHY_M_PC_DIS_FEFI BIT_8S /* Disable Far End Fault Indic. (FEFI) */
10157+
10158+#define PHY_M_PC_SH_TP_SEL BIT_6S /* Shielded Twisted Pair Select */
10159+#define PHY_M_PC_RX_FD_MSK (3<<2) /* Bit 3.. 2: Rx FIFO Depth Mask */
10160+
10161 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
10162-#define PHY_M_PS_SPEED_MSK (3<<14) /* Bit 15..14: Speed Mask */
10163-#define PHY_M_PS_SPEED_1000 (1<<15) /* 10 = 1000 Mbps */
10164-#define PHY_M_PS_SPEED_100 (1<<14) /* 01 = 100 Mbps */
10165-#define PHY_M_PS_SPEED_10 0 /* 00 = 10 Mbps */
10166-#define PHY_M_PS_FULL_DUP (1<<13) /* Bit 13: Full Duplex */
10167-#define PHY_M_PS_PAGE_REC (1<<12) /* Bit 12: Page Received */
10168-#define PHY_M_PS_SPDUP_RES (1<<11) /* Bit 11: Speed & Duplex Resolved */
10169-#define PHY_M_PS_LINK_UP (1<<10) /* Bit 10: Link Up */
10170-#define PHY_M_PS_CABLE_MSK (3<<7) /* Bit 9.. 7: Cable Length Mask */
10171-#define PHY_M_PS_MDI_X_STAT (1<<6) /* Bit 6: MDI Crossover Stat (1=MDIX) */
10172-#define PHY_M_PS_DOWNS_STAT (1<<5) /* Bit 5: Downshift Status (1=downsh.) */
10173-#define PHY_M_PS_ENDET_STAT (1<<4) /* Bit 4: Energy Detect Status (1=act) */
10174-#define PHY_M_PS_TX_P_EN (1<<3) /* Bit 3: Tx Pause Enabled */
10175-#define PHY_M_PS_RX_P_EN (1<<2) /* Bit 2: Rx Pause Enabled */
10176-#define PHY_M_PS_POL_REV (1<<1) /* Bit 1: Polarity Reversed */
10177-#define PHY_M_PC_JABBER (1<<0) /* Bit 0: Jabber */
10178+#define PHY_M_PS_SPEED_MSK (3<<14) /* Bit 15..14: Speed Mask */
10179+#define PHY_M_PS_SPEED_1000 BIT_15S /* 10 = 1000 Mbps */
10180+#define PHY_M_PS_SPEED_100 BIT_14S /* 01 = 100 Mbps */
10181+#define PHY_M_PS_SPEED_10 0 /* 00 = 10 Mbps */
10182+#define PHY_M_PS_FULL_DUP BIT_13S /* Full Duplex */
10183+#define PHY_M_PS_PAGE_REC BIT_12S /* Page Received */
10184+#define PHY_M_PS_SPDUP_RES BIT_11S /* Speed & Duplex Resolved */
10185+#define PHY_M_PS_LINK_UP BIT_10S /* Link Up */
10186+#define PHY_M_PS_CABLE_MSK (7<<7) /* Bit 9.. 7: Cable Length Mask */
10187+#define PHY_M_PS_MDI_X_STAT BIT_6S /* MDI Crossover Stat (1=MDIX) */
10188+#define PHY_M_PS_DOWNS_STAT BIT_5S /* Downshift Status (1=downsh.) */
10189+#define PHY_M_PS_ENDET_STAT BIT_4S /* Energy Detect Status (1=act) */
10190+#define PHY_M_PS_TX_P_EN BIT_3S /* Tx Pause Enabled */
10191+#define PHY_M_PS_RX_P_EN BIT_2S /* Rx Pause Enabled */
10192+#define PHY_M_PS_POL_REV BIT_1S /* Polarity Reversed */
10193+#define PHY_M_PS_JABBER BIT_0S /* Jabber */
10194
10195 #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
10196
10197+/* for 10/100 Fast Ethernet PHY (88E3082 only) */
10198+#define PHY_M_PS_DTE_DETECT BIT_15S /* Data Terminal Equipment (DTE) Detected */
10199+#define PHY_M_PS_RES_SPEED BIT_14S /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
10200+
10201 /***** PHY_MARV_INT_MASK 16 bit r/w Interrupt Mask Reg *****/
10202 /***** PHY_MARV_INT_STAT 16 bit r/o Interrupt Status Reg *****/
10203-#define PHY_M_IS_AN_ERROR (1<<15) /* Bit 15: Auto-Negotiation Error */
10204-#define PHY_M_IS_LSP_CHANGE (1<<14) /* Bit 14: Link Speed Changed */
10205-#define PHY_M_IS_DUP_CHANGE (1<<13) /* Bit 13: Duplex Mode Changed */
10206-#define PHY_M_IS_AN_PR (1<<12) /* Bit 12: Page Received */
10207-#define PHY_M_IS_AN_COMPL (1<<11) /* Bit 11: Auto-Negotiation Completed */
10208-#define PHY_M_IS_LST_CHANGE (1<<10) /* Bit 10: Link Status Changed */
10209-#define PHY_M_IS_SYMB_ERROR (1<<9) /* Bit 9: Symbol Error */
10210-#define PHY_M_IS_FALSE_CARR (1<<8) /* Bit 8: False Carrier */
10211-#define PHY_M_IS_FIFO_ERROR (1<<7) /* Bit 7: FIFO Overflow/Underrun Error */
10212-#define PHY_M_IS_MDI_CHANGE (1<<6) /* Bit 6: MDI Crossover Changed */
10213-#define PHY_M_IS_DOWNSH_DET (1<<5) /* Bit 5: Downshift Detected */
10214-#define PHY_M_IS_END_CHANGE (1<<4) /* Bit 4: Energy Detect Changed */
10215- /* Bit 3..2: reserved */
10216-#define PHY_M_IS_POL_CHANGE (1<<1) /* Bit 1: Polarity Changed */
10217-#define PHY_M_IS_JABBER (1<<0) /* Bit 0: Jabber */
10218+#define PHY_M_IS_AN_ERROR BIT_15S /* Auto-Negotiation Error */
10219+#define PHY_M_IS_LSP_CHANGE BIT_14S /* Link Speed Changed */
10220+#define PHY_M_IS_DUP_CHANGE BIT_13S /* Duplex Mode Changed */
10221+#define PHY_M_IS_AN_PR BIT_12S /* Page Received */
10222+#define PHY_M_IS_AN_COMPL BIT_11S /* Auto-Negotiation Completed */
10223+#define PHY_M_IS_LST_CHANGE BIT_10S /* Link Status Changed */
10224+#define PHY_M_IS_SYMB_ERROR BIT_9S /* Symbol Error */
10225+#define PHY_M_IS_FALSE_CARR BIT_8S /* False Carrier */
10226+#define PHY_M_IS_FIFO_ERROR BIT_7S /* FIFO Overflow/Underrun Error */
10227+#define PHY_M_IS_MDI_CHANGE BIT_6S /* MDI Crossover Changed */
10228+#define PHY_M_IS_DOWNSH_DET BIT_5S /* Downshift Detected */
10229+#define PHY_M_IS_END_CHANGE BIT_4S /* Energy Detect Changed */
10230+ /* Bit 3: reserved */
10231+#define PHY_M_IS_DTE_CHANGE BIT_2S /* DTE Power Det. Status Changed */
10232+ /* (88E1111 only) */
10233+#define PHY_M_IS_POL_CHANGE BIT_1S /* Polarity Changed */
10234+#define PHY_M_IS_JABBER BIT_0S /* Jabber */
10235
10236 #define PHY_M_DEF_MSK (PHY_M_IS_AN_ERROR | PHY_M_IS_AN_PR | \
10237 PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR)
10238
10239 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
10240-#define PHY_M_EC_M_DSC_MSK (3<<10) /* Bit 11..10: Master downshift counter */
10241-#define PHY_M_EC_S_DSC_MSK (3<<8) /* Bit 9.. 8: Slave downshift counter */
10242+#define PHY_M_EC_ENA_BC_EXT BIT_15S /* Enable Block Carr. Ext. (88E1111 only) */
10243+#define PHY_M_EC_ENA_LIN_LB BIT_14S /* Enable Line Loopback (88E1111 only) */
10244+ /* Bit 13: reserved */
10245+#define PHY_M_EC_DIS_LINK_P BIT_12S /* Disable Link Pulses (88E1111 only) */
10246+#define PHY_M_EC_M_DSC_MSK (3<<10) /* Bit 11..10: Master Downshift Counter */
10247+ /* (88E1040 Rev.C0 only) */
10248+#define PHY_M_EC_S_DSC_MSK (3<<8) /* Bit 9.. 8: Slave Downshift Counter */
10249+ /* (88E1040 Rev.C0 only) */
10250+#define PHY_M_EC_DSC_MSK_2 (7<<9) /* Bit 11.. 9: Downshift Counter */
10251+ /* (88E1040 Rev.D0 and higher) */
10252+#define PHY_M_EC_DOWN_S_ENA BIT_8S /* Downshift Enable (88E1040 Rev.D0 and */
10253+ /* 88E1111 !!! Errata in spec. (1=dis.) */
10254+#define PHY_M_EC_RX_TIM_CT BIT_7S /* RGMII Rx Timing Control*/
10255 #define PHY_M_EC_MAC_S_MSK (7<<4) /* Bit 6.. 4: Def. MAC interface speed */
10256-#define PHY_M_EC_FIB_AN_ENA (1<<3) /* Bit 3: Fiber Auto-Neg. Enable */
10257-
10258-#define PHY_M_EC_M_DSC(x) SHIFT10(x) /* 00=1x; 01=2x; 10=3x; 11=4x */
10259-#define PHY_M_EC_S_DSC(x) SHIFT8(x) /* 00=dis; 01=1x; 10=2x; 11=3x */
10260-#define PHY_M_EC_MAC_S(x) SHIFT4(x) /* 01X=0; 110=2.5; 111=25 (MHz) */
10261-
10262+#define PHY_M_EC_FIB_AN_ENA BIT_3S /* Fiber Auto-Neg. Enable 88E1040S only) */
10263+#define PHY_M_EC_DTE_D_ENA BIT_2S /* DTE Detect Enable (88E1111 only) */
10264+#define PHY_M_EC_TX_TIM_CT BIT_1S /* RGMII Tx Timing Control */
10265+#define PHY_M_EC_TRANS_DIS BIT_0S /* Transmitter Disable (88E1111 only) */
10266+
10267+#define PHY_M_EC_M_DSC(x) (SHIFT10(x) & PHY_M_EC_M_DSC_MSK)
10268+ /* 00=1x; 01=2x; 10=3x; 11=4x */
10269+#define PHY_M_EC_S_DSC(x) (SHIFT8(x) & PHY_M_EC_S_DSC_MSK)
10270+ /* 00=dis; 01=1x; 10=2x; 11=3x */
10271+#define PHY_M_EC_MAC_S(x) (SHIFT4(x) & PHY_M_EC_MAC_S_MSK)
10272+ /* 01X=0; 110=2.5; 111=25 (MHz) */
10273+
10274+#define PHY_M_EC_DSC_2(x) (SHIFT9(x) & PHY_M_EC_DSC_MSK_2)
10275+ /* 000=1x; 001=2x; 010=3x; 011=4x */
10276+ /* 100=5x; 101=6x; 110=7x; 111=8x */
10277 #define MAC_TX_CLK_0_MHZ 2
10278 #define MAC_TX_CLK_2_5_MHZ 6
10279 #define MAC_TX_CLK_25_MHZ 7
10280
10281 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
10282-#define PHY_M_LEDC_DIS_LED (1<<15) /* Bit 15: Disable LED */
10283-#define PHY_M_LEDC_PULS_MSK (7<<12) /* Bit 14..12: Pulse Stretch Mask */
10284-#define PHY_M_LEDC_F_INT (1<<11) /* Bit 11: Force Interrupt */
10285-#define PHY_M_LEDC_BL_R_MSK (7<<8) /* Bit 10.. 8: Blink Rate Mask */
10286- /* Bit 7.. 5: reserved */
10287-#define PHY_M_LEDC_LINK_MSK (3<<3) /* Bit 4.. 3: Link Control Mask */
10288-#define PHY_M_LEDC_DP_CTRL (1<<2) /* Bit 2: Duplex Control */
10289-#define PHY_M_LEDC_RX_CTRL (1<<1) /* Bit 1: Rx activity / Link */
10290-#define PHY_M_LEDC_TX_CTRL (1<<0) /* Bit 0: Tx activity / Link */
10291+#define PHY_M_LEDC_DIS_LED BIT_15S /* Disable LED */
10292+#define PHY_M_LEDC_PULS_MSK (7<<12) /* Bit 14..12: Pulse Stretch Mask */
10293+#define PHY_M_LEDC_F_INT BIT_11S /* Force Interrupt */
10294+#define PHY_M_LEDC_BL_R_MSK (7<<8) /* Bit 10.. 8: Blink Rate Mask */
10295+#define PHY_M_LEDC_DP_C_LSB BIT_7S /* Duplex Control (LSB, 88E1111 only) */
10296+#define PHY_M_LEDC_TX_C_LSB BIT_6S /* Tx Control (LSB, 88E1111 only) */
10297+#define PHY_M_LEDC_LK_C_MSK (7<<3) /* Bit 5.. 3: Link Control Mask */
10298+ /* (88E1111 only) */
10299+ /* Bit 7.. 5: reserved (88E1040 only) */
10300+#define PHY_M_LEDC_LINK_MSK (3<<3) /* Bit 4.. 3: Link Control Mask */
10301+ /* (88E1040 only) */
10302+#define PHY_M_LEDC_DP_CTRL BIT_2S /* Duplex Control */
10303+#define PHY_M_LEDC_DP_C_MSB BIT_2S /* Duplex Control (MSB, 88E1111 only) */
10304+#define PHY_M_LEDC_RX_CTRL BIT_1S /* Rx Activity / Link */
10305+#define PHY_M_LEDC_TX_CTRL BIT_0S /* Tx Activity / Link */
10306+#define PHY_M_LEDC_TX_C_MSB BIT_0S /* Tx Control (MSB, 88E1111 only) */
10307
10308-#define PHY_M_LED_PULS_DUR(x) SHIFT12(x) /* Pulse Stretch Duration */
10309+#define PHY_M_LED_PULS_DUR(x) (SHIFT12(x) & PHY_M_LEDC_PULS_MSK)
10310
10311-#define PULS_NO_STR 0 /* no pulse stretching */
10312-#define PULS_21MS 1 /* 21 ms to 42 ms */
10313+#define PULS_NO_STR 0 /* no pulse stretching */
10314+#define PULS_21MS 1 /* 21 ms to 42 ms */
10315 #define PULS_42MS 2 /* 42 ms to 84 ms */
10316 #define PULS_84MS 3 /* 84 ms to 170 ms */
10317 #define PULS_170MS 4 /* 170 ms to 340 ms */
10318@@ -1217,7 +1300,7 @@
10319 #define PULS_670MS 6 /* 670 ms to 1.3 s */
10320 #define PULS_1300MS 7 /* 1.3 s to 2.7 s */
10321
10322-#define PHY_M_LED_BLINK_RT(x) SHIFT8(x) /* Blink Rate */
10323+#define PHY_M_LED_BLINK_RT(x) (SHIFT8(x) & PHY_M_LEDC_BL_R_MSK)
10324
10325 #define BLINK_42MS 0 /* 42 ms */
10326 #define BLINK_84MS 1 /* 84 ms */
10327@@ -1227,6 +1310,8 @@
10328 /* values 5 - 7: reserved */
10329
10330 /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
10331+#define PHY_M_LED_MO_SGMII(x) SHIFT14(x) /* Bit 15..14: SGMII AN Timer */
10332+ /* Bit 13..12: reserved */
10333 #define PHY_M_LED_MO_DUP(x) SHIFT10(x) /* Bit 11..10: Duplex */
10334 #define PHY_M_LED_MO_10(x) SHIFT8(x) /* Bit 9.. 8: Link 10 */
10335 #define PHY_M_LED_MO_100(x) SHIFT6(x) /* Bit 7.. 6: Link 100 */
10336@@ -1240,30 +1325,35 @@
10337 #define MO_LED_ON 3
10338
10339 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
10340- /* Bit 15.. 7: reserved */
10341-#define PHY_M_EC2_FI_IMPED (1<<6) /* Bit 6: Fiber Input Impedance */
10342-#define PHY_M_EC2_FO_IMPED (1<<5) /* Bit 5: Fiber Output Impedance */
10343-#define PHY_M_EC2_FO_M_CLK (1<<4) /* Bit 4: Fiber Mode Clock Enable */
10344-#define PHY_M_EC2_FO_BOOST (1<<3) /* Bit 3: Fiber Output Boost */
10345+ /* Bit 15.. 7: reserved */
10346+#define PHY_M_EC2_FI_IMPED BIT_6S /* Fiber Input Impedance */
10347+#define PHY_M_EC2_FO_IMPED BIT_5S /* Fiber Output Impedance */
10348+#define PHY_M_EC2_FO_M_CLK BIT_4S /* Fiber Mode Clock Enable */
10349+#define PHY_M_EC2_FO_BOOST BIT_3S /* Fiber Output Boost */
10350 #define PHY_M_EC2_FO_AM_MSK 7 /* Bit 2.. 0: Fiber Output Amplitude */
10351
10352-/***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
10353-#define PHY_M_FC_AUTO_SEL (1<<15) /* Bit 15: Fiber/Copper Auto Sel. dis. */
10354-#define PHY_M_FC_AN_REG_ACC (1<<14) /* Bit 14: Fiber/Copper Autoneg. reg acc */
10355-#define PHY_M_FC_RESULUTION (1<<13) /* Bit 13: Fiber/Copper Resulution */
10356-#define PHY_M_SER_IF_AN_BP (1<<12) /* Bit 12: Ser IF autoneg. bypass enable */
10357-#define PHY_M_SER_IF_BP_ST (1<<11) /* Bit 11: Ser IF autoneg. bypass status */
10358-#define PHY_M_IRQ_POLARITY (1<<10) /* Bit 10: IRQ polarity */
10359- /* Bit 9..4: reserved */
10360-#define PHY_M_UNDOC1 (1<< 7) /* undocumented bit !! */
10361-#define PHY_M_MODE_MASK (0xf<<0)/* Bit 3..0: copy of HWCFG MODE[3:0] */
10362-
10363+/***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
10364+#define PHY_M_FC_AUTO_SEL BIT_15S /* Fiber/Copper Auto Sel. Dis. */
10365+#define PHY_M_FC_AN_REG_ACC BIT_14S /* Fiber/Copper AN Reg. Access */
10366+#define PHY_M_FC_RESOLUTION BIT_13S /* Fiber/Copper Resolution */
10367+#define PHY_M_SER_IF_AN_BP BIT_12S /* Ser. IF AN Bypass Enable */
10368+#define PHY_M_SER_IF_BP_ST BIT_11S /* Ser. IF AN Bypass Status */
10369+#define PHY_M_IRQ_POLARITY BIT_10S /* IRQ polarity */
10370+#define PHY_M_DIS_AUT_MED BIT_9S /* Disable Aut. Medium Reg. Selection */
10371+ /* (88E1111 only) */
10372+ /* Bit 9.. 4: reserved (88E1040 only) */
10373+#define PHY_M_UNDOC1 BIT_7S /* undocumented bit !! */
10374+#define PHY_M_DTE_POW_STAT BIT_4S /* DTE Power Status (88E1111 only) */
10375+#define PHY_M_MODE_MASK 0xf /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
10376
10377 /***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/
10378-#define PHY_M_CABD_ENA_TEST (1<<15) /* Bit 15: Enable Test */
10379-#define PHY_M_CABD_STAT_MSK (3<<13) /* Bit 14..13: Status */
10380- /* Bit 12.. 8: reserved */
10381-#define PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance */
10382+#define PHY_M_CABD_ENA_TEST BIT_15S /* Enable Test (Page 0) */
10383+#define PHY_M_CABD_DIS_WAIT BIT_15S /* Disable Waiting Period (Page 1) */
10384+ /* (88E1111 only) */
10385+#define PHY_M_CABD_STAT_MSK (3<<13) /* Bit 14..13: Status Mask */
10386+#define PHY_M_CABD_AMPL_MSK (0x1f<<8) /* Bit 12.. 8: Amplitude Mask */
10387+ /* (88E1111 only) */
10388+#define PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance Mask */
10389
10390 /* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */
10391 #define CABD_STAT_NORMAL 0
10392@@ -1271,6 +1361,79 @@
10393 #define CABD_STAT_OPEN 2
10394 #define CABD_STAT_FAIL 3
10395
10396+/* for 10/100 Fast Ethernet PHY (88E3082 only) */
10397+/***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
10398+ /* Bit 15..12: reserved (used internally) */
10399+#define PHY_M_FELP_LED2_MSK (0xf<<8) /* Bit 11.. 8: LED2 Mask (LINK) */
10400+#define PHY_M_FELP_LED1_MSK (0xf<<4) /* Bit 7.. 4: LED1 Mask (ACT) */
10401+#define PHY_M_FELP_LED0_MSK 0xf /* Bit 3.. 0: LED0 Mask (SPEED) */
10402+
10403+#define PHY_M_FELP_LED2_CTRL(x) (SHIFT8(x) & PHY_M_FELP_LED2_MSK)
10404+#define PHY_M_FELP_LED1_CTRL(x) (SHIFT4(x) & PHY_M_FELP_LED1_MSK)
10405+#define PHY_M_FELP_LED0_CTRL(x) (SHIFT0(x) & PHY_M_FELP_LED0_MSK)
10406+
10407+#define LED_PAR_CTRL_COLX 0x00
10408+#define LED_PAR_CTRL_ERROR 0x01
10409+#define LED_PAR_CTRL_DUPLEX 0x02
10410+#define LED_PAR_CTRL_DP_COL 0x03
10411+#define LED_PAR_CTRL_SPEED 0x04
10412+#define LED_PAR_CTRL_LINK 0x05
10413+#define LED_PAR_CTRL_TX 0x06
10414+#define LED_PAR_CTRL_RX 0x07
10415+#define LED_PAR_CTRL_ACT 0x08
10416+#define LED_PAR_CTRL_LNK_RX 0x09
10417+#define LED_PAR_CTRL_LNK_AC 0x0a
10418+#define LED_PAR_CTRL_ACT_BL 0x0b
10419+#define LED_PAR_CTRL_TX_BL 0x0c
10420+#define LED_PAR_CTRL_RX_BL 0x0d
10421+#define LED_PAR_CTRL_COL_BL 0x0e
10422+#define LED_PAR_CTRL_INACT 0x0f
10423+
10424+/***** PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
10425+#define PHY_M_FESC_DIS_WAIT BIT_2S /* Disable TDR Waiting Period */
10426+#define PHY_M_FESC_ENA_MCLK BIT_1S /* Enable MAC Rx Clock in sleep mode */
10427+#define PHY_M_FESC_SEL_CL_A BIT_0S /* Select Class A driver (100B-TX) */
10428+
10429+/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
10430+/***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/
10431+#define PHY_M_FIB_FORCE_LNK BIT_10S /* Force Link Good */
10432+#define PHY_M_FIB_SIGD_POL BIT_9S /* SIGDET Polarity */
10433+#define PHY_M_FIB_TX_DIS BIT_3S /* Transmitter Disable */
10434+
10435+/***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
10436+#define PHY_M_MAC_MD_MSK (7<<7) /* Bit 9.. 7: Mode Select Mask */
10437+#define PHY_M_MAC_GMIF_PUP BIT_3S /* GMII Power Up (88E1149 only) */
10438+
10439+#define PHY_M_MAC_MD_AUTO 3 /* Auto Copper/1000Base-X */
10440+#define PHY_M_MAC_MD_COPPER 5 /* Copper only */
10441+#define PHY_M_MAC_MD_1000BX 7 /* 1000Base-X only */
10442+#define PHY_M_MAC_MODE_SEL(x) (SHIFT7(x) & PHY_M_MAC_MD_MSK)
10443+
10444+/***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
10445+#define PHY_M_LEDC_LOS_MSK (0xf<<12) /* Bit 15..12: LOS LED Ctrl. Mask */
10446+#define PHY_M_LEDC_INIT_MSK (0xf<<8) /* Bit 11.. 8: INIT LED Ctrl. Mask */
10447+#define PHY_M_LEDC_STA1_MSK (0xf<<4) /* Bit 7.. 4: STAT1 LED Ctrl. Mask */
10448+#define PHY_M_LEDC_STA0_MSK 0xf /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
10449+
10450+#define PHY_M_LEDC_LOS_CTRL(x) (SHIFT12(x) & PHY_M_LEDC_LOS_MSK)
10451+#define PHY_M_LEDC_INIT_CTRL(x) (SHIFT8(x) & PHY_M_LEDC_INIT_MSK)
10452+#define PHY_M_LEDC_STA1_CTRL(x) (SHIFT4(x) & PHY_M_LEDC_STA1_MSK)
10453+#define PHY_M_LEDC_STA0_CTRL(x) (SHIFT0(x) & PHY_M_LEDC_STA0_MSK)
10454+
10455+/***** PHY_MARV_PHY_STAT (page 3) 16 bit r/w Polarity Control Reg. *****/
10456+#define PHY_M_POLC_LS1M_MSK (0xf<<12) /* Bit 15..12: LOS,STAT1 Mix % Mask */
10457+#define PHY_M_POLC_IS0M_MSK (0xf<<8) /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
10458+#define PHY_M_POLC_LOS_MSK (0x3<<6) /* Bit 7.. 6: LOS Pol. Ctrl. Mask */
10459+#define PHY_M_POLC_INIT_MSK (0x3<<4) /* Bit 5.. 4: INIT Pol. Ctrl. Mask */
10460+#define PHY_M_POLC_STA1_MSK (0x3<<2) /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */
10461+#define PHY_M_POLC_STA0_MSK 0x3 /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */
10462+
10463+#define PHY_M_POLC_LS1_P_MIX(x) (SHIFT12(x) & PHY_M_POLC_LS1M_MSK)
10464+#define PHY_M_POLC_IS0_P_MIX(x) (SHIFT8(x) & PHY_M_POLC_IS0M_MSK)
10465+#define PHY_M_POLC_LOS_CTRL(x) (SHIFT6(x) & PHY_M_POLC_LOS_MSK)
10466+#define PHY_M_POLC_INIT_CTRL(x) (SHIFT4(x) & PHY_M_POLC_INIT_MSK)
10467+#define PHY_M_POLC_STA1_CTRL(x) (SHIFT2(x) & PHY_M_POLC_STA1_MSK)
10468+#define PHY_M_POLC_STA0_CTRL(x) (SHIFT0(x) & PHY_M_POLC_STA0_MSK)
10469
10470 /*
10471 * GMAC registers
10472@@ -1431,141 +1594,159 @@
10473 */
10474
10475 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
10476-#define GM_GPSR_SPEED (1<<15) /* Bit 15: Port Speed (1 = 100 Mbps) */
10477-#define GM_GPSR_DUPLEX (1<<14) /* Bit 14: Duplex Mode (1 = Full) */
10478-#define GM_GPSR_FC_TX_DIS (1<<13) /* Bit 13: Tx Flow-Control Mode Disabled */
10479-#define GM_GPSR_LINK_UP (1<<12) /* Bit 12: Link Up Status */
10480-#define GM_GPSR_PAUSE (1<<11) /* Bit 11: Pause State */
10481-#define GM_GPSR_TX_ACTIVE (1<<10) /* Bit 10: Tx in Progress */
10482-#define GM_GPSR_EXC_COL (1<<9) /* Bit 9: Excessive Collisions Occured */
10483-#define GM_GPSR_LAT_COL (1<<8) /* Bit 8: Late Collisions Occured */
10484- /* Bit 7..6: reserved */
10485-#define GM_GPSR_PHY_ST_CH (1<<5) /* Bit 5: PHY Status Change */
10486-#define GM_GPSR_GIG_SPEED (1<<4) /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
10487-#define GM_GPSR_PART_MODE (1<<3) /* Bit 3: Partition mode */
10488-#define GM_GPSR_FC_RX_DIS (1<<2) /* Bit 2: Rx Flow-Control Mode Disabled */
10489-#define GM_GPSR_PROM_EN (1<<1) /* Bit 1: Promiscuous Mode Enabled */
10490- /* Bit 0: reserved */
10491-
10492+#define GM_GPSR_SPEED BIT_15S /* Port Speed (1 = 100 Mbps) */
10493+#define GM_GPSR_DUPLEX BIT_14S /* Duplex Mode (1 = Full) */
10494+#define GM_GPSR_FC_TX_DIS BIT_13S /* Tx Flow-Control Mode Disabled */
10495+#define GM_GPSR_LINK_UP BIT_12S /* Link Up Status */
10496+#define GM_GPSR_PAUSE BIT_11S /* Pause State */
10497+#define GM_GPSR_TX_ACTIVE BIT_10S /* Tx in Progress */
10498+#define GM_GPSR_EXC_COL BIT_9S /* Excessive Collisions Occured */
10499+#define GM_GPSR_LAT_COL BIT_8S /* Late Collisions Occured */
10500+ /* Bit 7.. 6: reserved */
10501+#define GM_GPSR_PHY_ST_CH BIT_5S /* PHY Status Change */
10502+#define GM_GPSR_GIG_SPEED BIT_4S /* Gigabit Speed (1 = 1000 Mbps) */
10503+#define GM_GPSR_PART_MODE BIT_3S /* Partition mode */
10504+#define GM_GPSR_FC_RX_DIS BIT_2S /* Rx Flow-Control Mode Disabled */
10505+ /* Bit 2.. 0: reserved */
10506+
10507 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
10508- /* Bit 15: reserved */
10509-#define GM_GPCR_PROM_ENA (1<<14) /* Bit 14: Enable Promiscuous Mode */
10510-#define GM_GPCR_FC_TX_DIS (1<<13) /* Bit 13: Disable Tx Flow-Control Mode */
10511-#define GM_GPCR_TX_ENA (1<<12) /* Bit 12: Enable Transmit */
10512-#define GM_GPCR_RX_ENA (1<<11) /* Bit 11: Enable Receive */
10513-#define GM_GPCR_BURST_ENA (1<<10) /* Bit 10: Enable Burst Mode */
10514-#define GM_GPCR_LOOP_ENA (1<<9) /* Bit 9: Enable MAC Loopback Mode */
10515-#define GM_GPCR_PART_ENA (1<<8) /* Bit 8: Enable Partition Mode */
10516-#define GM_GPCR_GIGS_ENA (1<<7) /* Bit 7: Gigabit Speed (1000 Mbps) */
10517-#define GM_GPCR_FL_PASS (1<<6) /* Bit 6: Force Link Pass */
10518-#define GM_GPCR_DUP_FULL (1<<5) /* Bit 5: Full Duplex Mode */
10519-#define GM_GPCR_FC_RX_DIS (1<<4) /* Bit 4: Disable Rx Flow-Control Mode */
10520-#define GM_GPCR_SPEED_100 (1<<3) /* Bit 3: Port Speed 100 Mbps */
10521-#define GM_GPCR_AU_DUP_DIS (1<<2) /* Bit 2: Disable Auto-Update Duplex */
10522-#define GM_GPCR_AU_FCT_DIS (1<<1) /* Bit 1: Disable Auto-Update Flow-C. */
10523-#define GM_GPCR_AU_SPD_DIS (1<<0) /* Bit 0: Disable Auto-Update Speed */
10524+#define GM_GPCR_RMII_PH_ENA BIT_15S /* Enable RMII for PHY (Yukon-FE only) */
10525+#define GM_GPCR_RMII_LB_ENA BIT_14S /* Enable RMII Loopback (Yukon-FE only) */
10526+#define GM_GPCR_FC_TX_DIS BIT_13S /* Disable Tx Flow-Control Mode */
10527+#define GM_GPCR_TX_ENA BIT_12S /* Enable Transmit */
10528+#define GM_GPCR_RX_ENA BIT_11S /* Enable Receive */
10529+ /* Bit 10: reserved */
10530+#define GM_GPCR_LOOP_ENA BIT_9S /* Enable MAC Loopback Mode */
10531+#define GM_GPCR_PART_ENA BIT_8S /* Enable Partition Mode */
10532+#define GM_GPCR_GIGS_ENA BIT_7S /* Gigabit Speed (1000 Mbps) */
10533+#define GM_GPCR_FL_PASS BIT_6S /* Force Link Pass */
10534+#define GM_GPCR_DUP_FULL BIT_5S /* Full Duplex Mode */
10535+#define GM_GPCR_FC_RX_DIS BIT_4S /* Disable Rx Flow-Control Mode */
10536+#define GM_GPCR_SPEED_100 BIT_3S /* Port Speed 100 Mbps */
10537+#define GM_GPCR_AU_DUP_DIS BIT_2S /* Disable Auto-Update Duplex */
10538+#define GM_GPCR_AU_FCT_DIS BIT_1S /* Disable Auto-Update Flow-C. */
10539+#define GM_GPCR_AU_SPD_DIS BIT_0S /* Disable Auto-Update Speed */
10540
10541 #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
10542 #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |\
10543 GM_GPCR_AU_SPD_DIS)
10544-
10545+
10546 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
10547-#define GM_TXCR_FORCE_JAM (1<<15) /* Bit 15: Force Jam / Flow-Control */
10548-#define GM_TXCR_CRC_DIS (1<<14) /* Bit 14: Disable insertion of CRC */
10549-#define GM_TXCR_PAD_DIS (1<<13) /* Bit 13: Disable padding of packets */
10550-#define GM_TXCR_COL_THR_MSK (1<<10) /* Bit 12..10: Collision Threshold */
10551+#define GM_TXCR_FORCE_JAM BIT_15S /* Force Jam / Flow-Control */
10552+#define GM_TXCR_CRC_DIS BIT_14S /* Disable insertion of CRC */
10553+#define GM_TXCR_PAD_DIS BIT_13S /* Disable padding of packets */
10554+#define GM_TXCR_COL_THR_MSK (7<<10) /* Bit 12..10: Collision Threshold Mask */
10555+ /* Bit 9.. 8: reserved */
10556+#define GM_TXCR_PAD_PAT_MSK 0xff /* Bit 7.. 0: Padding Pattern Mask */
10557+ /* (Yukon-2 only) */
10558
10559 #define TX_COL_THR(x) (SHIFT10(x) & GM_TXCR_COL_THR_MSK)
10560
10561 #define TX_COL_DEF 0x04
10562-
10563+
10564 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
10565-#define GM_RXCR_UCF_ENA (1<<15) /* Bit 15: Enable Unicast filtering */
10566-#define GM_RXCR_MCF_ENA (1<<14) /* Bit 14: Enable Multicast filtering */
10567-#define GM_RXCR_CRC_DIS (1<<13) /* Bit 13: Remove 4-byte CRC */
10568-#define GM_RXCR_PASS_FC (1<<12) /* Bit 12: Pass FC packets to FIFO */
10569-
10570+#define GM_RXCR_UCF_ENA BIT_15S /* Enable Unicast filtering */
10571+#define GM_RXCR_MCF_ENA BIT_14S /* Enable Multicast filtering */
10572+#define GM_RXCR_CRC_DIS BIT_13S /* Remove 4-byte CRC */
10573+#define GM_RXCR_PASS_FC BIT_12S /* Pass FC packets to FIFO (Yukon-1 only) */
10574+ /* Bit 11.. 0: reserved */
10575+
10576 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
10577-#define GM_TXPA_JAMLEN_MSK (0x03<<14) /* Bit 15..14: Jam Length */
10578-#define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13..9: Jam IPG */
10579-#define GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8..4: IPG Jam to Data */
10580- /* Bit 3..0: reserved */
10581+#define GM_TXPA_JAMLEN_MSK (3<<14) /* Bit 15..14: Jam Length Mask */
10582+#define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13.. 9: Jam IPG Mask */
10583+#define GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8.. 4: IPG Jam to Data Mask */
10584+#define GM_TXPA_BO_LIM_MSK 0x0f /* Bit 3.. 0: Backoff Limit Mask */
10585+ /* (Yukon-2 only) */
10586
10587 #define TX_JAM_LEN_VAL(x) (SHIFT14(x) & GM_TXPA_JAMLEN_MSK)
10588 #define TX_JAM_IPG_VAL(x) (SHIFT9(x) & GM_TXPA_JAMIPG_MSK)
10589 #define TX_IPG_JAM_DATA(x) (SHIFT4(x) & GM_TXPA_JAMDAT_MSK)
10590+#define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK)
10591
10592 #define TX_JAM_LEN_DEF 0x03
10593 #define TX_JAM_IPG_DEF 0x0b
10594 #define TX_IPG_JAM_DEF 0x1c
10595+#define TX_BOF_LIM_DEF 0x04
10596
10597 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
10598-#define GM_SMOD_DATABL_MSK (0x1f<<11) /* Bit 15..11: Data Blinder (r/o) */
10599-#define GM_SMOD_LIMIT_4 (1<<10) /* Bit 10: 4 consecutive Tx trials */
10600-#define GM_SMOD_VLAN_ENA (1<<9) /* Bit 9: Enable VLAN (Max. Frame Len) */
10601-#define GM_SMOD_JUMBO_ENA (1<<8) /* Bit 8: Enable Jumbo (Max. Frame Len) */
10602- /* Bit 7..5: reserved */
10603-#define GM_SMOD_IPG_MSK 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
10604-
10605+#define GM_SMOD_DATABL_MSK (0x1f<<11) /* Bit 15..11: Data Blinder */
10606+ /* r/o on Yukon, r/w on Yukon-EC */
10607+#define GM_SMOD_LIMIT_4 BIT_10S /* 4 consecutive Tx trials */
10608+#define GM_SMOD_VLAN_ENA BIT_9S /* Enable VLAN (Max. Frame Len) */
10609+#define GM_SMOD_JUMBO_ENA BIT_8S /* Enable Jumbo (Max. Frame Len) */
10610+ /* Bit 7.. 5: reserved */
10611+#define GM_SMOD_IPG_MSK 0x1f /* Bit 4.. 0: Inter-Packet Gap (IPG) */
10612+
10613 #define DATA_BLIND_VAL(x) (SHIFT11(x) & GM_SMOD_DATABL_MSK)
10614-#define DATA_BLIND_DEF 0x04
10615+#define IPG_DATA_VAL(x) ((x) & GM_SMOD_IPG_MSK)
10616
10617-#define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
10618+#define DATA_BLIND_DEF 0x04
10619 #define IPG_DATA_DEF 0x1e
10620
10621 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
10622 #define GM_SMI_CT_PHY_A_MSK (0x1f<<11) /* Bit 15..11: PHY Device Address */
10623 #define GM_SMI_CT_REG_A_MSK (0x1f<<6) /* Bit 10.. 6: PHY Register Address */
10624-#define GM_SMI_CT_OP_RD (1<<5) /* Bit 5: OpCode Read (0=Write)*/
10625-#define GM_SMI_CT_RD_VAL (1<<4) /* Bit 4: Read Valid (Read completed) */
10626-#define GM_SMI_CT_BUSY (1<<3) /* Bit 3: Busy (Operation in progress) */
10627- /* Bit 2..0: reserved */
10628-
10629+#define GM_SMI_CT_OP_RD BIT_5S /* OpCode Read (0=Write)*/
10630+#define GM_SMI_CT_RD_VAL BIT_4S /* Read Valid (Read completed) */
10631+#define GM_SMI_CT_BUSY BIT_3S /* Busy (Operation in progress) */
10632+ /* Bit 2.. 0: reserved */
10633+
10634 #define GM_SMI_CT_PHY_AD(x) (SHIFT11(x) & GM_SMI_CT_PHY_A_MSK)
10635 #define GM_SMI_CT_REG_AD(x) (SHIFT6(x) & GM_SMI_CT_REG_A_MSK)
10636
10637- /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
10638- /* Bit 15..6: reserved */
10639-#define GM_PAR_MIB_CLR (1<<5) /* Bit 5: Set MIB Clear Counter Mode */
10640-#define GM_PAR_MIB_TST (1<<4) /* Bit 4: MIB Load Counter (Test Mode) */
10641- /* Bit 3..0: reserved */
10642-
10643+/* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
10644+ /* Bit 15.. 6: reserved */
10645+#define GM_PAR_MIB_CLR BIT_5S /* Set MIB Clear Counter Mode */
10646+#define GM_PAR_MIB_TST BIT_4S /* MIB Load Counter (Test Mode) */
10647+ /* Bit 3.. 0: reserved */
10648+
10649 /* Receive Frame Status Encoding */
10650-#define GMR_FS_LEN (0xffffUL<<16) /* Bit 31..16: Rx Frame Length */
10651+#define GMR_FS_LEN_MSK (0xffffUL<<16) /* Bit 31..16: Rx Frame Length */
10652 /* Bit 15..14: reserved */
10653-#define GMR_FS_VLAN (1L<<13) /* Bit 13: VLAN Packet */
10654-#define GMR_FS_JABBER (1L<<12) /* Bit 12: Jabber Packet */
10655-#define GMR_FS_UN_SIZE (1L<<11) /* Bit 11: Undersize Packet */
10656-#define GMR_FS_MC (1L<<10) /* Bit 10: Multicast Packet */
10657-#define GMR_FS_BC (1L<<9) /* Bit 9: Broadcast Packet */
10658-#define GMR_FS_RX_OK (1L<<8) /* Bit 8: Receive OK (Good Packet) */
10659-#define GMR_FS_GOOD_FC (1L<<7) /* Bit 7: Good Flow-Control Packet */
10660-#define GMR_FS_BAD_FC (1L<<6) /* Bit 6: Bad Flow-Control Packet */
10661-#define GMR_FS_MII_ERR (1L<<5) /* Bit 5: MII Error */
10662-#define GMR_FS_LONG_ERR (1L<<4) /* Bit 4: Too Long Packet */
10663-#define GMR_FS_FRAGMENT (1L<<3) /* Bit 3: Fragment */
10664+#define GMR_FS_VLAN BIT_13 /* VLAN Packet */
10665+#define GMR_FS_JABBER BIT_12 /* Jabber Packet */
10666+#define GMR_FS_UN_SIZE BIT_11 /* Undersize Packet */
10667+#define GMR_FS_MC BIT_10 /* Multicast Packet */
10668+#define GMR_FS_BC BIT_9 /* Broadcast Packet */
10669+#define GMR_FS_RX_OK BIT_8 /* Receive OK (Good Packet) */
10670+#define GMR_FS_GOOD_FC BIT_7 /* Good Flow-Control Packet */
10671+#define GMR_FS_BAD_FC BIT_6 /* Bad Flow-Control Packet */
10672+#define GMR_FS_MII_ERR BIT_5 /* MII Error */
10673+#define GMR_FS_LONG_ERR BIT_4 /* Too Long Packet */
10674+#define GMR_FS_FRAGMENT BIT_3 /* Fragment */
10675 /* Bit 2: reserved */
10676-#define GMR_FS_CRC_ERR (1L<<1) /* Bit 1: CRC Error */
10677-#define GMR_FS_RX_FF_OV (1L<<0) /* Bit 0: Rx FIFO Overflow */
10678+#define GMR_FS_CRC_ERR BIT_1 /* CRC Error */
10679+#define GMR_FS_RX_FF_OV BIT_0 /* Rx FIFO Overflow */
10680+
10681+#define GMR_FS_LEN_SHIFT 16
10682
10683 /*
10684 * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR)
10685 */
10686-#define GMR_FS_ANY_ERR (GMR_FS_CRC_ERR | \
10687- GMR_FS_LONG_ERR | \
10688+#ifdef SK_DIAG
10689+#define GMR_FS_ANY_ERR ( \
10690+ GMR_FS_RX_FF_OV | \
10691+ GMR_FS_CRC_ERR | \
10692+ GMR_FS_FRAGMENT | \
10693 GMR_FS_MII_ERR | \
10694 GMR_FS_BAD_FC | \
10695 GMR_FS_GOOD_FC | \
10696 GMR_FS_JABBER)
10697-
10698-/* Rx GMAC FIFO Flush Mask (default) */
10699-#define RX_FF_FL_DEF_MSK (GMR_FS_CRC_ERR | \
10700+#else
10701+#define GMR_FS_ANY_ERR ( \
10702 GMR_FS_RX_FF_OV | \
10703+ GMR_FS_CRC_ERR | \
10704+ GMR_FS_FRAGMENT | \
10705+ GMR_FS_LONG_ERR | \
10706 GMR_FS_MII_ERR | \
10707 GMR_FS_BAD_FC | \
10708 GMR_FS_GOOD_FC | \
10709 GMR_FS_UN_SIZE | \
10710 GMR_FS_JABBER)
10711+#endif
10712+
10713+/* Rx GMAC FIFO Flush Mask (default) */
10714+#define RX_FF_FL_DEF_MSK GMR_FS_ANY_ERR
10715
10716 /* typedefs *******************************************************************/
10717
10718@@ -1577,3 +1758,4 @@
10719 #endif /* __cplusplus */
10720
10721 #endif /* __INC_XMAC_H */
10722+
10723diff -ruN linux/drivers/net/sk98lin/skaddr.c linux-new/drivers/net/sk98lin/skaddr.c
10724--- linux/drivers/net/sk98lin/skaddr.c 2006-04-11 19:19:28.000000000 +0200
10725+++ linux-new/drivers/net/sk98lin/skaddr.c 2006-01-18 14:37:24.000000000 +0100
10726@@ -2,8 +2,8 @@
10727 *
10728 * Name: skaddr.c
10729 * Project: Gigabit Ethernet Adapters, ADDR-Module
10730- * Version: $Revision$
10731- * Date: $Date$
10732+ * Version: $Revision$
10733+ * Date: $Date$
10734 * Purpose: Manage Addresses (Multicast and Unicast) and Promiscuous Mode.
10735 *
10736 ******************************************************************************/
10737@@ -11,7 +11,7 @@
10738 /******************************************************************************
10739 *
10740 * (C)Copyright 1998-2002 SysKonnect GmbH.
10741- * (C)Copyright 2002-2003 Marvell.
10742+ * (C)Copyright 2002-2005 Marvell.
10743 *
10744 * This program is free software; you can redistribute it and/or modify
10745 * it under the terms of the GNU General Public License as published by
10746@@ -44,7 +44,7 @@
10747
10748 #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
10749 static const char SysKonnectFileId[] =
10750- "@(#) $Id$ (C) Marvell.";
10751+ "@(#) $Id$ (C) Marvell.";
10752 #endif /* DEBUG ||!LINT || !SK_SLIM */
10753
10754 #define __SKADDR_C
10755@@ -58,11 +58,10 @@
10756
10757 /* defines ********************************************************************/
10758
10759-
10760 #define XMAC_POLY 0xEDB88320UL /* CRC32-Poly - XMAC: Little Endian */
10761 #define GMAC_POLY 0x04C11DB7L /* CRC16-Poly - GMAC: Little Endian */
10762 #define HASH_BITS 6 /* #bits in hash */
10763-#define SK_MC_BIT 0x01
10764+#define SK_MC_BIT 0x01
10765
10766 /* Error numbers and messages. */
10767
10768@@ -79,7 +78,7 @@
10769
10770 /* 64-bit hash values with all bits set. */
10771
10772-static const SK_U16 OnesHash[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
10773+SK_U16 OnesHash[4] = {0xffff, 0xffff, 0xffff, 0xffff};
10774
10775 /* local variables ************************************************************/
10776
10777@@ -136,13 +135,12 @@
10778
10779 switch (Level) {
10780 case SK_INIT_DATA:
10781- SK_MEMSET((char *) &pAC->Addr, (SK_U8) 0,
10782- (SK_U16) sizeof(SK_ADDR));
10783+ SK_MEMSET((char *)&pAC->Addr, (SK_U8)0, (SK_U16)sizeof(SK_ADDR));
10784
10785 for (i = 0; i < SK_MAX_MACS; i++) {
10786 pAPort = &pAC->Addr.Port[i];
10787 pAPort->PromMode = SK_PROM_MODE_NONE;
10788-
10789+
10790 pAPort->FirstExactMatchRlmt = SK_ADDR_FIRST_MATCH_RLMT;
10791 pAPort->FirstExactMatchDrv = SK_ADDR_FIRST_MATCH_DRV;
10792 pAPort->NextExactMatchRlmt = SK_ADDR_FIRST_MATCH_RLMT;
10793@@ -159,7 +157,7 @@
10794 /* pAC->Addr.InitDone = SK_INIT_DATA; */
10795 break;
10796
10797- case SK_INIT_IO:
10798+ case SK_INIT_IO:
10799 #ifndef SK_NO_RLMT
10800 for (i = 0; i < SK_MAX_NETS; i++) {
10801 pAC->Addr.Net[i].ActivePort = pAC->Rlmt.Net[i].ActivePort;
10802@@ -173,7 +171,7 @@
10803 }
10804 }
10805 #endif /* DEBUG */
10806-
10807+
10808 /* Read permanent logical MAC address from Control Register File. */
10809 for (j = 0; j < SK_MAC_ADDR_LEN; j++) {
10810 InAddr = (SK_U8 *) &pAC->Addr.Net[0].PermanentMacAddress.a[j];
10811@@ -191,11 +189,11 @@
10812 pAC->Addr.Port[pAC->Addr.Net[0].ActivePort].Exact[0] =
10813 pAC->Addr.Net[0].CurrentMacAddress;
10814 #if SK_MAX_NETS > 1
10815- /* Set logical MAC address for net 2 to (log | 3). */
10816+ /* Set logical MAC address for net 2 to. */
10817 if (!pAC->Addr.Net[1].CurrentMacAddressSet) {
10818 pAC->Addr.Net[1].PermanentMacAddress =
10819 pAC->Addr.Net[0].PermanentMacAddress;
10820- pAC->Addr.Net[1].PermanentMacAddress.a[5] |= 3;
10821+ pAC->Addr.Net[1].PermanentMacAddress.a[5] += 1;
10822 /* Set the current logical MAC address to the permanent one. */
10823 pAC->Addr.Net[1].CurrentMacAddress =
10824 pAC->Addr.Net[1].PermanentMacAddress;
10825@@ -213,8 +211,8 @@
10826 pAC->Addr.Net[i].PermanentMacAddress.a[2],
10827 pAC->Addr.Net[i].PermanentMacAddress.a[3],
10828 pAC->Addr.Net[i].PermanentMacAddress.a[4],
10829- pAC->Addr.Net[i].PermanentMacAddress.a[5]))
10830-
10831+ pAC->Addr.Net[i].PermanentMacAddress.a[5]));
10832+
10833 SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_INIT,
10834 ("Logical MAC Address (Net%d): %02X %02X %02X %02X %02X %02X\n",
10835 i,
10836@@ -223,7 +221,7 @@
10837 pAC->Addr.Net[i].CurrentMacAddress.a[2],
10838 pAC->Addr.Net[i].CurrentMacAddress.a[3],
10839 pAC->Addr.Net[i].CurrentMacAddress.a[4],
10840- pAC->Addr.Net[i].CurrentMacAddress.a[5]))
10841+ pAC->Addr.Net[i].CurrentMacAddress.a[5]));
10842 }
10843 #endif /* DEBUG */
10844
10845@@ -266,8 +264,8 @@
10846 pAPort->PermanentMacAddress.a[2],
10847 pAPort->PermanentMacAddress.a[3],
10848 pAPort->PermanentMacAddress.a[4],
10849- pAPort->PermanentMacAddress.a[5]))
10850-
10851+ pAPort->PermanentMacAddress.a[5]));
10852+
10853 SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_INIT,
10854 ("SkAddrInit: Physical MAC Address: %02X %02X %02X %02X %02X %02X\n",
10855 pAPort->CurrentMacAddress.a[0],
10856@@ -275,7 +273,7 @@
10857 pAPort->CurrentMacAddress.a[2],
10858 pAPort->CurrentMacAddress.a[3],
10859 pAPort->CurrentMacAddress.a[4],
10860- pAPort->CurrentMacAddress.a[5]))
10861+ pAPort->CurrentMacAddress.a[5]));
10862 #endif /* DEBUG */
10863 }
10864 /* pAC->Addr.InitDone = SK_INIT_IO; */
10865@@ -299,7 +297,7 @@
10866 }
10867
10868 return (SK_ADDR_SUCCESS);
10869-
10870+
10871 } /* SkAddrInit */
10872
10873 #ifndef SK_SLIM
10874@@ -333,16 +331,20 @@
10875 int Flags) /* permanent/non-perm, sw-only */
10876 {
10877 int ReturnCode;
10878-
10879+
10880 if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
10881 return (SK_ADDR_ILLEGAL_PORT);
10882 }
10883-
10884+
10885 if (pAC->GIni.GIGenesis) {
10886+#ifdef GENESIS
10887 ReturnCode = SkAddrXmacMcClear(pAC, IoC, PortNumber, Flags);
10888+#endif
10889 }
10890 else {
10891+#ifdef YUKON
10892 ReturnCode = SkAddrGmacMcClear(pAC, IoC, PortNumber, Flags);
10893+#endif
10894 }
10895
10896 return (ReturnCode);
10897@@ -352,7 +354,7 @@
10898 #endif /* !SK_SLIM */
10899
10900 #ifndef SK_SLIM
10901-
10902+#ifdef GENESIS
10903 /******************************************************************************
10904 *
10905 * SkAddrXmacMcClear - clear the multicast table
10906@@ -402,13 +404,13 @@
10907 }
10908
10909 return (SK_ADDR_SUCCESS);
10910-
10911-} /* SkAddrXmacMcClear */
10912
10913+} /* SkAddrXmacMcClear */
10914+#endif /* GENESIS */
10915 #endif /* !SK_SLIM */
10916
10917 #ifndef SK_SLIM
10918-
10919+#ifdef YUKON
10920 /******************************************************************************
10921 *
10922 * SkAddrGmacMcClear - clear the multicast table
10923@@ -447,38 +449,37 @@
10924 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[4],
10925 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[5],
10926 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[6],
10927- pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7]))
10928+ pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7]));
10929 #endif /* DEBUG */
10930
10931 /* Clear InexactFilter */
10932 for (i = 0; i < 8; i++) {
10933 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] = 0;
10934 }
10935-
10936+
10937 if (Flags & SK_ADDR_PERMANENT) { /* permanent => RLMT */
10938-
10939+
10940 /* Copy DRV bits to InexactFilter. */
10941 for (i = 0; i < 8; i++) {
10942 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |=
10943 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[i];
10944-
10945+
10946 /* Clear InexactRlmtFilter. */
10947 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[i] = 0;
10948-
10949- }
10950+ }
10951 }
10952 else { /* not permanent => DRV */
10953-
10954+
10955 /* Copy RLMT bits to InexactFilter. */
10956 for (i = 0; i < 8; i++) {
10957 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |=
10958 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[i];
10959-
10960+
10961 /* Clear InexactDrvFilter. */
10962 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[i] = 0;
10963 }
10964 }
10965-
10966+
10967 #ifdef DEBUG
10968 SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
10969 ("GMAC InexactFilter (cleared): %02X %02X %02X %02X %02X %02X %02X %02X\n",
10970@@ -489,19 +490,20 @@
10971 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[4],
10972 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[5],
10973 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[6],
10974- pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7]))
10975+ pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7]));
10976 #endif /* DEBUG */
10977-
10978+
10979 if (!(Flags & SK_MC_SW_ONLY)) {
10980 (void) SkAddrGmacMcUpdate(pAC, IoC, PortNumber);
10981 }
10982-
10983+
10984 return (SK_ADDR_SUCCESS);
10985
10986 } /* SkAddrGmacMcClear */
10987+#endif /* YUKON */
10988
10989 #ifndef SK_ADDR_CHEAT
10990-
10991+#ifdef GENESIS
10992 /******************************************************************************
10993 *
10994 * SkXmacMcHash - hash multicast address
10995@@ -538,8 +540,9 @@
10996 return (Crc & ((1 << HASH_BITS) - 1));
10997
10998 } /* SkXmacMcHash */
10999+#endif /* GENESIS */
11000
11001-
11002+#ifdef YUKON
11003 /******************************************************************************
11004 *
11005 * SkGmacMcHash - hash multicast address
11006@@ -570,7 +573,7 @@
11007 for (Byte = 0; Byte < 6; Byte++) {
11008 /* Get next byte. */
11009 Data = (SK_U32) pMc[Byte];
11010-
11011+
11012 /* Change bit order in byte. */
11013 TmpData = Data;
11014 for (Bit = 0; Bit < 8; Bit++) {
11015@@ -582,7 +585,7 @@
11016 }
11017 TmpData >>= 1;
11018 }
11019-
11020+
11021 Crc ^= (Data << 24);
11022 for (Bit = 0; Bit < 8; Bit++) {
11023 if (Crc & 0x80000000) {
11024@@ -593,11 +596,11 @@
11025 }
11026 }
11027 }
11028-
11029+
11030 return (Crc & ((1 << HASH_BITS) - 1));
11031
11032 } /* SkGmacMcHash */
11033-
11034+#endif /* YUKON */
11035 #endif /* !SK_ADDR_CHEAT */
11036
11037 /******************************************************************************
11038@@ -632,23 +635,27 @@
11039 int Flags) /* permanent/non-permanent */
11040 {
11041 int ReturnCode;
11042-
11043+
11044 if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
11045 return (SK_ADDR_ILLEGAL_PORT);
11046 }
11047-
11048+
11049 if (pAC->GIni.GIGenesis) {
11050+#ifdef GENESIS
11051 ReturnCode = SkAddrXmacMcAdd(pAC, IoC, PortNumber, pMc, Flags);
11052+#endif
11053 }
11054 else {
11055+#ifdef YUKON
11056 ReturnCode = SkAddrGmacMcAdd(pAC, IoC, PortNumber, pMc, Flags);
11057+#endif
11058 }
11059
11060 return (ReturnCode);
11061
11062 } /* SkAddrMcAdd */
11063
11064-
11065+#ifdef GENESIS
11066 /******************************************************************************
11067 *
11068 * SkAddrXmacMcAdd - add a multicast address to a port
11069@@ -693,7 +700,7 @@
11070 return (SK_MC_RLMT_OVERFLOW);
11071 }
11072 #endif /* DEBUG */
11073-
11074+
11075 if (pAC->Addr.Port[PortNumber].NextExactMatchRlmt >
11076 SK_ADDR_LAST_MATCH_RLMT) {
11077 return (SK_MC_RLMT_OVERFLOW);
11078@@ -714,7 +721,7 @@
11079 return (SK_MC_RLMT_OVERFLOW);
11080 }
11081 #endif /* DEBUG */
11082-
11083+
11084 if (pAC->Addr.Port[PortNumber].NextExactMatchDrv <= SK_ADDR_LAST_MATCH_DRV) {
11085
11086 /* Set exact match entry. */
11087@@ -758,8 +765,9 @@
11088 }
11089
11090 } /* SkAddrXmacMcAdd */
11091+#endif /* GENESIS */
11092
11093-
11094+#ifdef YUKON
11095 /******************************************************************************
11096 *
11097 * SkAddrGmacMcAdd - add a multicast address to a port
11098@@ -789,28 +797,29 @@
11099 #ifndef SK_ADDR_CHEAT
11100 SK_U32 HashBit;
11101 #endif /* !defined(SK_ADDR_CHEAT) */
11102-
11103+
11104 if (!(pMc->a[0] & SK_MC_BIT)) {
11105 /* Hashing only possible with multicast addresses */
11106 return (SK_MC_ILLEGAL_ADDRESS);
11107 }
11108-
11109+
11110 #ifndef SK_ADDR_CHEAT
11111-
11112+
11113 /* Compute hash value of address. */
11114 HashBit = SkGmacMcHash(&pMc->a[0]);
11115-
11116+
11117 if (Flags & SK_ADDR_PERMANENT) { /* permanent => RLMT */
11118-
11119+
11120 /* Add bit to InexactRlmtFilter. */
11121 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[HashBit / 8] |=
11122 1 << (HashBit % 8);
11123-
11124+
11125 /* Copy bit to InexactFilter. */
11126 for (i = 0; i < 8; i++) {
11127 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |=
11128 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[i];
11129 }
11130+
11131 #ifdef DEBUG
11132 SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
11133 ("GMAC InexactRlmtFilter: %02X %02X %02X %02X %02X %02X %02X %02X\n",
11134@@ -821,20 +830,21 @@
11135 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[4],
11136 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[5],
11137 pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[6],
11138- pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[7]))
11139+ pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[7]));
11140 #endif /* DEBUG */
11141 }
11142 else { /* not permanent => DRV */
11143-
11144+
11145 /* Add bit to InexactDrvFilter. */
11146 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[HashBit / 8] |=
11147 1 << (HashBit % 8);
11148-
11149+
11150 /* Copy bit to InexactFilter. */
11151 for (i = 0; i < 8; i++) {
11152 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |=
11153 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[i];
11154 }
11155+
11156 #ifdef DEBUG
11157 SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
11158 ("GMAC InexactDrvFilter: %02X %02X %02X %02X %02X %02X %02X %02X\n",
11159@@ -845,22 +855,22 @@
11160 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[4],
11161 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[5],
11162 pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[6],
11163- pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[7]))
11164+ pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[7]));
11165 #endif /* DEBUG */
11166 }
11167-
11168+
11169 #else /* SK_ADDR_CHEAT */
11170-
11171+
11172 /* Set all bits in InexactFilter. */
11173 for (i = 0; i < 8; i++) {
11174 pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] = 0xFF;
11175 }
11176 #endif /* SK_ADDR_CHEAT */
11177-
11178+
11179 return (SK_MC_FILTERING_INEXACT);
11180-
11181-} /* SkAddrGmacMcAdd */
11182
11183+} /* SkAddrGmacMcAdd */
11184+#endif /* YUKON */
11185 #endif /* !SK_SLIM */
11186
11187 /******************************************************************************
11188@@ -892,7 +902,8 @@
11189 SK_IOC IoC, /* I/O context */
11190 SK_U32 PortNumber) /* Port Number */
11191 {
11192- int ReturnCode = 0;
11193+ int ReturnCode = SK_ADDR_ILLEGAL_PORT;
11194+
11195 #if (!defined(SK_SLIM) || defined(DEBUG))
11196 if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
11197 return (SK_ADDR_ILLEGAL_PORT);
11198@@ -948,13 +959,13 @@
11199 SK_ADDR_PORT *pAPort;
11200
11201 SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
11202- ("SkAddrXmacMcUpdate on Port %u.\n", PortNumber))
11203-
11204+ ("SkAddrXmacMcUpdate on Port %u.\n", PortNumber));
11205+
11206 pAPort = &pAC->Addr.Port[PortNumber];
11207
11208 #ifdef DEBUG
11209 SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
11210- ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber]))
11211+ ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber]));
11212 #endif /* DEBUG */
11213
11214 /* Start with 0 to also program the logical MAC address. */
11215@@ -966,7 +977,7 @@
11216
11217 /* Clear other permanent exact match addresses on XMAC */
11218 if (pAPort->NextExactMatchRlmt <= SK_ADDR_LAST_MATCH_RLMT) {
11219-
11220+
11221 SkXmClrExactAddr(pAC, IoC, PortNumber, pAPort->NextExactMatchRlmt,
11222 SK_ADDR_LAST_MATCH_RLMT);
11223 }
11224@@ -978,7 +989,7 @@
11225
11226 /* Clear other non-permanent exact match addresses on XMAC */
11227 if (pAPort->NextExactMatchDrv <= SK_ADDR_LAST_MATCH_DRV) {
11228-
11229+
11230 SkXmClrExactAddr(pAC, IoC, PortNumber, pAPort->NextExactMatchDrv,
11231 SK_ADDR_LAST_MATCH_DRV);
11232 }
11233@@ -988,18 +999,18 @@
11234 }
11235
11236 if (pAPort->PromMode & SK_PROM_MODE_ALL_MC) {
11237-
11238+
11239 /* Set all bits in 64-bit hash register. */
11240 XM_OUTHASH(IoC, PortNumber, XM_HSM, &OnesHash);
11241-
11242+
11243 /* Enable Hashing */
11244 SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
11245 }
11246 else if (Inexact != 0) {
11247-
11248+
11249 /* Set 64-bit hash register to InexactFilter. */
11250 XM_OUTHASH(IoC, PortNumber, XM_HSM, &pAPort->InexactFilter.Bytes[0]);
11251-
11252+
11253 /* Enable Hashing */
11254 SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
11255 }
11256@@ -1014,7 +1025,7 @@
11257
11258 /* Set port's current physical MAC address. */
11259 OutAddr = (SK_U16 *) &pAPort->CurrentMacAddress.a[0];
11260-
11261+
11262 XM_OUTADDR(IoC, PortNumber, XM_SA, OutAddr);
11263
11264 #ifdef xDEBUG
11265@@ -1024,9 +1035,9 @@
11266
11267 /* Get exact match address i from port PortNumber. */
11268 InAddr = (SK_U16 *) &InAddr8[0];
11269-
11270+
11271 XM_INADDR(IoC, PortNumber, XM_EXM(i), InAddr);
11272-
11273+
11274 SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
11275 ("SkAddrXmacMcUpdate: MC address %d on Port %u: ",
11276 "%02x %02x %02x %02x %02x %02x -- %02x %02x %02x %02x %02x %02x\n",
11277@@ -1043,7 +1054,7 @@
11278 pAPort->Exact[i].a[2],
11279 pAPort->Exact[i].a[3],
11280 pAPort->Exact[i].a[4],
11281- pAPort->Exact[i].a[5]))
11282+ pAPort->Exact[i].a[5]));
11283 }
11284 #endif /* DEBUG */
11285
11286@@ -1054,7 +1065,7 @@
11287 else {
11288 return (SK_MC_FILTERING_INEXACT);
11289 }
11290-
11291+
11292 } /* SkAddrXmacMcUpdate */
11293
11294 #endif /* GENESIS */
11295@@ -1095,37 +1106,37 @@
11296 SK_ADDR_PORT *pAPort;
11297
11298 SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
11299- ("SkAddrGmacMcUpdate on Port %u.\n", PortNumber))
11300-
11301+ ("SkAddrGmacMcUpdate on Port %u.\n", PortNumber));
11302+
11303 pAPort = &pAC->Addr.Port[PortNumber];
11304
11305 #ifdef DEBUG
11306 SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
11307- ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber]))
11308+ ("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber]));
11309 #endif /* DEBUG */
11310-
11311+
11312 #ifndef SK_SLIM
11313 for (Inexact = 0, i = 0; i < 8; i++) {
11314 Inexact |= pAPort->InexactFilter.Bytes[i];
11315 }
11316-
11317+
11318 /* Set 64-bit hash register to InexactFilter. */
11319 GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1,
11320 &pAPort->InexactFilter.Bytes[0]);
11321-
11322- if (pAPort->PromMode & SK_PROM_MODE_ALL_MC) {
11323-
11324+
11325+ if (pAPort->PromMode & SK_PROM_MODE_ALL_MC) {
11326+
11327 /* Set all bits in 64-bit hash register. */
11328 GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1, &OnesHash);
11329-
11330+
11331 /* Enable Hashing */
11332 SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
11333 }
11334- else {
11335+ else {
11336 /* Enable Hashing. */
11337 SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
11338 }
11339-
11340+
11341 if (pAPort->PromMode != SK_PROM_MODE_NONE) {
11342 (void) SkAddrGmacPromiscuousChange(pAC, IoC, PortNumber, pAPort->PromMode);
11343 }
11344@@ -1136,19 +1147,19 @@
11345
11346 /* Enable Hashing */
11347 SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
11348-
11349+
11350 (void) SkAddrGmacPromiscuousChange(pAC, IoC, PortNumber, pAPort->PromMode);
11351-
11352+
11353 #endif /* SK_SLIM */
11354-
11355+
11356 /* Set port's current physical MAC address. */
11357 OutAddr = (SK_U16 *) &pAPort->CurrentMacAddress.a[0];
11358 GM_OUTADDR(IoC, PortNumber, GM_SRC_ADDR_1L, OutAddr);
11359-
11360+
11361 /* Set port's current logical MAC address. */
11362 OutAddr = (SK_U16 *) &pAPort->Exact[0].a[0];
11363 GM_OUTADDR(IoC, PortNumber, GM_SRC_ADDR_2L, OutAddr);
11364-
11365+
11366 #ifdef DEBUG
11367 SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
11368 ("SkAddrGmacMcUpdate: Permanent Physical MAC Address: %02X %02X %02X %02X %02X %02X\n",
11369@@ -1157,8 +1168,8 @@
11370 pAPort->Exact[0].a[2],
11371 pAPort->Exact[0].a[3],
11372 pAPort->Exact[0].a[4],
11373- pAPort->Exact[0].a[5]))
11374-
11375+ pAPort->Exact[0].a[5]));
11376+
11377 SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
11378 ("SkAddrGmacMcUpdate: Physical MAC Address: %02X %02X %02X %02X %02X %02X\n",
11379 pAPort->CurrentMacAddress.a[0],
11380@@ -1166,9 +1177,9 @@
11381 pAPort->CurrentMacAddress.a[2],
11382 pAPort->CurrentMacAddress.a[3],
11383 pAPort->CurrentMacAddress.a[4],
11384- pAPort->CurrentMacAddress.a[5]))
11385+ pAPort->CurrentMacAddress.a[5]));
11386 #endif /* DEBUG */
11387-
11388+
11389 #ifndef SK_SLIM
11390 /* Determine return value. */
11391 if (Inexact == 0 && pAPort->PromMode == 0) {
11392@@ -1180,7 +1191,7 @@
11393 #else /* SK_SLIM */
11394 return (SK_MC_FILTERING_INEXACT);
11395 #endif /* SK_SLIM */
11396-
11397+
11398 } /* SkAddrGmacMcUpdate */
11399
11400 #endif /* YUKON */
11401@@ -1275,26 +1286,46 @@
11402 (void) SkAddrMcUpdate(pAC, IoC, PortNumber);
11403 }
11404 else if (Flags & SK_ADDR_PHYSICAL_ADDRESS) { /* Physical MAC address. */
11405- if (SK_ADDR_EQUAL(pNewAddr->a,
11406- pAC->Addr.Net[NetNumber].CurrentMacAddress.a)) {
11407- return (SK_ADDR_DUPLICATE_ADDRESS);
11408- }
11409-
11410 for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) {
11411 if (!pAC->Addr.Port[i].CurrentMacAddressSet) {
11412 return (SK_ADDR_TOO_EARLY);
11413 }
11414+ }
11415
11416+ /*
11417+ * In dual net mode it should be possible to set all MAC
11418+ * addresses independently. Therefore the equality checks
11419+ * against the locical address of the same port and the
11420+ * physical address of the other port are suppressed here.
11421+ */
11422+#ifndef SK_NO_RLMT
11423+ if (pAC->Rlmt.NumNets == 1) {
11424+#endif /* SK_NO_RLMT */
11425 if (SK_ADDR_EQUAL(pNewAddr->a,
11426- pAC->Addr.Port[i].CurrentMacAddress.a)) {
11427- if (i == PortNumber) {
11428- return (SK_ADDR_SUCCESS);
11429- }
11430- else {
11431- return (SK_ADDR_DUPLICATE_ADDRESS);
11432+ pAC->Addr.Net[NetNumber].CurrentMacAddress.a)) {
11433+ return (SK_ADDR_DUPLICATE_ADDRESS);
11434+ }
11435+
11436+ for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) {
11437+ if (SK_ADDR_EQUAL(pNewAddr->a,
11438+ pAC->Addr.Port[i].CurrentMacAddress.a)) {
11439+ if (i == PortNumber) {
11440+ return (SK_ADDR_SUCCESS);
11441+ }
11442+ else {
11443+ return (SK_ADDR_DUPLICATE_ADDRESS);
11444+ }
11445 }
11446 }
11447+#ifndef SK_NO_RLMT
11448 }
11449+ else {
11450+ if (SK_ADDR_EQUAL(pNewAddr->a,
11451+ pAC->Addr.Port[PortNumber].CurrentMacAddress.a)) {
11452+ return (SK_ADDR_SUCCESS);
11453+ }
11454+ }
11455+#endif /* SK_NO_RLMT */
11456
11457 pAC->Addr.Port[PortNumber].PreviousMacAddress =
11458 pAC->Addr.Port[PortNumber].CurrentMacAddress;
11459@@ -1325,18 +1356,32 @@
11460 pAC->Addr.Net[NetNumber].CurrentMacAddress.a)) {
11461 return (SK_ADDR_SUCCESS);
11462 }
11463-
11464+
11465 for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) {
11466 if (!pAC->Addr.Port[i].CurrentMacAddressSet) {
11467 return (SK_ADDR_TOO_EARLY);
11468 }
11469+ }
11470
11471- if (SK_ADDR_EQUAL(pNewAddr->a,
11472- pAC->Addr.Port[i].CurrentMacAddress.a)) {
11473- return (SK_ADDR_DUPLICATE_ADDRESS);
11474+ /*
11475+ * In dual net mode on Yukon-2 adapters the physical address
11476+ * of port 0 and the logical address of port 1 are equal - in
11477+ * this case the equality check of the physical address leads
11478+ * to an error and is suppressed here.
11479+ */
11480+#ifndef SK_NO_RLMT
11481+ if (pAC->Rlmt.NumNets == 1) {
11482+#endif /* SK_NO_RLMT */
11483+ for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) {
11484+ if (SK_ADDR_EQUAL(pNewAddr->a,
11485+ pAC->Addr.Port[i].CurrentMacAddress.a)) {
11486+ return (SK_ADDR_DUPLICATE_ADDRESS);
11487+ }
11488 }
11489+#ifndef SK_NO_RLMT
11490 }
11491-
11492+#endif /* SK_NO_RLMT */
11493+
11494 /*
11495 * In case that the physical and the logical MAC addresses are equal
11496 * we must also change the physical MAC address here.
11497@@ -1345,11 +1390,11 @@
11498 */
11499 if (SK_ADDR_EQUAL(pAC->Addr.Port[PortNumber].CurrentMacAddress.a,
11500 pAC->Addr.Port[PortNumber].Exact[0].a)) {
11501-
11502+
11503 pAC->Addr.Port[PortNumber].PreviousMacAddress =
11504 pAC->Addr.Port[PortNumber].CurrentMacAddress;
11505 pAC->Addr.Port[PortNumber].CurrentMacAddress = *pNewAddr;
11506-
11507+
11508 #ifndef SK_NO_RLMT
11509 /* Report address change to RLMT. */
11510 Para.Para32[0] = PortNumber;
11511@@ -1357,7 +1402,7 @@
11512 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_PORT_ADDR, Para);
11513 #endif /* !SK_NO_RLMT */
11514 }
11515-
11516+
11517 #ifndef SK_NO_RLMT
11518 /* Set PortNumber to number of net's active port. */
11519 PortNumber = pAC->Rlmt.Net[NetNumber].
11520@@ -1373,8 +1418,8 @@
11521 pAC->Addr.Net[NetNumber].PermanentMacAddress.a[2],
11522 pAC->Addr.Net[NetNumber].PermanentMacAddress.a[3],
11523 pAC->Addr.Net[NetNumber].PermanentMacAddress.a[4],
11524- pAC->Addr.Net[NetNumber].PermanentMacAddress.a[5]))
11525-
11526+ pAC->Addr.Net[NetNumber].PermanentMacAddress.a[5]));
11527+
11528 SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
11529 ("SkAddrOverride: New logical MAC Address: %02X %02X %02X %02X %02X %02X\n",
11530 pAC->Addr.Net[NetNumber].CurrentMacAddress.a[0],
11531@@ -1382,17 +1427,16 @@
11532 pAC->Addr.Net[NetNumber].CurrentMacAddress.a[2],
11533 pAC->Addr.Net[NetNumber].CurrentMacAddress.a[3],
11534 pAC->Addr.Net[NetNumber].CurrentMacAddress.a[4],
11535- pAC->Addr.Net[NetNumber].CurrentMacAddress.a[5]))
11536+ pAC->Addr.Net[NetNumber].CurrentMacAddress.a[5]));
11537 #endif /* DEBUG */
11538
11539- /* Write address to first exact match entry of active port. */
11540- (void) SkAddrMcUpdate(pAC, IoC, PortNumber);
11541+ /* Write address to first exact match entry of active port. */
11542+ (void)SkAddrMcUpdate(pAC, IoC, PortNumber);
11543 }
11544
11545 return (SK_ADDR_SUCCESS);
11546-
11547-} /* SkAddrOverride */
11548
11549+} /* SkAddrOverride */
11550
11551 #endif /* SK_NO_MAO */
11552
11553@@ -1424,7 +1468,8 @@
11554 SK_U32 PortNumber, /* port whose promiscuous mode changes */
11555 int NewPromMode) /* new promiscuous mode */
11556 {
11557- int ReturnCode = 0;
11558+ int ReturnCode = SK_ADDR_ILLEGAL_PORT;
11559+
11560 #if (!defined(SK_SLIM) || defined(DEBUG))
11561 if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
11562 return (SK_ADDR_ILLEGAL_PORT);
11563@@ -1489,17 +1534,18 @@
11564 /* Promiscuous mode! */
11565 CurPromMode |= SK_PROM_MODE_LLC;
11566 }
11567-
11568+
11569 for (Inexact = 0xFF, i = 0; i < 8; i++) {
11570 Inexact &= pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i];
11571 }
11572+
11573 if (Inexact == 0xFF) {
11574 CurPromMode |= (pAC->Addr.Port[PortNumber].PromMode & SK_PROM_MODE_ALL_MC);
11575 }
11576 else {
11577 /* Get InexactModeBit (bit XM_MD_ENA_HASH in mode register) */
11578 XM_IN16(IoC, PortNumber, XM_MODE, &LoMode);
11579-
11580+
11581 InexactModeBit = (LoMode & XM_MD_ENA_HASH) != 0;
11582
11583 /* Read 64-bit hash register from XMAC */
11584@@ -1522,7 +1568,7 @@
11585
11586 if ((NewPromMode & SK_PROM_MODE_ALL_MC) &&
11587 !(CurPromMode & SK_PROM_MODE_ALL_MC)) { /* All MC. */
11588-
11589+
11590 /* Set all bits in 64-bit hash register. */
11591 XM_OUTHASH(IoC, PortNumber, XM_HSM, &OnesHash);
11592
11593@@ -1558,9 +1604,9 @@
11594 /* Clear Promiscuous Mode */
11595 SkMacPromiscMode(pAC, IoC, (int) PortNumber, SK_FALSE);
11596 }
11597-
11598+
11599 return (SK_ADDR_SUCCESS);
11600-
11601+
11602 } /* SkAddrXmacPromiscuousChange */
11603
11604 #endif /* GENESIS */
11605@@ -1607,22 +1653,25 @@
11606 CurPromMode |= (pAC->Addr.Port[PortNumber].PromMode & SK_PROM_MODE_ALL_MC);
11607 }
11608
11609+ /* dummy read after GM_IN16() */
11610+ SK_IN16(IoC, B0_RAP, &ReceiveControl);
11611+
11612 pAC->Addr.Port[PortNumber].PromMode = NewPromMode;
11613
11614 if (NewPromMode == CurPromMode) {
11615 return (SK_ADDR_SUCCESS);
11616 }
11617-
11618+
11619 if ((NewPromMode & SK_PROM_MODE_ALL_MC) &&
11620 !(CurPromMode & SK_PROM_MODE_ALL_MC)) { /* All MC */
11621-
11622+
11623 /* Set all bits in 64-bit hash register. */
11624 GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1, &OnesHash);
11625-
11626+
11627 /* Enable Hashing */
11628 SkMacHashing(pAC, IoC, (int) PortNumber, SK_TRUE);
11629 }
11630-
11631+
11632 if ((CurPromMode & SK_PROM_MODE_ALL_MC) &&
11633 !(NewPromMode & SK_PROM_MODE_ALL_MC)) { /* Norm. MC */
11634
11635@@ -1636,19 +1685,19 @@
11636
11637 if ((NewPromMode & SK_PROM_MODE_LLC) &&
11638 !(CurPromMode & SK_PROM_MODE_LLC)) { /* Prom. LLC */
11639-
11640+
11641 /* Set the MAC to Promiscuous Mode. */
11642 SkMacPromiscMode(pAC, IoC, (int) PortNumber, SK_TRUE);
11643 }
11644 else if ((CurPromMode & SK_PROM_MODE_LLC) &&
11645 !(NewPromMode & SK_PROM_MODE_LLC)) { /* Norm. LLC */
11646-
11647+
11648 /* Clear Promiscuous Mode. */
11649 SkMacPromiscMode(pAC, IoC, (int) PortNumber, SK_FALSE);
11650 }
11651
11652 return (SK_ADDR_SUCCESS);
11653-
11654+
11655 } /* SkAddrGmacPromiscuousChange */
11656
11657 #endif /* YUKON */
11658@@ -1720,33 +1769,33 @@
11659 pAC->Addr.Port[ToPortNumber].InexactFilter.Bytes[i];
11660 pAC->Addr.Port[ToPortNumber].InexactFilter.Bytes[i] = Byte;
11661 }
11662-
11663+
11664 i = pAC->Addr.Port[FromPortNumber].PromMode;
11665 pAC->Addr.Port[FromPortNumber].PromMode = pAC->Addr.Port[ToPortNumber].PromMode;
11666 pAC->Addr.Port[ToPortNumber].PromMode = i;
11667-
11668+
11669 if (pAC->GIni.GIGenesis) {
11670 DWord = pAC->Addr.Port[FromPortNumber].FirstExactMatchRlmt;
11671 pAC->Addr.Port[FromPortNumber].FirstExactMatchRlmt =
11672 pAC->Addr.Port[ToPortNumber].FirstExactMatchRlmt;
11673 pAC->Addr.Port[ToPortNumber].FirstExactMatchRlmt = DWord;
11674-
11675+
11676 DWord = pAC->Addr.Port[FromPortNumber].NextExactMatchRlmt;
11677 pAC->Addr.Port[FromPortNumber].NextExactMatchRlmt =
11678 pAC->Addr.Port[ToPortNumber].NextExactMatchRlmt;
11679 pAC->Addr.Port[ToPortNumber].NextExactMatchRlmt = DWord;
11680-
11681+
11682 DWord = pAC->Addr.Port[FromPortNumber].FirstExactMatchDrv;
11683 pAC->Addr.Port[FromPortNumber].FirstExactMatchDrv =
11684 pAC->Addr.Port[ToPortNumber].FirstExactMatchDrv;
11685 pAC->Addr.Port[ToPortNumber].FirstExactMatchDrv = DWord;
11686-
11687+
11688 DWord = pAC->Addr.Port[FromPortNumber].NextExactMatchDrv;
11689 pAC->Addr.Port[FromPortNumber].NextExactMatchDrv =
11690 pAC->Addr.Port[ToPortNumber].NextExactMatchDrv;
11691 pAC->Addr.Port[ToPortNumber].NextExactMatchDrv = DWord;
11692 }
11693-
11694+
11695 /* CAUTION: Solution works if only ports of one adapter are in use. */
11696 for (i = 0; (SK_U32) i < pAC->Rlmt.Net[pAC->Rlmt.Port[ToPortNumber].
11697 Net->NetNumber].NumPorts; i++) {
11698@@ -1757,12 +1806,12 @@
11699 /* 20001207 RA: Was "ToPortNumber;". */
11700 }
11701 }
11702-
11703+
11704 (void) SkAddrMcUpdate(pAC, IoC, FromPortNumber);
11705 (void) SkAddrMcUpdate(pAC, IoC, ToPortNumber);
11706
11707 return (SK_ADDR_SUCCESS);
11708-
11709+
11710 } /* SkAddrSwap */
11711
11712 #endif /* !SK_SLIM */
11713diff -ruN linux/drivers/net/sk98lin/skcsum.c linux-new/drivers/net/sk98lin/skcsum.c
11714--- linux/drivers/net/sk98lin/skcsum.c 1970-01-01 01:00:00.000000000 +0100
11715+++ linux-new/drivers/net/sk98lin/skcsum.c 2006-01-18 14:37:24.000000000 +0100
11716@@ -0,0 +1,871 @@
11717+/******************************************************************************
11718+ *
11719+ * Name: skcsum.c
11720+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
11721+ * Version: $Revision$
11722+ * Date: $Date$
11723+ * Purpose: Store/verify Internet checksum in send/receive packets.
11724+ *
11725+ ******************************************************************************/
11726+
11727+/******************************************************************************
11728+ *
11729+ * (C)Copyright 1998-2003 SysKonnect GmbH.
11730+ *
11731+ * This program is free software; you can redistribute it and/or modify
11732+ * it under the terms of the GNU General Public License as published by
11733+ * the Free Software Foundation; either version 2 of the License, or
11734+ * (at your option) any later version.
11735+ *
11736+ * The information in this file is provided "AS IS" without warranty.
11737+ *
11738+ ******************************************************************************/
11739+
11740+#ifdef SK_USE_CSUM /* Check if CSUM is to be used. */
11741+
11742+#ifndef lint
11743+static const char SysKonnectFileId[] =
11744+ "@(#) $Id$ (C) SysKonnect.";
11745+#endif /* !lint */
11746+
11747+/******************************************************************************
11748+ *
11749+ * Description:
11750+ *
11751+ * This is the "GEnesis" common module "CSUM".
11752+ *
11753+ * This module contains the code necessary to calculate, store, and verify the
11754+ * Internet Checksum of IP, TCP, and UDP frames.
11755+ *
11756+ * "GEnesis" is an abbreviation of "Gigabit Ethernet Network System in Silicon"
11757+ * and is the code name of this SysKonnect project.
11758+ *
11759+ * Compilation Options:
11760+ *
11761+ * SK_USE_CSUM - Define if CSUM is to be used. Otherwise, CSUM will be an
11762+ * empty module.
11763+ *
11764+ * SKCS_OVERWRITE_PROTO - Define to overwrite the default protocol id
11765+ * definitions. In this case, all SKCS_PROTO_xxx definitions must be made
11766+ * external.
11767+ *
11768+ * SKCS_OVERWRITE_STATUS - Define to overwrite the default return status
11769+ * definitions. In this case, all SKCS_STATUS_xxx definitions must be made
11770+ * external.
11771+ *
11772+ * Include File Hierarchy:
11773+ *
11774+ * "h/skdrv1st.h"
11775+ * "h/skcsum.h"
11776+ * "h/sktypes.h"
11777+ * "h/skqueue.h"
11778+ * "h/skdrv2nd.h"
11779+ *
11780+ ******************************************************************************/
11781+
11782+#include "h/skdrv1st.h"
11783+#include "h/skcsum.h"
11784+#include "h/skdrv2nd.h"
11785+
11786+/* defines ********************************************************************/
11787+
11788+/* The size of an Ethernet MAC header. */
11789+#define SKCS_ETHERNET_MAC_HEADER_SIZE (6+6+2)
11790+
11791+/* The size of the used topology's MAC header. */
11792+#define SKCS_MAC_HEADER_SIZE SKCS_ETHERNET_MAC_HEADER_SIZE
11793+
11794+/* The size of the IP header without any option fields. */
11795+#define SKCS_IP_HEADER_SIZE 20
11796+
11797+/*
11798+ * Field offsets within the IP header.
11799+ */
11800+
11801+/* "Internet Header Version" and "Length". */
11802+#define SKCS_OFS_IP_HEADER_VERSION_AND_LENGTH 0
11803+
11804+/* "Total Length". */
11805+#define SKCS_OFS_IP_TOTAL_LENGTH 2
11806+
11807+/* "Flags" "Fragment Offset". */
11808+#define SKCS_OFS_IP_FLAGS_AND_FRAGMENT_OFFSET 6
11809+
11810+/* "Next Level Protocol" identifier. */
11811+#define SKCS_OFS_IP_NEXT_LEVEL_PROTOCOL 9
11812+
11813+/* Source IP address. */
11814+#define SKCS_OFS_IP_SOURCE_ADDRESS 12
11815+
11816+/* Destination IP address. */
11817+#define SKCS_OFS_IP_DESTINATION_ADDRESS 16
11818+
11819+
11820+/*
11821+ * Field offsets within the UDP header.
11822+ */
11823+
11824+/* UDP checksum. */
11825+#define SKCS_OFS_UDP_CHECKSUM 6
11826+
11827+/* IP "Next Level Protocol" identifiers (see RFC 790). */
11828+#define SKCS_PROTO_ID_TCP 6 /* Transport Control Protocol */
11829+#define SKCS_PROTO_ID_UDP 17 /* User Datagram Protocol */
11830+
11831+/* IP "Don't Fragment" bit. */
11832+#define SKCS_IP_DONT_FRAGMENT SKCS_HTON16(0x4000)
11833+
11834+/* Add a byte offset to a pointer. */
11835+#define SKCS_IDX(pPtr, Ofs) ((void *) ((char *) (pPtr) + (Ofs)))
11836+
11837+/*
11838+ * Macros that convert host to network representation and vice versa, i.e.
11839+ * little/big endian conversion on little endian machines only.
11840+ */
11841+#ifdef SK_LITTLE_ENDIAN
11842+#define SKCS_HTON16(Val16) (((unsigned) (Val16) >> 8) | (((Val16) & 0xff) << 8))
11843+#endif /* SK_LITTLE_ENDIAN */
11844+#ifdef SK_BIG_ENDIAN
11845+#define SKCS_HTON16(Val16) (Val16)
11846+#endif /* SK_BIG_ENDIAN */
11847+#define SKCS_NTOH16(Val16) SKCS_HTON16(Val16)
11848+
11849+/* typedefs *******************************************************************/
11850+
11851+/* function prototypes ********************************************************/
11852+
11853+/******************************************************************************
11854+ *
11855+ * SkCsGetSendInfo - get checksum information for a send packet
11856+ *
11857+ * Description:
11858+ * Get all checksum information necessary to send a TCP or UDP packet. The
11859+ * function checks the IP header passed to it. If the high-level protocol
11860+ * is either TCP or UDP the pseudo header checksum is calculated and
11861+ * returned.
11862+ *
11863+ * The function returns the total length of the IP header (including any
11864+ * IP option fields), which is the same as the start offset of the IP data
11865+ * which in turn is the start offset of the TCP or UDP header.
11866+ *
11867+ * The function also returns the TCP or UDP pseudo header checksum, which
11868+ * should be used as the start value for the hardware checksum calculation.
11869+ * (Note that any actual pseudo header checksum can never calculate to
11870+ * zero.)
11871+ *
11872+ * Note:
11873+ * There is a bug in the GENESIS ASIC which may lead to wrong checksums.
11874+ *
11875+ * Arguments:
11876+ * pAc - A pointer to the adapter context struct.
11877+ *
11878+ * pIpHeader - Pointer to IP header. Must be at least the IP header *not*
11879+ * including any option fields, i.e. at least 20 bytes.
11880+ *
11881+ * Note: This pointer will be used to address 8-, 16-, and 32-bit
11882+ * variables with the respective alignment offsets relative to the pointer.
11883+ * Thus, the pointer should point to a 32-bit aligned address. If the
11884+ * target system cannot address 32-bit variables on non 32-bit aligned
11885+ * addresses, then the pointer *must* point to a 32-bit aligned address.
11886+ *
11887+ * pPacketInfo - A pointer to the packet information structure for this
11888+ * packet. Before calling this SkCsGetSendInfo(), the following field must
11889+ * be initialized:
11890+ *
11891+ * ProtocolFlags - Initialize with any combination of
11892+ * SKCS_PROTO_XXX bit flags. SkCsGetSendInfo() will only work on
11893+ * the protocols specified here. Any protocol(s) not specified
11894+ * here will be ignored.
11895+ *
11896+ * Note: Only one checksum can be calculated in hardware. Thus, if
11897+ * SKCS_PROTO_IP is specified in the 'ProtocolFlags',
11898+ * SkCsGetSendInfo() must calculate the IP header checksum in
11899+ * software. It might be a better idea to have the calling
11900+ * protocol stack calculate the IP header checksum.
11901+ *
11902+ * Returns: N/A
11903+ * On return, the following fields in 'pPacketInfo' may or may not have
11904+ * been filled with information, depending on the protocol(s) found in the
11905+ * packet:
11906+ *
11907+ * ProtocolFlags - Returns the SKCS_PROTO_XXX bit flags of the protocol(s)
11908+ * that were both requested by the caller and actually found in the packet.
11909+ * Protocol(s) not specified by the caller and/or not found in the packet
11910+ * will have their respective SKCS_PROTO_XXX bit flags reset.
11911+ *
11912+ * Note: For IP fragments, TCP and UDP packet information is ignored.
11913+ *
11914+ * IpHeaderLength - The total length in bytes of the complete IP header
11915+ * including any option fields is returned here. This is the start offset
11916+ * of the IP data, i.e. the TCP or UDP header if present.
11917+ *
11918+ * IpHeaderChecksum - If IP has been specified in the 'ProtocolFlags', the
11919+ * 16-bit Internet Checksum of the IP header is returned here. This value
11920+ * is to be stored into the packet's 'IP Header Checksum' field.
11921+ *
11922+ * PseudoHeaderChecksum - If this is a TCP or UDP packet and if TCP or UDP
11923+ * has been specified in the 'ProtocolFlags', the 16-bit Internet Checksum
11924+ * of the TCP or UDP pseudo header is returned here.
11925+ */
11926+void SkCsGetSendInfo(
11927+SK_AC *pAc, /* Adapter context struct. */
11928+void *pIpHeader, /* IP header. */
11929+SKCS_PACKET_INFO *pPacketInfo, /* Packet information struct. */
11930+int NetNumber) /* Net number */
11931+{
11932+ /* Internet Header Version found in IP header. */
11933+ unsigned InternetHeaderVersion;
11934+
11935+ /* Length of the IP header as found in IP header. */
11936+ unsigned IpHeaderLength;
11937+
11938+ /* Bit field specifiying the desired/found protocols. */
11939+ unsigned ProtocolFlags;
11940+
11941+ /* Next level protocol identifier found in IP header. */
11942+ unsigned NextLevelProtocol;
11943+
11944+ /* Length of IP data portion. */
11945+ unsigned IpDataLength;
11946+
11947+ /* TCP/UDP pseudo header checksum. */
11948+ unsigned long PseudoHeaderChecksum;
11949+
11950+ /* Pointer to next level protocol statistics structure. */
11951+ SKCS_PROTO_STATS *NextLevelProtoStats;
11952+
11953+ /* Temporary variable. */
11954+ unsigned Tmp;
11955+
11956+ Tmp = *(SK_U8 *)
11957+ SKCS_IDX(pIpHeader, SKCS_OFS_IP_HEADER_VERSION_AND_LENGTH);
11958+
11959+ /* Get the Internet Header Version (IHV). */
11960+ /* Note: The IHV is stored in the upper four bits. */
11961+
11962+ InternetHeaderVersion = Tmp >> 4;
11963+
11964+ /* Check the Internet Header Version. */
11965+ /* Note: We currently only support IP version 4. */
11966+
11967+ if (InternetHeaderVersion != 4) { /* IPv4? */
11968+ SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_TX,
11969+ ("Tx: Unknown Internet Header Version %u.\n",
11970+ InternetHeaderVersion));
11971+ pPacketInfo->ProtocolFlags = 0;
11972+ pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].TxUnableCts++;
11973+ return;
11974+ }
11975+
11976+ /* Get the IP header length (IHL). */
11977+ /*
11978+ * Note: The IHL is stored in the lower four bits as the number of
11979+ * 4-byte words.
11980+ */
11981+
11982+ IpHeaderLength = (Tmp & 0xf) * 4;
11983+ pPacketInfo->IpHeaderLength = IpHeaderLength;
11984+
11985+ /* Check the IP header length. */
11986+
11987+ /* 04-Aug-1998 sw - Really check the IHL? Necessary? */
11988+
11989+ if (IpHeaderLength < 5*4) {
11990+ SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_TX,
11991+ ("Tx: Invalid IP Header Length %u.\n", IpHeaderLength));
11992+ pPacketInfo->ProtocolFlags = 0;
11993+ pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].TxUnableCts++;
11994+ return;
11995+ }
11996+
11997+ /* This is an IPv4 frame with a header of valid length. */
11998+
11999+ pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].TxOkCts++;
12000+
12001+ /* Check if we should calculate the IP header checksum. */
12002+
12003+ ProtocolFlags = pPacketInfo->ProtocolFlags;
12004+
12005+ if (ProtocolFlags & SKCS_PROTO_IP) {
12006+ pPacketInfo->IpHeaderChecksum =
12007+ SkCsCalculateChecksum(pIpHeader, IpHeaderLength);
12008+ }
12009+
12010+ /* Get the next level protocol identifier. */
12011+
12012+ NextLevelProtocol =
12013+ *(SK_U8 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_NEXT_LEVEL_PROTOCOL);
12014+
12015+ /*
12016+ * Check if this is a TCP or UDP frame and if we should calculate the
12017+ * TCP/UDP pseudo header checksum.
12018+ *
12019+ * Also clear all protocol bit flags of protocols not present in the
12020+ * frame.
12021+ */
12022+
12023+ if ((ProtocolFlags & SKCS_PROTO_TCP) != 0 &&
12024+ NextLevelProtocol == SKCS_PROTO_ID_TCP) {
12025+ /* TCP/IP frame. */
12026+ ProtocolFlags &= SKCS_PROTO_TCP | SKCS_PROTO_IP;
12027+ NextLevelProtoStats =
12028+ &pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_TCP];
12029+ }
12030+ else if ((ProtocolFlags & SKCS_PROTO_UDP) != 0 &&
12031+ NextLevelProtocol == SKCS_PROTO_ID_UDP) {
12032+ /* UDP/IP frame. */
12033+ ProtocolFlags &= SKCS_PROTO_UDP | SKCS_PROTO_IP;
12034+ NextLevelProtoStats =
12035+ &pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_UDP];
12036+ }
12037+ else {
12038+ /*
12039+ * Either not a TCP or UDP frame and/or TCP/UDP processing not
12040+ * specified.
12041+ */
12042+ pPacketInfo->ProtocolFlags = ProtocolFlags & SKCS_PROTO_IP;
12043+ return;
12044+ }
12045+
12046+ /* Check if this is an IP fragment. */
12047+
12048+ /*
12049+ * Note: An IP fragment has a non-zero "Fragment Offset" field and/or
12050+ * the "More Fragments" bit set. Thus, if both the "Fragment Offset"
12051+ * and the "More Fragments" are zero, it is *not* a fragment. We can
12052+ * easily check both at the same time since they are in the same 16-bit
12053+ * word.
12054+ */
12055+
12056+ if ((*(SK_U16 *)
12057+ SKCS_IDX(pIpHeader, SKCS_OFS_IP_FLAGS_AND_FRAGMENT_OFFSET) &
12058+ ~SKCS_IP_DONT_FRAGMENT) != 0) {
12059+ /* IP fragment; ignore all other protocols. */
12060+ pPacketInfo->ProtocolFlags = ProtocolFlags & SKCS_PROTO_IP;
12061+ NextLevelProtoStats->TxUnableCts++;
12062+ return;
12063+ }
12064+
12065+ /*
12066+ * Calculate the TCP/UDP pseudo header checksum.
12067+ */
12068+
12069+ /* Get total length of IP header and data. */
12070+
12071+ IpDataLength =
12072+ *(SK_U16 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_TOTAL_LENGTH);
12073+
12074+ /* Get length of IP data portion. */
12075+
12076+ IpDataLength = SKCS_NTOH16(IpDataLength) - IpHeaderLength;
12077+
12078+ /* Calculate the sum of all pseudo header fields (16-bit). */
12079+
12080+ PseudoHeaderChecksum =
12081+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
12082+ SKCS_OFS_IP_SOURCE_ADDRESS + 0) +
12083+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
12084+ SKCS_OFS_IP_SOURCE_ADDRESS + 2) +
12085+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
12086+ SKCS_OFS_IP_DESTINATION_ADDRESS + 0) +
12087+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
12088+ SKCS_OFS_IP_DESTINATION_ADDRESS + 2) +
12089+ (unsigned long) SKCS_HTON16(NextLevelProtocol) +
12090+ (unsigned long) SKCS_HTON16(IpDataLength);
12091+
12092+ /* Add-in any carries. */
12093+
12094+ SKCS_OC_ADD(PseudoHeaderChecksum, PseudoHeaderChecksum, 0);
12095+
12096+ /* Add-in any new carry. */
12097+
12098+ SKCS_OC_ADD(pPacketInfo->PseudoHeaderChecksum, PseudoHeaderChecksum, 0);
12099+
12100+ pPacketInfo->ProtocolFlags = ProtocolFlags;
12101+ NextLevelProtoStats->TxOkCts++; /* Success. */
12102+} /* SkCsGetSendInfo */
12103+
12104+
12105+/******************************************************************************
12106+ *
12107+ * SkCsGetReceiveInfo - verify checksum information for a received packet
12108+ *
12109+ * Description:
12110+ * Verify a received frame's checksum. The function returns a status code
12111+ * reflecting the result of the verification.
12112+ *
12113+ * Note:
12114+ * Before calling this function you have to verify that the frame is
12115+ * not padded and Checksum1 and Checksum2 are bigger than 1.
12116+ *
12117+ * Arguments:
12118+ * pAc - Pointer to adapter context struct.
12119+ *
12120+ * pIpHeader - Pointer to IP header. Must be at least the length in bytes
12121+ * of the received IP header including any option fields. For UDP packets,
12122+ * 8 additional bytes are needed to access the UDP checksum.
12123+ *
12124+ * Note: The actual length of the IP header is stored in the lower four
12125+ * bits of the first octet of the IP header as the number of 4-byte words,
12126+ * so it must be multiplied by four to get the length in bytes. Thus, the
12127+ * maximum IP header length is 15 * 4 = 60 bytes.
12128+ *
12129+ * Checksum1 - The first 16-bit Internet Checksum calculated by the
12130+ * hardware starting at the offset returned by SkCsSetReceiveFlags().
12131+ *
12132+ * Checksum2 - The second 16-bit Internet Checksum calculated by the
12133+ * hardware starting at the offset returned by SkCsSetReceiveFlags().
12134+ *
12135+ * Returns:
12136+ * SKCS_STATUS_UNKNOWN_IP_VERSION - Not an IP v4 frame.
12137+ * SKCS_STATUS_IP_CSUM_ERROR - IP checksum error.
12138+ * SKCS_STATUS_IP_CSUM_ERROR_TCP - IP checksum error in TCP frame.
12139+ * SKCS_STATUS_IP_CSUM_ERROR_UDP - IP checksum error in UDP frame
12140+ * SKCS_STATUS_IP_FRAGMENT - IP fragment (IP checksum ok).
12141+ * SKCS_STATUS_IP_CSUM_OK - IP checksum ok (not a TCP or UDP frame).
12142+ * SKCS_STATUS_TCP_CSUM_ERROR - TCP checksum error (IP checksum ok).
12143+ * SKCS_STATUS_UDP_CSUM_ERROR - UDP checksum error (IP checksum ok).
12144+ * SKCS_STATUS_TCP_CSUM_OK - IP and TCP checksum ok.
12145+ * SKCS_STATUS_UDP_CSUM_OK - IP and UDP checksum ok.
12146+ * SKCS_STATUS_IP_CSUM_OK_NO_UDP - IP checksum OK and no UDP checksum.
12147+ *
12148+ * Note: If SKCS_OVERWRITE_STATUS is defined, the SKCS_STATUS_XXX values
12149+ * returned here can be defined in some header file by the module using CSUM.
12150+ * In this way, the calling module can assign return values for its own needs,
12151+ * e.g. by assigning bit flags to the individual protocols.
12152+ */
12153+SKCS_STATUS SkCsGetReceiveInfo(
12154+SK_AC *pAc, /* Adapter context struct. */
12155+void *pIpHeader, /* IP header. */
12156+unsigned Checksum1, /* Hardware checksum 1. */
12157+unsigned Checksum2, /* Hardware checksum 2. */
12158+int NetNumber) /* Net number */
12159+{
12160+ /* Internet Header Version found in IP header. */
12161+ unsigned InternetHeaderVersion;
12162+
12163+ /* Length of the IP header as found in IP header. */
12164+ unsigned IpHeaderLength;
12165+
12166+ /* Length of IP data portion. */
12167+ unsigned IpDataLength;
12168+
12169+ /* IP header checksum. */
12170+ unsigned IpHeaderChecksum;
12171+
12172+ /* IP header options checksum, if any. */
12173+ unsigned IpOptionsChecksum;
12174+
12175+ /* IP data checksum, i.e. TCP/UDP checksum. */
12176+ unsigned IpDataChecksum;
12177+
12178+ /* Next level protocol identifier found in IP header. */
12179+ unsigned NextLevelProtocol;
12180+
12181+ /* The checksum of the "next level protocol", i.e. TCP or UDP. */
12182+ unsigned long NextLevelProtocolChecksum;
12183+
12184+ /* Pointer to next level protocol statistics structure. */
12185+ SKCS_PROTO_STATS *NextLevelProtoStats;
12186+
12187+ /* Temporary variable. */
12188+ unsigned Tmp;
12189+
12190+ Tmp = *(SK_U8 *)
12191+ SKCS_IDX(pIpHeader, SKCS_OFS_IP_HEADER_VERSION_AND_LENGTH);
12192+
12193+ /* Get the Internet Header Version (IHV). */
12194+ /* Note: The IHV is stored in the upper four bits. */
12195+
12196+ InternetHeaderVersion = Tmp >> 4;
12197+
12198+ /* Check the Internet Header Version. */
12199+ /* Note: We currently only support IP version 4. */
12200+
12201+ if (InternetHeaderVersion != 4) { /* IPv4? */
12202+ SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_RX,
12203+ ("Rx: Unknown Internet Header Version %u.\n",
12204+ InternetHeaderVersion));
12205+ pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxUnableCts++;
12206+ return (SKCS_STATUS_UNKNOWN_IP_VERSION);
12207+ }
12208+
12209+ /* Get the IP header length (IHL). */
12210+ /*
12211+ * Note: The IHL is stored in the lower four bits as the number of
12212+ * 4-byte words.
12213+ */
12214+
12215+ IpHeaderLength = (Tmp & 0xf) * 4;
12216+
12217+ /* Check the IP header length. */
12218+
12219+ /* 04-Aug-1998 sw - Really check the IHL? Necessary? */
12220+
12221+ if (IpHeaderLength < 5*4) {
12222+ SK_DBG_MSG(pAc, SK_DBGMOD_CSUM, SK_DBGCAT_ERR | SK_DBGCAT_RX,
12223+ ("Rx: Invalid IP Header Length %u.\n", IpHeaderLength));
12224+ pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxErrCts++;
12225+ return (SKCS_STATUS_IP_CSUM_ERROR);
12226+ }
12227+
12228+ /* This is an IPv4 frame with a header of valid length. */
12229+
12230+ /* Get the IP header and data checksum. */
12231+
12232+ IpDataChecksum = Checksum2;
12233+
12234+ /*
12235+ * The IP header checksum is calculated as follows:
12236+ *
12237+ * IpHeaderChecksum = Checksum1 - Checksum2
12238+ */
12239+
12240+ SKCS_OC_SUB(IpHeaderChecksum, Checksum1, Checksum2);
12241+
12242+ /* Check if any IP header options. */
12243+
12244+ if (IpHeaderLength > SKCS_IP_HEADER_SIZE) {
12245+
12246+ /* Get the IP options checksum. */
12247+
12248+ IpOptionsChecksum = SkCsCalculateChecksum(
12249+ SKCS_IDX(pIpHeader, SKCS_IP_HEADER_SIZE),
12250+ IpHeaderLength - SKCS_IP_HEADER_SIZE);
12251+
12252+ /* Adjust the IP header and IP data checksums. */
12253+
12254+ SKCS_OC_ADD(IpHeaderChecksum, IpHeaderChecksum, IpOptionsChecksum);
12255+
12256+ SKCS_OC_SUB(IpDataChecksum, IpDataChecksum, IpOptionsChecksum);
12257+ }
12258+
12259+ /*
12260+ * Check if the IP header checksum is ok.
12261+ *
12262+ * NOTE: We must check the IP header checksum even if the caller just wants
12263+ * us to check upper-layer checksums, because we cannot do any further
12264+ * processing of the packet without a valid IP checksum.
12265+ */
12266+
12267+ /* Get the next level protocol identifier. */
12268+
12269+ NextLevelProtocol = *(SK_U8 *)
12270+ SKCS_IDX(pIpHeader, SKCS_OFS_IP_NEXT_LEVEL_PROTOCOL);
12271+
12272+ if (IpHeaderChecksum != 0xffff) {
12273+ pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_IP].RxErrCts++;
12274+ /* the NDIS tester wants to know the upper level protocol too */
12275+ if (NextLevelProtocol == SKCS_PROTO_ID_TCP) {
12276+ return(SKCS_STATUS_IP_CSUM_ERROR_TCP);
12277+ }
12278+ else if (NextLevelProtocol == SKCS_PROTO_ID_UDP) {
12279+ return(SKCS_STATUS_IP_CSUM_ERROR_UDP);
12280+ }
12281+ return (SKCS_STATUS_IP_CSUM_ERROR);
12282+ }
12283+
12284+ /*
12285+ * Check if this is a TCP or UDP frame and if we should calculate the
12286+ * TCP/UDP pseudo header checksum.
12287+ *
12288+ * Also clear all protocol bit flags of protocols not present in the
12289+ * frame.
12290+ */
12291+
12292+ if ((pAc->Csum.ReceiveFlags[NetNumber] & SKCS_PROTO_TCP) != 0 &&
12293+ NextLevelProtocol == SKCS_PROTO_ID_TCP) {
12294+ /* TCP/IP frame. */
12295+ NextLevelProtoStats =
12296+ &pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_TCP];
12297+ }
12298+ else if ((pAc->Csum.ReceiveFlags[NetNumber] & SKCS_PROTO_UDP) != 0 &&
12299+ NextLevelProtocol == SKCS_PROTO_ID_UDP) {
12300+ /* UDP/IP frame. */
12301+ NextLevelProtoStats =
12302+ &pAc->Csum.ProtoStats[NetNumber][SKCS_PROTO_STATS_UDP];
12303+ }
12304+ else {
12305+ /*
12306+ * Either not a TCP or UDP frame and/or TCP/UDP processing not
12307+ * specified.
12308+ */
12309+ return (SKCS_STATUS_IP_CSUM_OK);
12310+ }
12311+
12312+ /* Check if this is an IP fragment. */
12313+
12314+ /*
12315+ * Note: An IP fragment has a non-zero "Fragment Offset" field and/or
12316+ * the "More Fragments" bit set. Thus, if both the "Fragment Offset"
12317+ * and the "More Fragments" are zero, it is *not* a fragment. We can
12318+ * easily check both at the same time since they are in the same 16-bit
12319+ * word.
12320+ */
12321+
12322+ if ((*(SK_U16 *)
12323+ SKCS_IDX(pIpHeader, SKCS_OFS_IP_FLAGS_AND_FRAGMENT_OFFSET) &
12324+ ~SKCS_IP_DONT_FRAGMENT) != 0) {
12325+ /* IP fragment; ignore all other protocols. */
12326+ NextLevelProtoStats->RxUnableCts++;
12327+ return (SKCS_STATUS_IP_FRAGMENT);
12328+ }
12329+
12330+ /*
12331+ * 08-May-2000 ra
12332+ *
12333+ * From RFC 768 (UDP)
12334+ * If the computed checksum is zero, it is transmitted as all ones (the
12335+ * equivalent in one's complement arithmetic). An all zero transmitted
12336+ * checksum value means that the transmitter generated no checksum (for
12337+ * debugging or for higher level protocols that don't care).
12338+ */
12339+
12340+ if (NextLevelProtocol == SKCS_PROTO_ID_UDP &&
12341+ *(SK_U16*)SKCS_IDX(pIpHeader, IpHeaderLength + 6) == 0x0000) {
12342+
12343+ NextLevelProtoStats->RxOkCts++;
12344+
12345+ return (SKCS_STATUS_IP_CSUM_OK_NO_UDP);
12346+ }
12347+
12348+ /*
12349+ * Calculate the TCP/UDP checksum.
12350+ */
12351+
12352+ /* Get total length of IP header and data. */
12353+
12354+ IpDataLength =
12355+ *(SK_U16 *) SKCS_IDX(pIpHeader, SKCS_OFS_IP_TOTAL_LENGTH);
12356+
12357+ /* Get length of IP data portion. */
12358+
12359+ IpDataLength = SKCS_NTOH16(IpDataLength) - IpHeaderLength;
12360+
12361+ NextLevelProtocolChecksum =
12362+
12363+ /* Calculate the pseudo header checksum. */
12364+
12365+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
12366+ SKCS_OFS_IP_SOURCE_ADDRESS + 0) +
12367+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
12368+ SKCS_OFS_IP_SOURCE_ADDRESS + 2) +
12369+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
12370+ SKCS_OFS_IP_DESTINATION_ADDRESS + 0) +
12371+ (unsigned long) *(SK_U16 *) SKCS_IDX(pIpHeader,
12372+ SKCS_OFS_IP_DESTINATION_ADDRESS + 2) +
12373+ (unsigned long) SKCS_HTON16(NextLevelProtocol) +
12374+ (unsigned long) SKCS_HTON16(IpDataLength) +
12375+
12376+ /* Add the TCP/UDP header checksum. */
12377+
12378+ (unsigned long) IpDataChecksum;
12379+
12380+ /* Add-in any carries. */
12381+
12382+ SKCS_OC_ADD(NextLevelProtocolChecksum, NextLevelProtocolChecksum, 0);
12383+
12384+ /* Add-in any new carry. */
12385+
12386+ SKCS_OC_ADD(NextLevelProtocolChecksum, NextLevelProtocolChecksum, 0);
12387+
12388+ /* Check if the TCP/UDP checksum is ok. */
12389+
12390+ if ((unsigned) NextLevelProtocolChecksum == 0xffff) {
12391+
12392+ /* TCP/UDP checksum ok. */
12393+
12394+ NextLevelProtoStats->RxOkCts++;
12395+
12396+ return (NextLevelProtocol == SKCS_PROTO_ID_TCP ?
12397+ SKCS_STATUS_TCP_CSUM_OK : SKCS_STATUS_UDP_CSUM_OK);
12398+ }
12399+
12400+ /* TCP/UDP checksum error. */
12401+
12402+ NextLevelProtoStats->RxErrCts++;
12403+
12404+ return (NextLevelProtocol == SKCS_PROTO_ID_TCP ?
12405+ SKCS_STATUS_TCP_CSUM_ERROR : SKCS_STATUS_UDP_CSUM_ERROR);
12406+} /* SkCsGetReceiveInfo */
12407+
12408+
12409+/******************************************************************************
12410+ *
12411+ * SkCsSetReceiveFlags - set checksum receive flags
12412+ *
12413+ * Description:
12414+ * Use this function to set the various receive flags. According to the
12415+ * protocol flags set by the caller, the start offsets within received
12416+ * packets of the two hardware checksums are returned. These offsets must
12417+ * be stored in all receive descriptors.
12418+ *
12419+ * Arguments:
12420+ * pAc - Pointer to adapter context struct.
12421+ *
12422+ * ReceiveFlags - Any combination of SK_PROTO_XXX flags of the protocols
12423+ * for which the caller wants checksum information on received frames.
12424+ *
12425+ * pChecksum1Offset - The start offset of the first receive descriptor
12426+ * hardware checksum to be calculated for received frames is returned
12427+ * here.
12428+ *
12429+ * pChecksum2Offset - The start offset of the second receive descriptor
12430+ * hardware checksum to be calculated for received frames is returned
12431+ * here.
12432+ *
12433+ * Returns: N/A
12434+ * Returns the two hardware checksum start offsets.
12435+ */
12436+void SkCsSetReceiveFlags(
12437+SK_AC *pAc, /* Adapter context struct. */
12438+unsigned ReceiveFlags, /* New receive flags. */
12439+unsigned *pChecksum1Offset, /* Offset for hardware checksum 1. */
12440+unsigned *pChecksum2Offset, /* Offset for hardware checksum 2. */
12441+int NetNumber)
12442+{
12443+ /* Save the receive flags. */
12444+
12445+ pAc->Csum.ReceiveFlags[NetNumber] = ReceiveFlags;
12446+
12447+ /* First checksum start offset is the IP header. */
12448+ *pChecksum1Offset = SKCS_MAC_HEADER_SIZE;
12449+
12450+ /*
12451+ * Second checksum start offset is the IP data. Note that this may vary
12452+ * if there are any IP header options in the actual packet.
12453+ */
12454+ *pChecksum2Offset = SKCS_MAC_HEADER_SIZE + SKCS_IP_HEADER_SIZE;
12455+} /* SkCsSetReceiveFlags */
12456+
12457+#ifndef SK_CS_CALCULATE_CHECKSUM
12458+
12459+/******************************************************************************
12460+ *
12461+ * SkCsCalculateChecksum - calculate checksum for specified data
12462+ *
12463+ * Description:
12464+ * Calculate and return the 16-bit Internet Checksum for the specified
12465+ * data.
12466+ *
12467+ * Arguments:
12468+ * pData - Pointer to data for which the checksum shall be calculated.
12469+ * Note: The pointer should be aligned on a 16-bit boundary.
12470+ *
12471+ * Length - Length in bytes of data to checksum.
12472+ *
12473+ * Returns:
12474+ * The 16-bit Internet Checksum for the specified data.
12475+ *
12476+ * Note: The checksum is calculated in the machine's natural byte order,
12477+ * i.e. little vs. big endian. Thus, the resulting checksum is different
12478+ * for the same input data on little and big endian machines.
12479+ *
12480+ * However, when written back to the network packet, the byte order is
12481+ * always in correct network order.
12482+ */
12483+unsigned SkCsCalculateChecksum(
12484+void *pData, /* Data to checksum. */
12485+unsigned Length) /* Length of data. */
12486+{
12487+ SK_U16 *pU16; /* Pointer to the data as 16-bit words. */
12488+ unsigned long Checksum; /* Checksum; must be at least 32 bits. */
12489+
12490+ /* Sum up all 16-bit words. */
12491+
12492+ pU16 = (SK_U16 *) pData;
12493+ for (Checksum = 0; Length > 1; Length -= 2) {
12494+ Checksum += *pU16++;
12495+ }
12496+
12497+ /* If this is an odd number of bytes, add-in the last byte. */
12498+
12499+ if (Length > 0) {
12500+#ifdef SK_BIG_ENDIAN
12501+ /* Add the last byte as the high byte. */
12502+ Checksum += ((unsigned) *(SK_U8 *) pU16) << 8;
12503+#else /* !SK_BIG_ENDIAN */
12504+ /* Add the last byte as the low byte. */
12505+ Checksum += *(SK_U8 *) pU16;
12506+#endif /* !SK_BIG_ENDIAN */
12507+ }
12508+
12509+ /* Add-in any carries. */
12510+
12511+ SKCS_OC_ADD(Checksum, Checksum, 0);
12512+
12513+ /* Add-in any new carry. */
12514+
12515+ SKCS_OC_ADD(Checksum, Checksum, 0);
12516+
12517+ /* Note: All bits beyond the 16-bit limit are now zero. */
12518+
12519+ return ((unsigned) Checksum);
12520+} /* SkCsCalculateChecksum */
12521+
12522+#endif /* SK_CS_CALCULATE_CHECKSUM */
12523+
12524+/******************************************************************************
12525+ *
12526+ * SkCsEvent - the CSUM event dispatcher
12527+ *
12528+ * Description:
12529+ * This is the event handler for the CSUM module.
12530+ *
12531+ * Arguments:
12532+ * pAc - Pointer to adapter context.
12533+ *
12534+ * Ioc - I/O context.
12535+ *
12536+ * Event - Event id.
12537+ *
12538+ * Param - Event dependent parameter.
12539+ *
12540+ * Returns:
12541+ * The 16-bit Internet Checksum for the specified data.
12542+ *
12543+ * Note: The checksum is calculated in the machine's natural byte order,
12544+ * i.e. little vs. big endian. Thus, the resulting checksum is different
12545+ * for the same input data on little and big endian machines.
12546+ *
12547+ * However, when written back to the network packet, the byte order is
12548+ * always in correct network order.
12549+ */
12550+int SkCsEvent(
12551+SK_AC *pAc, /* Pointer to adapter context. */
12552+SK_IOC Ioc, /* I/O context. */
12553+SK_U32 Event, /* Event id. */
12554+SK_EVPARA Param) /* Event dependent parameter. */
12555+{
12556+ int ProtoIndex;
12557+ int NetNumber;
12558+
12559+ switch (Event) {
12560+ /*
12561+ * Clear protocol statistics.
12562+ *
12563+ * Param - Protocol index, or -1 for all protocols.
12564+ * - Net number.
12565+ */
12566+ case SK_CSUM_EVENT_CLEAR_PROTO_STATS:
12567+
12568+ ProtoIndex = (int)Param.Para32[1];
12569+ NetNumber = (int)Param.Para32[0];
12570+ if (ProtoIndex < 0) { /* Clear for all protocols. */
12571+ if (NetNumber >= 0) {
12572+ SK_MEMSET(&pAc->Csum.ProtoStats[NetNumber][0], 0,
12573+ sizeof(pAc->Csum.ProtoStats[NetNumber]));
12574+ }
12575+ }
12576+ else { /* Clear for individual protocol. */
12577+ SK_MEMSET(&pAc->Csum.ProtoStats[NetNumber][ProtoIndex], 0,
12578+ sizeof(pAc->Csum.ProtoStats[NetNumber][ProtoIndex]));
12579+ }
12580+ break;
12581+ default:
12582+ break;
12583+ }
12584+ return (0); /* Success. */
12585+} /* SkCsEvent */
12586+
12587+#endif /* SK_USE_CSUM */
12588diff -ruN linux/drivers/net/sk98lin/skdim.c linux-new/drivers/net/sk98lin/skdim.c
12589--- linux/drivers/net/sk98lin/skdim.c 2006-04-11 19:19:28.000000000 +0200
12590+++ linux-new/drivers/net/sk98lin/skdim.c 2006-01-18 14:37:24.000000000 +0100
12591@@ -1,17 +1,25 @@
12592 /******************************************************************************
12593 *
12594- * Name: skdim.c
12595- * Project: GEnesis, PCI Gigabit Ethernet Adapter
12596- * Version: $Revision$
12597- * Date: $Date$
12598- * Purpose: All functions to maintain interrupt moderation
12599+ * Name: skdim.c
12600+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
12601+ * Version: $Revision$
12602+ * Date: $Date$
12603+ * Purpose: All functions regardig interrupt moderation
12604 *
12605 ******************************************************************************/
12606
12607 /******************************************************************************
12608 *
12609 * (C)Copyright 1998-2002 SysKonnect GmbH.
12610- * (C)Copyright 2002-2003 Marvell.
12611+ * (C)Copyright 2002-2005 Marvell.
12612+ *
12613+ * Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet
12614+ * Server Adapters.
12615+ *
12616+ * Author: Ralph Roesler (rroesler@syskonnect.de)
12617+ * Mirko Lindner (mlindner@syskonnect.de)
12618+ *
12619+ * Address all question to: linux@syskonnect.de
12620 *
12621 * This program is free software; you can redistribute it and/or modify
12622 * it under the terms of the GNU General Public License as published by
12623@@ -20,723 +28,367 @@
12624 *
12625 * The information in this file is provided "AS IS" without warranty.
12626 *
12627- ******************************************************************************/
12628+ *****************************************************************************/
12629
12630-/******************************************************************************
12631- *
12632- * Description:
12633- *
12634- * This module is intended to manage the dynamic interrupt moderation on both
12635- * GEnesis and Yukon adapters.
12636- *
12637- * Include File Hierarchy:
12638- *
12639- * "skdrv1st.h"
12640- * "skdrv2nd.h"
12641- *
12642- ******************************************************************************/
12643-
12644-#ifndef lint
12645-static const char SysKonnectFileId[] =
12646- "@(#) $Id$ (C) SysKonnect.";
12647-#endif
12648-
12649-#define __SKADDR_C
12650-
12651-#ifdef __cplusplus
12652-#error C++ is not yet supported.
12653-extern "C" {
12654-#endif
12655-
12656-/*******************************************************************************
12657-**
12658-** Includes
12659-**
12660-*******************************************************************************/
12661-
12662-#ifndef __INC_SKDRV1ST_H
12663 #include "h/skdrv1st.h"
12664-#endif
12665-
12666-#ifndef __INC_SKDRV2ND_H
12667 #include "h/skdrv2nd.h"
12668-#endif
12669
12670-#include <linux/kernel_stat.h>
12671-
12672-/*******************************************************************************
12673-**
12674-** Defines
12675-**
12676-*******************************************************************************/
12677-
12678-/*******************************************************************************
12679-**
12680-** Typedefs
12681-**
12682-*******************************************************************************/
12683+/******************************************************************************
12684+ *
12685+ * Local Function Prototypes
12686+ *
12687+ *****************************************************************************/
12688
12689-/*******************************************************************************
12690-**
12691-** Local function prototypes
12692-**
12693-*******************************************************************************/
12694-
12695-static unsigned int GetCurrentSystemLoad(SK_AC *pAC);
12696-static SK_U64 GetIsrCalls(SK_AC *pAC);
12697-static SK_BOOL IsIntModEnabled(SK_AC *pAC);
12698-static void SetCurrIntCtr(SK_AC *pAC);
12699-static void EnableIntMod(SK_AC *pAC);
12700-static void DisableIntMod(SK_AC *pAC);
12701-static void ResizeDimTimerDuration(SK_AC *pAC);
12702-static void DisplaySelectedModerationType(SK_AC *pAC);
12703-static void DisplaySelectedModerationMask(SK_AC *pAC);
12704-static void DisplayDescrRatio(SK_AC *pAC);
12705+static SK_U64 getIsrCalls(SK_AC *pAC);
12706+static SK_BOOL isIntModEnabled(SK_AC *pAC);
12707+static void setCurrIntCtr(SK_AC *pAC);
12708+static void enableIntMod(SK_AC *pAC);
12709+static void disableIntMod(SK_AC *pAC);
12710
12711-/*******************************************************************************
12712-**
12713-** Global variables
12714-**
12715-*******************************************************************************/
12716+#define M_DIMINFO pAC->DynIrqModInfo
12717
12718-/*******************************************************************************
12719-**
12720-** Local variables
12721-**
12722-*******************************************************************************/
12723+/******************************************************************************
12724+ *
12725+ * Global Functions
12726+ *
12727+ *****************************************************************************/
12728
12729-/*******************************************************************************
12730-**
12731-** Global functions
12732-**
12733-*******************************************************************************/
12734+/*****************************************************************************
12735+ *
12736+ * SkDimModerate - Moderates the IRQs depending on the current needs
12737+ *
12738+ * Description:
12739+ * Moderation of IRQs depends on the number of occurred IRQs with
12740+ * respect to the previous moderation cycle.
12741+ *
12742+ * Returns: N/A
12743+ *
12744+ */
12745+void SkDimModerate(
12746+SK_AC *pAC) /* pointer to adapter control context */
12747+{
12748+ SK_U64 IsrCalls = getIsrCalls(pAC);
12749+
12750+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==> SkDimModerate\n"));
12751+
12752+ if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
12753+ if (isIntModEnabled(pAC)) {
12754+ if (IsrCalls < M_DIMINFO.MaxModIntsPerSecLowerLimit) {
12755+ disableIntMod(pAC);
12756+ }
12757+ } else {
12758+ if (IsrCalls > M_DIMINFO.MaxModIntsPerSecUpperLimit) {
12759+ enableIntMod(pAC);
12760+ }
12761+ }
12762+ }
12763+ setCurrIntCtr(pAC);
12764
12765-/*******************************************************************************
12766-** Function : SkDimModerate
12767-** Description : Called in every ISR to check if moderation is to be applied
12768-** or not for the current number of interrupts
12769-** Programmer : Ralph Roesler
12770-** Last Modified: 22-mar-03
12771-** Returns : void (!)
12772-** Notes : -
12773-*******************************************************************************/
12774-
12775-void
12776-SkDimModerate(SK_AC *pAC) {
12777- unsigned int CurrSysLoad = 0; /* expressed in percent */
12778- unsigned int LoadIncrease = 0; /* expressed in percent */
12779- SK_U64 ThresholdInts = 0;
12780- SK_U64 IsrCallsPerSec = 0;
12781+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("<== SkDimModerate\n"));
12782+}
12783
12784-#define M_DIMINFO pAC->DynIrqModInfo
12785+/*****************************************************************************
12786+ *
12787+ * SkDimStartModerationTimer - Starts the moderation timer
12788+ *
12789+ * Description:
12790+ * Dynamic interrupt moderation is regularly checked using the
12791+ * so-called moderation timer. This timer is started with this function.
12792+ *
12793+ * Returns: N/A
12794+ */
12795+void SkDimStartModerationTimer(
12796+SK_AC *pAC) /* pointer to adapter control context */
12797+{
12798+ SK_EVPARA EventParam; /* Event struct for timer event */
12799+
12800+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
12801+ ("==> SkDimStartModerationTimer\n"));
12802
12803- if (!IsIntModEnabled(pAC)) {
12804- if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
12805- CurrSysLoad = GetCurrentSystemLoad(pAC);
12806- if (CurrSysLoad > 75) {
12807- /*
12808- ** More than 75% total system load! Enable the moderation
12809- ** to shield the system against too many interrupts.
12810- */
12811- EnableIntMod(pAC);
12812- } else if (CurrSysLoad > M_DIMINFO.PrevSysLoad) {
12813- LoadIncrease = (CurrSysLoad - M_DIMINFO.PrevSysLoad);
12814- if (LoadIncrease > ((M_DIMINFO.PrevSysLoad *
12815- C_INT_MOD_ENABLE_PERCENTAGE) / 100)) {
12816- if (CurrSysLoad > 10) {
12817- /*
12818- ** More than 50% increase with respect to the
12819- ** previous load of the system. Most likely this
12820- ** is due to our ISR-proc...
12821- */
12822- EnableIntMod(pAC);
12823- }
12824- }
12825- } else {
12826- /*
12827- ** Neither too much system load at all nor too much increase
12828- ** with respect to the previous system load. Hence, we can leave
12829- ** the ISR-handling like it is without enabling moderation.
12830- */
12831- }
12832- M_DIMINFO.PrevSysLoad = CurrSysLoad;
12833- }
12834- } else {
12835- if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
12836- ThresholdInts = ((M_DIMINFO.MaxModIntsPerSec *
12837- C_INT_MOD_DISABLE_PERCENTAGE) / 100);
12838- IsrCallsPerSec = GetIsrCalls(pAC);
12839- if (IsrCallsPerSec <= ThresholdInts) {
12840- /*
12841- ** The number of interrupts within the last second is
12842- ** lower than the disable_percentage of the desried
12843- ** maxrate. Therefore we can disable the moderation.
12844- */
12845- DisableIntMod(pAC);
12846- M_DIMINFO.MaxModIntsPerSec =
12847- (M_DIMINFO.MaxModIntsPerSecUpperLimit +
12848- M_DIMINFO.MaxModIntsPerSecLowerLimit) / 2;
12849- } else {
12850- /*
12851- ** The number of interrupts per sec is the same as expected.
12852- ** Evalulate the descriptor-ratio. If it has changed, a resize
12853- ** in the moderation timer might be useful
12854- */
12855- if (M_DIMINFO.AutoSizing) {
12856- ResizeDimTimerDuration(pAC);
12857- }
12858- }
12859- }
12860- }
12861-
12862- /*
12863- ** Some information to the log...
12864- */
12865- if (M_DIMINFO.DisplayStats) {
12866- DisplaySelectedModerationType(pAC);
12867- DisplaySelectedModerationMask(pAC);
12868- DisplayDescrRatio(pAC);
12869- }
12870+ if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
12871+ SK_MEMSET((char *) &EventParam, 0, sizeof(EventParam));
12872+ EventParam.Para32[0] = SK_DRV_MODERATION_TIMER;
12873+ SkTimerStart(pAC, pAC->IoBase,
12874+ &pAC->DynIrqModInfo.ModTimer,
12875+ pAC->DynIrqModInfo.DynIrqModSampleInterval * 1000000,
12876+ SKGE_DRV, SK_DRV_TIMER, EventParam);
12877+ }
12878
12879- M_DIMINFO.NbrProcessedDescr = 0;
12880- SetCurrIntCtr(pAC);
12881+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
12882+ ("<== SkDimStartModerationTimer\n"));
12883 }
12884
12885-/*******************************************************************************
12886-** Function : SkDimStartModerationTimer
12887-** Description : Starts the audit-timer for the dynamic interrupt moderation
12888-** Programmer : Ralph Roesler
12889-** Last Modified: 22-mar-03
12890-** Returns : void (!)
12891-** Notes : -
12892-*******************************************************************************/
12893-
12894-void
12895-SkDimStartModerationTimer(SK_AC *pAC) {
12896- SK_EVPARA EventParam; /* Event struct for timer event */
12897-
12898- SK_MEMSET((char *) &EventParam, 0, sizeof(EventParam));
12899- EventParam.Para32[0] = SK_DRV_MODERATION_TIMER;
12900- SkTimerStart(pAC, pAC->IoBase, &pAC->DynIrqModInfo.ModTimer,
12901- SK_DRV_MODERATION_TIMER_LENGTH,
12902- SKGE_DRV, SK_DRV_TIMER, EventParam);
12903-}
12904+/*****************************************************************************
12905+ *
12906+ * SkDimEnableModerationIfNeeded - Enables or disables any moderationtype
12907+ *
12908+ * Description:
12909+ * This function effectively initializes the IRQ moderation of a network
12910+ * adapter. Depending on the configuration, this might be either static
12911+ * or dynamic. If no moderation is configured, this function will do
12912+ * nothing.
12913+ *
12914+ * Returns: N/A
12915+ */
12916+void SkDimEnableModerationIfNeeded(
12917+SK_AC *pAC) /* pointer to adapter control context */
12918+{
12919+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
12920+ ("==> SkDimEnableModerationIfNeeded\n"));
12921+
12922+ if (M_DIMINFO.IntModTypeSelect != C_INT_MOD_NONE) {
12923+ if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_STATIC) {
12924+ enableIntMod(pAC);
12925+ } else { /* must be C_INT_MOD_DYNAMIC */
12926+ SkDimStartModerationTimer(pAC);
12927+ }
12928+ }
12929
12930-/*******************************************************************************
12931-** Function : SkDimEnableModerationIfNeeded
12932-** Description : Either enables or disables moderation
12933-** Programmer : Ralph Roesler
12934-** Last Modified: 22-mar-03
12935-** Returns : void (!)
12936-** Notes : This function is called when a particular adapter is opened
12937-** There is no Disable function, because when all interrupts
12938-** might be disable, the moderation timer has no meaning at all
12939-******************************************************************************/
12940-
12941-void
12942-SkDimEnableModerationIfNeeded(SK_AC *pAC) {
12943-
12944- if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_STATIC) {
12945- EnableIntMod(pAC); /* notification print in this function */
12946- } else if (M_DIMINFO.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
12947- SkDimStartModerationTimer(pAC);
12948- if (M_DIMINFO.DisplayStats) {
12949- printk("Dynamic moderation has been enabled\n");
12950- }
12951- } else {
12952- if (M_DIMINFO.DisplayStats) {
12953- printk("No moderation has been enabled\n");
12954- }
12955- }
12956+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
12957+ ("<== SkDimEnableModerationIfNeeded\n"));
12958 }
12959
12960-/*******************************************************************************
12961-** Function : SkDimDisplayModerationSettings
12962-** Description : Displays the current settings regaring interrupt moderation
12963-** Programmer : Ralph Roesler
12964-** Last Modified: 22-mar-03
12965-** Returns : void (!)
12966-** Notes : -
12967-*******************************************************************************/
12968-
12969-void
12970-SkDimDisplayModerationSettings(SK_AC *pAC) {
12971- DisplaySelectedModerationType(pAC);
12972- DisplaySelectedModerationMask(pAC);
12973-}
12974+/*****************************************************************************
12975+ *
12976+ * SkDimDisableModeration - disables moderation if it is enabled
12977+ *
12978+ * Description:
12979+ * Disabling of the moderation requires that is enabled already.
12980+ *
12981+ * Returns: N/A
12982+ */
12983+void SkDimDisableModeration(
12984+SK_AC *pAC, /* pointer to adapter control context */
12985+int CurrentModeration) /* type of current moderation */
12986+{
12987+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
12988+ ("==> SkDimDisableModeration\n"));
12989+
12990+ if (M_DIMINFO.IntModTypeSelect != C_INT_MOD_NONE) {
12991+ if (CurrentModeration == C_INT_MOD_STATIC) {
12992+ disableIntMod(pAC);
12993+ } else { /* must be C_INT_MOD_DYNAMIC */
12994+ SkTimerStop(pAC, pAC->IoBase, &M_DIMINFO.ModTimer);
12995+ disableIntMod(pAC);
12996+ }
12997+ }
12998
12999-/*******************************************************************************
13000-**
13001-** Local functions
13002-**
13003-*******************************************************************************/
13004+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
13005+ ("<== SkDimDisableModeration\n"));
13006+}
13007
13008-/*******************************************************************************
13009-** Function : GetCurrentSystemLoad
13010-** Description : Retrieves the current system load of the system. This load
13011-** is evaluated for all processors within the system.
13012-** Programmer : Ralph Roesler
13013-** Last Modified: 22-mar-03
13014-** Returns : unsigned int: load expressed in percentage
13015-** Notes : The possible range being returned is from 0 up to 100.
13016-** Whereas 0 means 'no load at all' and 100 'system fully loaded'
13017-** It is impossible to determine what actually causes the system
13018-** to be in 100%, but maybe that is due to too much interrupts.
13019-*******************************************************************************/
13020-
13021-static unsigned int
13022-GetCurrentSystemLoad(SK_AC *pAC) {
13023- unsigned long jif = jiffies;
13024- unsigned int UserTime = 0;
13025- unsigned int SystemTime = 0;
13026- unsigned int NiceTime = 0;
13027- unsigned int IdleTime = 0;
13028- unsigned int TotalTime = 0;
13029- unsigned int UsedTime = 0;
13030- unsigned int SystemLoad = 0;
13031+/******************************************************************************
13032+ *
13033+ * Local Functions
13034+ *
13035+ *****************************************************************************/
13036
13037- /* unsigned int NbrCpu = 0; */
13038+/*****************************************************************************
13039+ *
13040+ * getIsrCalls - evaluate the number of IRQs handled in mod interval
13041+ *
13042+ * Description:
13043+ * Depending on the selected moderation mask, this function will return
13044+ * the number of interrupts handled in the previous moderation interval.
13045+ * This evaluated number is based on the current number of interrupts
13046+ * stored in PNMI-context and the previous stored interrupts.
13047+ *
13048+ * Returns:
13049+ * the number of IRQs handled
13050+ */
13051+static SK_U64 getIsrCalls(
13052+SK_AC *pAC) /* pointer to adapter control context */
13053+{
13054+ SK_U64 RxPort0IntDiff = 0, RxPort1IntDiff = 0;
13055+ SK_U64 TxPort0IntDiff = 0, TxPort1IntDiff = 0;
13056+ SK_U64 StatusPort0IntDiff = 0, StatusPort1IntDiff = 0;
13057+
13058+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==>getIsrCalls\n"));
13059+
13060+ if (!CHIP_ID_YUKON_2(pAC)) {
13061+ if ((M_DIMINFO.MaskIrqModeration == IRQ_MASK_TX_ONLY) ||
13062+ (M_DIMINFO.MaskIrqModeration == IRQ_MASK_SP_TX)) {
13063+ if (pAC->GIni.GIMacsFound == 2) {
13064+ TxPort1IntDiff =
13065+ pAC->Pnmi.Port[1].TxIntrCts -
13066+ M_DIMINFO.PrevPort1TxIntrCts;
13067+ }
13068+ TxPort0IntDiff = pAC->Pnmi.Port[0].TxIntrCts -
13069+ M_DIMINFO.PrevPort0TxIntrCts;
13070+ } else if ((M_DIMINFO.MaskIrqModeration == IRQ_MASK_RX_ONLY) ||
13071+ (M_DIMINFO.MaskIrqModeration == IRQ_MASK_SP_RX)) {
13072+ if (pAC->GIni.GIMacsFound == 2) {
13073+ RxPort1IntDiff =
13074+ pAC->Pnmi.Port[1].RxIntrCts -
13075+ M_DIMINFO.PrevPort1RxIntrCts;
13076+ }
13077+ RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts -
13078+ M_DIMINFO.PrevPort0RxIntrCts;
13079+ } else {
13080+ if (pAC->GIni.GIMacsFound == 2) {
13081+ RxPort1IntDiff =
13082+ pAC->Pnmi.Port[1].RxIntrCts -
13083+ M_DIMINFO.PrevPort1RxIntrCts;
13084+ TxPort1IntDiff =
13085+ pAC->Pnmi.Port[1].TxIntrCts -
13086+ M_DIMINFO.PrevPort1TxIntrCts;
13087+ }
13088+ RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts -
13089+ M_DIMINFO.PrevPort0RxIntrCts;
13090+ TxPort0IntDiff = pAC->Pnmi.Port[0].TxIntrCts -
13091+ M_DIMINFO.PrevPort0TxIntrCts;
13092+ }
13093+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
13094+ ("==>getIsrCalls (!CHIP_ID_YUKON_2)\n"));
13095+ return (RxPort0IntDiff + RxPort1IntDiff +
13096+ TxPort0IntDiff + TxPort1IntDiff);
13097+ }
13098
13099 /*
13100- ** The following lines have been commented out, because
13101- ** from kernel 2.5.44 onwards, the kernel-owned structure
13102- **
13103- ** struct kernel_stat kstat
13104- **
13105- ** is not marked as an exported symbol in the file
13106+ ** We have a Yukon2 compliant chipset if we come up to here
13107 **
13108- ** kernel/ksyms.c
13109- **
13110- ** As a consequence, using this driver as KLM is not possible
13111- ** and any access of the structure kernel_stat via the
13112- ** dedicated macros kstat_cpu(i).cpustat.xxx is to be avoided.
13113- **
13114- ** The kstat-information might be added again in future
13115- ** versions of the 2.5.xx kernel, but for the time being,
13116- ** number of interrupts will serve as indication how much
13117- ** load we currently have...
13118- **
13119- ** for (NbrCpu = 0; NbrCpu < num_online_cpus(); NbrCpu++) {
13120- ** UserTime = UserTime + kstat_cpu(NbrCpu).cpustat.user;
13121- ** NiceTime = NiceTime + kstat_cpu(NbrCpu).cpustat.nice;
13122- ** SystemTime = SystemTime + kstat_cpu(NbrCpu).cpustat.system;
13123- ** }
13124+ if (pAC->GIni.GIMacsFound == 2) {
13125+ StatusPort1IntDiff = pAC->Pnmi.Port[1].StatusLeIntrCts -
13126+ M_DIMINFO.PrevPort1StatusIntrCts;
13127+ }
13128+ StatusPort0IntDiff = pAC->Pnmi.Port[0].StatusLeIntrCts -
13129+ M_DIMINFO.PrevPort0StatusIntrCts;
13130 */
13131- SK_U64 ThresholdInts = 0;
13132- SK_U64 IsrCallsPerSec = 0;
13133-
13134- ThresholdInts = ((M_DIMINFO.MaxModIntsPerSec *
13135- C_INT_MOD_ENABLE_PERCENTAGE) + 100);
13136- IsrCallsPerSec = GetIsrCalls(pAC);
13137- if (IsrCallsPerSec >= ThresholdInts) {
13138- /*
13139- ** We do not know how much the real CPU-load is!
13140- ** Return 80% as a default in order to activate DIM
13141- */
13142- SystemLoad = 80;
13143- return (SystemLoad);
13144- }
13145-
13146- UsedTime = UserTime + NiceTime + SystemTime;
13147-
13148- IdleTime = jif * num_online_cpus() - UsedTime;
13149- TotalTime = UsedTime + IdleTime;
13150-
13151- SystemLoad = ( 100 * (UsedTime - M_DIMINFO.PrevUsedTime) ) /
13152- (TotalTime - M_DIMINFO.PrevTotalTime);
13153+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
13154+ ("==>getIsrCalls (CHIP_ID_YUKON_2)\n"));
13155+ return (StatusPort0IntDiff + StatusPort1IntDiff);
13156+}
13157
13158- if (M_DIMINFO.DisplayStats) {
13159- printk("Current system load is: %u\n", SystemLoad);
13160+/*****************************************************************************
13161+ *
13162+ * setCurrIntCtr - stores the current number of interrupts
13163+ *
13164+ * Description:
13165+ * Stores the current number of occurred interrupts in the adapter
13166+ * context. This is needed to evaluate the umber of interrupts within
13167+ * the moderation interval.
13168+ *
13169+ * Returns: N/A
13170+ *
13171+ */
13172+static void setCurrIntCtr(
13173+SK_AC *pAC) /* pointer to adapter control context */
13174+{
13175+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==>setCurrIntCtr\n"));
13176+
13177+ if (!CHIP_ID_YUKON_2(pAC)) {
13178+ if (pAC->GIni.GIMacsFound == 2) {
13179+ M_DIMINFO.PrevPort1RxIntrCts = pAC->Pnmi.Port[1].RxIntrCts;
13180+ M_DIMINFO.PrevPort1TxIntrCts = pAC->Pnmi.Port[1].TxIntrCts;
13181+ }
13182+ M_DIMINFO.PrevPort0RxIntrCts = pAC->Pnmi.Port[0].RxIntrCts;
13183+ M_DIMINFO.PrevPort0TxIntrCts = pAC->Pnmi.Port[0].TxIntrCts;
13184+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
13185+ ("<== setCurrIntCtr (!CHIP_ID_YUKON_2)\n"));
13186+ return;
13187 }
13188
13189- M_DIMINFO.PrevTotalTime = TotalTime;
13190- M_DIMINFO.PrevUsedTime = UsedTime;
13191-
13192- return (SystemLoad);
13193+ /*
13194+ ** We have a Yukon2 compliant chipset if we come up to here
13195+ **
13196+ if (pAC->GIni.GIMacsFound == 2) {
13197+ M_DIMINFO.PrevPort1StatusIntrCts = pAC->Pnmi.Port[1].StatusLeIntrCts;
13198+ }
13199+ M_DIMINFO.PrevPort0StatusIntrCts = pAC->Pnmi.Port[0].StatusLeIntrCts;
13200+ */
13201+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
13202+ ("<== setCurrIntCtr (CHIP_ID_YUKON_2)\n"));
13203 }
13204
13205-/*******************************************************************************
13206-** Function : GetIsrCalls
13207-** Description : Depending on the selected moderation mask, this function will
13208-** return the number of interrupts handled in the previous time-
13209-** frame. This evaluated number is based on the current number
13210-** of interrupts stored in PNMI-context and the previous stored
13211-** interrupts.
13212-** Programmer : Ralph Roesler
13213-** Last Modified: 23-mar-03
13214-** Returns : int: the number of interrupts being executed in the last
13215-** timeframe
13216-** Notes : It makes only sense to call this function, when dynamic
13217-** interrupt moderation is applied
13218-*******************************************************************************/
13219-
13220-static SK_U64
13221-GetIsrCalls(SK_AC *pAC) {
13222- SK_U64 RxPort0IntDiff = 0;
13223- SK_U64 RxPort1IntDiff = 0;
13224- SK_U64 TxPort0IntDiff = 0;
13225- SK_U64 TxPort1IntDiff = 0;
13226-
13227- if (pAC->DynIrqModInfo.MaskIrqModeration == IRQ_MASK_TX_ONLY) {
13228- if (pAC->GIni.GIMacsFound == 2) {
13229- TxPort1IntDiff = pAC->Pnmi.Port[1].TxIntrCts -
13230- pAC->DynIrqModInfo.PrevPort1TxIntrCts;
13231- }
13232- TxPort0IntDiff = pAC->Pnmi.Port[0].TxIntrCts -
13233- pAC->DynIrqModInfo.PrevPort0TxIntrCts;
13234- } else if (pAC->DynIrqModInfo.MaskIrqModeration == IRQ_MASK_RX_ONLY) {
13235- if (pAC->GIni.GIMacsFound == 2) {
13236- RxPort1IntDiff = pAC->Pnmi.Port[1].RxIntrCts -
13237- pAC->DynIrqModInfo.PrevPort1RxIntrCts;
13238- }
13239- RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts -
13240- pAC->DynIrqModInfo.PrevPort0RxIntrCts;
13241- } else {
13242- if (pAC->GIni.GIMacsFound == 2) {
13243- RxPort1IntDiff = pAC->Pnmi.Port[1].RxIntrCts -
13244- pAC->DynIrqModInfo.PrevPort1RxIntrCts;
13245- TxPort1IntDiff = pAC->Pnmi.Port[1].TxIntrCts -
13246- pAC->DynIrqModInfo.PrevPort1TxIntrCts;
13247- }
13248- RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts -
13249- pAC->DynIrqModInfo.PrevPort0RxIntrCts;
13250- TxPort0IntDiff = pAC->Pnmi.Port[0].TxIntrCts -
13251- pAC->DynIrqModInfo.PrevPort0TxIntrCts;
13252- }
13253-
13254- return (RxPort0IntDiff + RxPort1IntDiff + TxPort0IntDiff + TxPort1IntDiff);
13255+/*****************************************************************************
13256+ *
13257+ * isIntModEnabled - returns the current state of interrupt moderation
13258+ *
13259+ * Description:
13260+ * This function retrieves the current value of the interrupt moderation
13261+ * command register. Its content determines whether any moderation is
13262+ * running or not.
13263+ *
13264+ * Returns:
13265+ * SK_TRUE : IRQ moderation is currently active
13266+ * SK_FALSE: No IRQ moderation is active
13267+ */
13268+static SK_BOOL isIntModEnabled(
13269+SK_AC *pAC) /* pointer to adapter control context */
13270+{
13271+ unsigned long CtrCmd;
13272+
13273+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==>isIntModEnabled\n"));
13274+
13275+ SK_IN32(pAC->IoBase, B2_IRQM_CTRL, &CtrCmd);
13276+ if ((CtrCmd & TIM_START) == TIM_START) {
13277+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
13278+ ("<== isIntModEnabled (SK_TRUE)\n"));
13279+ return SK_TRUE;
13280+ }
13281+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,
13282+ ("<== isIntModEnabled (SK_FALSE)\n"));
13283+ return SK_FALSE;
13284 }
13285
13286-/*******************************************************************************
13287-** Function : GetRxCalls
13288-** Description : This function will return the number of times a receive inter-
13289-** rupt was processed. This is needed to evaluate any resizing
13290-** factor.
13291-** Programmer : Ralph Roesler
13292-** Last Modified: 23-mar-03
13293-** Returns : SK_U64: the number of RX-ints being processed
13294-** Notes : It makes only sense to call this function, when dynamic
13295-** interrupt moderation is applied
13296-*******************************************************************************/
13297-
13298-static SK_U64
13299-GetRxCalls(SK_AC *pAC) {
13300- SK_U64 RxPort0IntDiff = 0;
13301- SK_U64 RxPort1IntDiff = 0;
13302-
13303- if (pAC->GIni.GIMacsFound == 2) {
13304- RxPort1IntDiff = pAC->Pnmi.Port[1].RxIntrCts -
13305- pAC->DynIrqModInfo.PrevPort1RxIntrCts;
13306- }
13307- RxPort0IntDiff = pAC->Pnmi.Port[0].RxIntrCts -
13308- pAC->DynIrqModInfo.PrevPort0RxIntrCts;
13309-
13310- return (RxPort0IntDiff + RxPort1IntDiff);
13311-}
13312+/*****************************************************************************
13313+ *
13314+ * enableIntMod - enables the interrupt moderation
13315+ *
13316+ * Description:
13317+ * Enabling the interrupt moderation is done by putting the desired
13318+ * moderation interval in the B2_IRQM_INI register, specifying the
13319+ * desired maks in the B2_IRQM_MSK register and finally starting the
13320+ * IRQ moderation timer using the B2_IRQM_CTRL register.
13321+ *
13322+ * Returns: N/A
13323+ *
13324+ */
13325+static void enableIntMod(
13326+SK_AC *pAC) /* pointer to adapter control context */
13327+{
13328+ unsigned long ModBase;
13329+
13330+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==> enableIntMod\n"));
13331+
13332+ if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
13333+ ModBase = C_CLK_FREQ_GENESIS / M_DIMINFO.MaxModIntsPerSec;
13334+ } else if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) {
13335+ ModBase = C_CLK_FREQ_YUKON_EC / M_DIMINFO.MaxModIntsPerSec;
13336+ } else {
13337+ ModBase = C_CLK_FREQ_YUKON / M_DIMINFO.MaxModIntsPerSec;
13338+ }
13339
13340-/*******************************************************************************
13341-** Function : SetCurrIntCtr
13342-** Description : Will store the current number orf occured interrupts in the
13343-** adapter context. This is needed to evaluated the number of
13344-** interrupts within a current timeframe.
13345-** Programmer : Ralph Roesler
13346-** Last Modified: 23-mar-03
13347-** Returns : void (!)
13348-** Notes : -
13349-*******************************************************************************/
13350-
13351-static void
13352-SetCurrIntCtr(SK_AC *pAC) {
13353- if (pAC->GIni.GIMacsFound == 2) {
13354- pAC->DynIrqModInfo.PrevPort1RxIntrCts = pAC->Pnmi.Port[1].RxIntrCts;
13355- pAC->DynIrqModInfo.PrevPort1TxIntrCts = pAC->Pnmi.Port[1].TxIntrCts;
13356- }
13357- pAC->DynIrqModInfo.PrevPort0RxIntrCts = pAC->Pnmi.Port[0].RxIntrCts;
13358- pAC->DynIrqModInfo.PrevPort0TxIntrCts = pAC->Pnmi.Port[0].TxIntrCts;
13359-}
13360+ SK_OUT32(pAC->IoBase, B2_IRQM_INI, ModBase);
13361+ SK_OUT32(pAC->IoBase, B2_IRQM_MSK, M_DIMINFO.MaskIrqModeration);
13362+ SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_START);
13363
13364-/*******************************************************************************
13365-** Function : IsIntModEnabled()
13366-** Description : Retrieves the current value of the interrupts moderation
13367-** command register. Its content determines whether any
13368-** moderation is running or not.
13369-** Programmer : Ralph Roesler
13370-** Last Modified: 23-mar-03
13371-** Returns : SK_TRUE : if mod timer running
13372-** SK_FALSE : if no moderation is being performed
13373-** Notes : -
13374-*******************************************************************************/
13375-
13376-static SK_BOOL
13377-IsIntModEnabled(SK_AC *pAC) {
13378- unsigned long CtrCmd;
13379-
13380- SK_IN32(pAC->IoBase, B2_IRQM_CTRL, &CtrCmd);
13381- if ((CtrCmd & TIM_START) == TIM_START) {
13382- return SK_TRUE;
13383- } else {
13384- return SK_FALSE;
13385- }
13386+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("<== enableIntMod\n"));
13387 }
13388
13389-/*******************************************************************************
13390-** Function : EnableIntMod()
13391-** Description : Enables the interrupt moderation using the values stored in
13392-** in the pAC->DynIntMod data structure
13393-** Programmer : Ralph Roesler
13394-** Last Modified: 22-mar-03
13395-** Returns : -
13396-** Notes : -
13397-*******************************************************************************/
13398-
13399-static void
13400-EnableIntMod(SK_AC *pAC) {
13401- unsigned long ModBase;
13402-
13403- if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
13404- ModBase = C_CLK_FREQ_GENESIS / pAC->DynIrqModInfo.MaxModIntsPerSec;
13405- } else {
13406- ModBase = C_CLK_FREQ_YUKON / pAC->DynIrqModInfo.MaxModIntsPerSec;
13407- }
13408-
13409- SK_OUT32(pAC->IoBase, B2_IRQM_INI, ModBase);
13410- SK_OUT32(pAC->IoBase, B2_IRQM_MSK, pAC->DynIrqModInfo.MaskIrqModeration);
13411- SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_START);
13412- if (M_DIMINFO.DisplayStats) {
13413- printk("Enabled interrupt moderation (%i ints/sec)\n",
13414- M_DIMINFO.MaxModIntsPerSec);
13415- }
13416-}
13417+/*****************************************************************************
13418+ *
13419+ * disableIntMod - disables the interrupt moderation
13420+ *
13421+ * Description:
13422+ * Disabling the interrupt moderation is done by stopping the
13423+ * IRQ moderation timer using the B2_IRQM_CTRL register.
13424+ *
13425+ * Returns: N/A
13426+ *
13427+ */
13428+static void disableIntMod(
13429+SK_AC *pAC) /* pointer to adapter control context */
13430+{
13431+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("==> disableIntMod\n"));
13432
13433-/*******************************************************************************
13434-** Function : DisableIntMod()
13435-** Description : Disbles the interrupt moderation independent of what inter-
13436-** rupts are running or not
13437-** Programmer : Ralph Roesler
13438-** Last Modified: 23-mar-03
13439-** Returns : -
13440-** Notes : -
13441-*******************************************************************************/
13442-
13443-static void
13444-DisableIntMod(SK_AC *pAC) {
13445-
13446- SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_STOP);
13447- if (M_DIMINFO.DisplayStats) {
13448- printk("Disabled interrupt moderation\n");
13449- }
13450-}
13451+ SK_OUT32(pAC->IoBase, B2_IRQM_CTRL, TIM_STOP);
13452
13453-/*******************************************************************************
13454-** Function : ResizeDimTimerDuration();
13455-** Description : Checks the current used descriptor ratio and resizes the
13456-** duration timer (longer/smaller) if possible.
13457-** Programmer : Ralph Roesler
13458-** Last Modified: 23-mar-03
13459-** Returns : -
13460-** Notes : There are both maximum and minimum timer duration value.
13461-** This function assumes that interrupt moderation is already
13462-** enabled!
13463-*******************************************************************************/
13464-
13465-static void
13466-ResizeDimTimerDuration(SK_AC *pAC) {
13467- SK_BOOL IncreaseTimerDuration;
13468- int TotalMaxNbrDescr;
13469- int UsedDescrRatio;
13470- int RatioDiffAbs;
13471- int RatioDiffRel;
13472- int NewMaxModIntsPerSec;
13473- int ModAdjValue;
13474- long ModBase;
13475-
13476- /*
13477- ** Check first if we are allowed to perform any modification
13478- */
13479- if (IsIntModEnabled(pAC)) {
13480- if (M_DIMINFO.IntModTypeSelect != C_INT_MOD_DYNAMIC) {
13481- return;
13482- } else {
13483- if (M_DIMINFO.ModJustEnabled) {
13484- M_DIMINFO.ModJustEnabled = SK_FALSE;
13485- return;
13486- }
13487- }
13488- }
13489-
13490- /*
13491- ** If we got until here, we have to evaluate the amount of the
13492- ** descriptor ratio change...
13493- */
13494- TotalMaxNbrDescr = pAC->RxDescrPerRing * GetRxCalls(pAC);
13495- UsedDescrRatio = (M_DIMINFO.NbrProcessedDescr * 100) / TotalMaxNbrDescr;
13496-
13497- if (UsedDescrRatio > M_DIMINFO.PrevUsedDescrRatio) {
13498- RatioDiffAbs = (UsedDescrRatio - M_DIMINFO.PrevUsedDescrRatio);
13499- RatioDiffRel = (RatioDiffAbs * 100) / UsedDescrRatio;
13500- M_DIMINFO.PrevUsedDescrRatio = UsedDescrRatio;
13501- IncreaseTimerDuration = SK_FALSE; /* in other words: DECREASE */
13502- } else if (UsedDescrRatio < M_DIMINFO.PrevUsedDescrRatio) {
13503- RatioDiffAbs = (M_DIMINFO.PrevUsedDescrRatio - UsedDescrRatio);
13504- RatioDiffRel = (RatioDiffAbs * 100) / M_DIMINFO.PrevUsedDescrRatio;
13505- M_DIMINFO.PrevUsedDescrRatio = UsedDescrRatio;
13506- IncreaseTimerDuration = SK_TRUE; /* in other words: INCREASE */
13507- } else {
13508- RatioDiffAbs = (M_DIMINFO.PrevUsedDescrRatio - UsedDescrRatio);
13509- RatioDiffRel = (RatioDiffAbs * 100) / M_DIMINFO.PrevUsedDescrRatio;
13510- M_DIMINFO.PrevUsedDescrRatio = UsedDescrRatio;
13511- IncreaseTimerDuration = SK_TRUE; /* in other words: INCREASE */
13512- }
13513-
13514- /*
13515- ** Now we can determine the change in percent
13516- */
13517- if ((RatioDiffRel >= 0) && (RatioDiffRel <= 5) ) {
13518- ModAdjValue = 1; /* 1% change - maybe some other value in future */
13519- } else if ((RatioDiffRel > 5) && (RatioDiffRel <= 10) ) {
13520- ModAdjValue = 1; /* 1% change - maybe some other value in future */
13521- } else if ((RatioDiffRel > 10) && (RatioDiffRel <= 15) ) {
13522- ModAdjValue = 1; /* 1% change - maybe some other value in future */
13523- } else {
13524- ModAdjValue = 1; /* 1% change - maybe some other value in future */
13525- }
13526-
13527- if (IncreaseTimerDuration) {
13528- NewMaxModIntsPerSec = M_DIMINFO.MaxModIntsPerSec +
13529- (M_DIMINFO.MaxModIntsPerSec * ModAdjValue) / 100;
13530- } else {
13531- NewMaxModIntsPerSec = M_DIMINFO.MaxModIntsPerSec -
13532- (M_DIMINFO.MaxModIntsPerSec * ModAdjValue) / 100;
13533- }
13534-
13535- /*
13536- ** Check if we exceed boundaries...
13537- */
13538- if ( (NewMaxModIntsPerSec > M_DIMINFO.MaxModIntsPerSecUpperLimit) ||
13539- (NewMaxModIntsPerSec < M_DIMINFO.MaxModIntsPerSecLowerLimit)) {
13540- if (M_DIMINFO.DisplayStats) {
13541- printk("Cannot change ModTim from %i to %i ints/sec\n",
13542- M_DIMINFO.MaxModIntsPerSec, NewMaxModIntsPerSec);
13543- }
13544- return;
13545- } else {
13546- if (M_DIMINFO.DisplayStats) {
13547- printk("Resized ModTim from %i to %i ints/sec\n",
13548- M_DIMINFO.MaxModIntsPerSec, NewMaxModIntsPerSec);
13549- }
13550- }
13551-
13552- M_DIMINFO.MaxModIntsPerSec = NewMaxModIntsPerSec;
13553-
13554- if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
13555- ModBase = C_CLK_FREQ_GENESIS / pAC->DynIrqModInfo.MaxModIntsPerSec;
13556- } else {
13557- ModBase = C_CLK_FREQ_YUKON / pAC->DynIrqModInfo.MaxModIntsPerSec;
13558- }
13559-
13560- /*
13561- ** We do not need to touch any other registers
13562- */
13563- SK_OUT32(pAC->IoBase, B2_IRQM_INI, ModBase);
13564+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_MSG,("<== disableIntMod\n"));
13565 }
13566
13567 /*******************************************************************************
13568-** Function : DisplaySelectedModerationType()
13569-** Description : Displays what type of moderation we have
13570-** Programmer : Ralph Roesler
13571-** Last Modified: 23-mar-03
13572-** Returns : void!
13573-** Notes : -
13574-*******************************************************************************/
13575-
13576-static void
13577-DisplaySelectedModerationType(SK_AC *pAC) {
13578-
13579- if (pAC->DynIrqModInfo.DisplayStats) {
13580- if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_STATIC) {
13581- printk("Static int moderation runs with %i INTS/sec\n",
13582- pAC->DynIrqModInfo.MaxModIntsPerSec);
13583- } else if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
13584- if (IsIntModEnabled(pAC)) {
13585- printk("Dynamic int moderation runs with %i INTS/sec\n",
13586- pAC->DynIrqModInfo.MaxModIntsPerSec);
13587- } else {
13588- printk("Dynamic int moderation currently not applied\n");
13589- }
13590- } else {
13591- printk("No interrupt moderation selected!\n");
13592- }
13593- }
13594-}
13595-
13596-/*******************************************************************************
13597-** Function : DisplaySelectedModerationMask()
13598-** Description : Displays what interrupts are moderated
13599-** Programmer : Ralph Roesler
13600-** Last Modified: 23-mar-03
13601-** Returns : void!
13602-** Notes : -
13603-*******************************************************************************/
13604-
13605-static void
13606-DisplaySelectedModerationMask(SK_AC *pAC) {
13607-
13608- if (pAC->DynIrqModInfo.DisplayStats) {
13609- if (pAC->DynIrqModInfo.IntModTypeSelect != C_INT_MOD_NONE) {
13610- switch (pAC->DynIrqModInfo.MaskIrqModeration) {
13611- case IRQ_MASK_TX_ONLY:
13612- printk("Only Tx-interrupts are moderated\n");
13613- break;
13614- case IRQ_MASK_RX_ONLY:
13615- printk("Only Rx-interrupts are moderated\n");
13616- break;
13617- case IRQ_MASK_SP_ONLY:
13618- printk("Only special-interrupts are moderated\n");
13619- break;
13620- case IRQ_MASK_TX_RX:
13621- printk("Tx- and Rx-interrupts are moderated\n");
13622- break;
13623- case IRQ_MASK_SP_RX:
13624- printk("Special- and Rx-interrupts are moderated\n");
13625- break;
13626- case IRQ_MASK_SP_TX:
13627- printk("Special- and Tx-interrupts are moderated\n");
13628- break;
13629- case IRQ_MASK_RX_TX_SP:
13630- printk("All Rx-, Tx and special-interrupts are moderated\n");
13631- break;
13632- default:
13633- printk("Don't know what is moderated\n");
13634- break;
13635- }
13636- } else {
13637- printk("No specific interrupts masked for moderation\n");
13638- }
13639- }
13640-}
13641-
13642-/*******************************************************************************
13643-** Function : DisplayDescrRatio
13644-** Description : Like the name states...
13645-** Programmer : Ralph Roesler
13646-** Last Modified: 23-mar-03
13647-** Returns : void!
13648-** Notes : -
13649-*******************************************************************************/
13650-
13651-static void
13652-DisplayDescrRatio(SK_AC *pAC) {
13653- int TotalMaxNbrDescr = 0;
13654-
13655- if (pAC->DynIrqModInfo.DisplayStats) {
13656- TotalMaxNbrDescr = pAC->RxDescrPerRing * GetRxCalls(pAC);
13657- printk("Ratio descriptors: %i/%i\n",
13658- M_DIMINFO.NbrProcessedDescr, TotalMaxNbrDescr);
13659- }
13660-}
13661-
13662-/*******************************************************************************
13663-**
13664-** End of file
13665-**
13666-*******************************************************************************/
13667+ *
13668+ * End of file
13669+ *
13670+ ******************************************************************************/
13671diff -ruN linux/drivers/net/sk98lin/skethtool.c linux-new/drivers/net/sk98lin/skethtool.c
13672--- linux/drivers/net/sk98lin/skethtool.c 2006-04-11 19:19:28.000000000 +0200
13673+++ linux-new/drivers/net/sk98lin/skethtool.c 2006-01-18 14:37:24.000000000 +0100
13674@@ -2,8 +2,8 @@
13675 *
13676 * Name: skethtool.c
13677 * Project: GEnesis, PCI Gigabit Ethernet Adapter
13678- * Version: $Revision$
13679- * Date: $Date$
13680+ * Version: $Revision$
13681+ * Date: $Date$
13682 * Purpose: All functions regarding ethtool handling
13683 *
13684 ******************************************************************************/
13685@@ -11,7 +11,7 @@
13686 /******************************************************************************
13687 *
13688 * (C)Copyright 1998-2002 SysKonnect GmbH.
13689- * (C)Copyright 2002-2004 Marvell.
13690+ * (C)Copyright 2002-2005 Marvell.
13691 *
13692 * Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet
13693 * Server Adapters.
13694@@ -21,9 +21,6 @@
13695 *
13696 * Address all question to: linux@syskonnect.de
13697 *
13698- * The technical manual for the adapters is available from SysKonnect's
13699- * web pages: www.syskonnect.com
13700- *
13701 * This program is free software; you can redistribute it and/or modify
13702 * it under the terms of the GNU General Public License as published by
13703 * the Free Software Foundation; either version 2 of the License, or
13704@@ -36,10 +33,18 @@
13705 #include "h/skdrv1st.h"
13706 #include "h/skdrv2nd.h"
13707 #include "h/skversion.h"
13708-
13709 #include <linux/ethtool.h>
13710+#include <linux/module.h>
13711 #include <linux/timer.h>
13712-#include <linux/delay.h>
13713+
13714+/******************************************************************************
13715+ *
13716+ * External Functions and Data
13717+ *
13718+ *****************************************************************************/
13719+
13720+extern void SkDimDisableModeration(SK_AC *pAC, int CurrentModeration);
13721+extern void SkDimEnableModerationIfNeeded(SK_AC *pAC);
13722
13723 /******************************************************************************
13724 *
13725@@ -47,6 +52,12 @@
13726 *
13727 *****************************************************************************/
13728
13729+#ifndef ETHT_STATSTRING_LEN
13730+#define ETHT_STATSTRING_LEN 32
13731+#endif
13732+
13733+#define SK98LIN_STAT(m) sizeof(((SK_AC *)0)->m),offsetof(SK_AC, m)
13734+
13735 #define SUPP_COPPER_ALL (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
13736 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
13737 SUPPORTED_1000baseT_Half| SUPPORTED_1000baseT_Full| \
13738@@ -65,6 +76,454 @@
13739 ADVERTISED_FIBRE | \
13740 ADVERTISED_Autoneg)
13741
13742+/******************************************************************************
13743+ *
13744+ * Local Function Prototypes
13745+ *
13746+ *****************************************************************************/
13747+
13748+#ifdef ETHTOOL_GSET
13749+static void getSettings(SK_AC *pAC, int port, struct ethtool_cmd *ecmd);
13750+#endif
13751+#ifdef ETHTOOL_SSET
13752+static int setSettings(SK_AC *pAC, int port, struct ethtool_cmd *ecmd);
13753+#endif
13754+#ifdef ETHTOOL_GPAUSEPARAM
13755+static void getPauseParams(SK_AC *pAC, int port, struct ethtool_pauseparam *epause);
13756+#endif
13757+#ifdef ETHTOOL_SPAUSEPARAM
13758+static int setPauseParams(SK_AC *pAC, int port, struct ethtool_pauseparam *epause);
13759+#endif
13760+#ifdef ETHTOOL_GDRVINFO
13761+static void getDriverInfo(SK_AC *pAC, int port, struct ethtool_drvinfo *edrvinfo);
13762+#endif
13763+#ifdef ETHTOOL_PHYS_ID
13764+static int startLocateNIC(SK_AC *pAC, int port, struct ethtool_value *blinkSecs);
13765+static void toggleLeds(unsigned long ptr);
13766+#endif
13767+#ifdef ETHTOOL_GCOALESCE
13768+static void getModerationParams(SK_AC *pAC, int port, struct ethtool_coalesce *ecoalesc);
13769+#endif
13770+#ifdef ETHTOOL_SCOALESCE
13771+static int setModerationParams(SK_AC *pAC, int port, struct ethtool_coalesce *ecoalesc);
13772+#endif
13773+#ifdef ETHTOOL_GWOL
13774+static void getWOLsettings(SK_AC *pAC, int port, struct ethtool_wolinfo *ewol);
13775+#endif
13776+#ifdef ETHTOOL_SWOL
13777+static int setWOLsettings(SK_AC *pAC, int port, struct ethtool_wolinfo *ewol);
13778+#endif
13779+
13780+static int getPortNumber(struct net_device *netdev, struct ifreq *ifr);
13781+
13782+/******************************************************************************
13783+ *
13784+ * Local Variables
13785+ *
13786+ *****************************************************************************/
13787+
13788+struct sk98lin_stats {
13789+ char stat_string[ETHT_STATSTRING_LEN];
13790+ int sizeof_stat;
13791+ int stat_offset;
13792+};
13793+
13794+static struct sk98lin_stats sk98lin_etht_stats_port0[] = {
13795+ { "rx_packets" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxOkCts) },
13796+ { "tx_packets" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxOkCts) },
13797+ { "rx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxOctetsOkCts) },
13798+ { "tx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxOctetsOkCts) },
13799+ { "rx_errors" , SK98LIN_STAT(PnmiStruct.InErrorsCts) },
13800+ { "tx_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxSingleCollisionCts) },
13801+ { "rx_dropped" , SK98LIN_STAT(PnmiStruct.RxNoBufCts) },
13802+ { "tx_dropped" , SK98LIN_STAT(PnmiStruct.TxNoBufCts) },
13803+ { "multicasts" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxMulticastOkCts) },
13804+ { "collisions" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxSingleCollisionCts) },
13805+ { "rx_length_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxRuntCts) },
13806+ { "rx_buffer_overflow_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxFifoOverflowCts) },
13807+ { "rx_crc_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxFcsCts) },
13808+ { "rx_frame_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxFramingCts) },
13809+ { "rx_too_short_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxShortsCts) },
13810+ { "rx_too_long_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxTooLongCts) },
13811+ { "rx_carrier_extension_errors", SK98LIN_STAT(PnmiStruct.Stat[0].StatRxCextCts) },
13812+ { "rx_symbol_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxSymbolCts) },
13813+ { "rx_llc_mac_size_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxIRLengthCts) },
13814+ { "rx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxCarrierCts) },
13815+ { "rx_jabber_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxJabberCts) },
13816+ { "rx_missed_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatRxMissedCts) },
13817+ { "tx_abort_collision_errors" , SK98LIN_STAT(stats.tx_aborted_errors) },
13818+ { "tx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxCarrierCts) },
13819+ { "tx_buffer_underrun_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxFifoUnderrunCts) },
13820+ { "tx_heartbeat_errors" , SK98LIN_STAT(PnmiStruct.Stat[0].StatTxCarrierCts) } ,
13821+ { "tx_window_errors" , SK98LIN_STAT(stats.tx_window_errors) }
13822+};
13823+
13824+static struct sk98lin_stats sk98lin_etht_stats_port1[] = {
13825+ { "rx_packets" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxOkCts) },
13826+ { "tx_packets" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxOkCts) },
13827+ { "rx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxOctetsOkCts) },
13828+ { "tx_bytes" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxOctetsOkCts) },
13829+ { "rx_errors" , SK98LIN_STAT(PnmiStruct.InErrorsCts) },
13830+ { "tx_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxSingleCollisionCts) },
13831+ { "rx_dropped" , SK98LIN_STAT(PnmiStruct.RxNoBufCts) },
13832+ { "tx_dropped" , SK98LIN_STAT(PnmiStruct.TxNoBufCts) },
13833+ { "multicasts" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxMulticastOkCts) },
13834+ { "collisions" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxSingleCollisionCts) },
13835+ { "rx_length_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxRuntCts) },
13836+ { "rx_buffer_overflow_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxFifoOverflowCts) },
13837+ { "rx_crc_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxFcsCts) },
13838+ { "rx_frame_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxFramingCts) },
13839+ { "rx_too_short_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxShortsCts) },
13840+ { "rx_too_long_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxTooLongCts) },
13841+ { "rx_carrier_extension_errors", SK98LIN_STAT(PnmiStruct.Stat[1].StatRxCextCts) },
13842+ { "rx_symbol_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxSymbolCts) },
13843+ { "rx_llc_mac_size_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxIRLengthCts) },
13844+ { "rx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxCarrierCts) },
13845+ { "rx_jabber_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxJabberCts) },
13846+ { "rx_missed_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatRxMissedCts) },
13847+ { "tx_abort_collision_errors" , SK98LIN_STAT(stats.tx_aborted_errors) },
13848+ { "tx_carrier_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxCarrierCts) },
13849+ { "tx_buffer_underrun_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxFifoUnderrunCts) },
13850+ { "tx_heartbeat_errors" , SK98LIN_STAT(PnmiStruct.Stat[1].StatTxCarrierCts) } ,
13851+ { "tx_window_errors" , SK98LIN_STAT(stats.tx_window_errors) }
13852+};
13853+
13854+#define SK98LIN_STATS_LEN sizeof(sk98lin_etht_stats_port0) / sizeof(struct sk98lin_stats)
13855+
13856+static int nbrBlinkQuarterSeconds;
13857+static int currentPortIndex;
13858+static SK_BOOL isLocateNICrunning = SK_FALSE;
13859+static SK_BOOL isDualNetCard = SK_FALSE;
13860+static SK_BOOL doSwitchLEDsOn = SK_FALSE;
13861+static SK_BOOL boardWasDown[2] = { SK_FALSE, SK_FALSE };
13862+static struct timer_list locateNICtimer;
13863+
13864+/******************************************************************************
13865+ *
13866+ * Global Functions
13867+ *
13868+ *****************************************************************************/
13869+
13870+/*****************************************************************************
13871+ *
13872+ * SkEthIoctl - IOCTL entry point for all ethtool queries
13873+ *
13874+ * Description:
13875+ * Any IOCTL request that has to deal with the ethtool command tool is
13876+ * dispatched via this function.
13877+ *
13878+ * Returns:
13879+ * ==0: everything fine, no error
13880+ * !=0: the return value is the error code of the failure
13881+ */
13882+int SkEthIoctl(
13883+struct net_device *netdev, /* the pointer to netdev structure */
13884+struct ifreq *ifr) /* what interface the request refers to? */
13885+{
13886+ DEV_NET *pNet = (DEV_NET*) netdev->priv;
13887+ SK_AC *pAC = pNet->pAC;
13888+ void *pAddr = ifr->ifr_data;
13889+ int port = getPortNumber(netdev, ifr);
13890+ SK_PNMI_STRUCT_DATA *pPnmiStruct = &pAC->PnmiStruct;
13891+ SK_U32 Size = sizeof(SK_PNMI_STRUCT_DATA);
13892+ SK_U32 cmd;
13893+ struct sk98lin_stats *sk98lin_etht_stats =
13894+ (port == 0) ? sk98lin_etht_stats_port0 : sk98lin_etht_stats_port1;
13895+
13896+ if (get_user(cmd, (uint32_t *) pAddr)) {
13897+ return -EFAULT;
13898+ }
13899+
13900+ switch(cmd) {
13901+#ifdef ETHTOOL_GSET
13902+ case ETHTOOL_GSET: {
13903+ struct ethtool_cmd ecmd = { ETHTOOL_GSET };
13904+ getSettings(pAC, port, &ecmd);
13905+ if(copy_to_user(pAddr, &ecmd, sizeof(ecmd))) {
13906+ return -EFAULT;
13907+ }
13908+ return 0;
13909+ }
13910+ break;
13911+#endif
13912+#ifdef ETHTOOL_SSET
13913+ case ETHTOOL_SSET: {
13914+ struct ethtool_cmd ecmd;
13915+ if(copy_from_user(&ecmd, pAddr, sizeof(ecmd))) {
13916+ return -EFAULT;
13917+ }
13918+ return setSettings(pAC, port, &ecmd);
13919+ }
13920+ break;
13921+#endif
13922+#ifdef ETHTOOL_GLINK
13923+ case ETHTOOL_GLINK: {
13924+ struct ethtool_value edata = { ETHTOOL_GLINK };
13925+ edata.data = netif_carrier_ok(netdev);
13926+ if (copy_to_user(pAddr, &edata, sizeof(edata)))
13927+ return -EFAULT;
13928+ return 0;
13929+ }
13930+#endif
13931+#ifdef ETHTOOL_GDRVINFO
13932+ case ETHTOOL_GDRVINFO: {
13933+ struct ethtool_drvinfo drvinfo = { ETHTOOL_GDRVINFO };
13934+ getDriverInfo(pAC, port, &drvinfo);
13935+ if(copy_to_user(pAddr, &drvinfo, sizeof(drvinfo))) {
13936+ return -EFAULT;
13937+ }
13938+ return 0;
13939+ }
13940+ break;
13941+#endif
13942+#ifdef ETHTOOL_GSTRINGS
13943+ case ETHTOOL_GSTRINGS: {
13944+ struct ethtool_gstrings gstrings = { ETHTOOL_GSTRINGS };
13945+ char *strings = NULL;
13946+ int err = 0;
13947+ if(copy_from_user(&gstrings, pAddr, sizeof(gstrings))) {
13948+ return -EFAULT;
13949+ }
13950+ switch(gstrings.string_set) {
13951+#ifdef ETHTOOL_GSTATS
13952+ case ETH_SS_STATS: {
13953+ int i;
13954+ gstrings.len = SK98LIN_STATS_LEN;
13955+ if ((strings = kmalloc(SK98LIN_STATS_LEN*ETHT_STATSTRING_LEN,GFP_KERNEL)) == NULL) {
13956+ return -ENOMEM;
13957+ }
13958+ for(i=0; i < SK98LIN_STATS_LEN; i++) {
13959+ memcpy(&strings[i * ETHT_STATSTRING_LEN],
13960+ &(sk98lin_etht_stats[i].stat_string),
13961+ ETHT_STATSTRING_LEN);
13962+ }
13963+ }
13964+ break;
13965+#endif
13966+ default:
13967+ return -EOPNOTSUPP;
13968+ }
13969+ if(copy_to_user(pAddr, &gstrings, sizeof(gstrings))) {
13970+ err = -EFAULT;
13971+ }
13972+ pAddr = (void *) ((unsigned long int) pAddr + offsetof(struct ethtool_gstrings, data));
13973+ if(!err && copy_to_user(pAddr, strings, gstrings.len * ETH_GSTRING_LEN)) {
13974+ err = -EFAULT;
13975+ }
13976+ kfree(strings);
13977+ return err;
13978+ }
13979+#endif
13980+#ifdef ETHTOOL_GSTATS
13981+ case ETHTOOL_GSTATS: {
13982+ struct {
13983+ struct ethtool_stats eth_stats;
13984+ uint64_t data[SK98LIN_STATS_LEN];
13985+ } stats = { {ETHTOOL_GSTATS, SK98LIN_STATS_LEN} };
13986+ int i;
13987+
13988+ if (netif_running(pAC->dev[port])) {
13989+ SkPnmiGetStruct(pAC, pAC->IoBase, pPnmiStruct, &Size, port);
13990+ }
13991+ for(i = 0; i < SK98LIN_STATS_LEN; i++) {
13992+ if (netif_running(pAC->dev[port])) {
13993+ stats.data[i] = (sk98lin_etht_stats[i].sizeof_stat ==
13994+ sizeof(uint64_t)) ?
13995+ *(uint64_t *)((char *)pAC +
13996+ sk98lin_etht_stats[i].stat_offset) :
13997+ *(uint32_t *)((char *)pAC +
13998+ sk98lin_etht_stats[i].stat_offset);
13999+ } else {
14000+ stats.data[i] = (sk98lin_etht_stats[i].sizeof_stat ==
14001+ sizeof(uint64_t)) ? (uint64_t) 0 : (uint32_t) 0;
14002+ }
14003+ }
14004+ if(copy_to_user(pAddr, &stats, sizeof(stats))) {
14005+ return -EFAULT;
14006+ }
14007+ return 0;
14008+ }
14009+#endif
14010+#ifdef ETHTOOL_PHYS_ID
14011+ case ETHTOOL_PHYS_ID: {
14012+ struct ethtool_value blinkSecs;
14013+ if(copy_from_user(&blinkSecs, pAddr, sizeof(blinkSecs))) {
14014+ return -EFAULT;
14015+ }
14016+ return startLocateNIC(pAC, port, &blinkSecs);
14017+ }
14018+#endif
14019+#ifdef ETHTOOL_GPAUSEPARAM
14020+ case ETHTOOL_GPAUSEPARAM: {
14021+ struct ethtool_pauseparam epause = { ETHTOOL_GPAUSEPARAM };
14022+ getPauseParams(pAC, port, &epause);
14023+ if(copy_to_user(pAddr, &epause, sizeof(epause))) {
14024+ return -EFAULT;
14025+ }
14026+ return 0;
14027+ }
14028+#endif
14029+#ifdef ETHTOOL_SPAUSEPARAM
14030+ case ETHTOOL_SPAUSEPARAM: {
14031+ struct ethtool_pauseparam epause;
14032+ if(copy_from_user(&epause, pAddr, sizeof(epause))) {
14033+ return -EFAULT;
14034+ }
14035+ return setPauseParams(pAC, port, &epause);
14036+ }
14037+#endif
14038+#ifdef ETHTOOL_GSG
14039+ case ETHTOOL_GSG: {
14040+ struct ethtool_value edata = { ETHTOOL_GSG };
14041+ edata.data = (netdev->features & NETIF_F_SG) != 0;
14042+ if (copy_to_user(pAddr, &edata, sizeof(edata))) {
14043+ return -EFAULT;
14044+ }
14045+ return 0;
14046+ }
14047+#endif
14048+#ifdef ETHTOOL_SSG
14049+ case ETHTOOL_SSG: {
14050+ struct ethtool_value edata;
14051+ if (copy_from_user(&edata, pAddr, sizeof(edata))) {
14052+ return -EFAULT;
14053+ }
14054+ if (pAC->ChipsetType) { /* Don't handle if Genesis */
14055+ if (edata.data) {
14056+ netdev->features |= NETIF_F_SG;
14057+ } else {
14058+ netdev->features &= ~NETIF_F_SG;
14059+ }
14060+ }
14061+ return 0;
14062+ }
14063+#endif
14064+#ifdef ETHTOOL_GRXCSUM
14065+ case ETHTOOL_GRXCSUM: {
14066+ struct ethtool_value edata = { ETHTOOL_GRXCSUM };
14067+ edata.data = pAC->RxPort[port].UseRxCsum;
14068+ if (copy_to_user(pAddr, &edata, sizeof(edata))) {
14069+ return -EFAULT;
14070+ }
14071+ return 0;
14072+ }
14073+#endif
14074+#ifdef ETHTOOL_SRXCSUM
14075+ case ETHTOOL_SRXCSUM: {
14076+ struct ethtool_value edata;
14077+ if (copy_from_user(&edata, pAddr, sizeof(edata))) {
14078+ return -EFAULT;
14079+ }
14080+ pAC->RxPort[port].UseRxCsum = edata.data;
14081+ return 0;
14082+ }
14083+#endif
14084+#ifdef ETHTOOL_GTXCSUM
14085+ case ETHTOOL_GTXCSUM: {
14086+ struct ethtool_value edata = { ETHTOOL_GTXCSUM };
14087+ edata.data = ((netdev->features & NETIF_F_IP_CSUM) != 0);
14088+ if (copy_to_user(pAddr, &edata, sizeof(edata))) {
14089+ return -EFAULT;
14090+ }
14091+ return 0;
14092+ }
14093+#endif
14094+#ifdef ETHTOOL_STXCSUM
14095+ case ETHTOOL_STXCSUM: {
14096+ struct ethtool_value edata;
14097+ if (copy_from_user(&edata, pAddr, sizeof(edata))) {
14098+ return -EFAULT;
14099+ }
14100+ if (pAC->ChipsetType) { /* Don't handle if Genesis */
14101+ if (edata.data) {
14102+ netdev->features |= NETIF_F_IP_CSUM;
14103+ } else {
14104+ netdev->features &= ~NETIF_F_IP_CSUM;
14105+ }
14106+ }
14107+ return 0;
14108+ }
14109+#endif
14110+#ifdef ETHTOOL_NWAY_RST
14111+ case ETHTOOL_NWAY_RST: {
14112+ if(netif_running(netdev)) {
14113+ (*netdev->stop)(netdev);
14114+ (*netdev->open)(netdev);
14115+ }
14116+ return 0;
14117+ }
14118+#endif
14119+#ifdef NETIF_F_TSO
14120+#ifdef ETHTOOL_GTSO
14121+ case ETHTOOL_GTSO: {
14122+ struct ethtool_value edata = { ETHTOOL_GTSO };
14123+ edata.data = (netdev->features & NETIF_F_TSO) != 0;
14124+ if (copy_to_user(pAddr, &edata, sizeof(edata))) {
14125+ return -EFAULT;
14126+ }
14127+ return 0;
14128+ }
14129+#endif
14130+#ifdef ETHTOOL_STSO
14131+ case ETHTOOL_STSO: {
14132+ struct ethtool_value edata;
14133+ if (CHIP_ID_YUKON_2(pAC)) {
14134+ if (copy_from_user(&edata, pAddr, sizeof(edata))) {
14135+ return -EFAULT;
14136+ }
14137+ if (edata.data) {
14138+ netdev->features |= NETIF_F_TSO;
14139+ } else {
14140+ netdev->features &= ~NETIF_F_TSO;
14141+ }
14142+ return 0;
14143+ }
14144+ return -EOPNOTSUPP;
14145+ }
14146+#endif
14147+#endif
14148+#ifdef ETHTOOL_GCOALESCE
14149+ case ETHTOOL_GCOALESCE: {
14150+ struct ethtool_coalesce ecoalesc = { ETHTOOL_GCOALESCE };
14151+ getModerationParams(pAC, port, &ecoalesc);
14152+ if(copy_to_user(pAddr, &ecoalesc, sizeof(ecoalesc))) {
14153+ return -EFAULT;
14154+ }
14155+ return 0;
14156+ }
14157+#endif
14158+#ifdef ETHTOOL_SCOALESCE
14159+ case ETHTOOL_SCOALESCE: {
14160+ struct ethtool_coalesce ecoalesc;
14161+ if(copy_from_user(&ecoalesc, pAddr, sizeof(ecoalesc))) {
14162+ return -EFAULT;
14163+ }
14164+ return setModerationParams(pAC, port, &ecoalesc);
14165+ }
14166+#endif
14167+#ifdef ETHTOOL_GWOL
14168+ case ETHTOOL_GWOL: {
14169+ struct ethtool_wolinfo ewol = { ETHTOOL_GWOL };
14170+ getWOLsettings(pAC, port, &ewol);
14171+ if(copy_to_user(pAddr, &ewol, sizeof(ewol))) {
14172+ return -EFAULT;
14173+ }
14174+ return 0;
14175+ }
14176+#endif
14177+#ifdef ETHTOOL_SWOL
14178+ case ETHTOOL_SWOL: {
14179+ struct ethtool_wolinfo ewol;
14180+ if(copy_from_user(&ewol, pAddr, sizeof(ewol))) {
14181+ return -EFAULT;
14182+ }
14183+ return setWOLsettings(pAC, port, &ewol);
14184+ }
14185+#endif
14186+ default:
14187+ return -EOPNOTSUPP;
14188+ }
14189+} /* SkEthIoctl() */
14190
14191 /******************************************************************************
14192 *
14193@@ -72,6 +531,7 @@
14194 *
14195 *****************************************************************************/
14196
14197+#ifdef ETHTOOL_GSET
14198 /*****************************************************************************
14199 *
14200 * getSettings - retrieves the current settings of the selected adapter
14201@@ -81,15 +541,15 @@
14202 * This configuration involves a)speed, b)duplex and c)autoneg plus
14203 * a number of other variables.
14204 *
14205- * Returns: always 0
14206+ * Returns: N/A
14207 *
14208 */
14209-static int getSettings(struct net_device *dev, struct ethtool_cmd *ecmd)
14210+static void getSettings(
14211+SK_AC *pAC, /* pointer to adapter control context */
14212+int port, /* the port of the selected adapter */
14213+struct ethtool_cmd *ecmd) /* mandatory command structure for results */
14214 {
14215- const DEV_NET *pNet = netdev_priv(dev);
14216- int port = pNet->PortNr;
14217- const SK_AC *pAC = pNet->pAC;
14218- const SK_GEPORT *pPort = &pAC->GIni.GP[port];
14219+ SK_GEPORT *pPort = &pAC->GIni.GP[port];
14220
14221 static int DuplexAutoNegConfMap[9][3]= {
14222 { -1 , -1 , -1 },
14223@@ -102,6 +562,7 @@
14224 { SK_LMODE_AUTOSENSE , -1 , -1 },
14225 { SK_LMODE_INDETERMINATED, -1 , -1 }
14226 };
14227+
14228 static int SpeedConfMap[6][2] = {
14229 { 0 , -1 },
14230 { SK_LSPEED_AUTO , -1 },
14231@@ -110,6 +571,7 @@
14232 { SK_LSPEED_1000MBPS , SPEED_1000 },
14233 { SK_LSPEED_INDETERMINATED, -1 }
14234 };
14235+
14236 static int AdvSpeedMap[6][2] = {
14237 { 0 , -1 },
14238 { SK_LSPEED_AUTO , -1 },
14239@@ -137,12 +599,10 @@
14240 if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {
14241 ecmd->supported &= ~(SUPPORTED_1000baseT_Half);
14242 }
14243-#ifdef CHIP_ID_YUKON_FE
14244 if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) {
14245 ecmd->supported &= ~(SUPPORTED_1000baseT_Half);
14246 ecmd->supported &= ~(SUPPORTED_1000baseT_Full);
14247 }
14248-#endif
14249 }
14250 if (pAC->GIni.GP[0].PLinkSpeed != SK_LSPEED_AUTO) {
14251 ecmd->advertising = AdvSpeedMap[pPort->PLinkSpeed][1];
14252@@ -152,26 +612,20 @@
14253 } else {
14254 ecmd->advertising = ecmd->supported;
14255 }
14256-
14257- if (ecmd->autoneg == AUTONEG_ENABLE)
14258+ if (ecmd->autoneg == AUTONEG_ENABLE) {
14259 ecmd->advertising |= ADVERTISED_Autoneg;
14260+ } else {
14261+ ecmd->advertising = ADVERTISED_TP;
14262+ }
14263 } else {
14264 ecmd->port = PORT_FIBRE;
14265- ecmd->supported = SUPP_FIBRE_ALL;
14266- ecmd->advertising = ADV_FIBRE_ALL;
14267+ ecmd->supported = (SUPP_FIBRE_ALL);
14268+ ecmd->advertising = (ADV_FIBRE_ALL);
14269 }
14270- return 0;
14271-}
14272-
14273-/*
14274- * MIB infrastructure uses instance value starting at 1
14275- * based on board and port.
14276- */
14277-static inline u32 pnmiInstance(const DEV_NET *pNet)
14278-{
14279- return 1 + (pNet->pAC->RlmtNets == 2) + pNet->PortNr;
14280 }
14281+#endif
14282
14283+#ifdef ETHTOOL_SSET
14284 /*****************************************************************************
14285 *
14286 * setSettings - configures the settings of a selected adapter
14287@@ -181,422 +635,722 @@
14288 * c)autonegotiation.
14289 *
14290 * Returns:
14291- * 0: everything fine, no error
14292- * <0: the return value is the error code of the failure
14293+ * ==0: everything fine, no error
14294+ * !=0: the return value is the error code of the failure
14295 */
14296-static int setSettings(struct net_device *dev, struct ethtool_cmd *ecmd)
14297+static int setSettings(
14298+SK_AC *pAC, /* pointer to adapter control context */
14299+int port, /* the port of the selected adapter */
14300+struct ethtool_cmd *ecmd) /* command structure containing settings */
14301 {
14302- DEV_NET *pNet = netdev_priv(dev);
14303- SK_AC *pAC = pNet->pAC;
14304- u32 instance;
14305- char buf[4];
14306- int len = 1;
14307+ DEV_NET *pNet = (DEV_NET *) pAC->dev[port]->priv;
14308+ SK_U32 Instance;
14309+ char Buf[4];
14310+ unsigned int Len = 1;
14311+ int Ret;
14312
14313- if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100
14314- && ecmd->speed != SPEED_1000)
14315- return -EINVAL;
14316-
14317- if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
14318- return -EINVAL;
14319+ if (port == 0) {
14320+ Instance = (pAC->RlmtNets == 2) ? 1 : 2;
14321+ } else {
14322+ Instance = (pAC->RlmtNets == 2) ? 2 : 3;
14323+ }
14324
14325- if (ecmd->autoneg != AUTONEG_DISABLE && ecmd->autoneg != AUTONEG_ENABLE)
14326- return -EINVAL;
14327+ if (((ecmd->autoneg == AUTONEG_DISABLE) || (ecmd->autoneg == AUTONEG_ENABLE)) &&
14328+ ((ecmd->duplex == DUPLEX_FULL) || (ecmd->duplex == DUPLEX_HALF))) {
14329+ if (ecmd->autoneg == AUTONEG_DISABLE) {
14330+ if (ecmd->duplex == DUPLEX_FULL) {
14331+ *Buf = (char) SK_LMODE_FULL;
14332+ } else {
14333+ *Buf = (char) SK_LMODE_HALF;
14334+ }
14335+ } else {
14336+ if (ecmd->duplex == DUPLEX_FULL) {
14337+ *Buf = (char) SK_LMODE_AUTOFULL;
14338+ } else {
14339+ *Buf = (char) SK_LMODE_AUTOHALF;
14340+ }
14341+ }
14342
14343- if (ecmd->autoneg == AUTONEG_DISABLE)
14344- *buf = (ecmd->duplex == DUPLEX_FULL)
14345- ? SK_LMODE_FULL : SK_LMODE_HALF;
14346- else
14347- *buf = (ecmd->duplex == DUPLEX_FULL)
14348- ? SK_LMODE_AUTOFULL : SK_LMODE_AUTOHALF;
14349+ Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_LINK_MODE,
14350+ &Buf, &Len, Instance, pNet->NetNr);
14351
14352- instance = pnmiInstance(pNet);
14353- if (SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_LINK_MODE,
14354- &buf, &len, instance, pNet->NetNr) != SK_PNMI_ERR_OK)
14355- return -EINVAL;
14356-
14357- switch(ecmd->speed) {
14358- case SPEED_1000:
14359- *buf = SK_LSPEED_1000MBPS;
14360- break;
14361- case SPEED_100:
14362- *buf = SK_LSPEED_100MBPS;
14363- break;
14364- case SPEED_10:
14365- *buf = SK_LSPEED_10MBPS;
14366+ if (Ret != SK_PNMI_ERR_OK) {
14367+ return -EINVAL;
14368+ }
14369+ } else if (ecmd->autoneg == AUTONEG_ENABLE) {
14370+ /* Set default values */
14371+ *Buf = (char) SK_LMODE_AUTOFULL;
14372+ Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_LINK_MODE,
14373+ &Buf, &Len, Instance, pNet->NetNr);
14374 }
14375
14376- if (SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE,
14377- &buf, &len, instance, pNet->NetNr) != SK_PNMI_ERR_OK)
14378+ if ((ecmd->speed == SPEED_1000) ||
14379+ (ecmd->speed == SPEED_100) ||
14380+ (ecmd->speed == SPEED_10)) {
14381+ if (ecmd->autoneg == AUTONEG_ENABLE) {
14382+ *Buf = (char) SK_LSPEED_AUTO;
14383+ } else if (ecmd->speed == SPEED_1000) {
14384+ *Buf = (char) SK_LSPEED_1000MBPS;
14385+ } else if (ecmd->speed == SPEED_100) {
14386+ *Buf = (char) SK_LSPEED_100MBPS;
14387+ } else {
14388+ *Buf = (char) SK_LSPEED_10MBPS;
14389+ }
14390+
14391+ Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE,
14392+ &Buf, &Len, Instance, pNet->NetNr);
14393+
14394+ if (Ret != SK_PNMI_ERR_OK) {
14395+ return -EINVAL;
14396+ }
14397+ } else if (ecmd->autoneg == AUTONEG_ENABLE) {
14398+ *Buf = (char) SK_LSPEED_AUTO;
14399+ Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE,
14400+ &Buf, &Len, Instance, pNet->NetNr);
14401+ } else {
14402 return -EINVAL;
14403+ }
14404
14405 return 0;
14406 }
14407+#endif
14408
14409+#ifdef ETHTOOL_GPAUSEPARAM
14410 /*****************************************************************************
14411 *
14412- * getDriverInfo - returns generic driver and adapter information
14413+ * getPauseParams - retrieves the pause parameters
14414 *
14415 * Description:
14416- * Generic driver information is returned via this function, such as
14417- * the name of the driver, its version and and firmware version.
14418- * In addition to this, the location of the selected adapter is
14419- * returned as a bus info string (e.g. '01:05.0').
14420- *
14421+ * All current pause parameters of a selected adapter are placed
14422+ * in the passed ethtool_pauseparam structure and are returned.
14423+ *
14424 * Returns: N/A
14425 *
14426 */
14427-static void getDriverInfo(struct net_device *dev, struct ethtool_drvinfo *info)
14428+static void getPauseParams(
14429+SK_AC *pAC, /* pointer to adapter control context */
14430+int port, /* the port of the selected adapter */
14431+struct ethtool_pauseparam *epause) /* pause parameter struct for result */
14432 {
14433- const DEV_NET *pNet = netdev_priv(dev);
14434- const SK_AC *pAC = pNet->pAC;
14435- char vers[32];
14436-
14437- snprintf(vers, sizeof(vers)-1, VER_STRING "(v%d.%d)",
14438- (pAC->GIni.GIPciHwRev >> 4) & 0xf, pAC->GIni.GIPciHwRev & 0xf);
14439-
14440- strlcpy(info->driver, DRIVER_FILE_NAME, sizeof(info->driver));
14441- strcpy(info->version, vers);
14442- strcpy(info->fw_version, "N/A");
14443- strlcpy(info->bus_info, pci_name(pAC->PciDev), ETHTOOL_BUSINFO_LEN);
14444-}
14445-
14446-/*
14447- * Ethtool statistics support.
14448- */
14449-static const char StringsStats[][ETH_GSTRING_LEN] = {
14450- "rx_packets", "tx_packets",
14451- "rx_bytes", "tx_bytes",
14452- "rx_errors", "tx_errors",
14453- "rx_dropped", "tx_dropped",
14454- "multicasts", "collisions",
14455- "rx_length_errors", "rx_buffer_overflow_errors",
14456- "rx_crc_errors", "rx_frame_errors",
14457- "rx_too_short_errors", "rx_too_long_errors",
14458- "rx_carrier_extension_errors", "rx_symbol_errors",
14459- "rx_llc_mac_size_errors", "rx_carrier_errors",
14460- "rx_jabber_errors", "rx_missed_errors",
14461- "tx_abort_collision_errors", "tx_carrier_errors",
14462- "tx_buffer_underrun_errors", "tx_heartbeat_errors",
14463- "tx_window_errors",
14464-};
14465+ SK_GEPORT *pPort = &pAC->GIni.GP[port];
14466
14467-static int getStatsCount(struct net_device *dev)
14468-{
14469- return ARRAY_SIZE(StringsStats);
14470-}
14471+ epause->rx_pause = 0;
14472+ epause->tx_pause = 0;
14473
14474-static void getStrings(struct net_device *dev, u32 stringset, u8 *data)
14475-{
14476- switch(stringset) {
14477- case ETH_SS_STATS:
14478- memcpy(data, *StringsStats, sizeof(StringsStats));
14479- break;
14480+ if (pPort->PFlowCtrlMode == SK_FLOW_MODE_LOC_SEND) {
14481+ epause->tx_pause = 1;
14482+ }
14483+ if ((pPort->PFlowCtrlMode == SK_FLOW_MODE_SYMMETRIC) ||
14484+ (pPort->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM)) {
14485+ epause->tx_pause = 1;
14486+ epause->rx_pause = 1;
14487 }
14488-}
14489
14490-static void getEthtoolStats(struct net_device *dev,
14491- struct ethtool_stats *stats, u64 *data)
14492-{
14493- const DEV_NET *pNet = netdev_priv(dev);
14494- const SK_AC *pAC = pNet->pAC;
14495- const SK_PNMI_STRUCT_DATA *pPnmiStruct = &pAC->PnmiStruct;
14496-
14497- *data++ = pPnmiStruct->Stat[0].StatRxOkCts;
14498- *data++ = pPnmiStruct->Stat[0].StatTxOkCts;
14499- *data++ = pPnmiStruct->Stat[0].StatRxOctetsOkCts;
14500- *data++ = pPnmiStruct->Stat[0].StatTxOctetsOkCts;
14501- *data++ = pPnmiStruct->InErrorsCts;
14502- *data++ = pPnmiStruct->Stat[0].StatTxSingleCollisionCts;
14503- *data++ = pPnmiStruct->RxNoBufCts;
14504- *data++ = pPnmiStruct->TxNoBufCts;
14505- *data++ = pPnmiStruct->Stat[0].StatRxMulticastOkCts;
14506- *data++ = pPnmiStruct->Stat[0].StatTxSingleCollisionCts;
14507- *data++ = pPnmiStruct->Stat[0].StatRxRuntCts;
14508- *data++ = pPnmiStruct->Stat[0].StatRxFifoOverflowCts;
14509- *data++ = pPnmiStruct->Stat[0].StatRxFcsCts;
14510- *data++ = pPnmiStruct->Stat[0].StatRxFramingCts;
14511- *data++ = pPnmiStruct->Stat[0].StatRxShortsCts;
14512- *data++ = pPnmiStruct->Stat[0].StatRxTooLongCts;
14513- *data++ = pPnmiStruct->Stat[0].StatRxCextCts;
14514- *data++ = pPnmiStruct->Stat[0].StatRxSymbolCts;
14515- *data++ = pPnmiStruct->Stat[0].StatRxIRLengthCts;
14516- *data++ = pPnmiStruct->Stat[0].StatRxCarrierCts;
14517- *data++ = pPnmiStruct->Stat[0].StatRxJabberCts;
14518- *data++ = pPnmiStruct->Stat[0].StatRxMissedCts;
14519- *data++ = pAC->stats.tx_aborted_errors;
14520- *data++ = pPnmiStruct->Stat[0].StatTxCarrierCts;
14521- *data++ = pPnmiStruct->Stat[0].StatTxFifoUnderrunCts;
14522- *data++ = pPnmiStruct->Stat[0].StatTxCarrierCts;
14523- *data++ = pAC->stats.tx_window_errors;
14524+ if ((epause->rx_pause == 0) && (epause->tx_pause == 0)) {
14525+ epause->autoneg = SK_FALSE;
14526+ } else {
14527+ epause->autoneg = SK_TRUE;
14528+ }
14529 }
14530+#endif
14531
14532-
14533+#ifdef ETHTOOL_SPAUSEPARAM
14534 /*****************************************************************************
14535 *
14536- * toggleLeds - Changes the LED state of an adapter
14537+ * setPauseParams - configures the pause parameters of an adapter
14538 *
14539 * Description:
14540- * This function changes the current state of all LEDs of an adapter so
14541- * that it can be located by a user.
14542- *
14543- * Returns: N/A
14544+ * This function sets the Rx or Tx pause parameters
14545 *
14546+ * Returns:
14547+ * ==0: everything fine, no error
14548+ * !=0: the return value is the error code of the failure
14549 */
14550-static void toggleLeds(DEV_NET *pNet, int on)
14551+static int setPauseParams(
14552+SK_AC *pAC, /* pointer to adapter control context */
14553+int port, /* the port of the selected adapter */
14554+struct ethtool_pauseparam *epause) /* pause parameter struct with params */
14555 {
14556- SK_AC *pAC = pNet->pAC;
14557- int port = pNet->PortNr;
14558- void __iomem *io = pAC->IoBase;
14559-
14560- if (pAC->GIni.GIGenesis) {
14561- SK_OUT8(io, MR_ADDR(port,LNK_LED_REG),
14562- on ? SK_LNK_ON : SK_LNK_OFF);
14563- SkGeYellowLED(pAC, io,
14564- on ? (LED_ON >> 1) : (LED_OFF >> 1));
14565- SkGeXmitLED(pAC, io, MR_ADDR(port,RX_LED_INI),
14566- on ? SK_LED_TST : SK_LED_DIS);
14567-
14568- if (pAC->GIni.GP[port].PhyType == SK_PHY_BCOM)
14569- SkXmPhyWrite(pAC, io, port, PHY_BCOM_P_EXT_CTRL,
14570- on ? PHY_B_PEC_LED_ON : PHY_B_PEC_LED_OFF);
14571- else if (pAC->GIni.GP[port].PhyType == SK_PHY_LONE)
14572- SkXmPhyWrite(pAC, io, port, PHY_LONE_LED_CFG,
14573- on ? 0x0800 : PHY_L_LC_LEDT);
14574- else
14575- SkGeXmitLED(pAC, io, MR_ADDR(port,TX_LED_INI),
14576- on ? SK_LED_TST : SK_LED_DIS);
14577+ SK_GEPORT *pPort = &pAC->GIni.GP[port];
14578+ DEV_NET *pNet = (DEV_NET *) pAC->dev[port]->priv;
14579+ int PrevSpeedVal = pPort->PLinkSpeedUsed;
14580+
14581+ SK_U32 Instance;
14582+ char Buf[4];
14583+ int Ret;
14584+ SK_BOOL prevAutonegValue = SK_TRUE;
14585+ int prevTxPause = 0;
14586+ int prevRxPause = 0;
14587+ unsigned int Len = 1;
14588+
14589+ if (port == 0) {
14590+ Instance = (pAC->RlmtNets == 2) ? 1 : 2;
14591+ } else {
14592+ Instance = (pAC->RlmtNets == 2) ? 2 : 3;
14593+ }
14594+
14595+ /*
14596+ ** we have to determine the current settings to see if
14597+ ** the operator requested any modification of the flow
14598+ ** control parameters...
14599+ */
14600+ if (pPort->PFlowCtrlMode == SK_FLOW_MODE_LOC_SEND) {
14601+ prevTxPause = 1;
14602+ }
14603+ if ((pPort->PFlowCtrlMode == SK_FLOW_MODE_SYMMETRIC) ||
14604+ (pPort->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM)) {
14605+ prevTxPause = 1;
14606+ prevRxPause = 1;
14607+ }
14608+
14609+ if ((prevRxPause == 0) && (prevTxPause == 0)) {
14610+ prevAutonegValue = SK_FALSE;
14611+ }
14612+
14613+
14614+ /*
14615+ ** perform modifications regarding the changes
14616+ ** requested by the operator
14617+ */
14618+ if (epause->autoneg != prevAutonegValue) {
14619+ if (epause->autoneg == AUTONEG_DISABLE) {
14620+ *Buf = (char) SK_FLOW_MODE_NONE;
14621+ } else {
14622+ *Buf = (char) SK_FLOW_MODE_SYMMETRIC;
14623+ }
14624 } else {
14625- const u16 YukLedOn = (PHY_M_LED_MO_DUP(MO_LED_ON) |
14626- PHY_M_LED_MO_10(MO_LED_ON) |
14627- PHY_M_LED_MO_100(MO_LED_ON) |
14628- PHY_M_LED_MO_1000(MO_LED_ON) |
14629- PHY_M_LED_MO_RX(MO_LED_ON));
14630- const u16 YukLedOff = (PHY_M_LED_MO_DUP(MO_LED_OFF) |
14631- PHY_M_LED_MO_10(MO_LED_OFF) |
14632- PHY_M_LED_MO_100(MO_LED_OFF) |
14633- PHY_M_LED_MO_1000(MO_LED_OFF) |
14634- PHY_M_LED_MO_RX(MO_LED_OFF));
14635-
14636+ if(epause->rx_pause && epause->tx_pause) {
14637+ *Buf = (char) SK_FLOW_MODE_SYMMETRIC;
14638+ } else if (epause->rx_pause && !epause->tx_pause) {
14639+ *Buf = (char) SK_FLOW_MODE_SYM_OR_REM;
14640+ } else if(!epause->rx_pause && epause->tx_pause) {
14641+ *Buf = (char) SK_FLOW_MODE_LOC_SEND;
14642+ } else {
14643+ *Buf = (char) SK_FLOW_MODE_NONE;
14644+ }
14645+ }
14646+
14647+ Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_FLOWCTRL_MODE,
14648+ &Buf, &Len, Instance, pNet->NetNr);
14649+
14650+ if (Ret != SK_PNMI_ERR_OK) {
14651+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_CTRL,
14652+ ("ethtool (sk98lin): error changing rx/tx pause (%i)\n", Ret));
14653+ } else {
14654+ Len = 1; /* set buffer length to correct value */
14655+ }
14656+
14657+ /*
14658+ ** It may be that autoneg has been disabled! Therefore
14659+ ** set the speed to the previously used value...
14660+ */
14661+ *Buf = (char) PrevSpeedVal;
14662
14663- SkGmPhyWrite(pAC,io,port,PHY_MARV_LED_CTRL,0);
14664- SkGmPhyWrite(pAC,io,port,PHY_MARV_LED_OVER,
14665- on ? YukLedOn : YukLedOff);
14666+ Ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE,
14667+ &Buf, &Len, Instance, pNet->NetNr);
14668+
14669+ if (Ret != SK_PNMI_ERR_OK) {
14670+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_CTRL,
14671+ ("ethtool (sk98lin): error setting speed (%i)\n", Ret));
14672 }
14673+ return 0;
14674 }
14675+#endif
14676
14677+#ifdef ETHTOOL_GCOALESCE
14678 /*****************************************************************************
14679 *
14680- * skGeBlinkTimer - Changes the LED state of an adapter
14681+ * getModerationParams - retrieves the IRQ moderation settings
14682 *
14683 * Description:
14684- * This function changes the current state of all LEDs of an adapter so
14685- * that it can be located by a user. If the requested time interval for
14686- * this test has elapsed, this function cleans up everything that was
14687- * temporarily setup during the locate NIC test. This involves of course
14688- * also closing or opening any adapter so that the initial board state
14689- * is recovered.
14690+ * All current IRQ moderation settings of a selected adapter are placed
14691+ * in the passed ethtool_coalesce structure and are returned.
14692 *
14693 * Returns: N/A
14694 *
14695 */
14696-void SkGeBlinkTimer(unsigned long data)
14697+static void getModerationParams(
14698+SK_AC *pAC, /* pointer to adapter control context */
14699+int port, /* the port of the selected adapter */
14700+struct ethtool_coalesce *ecoalesc) /* IRQ moderation struct for results */
14701 {
14702- struct net_device *dev = (struct net_device *) data;
14703- DEV_NET *pNet = netdev_priv(dev);
14704- SK_AC *pAC = pNet->pAC;
14705-
14706- toggleLeds(pNet, pAC->LedsOn);
14707+ DIM_INFO *Info = &pAC->DynIrqModInfo;
14708+ SK_BOOL UseTxIrqModeration = SK_FALSE;
14709+ SK_BOOL UseRxIrqModeration = SK_FALSE;
14710+
14711+ if (Info->IntModTypeSelect != C_INT_MOD_NONE) {
14712+ if (CHIP_ID_YUKON_2(pAC)) {
14713+ UseRxIrqModeration = SK_TRUE;
14714+ UseTxIrqModeration = SK_TRUE;
14715+ } else {
14716+ if ((Info->MaskIrqModeration == IRQ_MASK_RX_ONLY) ||
14717+ (Info->MaskIrqModeration == IRQ_MASK_SP_RX) ||
14718+ (Info->MaskIrqModeration == IRQ_MASK_RX_TX_SP)) {
14719+ UseRxIrqModeration = SK_TRUE;
14720+ }
14721+ if ((Info->MaskIrqModeration == IRQ_MASK_TX_ONLY) ||
14722+ (Info->MaskIrqModeration == IRQ_MASK_SP_TX) ||
14723+ (Info->MaskIrqModeration == IRQ_MASK_RX_TX_SP)) {
14724+ UseTxIrqModeration = SK_TRUE;
14725+ }
14726+ }
14727
14728- pAC->LedsOn = !pAC->LedsOn;
14729- mod_timer(&pAC->BlinkTimer, jiffies + HZ/4);
14730+ if (UseRxIrqModeration) {
14731+ ecoalesc->rx_coalesce_usecs = 1000000 / Info->MaxModIntsPerSec;
14732+ }
14733+ if (UseTxIrqModeration) {
14734+ ecoalesc->tx_coalesce_usecs = 1000000 / Info->MaxModIntsPerSec;
14735+ }
14736+ if (Info->IntModTypeSelect == C_INT_MOD_DYNAMIC) {
14737+ ecoalesc->rate_sample_interval = Info->DynIrqModSampleInterval;
14738+ if (UseRxIrqModeration) {
14739+ ecoalesc->use_adaptive_rx_coalesce = 1;
14740+ ecoalesc->rx_coalesce_usecs_low =
14741+ 1000000 / Info->MaxModIntsPerSecLowerLimit;
14742+ ecoalesc->rx_coalesce_usecs_high =
14743+ 1000000 / Info->MaxModIntsPerSecUpperLimit;
14744+ }
14745+ if (UseTxIrqModeration) {
14746+ ecoalesc->use_adaptive_tx_coalesce = 1;
14747+ ecoalesc->tx_coalesce_usecs_low =
14748+ 1000000 / Info->MaxModIntsPerSecLowerLimit;
14749+ ecoalesc->tx_coalesce_usecs_high =
14750+ 1000000 / Info->MaxModIntsPerSecUpperLimit;
14751+ }
14752+ }
14753+ }
14754 }
14755+#endif
14756
14757+#ifdef ETHTOOL_SCOALESCE
14758 /*****************************************************************************
14759 *
14760- * locateDevice - start the locate NIC feature of the elected adapter
14761+ * setModerationParams - configures the IRQ moderation of an adapter
14762 *
14763 * Description:
14764- * This function is used if the user want to locate a particular NIC.
14765- * All LEDs are regularly switched on and off, so the NIC can easily
14766- * be identified.
14767+ * Depending on the desired IRQ moderation parameters, either a) static,
14768+ * b) dynamic or c) no moderation is configured.
14769 *
14770- * Returns:
14771- * ==0: everything fine, no error, locateNIC test was started
14772- * !=0: one locateNIC test runs already
14773+ * Returns:
14774+ * ==0: everything fine, no error
14775+ * !=0: the return value is the error code of the failure
14776 *
14777+ * Notes:
14778+ * The supported timeframe for the coalesced interrupts ranges from
14779+ * 33.333us (30 IntsPerSec) down to 25us (40.000 IntsPerSec).
14780+ * Any requested value that is not in this range will abort the request!
14781 */
14782-static int locateDevice(struct net_device *dev, u32 data)
14783+static int setModerationParams(
14784+SK_AC *pAC, /* pointer to adapter control context */
14785+int port, /* the port of the selected adapter */
14786+struct ethtool_coalesce *ecoalesc) /* IRQ moderation struct with params */
14787 {
14788- DEV_NET *pNet = netdev_priv(dev);
14789- SK_AC *pAC = pNet->pAC;
14790+ DIM_INFO *Info = &pAC->DynIrqModInfo;
14791+ int PrevModeration = Info->IntModTypeSelect;
14792
14793- if(!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
14794- data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
14795+ Info->IntModTypeSelect = C_INT_MOD_NONE; /* initial default */
14796
14797- /* start blinking */
14798- pAC->LedsOn = 0;
14799- mod_timer(&pAC->BlinkTimer, jiffies);
14800- msleep_interruptible(data * 1000);
14801- del_timer_sync(&pAC->BlinkTimer);
14802- toggleLeds(pNet, 0);
14803+ if ((ecoalesc->rx_coalesce_usecs) || (ecoalesc->tx_coalesce_usecs)) {
14804+ if (ecoalesc->rx_coalesce_usecs) {
14805+ if ((ecoalesc->rx_coalesce_usecs < 25) ||
14806+ (ecoalesc->rx_coalesce_usecs > 33333)) {
14807+ return -EINVAL;
14808+ }
14809+ }
14810+ if (ecoalesc->tx_coalesce_usecs) {
14811+ if ((ecoalesc->tx_coalesce_usecs < 25) ||
14812+ (ecoalesc->tx_coalesce_usecs > 33333)) {
14813+ return -EINVAL;
14814+ }
14815+ }
14816+ if (!CHIP_ID_YUKON_2(pAC)) {
14817+ if ((Info->MaskIrqModeration == IRQ_MASK_SP_RX) ||
14818+ (Info->MaskIrqModeration == IRQ_MASK_SP_TX) ||
14819+ (Info->MaskIrqModeration == IRQ_MASK_RX_TX_SP)) {
14820+ Info->MaskIrqModeration = IRQ_MASK_SP_ONLY;
14821+ }
14822+ }
14823+ Info->IntModTypeSelect = C_INT_MOD_STATIC;
14824+ if (ecoalesc->rx_coalesce_usecs) {
14825+ Info->MaxModIntsPerSec =
14826+ 1000000 / ecoalesc->rx_coalesce_usecs;
14827+ if (!CHIP_ID_YUKON_2(pAC)) {
14828+ if (Info->MaskIrqModeration == IRQ_MASK_TX_ONLY) {
14829+ Info->MaskIrqModeration = IRQ_MASK_TX_RX;
14830+ }
14831+ if (Info->MaskIrqModeration == IRQ_MASK_SP_ONLY) {
14832+ Info->MaskIrqModeration = IRQ_MASK_SP_RX;
14833+ }
14834+ if (Info->MaskIrqModeration == IRQ_MASK_SP_TX) {
14835+ Info->MaskIrqModeration = IRQ_MASK_RX_TX_SP;
14836+ }
14837+ } else {
14838+ Info->MaskIrqModeration = Y2_IRQ_MASK;
14839+ }
14840+ }
14841+ if (ecoalesc->tx_coalesce_usecs) {
14842+ Info->MaxModIntsPerSec =
14843+ 1000000 / ecoalesc->tx_coalesce_usecs;
14844+ if (!CHIP_ID_YUKON_2(pAC)) {
14845+ if (Info->MaskIrqModeration == IRQ_MASK_RX_ONLY) {
14846+ Info->MaskIrqModeration = IRQ_MASK_TX_RX;
14847+ }
14848+ if (Info->MaskIrqModeration == IRQ_MASK_SP_ONLY) {
14849+ Info->MaskIrqModeration = IRQ_MASK_SP_TX;
14850+ }
14851+ if (Info->MaskIrqModeration == IRQ_MASK_SP_RX) {
14852+ Info->MaskIrqModeration = IRQ_MASK_RX_TX_SP;
14853+ }
14854+ } else {
14855+ Info->MaskIrqModeration = Y2_IRQ_MASK;
14856+ }
14857+ }
14858+ }
14859+ if ((ecoalesc->rate_sample_interval) ||
14860+ (ecoalesc->rx_coalesce_usecs_low) ||
14861+ (ecoalesc->tx_coalesce_usecs_low) ||
14862+ (ecoalesc->rx_coalesce_usecs_high)||
14863+ (ecoalesc->tx_coalesce_usecs_high)) {
14864+ if (ecoalesc->rate_sample_interval) {
14865+ if ((ecoalesc->rate_sample_interval < 1) ||
14866+ (ecoalesc->rate_sample_interval > 10)) {
14867+ return -EINVAL;
14868+ }
14869+ }
14870+ if (ecoalesc->rx_coalesce_usecs_low) {
14871+ if ((ecoalesc->rx_coalesce_usecs_low < 25) ||
14872+ (ecoalesc->rx_coalesce_usecs_low > 33333)) {
14873+ return -EINVAL;
14874+ }
14875+ }
14876+ if (ecoalesc->rx_coalesce_usecs_high) {
14877+ if ((ecoalesc->rx_coalesce_usecs_high < 25) ||
14878+ (ecoalesc->rx_coalesce_usecs_high > 33333)) {
14879+ return -EINVAL;
14880+ }
14881+ }
14882+ if (ecoalesc->tx_coalesce_usecs_low) {
14883+ if ((ecoalesc->tx_coalesce_usecs_low < 25) ||
14884+ (ecoalesc->tx_coalesce_usecs_low > 33333)) {
14885+ return -EINVAL;
14886+ }
14887+ }
14888+ if (ecoalesc->tx_coalesce_usecs_high) {
14889+ if ((ecoalesc->tx_coalesce_usecs_high < 25) ||
14890+ (ecoalesc->tx_coalesce_usecs_high > 33333)) {
14891+ return -EINVAL;
14892+ }
14893+ }
14894
14895- return 0;
14896+ Info->IntModTypeSelect = C_INT_MOD_DYNAMIC;
14897+ if (ecoalesc->rate_sample_interval) {
14898+ Info->DynIrqModSampleInterval =
14899+ ecoalesc->rate_sample_interval;
14900+ }
14901+ if (ecoalesc->rx_coalesce_usecs_low) {
14902+ Info->MaxModIntsPerSecLowerLimit =
14903+ 1000000 / ecoalesc->rx_coalesce_usecs_low;
14904+ }
14905+ if (ecoalesc->tx_coalesce_usecs_low) {
14906+ Info->MaxModIntsPerSecLowerLimit =
14907+ 1000000 / ecoalesc->tx_coalesce_usecs_low;
14908+ }
14909+ if (ecoalesc->rx_coalesce_usecs_high) {
14910+ Info->MaxModIntsPerSecUpperLimit =
14911+ 1000000 / ecoalesc->rx_coalesce_usecs_high;
14912+ }
14913+ if (ecoalesc->tx_coalesce_usecs_high) {
14914+ Info->MaxModIntsPerSecUpperLimit =
14915+ 1000000 / ecoalesc->tx_coalesce_usecs_high;
14916+ }
14917+ }
14918+
14919+ if ((PrevModeration == C_INT_MOD_NONE) &&
14920+ (Info->IntModTypeSelect != C_INT_MOD_NONE)) {
14921+ SkDimEnableModerationIfNeeded(pAC);
14922+ }
14923+ if (PrevModeration != C_INT_MOD_NONE) {
14924+ SkDimDisableModeration(pAC, PrevModeration);
14925+ if (Info->IntModTypeSelect != C_INT_MOD_NONE) {
14926+ SkDimEnableModerationIfNeeded(pAC);
14927+ }
14928+ }
14929+
14930+ return 0;
14931 }
14932+#endif
14933
14934+#ifdef ETHTOOL_GWOL
14935 /*****************************************************************************
14936 *
14937- * getPauseParams - retrieves the pause parameters
14938+ * getWOLsettings - retrieves the WOL settings of the selected adapter
14939 *
14940 * Description:
14941- * All current pause parameters of a selected adapter are placed
14942- * in the passed ethtool_pauseparam structure and are returned.
14943+ * All current WOL settings of a selected adapter are placed in the
14944+ * passed ethtool_wolinfo structure and are returned to the caller.
14945 *
14946 * Returns: N/A
14947 *
14948 */
14949-static void getPauseParams(struct net_device *dev, struct ethtool_pauseparam *epause)
14950+static void getWOLsettings(
14951+SK_AC *pAC, /* pointer to adapter control context */
14952+int port, /* the port of the selected adapter */
14953+struct ethtool_wolinfo *ewol) /* mandatory WOL structure for results */
14954 {
14955- DEV_NET *pNet = netdev_priv(dev);
14956- SK_AC *pAC = pNet->pAC;
14957- SK_GEPORT *pPort = &pAC->GIni.GP[pNet->PortNr];
14958-
14959- epause->rx_pause = (pPort->PFlowCtrlMode == SK_FLOW_MODE_SYMMETRIC) ||
14960- (pPort->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM);
14961+ ewol->supported = pAC->WolInfo.SupportedWolOptions;
14962+ ewol->wolopts = pAC->WolInfo.ConfiguredWolOptions;
14963
14964- epause->tx_pause = epause->rx_pause || (pPort->PFlowCtrlMode == SK_FLOW_MODE_LOC_SEND);
14965- epause->autoneg = epause->rx_pause || epause->tx_pause;
14966+ return;
14967 }
14968+#endif
14969
14970+#ifdef ETHTOOL_SWOL
14971 /*****************************************************************************
14972 *
14973- * setPauseParams - configures the pause parameters of an adapter
14974+ * setWOLsettings - configures the WOL settings of a selected adapter
14975 *
14976 * Description:
14977- * This function sets the Rx or Tx pause parameters
14978+ * The WOL settings of a selected adapter are configured regarding
14979+ * the parameters in the passed ethtool_wolinfo structure.
14980+ * Note that currently only wake on magic packet is supported!
14981 *
14982 * Returns:
14983 * ==0: everything fine, no error
14984 * !=0: the return value is the error code of the failure
14985 */
14986-static int setPauseParams(struct net_device *dev , struct ethtool_pauseparam *epause)
14987+static int setWOLsettings(
14988+SK_AC *pAC, /* pointer to adapter control context */
14989+int port, /* the port of the selected adapter */
14990+struct ethtool_wolinfo *ewol) /* WOL structure containing settings */
14991 {
14992- DEV_NET *pNet = netdev_priv(dev);
14993- SK_AC *pAC = pNet->pAC;
14994- SK_GEPORT *pPort = &pAC->GIni.GP[pNet->PortNr];
14995- u32 instance = pnmiInstance(pNet);
14996- struct ethtool_pauseparam old;
14997- u8 oldspeed = pPort->PLinkSpeedUsed;
14998- char buf[4];
14999- int len = 1;
15000- int ret;
15001+ if (((ewol->wolopts & WAKE_MAGIC) == WAKE_MAGIC) || (ewol->wolopts == 0)) {
15002+ pAC->WolInfo.ConfiguredWolOptions = ewol->wolopts;
15003+ return 0;
15004+ }
15005+ return -EFAULT;
15006+}
15007+#endif
15008
15009- /*
15010- ** we have to determine the current settings to see if
15011- ** the operator requested any modification of the flow
15012- ** control parameters...
15013- */
15014- getPauseParams(dev, &old);
15015+#ifdef ETHTOOL_GDRVINFO
15016+/*****************************************************************************
15017+ *
15018+ * getDriverInfo - returns generic driver and adapter information
15019+ *
15020+ * Description:
15021+ * Generic driver information is returned via this function, such as
15022+ * the name of the driver, its version and and firmware version.
15023+ * In addition to this, the location of the selected adapter is
15024+ * returned as a bus info string (e.g. '01:05.0').
15025+ *
15026+ * Returns: N/A
15027+ *
15028+ */
15029+static void getDriverInfo(
15030+SK_AC *pAC, /* pointer to adapter control context */
15031+int port, /* the port of the selected adapter */
15032+struct ethtool_drvinfo *edrvinfo) /* mandatory info structure for results */
15033+{
15034+ char versionString[32];
15035
15036- /*
15037- ** perform modifications regarding the changes
15038- ** requested by the operator
15039- */
15040- if (epause->autoneg != old.autoneg)
15041- *buf = epause->autoneg ? SK_FLOW_MODE_NONE : SK_FLOW_MODE_SYMMETRIC;
15042- else {
15043- if (epause->rx_pause && epause->tx_pause)
15044- *buf = SK_FLOW_MODE_SYMMETRIC;
15045- else if (epause->rx_pause && !epause->tx_pause)
15046- *buf = SK_FLOW_MODE_SYM_OR_REM;
15047- else if (!epause->rx_pause && epause->tx_pause)
15048- *buf = SK_FLOW_MODE_LOC_SEND;
15049- else
15050- *buf = SK_FLOW_MODE_NONE;
15051+ snprintf(versionString, 32, "%s (%s)", VER_STRING, PATCHLEVEL);
15052+ strncpy(edrvinfo->driver, DRIVER_FILE_NAME , 32);
15053+ strncpy(edrvinfo->version, versionString , 32);
15054+ strncpy(edrvinfo->fw_version, "N/A", 32);
15055+ strncpy(edrvinfo->bus_info, pci_name(pAC->PciDev), 32);
15056+
15057+#ifdef ETHTOOL_GSTATS
15058+ edrvinfo->n_stats = SK98LIN_STATS_LEN;
15059+#endif
15060+}
15061+#endif
15062+
15063+#ifdef ETHTOOL_PHYS_ID
15064+/*****************************************************************************
15065+ *
15066+ * startLocateNIC - start the locate NIC feature of the elected adapter
15067+ *
15068+ * Description:
15069+ * This function is used if the user want to locate a particular NIC.
15070+ * All LEDs are regularly switched on and off, so the NIC can easily
15071+ * be identified.
15072+ *
15073+ * Returns:
15074+ * ==0: everything fine, no error, locateNIC test was started
15075+ * !=0: one locateNIC test runs already
15076+ *
15077+ */
15078+static int startLocateNIC(
15079+SK_AC *pAC, /* pointer to adapter control context */
15080+int port, /* the port of the selected adapter */
15081+struct ethtool_value *blinkSecs) /* how long the LEDs should blink in seconds */
15082+{
15083+ struct SK_NET_DEVICE *pDev = pAC->dev[port];
15084+ int OtherPort = (port) ? 0 : 1;
15085+ struct SK_NET_DEVICE *pOtherDev = pAC->dev[OtherPort];
15086+
15087+ if (isLocateNICrunning) {
15088+ return -EFAULT;
15089 }
15090+ isLocateNICrunning = SK_TRUE;
15091+ currentPortIndex = port;
15092+ isDualNetCard = (pDev != pOtherDev) ? SK_TRUE : SK_FALSE;
15093
15094- ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_FLOWCTRL_MODE,
15095- &buf, &len, instance, pNet->NetNr);
15096+ if (netif_running(pAC->dev[port])) {
15097+ boardWasDown[0] = SK_FALSE;
15098+ } else {
15099+ (*pDev->open)(pDev);
15100+ boardWasDown[0] = SK_TRUE;
15101+ }
15102
15103- if (ret != SK_PNMI_ERR_OK) {
15104- SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_CTRL,
15105- ("ethtool (sk98lin): error changing rx/tx pause (%i)\n", ret));
15106- goto err;
15107+ if (isDualNetCard) {
15108+ if (netif_running(pAC->dev[OtherPort])) {
15109+ boardWasDown[1] = SK_FALSE;
15110+ } else {
15111+ (*pOtherDev->open)(pOtherDev);
15112+ boardWasDown[1] = SK_TRUE;
15113+ }
15114 }
15115
15116- /*
15117- ** It may be that autoneg has been disabled! Therefore
15118- ** set the speed to the previously used value...
15119- */
15120- if (!epause->autoneg) {
15121- len = 1;
15122- ret = SkPnmiSetVar(pAC, pAC->IoBase, OID_SKGE_SPEED_MODE,
15123- &oldspeed, &len, instance, pNet->NetNr);
15124- if (ret != SK_PNMI_ERR_OK)
15125- SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_CTRL,
15126- ("ethtool (sk98lin): error setting speed (%i)\n", ret));
15127+ if ((blinkSecs->data < 1) || (blinkSecs->data > 30)) {
15128+ blinkSecs->data = 3; /* three seconds default */
15129 }
15130- err:
15131- return ret ? -EIO : 0;
15132-}
15133+ nbrBlinkQuarterSeconds = 4*blinkSecs->data;
15134
15135-/* Only Yukon supports checksum offload. */
15136-static int setScatterGather(struct net_device *dev, u32 data)
15137-{
15138- DEV_NET *pNet = netdev_priv(dev);
15139- SK_AC *pAC = pNet->pAC;
15140+ init_timer(&locateNICtimer);
15141+ locateNICtimer.function = toggleLeds;
15142+ locateNICtimer.data = (unsigned long) pAC;
15143+ locateNICtimer.expires = jiffies + HZ; /* initially 1sec */
15144+ add_timer(&locateNICtimer);
15145
15146- if (pAC->GIni.GIChipId == CHIP_ID_GENESIS)
15147- return -EOPNOTSUPP;
15148- return ethtool_op_set_sg(dev, data);
15149+ return 0;
15150 }
15151
15152-static int setTxCsum(struct net_device *dev, u32 data)
15153+/*****************************************************************************
15154+ *
15155+ * toggleLeds - Changes the LED state of an adapter
15156+ *
15157+ * Description:
15158+ * This function changes the current state of all LEDs of an adapter so
15159+ * that it can be located by a user. If the requested time interval for
15160+ * this test has elapsed, this function cleans up everything that was
15161+ * temporarily setup during the locate NIC test. This involves of course
15162+ * also closing or opening any adapter so that the initial board state
15163+ * is recovered.
15164+ *
15165+ * Returns: N/A
15166+ *
15167+ */
15168+static void toggleLeds(
15169+unsigned long ptr) /* holds the pointer to adapter control context */
15170 {
15171- DEV_NET *pNet = netdev_priv(dev);
15172- SK_AC *pAC = pNet->pAC;
15173-
15174- if (pAC->GIni.GIChipId == CHIP_ID_GENESIS)
15175- return -EOPNOTSUPP;
15176+ SK_AC *pAC = (SK_AC *) ptr;
15177+ int port = currentPortIndex;
15178+ SK_IOC IoC = pAC->IoBase;
15179+ struct SK_NET_DEVICE *pDev = pAC->dev[port];
15180+ int OtherPort = (port) ? 0 : 1;
15181+ struct SK_NET_DEVICE *pOtherDev = pAC->dev[OtherPort];
15182+
15183+ SK_U16 YukLedOn = (PHY_M_LED_MO_DUP(MO_LED_ON) |
15184+ PHY_M_LED_MO_10(MO_LED_ON) |
15185+ PHY_M_LED_MO_100(MO_LED_ON) |
15186+ PHY_M_LED_MO_1000(MO_LED_ON) |
15187+ PHY_M_LED_MO_RX(MO_LED_ON));
15188+ SK_U16 YukLedOff = (PHY_M_LED_MO_DUP(MO_LED_OFF) |
15189+ PHY_M_LED_MO_10(MO_LED_OFF) |
15190+ PHY_M_LED_MO_100(MO_LED_OFF) |
15191+ PHY_M_LED_MO_1000(MO_LED_OFF) |
15192+ PHY_M_LED_MO_RX(MO_LED_OFF));
15193+
15194+ nbrBlinkQuarterSeconds--;
15195+ if (nbrBlinkQuarterSeconds <= 0) {
15196+ (*pDev->stop)(pDev);
15197+ if (isDualNetCard) {
15198+ (*pOtherDev->stop)(pOtherDev);
15199+ }
15200
15201- return ethtool_op_set_tx_csum(dev, data);
15202-}
15203+ if (!boardWasDown[0]) {
15204+ (*pDev->open)(pDev);
15205+ }
15206+ if (isDualNetCard) {
15207+ (*pOtherDev->open)(pOtherDev);
15208+ }
15209+ isDualNetCard = SK_FALSE;
15210+ isLocateNICrunning = SK_FALSE;
15211+ return;
15212+ }
15213
15214-static u32 getRxCsum(struct net_device *dev)
15215-{
15216- DEV_NET *pNet = netdev_priv(dev);
15217- SK_AC *pAC = pNet->pAC;
15218+ doSwitchLEDsOn = (doSwitchLEDsOn) ? SK_FALSE : SK_TRUE;
15219+ if (doSwitchLEDsOn) {
15220+ if (pAC->GIni.GIGenesis) {
15221+ SK_OUT8(IoC,MR_ADDR(port,LNK_LED_REG),(SK_U8)SK_LNK_ON);
15222+ SkGeYellowLED(pAC,IoC,LED_ON >> 1);
15223+ SkGeXmitLED(pAC,IoC,MR_ADDR(port,RX_LED_INI),SK_LED_TST);
15224+ if (pAC->GIni.GP[port].PhyType == SK_PHY_BCOM) {
15225+ SkXmPhyWrite(pAC,IoC,port,PHY_BCOM_P_EXT_CTRL,PHY_B_PEC_LED_ON);
15226+ } else if (pAC->GIni.GP[port].PhyType == SK_PHY_LONE) {
15227+ SkXmPhyWrite(pAC,IoC,port,PHY_LONE_LED_CFG,0x0800);
15228+ } else {
15229+ SkGeXmitLED(pAC,IoC,MR_ADDR(port,TX_LED_INI),SK_LED_TST);
15230+ }
15231+ } else {
15232+ SkGmPhyWrite(pAC,IoC,port,PHY_MARV_LED_CTRL,0);
15233+ SkGmPhyWrite(pAC,IoC,port,PHY_MARV_LED_OVER,YukLedOn);
15234+ }
15235+ } else {
15236+ if (pAC->GIni.GIGenesis) {
15237+ SK_OUT8(IoC,MR_ADDR(port,LNK_LED_REG),(SK_U8)SK_LNK_OFF);
15238+ SkGeYellowLED(pAC,IoC,LED_OFF >> 1);
15239+ SkGeXmitLED(pAC,IoC,MR_ADDR(port,RX_LED_INI),SK_LED_DIS);
15240+ if (pAC->GIni.GP[port].PhyType == SK_PHY_BCOM) {
15241+ SkXmPhyWrite(pAC,IoC,port,PHY_BCOM_P_EXT_CTRL,PHY_B_PEC_LED_OFF);
15242+ } else if (pAC->GIni.GP[port].PhyType == SK_PHY_LONE) {
15243+ SkXmPhyWrite(pAC,IoC,port,PHY_LONE_LED_CFG,PHY_L_LC_LEDT);
15244+ } else {
15245+ SkGeXmitLED(pAC,IoC,MR_ADDR(port,TX_LED_INI),SK_LED_DIS);
15246+ }
15247+ } else {
15248+ SkGmPhyWrite(pAC,IoC,port,PHY_MARV_LED_CTRL,0);
15249+ SkGmPhyWrite(pAC,IoC,port,PHY_MARV_LED_OVER,YukLedOff);
15250+ }
15251+ }
15252
15253- return pAC->RxPort[pNet->PortNr].RxCsum;
15254-}
15255+ locateNICtimer.function = toggleLeds;
15256+ locateNICtimer.data = (unsigned long) pAC;
15257+ locateNICtimer.expires = jiffies + (HZ/4); /* 250ms */
15258+ add_timer(&locateNICtimer);
15259+}
15260+#endif
15261
15262-static int setRxCsum(struct net_device *dev, u32 data)
15263+/*****************************************************************************
15264+ *
15265+ * getPortNumber - evaluates the port number of an interface
15266+ *
15267+ * Description:
15268+ * It may be that the current interface refers to one which is located
15269+ * on a dual net adapter. Hence, this function will return the correct
15270+ * port for further use.
15271+ *
15272+ * Returns:
15273+ * the port number that corresponds to the selected adapter
15274+ *
15275+ */
15276+static int getPortNumber(
15277+struct net_device *netdev, /* the pointer to netdev structure */
15278+struct ifreq *ifr) /* what interface the request refers to? */
15279 {
15280- DEV_NET *pNet = netdev_priv(dev);
15281- SK_AC *pAC = pNet->pAC;
15282-
15283- if (pAC->GIni.GIChipId == CHIP_ID_GENESIS)
15284- return -EOPNOTSUPP;
15285+ DEV_NET *pNet = (DEV_NET*) netdev->priv;
15286+ SK_AC *pAC = pNet->pAC;
15287
15288- pAC->RxPort[pNet->PortNr].RxCsum = data != 0;
15289+ if (pAC->dev[1] != pAC->dev[0]) {
15290+ if (!strcmp(pAC->dev[1]->name, ifr->ifr_name)) {
15291+ return 1; /* port index 1 */
15292+ }
15293+ }
15294 return 0;
15295 }
15296
15297-struct ethtool_ops SkGeEthtoolOps = {
15298- .get_settings = getSettings,
15299- .set_settings = setSettings,
15300- .get_drvinfo = getDriverInfo,
15301- .get_strings = getStrings,
15302- .get_stats_count = getStatsCount,
15303- .get_ethtool_stats = getEthtoolStats,
15304- .phys_id = locateDevice,
15305- .get_pauseparam = getPauseParams,
15306- .set_pauseparam = setPauseParams,
15307- .get_link = ethtool_op_get_link,
15308- .get_perm_addr = ethtool_op_get_perm_addr,
15309- .get_sg = ethtool_op_get_sg,
15310- .set_sg = setScatterGather,
15311- .get_tx_csum = ethtool_op_get_tx_csum,
15312- .set_tx_csum = setTxCsum,
15313- .get_rx_csum = getRxCsum,
15314- .set_rx_csum = setRxCsum,
15315-};
15316+/*******************************************************************************
15317+ *
15318+ * End of file
15319+ *
15320+ ******************************************************************************/
15321diff -ruN linux/drivers/net/sk98lin/skge.c linux-new/drivers/net/sk98lin/skge.c
15322--- linux/drivers/net/sk98lin/skge.c 2006-04-11 19:19:28.000000000 +0200
15323+++ linux-new/drivers/net/sk98lin/skge.c 2006-01-18 14:37:24.000000000 +0100
15324@@ -1,32 +1,26 @@
15325 /******************************************************************************
15326 *
15327- * Name: skge.c
15328- * Project: GEnesis, PCI Gigabit Ethernet Adapter
15329- * Version: $Revision$
15330- * Date: $Date$
15331- * Purpose: The main driver source module
15332+ * Name: skge.c
15333+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
15334+ * Version: $Revision$
15335+ * Date: $Date$
15336+ * Purpose: The main driver source module
15337 *
15338 ******************************************************************************/
15339
15340 /******************************************************************************
15341 *
15342 * (C)Copyright 1998-2002 SysKonnect GmbH.
15343- * (C)Copyright 2002-2003 Marvell.
15344+ * (C)Copyright 2002-2005 Marvell.
15345 *
15346 * Driver for Marvell Yukon chipset and SysKonnect Gigabit Ethernet
15347 * Server Adapters.
15348 *
15349- * Created 10-Feb-1999, based on Linux' acenic.c, 3c59x.c and
15350- * SysKonnects GEnesis Solaris driver
15351- * Author: Christoph Goos (cgoos@syskonnect.de)
15352- * Mirko Lindner (mlindner@syskonnect.de)
15353+ * Author: Mirko Lindner (mlindner@syskonnect.de)
15354+ * Ralph Roesler (rroesler@syskonnect.de)
15355 *
15356 * Address all question to: linux@syskonnect.de
15357 *
15358- * The technical manual for the adapters is available from SysKonnect's
15359- * web pages: www.syskonnect.com
15360- * Goto "Support" and search Knowledge Base for "manual".
15361- *
15362 * This program is free software; you can redistribute it and/or modify
15363 * it under the terms of the GNU General Public License as published by
15364 * the Free Software Foundation; either version 2 of the License, or
15365@@ -38,85 +32,53 @@
15366
15367 /******************************************************************************
15368 *
15369- * Possible compiler options (#define xxx / -Dxxx):
15370- *
15371- * debugging can be enable by changing SK_DEBUG_CHKMOD and
15372- * SK_DEBUG_CHKCAT in makefile (described there).
15373- *
15374- ******************************************************************************/
15375-
15376-/******************************************************************************
15377- *
15378 * Description:
15379 *
15380- * This is the main module of the Linux GE driver.
15381- *
15382- * All source files except skge.c, skdrv1st.h, skdrv2nd.h and sktypes.h
15383- * are part of SysKonnect's COMMON MODULES for the SK-98xx adapters.
15384- * Those are used for drivers on multiple OS', so some thing may seem
15385- * unnecessary complicated on Linux. Please do not try to 'clean up'
15386- * them without VERY good reasons, because this will make it more
15387- * difficult to keep the Linux driver in synchronisation with the
15388- * other versions.
15389- *
15390- * Include file hierarchy:
15391- *
15392- * <linux/module.h>
15393- *
15394- * "h/skdrv1st.h"
15395- * <linux/types.h>
15396- * <linux/kernel.h>
15397- * <linux/string.h>
15398- * <linux/errno.h>
15399- * <linux/ioport.h>
15400- * <linux/slab.h>
15401- * <linux/interrupt.h>
15402- * <linux/pci.h>
15403- * <linux/bitops.h>
15404- * <asm/byteorder.h>
15405- * <asm/io.h>
15406- * <linux/netdevice.h>
15407- * <linux/etherdevice.h>
15408- * <linux/skbuff.h>
15409- * those three depending on kernel version used:
15410- * <linux/bios32.h>
15411- * <linux/init.h>
15412- * <asm/uaccess.h>
15413- * <net/checksum.h>
15414- *
15415- * "h/skerror.h"
15416- * "h/skdebug.h"
15417- * "h/sktypes.h"
15418- * "h/lm80.h"
15419- * "h/xmac_ii.h"
15420- *
15421- * "h/skdrv2nd.h"
15422- * "h/skqueue.h"
15423- * "h/skgehwt.h"
15424- * "h/sktimer.h"
15425- * "h/ski2c.h"
15426- * "h/skgepnmi.h"
15427- * "h/skvpd.h"
15428- * "h/skgehw.h"
15429- * "h/skgeinit.h"
15430- * "h/skaddr.h"
15431- * "h/skgesirq.h"
15432- * "h/skrlmt.h"
15433+ * All source files in this sk98lin directory except of the sk98lin
15434+ * Linux specific files
15435+ *
15436+ * - skdim.c
15437+ * - skethtool.c
15438+ * - skge.c
15439+ * - skproc.c
15440+ * - sky2.c
15441+ * - Makefile
15442+ * - h/skdrv1st.h
15443+ * - h/skdrv2nd.h
15444+ * - h/sktypes.h
15445+ * - h/skversion.h
15446+ *
15447+ * are part of SysKonnect's common modules for the SK-9xxx adapters.
15448+ *
15449+ * Those common module files which are not Linux specific are used to
15450+ * build drivers on different OS' (e.g. Windows, MAC OS) so that those
15451+ * drivers are based on the same set of files
15452+ *
15453+ * At a first glance, this seems to complicate things unnescessarily on
15454+ * Linux, but please do not try to 'clean up' them without VERY good
15455+ * reasons, because this will make it more difficult to keep the sk98lin
15456+ * driver for Linux in synchronisation with the other drivers running on
15457+ * other operating systems.
15458 *
15459 ******************************************************************************/
15460
15461 #include "h/skversion.h"
15462
15463-#include <linux/in.h>
15464 #include <linux/module.h>
15465-#include <linux/moduleparam.h>
15466 #include <linux/init.h>
15467-#include <linux/dma-mapping.h>
15468-#include <linux/ip.h>
15469+#include <linux/ethtool.h>
15470+
15471+#ifdef CONFIG_PROC_FS
15472+#include <linux/proc_fs.h>
15473+#endif
15474
15475 #include "h/skdrv1st.h"
15476 #include "h/skdrv2nd.h"
15477
15478+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
15479+#include <linux/moduleparam.h>
15480+#endif
15481+
15482 /*******************************************************************************
15483 *
15484 * Defines
15485@@ -126,62 +88,14 @@
15486 /* for debuging on x86 only */
15487 /* #define BREAKPOINT() asm(" int $3"); */
15488
15489-/* use the transmit hw checksum driver functionality */
15490-#define USE_SK_TX_CHECKSUM
15491-
15492-/* use the receive hw checksum driver functionality */
15493-#define USE_SK_RX_CHECKSUM
15494-
15495-/* use the scatter-gather functionality with sendfile() */
15496-#define SK_ZEROCOPY
15497-
15498-/* use of a transmit complete interrupt */
15499-#define USE_TX_COMPLETE
15500-
15501-/*
15502- * threshold for copying small receive frames
15503- * set to 0 to avoid copying, set to 9001 to copy all frames
15504- */
15505-#define SK_COPY_THRESHOLD 50
15506-
15507-/* number of adapters that can be configured via command line params */
15508-#define SK_MAX_CARD_PARAM 16
15509-
15510-
15511-
15512-/*
15513- * use those defines for a compile-in version of the driver instead
15514- * of command line parameters
15515- */
15516-// #define LINK_SPEED_A {"Auto", }
15517-// #define LINK_SPEED_B {"Auto", }
15518-// #define AUTO_NEG_A {"Sense", }
15519-// #define AUTO_NEG_B {"Sense", }
15520-// #define DUP_CAP_A {"Both", }
15521-// #define DUP_CAP_B {"Both", }
15522-// #define FLOW_CTRL_A {"SymOrRem", }
15523-// #define FLOW_CTRL_B {"SymOrRem", }
15524-// #define ROLE_A {"Auto", }
15525-// #define ROLE_B {"Auto", }
15526-// #define PREF_PORT {"A", }
15527-// #define CON_TYPE {"Auto", }
15528-// #define RLMT_MODE {"CheckLinkState", }
15529-
15530-#define DEV_KFREE_SKB(skb) dev_kfree_skb(skb)
15531-#define DEV_KFREE_SKB_IRQ(skb) dev_kfree_skb_irq(skb)
15532-#define DEV_KFREE_SKB_ANY(skb) dev_kfree_skb_any(skb)
15533-
15534
15535 /* Set blink mode*/
15536 #define OEM_CONFIG_VALUE ( SK_ACT_LED_BLINK | \
15537 SK_DUP_LED_NORMAL | \
15538 SK_LED_LINK100_ON)
15539
15540-
15541-/* Isr return value */
15542-#define SkIsrRetVar irqreturn_t
15543-#define SkIsrRetNone IRQ_NONE
15544-#define SkIsrRetHandled IRQ_HANDLED
15545+#define CLEAR_AND_START_RX(Port) SK_OUT8(pAC->IoBase, RxQueueAddr[(Port)]+Q_CSR, CSR_START | CSR_IRQ_CL_F)
15546+#define CLEAR_TX_IRQ(Port,Prio) SK_OUT8(pAC->IoBase, TxQueueAddr[(Port)][(Prio)]+Q_CSR, CSR_IRQ_CL_F)
15547
15548
15549 /*******************************************************************************
15550@@ -190,12 +104,25 @@
15551 *
15552 ******************************************************************************/
15553
15554+static int __devinit sk98lin_init_device(struct pci_dev *pdev, const struct pci_device_id *ent);
15555+static void sk98lin_remove_device(struct pci_dev *pdev);
15556+#ifdef CONFIG_PM
15557+static int sk98lin_suspend(struct pci_dev *pdev, u32 state);
15558+static int sk98lin_resume(struct pci_dev *pdev);
15559+static void SkEnableWOMagicPacket(SK_AC *pAC, SK_IOC IoC, SK_MAC_ADDR MacAddr);
15560+#endif
15561+#ifdef Y2_RECOVERY
15562+static void SkGeHandleKernelTimer(unsigned long ptr);
15563+void SkGeCheckTimer(DEV_NET *pNet);
15564+static SK_BOOL CheckRXCounters(DEV_NET *pNet);
15565+static void CheckRxPath(DEV_NET *pNet);
15566+#endif
15567 static void FreeResources(struct SK_NET_DEVICE *dev);
15568 static int SkGeBoardInit(struct SK_NET_DEVICE *dev, SK_AC *pAC);
15569 static SK_BOOL BoardAllocMem(SK_AC *pAC);
15570 static void BoardFreeMem(SK_AC *pAC);
15571 static void BoardInitMem(SK_AC *pAC);
15572-static void SetupRing(SK_AC*, void*, uintptr_t, RXD**, RXD**, RXD**, int*, SK_BOOL);
15573+static void SetupRing(SK_AC*, void*, uintptr_t, RXD**, RXD**, RXD**, int*, int*, SK_BOOL);
15574 static SkIsrRetVar SkGeIsr(int irq, void *dev_id, struct pt_regs *ptregs);
15575 static SkIsrRetVar SkGeIsrOnePort(int irq, void *dev_id, struct pt_regs *ptregs);
15576 static int SkGeOpen(struct SK_NET_DEVICE *dev);
15577@@ -206,39 +133,76 @@
15578 static struct net_device_stats *SkGeStats(struct SK_NET_DEVICE *dev);
15579 static int SkGeIoctl(struct SK_NET_DEVICE *dev, struct ifreq *rq, int cmd);
15580 static void GetConfiguration(SK_AC*);
15581+static void ProductStr(SK_AC*);
15582 static int XmitFrame(SK_AC*, TX_PORT*, struct sk_buff*);
15583 static void FreeTxDescriptors(SK_AC*pAC, TX_PORT*);
15584 static void FillRxRing(SK_AC*, RX_PORT*);
15585 static SK_BOOL FillRxDescriptor(SK_AC*, RX_PORT*);
15586+#ifdef CONFIG_SK98LIN_NAPI
15587+static int SkGePoll(struct net_device *dev, int *budget);
15588+static void ReceiveIrq(SK_AC*, RX_PORT*, SK_BOOL, int*, int);
15589+#else
15590 static void ReceiveIrq(SK_AC*, RX_PORT*, SK_BOOL);
15591-static void ClearAndStartRx(SK_AC*, int);
15592-static void ClearTxIrq(SK_AC*, int, int);
15593+#endif
15594+#ifdef SK_POLL_CONTROLLER
15595+static void SkGeNetPoll(struct SK_NET_DEVICE *dev);
15596+#endif
15597 static void ClearRxRing(SK_AC*, RX_PORT*);
15598 static void ClearTxRing(SK_AC*, TX_PORT*);
15599 static int SkGeChangeMtu(struct SK_NET_DEVICE *dev, int new_mtu);
15600 static void PortReInitBmu(SK_AC*, int);
15601 static int SkGeIocMib(DEV_NET*, unsigned int, int);
15602 static int SkGeInitPCI(SK_AC *pAC);
15603-static void StartDrvCleanupTimer(SK_AC *pAC);
15604-static void StopDrvCleanupTimer(SK_AC *pAC);
15605-static int XmitFrameSG(SK_AC*, TX_PORT*, struct sk_buff*);
15606-
15607-#ifdef SK_DIAG_SUPPORT
15608 static SK_U32 ParseDeviceNbrFromSlotName(const char *SlotName);
15609 static int SkDrvInitAdapter(SK_AC *pAC, int devNbr);
15610 static int SkDrvDeInitAdapter(SK_AC *pAC, int devNbr);
15611-#endif
15612+extern void SkLocalEventQueue( SK_AC *pAC,
15613+ SK_U32 Class,
15614+ SK_U32 Event,
15615+ SK_U32 Param1,
15616+ SK_U32 Param2,
15617+ SK_BOOL Flag);
15618+extern void SkLocalEventQueue64( SK_AC *pAC,
15619+ SK_U32 Class,
15620+ SK_U32 Event,
15621+ SK_U64 Param,
15622+ SK_BOOL Flag);
15623+
15624+static int XmitFrameSG(SK_AC*, TX_PORT*, struct sk_buff*);
15625
15626 /*******************************************************************************
15627 *
15628 * Extern Function Prototypes
15629 *
15630 ******************************************************************************/
15631+
15632+extern SK_BOOL SkY2AllocateResources(SK_AC *pAC);
15633+extern void SkY2FreeResources(SK_AC *pAC);
15634+extern void SkY2AllocateRxBuffers(SK_AC *pAC,SK_IOC IoC,int Port);
15635+extern void SkY2FreeRxBuffers(SK_AC *pAC,SK_IOC IoC,int Port);
15636+extern void SkY2FreeTxBuffers(SK_AC *pAC,SK_IOC IoC,int Port);
15637+extern SkIsrRetVar SkY2Isr(int irq,void *dev_id,struct pt_regs *ptregs);
15638+extern int SkY2Xmit(struct sk_buff *skb,struct SK_NET_DEVICE *dev);
15639+extern void SkY2PortStop(SK_AC *pAC,SK_IOC IoC,int Port,int Dir,int RstMode);
15640+extern void SkY2PortStart(SK_AC *pAC,SK_IOC IoC,int Port);
15641+extern int SkY2RlmtSend(SK_AC *pAC,int PortNr,struct sk_buff *pMessage);
15642+extern void SkY2RestartStatusUnit(SK_AC *pAC);
15643+extern void FillReceiveTableYukon2(SK_AC *pAC,SK_IOC IoC,int Port);
15644+#ifdef CONFIG_SK98LIN_NAPI
15645+extern int SkY2Poll(struct net_device *dev, int *budget);
15646+#endif
15647+
15648 extern void SkDimEnableModerationIfNeeded(SK_AC *pAC);
15649-extern void SkDimDisplayModerationSettings(SK_AC *pAC);
15650 extern void SkDimStartModerationTimer(SK_AC *pAC);
15651 extern void SkDimModerate(SK_AC *pAC);
15652-extern void SkGeBlinkTimer(unsigned long data);
15653+
15654+extern int SkEthIoctl(struct net_device *netdev, struct ifreq *ifr);
15655+
15656+#ifdef CONFIG_PROC_FS
15657+static const char SK_Root_Dir_entry[] = "sk98lin";
15658+static struct proc_dir_entry *pSkRootDir;
15659+extern struct file_operations sk_proc_fops;
15660+#endif
15661
15662 #ifdef DEBUG
15663 static void DumpMsg(struct sk_buff*, char*);
15664@@ -247,33 +211,436 @@
15665 #endif
15666
15667 /* global variables *********************************************************/
15668+static const char *BootString = BOOT_STRING;
15669+struct SK_NET_DEVICE *SkGeRootDev = NULL;
15670 static SK_BOOL DoPrintInterfaceChange = SK_TRUE;
15671-extern struct ethtool_ops SkGeEthtoolOps;
15672
15673 /* local variables **********************************************************/
15674 static uintptr_t TxQueueAddr[SK_MAX_MACS][2] = {{0x680, 0x600},{0x780, 0x700}};
15675 static uintptr_t RxQueueAddr[SK_MAX_MACS] = {0x400, 0x480};
15676+static int sk98lin_max_boards_found = 0;
15677+
15678+#ifdef CONFIG_PROC_FS
15679+static struct proc_dir_entry *pSkRootDir;
15680+#endif
15681+
15682+
15683+
15684+static struct pci_device_id sk98lin_pci_tbl[] __devinitdata = {
15685+/* { pci_vendor_id, pci_device_id, * SAMPLE ENTRY! *
15686+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, */
15687+ { 0x10b7, 0x1700, /* 3Com (10b7), Gigabit Ethernet Adapter */
15688+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
15689+ { 0x10b7, 0x80eb, /* 3Com (10b7), 3Com 3C940B Gigabit LOM Ethernet Adapter */
15690+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
15691+ { 0x1148, 0x4300, /* SysKonnect (1148), SK-98xx Gigabit Ethernet Server Adapter */
15692+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
15693+ { 0x1148, 0x4320, /* SysKonnect (1148), SK-98xx V2.0 Gigabit Ethernet Adapter */
15694+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
15695+ { 0x1148, 0x9000, /* SysKonnect (1148), SK-9Sxx 10/100/1000Base-T Server Adapter */
15696+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
15697+ { 0x1148, 0x9E00, /* SysKonnect (1148), SK-9Exx 10/100/1000Base-T Adapter */
15698+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
15699+ { 0x1186, 0x4b00, /* D-Link (1186), Gigabit Ethernet Adapter */
15700+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
15701+ { 0x1186, 0x4b01, /* D-Link (1186), Gigabit Ethernet Adapter */
15702+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
15703+ { 0x1186, 0x4c00, /* D-Link (1186), Gigabit Ethernet Adapter */
15704+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
15705+ { 0x11ab, 0x4320, /* Marvell (11ab), Gigabit Ethernet Controller */
15706+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
15707+ { 0x11ab, 0x4340, /* Marvell (11ab), Gigabit Ethernet Controller */
15708+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
15709+ { 0x11ab, 0x4341, /* Marvell (11ab), Gigabit Ethernet Controller */
15710+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
15711+ { 0x11ab, 0x4342, /* Marvell (11ab), Gigabit Ethernet Controller */
15712+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
15713+ { 0x11ab, 0x4343, /* Marvell (11ab), Gigabit Ethernet Controller */
15714+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
15715+ { 0x11ab, 0x4344, /* Marvell (11ab), Gigabit Ethernet Controller */
15716+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
15717+ { 0x11ab, 0x4345, /* Marvell (11ab), Gigabit Ethernet Controller */
15718+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
15719+ { 0x11ab, 0x4346, /* Marvell (11ab), Gigabit Ethernet Controller */
15720+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
15721+ { 0x11ab, 0x4347, /* Marvell (11ab), Gigabit Ethernet Controller */
15722+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
15723+ { 0x11ab, 0x4350, /* Marvell (11ab), Fast Ethernet Controller */
15724+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
15725+ { 0x11ab, 0x4351, /* Marvell (11ab), Fast Ethernet Controller */
15726+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
15727+ { 0x11ab, 0x4352, /* Marvell (11ab), Fast Ethernet Controller */
15728+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
15729+ { 0x11ab, 0x4360, /* Marvell (11ab), Gigabit Ethernet Controller */
15730+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
15731+ { 0x11ab, 0x4361, /* Marvell (11ab), Gigabit Ethernet Controller */
15732+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
15733+ { 0x11ab, 0x4362, /* Marvell (11ab), Gigabit Ethernet Controller */
15734+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
15735+ { 0x11ab, 0x4363, /* Marvell (11ab), Marvell */
15736+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
15737+ { 0x11ab, 0x5005, /* Marvell (11ab), Belkin */
15738+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
15739+ { 0x1371, 0x434e, /* CNet (1371), GigaCard Network Adapter */
15740+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
15741+ { 0x1737, 0x1032, /* Linksys (1737), Gigabit Network Adapter */
15742+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
15743+ { 0x1737, 0x1064, /* Linksys (1737), Gigabit Network Adapter */
15744+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
15745+ { 0, }
15746+};
15747+
15748+MODULE_DEVICE_TABLE(pci, sk98lin_pci_tbl);
15749+
15750+static struct pci_driver sk98lin_driver = {
15751+ .name = DRIVER_FILE_NAME,
15752+ .id_table = sk98lin_pci_tbl,
15753+ .probe = sk98lin_init_device,
15754+ .remove = __devexit_p(sk98lin_remove_device),
15755+#ifdef CONFIG_PM
15756+ .suspend = sk98lin_suspend,
15757+ .resume = sk98lin_resume
15758+#endif
15759+};
15760+
15761
15762 /*****************************************************************************
15763 *
15764- * SkPciWriteCfgDWord - write a 32 bit value to pci config space
15765+ * sk98lin_init_device - initialize the adapter
15766 *
15767 * Description:
15768- * This routine writes a 32 bit value to the pci configuration
15769- * space.
15770+ * This function initializes the adapter. Resources for
15771+ * the adapter are allocated and the adapter is brought into Init 1
15772+ * state.
15773 *
15774 * Returns:
15775- * 0 - indicate everything worked ok.
15776- * != 0 - error indication
15777+ * 0, if everything is ok
15778+ * !=0, on error
15779 */
15780-static inline int SkPciWriteCfgDWord(
15781-SK_AC *pAC, /* Adapter Control structure pointer */
15782-int PciAddr, /* PCI register address */
15783-SK_U32 Val) /* pointer to store the read value */
15784+static int __devinit sk98lin_init_device(struct pci_dev *pdev,
15785+ const struct pci_device_id *ent)
15786+
15787 {
15788- pci_write_config_dword(pAC->PciDev, PciAddr, Val);
15789- return(0);
15790-} /* SkPciWriteCfgDWord */
15791+ static SK_BOOL sk98lin_boot_string = SK_FALSE;
15792+ static SK_BOOL sk98lin_proc_entry = SK_FALSE;
15793+ static int sk98lin_boards_found = 0;
15794+ SK_AC *pAC;
15795+ DEV_NET *pNet = NULL;
15796+ struct SK_NET_DEVICE *dev = NULL;
15797+ int retval;
15798+#ifdef CONFIG_PROC_FS
15799+ struct proc_dir_entry *pProcFile;
15800+#endif
15801+ int pci_using_dac;
15802+
15803+ retval = pci_enable_device(pdev);
15804+ if (retval) {
15805+ printk(KERN_ERR "Cannot enable PCI device, "
15806+ "aborting.\n");
15807+ return retval;
15808+ }
15809+
15810+ dev = NULL;
15811+ pNet = NULL;
15812+
15813+
15814+ /* INSERT * We have to find the power-management capabilities */
15815+ /* Find power-management capability. */
15816+
15817+ pci_using_dac = 0; /* Set 32 bit DMA per default */
15818+ /* Configure DMA attributes. */
15819+ retval = pci_set_dma_mask(pdev, (u64) 0xffffffffffffffffULL);
15820+ if (!retval) {
15821+ pci_using_dac = 1;
15822+ } else {
15823+ retval = pci_set_dma_mask(pdev, (u64) 0xffffffff);
15824+ if (retval) {
15825+ printk(KERN_ERR "No usable DMA configuration, "
15826+ "aborting.\n");
15827+ return retval;
15828+ }
15829+ }
15830+
15831+
15832+ if ((dev = alloc_etherdev(sizeof(DEV_NET))) == NULL) {
15833+ printk(KERN_ERR "Unable to allocate etherdev "
15834+ "structure!\n");
15835+ return -ENODEV;
15836+ }
15837+
15838+ pNet = dev->priv;
15839+ pNet->pAC = kmalloc(sizeof(SK_AC), GFP_KERNEL);
15840+ if (pNet->pAC == NULL){
15841+ free_netdev(dev);
15842+ printk(KERN_ERR "Unable to allocate adapter "
15843+ "structure!\n");
15844+ return -ENODEV;
15845+ }
15846+
15847+
15848+ /* Print message */
15849+ if (!sk98lin_boot_string) {
15850+ /* set display flag to TRUE so that */
15851+ /* we only display this string ONCE */
15852+ sk98lin_boot_string = SK_TRUE;
15853+ printk("%s\n", BootString);
15854+ }
15855+
15856+ memset(pNet->pAC, 0, sizeof(SK_AC));
15857+ pAC = pNet->pAC;
15858+ pAC->PciDev = pdev;
15859+ pAC->PciDevId = pdev->device;
15860+ pAC->dev[0] = dev;
15861+ pAC->dev[1] = dev;
15862+ sprintf(pAC->Name, "SysKonnect SK-98xx");
15863+ pAC->CheckQueue = SK_FALSE;
15864+
15865+ dev->irq = pdev->irq;
15866+ retval = SkGeInitPCI(pAC);
15867+ if (retval) {
15868+ printk("SKGE: PCI setup failed: %i\n", retval);
15869+ free_netdev(dev);
15870+ return -ENODEV;
15871+ }
15872+
15873+ SET_MODULE_OWNER(dev);
15874+
15875+ dev->open = &SkGeOpen;
15876+ dev->stop = &SkGeClose;
15877+ dev->get_stats = &SkGeStats;
15878+ dev->set_multicast_list = &SkGeSetRxMode;
15879+ dev->set_mac_address = &SkGeSetMacAddr;
15880+ dev->do_ioctl = &SkGeIoctl;
15881+ dev->change_mtu = &SkGeChangeMtu;
15882+ dev->flags &= ~IFF_RUNNING;
15883+#ifdef SK_POLL_CONTROLLER
15884+ dev->poll_controller = SkGeNetPoll;
15885+#endif
15886+ SET_NETDEV_DEV(dev, &pdev->dev);
15887+
15888+ pAC->Index = sk98lin_boards_found;
15889+
15890+ if (SkGeBoardInit(dev, pAC)) {
15891+ free_netdev(dev);
15892+ return -ENODEV;
15893+ } else {
15894+ ProductStr(pAC);
15895+ }
15896+
15897+ if (pci_using_dac)
15898+ dev->features |= NETIF_F_HIGHDMA;
15899+
15900+ /* shifter to later moment in time... */
15901+ if (CHIP_ID_YUKON_2(pAC)) {
15902+ dev->hard_start_xmit = &SkY2Xmit;
15903+#ifdef CONFIG_SK98LIN_NAPI
15904+ dev->poll = &SkY2Poll;
15905+ dev->weight = 64;
15906+#endif
15907+ } else {
15908+ dev->hard_start_xmit = &SkGeXmit;
15909+#ifdef CONFIG_SK98LIN_NAPI
15910+ dev->poll = &SkGePoll;
15911+ dev->weight = 64;
15912+#endif
15913+ }
15914+
15915+#ifdef NETIF_F_TSO
15916+#ifdef USE_SK_TSO_FEATURE
15917+ if ((CHIP_ID_YUKON_2(pAC)) &&
15918+ (pAC->GIni.GIChipId != CHIP_ID_YUKON_EC_U)) {
15919+ dev->features |= NETIF_F_TSO;
15920+ }
15921+#endif
15922+#endif
15923+#ifdef CONFIG_SK98LIN_ZEROCOPY
15924+ if (pAC->GIni.GIChipId != CHIP_ID_GENESIS)
15925+ dev->features |= NETIF_F_SG;
15926+#endif
15927+#ifdef USE_SK_TX_CHECKSUM
15928+ if (pAC->GIni.GIChipId != CHIP_ID_GENESIS)
15929+ dev->features |= NETIF_F_IP_CSUM;
15930+#endif
15931+#ifdef USE_SK_RX_CHECKSUM
15932+ pAC->RxPort[0].UseRxCsum = SK_TRUE;
15933+ if (pAC->GIni.GIMacsFound == 2 ) {
15934+ pAC->RxPort[1].UseRxCsum = SK_TRUE;
15935+ }
15936+#endif
15937+
15938+ /* Save the hardware revision */
15939+ pAC->HWRevision = (((pAC->GIni.GIPciHwRev >> 4) & 0x0F)*10) +
15940+ (pAC->GIni.GIPciHwRev & 0x0F);
15941+
15942+ /* Set driver globals */
15943+ pAC->Pnmi.pDriverFileName = DRIVER_FILE_NAME;
15944+ pAC->Pnmi.pDriverReleaseDate = DRIVER_REL_DATE;
15945+
15946+ SK_MEMSET(&(pAC->PnmiBackup), 0, sizeof(SK_PNMI_STRUCT_DATA));
15947+ SK_MEMCPY(&(pAC->PnmiBackup), &(pAC->PnmiStruct),
15948+ sizeof(SK_PNMI_STRUCT_DATA));
15949+
15950+ /* Register net device */
15951+ retval = register_netdev(dev);
15952+ if (retval) {
15953+ printk(KERN_ERR "SKGE: Could not register device.\n");
15954+ FreeResources(dev);
15955+ free_netdev(dev);
15956+ return retval;
15957+ }
15958+
15959+ /* Save initial device name */
15960+ strcpy(pNet->InitialDevName, dev->name);
15961+
15962+ /* Set network to off */
15963+ netif_stop_queue(dev);
15964+ netif_carrier_off(dev);
15965+
15966+ /* Print adapter specific string from vpd and config settings */
15967+ printk("%s: %s\n", pNet->InitialDevName, pAC->DeviceStr);
15968+ printk(" PrefPort:%c RlmtMode:%s\n",
15969+ 'A' + pAC->Rlmt.Net[0].Port[pAC->Rlmt.Net[0].PrefPort]->PortNumber,
15970+ (pAC->RlmtMode==0) ? "Check Link State" :
15971+ ((pAC->RlmtMode==1) ? "Check Link State" :
15972+ ((pAC->RlmtMode==3) ? "Check Local Port" :
15973+ ((pAC->RlmtMode==7) ? "Check Segmentation" :
15974+ ((pAC->RlmtMode==17) ? "Dual Check Link State" :"Error")))));
15975+
15976+ SkGeYellowLED(pAC, pAC->IoBase, 1);
15977+
15978+ memcpy((caddr_t) &dev->dev_addr,
15979+ (caddr_t) &pAC->Addr.Net[0].CurrentMacAddress, 6);
15980+
15981+ /* First adapter... Create proc and print message */
15982+#ifdef CONFIG_PROC_FS
15983+ if (!sk98lin_proc_entry) {
15984+ sk98lin_proc_entry = SK_TRUE;
15985+ SK_MEMCPY(&SK_Root_Dir_entry, BootString,
15986+ sizeof(SK_Root_Dir_entry) - 1);
15987+
15988+ /*Create proc (directory)*/
15989+ if(!pSkRootDir) {
15990+ pSkRootDir = proc_mkdir(SK_Root_Dir_entry, proc_net);
15991+ if (!pSkRootDir) {
15992+ printk(KERN_WARNING "%s: Unable to create /proc/net/%s",
15993+ dev->name, SK_Root_Dir_entry);
15994+ } else {
15995+ pSkRootDir->owner = THIS_MODULE;
15996+ }
15997+ }
15998+ }
15999+
16000+ /* Create proc file */
16001+ if (pSkRootDir &&
16002+ (pProcFile = create_proc_entry(pNet->InitialDevName, S_IRUGO,
16003+ pSkRootDir))) {
16004+ pProcFile->proc_fops = &sk_proc_fops;
16005+ pProcFile->data = dev;
16006+ }
16007+
16008+#endif
16009+
16010+ pNet->PortNr = 0;
16011+ pNet->NetNr = 0;
16012+
16013+ sk98lin_boards_found++;
16014+ pci_set_drvdata(pdev, dev);
16015+
16016+ /* More then one port found */
16017+ if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
16018+ if ((dev = alloc_etherdev(sizeof(DEV_NET))) == 0) {
16019+ printk(KERN_ERR "Unable to allocate etherdev "
16020+ "structure!\n");
16021+ return -ENODEV;
16022+ }
16023+
16024+ pAC->dev[1] = dev;
16025+ pNet = dev->priv;
16026+ pNet->PortNr = 1;
16027+ pNet->NetNr = 1;
16028+ pNet->pAC = pAC;
16029+
16030+ if (CHIP_ID_YUKON_2(pAC)) {
16031+ dev->hard_start_xmit = &SkY2Xmit;
16032+#ifdef CONFIG_SK98LIN_NAPI
16033+ dev->poll = &SkY2Poll;
16034+ dev->weight = 64;
16035+#endif
16036+ } else {
16037+ dev->hard_start_xmit = &SkGeXmit;
16038+#ifdef CONFIG_SK98LIN_NAPI
16039+ dev->poll = &SkGePoll;
16040+ dev->weight = 64;
16041+#endif
16042+ }
16043+ dev->open = &SkGeOpen;
16044+ dev->stop = &SkGeClose;
16045+ dev->get_stats = &SkGeStats;
16046+ dev->set_multicast_list = &SkGeSetRxMode;
16047+ dev->set_mac_address = &SkGeSetMacAddr;
16048+ dev->do_ioctl = &SkGeIoctl;
16049+ dev->change_mtu = &SkGeChangeMtu;
16050+ dev->flags &= ~IFF_RUNNING;
16051+#ifdef SK_POLL_CONTROLLER
16052+ dev->poll_controller = SkGeNetPoll;
16053+#endif
16054+
16055+#ifdef NETIF_F_TSO
16056+#ifdef USE_SK_TSO_FEATURE
16057+ if ((CHIP_ID_YUKON_2(pAC)) &&
16058+ (pAC->GIni.GIChipId != CHIP_ID_YUKON_EC_U)) {
16059+ dev->features |= NETIF_F_TSO;
16060+ }
16061+#endif
16062+#endif
16063+#ifdef CONFIG_SK98LIN_ZEROCOPY
16064+ /* Don't handle if Genesis chipset */
16065+ if (pAC->GIni.GIChipId != CHIP_ID_GENESIS)
16066+ dev->features |= NETIF_F_SG;
16067+#endif
16068+#ifdef USE_SK_TX_CHECKSUM
16069+ /* Don't handle if Genesis chipset */
16070+ if (pAC->GIni.GIChipId != CHIP_ID_GENESIS)
16071+ dev->features |= NETIF_F_IP_CSUM;
16072+#endif
16073+
16074+ if (register_netdev(dev)) {
16075+ printk(KERN_ERR "SKGE: Could not register device.\n");
16076+ free_netdev(dev);
16077+ pAC->dev[1] = pAC->dev[0];
16078+ } else {
16079+
16080+ /* Save initial device name */
16081+ strcpy(pNet->InitialDevName, dev->name);
16082+
16083+ /* Set network to off */
16084+ netif_stop_queue(dev);
16085+ netif_carrier_off(dev);
16086+
16087+
16088+#ifdef CONFIG_PROC_FS
16089+ if (pSkRootDir
16090+ && (pProcFile = create_proc_entry(pNet->InitialDevName,
16091+ S_IRUGO, pSkRootDir))) {
16092+ pProcFile->proc_fops = &sk_proc_fops;
16093+ pProcFile->data = dev;
16094+ }
16095+#endif
16096+
16097+ memcpy((caddr_t) &dev->dev_addr,
16098+ (caddr_t) &pAC->Addr.Net[1].CurrentMacAddress, 6);
16099+
16100+ printk("%s: %s\n", pNet->InitialDevName, pAC->DeviceStr);
16101+ printk(" PrefPort:B RlmtMode:Dual Check Link State\n");
16102+ }
16103+ }
16104+
16105+ pAC->Index = sk98lin_boards_found;
16106+ sk98lin_max_boards_found = sk98lin_boards_found;
16107+ return 0;
16108+}
16109+
16110+
16111
16112 /*****************************************************************************
16113 *
16114@@ -282,22 +649,26 @@
16115 * Description:
16116 * This function initialize the PCI resources and IO
16117 *
16118- * Returns:
16119- * 0 - indicate everything worked ok.
16120- * != 0 - error indication
16121+ * Returns: N/A
16122+ *
16123 */
16124-static __devinit int SkGeInitPCI(SK_AC *pAC)
16125+int SkGeInitPCI(SK_AC *pAC)
16126 {
16127 struct SK_NET_DEVICE *dev = pAC->dev[0];
16128 struct pci_dev *pdev = pAC->PciDev;
16129 int retval;
16130
16131+ if (pci_enable_device(pdev) != 0) {
16132+ return 1;
16133+ }
16134+
16135 dev->mem_start = pci_resource_start (pdev, 0);
16136 pci_set_master(pdev);
16137
16138- retval = pci_request_regions(pdev, "sk98lin");
16139- if (retval)
16140- goto out;
16141+ if (pci_request_regions(pdev, DRIVER_FILE_NAME) != 0) {
16142+ retval = 2;
16143+ goto out_disable;
16144+ }
16145
16146 #ifdef SK_BIG_ENDIAN
16147 /*
16148@@ -315,9 +686,10 @@
16149 /*
16150 * Remap the regs into kernel space.
16151 */
16152- pAC->IoBase = ioremap_nocache(dev->mem_start, 0x4000);
16153- if (!pAC->IoBase) {
16154- retval = -EIO;
16155+ pAC->IoBase = (char*)ioremap_nocache(dev->mem_start, 0x4000);
16156+
16157+ if (!pAC->IoBase){
16158+ retval = 3;
16159 goto out_release;
16160 }
16161
16162@@ -325,10 +697,460 @@
16163
16164 out_release:
16165 pci_release_regions(pdev);
16166- out:
16167+ out_disable:
16168+ pci_disable_device(pdev);
16169 return retval;
16170 }
16171
16172+#ifdef Y2_RECOVERY
16173+/*****************************************************************************
16174+ *
16175+ * SkGeHandleKernelTimer - Handle the kernel timer requests
16176+ *
16177+ * Description:
16178+ * If the requested time interval for the timer has elapsed,
16179+ * this function checks the link state.
16180+ *
16181+ * Returns: N/A
16182+ *
16183+ */
16184+static void SkGeHandleKernelTimer(
16185+unsigned long ptr) /* holds the pointer to adapter control context */
16186+{
16187+ DEV_NET *pNet = (DEV_NET*) ptr;
16188+ SkGeCheckTimer(pNet);
16189+}
16190+
16191+/*****************************************************************************
16192+ *
16193+ * sk98lin_check_timer - Resume the the card
16194+ *
16195+ * Description:
16196+ * This function checks the kernel timer
16197+ *
16198+ * Returns: N/A
16199+ *
16200+ */
16201+void SkGeCheckTimer(
16202+DEV_NET *pNet) /* holds the pointer to adapter control context */
16203+{
16204+ SK_AC *pAC = pNet->pAC;
16205+ SK_BOOL StartTimer = SK_TRUE;
16206+
16207+ if (pNet->InRecover)
16208+ return;
16209+ if (pNet->TimerExpired)
16210+ return;
16211+ pNet->TimerExpired = SK_TRUE;
16212+
16213+#define TXPORT pAC->TxPort[pNet->PortNr][TX_PRIO_LOW]
16214+#define RXPORT pAC->RxPort[pNet->PortNr]
16215+
16216+ if ( (CHIP_ID_YUKON_2(pAC)) &&
16217+ (netif_running(pAC->dev[pNet->PortNr]))) {
16218+
16219+#ifdef Y2_RX_CHECK
16220+ if (HW_FEATURE(pAC, HWF_WA_DEV_4167)) {
16221+ /* Checks the RX path */
16222+ CheckRxPath(pNet);
16223+ }
16224+#endif
16225+
16226+ /* Checkthe transmitter */
16227+ if (!(IS_Q_EMPTY(&TXPORT.TxAQ_working))) {
16228+ if (TXPORT.LastDone != TXPORT.TxALET.Done) {
16229+ TXPORT.LastDone = TXPORT.TxALET.Done;
16230+ pNet->TransmitTimeoutTimer = 0;
16231+ } else {
16232+ pNet->TransmitTimeoutTimer++;
16233+ if (pNet->TransmitTimeoutTimer >= 10) {
16234+ pNet->TransmitTimeoutTimer = 0;
16235+#ifdef CHECK_TRANSMIT_TIMEOUT
16236+ StartTimer = SK_FALSE;
16237+ SkLocalEventQueue(pAC, SKGE_DRV,
16238+ SK_DRV_RECOVER,pNet->PortNr,-1,SK_FALSE);
16239+#endif
16240+ }
16241+ }
16242+ }
16243+
16244+#ifdef CHECK_TRANSMIT_TIMEOUT
16245+// if (!timer_pending(&pNet->KernelTimer)) {
16246+ pNet->KernelTimer.expires = jiffies + (HZ/4); /* 100ms */
16247+ add_timer(&pNet->KernelTimer);
16248+ pNet->TimerExpired = SK_FALSE;
16249+// }
16250+#endif
16251+ }
16252+}
16253+
16254+
16255+/*****************************************************************************
16256+*
16257+* CheckRXCounters - Checks the the statistics for RX path hang
16258+*
16259+* Description:
16260+* This function is called periodical by a timer.
16261+*
16262+* Notes:
16263+*
16264+* Function Parameters:
16265+*
16266+* Returns:
16267+* Traffic status
16268+*
16269+*/
16270+static SK_BOOL CheckRXCounters(
16271+DEV_NET *pNet) /* holds the pointer to adapter control context */
16272+{
16273+ SK_AC *pAC = pNet->pAC;
16274+ SK_BOOL bStatus = SK_FALSE;
16275+
16276+ /* Variable used to store the MAC RX FIFO RP, RPLev*/
16277+ SK_U32 MACFifoRP = 0;
16278+ SK_U32 MACFifoRLev = 0;
16279+
16280+ /* Variable used to store the PCI RX FIFO RP, RPLev*/
16281+ SK_U32 RXFifoRP = 0;
16282+ SK_U8 RXFifoRLev = 0;
16283+
16284+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
16285+ ("==> CheckRXCounters()\n"));
16286+
16287+ /*Check if statistic counters hangs*/
16288+ if (pNet->LastJiffies == pAC->dev[pNet->PortNr]->last_rx) {
16289+ /* Now read the values of read pointer/level from MAC RX FIFO again */
16290+ SK_IN32(pAC->IoBase, MR_ADDR(pNet->PortNr, RX_GMF_RP), &MACFifoRP);
16291+ SK_IN32(pAC->IoBase, MR_ADDR(pNet->PortNr, RX_GMF_RLEV), &MACFifoRLev);
16292+
16293+ /* Now read the values of read pointer/level from RX FIFO again */
16294+ SK_IN8(pAC->IoBase, Q_ADDR(pAC->GIni.GP[pNet->PortNr].PRxQOff, Q_RX_RP), &RXFifoRP);
16295+ SK_IN8(pAC->IoBase, Q_ADDR(pAC->GIni.GP[pNet->PortNr].PRxQOff, Q_RX_RL), &RXFifoRLev);
16296+
16297+ /* Check if the MAC RX hang */
16298+ if ((MACFifoRP == pNet->PreviousMACFifoRP) &&
16299+ (pNet->PreviousMACFifoRP != 0) &&
16300+ (MACFifoRLev >= pNet->PreviousMACFifoRLev)){
16301+ bStatus = SK_TRUE;
16302+ }
16303+
16304+ /* Check if the PCI RX hang */
16305+ if ((RXFifoRP == pNet->PreviousRXFifoRP) &&
16306+ (pNet->PreviousRXFifoRP != 0) &&
16307+ (RXFifoRLev >= pNet->PreviousRXFifoRLev)){
16308+ /*Set the flag to indicate that the RX FIFO hangs*/
16309+ bStatus = SK_TRUE;
16310+ }
16311+ }
16312+
16313+ /* Store now the values of counters for next check */
16314+ pNet->LastJiffies = pAC->dev[pNet->PortNr]->last_rx;
16315+
16316+ /* Store the values of read pointer/level from MAC RX FIFO for next test */
16317+ pNet->PreviousMACFifoRP = MACFifoRP;
16318+ pNet->PreviousMACFifoRLev = MACFifoRLev;
16319+
16320+ /* Store the values of read pointer/level from RX FIFO for next test */
16321+ pNet->PreviousRXFifoRP = RXFifoRP;
16322+ pNet->PreviousRXFifoRLev = RXFifoRLev;
16323+
16324+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
16325+ ("<== CheckRXCounters()\n"));
16326+
16327+ return bStatus;
16328+}
16329+
16330+/*****************************************************************************
16331+*
16332+* CheckRxPath - Checks if the RX path
16333+*
16334+* Description:
16335+* This function is called periodical by a timer.
16336+*
16337+* Notes:
16338+*
16339+* Function Parameters:
16340+*
16341+* Returns:
16342+* None.
16343+*
16344+*/
16345+static void CheckRxPath(
16346+DEV_NET *pNet) /* holds the pointer to adapter control context */
16347+{
16348+ unsigned long Flags; /* for the spin locks */
16349+ /* Initialize the pAC structure.*/
16350+ SK_AC *pAC = pNet->pAC;
16351+
16352+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
16353+ ("==> CheckRxPath()\n"));
16354+
16355+ /*If the statistics are not changed then could be an RX problem */
16356+ if (CheckRXCounters(pNet)){
16357+ /*
16358+ * First we try the simple solution by resetting the Level Timer
16359+ */
16360+
16361+ /* Stop Level Timer of Status BMU */
16362+ SK_OUT8(pAC->IoBase, STAT_LEV_TIMER_CTRL, TIM_STOP);
16363+
16364+ /* Start Level Timer of Status BMU */
16365+ SK_OUT8(pAC->IoBase, STAT_LEV_TIMER_CTRL, TIM_START);
16366+
16367+ if (!CheckRXCounters(pNet)) {
16368+ return;
16369+ }
16370+
16371+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
16372+ SkLocalEventQueue(pAC, SKGE_DRV,
16373+ SK_DRV_RECOVER,pNet->PortNr,-1,SK_TRUE);
16374+
16375+ /* Reset the fifo counters */
16376+ pNet->PreviousMACFifoRP = 0;
16377+ pNet->PreviousMACFifoRLev = 0;
16378+ pNet->PreviousRXFifoRP = 0;
16379+ pNet->PreviousRXFifoRLev = 0;
16380+
16381+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
16382+ }
16383+
16384+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
16385+ ("<== CheckRxPath()\n"));
16386+}
16387+
16388+
16389+
16390+#endif
16391+
16392+
16393+#ifdef CONFIG_PM
16394+/*****************************************************************************
16395+ *
16396+ * sk98lin_resume - Resume the the card
16397+ *
16398+ * Description:
16399+ * This function resumes the card into the D0 state
16400+ *
16401+ * Returns: N/A
16402+ *
16403+ */
16404+static int sk98lin_resume(
16405+struct pci_dev *pdev) /* the device that is to resume */
16406+{
16407+ struct net_device *dev = pci_get_drvdata(pdev);
16408+ DEV_NET *pNet = (DEV_NET*) dev->priv;
16409+ SK_AC *pAC = pNet->pAC;
16410+ SK_U16 PmCtlSts;
16411+
16412+ /* Set the power state to D0 */
16413+ pci_set_power_state(pdev, 0);
16414+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
16415+ pci_restore_state(pdev);
16416+#else
16417+ pci_restore_state(pdev, pAC->PciState);
16418+#endif
16419+
16420+ /* Set the adapter power state to D0 */
16421+ SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);
16422+ PmCtlSts &= ~(PCI_PM_STATE_D3); /* reset all DState bits */
16423+ PmCtlSts |= PCI_PM_STATE_D0;
16424+ SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PmCtlSts);
16425+
16426+ /* Reinit the adapter and start the port again */
16427+ pAC->BoardLevel = SK_INIT_DATA;
16428+ SkDrvLeaveDiagMode(pAC);
16429+
16430+ netif_device_attach(dev);
16431+ netif_start_queue(dev);
16432+ return 0;
16433+}
16434+
16435+/*****************************************************************************
16436+ *
16437+ * sk98lin_suspend - Suspend the card
16438+ *
16439+ * Description:
16440+ * This function suspends the card into a defined state
16441+ *
16442+ * Returns: N/A
16443+ *
16444+ */
16445+static int sk98lin_suspend(
16446+struct pci_dev *pdev, /* pointer to the device that is to suspend */
16447+u32 state) /* what power state is desired by Linux? */
16448+{
16449+ struct net_device *dev = pci_get_drvdata(pdev);
16450+ DEV_NET *pNet = (DEV_NET*) dev->priv;
16451+ SK_AC *pAC = pNet->pAC;
16452+ SK_U16 PciPMControlStatus;
16453+ SK_U16 PciPMCapabilities;
16454+ SK_MAC_ADDR MacAddr;
16455+ int i;
16456+
16457+ /* GEnesis and first yukon revs do not support power management */
16458+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {
16459+ if (pAC->GIni.GIChipRev == 0) {
16460+ return 0; /* power management not supported */
16461+ }
16462+ }
16463+
16464+ if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
16465+ return 0; /* not supported for this chipset */
16466+ }
16467+
16468+ if (pAC->WolInfo.ConfiguredWolOptions == 0) {
16469+ return 0; /* WOL possible, but disabled via ethtool */
16470+ }
16471+
16472+ if(netif_running(dev)) {
16473+ netif_stop_queue(dev); /* stop device if running */
16474+ }
16475+
16476+ netif_device_detach(dev);
16477+
16478+ /* read the PM control/status register from the PCI config space */
16479+ SK_IN16(pAC->IoBase, PCI_C(pAC, PCI_PM_CTL_STS), &PciPMControlStatus);
16480+
16481+ /* read the power management capabilities from the config space */
16482+ SK_IN16(pAC->IoBase, PCI_C(pAC, PCI_PM_CAP_REG), &PciPMCapabilities);
16483+
16484+ /* Enable WakeUp with Magic Packet - get MAC address from adapter */
16485+ for (i = 0; i < SK_MAC_ADDR_LEN; i++) {
16486+ /* virtual address: will be used for data */
16487+ SK_IN8(pAC->IoBase, (B2_MAC_1 + i), &MacAddr.a[i]);
16488+ }
16489+
16490+ SkDrvEnterDiagMode(pAC);
16491+ SkEnableWOMagicPacket(pAC, pAC->IoBase, MacAddr);
16492+
16493+ pci_enable_wake(pdev, 3, 1);
16494+ pci_enable_wake(pdev, 4, 1); /* 4 == D3 cold */
16495+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
16496+ pci_save_state(pdev);
16497+#else
16498+ pci_save_state(pdev, pAC->PciState);
16499+#endif
16500+ pci_set_power_state(pdev, state); /* set the state */
16501+
16502+ return 0;
16503+}
16504+
16505+
16506+/******************************************************************************
16507+ *
16508+ * SkEnableWOMagicPacket - Enable Wake on Magic Packet on the adapter
16509+ *
16510+ * Context:
16511+ * init, pageable
16512+ * the adapter should be de-initialized before calling this function
16513+ *
16514+ * Returns:
16515+ * nothing
16516+ */
16517+
16518+static void SkEnableWOMagicPacket(
16519+SK_AC *pAC, /* Adapter Control Context */
16520+SK_IOC IoC, /* I/O control context */
16521+SK_MAC_ADDR MacAddr) /* MacAddr expected in magic packet */
16522+{
16523+ SK_U16 Word;
16524+ SK_U32 DWord;
16525+ int i;
16526+ int HwPortIndex;
16527+ int Port = 0;
16528+
16529+ /* use Port 0 as long as we do not have any dual port cards which support WOL */
16530+ HwPortIndex = 0;
16531+ DWord = 0;
16532+
16533+ SK_OUT16(IoC, 0x0004, 0x0002); /* clear S/W Reset */
16534+ SK_OUT16(IoC, 0x0f10, 0x0002); /* clear Link Reset */
16535+
16536+ /*
16537+ * PHY Configuration:
16538+ * Autonegotioation is enalbed, advertise 10 HD, 10 FD,
16539+ * 100 HD, and 100 FD.
16540+ */
16541+ if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) ||
16542+ (pAC->GIni.GIChipId == CHIP_ID_YUKON) ||
16543+ (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE)) {
16544+
16545+ SK_OUT16(IoC, 0x0004, 0x0800); /* enable CLK_RUN */
16546+ SK_OUT8(IoC, 0x0007, 0xa9); /* enable VAUX */
16547+
16548+ /* WA code for COMA mode */
16549+ /* Only for yukon plus based chipsets rev A3 */
16550+ if (pAC->GIni.GIChipRev == CHIP_REV_YU_LITE_A3) {
16551+ SK_IN32(IoC, B2_GP_IO, &DWord);
16552+ DWord |= GP_DIR_9; /* set to output */
16553+ DWord &= ~GP_IO_9; /* clear PHY reset (active high) */
16554+ SK_OUT32(IoC, B2_GP_IO, DWord); /* clear PHY reset */
16555+ }
16556+
16557+ if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) ||
16558+ (pAC->GIni.GIChipId == CHIP_ID_YUKON)) {
16559+ SK_OUT32(IoC, 0x0f04, 0x01f04001); /* set PHY reset */
16560+ SK_OUT32(IoC, 0x0f04, 0x01f04002); /* clear PHY reset */
16561+ } else {
16562+ SK_OUT8(IoC, 0x0f04, 0x02); /* clear PHY reset */
16563+ }
16564+
16565+ SK_OUT8(IoC, 0x0f00, 0x02); /* clear MAC reset */
16566+ SkGmPhyWrite(pAC, IoC, Port, 4, 0x01e1); /* advertise 10/100 HD/FD */
16567+ SkGmPhyWrite(pAC, IoC, Port, 9, 0x0000); /* do not advertise 1000 HD/FD */
16568+ SkGmPhyWrite(pAC, IoC, Port, 00, 0xB300); /* 100 MBit, disable Autoneg */
16569+ } else if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) {
16570+ SK_OUT8(IoC, 0x0007, 0xa9); /* enable VAUX */
16571+ SK_OUT8(IoC, 0x0f04, 0x02); /* clear PHY reset */
16572+ SK_OUT8(IoC, 0x0f00, 0x02); /* clear MAC reset */
16573+ SkGmPhyWrite(pAC, IoC, Port, 16, 0x0130); /* Enable Automatic Crossover */
16574+ SkGmPhyWrite(pAC, IoC, Port, 00, 0xB300); /* 100 MBit, disable Autoneg */
16575+ }
16576+
16577+
16578+ /*
16579+ * MAC Configuration:
16580+ * Set the MAC to 100 HD and enable the auto update features
16581+ * for Speed, Flow Control and Duplex Mode.
16582+ * If autonegotiation completes successfully the
16583+ * MAC takes the link parameters from the PHY.
16584+ * If the link partner doesn't support autonegotiation
16585+ * the MAC can receive magic packets if the link partner
16586+ * uses 100 HD.
16587+ */
16588+ SK_OUT16(IoC, 0x2804, 0x3832);
16589+
16590+
16591+ /*
16592+ * Set Up Magic Packet parameters
16593+ */
16594+ for (i = 0; i < 6; i+=2) { /* set up magic packet MAC address */
16595+ SK_IN16(IoC, 0x100 + i, &Word);
16596+ SK_OUT16(IoC, 0xf24 + i, Word);
16597+ }
16598+
16599+ SK_OUT16(IoC, 0x0f20, 0x0208); /* enable PME on magic packet */
16600+ /* and on wake up frame */
16601+
16602+ /*
16603+ * Set up PME generation
16604+ */
16605+ /* set PME legacy mode */
16606+ /* Only for PCI express based chipsets */
16607+ if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) ||
16608+ (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE)) {
16609+ SkPciReadCfgDWord(pAC, 0x40, &DWord);
16610+ DWord |= 0x8000;
16611+ SkPciWriteCfgDWord(pAC, 0x40, DWord);
16612+ }
16613+
16614+ /* clear PME status and switch adapter to DState */
16615+ SkPciReadCfgWord(pAC, 0x4c, &Word);
16616+ Word |= 0x103;
16617+ SkPciWriteCfgWord(pAC, 0x4c, Word);
16618+} /* SkEnableWOMagicPacket */
16619+#endif
16620+
16621
16622 /*****************************************************************************
16623 *
16624@@ -347,20 +1169,24 @@
16625 DEV_NET *pNet;
16626 SK_AC *pAC;
16627
16628- pNet = netdev_priv(dev);
16629- pAC = pNet->pAC;
16630- AllocFlag = pAC->AllocFlag;
16631- if (pAC->PciDev) {
16632- pci_release_regions(pAC->PciDev);
16633- }
16634- if (AllocFlag & SK_ALLOC_IRQ) {
16635- free_irq(dev->irq, dev);
16636- }
16637- if (pAC->IoBase) {
16638- iounmap(pAC->IoBase);
16639- }
16640- if (pAC->pDescrMem) {
16641- BoardFreeMem(pAC);
16642+ if (dev->priv) {
16643+ pNet = (DEV_NET*) dev->priv;
16644+ pAC = pNet->pAC;
16645+ AllocFlag = pAC->AllocFlag;
16646+ if (pAC->PciDev) {
16647+ pci_release_regions(pAC->PciDev);
16648+ }
16649+ if (AllocFlag & SK_ALLOC_IRQ) {
16650+ free_irq(dev->irq, dev);
16651+ }
16652+ if (pAC->IoBase) {
16653+ iounmap(pAC->IoBase);
16654+ }
16655+ if (CHIP_ID_YUKON_2(pAC)) {
16656+ SkY2FreeResources(pAC);
16657+ } else {
16658+ BoardFreeMem(pAC);
16659+ }
16660 }
16661
16662 } /* FreeResources */
16663@@ -369,6 +1195,7 @@
16664 MODULE_DESCRIPTION("SysKonnect SK-NET Gigabit Ethernet SK-98xx driver");
16665 MODULE_LICENSE("GPL");
16666
16667+
16668 #ifdef LINK_SPEED_A
16669 static char *Speed_A[SK_MAX_CARD_PARAM] = LINK_SPEED;
16670 #else
16671@@ -441,37 +1268,146 @@
16672 static char *PrefPort[SK_MAX_CARD_PARAM] = {"", };
16673 #endif
16674
16675-#ifdef RLMT_MODE
16676-static char *RlmtMode[SK_MAX_CARD_PARAM] = RLMT_MODE;
16677-#else
16678-static char *RlmtMode[SK_MAX_CARD_PARAM] = {"", };
16679+#ifdef RLMT_MODE
16680+static char *RlmtMode[SK_MAX_CARD_PARAM] = RLMT_MODE;
16681+#else
16682+static char *RlmtMode[SK_MAX_CARD_PARAM] = {"", };
16683+#endif
16684+
16685+static int IntsPerSec[SK_MAX_CARD_PARAM];
16686+static char *Moderation[SK_MAX_CARD_PARAM];
16687+static char *ModerationMask[SK_MAX_CARD_PARAM];
16688+
16689+static char *LowLatency[SK_MAX_CARD_PARAM];
16690+
16691+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9)
16692+module_param_array(Speed_A, charp, NULL, 0);
16693+module_param_array(Speed_B, charp, NULL, 0);
16694+module_param_array(AutoNeg_A, charp, NULL, 0);
16695+module_param_array(AutoNeg_B, charp, NULL, 0);
16696+module_param_array(DupCap_A, charp, NULL, 0);
16697+module_param_array(DupCap_B, charp, NULL, 0);
16698+module_param_array(FlowCtrl_A, charp, NULL, 0);
16699+module_param_array(FlowCtrl_B, charp, NULL, 0);
16700+module_param_array(Role_A, charp, NULL, 0);
16701+module_param_array(Role_B, charp, NULL, 0);
16702+module_param_array(ConType, charp, NULL, 0);
16703+module_param_array(PrefPort, charp, NULL, 0);
16704+module_param_array(RlmtMode, charp, NULL, 0);
16705+/* used for interrupt moderation */
16706+module_param_array(IntsPerSec, int, NULL, 0);
16707+module_param_array(Moderation, charp, NULL, 0);
16708+module_param_array(ModerationMask, charp, NULL, 0);
16709+module_param_array(LowLatency, charp, NULL, 0);
16710+#else
16711+MODULE_PARM(Speed_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16712+MODULE_PARM(Speed_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16713+MODULE_PARM(AutoNeg_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16714+MODULE_PARM(AutoNeg_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16715+MODULE_PARM(DupCap_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16716+MODULE_PARM(DupCap_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16717+MODULE_PARM(FlowCtrl_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16718+MODULE_PARM(FlowCtrl_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16719+MODULE_PARM(Role_A, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16720+MODULE_PARM(Role_B, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16721+MODULE_PARM(ConType, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16722+MODULE_PARM(PrefPort, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16723+MODULE_PARM(RlmtMode, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16724+MODULE_PARM(IntsPerSec, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "i");
16725+MODULE_PARM(Moderation, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16726+MODULE_PARM(ModerationMask, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16727+MODULE_PARM(LowLatency, "1-" __MODULE_STRING(SK_MAX_CARD_PARAM) "s");
16728+#endif
16729+
16730+
16731+/*****************************************************************************
16732+ *
16733+ * sk98lin_remove_device - device deinit function
16734+ *
16735+ * Description:
16736+ * Disable adapter if it is still running, free resources,
16737+ * free device struct.
16738+ *
16739+ * Returns: N/A
16740+ */
16741+
16742+static void sk98lin_remove_device(struct pci_dev *pdev)
16743+{
16744+DEV_NET *pNet;
16745+SK_AC *pAC;
16746+struct SK_NET_DEVICE *next;
16747+unsigned long Flags;
16748+struct net_device *dev = pci_get_drvdata(pdev);
16749+
16750+
16751+ /* Device not available. Return. */
16752+ if (!dev)
16753+ return;
16754+
16755+ pNet = (DEV_NET*) dev->priv;
16756+ pAC = pNet->pAC;
16757+ next = pAC->Next;
16758+
16759+ netif_stop_queue(dev);
16760+ SkGeYellowLED(pAC, pAC->IoBase, 0);
16761+
16762+ if(pAC->BoardLevel == SK_INIT_RUN) {
16763+ /* board is still alive */
16764+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
16765+ SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP,
16766+ 0, -1, SK_FALSE);
16767+ SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP,
16768+ 1, -1, SK_TRUE);
16769+
16770+ /* disable interrupts */
16771+ SK_OUT32(pAC->IoBase, B0_IMSK, 0);
16772+ SkGeDeInit(pAC, pAC->IoBase);
16773+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
16774+ pAC->BoardLevel = SK_INIT_DATA;
16775+ /* We do NOT check here, if IRQ was pending, of course*/
16776+ }
16777+
16778+ if(pAC->BoardLevel == SK_INIT_IO) {
16779+ /* board is still alive */
16780+ SkGeDeInit(pAC, pAC->IoBase);
16781+ pAC->BoardLevel = SK_INIT_DATA;
16782+ }
16783+
16784+ if ((pAC->GIni.GIMacsFound == 2) && pAC->RlmtNets == 2){
16785+ unregister_netdev(pAC->dev[1]);
16786+ free_netdev(pAC->dev[1]);
16787+ }
16788+
16789+ FreeResources(dev);
16790+
16791+#ifdef CONFIG_PROC_FS
16792+ /* Remove the sk98lin procfs device entries */
16793+ if ((pAC->GIni.GIMacsFound == 2) && pAC->RlmtNets == 2){
16794+ remove_proc_entry(pAC->dev[1]->name, pSkRootDir);
16795+ }
16796+ remove_proc_entry(pNet->InitialDevName, pSkRootDir);
16797+#endif
16798+
16799+ dev->get_stats = NULL;
16800+ /*
16801+ * otherwise unregister_netdev calls get_stats with
16802+ * invalid IO ... :-(
16803+ */
16804+ unregister_netdev(dev);
16805+ free_netdev(dev);
16806+ kfree(pAC);
16807+ sk98lin_max_boards_found--;
16808+
16809+#ifdef CONFIG_PROC_FS
16810+ /* Remove all Proc entries if last device */
16811+ if (sk98lin_max_boards_found == 0) {
16812+ /* clear proc-dir */
16813+ remove_proc_entry(pSkRootDir->name, proc_net);
16814+ }
16815 #endif
16816
16817-static int IntsPerSec[SK_MAX_CARD_PARAM];
16818-static char *Moderation[SK_MAX_CARD_PARAM];
16819-static char *ModerationMask[SK_MAX_CARD_PARAM];
16820-static char *AutoSizing[SK_MAX_CARD_PARAM];
16821-static char *Stats[SK_MAX_CARD_PARAM];
16822+}
16823
16824-module_param_array(Speed_A, charp, NULL, 0);
16825-module_param_array(Speed_B, charp, NULL, 0);
16826-module_param_array(AutoNeg_A, charp, NULL, 0);
16827-module_param_array(AutoNeg_B, charp, NULL, 0);
16828-module_param_array(DupCap_A, charp, NULL, 0);
16829-module_param_array(DupCap_B, charp, NULL, 0);
16830-module_param_array(FlowCtrl_A, charp, NULL, 0);
16831-module_param_array(FlowCtrl_B, charp, NULL, 0);
16832-module_param_array(Role_A, charp, NULL, 0);
16833-module_param_array(Role_B, charp, NULL, 0);
16834-module_param_array(ConType, charp, NULL, 0);
16835-module_param_array(PrefPort, charp, NULL, 0);
16836-module_param_array(RlmtMode, charp, NULL, 0);
16837-/* used for interrupt moderation */
16838-module_param_array(IntsPerSec, int, NULL, 0);
16839-module_param_array(Moderation, charp, NULL, 0);
16840-module_param_array(Stats, charp, NULL, 0);
16841-module_param_array(ModerationMask, charp, NULL, 0);
16842-module_param_array(AutoSizing, charp, NULL, 0);
16843
16844 /*****************************************************************************
16845 *
16846@@ -486,7 +1422,7 @@
16847 * 0, if everything is ok
16848 * !=0, on error
16849 */
16850-static int __devinit SkGeBoardInit(struct SK_NET_DEVICE *dev, SK_AC *pAC)
16851+static int __init SkGeBoardInit(struct SK_NET_DEVICE *dev, SK_AC *pAC)
16852 {
16853 short i;
16854 unsigned long Flags;
16855@@ -509,12 +1445,11 @@
16856 spin_lock_init(&pAC->TxPort[i][0].TxDesRingLock);
16857 spin_lock_init(&pAC->RxPort[i].RxDesRingLock);
16858 }
16859- spin_lock_init(&pAC->SlowPathLock);
16860
16861- /* setup phy_id blink timer */
16862- pAC->BlinkTimer.function = SkGeBlinkTimer;
16863- pAC->BlinkTimer.data = (unsigned long) dev;
16864- init_timer(&pAC->BlinkTimer);
16865+ spin_lock_init(&pAC->InitLock); /* Init lock */
16866+ spin_lock_init(&pAC->SlowPathLock);
16867+ spin_lock_init(&pAC->TxQueueLock); /* for Yukon2 chipsets */
16868+ spin_lock_init(&pAC->SetPutIndexLock); /* for Yukon2 chipsets */
16869
16870 /* level 0 init common modules here */
16871
16872@@ -523,7 +1458,7 @@
16873 if (SkGeInit(pAC, pAC->IoBase, SK_INIT_DATA) != 0) {
16874 printk("HWInit (0) failed.\n");
16875 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
16876- return -EIO;
16877+ return(-EAGAIN);
16878 }
16879 SkI2cInit( pAC, pAC->IoBase, SK_INIT_DATA);
16880 SkEventInit(pAC, pAC->IoBase, SK_INIT_DATA);
16881@@ -533,19 +1468,17 @@
16882 SkTimerInit(pAC, pAC->IoBase, SK_INIT_DATA);
16883
16884 pAC->BoardLevel = SK_INIT_DATA;
16885- pAC->RxBufSize = ETH_BUF_SIZE;
16886+ pAC->RxPort[0].RxBufSize = ETH_BUF_SIZE;
16887+ pAC->RxPort[1].RxBufSize = ETH_BUF_SIZE;
16888
16889 SK_PNMI_SET_DRIVER_DESCR(pAC, DescrString);
16890 SK_PNMI_SET_DRIVER_VER(pAC, VerStr);
16891
16892- spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
16893-
16894 /* level 1 init common modules here (HW init) */
16895- spin_lock_irqsave(&pAC->SlowPathLock, Flags);
16896 if (SkGeInit(pAC, pAC->IoBase, SK_INIT_IO) != 0) {
16897 printk("sk98lin: HWInit (1) failed.\n");
16898 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
16899- return -EIO;
16900+ return(-EAGAIN);
16901 }
16902 SkI2cInit( pAC, pAC->IoBase, SK_INIT_IO);
16903 SkEventInit(pAC, pAC->IoBase, SK_INIT_IO);
16904@@ -553,46 +1486,93 @@
16905 SkAddrInit( pAC, pAC->IoBase, SK_INIT_IO);
16906 SkRlmtInit( pAC, pAC->IoBase, SK_INIT_IO);
16907 SkTimerInit(pAC, pAC->IoBase, SK_INIT_IO);
16908+#ifdef Y2_RECOVERY
16909+ /* mark entries invalid */
16910+ pAC->LastPort = 3;
16911+ pAC->LastOpc = 0xFF;
16912+#endif
16913
16914 /* Set chipset type support */
16915- pAC->ChipsetType = 0;
16916 if ((pAC->GIni.GIChipId == CHIP_ID_YUKON) ||
16917- (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE)) {
16918- pAC->ChipsetType = 1;
16919+ (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) ||
16920+ (pAC->GIni.GIChipId == CHIP_ID_YUKON_LP)) {
16921+ pAC->ChipsetType = 1; /* Yukon chipset (descriptor logic) */
16922+ } else if (CHIP_ID_YUKON_2(pAC)) {
16923+ pAC->ChipsetType = 2; /* Yukon2 chipset (list logic) */
16924+ } else {
16925+ pAC->ChipsetType = 0; /* Genesis chipset (descriptor logic) */
16926+ }
16927+
16928+ /* wake on lan support */
16929+ pAC->WolInfo.SupportedWolOptions = 0;
16930+#if defined (ETHTOOL_GWOL) && defined (ETHTOOL_SWOL)
16931+ if (pAC->GIni.GIChipId != CHIP_ID_GENESIS) {
16932+ pAC->WolInfo.SupportedWolOptions = WAKE_MAGIC;
16933+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {
16934+ if (pAC->GIni.GIChipRev == 0) {
16935+ pAC->WolInfo.SupportedWolOptions = 0;
16936+ }
16937+ }
16938 }
16939+#endif
16940+ pAC->WolInfo.ConfiguredWolOptions = pAC->WolInfo.SupportedWolOptions;
16941
16942 GetConfiguration(pAC);
16943 if (pAC->RlmtNets == 2) {
16944- pAC->GIni.GIPortUsage = SK_MUL_LINK;
16945+ pAC->GIni.GP[0].PPortUsage = SK_MUL_LINK;
16946+ pAC->GIni.GP[1].PPortUsage = SK_MUL_LINK;
16947 }
16948
16949 pAC->BoardLevel = SK_INIT_IO;
16950 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
16951
16952- if (pAC->GIni.GIMacsFound == 2) {
16953- Ret = request_irq(dev->irq, SkGeIsr, SA_SHIRQ, "sk98lin", dev);
16954- } else if (pAC->GIni.GIMacsFound == 1) {
16955- Ret = request_irq(dev->irq, SkGeIsrOnePort, SA_SHIRQ,
16956- "sk98lin", dev);
16957- } else {
16958- printk(KERN_WARNING "sk98lin: Illegal number of ports: %d\n",
16959- pAC->GIni.GIMacsFound);
16960- return -EIO;
16961+ if (!CHIP_ID_YUKON_2(pAC)) {
16962+ if (pAC->GIni.GIMacsFound == 2) {
16963+ Ret = request_irq(dev->irq, SkGeIsr, SA_SHIRQ, dev->name, dev);
16964+ } else if (pAC->GIni.GIMacsFound == 1) {
16965+ Ret = request_irq(dev->irq, SkGeIsrOnePort, SA_SHIRQ, dev->name, dev);
16966+ } else {
16967+ printk(KERN_WARNING "sk98lin: Illegal number of ports: %d\n",
16968+ pAC->GIni.GIMacsFound);
16969+ return -EAGAIN;
16970+ }
16971+ }
16972+ else {
16973+ Ret = request_irq(dev->irq, SkY2Isr, SA_SHIRQ, dev->name, dev);
16974 }
16975
16976 if (Ret) {
16977 printk(KERN_WARNING "sk98lin: Requested IRQ %d is busy.\n",
16978- dev->irq);
16979- return Ret;
16980+ dev->irq);
16981+ return -EAGAIN;
16982 }
16983 pAC->AllocFlag |= SK_ALLOC_IRQ;
16984
16985- /* Alloc memory for this board (Mem for RxD/TxD) : */
16986- if(!BoardAllocMem(pAC)) {
16987- printk("No memory for descriptor rings.\n");
16988- return -ENOMEM;
16989+ /*
16990+ ** Alloc descriptor/LETable memory for this board (both RxD/TxD)
16991+ */
16992+ if (CHIP_ID_YUKON_2(pAC)) {
16993+ if (!SkY2AllocateResources(pAC)) {
16994+ printk("No memory for Yukon2 settings\n");
16995+ return(-EAGAIN);
16996+ }
16997+ } else {
16998+ if(!BoardAllocMem(pAC)) {
16999+ printk("No memory for descriptor rings.\n");
17000+ return(-EAGAIN);
17001+ }
17002 }
17003
17004+#ifdef SK_USE_CSUM
17005+ SkCsSetReceiveFlags(pAC,
17006+ SKCS_PROTO_IP | SKCS_PROTO_TCP | SKCS_PROTO_UDP,
17007+ &pAC->CsOfs1, &pAC->CsOfs2, 0);
17008+ pAC->CsOfs = (pAC->CsOfs2 << 16) | pAC->CsOfs1;
17009+#endif
17010+
17011+ /*
17012+ ** Function BoardInitMem() for Yukon dependent settings...
17013+ */
17014 BoardInitMem(pAC);
17015 /* tschilling: New common function with minimum size check. */
17016 DualNet = SK_FALSE;
17017@@ -604,11 +1584,22 @@
17018 pAC,
17019 pAC->ActivePort,
17020 DualNet)) {
17021- BoardFreeMem(pAC);
17022+ if (CHIP_ID_YUKON_2(pAC)) {
17023+ SkY2FreeResources(pAC);
17024+ } else {
17025+ BoardFreeMem(pAC);
17026+ }
17027+
17028 printk("sk98lin: SkGeInitAssignRamToQueues failed.\n");
17029- return -EIO;
17030+ return(-EAGAIN);
17031 }
17032
17033+ /*
17034+ * Register the device here
17035+ */
17036+ pAC->Next = SkGeRootDev;
17037+ SkGeRootDev = dev;
17038+
17039 return (0);
17040 } /* SkGeBoardInit */
17041
17042@@ -627,7 +1618,8 @@
17043 * SK_TRUE, if all memory could be allocated
17044 * SK_FALSE, if not
17045 */
17046-static __devinit SK_BOOL BoardAllocMem(SK_AC *pAC)
17047+static SK_BOOL BoardAllocMem(
17048+SK_AC *pAC)
17049 {
17050 caddr_t pDescrMem; /* pointer to descriptor memory area */
17051 size_t AllocLength; /* length of complete descriptor area */
17052@@ -697,16 +1689,20 @@
17053
17054 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
17055 ("BoardFreeMem\n"));
17056+
17057+ if (pAC->pDescrMem) {
17058+
17059 #if (BITS_PER_LONG == 32)
17060- AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound + 8;
17061+ AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound + 8;
17062 #else
17063- AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound
17064- + RX_RING_SIZE + 8;
17065+ AllocLength = (RX_RING_SIZE + TX_RING_SIZE) * pAC->GIni.GIMacsFound
17066+ + RX_RING_SIZE + 8;
17067 #endif
17068
17069- pci_free_consistent(pAC->PciDev, AllocLength,
17070+ pci_free_consistent(pAC->PciDev, AllocLength,
17071 pAC->pDescrMem, pAC->pDescrMemDMA);
17072- pAC->pDescrMem = NULL;
17073+ pAC->pDescrMem = NULL;
17074+ }
17075 } /* BoardFreeMem */
17076
17077
17078@@ -715,12 +1711,13 @@
17079 * BoardInitMem - initiate the descriptor rings
17080 *
17081 * Description:
17082- * This function sets the descriptor rings up in memory.
17083+ * This function sets the descriptor rings or LETables up in memory.
17084 * The adapter is initialized with the descriptor start addresses.
17085 *
17086 * Returns: N/A
17087 */
17088-static __devinit void BoardInitMem(SK_AC *pAC)
17089+static void BoardInitMem(
17090+SK_AC *pAC) /* pointer to adapter context */
17091 {
17092 int i; /* loop counter */
17093 int RxDescrSize; /* the size of a rx descriptor rounded up to alignment*/
17094@@ -729,34 +1726,37 @@
17095 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
17096 ("BoardInitMem\n"));
17097
17098- RxDescrSize = (((sizeof(RXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN;
17099- pAC->RxDescrPerRing = RX_RING_SIZE / RxDescrSize;
17100- TxDescrSize = (((sizeof(TXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN;
17101- pAC->TxDescrPerRing = TX_RING_SIZE / RxDescrSize;
17102+ if (!pAC->GIni.GIYukon2) {
17103+ RxDescrSize = (((sizeof(RXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN;
17104+ pAC->RxDescrPerRing = RX_RING_SIZE / RxDescrSize;
17105+ TxDescrSize = (((sizeof(TXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN;
17106+ pAC->TxDescrPerRing = TX_RING_SIZE / RxDescrSize;
17107
17108- for (i=0; i<pAC->GIni.GIMacsFound; i++) {
17109- SetupRing(
17110- pAC,
17111- pAC->TxPort[i][0].pTxDescrRing,
17112- pAC->TxPort[i][0].VTxDescrRing,
17113- (RXD**)&pAC->TxPort[i][0].pTxdRingHead,
17114- (RXD**)&pAC->TxPort[i][0].pTxdRingTail,
17115- (RXD**)&pAC->TxPort[i][0].pTxdRingPrev,
17116- &pAC->TxPort[i][0].TxdRingFree,
17117- SK_TRUE);
17118- SetupRing(
17119- pAC,
17120- pAC->RxPort[i].pRxDescrRing,
17121- pAC->RxPort[i].VRxDescrRing,
17122- &pAC->RxPort[i].pRxdRingHead,
17123- &pAC->RxPort[i].pRxdRingTail,
17124- &pAC->RxPort[i].pRxdRingPrev,
17125- &pAC->RxPort[i].RxdRingFree,
17126- SK_FALSE);
17127+ for (i=0; i<pAC->GIni.GIMacsFound; i++) {
17128+ SetupRing(
17129+ pAC,
17130+ pAC->TxPort[i][0].pTxDescrRing,
17131+ pAC->TxPort[i][0].VTxDescrRing,
17132+ (RXD**)&pAC->TxPort[i][0].pTxdRingHead,
17133+ (RXD**)&pAC->TxPort[i][0].pTxdRingTail,
17134+ (RXD**)&pAC->TxPort[i][0].pTxdRingPrev,
17135+ &pAC->TxPort[i][0].TxdRingFree,
17136+ &pAC->TxPort[i][0].TxdRingPrevFree,
17137+ SK_TRUE);
17138+ SetupRing(
17139+ pAC,
17140+ pAC->RxPort[i].pRxDescrRing,
17141+ pAC->RxPort[i].VRxDescrRing,
17142+ &pAC->RxPort[i].pRxdRingHead,
17143+ &pAC->RxPort[i].pRxdRingTail,
17144+ &pAC->RxPort[i].pRxdRingPrev,
17145+ &pAC->RxPort[i].RxdRingFree,
17146+ &pAC->RxPort[i].RxdRingFree,
17147+ SK_FALSE);
17148+ }
17149 }
17150 } /* BoardInitMem */
17151
17152-
17153 /*****************************************************************************
17154 *
17155 * SetupRing - create one descriptor ring
17156@@ -776,6 +1776,7 @@
17157 RXD **ppRingTail, /* address where the tail should be written */
17158 RXD **ppRingPrev, /* address where the tail should be written */
17159 int *pRingFree, /* address where the # of free descr. goes */
17160+int *pRingPrevFree, /* address where the # of free descr. goes */
17161 SK_BOOL IsTx) /* flag: is this a tx ring */
17162 {
17163 int i; /* loop counter */
17164@@ -808,7 +1809,7 @@
17165 /* set the pointers right */
17166 pDescr->VNextRxd = VNextDescr & 0xffffffffULL;
17167 pDescr->pNextRxd = pNextDescr;
17168- if (!IsTx) pDescr->TcpSumStarts = ETH_HLEN << 16 | ETH_HLEN;
17169+ pDescr->TcpSumStarts = pAC->CsOfs;
17170
17171 /* advance one step */
17172 pPrevDescr = pDescr;
17173@@ -818,11 +1819,12 @@
17174 }
17175 pPrevDescr->pNextRxd = (RXD*) pMemArea;
17176 pPrevDescr->VNextRxd = VMemArea;
17177- pDescr = (RXD*) pMemArea;
17178- *ppRingHead = (RXD*) pMemArea;
17179- *ppRingTail = *ppRingHead;
17180- *ppRingPrev = pPrevDescr;
17181- *pRingFree = DescrNum;
17182+ pDescr = (RXD*) pMemArea;
17183+ *ppRingHead = (RXD*) pMemArea;
17184+ *ppRingTail = *ppRingHead;
17185+ *ppRingPrev = pPrevDescr;
17186+ *pRingFree = DescrNum;
17187+ *pRingPrevFree = DescrNum;
17188 } /* SetupRing */
17189
17190
17191@@ -887,17 +1889,35 @@
17192 SK_AC *pAC;
17193 SK_U32 IntSrc; /* interrupts source register contents */
17194
17195- pNet = netdev_priv(dev);
17196+ pNet = (DEV_NET*) dev->priv;
17197 pAC = pNet->pAC;
17198
17199 /*
17200 * Check and process if its our interrupt
17201 */
17202 SK_IN32(pAC->IoBase, B0_SP_ISRC, &IntSrc);
17203- if (IntSrc == 0) {
17204+ if ((IntSrc == 0) && (!pNet->NetConsoleMode)) {
17205 return SkIsrRetNone;
17206 }
17207
17208+#ifdef CONFIG_SK98LIN_NAPI
17209+ if (netif_rx_schedule_prep(dev)) {
17210+ pAC->GIni.GIValIrqMask &= ~(NAPI_DRV_IRQS);
17211+ SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
17212+ __netif_rx_schedule(dev);
17213+ }
17214+
17215+#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
17216+ if (IntSrc & IS_XA1_F) {
17217+ CLEAR_TX_IRQ(0, TX_PRIO_LOW);
17218+ }
17219+ if (IntSrc & IS_XA2_F) {
17220+ CLEAR_TX_IRQ(1, TX_PRIO_LOW);
17221+ }
17222+#endif
17223+
17224+
17225+#else
17226 while (((IntSrc & IRQ_MASK) & ~SPECIAL_IRQS) != 0) {
17227 #if 0 /* software irq currently not used */
17228 if (IntSrc & IS_IRQ_SW) {
17229@@ -911,6 +1931,7 @@
17230 SK_DBGCAT_DRV_INT_SRC,
17231 ("EOF RX1 IRQ\n"));
17232 ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE);
17233+ CLEAR_AND_START_RX(0);
17234 SK_PNMI_CNT_RX_INTR(pAC, 0);
17235 }
17236 if (IntSrc & IS_R2_F) {
17237@@ -918,6 +1939,7 @@
17238 SK_DBGCAT_DRV_INT_SRC,
17239 ("EOF RX2 IRQ\n"));
17240 ReceiveIrq(pAC, &pAC->RxPort[1], SK_TRUE);
17241+ CLEAR_AND_START_RX(1);
17242 SK_PNMI_CNT_RX_INTR(pAC, 1);
17243 }
17244 #ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
17245@@ -925,6 +1947,7 @@
17246 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
17247 SK_DBGCAT_DRV_INT_SRC,
17248 ("EOF AS TX1 IRQ\n"));
17249+ CLEAR_TX_IRQ(0, TX_PRIO_LOW);
17250 SK_PNMI_CNT_TX_INTR(pAC, 0);
17251 spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
17252 FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]);
17253@@ -934,6 +1957,7 @@
17254 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
17255 SK_DBGCAT_DRV_INT_SRC,
17256 ("EOF AS TX2 IRQ\n"));
17257+ CLEAR_TX_IRQ(1, TX_PRIO_LOW);
17258 SK_PNMI_CNT_TX_INTR(pAC, 1);
17259 spin_lock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock);
17260 FreeTxDescriptors(pAC, &pAC->TxPort[1][TX_PRIO_LOW]);
17261@@ -944,38 +1968,28 @@
17262 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
17263 SK_DBGCAT_DRV_INT_SRC,
17264 ("EOF SY TX1 IRQ\n"));
17265+ CLEAR_TX_IRQ(0, TX_PRIO_HIGH);
17266 SK_PNMI_CNT_TX_INTR(pAC, 1);
17267 spin_lock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock);
17268 FreeTxDescriptors(pAC, 0, TX_PRIO_HIGH);
17269 spin_unlock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock);
17270- ClearTxIrq(pAC, 0, TX_PRIO_HIGH);
17271 }
17272 if (IntSrc & IS_XS2_F) {
17273 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
17274 SK_DBGCAT_DRV_INT_SRC,
17275 ("EOF SY TX2 IRQ\n"));
17276+ CLEAR_TX_IRQ(1, TX_PRIO_HIGH);
17277 SK_PNMI_CNT_TX_INTR(pAC, 1);
17278 spin_lock(&pAC->TxPort[1][TX_PRIO_HIGH].TxDesRingLock);
17279 FreeTxDescriptors(pAC, 1, TX_PRIO_HIGH);
17280 spin_unlock(&pAC->TxPort[1][TX_PRIO_HIGH].TxDesRingLock);
17281- ClearTxIrq(pAC, 1, TX_PRIO_HIGH);
17282 }
17283 #endif
17284 #endif
17285
17286- /* do all IO at once */
17287- if (IntSrc & IS_R1_F)
17288- ClearAndStartRx(pAC, 0);
17289- if (IntSrc & IS_R2_F)
17290- ClearAndStartRx(pAC, 1);
17291-#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
17292- if (IntSrc & IS_XA1_F)
17293- ClearTxIrq(pAC, 0, TX_PRIO_LOW);
17294- if (IntSrc & IS_XA2_F)
17295- ClearTxIrq(pAC, 1, TX_PRIO_LOW);
17296-#endif
17297 SK_IN32(pAC->IoBase, B0_ISRC, &IntSrc);
17298 } /* while (IntSrc & IRQ_MASK != 0) */
17299+#endif
17300
17301 IntSrc &= pAC->GIni.GIValIrqMask;
17302 if ((IntSrc & SPECIAL_IRQS) || pAC->CheckQueue) {
17303@@ -989,18 +2003,12 @@
17304 SkEventDispatcher(pAC, pAC->IoBase);
17305 spin_unlock(&pAC->SlowPathLock);
17306 }
17307- /*
17308- * do it all again is case we cleared an interrupt that
17309- * came in after handling the ring (OUTs may be delayed
17310- * in hardware buffers, but are through after IN)
17311- *
17312- * rroesler: has been commented out and shifted to
17313- * SkGeDrvEvent(), because it is timer
17314- * guarded now
17315- *
17316+
17317+#ifndef CONFIG_SK98LIN_NAPI
17318+ /* Handle interrupts */
17319 ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE);
17320 ReceiveIrq(pAC, &pAC->RxPort[1], SK_TRUE);
17321- */
17322+#endif
17323
17324 if (pAC->CheckQueue) {
17325 pAC->CheckQueue = SK_FALSE;
17326@@ -1036,17 +2044,32 @@
17327 SK_AC *pAC;
17328 SK_U32 IntSrc; /* interrupts source register contents */
17329
17330- pNet = netdev_priv(dev);
17331+ pNet = (DEV_NET*) dev->priv;
17332 pAC = pNet->pAC;
17333
17334 /*
17335 * Check and process if its our interrupt
17336 */
17337 SK_IN32(pAC->IoBase, B0_SP_ISRC, &IntSrc);
17338- if (IntSrc == 0) {
17339+ if ((IntSrc == 0) && (!pNet->NetConsoleMode)) {
17340 return SkIsrRetNone;
17341 }
17342
17343+#ifdef CONFIG_SK98LIN_NAPI
17344+ if (netif_rx_schedule_prep(dev)) {
17345+ CLEAR_AND_START_RX(0);
17346+ CLEAR_TX_IRQ(0, TX_PRIO_LOW);
17347+ pAC->GIni.GIValIrqMask &= ~(NAPI_DRV_IRQS);
17348+ SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
17349+ __netif_rx_schedule(dev);
17350+ }
17351+
17352+#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
17353+ if (IntSrc & IS_XA1_F) {
17354+ CLEAR_TX_IRQ(0, TX_PRIO_LOW);
17355+ }
17356+#endif
17357+#else
17358 while (((IntSrc & IRQ_MASK) & ~SPECIAL_IRQS) != 0) {
17359 #if 0 /* software irq currently not used */
17360 if (IntSrc & IS_IRQ_SW) {
17361@@ -1060,6 +2083,7 @@
17362 SK_DBGCAT_DRV_INT_SRC,
17363 ("EOF RX1 IRQ\n"));
17364 ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE);
17365+ CLEAR_AND_START_RX(0);
17366 SK_PNMI_CNT_RX_INTR(pAC, 0);
17367 }
17368 #ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
17369@@ -1067,6 +2091,7 @@
17370 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
17371 SK_DBGCAT_DRV_INT_SRC,
17372 ("EOF AS TX1 IRQ\n"));
17373+ CLEAR_TX_IRQ(0, TX_PRIO_LOW);
17374 SK_PNMI_CNT_TX_INTR(pAC, 0);
17375 spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
17376 FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]);
17377@@ -1077,24 +2102,18 @@
17378 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
17379 SK_DBGCAT_DRV_INT_SRC,
17380 ("EOF SY TX1 IRQ\n"));
17381+ CLEAR_TX_IRQ(0, TX_PRIO_HIGH);
17382 SK_PNMI_CNT_TX_INTR(pAC, 0);
17383 spin_lock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock);
17384 FreeTxDescriptors(pAC, 0, TX_PRIO_HIGH);
17385 spin_unlock(&pAC->TxPort[0][TX_PRIO_HIGH].TxDesRingLock);
17386- ClearTxIrq(pAC, 0, TX_PRIO_HIGH);
17387 }
17388 #endif
17389 #endif
17390
17391- /* do all IO at once */
17392- if (IntSrc & IS_R1_F)
17393- ClearAndStartRx(pAC, 0);
17394-#ifdef USE_TX_COMPLETE /* only if tx complete interrupt used */
17395- if (IntSrc & IS_XA1_F)
17396- ClearTxIrq(pAC, 0, TX_PRIO_LOW);
17397-#endif
17398 SK_IN32(pAC->IoBase, B0_ISRC, &IntSrc);
17399 } /* while (IntSrc & IRQ_MASK != 0) */
17400+#endif
17401
17402 IntSrc &= pAC->GIni.GIValIrqMask;
17403 if ((IntSrc & SPECIAL_IRQS) || pAC->CheckQueue) {
17404@@ -1108,17 +2127,10 @@
17405 SkEventDispatcher(pAC, pAC->IoBase);
17406 spin_unlock(&pAC->SlowPathLock);
17407 }
17408- /*
17409- * do it all again is case we cleared an interrupt that
17410- * came in after handling the ring (OUTs may be delayed
17411- * in hardware buffers, but are through after IN)
17412- *
17413- * rroesler: has been commented out and shifted to
17414- * SkGeDrvEvent(), because it is timer
17415- * guarded now
17416- *
17417+
17418+#ifndef CONFIG_SK98LIN_NAPI
17419 ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE);
17420- */
17421+#endif
17422
17423 /* IRQ is processed - Enable IRQs again*/
17424 SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
17425@@ -1126,25 +2138,6 @@
17426 return SkIsrRetHandled;
17427 } /* SkGeIsrOnePort */
17428
17429-#ifdef CONFIG_NET_POLL_CONTROLLER
17430-/****************************************************************************
17431- *
17432- * SkGePollController - polling receive, for netconsole
17433- *
17434- * Description:
17435- * Polling receive - used by netconsole and other diagnostic tools
17436- * to allow network i/o with interrupts disabled.
17437- *
17438- * Returns: N/A
17439- */
17440-static void SkGePollController(struct net_device *dev)
17441-{
17442- disable_irq(dev->irq);
17443- SkGeIsr(dev->irq, dev, NULL);
17444- enable_irq(dev->irq);
17445-}
17446-#endif
17447-
17448 /****************************************************************************
17449 *
17450 * SkGeOpen - handle start of initialized adapter
17451@@ -1162,27 +2155,27 @@
17452 * != 0 on error
17453 */
17454 static int SkGeOpen(
17455-struct SK_NET_DEVICE *dev)
17456+struct SK_NET_DEVICE *dev) /* the device that is to be opened */
17457 {
17458- DEV_NET *pNet;
17459- SK_AC *pAC;
17460- unsigned long Flags; /* for spin lock */
17461- int i;
17462- SK_EVPARA EvPara; /* an event parameter union */
17463+ DEV_NET *pNet = (DEV_NET*) dev->priv;
17464+ SK_AC *pAC = pNet->pAC;
17465+ unsigned long Flags; /* for the spin locks */
17466+ unsigned long InitFlags; /* for the spin locks */
17467+ int CurrMac; /* loop ctr for ports */
17468
17469- pNet = netdev_priv(dev);
17470- pAC = pNet->pAC;
17471-
17472 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
17473 ("SkGeOpen: pAC=0x%lX:\n", (unsigned long)pAC));
17474+ spin_lock_irqsave(&pAC->InitLock, InitFlags);
17475
17476-#ifdef SK_DIAG_SUPPORT
17477 if (pAC->DiagModeActive == DIAG_ACTIVE) {
17478 if (pAC->Pnmi.DiagAttached == SK_DIAG_RUNNING) {
17479 return (-1); /* still in use by diag; deny actions */
17480 }
17481 }
17482-#endif
17483+
17484+ if (!try_module_get(THIS_MODULE)) {
17485+ return (-1); /* increase of usage count not possible */
17486+ }
17487
17488 /* Set blink mode */
17489 if ((pAC->PciDev->vendor == 0x1186) || (pAC->PciDev->vendor == 0x11ab ))
17490@@ -1191,6 +2184,7 @@
17491 if (pAC->BoardLevel == SK_INIT_DATA) {
17492 /* level 1 init common modules here */
17493 if (SkGeInit(pAC, pAC->IoBase, SK_INIT_IO) != 0) {
17494+ module_put(THIS_MODULE); /* decrease usage count */
17495 printk("%s: HWInit (1) failed.\n", pAC->dev[pNet->PortNr]->name);
17496 return (-1);
17497 }
17498@@ -1201,11 +2195,17 @@
17499 SkRlmtInit (pAC, pAC->IoBase, SK_INIT_IO);
17500 SkTimerInit (pAC, pAC->IoBase, SK_INIT_IO);
17501 pAC->BoardLevel = SK_INIT_IO;
17502+#ifdef Y2_RECOVERY
17503+ /* mark entries invalid */
17504+ pAC->LastPort = 3;
17505+ pAC->LastOpc = 0xFF;
17506+#endif
17507 }
17508
17509 if (pAC->BoardLevel != SK_INIT_RUN) {
17510 /* tschilling: Level 2 init modules here, check return value. */
17511 if (SkGeInit(pAC, pAC->IoBase, SK_INIT_RUN) != 0) {
17512+ module_put(THIS_MODULE); /* decrease usage count */
17513 printk("%s: HWInit (2) failed.\n", pAC->dev[pNet->PortNr]->name);
17514 return (-1);
17515 }
17516@@ -1218,44 +2218,62 @@
17517 pAC->BoardLevel = SK_INIT_RUN;
17518 }
17519
17520- for (i=0; i<pAC->GIni.GIMacsFound; i++) {
17521- /* Enable transmit descriptor polling. */
17522- SkGePollTxD(pAC, pAC->IoBase, i, SK_TRUE);
17523- FillRxRing(pAC, &pAC->RxPort[i]);
17524+ for (CurrMac=0; CurrMac<pAC->GIni.GIMacsFound; CurrMac++) {
17525+ if (!CHIP_ID_YUKON_2(pAC)) {
17526+ /* Enable transmit descriptor polling. */
17527+ SkGePollTxD(pAC, pAC->IoBase, CurrMac, SK_TRUE);
17528+ FillRxRing(pAC, &pAC->RxPort[CurrMac]);
17529+ SkMacRxTxEnable(pAC, pAC->IoBase, pNet->PortNr);
17530+ }
17531 }
17532- SkGeYellowLED(pAC, pAC->IoBase, 1);
17533
17534- StartDrvCleanupTimer(pAC);
17535+ SkGeYellowLED(pAC, pAC->IoBase, 1);
17536 SkDimEnableModerationIfNeeded(pAC);
17537- SkDimDisplayModerationSettings(pAC);
17538
17539- pAC->GIni.GIValIrqMask &= IRQ_MASK;
17540-
17541- /* enable Interrupts */
17542- SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
17543- SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK);
17544+ if (!CHIP_ID_YUKON_2(pAC)) {
17545+ /*
17546+ ** Has been setup already at SkGeInit(SK_INIT_IO),
17547+ ** but additional masking added for Genesis & Yukon
17548+ ** chipsets -> modify it...
17549+ */
17550+ pAC->GIni.GIValIrqMask &= IRQ_MASK;
17551+#ifndef USE_TX_COMPLETE
17552+ pAC->GIni.GIValIrqMask &= ~(TX_COMPL_IRQS);
17553+#endif
17554+ }
17555
17556 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
17557
17558 if ((pAC->RlmtMode != 0) && (pAC->MaxPorts == 0)) {
17559- EvPara.Para32[0] = pAC->RlmtNets;
17560- EvPara.Para32[1] = -1;
17561- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_SET_NETS,
17562- EvPara);
17563- EvPara.Para32[0] = pAC->RlmtMode;
17564- EvPara.Para32[1] = 0;
17565- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_MODE_CHANGE,
17566- EvPara);
17567+ SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_SET_NETS,
17568+ pAC->RlmtNets, -1, SK_FALSE);
17569+ SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_MODE_CHANGE,
17570+ pAC->RlmtMode, 0, SK_FALSE);
17571 }
17572
17573- EvPara.Para32[0] = pNet->NetNr;
17574- EvPara.Para32[1] = -1;
17575- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara);
17576- SkEventDispatcher(pAC, pAC->IoBase);
17577+ SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_START,
17578+ pNet->NetNr, -1, SK_TRUE);
17579 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
17580
17581- pAC->MaxPorts++;
17582+#ifdef Y2_RECOVERY
17583+ pNet->TimerExpired = SK_FALSE;
17584+ pNet->InRecover = SK_FALSE;
17585+ pNet->NetConsoleMode = SK_FALSE;
17586+
17587+ /* Initialize the kernel timer */
17588+ init_timer(&pNet->KernelTimer);
17589+ pNet->KernelTimer.function = SkGeHandleKernelTimer;
17590+ pNet->KernelTimer.data = (unsigned long) pNet;
17591+ pNet->KernelTimer.expires = jiffies + (HZ/4); /* initially 250ms */
17592+ add_timer(&pNet->KernelTimer);
17593+#endif
17594+
17595+ /* enable Interrupts */
17596+ SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
17597+ SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK);
17598
17599+ pAC->MaxPorts++;
17600+ spin_unlock_irqrestore(&pAC->InitLock, InitFlags);
17601
17602 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
17603 ("SkGeOpen suceeded\n"));
17604@@ -1276,32 +2294,37 @@
17605 * error code - on error
17606 */
17607 static int SkGeClose(
17608-struct SK_NET_DEVICE *dev)
17609+struct SK_NET_DEVICE *dev) /* the device that is to be closed */
17610 {
17611- DEV_NET *pNet;
17612- DEV_NET *newPtrNet;
17613- SK_AC *pAC;
17614-
17615- unsigned long Flags; /* for spin lock */
17616- int i;
17617- int PortIdx;
17618- SK_EVPARA EvPara;
17619-
17620+ DEV_NET *pNet = (DEV_NET*) dev->priv;
17621+ SK_AC *pAC = pNet->pAC;
17622+ DEV_NET *newPtrNet;
17623+ unsigned long Flags; /* for the spin locks */
17624+ unsigned long InitFlags; /* for the spin locks */
17625+ int CurrMac; /* loop ctr for the current MAC */
17626+ int PortIdx;
17627+#ifdef CONFIG_SK98LIN_NAPI
17628+ int WorkToDo = 1; /* min(*budget, dev->quota); */
17629+ int WorkDone = 0;
17630+#endif
17631 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
17632 ("SkGeClose: pAC=0x%lX ", (unsigned long)pAC));
17633+ spin_lock_irqsave(&pAC->InitLock, InitFlags);
17634
17635- pNet = netdev_priv(dev);
17636- pAC = pNet->pAC;
17637+#ifdef Y2_RECOVERY
17638+ pNet->InRecover = SK_TRUE;
17639+ del_timer(&pNet->KernelTimer);
17640+#endif
17641
17642-#ifdef SK_DIAG_SUPPORT
17643 if (pAC->DiagModeActive == DIAG_ACTIVE) {
17644 if (pAC->DiagFlowCtrl == SK_FALSE) {
17645+ module_put(THIS_MODULE);
17646 /*
17647 ** notify that the interface which has been closed
17648 ** by operator interaction must not be started up
17649 ** again when the DIAG has finished.
17650 */
17651- newPtrNet = netdev_priv(pAC->dev[0]);
17652+ newPtrNet = (DEV_NET *) pAC->dev[0]->priv;
17653 if (newPtrNet == pNet) {
17654 pAC->WasIfUp[0] = SK_FALSE;
17655 } else {
17656@@ -1312,7 +2335,6 @@
17657 pAC->DiagFlowCtrl = SK_FALSE;
17658 }
17659 }
17660-#endif
17661
17662 netif_stop_queue(dev);
17663
17664@@ -1321,8 +2343,6 @@
17665 else
17666 PortIdx = pNet->NetNr;
17667
17668- StopDrvCleanupTimer(pAC);
17669-
17670 /*
17671 * Clear multicast table, promiscuous mode ....
17672 */
17673@@ -1334,46 +2354,101 @@
17674 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
17675 /* disable interrupts */
17676 SK_OUT32(pAC->IoBase, B0_IMSK, 0);
17677- EvPara.Para32[0] = pNet->NetNr;
17678- EvPara.Para32[1] = -1;
17679- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
17680- SkEventDispatcher(pAC, pAC->IoBase);
17681+ SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP,
17682+ pNet->NetNr, -1, SK_TRUE);
17683 SK_OUT32(pAC->IoBase, B0_IMSK, 0);
17684 /* stop the hardware */
17685- SkGeDeInit(pAC, pAC->IoBase);
17686- pAC->BoardLevel = SK_INIT_DATA;
17687+
17688+
17689+ if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 1)) {
17690+ /* RLMT check link state mode */
17691+ for (CurrMac=0; CurrMac<pAC->GIni.GIMacsFound; CurrMac++) {
17692+ if (CHIP_ID_YUKON_2(pAC))
17693+ SkY2PortStop( pAC,
17694+ pAC->IoBase,
17695+ CurrMac,
17696+ SK_STOP_ALL,
17697+ SK_HARD_RST);
17698+ else
17699+ SkGeStopPort( pAC,
17700+ pAC->IoBase,
17701+ CurrMac,
17702+ SK_STOP_ALL,
17703+ SK_HARD_RST);
17704+ } /* for */
17705+ } else {
17706+ /* Single link or single port */
17707+ if (CHIP_ID_YUKON_2(pAC))
17708+ SkY2PortStop( pAC,
17709+ pAC->IoBase,
17710+ PortIdx,
17711+ SK_STOP_ALL,
17712+ SK_HARD_RST);
17713+ else
17714+ SkGeStopPort( pAC,
17715+ pAC->IoBase,
17716+ PortIdx,
17717+ SK_STOP_ALL,
17718+ SK_HARD_RST);
17719+ }
17720 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
17721 } else {
17722-
17723 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
17724- EvPara.Para32[0] = pNet->NetNr;
17725- EvPara.Para32[1] = -1;
17726- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
17727- SkPnmiEvent(pAC, pAC->IoBase, SK_PNMI_EVT_XMAC_RESET, EvPara);
17728- SkEventDispatcher(pAC, pAC->IoBase);
17729+ SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP,
17730+ pNet->NetNr, -1, SK_FALSE);
17731+ SkLocalEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET,
17732+ pNet->NetNr, -1, SK_TRUE);
17733 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
17734
17735 /* Stop port */
17736 spin_lock_irqsave(&pAC->TxPort[pNet->PortNr]
17737 [TX_PRIO_LOW].TxDesRingLock, Flags);
17738- SkGeStopPort(pAC, pAC->IoBase, pNet->PortNr,
17739- SK_STOP_ALL, SK_HARD_RST);
17740+ if (CHIP_ID_YUKON_2(pAC)) {
17741+ SkY2PortStop(pAC, pAC->IoBase, pNet->PortNr,
17742+ SK_STOP_ALL, SK_HARD_RST);
17743+ }
17744+ else {
17745+ SkGeStopPort(pAC, pAC->IoBase, pNet->PortNr,
17746+ SK_STOP_ALL, SK_HARD_RST);
17747+ }
17748 spin_unlock_irqrestore(&pAC->TxPort[pNet->PortNr]
17749 [TX_PRIO_LOW].TxDesRingLock, Flags);
17750 }
17751
17752 if (pAC->RlmtNets == 1) {
17753 /* clear all descriptor rings */
17754- for (i=0; i<pAC->GIni.GIMacsFound; i++) {
17755- ReceiveIrq(pAC, &pAC->RxPort[i], SK_TRUE);
17756- ClearRxRing(pAC, &pAC->RxPort[i]);
17757- ClearTxRing(pAC, &pAC->TxPort[i][TX_PRIO_LOW]);
17758+ for (CurrMac=0; CurrMac<pAC->GIni.GIMacsFound; CurrMac++) {
17759+ if (!CHIP_ID_YUKON_2(pAC)) {
17760+#ifdef CONFIG_SK98LIN_NAPI
17761+ WorkToDo = 1;
17762+ ReceiveIrq(pAC,&pAC->RxPort[CurrMac],
17763+ SK_TRUE,&WorkDone,WorkToDo);
17764+#else
17765+ ReceiveIrq(pAC,&pAC->RxPort[CurrMac],SK_TRUE);
17766+#endif
17767+ ClearRxRing(pAC, &pAC->RxPort[CurrMac]);
17768+ ClearTxRing(pAC, &pAC->TxPort[CurrMac][TX_PRIO_LOW]);
17769+ } else {
17770+ SkY2FreeRxBuffers(pAC, pAC->IoBase, CurrMac);
17771+ SkY2FreeTxBuffers(pAC, pAC->IoBase, CurrMac);
17772+ }
17773 }
17774 } else {
17775 /* clear port descriptor rings */
17776- ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE);
17777- ClearRxRing(pAC, &pAC->RxPort[pNet->PortNr]);
17778- ClearTxRing(pAC, &pAC->TxPort[pNet->PortNr][TX_PRIO_LOW]);
17779+ if (!CHIP_ID_YUKON_2(pAC)) {
17780+#ifdef CONFIG_SK98LIN_NAPI
17781+ WorkToDo = 1;
17782+ ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE, &WorkDone, WorkToDo);
17783+#else
17784+ ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE);
17785+#endif
17786+ ClearRxRing(pAC, &pAC->RxPort[pNet->PortNr]);
17787+ ClearTxRing(pAC, &pAC->TxPort[pNet->PortNr][TX_PRIO_LOW]);
17788+ }
17789+ else {
17790+ SkY2FreeRxBuffers(pAC, pAC->IoBase, pNet->PortNr);
17791+ SkY2FreeTxBuffers(pAC, pAC->IoBase, pNet->PortNr);
17792+ }
17793 }
17794
17795 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
17796@@ -1384,6 +2459,12 @@
17797 sizeof(SK_PNMI_STRUCT_DATA));
17798
17799 pAC->MaxPorts--;
17800+ module_put(THIS_MODULE);
17801+
17802+#ifdef Y2_RECOVERY
17803+ pNet->InRecover = SK_FALSE;
17804+#endif
17805+ spin_unlock_irqrestore(&pAC->InitLock, InitFlags);
17806
17807 return (0);
17808 } /* SkGeClose */
17809@@ -1410,7 +2491,7 @@
17810 SK_AC *pAC;
17811 int Rc; /* return code of XmitFrame */
17812
17813- pNet = netdev_priv(dev);
17814+ pNet = (DEV_NET*) dev->priv;
17815 pAC = pNet->pAC;
17816
17817 if ((!skb_shinfo(skb)->nr_frags) ||
17818@@ -1442,9 +2523,11 @@
17819 }
17820
17821 /* Transmitter out of resources? */
17822+#ifdef USE_TX_COMPLETE
17823 if (Rc <= 0) {
17824 netif_stop_queue(dev);
17825 }
17826+#endif
17827
17828 /* If not taken, give buffer ownership back to the
17829 * queueing layer.
17830@@ -1456,6 +2539,96 @@
17831 return (0);
17832 } /* SkGeXmit */
17833
17834+#ifdef CONFIG_SK98LIN_NAPI
17835+/*****************************************************************************
17836+ *
17837+ * SkGePoll - NAPI Rx polling callback for GEnesis and Yukon chipsets
17838+ *
17839+ * Description:
17840+ * Called by the Linux system in case NAPI polling is activated
17841+ *
17842+ * Returns:
17843+ * The number of work data still to be handled
17844+ */
17845+static int SkGePoll(struct net_device *dev, int *budget)
17846+{
17847+ SK_AC *pAC = ((DEV_NET*)(dev->priv))->pAC; /* pointer to adapter context */
17848+ int WorkToDo = min(*budget, dev->quota);
17849+ int WorkDone = 0;
17850+ unsigned long Flags;
17851+
17852+
17853+ if (pAC->dev[0] != pAC->dev[1]) {
17854+ spin_lock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock);
17855+ FreeTxDescriptors(pAC, &pAC->TxPort[1][TX_PRIO_LOW]);
17856+ spin_unlock(&pAC->TxPort[1][TX_PRIO_LOW].TxDesRingLock);
17857+
17858+ ReceiveIrq(pAC, &pAC->RxPort[1], SK_TRUE, &WorkDone, WorkToDo);
17859+ CLEAR_AND_START_RX(1);
17860+ }
17861+ spin_lock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
17862+ FreeTxDescriptors(pAC, &pAC->TxPort[0][TX_PRIO_LOW]);
17863+ spin_unlock(&pAC->TxPort[0][TX_PRIO_LOW].TxDesRingLock);
17864+
17865+ ReceiveIrq(pAC, &pAC->RxPort[0], SK_TRUE, &WorkDone, WorkToDo);
17866+ CLEAR_AND_START_RX(0);
17867+
17868+ *budget -= WorkDone;
17869+ dev->quota -= WorkDone;
17870+
17871+ if(WorkDone < WorkToDo) {
17872+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
17873+ netif_rx_complete(dev);
17874+ pAC->GIni.GIValIrqMask |= (NAPI_DRV_IRQS);
17875+#ifndef USE_TX_COMPLETE
17876+ pAC->GIni.GIValIrqMask &= ~(TX_COMPL_IRQS);
17877+#endif
17878+ /* enable interrupts again */
17879+ SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
17880+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
17881+ }
17882+ return (WorkDone >= WorkToDo);
17883+} /* SkGePoll */
17884+#endif
17885+
17886+#ifdef SK_POLL_CONTROLLER
17887+/*****************************************************************************
17888+ *
17889+ * SkGeNetPoll - Polling "interrupt"
17890+ *
17891+ * Description:
17892+ * Polling 'interrupt' - used by things like netconsole and netdump
17893+ * to send skbs without having to re-enable interrupts.
17894+ * It's not called while the interrupt routine is executing.
17895+ */
17896+static void SkGeNetPoll(
17897+struct SK_NET_DEVICE *dev)
17898+{
17899+DEV_NET *pNet;
17900+SK_AC *pAC;
17901+
17902+ pNet = (DEV_NET*) dev->priv;
17903+ pAC = pNet->pAC;
17904+ pNet->NetConsoleMode = SK_TRUE;
17905+
17906+ /* Prevent any reconfiguration while handling
17907+ the 'interrupt' */
17908+ SK_OUT32(pAC->IoBase, B0_IMSK, 0);
17909+
17910+ if (!CHIP_ID_YUKON_2(pAC)) {
17911+ /* Handle the GENESIS Isr */
17912+ if (pAC->GIni.GIMacsFound == 2)
17913+ SkGeIsr(dev->irq, dev, NULL);
17914+ else
17915+ SkGeIsrOnePort(dev->irq, dev, NULL);
17916+ } else {
17917+ /* Handle the Yukon2 Isr */
17918+ SkY2Isr(dev->irq, dev, NULL);
17919+ }
17920+
17921+}
17922+#endif
17923+
17924
17925 /*****************************************************************************
17926 *
17927@@ -1480,7 +2653,7 @@
17928 * < 0 - on failure: other problems ( -> return failure to upper layers)
17929 */
17930 static int XmitFrame(
17931-SK_AC *pAC, /* pointer to adapter context */
17932+SK_AC *pAC, /* pointer to adapter context */
17933 TX_PORT *pTxPort, /* pointer to struct of port to send to */
17934 struct sk_buff *pMessage) /* pointer to send-message */
17935 {
17936@@ -1488,17 +2661,22 @@
17937 TXD *pOldTxd;
17938 unsigned long Flags;
17939 SK_U64 PhysAddr;
17940+ int Protocol;
17941+ int IpHeaderLength;
17942 int BytesSend = pMessage->len;
17943
17944 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS, ("X"));
17945
17946 spin_lock_irqsave(&pTxPort->TxDesRingLock, Flags);
17947 #ifndef USE_TX_COMPLETE
17948- FreeTxDescriptors(pAC, pTxPort);
17949+ if ((pTxPort->TxdRingPrevFree - pTxPort->TxdRingFree) > 6) {
17950+ FreeTxDescriptors(pAC, pTxPort);
17951+ pTxPort->TxdRingPrevFree = pTxPort->TxdRingFree;
17952+ }
17953 #endif
17954 if (pTxPort->TxdRingFree == 0) {
17955 /*
17956- ** no enough free descriptors in ring at the moment.
17957+ ** not enough free descriptors in ring at the moment.
17958 ** Maybe free'ing some old one help?
17959 */
17960 FreeTxDescriptors(pAC, pTxPort);
17961@@ -1560,10 +2738,8 @@
17962 pTxd->pMBuf = pMessage;
17963
17964 if (pMessage->ip_summed == CHECKSUM_HW) {
17965- u16 hdrlen = pMessage->h.raw - pMessage->data;
17966- u16 offset = hdrlen + pMessage->csum;
17967-
17968- if ((pMessage->h.ipiph->protocol == IPPROTO_UDP ) &&
17969+ Protocol = ((SK_U8)pMessage->data[C_OFFSET_IPPROTO] & 0xff);
17970+ if ((Protocol == C_PROTO_ID_UDP) &&
17971 (pAC->GIni.GIChipRev == 0) &&
17972 (pAC->GIni.GIChipId == CHIP_ID_YUKON)) {
17973 pTxd->TBControl = BMU_TCP_CHECK;
17974@@ -1571,9 +2747,14 @@
17975 pTxd->TBControl = BMU_UDP_CHECK;
17976 }
17977
17978- pTxd->TcpSumOfs = 0;
17979- pTxd->TcpSumSt = hdrlen;
17980- pTxd->TcpSumWr = offset;
17981+ IpHeaderLength = (SK_U8)pMessage->data[C_OFFSET_IPHEADER];
17982+ IpHeaderLength = (IpHeaderLength & 0xf) * 4;
17983+ pTxd->TcpSumOfs = 0; /* PH-Checksum already calculated */
17984+ pTxd->TcpSumSt = C_LEN_ETHERMAC_HEADER + IpHeaderLength +
17985+ (Protocol == C_PROTO_ID_UDP ?
17986+ C_OFFSET_UDPHEADER_UDPCS :
17987+ C_OFFSET_TCPHEADER_TCPCS);
17988+ pTxd->TcpSumWr = C_LEN_ETHERMAC_HEADER + IpHeaderLength;
17989
17990 pTxd->TBControl |= BMU_OWN | BMU_STF |
17991 BMU_SW | BMU_EOF |
17992@@ -1581,7 +2762,7 @@
17993 BMU_IRQ_EOF |
17994 #endif
17995 pMessage->len;
17996- } else {
17997+ } else {
17998 pTxd->TBControl = BMU_OWN | BMU_STF | BMU_CHECK |
17999 BMU_SW | BMU_EOF |
18000 #ifdef USE_TX_COMPLETE
18001@@ -1636,10 +2817,11 @@
18002 TXD *pTxdLst;
18003 int CurrFrag;
18004 int BytesSend;
18005+ int IpHeaderLength;
18006+ int Protocol;
18007 skb_frag_t *sk_frag;
18008 SK_U64 PhysAddr;
18009 unsigned long Flags;
18010- SK_U32 Control;
18011
18012 spin_lock_irqsave(&pTxPort->TxDesRingLock, Flags);
18013 #ifndef USE_TX_COMPLETE
18014@@ -1662,6 +2844,7 @@
18015 pTxdFst = pTxd;
18016 pTxdLst = pTxd;
18017 BytesSend = 0;
18018+ Protocol = 0;
18019
18020 /*
18021 ** Map the first fragment (header) into the DMA-space
18022@@ -1679,31 +2862,32 @@
18023 ** Does the HW need to evaluate checksum for TCP or UDP packets?
18024 */
18025 if (pMessage->ip_summed == CHECKSUM_HW) {
18026- u16 hdrlen = pMessage->h.raw - pMessage->data;
18027- u16 offset = hdrlen + pMessage->csum;
18028-
18029- Control = BMU_STFWD;
18030-
18031+ pTxd->TBControl = BMU_STF | BMU_STFWD | skb_headlen(pMessage);
18032 /*
18033 ** We have to use the opcode for tcp here, because the
18034 ** opcode for udp is not working in the hardware yet
18035 ** (Revision 2.0)
18036 */
18037- if ((pMessage->h.ipiph->protocol == IPPROTO_UDP ) &&
18038+ Protocol = ((SK_U8)pMessage->data[C_OFFSET_IPPROTO] & 0xff);
18039+ if ((Protocol == C_PROTO_ID_UDP) &&
18040 (pAC->GIni.GIChipRev == 0) &&
18041 (pAC->GIni.GIChipId == CHIP_ID_YUKON)) {
18042- Control |= BMU_TCP_CHECK;
18043+ pTxd->TBControl |= BMU_TCP_CHECK;
18044 } else {
18045- Control |= BMU_UDP_CHECK;
18046+ pTxd->TBControl |= BMU_UDP_CHECK;
18047 }
18048
18049- pTxd->TcpSumOfs = 0;
18050- pTxd->TcpSumSt = hdrlen;
18051- pTxd->TcpSumWr = offset;
18052- } else
18053- Control = BMU_CHECK | BMU_SW;
18054-
18055- pTxd->TBControl = BMU_STF | Control | skb_headlen(pMessage);
18056+ IpHeaderLength = ((SK_U8)pMessage->data[C_OFFSET_IPHEADER] & 0xf)*4;
18057+ pTxd->TcpSumOfs = 0; /* PH-Checksum already claculated */
18058+ pTxd->TcpSumSt = C_LEN_ETHERMAC_HEADER + IpHeaderLength +
18059+ (Protocol == C_PROTO_ID_UDP ?
18060+ C_OFFSET_UDPHEADER_UDPCS :
18061+ C_OFFSET_TCPHEADER_TCPCS);
18062+ pTxd->TcpSumWr = C_LEN_ETHERMAC_HEADER + IpHeaderLength;
18063+ } else {
18064+ pTxd->TBControl = BMU_CHECK | BMU_SW | BMU_STF |
18065+ skb_headlen(pMessage);
18066+ }
18067
18068 pTxd = pTxd->pNextTxd;
18069 pTxPort->TxdRingFree--;
18070@@ -1727,18 +2911,40 @@
18071 pTxd->VDataHigh = (SK_U32) (PhysAddr >> 32);
18072 pTxd->pMBuf = pMessage;
18073
18074- pTxd->TBControl = Control | BMU_OWN | sk_frag->size;;
18075+ /*
18076+ ** Does the HW need to evaluate checksum for TCP or UDP packets?
18077+ */
18078+ if (pMessage->ip_summed == CHECKSUM_HW) {
18079+ pTxd->TBControl = BMU_OWN | BMU_SW | BMU_STFWD;
18080+ /*
18081+ ** We have to use the opcode for tcp here because the
18082+ ** opcode for udp is not working in the hardware yet
18083+ ** (revision 2.0)
18084+ */
18085+ if ((Protocol == C_PROTO_ID_UDP) &&
18086+ (pAC->GIni.GIChipRev == 0) &&
18087+ (pAC->GIni.GIChipId == CHIP_ID_YUKON)) {
18088+ pTxd->TBControl |= BMU_TCP_CHECK;
18089+ } else {
18090+ pTxd->TBControl |= BMU_UDP_CHECK;
18091+ }
18092+ } else {
18093+ pTxd->TBControl = BMU_CHECK | BMU_SW | BMU_OWN;
18094+ }
18095
18096 /*
18097 ** Do we have the last fragment?
18098 */
18099 if( (CurrFrag+1) == skb_shinfo(pMessage)->nr_frags ) {
18100 #ifdef USE_TX_COMPLETE
18101- pTxd->TBControl |= BMU_EOF | BMU_IRQ_EOF;
18102+ pTxd->TBControl |= BMU_EOF | BMU_IRQ_EOF | sk_frag->size;
18103 #else
18104- pTxd->TBControl |= BMU_EOF;
18105+ pTxd->TBControl |= BMU_EOF | sk_frag->size;
18106 #endif
18107 pTxdFst->TBControl |= BMU_OWN | BMU_SW;
18108+
18109+ } else {
18110+ pTxd->TBControl |= sk_frag->size;
18111 }
18112 pTxdLst = pTxd;
18113 pTxd = pTxd->pNextTxd;
18114@@ -1892,7 +3098,7 @@
18115 SK_U16 Length; /* data fragment length */
18116 SK_U64 PhysAddr; /* physical address of a rx buffer */
18117
18118- pMsgBlock = alloc_skb(pAC->RxBufSize, GFP_ATOMIC);
18119+ pMsgBlock = alloc_skb(pRxPort->RxBufSize, GFP_ATOMIC);
18120 if (pMsgBlock == NULL) {
18121 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
18122 SK_DBGCAT_DRV_ENTRY,
18123@@ -1906,12 +3112,12 @@
18124 pRxd = pRxPort->pRxdRingTail;
18125 pRxPort->pRxdRingTail = pRxd->pNextRxd;
18126 pRxPort->RxdRingFree--;
18127- Length = pAC->RxBufSize;
18128+ Length = pRxPort->RxBufSize;
18129 PhysAddr = (SK_U64) pci_map_page(pAC->PciDev,
18130 virt_to_page(pMsgBlock->data),
18131 ((unsigned long) pMsgBlock->data &
18132 ~PAGE_MASK),
18133- pAC->RxBufSize - 2,
18134+ pRxPort->RxBufSize - 2,
18135 PCI_DMA_FROMDEVICE);
18136
18137 pRxd->VDataLow = (SK_U32) (PhysAddr & 0xffffffff);
18138@@ -1951,7 +3157,7 @@
18139 pRxd = pRxPort->pRxdRingTail;
18140 pRxPort->pRxdRingTail = pRxd->pNextRxd;
18141 pRxPort->RxdRingFree--;
18142- Length = pAC->RxBufSize;
18143+ Length = pRxPort->RxBufSize;
18144
18145 pRxd->VDataLow = PhysLow;
18146 pRxd->VDataHigh = PhysHigh;
18147@@ -1976,28 +3182,40 @@
18148 * Returns: N/A
18149 */
18150 static void ReceiveIrq(
18151- SK_AC *pAC, /* pointer to adapter context */
18152- RX_PORT *pRxPort, /* pointer to receive port struct */
18153- SK_BOOL SlowPathLock) /* indicates if SlowPathLock is needed */
18154-{
18155-RXD *pRxd; /* pointer to receive descriptors */
18156-SK_U32 Control; /* control field of descriptor */
18157-struct sk_buff *pMsg; /* pointer to message holding frame */
18158-struct sk_buff *pNewMsg; /* pointer to a new message for copying frame */
18159-int FrameLength; /* total length of received frame */
18160-SK_MBUF *pRlmtMbuf; /* ptr to a buffer for giving a frame to rlmt */
18161-SK_EVPARA EvPara; /* an event parameter union */
18162-unsigned long Flags; /* for spin lock */
18163-int PortIndex = pRxPort->PortIndex;
18164-unsigned int Offset;
18165-unsigned int NumBytes;
18166-unsigned int ForRlmt;
18167-SK_BOOL IsBc;
18168-SK_BOOL IsMc;
18169-SK_BOOL IsBadFrame; /* Bad frame */
18170-
18171-SK_U32 FrameStat;
18172-SK_U64 PhysAddr;
18173+#ifdef CONFIG_SK98LIN_NAPI
18174+SK_AC *pAC, /* pointer to adapter context */
18175+RX_PORT *pRxPort, /* pointer to receive port struct */
18176+SK_BOOL SlowPathLock, /* indicates if SlowPathLock is needed */
18177+int *WorkDone,
18178+int WorkToDo)
18179+#else
18180+SK_AC *pAC, /* pointer to adapter context */
18181+RX_PORT *pRxPort, /* pointer to receive port struct */
18182+SK_BOOL SlowPathLock) /* indicates if SlowPathLock is needed */
18183+#endif
18184+{
18185+ RXD *pRxd; /* pointer to receive descriptors */
18186+ struct sk_buff *pMsg; /* pointer to message holding frame */
18187+ struct sk_buff *pNewMsg; /* pointer to new message for frame copy */
18188+ SK_MBUF *pRlmtMbuf; /* ptr to buffer for giving frame to RLMT */
18189+ SK_EVPARA EvPara; /* an event parameter union */
18190+ SK_U32 Control; /* control field of descriptor */
18191+ unsigned long Flags; /* for spin lock handling */
18192+ int PortIndex = pRxPort->PortIndex;
18193+ int FrameLength; /* total length of received frame */
18194+ int IpFrameLength; /* IP length of the received frame */
18195+ unsigned int Offset;
18196+ unsigned int NumBytes;
18197+ unsigned int RlmtNotifier;
18198+ SK_BOOL IsBc; /* we received a broadcast packet */
18199+ SK_BOOL IsMc; /* we received a multicast packet */
18200+ SK_BOOL IsBadFrame; /* the frame received is bad! */
18201+ SK_U32 FrameStat;
18202+ unsigned short Csum1;
18203+ unsigned short Csum2;
18204+ unsigned short Type;
18205+ int Result;
18206+ SK_U64 PhysAddr;
18207
18208 rx_start:
18209 /* do forever; exit if BMU_OWN found */
18210@@ -2019,6 +3237,13 @@
18211
18212 Control = pRxd->RBControl;
18213
18214+#ifdef CONFIG_SK98LIN_NAPI
18215+ if (*WorkDone >= WorkToDo) {
18216+ break;
18217+ }
18218+ (*WorkDone)++;
18219+#endif
18220+
18221 /* check if this descriptor is ready */
18222 if ((Control & BMU_OWN) != 0) {
18223 /* this descriptor is not yet ready */
18224@@ -2027,11 +3252,10 @@
18225 FillRxRing(pAC, pRxPort);
18226 return;
18227 }
18228- pAC->DynIrqModInfo.NbrProcessedDescr++;
18229
18230 /* get length of frame and check it */
18231 FrameLength = Control & BMU_BBC;
18232- if (FrameLength > pAC->RxBufSize) {
18233+ if (FrameLength > pRxPort->RxBufSize) {
18234 goto rx_failed;
18235 }
18236
18237@@ -2046,8 +3270,8 @@
18238 FrameStat = pRxd->FrameStat;
18239
18240 /* check for frame length mismatch */
18241-#define XMR_FS_LEN_SHIFT 18
18242-#define GMR_FS_LEN_SHIFT 16
18243+#define XMR_FS_LEN_SHIFT 18
18244+#define GMR_FS_LEN_SHIFT 16
18245 if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
18246 if (FrameLength != (SK_U32) (FrameStat >> XMR_FS_LEN_SHIFT)) {
18247 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
18248@@ -2057,8 +3281,7 @@
18249 (SK_U32) (FrameStat >> XMR_FS_LEN_SHIFT)));
18250 goto rx_failed;
18251 }
18252- }
18253- else {
18254+ } else {
18255 if (FrameLength != (SK_U32) (FrameStat >> GMR_FS_LEN_SHIFT)) {
18256 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
18257 SK_DBGCAT_DRV_RX_PROGRESS,
18258@@ -2091,9 +3314,6 @@
18259 /* DumpMsg(pMsg, "Rx"); */
18260
18261 if ((Control & BMU_STAT_VAL) != BMU_STAT_VAL || (IsBadFrame)) {
18262-#if 0
18263- (FrameStat & (XMR_FS_ANY_ERR | XMR_FS_2L_VLAN)) != 0) {
18264-#endif
18265 /* there is a receive error in this frame */
18266 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
18267 SK_DBGCAT_DRV_RX_PROGRESS,
18268@@ -2101,6 +3321,20 @@
18269 "Control: %x\nRxStat: %x\n",
18270 Control, FrameStat));
18271
18272+ PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32;
18273+ PhysAddr |= (SK_U64) pRxd->VDataLow;
18274+
18275+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5)
18276+ pci_dma_sync_single(pAC->PciDev,
18277+ (dma_addr_t) PhysAddr,
18278+ FrameLength,
18279+ PCI_DMA_FROMDEVICE);
18280+#else
18281+ pci_dma_sync_single_for_cpu(pAC->PciDev,
18282+ (dma_addr_t) PhysAddr,
18283+ FrameLength,
18284+ PCI_DMA_FROMDEVICE);
18285+#endif
18286 ReQueueRxBuffer(pAC, pRxPort, pMsg,
18287 pRxd->VDataHigh, pRxd->VDataLow);
18288
18289@@ -2120,96 +3354,107 @@
18290 skb_put(pNewMsg, FrameLength);
18291 PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32;
18292 PhysAddr |= (SK_U64) pRxd->VDataLow;
18293-
18294- pci_dma_sync_single_for_cpu(pAC->PciDev,
18295- (dma_addr_t) PhysAddr,
18296- FrameLength,
18297- PCI_DMA_FROMDEVICE);
18298- memcpy(pNewMsg->data, pMsg, FrameLength);
18299-
18300+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5)
18301+ pci_dma_sync_single(pAC->PciDev,
18302+ (dma_addr_t) PhysAddr,
18303+ FrameLength,
18304+ PCI_DMA_FROMDEVICE);
18305+#else
18306 pci_dma_sync_single_for_device(pAC->PciDev,
18307- (dma_addr_t) PhysAddr,
18308- FrameLength,
18309- PCI_DMA_FROMDEVICE);
18310+ (dma_addr_t) PhysAddr,
18311+ FrameLength,
18312+ PCI_DMA_FROMDEVICE);
18313+#endif
18314+
18315+ eth_copy_and_sum(pNewMsg, pMsg->data,
18316+ FrameLength, 0);
18317 ReQueueRxBuffer(pAC, pRxPort, pMsg,
18318 pRxd->VDataHigh, pRxd->VDataLow);
18319
18320 pMsg = pNewMsg;
18321
18322- }
18323- else {
18324+ } else {
18325 /*
18326 * if large frame, or SKB allocation failed, pass
18327 * the SKB directly to the networking
18328 */
18329-
18330 PhysAddr = ((SK_U64) pRxd->VDataHigh) << (SK_U64)32;
18331 PhysAddr |= (SK_U64) pRxd->VDataLow;
18332
18333 /* release the DMA mapping */
18334 pci_unmap_single(pAC->PciDev,
18335 PhysAddr,
18336- pAC->RxBufSize - 2,
18337+ pRxPort->RxBufSize - 2,
18338 PCI_DMA_FROMDEVICE);
18339+ skb_put(pMsg, FrameLength); /* set message len */
18340+ pMsg->ip_summed = CHECKSUM_NONE; /* initial default */
18341
18342- /* set length in message */
18343- skb_put(pMsg, FrameLength);
18344+ if (pRxPort->UseRxCsum) {
18345+ Type = ntohs(*((short*)&pMsg->data[12]));
18346+ if (Type == 0x800) {
18347+ IpFrameLength = (int) ntohs((unsigned short)
18348+ ((unsigned short *) pMsg->data)[8]);
18349+ if ((FrameLength - IpFrameLength) == 0xe) {
18350+ Csum1=le16_to_cpu(pRxd->TcpSums & 0xffff);
18351+ Csum2=le16_to_cpu((pRxd->TcpSums >> 16) & 0xffff);
18352+ if ((((Csum1 & 0xfffe) && (Csum2 & 0xfffe)) &&
18353+ (pAC->GIni.GIChipId == CHIP_ID_GENESIS)) ||
18354+ (pAC->ChipsetType)) {
18355+ Result = SkCsGetReceiveInfo(pAC, &pMsg->data[14],
18356+ Csum1, Csum2, PortIndex);
18357+ if ((Result == SKCS_STATUS_IP_FRAGMENT) ||
18358+ (Result == SKCS_STATUS_IP_CSUM_OK) ||
18359+ (Result == SKCS_STATUS_TCP_CSUM_OK) ||
18360+ (Result == SKCS_STATUS_UDP_CSUM_OK)) {
18361+ pMsg->ip_summed = CHECKSUM_UNNECESSARY;
18362+ } else if ((Result == SKCS_STATUS_TCP_CSUM_ERROR) ||
18363+ (Result == SKCS_STATUS_UDP_CSUM_ERROR) ||
18364+ (Result == SKCS_STATUS_IP_CSUM_ERROR_UDP) ||
18365+ (Result == SKCS_STATUS_IP_CSUM_ERROR_TCP) ||
18366+ (Result == SKCS_STATUS_IP_CSUM_ERROR)) {
18367+ /* HW Checksum error */
18368+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
18369+ SK_DBGCAT_DRV_RX_PROGRESS,
18370+ ("skge: CRC error. Frame dropped!\n"));
18371+ goto rx_failed;
18372+ } else {
18373+ pMsg->ip_summed = CHECKSUM_NONE;
18374+ }
18375+ }/* checksumControl calculation valid */
18376+ } /* Frame length check */
18377+ } /* IP frame */
18378+ } /* pRxPort->UseRxCsum */
18379 } /* frame > SK_COPY_TRESHOLD */
18380-
18381-#ifdef USE_SK_RX_CHECKSUM
18382- pMsg->csum = pRxd->TcpSums & 0xffff;
18383- pMsg->ip_summed = CHECKSUM_HW;
18384-#else
18385- pMsg->ip_summed = CHECKSUM_NONE;
18386-#endif
18387-
18388+
18389 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("V"));
18390- ForRlmt = SK_RLMT_RX_PROTOCOL;
18391-#if 0
18392- IsBc = (FrameStat & XMR_FS_BC)==XMR_FS_BC;
18393-#endif
18394+ RlmtNotifier = SK_RLMT_RX_PROTOCOL;
18395 SK_RLMT_PRE_LOOKAHEAD(pAC, PortIndex, FrameLength,
18396- IsBc, &Offset, &NumBytes);
18397+ IsBc, &Offset, &NumBytes);
18398 if (NumBytes != 0) {
18399-#if 0
18400- IsMc = (FrameStat & XMR_FS_MC)==XMR_FS_MC;
18401-#endif
18402- SK_RLMT_LOOKAHEAD(pAC, PortIndex,
18403- &pMsg->data[Offset],
18404- IsBc, IsMc, &ForRlmt);
18405+ SK_RLMT_LOOKAHEAD(pAC,PortIndex,&pMsg->data[Offset],
18406+ IsBc,IsMc,&RlmtNotifier);
18407 }
18408- if (ForRlmt == SK_RLMT_RX_PROTOCOL) {
18409- SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("W"));
18410+ if (RlmtNotifier == SK_RLMT_RX_PROTOCOL) {
18411+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("W"));
18412 /* send up only frames from active port */
18413- if ((PortIndex == pAC->ActivePort) ||
18414- (pAC->RlmtNets == 2)) {
18415- /* frame for upper layer */
18416+ if ((PortIndex == pAC->ActivePort)||(pAC->RlmtNets == 2)) {
18417 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("U"));
18418 #ifdef xDEBUG
18419 DumpMsg(pMsg, "Rx");
18420 #endif
18421- SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC,
18422- FrameLength, pRxPort->PortIndex);
18423-
18424- pMsg->dev = pAC->dev[pRxPort->PortIndex];
18425- pMsg->protocol = eth_type_trans(pMsg,
18426- pAC->dev[pRxPort->PortIndex]);
18427- netif_rx(pMsg);
18428- pAC->dev[pRxPort->PortIndex]->last_rx = jiffies;
18429- }
18430- else {
18431- /* drop frame */
18432+ SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC,FrameLength,PortIndex);
18433+ pMsg->dev = pAC->dev[PortIndex];
18434+ pMsg->protocol = eth_type_trans(pMsg,pAC->dev[PortIndex]);
18435+ netif_rx(pMsg); /* frame for upper layer */
18436+ pAC->dev[PortIndex]->last_rx = jiffies;
18437+ } else {
18438 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
18439- SK_DBGCAT_DRV_RX_PROGRESS,
18440- ("D"));
18441- DEV_KFREE_SKB(pMsg);
18442+ SK_DBGCAT_DRV_RX_PROGRESS,("D"));
18443+ DEV_KFREE_SKB(pMsg); /* drop frame */
18444 }
18445-
18446- } /* if not for rlmt */
18447- else {
18448- /* packet for rlmt */
18449+ } else { /* packet for RLMT stack */
18450 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
18451- SK_DBGCAT_DRV_RX_PROGRESS, ("R"));
18452+ SK_DBGCAT_DRV_RX_PROGRESS,("R"));
18453 pRlmtMbuf = SkDrvAllocRlmtMbuf(pAC,
18454 pAC->IoBase, FrameLength);
18455 if (pRlmtMbuf != NULL) {
18456@@ -2237,32 +3482,22 @@
18457 }
18458
18459 SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
18460- SK_DBGCAT_DRV_RX_PROGRESS,
18461- ("Q"));
18462+ SK_DBGCAT_DRV_RX_PROGRESS,("Q"));
18463 }
18464- if ((pAC->dev[pRxPort->PortIndex]->flags &
18465- (IFF_PROMISC | IFF_ALLMULTI)) != 0 ||
18466- (ForRlmt & SK_RLMT_RX_PROTOCOL) ==
18467- SK_RLMT_RX_PROTOCOL) {
18468- pMsg->dev = pAC->dev[pRxPort->PortIndex];
18469- pMsg->protocol = eth_type_trans(pMsg,
18470- pAC->dev[pRxPort->PortIndex]);
18471+ if ((pAC->dev[PortIndex]->flags & (IFF_PROMISC | IFF_ALLMULTI)) ||
18472+ (RlmtNotifier & SK_RLMT_RX_PROTOCOL)) {
18473+ pMsg->dev = pAC->dev[PortIndex];
18474+ pMsg->protocol = eth_type_trans(pMsg,pAC->dev[PortIndex]);
18475 netif_rx(pMsg);
18476- pAC->dev[pRxPort->PortIndex]->last_rx = jiffies;
18477- }
18478- else {
18479+ pAC->dev[PortIndex]->last_rx = jiffies;
18480+ } else {
18481 DEV_KFREE_SKB(pMsg);
18482 }
18483-
18484- } /* if packet for rlmt */
18485+ } /* if packet for RLMT stack */
18486 } /* for ... scanning the RXD ring */
18487
18488 /* RXD ring is empty -> fill and restart */
18489 FillRxRing(pAC, pRxPort);
18490- /* do not start if called from Close */
18491- if (pAC->BoardLevel > SK_INIT_DATA) {
18492- ClearAndStartRx(pAC, PortIndex);
18493- }
18494 return;
18495
18496 rx_failed:
18497@@ -2276,7 +3511,7 @@
18498 PhysAddr |= (SK_U64) pRxd->VDataLow;
18499 pci_unmap_page(pAC->PciDev,
18500 PhysAddr,
18501- pAC->RxBufSize - 2,
18502+ pRxPort->RxBufSize - 2,
18503 PCI_DMA_FROMDEVICE);
18504 DEV_KFREE_SKB_IRQ(pRxd->pMBuf);
18505 pRxd->pMBuf = NULL;
18506@@ -2286,49 +3521,6 @@
18507
18508 } /* ReceiveIrq */
18509
18510-
18511-/*****************************************************************************
18512- *
18513- * ClearAndStartRx - give a start receive command to BMU, clear IRQ
18514- *
18515- * Description:
18516- * This function sends a start command and a clear interrupt
18517- * command for one receive queue to the BMU.
18518- *
18519- * Returns: N/A
18520- * none
18521- */
18522-static void ClearAndStartRx(
18523-SK_AC *pAC, /* pointer to the adapter context */
18524-int PortIndex) /* index of the receive port (XMAC) */
18525-{
18526- SK_OUT8(pAC->IoBase,
18527- RxQueueAddr[PortIndex]+Q_CSR,
18528- CSR_START | CSR_IRQ_CL_F);
18529-} /* ClearAndStartRx */
18530-
18531-
18532-/*****************************************************************************
18533- *
18534- * ClearTxIrq - give a clear transmit IRQ command to BMU
18535- *
18536- * Description:
18537- * This function sends a clear tx IRQ command for one
18538- * transmit queue to the BMU.
18539- *
18540- * Returns: N/A
18541- */
18542-static void ClearTxIrq(
18543-SK_AC *pAC, /* pointer to the adapter context */
18544-int PortIndex, /* index of the transmit port (XMAC) */
18545-int Prio) /* priority or normal queue */
18546-{
18547- SK_OUT8(pAC->IoBase,
18548- TxQueueAddr[PortIndex][Prio]+Q_CSR,
18549- CSR_IRQ_CL_F);
18550-} /* ClearTxIrq */
18551-
18552-
18553 /*****************************************************************************
18554 *
18555 * ClearRxRing - remove all buffers from the receive ring
18556@@ -2359,7 +3551,7 @@
18557 PhysAddr |= (SK_U64) pRxd->VDataLow;
18558 pci_unmap_page(pAC->PciDev,
18559 PhysAddr,
18560- pAC->RxBufSize - 2,
18561+ pRxPort->RxBufSize - 2,
18562 PCI_DMA_FROMDEVICE);
18563 DEV_KFREE_SKB(pRxd->pMBuf);
18564 pRxd->pMBuf = NULL;
18565@@ -2417,31 +3609,32 @@
18566 static int SkGeSetMacAddr(struct SK_NET_DEVICE *dev, void *p)
18567 {
18568
18569-DEV_NET *pNet = netdev_priv(dev);
18570+DEV_NET *pNet = (DEV_NET*) dev->priv;
18571 SK_AC *pAC = pNet->pAC;
18572+int Ret;
18573
18574 struct sockaddr *addr = p;
18575 unsigned long Flags;
18576
18577 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
18578 ("SkGeSetMacAddr starts now...\n"));
18579- if(netif_running(dev))
18580- return -EBUSY;
18581
18582 memcpy(dev->dev_addr, addr->sa_data,dev->addr_len);
18583
18584 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
18585
18586 if (pAC->RlmtNets == 2)
18587- SkAddrOverride(pAC, pAC->IoBase, pNet->NetNr,
18588+ Ret = SkAddrOverride(pAC, pAC->IoBase, pNet->NetNr,
18589 (SK_MAC_ADDR*)dev->dev_addr, SK_ADDR_VIRTUAL_ADDRESS);
18590 else
18591- SkAddrOverride(pAC, pAC->IoBase, pAC->ActivePort,
18592+ Ret = SkAddrOverride(pAC, pAC->IoBase, pAC->ActivePort,
18593 (SK_MAC_ADDR*)dev->dev_addr, SK_ADDR_VIRTUAL_ADDRESS);
18594-
18595-
18596
18597 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
18598+
18599+ if (Ret != SK_ADDR_OVERRIDE_SUCCESS)
18600+ return -EBUSY;
18601+
18602 return 0;
18603 } /* SkGeSetMacAddr */
18604
18605@@ -2474,7 +3667,7 @@
18606 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
18607 ("SkGeSetRxMode starts now... "));
18608
18609- pNet = netdev_priv(dev);
18610+ pNet = (DEV_NET*) dev->priv;
18611 pAC = pNet->pAC;
18612 if (pAC->RlmtNets == 1)
18613 PortIdx = pAC->ActivePort;
18614@@ -2523,6 +3716,45 @@
18615
18616 /*****************************************************************************
18617 *
18618+ * SkSetMtuBufferSize - set the MTU buffer to another value
18619+ *
18620+ * Description:
18621+ * This function sets the new buffers and is called whenever the MTU
18622+ * size is changed
18623+ *
18624+ * Returns:
18625+ * N/A
18626+ */
18627+
18628+static void SkSetMtuBufferSize(
18629+SK_AC *pAC, /* pointer to adapter context */
18630+int PortNr, /* Port number */
18631+int Mtu) /* pointer to tx prt struct */
18632+{
18633+ pAC->RxPort[PortNr].RxBufSize = Mtu + 32;
18634+
18635+ /* RxBufSize must be a multiple of 8 */
18636+ while (pAC->RxPort[PortNr].RxBufSize % 8) {
18637+ pAC->RxPort[PortNr].RxBufSize =
18638+ pAC->RxPort[PortNr].RxBufSize + 1;
18639+ }
18640+
18641+ if (Mtu > 1500) {
18642+ pAC->GIni.GP[PortNr].PPortUsage = SK_JUMBO_LINK;
18643+ } else {
18644+ if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
18645+ pAC->GIni.GP[PortNr].PPortUsage = SK_MUL_LINK;
18646+ } else {
18647+ pAC->GIni.GP[PortNr].PPortUsage = SK_RED_LINK;
18648+ }
18649+ }
18650+
18651+ return;
18652+}
18653+
18654+
18655+/*****************************************************************************
18656+ *
18657 * SkGeChangeMtu - set the MTU to another value
18658 *
18659 * Description:
18660@@ -2536,28 +3768,32 @@
18661 */
18662 static int SkGeChangeMtu(struct SK_NET_DEVICE *dev, int NewMtu)
18663 {
18664-DEV_NET *pNet;
18665-struct net_device *pOtherDev;
18666-SK_AC *pAC;
18667-unsigned long Flags;
18668-int i;
18669-SK_EVPARA EvPara;
18670+DEV_NET *pNet;
18671+SK_AC *pAC;
18672+unsigned long Flags;
18673+#ifdef CONFIG_SK98LIN_NAPI
18674+int WorkToDo = 1; // min(*budget, dev->quota);
18675+int WorkDone = 0;
18676+#endif
18677
18678 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
18679 ("SkGeChangeMtu starts now...\n"));
18680
18681- pNet = netdev_priv(dev);
18682+ pNet = (DEV_NET*) dev->priv;
18683 pAC = pNet->pAC;
18684
18685+ /* MTU size outside the spec */
18686 if ((NewMtu < 68) || (NewMtu > SK_JUMBO_MTU)) {
18687 return -EINVAL;
18688 }
18689
18690- if(pAC->BoardLevel != SK_INIT_RUN) {
18691+ /* MTU > 1500 on yukon ulra not allowed */
18692+ if ((pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U)
18693+ && (NewMtu > 1500)){
18694 return -EINVAL;
18695 }
18696
18697-#ifdef SK_DIAG_SUPPORT
18698+ /* Diag access active */
18699 if (pAC->DiagModeActive == DIAG_ACTIVE) {
18700 if (pAC->DiagFlowCtrl == SK_FALSE) {
18701 return -1; /* still in use, deny any actions of MTU */
18702@@ -2565,201 +3801,74 @@
18703 pAC->DiagFlowCtrl = SK_FALSE;
18704 }
18705 }
18706-#endif
18707-
18708- pOtherDev = pAC->dev[1 - pNet->NetNr];
18709-
18710- if ( netif_running(pOtherDev) && (pOtherDev->mtu > 1500)
18711- && (NewMtu <= 1500))
18712- return 0;
18713
18714- pAC->RxBufSize = NewMtu + 32;
18715 dev->mtu = NewMtu;
18716+ SkSetMtuBufferSize(pAC, pNet->PortNr, NewMtu);
18717
18718- SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
18719- ("New MTU: %d\n", NewMtu));
18720+ if(!netif_running(dev)) {
18721+ /* Preset MTU size if device not ready/running */
18722+ return 0;
18723+ }
18724
18725- /*
18726- ** Prevent any reconfiguration while changing the MTU
18727- ** by disabling any interrupts
18728- */
18729+ /* Prevent any reconfiguration while changing the MTU
18730+ by disabling any interrupts */
18731 SK_OUT32(pAC->IoBase, B0_IMSK, 0);
18732 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
18733
18734- /*
18735- ** Notify RLMT that any ports are to be stopped
18736- */
18737- EvPara.Para32[0] = 0;
18738- EvPara.Para32[1] = -1;
18739- if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
18740- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
18741- EvPara.Para32[0] = 1;
18742- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
18743- } else {
18744- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
18745- }
18746-
18747- /*
18748- ** After calling the SkEventDispatcher(), RLMT is aware about
18749- ** the stopped ports -> configuration can take place!
18750- */
18751- SkEventDispatcher(pAC, pAC->IoBase);
18752-
18753- for (i=0; i<pAC->GIni.GIMacsFound; i++) {
18754- spin_lock(&pAC->TxPort[i][TX_PRIO_LOW].TxDesRingLock);
18755- netif_stop_queue(pAC->dev[i]);
18756+ /* Notify RLMT that the port has to be stopped */
18757+ netif_stop_queue(dev);
18758+ SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP,
18759+ pNet->PortNr, -1, SK_TRUE);
18760+ spin_lock(&pAC->TxPort[pNet->PortNr][TX_PRIO_LOW].TxDesRingLock);
18761
18762- }
18763
18764- /*
18765- ** Depending on the desired MTU size change, a different number of
18766- ** RX buffers need to be allocated
18767- */
18768- if (NewMtu > 1500) {
18769- /*
18770- ** Use less rx buffers
18771- */
18772- for (i=0; i<pAC->GIni.GIMacsFound; i++) {
18773- if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
18774- pAC->RxPort[i].RxFillLimit = pAC->RxDescrPerRing -
18775- (pAC->RxDescrPerRing / 4);
18776- } else {
18777- if (i == pAC->ActivePort) {
18778- pAC->RxPort[i].RxFillLimit = pAC->RxDescrPerRing -
18779- (pAC->RxDescrPerRing / 4);
18780- } else {
18781- pAC->RxPort[i].RxFillLimit = pAC->RxDescrPerRing -
18782- (pAC->RxDescrPerRing / 10);
18783- }
18784- }
18785- }
18786+ /* Change RxFillLimit to 1 */
18787+ if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
18788+ pAC->RxPort[pNet->PortNr].RxFillLimit = 1;
18789 } else {
18790- /*
18791- ** Use the normal amount of rx buffers
18792- */
18793- for (i=0; i<pAC->GIni.GIMacsFound; i++) {
18794- if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
18795- pAC->RxPort[i].RxFillLimit = 1;
18796- } else {
18797- if (i == pAC->ActivePort) {
18798- pAC->RxPort[i].RxFillLimit = 1;
18799- } else {
18800- pAC->RxPort[i].RxFillLimit = pAC->RxDescrPerRing -
18801- (pAC->RxDescrPerRing / 4);
18802- }
18803- }
18804- }
18805+ pAC->RxPort[1 - pNet->PortNr].RxFillLimit = 1;
18806+ pAC->RxPort[pNet->PortNr].RxFillLimit = pAC->RxDescrPerRing -
18807+ (pAC->RxDescrPerRing / 4);
18808 }
18809-
18810- SkGeDeInit(pAC, pAC->IoBase);
18811
18812- /*
18813- ** enable/disable hardware support for long frames
18814- */
18815- if (NewMtu > 1500) {
18816-// pAC->JumboActivated = SK_TRUE; /* is never set back !!! */
18817- pAC->GIni.GIPortUsage = SK_JUMBO_LINK;
18818+ /* clear and reinit the rx rings here, because of new MTU size */
18819+ if (CHIP_ID_YUKON_2(pAC)) {
18820+ SkY2PortStop(pAC, pAC->IoBase, pNet->PortNr, SK_STOP_ALL, SK_SOFT_RST);
18821+ SkY2AllocateRxBuffers(pAC, pAC->IoBase, pNet->PortNr);
18822+ SkY2PortStart(pAC, pAC->IoBase, pNet->PortNr);
18823 } else {
18824- if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
18825- pAC->GIni.GIPortUsage = SK_MUL_LINK;
18826- } else {
18827- pAC->GIni.GIPortUsage = SK_RED_LINK;
18828- }
18829- }
18830+// SkGeStopPort(pAC, pAC->IoBase, pNet->PortNr, SK_STOP_ALL, SK_SOFT_RST);
18831+#ifdef CONFIG_SK98LIN_NAPI
18832+ WorkToDo = 1;
18833+ ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE, &WorkDone, WorkToDo);
18834+#else
18835+ ReceiveIrq(pAC, &pAC->RxPort[pNet->PortNr], SK_TRUE);
18836+#endif
18837+ ClearRxRing(pAC, &pAC->RxPort[pNet->PortNr]);
18838+ FillRxRing(pAC, &pAC->RxPort[pNet->PortNr]);
18839
18840- SkGeInit( pAC, pAC->IoBase, SK_INIT_IO);
18841- SkI2cInit( pAC, pAC->IoBase, SK_INIT_IO);
18842- SkEventInit(pAC, pAC->IoBase, SK_INIT_IO);
18843- SkPnmiInit( pAC, pAC->IoBase, SK_INIT_IO);
18844- SkAddrInit( pAC, pAC->IoBase, SK_INIT_IO);
18845- SkRlmtInit( pAC, pAC->IoBase, SK_INIT_IO);
18846- SkTimerInit(pAC, pAC->IoBase, SK_INIT_IO);
18847-
18848- /*
18849- ** tschilling:
18850- ** Speed and others are set back to default in level 1 init!
18851- */
18852- GetConfiguration(pAC);
18853-
18854- SkGeInit( pAC, pAC->IoBase, SK_INIT_RUN);
18855- SkI2cInit( pAC, pAC->IoBase, SK_INIT_RUN);
18856- SkEventInit(pAC, pAC->IoBase, SK_INIT_RUN);
18857- SkPnmiInit( pAC, pAC->IoBase, SK_INIT_RUN);
18858- SkAddrInit( pAC, pAC->IoBase, SK_INIT_RUN);
18859- SkRlmtInit( pAC, pAC->IoBase, SK_INIT_RUN);
18860- SkTimerInit(pAC, pAC->IoBase, SK_INIT_RUN);
18861+ /* Enable transmit descriptor polling */
18862+ SkGePollTxD(pAC, pAC->IoBase, pNet->PortNr, SK_TRUE);
18863+ FillRxRing(pAC, &pAC->RxPort[pNet->PortNr]);
18864+ }
18865
18866- /*
18867- ** clear and reinit the rx rings here
18868- */
18869- for (i=0; i<pAC->GIni.GIMacsFound; i++) {
18870- ReceiveIrq(pAC, &pAC->RxPort[i], SK_TRUE);
18871- ClearRxRing(pAC, &pAC->RxPort[i]);
18872- FillRxRing(pAC, &pAC->RxPort[i]);
18873+ netif_start_queue(pAC->dev[pNet->PortNr]);
18874
18875- /*
18876- ** Enable transmit descriptor polling
18877- */
18878- SkGePollTxD(pAC, pAC->IoBase, i, SK_TRUE);
18879- FillRxRing(pAC, &pAC->RxPort[i]);
18880- };
18881+ spin_unlock(&pAC->TxPort[pNet->PortNr][TX_PRIO_LOW].TxDesRingLock);
18882
18883- SkGeYellowLED(pAC, pAC->IoBase, 1);
18884- SkDimEnableModerationIfNeeded(pAC);
18885- SkDimDisplayModerationSettings(pAC);
18886
18887- netif_start_queue(pAC->dev[pNet->PortNr]);
18888- for (i=pAC->GIni.GIMacsFound-1; i>=0; i--) {
18889- spin_unlock(&pAC->TxPort[i][TX_PRIO_LOW].TxDesRingLock);
18890- }
18891+ /* Notify RLMT about the changing and restarting one (or more) ports */
18892+ SkLocalEventQueue(pAC, SKGE_RLMT, SK_RLMT_START,
18893+ pNet->PortNr, -1, SK_TRUE);
18894
18895- /*
18896- ** Enable Interrupts again
18897- */
18898+ /* Enable Interrupts again */
18899 SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
18900 SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK);
18901
18902- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara);
18903- SkEventDispatcher(pAC, pAC->IoBase);
18904-
18905- /*
18906- ** Notify RLMT about the changing and restarting one (or more) ports
18907- */
18908- if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
18909- EvPara.Para32[0] = pAC->RlmtNets;
18910- EvPara.Para32[1] = -1;
18911- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_SET_NETS, EvPara);
18912- EvPara.Para32[0] = pNet->PortNr;
18913- EvPara.Para32[1] = -1;
18914- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara);
18915-
18916- if (netif_running(pOtherDev)) {
18917- DEV_NET *pOtherNet = netdev_priv(pOtherDev);
18918- EvPara.Para32[0] = pOtherNet->PortNr;
18919- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara);
18920- }
18921- } else {
18922- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara);
18923- }
18924-
18925- SkEventDispatcher(pAC, pAC->IoBase);
18926 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
18927-
18928- /*
18929- ** While testing this driver with latest kernel 2.5 (2.5.70), it
18930- ** seems as if upper layers have a problem to handle a successful
18931- ** return value of '0'. If such a zero is returned, the complete
18932- ** system hangs for several minutes (!), which is in acceptable.
18933- **
18934- ** Currently it is not clear, what the exact reason for this problem
18935- ** is. The implemented workaround for 2.5 is to return the desired
18936- ** new MTU size if all needed changes for the new MTU size where
18937- ** performed. In kernels 2.2 and 2.4, a zero value is returned,
18938- ** which indicates the successful change of the mtu-size.
18939- */
18940- return NewMtu;
18941+ return 0;
18942
18943-} /* SkGeChangeMtu */
18944+}
18945
18946
18947 /*****************************************************************************
18948@@ -2775,75 +3884,67 @@
18949 */
18950 static struct net_device_stats *SkGeStats(struct SK_NET_DEVICE *dev)
18951 {
18952-DEV_NET *pNet = netdev_priv(dev);
18953-SK_AC *pAC = pNet->pAC;
18954-SK_PNMI_STRUCT_DATA *pPnmiStruct; /* structure for all Pnmi-Data */
18955-SK_PNMI_STAT *pPnmiStat; /* pointer to virtual XMAC stat. data */
18956-SK_PNMI_CONF *pPnmiConf; /* pointer to virtual link config. */
18957-unsigned int Size; /* size of pnmi struct */
18958-unsigned long Flags; /* for spin lock */
18959-
18960- SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
18961- ("SkGeStats starts now...\n"));
18962- pPnmiStruct = &pAC->PnmiStruct;
18963+ DEV_NET *pNet = (DEV_NET*) dev->priv;
18964+ SK_AC *pAC = pNet->pAC;
18965+ unsigned long LateCollisions, ExcessiveCollisions, RxTooLong;
18966+ unsigned long Flags; /* for spin lock */
18967+ SK_U32 MaxNumOidEntries, Oid, Len;
18968+ char Buf[8];
18969+ struct {
18970+ SK_U32 Oid;
18971+ unsigned long *pVar;
18972+ } Vars[] = {
18973+ { OID_SKGE_STAT_TX_LATE_COL, &LateCollisions },
18974+ { OID_SKGE_STAT_TX_EXCESS_COL, &ExcessiveCollisions },
18975+ { OID_SKGE_STAT_RX_TOO_LONG, &RxTooLong },
18976+ { OID_SKGE_STAT_RX, &pAC->stats.rx_packets },
18977+ { OID_SKGE_STAT_TX, &pAC->stats.tx_packets },
18978+ { OID_SKGE_STAT_RX_OCTETS, &pAC->stats.rx_bytes },
18979+ { OID_SKGE_STAT_TX_OCTETS, &pAC->stats.tx_bytes },
18980+ { OID_SKGE_RX_NO_BUF_CTS, &pAC->stats.rx_dropped },
18981+ { OID_SKGE_TX_NO_BUF_CTS, &pAC->stats.tx_dropped },
18982+ { OID_SKGE_STAT_RX_MULTICAST, &pAC->stats.multicast },
18983+ { OID_SKGE_STAT_RX_RUNT, &pAC->stats.rx_length_errors },
18984+ { OID_SKGE_STAT_RX_FCS, &pAC->stats.rx_crc_errors },
18985+ { OID_SKGE_STAT_RX_FRAMING, &pAC->stats.rx_frame_errors },
18986+ { OID_SKGE_STAT_RX_OVERFLOW, &pAC->stats.rx_over_errors },
18987+ { OID_SKGE_STAT_RX_MISSED, &pAC->stats.rx_missed_errors },
18988+ { OID_SKGE_STAT_TX_CARRIER, &pAC->stats.tx_carrier_errors },
18989+ { OID_SKGE_STAT_TX_UNDERRUN, &pAC->stats.tx_fifo_errors },
18990+ };
18991+
18992+ if ((pAC->DiagModeActive == DIAG_NOTACTIVE) &&
18993+ (pAC->BoardLevel == SK_INIT_RUN)) {
18994+ memset(&pAC->stats, 0x00, sizeof(pAC->stats)); /* clean first */
18995+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
18996
18997-#ifdef SK_DIAG_SUPPORT
18998- if ((pAC->DiagModeActive == DIAG_NOTACTIVE) &&
18999- (pAC->BoardLevel == SK_INIT_RUN)) {
19000-#endif
19001- SK_MEMSET(pPnmiStruct, 0, sizeof(SK_PNMI_STRUCT_DATA));
19002- spin_lock_irqsave(&pAC->SlowPathLock, Flags);
19003- Size = SK_PNMI_STRUCT_SIZE;
19004- SkPnmiGetStruct(pAC, pAC->IoBase, pPnmiStruct, &Size, pNet->NetNr);
19005- spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
19006-#ifdef SK_DIAG_SUPPORT
19007- }
19008-#endif
19009+ MaxNumOidEntries = sizeof(Vars) / sizeof(Vars[0]);
19010+ for (Oid = 0; Oid < MaxNumOidEntries; Oid++) {
19011+ if (SkPnmiGetVar(pAC,pAC->IoBase, Vars[Oid].Oid,
19012+ &Buf, &Len, 1, pNet->NetNr) != SK_PNMI_ERR_OK) {
19013+ memset(Buf, 0x00, sizeof(Buf));
19014+ }
19015+ *Vars[Oid].pVar = (unsigned long) (*((SK_U64 *) Buf));
19016+ }
19017+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
19018
19019- pPnmiStat = &pPnmiStruct->Stat[0];
19020- pPnmiConf = &pPnmiStruct->Conf[0];
19021+ pAC->stats.collisions = LateCollisions + ExcessiveCollisions;
19022+ pAC->stats.tx_errors = pAC->stats.tx_carrier_errors +
19023+ pAC->stats.tx_fifo_errors;
19024+ pAC->stats.rx_errors = pAC->stats.rx_length_errors +
19025+ pAC->stats.rx_crc_errors +
19026+ pAC->stats.rx_frame_errors +
19027+ pAC->stats.rx_over_errors +
19028+ pAC->stats.rx_missed_errors;
19029
19030- pAC->stats.rx_packets = (SK_U32) pPnmiStruct->RxDeliveredCts & 0xFFFFFFFF;
19031- pAC->stats.tx_packets = (SK_U32) pPnmiStat->StatTxOkCts & 0xFFFFFFFF;
19032- pAC->stats.rx_bytes = (SK_U32) pPnmiStruct->RxOctetsDeliveredCts;
19033- pAC->stats.tx_bytes = (SK_U32) pPnmiStat->StatTxOctetsOkCts;
19034-
19035- if (dev->mtu <= 1500) {
19036- pAC->stats.rx_errors = (SK_U32) pPnmiStruct->InErrorsCts & 0xFFFFFFFF;
19037- } else {
19038- pAC->stats.rx_errors = (SK_U32) ((pPnmiStruct->InErrorsCts -
19039- pPnmiStat->StatRxTooLongCts) & 0xFFFFFFFF);
19040+ if (dev->mtu > 1500) {
19041+ pAC->stats.rx_errors = pAC->stats.rx_errors - RxTooLong;
19042+ }
19043 }
19044
19045-
19046- if (pAC->GIni.GP[0].PhyType == SK_PHY_XMAC && pAC->HWRevision < 12)
19047- pAC->stats.rx_errors = pAC->stats.rx_errors - pPnmiStat->StatRxShortsCts;
19048-
19049- pAC->stats.tx_errors = (SK_U32) pPnmiStat->StatTxSingleCollisionCts & 0xFFFFFFFF;
19050- pAC->stats.rx_dropped = (SK_U32) pPnmiStruct->RxNoBufCts & 0xFFFFFFFF;
19051- pAC->stats.tx_dropped = (SK_U32) pPnmiStruct->TxNoBufCts & 0xFFFFFFFF;
19052- pAC->stats.multicast = (SK_U32) pPnmiStat->StatRxMulticastOkCts & 0xFFFFFFFF;
19053- pAC->stats.collisions = (SK_U32) pPnmiStat->StatTxSingleCollisionCts & 0xFFFFFFFF;
19054-
19055- /* detailed rx_errors: */
19056- pAC->stats.rx_length_errors = (SK_U32) pPnmiStat->StatRxRuntCts & 0xFFFFFFFF;
19057- pAC->stats.rx_over_errors = (SK_U32) pPnmiStat->StatRxFifoOverflowCts & 0xFFFFFFFF;
19058- pAC->stats.rx_crc_errors = (SK_U32) pPnmiStat->StatRxFcsCts & 0xFFFFFFFF;
19059- pAC->stats.rx_frame_errors = (SK_U32) pPnmiStat->StatRxFramingCts & 0xFFFFFFFF;
19060- pAC->stats.rx_fifo_errors = (SK_U32) pPnmiStat->StatRxFifoOverflowCts & 0xFFFFFFFF;
19061- pAC->stats.rx_missed_errors = (SK_U32) pPnmiStat->StatRxMissedCts & 0xFFFFFFFF;
19062-
19063- /* detailed tx_errors */
19064- pAC->stats.tx_aborted_errors = (SK_U32) 0;
19065- pAC->stats.tx_carrier_errors = (SK_U32) pPnmiStat->StatTxCarrierCts & 0xFFFFFFFF;
19066- pAC->stats.tx_fifo_errors = (SK_U32) pPnmiStat->StatTxFifoUnderrunCts & 0xFFFFFFFF;
19067- pAC->stats.tx_heartbeat_errors = (SK_U32) pPnmiStat->StatTxCarrierCts & 0xFFFFFFFF;
19068- pAC->stats.tx_window_errors = (SK_U32) 0;
19069-
19070 return(&pAC->stats);
19071 } /* SkGeStats */
19072
19073-
19074 /*****************************************************************************
19075 *
19076 * SkGeIoctl - IO-control function
19077@@ -2851,38 +3952,41 @@
19078 * Description:
19079 * This function is called if an ioctl is issued on the device.
19080 * There are three subfunction for reading, writing and test-writing
19081- * the private MIB data structure (useful for SysKonnect-internal tools).
19082+ * the private MIB data structure (usefull for SysKonnect-internal tools).
19083 *
19084 * Returns:
19085 * 0, if everything is ok
19086 * !=0, on error
19087 */
19088-static int SkGeIoctl(struct SK_NET_DEVICE *dev, struct ifreq *rq, int cmd)
19089-{
19090-DEV_NET *pNet;
19091-SK_AC *pAC;
19092-void *pMemBuf;
19093-struct pci_dev *pdev = NULL;
19094-SK_GE_IOCTL Ioctl;
19095-unsigned int Err = 0;
19096-int Size = 0;
19097-int Ret = 0;
19098-unsigned int Length = 0;
19099-int HeaderLength = sizeof(SK_U32) + sizeof(SK_U32);
19100+static int SkGeIoctl(
19101+struct SK_NET_DEVICE *dev, /* the device the IOCTL is to be performed on */
19102+struct ifreq *rq, /* additional request structure containing data */
19103+int cmd) /* requested IOCTL command number */
19104+{
19105+ DEV_NET *pNet = (DEV_NET*) dev->priv;
19106+ SK_AC *pAC = pNet->pAC;
19107+ struct pci_dev *pdev = NULL;
19108+ void *pMemBuf;
19109+ SK_GE_IOCTL Ioctl;
19110+ unsigned long Flags; /* for spin lock */
19111+ unsigned int Err = 0;
19112+ unsigned int Length = 0;
19113+ int HeaderLength = sizeof(SK_U32) + sizeof(SK_U32);
19114+ int Size = 0;
19115+ int Ret = 0;
19116
19117 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
19118 ("SkGeIoctl starts now...\n"));
19119
19120- pNet = netdev_priv(dev);
19121- pAC = pNet->pAC;
19122-
19123 if(copy_from_user(&Ioctl, rq->ifr_data, sizeof(SK_GE_IOCTL))) {
19124 return -EFAULT;
19125 }
19126
19127 switch(cmd) {
19128- case SK_IOCTL_SETMIB:
19129- case SK_IOCTL_PRESETMIB:
19130+ case SIOCETHTOOL:
19131+ return SkEthIoctl(dev, rq);
19132+ case SK_IOCTL_SETMIB: /* FALL THRU */
19133+ case SK_IOCTL_PRESETMIB: /* FALL THRU (if capable!) */
19134 if (!capable(CAP_NET_ADMIN)) return -EPERM;
19135 case SK_IOCTL_GETMIB:
19136 if(copy_from_user(&pAC->PnmiStruct, Ioctl.pData,
19137@@ -2909,6 +4013,7 @@
19138 if (NULL == (pMemBuf = kmalloc(Length, GFP_KERNEL))) {
19139 return -ENOMEM;
19140 }
19141+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
19142 if(copy_from_user(pMemBuf, Ioctl.pData, Length)) {
19143 Err = -EFAULT;
19144 goto fault_gen;
19145@@ -2927,10 +4032,10 @@
19146 goto fault_gen;
19147 }
19148 fault_gen:
19149+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
19150 kfree(pMemBuf); /* cleanup everything */
19151 break;
19152-#ifdef SK_DIAG_SUPPORT
19153- case SK_IOCTL_DIAG:
19154+ case SK_IOCTL_DIAG:
19155 if (!capable(CAP_NET_ADMIN)) return -EPERM;
19156 if (Ioctl.Len < (sizeof(pAC->PnmiStruct) + HeaderLength)) {
19157 Length = Ioctl.Len;
19158@@ -2967,7 +4072,6 @@
19159 fault_diag:
19160 kfree(pMemBuf); /* cleanup everything */
19161 break;
19162-#endif
19163 default:
19164 Err = -EOPNOTSUPP;
19165 }
19166@@ -2999,12 +4103,12 @@
19167 unsigned int Size, /* length of ioctl data */
19168 int mode) /* flag for set/preset */
19169 {
19170-unsigned long Flags; /* for spin lock */
19171-SK_AC *pAC;
19172+ SK_AC *pAC = pNet->pAC;
19173+ unsigned long Flags; /* for spin lock */
19174
19175 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
19176 ("SkGeIocMib starts now...\n"));
19177- pAC = pNet->pAC;
19178+
19179 /* access MIB */
19180 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
19181 switch(mode) {
19182@@ -3047,17 +4151,18 @@
19183 SK_I32 Port; /* preferred port */
19184 SK_BOOL AutoSet;
19185 SK_BOOL DupSet;
19186-int LinkSpeed = SK_LSPEED_AUTO; /* Link speed */
19187-int AutoNeg = 1; /* autoneg off (0) or on (1) */
19188-int DuplexCap = 0; /* 0=both,1=full,2=half */
19189-int FlowCtrl = SK_FLOW_MODE_SYM_OR_REM; /* FlowControl */
19190-int MSMode = SK_MS_MODE_AUTO; /* master/slave mode */
19191-
19192-SK_BOOL IsConTypeDefined = SK_TRUE;
19193-SK_BOOL IsLinkSpeedDefined = SK_TRUE;
19194-SK_BOOL IsFlowCtrlDefined = SK_TRUE;
19195-SK_BOOL IsRoleDefined = SK_TRUE;
19196-SK_BOOL IsModeDefined = SK_TRUE;
19197+int LinkSpeed = SK_LSPEED_AUTO; /* Link speed */
19198+int AutoNeg = 1; /* autoneg off (0) or on (1) */
19199+int DuplexCap = 0; /* 0=both,1=full,2=half */
19200+int FlowCtrl = SK_FLOW_MODE_SYM_OR_REM; /* FlowControl */
19201+int MSMode = SK_MS_MODE_AUTO; /* master/slave mode */
19202+int IrqModMaskOffset = 6; /* all ints moderated=default */
19203+
19204+SK_BOOL IsConTypeDefined = SK_TRUE;
19205+SK_BOOL IsLinkSpeedDefined = SK_TRUE;
19206+SK_BOOL IsFlowCtrlDefined = SK_TRUE;
19207+SK_BOOL IsRoleDefined = SK_TRUE;
19208+SK_BOOL IsModeDefined = SK_TRUE;
19209 /*
19210 * The two parameters AutoNeg. and DuplexCap. map to one configuration
19211 * parameter. The mapping is described by this table:
19212@@ -3075,6 +4180,15 @@
19213 {SK_LMODE_AUTOBOTH , SK_LMODE_AUTOFULL , SK_LMODE_AUTOHALF },
19214 {SK_LMODE_AUTOSENSE, SK_LMODE_AUTOSENSE, SK_LMODE_AUTOSENSE} };
19215
19216+SK_U32 IrqModMask[7][2] =
19217+ { { IRQ_MASK_RX_ONLY , Y2_DRIVER_IRQS },
19218+ { IRQ_MASK_TX_ONLY , Y2_DRIVER_IRQS },
19219+ { IRQ_MASK_SP_ONLY , Y2_SPECIAL_IRQS },
19220+ { IRQ_MASK_SP_RX , Y2_IRQ_MASK },
19221+ { IRQ_MASK_TX_RX , Y2_DRIVER_IRQS },
19222+ { IRQ_MASK_SP_TX , Y2_IRQ_MASK },
19223+ { IRQ_MASK_RX_TX_SP, Y2_IRQ_MASK } };
19224+
19225 #define DC_BOTH 0
19226 #define DC_FULL 1
19227 #define DC_HALF 2
19228@@ -3114,7 +4228,7 @@
19229 **
19230 ** This ConType parameter is used for all ports of the adapter!
19231 */
19232- if ( (ConType != NULL) &&
19233+ if ( (ConType != NULL) &&
19234 (pAC->Index < SK_MAX_CARD_PARAM) &&
19235 (ConType[pAC->Index] != NULL) ) {
19236
19237@@ -3140,40 +4254,40 @@
19238 M_CurrPort.PMSMode = SK_MS_MODE_AUTO;
19239 M_CurrPort.PLinkSpeed = SK_LSPEED_AUTO;
19240 }
19241- } else if (strcmp(ConType[pAC->Index],"100FD")==0) {
19242+ } else if (strcmp(ConType[pAC->Index],"100FD")==0) {
19243 for (Port = 0; Port < SK_MAX_MACS; Port++) {
19244 M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_FULL];
19245 M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE;
19246 M_CurrPort.PMSMode = SK_MS_MODE_AUTO;
19247 M_CurrPort.PLinkSpeed = SK_LSPEED_100MBPS;
19248 }
19249- } else if (strcmp(ConType[pAC->Index],"100HD")==0) {
19250+ } else if (strcmp(ConType[pAC->Index],"100HD")==0) {
19251 for (Port = 0; Port < SK_MAX_MACS; Port++) {
19252 M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_HALF];
19253 M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE;
19254 M_CurrPort.PMSMode = SK_MS_MODE_AUTO;
19255 M_CurrPort.PLinkSpeed = SK_LSPEED_100MBPS;
19256 }
19257- } else if (strcmp(ConType[pAC->Index],"10FD")==0) {
19258+ } else if (strcmp(ConType[pAC->Index],"10FD")==0) {
19259 for (Port = 0; Port < SK_MAX_MACS; Port++) {
19260 M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_FULL];
19261 M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE;
19262 M_CurrPort.PMSMode = SK_MS_MODE_AUTO;
19263 M_CurrPort.PLinkSpeed = SK_LSPEED_10MBPS;
19264 }
19265- } else if (strcmp(ConType[pAC->Index],"10HD")==0) {
19266+ } else if (strcmp(ConType[pAC->Index],"10HD")==0) {
19267 for (Port = 0; Port < SK_MAX_MACS; Port++) {
19268 M_CurrPort.PLinkModeConf = Capabilities[AN_OFF][DC_HALF];
19269 M_CurrPort.PFlowCtrlMode = SK_FLOW_MODE_NONE;
19270 M_CurrPort.PMSMode = SK_MS_MODE_AUTO;
19271 M_CurrPort.PLinkSpeed = SK_LSPEED_10MBPS;
19272 }
19273- } else {
19274+ } else {
19275 printk("sk98lin: Illegal value \"%s\" for ConType\n",
19276 ConType[pAC->Index]);
19277 IsConTypeDefined = SK_FALSE; /* Wrong ConType defined */
19278 }
19279- } else {
19280+ } else {
19281 IsConTypeDefined = SK_FALSE; /* No ConType defined */
19282 }
19283
19284@@ -3192,14 +4306,30 @@
19285 } else if (strcmp(Speed_A[pAC->Index],"100")==0) {
19286 LinkSpeed = SK_LSPEED_100MBPS;
19287 } else if (strcmp(Speed_A[pAC->Index],"1000")==0) {
19288- LinkSpeed = SK_LSPEED_1000MBPS;
19289+ if ((pAC->PciDev->vendor == 0x11ab ) &&
19290+ (pAC->PciDev->device == 0x4350)) {
19291+ LinkSpeed = SK_LSPEED_100MBPS;
19292+ printk("sk98lin: Illegal value \"%s\" for Speed_A.\n"
19293+ "Gigabit speed not possible with this chip revision!",
19294+ Speed_A[pAC->Index]);
19295+ } else {
19296+ LinkSpeed = SK_LSPEED_1000MBPS;
19297+ }
19298 } else {
19299 printk("sk98lin: Illegal value \"%s\" for Speed_A\n",
19300 Speed_A[pAC->Index]);
19301 IsLinkSpeedDefined = SK_FALSE;
19302 }
19303 } else {
19304- IsLinkSpeedDefined = SK_FALSE;
19305+ if ((pAC->PciDev->vendor == 0x11ab ) &&
19306+ (pAC->PciDev->device == 0x4350)) {
19307+ /* Gigabit speed not supported
19308+ * Swith to speed 100
19309+ */
19310+ LinkSpeed = SK_LSPEED_100MBPS;
19311+ } else {
19312+ IsLinkSpeedDefined = SK_FALSE;
19313+ }
19314 }
19315
19316 /*
19317@@ -3294,9 +4424,6 @@
19318 }
19319
19320 if (!AutoSet && DupSet) {
19321- printk("sk98lin: Port A: Duplex setting not"
19322- " possible in\n default AutoNegotiation mode"
19323- " (Sense).\n Using AutoNegotiation On\n");
19324 AutoNeg = AN_ON;
19325 }
19326
19327@@ -3324,7 +4451,7 @@
19328 FlowCtrl = SK_FLOW_MODE_NONE;
19329 } else {
19330 printk("sk98lin: Illegal value \"%s\" for FlowCtrl_A\n",
19331- FlowCtrl_A[pAC->Index]);
19332+ FlowCtrl_A[pAC->Index]);
19333 IsFlowCtrlDefined = SK_FALSE;
19334 }
19335 } else {
19336@@ -3416,7 +4543,7 @@
19337 ** Decide whether to set new config value if somethig valid has
19338 ** been received.
19339 */
19340- if (IsLinkSpeedDefined) {
19341+ if (IsLinkSpeedDefined) {
19342 pAC->GIni.GP[1].PLinkSpeed = LinkSpeed;
19343 }
19344
19345@@ -3492,9 +4619,6 @@
19346 }
19347
19348 if (!AutoSet && DupSet) {
19349- printk("sk98lin: Port B: Duplex setting not"
19350- " possible in\n default AutoNegotiation mode"
19351- " (Sense).\n Using AutoNegotiation On\n");
19352 AutoNeg = AN_ON;
19353 }
19354
19355@@ -3607,11 +4731,15 @@
19356 }
19357
19358 pAC->RlmtNets = 1;
19359+ pAC->RlmtMode = 0;
19360
19361 if (RlmtMode != NULL && pAC->Index<SK_MAX_CARD_PARAM &&
19362 RlmtMode[pAC->Index] != NULL) {
19363 if (strcmp(RlmtMode[pAC->Index], "") == 0) {
19364- pAC->RlmtMode = 0;
19365+ if (pAC->GIni.GIMacsFound == 2) {
19366+ pAC->RlmtMode = SK_RLMT_CHECK_LINK;
19367+ pAC->RlmtNets = 2;
19368+ }
19369 } else if (strcmp(RlmtMode[pAC->Index], "CheckLinkState") == 0) {
19370 pAC->RlmtMode = SK_RLMT_CHECK_LINK;
19371 } else if (strcmp(RlmtMode[pAC->Index], "CheckLocalPort") == 0) {
19372@@ -3632,12 +4760,37 @@
19373 pAC->RlmtMode = 0;
19374 }
19375 } else {
19376- pAC->RlmtMode = 0;
19377+ if (pAC->GIni.GIMacsFound == 2) {
19378+ pAC->RlmtMode = SK_RLMT_CHECK_LINK;
19379+ pAC->RlmtNets = 2;
19380+ }
19381 }
19382-
19383+
19384+#ifdef SK_YUKON2
19385+ /*
19386+ ** use dualnet config per default
19387+ *
19388+ pAC->RlmtMode = SK_RLMT_CHECK_LINK;
19389+ pAC->RlmtNets = 2;
19390+ */
19391+#endif
19392+
19393+
19394+ /*
19395+ ** Check the LowLatance parameters
19396+ */
19397+ pAC->LowLatency = SK_FALSE;
19398+ if (LowLatency[pAC->Index] != NULL) {
19399+ if (strcmp(LowLatency[pAC->Index], "On") == 0) {
19400+ pAC->LowLatency = SK_TRUE;
19401+ }
19402+ }
19403+
19404+
19405 /*
19406 ** Check the interrupt moderation parameters
19407 */
19408+ pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_NONE;
19409 if (Moderation[pAC->Index] != NULL) {
19410 if (strcmp(Moderation[pAC->Index], "") == 0) {
19411 pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_NONE;
19412@@ -3651,70 +4804,49 @@
19413 printk("sk98lin: Illegal value \"%s\" for Moderation.\n"
19414 " Disable interrupt moderation.\n",
19415 Moderation[pAC->Index]);
19416- pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_NONE;
19417- }
19418- } else {
19419- pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_NONE;
19420- }
19421-
19422- if (Stats[pAC->Index] != NULL) {
19423- if (strcmp(Stats[pAC->Index], "Yes") == 0) {
19424- pAC->DynIrqModInfo.DisplayStats = SK_TRUE;
19425- } else {
19426- pAC->DynIrqModInfo.DisplayStats = SK_FALSE;
19427 }
19428 } else {
19429- pAC->DynIrqModInfo.DisplayStats = SK_FALSE;
19430+/* Set interrupt moderation if wished */
19431+#ifdef CONFIG_SK98LIN_STATINT
19432+ pAC->DynIrqModInfo.IntModTypeSelect = C_INT_MOD_STATIC;
19433+#endif
19434 }
19435
19436 if (ModerationMask[pAC->Index] != NULL) {
19437 if (strcmp(ModerationMask[pAC->Index], "Rx") == 0) {
19438- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_ONLY;
19439+ IrqModMaskOffset = 0;
19440 } else if (strcmp(ModerationMask[pAC->Index], "Tx") == 0) {
19441- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_TX_ONLY;
19442+ IrqModMaskOffset = 1;
19443 } else if (strcmp(ModerationMask[pAC->Index], "Sp") == 0) {
19444- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_SP_ONLY;
19445+ IrqModMaskOffset = 2;
19446 } else if (strcmp(ModerationMask[pAC->Index], "RxSp") == 0) {
19447- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_SP_RX;
19448+ IrqModMaskOffset = 3;
19449 } else if (strcmp(ModerationMask[pAC->Index], "SpRx") == 0) {
19450- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_SP_RX;
19451+ IrqModMaskOffset = 3;
19452 } else if (strcmp(ModerationMask[pAC->Index], "RxTx") == 0) {
19453- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_TX_RX;
19454+ IrqModMaskOffset = 4;
19455 } else if (strcmp(ModerationMask[pAC->Index], "TxRx") == 0) {
19456- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_TX_RX;
19457+ IrqModMaskOffset = 4;
19458 } else if (strcmp(ModerationMask[pAC->Index], "TxSp") == 0) {
19459- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_SP_TX;
19460+ IrqModMaskOffset = 5;
19461 } else if (strcmp(ModerationMask[pAC->Index], "SpTx") == 0) {
19462- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_SP_TX;
19463- } else if (strcmp(ModerationMask[pAC->Index], "RxTxSp") == 0) {
19464- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP;
19465- } else if (strcmp(ModerationMask[pAC->Index], "RxSpTx") == 0) {
19466- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP;
19467- } else if (strcmp(ModerationMask[pAC->Index], "TxRxSp") == 0) {
19468- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP;
19469- } else if (strcmp(ModerationMask[pAC->Index], "TxSpRx") == 0) {
19470- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP;
19471- } else if (strcmp(ModerationMask[pAC->Index], "SpTxRx") == 0) {
19472- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP;
19473- } else if (strcmp(ModerationMask[pAC->Index], "SpRxTx") == 0) {
19474- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_TX_SP;
19475- } else { /* some rubbish */
19476- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_RX_ONLY;
19477- }
19478- } else { /* operator has stated nothing */
19479- pAC->DynIrqModInfo.MaskIrqModeration = IRQ_MASK_TX_RX;
19480- }
19481-
19482- if (AutoSizing[pAC->Index] != NULL) {
19483- if (strcmp(AutoSizing[pAC->Index], "On") == 0) {
19484- pAC->DynIrqModInfo.AutoSizing = SK_FALSE;
19485- } else {
19486- pAC->DynIrqModInfo.AutoSizing = SK_FALSE;
19487+ IrqModMaskOffset = 5;
19488+ } else { /* some rubbish stated */
19489+ // IrqModMaskOffset = 6; ->has been initialized
19490+ // already at the begin of this function...
19491 }
19492- } else { /* operator has stated nothing */
19493- pAC->DynIrqModInfo.AutoSizing = SK_FALSE;
19494+ }
19495+ if (!CHIP_ID_YUKON_2(pAC)) {
19496+ pAC->DynIrqModInfo.MaskIrqModeration = IrqModMask[IrqModMaskOffset][0];
19497+ } else {
19498+ pAC->DynIrqModInfo.MaskIrqModeration = IrqModMask[IrqModMaskOffset][1];
19499 }
19500
19501+ if (!CHIP_ID_YUKON_2(pAC)) {
19502+ pAC->DynIrqModInfo.MaxModIntsPerSec = C_INTS_PER_SEC_DEFAULT;
19503+ } else {
19504+ pAC->DynIrqModInfo.MaxModIntsPerSec = C_Y2_INTS_PER_SEC_DEFAULT;
19505+ }
19506 if (IntsPerSec[pAC->Index] != 0) {
19507 if ((IntsPerSec[pAC->Index]< C_INT_MOD_IPS_LOWER_RANGE) ||
19508 (IntsPerSec[pAC->Index] > C_INT_MOD_IPS_UPPER_RANGE)) {
19509@@ -3723,28 +4855,25 @@
19510 IntsPerSec[pAC->Index],
19511 C_INT_MOD_IPS_LOWER_RANGE,
19512 C_INT_MOD_IPS_UPPER_RANGE,
19513- C_INTS_PER_SEC_DEFAULT);
19514- pAC->DynIrqModInfo.MaxModIntsPerSec = C_INTS_PER_SEC_DEFAULT;
19515+ pAC->DynIrqModInfo.MaxModIntsPerSec);
19516 } else {
19517 pAC->DynIrqModInfo.MaxModIntsPerSec = IntsPerSec[pAC->Index];
19518 }
19519- } else {
19520- pAC->DynIrqModInfo.MaxModIntsPerSec = C_INTS_PER_SEC_DEFAULT;
19521- }
19522+ }
19523
19524 /*
19525 ** Evaluate upper and lower moderation threshold
19526 */
19527 pAC->DynIrqModInfo.MaxModIntsPerSecUpperLimit =
19528 pAC->DynIrqModInfo.MaxModIntsPerSec +
19529- (pAC->DynIrqModInfo.MaxModIntsPerSec / 2);
19530+ (pAC->DynIrqModInfo.MaxModIntsPerSec / 5);
19531
19532 pAC->DynIrqModInfo.MaxModIntsPerSecLowerLimit =
19533 pAC->DynIrqModInfo.MaxModIntsPerSec -
19534- (pAC->DynIrqModInfo.MaxModIntsPerSec / 2);
19535-
19536- pAC->DynIrqModInfo.PrevTimeVal = jiffies; /* initial value */
19537+ (pAC->DynIrqModInfo.MaxModIntsPerSec / 5);
19538
19539+ pAC->DynIrqModInfo.DynIrqModSampleInterval =
19540+ SK_DRV_MODERATION_TIMER_LENGTH;
19541
19542 } /* GetConfiguration */
19543
19544@@ -3759,62 +4888,22 @@
19545 *
19546 * Returns: N/A
19547 */
19548-static inline int ProductStr(
19549- SK_AC *pAC, /* pointer to adapter context */
19550- char *DeviceStr, /* result string */
19551- int StrLen /* length of the string */
19552-)
19553+static void ProductStr(SK_AC *pAC)
19554 {
19555-char Keyword[] = VPD_NAME; /* vpd productname identifier */
19556-int ReturnCode; /* return code from vpd_read */
19557-unsigned long Flags;
19558+ char Default[] = "Generic Marvell Yukon chipset Ethernet device";
19559+ char Key[] = VPD_NAME; /* VPD productname key */
19560+ int StrLen = 80; /* stringlen */
19561+ unsigned long Flags;
19562
19563 spin_lock_irqsave(&pAC->SlowPathLock, Flags);
19564- ReturnCode = VpdRead(pAC, pAC->IoBase, Keyword, DeviceStr, &StrLen);
19565+ if (VpdRead(pAC, pAC->IoBase, Key, pAC->DeviceStr, &StrLen)) {
19566+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ERROR,
19567+ ("Error reading VPD data: %d\n", ReturnCode));
19568+ strcpy(pAC->DeviceStr, Default);
19569+ }
19570 spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
19571-
19572- return ReturnCode;
19573 } /* ProductStr */
19574
19575-/*****************************************************************************
19576- *
19577- * StartDrvCleanupTimer - Start timer to check for descriptors which
19578- * might be placed in descriptor ring, but
19579- * havent been handled up to now
19580- *
19581- * Description:
19582- * This function requests a HW-timer fo the Yukon card. The actions to
19583- * perform when this timer expires, are located in the SkDrvEvent().
19584- *
19585- * Returns: N/A
19586- */
19587-static void
19588-StartDrvCleanupTimer(SK_AC *pAC) {
19589- SK_EVPARA EventParam; /* Event struct for timer event */
19590-
19591- SK_MEMSET((char *) &EventParam, 0, sizeof(EventParam));
19592- EventParam.Para32[0] = SK_DRV_RX_CLEANUP_TIMER;
19593- SkTimerStart(pAC, pAC->IoBase, &pAC->DrvCleanupTimer,
19594- SK_DRV_RX_CLEANUP_TIMER_LENGTH,
19595- SKGE_DRV, SK_DRV_TIMER, EventParam);
19596-}
19597-
19598-/*****************************************************************************
19599- *
19600- * StopDrvCleanupTimer - Stop timer to check for descriptors
19601- *
19602- * Description:
19603- * This function requests a HW-timer fo the Yukon card. The actions to
19604- * perform when this timer expires, are located in the SkDrvEvent().
19605- *
19606- * Returns: N/A
19607- */
19608-static void
19609-StopDrvCleanupTimer(SK_AC *pAC) {
19610- SkTimerStop(pAC, pAC->IoBase, &pAC->DrvCleanupTimer);
19611- SK_MEMSET((char *) &pAC->DrvCleanupTimer, 0, sizeof(SK_TIMER));
19612-}
19613-
19614 /****************************************************************************/
19615 /* functions for common modules *********************************************/
19616 /****************************************************************************/
19617@@ -3903,7 +4992,9 @@
19618 SK_U64 SkOsGetTime(SK_AC *pAC)
19619 {
19620 SK_U64 PrivateJiffies;
19621+
19622 SkOsGetTimeCurrent(pAC, &PrivateJiffies);
19623+
19624 return PrivateJiffies;
19625 } /* SkOsGetTime */
19626
19627@@ -3976,6 +5067,28 @@
19628
19629 /*****************************************************************************
19630 *
19631+ * SkPciWriteCfgDWord - write a 32 bit value to pci config space
19632+ *
19633+ * Description:
19634+ * This routine writes a 32 bit value to the pci configuration
19635+ * space.
19636+ *
19637+ * Returns:
19638+ * 0 - indicate everything worked ok.
19639+ * != 0 - error indication
19640+ */
19641+int SkPciWriteCfgDWord(
19642+SK_AC *pAC, /* Adapter Control structure pointer */
19643+int PciAddr, /* PCI register address */
19644+SK_U32 Val) /* pointer to store the read value */
19645+{
19646+ pci_write_config_dword(pAC->PciDev, PciAddr, Val);
19647+ return(0);
19648+} /* SkPciWriteCfgDWord */
19649+
19650+
19651+/*****************************************************************************
19652+ *
19653 * SkPciWriteCfgWord - write a 16 bit value to pci config space
19654 *
19655 * Description:
19656@@ -4036,29 +5149,27 @@
19657 *
19658 */
19659 int SkDrvEvent(
19660-SK_AC *pAC, /* pointer to adapter context */
19661-SK_IOC IoC, /* io-context */
19662-SK_U32 Event, /* event-id */
19663-SK_EVPARA Param) /* event-parameter */
19664-{
19665-SK_MBUF *pRlmtMbuf; /* pointer to a rlmt-mbuf structure */
19666-struct sk_buff *pMsg; /* pointer to a message block */
19667-int FromPort; /* the port from which we switch away */
19668-int ToPort; /* the port we switch to */
19669-SK_EVPARA NewPara; /* parameter for further events */
19670-int Stat;
19671-unsigned long Flags;
19672-SK_BOOL DualNet;
19673+SK_AC *pAC, /* pointer to adapter context */
19674+SK_IOC IoC, /* IO control context */
19675+SK_U32 Event, /* event-id */
19676+SK_EVPARA Param) /* event-parameter */
19677+{
19678+ SK_MBUF *pRlmtMbuf; /* pointer to a rlmt-mbuf structure */
19679+ struct sk_buff *pMsg; /* pointer to a message block */
19680+ SK_BOOL DualNet;
19681+ SK_U32 Reason;
19682+ unsigned long Flags;
19683+ unsigned long InitFlags;
19684+ int FromPort; /* the port from which we switch away */
19685+ int ToPort; /* the port we switch to */
19686+ int Stat;
19687+ DEV_NET *pNet = NULL;
19688+#ifdef CONFIG_SK98LIN_NAPI
19689+ int WorkToDo = 1; /* min(*budget, dev->quota); */
19690+ int WorkDone = 0;
19691+#endif
19692
19693 switch (Event) {
19694- case SK_DRV_ADAP_FAIL:
19695- SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
19696- ("ADAPTER FAIL EVENT\n"));
19697- printk("%s: Adapter failed.\n", pAC->dev[0]->name);
19698- /* disable interrupts */
19699- SK_OUT32(pAC->IoBase, B0_IMSK, 0);
19700- /* cgoos */
19701- break;
19702 case SK_DRV_PORT_FAIL:
19703 FromPort = Param.Para32[0];
19704 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
19705@@ -4068,210 +5179,296 @@
19706 } else {
19707 printk("%s: Port B failed.\n", pAC->dev[1]->name);
19708 }
19709- /* cgoos */
19710 break;
19711- case SK_DRV_PORT_RESET: /* SK_U32 PortIdx */
19712- /* action list 4 */
19713+ case SK_DRV_PORT_RESET:
19714 FromPort = Param.Para32[0];
19715 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
19716 ("PORT RESET EVENT, Port: %d ", FromPort));
19717- NewPara.Para64 = FromPort;
19718- SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_XMAC_RESET, NewPara);
19719+ SkLocalEventQueue64(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET,
19720+ FromPort, SK_FALSE);
19721 spin_lock_irqsave(
19722 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
19723 Flags);
19724-
19725- SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_HARD_RST);
19726- netif_carrier_off(pAC->dev[Param.Para32[0]]);
19727+ if (CHIP_ID_YUKON_2(pAC)) {
19728+ SkY2PortStop(pAC, IoC, FromPort, SK_STOP_ALL, SK_HARD_RST);
19729+ } else {
19730+ SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_HARD_RST);
19731+ }
19732+ pAC->dev[Param.Para32[0]]->flags &= ~IFF_RUNNING;
19733 spin_unlock_irqrestore(
19734 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
19735 Flags);
19736
19737- /* clear rx ring from received frames */
19738- ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE);
19739-
19740- ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
19741+ if (!CHIP_ID_YUKON_2(pAC)) {
19742+#ifdef CONFIG_SK98LIN_NAPI
19743+ WorkToDo = 1;
19744+ ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE, &WorkDone, WorkToDo);
19745+#else
19746+ ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE);
19747+#endif
19748+ ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
19749+ }
19750 spin_lock_irqsave(
19751 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
19752 Flags);
19753-
19754- /* tschilling: Handling of return value inserted. */
19755- if (SkGeInitPort(pAC, IoC, FromPort)) {
19756- if (FromPort == 0) {
19757- printk("%s: SkGeInitPort A failed.\n", pAC->dev[0]->name);
19758+
19759+#ifdef USE_TIST_FOR_RESET
19760+ if (pAC->GIni.GIYukon2) {
19761+#ifdef Y2_RECOVERY
19762+ /* for Yukon II we want to have tist enabled all the time */
19763+ if (!SK_ADAPTER_WAITING_FOR_TIST(pAC)) {
19764+ Y2_ENABLE_TIST(pAC->IoBase);
19765+ }
19766+#else
19767+ /* make sure that we do not accept any status LEs from now on */
19768+ if (SK_ADAPTER_WAITING_FOR_TIST(pAC)) {
19769+#endif
19770+ /* port already waiting for tist */
19771+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
19772+ ("Port %c is now waiting for specific Tist\n",
19773+ 'A' + FromPort));
19774+ SK_SET_WAIT_BIT_FOR_PORT(
19775+ pAC,
19776+ SK_PSTATE_WAITING_FOR_SPECIFIC_TIST,
19777+ FromPort);
19778+ /* get current timestamp */
19779+ Y2_GET_TIST_LOW_VAL(pAC->IoBase, &pAC->MinTistLo);
19780+ pAC->MinTistHi = pAC->GIni.GITimeStampCnt;
19781+#ifndef Y2_RECOVERY
19782 } else {
19783- printk("%s: SkGeInitPort B failed.\n", pAC->dev[1]->name);
19784+ /* nobody is waiting yet */
19785+ SK_SET_WAIT_BIT_FOR_PORT(
19786+ pAC,
19787+ SK_PSTATE_WAITING_FOR_ANY_TIST,
19788+ FromPort);
19789+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
19790+ ("Port %c is now waiting for any Tist (0x%X)\n",
19791+ 'A' + FromPort, pAC->AdapterResetState));
19792+ /* start tist */
19793+ Y2_ENABLE_TIST(pAC-IoBase);
19794+ }
19795+#endif
19796+ }
19797+#endif
19798+
19799+#ifdef Y2_LE_CHECK
19800+ /* mark entries invalid */
19801+ pAC->LastPort = 3;
19802+ pAC->LastOpc = 0xFF;
19803+#endif
19804+ if (CHIP_ID_YUKON_2(pAC)) {
19805+ SkY2PortStart(pAC, IoC, FromPort);
19806+ } else {
19807+ /* tschilling: Handling of return value inserted. */
19808+ if (SkGeInitPort(pAC, IoC, FromPort)) {
19809+ if (FromPort == 0) {
19810+ printk("%s: SkGeInitPort A failed.\n", pAC->dev[0]->name);
19811+ } else {
19812+ printk("%s: SkGeInitPort B failed.\n", pAC->dev[1]->name);
19813+ }
19814 }
19815+ SkAddrMcUpdate(pAC,IoC, FromPort);
19816+ PortReInitBmu(pAC, FromPort);
19817+ SkGePollTxD(pAC, IoC, FromPort, SK_TRUE);
19818+ CLEAR_AND_START_RX(FromPort);
19819 }
19820- SkAddrMcUpdate(pAC,IoC, FromPort);
19821- PortReInitBmu(pAC, FromPort);
19822- SkGePollTxD(pAC, IoC, FromPort, SK_TRUE);
19823- ClearAndStartRx(pAC, FromPort);
19824 spin_unlock_irqrestore(
19825 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
19826 Flags);
19827 break;
19828- case SK_DRV_NET_UP: /* SK_U32 PortIdx */
19829- { struct net_device *dev = pAC->dev[Param.Para32[0]];
19830- /* action list 5 */
19831+ case SK_DRV_NET_UP:
19832+ spin_lock_irqsave(&pAC->InitLock, InitFlags);
19833 FromPort = Param.Para32[0];
19834 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
19835- ("NET UP EVENT, Port: %d ", Param.Para32[0]));
19836- /* Mac update */
19837- SkAddrMcUpdate(pAC,IoC, FromPort);
19838-
19839+ ("NET UP EVENT, Port: %d ", FromPort));
19840+ SkAddrMcUpdate(pAC,IoC, FromPort); /* Mac update */
19841 if (DoPrintInterfaceChange) {
19842- printk("%s: network connection up using"
19843- " port %c\n", pAC->dev[Param.Para32[0]]->name, 'A'+Param.Para32[0]);
19844+ printk("%s: network connection up using port %c\n",
19845+ pAC->dev[FromPort]->name, 'A'+FromPort);
19846
19847- /* tschilling: Values changed according to LinkSpeedUsed. */
19848- Stat = pAC->GIni.GP[FromPort].PLinkSpeedUsed;
19849- if (Stat == SK_LSPEED_STAT_10MBPS) {
19850- printk(" speed: 10\n");
19851- } else if (Stat == SK_LSPEED_STAT_100MBPS) {
19852- printk(" speed: 100\n");
19853- } else if (Stat == SK_LSPEED_STAT_1000MBPS) {
19854- printk(" speed: 1000\n");
19855- } else {
19856- printk(" speed: unknown\n");
19857- }
19858+ /* tschilling: Values changed according to LinkSpeedUsed. */
19859+ Stat = pAC->GIni.GP[FromPort].PLinkSpeedUsed;
19860+ if (Stat == SK_LSPEED_STAT_10MBPS) {
19861+ printk(" speed: 10\n");
19862+ } else if (Stat == SK_LSPEED_STAT_100MBPS) {
19863+ printk(" speed: 100\n");
19864+ } else if (Stat == SK_LSPEED_STAT_1000MBPS) {
19865+ printk(" speed: 1000\n");
19866+ } else {
19867+ printk(" speed: unknown\n");
19868+ }
19869
19870+ Stat = pAC->GIni.GP[FromPort].PLinkModeStatus;
19871+ if ((Stat == SK_LMODE_STAT_AUTOHALF) ||
19872+ (Stat == SK_LMODE_STAT_AUTOFULL)) {
19873+ printk(" autonegotiation: yes\n");
19874+ } else {
19875+ printk(" autonegotiation: no\n");
19876+ }
19877
19878- Stat = pAC->GIni.GP[FromPort].PLinkModeStatus;
19879- if (Stat == SK_LMODE_STAT_AUTOHALF ||
19880- Stat == SK_LMODE_STAT_AUTOFULL) {
19881- printk(" autonegotiation: yes\n");
19882- }
19883- else {
19884- printk(" autonegotiation: no\n");
19885- }
19886- if (Stat == SK_LMODE_STAT_AUTOHALF ||
19887- Stat == SK_LMODE_STAT_HALF) {
19888- printk(" duplex mode: half\n");
19889- }
19890- else {
19891- printk(" duplex mode: full\n");
19892- }
19893- Stat = pAC->GIni.GP[FromPort].PFlowCtrlStatus;
19894- if (Stat == SK_FLOW_STAT_REM_SEND ) {
19895- printk(" flowctrl: remote send\n");
19896- }
19897- else if (Stat == SK_FLOW_STAT_LOC_SEND ){
19898- printk(" flowctrl: local send\n");
19899- }
19900- else if (Stat == SK_FLOW_STAT_SYMMETRIC ){
19901- printk(" flowctrl: symmetric\n");
19902- }
19903- else {
19904- printk(" flowctrl: none\n");
19905- }
19906-
19907- /* tschilling: Check against CopperType now. */
19908- if ((pAC->GIni.GICopperType == SK_TRUE) &&
19909- (pAC->GIni.GP[FromPort].PLinkSpeedUsed ==
19910- SK_LSPEED_STAT_1000MBPS)) {
19911- Stat = pAC->GIni.GP[FromPort].PMSStatus;
19912- if (Stat == SK_MS_STAT_MASTER ) {
19913- printk(" role: master\n");
19914+ if ((Stat == SK_LMODE_STAT_AUTOHALF) ||
19915+ (Stat == SK_LMODE_STAT_HALF)) {
19916+ printk(" duplex mode: half\n");
19917+ } else {
19918+ printk(" duplex mode: full\n");
19919 }
19920- else if (Stat == SK_MS_STAT_SLAVE ) {
19921- printk(" role: slave\n");
19922+
19923+ Stat = pAC->GIni.GP[FromPort].PFlowCtrlStatus;
19924+ if (Stat == SK_FLOW_STAT_REM_SEND ) {
19925+ printk(" flowctrl: remote send\n");
19926+ } else if (Stat == SK_FLOW_STAT_LOC_SEND ) {
19927+ printk(" flowctrl: local send\n");
19928+ } else if (Stat == SK_FLOW_STAT_SYMMETRIC ) {
19929+ printk(" flowctrl: symmetric\n");
19930+ } else {
19931+ printk(" flowctrl: none\n");
19932 }
19933- else {
19934- printk(" role: ???\n");
19935+
19936+ /* tschilling: Check against CopperType now. */
19937+ if ((pAC->GIni.GICopperType == SK_TRUE) &&
19938+ (pAC->GIni.GP[FromPort].PLinkSpeedUsed ==
19939+ SK_LSPEED_STAT_1000MBPS)) {
19940+ Stat = pAC->GIni.GP[FromPort].PMSStatus;
19941+ if (Stat == SK_MS_STAT_MASTER ) {
19942+ printk(" role: master\n");
19943+ } else if (Stat == SK_MS_STAT_SLAVE ) {
19944+ printk(" role: slave\n");
19945+ } else {
19946+ printk(" role: ???\n");
19947+ }
19948 }
19949- }
19950
19951- /*
19952- Display dim (dynamic interrupt moderation)
19953- informations
19954- */
19955- if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_STATIC)
19956- printk(" irq moderation: static (%d ints/sec)\n",
19957+ /* Display interrupt moderation informations */
19958+ if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_STATIC) {
19959+ printk(" irq moderation: static (%d ints/sec)\n",
19960 pAC->DynIrqModInfo.MaxModIntsPerSec);
19961- else if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_DYNAMIC)
19962- printk(" irq moderation: dynamic (%d ints/sec)\n",
19963+ } else if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
19964+ printk(" irq moderation: dynamic (%d ints/sec)\n",
19965 pAC->DynIrqModInfo.MaxModIntsPerSec);
19966- else
19967- printk(" irq moderation: disabled\n");
19968+ } else {
19969+ printk(" irq moderation: disabled\n");
19970+ }
19971+
19972+#ifdef NETIF_F_TSO
19973+ if (CHIP_ID_YUKON_2(pAC)) {
19974+ if (pAC->dev[FromPort]->features & NETIF_F_TSO) {
19975+ printk(" tcp offload: enabled\n");
19976+ } else {
19977+ printk(" tcp offload: disabled\n");
19978+ }
19979+ }
19980+#endif
19981
19982+ if (pAC->dev[FromPort]->features & NETIF_F_SG) {
19983+ printk(" scatter-gather: enabled\n");
19984+ } else {
19985+ printk(" scatter-gather: disabled\n");
19986+ }
19987
19988- printk(" scatter-gather: %s\n",
19989- (dev->features & NETIF_F_SG) ? "enabled" : "disabled");
19990- printk(" tx-checksum: %s\n",
19991- (dev->features & NETIF_F_IP_CSUM) ? "enabled" : "disabled");
19992- printk(" rx-checksum: %s\n",
19993- pAC->RxPort[Param.Para32[0]].RxCsum ? "enabled" : "disabled");
19994+ if (pAC->dev[FromPort]->features & NETIF_F_IP_CSUM) {
19995+ printk(" tx-checksum: enabled\n");
19996+ } else {
19997+ printk(" tx-checksum: disabled\n");
19998+ }
19999
20000+ if (pAC->RxPort[FromPort].UseRxCsum) {
20001+ printk(" rx-checksum: enabled\n");
20002+ } else {
20003+ printk(" rx-checksum: disabled\n");
20004+ }
20005+#ifdef CONFIG_SK98LIN_NAPI
20006+ printk(" rx-polling: enabled\n");
20007+#endif
20008+ if (pAC->LowLatency) {
20009+ printk(" low latency: enabled\n");
20010+ }
20011 } else {
20012- DoPrintInterfaceChange = SK_TRUE;
20013- }
20014+ DoPrintInterfaceChange = SK_TRUE;
20015+ }
20016
20017- if ((Param.Para32[0] != pAC->ActivePort) &&
20018- (pAC->RlmtNets == 1)) {
20019- NewPara.Para32[0] = pAC->ActivePort;
20020- NewPara.Para32[1] = Param.Para32[0];
20021- SkEventQueue(pAC, SKGE_DRV, SK_DRV_SWITCH_INTERN,
20022- NewPara);
20023+ if ((FromPort != pAC->ActivePort)&&(pAC->RlmtNets == 1)) {
20024+ SkLocalEventQueue(pAC, SKGE_DRV, SK_DRV_SWITCH_INTERN,
20025+ pAC->ActivePort, FromPort, SK_FALSE);
20026 }
20027
20028 /* Inform the world that link protocol is up. */
20029- netif_carrier_on(dev);
20030+ netif_wake_queue(pAC->dev[FromPort]);
20031+ netif_carrier_on(pAC->dev[FromPort]);
20032+ pAC->dev[FromPort]->flags |= IFF_RUNNING;
20033+ spin_unlock_irqrestore(&pAC->InitLock, InitFlags);
20034 break;
20035- }
20036- case SK_DRV_NET_DOWN: /* SK_U32 Reason */
20037- /* action list 7 */
20038+ case SK_DRV_NET_DOWN:
20039+ Reason = Param.Para32[0];
20040+ FromPort = Param.Para32[1];
20041 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
20042 ("NET DOWN EVENT "));
20043+
20044+ /* Stop queue and carrier */
20045+ netif_stop_queue(pAC->dev[FromPort]);
20046+ netif_carrier_off(pAC->dev[FromPort]);
20047+
20048+ /* Print link change */
20049 if (DoPrintInterfaceChange) {
20050- printk("%s: network connection down\n",
20051- pAC->dev[Param.Para32[1]]->name);
20052+ if (pAC->dev[FromPort]->flags & IFF_RUNNING) {
20053+ printk("%s: network connection down\n",
20054+ pAC->dev[FromPort]->name);
20055+ }
20056 } else {
20057 DoPrintInterfaceChange = SK_TRUE;
20058 }
20059- netif_carrier_off(pAC->dev[Param.Para32[1]]);
20060+ pAC->dev[FromPort]->flags &= ~IFF_RUNNING;
20061 break;
20062- case SK_DRV_SWITCH_HARD: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */
20063- SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
20064- ("PORT SWITCH HARD "));
20065- case SK_DRV_SWITCH_SOFT: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */
20066- /* action list 6 */
20067- printk("%s: switching to port %c\n", pAC->dev[0]->name,
20068- 'A'+Param.Para32[1]);
20069- case SK_DRV_SWITCH_INTERN: /* SK_U32 FromPortIdx SK_U32 ToPortIdx */
20070+ case SK_DRV_SWITCH_HARD: /* FALL THRU */
20071+ case SK_DRV_SWITCH_SOFT: /* FALL THRU */
20072+ case SK_DRV_SWITCH_INTERN:
20073 FromPort = Param.Para32[0];
20074- ToPort = Param.Para32[1];
20075+ ToPort = Param.Para32[1];
20076+ printk("%s: switching from port %c to port %c\n",
20077+ pAC->dev[0]->name, 'A'+FromPort, 'A'+ToPort);
20078 SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
20079 ("PORT SWITCH EVENT, From: %d To: %d (Pref %d) ",
20080 FromPort, ToPort, pAC->Rlmt.Net[0].PrefPort));
20081- NewPara.Para64 = FromPort;
20082- SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_XMAC_RESET, NewPara);
20083- NewPara.Para64 = ToPort;
20084- SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_XMAC_RESET, NewPara);
20085+ SkLocalEventQueue64(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET,
20086+ FromPort, SK_FALSE);
20087+ SkLocalEventQueue64(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET,
20088+ ToPort, SK_FALSE);
20089 spin_lock_irqsave(
20090 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
20091 Flags);
20092 spin_lock(&pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock);
20093- SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST);
20094- SkGeStopPort(pAC, IoC, ToPort, SK_STOP_ALL, SK_SOFT_RST);
20095+ if (CHIP_ID_YUKON_2(pAC)) {
20096+ SkY2PortStop(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST);
20097+ SkY2PortStop(pAC, IoC, ToPort, SK_STOP_ALL, SK_SOFT_RST);
20098+ }
20099+ else {
20100+ SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST);
20101+ SkGeStopPort(pAC, IoC, ToPort, SK_STOP_ALL, SK_SOFT_RST);
20102+ }
20103 spin_unlock(&pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock);
20104 spin_unlock_irqrestore(
20105 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
20106 Flags);
20107
20108- ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE); /* clears rx ring */
20109- ReceiveIrq(pAC, &pAC->RxPort[ToPort], SK_FALSE); /* clears rx ring */
20110
20111- ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
20112- ClearTxRing(pAC, &pAC->TxPort[ToPort][TX_PRIO_LOW]);
20113+ if (!CHIP_ID_YUKON_2(pAC)) {
20114+#ifdef CONFIG_SK98LIN_NAPI
20115+ WorkToDo = 1;
20116+ ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE, &WorkDone, WorkToDo);
20117+ ReceiveIrq(pAC, &pAC->RxPort[ToPort], SK_FALSE, &WorkDone, WorkToDo);
20118+#else
20119+ ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE); /* clears rx ring */
20120+ ReceiveIrq(pAC, &pAC->RxPort[ToPort], SK_FALSE); /* clears rx ring */
20121+#endif
20122+ ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
20123+ ClearTxRing(pAC, &pAC->TxPort[ToPort][TX_PRIO_LOW]);
20124+ }
20125+
20126 spin_lock_irqsave(
20127 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
20128 Flags);
20129 spin_lock(&pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock);
20130 pAC->ActivePort = ToPort;
20131-#if 0
20132- SetQueueSizes(pAC);
20133-#else
20134+
20135 /* tschilling: New common function with minimum size check. */
20136 DualNet = SK_FALSE;
20137 if (pAC->RlmtNets == 2) {
20138@@ -4289,74 +5486,316 @@
20139 printk("SkGeInitAssignRamToQueues failed.\n");
20140 break;
20141 }
20142-#endif
20143- /* tschilling: Handling of return values inserted. */
20144- if (SkGeInitPort(pAC, IoC, FromPort) ||
20145- SkGeInitPort(pAC, IoC, ToPort)) {
20146- printk("%s: SkGeInitPort failed.\n", pAC->dev[0]->name);
20147+
20148+ if (!CHIP_ID_YUKON_2(pAC)) {
20149+ /* tschilling: Handling of return values inserted. */
20150+ if (SkGeInitPort(pAC, IoC, FromPort) ||
20151+ SkGeInitPort(pAC, IoC, ToPort)) {
20152+ printk("%s: SkGeInitPort failed.\n", pAC->dev[0]->name);
20153+ }
20154 }
20155- if (Event == SK_DRV_SWITCH_SOFT) {
20156- SkMacRxTxEnable(pAC, IoC, FromPort);
20157+ if (!CHIP_ID_YUKON_2(pAC)) {
20158+ if (Event == SK_DRV_SWITCH_SOFT) {
20159+ SkMacRxTxEnable(pAC, IoC, FromPort);
20160+ }
20161+ SkMacRxTxEnable(pAC, IoC, ToPort);
20162 }
20163- SkMacRxTxEnable(pAC, IoC, ToPort);
20164+
20165 SkAddrSwap(pAC, IoC, FromPort, ToPort);
20166 SkAddrMcUpdate(pAC, IoC, FromPort);
20167 SkAddrMcUpdate(pAC, IoC, ToPort);
20168- PortReInitBmu(pAC, FromPort);
20169- PortReInitBmu(pAC, ToPort);
20170- SkGePollTxD(pAC, IoC, FromPort, SK_TRUE);
20171- SkGePollTxD(pAC, IoC, ToPort, SK_TRUE);
20172- ClearAndStartRx(pAC, FromPort);
20173- ClearAndStartRx(pAC, ToPort);
20174+
20175+#ifdef USE_TIST_FOR_RESET
20176+ if (pAC->GIni.GIYukon2) {
20177+ /* make sure that we do not accept any status LEs from now on */
20178+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
20179+ ("both Ports now waiting for specific Tist\n"));
20180+ SK_SET_WAIT_BIT_FOR_PORT(
20181+ pAC,
20182+ SK_PSTATE_WAITING_FOR_ANY_TIST,
20183+ 0);
20184+ SK_SET_WAIT_BIT_FOR_PORT(
20185+ pAC,
20186+ SK_PSTATE_WAITING_FOR_ANY_TIST,
20187+ 1);
20188+
20189+ /* start tist */
20190+ Y2_ENABLE_TIST(pAC->IoBase);
20191+ }
20192+#endif
20193+ if (!CHIP_ID_YUKON_2(pAC)) {
20194+ PortReInitBmu(pAC, FromPort);
20195+ PortReInitBmu(pAC, ToPort);
20196+ SkGePollTxD(pAC, IoC, FromPort, SK_TRUE);
20197+ SkGePollTxD(pAC, IoC, ToPort, SK_TRUE);
20198+ CLEAR_AND_START_RX(FromPort);
20199+ CLEAR_AND_START_RX(ToPort);
20200+ } else {
20201+ SkY2PortStart(pAC, IoC, FromPort);
20202+ SkY2PortStart(pAC, IoC, ToPort);
20203+#ifdef SK_YUKON2
20204+ /* in yukon-II always port 0 has to be started first */
20205+ // SkY2PortStart(pAC, IoC, 0);
20206+ // SkY2PortStart(pAC, IoC, 1);
20207+#endif
20208+ }
20209 spin_unlock(&pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock);
20210 spin_unlock_irqrestore(
20211 &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
20212 Flags);
20213 break;
20214 case SK_DRV_RLMT_SEND: /* SK_MBUF *pMb */
20215- SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
20216- ("RLS "));
20217+ SK_DBG_MSG(NULL,SK_DBGMOD_DRV,SK_DBGCAT_DRV_EVENT,("RLS "));
20218 pRlmtMbuf = (SK_MBUF*) Param.pParaPtr;
20219 pMsg = (struct sk_buff*) pRlmtMbuf->pOs;
20220 skb_put(pMsg, pRlmtMbuf->Length);
20221- if (XmitFrame(pAC, &pAC->TxPort[pRlmtMbuf->PortIdx][TX_PRIO_LOW],
20222- pMsg) < 0)
20223+ if (!CHIP_ID_YUKON_2(pAC)) {
20224+ if (XmitFrame(pAC, &pAC->TxPort[pRlmtMbuf->PortIdx][TX_PRIO_LOW],
20225+ pMsg) < 0) {
20226+ DEV_KFREE_SKB_ANY(pMsg);
20227+ }
20228+ } else {
20229+ if (SkY2RlmtSend(pAC, pRlmtMbuf->PortIdx, pMsg) < 0) {
20230+ DEV_KFREE_SKB_ANY(pMsg);
20231+ }
20232+ }
20233+ break;
20234+ case SK_DRV_TIMER:
20235+ if (Param.Para32[0] == SK_DRV_MODERATION_TIMER) {
20236+ /* check what IRQs are to be moderated */
20237+ SkDimStartModerationTimer(pAC);
20238+ SkDimModerate(pAC);
20239+ } else {
20240+ printk("Expiration of unknown timer\n");
20241+ }
20242+ break;
20243+ case SK_DRV_ADAP_FAIL:
20244+#if (!defined (Y2_RECOVERY) && !defined (Y2_LE_CHECK))
20245+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
20246+ ("ADAPTER FAIL EVENT\n"));
20247+ printk("%s: Adapter failed.\n", pAC->dev[0]->name);
20248+ SK_OUT32(pAC->IoBase, B0_IMSK, 0); /* disable interrupts */
20249+ break;
20250+#endif
20251+
20252+#if (defined (Y2_RECOVERY) || defined (Y2_LE_CHECK))
20253+ case SK_DRV_RECOVER:
20254+ spin_lock_irqsave(&pAC->InitLock, InitFlags);
20255+ pNet = (DEV_NET *) pAC->dev[Param.Para32[0]]->priv;
20256+
20257+ /* Recover already in progress */
20258+ if (pNet->InRecover) {
20259+ break;
20260+ }
20261+
20262+ netif_stop_queue(pAC->dev[Param.Para32[0]]); /* stop device if running */
20263+ pNet->InRecover = SK_TRUE;
20264+
20265+ FromPort = Param.Para32[0];
20266+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
20267+ ("PORT RESET EVENT, Port: %d ", FromPort));
20268+
20269+ /* Disable interrupts */
20270+ SK_OUT32(pAC->IoBase, B0_IMSK, 0);
20271+ SK_OUT32(pAC->IoBase, B0_HWE_IMSK, 0);
20272+
20273+ SkLocalEventQueue64(pAC, SKGE_PNMI, SK_PNMI_EVT_XMAC_RESET,
20274+ FromPort, SK_FALSE);
20275+ spin_lock_irqsave(
20276+ &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
20277+ Flags);
20278+ if (CHIP_ID_YUKON_2(pAC)) {
20279+ SkY2PortStop(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST);
20280+ } else {
20281+ SkGeStopPort(pAC, IoC, FromPort, SK_STOP_ALL, SK_SOFT_RST);
20282+ }
20283+ pAC->dev[Param.Para32[0]]->flags &= ~IFF_RUNNING;
20284+ spin_unlock_irqrestore(
20285+ &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
20286+ Flags);
20287+
20288+ if (!CHIP_ID_YUKON_2(pAC)) {
20289+#ifdef CONFIG_SK98LIN_NAPI
20290+ WorkToDo = 1;
20291+ ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE, &WorkDone, WorkToDo);
20292+#else
20293+ ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE);
20294+#endif
20295+ ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
20296+ }
20297+ spin_lock_irqsave(
20298+ &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
20299+ Flags);
20300+
20301+#ifdef USE_TIST_FOR_RESET
20302+ if (pAC->GIni.GIYukon2) {
20303+#if 0
20304+ /* make sure that we do not accept any status LEs from now on */
20305+ Y2_ENABLE_TIST(pAC->IoBase);
20306+
20307+ /* get current timestamp */
20308+ Y2_GET_TIST_LOW_VAL(pAC->IoBase, &pAC->MinTistLo);
20309+ pAC->MinTistHi = pAC->GIni.GITimeStampCnt;
20310+
20311+ SK_SET_WAIT_BIT_FOR_PORT(
20312+ pAC,
20313+ SK_PSTATE_WAITING_FOR_SPECIFIC_TIST,
20314+ FromPort);
20315+#endif
20316+ SK_SET_WAIT_BIT_FOR_PORT(
20317+ pAC,
20318+ SK_PSTATE_WAITING_FOR_ANY_TIST,
20319+ FromPort);
20320+
20321+ /* start tist */
20322+ Y2_ENABLE_TIST(pAC->IoBase);
20323+ }
20324+#endif
20325+
20326+ /* Restart Receive BMU on Yukon-2 */
20327+ if (HW_FEATURE(pAC, HWF_WA_DEV_4167)) {
20328+ SkYuk2RestartRxBmu(pAC, IoC, FromPort);
20329+ }
20330+
20331+#ifdef Y2_LE_CHECK
20332+ /* mark entries invalid */
20333+ pAC->LastPort = 3;
20334+ pAC->LastOpc = 0xFF;
20335+#endif
20336+
20337+#endif
20338+ /* Restart ports but do not initialize PHY. */
20339+ if (CHIP_ID_YUKON_2(pAC)) {
20340+ SkY2PortStart(pAC, IoC, FromPort);
20341+ } else {
20342+ /* tschilling: Handling of return value inserted. */
20343+ if (SkGeInitPort(pAC, IoC, FromPort)) {
20344+ if (FromPort == 0) {
20345+ printk("%s: SkGeInitPort A failed.\n", pAC->dev[0]->name);
20346+ } else {
20347+ printk("%s: SkGeInitPort B failed.\n", pAC->dev[1]->name);
20348+ }
20349+ }
20350+ SkAddrMcUpdate(pAC,IoC, FromPort);
20351+ PortReInitBmu(pAC, FromPort);
20352+ SkGePollTxD(pAC, IoC, FromPort, SK_TRUE);
20353+ CLEAR_AND_START_RX(FromPort);
20354+ }
20355+ spin_unlock_irqrestore(
20356+ &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
20357+ Flags);
20358+
20359+ /* Map any waiting RX buffers to HW */
20360+ FillReceiveTableYukon2(pAC, pAC->IoBase, FromPort);
20361+
20362+ pNet->InRecover = SK_FALSE;
20363+ /* enable Interrupts */
20364+ SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
20365+ SK_OUT32(pAC->IoBase, B0_HWE_IMSK, IRQ_HWE_MASK);
20366+ netif_wake_queue(pAC->dev[FromPort]);
20367+ spin_unlock_irqrestore(&pAC->InitLock, InitFlags);
20368+ break;
20369+ default:
20370+ break;
20371+ }
20372+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
20373+ ("END EVENT "));
20374+
20375+ return (0);
20376+} /* SkDrvEvent */
20377+
20378+
20379+/******************************************************************************
20380+ *
20381+ * SkLocalEventQueue() - add event to queue
20382+ *
20383+ * Description:
20384+ * This function adds an event to the event queue and run the
20385+ * SkEventDispatcher. At least Init Level 1 is required to queue events,
20386+ * but will be scheduled add Init Level 2.
20387+ *
20388+ * returns:
20389+ * nothing
20390+ */
20391+void SkLocalEventQueue(
20392+SK_AC *pAC, /* Adapters context */
20393+SK_U32 Class, /* Event Class */
20394+SK_U32 Event, /* Event to be queued */
20395+SK_U32 Param1, /* Event parameter 1 */
20396+SK_U32 Param2, /* Event parameter 2 */
20397+SK_BOOL Dispatcher) /* Dispatcher flag:
20398+ * TRUE == Call SkEventDispatcher
20399+ * FALSE == Don't execute SkEventDispatcher
20400+ */
20401+{
20402+ SK_EVPARA EvPara;
20403+ EvPara.Para32[0] = Param1;
20404+ EvPara.Para32[1] = Param2;
20405+
20406+
20407+ if (Class == SKGE_PNMI) {
20408+ SkPnmiEvent( pAC,
20409+ pAC->IoBase,
20410+ Event,
20411+ EvPara);
20412+ } else {
20413+ SkEventQueue( pAC,
20414+ Class,
20415+ Event,
20416+ EvPara);
20417+ }
20418+
20419+ /* Run the dispatcher */
20420+ if (Dispatcher) {
20421+ SkEventDispatcher(pAC, pAC->IoBase);
20422+ }
20423+
20424+}
20425+
20426+/******************************************************************************
20427+ *
20428+ * SkLocalEventQueue64() - add event to queue (64bit version)
20429+ *
20430+ * Description:
20431+ * This function adds an event to the event queue and run the
20432+ * SkEventDispatcher. At least Init Level 1 is required to queue events,
20433+ * but will be scheduled add Init Level 2.
20434+ *
20435+ * returns:
20436+ * nothing
20437+ */
20438+void SkLocalEventQueue64(
20439+SK_AC *pAC, /* Adapters context */
20440+SK_U32 Class, /* Event Class */
20441+SK_U32 Event, /* Event to be queued */
20442+SK_U64 Param, /* Event parameter */
20443+SK_BOOL Dispatcher) /* Dispatcher flag:
20444+ * TRUE == Call SkEventDispatcher
20445+ * FALSE == Don't execute SkEventDispatcher
20446+ */
20447+{
20448+ SK_EVPARA EvPara;
20449+ EvPara.Para64 = Param;
20450+
20451+
20452+ if (Class == SKGE_PNMI) {
20453+ SkPnmiEvent( pAC,
20454+ pAC->IoBase,
20455+ Event,
20456+ EvPara);
20457+ } else {
20458+ SkEventQueue( pAC,
20459+ Class,
20460+ Event,
20461+ EvPara);
20462+ }
20463
20464- DEV_KFREE_SKB_ANY(pMsg);
20465- break;
20466- case SK_DRV_TIMER:
20467- if (Param.Para32[0] == SK_DRV_MODERATION_TIMER) {
20468- /*
20469- ** expiration of the moderation timer implies that
20470- ** dynamic moderation is to be applied
20471- */
20472- SkDimStartModerationTimer(pAC);
20473- SkDimModerate(pAC);
20474- if (pAC->DynIrqModInfo.DisplayStats) {
20475- SkDimDisplayModerationSettings(pAC);
20476- }
20477- } else if (Param.Para32[0] == SK_DRV_RX_CLEANUP_TIMER) {
20478- /*
20479- ** check if we need to check for descriptors which
20480- ** haven't been handled the last millisecs
20481- */
20482- StartDrvCleanupTimer(pAC);
20483- if (pAC->GIni.GIMacsFound == 2) {
20484- ReceiveIrq(pAC, &pAC->RxPort[1], SK_FALSE);
20485- }
20486- ReceiveIrq(pAC, &pAC->RxPort[0], SK_FALSE);
20487- } else {
20488- printk("Expiration of unknown timer\n");
20489- }
20490- break;
20491- default:
20492- break;
20493+ /* Run the dispatcher */
20494+ if (Dispatcher) {
20495+ SkEventDispatcher(pAC, pAC->IoBase);
20496 }
20497- SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
20498- ("END EVENT "));
20499-
20500- return (0);
20501-} /* SkDrvEvent */
20502+
20503+}
20504
20505
20506 /*****************************************************************************
20507@@ -4408,8 +5847,6 @@
20508
20509 } /* SkErrorLog */
20510
20511-#ifdef SK_DIAG_SUPPORT
20512-
20513 /*****************************************************************************
20514 *
20515 * SkDrvEnterDiagMode - handles DIAG attach request
20516@@ -4424,8 +5861,11 @@
20517 int SkDrvEnterDiagMode(
20518 SK_AC *pAc) /* pointer to adapter context */
20519 {
20520- DEV_NET *pNet = netdev_priv(pAc->dev[0]);
20521- SK_AC *pAC = pNet->pAC;
20522+ SK_AC *pAC = NULL;
20523+ DEV_NET *pNet = NULL;
20524+
20525+ pNet = (DEV_NET *) pAc->dev[0]->priv;
20526+ pAC = pNet->pAC;
20527
20528 SK_MEMCPY(&(pAc->PnmiBackup), &(pAc->PnmiStruct),
20529 sizeof(SK_PNMI_STRUCT_DATA));
20530@@ -4440,8 +5880,9 @@
20531 } else {
20532 pAC->WasIfUp[0] = SK_FALSE;
20533 }
20534- if (pNet != netdev_priv(pAC->dev[1])) {
20535- pNet = netdev_priv(pAC->dev[1]);
20536+
20537+ if (pNet != (DEV_NET *) pAc->dev[1]->priv) {
20538+ pNet = (DEV_NET *) pAc->dev[1]->priv;
20539 if (netif_running(pAC->dev[1])) {
20540 pAC->WasIfUp[1] = SK_TRUE;
20541 pAC->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */
20542@@ -4474,16 +5915,16 @@
20543 sizeof(SK_PNMI_STRUCT_DATA));
20544 pAc->DiagModeActive = DIAG_NOTACTIVE;
20545 pAc->Pnmi.DiagAttached = SK_DIAG_IDLE;
20546- if (pAc->WasIfUp[0] == SK_TRUE) {
20547- pAc->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */
20548+ if (pAc->WasIfUp[0] == SK_TRUE) {
20549+ pAc->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */
20550 DoPrintInterfaceChange = SK_FALSE;
20551- SkDrvInitAdapter(pAc, 0); /* first device */
20552- }
20553- if (pAc->WasIfUp[1] == SK_TRUE) {
20554- pAc->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */
20555+ SkDrvInitAdapter(pAc, 0); /* first device */
20556+ }
20557+ if (pAc->WasIfUp[1] == SK_TRUE) {
20558+ pAc->DiagFlowCtrl = SK_TRUE; /* for SkGeClose */
20559 DoPrintInterfaceChange = SK_FALSE;
20560- SkDrvInitAdapter(pAc, 1); /* second device */
20561- }
20562+ SkDrvInitAdapter(pAc, 1); /* second device */
20563+ }
20564 return(0);
20565 }
20566
20567@@ -4563,11 +6004,20 @@
20568
20569 dev = pAC->dev[devNbr];
20570
20571- /* On Linux 2.6 the network driver does NOT mess with reference
20572- ** counts. The driver MUST be able to be unloaded at any time
20573- ** due to the possibility of hotplug.
20574+ /*
20575+ ** Function SkGeClose() uses MOD_DEC_USE_COUNT (2.2/2.4)
20576+ ** or module_put() (2.6) to decrease the number of users for
20577+ ** a device, but if a device is to be put under control of
20578+ ** the DIAG, that count is OK already and does not need to
20579+ ** be adapted! Hence the opposite MOD_INC_USE_COUNT or
20580+ ** try_module_get() needs to be used again to correct that.
20581 */
20582+ if (!try_module_get(THIS_MODULE)) {
20583+ return (-1);
20584+ }
20585+
20586 if (SkGeClose(dev) != 0) {
20587+ module_put(THIS_MODULE);
20588 return (-1);
20589 }
20590 return (0);
20591@@ -4596,6 +6046,17 @@
20592
20593 if (SkGeOpen(dev) != 0) {
20594 return (-1);
20595+ } else {
20596+ /*
20597+ ** Function SkGeOpen() uses MOD_INC_USE_COUNT (2.2/2.4)
20598+ ** or try_module_get() (2.6) to increase the number of
20599+ ** users for a device, but if a device was just under
20600+ ** control of the DIAG, that count is OK already and
20601+ ** does not need to be adapted! Hence the opposite
20602+ ** MOD_DEC_USE_COUNT or module_put() needs to be used
20603+ ** again to correct that.
20604+ */
20605+ module_put(THIS_MODULE);
20606 }
20607
20608 /*
20609@@ -4608,14 +6069,25 @@
20610
20611 } /* SkDrvInitAdapter */
20612
20613-#endif
20614+static int __init sk98lin_init(void)
20615+{
20616+ return pci_module_init(&sk98lin_driver);
20617+}
20618+
20619+static void __exit sk98lin_cleanup(void)
20620+{
20621+ pci_unregister_driver(&sk98lin_driver);
20622+}
20623+
20624+module_init(sk98lin_init);
20625+module_exit(sk98lin_cleanup);
20626+
20627
20628 #ifdef DEBUG
20629 /****************************************************************************/
20630 /* "debug only" section *****************************************************/
20631 /****************************************************************************/
20632
20633-
20634 /*****************************************************************************
20635 *
20636 * DumpMsg - print a frame
20637@@ -4626,9 +6098,11 @@
20638 * Returns: N/A
20639 *
20640 */
20641-static void DumpMsg(struct sk_buff *skb, char *str)
20642+static void DumpMsg(
20643+struct sk_buff *skb, /* linux' socket buffer */
20644+char *str) /* additional msg string */
20645 {
20646- int msglen;
20647+ int msglen = (skb->len > 64) ? 64 : skb->len;
20648
20649 if (skb == NULL) {
20650 printk("DumpMsg(): NULL-Message\n");
20651@@ -4640,19 +6114,14 @@
20652 return;
20653 }
20654
20655- msglen = skb->len;
20656- if (msglen > 64)
20657- msglen = 64;
20658-
20659- printk("--- Begin of message from %s , len %d (from %d) ----\n", str, msglen, skb->len);
20660-
20661+ printk("DumpMsg: PhysPage: %p\n",
20662+ page_address(virt_to_page(skb->data)));
20663+ printk("--- Begin of message from %s , len %d (from %d) ----\n",
20664+ str, msglen, skb->len);
20665 DumpData((char *)skb->data, msglen);
20666-
20667 printk("------- End of message ---------\n");
20668 } /* DumpMsg */
20669
20670-
20671-
20672 /*****************************************************************************
20673 *
20674 * DumpData - print a data area
20675@@ -4664,23 +6133,22 @@
20676 * Returns: N/A
20677 *
20678 */
20679-static void DumpData(char *p, int size)
20680-{
20681-register int i;
20682-int haddr, addr;
20683-char hex_buffer[180];
20684-char asc_buffer[180];
20685-char HEXCHAR[] = "0123456789ABCDEF";
20686-
20687- addr = 0;
20688- haddr = 0;
20689- hex_buffer[0] = 0;
20690- asc_buffer[0] = 0;
20691+static void DumpData(
20692+char *p, /* pointer to area containing the data */
20693+int size) /* the size of that data area in bytes */
20694+{
20695+ register int i;
20696+ int haddr = 0, addr = 0;
20697+ char hex_buffer[180] = { '\0' };
20698+ char asc_buffer[180] = { '\0' };
20699+ char HEXCHAR[] = "0123456789ABCDEF";
20700+
20701 for (i=0; i < size; ) {
20702- if (*p >= '0' && *p <='z')
20703+ if (*p >= '0' && *p <='z') {
20704 asc_buffer[addr] = *p;
20705- else
20706+ } else {
20707 asc_buffer[addr] = '.';
20708+ }
20709 addr++;
20710 asc_buffer[addr] = 0;
20711 hex_buffer[haddr] = HEXCHAR[(*p & 0xf0) >> 4];
20712@@ -4706,27 +6174,24 @@
20713 * DumpLong - print a data area as long values
20714 *
20715 * Description:
20716- * This function prints a area of data to the system logfile/to the
20717+ * This function prints a long variable to the system logfile/to the
20718 * console.
20719 *
20720 * Returns: N/A
20721 *
20722 */
20723-static void DumpLong(char *pc, int size)
20724-{
20725-register int i;
20726-int haddr, addr;
20727-char hex_buffer[180];
20728-char asc_buffer[180];
20729-char HEXCHAR[] = "0123456789ABCDEF";
20730-long *p;
20731-int l;
20732-
20733- addr = 0;
20734- haddr = 0;
20735- hex_buffer[0] = 0;
20736- asc_buffer[0] = 0;
20737- p = (long*) pc;
20738+static void DumpLong(
20739+char *pc, /* location of the variable to print */
20740+int size) /* how large is the variable? */
20741+{
20742+ register int i;
20743+ int haddr = 0, addr = 0;
20744+ char hex_buffer[180] = { '\0' };
20745+ char asc_buffer[180] = { '\0' };
20746+ char HEXCHAR[] = "0123456789ABCDEF";
20747+ long *p = (long*) pc;
20748+ int l;
20749+
20750 for (i=0; i < size; ) {
20751 l = (long) *p;
20752 hex_buffer[haddr] = HEXCHAR[(l >> 28) & 0xf];
20753@@ -4760,386 +6225,9 @@
20754
20755 #endif
20756
20757-static int __devinit skge_probe_one(struct pci_dev *pdev,
20758- const struct pci_device_id *ent)
20759-{
20760- SK_AC *pAC;
20761- DEV_NET *pNet = NULL;
20762- struct net_device *dev = NULL;
20763- static int boards_found = 0;
20764- int error = -ENODEV;
20765- int using_dac = 0;
20766- char DeviceStr[80];
20767-
20768- if (pci_enable_device(pdev))
20769- goto out;
20770-
20771- /* Configure DMA attributes. */
20772- if (sizeof(dma_addr_t) > sizeof(u32) &&
20773- !(error = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
20774- using_dac = 1;
20775- error = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
20776- if (error < 0) {
20777- printk(KERN_ERR "sk98lin %s unable to obtain 64 bit DMA "
20778- "for consistent allocations\n", pci_name(pdev));
20779- goto out_disable_device;
20780- }
20781- } else {
20782- error = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
20783- if (error) {
20784- printk(KERN_ERR "sk98lin %s no usable DMA configuration\n",
20785- pci_name(pdev));
20786- goto out_disable_device;
20787- }
20788- }
20789-
20790- error = -ENOMEM;
20791- dev = alloc_etherdev(sizeof(DEV_NET));
20792- if (!dev) {
20793- printk(KERN_ERR "sk98lin: unable to allocate etherdev "
20794- "structure!\n");
20795- goto out_disable_device;
20796- }
20797-
20798- pNet = netdev_priv(dev);
20799- pNet->pAC = kzalloc(sizeof(SK_AC), GFP_KERNEL);
20800- if (!pNet->pAC) {
20801- printk(KERN_ERR "sk98lin: unable to allocate adapter "
20802- "structure!\n");
20803- goto out_free_netdev;
20804- }
20805-
20806- pAC = pNet->pAC;
20807- pAC->PciDev = pdev;
20808-
20809- pAC->dev[0] = dev;
20810- pAC->dev[1] = dev;
20811- pAC->CheckQueue = SK_FALSE;
20812-
20813- dev->irq = pdev->irq;
20814-
20815- error = SkGeInitPCI(pAC);
20816- if (error) {
20817- printk(KERN_ERR "sk98lin: PCI setup failed: %i\n", error);
20818- goto out_free_netdev;
20819- }
20820-
20821- SET_MODULE_OWNER(dev);
20822- dev->open = &SkGeOpen;
20823- dev->stop = &SkGeClose;
20824- dev->hard_start_xmit = &SkGeXmit;
20825- dev->get_stats = &SkGeStats;
20826- dev->set_multicast_list = &SkGeSetRxMode;
20827- dev->set_mac_address = &SkGeSetMacAddr;
20828- dev->do_ioctl = &SkGeIoctl;
20829- dev->change_mtu = &SkGeChangeMtu;
20830-#ifdef CONFIG_NET_POLL_CONTROLLER
20831- dev->poll_controller = &SkGePollController;
20832-#endif
20833- SET_NETDEV_DEV(dev, &pdev->dev);
20834- SET_ETHTOOL_OPS(dev, &SkGeEthtoolOps);
20835-
20836- /* Use only if yukon hardware */
20837- if (pAC->ChipsetType) {
20838-#ifdef USE_SK_TX_CHECKSUM
20839- dev->features |= NETIF_F_IP_CSUM;
20840-#endif
20841-#ifdef SK_ZEROCOPY
20842- dev->features |= NETIF_F_SG;
20843-#endif
20844-#ifdef USE_SK_RX_CHECKSUM
20845- pAC->RxPort[0].RxCsum = 1;
20846-#endif
20847- }
20848-
20849- if (using_dac)
20850- dev->features |= NETIF_F_HIGHDMA;
20851-
20852- pAC->Index = boards_found++;
20853-
20854- error = SkGeBoardInit(dev, pAC);
20855- if (error)
20856- goto out_free_netdev;
20857-
20858- /* Read Adapter name from VPD */
20859- if (ProductStr(pAC, DeviceStr, sizeof(DeviceStr)) != 0) {
20860- error = -EIO;
20861- printk(KERN_ERR "sk98lin: Could not read VPD data.\n");
20862- goto out_free_resources;
20863- }
20864-
20865- /* Register net device */
20866- error = register_netdev(dev);
20867- if (error) {
20868- printk(KERN_ERR "sk98lin: Could not register device.\n");
20869- goto out_free_resources;
20870- }
20871-
20872- /* Print adapter specific string from vpd */
20873- printk("%s: %s\n", dev->name, DeviceStr);
20874-
20875- /* Print configuration settings */
20876- printk(" PrefPort:%c RlmtMode:%s\n",
20877- 'A' + pAC->Rlmt.Net[0].Port[pAC->Rlmt.Net[0].PrefPort]->PortNumber,
20878- (pAC->RlmtMode==0) ? "Check Link State" :
20879- ((pAC->RlmtMode==1) ? "Check Link State" :
20880- ((pAC->RlmtMode==3) ? "Check Local Port" :
20881- ((pAC->RlmtMode==7) ? "Check Segmentation" :
20882- ((pAC->RlmtMode==17) ? "Dual Check Link State" :"Error")))));
20883-
20884- SkGeYellowLED(pAC, pAC->IoBase, 1);
20885-
20886- memcpy(&dev->dev_addr, &pAC->Addr.Net[0].CurrentMacAddress, 6);
20887- memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
20888-
20889- pNet->PortNr = 0;
20890- pNet->NetNr = 0;
20891-
20892- boards_found++;
20893-
20894- pci_set_drvdata(pdev, dev);
20895-
20896- /* More then one port found */
20897- if ((pAC->GIni.GIMacsFound == 2 ) && (pAC->RlmtNets == 2)) {
20898- dev = alloc_etherdev(sizeof(DEV_NET));
20899- if (!dev) {
20900- printk(KERN_ERR "sk98lin: unable to allocate etherdev "
20901- "structure!\n");
20902- goto single_port;
20903- }
20904-
20905- pNet = netdev_priv(dev);
20906- pNet->PortNr = 1;
20907- pNet->NetNr = 1;
20908- pNet->pAC = pAC;
20909-
20910- dev->open = &SkGeOpen;
20911- dev->stop = &SkGeClose;
20912- dev->hard_start_xmit = &SkGeXmit;
20913- dev->get_stats = &SkGeStats;
20914- dev->set_multicast_list = &SkGeSetRxMode;
20915- dev->set_mac_address = &SkGeSetMacAddr;
20916- dev->do_ioctl = &SkGeIoctl;
20917- dev->change_mtu = &SkGeChangeMtu;
20918- SET_NETDEV_DEV(dev, &pdev->dev);
20919- SET_ETHTOOL_OPS(dev, &SkGeEthtoolOps);
20920-
20921- if (pAC->ChipsetType) {
20922-#ifdef USE_SK_TX_CHECKSUM
20923- dev->features |= NETIF_F_IP_CSUM;
20924-#endif
20925-#ifdef SK_ZEROCOPY
20926- dev->features |= NETIF_F_SG;
20927-#endif
20928-#ifdef USE_SK_RX_CHECKSUM
20929- pAC->RxPort[1].RxCsum = 1;
20930-#endif
20931- }
20932-
20933- if (using_dac)
20934- dev->features |= NETIF_F_HIGHDMA;
20935-
20936- error = register_netdev(dev);
20937- if (error) {
20938- printk(KERN_ERR "sk98lin: Could not register device"
20939- " for second port. (%d)\n", error);
20940- free_netdev(dev);
20941- goto single_port;
20942- }
20943-
20944- pAC->dev[1] = dev;
20945- memcpy(&dev->dev_addr,
20946- &pAC->Addr.Net[1].CurrentMacAddress, 6);
20947- memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
20948-
20949- printk("%s: %s\n", dev->name, DeviceStr);
20950- printk(" PrefPort:B RlmtMode:Dual Check Link State\n");
20951- }
20952-
20953-single_port:
20954-
20955- /* Save the hardware revision */
20956- pAC->HWRevision = (((pAC->GIni.GIPciHwRev >> 4) & 0x0F)*10) +
20957- (pAC->GIni.GIPciHwRev & 0x0F);
20958-
20959- /* Set driver globals */
20960- pAC->Pnmi.pDriverFileName = DRIVER_FILE_NAME;
20961- pAC->Pnmi.pDriverReleaseDate = DRIVER_REL_DATE;
20962-
20963- memset(&pAC->PnmiBackup, 0, sizeof(SK_PNMI_STRUCT_DATA));
20964- memcpy(&pAC->PnmiBackup, &pAC->PnmiStruct, sizeof(SK_PNMI_STRUCT_DATA));
20965-
20966- return 0;
20967-
20968- out_free_resources:
20969- FreeResources(dev);
20970- out_free_netdev:
20971- free_netdev(dev);
20972- out_disable_device:
20973- pci_disable_device(pdev);
20974- out:
20975- return error;
20976-}
20977-
20978-static void __devexit skge_remove_one(struct pci_dev *pdev)
20979-{
20980- struct net_device *dev = pci_get_drvdata(pdev);
20981- DEV_NET *pNet = netdev_priv(dev);
20982- SK_AC *pAC = pNet->pAC;
20983- struct net_device *otherdev = pAC->dev[1];
20984-
20985- unregister_netdev(dev);
20986-
20987- SkGeYellowLED(pAC, pAC->IoBase, 0);
20988-
20989- if (pAC->BoardLevel == SK_INIT_RUN) {
20990- SK_EVPARA EvPara;
20991- unsigned long Flags;
20992-
20993- /* board is still alive */
20994- spin_lock_irqsave(&pAC->SlowPathLock, Flags);
20995- EvPara.Para32[0] = 0;
20996- EvPara.Para32[1] = -1;
20997- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
20998- EvPara.Para32[0] = 1;
20999- EvPara.Para32[1] = -1;
21000- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
21001- SkEventDispatcher(pAC, pAC->IoBase);
21002- /* disable interrupts */
21003- SK_OUT32(pAC->IoBase, B0_IMSK, 0);
21004- SkGeDeInit(pAC, pAC->IoBase);
21005- spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
21006- pAC->BoardLevel = SK_INIT_DATA;
21007- /* We do NOT check here, if IRQ was pending, of course*/
21008- }
21009-
21010- if (pAC->BoardLevel == SK_INIT_IO) {
21011- /* board is still alive */
21012- SkGeDeInit(pAC, pAC->IoBase);
21013- pAC->BoardLevel = SK_INIT_DATA;
21014- }
21015-
21016- FreeResources(dev);
21017- free_netdev(dev);
21018- if (otherdev != dev)
21019- free_netdev(otherdev);
21020- kfree(pAC);
21021-}
21022-
21023-#ifdef CONFIG_PM
21024-static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
21025-{
21026- struct net_device *dev = pci_get_drvdata(pdev);
21027- DEV_NET *pNet = netdev_priv(dev);
21028- SK_AC *pAC = pNet->pAC;
21029- struct net_device *otherdev = pAC->dev[1];
21030-
21031- if (netif_running(dev)) {
21032- netif_carrier_off(dev);
21033- DoPrintInterfaceChange = SK_FALSE;
21034- SkDrvDeInitAdapter(pAC, 0); /* performs SkGeClose */
21035- netif_device_detach(dev);
21036- }
21037- if (otherdev != dev) {
21038- if (netif_running(otherdev)) {
21039- netif_carrier_off(otherdev);
21040- DoPrintInterfaceChange = SK_FALSE;
21041- SkDrvDeInitAdapter(pAC, 1); /* performs SkGeClose */
21042- netif_device_detach(otherdev);
21043- }
21044- }
21045-
21046- pci_save_state(pdev);
21047- pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
21048- if (pAC->AllocFlag & SK_ALLOC_IRQ) {
21049- free_irq(dev->irq, dev);
21050- }
21051- pci_disable_device(pdev);
21052- pci_set_power_state(pdev, pci_choose_state(pdev, state));
21053-
21054- return 0;
21055-}
21056-
21057-static int skge_resume(struct pci_dev *pdev)
21058-{
21059- struct net_device *dev = pci_get_drvdata(pdev);
21060- DEV_NET *pNet = netdev_priv(dev);
21061- SK_AC *pAC = pNet->pAC;
21062- struct net_device *otherdev = pAC->dev[1];
21063- int ret;
21064-
21065- pci_set_power_state(pdev, PCI_D0);
21066- pci_restore_state(pdev);
21067- pci_enable_device(pdev);
21068- pci_set_master(pdev);
21069- if (pAC->GIni.GIMacsFound == 2)
21070- ret = request_irq(dev->irq, SkGeIsr, SA_SHIRQ, "sk98lin", dev);
21071- else
21072- ret = request_irq(dev->irq, SkGeIsrOnePort, SA_SHIRQ, "sk98lin", dev);
21073- if (ret) {
21074- printk(KERN_WARNING "sk98lin: unable to acquire IRQ %d\n", dev->irq);
21075- pAC->AllocFlag &= ~SK_ALLOC_IRQ;
21076- dev->irq = 0;
21077- pci_disable_device(pdev);
21078- return -EBUSY;
21079- }
21080-
21081- netif_device_attach(dev);
21082- if (netif_running(dev)) {
21083- DoPrintInterfaceChange = SK_FALSE;
21084- SkDrvInitAdapter(pAC, 0); /* first device */
21085- }
21086- if (otherdev != dev) {
21087- netif_device_attach(otherdev);
21088- if (netif_running(otherdev)) {
21089- DoPrintInterfaceChange = SK_FALSE;
21090- SkDrvInitAdapter(pAC, 1); /* second device */
21091- }
21092- }
21093-
21094- return 0;
21095-}
21096-#else
21097-#define skge_suspend NULL
21098-#define skge_resume NULL
21099-#endif
21100-
21101-static struct pci_device_id skge_pci_tbl[] = {
21102- { PCI_VENDOR_ID_3COM, 0x1700, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
21103- { PCI_VENDOR_ID_3COM, 0x80eb, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
21104- { PCI_VENDOR_ID_SYSKONNECT, 0x4300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
21105- { PCI_VENDOR_ID_SYSKONNECT, 0x4320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
21106-/* DLink card does not have valid VPD so this driver gags
21107- * { PCI_VENDOR_ID_DLINK, 0x4c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
21108- */
21109- { PCI_VENDOR_ID_MARVELL, 0x4320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
21110- { PCI_VENDOR_ID_MARVELL, 0x5005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
21111- { PCI_VENDOR_ID_CNET, 0x434e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
21112- { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
21113- { PCI_VENDOR_ID_LINKSYS, 0x1064, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
21114- { 0 }
21115-};
21116-
21117-MODULE_DEVICE_TABLE(pci, skge_pci_tbl);
21118-
21119-static struct pci_driver skge_driver = {
21120- .name = "sk98lin",
21121- .id_table = skge_pci_tbl,
21122- .probe = skge_probe_one,
21123- .remove = __devexit_p(skge_remove_one),
21124- .suspend = skge_suspend,
21125- .resume = skge_resume,
21126-};
21127-
21128-static int __init skge_init(void)
21129-{
21130- return pci_module_init(&skge_driver);
21131-}
21132-
21133-static void __exit skge_exit(void)
21134-{
21135- pci_unregister_driver(&skge_driver);
21136-}
21137+/*******************************************************************************
21138+ *
21139+ * End of file
21140+ *
21141+ ******************************************************************************/
21142
21143-module_init(skge_init);
21144-module_exit(skge_exit);
21145diff -ruN linux/drivers/net/sk98lin/skgehwt.c linux-new/drivers/net/sk98lin/skgehwt.c
21146--- linux/drivers/net/sk98lin/skgehwt.c 2006-04-11 19:19:28.000000000 +0200
21147+++ linux-new/drivers/net/sk98lin/skgehwt.c 2006-01-18 14:37:24.000000000 +0100
21148@@ -2,8 +2,8 @@
21149 *
21150 * Name: skgehwt.c
21151 * Project: Gigabit Ethernet Adapters, Event Scheduler Module
21152- * Version: $Revision$
21153- * Date: $Date$
21154+ * Version: $Revision$
21155+ * Date: $Date$
21156 * Purpose: Hardware Timer
21157 *
21158 ******************************************************************************/
21159@@ -11,7 +11,7 @@
21160 /******************************************************************************
21161 *
21162 * (C)Copyright 1998-2002 SysKonnect GmbH.
21163- * (C)Copyright 2002-2003 Marvell.
21164+ * (C)Copyright 2002-2004 Marvell.
21165 *
21166 * This program is free software; you can redistribute it and/or modify
21167 * it under the terms of the GNU General Public License as published by
21168@@ -27,7 +27,7 @@
21169 */
21170 #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
21171 static const char SysKonnectFileId[] =
21172- "@(#) $Id$ (C) Marvell.";
21173+ "@(#) $Id$ (C) Marvell.";
21174 #endif
21175
21176 #include "h/skdrv1st.h" /* Driver Specific Definitions */
21177@@ -44,10 +44,10 @@
21178 /*
21179 * Prototypes of local functions.
21180 */
21181-#define SK_HWT_MAX (65000)
21182+#define SK_HWT_MAX 65000UL * 160 /* ca. 10 sec. */
21183
21184 /* correction factor */
21185-#define SK_HWT_FAC (1000 * (SK_U32)pAC->GIni.GIHstClkFact / 100)
21186+#define SK_HWT_FAC (10 * (SK_U32)pAC->GIni.GIHstClkFact / 16)
21187
21188 /*
21189 * Initialize hardware timer.
21190@@ -73,29 +73,21 @@
21191 void SkHwtStart(
21192 SK_AC *pAC, /* Adapters context */
21193 SK_IOC Ioc, /* IoContext */
21194-SK_U32 Time) /* Time in units of 16us to load the timer with. */
21195+SK_U32 Time) /* Time in usec to load the timer */
21196 {
21197- SK_U32 Cnt;
21198-
21199 if (Time > SK_HWT_MAX)
21200 Time = SK_HWT_MAX;
21201
21202 pAC->Hwt.TStart = Time;
21203 pAC->Hwt.TStop = 0L;
21204
21205- Cnt = Time;
21206-
21207- /*
21208- * if time < 16 us
21209- * time = 16 us
21210- */
21211- if (!Cnt) {
21212- Cnt++;
21213+ if (!Time) {
21214+ Time = 1L;
21215 }
21216
21217- SK_OUT32(Ioc, B2_TI_INI, Cnt * SK_HWT_FAC);
21218-
21219- SK_OUT16(Ioc, B2_TI_CTRL, TIM_START); /* Start timer. */
21220+ SK_OUT32(Ioc, B2_TI_INI, Time * SK_HWT_FAC);
21221+
21222+ SK_OUT16(Ioc, B2_TI_CTRL, TIM_START); /* Start timer */
21223
21224 pAC->Hwt.TActive = SK_TRUE;
21225 }
21226@@ -109,13 +101,12 @@
21227 SK_IOC Ioc) /* IoContext */
21228 {
21229 SK_OUT16(Ioc, B2_TI_CTRL, TIM_STOP);
21230-
21231+
21232 SK_OUT16(Ioc, B2_TI_CTRL, TIM_CLR_IRQ);
21233
21234 pAC->Hwt.TActive = SK_FALSE;
21235 }
21236
21237-
21238 /*
21239 * Stop hardware timer and read time elapsed since last start.
21240 *
21241@@ -129,6 +120,9 @@
21242 {
21243 SK_U32 TRead;
21244 SK_U32 IStatus;
21245+ SK_U32 TimerInt;
21246+
21247+ TimerInt = CHIP_ID_YUKON_2(pAC) ? Y2_IS_TIMINT : IS_TIMINT;
21248
21249 if (pAC->Hwt.TActive) {
21250
21251@@ -139,15 +133,15 @@
21252
21253 SK_IN32(Ioc, B0_ISRC, &IStatus);
21254
21255- /* Check if timer expired (or wraped around) */
21256- if ((TRead > pAC->Hwt.TStart) || (IStatus & IS_TIMINT)) {
21257-
21258+ /* Check if timer expired (or wrapped around) */
21259+ if ((TRead > pAC->Hwt.TStart) || ((IStatus & TimerInt) != 0)) {
21260+
21261 SkHwtStop(pAC, Ioc);
21262-
21263+
21264 pAC->Hwt.TStop = pAC->Hwt.TStart;
21265 }
21266 else {
21267-
21268+
21269 pAC->Hwt.TStop = pAC->Hwt.TStart - TRead;
21270 }
21271 }
21272@@ -162,9 +156,9 @@
21273 SK_IOC Ioc) /* IoContext */
21274 {
21275 SkHwtStop(pAC, Ioc);
21276-
21277+
21278 pAC->Hwt.TStop = pAC->Hwt.TStart;
21279-
21280+
21281 SkTimerDone(pAC, Ioc);
21282 }
21283
21284diff -ruN linux/drivers/net/sk98lin/skgeinit.c linux-new/drivers/net/sk98lin/skgeinit.c
21285--- linux/drivers/net/sk98lin/skgeinit.c 2006-04-11 19:19:28.000000000 +0200
21286+++ linux-new/drivers/net/sk98lin/skgeinit.c 2006-01-18 14:37:24.000000000 +0100
21287@@ -2,23 +2,24 @@
21288 *
21289 * Name: skgeinit.c
21290 * Project: Gigabit Ethernet Adapters, Common Modules
21291- * Version: $Revision$
21292- * Date: $Date$
21293+ * Version: $Revision$
21294+ * Date: $Date$
21295 * Purpose: Contains functions to initialize the adapter
21296 *
21297 ******************************************************************************/
21298
21299 /******************************************************************************
21300 *
21301+ * LICENSE:
21302 * (C)Copyright 1998-2002 SysKonnect.
21303- * (C)Copyright 2002-2003 Marvell.
21304+ * (C)Copyright 2002-2005 Marvell.
21305 *
21306 * This program is free software; you can redistribute it and/or modify
21307 * it under the terms of the GNU General Public License as published by
21308 * the Free Software Foundation; either version 2 of the License, or
21309 * (at your option) any later version.
21310- *
21311 * The information in this file is provided "AS IS" without warranty.
21312+ * /LICENSE
21313 *
21314 ******************************************************************************/
21315
21316@@ -31,7 +32,7 @@
21317
21318 #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
21319 static const char SysKonnectFileId[] =
21320- "@(#) $Id$ (C) Marvell.";
21321+ "@(#) $Id$ (C) Marvell.";
21322 #endif
21323
21324 struct s_QOffTab {
21325@@ -39,6 +40,7 @@
21326 int XsQOff; /* Sync Tx Queue Address Offset */
21327 int XaQOff; /* Async Tx Queue Address Offset */
21328 };
21329+
21330 static struct s_QOffTab QOffTab[] = {
21331 {Q_R1, Q_XS1, Q_XA1}, {Q_R2, Q_XS2, Q_XA2}
21332 };
21333@@ -57,6 +59,97 @@
21334 #endif
21335 };
21336
21337+#ifndef SK_SLIM
21338+/******************************************************************************
21339+ *
21340+ * SkGePortVlan() - Enable / Disable VLAN support
21341+ *
21342+ * Description:
21343+ * Enable or disable the VLAN support of the selected port.
21344+ * The new configuration is *not* saved over any SkGeStopPort() and
21345+ * SkGeInitPort() calls.
21346+ * Currently this function is only supported on Yukon-2/EC adapters.
21347+ *
21348+ * Returns:
21349+ * nothing
21350+ */
21351+void SkGePortVlan(
21352+SK_AC *pAC, /* Adapter Context */
21353+SK_IOC IoC, /* I/O Context */
21354+int Port, /* Port number */
21355+SK_BOOL Enable) /* Flag */
21356+{
21357+ SK_U32 RxCtrl;
21358+ SK_U32 TxCtrl;
21359+
21360+ if (CHIP_ID_YUKON_2(pAC)) {
21361+ if (Enable) {
21362+ RxCtrl = RX_VLAN_STRIP_ON;
21363+ TxCtrl = TX_VLAN_TAG_ON;
21364+ }
21365+ else {
21366+ RxCtrl = RX_VLAN_STRIP_OFF;
21367+ TxCtrl = TX_VLAN_TAG_OFF;
21368+ }
21369+
21370+ SK_OUT32(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), RxCtrl);
21371+ SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), TxCtrl);
21372+ }
21373+} /* SkGePortVlan */
21374+
21375+
21376+/******************************************************************************
21377+ *
21378+ * SkGeRxRss() - Enable / Disable RSS Hash Calculation
21379+ *
21380+ * Description:
21381+ * Enable or disable the RSS hash calculation of the selected port.
21382+ * The new configuration is *not* saved over any SkGeStopPort() and
21383+ * SkGeInitPort() calls.
21384+ * Currently this function is only supported on Yukon-2/EC adapters.
21385+ *
21386+ * Returns:
21387+ * nothing
21388+ */
21389+void SkGeRxRss(
21390+SK_AC *pAC, /* Adapter Context */
21391+SK_IOC IoC, /* I/O Context */
21392+int Port, /* Port number */
21393+SK_BOOL Enable) /* Flag */
21394+{
21395+ if (CHIP_ID_YUKON_2(pAC)) {
21396+ SK_OUT32(IoC, Q_ADDR(pAC->GIni.GP[Port].PRxQOff, Q_CSR),
21397+ Enable ? BMU_ENA_RX_RSS_HASH : BMU_DIS_RX_RSS_HASH);
21398+ }
21399+} /* SkGeRxRss */
21400+
21401+
21402+/******************************************************************************
21403+ *
21404+ * SkGeRxCsum() - Enable / Disable Receive Checksum
21405+ *
21406+ * Description:
21407+ * Enable or disable the checksum of the selected port.
21408+ * The new configuration is *not* saved over any SkGeStopPort() and
21409+ * SkGeInitPort() calls.
21410+ * Currently this function is only supported on Yukon-2/EC adapters.
21411+ *
21412+ * Returns:
21413+ * nothing
21414+ */
21415+void SkGeRxCsum(
21416+SK_AC *pAC, /* Adapter Context */
21417+SK_IOC IoC, /* I/O Context */
21418+int Port, /* Port number */
21419+SK_BOOL Enable) /* Flag */
21420+{
21421+ if (CHIP_ID_YUKON_2(pAC)) {
21422+ SK_OUT32(IoC, Q_ADDR(pAC->GIni.GP[Port].PRxQOff, Q_CSR),
21423+ Enable ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
21424+ }
21425+} /* SkGeRxCsum */
21426+#endif /* !SK_SLIM */
21427+
21428 /******************************************************************************
21429 *
21430 * SkGePollRxD() - Enable / Disable Descriptor Polling of RxD Ring
21431@@ -71,8 +164,8 @@
21432 * nothing
21433 */
21434 void SkGePollRxD(
21435-SK_AC *pAC, /* adapter context */
21436-SK_IOC IoC, /* IO context */
21437+SK_AC *pAC, /* Adapter Context */
21438+SK_IOC IoC, /* I/O Context */
21439 int Port, /* Port Index (MAC_1 + n) */
21440 SK_BOOL PollRxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */
21441 {
21442@@ -80,8 +173,8 @@
21443
21444 pPrt = &pAC->GIni.GP[Port];
21445
21446- SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), (PollRxD) ?
21447- CSR_ENA_POL : CSR_DIS_POL);
21448+ SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), (SK_U32)((PollRxD) ?
21449+ CSR_ENA_POL : CSR_DIS_POL));
21450 } /* SkGePollRxD */
21451
21452
21453@@ -99,8 +192,8 @@
21454 * nothing
21455 */
21456 void SkGePollTxD(
21457-SK_AC *pAC, /* adapter context */
21458-SK_IOC IoC, /* IO context */
21459+SK_AC *pAC, /* Adapter Context */
21460+SK_IOC IoC, /* I/O Context */
21461 int Port, /* Port Index (MAC_1 + n) */
21462 SK_BOOL PollTxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */
21463 {
21464@@ -114,13 +207,13 @@
21465 if (pPrt->PXSQSize != 0) {
21466 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), DWord);
21467 }
21468-
21469+
21470 if (pPrt->PXAQSize != 0) {
21471 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), DWord);
21472 }
21473 } /* SkGePollTxD */
21474
21475-
21476+#ifndef SK_SLIM
21477 /******************************************************************************
21478 *
21479 * SkGeYellowLED() - Switch the yellow LED on or off.
21480@@ -135,20 +228,30 @@
21481 * nothing
21482 */
21483 void SkGeYellowLED(
21484-SK_AC *pAC, /* adapter context */
21485-SK_IOC IoC, /* IO context */
21486+SK_AC *pAC, /* Adapter Context */
21487+SK_IOC IoC, /* I/O Context */
21488 int State) /* yellow LED state, 0 = OFF, 0 != ON */
21489 {
21490+ int LedReg;
21491+
21492+ if (CHIP_ID_YUKON_2(pAC)) {
21493+ /* different mapping on Yukon-2 */
21494+ LedReg = B0_CTST + 1;
21495+ }
21496+ else {
21497+ LedReg = B0_LED;
21498+ }
21499+
21500 if (State == 0) {
21501- /* Switch yellow LED OFF */
21502- SK_OUT8(IoC, B0_LED, LED_STAT_OFF);
21503+ /* Switch state LED OFF */
21504+ SK_OUT8(IoC, LedReg, LED_STAT_OFF);
21505 }
21506 else {
21507- /* Switch yellow LED ON */
21508- SK_OUT8(IoC, B0_LED, LED_STAT_ON);
21509+ /* Switch state LED ON */
21510+ SK_OUT8(IoC, LedReg, LED_STAT_ON);
21511 }
21512 } /* SkGeYellowLED */
21513-
21514+#endif /* !SK_SLIM */
21515
21516 #if (!defined(SK_SLIM) || defined(GENESIS))
21517 /******************************************************************************
21518@@ -169,8 +272,8 @@
21519 * nothing
21520 */
21521 void SkGeXmitLED(
21522-SK_AC *pAC, /* adapter context */
21523-SK_IOC IoC, /* IO context */
21524+SK_AC *pAC, /* Adapter Context */
21525+SK_IOC IoC, /* I/O Context */
21526 int Led, /* offset to the LED Init Value register */
21527 int Mode) /* Mode may be SK_LED_DIS, SK_LED_ENA, SK_LED_TST */
21528 {
21529@@ -195,18 +298,17 @@
21530 */
21531 SK_OUT32(IoC, Led + XMIT_LED_CNT, 0);
21532 SK_OUT8(IoC, Led + XMIT_LED_TST, LED_T_OFF);
21533- break;
21534 }
21535-
21536+
21537 /*
21538- * 1000BT: The Transmit LED is driven by the PHY.
21539+ * 1000BT: the Transmit LED is driven by the PHY.
21540 * But the default LED configuration is used for
21541 * Level One and Broadcom PHYs.
21542- * (Broadcom: It may be that PHY_B_PEC_EN_LTR has to be set.)
21543- * (In this case it has to be added here. But we will see. XXX)
21544+ * (Broadcom: It may be that PHY_B_PEC_EN_LTR has to be set.
21545+ * In this case it has to be added here.)
21546 */
21547 } /* SkGeXmitLED */
21548-#endif /* !SK_SLIM || GENESIS */
21549+#endif /* !SK_SLIM || GENESIS */
21550
21551
21552 /******************************************************************************
21553@@ -227,7 +329,7 @@
21554 * 1: configuration error
21555 */
21556 static int DoCalcAddr(
21557-SK_AC *pAC, /* adapter context */
21558+SK_AC *pAC, /* Adapter Context */
21559 SK_GEPORT SK_FAR *pPrt, /* port index */
21560 int QuSize, /* size of the queue to configure in kB */
21561 SK_U32 SK_FAR *StartVal, /* start value for address calculation */
21562@@ -264,12 +366,35 @@
21563
21564 /******************************************************************************
21565 *
21566+ * SkGeRoundQueueSize() - Round the given queue size to the adpaters QZ units
21567+ *
21568+ * Description:
21569+ * This function rounds the given queue size in kBs to adapter specific
21570+ * queue size units (Genesis and Yukon: 8 kB, Yukon-2/EC: 1 kB).
21571+ *
21572+ * Returns:
21573+ * the rounded queue size in kB
21574+ */
21575+static int SkGeRoundQueueSize(
21576+SK_AC *pAC, /* Adapter Context */
21577+int QueueSizeKB) /* Queue size in kB */
21578+{
21579+ int QueueSizeSteps;
21580+
21581+ QueueSizeSteps = (CHIP_ID_YUKON_2(pAC)) ? QZ_STEP_Y2 : QZ_STEP;
21582+
21583+ return((QueueSizeKB + QueueSizeSteps - 1) & ~(QueueSizeSteps - 1));
21584+} /* SkGeRoundQueueSize */
21585+
21586+
21587+/******************************************************************************
21588+ *
21589 * SkGeInitAssignRamToQueues() - allocate default queue sizes
21590 *
21591 * Description:
21592 * This function assigns the memory to the different queues and ports.
21593 * When DualNet is set to SK_TRUE all ports get the same amount of memory.
21594- * Otherwise the first port gets most of the memory and all the
21595+ * Otherwise the first port gets most of the memory and all the
21596 * other ports just the required minimum.
21597 * This function can only be called when pAC->GIni.GIRamSize and
21598 * pAC->GIni.GIMacsFound have been initialized, usually this happens
21599@@ -282,102 +407,146 @@
21600 */
21601
21602 int SkGeInitAssignRamToQueues(
21603-SK_AC *pAC, /* Adapter context */
21604+SK_AC *pAC, /* Adapter Context */
21605 int ActivePort, /* Active Port in RLMT mode */
21606-SK_BOOL DualNet) /* adapter context */
21607+SK_BOOL DualNet) /* Dual Net active */
21608 {
21609 int i;
21610 int UsedKilobytes; /* memory already assigned */
21611 int ActivePortKilobytes; /* memory available for active port */
21612- SK_GEPORT *pGePort;
21613-
21614- UsedKilobytes = 0;
21615+ int MinQueueSize; /* min. memory for queues */
21616+ int TotalRamSize; /* total memory for queues */
21617+ SK_BOOL DualPortYukon2;
21618+ SK_GEPORT *pPrt;
21619
21620 if (ActivePort >= pAC->GIni.GIMacsFound) {
21621+
21622 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
21623 ("SkGeInitAssignRamToQueues: ActivePort (%d) invalid\n",
21624 ActivePort));
21625 return(1);
21626 }
21627- if (((pAC->GIni.GIMacsFound * (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE)) +
21628- ((RAM_QUOTA_SYNC == 0) ? 0 : SK_MIN_TXQ_SIZE)) > pAC->GIni.GIRamSize) {
21629+
21630+ DualPortYukon2 = (CHIP_ID_YUKON_2(pAC) && pAC->GIni.GIMacsFound == 2);
21631+
21632+ TotalRamSize = pAC->GIni.GIRamSize;
21633+
21634+ if (DualPortYukon2) {
21635+ TotalRamSize *= 2;
21636+ }
21637+
21638+ MinQueueSize = SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE;
21639+
21640+ if (MinQueueSize > pAC->GIni.GIRamSize) {
21641+ MinQueueSize = pAC->GIni.GIRamSize;
21642+ }
21643+
21644+ if ((pAC->GIni.GIMacsFound * MinQueueSize +
21645+ RAM_QUOTA_SYNC * SK_MIN_TXQ_SIZE) > TotalRamSize) {
21646+
21647 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
21648 ("SkGeInitAssignRamToQueues: Not enough memory (%d)\n",
21649- pAC->GIni.GIRamSize));
21650+ TotalRamSize));
21651 return(2);
21652 }
21653
21654 if (DualNet) {
21655 /* every port gets the same amount of memory */
21656- ActivePortKilobytes = pAC->GIni.GIRamSize / pAC->GIni.GIMacsFound;
21657+ ActivePortKilobytes = TotalRamSize / pAC->GIni.GIMacsFound;
21658+
21659 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
21660
21661- pGePort = &pAC->GIni.GP[i];
21662-
21663+ pPrt = &pAC->GIni.GP[i];
21664+
21665+ if (DualPortYukon2) {
21666+ ActivePortKilobytes = pAC->GIni.GIRamSize;
21667+ }
21668 /* take away the minimum memory for active queues */
21669- ActivePortKilobytes -= (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE);
21670+ ActivePortKilobytes -= MinQueueSize;
21671
21672 /* receive queue gets the minimum + 80% of the rest */
21673- pGePort->PRxQSize = (int) (ROUND_QUEUE_SIZE_KB((
21674- ActivePortKilobytes * (unsigned long) RAM_QUOTA_RX) / 100))
21675+ pPrt->PRxQSize = SkGeRoundQueueSize(pAC,
21676+ (int)((long)ActivePortKilobytes * RAM_QUOTA_RX) / 100)
21677 + SK_MIN_RXQ_SIZE;
21678
21679- ActivePortKilobytes -= (pGePort->PRxQSize - SK_MIN_RXQ_SIZE);
21680+ ActivePortKilobytes -= (pPrt->PRxQSize - SK_MIN_RXQ_SIZE);
21681
21682 /* synchronous transmit queue */
21683- pGePort->PXSQSize = 0;
21684+ pPrt->PXSQSize = 0;
21685
21686 /* asynchronous transmit queue */
21687- pGePort->PXAQSize = (int) ROUND_QUEUE_SIZE_KB(ActivePortKilobytes +
21688- SK_MIN_TXQ_SIZE);
21689+ pPrt->PXAQSize = SkGeRoundQueueSize(pAC,
21690+ ActivePortKilobytes + SK_MIN_TXQ_SIZE);
21691 }
21692 }
21693- else {
21694- /* Rlmt Mode or single link adapter */
21695+ else { /* RLMT Mode or single link adapter */
21696+
21697+ UsedKilobytes = 0;
21698
21699- /* Set standby queue size defaults for all standby ports */
21700+ /* set standby queue size defaults for all standby ports */
21701 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
21702
21703 if (i != ActivePort) {
21704- pGePort = &pAC->GIni.GP[i];
21705+ pPrt = &pAC->GIni.GP[i];
21706
21707- pGePort->PRxQSize = SK_MIN_RXQ_SIZE;
21708- pGePort->PXAQSize = SK_MIN_TXQ_SIZE;
21709- pGePort->PXSQSize = 0;
21710+ if (DualPortYukon2) {
21711+ pPrt->PRxQSize = SkGeRoundQueueSize(pAC,
21712+ (int)((long)(pAC->GIni.GIRamSize - MinQueueSize) *
21713+ RAM_QUOTA_RX) / 100) + SK_MIN_RXQ_SIZE;
21714+
21715+ pPrt->PXAQSize = pAC->GIni.GIRamSize - pPrt->PRxQSize;
21716+ }
21717+ else {
21718+ pPrt->PRxQSize = SK_MIN_RXQ_SIZE;
21719+ pPrt->PXAQSize = SK_MIN_TXQ_SIZE;
21720+ }
21721+ pPrt->PXSQSize = 0;
21722
21723 /* Count used RAM */
21724- UsedKilobytes += pGePort->PRxQSize + pGePort->PXAQSize;
21725+ UsedKilobytes += pPrt->PRxQSize + pPrt->PXAQSize;
21726 }
21727 }
21728 /* what's left? */
21729- ActivePortKilobytes = pAC->GIni.GIRamSize - UsedKilobytes;
21730+ ActivePortKilobytes = TotalRamSize - UsedKilobytes;
21731
21732 /* assign it to the active port */
21733 /* first take away the minimum memory */
21734- ActivePortKilobytes -= (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE);
21735- pGePort = &pAC->GIni.GP[ActivePort];
21736+ ActivePortKilobytes -= MinQueueSize;
21737+ pPrt = &pAC->GIni.GP[ActivePort];
21738+
21739+ /* receive queue gets 80% of the rest */
21740+ pPrt->PRxQSize = SkGeRoundQueueSize(pAC,
21741+ (int)((long)ActivePortKilobytes * RAM_QUOTA_RX) / 100);
21742
21743- /* receive queue get's the minimum + 80% of the rest */
21744- pGePort->PRxQSize = (int) (ROUND_QUEUE_SIZE_KB((ActivePortKilobytes *
21745- (unsigned long) RAM_QUOTA_RX) / 100)) + SK_MIN_RXQ_SIZE;
21746+ ActivePortKilobytes -= pPrt->PRxQSize;
21747
21748- ActivePortKilobytes -= (pGePort->PRxQSize - SK_MIN_RXQ_SIZE);
21749+ /* add the minimum memory for Rx queue */
21750+ pPrt->PRxQSize += MinQueueSize/2;
21751
21752 /* synchronous transmit queue */
21753- pGePort->PXSQSize = 0;
21754+ pPrt->PXSQSize = 0;
21755
21756- /* asynchronous transmit queue */
21757- pGePort->PXAQSize = (int) ROUND_QUEUE_SIZE_KB(ActivePortKilobytes) +
21758- SK_MIN_TXQ_SIZE;
21759+ /* asynchronous transmit queue gets 20% of the rest */
21760+ pPrt->PXAQSize = SkGeRoundQueueSize(pAC, ActivePortKilobytes) +
21761+ /* add the minimum memory for Tx queue */
21762+ MinQueueSize/2;
21763 }
21764-#ifdef VCPU
21765- VCPUprintf(0, "PRxQSize=%u, PXSQSize=%u, PXAQSize=%u\n",
21766- pGePort->PRxQSize, pGePort->PXSQSize, pGePort->PXAQSize);
21767-#endif /* VCPU */
21768+
21769+#ifdef DEBUG
21770+ for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
21771+
21772+ pPrt = &pAC->GIni.GP[i];
21773+
21774+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
21775+ ("Port %d: RxQSize=%u, TxAQSize=%u, TxSQSize=%u\n",
21776+ i, pPrt->PRxQSize, pPrt->PXAQSize, pPrt->PXSQSize));
21777+ }
21778+#endif /* DEBUG */
21779
21780 return(0);
21781 } /* SkGeInitAssignRamToQueues */
21782
21783+
21784 /******************************************************************************
21785 *
21786 * SkGeCheckQSize() - Checks the Adapters Queue Size Configuration
21787@@ -388,12 +557,12 @@
21788 * used ports.
21789 * This requirements must be fullfilled to have a valid configuration:
21790 * - The size of all queues must not exceed GIRamSize.
21791- * - The queue sizes must be specified in units of 8 kB.
21792+ * - The queue sizes must be specified in units of 8 kB (Genesis & Yukon).
21793 * - The size of Rx queues of available ports must not be
21794- * smaller than 16 kB.
21795+ * smaller than 16 kB (Genesis & Yukon) resp. 10 kB (Yukon-2).
21796 * - The size of at least one Tx queue (synch. or asynch.)
21797- * of available ports must not be smaller than 16 kB
21798- * when Jumbo Frames are used.
21799+ * of available ports must not be smaller than 16 kB (Genesis & Yukon),
21800+ * resp. 10 kB (Yukon-2) when Jumbo Frames are used.
21801 * - The RAM start and end addresses must not be changed
21802 * for ports which are already initialized.
21803 * Furthermore SkGeCheckQSize() defines the Start and End Addresses
21804@@ -404,7 +573,7 @@
21805 * 1: Queue Size Configuration invalid
21806 */
21807 static int SkGeCheckQSize(
21808-SK_AC *pAC, /* adapter context */
21809+SK_AC *pAC, /* Adapter Context */
21810 int Port) /* port index */
21811 {
21812 SK_GEPORT *pPrt;
21813@@ -414,55 +583,68 @@
21814 SK_U32 StartAddr;
21815 #ifndef SK_SLIM
21816 int UsedMem; /* total memory used (max. found ports) */
21817-#endif
21818+#endif
21819
21820 Rtv = 0;
21821-
21822+
21823 #ifndef SK_SLIM
21824
21825 UsedMem = 0;
21826+
21827 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
21828 pPrt = &pAC->GIni.GP[i];
21829
21830- if ((pPrt->PRxQSize & QZ_UNITS) != 0 ||
21831- (pPrt->PXSQSize & QZ_UNITS) != 0 ||
21832- (pPrt->PXAQSize & QZ_UNITS) != 0) {
21833+ if (CHIP_ID_YUKON_2(pAC)) {
21834+ UsedMem = 0;
21835+ }
21836+ else if (((pPrt->PRxQSize & QZ_UNITS) != 0 ||
21837+ (pPrt->PXSQSize & QZ_UNITS) != 0 ||
21838+ (pPrt->PXAQSize & QZ_UNITS) != 0)) {
21839
21840 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG);
21841 return(1);
21842 }
21843
21844- if (i == Port && pPrt->PRxQSize < SK_MIN_RXQ_SIZE) {
21845+#ifndef SK_DIAG
21846+ if (i == Port && pAC->GIni.GIRamSize > SK_MIN_RXQ_SIZE &&
21847+ pPrt->PRxQSize < SK_MIN_RXQ_SIZE) {
21848 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E011, SKERR_HWI_E011MSG);
21849 return(1);
21850 }
21851-
21852+
21853 /*
21854 * the size of at least one Tx queue (synch. or asynch.) has to be > 0.
21855 * if Jumbo Frames are used, this size has to be >= 16 kB.
21856 */
21857 if ((i == Port && pPrt->PXSQSize == 0 && pPrt->PXAQSize == 0) ||
21858- (pAC->GIni.GIPortUsage == SK_JUMBO_LINK &&
21859- ((pPrt->PXSQSize > 0 && pPrt->PXSQSize < SK_MIN_TXQ_SIZE) ||
21860+ (pPrt->PPortUsage == SK_JUMBO_LINK &&
21861+ ((pPrt->PXSQSize > 0 && pPrt->PXSQSize < SK_MIN_TXQ_SIZE) ||
21862 (pPrt->PXAQSize > 0 && pPrt->PXAQSize < SK_MIN_TXQ_SIZE)))) {
21863 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E023, SKERR_HWI_E023MSG);
21864 return(1);
21865 }
21866-
21867+#endif /* !SK_DIAG */
21868+
21869 UsedMem += pPrt->PRxQSize + pPrt->PXSQSize + pPrt->PXAQSize;
21870+
21871+ if (UsedMem > pAC->GIni.GIRamSize) {
21872+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG);
21873+ return(1);
21874+ }
21875 }
21876-
21877- if (UsedMem > pAC->GIni.GIRamSize) {
21878- SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG);
21879- return(1);
21880- }
21881-#endif /* !SK_SLIM */
21882+
21883+#endif /* !SK_SLIM */
21884
21885 /* Now start address calculation */
21886 StartAddr = pAC->GIni.GIRamOffs;
21887 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
21888+
21889 pPrt = &pAC->GIni.GP[i];
21890
21891+ if (CHIP_ID_YUKON_2(pAC)) {
21892+ StartAddr = 0;
21893+ }
21894+
21895 /* Calculate/Check values for the receive queue */
21896 Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PRxQSize, &StartAddr,
21897 &pPrt->PRxQRamStart, &pPrt->PRxQRamEnd);
21898@@ -502,8 +684,8 @@
21899 * nothing
21900 */
21901 static void SkGeInitMacArb(
21902-SK_AC *pAC, /* adapter context */
21903-SK_IOC IoC) /* IO context */
21904+SK_AC *pAC, /* Adapter Context */
21905+SK_IOC IoC) /* I/O Context */
21906 {
21907 /* release local reset */
21908 SK_OUT16(IoC, B3_MA_TO_CTRL, MA_RST_CLR);
21909@@ -542,8 +724,8 @@
21910 * nothing
21911 */
21912 static void SkGeInitPktArb(
21913-SK_AC *pAC, /* adapter context */
21914-SK_IOC IoC) /* IO context */
21915+SK_AC *pAC, /* Adapter Context */
21916+SK_IOC IoC) /* I/O Context */
21917 {
21918 /* release local reset */
21919 SK_OUT16(IoC, B3_PA_CTRL, PA_RST_CLR);
21920@@ -559,7 +741,8 @@
21921 * NOTE: the packet arbiter timeout interrupt is needed for
21922 * half duplex hangup workaround
21923 */
21924- if (pAC->GIni.GIPortUsage != SK_JUMBO_LINK) {
21925+ if (pAC->GIni.GP[MAC_1].PPortUsage != SK_JUMBO_LINK &&
21926+ pAC->GIni.GP[MAC_2].PPortUsage != SK_JUMBO_LINK) {
21927 if (pAC->GIni.GIMacsFound == 1) {
21928 SK_OUT16(IoC, B3_PA_CTRL, PA_ENA_TO_TX1);
21929 }
21930@@ -582,14 +765,11 @@
21931 * nothing
21932 */
21933 static void SkGeInitMacFifo(
21934-SK_AC *pAC, /* adapter context */
21935-SK_IOC IoC, /* IO context */
21936+SK_AC *pAC, /* Adapter Context */
21937+SK_IOC IoC, /* I/O Context */
21938 int Port) /* Port Index (MAC_1 + n) */
21939 {
21940 SK_U16 Word;
21941-#ifdef VCPU
21942- SK_U32 DWord;
21943-#endif /* VCPU */
21944 /*
21945 * For each FIFO:
21946 * - release local reset
21947@@ -597,63 +777,101 @@
21948 * - setup defaults for the control register
21949 * - enable the FIFO
21950 */
21951-
21952+
21953 #ifdef GENESIS
21954 if (pAC->GIni.GIGenesis) {
21955- /* Configure Rx MAC FIFO */
21956+ /* configure Rx MAC FIFO */
21957 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_CLR);
21958 SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_RX_CTRL_DEF);
21959 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
21960-
21961- /* Configure Tx MAC FIFO */
21962+
21963+ /* configure Tx MAC FIFO */
21964 SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_RST_CLR);
21965 SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
21966 SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
21967-
21968- /* Enable frame flushing if jumbo frames used */
21969- if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
21970+
21971+ /* enable frame flushing if jumbo frames used */
21972+ if (pAC->GIni.GP[Port].PPortUsage == SK_JUMBO_LINK) {
21973 SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
21974 }
21975 }
21976 #endif /* GENESIS */
21977-
21978+
21979 #ifdef YUKON
21980 if (pAC->GIni.GIYukon) {
21981- /* set Rx GMAC FIFO Flush Mask */
21982- SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), (SK_U16)RX_FF_FL_DEF_MSK);
21983-
21984+
21985 Word = (SK_U16)GMF_RX_CTRL_DEF;
21986
21987 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
21988- if (pAC->GIni.GIYukonLite && pAC->GIni.GIChipId == CHIP_ID_YUKON) {
21989+ if (pAC->GIni.GIYukonLite /* && pAC->GIni.GIChipId == CHIP_ID_YUKON */) {
21990
21991 Word &= ~GMF_RX_F_FL_ON;
21992 }
21993-
21994- /* Configure Rx MAC FIFO */
21995+
21996+ /* configure Rx GMAC FIFO */
21997 SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR);
21998 SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), Word);
21999-
22000- /* set Rx GMAC FIFO Flush Threshold (default: 0x0a -> 56 bytes) */
22001- SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
22002-
22003- /* Configure Tx MAC FIFO */
22004+
22005+ Word = RX_FF_FL_DEF_MSK;
22006+
22007+#ifndef SK_DIAG
22008+ if (HW_FEATURE(pAC, HWF_WA_DEV_4115)) {
22009+ /*
22010+ * Flushing must be enabled (needed for ASF see dev. #4.29),
22011+ * but the flushing mask should be disabled (see dev. #4.115)
22012+ */
22013+ Word = 0;
22014+ }
22015+#endif /* !SK_DIAG */
22016+
22017+ /* set Rx GMAC FIFO Flush Mask (after clearing reset) */
22018+ SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), Word);
22019+
22020+ /* default: 0x0a -> 56 bytes on Yukon-1 and 64 bytes on Yukon-2 */
22021+ Word = (SK_U16)RX_GMF_FL_THR_DEF;
22022+
22023+ if (CHIP_ID_YUKON_2(pAC)) {
22024+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC &&
22025+ pAC->GIni.GIAsfEnabled) {
22026+ /* WA for dev. #4.30 (reduce to 0x08 -> 48 bytes) */
22027+ Word -= 2;
22028+ }
22029+ }
22030+ else {
22031+ /*
22032+ * because Pause Packet Truncation in GMAC is not working
22033+ * we have to increase the Flush Threshold to 64 bytes
22034+ * in order to flush pause packets in Rx FIFO on Yukon-1
22035+ */
22036+ Word++;
22037+ }
22038+
22039+ /* set Rx GMAC FIFO Flush Threshold (after clearing reset) */
22040+ SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), Word);
22041+
22042+ /* configure Tx GMAC FIFO */
22043 SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR);
22044 SK_OUT16(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U16)GMF_TX_CTRL_DEF);
22045-
22046-#ifdef VCPU
22047- SK_IN32(IoC, MR_ADDR(Port, RX_GMF_AF_THR), &DWord);
22048- SK_IN32(IoC, MR_ADDR(Port, TX_GMF_AE_THR), &DWord);
22049-#endif /* VCPU */
22050-
22051- /* set Tx GMAC FIFO Almost Empty Threshold */
22052-/* SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_AE_THR), 0); */
22053+
22054+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) {
22055+ /* set Rx Pause Threshold */
22056+ SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_LP_THR), (SK_U16)SK_ECU_LLPP);
22057+ SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_UP_THR), (SK_U16)SK_ECU_ULPP);
22058+
22059+ if (pAC->GIni.GP[Port].PPortUsage == SK_JUMBO_LINK) {
22060+ /* set Tx GMAC FIFO Almost Empty Threshold */
22061+ SK_OUT16(IoC, MR_ADDR(Port, TX_GMF_AE_THR),
22062+ (SK_U16)SK_ECU_AE_THR);
22063+ /* disable Store & Forward mode for TX */
22064+ SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), TX_STFW_DIS);
22065+ }
22066+ }
22067 }
22068 #endif /* YUKON */
22069
22070 } /* SkGeInitMacFifo */
22071
22072-#ifdef SK_LNK_SYNC_CNT
22073+#ifdef SK_LNK_SYNC_CNT
22074 /******************************************************************************
22075 *
22076 * SkGeLoadLnkSyncCnt() - Load the Link Sync Counter and starts counting
22077@@ -674,8 +892,8 @@
22078 * nothing
22079 */
22080 void SkGeLoadLnkSyncCnt(
22081-SK_AC *pAC, /* adapter context */
22082-SK_IOC IoC, /* IO context */
22083+SK_AC *pAC, /* Adapter Context */
22084+SK_IOC IoC, /* I/O Context */
22085 int Port, /* Port Index (MAC_1 + n) */
22086 SK_U32 CntVal) /* Counter value */
22087 {
22088@@ -685,7 +903,7 @@
22089 SK_BOOL IrqPend;
22090
22091 /* stop counter */
22092- SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_STOP);
22093+ SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LNK_STOP);
22094
22095 /*
22096 * ASIC problem:
22097@@ -698,6 +916,7 @@
22098 IrqPend = SK_FALSE;
22099 SK_IN32(IoC, B0_ISRC, &ISrc);
22100 SK_IN32(IoC, B0_IMSK, &OrgIMsk);
22101+
22102 if (Port == MAC_1) {
22103 NewIMsk = OrgIMsk & ~IS_LNK_SYNC_M1;
22104 if ((ISrc & IS_LNK_SYNC_M1) != 0) {
22105@@ -710,6 +929,7 @@
22106 IrqPend = SK_TRUE;
22107 }
22108 }
22109+
22110 if (!IrqPend) {
22111 SK_OUT32(IoC, B0_IMSK, NewIMsk);
22112 }
22113@@ -718,15 +938,17 @@
22114 SK_OUT32(IoC, MR_ADDR(Port, LNK_SYNC_INI), CntVal);
22115
22116 /* start counter */
22117- SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_START);
22118+ SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LNK_START);
22119
22120 if (!IrqPend) {
22121- /* clear the unexpected IRQ, and restore the interrupt mask */
22122- SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_CLR_IRQ);
22123+ /* clear the unexpected IRQ */
22124+ SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LNK_CLR_IRQ);
22125+
22126+ /* restore the interrupt mask */
22127 SK_OUT32(IoC, B0_IMSK, OrgIMsk);
22128 }
22129 } /* SkGeLoadLnkSyncCnt*/
22130-#endif /* SK_LNK_SYNC_CNT */
22131+#endif /* SK_LNK_SYNC_CNT */
22132
22133 #if defined(SK_DIAG) || defined(SK_CFG_SYNC)
22134 /******************************************************************************
22135@@ -758,8 +980,8 @@
22136 * synchronous queue is configured
22137 */
22138 int SkGeCfgSync(
22139-SK_AC *pAC, /* adapter context */
22140-SK_IOC IoC, /* IO context */
22141+SK_AC *pAC, /* Adapter Context */
22142+SK_IOC IoC, /* I/O Context */
22143 int Port, /* Port Index (MAC_1 + n) */
22144 SK_U32 IntTime, /* Interval Timer Value in units of 8ns */
22145 SK_U32 LimCount, /* Number of bytes to transfer during IntTime */
22146@@ -777,16 +999,16 @@
22147 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG);
22148 return(1);
22149 }
22150-
22151+
22152 if (pAC->GIni.GP[Port].PXSQSize == 0) {
22153 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E009, SKERR_HWI_E009MSG);
22154 return(2);
22155 }
22156-
22157+
22158 /* calculate register values */
22159 IntTime = (IntTime / 2) * pAC->GIni.GIHstClkFact / 100;
22160 LimCount = LimCount / 8;
22161-
22162+
22163 if (IntTime > TXA_MAX_VAL || LimCount > TXA_MAX_VAL) {
22164 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG);
22165 return(1);
22166@@ -804,13 +1026,13 @@
22167 */
22168 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
22169 TXA_ENA_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
22170-
22171+
22172 SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), IntTime);
22173 SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), LimCount);
22174-
22175+
22176 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
22177 (SK_U8)(SyncMode & (TXA_ENA_ALLOC | TXA_DIS_ALLOC)));
22178-
22179+
22180 if (IntTime != 0 || LimCount != 0) {
22181 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_DIS_FSYNC | TXA_START_RC);
22182 }
22183@@ -831,10 +1053,10 @@
22184 * Returns:
22185 * nothing
22186 */
22187-static void DoInitRamQueue(
22188-SK_AC *pAC, /* adapter context */
22189-SK_IOC IoC, /* IO context */
22190-int QuIoOffs, /* Queue IO Address Offset */
22191+void DoInitRamQueue(
22192+SK_AC *pAC, /* Adapter Context */
22193+SK_IOC IoC, /* I/O Context */
22194+int QuIoOffs, /* Queue I/O Address Offset */
22195 SK_U32 QuStartAddr, /* Queue Start Address */
22196 SK_U32 QuEndAddr, /* Queue End Address */
22197 int QuType) /* Queue Type (SK_RX_SRAM_Q|SK_RX_BRAM_Q|SK_TX_RAM_Q) */
22198@@ -867,8 +1089,7 @@
22199
22200 /* continue with SK_RX_BRAM_Q */
22201 case SK_RX_BRAM_Q:
22202- /* write threshold for Rx Queue */
22203-
22204+ /* write threshold for Rx Queue (Pause packets) */
22205 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RX_UTPP), RxUpThresVal);
22206 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RX_LTPP), RxLoThresVal);
22207
22208@@ -882,7 +1103,8 @@
22209 * or YUKON is used ((GMAC Tx FIFO is only 1 kB)
22210 * we NEED Store & Forward of the RAM buffer.
22211 */
22212- if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK ||
22213+ if (pAC->GIni.GP[MAC_1].PPortUsage == SK_JUMBO_LINK ||
22214+ pAC->GIni.GP[MAC_2].PPortUsage == SK_JUMBO_LINK ||
22215 pAC->GIni.GIYukon) {
22216 /* enable Store & Forward Mode for the Tx Side */
22217 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_ENA_STFWD);
22218@@ -911,8 +1133,8 @@
22219 * nothing
22220 */
22221 static void SkGeInitRamBufs(
22222-SK_AC *pAC, /* adapter context */
22223-SK_IOC IoC, /* IO context */
22224+SK_AC *pAC, /* Adapter Context */
22225+SK_IOC IoC, /* I/O Context */
22226 int Port) /* Port Index (MAC_1 + n) */
22227 {
22228 SK_GEPORT *pPrt;
22229@@ -920,8 +1142,8 @@
22230
22231 pPrt = &pAC->GIni.GP[Port];
22232
22233- if (pPrt->PRxQSize == SK_MIN_RXQ_SIZE) {
22234- RxQType = SK_RX_SRAM_Q; /* small Rx Queue */
22235+ if (pPrt->PRxQSize <= SK_MIN_RXQ_SIZE) {
22236+ RxQType = SK_RX_SRAM_Q; /* small Rx Queue */
22237 }
22238 else {
22239 RxQType = SK_RX_BRAM_Q; /* big Rx Queue */
22240@@ -929,10 +1151,10 @@
22241
22242 DoInitRamQueue(pAC, IoC, pPrt->PRxQOff, pPrt->PRxQRamStart,
22243 pPrt->PRxQRamEnd, RxQType);
22244-
22245+
22246 DoInitRamQueue(pAC, IoC, pPrt->PXsQOff, pPrt->PXsQRamStart,
22247 pPrt->PXsQRamEnd, SK_TX_RAM_Q);
22248-
22249+
22250 DoInitRamQueue(pAC, IoC, pPrt->PXaQOff, pPrt->PXaQRamStart,
22251 pPrt->PXaQRamEnd, SK_TX_RAM_Q);
22252
22253@@ -953,26 +1175,37 @@
22254 * nothing
22255 */
22256 void SkGeInitRamIface(
22257-SK_AC *pAC, /* adapter context */
22258-SK_IOC IoC) /* IO context */
22259+SK_AC *pAC, /* Adapter Context */
22260+SK_IOC IoC) /* I/O Context */
22261 {
22262- /* release local reset */
22263- SK_OUT16(IoC, B3_RI_CTRL, RI_RST_CLR);
22264+ int i;
22265+ int RamBuffers;
22266
22267- /* configure timeout values */
22268- SK_OUT8(IoC, B3_RI_WTO_R1, SK_RI_TO_53);
22269- SK_OUT8(IoC, B3_RI_WTO_XA1, SK_RI_TO_53);
22270- SK_OUT8(IoC, B3_RI_WTO_XS1, SK_RI_TO_53);
22271- SK_OUT8(IoC, B3_RI_RTO_R1, SK_RI_TO_53);
22272- SK_OUT8(IoC, B3_RI_RTO_XA1, SK_RI_TO_53);
22273- SK_OUT8(IoC, B3_RI_RTO_XS1, SK_RI_TO_53);
22274- SK_OUT8(IoC, B3_RI_WTO_R2, SK_RI_TO_53);
22275- SK_OUT8(IoC, B3_RI_WTO_XA2, SK_RI_TO_53);
22276- SK_OUT8(IoC, B3_RI_WTO_XS2, SK_RI_TO_53);
22277- SK_OUT8(IoC, B3_RI_RTO_R2, SK_RI_TO_53);
22278- SK_OUT8(IoC, B3_RI_RTO_XA2, SK_RI_TO_53);
22279- SK_OUT8(IoC, B3_RI_RTO_XS2, SK_RI_TO_53);
22280+ if (CHIP_ID_YUKON_2(pAC)) {
22281+ RamBuffers = pAC->GIni.GIMacsFound;
22282+ }
22283+ else {
22284+ RamBuffers = 1;
22285+ }
22286+
22287+ for (i = 0; i < RamBuffers; i++) {
22288+ /* release local reset */
22289+ SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_CTRL), (SK_U8)RI_RST_CLR);
22290
22291+ /* configure timeout values */
22292+ SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
22293+ SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
22294+ SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
22295+ SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
22296+ SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
22297+ SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
22298+ SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
22299+ SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
22300+ SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
22301+ SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
22302+ SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
22303+ SK_OUT8(IoC, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
22304+ }
22305 } /* SkGeInitRamIface */
22306
22307
22308@@ -987,41 +1220,91 @@
22309 * nothing
22310 */
22311 static void SkGeInitBmu(
22312-SK_AC *pAC, /* adapter context */
22313-SK_IOC IoC, /* IO context */
22314+SK_AC *pAC, /* Adapter Context */
22315+SK_IOC IoC, /* I/O Context */
22316 int Port) /* Port Index (MAC_1 + n) */
22317 {
22318 SK_GEPORT *pPrt;
22319- SK_U32 RxWm;
22320- SK_U32 TxWm;
22321+ SK_U16 RxWm;
22322+ SK_U16 TxWm;
22323
22324 pPrt = &pAC->GIni.GP[Port];
22325
22326 RxWm = SK_BMU_RX_WM;
22327 TxWm = SK_BMU_TX_WM;
22328-
22329- if (!pAC->GIni.GIPciSlot64 && !pAC->GIni.GIPciClock66) {
22330- /* for better performance */
22331- RxWm /= 2;
22332- TxWm /= 2;
22333- }
22334
22335- /* Rx Queue: Release all local resets and set the watermark */
22336- SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_CLR_RESET);
22337- SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_F), RxWm);
22338+ if (CHIP_ID_YUKON_2(pAC)) {
22339
22340- /*
22341- * Tx Queue: Release all local resets if the queue is used !
22342- * set watermark
22343- */
22344- if (pPrt->PXSQSize != 0) {
22345- SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_CLR_RESET);
22346- SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_F), TxWm);
22347+ if (pAC->GIni.GIPciBus == SK_PEX_BUS) {
22348+ /* for better performance set it to 128 */
22349+ RxWm = SK_BMU_RX_WM_PEX;
22350+ }
22351+
22352+ /* Rx Queue: Release all local resets and set the watermark */
22353+ SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), BMU_CLR_RESET);
22354+ SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), BMU_OPER_INIT);
22355+ SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), BMU_FIFO_OP_ON);
22356+
22357+ SK_OUT16(IoC, Q_ADDR(pPrt->PRxQOff, Q_WM), RxWm);
22358+
22359+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U &&
22360+ pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A1) {
22361+ /* MAC Rx RAM Read is controlled by hardware */
22362+ SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_F), F_M_RX_RAM_DIS);
22363+ }
22364+
22365+ /*
22366+ * Tx Queue: Release all local resets if the queue is used !
22367+ * set watermark
22368+ */
22369+ if (pPrt->PXSQSize != 0 && HW_SYNC_TX_SUPPORTED(pAC)) {
22370+ /* Yukon-EC doesn't have a synchronous Tx queue */
22371+ SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), BMU_CLR_RESET);
22372+ SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), BMU_OPER_INIT);
22373+ SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), BMU_FIFO_OP_ON);
22374+
22375+ SK_OUT16(IoC, Q_ADDR(pPrt->PXsQOff, Q_WM), TxWm);
22376+ }
22377+
22378+ if (pPrt->PXAQSize != 0) {
22379+
22380+ SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), BMU_CLR_RESET);
22381+ SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), BMU_OPER_INIT);
22382+ SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), BMU_FIFO_OP_ON);
22383+
22384+ SK_OUT16(IoC, Q_ADDR(pPrt->PXaQOff, Q_WM), TxWm);
22385+
22386+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U &&
22387+ pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A0) {
22388+ /* fix for Yukon-EC Ultra: set BMU FIFO level */
22389+ SK_OUT16(IoC, Q_ADDR(pPrt->PXaQOff, Q_AL), SK_ECU_TXFF_LEV);
22390+ }
22391+ }
22392 }
22393-
22394- if (pPrt->PXAQSize != 0) {
22395- SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_CLR_RESET);
22396- SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_F), TxWm);
22397+ else {
22398+ if (!pAC->GIni.GIPciSlot64 && !pAC->GIni.GIPciClock66) {
22399+ /* for better performance */
22400+ RxWm /= 2;
22401+ TxWm /= 2;
22402+ }
22403+
22404+ /* Rx Queue: Release all local resets and set the watermark */
22405+ SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_CLR_RESET);
22406+ SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_F), RxWm);
22407+
22408+ /*
22409+ * Tx Queue: Release all local resets if the queue is used !
22410+ * set watermark
22411+ */
22412+ if (pPrt->PXSQSize != 0) {
22413+ SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_CLR_RESET);
22414+ SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_F), TxWm);
22415+ }
22416+
22417+ if (pPrt->PXAQSize != 0) {
22418+ SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_CLR_RESET);
22419+ SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_F), TxWm);
22420+ }
22421 }
22422 /*
22423 * Do NOT enable the descriptor poll timers here, because
22424@@ -1045,20 +1328,29 @@
22425 */
22426 static SK_U32 TestStopBit(
22427 SK_AC *pAC, /* Adapter Context */
22428-SK_IOC IoC, /* IO Context */
22429-int QuIoOffs) /* Queue IO Address Offset */
22430+SK_IOC IoC, /* I/O Context */
22431+int QuIoOffs) /* Queue I/O Address Offset */
22432 {
22433 SK_U32 QuCsr; /* CSR contents */
22434
22435 SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
22436-
22437- if ((QuCsr & (CSR_STOP | CSR_SV_IDLE)) == 0) {
22438- /* Stop Descriptor overridden by start command */
22439- SK_OUT32(IoC, Q_ADDR(QuIoOffs, Q_CSR), CSR_STOP);
22440
22441- SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
22442+ if (CHIP_ID_YUKON_2(pAC)) {
22443+ if ((QuCsr & (BMU_STOP | BMU_IDLE)) == 0) {
22444+ /* Stop Descriptor overridden by start command */
22445+ SK_OUT32(IoC, Q_ADDR(QuIoOffs, Q_CSR), BMU_STOP);
22446+
22447+ SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
22448+ }
22449+ }
22450+ else {
22451+ if ((QuCsr & (CSR_STOP | CSR_SV_IDLE)) == 0) {
22452+ /* Stop Descriptor overridden by start command */
22453+ SK_OUT32(IoC, Q_ADDR(QuIoOffs, Q_CSR), CSR_STOP);
22454+
22455+ SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
22456+ }
22457 }
22458-
22459 return(QuCsr);
22460 } /* TestStopBit */
22461
22462@@ -1082,8 +1374,8 @@
22463 * has to be stopped once before.
22464 * SK_STOP_ALL SK_STOP_TX + SK_STOP_RX
22465 *
22466- * RstMode = SK_SOFT_RST Resets the MAC. The PHY is still alive.
22467- * SK_HARD_RST Resets the MAC and the PHY.
22468+ * RstMode = SK_SOFT_RST Resets the MAC, the PHY is still alive.
22469+ * SK_HARD_RST Resets the MAC and the PHY.
22470 *
22471 * Example:
22472 * 1) A Link Down event was signaled for a port. Therefore the activity
22473@@ -1142,56 +1434,82 @@
22474 * SWITCH_PORT.
22475 */
22476 void SkGeStopPort(
22477-SK_AC *pAC, /* adapter context */
22478-SK_IOC IoC, /* I/O context */
22479-int Port, /* port to stop (MAC_1 + n) */
22480+SK_AC *pAC, /* Adapter Context */
22481+SK_IOC IoC, /* I/O Context */
22482+int Port, /* Port to stop (MAC_1 + n) */
22483 int Dir, /* Direction to Stop (SK_STOP_RX, SK_STOP_TX, SK_STOP_ALL) */
22484 int RstMode)/* Reset Mode (SK_SOFT_RST, SK_HARD_RST) */
22485 {
22486-#ifndef SK_DIAG
22487- SK_EVPARA Para;
22488-#endif /* !SK_DIAG */
22489 SK_GEPORT *pPrt;
22490- SK_U32 DWord;
22491+ SK_U32 RxCsr;
22492 SK_U32 XsCsr;
22493 SK_U32 XaCsr;
22494 SK_U64 ToutStart;
22495+ SK_U32 CsrStart;
22496+ SK_U32 CsrStop;
22497+ SK_U32 CsrIdle;
22498+ SK_U32 CsrTest;
22499+ SK_U8 rsl; /* FIFO read shadow level */
22500+ SK_U8 rl; /* FIFO read level */
22501 int i;
22502 int ToutCnt;
22503
22504 pPrt = &pAC->GIni.GP[Port];
22505
22506+ /* set the proper values of Q_CSR register layout depending on the chip */
22507+ if (CHIP_ID_YUKON_2(pAC)) {
22508+ CsrStart = BMU_START;
22509+ CsrStop = BMU_STOP;
22510+ CsrIdle = BMU_IDLE;
22511+ CsrTest = BMU_IDLE;
22512+ }
22513+ else {
22514+ CsrStart = CSR_START;
22515+ CsrStop = CSR_STOP;
22516+ CsrIdle = CSR_SV_IDLE;
22517+ CsrTest = CSR_SV_IDLE | CSR_STOP;
22518+ }
22519+
22520 if ((Dir & SK_STOP_TX) != 0) {
22521- /* disable receiver and transmitter */
22522- SkMacRxTxDisable(pAC, IoC, Port);
22523-
22524+
22525+ if (!pAC->GIni.GIAsfEnabled) {
22526+ /* disable receiver and transmitter */
22527+ SkMacRxTxDisable(pAC, IoC, Port);
22528+ }
22529+
22530 /* stop both transmit queues */
22531+ SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CsrStop);
22532+ SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CsrStop);
22533 /*
22534 * If the BMU is in the reset state CSR_STOP will terminate
22535 * immediately.
22536 */
22537- SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_STOP);
22538- SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_STOP);
22539
22540 ToutStart = SkOsGetTime(pAC);
22541 ToutCnt = 0;
22542 do {
22543- /*
22544- * Clear packet arbiter timeout to make sure
22545- * this loop will terminate.
22546- */
22547- SK_OUT16(IoC, B3_PA_CTRL, (SK_U16)((Port == MAC_1) ?
22548- PA_CLR_TO_TX1 : PA_CLR_TO_TX2));
22549-
22550- /*
22551- * If the transfer stucks at the MAC the STOP command will not
22552- * terminate if we don't flush the XMAC's transmit FIFO !
22553- */
22554- SkMacFlushTxFifo(pAC, IoC, Port);
22555+#ifdef GENESIS
22556+ if (pAC->GIni.GIGenesis) {
22557+ /* clear Tx packet arbiter timeout IRQ */
22558+ SK_OUT16(IoC, B3_PA_CTRL, (SK_U16)((Port == MAC_1) ?
22559+ PA_CLR_TO_TX1 : PA_CLR_TO_TX2));
22560+ /*
22561+ * If the transfer stucks at the XMAC the STOP command will not
22562+ * terminate if we don't flush the XMAC's transmit FIFO !
22563+ */
22564+ SkMacFlushTxFifo(pAC, IoC, Port);
22565+ }
22566+#endif /* GENESIS */
22567
22568- XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff);
22569 XaCsr = TestStopBit(pAC, IoC, pPrt->PXaQOff);
22570
22571+ if (HW_SYNC_TX_SUPPORTED(pAC)) {
22572+ XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff);
22573+ }
22574+ else {
22575+ XsCsr = XaCsr;
22576+ }
22577+
22578 if (SkOsGetTime(pAC) - ToutStart > (SK_TICKS_PER_SEC / 18)) {
22579 /*
22580 * Timeout of 1/18 second reached.
22581@@ -1199,67 +1517,115 @@
22582 */
22583 ToutCnt++;
22584 if (ToutCnt > 1) {
22585- /* Might be a problem when the driver event handler
22586- * calls StopPort again. XXX.
22587+ /*
22588+ * If BMU stop doesn't terminate, we assume that
22589+ * we have a stable state and can reset the BMU,
22590+ * the Prefetch Unit, and RAM buffer now.
22591 */
22592-
22593- /* Fatal Error, Loop aborted */
22594- SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E018,
22595- SKERR_HWI_E018MSG);
22596-#ifndef SK_DIAG
22597- Para.Para64 = Port;
22598- SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
22599-#endif /* !SK_DIAG */
22600- return;
22601+ break; /* ===> leave do/while loop here */
22602 }
22603 /*
22604- * Cache incoherency workaround: Assume a start command
22605+ * Cache incoherency workaround: assume a start command
22606 * has been lost while sending the frame.
22607 */
22608 ToutStart = SkOsGetTime(pAC);
22609
22610- if ((XsCsr & CSR_STOP) != 0) {
22611- SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_START);
22612+ if ((XsCsr & CsrStop) != 0) {
22613+ SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CsrStart);
22614 }
22615- if ((XaCsr & CSR_STOP) != 0) {
22616- SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_START);
22617+
22618+ if ((XaCsr & CsrStop) != 0) {
22619+ SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CsrStart);
22620 }
22621- }
22622
22623+ /*
22624+ * After the previous operations the X(s|a)Csr does no
22625+ * longer contain the proper values
22626+ */
22627+ XaCsr = TestStopBit(pAC, IoC, pPrt->PXaQOff);
22628+
22629+ if (HW_SYNC_TX_SUPPORTED(pAC)) {
22630+ XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff);
22631+ }
22632+ else {
22633+ XsCsr = XaCsr;
22634+ }
22635+ }
22636 /*
22637 * Because of the ASIC problem report entry from 21.08.1998 it is
22638 * required to wait until CSR_STOP is reset and CSR_SV_IDLE is set.
22639+ * (valid for GENESIS only)
22640 */
22641- } while ((XsCsr & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE ||
22642- (XaCsr & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE);
22643+ } while (((XsCsr & CsrTest) != CsrIdle ||
22644+ (XaCsr & CsrTest) != CsrIdle));
22645+
22646+ if (pAC->GIni.GIAsfEnabled) {
22647
22648- /* Reset the MAC depending on the RstMode */
22649- if (RstMode == SK_SOFT_RST) {
22650- SkMacSoftRst(pAC, IoC, Port);
22651+ pPrt->PState = (RstMode == SK_SOFT_RST) ? SK_PRT_STOP :
22652+ SK_PRT_RESET;
22653 }
22654 else {
22655- SkMacHardRst(pAC, IoC, Port);
22656- }
22657-
22658- /* Disable Force Sync bit and Enable Alloc bit */
22659- SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
22660+ /* Reset the MAC depending on the RstMode */
22661+ if (RstMode == SK_SOFT_RST) {
22662+
22663+ SkMacSoftRst(pAC, IoC, Port);
22664+ }
22665+ else {
22666+#ifdef SK_DIAG
22667+ if (HW_FEATURE(pAC, HWF_WA_DEV_472) && Port == MAC_1 &&
22668+ pAC->GIni.GP[MAC_2].PState == SK_PRT_RUN) {
22669+
22670+ pAC->GIni.GP[MAC_1].PState = SK_PRT_RESET;
22671+
22672+ /* set GPHY Control reset */
22673+ SK_OUT8(IoC, MR_ADDR(MAC_1, GPHY_CTRL), (SK_U8)GPC_RST_SET);
22674+ }
22675+ else {
22676+
22677+ SkMacHardRst(pAC, IoC, Port);
22678+ }
22679+#else /* !SK_DIAG */
22680+ SkMacHardRst(pAC, IoC, Port);
22681+#endif /* !SK_DIAG */
22682+ }
22683+ }
22684+
22685+ /* disable Force Sync bit and Enable Alloc bit */
22686+ SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
22687 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
22688-
22689+
22690 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
22691 SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), 0L);
22692 SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), 0L);
22693
22694 /* Perform a local reset of the port's Tx path */
22695+ if (CHIP_ID_YUKON_2(pAC)) {
22696+ /* Reset the PCI FIFO of the async Tx queue */
22697+ SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR),
22698+ BMU_RST_SET | BMU_FIFO_RST);
22699+
22700+ /* Reset the PCI FIFO of the sync Tx queue */
22701+ SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR),
22702+ BMU_RST_SET | BMU_FIFO_RST);
22703+
22704+ /* Reset the Tx prefetch units */
22705+ SK_OUT32(IoC, Y2_PREF_Q_ADDR(pPrt->PXaQOff, PREF_UNIT_CTRL_REG),
22706+ PREF_UNIT_RST_SET);
22707+ SK_OUT32(IoC, Y2_PREF_Q_ADDR(pPrt->PXsQOff, PREF_UNIT_CTRL_REG),
22708+ PREF_UNIT_RST_SET);
22709+ }
22710+ else {
22711+ /* Reset the PCI FIFO of the async Tx queue */
22712+ SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_SET_RESET);
22713+ /* Reset the PCI FIFO of the sync Tx queue */
22714+ SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_SET_RESET);
22715+ }
22716
22717- /* Reset the PCI FIFO of the async Tx queue */
22718- SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_SET_RESET);
22719- /* Reset the PCI FIFO of the sync Tx queue */
22720- SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_SET_RESET);
22721 /* Reset the RAM Buffer async Tx queue */
22722 SK_OUT8(IoC, RB_ADDR(pPrt->PXaQOff, RB_CTRL), RB_RST_SET);
22723 /* Reset the RAM Buffer sync Tx queue */
22724 SK_OUT8(IoC, RB_ADDR(pPrt->PXsQOff, RB_CTRL), RB_RST_SET);
22725-
22726+
22727 /* Reset Tx MAC FIFO */
22728 #ifdef GENESIS
22729 if (pAC->GIni.GIGenesis) {
22730@@ -1271,74 +1637,129 @@
22731 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_DIS);
22732 }
22733 #endif /* GENESIS */
22734-
22735+
22736 #ifdef YUKON
22737 if (pAC->GIni.GIYukon) {
22738- /* Reset TX MAC FIFO */
22739- SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_SET);
22740+ /* do the reset only if ASF is not enabled */
22741+ if (!pAC->GIni.GIAsfEnabled) {
22742+ /* Reset Tx MAC FIFO */
22743+ SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_SET);
22744+ }
22745+
22746+ /* set Pause Off */
22747+ SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_PAUSE_OFF);
22748 }
22749 #endif /* YUKON */
22750 }
22751
22752 if ((Dir & SK_STOP_RX) != 0) {
22753- /*
22754- * The RX Stop Command will not terminate if no buffers
22755- * are queued in the RxD ring. But it will always reach
22756- * the Idle state. Therefore we can use this feature to
22757- * stop the transfer of received packets.
22758- */
22759- /* stop the port's receive queue */
22760- SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_STOP);
22761-
22762- i = 100;
22763- do {
22764+
22765+ if (CHIP_ID_YUKON_2(pAC)) {
22766 /*
22767- * Clear packet arbiter timeout to make sure
22768- * this loop will terminate
22769+ * The RX Stop command will not work for Yukon-2 if the BMU does not
22770+ * reach the end of packet and since we can't make sure that we have
22771+ * incoming data, we must reset the BMU while it is not during a DMA
22772+ * transfer. Since it is possible that the RX path is still active,
22773+ * the RX RAM buffer will be stopped first, so any possible incoming
22774+ * data will not trigger a DMA. After the RAM buffer is stopped, the
22775+ * BMU is polled until any DMA in progress is ended and only then it
22776+ * will be reset.
22777 */
22778- SK_OUT16(IoC, B3_PA_CTRL, (SK_U16)((Port == MAC_1) ?
22779- PA_CLR_TO_RX1 : PA_CLR_TO_RX2));
22780
22781- DWord = TestStopBit(pAC, IoC, pPrt->PRxQOff);
22782+ /* disable the RAM Buffer receive queue */
22783+ SK_OUT8(IoC, RB_ADDR(pPrt->PRxQOff, RB_CTRL), RB_DIS_OP_MD);
22784
22785- /* timeout if i==0 (bug fix for #10748) */
22786- if (--i == 0) {
22787- SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E024,
22788- SKERR_HWI_E024MSG);
22789- break;
22790+ i = 0xffff;
22791+ while (--i) {
22792+ SK_IN8(IoC, RB_ADDR(pPrt->PRxQOff, Q_RX_RSL), &rsl);
22793+ SK_IN8(IoC, RB_ADDR(pPrt->PRxQOff, Q_RX_RL), &rl);
22794+
22795+ if (rsl == rl) {
22796+ break;
22797+ }
22798 }
22799+
22800 /*
22801- * because of the ASIC problem report entry from 21.08.98
22802- * it is required to wait until CSR_STOP is reset and
22803- * CSR_SV_IDLE is set.
22804+ * If the Rx side is blocked, the above loop cannot terminate.
22805+ * But, if there was any traffic it should be terminated, now.
22806+ * However, stop the Rx BMU and the Prefetch Unit !
22807 */
22808- } while ((DWord & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE);
22809+ SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR),
22810+ BMU_RST_SET | BMU_FIFO_RST);
22811+ /* reset the Rx prefetch unit */
22812+ SK_OUT32(IoC, Y2_PREF_Q_ADDR(pPrt->PRxQOff, PREF_UNIT_CTRL_REG),
22813+ PREF_UNIT_RST_SET);
22814+ }
22815+ else {
22816+ /*
22817+ * The RX Stop Command will not terminate if no buffers
22818+ * are queued in the RxD ring. But it will always reach
22819+ * the Idle state. Therefore we can use this feature to
22820+ * stop the transfer of received packets.
22821+ */
22822+ /* stop the port's receive queue */
22823+ SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CsrStop);
22824
22825- /* The path data transfer activity is fully stopped now */
22826+ i = 100;
22827+ do {
22828+#ifdef GENESIS
22829+ if (pAC->GIni.GIGenesis) {
22830+ /* clear Rx packet arbiter timeout IRQ */
22831+ SK_OUT16(IoC, B3_PA_CTRL, (SK_U16)((Port == MAC_1) ?
22832+ PA_CLR_TO_RX1 : PA_CLR_TO_RX2));
22833+ }
22834+#endif /* GENESIS */
22835+
22836+ RxCsr = TestStopBit(pAC, IoC, pPrt->PRxQOff);
22837+
22838+ /* timeout if i==0 (bug fix for #10748) */
22839+ if (--i == 0) {
22840+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E024,
22841+ SKERR_HWI_E024MSG);
22842+ break;
22843+ }
22844+ /*
22845+ * Because of the ASIC problem report entry from 21.08.1998 it is
22846+ * required to wait until CSR_STOP is reset and CSR_SV_IDLE is set.
22847+ * (valid for GENESIS only)
22848+ */
22849+ } while ((RxCsr & CsrTest) != CsrIdle);
22850+ /* The path data transfer activity is fully stopped now */
22851
22852- /* Perform a local reset of the port's Rx path */
22853+ /* Perform a local reset of the port's Rx path */
22854+ /* Reset the PCI FIFO of the Rx queue */
22855+ SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_SET_RESET);
22856+ }
22857
22858- /* Reset the PCI FIFO of the Rx queue */
22859- SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_SET_RESET);
22860 /* Reset the RAM Buffer receive queue */
22861 SK_OUT8(IoC, RB_ADDR(pPrt->PRxQOff, RB_CTRL), RB_RST_SET);
22862
22863 /* Reset Rx MAC FIFO */
22864 #ifdef GENESIS
22865 if (pAC->GIni.GIGenesis) {
22866-
22867+
22868 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_SET);
22869
22870 /* switch Rx LED off, stop the LED counter */
22871 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, RX_LED_INI), SK_LED_DIS);
22872 }
22873 #endif /* GENESIS */
22874-
22875 #ifdef YUKON
22876- if (pAC->GIni.GIYukon) {
22877+ if (pAC->GIni.GIYukon && !pAC->GIni.GIAsfEnabled) {
22878 /* Reset Rx MAC FIFO */
22879 SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_RST_SET);
22880 }
22881+
22882+ if (((pAC->GIni.GIChipId == CHIP_ID_YUKON) ||
22883+ (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE)) &&
22884+ (RstMode == SK_HARD_RST)) {
22885+ /* set Link Control reset */
22886+ SK_OUT8(IoC, MR_ADDR(Port, GMAC_LINK_CTRL), (SK_U8)GMLC_RST_SET);
22887+
22888+ /* clear Link Control reset */
22889+ SK_OUT8(IoC, MR_ADDR(Port, GMAC_LINK_CTRL), (SK_U8)GMLC_RST_CLR);
22890+ }
22891+
22892 #endif /* YUKON */
22893 }
22894 } /* SkGeStopPort */
22895@@ -1355,8 +1776,8 @@
22896 * nothing
22897 */
22898 static void SkGeInit0(
22899-SK_AC *pAC, /* adapter context */
22900-SK_IOC IoC) /* IO context */
22901+SK_AC *pAC, /* Adapter Context */
22902+SK_IOC IoC) /* I/O Context */
22903 {
22904 int i;
22905 SK_GEPORT *pPrt;
22906@@ -1365,6 +1786,7 @@
22907 pPrt = &pAC->GIni.GP[i];
22908
22909 pPrt->PState = SK_PRT_RESET;
22910+ pPrt->PPortUsage = SK_RED_LINK;
22911 pPrt->PRxQOff = QOffTab[i].RxQOff;
22912 pPrt->PXsQOff = QOffTab[i].XsQOff;
22913 pPrt->PXaQOff = QOffTab[i].XaQOff;
22914@@ -1393,24 +1815,30 @@
22915 pPrt->PLipaAutoNeg = (SK_U8)SK_LIPA_UNKNOWN;
22916 pPrt->PAutoNegFail = SK_FALSE;
22917 pPrt->PHWLinkUp = SK_FALSE;
22918- pPrt->PLinkBroken = SK_TRUE; /* See WA code */
22919+ pPrt->PLinkBroken = SK_TRUE; /* See WA code */
22920 pPrt->PPhyPowerState = PHY_PM_OPERATIONAL_MODE;
22921 pPrt->PMacColThres = TX_COL_DEF;
22922 pPrt->PMacJamLen = TX_JAM_LEN_DEF;
22923 pPrt->PMacJamIpgVal = TX_JAM_IPG_DEF;
22924 pPrt->PMacJamIpgData = TX_IPG_JAM_DEF;
22925+ pPrt->PMacBackOffLim = TX_BOF_LIM_DEF;
22926+ pPrt->PMacDataBlind = DATA_BLIND_DEF;
22927 pPrt->PMacIpgData = IPG_DATA_DEF;
22928 pPrt->PMacLimit4 = SK_FALSE;
22929 }
22930
22931- pAC->GIni.GIPortUsage = SK_RED_LINK;
22932 pAC->GIni.GILedBlinkCtrl = (SK_U16)OemConfig.Value;
22933- pAC->GIni.GIValIrqMask = IS_ALL_MSK;
22934+ pAC->GIni.GIChipCap = 0;
22935+
22936+ for (i = 0; i < 4; i++) {
22937+ pAC->GIni.HwF.Features[i]= 0x00000000;
22938+ pAC->GIni.HwF.OnMask[i] = 0x00000000;
22939+ pAC->GIni.HwF.OffMask[i] = 0x00000000;
22940+ }
22941
22942 } /* SkGeInit0*/
22943
22944 #ifdef SK_PCI_RESET
22945-
22946 /******************************************************************************
22947 *
22948 * SkGePciReset() - Reset PCI interface
22949@@ -1426,8 +1854,8 @@
22950 * 1: Power state could not be changed to 3.
22951 */
22952 static int SkGePciReset(
22953-SK_AC *pAC, /* adapter context */
22954-SK_IOC IoC) /* IO context */
22955+SK_AC *pAC, /* Adapter Context */
22956+SK_IOC IoC) /* I/O Context */
22957 {
22958 int i;
22959 SK_U16 PmCtlSts;
22960@@ -1450,7 +1878,7 @@
22961 /* We know the RAM Interface Arbiter is enabled. */
22962 SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D3);
22963 SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);
22964-
22965+
22966 if ((PmCtlSts & PCI_PM_STATE_MSK) != PCI_PM_STATE_D3) {
22967 return(1);
22968 }
22969@@ -1460,7 +1888,7 @@
22970
22971 /* Check for D0 state. */
22972 SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);
22973-
22974+
22975 if ((PmCtlSts & PCI_PM_STATE_MSK) != PCI_PM_STATE_D0) {
22976 return(1);
22977 }
22978@@ -1469,11 +1897,24 @@
22979 SkPciReadCfgWord(pAC, PCI_COMMAND, &PciCmd);
22980 SkPciReadCfgByte(pAC, PCI_CACHE_LSZ, &Cls);
22981 SkPciReadCfgDWord(pAC, PCI_BASE_1ST, &Bp1);
22982- SkPciReadCfgDWord(pAC, PCI_BASE_2ND, &Bp2);
22983+
22984+ /*
22985+ * Compute the location in PCI config space of BAR2
22986+ * relativ to the location of BAR1
22987+ */
22988+ if ((Bp1 & PCI_MEM_TYP_MSK) == PCI_MEM64BIT) {
22989+ /* BAR1 is 64 bits wide */
22990+ i = 8;
22991+ }
22992+ else {
22993+ i = 4;
22994+ }
22995+
22996+ SkPciReadCfgDWord(pAC, PCI_BASE_1ST + i, &Bp2);
22997 SkPciReadCfgByte(pAC, PCI_LAT_TIM, &Lat);
22998-
22999- if (PciCmd != 0 || Cls != (SK_U8)0 || Lat != (SK_U8)0 ||
23000- (Bp1 & 0xfffffff0L) != 0 || Bp2 != 1) {
23001+
23002+ if (PciCmd != 0 || Cls != 0 || (Bp1 & 0xfffffff0L) != 0 || Bp2 != 1 ||
23003+ Lat != 0) {
23004 return(1);
23005 }
23006
23007@@ -1484,9 +1925,115 @@
23008
23009 return(0);
23010 } /* SkGePciReset */
23011-
23012 #endif /* SK_PCI_RESET */
23013
23014+
23015+#ifndef SK_SLIM
23016+/******************************************************************************
23017+ *
23018+ * SkGeSetUpSupFeatures() - Collect Feature List for HW_FEATURE Macro
23019+ *
23020+ * Description:
23021+ * This function collects the available features and required
23022+ * deviation services of the Adapter and provides these
23023+ * information in the GIHwF struct. This information is used as
23024+ * default value and may be overritten by the driver using the
23025+ * SET_HW_FEATURE_MASK() macro in its Init0 phase.
23026+ *
23027+ * Notice:
23028+ * Using the On and Off mask: Never switch on the same bit in both
23029+ * masks simultaneously. However, if doing the Off mask will win.
23030+ *
23031+ * Returns:
23032+ * nothing
23033+ */
23034+static void SkGeSetUpSupFeatures(
23035+SK_AC *pAC, /* Adapter Context */
23036+SK_IOC IoC) /* I/O Context */
23037+{
23038+ int i;
23039+ SK_U16 Word;
23040+
23041+ switch (pAC->GIni.GIChipId) {
23042+ case CHIP_ID_YUKON_EC:
23043+ if (pAC->GIni.GIChipRev == CHIP_REV_YU_EC_A1) {
23044+ /* A0/A1 */
23045+ pAC->GIni.HwF.Features[HW_DEV_LIST] =
23046+ HWF_WA_DEV_42 | HWF_WA_DEV_46 | HWF_WA_DEV_43_418 |
23047+ HWF_WA_DEV_420 | HWF_WA_DEV_423 |
23048+ HWF_WA_DEV_424 | HWF_WA_DEV_425 | HWF_WA_DEV_427 |
23049+ HWF_WA_DEV_428 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
23050+ HWF_WA_DEV_4152| HWF_WA_DEV_4167;
23051+ }
23052+ else {
23053+ /* A2/A3 */
23054+ pAC->GIni.HwF.Features[HW_DEV_LIST] =
23055+ HWF_WA_DEV_424 | HWF_WA_DEV_425 | HWF_WA_DEV_427 |
23056+ HWF_WA_DEV_428 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
23057+ HWF_WA_DEV_4152| HWF_WA_DEV_4167;
23058+ }
23059+ break;
23060+ case CHIP_ID_YUKON_FE:
23061+ pAC->GIni.HwF.Features[HW_DEV_LIST] =
23062+ HWF_WA_DEV_427 | HWF_WA_DEV_4109 |
23063+ HWF_WA_DEV_4152| HWF_WA_DEV_4167;
23064+ break;
23065+ case CHIP_ID_YUKON_XL:
23066+ switch (pAC->GIni.GIChipRev) {
23067+ case CHIP_REV_YU_XL_A0: /* still needed for Diag */
23068+ pAC->GIni.HwF.Features[HW_DEV_LIST] =
23069+ HWF_WA_DEV_427 | HWF_WA_DEV_463 | HWF_WA_DEV_472 |
23070+ HWF_WA_DEV_479 | HWF_WA_DEV_483 | HWF_WA_DEV_4115 |
23071+ HWF_WA_DEV_4152| HWF_WA_DEV_4167;
23072+ break;
23073+
23074+ case CHIP_REV_YU_XL_A1:
23075+ pAC->GIni.HwF.Features[HW_DEV_LIST] =
23076+ HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
23077+ HWF_WA_DEV_4115| HWF_WA_DEV_4152| HWF_WA_DEV_4167;
23078+ break;
23079+
23080+ case CHIP_REV_YU_XL_A2:
23081+ pAC->GIni.HwF.Features[HW_DEV_LIST] =
23082+ HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
23083+ HWF_WA_DEV_4115 |HWF_WA_DEV_4167;
23084+ break;
23085+
23086+ case CHIP_REV_YU_XL_A3:
23087+ pAC->GIni.HwF.Features[HW_DEV_LIST] =
23088+ HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 |
23089+ HWF_WA_DEV_4115;
23090+ break;
23091+ }
23092+ break;
23093+ case CHIP_ID_YUKON_EC_U:
23094+ if (pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A0) {
23095+ pAC->GIni.HwF.Features[HW_DEV_LIST] =
23096+ HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109;
23097+ }
23098+ else if (pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A1) {
23099+ pAC->GIni.HwF.Features[HW_DEV_LIST] =
23100+ HWF_WA_DEV_427 | HWF_WA_DEV_4109 | HWF_WA_DEV_4185;
23101+
23102+ /* check for A1b */
23103+ SK_IN16(IoC, Q_ADDR(Q_XA1, Q_WM), &Word);
23104+ if (Word == 0) {
23105+ pAC->GIni.HwF.Features[HW_DEV_LIST] |=
23106+ HWF_WA_DEV_4185CS | HWF_WA_DEV_4200;
23107+ }
23108+ }
23109+ break;
23110+ }
23111+
23112+ for (i = 0; i < 4; i++) {
23113+ pAC->GIni.HwF.Features[i] =
23114+ (pAC->GIni.HwF.Features[i] | pAC->GIni.HwF.OnMask[i]) &
23115+ ~pAC->GIni.HwF.OffMask[i];
23116+ }
23117+} /* SkGeSetUpSupFeatures */
23118+#endif /* !SK_SLIM */
23119+
23120+
23121 /******************************************************************************
23122 *
23123 * SkGeInit1() - Level 1 Initialization
23124@@ -1509,80 +2056,235 @@
23125 * 6: HW self test failed
23126 */
23127 static int SkGeInit1(
23128-SK_AC *pAC, /* adapter context */
23129-SK_IOC IoC) /* IO context */
23130+SK_AC *pAC, /* Adapter Context */
23131+SK_IOC IoC) /* I/O Context */
23132 {
23133 SK_U8 Byte;
23134 SK_U16 Word;
23135- SK_U16 CtrlStat;
23136+ SK_U32 CtrlStat;
23137+ SK_U32 VauxAvail;
23138 SK_U32 DWord;
23139+ SK_U32 Our1;
23140+ SK_U32 PowerDownBit;
23141+ SK_BOOL FiberType;
23142+ SK_GEPORT *pPrt;
23143 int RetVal;
23144- int i;
23145+ int i, j;
23146
23147 RetVal = 0;
23148
23149- /* save CLK_RUN bits (YUKON-Lite) */
23150- SK_IN16(IoC, B0_CTST, &CtrlStat);
23151+ /* save CLK_RUN & ASF_ENABLE bits (YUKON-Lite, YUKON-EC) */
23152+ SK_IN32(IoC, B0_CTST, &CtrlStat);
23153
23154 #ifdef SK_PCI_RESET
23155 (void)SkGePciReset(pAC, IoC);
23156 #endif /* SK_PCI_RESET */
23157
23158- /* do the SW-reset */
23159- SK_OUT8(IoC, B0_CTST, CS_RST_SET);
23160-
23161 /* release the SW-reset */
23162+ /* Important: SW-reset has to be cleared here, to ensure
23163+ * the CHIP_ID can be read IO-mapped based, too -
23164+ * remember the RAP register can only be written if
23165+ * SW-reset is cleared.
23166+ */
23167 SK_OUT8(IoC, B0_CTST, CS_RST_CLR);
23168
23169+ /* read Chip Identification Number */
23170+ SK_IN8(IoC, B2_CHIP_ID, &Byte);
23171+ pAC->GIni.GIChipId = Byte;
23172+
23173+ pAC->GIni.GIAsfEnabled = SK_FALSE;
23174+
23175+ /* ASF support only for Yukon-2 */
23176+ if ((pAC->GIni.GIChipId >= CHIP_ID_YUKON_XL) &&
23177+ (pAC->GIni.GIChipId <= CHIP_ID_YUKON_EC)) {
23178+#ifdef SK_ASF
23179+ if ((CtrlStat & Y2_ASF_ENABLE) != 0) {
23180+ /* do the SW-reset only if ASF is not enabled */
23181+ pAC->GIni.GIAsfEnabled = SK_TRUE;
23182+ }
23183+#else /* !SK_ASF */
23184+
23185+ SK_IN8(IoC, B28_Y2_ASF_STAT_CMD, &Byte);
23186+
23187+ pAC->GIni.GIAsfRunning = Byte & Y2_ASF_RUNNING;
23188+
23189+ /* put ASF system in reset state */
23190+ SK_OUT8(IoC, B28_Y2_ASF_STAT_CMD, (SK_U8)Y2_ASF_RESET);
23191+
23192+ /* disable ASF Unit */
23193+ SK_OUT16(IoC, B0_CTST, Y2_ASF_DISABLE);
23194+#endif /* !SK_ASF */
23195+ }
23196+
23197+ if (!pAC->GIni.GIAsfEnabled) {
23198+ /* Yukon-2: required for Diag and Power Management */
23199+ /* set the SW-reset */
23200+ SK_OUT8(IoC, B0_CTST, CS_RST_SET);
23201+
23202+ /* release the SW-reset */
23203+ SK_OUT8(IoC, B0_CTST, CS_RST_CLR);
23204+ }
23205+
23206+ /* enable Config Write */
23207+ SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
23208+
23209 /* reset all error bits in the PCI STATUS register */
23210 /*
23211 * Note: PCI Cfg cycles cannot be used, because they are not
23212 * available on some platforms after 'boot time'.
23213 */
23214- SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);
23215-
23216- SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
23217- SK_OUT16(IoC, PCI_C(PCI_STATUS), (SK_U16)(Word | PCI_ERRBITS));
23218- SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
23219+ SK_IN16(IoC, PCI_C(pAC, PCI_STATUS), &Word);
23220+
23221+ SK_OUT16(IoC, PCI_C(pAC, PCI_STATUS), Word | (SK_U16)PCI_ERRBITS);
23222
23223 /* release Master Reset */
23224 SK_OUT8(IoC, B0_CTST, CS_MRST_CLR);
23225
23226 #ifdef CLK_RUN
23227 CtrlStat |= CS_CLK_RUN_ENA;
23228-#endif /* CLK_RUN */
23229
23230 /* restore CLK_RUN bits */
23231 SK_OUT16(IoC, B0_CTST, (SK_U16)(CtrlStat &
23232 (CS_CLK_RUN_HOT | CS_CLK_RUN_RST | CS_CLK_RUN_ENA)));
23233+#endif /* CLK_RUN */
23234+
23235+ if ((pAC->GIni.GIChipId >= CHIP_ID_YUKON_XL) &&
23236+ (pAC->GIni.GIChipId <= CHIP_ID_YUKON_FE)) {
23237+
23238+ pAC->GIni.GIYukon2 = SK_TRUE;
23239+ pAC->GIni.GIValIrqMask = Y2_IS_ALL_MSK;
23240+ pAC->GIni.GIValHwIrqMask = Y2_HWE_ALL_MSK;
23241+
23242+ VauxAvail = Y2_VAUX_AVAIL;
23243+
23244+ SK_IN32(IoC, PCI_C(pAC, PCI_OUR_STATUS), &DWord);
23245+
23246+ if ((DWord & PCI_OS_PCI_X) != 0) {
23247+#ifndef SK_SLIM
23248+ /* this is a PCI / PCI-X bus */
23249+ if ((DWord & PCI_OS_PCIX) != 0) {
23250+ /* this is a PCI-X bus */
23251+ pAC->GIni.GIPciBus = SK_PCIX_BUS;
23252+
23253+ /* PCI-X is always 64-bit wide */
23254+ pAC->GIni.GIPciSlot64 = SK_TRUE;
23255+
23256+ pAC->GIni.GIPciMode = (SK_U8)(PCI_OS_SPEED(DWord));
23257+ }
23258+ else {
23259+ /* this is a conventional PCI bus */
23260+ pAC->GIni.GIPciBus = SK_PCI_BUS;
23261+
23262+ SK_IN16(IoC, PCI_C(pAC, PCI_OUR_REG_2), &Word);
23263+
23264+ /* check if 64-bit width is used */
23265+ pAC->GIni.GIPciSlot64 = (SK_BOOL)
23266+ (((DWord & PCI_OS_PCI64B) != 0) &&
23267+ ((Word & PCI_USEDATA64) != 0));
23268+
23269+ /* check if 66 MHz PCI Clock is active */
23270+ pAC->GIni.GIPciClock66 = (SK_BOOL)((DWord & PCI_OS_PCI66M) != 0);
23271+ }
23272+#endif /* !SK_SLIM */
23273+ }
23274+ else {
23275+ /* this is a PEX bus */
23276+ pAC->GIni.GIPciBus = SK_PEX_BUS;
23277+
23278+ /* clear any PEX errors */
23279+ SK_OUT32(IoC, PCI_C(pAC, PEX_UNC_ERR_STAT), 0xffffffffUL);
23280+
23281+ SK_IN16(IoC, PCI_C(pAC, PEX_LNK_STAT), &Word);
23282+
23283+ pAC->GIni.GIPexWidth = (SK_U8)((Word & PEX_LS_LINK_WI_MSK) >> 4);
23284+ }
23285+ /*
23286+ * Yukon-2 chips family has a different way of providing
23287+ * the number of MACs available
23288+ */
23289+ pAC->GIni.GIMacsFound = 1;
23290+
23291+ SK_IN8(IoC, B2_Y2_HW_RES, &Byte);
23292+
23293+ if (CHIP_ID_YUKON_2(pAC)) {
23294+ /*
23295+ * OEM config value is overwritten and should not
23296+ * be used for Yukon-2
23297+ */
23298+ pAC->GIni.GILedBlinkCtrl |= SK_ACT_LED_BLINK;
23299+
23300+ if (CFG_LED_MODE(Byte) == CFG_LED_DUAL_ACT_LNK) {
23301+
23302+ pAC->GIni.GILedBlinkCtrl |= SK_DUAL_LED_ACT_LNK;
23303+ }
23304+ }
23305+
23306+ if ((Byte & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
23307+
23308+ SK_IN8(IoC, B2_Y2_CLK_GATE, &Byte);
23309+
23310+ if (!(Byte & Y2_STATUS_LNK2_INAC)) {
23311+ /* Link 2 activ */
23312+ pAC->GIni.GIMacsFound++;
23313+ }
23314+ }
23315+
23316+#ifdef VCPU
23317+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL) {
23318+ /* temporary WA for reported number of links */
23319+ pAC->GIni.GIMacsFound = 2;
23320+ }
23321+#endif /* VCPU */
23322+
23323+#ifdef REPLAY_TIMER
23324+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) {
23325+ SK_OUT16(IoC, PCI_C(pAC, PEX_ACK_RPLY_TOX1), 0x2710); /* 40 us */
23326+ }
23327+#endif
23328+
23329+ /* read Chip Revision */
23330+ SK_IN8(IoC, B2_MAC_CFG, &Byte);
23331+
23332+ pAC->GIni.GIChipCap = Byte & 0x0f;
23333+ }
23334+ else {
23335+ pAC->GIni.GIYukon2 = SK_FALSE;
23336+ pAC->GIni.GIValIrqMask = IS_ALL_MSK;
23337+ pAC->GIni.GIValHwIrqMask = 0; /* not activated */
23338+
23339+ VauxAvail = CS_VAUX_AVAIL;
23340+
23341+ /* read number of MACs and Chip Revision */
23342+ SK_IN8(IoC, B2_MAC_CFG, &Byte);
23343+
23344+ pAC->GIni.GIMacsFound = (Byte & CFG_SNG_MAC) ? 1 : 2;
23345+ }
23346
23347- /* read Chip Identification Number */
23348- SK_IN8(IoC, B2_CHIP_ID, &Byte);
23349- pAC->GIni.GIChipId = Byte;
23350-
23351- /* read number of MACs */
23352- SK_IN8(IoC, B2_MAC_CFG, &Byte);
23353- pAC->GIni.GIMacsFound = (Byte & CFG_SNG_MAC) ? 1 : 2;
23354-
23355 /* get Chip Revision Number */
23356 pAC->GIni.GIChipRev = (SK_U8)((Byte & CFG_CHIP_R_MSK) >> 4);
23357
23358- /* get diff. PCI parameters */
23359- SK_IN16(IoC, B0_CTST, &CtrlStat);
23360-
23361+#ifndef SK_DIAG
23362+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL &&
23363+ pAC->GIni.GIChipRev == CHIP_REV_YU_XL_A0) {
23364+ /* Yukon-2 Chip Rev. A0 */
23365+ return(6);
23366+ }
23367+#endif /* !SK_DIAG */
23368+
23369 /* read the adapters RAM size */
23370 SK_IN8(IoC, B2_E_0, &Byte);
23371-
23372+
23373 pAC->GIni.GIGenesis = SK_FALSE;
23374 pAC->GIni.GIYukon = SK_FALSE;
23375 pAC->GIni.GIYukonLite = SK_FALSE;
23376+ pAC->GIni.GIVauxAvail = SK_FALSE;
23377
23378 #ifdef GENESIS
23379 if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
23380
23381 pAC->GIni.GIGenesis = SK_TRUE;
23382
23383- if (Byte == (SK_U8)3) {
23384+ if (Byte == (SK_U8)3) {
23385 /* special case: 4 x 64k x 36, offset = 0x80000 */
23386 pAC->GIni.GIRamSize = 1024;
23387 pAC->GIni.GIRamOffs = (SK_U32)512 * 1024;
23388@@ -1591,57 +2293,83 @@
23389 pAC->GIni.GIRamSize = (int)Byte * 512;
23390 pAC->GIni.GIRamOffs = 0;
23391 }
23392- /* all GE adapters work with 53.125 MHz host clock */
23393+ /* all GENESIS adapters work with 53.125 MHz host clock */
23394 pAC->GIni.GIHstClkFact = SK_FACT_53;
23395-
23396+
23397 /* set Descr. Poll Timer Init Value to 250 ms */
23398 pAC->GIni.GIPollTimerVal =
23399 SK_DPOLL_DEF * (SK_U32)pAC->GIni.GIHstClkFact / 100;
23400 }
23401 #endif /* GENESIS */
23402-
23403+
23404 #ifdef YUKON
23405 if (pAC->GIni.GIChipId != CHIP_ID_GENESIS) {
23406-
23407+
23408 pAC->GIni.GIYukon = SK_TRUE;
23409-
23410+
23411 pAC->GIni.GIRamSize = (Byte == (SK_U8)0) ? 128 : (int)Byte * 4;
23412-
23413+
23414+#ifndef SK_SLIM
23415 pAC->GIni.GIRamOffs = 0;
23416-
23417- /* WA for chip Rev. A */
23418+
23419+ /* WA for Yukon chip Rev. A */
23420 pAC->GIni.GIWolOffs = (pAC->GIni.GIChipId == CHIP_ID_YUKON &&
23421 pAC->GIni.GIChipRev == 0) ? WOL_REG_OFFS : 0;
23422-
23423+
23424 /* get PM Capabilities of PCI config space */
23425- SK_IN16(IoC, PCI_C(PCI_PM_CAP_REG), &Word);
23426+ SK_IN16(IoC, PCI_C(pAC, PCI_PM_CAP_REG), &Word);
23427
23428 /* check if VAUX is available */
23429- if (((CtrlStat & CS_VAUX_AVAIL) != 0) &&
23430+ if (((CtrlStat & VauxAvail) != 0) &&
23431 /* check also if PME from D3cold is set */
23432 ((Word & PCI_PME_D3C_SUP) != 0)) {
23433 /* set entry in GE init struct */
23434 pAC->GIni.GIVauxAvail = SK_TRUE;
23435 }
23436-
23437- if (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) {
23438- /* this is Rev. A1 */
23439- pAC->GIni.GIYukonLite = SK_TRUE;
23440- }
23441- else {
23442- /* save Flash-Address Register */
23443- SK_IN32(IoC, B2_FAR, &DWord);
23444+#endif /* !SK_SLIM */
23445
23446- /* test Flash-Address Register */
23447- SK_OUT8(IoC, B2_FAR + 3, 0xff);
23448- SK_IN8(IoC, B2_FAR + 3, &Byte);
23449+ if (!CHIP_ID_YUKON_2(pAC)) {
23450
23451- if (Byte != 0) {
23452- /* this is Rev. A0 */
23453+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_LITE) {
23454+ /* this is Rev. A1 */
23455 pAC->GIni.GIYukonLite = SK_TRUE;
23456+ }
23457+#ifndef SK_SLIM
23458+ else {
23459+ /* save Flash-Address Register */
23460+ SK_IN32(IoC, B2_FAR, &DWord);
23461
23462- /* restore Flash-Address Register */
23463- SK_OUT32(IoC, B2_FAR, DWord);
23464+ /* test Flash-Address Register */
23465+ SK_OUT8(IoC, B2_FAR + 3, 0xff);
23466+ SK_IN8(IoC, B2_FAR + 3, &Byte);
23467+
23468+ if (Byte != 0) {
23469+ /* this is Rev. A0 */
23470+ pAC->GIni.GIYukonLite = SK_TRUE;
23471+
23472+ /* restore Flash-Address Register */
23473+ SK_OUT32(IoC, B2_FAR, DWord);
23474+ }
23475+ }
23476+#endif /* !SK_SLIM */
23477+ }
23478+ else {
23479+ /* Check for CLS = 0 (dev. #4.55) */
23480+ if (pAC->GIni.GIPciBus != SK_PEX_BUS) {
23481+ /* PCI and PCI-X */
23482+ SK_IN8(IoC, PCI_C(pAC, PCI_CACHE_LSZ), &Byte);
23483+
23484+ if (Byte == 0) {
23485+ /* set CLS to 2 if configured to 0 */
23486+ SK_OUT8(IoC, PCI_C(pAC, PCI_CACHE_LSZ), 2);
23487+ }
23488+
23489+ if (pAC->GIni.GIPciBus == SK_PCIX_BUS) {
23490+ /* set Cache Line Size opt. */
23491+ SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_1), &DWord);
23492+ DWord |= PCI_CLS_OPT;
23493+ SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_1), DWord);
23494+ }
23495 }
23496 }
23497
23498@@ -1649,138 +2377,282 @@
23499 SK_OUT8(IoC, B0_POWER_CTRL, (SK_U8)(PC_VAUX_ENA | PC_VCC_ENA |
23500 PC_VAUX_OFF | PC_VCC_ON));
23501
23502- /* read the Interrupt source */
23503- SK_IN32(IoC, B0_ISRC, &DWord);
23504-
23505- if ((DWord & IS_HW_ERR) != 0) {
23506- /* read the HW Error Interrupt source */
23507- SK_IN32(IoC, B0_HWE_ISRC, &DWord);
23508-
23509- if ((DWord & IS_IRQ_SENSOR) != 0) {
23510- /* disable HW Error IRQ */
23511- pAC->GIni.GIValIrqMask &= ~IS_HW_ERR;
23512+ Byte = 0;
23513+
23514+ if (CHIP_ID_YUKON_2(pAC)) {
23515+ switch (pAC->GIni.GIChipId) {
23516+ /* PEX adapters work with different host clock */
23517+ case CHIP_ID_YUKON_EC:
23518+ case CHIP_ID_YUKON_EC_U:
23519+ /* Yukon-EC works with 125 MHz host clock */
23520+ pAC->GIni.GIHstClkFact = SK_FACT_125;
23521+ break;
23522+ case CHIP_ID_YUKON_FE:
23523+ /* Yukon-FE works with 100 MHz host clock */
23524+ pAC->GIni.GIHstClkFact = SK_FACT_100;
23525+ break;
23526+ case CHIP_ID_YUKON_XL:
23527+ /* all Yukon-2 adapters work with 156 MHz host clock */
23528+ pAC->GIni.GIHstClkFact = 2 * SK_FACT_78;
23529+
23530+ if (pAC->GIni.GIChipRev > CHIP_REV_YU_XL_A1) {
23531+ /* enable bits are inverted */
23532+ Byte = (SK_U8)(Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
23533+ Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
23534+ Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
23535+ }
23536+ break;
23537+ default:
23538+ SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E006,
23539+ SKERR_HWI_E006MSG);
23540+ }
23541+
23542+ pAC->GIni.GIPollTimerVal =
23543+ SK_DPOLL_DEF_Y2 * (SK_U32)pAC->GIni.GIHstClkFact / 100;
23544+
23545+ /* set power down bit */
23546+ PowerDownBit = PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD;
23547+
23548+ /* disable Core Clock Division, set Clock Select to 0 (Yukon-2) */
23549+ SK_OUT32(IoC, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
23550+
23551+ /* enable MAC/PHY, PCI and Core Clock for both Links */
23552+ SK_OUT8(IoC, B2_Y2_CLK_GATE, Byte);
23553+ }
23554+ else {
23555+ /* YUKON adapters work with 78 MHz host clock */
23556+ pAC->GIni.GIHstClkFact = SK_FACT_78;
23557+
23558+ pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX; /* 215 ms */
23559+
23560+ /* read the Interrupt source */
23561+ SK_IN32(IoC, B0_ISRC, &DWord);
23562+
23563+ if ((DWord & IS_HW_ERR) != 0) {
23564+ /* read the HW Error Interrupt source */
23565+ SK_IN32(IoC, B0_HWE_ISRC, &DWord);
23566+
23567+ if ((DWord & IS_IRQ_SENSOR) != 0) {
23568+ /* disable HW Error IRQ */
23569+ pAC->GIni.GIValIrqMask &= ~IS_HW_ERR;
23570+ }
23571 }
23572+ /* set power down bit */
23573+ PowerDownBit = PCI_PHY_COMA;
23574 }
23575-
23576- for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
23577- /* set GMAC Link Control reset */
23578- SK_OUT16(IoC, MR_ADDR(i, GMAC_LINK_CTRL), GMLC_RST_SET);
23579
23580- /* clear GMAC Link Control reset */
23581- SK_OUT16(IoC, MR_ADDR(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
23582+ SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_1), &Our1);
23583+
23584+ Our1 &= ~PowerDownBit;
23585+
23586+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL &&
23587+ pAC->GIni.GIChipRev > CHIP_REV_YU_XL_A1) {
23588+ /* deassert Low Power for 1st PHY */
23589+ Our1 |= PCI_Y2_PHY1_COMA;
23590+
23591+ if (pAC->GIni.GIMacsFound > 1) {
23592+ /* deassert Low Power for 2nd PHY */
23593+ Our1 |= PCI_Y2_PHY2_COMA;
23594+ }
23595+ }
23596+ else if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) {
23597+ /* enable HW WOL */
23598+ SK_OUT16(IoC, B0_CTST, (SK_U16)Y2_HW_WOL_ON);
23599+
23600+ /* enable all clocks */
23601+ SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_3), 0);
23602+
23603+ SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_4), &DWord);
23604+
23605+ DWord &= P_ASPM_CONTROL_MSK;
23606+ /* set all bits to 0 except bits 15..12 */
23607+ SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_4), DWord);
23608+
23609+ /* set to default value */
23610+ SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_5), 0);
23611+ }
23612+
23613+ /* release PHY from PowerDown/COMA Mode */
23614+ SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_1), Our1);
23615+
23616+ if (!pAC->GIni.GIAsfEnabled) {
23617+
23618+ for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
23619+ /* set Link Control reset */
23620+ SK_OUT8(IoC, MR_ADDR(i, GMAC_LINK_CTRL), (SK_U8)GMLC_RST_SET);
23621+
23622+ /* clear Link Control reset */
23623+ SK_OUT8(IoC, MR_ADDR(i, GMAC_LINK_CTRL), (SK_U8)GMLC_RST_CLR);
23624+ }
23625 }
23626- /* all YU chips work with 78.125 MHz host clock */
23627- pAC->GIni.GIHstClkFact = SK_FACT_78;
23628-
23629- pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX; /* 215 ms */
23630 }
23631 #endif /* YUKON */
23632
23633- /* check if 64-bit PCI Slot is present */
23634- pAC->GIni.GIPciSlot64 = (SK_BOOL)((CtrlStat & CS_BUS_SLOT_SZ) != 0);
23635-
23636- /* check if 66 MHz PCI Clock is active */
23637- pAC->GIni.GIPciClock66 = (SK_BOOL)((CtrlStat & CS_BUS_CLOCK) != 0);
23638+ SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
23639+
23640+#ifndef SK_SLIM
23641+ if (!CHIP_ID_YUKON_2(pAC)) {
23642+ /* this is a conventional PCI bus */
23643+ pAC->GIni.GIPciBus = SK_PCI_BUS;
23644+
23645+ /* check if 64-bit PCI Slot is present */
23646+ pAC->GIni.GIPciSlot64 = (SK_BOOL)((CtrlStat & CS_BUS_SLOT_SZ) != 0);
23647+
23648+ /* check if 66 MHz PCI Clock is active */
23649+ pAC->GIni.GIPciClock66 = (SK_BOOL)((CtrlStat & CS_BUS_CLOCK) != 0);
23650+ }
23651
23652 /* read PCI HW Revision Id. */
23653- SK_IN8(IoC, PCI_C(PCI_REV_ID), &Byte);
23654+ SK_IN8(IoC, PCI_C(pAC, PCI_REV_ID), &Byte);
23655 pAC->GIni.GIPciHwRev = Byte;
23656
23657+ /* read connector type */
23658+ SK_IN8(IoC, B2_CONN_TYP, &pAC->GIni.GIConTyp);
23659+#endif /* !SK_SLIM */
23660+
23661 /* read the PMD type */
23662 SK_IN8(IoC, B2_PMD_TYP, &Byte);
23663- pAC->GIni.GICopperType = (SK_U8)(Byte == 'T');
23664
23665- /* read the PHY type */
23666+ pAC->GIni.GIPmdTyp = Byte;
23667+
23668+ FiberType = (Byte == 'L' || Byte == 'S' || Byte == 'P');
23669+
23670+ pAC->GIni.GICopperType = (SK_BOOL)(Byte == 'T' || Byte == '1' ||
23671+ (pAC->GIni.GIYukon2 && !FiberType));
23672+
23673+ /* read the PHY type (Yukon and Genesis) */
23674 SK_IN8(IoC, B2_E_1, &Byte);
23675
23676 Byte &= 0x0f; /* the PHY type is stored in the lower nibble */
23677 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
23678-
23679+
23680+ pPrt = &pAC->GIni.GP[i];
23681+
23682+ /* get the MAC addresses */
23683+ for (j = 0; j < 3; j++) {
23684+ SK_IN16(IoC, B2_MAC_1 + i * 8 + j * 2, &pPrt->PMacAddr[j]);
23685+ }
23686+
23687 #ifdef GENESIS
23688 if (pAC->GIni.GIGenesis) {
23689 switch (Byte) {
23690 case SK_PHY_XMAC:
23691- pAC->GIni.GP[i].PhyAddr = PHY_ADDR_XMAC;
23692+ pPrt->PhyAddr = PHY_ADDR_XMAC;
23693 break;
23694 case SK_PHY_BCOM:
23695- pAC->GIni.GP[i].PhyAddr = PHY_ADDR_BCOM;
23696- pAC->GIni.GP[i].PMSCap = (SK_U8)(SK_MS_CAP_AUTO |
23697+ pPrt->PhyAddr = PHY_ADDR_BCOM;
23698+ pPrt->PMSCap = (SK_U8)(SK_MS_CAP_AUTO |
23699 SK_MS_CAP_MASTER | SK_MS_CAP_SLAVE);
23700 break;
23701 #ifdef OTHER_PHY
23702 case SK_PHY_LONE:
23703- pAC->GIni.GP[i].PhyAddr = PHY_ADDR_LONE;
23704+ pPrt->PhyAddr = PHY_ADDR_LONE;
23705 break;
23706 case SK_PHY_NAT:
23707- pAC->GIni.GP[i].PhyAddr = PHY_ADDR_NAT;
23708+ pPrt->PhyAddr = PHY_ADDR_NAT;
23709 break;
23710 #endif /* OTHER_PHY */
23711 default:
23712 /* ERROR: unexpected PHY type detected */
23713 RetVal = 5;
23714- break;
23715 }
23716 }
23717 #endif /* GENESIS */
23718-
23719+
23720 #ifdef YUKON
23721 if (pAC->GIni.GIYukon) {
23722-
23723- if (Byte < (SK_U8)SK_PHY_MARV_COPPER) {
23724+
23725+ if (((Byte < (SK_U8)SK_PHY_MARV_COPPER) || pAC->GIni.GIYukon2) &&
23726+ !FiberType) {
23727 /* if this field is not initialized */
23728 Byte = (SK_U8)SK_PHY_MARV_COPPER;
23729-
23730+
23731 pAC->GIni.GICopperType = SK_TRUE;
23732 }
23733-
23734- pAC->GIni.GP[i].PhyAddr = PHY_ADDR_MARV;
23735-
23736+
23737+ pPrt->PhyAddr = PHY_ADDR_MARV;
23738+
23739 if (pAC->GIni.GICopperType) {
23740
23741- pAC->GIni.GP[i].PLinkSpeedCap = (SK_U8)(SK_LSPEED_CAP_AUTO |
23742- SK_LSPEED_CAP_10MBPS | SK_LSPEED_CAP_100MBPS |
23743- SK_LSPEED_CAP_1000MBPS);
23744-
23745- pAC->GIni.GP[i].PLinkSpeed = (SK_U8)SK_LSPEED_AUTO;
23746-
23747- pAC->GIni.GP[i].PMSCap = (SK_U8)(SK_MS_CAP_AUTO |
23748+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE ||
23749+ (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC &&
23750+ pAC->GIni.GIChipCap == 2)) {
23751+
23752+ pPrt->PLinkSpeedCap = (SK_U8)(SK_LSPEED_CAP_100MBPS |
23753+ SK_LSPEED_CAP_10MBPS);
23754+
23755+ pAC->GIni.GIRamSize = 4;
23756+ }
23757+ else {
23758+ pPrt->PLinkSpeedCap = (SK_U8)(SK_LSPEED_CAP_1000MBPS |
23759+ SK_LSPEED_CAP_100MBPS | SK_LSPEED_CAP_10MBPS |
23760+ SK_LSPEED_CAP_AUTO);
23761+ }
23762+
23763+ pPrt->PLinkSpeed = (SK_U8)SK_LSPEED_AUTO;
23764+
23765+ pPrt->PMSCap = (SK_U8)(SK_MS_CAP_AUTO |
23766 SK_MS_CAP_MASTER | SK_MS_CAP_SLAVE);
23767 }
23768 else {
23769 Byte = (SK_U8)SK_PHY_MARV_FIBER;
23770 }
23771 }
23772+
23773+ /* clear TWSI IRQ */
23774+ SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
23775+
23776 #endif /* YUKON */
23777-
23778- pAC->GIni.GP[i].PhyType = (int)Byte;
23779-
23780+
23781+ pPrt->PhyType = (int)Byte;
23782+
23783 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
23784- ("PHY type: %d PHY addr: %04x\n", Byte,
23785- pAC->GIni.GP[i].PhyAddr));
23786+ ("PHY type: %d PHY addr: %04x\n",
23787+ Byte, pPrt->PhyAddr));
23788 }
23789-
23790+
23791 /* get MAC Type & set function pointers dependent on */
23792 #ifdef GENESIS
23793 if (pAC->GIni.GIGenesis) {
23794-
23795+
23796 pAC->GIni.GIMacType = SK_MAC_XMAC;
23797
23798 pAC->GIni.GIFunc.pFnMacUpdateStats = SkXmUpdateStats;
23799 pAC->GIni.GIFunc.pFnMacStatistic = SkXmMacStatistic;
23800 pAC->GIni.GIFunc.pFnMacResetCounter = SkXmResetCounter;
23801 pAC->GIni.GIFunc.pFnMacOverflow = SkXmOverflowStatus;
23802+#ifdef SK_DIAG
23803+ pAC->GIni.GIFunc.pFnMacPhyRead = SkXmPhyRead;
23804+ pAC->GIni.GIFunc.pFnMacPhyWrite = SkXmPhyWrite;
23805+#else /* SK_DIAG */
23806+ pAC->GIni.GIFunc.pSkGeSirqIsr = SkGeYuSirqIsr;
23807+#endif /* !SK_DIAG */
23808 }
23809 #endif /* GENESIS */
23810-
23811+
23812 #ifdef YUKON
23813 if (pAC->GIni.GIYukon) {
23814-
23815+
23816+#ifndef SK_SLIM
23817 pAC->GIni.GIMacType = SK_MAC_GMAC;
23818
23819 pAC->GIni.GIFunc.pFnMacUpdateStats = SkGmUpdateStats;
23820 pAC->GIni.GIFunc.pFnMacStatistic = SkGmMacStatistic;
23821 pAC->GIni.GIFunc.pFnMacResetCounter = SkGmResetCounter;
23822 pAC->GIni.GIFunc.pFnMacOverflow = SkGmOverflowStatus;
23823+#endif /* !SK_SLIM */
23824+
23825+#ifdef SK_DIAG
23826+ pAC->GIni.GIFunc.pFnMacPhyRead = SkGmPhyRead;
23827+ pAC->GIni.GIFunc.pFnMacPhyWrite = SkGmPhyWrite;
23828+#else /* SK_DIAG */
23829+ if (CHIP_ID_YUKON_2(pAC)) {
23830+ pAC->GIni.GIFunc.pSkGeSirqIsr = SkYuk2SirqIsr;
23831+ }
23832+ else {
23833+ pAC->GIni.GIFunc.pSkGeSirqIsr = SkGeYuSirqIsr;
23834+ }
23835+#endif /* !SK_DIAG */
23836
23837 #ifdef SPECIAL_HANDLING
23838 if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {
23839@@ -1793,7 +2665,13 @@
23840 #endif
23841 }
23842 #endif /* YUKON */
23843-
23844+
23845+#ifndef SK_SLIM
23846+
23847+ SkGeSetUpSupFeatures(pAC, IoC);
23848+
23849+#endif /* !SK_SLIM */
23850+
23851 return(RetVal);
23852 } /* SkGeInit1 */
23853
23854@@ -1814,9 +2692,12 @@
23855 * nothing
23856 */
23857 static void SkGeInit2(
23858-SK_AC *pAC, /* adapter context */
23859-SK_IOC IoC) /* IO context */
23860+SK_AC *pAC, /* Adapter Context */
23861+SK_IOC IoC) /* I/O Context */
23862 {
23863+#ifdef YUKON
23864+ SK_U16 Word;
23865+#endif /* YUKON */
23866 #ifdef GENESIS
23867 SK_U32 DWord;
23868 #endif /* GENESIS */
23869@@ -1850,13 +2731,13 @@
23870 SkGeInitPktArb(pAC, IoC);
23871 }
23872 #endif /* GENESIS */
23873-
23874-#ifdef YUKON
23875+
23876+#ifdef xSK_DIAG
23877 if (pAC->GIni.GIYukon) {
23878 /* start Time Stamp Timer */
23879 SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8)GMT_ST_START);
23880 }
23881-#endif /* YUKON */
23882+#endif /* SK_DIAG */
23883
23884 /* enable the Tx Arbiters */
23885 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
23886@@ -1866,8 +2747,34 @@
23887 /* enable the RAM Interface Arbiter */
23888 SkGeInitRamIface(pAC, IoC);
23889
23890+#ifdef YUKON
23891+ if (CHIP_ID_YUKON_2(pAC)) {
23892+
23893+ if (pAC->GIni.GIPciBus == SK_PEX_BUS) {
23894+
23895+ SK_IN16(IoC, PCI_C(pAC, PEX_DEV_CTRL), &Word);
23896+
23897+ /* change Max. Read Request Size to 2048 bytes */
23898+ Word &= ~PEX_DC_MAX_RRS_MSK;
23899+ Word |= PEX_DC_MAX_RD_RQ_SIZE(4);
23900+
23901+ SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
23902+
23903+ SK_OUT16(IoC, PCI_C(pAC, PEX_DEV_CTRL), Word);
23904+
23905+ SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
23906+ }
23907+
23908+ /*
23909+ * Writing the HW Error Mask Reg. will not generate an IRQ
23910+ * as long as the B0_IMSK is not set by the driver.
23911+ */
23912+ SK_OUT32(IoC, B0_HWE_IMSK, pAC->GIni.GIValHwIrqMask);
23913+ }
23914+#endif /* YUKON */
23915 } /* SkGeInit2 */
23916
23917+
23918 /******************************************************************************
23919 *
23920 * SkGeInit() - Initialize the GE Adapter with the specified level.
23921@@ -1889,7 +2796,7 @@
23922 * if Number of MACs > SK_MAX_MACS
23923 *
23924 * After returning from Level 0 the adapter
23925- * may be accessed with IO operations.
23926+ * may be accessed with I/O operations.
23927 *
23928 * Level 2: start the Blink Source Counter
23929 *
23930@@ -1898,14 +2805,14 @@
23931 * 1: Number of MACs exceeds SK_MAX_MACS (after level 1)
23932 * 2: Adapter not present or not accessible
23933 * 3: Illegal initialization level
23934- * 4: Initialization Level 1 Call missing
23935+ * 4: Initialization level 1 call missing
23936 * 5: Unexpected PHY type detected
23937 * 6: HW self test failed
23938 */
23939 int SkGeInit(
23940-SK_AC *pAC, /* adapter context */
23941-SK_IOC IoC, /* IO context */
23942-int Level) /* initialization level */
23943+SK_AC *pAC, /* Adapter Context */
23944+SK_IOC IoC, /* I/O Context */
23945+int Level) /* Initialization Level */
23946 {
23947 int RetVal; /* return value */
23948 SK_U32 DWord;
23949@@ -1920,7 +2827,7 @@
23950 SkGeInit0(pAC, IoC);
23951 pAC->GIni.GILevel = SK_INIT_DATA;
23952 break;
23953-
23954+
23955 case SK_INIT_IO:
23956 /* Initialization Level 1 */
23957 RetVal = SkGeInit1(pAC, IoC);
23958@@ -1932,22 +2839,24 @@
23959 SK_OUT32(IoC, B2_IRQM_INI, SK_TEST_VAL);
23960 SK_IN32(IoC, B2_IRQM_INI, &DWord);
23961 SK_OUT32(IoC, B2_IRQM_INI, 0L);
23962-
23963+
23964 if (DWord != SK_TEST_VAL) {
23965 RetVal = 2;
23966 break;
23967 }
23968
23969+#ifdef DEBUG
23970 /* check if the number of GIMacsFound matches SK_MAX_MACS */
23971 if (pAC->GIni.GIMacsFound > SK_MAX_MACS) {
23972 RetVal = 1;
23973 break;
23974 }
23975+#endif /* DEBUG */
23976
23977 /* Level 1 successfully passed */
23978 pAC->GIni.GILevel = SK_INIT_IO;
23979 break;
23980-
23981+
23982 case SK_INIT_RUN:
23983 /* Initialization Level 2 */
23984 if (pAC->GIni.GILevel != SK_INIT_IO) {
23985@@ -1957,12 +2866,13 @@
23986 RetVal = 4;
23987 break;
23988 }
23989+
23990 SkGeInit2(pAC, IoC);
23991
23992 /* Level 2 successfully passed */
23993 pAC->GIni.GILevel = SK_INIT_RUN;
23994 break;
23995-
23996+
23997 default:
23998 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E003, SKERR_HWI_E003MSG);
23999 RetVal = 3;
24000@@ -1985,77 +2895,82 @@
24001 * nothing
24002 */
24003 void SkGeDeInit(
24004-SK_AC *pAC, /* adapter context */
24005-SK_IOC IoC) /* IO context */
24006+SK_AC *pAC, /* Adapter Context */
24007+SK_IOC IoC) /* I/O Context */
24008 {
24009 int i;
24010 SK_U16 Word;
24011
24012-#ifdef SK_PHY_LP_MODE
24013- SK_U8 Byte;
24014+#ifdef SK_PHY_LP_MODE_DEEP_SLEEP
24015 SK_U16 PmCtlSts;
24016-#endif /* SK_PHY_LP_MODE */
24017+#endif
24018
24019 #if (!defined(SK_SLIM) && !defined(VCPU))
24020 /* ensure I2C is ready */
24021 SkI2cWaitIrq(pAC, IoC);
24022-#endif
24023-
24024- /* stop all current transfer activity */
24025- for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
24026- if (pAC->GIni.GP[i].PState != SK_PRT_STOP &&
24027- pAC->GIni.GP[i].PState != SK_PRT_RESET) {
24028-
24029- SkGeStopPort(pAC, IoC, i, SK_STOP_ALL, SK_HARD_RST);
24030- }
24031- }
24032+#endif
24033
24034-#ifdef SK_PHY_LP_MODE
24035- /*
24036+#ifdef SK_PHY_LP_MODE_DEEP_SLEEP
24037+ /*
24038 * for power saving purposes within mobile environments
24039- * we set the PHY to coma mode and switch to D3 power state.
24040+ * we set the PHY to coma mode.
24041 */
24042- if (pAC->GIni.GIYukonLite &&
24043- pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3) {
24044+#ifdef XXX
24045+ if (pAC->GIni.GIVauxAvail) {
24046+ /* switch power to VAUX */
24047+ SK_OUT8(IoC, B0_POWER_CTRL, (SK_U8)(PC_VAUX_ENA | PC_VCC_ENA |
24048+ PC_VAUX_ON | PC_VCC_OFF));
24049+ }
24050+#endif /* XXX */
24051+
24052+ if (CHIP_ID_YUKON_2(pAC) && /* pAC->GIni.GIMacsFound == 1 && */
24053+ !pAC->GIni.GIAsfEnabled
24054+#ifdef XXX
24055+ || (pAC->GIni.GIYukonLite && pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3)
24056+#endif /* XXX */
24057+ ) {
24058+
24059+ /* flag for SkGmEnterLowPowerMode() that the call was from here */
24060+ pAC->GIni.GILevel = SK_INIT_IO;
24061
24062 /* for all ports switch PHY to coma mode */
24063 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
24064-
24065- SkGmEnterLowPowerMode(pAC, IoC, i, PHY_PM_DEEP_SLEEP);
24066- }
24067-
24068- if (pAC->GIni.GIVauxAvail) {
24069- /* switch power to VAUX */
24070- Byte = PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF;
24071
24072- SK_OUT8(IoC, B0_POWER_CTRL, Byte);
24073+ (void)SkGmEnterLowPowerMode(pAC, IoC, i, PHY_PM_DEEP_SLEEP);
24074 }
24075-
24076- /* switch to D3 state */
24077- SK_IN16(IoC, PCI_C(PCI_PM_CTL_STS), &PmCtlSts);
24078-
24079- PmCtlSts |= PCI_PM_STATE_D3;
24080+ }
24081+#else /* !SK_PHY_LP_MODE_DEEP_SLEEP */
24082
24083- SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
24084+ if (!pAC->GIni.GIAsfEnabled) {
24085+ /* stop all current transfer activity */
24086+ for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
24087+ if (pAC->GIni.GP[i].PState != SK_PRT_STOP &&
24088+ pAC->GIni.GP[i].PState != SK_PRT_RESET) {
24089
24090- SK_OUT16(IoC, PCI_C(PCI_PM_CTL_STS), PmCtlSts);
24091+ SkGeStopPort(pAC, IoC, i, SK_STOP_ALL, SK_HARD_RST);
24092+ }
24093+ }
24094 }
24095-#endif /* SK_PHY_LP_MODE */
24096
24097- /* Reset all bits in the PCI STATUS register */
24098+ /* reset all bits in the PCI STATUS register */
24099 /*
24100 * Note: PCI Cfg cycles cannot be used, because they are not
24101 * available on some platforms after 'boot time'.
24102 */
24103- SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);
24104-
24105+ SK_IN16(IoC, PCI_C(pAC, PCI_STATUS), &Word);
24106+
24107 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
24108- SK_OUT16(IoC, PCI_C(PCI_STATUS), (SK_U16)(Word | PCI_ERRBITS));
24109+
24110+ SK_OUT16(IoC, PCI_C(pAC, PCI_STATUS), Word | (SK_U16)PCI_ERRBITS);
24111+
24112 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
24113
24114- /* do the reset, all LEDs are switched off now */
24115- SK_OUT8(IoC, B0_CTST, CS_RST_SET);
24116-
24117+ if (!pAC->GIni.GIAsfEnabled) {
24118+ /* set the SW-reset */
24119+ SK_OUT8(IoC, B0_CTST, CS_RST_SET);
24120+ }
24121+#endif /* !SK_PHY_LP_MODE_DEEP_SLEEP */
24122+
24123 pAC->GIni.GILevel = SK_INIT_DATA;
24124 } /* SkGeDeInit */
24125
24126@@ -2089,8 +3004,8 @@
24127 * 2: The port has to be stopped before it can be initialized again.
24128 */
24129 int SkGeInitPort(
24130-SK_AC *pAC, /* adapter context */
24131-SK_IOC IoC, /* IO context */
24132+SK_AC *pAC, /* Adapter Context */
24133+SK_IOC IoC, /* I/O Context */
24134 int Port) /* Port to configure */
24135 {
24136 SK_GEPORT *pPrt;
24137@@ -2101,8 +3016,8 @@
24138 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E004, SKERR_HWI_E004MSG);
24139 return(1);
24140 }
24141-
24142- if (pPrt->PState == SK_PRT_INIT || pPrt->PState == SK_PRT_RUN) {
24143+
24144+ if (pPrt->PState >= SK_PRT_INIT) {
24145 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E005, SKERR_HWI_E005MSG);
24146 return(2);
24147 }
24148@@ -2119,29 +3034,29 @@
24149 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_ENA);
24150 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, RX_LED_INI), SK_LED_ENA);
24151 /* The Link LED is initialized by RLMT or Diagnostics itself */
24152-
24153+
24154 SkXmInitMac(pAC, IoC, Port);
24155 }
24156 #endif /* GENESIS */
24157-
24158+
24159 #ifdef YUKON
24160 if (pAC->GIni.GIYukon) {
24161
24162 SkGmInitMac(pAC, IoC, Port);
24163 }
24164 #endif /* YUKON */
24165-
24166+
24167 /* do NOT initialize the Link Sync Counter */
24168
24169 SkGeInitMacFifo(pAC, IoC, Port);
24170-
24171+
24172 SkGeInitRamBufs(pAC, IoC, Port);
24173-
24174+
24175 if (pPrt->PXSQSize != 0) {
24176 /* enable Force Sync bit if synchronous queue available */
24177 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_ENA_FSYNC);
24178 }
24179-
24180+
24181 SkGeInitBmu(pAC, IoC, Port);
24182
24183 /* mark port as initialized */
24184@@ -2149,3 +3064,192 @@
24185
24186 return(0);
24187 } /* SkGeInitPort */
24188+
24189+
24190+#if (defined(YUK2) && !defined(SK_SLIM))
24191+/******************************************************************************
24192+ *
24193+ * SkGeRamWrite() - Writes One quadword to RAM
24194+ *
24195+ * Returns:
24196+ * 0
24197+ */
24198+static void SkGeRamWrite(
24199+SK_AC *pAC, /* Adapter Context */
24200+SK_IOC IoC, /* I/O Context */
24201+SK_U32 Addr, /* Address to be written to (in quadwords) */
24202+SK_U32 LowDword, /* Lower Dword to be written */
24203+SK_U32 HighDword, /* Upper Dword to be written */
24204+int Port) /* Select RAM buffer (Yukon-2 has 2 RAM buffers) */
24205+{
24206+ SK_OUT32(IoC, SELECT_RAM_BUFFER(Port, B3_RAM_ADDR), Addr);
24207+
24208+ /* Write Access is initiated by writing the upper Dword */
24209+ SK_OUT32(IoC, SELECT_RAM_BUFFER(Port, B3_RAM_DATA_LO), LowDword);
24210+ SK_OUT32(IoC, SELECT_RAM_BUFFER(Port, B3_RAM_DATA_HI), HighDword);
24211+}
24212+
24213+/******************************************************************************
24214+ *
24215+ * SkYuk2RestartRxBmu() - Restart Receive BMU on Yukon-2
24216+ *
24217+ * return:
24218+ * 0 o.k.
24219+ * 1 timeout
24220+ */
24221+int SkYuk2RestartRxBmu(
24222+SK_AC *pAC, /* Adapter Context */
24223+SK_IOC IoC, /* I/O Context */
24224+int Port) /* Port Index (MAC_1 + n) */
24225+{
24226+ SK_U16 Word;
24227+ SK_U16 MacCtrl;
24228+ SK_U16 RxCtrl;
24229+ SK_U16 FlushMask;
24230+ SK_U16 FlushTrsh;
24231+ SK_U32 RamAdr;
24232+ SK_U32 StartTime;
24233+ SK_U32 CurrTime;
24234+ SK_U32 Delta;
24235+ SK_U32 TimeOut;
24236+ SK_GEPORT *pPrt; /* GIni Port struct pointer */
24237+ int Rtv;
24238+
24239+ Rtv = 0;
24240+
24241+ pPrt = &pAC->GIni.GP[Port];
24242+
24243+/*
24244+ 1. save Rx MAC FIFO Flush Mask and Rx MAC FIFO Flush Threshold
24245+ 2. save GMAC Rx Control Register
24246+ 3. re-initialize MAC Rx FIFO, Rx RAM Buffer Queue, PCI Rx FIFO,
24247+ Rx BMU and Rx Prefetch Unit of the link.
24248+ 4. set Rx MAC FIFO Flush Mask to 0xffff
24249+ set Rx MAC FIFO Flush Threshold to a high value, e.g. 0x20
24250+ 5. set GMAC to loopback mode and switch GMAC back to Rx/Tx enable
24251+ 6. clear Rx/Tx Frame Complete IRQ in Rx/T MAC FIFO Control Register
24252+ 7. send one packet with a size of 64bytes (size below flush threshold)
24253+ from TXA RAM Buffer Queue to set the rx_sop flop:
24254+ - set TxAQ Write Pointer to (packet size in qwords + 2)
24255+ - set TxAQ Level to (packet size in qwords + 2)
24256+ - write Internal Status Word 1 and 2 to TxAQ RAM Buffer Queue QWord 0,1
24257+ according to figure 61 on page 330 of Yukon-2 Spec.
24258+ - write MAC header with Destination Address = own MAC address to
24259+ TxAQ RAM Buffer Queue QWords 2 and 3
24260+ - set TxAQ Packet Counter to 1 -> packet is transmitted immediately
24261+ 8. poll GMAC IRQ Source Register for IRQ Rx/Tx Frame Complete
24262+ 9. restore GMAC Rx Control Register
24263+10. restore Rx MAC FIFO Flush Mask and Rx MAC FIFO Flush Threshold
24264+11. set GMAC back to GMII mode
24265+*/
24266+
24267+ /* save Rx GMAC FIFO Flush Mask */
24268+ SK_IN16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), &FlushMask);
24269+
24270+ /* save Rx GMAC FIFO Flush Threshold */
24271+ SK_IN16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), &FlushTrsh);
24272+
24273+ /* save GMAC Rx Control Register */
24274+ GM_IN16(IoC, Port, GM_RX_CTRL, &RxCtrl);
24275+
24276+ /* configure the GMAC FIFOs */
24277+ SkGeInitMacFifo(pAC, IoC, Port);
24278+
24279+ SkGeInitRamBufs(pAC, IoC, Port);
24280+
24281+ SkGeInitBmu(pAC, IoC, Port);
24282+
24283+ /* configure Rx GMAC FIFO */
24284+ SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), GMF_RX_CTRL_DEF);
24285+
24286+ /* set Rx GMAC FIFO Flush Mask */
24287+ SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), 0xffff);
24288+
24289+ /* set Rx GMAC FIFO Flush Threshold */
24290+ SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), 0x20);
24291+
24292+ /* set to promiscuous mode */
24293+ Word = RxCtrl & ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
24294+
24295+ /* set GMAC Rx Control Register */
24296+ GM_OUT16(IoC, Port, GM_RX_CTRL, Word);
24297+
24298+ /* get General Purpose Control */
24299+ GM_IN16(IoC, Port, GM_GP_CTRL, &MacCtrl);
24300+
24301+ /* enable MAC Loopback Mode*/
24302+ GM_OUT16(IoC, Port, GM_GP_CTRL, MacCtrl | GM_GPCR_LOOP_ENA);
24303+
24304+ /* enable MAC Loopback Mode and Rx/Tx */
24305+ GM_OUT16(IoC, Port, GM_GP_CTRL, MacCtrl | GM_GPCR_LOOP_ENA |
24306+ GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
24307+
24308+ /* clear GMAC IRQ Rx Frame Complete */
24309+ SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_CLI_RX_FC);
24310+
24311+ /* clear GMAC IRQ Tx Frame Complete */
24312+ SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_CLI_TX_FC);
24313+
24314+ /* send one packet with a size of 64bytes from RAM buffer*/
24315+
24316+ RamAdr = pPrt->PXaQRamStart / 8;
24317+
24318+ SK_OUT32(IoC, RB_ADDR(pPrt->PXaQOff, RB_WP), RamAdr + 10);
24319+
24320+ SK_OUT32(IoC, RB_ADDR(pPrt->PXaQOff, RB_LEV), 10);
24321+
24322+ /* write 1st status quad word (packet end address in RAM, packet length */
24323+ SkGeRamWrite(pAC, IoC, RamAdr, (RamAdr + 9) << 16, 64, Port);
24324+
24325+ /* write 2nd status quad word */
24326+ SkGeRamWrite(pAC, IoC, RamAdr + 1, 0, 0, Port);
24327+
24328+ /* write DA to MAC header */
24329+ SkGeRamWrite(pAC, IoC, RamAdr + 2, *(SK_U32 *)&pPrt->PMacAddr[0],
24330+ *(SK_U32 *)&pPrt->PMacAddr[2], Port);
24331+
24332+ SK_OUT32(IoC, RB_ADDR(pPrt->PXaQOff, RB_PC), 1);
24333+
24334+ SK_IN32(IoC, GMAC_TI_ST_VAL, &StartTime);
24335+
24336+ /* set timeout to 10 ms */
24337+ TimeOut = HW_MS_TO_TICKS(pAC, 10);
24338+
24339+ do {
24340+ SK_IN32(IoC, GMAC_TI_ST_VAL, &CurrTime);
24341+
24342+ if (CurrTime >= StartTime) {
24343+ Delta = CurrTime - StartTime;
24344+ }
24345+ else {
24346+ Delta = CurrTime + ~StartTime + 1;
24347+ }
24348+
24349+ if (Delta > TimeOut) {
24350+ Rtv = 1;
24351+ break;
24352+ }
24353+
24354+ /* read the GMAC Interrupt source register */
24355+ SK_IN16(IoC, MR_ADDR(Port, GMAC_IRQ_SRC), &Word);
24356+
24357+ } while ((Word & (GM_IS_TX_COMPL | GM_IS_RX_COMPL)) !=
24358+ (GM_IS_TX_COMPL | GM_IS_RX_COMPL));
24359+
24360+ /* disable MAC Loopback Mode and Rx/Tx */
24361+ GM_OUT16(IoC, Port, GM_GP_CTRL, MacCtrl);
24362+
24363+ /* restore GMAC Rx Control Register */
24364+ GM_OUT16(IoC, Port, GM_RX_CTRL, RxCtrl);
24365+
24366+ /* restore Rx GMAC FIFO Flush Mask */
24367+ SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), FlushMask);
24368+
24369+ /* restore Rx GMAC FIFO Flush Threshold */
24370+ SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), FlushTrsh);
24371+
24372+ return(Rtv);
24373+
24374+} /* SkYuk2RestartRxBmu */
24375+#endif /* YUK2 && !SK_SLIM */
24376+
24377diff -ruN linux/drivers/net/sk98lin/skgemib.c linux-new/drivers/net/sk98lin/skgemib.c
24378--- linux/drivers/net/sk98lin/skgemib.c 2006-04-11 19:19:28.000000000 +0200
24379+++ linux-new/drivers/net/sk98lin/skgemib.c 2006-01-18 14:37:24.000000000 +0100
24380@@ -1,1082 +1,1264 @@
24381-/*****************************************************************************
24382- *
24383- * Name: skgemib.c
24384- * Project: GEnesis, PCI Gigabit Ethernet Adapter
24385- * Version: $Revision$
24386- * Date: $Date$
24387- * Purpose: Private Network Management Interface Management Database
24388- *
24389- ****************************************************************************/
24390-
24391-/******************************************************************************
24392- *
24393- * (C)Copyright 1998-2002 SysKonnect GmbH.
24394- * (C)Copyright 2002-2003 Marvell.
24395- *
24396- * This program is free software; you can redistribute it and/or modify
24397- * it under the terms of the GNU General Public License as published by
24398- * the Free Software Foundation; either version 2 of the License, or
24399- * (at your option) any later version.
24400- *
24401- * The information in this file is provided "AS IS" without warranty.
24402- *
24403- ******************************************************************************/
24404-
24405-/*
24406- * PRIVATE OID handler function prototypes
24407- */
24408-PNMI_STATIC int Addr(SK_AC *pAC, SK_IOC IoC, int action,
24409- SK_U32 Id, char *pBuf, unsigned int *pLen, SK_U32 Instance,
24410- unsigned int TableIndex, SK_U32 NetIndex);
24411-PNMI_STATIC int CsumStat(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
24412- char *pBuf, unsigned int *pLen, SK_U32 Instance,
24413- unsigned int TableIndex, SK_U32 NetIndex);
24414-PNMI_STATIC int General(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
24415- char *pBuf, unsigned int *pLen, SK_U32 Instance,
24416- unsigned int TableIndex, SK_U32 NetIndex);
24417-PNMI_STATIC int Mac8023Stat(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
24418- char *pBuf, unsigned int *pLen, SK_U32 Instance,
24419- unsigned int TableIndex, SK_U32 NetIndex);
24420-PNMI_STATIC int MacPrivateConf(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
24421- char *pBuf, unsigned int *pLen, SK_U32 Instance,
24422- unsigned int TableIndex, SK_U32 NetIndex);
24423-PNMI_STATIC int MacPrivateStat(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
24424- char *pBuf, unsigned int *pLen, SK_U32 Instance,
24425- unsigned int TableIndex, SK_U32 NetIndex);
24426-PNMI_STATIC int Monitor(SK_AC *pAC, SK_IOC IoC, int action,
24427- SK_U32 Id, char *pBuf, unsigned int *pLen, SK_U32 Instance,
24428- unsigned int TableIndex, SK_U32 NetIndex);
24429-PNMI_STATIC int OidStruct(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
24430- char *pBuf, unsigned int *pLen, SK_U32 Instance,
24431- unsigned int TableIndex, SK_U32 NetIndex);
24432-PNMI_STATIC int Perform(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
24433- char *pBuf, unsigned int* pLen, SK_U32 Instance,
24434- unsigned int TableIndex, SK_U32 NetIndex);
24435-PNMI_STATIC int Rlmt(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
24436- char *pBuf, unsigned int *pLen, SK_U32 Instance,
24437- unsigned int TableIndex, SK_U32 NetIndex);
24438-PNMI_STATIC int RlmtStat(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
24439- char *pBuf, unsigned int *pLen, SK_U32 Instance,
24440- unsigned int TableIndex, SK_U32 NetIndex);
24441-PNMI_STATIC int SensorStat(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
24442- char *pBuf, unsigned int *pLen, SK_U32 Instance,
24443- unsigned int TableIndex, SK_U32 NetIndex);
24444-PNMI_STATIC int Vpd(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
24445- char *pBuf, unsigned int *pLen, SK_U32 Instance,
24446- unsigned int TableIndex, SK_U32 NetIndex);
24447-PNMI_STATIC int Vct(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
24448- char *pBuf, unsigned int *pLen, SK_U32 Instance,
24449- unsigned int TableIndex, SK_U32 NetIndex);
24450-
24451-#ifdef SK_POWER_MGMT
24452-PNMI_STATIC int PowerManagement(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
24453- char *pBuf, unsigned int *pLen, SK_U32 Instance,
24454- unsigned int TableIndex, SK_U32 NetIndex);
24455-#endif /* SK_POWER_MGMT */
24456-
24457-#ifdef SK_DIAG_SUPPORT
24458-PNMI_STATIC int DiagActions(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,
24459- char *pBuf, unsigned int *pLen, SK_U32 Instance,
24460- unsigned int TableIndex, SK_U32 NetIndex);
24461-#endif /* SK_DIAG_SUPPORT */
24462-
24463-
24464-/* defines *******************************************************************/
24465-#define ID_TABLE_SIZE (sizeof(IdTable)/sizeof(IdTable[0]))
24466-
24467-
24468-/* global variables **********************************************************/
24469-
24470-/*
24471- * Table to correlate OID with handler function and index to
24472- * hardware register stored in StatAddress if applicable.
24473- */
24474-PNMI_STATIC const SK_PNMI_TAB_ENTRY IdTable[] = {
24475- {OID_GEN_XMIT_OK,
24476- 0,
24477- 0,
24478- 0,
24479- SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX},
24480- {OID_GEN_RCV_OK,
24481- 0,
24482- 0,
24483- 0,
24484- SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX},
24485- {OID_GEN_XMIT_ERROR,
24486- 0,
24487- 0,
24488- 0,
24489- SK_PNMI_RO, General, 0},
24490- {OID_GEN_RCV_ERROR,
24491- 0,
24492- 0,
24493- 0,
24494- SK_PNMI_RO, General, 0},
24495- {OID_GEN_RCV_NO_BUFFER,
24496- 0,
24497- 0,
24498- 0,
24499- SK_PNMI_RO, General, 0},
24500- {OID_GEN_DIRECTED_FRAMES_XMIT,
24501- 0,
24502- 0,
24503- 0,
24504- SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_UNICAST},
24505- {OID_GEN_MULTICAST_FRAMES_XMIT,
24506- 0,
24507- 0,
24508- 0,
24509- SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_MULTICAST},
24510- {OID_GEN_BROADCAST_FRAMES_XMIT,
24511- 0,
24512- 0,
24513- 0,
24514- SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_BROADCAST},
24515- {OID_GEN_DIRECTED_FRAMES_RCV,
24516- 0,
24517- 0,
24518- 0,
24519- SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_UNICAST},
24520- {OID_GEN_MULTICAST_FRAMES_RCV,
24521- 0,
24522- 0,
24523- 0,
24524- SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_MULTICAST},
24525- {OID_GEN_BROADCAST_FRAMES_RCV,
24526- 0,
24527- 0,
24528- 0,
24529- SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_BROADCAST},
24530- {OID_GEN_RCV_CRC_ERROR,
24531- 0,
24532- 0,
24533- 0,
24534- SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_FCS},
24535- {OID_GEN_TRANSMIT_QUEUE_LENGTH,
24536- 0,
24537- 0,
24538- 0,
24539- SK_PNMI_RO, General, 0},
24540- {OID_802_3_PERMANENT_ADDRESS,
24541- 0,
24542- 0,
24543- 0,
24544- SK_PNMI_RO, Mac8023Stat, 0},
24545- {OID_802_3_CURRENT_ADDRESS,
24546- 0,
24547- 0,
24548- 0,
24549- SK_PNMI_RO, Mac8023Stat, 0},
24550- {OID_802_3_RCV_ERROR_ALIGNMENT,
24551- 0,
24552- 0,
24553- 0,
24554- SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_FRAMING},
24555- {OID_802_3_XMIT_ONE_COLLISION,
24556- 0,
24557- 0,
24558- 0,
24559- SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_SINGLE_COL},
24560- {OID_802_3_XMIT_MORE_COLLISIONS,
24561- 0,
24562- 0,
24563- 0,
24564- SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_MULTI_COL},
24565- {OID_802_3_XMIT_DEFERRED,
24566- 0,
24567- 0,
24568- 0,
24569- SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_DEFFERAL},
24570- {OID_802_3_XMIT_MAX_COLLISIONS,
24571- 0,
24572- 0,
24573- 0,
24574- SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_EXCESS_COL},
24575- {OID_802_3_RCV_OVERRUN,
24576- 0,
24577- 0,
24578- 0,
24579- SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_OVERFLOW},
24580- {OID_802_3_XMIT_UNDERRUN,
24581- 0,
24582- 0,
24583- 0,
24584- SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_UNDERRUN},
24585- {OID_802_3_XMIT_TIMES_CRS_LOST,
24586- 0,
24587- 0,
24588- 0,
24589- SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_CARRIER},
24590- {OID_802_3_XMIT_LATE_COLLISIONS,
24591- 0,
24592- 0,
24593- 0,
24594- SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_LATE_COL},
24595-#ifdef SK_POWER_MGMT
24596- {OID_PNP_CAPABILITIES,
24597- 0,
24598- 0,
24599- 0,
24600- SK_PNMI_RO, PowerManagement, 0},
24601- {OID_PNP_SET_POWER,
24602- 0,
24603- 0,
24604- 0,
24605- SK_PNMI_WO, PowerManagement, 0},
24606- {OID_PNP_QUERY_POWER,
24607- 0,
24608- 0,
24609- 0,
24610- SK_PNMI_RO, PowerManagement, 0},
24611- {OID_PNP_ADD_WAKE_UP_PATTERN,
24612- 0,
24613- 0,
24614- 0,
24615- SK_PNMI_WO, PowerManagement, 0},
24616- {OID_PNP_REMOVE_WAKE_UP_PATTERN,
24617- 0,
24618- 0,
24619- 0,
24620- SK_PNMI_WO, PowerManagement, 0},
24621- {OID_PNP_ENABLE_WAKE_UP,
24622- 0,
24623- 0,
24624- 0,
24625- SK_PNMI_RW, PowerManagement, 0},
24626-#endif /* SK_POWER_MGMT */
24627-#ifdef SK_DIAG_SUPPORT
24628- {OID_SKGE_DIAG_MODE,
24629- 0,
24630- 0,
24631- 0,
24632- SK_PNMI_RW, DiagActions, 0},
24633-#endif /* SK_DIAG_SUPPORT */
24634- {OID_SKGE_MDB_VERSION,
24635- 1,
24636- 0,
24637- SK_PNMI_MAI_OFF(MgmtDBVersion),
24638- SK_PNMI_RO, General, 0},
24639- {OID_SKGE_SUPPORTED_LIST,
24640- 0,
24641- 0,
24642- 0,
24643- SK_PNMI_RO, General, 0},
24644- {OID_SKGE_ALL_DATA,
24645- 0,
24646- 0,
24647- 0,
24648- SK_PNMI_RW, OidStruct, 0},
24649- {OID_SKGE_VPD_FREE_BYTES,
24650- 1,
24651- 0,
24652- SK_PNMI_MAI_OFF(VpdFreeBytes),
24653- SK_PNMI_RO, Vpd, 0},
24654- {OID_SKGE_VPD_ENTRIES_LIST,
24655- 1,
24656- 0,
24657- SK_PNMI_MAI_OFF(VpdEntriesList),
24658- SK_PNMI_RO, Vpd, 0},
24659- {OID_SKGE_VPD_ENTRIES_NUMBER,
24660- 1,
24661- 0,
24662- SK_PNMI_MAI_OFF(VpdEntriesNumber),
24663- SK_PNMI_RO, Vpd, 0},
24664- {OID_SKGE_VPD_KEY,
24665- SK_PNMI_VPD_ENTRIES,
24666- sizeof(SK_PNMI_VPD),
24667- SK_PNMI_OFF(Vpd) + SK_PNMI_VPD_OFF(VpdKey),
24668- SK_PNMI_RO, Vpd, 0},
24669- {OID_SKGE_VPD_VALUE,
24670- SK_PNMI_VPD_ENTRIES,
24671- sizeof(SK_PNMI_VPD),
24672- SK_PNMI_OFF(Vpd) + SK_PNMI_VPD_OFF(VpdValue),
24673- SK_PNMI_RO, Vpd, 0},
24674- {OID_SKGE_VPD_ACCESS,
24675- SK_PNMI_VPD_ENTRIES,
24676- sizeof(SK_PNMI_VPD),
24677- SK_PNMI_OFF(Vpd) + SK_PNMI_VPD_OFF(VpdAccess),
24678- SK_PNMI_RO, Vpd, 0},
24679- {OID_SKGE_VPD_ACTION,
24680- SK_PNMI_VPD_ENTRIES,
24681- sizeof(SK_PNMI_VPD),
24682- SK_PNMI_OFF(Vpd) + SK_PNMI_VPD_OFF(VpdAction),
24683- SK_PNMI_RW, Vpd, 0},
24684- {OID_SKGE_PORT_NUMBER,
24685- 1,
24686- 0,
24687- SK_PNMI_MAI_OFF(PortNumber),
24688- SK_PNMI_RO, General, 0},
24689- {OID_SKGE_DEVICE_TYPE,
24690- 1,
24691- 0,
24692- SK_PNMI_MAI_OFF(DeviceType),
24693- SK_PNMI_RO, General, 0},
24694- {OID_SKGE_DRIVER_DESCR,
24695- 1,
24696- 0,
24697- SK_PNMI_MAI_OFF(DriverDescr),
24698- SK_PNMI_RO, General, 0},
24699- {OID_SKGE_DRIVER_VERSION,
24700- 1,
24701- 0,
24702- SK_PNMI_MAI_OFF(DriverVersion),
24703- SK_PNMI_RO, General, 0},
24704- {OID_SKGE_DRIVER_RELDATE,
24705- 1,
24706- 0,
24707- SK_PNMI_MAI_OFF(DriverReleaseDate),
24708- SK_PNMI_RO, General, 0},
24709- {OID_SKGE_DRIVER_FILENAME,
24710- 1,
24711- 0,
24712- SK_PNMI_MAI_OFF(DriverFileName),
24713- SK_PNMI_RO, General, 0},
24714- {OID_SKGE_HW_DESCR,
24715- 1,
24716- 0,
24717- SK_PNMI_MAI_OFF(HwDescr),
24718- SK_PNMI_RO, General, 0},
24719- {OID_SKGE_HW_VERSION,
24720- 1,
24721- 0,
24722- SK_PNMI_MAI_OFF(HwVersion),
24723- SK_PNMI_RO, General, 0},
24724- {OID_SKGE_CHIPSET,
24725- 1,
24726- 0,
24727- SK_PNMI_MAI_OFF(Chipset),
24728- SK_PNMI_RO, General, 0},
24729- {OID_SKGE_CHIPID,
24730- 1,
24731- 0,
24732- SK_PNMI_MAI_OFF(ChipId),
24733- SK_PNMI_RO, General, 0},
24734- {OID_SKGE_RAMSIZE,
24735- 1,
24736- 0,
24737- SK_PNMI_MAI_OFF(RamSize),
24738- SK_PNMI_RO, General, 0},
24739- {OID_SKGE_VAUXAVAIL,
24740- 1,
24741- 0,
24742- SK_PNMI_MAI_OFF(VauxAvail),
24743- SK_PNMI_RO, General, 0},
24744- {OID_SKGE_ACTION,
24745- 1,
24746- 0,
24747- SK_PNMI_MAI_OFF(Action),
24748- SK_PNMI_RW, Perform, 0},
24749- {OID_SKGE_RESULT,
24750- 1,
24751- 0,
24752- SK_PNMI_MAI_OFF(TestResult),
24753- SK_PNMI_RO, General, 0},
24754- {OID_SKGE_BUS_TYPE,
24755- 1,
24756- 0,
24757- SK_PNMI_MAI_OFF(BusType),
24758- SK_PNMI_RO, General, 0},
24759- {OID_SKGE_BUS_SPEED,
24760- 1,
24761- 0,
24762- SK_PNMI_MAI_OFF(BusSpeed),
24763- SK_PNMI_RO, General, 0},
24764- {OID_SKGE_BUS_WIDTH,
24765- 1,
24766- 0,
24767- SK_PNMI_MAI_OFF(BusWidth),
24768- SK_PNMI_RO, General, 0},
24769- {OID_SKGE_TX_SW_QUEUE_LEN,
24770- 1,
24771- 0,
24772- SK_PNMI_MAI_OFF(TxSwQueueLen),
24773- SK_PNMI_RO, General, 0},
24774- {OID_SKGE_TX_SW_QUEUE_MAX,
24775- 1,
24776- 0,
24777- SK_PNMI_MAI_OFF(TxSwQueueMax),
24778- SK_PNMI_RO, General, 0},
24779- {OID_SKGE_TX_RETRY,
24780- 1,
24781- 0,
24782- SK_PNMI_MAI_OFF(TxRetryCts),
24783- SK_PNMI_RO, General, 0},
24784- {OID_SKGE_RX_INTR_CTS,
24785- 1,
24786- 0,
24787- SK_PNMI_MAI_OFF(RxIntrCts),
24788- SK_PNMI_RO, General, 0},
24789- {OID_SKGE_TX_INTR_CTS,
24790- 1,
24791- 0,
24792- SK_PNMI_MAI_OFF(TxIntrCts),
24793- SK_PNMI_RO, General, 0},
24794- {OID_SKGE_RX_NO_BUF_CTS,
24795- 1,
24796- 0,
24797- SK_PNMI_MAI_OFF(RxNoBufCts),
24798- SK_PNMI_RO, General, 0},
24799- {OID_SKGE_TX_NO_BUF_CTS,
24800- 1,
24801- 0,
24802- SK_PNMI_MAI_OFF(TxNoBufCts),
24803- SK_PNMI_RO, General, 0},
24804- {OID_SKGE_TX_USED_DESCR_NO,
24805- 1,
24806- 0,
24807- SK_PNMI_MAI_OFF(TxUsedDescrNo),
24808- SK_PNMI_RO, General, 0},
24809- {OID_SKGE_RX_DELIVERED_CTS,
24810- 1,
24811- 0,
24812- SK_PNMI_MAI_OFF(RxDeliveredCts),
24813- SK_PNMI_RO, General, 0},
24814- {OID_SKGE_RX_OCTETS_DELIV_CTS,
24815- 1,
24816- 0,
24817- SK_PNMI_MAI_OFF(RxOctetsDeliveredCts),
24818- SK_PNMI_RO, General, 0},
24819- {OID_SKGE_RX_HW_ERROR_CTS,
24820- 1,
24821- 0,
24822- SK_PNMI_MAI_OFF(RxHwErrorsCts),
24823- SK_PNMI_RO, General, 0},
24824- {OID_SKGE_TX_HW_ERROR_CTS,
24825- 1,
24826- 0,
24827- SK_PNMI_MAI_OFF(TxHwErrorsCts),
24828- SK_PNMI_RO, General, 0},
24829- {OID_SKGE_IN_ERRORS_CTS,
24830- 1,
24831- 0,
24832- SK_PNMI_MAI_OFF(InErrorsCts),
24833- SK_PNMI_RO, General, 0},
24834- {OID_SKGE_OUT_ERROR_CTS,
24835- 1,
24836- 0,
24837- SK_PNMI_MAI_OFF(OutErrorsCts),
24838- SK_PNMI_RO, General, 0},
24839- {OID_SKGE_ERR_RECOVERY_CTS,
24840- 1,
24841- 0,
24842- SK_PNMI_MAI_OFF(ErrRecoveryCts),
24843- SK_PNMI_RO, General, 0},
24844- {OID_SKGE_SYSUPTIME,
24845- 1,
24846- 0,
24847- SK_PNMI_MAI_OFF(SysUpTime),
24848- SK_PNMI_RO, General, 0},
24849- {OID_SKGE_SENSOR_NUMBER,
24850- 1,
24851- 0,
24852- SK_PNMI_MAI_OFF(SensorNumber),
24853- SK_PNMI_RO, General, 0},
24854- {OID_SKGE_SENSOR_INDEX,
24855- SK_PNMI_SENSOR_ENTRIES,
24856- sizeof(SK_PNMI_SENSOR),
24857- SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorIndex),
24858- SK_PNMI_RO, SensorStat, 0},
24859- {OID_SKGE_SENSOR_DESCR,
24860- SK_PNMI_SENSOR_ENTRIES,
24861- sizeof(SK_PNMI_SENSOR),
24862- SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorDescr),
24863- SK_PNMI_RO, SensorStat, 0},
24864- {OID_SKGE_SENSOR_TYPE,
24865- SK_PNMI_SENSOR_ENTRIES,
24866- sizeof(SK_PNMI_SENSOR),
24867- SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorType),
24868- SK_PNMI_RO, SensorStat, 0},
24869- {OID_SKGE_SENSOR_VALUE,
24870- SK_PNMI_SENSOR_ENTRIES,
24871- sizeof(SK_PNMI_SENSOR),
24872- SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorValue),
24873- SK_PNMI_RO, SensorStat, 0},
24874- {OID_SKGE_SENSOR_WAR_THRES_LOW,
24875- SK_PNMI_SENSOR_ENTRIES,
24876- sizeof(SK_PNMI_SENSOR),
24877- SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorWarningThresholdLow),
24878- SK_PNMI_RO, SensorStat, 0},
24879- {OID_SKGE_SENSOR_WAR_THRES_UPP,
24880- SK_PNMI_SENSOR_ENTRIES,
24881- sizeof(SK_PNMI_SENSOR),
24882- SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorWarningThresholdHigh),
24883- SK_PNMI_RO, SensorStat, 0},
24884- {OID_SKGE_SENSOR_ERR_THRES_LOW,
24885- SK_PNMI_SENSOR_ENTRIES,
24886- sizeof(SK_PNMI_SENSOR),
24887- SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorErrorThresholdLow),
24888- SK_PNMI_RO, SensorStat, 0},
24889- {OID_SKGE_SENSOR_ERR_THRES_UPP,
24890- SK_PNMI_SENSOR_ENTRIES,
24891- sizeof(SK_PNMI_SENSOR),
24892- SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorErrorThresholdHigh),
24893- SK_PNMI_RO, SensorStat, 0},
24894- {OID_SKGE_SENSOR_STATUS,
24895- SK_PNMI_SENSOR_ENTRIES,
24896- sizeof(SK_PNMI_SENSOR),
24897- SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorStatus),
24898- SK_PNMI_RO, SensorStat, 0},
24899- {OID_SKGE_SENSOR_WAR_CTS,
24900- SK_PNMI_SENSOR_ENTRIES,
24901- sizeof(SK_PNMI_SENSOR),
24902- SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorWarningCts),
24903- SK_PNMI_RO, SensorStat, 0},
24904- {OID_SKGE_SENSOR_ERR_CTS,
24905- SK_PNMI_SENSOR_ENTRIES,
24906- sizeof(SK_PNMI_SENSOR),
24907- SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorErrorCts),
24908- SK_PNMI_RO, SensorStat, 0},
24909- {OID_SKGE_SENSOR_WAR_TIME,
24910- SK_PNMI_SENSOR_ENTRIES,
24911- sizeof(SK_PNMI_SENSOR),
24912- SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorWarningTimestamp),
24913- SK_PNMI_RO, SensorStat, 0},
24914- {OID_SKGE_SENSOR_ERR_TIME,
24915- SK_PNMI_SENSOR_ENTRIES,
24916- sizeof(SK_PNMI_SENSOR),
24917- SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorErrorTimestamp),
24918- SK_PNMI_RO, SensorStat, 0},
24919- {OID_SKGE_CHKSM_NUMBER,
24920- 1,
24921- 0,
24922- SK_PNMI_MAI_OFF(ChecksumNumber),
24923- SK_PNMI_RO, General, 0},
24924- {OID_SKGE_CHKSM_RX_OK_CTS,
24925- SKCS_NUM_PROTOCOLS,
24926- sizeof(SK_PNMI_CHECKSUM),
24927- SK_PNMI_OFF(Checksum) + SK_PNMI_CHK_OFF(ChecksumRxOkCts),
24928- SK_PNMI_RO, CsumStat, 0},
24929- {OID_SKGE_CHKSM_RX_UNABLE_CTS,
24930- SKCS_NUM_PROTOCOLS,
24931- sizeof(SK_PNMI_CHECKSUM),
24932- SK_PNMI_OFF(Checksum) + SK_PNMI_CHK_OFF(ChecksumRxUnableCts),
24933- SK_PNMI_RO, CsumStat, 0},
24934- {OID_SKGE_CHKSM_RX_ERR_CTS,
24935- SKCS_NUM_PROTOCOLS,
24936- sizeof(SK_PNMI_CHECKSUM),
24937- SK_PNMI_OFF(Checksum) + SK_PNMI_CHK_OFF(ChecksumRxErrCts),
24938- SK_PNMI_RO, CsumStat, 0},
24939- {OID_SKGE_CHKSM_TX_OK_CTS,
24940- SKCS_NUM_PROTOCOLS,
24941- sizeof(SK_PNMI_CHECKSUM),
24942- SK_PNMI_OFF(Checksum) + SK_PNMI_CHK_OFF(ChecksumTxOkCts),
24943- SK_PNMI_RO, CsumStat, 0},
24944- {OID_SKGE_CHKSM_TX_UNABLE_CTS,
24945- SKCS_NUM_PROTOCOLS,
24946- sizeof(SK_PNMI_CHECKSUM),
24947- SK_PNMI_OFF(Checksum) + SK_PNMI_CHK_OFF(ChecksumTxUnableCts),
24948- SK_PNMI_RO, CsumStat, 0},
24949- {OID_SKGE_STAT_TX,
24950- SK_PNMI_MAC_ENTRIES,
24951- sizeof(SK_PNMI_STAT),
24952- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxOkCts),
24953- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX},
24954- {OID_SKGE_STAT_TX_OCTETS,
24955- SK_PNMI_MAC_ENTRIES,
24956- sizeof(SK_PNMI_STAT),
24957- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxOctetsOkCts),
24958- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_OCTET},
24959- {OID_SKGE_STAT_TX_BROADCAST,
24960- SK_PNMI_MAC_ENTRIES,
24961- sizeof(SK_PNMI_STAT),
24962- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxBroadcastOkCts),
24963- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_BROADCAST},
24964- {OID_SKGE_STAT_TX_MULTICAST,
24965- SK_PNMI_MAC_ENTRIES,
24966- sizeof(SK_PNMI_STAT),
24967- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxMulticastOkCts),
24968- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_MULTICAST},
24969- {OID_SKGE_STAT_TX_UNICAST,
24970- SK_PNMI_MAC_ENTRIES,
24971- sizeof(SK_PNMI_STAT),
24972- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxUnicastOkCts),
24973- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_UNICAST},
24974- {OID_SKGE_STAT_TX_LONGFRAMES,
24975- SK_PNMI_MAC_ENTRIES,
24976- sizeof(SK_PNMI_STAT),
24977- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxLongFramesCts),
24978- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_LONGFRAMES},
24979- {OID_SKGE_STAT_TX_BURST,
24980- SK_PNMI_MAC_ENTRIES,
24981- sizeof(SK_PNMI_STAT),
24982- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxBurstCts),
24983- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_BURST},
24984- {OID_SKGE_STAT_TX_PFLOWC,
24985- SK_PNMI_MAC_ENTRIES,
24986- sizeof(SK_PNMI_STAT),
24987- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxPauseMacCtrlCts),
24988- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_PMACC},
24989- {OID_SKGE_STAT_TX_FLOWC,
24990- SK_PNMI_MAC_ENTRIES,
24991- sizeof(SK_PNMI_STAT),
24992- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxMacCtrlCts),
24993- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_MACC},
24994- {OID_SKGE_STAT_TX_SINGLE_COL,
24995- SK_PNMI_MAC_ENTRIES,
24996- sizeof(SK_PNMI_STAT),
24997- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxSingleCollisionCts),
24998- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_SINGLE_COL},
24999- {OID_SKGE_STAT_TX_MULTI_COL,
25000- SK_PNMI_MAC_ENTRIES,
25001- sizeof(SK_PNMI_STAT),
25002- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxMultipleCollisionCts),
25003- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_MULTI_COL},
25004- {OID_SKGE_STAT_TX_EXCESS_COL,
25005- SK_PNMI_MAC_ENTRIES,
25006- sizeof(SK_PNMI_STAT),
25007- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxExcessiveCollisionCts),
25008- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_EXCESS_COL},
25009- {OID_SKGE_STAT_TX_LATE_COL,
25010- SK_PNMI_MAC_ENTRIES,
25011- sizeof(SK_PNMI_STAT),
25012- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxLateCollisionCts),
25013- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_LATE_COL},
25014- {OID_SKGE_STAT_TX_DEFFERAL,
25015- SK_PNMI_MAC_ENTRIES,
25016- sizeof(SK_PNMI_STAT),
25017- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxDeferralCts),
25018- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_DEFFERAL},
25019- {OID_SKGE_STAT_TX_EXCESS_DEF,
25020- SK_PNMI_MAC_ENTRIES,
25021- sizeof(SK_PNMI_STAT),
25022- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxExcessiveDeferralCts),
25023- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_EXCESS_DEF},
25024- {OID_SKGE_STAT_TX_UNDERRUN,
25025- SK_PNMI_MAC_ENTRIES,
25026- sizeof(SK_PNMI_STAT),
25027- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxFifoUnderrunCts),
25028- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_UNDERRUN},
25029- {OID_SKGE_STAT_TX_CARRIER,
25030- SK_PNMI_MAC_ENTRIES,
25031- sizeof(SK_PNMI_STAT),
25032- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxCarrierCts),
25033- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_CARRIER},
25034-/* {OID_SKGE_STAT_TX_UTIL,
25035- SK_PNMI_MAC_ENTRIES,
25036- sizeof(SK_PNMI_STAT),
25037- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxUtilization),
25038- SK_PNMI_RO, MacPrivateStat, (SK_U16)(-1)}, */
25039- {OID_SKGE_STAT_TX_64,
25040- SK_PNMI_MAC_ENTRIES,
25041- sizeof(SK_PNMI_STAT),
25042- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTx64Cts),
25043- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_64},
25044- {OID_SKGE_STAT_TX_127,
25045- SK_PNMI_MAC_ENTRIES,
25046- sizeof(SK_PNMI_STAT),
25047- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTx127Cts),
25048- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_127},
25049- {OID_SKGE_STAT_TX_255,
25050- SK_PNMI_MAC_ENTRIES,
25051- sizeof(SK_PNMI_STAT),
25052- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTx255Cts),
25053- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_255},
25054- {OID_SKGE_STAT_TX_511,
25055- SK_PNMI_MAC_ENTRIES,
25056- sizeof(SK_PNMI_STAT),
25057- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTx511Cts),
25058- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_511},
25059- {OID_SKGE_STAT_TX_1023,
25060- SK_PNMI_MAC_ENTRIES,
25061- sizeof(SK_PNMI_STAT),
25062- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTx1023Cts),
25063- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_1023},
25064- {OID_SKGE_STAT_TX_MAX,
25065- SK_PNMI_MAC_ENTRIES,
25066- sizeof(SK_PNMI_STAT),
25067- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxMaxCts),
25068- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_MAX},
25069- {OID_SKGE_STAT_TX_SYNC,
25070- SK_PNMI_MAC_ENTRIES,
25071- sizeof(SK_PNMI_STAT),
25072- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxSyncCts),
25073- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_SYNC},
25074- {OID_SKGE_STAT_TX_SYNC_OCTETS,
25075- SK_PNMI_MAC_ENTRIES,
25076- sizeof(SK_PNMI_STAT),
25077- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxSyncOctetsCts),
25078- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_SYNC_OCTET},
25079- {OID_SKGE_STAT_RX,
25080- SK_PNMI_MAC_ENTRIES,
25081- sizeof(SK_PNMI_STAT),
25082- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxOkCts),
25083- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX},
25084- {OID_SKGE_STAT_RX_OCTETS,
25085- SK_PNMI_MAC_ENTRIES,
25086- sizeof(SK_PNMI_STAT),
25087- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxOctetsOkCts),
25088- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_OCTET},
25089- {OID_SKGE_STAT_RX_BROADCAST,
25090- SK_PNMI_MAC_ENTRIES,
25091- sizeof(SK_PNMI_STAT),
25092- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxBroadcastOkCts),
25093- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_BROADCAST},
25094- {OID_SKGE_STAT_RX_MULTICAST,
25095- SK_PNMI_MAC_ENTRIES,
25096- sizeof(SK_PNMI_STAT),
25097- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxMulticastOkCts),
25098- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_MULTICAST},
25099- {OID_SKGE_STAT_RX_UNICAST,
25100- SK_PNMI_MAC_ENTRIES,
25101- sizeof(SK_PNMI_STAT),
25102- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxUnicastOkCts),
25103- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_UNICAST},
25104- {OID_SKGE_STAT_RX_LONGFRAMES,
25105- SK_PNMI_MAC_ENTRIES,
25106- sizeof(SK_PNMI_STAT),
25107- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxLongFramesCts),
25108- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_LONGFRAMES},
25109- {OID_SKGE_STAT_RX_PFLOWC,
25110- SK_PNMI_MAC_ENTRIES,
25111- sizeof(SK_PNMI_STAT),
25112- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxPauseMacCtrlCts),
25113- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_PMACC},
25114- {OID_SKGE_STAT_RX_FLOWC,
25115- SK_PNMI_MAC_ENTRIES,
25116- sizeof(SK_PNMI_STAT),
25117- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxMacCtrlCts),
25118- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_MACC},
25119- {OID_SKGE_STAT_RX_PFLOWC_ERR,
25120- SK_PNMI_MAC_ENTRIES,
25121- sizeof(SK_PNMI_STAT),
25122- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxPauseMacCtrlErrorCts),
25123- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_PMACC_ERR},
25124- {OID_SKGE_STAT_RX_FLOWC_UNKWN,
25125- SK_PNMI_MAC_ENTRIES,
25126- sizeof(SK_PNMI_STAT),
25127- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxMacCtrlUnknownCts),
25128- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_MACC_UNKWN},
25129- {OID_SKGE_STAT_RX_BURST,
25130- SK_PNMI_MAC_ENTRIES,
25131- sizeof(SK_PNMI_STAT),
25132- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxBurstCts),
25133- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_BURST},
25134- {OID_SKGE_STAT_RX_MISSED,
25135- SK_PNMI_MAC_ENTRIES,
25136- sizeof(SK_PNMI_STAT),
25137- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxMissedCts),
25138- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_MISSED},
25139- {OID_SKGE_STAT_RX_FRAMING,
25140- SK_PNMI_MAC_ENTRIES,
25141- sizeof(SK_PNMI_STAT),
25142- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxFramingCts),
25143- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_FRAMING},
25144- {OID_SKGE_STAT_RX_OVERFLOW,
25145- SK_PNMI_MAC_ENTRIES,
25146- sizeof(SK_PNMI_STAT),
25147- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxFifoOverflowCts),
25148- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_OVERFLOW},
25149- {OID_SKGE_STAT_RX_JABBER,
25150- SK_PNMI_MAC_ENTRIES,
25151- sizeof(SK_PNMI_STAT),
25152- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxJabberCts),
25153- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_JABBER},
25154- {OID_SKGE_STAT_RX_CARRIER,
25155- SK_PNMI_MAC_ENTRIES,
25156- sizeof(SK_PNMI_STAT),
25157- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxCarrierCts),
25158- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_CARRIER},
25159- {OID_SKGE_STAT_RX_IR_LENGTH,
25160- SK_PNMI_MAC_ENTRIES,
25161- sizeof(SK_PNMI_STAT),
25162- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxIRLengthCts),
25163- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_IRLENGTH},
25164- {OID_SKGE_STAT_RX_SYMBOL,
25165- SK_PNMI_MAC_ENTRIES,
25166- sizeof(SK_PNMI_STAT),
25167- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxSymbolCts),
25168- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_SYMBOL},
25169- {OID_SKGE_STAT_RX_SHORTS,
25170- SK_PNMI_MAC_ENTRIES,
25171- sizeof(SK_PNMI_STAT),
25172- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxShortsCts),
25173- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_SHORTS},
25174- {OID_SKGE_STAT_RX_RUNT,
25175- SK_PNMI_MAC_ENTRIES,
25176- sizeof(SK_PNMI_STAT),
25177- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxRuntCts),
25178- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_RUNT},
25179- {OID_SKGE_STAT_RX_CEXT,
25180- SK_PNMI_MAC_ENTRIES,
25181- sizeof(SK_PNMI_STAT),
25182- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxCextCts),
25183- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_CEXT},
25184- {OID_SKGE_STAT_RX_TOO_LONG,
25185- SK_PNMI_MAC_ENTRIES,
25186- sizeof(SK_PNMI_STAT),
25187- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxTooLongCts),
25188- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_TOO_LONG},
25189- {OID_SKGE_STAT_RX_FCS,
25190- SK_PNMI_MAC_ENTRIES,
25191- sizeof(SK_PNMI_STAT),
25192- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxFcsCts),
25193- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_FCS},
25194-/* {OID_SKGE_STAT_RX_UTIL,
25195- SK_PNMI_MAC_ENTRIES,
25196- sizeof(SK_PNMI_STAT),
25197- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxUtilization),
25198- SK_PNMI_RO, MacPrivateStat, (SK_U16)(-1)}, */
25199- {OID_SKGE_STAT_RX_64,
25200- SK_PNMI_MAC_ENTRIES,
25201- sizeof(SK_PNMI_STAT),
25202- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRx64Cts),
25203- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_64},
25204- {OID_SKGE_STAT_RX_127,
25205- SK_PNMI_MAC_ENTRIES,
25206- sizeof(SK_PNMI_STAT),
25207- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRx127Cts),
25208- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_127},
25209- {OID_SKGE_STAT_RX_255,
25210- SK_PNMI_MAC_ENTRIES,
25211- sizeof(SK_PNMI_STAT),
25212- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRx255Cts),
25213- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_255},
25214- {OID_SKGE_STAT_RX_511,
25215- SK_PNMI_MAC_ENTRIES,
25216- sizeof(SK_PNMI_STAT),
25217- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRx511Cts),
25218- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_511},
25219- {OID_SKGE_STAT_RX_1023,
25220- SK_PNMI_MAC_ENTRIES,
25221- sizeof(SK_PNMI_STAT),
25222- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRx1023Cts),
25223- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_1023},
25224- {OID_SKGE_STAT_RX_MAX,
25225- SK_PNMI_MAC_ENTRIES,
25226- sizeof(SK_PNMI_STAT),
25227- SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxMaxCts),
25228- SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_MAX},
25229- {OID_SKGE_PHYS_CUR_ADDR,
25230- SK_PNMI_MAC_ENTRIES,
25231- sizeof(SK_PNMI_CONF),
25232- SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfMacCurrentAddr),
25233- SK_PNMI_RW, Addr, 0},
25234- {OID_SKGE_PHYS_FAC_ADDR,
25235- SK_PNMI_MAC_ENTRIES,
25236- sizeof(SK_PNMI_CONF),
25237- SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfMacFactoryAddr),
25238- SK_PNMI_RO, Addr, 0},
25239- {OID_SKGE_PMD,
25240- SK_PNMI_MAC_ENTRIES,
25241- sizeof(SK_PNMI_CONF),
25242- SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPMD),
25243- SK_PNMI_RO, MacPrivateConf, 0},
25244- {OID_SKGE_CONNECTOR,
25245- SK_PNMI_MAC_ENTRIES,
25246- sizeof(SK_PNMI_CONF),
25247- SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfConnector),
25248- SK_PNMI_RO, MacPrivateConf, 0},
25249- {OID_SKGE_PHY_TYPE,
25250- SK_PNMI_MAC_ENTRIES,
25251- sizeof(SK_PNMI_CONF),
25252- SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyType),
25253- SK_PNMI_RO, MacPrivateConf, 0},
25254-#ifdef SK_PHY_LP_MODE
25255- {OID_SKGE_PHY_LP_MODE,
25256- SK_PNMI_MAC_ENTRIES,
25257- sizeof(SK_PNMI_CONF),
25258- SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyMode),
25259- SK_PNMI_RW, MacPrivateConf, 0},
25260-#endif
25261- {OID_SKGE_LINK_CAP,
25262- SK_PNMI_MAC_ENTRIES,
25263- sizeof(SK_PNMI_CONF),
25264- SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfLinkCapability),
25265- SK_PNMI_RO, MacPrivateConf, 0},
25266- {OID_SKGE_LINK_MODE,
25267- SK_PNMI_MAC_ENTRIES,
25268- sizeof(SK_PNMI_CONF),
25269- SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfLinkMode),
25270- SK_PNMI_RW, MacPrivateConf, 0},
25271- {OID_SKGE_LINK_MODE_STATUS,
25272- SK_PNMI_MAC_ENTRIES,
25273- sizeof(SK_PNMI_CONF),
25274- SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfLinkModeStatus),
25275- SK_PNMI_RO, MacPrivateConf, 0},
25276- {OID_SKGE_LINK_STATUS,
25277- SK_PNMI_MAC_ENTRIES,
25278- sizeof(SK_PNMI_CONF),
25279- SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfLinkStatus),
25280- SK_PNMI_RO, MacPrivateConf, 0},
25281- {OID_SKGE_FLOWCTRL_CAP,
25282- SK_PNMI_MAC_ENTRIES,
25283- sizeof(SK_PNMI_CONF),
25284- SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfFlowCtrlCapability),
25285- SK_PNMI_RO, MacPrivateConf, 0},
25286- {OID_SKGE_FLOWCTRL_MODE,
25287- SK_PNMI_MAC_ENTRIES,
25288- sizeof(SK_PNMI_CONF),
25289- SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfFlowCtrlMode),
25290- SK_PNMI_RW, MacPrivateConf, 0},
25291- {OID_SKGE_FLOWCTRL_STATUS,
25292- SK_PNMI_MAC_ENTRIES,
25293- sizeof(SK_PNMI_CONF),
25294- SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfFlowCtrlStatus),
25295- SK_PNMI_RO, MacPrivateConf, 0},
25296- {OID_SKGE_PHY_OPERATION_CAP,
25297- SK_PNMI_MAC_ENTRIES,
25298- sizeof(SK_PNMI_CONF),
25299- SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyOperationCapability),
25300- SK_PNMI_RO, MacPrivateConf, 0},
25301- {OID_SKGE_PHY_OPERATION_MODE,
25302- SK_PNMI_MAC_ENTRIES,
25303- sizeof(SK_PNMI_CONF),
25304- SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyOperationMode),
25305- SK_PNMI_RW, MacPrivateConf, 0},
25306- {OID_SKGE_PHY_OPERATION_STATUS,
25307- SK_PNMI_MAC_ENTRIES,
25308- sizeof(SK_PNMI_CONF),
25309- SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyOperationStatus),
25310- SK_PNMI_RO, MacPrivateConf, 0},
25311- {OID_SKGE_SPEED_CAP,
25312- SK_PNMI_MAC_ENTRIES,
25313- sizeof(SK_PNMI_CONF),
25314- SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfSpeedCapability),
25315- SK_PNMI_RO, MacPrivateConf, 0},
25316- {OID_SKGE_SPEED_MODE,
25317- SK_PNMI_MAC_ENTRIES,
25318- sizeof(SK_PNMI_CONF),
25319- SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfSpeedMode),
25320- SK_PNMI_RW, MacPrivateConf, 0},
25321- {OID_SKGE_SPEED_STATUS,
25322- SK_PNMI_MAC_ENTRIES,
25323- sizeof(SK_PNMI_CONF),
25324- SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfSpeedStatus),
25325- SK_PNMI_RO, MacPrivateConf, 0},
25326- {OID_SKGE_TRAP,
25327- 1,
25328- 0,
25329- SK_PNMI_MAI_OFF(Trap),
25330- SK_PNMI_RO, General, 0},
25331- {OID_SKGE_TRAP_NUMBER,
25332- 1,
25333- 0,
25334- SK_PNMI_MAI_OFF(TrapNumber),
25335- SK_PNMI_RO, General, 0},
25336- {OID_SKGE_RLMT_MODE,
25337- 1,
25338- 0,
25339- SK_PNMI_MAI_OFF(RlmtMode),
25340- SK_PNMI_RW, Rlmt, 0},
25341- {OID_SKGE_RLMT_PORT_NUMBER,
25342- 1,
25343- 0,
25344- SK_PNMI_MAI_OFF(RlmtPortNumber),
25345- SK_PNMI_RO, Rlmt, 0},
25346- {OID_SKGE_RLMT_PORT_ACTIVE,
25347- 1,
25348- 0,
25349- SK_PNMI_MAI_OFF(RlmtPortActive),
25350- SK_PNMI_RO, Rlmt, 0},
25351- {OID_SKGE_RLMT_PORT_PREFERRED,
25352- 1,
25353- 0,
25354- SK_PNMI_MAI_OFF(RlmtPortPreferred),
25355- SK_PNMI_RW, Rlmt, 0},
25356- {OID_SKGE_RLMT_CHANGE_CTS,
25357- 1,
25358- 0,
25359- SK_PNMI_MAI_OFF(RlmtChangeCts),
25360- SK_PNMI_RO, Rlmt, 0},
25361- {OID_SKGE_RLMT_CHANGE_TIME,
25362- 1,
25363- 0,
25364- SK_PNMI_MAI_OFF(RlmtChangeTime),
25365- SK_PNMI_RO, Rlmt, 0},
25366- {OID_SKGE_RLMT_CHANGE_ESTIM,
25367- 1,
25368- 0,
25369- SK_PNMI_MAI_OFF(RlmtChangeEstimate),
25370- SK_PNMI_RO, Rlmt, 0},
25371- {OID_SKGE_RLMT_CHANGE_THRES,
25372- 1,
25373- 0,
25374- SK_PNMI_MAI_OFF(RlmtChangeThreshold),
25375- SK_PNMI_RW, Rlmt, 0},
25376- {OID_SKGE_RLMT_PORT_INDEX,
25377- SK_PNMI_MAC_ENTRIES,
25378- sizeof(SK_PNMI_RLMT),
25379- SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtIndex),
25380- SK_PNMI_RO, RlmtStat, 0},
25381- {OID_SKGE_RLMT_STATUS,
25382- SK_PNMI_MAC_ENTRIES,
25383- sizeof(SK_PNMI_RLMT),
25384- SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtStatus),
25385- SK_PNMI_RO, RlmtStat, 0},
25386- {OID_SKGE_RLMT_TX_HELLO_CTS,
25387- SK_PNMI_MAC_ENTRIES,
25388- sizeof(SK_PNMI_RLMT),
25389- SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtTxHelloCts),
25390- SK_PNMI_RO, RlmtStat, 0},
25391- {OID_SKGE_RLMT_RX_HELLO_CTS,
25392- SK_PNMI_MAC_ENTRIES,
25393- sizeof(SK_PNMI_RLMT),
25394- SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtRxHelloCts),
25395- SK_PNMI_RO, RlmtStat, 0},
25396- {OID_SKGE_RLMT_TX_SP_REQ_CTS,
25397- SK_PNMI_MAC_ENTRIES,
25398- sizeof(SK_PNMI_RLMT),
25399- SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtTxSpHelloReqCts),
25400- SK_PNMI_RO, RlmtStat, 0},
25401- {OID_SKGE_RLMT_RX_SP_CTS,
25402- SK_PNMI_MAC_ENTRIES,
25403- sizeof(SK_PNMI_RLMT),
25404- SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtRxSpHelloCts),
25405- SK_PNMI_RO, RlmtStat, 0},
25406- {OID_SKGE_RLMT_MONITOR_NUMBER,
25407- 1,
25408- 0,
25409- SK_PNMI_MAI_OFF(RlmtMonitorNumber),
25410- SK_PNMI_RO, General, 0},
25411- {OID_SKGE_RLMT_MONITOR_INDEX,
25412- SK_PNMI_MONITOR_ENTRIES,
25413- sizeof(SK_PNMI_RLMT_MONITOR),
25414- SK_PNMI_OFF(RlmtMonitor) + SK_PNMI_MON_OFF(RlmtMonitorIndex),
25415- SK_PNMI_RO, Monitor, 0},
25416- {OID_SKGE_RLMT_MONITOR_ADDR,
25417- SK_PNMI_MONITOR_ENTRIES,
25418- sizeof(SK_PNMI_RLMT_MONITOR),
25419- SK_PNMI_OFF(RlmtMonitor) + SK_PNMI_MON_OFF(RlmtMonitorAddr),
25420- SK_PNMI_RO, Monitor, 0},
25421- {OID_SKGE_RLMT_MONITOR_ERRS,
25422- SK_PNMI_MONITOR_ENTRIES,
25423- sizeof(SK_PNMI_RLMT_MONITOR),
25424- SK_PNMI_OFF(RlmtMonitor) + SK_PNMI_MON_OFF(RlmtMonitorErrorCts),
25425- SK_PNMI_RO, Monitor, 0},
25426- {OID_SKGE_RLMT_MONITOR_TIMESTAMP,
25427- SK_PNMI_MONITOR_ENTRIES,
25428- sizeof(SK_PNMI_RLMT_MONITOR),
25429- SK_PNMI_OFF(RlmtMonitor) + SK_PNMI_MON_OFF(RlmtMonitorTimestamp),
25430- SK_PNMI_RO, Monitor, 0},
25431- {OID_SKGE_RLMT_MONITOR_ADMIN,
25432- SK_PNMI_MONITOR_ENTRIES,
25433- sizeof(SK_PNMI_RLMT_MONITOR),
25434- SK_PNMI_OFF(RlmtMonitor) + SK_PNMI_MON_OFF(RlmtMonitorAdmin),
25435- SK_PNMI_RW, Monitor, 0},
25436- {OID_SKGE_MTU,
25437- 1,
25438- 0,
25439- SK_PNMI_MAI_OFF(MtuSize),
25440- SK_PNMI_RW, MacPrivateConf, 0},
25441- {OID_SKGE_VCT_GET,
25442- 0,
25443- 0,
25444- 0,
25445- SK_PNMI_RO, Vct, 0},
25446- {OID_SKGE_VCT_SET,
25447- 0,
25448- 0,
25449- 0,
25450- SK_PNMI_WO, Vct, 0},
25451- {OID_SKGE_VCT_STATUS,
25452- 0,
25453- 0,
25454- 0,
25455- SK_PNMI_RO, Vct, 0},
25456- {OID_SKGE_BOARDLEVEL,
25457- 0,
25458- 0,
25459- 0,
25460- SK_PNMI_RO, General, 0},
25461-};
25462-
25463+/*****************************************************************************\r
25464+ *\r
25465+ * Name: skgemib.c\r
25466+ * Project: GEnesis, PCI Gigabit Ethernet Adapter\r
25467+ * Version: $Revision$\r
25468+ * Date: $Date$\r
25469+ * Purpose: Private Network Management Interface Management Database\r
25470+ *\r
25471+ ****************************************************************************/\r
25472+\r
25473+/******************************************************************************\r
25474+ *\r
25475+ * (C)Copyright 1998-2002 SysKonnect GmbH.\r
25476+ * (C)Copyright 2002-2003 Marvell.\r
25477+ *\r
25478+ * This program is free software; you can redistribute it and/or modify\r
25479+ * it under the terms of the GNU General Public License as published by\r
25480+ * the Free Software Foundation; either version 2 of the License, or\r
25481+ * (at your option) any later version.\r
25482+ *\r
25483+ * The information in this file is provided "AS IS" without warranty.\r
25484+ *\r
25485+ ******************************************************************************/\r
25486+\r
25487+/*\r
25488+ * PRIVATE OID handler function prototypes\r
25489+ */\r
25490+PNMI_STATIC int Addr(SK_AC *pAC, SK_IOC IoC, int action,\r
25491+ SK_U32 Id, char *pBuf, unsigned int *pLen, SK_U32 Instance,\r
25492+ unsigned int TableIndex, SK_U32 NetIndex);\r
25493+PNMI_STATIC int CsumStat(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,\r
25494+ char *pBuf, unsigned int *pLen, SK_U32 Instance,\r
25495+ unsigned int TableIndex, SK_U32 NetIndex);\r
25496+PNMI_STATIC int General(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,\r
25497+ char *pBuf, unsigned int *pLen, SK_U32 Instance,\r
25498+ unsigned int TableIndex, SK_U32 NetIndex);\r
25499+PNMI_STATIC int Mac8023Stat(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,\r
25500+ char *pBuf, unsigned int *pLen, SK_U32 Instance,\r
25501+ unsigned int TableIndex, SK_U32 NetIndex);\r
25502+PNMI_STATIC int MacPrivateConf(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,\r
25503+ char *pBuf, unsigned int *pLen, SK_U32 Instance,\r
25504+ unsigned int TableIndex, SK_U32 NetIndex);\r
25505+PNMI_STATIC int MacPrivateStat(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,\r
25506+ char *pBuf, unsigned int *pLen, SK_U32 Instance,\r
25507+ unsigned int TableIndex, SK_U32 NetIndex);\r
25508+PNMI_STATIC int Monitor(SK_AC *pAC, SK_IOC IoC, int action,\r
25509+ SK_U32 Id, char *pBuf, unsigned int *pLen, SK_U32 Instance,\r
25510+ unsigned int TableIndex, SK_U32 NetIndex);\r
25511+PNMI_STATIC int OidStruct(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,\r
25512+ char *pBuf, unsigned int *pLen, SK_U32 Instance,\r
25513+ unsigned int TableIndex, SK_U32 NetIndex);\r
25514+PNMI_STATIC int Perform(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,\r
25515+ char *pBuf, unsigned int* pLen, SK_U32 Instance,\r
25516+ unsigned int TableIndex, SK_U32 NetIndex);\r
25517+PNMI_STATIC int Rlmt(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,\r
25518+ char *pBuf, unsigned int *pLen, SK_U32 Instance,\r
25519+ unsigned int TableIndex, SK_U32 NetIndex);\r
25520+PNMI_STATIC int RlmtStat(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,\r
25521+ char *pBuf, unsigned int *pLen, SK_U32 Instance,\r
25522+ unsigned int TableIndex, SK_U32 NetIndex);\r
25523+PNMI_STATIC int SensorStat(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,\r
25524+ char *pBuf, unsigned int *pLen, SK_U32 Instance,\r
25525+ unsigned int TableIndex, SK_U32 NetIndex);\r
25526+PNMI_STATIC int Vpd(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,\r
25527+ char *pBuf, unsigned int *pLen, SK_U32 Instance,\r
25528+ unsigned int TableIndex, SK_U32 NetIndex);\r
25529+PNMI_STATIC int Vct(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,\r
25530+ char *pBuf, unsigned int *pLen, SK_U32 Instance,\r
25531+ unsigned int TableIndex, SK_U32 NetIndex);\r
25532+\r
25533+#ifdef SK_POWER_MGMT\r
25534+PNMI_STATIC int PowerManagement(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,\r
25535+ char *pBuf, unsigned int *pLen, SK_U32 Instance,\r
25536+ unsigned int TableIndex, SK_U32 NetIndex);\r
25537+#endif /* SK_POWER_MGMT */\r
25538+\r
25539+#ifdef SK_DIAG_SUPPORT\r
25540+PNMI_STATIC int DiagActions(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,\r
25541+ char *pBuf, unsigned int *pLen, SK_U32 Instance,\r
25542+ unsigned int TableIndex, SK_U32 NetIndex);\r
25543+#endif /* SK_DIAG_SUPPORT */\r
25544+\r
25545+\r
25546+/* defines *******************************************************************/\r
25547+#define ID_TABLE_SIZE (sizeof(IdTable)/sizeof(IdTable[0]))\r
25548+\r
25549+\r
25550+/* global variables **********************************************************/\r
25551+\r
25552+/*\r
25553+ * Table to correlate OID with handler function and index to\r
25554+ * hardware register stored in StatAddress if applicable.\r
25555+ */\r
25556+PNMI_STATIC const SK_PNMI_TAB_ENTRY IdTable[] = {\r
25557+ {OID_GEN_XMIT_OK,\r
25558+ 0,\r
25559+ 0,\r
25560+ 0,\r
25561+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX},\r
25562+ {OID_GEN_RCV_OK,\r
25563+ 0,\r
25564+ 0,\r
25565+ 0,\r
25566+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX},\r
25567+ {OID_GEN_XMIT_ERROR,\r
25568+ 0,\r
25569+ 0,\r
25570+ 0,\r
25571+ SK_PNMI_RO, General, 0},\r
25572+ {OID_GEN_RCV_ERROR,\r
25573+ 0,\r
25574+ 0,\r
25575+ 0,\r
25576+ SK_PNMI_RO, General, 0},\r
25577+ {OID_GEN_RCV_NO_BUFFER,\r
25578+ 0,\r
25579+ 0,\r
25580+ 0,\r
25581+ SK_PNMI_RO, General, 0},\r
25582+ {OID_GEN_DIRECTED_FRAMES_XMIT,\r
25583+ 0,\r
25584+ 0,\r
25585+ 0,\r
25586+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_UNICAST},\r
25587+ {OID_GEN_MULTICAST_FRAMES_XMIT,\r
25588+ 0,\r
25589+ 0,\r
25590+ 0,\r
25591+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_MULTICAST},\r
25592+ {OID_GEN_BROADCAST_FRAMES_XMIT,\r
25593+ 0,\r
25594+ 0,\r
25595+ 0,\r
25596+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_BROADCAST},\r
25597+ {OID_GEN_DIRECTED_FRAMES_RCV,\r
25598+ 0,\r
25599+ 0,\r
25600+ 0,\r
25601+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_UNICAST},\r
25602+ {OID_GEN_MULTICAST_FRAMES_RCV,\r
25603+ 0,\r
25604+ 0,\r
25605+ 0,\r
25606+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_MULTICAST},\r
25607+ {OID_GEN_BROADCAST_FRAMES_RCV,\r
25608+ 0,\r
25609+ 0,\r
25610+ 0,\r
25611+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_BROADCAST},\r
25612+ {OID_GEN_RCV_CRC_ERROR,\r
25613+ 0,\r
25614+ 0,\r
25615+ 0,\r
25616+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_FCS},\r
25617+ {OID_GEN_TRANSMIT_QUEUE_LENGTH,\r
25618+ 0,\r
25619+ 0,\r
25620+ 0,\r
25621+ SK_PNMI_RO, General, 0},\r
25622+ {OID_802_3_PERMANENT_ADDRESS,\r
25623+ 0,\r
25624+ 0,\r
25625+ 0,\r
25626+ SK_PNMI_RO, Mac8023Stat, 0},\r
25627+ {OID_802_3_CURRENT_ADDRESS,\r
25628+ 0,\r
25629+ 0,\r
25630+ 0,\r
25631+ SK_PNMI_RO, Mac8023Stat, 0},\r
25632+ {OID_802_3_RCV_ERROR_ALIGNMENT,\r
25633+ 0,\r
25634+ 0,\r
25635+ 0,\r
25636+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_FRAMING},\r
25637+ {OID_802_3_XMIT_ONE_COLLISION,\r
25638+ 0,\r
25639+ 0,\r
25640+ 0,\r
25641+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_SINGLE_COL},\r
25642+ {OID_802_3_XMIT_MORE_COLLISIONS,\r
25643+ 0,\r
25644+ 0,\r
25645+ 0,\r
25646+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_MULTI_COL},\r
25647+ {OID_802_3_XMIT_DEFERRED,\r
25648+ 0,\r
25649+ 0,\r
25650+ 0,\r
25651+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_DEFFERAL},\r
25652+ {OID_802_3_XMIT_MAX_COLLISIONS,\r
25653+ 0,\r
25654+ 0,\r
25655+ 0,\r
25656+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_EXCESS_COL},\r
25657+ {OID_802_3_RCV_OVERRUN,\r
25658+ 0,\r
25659+ 0,\r
25660+ 0,\r
25661+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HRX_OVERFLOW},\r
25662+ {OID_802_3_XMIT_UNDERRUN,\r
25663+ 0,\r
25664+ 0,\r
25665+ 0,\r
25666+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_UNDERRUN},\r
25667+ {OID_802_3_XMIT_TIMES_CRS_LOST,\r
25668+ 0,\r
25669+ 0,\r
25670+ 0,\r
25671+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_CARRIER},\r
25672+ {OID_802_3_XMIT_LATE_COLLISIONS,\r
25673+ 0,\r
25674+ 0,\r
25675+ 0,\r
25676+ SK_PNMI_RO, Mac8023Stat, SK_PNMI_HTX_LATE_COL},\r
25677+#ifdef SK_POWER_MGMT\r
25678+ {OID_PNP_CAPABILITIES,\r
25679+ 0,\r
25680+ 0,\r
25681+ 0,\r
25682+ SK_PNMI_RO, PowerManagement, 0},\r
25683+ {OID_PNP_SET_POWER,\r
25684+ 0,\r
25685+ 0,\r
25686+ 0,\r
25687+ SK_PNMI_WO, PowerManagement, 0},\r
25688+ {OID_PNP_QUERY_POWER,\r
25689+ 0,\r
25690+ 0,\r
25691+ 0,\r
25692+ SK_PNMI_RO, PowerManagement, 0},\r
25693+ {OID_PNP_ADD_WAKE_UP_PATTERN,\r
25694+ 0,\r
25695+ 0,\r
25696+ 0,\r
25697+ SK_PNMI_WO, PowerManagement, 0},\r
25698+ {OID_PNP_REMOVE_WAKE_UP_PATTERN,\r
25699+ 0,\r
25700+ 0,\r
25701+ 0,\r
25702+ SK_PNMI_WO, PowerManagement, 0},\r
25703+ {OID_PNP_ENABLE_WAKE_UP,\r
25704+ 0,\r
25705+ 0,\r
25706+ 0,\r
25707+ SK_PNMI_RW, PowerManagement, 0},\r
25708+#endif /* SK_POWER_MGMT */\r
25709+#ifdef SK_DIAG_SUPPORT\r
25710+ {OID_SKGE_DIAG_MODE,\r
25711+ 0,\r
25712+ 0,\r
25713+ 0,\r
25714+ SK_PNMI_RW, DiagActions, 0},\r
25715+#endif /* SK_DIAG_SUPPORT */\r
25716+#ifdef SK_ASF\r
25717+ {OID_SKGE_ASF,\r
25718+ 0,\r
25719+ 0,\r
25720+ 0,\r
25721+ SK_PNMI_RW, Asf, 0},\r
25722+ {OID_SKGE_ASF_STORE_CONFIG,\r
25723+ 0,\r
25724+ 0,\r
25725+ 0,\r
25726+ SK_PNMI_RW, Asf, 0},\r
25727+ {OID_SKGE_ASF_ENA,\r
25728+ 0,\r
25729+ 0,\r
25730+ 0,\r
25731+ SK_PNMI_RW, Asf, 0},\r
25732+ {OID_SKGE_ASF_RETRANS,\r
25733+ 0,\r
25734+ 0,\r
25735+ 0,\r
25736+ SK_PNMI_RW, Asf, 0},\r
25737+ {OID_SKGE_ASF_RETRANS_INT,\r
25738+ 0,\r
25739+ 0,\r
25740+ 0,\r
25741+ SK_PNMI_RW, Asf, 0},\r
25742+ {OID_SKGE_ASF_HB_ENA,\r
25743+ 0,\r
25744+ 0,\r
25745+ 0,\r
25746+ SK_PNMI_RW, Asf, 0},\r
25747+ {OID_SKGE_ASF_HB_INT,\r
25748+ 0,\r
25749+ 0,\r
25750+ 0,\r
25751+ SK_PNMI_RW, Asf, 0},\r
25752+ {OID_SKGE_ASF_WD_ENA,\r
25753+ 0,\r
25754+ 0,\r
25755+ 0,\r
25756+ SK_PNMI_RW, Asf, 0},\r
25757+ {OID_SKGE_ASF_WD_TIME,\r
25758+ 0,\r
25759+ 0,\r
25760+ 0,\r
25761+ SK_PNMI_RW, Asf, 0},\r
25762+ {OID_SKGE_ASF_IP_SOURCE,\r
25763+ 0,\r
25764+ 0,\r
25765+ 0,\r
25766+ SK_PNMI_RW, Asf, 0},\r
25767+ {OID_SKGE_ASF_MAC_SOURCE,\r
25768+ 0,\r
25769+ 0,\r
25770+ 0,\r
25771+ SK_PNMI_RW, Asf, 0},\r
25772+ {OID_SKGE_ASF_IP_DEST,\r
25773+ 0,\r
25774+ 0,\r
25775+ 0,\r
25776+ SK_PNMI_RW, Asf, 0},\r
25777+ {OID_SKGE_ASF_MAC_DEST,\r
25778+ 0,\r
25779+ 0,\r
25780+ 0,\r
25781+ SK_PNMI_RW, Asf, 0},\r
25782+ {OID_SKGE_ASF_COMMUNITY_NAME,\r
25783+ 0,\r
25784+ 0,\r
25785+ 0,\r
25786+ SK_PNMI_RW, Asf, 0},\r
25787+ {OID_SKGE_ASF_RSP_ENA,\r
25788+ 0,\r
25789+ 0,\r
25790+ 0,\r
25791+ SK_PNMI_RW, Asf, 0},\r
25792+ {OID_SKGE_ASF_RETRANS_COUNT_MIN,\r
25793+ 0,\r
25794+ 0,\r
25795+ 0,\r
25796+ SK_PNMI_RW, Asf, 0},\r
25797+ {OID_SKGE_ASF_RETRANS_COUNT_MAX,\r
25798+ 0,\r
25799+ 0,\r
25800+ 0,\r
25801+ SK_PNMI_RW, Asf, 0},\r
25802+ {OID_SKGE_ASF_RETRANS_INT_MIN,\r
25803+ 0,\r
25804+ 0,\r
25805+ 0,\r
25806+ SK_PNMI_RW, Asf, 0},\r
25807+ {OID_SKGE_ASF_RETRANS_INT_MAX,\r
25808+ 0,\r
25809+ 0,\r
25810+ 0,\r
25811+ SK_PNMI_RW, Asf, 0},\r
25812+ {OID_SKGE_ASF_HB_INT_MIN,\r
25813+ 0,\r
25814+ 0,\r
25815+ 0,\r
25816+ SK_PNMI_RW, Asf, 0},\r
25817+ {OID_SKGE_ASF_HB_INT_MAX,\r
25818+ 0,\r
25819+ 0,\r
25820+ 0,\r
25821+ SK_PNMI_RW, Asf, 0},\r
25822+ {OID_SKGE_ASF_WD_TIME_MIN,\r
25823+ 0,\r
25824+ 0,\r
25825+ 0,\r
25826+ SK_PNMI_RW, Asf, 0},\r
25827+ {OID_SKGE_ASF_WD_TIME_MAX,\r
25828+ 0,\r
25829+ 0,\r
25830+ 0,\r
25831+ SK_PNMI_RW, Asf, 0},\r
25832+ {OID_SKGE_ASF_HB_CAP,\r
25833+ 0,\r
25834+ 0,\r
25835+ 0,\r
25836+ SK_PNMI_RW, Asf, 0},\r
25837+ {OID_SKGE_ASF_WD_TIMER_RES,\r
25838+ 0,\r
25839+ 0,\r
25840+ 0,\r
25841+ SK_PNMI_RW, Asf, 0},\r
25842+ {OID_SKGE_ASF_GUID,\r
25843+ 0,\r
25844+ 0,\r
25845+ 0,\r
25846+ SK_PNMI_RW, Asf, 0},\r
25847+ {OID_SKGE_ASF_KEY_OP,\r
25848+ 0,\r
25849+ 0,\r
25850+ 0,\r
25851+ SK_PNMI_RW, Asf, 0},\r
25852+ {OID_SKGE_ASF_KEY_ADM,\r
25853+ 0,\r
25854+ 0,\r
25855+ 0,\r
25856+ SK_PNMI_RW, Asf, 0},\r
25857+ {OID_SKGE_ASF_KEY_GEN,\r
25858+ 0,\r
25859+ 0,\r
25860+ 0,\r
25861+ SK_PNMI_RW, Asf, 0},\r
25862+ {OID_SKGE_ASF_CAP,\r
25863+ 0,\r
25864+ 0,\r
25865+ 0,\r
25866+ SK_PNMI_RW, Asf, 0},\r
25867+ {OID_SKGE_ASF_PAR_1,\r
25868+ 0,\r
25869+ 0,\r
25870+ 0,\r
25871+ SK_PNMI_RW, Asf, 0},\r
25872+ {OID_SKGE_ASF_OVERALL_OID,\r
25873+ 0,\r
25874+ 0,\r
25875+ 0,\r
25876+ SK_PNMI_RW, Asf, 0},\r
25877+ {OID_SKGE_ASF_FWVER_OID,\r
25878+ 0,\r
25879+ 0,\r
25880+ 0,\r
25881+ SK_PNMI_RO, Asf, 0},\r
25882+ {OID_SKGE_ASF_ACPI_OID,\r
25883+ 0,\r
25884+ 0,\r
25885+ 0,\r
25886+ SK_PNMI_RO, Asf, 0},\r
25887+ {OID_SKGE_ASF_SMBUS_OID,\r
25888+ 0,\r
25889+ 0,\r
25890+ 0,\r
25891+ SK_PNMI_RO, Asf, 0},\r
25892+#endif /* SK_ASF */\r
25893+ {OID_SKGE_MDB_VERSION,\r
25894+ 1,\r
25895+ 0,\r
25896+ SK_PNMI_MAI_OFF(MgmtDBVersion),\r
25897+ SK_PNMI_RO, General, 0},\r
25898+ {OID_SKGE_SUPPORTED_LIST,\r
25899+ 0,\r
25900+ 0,\r
25901+ 0,\r
25902+ SK_PNMI_RO, General, 0},\r
25903+ {OID_SKGE_ALL_DATA,\r
25904+ 0,\r
25905+ 0,\r
25906+ 0,\r
25907+ SK_PNMI_RW, OidStruct, 0},\r
25908+ {OID_SKGE_VPD_FREE_BYTES,\r
25909+ 1,\r
25910+ 0,\r
25911+ SK_PNMI_MAI_OFF(VpdFreeBytes),\r
25912+ SK_PNMI_RO, Vpd, 0},\r
25913+ {OID_SKGE_VPD_ENTRIES_LIST,\r
25914+ 1,\r
25915+ 0,\r
25916+ SK_PNMI_MAI_OFF(VpdEntriesList),\r
25917+ SK_PNMI_RO, Vpd, 0},\r
25918+ {OID_SKGE_VPD_ENTRIES_NUMBER,\r
25919+ 1,\r
25920+ 0,\r
25921+ SK_PNMI_MAI_OFF(VpdEntriesNumber),\r
25922+ SK_PNMI_RO, Vpd, 0},\r
25923+ {OID_SKGE_VPD_KEY,\r
25924+ SK_PNMI_VPD_ENTRIES,\r
25925+ sizeof(SK_PNMI_VPD),\r
25926+ SK_PNMI_OFF(Vpd) + SK_PNMI_VPD_OFF(VpdKey),\r
25927+ SK_PNMI_RO, Vpd, 0},\r
25928+ {OID_SKGE_VPD_VALUE,\r
25929+ SK_PNMI_VPD_ENTRIES,\r
25930+ sizeof(SK_PNMI_VPD),\r
25931+ SK_PNMI_OFF(Vpd) + SK_PNMI_VPD_OFF(VpdValue),\r
25932+ SK_PNMI_RO, Vpd, 0},\r
25933+ {OID_SKGE_VPD_ACCESS,\r
25934+ SK_PNMI_VPD_ENTRIES,\r
25935+ sizeof(SK_PNMI_VPD),\r
25936+ SK_PNMI_OFF(Vpd) + SK_PNMI_VPD_OFF(VpdAccess),\r
25937+ SK_PNMI_RO, Vpd, 0},\r
25938+ {OID_SKGE_VPD_ACTION,\r
25939+ SK_PNMI_VPD_ENTRIES,\r
25940+ sizeof(SK_PNMI_VPD),\r
25941+ SK_PNMI_OFF(Vpd) + SK_PNMI_VPD_OFF(VpdAction),\r
25942+ SK_PNMI_RW, Vpd, 0},\r
25943+ {OID_SKGE_PORT_NUMBER, \r
25944+ 1,\r
25945+ 0,\r
25946+ SK_PNMI_MAI_OFF(PortNumber),\r
25947+ SK_PNMI_RO, General, 0},\r
25948+ {OID_SKGE_DEVICE_TYPE,\r
25949+ 1,\r
25950+ 0,\r
25951+ SK_PNMI_MAI_OFF(DeviceType),\r
25952+ SK_PNMI_RO, General, 0},\r
25953+ {OID_SKGE_DRIVER_DESCR,\r
25954+ 1,\r
25955+ 0,\r
25956+ SK_PNMI_MAI_OFF(DriverDescr),\r
25957+ SK_PNMI_RO, General, 0},\r
25958+ {OID_SKGE_DRIVER_VERSION,\r
25959+ 1,\r
25960+ 0,\r
25961+ SK_PNMI_MAI_OFF(DriverVersion),\r
25962+ SK_PNMI_RO, General, 0},\r
25963+ {OID_SKGE_DRIVER_RELDATE,\r
25964+ 1,\r
25965+ 0,\r
25966+ SK_PNMI_MAI_OFF(DriverReleaseDate),\r
25967+ SK_PNMI_RO, General, 0},\r
25968+ {OID_SKGE_DRIVER_FILENAME,\r
25969+ 1,\r
25970+ 0,\r
25971+ SK_PNMI_MAI_OFF(DriverFileName),\r
25972+ SK_PNMI_RO, General, 0},\r
25973+ {OID_SKGE_HW_DESCR,\r
25974+ 1,\r
25975+ 0,\r
25976+ SK_PNMI_MAI_OFF(HwDescr),\r
25977+ SK_PNMI_RO, General, 0},\r
25978+ {OID_SKGE_HW_VERSION,\r
25979+ 1,\r
25980+ 0,\r
25981+ SK_PNMI_MAI_OFF(HwVersion),\r
25982+ SK_PNMI_RO, General, 0},\r
25983+ {OID_SKGE_CHIPSET,\r
25984+ 1,\r
25985+ 0,\r
25986+ SK_PNMI_MAI_OFF(Chipset),\r
25987+ SK_PNMI_RO, General, 0},\r
25988+ {OID_SKGE_CHIPID,\r
25989+ 1,\r
25990+ 0,\r
25991+ SK_PNMI_MAI_OFF(ChipId),\r
25992+ SK_PNMI_RO, General, 0},\r
25993+ {OID_SKGE_RAMSIZE,\r
25994+ 1,\r
25995+ 0,\r
25996+ SK_PNMI_MAI_OFF(RamSize),\r
25997+ SK_PNMI_RO, General, 0},\r
25998+ {OID_SKGE_VAUXAVAIL,\r
25999+ 1,\r
26000+ 0,\r
26001+ SK_PNMI_MAI_OFF(VauxAvail),\r
26002+ SK_PNMI_RO, General, 0},\r
26003+ {OID_SKGE_ACTION,\r
26004+ 1,\r
26005+ 0,\r
26006+ SK_PNMI_MAI_OFF(Action),\r
26007+ SK_PNMI_RW, Perform, 0},\r
26008+ {OID_SKGE_RESULT,\r
26009+ 1,\r
26010+ 0,\r
26011+ SK_PNMI_MAI_OFF(TestResult),\r
26012+ SK_PNMI_RO, General, 0},\r
26013+ {OID_SKGE_BUS_TYPE,\r
26014+ 1,\r
26015+ 0,\r
26016+ SK_PNMI_MAI_OFF(BusType),\r
26017+ SK_PNMI_RO, General, 0},\r
26018+ {OID_SKGE_BUS_SPEED,\r
26019+ 1,\r
26020+ 0,\r
26021+ SK_PNMI_MAI_OFF(BusSpeed),\r
26022+ SK_PNMI_RO, General, 0},\r
26023+ {OID_SKGE_BUS_WIDTH,\r
26024+ 1,\r
26025+ 0,\r
26026+ SK_PNMI_MAI_OFF(BusWidth),\r
26027+ SK_PNMI_RO, General, 0},\r
26028+ {OID_SKGE_TX_SW_QUEUE_LEN,\r
26029+ 1,\r
26030+ 0,\r
26031+ SK_PNMI_MAI_OFF(TxSwQueueLen),\r
26032+ SK_PNMI_RO, General, 0},\r
26033+ {OID_SKGE_TX_SW_QUEUE_MAX,\r
26034+ 1,\r
26035+ 0,\r
26036+ SK_PNMI_MAI_OFF(TxSwQueueMax),\r
26037+ SK_PNMI_RO, General, 0},\r
26038+ {OID_SKGE_TX_RETRY,\r
26039+ 1,\r
26040+ 0,\r
26041+ SK_PNMI_MAI_OFF(TxRetryCts),\r
26042+ SK_PNMI_RO, General, 0},\r
26043+ {OID_SKGE_RX_INTR_CTS,\r
26044+ 1,\r
26045+ 0,\r
26046+ SK_PNMI_MAI_OFF(RxIntrCts),\r
26047+ SK_PNMI_RO, General, 0},\r
26048+ {OID_SKGE_TX_INTR_CTS,\r
26049+ 1,\r
26050+ 0,\r
26051+ SK_PNMI_MAI_OFF(TxIntrCts),\r
26052+ SK_PNMI_RO, General, 0},\r
26053+ {OID_SKGE_RX_NO_BUF_CTS,\r
26054+ 1,\r
26055+ 0,\r
26056+ SK_PNMI_MAI_OFF(RxNoBufCts),\r
26057+ SK_PNMI_RO, General, 0},\r
26058+ {OID_SKGE_TX_NO_BUF_CTS,\r
26059+ 1,\r
26060+ 0,\r
26061+ SK_PNMI_MAI_OFF(TxNoBufCts),\r
26062+ SK_PNMI_RO, General, 0},\r
26063+ {OID_SKGE_TX_USED_DESCR_NO,\r
26064+ 1,\r
26065+ 0,\r
26066+ SK_PNMI_MAI_OFF(TxUsedDescrNo),\r
26067+ SK_PNMI_RO, General, 0},\r
26068+ {OID_SKGE_RX_DELIVERED_CTS,\r
26069+ 1,\r
26070+ 0,\r
26071+ SK_PNMI_MAI_OFF(RxDeliveredCts),\r
26072+ SK_PNMI_RO, General, 0},\r
26073+ {OID_SKGE_RX_OCTETS_DELIV_CTS,\r
26074+ 1,\r
26075+ 0,\r
26076+ SK_PNMI_MAI_OFF(RxOctetsDeliveredCts),\r
26077+ SK_PNMI_RO, General, 0},\r
26078+ {OID_SKGE_RX_HW_ERROR_CTS,\r
26079+ 1,\r
26080+ 0,\r
26081+ SK_PNMI_MAI_OFF(RxHwErrorsCts),\r
26082+ SK_PNMI_RO, General, 0},\r
26083+ {OID_SKGE_TX_HW_ERROR_CTS,\r
26084+ 1,\r
26085+ 0,\r
26086+ SK_PNMI_MAI_OFF(TxHwErrorsCts),\r
26087+ SK_PNMI_RO, General, 0},\r
26088+ {OID_SKGE_IN_ERRORS_CTS,\r
26089+ 1,\r
26090+ 0,\r
26091+ SK_PNMI_MAI_OFF(InErrorsCts),\r
26092+ SK_PNMI_RO, General, 0},\r
26093+ {OID_SKGE_OUT_ERROR_CTS,\r
26094+ 1,\r
26095+ 0,\r
26096+ SK_PNMI_MAI_OFF(OutErrorsCts),\r
26097+ SK_PNMI_RO, General, 0},\r
26098+ {OID_SKGE_ERR_RECOVERY_CTS,\r
26099+ 1,\r
26100+ 0,\r
26101+ SK_PNMI_MAI_OFF(ErrRecoveryCts),\r
26102+ SK_PNMI_RO, General, 0},\r
26103+ {OID_SKGE_SYSUPTIME,\r
26104+ 1,\r
26105+ 0,\r
26106+ SK_PNMI_MAI_OFF(SysUpTime),\r
26107+ SK_PNMI_RO, General, 0},\r
26108+ {OID_SKGE_SENSOR_NUMBER,\r
26109+ 1,\r
26110+ 0,\r
26111+ SK_PNMI_MAI_OFF(SensorNumber),\r
26112+ SK_PNMI_RO, General, 0},\r
26113+ {OID_SKGE_SENSOR_INDEX,\r
26114+ SK_PNMI_SENSOR_ENTRIES,\r
26115+ sizeof(SK_PNMI_SENSOR),\r
26116+ SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorIndex),\r
26117+ SK_PNMI_RO, SensorStat, 0},\r
26118+ {OID_SKGE_SENSOR_DESCR,\r
26119+ SK_PNMI_SENSOR_ENTRIES,\r
26120+ sizeof(SK_PNMI_SENSOR),\r
26121+ SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorDescr),\r
26122+ SK_PNMI_RO, SensorStat, 0},\r
26123+ {OID_SKGE_SENSOR_TYPE,\r
26124+ SK_PNMI_SENSOR_ENTRIES,\r
26125+ sizeof(SK_PNMI_SENSOR),\r
26126+ SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorType),\r
26127+ SK_PNMI_RO, SensorStat, 0},\r
26128+ {OID_SKGE_SENSOR_VALUE,\r
26129+ SK_PNMI_SENSOR_ENTRIES,\r
26130+ sizeof(SK_PNMI_SENSOR),\r
26131+ SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorValue),\r
26132+ SK_PNMI_RO, SensorStat, 0},\r
26133+ {OID_SKGE_SENSOR_WAR_THRES_LOW,\r
26134+ SK_PNMI_SENSOR_ENTRIES,\r
26135+ sizeof(SK_PNMI_SENSOR),\r
26136+ SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorWarningThresholdLow),\r
26137+ SK_PNMI_RO, SensorStat, 0},\r
26138+ {OID_SKGE_SENSOR_WAR_THRES_UPP,\r
26139+ SK_PNMI_SENSOR_ENTRIES,\r
26140+ sizeof(SK_PNMI_SENSOR),\r
26141+ SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorWarningThresholdHigh),\r
26142+ SK_PNMI_RO, SensorStat, 0},\r
26143+ {OID_SKGE_SENSOR_ERR_THRES_LOW,\r
26144+ SK_PNMI_SENSOR_ENTRIES,\r
26145+ sizeof(SK_PNMI_SENSOR),\r
26146+ SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorErrorThresholdLow),\r
26147+ SK_PNMI_RO, SensorStat, 0},\r
26148+ {OID_SKGE_SENSOR_ERR_THRES_UPP,\r
26149+ SK_PNMI_SENSOR_ENTRIES,\r
26150+ sizeof(SK_PNMI_SENSOR),\r
26151+ SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorErrorThresholdHigh),\r
26152+ SK_PNMI_RO, SensorStat, 0},\r
26153+ {OID_SKGE_SENSOR_STATUS,\r
26154+ SK_PNMI_SENSOR_ENTRIES,\r
26155+ sizeof(SK_PNMI_SENSOR),\r
26156+ SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorStatus),\r
26157+ SK_PNMI_RO, SensorStat, 0},\r
26158+ {OID_SKGE_SENSOR_WAR_CTS,\r
26159+ SK_PNMI_SENSOR_ENTRIES,\r
26160+ sizeof(SK_PNMI_SENSOR),\r
26161+ SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorWarningCts),\r
26162+ SK_PNMI_RO, SensorStat, 0},\r
26163+ {OID_SKGE_SENSOR_ERR_CTS,\r
26164+ SK_PNMI_SENSOR_ENTRIES,\r
26165+ sizeof(SK_PNMI_SENSOR),\r
26166+ SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorErrorCts),\r
26167+ SK_PNMI_RO, SensorStat, 0},\r
26168+ {OID_SKGE_SENSOR_WAR_TIME,\r
26169+ SK_PNMI_SENSOR_ENTRIES,\r
26170+ sizeof(SK_PNMI_SENSOR),\r
26171+ SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorWarningTimestamp),\r
26172+ SK_PNMI_RO, SensorStat, 0},\r
26173+ {OID_SKGE_SENSOR_ERR_TIME,\r
26174+ SK_PNMI_SENSOR_ENTRIES,\r
26175+ sizeof(SK_PNMI_SENSOR),\r
26176+ SK_PNMI_OFF(Sensor) + SK_PNMI_SEN_OFF(SensorErrorTimestamp),\r
26177+ SK_PNMI_RO, SensorStat, 0},\r
26178+ {OID_SKGE_CHKSM_NUMBER,\r
26179+ 1,\r
26180+ 0,\r
26181+ SK_PNMI_MAI_OFF(ChecksumNumber),\r
26182+ SK_PNMI_RO, General, 0},\r
26183+ {OID_SKGE_CHKSM_RX_OK_CTS,\r
26184+ SKCS_NUM_PROTOCOLS,\r
26185+ sizeof(SK_PNMI_CHECKSUM),\r
26186+ SK_PNMI_OFF(Checksum) + SK_PNMI_CHK_OFF(ChecksumRxOkCts),\r
26187+ SK_PNMI_RO, CsumStat, 0},\r
26188+ {OID_SKGE_CHKSM_RX_UNABLE_CTS,\r
26189+ SKCS_NUM_PROTOCOLS,\r
26190+ sizeof(SK_PNMI_CHECKSUM),\r
26191+ SK_PNMI_OFF(Checksum) + SK_PNMI_CHK_OFF(ChecksumRxUnableCts),\r
26192+ SK_PNMI_RO, CsumStat, 0},\r
26193+ {OID_SKGE_CHKSM_RX_ERR_CTS,\r
26194+ SKCS_NUM_PROTOCOLS,\r
26195+ sizeof(SK_PNMI_CHECKSUM),\r
26196+ SK_PNMI_OFF(Checksum) + SK_PNMI_CHK_OFF(ChecksumRxErrCts),\r
26197+ SK_PNMI_RO, CsumStat, 0},\r
26198+ {OID_SKGE_CHKSM_TX_OK_CTS,\r
26199+ SKCS_NUM_PROTOCOLS,\r
26200+ sizeof(SK_PNMI_CHECKSUM),\r
26201+ SK_PNMI_OFF(Checksum) + SK_PNMI_CHK_OFF(ChecksumTxOkCts),\r
26202+ SK_PNMI_RO, CsumStat, 0},\r
26203+ {OID_SKGE_CHKSM_TX_UNABLE_CTS,\r
26204+ SKCS_NUM_PROTOCOLS,\r
26205+ sizeof(SK_PNMI_CHECKSUM),\r
26206+ SK_PNMI_OFF(Checksum) + SK_PNMI_CHK_OFF(ChecksumTxUnableCts),\r
26207+ SK_PNMI_RO, CsumStat, 0},\r
26208+ {OID_SKGE_STAT_TX,\r
26209+ SK_PNMI_MAC_ENTRIES,\r
26210+ sizeof(SK_PNMI_STAT),\r
26211+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxOkCts),\r
26212+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX},\r
26213+ {OID_SKGE_STAT_TX_OCTETS,\r
26214+ SK_PNMI_MAC_ENTRIES,\r
26215+ sizeof(SK_PNMI_STAT),\r
26216+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxOctetsOkCts),\r
26217+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_OCTET},\r
26218+ {OID_SKGE_STAT_TX_BROADCAST,\r
26219+ SK_PNMI_MAC_ENTRIES,\r
26220+ sizeof(SK_PNMI_STAT),\r
26221+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxBroadcastOkCts),\r
26222+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_BROADCAST},\r
26223+ {OID_SKGE_STAT_TX_MULTICAST,\r
26224+ SK_PNMI_MAC_ENTRIES,\r
26225+ sizeof(SK_PNMI_STAT),\r
26226+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxMulticastOkCts),\r
26227+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_MULTICAST},\r
26228+ {OID_SKGE_STAT_TX_UNICAST,\r
26229+ SK_PNMI_MAC_ENTRIES,\r
26230+ sizeof(SK_PNMI_STAT),\r
26231+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxUnicastOkCts),\r
26232+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_UNICAST},\r
26233+ {OID_SKGE_STAT_TX_LONGFRAMES,\r
26234+ SK_PNMI_MAC_ENTRIES,\r
26235+ sizeof(SK_PNMI_STAT),\r
26236+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxLongFramesCts),\r
26237+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_LONGFRAMES},\r
26238+ {OID_SKGE_STAT_TX_BURST,\r
26239+ SK_PNMI_MAC_ENTRIES,\r
26240+ sizeof(SK_PNMI_STAT),\r
26241+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxBurstCts),\r
26242+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_BURST},\r
26243+ {OID_SKGE_STAT_TX_PFLOWC,\r
26244+ SK_PNMI_MAC_ENTRIES,\r
26245+ sizeof(SK_PNMI_STAT),\r
26246+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxPauseMacCtrlCts),\r
26247+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_PMACC},\r
26248+ {OID_SKGE_STAT_TX_FLOWC,\r
26249+ SK_PNMI_MAC_ENTRIES,\r
26250+ sizeof(SK_PNMI_STAT),\r
26251+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxMacCtrlCts),\r
26252+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_MACC},\r
26253+ {OID_SKGE_STAT_TX_SINGLE_COL,\r
26254+ SK_PNMI_MAC_ENTRIES,\r
26255+ sizeof(SK_PNMI_STAT),\r
26256+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxSingleCollisionCts),\r
26257+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_SINGLE_COL},\r
26258+ {OID_SKGE_STAT_TX_MULTI_COL,\r
26259+ SK_PNMI_MAC_ENTRIES,\r
26260+ sizeof(SK_PNMI_STAT),\r
26261+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxMultipleCollisionCts),\r
26262+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_MULTI_COL},\r
26263+ {OID_SKGE_STAT_TX_EXCESS_COL,\r
26264+ SK_PNMI_MAC_ENTRIES,\r
26265+ sizeof(SK_PNMI_STAT),\r
26266+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxExcessiveCollisionCts),\r
26267+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_EXCESS_COL},\r
26268+ {OID_SKGE_STAT_TX_LATE_COL,\r
26269+ SK_PNMI_MAC_ENTRIES,\r
26270+ sizeof(SK_PNMI_STAT),\r
26271+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxLateCollisionCts),\r
26272+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_LATE_COL},\r
26273+ {OID_SKGE_STAT_TX_DEFFERAL,\r
26274+ SK_PNMI_MAC_ENTRIES,\r
26275+ sizeof(SK_PNMI_STAT),\r
26276+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxDeferralCts),\r
26277+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_DEFFERAL},\r
26278+ {OID_SKGE_STAT_TX_EXCESS_DEF,\r
26279+ SK_PNMI_MAC_ENTRIES,\r
26280+ sizeof(SK_PNMI_STAT),\r
26281+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxExcessiveDeferralCts),\r
26282+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_EXCESS_DEF},\r
26283+ {OID_SKGE_STAT_TX_UNDERRUN,\r
26284+ SK_PNMI_MAC_ENTRIES,\r
26285+ sizeof(SK_PNMI_STAT),\r
26286+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxFifoUnderrunCts),\r
26287+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_UNDERRUN},\r
26288+ {OID_SKGE_STAT_TX_CARRIER,\r
26289+ SK_PNMI_MAC_ENTRIES,\r
26290+ sizeof(SK_PNMI_STAT),\r
26291+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxCarrierCts),\r
26292+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_CARRIER},\r
26293+/* {OID_SKGE_STAT_TX_UTIL,\r
26294+ SK_PNMI_MAC_ENTRIES,\r
26295+ sizeof(SK_PNMI_STAT),\r
26296+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxUtilization),\r
26297+ SK_PNMI_RO, MacPrivateStat, (SK_U16)(-1)}, */\r
26298+ {OID_SKGE_STAT_TX_64,\r
26299+ SK_PNMI_MAC_ENTRIES,\r
26300+ sizeof(SK_PNMI_STAT),\r
26301+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTx64Cts),\r
26302+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_64},\r
26303+ {OID_SKGE_STAT_TX_127,\r
26304+ SK_PNMI_MAC_ENTRIES,\r
26305+ sizeof(SK_PNMI_STAT),\r
26306+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTx127Cts),\r
26307+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_127},\r
26308+ {OID_SKGE_STAT_TX_255,\r
26309+ SK_PNMI_MAC_ENTRIES,\r
26310+ sizeof(SK_PNMI_STAT),\r
26311+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTx255Cts),\r
26312+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_255},\r
26313+ {OID_SKGE_STAT_TX_511,\r
26314+ SK_PNMI_MAC_ENTRIES,\r
26315+ sizeof(SK_PNMI_STAT),\r
26316+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTx511Cts),\r
26317+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_511},\r
26318+ {OID_SKGE_STAT_TX_1023,\r
26319+ SK_PNMI_MAC_ENTRIES,\r
26320+ sizeof(SK_PNMI_STAT),\r
26321+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTx1023Cts),\r
26322+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_1023},\r
26323+ {OID_SKGE_STAT_TX_MAX,\r
26324+ SK_PNMI_MAC_ENTRIES,\r
26325+ sizeof(SK_PNMI_STAT),\r
26326+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxMaxCts),\r
26327+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_MAX},\r
26328+ {OID_SKGE_STAT_TX_SYNC,\r
26329+ SK_PNMI_MAC_ENTRIES,\r
26330+ sizeof(SK_PNMI_STAT),\r
26331+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxSyncCts),\r
26332+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_SYNC},\r
26333+ {OID_SKGE_STAT_TX_SYNC_OCTETS,\r
26334+ SK_PNMI_MAC_ENTRIES,\r
26335+ sizeof(SK_PNMI_STAT),\r
26336+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatTxSyncOctetsCts),\r
26337+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HTX_SYNC_OCTET},\r
26338+ {OID_SKGE_STAT_RX,\r
26339+ SK_PNMI_MAC_ENTRIES,\r
26340+ sizeof(SK_PNMI_STAT),\r
26341+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxOkCts),\r
26342+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX},\r
26343+ {OID_SKGE_STAT_RX_OCTETS,\r
26344+ SK_PNMI_MAC_ENTRIES,\r
26345+ sizeof(SK_PNMI_STAT),\r
26346+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxOctetsOkCts),\r
26347+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_OCTET},\r
26348+ {OID_SKGE_STAT_RX_BROADCAST,\r
26349+ SK_PNMI_MAC_ENTRIES,\r
26350+ sizeof(SK_PNMI_STAT),\r
26351+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxBroadcastOkCts),\r
26352+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_BROADCAST},\r
26353+ {OID_SKGE_STAT_RX_MULTICAST,\r
26354+ SK_PNMI_MAC_ENTRIES,\r
26355+ sizeof(SK_PNMI_STAT),\r
26356+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxMulticastOkCts),\r
26357+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_MULTICAST},\r
26358+ {OID_SKGE_STAT_RX_UNICAST,\r
26359+ SK_PNMI_MAC_ENTRIES,\r
26360+ sizeof(SK_PNMI_STAT),\r
26361+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxUnicastOkCts),\r
26362+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_UNICAST},\r
26363+ {OID_SKGE_STAT_RX_LONGFRAMES,\r
26364+ SK_PNMI_MAC_ENTRIES,\r
26365+ sizeof(SK_PNMI_STAT),\r
26366+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxLongFramesCts),\r
26367+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_LONGFRAMES},\r
26368+ {OID_SKGE_STAT_RX_PFLOWC,\r
26369+ SK_PNMI_MAC_ENTRIES,\r
26370+ sizeof(SK_PNMI_STAT),\r
26371+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxPauseMacCtrlCts),\r
26372+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_PMACC},\r
26373+ {OID_SKGE_STAT_RX_FLOWC,\r
26374+ SK_PNMI_MAC_ENTRIES,\r
26375+ sizeof(SK_PNMI_STAT),\r
26376+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxMacCtrlCts),\r
26377+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_MACC},\r
26378+ {OID_SKGE_STAT_RX_PFLOWC_ERR,\r
26379+ SK_PNMI_MAC_ENTRIES,\r
26380+ sizeof(SK_PNMI_STAT),\r
26381+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxPauseMacCtrlErrorCts),\r
26382+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_PMACC_ERR},\r
26383+ {OID_SKGE_STAT_RX_FLOWC_UNKWN,\r
26384+ SK_PNMI_MAC_ENTRIES,\r
26385+ sizeof(SK_PNMI_STAT),\r
26386+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxMacCtrlUnknownCts),\r
26387+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_MACC_UNKWN},\r
26388+ {OID_SKGE_STAT_RX_BURST,\r
26389+ SK_PNMI_MAC_ENTRIES,\r
26390+ sizeof(SK_PNMI_STAT),\r
26391+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxBurstCts),\r
26392+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_BURST},\r
26393+ {OID_SKGE_STAT_RX_MISSED,\r
26394+ SK_PNMI_MAC_ENTRIES,\r
26395+ sizeof(SK_PNMI_STAT),\r
26396+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxMissedCts),\r
26397+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_MISSED},\r
26398+ {OID_SKGE_STAT_RX_FRAMING,\r
26399+ SK_PNMI_MAC_ENTRIES,\r
26400+ sizeof(SK_PNMI_STAT),\r
26401+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxFramingCts),\r
26402+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_FRAMING},\r
26403+ {OID_SKGE_STAT_RX_OVERFLOW,\r
26404+ SK_PNMI_MAC_ENTRIES,\r
26405+ sizeof(SK_PNMI_STAT),\r
26406+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxFifoOverflowCts),\r
26407+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_OVERFLOW},\r
26408+ {OID_SKGE_STAT_RX_JABBER,\r
26409+ SK_PNMI_MAC_ENTRIES,\r
26410+ sizeof(SK_PNMI_STAT),\r
26411+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxJabberCts),\r
26412+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_JABBER},\r
26413+ {OID_SKGE_STAT_RX_CARRIER,\r
26414+ SK_PNMI_MAC_ENTRIES,\r
26415+ sizeof(SK_PNMI_STAT),\r
26416+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxCarrierCts),\r
26417+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_CARRIER},\r
26418+ {OID_SKGE_STAT_RX_IR_LENGTH,\r
26419+ SK_PNMI_MAC_ENTRIES,\r
26420+ sizeof(SK_PNMI_STAT),\r
26421+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxIRLengthCts),\r
26422+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_IRLENGTH},\r
26423+ {OID_SKGE_STAT_RX_SYMBOL,\r
26424+ SK_PNMI_MAC_ENTRIES,\r
26425+ sizeof(SK_PNMI_STAT),\r
26426+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxSymbolCts),\r
26427+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_SYMBOL},\r
26428+ {OID_SKGE_STAT_RX_SHORTS,\r
26429+ SK_PNMI_MAC_ENTRIES,\r
26430+ sizeof(SK_PNMI_STAT),\r
26431+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxShortsCts),\r
26432+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_SHORTS},\r
26433+ {OID_SKGE_STAT_RX_RUNT,\r
26434+ SK_PNMI_MAC_ENTRIES,\r
26435+ sizeof(SK_PNMI_STAT),\r
26436+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxRuntCts),\r
26437+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_RUNT},\r
26438+ {OID_SKGE_STAT_RX_CEXT,\r
26439+ SK_PNMI_MAC_ENTRIES,\r
26440+ sizeof(SK_PNMI_STAT),\r
26441+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxCextCts),\r
26442+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_CEXT},\r
26443+ {OID_SKGE_STAT_RX_TOO_LONG,\r
26444+ SK_PNMI_MAC_ENTRIES,\r
26445+ sizeof(SK_PNMI_STAT),\r
26446+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxTooLongCts),\r
26447+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_TOO_LONG},\r
26448+ {OID_SKGE_STAT_RX_FCS,\r
26449+ SK_PNMI_MAC_ENTRIES,\r
26450+ sizeof(SK_PNMI_STAT),\r
26451+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxFcsCts),\r
26452+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_FCS},\r
26453+/* {OID_SKGE_STAT_RX_UTIL,\r
26454+ SK_PNMI_MAC_ENTRIES,\r
26455+ sizeof(SK_PNMI_STAT),\r
26456+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxUtilization),\r
26457+ SK_PNMI_RO, MacPrivateStat, (SK_U16)(-1)}, */\r
26458+ {OID_SKGE_STAT_RX_64,\r
26459+ SK_PNMI_MAC_ENTRIES,\r
26460+ sizeof(SK_PNMI_STAT),\r
26461+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRx64Cts),\r
26462+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_64},\r
26463+ {OID_SKGE_STAT_RX_127,\r
26464+ SK_PNMI_MAC_ENTRIES,\r
26465+ sizeof(SK_PNMI_STAT),\r
26466+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRx127Cts),\r
26467+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_127},\r
26468+ {OID_SKGE_STAT_RX_255,\r
26469+ SK_PNMI_MAC_ENTRIES,\r
26470+ sizeof(SK_PNMI_STAT),\r
26471+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRx255Cts),\r
26472+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_255},\r
26473+ {OID_SKGE_STAT_RX_511,\r
26474+ SK_PNMI_MAC_ENTRIES,\r
26475+ sizeof(SK_PNMI_STAT),\r
26476+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRx511Cts),\r
26477+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_511},\r
26478+ {OID_SKGE_STAT_RX_1023,\r
26479+ SK_PNMI_MAC_ENTRIES,\r
26480+ sizeof(SK_PNMI_STAT),\r
26481+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRx1023Cts),\r
26482+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_1023},\r
26483+ {OID_SKGE_STAT_RX_MAX,\r
26484+ SK_PNMI_MAC_ENTRIES,\r
26485+ sizeof(SK_PNMI_STAT),\r
26486+ SK_PNMI_OFF(Stat) + SK_PNMI_STA_OFF(StatRxMaxCts),\r
26487+ SK_PNMI_RO, MacPrivateStat, SK_PNMI_HRX_MAX},\r
26488+ {OID_SKGE_PHYS_CUR_ADDR,\r
26489+ SK_PNMI_MAC_ENTRIES,\r
26490+ sizeof(SK_PNMI_CONF),\r
26491+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfMacCurrentAddr),\r
26492+ SK_PNMI_RW, Addr, 0},\r
26493+ {OID_SKGE_PHYS_FAC_ADDR,\r
26494+ SK_PNMI_MAC_ENTRIES,\r
26495+ sizeof(SK_PNMI_CONF),\r
26496+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfMacFactoryAddr),\r
26497+ SK_PNMI_RO, Addr, 0},\r
26498+ {OID_SKGE_PMD,\r
26499+ SK_PNMI_MAC_ENTRIES,\r
26500+ sizeof(SK_PNMI_CONF),\r
26501+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPMD),\r
26502+ SK_PNMI_RO, MacPrivateConf, 0},\r
26503+ {OID_SKGE_CONNECTOR,\r
26504+ SK_PNMI_MAC_ENTRIES,\r
26505+ sizeof(SK_PNMI_CONF),\r
26506+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfConnector),\r
26507+ SK_PNMI_RO, MacPrivateConf, 0},\r
26508+ {OID_SKGE_PHY_TYPE,\r
26509+ SK_PNMI_MAC_ENTRIES,\r
26510+ sizeof(SK_PNMI_CONF),\r
26511+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyType),\r
26512+ SK_PNMI_RO, MacPrivateConf, 0},\r
26513+#ifdef SK_PHY_LP_MODE\r
26514+ {OID_SKGE_PHY_LP_MODE,\r
26515+ SK_PNMI_MAC_ENTRIES,\r
26516+ sizeof(SK_PNMI_CONF),\r
26517+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyMode),\r
26518+ SK_PNMI_RW, MacPrivateConf, 0},\r
26519+#endif \r
26520+ {OID_SKGE_LINK_CAP,\r
26521+ SK_PNMI_MAC_ENTRIES,\r
26522+ sizeof(SK_PNMI_CONF),\r
26523+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfLinkCapability),\r
26524+ SK_PNMI_RO, MacPrivateConf, 0},\r
26525+ {OID_SKGE_LINK_MODE,\r
26526+ SK_PNMI_MAC_ENTRIES,\r
26527+ sizeof(SK_PNMI_CONF),\r
26528+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfLinkMode),\r
26529+ SK_PNMI_RW, MacPrivateConf, 0},\r
26530+ {OID_SKGE_LINK_MODE_STATUS,\r
26531+ SK_PNMI_MAC_ENTRIES,\r
26532+ sizeof(SK_PNMI_CONF),\r
26533+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfLinkModeStatus),\r
26534+ SK_PNMI_RO, MacPrivateConf, 0},\r
26535+ {OID_SKGE_LINK_STATUS,\r
26536+ SK_PNMI_MAC_ENTRIES,\r
26537+ sizeof(SK_PNMI_CONF),\r
26538+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfLinkStatus),\r
26539+ SK_PNMI_RO, MacPrivateConf, 0},\r
26540+ {OID_SKGE_FLOWCTRL_CAP,\r
26541+ SK_PNMI_MAC_ENTRIES,\r
26542+ sizeof(SK_PNMI_CONF),\r
26543+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfFlowCtrlCapability),\r
26544+ SK_PNMI_RO, MacPrivateConf, 0},\r
26545+ {OID_SKGE_FLOWCTRL_MODE,\r
26546+ SK_PNMI_MAC_ENTRIES,\r
26547+ sizeof(SK_PNMI_CONF),\r
26548+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfFlowCtrlMode),\r
26549+ SK_PNMI_RW, MacPrivateConf, 0},\r
26550+ {OID_SKGE_FLOWCTRL_STATUS,\r
26551+ SK_PNMI_MAC_ENTRIES,\r
26552+ sizeof(SK_PNMI_CONF),\r
26553+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfFlowCtrlStatus),\r
26554+ SK_PNMI_RO, MacPrivateConf, 0},\r
26555+ {OID_SKGE_PHY_OPERATION_CAP,\r
26556+ SK_PNMI_MAC_ENTRIES,\r
26557+ sizeof(SK_PNMI_CONF),\r
26558+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyOperationCapability),\r
26559+ SK_PNMI_RO, MacPrivateConf, 0},\r
26560+ {OID_SKGE_PHY_OPERATION_MODE,\r
26561+ SK_PNMI_MAC_ENTRIES,\r
26562+ sizeof(SK_PNMI_CONF),\r
26563+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyOperationMode),\r
26564+ SK_PNMI_RW, MacPrivateConf, 0},\r
26565+ {OID_SKGE_PHY_OPERATION_STATUS,\r
26566+ SK_PNMI_MAC_ENTRIES,\r
26567+ sizeof(SK_PNMI_CONF),\r
26568+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfPhyOperationStatus),\r
26569+ SK_PNMI_RO, MacPrivateConf, 0},\r
26570+ {OID_SKGE_SPEED_CAP,\r
26571+ SK_PNMI_MAC_ENTRIES,\r
26572+ sizeof(SK_PNMI_CONF),\r
26573+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfSpeedCapability),\r
26574+ SK_PNMI_RO, MacPrivateConf, 0},\r
26575+ {OID_SKGE_SPEED_MODE,\r
26576+ SK_PNMI_MAC_ENTRIES,\r
26577+ sizeof(SK_PNMI_CONF),\r
26578+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfSpeedMode),\r
26579+ SK_PNMI_RW, MacPrivateConf, 0},\r
26580+ {OID_SKGE_SPEED_STATUS,\r
26581+ SK_PNMI_MAC_ENTRIES,\r
26582+ sizeof(SK_PNMI_CONF),\r
26583+ SK_PNMI_OFF(Conf) + SK_PNMI_CNF_OFF(ConfSpeedStatus),\r
26584+ SK_PNMI_RO, MacPrivateConf, 0},\r
26585+ {OID_SKGE_TRAP,\r
26586+ 1,\r
26587+ 0,\r
26588+ SK_PNMI_MAI_OFF(Trap),\r
26589+ SK_PNMI_RO, General, 0},\r
26590+ {OID_SKGE_TRAP_NUMBER,\r
26591+ 1,\r
26592+ 0,\r
26593+ SK_PNMI_MAI_OFF(TrapNumber),\r
26594+ SK_PNMI_RO, General, 0},\r
26595+ {OID_SKGE_RLMT_MODE,\r
26596+ 1,\r
26597+ 0,\r
26598+ SK_PNMI_MAI_OFF(RlmtMode),\r
26599+ SK_PNMI_RW, Rlmt, 0},\r
26600+ {OID_SKGE_RLMT_PORT_NUMBER,\r
26601+ 1,\r
26602+ 0,\r
26603+ SK_PNMI_MAI_OFF(RlmtPortNumber),\r
26604+ SK_PNMI_RO, Rlmt, 0},\r
26605+ {OID_SKGE_RLMT_PORT_ACTIVE,\r
26606+ 1,\r
26607+ 0,\r
26608+ SK_PNMI_MAI_OFF(RlmtPortActive),\r
26609+ SK_PNMI_RO, Rlmt, 0},\r
26610+ {OID_SKGE_RLMT_PORT_PREFERRED,\r
26611+ 1,\r
26612+ 0,\r
26613+ SK_PNMI_MAI_OFF(RlmtPortPreferred),\r
26614+ SK_PNMI_RW, Rlmt, 0},\r
26615+ {OID_SKGE_RLMT_CHANGE_CTS,\r
26616+ 1,\r
26617+ 0,\r
26618+ SK_PNMI_MAI_OFF(RlmtChangeCts),\r
26619+ SK_PNMI_RO, Rlmt, 0},\r
26620+ {OID_SKGE_RLMT_CHANGE_TIME,\r
26621+ 1,\r
26622+ 0,\r
26623+ SK_PNMI_MAI_OFF(RlmtChangeTime),\r
26624+ SK_PNMI_RO, Rlmt, 0},\r
26625+ {OID_SKGE_RLMT_CHANGE_ESTIM,\r
26626+ 1,\r
26627+ 0,\r
26628+ SK_PNMI_MAI_OFF(RlmtChangeEstimate),\r
26629+ SK_PNMI_RO, Rlmt, 0},\r
26630+ {OID_SKGE_RLMT_CHANGE_THRES,\r
26631+ 1,\r
26632+ 0,\r
26633+ SK_PNMI_MAI_OFF(RlmtChangeThreshold),\r
26634+ SK_PNMI_RW, Rlmt, 0},\r
26635+ {OID_SKGE_RLMT_PORT_INDEX,\r
26636+ SK_PNMI_MAC_ENTRIES,\r
26637+ sizeof(SK_PNMI_RLMT),\r
26638+ SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtIndex),\r
26639+ SK_PNMI_RO, RlmtStat, 0},\r
26640+ {OID_SKGE_RLMT_STATUS,\r
26641+ SK_PNMI_MAC_ENTRIES,\r
26642+ sizeof(SK_PNMI_RLMT),\r
26643+ SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtStatus),\r
26644+ SK_PNMI_RO, RlmtStat, 0},\r
26645+ {OID_SKGE_RLMT_TX_HELLO_CTS,\r
26646+ SK_PNMI_MAC_ENTRIES,\r
26647+ sizeof(SK_PNMI_RLMT),\r
26648+ SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtTxHelloCts),\r
26649+ SK_PNMI_RO, RlmtStat, 0},\r
26650+ {OID_SKGE_RLMT_RX_HELLO_CTS,\r
26651+ SK_PNMI_MAC_ENTRIES,\r
26652+ sizeof(SK_PNMI_RLMT),\r
26653+ SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtRxHelloCts),\r
26654+ SK_PNMI_RO, RlmtStat, 0},\r
26655+ {OID_SKGE_RLMT_TX_SP_REQ_CTS,\r
26656+ SK_PNMI_MAC_ENTRIES,\r
26657+ sizeof(SK_PNMI_RLMT),\r
26658+ SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtTxSpHelloReqCts),\r
26659+ SK_PNMI_RO, RlmtStat, 0},\r
26660+ {OID_SKGE_RLMT_RX_SP_CTS,\r
26661+ SK_PNMI_MAC_ENTRIES,\r
26662+ sizeof(SK_PNMI_RLMT),\r
26663+ SK_PNMI_OFF(Rlmt) + SK_PNMI_RLM_OFF(RlmtRxSpHelloCts),\r
26664+ SK_PNMI_RO, RlmtStat, 0},\r
26665+ {OID_SKGE_RLMT_MONITOR_NUMBER,\r
26666+ 1,\r
26667+ 0,\r
26668+ SK_PNMI_MAI_OFF(RlmtMonitorNumber),\r
26669+ SK_PNMI_RO, General, 0},\r
26670+ {OID_SKGE_RLMT_MONITOR_INDEX,\r
26671+ SK_PNMI_MONITOR_ENTRIES,\r
26672+ sizeof(SK_PNMI_RLMT_MONITOR),\r
26673+ SK_PNMI_OFF(RlmtMonitor) + SK_PNMI_MON_OFF(RlmtMonitorIndex),\r
26674+ SK_PNMI_RO, Monitor, 0},\r
26675+ {OID_SKGE_RLMT_MONITOR_ADDR,\r
26676+ SK_PNMI_MONITOR_ENTRIES,\r
26677+ sizeof(SK_PNMI_RLMT_MONITOR),\r
26678+ SK_PNMI_OFF(RlmtMonitor) + SK_PNMI_MON_OFF(RlmtMonitorAddr),\r
26679+ SK_PNMI_RO, Monitor, 0},\r
26680+ {OID_SKGE_RLMT_MONITOR_ERRS,\r
26681+ SK_PNMI_MONITOR_ENTRIES,\r
26682+ sizeof(SK_PNMI_RLMT_MONITOR),\r
26683+ SK_PNMI_OFF(RlmtMonitor) + SK_PNMI_MON_OFF(RlmtMonitorErrorCts),\r
26684+ SK_PNMI_RO, Monitor, 0},\r
26685+ {OID_SKGE_RLMT_MONITOR_TIMESTAMP,\r
26686+ SK_PNMI_MONITOR_ENTRIES,\r
26687+ sizeof(SK_PNMI_RLMT_MONITOR),\r
26688+ SK_PNMI_OFF(RlmtMonitor) + SK_PNMI_MON_OFF(RlmtMonitorTimestamp),\r
26689+ SK_PNMI_RO, Monitor, 0},\r
26690+ {OID_SKGE_RLMT_MONITOR_ADMIN,\r
26691+ SK_PNMI_MONITOR_ENTRIES,\r
26692+ sizeof(SK_PNMI_RLMT_MONITOR),\r
26693+ SK_PNMI_OFF(RlmtMonitor) + SK_PNMI_MON_OFF(RlmtMonitorAdmin),\r
26694+ SK_PNMI_RW, Monitor, 0},\r
26695+ {OID_SKGE_MTU,\r
26696+ 1,\r
26697+ 0,\r
26698+ SK_PNMI_MAI_OFF(MtuSize),\r
26699+ SK_PNMI_RW, MacPrivateConf, 0},\r
26700+ {OID_SKGE_VCT_GET,\r
26701+ 0,\r
26702+ 0,\r
26703+ 0,\r
26704+ SK_PNMI_RO, Vct, 0},\r
26705+ {OID_SKGE_VCT_SET,\r
26706+ 0,\r
26707+ 0,\r
26708+ 0,\r
26709+ SK_PNMI_WO, Vct, 0},\r
26710+ {OID_SKGE_VCT_STATUS,\r
26711+ 0,\r
26712+ 0,\r
26713+ 0,\r
26714+ SK_PNMI_RO, Vct, 0},\r
26715+ {OID_SKGE_VCT_CAPABILITIES,\r
26716+ 0,\r
26717+ 0,\r
26718+ 0,\r
26719+ SK_PNMI_RO, Vct, 0},\r
26720+ {OID_SKGE_BOARDLEVEL,\r
26721+ 0,\r
26722+ 0,\r
26723+ 0,\r
26724+ SK_PNMI_RO, General, 0},\r
26725+};\r
26726+\r
26727diff -ruN linux/drivers/net/sk98lin/skgepnmi.c linux-new/drivers/net/sk98lin/skgepnmi.c
26728--- linux/drivers/net/sk98lin/skgepnmi.c 2006-04-11 19:19:28.000000000 +0200
26729+++ linux-new/drivers/net/sk98lin/skgepnmi.c 2006-01-18 14:37:24.000000000 +0100
26730@@ -1,8359 +1,8351 @@
26731-/*****************************************************************************
26732- *
26733- * Name: skgepnmi.c
26734- * Project: GEnesis, PCI Gigabit Ethernet Adapter
26735- * Version: $Revision$
26736- * Date: $Date$
26737- * Purpose: Private Network Management Interface
26738- *
26739- ****************************************************************************/
26740-
26741-/******************************************************************************
26742- *
26743- * (C)Copyright 1998-2002 SysKonnect GmbH.
26744- * (C)Copyright 2002-2003 Marvell.
26745- *
26746- * This program is free software; you can redistribute it and/or modify
26747- * it under the terms of the GNU General Public License as published by
26748- * the Free Software Foundation; either version 2 of the License, or
26749- * (at your option) any later version.
26750- *
26751- * The information in this file is provided "AS IS" without warranty.
26752- *
26753- ******************************************************************************/
26754-
26755-
26756-#ifndef _lint
26757-static const char SysKonnectFileId[] =
26758- "@(#) $Id$ (C) Marvell.";
26759-#endif /* !_lint */
26760-
26761-#include "h/skdrv1st.h"
26762-#include "h/sktypes.h"
26763-#include "h/xmac_ii.h"
26764-#include "h/skdebug.h"
26765-#include "h/skqueue.h"
26766-#include "h/skgepnmi.h"
26767-#include "h/skgesirq.h"
26768-#include "h/skcsum.h"
26769-#include "h/skvpd.h"
26770-#include "h/skgehw.h"
26771-#include "h/skgeinit.h"
26772-#include "h/skdrv2nd.h"
26773-#include "h/skgepnm2.h"
26774-#ifdef SK_POWER_MGMT
26775-#include "h/skgepmgt.h"
26776-#endif
26777-/* defines *******************************************************************/
26778-
26779-#ifndef DEBUG
26780-#define PNMI_STATIC static
26781-#else /* DEBUG */
26782-#define PNMI_STATIC
26783-#endif /* DEBUG */
26784-
26785-/*
26786- * Public Function prototypes
26787- */
26788-int SkPnmiInit(SK_AC *pAC, SK_IOC IoC, int level);
26789-int SkPnmiGetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void *pBuf,
26790- unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex);
26791-int SkPnmiPreSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void *pBuf,
26792- unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex);
26793-int SkPnmiSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void *pBuf,
26794- unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex);
26795-int SkPnmiGetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf,
26796- unsigned int *pLen, SK_U32 NetIndex);
26797-int SkPnmiPreSetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf,
26798- unsigned int *pLen, SK_U32 NetIndex);
26799-int SkPnmiSetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf,
26800- unsigned int *pLen, SK_U32 NetIndex);
26801-int SkPnmiEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Param);
26802-int SkPnmiGenIoctl(SK_AC *pAC, SK_IOC IoC, void * pBuf,
26803- unsigned int * pLen, SK_U32 NetIndex);
26804-
26805-
26806-/*
26807- * Private Function prototypes
26808- */
26809-
26810-PNMI_STATIC SK_U8 CalculateLinkModeStatus(SK_AC *pAC, SK_IOC IoC, unsigned int
26811- PhysPortIndex);
26812-PNMI_STATIC SK_U8 CalculateLinkStatus(SK_AC *pAC, SK_IOC IoC, unsigned int
26813- PhysPortIndex);
26814-PNMI_STATIC void CopyMac(char *pDst, SK_MAC_ADDR *pMac);
26815-PNMI_STATIC void CopyTrapQueue(SK_AC *pAC, char *pDstBuf);
26816-PNMI_STATIC SK_U64 GetPhysStatVal(SK_AC *pAC, SK_IOC IoC,
26817- unsigned int PhysPortIndex, unsigned int StatIndex);
26818-PNMI_STATIC SK_U64 GetStatVal(SK_AC *pAC, SK_IOC IoC, unsigned int LogPortIndex,
26819- unsigned int StatIndex, SK_U32 NetIndex);
26820-PNMI_STATIC char* GetTrapEntry(SK_AC *pAC, SK_U32 TrapId, unsigned int Size);
26821-PNMI_STATIC void GetTrapQueueLen(SK_AC *pAC, unsigned int *pLen,
26822- unsigned int *pEntries);
26823-PNMI_STATIC int GetVpdKeyArr(SK_AC *pAC, SK_IOC IoC, char *pKeyArr,
26824- unsigned int KeyArrLen, unsigned int *pKeyNo);
26825-PNMI_STATIC int LookupId(SK_U32 Id);
26826-PNMI_STATIC int MacUpdate(SK_AC *pAC, SK_IOC IoC, unsigned int FirstMac,
26827- unsigned int LastMac);
26828-PNMI_STATIC int PnmiStruct(SK_AC *pAC, SK_IOC IoC, int Action, char *pBuf,
26829- unsigned int *pLen, SK_U32 NetIndex);
26830-PNMI_STATIC int PnmiVar(SK_AC *pAC, SK_IOC IoC, int Action, SK_U32 Id,
26831- char *pBuf, unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex);
26832-PNMI_STATIC void QueueRlmtNewMacTrap(SK_AC *pAC, unsigned int ActiveMac);
26833-PNMI_STATIC void QueueRlmtPortTrap(SK_AC *pAC, SK_U32 TrapId,
26834- unsigned int PortIndex);
26835-PNMI_STATIC void QueueSensorTrap(SK_AC *pAC, SK_U32 TrapId,
26836- unsigned int SensorIndex);
26837-PNMI_STATIC void QueueSimpleTrap(SK_AC *pAC, SK_U32 TrapId);
26838-PNMI_STATIC void ResetCounter(SK_AC *pAC, SK_IOC IoC, SK_U32 NetIndex);
26839-PNMI_STATIC int RlmtUpdate(SK_AC *pAC, SK_IOC IoC, SK_U32 NetIndex);
26840-PNMI_STATIC int SirqUpdate(SK_AC *pAC, SK_IOC IoC);
26841-PNMI_STATIC void VirtualConf(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, char *pBuf);
26842-PNMI_STATIC int Vct(SK_AC *pAC, SK_IOC IoC, int Action, SK_U32 Id, char *pBuf,
26843- unsigned int *pLen, SK_U32 Instance, unsigned int TableIndex, SK_U32 NetIndex);
26844-PNMI_STATIC void CheckVctStatus(SK_AC *, SK_IOC, char *, SK_U32, SK_U32);
26845-
26846-/*
26847- * Table to correlate OID with handler function and index to
26848- * hardware register stored in StatAddress if applicable.
26849- */
26850-#include "skgemib.c"
26851-
26852-/* global variables **********************************************************/
26853-
26854-/*
26855- * Overflow status register bit table and corresponding counter
26856- * dependent on MAC type - the number relates to the size of overflow
26857- * mask returned by the pFnMacOverflow function
26858- */
26859-PNMI_STATIC const SK_U16 StatOvrflwBit[][SK_PNMI_MAC_TYPES] = {
26860-/* Bit0 */ { SK_PNMI_HTX, SK_PNMI_HTX_UNICAST},
26861-/* Bit1 */ { SK_PNMI_HTX_OCTETHIGH, SK_PNMI_HTX_BROADCAST},
26862-/* Bit2 */ { SK_PNMI_HTX_OCTETLOW, SK_PNMI_HTX_PMACC},
26863-/* Bit3 */ { SK_PNMI_HTX_BROADCAST, SK_PNMI_HTX_MULTICAST},
26864-/* Bit4 */ { SK_PNMI_HTX_MULTICAST, SK_PNMI_HTX_OCTETLOW},
26865-/* Bit5 */ { SK_PNMI_HTX_UNICAST, SK_PNMI_HTX_OCTETHIGH},
26866-/* Bit6 */ { SK_PNMI_HTX_LONGFRAMES, SK_PNMI_HTX_64},
26867-/* Bit7 */ { SK_PNMI_HTX_BURST, SK_PNMI_HTX_127},
26868-/* Bit8 */ { SK_PNMI_HTX_PMACC, SK_PNMI_HTX_255},
26869-/* Bit9 */ { SK_PNMI_HTX_MACC, SK_PNMI_HTX_511},
26870-/* Bit10 */ { SK_PNMI_HTX_SINGLE_COL, SK_PNMI_HTX_1023},
26871-/* Bit11 */ { SK_PNMI_HTX_MULTI_COL, SK_PNMI_HTX_MAX},
26872-/* Bit12 */ { SK_PNMI_HTX_EXCESS_COL, SK_PNMI_HTX_LONGFRAMES},
26873-/* Bit13 */ { SK_PNMI_HTX_LATE_COL, SK_PNMI_HTX_RESERVED},
26874-/* Bit14 */ { SK_PNMI_HTX_DEFFERAL, SK_PNMI_HTX_COL},
26875-/* Bit15 */ { SK_PNMI_HTX_EXCESS_DEF, SK_PNMI_HTX_LATE_COL},
26876-/* Bit16 */ { SK_PNMI_HTX_UNDERRUN, SK_PNMI_HTX_EXCESS_COL},
26877-/* Bit17 */ { SK_PNMI_HTX_CARRIER, SK_PNMI_HTX_MULTI_COL},
26878-/* Bit18 */ { SK_PNMI_HTX_UTILUNDER, SK_PNMI_HTX_SINGLE_COL},
26879-/* Bit19 */ { SK_PNMI_HTX_UTILOVER, SK_PNMI_HTX_UNDERRUN},
26880-/* Bit20 */ { SK_PNMI_HTX_64, SK_PNMI_HTX_RESERVED},
26881-/* Bit21 */ { SK_PNMI_HTX_127, SK_PNMI_HTX_RESERVED},
26882-/* Bit22 */ { SK_PNMI_HTX_255, SK_PNMI_HTX_RESERVED},
26883-/* Bit23 */ { SK_PNMI_HTX_511, SK_PNMI_HTX_RESERVED},
26884-/* Bit24 */ { SK_PNMI_HTX_1023, SK_PNMI_HTX_RESERVED},
26885-/* Bit25 */ { SK_PNMI_HTX_MAX, SK_PNMI_HTX_RESERVED},
26886-/* Bit26 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED},
26887-/* Bit27 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED},
26888-/* Bit28 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED},
26889-/* Bit29 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED},
26890-/* Bit30 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED},
26891-/* Bit31 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED},
26892-/* Bit32 */ { SK_PNMI_HRX, SK_PNMI_HRX_UNICAST},
26893-/* Bit33 */ { SK_PNMI_HRX_OCTETHIGH, SK_PNMI_HRX_BROADCAST},
26894-/* Bit34 */ { SK_PNMI_HRX_OCTETLOW, SK_PNMI_HRX_PMACC},
26895-/* Bit35 */ { SK_PNMI_HRX_BROADCAST, SK_PNMI_HRX_MULTICAST},
26896-/* Bit36 */ { SK_PNMI_HRX_MULTICAST, SK_PNMI_HRX_FCS},
26897-/* Bit37 */ { SK_PNMI_HRX_UNICAST, SK_PNMI_HRX_RESERVED},
26898-/* Bit38 */ { SK_PNMI_HRX_PMACC, SK_PNMI_HRX_OCTETLOW},
26899-/* Bit39 */ { SK_PNMI_HRX_MACC, SK_PNMI_HRX_OCTETHIGH},
26900-/* Bit40 */ { SK_PNMI_HRX_PMACC_ERR, SK_PNMI_HRX_BADOCTETLOW},
26901-/* Bit41 */ { SK_PNMI_HRX_MACC_UNKWN, SK_PNMI_HRX_BADOCTETHIGH},
26902-/* Bit42 */ { SK_PNMI_HRX_BURST, SK_PNMI_HRX_UNDERSIZE},
26903-/* Bit43 */ { SK_PNMI_HRX_MISSED, SK_PNMI_HRX_RUNT},
26904-/* Bit44 */ { SK_PNMI_HRX_FRAMING, SK_PNMI_HRX_64},
26905-/* Bit45 */ { SK_PNMI_HRX_OVERFLOW, SK_PNMI_HRX_127},
26906-/* Bit46 */ { SK_PNMI_HRX_JABBER, SK_PNMI_HRX_255},
26907-/* Bit47 */ { SK_PNMI_HRX_CARRIER, SK_PNMI_HRX_511},
26908-/* Bit48 */ { SK_PNMI_HRX_IRLENGTH, SK_PNMI_HRX_1023},
26909-/* Bit49 */ { SK_PNMI_HRX_SYMBOL, SK_PNMI_HRX_MAX},
26910-/* Bit50 */ { SK_PNMI_HRX_SHORTS, SK_PNMI_HRX_LONGFRAMES},
26911-/* Bit51 */ { SK_PNMI_HRX_RUNT, SK_PNMI_HRX_TOO_LONG},
26912-/* Bit52 */ { SK_PNMI_HRX_TOO_LONG, SK_PNMI_HRX_JABBER},
26913-/* Bit53 */ { SK_PNMI_HRX_FCS, SK_PNMI_HRX_RESERVED},
26914-/* Bit54 */ { SK_PNMI_HRX_RESERVED, SK_PNMI_HRX_OVERFLOW},
26915-/* Bit55 */ { SK_PNMI_HRX_CEXT, SK_PNMI_HRX_RESERVED},
26916-/* Bit56 */ { SK_PNMI_HRX_UTILUNDER, SK_PNMI_HRX_RESERVED},
26917-/* Bit57 */ { SK_PNMI_HRX_UTILOVER, SK_PNMI_HRX_RESERVED},
26918-/* Bit58 */ { SK_PNMI_HRX_64, SK_PNMI_HRX_RESERVED},
26919-/* Bit59 */ { SK_PNMI_HRX_127, SK_PNMI_HRX_RESERVED},
26920-/* Bit60 */ { SK_PNMI_HRX_255, SK_PNMI_HRX_RESERVED},
26921-/* Bit61 */ { SK_PNMI_HRX_511, SK_PNMI_HRX_RESERVED},
26922-/* Bit62 */ { SK_PNMI_HRX_1023, SK_PNMI_HRX_RESERVED},
26923-/* Bit63 */ { SK_PNMI_HRX_MAX, SK_PNMI_HRX_RESERVED}
26924-};
26925-
26926-/*
26927- * Table for hardware register saving on resets and port switches
26928- */
26929-PNMI_STATIC const SK_PNMI_STATADDR StatAddr[SK_PNMI_MAX_IDX][SK_PNMI_MAC_TYPES] = {
26930- /* SK_PNMI_HTX */
26931- {{XM_TXF_OK, SK_TRUE}, {0, SK_FALSE}},
26932- /* SK_PNMI_HTX_OCTETHIGH */
26933- {{XM_TXO_OK_HI, SK_TRUE}, {GM_TXO_OK_HI, SK_TRUE}},
26934- /* SK_PNMI_HTX_OCTETLOW */
26935- {{XM_TXO_OK_LO, SK_FALSE}, {GM_TXO_OK_LO, SK_FALSE}},
26936- /* SK_PNMI_HTX_BROADCAST */
26937- {{XM_TXF_BC_OK, SK_TRUE}, {GM_TXF_BC_OK, SK_TRUE}},
26938- /* SK_PNMI_HTX_MULTICAST */
26939- {{XM_TXF_MC_OK, SK_TRUE}, {GM_TXF_MC_OK, SK_TRUE}},
26940- /* SK_PNMI_HTX_UNICAST */
26941- {{XM_TXF_UC_OK, SK_TRUE}, {GM_TXF_UC_OK, SK_TRUE}},
26942- /* SK_PNMI_HTX_BURST */
26943- {{XM_TXE_BURST, SK_TRUE}, {0, SK_FALSE}},
26944- /* SK_PNMI_HTX_PMACC */
26945- {{XM_TXF_MPAUSE, SK_TRUE}, {GM_TXF_MPAUSE, SK_TRUE}},
26946- /* SK_PNMI_HTX_MACC */
26947- {{XM_TXF_MCTRL, SK_TRUE}, {0, SK_FALSE}},
26948- /* SK_PNMI_HTX_COL */
26949- {{0, SK_FALSE}, {GM_TXF_COL, SK_TRUE}},
26950- /* SK_PNMI_HTX_SINGLE_COL */
26951- {{XM_TXF_SNG_COL, SK_TRUE}, {GM_TXF_SNG_COL, SK_TRUE}},
26952- /* SK_PNMI_HTX_MULTI_COL */
26953- {{XM_TXF_MUL_COL, SK_TRUE}, {GM_TXF_MUL_COL, SK_TRUE}},
26954- /* SK_PNMI_HTX_EXCESS_COL */
26955- {{XM_TXF_ABO_COL, SK_TRUE}, {GM_TXF_ABO_COL, SK_TRUE}},
26956- /* SK_PNMI_HTX_LATE_COL */
26957- {{XM_TXF_LAT_COL, SK_TRUE}, {GM_TXF_LAT_COL, SK_TRUE}},
26958- /* SK_PNMI_HTX_DEFFERAL */
26959- {{XM_TXF_DEF, SK_TRUE}, {0, SK_FALSE}},
26960- /* SK_PNMI_HTX_EXCESS_DEF */
26961- {{XM_TXF_EX_DEF, SK_TRUE}, {0, SK_FALSE}},
26962- /* SK_PNMI_HTX_UNDERRUN */
26963- {{XM_TXE_FIFO_UR, SK_TRUE}, {GM_TXE_FIFO_UR, SK_TRUE}},
26964- /* SK_PNMI_HTX_CARRIER */
26965- {{XM_TXE_CS_ERR, SK_TRUE}, {0, SK_FALSE}},
26966- /* SK_PNMI_HTX_UTILUNDER */
26967- {{0, SK_FALSE}, {0, SK_FALSE}},
26968- /* SK_PNMI_HTX_UTILOVER */
26969- {{0, SK_FALSE}, {0, SK_FALSE}},
26970- /* SK_PNMI_HTX_64 */
26971- {{XM_TXF_64B, SK_TRUE}, {GM_TXF_64B, SK_TRUE}},
26972- /* SK_PNMI_HTX_127 */
26973- {{XM_TXF_127B, SK_TRUE}, {GM_TXF_127B, SK_TRUE}},
26974- /* SK_PNMI_HTX_255 */
26975- {{XM_TXF_255B, SK_TRUE}, {GM_TXF_255B, SK_TRUE}},
26976- /* SK_PNMI_HTX_511 */
26977- {{XM_TXF_511B, SK_TRUE}, {GM_TXF_511B, SK_TRUE}},
26978- /* SK_PNMI_HTX_1023 */
26979- {{XM_TXF_1023B, SK_TRUE}, {GM_TXF_1023B, SK_TRUE}},
26980- /* SK_PNMI_HTX_MAX */
26981- {{XM_TXF_MAX_SZ, SK_TRUE}, {GM_TXF_1518B, SK_TRUE}},
26982- /* SK_PNMI_HTX_LONGFRAMES */
26983- {{XM_TXF_LONG, SK_TRUE}, {GM_TXF_MAX_SZ, SK_TRUE}},
26984- /* SK_PNMI_HTX_SYNC */
26985- {{0, SK_FALSE}, {0, SK_FALSE}},
26986- /* SK_PNMI_HTX_SYNC_OCTET */
26987- {{0, SK_FALSE}, {0, SK_FALSE}},
26988- /* SK_PNMI_HTX_RESERVED */
26989- {{0, SK_FALSE}, {0, SK_FALSE}},
26990- /* SK_PNMI_HRX */
26991- {{XM_RXF_OK, SK_TRUE}, {0, SK_FALSE}},
26992- /* SK_PNMI_HRX_OCTETHIGH */
26993- {{XM_RXO_OK_HI, SK_TRUE}, {GM_RXO_OK_HI, SK_TRUE}},
26994- /* SK_PNMI_HRX_OCTETLOW */
26995- {{XM_RXO_OK_LO, SK_FALSE}, {GM_RXO_OK_LO, SK_FALSE}},
26996- /* SK_PNMI_HRX_BADOCTETHIGH */
26997- {{0, SK_FALSE}, {GM_RXO_ERR_HI, SK_TRUE}},
26998- /* SK_PNMI_HRX_BADOCTETLOW */
26999- {{0, SK_FALSE}, {GM_RXO_ERR_LO, SK_TRUE}},
27000- /* SK_PNMI_HRX_BROADCAST */
27001- {{XM_RXF_BC_OK, SK_TRUE}, {GM_RXF_BC_OK, SK_TRUE}},
27002- /* SK_PNMI_HRX_MULTICAST */
27003- {{XM_RXF_MC_OK, SK_TRUE}, {GM_RXF_MC_OK, SK_TRUE}},
27004- /* SK_PNMI_HRX_UNICAST */
27005- {{XM_RXF_UC_OK, SK_TRUE}, {GM_RXF_UC_OK, SK_TRUE}},
27006- /* SK_PNMI_HRX_PMACC */
27007- {{XM_RXF_MPAUSE, SK_TRUE}, {GM_RXF_MPAUSE, SK_TRUE}},
27008- /* SK_PNMI_HRX_MACC */
27009- {{XM_RXF_MCTRL, SK_TRUE}, {0, SK_FALSE}},
27010- /* SK_PNMI_HRX_PMACC_ERR */
27011- {{XM_RXF_INV_MP, SK_TRUE}, {0, SK_FALSE}},
27012- /* SK_PNMI_HRX_MACC_UNKWN */
27013- {{XM_RXF_INV_MOC, SK_TRUE}, {0, SK_FALSE}},
27014- /* SK_PNMI_HRX_BURST */
27015- {{XM_RXE_BURST, SK_TRUE}, {0, SK_FALSE}},
27016- /* SK_PNMI_HRX_MISSED */
27017- {{XM_RXE_FMISS, SK_TRUE}, {0, SK_FALSE}},
27018- /* SK_PNMI_HRX_FRAMING */
27019- {{XM_RXF_FRA_ERR, SK_TRUE}, {0, SK_FALSE}},
27020- /* SK_PNMI_HRX_UNDERSIZE */
27021- {{0, SK_FALSE}, {GM_RXF_SHT, SK_TRUE}},
27022- /* SK_PNMI_HRX_OVERFLOW */
27023- {{XM_RXE_FIFO_OV, SK_TRUE}, {GM_RXE_FIFO_OV, SK_TRUE}},
27024- /* SK_PNMI_HRX_JABBER */
27025- {{XM_RXF_JAB_PKT, SK_TRUE}, {GM_RXF_JAB_PKT, SK_TRUE}},
27026- /* SK_PNMI_HRX_CARRIER */
27027- {{XM_RXE_CAR_ERR, SK_TRUE}, {0, SK_FALSE}},
27028- /* SK_PNMI_HRX_IRLENGTH */
27029- {{XM_RXF_LEN_ERR, SK_TRUE}, {0, SK_FALSE}},
27030- /* SK_PNMI_HRX_SYMBOL */
27031- {{XM_RXE_SYM_ERR, SK_TRUE}, {0, SK_FALSE}},
27032- /* SK_PNMI_HRX_SHORTS */
27033- {{XM_RXE_SHT_ERR, SK_TRUE}, {0, SK_FALSE}},
27034- /* SK_PNMI_HRX_RUNT */
27035- {{XM_RXE_RUNT, SK_TRUE}, {GM_RXE_FRAG, SK_TRUE}},
27036- /* SK_PNMI_HRX_TOO_LONG */
27037- {{XM_RXF_LNG_ERR, SK_TRUE}, {GM_RXF_LNG_ERR, SK_TRUE}},
27038- /* SK_PNMI_HRX_FCS */
27039- {{XM_RXF_FCS_ERR, SK_TRUE}, {GM_RXF_FCS_ERR, SK_TRUE}},
27040- /* SK_PNMI_HRX_CEXT */
27041- {{XM_RXF_CEX_ERR, SK_TRUE}, {0, SK_FALSE}},
27042- /* SK_PNMI_HRX_UTILUNDER */
27043- {{0, SK_FALSE}, {0, SK_FALSE}},
27044- /* SK_PNMI_HRX_UTILOVER */
27045- {{0, SK_FALSE}, {0, SK_FALSE}},
27046- /* SK_PNMI_HRX_64 */
27047- {{XM_RXF_64B, SK_TRUE}, {GM_RXF_64B, SK_TRUE}},
27048- /* SK_PNMI_HRX_127 */
27049- {{XM_RXF_127B, SK_TRUE}, {GM_RXF_127B, SK_TRUE}},
27050- /* SK_PNMI_HRX_255 */
27051- {{XM_RXF_255B, SK_TRUE}, {GM_RXF_255B, SK_TRUE}},
27052- /* SK_PNMI_HRX_511 */
27053- {{XM_RXF_511B, SK_TRUE}, {GM_RXF_511B, SK_TRUE}},
27054- /* SK_PNMI_HRX_1023 */
27055- {{XM_RXF_1023B, SK_TRUE}, {GM_RXF_1023B, SK_TRUE}},
27056- /* SK_PNMI_HRX_MAX */
27057- {{XM_RXF_MAX_SZ, SK_TRUE}, {GM_RXF_1518B, SK_TRUE}},
27058- /* SK_PNMI_HRX_LONGFRAMES */
27059- {{0, SK_FALSE}, {GM_RXF_MAX_SZ, SK_TRUE}},
27060- /* SK_PNMI_HRX_RESERVED */
27061- {{0, SK_FALSE}, {0, SK_FALSE}}
27062-};
27063-
27064-
27065-/*****************************************************************************
27066- *
27067- * Public functions
27068- *
27069- */
27070-
27071-/*****************************************************************************
27072- *
27073- * SkPnmiInit - Init function of PNMI
27074- *
27075- * Description:
27076- * SK_INIT_DATA: Initialises the data structures
27077- * SK_INIT_IO: Resets the XMAC statistics, determines the device and
27078- * connector type.
27079- * SK_INIT_RUN: Starts a timer event for port switch per hour
27080- * calculation.
27081- *
27082- * Returns:
27083- * Always 0
27084- */
27085-int SkPnmiInit(
27086-SK_AC *pAC, /* Pointer to adapter context */
27087-SK_IOC IoC, /* IO context handle */
27088-int Level) /* Initialization level */
27089-{
27090- unsigned int PortMax; /* Number of ports */
27091- unsigned int PortIndex; /* Current port index in loop */
27092- SK_U16 Val16; /* Multiple purpose 16 bit variable */
27093- SK_U8 Val8; /* Mulitple purpose 8 bit variable */
27094- SK_EVPARA EventParam; /* Event struct for timer event */
27095- SK_PNMI_VCT *pVctBackupData;
27096-
27097-
27098- SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
27099- ("PNMI: SkPnmiInit: Called, level=%d\n", Level));
27100-
27101- switch (Level) {
27102-
27103- case SK_INIT_DATA:
27104- SK_MEMSET((char *)&pAC->Pnmi, 0, sizeof(pAC->Pnmi));
27105- pAC->Pnmi.TrapBufFree = SK_PNMI_TRAP_QUEUE_LEN;
27106- pAC->Pnmi.StartUpTime = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC));
27107- pAC->Pnmi.RlmtChangeThreshold = SK_PNMI_DEF_RLMT_CHG_THRES;
27108- for (PortIndex = 0; PortIndex < SK_MAX_MACS; PortIndex ++) {
27109-
27110- pAC->Pnmi.Port[PortIndex].ActiveFlag = SK_FALSE;
27111- pAC->Pnmi.DualNetActiveFlag = SK_FALSE;
27112- }
27113-
27114-#ifdef SK_PNMI_CHECK
27115- if (SK_PNMI_MAX_IDX != SK_PNMI_CNT_NO) {
27116-
27117- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR049, SK_PNMI_ERR049MSG);
27118-
27119- SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_INIT | SK_DBGCAT_FATAL,
27120- ("CounterOffset struct size (%d) differs from"
27121- "SK_PNMI_MAX_IDX (%d)\n",
27122- SK_PNMI_CNT_NO, SK_PNMI_MAX_IDX));
27123- }
27124-
27125- if (SK_PNMI_MAX_IDX !=
27126- (sizeof(StatAddr) / (sizeof(SK_PNMI_STATADDR) * SK_PNMI_MAC_TYPES))) {
27127-
27128- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR050, SK_PNMI_ERR050MSG);
27129-
27130- SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_INIT | SK_DBGCAT_FATAL,
27131- ("StatAddr table size (%d) differs from "
27132- "SK_PNMI_MAX_IDX (%d)\n",
27133- (sizeof(StatAddr) /
27134- (sizeof(SK_PNMI_STATADDR) * SK_PNMI_MAC_TYPES)),
27135- SK_PNMI_MAX_IDX));
27136- }
27137-#endif /* SK_PNMI_CHECK */
27138- break;
27139-
27140- case SK_INIT_IO:
27141- /*
27142- * Reset MAC counters
27143- */
27144- PortMax = pAC->GIni.GIMacsFound;
27145-
27146- for (PortIndex = 0; PortIndex < PortMax; PortIndex ++) {
27147-
27148- pAC->GIni.GIFunc.pFnMacResetCounter(pAC, IoC, PortIndex);
27149- }
27150-
27151- /* Initialize DSP variables for Vct() to 0xff => Never written! */
27152- for (PortIndex = 0; PortIndex < PortMax; PortIndex ++) {
27153- pAC->GIni.GP[PortIndex].PCableLen = 0xff;
27154- pVctBackupData = &pAC->Pnmi.VctBackup[PortIndex];
27155- pVctBackupData->PCableLen = 0xff;
27156- }
27157-
27158- /*
27159- * Get pci bus speed
27160- */
27161- SK_IN16(IoC, B0_CTST, &Val16);
27162- if ((Val16 & CS_BUS_CLOCK) == 0) {
27163-
27164- pAC->Pnmi.PciBusSpeed = 33;
27165- }
27166- else {
27167- pAC->Pnmi.PciBusSpeed = 66;
27168- }
27169-
27170- /*
27171- * Get pci bus width
27172- */
27173- SK_IN16(IoC, B0_CTST, &Val16);
27174- if ((Val16 & CS_BUS_SLOT_SZ) == 0) {
27175-
27176- pAC->Pnmi.PciBusWidth = 32;
27177- }
27178- else {
27179- pAC->Pnmi.PciBusWidth = 64;
27180- }
27181-
27182- /*
27183- * Get chipset
27184- */
27185- switch (pAC->GIni.GIChipId) {
27186- case CHIP_ID_GENESIS:
27187- pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_XMAC;
27188- break;
27189-
27190- case CHIP_ID_YUKON:
27191- pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON;
27192- break;
27193-
27194- default:
27195- break;
27196- }
27197-
27198- /*
27199- * Get PMD and DeviceType
27200- */
27201- SK_IN8(IoC, B2_PMD_TYP, &Val8);
27202- switch (Val8) {
27203- case 'S':
27204- pAC->Pnmi.PMD = 3;
27205- if (pAC->GIni.GIMacsFound > 1) {
27206-
27207- pAC->Pnmi.DeviceType = 0x00020002;
27208- }
27209- else {
27210- pAC->Pnmi.DeviceType = 0x00020001;
27211- }
27212- break;
27213-
27214- case 'L':
27215- pAC->Pnmi.PMD = 2;
27216- if (pAC->GIni.GIMacsFound > 1) {
27217-
27218- pAC->Pnmi.DeviceType = 0x00020004;
27219- }
27220- else {
27221- pAC->Pnmi.DeviceType = 0x00020003;
27222- }
27223- break;
27224-
27225- case 'C':
27226- pAC->Pnmi.PMD = 4;
27227- if (pAC->GIni.GIMacsFound > 1) {
27228-
27229- pAC->Pnmi.DeviceType = 0x00020006;
27230- }
27231- else {
27232- pAC->Pnmi.DeviceType = 0x00020005;
27233- }
27234- break;
27235-
27236- case 'T':
27237- pAC->Pnmi.PMD = 5;
27238- if (pAC->GIni.GIMacsFound > 1) {
27239-
27240- pAC->Pnmi.DeviceType = 0x00020008;
27241- }
27242- else {
27243- pAC->Pnmi.DeviceType = 0x00020007;
27244- }
27245- break;
27246-
27247- default :
27248- pAC->Pnmi.PMD = 1;
27249- pAC->Pnmi.DeviceType = 0;
27250- break;
27251- }
27252-
27253- /*
27254- * Get connector
27255- */
27256- SK_IN8(IoC, B2_CONN_TYP, &Val8);
27257- switch (Val8) {
27258- case 'C':
27259- pAC->Pnmi.Connector = 2;
27260- break;
27261-
27262- case 'D':
27263- pAC->Pnmi.Connector = 3;
27264- break;
27265-
27266- case 'F':
27267- pAC->Pnmi.Connector = 4;
27268- break;
27269-
27270- case 'J':
27271- pAC->Pnmi.Connector = 5;
27272- break;
27273-
27274- case 'V':
27275- pAC->Pnmi.Connector = 6;
27276- break;
27277-
27278- default:
27279- pAC->Pnmi.Connector = 1;
27280- break;
27281- }
27282- break;
27283-
27284- case SK_INIT_RUN:
27285- /*
27286- * Start timer for RLMT change counter
27287- */
27288- SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
27289- SkTimerStart(pAC, IoC, &pAC->Pnmi.RlmtChangeEstimate.EstTimer,
27290- 28125000, SKGE_PNMI, SK_PNMI_EVT_CHG_EST_TIMER,
27291- EventParam);
27292- break;
27293-
27294- default:
27295- break; /* Nothing todo */
27296- }
27297-
27298- return (0);
27299-}
27300-
27301-/*****************************************************************************
27302- *
27303- * SkPnmiGetVar - Retrieves the value of a single OID
27304- *
27305- * Description:
27306- * Calls a general sub-function for all this stuff. If the instance
27307- * -1 is passed, the values of all instances are returned in an
27308- * array of values.
27309- *
27310- * Returns:
27311- * SK_PNMI_ERR_OK The request was successfully performed
27312- * SK_PNMI_ERR_GENERAL A general severe internal error occured
27313- * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to take
27314- * the data.
27315- * SK_PNMI_ERR_UNKNOWN_OID The requested OID is unknown
27316- * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
27317- * exist (e.g. port instance 3 on a two port
27318- * adapter.
27319- */
27320-int SkPnmiGetVar(
27321-SK_AC *pAC, /* Pointer to adapter context */
27322-SK_IOC IoC, /* IO context handle */
27323-SK_U32 Id, /* Object ID that is to be processed */
27324-void *pBuf, /* Buffer to which the management data will be copied */
27325-unsigned int *pLen, /* On call: buffer length. On return: used buffer */
27326-SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
27327-SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */
27328-{
27329- SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
27330- ("PNMI: SkPnmiGetVar: Called, Id=0x%x, BufLen=%d, Instance=%d, NetIndex=%d\n",
27331- Id, *pLen, Instance, NetIndex));
27332-
27333- return (PnmiVar(pAC, IoC, SK_PNMI_GET, Id, (char *)pBuf, pLen,
27334- Instance, NetIndex));
27335-}
27336-
27337-/*****************************************************************************
27338- *
27339- * SkPnmiPreSetVar - Presets the value of a single OID
27340- *
27341- * Description:
27342- * Calls a general sub-function for all this stuff. The preset does
27343- * the same as a set, but returns just before finally setting the
27344- * new value. This is useful to check if a set might be successfull.
27345- * If the instance -1 is passed, an array of values is supposed and
27346- * all instances of the OID will be set.
27347- *
27348- * Returns:
27349- * SK_PNMI_ERR_OK The request was successfully performed.
27350- * SK_PNMI_ERR_GENERAL A general severe internal error occured.
27351- * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
27352- * the correct data (e.g. a 32bit value is
27353- * needed, but a 16 bit value was passed).
27354- * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid
27355- * value range.
27356- * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set.
27357- * SK_PNMI_ERR_UNKNOWN_OID The requested OID is unknown.
27358- * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
27359- * exist (e.g. port instance 3 on a two port
27360- * adapter.
27361- */
27362-int SkPnmiPreSetVar(
27363-SK_AC *pAC, /* Pointer to adapter context */
27364-SK_IOC IoC, /* IO context handle */
27365-SK_U32 Id, /* Object ID that is to be processed */
27366-void *pBuf, /* Buffer to which the management data will be copied */
27367-unsigned int *pLen, /* Total length of management data */
27368-SK_U32 Instance, /* Instance (1..n) that is to be set or -1 */
27369-SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */
27370-{
27371- SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
27372- ("PNMI: SkPnmiPreSetVar: Called, Id=0x%x, BufLen=%d, Instance=%d, NetIndex=%d\n",
27373- Id, *pLen, Instance, NetIndex));
27374-
27375-
27376- return (PnmiVar(pAC, IoC, SK_PNMI_PRESET, Id, (char *)pBuf, pLen,
27377- Instance, NetIndex));
27378-}
27379-
27380-/*****************************************************************************
27381- *
27382- * SkPnmiSetVar - Sets the value of a single OID
27383- *
27384- * Description:
27385- * Calls a general sub-function for all this stuff. The preset does
27386- * the same as a set, but returns just before finally setting the
27387- * new value. This is useful to check if a set might be successfull.
27388- * If the instance -1 is passed, an array of values is supposed and
27389- * all instances of the OID will be set.
27390- *
27391- * Returns:
27392- * SK_PNMI_ERR_OK The request was successfully performed.
27393- * SK_PNMI_ERR_GENERAL A general severe internal error occured.
27394- * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
27395- * the correct data (e.g. a 32bit value is
27396- * needed, but a 16 bit value was passed).
27397- * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid
27398- * value range.
27399- * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set.
27400- * SK_PNMI_ERR_UNKNOWN_OID The requested OID is unknown.
27401- * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
27402- * exist (e.g. port instance 3 on a two port
27403- * adapter.
27404- */
27405-int SkPnmiSetVar(
27406-SK_AC *pAC, /* Pointer to adapter context */
27407-SK_IOC IoC, /* IO context handle */
27408-SK_U32 Id, /* Object ID that is to be processed */
27409-void *pBuf, /* Buffer to which the management data will be copied */
27410-unsigned int *pLen, /* Total length of management data */
27411-SK_U32 Instance, /* Instance (1..n) that is to be set or -1 */
27412-SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */
27413-{
27414- SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
27415- ("PNMI: SkPnmiSetVar: Called, Id=0x%x, BufLen=%d, Instance=%d, NetIndex=%d\n",
27416- Id, *pLen, Instance, NetIndex));
27417-
27418- return (PnmiVar(pAC, IoC, SK_PNMI_SET, Id, (char *)pBuf, pLen,
27419- Instance, NetIndex));
27420-}
27421-
27422-/*****************************************************************************
27423- *
27424- * SkPnmiGetStruct - Retrieves the management database in SK_PNMI_STRUCT_DATA
27425- *
27426- * Description:
27427- * Runs through the IdTable, queries the single OIDs and stores the
27428- * returned data into the management database structure
27429- * SK_PNMI_STRUCT_DATA. The offset of the OID in the structure
27430- * is stored in the IdTable. The return value of the function will also
27431- * be stored in SK_PNMI_STRUCT_DATA if the passed buffer has the
27432- * minimum size of SK_PNMI_MIN_STRUCT_SIZE.
27433- *
27434- * Returns:
27435- * SK_PNMI_ERR_OK The request was successfully performed
27436- * SK_PNMI_ERR_GENERAL A general severe internal error occured
27437- * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to take
27438- * the data.
27439- * SK_PNMI_ERR_UNKNOWN_NET The requested NetIndex doesn't exist
27440- */
27441-int SkPnmiGetStruct(
27442-SK_AC *pAC, /* Pointer to adapter context */
27443-SK_IOC IoC, /* IO context handle */
27444-void *pBuf, /* Buffer to which the management data will be copied. */
27445-unsigned int *pLen, /* Length of buffer */
27446-SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */
27447-{
27448- int Ret;
27449- unsigned int TableIndex;
27450- unsigned int DstOffset;
27451- unsigned int InstanceNo;
27452- unsigned int InstanceCnt;
27453- SK_U32 Instance;
27454- unsigned int TmpLen;
27455- char KeyArr[SK_PNMI_VPD_ENTRIES][SK_PNMI_VPD_KEY_SIZE];
27456-
27457-
27458- SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
27459- ("PNMI: SkPnmiGetStruct: Called, BufLen=%d, NetIndex=%d\n",
27460- *pLen, NetIndex));
27461-
27462- if (*pLen < SK_PNMI_STRUCT_SIZE) {
27463-
27464- if (*pLen >= SK_PNMI_MIN_STRUCT_SIZE) {
27465-
27466- SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_TOO_SHORT,
27467- (SK_U32)(-1));
27468- }
27469-
27470- *pLen = SK_PNMI_STRUCT_SIZE;
27471- return (SK_PNMI_ERR_TOO_SHORT);
27472- }
27473-
27474- /*
27475- * Check NetIndex
27476- */
27477- if (NetIndex >= pAC->Rlmt.NumNets) {
27478- return (SK_PNMI_ERR_UNKNOWN_NET);
27479- }
27480-
27481- /* Update statistic */
27482- SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On call");
27483-
27484- if ((Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1)) !=
27485- SK_PNMI_ERR_OK) {
27486-
27487- SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1));
27488- *pLen = SK_PNMI_MIN_STRUCT_SIZE;
27489- return (Ret);
27490- }
27491-
27492- if ((Ret = RlmtUpdate(pAC, IoC, NetIndex)) != SK_PNMI_ERR_OK) {
27493-
27494- SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1));
27495- *pLen = SK_PNMI_MIN_STRUCT_SIZE;
27496- return (Ret);
27497- }
27498-
27499- if ((Ret = SirqUpdate(pAC, IoC)) != SK_PNMI_ERR_OK) {
27500-
27501- SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1));
27502- *pLen = SK_PNMI_MIN_STRUCT_SIZE;
27503- return (Ret);
27504- }
27505-
27506- /*
27507- * Increment semaphores to indicate that an update was
27508- * already done
27509- */
27510- pAC->Pnmi.MacUpdatedFlag ++;
27511- pAC->Pnmi.RlmtUpdatedFlag ++;
27512- pAC->Pnmi.SirqUpdatedFlag ++;
27513-
27514- /* Get vpd keys for instance calculation */
27515- Ret = GetVpdKeyArr(pAC, IoC, &KeyArr[0][0], sizeof(KeyArr), &TmpLen);
27516- if (Ret != SK_PNMI_ERR_OK) {
27517-
27518- pAC->Pnmi.MacUpdatedFlag --;
27519- pAC->Pnmi.RlmtUpdatedFlag --;
27520- pAC->Pnmi.SirqUpdatedFlag --;
27521-
27522- SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On return");
27523- SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1));
27524- *pLen = SK_PNMI_MIN_STRUCT_SIZE;
27525- return (SK_PNMI_ERR_GENERAL);
27526- }
27527-
27528- /* Retrieve values */
27529- SK_MEMSET((char *)pBuf, 0, SK_PNMI_STRUCT_SIZE);
27530- for (TableIndex = 0; TableIndex < ID_TABLE_SIZE; TableIndex ++) {
27531-
27532- InstanceNo = IdTable[TableIndex].InstanceNo;
27533- for (InstanceCnt = 1; InstanceCnt <= InstanceNo;
27534- InstanceCnt ++) {
27535-
27536- DstOffset = IdTable[TableIndex].Offset +
27537- (InstanceCnt - 1) *
27538- IdTable[TableIndex].StructSize;
27539-
27540- /*
27541- * For the VPD the instance is not an index number
27542- * but the key itself. Determin with the instance
27543- * counter the VPD key to be used.
27544- */
27545- if (IdTable[TableIndex].Id == OID_SKGE_VPD_KEY ||
27546- IdTable[TableIndex].Id == OID_SKGE_VPD_VALUE ||
27547- IdTable[TableIndex].Id == OID_SKGE_VPD_ACCESS ||
27548- IdTable[TableIndex].Id == OID_SKGE_VPD_ACTION) {
27549-
27550- SK_STRNCPY((char *)&Instance, KeyArr[InstanceCnt - 1], 4);
27551- }
27552- else {
27553- Instance = (SK_U32)InstanceCnt;
27554- }
27555-
27556- TmpLen = *pLen - DstOffset;
27557- Ret = IdTable[TableIndex].Func(pAC, IoC, SK_PNMI_GET,
27558- IdTable[TableIndex].Id, (char *)pBuf +
27559- DstOffset, &TmpLen, Instance, TableIndex, NetIndex);
27560-
27561- /*
27562- * An unknown instance error means that we reached
27563- * the last instance of that variable. Proceed with
27564- * the next OID in the table and ignore the return
27565- * code.
27566- */
27567- if (Ret == SK_PNMI_ERR_UNKNOWN_INST) {
27568-
27569- break;
27570- }
27571-
27572- if (Ret != SK_PNMI_ERR_OK) {
27573-
27574- pAC->Pnmi.MacUpdatedFlag --;
27575- pAC->Pnmi.RlmtUpdatedFlag --;
27576- pAC->Pnmi.SirqUpdatedFlag --;
27577-
27578- SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On return");
27579- SK_PNMI_SET_STAT(pBuf, Ret, DstOffset);
27580- *pLen = SK_PNMI_MIN_STRUCT_SIZE;
27581- return (Ret);
27582- }
27583- }
27584- }
27585-
27586- pAC->Pnmi.MacUpdatedFlag --;
27587- pAC->Pnmi.RlmtUpdatedFlag --;
27588- pAC->Pnmi.SirqUpdatedFlag --;
27589-
27590- *pLen = SK_PNMI_STRUCT_SIZE;
27591- SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On return");
27592- SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_OK, (SK_U32)(-1));
27593- return (SK_PNMI_ERR_OK);
27594-}
27595-
27596-/*****************************************************************************
27597- *
27598- * SkPnmiPreSetStruct - Presets the management database in SK_PNMI_STRUCT_DATA
27599- *
27600- * Description:
27601- * Calls a general sub-function for all this set stuff. The preset does
27602- * the same as a set, but returns just before finally setting the
27603- * new value. This is useful to check if a set might be successfull.
27604- * The sub-function runs through the IdTable, checks which OIDs are able
27605- * to set, and calls the handler function of the OID to perform the
27606- * preset. The return value of the function will also be stored in
27607- * SK_PNMI_STRUCT_DATA if the passed buffer has the minimum size of
27608- * SK_PNMI_MIN_STRUCT_SIZE.
27609- *
27610- * Returns:
27611- * SK_PNMI_ERR_OK The request was successfully performed.
27612- * SK_PNMI_ERR_GENERAL A general severe internal error occured.
27613- * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
27614- * the correct data (e.g. a 32bit value is
27615- * needed, but a 16 bit value was passed).
27616- * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid
27617- * value range.
27618- */
27619-int SkPnmiPreSetStruct(
27620-SK_AC *pAC, /* Pointer to adapter context */
27621-SK_IOC IoC, /* IO context handle */
27622-void *pBuf, /* Buffer which contains the data to be set */
27623-unsigned int *pLen, /* Length of buffer */
27624-SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */
27625-{
27626- SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
27627- ("PNMI: SkPnmiPreSetStruct: Called, BufLen=%d, NetIndex=%d\n",
27628- *pLen, NetIndex));
27629-
27630- return (PnmiStruct(pAC, IoC, SK_PNMI_PRESET, (char *)pBuf,
27631- pLen, NetIndex));
27632-}
27633-
27634-/*****************************************************************************
27635- *
27636- * SkPnmiSetStruct - Sets the management database in SK_PNMI_STRUCT_DATA
27637- *
27638- * Description:
27639- * Calls a general sub-function for all this set stuff. The return value
27640- * of the function will also be stored in SK_PNMI_STRUCT_DATA if the
27641- * passed buffer has the minimum size of SK_PNMI_MIN_STRUCT_SIZE.
27642- * The sub-function runs through the IdTable, checks which OIDs are able
27643- * to set, and calls the handler function of the OID to perform the
27644- * set. The return value of the function will also be stored in
27645- * SK_PNMI_STRUCT_DATA if the passed buffer has the minimum size of
27646- * SK_PNMI_MIN_STRUCT_SIZE.
27647- *
27648- * Returns:
27649- * SK_PNMI_ERR_OK The request was successfully performed.
27650- * SK_PNMI_ERR_GENERAL A general severe internal error occured.
27651- * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
27652- * the correct data (e.g. a 32bit value is
27653- * needed, but a 16 bit value was passed).
27654- * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid
27655- * value range.
27656- */
27657-int SkPnmiSetStruct(
27658-SK_AC *pAC, /* Pointer to adapter context */
27659-SK_IOC IoC, /* IO context handle */
27660-void *pBuf, /* Buffer which contains the data to be set */
27661-unsigned int *pLen, /* Length of buffer */
27662-SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */
27663-{
27664- SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
27665- ("PNMI: SkPnmiSetStruct: Called, BufLen=%d, NetIndex=%d\n",
27666- *pLen, NetIndex));
27667-
27668- return (PnmiStruct(pAC, IoC, SK_PNMI_SET, (char *)pBuf,
27669- pLen, NetIndex));
27670-}
27671-
27672-/*****************************************************************************
27673- *
27674- * SkPnmiEvent - Event handler
27675- *
27676- * Description:
27677- * Handles the following events:
27678- * SK_PNMI_EVT_SIRQ_OVERFLOW When a hardware counter overflows an
27679- * interrupt will be generated which is
27680- * first handled by SIRQ which generates a
27681- * this event. The event increments the
27682- * upper 32 bit of the 64 bit counter.
27683- * SK_PNMI_EVT_SEN_XXX The event is generated by the I2C module
27684- * when a sensor reports a warning or
27685- * error. The event will store a trap
27686- * message in the trap buffer.
27687- * SK_PNMI_EVT_CHG_EST_TIMER The timer event was initiated by this
27688- * module and is used to calculate the
27689- * port switches per hour.
27690- * SK_PNMI_EVT_CLEAR_COUNTER The event clears all counters and
27691- * timestamps.
27692- * SK_PNMI_EVT_XMAC_RESET The event is generated by the driver
27693- * before a hard reset of the XMAC is
27694- * performed. All counters will be saved
27695- * and added to the hardware counter
27696- * values after reset to grant continuous
27697- * counter values.
27698- * SK_PNMI_EVT_RLMT_PORT_UP Generated by RLMT to notify that a port
27699- * went logically up. A trap message will
27700- * be stored to the trap buffer.
27701- * SK_PNMI_EVT_RLMT_PORT_DOWN Generated by RLMT to notify that a port
27702- * went logically down. A trap message will
27703- * be stored to the trap buffer.
27704- * SK_PNMI_EVT_RLMT_SEGMENTATION Generated by RLMT to notify that two
27705- * spanning tree root bridges were
27706- * detected. A trap message will be stored
27707- * to the trap buffer.
27708- * SK_PNMI_EVT_RLMT_ACTIVE_DOWN Notifies PNMI that an active port went
27709- * down. PNMI will not further add the
27710- * statistic values to the virtual port.
27711- * SK_PNMI_EVT_RLMT_ACTIVE_UP Notifies PNMI that a port went up and
27712- * is now an active port. PNMI will now
27713- * add the statistic data of this port to
27714- * the virtual port.
27715- * SK_PNMI_EVT_RLMT_SET_NETS Notifies PNMI about the net mode. The first parameter
27716- * contains the number of nets. 1 means single net, 2 means
27717- * dual net. The second parameter is -1
27718- *
27719- * Returns:
27720- * Always 0
27721- */
27722-int SkPnmiEvent(
27723-SK_AC *pAC, /* Pointer to adapter context */
27724-SK_IOC IoC, /* IO context handle */
27725-SK_U32 Event, /* Event-Id */
27726-SK_EVPARA Param) /* Event dependent parameter */
27727-{
27728- unsigned int PhysPortIndex;
27729- unsigned int MaxNetNumber;
27730- int CounterIndex;
27731- int Ret;
27732- SK_U16 MacStatus;
27733- SK_U64 OverflowStatus;
27734- SK_U64 Mask;
27735- int MacType;
27736- SK_U64 Value;
27737- SK_U32 Val32;
27738- SK_U16 Register;
27739- SK_EVPARA EventParam;
27740- SK_U64 NewestValue;
27741- SK_U64 OldestValue;
27742- SK_U64 Delta;
27743- SK_PNMI_ESTIMATE *pEst;
27744- SK_U32 NetIndex;
27745- SK_GEPORT *pPrt;
27746- SK_PNMI_VCT *pVctBackupData;
27747- SK_U32 RetCode;
27748- int i;
27749- SK_U32 CableLength;
27750-
27751-
27752-#ifdef DEBUG
27753- if (Event != SK_PNMI_EVT_XMAC_RESET) {
27754-
27755- SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
27756- ("PNMI: SkPnmiEvent: Called, Event=0x%x, Param=0x%x\n",
27757- (unsigned int)Event, (unsigned int)Param.Para64));
27758- }
27759-#endif /* DEBUG */
27760- SK_PNMI_CHECKFLAGS("SkPnmiEvent: On call");
27761-
27762- MacType = pAC->GIni.GIMacType;
27763-
27764- switch (Event) {
27765-
27766- case SK_PNMI_EVT_SIRQ_OVERFLOW:
27767- PhysPortIndex = (int)Param.Para32[0];
27768- MacStatus = (SK_U16)Param.Para32[1];
27769-#ifdef DEBUG
27770- if (PhysPortIndex >= SK_MAX_MACS) {
27771-
27772- SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
27773- ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_SIRQ_OVERFLOW parameter"
27774- " wrong, PhysPortIndex=0x%x\n",
27775- PhysPortIndex));
27776- return (0);
27777- }
27778-#endif /* DEBUG */
27779- OverflowStatus = 0;
27780-
27781- /*
27782- * Check which source caused an overflow interrupt.
27783- */
27784- if ((pAC->GIni.GIFunc.pFnMacOverflow(pAC, IoC, PhysPortIndex,
27785- MacStatus, &OverflowStatus) != 0) ||
27786- (OverflowStatus == 0)) {
27787-
27788- SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return");
27789- return (0);
27790- }
27791-
27792- /*
27793- * Check the overflow status register and increment
27794- * the upper dword of corresponding counter.
27795- */
27796- for (CounterIndex = 0; CounterIndex < sizeof(Mask) * 8;
27797- CounterIndex ++) {
27798-
27799- Mask = (SK_U64)1 << CounterIndex;
27800- if ((OverflowStatus & Mask) == 0) {
27801-
27802- continue;
27803- }
27804-
27805- switch (StatOvrflwBit[CounterIndex][MacType]) {
27806-
27807- case SK_PNMI_HTX_UTILUNDER:
27808- case SK_PNMI_HTX_UTILOVER:
27809- if (MacType == SK_MAC_XMAC) {
27810- XM_IN16(IoC, PhysPortIndex, XM_TX_CMD, &Register);
27811- Register |= XM_TX_SAM_LINE;
27812- XM_OUT16(IoC, PhysPortIndex, XM_TX_CMD, Register);
27813- }
27814- break;
27815-
27816- case SK_PNMI_HRX_UTILUNDER:
27817- case SK_PNMI_HRX_UTILOVER:
27818- if (MacType == SK_MAC_XMAC) {
27819- XM_IN16(IoC, PhysPortIndex, XM_RX_CMD, &Register);
27820- Register |= XM_RX_SAM_LINE;
27821- XM_OUT16(IoC, PhysPortIndex, XM_RX_CMD, Register);
27822- }
27823- break;
27824-
27825- case SK_PNMI_HTX_OCTETHIGH:
27826- case SK_PNMI_HTX_OCTETLOW:
27827- case SK_PNMI_HTX_RESERVED:
27828- case SK_PNMI_HRX_OCTETHIGH:
27829- case SK_PNMI_HRX_OCTETLOW:
27830- case SK_PNMI_HRX_IRLENGTH:
27831- case SK_PNMI_HRX_RESERVED:
27832-
27833- /*
27834- * the following counters aren't be handled (id > 63)
27835- */
27836- case SK_PNMI_HTX_SYNC:
27837- case SK_PNMI_HTX_SYNC_OCTET:
27838- break;
27839-
27840- case SK_PNMI_HRX_LONGFRAMES:
27841- if (MacType == SK_MAC_GMAC) {
27842- pAC->Pnmi.Port[PhysPortIndex].
27843- CounterHigh[CounterIndex] ++;
27844- }
27845- break;
27846-
27847- default:
27848- pAC->Pnmi.Port[PhysPortIndex].
27849- CounterHigh[CounterIndex] ++;
27850- }
27851- }
27852- break;
27853-
27854- case SK_PNMI_EVT_SEN_WAR_LOW:
27855-#ifdef DEBUG
27856- if ((unsigned int)Param.Para64 >= (unsigned int)pAC->I2c.MaxSens) {
27857-
27858- SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
27859- ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_SEN_WAR_LOW parameter wrong, SensorIndex=%d\n",
27860- (unsigned int)Param.Para64));
27861- return (0);
27862- }
27863-#endif /* DEBUG */
27864-
27865- /*
27866- * Store a trap message in the trap buffer and generate
27867- * an event for user space applications with the
27868- * SK_DRIVER_SENDEVENT macro.
27869- */
27870- QueueSensorTrap(pAC, OID_SKGE_TRAP_SEN_WAR_LOW,
27871- (unsigned int)Param.Para64);
27872- (void)SK_DRIVER_SENDEVENT(pAC, IoC);
27873- break;
27874-
27875- case SK_PNMI_EVT_SEN_WAR_UPP:
27876-#ifdef DEBUG
27877- if ((unsigned int)Param.Para64 >= (unsigned int)pAC->I2c.MaxSens) {
27878-
27879- SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
27880- ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_SEN_WAR_UPP parameter wrong, SensorIndex=%d\n",
27881- (unsigned int)Param.Para64));
27882- return (0);
27883- }
27884-#endif /* DEBUG */
27885-
27886- /*
27887- * Store a trap message in the trap buffer and generate
27888- * an event for user space applications with the
27889- * SK_DRIVER_SENDEVENT macro.
27890- */
27891- QueueSensorTrap(pAC, OID_SKGE_TRAP_SEN_WAR_UPP,
27892- (unsigned int)Param.Para64);
27893- (void)SK_DRIVER_SENDEVENT(pAC, IoC);
27894- break;
27895-
27896- case SK_PNMI_EVT_SEN_ERR_LOW:
27897-#ifdef DEBUG
27898- if ((unsigned int)Param.Para64 >= (unsigned int)pAC->I2c.MaxSens) {
27899-
27900- SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
27901- ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_SEN_ERR_LOW parameter wrong, SensorIndex=%d\n",
27902- (unsigned int)Param.Para64));
27903- return (0);
27904- }
27905-#endif /* DEBUG */
27906-
27907- /*
27908- * Store a trap message in the trap buffer and generate
27909- * an event for user space applications with the
27910- * SK_DRIVER_SENDEVENT macro.
27911- */
27912- QueueSensorTrap(pAC, OID_SKGE_TRAP_SEN_ERR_LOW,
27913- (unsigned int)Param.Para64);
27914- (void)SK_DRIVER_SENDEVENT(pAC, IoC);
27915- break;
27916-
27917- case SK_PNMI_EVT_SEN_ERR_UPP:
27918-#ifdef DEBUG
27919- if ((unsigned int)Param.Para64 >= (unsigned int)pAC->I2c.MaxSens) {
27920-
27921- SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
27922- ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_SEN_ERR_UPP parameter wrong, SensorIndex=%d\n",
27923- (unsigned int)Param.Para64));
27924- return (0);
27925- }
27926-#endif /* DEBUG */
27927-
27928- /*
27929- * Store a trap message in the trap buffer and generate
27930- * an event for user space applications with the
27931- * SK_DRIVER_SENDEVENT macro.
27932- */
27933- QueueSensorTrap(pAC, OID_SKGE_TRAP_SEN_ERR_UPP,
27934- (unsigned int)Param.Para64);
27935- (void)SK_DRIVER_SENDEVENT(pAC, IoC);
27936- break;
27937-
27938- case SK_PNMI_EVT_CHG_EST_TIMER:
27939- /*
27940- * Calculate port switch average on a per hour basis
27941- * Time interval for check : 28125 ms
27942- * Number of values for average : 8
27943- *
27944- * Be careful in changing these values, on change check
27945- * - typedef of SK_PNMI_ESTIMATE (Size of EstValue
27946- * array one less than value number)
27947- * - Timer initialization SkTimerStart() in SkPnmiInit
27948- * - Delta value below must be multiplicated with
27949- * power of 2
27950- *
27951- */
27952- pEst = &pAC->Pnmi.RlmtChangeEstimate;
27953- CounterIndex = pEst->EstValueIndex + 1;
27954- if (CounterIndex == 7) {
27955-
27956- CounterIndex = 0;
27957- }
27958- pEst->EstValueIndex = CounterIndex;
27959-
27960- NewestValue = pAC->Pnmi.RlmtChangeCts;
27961- OldestValue = pEst->EstValue[CounterIndex];
27962- pEst->EstValue[CounterIndex] = NewestValue;
27963-
27964- /*
27965- * Calculate average. Delta stores the number of
27966- * port switches per 28125 * 8 = 225000 ms
27967- */
27968- if (NewestValue >= OldestValue) {
27969-
27970- Delta = NewestValue - OldestValue;
27971- }
27972- else {
27973- /* Overflow situation */
27974- Delta = (SK_U64)(0 - OldestValue) + NewestValue;
27975- }
27976-
27977- /*
27978- * Extrapolate delta to port switches per hour.
27979- * Estimate = Delta * (3600000 / 225000)
27980- * = Delta * 16
27981- * = Delta << 4
27982- */
27983- pAC->Pnmi.RlmtChangeEstimate.Estimate = Delta << 4;
27984-
27985- /*
27986- * Check if threshold is exceeded. If the threshold is
27987- * permanently exceeded every 28125 ms an event will be
27988- * generated to remind the user of this condition.
27989- */
27990- if ((pAC->Pnmi.RlmtChangeThreshold != 0) &&
27991- (pAC->Pnmi.RlmtChangeEstimate.Estimate >=
27992- pAC->Pnmi.RlmtChangeThreshold)) {
27993-
27994- QueueSimpleTrap(pAC, OID_SKGE_TRAP_RLMT_CHANGE_THRES);
27995- (void)SK_DRIVER_SENDEVENT(pAC, IoC);
27996- }
27997-
27998- SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
27999- SkTimerStart(pAC, IoC, &pAC->Pnmi.RlmtChangeEstimate.EstTimer,
28000- 28125000, SKGE_PNMI, SK_PNMI_EVT_CHG_EST_TIMER,
28001- EventParam);
28002- break;
28003-
28004- case SK_PNMI_EVT_CLEAR_COUNTER:
28005- /*
28006- * Param.Para32[0] contains the NetIndex (0 ..1).
28007- * Param.Para32[1] is reserved, contains -1.
28008- */
28009- NetIndex = (SK_U32)Param.Para32[0];
28010-
28011-#ifdef DEBUG
28012- if (NetIndex >= pAC->Rlmt.NumNets) {
28013-
28014- SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
28015- ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_CLEAR_COUNTER parameter wrong, NetIndex=%d\n",
28016- NetIndex));
28017-
28018- return (0);
28019- }
28020-#endif /* DEBUG */
28021-
28022- /*
28023- * Set all counters and timestamps to zero.
28024- * The according NetIndex is required as a
28025- * parameter of the event.
28026- */
28027- ResetCounter(pAC, IoC, NetIndex);
28028- break;
28029-
28030- case SK_PNMI_EVT_XMAC_RESET:
28031- /*
28032- * To grant continuous counter values store the current
28033- * XMAC statistic values to the entries 1..n of the
28034- * CounterOffset array. XMAC Errata #2
28035- */
28036-#ifdef DEBUG
28037- if ((unsigned int)Param.Para64 >= SK_MAX_MACS) {
28038-
28039- SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
28040- ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_XMAC_RESET parameter wrong, PhysPortIndex=%d\n",
28041- (unsigned int)Param.Para64));
28042- return (0);
28043- }
28044-#endif
28045- PhysPortIndex = (unsigned int)Param.Para64;
28046-
28047- /*
28048- * Update XMAC statistic to get fresh values
28049- */
28050- Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1);
28051- if (Ret != SK_PNMI_ERR_OK) {
28052-
28053- SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return");
28054- return (0);
28055- }
28056- /*
28057- * Increment semaphore to indicate that an update was
28058- * already done
28059- */
28060- pAC->Pnmi.MacUpdatedFlag ++;
28061-
28062- for (CounterIndex = 0; CounterIndex < SK_PNMI_MAX_IDX;
28063- CounterIndex ++) {
28064-
28065- if (!StatAddr[CounterIndex][MacType].GetOffset) {
28066-
28067- continue;
28068- }
28069-
28070- pAC->Pnmi.Port[PhysPortIndex].CounterOffset[CounterIndex] =
28071- GetPhysStatVal(pAC, IoC, PhysPortIndex, CounterIndex);
28072-
28073- pAC->Pnmi.Port[PhysPortIndex].CounterHigh[CounterIndex] = 0;
28074- }
28075-
28076- pAC->Pnmi.MacUpdatedFlag --;
28077- break;
28078-
28079- case SK_PNMI_EVT_RLMT_PORT_UP:
28080- PhysPortIndex = (unsigned int)Param.Para32[0];
28081-#ifdef DEBUG
28082- if (PhysPortIndex >= SK_MAX_MACS) {
28083-
28084- SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
28085- ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_PORT_UP parameter"
28086- " wrong, PhysPortIndex=%d\n", PhysPortIndex));
28087-
28088- return (0);
28089- }
28090-#endif /* DEBUG */
28091-
28092- /*
28093- * Store a trap message in the trap buffer and generate an event for
28094- * user space applications with the SK_DRIVER_SENDEVENT macro.
28095- */
28096- QueueRlmtPortTrap(pAC, OID_SKGE_TRAP_RLMT_PORT_UP, PhysPortIndex);
28097- (void)SK_DRIVER_SENDEVENT(pAC, IoC);
28098-
28099- /* Bugfix for XMAC errata (#10620)*/
28100- if (MacType == SK_MAC_XMAC) {
28101- /* Add incremental difference to offset (#10620)*/
28102- (void)pAC->GIni.GIFunc.pFnMacStatistic(pAC, IoC, PhysPortIndex,
28103- XM_RXE_SHT_ERR, &Val32);
28104-
28105- Value = (((SK_U64)pAC->Pnmi.Port[PhysPortIndex].
28106- CounterHigh[SK_PNMI_HRX_SHORTS] << 32) | (SK_U64)Val32);
28107- pAC->Pnmi.Port[PhysPortIndex].CounterOffset[SK_PNMI_HRX_SHORTS] +=
28108- Value - pAC->Pnmi.Port[PhysPortIndex].RxShortZeroMark;
28109- }
28110-
28111- /* Tell VctStatus() that a link was up meanwhile. */
28112- pAC->Pnmi.VctStatus[PhysPortIndex] |= SK_PNMI_VCT_LINK;
28113- break;
28114-
28115- case SK_PNMI_EVT_RLMT_PORT_DOWN:
28116- PhysPortIndex = (unsigned int)Param.Para32[0];
28117-
28118-#ifdef DEBUG
28119- if (PhysPortIndex >= SK_MAX_MACS) {
28120-
28121- SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
28122- ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_PORT_DOWN parameter"
28123- " wrong, PhysPortIndex=%d\n", PhysPortIndex));
28124-
28125- return (0);
28126- }
28127-#endif /* DEBUG */
28128-
28129- /*
28130- * Store a trap message in the trap buffer and generate an event for
28131- * user space applications with the SK_DRIVER_SENDEVENT macro.
28132- */
28133- QueueRlmtPortTrap(pAC, OID_SKGE_TRAP_RLMT_PORT_DOWN, PhysPortIndex);
28134- (void)SK_DRIVER_SENDEVENT(pAC, IoC);
28135-
28136- /* Bugfix #10620 - get zero level for incremental difference */
28137- if (MacType == SK_MAC_XMAC) {
28138-
28139- (void)pAC->GIni.GIFunc.pFnMacStatistic(pAC, IoC, PhysPortIndex,
28140- XM_RXE_SHT_ERR, &Val32);
28141-
28142- pAC->Pnmi.Port[PhysPortIndex].RxShortZeroMark =
28143- (((SK_U64)pAC->Pnmi.Port[PhysPortIndex].
28144- CounterHigh[SK_PNMI_HRX_SHORTS] << 32) | (SK_U64)Val32);
28145- }
28146- break;
28147-
28148- case SK_PNMI_EVT_RLMT_ACTIVE_DOWN:
28149- PhysPortIndex = (unsigned int)Param.Para32[0];
28150- NetIndex = (SK_U32)Param.Para32[1];
28151-
28152-#ifdef DEBUG
28153- if (PhysPortIndex >= SK_MAX_MACS) {
28154-
28155- SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
28156- ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_ACTIVE_DOWN parameter too high, PhysPort=%d\n",
28157- PhysPortIndex));
28158- }
28159-
28160- if (NetIndex >= pAC->Rlmt.NumNets) {
28161-
28162- SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
28163- ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_ACTIVE_DOWN parameter too high, NetIndex=%d\n",
28164- NetIndex));
28165- }
28166-#endif /* DEBUG */
28167-
28168- /*
28169- * For now, ignore event if NetIndex != 0.
28170- */
28171- if (Param.Para32[1] != 0) {
28172-
28173- return (0);
28174- }
28175-
28176- /*
28177- * Nothing to do if port is already inactive
28178- */
28179- if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
28180-
28181- return (0);
28182- }
28183-
28184- /*
28185- * Update statistic counters to calculate new offset for the virtual
28186- * port and increment semaphore to indicate that an update was already
28187- * done.
28188- */
28189- if (MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1) !=
28190- SK_PNMI_ERR_OK) {
28191-
28192- SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return");
28193- return (0);
28194- }
28195- pAC->Pnmi.MacUpdatedFlag ++;
28196-
28197- /*
28198- * Calculate new counter offset for virtual port to grant continous
28199- * counting on port switches. The virtual port consists of all currently
28200- * active ports. The port down event indicates that a port is removed
28201- * from the virtual port. Therefore add the counter value of the removed
28202- * port to the CounterOffset for the virtual port to grant the same
28203- * counter value.
28204- */
28205- for (CounterIndex = 0; CounterIndex < SK_PNMI_MAX_IDX;
28206- CounterIndex ++) {
28207-
28208- if (!StatAddr[CounterIndex][MacType].GetOffset) {
28209-
28210- continue;
28211- }
28212-
28213- Value = GetPhysStatVal(pAC, IoC, PhysPortIndex, CounterIndex);
28214-
28215- pAC->Pnmi.VirtualCounterOffset[CounterIndex] += Value;
28216- }
28217-
28218- /*
28219- * Set port to inactive
28220- */
28221- pAC->Pnmi.Port[PhysPortIndex].ActiveFlag = SK_FALSE;
28222-
28223- pAC->Pnmi.MacUpdatedFlag --;
28224- break;
28225-
28226- case SK_PNMI_EVT_RLMT_ACTIVE_UP:
28227- PhysPortIndex = (unsigned int)Param.Para32[0];
28228- NetIndex = (SK_U32)Param.Para32[1];
28229-
28230-#ifdef DEBUG
28231- if (PhysPortIndex >= SK_MAX_MACS) {
28232-
28233- SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
28234- ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_ACTIVE_UP parameter too high, PhysPort=%d\n",
28235- PhysPortIndex));
28236- }
28237-
28238- if (NetIndex >= pAC->Rlmt.NumNets) {
28239-
28240- SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
28241- ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_ACTIVE_UP parameter too high, NetIndex=%d\n",
28242- NetIndex));
28243- }
28244-#endif /* DEBUG */
28245-
28246- /*
28247- * For now, ignore event if NetIndex != 0.
28248- */
28249- if (Param.Para32[1] != 0) {
28250-
28251- return (0);
28252- }
28253-
28254- /*
28255- * Nothing to do if port is already active
28256- */
28257- if (pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
28258-
28259- return (0);
28260- }
28261-
28262- /*
28263- * Statistic maintenance
28264- */
28265- pAC->Pnmi.RlmtChangeCts ++;
28266- pAC->Pnmi.RlmtChangeTime = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC));
28267-
28268- /*
28269- * Store a trap message in the trap buffer and generate an event for
28270- * user space applications with the SK_DRIVER_SENDEVENT macro.
28271- */
28272- QueueRlmtNewMacTrap(pAC, PhysPortIndex);
28273- (void)SK_DRIVER_SENDEVENT(pAC, IoC);
28274-
28275- /*
28276- * Update statistic counters to calculate new offset for the virtual
28277- * port and increment semaphore to indicate that an update was
28278- * already done.
28279- */
28280- if (MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1) !=
28281- SK_PNMI_ERR_OK) {
28282-
28283- SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return");
28284- return (0);
28285- }
28286- pAC->Pnmi.MacUpdatedFlag ++;
28287-
28288- /*
28289- * Calculate new counter offset for virtual port to grant continous
28290- * counting on port switches. A new port is added to the virtual port.
28291- * Therefore substract the counter value of the new port from the
28292- * CounterOffset for the virtual port to grant the same value.
28293- */
28294- for (CounterIndex = 0; CounterIndex < SK_PNMI_MAX_IDX;
28295- CounterIndex ++) {
28296-
28297- if (!StatAddr[CounterIndex][MacType].GetOffset) {
28298-
28299- continue;
28300- }
28301-
28302- Value = GetPhysStatVal(pAC, IoC, PhysPortIndex, CounterIndex);
28303-
28304- pAC->Pnmi.VirtualCounterOffset[CounterIndex] -= Value;
28305- }
28306-
28307- /* Set port to active */
28308- pAC->Pnmi.Port[PhysPortIndex].ActiveFlag = SK_TRUE;
28309-
28310- pAC->Pnmi.MacUpdatedFlag --;
28311- break;
28312-
28313- case SK_PNMI_EVT_RLMT_SEGMENTATION:
28314- /*
28315- * Para.Para32[0] contains the NetIndex.
28316- */
28317-
28318- /*
28319- * Store a trap message in the trap buffer and generate an event for
28320- * user space applications with the SK_DRIVER_SENDEVENT macro.
28321- */
28322- QueueSimpleTrap(pAC, OID_SKGE_TRAP_RLMT_SEGMENTATION);
28323- (void)SK_DRIVER_SENDEVENT(pAC, IoC);
28324- break;
28325-
28326- case SK_PNMI_EVT_RLMT_SET_NETS:
28327- /*
28328- * Param.Para32[0] contains the number of Nets.
28329- * Param.Para32[1] is reserved, contains -1.
28330- */
28331- /*
28332- * Check number of nets
28333- */
28334- MaxNetNumber = pAC->GIni.GIMacsFound;
28335- if (((unsigned int)Param.Para32[0] < 1)
28336- || ((unsigned int)Param.Para32[0] > MaxNetNumber)) {
28337- return (SK_PNMI_ERR_UNKNOWN_NET);
28338- }
28339-
28340- if ((unsigned int)Param.Para32[0] == 1) { /* single net mode */
28341- pAC->Pnmi.DualNetActiveFlag = SK_FALSE;
28342- }
28343- else { /* dual net mode */
28344- pAC->Pnmi.DualNetActiveFlag = SK_TRUE;
28345- }
28346- break;
28347-
28348- case SK_PNMI_EVT_VCT_RESET:
28349- PhysPortIndex = Param.Para32[0];
28350- pPrt = &pAC->GIni.GP[PhysPortIndex];
28351- pVctBackupData = &pAC->Pnmi.VctBackup[PhysPortIndex];
28352-
28353- if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_PENDING) {
28354- RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_FALSE);
28355- if (RetCode == 2) {
28356- /*
28357- * VCT test is still running.
28358- * Start VCT timer counter again.
28359- */
28360- SK_MEMSET((char *) &Param, 0, sizeof(Param));
28361- Param.Para32[0] = PhysPortIndex;
28362- Param.Para32[1] = -1;
28363- SkTimerStart(pAC, IoC,
28364- &pAC->Pnmi.VctTimeout[PhysPortIndex].VctTimer,
28365- 4000000, SKGE_PNMI, SK_PNMI_EVT_VCT_RESET, Param);
28366- break;
28367- }
28368- pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_PENDING;
28369- pAC->Pnmi.VctStatus[PhysPortIndex] |=
28370- (SK_PNMI_VCT_NEW_VCT_DATA | SK_PNMI_VCT_TEST_DONE);
28371-
28372- /* Copy results for later use to PNMI struct. */
28373- for (i = 0; i < 4; i++) {
28374- if (pPrt->PMdiPairSts[i] == SK_PNMI_VCT_NORMAL_CABLE) {
28375- if ((pPrt->PMdiPairLen[i] > 35) &&
28376- (pPrt->PMdiPairLen[i] < 0xff)) {
28377- pPrt->PMdiPairSts[i] = SK_PNMI_VCT_IMPEDANCE_MISMATCH;
28378- }
28379- }
28380- if ((pPrt->PMdiPairLen[i] > 35) &&
28381- (pPrt->PMdiPairLen[i] != 0xff)) {
28382- CableLength = 1000 *
28383- (((175 * pPrt->PMdiPairLen[i]) / 210) - 28);
28384- }
28385- else {
28386- CableLength = 0;
28387- }
28388- pVctBackupData->PMdiPairLen[i] = CableLength;
28389- pVctBackupData->PMdiPairSts[i] = pPrt->PMdiPairSts[i];
28390- }
28391-
28392- Param.Para32[0] = PhysPortIndex;
28393- Param.Para32[1] = -1;
28394- SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Param);
28395- SkEventDispatcher(pAC, IoC);
28396- }
28397-
28398- break;
28399-
28400- default:
28401- break;
28402- }
28403-
28404- SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return");
28405- return (0);
28406-}
28407-
28408-
28409-/******************************************************************************
28410- *
28411- * Private functions
28412- *
28413- */
28414-
28415-/*****************************************************************************
28416- *
28417- * PnmiVar - Gets, presets, and sets single OIDs
28418- *
28419- * Description:
28420- * Looks up the requested OID, calls the corresponding handler
28421- * function, and passes the parameters with the get, preset, or
28422- * set command. The function is called by SkGePnmiGetVar,
28423- * SkGePnmiPreSetVar, or SkGePnmiSetVar.
28424- *
28425- * Returns:
28426- * SK_PNMI_ERR_XXX. For details have a look at the description of the
28427- * calling functions.
28428- * SK_PNMI_ERR_UNKNOWN_NET The requested NetIndex doesn't exist
28429- */
28430-PNMI_STATIC int PnmiVar(
28431-SK_AC *pAC, /* Pointer to adapter context */
28432-SK_IOC IoC, /* IO context handle */
28433-int Action, /* GET/PRESET/SET action */
28434-SK_U32 Id, /* Object ID that is to be processed */
28435-char *pBuf, /* Buffer used for the management data transfer */
28436-unsigned int *pLen, /* Total length of pBuf management data */
28437-SK_U32 Instance, /* Instance (1..n) that is to be set or -1 */
28438-SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */
28439-{
28440- unsigned int TableIndex;
28441- int Ret;
28442-
28443-
28444- if ((TableIndex = LookupId(Id)) == (unsigned int)(-1)) {
28445-
28446- *pLen = 0;
28447- return (SK_PNMI_ERR_UNKNOWN_OID);
28448- }
28449-
28450- /* Check NetIndex */
28451- if (NetIndex >= pAC->Rlmt.NumNets) {
28452- return (SK_PNMI_ERR_UNKNOWN_NET);
28453- }
28454-
28455- SK_PNMI_CHECKFLAGS("PnmiVar: On call");
28456-
28457- Ret = IdTable[TableIndex].Func(pAC, IoC, Action, Id, pBuf, pLen,
28458- Instance, TableIndex, NetIndex);
28459-
28460- SK_PNMI_CHECKFLAGS("PnmiVar: On return");
28461-
28462- return (Ret);
28463-}
28464-
28465-/*****************************************************************************
28466- *
28467- * PnmiStruct - Presets and Sets data in structure SK_PNMI_STRUCT_DATA
28468- *
28469- * Description:
28470- * The return value of the function will also be stored in
28471- * SK_PNMI_STRUCT_DATA if the passed buffer has the minimum size of
28472- * SK_PNMI_MIN_STRUCT_SIZE. The sub-function runs through the IdTable,
28473- * checks which OIDs are able to set, and calls the handler function of
28474- * the OID to perform the set. The return value of the function will
28475- * also be stored in SK_PNMI_STRUCT_DATA if the passed buffer has the
28476- * minimum size of SK_PNMI_MIN_STRUCT_SIZE. The function is called
28477- * by SkGePnmiPreSetStruct and SkGePnmiSetStruct.
28478- *
28479- * Returns:
28480- * SK_PNMI_ERR_XXX. The codes are described in the calling functions.
28481- * SK_PNMI_ERR_UNKNOWN_NET The requested NetIndex doesn't exist
28482- */
28483-PNMI_STATIC int PnmiStruct(
28484-SK_AC *pAC, /* Pointer to adapter context */
28485-SK_IOC IoC, /* IO context handle */
28486-int Action, /* PRESET/SET action to be performed */
28487-char *pBuf, /* Buffer used for the management data transfer */
28488-unsigned int *pLen, /* Length of pBuf management data buffer */
28489-SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */
28490-{
28491- int Ret;
28492- unsigned int TableIndex;
28493- unsigned int DstOffset;
28494- unsigned int Len;
28495- unsigned int InstanceNo;
28496- unsigned int InstanceCnt;
28497- SK_U32 Instance;
28498- SK_U32 Id;
28499-
28500-
28501- /* Check if the passed buffer has the right size */
28502- if (*pLen < SK_PNMI_STRUCT_SIZE) {
28503-
28504- /* Check if we can return the error within the buffer */
28505- if (*pLen >= SK_PNMI_MIN_STRUCT_SIZE) {
28506-
28507- SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_TOO_SHORT,
28508- (SK_U32)(-1));
28509- }
28510-
28511- *pLen = SK_PNMI_STRUCT_SIZE;
28512- return (SK_PNMI_ERR_TOO_SHORT);
28513- }
28514-
28515- /* Check NetIndex */
28516- if (NetIndex >= pAC->Rlmt.NumNets) {
28517- return (SK_PNMI_ERR_UNKNOWN_NET);
28518- }
28519-
28520- SK_PNMI_CHECKFLAGS("PnmiStruct: On call");
28521-
28522- /*
28523- * Update the values of RLMT and SIRQ and increment semaphores to
28524- * indicate that an update was already done.
28525- */
28526- if ((Ret = RlmtUpdate(pAC, IoC, NetIndex)) != SK_PNMI_ERR_OK) {
28527-
28528- SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1));
28529- *pLen = SK_PNMI_MIN_STRUCT_SIZE;
28530- return (Ret);
28531- }
28532-
28533- if ((Ret = SirqUpdate(pAC, IoC)) != SK_PNMI_ERR_OK) {
28534-
28535- SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1));
28536- *pLen = SK_PNMI_MIN_STRUCT_SIZE;
28537- return (Ret);
28538- }
28539-
28540- pAC->Pnmi.RlmtUpdatedFlag ++;
28541- pAC->Pnmi.SirqUpdatedFlag ++;
28542-
28543- /* Preset/Set values */
28544- for (TableIndex = 0; TableIndex < ID_TABLE_SIZE; TableIndex ++) {
28545-
28546- if ((IdTable[TableIndex].Access != SK_PNMI_RW) &&
28547- (IdTable[TableIndex].Access != SK_PNMI_WO)) {
28548-
28549- continue;
28550- }
28551-
28552- InstanceNo = IdTable[TableIndex].InstanceNo;
28553- Id = IdTable[TableIndex].Id;
28554-
28555- for (InstanceCnt = 1; InstanceCnt <= InstanceNo;
28556- InstanceCnt ++) {
28557-
28558- DstOffset = IdTable[TableIndex].Offset +
28559- (InstanceCnt - 1) *
28560- IdTable[TableIndex].StructSize;
28561-
28562- /*
28563- * Because VPD multiple instance variables are
28564- * not setable we do not need to evaluate VPD
28565- * instances. Have a look to VPD instance
28566- * calculation in SkPnmiGetStruct().
28567- */
28568- Instance = (SK_U32)InstanceCnt;
28569-
28570- /*
28571- * Evaluate needed buffer length
28572- */
28573- Len = 0;
28574- Ret = IdTable[TableIndex].Func(pAC, IoC,
28575- SK_PNMI_GET, IdTable[TableIndex].Id,
28576- NULL, &Len, Instance, TableIndex, NetIndex);
28577-
28578- if (Ret == SK_PNMI_ERR_UNKNOWN_INST) {
28579-
28580- break;
28581- }
28582- if (Ret != SK_PNMI_ERR_TOO_SHORT) {
28583-
28584- pAC->Pnmi.RlmtUpdatedFlag --;
28585- pAC->Pnmi.SirqUpdatedFlag --;
28586-
28587- SK_PNMI_CHECKFLAGS("PnmiStruct: On return");
28588- SK_PNMI_SET_STAT(pBuf,
28589- SK_PNMI_ERR_GENERAL, DstOffset);
28590- *pLen = SK_PNMI_MIN_STRUCT_SIZE;
28591- return (SK_PNMI_ERR_GENERAL);
28592- }
28593- if (Id == OID_SKGE_VPD_ACTION) {
28594-
28595- switch (*(pBuf + DstOffset)) {
28596-
28597- case SK_PNMI_VPD_CREATE:
28598- Len = 3 + *(pBuf + DstOffset + 3);
28599- break;
28600-
28601- case SK_PNMI_VPD_DELETE:
28602- Len = 3;
28603- break;
28604-
28605- default:
28606- Len = 1;
28607- break;
28608- }
28609- }
28610-
28611- /* Call the OID handler function */
28612- Ret = IdTable[TableIndex].Func(pAC, IoC, Action,
28613- IdTable[TableIndex].Id, pBuf + DstOffset,
28614- &Len, Instance, TableIndex, NetIndex);
28615-
28616- if (Ret != SK_PNMI_ERR_OK) {
28617-
28618- pAC->Pnmi.RlmtUpdatedFlag --;
28619- pAC->Pnmi.SirqUpdatedFlag --;
28620-
28621- SK_PNMI_CHECKFLAGS("PnmiStruct: On return");
28622- SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_BAD_VALUE,
28623- DstOffset);
28624- *pLen = SK_PNMI_MIN_STRUCT_SIZE;
28625- return (SK_PNMI_ERR_BAD_VALUE);
28626- }
28627- }
28628- }
28629-
28630- pAC->Pnmi.RlmtUpdatedFlag --;
28631- pAC->Pnmi.SirqUpdatedFlag --;
28632-
28633- SK_PNMI_CHECKFLAGS("PnmiStruct: On return");
28634- SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_OK, (SK_U32)(-1));
28635- return (SK_PNMI_ERR_OK);
28636-}
28637-
28638-/*****************************************************************************
28639- *
28640- * LookupId - Lookup an OID in the IdTable
28641- *
28642- * Description:
28643- * Scans the IdTable to find the table entry of an OID.
28644- *
28645- * Returns:
28646- * The table index or -1 if not found.
28647- */
28648-PNMI_STATIC int LookupId(
28649-SK_U32 Id) /* Object identifier to be searched */
28650-{
28651- int i;
28652-
28653- for (i = 0; i < ID_TABLE_SIZE; i++) {
28654-
28655- if (IdTable[i].Id == Id) {
28656-
28657- return i;
28658- }
28659- }
28660-
28661- return (-1);
28662-}
28663-
28664-/*****************************************************************************
28665- *
28666- * OidStruct - Handler of OID_SKGE_ALL_DATA
28667- *
28668- * Description:
28669- * This OID performs a Get/Preset/SetStruct call and returns all data
28670- * in a SK_PNMI_STRUCT_DATA structure.
28671- *
28672- * Returns:
28673- * SK_PNMI_ERR_OK The request was successfully performed.
28674- * SK_PNMI_ERR_GENERAL A general severe internal error occured.
28675- * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
28676- * the correct data (e.g. a 32bit value is
28677- * needed, but a 16 bit value was passed).
28678- * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid
28679- * value range.
28680- * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set.
28681- * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
28682- * exist (e.g. port instance 3 on a two port
28683- * adapter.
28684- */
28685-PNMI_STATIC int OidStruct(
28686-SK_AC *pAC, /* Pointer to adapter context */
28687-SK_IOC IoC, /* IO context handle */
28688-int Action, /* GET/PRESET/SET action */
28689-SK_U32 Id, /* Object ID that is to be processed */
28690-char *pBuf, /* Buffer used for the management data transfer */
28691-unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */
28692-SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
28693-unsigned int TableIndex, /* Index to the Id table */
28694-SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */
28695-{
28696- if (Id != OID_SKGE_ALL_DATA) {
28697-
28698- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR003,
28699- SK_PNMI_ERR003MSG);
28700-
28701- *pLen = 0;
28702- return (SK_PNMI_ERR_GENERAL);
28703- }
28704-
28705- /*
28706- * Check instance. We only handle single instance variables
28707- */
28708- if (Instance != (SK_U32)(-1) && Instance != 1) {
28709-
28710- *pLen = 0;
28711- return (SK_PNMI_ERR_UNKNOWN_INST);
28712- }
28713-
28714- switch (Action) {
28715-
28716- case SK_PNMI_GET:
28717- return (SkPnmiGetStruct(pAC, IoC, pBuf, pLen, NetIndex));
28718-
28719- case SK_PNMI_PRESET:
28720- return (SkPnmiPreSetStruct(pAC, IoC, pBuf, pLen, NetIndex));
28721-
28722- case SK_PNMI_SET:
28723- return (SkPnmiSetStruct(pAC, IoC, pBuf, pLen, NetIndex));
28724- }
28725-
28726- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR004, SK_PNMI_ERR004MSG);
28727-
28728- *pLen = 0;
28729- return (SK_PNMI_ERR_GENERAL);
28730-}
28731-
28732-/*****************************************************************************
28733- *
28734- * Perform - OID handler of OID_SKGE_ACTION
28735- *
28736- * Description:
28737- * None.
28738- *
28739- * Returns:
28740- * SK_PNMI_ERR_OK The request was successfully performed.
28741- * SK_PNMI_ERR_GENERAL A general severe internal error occured.
28742- * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
28743- * the correct data (e.g. a 32bit value is
28744- * needed, but a 16 bit value was passed).
28745- * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid
28746- * value range.
28747- * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set.
28748- * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
28749- * exist (e.g. port instance 3 on a two port
28750- * adapter.
28751- */
28752-PNMI_STATIC int Perform(
28753-SK_AC *pAC, /* Pointer to adapter context */
28754-SK_IOC IoC, /* IO context handle */
28755-int Action, /* GET/PRESET/SET action */
28756-SK_U32 Id, /* Object ID that is to be processed */
28757-char *pBuf, /* Buffer used for the management data transfer */
28758-unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */
28759-SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
28760-unsigned int TableIndex, /* Index to the Id table */
28761-SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */
28762-{
28763- int Ret;
28764- SK_U32 ActionOp;
28765-
28766-
28767- /*
28768- * Check instance. We only handle single instance variables
28769- */
28770- if (Instance != (SK_U32)(-1) && Instance != 1) {
28771-
28772- *pLen = 0;
28773- return (SK_PNMI_ERR_UNKNOWN_INST);
28774- }
28775-
28776- if (*pLen < sizeof(SK_U32)) {
28777-
28778- *pLen = sizeof(SK_U32);
28779- return (SK_PNMI_ERR_TOO_SHORT);
28780- }
28781-
28782- /* Check if a get should be performed */
28783- if (Action == SK_PNMI_GET) {
28784-
28785- /* A get is easy. We always return the same value */
28786- ActionOp = (SK_U32)SK_PNMI_ACT_IDLE;
28787- SK_PNMI_STORE_U32(pBuf, ActionOp);
28788- *pLen = sizeof(SK_U32);
28789-
28790- return (SK_PNMI_ERR_OK);
28791- }
28792-
28793- /* Continue with PRESET/SET action */
28794- if (*pLen > sizeof(SK_U32)) {
28795-
28796- return (SK_PNMI_ERR_BAD_VALUE);
28797- }
28798-
28799- /* Check if the command is a known one */
28800- SK_PNMI_READ_U32(pBuf, ActionOp);
28801- if (*pLen > sizeof(SK_U32) ||
28802- (ActionOp != SK_PNMI_ACT_IDLE &&
28803- ActionOp != SK_PNMI_ACT_RESET &&
28804- ActionOp != SK_PNMI_ACT_SELFTEST &&
28805- ActionOp != SK_PNMI_ACT_RESETCNT)) {
28806-
28807- *pLen = 0;
28808- return (SK_PNMI_ERR_BAD_VALUE);
28809- }
28810-
28811- /* A preset ends here */
28812- if (Action == SK_PNMI_PRESET) {
28813-
28814- return (SK_PNMI_ERR_OK);
28815- }
28816-
28817- switch (ActionOp) {
28818-
28819- case SK_PNMI_ACT_IDLE:
28820- /* Nothing to do */
28821- break;
28822-
28823- case SK_PNMI_ACT_RESET:
28824- /*
28825- * Perform a driver reset or something that comes near
28826- * to this.
28827- */
28828- Ret = SK_DRIVER_RESET(pAC, IoC);
28829- if (Ret != 0) {
28830-
28831- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR005,
28832- SK_PNMI_ERR005MSG);
28833-
28834- return (SK_PNMI_ERR_GENERAL);
28835- }
28836- break;
28837-
28838- case SK_PNMI_ACT_SELFTEST:
28839- /*
28840- * Perform a driver selftest or something similar to this.
28841- * Currently this feature is not used and will probably
28842- * implemented in another way.
28843- */
28844- Ret = SK_DRIVER_SELFTEST(pAC, IoC);
28845- pAC->Pnmi.TestResult = Ret;
28846- break;
28847-
28848- case SK_PNMI_ACT_RESETCNT:
28849- /* Set all counters and timestamps to zero */
28850- ResetCounter(pAC, IoC, NetIndex);
28851- break;
28852-
28853- default:
28854- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR006,
28855- SK_PNMI_ERR006MSG);
28856-
28857- return (SK_PNMI_ERR_GENERAL);
28858- }
28859-
28860- return (SK_PNMI_ERR_OK);
28861-}
28862-
28863-/*****************************************************************************
28864- *
28865- * Mac8023Stat - OID handler of OID_GEN_XXX and OID_802_3_XXX
28866- *
28867- * Description:
28868- * Retrieves the statistic values of the virtual port (logical
28869- * index 0). Only special OIDs of NDIS are handled which consist
28870- * of a 32 bit instead of a 64 bit value. The OIDs are public
28871- * because perhaps some other platform can use them too.
28872- *
28873- * Returns:
28874- * SK_PNMI_ERR_OK The request was successfully performed.
28875- * SK_PNMI_ERR_GENERAL A general severe internal error occured.
28876- * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
28877- * the correct data (e.g. a 32bit value is
28878- * needed, but a 16 bit value was passed).
28879- * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
28880- * exist (e.g. port instance 3 on a two port
28881- * adapter.
28882- */
28883-PNMI_STATIC int Mac8023Stat(
28884-SK_AC *pAC, /* Pointer to adapter context */
28885-SK_IOC IoC, /* IO context handle */
28886-int Action, /* GET/PRESET/SET action */
28887-SK_U32 Id, /* Object ID that is to be processed */
28888-char *pBuf, /* Buffer used for the management data transfer */
28889-unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */
28890-SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
28891-unsigned int TableIndex, /* Index to the Id table */
28892-SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */
28893-{
28894- int Ret;
28895- SK_U64 StatVal;
28896- SK_U32 StatVal32;
28897- SK_BOOL Is64BitReq = SK_FALSE;
28898-
28899- /*
28900- * Only the active Mac is returned
28901- */
28902- if (Instance != (SK_U32)(-1) && Instance != 1) {
28903-
28904- *pLen = 0;
28905- return (SK_PNMI_ERR_UNKNOWN_INST);
28906- }
28907-
28908- /*
28909- * Check action type
28910- */
28911- if (Action != SK_PNMI_GET) {
28912-
28913- *pLen = 0;
28914- return (SK_PNMI_ERR_READ_ONLY);
28915- }
28916-
28917- /* Check length */
28918- switch (Id) {
28919-
28920- case OID_802_3_PERMANENT_ADDRESS:
28921- case OID_802_3_CURRENT_ADDRESS:
28922- if (*pLen < sizeof(SK_MAC_ADDR)) {
28923-
28924- *pLen = sizeof(SK_MAC_ADDR);
28925- return (SK_PNMI_ERR_TOO_SHORT);
28926- }
28927- break;
28928-
28929- default:
28930-#ifndef SK_NDIS_64BIT_CTR
28931- if (*pLen < sizeof(SK_U32)) {
28932- *pLen = sizeof(SK_U32);
28933- return (SK_PNMI_ERR_TOO_SHORT);
28934- }
28935-
28936-#else /* SK_NDIS_64BIT_CTR */
28937-
28938- /* for compatibility, at least 32bit are required for OID */
28939- if (*pLen < sizeof(SK_U32)) {
28940- /*
28941- * but indicate handling for 64bit values,
28942- * if insufficient space is provided
28943- */
28944- *pLen = sizeof(SK_U64);
28945- return (SK_PNMI_ERR_TOO_SHORT);
28946- }
28947-
28948- Is64BitReq = (*pLen < sizeof(SK_U64)) ? SK_FALSE : SK_TRUE;
28949-#endif /* SK_NDIS_64BIT_CTR */
28950- break;
28951- }
28952-
28953- /*
28954- * Update all statistics, because we retrieve virtual MAC, which
28955- * consists of multiple physical statistics and increment semaphore
28956- * to indicate that an update was already done.
28957- */
28958- Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1);
28959- if ( Ret != SK_PNMI_ERR_OK) {
28960-
28961- *pLen = 0;
28962- return (Ret);
28963- }
28964- pAC->Pnmi.MacUpdatedFlag ++;
28965-
28966- /*
28967- * Get value (MAC Index 0 identifies the virtual MAC)
28968- */
28969- switch (Id) {
28970-
28971- case OID_802_3_PERMANENT_ADDRESS:
28972- CopyMac(pBuf, &pAC->Addr.Net[NetIndex].PermanentMacAddress);
28973- *pLen = sizeof(SK_MAC_ADDR);
28974- break;
28975-
28976- case OID_802_3_CURRENT_ADDRESS:
28977- CopyMac(pBuf, &pAC->Addr.Net[NetIndex].CurrentMacAddress);
28978- *pLen = sizeof(SK_MAC_ADDR);
28979- break;
28980-
28981- default:
28982- StatVal = GetStatVal(pAC, IoC, 0, IdTable[TableIndex].Param, NetIndex);
28983-
28984- /* by default 32bit values are evaluated */
28985- if (!Is64BitReq) {
28986- StatVal32 = (SK_U32)StatVal;
28987- SK_PNMI_STORE_U32(pBuf, StatVal32);
28988- *pLen = sizeof(SK_U32);
28989- }
28990- else {
28991- SK_PNMI_STORE_U64(pBuf, StatVal);
28992- *pLen = sizeof(SK_U64);
28993- }
28994- break;
28995- }
28996-
28997- pAC->Pnmi.MacUpdatedFlag --;
28998-
28999- return (SK_PNMI_ERR_OK);
29000-}
29001-
29002-/*****************************************************************************
29003- *
29004- * MacPrivateStat - OID handler function of OID_SKGE_STAT_XXX
29005- *
29006- * Description:
29007- * Retrieves the MAC statistic data.
29008- *
29009- * Returns:
29010- * SK_PNMI_ERR_OK The request was successfully performed.
29011- * SK_PNMI_ERR_GENERAL A general severe internal error occured.
29012- * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
29013- * the correct data (e.g. a 32bit value is
29014- * needed, but a 16 bit value was passed).
29015- * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
29016- * exist (e.g. port instance 3 on a two port
29017- * adapter.
29018- */
29019-PNMI_STATIC int MacPrivateStat(
29020-SK_AC *pAC, /* Pointer to adapter context */
29021-SK_IOC IoC, /* IO context handle */
29022-int Action, /* GET/PRESET/SET action */
29023-SK_U32 Id, /* Object ID that is to be processed */
29024-char *pBuf, /* Buffer used for the management data transfer */
29025-unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */
29026-SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
29027-unsigned int TableIndex, /* Index to the Id table */
29028-SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */
29029-{
29030- unsigned int LogPortMax;
29031- unsigned int LogPortIndex;
29032- unsigned int PhysPortMax;
29033- unsigned int Limit;
29034- unsigned int Offset;
29035- int MacType;
29036- int Ret;
29037- SK_U64 StatVal;
29038-
29039-
29040-
29041- /* Calculate instance if wished. MAC index 0 is the virtual MAC */
29042- PhysPortMax = pAC->GIni.GIMacsFound;
29043- LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax);
29044-
29045- MacType = pAC->GIni.GIMacType;
29046-
29047- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* Dual net mode */
29048- LogPortMax--;
29049- }
29050-
29051- if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried */
29052- /* Check instance range */
29053- if ((Instance < 1) || (Instance > LogPortMax)) {
29054-
29055- *pLen = 0;
29056- return (SK_PNMI_ERR_UNKNOWN_INST);
29057- }
29058- LogPortIndex = SK_PNMI_PORT_INST2LOG(Instance);
29059- Limit = LogPortIndex + 1;
29060- }
29061-
29062- else { /* Instance == (SK_U32)(-1), get all Instances of that OID */
29063-
29064- LogPortIndex = 0;
29065- Limit = LogPortMax;
29066- }
29067-
29068- /* Check action */
29069- if (Action != SK_PNMI_GET) {
29070-
29071- *pLen = 0;
29072- return (SK_PNMI_ERR_READ_ONLY);
29073- }
29074-
29075- /* Check length */
29076- if (*pLen < (Limit - LogPortIndex) * sizeof(SK_U64)) {
29077-
29078- *pLen = (Limit - LogPortIndex) * sizeof(SK_U64);
29079- return (SK_PNMI_ERR_TOO_SHORT);
29080- }
29081-
29082- /*
29083- * Update MAC statistic and increment semaphore to indicate that
29084- * an update was already done.
29085- */
29086- Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1);
29087- if (Ret != SK_PNMI_ERR_OK) {
29088-
29089- *pLen = 0;
29090- return (Ret);
29091- }
29092- pAC->Pnmi.MacUpdatedFlag ++;
29093-
29094- /* Get value */
29095- Offset = 0;
29096- for (; LogPortIndex < Limit; LogPortIndex ++) {
29097-
29098- switch (Id) {
29099-
29100-/* XXX not yet implemented due to XMAC problems
29101- case OID_SKGE_STAT_TX_UTIL:
29102- return (SK_PNMI_ERR_GENERAL);
29103-*/
29104-/* XXX not yet implemented due to XMAC problems
29105- case OID_SKGE_STAT_RX_UTIL:
29106- return (SK_PNMI_ERR_GENERAL);
29107-*/
29108- case OID_SKGE_STAT_RX:
29109- if (MacType == SK_MAC_GMAC) {
29110- StatVal =
29111- GetStatVal(pAC, IoC, LogPortIndex,
29112- SK_PNMI_HRX_BROADCAST, NetIndex) +
29113- GetStatVal(pAC, IoC, LogPortIndex,
29114- SK_PNMI_HRX_MULTICAST, NetIndex) +
29115- GetStatVal(pAC, IoC, LogPortIndex,
29116- SK_PNMI_HRX_UNICAST, NetIndex) +
29117- GetStatVal(pAC, IoC, LogPortIndex,
29118- SK_PNMI_HRX_UNDERSIZE, NetIndex);
29119- }
29120- else {
29121- StatVal = GetStatVal(pAC, IoC, LogPortIndex,
29122- IdTable[TableIndex].Param, NetIndex);
29123- }
29124- break;
29125-
29126- case OID_SKGE_STAT_TX:
29127- if (MacType == SK_MAC_GMAC) {
29128- StatVal =
29129- GetStatVal(pAC, IoC, LogPortIndex,
29130- SK_PNMI_HTX_BROADCAST, NetIndex) +
29131- GetStatVal(pAC, IoC, LogPortIndex,
29132- SK_PNMI_HTX_MULTICAST, NetIndex) +
29133- GetStatVal(pAC, IoC, LogPortIndex,
29134- SK_PNMI_HTX_UNICAST, NetIndex);
29135- }
29136- else {
29137- StatVal = GetStatVal(pAC, IoC, LogPortIndex,
29138- IdTable[TableIndex].Param, NetIndex);
29139- }
29140- break;
29141-
29142- default:
29143- StatVal = GetStatVal(pAC, IoC, LogPortIndex,
29144- IdTable[TableIndex].Param, NetIndex);
29145- }
29146- SK_PNMI_STORE_U64(pBuf + Offset, StatVal);
29147-
29148- Offset += sizeof(SK_U64);
29149- }
29150- *pLen = Offset;
29151-
29152- pAC->Pnmi.MacUpdatedFlag --;
29153-
29154- return (SK_PNMI_ERR_OK);
29155-}
29156-
29157-/*****************************************************************************
29158- *
29159- * Addr - OID handler function of OID_SKGE_PHYS_CUR_ADDR and _FAC_ADDR
29160- *
29161- * Description:
29162- * Get/Presets/Sets the current and factory MAC address. The MAC
29163- * address of the virtual port, which is reported to the OS, may
29164- * not be changed, but the physical ones. A set to the virtual port
29165- * will be ignored. No error should be reported because otherwise
29166- * a multiple instance set (-1) would always fail.
29167- *
29168- * Returns:
29169- * SK_PNMI_ERR_OK The request was successfully performed.
29170- * SK_PNMI_ERR_GENERAL A general severe internal error occured.
29171- * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
29172- * the correct data (e.g. a 32bit value is
29173- * needed, but a 16 bit value was passed).
29174- * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid
29175- * value range.
29176- * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set.
29177- * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
29178- * exist (e.g. port instance 3 on a two port
29179- * adapter.
29180- */
29181-PNMI_STATIC int Addr(
29182-SK_AC *pAC, /* Pointer to adapter context */
29183-SK_IOC IoC, /* IO context handle */
29184-int Action, /* GET/PRESET/SET action */
29185-SK_U32 Id, /* Object ID that is to be processed */
29186-char *pBuf, /* Buffer used for the management data transfer */
29187-unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */
29188-SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
29189-unsigned int TableIndex, /* Index to the Id table */
29190-SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */
29191-{
29192- int Ret;
29193- unsigned int LogPortMax;
29194- unsigned int PhysPortMax;
29195- unsigned int LogPortIndex;
29196- unsigned int PhysPortIndex;
29197- unsigned int Limit;
29198- unsigned int Offset = 0;
29199-
29200- /*
29201- * Calculate instance if wished. MAC index 0 is the virtual
29202- * MAC.
29203- */
29204- PhysPortMax = pAC->GIni.GIMacsFound;
29205- LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax);
29206-
29207- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* Dual net mode */
29208- LogPortMax--;
29209- }
29210-
29211- if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried */
29212- /* Check instance range */
29213- if ((Instance < 1) || (Instance > LogPortMax)) {
29214-
29215- *pLen = 0;
29216- return (SK_PNMI_ERR_UNKNOWN_INST);
29217- }
29218- LogPortIndex = SK_PNMI_PORT_INST2LOG(Instance);
29219- Limit = LogPortIndex + 1;
29220- }
29221- else { /* Instance == (SK_U32)(-1), get all Instances of that OID */
29222-
29223- LogPortIndex = 0;
29224- Limit = LogPortMax;
29225- }
29226-
29227- /*
29228- * Perform Action
29229- */
29230- if (Action == SK_PNMI_GET) {
29231-
29232- /* Check length */
29233- if (*pLen < (Limit - LogPortIndex) * 6) {
29234-
29235- *pLen = (Limit - LogPortIndex) * 6;
29236- return (SK_PNMI_ERR_TOO_SHORT);
29237- }
29238-
29239- /*
29240- * Get value
29241- */
29242- for (; LogPortIndex < Limit; LogPortIndex ++) {
29243-
29244- switch (Id) {
29245-
29246- case OID_SKGE_PHYS_CUR_ADDR:
29247- if (LogPortIndex == 0) {
29248- CopyMac(pBuf + Offset, &pAC->Addr.Net[NetIndex].CurrentMacAddress);
29249- }
29250- else {
29251- PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);
29252-
29253- CopyMac(pBuf + Offset,
29254- &pAC->Addr.Port[PhysPortIndex].CurrentMacAddress);
29255- }
29256- Offset += 6;
29257- break;
29258-
29259- case OID_SKGE_PHYS_FAC_ADDR:
29260- if (LogPortIndex == 0) {
29261- CopyMac(pBuf + Offset,
29262- &pAC->Addr.Net[NetIndex].PermanentMacAddress);
29263- }
29264- else {
29265- PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
29266- pAC, LogPortIndex);
29267-
29268- CopyMac(pBuf + Offset,
29269- &pAC->Addr.Port[PhysPortIndex].PermanentMacAddress);
29270- }
29271- Offset += 6;
29272- break;
29273-
29274- default:
29275- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR008,
29276- SK_PNMI_ERR008MSG);
29277-
29278- *pLen = 0;
29279- return (SK_PNMI_ERR_GENERAL);
29280- }
29281- }
29282-
29283- *pLen = Offset;
29284- }
29285- else {
29286- /*
29287- * The logical MAC address may not be changed only
29288- * the physical ones
29289- */
29290- if (Id == OID_SKGE_PHYS_FAC_ADDR) {
29291-
29292- *pLen = 0;
29293- return (SK_PNMI_ERR_READ_ONLY);
29294- }
29295-
29296- /*
29297- * Only the current address may be changed
29298- */
29299- if (Id != OID_SKGE_PHYS_CUR_ADDR) {
29300-
29301- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR009,
29302- SK_PNMI_ERR009MSG);
29303-
29304- *pLen = 0;
29305- return (SK_PNMI_ERR_GENERAL);
29306- }
29307-
29308- /* Check length */
29309- if (*pLen < (Limit - LogPortIndex) * 6) {
29310-
29311- *pLen = (Limit - LogPortIndex) * 6;
29312- return (SK_PNMI_ERR_TOO_SHORT);
29313- }
29314- if (*pLen > (Limit - LogPortIndex) * 6) {
29315-
29316- *pLen = 0;
29317- return (SK_PNMI_ERR_BAD_VALUE);
29318- }
29319-
29320- /*
29321- * Check Action
29322- */
29323- if (Action == SK_PNMI_PRESET) {
29324-
29325- *pLen = 0;
29326- return (SK_PNMI_ERR_OK);
29327- }
29328-
29329- /*
29330- * Set OID_SKGE_MAC_CUR_ADDR
29331- */
29332- for (; LogPortIndex < Limit; LogPortIndex ++, Offset += 6) {
29333-
29334- /*
29335- * A set to virtual port and set of broadcast
29336- * address will be ignored
29337- */
29338- if (LogPortIndex == 0 || SK_MEMCMP(pBuf + Offset,
29339- "\xff\xff\xff\xff\xff\xff", 6) == 0) {
29340-
29341- continue;
29342- }
29343-
29344- PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC,
29345- LogPortIndex);
29346-
29347- Ret = SkAddrOverride(pAC, IoC, PhysPortIndex,
29348- (SK_MAC_ADDR *)(pBuf + Offset),
29349- (LogPortIndex == 0 ? SK_ADDR_VIRTUAL_ADDRESS :
29350- SK_ADDR_PHYSICAL_ADDRESS));
29351- if (Ret != SK_ADDR_OVERRIDE_SUCCESS) {
29352-
29353- return (SK_PNMI_ERR_GENERAL);
29354- }
29355- }
29356- *pLen = Offset;
29357- }
29358-
29359- return (SK_PNMI_ERR_OK);
29360-}
29361-
29362-/*****************************************************************************
29363- *
29364- * CsumStat - OID handler function of OID_SKGE_CHKSM_XXX
29365- *
29366- * Description:
29367- * Retrieves the statistic values of the CSUM module. The CSUM data
29368- * structure must be available in the SK_AC even if the CSUM module
29369- * is not included, because PNMI reads the statistic data from the
29370- * CSUM part of SK_AC directly.
29371- *
29372- * Returns:
29373- * SK_PNMI_ERR_OK The request was successfully performed.
29374- * SK_PNMI_ERR_GENERAL A general severe internal error occured.
29375- * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
29376- * the correct data (e.g. a 32bit value is
29377- * needed, but a 16 bit value was passed).
29378- * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
29379- * exist (e.g. port instance 3 on a two port
29380- * adapter.
29381- */
29382-PNMI_STATIC int CsumStat(
29383-SK_AC *pAC, /* Pointer to adapter context */
29384-SK_IOC IoC, /* IO context handle */
29385-int Action, /* GET/PRESET/SET action */
29386-SK_U32 Id, /* Object ID that is to be processed */
29387-char *pBuf, /* Buffer used for the management data transfer */
29388-unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */
29389-SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
29390-unsigned int TableIndex, /* Index to the Id table */
29391-SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */
29392-{
29393- unsigned int Index;
29394- unsigned int Limit;
29395- unsigned int Offset = 0;
29396- SK_U64 StatVal;
29397-
29398-
29399- /*
29400- * Calculate instance if wished
29401- */
29402- if (Instance != (SK_U32)(-1)) {
29403-
29404- if ((Instance < 1) || (Instance > SKCS_NUM_PROTOCOLS)) {
29405-
29406- *pLen = 0;
29407- return (SK_PNMI_ERR_UNKNOWN_INST);
29408- }
29409- Index = (unsigned int)Instance - 1;
29410- Limit = Index + 1;
29411- }
29412- else {
29413- Index = 0;
29414- Limit = SKCS_NUM_PROTOCOLS;
29415- }
29416-
29417- /*
29418- * Check action
29419- */
29420- if (Action != SK_PNMI_GET) {
29421-
29422- *pLen = 0;
29423- return (SK_PNMI_ERR_READ_ONLY);
29424- }
29425-
29426- /* Check length */
29427- if (*pLen < (Limit - Index) * sizeof(SK_U64)) {
29428-
29429- *pLen = (Limit - Index) * sizeof(SK_U64);
29430- return (SK_PNMI_ERR_TOO_SHORT);
29431- }
29432-
29433- /*
29434- * Get value
29435- */
29436- for (; Index < Limit; Index ++) {
29437-
29438- switch (Id) {
29439-
29440- case OID_SKGE_CHKSM_RX_OK_CTS:
29441- StatVal = pAC->Csum.ProtoStats[NetIndex][Index].RxOkCts;
29442- break;
29443-
29444- case OID_SKGE_CHKSM_RX_UNABLE_CTS:
29445- StatVal = pAC->Csum.ProtoStats[NetIndex][Index].RxUnableCts;
29446- break;
29447-
29448- case OID_SKGE_CHKSM_RX_ERR_CTS:
29449- StatVal = pAC->Csum.ProtoStats[NetIndex][Index].RxErrCts;
29450- break;
29451-
29452- case OID_SKGE_CHKSM_TX_OK_CTS:
29453- StatVal = pAC->Csum.ProtoStats[NetIndex][Index].TxOkCts;
29454- break;
29455-
29456- case OID_SKGE_CHKSM_TX_UNABLE_CTS:
29457- StatVal = pAC->Csum.ProtoStats[NetIndex][Index].TxUnableCts;
29458- break;
29459-
29460- default:
29461- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR010,
29462- SK_PNMI_ERR010MSG);
29463-
29464- *pLen = 0;
29465- return (SK_PNMI_ERR_GENERAL);
29466- }
29467-
29468- SK_PNMI_STORE_U64(pBuf + Offset, StatVal);
29469- Offset += sizeof(SK_U64);
29470- }
29471-
29472- /*
29473- * Store used buffer space
29474- */
29475- *pLen = Offset;
29476-
29477- return (SK_PNMI_ERR_OK);
29478-}
29479-
29480-/*****************************************************************************
29481- *
29482- * SensorStat - OID handler function of OID_SKGE_SENSOR_XXX
29483- *
29484- * Description:
29485- * Retrieves the statistic values of the I2C module, which handles
29486- * the temperature and voltage sensors.
29487- *
29488- * Returns:
29489- * SK_PNMI_ERR_OK The request was successfully performed.
29490- * SK_PNMI_ERR_GENERAL A general severe internal error occured.
29491- * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
29492- * the correct data (e.g. a 32bit value is
29493- * needed, but a 16 bit value was passed).
29494- * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
29495- * exist (e.g. port instance 3 on a two port
29496- * adapter.
29497- */
29498-PNMI_STATIC int SensorStat(
29499-SK_AC *pAC, /* Pointer to adapter context */
29500-SK_IOC IoC, /* IO context handle */
29501-int Action, /* GET/PRESET/SET action */
29502-SK_U32 Id, /* Object ID that is to be processed */
29503-char *pBuf, /* Buffer used for the management data transfer */
29504-unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */
29505-SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
29506-unsigned int TableIndex, /* Index to the Id table */
29507-SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */
29508-{
29509- unsigned int i;
29510- unsigned int Index;
29511- unsigned int Limit;
29512- unsigned int Offset;
29513- unsigned int Len;
29514- SK_U32 Val32;
29515- SK_U64 Val64;
29516-
29517-
29518- /*
29519- * Calculate instance if wished
29520- */
29521- if ((Instance != (SK_U32)(-1))) {
29522-
29523- if ((Instance < 1) || (Instance > (SK_U32)pAC->I2c.MaxSens)) {
29524-
29525- *pLen = 0;
29526- return (SK_PNMI_ERR_UNKNOWN_INST);
29527- }
29528-
29529- Index = (unsigned int)Instance -1;
29530- Limit = (unsigned int)Instance;
29531- }
29532- else {
29533- Index = 0;
29534- Limit = (unsigned int) pAC->I2c.MaxSens;
29535- }
29536-
29537- /*
29538- * Check action
29539- */
29540- if (Action != SK_PNMI_GET) {
29541-
29542- *pLen = 0;
29543- return (SK_PNMI_ERR_READ_ONLY);
29544- }
29545-
29546- /* Check length */
29547- switch (Id) {
29548-
29549- case OID_SKGE_SENSOR_VALUE:
29550- case OID_SKGE_SENSOR_WAR_THRES_LOW:
29551- case OID_SKGE_SENSOR_WAR_THRES_UPP:
29552- case OID_SKGE_SENSOR_ERR_THRES_LOW:
29553- case OID_SKGE_SENSOR_ERR_THRES_UPP:
29554- if (*pLen < (Limit - Index) * sizeof(SK_U32)) {
29555-
29556- *pLen = (Limit - Index) * sizeof(SK_U32);
29557- return (SK_PNMI_ERR_TOO_SHORT);
29558- }
29559- break;
29560-
29561- case OID_SKGE_SENSOR_DESCR:
29562- for (Offset = 0, i = Index; i < Limit; i ++) {
29563-
29564- Len = (unsigned int)
29565- SK_STRLEN(pAC->I2c.SenTable[i].SenDesc) + 1;
29566- if (Len >= SK_PNMI_STRINGLEN2) {
29567-
29568- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR011,
29569- SK_PNMI_ERR011MSG);
29570-
29571- *pLen = 0;
29572- return (SK_PNMI_ERR_GENERAL);
29573- }
29574- Offset += Len;
29575- }
29576- if (*pLen < Offset) {
29577-
29578- *pLen = Offset;
29579- return (SK_PNMI_ERR_TOO_SHORT);
29580- }
29581- break;
29582-
29583- case OID_SKGE_SENSOR_INDEX:
29584- case OID_SKGE_SENSOR_TYPE:
29585- case OID_SKGE_SENSOR_STATUS:
29586- if (*pLen < Limit - Index) {
29587-
29588- *pLen = Limit - Index;
29589- return (SK_PNMI_ERR_TOO_SHORT);
29590- }
29591- break;
29592-
29593- case OID_SKGE_SENSOR_WAR_CTS:
29594- case OID_SKGE_SENSOR_WAR_TIME:
29595- case OID_SKGE_SENSOR_ERR_CTS:
29596- case OID_SKGE_SENSOR_ERR_TIME:
29597- if (*pLen < (Limit - Index) * sizeof(SK_U64)) {
29598-
29599- *pLen = (Limit - Index) * sizeof(SK_U64);
29600- return (SK_PNMI_ERR_TOO_SHORT);
29601- }
29602- break;
29603-
29604- default:
29605- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR012,
29606- SK_PNMI_ERR012MSG);
29607-
29608- *pLen = 0;
29609- return (SK_PNMI_ERR_GENERAL);
29610-
29611- }
29612-
29613- /*
29614- * Get value
29615- */
29616- for (Offset = 0; Index < Limit; Index ++) {
29617-
29618- switch (Id) {
29619-
29620- case OID_SKGE_SENSOR_INDEX:
29621- *(pBuf + Offset) = (char)Index;
29622- Offset += sizeof(char);
29623- break;
29624-
29625- case OID_SKGE_SENSOR_DESCR:
29626- Len = SK_STRLEN(pAC->I2c.SenTable[Index].SenDesc);
29627- SK_MEMCPY(pBuf + Offset + 1,
29628- pAC->I2c.SenTable[Index].SenDesc, Len);
29629- *(pBuf + Offset) = (char)Len;
29630- Offset += Len + 1;
29631- break;
29632-
29633- case OID_SKGE_SENSOR_TYPE:
29634- *(pBuf + Offset) =
29635- (char)pAC->I2c.SenTable[Index].SenType;
29636- Offset += sizeof(char);
29637- break;
29638-
29639- case OID_SKGE_SENSOR_VALUE:
29640- Val32 = (SK_U32)pAC->I2c.SenTable[Index].SenValue;
29641- SK_PNMI_STORE_U32(pBuf + Offset, Val32);
29642- Offset += sizeof(SK_U32);
29643- break;
29644-
29645- case OID_SKGE_SENSOR_WAR_THRES_LOW:
29646- Val32 = (SK_U32)pAC->I2c.SenTable[Index].
29647- SenThreWarnLow;
29648- SK_PNMI_STORE_U32(pBuf + Offset, Val32);
29649- Offset += sizeof(SK_U32);
29650- break;
29651-
29652- case OID_SKGE_SENSOR_WAR_THRES_UPP:
29653- Val32 = (SK_U32)pAC->I2c.SenTable[Index].
29654- SenThreWarnHigh;
29655- SK_PNMI_STORE_U32(pBuf + Offset, Val32);
29656- Offset += sizeof(SK_U32);
29657- break;
29658-
29659- case OID_SKGE_SENSOR_ERR_THRES_LOW:
29660- Val32 = (SK_U32)pAC->I2c.SenTable[Index].
29661- SenThreErrLow;
29662- SK_PNMI_STORE_U32(pBuf + Offset, Val32);
29663- Offset += sizeof(SK_U32);
29664- break;
29665-
29666- case OID_SKGE_SENSOR_ERR_THRES_UPP:
29667- Val32 = pAC->I2c.SenTable[Index].SenThreErrHigh;
29668- SK_PNMI_STORE_U32(pBuf + Offset, Val32);
29669- Offset += sizeof(SK_U32);
29670- break;
29671-
29672- case OID_SKGE_SENSOR_STATUS:
29673- *(pBuf + Offset) =
29674- (char)pAC->I2c.SenTable[Index].SenErrFlag;
29675- Offset += sizeof(char);
29676- break;
29677-
29678- case OID_SKGE_SENSOR_WAR_CTS:
29679- Val64 = pAC->I2c.SenTable[Index].SenWarnCts;
29680- SK_PNMI_STORE_U64(pBuf + Offset, Val64);
29681- Offset += sizeof(SK_U64);
29682- break;
29683-
29684- case OID_SKGE_SENSOR_ERR_CTS:
29685- Val64 = pAC->I2c.SenTable[Index].SenErrCts;
29686- SK_PNMI_STORE_U64(pBuf + Offset, Val64);
29687- Offset += sizeof(SK_U64);
29688- break;
29689-
29690- case OID_SKGE_SENSOR_WAR_TIME:
29691- Val64 = SK_PNMI_HUNDREDS_SEC(pAC->I2c.SenTable[Index].
29692- SenBegWarnTS);
29693- SK_PNMI_STORE_U64(pBuf + Offset, Val64);
29694- Offset += sizeof(SK_U64);
29695- break;
29696-
29697- case OID_SKGE_SENSOR_ERR_TIME:
29698- Val64 = SK_PNMI_HUNDREDS_SEC(pAC->I2c.SenTable[Index].
29699- SenBegErrTS);
29700- SK_PNMI_STORE_U64(pBuf + Offset, Val64);
29701- Offset += sizeof(SK_U64);
29702- break;
29703-
29704- default:
29705- SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR,
29706- ("SensorStat: Unknown OID should be handled before"));
29707-
29708- return (SK_PNMI_ERR_GENERAL);
29709- }
29710- }
29711-
29712- /*
29713- * Store used buffer space
29714- */
29715- *pLen = Offset;
29716-
29717- return (SK_PNMI_ERR_OK);
29718-}
29719-
29720-/*****************************************************************************
29721- *
29722- * Vpd - OID handler function of OID_SKGE_VPD_XXX
29723- *
29724- * Description:
29725- * Get/preset/set of VPD data. As instance the name of a VPD key
29726- * can be passed. The Instance parameter is a SK_U32 and can be
29727- * used as a string buffer for the VPD key, because their maximum
29728- * length is 4 byte.
29729- *
29730- * Returns:
29731- * SK_PNMI_ERR_OK The request was successfully performed.
29732- * SK_PNMI_ERR_GENERAL A general severe internal error occured.
29733- * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
29734- * the correct data (e.g. a 32bit value is
29735- * needed, but a 16 bit value was passed).
29736- * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid
29737- * value range.
29738- * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set.
29739- * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
29740- * exist (e.g. port instance 3 on a two port
29741- * adapter.
29742- */
29743-PNMI_STATIC int Vpd(
29744-SK_AC *pAC, /* Pointer to adapter context */
29745-SK_IOC IoC, /* IO context handle */
29746-int Action, /* GET/PRESET/SET action */
29747-SK_U32 Id, /* Object ID that is to be processed */
29748-char *pBuf, /* Buffer used for the management data transfer */
29749-unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */
29750-SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
29751-unsigned int TableIndex, /* Index to the Id table */
29752-SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */
29753-{
29754- SK_VPD_STATUS *pVpdStatus;
29755- unsigned int BufLen;
29756- char Buf[256];
29757- char KeyArr[SK_PNMI_VPD_ENTRIES][SK_PNMI_VPD_KEY_SIZE];
29758- char KeyStr[SK_PNMI_VPD_KEY_SIZE];
29759- unsigned int KeyNo;
29760- unsigned int Offset;
29761- unsigned int Index;
29762- unsigned int FirstIndex;
29763- unsigned int LastIndex;
29764- unsigned int Len;
29765- int Ret;
29766- SK_U32 Val32;
29767-
29768- /*
29769- * Get array of all currently stored VPD keys
29770- */
29771- Ret = GetVpdKeyArr(pAC, IoC, &KeyArr[0][0], sizeof(KeyArr), &KeyNo);
29772- if (Ret != SK_PNMI_ERR_OK) {
29773- *pLen = 0;
29774- return (Ret);
29775- }
29776-
29777- /*
29778- * If instance is not -1, try to find the requested VPD key for
29779- * the multiple instance variables. The other OIDs as for example
29780- * OID VPD_ACTION are single instance variables and must be
29781- * handled separatly.
29782- */
29783- FirstIndex = 0;
29784- LastIndex = KeyNo;
29785-
29786- if ((Instance != (SK_U32)(-1))) {
29787-
29788- if (Id == OID_SKGE_VPD_KEY || Id == OID_SKGE_VPD_VALUE ||
29789- Id == OID_SKGE_VPD_ACCESS) {
29790-
29791- SK_STRNCPY(KeyStr, (char *)&Instance, 4);
29792- KeyStr[4] = 0;
29793-
29794- for (Index = 0; Index < KeyNo; Index ++) {
29795-
29796- if (SK_STRCMP(KeyStr, KeyArr[Index]) == 0) {
29797- FirstIndex = Index;
29798- LastIndex = Index+1;
29799- break;
29800- }
29801- }
29802- if (Index == KeyNo) {
29803-
29804- *pLen = 0;
29805- return (SK_PNMI_ERR_UNKNOWN_INST);
29806- }
29807- }
29808- else if (Instance != 1) {
29809-
29810- *pLen = 0;
29811- return (SK_PNMI_ERR_UNKNOWN_INST);
29812- }
29813- }
29814-
29815- /*
29816- * Get value, if a query should be performed
29817- */
29818- if (Action == SK_PNMI_GET) {
29819-
29820- switch (Id) {
29821-
29822- case OID_SKGE_VPD_FREE_BYTES:
29823- /* Check length of buffer */
29824- if (*pLen < sizeof(SK_U32)) {
29825-
29826- *pLen = sizeof(SK_U32);
29827- return (SK_PNMI_ERR_TOO_SHORT);
29828- }
29829- /* Get number of free bytes */
29830- pVpdStatus = VpdStat(pAC, IoC);
29831- if (pVpdStatus == NULL) {
29832-
29833- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR017,
29834- SK_PNMI_ERR017MSG);
29835-
29836- *pLen = 0;
29837- return (SK_PNMI_ERR_GENERAL);
29838- }
29839- if ((pVpdStatus->vpd_status & VPD_VALID) == 0) {
29840-
29841- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR018,
29842- SK_PNMI_ERR018MSG);
29843-
29844- *pLen = 0;
29845- return (SK_PNMI_ERR_GENERAL);
29846- }
29847-
29848- Val32 = (SK_U32)pVpdStatus->vpd_free_rw;
29849- SK_PNMI_STORE_U32(pBuf, Val32);
29850- *pLen = sizeof(SK_U32);
29851- break;
29852-
29853- case OID_SKGE_VPD_ENTRIES_LIST:
29854- /* Check length */
29855- for (Len = 0, Index = 0; Index < KeyNo; Index ++) {
29856-
29857- Len += SK_STRLEN(KeyArr[Index]) + 1;
29858- }
29859- if (*pLen < Len) {
29860-
29861- *pLen = Len;
29862- return (SK_PNMI_ERR_TOO_SHORT);
29863- }
29864-
29865- /* Get value */
29866- *(pBuf) = (char)Len - 1;
29867- for (Offset = 1, Index = 0; Index < KeyNo; Index ++) {
29868-
29869- Len = SK_STRLEN(KeyArr[Index]);
29870- SK_MEMCPY(pBuf + Offset, KeyArr[Index], Len);
29871-
29872- Offset += Len;
29873-
29874- if (Index < KeyNo - 1) {
29875-
29876- *(pBuf + Offset) = ' ';
29877- Offset ++;
29878- }
29879- }
29880- *pLen = Offset;
29881- break;
29882-
29883- case OID_SKGE_VPD_ENTRIES_NUMBER:
29884- /* Check length */
29885- if (*pLen < sizeof(SK_U32)) {
29886-
29887- *pLen = sizeof(SK_U32);
29888- return (SK_PNMI_ERR_TOO_SHORT);
29889- }
29890-
29891- Val32 = (SK_U32)KeyNo;
29892- SK_PNMI_STORE_U32(pBuf, Val32);
29893- *pLen = sizeof(SK_U32);
29894- break;
29895-
29896- case OID_SKGE_VPD_KEY:
29897- /* Check buffer length, if it is large enough */
29898- for (Len = 0, Index = FirstIndex;
29899- Index < LastIndex; Index ++) {
29900-
29901- Len += SK_STRLEN(KeyArr[Index]) + 1;
29902- }
29903- if (*pLen < Len) {
29904-
29905- *pLen = Len;
29906- return (SK_PNMI_ERR_TOO_SHORT);
29907- }
29908-
29909- /*
29910- * Get the key to an intermediate buffer, because
29911- * we have to prepend a length byte.
29912- */
29913- for (Offset = 0, Index = FirstIndex;
29914- Index < LastIndex; Index ++) {
29915-
29916- Len = SK_STRLEN(KeyArr[Index]);
29917-
29918- *(pBuf + Offset) = (char)Len;
29919- SK_MEMCPY(pBuf + Offset + 1, KeyArr[Index],
29920- Len);
29921- Offset += Len + 1;
29922- }
29923- *pLen = Offset;
29924- break;
29925-
29926- case OID_SKGE_VPD_VALUE:
29927- /* Check the buffer length if it is large enough */
29928- for (Offset = 0, Index = FirstIndex;
29929- Index < LastIndex; Index ++) {
29930-
29931- BufLen = 256;
29932- if (VpdRead(pAC, IoC, KeyArr[Index], Buf,
29933- (int *)&BufLen) > 0 ||
29934- BufLen >= SK_PNMI_VPD_DATALEN) {
29935-
29936- SK_ERR_LOG(pAC, SK_ERRCL_SW,
29937- SK_PNMI_ERR021,
29938- SK_PNMI_ERR021MSG);
29939-
29940- return (SK_PNMI_ERR_GENERAL);
29941- }
29942- Offset += BufLen + 1;
29943- }
29944- if (*pLen < Offset) {
29945-
29946- *pLen = Offset;
29947- return (SK_PNMI_ERR_TOO_SHORT);
29948- }
29949-
29950- /*
29951- * Get the value to an intermediate buffer, because
29952- * we have to prepend a length byte.
29953- */
29954- for (Offset = 0, Index = FirstIndex;
29955- Index < LastIndex; Index ++) {
29956-
29957- BufLen = 256;
29958- if (VpdRead(pAC, IoC, KeyArr[Index], Buf,
29959- (int *)&BufLen) > 0 ||
29960- BufLen >= SK_PNMI_VPD_DATALEN) {
29961-
29962- SK_ERR_LOG(pAC, SK_ERRCL_SW,
29963- SK_PNMI_ERR022,
29964- SK_PNMI_ERR022MSG);
29965-
29966- *pLen = 0;
29967- return (SK_PNMI_ERR_GENERAL);
29968- }
29969-
29970- *(pBuf + Offset) = (char)BufLen;
29971- SK_MEMCPY(pBuf + Offset + 1, Buf, BufLen);
29972- Offset += BufLen + 1;
29973- }
29974- *pLen = Offset;
29975- break;
29976-
29977- case OID_SKGE_VPD_ACCESS:
29978- if (*pLen < LastIndex - FirstIndex) {
29979-
29980- *pLen = LastIndex - FirstIndex;
29981- return (SK_PNMI_ERR_TOO_SHORT);
29982- }
29983-
29984- for (Offset = 0, Index = FirstIndex;
29985- Index < LastIndex; Index ++) {
29986-
29987- if (VpdMayWrite(KeyArr[Index])) {
29988-
29989- *(pBuf + Offset) = SK_PNMI_VPD_RW;
29990- }
29991- else {
29992- *(pBuf + Offset) = SK_PNMI_VPD_RO;
29993- }
29994- Offset ++;
29995- }
29996- *pLen = Offset;
29997- break;
29998-
29999- case OID_SKGE_VPD_ACTION:
30000- Offset = LastIndex - FirstIndex;
30001- if (*pLen < Offset) {
30002-
30003- *pLen = Offset;
30004- return (SK_PNMI_ERR_TOO_SHORT);
30005- }
30006- SK_MEMSET(pBuf, 0, Offset);
30007- *pLen = Offset;
30008- break;
30009-
30010- default:
30011- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR023,
30012- SK_PNMI_ERR023MSG);
30013-
30014- *pLen = 0;
30015- return (SK_PNMI_ERR_GENERAL);
30016- }
30017- }
30018- else {
30019- /* The only OID which can be set is VPD_ACTION */
30020- if (Id != OID_SKGE_VPD_ACTION) {
30021-
30022- if (Id == OID_SKGE_VPD_FREE_BYTES ||
30023- Id == OID_SKGE_VPD_ENTRIES_LIST ||
30024- Id == OID_SKGE_VPD_ENTRIES_NUMBER ||
30025- Id == OID_SKGE_VPD_KEY ||
30026- Id == OID_SKGE_VPD_VALUE ||
30027- Id == OID_SKGE_VPD_ACCESS) {
30028-
30029- *pLen = 0;
30030- return (SK_PNMI_ERR_READ_ONLY);
30031- }
30032-
30033- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR024,
30034- SK_PNMI_ERR024MSG);
30035-
30036- *pLen = 0;
30037- return (SK_PNMI_ERR_GENERAL);
30038- }
30039-
30040- /*
30041- * From this point we handle VPD_ACTION. Check the buffer
30042- * length. It should at least have the size of one byte.
30043- */
30044- if (*pLen < 1) {
30045-
30046- *pLen = 1;
30047- return (SK_PNMI_ERR_TOO_SHORT);
30048- }
30049-
30050- /*
30051- * The first byte contains the VPD action type we should
30052- * perform.
30053- */
30054- switch (*pBuf) {
30055-
30056- case SK_PNMI_VPD_IGNORE:
30057- /* Nothing to do */
30058- break;
30059-
30060- case SK_PNMI_VPD_CREATE:
30061- /*
30062- * We have to create a new VPD entry or we modify
30063- * an existing one. Check first the buffer length.
30064- */
30065- if (*pLen < 4) {
30066-
30067- *pLen = 4;
30068- return (SK_PNMI_ERR_TOO_SHORT);
30069- }
30070- KeyStr[0] = pBuf[1];
30071- KeyStr[1] = pBuf[2];
30072- KeyStr[2] = 0;
30073-
30074- /*
30075- * Is the entry writable or does it belong to the
30076- * read-only area?
30077- */
30078- if (!VpdMayWrite(KeyStr)) {
30079-
30080- *pLen = 0;
30081- return (SK_PNMI_ERR_BAD_VALUE);
30082- }
30083-
30084- Offset = (int)pBuf[3] & 0xFF;
30085-
30086- SK_MEMCPY(Buf, pBuf + 4, Offset);
30087- Buf[Offset] = 0;
30088-
30089- /* A preset ends here */
30090- if (Action == SK_PNMI_PRESET) {
30091-
30092- return (SK_PNMI_ERR_OK);
30093- }
30094-
30095- /* Write the new entry or modify an existing one */
30096- Ret = VpdWrite(pAC, IoC, KeyStr, Buf);
30097- if (Ret == SK_PNMI_VPD_NOWRITE ) {
30098-
30099- *pLen = 0;
30100- return (SK_PNMI_ERR_BAD_VALUE);
30101- }
30102- else if (Ret != SK_PNMI_VPD_OK) {
30103-
30104- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR025,
30105- SK_PNMI_ERR025MSG);
30106-
30107- *pLen = 0;
30108- return (SK_PNMI_ERR_GENERAL);
30109- }
30110-
30111- /*
30112- * Perform an update of the VPD data. This is
30113- * not mandantory, but just to be sure.
30114- */
30115- Ret = VpdUpdate(pAC, IoC);
30116- if (Ret != SK_PNMI_VPD_OK) {
30117-
30118- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR026,
30119- SK_PNMI_ERR026MSG);
30120-
30121- *pLen = 0;
30122- return (SK_PNMI_ERR_GENERAL);
30123- }
30124- break;
30125-
30126- case SK_PNMI_VPD_DELETE:
30127- /* Check if the buffer size is plausible */
30128- if (*pLen < 3) {
30129-
30130- *pLen = 3;
30131- return (SK_PNMI_ERR_TOO_SHORT);
30132- }
30133- if (*pLen > 3) {
30134-
30135- *pLen = 0;
30136- return (SK_PNMI_ERR_BAD_VALUE);
30137- }
30138- KeyStr[0] = pBuf[1];
30139- KeyStr[1] = pBuf[2];
30140- KeyStr[2] = 0;
30141-
30142- /* Find the passed key in the array */
30143- for (Index = 0; Index < KeyNo; Index ++) {
30144-
30145- if (SK_STRCMP(KeyStr, KeyArr[Index]) == 0) {
30146-
30147- break;
30148- }
30149- }
30150- /*
30151- * If we cannot find the key it is wrong, so we
30152- * return an appropriate error value.
30153- */
30154- if (Index == KeyNo) {
30155-
30156- *pLen = 0;
30157- return (SK_PNMI_ERR_BAD_VALUE);
30158- }
30159-
30160- if (Action == SK_PNMI_PRESET) {
30161-
30162- return (SK_PNMI_ERR_OK);
30163- }
30164-
30165- /* Ok, you wanted it and you will get it */
30166- Ret = VpdDelete(pAC, IoC, KeyStr);
30167- if (Ret != SK_PNMI_VPD_OK) {
30168-
30169- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR027,
30170- SK_PNMI_ERR027MSG);
30171-
30172- *pLen = 0;
30173- return (SK_PNMI_ERR_GENERAL);
30174- }
30175-
30176- /*
30177- * Perform an update of the VPD data. This is
30178- * not mandantory, but just to be sure.
30179- */
30180- Ret = VpdUpdate(pAC, IoC);
30181- if (Ret != SK_PNMI_VPD_OK) {
30182-
30183- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR028,
30184- SK_PNMI_ERR028MSG);
30185-
30186- *pLen = 0;
30187- return (SK_PNMI_ERR_GENERAL);
30188- }
30189- break;
30190-
30191- default:
30192- *pLen = 0;
30193- return (SK_PNMI_ERR_BAD_VALUE);
30194- }
30195- }
30196-
30197- return (SK_PNMI_ERR_OK);
30198-}
30199-
30200-/*****************************************************************************
30201- *
30202- * General - OID handler function of various single instance OIDs
30203- *
30204- * Description:
30205- * The code is simple. No description necessary.
30206- *
30207- * Returns:
30208- * SK_PNMI_ERR_OK The request was successfully performed.
30209- * SK_PNMI_ERR_GENERAL A general severe internal error occured.
30210- * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
30211- * the correct data (e.g. a 32bit value is
30212- * needed, but a 16 bit value was passed).
30213- * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
30214- * exist (e.g. port instance 3 on a two port
30215- * adapter.
30216- */
30217-PNMI_STATIC int General(
30218-SK_AC *pAC, /* Pointer to adapter context */
30219-SK_IOC IoC, /* IO context handle */
30220-int Action, /* GET/PRESET/SET action */
30221-SK_U32 Id, /* Object ID that is to be processed */
30222-char *pBuf, /* Buffer used for the management data transfer */
30223-unsigned int *pLen, /* On call: buffer length. On return: used buffer */
30224-SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
30225-unsigned int TableIndex, /* Index to the Id table */
30226-SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */
30227-{
30228- int Ret;
30229- unsigned int Index;
30230- unsigned int Len;
30231- unsigned int Offset;
30232- unsigned int Val;
30233- SK_U8 Val8;
30234- SK_U16 Val16;
30235- SK_U32 Val32;
30236- SK_U64 Val64;
30237- SK_U64 Val64RxHwErrs = 0;
30238- SK_U64 Val64TxHwErrs = 0;
30239- SK_BOOL Is64BitReq = SK_FALSE;
30240- char Buf[256];
30241- int MacType;
30242-
30243- /*
30244- * Check instance. We only handle single instance variables.
30245- */
30246- if (Instance != (SK_U32)(-1) && Instance != 1) {
30247-
30248- *pLen = 0;
30249- return (SK_PNMI_ERR_UNKNOWN_INST);
30250- }
30251-
30252- /*
30253- * Check action. We only allow get requests.
30254- */
30255- if (Action != SK_PNMI_GET) {
30256-
30257- *pLen = 0;
30258- return (SK_PNMI_ERR_READ_ONLY);
30259- }
30260-
30261- MacType = pAC->GIni.GIMacType;
30262-
30263- /*
30264- * Check length for the various supported OIDs
30265- */
30266- switch (Id) {
30267-
30268- case OID_GEN_XMIT_ERROR:
30269- case OID_GEN_RCV_ERROR:
30270- case OID_GEN_RCV_NO_BUFFER:
30271-#ifndef SK_NDIS_64BIT_CTR
30272- if (*pLen < sizeof(SK_U32)) {
30273- *pLen = sizeof(SK_U32);
30274- return (SK_PNMI_ERR_TOO_SHORT);
30275- }
30276-
30277-#else /* SK_NDIS_64BIT_CTR */
30278-
30279- /*
30280- * for compatibility, at least 32bit are required for oid
30281- */
30282- if (*pLen < sizeof(SK_U32)) {
30283- /*
30284- * but indicate handling for 64bit values,
30285- * if insufficient space is provided
30286- */
30287- *pLen = sizeof(SK_U64);
30288- return (SK_PNMI_ERR_TOO_SHORT);
30289- }
30290-
30291- Is64BitReq = (*pLen < sizeof(SK_U64)) ? SK_FALSE : SK_TRUE;
30292-#endif /* SK_NDIS_64BIT_CTR */
30293- break;
30294-
30295- case OID_SKGE_PORT_NUMBER:
30296- case OID_SKGE_DEVICE_TYPE:
30297- case OID_SKGE_RESULT:
30298- case OID_SKGE_RLMT_MONITOR_NUMBER:
30299- case OID_GEN_TRANSMIT_QUEUE_LENGTH:
30300- case OID_SKGE_TRAP_NUMBER:
30301- case OID_SKGE_MDB_VERSION:
30302- case OID_SKGE_BOARDLEVEL:
30303- case OID_SKGE_CHIPID:
30304- case OID_SKGE_RAMSIZE:
30305- if (*pLen < sizeof(SK_U32)) {
30306-
30307- *pLen = sizeof(SK_U32);
30308- return (SK_PNMI_ERR_TOO_SHORT);
30309- }
30310- break;
30311-
30312- case OID_SKGE_CHIPSET:
30313- if (*pLen < sizeof(SK_U16)) {
30314-
30315- *pLen = sizeof(SK_U16);
30316- return (SK_PNMI_ERR_TOO_SHORT);
30317- }
30318- break;
30319-
30320- case OID_SKGE_BUS_TYPE:
30321- case OID_SKGE_BUS_SPEED:
30322- case OID_SKGE_BUS_WIDTH:
30323- case OID_SKGE_SENSOR_NUMBER:
30324- case OID_SKGE_CHKSM_NUMBER:
30325- case OID_SKGE_VAUXAVAIL:
30326- if (*pLen < sizeof(SK_U8)) {
30327-
30328- *pLen = sizeof(SK_U8);
30329- return (SK_PNMI_ERR_TOO_SHORT);
30330- }
30331- break;
30332-
30333- case OID_SKGE_TX_SW_QUEUE_LEN:
30334- case OID_SKGE_TX_SW_QUEUE_MAX:
30335- case OID_SKGE_TX_RETRY:
30336- case OID_SKGE_RX_INTR_CTS:
30337- case OID_SKGE_TX_INTR_CTS:
30338- case OID_SKGE_RX_NO_BUF_CTS:
30339- case OID_SKGE_TX_NO_BUF_CTS:
30340- case OID_SKGE_TX_USED_DESCR_NO:
30341- case OID_SKGE_RX_DELIVERED_CTS:
30342- case OID_SKGE_RX_OCTETS_DELIV_CTS:
30343- case OID_SKGE_RX_HW_ERROR_CTS:
30344- case OID_SKGE_TX_HW_ERROR_CTS:
30345- case OID_SKGE_IN_ERRORS_CTS:
30346- case OID_SKGE_OUT_ERROR_CTS:
30347- case OID_SKGE_ERR_RECOVERY_CTS:
30348- case OID_SKGE_SYSUPTIME:
30349- if (*pLen < sizeof(SK_U64)) {
30350-
30351- *pLen = sizeof(SK_U64);
30352- return (SK_PNMI_ERR_TOO_SHORT);
30353- }
30354- break;
30355-
30356- default:
30357- /* Checked later */
30358- break;
30359- }
30360-
30361- /* Update statistic */
30362- if (Id == OID_SKGE_RX_HW_ERROR_CTS ||
30363- Id == OID_SKGE_TX_HW_ERROR_CTS ||
30364- Id == OID_SKGE_IN_ERRORS_CTS ||
30365- Id == OID_SKGE_OUT_ERROR_CTS ||
30366- Id == OID_GEN_XMIT_ERROR ||
30367- Id == OID_GEN_RCV_ERROR) {
30368-
30369- /* Force the XMAC to update its statistic counters and
30370- * Increment semaphore to indicate that an update was
30371- * already done.
30372- */
30373- Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1);
30374- if (Ret != SK_PNMI_ERR_OK) {
30375-
30376- *pLen = 0;
30377- return (Ret);
30378- }
30379- pAC->Pnmi.MacUpdatedFlag ++;
30380-
30381- /*
30382- * Some OIDs consist of multiple hardware counters. Those
30383- * values which are contained in all of them will be added
30384- * now.
30385- */
30386- switch (Id) {
30387-
30388- case OID_SKGE_RX_HW_ERROR_CTS:
30389- case OID_SKGE_IN_ERRORS_CTS:
30390- case OID_GEN_RCV_ERROR:
30391- Val64RxHwErrs =
30392- GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_MISSED, NetIndex) +
30393- GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_FRAMING, NetIndex) +
30394- GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_OVERFLOW, NetIndex) +
30395- GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_JABBER, NetIndex) +
30396- GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_CARRIER, NetIndex) +
30397- GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_IRLENGTH, NetIndex) +
30398- GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_SYMBOL, NetIndex) +
30399- GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_SHORTS, NetIndex) +
30400- GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_RUNT, NetIndex) +
30401- GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_TOO_LONG, NetIndex) +
30402- GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_FCS, NetIndex) +
30403- GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_CEXT, NetIndex);
30404- break;
30405-
30406- case OID_SKGE_TX_HW_ERROR_CTS:
30407- case OID_SKGE_OUT_ERROR_CTS:
30408- case OID_GEN_XMIT_ERROR:
30409- Val64TxHwErrs =
30410- GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_EXCESS_COL, NetIndex) +
30411- GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_LATE_COL, NetIndex) +
30412- GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_UNDERRUN, NetIndex) +
30413- GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_CARRIER, NetIndex);
30414- break;
30415- }
30416- }
30417-
30418- /*
30419- * Retrieve value
30420- */
30421- switch (Id) {
30422-
30423- case OID_SKGE_SUPPORTED_LIST:
30424- Len = ID_TABLE_SIZE * sizeof(SK_U32);
30425- if (*pLen < Len) {
30426-
30427- *pLen = Len;
30428- return (SK_PNMI_ERR_TOO_SHORT);
30429- }
30430- for (Offset = 0, Index = 0; Offset < Len;
30431- Offset += sizeof(SK_U32), Index ++) {
30432-
30433- Val32 = (SK_U32)IdTable[Index].Id;
30434- SK_PNMI_STORE_U32(pBuf + Offset, Val32);
30435- }
30436- *pLen = Len;
30437- break;
30438-
30439- case OID_SKGE_BOARDLEVEL:
30440- Val32 = (SK_U32)pAC->GIni.GILevel;
30441- SK_PNMI_STORE_U32(pBuf, Val32);
30442- *pLen = sizeof(SK_U32);
30443- break;
30444-
30445- case OID_SKGE_PORT_NUMBER:
30446- Val32 = (SK_U32)pAC->GIni.GIMacsFound;
30447- SK_PNMI_STORE_U32(pBuf, Val32);
30448- *pLen = sizeof(SK_U32);
30449- break;
30450-
30451- case OID_SKGE_DEVICE_TYPE:
30452- Val32 = (SK_U32)pAC->Pnmi.DeviceType;
30453- SK_PNMI_STORE_U32(pBuf, Val32);
30454- *pLen = sizeof(SK_U32);
30455- break;
30456-
30457- case OID_SKGE_DRIVER_DESCR:
30458- if (pAC->Pnmi.pDriverDescription == NULL) {
30459-
30460- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR007,
30461- SK_PNMI_ERR007MSG);
30462-
30463- *pLen = 0;
30464- return (SK_PNMI_ERR_GENERAL);
30465- }
30466-
30467- Len = SK_STRLEN(pAC->Pnmi.pDriverDescription) + 1;
30468- if (Len > SK_PNMI_STRINGLEN1) {
30469-
30470- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR029,
30471- SK_PNMI_ERR029MSG);
30472-
30473- *pLen = 0;
30474- return (SK_PNMI_ERR_GENERAL);
30475- }
30476-
30477- if (*pLen < Len) {
30478-
30479- *pLen = Len;
30480- return (SK_PNMI_ERR_TOO_SHORT);
30481- }
30482- *pBuf = (char)(Len - 1);
30483- SK_MEMCPY(pBuf + 1, pAC->Pnmi.pDriverDescription, Len - 1);
30484- *pLen = Len;
30485- break;
30486-
30487- case OID_SKGE_DRIVER_VERSION:
30488- if (pAC->Pnmi.pDriverVersion == NULL) {
30489-
30490- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR030,
30491- SK_PNMI_ERR030MSG);
30492-
30493- *pLen = 0;
30494- return (SK_PNMI_ERR_GENERAL);
30495- }
30496-
30497- Len = SK_STRLEN(pAC->Pnmi.pDriverVersion) + 1;
30498- if (Len > SK_PNMI_STRINGLEN1) {
30499-
30500- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR031,
30501- SK_PNMI_ERR031MSG);
30502-
30503- *pLen = 0;
30504- return (SK_PNMI_ERR_GENERAL);
30505- }
30506-
30507- if (*pLen < Len) {
30508-
30509- *pLen = Len;
30510- return (SK_PNMI_ERR_TOO_SHORT);
30511- }
30512- *pBuf = (char)(Len - 1);
30513- SK_MEMCPY(pBuf + 1, pAC->Pnmi.pDriverVersion, Len - 1);
30514- *pLen = Len;
30515- break;
30516-
30517- case OID_SKGE_DRIVER_RELDATE:
30518- if (pAC->Pnmi.pDriverReleaseDate == NULL) {
30519-
30520- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR030,
30521- SK_PNMI_ERR053MSG);
30522-
30523- *pLen = 0;
30524- return (SK_PNMI_ERR_GENERAL);
30525- }
30526-
30527- Len = SK_STRLEN(pAC->Pnmi.pDriverReleaseDate) + 1;
30528- if (Len > SK_PNMI_STRINGLEN1) {
30529-
30530- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR031,
30531- SK_PNMI_ERR054MSG);
30532-
30533- *pLen = 0;
30534- return (SK_PNMI_ERR_GENERAL);
30535- }
30536-
30537- if (*pLen < Len) {
30538-
30539- *pLen = Len;
30540- return (SK_PNMI_ERR_TOO_SHORT);
30541- }
30542- *pBuf = (char)(Len - 1);
30543- SK_MEMCPY(pBuf + 1, pAC->Pnmi.pDriverReleaseDate, Len - 1);
30544- *pLen = Len;
30545- break;
30546-
30547- case OID_SKGE_DRIVER_FILENAME:
30548- if (pAC->Pnmi.pDriverFileName == NULL) {
30549-
30550- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR030,
30551- SK_PNMI_ERR055MSG);
30552-
30553- *pLen = 0;
30554- return (SK_PNMI_ERR_GENERAL);
30555- }
30556-
30557- Len = SK_STRLEN(pAC->Pnmi.pDriverFileName) + 1;
30558- if (Len > SK_PNMI_STRINGLEN1) {
30559-
30560- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR031,
30561- SK_PNMI_ERR056MSG);
30562-
30563- *pLen = 0;
30564- return (SK_PNMI_ERR_GENERAL);
30565- }
30566-
30567- if (*pLen < Len) {
30568-
30569- *pLen = Len;
30570- return (SK_PNMI_ERR_TOO_SHORT);
30571- }
30572- *pBuf = (char)(Len - 1);
30573- SK_MEMCPY(pBuf + 1, pAC->Pnmi.pDriverFileName, Len - 1);
30574- *pLen = Len;
30575- break;
30576-
30577- case OID_SKGE_HW_DESCR:
30578- /*
30579- * The hardware description is located in the VPD. This
30580- * query may move to the initialisation routine. But
30581- * the VPD data is cached and therefore a call here
30582- * will not make much difference.
30583- */
30584- Len = 256;
30585- if (VpdRead(pAC, IoC, VPD_NAME, Buf, (int *)&Len) > 0) {
30586-
30587- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR032,
30588- SK_PNMI_ERR032MSG);
30589-
30590- *pLen = 0;
30591- return (SK_PNMI_ERR_GENERAL);
30592- }
30593- Len ++;
30594- if (Len > SK_PNMI_STRINGLEN1) {
30595-
30596- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR033,
30597- SK_PNMI_ERR033MSG);
30598-
30599- *pLen = 0;
30600- return (SK_PNMI_ERR_GENERAL);
30601- }
30602- if (*pLen < Len) {
30603-
30604- *pLen = Len;
30605- return (SK_PNMI_ERR_TOO_SHORT);
30606- }
30607- *pBuf = (char)(Len - 1);
30608- SK_MEMCPY(pBuf + 1, Buf, Len - 1);
30609- *pLen = Len;
30610- break;
30611-
30612- case OID_SKGE_HW_VERSION:
30613- /* Oh, I love to do some string manipulation */
30614- if (*pLen < 5) {
30615-
30616- *pLen = 5;
30617- return (SK_PNMI_ERR_TOO_SHORT);
30618- }
30619- Val8 = (SK_U8)pAC->GIni.GIPciHwRev;
30620- pBuf[0] = 4;
30621- pBuf[1] = 'v';
30622- pBuf[2] = (char)(0x30 | ((Val8 >> 4) & 0x0F));
30623- pBuf[3] = '.';
30624- pBuf[4] = (char)(0x30 | (Val8 & 0x0F));
30625- *pLen = 5;
30626- break;
30627-
30628- case OID_SKGE_CHIPSET:
30629- Val16 = pAC->Pnmi.Chipset;
30630- SK_PNMI_STORE_U16(pBuf, Val16);
30631- *pLen = sizeof(SK_U16);
30632- break;
30633-
30634- case OID_SKGE_CHIPID:
30635- Val32 = pAC->GIni.GIChipId;
30636- SK_PNMI_STORE_U32(pBuf, Val32);
30637- *pLen = sizeof(SK_U32);
30638- break;
30639-
30640- case OID_SKGE_RAMSIZE:
30641- Val32 = pAC->GIni.GIRamSize;
30642- SK_PNMI_STORE_U32(pBuf, Val32);
30643- *pLen = sizeof(SK_U32);
30644- break;
30645-
30646- case OID_SKGE_VAUXAVAIL:
30647- *pBuf = (char) pAC->GIni.GIVauxAvail;
30648- *pLen = sizeof(char);
30649- break;
30650-
30651- case OID_SKGE_BUS_TYPE:
30652- *pBuf = (char) SK_PNMI_BUS_PCI;
30653- *pLen = sizeof(char);
30654- break;
30655-
30656- case OID_SKGE_BUS_SPEED:
30657- *pBuf = pAC->Pnmi.PciBusSpeed;
30658- *pLen = sizeof(char);
30659- break;
30660-
30661- case OID_SKGE_BUS_WIDTH:
30662- *pBuf = pAC->Pnmi.PciBusWidth;
30663- *pLen = sizeof(char);
30664- break;
30665-
30666- case OID_SKGE_RESULT:
30667- Val32 = pAC->Pnmi.TestResult;
30668- SK_PNMI_STORE_U32(pBuf, Val32);
30669- *pLen = sizeof(SK_U32);
30670- break;
30671-
30672- case OID_SKGE_SENSOR_NUMBER:
30673- *pBuf = (char)pAC->I2c.MaxSens;
30674- *pLen = sizeof(char);
30675- break;
30676-
30677- case OID_SKGE_CHKSM_NUMBER:
30678- *pBuf = SKCS_NUM_PROTOCOLS;
30679- *pLen = sizeof(char);
30680- break;
30681-
30682- case OID_SKGE_TRAP_NUMBER:
30683- GetTrapQueueLen(pAC, &Len, &Val);
30684- Val32 = (SK_U32)Val;
30685- SK_PNMI_STORE_U32(pBuf, Val32);
30686- *pLen = sizeof(SK_U32);
30687- break;
30688-
30689- case OID_SKGE_TRAP:
30690- GetTrapQueueLen(pAC, &Len, &Val);
30691- if (*pLen < Len) {
30692-
30693- *pLen = Len;
30694- return (SK_PNMI_ERR_TOO_SHORT);
30695- }
30696- CopyTrapQueue(pAC, pBuf);
30697- *pLen = Len;
30698- break;
30699-
30700- case OID_SKGE_RLMT_MONITOR_NUMBER:
30701-/* XXX Not yet implemented by RLMT therefore we return zero elements */
30702- Val32 = 0;
30703- SK_PNMI_STORE_U32(pBuf, Val32);
30704- *pLen = sizeof(SK_U32);
30705- break;
30706-
30707- case OID_SKGE_TX_SW_QUEUE_LEN:
30708- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
30709- if (MacType == SK_MAC_XMAC) {
30710- /* Dual net mode */
30711- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
30712- Val64 = pAC->Pnmi.BufPort[NetIndex].TxSwQueueLen;
30713- }
30714- /* Single net mode */
30715- else {
30716- Val64 = pAC->Pnmi.BufPort[0].TxSwQueueLen +
30717- pAC->Pnmi.BufPort[1].TxSwQueueLen;
30718- }
30719- }
30720- else {
30721- /* Dual net mode */
30722- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
30723- Val64 = pAC->Pnmi.Port[NetIndex].TxSwQueueLen;
30724- }
30725- /* Single net mode */
30726- else {
30727- Val64 = pAC->Pnmi.Port[0].TxSwQueueLen +
30728- pAC->Pnmi.Port[1].TxSwQueueLen;
30729- }
30730- }
30731- SK_PNMI_STORE_U64(pBuf, Val64);
30732- *pLen = sizeof(SK_U64);
30733- break;
30734-
30735-
30736- case OID_SKGE_TX_SW_QUEUE_MAX:
30737- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
30738- if (MacType == SK_MAC_XMAC) {
30739- /* Dual net mode */
30740- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
30741- Val64 = pAC->Pnmi.BufPort[NetIndex].TxSwQueueMax;
30742- }
30743- /* Single net mode */
30744- else {
30745- Val64 = pAC->Pnmi.BufPort[0].TxSwQueueMax +
30746- pAC->Pnmi.BufPort[1].TxSwQueueMax;
30747- }
30748- }
30749- else {
30750- /* Dual net mode */
30751- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
30752- Val64 = pAC->Pnmi.Port[NetIndex].TxSwQueueMax;
30753- }
30754- /* Single net mode */
30755- else {
30756- Val64 = pAC->Pnmi.Port[0].TxSwQueueMax +
30757- pAC->Pnmi.Port[1].TxSwQueueMax;
30758- }
30759- }
30760- SK_PNMI_STORE_U64(pBuf, Val64);
30761- *pLen = sizeof(SK_U64);
30762- break;
30763-
30764- case OID_SKGE_TX_RETRY:
30765- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
30766- if (MacType == SK_MAC_XMAC) {
30767- /* Dual net mode */
30768- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
30769- Val64 = pAC->Pnmi.BufPort[NetIndex].TxRetryCts;
30770- }
30771- /* Single net mode */
30772- else {
30773- Val64 = pAC->Pnmi.BufPort[0].TxRetryCts +
30774- pAC->Pnmi.BufPort[1].TxRetryCts;
30775- }
30776- }
30777- else {
30778- /* Dual net mode */
30779- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
30780- Val64 = pAC->Pnmi.Port[NetIndex].TxRetryCts;
30781- }
30782- /* Single net mode */
30783- else {
30784- Val64 = pAC->Pnmi.Port[0].TxRetryCts +
30785- pAC->Pnmi.Port[1].TxRetryCts;
30786- }
30787- }
30788- SK_PNMI_STORE_U64(pBuf, Val64);
30789- *pLen = sizeof(SK_U64);
30790- break;
30791-
30792- case OID_SKGE_RX_INTR_CTS:
30793- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
30794- if (MacType == SK_MAC_XMAC) {
30795- /* Dual net mode */
30796- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
30797- Val64 = pAC->Pnmi.BufPort[NetIndex].RxIntrCts;
30798- }
30799- /* Single net mode */
30800- else {
30801- Val64 = pAC->Pnmi.BufPort[0].RxIntrCts +
30802- pAC->Pnmi.BufPort[1].RxIntrCts;
30803- }
30804- }
30805- else {
30806- /* Dual net mode */
30807- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
30808- Val64 = pAC->Pnmi.Port[NetIndex].RxIntrCts;
30809- }
30810- /* Single net mode */
30811- else {
30812- Val64 = pAC->Pnmi.Port[0].RxIntrCts +
30813- pAC->Pnmi.Port[1].RxIntrCts;
30814- }
30815- }
30816- SK_PNMI_STORE_U64(pBuf, Val64);
30817- *pLen = sizeof(SK_U64);
30818- break;
30819-
30820- case OID_SKGE_TX_INTR_CTS:
30821- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
30822- if (MacType == SK_MAC_XMAC) {
30823- /* Dual net mode */
30824- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
30825- Val64 = pAC->Pnmi.BufPort[NetIndex].TxIntrCts;
30826- }
30827- /* Single net mode */
30828- else {
30829- Val64 = pAC->Pnmi.BufPort[0].TxIntrCts +
30830- pAC->Pnmi.BufPort[1].TxIntrCts;
30831- }
30832- }
30833- else {
30834- /* Dual net mode */
30835- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
30836- Val64 = pAC->Pnmi.Port[NetIndex].TxIntrCts;
30837- }
30838- /* Single net mode */
30839- else {
30840- Val64 = pAC->Pnmi.Port[0].TxIntrCts +
30841- pAC->Pnmi.Port[1].TxIntrCts;
30842- }
30843- }
30844- SK_PNMI_STORE_U64(pBuf, Val64);
30845- *pLen = sizeof(SK_U64);
30846- break;
30847-
30848- case OID_SKGE_RX_NO_BUF_CTS:
30849- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
30850- if (MacType == SK_MAC_XMAC) {
30851- /* Dual net mode */
30852- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
30853- Val64 = pAC->Pnmi.BufPort[NetIndex].RxNoBufCts;
30854- }
30855- /* Single net mode */
30856- else {
30857- Val64 = pAC->Pnmi.BufPort[0].RxNoBufCts +
30858- pAC->Pnmi.BufPort[1].RxNoBufCts;
30859- }
30860- }
30861- else {
30862- /* Dual net mode */
30863- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
30864- Val64 = pAC->Pnmi.Port[NetIndex].RxNoBufCts;
30865- }
30866- /* Single net mode */
30867- else {
30868- Val64 = pAC->Pnmi.Port[0].RxNoBufCts +
30869- pAC->Pnmi.Port[1].RxNoBufCts;
30870- }
30871- }
30872- SK_PNMI_STORE_U64(pBuf, Val64);
30873- *pLen = sizeof(SK_U64);
30874- break;
30875-
30876- case OID_SKGE_TX_NO_BUF_CTS:
30877- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
30878- if (MacType == SK_MAC_XMAC) {
30879- /* Dual net mode */
30880- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
30881- Val64 = pAC->Pnmi.BufPort[NetIndex].TxNoBufCts;
30882- }
30883- /* Single net mode */
30884- else {
30885- Val64 = pAC->Pnmi.BufPort[0].TxNoBufCts +
30886- pAC->Pnmi.BufPort[1].TxNoBufCts;
30887- }
30888- }
30889- else {
30890- /* Dual net mode */
30891- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
30892- Val64 = pAC->Pnmi.Port[NetIndex].TxNoBufCts;
30893- }
30894- /* Single net mode */
30895- else {
30896- Val64 = pAC->Pnmi.Port[0].TxNoBufCts +
30897- pAC->Pnmi.Port[1].TxNoBufCts;
30898- }
30899- }
30900- SK_PNMI_STORE_U64(pBuf, Val64);
30901- *pLen = sizeof(SK_U64);
30902- break;
30903-
30904- case OID_SKGE_TX_USED_DESCR_NO:
30905- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
30906- if (MacType == SK_MAC_XMAC) {
30907- /* Dual net mode */
30908- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
30909- Val64 = pAC->Pnmi.BufPort[NetIndex].TxUsedDescrNo;
30910- }
30911- /* Single net mode */
30912- else {
30913- Val64 = pAC->Pnmi.BufPort[0].TxUsedDescrNo +
30914- pAC->Pnmi.BufPort[1].TxUsedDescrNo;
30915- }
30916- }
30917- else {
30918- /* Dual net mode */
30919- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
30920- Val64 = pAC->Pnmi.Port[NetIndex].TxUsedDescrNo;
30921- }
30922- /* Single net mode */
30923- else {
30924- Val64 = pAC->Pnmi.Port[0].TxUsedDescrNo +
30925- pAC->Pnmi.Port[1].TxUsedDescrNo;
30926- }
30927- }
30928- SK_PNMI_STORE_U64(pBuf, Val64);
30929- *pLen = sizeof(SK_U64);
30930- break;
30931-
30932- case OID_SKGE_RX_DELIVERED_CTS:
30933- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
30934- if (MacType == SK_MAC_XMAC) {
30935- /* Dual net mode */
30936- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
30937- Val64 = pAC->Pnmi.BufPort[NetIndex].RxDeliveredCts;
30938- }
30939- /* Single net mode */
30940- else {
30941- Val64 = pAC->Pnmi.BufPort[0].RxDeliveredCts +
30942- pAC->Pnmi.BufPort[1].RxDeliveredCts;
30943- }
30944- }
30945- else {
30946- /* Dual net mode */
30947- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
30948- Val64 = pAC->Pnmi.Port[NetIndex].RxDeliveredCts;
30949- }
30950- /* Single net mode */
30951- else {
30952- Val64 = pAC->Pnmi.Port[0].RxDeliveredCts +
30953- pAC->Pnmi.Port[1].RxDeliveredCts;
30954- }
30955- }
30956- SK_PNMI_STORE_U64(pBuf, Val64);
30957- *pLen = sizeof(SK_U64);
30958- break;
30959-
30960- case OID_SKGE_RX_OCTETS_DELIV_CTS:
30961- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
30962- if (MacType == SK_MAC_XMAC) {
30963- /* Dual net mode */
30964- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
30965- Val64 = pAC->Pnmi.BufPort[NetIndex].RxOctetsDeliveredCts;
30966- }
30967- /* Single net mode */
30968- else {
30969- Val64 = pAC->Pnmi.BufPort[0].RxOctetsDeliveredCts +
30970- pAC->Pnmi.BufPort[1].RxOctetsDeliveredCts;
30971- }
30972- }
30973- else {
30974- /* Dual net mode */
30975- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
30976- Val64 = pAC->Pnmi.Port[NetIndex].RxOctetsDeliveredCts;
30977- }
30978- /* Single net mode */
30979- else {
30980- Val64 = pAC->Pnmi.Port[0].RxOctetsDeliveredCts +
30981- pAC->Pnmi.Port[1].RxOctetsDeliveredCts;
30982- }
30983- }
30984- SK_PNMI_STORE_U64(pBuf, Val64);
30985- *pLen = sizeof(SK_U64);
30986- break;
30987-
30988- case OID_SKGE_RX_HW_ERROR_CTS:
30989- SK_PNMI_STORE_U64(pBuf, Val64RxHwErrs);
30990- *pLen = sizeof(SK_U64);
30991- break;
30992-
30993- case OID_SKGE_TX_HW_ERROR_CTS:
30994- SK_PNMI_STORE_U64(pBuf, Val64TxHwErrs);
30995- *pLen = sizeof(SK_U64);
30996- break;
30997-
30998- case OID_SKGE_IN_ERRORS_CTS:
30999- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
31000- if (MacType == SK_MAC_XMAC) {
31001- /* Dual net mode */
31002- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
31003- Val64 = Val64RxHwErrs + pAC->Pnmi.BufPort[NetIndex].RxNoBufCts;
31004- }
31005- /* Single net mode */
31006- else {
31007- Val64 = Val64RxHwErrs +
31008- pAC->Pnmi.BufPort[0].RxNoBufCts +
31009- pAC->Pnmi.BufPort[1].RxNoBufCts;
31010- }
31011- }
31012- else {
31013- /* Dual net mode */
31014- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
31015- Val64 = Val64RxHwErrs + pAC->Pnmi.Port[NetIndex].RxNoBufCts;
31016- }
31017- /* Single net mode */
31018- else {
31019- Val64 = Val64RxHwErrs +
31020- pAC->Pnmi.Port[0].RxNoBufCts +
31021- pAC->Pnmi.Port[1].RxNoBufCts;
31022- }
31023- }
31024- SK_PNMI_STORE_U64(pBuf, Val64);
31025- *pLen = sizeof(SK_U64);
31026- break;
31027-
31028- case OID_SKGE_OUT_ERROR_CTS:
31029- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
31030- if (MacType == SK_MAC_XMAC) {
31031- /* Dual net mode */
31032- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
31033- Val64 = Val64TxHwErrs + pAC->Pnmi.BufPort[NetIndex].TxNoBufCts;
31034- }
31035- /* Single net mode */
31036- else {
31037- Val64 = Val64TxHwErrs +
31038- pAC->Pnmi.BufPort[0].TxNoBufCts +
31039- pAC->Pnmi.BufPort[1].TxNoBufCts;
31040- }
31041- }
31042- else {
31043- /* Dual net mode */
31044- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
31045- Val64 = Val64TxHwErrs + pAC->Pnmi.Port[NetIndex].TxNoBufCts;
31046- }
31047- /* Single net mode */
31048- else {
31049- Val64 = Val64TxHwErrs +
31050- pAC->Pnmi.Port[0].TxNoBufCts +
31051- pAC->Pnmi.Port[1].TxNoBufCts;
31052- }
31053- }
31054- SK_PNMI_STORE_U64(pBuf, Val64);
31055- *pLen = sizeof(SK_U64);
31056- break;
31057-
31058- case OID_SKGE_ERR_RECOVERY_CTS:
31059- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
31060- if (MacType == SK_MAC_XMAC) {
31061- /* Dual net mode */
31062- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
31063- Val64 = pAC->Pnmi.BufPort[NetIndex].ErrRecoveryCts;
31064- }
31065- /* Single net mode */
31066- else {
31067- Val64 = pAC->Pnmi.BufPort[0].ErrRecoveryCts +
31068- pAC->Pnmi.BufPort[1].ErrRecoveryCts;
31069- }
31070- }
31071- else {
31072- /* Dual net mode */
31073- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
31074- Val64 = pAC->Pnmi.Port[NetIndex].ErrRecoveryCts;
31075- }
31076- /* Single net mode */
31077- else {
31078- Val64 = pAC->Pnmi.Port[0].ErrRecoveryCts +
31079- pAC->Pnmi.Port[1].ErrRecoveryCts;
31080- }
31081- }
31082- SK_PNMI_STORE_U64(pBuf, Val64);
31083- *pLen = sizeof(SK_U64);
31084- break;
31085-
31086- case OID_SKGE_SYSUPTIME:
31087- Val64 = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC));
31088- Val64 -= pAC->Pnmi.StartUpTime;
31089- SK_PNMI_STORE_U64(pBuf, Val64);
31090- *pLen = sizeof(SK_U64);
31091- break;
31092-
31093- case OID_SKGE_MDB_VERSION:
31094- Val32 = SK_PNMI_MDB_VERSION;
31095- SK_PNMI_STORE_U32(pBuf, Val32);
31096- *pLen = sizeof(SK_U32);
31097- break;
31098-
31099- case OID_GEN_RCV_ERROR:
31100- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
31101- if (MacType == SK_MAC_XMAC) {
31102- Val64 = Val64RxHwErrs + pAC->Pnmi.BufPort[NetIndex].RxNoBufCts;
31103- }
31104- else {
31105- Val64 = Val64RxHwErrs + pAC->Pnmi.Port[NetIndex].RxNoBufCts;
31106- }
31107-
31108- /*
31109- * by default 32bit values are evaluated
31110- */
31111- if (!Is64BitReq) {
31112- Val32 = (SK_U32)Val64;
31113- SK_PNMI_STORE_U32(pBuf, Val32);
31114- *pLen = sizeof(SK_U32);
31115- }
31116- else {
31117- SK_PNMI_STORE_U64(pBuf, Val64);
31118- *pLen = sizeof(SK_U64);
31119- }
31120- break;
31121-
31122- case OID_GEN_XMIT_ERROR:
31123- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
31124- if (MacType == SK_MAC_XMAC) {
31125- Val64 = Val64TxHwErrs + pAC->Pnmi.BufPort[NetIndex].TxNoBufCts;
31126- }
31127- else {
31128- Val64 = Val64TxHwErrs + pAC->Pnmi.Port[NetIndex].TxNoBufCts;
31129- }
31130-
31131- /*
31132- * by default 32bit values are evaluated
31133- */
31134- if (!Is64BitReq) {
31135- Val32 = (SK_U32)Val64;
31136- SK_PNMI_STORE_U32(pBuf, Val32);
31137- *pLen = sizeof(SK_U32);
31138- }
31139- else {
31140- SK_PNMI_STORE_U64(pBuf, Val64);
31141- *pLen = sizeof(SK_U64);
31142- }
31143- break;
31144-
31145- case OID_GEN_RCV_NO_BUFFER:
31146- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
31147- if (MacType == SK_MAC_XMAC) {
31148- Val64 = pAC->Pnmi.BufPort[NetIndex].RxNoBufCts;
31149- }
31150- else {
31151- Val64 = pAC->Pnmi.Port[NetIndex].RxNoBufCts;
31152- }
31153-
31154- /*
31155- * by default 32bit values are evaluated
31156- */
31157- if (!Is64BitReq) {
31158- Val32 = (SK_U32)Val64;
31159- SK_PNMI_STORE_U32(pBuf, Val32);
31160- *pLen = sizeof(SK_U32);
31161- }
31162- else {
31163- SK_PNMI_STORE_U64(pBuf, Val64);
31164- *pLen = sizeof(SK_U64);
31165- }
31166- break;
31167-
31168- case OID_GEN_TRANSMIT_QUEUE_LENGTH:
31169- Val32 = (SK_U32)pAC->Pnmi.Port[NetIndex].TxSwQueueLen;
31170- SK_PNMI_STORE_U32(pBuf, Val32);
31171- *pLen = sizeof(SK_U32);
31172- break;
31173-
31174- default:
31175- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR034,
31176- SK_PNMI_ERR034MSG);
31177-
31178- *pLen = 0;
31179- return (SK_PNMI_ERR_GENERAL);
31180- }
31181-
31182- if (Id == OID_SKGE_RX_HW_ERROR_CTS ||
31183- Id == OID_SKGE_TX_HW_ERROR_CTS ||
31184- Id == OID_SKGE_IN_ERRORS_CTS ||
31185- Id == OID_SKGE_OUT_ERROR_CTS ||
31186- Id == OID_GEN_XMIT_ERROR ||
31187- Id == OID_GEN_RCV_ERROR) {
31188-
31189- pAC->Pnmi.MacUpdatedFlag --;
31190- }
31191-
31192- return (SK_PNMI_ERR_OK);
31193-}
31194-
31195-/*****************************************************************************
31196- *
31197- * Rlmt - OID handler function of OID_SKGE_RLMT_XXX single instance.
31198- *
31199- * Description:
31200- * Get/Presets/Sets the RLMT OIDs.
31201- *
31202- * Returns:
31203- * SK_PNMI_ERR_OK The request was successfully performed.
31204- * SK_PNMI_ERR_GENERAL A general severe internal error occured.
31205- * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
31206- * the correct data (e.g. a 32bit value is
31207- * needed, but a 16 bit value was passed).
31208- * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid
31209- * value range.
31210- * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set.
31211- * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
31212- * exist (e.g. port instance 3 on a two port
31213- * adapter.
31214- */
31215-PNMI_STATIC int Rlmt(
31216-SK_AC *pAC, /* Pointer to adapter context */
31217-SK_IOC IoC, /* IO context handle */
31218-int Action, /* GET/PRESET/SET action */
31219-SK_U32 Id, /* Object ID that is to be processed */
31220-char *pBuf, /* Buffer used for the management data transfer */
31221-unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */
31222-SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
31223-unsigned int TableIndex, /* Index to the Id table */
31224-SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */
31225-{
31226- int Ret;
31227- unsigned int PhysPortIndex;
31228- unsigned int PhysPortMax;
31229- SK_EVPARA EventParam;
31230- SK_U32 Val32;
31231- SK_U64 Val64;
31232-
31233-
31234- /*
31235- * Check instance. Only single instance OIDs are allowed here.
31236- */
31237- if (Instance != (SK_U32)(-1) && Instance != 1) {
31238-
31239- *pLen = 0;
31240- return (SK_PNMI_ERR_UNKNOWN_INST);
31241- }
31242-
31243- /*
31244- * Perform the requested action.
31245- */
31246- if (Action == SK_PNMI_GET) {
31247-
31248- /*
31249- * Check if the buffer length is large enough.
31250- */
31251-
31252- switch (Id) {
31253-
31254- case OID_SKGE_RLMT_MODE:
31255- case OID_SKGE_RLMT_PORT_ACTIVE:
31256- case OID_SKGE_RLMT_PORT_PREFERRED:
31257- if (*pLen < sizeof(SK_U8)) {
31258-
31259- *pLen = sizeof(SK_U8);
31260- return (SK_PNMI_ERR_TOO_SHORT);
31261- }
31262- break;
31263-
31264- case OID_SKGE_RLMT_PORT_NUMBER:
31265- if (*pLen < sizeof(SK_U32)) {
31266-
31267- *pLen = sizeof(SK_U32);
31268- return (SK_PNMI_ERR_TOO_SHORT);
31269- }
31270- break;
31271-
31272- case OID_SKGE_RLMT_CHANGE_CTS:
31273- case OID_SKGE_RLMT_CHANGE_TIME:
31274- case OID_SKGE_RLMT_CHANGE_ESTIM:
31275- case OID_SKGE_RLMT_CHANGE_THRES:
31276- if (*pLen < sizeof(SK_U64)) {
31277-
31278- *pLen = sizeof(SK_U64);
31279- return (SK_PNMI_ERR_TOO_SHORT);
31280- }
31281- break;
31282-
31283- default:
31284- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR035,
31285- SK_PNMI_ERR035MSG);
31286-
31287- *pLen = 0;
31288- return (SK_PNMI_ERR_GENERAL);
31289- }
31290-
31291- /*
31292- * Update RLMT statistic and increment semaphores to indicate
31293- * that an update was already done. Maybe RLMT will hold its
31294- * statistic always up to date some time. Then we can
31295- * remove this type of call.
31296- */
31297- if ((Ret = RlmtUpdate(pAC, IoC, NetIndex)) != SK_PNMI_ERR_OK) {
31298-
31299- *pLen = 0;
31300- return (Ret);
31301- }
31302- pAC->Pnmi.RlmtUpdatedFlag ++;
31303-
31304- /*
31305- * Retrieve Value
31306- */
31307- switch (Id) {
31308-
31309- case OID_SKGE_RLMT_MODE:
31310- *pBuf = (char)pAC->Rlmt.Net[0].RlmtMode;
31311- *pLen = sizeof(char);
31312- break;
31313-
31314- case OID_SKGE_RLMT_PORT_NUMBER:
31315- Val32 = (SK_U32)pAC->GIni.GIMacsFound;
31316- SK_PNMI_STORE_U32(pBuf, Val32);
31317- *pLen = sizeof(SK_U32);
31318- break;
31319-
31320- case OID_SKGE_RLMT_PORT_ACTIVE:
31321- *pBuf = 0;
31322- /*
31323- * If multiple ports may become active this OID
31324- * doesn't make sense any more. A new variable in
31325- * the port structure should be created. However,
31326- * for this variable the first active port is
31327- * returned.
31328- */
31329- PhysPortMax = pAC->GIni.GIMacsFound;
31330-
31331- for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;
31332- PhysPortIndex ++) {
31333-
31334- if (pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
31335-
31336- *pBuf = (char)SK_PNMI_PORT_PHYS2LOG(PhysPortIndex);
31337- break;
31338- }
31339- }
31340- *pLen = sizeof(char);
31341- break;
31342-
31343- case OID_SKGE_RLMT_PORT_PREFERRED:
31344- *pBuf = (char)SK_PNMI_PORT_PHYS2LOG(pAC->Rlmt.Net[NetIndex].Preference);
31345- *pLen = sizeof(char);
31346- break;
31347-
31348- case OID_SKGE_RLMT_CHANGE_CTS:
31349- Val64 = pAC->Pnmi.RlmtChangeCts;
31350- SK_PNMI_STORE_U64(pBuf, Val64);
31351- *pLen = sizeof(SK_U64);
31352- break;
31353-
31354- case OID_SKGE_RLMT_CHANGE_TIME:
31355- Val64 = pAC->Pnmi.RlmtChangeTime;
31356- SK_PNMI_STORE_U64(pBuf, Val64);
31357- *pLen = sizeof(SK_U64);
31358- break;
31359-
31360- case OID_SKGE_RLMT_CHANGE_ESTIM:
31361- Val64 = pAC->Pnmi.RlmtChangeEstimate.Estimate;
31362- SK_PNMI_STORE_U64(pBuf, Val64);
31363- *pLen = sizeof(SK_U64);
31364- break;
31365-
31366- case OID_SKGE_RLMT_CHANGE_THRES:
31367- Val64 = pAC->Pnmi.RlmtChangeThreshold;
31368- SK_PNMI_STORE_U64(pBuf, Val64);
31369- *pLen = sizeof(SK_U64);
31370- break;
31371-
31372- default:
31373- SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR,
31374- ("Rlmt: Unknown OID should be handled before"));
31375-
31376- pAC->Pnmi.RlmtUpdatedFlag --;
31377- *pLen = 0;
31378- return (SK_PNMI_ERR_GENERAL);
31379- }
31380-
31381- pAC->Pnmi.RlmtUpdatedFlag --;
31382- }
31383- else {
31384- /* Perform a preset or set */
31385- switch (Id) {
31386-
31387- case OID_SKGE_RLMT_MODE:
31388- /* Check if the buffer length is plausible */
31389- if (*pLen < sizeof(char)) {
31390-
31391- *pLen = sizeof(char);
31392- return (SK_PNMI_ERR_TOO_SHORT);
31393- }
31394- /* Check if the value range is correct */
31395- if (*pLen != sizeof(char) ||
31396- (*pBuf & SK_PNMI_RLMT_MODE_CHK_LINK) == 0 ||
31397- *(SK_U8 *)pBuf > 15) {
31398-
31399- *pLen = 0;
31400- return (SK_PNMI_ERR_BAD_VALUE);
31401- }
31402- /* The preset ends here */
31403- if (Action == SK_PNMI_PRESET) {
31404-
31405- *pLen = 0;
31406- return (SK_PNMI_ERR_OK);
31407- }
31408- /* Send an event to RLMT to change the mode */
31409- SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
31410- EventParam.Para32[0] |= (SK_U32)(*pBuf);
31411- EventParam.Para32[1] = 0;
31412- if (SkRlmtEvent(pAC, IoC, SK_RLMT_MODE_CHANGE,
31413- EventParam) > 0) {
31414-
31415- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR037,
31416- SK_PNMI_ERR037MSG);
31417-
31418- *pLen = 0;
31419- return (SK_PNMI_ERR_GENERAL);
31420- }
31421- break;
31422-
31423- case OID_SKGE_RLMT_PORT_PREFERRED:
31424- /* Check if the buffer length is plausible */
31425- if (*pLen < sizeof(char)) {
31426-
31427- *pLen = sizeof(char);
31428- return (SK_PNMI_ERR_TOO_SHORT);
31429- }
31430- /* Check if the value range is correct */
31431- if (*pLen != sizeof(char) || *(SK_U8 *)pBuf >
31432- (SK_U8)pAC->GIni.GIMacsFound) {
31433-
31434- *pLen = 0;
31435- return (SK_PNMI_ERR_BAD_VALUE);
31436- }
31437- /* The preset ends here */
31438- if (Action == SK_PNMI_PRESET) {
31439-
31440- *pLen = 0;
31441- return (SK_PNMI_ERR_OK);
31442- }
31443-
31444- /*
31445- * Send an event to RLMT change the preferred port.
31446- * A param of -1 means automatic mode. RLMT will
31447- * make the decision which is the preferred port.
31448- */
31449- SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
31450- EventParam.Para32[0] = (SK_U32)(*pBuf) - 1;
31451- EventParam.Para32[1] = NetIndex;
31452- if (SkRlmtEvent(pAC, IoC, SK_RLMT_PREFPORT_CHANGE,
31453- EventParam) > 0) {
31454-
31455- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR038,
31456- SK_PNMI_ERR038MSG);
31457-
31458- *pLen = 0;
31459- return (SK_PNMI_ERR_GENERAL);
31460- }
31461- break;
31462-
31463- case OID_SKGE_RLMT_CHANGE_THRES:
31464- /* Check if the buffer length is plausible */
31465- if (*pLen < sizeof(SK_U64)) {
31466-
31467- *pLen = sizeof(SK_U64);
31468- return (SK_PNMI_ERR_TOO_SHORT);
31469- }
31470- /*
31471- * There are not many restrictions to the
31472- * value range.
31473- */
31474- if (*pLen != sizeof(SK_U64)) {
31475-
31476- *pLen = 0;
31477- return (SK_PNMI_ERR_BAD_VALUE);
31478- }
31479- /* A preset ends here */
31480- if (Action == SK_PNMI_PRESET) {
31481-
31482- *pLen = 0;
31483- return (SK_PNMI_ERR_OK);
31484- }
31485- /*
31486- * Store the new threshold, which will be taken
31487- * on the next timer event.
31488- */
31489- SK_PNMI_READ_U64(pBuf, Val64);
31490- pAC->Pnmi.RlmtChangeThreshold = Val64;
31491- break;
31492-
31493- default:
31494- /* The other OIDs are not be able for set */
31495- *pLen = 0;
31496- return (SK_PNMI_ERR_READ_ONLY);
31497- }
31498- }
31499-
31500- return (SK_PNMI_ERR_OK);
31501-}
31502-
31503-/*****************************************************************************
31504- *
31505- * RlmtStat - OID handler function of OID_SKGE_RLMT_XXX multiple instance.
31506- *
31507- * Description:
31508- * Performs get requests on multiple instance variables.
31509- *
31510- * Returns:
31511- * SK_PNMI_ERR_OK The request was successfully performed.
31512- * SK_PNMI_ERR_GENERAL A general severe internal error occured.
31513- * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
31514- * the correct data (e.g. a 32bit value is
31515- * needed, but a 16 bit value was passed).
31516- * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
31517- * exist (e.g. port instance 3 on a two port
31518- * adapter.
31519- */
31520-PNMI_STATIC int RlmtStat(
31521-SK_AC *pAC, /* Pointer to adapter context */
31522-SK_IOC IoC, /* IO context handle */
31523-int Action, /* GET/PRESET/SET action */
31524-SK_U32 Id, /* Object ID that is to be processed */
31525-char *pBuf, /* Buffer used for the management data transfer */
31526-unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */
31527-SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
31528-unsigned int TableIndex, /* Index to the Id table */
31529-SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */
31530-{
31531- unsigned int PhysPortMax;
31532- unsigned int PhysPortIndex;
31533- unsigned int Limit;
31534- unsigned int Offset;
31535- int Ret;
31536- SK_U32 Val32;
31537- SK_U64 Val64;
31538-
31539- /*
31540- * Calculate the port indexes from the instance.
31541- */
31542- PhysPortMax = pAC->GIni.GIMacsFound;
31543-
31544- if ((Instance != (SK_U32)(-1))) {
31545- /* Check instance range */
31546- if ((Instance < 1) || (Instance > PhysPortMax)) {
31547-
31548- *pLen = 0;
31549- return (SK_PNMI_ERR_UNKNOWN_INST);
31550- }
31551-
31552- /* Single net mode */
31553- PhysPortIndex = Instance - 1;
31554-
31555- /* Dual net mode */
31556- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
31557- PhysPortIndex = NetIndex;
31558- }
31559-
31560- /* Both net modes */
31561- Limit = PhysPortIndex + 1;
31562- }
31563- else {
31564- /* Single net mode */
31565- PhysPortIndex = 0;
31566- Limit = PhysPortMax;
31567-
31568- /* Dual net mode */
31569- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
31570- PhysPortIndex = NetIndex;
31571- Limit = PhysPortIndex + 1;
31572- }
31573- }
31574-
31575- /*
31576- * Currently only get requests are allowed.
31577- */
31578- if (Action != SK_PNMI_GET) {
31579-
31580- *pLen = 0;
31581- return (SK_PNMI_ERR_READ_ONLY);
31582- }
31583-
31584- /*
31585- * Check if the buffer length is large enough.
31586- */
31587- switch (Id) {
31588-
31589- case OID_SKGE_RLMT_PORT_INDEX:
31590- case OID_SKGE_RLMT_STATUS:
31591- if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U32)) {
31592-
31593- *pLen = (Limit - PhysPortIndex) * sizeof(SK_U32);
31594- return (SK_PNMI_ERR_TOO_SHORT);
31595- }
31596- break;
31597-
31598- case OID_SKGE_RLMT_TX_HELLO_CTS:
31599- case OID_SKGE_RLMT_RX_HELLO_CTS:
31600- case OID_SKGE_RLMT_TX_SP_REQ_CTS:
31601- case OID_SKGE_RLMT_RX_SP_CTS:
31602- if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U64)) {
31603-
31604- *pLen = (Limit - PhysPortIndex) * sizeof(SK_U64);
31605- return (SK_PNMI_ERR_TOO_SHORT);
31606- }
31607- break;
31608-
31609- default:
31610- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR039,
31611- SK_PNMI_ERR039MSG);
31612-
31613- *pLen = 0;
31614- return (SK_PNMI_ERR_GENERAL);
31615-
31616- }
31617-
31618- /*
31619- * Update statistic and increment semaphores to indicate that
31620- * an update was already done.
31621- */
31622- if ((Ret = RlmtUpdate(pAC, IoC, NetIndex)) != SK_PNMI_ERR_OK) {
31623-
31624- *pLen = 0;
31625- return (Ret);
31626- }
31627- pAC->Pnmi.RlmtUpdatedFlag ++;
31628-
31629- /*
31630- * Get value
31631- */
31632- Offset = 0;
31633- for (; PhysPortIndex < Limit; PhysPortIndex ++) {
31634-
31635- switch (Id) {
31636-
31637- case OID_SKGE_RLMT_PORT_INDEX:
31638- Val32 = PhysPortIndex;
31639- SK_PNMI_STORE_U32(pBuf + Offset, Val32);
31640- Offset += sizeof(SK_U32);
31641- break;
31642-
31643- case OID_SKGE_RLMT_STATUS:
31644- if (pAC->Rlmt.Port[PhysPortIndex].PortState ==
31645- SK_RLMT_PS_INIT ||
31646- pAC->Rlmt.Port[PhysPortIndex].PortState ==
31647- SK_RLMT_PS_DOWN) {
31648-
31649- Val32 = SK_PNMI_RLMT_STATUS_ERROR;
31650- }
31651- else if (pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
31652-
31653- Val32 = SK_PNMI_RLMT_STATUS_ACTIVE;
31654- }
31655- else {
31656- Val32 = SK_PNMI_RLMT_STATUS_STANDBY;
31657- }
31658- SK_PNMI_STORE_U32(pBuf + Offset, Val32);
31659- Offset += sizeof(SK_U32);
31660- break;
31661-
31662- case OID_SKGE_RLMT_TX_HELLO_CTS:
31663- Val64 = pAC->Rlmt.Port[PhysPortIndex].TxHelloCts;
31664- SK_PNMI_STORE_U64(pBuf + Offset, Val64);
31665- Offset += sizeof(SK_U64);
31666- break;
31667-
31668- case OID_SKGE_RLMT_RX_HELLO_CTS:
31669- Val64 = pAC->Rlmt.Port[PhysPortIndex].RxHelloCts;
31670- SK_PNMI_STORE_U64(pBuf + Offset, Val64);
31671- Offset += sizeof(SK_U64);
31672- break;
31673-
31674- case OID_SKGE_RLMT_TX_SP_REQ_CTS:
31675- Val64 = pAC->Rlmt.Port[PhysPortIndex].TxSpHelloReqCts;
31676- SK_PNMI_STORE_U64(pBuf + Offset, Val64);
31677- Offset += sizeof(SK_U64);
31678- break;
31679-
31680- case OID_SKGE_RLMT_RX_SP_CTS:
31681- Val64 = pAC->Rlmt.Port[PhysPortIndex].RxSpHelloCts;
31682- SK_PNMI_STORE_U64(pBuf + Offset, Val64);
31683- Offset += sizeof(SK_U64);
31684- break;
31685-
31686- default:
31687- SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR,
31688- ("RlmtStat: Unknown OID should be errored before"));
31689-
31690- pAC->Pnmi.RlmtUpdatedFlag --;
31691- *pLen = 0;
31692- return (SK_PNMI_ERR_GENERAL);
31693- }
31694- }
31695- *pLen = Offset;
31696-
31697- pAC->Pnmi.RlmtUpdatedFlag --;
31698-
31699- return (SK_PNMI_ERR_OK);
31700-}
31701-
31702-/*****************************************************************************
31703- *
31704- * MacPrivateConf - OID handler function of OIDs concerning the configuration
31705- *
31706- * Description:
31707- * Get/Presets/Sets the OIDs concerning the configuration.
31708- *
31709- * Returns:
31710- * SK_PNMI_ERR_OK The request was successfully performed.
31711- * SK_PNMI_ERR_GENERAL A general severe internal error occured.
31712- * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
31713- * the correct data (e.g. a 32bit value is
31714- * needed, but a 16 bit value was passed).
31715- * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid
31716- * value range.
31717- * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set.
31718- * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
31719- * exist (e.g. port instance 3 on a two port
31720- * adapter.
31721- */
31722-PNMI_STATIC int MacPrivateConf(
31723-SK_AC *pAC, /* Pointer to adapter context */
31724-SK_IOC IoC, /* IO context handle */
31725-int Action, /* GET/PRESET/SET action */
31726-SK_U32 Id, /* Object ID that is to be processed */
31727-char *pBuf, /* Buffer used for the management data transfer */
31728-unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */
31729-SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
31730-unsigned int TableIndex, /* Index to the Id table */
31731-SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */
31732-{
31733- unsigned int PhysPortMax;
31734- unsigned int PhysPortIndex;
31735- unsigned int LogPortMax;
31736- unsigned int LogPortIndex;
31737- unsigned int Limit;
31738- unsigned int Offset;
31739- char Val8;
31740- char *pBufPtr;
31741- int Ret;
31742- SK_EVPARA EventParam;
31743- SK_U32 Val32;
31744-
31745- /*
31746- * Calculate instance if wished. MAC index 0 is the virtual MAC.
31747- */
31748- PhysPortMax = pAC->GIni.GIMacsFound;
31749- LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax);
31750-
31751- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* Dual net mode */
31752- LogPortMax--;
31753- }
31754-
31755- if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried */
31756- /* Check instance range */
31757- if ((Instance < 1) || (Instance > LogPortMax)) {
31758-
31759- *pLen = 0;
31760- return (SK_PNMI_ERR_UNKNOWN_INST);
31761- }
31762- LogPortIndex = SK_PNMI_PORT_INST2LOG(Instance);
31763- Limit = LogPortIndex + 1;
31764- }
31765-
31766- else { /* Instance == (SK_U32)(-1), get all Instances of that OID */
31767-
31768- LogPortIndex = 0;
31769- Limit = LogPortMax;
31770- }
31771-
31772- /*
31773- * Perform action
31774- */
31775- if (Action == SK_PNMI_GET) {
31776-
31777- /* Check length */
31778- switch (Id) {
31779-
31780- case OID_SKGE_PMD:
31781- case OID_SKGE_CONNECTOR:
31782- case OID_SKGE_LINK_CAP:
31783- case OID_SKGE_LINK_MODE:
31784- case OID_SKGE_LINK_MODE_STATUS:
31785- case OID_SKGE_LINK_STATUS:
31786- case OID_SKGE_FLOWCTRL_CAP:
31787- case OID_SKGE_FLOWCTRL_MODE:
31788- case OID_SKGE_FLOWCTRL_STATUS:
31789- case OID_SKGE_PHY_OPERATION_CAP:
31790- case OID_SKGE_PHY_OPERATION_MODE:
31791- case OID_SKGE_PHY_OPERATION_STATUS:
31792- case OID_SKGE_SPEED_CAP:
31793- case OID_SKGE_SPEED_MODE:
31794- case OID_SKGE_SPEED_STATUS:
31795-#ifdef SK_PHY_LP_MODE
31796- case OID_SKGE_PHY_LP_MODE:
31797-#endif
31798- if (*pLen < (Limit - LogPortIndex) * sizeof(SK_U8)) {
31799-
31800- *pLen = (Limit - LogPortIndex) * sizeof(SK_U8);
31801- return (SK_PNMI_ERR_TOO_SHORT);
31802- }
31803- break;
31804-
31805- case OID_SKGE_MTU:
31806- case OID_SKGE_PHY_TYPE:
31807- if (*pLen < (Limit - LogPortIndex) * sizeof(SK_U32)) {
31808-
31809- *pLen = (Limit - LogPortIndex) * sizeof(SK_U32);
31810- return (SK_PNMI_ERR_TOO_SHORT);
31811- }
31812- break;
31813-
31814- default:
31815- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR041,
31816- SK_PNMI_ERR041MSG);
31817- *pLen = 0;
31818- return (SK_PNMI_ERR_GENERAL);
31819- }
31820-
31821- /*
31822- * Update statistic and increment semaphore to indicate
31823- * that an update was already done.
31824- */
31825- if ((Ret = SirqUpdate(pAC, IoC)) != SK_PNMI_ERR_OK) {
31826-
31827- *pLen = 0;
31828- return (Ret);
31829- }
31830- pAC->Pnmi.SirqUpdatedFlag ++;
31831-
31832- /*
31833- * Get value
31834- */
31835- Offset = 0;
31836- for (; LogPortIndex < Limit; LogPortIndex ++) {
31837-
31838- pBufPtr = pBuf + Offset;
31839-
31840- switch (Id) {
31841-
31842- case OID_SKGE_PMD:
31843- *pBufPtr = pAC->Pnmi.PMD;
31844- Offset += sizeof(char);
31845- break;
31846-
31847- case OID_SKGE_CONNECTOR:
31848- *pBufPtr = pAC->Pnmi.Connector;
31849- Offset += sizeof(char);
31850- break;
31851-
31852- case OID_SKGE_PHY_TYPE:
31853- if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
31854- if (LogPortIndex == 0) {
31855- continue;
31856- }
31857- else {
31858- /* Get value for physical ports */
31859- PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
31860- pAC, LogPortIndex);
31861- Val32 = pAC->GIni.GP[PhysPortIndex].PhyType;
31862- SK_PNMI_STORE_U32(pBufPtr, Val32);
31863- }
31864- }
31865- else { /* DualNetMode */
31866-
31867- Val32 = pAC->GIni.GP[NetIndex].PhyType;
31868- SK_PNMI_STORE_U32(pBufPtr, Val32);
31869- }
31870- Offset += sizeof(SK_U32);
31871- break;
31872-
31873-#ifdef SK_PHY_LP_MODE
31874- case OID_SKGE_PHY_LP_MODE:
31875- if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
31876- if (LogPortIndex == 0) {
31877- continue;
31878- }
31879- else {
31880- /* Get value for physical ports */
31881- PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);
31882- Val8 = (SK_U8) pAC->GIni.GP[PhysPortIndex].PPhyPowerState;
31883- *pBufPtr = Val8;
31884- }
31885- }
31886- else { /* DualNetMode */
31887-
31888- Val8 = (SK_U8) pAC->GIni.GP[PhysPortIndex].PPhyPowerState;
31889- *pBufPtr = Val8;
31890- }
31891- Offset += sizeof(SK_U8);
31892- break;
31893-#endif
31894-
31895- case OID_SKGE_LINK_CAP:
31896- if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
31897- if (LogPortIndex == 0) {
31898- /* Get value for virtual port */
31899- VirtualConf(pAC, IoC, Id, pBufPtr);
31900- }
31901- else {
31902- /* Get value for physical ports */
31903- PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
31904- pAC, LogPortIndex);
31905-
31906- *pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkCap;
31907- }
31908- }
31909- else { /* DualNetMode */
31910-
31911- *pBufPtr = pAC->GIni.GP[NetIndex].PLinkCap;
31912- }
31913- Offset += sizeof(char);
31914- break;
31915-
31916- case OID_SKGE_LINK_MODE:
31917- if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
31918- if (LogPortIndex == 0) {
31919- /* Get value for virtual port */
31920- VirtualConf(pAC, IoC, Id, pBufPtr);
31921- }
31922- else {
31923- /* Get value for physical ports */
31924- PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
31925- pAC, LogPortIndex);
31926-
31927- *pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkModeConf;
31928- }
31929- }
31930- else { /* DualNetMode */
31931-
31932- *pBufPtr = pAC->GIni.GP[NetIndex].PLinkModeConf;
31933- }
31934- Offset += sizeof(char);
31935- break;
31936-
31937- case OID_SKGE_LINK_MODE_STATUS:
31938- if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
31939- if (LogPortIndex == 0) {
31940- /* Get value for virtual port */
31941- VirtualConf(pAC, IoC, Id, pBufPtr);
31942- }
31943- else {
31944- /* Get value for physical port */
31945- PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
31946- pAC, LogPortIndex);
31947-
31948- *pBufPtr =
31949- CalculateLinkModeStatus(pAC, IoC, PhysPortIndex);
31950- }
31951- }
31952- else { /* DualNetMode */
31953-
31954- *pBufPtr = CalculateLinkModeStatus(pAC, IoC, NetIndex);
31955- }
31956- Offset += sizeof(char);
31957- break;
31958-
31959- case OID_SKGE_LINK_STATUS:
31960- if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
31961- if (LogPortIndex == 0) {
31962- /* Get value for virtual port */
31963- VirtualConf(pAC, IoC, Id, pBufPtr);
31964- }
31965- else {
31966- /* Get value for physical ports */
31967- PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
31968- pAC, LogPortIndex);
31969-
31970- *pBufPtr = CalculateLinkStatus(pAC, IoC, PhysPortIndex);
31971- }
31972- }
31973- else { /* DualNetMode */
31974-
31975- *pBufPtr = CalculateLinkStatus(pAC, IoC, NetIndex);
31976- }
31977- Offset += sizeof(char);
31978- break;
31979-
31980- case OID_SKGE_FLOWCTRL_CAP:
31981- if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
31982- if (LogPortIndex == 0) {
31983- /* Get value for virtual port */
31984- VirtualConf(pAC, IoC, Id, pBufPtr);
31985- }
31986- else {
31987- /* Get value for physical ports */
31988- PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
31989- pAC, LogPortIndex);
31990-
31991- *pBufPtr = pAC->GIni.GP[PhysPortIndex].PFlowCtrlCap;
31992- }
31993- }
31994- else { /* DualNetMode */
31995-
31996- *pBufPtr = pAC->GIni.GP[NetIndex].PFlowCtrlCap;
31997- }
31998- Offset += sizeof(char);
31999- break;
32000-
32001- case OID_SKGE_FLOWCTRL_MODE:
32002- if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
32003- if (LogPortIndex == 0) {
32004- /* Get value for virtual port */
32005- VirtualConf(pAC, IoC, Id, pBufPtr);
32006- }
32007- else {
32008- /* Get value for physical port */
32009- PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
32010- pAC, LogPortIndex);
32011-
32012- *pBufPtr = pAC->GIni.GP[PhysPortIndex].PFlowCtrlMode;
32013- }
32014- }
32015- else { /* DualNetMode */
32016-
32017- *pBufPtr = pAC->GIni.GP[NetIndex].PFlowCtrlMode;
32018- }
32019- Offset += sizeof(char);
32020- break;
32021-
32022- case OID_SKGE_FLOWCTRL_STATUS:
32023- if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
32024- if (LogPortIndex == 0) {
32025- /* Get value for virtual port */
32026- VirtualConf(pAC, IoC, Id, pBufPtr);
32027- }
32028- else {
32029- /* Get value for physical port */
32030- PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
32031- pAC, LogPortIndex);
32032-
32033- *pBufPtr = pAC->GIni.GP[PhysPortIndex].PFlowCtrlStatus;
32034- }
32035- }
32036- else { /* DualNetMode */
32037-
32038- *pBufPtr = pAC->GIni.GP[NetIndex].PFlowCtrlStatus;
32039- }
32040- Offset += sizeof(char);
32041- break;
32042-
32043- case OID_SKGE_PHY_OPERATION_CAP:
32044- if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
32045- if (LogPortIndex == 0) {
32046- /* Get value for virtual port */
32047- VirtualConf(pAC, IoC, Id, pBufPtr);
32048- }
32049- else {
32050- /* Get value for physical ports */
32051- PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
32052- pAC, LogPortIndex);
32053-
32054- *pBufPtr = pAC->GIni.GP[PhysPortIndex].PMSCap;
32055- }
32056- }
32057- else { /* DualNetMode */
32058-
32059- *pBufPtr = pAC->GIni.GP[NetIndex].PMSCap;
32060- }
32061- Offset += sizeof(char);
32062- break;
32063-
32064- case OID_SKGE_PHY_OPERATION_MODE:
32065- if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
32066- if (LogPortIndex == 0) {
32067- /* Get value for virtual port */
32068- VirtualConf(pAC, IoC, Id, pBufPtr);
32069- }
32070- else {
32071- /* Get value for physical port */
32072- PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
32073- pAC, LogPortIndex);
32074-
32075- *pBufPtr = pAC->GIni.GP[PhysPortIndex].PMSMode;
32076- }
32077- }
32078- else { /* DualNetMode */
32079-
32080- *pBufPtr = pAC->GIni.GP[NetIndex].PMSMode;
32081- }
32082- Offset += sizeof(char);
32083- break;
32084-
32085- case OID_SKGE_PHY_OPERATION_STATUS:
32086- if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
32087- if (LogPortIndex == 0) {
32088- /* Get value for virtual port */
32089- VirtualConf(pAC, IoC, Id, pBufPtr);
32090- }
32091- else {
32092- /* Get value for physical port */
32093- PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
32094- pAC, LogPortIndex);
32095-
32096- *pBufPtr = pAC->GIni.GP[PhysPortIndex].PMSStatus;
32097- }
32098- }
32099- else {
32100-
32101- *pBufPtr = pAC->GIni.GP[NetIndex].PMSStatus;
32102- }
32103- Offset += sizeof(char);
32104- break;
32105-
32106- case OID_SKGE_SPEED_CAP:
32107- if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
32108- if (LogPortIndex == 0) {
32109- /* Get value for virtual port */
32110- VirtualConf(pAC, IoC, Id, pBufPtr);
32111- }
32112- else {
32113- /* Get value for physical ports */
32114- PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
32115- pAC, LogPortIndex);
32116-
32117- *pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkSpeedCap;
32118- }
32119- }
32120- else { /* DualNetMode */
32121-
32122- *pBufPtr = pAC->GIni.GP[NetIndex].PLinkSpeedCap;
32123- }
32124- Offset += sizeof(char);
32125- break;
32126-
32127- case OID_SKGE_SPEED_MODE:
32128- if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
32129- if (LogPortIndex == 0) {
32130- /* Get value for virtual port */
32131- VirtualConf(pAC, IoC, Id, pBufPtr);
32132- }
32133- else {
32134- /* Get value for physical port */
32135- PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
32136- pAC, LogPortIndex);
32137-
32138- *pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkSpeed;
32139- }
32140- }
32141- else { /* DualNetMode */
32142-
32143- *pBufPtr = pAC->GIni.GP[NetIndex].PLinkSpeed;
32144- }
32145- Offset += sizeof(char);
32146- break;
32147-
32148- case OID_SKGE_SPEED_STATUS:
32149- if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
32150- if (LogPortIndex == 0) {
32151- /* Get value for virtual port */
32152- VirtualConf(pAC, IoC, Id, pBufPtr);
32153- }
32154- else {
32155- /* Get value for physical port */
32156- PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
32157- pAC, LogPortIndex);
32158-
32159- *pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkSpeedUsed;
32160- }
32161- }
32162- else { /* DualNetMode */
32163-
32164- *pBufPtr = pAC->GIni.GP[NetIndex].PLinkSpeedUsed;
32165- }
32166- Offset += sizeof(char);
32167- break;
32168-
32169- case OID_SKGE_MTU:
32170- Val32 = SK_DRIVER_GET_MTU(pAC, IoC, NetIndex);
32171- SK_PNMI_STORE_U32(pBufPtr, Val32);
32172- Offset += sizeof(SK_U32);
32173- break;
32174-
32175- default:
32176- SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR,
32177- ("MacPrivateConf: Unknown OID should be handled before"));
32178-
32179- pAC->Pnmi.SirqUpdatedFlag --;
32180- return (SK_PNMI_ERR_GENERAL);
32181- }
32182- }
32183- *pLen = Offset;
32184- pAC->Pnmi.SirqUpdatedFlag --;
32185-
32186- return (SK_PNMI_ERR_OK);
32187- }
32188-
32189- /*
32190- * From here SET or PRESET action. Check if the passed
32191- * buffer length is plausible.
32192- */
32193- switch (Id) {
32194-
32195- case OID_SKGE_LINK_MODE:
32196- case OID_SKGE_FLOWCTRL_MODE:
32197- case OID_SKGE_PHY_OPERATION_MODE:
32198- case OID_SKGE_SPEED_MODE:
32199- if (*pLen < Limit - LogPortIndex) {
32200-
32201- *pLen = Limit - LogPortIndex;
32202- return (SK_PNMI_ERR_TOO_SHORT);
32203- }
32204- if (*pLen != Limit - LogPortIndex) {
32205-
32206- *pLen = 0;
32207- return (SK_PNMI_ERR_BAD_VALUE);
32208- }
32209- break;
32210-
32211-#ifdef SK_PHY_LP_MODE
32212- case OID_SKGE_PHY_LP_MODE:
32213- if (*pLen < Limit - LogPortIndex) {
32214-
32215- *pLen = Limit - LogPortIndex;
32216- return (SK_PNMI_ERR_TOO_SHORT);
32217- }
32218- break;
32219-#endif
32220-
32221- case OID_SKGE_MTU:
32222- if (*pLen < sizeof(SK_U32)) {
32223-
32224- *pLen = sizeof(SK_U32);
32225- return (SK_PNMI_ERR_TOO_SHORT);
32226- }
32227- if (*pLen != sizeof(SK_U32)) {
32228-
32229- *pLen = 0;
32230- return (SK_PNMI_ERR_BAD_VALUE);
32231- }
32232- break;
32233-
32234- default:
32235- *pLen = 0;
32236- return (SK_PNMI_ERR_READ_ONLY);
32237- }
32238-
32239- /*
32240- * Perform preset or set
32241- */
32242- Offset = 0;
32243- for (; LogPortIndex < Limit; LogPortIndex ++) {
32244-
32245- switch (Id) {
32246-
32247- case OID_SKGE_LINK_MODE:
32248- /* Check the value range */
32249- Val8 = *(pBuf + Offset);
32250- if (Val8 == 0) {
32251-
32252- Offset += sizeof(char);
32253- break;
32254- }
32255- if (Val8 < SK_LMODE_HALF ||
32256- (LogPortIndex != 0 && Val8 > SK_LMODE_AUTOSENSE) ||
32257- (LogPortIndex == 0 && Val8 > SK_LMODE_INDETERMINATED)) {
32258-
32259- *pLen = 0;
32260- return (SK_PNMI_ERR_BAD_VALUE);
32261- }
32262-
32263- /* The preset ends here */
32264- if (Action == SK_PNMI_PRESET) {
32265-
32266- return (SK_PNMI_ERR_OK);
32267- }
32268-
32269- if (LogPortIndex == 0) {
32270-
32271- /*
32272- * The virtual port consists of all currently
32273- * active ports. Find them and send an event
32274- * with the new link mode to SIRQ.
32275- */
32276- for (PhysPortIndex = 0;
32277- PhysPortIndex < PhysPortMax;
32278- PhysPortIndex ++) {
32279-
32280- if (!pAC->Pnmi.Port[PhysPortIndex].
32281- ActiveFlag) {
32282-
32283- continue;
32284- }
32285-
32286- EventParam.Para32[0] = PhysPortIndex;
32287- EventParam.Para32[1] = (SK_U32)Val8;
32288- if (SkGeSirqEvent(pAC, IoC,
32289- SK_HWEV_SET_LMODE,
32290- EventParam) > 0) {
32291-
32292- SK_ERR_LOG(pAC, SK_ERRCL_SW,
32293- SK_PNMI_ERR043,
32294- SK_PNMI_ERR043MSG);
32295-
32296- *pLen = 0;
32297- return (SK_PNMI_ERR_GENERAL);
32298- }
32299- }
32300- }
32301- else {
32302- /*
32303- * Send an event with the new link mode to
32304- * the SIRQ module.
32305- */
32306- EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
32307- pAC, LogPortIndex);
32308- EventParam.Para32[1] = (SK_U32)Val8;
32309- if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_LMODE,
32310- EventParam) > 0) {
32311-
32312- SK_ERR_LOG(pAC, SK_ERRCL_SW,
32313- SK_PNMI_ERR043,
32314- SK_PNMI_ERR043MSG);
32315-
32316- *pLen = 0;
32317- return (SK_PNMI_ERR_GENERAL);
32318- }
32319- }
32320- Offset += sizeof(char);
32321- break;
32322-
32323- case OID_SKGE_FLOWCTRL_MODE:
32324- /* Check the value range */
32325- Val8 = *(pBuf + Offset);
32326- if (Val8 == 0) {
32327-
32328- Offset += sizeof(char);
32329- break;
32330- }
32331- if (Val8 < SK_FLOW_MODE_NONE ||
32332- (LogPortIndex != 0 && Val8 > SK_FLOW_MODE_SYM_OR_REM) ||
32333- (LogPortIndex == 0 && Val8 > SK_FLOW_MODE_INDETERMINATED)) {
32334-
32335- *pLen = 0;
32336- return (SK_PNMI_ERR_BAD_VALUE);
32337- }
32338-
32339- /* The preset ends here */
32340- if (Action == SK_PNMI_PRESET) {
32341-
32342- return (SK_PNMI_ERR_OK);
32343- }
32344-
32345- if (LogPortIndex == 0) {
32346-
32347- /*
32348- * The virtual port consists of all currently
32349- * active ports. Find them and send an event
32350- * with the new flow control mode to SIRQ.
32351- */
32352- for (PhysPortIndex = 0;
32353- PhysPortIndex < PhysPortMax;
32354- PhysPortIndex ++) {
32355-
32356- if (!pAC->Pnmi.Port[PhysPortIndex].
32357- ActiveFlag) {
32358-
32359- continue;
32360- }
32361-
32362- EventParam.Para32[0] = PhysPortIndex;
32363- EventParam.Para32[1] = (SK_U32)Val8;
32364- if (SkGeSirqEvent(pAC, IoC,
32365- SK_HWEV_SET_FLOWMODE,
32366- EventParam) > 0) {
32367-
32368- SK_ERR_LOG(pAC, SK_ERRCL_SW,
32369- SK_PNMI_ERR044,
32370- SK_PNMI_ERR044MSG);
32371-
32372- *pLen = 0;
32373- return (SK_PNMI_ERR_GENERAL);
32374- }
32375- }
32376- }
32377- else {
32378- /*
32379- * Send an event with the new flow control
32380- * mode to the SIRQ module.
32381- */
32382- EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
32383- pAC, LogPortIndex);
32384- EventParam.Para32[1] = (SK_U32)Val8;
32385- if (SkGeSirqEvent(pAC, IoC,
32386- SK_HWEV_SET_FLOWMODE, EventParam)
32387- > 0) {
32388-
32389- SK_ERR_LOG(pAC, SK_ERRCL_SW,
32390- SK_PNMI_ERR044,
32391- SK_PNMI_ERR044MSG);
32392-
32393- *pLen = 0;
32394- return (SK_PNMI_ERR_GENERAL);
32395- }
32396- }
32397- Offset += sizeof(char);
32398- break;
32399-
32400- case OID_SKGE_PHY_OPERATION_MODE :
32401- /* Check the value range */
32402- Val8 = *(pBuf + Offset);
32403- if (Val8 == 0) {
32404- /* mode of this port remains unchanged */
32405- Offset += sizeof(char);
32406- break;
32407- }
32408- if (Val8 < SK_MS_MODE_AUTO ||
32409- (LogPortIndex != 0 && Val8 > SK_MS_MODE_SLAVE) ||
32410- (LogPortIndex == 0 && Val8 > SK_MS_MODE_INDETERMINATED)) {
32411-
32412- *pLen = 0;
32413- return (SK_PNMI_ERR_BAD_VALUE);
32414- }
32415-
32416- /* The preset ends here */
32417- if (Action == SK_PNMI_PRESET) {
32418-
32419- return (SK_PNMI_ERR_OK);
32420- }
32421-
32422- if (LogPortIndex == 0) {
32423-
32424- /*
32425- * The virtual port consists of all currently
32426- * active ports. Find them and send an event
32427- * with new master/slave (role) mode to SIRQ.
32428- */
32429- for (PhysPortIndex = 0;
32430- PhysPortIndex < PhysPortMax;
32431- PhysPortIndex ++) {
32432-
32433- if (!pAC->Pnmi.Port[PhysPortIndex].
32434- ActiveFlag) {
32435-
32436- continue;
32437- }
32438-
32439- EventParam.Para32[0] = PhysPortIndex;
32440- EventParam.Para32[1] = (SK_U32)Val8;
32441- if (SkGeSirqEvent(pAC, IoC,
32442- SK_HWEV_SET_ROLE,
32443- EventParam) > 0) {
32444-
32445- SK_ERR_LOG(pAC, SK_ERRCL_SW,
32446- SK_PNMI_ERR042,
32447- SK_PNMI_ERR042MSG);
32448-
32449- *pLen = 0;
32450- return (SK_PNMI_ERR_GENERAL);
32451- }
32452- }
32453- }
32454- else {
32455- /*
32456- * Send an event with the new master/slave
32457- * (role) mode to the SIRQ module.
32458- */
32459- EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
32460- pAC, LogPortIndex);
32461- EventParam.Para32[1] = (SK_U32)Val8;
32462- if (SkGeSirqEvent(pAC, IoC,
32463- SK_HWEV_SET_ROLE, EventParam) > 0) {
32464-
32465- SK_ERR_LOG(pAC, SK_ERRCL_SW,
32466- SK_PNMI_ERR042,
32467- SK_PNMI_ERR042MSG);
32468-
32469- *pLen = 0;
32470- return (SK_PNMI_ERR_GENERAL);
32471- }
32472- }
32473-
32474- Offset += sizeof(char);
32475- break;
32476-
32477- case OID_SKGE_SPEED_MODE:
32478- /* Check the value range */
32479- Val8 = *(pBuf + Offset);
32480- if (Val8 == 0) {
32481-
32482- Offset += sizeof(char);
32483- break;
32484- }
32485- if (Val8 < (SK_LSPEED_AUTO) ||
32486- (LogPortIndex != 0 && Val8 > (SK_LSPEED_1000MBPS)) ||
32487- (LogPortIndex == 0 && Val8 > (SK_LSPEED_INDETERMINATED))) {
32488-
32489- *pLen = 0;
32490- return (SK_PNMI_ERR_BAD_VALUE);
32491- }
32492-
32493- /* The preset ends here */
32494- if (Action == SK_PNMI_PRESET) {
32495-
32496- return (SK_PNMI_ERR_OK);
32497- }
32498-
32499- if (LogPortIndex == 0) {
32500-
32501- /*
32502- * The virtual port consists of all currently
32503- * active ports. Find them and send an event
32504- * with the new flow control mode to SIRQ.
32505- */
32506- for (PhysPortIndex = 0;
32507- PhysPortIndex < PhysPortMax;
32508- PhysPortIndex ++) {
32509-
32510- if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
32511-
32512- continue;
32513- }
32514-
32515- EventParam.Para32[0] = PhysPortIndex;
32516- EventParam.Para32[1] = (SK_U32)Val8;
32517- if (SkGeSirqEvent(pAC, IoC,
32518- SK_HWEV_SET_SPEED,
32519- EventParam) > 0) {
32520-
32521- SK_ERR_LOG(pAC, SK_ERRCL_SW,
32522- SK_PNMI_ERR045,
32523- SK_PNMI_ERR045MSG);
32524-
32525- *pLen = 0;
32526- return (SK_PNMI_ERR_GENERAL);
32527- }
32528- }
32529- }
32530- else {
32531- /*
32532- * Send an event with the new flow control
32533- * mode to the SIRQ module.
32534- */
32535- EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(
32536- pAC, LogPortIndex);
32537- EventParam.Para32[1] = (SK_U32)Val8;
32538- if (SkGeSirqEvent(pAC, IoC,
32539- SK_HWEV_SET_SPEED,
32540- EventParam) > 0) {
32541-
32542- SK_ERR_LOG(pAC, SK_ERRCL_SW,
32543- SK_PNMI_ERR045,
32544- SK_PNMI_ERR045MSG);
32545-
32546- *pLen = 0;
32547- return (SK_PNMI_ERR_GENERAL);
32548- }
32549- }
32550- Offset += sizeof(char);
32551- break;
32552-
32553- case OID_SKGE_MTU :
32554- /* Check the value range */
32555- Val32 = *(SK_U32*)(pBuf + Offset);
32556- if (Val32 == 0) {
32557- /* mtu of this port remains unchanged */
32558- Offset += sizeof(SK_U32);
32559- break;
32560- }
32561- if (SK_DRIVER_PRESET_MTU(pAC, IoC, NetIndex, Val32) != 0) {
32562- *pLen = 0;
32563- return (SK_PNMI_ERR_BAD_VALUE);
32564- }
32565-
32566- /* The preset ends here */
32567- if (Action == SK_PNMI_PRESET) {
32568- return (SK_PNMI_ERR_OK);
32569- }
32570-
32571- if (SK_DRIVER_SET_MTU(pAC, IoC, NetIndex, Val32) != 0) {
32572- return (SK_PNMI_ERR_GENERAL);
32573- }
32574-
32575- Offset += sizeof(SK_U32);
32576- break;
32577-
32578-#ifdef SK_PHY_LP_MODE
32579- case OID_SKGE_PHY_LP_MODE:
32580- /* The preset ends here */
32581- if (Action == SK_PNMI_PRESET) {
32582-
32583- return (SK_PNMI_ERR_OK);
32584- }
32585-
32586- if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
32587- if (LogPortIndex == 0) {
32588- Offset = 0;
32589- continue;
32590- }
32591- else {
32592- /* Set value for physical ports */
32593- PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);
32594-
32595- switch (*(pBuf + Offset)) {
32596- case 0:
32597- /* If LowPowerMode is active, we can leave it. */
32598- if (pAC->GIni.GP[PhysPortIndex].PPhyPowerState) {
32599-
32600- Val32 = SkGmLeaveLowPowerMode(pAC, IoC, PhysPortIndex);
32601-
32602- if (pAC->GIni.GP[PhysPortIndex].PPhyPowerState < 3) {
32603-
32604- SkDrvInitAdapter(pAC);
32605- }
32606- break;
32607- }
32608- else {
32609- *pLen = 0;
32610- return (SK_PNMI_ERR_GENERAL);
32611- }
32612- case 1:
32613- case 2:
32614- case 3:
32615- case 4:
32616- /* If no LowPowerMode is active, we can enter it. */
32617- if (!pAC->GIni.GP[PhysPortIndex].PPhyPowerState) {
32618-
32619- if ((*(pBuf + Offset)) < 3) {
32620-
32621- SkDrvDeInitAdapter(pAC);
32622- }
32623-
32624- Val32 = SkGmEnterLowPowerMode(pAC, IoC, PhysPortIndex, *pBuf);
32625- break;
32626- }
32627- else {
32628- *pLen = 0;
32629- return (SK_PNMI_ERR_GENERAL);
32630- }
32631- default:
32632- *pLen = 0;
32633- return (SK_PNMI_ERR_BAD_VALUE);
32634- }
32635- }
32636- }
32637- else { /* DualNetMode */
32638-
32639- switch (*(pBuf + Offset)) {
32640- case 0:
32641- /* If we are in a LowPowerMode, we can leave it. */
32642- if (pAC->GIni.GP[PhysPortIndex].PPhyPowerState) {
32643-
32644- Val32 = SkGmLeaveLowPowerMode(pAC, IoC, PhysPortIndex);
32645-
32646- if (pAC->GIni.GP[PhysPortIndex].PPhyPowerState < 3) {
32647-
32648- SkDrvInitAdapter(pAC);
32649- }
32650- break;
32651- }
32652- else {
32653- *pLen = 0;
32654- return (SK_PNMI_ERR_GENERAL);
32655- }
32656-
32657- case 1:
32658- case 2:
32659- case 3:
32660- case 4:
32661- /* If we are not already in LowPowerMode, we can enter it. */
32662- if (!pAC->GIni.GP[PhysPortIndex].PPhyPowerState) {
32663-
32664- if ((*(pBuf + Offset)) < 3) {
32665-
32666- SkDrvDeInitAdapter(pAC);
32667- }
32668- else {
32669-
32670- Val32 = SkGmEnterLowPowerMode(pAC, IoC, PhysPortIndex, *pBuf);
32671- }
32672- break;
32673- }
32674- else {
32675- *pLen = 0;
32676- return (SK_PNMI_ERR_GENERAL);
32677- }
32678-
32679- default:
32680- *pLen = 0;
32681- return (SK_PNMI_ERR_BAD_VALUE);
32682- }
32683- }
32684- Offset += sizeof(SK_U8);
32685- break;
32686-#endif
32687-
32688- default:
32689- SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR,
32690- ("MacPrivateConf: Unknown OID should be handled before set"));
32691-
32692- *pLen = 0;
32693- return (SK_PNMI_ERR_GENERAL);
32694- }
32695- }
32696-
32697- return (SK_PNMI_ERR_OK);
32698-}
32699-
32700-/*****************************************************************************
32701- *
32702- * Monitor - OID handler function for RLMT_MONITOR_XXX
32703- *
32704- * Description:
32705- * Because RLMT currently does not support the monitoring of
32706- * remote adapter cards, we return always an empty table.
32707- *
32708- * Returns:
32709- * SK_PNMI_ERR_OK The request was successfully performed.
32710- * SK_PNMI_ERR_GENERAL A general severe internal error occured.
32711- * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
32712- * the correct data (e.g. a 32bit value is
32713- * needed, but a 16 bit value was passed).
32714- * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid
32715- * value range.
32716- * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set.
32717- * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
32718- * exist (e.g. port instance 3 on a two port
32719- * adapter.
32720- */
32721-PNMI_STATIC int Monitor(
32722-SK_AC *pAC, /* Pointer to adapter context */
32723-SK_IOC IoC, /* IO context handle */
32724-int Action, /* GET/PRESET/SET action */
32725-SK_U32 Id, /* Object ID that is to be processed */
32726-char *pBuf, /* Buffer used for the management data transfer */
32727-unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */
32728-SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
32729-unsigned int TableIndex, /* Index to the Id table */
32730-SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */
32731-{
32732- unsigned int Index;
32733- unsigned int Limit;
32734- unsigned int Offset;
32735- unsigned int Entries;
32736-
32737-
32738- /*
32739- * Calculate instance if wished.
32740- */
32741- /* XXX Not yet implemented. Return always an empty table. */
32742- Entries = 0;
32743-
32744- if ((Instance != (SK_U32)(-1))) {
32745-
32746- if ((Instance < 1) || (Instance > Entries)) {
32747-
32748- *pLen = 0;
32749- return (SK_PNMI_ERR_UNKNOWN_INST);
32750- }
32751-
32752- Index = (unsigned int)Instance - 1;
32753- Limit = (unsigned int)Instance;
32754- }
32755- else {
32756- Index = 0;
32757- Limit = Entries;
32758- }
32759-
32760- /*
32761- * Get/Set value
32762- */
32763- if (Action == SK_PNMI_GET) {
32764-
32765- for (Offset=0; Index < Limit; Index ++) {
32766-
32767- switch (Id) {
32768-
32769- case OID_SKGE_RLMT_MONITOR_INDEX:
32770- case OID_SKGE_RLMT_MONITOR_ADDR:
32771- case OID_SKGE_RLMT_MONITOR_ERRS:
32772- case OID_SKGE_RLMT_MONITOR_TIMESTAMP:
32773- case OID_SKGE_RLMT_MONITOR_ADMIN:
32774- break;
32775-
32776- default:
32777- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR046,
32778- SK_PNMI_ERR046MSG);
32779-
32780- *pLen = 0;
32781- return (SK_PNMI_ERR_GENERAL);
32782- }
32783- }
32784- *pLen = Offset;
32785- }
32786- else {
32787- /* Only MONITOR_ADMIN can be set */
32788- if (Id != OID_SKGE_RLMT_MONITOR_ADMIN) {
32789-
32790- *pLen = 0;
32791- return (SK_PNMI_ERR_READ_ONLY);
32792- }
32793-
32794- /* Check if the length is plausible */
32795- if (*pLen < (Limit - Index)) {
32796-
32797- return (SK_PNMI_ERR_TOO_SHORT);
32798- }
32799- /* Okay, we have a wide value range */
32800- if (*pLen != (Limit - Index)) {
32801-
32802- *pLen = 0;
32803- return (SK_PNMI_ERR_BAD_VALUE);
32804- }
32805-/*
32806- for (Offset=0; Index < Limit; Index ++) {
32807- }
32808-*/
32809-/*
32810- * XXX Not yet implemented. Return always BAD_VALUE, because the table
32811- * is empty.
32812- */
32813- *pLen = 0;
32814- return (SK_PNMI_ERR_BAD_VALUE);
32815- }
32816-
32817- return (SK_PNMI_ERR_OK);
32818-}
32819-
32820-/*****************************************************************************
32821- *
32822- * VirtualConf - Calculates the values of configuration OIDs for virtual port
32823- *
32824- * Description:
32825- * We handle here the get of the configuration group OIDs, which are
32826- * a little bit complicated. The virtual port consists of all currently
32827- * active physical ports. If multiple ports are active and configured
32828- * differently we get in some trouble to return a single value. So we
32829- * get the value of the first active port and compare it with that of
32830- * the other active ports. If they are not the same, we return a value
32831- * that indicates that the state is indeterminated.
32832- *
32833- * Returns:
32834- * Nothing
32835- */
32836-PNMI_STATIC void VirtualConf(
32837-SK_AC *pAC, /* Pointer to adapter context */
32838-SK_IOC IoC, /* IO context handle */
32839-SK_U32 Id, /* Object ID that is to be processed */
32840-char *pBuf) /* Buffer used for the management data transfer */
32841-{
32842- unsigned int PhysPortMax;
32843- unsigned int PhysPortIndex;
32844- SK_U8 Val8;
32845- SK_U32 Val32;
32846- SK_BOOL PortActiveFlag;
32847- SK_GEPORT *pPrt;
32848-
32849- *pBuf = 0;
32850- PortActiveFlag = SK_FALSE;
32851- PhysPortMax = pAC->GIni.GIMacsFound;
32852-
32853- for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;
32854- PhysPortIndex ++) {
32855-
32856- pPrt = &pAC->GIni.GP[PhysPortIndex];
32857-
32858- /* Check if the physical port is active */
32859- if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
32860-
32861- continue;
32862- }
32863-
32864- PortActiveFlag = SK_TRUE;
32865-
32866- switch (Id) {
32867-
32868- case OID_SKGE_PHY_TYPE:
32869- /* Check if it is the first active port */
32870- if (*pBuf == 0) {
32871- Val32 = pPrt->PhyType;
32872- SK_PNMI_STORE_U32(pBuf, Val32);
32873- continue;
32874- }
32875-
32876- case OID_SKGE_LINK_CAP:
32877-
32878- /*
32879- * Different capabilities should not happen, but
32880- * in the case of the cases OR them all together.
32881- * From a curious point of view the virtual port
32882- * is capable of all found capabilities.
32883- */
32884- *pBuf |= pPrt->PLinkCap;
32885- break;
32886-
32887- case OID_SKGE_LINK_MODE:
32888- /* Check if it is the first active port */
32889- if (*pBuf == 0) {
32890-
32891- *pBuf = pPrt->PLinkModeConf;
32892- continue;
32893- }
32894-
32895- /*
32896- * If we find an active port with a different link
32897- * mode than the first one we return a value that
32898- * indicates that the link mode is indeterminated.
32899- */
32900- if (*pBuf != pPrt->PLinkModeConf) {
32901-
32902- *pBuf = SK_LMODE_INDETERMINATED;
32903- }
32904- break;
32905-
32906- case OID_SKGE_LINK_MODE_STATUS:
32907- /* Get the link mode of the physical port */
32908- Val8 = CalculateLinkModeStatus(pAC, IoC, PhysPortIndex);
32909-
32910- /* Check if it is the first active port */
32911- if (*pBuf == 0) {
32912-
32913- *pBuf = Val8;
32914- continue;
32915- }
32916-
32917- /*
32918- * If we find an active port with a different link
32919- * mode status than the first one we return a value
32920- * that indicates that the link mode status is
32921- * indeterminated.
32922- */
32923- if (*pBuf != Val8) {
32924-
32925- *pBuf = SK_LMODE_STAT_INDETERMINATED;
32926- }
32927- break;
32928-
32929- case OID_SKGE_LINK_STATUS:
32930- /* Get the link status of the physical port */
32931- Val8 = CalculateLinkStatus(pAC, IoC, PhysPortIndex);
32932-
32933- /* Check if it is the first active port */
32934- if (*pBuf == 0) {
32935-
32936- *pBuf = Val8;
32937- continue;
32938- }
32939-
32940- /*
32941- * If we find an active port with a different link
32942- * status than the first one, we return a value
32943- * that indicates that the link status is
32944- * indeterminated.
32945- */
32946- if (*pBuf != Val8) {
32947-
32948- *pBuf = SK_PNMI_RLMT_LSTAT_INDETERMINATED;
32949- }
32950- break;
32951-
32952- case OID_SKGE_FLOWCTRL_CAP:
32953- /* Check if it is the first active port */
32954- if (*pBuf == 0) {
32955-
32956- *pBuf = pPrt->PFlowCtrlCap;
32957- continue;
32958- }
32959-
32960- /*
32961- * From a curious point of view the virtual port
32962- * is capable of all found capabilities.
32963- */
32964- *pBuf |= pPrt->PFlowCtrlCap;
32965- break;
32966-
32967- case OID_SKGE_FLOWCTRL_MODE:
32968- /* Check if it is the first active port */
32969- if (*pBuf == 0) {
32970-
32971- *pBuf = pPrt->PFlowCtrlMode;
32972- continue;
32973- }
32974-
32975- /*
32976- * If we find an active port with a different flow
32977- * control mode than the first one, we return a value
32978- * that indicates that the mode is indeterminated.
32979- */
32980- if (*pBuf != pPrt->PFlowCtrlMode) {
32981-
32982- *pBuf = SK_FLOW_MODE_INDETERMINATED;
32983- }
32984- break;
32985-
32986- case OID_SKGE_FLOWCTRL_STATUS:
32987- /* Check if it is the first active port */
32988- if (*pBuf == 0) {
32989-
32990- *pBuf = pPrt->PFlowCtrlStatus;
32991- continue;
32992- }
32993-
32994- /*
32995- * If we find an active port with a different flow
32996- * control status than the first one, we return a
32997- * value that indicates that the status is
32998- * indeterminated.
32999- */
33000- if (*pBuf != pPrt->PFlowCtrlStatus) {
33001-
33002- *pBuf = SK_FLOW_STAT_INDETERMINATED;
33003- }
33004- break;
33005-
33006- case OID_SKGE_PHY_OPERATION_CAP:
33007- /* Check if it is the first active port */
33008- if (*pBuf == 0) {
33009-
33010- *pBuf = pPrt->PMSCap;
33011- continue;
33012- }
33013-
33014- /*
33015- * From a curious point of view the virtual port
33016- * is capable of all found capabilities.
33017- */
33018- *pBuf |= pPrt->PMSCap;
33019- break;
33020-
33021- case OID_SKGE_PHY_OPERATION_MODE:
33022- /* Check if it is the first active port */
33023- if (*pBuf == 0) {
33024-
33025- *pBuf = pPrt->PMSMode;
33026- continue;
33027- }
33028-
33029- /*
33030- * If we find an active port with a different master/
33031- * slave mode than the first one, we return a value
33032- * that indicates that the mode is indeterminated.
33033- */
33034- if (*pBuf != pPrt->PMSMode) {
33035-
33036- *pBuf = SK_MS_MODE_INDETERMINATED;
33037- }
33038- break;
33039-
33040- case OID_SKGE_PHY_OPERATION_STATUS:
33041- /* Check if it is the first active port */
33042- if (*pBuf == 0) {
33043-
33044- *pBuf = pPrt->PMSStatus;
33045- continue;
33046- }
33047-
33048- /*
33049- * If we find an active port with a different master/
33050- * slave status than the first one, we return a
33051- * value that indicates that the status is
33052- * indeterminated.
33053- */
33054- if (*pBuf != pPrt->PMSStatus) {
33055-
33056- *pBuf = SK_MS_STAT_INDETERMINATED;
33057- }
33058- break;
33059-
33060- case OID_SKGE_SPEED_MODE:
33061- /* Check if it is the first active port */
33062- if (*pBuf == 0) {
33063-
33064- *pBuf = pPrt->PLinkSpeed;
33065- continue;
33066- }
33067-
33068- /*
33069- * If we find an active port with a different flow
33070- * control mode than the first one, we return a value
33071- * that indicates that the mode is indeterminated.
33072- */
33073- if (*pBuf != pPrt->PLinkSpeed) {
33074-
33075- *pBuf = SK_LSPEED_INDETERMINATED;
33076- }
33077- break;
33078-
33079- case OID_SKGE_SPEED_STATUS:
33080- /* Check if it is the first active port */
33081- if (*pBuf == 0) {
33082-
33083- *pBuf = pPrt->PLinkSpeedUsed;
33084- continue;
33085- }
33086-
33087- /*
33088- * If we find an active port with a different flow
33089- * control status than the first one, we return a
33090- * value that indicates that the status is
33091- * indeterminated.
33092- */
33093- if (*pBuf != pPrt->PLinkSpeedUsed) {
33094-
33095- *pBuf = SK_LSPEED_STAT_INDETERMINATED;
33096- }
33097- break;
33098- }
33099- }
33100-
33101- /*
33102- * If no port is active return an indeterminated answer
33103- */
33104- if (!PortActiveFlag) {
33105-
33106- switch (Id) {
33107-
33108- case OID_SKGE_LINK_CAP:
33109- *pBuf = SK_LMODE_CAP_INDETERMINATED;
33110- break;
33111-
33112- case OID_SKGE_LINK_MODE:
33113- *pBuf = SK_LMODE_INDETERMINATED;
33114- break;
33115-
33116- case OID_SKGE_LINK_MODE_STATUS:
33117- *pBuf = SK_LMODE_STAT_INDETERMINATED;
33118- break;
33119-
33120- case OID_SKGE_LINK_STATUS:
33121- *pBuf = SK_PNMI_RLMT_LSTAT_INDETERMINATED;
33122- break;
33123-
33124- case OID_SKGE_FLOWCTRL_CAP:
33125- case OID_SKGE_FLOWCTRL_MODE:
33126- *pBuf = SK_FLOW_MODE_INDETERMINATED;
33127- break;
33128-
33129- case OID_SKGE_FLOWCTRL_STATUS:
33130- *pBuf = SK_FLOW_STAT_INDETERMINATED;
33131- break;
33132-
33133- case OID_SKGE_PHY_OPERATION_CAP:
33134- *pBuf = SK_MS_CAP_INDETERMINATED;
33135- break;
33136-
33137- case OID_SKGE_PHY_OPERATION_MODE:
33138- *pBuf = SK_MS_MODE_INDETERMINATED;
33139- break;
33140-
33141- case OID_SKGE_PHY_OPERATION_STATUS:
33142- *pBuf = SK_MS_STAT_INDETERMINATED;
33143- break;
33144- case OID_SKGE_SPEED_CAP:
33145- *pBuf = SK_LSPEED_CAP_INDETERMINATED;
33146- break;
33147-
33148- case OID_SKGE_SPEED_MODE:
33149- *pBuf = SK_LSPEED_INDETERMINATED;
33150- break;
33151-
33152- case OID_SKGE_SPEED_STATUS:
33153- *pBuf = SK_LSPEED_STAT_INDETERMINATED;
33154- break;
33155- }
33156- }
33157-}
33158-
33159-/*****************************************************************************
33160- *
33161- * CalculateLinkStatus - Determins the link status of a physical port
33162- *
33163- * Description:
33164- * Determins the link status the following way:
33165- * LSTAT_PHY_DOWN: Link is down
33166- * LSTAT_AUTONEG: Auto-negotiation failed
33167- * LSTAT_LOG_DOWN: Link is up but RLMT did not yet put the port
33168- * logically up.
33169- * LSTAT_LOG_UP: RLMT marked the port as up
33170- *
33171- * Returns:
33172- * Link status of physical port
33173- */
33174-PNMI_STATIC SK_U8 CalculateLinkStatus(
33175-SK_AC *pAC, /* Pointer to adapter context */
33176-SK_IOC IoC, /* IO context handle */
33177-unsigned int PhysPortIndex) /* Physical port index */
33178-{
33179- SK_U8 Result;
33180-
33181- if (!pAC->GIni.GP[PhysPortIndex].PHWLinkUp) {
33182-
33183- Result = SK_PNMI_RLMT_LSTAT_PHY_DOWN;
33184- }
33185- else if (pAC->GIni.GP[PhysPortIndex].PAutoNegFail > 0) {
33186-
33187- Result = SK_PNMI_RLMT_LSTAT_AUTONEG;
33188- }
33189- else if (!pAC->Rlmt.Port[PhysPortIndex].PortDown) {
33190-
33191- Result = SK_PNMI_RLMT_LSTAT_LOG_UP;
33192- }
33193- else {
33194- Result = SK_PNMI_RLMT_LSTAT_LOG_DOWN;
33195- }
33196-
33197- return (Result);
33198-}
33199-
33200-/*****************************************************************************
33201- *
33202- * CalculateLinkModeStatus - Determins the link mode status of a phys. port
33203- *
33204- * Description:
33205- * The COMMON module only tells us if the mode is half or full duplex.
33206- * But in the decade of auto sensing it is useful for the user to
33207- * know if the mode was negotiated or forced. Therefore we have a
33208- * look to the mode, which was last used by the negotiation process.
33209- *
33210- * Returns:
33211- * The link mode status
33212- */
33213-PNMI_STATIC SK_U8 CalculateLinkModeStatus(
33214-SK_AC *pAC, /* Pointer to adapter context */
33215-SK_IOC IoC, /* IO context handle */
33216-unsigned int PhysPortIndex) /* Physical port index */
33217-{
33218- SK_U8 Result;
33219-
33220- /* Get the current mode, which can be full or half duplex */
33221- Result = pAC->GIni.GP[PhysPortIndex].PLinkModeStatus;
33222-
33223- /* Check if no valid mode could be found (link is down) */
33224- if (Result < SK_LMODE_STAT_HALF) {
33225-
33226- Result = SK_LMODE_STAT_UNKNOWN;
33227- }
33228- else if (pAC->GIni.GP[PhysPortIndex].PLinkMode >= SK_LMODE_AUTOHALF) {
33229-
33230- /*
33231- * Auto-negotiation was used to bring up the link. Change
33232- * the already found duplex status that it indicates
33233- * auto-negotiation was involved.
33234- */
33235- if (Result == SK_LMODE_STAT_HALF) {
33236-
33237- Result = SK_LMODE_STAT_AUTOHALF;
33238- }
33239- else if (Result == SK_LMODE_STAT_FULL) {
33240-
33241- Result = SK_LMODE_STAT_AUTOFULL;
33242- }
33243- }
33244-
33245- return (Result);
33246-}
33247-
33248-/*****************************************************************************
33249- *
33250- * GetVpdKeyArr - Obtain an array of VPD keys
33251- *
33252- * Description:
33253- * Read the VPD keys and build an array of VPD keys, which are
33254- * easy to access.
33255- *
33256- * Returns:
33257- * SK_PNMI_ERR_OK Task successfully performed.
33258- * SK_PNMI_ERR_GENERAL Something went wrong.
33259- */
33260-PNMI_STATIC int GetVpdKeyArr(
33261-SK_AC *pAC, /* Pointer to adapter context */
33262-SK_IOC IoC, /* IO context handle */
33263-char *pKeyArr, /* Ptr KeyArray */
33264-unsigned int KeyArrLen, /* Length of array in bytes */
33265-unsigned int *pKeyNo) /* Number of keys */
33266-{
33267- unsigned int BufKeysLen = SK_PNMI_VPD_BUFSIZE;
33268- char BufKeys[SK_PNMI_VPD_BUFSIZE];
33269- unsigned int StartOffset;
33270- unsigned int Offset;
33271- int Index;
33272- int Ret;
33273-
33274-
33275- SK_MEMSET(pKeyArr, 0, KeyArrLen);
33276-
33277- /*
33278- * Get VPD key list
33279- */
33280- Ret = VpdKeys(pAC, IoC, (char *)&BufKeys, (int *)&BufKeysLen,
33281- (int *)pKeyNo);
33282- if (Ret > 0) {
33283-
33284- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR014,
33285- SK_PNMI_ERR014MSG);
33286-
33287- return (SK_PNMI_ERR_GENERAL);
33288- }
33289- /* If no keys are available return now */
33290- if (*pKeyNo == 0 || BufKeysLen == 0) {
33291-
33292- return (SK_PNMI_ERR_OK);
33293- }
33294- /*
33295- * If the key list is too long for us trunc it and give a
33296- * errorlog notification. This case should not happen because
33297- * the maximum number of keys is limited due to RAM limitations
33298- */
33299- if (*pKeyNo > SK_PNMI_VPD_ENTRIES) {
33300-
33301- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR015,
33302- SK_PNMI_ERR015MSG);
33303-
33304- *pKeyNo = SK_PNMI_VPD_ENTRIES;
33305- }
33306-
33307- /*
33308- * Now build an array of fixed string length size and copy
33309- * the keys together.
33310- */
33311- for (Index = 0, StartOffset = 0, Offset = 0; Offset < BufKeysLen;
33312- Offset ++) {
33313-
33314- if (BufKeys[Offset] != 0) {
33315-
33316- continue;
33317- }
33318-
33319- if (Offset - StartOffset > SK_PNMI_VPD_KEY_SIZE) {
33320-
33321- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR016,
33322- SK_PNMI_ERR016MSG);
33323- return (SK_PNMI_ERR_GENERAL);
33324- }
33325-
33326- SK_STRNCPY(pKeyArr + Index * SK_PNMI_VPD_KEY_SIZE,
33327- &BufKeys[StartOffset], SK_PNMI_VPD_KEY_SIZE);
33328-
33329- Index ++;
33330- StartOffset = Offset + 1;
33331- }
33332-
33333- /* Last key not zero terminated? Get it anyway */
33334- if (StartOffset < Offset) {
33335-
33336- SK_STRNCPY(pKeyArr + Index * SK_PNMI_VPD_KEY_SIZE,
33337- &BufKeys[StartOffset], SK_PNMI_VPD_KEY_SIZE);
33338- }
33339-
33340- return (SK_PNMI_ERR_OK);
33341-}
33342-
33343-/*****************************************************************************
33344- *
33345- * SirqUpdate - Let the SIRQ update its internal values
33346- *
33347- * Description:
33348- * Just to be sure that the SIRQ module holds its internal data
33349- * structures up to date, we send an update event before we make
33350- * any access.
33351- *
33352- * Returns:
33353- * SK_PNMI_ERR_OK Task successfully performed.
33354- * SK_PNMI_ERR_GENERAL Something went wrong.
33355- */
33356-PNMI_STATIC int SirqUpdate(
33357-SK_AC *pAC, /* Pointer to adapter context */
33358-SK_IOC IoC) /* IO context handle */
33359-{
33360- SK_EVPARA EventParam;
33361-
33362-
33363- /* Was the module already updated during the current PNMI call? */
33364- if (pAC->Pnmi.SirqUpdatedFlag > 0) {
33365-
33366- return (SK_PNMI_ERR_OK);
33367- }
33368-
33369- /* Send an synchronuous update event to the module */
33370- SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
33371- if (SkGeSirqEvent(pAC, IoC, SK_HWEV_UPDATE_STAT, EventParam) > 0) {
33372-
33373- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR047,
33374- SK_PNMI_ERR047MSG);
33375-
33376- return (SK_PNMI_ERR_GENERAL);
33377- }
33378-
33379- return (SK_PNMI_ERR_OK);
33380-}
33381-
33382-/*****************************************************************************
33383- *
33384- * RlmtUpdate - Let the RLMT update its internal values
33385- *
33386- * Description:
33387- * Just to be sure that the RLMT module holds its internal data
33388- * structures up to date, we send an update event before we make
33389- * any access.
33390- *
33391- * Returns:
33392- * SK_PNMI_ERR_OK Task successfully performed.
33393- * SK_PNMI_ERR_GENERAL Something went wrong.
33394- */
33395-PNMI_STATIC int RlmtUpdate(
33396-SK_AC *pAC, /* Pointer to adapter context */
33397-SK_IOC IoC, /* IO context handle */
33398-SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */
33399-{
33400- SK_EVPARA EventParam;
33401-
33402-
33403- /* Was the module already updated during the current PNMI call? */
33404- if (pAC->Pnmi.RlmtUpdatedFlag > 0) {
33405-
33406- return (SK_PNMI_ERR_OK);
33407- }
33408-
33409- /* Send an synchronuous update event to the module */
33410- SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
33411- EventParam.Para32[0] = NetIndex;
33412- EventParam.Para32[1] = (SK_U32)-1;
33413- if (SkRlmtEvent(pAC, IoC, SK_RLMT_STATS_UPDATE, EventParam) > 0) {
33414-
33415- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR048,
33416- SK_PNMI_ERR048MSG);
33417-
33418- return (SK_PNMI_ERR_GENERAL);
33419- }
33420-
33421- return (SK_PNMI_ERR_OK);
33422-}
33423-
33424-/*****************************************************************************
33425- *
33426- * MacUpdate - Force the XMAC to output the current statistic
33427- *
33428- * Description:
33429- * The XMAC holds its statistic internally. To obtain the current
33430- * values we must send a command so that the statistic data will
33431- * be written to a predefined memory area on the adapter.
33432- *
33433- * Returns:
33434- * SK_PNMI_ERR_OK Task successfully performed.
33435- * SK_PNMI_ERR_GENERAL Something went wrong.
33436- */
33437-PNMI_STATIC int MacUpdate(
33438-SK_AC *pAC, /* Pointer to adapter context */
33439-SK_IOC IoC, /* IO context handle */
33440-unsigned int FirstMac, /* Index of the first Mac to be updated */
33441-unsigned int LastMac) /* Index of the last Mac to be updated */
33442-{
33443- unsigned int MacIndex;
33444-
33445- /*
33446- * Were the statistics already updated during the
33447- * current PNMI call?
33448- */
33449- if (pAC->Pnmi.MacUpdatedFlag > 0) {
33450-
33451- return (SK_PNMI_ERR_OK);
33452- }
33453-
33454- /* Send an update command to all MACs specified */
33455- for (MacIndex = FirstMac; MacIndex <= LastMac; MacIndex ++) {
33456-
33457- /*
33458- * 2002-09-13 pweber: Freeze the current SW counters.
33459- * (That should be done as close as
33460- * possible to the update of the
33461- * HW counters)
33462- */
33463- if (pAC->GIni.GIMacType == SK_MAC_XMAC) {
33464- pAC->Pnmi.BufPort[MacIndex] = pAC->Pnmi.Port[MacIndex];
33465- }
33466-
33467- /* 2002-09-13 pweber: Update the HW counter */
33468- if (pAC->GIni.GIFunc.pFnMacUpdateStats(pAC, IoC, MacIndex) != 0) {
33469-
33470- return (SK_PNMI_ERR_GENERAL);
33471- }
33472- }
33473-
33474- return (SK_PNMI_ERR_OK);
33475-}
33476-
33477-/*****************************************************************************
33478- *
33479- * GetStatVal - Retrieve an XMAC statistic counter
33480- *
33481- * Description:
33482- * Retrieves the statistic counter of a virtual or physical port. The
33483- * virtual port is identified by the index 0. It consists of all
33484- * currently active ports. To obtain the counter value for this port
33485- * we must add the statistic counter of all active ports. To grant
33486- * continuous counter values for the virtual port even when port
33487- * switches occur we must additionally add a delta value, which was
33488- * calculated during a SK_PNMI_EVT_RLMT_ACTIVE_UP event.
33489- *
33490- * Returns:
33491- * Requested statistic value
33492- */
33493-PNMI_STATIC SK_U64 GetStatVal(
33494-SK_AC *pAC, /* Pointer to adapter context */
33495-SK_IOC IoC, /* IO context handle */
33496-unsigned int LogPortIndex, /* Index of the logical Port to be processed */
33497-unsigned int StatIndex, /* Index to statistic value */
33498-SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */
33499-{
33500- unsigned int PhysPortIndex;
33501- unsigned int PhysPortMax;
33502- SK_U64 Val = 0;
33503-
33504-
33505- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* Dual net mode */
33506-
33507- PhysPortIndex = NetIndex;
33508-
33509- Val = GetPhysStatVal(pAC, IoC, PhysPortIndex, StatIndex);
33510- }
33511- else { /* Single Net mode */
33512-
33513- if (LogPortIndex == 0) {
33514-
33515- PhysPortMax = pAC->GIni.GIMacsFound;
33516-
33517- /* Add counter of all active ports */
33518- for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;
33519- PhysPortIndex ++) {
33520-
33521- if (pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {
33522-
33523- Val += GetPhysStatVal(pAC, IoC, PhysPortIndex, StatIndex);
33524- }
33525- }
33526-
33527- /* Correct value because of port switches */
33528- Val += pAC->Pnmi.VirtualCounterOffset[StatIndex];
33529- }
33530- else {
33531- /* Get counter value of physical port */
33532- PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);
33533-
33534- Val = GetPhysStatVal(pAC, IoC, PhysPortIndex, StatIndex);
33535- }
33536- }
33537- return (Val);
33538-}
33539-
33540-/*****************************************************************************
33541- *
33542- * GetPhysStatVal - Get counter value for physical port
33543- *
33544- * Description:
33545- * Builds a 64bit counter value. Except for the octet counters
33546- * the lower 32bit are counted in hardware and the upper 32bit
33547- * in software by monitoring counter overflow interrupts in the
33548- * event handler. To grant continous counter values during XMAC
33549- * resets (caused by a workaround) we must add a delta value.
33550- * The delta was calculated in the event handler when a
33551- * SK_PNMI_EVT_XMAC_RESET was received.
33552- *
33553- * Returns:
33554- * Counter value
33555- */
33556-PNMI_STATIC SK_U64 GetPhysStatVal(
33557-SK_AC *pAC, /* Pointer to adapter context */
33558-SK_IOC IoC, /* IO context handle */
33559-unsigned int PhysPortIndex, /* Index of the logical Port to be processed */
33560-unsigned int StatIndex) /* Index to statistic value */
33561-{
33562- SK_U64 Val = 0;
33563- SK_U32 LowVal = 0;
33564- SK_U32 HighVal = 0;
33565- SK_U16 Word;
33566- int MacType;
33567- unsigned int HelpIndex;
33568- SK_GEPORT *pPrt;
33569-
33570- SK_PNMI_PORT *pPnmiPrt;
33571- SK_GEMACFUNC *pFnMac;
33572-
33573- pPrt = &pAC->GIni.GP[PhysPortIndex];
33574-
33575- MacType = pAC->GIni.GIMacType;
33576-
33577- /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort) */
33578- if (MacType == SK_MAC_XMAC) {
33579- pPnmiPrt = &pAC->Pnmi.BufPort[PhysPortIndex];
33580- }
33581- else {
33582- pPnmiPrt = &pAC->Pnmi.Port[PhysPortIndex];
33583- }
33584-
33585- pFnMac = &pAC->GIni.GIFunc;
33586-
33587- switch (StatIndex) {
33588- case SK_PNMI_HTX:
33589- if (MacType == SK_MAC_GMAC) {
33590- (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
33591- StatAddr[SK_PNMI_HTX_BROADCAST][MacType].Reg,
33592- &LowVal);
33593- (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
33594- StatAddr[SK_PNMI_HTX_MULTICAST][MacType].Reg,
33595- &HighVal);
33596- LowVal += HighVal;
33597- (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
33598- StatAddr[SK_PNMI_HTX_UNICAST][MacType].Reg,
33599- &HighVal);
33600- LowVal += HighVal;
33601- }
33602- else {
33603- (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
33604- StatAddr[StatIndex][MacType].Reg,
33605- &LowVal);
33606- }
33607- HighVal = pPnmiPrt->CounterHigh[StatIndex];
33608- break;
33609-
33610- case SK_PNMI_HRX:
33611- if (MacType == SK_MAC_GMAC) {
33612- (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
33613- StatAddr[SK_PNMI_HRX_BROADCAST][MacType].Reg,
33614- &LowVal);
33615- (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
33616- StatAddr[SK_PNMI_HRX_MULTICAST][MacType].Reg,
33617- &HighVal);
33618- LowVal += HighVal;
33619- (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
33620- StatAddr[SK_PNMI_HRX_UNICAST][MacType].Reg,
33621- &HighVal);
33622- LowVal += HighVal;
33623- }
33624- else {
33625- (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
33626- StatAddr[StatIndex][MacType].Reg,
33627- &LowVal);
33628- }
33629- HighVal = pPnmiPrt->CounterHigh[StatIndex];
33630- break;
33631-
33632- case SK_PNMI_HTX_OCTET:
33633- case SK_PNMI_HRX_OCTET:
33634- (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
33635- StatAddr[StatIndex][MacType].Reg,
33636- &HighVal);
33637- (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
33638- StatAddr[StatIndex + 1][MacType].Reg,
33639- &LowVal);
33640- break;
33641-
33642- case SK_PNMI_HTX_BURST:
33643- case SK_PNMI_HTX_EXCESS_DEF:
33644- case SK_PNMI_HTX_CARRIER:
33645- /* Not supported by GMAC */
33646- if (MacType == SK_MAC_GMAC) {
33647- return (Val);
33648- }
33649-
33650- (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
33651- StatAddr[StatIndex][MacType].Reg,
33652- &LowVal);
33653- HighVal = pPnmiPrt->CounterHigh[StatIndex];
33654- break;
33655-
33656- case SK_PNMI_HTX_MACC:
33657- /* GMAC only supports PAUSE MAC control frames */
33658- if (MacType == SK_MAC_GMAC) {
33659- HelpIndex = SK_PNMI_HTX_PMACC;
33660- }
33661- else {
33662- HelpIndex = StatIndex;
33663- }
33664-
33665- (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
33666- StatAddr[HelpIndex][MacType].Reg,
33667- &LowVal);
33668-
33669- HighVal = pPnmiPrt->CounterHigh[StatIndex];
33670- break;
33671-
33672- case SK_PNMI_HTX_COL:
33673- case SK_PNMI_HRX_UNDERSIZE:
33674- /* Not supported by XMAC */
33675- if (MacType == SK_MAC_XMAC) {
33676- return (Val);
33677- }
33678-
33679- (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
33680- StatAddr[StatIndex][MacType].Reg,
33681- &LowVal);
33682- HighVal = pPnmiPrt->CounterHigh[StatIndex];
33683- break;
33684-
33685- case SK_PNMI_HTX_DEFFERAL:
33686- /* Not supported by GMAC */
33687- if (MacType == SK_MAC_GMAC) {
33688- return (Val);
33689- }
33690-
33691- /*
33692- * XMAC counts frames with deferred transmission
33693- * even in full-duplex mode.
33694- *
33695- * In full-duplex mode the counter remains constant!
33696- */
33697- if ((pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOFULL) ||
33698- (pPrt->PLinkModeStatus == SK_LMODE_STAT_FULL)) {
33699-
33700- LowVal = 0;
33701- HighVal = 0;
33702- }
33703- else {
33704- /* Otherwise get contents of hardware register */
33705- (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
33706- StatAddr[StatIndex][MacType].Reg,
33707- &LowVal);
33708- HighVal = pPnmiPrt->CounterHigh[StatIndex];
33709- }
33710- break;
33711-
33712- case SK_PNMI_HRX_BADOCTET:
33713- /* Not supported by XMAC */
33714- if (MacType == SK_MAC_XMAC) {
33715- return (Val);
33716- }
33717-
33718- (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
33719- StatAddr[StatIndex][MacType].Reg,
33720- &HighVal);
33721- (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
33722- StatAddr[StatIndex + 1][MacType].Reg,
33723- &LowVal);
33724- break;
33725-
33726- case SK_PNMI_HTX_OCTETLOW:
33727- case SK_PNMI_HRX_OCTETLOW:
33728- case SK_PNMI_HRX_BADOCTETLOW:
33729- return (Val);
33730-
33731- case SK_PNMI_HRX_LONGFRAMES:
33732- /* For XMAC the SW counter is managed by PNMI */
33733- if (MacType == SK_MAC_XMAC) {
33734- return (pPnmiPrt->StatRxLongFrameCts);
33735- }
33736-
33737- (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
33738- StatAddr[StatIndex][MacType].Reg,
33739- &LowVal);
33740- HighVal = pPnmiPrt->CounterHigh[StatIndex];
33741- break;
33742-
33743- case SK_PNMI_HRX_TOO_LONG:
33744- (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
33745- StatAddr[StatIndex][MacType].Reg,
33746- &LowVal);
33747- HighVal = pPnmiPrt->CounterHigh[StatIndex];
33748-
33749- Val = (((SK_U64)HighVal << 32) | (SK_U64)LowVal);
33750-
33751- if (MacType == SK_MAC_GMAC) {
33752- /* For GMAC the SW counter is additionally managed by PNMI */
33753- Val += pPnmiPrt->StatRxFrameTooLongCts;
33754- }
33755- else {
33756- /*
33757- * Frames longer than IEEE 802.3 frame max size are counted
33758- * by XMAC in frame_too_long counter even reception of long
33759- * frames was enabled and the frame was correct.
33760- * So correct the value by subtracting RxLongFrame counter.
33761- */
33762- Val -= pPnmiPrt->StatRxLongFrameCts;
33763- }
33764-
33765- LowVal = (SK_U32)Val;
33766- HighVal = (SK_U32)(Val >> 32);
33767- break;
33768-
33769- case SK_PNMI_HRX_SHORTS:
33770- /* Not supported by GMAC */
33771- if (MacType == SK_MAC_GMAC) {
33772- /* GM_RXE_FRAG?? */
33773- return (Val);
33774- }
33775-
33776- /*
33777- * XMAC counts short frame errors even if link down (#10620)
33778- *
33779- * If link-down the counter remains constant
33780- */
33781- if (pPrt->PLinkModeStatus != SK_LMODE_STAT_UNKNOWN) {
33782-
33783- /* Otherwise get incremental difference */
33784- (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
33785- StatAddr[StatIndex][MacType].Reg,
33786- &LowVal);
33787- HighVal = pPnmiPrt->CounterHigh[StatIndex];
33788-
33789- Val = (((SK_U64)HighVal << 32) | (SK_U64)LowVal);
33790- Val -= pPnmiPrt->RxShortZeroMark;
33791-
33792- LowVal = (SK_U32)Val;
33793- HighVal = (SK_U32)(Val >> 32);
33794- }
33795- break;
33796-
33797- case SK_PNMI_HRX_MACC:
33798- case SK_PNMI_HRX_MACC_UNKWN:
33799- case SK_PNMI_HRX_BURST:
33800- case SK_PNMI_HRX_MISSED:
33801- case SK_PNMI_HRX_FRAMING:
33802- case SK_PNMI_HRX_CARRIER:
33803- case SK_PNMI_HRX_IRLENGTH:
33804- case SK_PNMI_HRX_SYMBOL:
33805- case SK_PNMI_HRX_CEXT:
33806- /* Not supported by GMAC */
33807- if (MacType == SK_MAC_GMAC) {
33808- return (Val);
33809- }
33810-
33811- (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
33812- StatAddr[StatIndex][MacType].Reg,
33813- &LowVal);
33814- HighVal = pPnmiPrt->CounterHigh[StatIndex];
33815- break;
33816-
33817- case SK_PNMI_HRX_PMACC_ERR:
33818- /* For GMAC the SW counter is managed by PNMI */
33819- if (MacType == SK_MAC_GMAC) {
33820- return (pPnmiPrt->StatRxPMaccErr);
33821- }
33822-
33823- (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
33824- StatAddr[StatIndex][MacType].Reg,
33825- &LowVal);
33826- HighVal = pPnmiPrt->CounterHigh[StatIndex];
33827- break;
33828-
33829- /* SW counter managed by PNMI */
33830- case SK_PNMI_HTX_SYNC:
33831- LowVal = (SK_U32)pPnmiPrt->StatSyncCts;
33832- HighVal = (SK_U32)(pPnmiPrt->StatSyncCts >> 32);
33833- break;
33834-
33835- /* SW counter managed by PNMI */
33836- case SK_PNMI_HTX_SYNC_OCTET:
33837- LowVal = (SK_U32)pPnmiPrt->StatSyncOctetsCts;
33838- HighVal = (SK_U32)(pPnmiPrt->StatSyncOctetsCts >> 32);
33839- break;
33840-
33841- case SK_PNMI_HRX_FCS:
33842- /*
33843- * Broadcom filters FCS errors and counts it in
33844- * Receive Error Counter register
33845- */
33846- if (pPrt->PhyType == SK_PHY_BCOM) {
33847- /* do not read while not initialized (PHY_READ hangs!)*/
33848- if (pPrt->PState != SK_PRT_RESET) {
33849- SkXmPhyRead(pAC, IoC, PhysPortIndex, PHY_BCOM_RE_CTR, &Word);
33850-
33851- LowVal = Word;
33852- }
33853- HighVal = pPnmiPrt->CounterHigh[StatIndex];
33854- }
33855- else {
33856- (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
33857- StatAddr[StatIndex][MacType].Reg,
33858- &LowVal);
33859- HighVal = pPnmiPrt->CounterHigh[StatIndex];
33860- }
33861- break;
33862-
33863- default:
33864- (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
33865- StatAddr[StatIndex][MacType].Reg,
33866- &LowVal);
33867- HighVal = pPnmiPrt->CounterHigh[StatIndex];
33868- break;
33869- }
33870-
33871- Val = (((SK_U64)HighVal << 32) | (SK_U64)LowVal);
33872-
33873- /* Correct value because of possible XMAC reset. XMAC Errata #2 */
33874- Val += pPnmiPrt->CounterOffset[StatIndex];
33875-
33876- return (Val);
33877-}
33878-
33879-/*****************************************************************************
33880- *
33881- * ResetCounter - Set all counters and timestamps to zero
33882- *
33883- * Description:
33884- * Notifies other common modules which store statistic data to
33885- * reset their counters and finally reset our own counters.
33886- *
33887- * Returns:
33888- * Nothing
33889- */
33890-PNMI_STATIC void ResetCounter(
33891-SK_AC *pAC, /* Pointer to adapter context */
33892-SK_IOC IoC, /* IO context handle */
33893-SK_U32 NetIndex)
33894-{
33895- unsigned int PhysPortIndex;
33896- SK_EVPARA EventParam;
33897-
33898-
33899- SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));
33900-
33901- /* Notify sensor module */
33902- SkEventQueue(pAC, SKGE_I2C, SK_I2CEV_CLEAR, EventParam);
33903-
33904- /* Notify RLMT module */
33905- EventParam.Para32[0] = NetIndex;
33906- EventParam.Para32[1] = (SK_U32)-1;
33907- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STATS_CLEAR, EventParam);
33908- EventParam.Para32[1] = 0;
33909-
33910- /* Notify SIRQ module */
33911- SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_CLEAR_STAT, EventParam);
33912-
33913- /* Notify CSUM module */
33914-#ifdef SK_USE_CSUM
33915- EventParam.Para32[0] = NetIndex;
33916- EventParam.Para32[1] = (SK_U32)-1;
33917- SkEventQueue(pAC, SKGE_CSUM, SK_CSUM_EVENT_CLEAR_PROTO_STATS,
33918- EventParam);
33919-#endif /* SK_USE_CSUM */
33920-
33921- /* Clear XMAC statistic */
33922- for (PhysPortIndex = 0; PhysPortIndex <
33923- (unsigned int)pAC->GIni.GIMacsFound; PhysPortIndex ++) {
33924-
33925- (void)pAC->GIni.GIFunc.pFnMacResetCounter(pAC, IoC, PhysPortIndex);
33926-
33927- SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex].CounterHigh,
33928- 0, sizeof(pAC->Pnmi.Port[PhysPortIndex].CounterHigh));
33929- SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex].
33930- CounterOffset, 0, sizeof(pAC->Pnmi.Port[
33931- PhysPortIndex].CounterOffset));
33932- SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex].StatSyncCts,
33933- 0, sizeof(pAC->Pnmi.Port[PhysPortIndex].StatSyncCts));
33934- SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex].
33935- StatSyncOctetsCts, 0, sizeof(pAC->Pnmi.Port[
33936- PhysPortIndex].StatSyncOctetsCts));
33937- SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex].
33938- StatRxLongFrameCts, 0, sizeof(pAC->Pnmi.Port[
33939- PhysPortIndex].StatRxLongFrameCts));
33940- SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex].
33941- StatRxFrameTooLongCts, 0, sizeof(pAC->Pnmi.Port[
33942- PhysPortIndex].StatRxFrameTooLongCts));
33943- SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex].
33944- StatRxPMaccErr, 0, sizeof(pAC->Pnmi.Port[
33945- PhysPortIndex].StatRxPMaccErr));
33946- }
33947-
33948- /*
33949- * Clear local statistics
33950- */
33951- SK_MEMSET((char *)&pAC->Pnmi.VirtualCounterOffset, 0,
33952- sizeof(pAC->Pnmi.VirtualCounterOffset));
33953- pAC->Pnmi.RlmtChangeCts = 0;
33954- pAC->Pnmi.RlmtChangeTime = 0;
33955- SK_MEMSET((char *)&pAC->Pnmi.RlmtChangeEstimate.EstValue[0], 0,
33956- sizeof(pAC->Pnmi.RlmtChangeEstimate.EstValue));
33957- pAC->Pnmi.RlmtChangeEstimate.EstValueIndex = 0;
33958- pAC->Pnmi.RlmtChangeEstimate.Estimate = 0;
33959- pAC->Pnmi.Port[NetIndex].TxSwQueueMax = 0;
33960- pAC->Pnmi.Port[NetIndex].TxRetryCts = 0;
33961- pAC->Pnmi.Port[NetIndex].RxIntrCts = 0;
33962- pAC->Pnmi.Port[NetIndex].TxIntrCts = 0;
33963- pAC->Pnmi.Port[NetIndex].RxNoBufCts = 0;
33964- pAC->Pnmi.Port[NetIndex].TxNoBufCts = 0;
33965- pAC->Pnmi.Port[NetIndex].TxUsedDescrNo = 0;
33966- pAC->Pnmi.Port[NetIndex].RxDeliveredCts = 0;
33967- pAC->Pnmi.Port[NetIndex].RxOctetsDeliveredCts = 0;
33968- pAC->Pnmi.Port[NetIndex].ErrRecoveryCts = 0;
33969-}
33970-
33971-/*****************************************************************************
33972- *
33973- * GetTrapEntry - Get an entry in the trap buffer
33974- *
33975- * Description:
33976- * The trap buffer stores various events. A user application somehow
33977- * gets notified that an event occured and retrieves the trap buffer
33978- * contens (or simply polls the buffer). The buffer is organized as
33979- * a ring which stores the newest traps at the beginning. The oldest
33980- * traps are overwritten by the newest ones. Each trap entry has a
33981- * unique number, so that applications may detect new trap entries.
33982- *
33983- * Returns:
33984- * A pointer to the trap entry
33985- */
33986-PNMI_STATIC char* GetTrapEntry(
33987-SK_AC *pAC, /* Pointer to adapter context */
33988-SK_U32 TrapId, /* SNMP ID of the trap */
33989-unsigned int Size) /* Space needed for trap entry */
33990-{
33991- unsigned int BufPad = pAC->Pnmi.TrapBufPad;
33992- unsigned int BufFree = pAC->Pnmi.TrapBufFree;
33993- unsigned int Beg = pAC->Pnmi.TrapQueueBeg;
33994- unsigned int End = pAC->Pnmi.TrapQueueEnd;
33995- char *pBuf = &pAC->Pnmi.TrapBuf[0];
33996- int Wrap;
33997- unsigned int NeededSpace;
33998- unsigned int EntrySize;
33999- SK_U32 Val32;
34000- SK_U64 Val64;
34001-
34002-
34003- /* Last byte of entry will get a copy of the entry length */
34004- Size ++;
34005-
34006- /*
34007- * Calculate needed buffer space */
34008- if (Beg >= Size) {
34009-
34010- NeededSpace = Size;
34011- Wrap = SK_FALSE;
34012- }
34013- else {
34014- NeededSpace = Beg + Size;
34015- Wrap = SK_TRUE;
34016- }
34017-
34018- /*
34019- * Check if enough buffer space is provided. Otherwise
34020- * free some entries. Leave one byte space between begin
34021- * and end of buffer to make it possible to detect whether
34022- * the buffer is full or empty
34023- */
34024- while (BufFree < NeededSpace + 1) {
34025-
34026- if (End == 0) {
34027-
34028- End = SK_PNMI_TRAP_QUEUE_LEN;
34029- }
34030-
34031- EntrySize = (unsigned int)*((unsigned char *)pBuf + End - 1);
34032- BufFree += EntrySize;
34033- End -= EntrySize;
34034-#ifdef DEBUG
34035- SK_MEMSET(pBuf + End, (char)(-1), EntrySize);
34036-#endif /* DEBUG */
34037- if (End == BufPad) {
34038-#ifdef DEBUG
34039- SK_MEMSET(pBuf, (char)(-1), End);
34040-#endif /* DEBUG */
34041- BufFree += End;
34042- End = 0;
34043- BufPad = 0;
34044- }
34045- }
34046-
34047- /*
34048- * Insert new entry as first entry. Newest entries are
34049- * stored at the beginning of the queue.
34050- */
34051- if (Wrap) {
34052-
34053- BufPad = Beg;
34054- Beg = SK_PNMI_TRAP_QUEUE_LEN - Size;
34055- }
34056- else {
34057- Beg = Beg - Size;
34058- }
34059- BufFree -= NeededSpace;
34060-
34061- /* Save the current offsets */
34062- pAC->Pnmi.TrapQueueBeg = Beg;
34063- pAC->Pnmi.TrapQueueEnd = End;
34064- pAC->Pnmi.TrapBufPad = BufPad;
34065- pAC->Pnmi.TrapBufFree = BufFree;
34066-
34067- /* Initialize the trap entry */
34068- *(pBuf + Beg + Size - 1) = (char)Size;
34069- *(pBuf + Beg) = (char)Size;
34070- Val32 = (pAC->Pnmi.TrapUnique) ++;
34071- SK_PNMI_STORE_U32(pBuf + Beg + 1, Val32);
34072- SK_PNMI_STORE_U32(pBuf + Beg + 1 + sizeof(SK_U32), TrapId);
34073- Val64 = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC));
34074- SK_PNMI_STORE_U64(pBuf + Beg + 1 + 2 * sizeof(SK_U32), Val64);
34075-
34076- return (pBuf + Beg);
34077-}
34078-
34079-/*****************************************************************************
34080- *
34081- * CopyTrapQueue - Copies the trap buffer for the TRAP OID
34082- *
34083- * Description:
34084- * On a query of the TRAP OID the trap buffer contents will be
34085- * copied continuously to the request buffer, which must be large
34086- * enough. No length check is performed.
34087- *
34088- * Returns:
34089- * Nothing
34090- */
34091-PNMI_STATIC void CopyTrapQueue(
34092-SK_AC *pAC, /* Pointer to adapter context */
34093-char *pDstBuf) /* Buffer to which the queued traps will be copied */
34094-{
34095- unsigned int BufPad = pAC->Pnmi.TrapBufPad;
34096- unsigned int Trap = pAC->Pnmi.TrapQueueBeg;
34097- unsigned int End = pAC->Pnmi.TrapQueueEnd;
34098- char *pBuf = &pAC->Pnmi.TrapBuf[0];
34099- unsigned int Len;
34100- unsigned int DstOff = 0;
34101-
34102-
34103- while (Trap != End) {
34104-
34105- Len = (unsigned int)*(pBuf + Trap);
34106-
34107- /*
34108- * Last byte containing a copy of the length will
34109- * not be copied.
34110- */
34111- *(pDstBuf + DstOff) = (char)(Len - 1);
34112- SK_MEMCPY(pDstBuf + DstOff + 1, pBuf + Trap + 1, Len - 2);
34113- DstOff += Len - 1;
34114-
34115- Trap += Len;
34116- if (Trap == SK_PNMI_TRAP_QUEUE_LEN) {
34117-
34118- Trap = BufPad;
34119- }
34120- }
34121-}
34122-
34123-/*****************************************************************************
34124- *
34125- * GetTrapQueueLen - Get the length of the trap buffer
34126- *
34127- * Description:
34128- * Evaluates the number of currently stored traps and the needed
34129- * buffer size to retrieve them.
34130- *
34131- * Returns:
34132- * Nothing
34133- */
34134-PNMI_STATIC void GetTrapQueueLen(
34135-SK_AC *pAC, /* Pointer to adapter context */
34136-unsigned int *pLen, /* Length in Bytes of all queued traps */
34137-unsigned int *pEntries) /* Returns number of trapes stored in queue */
34138-{
34139- unsigned int BufPad = pAC->Pnmi.TrapBufPad;
34140- unsigned int Trap = pAC->Pnmi.TrapQueueBeg;
34141- unsigned int End = pAC->Pnmi.TrapQueueEnd;
34142- char *pBuf = &pAC->Pnmi.TrapBuf[0];
34143- unsigned int Len;
34144- unsigned int Entries = 0;
34145- unsigned int TotalLen = 0;
34146-
34147-
34148- while (Trap != End) {
34149-
34150- Len = (unsigned int)*(pBuf + Trap);
34151- TotalLen += Len - 1;
34152- Entries ++;
34153-
34154- Trap += Len;
34155- if (Trap == SK_PNMI_TRAP_QUEUE_LEN) {
34156-
34157- Trap = BufPad;
34158- }
34159- }
34160-
34161- *pEntries = Entries;
34162- *pLen = TotalLen;
34163-}
34164-
34165-/*****************************************************************************
34166- *
34167- * QueueSimpleTrap - Store a simple trap to the trap buffer
34168- *
34169- * Description:
34170- * A simple trap is a trap with now additional data. It consists
34171- * simply of a trap code.
34172- *
34173- * Returns:
34174- * Nothing
34175- */
34176-PNMI_STATIC void QueueSimpleTrap(
34177-SK_AC *pAC, /* Pointer to adapter context */
34178-SK_U32 TrapId) /* Type of sensor trap */
34179-{
34180- GetTrapEntry(pAC, TrapId, SK_PNMI_TRAP_SIMPLE_LEN);
34181-}
34182-
34183-/*****************************************************************************
34184- *
34185- * QueueSensorTrap - Stores a sensor trap in the trap buffer
34186- *
34187- * Description:
34188- * Gets an entry in the trap buffer and fills it with sensor related
34189- * data.
34190- *
34191- * Returns:
34192- * Nothing
34193- */
34194-PNMI_STATIC void QueueSensorTrap(
34195-SK_AC *pAC, /* Pointer to adapter context */
34196-SK_U32 TrapId, /* Type of sensor trap */
34197-unsigned int SensorIndex) /* Index of sensor which caused the trap */
34198-{
34199- char *pBuf;
34200- unsigned int Offset;
34201- unsigned int DescrLen;
34202- SK_U32 Val32;
34203-
34204-
34205- /* Get trap buffer entry */
34206- DescrLen = SK_STRLEN(pAC->I2c.SenTable[SensorIndex].SenDesc);
34207- pBuf = GetTrapEntry(pAC, TrapId,
34208- SK_PNMI_TRAP_SENSOR_LEN_BASE + DescrLen);
34209- Offset = SK_PNMI_TRAP_SIMPLE_LEN;
34210-
34211- /* Store additionally sensor trap related data */
34212- Val32 = OID_SKGE_SENSOR_INDEX;
34213- SK_PNMI_STORE_U32(pBuf + Offset, Val32);
34214- *(pBuf + Offset + 4) = 4;
34215- Val32 = (SK_U32)SensorIndex;
34216- SK_PNMI_STORE_U32(pBuf + Offset + 5, Val32);
34217- Offset += 9;
34218-
34219- Val32 = (SK_U32)OID_SKGE_SENSOR_DESCR;
34220- SK_PNMI_STORE_U32(pBuf + Offset, Val32);
34221- *(pBuf + Offset + 4) = (char)DescrLen;
34222- SK_MEMCPY(pBuf + Offset + 5, pAC->I2c.SenTable[SensorIndex].SenDesc,
34223- DescrLen);
34224- Offset += DescrLen + 5;
34225-
34226- Val32 = OID_SKGE_SENSOR_TYPE;
34227- SK_PNMI_STORE_U32(pBuf + Offset, Val32);
34228- *(pBuf + Offset + 4) = 1;
34229- *(pBuf + Offset + 5) = (char)pAC->I2c.SenTable[SensorIndex].SenType;
34230- Offset += 6;
34231-
34232- Val32 = OID_SKGE_SENSOR_VALUE;
34233- SK_PNMI_STORE_U32(pBuf + Offset, Val32);
34234- *(pBuf + Offset + 4) = 4;
34235- Val32 = (SK_U32)pAC->I2c.SenTable[SensorIndex].SenValue;
34236- SK_PNMI_STORE_U32(pBuf + Offset + 5, Val32);
34237-}
34238-
34239-/*****************************************************************************
34240- *
34241- * QueueRlmtNewMacTrap - Store a port switch trap in the trap buffer
34242- *
34243- * Description:
34244- * Nothing further to explain.
34245- *
34246- * Returns:
34247- * Nothing
34248- */
34249-PNMI_STATIC void QueueRlmtNewMacTrap(
34250-SK_AC *pAC, /* Pointer to adapter context */
34251-unsigned int ActiveMac) /* Index (0..n) of the currently active port */
34252-{
34253- char *pBuf;
34254- SK_U32 Val32;
34255-
34256-
34257- pBuf = GetTrapEntry(pAC, OID_SKGE_TRAP_RLMT_CHANGE_PORT,
34258- SK_PNMI_TRAP_RLMT_CHANGE_LEN);
34259-
34260- Val32 = OID_SKGE_RLMT_PORT_ACTIVE;
34261- SK_PNMI_STORE_U32(pBuf + SK_PNMI_TRAP_SIMPLE_LEN, Val32);
34262- *(pBuf + SK_PNMI_TRAP_SIMPLE_LEN + 4) = 1;
34263- *(pBuf + SK_PNMI_TRAP_SIMPLE_LEN + 5) = (char)ActiveMac;
34264-}
34265-
34266-/*****************************************************************************
34267- *
34268- * QueueRlmtPortTrap - Store port related RLMT trap to trap buffer
34269- *
34270- * Description:
34271- * Nothing further to explain.
34272- *
34273- * Returns:
34274- * Nothing
34275- */
34276-PNMI_STATIC void QueueRlmtPortTrap(
34277-SK_AC *pAC, /* Pointer to adapter context */
34278-SK_U32 TrapId, /* Type of RLMT port trap */
34279-unsigned int PortIndex) /* Index of the port, which changed its state */
34280-{
34281- char *pBuf;
34282- SK_U32 Val32;
34283-
34284-
34285- pBuf = GetTrapEntry(pAC, TrapId, SK_PNMI_TRAP_RLMT_PORT_LEN);
34286-
34287- Val32 = OID_SKGE_RLMT_PORT_INDEX;
34288- SK_PNMI_STORE_U32(pBuf + SK_PNMI_TRAP_SIMPLE_LEN, Val32);
34289- *(pBuf + SK_PNMI_TRAP_SIMPLE_LEN + 4) = 1;
34290- *(pBuf + SK_PNMI_TRAP_SIMPLE_LEN + 5) = (char)PortIndex;
34291-}
34292-
34293-/*****************************************************************************
34294- *
34295- * CopyMac - Copies a MAC address
34296- *
34297- * Description:
34298- * Nothing further to explain.
34299- *
34300- * Returns:
34301- * Nothing
34302- */
34303-PNMI_STATIC void CopyMac(
34304-char *pDst, /* Pointer to destination buffer */
34305-SK_MAC_ADDR *pMac) /* Pointer of Source */
34306-{
34307- int i;
34308-
34309-
34310- for (i = 0; i < sizeof(SK_MAC_ADDR); i ++) {
34311-
34312- *(pDst + i) = pMac->a[i];
34313- }
34314-}
34315-
34316-#ifdef SK_POWER_MGMT
34317-/*****************************************************************************
34318- *
34319- * PowerManagement - OID handler function of PowerManagement OIDs
34320- *
34321- * Description:
34322- * The code is simple. No description necessary.
34323- *
34324- * Returns:
34325- * SK_PNMI_ERR_OK The request was successfully performed.
34326- * SK_PNMI_ERR_GENERAL A general severe internal error occured.
34327- * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
34328- * the correct data (e.g. a 32bit value is
34329- * needed, but a 16 bit value was passed).
34330- * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
34331- * exist (e.g. port instance 3 on a two port
34332- * adapter.
34333- */
34334-
34335-PNMI_STATIC int PowerManagement(
34336-SK_AC *pAC, /* Pointer to adapter context */
34337-SK_IOC IoC, /* IO context handle */
34338-int Action, /* Get/PreSet/Set action */
34339-SK_U32 Id, /* Object ID that is to be processed */
34340-char *pBuf, /* Buffer to which to mgmt data will be retrieved */
34341-unsigned int *pLen, /* On call: buffer length. On return: used buffer */
34342-SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
34343-unsigned int TableIndex, /* Index to the Id table */
34344-SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */
34345-{
34346-
34347- SK_U32 RetCode = SK_PNMI_ERR_GENERAL;
34348-
34349- /*
34350- * Check instance. We only handle single instance variables
34351- */
34352- if (Instance != (SK_U32)(-1) && Instance != 1) {
34353-
34354- *pLen = 0;
34355- return (SK_PNMI_ERR_UNKNOWN_INST);
34356- }
34357-
34358-
34359- /* Check length */
34360- switch (Id) {
34361-
34362- case OID_PNP_CAPABILITIES:
34363- if (*pLen < sizeof(SK_PNP_CAPABILITIES)) {
34364-
34365- *pLen = sizeof(SK_PNP_CAPABILITIES);
34366- return (SK_PNMI_ERR_TOO_SHORT);
34367- }
34368- break;
34369-
34370- case OID_PNP_SET_POWER:
34371- case OID_PNP_QUERY_POWER:
34372- if (*pLen < sizeof(SK_DEVICE_POWER_STATE))
34373- {
34374- *pLen = sizeof(SK_DEVICE_POWER_STATE);
34375- return (SK_PNMI_ERR_TOO_SHORT);
34376- }
34377- break;
34378-
34379- case OID_PNP_ADD_WAKE_UP_PATTERN:
34380- case OID_PNP_REMOVE_WAKE_UP_PATTERN:
34381- if (*pLen < sizeof(SK_PM_PACKET_PATTERN)) {
34382-
34383- *pLen = sizeof(SK_PM_PACKET_PATTERN);
34384- return (SK_PNMI_ERR_TOO_SHORT);
34385- }
34386- break;
34387-
34388- case OID_PNP_ENABLE_WAKE_UP:
34389- if (*pLen < sizeof(SK_U32)) {
34390-
34391- *pLen = sizeof(SK_U32);
34392- return (SK_PNMI_ERR_TOO_SHORT);
34393- }
34394- break;
34395- }
34396-
34397- /*
34398- * Perform action
34399- */
34400- if (Action == SK_PNMI_GET) {
34401-
34402- /*
34403- * Get value
34404- */
34405- switch (Id) {
34406-
34407- case OID_PNP_CAPABILITIES:
34408- RetCode = SkPowerQueryPnPCapabilities(pAC, IoC, pBuf, pLen);
34409- break;
34410-
34411- case OID_PNP_QUERY_POWER:
34412- /* The Windows DDK describes: An OID_PNP_QUERY_POWER requests
34413- the miniport to indicate whether it can transition its NIC
34414- to the low-power state.
34415- A miniport driver must always return NDIS_STATUS_SUCCESS
34416- to a query of OID_PNP_QUERY_POWER. */
34417- *pLen = sizeof(SK_DEVICE_POWER_STATE);
34418- RetCode = SK_PNMI_ERR_OK;
34419- break;
34420-
34421- /* NDIS handles these OIDs as write-only.
34422- * So in case of get action the buffer with written length = 0
34423- * is returned
34424- */
34425- case OID_PNP_SET_POWER:
34426- case OID_PNP_ADD_WAKE_UP_PATTERN:
34427- case OID_PNP_REMOVE_WAKE_UP_PATTERN:
34428- *pLen = 0;
34429- RetCode = SK_PNMI_ERR_NOT_SUPPORTED;
34430- break;
34431-
34432- case OID_PNP_ENABLE_WAKE_UP:
34433- RetCode = SkPowerGetEnableWakeUp(pAC, IoC, pBuf, pLen);
34434- break;
34435-
34436- default:
34437- RetCode = SK_PNMI_ERR_GENERAL;
34438- break;
34439- }
34440-
34441- return (RetCode);
34442- }
34443-
34444-
34445- /*
34446- * Perform preset or set
34447- */
34448-
34449- /* POWER module does not support PRESET action */
34450- if (Action == SK_PNMI_PRESET) {
34451- return (SK_PNMI_ERR_OK);
34452- }
34453-
34454- switch (Id) {
34455- case OID_PNP_SET_POWER:
34456- RetCode = SkPowerSetPower(pAC, IoC, pBuf, pLen);
34457- break;
34458-
34459- case OID_PNP_ADD_WAKE_UP_PATTERN:
34460- RetCode = SkPowerAddWakeUpPattern(pAC, IoC, pBuf, pLen);
34461- break;
34462-
34463- case OID_PNP_REMOVE_WAKE_UP_PATTERN:
34464- RetCode = SkPowerRemoveWakeUpPattern(pAC, IoC, pBuf, pLen);
34465- break;
34466-
34467- case OID_PNP_ENABLE_WAKE_UP:
34468- RetCode = SkPowerSetEnableWakeUp(pAC, IoC, pBuf, pLen);
34469- break;
34470-
34471- default:
34472- RetCode = SK_PNMI_ERR_READ_ONLY;
34473- }
34474-
34475- return (RetCode);
34476-}
34477-#endif /* SK_POWER_MGMT */
34478-
34479-#ifdef SK_DIAG_SUPPORT
34480-/*****************************************************************************
34481- *
34482- * DiagActions - OID handler function of Diagnostic driver
34483- *
34484- * Description:
34485- * The code is simple. No description necessary.
34486- *
34487- * Returns:
34488- * SK_PNMI_ERR_OK The request was successfully performed.
34489- * SK_PNMI_ERR_GENERAL A general severe internal error occured.
34490- * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
34491- * the correct data (e.g. a 32bit value is
34492- * needed, but a 16 bit value was passed).
34493- * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
34494- * exist (e.g. port instance 3 on a two port
34495- * adapter.
34496- */
34497-
34498-PNMI_STATIC int DiagActions(
34499-SK_AC *pAC, /* Pointer to adapter context */
34500-SK_IOC IoC, /* IO context handle */
34501-int Action, /* GET/PRESET/SET action */
34502-SK_U32 Id, /* Object ID that is to be processed */
34503-char *pBuf, /* Buffer used for the management data transfer */
34504-unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */
34505-SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */
34506-unsigned int TableIndex, /* Index to the Id table */
34507-SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */
34508-{
34509-
34510- SK_U32 DiagStatus;
34511- SK_U32 RetCode = SK_PNMI_ERR_GENERAL;
34512-
34513- /*
34514- * Check instance. We only handle single instance variables.
34515- */
34516- if (Instance != (SK_U32)(-1) && Instance != 1) {
34517-
34518- *pLen = 0;
34519- return (SK_PNMI_ERR_UNKNOWN_INST);
34520- }
34521-
34522- /*
34523- * Check length.
34524- */
34525- switch (Id) {
34526-
34527- case OID_SKGE_DIAG_MODE:
34528- if (*pLen < sizeof(SK_U32)) {
34529-
34530- *pLen = sizeof(SK_U32);
34531- return (SK_PNMI_ERR_TOO_SHORT);
34532- }
34533- break;
34534-
34535- default:
34536- SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR040, SK_PNMI_ERR040MSG);
34537- *pLen = 0;
34538- return (SK_PNMI_ERR_GENERAL);
34539- }
34540-
34541- /* Perform action. */
34542-
34543- /* GET value. */
34544- if (Action == SK_PNMI_GET) {
34545-
34546- switch (Id) {
34547-
34548- case OID_SKGE_DIAG_MODE:
34549- DiagStatus = pAC->Pnmi.DiagAttached;
34550- SK_PNMI_STORE_U32(pBuf, DiagStatus);
34551- *pLen = sizeof(SK_U32);
34552- RetCode = SK_PNMI_ERR_OK;
34553- break;
34554-
34555- default:
34556- *pLen = 0;
34557- RetCode = SK_PNMI_ERR_GENERAL;
34558- break;
34559- }
34560- return (RetCode);
34561- }
34562-
34563- /* From here SET or PRESET value. */
34564-
34565- /* PRESET value is not supported. */
34566- if (Action == SK_PNMI_PRESET) {
34567- return (SK_PNMI_ERR_OK);
34568- }
34569-
34570- /* SET value. */
34571- switch (Id) {
34572- case OID_SKGE_DIAG_MODE:
34573-
34574- /* Handle the SET. */
34575- switch (*pBuf) {
34576-
34577- /* Attach the DIAG to this adapter. */
34578- case SK_DIAG_ATTACHED:
34579- /* Check if we come from running */
34580- if (pAC->Pnmi.DiagAttached == SK_DIAG_RUNNING) {
34581-
34582- RetCode = SkDrvLeaveDiagMode(pAC);
34583-
34584- }
34585- else if (pAC->Pnmi.DiagAttached == SK_DIAG_IDLE) {
34586-
34587- RetCode = SK_PNMI_ERR_OK;
34588- }
34589-
34590- else {
34591-
34592- RetCode = SK_PNMI_ERR_GENERAL;
34593-
34594- }
34595-
34596- if (RetCode == SK_PNMI_ERR_OK) {
34597-
34598- pAC->Pnmi.DiagAttached = SK_DIAG_ATTACHED;
34599- }
34600- break;
34601-
34602- /* Enter the DIAG mode in the driver. */
34603- case SK_DIAG_RUNNING:
34604- RetCode = SK_PNMI_ERR_OK;
34605-
34606- /*
34607- * If DiagAttached is set, we can tell the driver
34608- * to enter the DIAG mode.
34609- */
34610- if (pAC->Pnmi.DiagAttached == SK_DIAG_ATTACHED) {
34611- /* If DiagMode is not active, we can enter it. */
34612- if (!pAC->DiagModeActive) {
34613-
34614- RetCode = SkDrvEnterDiagMode(pAC);
34615- }
34616- else {
34617-
34618- RetCode = SK_PNMI_ERR_GENERAL;
34619- }
34620- }
34621- else {
34622-
34623- RetCode = SK_PNMI_ERR_GENERAL;
34624- }
34625-
34626- if (RetCode == SK_PNMI_ERR_OK) {
34627-
34628- pAC->Pnmi.DiagAttached = SK_DIAG_RUNNING;
34629- }
34630- break;
34631-
34632- case SK_DIAG_IDLE:
34633- /* Check if we come from running */
34634- if (pAC->Pnmi.DiagAttached == SK_DIAG_RUNNING) {
34635-
34636- RetCode = SkDrvLeaveDiagMode(pAC);
34637-
34638- }
34639- else if (pAC->Pnmi.DiagAttached == SK_DIAG_ATTACHED) {
34640-
34641- RetCode = SK_PNMI_ERR_OK;
34642- }
34643-
34644- else {
34645-
34646- RetCode = SK_PNMI_ERR_GENERAL;
34647-
34648- }
34649-
34650- if (RetCode == SK_PNMI_ERR_OK) {
34651-
34652- pAC->Pnmi.DiagAttached = SK_DIAG_IDLE;
34653- }
34654- break;
34655-
34656- default:
34657- RetCode = SK_PNMI_ERR_BAD_VALUE;
34658- break;
34659- }
34660- break;
34661-
34662- default:
34663- RetCode = SK_PNMI_ERR_GENERAL;
34664- }
34665-
34666- if (RetCode == SK_PNMI_ERR_OK) {
34667- *pLen = sizeof(SK_U32);
34668- }
34669- else {
34670-
34671- *pLen = 0;
34672- }
34673- return (RetCode);
34674-}
34675-#endif /* SK_DIAG_SUPPORT */
34676-
34677-/*****************************************************************************
34678- *
34679- * Vct - OID handler function of OIDs
34680- *
34681- * Description:
34682- * The code is simple. No description necessary.
34683- *
34684- * Returns:
34685- * SK_PNMI_ERR_OK The request was performed successfully.
34686- * SK_PNMI_ERR_GENERAL A general severe internal error occured.
34687- * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain
34688- * the correct data (e.g. a 32bit value is
34689- * needed, but a 16 bit value was passed).
34690- * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
34691- * exist (e.g. port instance 3 on a two port
34692- * adapter).
34693- * SK_PNMI_ERR_READ_ONLY Only the Get action is allowed.
34694- *
34695- */
34696-
34697-PNMI_STATIC int Vct(
34698-SK_AC *pAC, /* Pointer to adapter context */
34699-SK_IOC IoC, /* IO context handle */
34700-int Action, /* GET/PRESET/SET action */
34701-SK_U32 Id, /* Object ID that is to be processed */
34702-char *pBuf, /* Buffer used for the management data transfer */
34703-unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */
34704-SK_U32 Instance, /* Instance (-1,2..n) that is to be queried */
34705-unsigned int TableIndex, /* Index to the Id table */
34706-SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */
34707-{
34708- SK_GEPORT *pPrt;
34709- SK_PNMI_VCT *pVctBackupData;
34710- SK_U32 LogPortMax;
34711- SK_U32 PhysPortMax;
34712- SK_U32 PhysPortIndex;
34713- SK_U32 Limit;
34714- SK_U32 Offset;
34715- SK_BOOL Link;
34716- SK_U32 RetCode = SK_PNMI_ERR_GENERAL;
34717- int i;
34718- SK_EVPARA Para;
34719- SK_U32 CableLength;
34720-
34721- /*
34722- * Calculate the port indexes from the instance.
34723- */
34724- PhysPortMax = pAC->GIni.GIMacsFound;
34725- LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax);
34726-
34727- /* Dual net mode? */
34728- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
34729- LogPortMax--;
34730- }
34731-
34732- if ((Instance != (SK_U32) (-1))) {
34733- /* Check instance range. */
34734- if ((Instance < 2) || (Instance > LogPortMax)) {
34735- *pLen = 0;
34736- return (SK_PNMI_ERR_UNKNOWN_INST);
34737- }
34738-
34739- if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
34740- PhysPortIndex = NetIndex;
34741- }
34742- else {
34743- PhysPortIndex = Instance - 2;
34744- }
34745- Limit = PhysPortIndex + 1;
34746- }
34747- else {
34748- /*
34749- * Instance == (SK_U32) (-1), get all Instances of that OID.
34750- *
34751- * Not implemented yet. May be used in future releases.
34752- */
34753- PhysPortIndex = 0;
34754- Limit = PhysPortMax;
34755- }
34756-
34757- pPrt = &pAC->GIni.GP[PhysPortIndex];
34758- if (pPrt->PHWLinkUp) {
34759- Link = SK_TRUE;
34760- }
34761- else {
34762- Link = SK_FALSE;
34763- }
34764-
34765- /* Check MAC type */
34766- if (pPrt->PhyType != SK_PHY_MARV_COPPER) {
34767- *pLen = 0;
34768- return (SK_PNMI_ERR_GENERAL);
34769- }
34770-
34771- /* Initialize backup data pointer. */
34772- pVctBackupData = &pAC->Pnmi.VctBackup[PhysPortIndex];
34773-
34774- /* Check action type */
34775- if (Action == SK_PNMI_GET) {
34776- /* Check length */
34777- switch (Id) {
34778-
34779- case OID_SKGE_VCT_GET:
34780- if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_PNMI_VCT)) {
34781- *pLen = (Limit - PhysPortIndex) * sizeof(SK_PNMI_VCT);
34782- return (SK_PNMI_ERR_TOO_SHORT);
34783- }
34784- break;
34785-
34786- case OID_SKGE_VCT_STATUS:
34787- if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U8)) {
34788- *pLen = (Limit - PhysPortIndex) * sizeof(SK_U8);
34789- return (SK_PNMI_ERR_TOO_SHORT);
34790- }
34791- break;
34792-
34793- default:
34794- *pLen = 0;
34795- return (SK_PNMI_ERR_GENERAL);
34796- }
34797-
34798- /* Get value */
34799- Offset = 0;
34800- for (; PhysPortIndex < Limit; PhysPortIndex++) {
34801- switch (Id) {
34802-
34803- case OID_SKGE_VCT_GET:
34804- if ((Link == SK_FALSE) &&
34805- (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_PENDING)) {
34806- RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_FALSE);
34807- if (RetCode == 0) {
34808- pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_PENDING;
34809- pAC->Pnmi.VctStatus[PhysPortIndex] |=
34810- (SK_PNMI_VCT_NEW_VCT_DATA | SK_PNMI_VCT_TEST_DONE);
34811-
34812- /* Copy results for later use to PNMI struct. */
34813- for (i = 0; i < 4; i++) {
34814- if (pPrt->PMdiPairSts[i] == SK_PNMI_VCT_NORMAL_CABLE) {
34815- if ((pPrt->PMdiPairLen[i] > 35) && (pPrt->PMdiPairLen[i] < 0xff)) {
34816- pPrt->PMdiPairSts[i] = SK_PNMI_VCT_IMPEDANCE_MISMATCH;
34817- }
34818- }
34819- if ((pPrt->PMdiPairLen[i] > 35) && (pPrt->PMdiPairLen[i] != 0xff)) {
34820- CableLength = 1000 * (((175 * pPrt->PMdiPairLen[i]) / 210) - 28);
34821- }
34822- else {
34823- CableLength = 0;
34824- }
34825- pVctBackupData->PMdiPairLen[i] = CableLength;
34826- pVctBackupData->PMdiPairSts[i] = pPrt->PMdiPairSts[i];
34827- }
34828-
34829- Para.Para32[0] = PhysPortIndex;
34830- Para.Para32[1] = -1;
34831- SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Para);
34832- SkEventDispatcher(pAC, IoC);
34833- }
34834- else {
34835- ; /* VCT test is running. */
34836- }
34837- }
34838-
34839- /* Get all results. */
34840- CheckVctStatus(pAC, IoC, pBuf, Offset, PhysPortIndex);
34841- Offset += sizeof(SK_U8);
34842- *(pBuf + Offset) = pPrt->PCableLen;
34843- Offset += sizeof(SK_U8);
34844- for (i = 0; i < 4; i++) {
34845- SK_PNMI_STORE_U32((pBuf + Offset), pVctBackupData->PMdiPairLen[i]);
34846- Offset += sizeof(SK_U32);
34847- }
34848- for (i = 0; i < 4; i++) {
34849- *(pBuf + Offset) = pVctBackupData->PMdiPairSts[i];
34850- Offset += sizeof(SK_U8);
34851- }
34852-
34853- RetCode = SK_PNMI_ERR_OK;
34854- break;
34855-
34856- case OID_SKGE_VCT_STATUS:
34857- CheckVctStatus(pAC, IoC, pBuf, Offset, PhysPortIndex);
34858- Offset += sizeof(SK_U8);
34859- RetCode = SK_PNMI_ERR_OK;
34860- break;
34861-
34862- default:
34863- *pLen = 0;
34864- return (SK_PNMI_ERR_GENERAL);
34865- }
34866- } /* for */
34867- *pLen = Offset;
34868- return (RetCode);
34869-
34870- } /* if SK_PNMI_GET */
34871-
34872- /*
34873- * From here SET or PRESET action. Check if the passed
34874- * buffer length is plausible.
34875- */
34876-
34877- /* Check length */
34878- switch (Id) {
34879- case OID_SKGE_VCT_SET:
34880- if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U32)) {
34881- *pLen = (Limit - PhysPortIndex) * sizeof(SK_U32);
34882- return (SK_PNMI_ERR_TOO_SHORT);
34883- }
34884- break;
34885-
34886- default:
34887- *pLen = 0;
34888- return (SK_PNMI_ERR_GENERAL);
34889- }
34890-
34891- /*
34892- * Perform preset or set.
34893- */
34894-
34895- /* VCT does not support PRESET action. */
34896- if (Action == SK_PNMI_PRESET) {
34897- return (SK_PNMI_ERR_OK);
34898- }
34899-
34900- Offset = 0;
34901- for (; PhysPortIndex < Limit; PhysPortIndex++) {
34902- switch (Id) {
34903- case OID_SKGE_VCT_SET: /* Start VCT test. */
34904- if (Link == SK_FALSE) {
34905- SkGeStopPort(pAC, IoC, PhysPortIndex, SK_STOP_ALL, SK_SOFT_RST);
34906-
34907- RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_TRUE);
34908- if (RetCode == 0) { /* RetCode: 0 => Start! */
34909- pAC->Pnmi.VctStatus[PhysPortIndex] |= SK_PNMI_VCT_PENDING;
34910- pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_NEW_VCT_DATA;
34911- pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_LINK;
34912-
34913- /*
34914- * Start VCT timer counter.
34915- */
34916- SK_MEMSET((char *) &Para, 0, sizeof(Para));
34917- Para.Para32[0] = PhysPortIndex;
34918- Para.Para32[1] = -1;
34919- SkTimerStart(pAC, IoC, &pAC->Pnmi.VctTimeout[PhysPortIndex].VctTimer,
34920- 4000000, SKGE_PNMI, SK_PNMI_EVT_VCT_RESET, Para);
34921- SK_PNMI_STORE_U32((pBuf + Offset), RetCode);
34922- RetCode = SK_PNMI_ERR_OK;
34923- }
34924- else { /* RetCode: 2 => Running! */
34925- SK_PNMI_STORE_U32((pBuf + Offset), RetCode);
34926- RetCode = SK_PNMI_ERR_OK;
34927- }
34928- }
34929- else { /* RetCode: 4 => Link! */
34930- RetCode = 4;
34931- SK_PNMI_STORE_U32((pBuf + Offset), RetCode);
34932- RetCode = SK_PNMI_ERR_OK;
34933- }
34934- Offset += sizeof(SK_U32);
34935- break;
34936-
34937- default:
34938- *pLen = 0;
34939- return (SK_PNMI_ERR_GENERAL);
34940- }
34941- } /* for */
34942- *pLen = Offset;
34943- return (RetCode);
34944-
34945-} /* Vct */
34946-
34947-
34948-PNMI_STATIC void CheckVctStatus(
34949-SK_AC *pAC,
34950-SK_IOC IoC,
34951-char *pBuf,
34952-SK_U32 Offset,
34953-SK_U32 PhysPortIndex)
34954-{
34955- SK_GEPORT *pPrt;
34956- SK_PNMI_VCT *pVctData;
34957- SK_U32 RetCode;
34958-
34959- pPrt = &pAC->GIni.GP[PhysPortIndex];
34960-
34961- pVctData = (SK_PNMI_VCT *) (pBuf + Offset);
34962- pVctData->VctStatus = SK_PNMI_VCT_NONE;
34963-
34964- if (!pPrt->PHWLinkUp) {
34965-
34966- /* Was a VCT test ever made before? */
34967- if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_TEST_DONE) {
34968- if ((pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_LINK)) {
34969- pVctData->VctStatus |= SK_PNMI_VCT_OLD_VCT_DATA;
34970- }
34971- else {
34972- pVctData->VctStatus |= SK_PNMI_VCT_NEW_VCT_DATA;
34973- }
34974- }
34975-
34976- /* Check VCT test status. */
34977- RetCode = SkGmCableDiagStatus(pAC,IoC, PhysPortIndex, SK_FALSE);
34978- if (RetCode == 2) { /* VCT test is running. */
34979- pVctData->VctStatus |= SK_PNMI_VCT_RUNNING;
34980- }
34981- else { /* VCT data was copied to pAC here. Check PENDING state. */
34982- if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_PENDING) {
34983- pVctData->VctStatus |= SK_PNMI_VCT_NEW_VCT_DATA;
34984- }
34985- }
34986-
34987- if (pPrt->PCableLen != 0xff) { /* Old DSP value. */
34988- pVctData->VctStatus |= SK_PNMI_VCT_OLD_DSP_DATA;
34989- }
34990- }
34991- else {
34992-
34993- /* Was a VCT test ever made before? */
34994- if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_TEST_DONE) {
34995- pVctData->VctStatus &= ~SK_PNMI_VCT_NEW_VCT_DATA;
34996- pVctData->VctStatus |= SK_PNMI_VCT_OLD_VCT_DATA;
34997- }
34998-
34999- /* DSP only valid in 100/1000 modes. */
35000- if (pAC->GIni.GP[PhysPortIndex].PLinkSpeedUsed !=
35001- SK_LSPEED_STAT_10MBPS) {
35002- pVctData->VctStatus |= SK_PNMI_VCT_NEW_DSP_DATA;
35003- }
35004- }
35005-} /* CheckVctStatus */
35006-
35007-
35008-/*****************************************************************************
35009- *
35010- * SkPnmiGenIoctl - Handles new generic PNMI IOCTL, calls the needed
35011- * PNMI function depending on the subcommand and
35012- * returns all data belonging to the complete database
35013- * or OID request.
35014- *
35015- * Description:
35016- * Looks up the requested subcommand, calls the corresponding handler
35017- * function and passes all required parameters to it.
35018- * The function is called by the driver. It is needed to handle the new
35019- * generic PNMI IOCTL. This IOCTL is given to the driver and contains both
35020- * the OID and a subcommand to decide what kind of request has to be done.
35021- *
35022- * Returns:
35023- * SK_PNMI_ERR_OK The request was successfully performed
35024- * SK_PNMI_ERR_GENERAL A general severe internal error occured
35025- * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to take
35026- * the data.
35027- * SK_PNMI_ERR_UNKNOWN_OID The requested OID is unknown
35028- * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't
35029- * exist (e.g. port instance 3 on a two port
35030- * adapter.
35031- */
35032-int SkPnmiGenIoctl(
35033-SK_AC *pAC, /* Pointer to adapter context struct */
35034-SK_IOC IoC, /* I/O context */
35035-void *pBuf, /* Buffer used for the management data transfer */
35036-unsigned int *pLen, /* Length of buffer */
35037-SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */
35038-{
35039-SK_I32 Mode; /* Store value of subcommand. */
35040-SK_U32 Oid; /* Store value of OID. */
35041-int ReturnCode; /* Store return value to show status of PNMI action. */
35042-int HeaderLength; /* Length of desired action plus OID. */
35043-
35044- ReturnCode = SK_PNMI_ERR_GENERAL;
35045-
35046- SK_MEMCPY(&Mode, pBuf, sizeof(SK_I32));
35047- SK_MEMCPY(&Oid, (char *) pBuf + sizeof(SK_I32), sizeof(SK_U32));
35048- HeaderLength = sizeof(SK_I32) + sizeof(SK_U32);
35049- *pLen = *pLen - HeaderLength;
35050- SK_MEMCPY((char *) pBuf + sizeof(SK_I32), (char *) pBuf + HeaderLength, *pLen);
35051-
35052- switch(Mode) {
35053- case SK_GET_SINGLE_VAR:
35054- ReturnCode = SkPnmiGetVar(pAC, IoC, Oid,
35055- (char *) pBuf + sizeof(SK_I32), pLen,
35056- ((SK_U32) (-1)), NetIndex);
35057- SK_PNMI_STORE_U32(pBuf, ReturnCode);
35058- *pLen = *pLen + sizeof(SK_I32);
35059- break;
35060- case SK_PRESET_SINGLE_VAR:
35061- ReturnCode = SkPnmiPreSetVar(pAC, IoC, Oid,
35062- (char *) pBuf + sizeof(SK_I32), pLen,
35063- ((SK_U32) (-1)), NetIndex);
35064- SK_PNMI_STORE_U32(pBuf, ReturnCode);
35065- *pLen = *pLen + sizeof(SK_I32);
35066- break;
35067- case SK_SET_SINGLE_VAR:
35068- ReturnCode = SkPnmiSetVar(pAC, IoC, Oid,
35069- (char *) pBuf + sizeof(SK_I32), pLen,
35070- ((SK_U32) (-1)), NetIndex);
35071- SK_PNMI_STORE_U32(pBuf, ReturnCode);
35072- *pLen = *pLen + sizeof(SK_I32);
35073- break;
35074- case SK_GET_FULL_MIB:
35075- ReturnCode = SkPnmiGetStruct(pAC, IoC, pBuf, pLen, NetIndex);
35076- break;
35077- case SK_PRESET_FULL_MIB:
35078- ReturnCode = SkPnmiPreSetStruct(pAC, IoC, pBuf, pLen, NetIndex);
35079- break;
35080- case SK_SET_FULL_MIB:
35081- ReturnCode = SkPnmiSetStruct(pAC, IoC, pBuf, pLen, NetIndex);
35082- break;
35083- default:
35084- break;
35085- }
35086-
35087- return (ReturnCode);
35088-
35089-} /* SkGeIocGen */
35090+/*****************************************************************************\r
35091+ *\r
35092+ * Name: skgepnmi.c\r
35093+ * Project: Gigabit Ethernet Adapters, PNMI-Module\r
35094+ * Version: $Revision$\r
35095+ * Date: $Date$\r
35096+ * Purpose: Private Network Management Interface\r
35097+ *\r
35098+ ****************************************************************************/\r
35099+\r
35100+/******************************************************************************\r
35101+ *\r
35102+ * (C)Copyright 1998-2002 SysKonnect GmbH.\r
35103+ * (C)Copyright 2002-2003 Marvell.\r
35104+ *\r
35105+ * This program is free software; you can redistribute it and/or modify\r
35106+ * it under the terms of the GNU General Public License as published by\r
35107+ * the Free Software Foundation; either version 2 of the License, or\r
35108+ * (at your option) any later version.\r
35109+ *\r
35110+ * The information in this file is provided "AS IS" without warranty.\r
35111+ *\r
35112+ ******************************************************************************/\r
35113+\r
35114+#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))\r
35115+static const char SysKonnectFileId[] =\r
35116+ "@(#) $Id$ (C) Marvell.";\r
35117+#endif\r
35118+\r
35119+#include "h/skdrv1st.h"\r
35120+#include "h/sktypes.h"\r
35121+#include "h/xmac_ii.h"\r
35122+#include "h/skdebug.h"\r
35123+#include "h/skqueue.h"\r
35124+#include "h/skgepnmi.h"\r
35125+#include "h/skgesirq.h"\r
35126+#include "h/skcsum.h"\r
35127+#include "h/skvpd.h"\r
35128+#include "h/skgehw.h"\r
35129+#include "h/sky2le.h"\r
35130+#include "h/skgeinit.h"\r
35131+#include "h/skdrv2nd.h"\r
35132+#include "h/skgepnm2.h"\r
35133+#ifdef SK_POWER_MGMT\r
35134+#include "h/skgepmgt.h"\r
35135+#endif /* SK_POWER_MGMT */\r
35136+\r
35137+/* defines *******************************************************************/\r
35138+\r
35139+#ifndef DEBUG\r
35140+#define PNMI_STATIC static\r
35141+#else /* DEBUG */\r
35142+#define PNMI_STATIC\r
35143+#endif /* DEBUG */\r
35144+\r
35145+/*\r
35146+ * Public Function prototypes\r
35147+ */\r
35148+int SkPnmiInit(SK_AC *pAC, SK_IOC IoC, int level);\r
35149+int SkPnmiGetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void *pBuf,\r
35150+ unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex);\r
35151+int SkPnmiPreSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void *pBuf,\r
35152+ unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex);\r
35153+int SkPnmiSetVar(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, void *pBuf,\r
35154+ unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex);\r
35155+int SkPnmiGetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf,\r
35156+ unsigned int *pLen, SK_U32 NetIndex);\r
35157+int SkPnmiPreSetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf,\r
35158+ unsigned int *pLen, SK_U32 NetIndex);\r
35159+int SkPnmiSetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf,\r
35160+ unsigned int *pLen, SK_U32 NetIndex);\r
35161+int SkPnmiEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Param);\r
35162+int SkPnmiGenIoctl(SK_AC *pAC, SK_IOC IoC, void * pBuf,\r
35163+ unsigned int * pLen, SK_U32 NetIndex);\r
35164+\r
35165+/*\r
35166+ * Private Function prototypes\r
35167+ */\r
35168+\r
35169+PNMI_STATIC SK_U8 CalculateLinkModeStatus(SK_AC *pAC, SK_IOC IoC, unsigned int\r
35170+ PhysPortIndex);\r
35171+PNMI_STATIC SK_U8 CalculateLinkStatus(SK_AC *pAC, SK_IOC IoC, unsigned int\r
35172+ PhysPortIndex);\r
35173+PNMI_STATIC void CopyMac(char *pDst, SK_MAC_ADDR *pMac);\r
35174+PNMI_STATIC void CopyTrapQueue(SK_AC *pAC, char *pDstBuf);\r
35175+PNMI_STATIC SK_U64 GetPhysStatVal(SK_AC *pAC, SK_IOC IoC,\r
35176+ unsigned int PhysPortIndex, unsigned int StatIndex);\r
35177+PNMI_STATIC SK_U64 GetStatVal(SK_AC *pAC, SK_IOC IoC, unsigned int LogPortIndex,\r
35178+ unsigned int StatIndex, SK_U32 NetIndex);\r
35179+PNMI_STATIC char* GetTrapEntry(SK_AC *pAC, SK_U32 TrapId, unsigned int Size);\r
35180+PNMI_STATIC void GetTrapQueueLen(SK_AC *pAC, unsigned int *pLen,\r
35181+ unsigned int *pEntries);\r
35182+PNMI_STATIC int GetVpdKeyArr(SK_AC *pAC, SK_IOC IoC, char *pKeyArr,\r
35183+ unsigned int KeyArrLen, unsigned int *pKeyNo);\r
35184+PNMI_STATIC int LookupId(SK_U32 Id);\r
35185+PNMI_STATIC int MacUpdate(SK_AC *pAC, SK_IOC IoC, unsigned int FirstMac,\r
35186+ unsigned int LastMac);\r
35187+PNMI_STATIC int PnmiStruct(SK_AC *pAC, SK_IOC IoC, int Action, char *pBuf,\r
35188+ unsigned int *pLen, SK_U32 NetIndex);\r
35189+PNMI_STATIC int PnmiVar(SK_AC *pAC, SK_IOC IoC, int Action, SK_U32 Id,\r
35190+ char *pBuf, unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex);\r
35191+PNMI_STATIC void QueueRlmtNewMacTrap(SK_AC *pAC, unsigned int ActiveMac);\r
35192+PNMI_STATIC void QueueRlmtPortTrap(SK_AC *pAC, SK_U32 TrapId,\r
35193+ unsigned int PortIndex);\r
35194+PNMI_STATIC void QueueSensorTrap(SK_AC *pAC, SK_U32 TrapId,\r
35195+ unsigned int SensorIndex);\r
35196+PNMI_STATIC void QueueSimpleTrap(SK_AC *pAC, SK_U32 TrapId);\r
35197+PNMI_STATIC void ResetCounter(SK_AC *pAC, SK_IOC IoC, SK_U32 NetIndex);\r
35198+PNMI_STATIC int RlmtUpdate(SK_AC *pAC, SK_IOC IoC, SK_U32 NetIndex);\r
35199+PNMI_STATIC int SirqUpdate(SK_AC *pAC, SK_IOC IoC);\r
35200+PNMI_STATIC void VirtualConf(SK_AC *pAC, SK_IOC IoC, SK_U32 Id, char *pBuf);\r
35201+PNMI_STATIC int Vct(SK_AC *pAC, SK_IOC IoC, int Action, SK_U32 Id, char *pBuf,\r
35202+ unsigned int *pLen, SK_U32 Instance, unsigned int TableIndex, SK_U32 NetIndex);\r
35203+PNMI_STATIC void CheckVctStatus(SK_AC *, SK_IOC, char *, SK_U32, SK_U32);\r
35204+PNMI_STATIC void VctGetResults(SK_AC *, SK_IOC, SK_U32);\r
35205+#ifdef SK_ASF\r
35206+PNMI_STATIC int Asf(SK_AC *pAC, SK_IOC IoC, int action, SK_U32 Id,\r
35207+ char *pBuf, unsigned int *pLen, SK_U32 Instance,\r
35208+ unsigned int TableIndex, SK_U32 NetIndex);\r
35209+#endif /* SK_ASF */\r
35210+\r
35211+/*\r
35212+ * Table to correlate OID with handler function and index to\r
35213+ * hardware register stored in StatAddress if applicable.\r
35214+ */\r
35215+#include "skgemib.c"\r
35216+\r
35217+/* global variables **********************************************************/\r
35218+\r
35219+/*\r
35220+ * Overflow status register bit table and corresponding counter\r
35221+ * dependent on MAC type - the number relates to the size of overflow\r
35222+ * mask returned by the pFnMacOverflow function\r
35223+ */\r
35224+PNMI_STATIC const SK_U16 StatOvrflwBit[][SK_PNMI_MAC_TYPES] = {\r
35225+/* Bit0 */ { SK_PNMI_HTX, SK_PNMI_HTX_UNICAST},\r
35226+/* Bit1 */ { SK_PNMI_HTX_OCTETHIGH, SK_PNMI_HTX_BROADCAST},\r
35227+/* Bit2 */ { SK_PNMI_HTX_OCTETLOW, SK_PNMI_HTX_PMACC},\r
35228+/* Bit3 */ { SK_PNMI_HTX_BROADCAST, SK_PNMI_HTX_MULTICAST},\r
35229+/* Bit4 */ { SK_PNMI_HTX_MULTICAST, SK_PNMI_HTX_OCTETLOW},\r
35230+/* Bit5 */ { SK_PNMI_HTX_UNICAST, SK_PNMI_HTX_OCTETHIGH},\r
35231+/* Bit6 */ { SK_PNMI_HTX_LONGFRAMES, SK_PNMI_HTX_64},\r
35232+/* Bit7 */ { SK_PNMI_HTX_BURST, SK_PNMI_HTX_127},\r
35233+/* Bit8 */ { SK_PNMI_HTX_PMACC, SK_PNMI_HTX_255},\r
35234+/* Bit9 */ { SK_PNMI_HTX_MACC, SK_PNMI_HTX_511},\r
35235+/* Bit10 */ { SK_PNMI_HTX_SINGLE_COL, SK_PNMI_HTX_1023},\r
35236+/* Bit11 */ { SK_PNMI_HTX_MULTI_COL, SK_PNMI_HTX_MAX},\r
35237+/* Bit12 */ { SK_PNMI_HTX_EXCESS_COL, SK_PNMI_HTX_LONGFRAMES},\r
35238+/* Bit13 */ { SK_PNMI_HTX_LATE_COL, SK_PNMI_HTX_RESERVED},\r
35239+/* Bit14 */ { SK_PNMI_HTX_DEFFERAL, SK_PNMI_HTX_COL},\r
35240+/* Bit15 */ { SK_PNMI_HTX_EXCESS_DEF, SK_PNMI_HTX_LATE_COL},\r
35241+/* Bit16 */ { SK_PNMI_HTX_UNDERRUN, SK_PNMI_HTX_EXCESS_COL},\r
35242+/* Bit17 */ { SK_PNMI_HTX_CARRIER, SK_PNMI_HTX_MULTI_COL},\r
35243+/* Bit18 */ { SK_PNMI_HTX_UTILUNDER, SK_PNMI_HTX_SINGLE_COL},\r
35244+/* Bit19 */ { SK_PNMI_HTX_UTILOVER, SK_PNMI_HTX_UNDERRUN},\r
35245+/* Bit20 */ { SK_PNMI_HTX_64, SK_PNMI_HTX_RESERVED},\r
35246+/* Bit21 */ { SK_PNMI_HTX_127, SK_PNMI_HTX_RESERVED},\r
35247+/* Bit22 */ { SK_PNMI_HTX_255, SK_PNMI_HTX_RESERVED},\r
35248+/* Bit23 */ { SK_PNMI_HTX_511, SK_PNMI_HTX_RESERVED},\r
35249+/* Bit24 */ { SK_PNMI_HTX_1023, SK_PNMI_HTX_RESERVED},\r
35250+/* Bit25 */ { SK_PNMI_HTX_MAX, SK_PNMI_HTX_RESERVED},\r
35251+/* Bit26 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED},\r
35252+/* Bit27 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED},\r
35253+/* Bit28 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED},\r
35254+/* Bit29 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED},\r
35255+/* Bit30 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED},\r
35256+/* Bit31 */ { SK_PNMI_HTX_RESERVED, SK_PNMI_HTX_RESERVED},\r
35257+/* Bit32 */ { SK_PNMI_HRX, SK_PNMI_HRX_UNICAST},\r
35258+/* Bit33 */ { SK_PNMI_HRX_OCTETHIGH, SK_PNMI_HRX_BROADCAST},\r
35259+/* Bit34 */ { SK_PNMI_HRX_OCTETLOW, SK_PNMI_HRX_PMACC},\r
35260+/* Bit35 */ { SK_PNMI_HRX_BROADCAST, SK_PNMI_HRX_MULTICAST},\r
35261+/* Bit36 */ { SK_PNMI_HRX_MULTICAST, SK_PNMI_HRX_FCS},\r
35262+/* Bit37 */ { SK_PNMI_HRX_UNICAST, SK_PNMI_HRX_RESERVED},\r
35263+/* Bit38 */ { SK_PNMI_HRX_PMACC, SK_PNMI_HRX_OCTETLOW},\r
35264+/* Bit39 */ { SK_PNMI_HRX_MACC, SK_PNMI_HRX_OCTETHIGH},\r
35265+/* Bit40 */ { SK_PNMI_HRX_PMACC_ERR, SK_PNMI_HRX_BADOCTETLOW},\r
35266+/* Bit41 */ { SK_PNMI_HRX_MACC_UNKWN, SK_PNMI_HRX_BADOCTETHIGH},\r
35267+/* Bit42 */ { SK_PNMI_HRX_BURST, SK_PNMI_HRX_UNDERSIZE},\r
35268+/* Bit43 */ { SK_PNMI_HRX_MISSED, SK_PNMI_HRX_RUNT},\r
35269+/* Bit44 */ { SK_PNMI_HRX_FRAMING, SK_PNMI_HRX_64},\r
35270+/* Bit45 */ { SK_PNMI_HRX_OVERFLOW, SK_PNMI_HRX_127},\r
35271+/* Bit46 */ { SK_PNMI_HRX_JABBER, SK_PNMI_HRX_255},\r
35272+/* Bit47 */ { SK_PNMI_HRX_CARRIER, SK_PNMI_HRX_511},\r
35273+/* Bit48 */ { SK_PNMI_HRX_IRLENGTH, SK_PNMI_HRX_1023},\r
35274+/* Bit49 */ { SK_PNMI_HRX_SYMBOL, SK_PNMI_HRX_MAX},\r
35275+/* Bit50 */ { SK_PNMI_HRX_SHORTS, SK_PNMI_HRX_LONGFRAMES},\r
35276+/* Bit51 */ { SK_PNMI_HRX_RUNT, SK_PNMI_HRX_TOO_LONG},\r
35277+/* Bit52 */ { SK_PNMI_HRX_TOO_LONG, SK_PNMI_HRX_JABBER},\r
35278+/* Bit53 */ { SK_PNMI_HRX_FCS, SK_PNMI_HRX_RESERVED},\r
35279+/* Bit54 */ { SK_PNMI_HRX_RESERVED, SK_PNMI_HRX_OVERFLOW},\r
35280+/* Bit55 */ { SK_PNMI_HRX_CEXT, SK_PNMI_HRX_RESERVED},\r
35281+/* Bit56 */ { SK_PNMI_HRX_UTILUNDER, SK_PNMI_HRX_RESERVED},\r
35282+/* Bit57 */ { SK_PNMI_HRX_UTILOVER, SK_PNMI_HRX_RESERVED},\r
35283+/* Bit58 */ { SK_PNMI_HRX_64, SK_PNMI_HRX_RESERVED},\r
35284+/* Bit59 */ { SK_PNMI_HRX_127, SK_PNMI_HRX_RESERVED},\r
35285+/* Bit60 */ { SK_PNMI_HRX_255, SK_PNMI_HRX_RESERVED},\r
35286+/* Bit61 */ { SK_PNMI_HRX_511, SK_PNMI_HRX_RESERVED},\r
35287+/* Bit62 */ { SK_PNMI_HRX_1023, SK_PNMI_HRX_RESERVED},\r
35288+/* Bit63 */ { SK_PNMI_HRX_MAX, SK_PNMI_HRX_RESERVED}\r
35289+};\r
35290+\r
35291+/*\r
35292+ * Table for hardware register saving on resets and port switches\r
35293+ */\r
35294+PNMI_STATIC const SK_PNMI_STATADDR StatAddr[SK_PNMI_MAX_IDX][SK_PNMI_MAC_TYPES] = {\r
35295+ /* SK_PNMI_HTX */\r
35296+ {{XM_TXF_OK, SK_TRUE}, {0, SK_FALSE}},\r
35297+ /* SK_PNMI_HTX_OCTETHIGH */\r
35298+ {{XM_TXO_OK_HI, SK_TRUE}, {GM_TXO_OK_HI, SK_TRUE}},\r
35299+ /* SK_PNMI_HTX_OCTETLOW */\r
35300+ {{XM_TXO_OK_LO, SK_FALSE}, {GM_TXO_OK_LO, SK_FALSE}},\r
35301+ /* SK_PNMI_HTX_BROADCAST */\r
35302+ {{XM_TXF_BC_OK, SK_TRUE}, {GM_TXF_BC_OK, SK_TRUE}},\r
35303+ /* SK_PNMI_HTX_MULTICAST */\r
35304+ {{XM_TXF_MC_OK, SK_TRUE}, {GM_TXF_MC_OK, SK_TRUE}},\r
35305+ /* SK_PNMI_HTX_UNICAST */\r
35306+ {{XM_TXF_UC_OK, SK_TRUE}, {GM_TXF_UC_OK, SK_TRUE}},\r
35307+ /* SK_PNMI_HTX_BURST */\r
35308+ {{XM_TXE_BURST, SK_TRUE}, {0, SK_FALSE}},\r
35309+ /* SK_PNMI_HTX_PMACC */\r
35310+ {{XM_TXF_MPAUSE, SK_TRUE}, {GM_TXF_MPAUSE, SK_TRUE}},\r
35311+ /* SK_PNMI_HTX_MACC */\r
35312+ {{XM_TXF_MCTRL, SK_TRUE}, {0, SK_FALSE}},\r
35313+ /* SK_PNMI_HTX_COL */\r
35314+ {{0, SK_FALSE}, {GM_TXF_COL, SK_TRUE}},\r
35315+ /* SK_PNMI_HTX_SINGLE_COL */\r
35316+ {{XM_TXF_SNG_COL, SK_TRUE}, {GM_TXF_SNG_COL, SK_TRUE}},\r
35317+ /* SK_PNMI_HTX_MULTI_COL */\r
35318+ {{XM_TXF_MUL_COL, SK_TRUE}, {GM_TXF_MUL_COL, SK_TRUE}},\r
35319+ /* SK_PNMI_HTX_EXCESS_COL */\r
35320+ {{XM_TXF_ABO_COL, SK_TRUE}, {GM_TXF_ABO_COL, SK_TRUE}},\r
35321+ /* SK_PNMI_HTX_LATE_COL */\r
35322+ {{XM_TXF_LAT_COL, SK_TRUE}, {GM_TXF_LAT_COL, SK_TRUE}},\r
35323+ /* SK_PNMI_HTX_DEFFERAL */\r
35324+ {{XM_TXF_DEF, SK_TRUE}, {0, SK_FALSE}},\r
35325+ /* SK_PNMI_HTX_EXCESS_DEF */\r
35326+ {{XM_TXF_EX_DEF, SK_TRUE}, {0, SK_FALSE}},\r
35327+ /* SK_PNMI_HTX_UNDERRUN */\r
35328+ {{XM_TXE_FIFO_UR, SK_TRUE}, {GM_TXE_FIFO_UR, SK_TRUE}},\r
35329+ /* SK_PNMI_HTX_CARRIER */\r
35330+ {{XM_TXE_CS_ERR, SK_TRUE}, {0, SK_FALSE}},\r
35331+ /* SK_PNMI_HTX_UTILUNDER */\r
35332+ {{0, SK_FALSE}, {0, SK_FALSE}},\r
35333+ /* SK_PNMI_HTX_UTILOVER */\r
35334+ {{0, SK_FALSE}, {0, SK_FALSE}},\r
35335+ /* SK_PNMI_HTX_64 */\r
35336+ {{XM_TXF_64B, SK_TRUE}, {GM_TXF_64B, SK_TRUE}},\r
35337+ /* SK_PNMI_HTX_127 */\r
35338+ {{XM_TXF_127B, SK_TRUE}, {GM_TXF_127B, SK_TRUE}},\r
35339+ /* SK_PNMI_HTX_255 */\r
35340+ {{XM_TXF_255B, SK_TRUE}, {GM_TXF_255B, SK_TRUE}},\r
35341+ /* SK_PNMI_HTX_511 */\r
35342+ {{XM_TXF_511B, SK_TRUE}, {GM_TXF_511B, SK_TRUE}},\r
35343+ /* SK_PNMI_HTX_1023 */\r
35344+ {{XM_TXF_1023B, SK_TRUE}, {GM_TXF_1023B, SK_TRUE}},\r
35345+ /* SK_PNMI_HTX_MAX */\r
35346+ {{XM_TXF_MAX_SZ, SK_TRUE}, {GM_TXF_1518B, SK_TRUE}},\r
35347+ /* SK_PNMI_HTX_LONGFRAMES */\r
35348+ {{XM_TXF_LONG, SK_TRUE}, {GM_TXF_MAX_SZ, SK_TRUE}},\r
35349+ /* SK_PNMI_HTX_SYNC */\r
35350+ {{0, SK_FALSE}, {0, SK_FALSE}},\r
35351+ /* SK_PNMI_HTX_SYNC_OCTET */\r
35352+ {{0, SK_FALSE}, {0, SK_FALSE}},\r
35353+ /* SK_PNMI_HTX_RESERVED */\r
35354+ {{0, SK_FALSE}, {0, SK_FALSE}},\r
35355+ /* SK_PNMI_HRX */\r
35356+ {{XM_RXF_OK, SK_TRUE}, {0, SK_FALSE}},\r
35357+ /* SK_PNMI_HRX_OCTETHIGH */\r
35358+ {{XM_RXO_OK_HI, SK_TRUE}, {GM_RXO_OK_HI, SK_TRUE}},\r
35359+ /* SK_PNMI_HRX_OCTETLOW */\r
35360+ {{XM_RXO_OK_LO, SK_FALSE}, {GM_RXO_OK_LO, SK_FALSE}},\r
35361+ /* SK_PNMI_HRX_BADOCTETHIGH */\r
35362+ {{0, SK_FALSE}, {GM_RXO_ERR_HI, SK_TRUE}},\r
35363+ /* SK_PNMI_HRX_BADOCTETLOW */\r
35364+ {{0, SK_FALSE}, {GM_RXO_ERR_LO, SK_TRUE}},\r
35365+ /* SK_PNMI_HRX_BROADCAST */\r
35366+ {{XM_RXF_BC_OK, SK_TRUE}, {GM_RXF_BC_OK, SK_TRUE}},\r
35367+ /* SK_PNMI_HRX_MULTICAST */\r
35368+ {{XM_RXF_MC_OK, SK_TRUE}, {GM_RXF_MC_OK, SK_TRUE}},\r
35369+ /* SK_PNMI_HRX_UNICAST */\r
35370+ {{XM_RXF_UC_OK, SK_TRUE}, {GM_RXF_UC_OK, SK_TRUE}},\r
35371+ /* SK_PNMI_HRX_PMACC */\r
35372+ {{XM_RXF_MPAUSE, SK_TRUE}, {GM_RXF_MPAUSE, SK_TRUE}},\r
35373+ /* SK_PNMI_HRX_MACC */\r
35374+ {{XM_RXF_MCTRL, SK_TRUE}, {0, SK_FALSE}},\r
35375+ /* SK_PNMI_HRX_PMACC_ERR */\r
35376+ {{XM_RXF_INV_MP, SK_TRUE}, {0, SK_FALSE}},\r
35377+ /* SK_PNMI_HRX_MACC_UNKWN */\r
35378+ {{XM_RXF_INV_MOC, SK_TRUE}, {0, SK_FALSE}},\r
35379+ /* SK_PNMI_HRX_BURST */\r
35380+ {{XM_RXE_BURST, SK_TRUE}, {0, SK_FALSE}},\r
35381+ /* SK_PNMI_HRX_MISSED */\r
35382+ {{XM_RXE_FMISS, SK_TRUE}, {0, SK_FALSE}},\r
35383+ /* SK_PNMI_HRX_FRAMING */\r
35384+ {{XM_RXF_FRA_ERR, SK_TRUE}, {0, SK_FALSE}},\r
35385+ /* SK_PNMI_HRX_UNDERSIZE */\r
35386+ {{0, SK_FALSE}, {GM_RXF_SHT, SK_TRUE}},\r
35387+ /* SK_PNMI_HRX_OVERFLOW */\r
35388+ {{XM_RXE_FIFO_OV, SK_TRUE}, {GM_RXE_FIFO_OV, SK_TRUE}},\r
35389+ /* SK_PNMI_HRX_JABBER */\r
35390+ {{XM_RXF_JAB_PKT, SK_TRUE}, {GM_RXF_JAB_PKT, SK_TRUE}},\r
35391+ /* SK_PNMI_HRX_CARRIER */\r
35392+ {{XM_RXE_CAR_ERR, SK_TRUE}, {0, SK_FALSE}},\r
35393+ /* SK_PNMI_HRX_IRLENGTH */\r
35394+ {{XM_RXF_LEN_ERR, SK_TRUE}, {0, SK_FALSE}},\r
35395+ /* SK_PNMI_HRX_SYMBOL */\r
35396+ {{XM_RXE_SYM_ERR, SK_TRUE}, {0, SK_FALSE}},\r
35397+ /* SK_PNMI_HRX_SHORTS */\r
35398+ {{XM_RXE_SHT_ERR, SK_TRUE}, {0, SK_FALSE}},\r
35399+ /* SK_PNMI_HRX_RUNT */\r
35400+ {{XM_RXE_RUNT, SK_TRUE}, {GM_RXE_FRAG, SK_TRUE}},\r
35401+ /* SK_PNMI_HRX_TOO_LONG */\r
35402+ {{XM_RXF_LNG_ERR, SK_TRUE}, {GM_RXF_LNG_ERR, SK_TRUE}},\r
35403+ /* SK_PNMI_HRX_FCS */\r
35404+ {{XM_RXF_FCS_ERR, SK_TRUE}, {GM_RXF_FCS_ERR, SK_TRUE}},\r
35405+ /* SK_PNMI_HRX_CEXT */\r
35406+ {{XM_RXF_CEX_ERR, SK_TRUE}, {0, SK_FALSE}},\r
35407+ /* SK_PNMI_HRX_UTILUNDER */\r
35408+ {{0, SK_FALSE}, {0, SK_FALSE}},\r
35409+ /* SK_PNMI_HRX_UTILOVER */\r
35410+ {{0, SK_FALSE}, {0, SK_FALSE}},\r
35411+ /* SK_PNMI_HRX_64 */\r
35412+ {{XM_RXF_64B, SK_TRUE}, {GM_RXF_64B, SK_TRUE}},\r
35413+ /* SK_PNMI_HRX_127 */\r
35414+ {{XM_RXF_127B, SK_TRUE}, {GM_RXF_127B, SK_TRUE}},\r
35415+ /* SK_PNMI_HRX_255 */\r
35416+ {{XM_RXF_255B, SK_TRUE}, {GM_RXF_255B, SK_TRUE}},\r
35417+ /* SK_PNMI_HRX_511 */\r
35418+ {{XM_RXF_511B, SK_TRUE}, {GM_RXF_511B, SK_TRUE}},\r
35419+ /* SK_PNMI_HRX_1023 */\r
35420+ {{XM_RXF_1023B, SK_TRUE}, {GM_RXF_1023B, SK_TRUE}},\r
35421+ /* SK_PNMI_HRX_MAX */\r
35422+ {{XM_RXF_MAX_SZ, SK_TRUE}, {GM_RXF_1518B, SK_TRUE}},\r
35423+ /* SK_PNMI_HRX_LONGFRAMES */\r
35424+ {{0, SK_FALSE}, {GM_RXF_MAX_SZ, SK_TRUE}},\r
35425+ /* SK_PNMI_HRX_RESERVED */\r
35426+ {{0, SK_FALSE}, {0, SK_FALSE}}\r
35427+};\r
35428+\r
35429+\r
35430+/*****************************************************************************\r
35431+ *\r
35432+ * Public functions\r
35433+ *\r
35434+ */\r
35435+\r
35436+/*****************************************************************************\r
35437+ *\r
35438+ * SkPnmiInit - Init function of PNMI\r
35439+ *\r
35440+ * Description:\r
35441+ * SK_INIT_DATA: Initialises the data structures\r
35442+ * SK_INIT_IO: Resets the XMAC statistics, determines the device and\r
35443+ * connector type.\r
35444+ * SK_INIT_RUN: Starts a timer event for port switch per hour\r
35445+ * calculation.\r
35446+ *\r
35447+ * Returns:\r
35448+ * Always 0\r
35449+ */\r
35450+int SkPnmiInit(\r
35451+SK_AC *pAC, /* Pointer to adapter context */\r
35452+SK_IOC IoC, /* IO context handle */\r
35453+int Level) /* Initialization level */\r
35454+{\r
35455+ unsigned int PortMax; /* Number of ports */\r
35456+ unsigned int PortIndex; /* Current port index in loop */\r
35457+ SK_EVPARA EventParam; /* Event struct for timer event */\r
35458+\r
35459+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
35460+ ("PNMI: SkPnmiInit: Called, level=%d\n", Level));\r
35461+\r
35462+ switch (Level) {\r
35463+\r
35464+ case SK_INIT_DATA:\r
35465+ SK_MEMSET((char *)&pAC->Pnmi, 0, sizeof(pAC->Pnmi));\r
35466+ \r
35467+ pAC->Pnmi.TrapBufFree = SK_PNMI_TRAP_QUEUE_LEN;\r
35468+ pAC->Pnmi.StartUpTime = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC));\r
35469+ pAC->Pnmi.RlmtChangeThreshold = SK_PNMI_DEF_RLMT_CHG_THRES;\r
35470+ \r
35471+ for (PortIndex = 0; PortIndex < SK_MAX_MACS; PortIndex ++) {\r
35472+\r
35473+ pAC->Pnmi.Port[PortIndex].ActiveFlag = SK_FALSE;\r
35474+ pAC->Pnmi.DualNetActiveFlag = SK_FALSE;\r
35475+\r
35476+ /* Initialize DSP variables for Vct() to 0xff => Never written! */ \r
35477+ pAC->GIni.GP[PortIndex].PCableLen = 0xff;\r
35478+ pAC->Pnmi.VctBackup[PortIndex].CableLen = 0xff;\r
35479+ }\r
35480+\r
35481+#ifdef SK_PNMI_CHECK\r
35482+ if (SK_PNMI_MAX_IDX != SK_PNMI_CNT_NO) {\r
35483+ \r
35484+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR049, SK_PNMI_ERR049MSG);\r
35485+\r
35486+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_INIT | SK_DBGCAT_FATAL,\r
35487+ ("CounterOffset struct size (%d) differs from"\r
35488+ "SK_PNMI_MAX_IDX (%d)\n",\r
35489+ SK_PNMI_CNT_NO, SK_PNMI_MAX_IDX));\r
35490+ }\r
35491+\r
35492+ if (SK_PNMI_MAX_IDX !=\r
35493+ (sizeof(StatAddr) / (sizeof(SK_PNMI_STATADDR) * SK_PNMI_MAC_TYPES))) {\r
35494+ \r
35495+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR050, SK_PNMI_ERR050MSG);\r
35496+\r
35497+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_INIT | SK_DBGCAT_FATAL,\r
35498+ ("StatAddr table size (%d) differs from "\r
35499+ "SK_PNMI_MAX_IDX (%d)\n",\r
35500+ (sizeof(StatAddr) /\r
35501+ (sizeof(SK_PNMI_STATADDR) * SK_PNMI_MAC_TYPES)),\r
35502+ SK_PNMI_MAX_IDX));\r
35503+ }\r
35504+#endif /* SK_PNMI_CHECK */\r
35505+ break;\r
35506+\r
35507+ case SK_INIT_IO:\r
35508+\r
35509+ /* Reset MAC counters. */\r
35510+ PortMax = pAC->GIni.GIMacsFound;\r
35511+\r
35512+ for (PortIndex = 0; PortIndex < PortMax; PortIndex ++) {\r
35513+\r
35514+ pAC->GIni.GIFunc.pFnMacResetCounter(pAC, IoC, PortIndex);\r
35515+ }\r
35516+\r
35517+ /* Get PCI bus speed. */\r
35518+ if (pAC->GIni.GIPciClock66) {\r
35519+\r
35520+ pAC->Pnmi.PciBusSpeed = 66;\r
35521+ }\r
35522+ else {\r
35523+ pAC->Pnmi.PciBusSpeed = 33;\r
35524+ }\r
35525+\r
35526+ /* Get PCI bus width. */\r
35527+ if (pAC->GIni.GIPciSlot64) {\r
35528+\r
35529+ pAC->Pnmi.PciBusWidth = 64;\r
35530+ }\r
35531+ else {\r
35532+ pAC->Pnmi.PciBusWidth = 32;\r
35533+ }\r
35534+\r
35535+ /* Get chipset. */\r
35536+ switch (pAC->GIni.GIChipId) {\r
35537+\r
35538+ case CHIP_ID_GENESIS:\r
35539+ pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_XMAC;\r
35540+ break;\r
35541+\r
35542+ case CHIP_ID_YUKON:\r
35543+ pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON;\r
35544+ break;\r
35545+\r
35546+ case CHIP_ID_YUKON_LITE:\r
35547+ pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_LITE;\r
35548+ break;\r
35549+\r
35550+ case CHIP_ID_YUKON_LP:\r
35551+ pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_LP;\r
35552+ break;\r
35553+\r
35554+ case CHIP_ID_YUKON_XL:\r
35555+ pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_XL;\r
35556+ break;\r
35557+\r
35558+ case CHIP_ID_YUKON_EC:\r
35559+ pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_EC;\r
35560+ break;\r
35561+\r
35562+ case CHIP_ID_YUKON_FE:\r
35563+ pAC->Pnmi.Chipset = SK_PNMI_CHIPSET_YUKON_FE;\r
35564+ break;\r
35565+\r
35566+ default:\r
35567+ break;\r
35568+ }\r
35569+\r
35570+ /* Get PMD and Device Type. */\r
35571+ switch (pAC->GIni.GIPmdTyp) {\r
35572+ \r
35573+ case 'S':\r
35574+ pAC->Pnmi.PMD = 3;\r
35575+ pAC->Pnmi.DeviceType = 0x00020001;\r
35576+ break;\r
35577+\r
35578+ case 'L':\r
35579+ pAC->Pnmi.PMD = 2;\r
35580+ pAC->Pnmi.DeviceType = 0x00020003;\r
35581+ break;\r
35582+\r
35583+ case 'C':\r
35584+ pAC->Pnmi.PMD = 4;\r
35585+ pAC->Pnmi.DeviceType = 0x00020005;\r
35586+ break;\r
35587+\r
35588+ case 'T':\r
35589+ pAC->Pnmi.PMD = 5;\r
35590+ pAC->Pnmi.DeviceType = 0x00020007;\r
35591+ break;\r
35592+\r
35593+ default :\r
35594+ pAC->Pnmi.PMD = 1;\r
35595+ pAC->Pnmi.DeviceType = 0;\r
35596+ break;\r
35597+ }\r
35598+\r
35599+ if (pAC->GIni.GIMacsFound > 1) {\r
35600+\r
35601+ pAC->Pnmi.DeviceType++;\r
35602+ }\r
35603+ \r
35604+ /* Get connector type. */\r
35605+ switch (pAC->GIni.GIConTyp) {\r
35606+ \r
35607+ case 'C':\r
35608+ pAC->Pnmi.Connector = 2;\r
35609+ break;\r
35610+\r
35611+ case 'D':\r
35612+ pAC->Pnmi.Connector = 3;\r
35613+ break;\r
35614+\r
35615+ case 'F':\r
35616+ pAC->Pnmi.Connector = 4;\r
35617+ break;\r
35618+\r
35619+ case 'J':\r
35620+ pAC->Pnmi.Connector = 5;\r
35621+ break;\r
35622+\r
35623+ case 'V':\r
35624+ pAC->Pnmi.Connector = 6;\r
35625+ break;\r
35626+\r
35627+ default:\r
35628+ pAC->Pnmi.Connector = 1;\r
35629+ break;\r
35630+ }\r
35631+ break;\r
35632+\r
35633+ case SK_INIT_RUN:\r
35634+\r
35635+ /* Start timer for RLMT change counter. */\r
35636+ SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));\r
35637+ \r
35638+ SkTimerStart(pAC, IoC, &pAC->Pnmi.RlmtChangeEstimate.EstTimer,\r
35639+ SK_PNMI_EVT_TIMER_CHECK, SKGE_PNMI, SK_PNMI_EVT_CHG_EST_TIMER,\r
35640+ EventParam);\r
35641+ break;\r
35642+\r
35643+ default:\r
35644+ break; /* Nothing to do. */\r
35645+ }\r
35646+\r
35647+ return (0);\r
35648+}\r
35649+\r
35650+/*****************************************************************************\r
35651+ *\r
35652+ * SkPnmiGetVar - Retrieves the value of a single OID\r
35653+ *\r
35654+ * Description:\r
35655+ * Calls a general sub-function for all this stuff. If the instance\r
35656+ * -1 is passed, the values of all instances are returned in an\r
35657+ * array of values.\r
35658+ *\r
35659+ * Returns:\r
35660+ * SK_PNMI_ERR_OK The request was successfully performed\r
35661+ * SK_PNMI_ERR_GENERAL A general severe internal error occured\r
35662+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to take\r
35663+ * the data.\r
35664+ * SK_PNMI_ERR_UNKNOWN_OID The requested OID is unknown\r
35665+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't\r
35666+ * exist (e.g. port instance 3 on a two port\r
35667+ * adapter.\r
35668+ */\r
35669+int SkPnmiGetVar(\r
35670+SK_AC *pAC, /* Pointer to adapter context */\r
35671+SK_IOC IoC, /* IO context handle */\r
35672+SK_U32 Id, /* Object ID that is to be processed */\r
35673+void *pBuf, /* Buffer to which the management data will be copied */\r
35674+unsigned int *pLen, /* On call: buffer length. On return: used buffer */\r
35675+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */\r
35676+SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */\r
35677+{\r
35678+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
35679+ ("PNMI: SkPnmiGetVar: Called, Id=0x%x, BufLen=%d, Instance=%d, NetIndex=%d\n",\r
35680+ Id, *pLen, Instance, NetIndex));\r
35681+\r
35682+ return (PnmiVar(pAC, IoC, SK_PNMI_GET, Id, (char *)pBuf, pLen,\r
35683+ Instance, NetIndex));\r
35684+}\r
35685+\r
35686+/*****************************************************************************\r
35687+ *\r
35688+ * SkPnmiPreSetVar - Presets the value of a single OID\r
35689+ *\r
35690+ * Description:\r
35691+ * Calls a general sub-function for all this stuff. The preset does\r
35692+ * the same as a set, but returns just before finally setting the\r
35693+ * new value. This is usefull to check if a set might be successfull.\r
35694+ * If the instance -1 is passed, an array of values is supposed and\r
35695+ * all instances of the OID will be set.\r
35696+ *\r
35697+ * Returns:\r
35698+ * SK_PNMI_ERR_OK The request was successfully performed.\r
35699+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.\r
35700+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain\r
35701+ * the correct data (e.g. a 32bit value is\r
35702+ * needed, but a 16 bit value was passed).\r
35703+ * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid\r
35704+ * value range.\r
35705+ * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set.\r
35706+ * SK_PNMI_ERR_UNKNOWN_OID The requested OID is unknown.\r
35707+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't\r
35708+ * exist (e.g. port instance 3 on a two port\r
35709+ * adapter.\r
35710+ */\r
35711+int SkPnmiPreSetVar(\r
35712+SK_AC *pAC, /* Pointer to adapter context */\r
35713+SK_IOC IoC, /* IO context handle */\r
35714+SK_U32 Id, /* Object ID that is to be processed */\r
35715+void *pBuf, /* Buffer to which the management data will be copied */\r
35716+unsigned int *pLen, /* Total length of management data */\r
35717+SK_U32 Instance, /* Instance (1..n) that is to be set or -1 */\r
35718+SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */\r
35719+{\r
35720+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
35721+ ("PNMI: SkPnmiPreSetVar: Called, Id=0x%x, BufLen=%d, Instance=%d, NetIndex=%d\n",\r
35722+ Id, *pLen, Instance, NetIndex));\r
35723+\r
35724+ return (PnmiVar(pAC, IoC, SK_PNMI_PRESET, Id, (char *)pBuf, pLen,\r
35725+ Instance, NetIndex));\r
35726+}\r
35727+\r
35728+/*****************************************************************************\r
35729+ *\r
35730+ * SkPnmiSetVar - Sets the value of a single OID\r
35731+ *\r
35732+ * Description:\r
35733+ * Calls a general sub-function for all this stuff. The preset does\r
35734+ * the same as a set, but returns just before finally setting the\r
35735+ * new value. This is usefull to check if a set might be successfull.\r
35736+ * If the instance -1 is passed, an array of values is supposed and\r
35737+ * all instances of the OID will be set.\r
35738+ *\r
35739+ * Returns:\r
35740+ * SK_PNMI_ERR_OK The request was successfully performed.\r
35741+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.\r
35742+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain\r
35743+ * the correct data (e.g. a 32bit value is\r
35744+ * needed, but a 16 bit value was passed).\r
35745+ * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid\r
35746+ * value range.\r
35747+ * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set.\r
35748+ * SK_PNMI_ERR_UNKNOWN_OID The requested OID is unknown.\r
35749+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't\r
35750+ * exist (e.g. port instance 3 on a two port\r
35751+ * adapter.\r
35752+ */\r
35753+int SkPnmiSetVar(\r
35754+SK_AC *pAC, /* Pointer to adapter context */\r
35755+SK_IOC IoC, /* IO context handle */\r
35756+SK_U32 Id, /* Object ID that is to be processed */\r
35757+void *pBuf, /* Buffer to which the management data will be copied */\r
35758+unsigned int *pLen, /* Total length of management data */\r
35759+SK_U32 Instance, /* Instance (1..n) that is to be set or -1 */\r
35760+SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */\r
35761+{\r
35762+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
35763+ ("PNMI: SkPnmiSetVar: Called, Id=0x%x, BufLen=%d, Instance=%d, NetIndex=%d\n",\r
35764+ Id, *pLen, Instance, NetIndex));\r
35765+\r
35766+ return (PnmiVar(pAC, IoC, SK_PNMI_SET, Id, (char *)pBuf, pLen,\r
35767+ Instance, NetIndex));\r
35768+}\r
35769+\r
35770+/*****************************************************************************\r
35771+ *\r
35772+ * SkPnmiGetStruct - Retrieves the management database in SK_PNMI_STRUCT_DATA\r
35773+ *\r
35774+ * Description:\r
35775+ * Runs through the IdTable, queries the single OIDs and stores the\r
35776+ * returned data into the management database structure\r
35777+ * SK_PNMI_STRUCT_DATA. The offset of the OID in the structure\r
35778+ * is stored in the IdTable. The return value of the function will also\r
35779+ * be stored in SK_PNMI_STRUCT_DATA if the passed buffer has the\r
35780+ * minimum size of SK_PNMI_MIN_STRUCT_SIZE.\r
35781+ *\r
35782+ * Returns:\r
35783+ * SK_PNMI_ERR_OK The request was successfully performed\r
35784+ * SK_PNMI_ERR_GENERAL A general severe internal error occured\r
35785+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to take\r
35786+ * the data.\r
35787+ * SK_PNMI_ERR_UNKNOWN_NET The requested NetIndex doesn't exist\r
35788+ */\r
35789+int SkPnmiGetStruct(\r
35790+SK_AC *pAC, /* Pointer to adapter context */\r
35791+SK_IOC IoC, /* IO context handle */\r
35792+void *pBuf, /* Buffer to which the management data will be copied. */\r
35793+unsigned int *pLen, /* Length of buffer */\r
35794+SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */\r
35795+{\r
35796+ int Ret;\r
35797+ unsigned int TableIndex;\r
35798+ unsigned int DstOffset;\r
35799+ unsigned int InstanceNo;\r
35800+ unsigned int InstanceCnt;\r
35801+ SK_U32 Instance;\r
35802+ unsigned int TmpLen;\r
35803+ char KeyArr[SK_PNMI_VPD_ENTRIES][SK_PNMI_VPD_KEY_SIZE];\r
35804+\r
35805+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
35806+ ("PNMI: SkPnmiGetStruct: Called, BufLen=%d, NetIndex=%d\n",\r
35807+ *pLen, NetIndex));\r
35808+\r
35809+ if (*pLen < SK_PNMI_STRUCT_SIZE) {\r
35810+\r
35811+ if (*pLen >= SK_PNMI_MIN_STRUCT_SIZE) {\r
35812+\r
35813+ SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_TOO_SHORT, (SK_U32)(-1));\r
35814+ }\r
35815+\r
35816+ *pLen = SK_PNMI_STRUCT_SIZE;\r
35817+ return (SK_PNMI_ERR_TOO_SHORT);\r
35818+ }\r
35819+\r
35820+ /* Check NetIndex. */\r
35821+ if (NetIndex >= pAC->Rlmt.NumNets) {\r
35822+ return (SK_PNMI_ERR_UNKNOWN_NET);\r
35823+ }\r
35824+\r
35825+ /* Update statistics. */\r
35826+ SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On call");\r
35827+\r
35828+ if ((Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1)) !=\r
35829+ SK_PNMI_ERR_OK) {\r
35830+\r
35831+ SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1));\r
35832+ *pLen = SK_PNMI_MIN_STRUCT_SIZE;\r
35833+ return (Ret);\r
35834+ }\r
35835+\r
35836+ if ((Ret = RlmtUpdate(pAC, IoC, NetIndex)) != SK_PNMI_ERR_OK) {\r
35837+\r
35838+ SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1));\r
35839+ *pLen = SK_PNMI_MIN_STRUCT_SIZE;\r
35840+ return (Ret);\r
35841+ }\r
35842+\r
35843+ if ((Ret = SirqUpdate(pAC, IoC)) != SK_PNMI_ERR_OK) {\r
35844+\r
35845+ SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1));\r
35846+ *pLen = SK_PNMI_MIN_STRUCT_SIZE;\r
35847+ return (Ret);\r
35848+ }\r
35849+\r
35850+ /* Increment semaphores to indicate that an update was already done. */\r
35851+ pAC->Pnmi.MacUpdatedFlag ++;\r
35852+ pAC->Pnmi.RlmtUpdatedFlag ++;\r
35853+ pAC->Pnmi.SirqUpdatedFlag ++;\r
35854+\r
35855+ /*\r
35856+ * Get VPD keys for instance calculation.\r
35857+ * Please read comment in Vpd().\r
35858+ */\r
35859+ if (pAC->Pnmi.VpdKeyReadError == SK_FALSE) {\r
35860+ Ret = GetVpdKeyArr(pAC, IoC, &KeyArr[0][0], sizeof(KeyArr), &TmpLen);\r
35861+ if (Ret != SK_PNMI_ERR_OK) {\r
35862+\r
35863+ pAC->Pnmi.MacUpdatedFlag --;\r
35864+ pAC->Pnmi.RlmtUpdatedFlag --;\r
35865+ pAC->Pnmi.SirqUpdatedFlag --;\r
35866+\r
35867+ SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On return");\r
35868+ SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1));\r
35869+ *pLen = SK_PNMI_MIN_STRUCT_SIZE;\r
35870+ return (SK_PNMI_ERR_GENERAL);\r
35871+ }\r
35872+ }\r
35873+\r
35874+ /* Retrieve values. */\r
35875+ SK_MEMSET((char *)pBuf, 0, SK_PNMI_STRUCT_SIZE);\r
35876+ \r
35877+ for (TableIndex = 0; TableIndex < ID_TABLE_SIZE; TableIndex ++) {\r
35878+\r
35879+ InstanceNo = IdTable[TableIndex].InstanceNo;\r
35880+ for (InstanceCnt = 1; InstanceCnt <= InstanceNo; InstanceCnt ++) {\r
35881+\r
35882+ DstOffset = IdTable[TableIndex].Offset +\r
35883+ (InstanceCnt - 1) *\r
35884+ IdTable[TableIndex].StructSize;\r
35885+\r
35886+ /*\r
35887+ * For the VPD the instance is not an index number\r
35888+ * but the key itself. Determin with the instance\r
35889+ * counter the VPD key to be used.\r
35890+ */\r
35891+ if (IdTable[TableIndex].Id == OID_SKGE_VPD_KEY ||\r
35892+ IdTable[TableIndex].Id == OID_SKGE_VPD_VALUE ||\r
35893+ IdTable[TableIndex].Id == OID_SKGE_VPD_ACCESS ||\r
35894+ IdTable[TableIndex].Id == OID_SKGE_VPD_ACTION) {\r
35895+\r
35896+ SK_STRNCPY((char *)&Instance, KeyArr[InstanceCnt - 1], 4);\r
35897+ }\r
35898+ else {\r
35899+ Instance = (SK_U32)InstanceCnt;\r
35900+ }\r
35901+\r
35902+ TmpLen = *pLen - DstOffset;\r
35903+ Ret = IdTable[TableIndex].Func(pAC, IoC, SK_PNMI_GET,\r
35904+ IdTable[TableIndex].Id, (char *)pBuf +\r
35905+ DstOffset, &TmpLen, Instance, TableIndex, NetIndex);\r
35906+\r
35907+ /*\r
35908+ * An unknown instance error means that we reached\r
35909+ * the last instance of that variable. Proceed with\r
35910+ * the next OID in the table and ignore the return\r
35911+ * code.\r
35912+ */\r
35913+ if (Ret == SK_PNMI_ERR_UNKNOWN_INST) {\r
35914+\r
35915+ break;\r
35916+ }\r
35917+\r
35918+ if (Ret != SK_PNMI_ERR_OK) {\r
35919+\r
35920+ pAC->Pnmi.MacUpdatedFlag --;\r
35921+ pAC->Pnmi.RlmtUpdatedFlag --;\r
35922+ pAC->Pnmi.SirqUpdatedFlag --;\r
35923+\r
35924+ SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On return");\r
35925+ SK_PNMI_SET_STAT(pBuf, Ret, DstOffset);\r
35926+ *pLen = SK_PNMI_MIN_STRUCT_SIZE;\r
35927+ return (Ret);\r
35928+ }\r
35929+ }\r
35930+ }\r
35931+\r
35932+ pAC->Pnmi.MacUpdatedFlag --;\r
35933+ pAC->Pnmi.RlmtUpdatedFlag --;\r
35934+ pAC->Pnmi.SirqUpdatedFlag --;\r
35935+\r
35936+ *pLen = SK_PNMI_STRUCT_SIZE;\r
35937+ SK_PNMI_CHECKFLAGS("SkPnmiGetStruct: On return");\r
35938+ SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_OK, (SK_U32)(-1));\r
35939+ return (SK_PNMI_ERR_OK);\r
35940+}\r
35941+\r
35942+/*****************************************************************************\r
35943+ *\r
35944+ * SkPnmiPreSetStruct - Presets the management database in SK_PNMI_STRUCT_DATA\r
35945+ *\r
35946+ * Description:\r
35947+ * Calls a general sub-function for all this set stuff. The preset does\r
35948+ * the same as a set, but returns just before finally setting the\r
35949+ * new value. This is usefull to check if a set might be successfull.\r
35950+ * The sub-function runs through the IdTable, checks which OIDs are able\r
35951+ * to set, and calls the handler function of the OID to perform the\r
35952+ * preset. The return value of the function will also be stored in\r
35953+ * SK_PNMI_STRUCT_DATA if the passed buffer has the minimum size of\r
35954+ * SK_PNMI_MIN_STRUCT_SIZE.\r
35955+ *\r
35956+ * Returns:\r
35957+ * SK_PNMI_ERR_OK The request was successfully performed.\r
35958+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.\r
35959+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain\r
35960+ * the correct data (e.g. a 32bit value is\r
35961+ * needed, but a 16 bit value was passed).\r
35962+ * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid\r
35963+ * value range.\r
35964+ */\r
35965+int SkPnmiPreSetStruct(\r
35966+SK_AC *pAC, /* Pointer to adapter context */\r
35967+SK_IOC IoC, /* IO context handle */\r
35968+void *pBuf, /* Buffer which contains the data to be set */\r
35969+unsigned int *pLen, /* Length of buffer */\r
35970+SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */\r
35971+{\r
35972+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
35973+ ("PNMI: SkPnmiPreSetStruct: Called, BufLen=%d, NetIndex=%d\n",\r
35974+ *pLen, NetIndex));\r
35975+\r
35976+ return (PnmiStruct(pAC, IoC, SK_PNMI_PRESET, (char *)pBuf,\r
35977+ pLen, NetIndex));\r
35978+}\r
35979+\r
35980+/*****************************************************************************\r
35981+ *\r
35982+ * SkPnmiSetStruct - Sets the management database in SK_PNMI_STRUCT_DATA\r
35983+ *\r
35984+ * Description:\r
35985+ * Calls a general sub-function for all this set stuff. The return value\r
35986+ * of the function will also be stored in SK_PNMI_STRUCT_DATA if the\r
35987+ * passed buffer has the minimum size of SK_PNMI_MIN_STRUCT_SIZE.\r
35988+ * The sub-function runs through the IdTable, checks which OIDs are able\r
35989+ * to set, and calls the handler function of the OID to perform the\r
35990+ * set. The return value of the function will also be stored in\r
35991+ * SK_PNMI_STRUCT_DATA if the passed buffer has the minimum size of\r
35992+ * SK_PNMI_MIN_STRUCT_SIZE.\r
35993+ *\r
35994+ * Returns:\r
35995+ * SK_PNMI_ERR_OK The request was successfully performed.\r
35996+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.\r
35997+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain\r
35998+ * the correct data (e.g. a 32bit value is\r
35999+ * needed, but a 16 bit value was passed).\r
36000+ * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid\r
36001+ * value range.\r
36002+ */\r
36003+int SkPnmiSetStruct(\r
36004+SK_AC *pAC, /* Pointer to adapter context */\r
36005+SK_IOC IoC, /* IO context handle */\r
36006+void *pBuf, /* Buffer which contains the data to be set */\r
36007+unsigned int *pLen, /* Length of buffer */\r
36008+SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */\r
36009+{\r
36010+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
36011+ ("PNMI: SkPnmiSetStruct: Called, BufLen=%d, NetIndex=%d\n",\r
36012+ *pLen, NetIndex));\r
36013+\r
36014+ return (PnmiStruct(pAC, IoC, SK_PNMI_SET, (char *)pBuf,\r
36015+ pLen, NetIndex));\r
36016+}\r
36017+\r
36018+/*****************************************************************************\r
36019+ *\r
36020+ * SkPnmiEvent - Event handler\r
36021+ *\r
36022+ * Description:\r
36023+ * Handles the following events:\r
36024+ * SK_PNMI_EVT_SIRQ_OVERFLOW When a hardware counter overflows an\r
36025+ * interrupt will be generated which is\r
36026+ * first handled by SIRQ which generates a\r
36027+ * this event. The event increments the\r
36028+ * upper 32 bit of the 64 bit counter.\r
36029+ * SK_PNMI_EVT_SEN_XXX The event is generated by the I2C module\r
36030+ * when a sensor reports a warning or\r
36031+ * error. The event will store a trap\r
36032+ * message in the trap buffer.\r
36033+ * SK_PNMI_EVT_CHG_EST_TIMER The timer event was initiated by this\r
36034+ * module and is used to calculate the\r
36035+ * port switches per hour.\r
36036+ * SK_PNMI_EVT_CLEAR_COUNTER The event clears all counters and\r
36037+ * timestamps.\r
36038+ * SK_PNMI_EVT_XMAC_RESET The event is generated by the driver\r
36039+ * before a hard reset of the XMAC is\r
36040+ * performed. All counters will be saved\r
36041+ * and added to the hardware counter\r
36042+ * values after reset to grant continuous\r
36043+ * counter values.\r
36044+ * SK_PNMI_EVT_RLMT_PORT_UP Generated by RLMT to notify that a port\r
36045+ * went logically up. A trap message will\r
36046+ * be stored to the trap buffer.\r
36047+ * SK_PNMI_EVT_RLMT_PORT_DOWN Generated by RLMT to notify that a port\r
36048+ * went logically down. A trap message will\r
36049+ * be stored to the trap buffer.\r
36050+ * SK_PNMI_EVT_RLMT_SEGMENTATION Generated by RLMT to notify that two\r
36051+ * spanning tree root bridges were\r
36052+ * detected. A trap message will be stored\r
36053+ * to the trap buffer.\r
36054+ * SK_PNMI_EVT_RLMT_ACTIVE_DOWN Notifies PNMI that an active port went\r
36055+ * down. PNMI will not further add the\r
36056+ * statistic values to the virtual port.\r
36057+ * SK_PNMI_EVT_RLMT_ACTIVE_UP Notifies PNMI that a port went up and\r
36058+ * is now an active port. PNMI will now\r
36059+ * add the statistic data of this port to\r
36060+ * the virtual port.\r
36061+ * SK_PNMI_EVT_RLMT_SET_NETS Notifies PNMI about the net mode. The first parameter\r
36062+ * contains the number of nets. 1 means single net, 2 means\r
36063+ * dual net. The second parameter is -1\r
36064+ *\r
36065+ * Returns:\r
36066+ * Always 0\r
36067+ */\r
36068+int SkPnmiEvent(\r
36069+SK_AC *pAC, /* Pointer to adapter context */\r
36070+SK_IOC IoC, /* IO context handle */\r
36071+SK_U32 Event, /* Event-Id */\r
36072+SK_EVPARA Param) /* Event dependent parameter */\r
36073+{\r
36074+ unsigned int PhysPortIndex;\r
36075+ unsigned int MaxNetNumber;\r
36076+ int CounterIndex;\r
36077+ SK_U16 MacStatus;\r
36078+ SK_U64 OverflowStatus;\r
36079+ SK_U64 Mask;\r
36080+ int MacType;\r
36081+ SK_U64 Value;\r
36082+ SK_U32 Val32;\r
36083+ SK_U16 Register;\r
36084+ SK_EVPARA EventParam;\r
36085+ SK_U64 NewestValue;\r
36086+ SK_U64 OldestValue;\r
36087+ SK_U64 Delta;\r
36088+ SK_PNMI_ESTIMATE *pEst;\r
36089+ SK_U32 NetIndex;\r
36090+ SK_U32 RetCode;\r
36091+\r
36092+#ifdef DEBUG\r
36093+ if (Event != SK_PNMI_EVT_XMAC_RESET) {\r
36094+\r
36095+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
36096+ ("PNMI: SkPnmiEvent: Called, Event=0x%x, Param=0x%x\n",\r
36097+ (unsigned int)Event, (unsigned int)Param.Para64));\r
36098+ }\r
36099+#endif /* DEBUG */\r
36100+ SK_PNMI_CHECKFLAGS("SkPnmiEvent: On call");\r
36101+\r
36102+ MacType = pAC->GIni.GIMacType;\r
36103+ \r
36104+ switch (Event) {\r
36105+\r
36106+ case SK_PNMI_EVT_SIRQ_OVERFLOW:\r
36107+ PhysPortIndex = (int)Param.Para32[0];\r
36108+ MacStatus = (SK_U16)Param.Para32[1];\r
36109+#ifdef DEBUG\r
36110+ if (PhysPortIndex >= SK_MAX_MACS) {\r
36111+\r
36112+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
36113+ ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_SIRQ_OVERFLOW parameter"\r
36114+ " wrong, PhysPortIndex=0x%x\n",\r
36115+ PhysPortIndex));\r
36116+ return (0);\r
36117+ }\r
36118+#endif /* DEBUG */\r
36119+ OverflowStatus = 0;\r
36120+\r
36121+ /* Check which source caused an overflow interrupt. */\r
36122+ if ((pAC->GIni.GIFunc.pFnMacOverflow(pAC, IoC, PhysPortIndex,\r
36123+ MacStatus, &OverflowStatus) != 0) ||\r
36124+ (OverflowStatus == 0)) {\r
36125+\r
36126+ SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return");\r
36127+ return (0);\r
36128+ }\r
36129+\r
36130+ /*\r
36131+ * Check the overflow status register and increment\r
36132+ * the upper dword of corresponding counter.\r
36133+ */\r
36134+ for (CounterIndex = 0; CounterIndex < sizeof(Mask) * 8;\r
36135+ CounterIndex ++) {\r
36136+\r
36137+ Mask = (SK_U64)1 << CounterIndex;\r
36138+ if ((OverflowStatus & Mask) == 0) {\r
36139+ continue;\r
36140+ }\r
36141+\r
36142+ switch (StatOvrflwBit[CounterIndex][MacType]) {\r
36143+\r
36144+ case SK_PNMI_HTX_UTILUNDER:\r
36145+ case SK_PNMI_HTX_UTILOVER:\r
36146+ if (MacType == SK_MAC_XMAC) {\r
36147+ XM_IN16(IoC, PhysPortIndex, XM_TX_CMD, &Register);\r
36148+ Register |= XM_TX_SAM_LINE;\r
36149+ XM_OUT16(IoC, PhysPortIndex, XM_TX_CMD, Register);\r
36150+ }\r
36151+ break;\r
36152+\r
36153+ case SK_PNMI_HRX_UTILUNDER:\r
36154+ case SK_PNMI_HRX_UTILOVER:\r
36155+ if (MacType == SK_MAC_XMAC) {\r
36156+ XM_IN16(IoC, PhysPortIndex, XM_RX_CMD, &Register);\r
36157+ Register |= XM_RX_SAM_LINE;\r
36158+ XM_OUT16(IoC, PhysPortIndex, XM_RX_CMD, Register);\r
36159+ }\r
36160+ break;\r
36161+\r
36162+ case SK_PNMI_HTX_OCTETHIGH:\r
36163+ case SK_PNMI_HTX_OCTETLOW:\r
36164+ case SK_PNMI_HTX_RESERVED:\r
36165+ case SK_PNMI_HRX_OCTETHIGH:\r
36166+ case SK_PNMI_HRX_OCTETLOW:\r
36167+ case SK_PNMI_HRX_IRLENGTH:\r
36168+ case SK_PNMI_HRX_RESERVED:\r
36169+ \r
36170+ /* The following counters aren't be handled (id > 63). */\r
36171+ case SK_PNMI_HTX_SYNC:\r
36172+ case SK_PNMI_HTX_SYNC_OCTET:\r
36173+ break;\r
36174+\r
36175+ case SK_PNMI_HRX_LONGFRAMES:\r
36176+ if (MacType == SK_MAC_GMAC) {\r
36177+ pAC->Pnmi.Port[PhysPortIndex].\r
36178+ CounterHigh[CounterIndex] ++;\r
36179+ }\r
36180+ break;\r
36181+\r
36182+ default:\r
36183+ pAC->Pnmi.Port[PhysPortIndex].\r
36184+ CounterHigh[CounterIndex] ++;\r
36185+ }\r
36186+ }\r
36187+ break;\r
36188+\r
36189+ case SK_PNMI_EVT_SEN_WAR_LOW:\r
36190+#ifdef DEBUG\r
36191+ if ((unsigned int)Param.Para64 >= (unsigned int)pAC->I2c.MaxSens) {\r
36192+\r
36193+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
36194+ ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_SEN_WAR_LOW parameter wrong, SensorIndex=%d\n",\r
36195+ (unsigned int)Param.Para64));\r
36196+ return (0);\r
36197+ }\r
36198+#endif /* DEBUG */\r
36199+\r
36200+ /*\r
36201+ * Store a trap message in the trap buffer and generate\r
36202+ * an event for user space applications with the\r
36203+ * SK_DRIVER_SENDEVENT macro.\r
36204+ */\r
36205+ QueueSensorTrap(pAC, OID_SKGE_TRAP_SEN_WAR_LOW,\r
36206+ (unsigned int)Param.Para64);\r
36207+ (void)SK_DRIVER_SENDEVENT(pAC, IoC);\r
36208+ break;\r
36209+\r
36210+ case SK_PNMI_EVT_SEN_WAR_UPP:\r
36211+#ifdef DEBUG\r
36212+ if ((unsigned int)Param.Para64 >= (unsigned int)pAC->I2c.MaxSens) {\r
36213+\r
36214+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
36215+ ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_SEN_WAR_UPP parameter wrong, SensorIndex=%d\n",\r
36216+ (unsigned int)Param.Para64));\r
36217+ return (0);\r
36218+ }\r
36219+#endif /* DEBUG */\r
36220+\r
36221+ /*\r
36222+ * Store a trap message in the trap buffer and generate\r
36223+ * an event for user space applications with the\r
36224+ * SK_DRIVER_SENDEVENT macro.\r
36225+ */\r
36226+ QueueSensorTrap(pAC, OID_SKGE_TRAP_SEN_WAR_UPP,\r
36227+ (unsigned int)Param.Para64);\r
36228+ (void)SK_DRIVER_SENDEVENT(pAC, IoC);\r
36229+ break;\r
36230+\r
36231+ case SK_PNMI_EVT_SEN_ERR_LOW:\r
36232+#ifdef DEBUG\r
36233+ if ((unsigned int)Param.Para64 >= (unsigned int)pAC->I2c.MaxSens) {\r
36234+\r
36235+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
36236+ ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_SEN_ERR_LOW parameter wrong, SensorIndex=%d\n",\r
36237+ (unsigned int)Param.Para64));\r
36238+ return (0);\r
36239+ }\r
36240+#endif /* DEBUG */\r
36241+\r
36242+ /*\r
36243+ * Store a trap message in the trap buffer and generate\r
36244+ * an event for user space applications with the\r
36245+ * SK_DRIVER_SENDEVENT macro.\r
36246+ */\r
36247+ QueueSensorTrap(pAC, OID_SKGE_TRAP_SEN_ERR_LOW,\r
36248+ (unsigned int)Param.Para64);\r
36249+ (void)SK_DRIVER_SENDEVENT(pAC, IoC);\r
36250+ break;\r
36251+ \r
36252+ case SK_PNMI_EVT_SEN_ERR_UPP:\r
36253+#ifdef DEBUG\r
36254+ if ((unsigned int)Param.Para64 >= (unsigned int)pAC->I2c.MaxSens) {\r
36255+\r
36256+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
36257+ ("PNMI: ERR: SK_PNMI_EVT_SEN_ERR_UPP parameter wrong, SensorIndex=%d\n",\r
36258+ (unsigned int)Param.Para64));\r
36259+ return (0);\r
36260+ }\r
36261+#endif /* DEBUG */\r
36262+\r
36263+ /*\r
36264+ * Store a trap message in the trap buffer and generate\r
36265+ * an event for user space applications with the\r
36266+ * SK_DRIVER_SENDEVENT macro.\r
36267+ */\r
36268+ QueueSensorTrap(pAC, OID_SKGE_TRAP_SEN_ERR_UPP,\r
36269+ (unsigned int)Param.Para64);\r
36270+ (void)SK_DRIVER_SENDEVENT(pAC, IoC);\r
36271+ break;\r
36272+\r
36273+ case SK_PNMI_EVT_CHG_EST_TIMER:\r
36274+ /*\r
36275+ * Calculate port switch average on a per hour basis\r
36276+ * Time interval for check : 28125 ms (SK_PNMI_EVT_TIMER_CHECK)\r
36277+ * Number of values for average : 8\r
36278+ *\r
36279+ * Be careful in changing these values, on change check\r
36280+ * - typedef of SK_PNMI_ESTIMATE (Size of EstValue\r
36281+ * array one less than value number)\r
36282+ * - Timer initialization SkTimerStart() in SkPnmiInit\r
36283+ * - Delta value below must be multiplicated with power of 2\r
36284+ */\r
36285+ pEst = &pAC->Pnmi.RlmtChangeEstimate;\r
36286+ CounterIndex = pEst->EstValueIndex + 1;\r
36287+ if (CounterIndex == 7) {\r
36288+\r
36289+ CounterIndex = 0;\r
36290+ }\r
36291+ pEst->EstValueIndex = CounterIndex;\r
36292+\r
36293+ NewestValue = pAC->Pnmi.RlmtChangeCts;\r
36294+ OldestValue = pEst->EstValue[CounterIndex];\r
36295+ pEst->EstValue[CounterIndex] = NewestValue;\r
36296+\r
36297+ /*\r
36298+ * Calculate average. Delta stores the number of\r
36299+ * port switches per 28125 * 8 = 225000 ms\r
36300+ */\r
36301+ if (NewestValue >= OldestValue) {\r
36302+\r
36303+ Delta = NewestValue - OldestValue;\r
36304+ }\r
36305+ else {\r
36306+ /* Overflow situation. */\r
36307+ Delta = (SK_U64)(0 - OldestValue) + NewestValue;\r
36308+ }\r
36309+\r
36310+ /*\r
36311+ * Extrapolate delta to port switches per hour.\r
36312+ * Estimate = Delta * (3600000 / 225000)\r
36313+ * = Delta * 16\r
36314+ * = Delta << 4\r
36315+ */\r
36316+ pAC->Pnmi.RlmtChangeEstimate.Estimate = Delta << 4;\r
36317+\r
36318+ /*\r
36319+ * Check if threshold is exceeded. If the threshold is\r
36320+ * permanently exceeded every 28125 ms an event will be\r
36321+ * generated to remind the user of this condition.\r
36322+ */\r
36323+ if ((pAC->Pnmi.RlmtChangeThreshold != 0) &&\r
36324+ (pAC->Pnmi.RlmtChangeEstimate.Estimate >=\r
36325+ pAC->Pnmi.RlmtChangeThreshold)) {\r
36326+\r
36327+ QueueSimpleTrap(pAC, OID_SKGE_TRAP_RLMT_CHANGE_THRES);\r
36328+ (void)SK_DRIVER_SENDEVENT(pAC, IoC);\r
36329+ }\r
36330+\r
36331+ SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));\r
36332+ \r
36333+ SkTimerStart(pAC, IoC, &pAC->Pnmi.RlmtChangeEstimate.EstTimer,\r
36334+ SK_PNMI_EVT_TIMER_CHECK, SKGE_PNMI, SK_PNMI_EVT_CHG_EST_TIMER,\r
36335+ EventParam);\r
36336+ break;\r
36337+\r
36338+ case SK_PNMI_EVT_CLEAR_COUNTER:\r
36339+ /*\r
36340+ * Param.Para32[0] contains the NetIndex (0 ..1).\r
36341+ * Param.Para32[1] is reserved, contains -1.\r
36342+ */\r
36343+ NetIndex = (SK_U32)Param.Para32[0];\r
36344+\r
36345+#ifdef DEBUG\r
36346+ if (NetIndex >= pAC->Rlmt.NumNets) {\r
36347+\r
36348+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
36349+ ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_CLEAR_COUNTER parameter wrong, NetIndex=%d\n",\r
36350+ NetIndex));\r
36351+\r
36352+ return (0);\r
36353+ }\r
36354+#endif /* DEBUG */\r
36355+\r
36356+ /*\r
36357+ * Set all counters and timestamps to zero.\r
36358+ * The according NetIndex is required as a\r
36359+ * parameter of the event.\r
36360+ */\r
36361+ ResetCounter(pAC, IoC, NetIndex);\r
36362+ break;\r
36363+\r
36364+ case SK_PNMI_EVT_XMAC_RESET:\r
36365+ /*\r
36366+ * To grant continuous counter values store the current\r
36367+ * XMAC statistic values to the entries 1..n of the\r
36368+ * CounterOffset array. XMAC Errata #2\r
36369+ */\r
36370+#ifdef DEBUG\r
36371+ if ((unsigned int)Param.Para64 >= SK_MAX_MACS) {\r
36372+\r
36373+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
36374+ ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_XMAC_RESET parameter wrong, PhysPortIndex=%d\n",\r
36375+ (unsigned int)Param.Para64));\r
36376+ return (0);\r
36377+ }\r
36378+#endif /* DEBUG */\r
36379+\r
36380+ PhysPortIndex = (unsigned int)Param.Para64;\r
36381+\r
36382+ /* Update XMAC statistic to get fresh values. */\r
36383+ if (MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1) !=\r
36384+ SK_PNMI_ERR_OK) {\r
36385+\r
36386+ SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return");\r
36387+ return (0);\r
36388+ }\r
36389+\r
36390+ /* Increment semaphore to indicate that an update was already done. */\r
36391+ pAC->Pnmi.MacUpdatedFlag ++;\r
36392+\r
36393+ for (CounterIndex = 0; CounterIndex < SK_PNMI_MAX_IDX;\r
36394+ CounterIndex ++) {\r
36395+\r
36396+ if (!StatAddr[CounterIndex][MacType].GetOffset) {\r
36397+ continue;\r
36398+ }\r
36399+\r
36400+ pAC->Pnmi.Port[PhysPortIndex].CounterOffset[CounterIndex] =\r
36401+ GetPhysStatVal(pAC, IoC, PhysPortIndex, CounterIndex);\r
36402+ \r
36403+ pAC->Pnmi.Port[PhysPortIndex].CounterHigh[CounterIndex] = 0;\r
36404+ }\r
36405+\r
36406+ pAC->Pnmi.MacUpdatedFlag --;\r
36407+ break;\r
36408+\r
36409+ case SK_PNMI_EVT_RLMT_PORT_UP:\r
36410+ PhysPortIndex = (unsigned int)Param.Para32[0];\r
36411+#ifdef DEBUG\r
36412+ if (PhysPortIndex >= SK_MAX_MACS) {\r
36413+\r
36414+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
36415+ ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_PORT_UP parameter"\r
36416+ " wrong, PhysPortIndex=%d\n", PhysPortIndex));\r
36417+\r
36418+ return (0);\r
36419+ }\r
36420+#endif /* DEBUG */\r
36421+\r
36422+ /*\r
36423+ * Store a trap message in the trap buffer and generate an event for\r
36424+ * user space applications with the SK_DRIVER_SENDEVENT macro.\r
36425+ */\r
36426+ QueueRlmtPortTrap(pAC, OID_SKGE_TRAP_RLMT_PORT_UP, PhysPortIndex);\r
36427+ (void)SK_DRIVER_SENDEVENT(pAC, IoC);\r
36428+\r
36429+ /* Bugfix for XMAC errata (#10620). */\r
36430+ if (MacType == SK_MAC_XMAC) {\r
36431+ /* Add incremental difference to offset (#10620). */\r
36432+ (void)pAC->GIni.GIFunc.pFnMacStatistic(pAC, IoC, PhysPortIndex,\r
36433+ XM_RXE_SHT_ERR, &Val32);\r
36434+ \r
36435+ Value = (((SK_U64)pAC->Pnmi.Port[PhysPortIndex].\r
36436+ CounterHigh[SK_PNMI_HRX_SHORTS] << 32) | (SK_U64)Val32);\r
36437+ \r
36438+ pAC->Pnmi.Port[PhysPortIndex].CounterOffset[SK_PNMI_HRX_SHORTS] +=\r
36439+ Value - pAC->Pnmi.Port[PhysPortIndex].RxShortZeroMark;\r
36440+ }\r
36441+ \r
36442+ /* Tell VctStatus() that a link was up meanwhile. */\r
36443+ pAC->Pnmi.VctStatus[PhysPortIndex] |= SK_PNMI_VCT_LINK; \r
36444+ break;\r
36445+\r
36446+ case SK_PNMI_EVT_RLMT_PORT_DOWN:\r
36447+ PhysPortIndex = (unsigned int)Param.Para32[0];\r
36448+\r
36449+#ifdef DEBUG\r
36450+ if (PhysPortIndex >= SK_MAX_MACS) {\r
36451+\r
36452+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
36453+ ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_PORT_DOWN parameter"\r
36454+ " wrong, PhysPortIndex=%d\n", PhysPortIndex));\r
36455+\r
36456+ return (0);\r
36457+ }\r
36458+#endif /* DEBUG */\r
36459+\r
36460+ /*\r
36461+ * Store a trap message in the trap buffer and generate an event for\r
36462+ * user space applications with the SK_DRIVER_SENDEVENT macro.\r
36463+ */\r
36464+ QueueRlmtPortTrap(pAC, OID_SKGE_TRAP_RLMT_PORT_DOWN, PhysPortIndex);\r
36465+ (void)SK_DRIVER_SENDEVENT(pAC, IoC);\r
36466+\r
36467+ /* Bugfix #10620 - get zero level for incremental difference. */\r
36468+ if (MacType == SK_MAC_XMAC) {\r
36469+\r
36470+ (void)pAC->GIni.GIFunc.pFnMacStatistic(pAC, IoC, PhysPortIndex,\r
36471+ XM_RXE_SHT_ERR, &Val32);\r
36472+ \r
36473+ pAC->Pnmi.Port[PhysPortIndex].RxShortZeroMark =\r
36474+ (((SK_U64)pAC->Pnmi.Port[PhysPortIndex].\r
36475+ CounterHigh[SK_PNMI_HRX_SHORTS] << 32) | (SK_U64)Val32);\r
36476+ }\r
36477+ break;\r
36478+\r
36479+ case SK_PNMI_EVT_RLMT_ACTIVE_DOWN:\r
36480+ PhysPortIndex = (unsigned int)Param.Para32[0];\r
36481+ NetIndex = (SK_U32)Param.Para32[1];\r
36482+\r
36483+#ifdef DEBUG\r
36484+ if (PhysPortIndex >= SK_MAX_MACS) {\r
36485+\r
36486+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
36487+ ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_ACTIVE_DOWN parameter too high, PhysPort=%d\n",\r
36488+ PhysPortIndex));\r
36489+ }\r
36490+\r
36491+ if (NetIndex >= pAC->Rlmt.NumNets) {\r
36492+\r
36493+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
36494+ ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_ACTIVE_DOWN parameter too high, NetIndex=%d\n",\r
36495+ NetIndex));\r
36496+ }\r
36497+#endif /* DEBUG */\r
36498+\r
36499+ /* For now, ignore event if NetIndex != 0. */\r
36500+ if (Param.Para32[1] != 0) {\r
36501+\r
36502+ return (0);\r
36503+ }\r
36504+\r
36505+ /* Nothing to do if port is already inactive. */\r
36506+ if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {\r
36507+\r
36508+ return (0);\r
36509+ }\r
36510+\r
36511+ /*\r
36512+ * Update statistic counters to calculate new offset for the virtual\r
36513+ * port and increment semaphore to indicate that an update was already\r
36514+ * done.\r
36515+ */\r
36516+ if (MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1) !=\r
36517+ SK_PNMI_ERR_OK) {\r
36518+\r
36519+ SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return");\r
36520+ return (0);\r
36521+ }\r
36522+ pAC->Pnmi.MacUpdatedFlag ++;\r
36523+\r
36524+ /*\r
36525+ * Calculate new counter offset for virtual port to grant continous\r
36526+ * counting on port switches. The virtual port consists of all currently\r
36527+ * active ports. The port down event indicates that a port is removed\r
36528+ * from the virtual port. Therefore add the counter value of the removed\r
36529+ * port to the CounterOffset for the virtual port to grant the same\r
36530+ * counter value.\r
36531+ */\r
36532+ for (CounterIndex = 0; CounterIndex < SK_PNMI_MAX_IDX;\r
36533+ CounterIndex ++) {\r
36534+\r
36535+ if (!StatAddr[CounterIndex][MacType].GetOffset) {\r
36536+ continue;\r
36537+ }\r
36538+\r
36539+ Value = GetPhysStatVal(pAC, IoC, PhysPortIndex, CounterIndex);\r
36540+\r
36541+ pAC->Pnmi.VirtualCounterOffset[CounterIndex] += Value;\r
36542+ }\r
36543+\r
36544+ /* Set port to inactive. */\r
36545+ pAC->Pnmi.Port[PhysPortIndex].ActiveFlag = SK_FALSE;\r
36546+\r
36547+ pAC->Pnmi.MacUpdatedFlag --;\r
36548+ break;\r
36549+\r
36550+ case SK_PNMI_EVT_RLMT_ACTIVE_UP:\r
36551+ PhysPortIndex = (unsigned int)Param.Para32[0];\r
36552+ NetIndex = (SK_U32)Param.Para32[1];\r
36553+\r
36554+#ifdef DEBUG\r
36555+ if (PhysPortIndex >= SK_MAX_MACS) {\r
36556+\r
36557+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
36558+ ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_ACTIVE_UP parameter too high, PhysPort=%d\n",\r
36559+ PhysPortIndex));\r
36560+ }\r
36561+\r
36562+ if (NetIndex >= pAC->Rlmt.NumNets) {\r
36563+\r
36564+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
36565+ ("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_ACTIVE_UP parameter too high, NetIndex=%d\n",\r
36566+ NetIndex));\r
36567+ }\r
36568+#endif /* DEBUG */\r
36569+\r
36570+ /* For now, ignore event if NetIndex != 0. */\r
36571+ if (Param.Para32[1] != 0) {\r
36572+\r
36573+ return (0);\r
36574+ }\r
36575+\r
36576+ /* Nothing to do if port is already inactive. */\r
36577+ if (pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {\r
36578+\r
36579+ return (0);\r
36580+ }\r
36581+\r
36582+ /* Statistic maintenance. */\r
36583+ pAC->Pnmi.RlmtChangeCts ++;\r
36584+ pAC->Pnmi.RlmtChangeTime = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC));\r
36585+\r
36586+ /*\r
36587+ * Store a trap message in the trap buffer and generate an event for\r
36588+ * user space applications with the SK_DRIVER_SENDEVENT macro.\r
36589+ */\r
36590+ QueueRlmtNewMacTrap(pAC, PhysPortIndex);\r
36591+ (void)SK_DRIVER_SENDEVENT(pAC, IoC);\r
36592+\r
36593+ /*\r
36594+ * Update statistic counters to calculate new offset for the virtual\r
36595+ * port and increment semaphore to indicate that an update was\r
36596+ * already done.\r
36597+ */\r
36598+ if (MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1) !=\r
36599+ SK_PNMI_ERR_OK) {\r
36600+\r
36601+ SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return");\r
36602+ return (0);\r
36603+ }\r
36604+ pAC->Pnmi.MacUpdatedFlag ++;\r
36605+\r
36606+ /*\r
36607+ * Calculate new counter offset for virtual port to grant continous\r
36608+ * counting on port switches. A new port is added to the virtual port.\r
36609+ * Therefore substract the counter value of the new port from the\r
36610+ * CounterOffset for the virtual port to grant the same value.\r
36611+ */\r
36612+ for (CounterIndex = 0; CounterIndex < SK_PNMI_MAX_IDX;\r
36613+ CounterIndex ++) {\r
36614+\r
36615+ if (!StatAddr[CounterIndex][MacType].GetOffset) {\r
36616+ continue;\r
36617+ }\r
36618+\r
36619+ Value = GetPhysStatVal(pAC, IoC, PhysPortIndex, CounterIndex);\r
36620+\r
36621+ pAC->Pnmi.VirtualCounterOffset[CounterIndex] -= Value;\r
36622+ }\r
36623+\r
36624+ /* Set port to active. */\r
36625+ pAC->Pnmi.Port[PhysPortIndex].ActiveFlag = SK_TRUE;\r
36626+\r
36627+ pAC->Pnmi.MacUpdatedFlag --;\r
36628+ break;\r
36629+\r
36630+ case SK_PNMI_EVT_RLMT_SEGMENTATION:\r
36631+ /* Para.Para32[0] contains the NetIndex. */\r
36632+\r
36633+ /*\r
36634+ * Store a trap message in the trap buffer and generate an event for\r
36635+ * user space applications with the SK_DRIVER_SENDEVENT macro.\r
36636+ */\r
36637+ QueueSimpleTrap(pAC, OID_SKGE_TRAP_RLMT_SEGMENTATION);\r
36638+ (void)SK_DRIVER_SENDEVENT(pAC, IoC);\r
36639+ break;\r
36640+\r
36641+ case SK_PNMI_EVT_RLMT_SET_NETS:\r
36642+ /*\r
36643+ * Param.Para32[0] contains the number of Nets.\r
36644+ * Param.Para32[1] is reserved, contains -1.\r
36645+ */\r
36646+ /* Check number of nets. */\r
36647+ MaxNetNumber = pAC->GIni.GIMacsFound;\r
36648+ \r
36649+ if (((unsigned int)Param.Para32[0] < 1) ||\r
36650+ ((unsigned int)Param.Para32[0] > MaxNetNumber)) {\r
36651+ \r
36652+ return (SK_PNMI_ERR_UNKNOWN_NET);\r
36653+ }\r
36654+\r
36655+ if ((unsigned int)Param.Para32[0] == 1) { /* SingleNet mode. */\r
36656+ pAC->Pnmi.DualNetActiveFlag = SK_FALSE;\r
36657+ }\r
36658+ else { /* DualNet mode. */\r
36659+ pAC->Pnmi.DualNetActiveFlag = SK_TRUE;\r
36660+ }\r
36661+ break;\r
36662+\r
36663+ case SK_PNMI_EVT_VCT_RESET:\r
36664+ PhysPortIndex = Param.Para32[0];\r
36665+ \r
36666+ if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_PENDING) {\r
36667+ \r
36668+ RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_FALSE);\r
36669+ \r
36670+ if (RetCode == 2) {\r
36671+ /*\r
36672+ * VCT test is still running.\r
36673+ * Start VCT timer counter again.\r
36674+ */\r
36675+ SK_MEMSET((char *)&Param, 0, sizeof(Param));\r
36676+ \r
36677+ Param.Para32[0] = PhysPortIndex;\r
36678+ Param.Para32[1] = -1;\r
36679+ \r
36680+ SkTimerStart(pAC, IoC, &pAC->Pnmi.VctTimeout[PhysPortIndex],\r
36681+ SK_PNMI_VCT_TIMER_CHECK, SKGE_PNMI, SK_PNMI_EVT_VCT_RESET, Param);\r
36682+ \r
36683+ break;\r
36684+ }\r
36685+ \r
36686+ VctGetResults(pAC, IoC, PhysPortIndex);\r
36687+ \r
36688+ EventParam.Para32[0] = PhysPortIndex;\r
36689+ EventParam.Para32[1] = -1;\r
36690+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, EventParam);\r
36691+\r
36692+ /* SkEventDispatcher(pAC, IoC); */\r
36693+ }\r
36694+ \r
36695+ break;\r
36696+\r
36697+ default:\r
36698+ break;\r
36699+ }\r
36700+\r
36701+ SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return");\r
36702+ return (0);\r
36703+}\r
36704+\r
36705+\r
36706+/******************************************************************************\r
36707+ *\r
36708+ * Private functions\r
36709+ *\r
36710+ */\r
36711+\r
36712+/*****************************************************************************\r
36713+ *\r
36714+ * PnmiVar - Gets, presets, and sets single OIDs\r
36715+ *\r
36716+ * Description:\r
36717+ * Looks up the requested OID, calls the corresponding handler\r
36718+ * function, and passes the parameters with the get, preset, or\r
36719+ * set command. The function is called by SkGePnmiGetVar,\r
36720+ * SkGePnmiPreSetVar, or SkGePnmiSetVar.\r
36721+ *\r
36722+ * Returns:\r
36723+ * SK_PNMI_ERR_XXX. For details have a look at the description of the\r
36724+ * calling functions.\r
36725+ * SK_PNMI_ERR_UNKNOWN_NET The requested NetIndex doesn't exist\r
36726+ */\r
36727+PNMI_STATIC int PnmiVar(\r
36728+SK_AC *pAC, /* Pointer to adapter context */\r
36729+SK_IOC IoC, /* IO context handle */\r
36730+int Action, /* GET/PRESET/SET action */\r
36731+SK_U32 Id, /* Object ID that is to be processed */\r
36732+char *pBuf, /* Buffer used for the management data transfer */\r
36733+unsigned int *pLen, /* Total length of pBuf management data */\r
36734+SK_U32 Instance, /* Instance (1..n) that is to be set or -1 */\r
36735+SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */\r
36736+{\r
36737+ unsigned int TableIndex;\r
36738+ int Ret;\r
36739+\r
36740+ if ((TableIndex = LookupId(Id)) == (unsigned int)(-1)) {\r
36741+\r
36742+ *pLen = 0;\r
36743+ return (SK_PNMI_ERR_UNKNOWN_OID);\r
36744+ }\r
36745+ \r
36746+ /* Check NetIndex. */\r
36747+ if (NetIndex >= pAC->Rlmt.NumNets) {\r
36748+ return (SK_PNMI_ERR_UNKNOWN_NET);\r
36749+ }\r
36750+\r
36751+ SK_PNMI_CHECKFLAGS("PnmiVar: On call");\r
36752+\r
36753+ Ret = IdTable[TableIndex].Func(pAC, IoC, Action, Id, pBuf, pLen,\r
36754+ Instance, TableIndex, NetIndex);\r
36755+\r
36756+ SK_PNMI_CHECKFLAGS("PnmiVar: On return");\r
36757+\r
36758+ return (Ret);\r
36759+}\r
36760+\r
36761+/*****************************************************************************\r
36762+ *\r
36763+ * PnmiStruct - Presets and Sets data in structure SK_PNMI_STRUCT_DATA\r
36764+ *\r
36765+ * Description:\r
36766+ * The return value of the function will also be stored in\r
36767+ * SK_PNMI_STRUCT_DATA if the passed buffer has the minimum size of\r
36768+ * SK_PNMI_MIN_STRUCT_SIZE. The sub-function runs through the IdTable,\r
36769+ * checks which OIDs are able to set, and calls the handler function of\r
36770+ * the OID to perform the set. The return value of the function will\r
36771+ * also be stored in SK_PNMI_STRUCT_DATA if the passed buffer has the\r
36772+ * minimum size of SK_PNMI_MIN_STRUCT_SIZE. The function is called\r
36773+ * by SkGePnmiPreSetStruct and SkGePnmiSetStruct.\r
36774+ *\r
36775+ * Returns:\r
36776+ * SK_PNMI_ERR_XXX. The codes are described in the calling functions.\r
36777+ * SK_PNMI_ERR_UNKNOWN_NET The requested NetIndex doesn't exist\r
36778+ */\r
36779+PNMI_STATIC int PnmiStruct(\r
36780+SK_AC *pAC, /* Pointer to adapter context */\r
36781+SK_IOC IoC, /* IO context handle */\r
36782+int Action, /* PRESET/SET action to be performed */\r
36783+char *pBuf, /* Buffer used for the management data transfer */\r
36784+unsigned int *pLen, /* Length of pBuf management data buffer */\r
36785+SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */\r
36786+{\r
36787+ int Ret;\r
36788+ unsigned int TableIndex;\r
36789+ unsigned int DstOffset;\r
36790+ unsigned int Len;\r
36791+ unsigned int InstanceNo;\r
36792+ unsigned int InstanceCnt;\r
36793+ SK_U32 Instance;\r
36794+ SK_U32 Id;\r
36795+\r
36796+ /* Check if the passed buffer has the right size. */\r
36797+ if (*pLen < SK_PNMI_STRUCT_SIZE) {\r
36798+\r
36799+ /* Check if we can return the error within the buffer. */\r
36800+ if (*pLen >= SK_PNMI_MIN_STRUCT_SIZE) {\r
36801+\r
36802+ SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_TOO_SHORT, (SK_U32)(-1));\r
36803+ }\r
36804+\r
36805+ *pLen = SK_PNMI_STRUCT_SIZE;\r
36806+ return (SK_PNMI_ERR_TOO_SHORT);\r
36807+ }\r
36808+ \r
36809+ /* Check NetIndex. */\r
36810+ if (NetIndex >= pAC->Rlmt.NumNets) {\r
36811+ return (SK_PNMI_ERR_UNKNOWN_NET);\r
36812+ }\r
36813+ \r
36814+ SK_PNMI_CHECKFLAGS("PnmiStruct: On call");\r
36815+\r
36816+ /*\r
36817+ * Update the values of RLMT and SIRQ and increment semaphores to\r
36818+ * indicate that an update was already done.\r
36819+ */\r
36820+ if ((Ret = RlmtUpdate(pAC, IoC, NetIndex)) != SK_PNMI_ERR_OK) {\r
36821+\r
36822+ SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1));\r
36823+ *pLen = SK_PNMI_MIN_STRUCT_SIZE;\r
36824+ return (Ret);\r
36825+ }\r
36826+\r
36827+ if ((Ret = SirqUpdate(pAC, IoC)) != SK_PNMI_ERR_OK) {\r
36828+\r
36829+ SK_PNMI_SET_STAT(pBuf, Ret, (SK_U32)(-1));\r
36830+ *pLen = SK_PNMI_MIN_STRUCT_SIZE;\r
36831+ return (Ret);\r
36832+ }\r
36833+\r
36834+ pAC->Pnmi.RlmtUpdatedFlag ++;\r
36835+ pAC->Pnmi.SirqUpdatedFlag ++;\r
36836+\r
36837+ /* PRESET/SET values. */\r
36838+ for (TableIndex = 0; TableIndex < ID_TABLE_SIZE; TableIndex ++) {\r
36839+\r
36840+ if ((IdTable[TableIndex].Access != SK_PNMI_RW) &&\r
36841+ (IdTable[TableIndex].Access != SK_PNMI_WO)) {\r
36842+ continue;\r
36843+ }\r
36844+\r
36845+ InstanceNo = IdTable[TableIndex].InstanceNo;\r
36846+ Id = IdTable[TableIndex].Id;\r
36847+\r
36848+ for (InstanceCnt = 1; InstanceCnt <= InstanceNo;\r
36849+ InstanceCnt ++) {\r
36850+\r
36851+ DstOffset = IdTable[TableIndex].Offset +\r
36852+ (InstanceCnt - 1) * IdTable[TableIndex].StructSize;\r
36853+\r
36854+ /*\r
36855+ * Because VPD multiple instance variables are\r
36856+ * not setable we do not need to evaluate VPD\r
36857+ * instances. Have a look to VPD instance\r
36858+ * calculation in SkPnmiGetStruct().\r
36859+ */\r
36860+ Instance = (SK_U32)InstanceCnt;\r
36861+\r
36862+ /* Evaluate needed buffer length. */\r
36863+ Len = 0;\r
36864+ Ret = IdTable[TableIndex].Func(pAC, IoC,\r
36865+ SK_PNMI_GET, IdTable[TableIndex].Id,\r
36866+ NULL, &Len, Instance, TableIndex, NetIndex);\r
36867+\r
36868+ if (Ret == SK_PNMI_ERR_UNKNOWN_INST) {\r
36869+\r
36870+ break;\r
36871+ }\r
36872+ if (Ret != SK_PNMI_ERR_TOO_SHORT) {\r
36873+\r
36874+ pAC->Pnmi.RlmtUpdatedFlag --;\r
36875+ pAC->Pnmi.SirqUpdatedFlag --;\r
36876+\r
36877+ SK_PNMI_CHECKFLAGS("PnmiStruct: On return");\r
36878+ SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_GENERAL, DstOffset);\r
36879+ *pLen = SK_PNMI_MIN_STRUCT_SIZE;\r
36880+ return (SK_PNMI_ERR_GENERAL);\r
36881+ }\r
36882+ if (Id == OID_SKGE_VPD_ACTION) {\r
36883+\r
36884+ switch (*(pBuf + DstOffset)) {\r
36885+\r
36886+ case SK_PNMI_VPD_CREATE:\r
36887+ Len = 3 + *(pBuf + DstOffset + 3);\r
36888+ break;\r
36889+\r
36890+ case SK_PNMI_VPD_DELETE:\r
36891+ Len = 3;\r
36892+ break;\r
36893+\r
36894+ default:\r
36895+ Len = 1;\r
36896+ break;\r
36897+ }\r
36898+ }\r
36899+\r
36900+ /* Call the OID handler function. */\r
36901+ Ret = IdTable[TableIndex].Func(pAC, IoC, Action,\r
36902+ IdTable[TableIndex].Id, pBuf + DstOffset,\r
36903+ &Len, Instance, TableIndex, NetIndex);\r
36904+\r
36905+ if (Ret != SK_PNMI_ERR_OK) {\r
36906+\r
36907+ pAC->Pnmi.RlmtUpdatedFlag --;\r
36908+ pAC->Pnmi.SirqUpdatedFlag --;\r
36909+\r
36910+ SK_PNMI_CHECKFLAGS("PnmiStruct: On return");\r
36911+ SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_BAD_VALUE, DstOffset);\r
36912+ *pLen = SK_PNMI_MIN_STRUCT_SIZE;\r
36913+ return (SK_PNMI_ERR_BAD_VALUE);\r
36914+ }\r
36915+ }\r
36916+ }\r
36917+\r
36918+ pAC->Pnmi.RlmtUpdatedFlag --;\r
36919+ pAC->Pnmi.SirqUpdatedFlag --;\r
36920+\r
36921+ SK_PNMI_CHECKFLAGS("PnmiStruct: On return");\r
36922+ SK_PNMI_SET_STAT(pBuf, SK_PNMI_ERR_OK, (SK_U32)(-1));\r
36923+ return (SK_PNMI_ERR_OK);\r
36924+}\r
36925+\r
36926+/*****************************************************************************\r
36927+ *\r
36928+ * LookupId - Lookup an OID in the IdTable\r
36929+ *\r
36930+ * Description:\r
36931+ * Scans the IdTable to find the table entry of an OID.\r
36932+ *\r
36933+ * Returns:\r
36934+ * The table index or -1 if not found.\r
36935+ */\r
36936+PNMI_STATIC int LookupId(\r
36937+SK_U32 Id) /* Object identifier to be searched */\r
36938+{\r
36939+ int i;\r
36940+\r
36941+ for (i = 0; i < ID_TABLE_SIZE; i++) {\r
36942+\r
36943+ if (IdTable[i].Id == Id) {\r
36944+\r
36945+ return (i);\r
36946+ }\r
36947+ }\r
36948+\r
36949+ return (-1);\r
36950+}\r
36951+\r
36952+/*****************************************************************************\r
36953+ *\r
36954+ * OidStruct - Handler of OID_SKGE_ALL_DATA\r
36955+ *\r
36956+ * Description:\r
36957+ * This OID performs a Get/Preset/SetStruct call and returns all data\r
36958+ * in a SK_PNMI_STRUCT_DATA structure.\r
36959+ *\r
36960+ * Returns:\r
36961+ * SK_PNMI_ERR_OK The request was successfully performed.\r
36962+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.\r
36963+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain\r
36964+ * the correct data (e.g. a 32bit value is\r
36965+ * needed, but a 16 bit value was passed).\r
36966+ * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid\r
36967+ * value range.\r
36968+ * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set.\r
36969+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't\r
36970+ * exist (e.g. port instance 3 on a two port\r
36971+ * adapter.\r
36972+ */\r
36973+PNMI_STATIC int OidStruct(\r
36974+SK_AC *pAC, /* Pointer to adapter context */\r
36975+SK_IOC IoC, /* IO context handle */\r
36976+int Action, /* GET/PRESET/SET action */\r
36977+SK_U32 Id, /* Object ID that is to be processed */\r
36978+char *pBuf, /* Buffer used for the management data transfer */\r
36979+unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */\r
36980+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */\r
36981+unsigned int TableIndex, /* Index to the Id table */\r
36982+SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */\r
36983+{\r
36984+ if (Id != OID_SKGE_ALL_DATA) {\r
36985+\r
36986+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR003, SK_PNMI_ERR003MSG);\r
36987+\r
36988+ *pLen = 0;\r
36989+ return (SK_PNMI_ERR_GENERAL);\r
36990+ }\r
36991+\r
36992+ /* Check instance. We only handle single instance variables. */\r
36993+ if (Instance != (SK_U32)(-1) && Instance != 1) {\r
36994+\r
36995+ *pLen = 0;\r
36996+ return (SK_PNMI_ERR_UNKNOWN_INST);\r
36997+ }\r
36998+\r
36999+ switch (Action) {\r
37000+\r
37001+ case SK_PNMI_GET:\r
37002+ return (SkPnmiGetStruct(pAC, IoC, pBuf, pLen, NetIndex));\r
37003+\r
37004+ case SK_PNMI_PRESET:\r
37005+ return (SkPnmiPreSetStruct(pAC, IoC, pBuf, pLen, NetIndex));\r
37006+\r
37007+ case SK_PNMI_SET:\r
37008+ return (SkPnmiSetStruct(pAC, IoC, pBuf, pLen, NetIndex));\r
37009+ }\r
37010+\r
37011+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR004, SK_PNMI_ERR004MSG);\r
37012+\r
37013+ *pLen = 0;\r
37014+ return (SK_PNMI_ERR_GENERAL);\r
37015+}\r
37016+\r
37017+/*****************************************************************************\r
37018+ *\r
37019+ * Perform - OID handler of OID_SKGE_ACTION\r
37020+ *\r
37021+ * Description:\r
37022+ * None.\r
37023+ *\r
37024+ * Returns:\r
37025+ * SK_PNMI_ERR_OK The request was successfully performed.\r
37026+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.\r
37027+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain\r
37028+ * the correct data (e.g. a 32bit value is\r
37029+ * needed, but a 16 bit value was passed).\r
37030+ * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid\r
37031+ * value range.\r
37032+ * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set.\r
37033+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't\r
37034+ * exist (e.g. port instance 3 on a two port\r
37035+ * adapter.\r
37036+ */\r
37037+PNMI_STATIC int Perform(\r
37038+SK_AC *pAC, /* Pointer to adapter context */\r
37039+SK_IOC IoC, /* IO context handle */\r
37040+int Action, /* GET/PRESET/SET action */\r
37041+SK_U32 Id, /* Object ID that is to be processed */\r
37042+char *pBuf, /* Buffer used for the management data transfer */\r
37043+unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */\r
37044+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */\r
37045+unsigned int TableIndex, /* Index to the Id table */\r
37046+SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */\r
37047+{\r
37048+ int Ret;\r
37049+ SK_U32 ActionOp;\r
37050+\r
37051+ /* Check instance. We only handle single instance variables. */\r
37052+ if (Instance != (SK_U32)(-1) && Instance != 1) {\r
37053+\r
37054+ *pLen = 0;\r
37055+ return (SK_PNMI_ERR_UNKNOWN_INST);\r
37056+ }\r
37057+\r
37058+ if (*pLen < sizeof(SK_U32)) {\r
37059+\r
37060+ *pLen = sizeof(SK_U32);\r
37061+ return (SK_PNMI_ERR_TOO_SHORT);\r
37062+ }\r
37063+\r
37064+ /* Check if a GET should be performed. */\r
37065+ if (Action == SK_PNMI_GET) {\r
37066+\r
37067+ /* A GET is easy. We always return the same value. */\r
37068+ ActionOp = (SK_U32)SK_PNMI_ACT_IDLE;\r
37069+ SK_PNMI_STORE_U32(pBuf, ActionOp);\r
37070+ *pLen = sizeof(SK_U32);\r
37071+\r
37072+ return (SK_PNMI_ERR_OK);\r
37073+ }\r
37074+\r
37075+ /* Continue with PRESET/SET action. */\r
37076+ if (*pLen > sizeof(SK_U32)) {\r
37077+\r
37078+ return (SK_PNMI_ERR_BAD_VALUE);\r
37079+ }\r
37080+\r
37081+ /* Check if the command is a known one. */\r
37082+ SK_PNMI_READ_U32(pBuf, ActionOp);\r
37083+ if (*pLen > sizeof(SK_U32) ||\r
37084+ (ActionOp != SK_PNMI_ACT_IDLE &&\r
37085+ ActionOp != SK_PNMI_ACT_RESET &&\r
37086+ ActionOp != SK_PNMI_ACT_SELFTEST &&\r
37087+ ActionOp != SK_PNMI_ACT_RESETCNT)) {\r
37088+\r
37089+ *pLen = 0;\r
37090+ return (SK_PNMI_ERR_BAD_VALUE);\r
37091+ }\r
37092+\r
37093+ /* A PRESET ends here. */\r
37094+ if (Action == SK_PNMI_PRESET) {\r
37095+\r
37096+ return (SK_PNMI_ERR_OK);\r
37097+ }\r
37098+\r
37099+ switch (ActionOp) {\r
37100+\r
37101+ case SK_PNMI_ACT_IDLE:\r
37102+ /* Nothing to do. */\r
37103+ break;\r
37104+\r
37105+ case SK_PNMI_ACT_RESET:\r
37106+ /* Perform a driver reset or something that comes near to this. */\r
37107+ Ret = SK_DRIVER_RESET(pAC, IoC);\r
37108+ if (Ret != 0) {\r
37109+\r
37110+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR005, SK_PNMI_ERR005MSG);\r
37111+\r
37112+ return (SK_PNMI_ERR_GENERAL);\r
37113+ }\r
37114+ break;\r
37115+\r
37116+ case SK_PNMI_ACT_SELFTEST:\r
37117+ /*\r
37118+ * Perform a driver selftest or something similar to this.\r
37119+ * Currently this feature is not used and will probably\r
37120+ * implemented in another way.\r
37121+ */\r
37122+ Ret = SK_DRIVER_SELFTEST(pAC, IoC);\r
37123+ pAC->Pnmi.TestResult = Ret;\r
37124+ break;\r
37125+\r
37126+ case SK_PNMI_ACT_RESETCNT:\r
37127+ /* Set all counters and timestamps to zero. */\r
37128+ ResetCounter(pAC, IoC, NetIndex);\r
37129+ break;\r
37130+\r
37131+ default:\r
37132+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR006, SK_PNMI_ERR006MSG);\r
37133+\r
37134+ return (SK_PNMI_ERR_GENERAL);\r
37135+ }\r
37136+\r
37137+ return (SK_PNMI_ERR_OK);\r
37138+}\r
37139+\r
37140+/*****************************************************************************\r
37141+ *\r
37142+ * Mac8023Stat - OID handler of OID_GEN_XXX and OID_802_3_XXX\r
37143+ *\r
37144+ * Description:\r
37145+ * Retrieves the statistic values of the virtual port (logical\r
37146+ * index 0). Only special OIDs of NDIS are handled which consist\r
37147+ * of a 32 bit instead of a 64 bit value. The OIDs are public\r
37148+ * because perhaps some other platform can use them too.\r
37149+ *\r
37150+ * Returns:\r
37151+ * SK_PNMI_ERR_OK The request was successfully performed.\r
37152+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.\r
37153+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain\r
37154+ * the correct data (e.g. a 32bit value is\r
37155+ * needed, but a 16 bit value was passed).\r
37156+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't\r
37157+ * exist (e.g. port instance 3 on a two port\r
37158+ * adapter.\r
37159+ */\r
37160+PNMI_STATIC int Mac8023Stat(\r
37161+SK_AC *pAC, /* Pointer to adapter context */\r
37162+SK_IOC IoC, /* IO context handle */\r
37163+int Action, /* GET/PRESET/SET action */\r
37164+SK_U32 Id, /* Object ID that is to be processed */\r
37165+char *pBuf, /* Buffer used for the management data transfer */\r
37166+unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */\r
37167+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */\r
37168+unsigned int TableIndex, /* Index to the Id table */\r
37169+SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */\r
37170+{\r
37171+ int Ret;\r
37172+ SK_U64 StatVal;\r
37173+ SK_U32 StatVal32;\r
37174+ SK_BOOL Is64BitReq = SK_FALSE;\r
37175+\r
37176+ /* Only the active MAC is returned. */\r
37177+ if (Instance != (SK_U32)(-1) && Instance != 1) {\r
37178+\r
37179+ *pLen = 0;\r
37180+ return (SK_PNMI_ERR_UNKNOWN_INST);\r
37181+ }\r
37182+\r
37183+ /* Check action type. */\r
37184+ if (Action != SK_PNMI_GET) {\r
37185+\r
37186+ *pLen = 0;\r
37187+ return (SK_PNMI_ERR_READ_ONLY);\r
37188+ }\r
37189+\r
37190+ /* Check length. */\r
37191+ switch (Id) {\r
37192+\r
37193+ case OID_802_3_PERMANENT_ADDRESS:\r
37194+ case OID_802_3_CURRENT_ADDRESS:\r
37195+ if (*pLen < sizeof(SK_MAC_ADDR)) {\r
37196+\r
37197+ *pLen = sizeof(SK_MAC_ADDR);\r
37198+ return (SK_PNMI_ERR_TOO_SHORT);\r
37199+ }\r
37200+ break;\r
37201+\r
37202+ default:\r
37203+#ifndef SK_NDIS_64BIT_CTR\r
37204+ if (*pLen < sizeof(SK_U32)) {\r
37205+ *pLen = sizeof(SK_U32);\r
37206+ return (SK_PNMI_ERR_TOO_SHORT);\r
37207+ }\r
37208+\r
37209+#else /* SK_NDIS_64BIT_CTR */\r
37210+\r
37211+ /* For compatibility, at least 32 bits are required for OID. */\r
37212+ if (*pLen < sizeof(SK_U32)) {\r
37213+ /*\r
37214+ * Indicate handling for 64 bit values,\r
37215+ * if insufficient space is provided.\r
37216+ */\r
37217+ *pLen = sizeof(SK_U64);\r
37218+ return (SK_PNMI_ERR_TOO_SHORT);\r
37219+ }\r
37220+\r
37221+ Is64BitReq = (*pLen < sizeof(SK_U64)) ? SK_FALSE : SK_TRUE;\r
37222+#endif /* SK_NDIS_64BIT_CTR */\r
37223+ break;\r
37224+ }\r
37225+\r
37226+ /*\r
37227+ * Update all statistics, because we retrieve virtual MAC, which\r
37228+ * consists of multiple physical statistics and increment semaphore\r
37229+ * to indicate that an update was already done.\r
37230+ */\r
37231+ Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1);\r
37232+ if (Ret != SK_PNMI_ERR_OK) {\r
37233+\r
37234+ *pLen = 0;\r
37235+ return (Ret);\r
37236+ }\r
37237+ pAC->Pnmi.MacUpdatedFlag ++;\r
37238+\r
37239+ /* Get value (MAC index 0 identifies the virtual MAC). */\r
37240+ switch (Id) {\r
37241+\r
37242+ case OID_802_3_PERMANENT_ADDRESS:\r
37243+ CopyMac(pBuf, &pAC->Addr.Net[NetIndex].PermanentMacAddress);\r
37244+ *pLen = sizeof(SK_MAC_ADDR);\r
37245+ break;\r
37246+\r
37247+ case OID_802_3_CURRENT_ADDRESS:\r
37248+ CopyMac(pBuf, &pAC->Addr.Net[NetIndex].CurrentMacAddress);\r
37249+ *pLen = sizeof(SK_MAC_ADDR);\r
37250+ break;\r
37251+\r
37252+ default:\r
37253+ StatVal = GetStatVal(pAC, IoC, 0, IdTable[TableIndex].Param, NetIndex);\r
37254+\r
37255+ /* By default 32 bit values are evaluated. */\r
37256+ if (!Is64BitReq) {\r
37257+ StatVal32 = (SK_U32)StatVal;\r
37258+ SK_PNMI_STORE_U32(pBuf, StatVal32);\r
37259+ *pLen = sizeof(SK_U32);\r
37260+ }\r
37261+ else {\r
37262+ SK_PNMI_STORE_U64(pBuf, StatVal);\r
37263+ *pLen = sizeof(SK_U64);\r
37264+ }\r
37265+ break;\r
37266+ }\r
37267+\r
37268+ pAC->Pnmi.MacUpdatedFlag --;\r
37269+\r
37270+ return (SK_PNMI_ERR_OK);\r
37271+}\r
37272+\r
37273+/*****************************************************************************\r
37274+ *\r
37275+ * MacPrivateStat - OID handler function of OID_SKGE_STAT_XXX\r
37276+ *\r
37277+ * Description:\r
37278+ * Retrieves the MAC statistic data.\r
37279+ *\r
37280+ * Returns:\r
37281+ * SK_PNMI_ERR_OK The request was successfully performed.\r
37282+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.\r
37283+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain\r
37284+ * the correct data (e.g. a 32bit value is\r
37285+ * needed, but a 16 bit value was passed).\r
37286+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't\r
37287+ * exist (e.g. port instance 3 on a two port\r
37288+ * adapter.\r
37289+ */\r
37290+PNMI_STATIC int MacPrivateStat(\r
37291+SK_AC *pAC, /* Pointer to adapter context */\r
37292+SK_IOC IoC, /* IO context handle */\r
37293+int Action, /* GET/PRESET/SET action */\r
37294+SK_U32 Id, /* Object ID that is to be processed */\r
37295+char *pBuf, /* Buffer used for the management data transfer */\r
37296+unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */\r
37297+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */\r
37298+unsigned int TableIndex, /* Index to the Id table */\r
37299+SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */\r
37300+{\r
37301+ unsigned int LogPortMax;\r
37302+ unsigned int LogPortIndex;\r
37303+ unsigned int PhysPortMax;\r
37304+ unsigned int Limit;\r
37305+ unsigned int Offset;\r
37306+ int MacType;\r
37307+ int Ret;\r
37308+ SK_U64 StatVal;\r
37309+\r
37310+ /* Calculate instance if wished. MAC index 0 is the virtual MAC. */\r
37311+ PhysPortMax = pAC->GIni.GIMacsFound;\r
37312+ LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax);\r
37313+ \r
37314+ MacType = pAC->GIni.GIMacType;\r
37315+\r
37316+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* DualNet mode. */\r
37317+ LogPortMax--;\r
37318+ }\r
37319+\r
37320+ if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried. */\r
37321+ /* Check instance range. */\r
37322+ if ((Instance < 1) || (Instance > LogPortMax)) {\r
37323+\r
37324+ *pLen = 0;\r
37325+ return (SK_PNMI_ERR_UNKNOWN_INST);\r
37326+ }\r
37327+ LogPortIndex = SK_PNMI_PORT_INST2LOG(Instance);\r
37328+ Limit = LogPortIndex + 1;\r
37329+ }\r
37330+\r
37331+ else { /* Instance == (SK_U32)(-1), get all Instances of that OID. */\r
37332+\r
37333+ LogPortIndex = 0;\r
37334+ Limit = LogPortMax;\r
37335+ }\r
37336+\r
37337+ /* Check action. */\r
37338+ if (Action != SK_PNMI_GET) {\r
37339+\r
37340+ *pLen = 0;\r
37341+ return (SK_PNMI_ERR_READ_ONLY);\r
37342+ }\r
37343+\r
37344+ /* Check length. */\r
37345+ if (*pLen < (Limit - LogPortIndex) * sizeof(SK_U64)) {\r
37346+\r
37347+ *pLen = (Limit - LogPortIndex) * sizeof(SK_U64);\r
37348+ return (SK_PNMI_ERR_TOO_SHORT);\r
37349+ }\r
37350+\r
37351+ /*\r
37352+ * Update MAC statistic and increment semaphore to indicate that\r
37353+ * an update was already done.\r
37354+ */\r
37355+ Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1);\r
37356+ if (Ret != SK_PNMI_ERR_OK) {\r
37357+\r
37358+ *pLen = 0;\r
37359+ return (Ret);\r
37360+ }\r
37361+ pAC->Pnmi.MacUpdatedFlag ++;\r
37362+\r
37363+ /* Get value. */\r
37364+ Offset = 0;\r
37365+ for (; LogPortIndex < Limit; LogPortIndex ++) {\r
37366+\r
37367+ switch (Id) {\r
37368+\r
37369+/* XXX not yet implemented due to XMAC problems\r
37370+ case OID_SKGE_STAT_TX_UTIL:\r
37371+ return (SK_PNMI_ERR_GENERAL);\r
37372+*/\r
37373+/* XXX not yet implemented due to XMAC problems\r
37374+ case OID_SKGE_STAT_RX_UTIL:\r
37375+ return (SK_PNMI_ERR_GENERAL);\r
37376+*/\r
37377+ case OID_SKGE_STAT_RX:\r
37378+ if (MacType == SK_MAC_GMAC) {\r
37379+ StatVal =\r
37380+ GetStatVal(pAC, IoC, LogPortIndex,\r
37381+ SK_PNMI_HRX_BROADCAST, NetIndex) +\r
37382+ GetStatVal(pAC, IoC, LogPortIndex,\r
37383+ SK_PNMI_HRX_MULTICAST, NetIndex) +\r
37384+ GetStatVal(pAC, IoC, LogPortIndex,\r
37385+ SK_PNMI_HRX_UNICAST, NetIndex) +\r
37386+ GetStatVal(pAC, IoC, LogPortIndex,\r
37387+ SK_PNMI_HRX_UNDERSIZE, NetIndex);\r
37388+ }\r
37389+ else {\r
37390+ StatVal = GetStatVal(pAC, IoC, LogPortIndex,\r
37391+ IdTable[TableIndex].Param, NetIndex);\r
37392+ }\r
37393+ break;\r
37394+\r
37395+ case OID_SKGE_STAT_TX:\r
37396+ if (MacType == SK_MAC_GMAC) {\r
37397+ StatVal =\r
37398+ GetStatVal(pAC, IoC, LogPortIndex,\r
37399+ SK_PNMI_HTX_BROADCAST, NetIndex) +\r
37400+ GetStatVal(pAC, IoC, LogPortIndex,\r
37401+ SK_PNMI_HTX_MULTICAST, NetIndex) +\r
37402+ GetStatVal(pAC, IoC, LogPortIndex,\r
37403+ SK_PNMI_HTX_UNICAST, NetIndex);\r
37404+ }\r
37405+ else {\r
37406+ StatVal = GetStatVal(pAC, IoC, LogPortIndex,\r
37407+ IdTable[TableIndex].Param, NetIndex);\r
37408+ }\r
37409+ break;\r
37410+\r
37411+ default:\r
37412+ StatVal = GetStatVal(pAC, IoC, LogPortIndex,\r
37413+ IdTable[TableIndex].Param, NetIndex);\r
37414+ }\r
37415+ SK_PNMI_STORE_U64(pBuf + Offset, StatVal);\r
37416+\r
37417+ Offset += sizeof(SK_U64);\r
37418+ }\r
37419+ *pLen = Offset;\r
37420+\r
37421+ pAC->Pnmi.MacUpdatedFlag --;\r
37422+\r
37423+ return (SK_PNMI_ERR_OK);\r
37424+}\r
37425+\r
37426+/*****************************************************************************\r
37427+ *\r
37428+ * Addr - OID handler function of OID_SKGE_PHYS_CUR_ADDR and _FAC_ADDR\r
37429+ *\r
37430+ * Description:\r
37431+ * Get/Presets/Sets the current and factory MAC address. The MAC\r
37432+ * address of the virtual port, which is reported to the OS, may\r
37433+ * not be changed, but the physical ones. A set to the virtual port\r
37434+ * will be ignored. No error should be reported because otherwise\r
37435+ * a multiple instance set (-1) would always fail.\r
37436+ *\r
37437+ * Returns:\r
37438+ * SK_PNMI_ERR_OK The request was successfully performed.\r
37439+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.\r
37440+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain\r
37441+ * the correct data (e.g. a 32bit value is\r
37442+ * needed, but a 16 bit value was passed).\r
37443+ * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid\r
37444+ * value range.\r
37445+ * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set.\r
37446+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't\r
37447+ * exist (e.g. port instance 3 on a two port\r
37448+ * adapter.\r
37449+ */\r
37450+PNMI_STATIC int Addr(\r
37451+SK_AC *pAC, /* Pointer to adapter context */\r
37452+SK_IOC IoC, /* IO context handle */\r
37453+int Action, /* GET/PRESET/SET action */\r
37454+SK_U32 Id, /* Object ID that is to be processed */\r
37455+char *pBuf, /* Buffer used for the management data transfer */\r
37456+unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */\r
37457+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */\r
37458+unsigned int TableIndex, /* Index to the Id table */\r
37459+SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */\r
37460+{\r
37461+ int Ret;\r
37462+ unsigned int LogPortMax;\r
37463+ unsigned int PhysPortMax;\r
37464+ unsigned int LogPortIndex;\r
37465+ unsigned int PhysPortIndex;\r
37466+ unsigned int Limit;\r
37467+ unsigned int Offset = 0;\r
37468+\r
37469+ /* Calculate instance if wished. MAC index 0 is the virtual MAC. */\r
37470+ PhysPortMax = pAC->GIni.GIMacsFound;\r
37471+ LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax);\r
37472+\r
37473+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* DualNet mode. */\r
37474+ LogPortMax--;\r
37475+ }\r
37476+\r
37477+ if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried. */\r
37478+ /* Check instance range. */\r
37479+ if ((Instance < 1) || (Instance > LogPortMax)) {\r
37480+\r
37481+ *pLen = 0;\r
37482+ return (SK_PNMI_ERR_UNKNOWN_INST);\r
37483+ }\r
37484+ LogPortIndex = SK_PNMI_PORT_INST2LOG(Instance);\r
37485+ Limit = LogPortIndex + 1;\r
37486+ }\r
37487+ else { /* Instance == (SK_U32)(-1), get all Instances of that OID. */\r
37488+\r
37489+ LogPortIndex = 0;\r
37490+ Limit = LogPortMax;\r
37491+ }\r
37492+\r
37493+ /* Perform action. */\r
37494+ if (Action == SK_PNMI_GET) {\r
37495+\r
37496+ /* Check length. */\r
37497+ if (*pLen < (Limit - LogPortIndex) * 6) {\r
37498+\r
37499+ *pLen = (Limit - LogPortIndex) * 6;\r
37500+ return (SK_PNMI_ERR_TOO_SHORT);\r
37501+ }\r
37502+\r
37503+ /* Get value. */\r
37504+ for (; LogPortIndex < Limit; LogPortIndex ++) {\r
37505+\r
37506+ switch (Id) {\r
37507+\r
37508+ case OID_SKGE_PHYS_CUR_ADDR:\r
37509+ if (LogPortIndex == 0) {\r
37510+ CopyMac(pBuf + Offset, &pAC->Addr.Net[NetIndex].CurrentMacAddress);\r
37511+ }\r
37512+ else {\r
37513+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);\r
37514+\r
37515+ CopyMac(pBuf + Offset,\r
37516+ &pAC->Addr.Port[PhysPortIndex].CurrentMacAddress);\r
37517+ }\r
37518+ Offset += 6;\r
37519+ break;\r
37520+\r
37521+ case OID_SKGE_PHYS_FAC_ADDR:\r
37522+ if (LogPortIndex == 0) {\r
37523+ CopyMac(pBuf + Offset,\r
37524+ &pAC->Addr.Net[NetIndex].PermanentMacAddress);\r
37525+ }\r
37526+ else {\r
37527+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);\r
37528+\r
37529+ CopyMac(pBuf + Offset,\r
37530+ &pAC->Addr.Port[PhysPortIndex].PermanentMacAddress);\r
37531+ }\r
37532+ Offset += 6;\r
37533+ break;\r
37534+\r
37535+ default:\r
37536+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR008, SK_PNMI_ERR008MSG);\r
37537+\r
37538+ *pLen = 0;\r
37539+ return (SK_PNMI_ERR_GENERAL);\r
37540+ }\r
37541+ }\r
37542+\r
37543+ *pLen = Offset;\r
37544+ }\r
37545+ else {\r
37546+ /*\r
37547+ * The logical MAC address may not be changed,\r
37548+ * only the physical ones.\r
37549+ */\r
37550+ if (Id == OID_SKGE_PHYS_FAC_ADDR) {\r
37551+\r
37552+ *pLen = 0;\r
37553+ return (SK_PNMI_ERR_READ_ONLY);\r
37554+ }\r
37555+\r
37556+ /* Only the current address may be changed. */\r
37557+ if (Id != OID_SKGE_PHYS_CUR_ADDR) {\r
37558+\r
37559+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR009, SK_PNMI_ERR009MSG);\r
37560+\r
37561+ *pLen = 0;\r
37562+ return (SK_PNMI_ERR_GENERAL);\r
37563+ }\r
37564+\r
37565+ /* Check length. */\r
37566+ if (*pLen < (Limit - LogPortIndex) * 6) {\r
37567+\r
37568+ *pLen = (Limit - LogPortIndex) * 6;\r
37569+ return (SK_PNMI_ERR_TOO_SHORT);\r
37570+ }\r
37571+ if (*pLen > (Limit - LogPortIndex) * 6) {\r
37572+\r
37573+ *pLen = 0;\r
37574+ return (SK_PNMI_ERR_BAD_VALUE);\r
37575+ }\r
37576+\r
37577+ /* Check action. */\r
37578+ if (Action == SK_PNMI_PRESET) {\r
37579+\r
37580+ *pLen = 0;\r
37581+ return (SK_PNMI_ERR_OK);\r
37582+ }\r
37583+\r
37584+ /* Set OID_SKGE_MAC_CUR_ADDR. */\r
37585+ for (; LogPortIndex < Limit; LogPortIndex ++, Offset += 6) {\r
37586+\r
37587+ /*\r
37588+ * A set to virtual port and set of broadcast\r
37589+ * address will be ignored.\r
37590+ */\r
37591+ if (LogPortIndex == 0 || SK_MEMCMP(pBuf + Offset,\r
37592+ "\xff\xff\xff\xff\xff\xff", 6) == 0) {\r
37593+ continue;\r
37594+ }\r
37595+\r
37596+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);\r
37597+\r
37598+ Ret = SkAddrOverride(pAC, IoC, PhysPortIndex,\r
37599+ (SK_MAC_ADDR *)(pBuf + Offset),\r
37600+ (LogPortIndex == 0 ? SK_ADDR_VIRTUAL_ADDRESS :\r
37601+ SK_ADDR_PHYSICAL_ADDRESS));\r
37602+ if (Ret != SK_ADDR_OVERRIDE_SUCCESS) {\r
37603+\r
37604+ return (SK_PNMI_ERR_GENERAL);\r
37605+ }\r
37606+ }\r
37607+ *pLen = Offset;\r
37608+ }\r
37609+\r
37610+ return (SK_PNMI_ERR_OK);\r
37611+}\r
37612+\r
37613+/*****************************************************************************\r
37614+ *\r
37615+ * CsumStat - OID handler function of OID_SKGE_CHKSM_XXX\r
37616+ *\r
37617+ * Description:\r
37618+ * Retrieves the statistic values of the CSUM module. The CSUM data\r
37619+ * structure must be available in the SK_AC even if the CSUM module\r
37620+ * is not included, because PNMI reads the statistic data from the\r
37621+ * CSUM part of SK_AC directly.\r
37622+ *\r
37623+ * Returns:\r
37624+ * SK_PNMI_ERR_OK The request was successfully performed.\r
37625+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.\r
37626+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain\r
37627+ * the correct data (e.g. a 32bit value is\r
37628+ * needed, but a 16 bit value was passed).\r
37629+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't\r
37630+ * exist (e.g. port instance 3 on a two port\r
37631+ * adapter.\r
37632+ */\r
37633+PNMI_STATIC int CsumStat(\r
37634+SK_AC *pAC, /* Pointer to adapter context */\r
37635+SK_IOC IoC, /* IO context handle */\r
37636+int Action, /* GET/PRESET/SET action */\r
37637+SK_U32 Id, /* Object ID that is to be processed */\r
37638+char *pBuf, /* Buffer used for the management data transfer */\r
37639+unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */\r
37640+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */\r
37641+unsigned int TableIndex, /* Index to the Id table */\r
37642+SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */\r
37643+{\r
37644+ unsigned int Index;\r
37645+ unsigned int Limit;\r
37646+ unsigned int Offset = 0;\r
37647+ SK_U64 StatVal;\r
37648+\r
37649+ /* Calculate instance if wished. */\r
37650+ if (Instance != (SK_U32)(-1)) {\r
37651+\r
37652+ if ((Instance < 1) || (Instance > SKCS_NUM_PROTOCOLS)) {\r
37653+\r
37654+ *pLen = 0;\r
37655+ return (SK_PNMI_ERR_UNKNOWN_INST);\r
37656+ }\r
37657+ Index = (unsigned int)Instance - 1;\r
37658+ Limit = Index + 1;\r
37659+ }\r
37660+ else {\r
37661+ Index = 0;\r
37662+ Limit = SKCS_NUM_PROTOCOLS;\r
37663+ }\r
37664+\r
37665+ /* Check action. */\r
37666+ if (Action != SK_PNMI_GET) {\r
37667+\r
37668+ *pLen = 0;\r
37669+ return (SK_PNMI_ERR_READ_ONLY);\r
37670+ }\r
37671+\r
37672+ /* Check length. */\r
37673+ if (*pLen < (Limit - Index) * sizeof(SK_U64)) {\r
37674+\r
37675+ *pLen = (Limit - Index) * sizeof(SK_U64);\r
37676+ return (SK_PNMI_ERR_TOO_SHORT);\r
37677+ }\r
37678+\r
37679+ /* Get value. */\r
37680+ for (; Index < Limit; Index ++) {\r
37681+\r
37682+ switch (Id) {\r
37683+\r
37684+ case OID_SKGE_CHKSM_RX_OK_CTS:\r
37685+ StatVal = pAC->Csum.ProtoStats[NetIndex][Index].RxOkCts;\r
37686+ break;\r
37687+\r
37688+ case OID_SKGE_CHKSM_RX_UNABLE_CTS:\r
37689+ StatVal = pAC->Csum.ProtoStats[NetIndex][Index].RxUnableCts;\r
37690+ break;\r
37691+\r
37692+ case OID_SKGE_CHKSM_RX_ERR_CTS:\r
37693+ StatVal = pAC->Csum.ProtoStats[NetIndex][Index].RxErrCts;\r
37694+ break;\r
37695+\r
37696+ case OID_SKGE_CHKSM_TX_OK_CTS:\r
37697+ StatVal = pAC->Csum.ProtoStats[NetIndex][Index].TxOkCts;\r
37698+ break;\r
37699+\r
37700+ case OID_SKGE_CHKSM_TX_UNABLE_CTS:\r
37701+ StatVal = pAC->Csum.ProtoStats[NetIndex][Index].TxUnableCts;\r
37702+ break;\r
37703+\r
37704+ default:\r
37705+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR010, SK_PNMI_ERR010MSG);\r
37706+\r
37707+ *pLen = 0;\r
37708+ return (SK_PNMI_ERR_GENERAL);\r
37709+ }\r
37710+\r
37711+ SK_PNMI_STORE_U64(pBuf + Offset, StatVal);\r
37712+ Offset += sizeof(SK_U64);\r
37713+ }\r
37714+\r
37715+ /* Store used buffer space. */\r
37716+ *pLen = Offset;\r
37717+\r
37718+ return (SK_PNMI_ERR_OK);\r
37719+}\r
37720+\r
37721+/*****************************************************************************\r
37722+ *\r
37723+ * SensorStat - OID handler function of OID_SKGE_SENSOR_XXX\r
37724+ *\r
37725+ * Description:\r
37726+ * Retrieves the statistic values of the I2C module, which handles\r
37727+ * the temperature and voltage sensors.\r
37728+ *\r
37729+ * Returns:\r
37730+ * SK_PNMI_ERR_OK The request was successfully performed.\r
37731+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.\r
37732+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain\r
37733+ * the correct data (e.g. a 32bit value is\r
37734+ * needed, but a 16 bit value was passed).\r
37735+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't\r
37736+ * exist (e.g. port instance 3 on a two port\r
37737+ * adapter.\r
37738+ */\r
37739+PNMI_STATIC int SensorStat(\r
37740+SK_AC *pAC, /* Pointer to adapter context */\r
37741+SK_IOC IoC, /* IO context handle */\r
37742+int Action, /* GET/PRESET/SET action */\r
37743+SK_U32 Id, /* Object ID that is to be processed */\r
37744+char *pBuf, /* Buffer used for the management data transfer */\r
37745+unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */\r
37746+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */\r
37747+unsigned int TableIndex, /* Index to the Id table */\r
37748+SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */\r
37749+{\r
37750+ unsigned int i;\r
37751+ unsigned int Index;\r
37752+ unsigned int Limit;\r
37753+ unsigned int Offset;\r
37754+ unsigned int Len;\r
37755+ SK_U32 Val32;\r
37756+ SK_U64 Val64;\r
37757+\r
37758+ /* Calculate instance if wished. */\r
37759+ if ((Instance != (SK_U32)(-1))) {\r
37760+\r
37761+ if ((Instance < 1) || (Instance > (SK_U32)pAC->I2c.MaxSens)) {\r
37762+\r
37763+ *pLen = 0;\r
37764+ return (SK_PNMI_ERR_UNKNOWN_INST);\r
37765+ }\r
37766+\r
37767+ Index = (unsigned int)Instance -1;\r
37768+ Limit = (unsigned int)Instance;\r
37769+ }\r
37770+ else {\r
37771+ Index = 0;\r
37772+ Limit = (unsigned int) pAC->I2c.MaxSens;\r
37773+ }\r
37774+\r
37775+ /* Check action. */\r
37776+ if (Action != SK_PNMI_GET) {\r
37777+\r
37778+ *pLen = 0;\r
37779+ return (SK_PNMI_ERR_READ_ONLY);\r
37780+ }\r
37781+\r
37782+ /* Check length. */\r
37783+ switch (Id) {\r
37784+\r
37785+ case OID_SKGE_SENSOR_VALUE:\r
37786+ case OID_SKGE_SENSOR_WAR_THRES_LOW:\r
37787+ case OID_SKGE_SENSOR_WAR_THRES_UPP:\r
37788+ case OID_SKGE_SENSOR_ERR_THRES_LOW:\r
37789+ case OID_SKGE_SENSOR_ERR_THRES_UPP:\r
37790+ if (*pLen < (Limit - Index) * sizeof(SK_U32)) {\r
37791+\r
37792+ *pLen = (Limit - Index) * sizeof(SK_U32);\r
37793+ return (SK_PNMI_ERR_TOO_SHORT);\r
37794+ }\r
37795+ break;\r
37796+\r
37797+ case OID_SKGE_SENSOR_DESCR:\r
37798+ for (Offset = 0, i = Index; i < Limit; i ++) {\r
37799+\r
37800+ Len = (unsigned int)\r
37801+ SK_STRLEN(pAC->I2c.SenTable[i].SenDesc) + 1;\r
37802+ if (Len >= SK_PNMI_STRINGLEN2) {\r
37803+\r
37804+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR011,\r
37805+ SK_PNMI_ERR011MSG);\r
37806+\r
37807+ *pLen = 0;\r
37808+ return (SK_PNMI_ERR_GENERAL);\r
37809+ }\r
37810+ Offset += Len;\r
37811+ }\r
37812+ if (*pLen < Offset) {\r
37813+\r
37814+ *pLen = Offset;\r
37815+ return (SK_PNMI_ERR_TOO_SHORT);\r
37816+ }\r
37817+ break;\r
37818+\r
37819+ case OID_SKGE_SENSOR_INDEX:\r
37820+ case OID_SKGE_SENSOR_TYPE:\r
37821+ case OID_SKGE_SENSOR_STATUS:\r
37822+ if (*pLen < Limit - Index) {\r
37823+\r
37824+ *pLen = Limit - Index;\r
37825+ return (SK_PNMI_ERR_TOO_SHORT);\r
37826+ }\r
37827+ break;\r
37828+\r
37829+ case OID_SKGE_SENSOR_WAR_CTS:\r
37830+ case OID_SKGE_SENSOR_WAR_TIME:\r
37831+ case OID_SKGE_SENSOR_ERR_CTS:\r
37832+ case OID_SKGE_SENSOR_ERR_TIME:\r
37833+ if (*pLen < (Limit - Index) * sizeof(SK_U64)) {\r
37834+\r
37835+ *pLen = (Limit - Index) * sizeof(SK_U64);\r
37836+ return (SK_PNMI_ERR_TOO_SHORT);\r
37837+ }\r
37838+ break;\r
37839+\r
37840+ default:\r
37841+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR012, SK_PNMI_ERR012MSG);\r
37842+\r
37843+ *pLen = 0;\r
37844+ return (SK_PNMI_ERR_GENERAL);\r
37845+\r
37846+ }\r
37847+\r
37848+ /* Get value. */\r
37849+ for (Offset = 0; Index < Limit; Index ++) {\r
37850+\r
37851+ switch (Id) {\r
37852+\r
37853+ case OID_SKGE_SENSOR_INDEX:\r
37854+ *(pBuf + Offset) = (char)Index;\r
37855+ Offset ++;\r
37856+ break;\r
37857+\r
37858+ case OID_SKGE_SENSOR_DESCR:\r
37859+ Len = SK_STRLEN(pAC->I2c.SenTable[Index].SenDesc);\r
37860+ SK_MEMCPY(pBuf + Offset + 1, pAC->I2c.SenTable[Index].SenDesc, Len);\r
37861+ *(pBuf + Offset) = (char)Len;\r
37862+ Offset += Len + 1;\r
37863+ break;\r
37864+\r
37865+ case OID_SKGE_SENSOR_TYPE:\r
37866+ *(pBuf + Offset) = (char)pAC->I2c.SenTable[Index].SenType;\r
37867+ Offset ++;\r
37868+ break;\r
37869+\r
37870+ case OID_SKGE_SENSOR_VALUE:\r
37871+ Val32 = (SK_U32)pAC->I2c.SenTable[Index].SenValue;\r
37872+ SK_PNMI_STORE_U32(pBuf + Offset, Val32);\r
37873+ Offset += sizeof(SK_U32);\r
37874+ break;\r
37875+\r
37876+ case OID_SKGE_SENSOR_WAR_THRES_LOW:\r
37877+ Val32 = (SK_U32)pAC->I2c.SenTable[Index].\r
37878+ SenThreWarnLow;\r
37879+ SK_PNMI_STORE_U32(pBuf + Offset, Val32);\r
37880+ Offset += sizeof(SK_U32);\r
37881+ break;\r
37882+\r
37883+ case OID_SKGE_SENSOR_WAR_THRES_UPP:\r
37884+ Val32 = (SK_U32)pAC->I2c.SenTable[Index].\r
37885+ SenThreWarnHigh;\r
37886+ SK_PNMI_STORE_U32(pBuf + Offset, Val32);\r
37887+ Offset += sizeof(SK_U32);\r
37888+ break;\r
37889+\r
37890+ case OID_SKGE_SENSOR_ERR_THRES_LOW:\r
37891+ Val32 = (SK_U32)pAC->I2c.SenTable[Index].\r
37892+ SenThreErrLow;\r
37893+ SK_PNMI_STORE_U32(pBuf + Offset, Val32);\r
37894+ Offset += sizeof(SK_U32);\r
37895+ break;\r
37896+\r
37897+ case OID_SKGE_SENSOR_ERR_THRES_UPP:\r
37898+ Val32 = pAC->I2c.SenTable[Index].SenThreErrHigh;\r
37899+ SK_PNMI_STORE_U32(pBuf + Offset, Val32);\r
37900+ Offset += sizeof(SK_U32);\r
37901+ break;\r
37902+\r
37903+ case OID_SKGE_SENSOR_STATUS:\r
37904+ *(pBuf + Offset) = (char)pAC->I2c.SenTable[Index].SenErrFlag;\r
37905+ Offset ++;\r
37906+ break;\r
37907+\r
37908+ case OID_SKGE_SENSOR_WAR_CTS:\r
37909+ Val64 = pAC->I2c.SenTable[Index].SenWarnCts;\r
37910+ SK_PNMI_STORE_U64(pBuf + Offset, Val64);\r
37911+ Offset += sizeof(SK_U64);\r
37912+ break;\r
37913+\r
37914+ case OID_SKGE_SENSOR_ERR_CTS:\r
37915+ Val64 = pAC->I2c.SenTable[Index].SenErrCts;\r
37916+ SK_PNMI_STORE_U64(pBuf + Offset, Val64);\r
37917+ Offset += sizeof(SK_U64);\r
37918+ break;\r
37919+\r
37920+ case OID_SKGE_SENSOR_WAR_TIME:\r
37921+ Val64 = SK_PNMI_HUNDREDS_SEC(pAC->I2c.SenTable[Index].\r
37922+ SenBegWarnTS);\r
37923+ SK_PNMI_STORE_U64(pBuf + Offset, Val64);\r
37924+ Offset += sizeof(SK_U64);\r
37925+ break;\r
37926+\r
37927+ case OID_SKGE_SENSOR_ERR_TIME:\r
37928+ Val64 = SK_PNMI_HUNDREDS_SEC(pAC->I2c.SenTable[Index].\r
37929+ SenBegErrTS);\r
37930+ SK_PNMI_STORE_U64(pBuf + Offset, Val64);\r
37931+ Offset += sizeof(SK_U64);\r
37932+ break;\r
37933+\r
37934+ default:\r
37935+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR,\r
37936+ ("SensorStat: Unknown OID should be handled before"));\r
37937+\r
37938+ return (SK_PNMI_ERR_GENERAL);\r
37939+ }\r
37940+ }\r
37941+\r
37942+ /* Store used buffer space. */\r
37943+ *pLen = Offset;\r
37944+\r
37945+ return (SK_PNMI_ERR_OK);\r
37946+}\r
37947+\r
37948+/*****************************************************************************\r
37949+ *\r
37950+ * Vpd - OID handler function of OID_SKGE_VPD_XXX\r
37951+ *\r
37952+ * Description:\r
37953+ * Get/preset/set of VPD data. As instance the name of a VPD key\r
37954+ * can be passed. The Instance parameter is a SK_U32 and can be\r
37955+ * used as a string buffer for the VPD key, because their maximum\r
37956+ * length is 4 byte.\r
37957+ *\r
37958+ * Returns:\r
37959+ * SK_PNMI_ERR_OK The request was successfully performed.\r
37960+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.\r
37961+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain\r
37962+ * the correct data (e.g. a 32bit value is\r
37963+ * needed, but a 16 bit value was passed).\r
37964+ * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid\r
37965+ * value range.\r
37966+ * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set.\r
37967+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't\r
37968+ * exist (e.g. port instance 3 on a two port\r
37969+ * adapter.\r
37970+ */\r
37971+PNMI_STATIC int Vpd(\r
37972+SK_AC *pAC, /* Pointer to adapter context */\r
37973+SK_IOC IoC, /* IO context handle */\r
37974+int Action, /* GET/PRESET/SET action */\r
37975+SK_U32 Id, /* Object ID that is to be processed */\r
37976+char *pBuf, /* Buffer used for the management data transfer */\r
37977+unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */\r
37978+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */\r
37979+unsigned int TableIndex, /* Index to the Id table */\r
37980+SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */\r
37981+{\r
37982+ SK_VPD_STATUS *pVpdStatus;\r
37983+ unsigned int BufLen;\r
37984+ char Buf[256];\r
37985+ char KeyArr[SK_PNMI_VPD_ENTRIES][SK_PNMI_VPD_KEY_SIZE];\r
37986+ char KeyStr[SK_PNMI_VPD_KEY_SIZE];\r
37987+ unsigned int KeyNo;\r
37988+ unsigned int Offset;\r
37989+ unsigned int Index;\r
37990+ unsigned int FirstIndex;\r
37991+ unsigned int LastIndex;\r
37992+ unsigned int Len;\r
37993+ int Ret;\r
37994+ SK_U32 Val32;\r
37995+\r
37996+ /*\r
37997+ * VpdKeyReadError will be set in GetVpdKeyArr() if an error occurs.\r
37998+ * Due to the fact that some drivers use SkPnmiGetStruct() to retrieve\r
37999+ * all statistical data, an error in GetVpdKeyArr() will generate a PNMI\r
38000+ * error and terminate SkPnmiGetStruct() without filling in statistical\r
38001+ * data into the PNMI struct. In this case the driver will get no values\r
38002+ * for statistical purposes (netstat, ifconfig etc.). GetVpdKeyArr() is\r
38003+ * the first function to be called in SkPnmiGetStruct(), so any error\r
38004+ * will terminate SkPnmiGetStruct() immediately. Hence, VpdKeyReadError will\r
38005+ * be set during the first call to GetVpdKeyArr() to make successful calls\r
38006+ * to SkPnmiGetStruct() possible. But there is another point to consider: \r
38007+ * When filling in the statistical data into the PNMI struct, the VPD\r
38008+ * handler Vpd() will also be called. If GetVpdKeyArr() in Vpd() would\r
38009+ * return with SK_PNMI_ERR_GENERAL, SkPnmiGetStruct() would fail again.\r
38010+ * For this reason VpdKeyReadError is checked here and, if set, Vpd()\r
38011+ * will return without doing anything and the return value SK_PNMI_ERR_OK.\r
38012+ * Therefore SkPnmiGetStruct() is able to continue and fill in all other\r
38013+ * statistical data. \r
38014+ */ \r
38015+ if (pAC->Pnmi.VpdKeyReadError == SK_TRUE) {\r
38016+ return (SK_PNMI_ERR_OK);\r
38017+ }\r
38018+\r
38019+ /* Get array of all currently stored VPD keys. */\r
38020+ Ret = GetVpdKeyArr(pAC, IoC, &KeyArr[0][0], sizeof(KeyArr), &KeyNo);\r
38021+ if (Ret != SK_PNMI_ERR_OK) {\r
38022+ *pLen = 0;\r
38023+ return (Ret);\r
38024+ }\r
38025+\r
38026+ /*\r
38027+ * If instance is not -1, try to find the requested VPD key for\r
38028+ * the multiple instance variables. The other OIDs as for example\r
38029+ * OID VPD_ACTION are single instance variables and must be\r
38030+ * handled separatly.\r
38031+ */\r
38032+ FirstIndex = 0;\r
38033+ LastIndex = KeyNo;\r
38034+\r
38035+ if ((Instance != (SK_U32)(-1))) {\r
38036+\r
38037+ if (Id == OID_SKGE_VPD_KEY || Id == OID_SKGE_VPD_VALUE ||\r
38038+ Id == OID_SKGE_VPD_ACCESS) {\r
38039+\r
38040+ SK_STRNCPY(KeyStr, (char *)&Instance, 4);\r
38041+ KeyStr[4] = 0;\r
38042+\r
38043+ for (Index = 0; Index < KeyNo; Index ++) {\r
38044+\r
38045+ if (SK_STRCMP(KeyStr, KeyArr[Index]) == 0) {\r
38046+ FirstIndex = Index;\r
38047+ LastIndex = Index+1;\r
38048+ break;\r
38049+ }\r
38050+ }\r
38051+ if (Index == KeyNo) {\r
38052+\r
38053+ *pLen = 0;\r
38054+ return (SK_PNMI_ERR_UNKNOWN_INST);\r
38055+ }\r
38056+ }\r
38057+ else if (Instance != 1) {\r
38058+\r
38059+ *pLen = 0;\r
38060+ return (SK_PNMI_ERR_UNKNOWN_INST);\r
38061+ }\r
38062+ }\r
38063+\r
38064+ /* Get value, if a query should be performed. */\r
38065+ if (Action == SK_PNMI_GET) {\r
38066+\r
38067+ switch (Id) {\r
38068+\r
38069+ case OID_SKGE_VPD_FREE_BYTES:\r
38070+ /* Check length of buffer. */\r
38071+ if (*pLen < sizeof(SK_U32)) {\r
38072+\r
38073+ *pLen = sizeof(SK_U32);\r
38074+ return (SK_PNMI_ERR_TOO_SHORT);\r
38075+ }\r
38076+ /* Get number of free bytes. */\r
38077+ pVpdStatus = VpdStat(pAC, IoC);\r
38078+ if (pVpdStatus == NULL) {\r
38079+\r
38080+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
38081+ (SK_PNMI_ERR017MSG));\r
38082+\r
38083+ *pLen = 0;\r
38084+ return (SK_PNMI_ERR_GENERAL);\r
38085+ }\r
38086+ if ((pVpdStatus->vpd_status & VPD_VALID) == 0) {\r
38087+\r
38088+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
38089+ (SK_PNMI_ERR018MSG));\r
38090+\r
38091+ *pLen = 0;\r
38092+ return (SK_PNMI_ERR_GENERAL);\r
38093+ }\r
38094+ \r
38095+ Val32 = (SK_U32)pVpdStatus->vpd_free_rw;\r
38096+ SK_PNMI_STORE_U32(pBuf, Val32);\r
38097+ *pLen = sizeof(SK_U32);\r
38098+ break;\r
38099+\r
38100+ case OID_SKGE_VPD_ENTRIES_LIST:\r
38101+ /* Check length. */\r
38102+ for (Len = 0, Index = 0; Index < KeyNo; Index ++) {\r
38103+\r
38104+ Len += SK_STRLEN(KeyArr[Index]) + 1;\r
38105+ }\r
38106+ if (*pLen < Len) {\r
38107+\r
38108+ *pLen = Len;\r
38109+ return (SK_PNMI_ERR_TOO_SHORT);\r
38110+ }\r
38111+\r
38112+ /* Get value. */\r
38113+ *(pBuf) = (char)Len - 1;\r
38114+ for (Offset = 1, Index = 0; Index < KeyNo; Index ++) {\r
38115+\r
38116+ Len = SK_STRLEN(KeyArr[Index]);\r
38117+ SK_MEMCPY(pBuf + Offset, KeyArr[Index], Len);\r
38118+\r
38119+ Offset += Len;\r
38120+\r
38121+ if (Index < KeyNo - 1) {\r
38122+\r
38123+ *(pBuf + Offset) = ' ';\r
38124+ Offset ++;\r
38125+ }\r
38126+ }\r
38127+ *pLen = Offset;\r
38128+ break;\r
38129+\r
38130+ case OID_SKGE_VPD_ENTRIES_NUMBER:\r
38131+ /* Check length. */\r
38132+ if (*pLen < sizeof(SK_U32)) {\r
38133+\r
38134+ *pLen = sizeof(SK_U32);\r
38135+ return (SK_PNMI_ERR_TOO_SHORT);\r
38136+ }\r
38137+\r
38138+ Val32 = (SK_U32)KeyNo;\r
38139+ SK_PNMI_STORE_U32(pBuf, Val32);\r
38140+ *pLen = sizeof(SK_U32);\r
38141+ break;\r
38142+\r
38143+ case OID_SKGE_VPD_KEY:\r
38144+ /* Check buffer length, if it is large enough. */\r
38145+ for (Len = 0, Index = FirstIndex;\r
38146+ Index < LastIndex; Index ++) {\r
38147+\r
38148+ Len += SK_STRLEN(KeyArr[Index]) + 1;\r
38149+ }\r
38150+ if (*pLen < Len) {\r
38151+\r
38152+ *pLen = Len;\r
38153+ return (SK_PNMI_ERR_TOO_SHORT);\r
38154+ }\r
38155+\r
38156+ /*\r
38157+ * Get the key to an intermediate buffer, because\r
38158+ * we have to prepend a length byte.\r
38159+ */\r
38160+ for (Offset = 0, Index = FirstIndex; Index < LastIndex; Index ++) {\r
38161+\r
38162+ Len = SK_STRLEN(KeyArr[Index]);\r
38163+\r
38164+ *(pBuf + Offset) = (char)Len;\r
38165+ SK_MEMCPY(pBuf + Offset + 1, KeyArr[Index], Len);\r
38166+ Offset += Len + 1;\r
38167+ }\r
38168+ *pLen = Offset;\r
38169+ break;\r
38170+\r
38171+ case OID_SKGE_VPD_VALUE:\r
38172+ /* Check the buffer length if it is large enough. */\r
38173+ for (Offset = 0, Index = FirstIndex; Index < LastIndex; Index ++) {\r
38174+\r
38175+ BufLen = 256;\r
38176+ if (VpdRead(pAC, IoC, KeyArr[Index], Buf,\r
38177+ (int *)&BufLen) > 0 ||\r
38178+ BufLen >= SK_PNMI_VPD_DATALEN) {\r
38179+\r
38180+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
38181+ (SK_PNMI_ERR021MSG));\r
38182+\r
38183+ return (SK_PNMI_ERR_GENERAL);\r
38184+ }\r
38185+ Offset += BufLen + 1;\r
38186+ }\r
38187+ if (*pLen < Offset) {\r
38188+\r
38189+ *pLen = Offset;\r
38190+ return (SK_PNMI_ERR_TOO_SHORT);\r
38191+ }\r
38192+\r
38193+ /*\r
38194+ * Get the value to an intermediate buffer, because\r
38195+ * we have to prepend a length byte.\r
38196+ */\r
38197+ for (Offset = 0, Index = FirstIndex; Index < LastIndex; Index ++) {\r
38198+\r
38199+ BufLen = 256;\r
38200+ if (VpdRead(pAC, IoC, KeyArr[Index], Buf,\r
38201+ (int *)&BufLen) > 0 ||\r
38202+ BufLen >= SK_PNMI_VPD_DATALEN) {\r
38203+\r
38204+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
38205+ (SK_PNMI_ERR022MSG));\r
38206+\r
38207+ *pLen = 0;\r
38208+ return (SK_PNMI_ERR_GENERAL);\r
38209+ }\r
38210+\r
38211+ *(pBuf + Offset) = (char)BufLen;\r
38212+ SK_MEMCPY(pBuf + Offset + 1, Buf, BufLen);\r
38213+ Offset += BufLen + 1;\r
38214+ }\r
38215+ *pLen = Offset;\r
38216+ break;\r
38217+\r
38218+ case OID_SKGE_VPD_ACCESS:\r
38219+ if (*pLen < LastIndex - FirstIndex) {\r
38220+\r
38221+ *pLen = LastIndex - FirstIndex;\r
38222+ return (SK_PNMI_ERR_TOO_SHORT);\r
38223+ }\r
38224+\r
38225+ for (Offset = 0, Index = FirstIndex; Index < LastIndex; Index ++) {\r
38226+\r
38227+ if (VpdMayWrite(KeyArr[Index])) {\r
38228+\r
38229+ *(pBuf + Offset) = SK_PNMI_VPD_RW;\r
38230+ }\r
38231+ else {\r
38232+ *(pBuf + Offset) = SK_PNMI_VPD_RO;\r
38233+ }\r
38234+ Offset ++;\r
38235+ }\r
38236+ *pLen = Offset;\r
38237+ break;\r
38238+\r
38239+ case OID_SKGE_VPD_ACTION:\r
38240+ Offset = LastIndex - FirstIndex;\r
38241+ if (*pLen < Offset) {\r
38242+\r
38243+ *pLen = Offset;\r
38244+ return (SK_PNMI_ERR_TOO_SHORT);\r
38245+ }\r
38246+ SK_MEMSET(pBuf, 0, Offset);\r
38247+ *pLen = Offset;\r
38248+ break;\r
38249+\r
38250+ default:\r
38251+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
38252+ (SK_PNMI_ERR023MSG));\r
38253+\r
38254+ *pLen = 0;\r
38255+ return (SK_PNMI_ERR_GENERAL);\r
38256+ }\r
38257+ }\r
38258+ else {\r
38259+ /* The only OID which can be set is VPD_ACTION. */\r
38260+ if (Id != OID_SKGE_VPD_ACTION) {\r
38261+\r
38262+ if (Id == OID_SKGE_VPD_FREE_BYTES ||\r
38263+ Id == OID_SKGE_VPD_ENTRIES_LIST ||\r
38264+ Id == OID_SKGE_VPD_ENTRIES_NUMBER ||\r
38265+ Id == OID_SKGE_VPD_KEY ||\r
38266+ Id == OID_SKGE_VPD_VALUE ||\r
38267+ Id == OID_SKGE_VPD_ACCESS) {\r
38268+\r
38269+ *pLen = 0;\r
38270+ return (SK_PNMI_ERR_READ_ONLY);\r
38271+ }\r
38272+\r
38273+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
38274+ (SK_PNMI_ERR024MSG));\r
38275+\r
38276+ *pLen = 0;\r
38277+ return (SK_PNMI_ERR_GENERAL);\r
38278+ }\r
38279+\r
38280+ /*\r
38281+ * From this point we handle VPD_ACTION. Check the buffer\r
38282+ * length. It should at least have the size of one byte.\r
38283+ */\r
38284+ if (*pLen < 1) {\r
38285+\r
38286+ *pLen = 1;\r
38287+ return (SK_PNMI_ERR_TOO_SHORT);\r
38288+ }\r
38289+\r
38290+ /* The first byte contains the VPD action type we should perform. */\r
38291+ switch (*pBuf) {\r
38292+\r
38293+ case SK_PNMI_VPD_IGNORE:\r
38294+ /* Nothing to do. */\r
38295+ break;\r
38296+\r
38297+ case SK_PNMI_VPD_CREATE:\r
38298+ /*\r
38299+ * We have to create a new VPD entry or we modify\r
38300+ * an existing one. Check first the buffer length.\r
38301+ */\r
38302+ if (*pLen < 4) {\r
38303+\r
38304+ *pLen = 4;\r
38305+ return (SK_PNMI_ERR_TOO_SHORT);\r
38306+ }\r
38307+ KeyStr[0] = pBuf[1];\r
38308+ KeyStr[1] = pBuf[2];\r
38309+ KeyStr[2] = 0;\r
38310+\r
38311+ /*\r
38312+ * Is the entry writable or does it belong to the\r
38313+ * read-only area?\r
38314+ */\r
38315+ if (!VpdMayWrite(KeyStr)) {\r
38316+\r
38317+ *pLen = 0;\r
38318+ return (SK_PNMI_ERR_BAD_VALUE);\r
38319+ }\r
38320+\r
38321+ Offset = (int)pBuf[3] & 0xFF;\r
38322+\r
38323+ SK_MEMCPY(Buf, pBuf + 4, Offset);\r
38324+ Buf[Offset] = 0;\r
38325+\r
38326+ /* A PRESET ends here. */\r
38327+ if (Action == SK_PNMI_PRESET) {\r
38328+\r
38329+ return (SK_PNMI_ERR_OK);\r
38330+ }\r
38331+\r
38332+ /* Write the new entry or modify an existing one .*/\r
38333+ Ret = VpdWrite(pAC, IoC, KeyStr, Buf);\r
38334+ if (Ret == SK_PNMI_VPD_NOWRITE ) {\r
38335+\r
38336+ *pLen = 0;\r
38337+ return (SK_PNMI_ERR_BAD_VALUE);\r
38338+ }\r
38339+ else if (Ret != SK_PNMI_VPD_OK) {\r
38340+\r
38341+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
38342+ (SK_PNMI_ERR025MSG));\r
38343+\r
38344+ *pLen = 0;\r
38345+ return (SK_PNMI_ERR_GENERAL);\r
38346+ }\r
38347+\r
38348+ /*\r
38349+ * Perform an update of the VPD data. This is\r
38350+ * not mandantory, but just to be sure.\r
38351+ */\r
38352+ Ret = VpdUpdate(pAC, IoC);\r
38353+ if (Ret != SK_PNMI_VPD_OK) {\r
38354+\r
38355+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
38356+ (SK_PNMI_ERR026MSG));\r
38357+\r
38358+ *pLen = 0;\r
38359+ return (SK_PNMI_ERR_GENERAL);\r
38360+ }\r
38361+ break;\r
38362+\r
38363+ case SK_PNMI_VPD_DELETE:\r
38364+ /* Check if the buffer size is plausible. */\r
38365+ if (*pLen < 3) {\r
38366+\r
38367+ *pLen = 3;\r
38368+ return (SK_PNMI_ERR_TOO_SHORT);\r
38369+ }\r
38370+ if (*pLen > 3) {\r
38371+\r
38372+ *pLen = 0;\r
38373+ return (SK_PNMI_ERR_BAD_VALUE);\r
38374+ }\r
38375+ KeyStr[0] = pBuf[1];\r
38376+ KeyStr[1] = pBuf[2];\r
38377+ KeyStr[2] = 0;\r
38378+\r
38379+ /* Find the passed key in the array. */\r
38380+ for (Index = 0; Index < KeyNo; Index ++) {\r
38381+\r
38382+ if (SK_STRCMP(KeyStr, KeyArr[Index]) == 0) {\r
38383+\r
38384+ break;\r
38385+ }\r
38386+ }\r
38387+\r
38388+ /*\r
38389+ * If we cannot find the key it is wrong, so we\r
38390+ * return an appropriate error value.\r
38391+ */\r
38392+ if (Index == KeyNo) {\r
38393+\r
38394+ *pLen = 0;\r
38395+ return (SK_PNMI_ERR_BAD_VALUE);\r
38396+ }\r
38397+\r
38398+ if (Action == SK_PNMI_PRESET) {\r
38399+\r
38400+ return (SK_PNMI_ERR_OK);\r
38401+ }\r
38402+\r
38403+ /* Ok, you wanted it and you will get it. */\r
38404+ Ret = VpdDelete(pAC, IoC, KeyStr);\r
38405+ if (Ret != SK_PNMI_VPD_OK) {\r
38406+\r
38407+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
38408+ (SK_PNMI_ERR027MSG));\r
38409+\r
38410+ *pLen = 0;\r
38411+ return (SK_PNMI_ERR_GENERAL);\r
38412+ }\r
38413+\r
38414+ /*\r
38415+ * Perform an update of the VPD data. This is\r
38416+ * not mandantory, but just to be sure.\r
38417+ */\r
38418+ Ret = VpdUpdate(pAC, IoC);\r
38419+ if (Ret != SK_PNMI_VPD_OK) {\r
38420+\r
38421+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
38422+ (SK_PNMI_ERR028MSG));\r
38423+\r
38424+ *pLen = 0;\r
38425+ return (SK_PNMI_ERR_GENERAL);\r
38426+ }\r
38427+ break;\r
38428+\r
38429+ default:\r
38430+ *pLen = 0;\r
38431+ return (SK_PNMI_ERR_BAD_VALUE);\r
38432+ }\r
38433+ }\r
38434+\r
38435+ return (SK_PNMI_ERR_OK);\r
38436+}\r
38437+\r
38438+/*****************************************************************************\r
38439+ *\r
38440+ * General - OID handler function of various single instance OIDs\r
38441+ *\r
38442+ * Description:\r
38443+ * The code is simple. No description necessary.\r
38444+ *\r
38445+ * Returns:\r
38446+ * SK_PNMI_ERR_OK The request was successfully performed.\r
38447+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.\r
38448+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain\r
38449+ * the correct data (e.g. a 32bit value is\r
38450+ * needed, but a 16 bit value was passed).\r
38451+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't\r
38452+ * exist (e.g. port instance 3 on a two port\r
38453+ * adapter.\r
38454+ */\r
38455+PNMI_STATIC int General(\r
38456+SK_AC *pAC, /* Pointer to adapter context */\r
38457+SK_IOC IoC, /* IO context handle */\r
38458+int Action, /* GET/PRESET/SET action */\r
38459+SK_U32 Id, /* Object ID that is to be processed */\r
38460+char *pBuf, /* Buffer used for the management data transfer */\r
38461+unsigned int *pLen, /* On call: buffer length. On return: used buffer */\r
38462+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */\r
38463+unsigned int TableIndex, /* Index to the Id table */\r
38464+SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */\r
38465+{\r
38466+ int Ret;\r
38467+ unsigned int Index;\r
38468+ unsigned int Len;\r
38469+ unsigned int Offset;\r
38470+ unsigned int Val;\r
38471+ SK_U8 Val8;\r
38472+ SK_U16 Val16;\r
38473+ SK_U32 Val32;\r
38474+ SK_U64 Val64;\r
38475+ SK_U64 Val64RxHwErrs = 0;\r
38476+ SK_U64 Val64RxRunt = 0;\r
38477+ SK_U64 Val64RxFcs = 0;\r
38478+ SK_U64 Val64TxHwErrs = 0;\r
38479+ SK_BOOL Is64BitReq = SK_FALSE;\r
38480+ char Buf[256];\r
38481+ int MacType;\r
38482+\r
38483+ /* Check instance. We only handle single instance variables. */\r
38484+ if (Instance != (SK_U32)(-1) && Instance != 1) {\r
38485+\r
38486+ *pLen = 0;\r
38487+ return (SK_PNMI_ERR_UNKNOWN_INST);\r
38488+ }\r
38489+\r
38490+ /* Check action. We only allow get requests. */\r
38491+ if (Action != SK_PNMI_GET) {\r
38492+\r
38493+ *pLen = 0;\r
38494+ return (SK_PNMI_ERR_READ_ONLY);\r
38495+ }\r
38496+ \r
38497+ MacType = pAC->GIni.GIMacType;\r
38498+ \r
38499+ /* Check length for the various supported OIDs. */\r
38500+ switch (Id) {\r
38501+\r
38502+ case OID_GEN_XMIT_ERROR:\r
38503+ case OID_GEN_RCV_ERROR:\r
38504+ case OID_GEN_RCV_NO_BUFFER:\r
38505+#ifndef SK_NDIS_64BIT_CTR\r
38506+ if (*pLen < sizeof(SK_U32)) {\r
38507+ *pLen = sizeof(SK_U32);\r
38508+ return (SK_PNMI_ERR_TOO_SHORT);\r
38509+ }\r
38510+\r
38511+#else /* SK_NDIS_64BIT_CTR */\r
38512+\r
38513+ /* For compatibility, at least 32bit are required for OID. */\r
38514+ if (*pLen < sizeof(SK_U32)) {\r
38515+ /*\r
38516+ * Indicate handling for 64bit values,\r
38517+ * if insufficient space is provided.\r
38518+ */\r
38519+ *pLen = sizeof(SK_U64);\r
38520+ return (SK_PNMI_ERR_TOO_SHORT);\r
38521+ }\r
38522+\r
38523+ Is64BitReq = (*pLen < sizeof(SK_U64)) ? SK_FALSE : SK_TRUE;\r
38524+#endif /* SK_NDIS_64BIT_CTR */\r
38525+ break;\r
38526+\r
38527+ case OID_SKGE_PORT_NUMBER:\r
38528+ case OID_SKGE_DEVICE_TYPE:\r
38529+ case OID_SKGE_RESULT:\r
38530+ case OID_SKGE_RLMT_MONITOR_NUMBER:\r
38531+ case OID_GEN_TRANSMIT_QUEUE_LENGTH:\r
38532+ case OID_SKGE_TRAP_NUMBER:\r
38533+ case OID_SKGE_MDB_VERSION:\r
38534+ case OID_SKGE_BOARDLEVEL:\r
38535+ case OID_SKGE_CHIPID:\r
38536+ case OID_SKGE_RAMSIZE:\r
38537+ if (*pLen < sizeof(SK_U32)) {\r
38538+\r
38539+ *pLen = sizeof(SK_U32);\r
38540+ return (SK_PNMI_ERR_TOO_SHORT);\r
38541+ }\r
38542+ break;\r
38543+\r
38544+ case OID_SKGE_CHIPSET:\r
38545+ if (*pLen < sizeof(SK_U16)) {\r
38546+\r
38547+ *pLen = sizeof(SK_U16);\r
38548+ return (SK_PNMI_ERR_TOO_SHORT);\r
38549+ }\r
38550+ break;\r
38551+\r
38552+ case OID_SKGE_BUS_TYPE:\r
38553+ case OID_SKGE_BUS_SPEED:\r
38554+ case OID_SKGE_BUS_WIDTH:\r
38555+ case OID_SKGE_SENSOR_NUMBER:\r
38556+ case OID_SKGE_CHKSM_NUMBER:\r
38557+ case OID_SKGE_VAUXAVAIL:\r
38558+ if (*pLen < sizeof(SK_U8)) {\r
38559+\r
38560+ *pLen = sizeof(SK_U8);\r
38561+ return (SK_PNMI_ERR_TOO_SHORT);\r
38562+ }\r
38563+ break;\r
38564+\r
38565+ case OID_SKGE_TX_SW_QUEUE_LEN:\r
38566+ case OID_SKGE_TX_SW_QUEUE_MAX:\r
38567+ case OID_SKGE_TX_RETRY:\r
38568+ case OID_SKGE_RX_INTR_CTS:\r
38569+ case OID_SKGE_TX_INTR_CTS:\r
38570+ case OID_SKGE_RX_NO_BUF_CTS:\r
38571+ case OID_SKGE_TX_NO_BUF_CTS:\r
38572+ case OID_SKGE_TX_USED_DESCR_NO:\r
38573+ case OID_SKGE_RX_DELIVERED_CTS:\r
38574+ case OID_SKGE_RX_OCTETS_DELIV_CTS:\r
38575+ case OID_SKGE_RX_HW_ERROR_CTS:\r
38576+ case OID_SKGE_TX_HW_ERROR_CTS:\r
38577+ case OID_SKGE_IN_ERRORS_CTS:\r
38578+ case OID_SKGE_OUT_ERROR_CTS:\r
38579+ case OID_SKGE_ERR_RECOVERY_CTS:\r
38580+ case OID_SKGE_SYSUPTIME:\r
38581+ if (*pLen < sizeof(SK_U64)) {\r
38582+\r
38583+ *pLen = sizeof(SK_U64);\r
38584+ return (SK_PNMI_ERR_TOO_SHORT);\r
38585+ }\r
38586+ break;\r
38587+\r
38588+ default:\r
38589+ /* Checked later. */\r
38590+ break;\r
38591+ }\r
38592+\r
38593+ /* Update statistics. */\r
38594+ if (Id == OID_SKGE_RX_HW_ERROR_CTS ||\r
38595+ Id == OID_SKGE_TX_HW_ERROR_CTS ||\r
38596+ Id == OID_SKGE_IN_ERRORS_CTS ||\r
38597+ Id == OID_SKGE_OUT_ERROR_CTS ||\r
38598+ Id == OID_GEN_XMIT_ERROR ||\r
38599+ Id == OID_GEN_RCV_ERROR) {\r
38600+\r
38601+ /*\r
38602+ * Force the XMAC to update its statistic counters and\r
38603+ * Increment semaphore to indicate that an update was\r
38604+ * already done.\r
38605+ */\r
38606+ Ret = MacUpdate(pAC, IoC, 0, pAC->GIni.GIMacsFound - 1);\r
38607+ if (Ret != SK_PNMI_ERR_OK) {\r
38608+\r
38609+ *pLen = 0;\r
38610+ return (Ret);\r
38611+ }\r
38612+ pAC->Pnmi.MacUpdatedFlag ++;\r
38613+\r
38614+ /*\r
38615+ * Some OIDs consist of multiple hardware counters. Those\r
38616+ * values which are contained in all of them will be added\r
38617+ * now.\r
38618+ */\r
38619+ switch (Id) {\r
38620+\r
38621+ case OID_SKGE_RX_HW_ERROR_CTS:\r
38622+ case OID_SKGE_IN_ERRORS_CTS:\r
38623+ case OID_GEN_RCV_ERROR:\r
38624+ Val64RxHwErrs =\r
38625+ GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_MISSED, NetIndex) +\r
38626+ GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_FRAMING, NetIndex) +\r
38627+ GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_OVERFLOW, NetIndex) +\r
38628+ GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_JABBER, NetIndex) +\r
38629+ GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_CARRIER, NetIndex) +\r
38630+ GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_IRLENGTH, NetIndex) +\r
38631+ GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_SYMBOL, NetIndex) +\r
38632+ GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_SHORTS, NetIndex) +\r
38633+ GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_TOO_LONG, NetIndex) +\r
38634+ GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_CEXT, NetIndex);\r
38635+\r
38636+\r
38637+ /*\r
38638+ * In some cases the runt and fcs counters are incremented when collisions\r
38639+ * occur. We have to correct those counters here.\r
38640+ */\r
38641+ Val64RxRunt = GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_RUNT, NetIndex);\r
38642+ Val64RxFcs = GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_FCS, NetIndex);\r
38643+\r
38644+ if (Val64RxRunt > Val64RxFcs) {\r
38645+ Val64RxRunt -= Val64RxFcs;\r
38646+ Val64RxHwErrs += Val64RxRunt;\r
38647+ }\r
38648+ else {\r
38649+ Val64RxFcs -= Val64RxRunt;\r
38650+ Val64RxHwErrs += Val64RxFcs;\r
38651+ }\r
38652+ break;\r
38653+\r
38654+ case OID_SKGE_TX_HW_ERROR_CTS:\r
38655+ case OID_SKGE_OUT_ERROR_CTS:\r
38656+ case OID_GEN_XMIT_ERROR:\r
38657+ Val64TxHwErrs =\r
38658+ GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_EXCESS_COL, NetIndex) +\r
38659+ GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_LATE_COL, NetIndex) +\r
38660+ GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_UNDERRUN, NetIndex) +\r
38661+ GetStatVal(pAC, IoC, 0, SK_PNMI_HTX_CARRIER, NetIndex);\r
38662+ break;\r
38663+ }\r
38664+ }\r
38665+\r
38666+ /* Retrieve value. */\r
38667+ switch (Id) {\r
38668+\r
38669+ case OID_SKGE_SUPPORTED_LIST:\r
38670+ Len = ID_TABLE_SIZE * sizeof(SK_U32);\r
38671+ if (*pLen < Len) {\r
38672+\r
38673+ *pLen = Len;\r
38674+ return (SK_PNMI_ERR_TOO_SHORT);\r
38675+ }\r
38676+ for (Offset = 0, Index = 0; Offset < Len; Index ++) {\r
38677+\r
38678+ Val32 = (SK_U32)IdTable[Index].Id;\r
38679+ SK_PNMI_STORE_U32(pBuf + Offset, Val32);\r
38680+ Offset += sizeof(SK_U32);\r
38681+ }\r
38682+ *pLen = Len;\r
38683+ break;\r
38684+\r
38685+ case OID_SKGE_BOARDLEVEL:\r
38686+ Val32 = (SK_U32)pAC->GIni.GILevel;\r
38687+ SK_PNMI_STORE_U32(pBuf, Val32);\r
38688+ *pLen = sizeof(SK_U32);\r
38689+ break;\r
38690+\r
38691+ case OID_SKGE_PORT_NUMBER:\r
38692+ Val32 = (SK_U32)pAC->GIni.GIMacsFound;\r
38693+ SK_PNMI_STORE_U32(pBuf, Val32);\r
38694+ *pLen = sizeof(SK_U32);\r
38695+ break;\r
38696+\r
38697+ case OID_SKGE_DEVICE_TYPE:\r
38698+ Val32 = (SK_U32)pAC->Pnmi.DeviceType;\r
38699+ SK_PNMI_STORE_U32(pBuf, Val32);\r
38700+ *pLen = sizeof(SK_U32);\r
38701+ break;\r
38702+\r
38703+ case OID_SKGE_DRIVER_DESCR:\r
38704+ if (pAC->Pnmi.pDriverDescription == NULL) {\r
38705+\r
38706+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR007, SK_PNMI_ERR007MSG);\r
38707+\r
38708+ *pLen = 0;\r
38709+ return (SK_PNMI_ERR_GENERAL);\r
38710+ }\r
38711+\r
38712+ Len = SK_STRLEN(pAC->Pnmi.pDriverDescription) + 1;\r
38713+ if (Len > SK_PNMI_STRINGLEN1) {\r
38714+\r
38715+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR029, SK_PNMI_ERR029MSG);\r
38716+\r
38717+ *pLen = 0;\r
38718+ return (SK_PNMI_ERR_GENERAL);\r
38719+ }\r
38720+\r
38721+ if (*pLen < Len) {\r
38722+\r
38723+ *pLen = Len;\r
38724+ return (SK_PNMI_ERR_TOO_SHORT);\r
38725+ }\r
38726+ *pBuf = (char)(Len - 1);\r
38727+ SK_MEMCPY(pBuf + 1, pAC->Pnmi.pDriverDescription, Len - 1);\r
38728+ *pLen = Len;\r
38729+ break;\r
38730+\r
38731+ case OID_SKGE_DRIVER_VERSION:\r
38732+ if (pAC->Pnmi.pDriverVersion == NULL) {\r
38733+\r
38734+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR030, SK_PNMI_ERR030MSG);\r
38735+\r
38736+ *pLen = 0;\r
38737+ return (SK_PNMI_ERR_GENERAL);\r
38738+ }\r
38739+\r
38740+ Len = SK_STRLEN(pAC->Pnmi.pDriverVersion) + 1;\r
38741+ if (Len > SK_PNMI_STRINGLEN1) {\r
38742+\r
38743+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR031, SK_PNMI_ERR031MSG);\r
38744+\r
38745+ *pLen = 0;\r
38746+ return (SK_PNMI_ERR_GENERAL);\r
38747+ }\r
38748+\r
38749+ if (*pLen < Len) {\r
38750+\r
38751+ *pLen = Len;\r
38752+ return (SK_PNMI_ERR_TOO_SHORT);\r
38753+ }\r
38754+ *pBuf = (char)(Len - 1);\r
38755+ SK_MEMCPY(pBuf + 1, pAC->Pnmi.pDriverVersion, Len - 1);\r
38756+ *pLen = Len;\r
38757+ break;\r
38758+\r
38759+ case OID_SKGE_DRIVER_RELDATE:\r
38760+ if (pAC->Pnmi.pDriverReleaseDate == NULL) {\r
38761+\r
38762+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR053, SK_PNMI_ERR053MSG);\r
38763+\r
38764+ *pLen = 0;\r
38765+ return (SK_PNMI_ERR_GENERAL);\r
38766+ }\r
38767+\r
38768+ Len = SK_STRLEN(pAC->Pnmi.pDriverReleaseDate) + 1;\r
38769+ if (Len > SK_PNMI_STRINGLEN1) {\r
38770+\r
38771+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR054, SK_PNMI_ERR054MSG);\r
38772+\r
38773+ *pLen = 0;\r
38774+ return (SK_PNMI_ERR_GENERAL);\r
38775+ }\r
38776+\r
38777+ if (*pLen < Len) {\r
38778+\r
38779+ *pLen = Len;\r
38780+ return (SK_PNMI_ERR_TOO_SHORT);\r
38781+ }\r
38782+ *pBuf = (char)(Len - 1);\r
38783+ SK_MEMCPY(pBuf + 1, pAC->Pnmi.pDriverReleaseDate, Len - 1);\r
38784+ *pLen = Len;\r
38785+ break;\r
38786+\r
38787+ case OID_SKGE_DRIVER_FILENAME:\r
38788+ if (pAC->Pnmi.pDriverFileName == NULL) {\r
38789+\r
38790+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR055, SK_PNMI_ERR055MSG);\r
38791+\r
38792+ *pLen = 0;\r
38793+ return (SK_PNMI_ERR_GENERAL);\r
38794+ }\r
38795+\r
38796+ Len = SK_STRLEN(pAC->Pnmi.pDriverFileName) + 1;\r
38797+ if (Len > SK_PNMI_STRINGLEN1) {\r
38798+\r
38799+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR056, SK_PNMI_ERR056MSG);\r
38800+\r
38801+ *pLen = 0;\r
38802+ return (SK_PNMI_ERR_GENERAL);\r
38803+ }\r
38804+\r
38805+ if (*pLen < Len) {\r
38806+\r
38807+ *pLen = Len;\r
38808+ return (SK_PNMI_ERR_TOO_SHORT);\r
38809+ }\r
38810+ *pBuf = (char)(Len - 1);\r
38811+ SK_MEMCPY(pBuf + 1, pAC->Pnmi.pDriverFileName, Len - 1);\r
38812+ *pLen = Len;\r
38813+ break;\r
38814+\r
38815+ case OID_SKGE_HW_DESCR:\r
38816+ /*\r
38817+ * The hardware description is located in the VPD. This\r
38818+ * query may move to the initialisation routine. But\r
38819+ * the VPD data is cached and therefore a call here\r
38820+ * will not make much difference.\r
38821+ * Please read comment in Vpd().\r
38822+ */\r
38823+ if (pAC->Pnmi.VpdKeyReadError == SK_TRUE) {\r
38824+ return (SK_PNMI_ERR_OK);\r
38825+ }\r
38826+\r
38827+ Len = 256;\r
38828+ if (VpdRead(pAC, IoC, VPD_NAME, Buf, (int *)&Len) > 0) {\r
38829+\r
38830+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR032, SK_PNMI_ERR032MSG);\r
38831+\r
38832+ *pLen = 0;\r
38833+ return (SK_PNMI_ERR_GENERAL);\r
38834+ }\r
38835+ Len ++;\r
38836+ if (Len > SK_PNMI_STRINGLEN1) {\r
38837+\r
38838+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR033, SK_PNMI_ERR033MSG);\r
38839+\r
38840+ *pLen = 0;\r
38841+ return (SK_PNMI_ERR_GENERAL);\r
38842+ }\r
38843+ if (*pLen < Len) {\r
38844+\r
38845+ *pLen = Len;\r
38846+ return (SK_PNMI_ERR_TOO_SHORT);\r
38847+ }\r
38848+ *pBuf = (char)(Len - 1);\r
38849+ SK_MEMCPY(pBuf + 1, Buf, Len - 1);\r
38850+ *pLen = Len;\r
38851+ break;\r
38852+\r
38853+ case OID_SKGE_HW_VERSION:\r
38854+ if (*pLen < 5) {\r
38855+\r
38856+ *pLen = 5;\r
38857+ return (SK_PNMI_ERR_TOO_SHORT);\r
38858+ }\r
38859+ Val8 = (SK_U8)pAC->GIni.GIPciHwRev;\r
38860+ pBuf[0] = 4;\r
38861+ pBuf[1] = 'v';\r
38862+ pBuf[2] = (char)('0' | ((Val8 >> 4) & 0x0f));\r
38863+ pBuf[3] = '.';\r
38864+ pBuf[4] = (char)('0' | (Val8 & 0x0f));\r
38865+ *pLen = 5;\r
38866+ break;\r
38867+\r
38868+ case OID_SKGE_CHIPSET:\r
38869+ Val16 = pAC->Pnmi.Chipset;\r
38870+ SK_PNMI_STORE_U16(pBuf, Val16);\r
38871+ *pLen = sizeof(SK_U16);\r
38872+ break;\r
38873+\r
38874+ case OID_SKGE_CHIPID:\r
38875+ Val32 = pAC->GIni.GIChipId;\r
38876+ SK_PNMI_STORE_U32(pBuf, Val32);\r
38877+ *pLen = sizeof(SK_U32);\r
38878+ break;\r
38879+\r
38880+ case OID_SKGE_RAMSIZE:\r
38881+ Val32 = pAC->GIni.GIRamSize;\r
38882+ SK_PNMI_STORE_U32(pBuf, Val32);\r
38883+ *pLen = sizeof(SK_U32);\r
38884+ break;\r
38885+\r
38886+ case OID_SKGE_VAUXAVAIL:\r
38887+ *pBuf = (char)pAC->GIni.GIVauxAvail;\r
38888+ *pLen = sizeof(char);\r
38889+ break;\r
38890+\r
38891+ case OID_SKGE_BUS_TYPE:\r
38892+ *pBuf = (char)SK_PNMI_BUS_PCI;\r
38893+ *pLen = sizeof(char);\r
38894+ break;\r
38895+\r
38896+ case OID_SKGE_BUS_SPEED:\r
38897+ *pBuf = pAC->Pnmi.PciBusSpeed;\r
38898+ *pLen = sizeof(char);\r
38899+ break;\r
38900+\r
38901+ case OID_SKGE_BUS_WIDTH:\r
38902+ *pBuf = pAC->Pnmi.PciBusWidth;\r
38903+ *pLen = sizeof(char);\r
38904+ break;\r
38905+\r
38906+ case OID_SKGE_RESULT:\r
38907+ Val32 = pAC->Pnmi.TestResult;\r
38908+ SK_PNMI_STORE_U32(pBuf, Val32);\r
38909+ *pLen = sizeof(SK_U32);\r
38910+ break;\r
38911+\r
38912+ case OID_SKGE_SENSOR_NUMBER:\r
38913+ *pBuf = (char)pAC->I2c.MaxSens;\r
38914+ *pLen = sizeof(char);\r
38915+ break;\r
38916+\r
38917+ case OID_SKGE_CHKSM_NUMBER:\r
38918+ *pBuf = SKCS_NUM_PROTOCOLS;\r
38919+ *pLen = sizeof(char);\r
38920+ break;\r
38921+\r
38922+ case OID_SKGE_TRAP_NUMBER:\r
38923+ GetTrapQueueLen(pAC, &Len, &Val);\r
38924+ Val32 = (SK_U32)Val;\r
38925+ SK_PNMI_STORE_U32(pBuf, Val32);\r
38926+ *pLen = sizeof(SK_U32);\r
38927+ break;\r
38928+\r
38929+ case OID_SKGE_TRAP:\r
38930+ GetTrapQueueLen(pAC, &Len, &Val);\r
38931+ if (*pLen < Len) {\r
38932+\r
38933+ *pLen = Len;\r
38934+ return (SK_PNMI_ERR_TOO_SHORT);\r
38935+ }\r
38936+ CopyTrapQueue(pAC, pBuf);\r
38937+ *pLen = Len;\r
38938+ break;\r
38939+\r
38940+ case OID_SKGE_RLMT_MONITOR_NUMBER:\r
38941+ /* Not yet implemented by RLMT, therefore we return zero elements. */\r
38942+ Val32 = 0;\r
38943+ SK_PNMI_STORE_U32(pBuf, Val32);\r
38944+ *pLen = sizeof(SK_U32);\r
38945+ break;\r
38946+\r
38947+ case OID_SKGE_TX_SW_QUEUE_LEN:\r
38948+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */\r
38949+ if (MacType == SK_MAC_XMAC) {\r
38950+ /* DualNet mode. */\r
38951+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
38952+ Val64 = pAC->Pnmi.BufPort[NetIndex].TxSwQueueLen;\r
38953+ }\r
38954+ /* SingleNet mode. */\r
38955+ else {\r
38956+ Val64 = pAC->Pnmi.BufPort[0].TxSwQueueLen +\r
38957+ pAC->Pnmi.BufPort[1].TxSwQueueLen;\r
38958+ } \r
38959+ }\r
38960+ else {\r
38961+ /* DualNet mode. */\r
38962+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
38963+ Val64 = pAC->Pnmi.Port[NetIndex].TxSwQueueLen;\r
38964+ }\r
38965+ /* SingleNet mode. */\r
38966+ else {\r
38967+ Val64 = pAC->Pnmi.Port[0].TxSwQueueLen +\r
38968+ pAC->Pnmi.Port[1].TxSwQueueLen;\r
38969+ } \r
38970+ }\r
38971+ SK_PNMI_STORE_U64(pBuf, Val64);\r
38972+ *pLen = sizeof(SK_U64);\r
38973+ break;\r
38974+\r
38975+\r
38976+ case OID_SKGE_TX_SW_QUEUE_MAX:\r
38977+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */\r
38978+ if (MacType == SK_MAC_XMAC) {\r
38979+ /* DualNet mode. */\r
38980+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
38981+ Val64 = pAC->Pnmi.BufPort[NetIndex].TxSwQueueMax;\r
38982+ }\r
38983+ /* SingleNet mode. */\r
38984+ else {\r
38985+ Val64 = pAC->Pnmi.BufPort[0].TxSwQueueMax +\r
38986+ pAC->Pnmi.BufPort[1].TxSwQueueMax;\r
38987+ }\r
38988+ }\r
38989+ else {\r
38990+ /* DualNet mode. */\r
38991+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
38992+ Val64 = pAC->Pnmi.Port[NetIndex].TxSwQueueMax;\r
38993+ }\r
38994+ /* SingleNet mode. */\r
38995+ else {\r
38996+ Val64 = pAC->Pnmi.Port[0].TxSwQueueMax +\r
38997+ pAC->Pnmi.Port[1].TxSwQueueMax;\r
38998+ }\r
38999+ }\r
39000+ SK_PNMI_STORE_U64(pBuf, Val64);\r
39001+ *pLen = sizeof(SK_U64);\r
39002+ break;\r
39003+\r
39004+ case OID_SKGE_TX_RETRY:\r
39005+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */\r
39006+ if (MacType == SK_MAC_XMAC) {\r
39007+ /* DualNet mode. */\r
39008+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
39009+ Val64 = pAC->Pnmi.BufPort[NetIndex].TxRetryCts;\r
39010+ }\r
39011+ /* SingleNet mode. */\r
39012+ else {\r
39013+ Val64 = pAC->Pnmi.BufPort[0].TxRetryCts +\r
39014+ pAC->Pnmi.BufPort[1].TxRetryCts;\r
39015+ }\r
39016+ }\r
39017+ else {\r
39018+ /* DualNet mode. */\r
39019+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
39020+ Val64 = pAC->Pnmi.Port[NetIndex].TxRetryCts;\r
39021+ }\r
39022+ /* SingleNet mode. */\r
39023+ else {\r
39024+ Val64 = pAC->Pnmi.Port[0].TxRetryCts +\r
39025+ pAC->Pnmi.Port[1].TxRetryCts;\r
39026+ }\r
39027+ }\r
39028+ SK_PNMI_STORE_U64(pBuf, Val64);\r
39029+ *pLen = sizeof(SK_U64);\r
39030+ break;\r
39031+\r
39032+ case OID_SKGE_RX_INTR_CTS:\r
39033+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */\r
39034+ if (MacType == SK_MAC_XMAC) {\r
39035+ /* DualNet mode. */\r
39036+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
39037+ Val64 = pAC->Pnmi.BufPort[NetIndex].RxIntrCts;\r
39038+ }\r
39039+ /* SingleNet mode. */\r
39040+ else {\r
39041+ Val64 = pAC->Pnmi.BufPort[0].RxIntrCts +\r
39042+ pAC->Pnmi.BufPort[1].RxIntrCts;\r
39043+ }\r
39044+ }\r
39045+ else {\r
39046+ /* DualNet mode. */\r
39047+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
39048+ Val64 = pAC->Pnmi.Port[NetIndex].RxIntrCts;\r
39049+ }\r
39050+ /* SingleNet mode. */\r
39051+ else {\r
39052+ Val64 = pAC->Pnmi.Port[0].RxIntrCts +\r
39053+ pAC->Pnmi.Port[1].RxIntrCts;\r
39054+ }\r
39055+ }\r
39056+ SK_PNMI_STORE_U64(pBuf, Val64);\r
39057+ *pLen = sizeof(SK_U64);\r
39058+ break;\r
39059+\r
39060+ case OID_SKGE_TX_INTR_CTS:\r
39061+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */\r
39062+ if (MacType == SK_MAC_XMAC) {\r
39063+ /* DualNet mode. */\r
39064+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
39065+ Val64 = pAC->Pnmi.BufPort[NetIndex].TxIntrCts;\r
39066+ }\r
39067+ /* SingleNet mode. */\r
39068+ else {\r
39069+ Val64 = pAC->Pnmi.BufPort[0].TxIntrCts +\r
39070+ pAC->Pnmi.BufPort[1].TxIntrCts;\r
39071+ }\r
39072+ }\r
39073+ else {\r
39074+ /* DualNet mode. */\r
39075+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
39076+ Val64 = pAC->Pnmi.Port[NetIndex].TxIntrCts;\r
39077+ }\r
39078+ /* SingleNet mode. */\r
39079+ else {\r
39080+ Val64 = pAC->Pnmi.Port[0].TxIntrCts +\r
39081+ pAC->Pnmi.Port[1].TxIntrCts;\r
39082+ }\r
39083+ }\r
39084+ SK_PNMI_STORE_U64(pBuf, Val64);\r
39085+ *pLen = sizeof(SK_U64);\r
39086+ break;\r
39087+\r
39088+ case OID_SKGE_RX_NO_BUF_CTS:\r
39089+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */\r
39090+ if (MacType == SK_MAC_XMAC) {\r
39091+ /* DualNet mode. */\r
39092+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
39093+ Val64 = pAC->Pnmi.BufPort[NetIndex].RxNoBufCts;\r
39094+ }\r
39095+ /* SingleNet mode. */\r
39096+ else {\r
39097+ Val64 = pAC->Pnmi.BufPort[0].RxNoBufCts +\r
39098+ pAC->Pnmi.BufPort[1].RxNoBufCts;\r
39099+ }\r
39100+ }\r
39101+ else {\r
39102+ /* DualNet mode. */\r
39103+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
39104+ Val64 = pAC->Pnmi.Port[NetIndex].RxNoBufCts;\r
39105+ }\r
39106+ /* SingleNet mode. */\r
39107+ else {\r
39108+ Val64 = pAC->Pnmi.Port[0].RxNoBufCts +\r
39109+ pAC->Pnmi.Port[1].RxNoBufCts;\r
39110+ }\r
39111+ }\r
39112+ SK_PNMI_STORE_U64(pBuf, Val64);\r
39113+ *pLen = sizeof(SK_U64);\r
39114+ break;\r
39115+\r
39116+ case OID_SKGE_TX_NO_BUF_CTS:\r
39117+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */\r
39118+ if (MacType == SK_MAC_XMAC) {\r
39119+ /* DualNet mode. */\r
39120+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
39121+ Val64 = pAC->Pnmi.BufPort[NetIndex].TxNoBufCts;\r
39122+ }\r
39123+ /* SingleNet mode. */\r
39124+ else {\r
39125+ Val64 = pAC->Pnmi.BufPort[0].TxNoBufCts +\r
39126+ pAC->Pnmi.BufPort[1].TxNoBufCts;\r
39127+ }\r
39128+ }\r
39129+ else {\r
39130+ /* DualNet mode. */\r
39131+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
39132+ Val64 = pAC->Pnmi.Port[NetIndex].TxNoBufCts;\r
39133+ }\r
39134+ /* SingleNet mode. */\r
39135+ else {\r
39136+ Val64 = pAC->Pnmi.Port[0].TxNoBufCts +\r
39137+ pAC->Pnmi.Port[1].TxNoBufCts;\r
39138+ }\r
39139+ }\r
39140+ SK_PNMI_STORE_U64(pBuf, Val64);\r
39141+ *pLen = sizeof(SK_U64);\r
39142+ break;\r
39143+\r
39144+ case OID_SKGE_TX_USED_DESCR_NO:\r
39145+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */\r
39146+ if (MacType == SK_MAC_XMAC) {\r
39147+ /* DualNet mode. */\r
39148+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
39149+ Val64 = pAC->Pnmi.BufPort[NetIndex].TxUsedDescrNo;\r
39150+ }\r
39151+ /* SingleNet mode. */\r
39152+ else {\r
39153+ Val64 = pAC->Pnmi.BufPort[0].TxUsedDescrNo +\r
39154+ pAC->Pnmi.BufPort[1].TxUsedDescrNo;\r
39155+ }\r
39156+ }\r
39157+ else {\r
39158+ /* DualNet mode. */\r
39159+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
39160+ Val64 = pAC->Pnmi.Port[NetIndex].TxUsedDescrNo;\r
39161+ }\r
39162+ /* SingleNet mode. */\r
39163+ else {\r
39164+ Val64 = pAC->Pnmi.Port[0].TxUsedDescrNo +\r
39165+ pAC->Pnmi.Port[1].TxUsedDescrNo;\r
39166+ }\r
39167+ }\r
39168+ SK_PNMI_STORE_U64(pBuf, Val64);\r
39169+ *pLen = sizeof(SK_U64);\r
39170+ break;\r
39171+\r
39172+ case OID_SKGE_RX_DELIVERED_CTS:\r
39173+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */\r
39174+ if (MacType == SK_MAC_XMAC) {\r
39175+ /* DualNet mode. */\r
39176+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
39177+ Val64 = pAC->Pnmi.BufPort[NetIndex].RxDeliveredCts;\r
39178+ }\r
39179+ /* SingleNet mode. */\r
39180+ else {\r
39181+ Val64 = pAC->Pnmi.BufPort[0].RxDeliveredCts +\r
39182+ pAC->Pnmi.BufPort[1].RxDeliveredCts;\r
39183+ }\r
39184+ }\r
39185+ else {\r
39186+ /* DualNet mode. */\r
39187+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
39188+ Val64 = pAC->Pnmi.Port[NetIndex].RxDeliveredCts;\r
39189+ }\r
39190+ /* SingleNet mode. */\r
39191+ else {\r
39192+ Val64 = pAC->Pnmi.Port[0].RxDeliveredCts +\r
39193+ pAC->Pnmi.Port[1].RxDeliveredCts;\r
39194+ }\r
39195+ }\r
39196+ SK_PNMI_STORE_U64(pBuf, Val64);\r
39197+ *pLen = sizeof(SK_U64);\r
39198+ break;\r
39199+\r
39200+ case OID_SKGE_RX_OCTETS_DELIV_CTS:\r
39201+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */\r
39202+ if (MacType == SK_MAC_XMAC) {\r
39203+ /* DualNet mode. */\r
39204+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
39205+ Val64 = pAC->Pnmi.BufPort[NetIndex].RxOctetsDeliveredCts;\r
39206+ }\r
39207+ /* SingleNet mode. */\r
39208+ else {\r
39209+ Val64 = pAC->Pnmi.BufPort[0].RxOctetsDeliveredCts +\r
39210+ pAC->Pnmi.BufPort[1].RxOctetsDeliveredCts;\r
39211+ }\r
39212+ }\r
39213+ else {\r
39214+ /* DualNet mode. */\r
39215+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
39216+ Val64 = pAC->Pnmi.Port[NetIndex].RxOctetsDeliveredCts;\r
39217+ }\r
39218+ /* SingleNet mode. */\r
39219+ else {\r
39220+ Val64 = pAC->Pnmi.Port[0].RxOctetsDeliveredCts +\r
39221+ pAC->Pnmi.Port[1].RxOctetsDeliveredCts;\r
39222+ }\r
39223+ }\r
39224+ SK_PNMI_STORE_U64(pBuf, Val64);\r
39225+ *pLen = sizeof(SK_U64);\r
39226+ break;\r
39227+\r
39228+ case OID_SKGE_RX_HW_ERROR_CTS:\r
39229+ SK_PNMI_STORE_U64(pBuf, Val64RxHwErrs);\r
39230+ *pLen = sizeof(SK_U64);\r
39231+ break;\r
39232+\r
39233+ case OID_SKGE_TX_HW_ERROR_CTS:\r
39234+ SK_PNMI_STORE_U64(pBuf, Val64TxHwErrs);\r
39235+ *pLen = sizeof(SK_U64);\r
39236+ break;\r
39237+\r
39238+ case OID_SKGE_IN_ERRORS_CTS:\r
39239+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */\r
39240+ if (MacType == SK_MAC_XMAC) {\r
39241+ /* DualNet mode. */\r
39242+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
39243+ Val64 = Val64RxHwErrs + pAC->Pnmi.BufPort[NetIndex].RxNoBufCts;\r
39244+ }\r
39245+ /* SingleNet mode. */\r
39246+ else {\r
39247+ Val64 = Val64RxHwErrs +\r
39248+ pAC->Pnmi.BufPort[0].RxNoBufCts +\r
39249+ pAC->Pnmi.BufPort[1].RxNoBufCts;\r
39250+ }\r
39251+ }\r
39252+ else {\r
39253+ /* DualNet mode. */\r
39254+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
39255+ Val64 = Val64RxHwErrs + pAC->Pnmi.Port[NetIndex].RxNoBufCts;\r
39256+ }\r
39257+ /* SingleNet mode. */\r
39258+ else {\r
39259+ Val64 = Val64RxHwErrs +\r
39260+ pAC->Pnmi.Port[0].RxNoBufCts +\r
39261+ pAC->Pnmi.Port[1].RxNoBufCts;\r
39262+ }\r
39263+ }\r
39264+ SK_PNMI_STORE_U64(pBuf, Val64);\r
39265+ *pLen = sizeof(SK_U64);\r
39266+ break;\r
39267+\r
39268+ case OID_SKGE_OUT_ERROR_CTS:\r
39269+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */\r
39270+ if (MacType == SK_MAC_XMAC) {\r
39271+ /* DualNet mode. */\r
39272+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
39273+ Val64 = Val64TxHwErrs + pAC->Pnmi.BufPort[NetIndex].TxNoBufCts;\r
39274+ }\r
39275+ /* SingleNet mode. */\r
39276+ else {\r
39277+ Val64 = Val64TxHwErrs +\r
39278+ pAC->Pnmi.BufPort[0].TxNoBufCts +\r
39279+ pAC->Pnmi.BufPort[1].TxNoBufCts;\r
39280+ }\r
39281+ }\r
39282+ else {\r
39283+ /* DualNet mode. */\r
39284+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
39285+ Val64 = Val64TxHwErrs + pAC->Pnmi.Port[NetIndex].TxNoBufCts;\r
39286+ }\r
39287+ /* SingleNet mode. */\r
39288+ else {\r
39289+ Val64 = Val64TxHwErrs +\r
39290+ pAC->Pnmi.Port[0].TxNoBufCts +\r
39291+ pAC->Pnmi.Port[1].TxNoBufCts;\r
39292+ }\r
39293+ }\r
39294+ SK_PNMI_STORE_U64(pBuf, Val64);\r
39295+ *pLen = sizeof(SK_U64);\r
39296+ break;\r
39297+\r
39298+ case OID_SKGE_ERR_RECOVERY_CTS:\r
39299+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */\r
39300+ if (MacType == SK_MAC_XMAC) {\r
39301+ /* DualNet mode. */\r
39302+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
39303+ Val64 = pAC->Pnmi.BufPort[NetIndex].ErrRecoveryCts;\r
39304+ }\r
39305+ /* SingleNet mode. */\r
39306+ else {\r
39307+ Val64 = pAC->Pnmi.BufPort[0].ErrRecoveryCts +\r
39308+ pAC->Pnmi.BufPort[1].ErrRecoveryCts;\r
39309+ }\r
39310+ }\r
39311+ else {\r
39312+ /* DualNet mode. */\r
39313+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
39314+ Val64 = pAC->Pnmi.Port[NetIndex].ErrRecoveryCts;\r
39315+ }\r
39316+ /* SingleNet mode. */\r
39317+ else {\r
39318+ Val64 = pAC->Pnmi.Port[0].ErrRecoveryCts +\r
39319+ pAC->Pnmi.Port[1].ErrRecoveryCts;\r
39320+ }\r
39321+ }\r
39322+ SK_PNMI_STORE_U64(pBuf, Val64);\r
39323+ *pLen = sizeof(SK_U64);\r
39324+ break;\r
39325+\r
39326+ case OID_SKGE_SYSUPTIME:\r
39327+ Val64 = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC));\r
39328+ Val64 -= pAC->Pnmi.StartUpTime;\r
39329+ SK_PNMI_STORE_U64(pBuf, Val64);\r
39330+ *pLen = sizeof(SK_U64);\r
39331+ break;\r
39332+\r
39333+ case OID_SKGE_MDB_VERSION:\r
39334+ Val32 = SK_PNMI_MDB_VERSION;\r
39335+ SK_PNMI_STORE_U32(pBuf, Val32);\r
39336+ *pLen = sizeof(SK_U32);\r
39337+ break;\r
39338+\r
39339+ case OID_GEN_RCV_ERROR:\r
39340+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */\r
39341+ if (MacType == SK_MAC_XMAC) {\r
39342+ Val64 = Val64RxHwErrs + pAC->Pnmi.BufPort[NetIndex].RxNoBufCts;\r
39343+ }\r
39344+ else {\r
39345+ Val64 = Val64RxHwErrs + pAC->Pnmi.Port[NetIndex].RxNoBufCts;\r
39346+ }\r
39347+\r
39348+ /*\r
39349+ * By default 32bit values are evaluated.\r
39350+ */\r
39351+ if (!Is64BitReq) {\r
39352+ Val32 = (SK_U32)Val64;\r
39353+ SK_PNMI_STORE_U32(pBuf, Val32);\r
39354+ *pLen = sizeof(SK_U32);\r
39355+ }\r
39356+ else {\r
39357+ SK_PNMI_STORE_U64(pBuf, Val64);\r
39358+ *pLen = sizeof(SK_U64);\r
39359+ }\r
39360+ break;\r
39361+\r
39362+ case OID_GEN_XMIT_ERROR:\r
39363+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */\r
39364+ if (MacType == SK_MAC_XMAC) {\r
39365+ Val64 = Val64TxHwErrs + pAC->Pnmi.BufPort[NetIndex].TxNoBufCts;\r
39366+ }\r
39367+ else {\r
39368+ Val64 = Val64TxHwErrs + pAC->Pnmi.Port[NetIndex].TxNoBufCts;\r
39369+ }\r
39370+\r
39371+ /*\r
39372+ * By default 32bit values are evaluated.\r
39373+ */\r
39374+ if (!Is64BitReq) {\r
39375+ Val32 = (SK_U32)Val64;\r
39376+ SK_PNMI_STORE_U32(pBuf, Val32);\r
39377+ *pLen = sizeof(SK_U32);\r
39378+ }\r
39379+ else {\r
39380+ SK_PNMI_STORE_U64(pBuf, Val64);\r
39381+ *pLen = sizeof(SK_U64);\r
39382+ }\r
39383+ break;\r
39384+\r
39385+ case OID_GEN_RCV_NO_BUFFER:\r
39386+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */\r
39387+ if (MacType == SK_MAC_XMAC) {\r
39388+ Val64 = pAC->Pnmi.BufPort[NetIndex].RxNoBufCts + \r
39389+ GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_OVERFLOW, NetIndex);\r
39390+\r
39391+ }\r
39392+ else {\r
39393+ Val64 = pAC->Pnmi.Port[NetIndex].RxNoBufCts +\r
39394+ GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_OVERFLOW, NetIndex);\r
39395+ }\r
39396+\r
39397+ /*\r
39398+ * By default 32bit values are evaluated.\r
39399+ */\r
39400+ if (!Is64BitReq) {\r
39401+ Val32 = (SK_U32)Val64;\r
39402+ SK_PNMI_STORE_U32(pBuf, Val32);\r
39403+ *pLen = sizeof(SK_U32);\r
39404+ }\r
39405+ else {\r
39406+ SK_PNMI_STORE_U64(pBuf, Val64);\r
39407+ *pLen = sizeof(SK_U64);\r
39408+ }\r
39409+ break;\r
39410+\r
39411+ case OID_GEN_TRANSMIT_QUEUE_LENGTH:\r
39412+ Val32 = (SK_U32)pAC->Pnmi.Port[NetIndex].TxSwQueueLen;\r
39413+ SK_PNMI_STORE_U32(pBuf, Val32);\r
39414+ *pLen = sizeof(SK_U32);\r
39415+ break;\r
39416+\r
39417+ default:\r
39418+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR034, SK_PNMI_ERR034MSG);\r
39419+\r
39420+ *pLen = 0;\r
39421+ return (SK_PNMI_ERR_GENERAL);\r
39422+ }\r
39423+\r
39424+ if (Id == OID_SKGE_RX_HW_ERROR_CTS ||\r
39425+ Id == OID_SKGE_TX_HW_ERROR_CTS ||\r
39426+ Id == OID_SKGE_IN_ERRORS_CTS ||\r
39427+ Id == OID_SKGE_OUT_ERROR_CTS ||\r
39428+ Id == OID_GEN_XMIT_ERROR ||\r
39429+ Id == OID_GEN_RCV_ERROR) {\r
39430+\r
39431+ pAC->Pnmi.MacUpdatedFlag --;\r
39432+ }\r
39433+\r
39434+ return (SK_PNMI_ERR_OK);\r
39435+}\r
39436+\r
39437+/*****************************************************************************\r
39438+ *\r
39439+ * Rlmt - OID handler function of OID_SKGE_RLMT_XXX single instance.\r
39440+ *\r
39441+ * Description:\r
39442+ * Get/Presets/Sets the RLMT OIDs.\r
39443+ *\r
39444+ * Returns:\r
39445+ * SK_PNMI_ERR_OK The request was successfully performed.\r
39446+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.\r
39447+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain\r
39448+ * the correct data (e.g. a 32bit value is\r
39449+ * needed, but a 16 bit value was passed).\r
39450+ * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid\r
39451+ * value range.\r
39452+ * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set.\r
39453+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't\r
39454+ * exist (e.g. port instance 3 on a two port\r
39455+ * adapter.\r
39456+ */\r
39457+PNMI_STATIC int Rlmt(\r
39458+SK_AC *pAC, /* Pointer to adapter context */\r
39459+SK_IOC IoC, /* IO context handle */\r
39460+int Action, /* GET/PRESET/SET action */\r
39461+SK_U32 Id, /* Object ID that is to be processed */\r
39462+char *pBuf, /* Buffer used for the management data transfer */\r
39463+unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */\r
39464+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */\r
39465+unsigned int TableIndex, /* Index to the Id table */\r
39466+SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */\r
39467+{\r
39468+ int Ret;\r
39469+ unsigned int PhysPortIndex;\r
39470+ unsigned int PhysPortMax;\r
39471+ SK_EVPARA EventParam;\r
39472+ SK_U32 Val32;\r
39473+ SK_U64 Val64;\r
39474+\r
39475+ /* Check instance. Only single instance OIDs are allowed here. */\r
39476+ if (Instance != (SK_U32)(-1) && Instance != 1) {\r
39477+\r
39478+ *pLen = 0;\r
39479+ return (SK_PNMI_ERR_UNKNOWN_INST);\r
39480+ }\r
39481+\r
39482+ /* Perform the requested action. */\r
39483+ if (Action == SK_PNMI_GET) {\r
39484+\r
39485+ /* Check if the buffer length is large enough. */\r
39486+ switch (Id) {\r
39487+\r
39488+ case OID_SKGE_RLMT_MODE:\r
39489+ case OID_SKGE_RLMT_PORT_ACTIVE:\r
39490+ case OID_SKGE_RLMT_PORT_PREFERRED:\r
39491+ if (*pLen < sizeof(SK_U8)) {\r
39492+\r
39493+ *pLen = sizeof(SK_U8);\r
39494+ return (SK_PNMI_ERR_TOO_SHORT);\r
39495+ }\r
39496+ break;\r
39497+\r
39498+ case OID_SKGE_RLMT_PORT_NUMBER:\r
39499+ if (*pLen < sizeof(SK_U32)) {\r
39500+\r
39501+ *pLen = sizeof(SK_U32);\r
39502+ return (SK_PNMI_ERR_TOO_SHORT);\r
39503+ }\r
39504+ break;\r
39505+\r
39506+ case OID_SKGE_RLMT_CHANGE_CTS:\r
39507+ case OID_SKGE_RLMT_CHANGE_TIME:\r
39508+ case OID_SKGE_RLMT_CHANGE_ESTIM:\r
39509+ case OID_SKGE_RLMT_CHANGE_THRES:\r
39510+ if (*pLen < sizeof(SK_U64)) {\r
39511+\r
39512+ *pLen = sizeof(SK_U64);\r
39513+ return (SK_PNMI_ERR_TOO_SHORT);\r
39514+ }\r
39515+ break;\r
39516+\r
39517+ default:\r
39518+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR035, SK_PNMI_ERR035MSG);\r
39519+\r
39520+ *pLen = 0;\r
39521+ return (SK_PNMI_ERR_GENERAL);\r
39522+ }\r
39523+\r
39524+ /*\r
39525+ * Update RLMT statistic and increment semaphores to indicate\r
39526+ * that an update was already done. Maybe RLMT will hold its\r
39527+ * statistic always up to date some time. Then we can\r
39528+ * remove this type of call.\r
39529+ */\r
39530+ if ((Ret = RlmtUpdate(pAC, IoC, NetIndex)) != SK_PNMI_ERR_OK) {\r
39531+\r
39532+ *pLen = 0;\r
39533+ return (Ret);\r
39534+ }\r
39535+ pAC->Pnmi.RlmtUpdatedFlag ++;\r
39536+\r
39537+ /* Retrieve value. */\r
39538+ switch (Id) {\r
39539+\r
39540+ case OID_SKGE_RLMT_MODE:\r
39541+ *pBuf = (char)pAC->Rlmt.Net[0].RlmtMode;\r
39542+ *pLen = sizeof(char);\r
39543+ break;\r
39544+\r
39545+ case OID_SKGE_RLMT_PORT_NUMBER:\r
39546+ Val32 = (SK_U32)pAC->GIni.GIMacsFound;\r
39547+ SK_PNMI_STORE_U32(pBuf, Val32);\r
39548+ *pLen = sizeof(SK_U32);\r
39549+ break;\r
39550+\r
39551+ case OID_SKGE_RLMT_PORT_ACTIVE:\r
39552+ *pBuf = 0;\r
39553+ /*\r
39554+ * If multiple ports may become active this OID\r
39555+ * doesn't make sense any more. A new variable in\r
39556+ * the port structure should be created. However,\r
39557+ * for this variable the first active port is\r
39558+ * returned.\r
39559+ */\r
39560+ PhysPortMax = pAC->GIni.GIMacsFound;\r
39561+\r
39562+ for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;\r
39563+ PhysPortIndex ++) {\r
39564+\r
39565+ if (pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {\r
39566+\r
39567+ *pBuf = (char)SK_PNMI_PORT_PHYS2LOG(PhysPortIndex);\r
39568+ break;\r
39569+ }\r
39570+ }\r
39571+ *pLen = sizeof(char);\r
39572+ break;\r
39573+\r
39574+ case OID_SKGE_RLMT_PORT_PREFERRED:\r
39575+ *pBuf = (char)SK_PNMI_PORT_PHYS2LOG(pAC->Rlmt.Net[NetIndex].Preference);\r
39576+ *pLen = sizeof(char);\r
39577+ break;\r
39578+\r
39579+ case OID_SKGE_RLMT_CHANGE_CTS:\r
39580+ Val64 = pAC->Pnmi.RlmtChangeCts;\r
39581+ SK_PNMI_STORE_U64(pBuf, Val64);\r
39582+ *pLen = sizeof(SK_U64);\r
39583+ break;\r
39584+\r
39585+ case OID_SKGE_RLMT_CHANGE_TIME:\r
39586+ Val64 = pAC->Pnmi.RlmtChangeTime;\r
39587+ SK_PNMI_STORE_U64(pBuf, Val64);\r
39588+ *pLen = sizeof(SK_U64);\r
39589+ break;\r
39590+\r
39591+ case OID_SKGE_RLMT_CHANGE_ESTIM:\r
39592+ Val64 = pAC->Pnmi.RlmtChangeEstimate.Estimate;\r
39593+ SK_PNMI_STORE_U64(pBuf, Val64);\r
39594+ *pLen = sizeof(SK_U64);\r
39595+ break;\r
39596+\r
39597+ case OID_SKGE_RLMT_CHANGE_THRES:\r
39598+ Val64 = pAC->Pnmi.RlmtChangeThreshold;\r
39599+ SK_PNMI_STORE_U64(pBuf, Val64);\r
39600+ *pLen = sizeof(SK_U64);\r
39601+ break;\r
39602+\r
39603+ default:\r
39604+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR,\r
39605+ ("Rlmt: Unknown OID should be handled before"));\r
39606+\r
39607+ pAC->Pnmi.RlmtUpdatedFlag --;\r
39608+ *pLen = 0;\r
39609+ return (SK_PNMI_ERR_GENERAL);\r
39610+ }\r
39611+\r
39612+ pAC->Pnmi.RlmtUpdatedFlag --;\r
39613+ }\r
39614+ else {\r
39615+ /* Perform a PRESET or SET. */\r
39616+ switch (Id) {\r
39617+\r
39618+ case OID_SKGE_RLMT_MODE:\r
39619+ /* Check if the buffer length is plausible. */\r
39620+ if (*pLen < sizeof(char)) {\r
39621+\r
39622+ *pLen = sizeof(char);\r
39623+ return (SK_PNMI_ERR_TOO_SHORT);\r
39624+ }\r
39625+ /* Check if the value range is correct. */\r
39626+ if (*pLen != sizeof(char) ||\r
39627+ (*pBuf & SK_PNMI_RLMT_MODE_CHK_LINK) == 0 ||\r
39628+ *(SK_U8 *)pBuf > 15) {\r
39629+\r
39630+ *pLen = 0;\r
39631+ return (SK_PNMI_ERR_BAD_VALUE);\r
39632+ }\r
39633+ /* The PRESET ends here. */\r
39634+ if (Action == SK_PNMI_PRESET) {\r
39635+\r
39636+ *pLen = 0;\r
39637+ return (SK_PNMI_ERR_OK);\r
39638+ }\r
39639+ /* Send an event to RLMT to change the mode. */\r
39640+ SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));\r
39641+ \r
39642+ EventParam.Para32[0] |= (SK_U32)(*pBuf);\r
39643+ EventParam.Para32[1] = 0;\r
39644+ if (SkRlmtEvent(pAC, IoC, SK_RLMT_MODE_CHANGE,\r
39645+ EventParam) > 0) {\r
39646+\r
39647+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR037, SK_PNMI_ERR037MSG);\r
39648+\r
39649+ *pLen = 0;\r
39650+ return (SK_PNMI_ERR_GENERAL);\r
39651+ }\r
39652+ break;\r
39653+\r
39654+ case OID_SKGE_RLMT_PORT_PREFERRED:\r
39655+ /* PRESET/SET action makes no sense in Dual Net mode. */\r
39656+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
39657+ break;\r
39658+ }\r
39659+ \r
39660+ /* Check if the buffer length is plausible. */\r
39661+ if (*pLen < sizeof(char)) {\r
39662+\r
39663+ *pLen = sizeof(char);\r
39664+ return (SK_PNMI_ERR_TOO_SHORT);\r
39665+ }\r
39666+ /* Check if the value range is correct. */\r
39667+ if (*pLen != sizeof(char) || *(SK_U8 *)pBuf >\r
39668+ (SK_U8)pAC->GIni.GIMacsFound) {\r
39669+\r
39670+ *pLen = 0;\r
39671+ return (SK_PNMI_ERR_BAD_VALUE);\r
39672+ }\r
39673+ /* The PRESET ends here. */\r
39674+ if (Action == SK_PNMI_PRESET) {\r
39675+\r
39676+ *pLen = 0;\r
39677+ return (SK_PNMI_ERR_OK);\r
39678+ }\r
39679+\r
39680+ /*\r
39681+ * Send an event to RLMT change the preferred port.\r
39682+ * A param of -1 means automatic mode. RLMT will\r
39683+ * make the decision which is the preferred port.\r
39684+ */\r
39685+ SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));\r
39686+ \r
39687+ EventParam.Para32[0] = (SK_U32)(*pBuf) - 1;\r
39688+ EventParam.Para32[1] = NetIndex;\r
39689+ if (SkRlmtEvent(pAC, IoC, SK_RLMT_PREFPORT_CHANGE,\r
39690+ EventParam) > 0) {\r
39691+\r
39692+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR038, SK_PNMI_ERR038MSG);\r
39693+\r
39694+ *pLen = 0;\r
39695+ return (SK_PNMI_ERR_GENERAL);\r
39696+ }\r
39697+ break;\r
39698+\r
39699+ case OID_SKGE_RLMT_CHANGE_THRES:\r
39700+ /* Check if the buffer length is plausible. */\r
39701+ if (*pLen < sizeof(SK_U64)) {\r
39702+\r
39703+ *pLen = sizeof(SK_U64);\r
39704+ return (SK_PNMI_ERR_TOO_SHORT);\r
39705+ }\r
39706+ \r
39707+ /* There are not many restrictions to the value range. */\r
39708+ if (*pLen != sizeof(SK_U64)) {\r
39709+\r
39710+ *pLen = 0;\r
39711+ return (SK_PNMI_ERR_BAD_VALUE);\r
39712+ }\r
39713+ /* The PRESET ends here. */\r
39714+ if (Action == SK_PNMI_PRESET) {\r
39715+\r
39716+ *pLen = 0;\r
39717+ return (SK_PNMI_ERR_OK);\r
39718+ }\r
39719+ /*\r
39720+ * Store the new threshold, which will be taken\r
39721+ * on the next timer event.\r
39722+ */\r
39723+ SK_PNMI_READ_U64(pBuf, Val64);\r
39724+ pAC->Pnmi.RlmtChangeThreshold = Val64;\r
39725+ break;\r
39726+\r
39727+ default:\r
39728+ /* The other OIDs are not be able for set. */\r
39729+ *pLen = 0;\r
39730+ return (SK_PNMI_ERR_READ_ONLY);\r
39731+ }\r
39732+ }\r
39733+\r
39734+ return (SK_PNMI_ERR_OK);\r
39735+}\r
39736+\r
39737+/*****************************************************************************\r
39738+ *\r
39739+ * RlmtStat - OID handler function of OID_SKGE_RLMT_XXX multiple instance.\r
39740+ *\r
39741+ * Description:\r
39742+ * Performs get requests on multiple instance variables.\r
39743+ *\r
39744+ * Returns:\r
39745+ * SK_PNMI_ERR_OK The request was successfully performed.\r
39746+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.\r
39747+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain\r
39748+ * the correct data (e.g. a 32bit value is\r
39749+ * needed, but a 16 bit value was passed).\r
39750+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't\r
39751+ * exist (e.g. port instance 3 on a two port\r
39752+ * adapter.\r
39753+ */\r
39754+PNMI_STATIC int RlmtStat(\r
39755+SK_AC *pAC, /* Pointer to adapter context */\r
39756+SK_IOC IoC, /* IO context handle */\r
39757+int Action, /* GET/PRESET/SET action */\r
39758+SK_U32 Id, /* Object ID that is to be processed */\r
39759+char *pBuf, /* Buffer used for the management data transfer */\r
39760+unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */\r
39761+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */\r
39762+unsigned int TableIndex, /* Index to the Id table */\r
39763+SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */\r
39764+{\r
39765+ unsigned int PhysPortMax;\r
39766+ unsigned int PhysPortIndex;\r
39767+ unsigned int Limit;\r
39768+ unsigned int Offset;\r
39769+ int Ret;\r
39770+ SK_U32 Val32;\r
39771+ SK_U64 Val64;\r
39772+\r
39773+\r
39774+ /* Calculate the port indexes from the instance. */\r
39775+ PhysPortMax = pAC->GIni.GIMacsFound;\r
39776+\r
39777+ if ((Instance != (SK_U32)(-1))) {\r
39778+ /* Check instance range. */\r
39779+ if ((Instance < 1) || (Instance > PhysPortMax)) {\r
39780+\r
39781+ *pLen = 0;\r
39782+ return (SK_PNMI_ERR_UNKNOWN_INST);\r
39783+ }\r
39784+\r
39785+ /* SingleNet mode. */\r
39786+ PhysPortIndex = Instance - 1;\r
39787+\r
39788+ /* DualNet mode. */\r
39789+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
39790+ PhysPortIndex = NetIndex;\r
39791+ }\r
39792+\r
39793+ /* Both net modes. */\r
39794+ Limit = PhysPortIndex + 1;\r
39795+ }\r
39796+ else {\r
39797+ /* SingleNet mode. */\r
39798+ PhysPortIndex = 0;\r
39799+ Limit = PhysPortMax;\r
39800+\r
39801+ /* DualNet mode. */\r
39802+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
39803+ PhysPortIndex = NetIndex;\r
39804+ Limit = PhysPortIndex + 1;\r
39805+ }\r
39806+ }\r
39807+\r
39808+ /* Currently only GET requests are allowed. */\r
39809+ if (Action != SK_PNMI_GET) {\r
39810+\r
39811+ *pLen = 0;\r
39812+ return (SK_PNMI_ERR_READ_ONLY);\r
39813+ }\r
39814+\r
39815+ /* Check if the buffer length is large enough. */\r
39816+ switch (Id) {\r
39817+\r
39818+ case OID_SKGE_RLMT_PORT_INDEX:\r
39819+ case OID_SKGE_RLMT_STATUS:\r
39820+ if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U32)) {\r
39821+\r
39822+ *pLen = (Limit - PhysPortIndex) * sizeof(SK_U32);\r
39823+ return (SK_PNMI_ERR_TOO_SHORT);\r
39824+ }\r
39825+ break;\r
39826+\r
39827+ case OID_SKGE_RLMT_TX_HELLO_CTS:\r
39828+ case OID_SKGE_RLMT_RX_HELLO_CTS:\r
39829+ case OID_SKGE_RLMT_TX_SP_REQ_CTS:\r
39830+ case OID_SKGE_RLMT_RX_SP_CTS:\r
39831+ if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U64)) {\r
39832+\r
39833+ *pLen = (Limit - PhysPortIndex) * sizeof(SK_U64);\r
39834+ return (SK_PNMI_ERR_TOO_SHORT);\r
39835+ }\r
39836+ break;\r
39837+\r
39838+ default:\r
39839+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR039, SK_PNMI_ERR039MSG);\r
39840+\r
39841+ *pLen = 0;\r
39842+ return (SK_PNMI_ERR_GENERAL);\r
39843+\r
39844+ }\r
39845+\r
39846+ /*\r
39847+ * Update statistic and increment semaphores to indicate that\r
39848+ * an update was already done.\r
39849+ */\r
39850+ if ((Ret = RlmtUpdate(pAC, IoC, NetIndex)) != SK_PNMI_ERR_OK) {\r
39851+\r
39852+ *pLen = 0;\r
39853+ return (Ret);\r
39854+ }\r
39855+ pAC->Pnmi.RlmtUpdatedFlag ++;\r
39856+\r
39857+ /* Get value. */\r
39858+ Offset = 0;\r
39859+ for (; PhysPortIndex < Limit; PhysPortIndex ++) {\r
39860+\r
39861+ switch (Id) {\r
39862+\r
39863+ case OID_SKGE_RLMT_PORT_INDEX:\r
39864+ Val32 = PhysPortIndex;\r
39865+ SK_PNMI_STORE_U32(pBuf + Offset, Val32);\r
39866+ Offset += sizeof(SK_U32);\r
39867+ break;\r
39868+\r
39869+ case OID_SKGE_RLMT_STATUS:\r
39870+ if (pAC->Rlmt.Port[PhysPortIndex].PortState ==\r
39871+ SK_RLMT_PS_INIT ||\r
39872+ pAC->Rlmt.Port[PhysPortIndex].PortState ==\r
39873+ SK_RLMT_PS_DOWN) {\r
39874+\r
39875+ Val32 = SK_PNMI_RLMT_STATUS_ERROR;\r
39876+ }\r
39877+ else if (pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {\r
39878+\r
39879+ Val32 = SK_PNMI_RLMT_STATUS_ACTIVE;\r
39880+ }\r
39881+ else {\r
39882+ Val32 = SK_PNMI_RLMT_STATUS_STANDBY;\r
39883+ }\r
39884+ SK_PNMI_STORE_U32(pBuf + Offset, Val32);\r
39885+ Offset += sizeof(SK_U32);\r
39886+ break;\r
39887+\r
39888+ case OID_SKGE_RLMT_TX_HELLO_CTS:\r
39889+ Val64 = pAC->Rlmt.Port[PhysPortIndex].TxHelloCts;\r
39890+ SK_PNMI_STORE_U64(pBuf + Offset, Val64);\r
39891+ Offset += sizeof(SK_U64);\r
39892+ break;\r
39893+\r
39894+ case OID_SKGE_RLMT_RX_HELLO_CTS:\r
39895+ Val64 = pAC->Rlmt.Port[PhysPortIndex].RxHelloCts;\r
39896+ SK_PNMI_STORE_U64(pBuf + Offset, Val64);\r
39897+ Offset += sizeof(SK_U64);\r
39898+ break;\r
39899+\r
39900+ case OID_SKGE_RLMT_TX_SP_REQ_CTS:\r
39901+ Val64 = pAC->Rlmt.Port[PhysPortIndex].TxSpHelloReqCts;\r
39902+ SK_PNMI_STORE_U64(pBuf + Offset, Val64);\r
39903+ Offset += sizeof(SK_U64);\r
39904+ break;\r
39905+\r
39906+ case OID_SKGE_RLMT_RX_SP_CTS:\r
39907+ Val64 = pAC->Rlmt.Port[PhysPortIndex].RxSpHelloCts;\r
39908+ SK_PNMI_STORE_U64(pBuf + Offset, Val64);\r
39909+ Offset += sizeof(SK_U64);\r
39910+ break;\r
39911+\r
39912+ default:\r
39913+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR,\r
39914+ ("RlmtStat: Unknown OID should be errored before"));\r
39915+\r
39916+ pAC->Pnmi.RlmtUpdatedFlag --;\r
39917+ *pLen = 0;\r
39918+ return (SK_PNMI_ERR_GENERAL);\r
39919+ }\r
39920+ }\r
39921+ *pLen = Offset;\r
39922+\r
39923+ pAC->Pnmi.RlmtUpdatedFlag --;\r
39924+\r
39925+ return (SK_PNMI_ERR_OK);\r
39926+}\r
39927+\r
39928+/*****************************************************************************\r
39929+ *\r
39930+ * MacPrivateConf - OID handler function of OIDs concerning the configuration\r
39931+ *\r
39932+ * Description:\r
39933+ * Get/Presets/Sets the OIDs concerning the configuration.\r
39934+ *\r
39935+ * Returns:\r
39936+ * SK_PNMI_ERR_OK The request was successfully performed.\r
39937+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.\r
39938+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain\r
39939+ * the correct data (e.g. a 32bit value is\r
39940+ * needed, but a 16 bit value was passed).\r
39941+ * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid\r
39942+ * value range.\r
39943+ * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set.\r
39944+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't\r
39945+ * exist (e.g. port instance 3 on a two port\r
39946+ * adapter.\r
39947+ */\r
39948+PNMI_STATIC int MacPrivateConf(\r
39949+SK_AC *pAC, /* Pointer to adapter context */\r
39950+SK_IOC IoC, /* IO context handle */\r
39951+int Action, /* GET/PRESET/SET action */\r
39952+SK_U32 Id, /* Object ID that is to be processed */\r
39953+char *pBuf, /* Buffer used for the management data transfer */\r
39954+unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */\r
39955+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */\r
39956+unsigned int TableIndex, /* Index to the Id table */\r
39957+SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */\r
39958+{\r
39959+ unsigned int PhysPortMax;\r
39960+ unsigned int PhysPortIndex;\r
39961+ unsigned int LogPortMax;\r
39962+ unsigned int LogPortIndex;\r
39963+ unsigned int Limit;\r
39964+ unsigned int Offset;\r
39965+ char Val8;\r
39966+ char *pBufPtr;\r
39967+ int Ret;\r
39968+ SK_EVPARA EventParam;\r
39969+ SK_U32 Val32;\r
39970+#ifdef SK_PHY_LP_MODE\r
39971+ SK_U8 CurrentPhyPowerState;\r
39972+#endif /* SK_PHY_LP_MODE */\r
39973+\r
39974+\r
39975+ /* Calculate instance if wished. MAC index 0 is the virtual MAC. */\r
39976+ PhysPortMax = pAC->GIni.GIMacsFound;\r
39977+ LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax);\r
39978+\r
39979+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* DualNet mode. */\r
39980+ LogPortMax--;\r
39981+ }\r
39982+\r
39983+ if ((Instance != (SK_U32)(-1))) { /* Only one specific instance is queried. */\r
39984+ /* Check instance range. */\r
39985+ if ((Instance < 1) || (Instance > LogPortMax)) {\r
39986+\r
39987+ *pLen = 0;\r
39988+ return (SK_PNMI_ERR_UNKNOWN_INST);\r
39989+ }\r
39990+ LogPortIndex = SK_PNMI_PORT_INST2LOG(Instance);\r
39991+ Limit = LogPortIndex + 1;\r
39992+ }\r
39993+\r
39994+ else { /* Instance == (SK_U32)(-1), get all Instances of that OID. */\r
39995+\r
39996+ LogPortIndex = 0;\r
39997+ Limit = LogPortMax;\r
39998+ }\r
39999+\r
40000+ /* Perform action. */\r
40001+ if (Action == SK_PNMI_GET) {\r
40002+\r
40003+ /* Check length. */\r
40004+ switch (Id) {\r
40005+\r
40006+ case OID_SKGE_PMD:\r
40007+ case OID_SKGE_CONNECTOR:\r
40008+ case OID_SKGE_LINK_CAP:\r
40009+ case OID_SKGE_LINK_MODE:\r
40010+ case OID_SKGE_LINK_MODE_STATUS:\r
40011+ case OID_SKGE_LINK_STATUS:\r
40012+ case OID_SKGE_FLOWCTRL_CAP:\r
40013+ case OID_SKGE_FLOWCTRL_MODE:\r
40014+ case OID_SKGE_FLOWCTRL_STATUS:\r
40015+ case OID_SKGE_PHY_OPERATION_CAP:\r
40016+ case OID_SKGE_PHY_OPERATION_MODE:\r
40017+ case OID_SKGE_PHY_OPERATION_STATUS:\r
40018+ case OID_SKGE_SPEED_CAP:\r
40019+ case OID_SKGE_SPEED_MODE:\r
40020+ case OID_SKGE_SPEED_STATUS:\r
40021+#ifdef SK_PHY_LP_MODE\r
40022+ case OID_SKGE_PHY_LP_MODE:\r
40023+#endif\r
40024+ if (*pLen < (Limit - LogPortIndex) * sizeof(SK_U8)) {\r
40025+\r
40026+ *pLen = (Limit - LogPortIndex) * sizeof(SK_U8);\r
40027+ return (SK_PNMI_ERR_TOO_SHORT);\r
40028+ }\r
40029+ break;\r
40030+\r
40031+ case OID_SKGE_MTU:\r
40032+ case OID_SKGE_PHY_TYPE:\r
40033+ if (*pLen < (Limit - LogPortIndex) * sizeof(SK_U32)) {\r
40034+\r
40035+ *pLen = (Limit - LogPortIndex) * sizeof(SK_U32);\r
40036+ return (SK_PNMI_ERR_TOO_SHORT);\r
40037+ }\r
40038+ break;\r
40039+\r
40040+ default:\r
40041+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR041, SK_PNMI_ERR041MSG);\r
40042+ *pLen = 0;\r
40043+ return (SK_PNMI_ERR_GENERAL);\r
40044+ }\r
40045+\r
40046+ /*\r
40047+ * Update statistic and increment semaphore to indicate\r
40048+ * that an update was already done.\r
40049+ */\r
40050+ if ((Ret = SirqUpdate(pAC, IoC)) != SK_PNMI_ERR_OK) {\r
40051+\r
40052+ *pLen = 0;\r
40053+ return (Ret);\r
40054+ }\r
40055+ pAC->Pnmi.SirqUpdatedFlag ++;\r
40056+\r
40057+ /* Get value. */\r
40058+ Offset = 0;\r
40059+ for (; LogPortIndex < Limit; LogPortIndex ++) {\r
40060+\r
40061+ pBufPtr = pBuf + Offset;\r
40062+ \r
40063+ switch (Id) {\r
40064+\r
40065+ case OID_SKGE_PMD:\r
40066+ *pBufPtr = pAC->Pnmi.PMD;\r
40067+ Offset ++;\r
40068+ break;\r
40069+\r
40070+ case OID_SKGE_CONNECTOR:\r
40071+ *pBufPtr = pAC->Pnmi.Connector;\r
40072+ Offset ++;\r
40073+ break;\r
40074+\r
40075+ case OID_SKGE_PHY_TYPE:\r
40076+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */\r
40077+ if (LogPortIndex == 0) {\r
40078+ continue;\r
40079+ }\r
40080+ /* Get value for physical port. */\r
40081+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);\r
40082+ Val32 = pAC->GIni.GP[PhysPortIndex].PhyType;\r
40083+ }\r
40084+ else { /* DualNet mode. */\r
40085+ \r
40086+ Val32 = pAC->GIni.GP[NetIndex].PhyType;\r
40087+ }\r
40088+ SK_PNMI_STORE_U32(pBufPtr, Val32);\r
40089+ Offset += sizeof(SK_U32);\r
40090+ break;\r
40091+\r
40092+#ifdef SK_PHY_LP_MODE\r
40093+ case OID_SKGE_PHY_LP_MODE:\r
40094+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */\r
40095+ if (LogPortIndex == 0) {\r
40096+ continue;\r
40097+ }\r
40098+ /* Get value for physical port. */\r
40099+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);\r
40100+ *pBufPtr = (SK_U8)pAC->GIni.GP[PhysPortIndex].PPhyPowerState;\r
40101+ }\r
40102+ else { /* DualNet mode. */\r
40103+ \r
40104+ *pBufPtr = (SK_U8)pAC->GIni.GP[NetIndex].PPhyPowerState;\r
40105+ }\r
40106+ Offset += sizeof(SK_U8);\r
40107+ break;\r
40108+#endif\r
40109+\r
40110+ case OID_SKGE_LINK_CAP:\r
40111+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */\r
40112+ if (LogPortIndex == 0) {\r
40113+ /* Get value for virtual port. */\r
40114+ VirtualConf(pAC, IoC, Id, pBufPtr);\r
40115+ }\r
40116+ else {\r
40117+ /* Get value for physical port. */\r
40118+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(\r
40119+ pAC, LogPortIndex);\r
40120+\r
40121+ *pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkCap;\r
40122+ }\r
40123+ }\r
40124+ else { /* DualNet mode. */\r
40125+ \r
40126+ *pBufPtr = pAC->GIni.GP[NetIndex].PLinkCap;\r
40127+ }\r
40128+ Offset ++;\r
40129+ break;\r
40130+\r
40131+ case OID_SKGE_LINK_MODE:\r
40132+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */\r
40133+ if (LogPortIndex == 0) {\r
40134+ /* Get value for virtual port. */\r
40135+ VirtualConf(pAC, IoC, Id, pBufPtr);\r
40136+ }\r
40137+ else {\r
40138+ /* Get value for physical port. */\r
40139+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(\r
40140+ pAC, LogPortIndex);\r
40141+\r
40142+ *pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkModeConf;\r
40143+ }\r
40144+ }\r
40145+ else { /* DualNet mode. */\r
40146+ \r
40147+ *pBufPtr = pAC->GIni.GP[NetIndex].PLinkModeConf;\r
40148+ }\r
40149+ Offset ++;\r
40150+ break;\r
40151+\r
40152+ case OID_SKGE_LINK_MODE_STATUS:\r
40153+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */\r
40154+ if (LogPortIndex == 0) {\r
40155+ /* Get value for virtual port. */\r
40156+ VirtualConf(pAC, IoC, Id, pBufPtr);\r
40157+ }\r
40158+ else {\r
40159+ /* Get value for physical port. */\r
40160+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(\r
40161+ pAC, LogPortIndex);\r
40162+\r
40163+ *pBufPtr =\r
40164+ CalculateLinkModeStatus(pAC, IoC, PhysPortIndex);\r
40165+ }\r
40166+ }\r
40167+ else { /* DualNet mode. */\r
40168+ \r
40169+ *pBufPtr = CalculateLinkModeStatus(pAC, IoC, NetIndex);\r
40170+ }\r
40171+ Offset ++;\r
40172+ break;\r
40173+\r
40174+ case OID_SKGE_LINK_STATUS:\r
40175+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */\r
40176+ if (LogPortIndex == 0) {\r
40177+ /* Get value for virtual port. */\r
40178+ VirtualConf(pAC, IoC, Id, pBufPtr);\r
40179+ }\r
40180+ else {\r
40181+ /* Get value for physical port. */\r
40182+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(\r
40183+ pAC, LogPortIndex);\r
40184+ \r
40185+ *pBufPtr = CalculateLinkStatus(pAC, IoC, PhysPortIndex);\r
40186+ }\r
40187+ }\r
40188+ else { /* DualNet mode. */\r
40189+\r
40190+ *pBufPtr = CalculateLinkStatus(pAC, IoC, NetIndex);\r
40191+ }\r
40192+ Offset ++;\r
40193+ break;\r
40194+\r
40195+ case OID_SKGE_FLOWCTRL_CAP:\r
40196+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */\r
40197+ if (LogPortIndex == 0) {\r
40198+ /* Get value for virtual port. */\r
40199+ VirtualConf(pAC, IoC, Id, pBufPtr);\r
40200+ }\r
40201+ else {\r
40202+ /* Get value for physical port. */\r
40203+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(\r
40204+ pAC, LogPortIndex);\r
40205+ \r
40206+ *pBufPtr = pAC->GIni.GP[PhysPortIndex].PFlowCtrlCap;\r
40207+ }\r
40208+ }\r
40209+ else { /* DualNet mode. */\r
40210+ \r
40211+ *pBufPtr = pAC->GIni.GP[NetIndex].PFlowCtrlCap;\r
40212+ }\r
40213+ Offset ++;\r
40214+ break;\r
40215+\r
40216+ case OID_SKGE_FLOWCTRL_MODE:\r
40217+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */\r
40218+ if (LogPortIndex == 0) {\r
40219+ /* Get value for virtual port. */\r
40220+ VirtualConf(pAC, IoC, Id, pBufPtr);\r
40221+ }\r
40222+ else {\r
40223+ /* Get value for physical port. */\r
40224+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(\r
40225+ pAC, LogPortIndex);\r
40226+ \r
40227+ *pBufPtr = pAC->GIni.GP[PhysPortIndex].PFlowCtrlMode;\r
40228+ }\r
40229+ }\r
40230+ else { /* DualNet mode. */\r
40231+\r
40232+ *pBufPtr = pAC->GIni.GP[NetIndex].PFlowCtrlMode;\r
40233+ }\r
40234+ Offset ++;\r
40235+ break;\r
40236+\r
40237+ case OID_SKGE_FLOWCTRL_STATUS:\r
40238+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */\r
40239+ if (LogPortIndex == 0) {\r
40240+ /* Get value for virtual port. */\r
40241+ VirtualConf(pAC, IoC, Id, pBufPtr);\r
40242+ }\r
40243+ else {\r
40244+ /* Get value for physical port. */\r
40245+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(\r
40246+ pAC, LogPortIndex);\r
40247+ \r
40248+ *pBufPtr = pAC->GIni.GP[PhysPortIndex].PFlowCtrlStatus;\r
40249+ }\r
40250+ }\r
40251+ else { /* DualNet mode. */\r
40252+\r
40253+ *pBufPtr = pAC->GIni.GP[NetIndex].PFlowCtrlStatus;\r
40254+ }\r
40255+ Offset ++;\r
40256+ break;\r
40257+\r
40258+ case OID_SKGE_PHY_OPERATION_CAP:\r
40259+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet Mode. */\r
40260+ if (LogPortIndex == 0) {\r
40261+ /* Get value for virtual port. */\r
40262+ VirtualConf(pAC, IoC, Id, pBufPtr);\r
40263+ }\r
40264+ else {\r
40265+ /* Get value for physical port. */\r
40266+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(\r
40267+ pAC, LogPortIndex);\r
40268+ \r
40269+ *pBufPtr = pAC->GIni.GP[PhysPortIndex].PMSCap;\r
40270+ }\r
40271+ }\r
40272+ else { /* DualNet mode. */\r
40273+ \r
40274+ *pBufPtr = pAC->GIni.GP[NetIndex].PMSCap;\r
40275+ }\r
40276+ Offset ++;\r
40277+ break;\r
40278+\r
40279+ case OID_SKGE_PHY_OPERATION_MODE:\r
40280+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */\r
40281+ if (LogPortIndex == 0) {\r
40282+ /* Get value for virtual port. */\r
40283+ VirtualConf(pAC, IoC, Id, pBufPtr);\r
40284+ }\r
40285+ else {\r
40286+ /* Get value for physical port. */\r
40287+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(\r
40288+ pAC, LogPortIndex);\r
40289+\r
40290+ *pBufPtr = pAC->GIni.GP[PhysPortIndex].PMSMode;\r
40291+ }\r
40292+ }\r
40293+ else { /* DualNet mode. */\r
40294+ \r
40295+ *pBufPtr = pAC->GIni.GP[NetIndex].PMSMode;\r
40296+ }\r
40297+ Offset ++;\r
40298+ break;\r
40299+\r
40300+ case OID_SKGE_PHY_OPERATION_STATUS:\r
40301+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */\r
40302+ if (LogPortIndex == 0) {\r
40303+ /* Get value for virtual port. */\r
40304+ VirtualConf(pAC, IoC, Id, pBufPtr);\r
40305+ }\r
40306+ else {\r
40307+ /* Get value for physical port. */\r
40308+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(\r
40309+ pAC, LogPortIndex);\r
40310+ \r
40311+ *pBufPtr = pAC->GIni.GP[PhysPortIndex].PMSStatus;\r
40312+ }\r
40313+ }\r
40314+ else {\r
40315+ \r
40316+ *pBufPtr = pAC->GIni.GP[NetIndex].PMSStatus;\r
40317+ }\r
40318+ Offset ++;\r
40319+ break;\r
40320+\r
40321+ case OID_SKGE_SPEED_CAP:\r
40322+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */\r
40323+ if (LogPortIndex == 0) {\r
40324+ /* Get value for virtual port. */\r
40325+ VirtualConf(pAC, IoC, Id, pBufPtr);\r
40326+ }\r
40327+ else {\r
40328+ /* Get value for physical port. */\r
40329+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(\r
40330+ pAC, LogPortIndex);\r
40331+ \r
40332+ *pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkSpeedCap;\r
40333+ }\r
40334+ }\r
40335+ else { /* DualNet mode. */\r
40336+ \r
40337+ *pBufPtr = pAC->GIni.GP[NetIndex].PLinkSpeedCap;\r
40338+ }\r
40339+ Offset ++;\r
40340+ break;\r
40341+\r
40342+ case OID_SKGE_SPEED_MODE:\r
40343+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */\r
40344+ if (LogPortIndex == 0) {\r
40345+ /* Get value for virtual port. */\r
40346+ VirtualConf(pAC, IoC, Id, pBufPtr);\r
40347+ }\r
40348+ else {\r
40349+ /* Get value for physical port. */\r
40350+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(\r
40351+ pAC, LogPortIndex);\r
40352+ \r
40353+ *pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkSpeed;\r
40354+ }\r
40355+ }\r
40356+ else { /* DualNet mode. */\r
40357+\r
40358+ *pBufPtr = pAC->GIni.GP[NetIndex].PLinkSpeed;\r
40359+ }\r
40360+ Offset ++;\r
40361+ break;\r
40362+\r
40363+ case OID_SKGE_SPEED_STATUS:\r
40364+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */\r
40365+ if (LogPortIndex == 0) {\r
40366+ /* Get value for virtual port. */\r
40367+ VirtualConf(pAC, IoC, Id, pBufPtr);\r
40368+ }\r
40369+ else {\r
40370+ /* Get value for physical port. */\r
40371+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(\r
40372+ pAC, LogPortIndex);\r
40373+ \r
40374+ *pBufPtr = pAC->GIni.GP[PhysPortIndex].PLinkSpeedUsed;\r
40375+ }\r
40376+ }\r
40377+ else { /* DualNet mode. */\r
40378+\r
40379+ *pBufPtr = pAC->GIni.GP[NetIndex].PLinkSpeedUsed;\r
40380+ }\r
40381+ Offset ++;\r
40382+ break;\r
40383+ \r
40384+ case OID_SKGE_MTU:\r
40385+ Val32 = SK_DRIVER_GET_MTU(pAC, IoC, NetIndex);\r
40386+ SK_PNMI_STORE_U32(pBufPtr, Val32);\r
40387+ Offset += sizeof(SK_U32);\r
40388+ break;\r
40389+\r
40390+ default:\r
40391+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR,\r
40392+ ("MacPrivateConf: Unknown OID should be handled before"));\r
40393+\r
40394+ pAC->Pnmi.SirqUpdatedFlag --;\r
40395+ return (SK_PNMI_ERR_GENERAL);\r
40396+ }\r
40397+ }\r
40398+ *pLen = Offset;\r
40399+ pAC->Pnmi.SirqUpdatedFlag --;\r
40400+\r
40401+ return (SK_PNMI_ERR_OK);\r
40402+ }\r
40403+\r
40404+ /*\r
40405+ * From here SET or PRESET action. Check if the passed\r
40406+ * buffer length is plausible.\r
40407+ */\r
40408+ switch (Id) {\r
40409+\r
40410+ case OID_SKGE_LINK_MODE:\r
40411+ case OID_SKGE_FLOWCTRL_MODE:\r
40412+ case OID_SKGE_PHY_OPERATION_MODE:\r
40413+ case OID_SKGE_SPEED_MODE:\r
40414+ if (*pLen < Limit - LogPortIndex) {\r
40415+\r
40416+ *pLen = Limit - LogPortIndex;\r
40417+ return (SK_PNMI_ERR_TOO_SHORT);\r
40418+ }\r
40419+ if (*pLen != Limit - LogPortIndex) {\r
40420+\r
40421+ *pLen = 0;\r
40422+ return (SK_PNMI_ERR_BAD_VALUE);\r
40423+ }\r
40424+ break;\r
40425+\r
40426+#ifdef SK_PHY_LP_MODE\r
40427+ case OID_SKGE_PHY_LP_MODE:\r
40428+ if (*pLen < Limit - LogPortIndex) {\r
40429+\r
40430+ *pLen = Limit - LogPortIndex;\r
40431+ return (SK_PNMI_ERR_TOO_SHORT);\r
40432+ }\r
40433+ break;\r
40434+#endif /* SK_PHY_LP_MODE */\r
40435+\r
40436+ case OID_SKGE_MTU:\r
40437+ if (*pLen < (Limit - LogPortIndex) * sizeof(SK_U32)) {\r
40438+\r
40439+ *pLen = (Limit - LogPortIndex) * sizeof(SK_U32);\r
40440+ return (SK_PNMI_ERR_TOO_SHORT);\r
40441+ }\r
40442+ break;\r
40443+ \r
40444+ default:\r
40445+ *pLen = 0;\r
40446+ return (SK_PNMI_ERR_READ_ONLY);\r
40447+ }\r
40448+\r
40449+ /* Perform PRESET or SET. */\r
40450+ Offset = 0;\r
40451+ for (; LogPortIndex < Limit; LogPortIndex ++) {\r
40452+\r
40453+ Val8 = *(pBuf + Offset);\r
40454+\r
40455+ switch (Id) {\r
40456+\r
40457+ case OID_SKGE_LINK_MODE:\r
40458+ /* Check the value range. */\r
40459+ if (Val8 == 0) {\r
40460+ Offset++;\r
40461+ break;\r
40462+ }\r
40463+ if (Val8 < SK_LMODE_HALF ||\r
40464+ (LogPortIndex != 0 && Val8 > SK_LMODE_AUTOSENSE) ||\r
40465+ (LogPortIndex == 0 && Val8 > SK_LMODE_INDETERMINATED)) {\r
40466+\r
40467+ *pLen = 0;\r
40468+ return (SK_PNMI_ERR_BAD_VALUE);\r
40469+ }\r
40470+\r
40471+ /* The PRESET ends here. */\r
40472+ if (Action == SK_PNMI_PRESET) {\r
40473+\r
40474+ return (SK_PNMI_ERR_OK);\r
40475+ }\r
40476+\r
40477+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */\r
40478+ if (LogPortIndex == 0) {\r
40479+ /*\r
40480+ * The virtual port consists of all currently\r
40481+ * active ports. Find them and send an event\r
40482+ * with the new link mode to SIRQ.\r
40483+ */\r
40484+ for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;\r
40485+ PhysPortIndex ++) {\r
40486+\r
40487+ if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {\r
40488+ continue;\r
40489+ }\r
40490+ \r
40491+ EventParam.Para32[0] = PhysPortIndex;\r
40492+ EventParam.Para32[1] = (SK_U32)Val8;\r
40493+ if (SkGeSirqEvent(pAC, IoC,\r
40494+ SK_HWEV_SET_LMODE,\r
40495+ EventParam) > 0) {\r
40496+ \r
40497+ SK_ERR_LOG(pAC, SK_ERRCL_SW,\r
40498+ SK_PNMI_ERR043,\r
40499+ SK_PNMI_ERR043MSG);\r
40500+ \r
40501+ *pLen = 0;\r
40502+ return (SK_PNMI_ERR_GENERAL);\r
40503+ }\r
40504+ } /* for */\r
40505+ }\r
40506+ else {\r
40507+ /*\r
40508+ * Send an event with the new link mode to\r
40509+ * the SIRQ module.\r
40510+ */\r
40511+ EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(\r
40512+ pAC, LogPortIndex);\r
40513+ EventParam.Para32[1] = (SK_U32)Val8;\r
40514+ if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_LMODE,\r
40515+ EventParam) > 0) {\r
40516+ \r
40517+ SK_ERR_LOG(pAC, SK_ERRCL_SW,\r
40518+ SK_PNMI_ERR043,\r
40519+ SK_PNMI_ERR043MSG);\r
40520+ \r
40521+ *pLen = 0;\r
40522+ return (SK_PNMI_ERR_GENERAL);\r
40523+ }\r
40524+ }\r
40525+ }\r
40526+ else { /* DualNet mode. */\r
40527+\r
40528+ /*\r
40529+ * Send an event with the new link mode to\r
40530+ * the SIRQ module.\r
40531+ */\r
40532+ EventParam.Para32[0] = NetIndex;\r
40533+ EventParam.Para32[1] = (SK_U32)Val8;\r
40534+ if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_LMODE,\r
40535+ EventParam) > 0) {\r
40536+\r
40537+ SK_ERR_LOG(pAC, SK_ERRCL_SW,\r
40538+ SK_PNMI_ERR043,\r
40539+ SK_PNMI_ERR043MSG);\r
40540+\r
40541+ *pLen = 0;\r
40542+ return (SK_PNMI_ERR_GENERAL);\r
40543+ }\r
40544+ }\r
40545+ Offset++;\r
40546+ break;\r
40547+\r
40548+ case OID_SKGE_FLOWCTRL_MODE:\r
40549+ /* Check the value range. */\r
40550+ if (Val8 == 0) {\r
40551+ Offset++;\r
40552+ break;\r
40553+ }\r
40554+ if (Val8 < SK_FLOW_MODE_NONE ||\r
40555+ (LogPortIndex != 0 && Val8 > SK_FLOW_MODE_SYM_OR_REM) ||\r
40556+ (LogPortIndex == 0 && Val8 > SK_FLOW_MODE_INDETERMINATED)) {\r
40557+\r
40558+ *pLen = 0;\r
40559+ return (SK_PNMI_ERR_BAD_VALUE);\r
40560+ }\r
40561+\r
40562+ /* The PRESET ends here. */\r
40563+ if (Action == SK_PNMI_PRESET) {\r
40564+\r
40565+ return (SK_PNMI_ERR_OK);\r
40566+ }\r
40567+\r
40568+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */\r
40569+ if (LogPortIndex == 0) {\r
40570+ /*\r
40571+ * The virtual port consists of all currently\r
40572+ * active ports. Find them and send an event\r
40573+ * with the new flow control mode to SIRQ.\r
40574+ */\r
40575+ for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;\r
40576+ PhysPortIndex ++) {\r
40577+\r
40578+ if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {\r
40579+ continue;\r
40580+ }\r
40581+\r
40582+ EventParam.Para32[0] = PhysPortIndex;\r
40583+ EventParam.Para32[1] = (SK_U32)Val8;\r
40584+ if (SkGeSirqEvent(pAC, IoC,\r
40585+ SK_HWEV_SET_FLOWMODE,\r
40586+ EventParam) > 0) {\r
40587+\r
40588+ SK_ERR_LOG(pAC, SK_ERRCL_SW,\r
40589+ SK_PNMI_ERR044,\r
40590+ SK_PNMI_ERR044MSG);\r
40591+\r
40592+ *pLen = 0;\r
40593+ return (SK_PNMI_ERR_GENERAL);\r
40594+ }\r
40595+ }\r
40596+ }\r
40597+ else {\r
40598+ /*\r
40599+ * Send an event with the new flow control\r
40600+ * mode to the SIRQ module.\r
40601+ */\r
40602+ EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(\r
40603+ pAC, LogPortIndex);\r
40604+ EventParam.Para32[1] = (SK_U32)Val8;\r
40605+ if (SkGeSirqEvent(pAC, IoC,\r
40606+ SK_HWEV_SET_FLOWMODE,\r
40607+ EventParam) > 0) {\r
40608+\r
40609+ SK_ERR_LOG(pAC, SK_ERRCL_SW,\r
40610+ SK_PNMI_ERR044,\r
40611+ SK_PNMI_ERR044MSG);\r
40612+\r
40613+ *pLen = 0;\r
40614+ return (SK_PNMI_ERR_GENERAL);\r
40615+ }\r
40616+ }\r
40617+ }\r
40618+ else { /* DualNet mode. */\r
40619+ \r
40620+ /*\r
40621+ * Send an event with the new link mode to\r
40622+ * the SIRQ module.\r
40623+ */\r
40624+ EventParam.Para32[0] = NetIndex;\r
40625+ EventParam.Para32[1] = (SK_U32)Val8;\r
40626+ if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_FLOWMODE,\r
40627+ EventParam) > 0) {\r
40628+\r
40629+ SK_ERR_LOG(pAC, SK_ERRCL_SW,\r
40630+ SK_PNMI_ERR044,\r
40631+ SK_PNMI_ERR044MSG);\r
40632+\r
40633+ *pLen = 0;\r
40634+ return (SK_PNMI_ERR_GENERAL);\r
40635+ }\r
40636+ }\r
40637+ Offset++;\r
40638+ break;\r
40639+\r
40640+ case OID_SKGE_PHY_OPERATION_MODE :\r
40641+ /* Check the value range. */\r
40642+ if (Val8 == 0) {\r
40643+ /* Mode of this port remains unchanged. */\r
40644+ Offset++;\r
40645+ break;\r
40646+ }\r
40647+ if (Val8 < SK_MS_MODE_AUTO ||\r
40648+ (LogPortIndex != 0 && Val8 > SK_MS_MODE_SLAVE) ||\r
40649+ (LogPortIndex == 0 && Val8 > SK_MS_MODE_INDETERMINATED)) {\r
40650+\r
40651+ *pLen = 0;\r
40652+ return (SK_PNMI_ERR_BAD_VALUE);\r
40653+ }\r
40654+\r
40655+ /* The PRESET ends here. */\r
40656+ if (Action == SK_PNMI_PRESET) {\r
40657+\r
40658+ return (SK_PNMI_ERR_OK);\r
40659+ }\r
40660+\r
40661+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */\r
40662+ if (LogPortIndex == 0) {\r
40663+ /*\r
40664+ * The virtual port consists of all currently\r
40665+ * active ports. Find them and send an event\r
40666+ * with new master/slave (role) mode to SIRQ.\r
40667+ */\r
40668+ for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;\r
40669+ PhysPortIndex ++) {\r
40670+\r
40671+ if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {\r
40672+ continue;\r
40673+ }\r
40674+\r
40675+ EventParam.Para32[0] = PhysPortIndex;\r
40676+ EventParam.Para32[1] = (SK_U32)Val8;\r
40677+ if (SkGeSirqEvent(pAC, IoC,\r
40678+ SK_HWEV_SET_ROLE,\r
40679+ EventParam) > 0) {\r
40680+\r
40681+ SK_ERR_LOG(pAC, SK_ERRCL_SW,\r
40682+ SK_PNMI_ERR042,\r
40683+ SK_PNMI_ERR042MSG);\r
40684+\r
40685+ *pLen = 0;\r
40686+ return (SK_PNMI_ERR_GENERAL);\r
40687+ }\r
40688+ }\r
40689+ }\r
40690+ else {\r
40691+ /*\r
40692+ * Send an event with the new master/slave\r
40693+ * (role) mode to the SIRQ module.\r
40694+ */\r
40695+ EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(\r
40696+ pAC, LogPortIndex);\r
40697+ EventParam.Para32[1] = (SK_U32)Val8;\r
40698+ if (SkGeSirqEvent(pAC, IoC,\r
40699+ SK_HWEV_SET_ROLE, EventParam) > 0) {\r
40700+\r
40701+ SK_ERR_LOG(pAC, SK_ERRCL_SW,\r
40702+ SK_PNMI_ERR042,\r
40703+ SK_PNMI_ERR042MSG);\r
40704+\r
40705+ *pLen = 0;\r
40706+ return (SK_PNMI_ERR_GENERAL);\r
40707+ }\r
40708+ }\r
40709+ }\r
40710+ else { /* DualNet mode. */\r
40711+\r
40712+ /*\r
40713+ * Send an event with the new link mode to\r
40714+ * the SIRQ module.\r
40715+ */\r
40716+ EventParam.Para32[0] = NetIndex;\r
40717+ EventParam.Para32[1] = (SK_U32)Val8;\r
40718+ if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_ROLE,\r
40719+ EventParam) > 0) {\r
40720+\r
40721+ SK_ERR_LOG(pAC, SK_ERRCL_SW,\r
40722+ SK_PNMI_ERR042,\r
40723+ SK_PNMI_ERR042MSG);\r
40724+\r
40725+ *pLen = 0;\r
40726+ return (SK_PNMI_ERR_GENERAL);\r
40727+ }\r
40728+ }\r
40729+ Offset++;\r
40730+ break;\r
40731+\r
40732+ case OID_SKGE_SPEED_MODE:\r
40733+ /* Check the value range. */\r
40734+ if (Val8 == 0) {\r
40735+ Offset++;\r
40736+ break;\r
40737+ }\r
40738+ if (Val8 < (SK_LSPEED_AUTO) ||\r
40739+ (LogPortIndex != 0 && Val8 > (SK_LSPEED_1000MBPS)) ||\r
40740+ (LogPortIndex == 0 && Val8 > (SK_LSPEED_INDETERMINATED))) {\r
40741+\r
40742+ *pLen = 0;\r
40743+ return (SK_PNMI_ERR_BAD_VALUE);\r
40744+ }\r
40745+\r
40746+ /* The PRESET ends here. */\r
40747+ if (Action == SK_PNMI_PRESET) {\r
40748+\r
40749+ return (SK_PNMI_ERR_OK);\r
40750+ }\r
40751+\r
40752+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */\r
40753+ if (LogPortIndex == 0) {\r
40754+\r
40755+ /*\r
40756+ * The virtual port consists of all currently\r
40757+ * active ports. Find them and send an event\r
40758+ * with the new flow control mode to SIRQ.\r
40759+ */\r
40760+ for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;\r
40761+ PhysPortIndex ++) {\r
40762+\r
40763+ if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {\r
40764+ continue;\r
40765+ }\r
40766+\r
40767+ EventParam.Para32[0] = PhysPortIndex;\r
40768+ EventParam.Para32[1] = (SK_U32)Val8;\r
40769+ if (SkGeSirqEvent(pAC, IoC,\r
40770+ SK_HWEV_SET_SPEED,\r
40771+ EventParam) > 0) {\r
40772+\r
40773+ SK_ERR_LOG(pAC, SK_ERRCL_SW,\r
40774+ SK_PNMI_ERR045,\r
40775+ SK_PNMI_ERR045MSG);\r
40776+\r
40777+ *pLen = 0;\r
40778+ return (SK_PNMI_ERR_GENERAL);\r
40779+ }\r
40780+ }\r
40781+ }\r
40782+ else {\r
40783+ /*\r
40784+ * Send an event with the new flow control\r
40785+ * mode to the SIRQ module.\r
40786+ */\r
40787+ EventParam.Para32[0] = SK_PNMI_PORT_LOG2PHYS(\r
40788+ pAC, LogPortIndex);\r
40789+ EventParam.Para32[1] = (SK_U32)Val8;\r
40790+ if (SkGeSirqEvent(pAC, IoC,\r
40791+ SK_HWEV_SET_SPEED,\r
40792+ EventParam) > 0) {\r
40793+\r
40794+ SK_ERR_LOG(pAC, SK_ERRCL_SW,\r
40795+ SK_PNMI_ERR045,\r
40796+ SK_PNMI_ERR045MSG);\r
40797+\r
40798+ *pLen = 0;\r
40799+ return (SK_PNMI_ERR_GENERAL);\r
40800+ }\r
40801+ }\r
40802+ }\r
40803+ else { /* DualNet mode. */\r
40804+ \r
40805+ /*\r
40806+ * Send an event with the new link mode to\r
40807+ * the SIRQ module.\r
40808+ */\r
40809+ EventParam.Para32[0] = NetIndex;\r
40810+ EventParam.Para32[1] = (SK_U32)Val8;\r
40811+ if (SkGeSirqEvent(pAC, IoC, SK_HWEV_SET_SPEED,\r
40812+ EventParam) > 0) {\r
40813+\r
40814+ SK_ERR_LOG(pAC, SK_ERRCL_SW,\r
40815+ SK_PNMI_ERR045,\r
40816+ SK_PNMI_ERR045MSG);\r
40817+\r
40818+ *pLen = 0;\r
40819+ return (SK_PNMI_ERR_GENERAL);\r
40820+ }\r
40821+ }\r
40822+ Offset++;\r
40823+ break;\r
40824+\r
40825+ case OID_SKGE_MTU:\r
40826+ /* Check the value range. */\r
40827+ SK_PNMI_READ_U32((pBuf + Offset), Val32);\r
40828+\r
40829+ if (Val32 == 0) {\r
40830+ /* MTU of this port remains unchanged. */\r
40831+ Offset += sizeof(SK_U32);\r
40832+ break;\r
40833+ }\r
40834+\r
40835+ if (SK_DRIVER_PRESET_MTU(pAC, IoC, NetIndex, Val32) != 0) {\r
40836+ *pLen = 0;\r
40837+ return (SK_PNMI_ERR_BAD_VALUE);\r
40838+ }\r
40839+\r
40840+ /* The PRESET ends here. */\r
40841+ if (Action == SK_PNMI_PRESET) {\r
40842+ return (SK_PNMI_ERR_OK);\r
40843+ }\r
40844+\r
40845+ if (SK_DRIVER_SET_MTU(pAC, IoC, NetIndex, Val32) != 0) {\r
40846+ return (SK_PNMI_ERR_GENERAL);\r
40847+ }\r
40848+\r
40849+ Offset += sizeof(SK_U32);\r
40850+ break;\r
40851+\r
40852+#ifdef SK_PHY_LP_MODE\r
40853+ case OID_SKGE_PHY_LP_MODE:\r
40854+ /* The PRESET ends here. */\r
40855+ if (Action == SK_PNMI_PRESET) {\r
40856+\r
40857+ return (SK_PNMI_ERR_OK);\r
40858+ }\r
40859+\r
40860+ if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNet mode. */\r
40861+ if (LogPortIndex == 0) {\r
40862+ Offset = 0;\r
40863+ continue;\r
40864+ }\r
40865+ }\r
40866+ /* Set value for physical port. */\r
40867+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);\r
40868+ CurrentPhyPowerState = pAC->GIni.GP[PhysPortIndex].PPhyPowerState;\r
40869+\r
40870+ switch (Val8) {\r
40871+ case PHY_PM_OPERATIONAL_MODE:\r
40872+ /* If LowPowerMode is active, we can leave it. */\r
40873+ if (CurrentPhyPowerState) {\r
40874+\r
40875+ Val32 = SkGmLeaveLowPowerMode(pAC, IoC, PhysPortIndex);\r
40876+ \r
40877+ if ((CurrentPhyPowerState == PHY_PM_DEEP_SLEEP) ||\r
40878+ (CurrentPhyPowerState == PHY_PM_IEEE_POWER_DOWN)) {\r
40879+ \r
40880+ SkDrvInitAdapter(pAC);\r
40881+ }\r
40882+ break;\r
40883+ }\r
40884+ else {\r
40885+ *pLen = 0;\r
40886+ return (SK_PNMI_ERR_GENERAL);\r
40887+ }\r
40888+ case PHY_PM_DEEP_SLEEP:\r
40889+ case PHY_PM_IEEE_POWER_DOWN:\r
40890+ /* If no LowPowerMode is active, we can enter it. */\r
40891+ if (!CurrentPhyPowerState) {\r
40892+ SkDrvDeInitAdapter(pAC);\r
40893+ }\r
40894+\r
40895+ case PHY_PM_ENERGY_DETECT:\r
40896+ case PHY_PM_ENERGY_DETECT_PLUS:\r
40897+ /* If no LowPowerMode is active, we can enter it. */\r
40898+ if (!CurrentPhyPowerState) {\r
40899+\r
40900+ Val32 = SkGmEnterLowPowerMode(pAC, IoC, PhysPortIndex, *pBuf);\r
40901+ break;\r
40902+ }\r
40903+ else {\r
40904+ *pLen = 0;\r
40905+ return (SK_PNMI_ERR_GENERAL);\r
40906+ }\r
40907+ default:\r
40908+ *pLen = 0;\r
40909+ return (SK_PNMI_ERR_BAD_VALUE);\r
40910+ }\r
40911+ Offset++;\r
40912+ break;\r
40913+#endif /* SK_PHY_LP_MODE */\r
40914+\r
40915+ default:\r
40916+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR,\r
40917+ ("MacPrivateConf: Unknown OID should be handled before set"));\r
40918+\r
40919+ *pLen = 0;\r
40920+ return (SK_PNMI_ERR_GENERAL);\r
40921+ }\r
40922+ }\r
40923+\r
40924+ return (SK_PNMI_ERR_OK);\r
40925+}\r
40926+\r
40927+/*****************************************************************************\r
40928+ *\r
40929+ * Monitor - OID handler function for RLMT_MONITOR_XXX\r
40930+ *\r
40931+ * Description:\r
40932+ * Because RLMT currently does not support the monitoring of\r
40933+ * remote adapter cards, we return always an empty table.\r
40934+ *\r
40935+ * Returns:\r
40936+ * SK_PNMI_ERR_OK The request was successfully performed.\r
40937+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.\r
40938+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain\r
40939+ * the correct data (e.g. a 32bit value is\r
40940+ * needed, but a 16 bit value was passed).\r
40941+ * SK_PNMI_ERR_BAD_VALUE The passed value is not in the valid\r
40942+ * value range.\r
40943+ * SK_PNMI_ERR_READ_ONLY The OID is read-only and cannot be set.\r
40944+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't\r
40945+ * exist (e.g. port instance 3 on a two port\r
40946+ * adapter.\r
40947+ */\r
40948+PNMI_STATIC int Monitor(\r
40949+SK_AC *pAC, /* Pointer to adapter context */\r
40950+SK_IOC IoC, /* IO context handle */\r
40951+int Action, /* GET/PRESET/SET action */\r
40952+SK_U32 Id, /* Object ID that is to be processed */\r
40953+char *pBuf, /* Buffer used for the management data transfer */\r
40954+unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */\r
40955+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */\r
40956+unsigned int TableIndex, /* Index to the Id table */\r
40957+SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */\r
40958+{\r
40959+ unsigned int Index;\r
40960+ unsigned int Limit;\r
40961+ unsigned int Offset;\r
40962+ unsigned int Entries;\r
40963+ \r
40964+ /* Not implemented yet. Return always an empty table. */\r
40965+ Entries = 0;\r
40966+\r
40967+ /* Calculate instance if wished. */\r
40968+ if ((Instance != (SK_U32)(-1))) {\r
40969+\r
40970+ if ((Instance < 1) || (Instance > Entries)) {\r
40971+\r
40972+ *pLen = 0;\r
40973+ return (SK_PNMI_ERR_UNKNOWN_INST);\r
40974+ }\r
40975+\r
40976+ Index = (unsigned int)Instance - 1;\r
40977+ Limit = (unsigned int)Instance;\r
40978+ }\r
40979+ else {\r
40980+ Index = 0;\r
40981+ Limit = Entries;\r
40982+ }\r
40983+\r
40984+ /* GET/SET value. */\r
40985+ if (Action == SK_PNMI_GET) {\r
40986+\r
40987+ for (Offset = 0; Index < Limit; Index ++) {\r
40988+\r
40989+ switch (Id) {\r
40990+\r
40991+ case OID_SKGE_RLMT_MONITOR_INDEX:\r
40992+ case OID_SKGE_RLMT_MONITOR_ADDR:\r
40993+ case OID_SKGE_RLMT_MONITOR_ERRS:\r
40994+ case OID_SKGE_RLMT_MONITOR_TIMESTAMP:\r
40995+ case OID_SKGE_RLMT_MONITOR_ADMIN:\r
40996+ break;\r
40997+\r
40998+ default:\r
40999+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR046,\r
41000+ SK_PNMI_ERR046MSG);\r
41001+\r
41002+ *pLen = 0;\r
41003+ return (SK_PNMI_ERR_GENERAL);\r
41004+ }\r
41005+ }\r
41006+ *pLen = Offset;\r
41007+ }\r
41008+ else {\r
41009+ /* Only MONITOR_ADMIN can be set. */\r
41010+ if (Id != OID_SKGE_RLMT_MONITOR_ADMIN) {\r
41011+\r
41012+ *pLen = 0;\r
41013+ return (SK_PNMI_ERR_READ_ONLY);\r
41014+ }\r
41015+\r
41016+ /* Check if the length is plausible. */\r
41017+ if (*pLen < (Limit - Index)) {\r
41018+\r
41019+ return (SK_PNMI_ERR_TOO_SHORT);\r
41020+ }\r
41021+ /* Okay, we have a wide value range. */\r
41022+ if (*pLen != (Limit - Index)) {\r
41023+\r
41024+ *pLen = 0;\r
41025+ return (SK_PNMI_ERR_BAD_VALUE);\r
41026+ }\r
41027+\r
41028+ /*\r
41029+ * Not yet implemented. Return always BAD_VALUE,\r
41030+ * because the table is empty.\r
41031+ */\r
41032+ *pLen = 0;\r
41033+ return (SK_PNMI_ERR_BAD_VALUE);\r
41034+ }\r
41035+\r
41036+ return (SK_PNMI_ERR_OK);\r
41037+}\r
41038+\r
41039+/*****************************************************************************\r
41040+ *\r
41041+ * VirtualConf - Calculates the values of configuration OIDs for virtual port\r
41042+ *\r
41043+ * Description:\r
41044+ * We handle here the get of the configuration group OIDs, which are\r
41045+ * a little bit complicated. The virtual port consists of all currently\r
41046+ * active physical ports. If multiple ports are active and configured\r
41047+ * differently we get in some trouble to return a single value. So we\r
41048+ * get the value of the first active port and compare it with that of\r
41049+ * the other active ports. If they are not the same, we return a value\r
41050+ * that indicates that the state is indeterminated.\r
41051+ *\r
41052+ * Returns:\r
41053+ * Nothing\r
41054+ */\r
41055+PNMI_STATIC void VirtualConf(\r
41056+SK_AC *pAC, /* Pointer to adapter context */\r
41057+SK_IOC IoC, /* IO context handle */\r
41058+SK_U32 Id, /* Object ID that is to be processed */\r
41059+char *pBuf) /* Buffer used for the management data transfer */\r
41060+{\r
41061+ unsigned int PhysPortMax;\r
41062+ unsigned int PhysPortIndex;\r
41063+ SK_U8 Val8;\r
41064+ SK_U32 Val32;\r
41065+ SK_BOOL PortActiveFlag;\r
41066+ SK_GEPORT *pPrt;\r
41067+\r
41068+ *pBuf = 0;\r
41069+ PortActiveFlag = SK_FALSE;\r
41070+ PhysPortMax = pAC->GIni.GIMacsFound;\r
41071+ \r
41072+ for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax; PhysPortIndex ++) {\r
41073+\r
41074+ pPrt = &pAC->GIni.GP[PhysPortIndex];\r
41075+\r
41076+ /* Check if the physical port is active. */\r
41077+ if (!pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {\r
41078+ continue;\r
41079+ }\r
41080+\r
41081+ PortActiveFlag = SK_TRUE;\r
41082+\r
41083+ switch (Id) {\r
41084+\r
41085+ case OID_SKGE_PHY_TYPE:\r
41086+ /* Check if it is the first active port. */\r
41087+ if (*pBuf == 0) {\r
41088+ Val32 = pPrt->PhyType;\r
41089+ SK_PNMI_STORE_U32(pBuf, Val32);\r
41090+ continue;\r
41091+ }\r
41092+ break;\r
41093+\r
41094+ case OID_SKGE_LINK_CAP:\r
41095+\r
41096+ /*\r
41097+ * Different capabilities should not happen, but\r
41098+ * in the case of the cases OR them all together.\r
41099+ * From a curious point of view the virtual port\r
41100+ * is capable of all found capabilities.\r
41101+ */\r
41102+ *pBuf |= pPrt->PLinkCap;\r
41103+ break;\r
41104+\r
41105+ case OID_SKGE_LINK_MODE:\r
41106+ /* Check if it is the first active port. */\r
41107+ if (*pBuf == 0) {\r
41108+\r
41109+ *pBuf = pPrt->PLinkModeConf;\r
41110+ continue;\r
41111+ }\r
41112+\r
41113+ /*\r
41114+ * If we find an active port with a different link mode\r
41115+ * than the first one we return indeterminated.\r
41116+ */\r
41117+ if (*pBuf != pPrt->PLinkModeConf) {\r
41118+\r
41119+ *pBuf = SK_LMODE_INDETERMINATED;\r
41120+ }\r
41121+ break;\r
41122+\r
41123+ case OID_SKGE_LINK_MODE_STATUS:\r
41124+ /* Get the link mode of the physical port. */\r
41125+ Val8 = CalculateLinkModeStatus(pAC, IoC, PhysPortIndex);\r
41126+\r
41127+ /* Check if it is the first active port. */\r
41128+ if (*pBuf == 0) {\r
41129+\r
41130+ *pBuf = Val8;\r
41131+ continue;\r
41132+ }\r
41133+\r
41134+ /*\r
41135+ * If we find an active port with a different link mode status\r
41136+ * than the first one we return indeterminated.\r
41137+ */\r
41138+ if (*pBuf != Val8) {\r
41139+\r
41140+ *pBuf = SK_LMODE_STAT_INDETERMINATED;\r
41141+ }\r
41142+ break;\r
41143+\r
41144+ case OID_SKGE_LINK_STATUS:\r
41145+ /* Get the link status of the physical port. */\r
41146+ Val8 = CalculateLinkStatus(pAC, IoC, PhysPortIndex);\r
41147+\r
41148+ /* Check if it is the first active port. */\r
41149+ if (*pBuf == 0) {\r
41150+\r
41151+ *pBuf = Val8;\r
41152+ continue;\r
41153+ }\r
41154+\r
41155+ /*\r
41156+ * If we find an active port with a different link status\r
41157+ * than the first one we return indeterminated.\r
41158+ */\r
41159+ if (*pBuf != Val8) {\r
41160+\r
41161+ *pBuf = SK_PNMI_RLMT_LSTAT_INDETERMINATED;\r
41162+ }\r
41163+ break;\r
41164+\r
41165+ case OID_SKGE_FLOWCTRL_CAP:\r
41166+ /* Check if it is the first active port. */\r
41167+ if (*pBuf == 0) {\r
41168+\r
41169+ *pBuf = pPrt->PFlowCtrlCap;\r
41170+ continue;\r
41171+ }\r
41172+\r
41173+ /*\r
41174+ * From a curious point of view the virtual port\r
41175+ * is capable of all found capabilities.\r
41176+ */\r
41177+ *pBuf |= pPrt->PFlowCtrlCap;\r
41178+ break;\r
41179+\r
41180+ case OID_SKGE_FLOWCTRL_MODE:\r
41181+ /* Check if it is the first active port. */\r
41182+ if (*pBuf == 0) {\r
41183+\r
41184+ *pBuf = pPrt->PFlowCtrlMode;\r
41185+ continue;\r
41186+ }\r
41187+\r
41188+ /*\r
41189+ * If we find an active port with a different flow-control mode\r
41190+ * than the first one we return indeterminated.\r
41191+ */\r
41192+ if (*pBuf != pPrt->PFlowCtrlMode) {\r
41193+\r
41194+ *pBuf = SK_FLOW_MODE_INDETERMINATED;\r
41195+ }\r
41196+ break;\r
41197+\r
41198+ case OID_SKGE_FLOWCTRL_STATUS:\r
41199+ /* Check if it is the first active port. */\r
41200+ if (*pBuf == 0) {\r
41201+\r
41202+ *pBuf = pPrt->PFlowCtrlStatus;\r
41203+ continue;\r
41204+ }\r
41205+\r
41206+ /*\r
41207+ * If we find an active port with a different flow-control status\r
41208+ * than the first one we return indeterminated.\r
41209+ */\r
41210+ if (*pBuf != pPrt->PFlowCtrlStatus) {\r
41211+\r
41212+ *pBuf = SK_FLOW_STAT_INDETERMINATED;\r
41213+ }\r
41214+ break;\r
41215+ \r
41216+ case OID_SKGE_PHY_OPERATION_CAP:\r
41217+ /* Check if it is the first active port. */\r
41218+ if (*pBuf == 0) {\r
41219+\r
41220+ *pBuf = pPrt->PMSCap;\r
41221+ continue;\r
41222+ }\r
41223+\r
41224+ /*\r
41225+ * From a curious point of view the virtual port\r
41226+ * is capable of all found capabilities.\r
41227+ */\r
41228+ *pBuf |= pPrt->PMSCap;\r
41229+ break;\r
41230+\r
41231+ case OID_SKGE_PHY_OPERATION_MODE:\r
41232+ /* Check if it is the first active port. */\r
41233+ if (*pBuf == 0) {\r
41234+\r
41235+ *pBuf = pPrt->PMSMode;\r
41236+ continue;\r
41237+ }\r
41238+\r
41239+ /*\r
41240+ * If we find an active port with a different master/slave mode\r
41241+ * than the first one we return indeterminated.\r
41242+ */\r
41243+ if (*pBuf != pPrt->PMSMode) {\r
41244+\r
41245+ *pBuf = SK_MS_MODE_INDETERMINATED;\r
41246+ }\r
41247+ break;\r
41248+\r
41249+ case OID_SKGE_PHY_OPERATION_STATUS:\r
41250+ /* Check if it is the first active port. */\r
41251+ if (*pBuf == 0) {\r
41252+\r
41253+ *pBuf = pPrt->PMSStatus;\r
41254+ continue;\r
41255+ }\r
41256+\r
41257+ /*\r
41258+ * If we find an active port with a different master/slave status\r
41259+ * than the first one we return indeterminated.\r
41260+ */\r
41261+ if (*pBuf != pPrt->PMSStatus) {\r
41262+\r
41263+ *pBuf = SK_MS_STAT_INDETERMINATED;\r
41264+ }\r
41265+ break;\r
41266+ \r
41267+ case OID_SKGE_SPEED_MODE:\r
41268+ /* Check if it is the first active port. */\r
41269+ if (*pBuf == 0) {\r
41270+\r
41271+ *pBuf = pPrt->PLinkSpeed;\r
41272+ continue;\r
41273+ }\r
41274+\r
41275+ /*\r
41276+ * If we find an active port with a different link speed\r
41277+ * than the first one we return indeterminated.\r
41278+ */\r
41279+ if (*pBuf != pPrt->PLinkSpeed) {\r
41280+\r
41281+ *pBuf = SK_LSPEED_INDETERMINATED;\r
41282+ }\r
41283+ break;\r
41284+ \r
41285+ case OID_SKGE_SPEED_STATUS:\r
41286+ /* Check if it is the first active port. */\r
41287+ if (*pBuf == 0) {\r
41288+\r
41289+ *pBuf = pPrt->PLinkSpeedUsed;\r
41290+ continue;\r
41291+ }\r
41292+\r
41293+ /*\r
41294+ * If we find an active port with a different link speed used\r
41295+ * than the first one we return indeterminated.\r
41296+ */\r
41297+ if (*pBuf != pPrt->PLinkSpeedUsed) {\r
41298+\r
41299+ *pBuf = SK_LSPEED_STAT_INDETERMINATED;\r
41300+ }\r
41301+ break;\r
41302+ }\r
41303+ }\r
41304+\r
41305+ /* If no port is active return an indeterminated answer. */\r
41306+ if (!PortActiveFlag) {\r
41307+\r
41308+ switch (Id) {\r
41309+\r
41310+ case OID_SKGE_LINK_CAP:\r
41311+ *pBuf = SK_LMODE_CAP_INDETERMINATED;\r
41312+ break;\r
41313+\r
41314+ case OID_SKGE_LINK_MODE:\r
41315+ *pBuf = SK_LMODE_INDETERMINATED;\r
41316+ break;\r
41317+\r
41318+ case OID_SKGE_LINK_MODE_STATUS:\r
41319+ *pBuf = SK_LMODE_STAT_INDETERMINATED;\r
41320+ break;\r
41321+\r
41322+ case OID_SKGE_LINK_STATUS:\r
41323+ *pBuf = SK_PNMI_RLMT_LSTAT_INDETERMINATED;\r
41324+ break;\r
41325+\r
41326+ case OID_SKGE_FLOWCTRL_CAP:\r
41327+ case OID_SKGE_FLOWCTRL_MODE:\r
41328+ *pBuf = SK_FLOW_MODE_INDETERMINATED;\r
41329+ break;\r
41330+\r
41331+ case OID_SKGE_FLOWCTRL_STATUS:\r
41332+ *pBuf = SK_FLOW_STAT_INDETERMINATED;\r
41333+ break;\r
41334+ \r
41335+ case OID_SKGE_PHY_OPERATION_CAP:\r
41336+ *pBuf = SK_MS_CAP_INDETERMINATED;\r
41337+ break;\r
41338+\r
41339+ case OID_SKGE_PHY_OPERATION_MODE:\r
41340+ *pBuf = SK_MS_MODE_INDETERMINATED;\r
41341+ break;\r
41342+\r
41343+ case OID_SKGE_PHY_OPERATION_STATUS:\r
41344+ *pBuf = SK_MS_STAT_INDETERMINATED;\r
41345+ break;\r
41346+ case OID_SKGE_SPEED_CAP:\r
41347+ *pBuf = SK_LSPEED_CAP_INDETERMINATED;\r
41348+ break;\r
41349+\r
41350+ case OID_SKGE_SPEED_MODE:\r
41351+ *pBuf = SK_LSPEED_INDETERMINATED;\r
41352+ break;\r
41353+\r
41354+ case OID_SKGE_SPEED_STATUS:\r
41355+ *pBuf = SK_LSPEED_STAT_INDETERMINATED;\r
41356+ break;\r
41357+ }\r
41358+ }\r
41359+}\r
41360+\r
41361+/*****************************************************************************\r
41362+ *\r
41363+ * CalculateLinkStatus - Determins the link status of a physical port\r
41364+ *\r
41365+ * Description:\r
41366+ * Determins the link status the following way:\r
41367+ * LSTAT_PHY_DOWN: Link is down\r
41368+ * LSTAT_AUTONEG: Auto-negotiation failed\r
41369+ * LSTAT_LOG_DOWN: Link is up but RLMT did not yet put the port\r
41370+ * logically up.\r
41371+ * LSTAT_LOG_UP: RLMT marked the port as up\r
41372+ *\r
41373+ * Returns:\r
41374+ * Link status of physical port\r
41375+ */\r
41376+PNMI_STATIC SK_U8 CalculateLinkStatus(\r
41377+SK_AC *pAC, /* Pointer to adapter context */\r
41378+SK_IOC IoC, /* IO context handle */\r
41379+unsigned int PhysPortIndex) /* Physical port index */\r
41380+{\r
41381+ SK_U8 Result;\r
41382+\r
41383+ if (!pAC->GIni.GP[PhysPortIndex].PHWLinkUp) {\r
41384+\r
41385+ Result = SK_PNMI_RLMT_LSTAT_PHY_DOWN;\r
41386+ }\r
41387+ else if (pAC->GIni.GP[PhysPortIndex].PAutoNegFail > 0) {\r
41388+\r
41389+ Result = SK_PNMI_RLMT_LSTAT_AUTONEG;\r
41390+ }\r
41391+ else if (!pAC->Rlmt.Port[PhysPortIndex].PortDown) {\r
41392+\r
41393+ Result = SK_PNMI_RLMT_LSTAT_LOG_UP;\r
41394+ }\r
41395+ else {\r
41396+ Result = SK_PNMI_RLMT_LSTAT_LOG_DOWN;\r
41397+ }\r
41398+\r
41399+ return (Result);\r
41400+}\r
41401+\r
41402+/*****************************************************************************\r
41403+ *\r
41404+ * CalculateLinkModeStatus - Determins the link mode status of a phys. port\r
41405+ *\r
41406+ * Description:\r
41407+ * The COMMON module only tells us if the mode is half or full duplex.\r
41408+ * But in the decade of auto sensing it is usefull for the user to\r
41409+ * know if the mode was negotiated or forced. Therefore we have a\r
41410+ * look to the mode, which was last used by the negotiation process.\r
41411+ *\r
41412+ * Returns:\r
41413+ * The link mode status\r
41414+ */\r
41415+PNMI_STATIC SK_U8 CalculateLinkModeStatus(\r
41416+SK_AC *pAC, /* Pointer to adapter context */\r
41417+SK_IOC IoC, /* IO context handle */\r
41418+unsigned int PhysPortIndex) /* Physical port index */\r
41419+{\r
41420+ SK_U8 Result;\r
41421+\r
41422+ /* Get the current mode, which can be full or half duplex. */\r
41423+ Result = pAC->GIni.GP[PhysPortIndex].PLinkModeStatus;\r
41424+\r
41425+ /* Check if no valid mode could be found (link is down). */\r
41426+ if (Result < SK_LMODE_STAT_HALF) {\r
41427+\r
41428+ Result = SK_LMODE_STAT_UNKNOWN;\r
41429+ }\r
41430+ else if (pAC->GIni.GP[PhysPortIndex].PLinkMode >= SK_LMODE_AUTOHALF) {\r
41431+ /*\r
41432+ * Auto-negotiation was used to bring up the link. Change\r
41433+ * the already found duplex status that it indicates\r
41434+ * auto-negotiation was involved.\r
41435+ */\r
41436+ if (Result == SK_LMODE_STAT_HALF) {\r
41437+\r
41438+ Result = SK_LMODE_STAT_AUTOHALF;\r
41439+ }\r
41440+ else if (Result == SK_LMODE_STAT_FULL) {\r
41441+\r
41442+ Result = SK_LMODE_STAT_AUTOFULL;\r
41443+ }\r
41444+ }\r
41445+\r
41446+ return (Result);\r
41447+}\r
41448+\r
41449+/*****************************************************************************\r
41450+ *\r
41451+ * GetVpdKeyArr - Obtain an array of VPD keys\r
41452+ *\r
41453+ * Description:\r
41454+ * Read the VPD keys and build an array of VPD keys, which are\r
41455+ * easy to access.\r
41456+ *\r
41457+ * Returns:\r
41458+ * SK_PNMI_ERR_OK Task successfully performed.\r
41459+ * SK_PNMI_ERR_GENERAL Something went wrong.\r
41460+ */\r
41461+PNMI_STATIC int GetVpdKeyArr(\r
41462+SK_AC *pAC, /* Pointer to adapter context */\r
41463+SK_IOC IoC, /* IO context handle */\r
41464+char *pKeyArr, /* Ptr KeyArray */\r
41465+unsigned int KeyArrLen, /* Length of array in bytes */\r
41466+unsigned int *pKeyNo) /* Number of keys */\r
41467+{\r
41468+ unsigned int BufKeysLen = SK_PNMI_VPD_BUFSIZE;\r
41469+ char BufKeys[SK_PNMI_VPD_BUFSIZE];\r
41470+ unsigned int StartOffset;\r
41471+ unsigned int Offset;\r
41472+ int Index;\r
41473+ int Ret;\r
41474+\r
41475+ SK_MEMSET(pKeyArr, 0, KeyArrLen);\r
41476+\r
41477+ /* Get VPD key list. */\r
41478+ Ret = VpdKeys(pAC, IoC, BufKeys, (int *)&BufKeysLen,\r
41479+ (int *)pKeyNo);\r
41480+ \r
41481+ if (Ret > 0) {\r
41482+\r
41483+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
41484+ (SK_PNMI_ERR014MSG));\r
41485+\r
41486+ /* Please read comment in Vpd(). */\r
41487+ pAC->Pnmi.VpdKeyReadError = SK_TRUE;\r
41488+ return (SK_PNMI_ERR_GENERAL);\r
41489+ }\r
41490+ /* If no keys are available return now. */\r
41491+ if (*pKeyNo == 0 || BufKeysLen == 0) {\r
41492+\r
41493+ return (SK_PNMI_ERR_OK);\r
41494+ }\r
41495+ /*\r
41496+ * If the key list is too long for us trunc it and give a\r
41497+ * errorlog notification. This case should not happen because\r
41498+ * the maximum number of keys is limited due to RAM limitations.\r
41499+ */\r
41500+ if (*pKeyNo > SK_PNMI_VPD_ENTRIES) {\r
41501+\r
41502+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
41503+ (SK_PNMI_ERR015MSG));\r
41504+\r
41505+ *pKeyNo = SK_PNMI_VPD_ENTRIES;\r
41506+ }\r
41507+\r
41508+ /*\r
41509+ * Now build an array of fixed string length size and copy\r
41510+ * the keys together.\r
41511+ */\r
41512+ for (Index = 0, StartOffset = 0, Offset = 0; Offset < BufKeysLen;\r
41513+ Offset ++) {\r
41514+\r
41515+ if (BufKeys[Offset] != 0) {\r
41516+ continue;\r
41517+ }\r
41518+\r
41519+ if (Offset - StartOffset > SK_PNMI_VPD_KEY_SIZE) {\r
41520+\r
41521+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,\r
41522+ (SK_PNMI_ERR016MSG));\r
41523+\r
41524+ return (SK_PNMI_ERR_GENERAL);\r
41525+ }\r
41526+\r
41527+ SK_STRNCPY(pKeyArr + Index * SK_PNMI_VPD_KEY_SIZE,\r
41528+ &BufKeys[StartOffset], SK_PNMI_VPD_KEY_SIZE);\r
41529+\r
41530+ Index ++;\r
41531+ StartOffset = Offset + 1;\r
41532+ }\r
41533+\r
41534+ /* Last key not zero terminated? Get it anyway. */\r
41535+ if (StartOffset < Offset) {\r
41536+\r
41537+ SK_STRNCPY(pKeyArr + Index * SK_PNMI_VPD_KEY_SIZE,\r
41538+ &BufKeys[StartOffset], SK_PNMI_VPD_KEY_SIZE);\r
41539+ }\r
41540+\r
41541+ return (SK_PNMI_ERR_OK);\r
41542+}\r
41543+\r
41544+/*****************************************************************************\r
41545+ *\r
41546+ * SirqUpdate - Let the SIRQ update its internal values\r
41547+ *\r
41548+ * Description:\r
41549+ * Just to be sure that the SIRQ module holds its internal data\r
41550+ * structures up to date, we send an update event before we make\r
41551+ * any access.\r
41552+ *\r
41553+ * Returns:\r
41554+ * SK_PNMI_ERR_OK Task successfully performed.\r
41555+ * SK_PNMI_ERR_GENERAL Something went wrong.\r
41556+ */\r
41557+PNMI_STATIC int SirqUpdate(\r
41558+SK_AC *pAC, /* Pointer to adapter context */\r
41559+SK_IOC IoC) /* IO context handle */\r
41560+{\r
41561+ SK_EVPARA EventParam;\r
41562+\r
41563+ /* Was the module already updated during the current PNMI call? */\r
41564+ if (pAC->Pnmi.SirqUpdatedFlag > 0) {\r
41565+\r
41566+ return (SK_PNMI_ERR_OK);\r
41567+ }\r
41568+\r
41569+ /* Send an synchronuous update event to the module. */\r
41570+ SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));\r
41571+ \r
41572+ if (SkGeSirqEvent(pAC, IoC, SK_HWEV_UPDATE_STAT, EventParam)) {\r
41573+\r
41574+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR047, SK_PNMI_ERR047MSG);\r
41575+\r
41576+ return (SK_PNMI_ERR_GENERAL);\r
41577+ }\r
41578+\r
41579+ return (SK_PNMI_ERR_OK);\r
41580+}\r
41581+\r
41582+/*****************************************************************************\r
41583+ *\r
41584+ * RlmtUpdate - Let the RLMT update its internal values\r
41585+ *\r
41586+ * Description:\r
41587+ * Just to be sure that the RLMT module holds its internal data\r
41588+ * structures up to date, we send an update event before we make\r
41589+ * any access.\r
41590+ *\r
41591+ * Returns:\r
41592+ * SK_PNMI_ERR_OK Task successfully performed.\r
41593+ * SK_PNMI_ERR_GENERAL Something went wrong.\r
41594+ */\r
41595+PNMI_STATIC int RlmtUpdate(\r
41596+SK_AC *pAC, /* Pointer to adapter context */\r
41597+SK_IOC IoC, /* IO context handle */\r
41598+SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */\r
41599+{\r
41600+ SK_EVPARA EventParam;\r
41601+\r
41602+ /* Was the module already updated during the current PNMI call? */\r
41603+ if (pAC->Pnmi.RlmtUpdatedFlag > 0) {\r
41604+\r
41605+ return (SK_PNMI_ERR_OK);\r
41606+ }\r
41607+\r
41608+ /* Send an synchronuous update event to the module. */\r
41609+ SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));\r
41610+ EventParam.Para32[0] = NetIndex;\r
41611+ EventParam.Para32[1] = (SK_U32)-1;\r
41612+ if (SkRlmtEvent(pAC, IoC, SK_RLMT_STATS_UPDATE, EventParam) > 0) {\r
41613+\r
41614+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR048, SK_PNMI_ERR048MSG);\r
41615+\r
41616+ return (SK_PNMI_ERR_GENERAL);\r
41617+ }\r
41618+\r
41619+ return (SK_PNMI_ERR_OK);\r
41620+}\r
41621+\r
41622+/*****************************************************************************\r
41623+ *\r
41624+ * MacUpdate - Force the XMAC to output the current statistic\r
41625+ *\r
41626+ * Description:\r
41627+ * The XMAC holds its statistic internally. To obtain the current\r
41628+ * values we must send a command so that the statistic data will\r
41629+ * be written to a predefined memory area on the adapter.\r
41630+ *\r
41631+ * Returns:\r
41632+ * SK_PNMI_ERR_OK Task successfully performed.\r
41633+ * SK_PNMI_ERR_GENERAL Something went wrong.\r
41634+ */\r
41635+PNMI_STATIC int MacUpdate(\r
41636+SK_AC *pAC, /* Pointer to adapter context */\r
41637+SK_IOC IoC, /* IO context handle */\r
41638+unsigned int FirstMac, /* Index of the first Mac to be updated */\r
41639+unsigned int LastMac) /* Index of the last Mac to be updated */\r
41640+{\r
41641+ unsigned int MacIndex;\r
41642+\r
41643+ /*\r
41644+ * Were the statistics already updated during the\r
41645+ * current PNMI call?\r
41646+ */\r
41647+ if (pAC->Pnmi.MacUpdatedFlag > 0) {\r
41648+\r
41649+ return (SK_PNMI_ERR_OK);\r
41650+ }\r
41651+\r
41652+ /* Send an update command to all MACs specified. */\r
41653+ for (MacIndex = FirstMac; MacIndex <= LastMac; MacIndex ++) {\r
41654+\r
41655+ /*\r
41656+ * 2002-09-13 pweber: Freeze the current SW counters.\r
41657+ * (That should be done as close as\r
41658+ * possible to the update of the\r
41659+ * HW counters).\r
41660+ */\r
41661+ if (pAC->GIni.GIMacType == SK_MAC_XMAC) {\r
41662+ pAC->Pnmi.BufPort[MacIndex] = pAC->Pnmi.Port[MacIndex];\r
41663+ }\r
41664+ \r
41665+ /* 2002-09-13 pweber: Update the HW counter. */\r
41666+ if (pAC->GIni.GIFunc.pFnMacUpdateStats(pAC, IoC, MacIndex) != 0) {\r
41667+\r
41668+ return (SK_PNMI_ERR_GENERAL);\r
41669+ }\r
41670+ }\r
41671+\r
41672+ return (SK_PNMI_ERR_OK);\r
41673+}\r
41674+\r
41675+/*****************************************************************************\r
41676+ *\r
41677+ * GetStatVal - Retrieve an XMAC statistic counter\r
41678+ *\r
41679+ * Description:\r
41680+ * Retrieves the statistic counter of a virtual or physical port. The\r
41681+ * virtual port is identified by the index 0. It consists of all\r
41682+ * currently active ports. To obtain the counter value for this port\r
41683+ * we must add the statistic counter of all active ports. To grant\r
41684+ * continuous counter values for the virtual port even when port\r
41685+ * switches occur we must additionally add a delta value, which was\r
41686+ * calculated during a SK_PNMI_EVT_RLMT_ACTIVE_UP event.\r
41687+ *\r
41688+ * Returns:\r
41689+ * Requested statistic value\r
41690+ */\r
41691+PNMI_STATIC SK_U64 GetStatVal(\r
41692+SK_AC *pAC, /* Pointer to adapter context */\r
41693+SK_IOC IoC, /* IO context handle */\r
41694+unsigned int LogPortIndex, /* Index of the logical Port to be processed */\r
41695+unsigned int StatIndex, /* Index to statistic value */\r
41696+SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */\r
41697+{\r
41698+ unsigned int PhysPortIndex;\r
41699+ unsigned int PhysPortMax;\r
41700+ SK_U64 Val = 0;\r
41701+\r
41702+\r
41703+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) { /* DualNet mode. */\r
41704+\r
41705+ PhysPortIndex = NetIndex;\r
41706+ \r
41707+ Val = GetPhysStatVal(pAC, IoC, PhysPortIndex, StatIndex);\r
41708+ }\r
41709+ else { /* SingleNet mode. */\r
41710+\r
41711+ if (LogPortIndex == 0) {\r
41712+\r
41713+ PhysPortMax = pAC->GIni.GIMacsFound;\r
41714+\r
41715+ /* Add counter of all active ports. */\r
41716+ for (PhysPortIndex = 0; PhysPortIndex < PhysPortMax;\r
41717+ PhysPortIndex ++) {\r
41718+\r
41719+ if (pAC->Pnmi.Port[PhysPortIndex].ActiveFlag) {\r
41720+\r
41721+ Val += GetPhysStatVal(pAC, IoC, PhysPortIndex, StatIndex);\r
41722+ }\r
41723+ }\r
41724+\r
41725+ /* Correct value because of port switches. */\r
41726+ Val += pAC->Pnmi.VirtualCounterOffset[StatIndex];\r
41727+ }\r
41728+ else {\r
41729+ /* Get counter value of physical port. */\r
41730+ PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(pAC, LogPortIndex);\r
41731+ \r
41732+ Val = GetPhysStatVal(pAC, IoC, PhysPortIndex, StatIndex);\r
41733+ }\r
41734+ }\r
41735+ return (Val);\r
41736+}\r
41737+\r
41738+/*****************************************************************************\r
41739+ *\r
41740+ * GetPhysStatVal - Get counter value for physical port\r
41741+ *\r
41742+ * Description:\r
41743+ * Builds a 64bit counter value. Except for the octet counters\r
41744+ * the lower 32bit are counted in hardware and the upper 32bit\r
41745+ * in software by monitoring counter overflow interrupts in the\r
41746+ * event handler. To grant continous counter values during XMAC\r
41747+ * resets (caused by a workaround) we must add a delta value.\r
41748+ * The delta was calculated in the event handler when a\r
41749+ * SK_PNMI_EVT_XMAC_RESET was received.\r
41750+ *\r
41751+ * Returns:\r
41752+ * Counter value\r
41753+ */\r
41754+PNMI_STATIC SK_U64 GetPhysStatVal(\r
41755+SK_AC *pAC, /* Pointer to adapter context */\r
41756+SK_IOC IoC, /* IO context handle */\r
41757+unsigned int PhysPortIndex, /* Index of the logical Port to be processed */\r
41758+unsigned int StatIndex) /* Index to statistic value */\r
41759+{\r
41760+ SK_U64 Val = 0;\r
41761+ SK_U32 LowVal = 0;\r
41762+ SK_U32 HighVal = 0;\r
41763+ SK_U16 Word;\r
41764+ int MacType;\r
41765+ unsigned int HelpIndex;\r
41766+ SK_GEPORT *pPrt;\r
41767+ \r
41768+ SK_PNMI_PORT *pPnmiPrt;\r
41769+ SK_GEMACFUNC *pFnMac;\r
41770+ \r
41771+ pPrt = &pAC->GIni.GP[PhysPortIndex];\r
41772+ \r
41773+ MacType = pAC->GIni.GIMacType;\r
41774+ \r
41775+ /* 2002-09-17 pweber: For XMAC, use the frozen SW counters (BufPort). */\r
41776+ if (MacType == SK_MAC_XMAC) {\r
41777+ pPnmiPrt = &pAC->Pnmi.BufPort[PhysPortIndex];\r
41778+ }\r
41779+ else {\r
41780+ pPnmiPrt = &pAC->Pnmi.Port[PhysPortIndex];\r
41781+ }\r
41782+ \r
41783+ pFnMac = &pAC->GIni.GIFunc;\r
41784+\r
41785+ switch (StatIndex) {\r
41786+ case SK_PNMI_HTX:\r
41787+ if (MacType == SK_MAC_GMAC) {\r
41788+ (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,\r
41789+ StatAddr[SK_PNMI_HTX_BROADCAST][MacType].Reg,\r
41790+ &LowVal);\r
41791+ (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,\r
41792+ StatAddr[SK_PNMI_HTX_MULTICAST][MacType].Reg,\r
41793+ &HighVal);\r
41794+ LowVal += HighVal;\r
41795+ (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,\r
41796+ StatAddr[SK_PNMI_HTX_UNICAST][MacType].Reg,\r
41797+ &HighVal);\r
41798+ LowVal += HighVal;\r
41799+ }\r
41800+ else {\r
41801+ (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,\r
41802+ StatAddr[StatIndex][MacType].Reg,\r
41803+ &LowVal);\r
41804+ }\r
41805+ HighVal = pPnmiPrt->CounterHigh[StatIndex];\r
41806+ break;\r
41807+ \r
41808+ case SK_PNMI_HRX:\r
41809+ if (MacType == SK_MAC_GMAC) {\r
41810+ (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,\r
41811+ StatAddr[SK_PNMI_HRX_BROADCAST][MacType].Reg,\r
41812+ &LowVal);\r
41813+ (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,\r
41814+ StatAddr[SK_PNMI_HRX_MULTICAST][MacType].Reg,\r
41815+ &HighVal);\r
41816+ LowVal += HighVal;\r
41817+ (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,\r
41818+ StatAddr[SK_PNMI_HRX_UNICAST][MacType].Reg,\r
41819+ &HighVal);\r
41820+ LowVal += HighVal;\r
41821+ }\r
41822+ else {\r
41823+ (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,\r
41824+ StatAddr[StatIndex][MacType].Reg,\r
41825+ &LowVal);\r
41826+ }\r
41827+ HighVal = pPnmiPrt->CounterHigh[StatIndex];\r
41828+ break;\r
41829+\r
41830+ case SK_PNMI_HTX_OCTET:\r
41831+ case SK_PNMI_HRX_OCTET:\r
41832+ (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,\r
41833+ StatAddr[StatIndex][MacType].Reg,\r
41834+ &HighVal);\r
41835+ (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,\r
41836+ StatAddr[StatIndex + 1][MacType].Reg,\r
41837+ &LowVal);\r
41838+ break;\r
41839+\r
41840+ case SK_PNMI_HTX_BURST:\r
41841+ case SK_PNMI_HTX_EXCESS_DEF:\r
41842+ case SK_PNMI_HTX_CARRIER:\r
41843+ /* Not supported by GMAC. */\r
41844+ if (MacType == SK_MAC_GMAC) {\r
41845+ return (Val);\r
41846+ }\r
41847+\r
41848+ (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,\r
41849+ StatAddr[StatIndex][MacType].Reg,\r
41850+ &LowVal);\r
41851+ HighVal = pPnmiPrt->CounterHigh[StatIndex];\r
41852+ break;\r
41853+\r
41854+ case SK_PNMI_HTX_MACC:\r
41855+ /* GMAC only supports PAUSE MAC control frames. */\r
41856+ if (MacType == SK_MAC_GMAC) {\r
41857+ HelpIndex = SK_PNMI_HTX_PMACC;\r
41858+ }\r
41859+ else {\r
41860+ HelpIndex = StatIndex;\r
41861+ }\r
41862+ \r
41863+ (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,\r
41864+ StatAddr[HelpIndex][MacType].Reg,\r
41865+ &LowVal);\r
41866+\r
41867+ HighVal = pPnmiPrt->CounterHigh[StatIndex];\r
41868+ break;\r
41869+\r
41870+ case SK_PNMI_HTX_COL:\r
41871+ case SK_PNMI_HRX_UNDERSIZE:\r
41872+ /* Not supported by XMAC. */\r
41873+ if (MacType == SK_MAC_XMAC) {\r
41874+ return (Val);\r
41875+ }\r
41876+\r
41877+ (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,\r
41878+ StatAddr[StatIndex][MacType].Reg,\r
41879+ &LowVal);\r
41880+ HighVal = pPnmiPrt->CounterHigh[StatIndex];\r
41881+ break;\r
41882+\r
41883+ case SK_PNMI_HTX_DEFFERAL:\r
41884+ /* Not supported by GMAC. */\r
41885+ if (MacType == SK_MAC_GMAC) {\r
41886+ return (Val);\r
41887+ }\r
41888+ \r
41889+ /*\r
41890+ * XMAC counts frames with deferred transmission\r
41891+ * even in full-duplex mode.\r
41892+ *\r
41893+ * In full-duplex mode the counter remains constant!\r
41894+ */\r
41895+ if ((pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOFULL) ||\r
41896+ (pPrt->PLinkModeStatus == SK_LMODE_STAT_FULL)) {\r
41897+\r
41898+ LowVal = 0;\r
41899+ HighVal = 0;\r
41900+ }\r
41901+ else {\r
41902+ /* Otherwise get contents of hardware register. */\r
41903+ (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,\r
41904+ StatAddr[StatIndex][MacType].Reg,\r
41905+ &LowVal);\r
41906+ HighVal = pPnmiPrt->CounterHigh[StatIndex];\r
41907+ }\r
41908+ break;\r
41909+\r
41910+ case SK_PNMI_HRX_BADOCTET:\r
41911+ /* Not supported by XMAC. */\r
41912+ if (MacType == SK_MAC_XMAC) {\r
41913+ return (Val);\r
41914+ }\r
41915+\r
41916+ (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,\r
41917+ StatAddr[StatIndex][MacType].Reg,\r
41918+ &HighVal);\r
41919+ (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,\r
41920+ StatAddr[StatIndex + 1][MacType].Reg,\r
41921+ &LowVal);\r
41922+ break;\r
41923+\r
41924+ case SK_PNMI_HTX_OCTETLOW:\r
41925+ case SK_PNMI_HRX_OCTETLOW:\r
41926+ case SK_PNMI_HRX_BADOCTETLOW:\r
41927+ return (Val);\r
41928+\r
41929+ case SK_PNMI_HRX_LONGFRAMES:\r
41930+ /* For XMAC the SW counter is managed by PNMI. */\r
41931+ if (MacType == SK_MAC_XMAC) {\r
41932+ return (pPnmiPrt->StatRxLongFrameCts);\r
41933+ }\r
41934+ \r
41935+ (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,\r
41936+ StatAddr[StatIndex][MacType].Reg,\r
41937+ &LowVal);\r
41938+ HighVal = pPnmiPrt->CounterHigh[StatIndex];\r
41939+ break;\r
41940+ \r
41941+ case SK_PNMI_HRX_TOO_LONG:\r
41942+ (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,\r
41943+ StatAddr[StatIndex][MacType].Reg,\r
41944+ &LowVal);\r
41945+ HighVal = pPnmiPrt->CounterHigh[StatIndex];\r
41946+ \r
41947+ Val = (((SK_U64)HighVal << 32) | (SK_U64)LowVal);\r
41948+\r
41949+ if (MacType == SK_MAC_GMAC) {\r
41950+ /* For GMAC the SW counter is additionally managed by PNMI. */\r
41951+ Val += pPnmiPrt->StatRxFrameTooLongCts;\r
41952+ }\r
41953+ else {\r
41954+ /*\r
41955+ * Frames longer than IEEE 802.3 frame max size are counted\r
41956+ * by XMAC in frame_too_long counter even reception of long\r
41957+ * frames was enabled and the frame was correct.\r
41958+ * So correct the value by subtracting RxLongFrame counter.\r
41959+ */\r
41960+ Val -= pPnmiPrt->StatRxLongFrameCts;\r
41961+ }\r
41962+\r
41963+ LowVal = (SK_U32)Val;\r
41964+ HighVal = (SK_U32)(Val >> 32);\r
41965+ break;\r
41966+ \r
41967+ case SK_PNMI_HRX_SHORTS:\r
41968+ /* Not supported by GMAC. */\r
41969+ if (MacType == SK_MAC_GMAC) {\r
41970+ /* GM_RXE_FRAG?? */\r
41971+ return (Val);\r
41972+ }\r
41973+ \r
41974+ /*\r
41975+ * XMAC counts short frame errors even if link down (#10620).\r
41976+ * If the link is down, the counter remains constant.\r
41977+ */\r
41978+ if (pPrt->PLinkModeStatus != SK_LMODE_STAT_UNKNOWN) {\r
41979+\r
41980+ /* Otherwise get incremental difference. */\r
41981+ (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,\r
41982+ StatAddr[StatIndex][MacType].Reg,\r
41983+ &LowVal);\r
41984+ HighVal = pPnmiPrt->CounterHigh[StatIndex];\r
41985+\r
41986+ Val = (((SK_U64)HighVal << 32) | (SK_U64)LowVal);\r
41987+ Val -= pPnmiPrt->RxShortZeroMark;\r
41988+\r
41989+ LowVal = (SK_U32)Val;\r
41990+ HighVal = (SK_U32)(Val >> 32);\r
41991+ }\r
41992+ break;\r
41993+\r
41994+ case SK_PNMI_HRX_MACC:\r
41995+ case SK_PNMI_HRX_MACC_UNKWN:\r
41996+ case SK_PNMI_HRX_BURST:\r
41997+ case SK_PNMI_HRX_MISSED:\r
41998+ case SK_PNMI_HRX_FRAMING:\r
41999+ case SK_PNMI_HRX_CARRIER:\r
42000+ case SK_PNMI_HRX_IRLENGTH:\r
42001+ case SK_PNMI_HRX_SYMBOL:\r
42002+ case SK_PNMI_HRX_CEXT:\r
42003+ /* Not supported by GMAC. */\r
42004+ if (MacType == SK_MAC_GMAC) {\r
42005+ return (Val);\r
42006+ }\r
42007+\r
42008+ (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,\r
42009+ StatAddr[StatIndex][MacType].Reg,\r
42010+ &LowVal);\r
42011+ HighVal = pPnmiPrt->CounterHigh[StatIndex];\r
42012+ break;\r
42013+\r
42014+ case SK_PNMI_HRX_PMACC_ERR:\r
42015+ /* For GMAC the SW counter is managed by PNMI. */\r
42016+ if (MacType == SK_MAC_GMAC) {\r
42017+ return (pPnmiPrt->StatRxPMaccErr);\r
42018+ }\r
42019+ \r
42020+ (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,\r
42021+ StatAddr[StatIndex][MacType].Reg,\r
42022+ &LowVal);\r
42023+ HighVal = pPnmiPrt->CounterHigh[StatIndex];\r
42024+ break;\r
42025+\r
42026+ /* SW counter managed by PNMI. */\r
42027+ case SK_PNMI_HTX_SYNC:\r
42028+ LowVal = (SK_U32)pPnmiPrt->StatSyncCts;\r
42029+ HighVal = (SK_U32)(pPnmiPrt->StatSyncCts >> 32);\r
42030+ break;\r
42031+\r
42032+ /* SW counter managed by PNMI. */\r
42033+ case SK_PNMI_HTX_SYNC_OCTET:\r
42034+ LowVal = (SK_U32)pPnmiPrt->StatSyncOctetsCts;\r
42035+ HighVal = (SK_U32)(pPnmiPrt->StatSyncOctetsCts >> 32);\r
42036+ break;\r
42037+\r
42038+ case SK_PNMI_HRX_FCS:\r
42039+ /*\r
42040+ * Broadcom filters FCS errors and counts them in\r
42041+ * Receive Error Counter register.\r
42042+ */\r
42043+ if (pPrt->PhyType == SK_PHY_BCOM) {\r
42044+#ifdef GENESIS\r
42045+ /* Do not read while not initialized (PHY_READ hangs!). */\r
42046+ if (pPrt->PState != SK_PRT_RESET) {\r
42047+ SkXmPhyRead(pAC, IoC, PhysPortIndex, PHY_BCOM_RE_CTR, &Word);\r
42048+ \r
42049+ LowVal = Word;\r
42050+ }\r
42051+ HighVal = pPnmiPrt->CounterHigh[StatIndex];\r
42052+#endif /* GENESIS */\r
42053+ }\r
42054+ else {\r
42055+ (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,\r
42056+ StatAddr[StatIndex][MacType].Reg,\r
42057+ &LowVal);\r
42058+ HighVal = pPnmiPrt->CounterHigh[StatIndex];\r
42059+ }\r
42060+ break;\r
42061+\r
42062+ default:\r
42063+ (void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,\r
42064+ StatAddr[StatIndex][MacType].Reg,\r
42065+ &LowVal);\r
42066+ HighVal = pPnmiPrt->CounterHigh[StatIndex];\r
42067+ break;\r
42068+ }\r
42069+\r
42070+ Val = (((SK_U64)HighVal << 32) | (SK_U64)LowVal);\r
42071+\r
42072+ /* Correct value because of possible XMAC reset (XMAC Errata #2). */\r
42073+ Val += pPnmiPrt->CounterOffset[StatIndex];\r
42074+\r
42075+ return (Val);\r
42076+}\r
42077+\r
42078+/*****************************************************************************\r
42079+ *\r
42080+ * ResetCounter - Set all counters and timestamps to zero\r
42081+ *\r
42082+ * Description:\r
42083+ * Notifies other common modules which store statistic data to\r
42084+ * reset their counters and finally reset our own counters.\r
42085+ *\r
42086+ * Returns:\r
42087+ * Nothing\r
42088+ */\r
42089+PNMI_STATIC void ResetCounter(\r
42090+SK_AC *pAC, /* Pointer to adapter context */\r
42091+SK_IOC IoC, /* IO context handle */\r
42092+SK_U32 NetIndex)\r
42093+{\r
42094+ unsigned int PhysPortIndex;\r
42095+ SK_EVPARA EventParam;\r
42096+\r
42097+ SK_MEMSET((char *)&EventParam, 0, sizeof(EventParam));\r
42098+\r
42099+ /* Notify sensor module. */\r
42100+ SkEventQueue(pAC, SKGE_I2C, SK_I2CEV_CLEAR, EventParam);\r
42101+\r
42102+ /* Notify RLMT module. */\r
42103+ EventParam.Para32[0] = NetIndex;\r
42104+ EventParam.Para32[1] = (SK_U32)-1;\r
42105+ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STATS_CLEAR, EventParam);\r
42106+ EventParam.Para32[1] = 0;\r
42107+\r
42108+ /* Notify SIRQ module. */\r
42109+ SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_CLEAR_STAT, EventParam);\r
42110+\r
42111+ /* Notify CSUM module. */\r
42112+#ifdef SK_USE_CSUM\r
42113+ EventParam.Para32[0] = NetIndex;\r
42114+ EventParam.Para32[1] = (SK_U32)-1;\r
42115+ SkEventQueue(pAC, SKGE_CSUM, SK_CSUM_EVENT_CLEAR_PROTO_STATS,\r
42116+ EventParam);\r
42117+#endif /* SK_USE_CSUM */\r
42118+ \r
42119+ /* Clear XMAC statistics. */\r
42120+ for (PhysPortIndex = 0; PhysPortIndex <\r
42121+ (unsigned int)pAC->GIni.GIMacsFound; PhysPortIndex ++) {\r
42122+\r
42123+ (void)pAC->GIni.GIFunc.pFnMacResetCounter(pAC, IoC, PhysPortIndex);\r
42124+\r
42125+ SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex].CounterHigh,\r
42126+ 0, sizeof(pAC->Pnmi.Port[PhysPortIndex].CounterHigh));\r
42127+ SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex].\r
42128+ CounterOffset, 0, sizeof(pAC->Pnmi.Port[\r
42129+ PhysPortIndex].CounterOffset));\r
42130+ SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex].StatSyncCts,\r
42131+ 0, sizeof(pAC->Pnmi.Port[PhysPortIndex].StatSyncCts));\r
42132+ SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex].\r
42133+ StatSyncOctetsCts, 0, sizeof(pAC->Pnmi.Port[\r
42134+ PhysPortIndex].StatSyncOctetsCts));\r
42135+ SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex].\r
42136+ StatRxLongFrameCts, 0, sizeof(pAC->Pnmi.Port[\r
42137+ PhysPortIndex].StatRxLongFrameCts));\r
42138+ SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex].\r
42139+ StatRxFrameTooLongCts, 0, sizeof(pAC->Pnmi.Port[\r
42140+ PhysPortIndex].StatRxFrameTooLongCts));\r
42141+ SK_MEMSET((char *)&pAC->Pnmi.Port[PhysPortIndex].\r
42142+ StatRxPMaccErr, 0, sizeof(pAC->Pnmi.Port[\r
42143+ PhysPortIndex].StatRxPMaccErr));\r
42144+ }\r
42145+\r
42146+ /* Clear local statistics. */\r
42147+ SK_MEMSET((char *)&pAC->Pnmi.VirtualCounterOffset, 0,\r
42148+ sizeof(pAC->Pnmi.VirtualCounterOffset));\r
42149+ \r
42150+ pAC->Pnmi.RlmtChangeCts = 0;\r
42151+ pAC->Pnmi.RlmtChangeTime = 0;\r
42152+ \r
42153+ SK_MEMSET((char *)&pAC->Pnmi.RlmtChangeEstimate.EstValue[0], 0,\r
42154+ sizeof(pAC->Pnmi.RlmtChangeEstimate.EstValue));\r
42155+ pAC->Pnmi.RlmtChangeEstimate.EstValueIndex = 0;\r
42156+ pAC->Pnmi.RlmtChangeEstimate.Estimate = 0;\r
42157+ pAC->Pnmi.Port[NetIndex].TxSwQueueMax = 0;\r
42158+ pAC->Pnmi.Port[NetIndex].TxRetryCts = 0;\r
42159+ pAC->Pnmi.Port[NetIndex].RxIntrCts = 0;\r
42160+ pAC->Pnmi.Port[NetIndex].TxIntrCts = 0;\r
42161+ pAC->Pnmi.Port[NetIndex].RxNoBufCts = 0;\r
42162+ pAC->Pnmi.Port[NetIndex].TxNoBufCts = 0;\r
42163+ pAC->Pnmi.Port[NetIndex].TxUsedDescrNo = 0;\r
42164+ pAC->Pnmi.Port[NetIndex].RxDeliveredCts = 0;\r
42165+ pAC->Pnmi.Port[NetIndex].RxOctetsDeliveredCts = 0;\r
42166+ pAC->Pnmi.Port[NetIndex].ErrRecoveryCts = 0;\r
42167+}\r
42168+\r
42169+/*****************************************************************************\r
42170+ *\r
42171+ * GetTrapEntry - Get an entry in the trap buffer\r
42172+ *\r
42173+ * Description:\r
42174+ * The trap buffer stores various events. A user application somehow\r
42175+ * gets notified that an event occured and retrieves the trap buffer\r
42176+ * contens (or simply polls the buffer). The buffer is organized as\r
42177+ * a ring which stores the newest traps at the beginning. The oldest\r
42178+ * traps are overwritten by the newest ones. Each trap entry has a\r
42179+ * unique number, so that applications may detect new trap entries.\r
42180+ *\r
42181+ * Returns:\r
42182+ * A pointer to the trap entry\r
42183+ */\r
42184+PNMI_STATIC char* GetTrapEntry(\r
42185+SK_AC *pAC, /* Pointer to adapter context */\r
42186+SK_U32 TrapId, /* SNMP ID of the trap */\r
42187+unsigned int Size) /* Space needed for trap entry */\r
42188+{\r
42189+ unsigned int BufPad = pAC->Pnmi.TrapBufPad;\r
42190+ unsigned int BufFree = pAC->Pnmi.TrapBufFree;\r
42191+ unsigned int Beg = pAC->Pnmi.TrapQueueBeg;\r
42192+ unsigned int End = pAC->Pnmi.TrapQueueEnd;\r
42193+ char *pBuf = &pAC->Pnmi.TrapBuf[0];\r
42194+ int Wrap;\r
42195+ unsigned int NeededSpace;\r
42196+ unsigned int EntrySize;\r
42197+ SK_U32 Val32;\r
42198+ SK_U64 Val64;\r
42199+\r
42200+ /* Last byte of entry will get a copy of the entry length. */\r
42201+ Size ++;\r
42202+\r
42203+ /* Calculate needed buffer space. */\r
42204+ if (Beg >= Size) {\r
42205+\r
42206+ NeededSpace = Size;\r
42207+ Wrap = SK_FALSE;\r
42208+ }\r
42209+ else {\r
42210+ NeededSpace = Beg + Size;\r
42211+ Wrap = SK_TRUE;\r
42212+ }\r
42213+\r
42214+ /*\r
42215+ * Check if enough buffer space is provided. Otherwise\r
42216+ * free some entries. Leave one byte space between begin\r
42217+ * and end of buffer to make it possible to detect whether\r
42218+ * the buffer is full or empty.\r
42219+ */\r
42220+ while (BufFree < NeededSpace + 1) {\r
42221+\r
42222+ if (End == 0) {\r
42223+\r
42224+ End = SK_PNMI_TRAP_QUEUE_LEN;\r
42225+ }\r
42226+\r
42227+ EntrySize = (unsigned int)*((unsigned char *)pBuf + End - 1);\r
42228+ BufFree += EntrySize;\r
42229+ End -= EntrySize;\r
42230+#ifdef DEBUG\r
42231+ SK_MEMSET(pBuf + End, (char)(-1), EntrySize);\r
42232+#endif /* DEBUG */\r
42233+ if (End == BufPad) {\r
42234+#ifdef DEBUG\r
42235+ SK_MEMSET(pBuf, (char)(-1), End);\r
42236+#endif /* DEBUG */\r
42237+ BufFree += End;\r
42238+ End = 0;\r
42239+ BufPad = 0;\r
42240+ }\r
42241+ }\r
42242+\r
42243+ /*\r
42244+ * Insert new entry as first entry. Newest entries are\r
42245+ * stored at the beginning of the queue.\r
42246+ */\r
42247+ if (Wrap) {\r
42248+\r
42249+ BufPad = Beg;\r
42250+ Beg = SK_PNMI_TRAP_QUEUE_LEN - Size;\r
42251+ }\r
42252+ else {\r
42253+ Beg = Beg - Size;\r
42254+ }\r
42255+ BufFree -= NeededSpace;\r
42256+\r
42257+ /* Save the current offsets. */\r
42258+ pAC->Pnmi.TrapQueueBeg = Beg;\r
42259+ pAC->Pnmi.TrapQueueEnd = End;\r
42260+ pAC->Pnmi.TrapBufPad = BufPad;\r
42261+ pAC->Pnmi.TrapBufFree = BufFree;\r
42262+\r
42263+ /* Initialize the trap entry. */\r
42264+ *(pBuf + Beg + Size - 1) = (char)Size;\r
42265+ *(pBuf + Beg) = (char)Size;\r
42266+ Val32 = (pAC->Pnmi.TrapUnique) ++;\r
42267+ SK_PNMI_STORE_U32(pBuf + Beg + 1, Val32);\r
42268+ SK_PNMI_STORE_U32(pBuf + Beg + 1 + sizeof(SK_U32), TrapId);\r
42269+ Val64 = SK_PNMI_HUNDREDS_SEC(SkOsGetTime(pAC));\r
42270+ SK_PNMI_STORE_U64(pBuf + Beg + 1 + 2 * sizeof(SK_U32), Val64);\r
42271+\r
42272+ return (pBuf + Beg);\r
42273+}\r
42274+\r
42275+/*****************************************************************************\r
42276+ *\r
42277+ * CopyTrapQueue - Copies the trap buffer for the TRAP OID\r
42278+ *\r
42279+ * Description:\r
42280+ * On a query of the TRAP OID the trap buffer contents will be\r
42281+ * copied continuously to the request buffer, which must be large\r
42282+ * enough. No length check is performed.\r
42283+ *\r
42284+ * Returns:\r
42285+ * Nothing\r
42286+ */\r
42287+PNMI_STATIC void CopyTrapQueue(\r
42288+SK_AC *pAC, /* Pointer to adapter context */\r
42289+char *pDstBuf) /* Buffer to which the queued traps will be copied */\r
42290+{\r
42291+ unsigned int BufPad = pAC->Pnmi.TrapBufPad;\r
42292+ unsigned int Trap = pAC->Pnmi.TrapQueueBeg;\r
42293+ unsigned int End = pAC->Pnmi.TrapQueueEnd;\r
42294+ char *pBuf = &pAC->Pnmi.TrapBuf[0];\r
42295+ unsigned int Len;\r
42296+ unsigned int DstOff = 0;\r
42297+\r
42298+ while (Trap != End) {\r
42299+\r
42300+ Len = (unsigned int)*(pBuf + Trap);\r
42301+\r
42302+ /*\r
42303+ * Last byte containing a copy of the length will\r
42304+ * not be copied.\r
42305+ */\r
42306+ *(pDstBuf + DstOff) = (char)(Len - 1);\r
42307+ SK_MEMCPY(pDstBuf + DstOff + 1, pBuf + Trap + 1, Len - 2);\r
42308+ DstOff += Len - 1;\r
42309+\r
42310+ Trap += Len;\r
42311+ if (Trap == SK_PNMI_TRAP_QUEUE_LEN) {\r
42312+\r
42313+ Trap = BufPad;\r
42314+ }\r
42315+ }\r
42316+}\r
42317+\r
42318+/*****************************************************************************\r
42319+ *\r
42320+ * GetTrapQueueLen - Get the length of the trap buffer\r
42321+ *\r
42322+ * Description:\r
42323+ * Evaluates the number of currently stored traps and the needed\r
42324+ * buffer size to retrieve them.\r
42325+ *\r
42326+ * Returns:\r
42327+ * Nothing\r
42328+ */\r
42329+PNMI_STATIC void GetTrapQueueLen(\r
42330+SK_AC *pAC, /* Pointer to adapter context */\r
42331+unsigned int *pLen, /* Length in Bytes of all queued traps */\r
42332+unsigned int *pEntries) /* Returns number of trapes stored in queue */\r
42333+{\r
42334+ unsigned int BufPad = pAC->Pnmi.TrapBufPad;\r
42335+ unsigned int Trap = pAC->Pnmi.TrapQueueBeg;\r
42336+ unsigned int End = pAC->Pnmi.TrapQueueEnd;\r
42337+ char *pBuf = &pAC->Pnmi.TrapBuf[0];\r
42338+ unsigned int Len;\r
42339+ unsigned int Entries = 0;\r
42340+ unsigned int TotalLen = 0;\r
42341+\r
42342+ while (Trap != End) {\r
42343+\r
42344+ Len = (unsigned int)*(pBuf + Trap);\r
42345+ TotalLen += Len - 1;\r
42346+ Entries ++;\r
42347+\r
42348+ Trap += Len;\r
42349+ if (Trap == SK_PNMI_TRAP_QUEUE_LEN) {\r
42350+\r
42351+ Trap = BufPad;\r
42352+ }\r
42353+ }\r
42354+\r
42355+ *pEntries = Entries;\r
42356+ *pLen = TotalLen;\r
42357+}\r
42358+\r
42359+/*****************************************************************************\r
42360+ *\r
42361+ * QueueSimpleTrap - Store a simple trap to the trap buffer\r
42362+ *\r
42363+ * Description:\r
42364+ * A simple trap is a trap with now additional data. It consists\r
42365+ * simply of a trap code.\r
42366+ *\r
42367+ * Returns:\r
42368+ * Nothing\r
42369+ */\r
42370+PNMI_STATIC void QueueSimpleTrap(\r
42371+SK_AC *pAC, /* Pointer to adapter context */\r
42372+SK_U32 TrapId) /* Type of sensor trap */\r
42373+{\r
42374+ GetTrapEntry(pAC, TrapId, SK_PNMI_TRAP_SIMPLE_LEN);\r
42375+}\r
42376+\r
42377+/*****************************************************************************\r
42378+ *\r
42379+ * QueueSensorTrap - Stores a sensor trap in the trap buffer\r
42380+ *\r
42381+ * Description:\r
42382+ * Gets an entry in the trap buffer and fills it with sensor related\r
42383+ * data.\r
42384+ *\r
42385+ * Returns:\r
42386+ * Nothing\r
42387+ */\r
42388+PNMI_STATIC void QueueSensorTrap(\r
42389+SK_AC *pAC, /* Pointer to adapter context */\r
42390+SK_U32 TrapId, /* Type of sensor trap */\r
42391+unsigned int SensorIndex) /* Index of sensor which caused the trap */\r
42392+{\r
42393+ char *pBuf;\r
42394+ unsigned int Offset;\r
42395+ unsigned int DescrLen;\r
42396+ SK_U32 Val32;\r
42397+\r
42398+ /* Get trap buffer entry. */\r
42399+ DescrLen = SK_STRLEN(pAC->I2c.SenTable[SensorIndex].SenDesc);\r
42400+ \r
42401+ pBuf = GetTrapEntry(pAC, TrapId,\r
42402+ SK_PNMI_TRAP_SENSOR_LEN_BASE + DescrLen);\r
42403+ Offset = SK_PNMI_TRAP_SIMPLE_LEN;\r
42404+\r
42405+ /* Store additionally sensor trap related data. */\r
42406+ Val32 = OID_SKGE_SENSOR_INDEX;\r
42407+ SK_PNMI_STORE_U32(pBuf + Offset, Val32);\r
42408+ *(pBuf + Offset + 4) = 4;\r
42409+ Val32 = (SK_U32)SensorIndex;\r
42410+ SK_PNMI_STORE_U32(pBuf + Offset + 5, Val32);\r
42411+ Offset += 9;\r
42412+ \r
42413+ Val32 = (SK_U32)OID_SKGE_SENSOR_DESCR;\r
42414+ SK_PNMI_STORE_U32(pBuf + Offset, Val32);\r
42415+ *(pBuf + Offset + 4) = (char)DescrLen;\r
42416+ SK_MEMCPY(pBuf + Offset + 5, pAC->I2c.SenTable[SensorIndex].SenDesc,\r
42417+ DescrLen);\r
42418+ Offset += DescrLen + 5;\r
42419+\r
42420+ Val32 = OID_SKGE_SENSOR_TYPE;\r
42421+ SK_PNMI_STORE_U32(pBuf + Offset, Val32);\r
42422+ *(pBuf + Offset + 4) = 1;\r
42423+ *(pBuf + Offset + 5) = (char)pAC->I2c.SenTable[SensorIndex].SenType;\r
42424+ Offset += 6;\r
42425+\r
42426+ Val32 = OID_SKGE_SENSOR_VALUE;\r
42427+ SK_PNMI_STORE_U32(pBuf + Offset, Val32);\r
42428+ *(pBuf + Offset + 4) = 4;\r
42429+ Val32 = (SK_U32)pAC->I2c.SenTable[SensorIndex].SenValue;\r
42430+ SK_PNMI_STORE_U32(pBuf + Offset + 5, Val32);\r
42431+}\r
42432+\r
42433+/*****************************************************************************\r
42434+ *\r
42435+ * QueueRlmtNewMacTrap - Store a port switch trap in the trap buffer\r
42436+ *\r
42437+ * Description:\r
42438+ * Nothing further to explain.\r
42439+ *\r
42440+ * Returns:\r
42441+ * Nothing\r
42442+ */\r
42443+PNMI_STATIC void QueueRlmtNewMacTrap(\r
42444+SK_AC *pAC, /* Pointer to adapter context */\r
42445+unsigned int ActiveMac) /* Index (0..n) of the currently active port */\r
42446+{\r
42447+ char *pBuf;\r
42448+ SK_U32 Val32;\r
42449+\r
42450+ pBuf = GetTrapEntry(pAC, OID_SKGE_TRAP_RLMT_CHANGE_PORT,\r
42451+ SK_PNMI_TRAP_RLMT_CHANGE_LEN);\r
42452+\r
42453+ Val32 = OID_SKGE_RLMT_PORT_ACTIVE;\r
42454+ SK_PNMI_STORE_U32(pBuf + SK_PNMI_TRAP_SIMPLE_LEN, Val32);\r
42455+ *(pBuf + SK_PNMI_TRAP_SIMPLE_LEN + 4) = 1;\r
42456+ *(pBuf + SK_PNMI_TRAP_SIMPLE_LEN + 5) = (char)ActiveMac;\r
42457+}\r
42458+\r
42459+/*****************************************************************************\r
42460+ *\r
42461+ * QueueRlmtPortTrap - Store port related RLMT trap to trap buffer\r
42462+ *\r
42463+ * Description:\r
42464+ * Nothing further to explain.\r
42465+ *\r
42466+ * Returns:\r
42467+ * Nothing\r
42468+ */\r
42469+PNMI_STATIC void QueueRlmtPortTrap(\r
42470+SK_AC *pAC, /* Pointer to adapter context */\r
42471+SK_U32 TrapId, /* Type of RLMT port trap */\r
42472+unsigned int PortIndex) /* Index of the port, which changed its state */\r
42473+{\r
42474+ char *pBuf;\r
42475+ SK_U32 Val32;\r
42476+\r
42477+ pBuf = GetTrapEntry(pAC, TrapId, SK_PNMI_TRAP_RLMT_PORT_LEN);\r
42478+\r
42479+ Val32 = OID_SKGE_RLMT_PORT_INDEX;\r
42480+ SK_PNMI_STORE_U32(pBuf + SK_PNMI_TRAP_SIMPLE_LEN, Val32);\r
42481+ *(pBuf + SK_PNMI_TRAP_SIMPLE_LEN + 4) = 1;\r
42482+ *(pBuf + SK_PNMI_TRAP_SIMPLE_LEN + 5) = (char)PortIndex;\r
42483+}\r
42484+\r
42485+/*****************************************************************************\r
42486+ *\r
42487+ * CopyMac - Copies a MAC address\r
42488+ *\r
42489+ * Description:\r
42490+ * Nothing further to explain.\r
42491+ *\r
42492+ * Returns:\r
42493+ * Nothing\r
42494+ */\r
42495+PNMI_STATIC void CopyMac(\r
42496+char *pDst, /* Pointer to destination buffer */\r
42497+SK_MAC_ADDR *pMac) /* Pointer of Source */\r
42498+{\r
42499+ int i;\r
42500+\r
42501+ for (i = 0; i < sizeof(SK_MAC_ADDR); i ++) {\r
42502+\r
42503+ *(pDst + i) = pMac->a[i];\r
42504+ }\r
42505+}\r
42506+\r
42507+#ifdef SK_POWER_MGMT\r
42508+/*****************************************************************************\r
42509+ *\r
42510+ * PowerManagement - OID handler function of PowerManagement OIDs\r
42511+ *\r
42512+ * Description:\r
42513+ * The code is simple. No description necessary.\r
42514+ *\r
42515+ * Returns:\r
42516+ * SK_PNMI_ERR_OK The request was successfully performed.\r
42517+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.\r
42518+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain\r
42519+ * the correct data (e.g. a 32bit value is\r
42520+ * needed, but a 16 bit value was passed).\r
42521+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't\r
42522+ * exist (e.g. port instance 3 on a two port\r
42523+ * adapter.\r
42524+ */\r
42525+\r
42526+PNMI_STATIC int PowerManagement(\r
42527+SK_AC *pAC, /* Pointer to adapter context */\r
42528+SK_IOC IoC, /* IO context handle */\r
42529+int Action, /* Get/PreSet/Set action */\r
42530+SK_U32 Id, /* Object ID that is to be processed */\r
42531+char *pBuf, /* Buffer to which to mgmt data will be retrieved */\r
42532+unsigned int *pLen, /* On call: buffer length. On return: used buffer */\r
42533+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */\r
42534+unsigned int TableIndex, /* Index to the Id table */\r
42535+SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */\r
42536+{\r
42537+ \r
42538+ int i;\r
42539+ unsigned int HwPortIndex;\r
42540+ \r
42541+ SK_U32 RetCode = SK_PNMI_ERR_GENERAL;\r
42542+\r
42543+ /* Check instance. We only handle single instance variables. */\r
42544+ if ((Instance != (SK_U32)(-1))) {\r
42545+\r
42546+ *pLen = 0;\r
42547+ return (SK_PNMI_ERR_UNKNOWN_INST);\r
42548+ }\r
42549+\r
42550+ /* Get hardware port index */\r
42551+ HwPortIndex = NetIndex;\r
42552+ \r
42553+ /* Check length. */\r
42554+ switch (Id) {\r
42555+\r
42556+ case OID_PNP_CAPABILITIES:\r
42557+ if (*pLen < sizeof(SK_PNP_CAPABILITIES)) {\r
42558+\r
42559+ *pLen = sizeof(SK_PNP_CAPABILITIES);\r
42560+ return (SK_PNMI_ERR_TOO_SHORT);\r
42561+ }\r
42562+ break;\r
42563+\r
42564+ case OID_PNP_SET_POWER:\r
42565+ case OID_PNP_QUERY_POWER:\r
42566+ if (*pLen < sizeof(SK_DEVICE_POWER_STATE))\r
42567+ {\r
42568+ *pLen = sizeof(SK_DEVICE_POWER_STATE);\r
42569+ return (SK_PNMI_ERR_TOO_SHORT);\r
42570+ }\r
42571+ break;\r
42572+\r
42573+ case OID_PNP_ADD_WAKE_UP_PATTERN:\r
42574+ case OID_PNP_REMOVE_WAKE_UP_PATTERN:\r
42575+ if (*pLen < sizeof(SK_PM_PACKET_PATTERN)) {\r
42576+\r
42577+ *pLen = sizeof(SK_PM_PACKET_PATTERN);\r
42578+ return (SK_PNMI_ERR_TOO_SHORT);\r
42579+ }\r
42580+ break;\r
42581+\r
42582+ case OID_PNP_ENABLE_WAKE_UP:\r
42583+ if (*pLen < sizeof(SK_U32)) {\r
42584+\r
42585+ *pLen = sizeof(SK_U32);\r
42586+ return (SK_PNMI_ERR_TOO_SHORT);\r
42587+ }\r
42588+ break;\r
42589+ }\r
42590+ \r
42591+ /* Perform action. */\r
42592+ if (Action == SK_PNMI_GET) {\r
42593+\r
42594+ /* Get value. */\r
42595+ switch (Id) {\r
42596+\r
42597+ case OID_PNP_CAPABILITIES:\r
42598+ RetCode = SkPowerQueryPnPCapabilities(pAC, IoC, pBuf, pLen);\r
42599+ break;\r
42600+\r
42601+ case OID_PNP_QUERY_POWER:\r
42602+ /*\r
42603+ * The Windows DDK describes: An OID_PNP_QUERY_POWER requests\r
42604+ * the miniport to indicate whether it can transition its NIC\r
42605+ * to the low-power state.\r
42606+ * A miniport driver must always return NDIS_STATUS_SUCCESS\r
42607+ * to a query of OID_PNP_QUERY_POWER.\r
42608+ */\r
42609+ *pLen = sizeof(SK_DEVICE_POWER_STATE);\r
42610+ RetCode = SK_PNMI_ERR_OK;\r
42611+ break;\r
42612+\r
42613+ /*\r
42614+ * NDIS handles these OIDs as write-only.\r
42615+ * So in case of get action the buffer with written length = 0\r
42616+ * is returned.\r
42617+ */\r
42618+ case OID_PNP_SET_POWER:\r
42619+ case OID_PNP_ADD_WAKE_UP_PATTERN:\r
42620+ case OID_PNP_REMOVE_WAKE_UP_PATTERN:\r
42621+ *pLen = 0; \r
42622+ RetCode = SK_PNMI_ERR_NOT_SUPPORTED;\r
42623+ break;\r
42624+\r
42625+ case OID_PNP_ENABLE_WAKE_UP:\r
42626+ RetCode = SkPowerGetEnableWakeUp(pAC, IoC, HwPortIndex, pBuf, pLen);\r
42627+ break;\r
42628+\r
42629+ default:\r
42630+ RetCode = SK_PNMI_ERR_GENERAL;\r
42631+ break;\r
42632+ }\r
42633+\r
42634+ return (RetCode);\r
42635+ }\r
42636+ \r
42637+ /* Perform PRESET or SET. */\r
42638+ \r
42639+ /* The POWER module does not support PRESET action. */\r
42640+ if (Action == SK_PNMI_PRESET) {\r
42641+\r
42642+ return (SK_PNMI_ERR_OK);\r
42643+ }\r
42644+\r
42645+ /* */\r
42646+ i= HwPortIndex;\r
42647+\r
42648+ switch (Id) {\r
42649+ case OID_PNP_SET_POWER:\r
42650+ /* Dual net mode? */\r
42651+ for (i = 0; i < pAC->GIni.GIMacsFound; i++) {\r
42652+ if (RetCode = SkPowerSetPower(pAC, IoC, i, pBuf, pLen)) {\r
42653+ break;\r
42654+ }\r
42655+ }\r
42656+ break;\r
42657+\r
42658+ case OID_PNP_ADD_WAKE_UP_PATTERN:\r
42659+ for (i = 0; i < pAC->GIni.GIMacsFound; i++) {\r
42660+ if (RetCode = SkPowerAddWakeUpPattern(pAC, IoC, i, pBuf, pLen)) {\r
42661+ break;\r
42662+ }\r
42663+ }\r
42664+ break;\r
42665+ \r
42666+ case OID_PNP_REMOVE_WAKE_UP_PATTERN:\r
42667+ for (i = 0; i < pAC->GIni.GIMacsFound; i++) {\r
42668+ if (RetCode = SkPowerRemoveWakeUpPattern(pAC, IoC, i, pBuf, pLen)) {\r
42669+ break;\r
42670+ }\r
42671+ }\r
42672+ break;\r
42673+ \r
42674+ case OID_PNP_ENABLE_WAKE_UP:\r
42675+ for (i = 0; i < pAC->GIni.GIMacsFound; i++) {\r
42676+ if (RetCode = SkPowerSetEnableWakeUp(pAC, IoC, i, pBuf, pLen)) {\r
42677+ break;\r
42678+ }\r
42679+ }\r
42680+ break;\r
42681+ \r
42682+ default:\r
42683+ RetCode = SK_PNMI_ERR_READ_ONLY;\r
42684+ }\r
42685+ \r
42686+ return (RetCode);\r
42687+}\r
42688+#endif /* SK_POWER_MGMT */\r
42689+\r
42690+#ifdef SK_DIAG_SUPPORT\r
42691+/*****************************************************************************\r
42692+ *\r
42693+ * DiagActions - OID handler function of Diagnostic driver\r
42694+ *\r
42695+ * Description:\r
42696+ * The code is simple. No description necessary.\r
42697+ *\r
42698+ * Returns:\r
42699+ * SK_PNMI_ERR_OK The request was successfully performed.\r
42700+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.\r
42701+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain\r
42702+ * the correct data (e.g. a 32bit value is\r
42703+ * needed, but a 16 bit value was passed).\r
42704+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't\r
42705+ * exist (e.g. port instance 3 on a two port\r
42706+ * adapter.\r
42707+ */\r
42708+\r
42709+PNMI_STATIC int DiagActions(\r
42710+SK_AC *pAC, /* Pointer to adapter context */\r
42711+SK_IOC IoC, /* IO context handle */\r
42712+int Action, /* GET/PRESET/SET action */\r
42713+SK_U32 Id, /* Object ID that is to be processed */\r
42714+char *pBuf, /* Buffer used for the management data transfer */\r
42715+unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */\r
42716+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */\r
42717+unsigned int TableIndex, /* Index to the Id table */\r
42718+SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */\r
42719+{\r
42720+ SK_U32 DiagStatus;\r
42721+ SK_U32 RetCode = SK_PNMI_ERR_GENERAL;\r
42722+\r
42723+ /* Check instance. We only handle single instance variables. */\r
42724+ if (Instance != (SK_U32)(-1) && Instance != 1) {\r
42725+\r
42726+ *pLen = 0;\r
42727+ return (SK_PNMI_ERR_UNKNOWN_INST);\r
42728+ }\r
42729+\r
42730+ /* Check length. */\r
42731+ switch (Id) {\r
42732+\r
42733+ case OID_SKGE_DIAG_MODE:\r
42734+ if (*pLen < sizeof(SK_U32)) {\r
42735+\r
42736+ *pLen = sizeof(SK_U32);\r
42737+ return (SK_PNMI_ERR_TOO_SHORT);\r
42738+ }\r
42739+ break;\r
42740+\r
42741+ default:\r
42742+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR040, SK_PNMI_ERR040MSG);\r
42743+ *pLen = 0;\r
42744+ return (SK_PNMI_ERR_GENERAL);\r
42745+ }\r
42746+\r
42747+ /* Perform action. */\r
42748+ if (Action == SK_PNMI_GET) {\r
42749+\r
42750+ /* Get value. */\r
42751+ switch (Id) {\r
42752+\r
42753+ case OID_SKGE_DIAG_MODE:\r
42754+ DiagStatus = pAC->Pnmi.DiagAttached;\r
42755+ SK_PNMI_STORE_U32(pBuf, DiagStatus);\r
42756+ *pLen = sizeof(SK_U32); \r
42757+ RetCode = SK_PNMI_ERR_OK;\r
42758+ break;\r
42759+\r
42760+ default:\r
42761+ *pLen = 0; \r
42762+ RetCode = SK_PNMI_ERR_GENERAL;\r
42763+ break;\r
42764+ }\r
42765+ return (RetCode);\r
42766+ }\r
42767+\r
42768+ /* From here SET or PRESET value. */\r
42769+ \r
42770+ /* PRESET value is not supported. */\r
42771+ if (Action == SK_PNMI_PRESET) {\r
42772+\r
42773+ return (SK_PNMI_ERR_OK);\r
42774+ }\r
42775+\r
42776+ /* SET value. */\r
42777+ switch (Id) {\r
42778+ case OID_SKGE_DIAG_MODE:\r
42779+\r
42780+ /* Handle the SET. */\r
42781+ switch (*pBuf) {\r
42782+\r
42783+ /* Attach the DIAG to this adapter. */\r
42784+ case SK_DIAG_ATTACHED:\r
42785+ /* Check if we come from running. */\r
42786+ if (pAC->Pnmi.DiagAttached == SK_DIAG_RUNNING) {\r
42787+\r
42788+ RetCode = SkDrvLeaveDiagMode(pAC);\r
42789+\r
42790+ }\r
42791+ else if (pAC->Pnmi.DiagAttached == SK_DIAG_IDLE) {\r
42792+\r
42793+ RetCode = SK_PNMI_ERR_OK;\r
42794+ } \r
42795+ \r
42796+ else {\r
42797+\r
42798+ RetCode = SK_PNMI_ERR_GENERAL;\r
42799+\r
42800+ }\r
42801+ \r
42802+ if (RetCode == SK_PNMI_ERR_OK) {\r
42803+\r
42804+ pAC->Pnmi.DiagAttached = SK_DIAG_ATTACHED;\r
42805+ }\r
42806+ break;\r
42807+\r
42808+ /* Enter the DIAG mode in the driver. */\r
42809+ case SK_DIAG_RUNNING:\r
42810+ RetCode = SK_PNMI_ERR_OK;\r
42811+ \r
42812+ /*\r
42813+ * If DiagAttached is set, we can tell the driver\r
42814+ * to enter the DIAG mode.\r
42815+ */\r
42816+ if (pAC->Pnmi.DiagAttached == SK_DIAG_ATTACHED) {\r
42817+ /* If DiagMode is not active, we can enter it. */\r
42818+ if (!pAC->DiagModeActive) {\r
42819+\r
42820+ RetCode = SkDrvEnterDiagMode(pAC);\r
42821+ }\r
42822+ else {\r
42823+\r
42824+ RetCode = SK_PNMI_ERR_GENERAL;\r
42825+ }\r
42826+ }\r
42827+ else {\r
42828+\r
42829+ RetCode = SK_PNMI_ERR_GENERAL;\r
42830+ }\r
42831+ \r
42832+ if (RetCode == SK_PNMI_ERR_OK) {\r
42833+\r
42834+ pAC->Pnmi.DiagAttached = SK_DIAG_RUNNING;\r
42835+ }\r
42836+ break;\r
42837+\r
42838+ case SK_DIAG_IDLE:\r
42839+ /* Check if we come from running. */\r
42840+ if (pAC->Pnmi.DiagAttached == SK_DIAG_RUNNING) {\r
42841+\r
42842+ RetCode = SkDrvLeaveDiagMode(pAC);\r
42843+\r
42844+ }\r
42845+ else if (pAC->Pnmi.DiagAttached == SK_DIAG_ATTACHED) {\r
42846+\r
42847+ RetCode = SK_PNMI_ERR_OK;\r
42848+ } \r
42849+ \r
42850+ else {\r
42851+\r
42852+ RetCode = SK_PNMI_ERR_GENERAL;\r
42853+\r
42854+ }\r
42855+\r
42856+ if (RetCode == SK_PNMI_ERR_OK) {\r
42857+\r
42858+ pAC->Pnmi.DiagAttached = SK_DIAG_IDLE;\r
42859+ }\r
42860+ break;\r
42861+\r
42862+ default:\r
42863+ RetCode = SK_PNMI_ERR_BAD_VALUE;\r
42864+ break;\r
42865+ }\r
42866+ break;\r
42867+\r
42868+ default:\r
42869+ RetCode = SK_PNMI_ERR_GENERAL;\r
42870+ }\r
42871+\r
42872+ if (RetCode == SK_PNMI_ERR_OK) {\r
42873+ *pLen = sizeof(SK_U32);\r
42874+ }\r
42875+ else {\r
42876+\r
42877+ *pLen = 0;\r
42878+ }\r
42879+ return (RetCode);\r
42880+}\r
42881+#endif /* SK_DIAG_SUPPORT */\r
42882+\r
42883+/*****************************************************************************\r
42884+ *\r
42885+ * Vct - OID handler function of OIDs for Virtual Cable Tester (VCT)\r
42886+ *\r
42887+ * Description:\r
42888+ * The code is simple. No description necessary.\r
42889+ *\r
42890+ * Returns:\r
42891+ * SK_PNMI_ERR_OK The request was performed successfully.\r
42892+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.\r
42893+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain\r
42894+ * the correct data (e.g. a 32bit value is\r
42895+ * needed, but a 16 bit value was passed).\r
42896+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't\r
42897+ * exist (e.g. port instance 3 on a two port\r
42898+ * adapter).\r
42899+ * SK_PNMI_ERR_READ_ONLY Only the Get action is allowed.\r
42900+ *\r
42901+ */\r
42902+\r
42903+PNMI_STATIC int Vct(\r
42904+SK_AC *pAC, /* Pointer to adapter context */\r
42905+SK_IOC IoC, /* IO context handle */\r
42906+int Action, /* GET/PRESET/SET action */\r
42907+SK_U32 Id, /* Object ID that is to be processed */\r
42908+char *pBuf, /* Buffer used for the management data transfer */\r
42909+unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */\r
42910+SK_U32 Instance, /* Instance (-1,2..n) that is to be queried */\r
42911+unsigned int TableIndex, /* Index to the Id table */\r
42912+SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */\r
42913+{\r
42914+ SK_GEPORT *pPrt;\r
42915+ SK_PNMI_VCT *pVctBackupData;\r
42916+ SK_U32 LogPortMax;\r
42917+ SK_U32 PhysPortMax;\r
42918+ SK_U32 PhysPortIndex;\r
42919+ SK_U32 Limit;\r
42920+ SK_U32 Offset;\r
42921+ SK_U32 RetCode;\r
42922+ int i;\r
42923+ SK_EVPARA Para;\r
42924+\r
42925+ RetCode = SK_PNMI_ERR_GENERAL;\r
42926+\r
42927+ /* Calculate the port indexes from the instance. */\r
42928+ PhysPortMax = pAC->GIni.GIMacsFound;\r
42929+ LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax);\r
42930+\r
42931+ /* Dual net mode? */\r
42932+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
42933+ LogPortMax--;\r
42934+ }\r
42935+\r
42936+ if ((Instance != (SK_U32) (-1))) {\r
42937+ /*\r
42938+ * Get one instance of that OID, so check the instance range:\r
42939+ * There is no virtual port with an Instance == 1, so we get\r
42940+ * the values from one physical port only.\r
42941+ */ \r
42942+ if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {\r
42943+ PhysPortIndex = NetIndex;\r
42944+ }\r
42945+ else {\r
42946+ if ((Instance < 2) || (Instance > LogPortMax)) {\r
42947+ *pLen = 0;\r
42948+ return (SK_PNMI_ERR_UNKNOWN_INST);\r
42949+ }\r
42950+ PhysPortIndex = Instance - 2;\r
42951+ }\r
42952+ Limit = PhysPortIndex + 1;\r
42953+ }\r
42954+ else {\r
42955+ /*\r
42956+ * Instance == (SK_U32) (-1), so get all instances of that OID.\r
42957+ * There is no virtual port with an Instance == 1, so we get\r
42958+ * the values from all physical ports.\r
42959+ */\r
42960+ PhysPortIndex = 0;\r
42961+ Limit = PhysPortMax;\r
42962+ }\r
42963+\r
42964+ /* Check MAC type. */\r
42965+ if ((Id != OID_SKGE_VCT_CAPABILITIES) &&\r
42966+ (pAC->GIni.GP[PhysPortIndex].PhyType != SK_PHY_MARV_COPPER)) {\r
42967+ *pLen = 0;\r
42968+ return (SK_PNMI_ERR_NOT_SUPPORTED);\r
42969+ }\r
42970+\r
42971+ /* Check action type. */\r
42972+ if (Action == SK_PNMI_GET) {\r
42973+ /* Check length. */\r
42974+ switch (Id) {\r
42975+\r
42976+ case OID_SKGE_VCT_GET:\r
42977+ if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_PNMI_VCT)) {\r
42978+ *pLen = (Limit - PhysPortIndex) * sizeof(SK_PNMI_VCT);\r
42979+ return (SK_PNMI_ERR_TOO_SHORT);\r
42980+ }\r
42981+ break;\r
42982+\r
42983+ case OID_SKGE_VCT_STATUS:\r
42984+ case OID_SKGE_VCT_CAPABILITIES:\r
42985+ if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U8)) {\r
42986+ *pLen = (Limit - PhysPortIndex) * sizeof(SK_U8);\r
42987+ return (SK_PNMI_ERR_TOO_SHORT);\r
42988+ }\r
42989+ break;\r
42990+\r
42991+ default:\r
42992+ *pLen = 0;\r
42993+ return (SK_PNMI_ERR_GENERAL);\r
42994+ } \r
42995+\r
42996+ /* Get value. */\r
42997+ Offset = 0;\r
42998+ for (; PhysPortIndex < Limit; PhysPortIndex++) {\r
42999+\r
43000+ pPrt = &pAC->GIni.GP[PhysPortIndex];\r
43001+\r
43002+ switch (Id) {\r
43003+\r
43004+ case OID_SKGE_VCT_GET:\r
43005+ if (!pPrt->PHWLinkUp &&\r
43006+ (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_PENDING)) {\r
43007+\r
43008+ RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_FALSE);\r
43009+\r
43010+ if (RetCode == 0) {\r
43011+\r
43012+ /* VCT test is finished, so save the data. */\r
43013+ VctGetResults(pAC, IoC, PhysPortIndex);\r
43014+\r
43015+ Para.Para32[0] = PhysPortIndex;\r
43016+ Para.Para32[1] = -1;\r
43017+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Para);\r
43018+\r
43019+ /* SkEventDispatcher(pAC, IoC); */\r
43020+ }\r
43021+ }\r
43022+\r
43023+ /* Initialize backup data pointer. */\r
43024+ pVctBackupData = &pAC->Pnmi.VctBackup[PhysPortIndex];\r
43025+\r
43026+ /* Get all results. */\r
43027+ CheckVctStatus(pAC, IoC, pBuf, Offset, PhysPortIndex);\r
43028+\r
43029+ Offset++;\r
43030+ *(pBuf + Offset) = pPrt->PCableLen;\r
43031+ Offset++;\r
43032+ for (i = 0; i < 4; i++) {\r
43033+\r
43034+ SK_PNMI_STORE_U32((pBuf + Offset), pVctBackupData->MdiPairLen[i]);\r
43035+ Offset += sizeof(SK_U32);\r
43036+ }\r
43037+ for (i = 0; i < 4; i++) {\r
43038+\r
43039+ *(pBuf + Offset) = pVctBackupData->MdiPairSts[i];\r
43040+ Offset++;\r
43041+ }\r
43042+\r
43043+ RetCode = SK_PNMI_ERR_OK;\r
43044+ break;\r
43045+\r
43046+ case OID_SKGE_VCT_STATUS:\r
43047+ CheckVctStatus(pAC, IoC, pBuf, Offset, PhysPortIndex);\r
43048+\r
43049+ Offset++;\r
43050+ RetCode = SK_PNMI_ERR_OK;\r
43051+ break;\r
43052+\r
43053+ case OID_SKGE_VCT_CAPABILITIES:\r
43054+ if (pPrt->PhyType != SK_PHY_MARV_COPPER) {\r
43055+ *(pBuf + Offset) = SK_PNMI_VCT_NOT_SUPPORTED;\r
43056+ }\r
43057+ else {\r
43058+ *(pBuf + Offset) = SK_PNMI_VCT_SUPPORTED;\r
43059+ }\r
43060+ Offset++;\r
43061+\r
43062+ RetCode = SK_PNMI_ERR_OK;\r
43063+ break;\r
43064+\r
43065+ default:\r
43066+ *pLen = 0;\r
43067+ return (SK_PNMI_ERR_GENERAL);\r
43068+ }\r
43069+ } /* for */\r
43070+ *pLen = Offset;\r
43071+ return (RetCode);\r
43072+\r
43073+ } /* if SK_PNMI_GET */\r
43074+\r
43075+ /*\r
43076+ * From here SET or PRESET action. Check if the passed\r
43077+ * buffer length is plausible.\r
43078+ */\r
43079+\r
43080+ /* Check length. */\r
43081+ switch (Id) {\r
43082+ case OID_SKGE_VCT_SET:\r
43083+ if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U32)) {\r
43084+ *pLen = (Limit - PhysPortIndex) * sizeof(SK_U32);\r
43085+ return (SK_PNMI_ERR_TOO_SHORT);\r
43086+ }\r
43087+ break;\r
43088+\r
43089+ default:\r
43090+ *pLen = 0;\r
43091+ return (SK_PNMI_ERR_GENERAL);\r
43092+ }\r
43093+\r
43094+ /* Perform PRESET or SET. */\r
43095+\r
43096+ /* VCT does not support PRESET action. */\r
43097+ if (Action == SK_PNMI_PRESET) {\r
43098+\r
43099+ return (SK_PNMI_ERR_OK);\r
43100+ }\r
43101+\r
43102+ Offset = 0;\r
43103+ for (; PhysPortIndex < Limit; PhysPortIndex++) {\r
43104+\r
43105+ pPrt = &pAC->GIni.GP[PhysPortIndex];\r
43106+\r
43107+ switch (Id) {\r
43108+ case OID_SKGE_VCT_SET: /* Start VCT test. */\r
43109+ if (!pPrt->PHWLinkUp) {\r
43110+ SkGeStopPort(pAC, IoC, PhysPortIndex, SK_STOP_ALL, SK_SOFT_RST);\r
43111+\r
43112+ RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_TRUE);\r
43113+\r
43114+ if (RetCode == 0) { /* RetCode: 0 => Start! */\r
43115+ pAC->Pnmi.VctStatus[PhysPortIndex] |= SK_PNMI_VCT_PENDING;\r
43116+ pAC->Pnmi.VctStatus[PhysPortIndex] &=\r
43117+ ~(SK_PNMI_VCT_NEW_VCT_DATA | SK_PNMI_VCT_LINK);\r
43118+\r
43119+ /* Start VCT timer counter. */\r
43120+ SK_MEMSET((char *)&Para, 0, sizeof(Para));\r
43121+ Para.Para32[0] = PhysPortIndex;\r
43122+ Para.Para32[1] = -1;\r
43123+\r
43124+ SkTimerStart(pAC, IoC, &pAC->Pnmi.VctTimeout[PhysPortIndex],\r
43125+ SK_PNMI_VCT_TIMER_CHECK, SKGE_PNMI, SK_PNMI_EVT_VCT_RESET, Para);\r
43126+\r
43127+ SK_PNMI_STORE_U32((pBuf + Offset), RetCode);\r
43128+ RetCode = SK_PNMI_ERR_OK;\r
43129+ }\r
43130+ else { /* RetCode: 2 => Running! */\r
43131+ SK_PNMI_STORE_U32((pBuf + Offset), RetCode);\r
43132+ RetCode = SK_PNMI_ERR_OK;\r
43133+ }\r
43134+ }\r
43135+ else { /* RetCode: 4 => Link! */\r
43136+ RetCode = 4;\r
43137+ SK_PNMI_STORE_U32((pBuf + Offset), RetCode);\r
43138+ RetCode = SK_PNMI_ERR_OK;\r
43139+ }\r
43140+ Offset += sizeof(SK_U32);\r
43141+ break;\r
43142+\r
43143+ default:\r
43144+ *pLen = 0;\r
43145+ return (SK_PNMI_ERR_GENERAL);\r
43146+ }\r
43147+ } /* for */\r
43148+ *pLen = Offset;\r
43149+ return (RetCode);\r
43150+\r
43151+} /* Vct */\r
43152+\r
43153+\r
43154+PNMI_STATIC void VctGetResults(\r
43155+SK_AC *pAC,\r
43156+SK_IOC IoC,\r
43157+SK_U32 Port)\r
43158+{\r
43159+ SK_GEPORT *pPrt;\r
43160+ int i;\r
43161+ SK_U8 PairLen;\r
43162+ SK_U8 PairSts;\r
43163+ SK_U32 MinLength;\r
43164+ SK_U32 CableLength;\r
43165+\r
43166+ pPrt = &pAC->GIni.GP[Port];\r
43167+\r
43168+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) {\r
43169+ MinLength = 25;\r
43170+ }\r
43171+ else {\r
43172+ MinLength = 35;\r
43173+ }\r
43174+\r
43175+ /* Copy results for later use to PNMI struct. */\r
43176+ for (i = 0; i < 4; i++) {\r
43177+\r
43178+ PairLen = pPrt->PMdiPairLen[i];\r
43179+\r
43180+ if (((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) == 0) && (i > 1)) {\r
43181+ PairSts = SK_PNMI_VCT_NOT_PRESENT;\r
43182+ }\r
43183+ else {\r
43184+ PairSts = pPrt->PMdiPairSts[i];\r
43185+ }\r
43186+\r
43187+ if ((PairSts == SK_PNMI_VCT_NORMAL_CABLE) &&\r
43188+ (PairLen > 28) && (PairLen < 0xff)) {\r
43189+\r
43190+ PairSts = SK_PNMI_VCT_IMPEDANCE_MISMATCH;\r
43191+ }\r
43192+\r
43193+ /* Ignore values <= MinLength, the linear factor is 4/5. */\r
43194+ if ((PairLen > MinLength) && (PairLen < 0xff)) {\r
43195+ \r
43196+ CableLength = 1000UL * (PairLen - MinLength) * 4 / 5;\r
43197+ }\r
43198+ else {\r
43199+ /* No cable or short cable. */\r
43200+ CableLength = 0;\r
43201+ }\r
43202+\r
43203+ pAC->Pnmi.VctBackup[Port].MdiPairLen[i] = CableLength;\r
43204+ pAC->Pnmi.VctBackup[Port].MdiPairSts[i] = PairSts;\r
43205+ }\r
43206+\r
43207+ pAC->Pnmi.VctStatus[Port] &= ~SK_PNMI_VCT_PENDING;\r
43208+ pAC->Pnmi.VctStatus[Port] |= (SK_PNMI_VCT_NEW_VCT_DATA |\r
43209+ SK_PNMI_VCT_TEST_DONE);\r
43210+\r
43211+} /* GetVctResults */\r
43212+\r
43213+PNMI_STATIC void CheckVctStatus(\r
43214+SK_AC *pAC,\r
43215+SK_IOC IoC,\r
43216+char *pBuf,\r
43217+SK_U32 Offset,\r
43218+SK_U32 PhysPortIndex)\r
43219+{\r
43220+ SK_GEPORT *pPrt;\r
43221+ SK_PNMI_VCT *pVctData;\r
43222+ SK_U8 VctStatus;\r
43223+ SK_U32 RetCode;\r
43224+\r
43225+ pPrt = &pAC->GIni.GP[PhysPortIndex];\r
43226+\r
43227+ pVctData = (SK_PNMI_VCT *) (pBuf + Offset);\r
43228+ pVctData->VctStatus = SK_PNMI_VCT_NONE;\r
43229+\r
43230+ VctStatus = pAC->Pnmi.VctStatus[PhysPortIndex];\r
43231+\r
43232+ if (!pPrt->PHWLinkUp) {\r
43233+\r
43234+ /* Was a VCT test ever made before? */\r
43235+ if (VctStatus & SK_PNMI_VCT_TEST_DONE) {\r
43236+ if (VctStatus & SK_PNMI_VCT_LINK) {\r
43237+ pVctData->VctStatus |= SK_PNMI_VCT_OLD_VCT_DATA;\r
43238+ }\r
43239+ else {\r
43240+ pVctData->VctStatus |= SK_PNMI_VCT_NEW_VCT_DATA;\r
43241+ }\r
43242+ }\r
43243+\r
43244+ /* Check VCT test status. */\r
43245+ RetCode = SkGmCableDiagStatus(pAC,IoC, PhysPortIndex, SK_FALSE);\r
43246+\r
43247+ if (RetCode == 2) { /* VCT test is running. */\r
43248+ pVctData->VctStatus |= SK_PNMI_VCT_RUNNING;\r
43249+ }\r
43250+ else { /* VCT data was copied to pAC here. Check PENDING state. */\r
43251+ if (VctStatus & SK_PNMI_VCT_PENDING) {\r
43252+ pVctData->VctStatus |= SK_PNMI_VCT_NEW_VCT_DATA;\r
43253+ }\r
43254+ }\r
43255+\r
43256+ if (pPrt->PCableLen != 0xff) { /* Old DSP value. */\r
43257+ pVctData->VctStatus |= SK_PNMI_VCT_OLD_DSP_DATA;\r
43258+ }\r
43259+ }\r
43260+ else {\r
43261+ /* Was a VCT test ever made before? */\r
43262+ if (VctStatus & SK_PNMI_VCT_TEST_DONE) {\r
43263+ pVctData->VctStatus &= ~SK_PNMI_VCT_NEW_VCT_DATA;\r
43264+ pVctData->VctStatus |= SK_PNMI_VCT_OLD_VCT_DATA;\r
43265+ }\r
43266+\r
43267+ /* DSP only valid in 100/1000 modes. */\r
43268+ if (pPrt->PLinkSpeedUsed != SK_LSPEED_STAT_10MBPS) {\r
43269+ pVctData->VctStatus |= SK_PNMI_VCT_NEW_DSP_DATA;\r
43270+ }\r
43271+ }\r
43272+\r
43273+} /* CheckVctStatus */\r
43274+\r
43275+\r
43276+/*****************************************************************************\r
43277+ *\r
43278+ * SkPnmiGenIoctl - Handles new generic PNMI IOCTL, calls the needed\r
43279+ * PNMI function depending on the subcommand and\r
43280+ * returns all data belonging to the complete database\r
43281+ * or OID request.\r
43282+ *\r
43283+ * Description:\r
43284+ * Looks up the requested subcommand, calls the corresponding handler\r
43285+ * function and passes all required parameters to it.\r
43286+ * The function is called by the driver. It is needed to handle the new\r
43287+ * generic PNMI IOCTL. This IOCTL is given to the driver and contains both\r
43288+ * the OID and a subcommand to decide what kind of request has to be done.\r
43289+ *\r
43290+ * Returns:\r
43291+ * SK_PNMI_ERR_OK The request was successfully performed\r
43292+ * SK_PNMI_ERR_GENERAL A general severe internal error occured\r
43293+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to take\r
43294+ * the data.\r
43295+ * SK_PNMI_ERR_UNKNOWN_OID The requested OID is unknown\r
43296+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't\r
43297+ * exist (e.g. port instance 3 on a two port\r
43298+ * adapter.\r
43299+ */\r
43300+int SkPnmiGenIoctl(\r
43301+SK_AC *pAC, /* Pointer to adapter context struct */\r
43302+SK_IOC IoC, /* I/O context */\r
43303+void *pBuf, /* Buffer used for the management data transfer */\r
43304+unsigned int *pLen, /* Length of buffer */\r
43305+SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */\r
43306+{\r
43307+SK_I32 Mode; /* Store value of subcommand. */\r
43308+SK_U32 Oid; /* Store value of OID. */\r
43309+int ReturnCode; /* Store return value to show status of PNMI action. */\r
43310+int HeaderLength; /* Length of desired action plus OID. */\r
43311+\r
43312+ ReturnCode = SK_PNMI_ERR_GENERAL;\r
43313+ \r
43314+ SK_MEMCPY(&Mode, pBuf, sizeof(SK_I32));\r
43315+ SK_MEMCPY(&Oid, (char *)pBuf + sizeof(SK_I32), sizeof(SK_U32));\r
43316+ HeaderLength = sizeof(SK_I32) + sizeof(SK_U32);\r
43317+ *pLen = *pLen - HeaderLength;\r
43318+ SK_MEMCPY((char *)pBuf + sizeof(SK_I32), (char *)pBuf + HeaderLength, *pLen);\r
43319+ \r
43320+ switch(Mode) {\r
43321+ case SK_GET_SINGLE_VAR:\r
43322+ ReturnCode = SkPnmiGetVar(pAC, IoC, Oid,\r
43323+ (char *)pBuf + sizeof(SK_I32), pLen,\r
43324+ ((SK_U32) (-1)), NetIndex);\r
43325+ SK_PNMI_STORE_U32(pBuf, ReturnCode);\r
43326+ *pLen = *pLen + sizeof(SK_I32);\r
43327+ break;\r
43328+ case SK_PRESET_SINGLE_VAR:\r
43329+ ReturnCode = SkPnmiPreSetVar(pAC, IoC, Oid,\r
43330+ (char *)pBuf + sizeof(SK_I32), pLen,\r
43331+ ((SK_U32) (-1)), NetIndex);\r
43332+ SK_PNMI_STORE_U32(pBuf, ReturnCode);\r
43333+ *pLen = *pLen + sizeof(SK_I32);\r
43334+ break;\r
43335+ case SK_SET_SINGLE_VAR:\r
43336+ ReturnCode = SkPnmiSetVar(pAC, IoC, Oid,\r
43337+ (char *)pBuf + sizeof(SK_I32), pLen,\r
43338+ ((SK_U32) (-1)), NetIndex);\r
43339+ SK_PNMI_STORE_U32(pBuf, ReturnCode);\r
43340+ *pLen = *pLen + sizeof(SK_I32);\r
43341+ break;\r
43342+ case SK_GET_FULL_MIB:\r
43343+ ReturnCode = SkPnmiGetStruct(pAC, IoC, pBuf, pLen, NetIndex);\r
43344+ break;\r
43345+ case SK_PRESET_FULL_MIB:\r
43346+ ReturnCode = SkPnmiPreSetStruct(pAC, IoC, pBuf, pLen, NetIndex);\r
43347+ break;\r
43348+ case SK_SET_FULL_MIB:\r
43349+ ReturnCode = SkPnmiSetStruct(pAC, IoC, pBuf, pLen, NetIndex);\r
43350+ break;\r
43351+ default:\r
43352+ break;\r
43353+ }\r
43354+ \r
43355+ return (ReturnCode);\r
43356+\r
43357+} /* SkGeIocGen */\r
43358+\r
43359+#ifdef SK_ASF\r
43360+/*****************************************************************************\r
43361+ *\r
43362+ * Asf\r
43363+ *\r
43364+ * Description:\r
43365+ * The code is simple. No description necessary.\r
43366+ *\r
43367+ * Returns:\r
43368+ * SK_PNMI_ERR_OK The request was successfully performed.\r
43369+ * SK_PNMI_ERR_GENERAL A general severe internal error occured.\r
43370+ * SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to contain\r
43371+ * the correct data (e.g. a 32bit value is\r
43372+ * needed, but a 16 bit value was passed).\r
43373+ * SK_PNMI_ERR_UNKNOWN_INST The requested instance of the OID doesn't\r
43374+ * exist (e.g. port instance 3 on a two port\r
43375+ * adapter.\r
43376+ */\r
43377+\r
43378+PNMI_STATIC int Asf(\r
43379+SK_AC *pAC, /* Pointer to adapter context */\r
43380+SK_IOC IoC, /* IO context handle */\r
43381+int Action, /* GET/PRESET/SET action */\r
43382+SK_U32 Id, /* Object ID that is to be processed */\r
43383+char *pBuf, /* Buffer used for the management data transfer */\r
43384+unsigned int *pLen, /* On call: pBuf buffer length. On return: used buffer */\r
43385+SK_U32 Instance, /* Instance (1..n) that is to be queried or -1 */\r
43386+unsigned int TableIndex, /* Index to the Id table */\r
43387+SK_U32 NetIndex) /* NetIndex (0..n), in single net mode always zero */\r
43388+{\r
43389+ SK_U32 RetCode = SK_PNMI_ERR_GENERAL;\r
43390+\r
43391+ /*\r
43392+ * Check instance. We only handle single instance variables.\r
43393+ */\r
43394+ if (Instance != (SK_U32)(-1) && Instance != 1) {\r
43395+\r
43396+ *pLen = 0;\r
43397+ return (SK_PNMI_ERR_UNKNOWN_INST);\r
43398+ }\r
43399+\r
43400+ /* Perform action. */\r
43401+ /* GET value. */\r
43402+ if (Action == SK_PNMI_GET) {\r
43403+ switch (Id) {\r
43404+ case OID_SKGE_ASF: \r
43405+ RetCode = SkAsfGet(pAC, IoC, (SK_U8 *) pBuf, pLen);\r
43406+ break;\r
43407+ default:\r
43408+ RetCode = SkAsfGetOid( pAC, IoC, Id, Instance, (SK_U8 *) pBuf, pLen );\r
43409+ break;\r
43410+ }\r
43411+\r
43412+ return (RetCode); \r
43413+ }\r
43414+\r
43415+ /* PRESET value. */\r
43416+ if (Action == SK_PNMI_PRESET) { \r
43417+ switch (Id) {\r
43418+ case OID_SKGE_ASF:\r
43419+ RetCode = SkAsfPreSet(pAC, IoC, (SK_U8 *) pBuf, pLen);\r
43420+ break;\r
43421+ default:\r
43422+ RetCode = SkAsfPreSetOid( pAC, IoC, Id, Instance, (SK_U8 *) pBuf, pLen );\r
43423+ break;\r
43424+ }\r
43425+ }\r
43426+\r
43427+ /* SET value. */\r
43428+ if (Action == SK_PNMI_SET) {\r
43429+ switch (Id) {\r
43430+ case OID_SKGE_ASF:\r
43431+ RetCode = SkAsfSet(pAC, IoC, (SK_U8 *) pBuf, pLen);\r
43432+ break;\r
43433+ default:\r
43434+ RetCode = SkAsfSetOid( pAC, IoC, Id, Instance, (SK_U8 *) pBuf, pLen );\r
43435+ break;\r
43436+ }\r
43437+ }\r
43438+ return (RetCode);\r
43439+}\r
43440+#endif /* SK_ASF */\r
43441diff -ruN linux/drivers/net/sk98lin/skgesirq.c linux-new/drivers/net/sk98lin/skgesirq.c
43442--- linux/drivers/net/sk98lin/skgesirq.c 2006-04-11 19:19:28.000000000 +0200
43443+++ linux-new/drivers/net/sk98lin/skgesirq.c 2006-01-18 14:37:24.000000000 +0100
43444@@ -2,23 +2,24 @@
43445 *
43446 * Name: skgesirq.c
43447 * Project: Gigabit Ethernet Adapters, Common Modules
43448- * Version: $Revision$
43449- * Date: $Date$
43450+ * Version: $Revision$
43451+ * Date: $Date$
43452 * Purpose: Special IRQ module
43453 *
43454 ******************************************************************************/
43455
43456 /******************************************************************************
43457 *
43458+ * LICENSE:
43459 * (C)Copyright 1998-2002 SysKonnect.
43460- * (C)Copyright 2002-2003 Marvell.
43461+ * (C)Copyright 2002-2005 Marvell.
43462 *
43463 * This program is free software; you can redistribute it and/or modify
43464 * it under the terms of the GNU General Public License as published by
43465 * the Free Software Foundation; either version 2 of the License, or
43466 * (at your option) any later version.
43467- *
43468 * The information in this file is provided "AS IS" without warranty.
43469+ * /LICENSE
43470 *
43471 ******************************************************************************/
43472
43473@@ -38,7 +39,7 @@
43474 * right after this ISR.
43475 *
43476 * The Interrupt source register of the adapter is NOT read by this module.
43477- * SO if the drivers implementor needs a while loop around the
43478+ * SO if the drivers implementor needs a while loop around the
43479 * slow data paths interrupt bits, he needs to call the SkGeSirqIsr() for
43480 * each loop entered.
43481 *
43482@@ -46,11 +47,6 @@
43483 *
43484 */
43485
43486-#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
43487-static const char SysKonnectFileId[] =
43488- "@(#) $Id$ (C) Marvell.";
43489-#endif
43490-
43491 #include "h/skdrv1st.h" /* Driver Specific Definitions */
43492 #ifndef SK_SLIM
43493 #include "h/skgepnmi.h" /* PNMI Definitions */
43494@@ -58,6 +54,13 @@
43495 #endif
43496 #include "h/skdrv2nd.h" /* Adapter Control and Driver specific Def. */
43497
43498+/* local variables ************************************************************/
43499+
43500+#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
43501+static const char SysKonnectFileId[] =
43502+ "@(#) $Id$ (C) Marvell.";
43503+#endif
43504+
43505 /* local function prototypes */
43506 #ifdef GENESIS
43507 static int SkGePortCheckUpXmac(SK_AC*, SK_IOC, int, SK_BOOL);
43508@@ -86,7 +89,7 @@
43509 XM_RXF_511B,
43510 XM_RXF_1023B,
43511 XM_RXF_MAX_SZ
43512-} ;
43513+};
43514 #endif /* GENESIS */
43515
43516 #ifdef __C2MAN__
43517@@ -109,8 +112,8 @@
43518 * Returns: N/A
43519 */
43520 static void SkHWInitDefSense(
43521-SK_AC *pAC, /* adapter context */
43522-SK_IOC IoC, /* IO context */
43523+SK_AC *pAC, /* Adapter Context */
43524+SK_IOC IoC, /* I/O context */
43525 int Port) /* Port Index (MAC_1 + n) */
43526 {
43527 SK_GEPORT *pPrt; /* GIni Port struct pointer */
43528@@ -119,7 +122,7 @@
43529
43530 pPrt->PAutoNegTimeOut = 0;
43531
43532- if (pPrt->PLinkModeConf != SK_LMODE_AUTOSENSE) {
43533+ if (pPrt->PLinkModeConf != (SK_U8)SK_LMODE_AUTOSENSE) {
43534 pPrt->PLinkMode = pPrt->PLinkModeConf;
43535 return;
43536 }
43537@@ -145,8 +148,8 @@
43538 *
43539 */
43540 static SK_U8 SkHWSenseGetNext(
43541-SK_AC *pAC, /* adapter context */
43542-SK_IOC IoC, /* IO context */
43543+SK_AC *pAC, /* Adapter Context */
43544+SK_IOC IoC, /* I/O context */
43545 int Port) /* Port Index (MAC_1 + n) */
43546 {
43547 SK_GEPORT *pPrt; /* GIni Port struct pointer */
43548@@ -155,18 +158,18 @@
43549
43550 pPrt->PAutoNegTimeOut = 0;
43551
43552- if (pPrt->PLinkModeConf != (SK_U8)SK_LMODE_AUTOSENSE) {
43553+ if (pPrt->PLinkModeConf != (SK_U8)SK_LMODE_AUTOSENSE) {
43554 /* Leave all as configured */
43555 return(pPrt->PLinkModeConf);
43556 }
43557
43558- if (pPrt->PLinkMode == (SK_U8)SK_LMODE_AUTOFULL) {
43559+ if (pPrt->PLinkMode == (SK_U8)SK_LMODE_AUTOFULL) {
43560 /* Return next mode AUTOBOTH */
43561- return ((SK_U8)SK_LMODE_AUTOBOTH);
43562+ return((SK_U8)SK_LMODE_AUTOBOTH);
43563 }
43564
43565 /* Return default autofull */
43566- return ((SK_U8)SK_LMODE_AUTOFULL);
43567+ return((SK_U8)SK_LMODE_AUTOFULL);
43568 } /* SkHWSenseGetNext */
43569
43570
43571@@ -179,8 +182,8 @@
43572 * Returns: N/A
43573 */
43574 static void SkHWSenseSetNext(
43575-SK_AC *pAC, /* adapter context */
43576-SK_IOC IoC, /* IO context */
43577+SK_AC *pAC, /* Adapter Context */
43578+SK_IOC IoC, /* I/O context */
43579 int Port, /* Port Index (MAC_1 + n) */
43580 SK_U8 NewMode) /* New Mode to be written in sense mode */
43581 {
43582@@ -190,7 +193,7 @@
43583
43584 pPrt->PAutoNegTimeOut = 0;
43585
43586- if (pPrt->PLinkModeConf != (SK_U8)SK_LMODE_AUTOSENSE) {
43587+ if (pPrt->PLinkModeConf != (SK_U8)SK_LMODE_AUTOSENSE) {
43588 return;
43589 }
43590
43591@@ -214,8 +217,8 @@
43592 * Returns: N/A
43593 */
43594 void SkHWLinkDown(
43595-SK_AC *pAC, /* adapter context */
43596-SK_IOC IoC, /* IO context */
43597+SK_AC *pAC, /* Adapter Context */
43598+SK_IOC IoC, /* I/O context */
43599 int Port) /* Port Index (MAC_1 + n) */
43600 {
43601 SK_GEPORT *pPrt; /* GIni Port struct pointer */
43602@@ -227,11 +230,11 @@
43603
43604 /* Disable Receiver and Transmitter */
43605 SkMacRxTxDisable(pAC, IoC, Port);
43606-
43607+
43608 /* Init default sense mode */
43609 SkHWInitDefSense(pAC, IoC, Port);
43610
43611- if (pPrt->PHWLinkUp == SK_FALSE) {
43612+ if (!pPrt->PHWLinkUp) {
43613 return;
43614 }
43615
43616@@ -241,10 +244,12 @@
43617 /* Set Link to DOWN */
43618 pPrt->PHWLinkUp = SK_FALSE;
43619
43620+#ifndef SK_SLIM
43621 /* Reset Port stati */
43622- pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN;
43623- pPrt->PFlowCtrlStatus = (SK_U8)SK_FLOW_STAT_NONE;
43624+ pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN;
43625+ pPrt->PFlowCtrlStatus = (SK_U8)SK_FLOW_STAT_NONE;
43626 pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_INDETERMINATED;
43627+#endif /* !SK_SLIM */
43628
43629 /* Re-init Phy especially when the AutoSense default is set now */
43630 SkMacInitPhy(pAC, IoC, Port, SK_FALSE);
43631@@ -266,8 +271,8 @@
43632 * Returns: N/A
43633 */
43634 void SkHWLinkUp(
43635-SK_AC *pAC, /* adapter context */
43636-SK_IOC IoC, /* IO context */
43637+SK_AC *pAC, /* Adapter Context */
43638+SK_IOC IoC, /* I/O context */
43639 int Port) /* Port Index (MAC_1 + n) */
43640 {
43641 SK_GEPORT *pPrt; /* GIni Port struct pointer */
43642@@ -280,12 +285,14 @@
43643 }
43644
43645 pPrt->PHWLinkUp = SK_TRUE;
43646+
43647+#ifndef SK_SLIM
43648 pPrt->PAutoNegFail = SK_FALSE;
43649- pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN;
43650+ pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN;
43651
43652- if (pPrt->PLinkMode != (SK_U8)SK_LMODE_AUTOHALF &&
43653- pPrt->PLinkMode != (SK_U8)SK_LMODE_AUTOFULL &&
43654- pPrt->PLinkMode != (SK_U8)SK_LMODE_AUTOBOTH) {
43655+ if (pPrt->PLinkMode != (SK_U8)SK_LMODE_AUTOHALF &&
43656+ pPrt->PLinkMode != (SK_U8)SK_LMODE_AUTOFULL &&
43657+ pPrt->PLinkMode != (SK_U8)SK_LMODE_AUTOBOTH) {
43658 /* Link is up and no Auto-negotiation should be done */
43659
43660 /* Link speed should be the configured one */
43661@@ -293,7 +300,9 @@
43662 case SK_LSPEED_AUTO:
43663 /* default is 1000 Mbps */
43664 case SK_LSPEED_1000MBPS:
43665- pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_1000MBPS;
43666+ pPrt->PLinkSpeedUsed =
43667+ (SK_U8)((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) ?
43668+ SK_LSPEED_STAT_1000MBPS : SK_LSPEED_STAT_100MBPS;
43669 break;
43670 case SK_LSPEED_100MBPS:
43671 pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_100MBPS;
43672@@ -304,19 +313,22 @@
43673 }
43674
43675 /* Set Link Mode Status */
43676- if (pPrt->PLinkMode == SK_LMODE_FULL) {
43677+ if (pPrt->PLinkMode == (SK_U8)SK_LMODE_FULL) {
43678 pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_FULL;
43679 }
43680 else {
43681- pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_HALF;
43682+ pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_HALF;
43683 }
43684
43685 /* No flow control without auto-negotiation */
43686- pPrt->PFlowCtrlStatus = (SK_U8)SK_FLOW_STAT_NONE;
43687+ pPrt->PFlowCtrlStatus = (SK_U8)SK_FLOW_STAT_NONE;
43688+#endif /* !SK_SLIM */
43689
43690 /* enable Rx/Tx */
43691- (void)SkMacRxTxEnable(pAC, IoC, Port);
43692+ (void)SkMacRxTxEnable(pAC, IoC, Port);
43693+#ifndef SK_SLIM
43694 }
43695+#endif /* !SK_SLIM */
43696 } /* SkHWLinkUp */
43697
43698
43699@@ -329,14 +341,16 @@
43700 * Returns: N/A
43701 */
43702 static void SkMacParity(
43703-SK_AC *pAC, /* adapter context */
43704-SK_IOC IoC, /* IO context */
43705-int Port) /* Port Index of the port failed */
43706+SK_AC *pAC, /* Adapter Context */
43707+SK_IOC IoC, /* I/O context */
43708+int Port) /* Port Index (MAC_1 + n) */
43709 {
43710 SK_EVPARA Para;
43711 SK_GEPORT *pPrt; /* GIni Port struct pointer */
43712 SK_U32 TxMax; /* Tx Max Size Counter */
43713
43714+ TxMax = 0;
43715+
43716 pPrt = &pAC->GIni.GP[Port];
43717
43718 /* Clear IRQ Tx Parity Error */
43719@@ -346,7 +360,7 @@
43720 SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_CLR_PERR);
43721 }
43722 #endif /* GENESIS */
43723-
43724+
43725 #ifdef YUKON
43726 if (pAC->GIni.GIYukon) {
43727 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
43728@@ -355,7 +369,7 @@
43729 pAC->GIni.GIChipRev == 0) ? GMF_CLI_TX_FC : GMF_CLI_TX_PE));
43730 }
43731 #endif /* YUKON */
43732-
43733+
43734 if (pPrt->PCheckPar) {
43735
43736 if (Port == MAC_1) {
43737@@ -366,7 +380,7 @@
43738 }
43739 Para.Para64 = Port;
43740 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
43741-
43742+
43743 Para.Para32[0] = Port;
43744 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
43745
43746@@ -378,18 +392,18 @@
43747 if (pAC->GIni.GIGenesis) {
43748 /* Snap statistic counters */
43749 (void)SkXmUpdateStats(pAC, IoC, Port);
43750-
43751+
43752 (void)SkXmMacStatistic(pAC, IoC, Port, XM_TXF_MAX_SZ, &TxMax);
43753 }
43754 #endif /* GENESIS */
43755-
43756+
43757 #ifdef YUKON
43758 if (pAC->GIni.GIYukon) {
43759
43760 (void)SkGmMacStatistic(pAC, IoC, Port, GM_TXF_1518B, &TxMax);
43761 }
43762 #endif /* YUKON */
43763-
43764+
43765 if (TxMax > 0) {
43766 /* From now on check the parity */
43767 pPrt->PCheckPar = SK_TRUE;
43768@@ -399,15 +413,15 @@
43769
43770 /******************************************************************************
43771 *
43772- * SkGeHwErr() - Hardware Error service routine
43773+ * SkGeYuHwErr() - Hardware Error service routine (Genesis and Yukon)
43774 *
43775 * Description: handles all HW Error interrupts
43776 *
43777 * Returns: N/A
43778 */
43779-static void SkGeHwErr(
43780-SK_AC *pAC, /* adapter context */
43781-SK_IOC IoC, /* IO context */
43782+static void SkGeYuHwErr(
43783+SK_AC *pAC, /* Adapter Context */
43784+SK_IOC IoC, /* I/O context */
43785 SK_U32 HwStatus) /* Interrupt status word */
43786 {
43787 SK_EVPARA Para;
43788@@ -423,10 +437,10 @@
43789 }
43790
43791 /* Reset all bits in the PCI STATUS register */
43792- SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);
43793-
43794+ SK_IN16(IoC, PCI_C(pAC, PCI_STATUS), &Word);
43795+
43796 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
43797- SK_OUT16(IoC, PCI_C(PCI_STATUS), (SK_U16)(Word | PCI_ERRBITS));
43798+ SK_OUT16(IoC, PCI_C(pAC, PCI_STATUS), (SK_U16)(Word | PCI_ERRBITS));
43799 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
43800
43801 Para.Para64 = 0;
43802@@ -461,7 +475,7 @@
43803 }
43804 }
43805 #endif /* GENESIS */
43806-
43807+
43808 #ifdef YUKON
43809 if (pAC->GIni.GIYukon) {
43810 /* This is necessary only for Rx timing measurements */
43811@@ -484,14 +498,18 @@
43812 #endif /* YUKON */
43813
43814 if ((HwStatus & IS_RAM_RD_PAR) != 0) {
43815+
43816 SK_OUT16(IoC, B3_RI_CTRL, RI_CLR_RD_PERR);
43817+
43818 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E014, SKERR_SIRQ_E014MSG);
43819 Para.Para64 = 0;
43820 SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
43821 }
43822
43823 if ((HwStatus & IS_RAM_WR_PAR) != 0) {
43824+
43825 SK_OUT16(IoC, B3_RI_CTRL, RI_CLR_WR_PERR);
43826+
43827 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E015, SKERR_SIRQ_E015MSG);
43828 Para.Para64 = 0;
43829 SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
43830@@ -512,7 +530,7 @@
43831 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E018, SKERR_SIRQ_E018MSG);
43832 Para.Para64 = MAC_1;
43833 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
43834-
43835+
43836 Para.Para32[0] = MAC_1;
43837 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
43838 }
43839@@ -524,37 +542,288 @@
43840 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E019, SKERR_SIRQ_E019MSG);
43841 Para.Para64 = MAC_2;
43842 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
43843-
43844+
43845 Para.Para32[0] = MAC_2;
43846 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
43847 }
43848-} /* SkGeHwErr */
43849+} /* SkGeYuHwErr */
43850+
43851+#ifdef YUK2
43852+/******************************************************************************
43853+ *
43854+ * SkYuk2HwPortErr() - Service HW Errors for specified port (Yukon-2 only)
43855+ *
43856+ * Description: handles the HW Error interrupts for a specific port.
43857+ *
43858+ * Returns: N/A
43859+ */
43860+static void SkYuk2HwPortErr(
43861+SK_AC *pAC, /* Adapter Context */
43862+SK_IOC IoC, /* I/O Context */
43863+SK_U32 HwStatus, /* Interrupt status word */
43864+int Port) /* Port Index (MAC_1 + n) */
43865+{
43866+ SK_EVPARA Para;
43867+ int Queue;
43868+
43869+ if (Port == MAC_2) {
43870+ HwStatus >>= 8;
43871+ }
43872+
43873+ if ((HwStatus & Y2_HWE_L1_MASK) == 0) {
43874+ return;
43875+ }
43876
43877+ if ((HwStatus & Y2_IS_PAR_RD1) != 0) {
43878+ /* Clear IRQ */
43879+ SK_OUT16(IoC, SELECT_RAM_BUFFER(Port, B3_RI_CTRL), RI_CLR_RD_PERR);
43880+
43881+ if (Port == MAC_1) {
43882+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E028, SKERR_SIRQ_E028MSG);
43883+ }
43884+ else {
43885+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E030, SKERR_SIRQ_E030MSG);
43886+ }
43887+ }
43888+
43889+ if ((HwStatus & Y2_IS_PAR_WR1) != 0) {
43890+ /* Clear IRQ */
43891+ SK_OUT16(IoC, SELECT_RAM_BUFFER(Port, B3_RI_CTRL), RI_CLR_WR_PERR);
43892+
43893+ if (Port == MAC_1) {
43894+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E029, SKERR_SIRQ_E029MSG);
43895+ }
43896+ else {
43897+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E031, SKERR_SIRQ_E031MSG);
43898+ }
43899+ }
43900+
43901+ if ((HwStatus & Y2_IS_PAR_MAC1) != 0) {
43902+ /* Clear IRQ */
43903+ SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
43904+
43905+ if (Port == MAC_1) {
43906+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E016, SKERR_SIRQ_E016MSG);
43907+ }
43908+ else {
43909+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E017, SKERR_SIRQ_E017MSG);
43910+ }
43911+ }
43912+
43913+ if ((HwStatus & Y2_IS_PAR_RX1) != 0) {
43914+ if (Port == MAC_1) {
43915+ Queue = Q_R1;
43916+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E018, SKERR_SIRQ_E018MSG);
43917+ }
43918+ else {
43919+ Queue = Q_R2;
43920+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E019, SKERR_SIRQ_E019MSG);
43921+ }
43922+ /* Clear IRQ */
43923+ SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_PAR);
43924+ }
43925+
43926+ if ((HwStatus & Y2_IS_TCP_TXS1) != 0) {
43927+ if (Port == MAC_1) {
43928+ Queue = Q_XS1;
43929+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E033, SKERR_SIRQ_E033MSG);
43930+ }
43931+ else {
43932+ Queue = Q_XS2;
43933+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E035, SKERR_SIRQ_E035MSG);
43934+ }
43935+ /* Clear IRQ */
43936+ SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_TCP);
43937+ }
43938+
43939+ if ((HwStatus & Y2_IS_TCP_TXA1) != 0) {
43940+ if (Port == MAC_1) {
43941+ Queue = Q_XA1;
43942+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E032, SKERR_SIRQ_E032MSG);
43943+ }
43944+ else {
43945+ Queue = Q_XA2;
43946+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E034, SKERR_SIRQ_E034MSG);
43947+ }
43948+ /* Clear IRQ */
43949+ SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_TCP);
43950+ }
43951+
43952+ Para.Para64 = Port;
43953+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
43954+
43955+ Para.Para32[0] = Port;
43956+ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
43957+
43958+} /* SkYuk2HwPortErr */
43959
43960 /******************************************************************************
43961 *
43962- * SkGeSirqIsr() - Special Interrupt Service Routine
43963+ * SkYuk2HwErr() - Hardware Error service routine (Yukon-2 only)
43964 *
43965- * Description: handles all non data transfer specific interrupts (slow path)
43966+ * Description: handles all HW Error interrupts
43967+ *
43968+ * Returns: N/A
43969+ */
43970+static void SkYuk2HwErr(
43971+SK_AC *pAC, /* Adapter Context */
43972+SK_IOC IoC, /* I/O Context */
43973+SK_U32 HwStatus) /* Interrupt status word */
43974+{
43975+ SK_EVPARA Para;
43976+ SK_U16 Word;
43977+ SK_U32 DWord;
43978+ SK_U32 TlpHead[4];
43979+ int i;
43980+
43981+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
43982+ ("HW-Error Status: 0x%08lX\n", HwStatus));
43983+
43984+ /* This is necessary only for Rx timing measurements */
43985+ if ((HwStatus & Y2_IS_TIST_OV) != 0) {
43986+ /* increment Time Stamp Timer counter (high) */
43987+ pAC->GIni.GITimeStampCnt++;
43988+
43989+ /* Clear Time Stamp Timer IRQ */
43990+ SK_OUT8(IoC, GMAC_TI_ST_CTRL, (SK_U8)GMT_ST_CLR_IRQ);
43991+ }
43992+
43993+ /* Evaluate Y2_IS_PCI_NEXP before Y2_IS_MST_ERR or Y2_IS_IRQ_STAT */
43994+ if ((HwStatus & Y2_IS_PCI_NEXP) != 0) {
43995+ /*
43996+ * This error is also mapped either to Master Abort (Y2_IS_MST_ERR)
43997+ * or Target Abort (Y2_IS_IRQ_STAT) bit and can only be cleared there.
43998+ * Therefore handle this event just by printing an error log entry.
43999+ */
44000+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E027, SKERR_SIRQ_E027MSG);
44001+ }
44002+
44003+ if ((HwStatus & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) {
44004+ /* PCI Errors occured */
44005+ if ((HwStatus & Y2_IS_IRQ_STAT) != 0) {
44006+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E013, SKERR_SIRQ_E013MSG);
44007+ }
44008+ else {
44009+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E012, SKERR_SIRQ_E012MSG);
44010+ }
44011+
44012+ /* Reset all bits in the PCI STATUS register */
44013+ SK_IN16(IoC, PCI_C(pAC, PCI_STATUS), &Word);
44014+
44015+ SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
44016+ SK_OUT16(IoC, PCI_C(pAC, PCI_STATUS), (SK_U16)(Word | PCI_ERRBITS));
44017+ SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
44018+
44019+ Para.Para64 = 0;
44020+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
44021+ }
44022+
44023+ /* check for PCI-Express Uncorrectable Error */
44024+ if ((HwStatus & Y2_IS_PCI_EXP) != 0) {
44025+ /*
44026+ * On PCI-Express bus bridges are called root complexes (RC).
44027+ * PCI-Express errors are recognized by the root complex too,
44028+ * which requests the system to handle the problem. After error
44029+ * occurence it may be that no access to the adapter may be performed
44030+ * any longer.
44031+ */
44032+
44033+ /* Get uncorrectable error status */
44034+ SK_IN32(IoC, PCI_C(pAC, PEX_UNC_ERR_STAT), &DWord);
44035+
44036+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
44037+ ("PEX Uncorr.Error Status: 0x%08lX\n", DWord));
44038+
44039+ if (DWord != PEX_UNSUP_REQ) {
44040+ /* ignore Unsupported Request Errors */
44041+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E026, SKERR_SIRQ_E026MSG);
44042+ }
44043+
44044+ if ((DWord & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) {
44045+ /*
44046+ * Stop only, if the uncorrectable error is fatal or
44047+ * Poisoned TLP occured
44048+ */
44049+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, ("Header Log:"));
44050+
44051+ for (i = 0; i < 4; i++) {
44052+ /* get TLP Header from Log Registers */
44053+ SK_IN32(IoC, PCI_C(pAC, PEX_HEADER_LOG + i*4), &TlpHead[i]);
44054+
44055+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
44056+ (" 0x%08lX", TlpHead[i]));
44057+ }
44058+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ, ("\n"));
44059+
44060+ /* check for vendor defined broadcast message */
44061+ if (TlpHead[0] == 0x73004001 && (SK_U8)TlpHead[1] == 0x7f) {
44062+
44063+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
44064+ ("Vendor defined broadcast message\n"));
44065+ }
44066+ else {
44067+ Para.Para64 = 0;
44068+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
44069+
44070+ pAC->GIni.GIValHwIrqMask &= ~Y2_IS_PCI_EXP;
44071+ /* Rewrite HW IRQ mask */
44072+ SK_OUT32(IoC, B0_HWE_IMSK, pAC->GIni.GIValHwIrqMask);
44073+ }
44074+ }
44075+ /* clear the interrupt */
44076+ SK_OUT32(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
44077+ SK_OUT32(IoC, PCI_C(pAC, PEX_UNC_ERR_STAT), 0xffffffffUL);
44078+ SK_OUT32(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
44079+ }
44080+
44081+ for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
44082+
44083+ SkYuk2HwPortErr(pAC, IoC, HwStatus, i);
44084+ }
44085+
44086+} /* SkYuk2HwErr */
44087+#endif /* YUK2 */
44088+
44089+/******************************************************************************
44090+ *
44091+ * SkGeSirqIsr() - Wrapper for Special Interrupt Service Routine
44092+ *
44093+ * Description: calls the preselected special ISR (slow path)
44094 *
44095 * Returns: N/A
44096 */
44097 void SkGeSirqIsr(
44098-SK_AC *pAC, /* adapter context */
44099-SK_IOC IoC, /* IO context */
44100+SK_AC *pAC, /* Adapter Context */
44101+SK_IOC IoC, /* I/O context */
44102+SK_U32 Istatus) /* Interrupt status word */
44103+{
44104+ pAC->GIni.GIFunc.pSkGeSirqIsr(pAC, IoC, Istatus);
44105+}
44106+
44107+/******************************************************************************
44108+ *
44109+ * SkGeYuSirqIsr() - Special Interrupt Service Routine
44110+ *
44111+ * Description: handles all non data transfer specific interrupts (slow path)
44112+ *
44113+ * Returns: N/A
44114+ */
44115+void SkGeYuSirqIsr(
44116+SK_AC *pAC, /* Adapter Context */
44117+SK_IOC IoC, /* I/O Context */
44118 SK_U32 Istatus) /* Interrupt status word */
44119 {
44120 SK_EVPARA Para;
44121 SK_U32 RegVal32; /* Read register value */
44122 SK_GEPORT *pPrt; /* GIni Port struct pointer */
44123- SK_U16 PhyInt;
44124+ SK_U16 PhyInt;
44125 int i;
44126
44127 if (((Istatus & IS_HW_ERR) & pAC->GIni.GIValIrqMask) != 0) {
44128 /* read the HW Error Interrupt source */
44129 SK_IN32(IoC, B0_HWE_ISRC, &RegVal32);
44130-
44131- SkGeHwErr(pAC, IoC, RegVal32);
44132+
44133+ SkGeYuHwErr(pAC, IoC, RegVal32);
44134 }
44135
44136 /*
44137@@ -569,7 +838,7 @@
44138 }
44139
44140 if (((Istatus & (IS_PA_TO_RX2 | IS_PA_TO_TX2)) != 0) &&
44141- pAC->GIni.GP[MAC_2].PState == SK_PRT_RESET) {
44142+ pAC->GIni.GP[MAC_2].PState == SK_PRT_RESET) {
44143 /* MAC 2 was not initialized but Packet timeout occured */
44144 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E005,
44145 SKERR_SIRQ_E005MSG);
44146@@ -590,8 +859,8 @@
44147 }
44148
44149 if ((Istatus & IS_PA_TO_TX1) != 0) {
44150-
44151- pPrt = &pAC->GIni.GP[0];
44152+
44153+ pPrt = &pAC->GIni.GP[MAC_1];
44154
44155 /* May be a normal situation in a server with a slow network */
44156 SK_OUT16(IoC, B3_PA_CTRL, PA_CLR_TO_TX1);
44157@@ -612,25 +881,18 @@
44158 * we ignore those
44159 */
44160 pPrt->HalfDupTimerActive = SK_TRUE;
44161-#ifdef XXX
44162- Len = sizeof(SK_U64);
44163- SkPnmiGetVar(pAC, IoC, OID_SKGE_STAT_TX_OCTETS, (char *)&Octets,
44164- &Len, (SK_U32)SK_PNMI_PORT_PHYS2INST(pAC, 0),
44165- pAC->Rlmt.Port[0].Net->NetNumber);
44166-
44167- pPrt->LastOctets = Octets;
44168-#endif /* XXX */
44169+
44170 /* Snap statistic counters */
44171 (void)SkXmUpdateStats(pAC, IoC, 0);
44172
44173 (void)SkXmMacStatistic(pAC, IoC, 0, XM_TXO_OK_HI, &RegVal32);
44174
44175 pPrt->LastOctets = (SK_U64)RegVal32 << 32;
44176-
44177+
44178 (void)SkXmMacStatistic(pAC, IoC, 0, XM_TXO_OK_LO, &RegVal32);
44179
44180 pPrt->LastOctets += RegVal32;
44181-
44182+
44183 Para.Para32[0] = 0;
44184 SkTimerStart(pAC, IoC, &pPrt->HalfDupChkTimer, SK_HALFDUP_CHK_TIME,
44185 SKGE_HWAC, SK_HWEV_HALFDUP_CHK, Para);
44186@@ -640,8 +902,8 @@
44187 }
44188
44189 if ((Istatus & IS_PA_TO_TX2) != 0) {
44190-
44191- pPrt = &pAC->GIni.GP[1];
44192+
44193+ pPrt = &pAC->GIni.GP[MAC_2];
44194
44195 /* May be a normal situation in a server with a slow network */
44196 SK_OUT16(IoC, B3_PA_CTRL, PA_CLR_TO_TX2);
44197@@ -653,25 +915,18 @@
44198 pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOHALF) &&
44199 !pPrt->HalfDupTimerActive) {
44200 pPrt->HalfDupTimerActive = SK_TRUE;
44201-#ifdef XXX
44202- Len = sizeof(SK_U64);
44203- SkPnmiGetVar(pAC, IoC, OID_SKGE_STAT_TX_OCTETS, (char *)&Octets,
44204- &Len, (SK_U32)SK_PNMI_PORT_PHYS2INST(pAC, 1),
44205- pAC->Rlmt.Port[1].Net->NetNumber);
44206-
44207- pPrt->LastOctets = Octets;
44208-#endif /* XXX */
44209+
44210 /* Snap statistic counters */
44211 (void)SkXmUpdateStats(pAC, IoC, 1);
44212
44213 (void)SkXmMacStatistic(pAC, IoC, 1, XM_TXO_OK_HI, &RegVal32);
44214
44215 pPrt->LastOctets = (SK_U64)RegVal32 << 32;
44216-
44217+
44218 (void)SkXmMacStatistic(pAC, IoC, 1, XM_TXO_OK_LO, &RegVal32);
44219
44220 pPrt->LastOctets += RegVal32;
44221-
44222+
44223 Para.Para32[0] = 1;
44224 SkTimerStart(pAC, IoC, &pPrt->HalfDupChkTimer, SK_HALFDUP_CHK_TIME,
44225 SKGE_HWAC, SK_HWEV_HALFDUP_CHK, Para);
44226@@ -684,6 +939,7 @@
44227 if ((Istatus & IS_R1_C) != 0) {
44228 /* Clear IRQ */
44229 SK_OUT32(IoC, B0_R1_CSR, CSR_IRQ_CL_C);
44230+
44231 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E006,
44232 SKERR_SIRQ_E006MSG);
44233 Para.Para64 = MAC_1;
44234@@ -695,6 +951,7 @@
44235 if ((Istatus & IS_R2_C) != 0) {
44236 /* Clear IRQ */
44237 SK_OUT32(IoC, B0_R2_CSR, CSR_IRQ_CL_C);
44238+
44239 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E007,
44240 SKERR_SIRQ_E007MSG);
44241 Para.Para64 = MAC_2;
44242@@ -706,6 +963,7 @@
44243 if ((Istatus & IS_XS1_C) != 0) {
44244 /* Clear IRQ */
44245 SK_OUT32(IoC, B0_XS1_CSR, CSR_IRQ_CL_C);
44246+
44247 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E008,
44248 SKERR_SIRQ_E008MSG);
44249 Para.Para64 = MAC_1;
44250@@ -717,6 +975,7 @@
44251 if ((Istatus & IS_XA1_C) != 0) {
44252 /* Clear IRQ */
44253 SK_OUT32(IoC, B0_XA1_CSR, CSR_IRQ_CL_C);
44254+
44255 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E009,
44256 SKERR_SIRQ_E009MSG);
44257 Para.Para64 = MAC_1;
44258@@ -728,6 +987,7 @@
44259 if ((Istatus & IS_XS2_C) != 0) {
44260 /* Clear IRQ */
44261 SK_OUT32(IoC, B0_XS2_CSR, CSR_IRQ_CL_C);
44262+
44263 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E010,
44264 SKERR_SIRQ_E010MSG);
44265 Para.Para64 = MAC_2;
44266@@ -739,6 +999,7 @@
44267 if ((Istatus & IS_XA2_C) != 0) {
44268 /* Clear IRQ */
44269 SK_OUT32(IoC, B0_XA2_CSR, CSR_IRQ_CL_C);
44270+
44271 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E011,
44272 SKERR_SIRQ_E011MSG);
44273 Para.Para64 = MAC_2;
44274@@ -751,39 +1012,37 @@
44275 if ((Istatus & IS_EXT_REG) != 0) {
44276 /* Test IRQs from PHY */
44277 for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
44278-
44279+
44280 pPrt = &pAC->GIni.GP[i];
44281-
44282+
44283 if (pPrt->PState == SK_PRT_RESET) {
44284 continue;
44285 }
44286-
44287+
44288 #ifdef GENESIS
44289 if (pAC->GIni.GIGenesis) {
44290-
44291+
44292 switch (pPrt->PhyType) {
44293-
44294+
44295 case SK_PHY_XMAC:
44296 break;
44297-
44298+
44299 case SK_PHY_BCOM:
44300 SkXmPhyRead(pAC, IoC, i, PHY_BCOM_INT_STAT, &PhyInt);
44301-
44302+
44303 if ((PhyInt & ~PHY_B_DEF_MSK) != 0) {
44304 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
44305- ("Port %d Bcom Int: 0x%04X\n",
44306- i, PhyInt));
44307+ ("Port %d PHY Int: 0x%04X\n", i, PhyInt));
44308 SkPhyIsrBcom(pAC, IoC, i, PhyInt);
44309 }
44310 break;
44311 #ifdef OTHER_PHY
44312 case SK_PHY_LONE:
44313 SkXmPhyRead(pAC, IoC, i, PHY_LONE_INT_STAT, &PhyInt);
44314-
44315+
44316 if ((PhyInt & PHY_L_DEF_MSK) != 0) {
44317 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
44318- ("Port %d Lone Int: %x\n",
44319- i, PhyInt));
44320+ ("Port %d PHY Int: 0x%04X\n", i, PhyInt));
44321 SkPhyIsrLone(pAC, IoC, i, PhyInt);
44322 }
44323 break;
44324@@ -791,7 +1050,7 @@
44325 }
44326 }
44327 #endif /* GENESIS */
44328-
44329+
44330 #ifdef YUKON
44331 if (pAC->GIni.GIYukon) {
44332 /* Read PHY Interrupt Status */
44333@@ -799,8 +1058,7 @@
44334
44335 if ((PhyInt & PHY_M_DEF_MSK) != 0) {
44336 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
44337- ("Port %d Marv Int: 0x%04X\n",
44338- i, PhyInt));
44339+ ("Port %d PHY Int: 0x%04X\n", i, PhyInt));
44340 SkPhyIsrGmac(pAC, IoC, i, PhyInt);
44341 }
44342 }
44343@@ -808,13 +1066,13 @@
44344 }
44345 }
44346
44347- /* I2C Ready interrupt */
44348+ /* TWSI Ready interrupt */
44349 if ((Istatus & IS_I2C_READY) != 0) {
44350 #ifdef SK_SLIM
44351- SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
44352-#else
44353+ SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
44354+#else
44355 SkI2cIsr(pAC, IoC);
44356-#endif
44357+#endif
44358 }
44359
44360 /* SW forced interrupt */
44361@@ -829,7 +1087,7 @@
44362 * us only a link going down.
44363 */
44364 /* clear interrupt */
44365- SK_OUT8(IoC, MR_ADDR(MAC_1, LNK_SYNC_CTRL), LED_CLR_IRQ);
44366+ SK_OUT8(IoC, MR_ADDR(MAC_1, LNK_SYNC_CTRL), LNK_CLR_IRQ);
44367 }
44368
44369 /* Check MAC after link sync counter */
44370@@ -844,7 +1102,7 @@
44371 * us only a link going down.
44372 */
44373 /* clear interrupt */
44374- SK_OUT8(IoC, MR_ADDR(MAC_2, LNK_SYNC_CTRL), LED_CLR_IRQ);
44375+ SK_OUT8(IoC, MR_ADDR(MAC_2, LNK_SYNC_CTRL), LNK_CLR_IRQ);
44376 }
44377
44378 /* Check MAC after link sync counter */
44379@@ -860,13 +1118,189 @@
44380 /* read the HW Error Interrupt source */
44381 SK_IN32(IoC, B0_HWE_ISRC, &RegVal32);
44382
44383- SkGeHwErr(pAC, IoC, RegVal32);
44384+ SkGeYuHwErr(pAC, IoC, RegVal32);
44385+ }
44386+
44387+ SkHwtIsr(pAC, IoC);
44388+ }
44389+
44390+} /* SkGeYuSirqIsr */
44391+
44392+#ifdef YUK2
44393+/******************************************************************************
44394+ *
44395+ * SkYuk2PortSirq() - Service HW Errors for specified port (Yukon-2 only)
44396+ *
44397+ * Description: handles the HW Error interrupts for a specific port.
44398+ *
44399+ * Returns: N/A
44400+ */
44401+static void SkYuk2PortSirq(
44402+SK_AC *pAC, /* Adapter Context */
44403+SK_IOC IoC, /* I/O Context */
44404+SK_U32 IStatus, /* Interrupt status word */
44405+int Port) /* Port Index (MAC_1 + n) */
44406+{
44407+ SK_EVPARA Para;
44408+ int Queue;
44409+ SK_U16 PhyInt;
44410+
44411+ if (Port == MAC_2) {
44412+ IStatus >>= 8;
44413+ }
44414+
44415+ /* Interrupt from PHY */
44416+ if ((IStatus & Y2_IS_IRQ_PHY1) != 0) {
44417+ /* Read PHY Interrupt Status */
44418+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_INT_STAT, &PhyInt);
44419+
44420+ if ((PhyInt & PHY_M_DEF_MSK) != 0) {
44421+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
44422+ ("Port %d PHY Int: 0x%04X\n", Port, PhyInt));
44423+ SkPhyIsrGmac(pAC, IoC, Port, PhyInt);
44424+ }
44425+ }
44426+
44427+ /* Interrupt from MAC */
44428+ if ((IStatus & Y2_IS_IRQ_MAC1) != 0) {
44429+ SkMacIrq(pAC, IoC, Port);
44430+ }
44431+
44432+ if ((IStatus & (Y2_IS_CHK_RX1 | Y2_IS_CHK_TXS1 | Y2_IS_CHK_TXA1)) != 0) {
44433+ if ((IStatus & Y2_IS_CHK_RX1) != 0) {
44434+ if (Port == MAC_1) {
44435+ Queue = Q_R1;
44436+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E006,
44437+ SKERR_SIRQ_E006MSG);
44438+ }
44439+ else {
44440+ Queue = Q_R2;
44441+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E007,
44442+ SKERR_SIRQ_E007MSG);
44443+ }
44444+ /* Clear IRQ */
44445+ SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_CHK);
44446+ }
44447+
44448+ if ((IStatus & Y2_IS_CHK_TXS1) != 0) {
44449+ if (Port == MAC_1) {
44450+ Queue = Q_XS1;
44451+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E008,
44452+ SKERR_SIRQ_E008MSG);
44453+ }
44454+ else {
44455+ Queue = Q_XS2;
44456+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E010,
44457+ SKERR_SIRQ_E010MSG);
44458+ }
44459+ /* Clear IRQ */
44460+ SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_CHK);
44461+ }
44462+
44463+ if ((IStatus & Y2_IS_CHK_TXA1) != 0) {
44464+ if (Port == MAC_1) {
44465+ Queue = Q_XA1;
44466+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E009,
44467+ SKERR_SIRQ_E009MSG);
44468+ }
44469+ else {
44470+ Queue = Q_XA2;
44471+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E011,
44472+ SKERR_SIRQ_E011MSG);
44473+ }
44474+ /* Clear IRQ */
44475+ SK_OUT32(IoC, Q_ADDR(Queue, Q_CSR), BMU_CLR_IRQ_CHK);
44476 }
44477
44478+ Para.Para64 = Port;
44479+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
44480+
44481+ Para.Para32[0] = Port;
44482+ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
44483+ }
44484+} /* SkYuk2PortSirq */
44485+#endif /* YUK2 */
44486+
44487+/******************************************************************************
44488+ *
44489+ * SkYuk2SirqIsr() - Special Interrupt Service Routine (Yukon-2 only)
44490+ *
44491+ * Description: handles all non data transfer specific interrupts (slow path)
44492+ *
44493+ * Returns: N/A
44494+ */
44495+void SkYuk2SirqIsr(
44496+SK_AC *pAC, /* Adapter Context */
44497+SK_IOC IoC, /* I/O Context */
44498+SK_U32 Istatus) /* Interrupt status word */
44499+{
44500+#ifdef YUK2
44501+ SK_EVPARA Para;
44502+ SK_U32 RegVal32; /* Read register value */
44503+ SK_U8 Value;
44504+
44505+ /* HW Error indicated ? */
44506+ if (((Istatus & Y2_IS_HW_ERR) & pAC->GIni.GIValIrqMask) != 0) {
44507+ /* read the HW Error Interrupt source */
44508+ SK_IN32(IoC, B0_HWE_ISRC, &RegVal32);
44509+
44510+ SkYuk2HwErr(pAC, IoC, RegVal32);
44511+ }
44512+
44513+ /* Interrupt from ASF Subsystem */
44514+ if ((Istatus & Y2_IS_ASF) != 0) {
44515+ /* clear IRQ */
44516+ /* later on clearing should be done in ASF ISR handler */
44517+ SK_IN8(IoC, B28_Y2_ASF_STAT_CMD, &Value);
44518+ Value |= Y2_ASF_CLR_HSTI;
44519+ SK_OUT8(IoC, B28_Y2_ASF_STAT_CMD, Value);
44520+ /* Call IRQ handler in ASF Module */
44521+ /* TBD */
44522+ }
44523+
44524+ /* Check IRQ from polling unit */
44525+ if ((Istatus & Y2_IS_POLL_CHK) != 0) {
44526+ /* Clear IRQ */
44527+ SK_OUT32(IoC, POLL_CTRL, PC_CLR_IRQ_CHK);
44528+
44529+ SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E036,
44530+ SKERR_SIRQ_E036MSG);
44531+ Para.Para64 = 0;
44532+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_ADAP_FAIL, Para);
44533+ }
44534+
44535+ /* TWSI Ready interrupt */
44536+ if ((Istatus & Y2_IS_TWSI_RDY) != 0) {
44537+#ifdef SK_SLIM
44538+ SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
44539+#else
44540+ SkI2cIsr(pAC, IoC);
44541+#endif
44542+ }
44543+
44544+ /* SW forced interrupt */
44545+ if ((Istatus & Y2_IS_IRQ_SW) != 0) {
44546+ /* clear the software IRQ */
44547+ SK_OUT8(IoC, B0_CTST, CS_CL_SW_IRQ);
44548+ }
44549+
44550+ if ((Istatus & Y2_IS_L1_MASK) != 0) {
44551+ SkYuk2PortSirq(pAC, IoC, Istatus, MAC_1);
44552+ }
44553+
44554+ if ((Istatus & Y2_IS_L2_MASK) != 0) {
44555+ SkYuk2PortSirq(pAC, IoC, Istatus, MAC_2);
44556+ }
44557+
44558+ /* Timer interrupt (served last) */
44559+ if ((Istatus & Y2_IS_TIMINT) != 0) {
44560+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
44561+ ("Timer Int: 0x%08lX\n", Istatus));
44562 SkHwtIsr(pAC, IoC);
44563 }
44564+#endif /* YUK2 */
44565
44566-} /* SkGeSirqIsr */
44567+} /* SkYuk2SirqIsr */
44568
44569
44570 #ifdef GENESIS
44571@@ -880,8 +1314,8 @@
44572 */
44573 static int SkGePortCheckShorts(
44574 SK_AC *pAC, /* Adapter Context */
44575-SK_IOC IoC, /* IO Context */
44576-int Port) /* Which port should be checked */
44577+SK_IOC IoC, /* I/O Context */
44578+int Port) /* Port Index (MAC_1 + n) */
44579 {
44580 SK_U32 Shorts; /* Short Event Counter */
44581 SK_U32 CheckShorts; /* Check value for Short Event Counter */
44582@@ -909,9 +1343,9 @@
44583 RxCts = 0;
44584
44585 for (i = 0; i < sizeof(SkGeRxRegs)/sizeof(SkGeRxRegs[0]); i++) {
44586-
44587+
44588 (void)SkXmMacStatistic(pAC, IoC, Port, SkGeRxRegs[i], &RxTmp);
44589-
44590+
44591 RxCts += (SK_U64)RxTmp;
44592 }
44593
44594@@ -928,11 +1362,11 @@
44595 CheckShorts = 2;
44596
44597 (void)SkXmMacStatistic(pAC, IoC, Port, XM_RXF_FCS_ERR, &FcsErrCts);
44598-
44599- if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE &&
44600- pPrt->PLipaAutoNeg == SK_LIPA_UNKNOWN &&
44601- (pPrt->PLinkMode == SK_LMODE_HALF ||
44602- pPrt->PLinkMode == SK_LMODE_FULL)) {
44603+
44604+ if (pPrt->PLinkModeConf == (SK_U8)SK_LMODE_AUTOSENSE &&
44605+ pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_UNKNOWN &&
44606+ (pPrt->PLinkMode == (SK_U8)SK_LMODE_HALF ||
44607+ pPrt->PLinkMode == (SK_U8)SK_LMODE_FULL)) {
44608 /*
44609 * This is autosensing and we are in the fallback
44610 * manual full/half duplex mode.
44611@@ -941,16 +1375,16 @@
44612 /* Nothing received, restart link */
44613 pPrt->PPrevFcs = FcsErrCts;
44614 pPrt->PPrevShorts = Shorts;
44615-
44616+
44617 return(SK_HW_PS_RESTART);
44618 }
44619 else {
44620- pPrt->PLipaAutoNeg = SK_LIPA_MANUAL;
44621+ pPrt->PLipaAutoNeg = (SK_U8)SK_LIPA_MANUAL;
44622 }
44623 }
44624
44625 if (((RxCts - pPrt->PPrevRx) > pPrt->PRxLim) ||
44626- (!(FcsErrCts - pPrt->PPrevFcs))) {
44627+ (!(FcsErrCts - pPrt->PPrevFcs))) {
44628 /*
44629 * Note: The compare with zero above has to be done the way shown,
44630 * otherwise the Linux driver will have a problem.
44631@@ -995,29 +1429,25 @@
44632 */
44633 static int SkGePortCheckUp(
44634 SK_AC *pAC, /* Adapter Context */
44635-SK_IOC IoC, /* IO Context */
44636-int Port) /* Which port should be checked */
44637+SK_IOC IoC, /* I/O Context */
44638+int Port) /* Port Index (MAC_1 + n) */
44639 {
44640 SK_GEPORT *pPrt; /* GIni Port struct pointer */
44641 SK_BOOL AutoNeg; /* Is Auto-negotiation used ? */
44642 int Rtv; /* Return value */
44643
44644 Rtv = SK_HW_PS_NONE;
44645-
44646+
44647 pPrt = &pAC->GIni.GP[Port];
44648
44649- if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
44650- AutoNeg = SK_FALSE;
44651- }
44652- else {
44653- AutoNeg = SK_TRUE;
44654- }
44655+ AutoNeg = pPrt->PLinkMode != SK_LMODE_HALF &&
44656+ pPrt->PLinkMode != SK_LMODE_FULL;
44657
44658 #ifdef GENESIS
44659 if (pAC->GIni.GIGenesis) {
44660
44661 switch (pPrt->PhyType) {
44662-
44663+
44664 case SK_PHY_XMAC:
44665 Rtv = SkGePortCheckUpXmac(pAC, IoC, Port, AutoNeg);
44666 break;
44667@@ -1035,15 +1465,15 @@
44668 }
44669 }
44670 #endif /* GENESIS */
44671-
44672+
44673 #ifdef YUKON
44674 if (pAC->GIni.GIYukon) {
44675-
44676+
44677 Rtv = SkGePortCheckUpGmac(pAC, IoC, Port, AutoNeg);
44678 }
44679 #endif /* YUKON */
44680
44681- return(Rtv);
44682+ return(Rtv);
44683 } /* SkGePortCheckUp */
44684
44685
44686@@ -1059,8 +1489,8 @@
44687 */
44688 static int SkGePortCheckUpXmac(
44689 SK_AC *pAC, /* Adapter Context */
44690-SK_IOC IoC, /* IO Context */
44691-int Port, /* Which port should be checked */
44692+SK_IOC IoC, /* I/O Context */
44693+int Port, /* Port Index (MAC_1 + n) */
44694 SK_BOOL AutoNeg) /* Is Auto-negotiation used ? */
44695 {
44696 SK_U32 Shorts; /* Short Event Counter */
44697@@ -1098,7 +1528,7 @@
44698 XM_IN16(IoC, Port, XM_ISRC, &Isrc);
44699 IsrcSum |= Isrc;
44700 SkXmAutoNegLipaXmac(pAC, IoC, Port, IsrcSum);
44701-
44702+
44703 if ((Isrc & XM_IS_INP_ASS) == 0) {
44704 /* It has been in sync since last time */
44705 /* Restart the PORT */
44706@@ -1117,14 +1547,14 @@
44707 * Link Restart Workaround:
44708 * it may be possible that the other Link side
44709 * restarts its link as well an we detect
44710- * another LinkBroken. To prevent this
44711+ * another PLinkBroken. To prevent this
44712 * happening we check for a maximum number
44713 * of consecutive restart. If those happens,
44714 * we do NOT restart the active link and
44715 * check whether the link is now o.k.
44716 */
44717 pPrt->PLinkResCt++;
44718-
44719+
44720 pPrt->PAutoNegTimeOut = 0;
44721
44722 if (pPrt->PLinkResCt < SK_MAX_LRESTART) {
44723@@ -1132,13 +1562,13 @@
44724 }
44725
44726 pPrt->PLinkResCt = 0;
44727-
44728+
44729 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
44730 ("Do NOT restart on Port %d %x %x\n", Port, Isrc, IsrcSum));
44731 }
44732 else {
44733 pPrt->PIsave = (SK_U16)(IsrcSum & XM_IS_AND);
44734-
44735+
44736 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
44737 ("Save Sync/nosync Port %d %x %x\n", Port, Isrc, IsrcSum));
44738
44739@@ -1165,7 +1595,7 @@
44740 if ((Isrc & XM_IS_INP_ASS) != 0) {
44741 pPrt->PLinkBroken = SK_TRUE;
44742 /* Re-Init Link partner Autoneg flag */
44743- pPrt->PLipaAutoNeg = SK_LIPA_UNKNOWN;
44744+ pPrt->PLipaAutoNeg = (SK_U8)SK_LIPA_UNKNOWN;
44745 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
44746 ("Link broken Port %d\n", Port));
44747
44748@@ -1178,7 +1608,7 @@
44749 }
44750 else {
44751 SkXmAutoNegLipaXmac(pAC, IoC, Port, Isrc);
44752-
44753+
44754 if (SkGePortCheckShorts(pAC, IoC, Port) == SK_HW_PS_RESTART) {
44755 return(SK_HW_PS_RESTART);
44756 }
44757@@ -1194,7 +1624,7 @@
44758 IsrcSum |= Isrc;
44759
44760 SkXmAutoNegLipaXmac(pAC, IoC, Port, IsrcSum);
44761-
44762+
44763 if ((GpReg & XM_GP_INP_ASS) != 0 || (IsrcSum & XM_IS_INP_ASS) != 0) {
44764 if ((GpReg & XM_GP_INP_ASS) == 0) {
44765 /* Save Auto-negotiation Done interrupt only if link is in sync */
44766@@ -1210,17 +1640,21 @@
44767 }
44768
44769 if (AutoNeg) {
44770+ /* Auto-Negotiation Done ? */
44771 if ((IsrcSum & XM_IS_AND) != 0) {
44772+
44773 SkHWLinkUp(pAC, IoC, Port);
44774+
44775 Done = SkMacAutoNegDone(pAC, IoC, Port);
44776+
44777 if (Done != SK_AND_OK) {
44778 /* Get PHY parameters, for debugging only */
44779 SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_AUNE_LP, &LpAb);
44780 SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_RES_ABI, &ResAb);
44781- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
44782+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
44783 ("AutoNeg FAIL Port %d (LpAb %x, ResAb %x)\n",
44784- Port, LpAb, ResAb));
44785-
44786+ Port, LpAb, ResAb));
44787+
44788 /* Try next possible mode */
44789 NextMode = SkHWSenseGetNext(pAC, IoC, Port);
44790 SkHWLinkDown(pAC, IoC, Port);
44791@@ -1236,42 +1670,41 @@
44792 * (clear Page Received bit if set)
44793 */
44794 SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_AUNE_EXP, &ExtStat);
44795-
44796+
44797 return(SK_HW_PS_LINK);
44798 }
44799-
44800+
44801 /* AutoNeg not done, but HW link is up. Check for timeouts */
44802- pPrt->PAutoNegTimeOut++;
44803- if (pPrt->PAutoNegTimeOut >= SK_AND_MAX_TO) {
44804+ if (pPrt->PAutoNegTimeOut++ >= SK_AND_MAX_TO) {
44805 /* Increase the Timeout counter */
44806 pPrt->PAutoNegTOCt++;
44807
44808 /* Timeout occured */
44809 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
44810 ("AutoNeg timeout Port %d\n", Port));
44811- if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE &&
44812- pPrt->PLipaAutoNeg != SK_LIPA_AUTO) {
44813+ if (pPrt->PLinkModeConf == (SK_U8)SK_LMODE_AUTOSENSE &&
44814+ pPrt->PLipaAutoNeg != (SK_U8)SK_LIPA_AUTO) {
44815 /* Set Link manually up */
44816 SkHWSenseSetNext(pAC, IoC, Port, SK_LMODE_FULL);
44817 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
44818 ("Set manual full duplex Port %d\n", Port));
44819 }
44820
44821- if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE &&
44822- pPrt->PLipaAutoNeg == SK_LIPA_AUTO &&
44823+ if (pPrt->PLinkModeConf == (SK_U8)SK_LMODE_AUTOSENSE &&
44824+ pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_AUTO &&
44825 pPrt->PAutoNegTOCt >= SK_MAX_ANEG_TO) {
44826 /*
44827 * This is rather complicated.
44828 * we need to check here whether the LIPA_AUTO
44829 * we saw before is false alert. We saw at one
44830- * switch ( SR8800) that on boot time it sends
44831+ * switch (SR8800) that on boot time it sends
44832 * just one auto-neg packet and does no further
44833 * auto-negotiation.
44834 * Solution: we restart the autosensing after
44835 * a few timeouts.
44836 */
44837 pPrt->PAutoNegTOCt = 0;
44838- pPrt->PLipaAutoNeg = SK_LIPA_UNKNOWN;
44839+ pPrt->PLipaAutoNeg = (SK_U8)SK_LIPA_UNKNOWN;
44840 SkHWInitDefSense(pAC, IoC, Port);
44841 }
44842
44843@@ -1282,18 +1715,18 @@
44844 else {
44845 /* Link is up and we don't need more */
44846 #ifdef DEBUG
44847- if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) {
44848- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
44849+ if (pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_AUTO) {
44850+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
44851 ("ERROR: Lipa auto detected on port %d\n", Port));
44852 }
44853 #endif /* DEBUG */
44854 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
44855 ("Link sync(GP), Port %d\n", Port));
44856 SkHWLinkUp(pAC, IoC, Port);
44857-
44858+
44859 /*
44860- * Link sync (GP) and so assume a good connection. But if not received
44861- * a bunch of frames received in a time slot (maybe broken tx cable)
44862+ * Link sync (GP) and so assume a good connection. But if no
44863+ * bunch of frames received in a time slot (maybe broken Tx cable)
44864 * the port is restart.
44865 */
44866 return(SK_HW_PS_LINK);
44867@@ -1314,8 +1747,8 @@
44868 */
44869 static int SkGePortCheckUpBcom(
44870 SK_AC *pAC, /* Adapter Context */
44871-SK_IOC IoC, /* IO Context */
44872-int Port, /* Which port should be checked */
44873+SK_IOC IoC, /* I/O Context */
44874+int Port, /* Port Index (MAC_1 + n) */
44875 SK_BOOL AutoNeg) /* Is Auto-negotiation used ? */
44876 {
44877 SK_GEPORT *pPrt; /* GIni Port struct pointer */
44878@@ -1334,74 +1767,6 @@
44879 /* Check for No HCD Link events (#10523) */
44880 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_STAT, &Isrc);
44881
44882-#ifdef xDEBUG
44883- if ((Isrc & ~(PHY_B_IS_HCT | PHY_B_IS_LCT) ==
44884- (PHY_B_IS_SCR_S_ER | PHY_B_IS_RRS_CHANGE | PHY_B_IS_LRS_CHANGE)) {
44885-
44886- SK_U32 Stat1, Stat2, Stat3;
44887-
44888- Stat1 = 0;
44889- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_MASK, &Stat1);
44890- CMSMPrintString(
44891- pAC->pConfigTable,
44892- MSG_TYPE_RUNTIME_INFO,
44893- "CheckUp1 - Stat: %x, Mask: %x",
44894- (void *)Isrc,
44895- (void *)Stat1);
44896-
44897- Stat1 = 0;
44898- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_CTRL, &Stat1);
44899- Stat2 = 0;
44900- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_STAT, &Stat2);
44901- Stat1 = Stat1 << 16 | Stat2;
44902- Stat2 = 0;
44903- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_ADV, &Stat2);
44904- Stat3 = 0;
44905- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &Stat3);
44906- Stat2 = Stat2 << 16 | Stat3;
44907- CMSMPrintString(
44908- pAC->pConfigTable,
44909- MSG_TYPE_RUNTIME_INFO,
44910- "Ctrl/Stat: %x, AN Adv/LP: %x",
44911- (void *)Stat1,
44912- (void *)Stat2);
44913-
44914- Stat1 = 0;
44915- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_EXP, &Stat1);
44916- Stat2 = 0;
44917- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_EXT_STAT, &Stat2);
44918- Stat1 = Stat1 << 16 | Stat2;
44919- Stat2 = 0;
44920- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_CTRL, &Stat2);
44921- Stat3 = 0;
44922- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &Stat3);
44923- Stat2 = Stat2 << 16 | Stat3;
44924- CMSMPrintString(
44925- pAC->pConfigTable,
44926- MSG_TYPE_RUNTIME_INFO,
44927- "AN Exp/IEEE Ext: %x, 1000T Ctrl/Stat: %x",
44928- (void *)Stat1,
44929- (void *)Stat2);
44930-
44931- Stat1 = 0;
44932- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_CTRL, &Stat1);
44933- Stat2 = 0;
44934- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_STAT, &Stat2);
44935- Stat1 = Stat1 << 16 | Stat2;
44936- Stat2 = 0;
44937- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &Stat2);
44938- Stat3 = 0;
44939- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_STAT, &Stat3);
44940- Stat2 = Stat2 << 16 | Stat3;
44941- CMSMPrintString(
44942- pAC->pConfigTable,
44943- MSG_TYPE_RUNTIME_INFO,
44944- "PHY Ext Ctrl/Stat: %x, Aux Ctrl/Stat: %x",
44945- (void *)Stat1,
44946- (void *)Stat2);
44947- }
44948-#endif /* DEBUG */
44949-
44950 if ((Isrc & (PHY_B_IS_NO_HDCL /* | PHY_B_IS_NO_HDC */)) != 0) {
44951 /*
44952 * Workaround BCom Errata:
44953@@ -1414,14 +1779,6 @@
44954 (SK_U16)(Ctrl & ~PHY_CT_LOOP));
44955 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
44956 ("No HCD Link event, Port %d\n", Port));
44957-#ifdef xDEBUG
44958- CMSMPrintString(
44959- pAC->pConfigTable,
44960- MSG_TYPE_RUNTIME_INFO,
44961- "No HCD link event, port %d.",
44962- (void *)Port,
44963- (void *)NULL);
44964-#endif /* DEBUG */
44965 }
44966
44967 /* Not obsolete: link status bit is latched to 0 and autoclearing! */
44968@@ -1431,72 +1788,6 @@
44969 return(SK_HW_PS_NONE);
44970 }
44971
44972-#ifdef xDEBUG
44973- {
44974- SK_U32 Stat1, Stat2, Stat3;
44975-
44976- Stat1 = 0;
44977- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_MASK, &Stat1);
44978- CMSMPrintString(
44979- pAC->pConfigTable,
44980- MSG_TYPE_RUNTIME_INFO,
44981- "CheckUp1a - Stat: %x, Mask: %x",
44982- (void *)Isrc,
44983- (void *)Stat1);
44984-
44985- Stat1 = 0;
44986- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_CTRL, &Stat1);
44987- Stat2 = 0;
44988- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_STAT, &PhyStat);
44989- Stat1 = Stat1 << 16 | PhyStat;
44990- Stat2 = 0;
44991- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_ADV, &Stat2);
44992- Stat3 = 0;
44993- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &Stat3);
44994- Stat2 = Stat2 << 16 | Stat3;
44995- CMSMPrintString(
44996- pAC->pConfigTable,
44997- MSG_TYPE_RUNTIME_INFO,
44998- "Ctrl/Stat: %x, AN Adv/LP: %x",
44999- (void *)Stat1,
45000- (void *)Stat2);
45001-
45002- Stat1 = 0;
45003- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_EXP, &Stat1);
45004- Stat2 = 0;
45005- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_EXT_STAT, &Stat2);
45006- Stat1 = Stat1 << 16 | Stat2;
45007- Stat2 = 0;
45008- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_CTRL, &Stat2);
45009- Stat3 = 0;
45010- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &ResAb);
45011- Stat2 = Stat2 << 16 | ResAb;
45012- CMSMPrintString(
45013- pAC->pConfigTable,
45014- MSG_TYPE_RUNTIME_INFO,
45015- "AN Exp/IEEE Ext: %x, 1000T Ctrl/Stat: %x",
45016- (void *)Stat1,
45017- (void *)Stat2);
45018-
45019- Stat1 = 0;
45020- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_CTRL, &Stat1);
45021- Stat2 = 0;
45022- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_P_EXT_STAT, &Stat2);
45023- Stat1 = Stat1 << 16 | Stat2;
45024- Stat2 = 0;
45025- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &Stat2);
45026- Stat3 = 0;
45027- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_STAT, &Stat3);
45028- Stat2 = Stat2 << 16 | Stat3;
45029- CMSMPrintString(
45030- pAC->pConfigTable,
45031- MSG_TYPE_RUNTIME_INFO,
45032- "PHY Ext Ctrl/Stat: %x, Aux Ctrl/Stat: %x",
45033- (void *)Stat1,
45034- (void *)Stat2);
45035- }
45036-#endif /* DEBUG */
45037-
45038 /*
45039 * Here we usually can check whether the link is in sync and
45040 * auto-negotiation is done.
45041@@ -1505,7 +1796,7 @@
45042 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_STAT, &PhyStat);
45043
45044 SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat);
45045-
45046+
45047 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
45048 ("CheckUp Port %d, PhyStat: 0x%04X\n", Port, PhyStat));
45049
45050@@ -1513,88 +1804,62 @@
45051
45052 if ((ResAb & PHY_B_1000S_MSF) != 0) {
45053 /* Error */
45054- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
45055- ("Master/Slave Fault port %d\n", Port));
45056-
45057+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
45058+ ("Master/Slave Fault, ResAb: 0x%04X\n", ResAb));
45059+
45060 pPrt->PAutoNegFail = SK_TRUE;
45061 pPrt->PMSStatus = SK_MS_STAT_FAULT;
45062-
45063+
45064 return(SK_HW_PS_RESTART);
45065 }
45066
45067 if ((PhyStat & PHY_ST_LSYNC) == 0) {
45068 return(SK_HW_PS_NONE);
45069 }
45070-
45071+
45072 pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
45073 SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE;
45074-
45075+
45076 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
45077 ("Port %d, ResAb: 0x%04X\n", Port, ResAb));
45078
45079 if (AutoNeg) {
45080+ /* Auto-Negotiation Over ? */
45081 if ((PhyStat & PHY_ST_AN_OVER) != 0) {
45082-
45083+
45084 SkHWLinkUp(pAC, IoC, Port);
45085-
45086+
45087 Done = SkMacAutoNegDone(pAC, IoC, Port);
45088-
45089+
45090 if (Done != SK_AND_OK) {
45091 #ifdef DEBUG
45092 /* Get PHY parameters, for debugging only */
45093 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &LpAb);
45094 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &ExtStat);
45095- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
45096+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
45097 ("AutoNeg FAIL Port %d (LpAb %x, 1000TStat %x)\n",
45098 Port, LpAb, ExtStat));
45099 #endif /* DEBUG */
45100 return(SK_HW_PS_RESTART);
45101 }
45102 else {
45103-#ifdef xDEBUG
45104- /* Dummy read ISR to prevent extra link downs/ups */
45105- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_STAT, &ExtStat);
45106-
45107- if ((ExtStat & ~(PHY_B_IS_HCT | PHY_B_IS_LCT)) != 0) {
45108- CMSMPrintString(
45109- pAC->pConfigTable,
45110- MSG_TYPE_RUNTIME_INFO,
45111- "CheckUp2 - Stat: %x",
45112- (void *)ExtStat,
45113- (void *)NULL);
45114- }
45115-#endif /* DEBUG */
45116 return(SK_HW_PS_LINK);
45117 }
45118 }
45119 }
45120 else { /* !AutoNeg */
45121- /* Link is up and we don't need more. */
45122+ /* Link is up and we don't need more */
45123 #ifdef DEBUG
45124- if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) {
45125- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
45126+ if (pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_AUTO) {
45127+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
45128 ("ERROR: Lipa auto detected on port %d\n", Port));
45129 }
45130 #endif /* DEBUG */
45131
45132-#ifdef xDEBUG
45133- /* Dummy read ISR to prevent extra link downs/ups */
45134- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_INT_STAT, &ExtStat);
45135-
45136- if ((ExtStat & ~(PHY_B_IS_HCT | PHY_B_IS_LCT)) != 0) {
45137- CMSMPrintString(
45138- pAC->pConfigTable,
45139- MSG_TYPE_RUNTIME_INFO,
45140- "CheckUp3 - Stat: %x",
45141- (void *)ExtStat,
45142- (void *)NULL);
45143- }
45144-#endif /* DEBUG */
45145-
45146 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
45147 ("Link sync(GP), Port %d\n", Port));
45148 SkHWLinkUp(pAC, IoC, Port);
45149-
45150+
45151 return(SK_HW_PS_LINK);
45152 }
45153
45154@@ -1615,17 +1880,18 @@
45155 */
45156 static int SkGePortCheckUpGmac(
45157 SK_AC *pAC, /* Adapter Context */
45158-SK_IOC IoC, /* IO Context */
45159-int Port, /* Which port should be checked */
45160+SK_IOC IoC, /* I/O Context */
45161+int Port, /* Port Index (MAC_1 + n) */
45162 SK_BOOL AutoNeg) /* Is Auto-negotiation used ? */
45163 {
45164 SK_GEPORT *pPrt; /* GIni Port struct pointer */
45165 int Done;
45166- SK_U16 PhyIsrc; /* PHY Interrupt source */
45167- SK_U16 PhyStat; /* PPY Status */
45168+ SK_U16 PhyStat; /* PHY Status */
45169 SK_U16 PhySpecStat;/* PHY Specific Status */
45170 SK_U16 ResAb; /* Master/Slave resolution */
45171+#ifndef SK_SLIM
45172 SK_EVPARA Para;
45173+#endif /* !SK_SLIM */
45174 #ifdef DEBUG
45175 SK_U16 Word; /* I/O helper */
45176 #endif /* DEBUG */
45177@@ -1642,94 +1908,124 @@
45178 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
45179 ("CheckUp Port %d, PhyStat: 0x%04X\n", Port, PhyStat));
45180
45181- /* Read PHY Interrupt Status */
45182- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_INT_STAT, &PhyIsrc);
45183+ SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat);
45184
45185- if ((PhyIsrc & PHY_M_IS_AN_COMPL) != 0) {
45186- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
45187- ("Auto-Negotiation Completed, PhyIsrc: 0x%04X\n", PhyIsrc));
45188- }
45189+ if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
45190
45191- if ((PhyIsrc & PHY_M_IS_LSP_CHANGE) != 0) {
45192- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
45193- ("Link Speed Changed, PhyIsrc: 0x%04X\n", PhyIsrc));
45194- }
45195+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_STAT, &ResAb);
45196
45197- SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat);
45198-
45199- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_STAT, &ResAb);
45200+ if ((ResAb & PHY_B_1000S_MSF) != 0) {
45201+ /* Error */
45202+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
45203+ ("Master/Slave Fault, ResAb: 0x%04X\n", ResAb));
45204
45205- if ((ResAb & PHY_B_1000S_MSF) != 0) {
45206- /* Error */
45207- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
45208- ("Master/Slave Fault port %d\n", Port));
45209-
45210- pPrt->PAutoNegFail = SK_TRUE;
45211- pPrt->PMSStatus = SK_MS_STAT_FAULT;
45212-
45213- return(SK_HW_PS_RESTART);
45214+ pPrt->PAutoNegFail = SK_TRUE;
45215+ pPrt->PMSStatus = SK_MS_STAT_FAULT;
45216+
45217+ return(SK_HW_PS_RESTART);
45218+ }
45219 }
45220
45221 /* Read PHY Specific Status */
45222 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &PhySpecStat);
45223-
45224+
45225 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
45226 ("Phy1000BT: 0x%04X, PhySpecStat: 0x%04X\n", ResAb, PhySpecStat));
45227
45228 #ifdef DEBUG
45229 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_EXP, &Word);
45230
45231- if ((PhyIsrc & PHY_M_IS_AN_PR) != 0 || (Word & PHY_ANE_RX_PG) != 0 ||
45232- (PhySpecStat & PHY_M_PS_PAGE_REC) != 0) {
45233+ if ((Word & PHY_ANE_RX_PG) != 0 ||
45234+ (PhySpecStat & PHY_M_PS_PAGE_REC) != 0) {
45235 /* Read PHY Next Page Link Partner */
45236 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_NEPG_LP, &Word);
45237
45238 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
45239- ("Page Received, NextPage: 0x%04X\n", Word));
45240+ ("Page received, NextPage: 0x%04X\n", Word));
45241 }
45242 #endif /* DEBUG */
45243
45244 if ((PhySpecStat & PHY_M_PS_LINK_UP) == 0) {
45245+ /* Link down */
45246 return(SK_HW_PS_NONE);
45247 }
45248-
45249- if ((PhySpecStat & PHY_M_PS_DOWNS_STAT) != 0 ||
45250- (PhyIsrc & PHY_M_IS_DOWNSH_DET) != 0) {
45251- /* Downshift detected */
45252- SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E025, SKERR_SIRQ_E025MSG);
45253-
45254- Para.Para64 = Port;
45255- SkEventQueue(pAC, SKGE_DRV, SK_DRV_DOWNSHIFT_DET, Para);
45256-
45257- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
45258- ("Downshift detected, PhyIsrc: 0x%04X\n", PhyIsrc));
45259+
45260+#ifdef XXX
45261+ SK_U16 PhyInt;
45262+ /* Read PHY Interrupt Status */
45263+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_INT_STAT, &PhyInt);
45264+
45265+ /* cross check that the link is really up */
45266+ if ((PhyInt & PHY_M_IS_LST_CHANGE) == 0) {
45267+ /* Link Status unchanged */
45268+ return(SK_HW_PS_NONE);
45269 }
45270+#endif /* XXX */
45271+
45272+#ifndef SK_SLIM
45273+ if (pAC->GIni.GICopperType) {
45274+
45275+ if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
45276+
45277+ if ((PhySpecStat & PHY_M_PS_DOWNS_STAT) != 0) {
45278+ /* Downshift detected */
45279+ Para.Para64 = Port;
45280+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_DOWNSHIFT_DET, Para);
45281+
45282+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
45283+ ("Downshift detected, PhySpecStat: 0x%04X\n", PhySpecStat));
45284+
45285+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E025,
45286+ SKERR_SIRQ_E025MSG);
45287+ }
45288+
45289+ pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
45290+ SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE;
45291+ }
45292+
45293+ if ((PhySpecStat & PHY_M_PS_MDI_X_STAT) != 0) {
45294+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
45295+ ("MDI Xover detected, PhyStat: 0x%04X\n", PhySpecStat));
45296+ }
45297+
45298+ /* on PHY 88E1112 & 88E1145 cable length is in Reg. 26, Page 5 */
45299+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL ||
45300+ pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) {
45301+ /* select page 5 to access VCT DSP distance register */
45302+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 5);
45303+
45304+ /* get VCT DSP distance */
45305+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL_2, &PhySpecStat);
45306+
45307+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0);
45308+
45309+ pPrt->PCableLen = (SK_U8)(PhySpecStat & PHY_M_EC2_FO_AM_MSK);
45310+ }
45311+ else {
45312+ pPrt->PCableLen = (SK_U8)((PhySpecStat & PHY_M_PS_CABLE_MSK) >> 7);
45313+ }
45314+ }
45315+#endif /* !SK_SLIM */
45316
45317- pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
45318- SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE;
45319-
45320- pPrt->PCableLen = (SK_U8)((PhySpecStat & PHY_M_PS_CABLE_MSK) >> 7);
45321-
45322 if (AutoNeg) {
45323- /* Auto-Negotiation Over ? */
45324+ /* Auto-Negotiation Complete ? */
45325 if ((PhyStat & PHY_ST_AN_OVER) != 0) {
45326-
45327+
45328 SkHWLinkUp(pAC, IoC, Port);
45329-
45330+
45331 Done = SkMacAutoNegDone(pAC, IoC, Port);
45332-
45333+
45334 if (Done != SK_AND_OK) {
45335 return(SK_HW_PS_RESTART);
45336 }
45337-
45338+
45339 return(SK_HW_PS_LINK);
45340 }
45341 }
45342 else { /* !AutoNeg */
45343- /* Link is up and we don't need more */
45344 #ifdef DEBUG
45345- if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) {
45346- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
45347+ if (pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_AUTO) {
45348+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
45349 ("ERROR: Lipa auto detected on port %d\n", Port));
45350 }
45351 #endif /* DEBUG */
45352@@ -1737,12 +2033,13 @@
45353 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
45354 ("Link sync, Port %d\n", Port));
45355 SkHWLinkUp(pAC, IoC, Port);
45356-
45357+
45358 return(SK_HW_PS_LINK);
45359 }
45360
45361 return(SK_HW_PS_NONE);
45362 } /* SkGePortCheckUpGmac */
45363+
45364 #endif /* YUKON */
45365
45366
45367@@ -1758,8 +2055,8 @@
45368 */
45369 static int SkGePortCheckUpLone(
45370 SK_AC *pAC, /* Adapter Context */
45371-SK_IOC IoC, /* IO Context */
45372-int Port, /* Which port should be checked */
45373+SK_IOC IoC, /* I/O Context */
45374+int Port, /* Port Index (MAC_1 + n) */
45375 SK_BOOL AutoNeg) /* Is Auto-negotiation used ? */
45376 {
45377 SK_GEPORT *pPrt; /* GIni Port struct pointer */
45378@@ -1788,7 +2085,7 @@
45379 StatSum |= PhyStat;
45380
45381 SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat);
45382-
45383+
45384 if ((PhyStat & PHY_ST_LSYNC) == 0) {
45385 /* Save Auto-negotiation Done bit */
45386 pPrt->PIsave = (SK_U16)(StatSum & PHY_ST_AN_OVER);
45387@@ -1802,17 +2099,21 @@
45388 }
45389
45390 if (AutoNeg) {
45391+ /* Auto-Negotiation Over ? */
45392 if ((StatSum & PHY_ST_AN_OVER) != 0) {
45393+
45394 SkHWLinkUp(pAC, IoC, Port);
45395+
45396 Done = SkMacAutoNegDone(pAC, IoC, Port);
45397+
45398 if (Done != SK_AND_OK) {
45399 /* Get PHY parameters, for debugging only */
45400 SkXmPhyRead(pAC, IoC, Port, PHY_LONE_AUNE_LP, &LpAb);
45401 SkXmPhyRead(pAC, IoC, Port, PHY_LONE_1000T_STAT, &ExtStat);
45402- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
45403+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
45404 ("AutoNeg FAIL Port %d (LpAb %x, 1000TStat %x)\n",
45405 Port, LpAb, ExtStat));
45406-
45407+
45408 /* Try next possible mode */
45409 NextMode = SkHWSenseGetNext(pAC, IoC, Port);
45410 SkHWLinkDown(pAC, IoC, Port);
45411@@ -1833,15 +2134,14 @@
45412 return(SK_HW_PS_LINK);
45413 }
45414 }
45415-
45416+
45417 /* AutoNeg not done, but HW link is up. Check for timeouts */
45418- pPrt->PAutoNegTimeOut++;
45419- if (pPrt->PAutoNegTimeOut >= SK_AND_MAX_TO) {
45420+ if (pPrt->PAutoNegTimeOut++ >= SK_AND_MAX_TO) {
45421 /* Timeout occured */
45422 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
45423 ("AutoNeg timeout Port %d\n", Port));
45424- if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE &&
45425- pPrt->PLipaAutoNeg != SK_LIPA_AUTO) {
45426+ if (pPrt->PLinkModeConf == (SK_U8)SK_LMODE_AUTOSENSE &&
45427+ pPrt->PLipaAutoNeg != (SK_U8)SK_LIPA_AUTO) {
45428 /* Set Link manually up */
45429 SkHWSenseSetNext(pAC, IoC, Port, SK_LMODE_FULL);
45430 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
45431@@ -1855,8 +2155,8 @@
45432 else {
45433 /* Link is up and we don't need more */
45434 #ifdef DEBUG
45435- if (pPrt->PLipaAutoNeg == SK_LIPA_AUTO) {
45436- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
45437+ if (pPrt->PLipaAutoNeg == (SK_U8)SK_LIPA_AUTO) {
45438+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
45439 ("ERROR: Lipa auto detected on port %d\n", Port));
45440 }
45441 #endif /* DEBUG */
45442@@ -1866,11 +2166,12 @@
45443 * extra link down/ups
45444 */
45445 SkXmPhyRead(pAC, IoC, Port, PHY_LONE_INT_STAT, &ExtStat);
45446-
45447+
45448 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
45449 ("Link sync(GP), Port %d\n", Port));
45450+
45451 SkHWLinkUp(pAC, IoC, Port);
45452-
45453+
45454 return(SK_HW_PS_LINK);
45455 }
45456
45457@@ -1889,8 +2190,8 @@
45458 */
45459 static int SkGePortCheckUpNat(
45460 SK_AC *pAC, /* Adapter Context */
45461-SK_IOC IoC, /* IO Context */
45462-int Port, /* Which port should be checked */
45463+SK_IOC IoC, /* I/O Context */
45464+int Port, /* Port Index (MAC_1 + n) */
45465 SK_BOOL AutoNeg) /* Is Auto-negotiation used ? */
45466 {
45467 /* todo: National */
45468@@ -1909,38 +2210,40 @@
45469 */
45470 int SkGeSirqEvent(
45471 SK_AC *pAC, /* Adapter Context */
45472-SK_IOC IoC, /* Io Context */
45473+SK_IOC IoC, /* I/O Context */
45474 SK_U32 Event, /* Module specific Event */
45475 SK_EVPARA Para) /* Event specific Parameter */
45476 {
45477 SK_GEPORT *pPrt; /* GIni Port struct pointer */
45478- SK_U32 Port;
45479+ int Port;
45480 SK_U32 Val32;
45481 int PortStat;
45482+#ifndef SK_SLIM
45483 SK_U8 Val8;
45484+#endif
45485 #ifdef GENESIS
45486 SK_U64 Octets;
45487 #endif /* GENESIS */
45488
45489- Port = Para.Para32[0];
45490+ Port = (int)Para.Para32[0];
45491 pPrt = &pAC->GIni.GP[Port];
45492
45493 switch (Event) {
45494 case SK_HWEV_WATIM:
45495 if (pPrt->PState == SK_PRT_RESET) {
45496-
45497+
45498 PortStat = SK_HW_PS_NONE;
45499 }
45500 else {
45501 /* Check whether port came up */
45502- PortStat = SkGePortCheckUp(pAC, IoC, (int)Port);
45503+ PortStat = SkGePortCheckUp(pAC, IoC, Port);
45504 }
45505
45506 switch (PortStat) {
45507 case SK_HW_PS_RESTART:
45508 if (pPrt->PHWLinkUp) {
45509 /* Set Link to down */
45510- SkHWLinkDown(pAC, IoC, (int)Port);
45511+ SkHWLinkDown(pAC, IoC, Port);
45512
45513 /*
45514 * Signal directly to RLMT to ensure correct
45515@@ -1958,22 +2261,28 @@
45516 SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_UP, Para);
45517 break;
45518 }
45519-
45520+
45521 /* Start again the check Timer */
45522 if (pPrt->PHWLinkUp) {
45523+
45524 Val32 = SK_WA_ACT_TIME;
45525 }
45526 else {
45527 Val32 = SK_WA_INA_TIME;
45528- }
45529
45530- /* Todo: still needed for non-XMAC PHYs??? */
45531+ if (pAC->GIni.GIYukon) {
45532+ Val32 *= 5;
45533+ }
45534+ }
45535 /* Start workaround Errata #2 timer */
45536 SkTimerStart(pAC, IoC, &pPrt->PWaTimer, Val32,
45537 SKGE_HWAC, SK_HWEV_WATIM, Para);
45538+
45539 break;
45540
45541 case SK_HWEV_PORT_START:
45542+
45543+#ifndef SK_SLIM
45544 if (pPrt->PHWLinkUp) {
45545 /*
45546 * Signal directly to RLMT to ensure correct
45547@@ -1981,8 +2290,9 @@
45548 */
45549 SkRlmtEvent(pAC, IoC, SK_RLMT_LINK_DOWN, Para);
45550 }
45551+#endif /* !SK_SLIM */
45552
45553- SkHWLinkDown(pAC, IoC, (int)Port);
45554+ SkHWLinkDown(pAC, IoC, Port);
45555
45556 /* Schedule Port RESET */
45557 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Para);
45558@@ -1990,9 +2300,11 @@
45559 /* Start workaround Errata #2 timer */
45560 SkTimerStart(pAC, IoC, &pPrt->PWaTimer, SK_WA_INA_TIME,
45561 SKGE_HWAC, SK_HWEV_WATIM, Para);
45562+
45563 break;
45564
45565 case SK_HWEV_PORT_STOP:
45566+#ifndef SK_SLIM
45567 if (pPrt->PHWLinkUp) {
45568 /*
45569 * Signal directly to RLMT to ensure correct
45570@@ -2000,20 +2312,22 @@
45571 */
45572 SkRlmtEvent(pAC, IoC, SK_RLMT_LINK_DOWN, Para);
45573 }
45574+#endif /* !SK_SLIM */
45575
45576 /* Stop Workaround Timer */
45577 SkTimerStop(pAC, IoC, &pPrt->PWaTimer);
45578
45579- SkHWLinkDown(pAC, IoC, (int)Port);
45580+ SkHWLinkDown(pAC, IoC, Port);
45581 break;
45582
45583+#ifndef SK_SLIM
45584 case SK_HWEV_UPDATE_STAT:
45585 /* We do NOT need to update any statistics */
45586 break;
45587
45588 case SK_HWEV_CLEAR_STAT:
45589 /* We do NOT need to clear any statistics */
45590- for (Port = 0; Port < (SK_U32)pAC->GIni.GIMacsFound; Port++) {
45591+ for (Port = 0; Port < pAC->GIni.GIMacsFound; Port++) {
45592 pPrt->PPrevRx = 0;
45593 pPrt->PPrevFcs = 0;
45594 pPrt->PPrevShorts = 0;
45595@@ -2074,6 +2388,7 @@
45596 SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_PORT_START, Para);
45597 }
45598 break;
45599+#endif /* !SK_SLIM */
45600
45601 #ifdef GENESIS
45602 case SK_HWEV_HALFDUP_CHK:
45603@@ -2085,23 +2400,18 @@
45604 pPrt->HalfDupTimerActive = SK_FALSE;
45605 if (pPrt->PLinkModeStatus == SK_LMODE_STAT_HALF ||
45606 pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOHALF) {
45607-#ifdef XXX
45608- Len = sizeof(SK_U64);
45609- SkPnmiGetVar(pAC, IoC, OID_SKGE_STAT_TX_OCTETS, (char *)&Octets,
45610- &Len, (SK_U32)SK_PNMI_PORT_PHYS2INST(pAC, Port),
45611- pAC->Rlmt.Port[Port].Net->NetNumber);
45612-#endif /* XXX */
45613+
45614 /* Snap statistic counters */
45615 (void)SkXmUpdateStats(pAC, IoC, Port);
45616
45617 (void)SkXmMacStatistic(pAC, IoC, Port, XM_TXO_OK_HI, &Val32);
45618
45619 Octets = (SK_U64)Val32 << 32;
45620-
45621+
45622 (void)SkXmMacStatistic(pAC, IoC, Port, XM_TXO_OK_LO, &Val32);
45623
45624 Octets += Val32;
45625-
45626+
45627 if (pPrt->LastOctets == Octets) {
45628 /* Tx hanging, a FIFO flush restarts it */
45629 SkMacFlushTxFifo(pAC, IoC, Port);
45630@@ -2110,7 +2420,7 @@
45631 }
45632 break;
45633 #endif /* GENESIS */
45634-
45635+
45636 default:
45637 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_SIRQ_E001, SKERR_SIRQ_E001MSG);
45638 break;
45639@@ -2131,8 +2441,8 @@
45640 */
45641 static void SkPhyIsrBcom(
45642 SK_AC *pAC, /* Adapter Context */
45643-SK_IOC IoC, /* Io Context */
45644-int Port, /* Port Num = PHY Num */
45645+SK_IOC IoC, /* I/O Context */
45646+int Port, /* Port Index (MAC_1 + n) */
45647 SK_U16 IStatus) /* Interrupt Status */
45648 {
45649 SK_GEPORT *pPrt; /* GIni Port struct pointer */
45650@@ -2145,7 +2455,7 @@
45651 SK_ERR_LOG(pAC, SK_ERRCL_HW | SK_ERRCL_INIT, SKERR_SIRQ_E022,
45652 SKERR_SIRQ_E022MSG);
45653 }
45654-
45655+
45656 if ((IStatus & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) != 0) {
45657
45658 SkHWLinkDown(pAC, IoC, Port);
45659@@ -2174,8 +2484,8 @@
45660 */
45661 static void SkPhyIsrGmac(
45662 SK_AC *pAC, /* Adapter Context */
45663-SK_IOC IoC, /* Io Context */
45664-int Port, /* Port Num = PHY Num */
45665+SK_IOC IoC, /* I/O Context */
45666+int Port, /* Port Index (MAC_1 + n) */
45667 SK_U16 IStatus) /* Interrupt Status */
45668 {
45669 SK_GEPORT *pPrt; /* GIni Port struct pointer */
45670@@ -2184,37 +2494,69 @@
45671
45672 pPrt = &pAC->GIni.GP[Port];
45673
45674- if ((IStatus & (PHY_M_IS_AN_PR | PHY_M_IS_LST_CHANGE)) != 0) {
45675-
45676- SkHWLinkDown(pAC, IoC, Port);
45677+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
45678+ ("Port %d PHY IRQ, PhyIsrc: 0x%04X\n", Port, IStatus));
45679
45680- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_ADV, &Word);
45681+ if ((IStatus & PHY_M_IS_LST_CHANGE) != 0) {
45682
45683 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
45684- ("AutoNeg.Adv: 0x%04X\n", Word));
45685-
45686- /* Set Auto-negotiation advertisement */
45687- if (pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM) {
45688- /* restore Asymmetric Pause bit */
45689- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_AUNE_ADV,
45690- (SK_U16)(Word | PHY_M_AN_ASP));
45691- }
45692-
45693+ ("Link Status changed\n"));
45694+
45695 Para.Para32[0] = (SK_U32)Port;
45696- /* Signal to RLMT */
45697- SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
45698+
45699+ if (pPrt->PHWLinkUp) {
45700+
45701+ SkHWLinkDown(pAC, IoC, Port);
45702+
45703+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_ADV, &Word);
45704+
45705+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
45706+ ("AutoNeg.Adv: 0x%04X\n", Word));
45707+
45708+ /* Set Auto-negotiation advertisement */
45709+ if (pAC->GIni.GIChipId != CHIP_ID_YUKON_FE &&
45710+ pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM) {
45711+ /* restore Asymmetric Pause bit */
45712+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_AUNE_ADV,
45713+ (SK_U16)(Word | PHY_M_AN_ASP));
45714+ }
45715+
45716+ /* Signal to RLMT */
45717+ SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
45718+ }
45719+ else {
45720+ if ((IStatus & PHY_M_IS_AN_COMPL) != 0) {
45721+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
45722+ ("Auto-Negotiation completed\n"));
45723+ }
45724+
45725+ if ((IStatus & PHY_M_IS_LSP_CHANGE) != 0) {
45726+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
45727+ ("Link Speed changed\n"));
45728+ }
45729+
45730+ SkEventQueue(pAC, SKGE_HWAC, SK_HWEV_WATIM, Para);
45731+ }
45732 }
45733-
45734+
45735 if ((IStatus & PHY_M_IS_AN_ERROR) != 0) {
45736- /* Auto-Negotiation Error */
45737- SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E023, SKERR_SIRQ_E023MSG);
45738+ /* the copper PHY makes 1 retry */
45739+ if (pAC->GIni.GICopperType) {
45740+ /* not logged as error, it might be the first attempt */
45741+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
45742+ ("Auto-Negotiation Error\n"));
45743+ }
45744+ else {
45745+ /* Auto-Negotiation Error */
45746+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E023, SKERR_SIRQ_E023MSG);
45747+ }
45748 }
45749-
45750+
45751 if ((IStatus & PHY_M_IS_FIFO_ERROR) != 0) {
45752 /* FIFO Overflow/Underrun Error */
45753 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E024, SKERR_SIRQ_E024MSG);
45754 }
45755-
45756+
45757 } /* SkPhyIsrGmac */
45758 #endif /* YUKON */
45759
45760@@ -2230,14 +2572,14 @@
45761 */
45762 static void SkPhyIsrLone(
45763 SK_AC *pAC, /* Adapter Context */
45764-SK_IOC IoC, /* Io Context */
45765-int Port, /* Port Num = PHY Num */
45766+SK_IOC IoC, /* I/O Context */
45767+int Port, /* Port Index (MAC_1 + n) */
45768 SK_U16 IStatus) /* Interrupt Status */
45769 {
45770 SK_EVPARA Para;
45771
45772 if (IStatus & (PHY_L_IS_DUP | PHY_L_IS_ISOL)) {
45773-
45774+
45775 SkHWLinkDown(pAC, IoC, Port);
45776
45777 Para.Para32[0] = (SK_U32)Port;
45778@@ -2249,3 +2591,4 @@
45779 #endif /* OTHER_PHY */
45780
45781 /* End of File */
45782+
45783diff -ruN linux/drivers/net/sk98lin/ski2c.c linux-new/drivers/net/sk98lin/ski2c.c
45784--- linux/drivers/net/sk98lin/ski2c.c 2006-04-11 19:19:28.000000000 +0200
45785+++ linux-new/drivers/net/sk98lin/ski2c.c 1970-01-01 01:00:00.000000000 +0100
45786@@ -1,1296 +0,0 @@
45787-/******************************************************************************
45788- *
45789- * Name: ski2c.c
45790- * Project: Gigabit Ethernet Adapters, TWSI-Module
45791- * Version: $Revision$
45792- * Date: $Date$
45793- * Purpose: Functions to access Voltage and Temperature Sensor
45794- *
45795- ******************************************************************************/
45796-
45797-/******************************************************************************
45798- *
45799- * (C)Copyright 1998-2002 SysKonnect.
45800- * (C)Copyright 2002-2003 Marvell.
45801- *
45802- * This program is free software; you can redistribute it and/or modify
45803- * it under the terms of the GNU General Public License as published by
45804- * the Free Software Foundation; either version 2 of the License, or
45805- * (at your option) any later version.
45806- *
45807- * The information in this file is provided "AS IS" without warranty.
45808- *
45809- ******************************************************************************/
45810-
45811-/*
45812- * I2C Protocol
45813- */
45814-#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
45815-static const char SysKonnectFileId[] =
45816- "@(#) $Id$ (C) Marvell. ";
45817-#endif
45818-
45819-#include "h/skdrv1st.h" /* Driver Specific Definitions */
45820-#include "h/lm80.h"
45821-#include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */
45822-
45823-#ifdef __C2MAN__
45824-/*
45825- I2C protocol implementation.
45826-
45827- General Description:
45828-
45829- The I2C protocol is used for the temperature sensors and for
45830- the serial EEPROM which hold the configuration.
45831-
45832- This file covers functions that allow to read write and do
45833- some bulk requests a specified I2C address.
45834-
45835- The Genesis has 2 I2C buses. One for the EEPROM which holds
45836- the VPD Data and one for temperature and voltage sensor.
45837- The following picture shows the I2C buses, I2C devices and
45838- their control registers.
45839-
45840- Note: The VPD functions are in skvpd.c
45841-.
45842-. PCI Config I2C Bus for VPD Data:
45843-.
45844-. +------------+
45845-. | VPD EEPROM |
45846-. +------------+
45847-. |
45848-. | <-- I2C
45849-. |
45850-. +-----------+-----------+
45851-. | |
45852-. +-----------------+ +-----------------+
45853-. | PCI_VPD_ADR_REG | | PCI_VPD_DAT_REG |
45854-. +-----------------+ +-----------------+
45855-.
45856-.
45857-. I2C Bus for LM80 sensor:
45858-.
45859-. +-----------------+
45860-. | Temperature and |
45861-. | Voltage Sensor |
45862-. | LM80 |
45863-. +-----------------+
45864-. |
45865-. |
45866-. I2C --> |
45867-. |
45868-. +----+
45869-. +-------------->| OR |<--+
45870-. | +----+ |
45871-. +------+------+ |
45872-. | | |
45873-. +--------+ +--------+ +----------+
45874-. | B2_I2C | | B2_I2C | | B2_I2C |
45875-. | _CTRL | | _DATA | | _SW |
45876-. +--------+ +--------+ +----------+
45877-.
45878- The I2C bus may be driven by the B2_I2C_SW or by the B2_I2C_CTRL
45879- and B2_I2C_DATA registers.
45880- For driver software it is recommended to use the I2C control and
45881- data register, because I2C bus timing is done by the ASIC and
45882- an interrupt may be received when the I2C request is completed.
45883-
45884- Clock Rate Timing: MIN MAX generated by
45885- VPD EEPROM: 50 kHz 100 kHz HW
45886- LM80 over I2C Ctrl/Data reg. 50 kHz 100 kHz HW
45887- LM80 over B2_I2C_SW register 0 400 kHz SW
45888-
45889- Note: The clock generated by the hardware is dependend on the
45890- PCI clock. If the PCI bus clock is 33 MHz, the I2C/VPD
45891- clock is 50 kHz.
45892- */
45893-intro()
45894-{}
45895-#endif
45896-
45897-#ifdef SK_DIAG
45898-/*
45899- * I2C Fast Mode timing values used by the LM80.
45900- * If new devices are added to the I2C bus the timing values have to be checked.
45901- */
45902-#ifndef I2C_SLOW_TIMING
45903-#define T_CLK_LOW 1300L /* clock low time in ns */
45904-#define T_CLK_HIGH 600L /* clock high time in ns */
45905-#define T_DATA_IN_SETUP 100L /* data in Set-up Time */
45906-#define T_START_HOLD 600L /* start condition hold time */
45907-#define T_START_SETUP 600L /* start condition Set-up time */
45908-#define T_STOP_SETUP 600L /* stop condition Set-up time */
45909-#define T_BUS_IDLE 1300L /* time the bus must free after Tx */
45910-#define T_CLK_2_DATA_OUT 900L /* max. clock low to data output valid */
45911-#else /* I2C_SLOW_TIMING */
45912-/* I2C Standard Mode Timing */
45913-#define T_CLK_LOW 4700L /* clock low time in ns */
45914-#define T_CLK_HIGH 4000L /* clock high time in ns */
45915-#define T_DATA_IN_SETUP 250L /* data in Set-up Time */
45916-#define T_START_HOLD 4000L /* start condition hold time */
45917-#define T_START_SETUP 4700L /* start condition Set-up time */
45918-#define T_STOP_SETUP 4000L /* stop condition Set-up time */
45919-#define T_BUS_IDLE 4700L /* time the bus must free after Tx */
45920-#endif /* !I2C_SLOW_TIMING */
45921-
45922-#define NS2BCLK(x) (((x)*125)/10000)
45923-
45924-/*
45925- * I2C Wire Operations
45926- *
45927- * About I2C_CLK_LOW():
45928- *
45929- * The Data Direction bit (I2C_DATA_DIR) has to be set to input when setting
45930- * clock to low, to prevent the ASIC and the I2C data client from driving the
45931- * serial data line simultaneously (ASIC: last bit of a byte = '1', I2C client
45932- * send an 'ACK'). See also Concentrator Bugreport No. 10192.
45933- */
45934-#define I2C_DATA_HIGH(IoC) SK_I2C_SET_BIT(IoC, I2C_DATA)
45935-#define I2C_DATA_LOW(IoC) SK_I2C_CLR_BIT(IoC, I2C_DATA)
45936-#define I2C_DATA_OUT(IoC) SK_I2C_SET_BIT(IoC, I2C_DATA_DIR)
45937-#define I2C_DATA_IN(IoC) SK_I2C_CLR_BIT(IoC, I2C_DATA_DIR | I2C_DATA)
45938-#define I2C_CLK_HIGH(IoC) SK_I2C_SET_BIT(IoC, I2C_CLK)
45939-#define I2C_CLK_LOW(IoC) SK_I2C_CLR_BIT(IoC, I2C_CLK | I2C_DATA_DIR)
45940-#define I2C_START_COND(IoC) SK_I2C_CLR_BIT(IoC, I2C_CLK)
45941-
45942-#define NS2CLKT(x) ((x*125L)/10000)
45943-
45944-/*--------------- I2C Interface Register Functions --------------- */
45945-
45946-/*
45947- * sending one bit
45948- */
45949-void SkI2cSndBit(
45950-SK_IOC IoC, /* I/O Context */
45951-SK_U8 Bit) /* Bit to send */
45952-{
45953- I2C_DATA_OUT(IoC);
45954- if (Bit) {
45955- I2C_DATA_HIGH(IoC);
45956- }
45957- else {
45958- I2C_DATA_LOW(IoC);
45959- }
45960- SkDgWaitTime(IoC, NS2BCLK(T_DATA_IN_SETUP));
45961- I2C_CLK_HIGH(IoC);
45962- SkDgWaitTime(IoC, NS2BCLK(T_CLK_HIGH));
45963- I2C_CLK_LOW(IoC);
45964-} /* SkI2cSndBit*/
45965-
45966-
45967-/*
45968- * Signal a start to the I2C Bus.
45969- *
45970- * A start is signaled when data goes to low in a high clock cycle.
45971- *
45972- * Ends with Clock Low.
45973- *
45974- * Status: not tested
45975- */
45976-void SkI2cStart(
45977-SK_IOC IoC) /* I/O Context */
45978-{
45979- /* Init data and Clock to output lines */
45980- /* Set Data high */
45981- I2C_DATA_OUT(IoC);
45982- I2C_DATA_HIGH(IoC);
45983- /* Set Clock high */
45984- I2C_CLK_HIGH(IoC);
45985-
45986- SkDgWaitTime(IoC, NS2BCLK(T_START_SETUP));
45987-
45988- /* Set Data Low */
45989- I2C_DATA_LOW(IoC);
45990-
45991- SkDgWaitTime(IoC, NS2BCLK(T_START_HOLD));
45992-
45993- /* Clock low without Data to Input */
45994- I2C_START_COND(IoC);
45995-
45996- SkDgWaitTime(IoC, NS2BCLK(T_CLK_LOW));
45997-} /* SkI2cStart */
45998-
45999-
46000-void SkI2cStop(
46001-SK_IOC IoC) /* I/O Context */
46002-{
46003- /* Init data and Clock to output lines */
46004- /* Set Data low */
46005- I2C_DATA_OUT(IoC);
46006- I2C_DATA_LOW(IoC);
46007-
46008- SkDgWaitTime(IoC, NS2BCLK(T_CLK_2_DATA_OUT));
46009-
46010- /* Set Clock high */
46011- I2C_CLK_HIGH(IoC);
46012-
46013- SkDgWaitTime(IoC, NS2BCLK(T_STOP_SETUP));
46014-
46015- /*
46016- * Set Data High: Do it by setting the Data Line to Input.
46017- * Because of a pull up resistor the Data Line
46018- * floods to high.
46019- */
46020- I2C_DATA_IN(IoC);
46021-
46022- /*
46023- * When I2C activity is stopped
46024- * o DATA should be set to input and
46025- * o CLOCK should be set to high!
46026- */
46027- SkDgWaitTime(IoC, NS2BCLK(T_BUS_IDLE));
46028-} /* SkI2cStop */
46029-
46030-
46031-/*
46032- * Receive just one bit via the I2C bus.
46033- *
46034- * Note: Clock must be set to LOW before calling this function.
46035- *
46036- * Returns The received bit.
46037- */
46038-int SkI2cRcvBit(
46039-SK_IOC IoC) /* I/O Context */
46040-{
46041- int Bit;
46042- SK_U8 I2cSwCtrl;
46043-
46044- /* Init data as input line */
46045- I2C_DATA_IN(IoC);
46046-
46047- SkDgWaitTime(IoC, NS2BCLK(T_CLK_2_DATA_OUT));
46048-
46049- I2C_CLK_HIGH(IoC);
46050-
46051- SkDgWaitTime(IoC, NS2BCLK(T_CLK_HIGH));
46052-
46053- SK_I2C_GET_SW(IoC, &I2cSwCtrl);
46054-
46055- Bit = (I2cSwCtrl & I2C_DATA) ? 1 : 0;
46056-
46057- I2C_CLK_LOW(IoC);
46058- SkDgWaitTime(IoC, NS2BCLK(T_CLK_LOW-T_CLK_2_DATA_OUT));
46059-
46060- return(Bit);
46061-} /* SkI2cRcvBit */
46062-
46063-
46064-/*
46065- * Receive an ACK.
46066- *
46067- * returns 0 If acknowledged
46068- * 1 in case of an error
46069- */
46070-int SkI2cRcvAck(
46071-SK_IOC IoC) /* I/O Context */
46072-{
46073- /*
46074- * Received bit must be zero.
46075- */
46076- return(SkI2cRcvBit(IoC) != 0);
46077-} /* SkI2cRcvAck */
46078-
46079-
46080-/*
46081- * Send an NACK.
46082- */
46083-void SkI2cSndNAck(
46084-SK_IOC IoC) /* I/O Context */
46085-{
46086- /*
46087- * Received bit must be zero.
46088- */
46089- SkI2cSndBit(IoC, 1);
46090-} /* SkI2cSndNAck */
46091-
46092-
46093-/*
46094- * Send an ACK.
46095- */
46096-void SkI2cSndAck(
46097-SK_IOC IoC) /* I/O Context */
46098-{
46099- /*
46100- * Received bit must be zero.
46101- */
46102- SkI2cSndBit(IoC, 0);
46103-} /* SkI2cSndAck */
46104-
46105-
46106-/*
46107- * Send one byte to the I2C device and wait for ACK.
46108- *
46109- * Return acknowleged status.
46110- */
46111-int SkI2cSndByte(
46112-SK_IOC IoC, /* I/O Context */
46113-int Byte) /* byte to send */
46114-{
46115- int i;
46116-
46117- for (i = 0; i < 8; i++) {
46118- if (Byte & (1<<(7-i))) {
46119- SkI2cSndBit(IoC, 1);
46120- }
46121- else {
46122- SkI2cSndBit(IoC, 0);
46123- }
46124- }
46125-
46126- return(SkI2cRcvAck(IoC));
46127-} /* SkI2cSndByte */
46128-
46129-
46130-/*
46131- * Receive one byte and ack it.
46132- *
46133- * Return byte.
46134- */
46135-int SkI2cRcvByte(
46136-SK_IOC IoC, /* I/O Context */
46137-int Last) /* Last Byte Flag */
46138-{
46139- int i;
46140- int Byte = 0;
46141-
46142- for (i = 0; i < 8; i++) {
46143- Byte <<= 1;
46144- Byte |= SkI2cRcvBit(IoC);
46145- }
46146-
46147- if (Last) {
46148- SkI2cSndNAck(IoC);
46149- }
46150- else {
46151- SkI2cSndAck(IoC);
46152- }
46153-
46154- return(Byte);
46155-} /* SkI2cRcvByte */
46156-
46157-
46158-/*
46159- * Start dialog and send device address
46160- *
46161- * Return 0 if acknowleged, 1 in case of an error
46162- */
46163-int SkI2cSndDev(
46164-SK_IOC IoC, /* I/O Context */
46165-int Addr, /* Device Address */
46166-int Rw) /* Read / Write Flag */
46167-{
46168- SkI2cStart(IoC);
46169- Rw = ~Rw;
46170- Rw &= I2C_WRITE;
46171- return(SkI2cSndByte(IoC, (Addr<<1) | Rw));
46172-} /* SkI2cSndDev */
46173-
46174-#endif /* SK_DIAG */
46175-
46176-/*----------------- I2C CTRL Register Functions ----------*/
46177-
46178-/*
46179- * waits for a completion of an I2C transfer
46180- *
46181- * returns 0: success, transfer completes
46182- * 1: error, transfer does not complete, I2C transfer
46183- * killed, wait loop terminated.
46184- */
46185-int SkI2cWait(
46186-SK_AC *pAC, /* Adapter Context */
46187-SK_IOC IoC, /* I/O Context */
46188-int Event) /* complete event to wait for (I2C_READ or I2C_WRITE) */
46189-{
46190- SK_U64 StartTime;
46191- SK_U64 CurrentTime;
46192- SK_U32 I2cCtrl;
46193-
46194- StartTime = SkOsGetTime(pAC);
46195-
46196- do {
46197- CurrentTime = SkOsGetTime(pAC);
46198-
46199- if (CurrentTime - StartTime > SK_TICKS_PER_SEC / 8) {
46200-
46201- SK_I2C_STOP(IoC);
46202-#ifndef SK_DIAG
46203- SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E002, SKERR_I2C_E002MSG);
46204-#endif /* !SK_DIAG */
46205- return(1);
46206- }
46207-
46208- SK_I2C_GET_CTL(IoC, &I2cCtrl);
46209-
46210-#ifdef xYUKON_DBG
46211- printf("StartTime=%lu, CurrentTime=%lu\n",
46212- StartTime, CurrentTime);
46213- if (kbhit()) {
46214- return(1);
46215- }
46216-#endif /* YUKON_DBG */
46217-
46218- } while ((I2cCtrl & I2C_FLAG) == (SK_U32)Event << 31);
46219-
46220- return(0);
46221-} /* SkI2cWait */
46222-
46223-
46224-/*
46225- * waits for a completion of an I2C transfer
46226- *
46227- * Returns
46228- * Nothing
46229- */
46230-void SkI2cWaitIrq(
46231-SK_AC *pAC, /* Adapter Context */
46232-SK_IOC IoC) /* I/O Context */
46233-{
46234- SK_SENSOR *pSen;
46235- SK_U64 StartTime;
46236- SK_U32 IrqSrc;
46237-
46238- pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
46239-
46240- if (pSen->SenState == SK_SEN_IDLE) {
46241- return;
46242- }
46243-
46244- StartTime = SkOsGetTime(pAC);
46245-
46246- do {
46247- if (SkOsGetTime(pAC) - StartTime > SK_TICKS_PER_SEC / 8) {
46248-
46249- SK_I2C_STOP(IoC);
46250-#ifndef SK_DIAG
46251- SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E016, SKERR_I2C_E016MSG);
46252-#endif /* !SK_DIAG */
46253- return;
46254- }
46255-
46256- SK_IN32(IoC, B0_ISRC, &IrqSrc);
46257-
46258- } while ((IrqSrc & IS_I2C_READY) == 0);
46259-
46260- pSen->SenState = SK_SEN_IDLE;
46261- return;
46262-} /* SkI2cWaitIrq */
46263-
46264-/*
46265- * writes a single byte or 4 bytes into the I2C device
46266- *
46267- * returns 0: success
46268- * 1: error
46269- */
46270-int SkI2cWrite(
46271-SK_AC *pAC, /* Adapter Context */
46272-SK_IOC IoC, /* I/O Context */
46273-SK_U32 I2cData, /* I2C Data to write */
46274-int I2cDev, /* I2C Device Address */
46275-int I2cDevSize, /* I2C Device Size (e.g. I2C_025K_DEV or I2C_2K_DEV) */
46276-int I2cReg, /* I2C Device Register Address */
46277-int I2cBurst) /* I2C Burst Flag */
46278-{
46279- SK_OUT32(IoC, B2_I2C_DATA, I2cData);
46280-
46281- SK_I2C_CTL(IoC, I2C_WRITE, I2cDev, I2cDevSize, I2cReg, I2cBurst);
46282-
46283- return(SkI2cWait(pAC, IoC, I2C_WRITE));
46284-} /* SkI2cWrite*/
46285-
46286-
46287-#ifdef SK_DIAG
46288-/*
46289- * reads a single byte or 4 bytes from the I2C device
46290- *
46291- * returns the word read
46292- */
46293-SK_U32 SkI2cRead(
46294-SK_AC *pAC, /* Adapter Context */
46295-SK_IOC IoC, /* I/O Context */
46296-int I2cDev, /* I2C Device Address */
46297-int I2cDevSize, /* I2C Device Size (e.g. I2C_025K_DEV or I2C_2K_DEV) */
46298-int I2cReg, /* I2C Device Register Address */
46299-int I2cBurst) /* I2C Burst Flag */
46300-{
46301- SK_U32 Data;
46302-
46303- SK_OUT32(IoC, B2_I2C_DATA, 0);
46304- SK_I2C_CTL(IoC, I2C_READ, I2cDev, I2cDevSize, I2cReg, I2cBurst);
46305-
46306- if (SkI2cWait(pAC, IoC, I2C_READ) != 0) {
46307- w_print("%s\n", SKERR_I2C_E002MSG);
46308- }
46309-
46310- SK_IN32(IoC, B2_I2C_DATA, &Data);
46311-
46312- return(Data);
46313-} /* SkI2cRead */
46314-#endif /* SK_DIAG */
46315-
46316-
46317-/*
46318- * read a sensor's value
46319- *
46320- * This function reads a sensor's value from the I2C sensor chip. The sensor
46321- * is defined by its index into the sensors database in the struct pAC points
46322- * to.
46323- * Returns
46324- * 1 if the read is completed
46325- * 0 if the read must be continued (I2C Bus still allocated)
46326- */
46327-int SkI2cReadSensor(
46328-SK_AC *pAC, /* Adapter Context */
46329-SK_IOC IoC, /* I/O Context */
46330-SK_SENSOR *pSen) /* Sensor to be read */
46331-{
46332- if (pSen->SenRead != NULL) {
46333- return((*pSen->SenRead)(pAC, IoC, pSen));
46334- }
46335- else {
46336- return(0); /* no success */
46337- }
46338-} /* SkI2cReadSensor */
46339-
46340-/*
46341- * Do the Init state 0 initialization
46342- */
46343-static int SkI2cInit0(
46344-SK_AC *pAC) /* Adapter Context */
46345-{
46346- int i;
46347-
46348- /* Begin with first sensor */
46349- pAC->I2c.CurrSens = 0;
46350-
46351- /* Begin with timeout control for state machine */
46352- pAC->I2c.TimerMode = SK_TIMER_WATCH_SM;
46353-
46354- /* Set sensor number to zero */
46355- pAC->I2c.MaxSens = 0;
46356-
46357-#ifndef SK_DIAG
46358- /* Initialize Number of Dummy Reads */
46359- pAC->I2c.DummyReads = SK_MAX_SENSORS;
46360-#endif
46361-
46362- for (i = 0; i < SK_MAX_SENSORS; i++) {
46363- pAC->I2c.SenTable[i].SenDesc = "unknown";
46364- pAC->I2c.SenTable[i].SenType = SK_SEN_UNKNOWN;
46365- pAC->I2c.SenTable[i].SenThreErrHigh = 0;
46366- pAC->I2c.SenTable[i].SenThreErrLow = 0;
46367- pAC->I2c.SenTable[i].SenThreWarnHigh = 0;
46368- pAC->I2c.SenTable[i].SenThreWarnLow = 0;
46369- pAC->I2c.SenTable[i].SenReg = LM80_FAN2_IN;
46370- pAC->I2c.SenTable[i].SenInit = SK_SEN_DYN_INIT_NONE;
46371- pAC->I2c.SenTable[i].SenValue = 0;
46372- pAC->I2c.SenTable[i].SenErrFlag = SK_SEN_ERR_NOT_PRESENT;
46373- pAC->I2c.SenTable[i].SenErrCts = 0;
46374- pAC->I2c.SenTable[i].SenBegErrTS = 0;
46375- pAC->I2c.SenTable[i].SenState = SK_SEN_IDLE;
46376- pAC->I2c.SenTable[i].SenRead = NULL;
46377- pAC->I2c.SenTable[i].SenDev = 0;
46378- }
46379-
46380- /* Now we are "INIT data"ed */
46381- pAC->I2c.InitLevel = SK_INIT_DATA;
46382- return(0);
46383-} /* SkI2cInit0*/
46384-
46385-
46386-/*
46387- * Do the init state 1 initialization
46388- *
46389- * initialize the following register of the LM80:
46390- * Configuration register:
46391- * - START, noINT, activeLOW, noINT#Clear, noRESET, noCI, noGPO#, noINIT
46392- *
46393- * Interrupt Mask Register 1:
46394- * - all interrupts are Disabled (0xff)
46395- *
46396- * Interrupt Mask Register 2:
46397- * - all interrupts are Disabled (0xff) Interrupt modi doesn't matter.
46398- *
46399- * Fan Divisor/RST_OUT register:
46400- * - Divisors set to 1 (bits 00), all others 0s.
46401- *
46402- * OS# Configuration/Temperature resolution Register:
46403- * - all 0s
46404- *
46405- */
46406-static int SkI2cInit1(
46407-SK_AC *pAC, /* Adapter Context */
46408-SK_IOC IoC) /* I/O Context */
46409-{
46410- int i;
46411- SK_U8 I2cSwCtrl;
46412- SK_GEPORT *pPrt; /* GIni Port struct pointer */
46413-
46414- if (pAC->I2c.InitLevel != SK_INIT_DATA) {
46415- /* ReInit not needed in I2C module */
46416- return(0);
46417- }
46418-
46419- /* Set the Direction of I2C-Data Pin to IN */
46420- SK_I2C_CLR_BIT(IoC, I2C_DATA_DIR | I2C_DATA);
46421- /* Check for 32-Bit Yukon with Low at I2C-Data Pin */
46422- SK_I2C_GET_SW(IoC, &I2cSwCtrl);
46423-
46424- if ((I2cSwCtrl & I2C_DATA) == 0) {
46425- /* this is a 32-Bit board */
46426- pAC->GIni.GIYukon32Bit = SK_TRUE;
46427- return(0);
46428- }
46429-
46430- /* Check for 64 Bit Yukon without sensors */
46431- if (SkI2cWrite(pAC, IoC, 0, LM80_ADDR, I2C_025K_DEV, LM80_CFG, 0) != 0) {
46432- return(0);
46433- }
46434-
46435- (void)SkI2cWrite(pAC, IoC, 0xffUL, LM80_ADDR, I2C_025K_DEV, LM80_IMSK_1, 0);
46436-
46437- (void)SkI2cWrite(pAC, IoC, 0xffUL, LM80_ADDR, I2C_025K_DEV, LM80_IMSK_2, 0);
46438-
46439- (void)SkI2cWrite(pAC, IoC, 0, LM80_ADDR, I2C_025K_DEV, LM80_FAN_CTRL, 0);
46440-
46441- (void)SkI2cWrite(pAC, IoC, 0, LM80_ADDR, I2C_025K_DEV, LM80_TEMP_CTRL, 0);
46442-
46443- (void)SkI2cWrite(pAC, IoC, (SK_U32)LM80_CFG_START, LM80_ADDR, I2C_025K_DEV,
46444- LM80_CFG, 0);
46445-
46446- /*
46447- * MaxSens has to be updated here, because PhyType is not
46448- * set when performing Init Level 0
46449- */
46450- pAC->I2c.MaxSens = 5;
46451-
46452- pPrt = &pAC->GIni.GP[0];
46453-
46454- if (pAC->GIni.GIGenesis) {
46455- if (pPrt->PhyType == SK_PHY_BCOM) {
46456- if (pAC->GIni.GIMacsFound == 1) {
46457- pAC->I2c.MaxSens += 1;
46458- }
46459- else {
46460- pAC->I2c.MaxSens += 3;
46461- }
46462- }
46463- }
46464- else {
46465- pAC->I2c.MaxSens += 3;
46466- }
46467-
46468- for (i = 0; i < pAC->I2c.MaxSens; i++) {
46469- switch (i) {
46470- case 0:
46471- pAC->I2c.SenTable[i].SenDesc = "Temperature";
46472- pAC->I2c.SenTable[i].SenType = SK_SEN_TEMP;
46473- pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_TEMP_HIGH_ERR;
46474- pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_TEMP_HIGH_WARN;
46475- pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_TEMP_LOW_WARN;
46476- pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_TEMP_LOW_ERR;
46477- pAC->I2c.SenTable[i].SenReg = LM80_TEMP_IN;
46478- break;
46479- case 1:
46480- pAC->I2c.SenTable[i].SenDesc = "Voltage PCI";
46481- pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
46482- pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PCI_5V_HIGH_ERR;
46483- pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PCI_5V_HIGH_WARN;
46484- pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PCI_5V_LOW_WARN;
46485- pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PCI_5V_LOW_ERR;
46486- pAC->I2c.SenTable[i].SenReg = LM80_VT0_IN;
46487- break;
46488- case 2:
46489- pAC->I2c.SenTable[i].SenDesc = "Voltage PCI-IO";
46490- pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
46491- pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PCI_IO_5V_HIGH_ERR;
46492- pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PCI_IO_5V_HIGH_WARN;
46493- pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PCI_IO_3V3_LOW_WARN;
46494- pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PCI_IO_3V3_LOW_ERR;
46495- pAC->I2c.SenTable[i].SenReg = LM80_VT1_IN;
46496- pAC->I2c.SenTable[i].SenInit = SK_SEN_DYN_INIT_PCI_IO;
46497- break;
46498- case 3:
46499- pAC->I2c.SenTable[i].SenDesc = "Voltage ASIC";
46500- pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
46501- pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_VDD_HIGH_ERR;
46502- pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_VDD_HIGH_WARN;
46503- pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_VDD_LOW_WARN;
46504- pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_VDD_LOW_ERR;
46505- pAC->I2c.SenTable[i].SenReg = LM80_VT2_IN;
46506- break;
46507- case 4:
46508- if (pAC->GIni.GIGenesis) {
46509- if (pPrt->PhyType == SK_PHY_BCOM) {
46510- pAC->I2c.SenTable[i].SenDesc = "Voltage PHY A PLL";
46511- pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR;
46512- pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN;
46513- pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN;
46514- pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR;
46515- }
46516- else {
46517- pAC->I2c.SenTable[i].SenDesc = "Voltage PMA";
46518- pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR;
46519- pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN;
46520- pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN;
46521- pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR;
46522- }
46523- }
46524- else {
46525- pAC->I2c.SenTable[i].SenDesc = "Voltage VAUX";
46526- pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_VAUX_3V3_HIGH_ERR;
46527- pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_VAUX_3V3_HIGH_WARN;
46528- if (pAC->GIni.GIVauxAvail) {
46529- pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_VAUX_3V3_LOW_WARN;
46530- pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_VAUX_3V3_LOW_ERR;
46531- }
46532- else {
46533- pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_VAUX_0V_WARN_ERR;
46534- pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_VAUX_0V_WARN_ERR;
46535- }
46536- }
46537- pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
46538- pAC->I2c.SenTable[i].SenReg = LM80_VT3_IN;
46539- break;
46540- case 5:
46541- if (pAC->GIni.GIGenesis) {
46542- pAC->I2c.SenTable[i].SenDesc = "Voltage PHY 2V5";
46543- pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PHY_2V5_HIGH_ERR;
46544- pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PHY_2V5_HIGH_WARN;
46545- pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PHY_2V5_LOW_WARN;
46546- pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PHY_2V5_LOW_ERR;
46547- }
46548- else {
46549- pAC->I2c.SenTable[i].SenDesc = "Voltage Core 1V5";
46550- pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_CORE_1V5_HIGH_ERR;
46551- pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_CORE_1V5_HIGH_WARN;
46552- pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_CORE_1V5_LOW_WARN;
46553- pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_CORE_1V5_LOW_ERR;
46554- }
46555- pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
46556- pAC->I2c.SenTable[i].SenReg = LM80_VT4_IN;
46557- break;
46558- case 6:
46559- if (pAC->GIni.GIGenesis) {
46560- pAC->I2c.SenTable[i].SenDesc = "Voltage PHY B PLL";
46561- }
46562- else {
46563- pAC->I2c.SenTable[i].SenDesc = "Voltage PHY 3V3";
46564- }
46565- pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
46566- pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR;
46567- pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN;
46568- pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN;
46569- pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR;
46570- pAC->I2c.SenTable[i].SenReg = LM80_VT5_IN;
46571- break;
46572- case 7:
46573- if (pAC->GIni.GIGenesis) {
46574- pAC->I2c.SenTable[i].SenDesc = "Speed Fan";
46575- pAC->I2c.SenTable[i].SenType = SK_SEN_FAN;
46576- pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_FAN_HIGH_ERR;
46577- pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_FAN_HIGH_WARN;
46578- pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_FAN_LOW_WARN;
46579- pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_FAN_LOW_ERR;
46580- pAC->I2c.SenTable[i].SenReg = LM80_FAN2_IN;
46581- }
46582- else {
46583- pAC->I2c.SenTable[i].SenDesc = "Voltage PHY 2V5";
46584- pAC->I2c.SenTable[i].SenType = SK_SEN_VOLT;
46585- pAC->I2c.SenTable[i].SenThreErrHigh = SK_SEN_PHY_2V5_HIGH_ERR;
46586- pAC->I2c.SenTable[i].SenThreWarnHigh = SK_SEN_PHY_2V5_HIGH_WARN;
46587- pAC->I2c.SenTable[i].SenThreWarnLow = SK_SEN_PHY_2V5_LOW_WARN;
46588- pAC->I2c.SenTable[i].SenThreErrLow = SK_SEN_PHY_2V5_LOW_ERR;
46589- pAC->I2c.SenTable[i].SenReg = LM80_VT6_IN;
46590- }
46591- break;
46592- default:
46593- SK_ERR_LOG(pAC, SK_ERRCL_INIT | SK_ERRCL_SW,
46594- SKERR_I2C_E001, SKERR_I2C_E001MSG);
46595- break;
46596- }
46597-
46598- pAC->I2c.SenTable[i].SenValue = 0;
46599- pAC->I2c.SenTable[i].SenErrFlag = SK_SEN_ERR_OK;
46600- pAC->I2c.SenTable[i].SenErrCts = 0;
46601- pAC->I2c.SenTable[i].SenBegErrTS = 0;
46602- pAC->I2c.SenTable[i].SenState = SK_SEN_IDLE;
46603- pAC->I2c.SenTable[i].SenRead = SkLm80ReadSensor;
46604- pAC->I2c.SenTable[i].SenDev = LM80_ADDR;
46605- }
46606-
46607-#ifndef SK_DIAG
46608- pAC->I2c.DummyReads = pAC->I2c.MaxSens;
46609-#endif /* !SK_DIAG */
46610-
46611- /* Clear I2C IRQ */
46612- SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
46613-
46614- /* Now we are I/O initialized */
46615- pAC->I2c.InitLevel = SK_INIT_IO;
46616- return(0);
46617-} /* SkI2cInit1 */
46618-
46619-
46620-/*
46621- * Init level 2: Start first sensor read.
46622- */
46623-static int SkI2cInit2(
46624-SK_AC *pAC, /* Adapter Context */
46625-SK_IOC IoC) /* I/O Context */
46626-{
46627- int ReadComplete;
46628- SK_SENSOR *pSen;
46629-
46630- if (pAC->I2c.InitLevel != SK_INIT_IO) {
46631- /* ReInit not needed in I2C module */
46632- /* Init0 and Init2 not permitted */
46633- return(0);
46634- }
46635-
46636- pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
46637- ReadComplete = SkI2cReadSensor(pAC, IoC, pSen);
46638-
46639- if (ReadComplete) {
46640- SK_ERR_LOG(pAC, SK_ERRCL_INIT, SKERR_I2C_E008, SKERR_I2C_E008MSG);
46641- }
46642-
46643- /* Now we are correctly initialized */
46644- pAC->I2c.InitLevel = SK_INIT_RUN;
46645-
46646- return(0);
46647-} /* SkI2cInit2*/
46648-
46649-
46650-/*
46651- * Initialize I2C devices
46652- *
46653- * Get the first voltage value and discard it.
46654- * Go into temperature read mode. A default pointer is not set.
46655- *
46656- * The things to be done depend on the init level in the parameter list:
46657- * Level 0:
46658- * Initialize only the data structures. Do NOT access hardware.
46659- * Level 1:
46660- * Initialize hardware through SK_IN / SK_OUT commands. Do NOT use interrupts.
46661- * Level 2:
46662- * Everything is possible. Interrupts may be used from now on.
46663- *
46664- * return:
46665- * 0 = success
46666- * other = error.
46667- */
46668-int SkI2cInit(
46669-SK_AC *pAC, /* Adapter Context */
46670-SK_IOC IoC, /* I/O Context needed in levels 1 and 2 */
46671-int Level) /* Init Level */
46672-{
46673-
46674- switch (Level) {
46675- case SK_INIT_DATA:
46676- return(SkI2cInit0(pAC));
46677- case SK_INIT_IO:
46678- return(SkI2cInit1(pAC, IoC));
46679- case SK_INIT_RUN:
46680- return(SkI2cInit2(pAC, IoC));
46681- default:
46682- break;
46683- }
46684-
46685- return(0);
46686-} /* SkI2cInit */
46687-
46688-
46689-#ifndef SK_DIAG
46690-
46691-/*
46692- * Interrupt service function for the I2C Interface
46693- *
46694- * Clears the Interrupt source
46695- *
46696- * Reads the register and check it for sending a trap.
46697- *
46698- * Starts the timer if necessary.
46699- */
46700-void SkI2cIsr(
46701-SK_AC *pAC, /* Adapter Context */
46702-SK_IOC IoC) /* I/O Context */
46703-{
46704- SK_EVPARA Para;
46705-
46706- /* Clear I2C IRQ */
46707- SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
46708-
46709- Para.Para64 = 0;
46710- SkEventQueue(pAC, SKGE_I2C, SK_I2CEV_IRQ, Para);
46711-} /* SkI2cIsr */
46712-
46713-
46714-/*
46715- * Check this sensors Value against the threshold and send events.
46716- */
46717-static void SkI2cCheckSensor(
46718-SK_AC *pAC, /* Adapter Context */
46719-SK_SENSOR *pSen)
46720-{
46721- SK_EVPARA ParaLocal;
46722- SK_BOOL TooHigh; /* Is sensor too high? */
46723- SK_BOOL TooLow; /* Is sensor too low? */
46724- SK_U64 CurrTime; /* Current Time */
46725- SK_BOOL DoTrapSend; /* We need to send a trap */
46726- SK_BOOL DoErrLog; /* We need to log the error */
46727- SK_BOOL IsError; /* We need to log the error */
46728-
46729- /* Check Dummy Reads first */
46730- if (pAC->I2c.DummyReads > 0) {
46731- pAC->I2c.DummyReads--;
46732- return;
46733- }
46734-
46735- /* Get the current time */
46736- CurrTime = SkOsGetTime(pAC);
46737-
46738- /* Set para to the most useful setting: The current sensor. */
46739- ParaLocal.Para64 = (SK_U64)pAC->I2c.CurrSens;
46740-
46741- /* Check the Value against the thresholds. First: Error Thresholds */
46742- TooHigh = (pSen->SenValue > pSen->SenThreErrHigh);
46743- TooLow = (pSen->SenValue < pSen->SenThreErrLow);
46744-
46745- IsError = SK_FALSE;
46746- if (TooHigh || TooLow) {
46747- /* Error condition is satisfied */
46748- DoTrapSend = SK_TRUE;
46749- DoErrLog = SK_TRUE;
46750-
46751- /* Now error condition is satisfied */
46752- IsError = SK_TRUE;
46753-
46754- if (pSen->SenErrFlag == SK_SEN_ERR_ERR) {
46755- /* This state is the former one */
46756-
46757- /* So check first whether we have to send a trap */
46758- if (pSen->SenLastErrTrapTS + SK_SEN_ERR_TR_HOLD >
46759- CurrTime) {
46760- /*
46761- * Do NOT send the Trap. The hold back time
46762- * has to run out first.
46763- */
46764- DoTrapSend = SK_FALSE;
46765- }
46766-
46767- /* Check now whether we have to log an Error */
46768- if (pSen->SenLastErrLogTS + SK_SEN_ERR_LOG_HOLD >
46769- CurrTime) {
46770- /*
46771- * Do NOT log the error. The hold back time
46772- * has to run out first.
46773- */
46774- DoErrLog = SK_FALSE;
46775- }
46776- }
46777- else {
46778- /* We came from a different state -> Set Begin Time Stamp */
46779- pSen->SenBegErrTS = CurrTime;
46780- pSen->SenErrFlag = SK_SEN_ERR_ERR;
46781- }
46782-
46783- if (DoTrapSend) {
46784- /* Set current Time */
46785- pSen->SenLastErrTrapTS = CurrTime;
46786- pSen->SenErrCts++;
46787-
46788- /* Queue PNMI Event */
46789- SkEventQueue(pAC, SKGE_PNMI, (TooHigh ?
46790- SK_PNMI_EVT_SEN_ERR_UPP :
46791- SK_PNMI_EVT_SEN_ERR_LOW),
46792- ParaLocal);
46793- }
46794-
46795- if (DoErrLog) {
46796- /* Set current Time */
46797- pSen->SenLastErrLogTS = CurrTime;
46798-
46799- if (pSen->SenType == SK_SEN_TEMP) {
46800- SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E011, SKERR_I2C_E011MSG);
46801- }
46802- else if (pSen->SenType == SK_SEN_VOLT) {
46803- SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E012, SKERR_I2C_E012MSG);
46804- }
46805- else {
46806- SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E015, SKERR_I2C_E015MSG);
46807- }
46808- }
46809- }
46810-
46811- /* Check the Value against the thresholds */
46812- /* 2nd: Warning thresholds */
46813- TooHigh = (pSen->SenValue > pSen->SenThreWarnHigh);
46814- TooLow = (pSen->SenValue < pSen->SenThreWarnLow);
46815-
46816- if (!IsError && (TooHigh || TooLow)) {
46817- /* Error condition is satisfied */
46818- DoTrapSend = SK_TRUE;
46819- DoErrLog = SK_TRUE;
46820-
46821- if (pSen->SenErrFlag == SK_SEN_ERR_WARN) {
46822- /* This state is the former one */
46823-
46824- /* So check first whether we have to send a trap */
46825- if (pSen->SenLastWarnTrapTS + SK_SEN_WARN_TR_HOLD > CurrTime) {
46826- /*
46827- * Do NOT send the Trap. The hold back time
46828- * has to run out first.
46829- */
46830- DoTrapSend = SK_FALSE;
46831- }
46832-
46833- /* Check now whether we have to log an Error */
46834- if (pSen->SenLastWarnLogTS + SK_SEN_WARN_LOG_HOLD > CurrTime) {
46835- /*
46836- * Do NOT log the error. The hold back time
46837- * has to run out first.
46838- */
46839- DoErrLog = SK_FALSE;
46840- }
46841- }
46842- else {
46843- /* We came from a different state -> Set Begin Time Stamp */
46844- pSen->SenBegWarnTS = CurrTime;
46845- pSen->SenErrFlag = SK_SEN_ERR_WARN;
46846- }
46847-
46848- if (DoTrapSend) {
46849- /* Set current Time */
46850- pSen->SenLastWarnTrapTS = CurrTime;
46851- pSen->SenWarnCts++;
46852-
46853- /* Queue PNMI Event */
46854- SkEventQueue(pAC, SKGE_PNMI, (TooHigh ?
46855- SK_PNMI_EVT_SEN_WAR_UPP :
46856- SK_PNMI_EVT_SEN_WAR_LOW),
46857- ParaLocal);
46858- }
46859-
46860- if (DoErrLog) {
46861- /* Set current Time */
46862- pSen->SenLastWarnLogTS = CurrTime;
46863-
46864- if (pSen->SenType == SK_SEN_TEMP) {
46865- SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E009, SKERR_I2C_E009MSG);
46866- }
46867- else if (pSen->SenType == SK_SEN_VOLT) {
46868- SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E010, SKERR_I2C_E010MSG);
46869- }
46870- else {
46871- SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E014, SKERR_I2C_E014MSG);
46872- }
46873- }
46874- }
46875-
46876- /* Check for NO error at all */
46877- if (!IsError && !TooHigh && !TooLow) {
46878- /* Set o.k. Status if no error and no warning condition */
46879- pSen->SenErrFlag = SK_SEN_ERR_OK;
46880- }
46881-
46882- /* End of check against the thresholds */
46883-
46884- /* Bug fix AF: 16.Aug.2001: Correct the init base
46885- * of LM80 sensor.
46886- */
46887- if (pSen->SenInit == SK_SEN_DYN_INIT_PCI_IO) {
46888-
46889- pSen->SenInit = SK_SEN_DYN_INIT_NONE;
46890-
46891- if (pSen->SenValue > SK_SEN_PCI_IO_RANGE_LIMITER) {
46892- /* 5V PCI-IO Voltage */
46893- pSen->SenThreWarnLow = SK_SEN_PCI_IO_5V_LOW_WARN;
46894- pSen->SenThreErrLow = SK_SEN_PCI_IO_5V_LOW_ERR;
46895- }
46896- else {
46897- /* 3.3V PCI-IO Voltage */
46898- pSen->SenThreWarnHigh = SK_SEN_PCI_IO_3V3_HIGH_WARN;
46899- pSen->SenThreErrHigh = SK_SEN_PCI_IO_3V3_HIGH_ERR;
46900- }
46901- }
46902-
46903-#ifdef TEST_ONLY
46904- /* Dynamic thresholds also for VAUX of LM80 sensor */
46905- if (pSen->SenInit == SK_SEN_DYN_INIT_VAUX) {
46906-
46907- pSen->SenInit = SK_SEN_DYN_INIT_NONE;
46908-
46909- /* 3.3V VAUX Voltage */
46910- if (pSen->SenValue > SK_SEN_VAUX_RANGE_LIMITER) {
46911- pSen->SenThreWarnLow = SK_SEN_VAUX_3V3_LOW_WARN;
46912- pSen->SenThreErrLow = SK_SEN_VAUX_3V3_LOW_ERR;
46913- }
46914- /* 0V VAUX Voltage */
46915- else {
46916- pSen->SenThreWarnHigh = SK_SEN_VAUX_0V_WARN_ERR;
46917- pSen->SenThreErrHigh = SK_SEN_VAUX_0V_WARN_ERR;
46918- }
46919- }
46920-
46921- /*
46922- * Check initialization state:
46923- * The VIO Thresholds need adaption
46924- */
46925- if (!pSen->SenInit && pSen->SenReg == LM80_VT1_IN &&
46926- pSen->SenValue > SK_SEN_WARNLOW2C &&
46927- pSen->SenValue < SK_SEN_WARNHIGH2) {
46928- pSen->SenThreErrLow = SK_SEN_ERRLOW2C;
46929- pSen->SenThreWarnLow = SK_SEN_WARNLOW2C;
46930- pSen->SenInit = SK_TRUE;
46931- }
46932-
46933- if (!pSen->SenInit && pSen->SenReg == LM80_VT1_IN &&
46934- pSen->SenValue > SK_SEN_WARNLOW2 &&
46935- pSen->SenValue < SK_SEN_WARNHIGH2C) {
46936- pSen->SenThreErrHigh = SK_SEN_ERRHIGH2C;
46937- pSen->SenThreWarnHigh = SK_SEN_WARNHIGH2C;
46938- pSen->SenInit = SK_TRUE;
46939- }
46940-#endif
46941-
46942- if (pSen->SenInit != SK_SEN_DYN_INIT_NONE) {
46943- SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E013, SKERR_I2C_E013MSG);
46944- }
46945-} /* SkI2cCheckSensor */
46946-
46947-
46948-/*
46949- * The only Event to be served is the timeout event
46950- *
46951- */
46952-int SkI2cEvent(
46953-SK_AC *pAC, /* Adapter Context */
46954-SK_IOC IoC, /* I/O Context */
46955-SK_U32 Event, /* Module specific Event */
46956-SK_EVPARA Para) /* Event specific Parameter */
46957-{
46958- int ReadComplete;
46959- SK_SENSOR *pSen;
46960- SK_U32 Time;
46961- SK_EVPARA ParaLocal;
46962- int i;
46963-
46964- /* New case: no sensors */
46965- if (pAC->I2c.MaxSens == 0) {
46966- return(0);
46967- }
46968-
46969- switch (Event) {
46970- case SK_I2CEV_IRQ:
46971- pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
46972- ReadComplete = SkI2cReadSensor(pAC, IoC, pSen);
46973-
46974- if (ReadComplete) {
46975- /* Check sensor against defined thresholds */
46976- SkI2cCheckSensor(pAC, pSen);
46977-
46978- /* Increment Current sensor and set appropriate Timeout */
46979- pAC->I2c.CurrSens++;
46980- if (pAC->I2c.CurrSens >= pAC->I2c.MaxSens) {
46981- pAC->I2c.CurrSens = 0;
46982- Time = SK_I2C_TIM_LONG;
46983- }
46984- else {
46985- Time = SK_I2C_TIM_SHORT;
46986- }
46987-
46988- /* Start Timer */
46989- ParaLocal.Para64 = (SK_U64)0;
46990-
46991- pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING;
46992-
46993- SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time,
46994- SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
46995- }
46996- else {
46997- /* Start Timer */
46998- ParaLocal.Para64 = (SK_U64)0;
46999-
47000- pAC->I2c.TimerMode = SK_TIMER_WATCH_SM;
47001-
47002- SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, SK_I2C_TIM_WATCH,
47003- SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
47004- }
47005- break;
47006- case SK_I2CEV_TIM:
47007- if (pAC->I2c.TimerMode == SK_TIMER_NEW_GAUGING) {
47008-
47009- ParaLocal.Para64 = (SK_U64)0;
47010- SkTimerStop(pAC, IoC, &pAC->I2c.SenTimer);
47011-
47012- pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
47013- ReadComplete = SkI2cReadSensor(pAC, IoC, pSen);
47014-
47015- if (ReadComplete) {
47016- /* Check sensor against defined thresholds */
47017- SkI2cCheckSensor(pAC, pSen);
47018-
47019- /* Increment Current sensor and set appropriate Timeout */
47020- pAC->I2c.CurrSens++;
47021- if (pAC->I2c.CurrSens == pAC->I2c.MaxSens) {
47022- pAC->I2c.CurrSens = 0;
47023- Time = SK_I2C_TIM_LONG;
47024- }
47025- else {
47026- Time = SK_I2C_TIM_SHORT;
47027- }
47028-
47029- /* Start Timer */
47030- ParaLocal.Para64 = (SK_U64)0;
47031-
47032- pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING;
47033-
47034- SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time,
47035- SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
47036- }
47037- }
47038- else {
47039- pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
47040- pSen->SenErrFlag = SK_SEN_ERR_FAULTY;
47041- SK_I2C_STOP(IoC);
47042-
47043- /* Increment Current sensor and set appropriate Timeout */
47044- pAC->I2c.CurrSens++;
47045- if (pAC->I2c.CurrSens == pAC->I2c.MaxSens) {
47046- pAC->I2c.CurrSens = 0;
47047- Time = SK_I2C_TIM_LONG;
47048- }
47049- else {
47050- Time = SK_I2C_TIM_SHORT;
47051- }
47052-
47053- /* Start Timer */
47054- ParaLocal.Para64 = (SK_U64)0;
47055-
47056- pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING;
47057-
47058- SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time,
47059- SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
47060- }
47061- break;
47062- case SK_I2CEV_CLEAR:
47063- for (i = 0; i < SK_MAX_SENSORS; i++) {
47064- pAC->I2c.SenTable[i].SenErrFlag = SK_SEN_ERR_OK;
47065- pAC->I2c.SenTable[i].SenErrCts = 0;
47066- pAC->I2c.SenTable[i].SenWarnCts = 0;
47067- pAC->I2c.SenTable[i].SenBegErrTS = 0;
47068- pAC->I2c.SenTable[i].SenBegWarnTS = 0;
47069- pAC->I2c.SenTable[i].SenLastErrTrapTS = (SK_U64)0;
47070- pAC->I2c.SenTable[i].SenLastErrLogTS = (SK_U64)0;
47071- pAC->I2c.SenTable[i].SenLastWarnTrapTS = (SK_U64)0;
47072- pAC->I2c.SenTable[i].SenLastWarnLogTS = (SK_U64)0;
47073- }
47074- break;
47075- default:
47076- SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E006, SKERR_I2C_E006MSG);
47077- }
47078-
47079- return(0);
47080-} /* SkI2cEvent*/
47081-
47082-#endif /* !SK_DIAG */
47083diff -ruN linux/drivers/net/sk98lin/sklm80.c linux-new/drivers/net/sk98lin/sklm80.c
47084--- linux/drivers/net/sk98lin/sklm80.c 2006-04-11 19:19:28.000000000 +0200
47085+++ linux-new/drivers/net/sk98lin/sklm80.c 2006-01-18 14:37:24.000000000 +0100
47086@@ -2,8 +2,8 @@
47087 *
47088 * Name: sklm80.c
47089 * Project: Gigabit Ethernet Adapters, TWSI-Module
47090- * Version: $Revision$
47091- * Date: $Date$
47092+ * Version: $Revision$
47093+ * Date: $Date$
47094 * Purpose: Functions to access Voltage and Temperature Sensor (LM80)
47095 *
47096 ******************************************************************************/
47097@@ -27,7 +27,7 @@
47098 */
47099 #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
47100 static const char SysKonnectFileId[] =
47101- "@(#) $Id$ (C) Marvell. ";
47102+ "@(#) $Id$ (C) Marvell. ";
47103 #endif
47104
47105 #include "h/skdrv1st.h" /* Driver Specific Definitions */
47106@@ -111,12 +111,12 @@
47107 /*
47108 * read a sensors value (LM80 specific)
47109 *
47110- * This function reads a sensors value from the I2C sensor chip LM80.
47111+ * This function reads a sensors value from the TWSI sensor chip LM80.
47112 * The sensor is defined by its index into the sensors database in the struct
47113 * pAC points to.
47114 *
47115 * Returns 1 if the read is completed
47116- * 0 if the read must be continued (I2C Bus still allocated)
47117+ * 0 if the read must be continued (TWSI Bus still allocated)
47118 */
47119 int SkLm80ReadSensor(
47120 SK_AC *pAC, /* Adapter Context */
47121diff -ruN linux/drivers/net/sk98lin/skproc.c linux-new/drivers/net/sk98lin/skproc.c
47122--- linux/drivers/net/sk98lin/skproc.c 1970-01-01 01:00:00.000000000 +0100
47123+++ linux-new/drivers/net/sk98lin/skproc.c 2006-01-18 14:37:24.000000000 +0100
47124@@ -0,0 +1,477 @@
47125+/******************************************************************************
47126+ *
47127+ * Name: skproc.c
47128+ * Project: GEnesis, PCI Gigabit Ethernet Adapter
47129+ * Version: $Revision$
47130+ * Date: $Date$
47131+ * Purpose: Functions to display statictic data
47132+ *
47133+ ******************************************************************************/
47134+
47135+/******************************************************************************
47136+ *
47137+ * (C)Copyright 1998-2002 SysKonnect GmbH.
47138+ * (C)Copyright 2002-2005 Marvell.
47139+ *
47140+ * Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet
47141+ * Server Adapters.
47142+ *
47143+ * Author: Ralph Roesler (rroesler@syskonnect.de)
47144+ * Mirko Lindner (mlindner@syskonnect.de)
47145+ *
47146+ * Address all question to: linux@syskonnect.de
47147+ *
47148+ * This program is free software; you can redistribute it and/or modify
47149+ * it under the terms of the GNU General Public License as published by
47150+ * the Free Software Foundation; either version 2 of the License, or
47151+ * (at your option) any later version.
47152+ *
47153+ * The information in this file is provided "AS IS" without warranty.
47154+ *
47155+ *****************************************************************************/
47156+
47157+#include <linux/proc_fs.h>
47158+#include <linux/seq_file.h>
47159+
47160+#include "h/skdrv1st.h"
47161+#include "h/skdrv2nd.h"
47162+#include "h/skversion.h"
47163+
47164+extern struct SK_NET_DEVICE *SkGeRootDev;
47165+
47166+/******************************************************************************
47167+ *
47168+ * Local Function Prototypes and Local Variables
47169+ *
47170+ *****************************************************************************/
47171+
47172+static int sk_proc_print(void *writePtr, char *format, ...);
47173+static void sk_gen_browse(void *buffer);
47174+static int len;
47175+
47176+static int sk_seq_show(struct seq_file *seq, void *v);
47177+static int sk_proc_open(struct inode *inode, struct file *file);
47178+struct file_operations sk_proc_fops = {
47179+ .owner = THIS_MODULE,
47180+ .open = sk_proc_open,
47181+ .read = seq_read,
47182+ .llseek = seq_lseek,
47183+ .release = single_release,
47184+};
47185+struct net_device *currDev = NULL;
47186+
47187+/*****************************************************************************
47188+ *
47189+ * sk_gen_browse -generic print "summaries" entry
47190+ *
47191+ * Description:
47192+ * This function fills the proc entry with statistic data about
47193+ * the ethernet device.
47194+ *
47195+ * Returns: N/A
47196+ *
47197+ */
47198+static void sk_gen_browse(
47199+void *buffer) /* buffer where the statistics will be stored in */
47200+{
47201+ struct SK_NET_DEVICE *SkgeProcDev = SkGeRootDev;
47202+ struct SK_NET_DEVICE *next;
47203+ SK_BOOL DisableStatistic = 0;
47204+ SK_PNMI_STRUCT_DATA *pPnmiStruct;
47205+ SK_PNMI_STAT *pPnmiStat;
47206+ unsigned long Flags;
47207+ unsigned int Size;
47208+ DEV_NET *pNet;
47209+ SK_AC *pAC;
47210+ char sens_msg[50];
47211+ int card_type;
47212+ int MaxSecurityCount = 0;
47213+ int t;
47214+ int i;
47215+
47216+ while (SkgeProcDev) {
47217+ MaxSecurityCount++;
47218+ if (MaxSecurityCount > 100) {
47219+ printk("Max limit for sk_proc_read security counter!\n");
47220+ return;
47221+ }
47222+ pNet = (DEV_NET*) SkgeProcDev->priv;
47223+ pAC = pNet->pAC;
47224+ next = pAC->Next;
47225+ pPnmiStruct = &pAC->PnmiStruct;
47226+ /* NetIndex in GetStruct is now required, zero is only dummy */
47227+
47228+ for (t=pAC->GIni.GIMacsFound; t > 0; t--) {
47229+ if ((pAC->GIni.GIMacsFound == 2) && pAC->RlmtNets == 1)
47230+ t--;
47231+
47232+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
47233+ Size = SK_PNMI_STRUCT_SIZE;
47234+ DisableStatistic = 0;
47235+ if (pAC->BoardLevel == SK_INIT_DATA) {
47236+ SK_MEMCPY(&(pAC->PnmiStruct), &(pAC->PnmiBackup), sizeof(SK_PNMI_STRUCT_DATA));
47237+ if (pAC->DiagModeActive == DIAG_NOTACTIVE) {
47238+ pAC->Pnmi.DiagAttached = SK_DIAG_IDLE;
47239+ }
47240+ } else {
47241+ SkPnmiGetStruct(pAC, pAC->IoBase, pPnmiStruct, &Size, t-1);
47242+ }
47243+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
47244+ if (strcmp(pAC->dev[t-1]->name, currDev->name) == 0) {
47245+ if (!pAC->GIni.GIYukon32Bit)
47246+ card_type = 64;
47247+ else
47248+ card_type = 32;
47249+
47250+ pPnmiStat = &pPnmiStruct->Stat[0];
47251+ len = sk_proc_print(buffer,
47252+ "\nDetailed statistic for device %s\n",
47253+ pAC->dev[t-1]->name);
47254+ len += sk_proc_print(buffer,
47255+ "=======================================\n");
47256+
47257+ /* Board statistics */
47258+ len += sk_proc_print(buffer,
47259+ "\nBoard statistics\n\n");
47260+ len += sk_proc_print(buffer,
47261+ "Card name %s\n",
47262+ pAC->DeviceStr);
47263+ len += sk_proc_print(buffer,
47264+ "Vendor/Device ID %x/%x\n",
47265+ pAC->PciDev->vendor,
47266+ pAC->PciDev->device);
47267+ len += sk_proc_print(buffer,
47268+ "Card type (Bit) %d\n",
47269+ card_type);
47270+
47271+ len += sk_proc_print(buffer,
47272+ "Active Port %c\n",
47273+ 'A' + pAC->Rlmt.Net[t-1].Port[pAC->Rlmt.
47274+ Net[t-1].PrefPort]->PortNumber);
47275+ len += sk_proc_print(buffer,
47276+ "Preferred Port %c\n",
47277+ 'A' + pAC->Rlmt.Net[t-1].Port[pAC->Rlmt.
47278+ Net[t-1].PrefPort]->PortNumber);
47279+
47280+ if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_STATIC) {
47281+ len += sk_proc_print(buffer,
47282+ "Interrupt Moderation static (%d ints/sec)\n",
47283+ pAC->DynIrqModInfo.MaxModIntsPerSec);
47284+ } else if (pAC->DynIrqModInfo.IntModTypeSelect == C_INT_MOD_DYNAMIC) {
47285+ len += sk_proc_print(buffer,
47286+ "Interrupt Moderation dynamic (%d ints/sec)\n",
47287+ pAC->DynIrqModInfo.MaxModIntsPerSec);
47288+ } else {
47289+ len += sk_proc_print(buffer,
47290+ "Interrupt Moderation disabled\n");
47291+ }
47292+
47293+ if (pAC->GIni.GIPciBus == SK_PEX_BUS) {
47294+ len += sk_proc_print(buffer,
47295+ "Bus type PCI-Express\n");
47296+ len += sk_proc_print(buffer,
47297+ "Bus width (Lanes) %d\n",
47298+ pAC->GIni.GIPexWidth);
47299+ } else {
47300+ if (pAC->GIni.GIPciBus == SK_PCIX_BUS) {
47301+ len += sk_proc_print(buffer,
47302+ "Bus type PCI-X\n");
47303+ if (pAC->GIni.GIPciMode == PCI_OS_SPD_X133) {
47304+ len += sk_proc_print(buffer,
47305+ "Bus speed (MHz) 133\n");
47306+ } else if (pAC->GIni.GIPciMode == PCI_OS_SPD_X100) {
47307+ len += sk_proc_print(buffer,
47308+ "Bus speed (MHz) 100\n");
47309+ } else if (pAC->GIni.GIPciMode == PCI_OS_SPD_X66) {
47310+ len += sk_proc_print(buffer,
47311+ "Bus speed (MHz) 66\n");
47312+ } else {
47313+ len += sk_proc_print(buffer,
47314+ "Bus speed (MHz) 33\n");
47315+ }
47316+ } else {
47317+ len += sk_proc_print(buffer,
47318+ "Bus type PCI\n");
47319+ len += sk_proc_print(buffer,
47320+ "Bus speed (MHz) %d\n",
47321+ pPnmiStruct->BusSpeed);
47322+ }
47323+ len += sk_proc_print(buffer,
47324+ "Bus width (Bit) %d\n",
47325+ pPnmiStruct->BusWidth);
47326+ }
47327+
47328+ len += sk_proc_print(buffer,
47329+ "Driver version %s (%s)\n",
47330+ VER_STRING, PATCHLEVEL);
47331+ len += sk_proc_print(buffer,
47332+ "Driver release date %s\n",
47333+ pAC->Pnmi.pDriverReleaseDate);
47334+ len += sk_proc_print(buffer,
47335+ "Hardware revision v%d.%d\n",
47336+ (pAC->GIni.GIPciHwRev >> 4) & 0x0F,
47337+ pAC->GIni.GIPciHwRev & 0x0F);
47338+
47339+ if (!netif_running(pAC->dev[t-1])) {
47340+ len += sk_proc_print(buffer,
47341+ "\n Device %s is down.\n"
47342+ " Therefore no statistics are available.\n"
47343+ " After bringing the device up (ifconfig)"
47344+ " statistics will\n"
47345+ " be displayed.\n",
47346+ pAC->dev[t-1]->name);
47347+ DisableStatistic = 1;
47348+ }
47349+
47350+ /* Display only if statistic info available */
47351+ /* Print sensor informations */
47352+ if (!DisableStatistic) {
47353+ for (i=0; i < pAC->I2c.MaxSens; i ++) {
47354+ /* Check type */
47355+ switch (pAC->I2c.SenTable[i].SenType) {
47356+ case 1:
47357+ strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc);
47358+ strcat(sens_msg, " (C)");
47359+ len += sk_proc_print(buffer,
47360+ "%-25s %d.%02d\n",
47361+ sens_msg,
47362+ pAC->I2c.SenTable[i].SenValue / 10,
47363+ pAC->I2c.SenTable[i].SenValue %
47364+ 10);
47365+
47366+ strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc);
47367+ strcat(sens_msg, " (F)");
47368+ len += sk_proc_print(buffer,
47369+ "%-25s %d.%02d\n",
47370+ sens_msg,
47371+ ((((pAC->I2c.SenTable[i].SenValue)
47372+ *10)*9)/5 + 3200)/100,
47373+ ((((pAC->I2c.SenTable[i].SenValue)
47374+ *10)*9)/5 + 3200) % 10);
47375+ break;
47376+ case 2:
47377+ strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc);
47378+ strcat(sens_msg, " (V)");
47379+ len += sk_proc_print(buffer,
47380+ "%-25s %d.%03d\n",
47381+ sens_msg,
47382+ pAC->I2c.SenTable[i].SenValue / 1000,
47383+ pAC->I2c.SenTable[i].SenValue % 1000);
47384+ break;
47385+ case 3:
47386+ strcpy(sens_msg, pAC->I2c.SenTable[i].SenDesc);
47387+ strcat(sens_msg, " (rpm)");
47388+ len += sk_proc_print(buffer,
47389+ "%-25s %d\n",
47390+ sens_msg,
47391+ pAC->I2c.SenTable[i].SenValue);
47392+ break;
47393+ default:
47394+ break;
47395+ }
47396+ }
47397+
47398+ /*Receive statistics */
47399+ len += sk_proc_print(buffer,
47400+ "\nReceive statistics\n\n");
47401+
47402+ len += sk_proc_print(buffer,
47403+ "Received bytes %Lu\n",
47404+ (unsigned long long) pPnmiStat->StatRxOctetsOkCts);
47405+ len += sk_proc_print(buffer,
47406+ "Received packets %Lu\n",
47407+ (unsigned long long) pPnmiStat->StatRxOkCts);
47408+#if 0
47409+ if (pAC->GIni.GP[0].PhyType == SK_PHY_XMAC &&
47410+ pAC->HWRevision < 12) {
47411+ pPnmiStruct->InErrorsCts = pPnmiStruct->InErrorsCts -
47412+ pPnmiStat->StatRxShortsCts;
47413+ pPnmiStat->StatRxShortsCts = 0;
47414+ }
47415+#endif
47416+ if (pAC->dev[t-1]->mtu > 1500)
47417+ pPnmiStruct->InErrorsCts = pPnmiStruct->InErrorsCts -
47418+ pPnmiStat->StatRxTooLongCts;
47419+
47420+ len += sk_proc_print(buffer,
47421+ "Receive errors %Lu\n",
47422+ (unsigned long long) pPnmiStruct->InErrorsCts);
47423+ len += sk_proc_print(buffer,
47424+ "Receive dropped %Lu\n",
47425+ (unsigned long long) pPnmiStruct->RxNoBufCts);
47426+ len += sk_proc_print(buffer,
47427+ "Received multicast %Lu\n",
47428+ (unsigned long long) pPnmiStat->StatRxMulticastOkCts);
47429+#ifdef ADVANCED_STATISTIC_OUTPUT
47430+ len += sk_proc_print(buffer,
47431+ "Receive error types\n");
47432+ len += sk_proc_print(buffer,
47433+ " length %Lu\n",
47434+ (unsigned long long) pPnmiStat->StatRxRuntCts);
47435+ len += sk_proc_print(buffer,
47436+ " buffer overflow %Lu\n",
47437+ (unsigned long long) pPnmiStat->StatRxFifoOverflowCts);
47438+ len += sk_proc_print(buffer,
47439+ " bad crc %Lu\n",
47440+ (unsigned long long) pPnmiStat->StatRxFcsCts);
47441+ len += sk_proc_print(buffer,
47442+ " framing %Lu\n",
47443+ (unsigned long long) pPnmiStat->StatRxFramingCts);
47444+ len += sk_proc_print(buffer,
47445+ " missed frames %Lu\n",
47446+ (unsigned long long) pPnmiStat->StatRxMissedCts);
47447+
47448+ if (pAC->dev[t-1]->mtu > 1500)
47449+ pPnmiStat->StatRxTooLongCts = 0;
47450+
47451+ len += sk_proc_print(buffer,
47452+ " too long %Lu\n",
47453+ (unsigned long long) pPnmiStat->StatRxTooLongCts);
47454+ len += sk_proc_print(buffer,
47455+ " carrier extension %Lu\n",
47456+ (unsigned long long) pPnmiStat->StatRxCextCts);
47457+ len += sk_proc_print(buffer,
47458+ " too short %Lu\n",
47459+ (unsigned long long) pPnmiStat->StatRxShortsCts);
47460+ len += sk_proc_print(buffer,
47461+ " symbol %Lu\n",
47462+ (unsigned long long) pPnmiStat->StatRxSymbolCts);
47463+ len += sk_proc_print(buffer,
47464+ " LLC MAC size %Lu\n",
47465+ (unsigned long long) pPnmiStat->StatRxIRLengthCts);
47466+ len += sk_proc_print(buffer,
47467+ " carrier event %Lu\n",
47468+ (unsigned long long) pPnmiStat->StatRxCarrierCts);
47469+ len += sk_proc_print(buffer,
47470+ " jabber %Lu\n",
47471+ (unsigned long long) pPnmiStat->StatRxJabberCts);
47472+#endif
47473+
47474+ /*Transmit statistics */
47475+ len += sk_proc_print(buffer,
47476+ "\nTransmit statistics\n\n");
47477+
47478+ len += sk_proc_print(buffer,
47479+ "Transmitted bytes %Lu\n",
47480+ (unsigned long long) pPnmiStat->StatTxOctetsOkCts);
47481+ len += sk_proc_print(buffer,
47482+ "Transmitted packets %Lu\n",
47483+ (unsigned long long) pPnmiStat->StatTxOkCts);
47484+ len += sk_proc_print(buffer,
47485+ "Transmit errors %Lu\n",
47486+ (unsigned long long) pPnmiStat->StatTxSingleCollisionCts);
47487+ len += sk_proc_print(buffer,
47488+ "Transmit dropped %Lu\n",
47489+ (unsigned long long) pPnmiStruct->TxNoBufCts);
47490+ len += sk_proc_print(buffer,
47491+ "Transmit collisions %Lu\n",
47492+ (unsigned long long) pPnmiStat->StatTxSingleCollisionCts);
47493+#ifdef ADVANCED_STATISTIC_OUTPUT
47494+ len += sk_proc_print(buffer,
47495+ "Transmit error types\n");
47496+ len += sk_proc_print(buffer,
47497+ " excessive collision %ld\n",
47498+ pAC->stats.tx_aborted_errors);
47499+ len += sk_proc_print(buffer,
47500+ " carrier %Lu\n",
47501+ (unsigned long long) pPnmiStat->StatTxCarrierCts);
47502+ len += sk_proc_print(buffer,
47503+ " fifo underrun %Lu\n",
47504+ (unsigned long long) pPnmiStat->StatTxFifoUnderrunCts);
47505+ len += sk_proc_print(buffer,
47506+ " heartbeat %Lu\n",
47507+ (unsigned long long) pPnmiStat->StatTxCarrierCts);
47508+ len += sk_proc_print(buffer,
47509+ " window %ld\n",
47510+ pAC->stats.tx_window_errors);
47511+#endif
47512+ } /* if (!DisableStatistic) */
47513+
47514+ } /* if (strcmp(pACname, currDeviceName) == 0) */
47515+ }
47516+ SkgeProcDev = next;
47517+ }
47518+}
47519+
47520+/*****************************************************************************
47521+ *
47522+ * sk_proc_print - generic line print
47523+ *
47524+ * Description:
47525+ * This function fills the proc entry with statistic data about the
47526+ * ethernet device.
47527+ *
47528+ * Returns:
47529+ * the number of bytes written
47530+ *
47531+ */
47532+static int sk_proc_print(
47533+void *writePtr, /* the buffer pointer */
47534+char *format, /* the format of the string */
47535+...) /* variable list of arguments */
47536+{
47537+#define MAX_LEN_SINGLE_LINE 256
47538+ char str[MAX_LEN_SINGLE_LINE];
47539+ va_list a_start;
47540+ int lenght = 0;
47541+
47542+ struct seq_file *seq = (struct seq_file *) writePtr;
47543+
47544+ SK_MEMSET(str, 0, MAX_LEN_SINGLE_LINE);
47545+
47546+ va_start(a_start, format);
47547+ vsprintf(str, format, a_start);
47548+ va_end(a_start);
47549+
47550+ lenght = strlen(str);
47551+
47552+ seq_printf(seq, str);
47553+ return lenght;
47554+}
47555+
47556+/*****************************************************************************
47557+ *
47558+ * sk_seq_show - show proc information of a particular adapter
47559+ *
47560+ * Description:
47561+ * This function fills the proc entry with statistic data about the
47562+ * ethernet device. It invokes the generic sk_gen_browse() to print
47563+ * out all items one per one.
47564+ *
47565+ * Returns:
47566+ * the number of bytes written
47567+ *
47568+ */
47569+static int sk_seq_show(
47570+struct seq_file *seq, /* the sequence pointer */
47571+void *v) /* additional pointer */
47572+{
47573+ void *castedBuffer = (void *) seq;
47574+ currDev = seq->private;
47575+ sk_gen_browse(castedBuffer);
47576+ return 0;
47577+}
47578+
47579+/*****************************************************************************
47580+ *
47581+ * sk_proc_open - register the show function when proc is open'ed
47582+ *
47583+ * Description:
47584+ * This function is called whenever a sk98lin proc file is queried.
47585+ *
47586+ * Returns:
47587+ * the return value of single_open()
47588+ *
47589+ */
47590+static int sk_proc_open(
47591+struct inode *inode, /* the inode of the file */
47592+struct file *file) /* the file pointer itself */
47593+{
47594+ return single_open(file, sk_seq_show, PDE(inode)->data);
47595+}
47596+
47597+/*******************************************************************************
47598+ *
47599+ * End of file
47600+ *
47601+ ******************************************************************************/
47602diff -ruN linux/drivers/net/sk98lin/skqueue.c linux-new/drivers/net/sk98lin/skqueue.c
47603--- linux/drivers/net/sk98lin/skqueue.c 2006-04-11 19:19:28.000000000 +0200
47604+++ linux-new/drivers/net/sk98lin/skqueue.c 2006-01-18 14:37:24.000000000 +0100
47605@@ -2,8 +2,8 @@
47606 *
47607 * Name: skqueue.c
47608 * Project: Gigabit Ethernet Adapters, Event Scheduler Module
47609- * Version: $Revision$
47610- * Date: $Date$
47611+ * Version: $Revision$
47612+ * Date: $Date$
47613 * Purpose: Management of an event queue.
47614 *
47615 ******************************************************************************/
47616@@ -28,7 +28,7 @@
47617 */
47618 #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
47619 static const char SysKonnectFileId[] =
47620- "@(#) $Id$ (C) Marvell.";
47621+ "@(#) $Id$ (C) Marvell.";
47622 #endif
47623
47624 #include "h/skdrv1st.h" /* Driver Specific Definitions */
47625@@ -48,10 +48,16 @@
47626
47627 #define PRINTF(a,b,c)
47628
47629-/*
47630- * init event queue management
47631+/******************************************************************************
47632+ *
47633+ * SkEventInit() - init event queue management
47634 *
47635- * Must be called during init level 0.
47636+ * Description:
47637+ * This function initializes event queue management.
47638+ * It must be called during init level 0.
47639+ *
47640+ * Returns:
47641+ * nothing
47642 */
47643 void SkEventInit(
47644 SK_AC *pAC, /* Adapter context */
47645@@ -67,8 +73,17 @@
47646 }
47647 }
47648
47649-/*
47650- * add event to queue
47651+/******************************************************************************
47652+ *
47653+ * SkEventQueue() - add event to queue
47654+ *
47655+ * Description:
47656+ * This function adds an event to the event queue.
47657+ * At least Init Level 1 is required to queue events,
47658+ * but will be scheduled add Init Level 2.
47659+ *
47660+ * returns:
47661+ * nothing
47662 */
47663 void SkEventQueue(
47664 SK_AC *pAC, /* Adapters context */
47665@@ -76,26 +91,45 @@
47666 SK_U32 Event, /* Event to be queued */
47667 SK_EVPARA Para) /* Event parameter */
47668 {
47669- pAC->Event.EvPut->Class = Class;
47670- pAC->Event.EvPut->Event = Event;
47671- pAC->Event.EvPut->Para = Para;
47672+
47673+ if (pAC->GIni.GILevel == SK_INIT_DATA) {
47674+ SK_ERR_LOG(pAC, SK_ERRCL_NORES, SKERR_Q_E003, SKERR_Q_E003MSG);
47675+ }
47676+ else {
47677+ pAC->Event.EvPut->Class = Class;
47678+ pAC->Event.EvPut->Event = Event;
47679+ pAC->Event.EvPut->Para = Para;
47680
47681- if (++pAC->Event.EvPut == &pAC->Event.EvQueue[SK_MAX_EVENT])
47682- pAC->Event.EvPut = pAC->Event.EvQueue;
47683+ if (++pAC->Event.EvPut == &pAC->Event.EvQueue[SK_MAX_EVENT])
47684+ pAC->Event.EvPut = pAC->Event.EvQueue;
47685
47686- if (pAC->Event.EvPut == pAC->Event.EvGet) {
47687- SK_ERR_LOG(pAC, SK_ERRCL_NORES, SKERR_Q_E001, SKERR_Q_E001MSG);
47688+ if (pAC->Event.EvPut == pAC->Event.EvGet) {
47689+ SK_ERR_LOG(pAC, SK_ERRCL_NORES, SKERR_Q_E001, SKERR_Q_E001MSG);
47690+ }
47691 }
47692 }
47693
47694-/*
47695- * event dispatcher
47696- * while event queue is not empty
47697- * get event from queue
47698- * send command to state machine
47699- * end
47700- * return error reported by individual Event function
47701- * 0 if no error occured.
47702+/******************************************************************************
47703+ *
47704+ * SkEventDispatcher() - Event Dispatcher
47705+ *
47706+ * Description:
47707+ * The event dispatcher performs the following operations:
47708+ * o while event queue is not empty
47709+ * - get event from queue
47710+ * - send event to state machine
47711+ * end
47712+ *
47713+ * CAUTION:
47714+ * The event functions MUST report an error if performing a reinitialization
47715+ * of the event queue, e.g. performing level Init 0..2 while in dispatcher
47716+ * call!
47717+ * ANY OTHER return value delays scheduling the other events in the
47718+ * queue. In this case the event blocks the queue until
47719+ * the error condition is cleared!
47720+ *
47721+ * Returns:
47722+ * The return value error reported by individual event function
47723 */
47724 int SkEventDispatcher(
47725 SK_AC *pAC, /* Adapters Context */
47726@@ -105,6 +139,10 @@
47727 SK_U32 Class;
47728 int Rtv;
47729
47730+ if (pAC->GIni.GILevel != SK_INIT_RUN) {
47731+ SK_ERR_LOG(pAC, SK_ERRCL_NORES, SKERR_Q_E005, SKERR_Q_E005MSG);
47732+ }
47733+
47734 pEv = pAC->Event.EvGet;
47735
47736 PRINTF("dispatch get %x put %x\n", pEv, pAC->Event.ev_put);
47737@@ -152,6 +190,11 @@
47738 Rtv = SkFdEvent(pAC, Ioc, pEv->Event, pEv->Para);
47739 break;
47740 #endif /* SK_USE_LAC_EV */
47741+#ifdef SK_ASF
47742+ case SKGE_ASF :
47743+ Rtv = SkAsfEvent(pAC,Ioc,pEv->Event,pEv->Para);
47744+ break ;
47745+#endif
47746 #ifdef SK_USE_CSUM
47747 case SKGE_CSUM :
47748 Rtv = SkCsEvent(pAC, Ioc, pEv->Event, pEv->Para);
47749@@ -163,6 +206,20 @@
47750 }
47751
47752 if (Rtv != 0) {
47753+ /*
47754+ * Special Case: See CAUTION statement above.
47755+ * We assume the event queue is reset.
47756+ */
47757+ if (pAC->Event.EvGet != pAC->Event.EvQueue &&
47758+ pAC->Event.EvGet != pEv) {
47759+ /*
47760+ * Create an error log entry if the
47761+ * event queue isn't reset.
47762+ * In this case it may be blocked.
47763+ */
47764+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_Q_E004, SKERR_Q_E004MSG);
47765+ }
47766+
47767 return(Rtv);
47768 }
47769
47770diff -ruN linux/drivers/net/sk98lin/skrlmt.c linux-new/drivers/net/sk98lin/skrlmt.c
47771--- linux/drivers/net/sk98lin/skrlmt.c 2006-04-11 19:19:28.000000000 +0200
47772+++ linux-new/drivers/net/sk98lin/skrlmt.c 2006-01-18 14:37:24.000000000 +0100
47773@@ -2,8 +2,8 @@
47774 *
47775 * Name: skrlmt.c
47776 * Project: GEnesis, PCI Gigabit Ethernet Adapter
47777- * Version: $Revision$
47778- * Date: $Date$
47779+ * Version: $Revision$
47780+ * Date: $Date$
47781 * Purpose: Manage links on SK-NET Adapters, esp. redundant ones.
47782 *
47783 ******************************************************************************/
47784@@ -39,7 +39,7 @@
47785
47786 #ifndef lint
47787 static const char SysKonnectFileId[] =
47788- "@(#) $Id$ (C) Marvell.";
47789+ "@(#) $Id$ (C) Marvell.";
47790 #endif /* !defined(lint) */
47791
47792 #define __SKRLMT_C
47793@@ -350,7 +350,7 @@
47794 SK_BOOL PhysicalAMacAddressSet;
47795
47796 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_INIT,
47797- ("RLMT Init level %d.\n", Level))
47798+ ("RLMT Init level %d.\n", Level));
47799
47800 switch (Level) {
47801 case SK_INIT_DATA: /* Initialize data structures. */
47802@@ -390,7 +390,7 @@
47803
47804 case SK_INIT_IO: /* GIMacsFound first available here. */
47805 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_INIT,
47806- ("RLMT: %d MACs were detected.\n", pAC->GIni.GIMacsFound))
47807+ ("RLMT: %d MACs were detected.\n", pAC->GIni.GIMacsFound));
47808
47809 pAC->Rlmt.Net[0].NumPorts = pAC->GIni.GIMacsFound;
47810
47811@@ -512,7 +512,7 @@
47812 }
47813
47814 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
47815- ("SkRlmtBuildCheckChain.\n"))
47816+ ("SkRlmtBuildCheckChain.\n"));
47817
47818 NumMacsUp = 0;
47819
47820@@ -558,7 +558,7 @@
47821 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
47822 ("Port %d checks %d other ports: %2X.\n", i,
47823 pAC->Rlmt.Net[NetIdx].Port[i]->PortsChecked,
47824- pAC->Rlmt.Net[NetIdx].Port[i]->PortCheck[0].CheckAddr.a[5]))
47825+ pAC->Rlmt.Net[NetIdx].Port[i]->PortCheck[0].CheckAddr.a[5]));
47826 }
47827 #endif /* DEBUG */
47828
47829@@ -604,7 +604,7 @@
47830 if ((CheckSrc == 0) || (CheckDest == 0)) {
47831 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_ERR,
47832 ("SkRlmtBuildPacket: Invalid %s%saddr.\n",
47833- (CheckSrc == 0 ? "Src" : ""), (CheckDest == 0 ? "Dest" : "")))
47834+ (CheckSrc == 0 ? "Src" : ""), (CheckDest == 0 ? "Dest" : "")));
47835 }
47836 #endif
47837
47838@@ -796,7 +796,7 @@
47839
47840 SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para);
47841 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_TX,
47842- ("SkRlmtSend: BPDU Packet on Port %u.\n", PortNumber))
47843+ ("SkRlmtSend: BPDU Packet on Port %u.\n", PortNumber));
47844 }
47845 }
47846 return;
47847@@ -835,7 +835,7 @@
47848 * Bring it up.
47849 */
47850 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
47851- ("SkRlmtPacketReceive: Received on PortDown.\n"))
47852+ ("SkRlmtPacketReceive: Received on PortDown.\n"));
47853
47854 pRPort->PortState = SK_RLMT_PS_GOING_UP;
47855 pRPort->GuTimeStamp = SkOsGetTime(pAC);
47856@@ -849,7 +849,7 @@
47857 } /* PortDown && !SuspectTx */
47858 else if (pRPort->CheckingState & SK_RLMT_PCS_RX) {
47859 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
47860- ("SkRlmtPacketReceive: Stop bringing port down.\n"))
47861+ ("SkRlmtPacketReceive: Stop bringing port down.\n"));
47862 SkTimerStop(pAC, IoC, &pRPort->DownRxTimer);
47863 pRPort->CheckingState &= ~SK_RLMT_PCS_RX;
47864 /* pAC->Rlmt.CheckSwitch = SK_TRUE; */
47865@@ -896,7 +896,7 @@
47866 pRPort = &pAC->Rlmt.Port[PortNumber];
47867
47868 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
47869- ("SkRlmtPacketReceive: PortNumber == %d.\n", PortNumber))
47870+ ("SkRlmtPacketReceive: PortNumber == %d.\n", PortNumber));
47871
47872 pRPacket = (SK_RLMT_PACKET*)pMb->pData;
47873 pSPacket = (SK_SPTREE_PACKET*)pRPacket;
47874@@ -917,7 +917,7 @@
47875
47876 /* Not sent to current MAC or registered MC address => Trash it. */
47877 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
47878- ("SkRlmtPacketReceive: Not for me.\n"))
47879+ ("SkRlmtPacketReceive: Not for me.\n"));
47880
47881 SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
47882 return;
47883@@ -955,7 +955,7 @@
47884 pRPacket->Indicator[5] == SK_RLMT_INDICATOR5 &&
47885 pRPacket->Indicator[6] == SK_RLMT_INDICATOR6) {
47886 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
47887- ("SkRlmtPacketReceive: Duplicate MAC Address.\n"))
47888+ ("SkRlmtPacketReceive: Duplicate MAC Address.\n"));
47889
47890 /* Error Log entry. */
47891 SK_ERR_LOG(pAC, SK_ERRCL_COMM, SKERR_RLMT_E006, SKERR_RLMT_E006_MSG);
47892@@ -963,7 +963,7 @@
47893 else {
47894 /* Simply trash it. */
47895 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
47896- ("SkRlmtPacketReceive: Sent by me.\n"))
47897+ ("SkRlmtPacketReceive: Sent by me.\n"));
47898 }
47899
47900 SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
47901@@ -1007,7 +1007,7 @@
47902 #endif /* 0 */
47903
47904 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
47905- ("SkRlmtPacketReceive: Announce.\n"))
47906+ ("SkRlmtPacketReceive: Announce.\n"));
47907
47908 SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
47909 break;
47910@@ -1015,7 +1015,7 @@
47911 case SK_PACKET_ALIVE:
47912 if (pRPacket->SSap & LLC_COMMAND_RESPONSE_BIT) {
47913 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
47914- ("SkRlmtPacketReceive: Alive Reply.\n"))
47915+ ("SkRlmtPacketReceive: Alive Reply.\n"));
47916
47917 if (!(pAC->Addr.Port[PortNumber].PromMode & SK_PROM_MODE_LLC) ||
47918 SK_ADDR_EQUAL(
47919@@ -1046,7 +1046,7 @@
47920 }
47921 else { /* Alive Request Packet. */
47922 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
47923- ("SkRlmtPacketReceive: Alive Request.\n"))
47924+ ("SkRlmtPacketReceive: Alive Request.\n"));
47925
47926 pRPort->RxHelloCts++;
47927
47928@@ -1065,7 +1065,7 @@
47929
47930 case SK_PACKET_CHECK_TX:
47931 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
47932- ("SkRlmtPacketReceive: Check your tx line.\n"))
47933+ ("SkRlmtPacketReceive: Check your tx line.\n"));
47934
47935 /* A port checking us requests us to check our tx line. */
47936 pRPort->CheckingState |= SK_RLMT_PCS_TX;
47937@@ -1088,7 +1088,7 @@
47938
47939 case SK_PACKET_ADDR_CHANGED:
47940 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
47941- ("SkRlmtPacketReceive: Address Change.\n"))
47942+ ("SkRlmtPacketReceive: Address Change.\n"));
47943
47944 /* Build the check chain. */
47945 SkRlmtBuildCheckChain(pAC, pRPort->Net->NetNumber);
47946@@ -1097,7 +1097,7 @@
47947
47948 default:
47949 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
47950- ("SkRlmtPacketReceive: Unknown RLMT packet.\n"))
47951+ ("SkRlmtPacketReceive: Unknown RLMT packet.\n"));
47952
47953 /* RA;:;: ??? */
47954 SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
47955@@ -1107,7 +1107,7 @@
47956 pSPacket->Ctrl == SK_RLMT_SPT_CTRL &&
47957 (pSPacket->SSap & ~LLC_COMMAND_RESPONSE_BIT) == SK_RLMT_SPT_SSAP) {
47958 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
47959- ("SkRlmtPacketReceive: BPDU Packet.\n"))
47960+ ("SkRlmtPacketReceive: BPDU Packet.\n"));
47961
47962 /* Spanning Tree packet. */
47963 pRPort->RxSpHelloCts++;
47964@@ -1139,7 +1139,7 @@
47965 pRPort->Root.Id[0], pRPort->Root.Id[1],
47966 pRPort->Root.Id[2], pRPort->Root.Id[3],
47967 pRPort->Root.Id[4], pRPort->Root.Id[5],
47968- pRPort->Root.Id[6], pRPort->Root.Id[7]))
47969+ pRPort->Root.Id[6], pRPort->Root.Id[7]));
47970 }
47971
47972 SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
47973@@ -1150,7 +1150,7 @@
47974 }
47975 else {
47976 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_RX,
47977- ("SkRlmtPacketReceive: Unknown Packet Type.\n"))
47978+ ("SkRlmtPacketReceive: Unknown Packet Type.\n"));
47979
47980 /* Unknown packet. */
47981 SkDrvFreeRlmtMbuf(pAC, IoC, pMb);
47982@@ -1232,7 +1232,7 @@
47983 if ((pRPort->PacketsPerTimeSlot - pRPort->BpduPacketsPerTimeSlot) == 0) {
47984 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
47985 ("SkRlmtCheckPort %d: No (%d) receives in last time slot.\n",
47986- PortNumber, pRPort->PacketsPerTimeSlot))
47987+ PortNumber, pRPort->PacketsPerTimeSlot));
47988
47989 /*
47990 * Check segmentation if there was no receive at least twice
47991@@ -1249,7 +1249,7 @@
47992
47993 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
47994 ("SkRlmtCheckPort: PortsSuspect %d, PcsRx %d.\n",
47995- pRPort->PortsSuspect, pRPort->CheckingState & SK_RLMT_PCS_RX))
47996+ pRPort->PortsSuspect, pRPort->CheckingState & SK_RLMT_PCS_RX));
47997
47998 if (pRPort->PortState != SK_RLMT_PS_DOWN) {
47999 NewTimeout = TO_SHORTEN(pAC->Rlmt.Port[PortNumber].Net->TimeoutValue);
48000@@ -1295,7 +1295,7 @@
48001 ("SkRlmtCheckPort %d: %d (%d) receives in last time slot.\n",
48002 PortNumber,
48003 pRPort->PacketsPerTimeSlot - pRPort->BpduPacketsPerTimeSlot,
48004- pRPort->PacketsPerTimeSlot))
48005+ pRPort->PacketsPerTimeSlot));
48006
48007 SkRlmtPortReceives(pAC, IoC, PortNumber);
48008 if (pAC->Rlmt.CheckSwitch) {
48009@@ -1345,7 +1345,7 @@
48010 i,
48011 pAC->Rlmt.Port[i].PortDown, pAC->Rlmt.Port[i].PortNoRx,
48012 *((SK_U32*)(&pAC->Rlmt.Port[i].BcTimeStamp) + OFFS_HI32),
48013- *((SK_U32*)(&pAC->Rlmt.Port[i].BcTimeStamp) + OFFS_LO32)))
48014+ *((SK_U32*)(&pAC->Rlmt.Port[i].BcTimeStamp) + OFFS_LO32)));
48015
48016 if (!pAC->Rlmt.Port[i].PortDown && !pAC->Rlmt.Port[i].PortNoRx) {
48017 if (!PortFound || pAC->Rlmt.Port[i].BcTimeStamp > BcTimeStamp) {
48018@@ -1358,7 +1358,7 @@
48019
48020 if (PortFound) {
48021 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48022- ("Port %d received the last broadcast.\n", *pSelect))
48023+ ("Port %d received the last broadcast.\n", *pSelect));
48024
48025 /* Look if another port's time stamp is similar. */
48026 for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) {
48027@@ -1373,7 +1373,7 @@
48028 PortFound = SK_FALSE;
48029
48030 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48031- ("Port %d received a broadcast at a similar time.\n", i))
48032+ ("Port %d received a broadcast at a similar time.\n", i));
48033 break;
48034 }
48035 }
48036@@ -1385,7 +1385,7 @@
48037 ("SK_RLMT_SELECT_BCRX found Port %d receiving the substantially "
48038 "latest broadcast (%u).\n",
48039 *pSelect,
48040- BcTimeStamp - pAC->Rlmt.Port[1 - *pSelect].BcTimeStamp))
48041+ BcTimeStamp - pAC->Rlmt.Port[1 - *pSelect].BcTimeStamp));
48042 }
48043 #endif /* DEBUG */
48044
48045@@ -1434,7 +1434,7 @@
48046 PortFound = SK_TRUE;
48047 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48048 ("SK_RLMT_SELECT_NOTSUSPECT found Port %d up and not check RX.\n",
48049- *pSelect))
48050+ *pSelect));
48051 break;
48052 }
48053 }
48054@@ -1483,7 +1483,7 @@
48055 }
48056 PortFound = SK_TRUE;
48057 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48058- ("SK_RLMT_SELECT_UP found Port %d up.\n", *pSelect))
48059+ ("SK_RLMT_SELECT_UP found Port %d up.\n", *pSelect));
48060 break;
48061 }
48062 }
48063@@ -1544,7 +1544,7 @@
48064 }
48065
48066 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48067- ("SK_RLMT_SELECT_GOINGUP found Port %d going up.\n", *pSelect))
48068+ ("SK_RLMT_SELECT_GOINGUP found Port %d going up.\n", *pSelect));
48069 return (SK_TRUE);
48070 } /* SkRlmtSelectGoingUp */
48071
48072@@ -1590,7 +1590,7 @@
48073 }
48074 PortFound = SK_TRUE;
48075 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48076- ("SK_RLMT_SELECT_DOWN found Port %d down.\n", *pSelect))
48077+ ("SK_RLMT_SELECT_DOWN found Port %d down.\n", *pSelect));
48078 break;
48079 }
48080 }
48081@@ -1680,16 +1680,19 @@
48082 Para.Para32[1] = NetIdx;
48083 SkEventQueue(pAC, SKGE_DRV, SK_DRV_NET_UP, Para);
48084
48085- if ((pAC->Rlmt.Net[NetIdx].RlmtMode & SK_RLMT_TRANSPARENT) == 0 &&
48086- (Para.pParaPtr = SkRlmtBuildPacket(pAC, IoC,
48087- pAC->Rlmt.Net[NetIdx].Port[i]->PortNumber,
48088- SK_PACKET_ANNOUNCE, &pAC->Addr.Net[NetIdx].
48089- CurrentMacAddress, &SkRlmtMcAddr)) != NULL) {
48090- /*
48091- * Send announce packet to RLMT multicast address to force
48092- * switches to learn the new location of the logical MAC address.
48093- */
48094- SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para);
48095+ if (pAC->Rlmt.NumNets == 1) {
48096+ if ((pAC->Rlmt.Net[NetIdx].RlmtMode & SK_RLMT_TRANSPARENT) == 0 &&
48097+ (Para.pParaPtr = SkRlmtBuildPacket(pAC, IoC,
48098+ pAC->Rlmt.Net[NetIdx].Port[i]->PortNumber,
48099+ SK_PACKET_ANNOUNCE, &pAC->Addr.Net[NetIdx].
48100+ CurrentMacAddress, &SkRlmtMcAddr)) != NULL) {
48101+
48102+ /*
48103+ * Send announce packet to RLMT multicast address to force
48104+ * switches to learn the new location of the logical MAC address.
48105+ */
48106+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para);
48107+ }
48108 }
48109 }
48110 else {
48111@@ -1788,7 +1791,7 @@
48112
48113 if (Para.Para32[1] != Active) {
48114 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48115- ("Active: %d, Para1: %d.\n", Active, Para.Para32[1]))
48116+ ("Active: %d, Para1: %d.\n", Active, Para.Para32[1]));
48117 pAC->Rlmt.Net[NetIdx].ActivePort = Para.Para32[1];
48118 Para.Para32[0] = pAC->Rlmt.Net[NetIdx].
48119 Port[Para.Para32[0]]->PortNumber;
48120@@ -1868,7 +1871,7 @@
48121 pNet->Port[i]->Root.Id[0], pNet->Port[i]->Root.Id[1],
48122 pNet->Port[i]->Root.Id[2], pNet->Port[i]->Root.Id[3],
48123 pNet->Port[i]->Root.Id[4], pNet->Port[i]->Root.Id[5],
48124- pNet->Port[i]->Root.Id[6], pNet->Port[i]->Root.Id[7]))
48125+ pNet->Port[i]->Root.Id[6], pNet->Port[i]->Root.Id[7]));
48126
48127 if (!pNet->RootIdSet) {
48128 pNet->Root = pNet->Port[i]->Root;
48129@@ -1963,13 +1966,13 @@
48130 SK_U32 i;
48131
48132 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48133- ("SK_RLMT_PORTSTART_TIMEOUT Port %d Event BEGIN.\n", Para.Para32[0]))
48134+ ("SK_RLMT_PORTSTART_TIMEOUT Port %d Event BEGIN.\n", Para.Para32[0]));
48135
48136 if (Para.Para32[1] != (SK_U32)-1) {
48137 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48138- ("Bad Parameter.\n"))
48139+ ("Bad Parameter.\n"));
48140 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48141- ("SK_RLMT_PORTSTART_TIMEOUT Event EMPTY.\n"))
48142+ ("SK_RLMT_PORTSTART_TIMEOUT Event EMPTY.\n"));
48143 return;
48144 }
48145
48146@@ -1990,7 +1993,7 @@
48147 }
48148
48149 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48150- ("SK_RLMT_PORTSTART_TIMEOUT Event END.\n"))
48151+ ("SK_RLMT_PORTSTART_TIMEOUT Event END.\n"));
48152 } /* SkRlmtEvtPortStartTim */
48153
48154
48155@@ -2018,21 +2021,21 @@
48156 SK_EVPARA Para2;
48157
48158 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48159- ("SK_RLMT_LINK_UP Port %d Event BEGIN.\n", Para.Para32[0]))
48160+ ("SK_RLMT_LINK_UP Port %d Event BEGIN.\n", Para.Para32[0]));
48161
48162 pRPort = &pAC->Rlmt.Port[Para.Para32[0]];
48163 if (!pRPort->PortStarted) {
48164 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_RLMT_E008, SKERR_RLMT_E008_MSG);
48165
48166 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48167- ("SK_RLMT_LINK_UP Event EMPTY.\n"))
48168+ ("SK_RLMT_LINK_UP Event EMPTY.\n"));
48169 return;
48170 }
48171
48172 if (!pRPort->LinkDown) {
48173 /* RA;:;: Any better solution? */
48174 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48175- ("SK_RLMT_LINK_UP Event EMPTY.\n"))
48176+ ("SK_RLMT_LINK_UP Event EMPTY.\n"));
48177 return;
48178 }
48179
48180@@ -2082,16 +2085,19 @@
48181 Para2.Para32[1] = (SK_U32)-1;
48182 SkTimerStart(pAC, IoC, &pRPort->UpTimer, SK_RLMT_PORTUP_TIM_VAL,
48183 SKGE_RLMT, SK_RLMT_PORTUP_TIM, Para2);
48184-
48185+
48186 /* Later: if (pAC->Rlmt.RlmtMode & SK_RLMT_CHECK_LOC_LINK) && */
48187- if ((pRPort->Net->RlmtMode & SK_RLMT_TRANSPARENT) == 0 &&
48188- (pRPort->Net->RlmtMode & SK_RLMT_CHECK_LINK) != 0 &&
48189- (Para2.pParaPtr =
48190- SkRlmtBuildPacket(pAC, IoC, Para.Para32[0], SK_PACKET_ANNOUNCE,
48191- &pAC->Addr.Port[Para.Para32[0]].CurrentMacAddress, &SkRlmtMcAddr)
48192- ) != NULL) {
48193- /* Send "new" packet to RLMT multicast address. */
48194- SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para2);
48195+ if (pAC->Rlmt.NumNets == 1) {
48196+ if ((pRPort->Net->RlmtMode & SK_RLMT_TRANSPARENT) == 0 &&
48197+ (pRPort->Net->RlmtMode & SK_RLMT_CHECK_LINK) != 0 &&
48198+ (Para2.pParaPtr =
48199+ SkRlmtBuildPacket(pAC, IoC, Para.Para32[0], SK_PACKET_ANNOUNCE,
48200+ &pAC->Addr.Port[Para.Para32[0]].CurrentMacAddress, &SkRlmtMcAddr)
48201+ ) != NULL) {
48202+
48203+ /* Send "new" packet to RLMT multicast address. */
48204+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_RLMT_SEND, Para2);
48205+ }
48206 }
48207
48208 if (pRPort->Net->RlmtMode & SK_RLMT_CHECK_SEG) {
48209@@ -2110,7 +2116,7 @@
48210 }
48211
48212 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48213- ("SK_RLMT_LINK_UP Event END.\n"))
48214+ ("SK_RLMT_LINK_UP Event END.\n"));
48215 } /* SkRlmtEvtLinkUp */
48216
48217
48218@@ -2136,20 +2142,20 @@
48219 SK_RLMT_PORT *pRPort;
48220
48221 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48222- ("SK_RLMT_PORTUP_TIM Port %d Event BEGIN.\n", Para.Para32[0]))
48223+ ("SK_RLMT_PORTUP_TIM Port %d Event BEGIN.\n", Para.Para32[0]));
48224
48225 if (Para.Para32[1] != (SK_U32)-1) {
48226 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48227- ("Bad Parameter.\n"))
48228+ ("Bad Parameter.\n"));
48229 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48230- ("SK_RLMT_PORTUP_TIM Event EMPTY.\n"))
48231+ ("SK_RLMT_PORTUP_TIM Event EMPTY.\n"));
48232 return;
48233 }
48234
48235 pRPort = &pAC->Rlmt.Port[Para.Para32[0]];
48236 if (pRPort->LinkDown || (pRPort->PortState == SK_RLMT_PS_UP)) {
48237 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48238- ("SK_RLMT_PORTUP_TIM Port %d Event EMPTY.\n", Para.Para32[0]))
48239+ ("SK_RLMT_PORTUP_TIM Port %d Event EMPTY.\n", Para.Para32[0]));
48240 return;
48241 }
48242
48243@@ -2164,7 +2170,7 @@
48244 }
48245
48246 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48247- ("SK_RLMT_PORTUP_TIM Event END.\n"))
48248+ ("SK_RLMT_PORTUP_TIM Event END.\n"));
48249 } /* SkRlmtEvtPortUpTim */
48250
48251
48252@@ -2192,13 +2198,13 @@
48253
48254 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48255 ("SK_RLMT_PORTDOWN* Port %d Event (%d) BEGIN.\n",
48256- Para.Para32[0], Event))
48257+ Para.Para32[0], Event));
48258
48259 if (Para.Para32[1] != (SK_U32)-1) {
48260 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48261- ("Bad Parameter.\n"))
48262+ ("Bad Parameter.\n"));
48263 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48264- ("SK_RLMT_PORTDOWN* Event EMPTY.\n"))
48265+ ("SK_RLMT_PORTDOWN* Event EMPTY.\n"));
48266 return;
48267 }
48268
48269@@ -2206,7 +2212,7 @@
48270 if (!pRPort->PortStarted || (Event == SK_RLMT_PORTDOWN_TX_TIM &&
48271 !(pRPort->CheckingState & SK_RLMT_PCS_TX))) {
48272 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48273- ("SK_RLMT_PORTDOWN* Event (%d) EMPTY.\n", Event))
48274+ ("SK_RLMT_PORTDOWN* Event (%d) EMPTY.\n", Event));
48275 return;
48276 }
48277
48278@@ -2243,7 +2249,7 @@
48279 }
48280
48281 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48282- ("SK_RLMT_PORTDOWN* Event (%d) END.\n", Event))
48283+ ("SK_RLMT_PORTDOWN* Event (%d) END.\n", Event));
48284 } /* SkRlmtEvtPortDownX */
48285
48286
48287@@ -2270,7 +2276,7 @@
48288
48289 pRPort = &pAC->Rlmt.Port[Para.Para32[0]];
48290 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48291- ("SK_RLMT_LINK_DOWN Port %d Event BEGIN.\n", Para.Para32[0]))
48292+ ("SK_RLMT_LINK_DOWN Port %d Event BEGIN.\n", Para.Para32[0]));
48293
48294 if (!pAC->Rlmt.Port[Para.Para32[0]].LinkDown) {
48295 pRPort->Net->LinksUp--;
48296@@ -2289,7 +2295,7 @@
48297 }
48298
48299 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48300- ("SK_RLMT_LINK_DOWN Event END.\n"))
48301+ ("SK_RLMT_LINK_DOWN Event END.\n"));
48302 } /* SkRlmtEvtLinkDown */
48303
48304
48305@@ -2318,13 +2324,13 @@
48306 SK_MAC_ADDR *pNewMacAddr;
48307
48308 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48309- ("SK_RLMT_PORT_ADDR Port %d Event BEGIN.\n", Para.Para32[0]))
48310+ ("SK_RLMT_PORT_ADDR Port %d Event BEGIN.\n", Para.Para32[0]));
48311
48312 if (Para.Para32[1] != (SK_U32)-1) {
48313 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48314- ("Bad Parameter.\n"))
48315+ ("Bad Parameter.\n"));
48316 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48317- ("SK_RLMT_PORT_ADDR Event EMPTY.\n"))
48318+ ("SK_RLMT_PORT_ADDR Event EMPTY.\n"));
48319 return;
48320 }
48321
48322@@ -2348,7 +2354,7 @@
48323 }
48324
48325 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48326- ("SK_RLMT_PORT_ADDR Event END.\n"))
48327+ ("SK_RLMT_PORT_ADDR Event END.\n"));
48328 } /* SkRlmtEvtPortAddr */
48329
48330
48331@@ -2376,35 +2382,35 @@
48332 SK_U32 PortNumber;
48333
48334 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48335- ("SK_RLMT_START Net %d Event BEGIN.\n", Para.Para32[0]))
48336+ ("SK_RLMT_START Net %d Event BEGIN.\n", Para.Para32[0]));
48337
48338 if (Para.Para32[1] != (SK_U32)-1) {
48339 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48340- ("Bad Parameter.\n"))
48341+ ("Bad Parameter.\n"));
48342 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48343- ("SK_RLMT_START Event EMPTY.\n"))
48344+ ("SK_RLMT_START Event EMPTY.\n"));
48345 return;
48346 }
48347
48348 if (Para.Para32[0] >= pAC->Rlmt.NumNets) {
48349 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48350- ("Bad NetNumber %d.\n", Para.Para32[0]))
48351+ ("Bad NetNumber %d.\n", Para.Para32[0]));
48352 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48353- ("SK_RLMT_START Event EMPTY.\n"))
48354+ ("SK_RLMT_START Event EMPTY.\n"));
48355 return;
48356 }
48357
48358 if (pAC->Rlmt.Net[Para.Para32[0]].RlmtState != SK_RLMT_RS_INIT) {
48359 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48360- ("SK_RLMT_START Event EMPTY.\n"))
48361+ ("SK_RLMT_START Event EMPTY.\n"));
48362 return;
48363 }
48364
48365 if (pAC->Rlmt.NetsStarted >= pAC->Rlmt.NumNets) {
48366 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48367- ("All nets should have been started.\n"))
48368+ ("All nets should have been started.\n"));
48369 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48370- ("SK_RLMT_START Event EMPTY.\n"))
48371+ ("SK_RLMT_START Event EMPTY.\n"));
48372 return;
48373 }
48374
48375@@ -2438,7 +2444,7 @@
48376 pAC->Rlmt.NetsStarted++;
48377
48378 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48379- ("SK_RLMT_START Event END.\n"))
48380+ ("SK_RLMT_START Event END.\n"));
48381 } /* SkRlmtEvtStart */
48382
48383
48384@@ -2466,35 +2472,35 @@
48385 SK_U32 i;
48386
48387 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48388- ("SK_RLMT_STOP Net %d Event BEGIN.\n", Para.Para32[0]))
48389+ ("SK_RLMT_STOP Net %d Event BEGIN.\n", Para.Para32[0]));
48390
48391 if (Para.Para32[1] != (SK_U32)-1) {
48392 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48393- ("Bad Parameter.\n"))
48394+ ("Bad Parameter.\n"));
48395 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48396- ("SK_RLMT_STOP Event EMPTY.\n"))
48397+ ("SK_RLMT_STOP Event EMPTY.\n"));
48398 return;
48399 }
48400
48401 if (Para.Para32[0] >= pAC->Rlmt.NumNets) {
48402 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48403- ("Bad NetNumber %d.\n", Para.Para32[0]))
48404+ ("Bad NetNumber %d.\n", Para.Para32[0]));
48405 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48406- ("SK_RLMT_STOP Event EMPTY.\n"))
48407+ ("SK_RLMT_STOP Event EMPTY.\n"));
48408 return;
48409 }
48410
48411 if (pAC->Rlmt.Net[Para.Para32[0]].RlmtState == SK_RLMT_RS_INIT) {
48412 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48413- ("SK_RLMT_STOP Event EMPTY.\n"))
48414+ ("SK_RLMT_STOP Event EMPTY.\n"));
48415 return;
48416 }
48417
48418 if (pAC->Rlmt.NetsStarted == 0) {
48419 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48420- ("All nets are stopped.\n"))
48421+ ("All nets are stopped.\n"));
48422 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48423- ("SK_RLMT_STOP Event EMPTY.\n"))
48424+ ("SK_RLMT_STOP Event EMPTY.\n"));
48425 return;
48426 }
48427
48428@@ -2529,7 +2535,7 @@
48429 pAC->Rlmt.NetsStarted--;
48430
48431 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48432- ("SK_RLMT_STOP Event END.\n"))
48433+ ("SK_RLMT_STOP Event END.\n"));
48434 } /* SkRlmtEvtStop */
48435
48436
48437@@ -2559,13 +2565,13 @@
48438 SK_U32 i;
48439
48440 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48441- ("SK_RLMT_TIM Event BEGIN.\n"))
48442+ ("SK_RLMT_TIM Event BEGIN.\n"));
48443
48444 if (Para.Para32[1] != (SK_U32)-1) {
48445 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48446- ("Bad Parameter.\n"))
48447+ ("Bad Parameter.\n"));
48448 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48449- ("SK_RLMT_TIM Event EMPTY.\n"))
48450+ ("SK_RLMT_TIM Event EMPTY.\n"));
48451 return;
48452 }
48453
48454@@ -2637,7 +2643,7 @@
48455 }
48456
48457 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48458- ("SK_RLMT_TIM Event END.\n"))
48459+ ("SK_RLMT_TIM Event END.\n"));
48460 } /* SkRlmtEvtTim */
48461
48462
48463@@ -2665,13 +2671,13 @@
48464 #endif /* DEBUG */
48465
48466 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48467- ("SK_RLMT_SEG_TIM Event BEGIN.\n"))
48468+ ("SK_RLMT_SEG_TIM Event BEGIN.\n"));
48469
48470 if (Para.Para32[1] != (SK_U32)-1) {
48471 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48472- ("Bad Parameter.\n"))
48473+ ("Bad Parameter.\n"));
48474 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48475- ("SK_RLMT_SEG_TIM Event EMPTY.\n"))
48476+ ("SK_RLMT_SEG_TIM Event EMPTY.\n"));
48477 return;
48478 }
48479
48480@@ -2695,7 +2701,7 @@
48481 InAddr8[3], InAddr8[4], InAddr8[5],
48482 pAPort->Exact[k].a[0], pAPort->Exact[k].a[1],
48483 pAPort->Exact[k].a[2], pAPort->Exact[k].a[3],
48484- pAPort->Exact[k].a[4], pAPort->Exact[k].a[5]))
48485+ pAPort->Exact[k].a[4], pAPort->Exact[k].a[5]));
48486 }
48487 }
48488 #endif /* xDEBUG */
48489@@ -2703,7 +2709,7 @@
48490 SkRlmtCheckSeg(pAC, IoC, Para.Para32[0]);
48491
48492 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48493- ("SK_RLMT_SEG_TIM Event END.\n"))
48494+ ("SK_RLMT_SEG_TIM Event END.\n"));
48495 } /* SkRlmtEvtSegTim */
48496
48497
48498@@ -2732,18 +2738,18 @@
48499
48500
48501 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48502- ("SK_RLMT_PACKET_RECEIVED Event BEGIN.\n"))
48503+ ("SK_RLMT_PACKET_RECEIVED Event BEGIN.\n"));
48504
48505 /* Should we ignore frames during port switching? */
48506
48507 #ifdef DEBUG
48508 pMb = Para.pParaPtr;
48509 if (pMb == NULL) {
48510- SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, ("No mbuf.\n"))
48511+ SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL, ("No mbuf.\n"));
48512 }
48513 else if (pMb->pNext != NULL) {
48514 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48515- ("More than one mbuf or pMb->pNext not set.\n"))
48516+ ("More than one mbuf or pMb->pNext not set.\n"));
48517 }
48518 #endif /* DEBUG */
48519
48520@@ -2761,7 +2767,7 @@
48521 }
48522
48523 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48524- ("SK_RLMT_PACKET_RECEIVED Event END.\n"))
48525+ ("SK_RLMT_PACKET_RECEIVED Event END.\n"));
48526 } /* SkRlmtEvtPacketRx */
48527
48528
48529@@ -2788,21 +2794,21 @@
48530 SK_RLMT_PORT *pRPort;
48531
48532 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48533- ("SK_RLMT_STATS_CLEAR Event BEGIN.\n"))
48534+ ("SK_RLMT_STATS_CLEAR Event BEGIN.\n"));
48535
48536 if (Para.Para32[1] != (SK_U32)-1) {
48537 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48538- ("Bad Parameter.\n"))
48539+ ("Bad Parameter.\n"));
48540 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48541- ("SK_RLMT_STATS_CLEAR Event EMPTY.\n"))
48542+ ("SK_RLMT_STATS_CLEAR Event EMPTY.\n"));
48543 return;
48544 }
48545
48546 if (Para.Para32[0] >= pAC->Rlmt.NumNets) {
48547 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48548- ("Bad NetNumber %d.\n", Para.Para32[0]))
48549+ ("Bad NetNumber %d.\n", Para.Para32[0]));
48550 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48551- ("SK_RLMT_STATS_CLEAR Event EMPTY.\n"))
48552+ ("SK_RLMT_STATS_CLEAR Event EMPTY.\n"));
48553 return;
48554 }
48555
48556@@ -2817,7 +2823,7 @@
48557 }
48558
48559 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48560- ("SK_RLMT_STATS_CLEAR Event END.\n"))
48561+ ("SK_RLMT_STATS_CLEAR Event END.\n"));
48562 } /* SkRlmtEvtStatsClear */
48563
48564
48565@@ -2841,28 +2847,28 @@
48566 SK_EVPARA Para) /* SK_U32 NetNumber; SK_U32 -1 */
48567 {
48568 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48569- ("SK_RLMT_STATS_UPDATE Event BEGIN.\n"))
48570+ ("SK_RLMT_STATS_UPDATE Event BEGIN.\n"));
48571
48572 if (Para.Para32[1] != (SK_U32)-1) {
48573 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48574- ("Bad Parameter.\n"))
48575+ ("Bad Parameter.\n"));
48576 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48577- ("SK_RLMT_STATS_UPDATE Event EMPTY.\n"))
48578+ ("SK_RLMT_STATS_UPDATE Event EMPTY.\n"));
48579 return;
48580 }
48581
48582 if (Para.Para32[0] >= pAC->Rlmt.NumNets) {
48583 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48584- ("Bad NetNumber %d.\n", Para.Para32[0]))
48585+ ("Bad NetNumber %d.\n", Para.Para32[0]));
48586 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48587- ("SK_RLMT_STATS_UPDATE Event EMPTY.\n"))
48588+ ("SK_RLMT_STATS_UPDATE Event EMPTY.\n"));
48589 return;
48590 }
48591
48592 /* Update statistics - currently always up-to-date. */
48593
48594 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48595- ("SK_RLMT_STATS_UPDATE Event END.\n"))
48596+ ("SK_RLMT_STATS_UPDATE Event END.\n"));
48597 } /* SkRlmtEvtStatsUpdate */
48598
48599
48600@@ -2886,13 +2892,13 @@
48601 SK_EVPARA Para) /* SK_U32 PortIndex; SK_U32 NetNumber */
48602 {
48603 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48604- ("SK_RLMT_PREFPORT_CHANGE to Port %d Event BEGIN.\n", Para.Para32[0]))
48605+ ("SK_RLMT_PREFPORT_CHANGE to Port %d Event BEGIN.\n", Para.Para32[0]));
48606
48607 if (Para.Para32[1] >= pAC->Rlmt.NumNets) {
48608 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48609- ("Bad NetNumber %d.\n", Para.Para32[1]))
48610+ ("Bad NetNumber %d.\n", Para.Para32[1]));
48611 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48612- ("SK_RLMT_PREFPORT_CHANGE Event EMPTY.\n"))
48613+ ("SK_RLMT_PREFPORT_CHANGE Event EMPTY.\n"));
48614 return;
48615 }
48616
48617@@ -2905,7 +2911,7 @@
48618 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_RLMT_E010, SKERR_RLMT_E010_MSG);
48619
48620 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48621- ("SK_RLMT_PREFPORT_CHANGE Event EMPTY.\n"))
48622+ ("SK_RLMT_PREFPORT_CHANGE Event EMPTY.\n"));
48623 return;
48624 }
48625
48626@@ -2919,7 +2925,7 @@
48627 }
48628
48629 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48630- ("SK_RLMT_PREFPORT_CHANGE Event END.\n"))
48631+ ("SK_RLMT_PREFPORT_CHANGE Event END.\n"));
48632 } /* SkRlmtEvtPrefportChange */
48633
48634
48635@@ -2945,37 +2951,37 @@
48636 int i;
48637
48638 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48639- ("SK_RLMT_SET_NETS Event BEGIN.\n"))
48640+ ("SK_RLMT_SET_NETS Event BEGIN.\n"));
48641
48642 if (Para.Para32[1] != (SK_U32)-1) {
48643 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48644- ("Bad Parameter.\n"))
48645+ ("Bad Parameter.\n"));
48646 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48647- ("SK_RLMT_SET_NETS Event EMPTY.\n"))
48648+ ("SK_RLMT_SET_NETS Event EMPTY.\n"));
48649 return;
48650 }
48651
48652 if (Para.Para32[0] == 0 || Para.Para32[0] > SK_MAX_NETS ||
48653 Para.Para32[0] > (SK_U32)pAC->GIni.GIMacsFound) {
48654 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48655- ("Bad number of nets: %d.\n", Para.Para32[0]))
48656+ ("Bad number of nets: %d.\n", Para.Para32[0]));
48657 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48658- ("SK_RLMT_SET_NETS Event EMPTY.\n"))
48659+ ("SK_RLMT_SET_NETS Event EMPTY.\n"));
48660 return;
48661 }
48662
48663 if (Para.Para32[0] == pAC->Rlmt.NumNets) { /* No change. */
48664 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48665- ("SK_RLMT_SET_NETS Event EMPTY.\n"))
48666+ ("SK_RLMT_SET_NETS Event EMPTY.\n"));
48667 return;
48668 }
48669
48670 /* Entering and leaving dual mode only allowed while nets are stopped. */
48671 if (pAC->Rlmt.NetsStarted > 0) {
48672 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48673- ("Changing dual mode only allowed while all nets are stopped.\n"))
48674+ ("Changing dual mode only allowed while all nets are stopped.\n"));
48675 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48676- ("SK_RLMT_SET_NETS Event EMPTY.\n"))
48677+ ("SK_RLMT_SET_NETS Event EMPTY.\n"));
48678 return;
48679 }
48680
48681@@ -3006,9 +3012,10 @@
48682 SkEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_RLMT_SET_NETS, Para);
48683
48684 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48685- ("RLMT: Changed to one net with two ports.\n"))
48686+ ("RLMT: Changed to one net with two ports.\n"));
48687 }
48688 else if (Para.Para32[0] == 2) {
48689+ pAC->Rlmt.RlmtOff = SK_TRUE;
48690 pAC->Rlmt.Port[1].Net= &pAC->Rlmt.Net[1];
48691 pAC->Rlmt.Net[1].NumPorts = pAC->GIni.GIMacsFound - 1;
48692 pAC->Rlmt.Net[0].NumPorts =
48693@@ -3035,19 +3042,19 @@
48694 SkEventQueue(pAC, SKGE_PNMI, SK_PNMI_EVT_RLMT_SET_NETS, Para);
48695
48696 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48697- ("RLMT: Changed to two nets with one port each.\n"))
48698+ ("RLMT: Changed to two nets with one port each.\n"));
48699 }
48700 else {
48701 /* Not implemented for more than two nets. */
48702 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48703- ("SetNets not implemented for more than two nets.\n"))
48704+ ("SetNets not implemented for more than two nets.\n"));
48705 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48706- ("SK_RLMT_SET_NETS Event EMPTY.\n"))
48707+ ("SK_RLMT_SET_NETS Event EMPTY.\n"));
48708 return;
48709 }
48710
48711 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48712- ("SK_RLMT_SET_NETS Event END.\n"))
48713+ ("SK_RLMT_SET_NETS Event END.\n"));
48714 } /* SkRlmtSetNets */
48715
48716
48717@@ -3075,13 +3082,13 @@
48718 SK_U32 PrevRlmtMode;
48719
48720 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48721- ("SK_RLMT_MODE_CHANGE Event BEGIN.\n"))
48722+ ("SK_RLMT_MODE_CHANGE Event BEGIN.\n"));
48723
48724 if (Para.Para32[1] >= pAC->Rlmt.NumNets) {
48725 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48726- ("Bad NetNumber %d.\n", Para.Para32[1]))
48727+ ("Bad NetNumber %d.\n", Para.Para32[1]));
48728 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48729- ("SK_RLMT_MODE_CHANGE Event EMPTY.\n"))
48730+ ("SK_RLMT_MODE_CHANGE Event EMPTY.\n"));
48731 return;
48732 }
48733
48734@@ -3091,9 +3098,9 @@
48735 Para.Para32[0] != SK_RLMT_MODE_CLS) {
48736 pAC->Rlmt.Net[Para.Para32[1]].RlmtMode = SK_RLMT_MODE_CLS;
48737 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48738- ("Forced RLMT mode to CLS on single port net.\n"))
48739+ ("Forced RLMT mode to CLS on single port net.\n"));
48740 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48741- ("SK_RLMT_MODE_CHANGE Event EMPTY.\n"))
48742+ ("SK_RLMT_MODE_CHANGE Event EMPTY.\n"));
48743 return;
48744 }
48745
48746@@ -3159,7 +3166,7 @@
48747 } /* SK_RLMT_CHECK_SEG bit changed. */
48748
48749 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48750- ("SK_RLMT_MODE_CHANGE Event END.\n"))
48751+ ("SK_RLMT_MODE_CHANGE Event END.\n"));
48752 } /* SkRlmtEvtModeChange */
48753
48754
48755@@ -3245,7 +3252,7 @@
48756
48757 default: /* Create error log entry. */
48758 SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
48759- ("Unknown RLMT Event %d.\n", Event))
48760+ ("Unknown RLMT Event %d.\n", Event));
48761 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_RLMT_E003, SKERR_RLMT_E003_MSG);
48762 break;
48763 } /* switch() */
48764diff -ruN linux/drivers/net/sk98lin/sktimer.c linux-new/drivers/net/sk98lin/sktimer.c
48765--- linux/drivers/net/sk98lin/sktimer.c 2006-04-11 19:19:28.000000000 +0200
48766+++ linux-new/drivers/net/sk98lin/sktimer.c 2006-01-18 14:37:24.000000000 +0100
48767@@ -2,8 +2,8 @@
48768 *
48769 * Name: sktimer.c
48770 * Project: Gigabit Ethernet Adapters, Event Scheduler Module
48771- * Version: $Revision$
48772- * Date: $Date$
48773+ * Version: $Revision$
48774+ * Date: $Date$
48775 * Purpose: High level timer functions.
48776 *
48777 ******************************************************************************/
48778@@ -11,7 +11,7 @@
48779 /******************************************************************************
48780 *
48781 * (C)Copyright 1998-2002 SysKonnect GmbH.
48782- * (C)Copyright 2002-2003 Marvell.
48783+ * (C)Copyright 2002-2004 Marvell.
48784 *
48785 * This program is free software; you can redistribute it and/or modify
48786 * it under the terms of the GNU General Public License as published by
48787@@ -22,13 +22,12 @@
48788 *
48789 ******************************************************************************/
48790
48791-
48792 /*
48793 * Event queue and dispatcher
48794 */
48795 #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
48796 static const char SysKonnectFileId[] =
48797- "@(#) $Id$ (C) Marvell.";
48798+ "@(#) $Id$ (C) Marvell.";
48799 #endif
48800
48801 #include "h/skdrv1st.h" /* Driver Specific Definitions */
48802@@ -62,7 +61,7 @@
48803 {
48804 switch (Level) {
48805 case SK_INIT_DATA:
48806- pAC->Tim.StQueue = NULL;
48807+ pAC->Tim.StQueue = 0;
48808 break;
48809 case SK_INIT_IO:
48810 SkHwtInit(pAC, Ioc);
48811@@ -85,22 +84,20 @@
48812 SK_TIMER **ppTimPrev;
48813 SK_TIMER *pTm;
48814
48815- /*
48816- * remove timer from queue
48817- */
48818+ /* remove timer from queue */
48819 pTimer->TmActive = SK_FALSE;
48820-
48821+
48822 if (pAC->Tim.StQueue == pTimer && !pTimer->TmNext) {
48823 SkHwtStop(pAC, Ioc);
48824 }
48825-
48826+
48827 for (ppTimPrev = &pAC->Tim.StQueue; (pTm = *ppTimPrev);
48828 ppTimPrev = &pTm->TmNext ) {
48829-
48830+
48831 if (pTm == pTimer) {
48832 /*
48833 * Timer found in queue
48834- * - dequeue it and
48835+ * - dequeue it
48836 * - correct delta of the next timer
48837 */
48838 *ppTimPrev = pTm->TmNext;
48839@@ -121,7 +118,7 @@
48840 SK_AC *pAC, /* Adapters context */
48841 SK_IOC Ioc, /* IoContext */
48842 SK_TIMER *pTimer, /* Timer Pointer to be started */
48843-SK_U32 Time, /* Time value */
48844+SK_U32 Time, /* Time Value (in microsec.) */
48845 SK_U32 Class, /* Event Class for this timer */
48846 SK_U32 Event, /* Event Value for this timer */
48847 SK_EVPARA Para) /* Event Parameter for this timer */
48848@@ -130,11 +127,6 @@
48849 SK_TIMER *pTm;
48850 SK_U32 Delta;
48851
48852- Time /= 16; /* input is uS, clock ticks are 16uS */
48853-
48854- if (!Time)
48855- Time = 1;
48856-
48857 SkTimerStop(pAC, Ioc, pTimer);
48858
48859 pTimer->TmClass = Class;
48860@@ -143,31 +135,26 @@
48861 pTimer->TmActive = SK_TRUE;
48862
48863 if (!pAC->Tim.StQueue) {
48864- /* First Timer to be started */
48865+ /* first Timer to be started */
48866 pAC->Tim.StQueue = pTimer;
48867- pTimer->TmNext = NULL;
48868+ pTimer->TmNext = 0;
48869 pTimer->TmDelta = Time;
48870-
48871+
48872 SkHwtStart(pAC, Ioc, Time);
48873-
48874+
48875 return;
48876 }
48877
48878- /*
48879- * timer correction
48880- */
48881+ /* timer correction */
48882 timer_done(pAC, Ioc, 0);
48883
48884- /*
48885- * find position in queue
48886- */
48887+ /* find position in queue */
48888 Delta = 0;
48889 for (ppTimPrev = &pAC->Tim.StQueue; (pTm = *ppTimPrev);
48890 ppTimPrev = &pTm->TmNext ) {
48891-
48892+
48893 if (Delta + pTm->TmDelta > Time) {
48894- /* Position found */
48895- /* Here the timer needs to be inserted. */
48896+ /* the timer needs to be inserted here */
48897 break;
48898 }
48899 Delta += pTm->TmDelta;
48900@@ -179,9 +166,7 @@
48901 pTimer->TmDelta = Time - Delta;
48902
48903 if (pTm) {
48904- /* There is a next timer
48905- * -> correct its Delta value.
48906- */
48907+ /* there is a next timer: correct its Delta value */
48908 pTm->TmDelta -= pTimer->TmDelta;
48909 }
48910
48911@@ -210,7 +195,7 @@
48912 int Done = 0;
48913
48914 Delta = SkHwtRead(pAC, Ioc);
48915-
48916+
48917 ppLast = &pAC->Tim.StQueue;
48918 pTm = pAC->Tim.StQueue;
48919 while (pTm && !Done) {
48920@@ -228,13 +213,13 @@
48921 Done = 1;
48922 }
48923 }
48924- *ppLast = NULL;
48925+ *ppLast = 0;
48926 /*
48927 * pTm points to the first Timer that did not run out.
48928 * StQueue points to the first Timer that run out.
48929 */
48930
48931- for ( pTComp = pAC->Tim.StQueue; pTComp; pTComp = pTComp->TmNext) {
48932+ for (pTComp = pAC->Tim.StQueue; pTComp; pTComp = pTComp->TmNext) {
48933 SkEventQueue(pAC,pTComp->TmClass, pTComp->TmEvent, pTComp->TmPara);
48934 }
48935
48936diff -ruN linux/drivers/net/sk98lin/sktwsi.c linux-new/drivers/net/sk98lin/sktwsi.c
48937--- linux/drivers/net/sk98lin/sktwsi.c 1970-01-01 01:00:00.000000000 +0100
48938+++ linux-new/drivers/net/sk98lin/sktwsi.c 2006-01-18 14:37:24.000000000 +0100
48939@@ -0,0 +1,1359 @@
48940+/******************************************************************************
48941+ *
48942+ * Name: sktwsi.c
48943+ * Project: Gigabit Ethernet Adapters, TWSI-Module
48944+ * Version: $Revision$
48945+ * Date: $Date$
48946+ * Purpose: Functions to access Voltage and Temperature Sensor
48947+ *
48948+ ******************************************************************************/
48949+
48950+/******************************************************************************
48951+ *
48952+ * (C)Copyright 1998-2002 SysKonnect.
48953+ * (C)Copyright 2002-2005 Marvell.
48954+ *
48955+ * This program is free software; you can redistribute it and/or modify
48956+ * it under the terms of the GNU General Public License as published by
48957+ * the Free Software Foundation; either version 2 of the License, or
48958+ * (at your option) any later version.
48959+ * The information in this file is provided "AS IS" without warranty.
48960+ *
48961+ ******************************************************************************/
48962+
48963+/*
48964+ * TWSI Protocol
48965+ */
48966+#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
48967+static const char SysKonnectFileId[] =
48968+ "@(#) $Id$ (C) Marvell.";
48969+#endif
48970+
48971+#include "h/skdrv1st.h" /* Driver Specific Definitions */
48972+#include "h/lm80.h"
48973+#include "h/skdrv2nd.h" /* Adapter Control- and Driver specific Def. */
48974+
48975+#ifdef __C2MAN__
48976+/*
48977+ TWSI protocol implementation.
48978+
48979+ General Description:
48980+
48981+ The TWSI protocol is used for the temperature sensors and for
48982+ the serial EEPROM which hold the configuration.
48983+
48984+ This file covers functions that allow to read write and do
48985+ some bulk requests a specified TWSI address.
48986+
48987+ The Genesis has 2 TWSI buses. One for the EEPROM which holds
48988+ the VPD Data and one for temperature and voltage sensor.
48989+ The following picture shows the TWSI buses, TWSI devices and
48990+ their control registers.
48991+
48992+ Note: The VPD functions are in skvpd.c
48993+.
48994+. PCI Config TWSI Bus for VPD Data:
48995+.
48996+. +------------+
48997+. | VPD EEPROM |
48998+. +------------+
48999+. |
49000+. | <-- TWSI
49001+. |
49002+. +-----------+-----------+
49003+. | |
49004+. +-----------------+ +-----------------+
49005+. | PCI_VPD_ADR_REG | | PCI_VPD_DAT_REG |
49006+. +-----------------+ +-----------------+
49007+.
49008+.
49009+. TWSI Bus for LM80 sensor:
49010+.
49011+. +-----------------+
49012+. | Temperature and |
49013+. | Voltage Sensor |
49014+. | LM80 |
49015+. +-----------------+
49016+. |
49017+. |
49018+. TWSI --> |
49019+. |
49020+. +----+
49021+. +-------------->| OR |<--+
49022+. | +----+ |
49023+. +------+------+ |
49024+. | | |
49025+. +--------+ +--------+ +----------+
49026+. | B2_I2C | | B2_I2C | | B2_I2C |
49027+. | _CTRL | | _DATA | | _SW |
49028+. +--------+ +--------+ +----------+
49029+.
49030+ The TWSI bus may be driven by the B2_I2C_SW or by the B2_I2C_CTRL
49031+ and B2_I2C_DATA registers.
49032+ For driver software it is recommended to use the TWSI control and
49033+ data register, because TWSI bus timing is done by the ASIC and
49034+ an interrupt may be received when the TWSI request is completed.
49035+
49036+ Clock Rate Timing: MIN MAX generated by
49037+ VPD EEPROM: 50 kHz 100 kHz HW
49038+ LM80 over TWSI Ctrl/Data reg. 50 kHz 100 kHz HW
49039+ LM80 over B2_I2C_SW register 0 400 kHz SW
49040+
49041+ Note: The clock generated by the hardware is dependend on the
49042+ PCI clock. If the PCI bus clock is 33 MHz, the I2C/VPD
49043+ clock is 50 kHz.
49044+ */
49045+intro()
49046+{}
49047+#endif
49048+
49049+#ifdef SK_DIAG
49050+/*
49051+ * TWSI Fast Mode timing values used by the LM80.
49052+ * If new devices are added to the TWSI bus the timing values have to be checked.
49053+ */
49054+#ifndef I2C_SLOW_TIMING
49055+#define T_CLK_LOW 1300L /* clock low time in ns */
49056+#define T_CLK_HIGH 600L /* clock high time in ns */
49057+#define T_DATA_IN_SETUP 100L /* data in Set-up Time */
49058+#define T_START_HOLD 600L /* start condition hold time */
49059+#define T_START_SETUP 600L /* start condition Set-up time */
49060+#define T_STOP_SETUP 600L /* stop condition Set-up time */
49061+#define T_BUS_IDLE 1300L /* time the bus must free after Tx */
49062+#define T_CLK_2_DATA_OUT 900L /* max. clock low to data output valid */
49063+#else /* I2C_SLOW_TIMING */
49064+/* TWSI Standard Mode Timing */
49065+#define T_CLK_LOW 4700L /* clock low time in ns */
49066+#define T_CLK_HIGH 4000L /* clock high time in ns */
49067+#define T_DATA_IN_SETUP 250L /* data in Set-up Time */
49068+#define T_START_HOLD 4000L /* start condition hold time */
49069+#define T_START_SETUP 4700L /* start condition Set-up time */
49070+#define T_STOP_SETUP 4000L /* stop condition Set-up time */
49071+#define T_BUS_IDLE 4700L /* time the bus must free after Tx */
49072+#endif /* !I2C_SLOW_TIMING */
49073+
49074+#define NS2BCLK(x) (((x)*125)/10000)
49075+
49076+/*
49077+ * TWSI Wire Operations
49078+ *
49079+ * About I2C_CLK_LOW():
49080+ *
49081+ * The Data Direction bit (I2C_DATA_DIR) has to be set to input when setting
49082+ * clock to low, to prevent the ASIC and the TWSI data client from driving the
49083+ * serial data line simultaneously (ASIC: last bit of a byte = '1', TWSI client
49084+ * send an 'ACK'). See also Concentrator Bugreport No. 10192.
49085+ */
49086+#define I2C_DATA_HIGH(IoC) SK_I2C_SET_BIT(IoC, I2C_DATA)
49087+#define I2C_DATA_LOW(IoC) SK_I2C_CLR_BIT(IoC, I2C_DATA)
49088+#define I2C_DATA_OUT(IoC) SK_I2C_SET_BIT(IoC, I2C_DATA_DIR)
49089+#define I2C_DATA_IN(IoC) SK_I2C_CLR_BIT(IoC, I2C_DATA_DIR | I2C_DATA)
49090+#define I2C_CLK_HIGH(IoC) SK_I2C_SET_BIT(IoC, I2C_CLK)
49091+#define I2C_CLK_LOW(IoC) SK_I2C_CLR_BIT(IoC, I2C_CLK | I2C_DATA_DIR)
49092+#define I2C_START_COND(IoC) SK_I2C_CLR_BIT(IoC, I2C_CLK)
49093+
49094+#define NS2CLKT(x) ((x*125L)/10000)
49095+
49096+/*--------------- TWSI Interface Register Functions --------------- */
49097+
49098+/*
49099+ * sending one bit
49100+ */
49101+void SkI2cSndBit(
49102+SK_IOC IoC, /* I/O Context */
49103+SK_U8 Bit) /* Bit to send */
49104+{
49105+ I2C_DATA_OUT(IoC);
49106+ if (Bit) {
49107+ I2C_DATA_HIGH(IoC);
49108+ }
49109+ else {
49110+ I2C_DATA_LOW(IoC);
49111+ }
49112+ SkDgWaitTime(IoC, NS2BCLK(T_DATA_IN_SETUP));
49113+ I2C_CLK_HIGH(IoC);
49114+ SkDgWaitTime(IoC, NS2BCLK(T_CLK_HIGH));
49115+ I2C_CLK_LOW(IoC);
49116+} /* SkI2cSndBit*/
49117+
49118+
49119+/*
49120+ * Signal a start to the TWSI Bus.
49121+ *
49122+ * A start is signaled when data goes to low in a high clock cycle.
49123+ *
49124+ * Ends with Clock Low.
49125+ *
49126+ * Status: not tested
49127+ */
49128+void SkI2cStart(
49129+SK_IOC IoC) /* I/O Context */
49130+{
49131+ /* Init data and Clock to output lines */
49132+ /* Set Data high */
49133+ I2C_DATA_OUT(IoC);
49134+ I2C_DATA_HIGH(IoC);
49135+ /* Set Clock high */
49136+ I2C_CLK_HIGH(IoC);
49137+
49138+ SkDgWaitTime(IoC, NS2BCLK(T_START_SETUP));
49139+
49140+ /* Set Data Low */
49141+ I2C_DATA_LOW(IoC);
49142+
49143+ SkDgWaitTime(IoC, NS2BCLK(T_START_HOLD));
49144+
49145+ /* Clock low without Data to Input */
49146+ I2C_START_COND(IoC);
49147+
49148+ SkDgWaitTime(IoC, NS2BCLK(T_CLK_LOW));
49149+} /* SkI2cStart */
49150+
49151+
49152+void SkI2cStop(
49153+SK_IOC IoC) /* I/O Context */
49154+{
49155+ /* Init data and Clock to output lines */
49156+ /* Set Data low */
49157+ I2C_DATA_OUT(IoC);
49158+ I2C_DATA_LOW(IoC);
49159+
49160+ SkDgWaitTime(IoC, NS2BCLK(T_CLK_2_DATA_OUT));
49161+
49162+ /* Set Clock high */
49163+ I2C_CLK_HIGH(IoC);
49164+
49165+ SkDgWaitTime(IoC, NS2BCLK(T_STOP_SETUP));
49166+
49167+ /*
49168+ * Set Data High: Do it by setting the Data Line to Input.
49169+ * Because of a pull up resistor the Data Line
49170+ * floods to high.
49171+ */
49172+ I2C_DATA_IN(IoC);
49173+
49174+ /*
49175+ * When TWSI activity is stopped
49176+ * o DATA should be set to input and
49177+ * o CLOCK should be set to high!
49178+ */
49179+ SkDgWaitTime(IoC, NS2BCLK(T_BUS_IDLE));
49180+} /* SkI2cStop */
49181+
49182+
49183+/*
49184+ * Receive just one bit via the TWSI bus.
49185+ *
49186+ * Note: Clock must be set to LOW before calling this function.
49187+ *
49188+ * Returns The received bit.
49189+ */
49190+int SkI2cRcvBit(
49191+SK_IOC IoC) /* I/O Context */
49192+{
49193+ int Bit;
49194+ SK_U8 I2cSwCtrl;
49195+
49196+ /* Init data as input line */
49197+ I2C_DATA_IN(IoC);
49198+
49199+ SkDgWaitTime(IoC, NS2BCLK(T_CLK_2_DATA_OUT));
49200+
49201+ I2C_CLK_HIGH(IoC);
49202+
49203+ SkDgWaitTime(IoC, NS2BCLK(T_CLK_HIGH));
49204+
49205+ SK_I2C_GET_SW(IoC, &I2cSwCtrl);
49206+
49207+ Bit = (I2cSwCtrl & I2C_DATA) ? 1 : 0;
49208+
49209+ I2C_CLK_LOW(IoC);
49210+ SkDgWaitTime(IoC, NS2BCLK(T_CLK_LOW-T_CLK_2_DATA_OUT));
49211+
49212+ return(Bit);
49213+} /* SkI2cRcvBit */
49214+
49215+
49216+/*
49217+ * Receive an ACK.
49218+ *
49219+ * returns 0 If acknowledged
49220+ * 1 in case of an error
49221+ */
49222+int SkI2cRcvAck(
49223+SK_IOC IoC) /* I/O Context */
49224+{
49225+ /*
49226+ * Received bit must be zero.
49227+ */
49228+ return(SkI2cRcvBit(IoC) != 0);
49229+} /* SkI2cRcvAck */
49230+
49231+
49232+/*
49233+ * Send an NACK.
49234+ */
49235+void SkI2cSndNAck(
49236+SK_IOC IoC) /* I/O Context */
49237+{
49238+ /*
49239+ * Received bit must be zero.
49240+ */
49241+ SkI2cSndBit(IoC, 1);
49242+} /* SkI2cSndNAck */
49243+
49244+
49245+/*
49246+ * Send an ACK.
49247+ */
49248+void SkI2cSndAck(
49249+SK_IOC IoC) /* I/O Context */
49250+{
49251+ /*
49252+ * Received bit must be zero.
49253+ */
49254+ SkI2cSndBit(IoC, 0);
49255+} /* SkI2cSndAck */
49256+
49257+
49258+/*
49259+ * Send one byte to the TWSI device and wait for ACK.
49260+ *
49261+ * Return acknowleged status.
49262+ */
49263+int SkI2cSndByte(
49264+SK_IOC IoC, /* I/O Context */
49265+int Byte) /* byte to send */
49266+{
49267+ int i;
49268+
49269+ for (i = 0; i < 8; i++) {
49270+ if (Byte & (1<<(7-i))) {
49271+ SkI2cSndBit(IoC, 1);
49272+ }
49273+ else {
49274+ SkI2cSndBit(IoC, 0);
49275+ }
49276+ }
49277+
49278+ return(SkI2cRcvAck(IoC));
49279+} /* SkI2cSndByte */
49280+
49281+
49282+/*
49283+ * Receive one byte and ack it.
49284+ *
49285+ * Return byte.
49286+ */
49287+int SkI2cRcvByte(
49288+SK_IOC IoC, /* I/O Context */
49289+int Last) /* Last Byte Flag */
49290+{
49291+ int i;
49292+ int Byte = 0;
49293+
49294+ for (i = 0; i < 8; i++) {
49295+ Byte <<= 1;
49296+ Byte |= SkI2cRcvBit(IoC);
49297+ }
49298+
49299+ if (Last) {
49300+ SkI2cSndNAck(IoC);
49301+ }
49302+ else {
49303+ SkI2cSndAck(IoC);
49304+ }
49305+
49306+ return(Byte);
49307+} /* SkI2cRcvByte */
49308+
49309+
49310+/*
49311+ * Start dialog and send device address
49312+ *
49313+ * Return 0 if acknowleged, 1 in case of an error
49314+ */
49315+int SkI2cSndDev(
49316+SK_IOC IoC, /* I/O Context */
49317+int Addr, /* Device Address */
49318+int Rw) /* Read / Write Flag */
49319+{
49320+ SkI2cStart(IoC);
49321+ Rw = ~Rw;
49322+ Rw &= I2C_WRITE;
49323+ return(SkI2cSndByte(IoC, (Addr << 1) | Rw));
49324+} /* SkI2cSndDev */
49325+
49326+#endif /* SK_DIAG */
49327+
49328+/*----------------- TWSI CTRL Register Functions ----------*/
49329+
49330+/*
49331+ * waits for a completion of a TWSI transfer
49332+ *
49333+ * returns 0: success, transfer completes
49334+ * 1: error, transfer does not complete, TWSI transfer
49335+ * killed, wait loop terminated.
49336+ */
49337+int SkI2cWait(
49338+SK_AC *pAC, /* Adapter Context */
49339+SK_IOC IoC, /* I/O Context */
49340+int Event) /* complete event to wait for (I2C_READ or I2C_WRITE) */
49341+{
49342+ SK_U64 StartTime;
49343+ SK_U64 CurrentTime;
49344+ SK_U32 I2cCtrl;
49345+
49346+ StartTime = SkOsGetTime(pAC);
49347+
49348+ do {
49349+ CurrentTime = SkOsGetTime(pAC);
49350+
49351+ if (CurrentTime - StartTime > SK_TICKS_PER_SEC / 8) {
49352+
49353+ SK_I2C_STOP(IoC);
49354+#ifndef SK_DIAG
49355+ if (pAC->I2c.InitLevel > SK_INIT_DATA) {
49356+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E002, SKERR_I2C_E002MSG);
49357+ }
49358+#endif /* !SK_DIAG */
49359+ return(1);
49360+ }
49361+
49362+ SK_I2C_GET_CTL(IoC, &I2cCtrl);
49363+
49364+#ifdef xYUKON_DBG
49365+ printf("StartTime=%lu, CurrentTime=%lu\n",
49366+ StartTime, CurrentTime);
49367+ if (kbhit()) {
49368+ return(1);
49369+ }
49370+#endif /* YUKON_DBG */
49371+
49372+ } while ((I2cCtrl & I2C_FLAG) == (SK_U32)Event << 31);
49373+
49374+ return(0);
49375+} /* SkI2cWait */
49376+
49377+
49378+/*
49379+ * waits for a completion of a TWSI transfer
49380+ *
49381+ * Returns
49382+ * Nothing
49383+ */
49384+void SkI2cWaitIrq(
49385+SK_AC *pAC, /* Adapter Context */
49386+SK_IOC IoC) /* I/O Context */
49387+{
49388+ SK_SENSOR *pSen;
49389+ SK_U64 StartTime;
49390+ SK_U32 IrqSrc;
49391+ SK_U32 IsTwsiReadyBit;
49392+
49393+ pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
49394+
49395+ if (pSen->SenState == SK_SEN_IDLE) {
49396+ return;
49397+ }
49398+
49399+ IsTwsiReadyBit = CHIP_ID_YUKON_2(pAC) ? Y2_IS_TWSI_RDY : IS_I2C_READY;
49400+
49401+ StartTime = SkOsGetTime(pAC);
49402+
49403+ do {
49404+ if (SkOsGetTime(pAC) - StartTime > SK_TICKS_PER_SEC / 8) {
49405+
49406+ SK_I2C_STOP(IoC);
49407+#ifndef SK_DIAG
49408+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E016, SKERR_I2C_E016MSG);
49409+#endif /* !SK_DIAG */
49410+ return;
49411+ }
49412+
49413+ SK_IN32(IoC, B0_ISRC, &IrqSrc);
49414+
49415+ } while ((IrqSrc & IsTwsiReadyBit) == 0);
49416+
49417+ pSen->SenState = SK_SEN_IDLE;
49418+ return;
49419+} /* SkI2cWaitIrq */
49420+
49421+/*
49422+ * writes a single byte or 4 bytes into the TWSI device
49423+ *
49424+ * returns 0: success
49425+ * 1: error
49426+ */
49427+int SkI2cWrite(
49428+SK_AC *pAC, /* Adapter Context */
49429+SK_IOC IoC, /* I/O Context */
49430+SK_U32 I2cData, /* TWSI Data to write */
49431+int I2cDev, /* TWSI Device Address */
49432+int I2cDevSize, /* TWSI Device Size (e.g. I2C_025K_DEV or I2C_2K_DEV) */
49433+int I2cReg, /* TWSI Device Register Address */
49434+int I2cBurst) /* TWSI Burst Flag */
49435+{
49436+ SK_OUT32(IoC, B2_I2C_DATA, I2cData);
49437+
49438+ SK_I2C_CTL(IoC, I2C_WRITE, I2cDev, I2cDevSize, I2cReg, I2cBurst);
49439+
49440+ return(SkI2cWait(pAC, IoC, I2C_WRITE));
49441+} /* SkI2cWrite*/
49442+
49443+
49444+#ifdef SK_DIAG
49445+/*
49446+ * reads a single byte or 4 bytes from the TWSI device
49447+ *
49448+ * returns the word read
49449+ */
49450+SK_U32 SkI2cRead(
49451+SK_AC *pAC, /* Adapter Context */
49452+SK_IOC IoC, /* I/O Context */
49453+int I2cDev, /* TWSI Device Address */
49454+int I2cDevSize, /* TWSI Device Size (e.g. I2C_025K_DEV or I2C_2K_DEV) */
49455+int I2cReg, /* TWSI Device Register Address */
49456+int I2cBurst) /* TWSI Burst Flag */
49457+{
49458+ SK_U32 Data;
49459+
49460+ SK_OUT32(IoC, B2_I2C_DATA, 0);
49461+
49462+ SK_I2C_CTL(IoC, I2C_READ, I2cDev, I2cDevSize, I2cReg, I2cBurst);
49463+
49464+ if (SkI2cWait(pAC, IoC, I2C_READ) != 0) {
49465+ w_print("%s\n", SKERR_I2C_E002MSG);
49466+ }
49467+
49468+ SK_IN32(IoC, B2_I2C_DATA, &Data);
49469+
49470+ return(Data);
49471+} /* SkI2cRead */
49472+#endif /* SK_DIAG */
49473+
49474+
49475+/*
49476+ * read a sensor's value
49477+ *
49478+ * This function reads a sensor's value from the TWSI sensor chip. The sensor
49479+ * is defined by its index into the sensors database in the struct pAC points
49480+ * to.
49481+ * Returns
49482+ * 1 if the read is completed
49483+ * 0 if the read must be continued (TWSI Bus still allocated)
49484+ */
49485+int SkI2cReadSensor(
49486+SK_AC *pAC, /* Adapter Context */
49487+SK_IOC IoC, /* I/O Context */
49488+SK_SENSOR *pSen) /* Sensor to be read */
49489+{
49490+ if (pSen->SenRead != NULL) {
49491+ return((*pSen->SenRead)(pAC, IoC, pSen));
49492+ }
49493+
49494+ return(0); /* no success */
49495+} /* SkI2cReadSensor */
49496+
49497+/*
49498+ * Do the Init state 0 initialization
49499+ */
49500+static int SkI2cInit0(
49501+SK_AC *pAC) /* Adapter Context */
49502+{
49503+ int i;
49504+ SK_SENSOR *pSen;
49505+
49506+ /* Begin with first sensor */
49507+ pAC->I2c.CurrSens = 0;
49508+
49509+ /* Begin with timeout control for state machine */
49510+ pAC->I2c.TimerMode = SK_TIMER_WATCH_SM;
49511+
49512+ /* Set sensor number to zero */
49513+ pAC->I2c.MaxSens = 0;
49514+
49515+#ifndef SK_DIAG
49516+ /* Initialize Number of Dummy Reads */
49517+ pAC->I2c.DummyReads = SK_MAX_SENSORS;
49518+#endif /* !SK_DIAG */
49519+
49520+ for (i = 0; i < SK_MAX_SENSORS; i++) {
49521+ pSen = &pAC->I2c.SenTable[i];
49522+
49523+ pSen->SenDesc = "unknown";
49524+ pSen->SenType = SK_SEN_UNKNOWN;
49525+ pSen->SenThreErrHigh = 0;
49526+ pSen->SenThreErrLow = 0;
49527+ pSen->SenThreWarnHigh = 0;
49528+ pSen->SenThreWarnLow = 0;
49529+ pSen->SenReg = LM80_FAN2_IN;
49530+ pSen->SenInit = SK_SEN_DYN_INIT_NONE;
49531+ pSen->SenValue = 0;
49532+ pSen->SenErrFlag = SK_SEN_ERR_NOT_PRESENT;
49533+ pSen->SenErrCts = 0;
49534+ pSen->SenBegErrTS = 0;
49535+ pSen->SenState = SK_SEN_IDLE;
49536+ pSen->SenRead = NULL;
49537+ pSen->SenDev = 0;
49538+ }
49539+
49540+ /* Now we are "INIT data"ed */
49541+ pAC->I2c.InitLevel = SK_INIT_DATA;
49542+ return(0);
49543+} /* SkI2cInit0*/
49544+
49545+
49546+/*
49547+ * Do the init state 1 initialization
49548+ *
49549+ * initialize the following register of the LM80:
49550+ * Configuration register:
49551+ * - START, noINT, activeLOW, noINT#Clear, noRESET, noCI, noGPO#, noINIT
49552+ *
49553+ * Interrupt Mask Register 1:
49554+ * - all interrupts are Disabled (0xff)
49555+ *
49556+ * Interrupt Mask Register 2:
49557+ * - all interrupts are Disabled (0xff) Interrupt modi doesn't matter.
49558+ *
49559+ * Fan Divisor/RST_OUT register:
49560+ * - Divisors set to 1 (bits 00), all others 0s.
49561+ *
49562+ * OS# Configuration/Temperature resolution Register:
49563+ * - all 0s
49564+ *
49565+ */
49566+static int SkI2cInit1(
49567+SK_AC *pAC, /* Adapter Context */
49568+SK_IOC IoC) /* I/O Context */
49569+{
49570+ int i;
49571+ SK_U8 I2cSwCtrl;
49572+ SK_GEPORT *pPrt; /* GIni Port struct pointer */
49573+ SK_SENSOR *pSen;
49574+
49575+ if (pAC->I2c.InitLevel != SK_INIT_DATA) {
49576+ /* Re-init not needed in TWSI module */
49577+ return(0);
49578+ }
49579+
49580+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC ||
49581+ pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) {
49582+ /* No sensors on Yukon-EC and Yukon-FE */
49583+ return(0);
49584+ }
49585+
49586+ /* Set the Direction of TWSI-Data Pin to IN */
49587+ SK_I2C_CLR_BIT(IoC, I2C_DATA_DIR | I2C_DATA);
49588+
49589+ /* Check for 32-Bit Yukon with Low at TWSI-Data Pin */
49590+ SK_I2C_GET_SW(IoC, &I2cSwCtrl);
49591+
49592+ if ((I2cSwCtrl & I2C_DATA) == 0) {
49593+ /* this is a 32-Bit board */
49594+ pAC->GIni.GIYukon32Bit = SK_TRUE;
49595+ return(0);
49596+ }
49597+
49598+ /* Check for 64 Bit Yukon without sensors */
49599+ if (SkI2cWrite(pAC, IoC, 0, LM80_ADDR, I2C_025K_DEV, LM80_CFG, 0) != 0) {
49600+ return(0);
49601+ }
49602+
49603+ (void)SkI2cWrite(pAC, IoC, 0xffUL, LM80_ADDR, I2C_025K_DEV, LM80_IMSK_1, 0);
49604+
49605+ (void)SkI2cWrite(pAC, IoC, 0xffUL, LM80_ADDR, I2C_025K_DEV, LM80_IMSK_2, 0);
49606+
49607+ (void)SkI2cWrite(pAC, IoC, 0, LM80_ADDR, I2C_025K_DEV, LM80_FAN_CTRL, 0);
49608+
49609+ (void)SkI2cWrite(pAC, IoC, 0, LM80_ADDR, I2C_025K_DEV, LM80_TEMP_CTRL, 0);
49610+
49611+ (void)SkI2cWrite(pAC, IoC, (SK_U32)LM80_CFG_START, LM80_ADDR, I2C_025K_DEV,
49612+ LM80_CFG, 0);
49613+
49614+ /*
49615+ * MaxSens has to be updated here, because PhyType is not
49616+ * set when performing Init Level 0
49617+ */
49618+ pAC->I2c.MaxSens = 5;
49619+
49620+ pPrt = &pAC->GIni.GP[0];
49621+
49622+ if (pAC->GIni.GIGenesis) {
49623+ if (pPrt->PhyType == SK_PHY_BCOM) {
49624+ if (pAC->GIni.GIMacsFound == 1) {
49625+ pAC->I2c.MaxSens += 1;
49626+ }
49627+ else {
49628+ pAC->I2c.MaxSens += 3;
49629+ }
49630+ }
49631+ }
49632+ else {
49633+ pAC->I2c.MaxSens += 3;
49634+ }
49635+
49636+ for (i = 0; i < pAC->I2c.MaxSens; i++) {
49637+ pSen = &pAC->I2c.SenTable[i];
49638+ switch (i) {
49639+ case 0:
49640+ pSen->SenDesc = "Temperature";
49641+ pSen->SenType = SK_SEN_TEMP;
49642+ pSen->SenThreErrHigh = SK_SEN_TEMP_HIGH_ERR;
49643+ pSen->SenThreWarnHigh = SK_SEN_TEMP_HIGH_WARN;
49644+ pSen->SenThreWarnLow = SK_SEN_TEMP_LOW_WARN;
49645+ pSen->SenThreErrLow = SK_SEN_TEMP_LOW_ERR;
49646+ pSen->SenReg = LM80_TEMP_IN;
49647+ break;
49648+ case 1:
49649+ pSen->SenDesc = "Voltage PCI";
49650+ pSen->SenType = SK_SEN_VOLT;
49651+ pSen->SenThreErrHigh = SK_SEN_PCI_5V_HIGH_ERR;
49652+ pSen->SenThreWarnHigh = SK_SEN_PCI_5V_HIGH_WARN;
49653+ if (pAC->GIni.GIPciBus != SK_PEX_BUS) {
49654+ pSen->SenThreWarnLow = SK_SEN_PCI_5V_LOW_WARN;
49655+ pSen->SenThreErrLow = SK_SEN_PCI_5V_LOW_ERR;
49656+ }
49657+ else {
49658+ pSen->SenThreWarnLow = 0;
49659+ pSen->SenThreErrLow = 0;
49660+ }
49661+ pSen->SenReg = LM80_VT0_IN;
49662+ break;
49663+ case 2:
49664+ pSen->SenDesc = "Voltage PCI-IO";
49665+ pSen->SenType = SK_SEN_VOLT;
49666+ pSen->SenThreErrHigh = SK_SEN_PCI_IO_5V_HIGH_ERR;
49667+ pSen->SenThreWarnHigh = SK_SEN_PCI_IO_5V_HIGH_WARN;
49668+ if (pAC->GIni.GIPciBus != SK_PEX_BUS) {
49669+ pSen->SenThreWarnLow = SK_SEN_PCI_IO_3V3_LOW_WARN;
49670+ pSen->SenThreErrLow = SK_SEN_PCI_IO_3V3_LOW_ERR;
49671+ }
49672+ else {
49673+ pSen->SenThreWarnLow = 0;
49674+ pSen->SenThreErrLow = 0;
49675+ }
49676+ pSen->SenReg = LM80_VT1_IN;
49677+ pSen->SenInit = SK_SEN_DYN_INIT_PCI_IO;
49678+ break;
49679+ case 3:
49680+ if (pAC->GIni.GIGenesis) {
49681+ pSen->SenDesc = "Voltage ASIC";
49682+ }
49683+ else {
49684+ pSen->SenDesc = "Voltage VMAIN";
49685+ }
49686+ pSen->SenType = SK_SEN_VOLT;
49687+ pSen->SenThreErrHigh = SK_SEN_VDD_HIGH_ERR;
49688+ pSen->SenThreWarnHigh = SK_SEN_VDD_HIGH_WARN;
49689+ pSen->SenThreWarnLow = SK_SEN_VDD_LOW_WARN;
49690+ pSen->SenThreErrLow = SK_SEN_VDD_LOW_ERR;
49691+ pSen->SenReg = LM80_VT2_IN;
49692+ break;
49693+ case 4:
49694+ if (pAC->GIni.GIGenesis) {
49695+ if (pPrt->PhyType == SK_PHY_BCOM) {
49696+ pSen->SenDesc = "Voltage PHY A PLL";
49697+ pSen->SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR;
49698+ pSen->SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN;
49699+ pSen->SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN;
49700+ pSen->SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR;
49701+ }
49702+ else {
49703+ pSen->SenDesc = "Voltage PMA";
49704+ pSen->SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR;
49705+ pSen->SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN;
49706+ pSen->SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN;
49707+ pSen->SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR;
49708+ }
49709+ }
49710+ else {
49711+ pSen->SenDesc = "Voltage VAUX";
49712+ pSen->SenThreErrHigh = SK_SEN_VAUX_3V3_HIGH_ERR;
49713+ pSen->SenThreWarnHigh = SK_SEN_VAUX_3V3_HIGH_WARN;
49714+ if (pAC->GIni.GIVauxAvail) {
49715+ pSen->SenThreWarnLow = SK_SEN_VAUX_3V3_LOW_WARN;
49716+ pSen->SenThreErrLow = SK_SEN_VAUX_3V3_LOW_ERR;
49717+ }
49718+ else {
49719+ pSen->SenThreErrLow = 0;
49720+ pSen->SenThreWarnLow = 0;
49721+ }
49722+ }
49723+ pSen->SenType = SK_SEN_VOLT;
49724+ pSen->SenReg = LM80_VT3_IN;
49725+ break;
49726+ case 5:
49727+ if (CHIP_ID_YUKON_2(pAC)) {
49728+ if (pAC->GIni.GIChipRev == 0) {
49729+ pSen->SenDesc = "Voltage Core 1V3";
49730+ pSen->SenThreErrHigh = SK_SEN_CORE_1V3_HIGH_ERR;
49731+ pSen->SenThreWarnHigh = SK_SEN_CORE_1V3_HIGH_WARN;
49732+ pSen->SenThreWarnLow = SK_SEN_CORE_1V3_LOW_WARN;
49733+ pSen->SenThreErrLow = SK_SEN_CORE_1V3_LOW_ERR;
49734+ }
49735+ else {
49736+ pSen->SenDesc = "Voltage Core 1V2";
49737+ pSen->SenThreErrHigh = SK_SEN_CORE_1V2_HIGH_ERR;
49738+ pSen->SenThreWarnHigh = SK_SEN_CORE_1V2_HIGH_WARN;
49739+ pSen->SenThreWarnLow = SK_SEN_CORE_1V2_LOW_WARN;
49740+ pSen->SenThreErrLow = SK_SEN_CORE_1V2_LOW_ERR;
49741+ }
49742+ }
49743+ else {
49744+ if (pAC->GIni.GIGenesis) {
49745+ pSen->SenDesc = "Voltage PHY 2V5";
49746+ pSen->SenThreErrHigh = SK_SEN_PHY_2V5_HIGH_ERR;
49747+ pSen->SenThreWarnHigh = SK_SEN_PHY_2V5_HIGH_WARN;
49748+ pSen->SenThreWarnLow = SK_SEN_PHY_2V5_LOW_WARN;
49749+ pSen->SenThreErrLow = SK_SEN_PHY_2V5_LOW_ERR;
49750+ }
49751+ else {
49752+ pSen->SenDesc = "Voltage Core 1V5";
49753+ pSen->SenThreErrHigh = SK_SEN_CORE_1V5_HIGH_ERR;
49754+ pSen->SenThreWarnHigh = SK_SEN_CORE_1V5_HIGH_WARN;
49755+ pSen->SenThreWarnLow = SK_SEN_CORE_1V5_LOW_WARN;
49756+ pSen->SenThreErrLow = SK_SEN_CORE_1V5_LOW_ERR;
49757+ }
49758+ }
49759+ pSen->SenType = SK_SEN_VOLT;
49760+ pSen->SenReg = LM80_VT4_IN;
49761+ break;
49762+ case 6:
49763+ if (CHIP_ID_YUKON_2(pAC)) {
49764+ pSen->SenDesc = "Voltage PHY 1V5";
49765+ pSen->SenThreErrHigh = SK_SEN_CORE_1V5_HIGH_ERR;
49766+ pSen->SenThreWarnHigh = SK_SEN_CORE_1V5_HIGH_WARN;
49767+ if (pAC->GIni.GIPciBus == SK_PEX_BUS) {
49768+ pSen->SenThreWarnLow = SK_SEN_CORE_1V5_LOW_WARN;
49769+ pSen->SenThreErrLow = SK_SEN_CORE_1V5_LOW_ERR;
49770+ }
49771+ else {
49772+ pSen->SenThreWarnLow = 0;
49773+ pSen->SenThreErrLow = 0;
49774+ }
49775+ }
49776+ else {
49777+ if (pAC->GIni.GIGenesis) {
49778+ pSen->SenDesc = "Voltage PHY B PLL";
49779+ }
49780+ else {
49781+ pSen->SenDesc = "Voltage PHY 3V3";
49782+ }
49783+ pSen->SenThreErrHigh = SK_SEN_PLL_3V3_HIGH_ERR;
49784+ pSen->SenThreWarnHigh = SK_SEN_PLL_3V3_HIGH_WARN;
49785+ pSen->SenThreWarnLow = SK_SEN_PLL_3V3_LOW_WARN;
49786+ pSen->SenThreErrLow = SK_SEN_PLL_3V3_LOW_ERR;
49787+ }
49788+ pSen->SenType = SK_SEN_VOLT;
49789+ pSen->SenReg = LM80_VT5_IN;
49790+ break;
49791+ case 7:
49792+ if (pAC->GIni.GIGenesis) {
49793+ pSen->SenDesc = "Speed Fan";
49794+ pSen->SenType = SK_SEN_FAN;
49795+ pSen->SenThreErrHigh = SK_SEN_FAN_HIGH_ERR;
49796+ pSen->SenThreWarnHigh = SK_SEN_FAN_HIGH_WARN;
49797+ pSen->SenThreWarnLow = SK_SEN_FAN_LOW_WARN;
49798+ pSen->SenThreErrLow = SK_SEN_FAN_LOW_ERR;
49799+ pSen->SenReg = LM80_FAN2_IN;
49800+ }
49801+ else {
49802+ pSen->SenDesc = "Voltage PHY 2V5";
49803+ pSen->SenType = SK_SEN_VOLT;
49804+ pSen->SenThreErrHigh = SK_SEN_PHY_2V5_HIGH_ERR;
49805+ pSen->SenThreWarnHigh = SK_SEN_PHY_2V5_HIGH_WARN;
49806+ pSen->SenThreWarnLow = SK_SEN_PHY_2V5_LOW_WARN;
49807+ pSen->SenThreErrLow = SK_SEN_PHY_2V5_LOW_ERR;
49808+ pSen->SenReg = LM80_VT6_IN;
49809+ }
49810+ break;
49811+ default:
49812+ SK_ERR_LOG(pAC, SK_ERRCL_INIT | SK_ERRCL_SW,
49813+ SKERR_I2C_E001, SKERR_I2C_E001MSG);
49814+ break;
49815+ }
49816+
49817+ pSen->SenValue = 0;
49818+ pSen->SenErrFlag = SK_SEN_ERR_OK;
49819+ pSen->SenErrCts = 0;
49820+ pSen->SenBegErrTS = 0;
49821+ pSen->SenState = SK_SEN_IDLE;
49822+ if (pSen->SenThreWarnLow != 0) {
49823+ pSen->SenRead = SkLm80ReadSensor;
49824+ }
49825+ pSen->SenDev = LM80_ADDR;
49826+ }
49827+
49828+#ifndef SK_DIAG
49829+ pAC->I2c.DummyReads = pAC->I2c.MaxSens;
49830+#endif /* !SK_DIAG */
49831+
49832+ /* Clear TWSI IRQ */
49833+ SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
49834+
49835+ /* Now we are I/O initialized */
49836+ pAC->I2c.InitLevel = SK_INIT_IO;
49837+ return(0);
49838+} /* SkI2cInit1 */
49839+
49840+
49841+/*
49842+ * Init level 2: Start first sensor read.
49843+ */
49844+static int SkI2cInit2(
49845+SK_AC *pAC, /* Adapter Context */
49846+SK_IOC IoC) /* I/O Context */
49847+{
49848+ int ReadComplete;
49849+ SK_SENSOR *pSen;
49850+
49851+ if (pAC->I2c.InitLevel != SK_INIT_IO) {
49852+ /* ReInit not needed in TWSI module */
49853+ /* Init0 and Init2 not permitted */
49854+ return(0);
49855+ }
49856+
49857+ pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
49858+
49859+ ReadComplete = SkI2cReadSensor(pAC, IoC, pSen);
49860+
49861+ if (ReadComplete) {
49862+ SK_ERR_LOG(pAC, SK_ERRCL_INIT, SKERR_I2C_E008, SKERR_I2C_E008MSG);
49863+ }
49864+
49865+ /* Now we are correctly initialized */
49866+ pAC->I2c.InitLevel = SK_INIT_RUN;
49867+
49868+ return(0);
49869+} /* SkI2cInit2*/
49870+
49871+
49872+/*
49873+ * Initialize TWSI devices
49874+ *
49875+ * Get the first voltage value and discard it.
49876+ * Go into temperature read mode. A default pointer is not set.
49877+ *
49878+ * The things to be done depend on the init level in the parameter list:
49879+ * Level 0:
49880+ * Initialize only the data structures. Do NOT access hardware.
49881+ * Level 1:
49882+ * Initialize hardware through SK_IN / SK_OUT commands. Do NOT use interrupts.
49883+ * Level 2:
49884+ * Everything is possible. Interrupts may be used from now on.
49885+ *
49886+ * return:
49887+ * 0 = success
49888+ * other = error.
49889+ */
49890+int SkI2cInit(
49891+SK_AC *pAC, /* Adapter Context */
49892+SK_IOC IoC, /* I/O Context needed in levels 1 and 2 */
49893+int Level) /* Init Level */
49894+{
49895+
49896+ switch (Level) {
49897+ case SK_INIT_DATA:
49898+ return(SkI2cInit0(pAC));
49899+ case SK_INIT_IO:
49900+ return(SkI2cInit1(pAC, IoC));
49901+ case SK_INIT_RUN:
49902+ return(SkI2cInit2(pAC, IoC));
49903+ default:
49904+ break;
49905+ }
49906+
49907+ return(0);
49908+} /* SkI2cInit */
49909+
49910+
49911+#ifndef SK_DIAG
49912+/*
49913+ * Interrupt service function for the TWSI Interface
49914+ *
49915+ * Clears the Interrupt source
49916+ *
49917+ * Reads the register and check it for sending a trap.
49918+ *
49919+ * Starts the timer if necessary.
49920+ */
49921+void SkI2cIsr(
49922+SK_AC *pAC, /* Adapter Context */
49923+SK_IOC IoC) /* I/O Context */
49924+{
49925+ SK_EVPARA Para;
49926+
49927+ /* Clear TWSI IRQ */
49928+ SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
49929+
49930+ Para.Para64 = 0;
49931+ SkEventQueue(pAC, SKGE_I2C, SK_I2CEV_IRQ, Para);
49932+} /* SkI2cIsr */
49933+
49934+
49935+/*
49936+ * Check this sensors Value against the threshold and send events.
49937+ */
49938+static void SkI2cCheckSensor(
49939+SK_AC *pAC, /* Adapter Context */
49940+SK_SENSOR *pSen)
49941+{
49942+ SK_EVPARA ParaLocal;
49943+ SK_BOOL TooHigh; /* Is sensor too high? */
49944+ SK_BOOL TooLow; /* Is sensor too low? */
49945+ SK_U64 CurrTime; /* Current Time */
49946+ SK_BOOL DoTrapSend; /* We need to send a trap */
49947+ SK_BOOL DoErrLog; /* We need to log the error */
49948+ SK_BOOL IsError; /* Error occured */
49949+
49950+ /* Check Dummy Reads first */
49951+ if (pAC->I2c.DummyReads > 0) {
49952+ pAC->I2c.DummyReads--;
49953+ return;
49954+ }
49955+
49956+ /* Get the current time */
49957+ CurrTime = SkOsGetTime(pAC);
49958+
49959+ /* Set para to the most useful setting: The current sensor. */
49960+ ParaLocal.Para64 = (SK_U64)pAC->I2c.CurrSens;
49961+
49962+ /* Check the Value against the thresholds. First: Error Thresholds */
49963+ TooHigh = pSen->SenValue > pSen->SenThreErrHigh;
49964+ TooLow = pSen->SenValue < pSen->SenThreErrLow;
49965+
49966+ IsError = SK_FALSE;
49967+
49968+ if (TooHigh || TooLow) {
49969+ /* Error condition is satisfied */
49970+ DoTrapSend = SK_TRUE;
49971+ DoErrLog = SK_TRUE;
49972+
49973+ /* Now error condition is satisfied */
49974+ IsError = SK_TRUE;
49975+
49976+ if (pSen->SenErrFlag == SK_SEN_ERR_ERR) {
49977+ /* This state is the former one */
49978+
49979+ /* So check first whether we have to send a trap */
49980+ if (pSen->SenLastErrTrapTS + SK_SEN_ERR_TR_HOLD > CurrTime) {
49981+ /*
49982+ * Do NOT send the Trap. The hold back time
49983+ * has to run out first.
49984+ */
49985+ DoTrapSend = SK_FALSE;
49986+ }
49987+
49988+ /* Check now whether we have to log an Error */
49989+ if (pSen->SenLastErrLogTS + SK_SEN_ERR_LOG_HOLD > CurrTime) {
49990+ /*
49991+ * Do NOT log the error. The hold back time
49992+ * has to run out first.
49993+ */
49994+ DoErrLog = SK_FALSE;
49995+ }
49996+ }
49997+ else {
49998+ /* We came from a different state -> Set Begin Time Stamp */
49999+ pSen->SenBegErrTS = CurrTime;
50000+ pSen->SenErrFlag = SK_SEN_ERR_ERR;
50001+ }
50002+
50003+ if (DoTrapSend) {
50004+ /* Set current Time */
50005+ pSen->SenLastErrTrapTS = CurrTime;
50006+ pSen->SenErrCts++;
50007+
50008+ /* Queue PNMI Event */
50009+ SkEventQueue(pAC, SKGE_PNMI, TooHigh ?
50010+ SK_PNMI_EVT_SEN_ERR_UPP : SK_PNMI_EVT_SEN_ERR_LOW,
50011+ ParaLocal);
50012+ }
50013+
50014+ if (DoErrLog) {
50015+ /* Set current Time */
50016+ pSen->SenLastErrLogTS = CurrTime;
50017+
50018+ if (pSen->SenType == SK_SEN_TEMP) {
50019+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E011, SKERR_I2C_E011MSG);
50020+ }
50021+ else if (pSen->SenType == SK_SEN_VOLT) {
50022+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E012, SKERR_I2C_E012MSG);
50023+ }
50024+ else {
50025+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E015, SKERR_I2C_E015MSG);
50026+ }
50027+ }
50028+ }
50029+
50030+ /* Check the Value against the thresholds */
50031+ /* 2nd: Warning thresholds */
50032+ TooHigh = pSen->SenValue > pSen->SenThreWarnHigh;
50033+ TooLow = pSen->SenValue < pSen->SenThreWarnLow;
50034+
50035+ if (!IsError && (TooHigh || TooLow)) {
50036+ /* Error condition is satisfied */
50037+ DoTrapSend = SK_TRUE;
50038+ DoErrLog = SK_TRUE;
50039+
50040+ if (pSen->SenErrFlag == SK_SEN_ERR_WARN) {
50041+ /* This state is the former one */
50042+
50043+ /* So check first whether we have to send a trap */
50044+ if (pSen->SenLastWarnTrapTS + SK_SEN_WARN_TR_HOLD > CurrTime) {
50045+ /*
50046+ * Do NOT send the Trap. The hold back time
50047+ * has to run out first.
50048+ */
50049+ DoTrapSend = SK_FALSE;
50050+ }
50051+
50052+ /* Check now whether we have to log an Error */
50053+ if (pSen->SenLastWarnLogTS + SK_SEN_WARN_LOG_HOLD > CurrTime) {
50054+ /*
50055+ * Do NOT log the error. The hold back time
50056+ * has to run out first.
50057+ */
50058+ DoErrLog = SK_FALSE;
50059+ }
50060+ }
50061+ else {
50062+ /* We came from a different state -> Set Begin Time Stamp */
50063+ pSen->SenBegWarnTS = CurrTime;
50064+ pSen->SenErrFlag = SK_SEN_ERR_WARN;
50065+ }
50066+
50067+ if (DoTrapSend) {
50068+ /* Set current Time */
50069+ pSen->SenLastWarnTrapTS = CurrTime;
50070+ pSen->SenWarnCts++;
50071+
50072+ /* Queue PNMI Event */
50073+ SkEventQueue(pAC, SKGE_PNMI, TooHigh ?
50074+ SK_PNMI_EVT_SEN_WAR_UPP : SK_PNMI_EVT_SEN_WAR_LOW, ParaLocal);
50075+ }
50076+
50077+ if (DoErrLog) {
50078+ /* Set current Time */
50079+ pSen->SenLastWarnLogTS = CurrTime;
50080+
50081+ if (pSen->SenType == SK_SEN_TEMP) {
50082+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E009, SKERR_I2C_E009MSG);
50083+ }
50084+ else if (pSen->SenType == SK_SEN_VOLT) {
50085+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E010, SKERR_I2C_E010MSG);
50086+ }
50087+ else {
50088+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E014, SKERR_I2C_E014MSG);
50089+ }
50090+ }
50091+ }
50092+
50093+ /* Check for NO error at all */
50094+ if (!IsError && !TooHigh && !TooLow) {
50095+ /* Set o.k. Status if no error and no warning condition */
50096+ pSen->SenErrFlag = SK_SEN_ERR_OK;
50097+ }
50098+
50099+ /* End of check against the thresholds */
50100+
50101+ if (pSen->SenInit == SK_SEN_DYN_INIT_PCI_IO) {
50102+ /* Bug fix AF: 16.Aug.2001: Correct the init base of LM80 sensor */
50103+ pSen->SenInit = SK_SEN_DYN_INIT_NONE;
50104+
50105+ if (pSen->SenValue > SK_SEN_PCI_IO_RANGE_LIMITER) {
50106+ /* 5V PCI-IO Voltage */
50107+ pSen->SenThreWarnLow = SK_SEN_PCI_IO_5V_LOW_WARN;
50108+ pSen->SenThreErrLow = SK_SEN_PCI_IO_5V_LOW_ERR;
50109+ }
50110+ else {
50111+ /* 3.3V PCI-IO Voltage */
50112+ pSen->SenThreWarnHigh = SK_SEN_PCI_IO_3V3_HIGH_WARN;
50113+ pSen->SenThreErrHigh = SK_SEN_PCI_IO_3V3_HIGH_ERR;
50114+ }
50115+ }
50116+
50117+#ifdef TEST_ONLY
50118+ /* Dynamic thresholds also for VAUX of LM80 sensor */
50119+ if (pSen->SenInit == SK_SEN_DYN_INIT_VAUX) {
50120+
50121+ pSen->SenInit = SK_SEN_DYN_INIT_NONE;
50122+
50123+ /* 3.3V VAUX Voltage */
50124+ if (pSen->SenValue > SK_SEN_VAUX_RANGE_LIMITER) {
50125+ pSen->SenThreWarnLow = SK_SEN_VAUX_3V3_LOW_WARN;
50126+ pSen->SenThreErrLow = SK_SEN_VAUX_3V3_LOW_ERR;
50127+ }
50128+ /* 0V VAUX Voltage */
50129+ else {
50130+ pSen->SenThreWarnHigh = SK_SEN_VAUX_0V_WARN_ERR;
50131+ pSen->SenThreErrHigh = SK_SEN_VAUX_0V_WARN_ERR;
50132+ }
50133+ }
50134+
50135+ /* Check initialization state: the VIO Thresholds need adaption */
50136+ if (!pSen->SenInit && pSen->SenReg == LM80_VT1_IN &&
50137+ pSen->SenValue > SK_SEN_WARNLOW2C &&
50138+ pSen->SenValue < SK_SEN_WARNHIGH2) {
50139+
50140+ pSen->SenThreErrLow = SK_SEN_ERRLOW2C;
50141+ pSen->SenThreWarnLow = SK_SEN_WARNLOW2C;
50142+ pSen->SenInit = SK_TRUE;
50143+ }
50144+
50145+ if (!pSen->SenInit && pSen->SenReg == LM80_VT1_IN &&
50146+ pSen->SenValue > SK_SEN_WARNLOW2 &&
50147+ pSen->SenValue < SK_SEN_WARNHIGH2C) {
50148+
50149+ pSen->SenThreErrHigh = SK_SEN_ERRHIGH2C;
50150+ pSen->SenThreWarnHigh = SK_SEN_WARNHIGH2C;
50151+ pSen->SenInit = SK_TRUE;
50152+ }
50153+#endif
50154+
50155+ if (pSen->SenInit != SK_SEN_DYN_INIT_NONE) {
50156+ SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_I2C_E013, SKERR_I2C_E013MSG);
50157+ }
50158+} /* SkI2cCheckSensor */
50159+
50160+
50161+/*
50162+ * The only Event to be served is the timeout event
50163+ *
50164+ */
50165+int SkI2cEvent(
50166+SK_AC *pAC, /* Adapter Context */
50167+SK_IOC IoC, /* I/O Context */
50168+SK_U32 Event, /* Module specific Event */
50169+SK_EVPARA Para) /* Event specific Parameter */
50170+{
50171+ int ReadComplete;
50172+ SK_SENSOR *pSen;
50173+ SK_U32 Time;
50174+ SK_EVPARA ParaLocal;
50175+ int i;
50176+
50177+ /* New case: no sensors */
50178+ if (pAC->I2c.MaxSens == 0) {
50179+ return(0);
50180+ }
50181+
50182+ switch (Event) {
50183+ case SK_I2CEV_IRQ:
50184+ pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
50185+ ReadComplete = SkI2cReadSensor(pAC, IoC, pSen);
50186+
50187+ if (ReadComplete) {
50188+ /* Check sensor against defined thresholds */
50189+ SkI2cCheckSensor(pAC, pSen);
50190+
50191+ /* Increment Current sensor and set appropriate Timeout */
50192+ pAC->I2c.CurrSens++;
50193+ if (pAC->I2c.CurrSens >= pAC->I2c.MaxSens) {
50194+ pAC->I2c.CurrSens = 0;
50195+ Time = SK_I2C_TIM_LONG;
50196+ }
50197+ else {
50198+ Time = SK_I2C_TIM_SHORT;
50199+ }
50200+
50201+ /* Start Timer */
50202+ ParaLocal.Para64 = (SK_U64)0;
50203+
50204+ pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING;
50205+
50206+ SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time,
50207+ SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
50208+ }
50209+ else {
50210+ /* Start Timer */
50211+ ParaLocal.Para64 = (SK_U64)0;
50212+
50213+ pAC->I2c.TimerMode = SK_TIMER_WATCH_SM;
50214+
50215+ SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, SK_I2C_TIM_WATCH,
50216+ SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
50217+ }
50218+ break;
50219+ case SK_I2CEV_TIM:
50220+ if (pAC->I2c.TimerMode == SK_TIMER_NEW_GAUGING) {
50221+
50222+ ParaLocal.Para64 = (SK_U64)0;
50223+ SkTimerStop(pAC, IoC, &pAC->I2c.SenTimer);
50224+
50225+ pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
50226+ ReadComplete = SkI2cReadSensor(pAC, IoC, pSen);
50227+
50228+ if (ReadComplete) {
50229+ /* Check sensor against defined thresholds */
50230+ SkI2cCheckSensor(pAC, pSen);
50231+
50232+ /* Increment Current sensor and set appropriate Timeout */
50233+ pAC->I2c.CurrSens++;
50234+ if (pAC->I2c.CurrSens == pAC->I2c.MaxSens) {
50235+ pAC->I2c.CurrSens = 0;
50236+ Time = SK_I2C_TIM_LONG;
50237+ }
50238+ else {
50239+ Time = SK_I2C_TIM_SHORT;
50240+ }
50241+
50242+ /* Start Timer */
50243+ ParaLocal.Para64 = (SK_U64)0;
50244+
50245+ pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING;
50246+
50247+ SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time,
50248+ SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
50249+ }
50250+ }
50251+ else {
50252+ pSen = &pAC->I2c.SenTable[pAC->I2c.CurrSens];
50253+ pSen->SenErrFlag = SK_SEN_ERR_FAULTY;
50254+ SK_I2C_STOP(IoC);
50255+
50256+ /* Increment Current sensor and set appropriate Timeout */
50257+ pAC->I2c.CurrSens++;
50258+ if (pAC->I2c.CurrSens == pAC->I2c.MaxSens) {
50259+ pAC->I2c.CurrSens = 0;
50260+ Time = SK_I2C_TIM_LONG;
50261+ }
50262+ else {
50263+ Time = SK_I2C_TIM_SHORT;
50264+ }
50265+
50266+ /* Start Timer */
50267+ ParaLocal.Para64 = (SK_U64)0;
50268+
50269+ pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING;
50270+
50271+ SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time,
50272+ SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
50273+ }
50274+ break;
50275+ case SK_I2CEV_CLEAR:
50276+ for (i = 0; i < SK_MAX_SENSORS; i++) {
50277+ pSen = &pAC->I2c.SenTable[i];
50278+
50279+ pSen->SenErrFlag = SK_SEN_ERR_OK;
50280+ pSen->SenErrCts = 0;
50281+ pSen->SenWarnCts = 0;
50282+ pSen->SenBegErrTS = 0;
50283+ pSen->SenBegWarnTS = 0;
50284+ pSen->SenLastErrTrapTS = (SK_U64)0;
50285+ pSen->SenLastErrLogTS = (SK_U64)0;
50286+ pSen->SenLastWarnTrapTS = (SK_U64)0;
50287+ pSen->SenLastWarnLogTS = (SK_U64)0;
50288+ }
50289+ break;
50290+ default:
50291+ SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E006, SKERR_I2C_E006MSG);
50292+ }
50293+
50294+ return(0);
50295+} /* SkI2cEvent*/
50296+
50297+#endif /* !SK_DIAG */
50298+
50299diff -ruN linux/drivers/net/sk98lin/skvpd.c linux-new/drivers/net/sk98lin/skvpd.c
50300--- linux/drivers/net/sk98lin/skvpd.c 2006-04-11 19:19:28.000000000 +0200
50301+++ linux-new/drivers/net/sk98lin/skvpd.c 2006-01-18 14:37:24.000000000 +0100
50302@@ -1,22 +1,22 @@
50303 /******************************************************************************
50304 *
50305 * Name: skvpd.c
50306- * Project: GEnesis, PCI Gigabit Ethernet Adapter
50307- * Version: $Revision$
50308- * Date: $Date$
50309- * Purpose: Shared software to read and write VPD data
50310+ * Project: Gigabit Ethernet Adapters, VPD-Module
50311+ * Version: $Revision$
50312+ * Date: $Date$
50313+ * Purpose: Shared software to read and write VPD
50314 *
50315 ******************************************************************************/
50316
50317 /******************************************************************************
50318 *
50319- * (C)Copyright 1998-2003 SysKonnect GmbH.
50320+ * (C)Copyright 1998-2002 SysKonnect.
50321+ * (C)Copyright 2002-2004 Marvell.
50322 *
50323 * This program is free software; you can redistribute it and/or modify
50324 * it under the terms of the GNU General Public License as published by
50325 * the Free Software Foundation; either version 2 of the License, or
50326 * (at your option) any later version.
50327- *
50328 * The information in this file is provided "AS IS" without warranty.
50329 *
50330 ******************************************************************************/
50331@@ -25,7 +25,7 @@
50332 Please refer skvpd.txt for infomation how to include this module
50333 */
50334 static const char SysKonnectFileId[] =
50335- "@(#)$Id$ (C) SK";
50336+ "@(#) $Id$ (C) Marvell.";
50337
50338 #include "h/skdrv1st.h"
50339 #include "h/sktypes.h"
50340@@ -59,9 +59,10 @@
50341 SK_U64 start_time;
50342 SK_U16 state;
50343
50344- SK_DBG_MSG(pAC,SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
50345+ SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
50346 ("VPD wait for %s\n", event?"Write":"Read"));
50347 start_time = SkOsGetTime(pAC);
50348+
50349 do {
50350 if (SkOsGetTime(pAC) - start_time > SK_TICKS_PER_SEC) {
50351
50352@@ -81,17 +82,18 @@
50353 ("ERROR:VPD wait timeout\n"));
50354 return(1);
50355 }
50356-
50357+
50358 VPD_IN16(pAC, IoC, PCI_VPD_ADR_REG, &state);
50359-
50360+
50361 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
50362 ("state = %x, event %x\n",state,event));
50363- } while((int)(state & PCI_VPD_FLAG) == event);
50364+ } while ((int)(state & PCI_VPD_FLAG) == event);
50365
50366 return(0);
50367 }
50368
50369-#ifdef SKDIAG
50370+
50371+#ifdef SK_DIAG
50372
50373 /*
50374 * Read the dword at address 'addr' from the VPD EEPROM.
50375@@ -124,16 +126,15 @@
50376 Rtv = 0;
50377
50378 VPD_IN32(pAC, IoC, PCI_VPD_DAT_REG, &Rtv);
50379-
50380+
50381 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
50382 ("VPD read dword data = 0x%x\n",Rtv));
50383 return(Rtv);
50384 }
50385+#endif /* SK_DIAG */
50386
50387-#endif /* SKDIAG */
50388-
50389-#if 0
50390
50391+#ifdef XXX
50392 /*
50393 Write the dword 'data' at address 'addr' into the VPD EEPROM, and
50394 verify that the data is written.
50395@@ -151,7 +152,6 @@
50396 . over all 3.8 ms 13.2 ms
50397 .
50398
50399-
50400 Returns 0: success
50401 1: error, I2C transfer does not terminate
50402 2: error, data verify error
50403@@ -189,7 +189,8 @@
50404 return(0);
50405 } /* VpdWriteDWord */
50406
50407-#endif /* 0 */
50408+#endif /* XXX */
50409+
50410
50411 /*
50412 * Read one Stream of 'len' bytes of VPD data, starting at 'addr' from
50413@@ -215,7 +216,7 @@
50414 pComp = (SK_U8 *) buf;
50415
50416 for (i = 0; i < Len; i++, buf++) {
50417- if ((i%sizeof(SK_U32)) == 0) {
50418+ if ((i % SZ_LONG) == 0) {
50419 /*
50420 * At the begin of each cycle read the Data Reg
50421 * So it is initialized even if only a few bytes
50422@@ -233,14 +234,13 @@
50423 }
50424 }
50425
50426- /* Write current Byte */
50427- VPD_OUT8(pAC, IoC, PCI_VPD_DAT_REG + (i%sizeof(SK_U32)),
50428- *(SK_U8*)buf);
50429+ /* Write current byte */
50430+ VPD_OUT8(pAC, IoC, PCI_VPD_DAT_REG + (i % SZ_LONG), *(SK_U8*)buf);
50431
50432- if (((i%sizeof(SK_U32)) == 3) || (i == (Len - 1))) {
50433+ if (((i % SZ_LONG) == 3) || (i == (Len - 1))) {
50434 /* New Address needs to be written to VPD_ADDR reg */
50435 AdrReg = (SK_U16) Addr;
50436- Addr += sizeof(SK_U32);
50437+ Addr += SZ_LONG;
50438 AdrReg |= VPD_WRITE; /* WRITE operation */
50439
50440 VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, AdrReg);
50441@@ -250,7 +250,7 @@
50442 if (Rtv != 0) {
50443 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
50444 ("Write Timed Out\n"));
50445- return(i - (i%sizeof(SK_U32)));
50446+ return(i - (i % SZ_LONG));
50447 }
50448
50449 /*
50450@@ -265,18 +265,18 @@
50451 if (Rtv != 0) {
50452 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
50453 ("Verify Timed Out\n"));
50454- return(i - (i%sizeof(SK_U32)));
50455+ return(i - (i % SZ_LONG));
50456 }
50457
50458- for (j = 0; j <= (int)(i%sizeof(SK_U32)); j++, pComp++) {
50459-
50460+ for (j = 0; j <= (int)(i % SZ_LONG); j++, pComp++) {
50461+
50462 VPD_IN8(pAC, IoC, PCI_VPD_DAT_REG + j, &Data);
50463-
50464+
50465 if (Data != *pComp) {
50466 /* Verify Error */
50467 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
50468 ("WriteStream Verify Error\n"));
50469- return(i - (i%sizeof(SK_U32)) + j);
50470+ return(i - (i % SZ_LONG) + j);
50471 }
50472 }
50473 }
50474@@ -284,7 +284,7 @@
50475
50476 return(Len);
50477 }
50478-
50479+
50480
50481 /*
50482 * Read one Stream of 'len' bytes of VPD data, starting at 'addr' from
50483@@ -304,10 +304,10 @@
50484 int Rtv;
50485
50486 for (i = 0; i < Len; i++, buf++) {
50487- if ((i%sizeof(SK_U32)) == 0) {
50488+ if ((i % SZ_LONG) == 0) {
50489 /* New Address needs to be written to VPD_ADDR reg */
50490 AdrReg = (SK_U16) Addr;
50491- Addr += sizeof(SK_U32);
50492+ Addr += SZ_LONG;
50493 AdrReg &= ~VPD_WRITE; /* READ operation */
50494
50495 VPD_OUT16(pAC, IoC, PCI_VPD_ADR_REG, AdrReg);
50496@@ -318,13 +318,13 @@
50497 return(i);
50498 }
50499 }
50500- VPD_IN8(pAC, IoC, PCI_VPD_DAT_REG + (i%sizeof(SK_U32)),
50501- (SK_U8 *)buf);
50502+ VPD_IN8(pAC, IoC, PCI_VPD_DAT_REG + (i % SZ_LONG), (SK_U8 *)buf);
50503 }
50504
50505 return(Len);
50506 }
50507
50508+
50509 /*
50510 * Read ore writes 'len' bytes of VPD data, starting at 'addr' from
50511 * or to the I2C EEPROM.
50512@@ -350,14 +350,14 @@
50513 return(0);
50514
50515 vpd_rom_size = pAC->vpd.rom_size;
50516-
50517+
50518 if (addr > vpd_rom_size - 4) {
50519 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
50520 ("Address error: 0x%x, exp. < 0x%x\n",
50521 addr, vpd_rom_size - 4));
50522 return(0);
50523 }
50524-
50525+
50526 if (addr + len > vpd_rom_size) {
50527 len = vpd_rom_size - addr;
50528 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
50529@@ -374,8 +374,8 @@
50530 return(Rtv);
50531 }
50532
50533-#ifdef SKDIAG
50534
50535+#if defined (SK_DIAG) || defined (SK_ASF)
50536 /*
50537 * Read 'len' bytes of VPD data, starting at 'addr'.
50538 *
50539@@ -391,6 +391,7 @@
50540 return(VpdTransferBlock(pAC, IoC, buf, addr, len, VPD_READ));
50541 }
50542
50543+
50544 /*
50545 * Write 'len' bytes of *but to the VPD EEPROM, starting at 'addr'.
50546 *
50547@@ -405,18 +406,27 @@
50548 {
50549 return(VpdTransferBlock(pAC, IoC, buf, addr, len, VPD_WRITE));
50550 }
50551-#endif /* SKDIAG */
50552+#endif /* SK_DIAG */
50553
50554-/*
50555- * (re)initialize the VPD buffer
50556+
50557+/******************************************************************************
50558 *
50559- * Reads the VPD data from the EEPROM into the VPD buffer.
50560- * Get the remaining read only and read / write space.
50561+ * VpdInit() - (re)initialize the VPD buffer
50562 *
50563- * return 0: success
50564- * 1: fatal VPD error
50565+ * Description:
50566+ * Reads the VPD data from the EEPROM into the VPD buffer.
50567+ * Get the remaining read only and read / write space.
50568+ *
50569+ * Note:
50570+ * This is a local function and should be used locally only.
50571+ * However, the ASF module needs to use this function also.
50572+ * Therfore it has been published.
50573+ *
50574+ * Returns:
50575+ * 0: success
50576+ * 1: fatal VPD error
50577 */
50578-static int VpdInit(
50579+int VpdInit(
50580 SK_AC *pAC, /* Adapters context */
50581 SK_IOC IoC) /* IO Context */
50582 {
50583@@ -427,14 +437,14 @@
50584 SK_U16 dev_id;
50585 SK_U32 our_reg2;
50586
50587- SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_INIT, ("VpdInit .. "));
50588-
50589+ SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_INIT, ("VpdInit ... "));
50590+
50591 VPD_IN16(pAC, IoC, PCI_DEVICE_ID, &dev_id);
50592-
50593+
50594 VPD_IN32(pAC, IoC, PCI_OUR_REG_2, &our_reg2);
50595-
50596+
50597 pAC->vpd.rom_size = 256 << ((our_reg2 & PCI_VPD_ROM_SZ) >> 14);
50598-
50599+
50600 /*
50601 * this function might get used before the hardware is initialized
50602 * therefore we cannot always trust in GIChipId
50603@@ -465,19 +475,15 @@
50604 ("Block Read Error\n"));
50605 return(1);
50606 }
50607-
50608+
50609 pAC->vpd.vpd_size = vpd_size;
50610
50611 /* Asus K8V Se Deluxe bugfix. Correct VPD content */
50612- /* MBo April 2004 */
50613- if (((unsigned char)pAC->vpd.vpd_buf[0x3f] == 0x38) &&
50614- ((unsigned char)pAC->vpd.vpd_buf[0x40] == 0x3c) &&
50615- ((unsigned char)pAC->vpd.vpd_buf[0x41] == 0x45)) {
50616- printk("sk98lin: Asus mainboard with buggy VPD? "
50617- "Correcting data.\n");
50618- pAC->vpd.vpd_buf[0x40] = 0x38;
50619- }
50620+ i = 62;
50621+ if (!SK_STRNCMP(pAC->vpd.vpd_buf + i, " 8<E", 4)) {
50622
50623+ pAC->vpd.vpd_buf[i + 2] = '8';
50624+ }
50625
50626 /* find the end tag of the RO area */
50627 if (!(r = vpd_find_para(pAC, VPD_RV, &rp))) {
50628@@ -485,9 +491,9 @@
50629 ("Encoding Error: RV Tag not found\n"));
50630 return(1);
50631 }
50632-
50633+
50634 if (r->p_val + r->p_len > pAC->vpd.vpd_buf + vpd_size/2) {
50635- SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
50636+ SK_DBG_MSG(pAC, SK_DBGMOD_VPD,SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
50637 ("Encoding Error: Invalid VPD struct size\n"));
50638 return(1);
50639 }
50640@@ -497,7 +503,7 @@
50641 for (i = 0, x = 0; (unsigned)i <= (unsigned)vpd_size/2 - r->p_len; i++) {
50642 x += pAC->vpd.vpd_buf[i];
50643 }
50644-
50645+
50646 if (x != 0) {
50647 /* checksum error */
50648 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
50649@@ -511,7 +517,7 @@
50650 ("Encoding Error: RV Tag not found\n"));
50651 return(1);
50652 }
50653-
50654+
50655 if (r->p_val < pAC->vpd.vpd_buf + vpd_size/2) {
50656 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
50657 ("Encoding Error: Invalid VPD struct size\n"));
50658@@ -531,6 +537,7 @@
50659 return(0);
50660 }
50661
50662+
50663 /*
50664 * find the Keyword 'key' in the VPD buffer and fills the
50665 * parameter struct 'p' with it's values
50666@@ -541,7 +548,7 @@
50667 static SK_VPD_PARA *vpd_find_para(
50668 SK_AC *pAC, /* common data base */
50669 const char *key, /* keyword to find (e.g. "MN") */
50670-SK_VPD_PARA *p) /* parameter description struct */
50671+SK_VPD_PARA *p) /* parameter description struct */
50672 {
50673 char *v ; /* points to VPD buffer */
50674 int max; /* Maximum Number of Iterations */
50675@@ -556,10 +563,10 @@
50676 if (*v != (char)RES_ID) {
50677 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
50678 ("Error: 0x%x missing\n", RES_ID));
50679- return NULL;
50680+ return(0);
50681 }
50682
50683- if (strcmp(key, VPD_NAME) == 0) {
50684+ if (SK_STRCMP(key, VPD_NAME) == 0) {
50685 p->p_len = VPD_GET_RES_LEN(v);
50686 p->p_val = VPD_GET_VAL(v);
50687 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
50688@@ -569,7 +576,7 @@
50689
50690 v += 3 + VPD_GET_RES_LEN(v) + 3;
50691 for (;; ) {
50692- if (SK_MEMCMP(key,v,2) == 0) {
50693+ if (SK_MEMCMP(key, v, 2) == 0) {
50694 p->p_len = VPD_GET_VPD_LEN(v);
50695 p->p_val = VPD_GET_VAL(v);
50696 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
50697@@ -579,11 +586,11 @@
50698
50699 /* exit when reaching the "RW" Tag or the maximum of itera. */
50700 max--;
50701- if (SK_MEMCMP(VPD_RW,v,2) == 0 || max == 0) {
50702+ if (SK_MEMCMP(VPD_RW, v, 2) == 0 || max == 0) {
50703 break;
50704 }
50705
50706- if (SK_MEMCMP(VPD_RV,v,2) == 0) {
50707+ if (SK_MEMCMP(VPD_RV, v, 2) == 0) {
50708 v += 3 + VPD_GET_VPD_LEN(v) + 3; /* skip VPD-W */
50709 }
50710 else {
50711@@ -600,9 +607,10 @@
50712 ("Key/Len Encoding error\n"));
50713 }
50714 #endif /* DEBUG */
50715- return NULL;
50716+ return(0);
50717 }
50718
50719+
50720 /*
50721 * Move 'n' bytes. Begin with the last byte if 'n' is > 0,
50722 * Start with the last byte if n is < 0.
50723@@ -637,6 +645,7 @@
50724 }
50725 }
50726
50727+
50728 /*
50729 * setup the VPD keyword 'key' at 'ip'.
50730 *
50731@@ -653,10 +662,11 @@
50732 p = (SK_VPD_KEY *) ip;
50733 p->p_key[0] = key[0];
50734 p->p_key[1] = key[1];
50735- p->p_len = (unsigned char) len;
50736- SK_MEMCPY(&p->p_val,buf,len);
50737+ p->p_len = (unsigned char)len;
50738+ SK_MEMCPY(&p->p_val, buf, len);
50739 }
50740
50741+
50742 /*
50743 * Setup the VPD end tag "RV" / "RW".
50744 * Also correct the remaining space variables vpd_free_ro / vpd_free_rw.
50745@@ -682,7 +692,7 @@
50746
50747 if (p->p_key[0] != 'R' || (p->p_key[1] != 'V' && p->p_key[1] != 'W')) {
50748 /* something wrong here, encoding error */
50749- SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
50750+ SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
50751 ("Encoding Error: invalid end tag\n"));
50752 return(1);
50753 }
50754@@ -714,6 +724,7 @@
50755 return(0);
50756 }
50757
50758+
50759 /*
50760 * Insert a VPD keyword into the VPD buffer.
50761 *
50762@@ -747,11 +758,11 @@
50763
50764 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
50765 ("VPD setup para key = %s, val = %s\n",key,buf));
50766-
50767+
50768 vpd_size = pAC->vpd.vpd_size;
50769
50770 rtv = 0;
50771- ip = NULL;
50772+ ip = 0;
50773 if (type == VPD_RW_KEY) {
50774 /* end tag is "RW" */
50775 free = pAC->vpd.v.vpd_free_rw;
50776@@ -875,18 +886,18 @@
50777 }
50778 }
50779
50780- if ((signed)strlen(VPD_NAME) + 1 <= *len) {
50781+ if ((signed)SK_STRLEN(VPD_NAME) + 1 <= *len) {
50782 v = pAC->vpd.vpd_buf;
50783- strcpy(buf,VPD_NAME);
50784- n = strlen(VPD_NAME) + 1;
50785+ SK_STRCPY(buf, VPD_NAME);
50786+ n = SK_STRLEN(VPD_NAME) + 1;
50787 buf += n;
50788 *elements = 1;
50789 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_RX,
50790- ("'%c%c' ",v[0],v[1]));
50791+ ("'%c%c' ", v[0], v[1]));
50792 }
50793 else {
50794 *len = 0;
50795- SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR,
50796+ SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
50797 ("buffer overflow\n"));
50798 return(2);
50799 }
50800@@ -894,17 +905,17 @@
50801 v += 3 + VPD_GET_RES_LEN(v) + 3;
50802 for (;; ) {
50803 /* exit when reaching the "RW" Tag */
50804- if (SK_MEMCMP(VPD_RW,v,2) == 0) {
50805+ if (SK_MEMCMP(VPD_RW, v, 2) == 0) {
50806 break;
50807 }
50808
50809- if (SK_MEMCMP(VPD_RV,v,2) == 0) {
50810+ if (SK_MEMCMP(VPD_RV, v, 2) == 0) {
50811 v += 3 + VPD_GET_VPD_LEN(v) + 3; /* skip VPD-W */
50812 continue;
50813 }
50814
50815 if (n+3 <= *len) {
50816- SK_MEMCPY(buf,v,2);
50817+ SK_MEMCPY(buf, v, 2);
50818 buf += 2;
50819 *buf++ = '\0';
50820 n += 3;
50821@@ -991,13 +1002,14 @@
50822 {
50823 if ((*key != 'Y' && *key != 'V') ||
50824 key[1] < '0' || key[1] > 'Z' ||
50825- (key[1] > '9' && key[1] < 'A') || strlen(key) != 2) {
50826+ (key[1] > '9' && key[1] < 'A') || SK_STRLEN(key) != 2) {
50827
50828 return(SK_FALSE);
50829 }
50830 return(SK_TRUE);
50831 }
50832
50833+
50834 /*
50835 * Read the contents of the VPD EEPROM and copy it to the VPD
50836 * buffer if not already done. Insert/overwrite the keyword 'key'
50837@@ -1026,7 +1038,7 @@
50838
50839 if ((*key != 'Y' && *key != 'V') ||
50840 key[1] < '0' || key[1] > 'Z' ||
50841- (key[1] > '9' && key[1] < 'A') || strlen(key) != 2) {
50842+ (key[1] > '9' && key[1] < 'A') || SK_STRLEN(key) != 2) {
50843
50844 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
50845 ("illegal key tag, keyword not written\n"));
50846@@ -1042,13 +1054,13 @@
50847 }
50848
50849 rtv = 0;
50850- len = strlen(buf);
50851+ len = SK_STRLEN(buf);
50852 if (len > VPD_MAX_LEN) {
50853 /* cut it */
50854 len = VPD_MAX_LEN;
50855 rtv = 2;
50856 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
50857- ("keyword too long, cut after %d bytes\n",VPD_MAX_LEN));
50858+ ("keyword too long, cut after %d bytes\n", VPD_MAX_LEN));
50859 }
50860 if ((rtv2 = VpdSetupPara(pAC, key, buf, len, VPD_RW_KEY, OWR_KEY)) != 0) {
50861 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
50862@@ -1059,6 +1071,7 @@
50863 return(rtv);
50864 }
50865
50866+
50867 /*
50868 * Read the contents of the VPD EEPROM and copy it to the
50869 * VPD buffer if not already done. Remove the VPD keyword
50870@@ -1082,7 +1095,7 @@
50871
50872 vpd_size = pAC->vpd.vpd_size;
50873
50874- SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_TX,("VPD delete key %s\n",key));
50875+ SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_TX, ("VPD delete key %s\n", key));
50876 if ((pAC->vpd.v.vpd_status & VPD_VALID) == 0) {
50877 if (VpdInit(pAC, IoC) != 0) {
50878 SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
50879@@ -1119,6 +1132,7 @@
50880 return(0);
50881 }
50882
50883+
50884 /*
50885 * If the VPD buffer contains valid data write the VPD
50886 * read/write area back to the VPD EEPROM.
50887@@ -1149,7 +1163,6 @@
50888 }
50889
50890
50891-
50892 /*
50893 * Read the contents of the VPD EEPROM and copy it to the VPD buffer
50894 * if not already done. If the keyword "VF" is not present it will be
50895@@ -1178,7 +1191,7 @@
50896 }
50897 }
50898
50899- len = strlen(msg);
50900+ len = SK_STRLEN(msg);
50901 if (len > VPD_MAX_LEN) {
50902 /* cut it */
50903 len = VPD_MAX_LEN;
50904diff -ruN linux/drivers/net/sk98lin/skxmac2.c linux-new/drivers/net/sk98lin/skxmac2.c
50905--- linux/drivers/net/sk98lin/skxmac2.c 2006-04-11 19:19:28.000000000 +0200
50906+++ linux-new/drivers/net/sk98lin/skxmac2.c 2006-01-18 14:37:24.000000000 +0100
50907@@ -2,23 +2,24 @@
50908 *
50909 * Name: skxmac2.c
50910 * Project: Gigabit Ethernet Adapters, Common Modules
50911- * Version: $Revision$
50912- * Date: $Date$
50913+ * Version: $Revision$
50914+ * Date: $Date$
50915 * Purpose: Contains functions to initialize the MACs and PHYs
50916 *
50917 ******************************************************************************/
50918
50919 /******************************************************************************
50920 *
50921+ * LICENSE:
50922 * (C)Copyright 1998-2002 SysKonnect.
50923- * (C)Copyright 2002-2003 Marvell.
50924+ * (C)Copyright 2002-2005 Marvell.
50925 *
50926 * This program is free software; you can redistribute it and/or modify
50927 * it under the terms of the GNU General Public License as published by
50928 * the Free Software Foundation; either version 2 of the License, or
50929 * (at your option) any later version.
50930- *
50931 * The information in this file is provided "AS IS" without warranty.
50932+ * /LICENSE
50933 *
50934 ******************************************************************************/
50935
50936@@ -37,7 +38,7 @@
50937
50938 #if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
50939 static const char SysKonnectFileId[] =
50940- "@(#) $Id$ (C) Marvell.";
50941+ "@(#) $Id$ (C) Marvell.";
50942 #endif
50943
50944 #ifdef GENESIS
50945@@ -83,7 +84,7 @@
50946 * Returns:
50947 * nothing
50948 */
50949-void SkXmPhyRead(
50950+int SkXmPhyRead(
50951 SK_AC *pAC, /* Adapter Context */
50952 SK_IOC IoC, /* I/O Context */
50953 int Port, /* Port Index (MAC_1 + n) */
50954@@ -94,13 +95,13 @@
50955 SK_GEPORT *pPrt;
50956
50957 pPrt = &pAC->GIni.GP[Port];
50958-
50959+
50960 /* write the PHY register's address */
50961 XM_OUT16(IoC, Port, XM_PHY_ADDR, PhyReg | pPrt->PhyAddr);
50962-
50963+
50964 /* get the PHY register's value */
50965 XM_IN16(IoC, Port, XM_PHY_DATA, pVal);
50966-
50967+
50968 if (pPrt->PhyType != SK_PHY_XMAC) {
50969 do {
50970 XM_IN16(IoC, Port, XM_MMU_CMD, &Mmu);
50971@@ -110,6 +111,8 @@
50972 /* get the PHY register's value */
50973 XM_IN16(IoC, Port, XM_PHY_DATA, pVal);
50974 }
50975+
50976+ return(0);
50977 } /* SkXmPhyRead */
50978
50979
50980@@ -122,7 +125,7 @@
50981 * Returns:
50982 * nothing
50983 */
50984-void SkXmPhyWrite(
50985+int SkXmPhyWrite(
50986 SK_AC *pAC, /* Adapter Context */
50987 SK_IOC IoC, /* I/O Context */
50988 int Port, /* Port Index (MAC_1 + n) */
50989@@ -133,26 +136,28 @@
50990 SK_GEPORT *pPrt;
50991
50992 pPrt = &pAC->GIni.GP[Port];
50993-
50994+
50995 if (pPrt->PhyType != SK_PHY_XMAC) {
50996 do {
50997 XM_IN16(IoC, Port, XM_MMU_CMD, &Mmu);
50998 /* wait until 'Busy' is cleared */
50999 } while ((Mmu & XM_MMU_PHY_BUSY) != 0);
51000 }
51001-
51002+
51003 /* write the PHY register's address */
51004 XM_OUT16(IoC, Port, XM_PHY_ADDR, PhyReg | pPrt->PhyAddr);
51005-
51006+
51007 /* write the PHY register's value */
51008 XM_OUT16(IoC, Port, XM_PHY_DATA, Val);
51009-
51010+
51011 if (pPrt->PhyType != SK_PHY_XMAC) {
51012 do {
51013 XM_IN16(IoC, Port, XM_MMU_CMD, &Mmu);
51014 /* wait until 'Busy' is cleared */
51015 } while ((Mmu & XM_MMU_PHY_BUSY) != 0);
51016 }
51017+
51018+ return(0);
51019 } /* SkXmPhyWrite */
51020 #endif /* GENESIS */
51021
51022@@ -165,63 +170,97 @@
51023 * Description: reads a 16-bit word from GPHY through MDIO
51024 *
51025 * Returns:
51026- * nothing
51027+ * 0 o.k.
51028+ * 1 error during MDIO read
51029+ * 2 timeout
51030 */
51031-void SkGmPhyRead(
51032+int SkGmPhyRead(
51033 SK_AC *pAC, /* Adapter Context */
51034 SK_IOC IoC, /* I/O Context */
51035 int Port, /* Port Index (MAC_1 + n) */
51036 int PhyReg, /* Register Address (Offset) */
51037 SK_U16 SK_FAR *pVal) /* Pointer to Value */
51038 {
51039+ SK_U16 Word;
51040 SK_U16 Ctrl;
51041 SK_GEPORT *pPrt;
51042-#ifdef VCPU
51043- u_long SimCyle;
51044- u_long SimLowTime;
51045-
51046- VCPUgetTime(&SimCyle, &SimLowTime);
51047- VCPUprintf(0, "SkGmPhyRead(%u), SimCyle=%u, SimLowTime=%u\n",
51048- PhyReg, SimCyle, SimLowTime);
51049-#endif /* VCPU */
51050-
51051+ SK_U32 StartTime;
51052+ SK_U32 CurrTime;
51053+ SK_U32 Delta;
51054+ SK_U32 TimeOut;
51055+ int Rtv;
51056+
51057+ Rtv = 0;
51058+
51059+ *pVal = 0xffff;
51060+
51061 pPrt = &pAC->GIni.GP[Port];
51062-
51063+
51064 /* set PHY-Register offset and 'Read' OpCode (= 1) */
51065- *pVal = (SK_U16)(GM_SMI_CT_PHY_AD(pPrt->PhyAddr) |
51066+ Word = (SK_U16)(GM_SMI_CT_PHY_AD(pPrt->PhyAddr) |
51067 GM_SMI_CT_REG_AD(PhyReg) | GM_SMI_CT_OP_RD);
51068
51069- GM_OUT16(IoC, Port, GM_SMI_CTRL, *pVal);
51070+ GM_OUT16(IoC, Port, GM_SMI_CTRL, Word);
51071
51072- GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);
51073-
51074 /* additional check for MDC/MDIO activity */
51075- if ((Ctrl & GM_SMI_CT_BUSY) == 0) {
51076- *pVal = 0;
51077- return;
51078+ GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);
51079+
51080+ if (Ctrl == 0xffff || (Ctrl & GM_SMI_CT_OP_RD) == 0) {
51081+
51082+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
51083+ ("PHY read impossible on Port %d (Ctrl=0x%04x)\n", Port, Ctrl));
51084+
51085+ return(1);
51086 }
51087
51088- *pVal |= GM_SMI_CT_BUSY;
51089-
51090- do {
51091+ Word |= GM_SMI_CT_BUSY;
51092+
51093+ SK_IN32(IoC, GMAC_TI_ST_VAL, &StartTime);
51094+
51095+ /* set timeout to 10 ms */
51096+ TimeOut = HW_MS_TO_TICKS(pAC, 10);
51097+
51098+ do { /* wait until 'Busy' is cleared and 'ReadValid' is set */
51099 #ifdef VCPU
51100 VCPUwaitTime(1000);
51101 #endif /* VCPU */
51102
51103+ SK_IN32(IoC, GMAC_TI_ST_VAL, &CurrTime);
51104+
51105+ if (CurrTime >= StartTime) {
51106+ Delta = CurrTime - StartTime;
51107+ }
51108+ else {
51109+ Delta = CurrTime + ~StartTime + 1;
51110+ }
51111+
51112+ if (Delta > TimeOut) {
51113+
51114+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
51115+ ("PHY read timeout on Port %d (Ctrl=0x%04x)\n", Port, Ctrl));
51116+ Rtv = 2;
51117+ break;
51118+ }
51119+
51120 GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);
51121
51122- /* wait until 'ReadValid' is set */
51123- } while (Ctrl == *pVal);
51124-
51125- /* get the PHY register's value */
51126+ /* Error on reading SMI Control Register */
51127+ if (Ctrl == 0xffff) {
51128+ return(1);
51129+ }
51130+
51131+ } while ((Ctrl ^ Word) != (GM_SMI_CT_RD_VAL | GM_SMI_CT_BUSY));
51132+
51133 GM_IN16(IoC, Port, GM_SMI_DATA, pVal);
51134
51135-#ifdef VCPU
51136- VCPUgetTime(&SimCyle, &SimLowTime);
51137- VCPUprintf(0, "VCPUgetTime(), SimCyle=%u, SimLowTime=%u\n",
51138- SimCyle, SimLowTime);
51139-#endif /* VCPU */
51140+ /* dummy read after GM_IN16() */
51141+ SK_IN32(IoC, GMAC_TI_ST_VAL, &CurrTime);
51142
51143+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
51144+ ("SkGmPhyRead Port:%d, Reg=%d, Val = 0x%04X\n",
51145+ Port, PhyReg, *pVal));
51146+
51147+ return(Rtv);
51148 } /* SkGmPhyRead */
51149
51150
51151@@ -232,9 +271,11 @@
51152 * Description: writes a 16-bit word to GPHY through MDIO
51153 *
51154 * Returns:
51155- * nothing
51156+ * 0 o.k.
51157+ * 1 error during MDIO read
51158+ * 2 timeout
51159 */
51160-void SkGmPhyWrite(
51161+int SkGmPhyWrite(
51162 SK_AC *pAC, /* Adapter Context */
51163 SK_IOC IoC, /* I/O Context */
51164 int Port, /* Port Index (MAC_1 + n) */
51165@@ -243,54 +284,78 @@
51166 {
51167 SK_U16 Ctrl;
51168 SK_GEPORT *pPrt;
51169-#ifdef VCPU
51170- SK_U32 DWord;
51171- u_long SimCyle;
51172- u_long SimLowTime;
51173-
51174- VCPUgetTime(&SimCyle, &SimLowTime);
51175- VCPUprintf(0, "SkGmPhyWrite(Reg=%u, Val=0x%04x), SimCyle=%u, SimLowTime=%u\n",
51176- PhyReg, Val, SimCyle, SimLowTime);
51177-#endif /* VCPU */
51178-
51179+ SK_U32 StartTime;
51180+ SK_U32 CurrTime;
51181+ SK_U32 Delta;
51182+ SK_U32 TimeOut;
51183+
51184+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
51185+ ("SkGmPhyWrite Port:%d, Reg=%d, Val = 0x%04X\n",
51186+ Port, PhyReg, Val));
51187+
51188 pPrt = &pAC->GIni.GP[Port];
51189-
51190+
51191 /* write the PHY register's value */
51192 GM_OUT16(IoC, Port, GM_SMI_DATA, Val);
51193-
51194- /* set PHY-Register offset and 'Write' OpCode (= 0) */
51195- Val = GM_SMI_CT_PHY_AD(pPrt->PhyAddr) | GM_SMI_CT_REG_AD(PhyReg);
51196
51197- GM_OUT16(IoC, Port, GM_SMI_CTRL, Val);
51198-
51199- GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);
51200-
51201+#ifdef DEBUG
51202 /* additional check for MDC/MDIO activity */
51203- if ((Ctrl & GM_SMI_CT_BUSY) == 0) {
51204- return;
51205+ GM_IN16(IoC, Port, GM_SMI_DATA, &Ctrl);
51206+
51207+ if (Ctrl != Val) {
51208+
51209+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
51210+ ("PHY write impossible on Port %d (Val=0x%04x)\n", Port, Ctrl));
51211+
51212+ return(1);
51213 }
51214-
51215- Val |= GM_SMI_CT_BUSY;
51216+#endif /* DEBUG */
51217
51218- do {
51219-#ifdef VCPU
51220- /* read Timer value */
51221- SK_IN32(IoC, B2_TI_VAL, &DWord);
51222+ /* set PHY-Register offset and 'Write' OpCode (= 0) */
51223+ Ctrl = (SK_U16)(GM_SMI_CT_PHY_AD(pPrt->PhyAddr) |
51224+ GM_SMI_CT_REG_AD(PhyReg));
51225
51226+ GM_OUT16(IoC, Port, GM_SMI_CTRL, Ctrl);
51227+
51228+ SK_IN32(IoC, GMAC_TI_ST_VAL, &StartTime);
51229+
51230+ /* set timeout to 10 ms */
51231+ TimeOut = HW_MS_TO_TICKS(pAC, 10);
51232+
51233+ do { /* wait until 'Busy' is cleared */
51234+#ifdef VCPU
51235 VCPUwaitTime(1000);
51236 #endif /* VCPU */
51237
51238+ SK_IN32(IoC, GMAC_TI_ST_VAL, &CurrTime);
51239+
51240+ if (CurrTime >= StartTime) {
51241+ Delta = CurrTime - StartTime;
51242+ }
51243+ else {
51244+ Delta = CurrTime + ~StartTime + 1;
51245+ }
51246+
51247+ if (Delta > TimeOut) {
51248+
51249+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
51250+ ("PHY write timeout on Port %d (Ctrl=0x%04x)\n", Port, Ctrl));
51251+ return(2);
51252+ }
51253+
51254 GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);
51255
51256- /* wait until 'Busy' is cleared */
51257- } while (Ctrl == Val);
51258-
51259-#ifdef VCPU
51260- VCPUgetTime(&SimCyle, &SimLowTime);
51261- VCPUprintf(0, "VCPUgetTime(), SimCyle=%u, SimLowTime=%u\n",
51262- SimCyle, SimLowTime);
51263-#endif /* VCPU */
51264+ /* Error on reading SMI Control Register */
51265+ if (Ctrl == 0xffff) {
51266+ return(1);
51267+ }
51268
51269+ } while ((Ctrl & GM_SMI_CT_BUSY) != 0);
51270+
51271+ /* dummy read after GM_IN16() */
51272+ SK_IN32(IoC, GMAC_TI_ST_VAL, &CurrTime);
51273+
51274+ return(0);
51275 } /* SkGmPhyWrite */
51276 #endif /* YUKON */
51277
51278@@ -312,16 +377,8 @@
51279 int PhyReg, /* Register Address (Offset) */
51280 SK_U16 *pVal) /* Pointer to Value */
51281 {
51282- void (*r_func)(SK_AC *pAC, SK_IOC IoC, int Port, int Reg, SK_U16 *pVal);
51283
51284- if (pAC->GIni.GIGenesis) {
51285- r_func = SkXmPhyRead;
51286- }
51287- else {
51288- r_func = SkGmPhyRead;
51289- }
51290-
51291- r_func(pAC, IoC, Port, PhyReg, pVal);
51292+ pAC->GIni.GIFunc.pFnMacPhyRead(pAC, IoC, Port, PhyReg, pVal);
51293 } /* SkGePhyRead */
51294
51295
51296@@ -341,16 +398,8 @@
51297 int PhyReg, /* Register Address (Offset) */
51298 SK_U16 Val) /* Value */
51299 {
51300- void (*w_func)(SK_AC *pAC, SK_IOC IoC, int Port, int Reg, SK_U16 Val);
51301
51302- if (pAC->GIni.GIGenesis) {
51303- w_func = SkXmPhyWrite;
51304- }
51305- else {
51306- w_func = SkGmPhyWrite;
51307- }
51308-
51309- w_func(pAC, IoC, Port, PhyReg, Val);
51310+ pAC->GIni.GIFunc.pFnMacPhyWrite(pAC, IoC, Port, PhyReg, Val);
51311 } /* SkGePhyWrite */
51312 #endif /* SK_DIAG */
51313
51314@@ -360,15 +409,15 @@
51315 * SkMacPromiscMode() - Enable / Disable Promiscuous Mode
51316 *
51317 * Description:
51318- * enables / disables promiscuous mode by setting Mode Register (XMAC) or
51319- * Receive Control Register (GMAC) dep. on board type
51320+ * enables / disables promiscuous mode by setting Mode Register (XMAC) or
51321+ * Receive Control Register (GMAC) dep. on board type
51322 *
51323 * Returns:
51324 * nothing
51325 */
51326 void SkMacPromiscMode(
51327-SK_AC *pAC, /* adapter context */
51328-SK_IOC IoC, /* IO context */
51329+SK_AC *pAC, /* Adapter Context */
51330+SK_IOC IoC, /* I/O Context */
51331 int Port, /* Port Index (MAC_1 + n) */
51332 SK_BOOL Enable) /* Enable / Disable */
51333 {
51334@@ -377,11 +426,11 @@
51335 #endif
51336 #ifdef GENESIS
51337 SK_U32 MdReg;
51338-#endif
51339+#endif
51340
51341 #ifdef GENESIS
51342 if (pAC->GIni.GIGenesis) {
51343-
51344+
51345 XM_IN32(IoC, Port, XM_MODE, &MdReg);
51346 /* enable or disable promiscuous mode */
51347 if (Enable) {
51348@@ -394,12 +443,12 @@
51349 XM_OUT32(IoC, Port, XM_MODE, MdReg);
51350 }
51351 #endif /* GENESIS */
51352-
51353+
51354 #ifdef YUKON
51355 if (pAC->GIni.GIYukon) {
51356-
51357+
51358 GM_IN16(IoC, Port, GM_RX_CTRL, &RcReg);
51359-
51360+
51361 /* enable or disable unicast and multicast filtering */
51362 if (Enable) {
51363 RcReg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
51364@@ -420,28 +469,28 @@
51365 * SkMacHashing() - Enable / Disable Hashing
51366 *
51367 * Description:
51368- * enables / disables hashing by setting Mode Register (XMAC) or
51369- * Receive Control Register (GMAC) dep. on board type
51370+ * enables / disables hashing by setting Mode Register (XMAC) or
51371+ * Receive Control Register (GMAC) dep. on board type
51372 *
51373 * Returns:
51374 * nothing
51375 */
51376 void SkMacHashing(
51377-SK_AC *pAC, /* adapter context */
51378-SK_IOC IoC, /* IO context */
51379+SK_AC *pAC, /* Adapter Context */
51380+SK_IOC IoC, /* I/O Context */
51381 int Port, /* Port Index (MAC_1 + n) */
51382 SK_BOOL Enable) /* Enable / Disable */
51383 {
51384 #ifdef YUKON
51385 SK_U16 RcReg;
51386-#endif
51387+#endif
51388 #ifdef GENESIS
51389 SK_U32 MdReg;
51390 #endif
51391
51392 #ifdef GENESIS
51393 if (pAC->GIni.GIGenesis) {
51394-
51395+
51396 XM_IN32(IoC, Port, XM_MODE, &MdReg);
51397 /* enable or disable hashing */
51398 if (Enable) {
51399@@ -454,12 +503,12 @@
51400 XM_OUT32(IoC, Port, XM_MODE, MdReg);
51401 }
51402 #endif /* GENESIS */
51403-
51404+
51405 #ifdef YUKON
51406 if (pAC->GIni.GIYukon) {
51407-
51408+
51409 GM_IN16(IoC, Port, GM_RX_CTRL, &RcReg);
51410-
51411+
51412 /* enable or disable multicast filtering */
51413 if (Enable) {
51414 RcReg |= GM_RXCR_MCF_ENA;
51415@@ -487,8 +536,8 @@
51416 * - don't set XMR_FS_ERR in status SK_LENERR_OK_ON/OFF
51417 * for inrange length error frames
51418 * - don't set XMR_FS_ERR in status SK_BIG_PK_OK_ON/OFF
51419- * for frames > 1514 bytes
51420- * - enable Rx of own packets SK_SELF_RX_ON/OFF
51421+ * for frames > 1514 bytes
51422+ * - enable Rx of own packets SK_SELF_RX_ON/OFF
51423 *
51424 * for incoming packets may be enabled/disabled by this function.
51425 * Additional modes may be added later.
51426@@ -499,11 +548,11 @@
51427 * nothing
51428 */
51429 static void SkXmSetRxCmd(
51430-SK_AC *pAC, /* adapter context */
51431-SK_IOC IoC, /* IO context */
51432+SK_AC *pAC, /* Adapter Context */
51433+SK_IOC IoC, /* I/O Context */
51434 int Port, /* Port Index (MAC_1 + n) */
51435 int Mode) /* Mode is SK_STRIP_FCS_ON/OFF, SK_STRIP_PAD_ON/OFF,
51436- SK_LENERR_OK_ON/OFF, or SK_BIG_PK_OK_ON/OFF */
51437+ SK_LENERR_OK_ON/OFF, or SK_BIG_PK_OK_ON/OFF */
51438 {
51439 SK_U16 OldRxCmd;
51440 SK_U16 RxCmd;
51441@@ -511,7 +560,7 @@
51442 XM_IN16(IoC, Port, XM_RX_CMD, &OldRxCmd);
51443
51444 RxCmd = OldRxCmd;
51445-
51446+
51447 switch (Mode & (SK_STRIP_FCS_ON | SK_STRIP_FCS_OFF)) {
51448 case SK_STRIP_FCS_ON:
51449 RxCmd |= XM_RX_STRIP_FCS;
51450@@ -572,8 +621,8 @@
51451 * The features
51452 * - FCS (CRC) stripping, SK_STRIP_FCS_ON/OFF
51453 * - don't set GMR_FS_LONG_ERR SK_BIG_PK_OK_ON/OFF
51454- * for frames > 1514 bytes
51455- * - enable Rx of own packets SK_SELF_RX_ON/OFF
51456+ * for frames > 1514 bytes
51457+ * - enable Rx of own packets SK_SELF_RX_ON/OFF
51458 *
51459 * for incoming packets may be enabled/disabled by this function.
51460 * Additional modes may be added later.
51461@@ -584,20 +633,17 @@
51462 * nothing
51463 */
51464 static void SkGmSetRxCmd(
51465-SK_AC *pAC, /* adapter context */
51466-SK_IOC IoC, /* IO context */
51467+SK_AC *pAC, /* Adapter Context */
51468+SK_IOC IoC, /* I/O Context */
51469 int Port, /* Port Index (MAC_1 + n) */
51470 int Mode) /* Mode is SK_STRIP_FCS_ON/OFF, SK_STRIP_PAD_ON/OFF,
51471- SK_LENERR_OK_ON/OFF, or SK_BIG_PK_OK_ON/OFF */
51472+ SK_LENERR_OK_ON/OFF, or SK_BIG_PK_OK_ON/OFF */
51473 {
51474- SK_U16 OldRxCmd;
51475 SK_U16 RxCmd;
51476
51477 if ((Mode & (SK_STRIP_FCS_ON | SK_STRIP_FCS_OFF)) != 0) {
51478-
51479- GM_IN16(IoC, Port, GM_RX_CTRL, &OldRxCmd);
51480
51481- RxCmd = OldRxCmd;
51482+ GM_IN16(IoC, Port, GM_RX_CTRL, &RxCmd);
51483
51484 if ((Mode & SK_STRIP_FCS_ON) != 0) {
51485 RxCmd |= GM_RXCR_CRC_DIS;
51486@@ -605,17 +651,13 @@
51487 else {
51488 RxCmd &= ~GM_RXCR_CRC_DIS;
51489 }
51490- /* Write the new mode to the Rx control register if required */
51491- if (OldRxCmd != RxCmd) {
51492- GM_OUT16(IoC, Port, GM_RX_CTRL, RxCmd);
51493- }
51494+ /* Write the new mode to the Rx Control register */
51495+ GM_OUT16(IoC, Port, GM_RX_CTRL, RxCmd);
51496 }
51497
51498 if ((Mode & (SK_BIG_PK_OK_ON | SK_BIG_PK_OK_OFF)) != 0) {
51499-
51500- GM_IN16(IoC, Port, GM_SERIAL_MODE, &OldRxCmd);
51501
51502- RxCmd = OldRxCmd;
51503+ GM_IN16(IoC, Port, GM_SERIAL_MODE, &RxCmd);
51504
51505 if ((Mode & SK_BIG_PK_OK_ON) != 0) {
51506 RxCmd |= GM_SMOD_JUMBO_ENA;
51507@@ -623,10 +665,8 @@
51508 else {
51509 RxCmd &= ~GM_SMOD_JUMBO_ENA;
51510 }
51511- /* Write the new mode to the Rx control register if required */
51512- if (OldRxCmd != RxCmd) {
51513- GM_OUT16(IoC, Port, GM_SERIAL_MODE, RxCmd);
51514- }
51515+ /* Write the new mode to the Serial Mode register */
51516+ GM_OUT16(IoC, Port, GM_SERIAL_MODE, RxCmd);
51517 }
51518 } /* SkGmSetRxCmd */
51519
51520@@ -641,17 +681,17 @@
51521 * nothing
51522 */
51523 void SkMacSetRxCmd(
51524-SK_AC *pAC, /* adapter context */
51525-SK_IOC IoC, /* IO context */
51526+SK_AC *pAC, /* Adapter Context */
51527+SK_IOC IoC, /* I/O Context */
51528 int Port, /* Port Index (MAC_1 + n) */
51529 int Mode) /* Rx Mode */
51530 {
51531 if (pAC->GIni.GIGenesis) {
51532-
51533+
51534 SkXmSetRxCmd(pAC, IoC, Port, Mode);
51535 }
51536 else {
51537-
51538+
51539 SkGmSetRxCmd(pAC, IoC, Port, Mode);
51540 }
51541
51542@@ -668,15 +708,15 @@
51543 * nothing
51544 */
51545 void SkMacCrcGener(
51546-SK_AC *pAC, /* adapter context */
51547-SK_IOC IoC, /* IO context */
51548+SK_AC *pAC, /* Adapter Context */
51549+SK_IOC IoC, /* I/O Context */
51550 int Port, /* Port Index (MAC_1 + n) */
51551 SK_BOOL Enable) /* Enable / Disable */
51552 {
51553 SK_U16 Word;
51554
51555 if (pAC->GIni.GIGenesis) {
51556-
51557+
51558 XM_IN16(IoC, Port, XM_TX_CMD, &Word);
51559
51560 if (Enable) {
51561@@ -689,9 +729,9 @@
51562 XM_OUT16(IoC, Port, XM_TX_CMD, Word);
51563 }
51564 else {
51565-
51566+
51567 GM_IN16(IoC, Port, GM_TX_CTRL, &Word);
51568-
51569+
51570 if (Enable) {
51571 Word &= ~GM_TXCR_CRC_DIS;
51572 }
51573@@ -721,14 +761,14 @@
51574 * nothing
51575 */
51576 void SkXmClrExactAddr(
51577-SK_AC *pAC, /* adapter context */
51578-SK_IOC IoC, /* IO context */
51579+SK_AC *pAC, /* Adapter Context */
51580+SK_IOC IoC, /* I/O Context */
51581 int Port, /* Port Index (MAC_1 + n) */
51582 int StartNum, /* Begin with this Address Register Index (0..15) */
51583 int StopNum) /* Stop after finished with this Register Idx (0..15) */
51584 {
51585 int i;
51586- SK_U16 ZeroAddr[3] = {0x0000, 0x0000, 0x0000};
51587+ SK_U16 ZeroAddr[3] = {0, 0, 0};
51588
51589 if ((unsigned)StartNum > 15 || (unsigned)StopNum > 15 ||
51590 StartNum > StopNum) {
51591@@ -738,7 +778,7 @@
51592 }
51593
51594 for (i = StartNum; i <= StopNum; i++) {
51595- XM_OUTADDR(IoC, Port, XM_EXM(i), &ZeroAddr[0]);
51596+ XM_OUTADDR(IoC, Port, XM_EXM(i), ZeroAddr);
51597 }
51598 } /* SkXmClrExactAddr */
51599 #endif /* GENESIS */
51600@@ -755,21 +795,21 @@
51601 * nothing
51602 */
51603 void SkMacFlushTxFifo(
51604-SK_AC *pAC, /* adapter context */
51605-SK_IOC IoC, /* IO context */
51606+SK_AC *pAC, /* Adapter Context */
51607+SK_IOC IoC, /* I/O Context */
51608 int Port) /* Port Index (MAC_1 + n) */
51609 {
51610 #ifdef GENESIS
51611 SK_U32 MdReg;
51612
51613 if (pAC->GIni.GIGenesis) {
51614-
51615+
51616 XM_IN32(IoC, Port, XM_MODE, &MdReg);
51617
51618 XM_OUT32(IoC, Port, XM_MODE, MdReg | XM_MD_FTF);
51619 }
51620 #endif /* GENESIS */
51621-
51622+
51623 #ifdef YUKON
51624 if (pAC->GIni.GIYukon) {
51625 /* no way to flush the FIFO we have to issue a reset */
51626@@ -791,8 +831,8 @@
51627 * nothing
51628 */
51629 void SkMacFlushRxFifo(
51630-SK_AC *pAC, /* adapter context */
51631-SK_IOC IoC, /* IO context */
51632+SK_AC *pAC, /* Adapter Context */
51633+SK_IOC IoC, /* I/O Context */
51634 int Port) /* Port Index (MAC_1 + n) */
51635 {
51636 #ifdef GENESIS
51637@@ -805,7 +845,7 @@
51638 XM_OUT32(IoC, Port, XM_MODE, MdReg | XM_MD_FRF);
51639 }
51640 #endif /* GENESIS */
51641-
51642+
51643 #ifdef YUKON
51644 if (pAC->GIni.GIYukon) {
51645 /* no way to flush the FIFO we have to issue a reset */
51646@@ -853,23 +893,23 @@
51647 * nothing
51648 */
51649 static void SkXmSoftRst(
51650-SK_AC *pAC, /* adapter context */
51651-SK_IOC IoC, /* IO context */
51652+SK_AC *pAC, /* Adapter Context */
51653+SK_IOC IoC, /* I/O Context */
51654 int Port) /* Port Index (MAC_1 + n) */
51655 {
51656- SK_U16 ZeroAddr[4] = {0x0000, 0x0000, 0x0000, 0x0000};
51657-
51658+ SK_U16 ZeroAddr[4] = {0, 0, 0, 0};
51659+
51660 /* reset the statistics module */
51661 XM_OUT32(IoC, Port, XM_GP_PORT, XM_GP_RES_STAT);
51662
51663 /* disable all XMAC IRQs */
51664 XM_OUT16(IoC, Port, XM_IMSK, 0xffff);
51665-
51666+
51667 XM_OUT32(IoC, Port, XM_MODE, 0); /* clear Mode Reg */
51668-
51669+
51670 XM_OUT16(IoC, Port, XM_TX_CMD, 0); /* reset TX CMD Reg */
51671 XM_OUT16(IoC, Port, XM_RX_CMD, 0); /* reset RX CMD Reg */
51672-
51673+
51674 /* disable all PHY IRQs */
51675 switch (pAC->GIni.GP[Port].PhyType) {
51676 case SK_PHY_BCOM:
51677@@ -887,13 +927,13 @@
51678 }
51679
51680 /* clear the Hash Register */
51681- XM_OUTHASH(IoC, Port, XM_HSM, &ZeroAddr);
51682+ XM_OUTHASH(IoC, Port, XM_HSM, ZeroAddr);
51683
51684 /* clear the Exact Match Address registers */
51685 SkXmClrExactAddr(pAC, IoC, Port, 0, 15);
51686-
51687+
51688 /* clear the Source Check Address registers */
51689- XM_OUTHASH(IoC, Port, XM_SRC_CHK, &ZeroAddr);
51690+ XM_OUTHASH(IoC, Port, XM_SRC_CHK, ZeroAddr);
51691
51692 } /* SkXmSoftRst */
51693
51694@@ -916,8 +956,8 @@
51695 * nothing
51696 */
51697 static void SkXmHardRst(
51698-SK_AC *pAC, /* adapter context */
51699-SK_IOC IoC, /* IO context */
51700+SK_AC *pAC, /* Adapter Context */
51701+SK_IOC IoC, /* I/O Context */
51702 int Port) /* Port Index (MAC_1 + n) */
51703 {
51704 SK_U32 Reg;
51705@@ -940,19 +980,19 @@
51706 }
51707
51708 SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
51709-
51710+
51711 SK_IN16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), &Word);
51712-
51713+
51714 } while ((Word & MFF_SET_MAC_RST) == 0);
51715 }
51716
51717 /* For external PHYs there must be special handling */
51718 if (pAC->GIni.GP[Port].PhyType != SK_PHY_XMAC) {
51719-
51720+
51721 SK_IN32(IoC, B2_GP_IO, &Reg);
51722-
51723+
51724 if (Port == 0) {
51725- Reg |= GP_DIR_0; /* set to output */
51726+ Reg |= GP_DIR_0; /* set to output */
51727 Reg &= ~GP_IO_0; /* set PHY reset (active low) */
51728 }
51729 else {
51730@@ -978,12 +1018,12 @@
51731 * nothing
51732 */
51733 static void SkXmClearRst(
51734-SK_AC *pAC, /* adapter context */
51735-SK_IOC IoC, /* IO context */
51736+SK_AC *pAC, /* Adapter Context */
51737+SK_IOC IoC, /* I/O Context */
51738 int Port) /* Port Index (MAC_1 + n) */
51739 {
51740 SK_U32 DWord;
51741-
51742+
51743 /* clear HW reset */
51744 SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
51745
51746@@ -1000,7 +1040,7 @@
51747 /* Clear PHY reset */
51748 SK_OUT32(IoC, B2_GP_IO, DWord);
51749
51750- /* Enable GMII interface */
51751+ /* enable GMII interface */
51752 XM_OUT16(IoC, Port, XM_HW_CFG, XM_HW_GMII_MD);
51753 }
51754 } /* SkXmClearRst */
51755@@ -1020,29 +1060,28 @@
51756 * nothing
51757 */
51758 static void SkGmSoftRst(
51759-SK_AC *pAC, /* adapter context */
51760-SK_IOC IoC, /* IO context */
51761+SK_AC *pAC, /* Adapter Context */
51762+SK_IOC IoC, /* I/O Context */
51763 int Port) /* Port Index (MAC_1 + n) */
51764 {
51765- SK_U16 EmptyHash[4] = {0x0000, 0x0000, 0x0000, 0x0000};
51766- SK_U16 RxCtrl;
51767+ SK_U16 EmptyHash[4] = { 0x0000, 0x0000, 0x0000, 0x0000 };
51768+ SK_U16 RxCtrl;
51769
51770 /* reset the statistics module */
51771
51772 /* disable all GMAC IRQs */
51773- SK_OUT8(IoC, GMAC_IRQ_MSK, 0);
51774-
51775+ SK_OUT8(IoC, MR_ADDR(Port, GMAC_IRQ_MSK), 0);
51776+
51777 /* disable all PHY IRQs */
51778 SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, 0);
51779-
51780+
51781 /* clear the Hash Register */
51782 GM_OUTHASH(IoC, Port, GM_MC_ADDR_H1, EmptyHash);
51783
51784- /* Enable Unicast and Multicast filtering */
51785+ /* enable Unicast and Multicast filtering */
51786 GM_IN16(IoC, Port, GM_RX_CTRL, &RxCtrl);
51787-
51788- GM_OUT16(IoC, Port, GM_RX_CTRL,
51789- (SK_U16)(RxCtrl | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA));
51790+
51791+ GM_OUT16(IoC, Port, GM_RX_CTRL, RxCtrl | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
51792
51793 } /* SkGmSoftRst */
51794
51795@@ -1057,16 +1096,16 @@
51796 * nothing
51797 */
51798 static void SkGmHardRst(
51799-SK_AC *pAC, /* adapter context */
51800-SK_IOC IoC, /* IO context */
51801+SK_AC *pAC, /* Adapter Context */
51802+SK_IOC IoC, /* I/O Context */
51803 int Port) /* Port Index (MAC_1 + n) */
51804 {
51805 SK_U32 DWord;
51806-
51807+
51808 /* WA code for COMA mode */
51809 if (pAC->GIni.GIYukonLite &&
51810 pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3) {
51811-
51812+
51813 SK_IN32(IoC, B2_GP_IO, &DWord);
51814
51815 DWord |= (GP_DIR_9 | GP_IO_9);
51816@@ -1076,10 +1115,10 @@
51817 }
51818
51819 /* set GPHY Control reset */
51820- SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), GPC_RST_SET);
51821+ SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_SET);
51822
51823 /* set GMAC Control reset */
51824- SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_RST_SET);
51825+ SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_SET);
51826
51827 } /* SkGmHardRst */
51828
51829@@ -1094,24 +1133,29 @@
51830 * nothing
51831 */
51832 static void SkGmClearRst(
51833-SK_AC *pAC, /* adapter context */
51834-SK_IOC IoC, /* IO context */
51835+SK_AC *pAC, /* Adapter Context */
51836+SK_IOC IoC, /* I/O Context */
51837 int Port) /* Port Index (MAC_1 + n) */
51838 {
51839 SK_U32 DWord;
51840-
51841+#ifndef SK_SLIM
51842+ SK_U16 PhyId0;
51843+ SK_U16 PhyId1;
51844+ SK_U16 Word;
51845+#endif
51846+
51847 #ifdef XXX
51848- /* clear GMAC Control reset */
51849- SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_RST_CLR);
51850+ /* clear GMAC Control reset */
51851+ SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_CLR);
51852
51853- /* set GMAC Control reset */
51854- SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_RST_SET);
51855+ /* set GMAC Control reset */
51856+ SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_SET);
51857 #endif /* XXX */
51858
51859 /* WA code for COMA mode */
51860 if (pAC->GIni.GIYukonLite &&
51861 pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3) {
51862-
51863+
51864 SK_IN32(IoC, B2_GP_IO, &DWord);
51865
51866 DWord |= GP_DIR_9; /* set to output */
51867@@ -1121,30 +1165,87 @@
51868 SK_OUT32(IoC, B2_GP_IO, DWord);
51869 }
51870
51871- /* set HWCFG_MODE */
51872- DWord = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
51873- GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE |
51874- (pAC->GIni.GICopperType ? GPC_HWCFG_GMII_COP :
51875- GPC_HWCFG_GMII_FIB);
51876+#ifdef VCPU
51877+ /* set MAC Reset before PHY reset is set */
51878+ SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_SET);
51879+#endif /* VCPU */
51880+
51881+ if (CHIP_ID_YUKON_2(pAC)) {
51882+ /* set GPHY Control reset */
51883+ SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_SET);
51884
51885- /* set GPHY Control reset */
51886- SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), DWord | GPC_RST_SET);
51887+ /* release GPHY Control reset */
51888+ SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_CLR);
51889
51890- /* release GPHY Control reset */
51891- SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), DWord | GPC_RST_CLR);
51892+#ifdef DEBUG
51893+ /* additional check for PEX */
51894+ SK_IN16(IoC, GPHY_CTRL, &Word);
51895+
51896+ if (pAC->GIni.GIPciBus == SK_PEX_BUS && Word != GPC_RST_CLR) {
51897+
51898+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
51899+ ("Error on PEX-bus after GPHY reset\n"));
51900+ }
51901+#endif /* DEBUG */
51902+ }
51903+ else {
51904+ /* set HWCFG_MODE */
51905+ DWord = GPC_INT_POL | GPC_DIS_FC | GPC_DIS_SLEEP |
51906+ GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE |
51907+ (pAC->GIni.GICopperType ? GPC_HWCFG_GMII_COP :
51908+ GPC_HWCFG_GMII_FIB);
51909+
51910+ /* set GPHY Control reset */
51911+ SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), DWord | GPC_RST_SET);
51912+
51913+ /* release GPHY Control reset */
51914+ SK_OUT32(IoC, MR_ADDR(Port, GPHY_CTRL), DWord | GPC_RST_CLR);
51915+ }
51916
51917 #ifdef VCPU
51918+ /* wait for internal initialization of GPHY */
51919+ VCPUprintf(0, "Waiting until PHY %d is ready to initialize\n", Port);
51920+ VCpuWait(10000);
51921+
51922+ /* release GMAC reset */
51923+ SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_CLR);
51924+
51925+ /* wait for stable GMAC clock */
51926 VCpuWait(9000);
51927 #endif /* VCPU */
51928
51929 /* clear GMAC Control reset */
51930- SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
51931+ SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_CLR);
51932+
51933+#ifdef SK_DIAG
51934+ if (HW_FEATURE(pAC, HWF_WA_DEV_472) && Port == MAC_2) {
51935+
51936+ /* clear GMAC 1 Control reset */
51937+ SK_OUT8(IoC, MR_ADDR(MAC_1, GMAC_CTRL), (SK_U8)GMC_RST_CLR);
51938+
51939+ do {
51940+ /* set GMAC 2 Control reset */
51941+ SK_OUT8(IoC, MR_ADDR(MAC_2, GMAC_CTRL), (SK_U8)GMC_RST_SET);
51942+
51943+ /* clear GMAC 2 Control reset */
51944+ SK_OUT8(IoC, MR_ADDR(MAC_2, GMAC_CTRL), (SK_U8)GMC_RST_CLR);
51945+
51946+ SkGmPhyRead(pAC, IoC, MAC_2, PHY_MARV_ID0, &PhyId0);
51947+
51948+ SkGmPhyRead(pAC, IoC, MAC_2, PHY_MARV_ID1, &PhyId1);
51949+
51950+ SkGmPhyRead(pAC, IoC, MAC_2, PHY_MARV_INT_MASK, &Word);
51951+
51952+ } while (Word != 0 || PhyId0 != PHY_MARV_ID0_VAL ||
51953+ PhyId1 != PHY_MARV_ID1_Y2);
51954+ }
51955+#endif /* SK_DIAG */
51956
51957 #ifdef VCPU
51958 VCpuWait(2000);
51959-
51960+
51961 SK_IN32(IoC, MR_ADDR(Port, GPHY_CTRL), &DWord);
51962-
51963+
51964 SK_IN32(IoC, B0_ISRC, &DWord);
51965 #endif /* VCPU */
51966
51967@@ -1162,37 +1263,33 @@
51968 * nothing
51969 */
51970 void SkMacSoftRst(
51971-SK_AC *pAC, /* adapter context */
51972-SK_IOC IoC, /* IO context */
51973+SK_AC *pAC, /* Adapter Context */
51974+SK_IOC IoC, /* I/O Context */
51975 int Port) /* Port Index (MAC_1 + n) */
51976 {
51977- SK_GEPORT *pPrt;
51978-
51979- pPrt = &pAC->GIni.GP[Port];
51980-
51981 /* disable receiver and transmitter */
51982 SkMacRxTxDisable(pAC, IoC, Port);
51983
51984 #ifdef GENESIS
51985 if (pAC->GIni.GIGenesis) {
51986-
51987+
51988 SkXmSoftRst(pAC, IoC, Port);
51989 }
51990 #endif /* GENESIS */
51991-
51992+
51993 #ifdef YUKON
51994 if (pAC->GIni.GIYukon) {
51995-
51996+
51997 SkGmSoftRst(pAC, IoC, Port);
51998 }
51999 #endif /* YUKON */
52000
52001 /* flush the MAC's Rx and Tx FIFOs */
52002 SkMacFlushTxFifo(pAC, IoC, Port);
52003-
52004+
52005 SkMacFlushRxFifo(pAC, IoC, Port);
52006
52007- pPrt->PState = SK_PRT_STOP;
52008+ pAC->GIni.GP[Port].PState = SK_PRT_STOP;
52009
52010 } /* SkMacSoftRst */
52011
52012@@ -1207,30 +1304,32 @@
52013 * nothing
52014 */
52015 void SkMacHardRst(
52016-SK_AC *pAC, /* adapter context */
52017-SK_IOC IoC, /* IO context */
52018+SK_AC *pAC, /* Adapter Context */
52019+SK_IOC IoC, /* I/O Context */
52020 int Port) /* Port Index (MAC_1 + n) */
52021 {
52022-
52023+
52024 #ifdef GENESIS
52025 if (pAC->GIni.GIGenesis) {
52026-
52027+
52028 SkXmHardRst(pAC, IoC, Port);
52029 }
52030 #endif /* GENESIS */
52031-
52032+
52033 #ifdef YUKON
52034 if (pAC->GIni.GIYukon) {
52035-
52036+
52037 SkGmHardRst(pAC, IoC, Port);
52038 }
52039 #endif /* YUKON */
52040
52041+ pAC->GIni.GP[Port].PHWLinkUp = SK_FALSE;
52042+
52043 pAC->GIni.GP[Port].PState = SK_PRT_RESET;
52044
52045 } /* SkMacHardRst */
52046
52047-
52048+#ifndef SK_SLIM
52049 /******************************************************************************
52050 *
52051 * SkMacClearRst() - Clear the MAC reset
52052@@ -1241,27 +1340,27 @@
52053 * nothing
52054 */
52055 void SkMacClearRst(
52056-SK_AC *pAC, /* adapter context */
52057-SK_IOC IoC, /* IO context */
52058+SK_AC *pAC, /* Adapter Context */
52059+SK_IOC IoC, /* I/O Context */
52060 int Port) /* Port Index (MAC_1 + n) */
52061 {
52062-
52063+
52064 #ifdef GENESIS
52065 if (pAC->GIni.GIGenesis) {
52066-
52067+
52068 SkXmClearRst(pAC, IoC, Port);
52069 }
52070 #endif /* GENESIS */
52071-
52072+
52073 #ifdef YUKON
52074 if (pAC->GIni.GIYukon) {
52075-
52076+
52077 SkGmClearRst(pAC, IoC, Port);
52078 }
52079 #endif /* YUKON */
52080
52081 } /* SkMacClearRst */
52082-
52083+#endif /* !SK_SLIM */
52084
52085 #ifdef GENESIS
52086 /******************************************************************************
52087@@ -1279,8 +1378,8 @@
52088 * nothing
52089 */
52090 void SkXmInitMac(
52091-SK_AC *pAC, /* adapter context */
52092-SK_IOC IoC, /* IO context */
52093+SK_AC *pAC, /* Adapter Context */
52094+SK_IOC IoC, /* I/O Context */
52095 int Port) /* Port Index (MAC_1 + n) */
52096 {
52097 SK_GEPORT *pPrt;
52098@@ -1290,13 +1389,13 @@
52099 pPrt = &pAC->GIni.GP[Port];
52100
52101 if (pPrt->PState == SK_PRT_STOP) {
52102- /* Port State: SK_PRT_STOP */
52103 /* Verify that the reset bit is cleared */
52104 SK_IN16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), &SWord);
52105
52106 if ((SWord & MFF_SET_MAC_RST) != 0) {
52107 /* PState does not match HW state */
52108- SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E006, SKERR_HWI_E006MSG);
52109+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
52110+ ("SkXmInitMac: PState does not match HW state"));
52111 /* Correct it */
52112 pPrt->PState = SK_PRT_RESET;
52113 }
52114@@ -1315,7 +1414,7 @@
52115 * Must be done AFTER first access to BCOM chip.
52116 */
52117 XM_IN16(IoC, Port, XM_MMU_CMD, &SWord);
52118-
52119+
52120 XM_OUT16(IoC, Port, XM_MMU_CMD, SWord | XM_MMU_NO_PRE);
52121
52122 if (pPrt->PhyId1 == PHY_BCOM_ID1_C0) {
52123@@ -1348,7 +1447,7 @@
52124 * Disable Power Management after reset.
52125 */
52126 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &SWord);
52127-
52128+
52129 SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUX_CTRL,
52130 (SK_U16)(SWord | PHY_B_AC_DIS_PM));
52131
52132@@ -1357,7 +1456,7 @@
52133
52134 /* Dummy read the Interrupt source register */
52135 XM_IN16(IoC, Port, XM_ISRC, &SWord);
52136-
52137+
52138 /*
52139 * The auto-negotiation process starts immediately after
52140 * clearing the reset. The auto-negotiation process should be
52141@@ -1383,7 +1482,7 @@
52142 * independent. Remember this when changing.
52143 */
52144 SK_IN16(IoC, (B2_MAC_2 + Port * 8 + i * 2), &SWord);
52145-
52146+
52147 XM_OUT16(IoC, Port, (XM_SA + i * 2), SWord);
52148 }
52149
52150@@ -1401,7 +1500,7 @@
52151 SWord = SK_XM_THR_SL; /* for single port */
52152
52153 if (pAC->GIni.GIMacsFound > 1) {
52154- switch (pAC->GIni.GIPortUsage) {
52155+ switch (pPrt->PPortUsage) {
52156 case SK_RED_LINK:
52157 SWord = SK_XM_THR_REDL; /* redundant link */
52158 break;
52159@@ -1424,7 +1523,7 @@
52160 /* setup register defaults for the Rx Command Register */
52161 SWord = XM_RX_STRIP_FCS | XM_RX_LENERR_OK;
52162
52163- if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
52164+ if (pPrt->PPortUsage == SK_JUMBO_LINK) {
52165 SWord |= XM_RX_BIG_PK_OK;
52166 }
52167
52168@@ -1436,7 +1535,7 @@
52169 */
52170 SWord |= XM_RX_DIS_CEXT;
52171 }
52172-
52173+
52174 XM_OUT16(IoC, Port, XM_RX_CMD, SWord);
52175
52176 /*
52177@@ -1493,8 +1592,8 @@
52178 * nothing
52179 */
52180 void SkGmInitMac(
52181-SK_AC *pAC, /* adapter context */
52182-SK_IOC IoC, /* IO context */
52183+SK_AC *pAC, /* Adapter Context */
52184+SK_IOC IoC, /* I/O Context */
52185 int Port) /* Port Index (MAC_1 + n) */
52186 {
52187 SK_GEPORT *pPrt;
52188@@ -1505,24 +1604,29 @@
52189 pPrt = &pAC->GIni.GP[Port];
52190
52191 if (pPrt->PState == SK_PRT_STOP) {
52192- /* Port State: SK_PRT_STOP */
52193 /* Verify that the reset bit is cleared */
52194 SK_IN32(IoC, MR_ADDR(Port, GMAC_CTRL), &DWord);
52195-
52196+
52197 if ((DWord & GMC_RST_SET) != 0) {
52198 /* PState does not match HW state */
52199- SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E006, SKERR_HWI_E006MSG);
52200+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
52201+ ("SkGmInitMac: PState does not match HW state"));
52202 /* Correct it */
52203 pPrt->PState = SK_PRT_RESET;
52204 }
52205+ else {
52206+ /* enable PHY interrupts */
52207+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK,
52208+ (SK_U16)PHY_M_DEF_MSK);
52209+ }
52210 }
52211
52212 if (pPrt->PState == SK_PRT_RESET) {
52213-
52214+
52215 SkGmHardRst(pAC, IoC, Port);
52216
52217 SkGmClearRst(pAC, IoC, Port);
52218-
52219+
52220 /* Auto-negotiation ? */
52221 if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
52222 /* Auto-negotiation disabled */
52223@@ -1532,10 +1636,10 @@
52224
52225 /* disable auto-update for speed, duplex and flow-control */
52226 SWord |= GM_GPCR_AU_ALL_DIS;
52227-
52228+
52229 /* setup General Purpose Control Register */
52230 GM_OUT16(IoC, Port, GM_GP_CTRL, SWord);
52231-
52232+
52233 SWord = GM_GPCR_AU_ALL_DIS;
52234 }
52235 else {
52236@@ -1546,7 +1650,10 @@
52237 switch (pPrt->PLinkSpeed) {
52238 case SK_LSPEED_AUTO:
52239 case SK_LSPEED_1000MBPS:
52240- SWord |= GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100;
52241+ if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
52242+
52243+ SWord |= GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100;
52244+ }
52245 break;
52246 case SK_LSPEED_100MBPS:
52247 SWord |= GM_GPCR_SPEED_100;
52248@@ -1564,8 +1671,6 @@
52249 /* flow-control settings */
52250 switch (pPrt->PFlowCtrlMode) {
52251 case SK_FLOW_MODE_NONE:
52252- /* set Pause Off */
52253- SK_OUT32(IoC, MR_ADDR(Port, GMAC_CTRL), GMC_PAUSE_OFF);
52254 /* disable Tx & Rx flow-control */
52255 SWord |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
52256 break;
52257@@ -1583,24 +1688,22 @@
52258 GM_OUT16(IoC, Port, GM_GP_CTRL, SWord);
52259
52260 /* dummy read the Interrupt Source Register */
52261- SK_IN16(IoC, GMAC_IRQ_SRC, &SWord);
52262-
52263+ SK_IN16(IoC, MR_ADDR(Port, GMAC_IRQ_SRC), &SWord);
52264+
52265 #ifndef VCPU
52266- /* read Id from PHY */
52267- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_ID1, &pPrt->PhyId1);
52268-
52269 SkGmInitPhyMarv(pAC, IoC, Port, SK_FALSE);
52270-#endif /* VCPU */
52271+#endif /* !VCPU */
52272 }
52273
52274 (void)SkGmResetCounter(pAC, IoC, Port);
52275
52276 /* setup Transmit Control Register */
52277- GM_OUT16(IoC, Port, GM_TX_CTRL, TX_COL_THR(pPrt->PMacColThres));
52278+ GM_OUT16(IoC, Port, GM_TX_CTRL, (SK_U16)TX_COL_THR(pPrt->PMacColThres));
52279
52280 /* setup Receive Control Register */
52281- GM_OUT16(IoC, Port, GM_RX_CTRL, GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA |
52282- GM_RXCR_CRC_DIS);
52283+ SWord = GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA | GM_RXCR_CRC_DIS;
52284+
52285+ GM_OUT16(IoC, Port, GM_RX_CTRL, SWord);
52286
52287 /* setup Transmit Flow Control Register */
52288 GM_OUT16(IoC, Port, GM_TX_FLOW_CTRL, 0xffff);
52289@@ -1610,31 +1713,29 @@
52290 GM_IN16(IoC, Port, GM_TX_PARAM, &SWord);
52291 #endif /* VCPU */
52292
52293- SWord = TX_JAM_LEN_VAL(pPrt->PMacJamLen) |
52294- TX_JAM_IPG_VAL(pPrt->PMacJamIpgVal) |
52295- TX_IPG_JAM_DATA(pPrt->PMacJamIpgData);
52296-
52297+ SWord = (SK_U16)(TX_JAM_LEN_VAL(pPrt->PMacJamLen) |
52298+ TX_JAM_IPG_VAL(pPrt->PMacJamIpgVal) |
52299+ TX_IPG_JAM_DATA(pPrt->PMacJamIpgData) |
52300+ TX_BACK_OFF_LIM(pPrt->PMacBackOffLim));
52301+
52302 GM_OUT16(IoC, Port, GM_TX_PARAM, SWord);
52303
52304 /* configure the Serial Mode Register */
52305-#ifdef VCPU
52306- GM_IN16(IoC, Port, GM_SERIAL_MODE, &SWord);
52307-#endif /* VCPU */
52308-
52309- SWord = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(pPrt->PMacIpgData);
52310+ SWord = (SK_U16)(DATA_BLIND_VAL(pPrt->PMacDataBlind) |
52311+ GM_SMOD_VLAN_ENA | IPG_DATA_VAL(pPrt->PMacIpgData));
52312
52313 if (pPrt->PMacLimit4) {
52314 /* reset of collision counter after 4 consecutive collisions */
52315 SWord |= GM_SMOD_LIMIT_4;
52316 }
52317
52318- if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
52319+ if (pPrt->PPortUsage == SK_JUMBO_LINK) {
52320 /* enable jumbo mode (Max. Frame Length = 9018) */
52321 SWord |= GM_SMOD_JUMBO_ENA;
52322 }
52323-
52324+
52325 GM_OUT16(IoC, Port, GM_SERIAL_MODE, SWord);
52326-
52327+
52328 /*
52329 * configure the GMACs Station Addresses
52330 * in PROM you can find our addresses at:
52331@@ -1663,17 +1764,17 @@
52332 else {
52333 GM_OUT16(IoC, Port, (GM_SRC_ADDR_1L + i * 4), SWord);
52334 }
52335-#else
52336+#else
52337 GM_OUT16(IoC, Port, (GM_SRC_ADDR_1L + i * 4), SWord);
52338 #endif /* WA_DEV_16 */
52339-
52340+
52341 /* virtual address: will be used for data */
52342 SK_IN16(IoC, (B2_MAC_1 + Port * 8 + i * 2), &SWord);
52343
52344 GM_OUT16(IoC, Port, (GM_SRC_ADDR_2L + i * 4), SWord);
52345-
52346+
52347 /* reset Multicast filtering Hash registers 1-3 */
52348- GM_OUT16(IoC, Port, GM_MC_ADDR_H1 + 4*i, 0);
52349+ GM_OUT16(IoC, Port, GM_MC_ADDR_H1 + i * 4, 0);
52350 }
52351
52352 /* reset Multicast filtering Hash register 4 */
52353@@ -1684,18 +1785,6 @@
52354 GM_OUT16(IoC, Port, GM_RX_IRQ_MSK, 0);
52355 GM_OUT16(IoC, Port, GM_TR_IRQ_MSK, 0);
52356
52357-#if defined(SK_DIAG) || defined(DEBUG)
52358- /* read General Purpose Status */
52359- GM_IN16(IoC, Port, GM_GP_STAT, &SWord);
52360-
52361- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
52362- ("MAC Stat Reg.=0x%04X\n", SWord));
52363-#endif /* SK_DIAG || DEBUG */
52364-
52365-#ifdef SK_DIAG
52366- c_print("MAC Stat Reg=0x%04X\n", SWord);
52367-#endif /* SK_DIAG */
52368-
52369 } /* SkGmInitMac */
52370 #endif /* YUKON */
52371
52372@@ -1714,8 +1803,8 @@
52373 * nothing
52374 */
52375 void SkXmInitDupMd(
52376-SK_AC *pAC, /* adapter context */
52377-SK_IOC IoC, /* IO context */
52378+SK_AC *pAC, /* Adapter Context */
52379+SK_IOC IoC, /* I/O Context */
52380 int Port) /* Port Index (MAC_1 + n) */
52381 {
52382 switch (pAC->GIni.GP[Port].PLinkModeStatus) {
52383@@ -1762,8 +1851,8 @@
52384 * nothing
52385 */
52386 void SkXmInitPauseMd(
52387-SK_AC *pAC, /* adapter context */
52388-SK_IOC IoC, /* IO context */
52389+SK_AC *pAC, /* Adapter Context */
52390+SK_IOC IoC, /* I/O Context */
52391 int Port) /* Port Index (MAC_1 + n) */
52392 {
52393 SK_GEPORT *pPrt;
52394@@ -1773,11 +1862,11 @@
52395 pPrt = &pAC->GIni.GP[Port];
52396
52397 XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
52398-
52399+
52400 if (pPrt->PFlowCtrlStatus == SK_FLOW_STAT_NONE ||
52401 pPrt->PFlowCtrlStatus == SK_FLOW_STAT_LOC_SEND) {
52402
52403- /* Disable Pause Frame Reception */
52404+ /* disable Pause Frame Reception */
52405 Word |= XM_MMU_IGN_PF;
52406 }
52407 else {
52408@@ -1785,10 +1874,10 @@
52409 * enabling pause frame reception is required for 1000BT
52410 * because the XMAC is not reset if the link is going down
52411 */
52412- /* Enable Pause Frame Reception */
52413+ /* enable Pause Frame Reception */
52414 Word &= ~XM_MMU_IGN_PF;
52415- }
52416-
52417+ }
52418+
52419 XM_OUT16(IoC, Port, XM_MMU_CMD, Word);
52420
52421 XM_IN32(IoC, Port, XM_MODE, &DWord);
52422@@ -1811,10 +1900,10 @@
52423 /* remember this value is defined in big endian (!) */
52424 XM_OUT16(IoC, Port, XM_MAC_PTIME, 0xffff);
52425
52426- /* Set Pause Mode in Mode Register */
52427+ /* set Pause Mode in Mode Register */
52428 DWord |= XM_PAUSE_MODE;
52429
52430- /* Set Pause Mode in MAC Rx FIFO */
52431+ /* set Pause Mode in MAC Rx FIFO */
52432 SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
52433 }
52434 else {
52435@@ -1822,13 +1911,13 @@
52436 * disable pause frame generation is required for 1000BT
52437 * because the XMAC is not reset if the link is going down
52438 */
52439- /* Disable Pause Mode in Mode Register */
52440+ /* disable Pause Mode in Mode Register */
52441 DWord &= ~XM_PAUSE_MODE;
52442
52443- /* Disable Pause Mode in MAC Rx FIFO */
52444+ /* disable Pause Mode in MAC Rx FIFO */
52445 SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
52446 }
52447-
52448+
52449 XM_OUT32(IoC, Port, XM_MODE, DWord);
52450 } /* SkXmInitPauseMd*/
52451
52452@@ -1845,8 +1934,8 @@
52453 * nothing
52454 */
52455 static void SkXmInitPhyXmac(
52456-SK_AC *pAC, /* adapter context */
52457-SK_IOC IoC, /* IO context */
52458+SK_AC *pAC, /* Adapter Context */
52459+SK_IOC IoC, /* I/O Context */
52460 int Port, /* Port Index (MAC_1 + n) */
52461 SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */
52462 {
52463@@ -1855,12 +1944,12 @@
52464
52465 pPrt = &pAC->GIni.GP[Port];
52466 Ctrl = 0;
52467-
52468+
52469 /* Auto-negotiation ? */
52470 if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
52471 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
52472 ("InitPhyXmac: no auto-negotiation Port %d\n", Port));
52473- /* Set DuplexMode in Config register */
52474+ /* set DuplexMode in Config register */
52475 if (pPrt->PLinkMode == SK_LMODE_FULL) {
52476 Ctrl |= PHY_CT_DUP_MD;
52477 }
52478@@ -1873,9 +1962,9 @@
52479 else {
52480 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
52481 ("InitPhyXmac: with auto-negotiation Port %d\n", Port));
52482- /* Set Auto-negotiation advertisement */
52483+ /* set Auto-negotiation advertisement */
52484
52485- /* Set Full/half duplex capabilities */
52486+ /* set Full/half duplex capabilities */
52487 switch (pPrt->PLinkMode) {
52488 case SK_LMODE_AUTOHALF:
52489 Ctrl |= PHY_X_AN_HD;
52490@@ -1891,7 +1980,7 @@
52491 SKERR_HWI_E015MSG);
52492 }
52493
52494- /* Set Flow-control capabilities */
52495+ /* set Flow-control capabilities */
52496 switch (pPrt->PFlowCtrlMode) {
52497 case SK_FLOW_MODE_NONE:
52498 Ctrl |= PHY_X_P_NO_PAUSE;
52499@@ -1918,7 +2007,7 @@
52500 }
52501
52502 if (DoLoop) {
52503- /* Set the Phy Loopback bit, too */
52504+ /* set the Phy Loopback bit, too */
52505 Ctrl |= PHY_CT_LOOP;
52506 }
52507
52508@@ -1939,8 +2028,8 @@
52509 * nothing
52510 */
52511 static void SkXmInitPhyBcom(
52512-SK_AC *pAC, /* adapter context */
52513-SK_IOC IoC, /* IO context */
52514+SK_AC *pAC, /* Adapter Context */
52515+SK_IOC IoC, /* I/O Context */
52516 int Port, /* Port Index (MAC_1 + n) */
52517 SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */
52518 {
52519@@ -1962,7 +2051,7 @@
52520 /* manually Master/Slave ? */
52521 if (pPrt->PMSMode != SK_MS_MODE_AUTO) {
52522 Ctrl2 |= PHY_B_1000C_MSE;
52523-
52524+
52525 if (pPrt->PMSMode == SK_MS_MODE_MASTER) {
52526 Ctrl2 |= PHY_B_1000C_MSC;
52527 }
52528@@ -1971,7 +2060,7 @@
52529 if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
52530 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
52531 ("InitPhyBcom: no auto-negotiation Port %d\n", Port));
52532- /* Set DuplexMode in Config register */
52533+ /* set DuplexMode in Config register */
52534 if (pPrt->PLinkMode == SK_LMODE_FULL) {
52535 Ctrl1 |= PHY_CT_DUP_MD;
52536 }
52537@@ -1989,7 +2078,7 @@
52538 else {
52539 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
52540 ("InitPhyBcom: with auto-negotiation Port %d\n", Port));
52541- /* Set Auto-negotiation advertisement */
52542+ /* set Auto-negotiation advertisement */
52543
52544 /*
52545 * Workaround BCOM Errata #1 for the C5 type.
52546@@ -1997,8 +2086,8 @@
52547 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
52548 */
52549 Ctrl2 |= PHY_B_1000C_RD;
52550-
52551- /* Set Full/half duplex capabilities */
52552+
52553+ /* set Full/half duplex capabilities */
52554 switch (pPrt->PLinkMode) {
52555 case SK_LMODE_AUTOHALF:
52556 Ctrl2 |= PHY_B_1000C_AHD;
52557@@ -2014,7 +2103,7 @@
52558 SKERR_HWI_E015MSG);
52559 }
52560
52561- /* Set Flow-control capabilities */
52562+ /* set Flow-control capabilities */
52563 switch (pPrt->PFlowCtrlMode) {
52564 case SK_FLOW_MODE_NONE:
52565 Ctrl3 |= PHY_B_P_NO_PAUSE;
52566@@ -2036,27 +2125,27 @@
52567 /* Restart Auto-negotiation */
52568 Ctrl1 |= PHY_CT_ANE | PHY_CT_RE_CFG;
52569 }
52570-
52571+
52572 /* Initialize LED register here? */
52573 /* No. Please do it in SkDgXmitLed() (if required) and swap
52574- init order of LEDs and XMAC. (MAl) */
52575-
52576+ init order of LEDs and XMAC. (MAl) */
52577+
52578 /* Write 1000Base-T Control Register */
52579 SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_1000T_CTRL, Ctrl2);
52580 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
52581- ("Set 1000B-T Ctrl Reg=0x%04X\n", Ctrl2));
52582-
52583+ ("Set 1000B-T Ctrl Reg = 0x%04X\n", Ctrl2));
52584+
52585 /* Write AutoNeg Advertisement Register */
52586 SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUNE_ADV, Ctrl3);
52587 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
52588- ("Set Auto-Neg.Adv.Reg=0x%04X\n", Ctrl3));
52589-
52590+ ("Set Auto-Neg.Adv.Reg = 0x%04X\n", Ctrl3));
52591+
52592 if (DoLoop) {
52593- /* Set the Phy Loopback bit, too */
52594+ /* set the Phy Loopback bit, too */
52595 Ctrl1 |= PHY_CT_LOOP;
52596 }
52597
52598- if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
52599+ if (pPrt->PPortUsage == SK_JUMBO_LINK) {
52600 /* configure FIFO to high latency for transmission of ext. packets */
52601 Ctrl4 |= PHY_B_PEC_HIGH_LA;
52602
52603@@ -2068,45 +2157,41 @@
52604
52605 /* Configure LED Traffic Mode and Jumbo Frame usage if specified */
52606 SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_P_EXT_CTRL, Ctrl4);
52607-
52608+
52609 /* Write to the Phy control register */
52610 SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_CTRL, Ctrl1);
52611 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
52612- ("PHY Control Reg=0x%04X\n", Ctrl1));
52613+ ("PHY Control Reg = 0x%04X\n", Ctrl1));
52614 } /* SkXmInitPhyBcom */
52615 #endif /* GENESIS */
52616
52617
52618 #ifdef YUKON
52619-#ifndef SK_SLIM
52620+#ifdef SK_PHY_LP_MODE
52621 /******************************************************************************
52622 *
52623 * SkGmEnterLowPowerMode()
52624 *
52625- * Description:
52626+ * Description:
52627 * This function sets the Marvell Alaska PHY to the low power mode
52628 * given by parameter mode.
52629 * The following low power modes are available:
52630- *
52631- * - Coma Mode (Deep Sleep):
52632- * Power consumption: ~15 - 30 mW
52633+ *
52634+ * - COMA Mode (Deep Sleep):
52635 * The PHY cannot wake up on its own.
52636 *
52637 * - IEEE 22.2.4.1.5 compatible power down mode
52638- * Power consumption: ~240 mW
52639 * The PHY cannot wake up on its own.
52640 *
52641 * - energy detect mode
52642- * Power consumption: ~160 mW
52643 * The PHY can wake up on its own by detecting activity
52644 * on the CAT 5 cable.
52645 *
52646 * - energy detect plus mode
52647- * Power consumption: ~150 mW
52648 * The PHY can wake up on its own by detecting activity
52649 * on the CAT 5 cable.
52650 * Connected devices can be woken up by sending normal link
52651- * pulses every one second.
52652+ * pulses every second.
52653 *
52654 * Note:
52655 *
52656@@ -2115,113 +2200,298 @@
52657 * 1: error
52658 */
52659 int SkGmEnterLowPowerMode(
52660-SK_AC *pAC, /* adapter context */
52661-SK_IOC IoC, /* IO context */
52662+SK_AC *pAC, /* Adapter Context */
52663+SK_IOC IoC, /* I/O Context */
52664 int Port, /* Port Index (e.g. MAC_1) */
52665 SK_U8 Mode) /* low power mode */
52666 {
52667+ SK_U8 LastMode;
52668+ SK_U8 Byte;
52669 SK_U16 Word;
52670+ SK_U16 ClkDiv;
52671 SK_U32 DWord;
52672- SK_U8 LastMode;
52673+ SK_U32 PowerDownBit;
52674+ int ChipId;
52675 int Ret = 0;
52676
52677- if (pAC->GIni.GIYukonLite &&
52678- pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3) {
52679+ if (!(CHIP_ID_YUKON_2(pAC) || (pAC->GIni.GIYukonLite &&
52680+ pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3))) {
52681
52682- /* save current power mode */
52683- LastMode = pAC->GIni.GP[Port].PPhyPowerState;
52684- pAC->GIni.GP[Port].PPhyPowerState = Mode;
52685-
52686- switch (Mode) {
52687- /* coma mode (deep sleep) */
52688- case PHY_PM_DEEP_SLEEP:
52689- /* setup General Purpose Control Register */
52690- GM_OUT16(IoC, 0, GM_GP_CTRL, GM_GPCR_FL_PASS |
52691- GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
52692-
52693- /* apply COMA mode workaround */
52694- SkGmPhyWrite(pAC, IoC, Port, 29, 0x001f);
52695- SkGmPhyWrite(pAC, IoC, Port, 30, 0xfff3);
52696-
52697- SK_IN32(IoC, PCI_C(PCI_OUR_REG_1), &DWord);
52698-
52699- SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
52700-
52701- /* Set PHY to Coma Mode */
52702- SK_OUT32(IoC, PCI_C(PCI_OUR_REG_1), DWord | PCI_PHY_COMA);
52703-
52704- SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
52705-
52706- break;
52707-
52708- /* IEEE 22.2.4.1.5 compatible power down mode */
52709- case PHY_PM_IEEE_POWER_DOWN:
52710- /*
52711- * - disable MAC 125 MHz clock
52712- * - allow MAC power down
52713- */
52714- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
52715- Word |= PHY_M_PC_DIS_125CLK;
52716- Word &= ~PHY_M_PC_MAC_POW_UP;
52717- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
52718+ return(1);
52719+ }
52720
52721- /*
52722- * register changes must be followed by a software
52723- * reset to take effect
52724- */
52725- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word);
52726- Word |= PHY_CT_RESET;
52727- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word);
52728-
52729- /* switch IEEE compatible power down mode on */
52730- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word);
52731- Word |= PHY_CT_PDOWN;
52732- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word);
52733- break;
52734+ /* save current power mode */
52735+ LastMode = pAC->GIni.GP[Port].PPhyPowerState;
52736+ pAC->GIni.GP[Port].PPhyPowerState = Mode;
52737
52738- /* energy detect and energy detect plus mode */
52739- case PHY_PM_ENERGY_DETECT:
52740- case PHY_PM_ENERGY_DETECT_PLUS:
52741- /*
52742- * - disable MAC 125 MHz clock
52743- */
52744- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
52745- Word |= PHY_M_PC_DIS_125CLK;
52746- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
52747-
52748- /* activate energy detect mode 1 */
52749- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
52750-
52751- /* energy detect mode */
52752- if (Mode == PHY_PM_ENERGY_DETECT) {
52753- Word |= PHY_M_PC_EN_DET;
52754+ ChipId = pAC->GIni.GIChipId;
52755+
52756+ SK_DBG_MSG(pAC, SK_DBGMOD_POWM, SK_DBGCAT_CTRL,
52757+ ("SkGmEnterLowPowerMode: %u\n", Mode));
52758+
52759+ /* release GPHY Control reset */
52760+ SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_CLR);
52761+
52762+ /* release GMAC reset */
52763+ SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), (SK_U8)GMC_RST_CLR);
52764+
52765+ if (ChipId == CHIP_ID_YUKON_EC_U) {
52766+ /* select page 2 to access MAC control register */
52767+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 2);
52768+
52769+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
52770+ /* allow GMII Power Down */
52771+ Word &= ~PHY_M_MAC_GMIF_PUP;
52772+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
52773+
52774+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0);
52775+ }
52776+
52777+ switch (Mode) {
52778+ /* COMA mode (deep sleep) */
52779+ case PHY_PM_DEEP_SLEEP:
52780+ /* setup General Purpose Control Register */
52781+ GM_OUT16(IoC, Port, GM_GP_CTRL, GM_GPCR_FL_PASS |
52782+ GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
52783+
52784+ if (CHIP_ID_YUKON_2(pAC)) {
52785+ /* set power down bit */
52786+ PowerDownBit = (Port == MAC_1) ? PCI_Y2_PHY1_POWD :
52787+ PCI_Y2_PHY2_POWD;
52788+
52789+ if (ChipId != CHIP_ID_YUKON_EC) {
52790+
52791+ if (ChipId == CHIP_ID_YUKON_EC_U) {
52792+
52793+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
52794+ /* enable Power Down */
52795+ Word |= PHY_M_PC_POW_D_ENA;
52796+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
52797+ }
52798+
52799+ /* set IEEE compatible Power Down Mode (dev. #4.99) */
52800+ Ret = SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PHY_CT_PDOWN);
52801+ }
52802+ }
52803+ else {
52804+ /* apply COMA mode workaround */
52805+ (void)SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_ADDR, 0x001f);
52806+
52807+ Ret = SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xfff3);
52808+
52809+ PowerDownBit = PCI_PHY_COMA;
52810+ }
52811+
52812+ SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
52813+
52814+ SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_1), &DWord);
52815+
52816+ /* set PHY to PowerDown/COMA Mode */
52817+ SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_1), DWord | PowerDownBit);
52818+
52819+ /* check if this routine was called from a for() loop */
52820+ if (pAC->GIni.GIMacsFound == 1 || Port == MAC_2) {
52821+
52822+ /* ASF system clock stopped */
52823+ SK_OUT8(IoC, B28_Y2_ASF_STAT_CMD, (SK_U8)Y2_ASF_CLK_HALT);
52824+
52825+ if (ChipId == CHIP_ID_YUKON_EC_U) {
52826+ /* set GPHY Control reset */
52827+ SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_SET);
52828+
52829+ /* additional power saving measurements */
52830+ SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_4), &DWord);
52831+
52832+ /* set gating core clock for LTSSM in L1 state */
52833+ DWord |= (P_PEX_LTSSM_STAT(P_PEX_LTSSM_L1_STAT) |
52834+ /* auto clock gated scheme controlled by CLKREQ */
52835+ P_ASPM_A1_MODE_SELECT |
52836+ /* enable Gate Root Core Clock */
52837+ P_CLK_GATE_ROOT_COR_ENA);
52838+
52839+ if (HW_FEATURE(pAC, HWF_WA_DEV_4200)) {
52840+ /* Enable Clock Power Management (CLKREQ) */
52841+ SK_IN16(IoC, PCI_C(pAC, PEX_LNK_CTRL), &Word);
52842+ Word |= PEX_LC_CLK_PM_ENA;
52843+ SK_OUT16(IoC, PCI_C(pAC, PEX_LNK_CTRL), Word);
52844 }
52845- /* energy detect plus mode */
52846 else {
52847- Word |= PHY_M_PC_EN_DET_PLUS;
52848+ /* Force CLKREQ Enable in Our4 (A1b only) */
52849+ DWord |= P_ASPM_FORCE_CLKREQ_ENA;
52850 }
52851
52852- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
52853+ SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_4), DWord);
52854
52855- /*
52856- * reinitialize the PHY to force a software reset
52857- * which is necessary after the register settings
52858- * for the energy detect modes.
52859- * Furthermore reinitialisation prevents that the
52860- * PHY is running out of a stable state.
52861- */
52862- SkGmInitPhyMarv(pAC, IoC, Port, SK_FALSE);
52863- break;
52864+ /* set Mask Register for Release/Gate Clock */
52865+ SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_5),
52866+ P_REL_PCIE_EXIT_L1_ST | P_GAT_PCIE_ENTER_L1_ST |
52867+ P_REL_PCIE_RX_EX_IDLE | P_GAT_PCIE_RX_EL_IDLE |
52868+ P_REL_GPHY_LINK_UP | P_GAT_GPHY_LINK_DOWN);
52869+ }
52870
52871- /* don't change current power mode */
52872- default:
52873- pAC->GIni.GP[Port].PPhyPowerState = LastMode;
52874- Ret = 1;
52875- break;
52876+ if (HW_FEATURE(pAC, HWF_RED_CORE_CLK_SUP)) {
52877+ /* divide clock by 4 only for Yukon-EC */
52878+ ClkDiv = (ChipId == CHIP_ID_YUKON_EC) ? 1 : 0;
52879+
52880+ /* on Yukon-2 clock select value is 31 */
52881+ DWord = (ChipId == CHIP_ID_YUKON_XL) ?
52882+ (Y2_CLK_DIV_VAL_2(0) | Y2_CLK_SEL_VAL_2(31)) :
52883+ Y2_CLK_DIV_VAL(ClkDiv);
52884+
52885+ /* check for Yukon-2 dual port PCI-Express adapter */
52886+ if (!(pAC->GIni.GIMacsFound == 2 &&
52887+ pAC->GIni.GIPciBus == SK_PEX_BUS)) {
52888+ /* enable Core Clock Division */
52889+ DWord |= Y2_CLK_DIV_ENA;
52890+ }
52891+
52892+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
52893+ ("Set Core Clock: 0x%08X\n", DWord));
52894+
52895+ /* reduce Core Clock Frequency */
52896+ SK_OUT32(IoC, B2_Y2_CLK_CTRL, DWord);
52897+ }
52898+
52899+ if (HW_FEATURE(pAC, HWF_CLK_GATING_ENABLE)) {
52900+ /* check for Yukon-2 Rev. A2 */
52901+ if (ChipId == CHIP_ID_YUKON_XL &&
52902+ pAC->GIni.GIChipRev > CHIP_REV_YU_XL_A1) {
52903+ /* enable bits are inverted */
52904+ Byte = 0;
52905+ }
52906+ else {
52907+ Byte = (SK_U8)(Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
52908+ Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
52909+ Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
52910+ }
52911+
52912+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
52913+ ("Set Clock Gating: 0x%02X\n", Byte));
52914+
52915+ /* disable MAC/PHY, PCI and Core Clock for both Links */
52916+ SK_OUT8(IoC, B2_Y2_CLK_GATE, Byte);
52917+ }
52918+
52919+ if (pAC->GIni.GIVauxAvail) {
52920+ /* switch power to VAUX */
52921+ SK_OUT8(IoC, B0_POWER_CTRL, (SK_U8)(PC_VAUX_ENA | PC_VCC_ENA |
52922+ PC_VAUX_ON | PC_VCC_OFF));
52923+ }
52924+#ifdef DEBUG
52925+ SK_IN32(IoC, B0_CTST, &DWord);
52926+
52927+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
52928+ ("Ctrl/Stat & Switch: 0x%08x\n", DWord));
52929+#endif /* DEBUG */
52930+
52931+ if (pAC->GIni.GILevel != SK_INIT_IO &&
52932+ pAC->GIni.GIMacsFound == 1 &&
52933+ pAC->GIni.GIPciBus == SK_PEX_BUS) {
52934+
52935+ if (ChipId == CHIP_ID_YUKON_EC_U) {
52936+
52937+#ifdef PCI_E_L1_STATE
52938+ SK_IN16(IoC, PCI_C(pAC, PCI_OUR_REG_1), &Word);
52939+ /* force to PCIe L1 */
52940+ Word |= (SK_U16)PCI_FORCE_PEX_L1;
52941+ SK_OUT16(IoC, PCI_C(pAC, PCI_OUR_REG_1), Word);
52942+#endif /* PCI_E_L1_STATE */
52943+ }
52944+ else {
52945+ /* switch to D1 state */
52946+ SK_OUT8(IoC, PCI_C(pAC, PCI_PM_CTL_STS), PCI_PM_STATE_D1);
52947+ }
52948+ }
52949 }
52950- }
52951- /* low power modes are not supported by this chip */
52952- else {
52953+
52954+ break;
52955+
52956+ /* IEEE 22.2.4.1.5 compatible power down mode */
52957+ case PHY_PM_IEEE_POWER_DOWN:
52958+
52959+ Ret = SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
52960+
52961+ Word |= PHY_M_PC_POL_R_DIS;
52962+
52963+ if (!CHIP_ID_YUKON_2(pAC)) {
52964+ /* disable MAC 125 MHz clock */
52965+ Word |= PHY_M_PC_DIS_125CLK;
52966+ Word &= ~PHY_M_PC_MAC_POW_UP;
52967+ }
52968+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
52969+
52970+ /* these register changes must be followed by a software reset */
52971+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word);
52972+
52973+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word | PHY_CT_RESET);
52974+
52975+ /* switch IEEE compatible power down mode on */
52976+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word | PHY_CT_PDOWN);
52977+
52978+ break;
52979+
52980+ /* energy detect and energy detect plus mode */
52981+ case PHY_PM_ENERGY_DETECT:
52982+ case PHY_PM_ENERGY_DETECT_PLUS:
52983+
52984+ Ret = SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
52985+
52986+ Word |= PHY_M_PC_POL_R_DIS;
52987+
52988+ if (!CHIP_ID_YUKON_2(pAC)) {
52989+ /* disable MAC 125 MHz clock */
52990+ Word |= PHY_M_PC_DIS_125CLK;
52991+ }
52992+
52993+ if (ChipId == CHIP_ID_YUKON_FE) {
52994+ /* enable Energy Detect (sense & pulse) */
52995+ Word |= PHY_M_PC_ENA_ENE_DT;
52996+ }
52997+ else {
52998+ /* clear energy detect mode bits */
52999+ Word &= ~PHY_M_PC_EN_DET_MSK;
53000+
53001+ Word |= (Mode == PHY_PM_ENERGY_DETECT) ? PHY_M_PC_EN_DET :
53002+ PHY_M_PC_EN_DET_PLUS;
53003+ }
53004+
53005+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
53006+
53007+ /* these register changes must be followed by a software reset */
53008+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word);
53009+ Word |= PHY_CT_RESET;
53010+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word);
53011+
53012+ if (ChipId == CHIP_ID_YUKON_EC_U) {
53013+ /* additional power saving measurements */
53014+ SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_4), &DWord);
53015+
53016+ /* set gating core clock for LTSSM in L1 state */
53017+ DWord |= (P_PEX_LTSSM_STAT(P_PEX_LTSSM_L1_STAT) |
53018+ /* Enable Gate Root Core Clock */
53019+ P_CLK_GATE_ROOT_COR_ENA);
53020+
53021+ SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_4), DWord);
53022+
53023+ /* set Mask Register for Release/Gate Clock */
53024+ SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_5),
53025+ P_REL_PCIE_EXIT_L1_ST | P_GAT_PCIE_ENTER_L1_ST |
53026+ P_REL_PCIE_RX_EX_IDLE | P_GAT_PCIE_RX_EL_IDLE |
53027+ P_REL_GPHY_LINK_UP | P_GAT_GPHY_LINK_DOWN);
53028+
53029+#ifdef PCI_E_L1_STATE
53030+ SK_IN16(IoC, PCI_C(pAC, PCI_OUR_REG_1), &Word);
53031+ /* enable PCIe L1 on GPHY link down */
53032+ Word |= (SK_U16)PCI_ENA_GPHY_LNK;
53033+ SK_OUT16(IoC, PCI_C(pAC, PCI_OUR_REG_1), Word);
53034+#endif /* PCI_E_L1_STATE */
53035+ }
53036+
53037+ break;
53038+
53039+ /* don't change current power mode */
53040+ default:
53041+ pAC->GIni.GP[Port].PPhyPowerState = LastMode;
53042 Ret = 1;
53043 }
53044
53045@@ -2233,7 +2503,7 @@
53046 *
53047 * SkGmLeaveLowPowerMode()
53048 *
53049- * Description:
53050+ * Description:
53051 * Leave the current low power mode and switch to normal mode
53052 *
53053 * Note:
53054@@ -2243,115 +2513,169 @@
53055 * 1: error
53056 */
53057 int SkGmLeaveLowPowerMode(
53058-SK_AC *pAC, /* adapter context */
53059-SK_IOC IoC, /* IO context */
53060+SK_AC *pAC, /* Adapter Context */
53061+SK_IOC IoC, /* I/O Context */
53062 int Port) /* Port Index (e.g. MAC_1) */
53063 {
53064 SK_U32 DWord;
53065+ SK_U32 PowerDownBit;
53066 SK_U16 Word;
53067 SK_U8 LastMode;
53068+ int ChipId;
53069 int Ret = 0;
53070
53071- if (pAC->GIni.GIYukonLite &&
53072- pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3) {
53073+ if (!(CHIP_ID_YUKON_2(pAC) || (pAC->GIni.GIYukonLite &&
53074+ pAC->GIni.GIChipRev >= CHIP_REV_YU_LITE_A3))) {
53075
53076- /* save current power mode */
53077- LastMode = pAC->GIni.GP[Port].PPhyPowerState;
53078- pAC->GIni.GP[Port].PPhyPowerState = PHY_PM_OPERATIONAL_MODE;
53079-
53080- switch (LastMode) {
53081- /* coma mode (deep sleep) */
53082- case PHY_PM_DEEP_SLEEP:
53083- SK_IN32(IoC, PCI_C(PCI_OUR_REG_1), &DWord);
53084-
53085- SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
53086-
53087- /* Release PHY from Coma Mode */
53088- SK_OUT32(IoC, PCI_C(PCI_OUR_REG_1), DWord & ~PCI_PHY_COMA);
53089-
53090- SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
53091-
53092- SK_IN32(IoC, B2_GP_IO, &DWord);
53093-
53094- /* set to output */
53095- DWord |= (GP_DIR_9 | GP_IO_9);
53096-
53097- /* set PHY reset */
53098- SK_OUT32(IoC, B2_GP_IO, DWord);
53099-
53100- DWord &= ~GP_IO_9; /* clear PHY reset (active high) */
53101-
53102- /* clear PHY reset */
53103- SK_OUT32(IoC, B2_GP_IO, DWord);
53104- break;
53105-
53106- /* IEEE 22.2.4.1.5 compatible power down mode */
53107- case PHY_PM_IEEE_POWER_DOWN:
53108- /*
53109- * - enable MAC 125 MHz clock
53110- * - set MAC power up
53111- */
53112- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
53113- Word &= ~PHY_M_PC_DIS_125CLK;
53114- Word |= PHY_M_PC_MAC_POW_UP;
53115- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
53116+ return(1);
53117+ }
53118
53119- /*
53120- * register changes must be followed by a software
53121- * reset to take effect
53122- */
53123- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word);
53124- Word |= PHY_CT_RESET;
53125- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word);
53126-
53127- /* switch IEEE compatible power down mode off */
53128- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word);
53129- Word &= ~PHY_CT_PDOWN;
53130- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word);
53131- break;
53132+ /* save current power mode */
53133+ LastMode = pAC->GIni.GP[Port].PPhyPowerState;
53134+ pAC->GIni.GP[Port].PPhyPowerState = PHY_PM_OPERATIONAL_MODE;
53135
53136- /* energy detect and energy detect plus mode */
53137- case PHY_PM_ENERGY_DETECT:
53138- case PHY_PM_ENERGY_DETECT_PLUS:
53139- /*
53140- * - enable MAC 125 MHz clock
53141- */
53142- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
53143- Word &= ~PHY_M_PC_DIS_125CLK;
53144- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
53145-
53146- /* disable energy detect mode */
53147- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
53148- Word &= ~PHY_M_PC_EN_DET_MSK;
53149- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
53150+ ChipId = pAC->GIni.GIChipId;
53151
53152- /*
53153- * reinitialize the PHY to force a software reset
53154- * which is necessary after the register settings
53155- * for the energy detect modes.
53156- * Furthermore reinitialisation prevents that the
53157- * PHY is running out of a stable state.
53158- */
53159- SkGmInitPhyMarv(pAC, IoC, Port, SK_FALSE);
53160- break;
53161+ SK_DBG_MSG(pAC, SK_DBGMOD_POWM, SK_DBGCAT_CTRL,
53162+ ("SkGmLeaveLowPowerMode: %u\n", LastMode));
53163
53164- /* don't change current power mode */
53165- default:
53166- pAC->GIni.GP[Port].PPhyPowerState = LastMode;
53167- Ret = 1;
53168- break;
53169+ switch (LastMode) {
53170+ /* COMA mode (deep sleep) */
53171+ case PHY_PM_DEEP_SLEEP:
53172+
53173+ if (ChipId == CHIP_ID_YUKON_EC_U) {
53174+#ifdef PCI_E_L1_STATE
53175+ /* set to default value (leave PCIe L1) */
53176+ SkPciWriteCfgWord(pAC, PCI_OUR_REG_1, 0);
53177+#endif /* PCI_E_L1_STATE */
53178+
53179+ SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_4), &DWord);
53180+
53181+ DWord &= P_ASPM_CONTROL_MSK;
53182+ /* set all bits to 0 except bits 15..12 */
53183+ SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_4), DWord);
53184+
53185+ /* set to default value */
53186+ SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_5), 0);
53187 }
53188- }
53189- /* low power modes are not supported by this chip */
53190- else {
53191+ else {
53192+ SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &Word);
53193+
53194+ /* reset all DState bits */
53195+ Word &= ~(PCI_PM_STATE_MSK);
53196+
53197+ /* switch to D0 state */
53198+ SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, Word);
53199+ }
53200+
53201+ SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
53202+
53203+ if (CHIP_ID_YUKON_2(pAC)) {
53204+ /* disable Core Clock Division */
53205+ SK_OUT32(IoC, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
53206+
53207+ /* set power down bit */
53208+ PowerDownBit = (Port == MAC_1) ? PCI_Y2_PHY1_POWD :
53209+ PCI_Y2_PHY2_POWD;
53210+ }
53211+ else {
53212+ PowerDownBit = PCI_PHY_COMA;
53213+ }
53214+
53215+ SK_IN32(IoC, PCI_C(pAC, PCI_OUR_REG_1), &DWord);
53216+
53217+ /* Release PHY from PowerDown/COMA Mode */
53218+ SK_OUT32(IoC, PCI_C(pAC, PCI_OUR_REG_1), DWord & ~PowerDownBit);
53219+
53220+ SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
53221+
53222+ if (CHIP_ID_YUKON_2(pAC)) {
53223+
53224+ if (ChipId == CHIP_ID_YUKON_FE) {
53225+ /* release IEEE compatible Power Down Mode */
53226+ Ret = SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PHY_CT_ANE);
53227+ }
53228+ else if (ChipId == CHIP_ID_YUKON_EC_U) {
53229+ /* release GPHY Control reset */
53230+ SK_OUT8(IoC, MR_ADDR(Port, GPHY_CTRL), (SK_U8)GPC_RST_CLR);
53231+ }
53232+ }
53233+ else {
53234+ SK_IN32(IoC, B2_GP_IO, &DWord);
53235+
53236+ /* set to output */
53237+ DWord |= (GP_DIR_9 | GP_IO_9);
53238+
53239+ /* set PHY reset */
53240+ SK_OUT32(IoC, B2_GP_IO, DWord);
53241+
53242+ DWord &= ~GP_IO_9; /* clear PHY reset (active high) */
53243+
53244+ /* clear PHY reset */
53245+ SK_OUT32(IoC, B2_GP_IO, DWord);
53246+ }
53247+
53248+ break;
53249+
53250+ /* IEEE 22.2.4.1.5 compatible power down mode */
53251+ case PHY_PM_IEEE_POWER_DOWN:
53252+
53253+ if (ChipId != CHIP_ID_YUKON_XL) {
53254+
53255+ Ret = SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
53256+ Word &= ~PHY_M_PC_DIS_125CLK; /* enable MAC 125 MHz clock */
53257+ Word |= PHY_M_PC_MAC_POW_UP; /* set MAC power up */
53258+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
53259+
53260+ /* these register changes must be followed by a software reset */
53261+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word);
53262+ Word |= PHY_CT_RESET;
53263+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word);
53264+ }
53265+
53266+ /* switch IEEE compatible power down mode off */
53267+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word);
53268+ Word &= ~PHY_CT_PDOWN;
53269+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word);
53270+
53271+ break;
53272+
53273+ /* energy detect and energy detect plus mode */
53274+ case PHY_PM_ENERGY_DETECT:
53275+ case PHY_PM_ENERGY_DETECT_PLUS:
53276+
53277+ if (ChipId != CHIP_ID_YUKON_XL) {
53278+
53279+ Ret = SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Word);
53280+
53281+ if (ChipId == CHIP_ID_YUKON_FE) {
53282+ /* disable Energy Detect */
53283+ Word &= ~PHY_M_PC_ENA_ENE_DT;
53284+ }
53285+ else {
53286+ /* disable energy detect mode & enable MAC 125 MHz clock */
53287+ Word &= ~(PHY_M_PC_EN_DET_MSK | PHY_M_PC_DIS_125CLK);
53288+ }
53289+
53290+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Word);
53291+
53292+ /* these register changes must be followed by a software reset */
53293+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &Word);
53294+ Word |= PHY_CT_RESET;
53295+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, Word);
53296+ }
53297+ break;
53298+
53299+ /* don't change current power mode */
53300+ default:
53301+ pAC->GIni.GP[Port].PPhyPowerState = LastMode;
53302 Ret = 1;
53303 }
53304
53305 return(Ret);
53306
53307 } /* SkGmLeaveLowPowerMode */
53308-#endif /* !SK_SLIM */
53309-
53310+#endif /* SK_PHY_LP_MODE */
53311
53312 /******************************************************************************
53313 *
53314@@ -2365,107 +2689,242 @@
53315 * nothing
53316 */
53317 static void SkGmInitPhyMarv(
53318-SK_AC *pAC, /* adapter context */
53319-SK_IOC IoC, /* IO context */
53320+SK_AC *pAC, /* Adapter Context */
53321+SK_IOC IoC, /* I/O Context */
53322 int Port, /* Port Index (MAC_1 + n) */
53323 SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */
53324 {
53325 SK_GEPORT *pPrt;
53326+ SK_BOOL AutoNeg;
53327 SK_U16 PhyCtrl;
53328 SK_U16 C1000BaseT;
53329 SK_U16 AutoNegAdv;
53330+ SK_U8 PauseMode;
53331+ int ChipId;
53332+#ifndef VCPU
53333+ SK_U16 SWord;
53334+ SK_U16 PageReg;
53335+#ifndef SK_SLIM
53336+ SK_U16 LoopSpeed;
53337+#endif /* !SK_SLIM */
53338 SK_U16 ExtPhyCtrl;
53339 SK_U16 LedCtrl;
53340- SK_BOOL AutoNeg;
53341+ SK_U16 LedOver;
53342+#ifndef SK_DIAG
53343+ SK_EVPARA Para;
53344+#endif /* !SK_DIAG */
53345 #if defined(SK_DIAG) || defined(DEBUG)
53346 SK_U16 PhyStat;
53347 SK_U16 PhyStat1;
53348 SK_U16 PhySpecStat;
53349 #endif /* SK_DIAG || DEBUG */
53350+#endif /* !VCPU */
53351+
53352+ /* set Pause On */
53353+ PauseMode = (SK_U8)GMC_PAUSE_ON;
53354
53355 pPrt = &pAC->GIni.GP[Port];
53356
53357+ ChipId = pAC->GIni.GIChipId;
53358+
53359 /* Auto-negotiation ? */
53360- if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
53361- AutoNeg = SK_FALSE;
53362+ AutoNeg = pPrt->PLinkMode != SK_LMODE_HALF &&
53363+ pPrt->PLinkMode != SK_LMODE_FULL;
53364+
53365+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
53366+ ("InitPhyMarv: Port %d, Auto-neg. %s, LMode %d, LSpeed %d, FlowC %d\n",
53367+ Port, AutoNeg ? "ON" : "OFF",
53368+ pPrt->PLinkMode, pPrt->PLinkSpeed, pPrt->PFlowCtrlMode));
53369+
53370+#ifndef VCPU
53371+ /* read Id from PHY */
53372+ if (SkGmPhyRead(pAC, IoC, Port, PHY_MARV_ID1, &pPrt->PhyId1) != 0) {
53373+
53374+#ifndef SK_DIAG
53375+ Para.Para64 = Port;
53376+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para);
53377+#endif /* !SK_DIAG */
53378+
53379+ return;
53380 }
53381- else {
53382- AutoNeg = SK_TRUE;
53383+
53384+ if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
53385+
53386+#ifndef SK_SLIM
53387+ if (DoLoop) {
53388+ /* special setup for PHY 88E1112 */
53389+ if (ChipId == CHIP_ID_YUKON_XL) {
53390+
53391+ LoopSpeed = pPrt->PLinkSpeed;
53392+
53393+ if (LoopSpeed == SK_LSPEED_AUTO) {
53394+ /* force 1000 Mbps */
53395+ LoopSpeed = SK_LSPEED_1000MBPS;
53396+ }
53397+ LoopSpeed += 2;
53398+
53399+ /* save page register */
53400+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_ADR, &PageReg);
53401+
53402+ /* select page 2 to access MAC control register */
53403+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 2);
53404+
53405+ /* set MAC interface speed */
53406+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, LoopSpeed << 4);
53407+
53408+ /* restore page register */
53409+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, PageReg);
53410+
53411+ /* disable link pulses */
53412+ SWord = PHY_M_PC_DIS_LINK_P;
53413+ }
53414+ else {
53415+ /* set 'MAC Power up'-bit, set Manual MDI configuration */
53416+ SWord = PHY_M_PC_MAC_POW_UP;
53417+ }
53418+
53419+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, SWord);
53420+ }
53421+ else
53422+#endif /* !SK_SLIM */
53423+ if (AutoNeg && pPrt->PLinkSpeed == SK_LSPEED_AUTO &&
53424+ !(ChipId == CHIP_ID_YUKON_XL || ChipId == CHIP_ID_YUKON_EC_U)) {
53425+ /* Read Ext. PHY Specific Control */
53426+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl);
53427+
53428+ ExtPhyCtrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
53429+ PHY_M_EC_MAC_S_MSK);
53430+
53431+ ExtPhyCtrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
53432+
53433+ /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
53434+ if (pAC->GIni.GIYukonLite || ChipId == CHIP_ID_YUKON_EC) {
53435+ /* set downshift counter to 3x and enable downshift */
53436+ ExtPhyCtrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
53437+ }
53438+ else {
53439+ /* set master & slave downshift counter to 1x */
53440+ ExtPhyCtrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
53441+ }
53442+
53443+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_CTRL, ExtPhyCtrl);
53444+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
53445+ ("Set Ext. PHY Ctrl = 0x%04X\n", ExtPhyCtrl));
53446+ }
53447 }
53448-
53449- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
53450- ("InitPhyMarv: Port %d, auto-negotiation %s\n",
53451- Port, AutoNeg ? "ON" : "OFF"));
53452
53453-#ifdef VCPU
53454- VCPUprintf(0, "SkGmInitPhyMarv(), Port=%u, DoLoop=%u\n",
53455- Port, DoLoop);
53456-#else /* VCPU */
53457- if (DoLoop) {
53458- /* Set 'MAC Power up'-bit, set Manual MDI configuration */
53459- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL,
53460- PHY_M_PC_MAC_POW_UP);
53461+ if (CHIP_ID_YUKON_2(pAC)) {
53462+ /* Read PHY Specific Control */
53463+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &PhyCtrl);
53464+
53465+ if (!DoLoop && pAC->GIni.GICopperType) {
53466+
53467+ if (ChipId == CHIP_ID_YUKON_FE) {
53468+ /* enable Automatic Crossover (!!! Bits 5..4) */
53469+ PhyCtrl |= (SK_U16)(PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1);
53470+ }
53471+ else {
53472+ /* disable Energy Detect Mode */
53473+ PhyCtrl &= ~PHY_M_PC_EN_DET_MSK;
53474+
53475+ /* enable Automatic Crossover */
53476+ PhyCtrl |= (SK_U16)PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
53477+
53478+ /* downshift on PHY 88E1112 and 88E1149 is changed */
53479+ if (AutoNeg && pPrt->PLinkSpeed == SK_LSPEED_AUTO &&
53480+ (ChipId == CHIP_ID_YUKON_XL ||
53481+ ChipId == CHIP_ID_YUKON_EC_U)) {
53482+ /* set downshift counter to 3x and enable downshift */
53483+ PhyCtrl &= ~PHY_M_PC_DSC_MSK;
53484+ PhyCtrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
53485+ }
53486+ }
53487+ }
53488+ /* workaround for deviation #4.88 (CRC errors) */
53489+ else {
53490+ /* disable Automatic Crossover */
53491+ PhyCtrl &= ~PHY_M_PC_MDIX_MSK;
53492+ }
53493+
53494+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, PhyCtrl);
53495 }
53496- else if (AutoNeg && pPrt->PLinkSpeed == SK_LSPEED_AUTO) {
53497- /* Read Ext. PHY Specific Control */
53498- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl);
53499-
53500- ExtPhyCtrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
53501- PHY_M_EC_MAC_S_MSK);
53502-
53503- ExtPhyCtrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ) |
53504- PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
53505-
53506- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_CTRL, ExtPhyCtrl);
53507- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
53508- ("Set Ext. PHY Ctrl=0x%04X\n", ExtPhyCtrl));
53509+
53510+ /* special setup for PHY 88E1112 Fiber */
53511+ if (ChipId == CHIP_ID_YUKON_XL && !pAC->GIni.GICopperType) {
53512+ /* select 1000BASE-X only mode in MAC Specific Ctrl Reg. */
53513+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 2);
53514+
53515+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &SWord);
53516+
53517+ SWord &= ~PHY_M_MAC_MD_MSK;
53518+ SWord |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
53519+
53520+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, SWord);
53521+
53522+ /* select page 1 to access Fiber registers */
53523+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 1);
53524+
53525+ if (pAC->GIni.GIPmdTyp == 'P') {
53526+ /* for SFP-module set SIGDET polarity to low */
53527+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &SWord);
53528+
53529+ SWord |= PHY_M_FIB_SIGD_POL;
53530+
53531+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, SWord);
53532+ }
53533 }
53534
53535 /* Read PHY Control */
53536 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &PhyCtrl);
53537
53538+#ifndef SK_SLIM
53539 if (!AutoNeg) {
53540- /* Disable Auto-negotiation */
53541+ /* disable Auto-negotiation */
53542 PhyCtrl &= ~PHY_CT_ANE;
53543 }
53544+#endif /* !SK_SLIM */
53545
53546 PhyCtrl |= PHY_CT_RESET;
53547- /* Assert software reset */
53548+ /* assert software reset */
53549 SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PhyCtrl);
53550-#endif /* VCPU */
53551+#endif /* !VCPU */
53552
53553 PhyCtrl = 0 /* PHY_CT_COL_TST */;
53554 C1000BaseT = 0;
53555 AutoNegAdv = PHY_SEL_TYPE;
53556
53557+#ifndef SK_SLIM
53558 /* manually Master/Slave ? */
53559 if (pPrt->PMSMode != SK_MS_MODE_AUTO) {
53560 /* enable Manual Master/Slave */
53561 C1000BaseT |= PHY_M_1000C_MSE;
53562-
53563+
53564 if (pPrt->PMSMode == SK_MS_MODE_MASTER) {
53565 C1000BaseT |= PHY_M_1000C_MSC; /* set it to Master */
53566 }
53567 }
53568-
53569+#endif /* !SK_SLIM */
53570+
53571 /* Auto-negotiation ? */
53572 if (!AutoNeg) {
53573-
53574+
53575+#ifndef SK_SLIM
53576 if (pPrt->PLinkMode == SK_LMODE_FULL) {
53577- /* Set Full Duplex Mode */
53578+ /* set Full Duplex Mode */
53579 PhyCtrl |= PHY_CT_DUP_MD;
53580 }
53581
53582- /* Set Master/Slave manually if not already done */
53583+ /* set Master/Slave manually if not already done */
53584 if (pPrt->PMSMode == SK_MS_MODE_AUTO) {
53585 C1000BaseT |= PHY_M_1000C_MSE; /* set it to Slave */
53586 }
53587
53588- /* Set Speed */
53589+ /* set Speed */
53590 switch (pPrt->PLinkSpeed) {
53591 case SK_LSPEED_AUTO:
53592 case SK_LSPEED_1000MBPS:
53593- PhyCtrl |= PHY_CT_SP1000;
53594+ PhyCtrl |= (((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) ?
53595+ PHY_CT_SP1000 : PHY_CT_SP100);
53596 break;
53597 case SK_LSPEED_100MBPS:
53598 PhyCtrl |= PHY_CT_SP100;
53599@@ -2477,38 +2936,67 @@
53600 SKERR_HWI_E019MSG);
53601 }
53602
53603+ if ((pPrt->PFlowCtrlMode == SK_FLOW_STAT_NONE) ||
53604+ /* disable Pause also for 10/100 Mbps in half duplex mode */
53605+ ((ChipId != CHIP_ID_YUKON_EC_U) &&
53606+ (pPrt->PLinkMode == SK_LMODE_HALF) &&
53607+ ((pPrt->PLinkSpeed == SK_LSPEED_STAT_100MBPS) ||
53608+ (pPrt->PLinkSpeed == SK_LSPEED_STAT_10MBPS)))) {
53609+
53610+ /* set Pause Off */
53611+ PauseMode = (SK_U8)GMC_PAUSE_OFF;
53612+ }
53613+
53614+ SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), PauseMode);
53615+
53616 if (!DoLoop) {
53617+ /* assert software reset */
53618 PhyCtrl |= PHY_CT_RESET;
53619 }
53620+#endif /* !SK_SLIM */
53621 }
53622 else {
53623- /* Set Auto-negotiation advertisement */
53624-
53625+ /* set Auto-negotiation advertisement */
53626+
53627 if (pAC->GIni.GICopperType) {
53628- /* Set Speed capabilities */
53629+ /* set Speed capabilities */
53630 switch (pPrt->PLinkSpeed) {
53631 case SK_LSPEED_AUTO:
53632- C1000BaseT |= PHY_M_1000C_AHD | PHY_M_1000C_AFD;
53633+ if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
53634+ C1000BaseT |= PHY_M_1000C_AFD;
53635+#ifdef xSK_DIAG
53636+ C1000BaseT |= PHY_M_1000C_AHD;
53637+#endif /* SK_DIAG */
53638+ }
53639 AutoNegAdv |= PHY_M_AN_100_FD | PHY_M_AN_100_HD |
53640 PHY_M_AN_10_FD | PHY_M_AN_10_HD;
53641 break;
53642 case SK_LSPEED_1000MBPS:
53643- C1000BaseT |= PHY_M_1000C_AHD | PHY_M_1000C_AFD;
53644+ if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
53645+ C1000BaseT |= PHY_M_1000C_AFD;
53646+#ifdef xSK_DIAG
53647+ C1000BaseT |= PHY_M_1000C_AHD;
53648+#endif /* SK_DIAG */
53649+ }
53650 break;
53651 case SK_LSPEED_100MBPS:
53652- AutoNegAdv |= PHY_M_AN_100_FD | PHY_M_AN_100_HD |
53653- /* advertise 10Base-T also */
53654- PHY_M_AN_10_FD | PHY_M_AN_10_HD;
53655+ if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_100MBPS) != 0) {
53656+ AutoNegAdv |= PHY_M_AN_100_FD | PHY_M_AN_100_HD |
53657+ /* advertise 10Base-T also */
53658+ PHY_M_AN_10_FD | PHY_M_AN_10_HD;
53659+ }
53660 break;
53661 case SK_LSPEED_10MBPS:
53662- AutoNegAdv |= PHY_M_AN_10_FD | PHY_M_AN_10_HD;
53663+ if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_10MBPS) != 0) {
53664+ AutoNegAdv |= PHY_M_AN_10_FD | PHY_M_AN_10_HD;
53665+ }
53666 break;
53667 default:
53668 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E019,
53669 SKERR_HWI_E019MSG);
53670 }
53671
53672- /* Set Full/half duplex capabilities */
53673+ /* set Full/half duplex capabilities */
53674 switch (pPrt->PLinkMode) {
53675 case SK_LMODE_AUTOHALF:
53676 C1000BaseT &= ~PHY_M_1000C_AFD;
53677@@ -2524,8 +3012,8 @@
53678 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E015,
53679 SKERR_HWI_E015MSG);
53680 }
53681-
53682- /* Set Flow-control capabilities */
53683+
53684+ /* set Flow-control capabilities */
53685 switch (pPrt->PFlowCtrlMode) {
53686 case SK_FLOW_MODE_NONE:
53687 AutoNegAdv |= PHY_B_P_NO_PAUSE;
53688@@ -2544,9 +3032,9 @@
53689 SKERR_HWI_E016MSG);
53690 }
53691 }
53692- else { /* special defines for FIBER (88E1011S only) */
53693-
53694- /* Set Full/half duplex capabilities */
53695+ else { /* special defines for FIBER (88E1040S only) */
53696+
53697+ /* set Full/half duplex capabilities */
53698 switch (pPrt->PLinkMode) {
53699 case SK_LMODE_AUTOHALF:
53700 AutoNegAdv |= PHY_M_AN_1000X_AHD;
53701@@ -2561,8 +3049,8 @@
53702 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E015,
53703 SKERR_HWI_E015MSG);
53704 }
53705-
53706- /* Set Flow-control capabilities */
53707+
53708+ /* set Flow-control capabilities */
53709 switch (pPrt->PFlowCtrlMode) {
53710 case SK_FLOW_MODE_NONE:
53711 AutoNegAdv |= PHY_M_P_NO_PAUSE_X;
53712@@ -2587,138 +3075,228 @@
53713 PhyCtrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
53714 }
53715 }
53716-
53717+
53718 #ifdef VCPU
53719 /*
53720 * E-mail from Gu Lin (08-03-2002):
53721 */
53722-
53723+
53724 /* Program PHY register 30 as 16'h0708 for simulation speed up */
53725 SkGmPhyWrite(pAC, IoC, Port, 30, 0x0700 /* 0x0708 */);
53726-
53727+
53728 VCpuWait(2000);
53729
53730-#else /* VCPU */
53731-
53732- /* Write 1000Base-T Control Register */
53733- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_1000T_CTRL, C1000BaseT);
53734- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
53735- ("Set 1000B-T Ctrl =0x%04X\n", C1000BaseT));
53736-
53737+#else /* !VCPU */
53738+
53739+ if (ChipId != CHIP_ID_YUKON_FE) {
53740+ /* Write 1000Base-T Control Register */
53741+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_1000T_CTRL, C1000BaseT);
53742+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
53743+ ("Set 1000B-T Ctrl = 0x%04X\n", C1000BaseT));
53744+ }
53745+
53746 /* Write AutoNeg Advertisement Register */
53747 SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_AUNE_ADV, AutoNegAdv);
53748 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
53749- ("Set Auto-Neg.Adv.=0x%04X\n", AutoNegAdv));
53750-#endif /* VCPU */
53751-
53752+ ("Set Auto-Neg.Adv. = 0x%04X\n", AutoNegAdv));
53753+#endif /* !VCPU */
53754+
53755+#ifndef SK_SLIM
53756 if (DoLoop) {
53757- /* Set the PHY Loopback bit */
53758+ /* set the PHY Loopback bit */
53759 PhyCtrl |= PHY_CT_LOOP;
53760
53761 #ifdef XXX
53762 /* Program PHY register 16 as 16'h0400 to force link good */
53763 SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, PHY_M_PC_FL_GOOD);
53764-#endif /* XXX */
53765
53766-#ifndef VCPU
53767 if (pPrt->PLinkSpeed != SK_LSPEED_AUTO) {
53768 /* Write Ext. PHY Specific Control */
53769 SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_CTRL,
53770 (SK_U16)((pPrt->PLinkSpeed + 2) << 4));
53771 }
53772-#endif /* VCPU */
53773+#endif /* XXX */
53774 }
53775 #ifdef TEST_ONLY
53776 else if (pPrt->PLinkSpeed == SK_LSPEED_10MBPS) {
53777- /* Write PHY Specific Control */
53778- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL,
53779- PHY_M_PC_EN_DET_MSK);
53780+ /* Write PHY Specific Control */
53781+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, PHY_M_PC_EN_DET_MSK);
53782 }
53783 #endif
53784+#endif /* !SK_SLIM */
53785
53786 /* Write to the PHY Control register */
53787 SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, PhyCtrl);
53788 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
53789- ("Set PHY Ctrl Reg.=0x%04X\n", PhyCtrl));
53790+ ("Set PHY Ctrl Reg. = 0x%04X\n", PhyCtrl));
53791
53792 #ifdef VCPU
53793 VCpuWait(2000);
53794-#else
53795+#else /* !VCPU */
53796
53797- LedCtrl = PHY_M_LED_PULS_DUR(PULS_170MS) | PHY_M_LED_BLINK_RT(BLINK_84MS);
53798+ LedCtrl = PHY_M_LED_PULS_DUR(PULS_170MS);
53799+
53800+ LedOver = 0;
53801
53802 if ((pAC->GIni.GILedBlinkCtrl & SK_ACT_LED_BLINK) != 0) {
53803- LedCtrl |= PHY_M_LEDC_RX_CTRL | PHY_M_LEDC_TX_CTRL;
53804+
53805+ if (ChipId == CHIP_ID_YUKON_FE) {
53806+ /* on 88E3082 these bits are at 11..9 (shifted left) */
53807+ LedCtrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
53808+
53809+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_FE_LED_PAR, &SWord);
53810+
53811+ /* delete ACT LED control bits */
53812+ SWord &= ~PHY_M_FELP_LED1_MSK;
53813+ /* change ACT LED control to blink mode */
53814+ SWord |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
53815+
53816+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_FE_LED_PAR, SWord);
53817+ }
53818+ else if (ChipId == CHIP_ID_YUKON_XL || ChipId == CHIP_ID_YUKON_EC_U) {
53819+ /* save page register */
53820+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_ADR, &PageReg);
53821+
53822+ /* select page 3 to access LED control register */
53823+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 3);
53824+
53825+ /* set LED Function Control register */
53826+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, (SK_U16)
53827+ (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
53828+ PHY_M_LEDC_INIT_CTRL(
53829+ ChipId == CHIP_ID_YUKON_XL ? 7 : 8) | /* 10 Mbps */
53830+ PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
53831+ PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
53832+
53833+ if (ChipId == CHIP_ID_YUKON_XL) {
53834+ /* set Polarity Control register */
53835+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_STAT, (SK_U16)
53836+ (PHY_M_POLC_LS1_P_MIX(4) | PHY_M_POLC_IS0_P_MIX(4) |
53837+ PHY_M_POLC_LOS_CTRL(2) | PHY_M_POLC_INIT_CTRL(2) |
53838+ PHY_M_POLC_STA1_CTRL(2) | PHY_M_POLC_STA0_CTRL(2)));
53839+ }
53840+ else if (ChipId == CHIP_ID_YUKON_EC_U) {
53841+ /* set Blink Rate in LED Timer Control Register */
53842+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK,
53843+ LedCtrl | (SK_U16)PHY_M_LED_BLINK_RT(BLINK_84MS));
53844+ }
53845+ /* restore page register */
53846+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, PageReg);
53847+ }
53848+ else {
53849+ /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
53850+ LedCtrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
53851+
53852+ /* on PHY 88E1111 there is a change for LED control */
53853+ if (ChipId == CHIP_ID_YUKON_EC &&
53854+ (pAC->GIni.GILedBlinkCtrl & SK_DUAL_LED_ACT_LNK) != 0) {
53855+ /* Yukon-EC needs setting of 2 bits: 0,6=11) */
53856+ LedCtrl |= PHY_M_LEDC_TX_C_LSB;
53857+ }
53858+ /* turn off the Rx LED (LED_RX) */
53859+ LedOver |= PHY_M_LED_MO_RX(MO_LED_OFF);
53860+ }
53861 }
53862
53863 if ((pAC->GIni.GILedBlinkCtrl & SK_DUP_LED_NORMAL) != 0) {
53864+ /* disable blink mode (LED_DUPLEX) on collisions */
53865 LedCtrl |= PHY_M_LEDC_DP_CTRL;
53866 }
53867-
53868- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_LED_CTRL, LedCtrl);
53869
53870- if ((pAC->GIni.GILedBlinkCtrl & SK_LED_LINK100_ON) != 0) {
53871- /* only in forced 100 Mbps mode */
53872- if (!AutoNeg && pPrt->PLinkSpeed == SK_LSPEED_100MBPS) {
53873+ if (ChipId == CHIP_ID_YUKON_EC_U &&
53874+ pAC->GIni.GIChipRev == CHIP_REV_YU_EC_U_A1) {
53875
53876- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_LED_OVER,
53877- PHY_M_LED_MO_100(MO_LED_ON));
53878+ /* apply fixes in PHY AFE */
53879+ SkGmPhyWrite(pAC, IoC, Port, 22, 255);
53880+ /* increase differential signal amplitude in 10BASE-T */
53881+ SkGmPhyWrite(pAC, IoC, Port, 24, 0xaa99);
53882+ SkGmPhyWrite(pAC, IoC, Port, 23, 0x2011);
53883+
53884+ /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
53885+ SkGmPhyWrite(pAC, IoC, Port, 24, 0xa204);
53886+ SkGmPhyWrite(pAC, IoC, Port, 23, 0x2002);
53887+
53888+ /* set page register to 0 */
53889+ SkGmPhyWrite(pAC, IoC, Port, 22, 0);
53890+ }
53891+ else {
53892+ /* no effect on Yukon-XL and Yukon-EC Ultra */
53893+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_LED_CTRL, LedCtrl);
53894+
53895+#ifndef SK_SLIM
53896+ if ((pAC->GIni.GILedBlinkCtrl & SK_LED_LINK100_ON) != 0) {
53897+ /* only in forced 100 Mbps mode */
53898+ if (!AutoNeg && pPrt->PLinkSpeed == SK_LSPEED_100MBPS) {
53899+ /* turn on 100 Mbps LED (LED_LINK100) */
53900+ LedOver |= PHY_M_LED_MO_100(MO_LED_ON);
53901+ }
53902+ }
53903+#endif /* !SK_SLIM */
53904+
53905+ if (LedOver != 0) {
53906+ /* set Manual LED Override */
53907+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_LED_OVER, LedOver);
53908 }
53909 }
53910
53911 #ifdef SK_DIAG
53912- c_print("Set PHY Ctrl=0x%04X\n", PhyCtrl);
53913- c_print("Set 1000 B-T=0x%04X\n", C1000BaseT);
53914- c_print("Set Auto-Neg=0x%04X\n", AutoNegAdv);
53915- c_print("Set Ext Ctrl=0x%04X\n", ExtPhyCtrl);
53916+ c_print("Set PHY Ctrl = 0x%04X\n", PhyCtrl);
53917+ c_print("Set 1000 B-T = 0x%04X\n", C1000BaseT);
53918+ c_print("Set Auto-Neg = 0x%04X\n", AutoNegAdv);
53919+ c_print("Set Ext Ctrl = 0x%04X\n", ExtPhyCtrl);
53920 #endif /* SK_DIAG */
53921
53922 #if defined(SK_DIAG) || defined(DEBUG)
53923 /* Read PHY Control */
53924 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &PhyCtrl);
53925 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
53926- ("PHY Ctrl Reg.=0x%04X\n", PhyCtrl));
53927-
53928- /* Read 1000Base-T Control Register */
53929- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_CTRL, &C1000BaseT);
53930- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
53931- ("1000B-T Ctrl =0x%04X\n", C1000BaseT));
53932-
53933+ ("PHY Ctrl Reg. = 0x%04X\n", PhyCtrl));
53934+
53935 /* Read AutoNeg Advertisement Register */
53936 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_ADV, &AutoNegAdv);
53937 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
53938- ("Auto-Neg.Adv.=0x%04X\n", AutoNegAdv));
53939-
53940- /* Read Ext. PHY Specific Control */
53941- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl);
53942- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
53943- ("Ext. PHY Ctrl=0x%04X\n", ExtPhyCtrl));
53944-
53945+ ("Auto-Neg.Adv. = 0x%04X\n", AutoNegAdv));
53946+
53947+ if (ChipId != CHIP_ID_YUKON_FE) {
53948+ /* Read 1000Base-T Control Register */
53949+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_CTRL, &C1000BaseT);
53950+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
53951+ ("1000B-T Ctrl = 0x%04X\n", C1000BaseT));
53952+
53953+ /* Read Ext. PHY Specific Control */
53954+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl);
53955+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
53956+ ("Ext. PHY Ctrl = 0x%04X\n", ExtPhyCtrl));
53957+ }
53958+
53959 /* Read PHY Status */
53960 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_STAT, &PhyStat);
53961 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
53962- ("PHY Stat Reg.=0x%04X\n", PhyStat));
53963+ ("PHY Stat Reg. = 0x%04X\n", PhyStat));
53964+
53965 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_STAT, &PhyStat1);
53966 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
53967- ("PHY Stat Reg.=0x%04X\n", PhyStat1));
53968-
53969+ ("PHY Stat Reg. = 0x%04X\n", PhyStat1));
53970+
53971 /* Read PHY Specific Status */
53972 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &PhySpecStat);
53973 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
53974- ("PHY Spec Stat=0x%04X\n", PhySpecStat));
53975+ ("PHY Spec Stat = 0x%04X\n", PhySpecStat));
53976 #endif /* SK_DIAG || DEBUG */
53977
53978 #ifdef SK_DIAG
53979- c_print("PHY Ctrl Reg=0x%04X\n", PhyCtrl);
53980- c_print("PHY 1000 Reg=0x%04X\n", C1000BaseT);
53981- c_print("PHY AnAd Reg=0x%04X\n", AutoNegAdv);
53982- c_print("Ext Ctrl Reg=0x%04X\n", ExtPhyCtrl);
53983- c_print("PHY Stat Reg=0x%04X\n", PhyStat);
53984- c_print("PHY Stat Reg=0x%04X\n", PhyStat1);
53985- c_print("PHY Spec Reg=0x%04X\n", PhySpecStat);
53986+ c_print("PHY Ctrl Reg = 0x%04X\n", PhyCtrl);
53987+ c_print("PHY 1000 Reg = 0x%04X\n", C1000BaseT);
53988+ c_print("PHY AnAd Reg = 0x%04X\n", AutoNegAdv);
53989+ c_print("Ext Ctrl Reg = 0x%04X\n", ExtPhyCtrl);
53990+ c_print("PHY Stat Reg = 0x%04X\n", PhyStat);
53991+ c_print("PHY Stat Reg = 0x%04X\n", PhyStat1);
53992+ c_print("PHY Spec Reg = 0x%04X\n", PhySpecStat);
53993 #endif /* SK_DIAG */
53994
53995-#endif /* VCPU */
53996+ /* enable PHY interrupts */
53997+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, (SK_U16)PHY_M_DEF_MSK);
53998+#endif /* !VCPU */
53999
54000 } /* SkGmInitPhyMarv */
54001 #endif /* YUKON */
54002@@ -2737,8 +3315,8 @@
54003 * nothing
54004 */
54005 static void SkXmInitPhyLone(
54006-SK_AC *pAC, /* adapter context */
54007-SK_IOC IoC, /* IO context */
54008+SK_AC *pAC, /* Adapter Context */
54009+SK_IOC IoC, /* I/O Context */
54010 int Port, /* Port Index (MAC_1 + n) */
54011 SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */
54012 {
54013@@ -2756,7 +3334,7 @@
54014 /* manually Master/Slave ? */
54015 if (pPrt->PMSMode != SK_MS_MODE_AUTO) {
54016 Ctrl2 |= PHY_L_1000C_MSE;
54017-
54018+
54019 if (pPrt->PMSMode == SK_MS_MODE_MASTER) {
54020 Ctrl2 |= PHY_L_1000C_MSC;
54021 }
54022@@ -2769,7 +3347,7 @@
54023 */
54024 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
54025 ("InitPhyLone: no auto-negotiation Port %d\n", Port));
54026- /* Set DuplexMode in Config register */
54027+ /* set DuplexMode in Config register */
54028 if (pPrt->PLinkMode == SK_LMODE_FULL) {
54029 Ctrl1 |= PHY_CT_DUP_MD;
54030 }
54031@@ -2778,7 +3356,6 @@
54032 if (pPrt->PMSMode == SK_MS_MODE_AUTO) {
54033 Ctrl2 |= PHY_L_1000C_MSE; /* set it to Slave */
54034 }
54035-
54036 /*
54037 * Do NOT enable Auto-negotiation here. This would hold
54038 * the link down because no IDLES are transmitted
54039@@ -2787,9 +3364,9 @@
54040 else {
54041 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
54042 ("InitPhyLone: with auto-negotiation Port %d\n", Port));
54043- /* Set Auto-negotiation advertisement */
54044+ /* set Auto-negotiation advertisement */
54045
54046- /* Set Full/half duplex capabilities */
54047+ /* set Full/half duplex capabilities */
54048 switch (pPrt->PLinkMode) {
54049 case SK_LMODE_AUTOHALF:
54050 Ctrl2 |= PHY_L_1000C_AHD;
54051@@ -2805,7 +3382,7 @@
54052 SKERR_HWI_E015MSG);
54053 }
54054
54055- /* Set Flow-control capabilities */
54056+ /* set Flow-control capabilities */
54057 switch (pPrt->PFlowCtrlMode) {
54058 case SK_FLOW_MODE_NONE:
54059 Ctrl3 |= PHY_L_P_NO_PAUSE;
54060@@ -2827,26 +3404,26 @@
54061 /* Restart Auto-negotiation */
54062 Ctrl1 = PHY_CT_ANE | PHY_CT_RE_CFG;
54063 }
54064-
54065+
54066 /* Write 1000Base-T Control Register */
54067 SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_1000T_CTRL, Ctrl2);
54068 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
54069- ("1000B-T Ctrl Reg=0x%04X\n", Ctrl2));
54070-
54071+ ("1000B-T Ctrl Reg = 0x%04X\n", Ctrl2));
54072+
54073 /* Write AutoNeg Advertisement Register */
54074 SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_AUNE_ADV, Ctrl3);
54075 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
54076- ("Auto-Neg.Adv.Reg=0x%04X\n", Ctrl3));
54077+ ("Auto-Neg.Adv.Reg = 0x%04X\n", Ctrl3));
54078
54079 if (DoLoop) {
54080- /* Set the Phy Loopback bit, too */
54081+ /* set the Phy Loopback bit, too */
54082 Ctrl1 |= PHY_CT_LOOP;
54083 }
54084
54085 /* Write to the Phy control register */
54086 SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_CTRL, Ctrl1);
54087 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
54088- ("PHY Control Reg=0x%04X\n", Ctrl1));
54089+ ("PHY Control Reg = 0x%04X\n", Ctrl1));
54090 } /* SkXmInitPhyLone */
54091
54092
54093@@ -2862,8 +3439,8 @@
54094 * nothing
54095 */
54096 static void SkXmInitPhyNat(
54097-SK_AC *pAC, /* adapter context */
54098-SK_IOC IoC, /* IO context */
54099+SK_AC *pAC, /* Adapter Context */
54100+SK_IOC IoC, /* I/O Context */
54101 int Port, /* Port Index (MAC_1 + n) */
54102 SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */
54103 {
54104@@ -2884,8 +3461,8 @@
54105 * nothing
54106 */
54107 void SkMacInitPhy(
54108-SK_AC *pAC, /* adapter context */
54109-SK_IOC IoC, /* IO context */
54110+SK_AC *pAC, /* Adapter Context */
54111+SK_IOC IoC, /* I/O Context */
54112 int Port, /* Port Index (MAC_1 + n) */
54113 SK_BOOL DoLoop) /* Should a Phy LoopBack be set-up? */
54114 {
54115@@ -2895,7 +3472,7 @@
54116
54117 #ifdef GENESIS
54118 if (pAC->GIni.GIGenesis) {
54119-
54120+
54121 switch (pPrt->PhyType) {
54122 case SK_PHY_XMAC:
54123 SkXmInitPhyXmac(pAC, IoC, Port, DoLoop);
54124@@ -2914,10 +3491,10 @@
54125 }
54126 }
54127 #endif /* GENESIS */
54128-
54129+
54130 #ifdef YUKON
54131 if (pAC->GIni.GIYukon) {
54132-
54133+
54134 SkGmInitPhyMarv(pAC, IoC, Port, DoLoop);
54135 }
54136 #endif /* YUKON */
54137@@ -2935,17 +3512,17 @@
54138 *
54139 * Returns:
54140 * SK_AND_OK o.k.
54141- * SK_AND_DUP_CAP Duplex capability error happened
54142- * SK_AND_OTHER Other error happened
54143+ * SK_AND_DUP_CAP Duplex capability error happened
54144+ * SK_AND_OTHER Other error happened
54145 */
54146 static int SkXmAutoNegDoneXmac(
54147-SK_AC *pAC, /* adapter context */
54148-SK_IOC IoC, /* IO context */
54149+SK_AC *pAC, /* Adapter Context */
54150+SK_IOC IoC, /* I/O Context */
54151 int Port) /* Port Index (MAC_1 + n) */
54152 {
54153 SK_GEPORT *pPrt;
54154 SK_U16 ResAb; /* Resolved Ability */
54155- SK_U16 LPAb; /* Link Partner Ability */
54156+ SK_U16 LinkPartAb; /* Link Partner Ability */
54157
54158 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
54159 ("AutoNegDoneXmac, Port %d\n", Port));
54160@@ -2953,15 +3530,15 @@
54161 pPrt = &pAC->GIni.GP[Port];
54162
54163 /* Get PHY parameters */
54164- SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_AUNE_LP, &LPAb);
54165+ SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_AUNE_LP, &LinkPartAb);
54166 SkXmPhyRead(pAC, IoC, Port, PHY_XMAC_RES_ABI, &ResAb);
54167
54168- if ((LPAb & PHY_X_AN_RFB) != 0) {
54169+ if ((LinkPartAb & PHY_X_AN_RFB) != 0) {
54170 /* At least one of the remote fault bit is set */
54171- /* Error */
54172- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
54173+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
54174 ("AutoNegFail: Remote fault bit set Port %d\n", Port));
54175 pPrt->PAutoNegFail = SK_TRUE;
54176+
54177 return(SK_AND_OTHER);
54178 }
54179
54180@@ -2974,9 +3551,10 @@
54181 }
54182 else {
54183 /* Error */
54184- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
54185+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
54186 ("AutoNegFail: Duplex mode mismatch Port %d\n", Port));
54187 pPrt->PAutoNegFail = SK_TRUE;
54188+
54189 return(SK_AND_DUP_CAP);
54190 }
54191
54192@@ -2984,19 +3562,19 @@
54193 /* We are NOT using chapter 4.23 of the Xaqti manual */
54194 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
54195 if ((pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYMMETRIC ||
54196- pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM) &&
54197- (LPAb & PHY_X_P_SYM_MD) != 0) {
54198+ pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM) &&
54199+ (LinkPartAb & PHY_X_P_SYM_MD) != 0) {
54200 /* Symmetric PAUSE */
54201 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC;
54202 }
54203 else if (pPrt->PFlowCtrlMode == SK_FLOW_MODE_SYM_OR_REM &&
54204- (LPAb & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD) {
54205- /* Enable PAUSE receive, disable PAUSE transmit */
54206+ (LinkPartAb & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD) {
54207+ /* enable PAUSE receive, disable PAUSE transmit */
54208 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND;
54209 }
54210 else if (pPrt->PFlowCtrlMode == SK_FLOW_MODE_LOC_SEND &&
54211- (LPAb & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD) {
54212- /* Disable PAUSE receive, enable PAUSE transmit */
54213+ (LinkPartAb & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD) {
54214+ /* disable PAUSE receive, enable PAUSE transmit */
54215 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND;
54216 }
54217 else {
54218@@ -3018,41 +3596,40 @@
54219 *
54220 * Returns:
54221 * SK_AND_OK o.k.
54222- * SK_AND_DUP_CAP Duplex capability error happened
54223- * SK_AND_OTHER Other error happened
54224+ * SK_AND_DUP_CAP Duplex capability error happened
54225+ * SK_AND_OTHER Other error happened
54226 */
54227 static int SkXmAutoNegDoneBcom(
54228-SK_AC *pAC, /* adapter context */
54229-SK_IOC IoC, /* IO context */
54230+SK_AC *pAC, /* Adapter Context */
54231+SK_IOC IoC, /* I/O Context */
54232 int Port) /* Port Index (MAC_1 + n) */
54233 {
54234 SK_GEPORT *pPrt;
54235- SK_U16 LPAb; /* Link Partner Ability */
54236- SK_U16 AuxStat; /* Auxiliary Status */
54237-
54238 #ifdef TEST_ONLY
54239-01-Sep-2000 RA;:;:
54240 SK_U16 ResAb; /* Resolved Ability */
54241-#endif /* 0 */
54242+#endif
54243+ SK_U16 LinkPartAb; /* Link Partner Ability */
54244+ SK_U16 AuxStat; /* Auxiliary Status */
54245+
54246
54247 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
54248 ("AutoNegDoneBcom, Port %d\n", Port));
54249 pPrt = &pAC->GIni.GP[Port];
54250
54251 /* Get PHY parameters */
54252- SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &LPAb);
54253+ SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUNE_LP, &LinkPartAb);
54254 #ifdef TEST_ONLY
54255-01-Sep-2000 RA;:;:
54256 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &ResAb);
54257-#endif /* 0 */
54258-
54259+#endif
54260+
54261 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_STAT, &AuxStat);
54262
54263- if ((LPAb & PHY_B_AN_RF) != 0) {
54264+ if ((LinkPartAb & PHY_B_AN_RF) != 0) {
54265 /* Remote fault bit is set: Error */
54266- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
54267+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
54268 ("AutoNegFail: Remote fault bit set Port %d\n", Port));
54269 pPrt->PAutoNegFail = SK_TRUE;
54270+
54271 return(SK_AND_OTHER);
54272 }
54273
54274@@ -3065,26 +3642,26 @@
54275 }
54276 else {
54277 /* Error */
54278- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
54279+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
54280 ("AutoNegFail: Duplex mode mismatch Port %d\n", Port));
54281 pPrt->PAutoNegFail = SK_TRUE;
54282+
54283 return(SK_AND_DUP_CAP);
54284 }
54285-
54286+
54287 #ifdef TEST_ONLY
54288-01-Sep-2000 RA;:;:
54289 /* Check Master/Slave resolution */
54290 if ((ResAb & PHY_B_1000S_MSF) != 0) {
54291- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
54292+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
54293 ("Master/Slave Fault Port %d\n", Port));
54294 pPrt->PAutoNegFail = SK_TRUE;
54295 pPrt->PMSStatus = SK_MS_STAT_FAULT;
54296 return(SK_AND_OTHER);
54297 }
54298-
54299+
54300 pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
54301 SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE;
54302-#endif /* 0 */
54303+#endif
54304
54305 /* Check PAUSE mismatch ??? */
54306 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
54307@@ -3093,11 +3670,11 @@
54308 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC;
54309 }
54310 else if ((AuxStat & PHY_B_AS_PAUSE_MSK) == PHY_B_AS_PRR) {
54311- /* Enable PAUSE receive, disable PAUSE transmit */
54312+ /* enable PAUSE receive, disable PAUSE transmit */
54313 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND;
54314 }
54315 else if ((AuxStat & PHY_B_AS_PAUSE_MSK) == PHY_B_AS_PRT) {
54316- /* Disable PAUSE receive, enable PAUSE transmit */
54317+ /* disable PAUSE receive, enable PAUSE transmit */
54318 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND;
54319 }
54320 else {
54321@@ -3111,6 +3688,7 @@
54322 #endif /* GENESIS */
54323
54324
54325+#ifndef SK_SLIM
54326 #ifdef YUKON
54327 /******************************************************************************
54328 *
54329@@ -3121,102 +3699,148 @@
54330 *
54331 * Returns:
54332 * SK_AND_OK o.k.
54333- * SK_AND_DUP_CAP Duplex capability error happened
54334- * SK_AND_OTHER Other error happened
54335+ * SK_AND_DUP_CAP Duplex capability error happened
54336+ * SK_AND_OTHER Other error happened
54337 */
54338 static int SkGmAutoNegDoneMarv(
54339-SK_AC *pAC, /* adapter context */
54340-SK_IOC IoC, /* IO context */
54341+SK_AC *pAC, /* Adapter Context */
54342+SK_IOC IoC, /* I/O Context */
54343 int Port) /* Port Index (MAC_1 + n) */
54344 {
54345 SK_GEPORT *pPrt;
54346- SK_U16 LPAb; /* Link Partner Ability */
54347 SK_U16 ResAb; /* Resolved Ability */
54348+ SK_U16 LinkPartAb; /* Link Partner Ability */
54349 SK_U16 AuxStat; /* Auxiliary Status */
54350+ SK_U8 PauseMode; /* Pause Mode */
54351+
54352+ /* set Pause On */
54353+ PauseMode = (SK_U8)GMC_PAUSE_ON;
54354
54355 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
54356 ("AutoNegDoneMarv, Port %d\n", Port));
54357+
54358 pPrt = &pAC->GIni.GP[Port];
54359
54360 /* Get PHY parameters */
54361- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_LP, &LPAb);
54362+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_LP, &LinkPartAb);
54363 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
54364- ("Link P.Abil.=0x%04X\n", LPAb));
54365-
54366- if ((LPAb & PHY_M_AN_RF) != 0) {
54367- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
54368+ ("Link P.Abil. = 0x%04X\n", LinkPartAb));
54369+
54370+ if ((LinkPartAb & PHY_M_AN_RF) != 0) {
54371+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
54372 ("AutoNegFail: Remote fault bit set Port %d\n", Port));
54373 pPrt->PAutoNegFail = SK_TRUE;
54374+
54375 return(SK_AND_OTHER);
54376 }
54377
54378- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_STAT, &ResAb);
54379-
54380- /* Check Master/Slave resolution */
54381- if ((ResAb & PHY_B_1000S_MSF) != 0) {
54382+ /* Read PHY Auto-Negotiation Expansion */
54383+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_EXP, &LinkPartAb);
54384+
54385+ if ((LinkPartAb & PHY_ANE_LP_CAP) == 0) {
54386+
54387 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
54388- ("Master/Slave Fault Port %d\n", Port));
54389- pPrt->PAutoNegFail = SK_TRUE;
54390- pPrt->PMSStatus = SK_MS_STAT_FAULT;
54391- return(SK_AND_OTHER);
54392+ ("Link Partner not Auto-Neg. able, AN Exp.: 0x%04X\n", LinkPartAb));
54393+ }
54394+
54395+ if ((pPrt->PLinkSpeedCap & SK_LSPEED_CAP_1000MBPS) != 0) {
54396+
54397+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_STAT, &ResAb);
54398+
54399+ /* Check Master/Slave resolution */
54400+ if ((ResAb & PHY_B_1000S_MSF) != 0) {
54401+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
54402+ ("Master/Slave Fault Port %d\n", Port));
54403+ pPrt->PAutoNegFail = SK_TRUE;
54404+ pPrt->PMSStatus = SK_MS_STAT_FAULT;
54405+ return(SK_AND_OTHER);
54406+ }
54407+
54408+ pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
54409+ (SK_U8)SK_MS_STAT_MASTER : (SK_U8)SK_MS_STAT_SLAVE;
54410 }
54411-
54412- pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
54413- (SK_U8)SK_MS_STAT_MASTER : (SK_U8)SK_MS_STAT_SLAVE;
54414-
54415+
54416 /* Read PHY Specific Status */
54417 SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &AuxStat);
54418-
54419+
54420 /* Check Speed & Duplex resolved */
54421 if ((AuxStat & PHY_M_PS_SPDUP_RES) == 0) {
54422- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
54423+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
54424 ("AutoNegFail: Speed & Duplex not resolved, Port %d\n", Port));
54425 pPrt->PAutoNegFail = SK_TRUE;
54426 pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_UNKNOWN;
54427+
54428 return(SK_AND_DUP_CAP);
54429 }
54430-
54431- if ((AuxStat & PHY_M_PS_FULL_DUP) != 0) {
54432- pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_AUTOFULL;
54433- }
54434- else {
54435- pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_AUTOHALF;
54436- }
54437-
54438- /* Check PAUSE mismatch ??? */
54439- /* We are using IEEE 802.3z/D5.0 Table 37-4 */
54440- if ((AuxStat & PHY_M_PS_PAUSE_MSK) == PHY_M_PS_PAUSE_MSK) {
54441- /* Symmetric PAUSE */
54442- pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC;
54443- }
54444- else if ((AuxStat & PHY_M_PS_PAUSE_MSK) == PHY_M_PS_RX_P_EN) {
54445- /* Enable PAUSE receive, disable PAUSE transmit */
54446- pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND;
54447- }
54448- else if ((AuxStat & PHY_M_PS_PAUSE_MSK) == PHY_M_PS_TX_P_EN) {
54449- /* Disable PAUSE receive, enable PAUSE transmit */
54450- pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND;
54451+
54452+ pPrt->PLinkModeStatus = (SK_U8)(((AuxStat & PHY_M_PS_FULL_DUP) != 0) ?
54453+ SK_LMODE_STAT_AUTOFULL : SK_LMODE_STAT_AUTOHALF);
54454+
54455+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) {
54456+ /* set used link speed */
54457+ pPrt->PLinkSpeedUsed = (SK_U8)(((AuxStat & PHY_M_PS_SPEED_100) != 0) ?
54458+ SK_LSPEED_STAT_100MBPS : SK_LSPEED_STAT_10MBPS);
54459 }
54460 else {
54461- /* PAUSE mismatch -> no PAUSE */
54462- pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
54463+ /* set used link speed */
54464+ switch ((unsigned)(AuxStat & PHY_M_PS_SPEED_MSK)) {
54465+ case (unsigned)PHY_M_PS_SPEED_1000:
54466+ pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_1000MBPS;
54467+ break;
54468+ case PHY_M_PS_SPEED_100:
54469+ pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_100MBPS;
54470+ break;
54471+ default:
54472+ pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_10MBPS;
54473+ }
54474+
54475+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL ||
54476+ pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U) {
54477+ /* Tx & Rx Pause Enabled bits are at 9..8 */
54478+ AuxStat >>= 6;
54479+
54480+ if (!pAC->GIni.GICopperType) {
54481+ /* always 1000 Mbps on fiber */
54482+ pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_1000MBPS;
54483+ }
54484+ }
54485+
54486+ AuxStat &= PHY_M_PS_PAUSE_MSK;
54487+ /* We are using IEEE 802.3z/D5.0 Table 37-4 */
54488+ if (AuxStat == PHY_M_PS_PAUSE_MSK) {
54489+ /* Symmetric PAUSE */
54490+ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_SYMMETRIC;
54491+ }
54492+ else if (AuxStat == PHY_M_PS_RX_P_EN) {
54493+ /* enable PAUSE receive, disable PAUSE transmit */
54494+ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND;
54495+ }
54496+ else if (AuxStat == PHY_M_PS_TX_P_EN) {
54497+ /* disable PAUSE receive, enable PAUSE transmit */
54498+ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND;
54499+ }
54500+ else {
54501+ /* PAUSE mismatch -> no PAUSE */
54502+ pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
54503+ }
54504 }
54505-
54506- /* set used link speed */
54507- switch ((unsigned)(AuxStat & PHY_M_PS_SPEED_MSK)) {
54508- case (unsigned)PHY_M_PS_SPEED_1000:
54509- pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_1000MBPS;
54510- break;
54511- case PHY_M_PS_SPEED_100:
54512- pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_100MBPS;
54513- break;
54514- default:
54515- pPrt->PLinkSpeedUsed = (SK_U8)SK_LSPEED_STAT_10MBPS;
54516+
54517+ if ((pPrt->PFlowCtrlStatus == SK_FLOW_STAT_NONE) ||
54518+ /* disable Pause also for 10/100 Mbps in half duplex mode */
54519+ ((pAC->GIni.GIChipId != CHIP_ID_YUKON_EC_U) &&
54520+ (pPrt->PLinkSpeedUsed < (SK_U8)SK_LSPEED_STAT_1000MBPS) &&
54521+ pPrt->PLinkModeStatus == (SK_U8)SK_LMODE_STAT_AUTOHALF)) {
54522+
54523+ /* set Pause Off */
54524+ PauseMode = (SK_U8)GMC_PAUSE_OFF;
54525 }
54526
54527+ SK_OUT8(IoC, MR_ADDR(Port, GMAC_CTRL), PauseMode);
54528+
54529 return(SK_AND_OK);
54530 } /* SkGmAutoNegDoneMarv */
54531 #endif /* YUKON */
54532+#endif /* !SK_SLIM */
54533
54534
54535 #ifdef OTHER_PHY
54536@@ -3229,17 +3853,17 @@
54537 *
54538 * Returns:
54539 * SK_AND_OK o.k.
54540- * SK_AND_DUP_CAP Duplex capability error happened
54541- * SK_AND_OTHER Other error happened
54542+ * SK_AND_DUP_CAP Duplex capability error happened
54543+ * SK_AND_OTHER Other error happened
54544 */
54545 static int SkXmAutoNegDoneLone(
54546-SK_AC *pAC, /* adapter context */
54547-SK_IOC IoC, /* IO context */
54548+SK_AC *pAC, /* Adapter Context */
54549+SK_IOC IoC, /* I/O Context */
54550 int Port) /* Port Index (MAC_1 + n) */
54551 {
54552 SK_GEPORT *pPrt;
54553 SK_U16 ResAb; /* Resolved Ability */
54554- SK_U16 LPAb; /* Link Partner Ability */
54555+ SK_U16 LinkPartAb; /* Link Partner Ability */
54556 SK_U16 QuickStat; /* Auxiliary Status */
54557
54558 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
54559@@ -3247,16 +3871,16 @@
54560 pPrt = &pAC->GIni.GP[Port];
54561
54562 /* Get PHY parameters */
54563- SkXmPhyRead(pAC, IoC, Port, PHY_LONE_AUNE_LP, &LPAb);
54564+ SkXmPhyRead(pAC, IoC, Port, PHY_LONE_AUNE_LP, &LinkPartAb);
54565 SkXmPhyRead(pAC, IoC, Port, PHY_LONE_1000T_STAT, &ResAb);
54566 SkXmPhyRead(pAC, IoC, Port, PHY_LONE_Q_STAT, &QuickStat);
54567
54568- if ((LPAb & PHY_L_AN_RF) != 0) {
54569+ if ((LinkPartAb & PHY_L_AN_RF) != 0) {
54570 /* Remote fault bit is set */
54571- /* Error */
54572- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
54573+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
54574 ("AutoNegFail: Remote fault bit set Port %d\n", Port));
54575 pPrt->PAutoNegFail = SK_TRUE;
54576+
54577 return(SK_AND_OTHER);
54578 }
54579
54580@@ -3267,28 +3891,25 @@
54581 else {
54582 pPrt->PLinkModeStatus = (SK_U8)SK_LMODE_STAT_AUTOHALF;
54583 }
54584-
54585+
54586 /* Check Master/Slave resolution */
54587 if ((ResAb & PHY_L_1000S_MSF) != 0) {
54588 /* Error */
54589- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
54590+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
54591 ("Master/Slave Fault Port %d\n", Port));
54592 pPrt->PAutoNegFail = SK_TRUE;
54593 pPrt->PMSStatus = SK_MS_STAT_FAULT;
54594 return(SK_AND_OTHER);
54595 }
54596- else if (ResAb & PHY_L_1000S_MSR) {
54597- pPrt->PMSStatus = SK_MS_STAT_MASTER;
54598- }
54599- else {
54600- pPrt->PMSStatus = SK_MS_STAT_SLAVE;
54601- }
54602+
54603+ pPrt->PMSStatus = ((ResAb & PHY_L_1000S_MSR) != 0) ?
54604+ (SK_U8)SK_MS_STAT_MASTER : (SK_U8)SK_MS_STAT_SLAVE;
54605
54606 /* Check PAUSE mismatch */
54607 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
54608 /* we must manually resolve the abilities here */
54609 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
54610-
54611+
54612 switch (pPrt->PFlowCtrlMode) {
54613 case SK_FLOW_MODE_NONE:
54614 /* default */
54615@@ -3296,7 +3917,7 @@
54616 case SK_FLOW_MODE_LOC_SEND:
54617 if ((QuickStat & (PHY_L_QS_PAUSE | PHY_L_QS_AS_PAUSE)) ==
54618 (PHY_L_QS_PAUSE | PHY_L_QS_AS_PAUSE)) {
54619- /* Disable PAUSE receive, enable PAUSE transmit */
54620+ /* disable PAUSE receive, enable PAUSE transmit */
54621 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_LOC_SEND;
54622 }
54623 break;
54624@@ -3309,7 +3930,7 @@
54625 case SK_FLOW_MODE_SYM_OR_REM:
54626 if ((QuickStat & (PHY_L_QS_PAUSE | PHY_L_QS_AS_PAUSE)) ==
54627 PHY_L_QS_AS_PAUSE) {
54628- /* Enable PAUSE receive, disable PAUSE transmit */
54629+ /* enable PAUSE receive, disable PAUSE transmit */
54630 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_REM_SEND;
54631 }
54632 else if ((QuickStat & PHY_L_QS_PAUSE) != 0) {
54633@@ -3321,7 +3942,7 @@
54634 SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E016,
54635 SKERR_HWI_E016MSG);
54636 }
54637-
54638+
54639 return(SK_AND_OK);
54640 } /* SkXmAutoNegDoneLone */
54641
54642@@ -3335,12 +3956,12 @@
54643 *
54644 * Returns:
54645 * SK_AND_OK o.k.
54646- * SK_AND_DUP_CAP Duplex capability error happened
54647- * SK_AND_OTHER Other error happened
54648+ * SK_AND_DUP_CAP Duplex capability error happened
54649+ * SK_AND_OTHER Other error happened
54650 */
54651 static int SkXmAutoNegDoneNat(
54652-SK_AC *pAC, /* adapter context */
54653-SK_IOC IoC, /* IO context */
54654+SK_AC *pAC, /* Adapter Context */
54655+SK_IOC IoC, /* I/O Context */
54656 int Port) /* Port Index (MAC_1 + n) */
54657 {
54658 /* todo: National */
54659@@ -3357,12 +3978,12 @@
54660 *
54661 * Returns:
54662 * SK_AND_OK o.k.
54663- * SK_AND_DUP_CAP Duplex capability error happened
54664- * SK_AND_OTHER Other error happened
54665+ * SK_AND_DUP_CAP Duplex capability error happened
54666+ * SK_AND_OTHER Other error happened
54667 */
54668-int SkMacAutoNegDone(
54669-SK_AC *pAC, /* adapter context */
54670-SK_IOC IoC, /* IO context */
54671+int SkMacAutoNegDone(
54672+SK_AC *pAC, /* Adapter Context */
54673+SK_IOC IoC, /* I/O Context */
54674 int Port) /* Port Index (MAC_1 + n) */
54675 {
54676 SK_GEPORT *pPrt;
54677@@ -3374,9 +3995,9 @@
54678
54679 #ifdef GENESIS
54680 if (pAC->GIni.GIGenesis) {
54681-
54682+
54683 switch (pPrt->PhyType) {
54684-
54685+
54686 case SK_PHY_XMAC:
54687 Rtv = SkXmAutoNegDoneXmac(pAC, IoC, Port);
54688 break;
54689@@ -3396,30 +4017,33 @@
54690 }
54691 }
54692 #endif /* GENESIS */
54693-
54694+
54695+#ifndef SK_SLIM
54696 #ifdef YUKON
54697 if (pAC->GIni.GIYukon) {
54698-
54699+
54700 Rtv = SkGmAutoNegDoneMarv(pAC, IoC, Port);
54701 }
54702 #endif /* YUKON */
54703-
54704+
54705 if (Rtv != SK_AND_OK) {
54706 return(Rtv);
54707 }
54708
54709 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
54710 ("AutoNeg done Port %d\n", Port));
54711-
54712+
54713 /* We checked everything and may now enable the link */
54714 pPrt->PAutoNegFail = SK_FALSE;
54715+#endif /* !SK_SLIM */
54716
54717 SkMacRxTxEnable(pAC, IoC, Port);
54718-
54719+
54720 return(SK_AND_OK);
54721 } /* SkMacAutoNegDone */
54722
54723
54724+#ifndef SK_SLIM
54725 #ifdef GENESIS
54726 /******************************************************************************
54727 *
54728@@ -3433,7 +4057,7 @@
54729 */
54730 static void SkXmSetRxTxEn(
54731 SK_AC *pAC, /* Adapter Context */
54732-SK_IOC IoC, /* IO context */
54733+SK_IOC IoC, /* I/O Context */
54734 int Port, /* Port Index (MAC_1 + n) */
54735 int Para) /* Parameter to set: MAC or PHY LoopBack, Duplex Mode */
54736 {
54737@@ -3458,7 +4082,7 @@
54738 Word &= ~XM_MMU_GMII_LOOP;
54739 break;
54740 }
54741-
54742+
54743 switch (Para & (SK_PHY_FULLD_ON | SK_PHY_FULLD_OFF)) {
54744 case SK_PHY_FULLD_ON:
54745 Word |= XM_MMU_GMII_FD;
54746@@ -3467,7 +4091,7 @@
54747 Word &= ~XM_MMU_GMII_FD;
54748 break;
54749 }
54750-
54751+
54752 XM_OUT16(IoC, Port, XM_MMU_CMD, Word | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
54753
54754 /* dummy read to ensure writing */
54755@@ -3490,12 +4114,12 @@
54756 */
54757 static void SkGmSetRxTxEn(
54758 SK_AC *pAC, /* Adapter Context */
54759-SK_IOC IoC, /* IO context */
54760+SK_IOC IoC, /* I/O Context */
54761 int Port, /* Port Index (MAC_1 + n) */
54762 int Para) /* Parameter to set: MAC LoopBack, Duplex Mode */
54763 {
54764 SK_U16 Ctrl;
54765-
54766+
54767 GM_IN16(IoC, Port, GM_GP_CTRL, &Ctrl);
54768
54769 switch (Para & (SK_MAC_LOOPB_ON | SK_MAC_LOOPB_OFF)) {
54770@@ -3515,18 +4139,18 @@
54771 Ctrl &= ~GM_GPCR_DUP_FULL;
54772 break;
54773 }
54774-
54775- GM_OUT16(IoC, Port, GM_GP_CTRL, (SK_U16)(Ctrl | GM_GPCR_RX_ENA |
54776- GM_GPCR_TX_ENA));
54777
54778+ GM_OUT16(IoC, Port, GM_GP_CTRL, Ctrl | GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
54779+
54780+#ifdef XXX
54781 /* dummy read to ensure writing */
54782 GM_IN16(IoC, Port, GM_GP_CTRL, &Ctrl);
54783+#endif /* XXX */
54784
54785 } /* SkGmSetRxTxEn */
54786 #endif /* YUKON */
54787
54788
54789-#ifndef SK_SLIM
54790 /******************************************************************************
54791 *
54792 * SkMacSetRxTxEn() - Special Set Rx/Tx Enable and parameters
54793@@ -3537,20 +4161,20 @@
54794 */
54795 void SkMacSetRxTxEn(
54796 SK_AC *pAC, /* Adapter Context */
54797-SK_IOC IoC, /* IO context */
54798+SK_IOC IoC, /* I/O Context */
54799 int Port, /* Port Index (MAC_1 + n) */
54800 int Para)
54801 {
54802 #ifdef GENESIS
54803 if (pAC->GIni.GIGenesis) {
54804-
54805+
54806 SkXmSetRxTxEn(pAC, IoC, Port, Para);
54807 }
54808 #endif /* GENESIS */
54809-
54810+
54811 #ifdef YUKON
54812 if (pAC->GIni.GIYukon) {
54813-
54814+
54815 SkGmSetRxTxEn(pAC, IoC, Port, Para);
54816 }
54817 #endif /* YUKON */
54818@@ -3570,8 +4194,8 @@
54819 * != 0 Error happened
54820 */
54821 int SkMacRxTxEnable(
54822-SK_AC *pAC, /* adapter context */
54823-SK_IOC IoC, /* IO context */
54824+SK_AC *pAC, /* Adapter Context */
54825+SK_IOC IoC, /* I/O Context */
54826 int Port) /* Port Index (MAC_1 + n) */
54827 {
54828 SK_GEPORT *pPrt;
54829@@ -3589,9 +4213,9 @@
54830 }
54831
54832 if ((pPrt->PLinkMode == SK_LMODE_AUTOHALF ||
54833- pPrt->PLinkMode == SK_LMODE_AUTOFULL ||
54834- pPrt->PLinkMode == SK_LMODE_AUTOBOTH) &&
54835- pPrt->PAutoNegFail) {
54836+ pPrt->PLinkMode == SK_LMODE_AUTOFULL ||
54837+ pPrt->PLinkMode == SK_LMODE_AUTOBOTH) &&
54838+ pPrt->PAutoNegFail) {
54839 /* Auto-negotiation is not done or failed */
54840 return(0);
54841 }
54842@@ -3600,9 +4224,9 @@
54843 if (pAC->GIni.GIGenesis) {
54844 /* set Duplex Mode and Pause Mode */
54845 SkXmInitDupMd(pAC, IoC, Port);
54846-
54847+
54848 SkXmInitPauseMd(pAC, IoC, Port);
54849-
54850+
54851 /*
54852 * Initialize the Interrupt Mask Register. Default IRQs are...
54853 * - Link Asynchronous Event
54854@@ -3618,23 +4242,23 @@
54855 /* add IRQ for Receive FIFO Overflow */
54856 IntMask &= ~XM_IS_RXF_OV;
54857 #endif /* DEBUG */
54858-
54859+
54860 if (pPrt->PhyType != SK_PHY_XMAC) {
54861 /* disable GP0 interrupt bit */
54862 IntMask |= XM_IS_INP_ASS;
54863 }
54864 XM_OUT16(IoC, Port, XM_IMSK, IntMask);
54865-
54866+
54867 /* get MMU Command Reg. */
54868 XM_IN16(IoC, Port, XM_MMU_CMD, &Reg);
54869-
54870+
54871 if (pPrt->PhyType != SK_PHY_XMAC &&
54872 (pPrt->PLinkModeStatus == SK_LMODE_STAT_FULL ||
54873 pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOFULL)) {
54874 /* set to Full Duplex */
54875 Reg |= XM_MMU_GMII_FD;
54876 }
54877-
54878+
54879 switch (pPrt->PhyType) {
54880 case SK_PHY_BCOM:
54881 /*
54882@@ -3644,7 +4268,7 @@
54883 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &SWord);
54884 SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUX_CTRL,
54885 (SK_U16)(SWord & ~PHY_B_AC_DIS_PM));
54886- SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_INT_MASK,
54887+ SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_INT_MASK,
54888 (SK_U16)PHY_B_DEF_MSK);
54889 break;
54890 #ifdef OTHER_PHY
54891@@ -3658,12 +4282,12 @@
54892 break;
54893 #endif /* OTHER_PHY */
54894 }
54895-
54896+
54897 /* enable Rx/Tx */
54898 XM_OUT16(IoC, Port, XM_MMU_CMD, Reg | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
54899 }
54900 #endif /* GENESIS */
54901-
54902+
54903 #ifdef YUKON
54904 if (pAC->GIni.GIYukon) {
54905 /*
54906@@ -3674,34 +4298,34 @@
54907 */
54908 IntMask = GMAC_DEF_MSK;
54909
54910-#ifdef DEBUG
54911+#if (defined(DEBUG) || defined(YUK2)) && (!defined(SK_SLIM))
54912 /* add IRQ for Receive FIFO Overrun */
54913 IntMask |= GM_IS_RX_FF_OR;
54914-#endif /* DEBUG */
54915-
54916- SK_OUT8(IoC, GMAC_IRQ_MSK, (SK_U8)IntMask);
54917-
54918+#endif
54919+
54920+ SK_OUT8(IoC, MR_ADDR(Port, GMAC_IRQ_MSK), (SK_U8)IntMask);
54921+
54922 /* get General Purpose Control */
54923 GM_IN16(IoC, Port, GM_GP_CTRL, &Reg);
54924-
54925+
54926 if (pPrt->PLinkModeStatus == SK_LMODE_STAT_FULL ||
54927 pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOFULL) {
54928 /* set to Full Duplex */
54929 Reg |= GM_GPCR_DUP_FULL;
54930 }
54931-
54932+
54933 /* enable Rx/Tx */
54934- GM_OUT16(IoC, Port, GM_GP_CTRL, (SK_U16)(Reg | GM_GPCR_RX_ENA |
54935- GM_GPCR_TX_ENA));
54936+ GM_OUT16(IoC, Port, GM_GP_CTRL, Reg | GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
54937
54938-#ifndef VCPU
54939- /* Enable all PHY interrupts */
54940- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK,
54941- (SK_U16)PHY_M_DEF_MSK);
54942-#endif /* VCPU */
54943+#ifdef XXX
54944+ /* dummy read to ensure writing */
54945+ GM_IN16(IoC, Port, GM_GP_CTRL, &Reg);
54946+#endif /* XXX */
54947 }
54948 #endif /* YUKON */
54949-
54950+
54951+ pAC->GIni.GP[Port].PState = SK_PRT_RUN;
54952+
54953 return(0);
54954
54955 } /* SkMacRxTxEnable */
54956@@ -3717,33 +4341,38 @@
54957 */
54958 void SkMacRxTxDisable(
54959 SK_AC *pAC, /* Adapter Context */
54960-SK_IOC IoC, /* IO context */
54961+SK_IOC IoC, /* I/O Context */
54962 int Port) /* Port Index (MAC_1 + n) */
54963 {
54964 SK_U16 Word;
54965
54966 #ifdef GENESIS
54967 if (pAC->GIni.GIGenesis) {
54968-
54969+
54970 XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
54971-
54972- XM_OUT16(IoC, Port, XM_MMU_CMD, Word & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
54973-
54974+
54975+ Word &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
54976+
54977+ XM_OUT16(IoC, Port, XM_MMU_CMD, Word);
54978+
54979 /* dummy read to ensure writing */
54980 XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
54981 }
54982 #endif /* GENESIS */
54983-
54984+
54985 #ifdef YUKON
54986 if (pAC->GIni.GIYukon) {
54987-
54988+
54989 GM_IN16(IoC, Port, GM_GP_CTRL, &Word);
54990
54991- GM_OUT16(IoC, Port, GM_GP_CTRL, (SK_U16)(Word & ~(GM_GPCR_RX_ENA |
54992- GM_GPCR_TX_ENA)));
54993+ Word &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
54994
54995+ GM_OUT16(IoC, Port, GM_GP_CTRL, Word);
54996+
54997+#ifdef XXX
54998 /* dummy read to ensure writing */
54999 GM_IN16(IoC, Port, GM_GP_CTRL, &Word);
55000+#endif /* XXX */
55001 }
55002 #endif /* YUKON */
55003
55004@@ -3760,7 +4389,7 @@
55005 */
55006 void SkMacIrqDisable(
55007 SK_AC *pAC, /* Adapter Context */
55008-SK_IOC IoC, /* IO context */
55009+SK_IOC IoC, /* I/O Context */
55010 int Port) /* Port Index (MAC_1 + n) */
55011 {
55012 SK_GEPORT *pPrt;
55013@@ -3772,18 +4401,18 @@
55014
55015 #ifdef GENESIS
55016 if (pAC->GIni.GIGenesis) {
55017-
55018+
55019 /* disable all XMAC IRQs */
55020- XM_OUT16(IoC, Port, XM_IMSK, 0xffff);
55021-
55022- /* Disable all PHY interrupts */
55023+ XM_OUT16(IoC, Port, XM_IMSK, 0xffff);
55024+
55025+ /* disable all PHY interrupts */
55026 switch (pPrt->PhyType) {
55027 case SK_PHY_BCOM:
55028 /* Make sure that PHY is initialized */
55029 if (pPrt->PState != SK_PRT_RESET) {
55030 /* NOT allowed if BCOM is in RESET state */
55031 /* Workaround BCOM Errata (#10523) all BCom */
55032- /* Disable Power Management if link is down */
55033+ /* disable Power Management if link is down */
55034 SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &Word);
55035 SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUX_CTRL,
55036 (SK_U16)(Word | PHY_B_AC_DIS_PM));
55037@@ -3802,16 +4431,16 @@
55038 }
55039 }
55040 #endif /* GENESIS */
55041-
55042+
55043 #ifdef YUKON
55044 if (pAC->GIni.GIYukon) {
55045 /* disable all GMAC IRQs */
55046- SK_OUT8(IoC, GMAC_IRQ_MSK, 0);
55047-
55048+ SK_OUT8(IoC, MR_ADDR(Port, GMAC_IRQ_MSK), 0);
55049+
55050 #ifndef VCPU
55051- /* Disable all PHY interrupts */
55052+ /* disable all PHY interrupts */
55053 SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, 0);
55054-#endif /* VCPU */
55055+#endif /* !VCPU */
55056 }
55057 #endif /* YUKON */
55058
55059@@ -3823,29 +4452,72 @@
55060 *
55061 * SkXmSendCont() - Enable / Disable Send Continuous Mode
55062 *
55063- * Description: enable / disable Send Continuous Mode on XMAC
55064+ * Description: enable / disable Send Continuous Mode on XMAC resp.
55065+ * Packet Generation on GPHY
55066 *
55067 * Returns:
55068 * nothing
55069 */
55070 void SkXmSendCont(
55071-SK_AC *pAC, /* adapter context */
55072-SK_IOC IoC, /* IO context */
55073+SK_AC *pAC, /* Adapter Context */
55074+SK_IOC IoC, /* I/O Context */
55075 int Port, /* Port Index (MAC_1 + n) */
55076 SK_BOOL Enable) /* Enable / Disable */
55077 {
55078+ SK_U16 Reg;
55079+ SK_U16 Save;
55080 SK_U32 MdReg;
55081
55082- XM_IN32(IoC, Port, XM_MODE, &MdReg);
55083+ if (pAC->GIni.GIGenesis) {
55084+ XM_IN32(IoC, Port, XM_MODE, &MdReg);
55085
55086- if (Enable) {
55087- MdReg |= XM_MD_TX_CONT;
55088+ if (Enable) {
55089+ MdReg |= XM_MD_TX_CONT;
55090+ }
55091+ else {
55092+ MdReg &= ~XM_MD_TX_CONT;
55093+ }
55094+ /* setup Mode Register */
55095+ XM_OUT32(IoC, Port, XM_MODE, MdReg);
55096 }
55097 else {
55098- MdReg &= ~XM_MD_TX_CONT;
55099+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) {
55100+ /* select page 18 */
55101+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_ADDR, 18);
55102+
55103+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PAGE_DATA, &Reg);
55104+
55105+ Reg &= ~0x003c; /* clear bits 5..2 */
55106+
55107+ if (Enable) {
55108+ /* enable packet generation, 1518 byte length */
55109+ Reg |= (BIT_5S | BIT_3S);
55110+ }
55111+
55112+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, Reg);
55113+ }
55114+ else if (pAC->GIni.GIChipId == CHIP_ID_YUKON_XL) {
55115+ /* save page register */
55116+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_ADR, &Save);
55117+
55118+ /* select page 6 to access Packet Generation register */
55119+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 6);
55120+
55121+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_CTRL, &Reg);
55122+
55123+ Reg &= ~0x003f; /* clear bits 5..0 */
55124+
55125+ if (Enable) {
55126+ /* enable packet generation, 1518 byte length */
55127+ Reg |= (BIT_3S | BIT_1S);
55128+ }
55129+
55130+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PHY_CTRL, Reg);
55131+
55132+ /* restore page register */
55133+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, Save);
55134+ }
55135 }
55136- /* setup Mode Register */
55137- XM_OUT32(IoC, Port, XM_MODE, MdReg);
55138
55139 } /* SkXmSendCont */
55140
55141@@ -3860,8 +4532,8 @@
55142 * nothing
55143 */
55144 void SkMacTimeStamp(
55145-SK_AC *pAC, /* adapter context */
55146-SK_IOC IoC, /* IO context */
55147+SK_AC *pAC, /* Adapter Context */
55148+SK_IOC IoC, /* I/O Context */
55149 int Port, /* Port Index (MAC_1 + n) */
55150 SK_BOOL Enable) /* Enable / Disable */
55151 {
55152@@ -3906,8 +4578,8 @@
55153 * is set true.
55154 */
55155 void SkXmAutoNegLipaXmac(
55156-SK_AC *pAC, /* adapter context */
55157-SK_IOC IoC, /* IO context */
55158+SK_AC *pAC, /* Adapter Context */
55159+SK_IOC IoC, /* I/O Context */
55160 int Port, /* Port Index (MAC_1 + n) */
55161 SK_U16 IStatus) /* Interrupt Status word to analyse */
55162 {
55163@@ -3919,8 +4591,9 @@
55164 (IStatus & (XM_IS_LIPA_RC | XM_IS_RX_PAGE | XM_IS_AND)) != 0) {
55165
55166 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
55167- ("AutoNegLipa: AutoNeg detected on Port %d, IStatus=0x%04X\n",
55168+ ("AutoNegLipa: AutoNeg detected on Port %d, IStatus = 0x%04X\n",
55169 Port, IStatus));
55170+
55171 pPrt->PLipaAutoNeg = SK_LIPA_AUTO;
55172 }
55173 } /* SkXmAutoNegLipaXmac */
55174@@ -3936,8 +4609,8 @@
55175 * is set true.
55176 */
55177 void SkMacAutoNegLipaPhy(
55178-SK_AC *pAC, /* adapter context */
55179-SK_IOC IoC, /* IO context */
55180+SK_AC *pAC, /* Adapter Context */
55181+SK_IOC IoC, /* I/O Context */
55182 int Port, /* Port Index (MAC_1 + n) */
55183 SK_U16 PhyStat) /* PHY Status word to analyse */
55184 {
55185@@ -3949,8 +4622,9 @@
55186 (PhyStat & PHY_ST_AN_OVER) != 0) {
55187
55188 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
55189- ("AutoNegLipa: AutoNeg detected on Port %d, PhyStat=0x%04X\n",
55190+ ("AutoNegLipa: AutoNeg detected on Port %d, PhyStat = 0x%04X\n",
55191 Port, PhyStat));
55192+
55193 pPrt->PLipaAutoNeg = SK_LIPA_AUTO;
55194 }
55195 } /* SkMacAutoNegLipaPhy */
55196@@ -3965,7 +4639,7 @@
55197 *
55198 * Note:
55199 * With an external PHY, some interrupt bits are not meaningfull any more:
55200- * - LinkAsyncEvent (bit #14) XM_IS_LNK_AE
55201+ * - LinkAsyncEvent (bit #14) XM_IS_LNK_AE
55202 * - LinkPartnerReqConfig (bit #10) XM_IS_LIPA_RC
55203 * - Page Received (bit #9) XM_IS_RX_PAGE
55204 * - NextPageLoadedForXmt (bit #8) XM_IS_TX_PAGE
55205@@ -3977,22 +4651,23 @@
55206 * nothing
55207 */
55208 void SkXmIrq(
55209-SK_AC *pAC, /* adapter context */
55210-SK_IOC IoC, /* IO context */
55211+SK_AC *pAC, /* Adapter Context */
55212+SK_IOC IoC, /* I/O Context */
55213 int Port) /* Port Index (MAC_1 + n) */
55214 {
55215 SK_GEPORT *pPrt;
55216- SK_EVPARA Para;
55217 SK_U16 IStatus; /* Interrupt status read from the XMAC */
55218 SK_U16 IStatus2;
55219 #ifdef SK_SLIM
55220- SK_U64 OverflowStatus;
55221-#endif
55222+ SK_U64 OverflowStatus;
55223+#else
55224+ SK_EVPARA Para;
55225+#endif /* SK_SLIM */
55226
55227 pPrt = &pAC->GIni.GP[Port];
55228-
55229+
55230 XM_IN16(IoC, Port, XM_ISRC, &IStatus);
55231-
55232+
55233 /* LinkPartner Auto-negable? */
55234 if (pPrt->PhyType == SK_PHY_XMAC) {
55235 SkXmAutoNegLipaXmac(pAC, IoC, Port, IStatus);
55236@@ -4003,7 +4678,7 @@
55237 XM_IS_RX_PAGE | XM_IS_TX_PAGE |
55238 XM_IS_AND | XM_IS_INP_ASS);
55239 }
55240-
55241+
55242 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
55243 ("XmacIrq Port %d Isr 0x%04X\n", Port, IStatus));
55244
55245@@ -4113,49 +4788,55 @@
55246 * nothing
55247 */
55248 void SkGmIrq(
55249-SK_AC *pAC, /* adapter context */
55250-SK_IOC IoC, /* IO context */
55251+SK_AC *pAC, /* Adapter Context */
55252+SK_IOC IoC, /* I/O Context */
55253 int Port) /* Port Index (MAC_1 + n) */
55254 {
55255 SK_GEPORT *pPrt;
55256 SK_U8 IStatus; /* Interrupt status */
55257 #ifdef SK_SLIM
55258- SK_U64 OverflowStatus;
55259+ SK_U64 OverflowStatus;
55260 #else
55261 SK_EVPARA Para;
55262-#endif
55263+#endif /* SK_SLIM */
55264
55265 pPrt = &pAC->GIni.GP[Port];
55266-
55267- SK_IN8(IoC, GMAC_IRQ_SRC, &IStatus);
55268-
55269+
55270+ SK_IN8(IoC, MR_ADDR(Port, GMAC_IRQ_SRC), &IStatus);
55271+
55272 #ifdef XXX
55273 /* LinkPartner Auto-negable? */
55274 SkMacAutoNegLipaPhy(pAC, IoC, Port, IStatus);
55275 #endif /* XXX */
55276-
55277+
55278 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
55279- ("GmacIrq Port %d Isr 0x%04X\n", Port, IStatus));
55280+ ("GmacIrq Port %d Isr 0x%02X\n", Port, IStatus));
55281
55282 /* Combined Tx & Rx Counter Overflow SIRQ Event */
55283 if (IStatus & (GM_IS_RX_CO_OV | GM_IS_TX_CO_OV)) {
55284 /* these IRQs will be cleared by reading GMACs register */
55285 #ifdef SK_SLIM
55286- SkGmOverflowStatus(pAC, IoC, Port, IStatus, &OverflowStatus);
55287+ SkGmOverflowStatus(pAC, IoC, Port, (SK_U16)IStatus, &OverflowStatus);
55288 #else
55289 Para.Para32[0] = (SK_U32)Port;
55290 Para.Para32[1] = (SK_U32)IStatus;
55291 SkPnmiEvent(pAC, IoC, SK_PNMI_EVT_SIRQ_OVERFLOW, Para);
55292-#endif
55293+#endif /* SK_SLIM */
55294 }
55295
55296+#ifndef SK_SLIM
55297 if (IStatus & GM_IS_RX_FF_OR) {
55298 /* clear GMAC Rx FIFO Overrun IRQ */
55299 SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_CLI_RX_FO);
55300+
55301+ Para.Para64 = Port;
55302+ SkEventQueue(pAC, SKGE_DRV, SK_DRV_RX_OVERFLOW, Para);
55303+
55304 #ifdef DEBUG
55305 pPrt->PRxOverCnt++;
55306 #endif /* DEBUG */
55307 }
55308+#endif /* !SK_SLIM */
55309
55310 if (IStatus & GM_IS_TX_FF_UR) {
55311 /* clear GMAC Tx FIFO Underrun IRQ */
55312@@ -4185,8 +4866,8 @@
55313 * nothing
55314 */
55315 void SkMacIrq(
55316-SK_AC *pAC, /* adapter context */
55317-SK_IOC IoC, /* IO context */
55318+SK_AC *pAC, /* Adapter Context */
55319+SK_IOC IoC, /* I/O Context */
55320 int Port) /* Port Index (MAC_1 + n) */
55321 {
55322 #ifdef GENESIS
55323@@ -4195,7 +4876,7 @@
55324 SkXmIrq(pAC, IoC, Port);
55325 }
55326 #endif /* GENESIS */
55327-
55328+
55329 #ifdef YUKON
55330 if (pAC->GIni.GIYukon) {
55331 /* IRQ from GMAC */
55332@@ -4222,8 +4903,8 @@
55333 * 1: something went wrong
55334 */
55335 int SkXmUpdateStats(
55336-SK_AC *pAC, /* adapter context */
55337-SK_IOC IoC, /* IO context */
55338+SK_AC *pAC, /* Adapter Context */
55339+SK_IOC IoC, /* I/O Context */
55340 unsigned int Port) /* Port Index (MAC_1 + n) */
55341 {
55342 SK_GEPORT *pPrt;
55343@@ -4245,7 +4926,7 @@
55344 do {
55345
55346 XM_IN16(IoC, Port, XM_STAT_CMD, &StatReg);
55347-
55348+
55349 if (++WaitIndex > 10) {
55350
55351 SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E021, SKERR_HWI_E021MSG);
55352@@ -4253,7 +4934,7 @@
55353 return(1);
55354 }
55355 } while ((StatReg & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) != 0);
55356-
55357+
55358 return(0);
55359 } /* SkXmUpdateStats */
55360
55361@@ -4272,19 +4953,19 @@
55362 * 1: something went wrong
55363 */
55364 int SkXmMacStatistic(
55365-SK_AC *pAC, /* adapter context */
55366-SK_IOC IoC, /* IO context */
55367+SK_AC *pAC, /* Adapter Context */
55368+SK_IOC IoC, /* I/O Context */
55369 unsigned int Port, /* Port Index (MAC_1 + n) */
55370 SK_U16 StatAddr, /* MIB counter base address */
55371-SK_U32 SK_FAR *pVal) /* ptr to return statistic value */
55372+SK_U32 SK_FAR *pVal) /* Pointer to return statistic value */
55373 {
55374 if ((StatAddr < XM_TXF_OK) || (StatAddr > XM_RXF_MAX_SZ)) {
55375-
55376+
55377 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E022, SKERR_HWI_E022MSG);
55378-
55379+
55380 return(1);
55381 }
55382-
55383+
55384 XM_IN32(IoC, Port, StatAddr, pVal);
55385
55386 return(0);
55387@@ -4303,12 +4984,12 @@
55388 * 1: something went wrong
55389 */
55390 int SkXmResetCounter(
55391-SK_AC *pAC, /* adapter context */
55392-SK_IOC IoC, /* IO context */
55393+SK_AC *pAC, /* Adapter Context */
55394+SK_IOC IoC, /* I/O Context */
55395 unsigned int Port) /* Port Index (MAC_1 + n) */
55396 {
55397 XM_OUT16(IoC, Port, XM_STAT_CMD, XM_SC_CLR_RXC | XM_SC_CLR_TXC);
55398- /* Clear two times according to Errata #3 */
55399+ /* Clear two times according to XMAC Errata #3 */
55400 XM_OUT16(IoC, Port, XM_STAT_CMD, XM_SC_CLR_RXC | XM_SC_CLR_TXC);
55401
55402 return(0);
55403@@ -4335,11 +5016,11 @@
55404 * 1: something went wrong
55405 */
55406 int SkXmOverflowStatus(
55407-SK_AC *pAC, /* adapter context */
55408-SK_IOC IoC, /* IO context */
55409+SK_AC *pAC, /* Adapter Context */
55410+SK_IOC IoC, /* I/O Context */
55411 unsigned int Port, /* Port Index (MAC_1 + n) */
55412-SK_U16 IStatus, /* Interupt Status from MAC */
55413-SK_U64 SK_FAR *pStatus) /* ptr for return overflow status value */
55414+SK_U16 IStatus, /* Interrupt Status from MAC */
55415+SK_U64 SK_FAR *pStatus) /* Pointer for return overflow status value */
55416 {
55417 SK_U64 Status; /* Overflow status */
55418 SK_U32 RegVal;
55419@@ -4351,7 +5032,7 @@
55420 XM_IN32(IoC, Port, XM_RX_CNT_EV, &RegVal);
55421 Status |= (SK_U64)RegVal << 32;
55422 }
55423-
55424+
55425 if ((IStatus & XM_IS_TXC_OV) != 0) {
55426
55427 XM_IN32(IoC, Port, XM_TX_CNT_EV, &RegVal);
55428@@ -4378,8 +5059,8 @@
55429 * 1: something went wrong
55430 */
55431 int SkGmUpdateStats(
55432-SK_AC *pAC, /* adapter context */
55433-SK_IOC IoC, /* IO context */
55434+SK_AC *pAC, /* Adapter Context */
55435+SK_IOC IoC, /* I/O Context */
55436 unsigned int Port) /* Port Index (MAC_1 + n) */
55437 {
55438 return(0);
55439@@ -4400,24 +5081,27 @@
55440 * 1: something went wrong
55441 */
55442 int SkGmMacStatistic(
55443-SK_AC *pAC, /* adapter context */
55444-SK_IOC IoC, /* IO context */
55445+SK_AC *pAC, /* Adapter Context */
55446+SK_IOC IoC, /* I/O Context */
55447 unsigned int Port, /* Port Index (MAC_1 + n) */
55448 SK_U16 StatAddr, /* MIB counter base address */
55449-SK_U32 SK_FAR *pVal) /* ptr to return statistic value */
55450+SK_U32 SK_FAR *pVal) /* Pointer to return statistic value */
55451 {
55452
55453 if ((StatAddr < GM_RXF_UC_OK) || (StatAddr > GM_TXE_FIFO_UR)) {
55454-
55455+
55456 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E022, SKERR_HWI_E022MSG);
55457-
55458- SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
55459+
55460+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
55461 ("SkGmMacStat: wrong MIB counter 0x%04X\n", StatAddr));
55462 return(1);
55463 }
55464-
55465+
55466 GM_IN32(IoC, Port, StatAddr, pVal);
55467
55468+ /* dummy read after GM_IN32() */
55469+ SK_IN16(IoC, B0_RAP, &StatAddr);
55470+
55471 return(0);
55472 } /* SkGmMacStatistic */
55473
55474@@ -4434,8 +5118,8 @@
55475 * 1: something went wrong
55476 */
55477 int SkGmResetCounter(
55478-SK_AC *pAC, /* adapter context */
55479-SK_IOC IoC, /* IO context */
55480+SK_AC *pAC, /* Adapter Context */
55481+SK_IOC IoC, /* I/O Context */
55482 unsigned int Port) /* Port Index (MAC_1 + n) */
55483 {
55484 SK_U16 Reg; /* Phy Address Register */
55485@@ -4446,16 +5130,16 @@
55486
55487 /* set MIB Clear Counter Mode */
55488 GM_OUT16(IoC, Port, GM_PHY_ADDR, Reg | GM_PAR_MIB_CLR);
55489-
55490+
55491 /* read all MIB Counters with Clear Mode set */
55492 for (i = 0; i < GM_MIB_CNT_SIZE; i++) {
55493 /* the reset is performed only when the lower 16 bits are read */
55494 GM_IN16(IoC, Port, GM_MIB_CNT_BASE + 8*i, &Word);
55495 }
55496-
55497+
55498 /* clear MIB Clear Counter Mode */
55499 GM_OUT16(IoC, Port, GM_PHY_ADDR, Reg);
55500-
55501+
55502 return(0);
55503 } /* SkGmResetCounter */
55504
55505@@ -4469,48 +5153,62 @@
55506 * resulting counter overflow status is written to <pStatus>, whereas the
55507 * the following bit coding is used:
55508 * 63:56 - unused
55509- * 55:48 - TxRx interrupt register bit7:0
55510- * 32:47 - Rx interrupt register
55511+ * 55:48 - TxRx interrupt register bit 7:0
55512+ * 47:32 - Rx interrupt register
55513 * 31:24 - unused
55514- * 23:16 - TxRx interrupt register bit15:8
55515- * 15:0 - Tx interrupt register
55516+ * 23:16 - TxRx interrupt register bit 15:8
55517+ * 15: 0 - Tx interrupt register
55518 *
55519 * Returns:
55520 * 0: success
55521 * 1: something went wrong
55522 */
55523 int SkGmOverflowStatus(
55524-SK_AC *pAC, /* adapter context */
55525-SK_IOC IoC, /* IO context */
55526+SK_AC *pAC, /* Adapter Context */
55527+SK_IOC IoC, /* I/O Context */
55528 unsigned int Port, /* Port Index (MAC_1 + n) */
55529-SK_U16 IStatus, /* Interupt Status from MAC */
55530-SK_U64 SK_FAR *pStatus) /* ptr for return overflow status value */
55531+SK_U16 IStatus, /* Interrupt Status from MAC */
55532+SK_U64 SK_FAR *pStatus) /* Pointer for return overflow status value */
55533 {
55534- SK_U64 Status; /* Overflow status */
55535 SK_U16 RegVal;
55536+#ifndef SK_SLIM
55537+ SK_U64 Status; /* Overflow status */
55538
55539 Status = 0;
55540+#endif /* !SK_SLIM */
55541
55542 if ((IStatus & GM_IS_RX_CO_OV) != 0) {
55543 /* this register is self-clearing after read */
55544 GM_IN16(IoC, Port, GM_RX_IRQ_SRC, &RegVal);
55545+
55546+#ifndef SK_SLIM
55547 Status |= (SK_U64)RegVal << 32;
55548+#endif /* !SK_SLIM */
55549 }
55550-
55551+
55552 if ((IStatus & GM_IS_TX_CO_OV) != 0) {
55553 /* this register is self-clearing after read */
55554 GM_IN16(IoC, Port, GM_TX_IRQ_SRC, &RegVal);
55555+
55556+#ifndef SK_SLIM
55557 Status |= (SK_U64)RegVal;
55558+#endif /* !SK_SLIM */
55559 }
55560-
55561+
55562 /* this register is self-clearing after read */
55563 GM_IN16(IoC, Port, GM_TR_IRQ_SRC, &RegVal);
55564+
55565+#ifndef SK_SLIM
55566 /* Rx overflow interrupt register bits (LoByte)*/
55567 Status |= (SK_U64)((SK_U8)RegVal) << 48;
55568 /* Tx overflow interrupt register bits (HiByte)*/
55569 Status |= (SK_U64)(RegVal >> 8) << 16;
55570
55571 *pStatus = Status;
55572+#endif /* !SK_SLIM */
55573+
55574+ /* dummy read after GM_IN16() */
55575+ SK_IN16(IoC, B0_RAP, &RegVal);
55576
55577 return(0);
55578 } /* SkGmOverflowStatus */
55579@@ -4526,60 +5224,118 @@
55580 * gets the results if 'StartTest' is true
55581 *
55582 * NOTE: this test is meaningful only when link is down
55583- *
55584+ *
55585 * Returns:
55586 * 0: success
55587 * 1: no YUKON copper
55588 * 2: test in progress
55589 */
55590 int SkGmCableDiagStatus(
55591-SK_AC *pAC, /* adapter context */
55592-SK_IOC IoC, /* IO context */
55593+SK_AC *pAC, /* Adapter Context */
55594+SK_IOC IoC, /* I/O Context */
55595 int Port, /* Port Index (MAC_1 + n) */
55596 SK_BOOL StartTest) /* flag for start / get result */
55597 {
55598 int i;
55599+ int CableDiagOffs;
55600+ int MdiPairs;
55601+ SK_BOOL FastEthernet;
55602+ SK_BOOL Yukon2;
55603 SK_U16 RegVal;
55604 SK_GEPORT *pPrt;
55605
55606 pPrt = &pAC->GIni.GP[Port];
55607
55608 if (pPrt->PhyType != SK_PHY_MARV_COPPER) {
55609-
55610+
55611 return(1);
55612 }
55613
55614+ Yukon2 = pAC->GIni.GIChipId == CHIP_ID_YUKON_XL ||
55615+ pAC->GIni.GIChipId == CHIP_ID_YUKON_EC_U;
55616+
55617+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_FE) {
55618+
55619+ CableDiagOffs = PHY_MARV_FE_VCT_TX;
55620+ FastEthernet = SK_TRUE;
55621+ MdiPairs = 2;
55622+ }
55623+ else {
55624+ CableDiagOffs = Yukon2 ? PHY_MARV_PHY_CTRL : PHY_MARV_CABLE_DIAG;
55625+ FastEthernet = SK_FALSE;
55626+ MdiPairs = 4;
55627+ }
55628+
55629 if (StartTest) {
55630+
55631+ /* set to RESET to avoid PortCheckUp */
55632+ pPrt->PState = SK_PRT_RESET;
55633+
55634 /* only start the cable test */
55635- if ((pPrt->PhyId1 & PHY_I1_REV_MSK) < 4) {
55636- /* apply TDR workaround from Marvell */
55637- SkGmPhyWrite(pAC, IoC, Port, 29, 0x001e);
55638-
55639- SkGmPhyWrite(pAC, IoC, Port, 30, 0xcc00);
55640- SkGmPhyWrite(pAC, IoC, Port, 30, 0xc800);
55641- SkGmPhyWrite(pAC, IoC, Port, 30, 0xc400);
55642- SkGmPhyWrite(pAC, IoC, Port, 30, 0xc000);
55643- SkGmPhyWrite(pAC, IoC, Port, 30, 0xc100);
55644+ if (!FastEthernet) {
55645+
55646+ if ((((pPrt->PhyId1 & PHY_I1_MOD_NUM) >> 4) == 2) &&
55647+ ((pPrt->PhyId1 & PHY_I1_REV_MSK) < 4)) {
55648+ /* apply TDR workaround for model 2, rev. < 4 */
55649+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_ADDR, 0x001e);
55650+
55651+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xcc00);
55652+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xc800);
55653+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xc400);
55654+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xc000);
55655+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_PAGE_DATA, 0xc100);
55656+ }
55657+
55658+#ifdef YUKON_DBG
55659+ if (pAC->GIni.GIChipId == CHIP_ID_YUKON_EC) {
55660+ /* set address to 1 for page 1 */
55661+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 1);
55662+
55663+ /* disable waiting period */
55664+ SkGmPhyWrite(pAC, IoC, Port, CableDiagOffs,
55665+ PHY_M_CABD_DIS_WAIT);
55666+ }
55667+#endif
55668+ if (Yukon2) {
55669+ /* set address to 5 for page 5 */
55670+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 5);
55671+
55672+#ifdef YUKON_DBG
55673+ /* disable waiting period */
55674+ SkGmPhyWrite(pAC, IoC, Port, CableDiagOffs + 1,
55675+ PHY_M_CABD_DIS_WAIT);
55676+#endif
55677+ }
55678+ else {
55679+ /* set address to 0 for MDI[0] (Page 0) */
55680+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0);
55681+ }
55682 }
55683+ else {
55684+ RegVal = PHY_CT_RESET | PHY_CT_SP100;
55685
55686- /* set address to 0 for MDI[0] */
55687- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, 0);
55688+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL, RegVal);
55689
55690- /* Read Cable Diagnostic Reg */
55691- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CABLE_DIAG, &RegVal);
55692+#ifdef xYUKON_DBG
55693+ SkGmPhyRead(pAC, IoC, Port, PHY_MARV_FE_SPEC_2, &RegVal);
55694+ /* disable waiting period */
55695+ RegVal |= PHY_M_FESC_DIS_WAIT;
55696+
55697+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_FE_SPEC_2, RegVal);
55698+#endif
55699+ }
55700
55701 /* start Cable Diagnostic Test */
55702- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CABLE_DIAG,
55703- (SK_U16)(RegVal | PHY_M_CABD_ENA_TEST));
55704-
55705+ SkGmPhyWrite(pAC, IoC, Port, CableDiagOffs, PHY_M_CABD_ENA_TEST);
55706+
55707 return(0);
55708 }
55709-
55710+
55711 /* Read Cable Diagnostic Reg */
55712- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CABLE_DIAG, &RegVal);
55713+ SkGmPhyRead(pAC, IoC, Port, CableDiagOffs, &RegVal);
55714
55715 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
55716- ("PHY Cable Diag.=0x%04X\n", RegVal));
55717+ ("PHY Cable Diag. = 0x%04X\n", RegVal));
55718
55719 if ((RegVal & PHY_M_CABD_ENA_TEST) != 0) {
55720 /* test is running */
55721@@ -4587,16 +5343,24 @@
55722 }
55723
55724 /* get the test results */
55725- for (i = 0; i < 4; i++) {
55726- /* set address to i for MDI[i] */
55727- SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, (SK_U16)i);
55728+ for (i = 0; i < MdiPairs; i++) {
55729+
55730+ if (!FastEthernet && !Yukon2) {
55731+ /* set address to i for MDI[i] */
55732+ SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_ADR, (SK_U16)i);
55733+ }
55734
55735 /* get Cable Diagnostic values */
55736- SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CABLE_DIAG, &RegVal);
55737+ SkGmPhyRead(pAC, IoC, Port, CableDiagOffs, &RegVal);
55738
55739 pPrt->PMdiPairLen[i] = (SK_U8)(RegVal & PHY_M_CABD_DIST_MSK);
55740
55741 pPrt->PMdiPairSts[i] = (SK_U8)((RegVal & PHY_M_CABD_STAT_MSK) >> 13);
55742+
55743+ if (FastEthernet || Yukon2) {
55744+ /* get next register */
55745+ CableDiagOffs++;
55746+ }
55747 }
55748
55749 return(0);
55750@@ -4605,3 +5369,4 @@
55751 #endif /* YUKON */
55752
55753 /* End of file */
55754+
55755diff -ruN linux/drivers/net/sk98lin/sky2.c linux-new/drivers/net/sk98lin/sky2.c
55756--- linux/drivers/net/sk98lin/sky2.c 1970-01-01 01:00:00.000000000 +0100
55757+++ linux-new/drivers/net/sk98lin/sky2.c 2006-01-18 14:37:24.000000000 +0100
615eba13 55758@@ -0,0 +1,2718 @@
5902d8ee 55759+/******************************************************************************
55760+ *
55761+ * Name: sky2.c
55762+ * Project: Yukon2 specific functions and implementations
55763+ * Version: $Revision$
55764+ * Date: $Date$
55765+ * Purpose: The main driver source module
55766+ *
55767+ *****************************************************************************/
55768+
55769+/******************************************************************************
55770+ *
55771+ * (C)Copyright 1998-2002 SysKonnect GmbH.
55772+ * (C)Copyright 2002-2005 Marvell.
55773+ *
55774+ * Driver for Marvell Yukon/2 chipset and SysKonnect Gigabit Ethernet
55775+ * Server Adapters.
55776+ *
55777+ * Author: Ralph Roesler (rroesler@syskonnect.de)
55778+ * Mirko Lindner (mlindner@syskonnect.de)
55779+ *
55780+ * Address all question to: linux@syskonnect.de
55781+ *
55782+ * This program is free software; you can redistribute it and/or modify
55783+ * it under the terms of the GNU General Public License as published by
55784+ * the Free Software Foundation; either version 2 of the License, or
55785+ * (at your option) any later version.
55786+ *
55787+ * The information in this file is provided "AS IS" without warranty.
55788+ *
55789+ *****************************************************************************/
55790+
55791+#include "h/skdrv1st.h"
55792+#include "h/skdrv2nd.h"
615eba13 55793+#include <linux/ip.h>
5902d8ee 55794+#include <linux/tcp.h>
55795+
55796+/******************************************************************************
55797+ *
55798+ * Local Function Prototypes
55799+ *
55800+ *****************************************************************************/
55801+
55802+static void InitPacketQueues(SK_AC *pAC,int Port);
55803+static void GiveTxBufferToHw(SK_AC *pAC,SK_IOC IoC,int Port);
55804+static void GiveRxBufferToHw(SK_AC *pAC,SK_IOC IoC,int Port,SK_PACKET *pPacket);
55805+static SK_BOOL HandleReceives(SK_AC *pAC,int Port,SK_U16 Len,SK_U32 FrameStatus,SK_U16 Tcp1,SK_U16 Tcp2,SK_U32 Tist,SK_U16 Vlan);
55806+static void CheckForSendComplete(SK_AC *pAC,SK_IOC IoC,int Port,SK_PKT_QUEUE *pPQ,SK_LE_TABLE *pLETab,unsigned int Done);
55807+static void UnmapAndFreeTxPktBuffer(SK_AC *pAC,SK_PACKET *pSkPacket,int TxPort);
55808+static SK_BOOL AllocateAndInitLETables(SK_AC *pAC);
55809+static SK_BOOL AllocatePacketBuffersYukon2(SK_AC *pAC);
55810+static void FreeLETables(SK_AC *pAC);
55811+static void FreePacketBuffers(SK_AC *pAC);
55812+static SK_BOOL AllocAndMapRxBuffer(SK_AC *pAC,SK_PACKET *pSkPacket,int Port);
55813+#ifdef CONFIG_SK98LIN_NAPI
55814+static SK_BOOL HandleStatusLEs(SK_AC *pAC,int *WorkDone,int WorkToDo);
55815+#else
55816+static SK_BOOL HandleStatusLEs(SK_AC *pAC);
55817+#endif
55818+
55819+extern void SkGeCheckTimer (DEV_NET *pNet);
55820+extern void SkLocalEventQueue( SK_AC *pAC,
55821+ SK_U32 Class,
55822+ SK_U32 Event,
55823+ SK_U32 Param1,
55824+ SK_U32 Param2,
55825+ SK_BOOL Flag);
55826+extern void SkLocalEventQueue64( SK_AC *pAC,
55827+ SK_U32 Class,
55828+ SK_U32 Event,
55829+ SK_U64 Param,
55830+ SK_BOOL Flag);
55831+
55832+/******************************************************************************
55833+ *
55834+ * Local Variables
55835+ *
55836+ *****************************************************************************/
55837+
55838+#define MAX_NBR_RX_BUFFERS_IN_HW 0x15
55839+static SK_U8 NbrRxBuffersInHW;
55840+#define FLUSH_OPC(le)
55841+
55842+/******************************************************************************
55843+ *
55844+ * Global Functions
55845+ *
55846+ *****************************************************************************/
55847+
55848+int SkY2Xmit( struct sk_buff *skb, struct SK_NET_DEVICE *dev);
55849+void FillReceiveTableYukon2(SK_AC *pAC,SK_IOC IoC,int Port);
55850+
55851+/*****************************************************************************
55852+ *
55853+ * SkY2RestartStatusUnit - restarts teh status unit
55854+ *
55855+ * Description:
55856+ * Reenables the status unit after any De-Init (e.g. when altering
55857+ * the sie of the MTU via 'ifconfig a.b.c.d mtu xxx')
55858+ *
55859+ * Returns: N/A
55860+ */
55861+void SkY2RestartStatusUnit(
55862+SK_AC *pAC) /* pointer to adapter control context */
55863+{
55864+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
55865+ ("==> SkY2RestartStatusUnit\n"));
55866+
55867+ /*
55868+ ** It might be that the TX timer is not started. Therefore
55869+ ** it is initialized here -> to be more investigated!
55870+ */
55871+ SK_OUT32(pAC->IoBase, STAT_TX_TIMER_INI, HW_MS_TO_TICKS(pAC,10));
55872+
55873+ pAC->StatusLETable.Done = 0;
55874+ pAC->StatusLETable.Put = 0;
55875+ pAC->StatusLETable.HwPut = 0;
55876+ SkGeY2InitStatBmu(pAC, pAC->IoBase, &pAC->StatusLETable);
55877+
55878+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
55879+ ("<== SkY2RestartStatusUnit\n"));
55880+}
55881+
55882+/*****************************************************************************
55883+ *
55884+ * SkY2RlmtSend - sends out a single RLMT notification
55885+ *
55886+ * Description:
55887+ * This function sends out an RLMT frame
55888+ *
55889+ * Returns:
55890+ * > 0 - on succes: the number of bytes in the message
55891+ * = 0 - on resource shortage: this frame sent or dropped, now
55892+ * the ring is full ( -> set tbusy)
55893+ * < 0 - on failure: other problems ( -> return failure to upper layers)
55894+ */
55895+int SkY2RlmtSend (
55896+SK_AC *pAC, /* pointer to adapter control context */
55897+int PortNr, /* index of port the packet(s) shall be send to */
55898+struct sk_buff *pMessage) /* pointer to send-message */
55899+{
55900+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
55901+ ("=== SkY2RlmtSend\n"));
55902+#if 0
55903+ return -1; // temporarily do not send out RLMT frames
55904+#endif
55905+ skb_shinfo(pMessage)->nr_frags = (2*MAX_SKB_FRAGS) + PortNr;
55906+ return(SkY2Xmit(pMessage, pAC->dev[PortNr])); // SkY2Xmit needs device
55907+}
55908+
55909+/*****************************************************************************
55910+ *
55911+ * SkY2AllocateResources - Allocates all required resources for Yukon2
55912+ *
55913+ * Description:
55914+ * This function allocates all memory needed for the Yukon2.
55915+ * It maps also RX buffers to the LETables and initializes the
55916+ * status list element table.
55917+ *
55918+ * Returns:
55919+ * SK_TRUE, if all resources could be allocated and setup succeeded
55920+ * SK_FALSE, if an error
55921+ */
55922+SK_BOOL SkY2AllocateResources (
55923+SK_AC *pAC) /* pointer to adapter control context */
55924+{
55925+ int CurrMac;
55926+
55927+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
55928+ ("==> SkY2AllocateResources\n"));
55929+
55930+ /*
55931+ ** Initialize the packet queue variables first
55932+ */
55933+ for (CurrMac = 0; CurrMac < pAC->GIni.GIMacsFound; CurrMac++) {
55934+ InitPacketQueues(pAC, CurrMac);
55935+ }
55936+
55937+ /*
55938+ ** Get sufficient memory for the LETables
55939+ */
55940+ if (!AllocateAndInitLETables(pAC)) {
55941+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
55942+ SK_DBGCAT_INIT | SK_DBGCAT_DRV_ERROR,
55943+ ("No memory for LETable.\n"));
55944+ return(SK_FALSE);
55945+ }
55946+
55947+ /*
55948+ ** Allocate and intialize memory for both RX and TX
55949+ ** packet and fragment buffers. On an error, free
55950+ ** previously allocated LETable memory and quit.
55951+ */
55952+ if (!AllocatePacketBuffersYukon2(pAC)) {
55953+ FreeLETables(pAC);
55954+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
55955+ SK_DBGCAT_INIT | SK_DBGCAT_DRV_ERROR,
55956+ ("No memory for Packetbuffers.\n"));
55957+ return(SK_FALSE);
55958+ }
55959+
55960+ /*
55961+ ** Rx and Tx LE tables will be initialized in SkGeOpen()
55962+ **
55963+ ** It might be that the TX timer is not started. Therefore
55964+ ** it is initialized here -> to be more investigated!
55965+ */
55966+ SK_OUT32(pAC->IoBase, STAT_TX_TIMER_INI, HW_MS_TO_TICKS(pAC,10));
55967+ SkGeY2InitStatBmu(pAC, pAC->IoBase, &pAC->StatusLETable);
55968+
55969+ pAC->MaxUnusedRxLeWorking = MAX_UNUSED_RX_LE_WORKING;
55970+
55971+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
55972+ ("<== SkY2AllocateResources\n"));
55973+
55974+ return (SK_TRUE);
55975+}
55976+
55977+/*****************************************************************************
55978+ *
55979+ * SkY2FreeResources - Frees previously allocated resources of Yukon2
55980+ *
55981+ * Description:
55982+ * This function frees all previously allocated memory of the Yukon2.
55983+ *
55984+ * Returns: N/A
55985+ */
55986+void SkY2FreeResources (
55987+SK_AC *pAC) /* pointer to adapter control context */
55988+{
55989+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
55990+ ("==> SkY2FreeResources\n"));
55991+
55992+ FreeLETables(pAC);
55993+ FreePacketBuffers(pAC);
55994+
55995+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
55996+ ("<== SkY2FreeResources\n"));
55997+}
55998+
55999+/*****************************************************************************
56000+ *
56001+ * SkY2AllocateRxBuffers - Allocates the receive buffers for a port
56002+ *
56003+ * Description:
56004+ * This function allocated all the RX buffers of the Yukon2.
56005+ *
56006+ * Returns: N/A
56007+ */
56008+void SkY2AllocateRxBuffers (
56009+SK_AC *pAC, /* pointer to adapter control context */
56010+SK_IOC IoC, /* I/O control context */
56011+int Port) /* port index of RX */
56012+{
56013+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
56014+ ("==> SkY2AllocateRxBuffers (Port %c)\n", Port));
56015+
56016+ FillReceiveTableYukon2(pAC, IoC, Port);
56017+
56018+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
56019+ ("<== SkY2AllocateRxBuffers\n"));
56020+}
56021+
56022+/*****************************************************************************
56023+ *
56024+ * SkY2FreeRxBuffers - Free's all allocates RX buffers of
56025+ *
56026+ * Description:
56027+ * This function frees all RX buffers of the Yukon2 for a single port
56028+ *
56029+ * Returns: N/A
56030+ */
56031+void SkY2FreeRxBuffers (
56032+SK_AC *pAC, /* pointer to adapter control context */
56033+SK_IOC IoC, /* I/O control context */
56034+int Port) /* port index of RX */
56035+{
56036+ SK_PACKET *pSkPacket;
56037+ unsigned long Flags; /* for POP/PUSH macros */
56038+
56039+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
56040+ ("==> SkY2FreeRxBuffers (Port %c)\n", Port));
56041+
56042+ if (pAC->RxPort[Port].ReceivePacketTable != NULL) {
56043+ POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_working, pSkPacket);
56044+ while (pSkPacket != NULL) {
56045+ if ((pSkPacket->pFrag) != NULL) {
56046+ pci_unmap_page(pAC->PciDev,
56047+ (dma_addr_t) pSkPacket->pFrag->pPhys,
56048+ pSkPacket->pFrag->FragLen - 2,
56049+ PCI_DMA_FROMDEVICE);
56050+
56051+ /* wipe out any rubbish data that may interfere */
56052+ skb_shinfo(pSkPacket->pMBuf)->nr_frags = 0;
56053+ skb_shinfo(pSkPacket->pMBuf)->frag_list = NULL;
56054+ DEV_KFREE_SKB_ANY(pSkPacket->pMBuf);
56055+ pSkPacket->pMBuf = NULL;
56056+ pSkPacket->pFrag->pPhys = (SK_U64) 0;
56057+ pSkPacket->pFrag->pVirt = NULL;
56058+ }
56059+ PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pSkPacket);
56060+ POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_working, pSkPacket);
56061+ }
56062+ }
56063+
56064+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
56065+ ("<== SkY2FreeRxBuffers\n"));
56066+}
56067+
56068+/*****************************************************************************
56069+ *
56070+ * SkY2FreeTxBuffers - Free's any currently maintained Tx buffer
56071+ *
56072+ * Description:
56073+ * This function frees the TX buffers of the Yukon2 for a single port
56074+ * which might be in use by a transmit action
56075+ *
56076+ * Returns: N/A
56077+ */
56078+void SkY2FreeTxBuffers (
56079+SK_AC *pAC, /* pointer to adapter control context */
56080+SK_IOC IoC, /* I/O control context */
56081+int Port) /* port index of TX */
56082+{
56083+ SK_PACKET *pSkPacket;
56084+ SK_FRAG *pSkFrag;
56085+ unsigned long Flags;
56086+
56087+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
56088+ ("==> SkY2FreeTxBuffers (Port %c)\n", Port));
56089+
56090+ if (pAC->TxPort[Port][0].TransmitPacketTable != NULL) {
56091+ POP_FIRST_PKT_FROM_QUEUE(&pAC->TxPort[Port][0].TxAQ_working, pSkPacket);
56092+ while (pSkPacket != NULL) {
56093+ if ((pSkFrag = pSkPacket->pFrag) != NULL) {
56094+ UnmapAndFreeTxPktBuffer(pAC, pSkPacket, Port);
56095+ }
56096+ PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->TxPort[Port][0].TxQ_free, pSkPacket);
56097+ POP_FIRST_PKT_FROM_QUEUE(&pAC->TxPort[Port][0].TxAQ_working, pSkPacket);
56098+ }
56099+#if USE_SYNC_TX_QUEUE
56100+ POP_FIRST_PKT_FROM_QUEUE(&pAC->TxPort[Port][0].TxSQ_working, pSkPacket);
56101+ while (pSkPacket != NULL) {
56102+ if ((pSkFrag = pSkPacket->pFrag) != NULL) {
56103+ UnmapAndFreeTxPktBuffer(pAC, pSkPacket, Port);
56104+ }
56105+ PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->TxPort[Port][0].TxQ_free, pSkPacket);
56106+ POP_FIRST_PKT_FROM_QUEUE(&pAC->TxPort[Port][0].TxSQ_working, pSkPacket);
56107+ }
56108+#endif
56109+ }
56110+
56111+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
56112+ ("<== SkY2FreeTxBuffers\n"));
56113+}
56114+
56115+/*****************************************************************************
56116+ *
56117+ * SkY2Isr - handle a receive IRQ for all yukon2 cards
56118+ *
56119+ * Description:
56120+ * This function is called when a receive IRQ is set. (only for yukon2)
56121+ * HandleReceives does the deferred processing of all outstanding
56122+ * interrupt operations.
56123+ *
56124+ * Returns: N/A
56125+ */
56126+SkIsrRetVar SkY2Isr (
56127+int irq, /* the irq we have received (might be shared!) */
56128+void *dev_id, /* current device id */
56129+struct pt_regs *ptregs) /* not used by our driver */
56130+{
56131+ struct SK_NET_DEVICE *dev = (struct SK_NET_DEVICE *)dev_id;
56132+ DEV_NET *pNet = (DEV_NET*) dev->priv;
56133+ SK_AC *pAC = pNet->pAC;
56134+ SK_U32 IntSrc;
56135+ unsigned long Flags;
56136+#ifndef CONFIG_SK98LIN_NAPI
56137+ SK_BOOL handledStatLE = SK_FALSE;
56138+#else
56139+ SK_BOOL SetIntMask = SK_FALSE;
56140+#endif
56141+
56142+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
56143+ ("==> SkY2Isr\n"));
56144+
56145+ SK_IN32(pAC->IoBase, B0_Y2_SP_ISRC2, &IntSrc);
56146+
56147+ if ((IntSrc == 0) && (!pNet->NetConsoleMode)){
56148+ SK_OUT32(pAC->IoBase, B0_Y2_SP_ICR, 2);
56149+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
56150+ ("No Interrupt\n ==> SkY2Isr\n"));
56151+ return SkIsrRetNone;
56152+
56153+ }
56154+
56155+#ifdef Y2_RECOVERY
56156+ if (pNet->InRecover) {
56157+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
56158+ ("Already in recover\n ==> SkY2Isr\n"));
56159+ SK_OUT32(pAC->IoBase, B0_Y2_SP_ICR, 2);
56160+ return SkIsrRetNone;
56161+ }
56162+#endif
56163+
56164+#ifdef CONFIG_SK98LIN_NAPI
56165+ if (netif_rx_schedule_prep(pAC->dev[0])) {
56166+ pAC->GIni.GIValIrqMask &= ~(Y2_IS_STAT_BMU);
56167+ SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
56168+ SetIntMask = SK_TRUE;
56169+ __netif_rx_schedule(pAC->dev[0]);
56170+ }
56171+
56172+ if (netif_rx_schedule_prep(pAC->dev[1])) {
56173+ if (!SetIntMask) {
56174+ pAC->GIni.GIValIrqMask &= ~(Y2_IS_STAT_BMU);
56175+ SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
56176+ }
56177+ __netif_rx_schedule(pAC->dev[1]);
56178+ }
56179+#else
56180+ handledStatLE = HandleStatusLEs(pAC);
56181+#endif
56182+
56183+ /*
56184+ ** Check for Special Interrupts
56185+ */
56186+ if ((IntSrc & ~Y2_IS_STAT_BMU) || pAC->CheckQueue || pNet->TimerExpired) {
56187+ pAC->CheckQueue = SK_FALSE;
56188+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
56189+ SkGeSirqIsr(pAC, pAC->IoBase, IntSrc);
56190+ SkEventDispatcher(pAC, pAC->IoBase);
56191+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
56192+ }
56193+
56194+ /* Speed enhancement for a2 chipsets */
56195+ if (HW_FEATURE(pAC, HWF_WA_DEV_42)) {
56196+ spin_lock_irqsave(&pAC->SetPutIndexLock, Flags);
56197+ SkGeY2SetPutIndex(pAC, pAC->IoBase, Y2_PREF_Q_ADDR(Q_XA1,0), &pAC->TxPort[0][0].TxALET);
56198+ SkGeY2SetPutIndex(pAC, pAC->IoBase, Y2_PREF_Q_ADDR(Q_R1,0), &pAC->RxPort[0].RxLET);
56199+ spin_unlock_irqrestore(&pAC->SetPutIndexLock, Flags);
56200+ }
56201+
56202+ /*
56203+ ** Reenable interrupts and signal end of ISR
56204+ */
56205+ SK_OUT32(pAC->IoBase, B0_Y2_SP_ICR, 2);
56206+
56207+ /*
56208+ ** Stop and restart TX timer in case a Status LE was handled
56209+ */
56210+#ifndef CONFIG_SK98LIN_NAPI
56211+ if ((HW_FEATURE(pAC, HWF_WA_DEV_43_418)) && (handledStatLE)) {
56212+ SK_OUT8(pAC->IoBase, STAT_TX_TIMER_CTRL, TIM_STOP);
56213+ SK_OUT8(pAC->IoBase, STAT_TX_TIMER_CTRL, TIM_START);
56214+ }
56215+#endif
56216+
56217+ if (!(IS_Q_EMPTY(&(pAC->TxPort[0][TX_PRIO_LOW].TxAQ_waiting)))) {
56218+ GiveTxBufferToHw(pAC, pAC->IoBase, 0);
56219+ }
56220+ if (!(IS_Q_EMPTY(&(pAC->TxPort[1][TX_PRIO_LOW].TxAQ_waiting)))) {
56221+ GiveTxBufferToHw(pAC, pAC->IoBase, 1);
56222+ }
56223+
56224+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
56225+ ("<== SkY2Isr\n"));
56226+
56227+ return SkIsrRetHandled;
56228+} /* SkY2Isr */
56229+
56230+/*****************************************************************************
56231+ *
56232+ * SkY2Xmit - Linux frame transmit function for Yukon2
56233+ *
56234+ * Description:
56235+ * The system calls this function to send frames onto the wire.
56236+ * It puts the frame in the tx descriptor ring. If the ring is
56237+ * full then, the 'tbusy' flag is set.
56238+ *
56239+ * Returns:
56240+ * 0, if everything is ok
56241+ * !=0, on error
56242+ *
56243+ * WARNING:
56244+ * returning 1 in 'tbusy' case caused system crashes (double
56245+ * allocated skb's) !!!
56246+ */
56247+int SkY2Xmit(
56248+struct sk_buff *skb, /* socket buffer to be sent */
56249+struct SK_NET_DEVICE *dev) /* via which device? */
56250+{
56251+ DEV_NET *pNet = (DEV_NET*) dev->priv;
56252+ SK_AC *pAC = pNet->pAC;
56253+ SK_U8 FragIdx = 0;
56254+ SK_PACKET *pSkPacket;
56255+ SK_FRAG *PrevFrag;
56256+ SK_FRAG *CurrFrag;
56257+ SK_PKT_QUEUE *pWorkQueue; /* corresponding TX queue */
56258+ SK_PKT_QUEUE *pWaitQueue;
56259+ SK_PKT_QUEUE *pFreeQueue;
56260+ SK_LE_TABLE *pLETab; /* corresponding LETable */
56261+ skb_frag_t *sk_frag;
56262+ SK_U64 PhysAddr;
56263+ unsigned long Flags;
56264+ unsigned int Port;
56265+ int CurrFragCtr;
56266+
56267+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
56268+ ("==> SkY2Xmit\n"));
56269+
56270+ /*
56271+ ** Get port and return if no free packet is available
56272+ */
56273+ if (skb_shinfo(skb)->nr_frags > MAX_SKB_FRAGS) {
56274+ Port = skb_shinfo(skb)->nr_frags - (2*MAX_SKB_FRAGS);
56275+ skb_shinfo(skb)->nr_frags = 0;
56276+ } else {
56277+ Port = (pAC->RlmtNets == 2) ? pNet->PortNr : pAC->ActivePort;
56278+ }
56279+
56280+ if (IS_Q_EMPTY(&(pAC->TxPort[Port][TX_PRIO_LOW].TxQ_free))) {
56281+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
56282+ SK_DBGCAT_DRV_TX_PROGRESS | SK_DBGCAT_DRV_ERROR,
56283+ ("Not free packets available for send\n"));
56284+ return 1; /* zero bytes sent! */
56285+ }
56286+
56287+ /*
56288+ ** Put any new packet to be sent in the waiting queue and
56289+ ** handle also any possible fragment of that packet.
56290+ */
56291+ pWorkQueue = &(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_working);
56292+ pWaitQueue = &(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting);
56293+ pFreeQueue = &(pAC->TxPort[Port][TX_PRIO_LOW].TxQ_free);
56294+ pLETab = &(pAC->TxPort[Port][TX_PRIO_LOW].TxALET);
56295+
56296+ /*
56297+ ** Normal send operations require only one fragment, because
56298+ ** only one sk_buff data area is passed.
56299+ ** In contradiction to this, scatter-gather (zerocopy) send
56300+ ** operations might pass one or more additional fragments
56301+ ** where each fragment needs a separate fragment info packet.
56302+ */
56303+ if (((skb_shinfo(skb)->nr_frags + 1) * MAX_FRAG_OVERHEAD) >
56304+ NUM_FREE_LE_IN_TABLE(pLETab)) {
56305+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
56306+ SK_DBGCAT_DRV_TX_PROGRESS | SK_DBGCAT_DRV_ERROR,
56307+ ("Not enough LE available for send\n"));
56308+ return 1; /* zero bytes sent! */
56309+ }
56310+
56311+ if ((skb_shinfo(skb)->nr_frags + 1) > MAX_NUM_FRAGS) {
56312+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
56313+ SK_DBGCAT_DRV_TX_PROGRESS | SK_DBGCAT_DRV_ERROR,
56314+ ("Not even one fragment available for send\n"));
56315+ return 1; /* zero bytes sent! */
56316+ }
56317+
56318+ /*
56319+ ** Get first packet from free packet queue
56320+ */
56321+ POP_FIRST_PKT_FROM_QUEUE(pFreeQueue, pSkPacket);
56322+ if(pSkPacket == NULL) {
56323+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
56324+ SK_DBGCAT_DRV_TX_PROGRESS | SK_DBGCAT_DRV_ERROR,
56325+ ("Could not obtain free packet used for xmit\n"));
56326+ return 1; /* zero bytes sent! */
56327+ }
56328+
56329+ pSkPacket->pFrag = &(pSkPacket->FragArray[FragIdx]);
56330+
56331+ /*
56332+ ** map the sk_buff to be available for the adapter
56333+ */
56334+ PhysAddr = (SK_U64) pci_map_page(pAC->PciDev,
56335+ virt_to_page(skb->data),
56336+ ((unsigned long) skb->data & ~PAGE_MASK),
56337+ skb_headlen(skb),
56338+ PCI_DMA_TODEVICE);
56339+ pSkPacket->pMBuf = skb;
56340+ pSkPacket->pFrag->pPhys = PhysAddr;
56341+ pSkPacket->pFrag->FragLen = skb_headlen(skb);
56342+ pSkPacket->pFrag->pNext = NULL; /* initial has no next default */
56343+ pSkPacket->NumFrags = skb_shinfo(skb)->nr_frags + 1;
56344+
56345+ PrevFrag = pSkPacket->pFrag;
56346+
56347+ /*
56348+ ** Each scatter-gather fragment need to be mapped...
56349+ */
56350+ for ( CurrFragCtr = 0;
56351+ CurrFragCtr < skb_shinfo(skb)->nr_frags;
56352+ CurrFragCtr++) {
56353+ FragIdx++;
56354+ sk_frag = &skb_shinfo(skb)->frags[CurrFragCtr];
56355+ CurrFrag = &(pSkPacket->FragArray[FragIdx]);
56356+
56357+ /*
56358+ ** map the sk_buff to be available for the adapter
56359+ */
56360+ PhysAddr = (SK_U64) pci_map_page(pAC->PciDev,
56361+ sk_frag->page,
56362+ sk_frag->page_offset,
56363+ sk_frag->size,
56364+ PCI_DMA_TODEVICE);
56365+
56366+ CurrFrag->pPhys = PhysAddr;
56367+ CurrFrag->FragLen = sk_frag->size;
56368+ CurrFrag->pNext = NULL;
56369+
56370+ /*
56371+ ** Add the new fragment to the list of fragments
56372+ */
56373+ PrevFrag->pNext = CurrFrag;
56374+ PrevFrag = CurrFrag;
56375+ }
56376+
56377+ /*
56378+ ** Add packet to waiting packets queue
56379+ */
56380+ PUSH_PKT_AS_LAST_IN_QUEUE(pWaitQueue, pSkPacket);
56381+ GiveTxBufferToHw(pAC, pAC->IoBase, Port);
56382+ dev->trans_start = jiffies;
56383+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
56384+ ("<== SkY2Xmit(return 0)\n"));
56385+ return (0);
56386+} /* SkY2Xmit */
56387+
56388+#ifdef CONFIG_SK98LIN_NAPI
56389+/*****************************************************************************
56390+ *
56391+ * SkY2Poll - NAPI Rx polling callback for Yukon2 chipsets
56392+ *
56393+ * Description:
56394+ * Called by the Linux system in case NAPI polling is activated
56395+ *
56396+ * Returns
56397+ * The number of work data still to be handled
56398+ *
56399+ * Notes
56400+ * The slowpath lock needs to be set because HW accesses may
56401+ * interfere with slowpath events (e.g. TWSI)
56402+ */
56403+int SkY2Poll(
56404+struct net_device *dev, /* device that needs to be polled */
56405+int *budget) /* how many budget do we have? */
56406+{
56407+ SK_AC *pAC = ((DEV_NET*)(dev->priv))->pAC;
56408+ int WorkToDo = min(*budget, dev->quota);
56409+ int WorkDone = 0;
56410+ SK_BOOL handledStatLE = SK_FALSE;
56411+ unsigned long Flags;
56412+
56413+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
56414+ handledStatLE = HandleStatusLEs(pAC, &WorkDone, WorkToDo);
56415+
56416+ *budget -= WorkDone;
56417+ dev->quota -= WorkDone;
56418+
56419+ if(WorkDone < WorkToDo) {
56420+ netif_rx_complete(dev);
56421+ pAC->GIni.GIValIrqMask |= (Y2_IS_STAT_BMU);
56422+ SK_OUT32(pAC->IoBase, B0_IMSK, pAC->GIni.GIValIrqMask);
56423+ if ((HW_FEATURE(pAC, HWF_WA_DEV_43_418)) && (handledStatLE)) {
56424+ SK_OUT8(pAC->IoBase, STAT_TX_TIMER_CTRL, TIM_STOP);
56425+ SK_OUT8(pAC->IoBase, STAT_TX_TIMER_CTRL, TIM_START);
56426+ }
56427+ }
56428+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
56429+ return (WorkDone >= WorkToDo);
56430+} /* SkY2Poll */
56431+#endif
56432+
56433+/******************************************************************************
56434+ *
56435+ * SkY2PortStop - stop a port on Yukon2
56436+ *
56437+ * Description:
56438+ * This function stops a port of the Yukon2 chip. This stop
56439+ * stop needs to be performed in a specific order:
56440+ *
56441+ * a) Stop the Prefetch unit
56442+ * b) Stop the Port (MAC, PHY etc.)
56443+ *
56444+ * Returns: N/A
56445+ */
56446+void SkY2PortStop(
56447+SK_AC *pAC, /* adapter control context */
56448+SK_IOC IoC, /* I/O control context (address of adapter registers) */
56449+int Port, /* port to stop (MAC_1 + n) */
56450+int Dir, /* StopDirection (SK_STOP_RX, SK_STOP_TX, SK_STOP_ALL) */
56451+int RstMode) /* Reset Mode (SK_SOFT_RST, SK_HARD_RST) */
56452+{
56453+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
56454+ ("==> SkY2PortStop (Port %c)\n", 'A' + Port));
56455+
56456+ /*
56457+ ** Stop the HW
56458+ */
56459+ SkGeStopPort(pAC, IoC, Port, Dir, RstMode);
56460+
56461+ /*
56462+ ** Move any TX packet from work queues into the free queue again
56463+ ** and initialize the TX LETable variables
56464+ */
56465+ SkY2FreeTxBuffers(pAC, pAC->IoBase, Port);
56466+ pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Bmu.RxTx.TcpWp = 0;
56467+ pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Bmu.RxTx.MssValue = 0;
56468+ pAC->TxPort[Port][TX_PRIO_LOW].TxALET.BufHighAddr = 0;
56469+ pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Done = 0;
56470+ pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Put = 0;
56471+ // pAC->GIni.GP[Port].PState = SK_PRT_STOP;
56472+
56473+ /*
56474+ ** Move any RX packet from work queue into the waiting queue
56475+ ** and initialize the RX LETable variables
56476+ */
56477+ SkY2FreeRxBuffers(pAC, pAC->IoBase, Port);
56478+ pAC->RxPort[Port].RxLET.BufHighAddr = 0;
56479+
56480+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
56481+ ("<== SkY2PortStop()\n"));
56482+}
56483+
56484+/******************************************************************************
56485+ *
56486+ * SkY2PortStart - start a port on Yukon2
56487+ *
56488+ * Description:
56489+ * This function starts a port of the Yukon2 chip. This start
56490+ * action needs to be performed in a specific order:
56491+ *
56492+ * a) Initialize the LET indices (PUT/GET to 0)
56493+ * b) Initialize the LET in HW (enables also prefetch unit)
56494+ * c) Move all RX buffers from waiting queue to working queue
56495+ * which involves also setting up of RX list elements
56496+ * d) Initialize the FIFO settings of Yukon2 (Watermark etc.)
56497+ * e) Initialize the Port (MAC, PHY etc.)
56498+ * f) Initialize the MC addresses
56499+ *
56500+ * Returns: N/A
56501+ */
56502+void SkY2PortStart(
56503+SK_AC *pAC, /* adapter control context */
56504+SK_IOC IoC, /* I/O control context (address of adapter registers) */
56505+int Port) /* port to start */
56506+{
56507+ // SK_GEPORT *pPrt = &pAC->GIni.GP[Port];
56508+ SK_HWLE *pLE;
56509+ SK_U32 DWord;
56510+ SK_U32 PrefetchReg; /* register for Put index */
56511+
56512+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
56513+ ("==> SkY2PortStart (Port %c)\n", 'A' + Port));
56514+
56515+ /*
56516+ ** Initialize the LET indices
56517+ */
56518+ pAC->RxPort[Port].RxLET.Done = 0;
56519+ pAC->RxPort[Port].RxLET.Put = 0;
56520+ pAC->RxPort[Port].RxLET.HwPut = 0;
56521+ pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Done = 0;
56522+ pAC->TxPort[Port][TX_PRIO_LOW].TxALET.Put = 0;
56523+ pAC->TxPort[Port][TX_PRIO_LOW].TxALET.HwPut = 0;
56524+ if (HW_SYNC_TX_SUPPORTED(pAC)) {
56525+ pAC->TxPort[Port][TX_PRIO_LOW].TxSLET.Done = 0;
56526+ pAC->TxPort[Port][TX_PRIO_LOW].TxSLET.Put = 0;
56527+ pAC->TxPort[Port][TX_PRIO_LOW].TxSLET.HwPut = 0;
56528+ }
56529+
56530+ if (HW_FEATURE(pAC, HWF_WA_DEV_420)) {
56531+ /*
56532+ ** It might be that we have to limit the RX buffers
56533+ ** effectively passed to HW. Initialize the start
56534+ ** value in that case...
56535+ */
56536+ NbrRxBuffersInHW = 0;
56537+ }
56538+
56539+ /*
56540+ ** TODO on dual net adapters we need to check if
56541+ ** StatusLETable need to be set...
56542+ **
56543+ ** pAC->StatusLETable.Done = 0;
56544+ ** pAC->StatusLETable.Put = 0;
56545+ ** pAC->StatusLETable.HwPut = 0;
56546+ ** SkGeY2InitPrefetchUnit(pAC, pAC->IoBase, Q_ST, &pAC->StatusLETable);
56547+ */
56548+
56549+ /*
56550+ ** Initialize the LET in HW (enables also prefetch unit)
56551+ */
56552+ SkGeY2InitPrefetchUnit(pAC, IoC,(Port == 0) ? Q_R1 : Q_R2,
56553+ &pAC->RxPort[Port].RxLET);
56554+ SkGeY2InitPrefetchUnit( pAC, IoC,(Port == 0) ? Q_XA1 : Q_XA2,
56555+ &pAC->TxPort[Port][TX_PRIO_LOW].TxALET);
56556+ if (HW_SYNC_TX_SUPPORTED(pAC)) {
56557+ SkGeY2InitPrefetchUnit( pAC, IoC, (Port == 0) ? Q_XS1 : Q_XS2,
56558+ &pAC->TxPort[Port][TX_PRIO_HIGH].TxSLET);
56559+ }
56560+
56561+
56562+ /*
56563+ ** Using new values for the watermarks and the timer for
56564+ ** low latency optimization
56565+ */
56566+ if (pAC->LowLatency) {
56567+ SK_OUT8(IoC, STAT_FIFO_WM, 1);
56568+ SK_OUT8(IoC, STAT_FIFO_ISR_WM, 1);
56569+ SK_OUT32(IoC, STAT_LEV_TIMER_INI, 50);
56570+ SK_OUT32(IoC, STAT_ISR_TIMER_INI, 10);
56571+ }
56572+
56573+
56574+ /*
56575+ ** Initialize the Port (MAC, PHY etc.)
56576+ */
56577+ if (SkGeInitPort(pAC, IoC, Port)) {
56578+ if (Port == 0) {
56579+ printk("%s: SkGeInitPort A failed.\n",pAC->dev[0]->name);
56580+ } else {
56581+ printk("%s: SkGeInitPort B failed.\n",pAC->dev[1]->name);
56582+ }
56583+ }
56584+
56585+ if (IS_GMAC(pAC)) {
56586+ /* disable Rx GMAC FIFO Flush Mode */
56587+ SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8) GMF_RX_F_FL_OFF);
56588+ }
56589+
56590+ /*
56591+ ** Initialize the MC addresses
56592+ */
56593+ SkAddrMcUpdate(pAC,IoC, Port);
56594+
56595+ SkMacRxTxEnable(pAC, IoC,Port);
56596+
56597+ if (pAC->RxPort[Port].UseRxCsum) {
56598+ SkGeRxCsum(pAC, IoC, Port, SK_TRUE);
56599+
56600+ GET_RX_LE(pLE, &pAC->RxPort[Port].RxLET);
56601+ RXLE_SET_STACS1(pLE, pAC->CsOfs1);
56602+ RXLE_SET_STACS2(pLE, pAC->CsOfs2);
56603+ RXLE_SET_CTRL(pLE, 0);
56604+
56605+ RXLE_SET_OPC(pLE, OP_TCPSTART | HW_OWNER);
56606+ FLUSH_OPC(pLE);
56607+ if (Port == 0) {
56608+ PrefetchReg=Y2_PREF_Q_ADDR(Q_R1,PREF_UNIT_PUT_IDX_REG);
56609+ } else {
56610+ PrefetchReg=Y2_PREF_Q_ADDR(Q_R2,PREF_UNIT_PUT_IDX_REG);
56611+ }
56612+ DWord = GET_PUT_IDX(&pAC->RxPort[Port].RxLET);
56613+ SK_OUT32(IoC, PrefetchReg, DWord);
56614+ UPDATE_HWPUT_IDX(&pAC->RxPort[Port].RxLET);
56615+ }
56616+
56617+ pAC->GIni.GP[Port].PState = SK_PRT_RUN;
56618+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
56619+ ("<== SkY2PortStart()\n"));
56620+}
56621+
56622+/******************************************************************************
56623+ *
56624+ * Local Functions
56625+ *
56626+ *****************************************************************************/
56627+
56628+/*****************************************************************************
56629+ *
56630+ * InitPacketQueues - initialize SW settings of packet queues
56631+ *
56632+ * Description:
56633+ * This function will initialize the packet queues for a port.
56634+ *
56635+ * Returns: N/A
56636+ */
56637+static void InitPacketQueues(
56638+SK_AC *pAC, /* pointer to adapter control context */
56639+int Port) /* index of port to be initialized */
56640+{
56641+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
56642+ ("==> InitPacketQueues(Port %c)\n", 'A' + Port));
56643+
56644+ pAC->RxPort[Port].RxQ_working.pHead = NULL;
56645+ pAC->RxPort[Port].RxQ_working.pTail = NULL;
56646+ spin_lock_init(&pAC->RxPort[Port].RxQ_working.QueueLock);
56647+
56648+ pAC->RxPort[Port].RxQ_waiting.pHead = NULL;
56649+ pAC->RxPort[Port].RxQ_waiting.pTail = NULL;
56650+ spin_lock_init(&pAC->RxPort[Port].RxQ_waiting.QueueLock);
56651+
56652+ pAC->TxPort[Port][TX_PRIO_LOW].TxQ_free.pHead = NULL;
56653+ pAC->TxPort[Port][TX_PRIO_LOW].TxQ_free.pTail = NULL;
56654+ spin_lock_init(&pAC->TxPort[Port][TX_PRIO_LOW].TxQ_free.QueueLock);
56655+
56656+ pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_working.pHead = NULL;
56657+ pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_working.pTail = NULL;
56658+ spin_lock_init(&pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_working.QueueLock);
56659+
56660+ pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting.pHead = NULL;
56661+ pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting.pTail = NULL;
56662+ spin_lock_init(&pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting.QueueLock);
56663+
56664+#if USE_SYNC_TX_QUEUE
56665+ pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_working.pHead = NULL;
56666+ pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_working.pTail = NULL;
56667+ spin_lock_init(&pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_working.QueueLock);
56668+
56669+ pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_waiting.pHead = NULL;
56670+ pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_waiting.pTail = NULL;
56671+ spin_lock_init(&pAC->TxPort[Port][TX_PRIO_LOW].TxSQ_waiting.QueueLock);
56672+#endif
56673+
56674+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
56675+ ("<== InitPacketQueues(Port %c)\n", 'A' + Port));
56676+} /* InitPacketQueues */
56677+
56678+/*****************************************************************************
56679+ *
56680+ * GiveTxBufferToHw - commits a previously allocated DMA area to HW
56681+ *
56682+ * Description:
56683+ * This functions gives transmit buffers to HW. If no list elements
56684+ * are available the buffers will be queued.
56685+ *
56686+ * Notes:
56687+ * This function can run only once in a system at one time.
56688+ *
56689+ * Returns: N/A
56690+ */
56691+static void GiveTxBufferToHw(
56692+SK_AC *pAC, /* pointer to adapter control context */
56693+SK_IOC IoC, /* I/O control context (address of registers) */
56694+int Port) /* port index for which the buffer is used */
56695+{
56696+ SK_HWLE *pLE;
56697+ SK_PACKET *pSkPacket;
56698+ SK_FRAG *pFrag;
56699+ SK_PKT_QUEUE *pWorkQueue; /* corresponding TX queue */
56700+ SK_PKT_QUEUE *pWaitQueue;
56701+ SK_LE_TABLE *pLETab; /* corresponding LETable */
56702+ SK_BOOL SetOpcodePacketFlag;
56703+ SK_U32 HighAddress;
56704+ SK_U32 LowAddress;
56705+ SK_U16 TcpSumStart;
56706+ SK_U16 TcpSumWrite;
56707+ SK_U8 OpCode;
56708+ SK_U8 Ctrl;
56709+ unsigned long Flags;
56710+ unsigned long LockFlag;
56711+ int Protocol;
56712+#ifdef NETIF_F_TSO
56713+ SK_U16 Mss;
56714+ int TcpOptLen;
56715+ int IpTcpLen;
56716+#endif
56717+
56718+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
56719+ ("==> GiveTxBufferToHw\n"));
56720+
56721+ if (IS_Q_EMPTY(&(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting))) {
56722+ return;
56723+ }
56724+
56725+ spin_lock_irqsave(&pAC->TxQueueLock, LockFlag);
56726+
56727+ /*
56728+ ** Initialize queue settings
56729+ */
56730+ pWorkQueue = &(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_working);
56731+ pWaitQueue = &(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting);
56732+ pLETab = &(pAC->TxPort[Port][TX_PRIO_LOW].TxALET);
56733+
56734+ POP_FIRST_PKT_FROM_QUEUE(pWaitQueue, pSkPacket);
56735+ while (pSkPacket != NULL) {
56736+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
56737+ ("\tWe have a packet to send %p\n", pSkPacket));
56738+
56739+ /*
56740+ ** the first frag of a packet gets opcode OP_PACKET
56741+ */
56742+ SetOpcodePacketFlag = SK_TRUE;
56743+ pFrag = pSkPacket->pFrag;
56744+
56745+ /*
56746+ ** fill list elements with data from fragments
56747+ */
56748+ while (pFrag != NULL) {
56749+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
56750+ ("\tGet LE\n"));
56751+#ifdef NETIF_F_TSO
56752+ Mss = skb_shinfo(pSkPacket->pMBuf)->tso_size;
56753+ if (Mss) {
56754+ TcpOptLen = ((pSkPacket->pMBuf->h.th->doff - 5) * 4);
56755+ IpTcpLen = ((pSkPacket->pMBuf->nh.iph->ihl * 4) +
56756+ sizeof(struct tcphdr));
56757+ Mss += (TcpOptLen + IpTcpLen + C_LEN_ETHERMAC_HEADER);
56758+ }
56759+ if (pLETab->Bmu.RxTx.MssValue != Mss) {
56760+ pLETab->Bmu.RxTx.MssValue = Mss;
56761+ /* Take a new LE for TSO from the table */
56762+ GET_TX_LE(pLE, pLETab);
56763+
56764+#if 0
56765+ if(pSkPacket->VlanId) {
56766+ TXLE_SET_OPC(pLE, OP_LRGLENVLAN | HW_OWNER);
56767+ TXLE_SET_VLAN(pLE, pSkPacket->VlanId);
56768+ pSkPacket->VlanId = 0;
56769+ Ctrl |= INS_VLAN;
56770+ } else {
56771+#endif
56772+ TXLE_SET_OPC(pLE, OP_LRGLEN | HW_OWNER);
56773+#if 0
56774+ }
56775+#endif
56776+ /* set maximum segment size for new packet */
56777+ TXLE_SET_LSLEN(pLE, pLETab->Bmu.RxTx.MssValue);
56778+ FLUSH_OPC(pLE) ;
56779+ }
56780+#endif
56781+ GET_TX_LE(pLE, pLETab);
56782+ Ctrl = 0;
56783+
56784+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
56785+ ("\tGot empty LE %p idx %d\n", pLE, GET_PUT_IDX(pLETab)));
56786+
56787+ SK_DBG_DUMP_TX_LE(pLE);
56788+
56789+ LowAddress = (SK_U32) (pFrag->pPhys & 0xffffffff);
56790+ HighAddress = (SK_U32) (pFrag->pPhys >> 32);
56791+
56792+ if (HighAddress != pLETab->BufHighAddr) {
56793+ /* set opcode high part of the address in one LE */
56794+ OpCode = OP_ADDR64 | HW_OWNER;
56795+
56796+ /* Set now the 32 high bits of the address */
56797+ TXLE_SET_ADDR( pLE, HighAddress);
56798+
56799+ /* Set the opcode into the LE */
56800+ TXLE_SET_OPC(pLE, OpCode);
56801+
56802+ /* Flush the LE to memory */
56803+ FLUSH_OPC(pLE);
56804+
56805+ /* remember the HighAddress we gave to the Hardware */
56806+ pLETab->BufHighAddr = HighAddress;
56807+
56808+ /* get a new LE because we filled one with high address */
56809+ GET_TX_LE(pLE, pLETab);
56810+ }
56811+
56812+ /*
56813+ ** TCP checksum offload
56814+ */
56815+ if ((pSkPacket->pMBuf->ip_summed == CHECKSUM_HW) &&
56816+ (SetOpcodePacketFlag == SK_TRUE)) {
56817+ Protocol = ((SK_U8)pSkPacket->pMBuf->data[C_OFFSET_IPPROTO] & 0xff);
56818+ /* if (Protocol & C_PROTO_ID_IP) { Ctrl = 0; } */
56819+ if (Protocol & C_PROTO_ID_TCP) {
56820+ Ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
56821+ /* TCP Checksum Calculation Start Position */
56822+ TcpSumStart = C_LEN_ETHERMAC_HEADER + IP_HDR_LEN;
56823+ /* TCP Checksum Write Position */
56824+ TcpSumWrite = TcpSumStart + TCP_CSUM_OFFS;
56825+ } else {
56826+ Ctrl = UDPTCP | CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
56827+ /* TCP Checksum Calculation Start Position */
56828+ TcpSumStart = ETHER_MAC_HDR_LEN + IP_HDR_LEN;
56829+ /* UDP Checksum Write Position */
56830+ TcpSumWrite = TcpSumStart + UDP_CSUM_OFFS;
56831+ }
56832+
56833+ if ((Ctrl) && (pLETab->Bmu.RxTx.TcpWp != TcpSumWrite)) {
56834+ /* Update the last value of the write position */
56835+ pLETab->Bmu.RxTx.TcpWp = TcpSumWrite;
56836+
56837+ /* Set the Lock field for this LE: */
56838+ /* Checksum calculation for one packet only */
56839+ TXLE_SET_LCKCS(pLE, 1);
56840+
56841+ /* Set the start position for checksum. */
56842+ TXLE_SET_STACS(pLE, TcpSumStart);
56843+
56844+ /* Set the position where the checksum will be writen */
56845+ TXLE_SET_WRICS(pLE, TcpSumWrite);
56846+
56847+ /* Set the initial value for checksum */
56848+ /* PseudoHeader CS passed from Linux -> 0! */
56849+ TXLE_SET_INICS(pLE, 0);
56850+
56851+ /* Set the opcode for tcp checksum */
56852+ TXLE_SET_OPC(pLE, OP_TCPLISW | HW_OWNER);
56853+
56854+ /* Flush the LE to memory */
56855+ FLUSH_OPC(pLE);
56856+
56857+ /* get a new LE because we filled one with data for checksum */
56858+ GET_TX_LE(pLE, pLETab);
56859+ }
56860+ } /* end TCP offload handling */
56861+
56862+ TXLE_SET_ADDR(pLE, LowAddress);
56863+ TXLE_SET_LEN(pLE, pFrag->FragLen);
56864+
56865+ if (SetOpcodePacketFlag){
56866+#ifdef NETIF_F_TSO
56867+ if (Mss) {
56868+ OpCode = OP_LARGESEND | HW_OWNER;
56869+ } else {
56870+#endif
56871+ OpCode = OP_PACKET| HW_OWNER;
56872+#ifdef NETIF_F_TSO
56873+ }
56874+#endif
56875+ SetOpcodePacketFlag = SK_FALSE;
56876+ } else {
56877+ /* Follow packet in a sequence has always OP_BUFFER */
56878+ OpCode = OP_BUFFER | HW_OWNER;
56879+ }
56880+
56881+ /* Check if the low address is near the upper limit. */
56882+ CHECK_LOW_ADDRESS(pLETab->BufHighAddr, LowAddress, pFrag->FragLen);
56883+
56884+ pFrag = pFrag->pNext;
56885+ if (pFrag == NULL) {
56886+ /* mark last fragment */
56887+ Ctrl |= EOP;
56888+ }
56889+ TXLE_SET_CTRL(pLE, Ctrl);
56890+ TXLE_SET_OPC(pLE, OpCode);
56891+ FLUSH_OPC(pLE);
56892+
56893+ SK_DBG_DUMP_TX_LE(pLE);
56894+ }
56895+
56896+ /*
56897+ ** Remember next LE for tx complete
56898+ */
56899+ pSkPacket->NextLE = GET_PUT_IDX(pLETab);
56900+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
56901+ ("\tNext LE for pkt %p is %d\n", pSkPacket, pSkPacket->NextLE));
56902+
56903+ /*
56904+ ** Add packet to working packets queue
56905+ */
56906+ PUSH_PKT_AS_LAST_IN_QUEUE(pWorkQueue, pSkPacket);
56907+
56908+ /*
56909+ ** give transmit start command
56910+ */
56911+ if (HW_FEATURE(pAC, HWF_WA_DEV_42)) {
56912+ spin_lock(&pAC->SetPutIndexLock);
56913+ SkGeY2SetPutIndex(pAC, pAC->IoBase, Y2_PREF_Q_ADDR(Q_XA1,0), &pAC->TxPort[0][0].TxALET);
56914+ spin_unlock(&pAC->SetPutIndexLock);
56915+ } else {
56916+ /* write put index */
56917+ if (Port == 0) {
56918+ SK_OUT32(pAC->IoBase,
56919+ Y2_PREF_Q_ADDR(Q_XA1,PREF_UNIT_PUT_IDX_REG),
56920+ GET_PUT_IDX(&pAC->TxPort[0][0].TxALET));
56921+ UPDATE_HWPUT_IDX(&pAC->TxPort[0][0].TxALET);
56922+ } else {
56923+ SK_OUT32(pAC->IoBase,
56924+ Y2_PREF_Q_ADDR(Q_XA2, PREF_UNIT_PUT_IDX_REG),
56925+ GET_PUT_IDX(&pAC->TxPort[1][0].TxALET));
56926+ UPDATE_HWPUT_IDX(&pAC->TxPort[1][0].TxALET);
56927+ }
56928+ }
56929+
56930+ if (IS_Q_EMPTY(&(pAC->TxPort[Port][TX_PRIO_LOW].TxAQ_waiting))) {
56931+ break; /* get out of while */
56932+ }
56933+ POP_FIRST_PKT_FROM_QUEUE(pWaitQueue, pSkPacket);
56934+ } /* while (pSkPacket != NULL) */
56935+
56936+ spin_unlock_irqrestore(&pAC->TxQueueLock, LockFlag);
56937+
56938+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
56939+ ("<== GiveTxBufferToHw\n"));
56940+ return;
56941+} /* GiveTxBufferToHw */
56942+
56943+/***********************************************************************
56944+ *
56945+ * GiveRxBufferToHw - commits a previously allocated DMA area to HW
56946+ *
56947+ * Description:
56948+ * This functions gives receive buffers to HW. If no list elements
56949+ * are available the buffers will be queued.
56950+ *
56951+ * Notes:
56952+ * This function can run only once in a system at one time.
56953+ *
56954+ * Returns: N/A
56955+ */
56956+static void GiveRxBufferToHw(
56957+SK_AC *pAC, /* pointer to adapter control context */
56958+SK_IOC IoC, /* I/O control context (address of registers) */
56959+int Port, /* port index for which the buffer is used */
56960+SK_PACKET *pPacket) /* receive buffer(s) */
56961+{
56962+ SK_HWLE *pLE;
56963+ SK_LE_TABLE *pLETab;
56964+ SK_BOOL Done = SK_FALSE; /* at least on LE changed? */
56965+ SK_U32 LowAddress;
56966+ SK_U32 HighAddress;
56967+ SK_U32 PrefetchReg; /* register for Put index */
56968+ unsigned NumFree;
56969+ unsigned Required;
56970+ unsigned long Flags;
56971+
56972+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
56973+ ("==> GiveRxBufferToHw(Port %c, Packet %p)\n", 'A' + Port, pPacket));
56974+
56975+ pLETab = &pAC->RxPort[Port].RxLET;
56976+
56977+ if (Port == 0) {
56978+ PrefetchReg = Y2_PREF_Q_ADDR(Q_R1, PREF_UNIT_PUT_IDX_REG);
56979+ } else {
56980+ PrefetchReg = Y2_PREF_Q_ADDR(Q_R2, PREF_UNIT_PUT_IDX_REG);
56981+ }
56982+
56983+ if (pPacket != NULL) {
56984+ /*
56985+ ** For the time being, we have only one packet passed
56986+ ** to this function which might be changed in future!
56987+ */
56988+ PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket);
56989+ }
56990+
56991+ /*
56992+ ** now pPacket contains the very first waiting packet
56993+ */
56994+ POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket);
56995+ while (pPacket != NULL) {
56996+ if (HW_FEATURE(pAC, HWF_WA_DEV_420)) {
56997+ if (NbrRxBuffersInHW >= MAX_NBR_RX_BUFFERS_IN_HW) {
56998+ PUSH_PKT_AS_FIRST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket);
56999+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
57000+ ("<== GiveRxBufferToHw()\n"));
57001+ return;
57002+ }
57003+ NbrRxBuffersInHW++;
57004+ }
57005+
57006+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
57007+ ("Try to add packet %p\n", pPacket));
57008+
57009+ /*
57010+ ** Check whether we have enough listelements:
57011+ **
57012+ ** we have to take into account that each fragment
57013+ ** may need an additional list element for the high
57014+ ** part of the address here I simplified it by
57015+ ** using MAX_FRAG_OVERHEAD maybe it's worth to split
57016+ ** this constant for Rx and Tx or to calculate the
57017+ ** real number of needed LE's
57018+ */
57019+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
57020+ ("\tNum %d Put %d Done %d Free %d %d\n",
57021+ pLETab->Num, pLETab->Put, pLETab->Done,
57022+ NUM_FREE_LE_IN_TABLE(pLETab),
57023+ (NUM_FREE_LE_IN_TABLE(pLETab))));
57024+
57025+ Required = pPacket->NumFrags + MAX_FRAG_OVERHEAD;
57026+ NumFree = NUM_FREE_LE_IN_TABLE(pLETab);
57027+ if (NumFree) {
57028+ NumFree--;
57029+ }
57030+
57031+ if (Required > NumFree ) {
57032+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
57033+ SK_DBGCAT_DRV_RX_PROGRESS | SK_DBGCAT_DRV_ERROR,
57034+ ("\tOut of LEs have %d need %d\n",
57035+ NumFree, Required));
57036+
57037+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
57038+ ("\tWaitQueue starts with packet %p\n", pPacket));
57039+ PUSH_PKT_AS_FIRST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket);
57040+ if (Done) {
57041+ /*
57042+ ** write Put index to BMU or Polling Unit and make the LE's
57043+ ** available for the hardware
57044+ */
57045+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
57046+ ("\tWrite new Put Idx\n"));
57047+
57048+ SK_OUT32(IoC, PrefetchReg, GET_PUT_IDX(pLETab));
57049+ UPDATE_HWPUT_IDX(pLETab);
57050+ }
57051+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
57052+ ("<== GiveRxBufferToHw()\n"));
57053+ return;
57054+ } else {
57055+ if (!AllocAndMapRxBuffer(pAC, pPacket, Port)) {
57056+ /*
57057+ ** Failure while allocating sk_buff might
57058+ ** be due to temporary short of resources
57059+ ** Maybe next time buffers are available.
57060+ ** Until this, the packet remains in the
57061+ ** RX waiting queue...
57062+ */
57063+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
57064+ SK_DBGCAT_DRV_RX_PROGRESS | SK_DBGCAT_DRV_ERROR,
57065+ ("Failed to allocate Rx buffer\n"));
57066+
57067+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
57068+ ("WaitQueue starts with packet %p\n", pPacket));
57069+ PUSH_PKT_AS_FIRST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket);
57070+ if (Done) {
57071+ /*
57072+ ** write Put index to BMU or Polling
57073+ ** Unit and make the LE's
57074+ ** available for the hardware
57075+ */
57076+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
57077+ ("\tWrite new Put Idx\n"));
57078+
57079+ SK_OUT32(IoC, PrefetchReg, GET_PUT_IDX(pLETab));
57080+ UPDATE_HWPUT_IDX(pLETab);
57081+ }
57082+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
57083+ ("<== GiveRxBufferToHw()\n"));
57084+ return;
57085+ }
57086+ }
57087+ Done = SK_TRUE;
57088+
57089+ LowAddress = (SK_U32) (pPacket->pFrag->pPhys & 0xffffffff);
57090+ HighAddress = (SK_U32) (pPacket->pFrag->pPhys >> 32);
57091+ if (HighAddress != pLETab->BufHighAddr) {
57092+ /* get a new LE for high address */
57093+ GET_RX_LE(pLE, pLETab);
57094+
57095+ /* Set now the 32 high bits of the address */
57096+ RXLE_SET_ADDR(pLE, HighAddress);
57097+
57098+ /* Set the control bits of the address */
57099+ RXLE_SET_CTRL(pLE, 0);
57100+
57101+ /* Set the opcode into the LE */
57102+ RXLE_SET_OPC(pLE, (OP_ADDR64 | HW_OWNER));
57103+
57104+ /* Flush the LE to memory */
57105+ FLUSH_OPC(pLE);
57106+
57107+ /* remember the HighAddress we gave to the Hardware */
57108+ pLETab->BufHighAddr = HighAddress;
57109+ }
57110+
57111+ /*
57112+ ** Fill data into listelement
57113+ */
57114+ GET_RX_LE(pLE, pLETab);
57115+ RXLE_SET_ADDR(pLE, LowAddress);
57116+ RXLE_SET_LEN(pLE, pPacket->pFrag->FragLen);
57117+ RXLE_SET_CTRL(pLE, 0);
57118+ RXLE_SET_OPC(pLE, (OP_PACKET | HW_OWNER));
57119+ FLUSH_OPC(pLE);
57120+
57121+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
57122+ ("=== LE filled\n"));
57123+
57124+ SK_DBG_DUMP_RX_LE(pLE);
57125+
57126+ /*
57127+ ** Remember next LE for rx complete
57128+ */
57129+ pPacket->NextLE = GET_PUT_IDX(pLETab);
57130+
57131+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
57132+ ("\tPackets Next LE is %d\n", pPacket->NextLE));
57133+
57134+ /*
57135+ ** Add packet to working receive buffer queue and get
57136+ ** any next packet out of the waiting queue
57137+ */
57138+ PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_working, pPacket);
57139+ if (IS_Q_EMPTY(&(pAC->RxPort[Port].RxQ_waiting))) {
57140+ break; /* get out of while processing */
57141+ }
57142+ POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pPacket);
57143+ }
57144+
57145+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
57146+ ("\tWaitQueue is empty\n"));
57147+
57148+ if (Done) {
57149+ /*
57150+ ** write Put index to BMU or Polling Unit and make the LE's
57151+ ** available for the hardware
57152+ */
57153+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
57154+ ("\tWrite new Put Idx\n"));
57155+
57156+ /* Speed enhancement for a2 chipsets */
57157+ if (HW_FEATURE(pAC, HWF_WA_DEV_42)) {
57158+ spin_lock_irqsave(&pAC->SetPutIndexLock, Flags);
57159+ SkGeY2SetPutIndex(pAC, pAC->IoBase, Y2_PREF_Q_ADDR(Q_R1,0), pLETab);
57160+ spin_unlock_irqrestore(&pAC->SetPutIndexLock, Flags);
57161+ } else {
57162+ /* write put index */
57163+ if (Port == 0) {
57164+ SK_OUT32(IoC,
57165+ Y2_PREF_Q_ADDR(Q_R1, PREF_UNIT_PUT_IDX_REG),
57166+ GET_PUT_IDX(pLETab));
57167+ } else {
57168+ SK_OUT32(IoC,
57169+ Y2_PREF_Q_ADDR(Q_R2, PREF_UNIT_PUT_IDX_REG),
57170+ GET_PUT_IDX(pLETab));
57171+ }
57172+
57173+ /* Update put index */
57174+ UPDATE_HWPUT_IDX(pLETab);
57175+ }
57176+ }
57177+
57178+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
57179+ ("<== GiveRxBufferToHw()\n"));
57180+} /* GiveRxBufferToHw */
57181+
57182+/***********************************************************************
57183+ *
57184+ * FillReceiveTableYukon2 - map any waiting RX buffers to HW
57185+ *
57186+ * Description:
57187+ * If the list element table contains more empty elements than
57188+ * specified this function tries to refill them.
57189+ *
57190+ * Notes:
57191+ * This function can run only once per port in a system at one time.
57192+ *
57193+ * Returns: N/A
57194+ */
57195+void FillReceiveTableYukon2(
57196+SK_AC *pAC, /* pointer to adapter control context */
57197+SK_IOC IoC, /* I/O control context */
57198+int Port) /* port index of RX */
57199+{
57200+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
57201+ ("==> FillReceiveTableYukon2 (Port %c)\n", 'A' + Port));
57202+
57203+ if (NUM_FREE_LE_IN_TABLE(&pAC->RxPort[Port].RxLET) >
57204+ pAC->MaxUnusedRxLeWorking) {
57205+
57206+ /*
57207+ ** Give alle waiting receive buffers down
57208+ ** The queue holds all RX packets that
57209+ ** need a fresh allocation of the sk_buff.
57210+ */
57211+ if (pAC->RxPort[Port].RxQ_waiting.pHead != NULL) {
57212+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
57213+ ("Waiting queue is not empty -> give it to HW"));
57214+ GiveRxBufferToHw(pAC, IoC, Port, NULL);
57215+ }
57216+ }
57217+
57218+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
57219+ ("<== FillReceiveTableYukon2 ()\n"));
57220+} /* FillReceiveTableYukon2 */
57221+
57222+/******************************************************************************
57223+ *
57224+ *
57225+ * HandleReceives - will pass any ready RX packet to kernel
57226+ *
57227+ * Description:
57228+ * This functions handles a received packet. It checks wether it is
57229+ * valid, updates the receive list element table and gives the receive
57230+ * buffer to Linux
57231+ *
57232+ * Notes:
57233+ * This function can run only once per port at one time in the system.
57234+ *
57235+ * Returns: N/A
57236+ */
57237+static SK_BOOL HandleReceives(
57238+SK_AC *pAC, /* adapter control context */
57239+int Port, /* port on which a packet has been received */
57240+SK_U16 Len, /* number of bytes which was actually received */
57241+SK_U32 FrameStatus, /* MAC frame status word */
57242+SK_U16 Tcp1, /* first hw checksum */
57243+SK_U16 Tcp2, /* second hw checksum */
57244+SK_U32 Tist, /* timestamp */
57245+SK_U16 Vlan) /* Vlan Id */
57246+{
57247+
57248+ SK_PACKET *pSkPacket;
57249+ SK_LE_TABLE *pLETab;
57250+ SK_MBUF *pRlmtMbuf; /* buffer for giving RLMT frame */
57251+ struct sk_buff *pMsg; /* ptr to message holding frame */
57252+#ifdef __ia64__
57253+ struct sk_buff *pNewMsg; /* used when IP aligning */
57254+#endif
57255+
57256+#ifdef CONFIG_SK98LIN_NAPI
57257+ SK_BOOL SlowPathLock = SK_FALSE;
57258+#else
57259+ SK_BOOL SlowPathLock = SK_TRUE;
57260+#endif
57261+ SK_BOOL IsGoodPkt;
57262+ SK_BOOL IsBc;
57263+ SK_BOOL IsMc;
57264+ SK_EVPARA EvPara; /* an event parameter union */
57265+ SK_I16 LenToFree; /* must be signed integer */
57266+
57267+ unsigned long Flags; /* for spin lock */
57268+ unsigned int RlmtNotifier;
57269+ unsigned short Type;
57270+ int IpFrameLength;
57271+ int FrameLength; /* total length of recvd frame */
57272+ int HeaderLength;
57273+ int NumBytes;
57274+ int Result;
57275+ int Offset = 0;
57276+
57277+#ifdef Y2_SYNC_CHECK
57278+ SK_U16 MyTcp;
57279+#endif
57280+
57281+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
57282+ ("==> HandleReceives (Port %c)\n", 'A' + Port));
57283+
57284+ /*
57285+ ** initialize vars for selected port
57286+ */
57287+ pLETab = &pAC->RxPort[Port].RxLET;
57288+
57289+ /*
57290+ ** check whether we want to receive this packet
57291+ */
57292+ SK_Y2_RXSTAT_CHECK_PKT(Len, FrameStatus, IsGoodPkt);
57293+
57294+ /*
57295+ ** Remember length to free (in case of RxBuffer overruns;
57296+ ** unlikely, but might happen once in a while)
57297+ */
57298+ LenToFree = (SK_I16) Len;
57299+
57300+ /*
57301+ ** maybe we put these two checks into the SK_RXDESC_CHECK_PKT macro too
57302+ */
57303+ if (Len > pAC->RxPort[Port].RxBufSize) {
57304+ IsGoodPkt = SK_FALSE;
57305+ }
57306+
57307+ /*
57308+ ** take first receive buffer out of working queue
57309+ */
57310+ POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_working, pSkPacket);
57311+ if (pSkPacket == NULL) {
57312+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
57313+ SK_DBGCAT_DRV_ERROR,
57314+ ("Packet not available. NULL pointer.\n"));
57315+ return(SK_TRUE);
57316+ }
57317+
57318+ if (HW_FEATURE(pAC, HWF_WA_DEV_420)) {
57319+ NbrRxBuffersInHW--;
57320+ }
57321+
57322+ /*
57323+ ** Verify the received length of the frame! Note that having
57324+ ** multiple RxBuffers being aware of one single receive packet
57325+ ** (one packet spread over multiple RxBuffers) is not supported
57326+ ** by this driver!
57327+ */
57328+ if ((Len > pAC->RxPort[Port].RxBufSize) ||
57329+ (Len > (SK_U16) pSkPacket->PacketLen)) {
57330+ IsGoodPkt = SK_FALSE;
57331+ }
57332+
57333+ /*
57334+ ** Reset own bit in LE's between old and new Done index
57335+ ** This is not really necessary but makes debugging easier
57336+ */
57337+ CLEAR_LE_OWN_FROM_DONE_TO(pLETab, pSkPacket->NextLE);
57338+
57339+ /*
57340+ ** Free the list elements for new Rx buffers
57341+ */
57342+ SET_DONE_INDEX(pLETab, pSkPacket->NextLE);
57343+ pMsg = pSkPacket->pMBuf;
57344+ FrameLength = Len;
57345+
57346+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
57347+ ("Received frame of length %d on port %d\n",FrameLength, Port));
57348+
57349+ if (!IsGoodPkt) {
57350+ /*
57351+ ** release the DMA mapping
57352+ */
57353+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5)
57354+ pci_dma_sync_single(pAC->PciDev,
57355+ (dma_addr_t) pSkPacket->pFrag->pPhys,
57356+ pSkPacket->pFrag->FragLen,
57357+ PCI_DMA_FROMDEVICE);
57358+
57359+#else
57360+ pci_dma_sync_single_for_cpu(pAC->PciDev,
57361+ (dma_addr_t) pSkPacket->pFrag->pPhys,
57362+ pSkPacket->pFrag->FragLen,
57363+ PCI_DMA_FROMDEVICE);
57364+#endif
57365+
57366+ DEV_KFREE_SKB_ANY(pSkPacket->pMBuf);
57367+ PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pSkPacket);
57368+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
57369+ ("<== HandleReceives (Port %c)\n", 'A' + Port));
57370+
57371+ /*
57372+ ** Sanity check for RxBuffer overruns...
57373+ */
57374+ LenToFree = LenToFree - (pSkPacket->pFrag->FragLen);
57375+ while (LenToFree > 0) {
57376+ POP_FIRST_PKT_FROM_QUEUE(&pAC->RxPort[Port].RxQ_working, pSkPacket);
57377+ if (HW_FEATURE(pAC, HWF_WA_DEV_420)) {
57378+ NbrRxBuffersInHW--;
57379+ }
57380+ CLEAR_LE_OWN_FROM_DONE_TO(pLETab, pSkPacket->NextLE);
57381+ SET_DONE_INDEX(pLETab, pSkPacket->NextLE);
57382+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5)
57383+ pci_dma_sync_single(pAC->PciDev,
57384+ (dma_addr_t) pSkPacket->pFrag->pPhys,
57385+ pSkPacket->pFrag->FragLen,
57386+ PCI_DMA_FROMDEVICE);
57387+#else
57388+ pci_dma_sync_single_for_device(pAC->PciDev,
57389+ (dma_addr_t) pSkPacket->pFrag->pPhys,
57390+ pSkPacket->pFrag->FragLen,
57391+ PCI_DMA_FROMDEVICE);
57392+#endif
57393+
57394+ DEV_KFREE_SKB_ANY(pSkPacket->pMBuf);
57395+ PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pSkPacket);
57396+ LenToFree = LenToFree - ((SK_I16)(pSkPacket->pFrag->FragLen));
57397+
57398+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
57399+ SK_DBGCAT_DRV_RX_PROGRESS | SK_DBGCAT_DRV_ERROR,
57400+ ("<==HandleReceives (Port %c) drop faulty len pkt(2)\n",'A'+Port));
57401+ }
57402+ return(SK_TRUE);
57403+ } else {
57404+ /*
57405+ ** Release the DMA mapping
57406+ */
57407+ pci_unmap_single(pAC->PciDev,
57408+ pSkPacket->pFrag->pPhys,
57409+ pAC->RxPort[Port].RxBufSize,
57410+ PCI_DMA_FROMDEVICE);
57411+
57412+ skb_put(pMsg, FrameLength); /* set message len */
57413+ pMsg->ip_summed = CHECKSUM_NONE; /* initial default */
57414+
57415+#ifdef Y2_SYNC_CHECK
57416+ pAC->FramesWithoutSyncCheck++;
57417+ if (pAC->FramesWithoutSyncCheck > Y2_RESYNC_WATERMARK) {
57418+ if ((Tcp1 != 1) || (Tcp2 != 0)) {
57419+ pAC->FramesWithoutSyncCheck = 0;
57420+ MyTcp = (SK_U16) SkCsCalculateChecksum(
57421+ &pMsg->data[14],
57422+ FrameLength - 14);
57423+ if (MyTcp != Tcp1) {
57424+ /* Queue port reset event */
57425+ SkLocalEventQueue(pAC, SKGE_DRV,
57426+ SK_DRV_RECOVER,Port,-1,SK_FALSE);
57427+ }
57428+ }
57429+ }
57430+#endif
57431+
57432+ if (pAC->RxPort[Port].UseRxCsum) {
57433+ Type = ntohs(*((short*)&pMsg->data[12]));
57434+ if (Type == 0x800) {
57435+ *((char *)&(IpFrameLength)) = pMsg->data[16];
57436+ *(((char *)&(IpFrameLength))+1) = pMsg->data[17];
57437+ IpFrameLength = ntohs(IpFrameLength);
57438+ HeaderLength = FrameLength - IpFrameLength;
57439+ if (HeaderLength == 0xe) {
57440+ Result =
57441+ SkCsGetReceiveInfo(pAC,&pMsg->data[14],Tcp1,Tcp2, Port);
57442+ if ((Result == SKCS_STATUS_IP_FRAGMENT) ||
57443+ (Result == SKCS_STATUS_IP_CSUM_OK) ||
57444+ (Result == SKCS_STATUS_TCP_CSUM_OK) ||
57445+ (Result == SKCS_STATUS_UDP_CSUM_OK)) {
57446+ pMsg->ip_summed = CHECKSUM_UNNECESSARY;
57447+ } else if ((Result == SKCS_STATUS_TCP_CSUM_ERROR) ||
57448+ (Result == SKCS_STATUS_UDP_CSUM_ERROR) ||
57449+ (Result == SKCS_STATUS_IP_CSUM_ERROR_UDP) ||
57450+ (Result == SKCS_STATUS_IP_CSUM_ERROR_TCP) ||
57451+ (Result == SKCS_STATUS_IP_CSUM_ERROR)) {
57452+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
57453+ SK_DBGCAT_DRV_RX_PROGRESS | SK_DBGCAT_DRV_ERROR,
57454+ ("skge: CRC error. Frame dropped!\n"));
57455+ DEV_KFREE_SKB_ANY(pMsg);
57456+ PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pSkPacket);
57457+ SK_DBG_MSG(pAC,SK_DBGMOD_DRV,SK_DBGCAT_DRV_RX_PROGRESS,
57458+ ("<==HandleReceives(Port %c)\n",'A'+Port));
57459+ return(SK_TRUE);
57460+ } else {
57461+ pMsg->ip_summed = CHECKSUM_NONE;
57462+ }
57463+ } /* end if (HeaderLength == valid) */
57464+ } /* end if (Type == 0x800) -> IP frame */
57465+ } /* end if (pRxPort->UseRxCsum) */
57466+
57467+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
57468+ SK_DBGCAT_DRV_RX_PROGRESS,("V"));
57469+ RlmtNotifier = SK_RLMT_RX_PROTOCOL;
57470+
57471+ IsBc = (FrameStatus & GMR_FS_BC) ? SK_TRUE : SK_FALSE;
57472+ SK_RLMT_PRE_LOOKAHEAD(pAC,Port,FrameLength,
57473+ IsBc,&Offset,&NumBytes);
57474+ if (NumBytes != 0) {
57475+ IsMc = (FrameStatus & GMR_FS_MC) ? SK_TRUE : SK_FALSE;
57476+ SK_RLMT_LOOKAHEAD(pAC,Port,&pMsg->data[Offset],
57477+ IsBc,IsMc,&RlmtNotifier);
57478+ }
57479+
57480+ if (RlmtNotifier == SK_RLMT_RX_PROTOCOL) {
57481+ SK_DBG_MSG(NULL,SK_DBGMOD_DRV,
57482+ SK_DBGCAT_DRV_RX_PROGRESS,("W"));
57483+ if ((Port == pAC->ActivePort)||(pAC->RlmtNets == 2)) {
57484+ /* send up only frames from active port */
57485+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
57486+ SK_DBGCAT_DRV_RX_PROGRESS,("U"));
57487+#ifdef xDEBUG
57488+ DumpMsg(pMsg, "Rx");
57489+#endif
57490+ SK_PNMI_CNT_RX_OCTETS_DELIVERED(pAC,
57491+ FrameLength, Port);
57492+#ifdef __ia64__
57493+ pNewMsg = alloc_skb(pMsg->len, GFP_ATOMIC);
57494+ skb_reserve(pNewMsg, 2); /* to align IP */
57495+ SK_MEMCPY(pNewMsg->data,pMsg->data,pMsg->len);
57496+ pNewMsg->ip_summed = pMsg->ip_summed;
57497+ skb_put(pNewMsg, pMsg->len);
57498+ DEV_KFREE_SKB_ANY(pMsg);
57499+ pMsg = pNewMsg;
57500+#endif
57501+ pMsg->dev = pAC->dev[Port];
57502+ pMsg->protocol = eth_type_trans(pMsg,
57503+ pAC->dev[Port]);
57504+ netif_rx(pMsg);
57505+ pAC->dev[Port]->last_rx = jiffies;
57506+ } else { /* drop frame */
57507+ SK_DBG_MSG(NULL,SK_DBGMOD_DRV,
57508+ SK_DBGCAT_DRV_RX_PROGRESS,("D"));
57509+ DEV_KFREE_SKB_ANY(pMsg);
57510+ }
57511+ } else { /* This is an RLMT-packet! */
57512+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
57513+ SK_DBGCAT_DRV_RX_PROGRESS,("R"));
57514+ pRlmtMbuf = SkDrvAllocRlmtMbuf(pAC,
57515+ pAC->IoBase, FrameLength);
57516+ if (pRlmtMbuf != NULL) {
57517+ pRlmtMbuf->pNext = NULL;
57518+ pRlmtMbuf->Length = FrameLength;
57519+ pRlmtMbuf->PortIdx = Port;
57520+ EvPara.pParaPtr = pRlmtMbuf;
57521+ SK_MEMCPY((char*)(pRlmtMbuf->pData),
57522+ (char*)(pMsg->data),FrameLength);
57523+
57524+ if (SlowPathLock == SK_TRUE) {
57525+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
57526+ SkEventQueue(pAC, SKGE_RLMT,
57527+ SK_RLMT_PACKET_RECEIVED,
57528+ EvPara);
57529+ pAC->CheckQueue = SK_TRUE;
57530+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
57531+ } else {
57532+ SkEventQueue(pAC, SKGE_RLMT,
57533+ SK_RLMT_PACKET_RECEIVED,
57534+ EvPara);
57535+ pAC->CheckQueue = SK_TRUE;
57536+ }
57537+
57538+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
57539+ SK_DBGCAT_DRV_RX_PROGRESS,("Q"));
57540+ }
57541+ if (pAC->dev[Port]->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
57542+#ifdef __ia64__
57543+ pNewMsg = alloc_skb(pMsg->len, GFP_ATOMIC);
57544+ skb_reserve(pNewMsg, 2); /* to align IP */
57545+ SK_MEMCPY(pNewMsg->data,pMsg->data,pMsg->len);
57546+ pNewMsg->ip_summed = pMsg->ip_summed;
57547+ pNewMsg->len = pMsg->len;
57548+ DEV_KFREE_SKB_ANY(pMsg);
57549+ pMsg = pNewMsg;
57550+#endif
57551+ pMsg->dev = pAC->dev[Port];
57552+ pMsg->protocol = eth_type_trans(pMsg,pAC->dev[Port]);
57553+ netif_rx(pMsg);
57554+ pAC->dev[Port]->last_rx = jiffies;
57555+ } else {
57556+ DEV_KFREE_SKB_ANY(pMsg);
57557+ }
57558+ } /* if packet for rlmt */
57559+ PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[Port].RxQ_waiting, pSkPacket);
57560+ } /* end if-else (IsGoodPkt) */
57561+
57562+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
57563+ ("<== HandleReceives (Port %c)\n", 'A' + Port));
57564+ return(SK_TRUE);
57565+
57566+} /* HandleReceives */
57567+
57568+/***********************************************************************
57569+ *
57570+ * CheckForSendComplete - Frees any freeable Tx bufffer
57571+ *
57572+ * Description:
57573+ * This function checks the queues of a port for completed send
57574+ * packets and returns these packets back to the OS.
57575+ *
57576+ * Notes:
57577+ * This function can run simultaneously for both ports if
57578+ * the OS function OSReturnPacket() can handle this,
57579+ *
57580+ * Such a send complete does not mean, that the packet is really
57581+ * out on the wire. We just know that the adapter has copied it
57582+ * into its internal memory and the buffer in the systems memory
57583+ * is no longer needed.
57584+ *
57585+ * Returns: N/A
57586+ */
57587+static void CheckForSendComplete(
57588+SK_AC *pAC, /* pointer to adapter control context */
57589+SK_IOC IoC, /* I/O control context */
57590+int Port, /* port index */
57591+SK_PKT_QUEUE *pPQ, /* tx working packet queue to check */
57592+SK_LE_TABLE *pLETab, /* corresponding list element table */
57593+unsigned int Done) /* done index reported for this LET */
57594+{
57595+ SK_PACKET *pSkPacket;
57596+ SK_PKT_QUEUE SendCmplPktQ = { NULL, NULL, SPIN_LOCK_UNLOCKED };
57597+ SK_BOOL DoWakeQueue = SK_FALSE;
57598+ unsigned long Flags;
57599+ unsigned Put;
57600+
57601+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
57602+ ("==> CheckForSendComplete(Port %c)\n", 'A' + Port));
57603+
57604+ /*
57605+ ** Reset own bit in LE's between old and new Done index
57606+ ** This is not really necessairy but makes debugging easier
57607+ */
57608+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
57609+ ("Clear Own Bits in TxTable from %d to %d\n",
57610+ pLETab->Done, (Done == 0) ?
57611+ NUM_LE_IN_TABLE(pLETab) :
57612+ (Done - 1)));
57613+
57614+ spin_lock_irqsave(&(pPQ->QueueLock), Flags);
57615+
57616+ CLEAR_LE_OWN_FROM_DONE_TO(pLETab, Done);
57617+
57618+ Put = GET_PUT_IDX(pLETab);
57619+
57620+ /*
57621+ ** Check whether some packets have been completed
57622+ */
57623+ PLAIN_POP_FIRST_PKT_FROM_QUEUE(pPQ, pSkPacket);
57624+ while (pSkPacket != NULL) {
57625+
57626+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
57627+ ("Check Completion of Tx packet %p\n", pSkPacket));
57628+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
57629+ ("Put %d NewDone %d NextLe of Packet %d\n", Put, Done,
57630+ pSkPacket->NextLE));
57631+
57632+ if ((Put > Done) &&
57633+ ((pSkPacket->NextLE > Put) || (pSkPacket->NextLE <= Done))) {
57634+ PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(&SendCmplPktQ, pSkPacket);
57635+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
57636+ ("Packet finished (a)\n"));
57637+ } else if ((Done > Put) &&
57638+ (pSkPacket->NextLE > Put) && (pSkPacket->NextLE <= Done)) {
57639+ PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(&SendCmplPktQ, pSkPacket);
57640+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
57641+ ("Packet finished (b)\n"));
57642+ } else if ((Done == TXA_MAX_LE-1) && (Put == 0) && (pSkPacket->NextLE == 0)) {
57643+ PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(&SendCmplPktQ, pSkPacket);
57644+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
57645+ ("Packet finished (b)\n"));
57646+ DoWakeQueue = SK_TRUE;
57647+ } else if (Done == Put) {
57648+ /* all packets have been sent */
57649+ PLAIN_PUSH_PKT_AS_LAST_IN_QUEUE(&SendCmplPktQ, pSkPacket);
57650+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
57651+ ("Packet finished (c)\n"));
57652+ } else {
57653+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
57654+ ("Packet not yet finished\n"));
57655+ PLAIN_PUSH_PKT_AS_FIRST_IN_QUEUE(pPQ, pSkPacket);
57656+ break;
57657+ }
57658+ PLAIN_POP_FIRST_PKT_FROM_QUEUE(pPQ, pSkPacket);
57659+ }
57660+ spin_unlock_irqrestore(&(pPQ->QueueLock), Flags);
57661+
57662+ /*
57663+ ** Set new done index in list element table
57664+ */
57665+ SET_DONE_INDEX(pLETab, Done);
57666+
57667+ /*
57668+ ** All TX packets that are send complete should be added to
57669+ ** the free queue again for new sents to come
57670+ */
57671+ pSkPacket = SendCmplPktQ.pHead;
57672+ while (pSkPacket != NULL) {
57673+ while (pSkPacket->pFrag != NULL) {
57674+ pci_unmap_page(pAC->PciDev,
57675+ (dma_addr_t) pSkPacket->pFrag->pPhys,
57676+ pSkPacket->pFrag->FragLen,
57677+ PCI_DMA_FROMDEVICE);
57678+ pSkPacket->pFrag = pSkPacket->pFrag->pNext;
57679+ }
57680+
57681+ DEV_KFREE_SKB_ANY(pSkPacket->pMBuf);
57682+ pSkPacket->pMBuf = NULL;
57683+ pSkPacket = pSkPacket->pNext; /* get next packet */
57684+ }
57685+
57686+ /*
57687+ ** Append the available TX packets back to free queue
57688+ */
57689+ if (SendCmplPktQ.pHead != NULL) {
57690+ spin_lock_irqsave(&(pAC->TxPort[Port][0].TxQ_free.QueueLock), Flags);
57691+ if (pAC->TxPort[Port][0].TxQ_free.pTail != NULL) {
57692+ pAC->TxPort[Port][0].TxQ_free.pTail->pNext = SendCmplPktQ.pHead;
57693+ pAC->TxPort[Port][0].TxQ_free.pTail = SendCmplPktQ.pTail;
57694+ if (pAC->TxPort[Port][0].TxQ_free.pHead->pNext == NULL) {
57695+ netif_wake_queue(pAC->dev[Port]);
57696+ }
57697+ } else {
57698+ pAC->TxPort[Port][0].TxQ_free.pHead = SendCmplPktQ.pHead;
57699+ pAC->TxPort[Port][0].TxQ_free.pTail = SendCmplPktQ.pTail;
57700+ netif_wake_queue(pAC->dev[Port]);
57701+ }
57702+ if (Done == Put) {
57703+ netif_wake_queue(pAC->dev[Port]);
57704+ }
57705+ if (DoWakeQueue) {
57706+ netif_wake_queue(pAC->dev[Port]);
57707+ DoWakeQueue = SK_FALSE;
57708+ }
57709+ spin_unlock_irqrestore(&pAC->TxPort[Port][0].TxQ_free.QueueLock, Flags);
57710+ }
57711+
57712+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
57713+ ("<== CheckForSendComplete()\n"));
57714+
57715+ return;
57716+} /* CheckForSendComplete */
57717+
57718+/*****************************************************************************
57719+ *
57720+ * UnmapAndFreeTxPktBuffer
57721+ *
57722+ * Description:
57723+ * This function free any allocated space of receive buffers
57724+ *
57725+ * Arguments:
57726+ * pAC - A pointer to the adapter context struct.
57727+ *
57728+ */
57729+static void UnmapAndFreeTxPktBuffer(
57730+SK_AC *pAC, /* pointer to adapter context */
57731+SK_PACKET *pSkPacket, /* pointer to port struct of ring to fill */
57732+int TxPort) /* TX port index */
57733+{
57734+ SK_FRAG *pFrag = pSkPacket->pFrag;
57735+
57736+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
57737+ ("--> UnmapAndFreeTxPktBuffer\n"));
57738+
57739+ while (pFrag != NULL) {
57740+ pci_unmap_page(pAC->PciDev,
57741+ (dma_addr_t) pFrag->pPhys,
57742+ pFrag->FragLen,
57743+ PCI_DMA_FROMDEVICE);
57744+ pFrag = pFrag->pNext;
57745+ }
57746+
57747+ DEV_KFREE_SKB_ANY(pSkPacket->pMBuf);
57748+ pSkPacket->pMBuf = NULL;
57749+
57750+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
57751+ ("<-- UnmapAndFreeTxPktBuffer\n"));
57752+}
57753+
57754+/*****************************************************************************
57755+ *
57756+ * HandleStatusLEs
57757+ *
57758+ * Description:
57759+ * This function checks for any new status LEs that may have been
57760+ * received. Those status LEs may either be Rx or Tx ones.
57761+ *
57762+ * Returns: N/A
57763+ */
57764+static SK_BOOL HandleStatusLEs(
57765+#ifdef CONFIG_SK98LIN_NAPI
57766+SK_AC *pAC, /* pointer to adapter context */
57767+int *WorkDone, /* Done counter needed for NAPI */
57768+int WorkToDo) /* ToDo counter for NAPI */
57769+#else
57770+SK_AC *pAC) /* pointer to adapter context */
57771+#endif
57772+{
57773+ int DoneTxA[SK_MAX_MACS];
57774+ int DoneTxS[SK_MAX_MACS];
57775+ int Port;
57776+ SK_BOOL handledStatLE = SK_FALSE;
57777+ SK_BOOL NewDone = SK_FALSE;
57778+ SK_HWLE *pLE;
57779+ SK_U16 HighVal;
57780+ SK_U32 LowVal;
57781+ SK_U8 OpCode;
57782+ int i;
57783+
57784+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
57785+ ("==> HandleStatusLEs\n"));
57786+
57787+ do {
57788+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
57789+ ("Check next Own Bit of ST-LE[%d]: 0x%li \n",
57790+ (pAC->StatusLETable.Done + 1) % NUM_LE_IN_TABLE(&pAC->StatusLETable),
57791+ OWN_OF_FIRST_LE(&pAC->StatusLETable)));
57792+
57793+ while (OWN_OF_FIRST_LE(&pAC->StatusLETable) == HW_OWNER) {
57794+ GET_ST_LE(pLE, &pAC->StatusLETable);
57795+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
57796+ ("Working on finished status LE[%d]:\n",
57797+ GET_DONE_INDEX(&pAC->StatusLETable)));
57798+ SK_DBG_DUMP_ST_LE(pLE);
57799+ handledStatLE = SK_TRUE;
57800+ OpCode = STLE_GET_OPC(pLE) & ~HW_OWNER;
57801+ Port = STLE_GET_LINK(pLE);
57802+
57803+#ifdef USE_TIST_FOR_RESET
57804+ if (SK_ADAPTER_WAITING_FOR_TIST(pAC)) {
57805+ /* do we just have a tist LE ? */
57806+ if ((OpCode & OP_RXTIMESTAMP) == OP_RXTIMESTAMP) {
57807+ for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
57808+ if (SK_PORT_WAITING_FOR_ANY_TIST(pAC, i)) {
57809+ /* if a port is waiting for any tist it is done */
57810+ SK_CLR_STATE_FOR_PORT(pAC, i);
57811+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
57812+ ("Got any Tist on port %c (now 0x%X!!!)\n",
57813+ 'A' + i, pAC->AdapterResetState));
57814+ }
57815+ if (SK_PORT_WAITING_FOR_SPECIFIC_TIST(pAC, i)) {
57816+ Y2_GET_TIST_LOW_VAL(pAC->IoBase, &LowVal);
57817+ if ((pAC->MinTistHi != pAC->GIni.GITimeStampCnt) ||
57818+ (pAC->MinTistLo < LowVal)) {
57819+ /* time is up now */
57820+ SK_CLR_STATE_FOR_PORT(pAC, i);
57821+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
57822+ ("Got expected Tist on Port %c (now 0x%X)!!!\n",
57823+ 'A' + i, pAC->AdapterResetState));
57824+#ifdef Y2_SYNC_CHECK
57825+ pAC->FramesWithoutSyncCheck =
57826+ Y2_RESYNC_WATERMARK;
57827+#endif
57828+ } else {
57829+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
57830+ ("Got Tist %l:%l on Port %c but still waiting\n",
57831+ pAC->GIni.GITimeStampCnt, pAC->MinTistLo,
57832+ 'A' + i));
57833+ }
57834+ }
57835+ }
57836+#ifndef Y2_RECOVERY
57837+ if (!SK_ADAPTER_WAITING_FOR_TIST(pAC)) {
57838+ /* nobody needs tist anymore - turn it off */
57839+ Y2_DISABLE_TIST(pAC->IoBase);
57840+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
57841+ ("Turn off Tist !!!\n"));
57842+ }
57843+#endif
57844+ } else if (OpCode == OP_TXINDEXLE) {
57845+ /*
57846+ * change OpCode to notify the folowing code
57847+ * to ignore the done index from this LE
57848+ * unfortunately tist LEs will be generated only
57849+ * for RxStat LEs
57850+ * so in order to get a safe Done index for a
57851+ * port currently waiting for a tist we have to
57852+ * get the done index directly from the BMU
57853+ */
57854+ OpCode = OP_MOD_TXINDEX;
57855+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
57856+ ("Mark unusable TX_INDEX LE!!!\n"));
57857+ } else {
57858+ if (SK_PORT_WAITING_FOR_TIST(pAC, Port)) {
57859+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
57860+ ("Ignore LE 0x%X on Port %c!!!\n",
57861+ OpCode, 'A' + Port));
57862+ OpCode = OP_MOD_LE;
57863+#ifdef Y2_LE_CHECK
57864+ /* mark entries invalid */
57865+ pAC->LastOpc = 0xFF;
57866+ pAC->LastPort = 3;
57867+#endif
57868+ }
57869+ }
57870+ } /* if (SK_ADAPTER_WAITING_FOR_TIST(pAC)) */
57871+#endif
57872+
57873+
57874+
57875+
57876+
57877+#ifdef Y2_LE_CHECK
57878+ if (pAC->LastOpc != 0xFF) {
57879+ /* last opc is valid
57880+ * check if current opcode follows last opcode
57881+ */
57882+ if ((((OpCode & OP_RXTIMESTAMP) == OP_RXTIMESTAMP) && (pAC->LastOpc != OP_RXSTAT)) ||
57883+ (((OpCode & OP_RXCHKS) == OP_RXCHKS) && (pAC->LastOpc != OP_RXTIMESTAMP)) ||
57884+ ((OpCode == OP_RXSTAT) && (pAC->LastOpc != OP_RXCHKS))) {
57885+
57886+ /* opcode sequence broken
57887+ * current LE is invalid
57888+ */
57889+
57890+ if (pAC->LastOpc == OP_RXTIMESTAMP) {
57891+ /* force invalid checksum */
57892+ pLE->St.StUn.StRxTCPCSum.RxTCPSum1 = 1;
57893+ pLE->St.StUn.StRxTCPCSum.RxTCPSum2 = 0;
57894+ OpCode = pAC->LastOpc = OP_RXCHKS;
57895+ Port = pAC->LastPort;
57896+ } else if (pAC->LastOpc == OP_RXCHKS) {
57897+ /* force invalid frame */
57898+ Port = pAC->LastPort;
57899+ pLE->St.Stat.BufLen = 64;
57900+ pLE->St.StUn.StRxStatWord = GMR_FS_CRC_ERR;
57901+ OpCode = pAC->LastOpc = OP_RXSTAT;
57902+#ifdef Y2_SYNC_CHECK
57903+ /* force rx sync check */
57904+ pAC->FramesWithoutSyncCheck = Y2_RESYNC_WATERMARK;
57905+#endif
57906+ } else if (pAC->LastOpc == OP_RXSTAT) {
57907+ /* create dont care tist */
57908+ pLE->St.StUn.StRxTimeStamp = 0;
57909+ OpCode = pAC->LastOpc = OP_RXTIMESTAMP;
57910+ /* dont know the port yet */
57911+ } else {
57912+#ifdef DEBUG
57913+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
57914+ ("Unknown LastOpc %X for Timestamp on port %c.\n",
57915+ pAC->LastOpc, Port));
57916+#endif
57917+ }
57918+ }
57919+ }
57920+#endif
57921+
57922+ switch (OpCode) {
57923+ case OP_RXSTAT:
57924+#ifdef Y2_RECOVERY
57925+ pAC->LastOpc = OP_RXSTAT;
57926+#endif
57927+ /*
57928+ ** This is always the last Status LE belonging
57929+ ** to a received packet -> handle it...
57930+ */
57931+ if ((Port != 0) && (Port != 1)) {
57932+ /* Unknown port */
57933+ panic("sk98lin: Unknown port %d\n",
57934+ Port);
57935+ }
57936+
57937+ HandleReceives(
57938+ pAC,
57939+ Port,
57940+ STLE_GET_LEN(pLE),
57941+ STLE_GET_FRSTATUS(pLE),
57942+ pAC->StatusLETable.Bmu.Stat.TcpSum1,
57943+ pAC->StatusLETable.Bmu.Stat.TcpSum2,
57944+ pAC->StatusLETable.Bmu.Stat.RxTimeStamp,
57945+ pAC->StatusLETable.Bmu.Stat.VlanId);
57946+#ifdef CONFIG_SK98LIN_NAPI
57947+ if (*WorkDone >= WorkToDo) {
57948+ break;
57949+ }
57950+ (*WorkDone)++;
57951+#endif
57952+ break;
57953+ case OP_RXVLAN:
57954+ /* this value will be used for next RXSTAT */
57955+ pAC->StatusLETable.Bmu.Stat.VlanId = STLE_GET_VLAN(pLE);
57956+ break;
57957+ case OP_RXTIMEVLAN:
57958+ /* this value will be used for next RXSTAT */
57959+ pAC->StatusLETable.Bmu.Stat.VlanId = STLE_GET_VLAN(pLE);
57960+ /* fall through */
57961+ case OP_RXTIMESTAMP:
57962+ /* this value will be used for next RXSTAT */
57963+ pAC->StatusLETable.Bmu.Stat.RxTimeStamp = STLE_GET_TIST(pLE);
57964+#ifdef Y2_RECOVERY
57965+ pAC->LastOpc = OP_RXTIMESTAMP;
57966+ pAC->LastPort = Port;
57967+#endif
57968+ break;
57969+ case OP_RXCHKSVLAN:
57970+ /* this value will be used for next RXSTAT */
57971+ pAC->StatusLETable.Bmu.Stat.VlanId = STLE_GET_VLAN(pLE);
57972+ /* fall through */
57973+ case OP_RXCHKS:
57974+ /* this value will be used for next RXSTAT */
57975+ pAC->StatusLETable.Bmu.Stat.TcpSum1 = STLE_GET_TCP1(pLE);
57976+ pAC->StatusLETable.Bmu.Stat.TcpSum2 = STLE_GET_TCP2(pLE);
57977+#ifdef Y2_RECOVERY
57978+ pAC->LastPort = Port;
57979+ pAC->LastOpc = OP_RXCHKS;
57980+#endif
57981+ break;
57982+ case OP_RSS_HASH:
57983+ /* this value will be used for next RXSTAT */
57984+#if 0
57985+ pAC->StatusLETable.Bmu.Stat.RssHashValue = STLE_GET_RSS(pLE);
57986+#endif
57987+ break;
57988+ case OP_TXINDEXLE:
57989+ /*
57990+ ** :;:; TODO
57991+ ** it would be possible to check for which queues
57992+ ** the index has been changed and call
57993+ ** CheckForSendComplete() only for such queues
57994+ */
57995+ STLE_GET_DONE_IDX(pLE,LowVal,HighVal);
57996+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
57997+ ("LowVal: 0x%x HighVal: 0x%x\n", LowVal, HighVal));
57998+
57999+ /*
58000+ ** It would be possible to check whether we really
58001+ ** need the values for second port or sync queue,
58002+ ** but I think checking whether we need them is
58003+ ** more expensive than the calculation
58004+ */
58005+ DoneTxA[0] = STLE_GET_DONE_IDX_TXA1(LowVal,HighVal);
58006+ DoneTxS[0] = STLE_GET_DONE_IDX_TXS1(LowVal,HighVal);
58007+ DoneTxA[1] = STLE_GET_DONE_IDX_TXA2(LowVal,HighVal);
58008+ DoneTxS[1] = STLE_GET_DONE_IDX_TXS2(LowVal,HighVal);
58009+
58010+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
58011+ ("DoneTxa1 0x%x DoneTxS1: 0x%x DoneTxa2 0x%x DoneTxS2: 0x%x\n",
58012+ DoneTxA[0], DoneTxS[0], DoneTxA[1], DoneTxS[1]));
58013+
58014+ NewDone = SK_TRUE;
58015+ break;
58016+#ifdef USE_TIST_FOR_RESET
58017+ case OP_MOD_TXINDEX:
58018+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
58019+ ("OP_MOD_TXINDEX\n"));
58020+ SK_IN16(pAC->IoBase, Q_ADDR(Q_XA1, Q_DONE), &DoneTxA[0]);
58021+ if (pAC->GIni.GIMacsFound > 1) {
58022+ SK_IN16(pAC->IoBase, Q_ADDR(Q_XA2, Q_DONE), &DoneTxA[1]);
58023+ }
58024+ NewDone = SK_TRUE;
58025+ break;
58026+ case OP_MOD_LE:
58027+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DUMP,
58028+ ("Ignore marked LE on port in Reset\n"));
58029+ break;
58030+#endif
58031+
58032+ default:
58033+ /*
58034+ ** Have to handle the illegal Opcode in Status LE
58035+ */
58036+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
58037+ ("Unexpected OpCode\n"));
58038+ break;
58039+ }
58040+
58041+#ifdef Y2_RECOVERY
58042+ OpCode = STLE_GET_OPC(pLE) & ~HW_OWNER;
58043+ STLE_SET_OPC(pLE, OpCode);
58044+#else
58045+ /*
58046+ ** Reset own bit we have to do this in order to detect a overflow
58047+ */
58048+ STLE_SET_OPC(pLE, SW_OWNER);
58049+#endif
58050+ } /* while (OWN_OF_FIRST_LE(&pAC->StatusLETable) == HW_OWNER) */
58051+
58052+ /*
58053+ ** Now handle any new transmit complete
58054+ */
58055+ if (NewDone) {
58056+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
58057+ ("Done Index for Tx BMU has been changed\n"));
58058+ for (Port = 0; Port < pAC->GIni.GIMacsFound; Port++) {
58059+ /*
58060+ ** Do we have a new Done idx ?
58061+ */
58062+ if (DoneTxA[Port] != GET_DONE_INDEX(&pAC->TxPort[Port][0].TxALET)) {
58063+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
58064+ ("Check TxA%d\n", Port + 1));
58065+ CheckForSendComplete(pAC, pAC->IoBase, Port,
58066+ &(pAC->TxPort[Port][0].TxAQ_working),
58067+ &pAC->TxPort[Port][0].TxALET,
58068+ DoneTxA[Port]);
58069+ } else {
58070+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
58071+ ("No changes for TxA%d\n", Port + 1));
58072+ }
58073+#if USE_SYNC_TX_QUEUE
58074+ if (HW_SYNC_TX_SUPPORTED(pAC)) {
58075+ /*
58076+ ** Do we have a new Done idx ?
58077+ */
58078+ if (DoneTxS[Port] !=
58079+ GET_DONE_INDEX(&pAC->TxPort[Port][0].TxSLET)) {
58080+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
58081+ SK_DBGCAT_DRV_INT_SRC,
58082+ ("Check TxS%d\n", Port));
58083+ CheckForSendComplete(pAC, pAC->IoBase, Port,
58084+ &(pAC->TxPort[Port][0].TxSQ_working),
58085+ &pAC->TxPort[Port][0].TxSLET,
58086+ DoneTxS[Port]);
58087+ } else {
58088+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
58089+ SK_DBGCAT_DRV_INT_SRC,
58090+ ("No changes for TxS%d\n", Port));
58091+ }
58092+ }
58093+#endif
58094+ }
58095+ }
58096+ NewDone = SK_FALSE;
58097+
58098+ /*
58099+ ** Check whether we have to refill our RX table
58100+ */
58101+ if (HW_FEATURE(pAC, HWF_WA_DEV_420)) {
58102+ if (NbrRxBuffersInHW < MAX_NBR_RX_BUFFERS_IN_HW) {
58103+ for (Port = 0; Port < pAC->GIni.GIMacsFound; Port++) {
58104+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
58105+ ("Check for refill of RxBuffers on Port %c\n", 'A' + Port));
58106+ FillReceiveTableYukon2(pAC, pAC->IoBase, Port);
58107+ }
58108+ }
58109+ } else {
58110+ for (Port = 0; Port < pAC->GIni.GIMacsFound; Port++) {
58111+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
58112+ ("Check for refill of RxBuffers on Port %c\n", 'A' + Port));
58113+ if (NUM_FREE_LE_IN_TABLE(&pAC->RxPort[Port].RxLET) >= 64) {
58114+ FillReceiveTableYukon2(pAC, pAC->IoBase, Port);
58115+ }
58116+ }
58117+ }
58118+#ifdef CONFIG_SK98LIN_NAPI
58119+ if (*WorkDone >= WorkToDo) {
58120+ break;
58121+ }
58122+#endif
58123+ } while (OWN_OF_FIRST_LE(&pAC->StatusLETable) == HW_OWNER);
58124+
58125+ /*
58126+ ** Clear status BMU
58127+ */
58128+ SK_OUT32(pAC->IoBase, STAT_CTRL, SC_STAT_CLR_IRQ);
58129+
58130+ return(handledStatLE);
58131+} /* HandleStatusLEs */
58132+
58133+/*****************************************************************************
58134+ *
58135+ * AllocateAndInitLETables - allocate memory for the LETable and init
58136+ *
58137+ * Description:
58138+ * This function will allocate space for the LETable and will also
58139+ * initialize them. The size of the tables must have been specified
58140+ * before.
58141+ *
58142+ * Arguments:
58143+ * pAC - A pointer to the adapter context struct.
58144+ *
58145+ * Returns:
58146+ * SK_TRUE - all LETables initialized
58147+ * SK_FALSE - failed
58148+ */
58149+static SK_BOOL AllocateAndInitLETables(
58150+SK_AC *pAC) /* pointer to adapter context */
58151+{
58152+ char *pVirtMemAddr;
58153+ dma_addr_t pPhysMemAddr = 0;
58154+ SK_U32 CurrMac;
58155+ unsigned Size;
58156+ unsigned Aligned;
58157+ unsigned Alignment;
58158+
58159+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
58160+ ("==> AllocateAndInitLETables()\n"));
58161+
58162+ /*
58163+ ** Determine how much memory we need with respect to alignment
58164+ */
58165+ Alignment = MAX_LEN_OF_LE_TAB;
58166+ Size = 0;
58167+ for (CurrMac = 0; CurrMac < pAC->GIni.GIMacsFound; CurrMac++) {
58168+ SK_ALIGN_SIZE(LE_TAB_SIZE(RX_MAX_LE), Alignment, Aligned);
58169+ Size += Aligned;
58170+ SK_ALIGN_SIZE(LE_TAB_SIZE(TXA_MAX_LE), Alignment, Aligned);
58171+ Size += Aligned;
58172+ SK_ALIGN_SIZE(LE_TAB_SIZE(TXS_MAX_LE), Alignment, Aligned);
58173+ Size += Aligned;
58174+ }
58175+ SK_ALIGN_SIZE(LE_TAB_SIZE(ST_MAX_LE), Alignment, Aligned);
58176+ Size += Aligned;
58177+ Size += Alignment;
58178+ pAC->SizeOfAlignedLETables = Size;
58179+
58180+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
58181+ ("Need %08x bytes in total\n", Size));
58182+
58183+ /*
58184+ ** Allocate the memory
58185+ */
58186+ pVirtMemAddr = pci_alloc_consistent(pAC->PciDev, Size, &pPhysMemAddr);
58187+ if (pVirtMemAddr == NULL) {
58188+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV,
58189+ SK_DBGCAT_INIT | SK_DBGCAT_DRV_ERROR,
58190+ ("AllocateAndInitLETables: kernel malloc failed!\n"));
58191+ return (SK_FALSE);
58192+ }
58193+
58194+ /*
58195+ ** Initialize the memory
58196+ */
58197+ SK_MEMSET(pVirtMemAddr, 0, Size);
58198+ ALIGN_ADDR(pVirtMemAddr, Alignment); /* Macro defined in skgew.h */
58199+
58200+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
58201+ ("Virtual address of LETab is %8p!\n", pVirtMemAddr));
58202+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
58203+ ("Phys address of LETab is %8p!\n", (void *) pPhysMemAddr));
58204+
58205+ for (CurrMac = 0; CurrMac < pAC->GIni.GIMacsFound; CurrMac++) {
58206+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
58207+ ("RxLeTable for Port %c", 'A' + CurrMac));
58208+ SkGeY2InitSingleLETable(
58209+ pAC,
58210+ &pAC->RxPort[CurrMac].RxLET,
58211+ RX_MAX_LE,
58212+ pVirtMemAddr,
58213+ (SK_U32) (pPhysMemAddr & 0xffffffff),
58214+ (SK_U32) (((SK_U64) pPhysMemAddr) >> 32));
58215+
58216+ SK_ALIGN_SIZE(LE_TAB_SIZE(RX_MAX_LE), Alignment, Aligned);
58217+ pVirtMemAddr += Aligned;
58218+ pPhysMemAddr += Aligned;
58219+
58220+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
58221+ ("TxALeTable for Port %c", 'A' + CurrMac));
58222+ SkGeY2InitSingleLETable(
58223+ pAC,
58224+ &pAC->TxPort[CurrMac][0].TxALET,
58225+ TXA_MAX_LE,
58226+ pVirtMemAddr,
58227+ (SK_U32) (pPhysMemAddr & 0xffffffff),
58228+ (SK_U32) (((SK_U64) pPhysMemAddr) >> 32));
58229+
58230+ SK_ALIGN_SIZE(LE_TAB_SIZE(TXA_MAX_LE), Alignment, Aligned);
58231+ pVirtMemAddr += Aligned;
58232+ pPhysMemAddr += Aligned;
58233+
58234+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
58235+ ("TxSLeTable for Port %c", 'A' + CurrMac));
58236+ SkGeY2InitSingleLETable(
58237+ pAC,
58238+ &pAC->TxPort[CurrMac][0].TxSLET,
58239+ TXS_MAX_LE,
58240+ pVirtMemAddr,
58241+ (SK_U32) (pPhysMemAddr & 0xffffffff),
58242+ (SK_U32) (((SK_U64) pPhysMemAddr) >> 32));
58243+
58244+ SK_ALIGN_SIZE(LE_TAB_SIZE(TXS_MAX_LE), Alignment, Aligned);
58245+ pVirtMemAddr += Aligned;
58246+ pPhysMemAddr += Aligned;
58247+ }
58248+
58249+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,("StLeTable"));
58250+
58251+ SkGeY2InitSingleLETable(
58252+ pAC,
58253+ &pAC->StatusLETable,
58254+ ST_MAX_LE,
58255+ pVirtMemAddr,
58256+ (SK_U32) (pPhysMemAddr & 0xffffffff),
58257+ (SK_U32) (((SK_U64) pPhysMemAddr) >> 32));
58258+
58259+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
58260+ ("<== AllocateAndInitLETables(OK)\n"));
58261+ return(SK_TRUE);
58262+} /* AllocateAndInitLETables */
58263+
58264+/*****************************************************************************
58265+ *
58266+ * AllocatePacketBuffersYukon2 - allocate packet and fragment buffers
58267+ *
58268+ * Description:
58269+ * This function will allocate space for the packets and fragments
58270+ *
58271+ * Arguments:
58272+ * pAC - A pointer to the adapter context struct.
58273+ *
58274+ * Returns:
58275+ * SK_TRUE - Memory was allocated correctly
58276+ * SK_FALSE - An error occured
58277+ */
58278+static SK_BOOL AllocatePacketBuffersYukon2(
58279+SK_AC *pAC) /* pointer to adapter context */
58280+{
58281+ SK_PACKET *pRxPacket;
58282+ SK_PACKET *pTxPacket;
58283+ SK_U32 CurrBuff;
58284+ SK_U32 CurrMac;
58285+ unsigned long Flags; /* needed for POP/PUSH functions */
58286+
58287+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
58288+ ("==> AllocatePacketBuffersYukon2()"));
58289+
58290+ for (CurrMac = 0; CurrMac < pAC->GIni.GIMacsFound; CurrMac++) {
58291+ /*
58292+ ** Allocate RX packet space, initialize the packets and
58293+ ** add them to the RX waiting queue. Waiting queue means
58294+ ** that packet and fragment are initialized, but no sk_buff
58295+ ** has been assigned to it yet.
58296+ */
58297+ pAC->RxPort[CurrMac].ReceivePacketTable =
58298+ kmalloc((RX_MAX_NBR_BUFFERS * sizeof(SK_PACKET)), GFP_KERNEL);
58299+
58300+ if (pAC->RxPort[CurrMac].ReceivePacketTable == NULL) {
58301+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_INIT | SK_DBGCAT_DRV_ERROR,
58302+ ("AllocatePacketBuffersYukon2: no mem RxPkts (port %i)",CurrMac));
58303+ break;
58304+ } else {
58305+ SK_MEMSET(pAC->RxPort[CurrMac].ReceivePacketTable, 0,
58306+ (RX_MAX_NBR_BUFFERS * sizeof(SK_PACKET)));
58307+
58308+ pRxPacket = pAC->RxPort[CurrMac].ReceivePacketTable;
58309+
58310+ for (CurrBuff=0;CurrBuff<RX_MAX_NBR_BUFFERS;CurrBuff++) {
58311+ pRxPacket->pFrag = &(pRxPacket->FragArray[0]);
58312+ pRxPacket->NumFrags = 1;
58313+ PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->RxPort[CurrMac].RxQ_waiting, pRxPacket);
58314+ pRxPacket++;
58315+ }
58316+ }
58317+
58318+ /*
58319+ ** Allocate TX packet space, initialize the packets and
58320+ ** add them to the TX free queue. Free queue means that
58321+ ** packet is available and initialized, but no fragment
58322+ ** has been assigned to it. (Must be done at TX side)
58323+ */
58324+ pAC->TxPort[CurrMac][0].TransmitPacketTable =
58325+ kmalloc((TX_MAX_NBR_BUFFERS * sizeof(SK_PACKET)), GFP_KERNEL);
58326+
58327+ if (pAC->TxPort[CurrMac][0].TransmitPacketTable == NULL) {
58328+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_INIT | SK_DBGCAT_DRV_ERROR,
58329+ ("AllocatePacketBuffersYukon2: no mem TxPkts (port %i)",CurrMac));
58330+ kfree(pAC->RxPort[CurrMac].ReceivePacketTable);
58331+ return(SK_FALSE);
58332+ } else {
58333+ SK_MEMSET(pAC->TxPort[CurrMac][0].TransmitPacketTable, 0,
58334+ (TX_MAX_NBR_BUFFERS * sizeof(SK_PACKET)));
58335+
58336+ pTxPacket = pAC->TxPort[CurrMac][0].TransmitPacketTable;
58337+
58338+ for (CurrBuff=0;CurrBuff<TX_MAX_NBR_BUFFERS;CurrBuff++) {
58339+ PUSH_PKT_AS_LAST_IN_QUEUE(&pAC->TxPort[CurrMac][0].TxQ_free, pTxPacket);
58340+ pTxPacket++;
58341+ }
58342+ }
58343+ } /* end for (CurrMac = 0; CurrMac < pAC->GIni.GIMacsFound; CurrMac++) */
58344+
58345+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_INIT,
58346+ ("<== AllocatePacketBuffersYukon2 (OK)\n"));
58347+ return(SK_TRUE);
58348+
58349+} /* AllocatePacketBuffersYukon2 */
58350+
58351+/*****************************************************************************
58352+ *
58353+ * FreeLETables - release allocated memory of LETables
58354+ *
58355+ * Description:
58356+ * This function will free all resources of the LETables
58357+ *
58358+ * Arguments:
58359+ * pAC - A pointer to the adapter context struct.
58360+ *
58361+ * Returns: N/A
58362+ */
58363+static void FreeLETables(
58364+SK_AC *pAC) /* pointer to adapter control context */
58365+{
58366+ dma_addr_t pPhysMemAddr;
58367+ char *pVirtMemAddr;
58368+
58369+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
58370+ ("==> FreeLETables()\n"));
58371+
58372+ /*
58373+ ** The RxLETable is the first of all LET.
58374+ ** Therefore we can use its address for the input
58375+ ** of the free function.
58376+ */
58377+ pVirtMemAddr = (char *) pAC->RxPort[0].RxLET.pLETab;
58378+ pPhysMemAddr = (((SK_U64) pAC->RxPort[0].RxLET.pPhyLETABHigh << (SK_U64) 32) |
58379+ ((SK_U64) pAC->RxPort[0].RxLET.pPhyLETABLow));
58380+
58381+ /* free continuous memory */
58382+ pci_free_consistent(pAC->PciDev, pAC->SizeOfAlignedLETables,
58383+ pVirtMemAddr, pPhysMemAddr);
58384+
58385+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
58386+ ("<== FreeLETables()\n"));
58387+} /* FreeLETables */
58388+
58389+/*****************************************************************************
58390+ *
58391+ * FreePacketBuffers - free's all packet buffers of an adapter
58392+ *
58393+ * Description:
58394+ * This function will free all previously allocated memory of the
58395+ * packet buffers.
58396+ *
58397+ * Arguments:
58398+ * pAC - A pointer to the adapter context struct.
58399+ *
58400+ * Returns: N/A
58401+ */
58402+static void FreePacketBuffers(
58403+SK_AC *pAC) /* pointer to adapter control context */
58404+{
58405+ int Port;
58406+
58407+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
58408+ ("==> FreePacketBuffers()\n"));
58409+
58410+ for (Port = 0; Port < pAC->GIni.GIMacsFound; Port++) {
58411+ kfree(pAC->RxPort[Port].ReceivePacketTable);
58412+ kfree(pAC->TxPort[Port][0].TransmitPacketTable);
58413+ }
58414+
58415+ SK_DBG_MSG(pAC, SK_DBGMOD_DRV, SK_DBGCAT_DRV_MSG,
58416+ ("<== FreePacketBuffers()\n"));
58417+} /* FreePacketBuffers */
58418+
58419+/*****************************************************************************
58420+ *
58421+ * AllocAndMapRxBuffer - fill one buffer into the receive packet/fragment
58422+ *
58423+ * Description:
58424+ * The function allocates a new receive buffer and assigns it to the
58425+ * the passsed receive packet/fragment
58426+ *
58427+ * Returns:
58428+ * SK_TRUE - a buffer was allocated and assigned
58429+ * SK_FALSE - a buffer could not be added
58430+ */
58431+static SK_BOOL AllocAndMapRxBuffer(
58432+SK_AC *pAC, /* pointer to the adapter control context */
58433+SK_PACKET *pSkPacket, /* pointer to packet that is to fill */
58434+int Port) /* port the packet belongs to */
58435+{
58436+ struct sk_buff *pMsgBlock; /* pointer to a new message block */
58437+ SK_U64 PhysAddr; /* physical address of a rx buffer */
58438+
58439+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
58440+ ("--> AllocAndMapRxBuffer (Port: %i)\n", Port));
58441+
58442+ pMsgBlock = alloc_skb(pAC->RxPort[Port].RxBufSize, GFP_ATOMIC);
58443+ if (pMsgBlock == NULL) {
58444+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
58445+ SK_DBGCAT_DRV_RX_PROGRESS | SK_DBGCAT_DRV_ERROR,
58446+ ("%s: Allocation of rx buffer failed !\n",
58447+ pAC->dev[Port]->name));
58448+ SK_PNMI_CNT_NO_RX_BUF(pAC, pAC->RxPort[Port].PortIndex);
58449+ return(SK_FALSE);
58450+ }
58451+ skb_reserve(pMsgBlock, 8);
58452+
58453+ PhysAddr = (SK_U64) pci_map_page(pAC->PciDev,
58454+ virt_to_page(pMsgBlock->data),
58455+ ((unsigned long) pMsgBlock->data &
58456+ ~PAGE_MASK),
58457+ pAC->RxPort[Port].RxBufSize,
58458+ PCI_DMA_FROMDEVICE);
58459+
58460+ pSkPacket->pFrag->pVirt = pMsgBlock->data;
58461+ pSkPacket->pFrag->pPhys = PhysAddr;
58462+ pSkPacket->pFrag->FragLen = pAC->RxPort[Port].RxBufSize; /* for correct unmap */
58463+ pSkPacket->pMBuf = pMsgBlock;
58464+ pSkPacket->PacketLen = pAC->RxPort[Port].RxBufSize;
58465+
58466+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_RX_PROGRESS,
58467+ ("<-- AllocAndMapRxBuffer\n"));
58468+
58469+ return (SK_TRUE);
58470+} /* AllocAndMapRxBuffer */
58471+
58472+/*******************************************************************************
58473+ *
58474+ * End of file
58475+ *
58476+ ******************************************************************************/
58477diff -ruN linux/drivers/net/sk98lin/sky2le.c linux-new/drivers/net/sk98lin/sky2le.c
58478--- linux/drivers/net/sk98lin/sky2le.c 1970-01-01 01:00:00.000000000 +0100
58479+++ linux-new/drivers/net/sk98lin/sky2le.c 2006-01-18 14:37:24.000000000 +0100
58480@@ -0,0 +1,512 @@
58481+/*****************************************************************************
58482+ *
58483+ * Name: sky2le.c
58484+ * Project: Gigabit Ethernet Adapters, Common Modules
58485+ * Version: $Revision$
58486+ * Date: $Date$
58487+ * Purpose: Functions for handling List Element Tables
58488+ *
58489+ *****************************************************************************/
58490+
58491+/******************************************************************************
58492+ *
58493+ * LICENSE:
58494+ * (C)Copyright 2002-2004 Marvell.
58495+ *
58496+ * This program is free software; you can redistribute it and/or modify
58497+ * it under the terms of the GNU General Public License as published by
58498+ * the Free Software Foundation; either version 2 of the License, or
58499+ * (at your option) any later version.
58500+ * The information in this file is provided "AS IS" without warranty.
58501+ * /LICENSE
58502+ *
58503+ ******************************************************************************/
58504+
58505+/*****************************************************************************
58506+ *
58507+ * Description:
58508+ *
58509+ * This module contains the code necessary for handling List Elements.
58510+ *
58511+ * Supported Gigabit Ethernet Chipsets:
58512+ * Yukon-2 (PCI, PCI-X, PCI-Express)
58513+ *
58514+ * Include File Hierarchy:
58515+ *
58516+ *
58517+ *****************************************************************************/
58518+#include "h/skdrv1st.h"
58519+#include "h/skdrv2nd.h"
58520+
58521+/* defines *******************************************************************/
58522+/* typedefs ******************************************************************/
58523+/* global variables **********************************************************/
58524+/* local variables ***********************************************************/
58525+
58526+#if (defined(DEBUG) || ((!defined(LINT)) && (!defined(SK_SLIM))))
58527+static const char SysKonnectFileId[] =
58528+ "@(#) $Id$ (C) Marvell.";
58529+#endif /* DEBUG || (!LINT && !SK_SLIM) */
58530+
58531+/* function prototypes *******************************************************/
58532+
58533+/*****************************************************************************
58534+ *
58535+ * SkGeY2InitSingleLETable() - initializes a list element table
58536+ *
58537+ * Description:
58538+ * This function will initialize the selected list element table.
58539+ * Should be called once during DriverInit. No InitLevel required.
58540+ *
58541+ * Arguments:
58542+ * pAC - pointer to the adapter context struct.
58543+ * pLETab - pointer to list element table structure
58544+ * NumLE - number of list elements in this table
58545+ * pVMem - virtual address of memory allocated for this LE table
58546+ * PMemLowAddr - physical address of memory to be used for the LE table
58547+ * PMemHighAddr
58548+ *
58549+ * Returns:
58550+ * nothing
58551+ */
58552+void SkGeY2InitSingleLETable(
58553+SK_AC *pAC, /* pointer to adapter context */
58554+SK_LE_TABLE *pLETab, /* pointer to list element table to be initialized */
58555+unsigned int NumLE, /* number of list elements to be filled in tab */
58556+void *pVMem, /* virtual address of memory used for list elements */
58557+SK_U32 PMemLowAddr, /* physical addr of mem used for LE */
58558+SK_U32 PMemHighAddr)
58559+{
58560+ unsigned int i;
58561+
58562+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
58563+ ("==> SkGeY2InitSingleLETable()\n"));
58564+
58565+#ifdef DEBUG
58566+ if (NumLE != 2) { /* not table for polling unit */
58567+ if ((NumLE % MIN_LEN_OF_LE_TAB) != 0 || NumLE > MAX_LEN_OF_LE_TAB) {
58568+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
58569+ ("ERROR: Illegal number of list elements %d\n", NumLE));
58570+ }
58571+ }
58572+#endif /* DEBUG */
58573+
58574+ /* special case: unused list element table */
58575+ if (NumLE == 0) {
58576+ PMemLowAddr = 0;
58577+ PMemHighAddr = 0;
58578+ pVMem = 0;
58579+ }
58580+
58581+ /*
58582+ * in order to get the best possible performance the macros to access
58583+ * list elements use & instead of %
58584+ * this requires the length of LE tables to be a power of 2
58585+ */
58586+
58587+ /*
58588+ * this code guarantees that we use the next power of 2 below the
58589+ * value specified for NumLe - this way some LEs in the table may
58590+ * not be used but the macros work correctly
58591+ * this code does not check for bad values below 128 because in such a
58592+ * case we cannot do anything here
58593+ */
58594+
58595+ if ((NumLE != 2) && (NumLE != 0)) {
58596+ /* no check for polling unit and unused sync Tx */
58597+ i = MIN_LEN_OF_LE_TAB;
58598+ while (NumLE > i) {
58599+ i *= 2;
58600+ if (i > MAX_LEN_OF_LE_TAB) {
58601+ break;
58602+ }
58603+ }
58604+ if (NumLE != i) {
58605+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
58606+ ("ERROR: Illegal number of list elements %d adjusted to %d\n",
58607+ NumLE, (i / 2)));
58608+ NumLE = i / 2;
58609+ }
58610+ }
58611+
58612+ /* set addresses */
58613+ pLETab->pPhyLETABLow = PMemLowAddr;
58614+ pLETab->pPhyLETABHigh = PMemHighAddr;
58615+ pLETab->pLETab = pVMem;
58616+
58617+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
58618+ ("contains %d LEs", NumLE));
58619+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
58620+ (" and starts at virt %08lx and phys %08lx:%08lx\n",
58621+ pVMem, PMemHighAddr, PMemLowAddr));
58622+
58623+ /* initialize indexes */
58624+ pLETab->Done = 0;
58625+ pLETab->Put = 0;
58626+ pLETab->HwPut = 0;
58627+ /* initialize size */
58628+ pLETab->Num = NumLE;
58629+
58630+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
58631+ ("<== SkGeY2InitSingleLETable()\n"));
58632+} /* SkGeY2InitSingleLETable */
58633+
58634+/*****************************************************************************
58635+ *
58636+ * SkGeY2InitPrefetchUnit() - Initialize a Prefetch Unit
58637+ *
58638+ * Description:
58639+ * Calling this function requires an already configured list element
58640+ * table. The prefetch unit to be configured is specified in the parameter
58641+ * 'Queue'. The function is able to initialze the prefetch units of
58642+ * the following queues: Q_R1, Q_R2, Q_XS1, Q_XS2, Q_XA1, Q_XA2.
58643+ * The funcution should be called before SkGeInitPort().
58644+ *
58645+ * Arguments:
58646+ * pAC - pointer to the adapter context struct.
58647+ * IoC - I/O context.
58648+ * Queue - I/O offset of queue e.g. Q_XA1.
58649+ * pLETab - pointer to list element table to be initialized
58650+ *
58651+ * Returns: N/A
58652+ */
58653+void SkGeY2InitPrefetchUnit(
58654+SK_AC *pAC, /* pointer to adapter context */
58655+SK_IOC IoC, /* I/O context */
58656+unsigned int Queue, /* Queue offset for finding the right registers */
58657+SK_LE_TABLE *pLETab) /* pointer to list element table to be initialized */
58658+{
58659+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
58660+ ("==> SkGeY2InitPrefetchUnit()\n"));
58661+
58662+#ifdef DEBUG
58663+ if (Queue != Q_R1 && Queue != Q_R2 && Queue != Q_XS1 &&
58664+ Queue != Q_XS2 && Queue != Q_XA1 && Queue != Q_XA2) {
58665+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_ERR,
58666+ ("ERROR: Illegal queue identifier %x\n", Queue));
58667+ }
58668+#endif /* DEBUG */
58669+
58670+ /* disable the prefetch unit */
58671+ SK_OUT32(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_CTRL_REG), PREF_UNIT_RST_SET);
58672+ SK_OUT32(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_CTRL_REG), PREF_UNIT_RST_CLR);
58673+
58674+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
58675+ ("Base address: %08lx:%08lx\n", pLETab->pPhyLETABHigh,
58676+ pLETab->pPhyLETABLow));
58677+
58678+ /* Set the list base address high part*/
58679+ SK_OUT32(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_ADDR_HI_REG),
58680+ pLETab->pPhyLETABHigh);
58681+
58682+ /* Set the list base address low part */
58683+ SK_OUT32(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_ADDR_LOW_REG),
58684+ pLETab->pPhyLETABLow);
58685+
58686+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
58687+ ("Last index: %d\n", pLETab->Num-1));
58688+
58689+ /* Set the list last index */
58690+ SK_OUT16(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_LAST_IDX_REG),
58691+ (SK_U16)(pLETab->Num - 1));
58692+
58693+ /* turn on prefetch unit */
58694+ SK_OUT32(IoC, Y2_PREF_Q_ADDR(Queue, PREF_UNIT_CTRL_REG), PREF_UNIT_OP_ON);
58695+
58696+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
58697+ ("<== SkGeY2InitPrefetchUnit()\n"));
58698+} /* SkGeY2InitPrefetchUnit */
58699+
58700+
58701+/*****************************************************************************
58702+ *
58703+ * SkGeY2InitStatBmu() - Initialize the Status BMU
58704+ *
58705+ * Description:
58706+ * Calling this function requires an already configured list element
58707+ * table. Ensure the status BMU is only initialized once during
58708+ * DriverInit - InitLevel2 required.
58709+ *
58710+ * Arguments:
58711+ * pAC - pointer to the adapter context struct.
58712+ * IoC - I/O context.
58713+ * pLETab - pointer to status LE table to be initialized
58714+ *
58715+ * Returns: N/A
58716+ */
58717+void SkGeY2InitStatBmu(
58718+SK_AC *pAC, /* pointer to adapter context */
58719+SK_IOC IoC, /* I/O context */
58720+SK_LE_TABLE *pLETab) /* pointer to status LE table */
58721+{
58722+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
58723+ ("==> SkGeY2InitStatBmu()\n"));
58724+
58725+ /* disable the prefetch unit */
58726+ SK_OUT32(IoC, STAT_CTRL, SC_STAT_RST_SET);
58727+ SK_OUT32(IoC, STAT_CTRL, SC_STAT_RST_CLR);
58728+
58729+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
58730+ ("Base address Low: %08lX\n", pLETab->pPhyLETABLow));
58731+
58732+ /* Set the list base address */
58733+ SK_OUT32(IoC, STAT_LIST_ADDR_LO, pLETab->pPhyLETABLow);
58734+
58735+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
58736+ ("Base address High: %08lX\n", pLETab->pPhyLETABHigh));
58737+
58738+ SK_OUT32(IoC, STAT_LIST_ADDR_HI, pLETab->pPhyLETABHigh);
58739+
58740+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
58741+ ("Last index: %d\n", pLETab->Num - 1));
58742+
58743+ /* Set the list last index */
58744+ SK_OUT16(IoC, STAT_LAST_IDX, (SK_U16)(pLETab->Num - 1));
58745+
58746+ if (HW_FEATURE(pAC, HWF_WA_DEV_43_418)) {
58747+
58748+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
58749+ ("Set Tx index threshold\n"));
58750+ /* WA for dev. #4.3 */
58751+ SK_OUT16(IoC, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK);
58752+
58753+ /* set Status-FIFO watermark */
58754+ SK_OUT8(IoC, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
58755+
58756+ /* set Status-FIFO ISR watermark */
58757+ SK_OUT8(IoC, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
58758+
58759+ /* WA for dev. #4.3 and #4.18 */
58760+ /* set Status-FIFO Tx timer init value */
58761+ SK_OUT32(IoC, STAT_TX_TIMER_INI, HW_MS_TO_TICKS(pAC, 10));
58762+ }
58763+ else {
58764+ /*
58765+ * Further settings may be added if required...
58766+ * 1) Status-FIFO watermark (STAT_FIFO_WM, STAT_FIFO_ISR_WM)
58767+ * 2) Status-FIFO timer values (STAT_TX_TIMER_INI,
58768+ * STAT_LEV_TIMER_INI and STAT_ISR_TIMER_INI)
58769+ * but tests shows that the default values give the best results,
58770+ * therefore the defaults are used.
58771+ */
58772+
58773+ /*
58774+ * Theses settings should avoid the
58775+ * temporary hanging of the status BMU.
58776+ * May be not all required... still under investigation...
58777+ */
58778+ SK_OUT16(IoC, STAT_TX_IDX_TH, 0x000a);
58779+
58780+ /* set Status-FIFO watermark */
58781+ SK_OUT8(IoC, STAT_FIFO_WM, 0x10);
58782+
58783+
58784+ /* set Status-FIFO ISR watermark */
58785+ if (HW_FEATURE(pAC, HWF_WA_DEV_4109)) {
58786+ SK_OUT8(IoC, STAT_FIFO_ISR_WM, 0x10);
58787+ }
58788+ else {
58789+ SK_OUT8(IoC, STAT_FIFO_ISR_WM, 0x04);
58790+ }
58791+
58792+ SK_OUT32(IoC, STAT_ISR_TIMER_INI, 0x0190);
58793+ }
58794+
58795+ /* start Status-FIFO timer */
58796+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
58797+ ("Start Status FiFo timer\n"));
58798+
58799+ /* enable the prefetch unit */
58800+ /* operational bit not functional for Yukon-EC, but fixed in Yukon-2 */
58801+ SK_OUT32(IoC, STAT_CTRL, SC_STAT_OP_ON);
58802+
58803+ /* start Status-FIFO timer */
58804+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
58805+ ("Start Status FiFo timer\n"));
58806+
58807+ SK_OUT8(IoC, STAT_TX_TIMER_CTRL, TIM_START);
58808+ SK_OUT8(IoC, STAT_LEV_TIMER_CTRL, TIM_START);
58809+ SK_OUT8(IoC, STAT_ISR_TIMER_CTRL, TIM_START);
58810+
58811+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
58812+ ("<== SkGeY2InitStatBmu()\n"));
58813+} /* SkGeY2InitStatBmu */
58814+
58815+#ifdef USE_POLLING_UNIT
58816+/*****************************************************************************
58817+ *
58818+ * SkGeY2InitPollUnit() - Initialize the Polling Unit
58819+ *
58820+ * Description:
58821+ * This function will write the data of one polling LE table into the
58822+ * adapter.
58823+ *
58824+ * Arguments:
58825+ * pAC - pointer to the adapter context struct.
58826+ * IoC - I/O context.
58827+ * pLETab - pointer to polling LE table to be initialized
58828+ *
58829+ * Returns: N/A
58830+ */
58831+void SkGeY2InitPollUnit(
58832+SK_AC *pAC, /* pointer to adapter context */
58833+SK_IOC IoC, /* I/O context */
58834+SK_LE_TABLE *pLETab) /* pointer to polling LE table */
58835+{
58836+ SK_HWLE *pLE;
58837+ int i;
58838+#ifdef VCPU
58839+ VCPU_VARS();
58840+#endif /* VCPU */
58841+
58842+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
58843+ ("==> SkGeY2InitPollUnit()\n"));
58844+
58845+#ifdef VCPU
58846+ for (i = 0; i < SK_MAX_MACS; i++) {
58847+ GET_PO_LE(pLE, pLETab, i);
58848+ VCPU_START_AND_COPY_LE();
58849+ /* initialize polling LE but leave indexes invalid */
58850+ POLE_SET_OPC(pLE, OP_PUTIDX | HW_OWNER);
58851+ POLE_SET_LINK(pLE, i);
58852+ POLE_SET_RXIDX(pLE, 0);
58853+ POLE_SET_TXAIDX(pLE, 0);
58854+ POLE_SET_TXSIDX(pLE, 0);
58855+ VCPU_WRITE_LE();
58856+ SK_DBG_DUMP_PO_LE(pLE);
58857+ }
58858+#endif /* VCPU */
58859+
58860+ /* disable the polling unit */
58861+ SK_OUT32(IoC, POLL_CTRL, PC_POLL_RST_SET);
58862+ SK_OUT32(IoC, POLL_CTRL, PC_POLL_RST_CLR);
58863+
58864+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
58865+ ("Base address Low: %08lX\n", pLETab->pPhyLETABLow));
58866+
58867+ /* Set the list base address */
58868+ SK_OUT32(IoC, POLL_LIST_ADDR_LO, pLETab->pPhyLETABLow);
58869+
58870+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
58871+ ("Base address High: %08lX\n", pLETab->pPhyLETABHigh));
58872+
58873+ SK_OUT32(IoC, POLL_LIST_ADDR_HI, pLETab->pPhyLETABHigh);
58874+
58875+ /* we don't need to write the last index - it is hardwired to 1 */
58876+
58877+ /* enable the prefetch unit */
58878+ SK_OUT32(IoC, POLL_CTRL, PC_POLL_OP_ON);
58879+
58880+ /*
58881+ * now we have to start the descriptor poll timer because it triggers
58882+ * the polling unit
58883+ */
58884+
58885+ /*
58886+ * still playing with the value (timer runs at 125 MHz)
58887+ * descriptor poll timer is enabled by GeInit
58888+ */
58889+ SK_OUT32(IoC, B28_DPT_INI,
58890+ (SK_DPOLL_DEF_Y2 * (SK_U32)pAC->GIni.GIHstClkFact / 100));
58891+
58892+ SK_OUT8(IoC, B28_DPT_CTRL, TIM_START);
58893+
58894+ SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
58895+ ("<== SkGeY2InitPollUnit()\n"));
58896+} /* SkGeY2InitPollUnit */
58897+#endif /* USE_POLLING_UNIT */
58898+
58899+
58900+/******************************************************************************
58901+ *
58902+ * SkGeY2SetPutIndex
58903+ *
58904+ * Description:
58905+ * This function is writing the Done index of a transmit
58906+ * list element table.
58907+ *
58908+ * Notes:
58909+ * Dev. Issue 4.2
58910+ *
58911+ * Returns: N/A
58912+ */
58913+void SkGeY2SetPutIndex(
58914+SK_AC *pAC, /* pointer to adapter context */
58915+SK_IOC IoC, /* pointer to the IO context */
58916+SK_U32 StartAddrPrefetchUnit, /* start address of the prefetch unit */
58917+SK_LE_TABLE *pLETab) /* list element table to work with */
58918+{
58919+ unsigned int Put;
58920+ SK_U16 EndOfListIndex;
58921+ SK_U16 HwGetIndex;
58922+ SK_U16 HwPutIndex;
58923+
58924+ /* set put index we would like to write */
58925+ Put = GET_PUT_IDX(pLETab);
58926+
58927+ /*
58928+ * in this case we wrap around
58929+ * new put is lower than last put given to hw
58930+ */
58931+ if (Put < pLETab->HwPut) {
58932+
58933+ /* set put index = last index of list */
58934+ EndOfListIndex = (NUM_LE_IN_TABLE(pLETab)-1);
58935+
58936+ /* read get index of hw prefetch unit */
58937+ SK_IN16(IoC, (StartAddrPrefetchUnit + PREF_UNIT_GET_IDX_REG),
58938+ &HwGetIndex);
58939+
58940+ /* read put index of hw prefetch unit */
58941+ SK_IN16(IoC, (StartAddrPrefetchUnit + PREF_UNIT_PUT_IDX_REG),
58942+ &HwPutIndex);
58943+
58944+ /* prefetch unit reached end of list */
58945+ /* prefetch unit reached first list element */
58946+ if (HwGetIndex == 0) {
58947+ /* restore watermark */
58948+ SK_OUT8(IoC, StartAddrPrefetchUnit + PREF_UNIT_FIFO_WM_REG, 0xe0U);
58949+ /* write put index */
58950+ SK_OUT16(IoC, StartAddrPrefetchUnit + PREF_UNIT_PUT_IDX_REG,
58951+ (SK_U16)Put);
58952+
58953+ /* remember put index we wrote to hw */
58954+ pLETab->HwPut = Put;
58955+ }
58956+ else if (HwGetIndex == EndOfListIndex) {
58957+ /* set watermark to one list element */
58958+ SK_OUT8(IoC, StartAddrPrefetchUnit + PREF_UNIT_FIFO_WM_REG, 8);
58959+ /* set put index to first list element */
58960+ SK_OUT16(IoC, StartAddrPrefetchUnit + PREF_UNIT_PUT_IDX_REG, 0);
58961+ }
58962+ /* prefetch unit did not reach end of list yet */
58963+ /* and we did not write put index to end of list yet */
58964+ else if ((HwPutIndex != EndOfListIndex) &&
58965+ (HwGetIndex != EndOfListIndex)) {
58966+ /* write put index */
58967+ SK_OUT16(IoC, StartAddrPrefetchUnit + PREF_UNIT_PUT_IDX_REG,
58968+ EndOfListIndex);
58969+ }
58970+ else {
58971+ /* do nothing */
58972+ }
58973+ }
58974+ else {
58975+#ifdef XXX /* leads in to problems in the Windows Driver */
58976+ if (Put != pLETab->HwPut) {
58977+ /* write put index */
58978+ SK_OUT16(IoC, StartAddrPrefetchUnit + PREF_UNIT_PUT_IDX_REG,
58979+ (SK_U16)Put);
58980+ /* update put index */
58981+ UPDATE_HWPUT_IDX(pLETab);
58982+ }
58983+#else
58984+ /* write put index */
58985+ SK_OUT16(IoC, StartAddrPrefetchUnit + PREF_UNIT_PUT_IDX_REG,
58986+ (SK_U16)Put);
58987+ /* update put index */
58988+ UPDATE_HWPUT_IDX(pLETab);
58989+#endif
58990+ }
58991+} /* SkGeY2SetPutIndex */
58992+
58993diff -ruN linux/Documentation/networking/sk98lin.txt linux-new/Documentation/networking/sk98lin.txt
58994--- linux/Documentation/networking/sk98lin.txt 2006-04-11 19:19:28.000000000 +0200
58995+++ linux-new/drivers/net/sk98lin/sk98lin.txt 2006-01-18 14:37:24.000000000 +0100
58996@@ -1,38 +1,56 @@
58997-(C)Copyright 1999-2004 Marvell(R).
58998-All rights reserved
58999-===========================================================================
59000+(C)Copyright 1999-2006 Marvell(R).
59001+All rights reserved.
59002+================================================================================
59003
59004-sk98lin.txt created 13-Feb-2004
59005+sk98lin.txt created 18-Jan-2006
59006
59007-Readme File for sk98lin v6.23
59008-Marvell Yukon/SysKonnect SK-98xx Gigabit Ethernet Adapter family driver for LINUX
59009+Readme File for sk98lin v8.31.2.3
59010+Marvell Yukon/SysKonnect SK-98xx Gigabit Ethernet Adapter driver for LINUX
59011
59012 This file contains
59013 1 Overview
59014- 2 Required Files
59015- 3 Installation
59016- 3.1 Driver Installation
59017- 3.2 Inclusion of adapter at system start
59018- 4 Driver Parameters
59019- 4.1 Per-Port Parameters
59020- 4.2 Adapter Parameters
59021- 5 Large Frame Support
59022- 6 VLAN and Link Aggregation Support (IEEE 802.1, 802.1q, 802.3ad)
59023- 7 Troubleshooting
59024+ 2 Supported Functions
59025+ 3 Required Files
59026+ 4 Installation
59027+ 4.1 Driver Installation
59028+ 4.2 Inclusion of adapter at system start
59029+ 5 Driver Parameters
59030+ 5.1 Per-Port Parameters
59031+ 5.2 Adapter Parameters
59032+ 6 Ethtool Support
59033+ 7 Large Frame Support
59034+ 8 VLAN and Link Aggregation Support (IEEE 802.1, 802.1q, 802.3ad)
59035+ 9 Wake on Lan support
59036+10 Troubleshooting
59037
59038-===========================================================================
59039+================================================================================
59040
59041
59042 1 Overview
59043 ===========
59044
59045-The sk98lin driver supports the Marvell Yukon and SysKonnect
59046-SK-98xx/SK-95xx compliant Gigabit Ethernet Adapter on Linux. It has
59047-been tested with Linux on Intel/x86 machines.
59048+The sk98lin driver supports the Marvell Yukon, Yukon EC/FE, Yukon 2
59049+and SysKonnect SK-98xx/SK-95xx compliant Gigabit Ethernet Adapter on Linux.
59050+It has been tested with Linux on Intel/x86, x86_64 and IA64 machines.
59051 ***
59052
59053+2 Supported Functions
59054+======================
59055+
59056+The following functions are supported by the driver:
59057
59058-2 Required Files
59059+ NOTE 1: The hardware support depends on the used card
59060+
59061+ - RX/TX HW Checksum
59062+ - Hardware interrupt moderation (static/dynamic)
59063+ - Transmit poll
59064+ - Zerocopy/Scatter-Gather
59065+ - Ethtool support
59066+ - Wake on Lan (Magic Packet only) (From suspend and APM only)
59067+ - DualNet
59068+
59069+
59070+3 Required Files
59071 =================
59072
59073 The linux kernel source.
59074@@ -40,16 +58,14 @@
59075 ***
59076
59077
59078-3 Installation
59079+4 Installation
59080 ===============
59081
59082 It is recommended to download the latest version of the driver from the
59083-SysKonnect web site www.syskonnect.com. If you have downloaded the latest
59084-driver, the Linux kernel has to be patched before the driver can be
59085-installed. For details on how to patch a Linux kernel, refer to the
59086-patch.txt file.
59087+SysKonnect web site www.syskonnect.com. For details on Installation
59088+Instructions for sk98lin Driver, please refer to the README.txt file.
59089
59090-3.1 Driver Installation
59091+4.1 Driver Installation
59092 ------------------------
59093
59094 The following steps describe the actions that are required to install
59095@@ -91,7 +107,7 @@
59096 with (M)
59097 5. Execute the command "make modules".
59098 6. Execute the command "make modules_install".
59099- The appropriate modules will be installed.
59100+ The appropiate modules will be installed.
59101 7. Reboot your system.
59102
59103
59104@@ -110,13 +126,13 @@
59105
59106 NOTE 1: If you have more than one Marvell Yukon or SysKonnect SK-98xx
59107 adapter installed, the adapters will be listed as 'eth0',
59108- 'eth1', 'eth2', etc.
59109- For each adapter, repeat steps 3 and 4 below.
59110+ 'eth1', 'eth2', etc.
59111+ For each adapter, repeat steps 3 and 4 below.
59112
59113 NOTE 2: If you have other Ethernet adapters installed, your Marvell
59114 Yukon or SysKonnect SK-98xx adapter will be mapped to the
59115- next available number, e.g. 'eth1'. The mapping is executed
59116- automatically.
59117+ next available number, e.g. 'eth1'. The mapping is executed
59118+ automatically.
59119 The module installation message (displayed either in a system
59120 log file or on the console) prints a line for each adapter
59121 found containing the corresponding 'ethX'.
59122@@ -153,7 +169,7 @@
59123 1. Execute the command "ifconfig eth0 down".
59124 2. Execute the command "rmmod sk98lin".
59125
59126-3.2 Inclusion of adapter at system start
59127+4.2 Inclusion of adapter at system start
59128 -----------------------------------------
59129
59130 Since a large number of different Linux distributions are
59131@@ -165,7 +181,8 @@
59132
59133 ***
59134
59135-4 Driver Parameters
59136+
59137+5 Driver Parameters
59138 ====================
59139
59140 Parameters can be set at the command line after the module has been
59141@@ -174,7 +191,7 @@
59142 to the driver module.
59143
59144 If you use the kernel module loader, you can set driver parameters
59145-in the file /etc/modprobe.conf (or /etc/modules.conf in 2.4 or earlier).
59146+in the file /etc/modules.conf (or old name: /etc/conf.modules).
59147 To set the driver parameters in this file, proceed as follows:
59148
59149 1. Insert a line of the form :
59150@@ -208,7 +225,7 @@
59151 more adapters, adjust this and recompile.
59152
59153
59154-4.1 Per-Port Parameters
59155+5.1 Per-Port Parameters
59156 ------------------------
59157
59158 These settings are available for each port on the adapter.
59159@@ -245,7 +262,7 @@
59160 This parameters is only relevant if auto-negotiation for this port is
59161 not set to "Sense". If auto-negotiation is set to "On", all three values
59162 are possible. If it is set to "Off", only "Full" and "Half" are allowed.
59163-This parameter is useful if your link partner does not support all
59164+This parameter is usefull if your link partner does not support all
59165 possible combinations.
59166
59167 Flow Control
59168@@ -282,7 +299,7 @@
59169 with this parameter.
59170
59171
59172-4.2 Adapter Parameters
59173+5.2 Adapter Parameters
59174 -----------------------
59175
59176 Connection Type (SK-98xx V2.0 copper adapters only)
59177@@ -379,7 +396,6 @@
59178 is tremendous. On the other hand, selecting a very short moderation time might
59179 compensate the use of any moderation being applied.
59180
59181-
59182 Preferred Port
59183 --------------
59184 Parameter: PrefPort
59185@@ -394,7 +410,7 @@
59186 ------------------------------------------------
59187 Parameter: RlmtMode
59188 Values: CheckLinkState,CheckLocalPort, CheckSeg, DualNet
59189-Default: CheckLinkState
59190+Default: CheckLinkState (DualNet on dual port adapters)
59191
59192 RLMT monitors the status of the port. If the link of the active port
59193 fails, RLMT switches immediately to the standby link. The virtual link is
59194@@ -429,10 +445,94 @@
59195 where a network path between the ports on one adapter exists.
59196 Moreover, they are not designed to work where adapters are connected
59197 back-to-back.
59198+
59199+LowLatency
59200+----------
59201+Parameter: LowLatency
59202+Values: On, Off
59203+Default: Off
59204+
59205+This is used to reduce the packet latency time of the adapter. Setting the
59206+LowLatency parameter to 'On' forces the adapter to pass any received packet
59207+immediately to upper network layers and to send out any transmit packet as
59208+fast as possible.
59209+
59210+NOTE 1: The system load increases if LowLatency is set to 'On' and a lot
59211+ of data packets are transmitted and received.
59212+
59213+NOTE 2: This parameter is only used on adapters which are based on
59214+ PCI Express compatible chipsets.
59215 ***
59216
59217
59218-5 Large Frame Support
59219+6 Ethtool Support
59220+==================
59221+
59222+The sk98lin driver provides built-in ethtool support. The ethtool
59223+can be used to display or modify interface specific configurations.
59224+
59225+Ethtool commands are invoked using a single parameter which reflects
59226+the requested ethtool command plus an optional number of parameters
59227+which belong to the desired command.
59228+
59229+It is not the intention of this section to explain the ethtool command
59230+line tool and all its options. For further information refer to the
59231+manpage of the ethtool. This sections describes only the sk98lin
59232+driver supported ethtool commands.
59233+
59234+Pause Parameters
59235+----------------
59236+Query command: -a
59237+Set command: -A [autoneg on|off] [rx on|off] [tx on|off]
59238+Sample: ethtool -A eth0 rx off tx off
59239+
59240+Coalescing Parameters
59241+---------------------
59242+Query command: -c
59243+Set command: -C [sample-interval I]
59244+ [rx-usecs N] [tx-usecs N]
59245+ [rx-usecs-low N] [tx-usecs-low N]
59246+ [rx-usecs-high N] [tx-usecs-high N]
59247+Parameter: I = Length of sample interval, in seconds
59248+ (supported values range from 1...10)
59249+ N = Length of coalescing interval, in microseconds
59250+ (supported values range from 25...33,333)
59251+Sample: ethtool -C eth2 rx-usecs 500 tx-usecs 500
59252+
59253+NOTE: The sk98lin driver does not support different settings
59254+ for the rx and tx interrupt coalescing parameters.
59255+
59256+Driver Information
59257+------------------
59258+Query command: -i
59259+Sample: ethtool -i eth1
59260+
59261+Checksumming Parameters
59262+-----------------------
59263+Query command: -k
59264+Set command: -K [rx on|off] [tx on|off] [sg on|off]
59265+Sample: ethtool -K eth0 sg off
59266+
59267+Locate NIC Command
59268+------------------
59269+Query command: -p [N]
59270+Parameter: N = Amount of time to perform locate NIC command, in seconds
59271+Sample: ethtool -p 10 eth1
59272+
59273+Driver-specific Statistics
59274+--------------------------
59275+Query command: -S
59276+Sample: ethtool -S eth0
59277+
59278+Setting Parameters
59279+------------------
59280+Set command: -s [speed 10|100|1000] [duplex half|full]
59281+ [autoneg on|off] [wol gd]
59282+Sample: ethtool -s eth2 wol d
59283+***
59284+
59285+
59286+7 Large Frame Support
59287 ======================
59288
59289 The driver supports large frames (also called jumbo frames). Using large
59290@@ -444,10 +544,10 @@
59291 ifconfig eth0 mtu 9000
59292 This will only work if you have two adapters connected back-to-back
59293 or if you use a switch that supports large frames. When using a switch,
59294-it should be configured to allow large frames and auto-negotiation should
59295-be set to OFF. The setting must be configured on all adapters that can be
59296-reached by the large frames. If one adapter is not set to receive large
59297-frames, it will simply drop them.
59298+it should be configured to allow large frames. The setting must be
59299+configured on all adapters that can be reached by the large frames.
59300+If one adapter is not set to receive large frames, it will simply drop
59301+them.
59302
59303 You can switch back to the standard ethernet frame size by executing the
59304 following command:
59305@@ -459,7 +559,7 @@
59306 ***
59307
59308
59309-6 VLAN and Link Aggregation Support (IEEE 802.1, 802.1q, 802.3ad)
59310+8 VLAN and Link Aggregation Support (IEEE 802.1, 802.1q, 802.3ad)
59311 ==================================================================
59312
59313 The Marvell Yukon/SysKonnect Linux drivers are able to support VLAN and
59314@@ -477,8 +577,21 @@
59315 cause problems when unloading the driver.
59316
59317
59318-7 Troubleshooting
59319-==================
59320+9 Wake on Lan support
59321+======================
59322+
59323+The sk98lin driver supports wake up from suspend mode with MagicPacket
59324+on APM systems. Wake on Lan support is enabled by default. To disable it
59325+please use the ethtool.
59326+
59327+NOTE 1: APM support has to be enabled in BIOS and in the kernel.
59328+
59329+NOTE 2: Refer to the kernel documentation for additional requirements
59330+ regarding APM support.
59331+
59332+
59333+10 Troubleshooting
59334+===================
59335
59336 If any problems occur during the installation process, check the
59337 following list:
59338diff -ruN linux/drivers/net/Kconfig linux-new/drivers/net/Kconfig
59339--- linux/drivers/net/Kconfig 2006-04-12 18:56:12.000000000 +0200
59340+++ linux-new/drivers/net/Kconfig 2006-04-12 18:59:13.633862750 +0200
59341@@ -2181,22 +2181,32 @@
59342 To compile this driver as a module, choose M here: the module
59343 will be called sky2. This is recommended.
59344
59345+
59346 config SK98LIN
59347 tristate "Marvell Yukon Chipset / SysKonnect SK-98xx Support"
59348 depends on PCI
59349 ---help---
59350 Say Y here if you have a Marvell Yukon or SysKonnect SK-98xx/SK-95xx
59351- compliant Gigabit Ethernet Adapter.
59352-
59353- This driver supports the original Yukon chipset. A cleaner driver is
59354- also available (skge) which seems to work better than this one.
59355-
59356- This driver does not support the newer Yukon2 chipset. A seperate
59357- driver, sky2, is provided to support Yukon2-based adapters.
59358-
59359- The following adapters are supported by this driver:
59360+ compliant Gigabit Ethernet Adapter. The following adapters are supported
59361+ by this driver:
59362 - 3Com 3C940 Gigabit LOM Ethernet Adapter
59363 - 3Com 3C941 Gigabit LOM Ethernet Adapter
59364+ - 88E8021 Marvell 1000 Mbit PCI-X, single Port Copper
59365+ - 88E8021 Marvell 1000 Mbit PCI-X, single Port Fiber LX
59366+ - 88E8021 Marvell 1000 Mbit PCI-X, single Port Fiber SX
59367+ - 88E8022 Marvell 1000 Mbit PCI-X, dual Port Copper
59368+ - 88E8022 Marvell 1000 Mbit PCI-X, dual Port Copper (Gateway)
59369+ - 88E8022 Marvell 1000 Mbit PCI-X, dual Port Fiber LX
59370+ - 88E8022 Marvell 1000 Mbit PCI-X, dual Port Fiber SX
59371+ - 88E8061 Marvell 1000 Mbit PCI-E, single Port Copper
59372+ - 88E8061 Marvell 1000 Mbit PCI-E, single Port Fiber LX
59373+ - 88E8061 Marvell 1000 Mbit PCI-E, single Port Fiber SX
59374+ - 88E8062 Marvell 1000 Mbit PCI-E, dual Port Copper
59375+ - 88E8062 Marvell 1000 Mbit PCI-E, dual Port Copper (Gateway)
59376+ - 88E8062 Marvell 1000 Mbit PCI-E, dual Port Fiber LX
59377+ - 88E8062 Marvell 1000 Mbit PCI-E, dual Port Fiber SX
59378+ - Abocom EFE3K - 10/100 Ethernet Expresscard
59379+ - Abocom EGE5K - Giga Ethernet Expresscard
59380 - Allied Telesyn AT-2970LX Gigabit Ethernet Adapter
59381 - Allied Telesyn AT-2970LX/2SC Gigabit Ethernet Adapter
59382 - Allied Telesyn AT-2970SX Gigabit Ethernet Adapter
59383@@ -2206,31 +2216,82 @@
59384 - Allied Telesyn AT-2971SX Gigabit Ethernet Adapter
59385 - Allied Telesyn AT-2971T Gigabit Ethernet Adapter
59386 - Belkin Gigabit Desktop Card 10/100/1000Base-T Adapter, Copper RJ-45
59387+ - DGE-530T Gigabit Ethernet Adapter
59388+ - DGE-560T Gigabit Ethernet Adapter
59389 - EG1032 v2 Instant Gigabit Network Adapter
59390 - EG1064 v2 Instant Gigabit Network Adapter
59391- - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Abit)
59392- - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Albatron)
59393- - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Asus)
59394- - Marvell 88E8001 Gigabit LOM Ethernet Adapter (ECS)
59395- - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Epox)
59396- - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Foxconn)
59397- - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Gigabyte)
59398- - Marvell 88E8001 Gigabit LOM Ethernet Adapter (Iwill)
59399- - Marvell 88E8050 Gigabit LOM Ethernet Adapter (Intel)
59400+ - Marvell 88E8001 Gigabit Ethernet Controller (Abit)
59401+ - Marvell 88E8001 Gigabit Ethernet Controller (Albatron)
59402+ - Marvell 88E8001 Gigabit Ethernet Controller (Asus)
59403+ - Marvell 88E8001 Gigabit Ethernet Controller (Chaintech)
59404+ - Marvell 88E8001 Gigabit Ethernet Controller (ECS)
59405+ - Marvell 88E8001 Gigabit Ethernet Controller (Epox)
59406+ - Marvell 88E8001 Gigabit Ethernet Controller (Foxconn)
59407+ - Marvell 88E8001 Gigabit Ethernet Controller (Gigabyte)
59408+ - Marvell 88E8001 Gigabit Ethernet Controller (Iwill)
59409+ - Marvell 88E8035 Fast Ethernet Controller (LGE)
59410+ - Marvell 88E8035 Fast Ethernet Controller (Toshiba)
59411+ - Marvell 88E8036 Fast Ethernet Controller (Arima)
59412+ - Marvell 88E8036 Fast Ethernet Controller (Compal)
59413+ - Marvell 88E8036 Fast Ethernet Controller (Inventec)
59414+ - Marvell 88E8036 Fast Ethernet Controller (LGE)
59415+ - Marvell 88E8036 Fast Ethernet Controller (Mitac)
59416+ - Marvell 88E8036 Fast Ethernet Controller (Panasonic)
59417+ - Marvell 88E8036 Fast Ethernet Controller (Quanta)
59418+ - Marvell 88E8036 Fast Ethernet Controller (Toshiba)
59419+ - Marvell 88E8036 Fast Ethernet Controller (Wistron)
59420+ - Marvell 88E8050 Gigabit Ethernet Controller (Gateway)
59421+ - Marvell 88E8050 Gigabit Ethernet Controller (Intel)
59422+ - Marvell 88E8052 Gigabit Ethernet Controller (ASRock)
59423+ - Marvell 88E8052 Gigabit Ethernet Controller (Aopen)
59424+ - Marvell 88E8052 Gigabit Ethernet Controller (Asus)
59425+ - Marvell 88E8052 Gigabit Ethernet Controller (Gateway)
59426+ - Marvell 88E8052 Gigabit Ethernet Controller (Gigabyte)
59427+ - Marvell 88E8052 Gigabit Ethernet Controller (MSI)
59428+ - Marvell 88E8052 Gigabit Ethernet Controller (Wistron)
59429+ - Marvell 88E8053 Gigabit Ethernet Controller (ASRock)
59430+ - Marvell 88E8053 Gigabit Ethernet Controller (Albatron)
59431+ - Marvell 88E8053 Gigabit Ethernet Controller (Aopen)
59432+ - Marvell 88E8053 Gigabit Ethernet Controller (Arima)
59433+ - Marvell 88E8053 Gigabit Ethernet Controller (Asus)
59434+ - Marvell 88E8053 Gigabit Ethernet Controller (Chaintech)
59435+ - Marvell 88E8053 Gigabit Ethernet Controller (Clevo)
59436+ - Marvell 88E8053 Gigabit Ethernet Controller (Compal)
59437+ - Marvell 88E8053 Gigabit Ethernet Controller (DFI)
59438+ - Marvell 88E8053 Gigabit Ethernet Controller (ECS)
59439+ - Marvell 88E8053 Gigabit Ethernet Controller (Epox)
59440+ - Marvell 88E8053 Gigabit Ethernet Controller (Gigabyte)
59441+ - Marvell 88E8053 Gigabit Ethernet Controller (Inventec)
59442+ - Marvell 88E8053 Gigabit Ethernet Controller (LGE)
59443+ - Marvell 88E8053 Gigabit Ethernet Controller (MSI)
59444+ - Marvell 88E8053 Gigabit Ethernet Controller (Mitac)
59445+ - Marvell 88E8053 Gigabit Ethernet Controller (Panasonic)
59446+ - Marvell 88E8053 Gigabit Ethernet Controller (Quanta)
59447+ - Marvell 88E8053 Gigabit Ethernet Controller (SOYO)
59448+ - Marvell 88E8053 Gigabit Ethernet Controller (Shuttle)
59449+ - Marvell 88E8053 Gigabit Ethernet Controller (Toshiba)
59450+ - Marvell 88E8053 Gigabit Ethernet Controller (Trigem)
59451+ - Marvell RDK-8001
59452 - Marvell RDK-8001 Adapter
59453 - Marvell RDK-8002 Adapter
59454+ - Marvell RDK-8003
59455 - Marvell RDK-8003 Adapter
59456 - Marvell RDK-8004 Adapter
59457 - Marvell RDK-8006 Adapter
59458 - Marvell RDK-8007 Adapter
59459 - Marvell RDK-8008 Adapter
59460 - Marvell RDK-8009 Adapter
59461- - Marvell RDK-8010 Adapter
59462+ - Marvell RDK-8010
59463 - Marvell RDK-8011 Adapter
59464 - Marvell RDK-8012 Adapter
59465- - Marvell RDK-8052 Adapter
59466- - Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Adapter (32 bit)
59467- - Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Adapter (64 bit)
59468+ - Marvell RDK-8035
59469+ - Marvell RDK-8036
59470+ - Marvell RDK-8052
59471+ - Marvell RDK-8053
59472+ - Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Controller (32 bit)
59473+ - Marvell Yukon Gigabit Ethernet 10/100/1000Base-T Controller (64 bit)
59474+ - Marvell Yukon-EC Ultra, no ASF (Battery Power Service Support)
59475+ - Marvell Yukon-FE Fast Ethernet, Reduced Battery Power Service Support)
59476 - N-Way PCI-Bus Giga-Card 1000/100/10Mbps(L)
59477 - SK-9521 10/100/1000Base-T Adapter
59478 - SK-9521 V2.0 10/100/1000Base-T Adapter
59479@@ -2250,21 +2311,37 @@
59480 - SK-9871 Gigabit Ethernet Server Adapter (SK-NET GE-ZX)
59481 - SK-9871 V2.0 Gigabit Ethernet 1000Base-ZX Adapter
59482 - SK-9872 Gigabit Ethernet Server Adapter (SK-NET GE-ZX dual link)
59483+ - SK-9S21 Server Adapter
59484+ - SK-9S22 Server Adapter
59485+ - SK-9S24 Server Adapter
59486+ - SK-9S34 Server Adapter
59487+ - SK-9S81 Server Adapter
59488+ - SK-9S82 Server Adapter
59489+ - SK-9S91 Server Adapter
59490+ - SK-9S92 Server Adapter
59491 - SMC EZ Card 1000 (SMC9452TXV.2)
59492
59493 The adapters support Jumbo Frames.
59494 The dual link adapters support link-failover and dual port features.
59495 Both Marvell Yukon and SysKonnect SK-98xx/SK-95xx adapters support
59496 the scatter-gather functionality with sendfile(). Please refer to
59497- <file:Documentation/networking/sk98lin.txt> for more information about
59498+ Documentation/networking/sk98lin.txt for more information about
59499 optional driver parameters.
59500 Questions concerning this driver may be addressed to:
59501- <linux@syskonnect.de>
59502+ linux@syskonnect.de
59503
59504 If you want to compile this driver as a module ( = code which can be
59505 inserted in and removed from the running kernel whenever you want),
59506- say M here and read <file:Documentation/kbuild/modules.txt>. The module will
59507- be called sk98lin. This is recommended.
59508+ say M here and read Documentation/modules.txt. This is recommended.
59509+ The module will be called sk98lin. This is recommended.
59510+
59511+config SK98LIN_NAPI
59512+ bool "Use Rx polling (NAPI)"
59513+ depends on SK98LIN
59514+ help
59515+ NAPI is a new driver API designed to reduce CPU and interrupt load
59516+ when the driver is receiving lots of packets from the card.
59517+
59518
59519 config VIA_VELOCITY
59520 tristate "VIA Velocity support"
The Linux kernel (the core of the Linux operating system)
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