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- bump nouveau API to 0.0.15
[packages/libdrm.git] / libdrm-nouveau-abi-0.0.15.patch
CommitLineData
fa8be192
PZ		 1diff --git a/libdrm/nouveau/Makefile.am b/libdrm/nouveau/Makefile.am
2index 688eeca..490ce57 100644
3--- a/libdrm/nouveau/Makefile.am
4+++ b/libdrm/nouveau/Makefile.am
5@@ -18,9 +18,6 @@ libdrm_nouveau_la_SOURCES = \
6 nouveau_notifier.c \
7 nouveau_bo.c \
8 nouveau_resource.c \
9- nouveau_dma.c \
10- nouveau_fence.c \
11- nouveau_dma.h \
12 nouveau_private.h
13
14 libdrm_nouveaucommonincludedir = ${includedir}/nouveau
15diff --git a/libdrm/nouveau/nouveau_bo.c b/libdrm/nouveau/nouveau_bo.c
16index fea3a7d..520d5d7 100644
17--- a/libdrm/nouveau/nouveau_bo.c
18+++ b/libdrm/nouveau/nouveau_bo.c
19@@ -49,7 +49,7 @@ nouveau_bo_info(struct nouveau_bo_priv *nvbo, struct drm_nouveau_gem_info *arg)
20 {
21 nvbo->handle = nvbo->base.handle = arg->handle;
22 nvbo->domain = arg->domain;
23- nvbo->size = nvbo->base.size = arg->size;
24+ nvbo->size = arg->size;
25 nvbo->offset = arg->offset;
26 nvbo->map_handle = arg->map_handle;
27 nvbo->base.tile_mode = arg->tile_mode;
28@@ -91,28 +91,6 @@ nouveau_bo_ufree(struct nouveau_bo_priv *nvbo)
29 }
30
31 static void
32-nouveau_bo_kfree_nomm(struct nouveau_bo_priv *nvbo)
33-{
34- struct nouveau_device_priv *nvdev = nouveau_device(nvbo->base.device);
35- struct drm_nouveau_mem_free req;
36-
37- if (nvbo->map) {
38- drmUnmap(nvbo->map, nvbo->size);
39- nvbo->map = NULL;
40- }
41-
42- req.offset = nvbo->offset;
43- if (nvbo->domain & NOUVEAU_BO_GART)
44- req.flags = NOUVEAU_MEM_AGP | NOUVEAU_MEM_PCI;
45- else
46- if (nvbo->domain & NOUVEAU_BO_VRAM)
47- req.flags = NOUVEAU_MEM_FB;
48- drmCommandWrite(nvdev->fd, DRM_NOUVEAU_MEM_FREE, &req, sizeof(req));
49-
50- nvbo->handle = 0;
51-}
52-
53-static void
54 nouveau_bo_kfree(struct nouveau_bo_priv *nvbo)
55 {
56 struct nouveau_device_priv *nvdev = nouveau_device(nvbo->base.device);
57@@ -121,11 +99,6 @@ nouveau_bo_kfree(struct nouveau_bo_priv *nvbo)
58 if (!nvbo->handle)
59 return;
60
61- if (!nvdev->mm_enabled) {
62- nouveau_bo_kfree_nomm(nvbo);
63- return;
64- }
65-
66 if (nvbo->map) {
67 munmap(nvbo->map, nvbo->size);
68 nvbo->map = NULL;
69@@ -137,51 +110,6 @@ nouveau_bo_kfree(struct nouveau_bo_priv *nvbo)
70 }
71
72 static int
73-nouveau_bo_kalloc_nomm(struct nouveau_bo_priv *nvbo)
74-{
75- struct nouveau_device_priv *nvdev = nouveau_device(nvbo->base.device);
76- struct drm_nouveau_mem_alloc req;
77- int ret;
78-
79- if (nvbo->handle)
80- return 0;
81-
82- if (!(nvbo->flags & (NOUVEAU_BO_VRAM|NOUVEAU_BO_GART)))
83- nvbo->flags |= (NOUVEAU_BO_GART | NOUVEAU_BO_VRAM);
84-
85- req.size = nvbo->size;
86- req.alignment = nvbo->align;
87- req.flags = 0;
88- if (nvbo->flags & NOUVEAU_BO_VRAM)
89- req.flags |= NOUVEAU_MEM_FB;
90- if (nvbo->flags & NOUVEAU_BO_GART)
91- req.flags |= (NOUVEAU_MEM_AGP | NOUVEAU_MEM_PCI);
92- if (nvbo->flags & NOUVEAU_BO_TILED) {
93- req.flags |= NOUVEAU_MEM_TILE;
94- if (nvbo->flags & NOUVEAU_BO_ZTILE)
95- req.flags |= NOUVEAU_MEM_TILE_ZETA;
96- }
97- req.flags |= NOUVEAU_MEM_MAPPED;
98-
99- ret = drmCommandWriteRead(nvdev->fd, DRM_NOUVEAU_MEM_ALLOC,
100- &req, sizeof(req));
101- if (ret)
102- return ret;
103-
104- nvbo->handle =
105- nvbo->map_handle = req.map_handle;
106- nvbo->size = req.size;
107- nvbo->offset = req.offset;
108- if (req.flags & (NOUVEAU_MEM_AGP | NOUVEAU_MEM_PCI))
109- nvbo->domain = NOUVEAU_BO_GART;
110- else
111- if (req.flags & NOUVEAU_MEM_FB)
112- nvbo->domain = NOUVEAU_BO_VRAM;
113-
114- return 0;
115-}
116-
117-static int
118 nouveau_bo_kalloc(struct nouveau_bo_priv *nvbo, struct nouveau_channel *chan)
119 {
120 struct nouveau_device_priv *nvdev = nouveau_device(nvbo->base.device);
121@@ -192,9 +120,6 @@ nouveau_bo_kalloc(struct nouveau_bo_priv *nvbo, struct nouveau_channel *chan)
122 if (nvbo->handle || (nvbo->flags & NOUVEAU_BO_PIN))
123 return 0;
124
125- if (!nvdev->mm_enabled)
126- return nouveau_bo_kalloc_nomm(nvbo);
127-
128 req.channel_hint = chan ? chan->id : 0;
129 req.align = nvbo->align;
130
131@@ -227,21 +152,6 @@ nouveau_bo_kalloc(struct nouveau_bo_priv *nvbo, struct nouveau_channel *chan)
132 }
133
134 static int
135-nouveau_bo_kmap_nomm(struct nouveau_bo_priv *nvbo)
136-{
137- struct nouveau_device_priv *nvdev = nouveau_device(nvbo->base.device);
138- int ret;
139-
140- ret = drmMap(nvdev->fd, nvbo->handle, nvbo->size, &nvbo->map);
141- if (ret) {
142- nvbo->map = NULL;
143- return ret;
144- }
145-
146- return 0;
147-}
148-
149-static int
150 nouveau_bo_kmap(struct nouveau_bo_priv *nvbo)
151 {
152 struct nouveau_device_priv *nvdev = nouveau_device(nvbo->base.device);
153@@ -252,9 +162,6 @@ nouveau_bo_kmap(struct nouveau_bo_priv *nvbo)
154 if (!nvbo->map_handle)
155 return -EINVAL;
156
157- if (!nvdev->mm_enabled)
158- return nouveau_bo_kmap_nomm(nvbo);
159-
160 nvbo->map = mmap(0, nvbo->size, PROT_READ | PROT_WRITE,
161 MAP_SHARED, nvdev->fd, nvbo->map_handle);
162 if (nvbo->map == MAP_FAILED) {
163@@ -328,7 +235,7 @@ nouveau_bo_user(struct nouveau_device *dev, void *ptr, int size,
164 struct nouveau_bo_priv *nvbo;
165 int ret;
166
167- ret = nouveau_bo_new(dev, 0, 0, size, bo);
168+ ret = nouveau_bo_new(dev, NOUVEAU_BO_MAP, 0, size, bo);
169 if (ret)
170 return ret;
171 nvbo = nouveau_bo(*bo);
172@@ -339,28 +246,6 @@ nouveau_bo_user(struct nouveau_device *dev, void *ptr, int size,
173 }
174
175 int
176-nouveau_bo_fake(struct nouveau_device *dev, uint64_t offset, uint32_t flags,
177- uint32_t size, void *map, struct nouveau_bo **bo)
178-{
179- struct nouveau_bo_priv *nvbo;
180- int ret;
181-
182- ret = nouveau_bo_new(dev, flags & ~NOUVEAU_BO_PIN, 0, size, bo);
183- if (ret)
184- return ret;
185- nvbo = nouveau_bo(*bo);
186-
187- nvbo->flags = flags | NOUVEAU_BO_PIN;
188- nvbo->domain = (flags & (NOUVEAU_BO_VRAM|NOUVEAU_BO_GART));
189- nvbo->offset = offset;
190- nvbo->size = nvbo->base.size = size;
191- nvbo->map = map;
192- nvbo->base.flags = nvbo->flags;
193- nvbo->base.offset = nvbo->offset;
194- return 0;
195-}
196-
197-int
198 nouveau_bo_wrap(struct nouveau_device *dev, uint32_t handle,
199 struct nouveau_bo **bo)
200 {
201@@ -369,9 +254,6 @@ nouveau_bo_wrap(struct nouveau_device *dev, uint32_t handle,
202 struct nouveau_bo_priv *nvbo;
203 int ret;
204
205- if (!nvdev->mm_enabled)
206- return -ENODEV;
207-
208 ret = nouveau_bo_new(dev, 0, 0, 0, bo);
209 if (ret)
210 return ret;
211@@ -386,6 +268,7 @@ nouveau_bo_wrap(struct nouveau_device *dev, uint32_t handle,
212 }
213
214 nouveau_bo_info(nvbo, &req);
215+ nvbo->base.size = nvbo->size;
216 return 0;
217 }
218
219@@ -406,18 +289,14 @@ nouveau_bo_handle_get(struct nouveau_bo *bo, uint32_t *handle)
220 if (ret)
221 return ret;
222
223- if (nvdev->mm_enabled) {
224- req.handle = nvbo->handle;
225- ret = ioctl(nvdev->fd, DRM_IOCTL_GEM_FLINK, &req);
226- if (ret) {
227- nouveau_bo_kfree(nvbo);
228- return ret;
229- }
230-
231- nvbo->global_handle = req.name;
232- } else {
233- nvbo->global_handle = nvbo->offset;
234+ req.handle = nvbo->handle;
235+ ret = ioctl(nvdev->fd, DRM_IOCTL_GEM_FLINK, &req);
236+ if (ret) {
237+ nouveau_bo_kfree(nvbo);
238+ return ret;
239 }
240+
241+ nvbo->global_handle = req.name;
242 }
243
244 *handle = nvbo->global_handle;
245@@ -433,51 +312,25 @@ nouveau_bo_handle_ref(struct nouveau_device *dev, uint32_t handle,
246 struct drm_gem_open req;
247 int ret;
248
249- if (!nvdev->mm_enabled) {
250- ret = nouveau_bo_new(dev, 0, 0, 0, bo);
251- if (ret)
252- return ret;
253- nvbo = nouveau_bo(*bo);
254-
255- nvbo->handle = 0;
256- nvbo->offset = handle;
257- nvbo->domain = NOUVEAU_BO_VRAM;
258- nvbo->flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_PIN;
259- nvbo->base.offset = nvbo->offset;
260- nvbo->base.flags = nvbo->flags;
261- } else {
262- req.name = handle;
263- ret = ioctl(nvdev->fd, DRM_IOCTL_GEM_OPEN, &req);
264- if (ret) {
265- nouveau_bo_ref(NULL, bo);
266- return ret;
267- }
268-
269- ret = nouveau_bo_wrap(dev, req.handle, bo);
270- if (ret) {
271- nouveau_bo_ref(NULL, bo);
272- return ret;
273- }
274+ req.name = handle;
275+ ret = ioctl(nvdev->fd, DRM_IOCTL_GEM_OPEN, &req);
276+ if (ret) {
277+ nouveau_bo_ref(NULL, bo);
278+ return ret;
279+ }
280
281- nvbo = nouveau_bo(*bo);
282+ ret = nouveau_bo_wrap(dev, req.handle, bo);
283+ if (ret) {
284+ nouveau_bo_ref(NULL, bo);
285+ return ret;
286 }
287
288+ nvbo = nouveau_bo(*bo);
289 nvbo->base.handle = nvbo->handle;
290 return 0;
291 }
292
293 static void
294-nouveau_bo_del_cb(void *priv)
295-{
296- struct nouveau_bo_priv *nvbo = priv;
297-
298- nouveau_fence_ref(NULL, &nvbo->fence);
299- nouveau_fence_ref(NULL, &nvbo->wr_fence);
300- nouveau_bo_kfree(nvbo);
301- free(nvbo);
302-}
303-
304-static void
305 nouveau_bo_del(struct nouveau_bo **bo)
306 {
307 struct nouveau_bo_priv *nvbo;
308@@ -496,18 +349,8 @@ nouveau_bo_del(struct nouveau_bo **bo)
309 }
310
311 nouveau_bo_ufree(nvbo);
312-
313- if (!nouveau_device(nvbo->base.device)->mm_enabled && nvbo->fence) {
314- nouveau_fence_flush(nvbo->fence->channel);
315- if (nouveau_fence(nvbo->fence)->signalled) {
316- nouveau_bo_del_cb(nvbo);
317- } else {
318- nouveau_fence_signal_cb(nvbo->fence,
319- nouveau_bo_del_cb, nvbo);
320- }
321- } else {
322- nouveau_bo_del_cb(nvbo);
323- }
324+ nouveau_bo_kfree(nvbo);
325+ free(nvbo);
326 }
327
328 int
329@@ -527,24 +370,7 @@ nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pbo)
330 }
331
332 static int
333-nouveau_bo_wait_nomm(struct nouveau_bo *bo, int cpu_write)
334-{
335- struct nouveau_bo_priv *nvbo = nouveau_bo(bo);
336- int ret = 0;
337-
338- if (cpu_write)
339- ret = nouveau_fence_wait(&nvbo->fence);
340- else
341- ret = nouveau_fence_wait(&nvbo->wr_fence);
342- if (ret)
343- return ret;
344-
345- nvbo->write_marker = 0;
346- return 0;
347-}
348-
349-static int
350-nouveau_bo_wait(struct nouveau_bo *bo, int cpu_write)
351+nouveau_bo_wait(struct nouveau_bo *bo, int cpu_write, int no_wait, int no_block)
352 {
353 struct nouveau_device_priv *nvdev = nouveau_device(bo->device);
354 struct nouveau_bo_priv *nvbo = nouveau_bo(bo);
355@@ -560,10 +386,15 @@ nouveau_bo_wait(struct nouveau_bo *bo, int cpu_write)
356 nouveau_pushbuf_flush(nvbo->pending_channel, 0);
357 }
358
359- if (!nvdev->mm_enabled)
360- return nouveau_bo_wait_nomm(bo, cpu_write);
361-
362 req.handle = nvbo->handle;
363+ req.flags = 0;
364+ if (cpu_write)
365+ req.flags |= NOUVEAU_GEM_CPU_PREP_WRITE;
366+ if (no_wait)
367+ req.flags |= NOUVEAU_GEM_CPU_PREP_NOWAIT;
368+ if (no_block)
369+ req.flags |= NOUVEAU_GEM_CPU_PREP_NOBLOCK;
370+
371 do {
372 ret = drmCommandWrite(nvdev->fd, DRM_NOUVEAU_GEM_CPU_PREP,
373 &req, sizeof(req));
374@@ -608,7 +439,8 @@ nouveau_bo_map_range(struct nouveau_bo *bo, uint32_t delta, uint32_t size,
375 return ret;
376
377 if (!(flags & NOUVEAU_BO_NOSYNC)) {
378- ret = nouveau_bo_wait(bo, (flags & NOUVEAU_BO_WR));
379+ ret = nouveau_bo_wait(bo, (flags & NOUVEAU_BO_WR),
380+ (flags & NOUVEAU_BO_NOWAIT), 0);
381 if (ret)
382 return ret;
383 }
384@@ -633,10 +465,9 @@ nouveau_bo_map(struct nouveau_bo *bo, uint32_t flags)
385 void
386 nouveau_bo_unmap(struct nouveau_bo *bo)
387 {
388- struct nouveau_device_priv *nvdev = nouveau_device(bo->device);
389 struct nouveau_bo_priv *nvbo = nouveau_bo(bo);
390
391- if (nvdev->mm_enabled && bo->map && !nvbo->sysmem) {
392+ if (bo->map && !nvbo->sysmem) {
393 struct nouveau_device_priv *nvdev = nouveau_device(bo->device);
394 struct drm_nouveau_gem_cpu_fini req;
395
396@@ -649,95 +480,6 @@ nouveau_bo_unmap(struct nouveau_bo *bo)
397 }
398
399 int
400-nouveau_bo_validate_nomm(struct nouveau_bo_priv *nvbo, uint32_t flags)
401-{
402- struct nouveau_bo *new = NULL;
403- uint32_t t_handle, t_domain, t_offset, t_size, t_maph;
404- void *t_map;
405- int ret;
406-
407- if ((flags & NOUVEAU_BO_VRAM) && nvbo->domain == NOUVEAU_BO_VRAM)
408- return 0;
409- if ((flags & NOUVEAU_BO_GART) && nvbo->domain == NOUVEAU_BO_GART)
410- return 0;
411- assert(flags & (NOUVEAU_BO_VRAM|NOUVEAU_BO_GART));
412-
413- /* Keep tiling info */
414- flags |= (nvbo->flags & (NOUVEAU_BO_TILED|NOUVEAU_BO_ZTILE));
415-
416- ret = nouveau_bo_new(nvbo->base.device, flags, 0, nvbo->size, &new);
417- if (ret)
418- return ret;
419-
420- ret = nouveau_bo_kalloc(nouveau_bo(new), NULL);
421- if (ret) {
422- nouveau_bo_ref(NULL, &new);
423- return ret;
424- }
425-
426- if (nvbo->handle || nvbo->sysmem) {
427- nouveau_bo_kmap(nouveau_bo(new));
428-
429- if (!nvbo->base.map) {
430- nouveau_bo_map(&nvbo->base, NOUVEAU_BO_RD);
431- memcpy(nouveau_bo(new)->map, nvbo->base.map, nvbo->base.size);
432- nouveau_bo_unmap(&nvbo->base);
433- } else {
434- memcpy(nouveau_bo(new)->map, nvbo->base.map, nvbo->base.size);
435- }
436- }
437-
438- t_handle = nvbo->handle;
439- t_maph = nvbo->map_handle;
440- t_domain = nvbo->domain;
441- t_offset = nvbo->offset;
442- t_size = nvbo->size;
443- t_map = nvbo->map;
444-
445- nvbo->handle = nouveau_bo(new)->handle;
446- nvbo->map_handle = nouveau_bo(new)->map_handle;
447- nvbo->domain = nouveau_bo(new)->domain;
448- nvbo->offset = nouveau_bo(new)->offset;
449- nvbo->size = nouveau_bo(new)->size;
450- nvbo->map = nouveau_bo(new)->map;
451-
452- nouveau_bo(new)->handle = t_handle;
453- nouveau_bo(new)->map_handle = t_maph;
454- nouveau_bo(new)->domain = t_domain;
455- nouveau_bo(new)->offset = t_offset;
456- nouveau_bo(new)->size = t_size;
457- nouveau_bo(new)->map = t_map;
458-
459- nouveau_bo_ref(NULL, &new);
460-
461- return 0;
462-}
463-
464-static int
465-nouveau_bo_pin_nomm(struct nouveau_bo *bo, uint32_t flags)
466-{
467- struct nouveau_bo_priv *nvbo = nouveau_bo(bo);
468- int ret;
469-
470- if (!nvbo->handle) {
471- if (!(flags & (NOUVEAU_BO_VRAM | NOUVEAU_BO_GART)))
472- return -EINVAL;
473-
474- ret = nouveau_bo_validate_nomm(nvbo, flags & ~NOUVEAU_BO_PIN);
475- if (ret)
476- return ret;
477- }
478-
479- nvbo->pinned = 1;
480-
481- /* Fill in public nouveau_bo members */
482- bo->flags = nvbo->domain;
483- bo->offset = nvbo->offset;
484-
485- return 0;
486-}
487-
488-int
489 nouveau_bo_pin(struct nouveau_bo *bo, uint32_t flags)
490 {
491 struct nouveau_device_priv *nvdev = nouveau_device(bo->device);
492@@ -748,9 +490,6 @@ nouveau_bo_pin(struct nouveau_bo *bo, uint32_t flags)
493 if (nvbo->pinned)
494 return 0;
495
496- if (!nvdev->mm_enabled)
497- return nouveau_bo_pin_nomm(bo, flags);
498-
499 /* Ensure we have a kernel object... */
500 if (!nvbo->flags) {
501 if (!(flags & (NOUVEAU_BO_VRAM | NOUVEAU_BO_GART)))
502@@ -801,80 +540,16 @@ nouveau_bo_unpin(struct nouveau_bo *bo)
503 if (!nvbo->pinned)
504 return;
505
506- if (nvdev->mm_enabled) {
507- req.handle = nvbo->handle;
508- drmCommandWrite(nvdev->fd, DRM_NOUVEAU_GEM_UNPIN,
509- &req, sizeof(req));
510- }
511+ req.handle = nvbo->handle;
512+ drmCommandWrite(nvdev->fd, DRM_NOUVEAU_GEM_UNPIN, &req, sizeof(req));
513
514 nvbo->pinned = bo->offset = bo->flags = 0;
515 }
516
517 int
518-nouveau_bo_tile(struct nouveau_bo *bo, uint32_t flags, uint32_t delta,
519- uint32_t size)
520-{
521- struct nouveau_device_priv *nvdev = nouveau_device(bo->device);
522- struct nouveau_bo_priv *nvbo = nouveau_bo(bo);
523- uint32_t kern_flags = 0;
524- int ret = 0;
525-
526- if (flags & NOUVEAU_BO_TILED) {
527- kern_flags |= NOUVEAU_MEM_TILE;
528- if (flags & NOUVEAU_BO_ZTILE)
529- kern_flags |= NOUVEAU_MEM_TILE_ZETA;
530- }
531-
532- if (nvdev->mm_enabled) {
533- struct drm_nouveau_gem_tile req;
534-
535- req.handle = nvbo->handle;
536- req.delta = delta;
537- req.size = size;
538- req.flags = kern_flags;
539- ret = drmCommandWrite(nvdev->fd, DRM_NOUVEAU_GEM_TILE,
540- &req, sizeof(req));
541- } else {
542- struct drm_nouveau_mem_tile req;
543-
544- req.offset = nvbo->offset;
545- req.delta = delta;
546- req.size = size;
547- req.flags = kern_flags;
548-
549- if (flags & NOUVEAU_BO_VRAM)
550- req.flags |= NOUVEAU_MEM_FB;
551- if (flags & NOUVEAU_BO_GART)
552- req.flags |= NOUVEAU_MEM_AGP;
553-
554- ret = drmCommandWrite(nvdev->fd, DRM_NOUVEAU_MEM_TILE,
555- &req, sizeof(req));
556- }
557-
558- return 0;
559-}
560-
561-int
562 nouveau_bo_busy(struct nouveau_bo *bo, uint32_t access)
563 {
564- struct nouveau_device_priv *nvdev = nouveau_device(bo->device);
565- struct nouveau_bo_priv *nvbo = nouveau_bo(bo);
566-
567- if (!nvdev->mm_enabled) {
568- struct nouveau_fence *fence;
569-
570- if (nvbo->pending && (nvbo->pending->write_domains ||
571- (access & NOUVEAU_BO_WR)))
572- return 1;
573-
574- if (access & NOUVEAU_BO_WR)
575- fence = nvbo->fence;
576- else
577- fence = nvbo->wr_fence;
578- return !nouveau_fence(fence)->signalled;
579- }
580-
581- return 1;
582+ return nouveau_bo_wait(bo, (access & NOUVEAU_BO_WR), 1, 1);
583 }
584
585 struct drm_nouveau_gem_pushbuf_bo *
586@@ -904,12 +579,12 @@ nouveau_bo_emit_buffer(struct nouveau_channel *chan, struct nouveau_bo *bo)
587 nvbo->sysmem = sysmem_tmp;
588
589 memcpy(bo->map, nvbo->sysmem, nvbo->base.size);
590- nouveau_bo_unmap(bo);
591 nouveau_bo_ufree(nvbo);
592+ nouveau_bo_unmap(bo);
593 }
594 }
595
596- if (nvpb->nr_buffers >= NOUVEAU_PUSHBUF_MAX_BUFFERS)
597+ if (nvpb->nr_buffers >= NOUVEAU_GEM_MAX_BUFFERS)
598 return NULL;
599 pbbo = nvpb->buffers + nvpb->nr_buffers++;
600 nvbo->pending = pbbo;
601diff --git a/libdrm/nouveau/nouveau_bo.h b/libdrm/nouveau/nouveau_bo.h
602index 9b1feff..97ad2d7 100644
603--- a/libdrm/nouveau/nouveau_bo.h
604+++ b/libdrm/nouveau/nouveau_bo.h
605@@ -72,10 +72,6 @@ nouveau_bo_user(struct nouveau_device *, void *ptr, int size,
606 struct nouveau_bo **);
607
608 int
609-nouveau_bo_fake(struct nouveau_device *dev, uint64_t offset, uint32_t flags,
610- uint32_t size, void *map, struct nouveau_bo **);
611-
612-int
613 nouveau_bo_wrap(struct nouveau_device *, uint32_t handle, struct nouveau_bo **);
614
615 int
616@@ -108,10 +104,6 @@ void
617 nouveau_bo_unpin(struct nouveau_bo *);
618
619 int
620-nouveau_bo_tile(struct nouveau_bo *, uint32_t flags, uint32_t delta,
621- uint32_t size);
622-
623-int
624 nouveau_bo_busy(struct nouveau_bo *, uint32_t access);
625
626 #endif
627diff --git a/libdrm/nouveau/nouveau_channel.c b/libdrm/nouveau/nouveau_channel.c
628index 5de27dc..674c5c3 100644
629--- a/libdrm/nouveau/nouveau_channel.c
630+++ b/libdrm/nouveau/nouveau_channel.c
631@@ -74,8 +74,10 @@ nouveau_channel_alloc(struct nouveau_device *dev, uint32_t fb_ctxdma,
632 nvchan->base.subc[i].gr = &gr->base;
633 }
634
635- ret = drmMap(nvdev->fd, nvchan->drm.notifier, nvchan->drm.notifier_size,
636- (drmAddressPtr)&nvchan->notifier_block);
637+ ret = nouveau_bo_wrap(dev, nvchan->drm.notifier_handle,
638+ &nvchan->notifier_bo);
639+ if (!ret)
640+ ret = nouveau_bo_map(nvchan->notifier_bo, NOUVEAU_BO_RDWR);
641 if (ret) {
642 nouveau_channel_free((void *)&nvchan);
643 return ret;
644@@ -88,49 +90,8 @@ nouveau_channel_alloc(struct nouveau_device *dev, uint32_t fb_ctxdma,
645 return ret;
646 }
647
648- if (!nvdev->mm_enabled) {
649- ret = drmMap(nvdev->fd, nvchan->drm.ctrl, nvchan->drm.ctrl_size,
650- (void*)&nvchan->user);
651- if (ret) {
652- nouveau_channel_free((void *)&nvchan);
653- return ret;
654- }
655- nvchan->put = &nvchan->user[0x40/4];
656- nvchan->get = &nvchan->user[0x44/4];
657- nvchan->ref_cnt = &nvchan->user[0x48/4];
658-
659- ret = drmMap(nvdev->fd, nvchan->drm.cmdbuf,
660- nvchan->drm.cmdbuf_size, (void*)&nvchan->pushbuf);
661- if (ret) {
662- nouveau_channel_free((void *)&nvchan);
663- return ret;
664- }
665-
666- nouveau_dma_channel_init(&nvchan->base);
667- }
668-
669 nouveau_pushbuf_init(&nvchan->base);
670
671- if (!nvdev->mm_enabled && dev->chipset < 0x10) {
672- ret = nouveau_grobj_alloc(&nvchan->base, 0xbeef3904, 0x5039,
673- &nvchan->fence_grobj);
674- if (ret) {
675- nouveau_channel_free((void *)&nvchan);
676- return ret;
677- }
678-
679- ret = nouveau_notifier_alloc(&nvchan->base, 0xbeef3905, 1,
680- &nvchan->fence_ntfy);
681- if (ret) {
682- nouveau_channel_free((void *)&nvchan);
683- return ret;
684- }
685-
686- BEGIN_RING(&nvchan->base, nvchan->fence_grobj, 0x0180, 1);
687- OUT_RING (&nvchan->base, nvchan->fence_ntfy->handle);
688- nvchan->fence_grobj->bound = NOUVEAU_GROBJ_BOUND_EXPLICIT;
689- }
690-
691 *chan = &nvchan->base;
692 return 0;
693 }
694@@ -147,28 +108,15 @@ nouveau_channel_free(struct nouveau_channel **chan)
695 nvchan = nouveau_channel(*chan);
696 *chan = NULL;
697 nvdev = nouveau_device(nvchan->base.device);
698-
699- FIRE_RING(&nvchan->base);
700-
701- if (!nvdev->mm_enabled) {
702- struct nouveau_fence *fence = NULL;
703
704- /* Make sure all buffer objects on delayed delete queue
705- * actually get freed.
706- */
707- nouveau_fence_new(&nvchan->base, &fence);
708- nouveau_fence_emit(fence);
709- nouveau_fence_wait(&fence);
710- }
711+ FIRE_RING(&nvchan->base);
712
713- if (nvchan->notifier_block)
714- drmUnmap(nvchan->notifier_block, nvchan->drm.notifier_size);
715+ nouveau_bo_unmap(nvchan->notifier_bo);
716+ nouveau_bo_ref(NULL, &nvchan->notifier_bo);
717
718 nouveau_grobj_free(&nvchan->base.vram);
719 nouveau_grobj_free(&nvchan->base.gart);
720 nouveau_grobj_free(&nvchan->base.nullobj);
721- nouveau_grobj_free(&nvchan->fence_grobj);
722- nouveau_notifier_free(&nvchan->fence_ntfy);
723
724 cf.channel = nvchan->drm.channel;
725 drmCommandWrite(nvdev->fd, DRM_NOUVEAU_CHANNEL_FREE, &cf, sizeof(cf));
726diff --git a/libdrm/nouveau/nouveau_class.h b/libdrm/nouveau/nouveau_class.h
727index 3df3d7b..4d1c509 100644
728--- a/libdrm/nouveau/nouveau_class.h
729+++ b/libdrm/nouveau/nouveau_class.h
730@@ -6564,6 +6564,14 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
731 #define NV40TCL_BLEND_FUNC_DST_ALPHA_CONSTANT_ALPHA 0x80030000
732 #define NV40TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_ALPHA 0x80040000
733 #define NV40TCL_BLEND_COLOR 0x0000031c
734+#define NV40TCL_BLEND_COLOR_B_SHIFT 0
735+#define NV40TCL_BLEND_COLOR_B_MASK 0x000000ff
736+#define NV40TCL_BLEND_COLOR_G_SHIFT 8
737+#define NV40TCL_BLEND_COLOR_G_MASK 0x0000ff00
738+#define NV40TCL_BLEND_COLOR_R_SHIFT 16
739+#define NV40TCL_BLEND_COLOR_R_MASK 0x00ff0000
740+#define NV40TCL_BLEND_COLOR_A_SHIFT 24
741+#define NV40TCL_BLEND_COLOR_A_MASK 0xff000000
742 #define NV40TCL_BLEND_EQUATION 0x00000320
743 #define NV40TCL_BLEND_EQUATION_RGB_SHIFT 0
744 #define NV40TCL_BLEND_EQUATION_RGB_MASK 0x0000ffff
745@@ -6778,6 +6786,25 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
746 #define NV40TCL_VTX_ATTR_3I_Z__SIZE 0x00000010
747 #define NV40TCL_VTX_ATTR_3I_Z_Z_SHIFT 0
748 #define NV40TCL_VTX_ATTR_3I_Z_Z_MASK 0x0000ffff
749+#define NV40TCL_TEX_FILTER_OPTIMIZATION 0x00000b00
750+#define NV40TCL_TEX_FILTER_OPTIMIZATION_TRILINEAR_SHIFT 0
751+#define NV40TCL_TEX_FILTER_OPTIMIZATION_TRILINEAR_MASK 0x0000001f
752+#define NV40TCL_TEX_FILTER_OPTIMIZATION_TRILINEAR_OFF 0x00000000
753+#define NV40TCL_TEX_FILTER_OPTIMIZATION_TRILINEAR_HIGH_QUALITY 0x00000004
754+#define NV40TCL_TEX_FILTER_OPTIMIZATION_TRILINEAR_QUALITY 0x00000006
755+#define NV40TCL_TEX_FILTER_OPTIMIZATION_TRILINEAR_PERFORMANCE 0x00000008
756+#define NV40TCL_TEX_FILTER_OPTIMIZATION_TRILINEAR_HIGH_PERFORMANCE 0x00000018
757+#define NV40TCL_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE_SHIFT 6
758+#define NV40TCL_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE_MASK 0x000001c0
759+#define NV40TCL_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE_OFF 0x00000000
760+#define NV40TCL_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE_HIGH_QUALITY 0x000000c0
761+#define NV40TCL_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE_QUALITY 0x000001c0
762+#define NV40TCL_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE_PERFORMANCE 0x00000140
763+#define NV40TCL_TEX_FILTER_OPTIMIZATION_UNKNOWN_SHIFT 10
764+#define NV40TCL_TEX_FILTER_OPTIMIZATION_UNKNOWN_MASK 0x00007c00
765+#define NV40TCL_TEX_FILTER_OPTIMIZATION_UNKNOWN_OFF 0x00000000
766+#define NV40TCL_TEX_FILTER_OPTIMIZATION_UNKNOWN_PARTIAL 0x00002c00
767+#define NV40TCL_TEX_FILTER_OPTIMIZATION_UNKNOWN_FULL 0x00007c00
768 #define NV40TCL_UNK0B40(x) (0x00000b40+((x)*4))
769 #define NV40TCL_UNK0B40__SIZE 0x00000008
770 #define NV40TCL_VP_UPLOAD_INST(x) (0x00000b80+((x)*4))
771@@ -6951,7 +6978,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
772 #define NV40TCL_TEX_WRAP(x) (0x00001a08+((x)*32))
773 #define NV40TCL_TEX_WRAP__SIZE 0x00000010
774 #define NV40TCL_TEX_WRAP_S_SHIFT 0
775-#define NV40TCL_TEX_WRAP_S_MASK 0x000000ff
776+#define NV40TCL_TEX_WRAP_S_MASK 0x0000000f
777 #define NV40TCL_TEX_WRAP_S_REPEAT 0x00000001
778 #define NV40TCL_TEX_WRAP_S_MIRRORED_REPEAT 0x00000002
779 #define NV40TCL_TEX_WRAP_S_CLAMP_TO_EDGE 0x00000003
780@@ -6960,6 +6987,12 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
781 #define NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_EDGE 0x00000006
782 #define NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_BORDER 0x00000007
783 #define NV40TCL_TEX_WRAP_S_MIRROR_CLAMP 0x00000008
784+#define NV40TCL_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_SHIFT 4
785+#define NV40TCL_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_MASK 0x00000070
786+#define NV40TCL_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_OFF 0x00000000
787+#define NV40TCL_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_QUALITY 0x00000020
788+#define NV40TCL_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_PERFORMANCE 0x00000030
789+#define NV40TCL_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_HIGH_PERFORMANCE 0x00000070
790 #define NV40TCL_TEX_WRAP_T_SHIFT 8
791 #define NV40TCL_TEX_WRAP_T_MASK 0x00000f00
792 #define NV40TCL_TEX_WRAP_T_REPEAT 0x00000100
793@@ -6973,7 +7006,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
794 #define NV40TCL_TEX_WRAP_EXPAND_NORMAL_SHIFT 12
795 #define NV40TCL_TEX_WRAP_EXPAND_NORMAL_MASK 0x0000f000
796 #define NV40TCL_TEX_WRAP_R_SHIFT 16
797-#define NV40TCL_TEX_WRAP_R_MASK 0x00ff0000
798+#define NV40TCL_TEX_WRAP_R_MASK 0x000f0000
799 #define NV40TCL_TEX_WRAP_R_REPEAT 0x00010000
800 #define NV40TCL_TEX_WRAP_R_MIRRORED_REPEAT 0x00020000
801 #define NV40TCL_TEX_WRAP_R_CLAMP_TO_EDGE 0x00030000
802@@ -6982,6 +7015,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
803 #define NV40TCL_TEX_WRAP_R_MIRROR_CLAMP_TO_EDGE 0x00060000
804 #define NV40TCL_TEX_WRAP_R_MIRROR_CLAMP_TO_BORDER 0x00070000
805 #define NV40TCL_TEX_WRAP_R_MIRROR_CLAMP 0x00080000
806+#define NV40TCL_TEX_WRAP_GAMMA_DECREASE_FILTER_SHIFT 20
807+#define NV40TCL_TEX_WRAP_GAMMA_DECREASE_FILTER_MASK 0x00f00000
808+#define NV40TCL_TEX_WRAP_GAMMA_DECREASE_FILTER_NONE 0x00000000
809+#define NV40TCL_TEX_WRAP_GAMMA_DECREASE_FILTER_RED 0x00100000
810+#define NV40TCL_TEX_WRAP_GAMMA_DECREASE_FILTER_GREEN 0x00200000
811+#define NV40TCL_TEX_WRAP_GAMMA_DECREASE_FILTER_BLUE 0x00400000
812+#define NV40TCL_TEX_WRAP_GAMMA_DECREASE_FILTER_ALL 0x00f00000
813 #define NV40TCL_TEX_WRAP_RCOMP_SHIFT 28
814 #define NV40TCL_TEX_WRAP_RCOMP_MASK 0xf0000000
815 #define NV40TCL_TEX_WRAP_RCOMP_NEVER 0x00000000
816@@ -7150,22 +7190,74 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
817 #define NV50_2D_DMA_IN_MEMORY1 0x00000188
818 #define NV50_2D_DMA_IN_MEMORY2 0x0000018c
819 #define NV50_2D_DST_FORMAT 0x00000200
820-#define NV50_2D_DST_FORMAT_32BPP 0x000000cf
821-#define NV50_2D_DST_FORMAT_24BPP 0x000000e6
822-#define NV50_2D_DST_FORMAT_16BPP 0x000000e8
823-#define NV50_2D_DST_FORMAT_8BPP 0x000000f3
824-#define NV50_2D_DST_FORMAT_15BPP 0x000000f8
825+#define NV50_2D_DST_FORMAT_R32G32B32A32_FLOAT 0x000000c0
826+#define NV50_2D_DST_FORMAT_R32G32B32_FLOAT 0x000000c3
827+#define NV50_2D_DST_FORMAT_R16G16B16A16_UNORM 0x000000c6
828+#define NV50_2D_DST_FORMAT_R16G16B16A16_SNORM 0x000000c7
829+#define NV50_2D_DST_FORMAT_R16G16B16A16_FLOAT 0x000000ca
830+#define NV50_2D_DST_FORMAT_R32G32_FLOAT 0x000000cb
831+#define NV50_2D_DST_FORMAT_R16G16B16X16_FLOAT 0x000000ce
832+#define NV50_2D_DST_FORMAT_A8R8G8B8_UNORM 0x000000cf
833+#define NV50_2D_DST_FORMAT_A2B10G10R10_UNORM 0x000000d1
834+#define NV50_2D_DST_FORMAT_A8B8G8R8_UNORM 0x000000d6
835+#define NV50_2D_DST_FORMAT_A8B8G8R8_SNORM 0x000000d7
836+#define NV50_2D_DST_FORMAT_R16G16_UNORM 0x000000da
837+#define NV50_2D_DST_FORMAT_R16G16_SNORM 0x000000db
838+#define NV50_2D_DST_FORMAT_R16G16_FLOAT 0x000000de
839+#define NV50_2D_DST_FORMAT_A2R10G10B10_UNORM 0x000000df
840+#define NV50_2D_DST_FORMAT_B10G11R11_FLOAT 0x000000e0
841+#define NV50_2D_DST_FORMAT_R32_FLOAT 0x000000e5
842+#define NV50_2D_DST_FORMAT_X8R8G8B8_UNORM 0x000000e6
843+#define NV50_2D_DST_FORMAT_R5G6B5_UNORM 0x000000e8
844+#define NV50_2D_DST_FORMAT_R16_FLOAT 0x000000e9
845+#define NV50_2D_DST_FORMAT_R8G8_UNORM 0x000000ea
846+#define NV50_2D_DST_FORMAT_R8G8_SNORM 0x000000eb
847+#define NV50_2D_DST_FORMAT_R16_UNORM 0x000000ee
848+#define NV50_2D_DST_FORMAT_R16_SNORM 0x000000ef
849+#define NV50_2D_DST_FORMAT_R8_UNORM 0x000000f3
850+#define NV50_2D_DST_FORMAT_R32_BOOLEAN 0x000000f6
851+#define NV50_2D_DST_FORMAT_A8_UNORM 0x000000f7
852+#define NV50_2D_DST_FORMAT_X1B5G5R5_UNORM 0x000000f8
853+#define NV50_2D_DST_FORMAT_X8B8G8R8_UNORM 0x000000f9
854+#define NV50_2D_DST_LINEAR 0x00000204
855+#define NV50_2D_DST_TILE_MODE 0x00000208
856 #define NV50_2D_DST_PITCH 0x00000214
857 #define NV50_2D_DST_WIDTH 0x00000218
858 #define NV50_2D_DST_HEIGHT 0x0000021c
859 #define NV50_2D_DST_ADDRESS_HIGH 0x00000220
860 #define NV50_2D_DST_ADDRESS_LOW 0x00000224
861 #define NV50_2D_SRC_FORMAT 0x00000230
862-#define NV50_2D_SRC_FORMAT_32BPP 0x000000cf
863-#define NV50_2D_SRC_FORMAT_24BPP 0x000000e6
864-#define NV50_2D_SRC_FORMAT_16BPP 0x000000e8
865-#define NV50_2D_SRC_FORMAT_8BPP 0x000000f3
866-#define NV50_2D_SRC_FORMAT_15BPP 0x000000f8
867+#define NV50_2D_SRC_FORMAT_R32G32B32A32_FLOAT 0x000000c0
868+#define NV50_2D_SRC_FORMAT_R32G32B32_FLOAT 0x000000c3
869+#define NV50_2D_SRC_FORMAT_R16G16B16A16_UNORM 0x000000c6
870+#define NV50_2D_SRC_FORMAT_R16G16B16A16_SNORM 0x000000c7
871+#define NV50_2D_SRC_FORMAT_R16G16B16A16_FLOAT 0x000000ca
872+#define NV50_2D_SRC_FORMAT_R32G32_FLOAT 0x000000cb
873+#define NV50_2D_SRC_FORMAT_R16G16B16X16_FLOAT 0x000000ce
874+#define NV50_2D_SRC_FORMAT_A8R8G8B8_UNORM 0x000000cf
875+#define NV50_2D_SRC_FORMAT_A2B10G10R10_UNORM 0x000000d1
876+#define NV50_2D_SRC_FORMAT_A8B8G8R8_UNORM 0x000000d6
877+#define NV50_2D_SRC_FORMAT_A8B8G8R8_SNORM 0x000000d7
878+#define NV50_2D_SRC_FORMAT_R16G16_UNORM 0x000000da
879+#define NV50_2D_SRC_FORMAT_R16G16_SNORM 0x000000db
880+#define NV50_2D_SRC_FORMAT_R16G16_FLOAT 0x000000de
881+#define NV50_2D_SRC_FORMAT_A2R10G10B10_UNORM 0x000000df
882+#define NV50_2D_SRC_FORMAT_B10G11R11_FLOAT 0x000000e0
883+#define NV50_2D_SRC_FORMAT_R32_FLOAT 0x000000e5
884+#define NV50_2D_SRC_FORMAT_X8R8G8B8_UNORM 0x000000e6
885+#define NV50_2D_SRC_FORMAT_R5G6B5_UNORM 0x000000e8
886+#define NV50_2D_SRC_FORMAT_R16_FLOAT 0x000000e9
887+#define NV50_2D_SRC_FORMAT_R8G8_UNORM 0x000000ea
888+#define NV50_2D_SRC_FORMAT_R8G8_SNORM 0x000000eb
889+#define NV50_2D_SRC_FORMAT_R16_UNORM 0x000000ee
890+#define NV50_2D_SRC_FORMAT_R16_SNORM 0x000000ef
891+#define NV50_2D_SRC_FORMAT_R8_UNORM 0x000000f3
892+#define NV50_2D_SRC_FORMAT_R32_BOOLEAN 0x000000f6
893+#define NV50_2D_SRC_FORMAT_A8_UNORM 0x000000f7
894+#define NV50_2D_SRC_FORMAT_X1B5G5R5_UNORM 0x000000f8
895+#define NV50_2D_SRC_FORMAT_X8B8G8R8_UNORM 0x000000f9
896+#define NV50_2D_SRC_LINEAR 0x00000234
897+#define NV50_2D_SRC_TILE_MODE 0x00000238
898 #define NV50_2D_SRC_PITCH 0x00000244
899 #define NV50_2D_SRC_WIDTH 0x00000248
900 #define NV50_2D_SRC_HEIGHT 0x0000024c
901@@ -7193,11 +7285,35 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
902 #define NV50_2D_PATTERN_BITMAP(x) (0x000002f8+((x)*4))
903 #define NV50_2D_PATTERN_BITMAP__SIZE 0x00000002
904 #define NV50_2D_RECT_FORMAT 0x00000584
905-#define NV50_2D_RECT_FORMAT_32BPP 0x000000cf
906-#define NV50_2D_RECT_FORMAT_24BPP 0x000000e6
907-#define NV50_2D_RECT_FORMAT_16BPP 0x000000e8
908-#define NV50_2D_RECT_FORMAT_8BPP 0x000000f3
909-#define NV50_2D_RECT_FORMAT_15BPP 0x000000f8
910+#define NV50_2D_RECT_FORMAT_R32G32B32A32_FLOAT 0x000000c0
911+#define NV50_2D_RECT_FORMAT_R32G32B32_FLOAT 0x000000c3
912+#define NV50_2D_RECT_FORMAT_R16G16B16A16_UNORM 0x000000c6
913+#define NV50_2D_RECT_FORMAT_R16G16B16A16_SNORM 0x000000c7
914+#define NV50_2D_RECT_FORMAT_R16G16B16A16_FLOAT 0x000000ca
915+#define NV50_2D_RECT_FORMAT_R32G32_FLOAT 0x000000cb
916+#define NV50_2D_RECT_FORMAT_R16G16B16X16_FLOAT 0x000000ce
917+#define NV50_2D_RECT_FORMAT_A8R8G8B8_UNORM 0x000000cf
918+#define NV50_2D_RECT_FORMAT_A2B10G10R10_UNORM 0x000000d1
919+#define NV50_2D_RECT_FORMAT_A8B8G8R8_UNORM 0x000000d6
920+#define NV50_2D_RECT_FORMAT_A8B8G8R8_SNORM 0x000000d7
921+#define NV50_2D_RECT_FORMAT_R16G16_UNORM 0x000000da
922+#define NV50_2D_RECT_FORMAT_R16G16_SNORM 0x000000db
923+#define NV50_2D_RECT_FORMAT_R16G16_FLOAT 0x000000de
924+#define NV50_2D_RECT_FORMAT_A2R10G10B10_UNORM 0x000000df
925+#define NV50_2D_RECT_FORMAT_B10G11R11_FLOAT 0x000000e0
926+#define NV50_2D_RECT_FORMAT_R32_FLOAT 0x000000e5
927+#define NV50_2D_RECT_FORMAT_X8R8G8B8_UNORM 0x000000e6
928+#define NV50_2D_RECT_FORMAT_R5G6B5_UNORM 0x000000e8
929+#define NV50_2D_RECT_FORMAT_R16_FLOAT 0x000000e9
930+#define NV50_2D_RECT_FORMAT_R8G8_UNORM 0x000000ea
931+#define NV50_2D_RECT_FORMAT_R8G8_SNORM 0x000000eb
932+#define NV50_2D_RECT_FORMAT_R16_UNORM 0x000000ee
933+#define NV50_2D_RECT_FORMAT_R16_SNORM 0x000000ef
934+#define NV50_2D_RECT_FORMAT_R8_UNORM 0x000000f3
935+#define NV50_2D_RECT_FORMAT_R32_BOOLEAN 0x000000f6
936+#define NV50_2D_RECT_FORMAT_A8_UNORM 0x000000f7
937+#define NV50_2D_RECT_FORMAT_X1B5G5R5_UNORM 0x000000f8
938+#define NV50_2D_RECT_FORMAT_X8B8G8R8_UNORM 0x000000f9
939 #define NV50_2D_RECT_COLOR 0x00000588
940 #define NV50_2D_RECT_X1 0x00000600
941 #define NV50_2D_RECT_Y1 0x00000604
942@@ -7205,11 +7321,35 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
943 #define NV50_2D_RECT_Y2 0x0000060c
944 #define NV50_2D_SIFC_UNK0800 0x00000800
945 #define NV50_2D_SIFC_FORMAT 0x00000804
946-#define NV50_2D_SIFC_FORMAT_32BPP 0x000000cf
947-#define NV50_2D_SIFC_FORMAT_24BPP 0x000000e6
948-#define NV50_2D_SIFC_FORMAT_16BPP 0x000000e8
949-#define NV50_2D_SIFC_FORMAT_8BPP 0x000000f3
950-#define NV50_2D_SIFC_FORMAT_15BPP 0x000000f8
951+#define NV50_2D_SIFC_FORMAT_R32G32B32A32_FLOAT 0x000000c0
952+#define NV50_2D_SIFC_FORMAT_R32G32B32_FLOAT 0x000000c3
953+#define NV50_2D_SIFC_FORMAT_R16G16B16A16_UNORM 0x000000c6
954+#define NV50_2D_SIFC_FORMAT_R16G16B16A16_SNORM 0x000000c7
955+#define NV50_2D_SIFC_FORMAT_R16G16B16A16_FLOAT 0x000000ca
956+#define NV50_2D_SIFC_FORMAT_R32G32_FLOAT 0x000000cb
957+#define NV50_2D_SIFC_FORMAT_R16G16B16X16_FLOAT 0x000000ce
958+#define NV50_2D_SIFC_FORMAT_A8R8G8B8_UNORM 0x000000cf
959+#define NV50_2D_SIFC_FORMAT_A2B10G10R10_UNORM 0x000000d1
960+#define NV50_2D_SIFC_FORMAT_A8B8G8R8_UNORM 0x000000d6
961+#define NV50_2D_SIFC_FORMAT_A8B8G8R8_SNORM 0x000000d7
962+#define NV50_2D_SIFC_FORMAT_R16G16_UNORM 0x000000da
963+#define NV50_2D_SIFC_FORMAT_R16G16_SNORM 0x000000db
964+#define NV50_2D_SIFC_FORMAT_R16G16_FLOAT 0x000000de
965+#define NV50_2D_SIFC_FORMAT_A2R10G10B10_UNORM 0x000000df
966+#define NV50_2D_SIFC_FORMAT_B10G11R11_FLOAT 0x000000e0
967+#define NV50_2D_SIFC_FORMAT_R32_FLOAT 0x000000e5
968+#define NV50_2D_SIFC_FORMAT_X8R8G8B8_UNORM 0x000000e6
969+#define NV50_2D_SIFC_FORMAT_R5G6B5_UNORM 0x000000e8
970+#define NV50_2D_SIFC_FORMAT_R16_FLOAT 0x000000e9
971+#define NV50_2D_SIFC_FORMAT_R8G8_UNORM 0x000000ea
972+#define NV50_2D_SIFC_FORMAT_R8G8_SNORM 0x000000eb
973+#define NV50_2D_SIFC_FORMAT_R16_UNORM 0x000000ee
974+#define NV50_2D_SIFC_FORMAT_R16_SNORM 0x000000ef
975+#define NV50_2D_SIFC_FORMAT_R8_UNORM 0x000000f3
976+#define NV50_2D_SIFC_FORMAT_R32_BOOLEAN 0x000000f6
977+#define NV50_2D_SIFC_FORMAT_A8_UNORM 0x000000f7
978+#define NV50_2D_SIFC_FORMAT_X1B5G5R5_UNORM 0x000000f8
979+#define NV50_2D_SIFC_FORMAT_X8B8G8R8_UNORM 0x000000f9
980 #define NV50_2D_SIFC_WIDTH 0x00000838
981 #define NV50_2D_SIFC_HEIGHT 0x0000083c
982 #define NV50_2D_SIFC_SCALE_UNK0840 0x00000840
983@@ -7231,8 +7371,24 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
984
985 #define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039
986
987+#define NV50_MEMORY_TO_MEMORY_FORMAT_LINEAR_IN 0x00000200
988+#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_MODE_IN 0x00000204
989+#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_PITCH_IN 0x00000208
990+#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_HEIGHT_IN 0x0000020c
991+#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN 0x00000218
992+#define NV50_MEMORY_TO_MEMORY_FORMAT_LINEAR_OUT 0x0000021c
993+#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_MODE_OUT 0x00000220
994+#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_PITCH_OUT 0x00000224
995+#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_HEIGHT_OUT 0x00000228
996+#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT 0x00000234
997 #define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH 0x00000238
998 #define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH 0x0000023c
999+#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c
1000+#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT 0x00000310
1001+#define NV50_MEMORY_TO_MEMORY_FORMAT_PITCH_IN 0x00000314
1002+#define NV50_MEMORY_TO_MEMORY_FORMAT_PITCH_OUT 0x00000318
1003+#define NV50_MEMORY_TO_MEMORY_FORMAT_LINE_LENGTH_IN 0x0000031c
1004+#define NV50_MEMORY_TO_MEMORY_FORMAT_LINE_COUNT 0x00000320
1005
1006
1007 #define NV50TCL 0x00005097
1008@@ -7250,13 +7406,37 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
1009 #define NV50TCL_RT_ADDRESS_LOW__SIZE 0x00000008
1010 #define NV50TCL_RT_FORMAT(x) (0x00000208+((x)*32))
1011 #define NV50TCL_RT_FORMAT__SIZE 0x00000008
1012-#define NV50TCL_RT_FORMAT_32BPP 0x000000cf
1013-#define NV50TCL_RT_FORMAT_24BPP 0x000000e6
1014-#define NV50TCL_RT_FORMAT_16BPP 0x000000e8
1015-#define NV50TCL_RT_FORMAT_8BPP 0x000000f3
1016-#define NV50TCL_RT_FORMAT_15BPP 0x000000f8
1017-#define NV50TCL_RT_TILE_UNK(x) (0x0000020c+((x)*32))
1018-#define NV50TCL_RT_TILE_UNK__SIZE 0x00000008
1019+#define NV50TCL_RT_FORMAT_R32G32B32A32_FLOAT 0x000000c0
1020+#define NV50TCL_RT_FORMAT_R32G32B32_FLOAT 0x000000c3
1021+#define NV50TCL_RT_FORMAT_R16G16B16A16_UNORM 0x000000c6
1022+#define NV50TCL_RT_FORMAT_R16G16B16A16_SNORM 0x000000c7
1023+#define NV50TCL_RT_FORMAT_R16G16B16A16_FLOAT 0x000000ca
1024+#define NV50TCL_RT_FORMAT_R32G32_FLOAT 0x000000cb
1025+#define NV50TCL_RT_FORMAT_R16G16B16X16_FLOAT 0x000000ce
1026+#define NV50TCL_RT_FORMAT_A8R8G8B8_UNORM 0x000000cf
1027+#define NV50TCL_RT_FORMAT_A2B10G10R10_UNORM 0x000000d1
1028+#define NV50TCL_RT_FORMAT_A8B8G8R8_UNORM 0x000000d6
1029+#define NV50TCL_RT_FORMAT_A8B8G8R8_SNORM 0x000000d7
1030+#define NV50TCL_RT_FORMAT_R16G16_UNORM 0x000000da
1031+#define NV50TCL_RT_FORMAT_R16G16_SNORM 0x000000db
1032+#define NV50TCL_RT_FORMAT_R16G16_FLOAT 0x000000de
1033+#define NV50TCL_RT_FORMAT_A2R10G10B10_UNORM 0x000000df
1034+#define NV50TCL_RT_FORMAT_B10G11R11_FLOAT 0x000000e0
1035+#define NV50TCL_RT_FORMAT_R32_FLOAT 0x000000e5
1036+#define NV50TCL_RT_FORMAT_X8R8G8B8_UNORM 0x000000e6
1037+#define NV50TCL_RT_FORMAT_R5G6B5_UNORM 0x000000e8
1038+#define NV50TCL_RT_FORMAT_R16_FLOAT 0x000000e9
1039+#define NV50TCL_RT_FORMAT_R8G8_UNORM 0x000000ea
1040+#define NV50TCL_RT_FORMAT_R8G8_SNORM 0x000000eb
1041+#define NV50TCL_RT_FORMAT_R16_UNORM 0x000000ee
1042+#define NV50TCL_RT_FORMAT_R16_SNORM 0x000000ef
1043+#define NV50TCL_RT_FORMAT_R8_UNORM 0x000000f3
1044+#define NV50TCL_RT_FORMAT_R32_BOOLEAN 0x000000f6
1045+#define NV50TCL_RT_FORMAT_A8_UNORM 0x000000f7
1046+#define NV50TCL_RT_FORMAT_X1B5G5R5_UNORM 0x000000f8
1047+#define NV50TCL_RT_FORMAT_X8B8G8R8_UNORM 0x000000f9
1048+#define NV50TCL_RT_TILE_MODE(x) (0x0000020c+((x)*32))
1049+#define NV50TCL_RT_TILE_MODE__SIZE 0x00000008
1050 #define NV50TCL_RT_UNK4(x) (0x00000210+((x)*32))
1051 #define NV50TCL_RT_UNK4__SIZE 0x00000008
1052 #define NV50TCL_VTX_ATTR_1F(x) (0x00000300+((x)*4))
1053@@ -7313,10 +7493,16 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
1054 #define NV50TCL_VTX_ATTR_4NI_1_W_MASK 0xffff0000
1055 #define NV50TCL_VERTEX_ARRAY_FORMAT(x) (0x00000900+((x)*16))
1056 #define NV50TCL_VERTEX_ARRAY_FORMAT__SIZE 0x00000010
1057-#define NV50TCL_VIEWPORT_UNK0(x) (0x00000a00+((x)*4))
1058-#define NV50TCL_VIEWPORT_UNK0__SIZE 0x00000003
1059-#define NV50TCL_VIEWPORT_UNK1(x) (0x00000a0c+((x)*4))
1060-#define NV50TCL_VIEWPORT_UNK1__SIZE 0x00000003
1061+#define NV50TCL_VERTEX_ARRAY_FORMAT_STRIDE_SHIFT 0
1062+#define NV50TCL_VERTEX_ARRAY_FORMAT_STRIDE_MASK 0x000000ff
1063+#define NV50TCL_UNK0904_OFFSET_HIGH(x) (0x00000904+((x)*16))
1064+#define NV50TCL_UNK0904_OFFSET_HIGH__SIZE 0x00000010
1065+#define NV50TCL_UNK0904_OFFSET_LOW(x) (0x00000908+((x)*16))
1066+#define NV50TCL_UNK0904_OFFSET_LOW__SIZE 0x00000010
1067+#define NV50TCL_VIEWPORT_SCALE(x) (0x00000a00+((x)*4))
1068+#define NV50TCL_VIEWPORT_SCALE__SIZE 0x00000003
1069+#define NV50TCL_VIEWPORT_TRANSLATE(x) (0x00000a0c+((x)*4))
1070+#define NV50TCL_VIEWPORT_TRANSLATE__SIZE 0x00000003
1071 #define NV50TCL_VIEWPORT_HORIZ 0x00000c00
1072 #define NV50TCL_VIEWPORT_HORIZ_X_SHIFT 0
1073 #define NV50TCL_VIEWPORT_HORIZ_X_MASK 0x0000ffff
1074@@ -7339,6 +7525,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
1075 #define NV50TCL_CLEAR_COLOR__SIZE 0x00000004
1076 #define NV50TCL_CLEAR_DEPTH 0x00000d90
1077 #define NV50TCL_CLEAR_STENCIL 0x00000da0
1078+#define NV50TCL_STRMOUT_UNK0DA8 0x00000da8
1079 #define NV50TCL_POLYGON_MODE_FRONT 0x00000dac
1080 #define NV50TCL_POLYGON_MODE_FRONT_POINT 0x00001b00
1081 #define NV50TCL_POLYGON_MODE_FRONT_LINE 0x00001b01
1082@@ -7351,16 +7538,19 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
1083 #define NV50TCL_POLYGON_OFFSET_POINT_ENABLE 0x00000dc0
1084 #define NV50TCL_POLYGON_OFFSET_LINE_ENABLE 0x00000dc4
1085 #define NV50TCL_POLYGON_OFFSET_FILL_ENABLE 0x00000dc8
1086+#define NV50TCL_WINDOW_LEFT 0x00000df8
1087+#define NV50TCL_WINDOW_BOTTOM 0x00000dfc
1088+#define NV50TCL_SCISSOR_ENABLE 0x00000e00
1089 #define NV50TCL_SCISSOR_HORIZ 0x00000e04
1090 #define NV50TCL_SCISSOR_HORIZ_L_SHIFT 0
1091 #define NV50TCL_SCISSOR_HORIZ_L_MASK 0x0000ffff
1092 #define NV50TCL_SCISSOR_HORIZ_R_SHIFT 16
1093 #define NV50TCL_SCISSOR_HORIZ_R_MASK 0xffff0000
1094 #define NV50TCL_SCISSOR_VERT 0x00000e08
1095-#define NV50TCL_SCISSOR_VERT_T_SHIFT 0
1096-#define NV50TCL_SCISSOR_VERT_T_MASK 0x0000ffff
1097-#define NV50TCL_SCISSOR_VERT_B_SHIFT 16
1098-#define NV50TCL_SCISSOR_VERT_B_MASK 0xffff0000
1099+#define NV50TCL_SCISSOR_VERT_B_SHIFT 0
1100+#define NV50TCL_SCISSOR_VERT_B_MASK 0x0000ffff
1101+#define NV50TCL_SCISSOR_VERT_T_SHIFT 16
1102+#define NV50TCL_SCISSOR_VERT_T_MASK 0xffff0000
1103 #define NV50TCL_CB_ADDR 0x00000f00
1104 #define NV50TCL_CB_ADDR_ID_SHIFT 8
1105 #define NV50TCL_CB_ADDR_ID_MASK 0xffffff00
1106@@ -7375,16 +7565,40 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
1107 #define NV50TCL_GP_ADDRESS_LOW 0x00000f74
1108 #define NV50TCL_VP_ADDRESS_HIGH 0x00000f7c
1109 #define NV50TCL_VP_ADDRESS_LOW 0x00000f80
1110+#define NV50TCL_UNK0F84_ADDRESS_HIGH 0x00000f84
1111+#define NV50TCL_UNK0F84_ADDRESS_LOW 0x00000f88
1112+#define NV50TCL_DEPTH_BOUNDS(x) (0x00000f9c+((x)*4))
1113+#define NV50TCL_DEPTH_BOUNDS__SIZE 0x00000002
1114 #define NV50TCL_FP_ADDRESS_HIGH 0x00000fa4
1115 #define NV50TCL_FP_ADDRESS_LOW 0x00000fa8
1116+#define NV50TCL_MSAA_MASK(x) (0x00000fbc+((x)*4))
1117+#define NV50TCL_MSAA_MASK__SIZE 0x00000004
1118 #define NV50TCL_ZETA_ADDRESS_HIGH 0x00000fe0
1119 #define NV50TCL_ZETA_ADDRESS_LOW 0x00000fe4
1120-#define NV50TCL_UNKFF4 0x00000ff4
1121-#define NV50TCL_UNKFF4_W_SHIFT 16
1122-#define NV50TCL_UNKFF4_W_MASK 0xffff0000
1123-#define NV50TCL_UNKFF8 0x00000ff8
1124-#define NV50TCL_UNKFF8_H_SHIFT 16
1125-#define NV50TCL_UNKFF8_H_MASK 0xffff0000
1126+#define NV50TCL_ZETA_FORMAT 0x00000fe8
1127+#define NV50TCL_ZETA_FORMAT_Z32_FLOAT 0x0000000a
1128+#define NV50TCL_ZETA_FORMAT_Z24S8_UNORM 0x00000014
1129+#define NV50TCL_ZETA_FORMAT_X8Z24_UNORM 0x00000015
1130+#define NV50TCL_ZETA_FORMAT_S8Z24_UNORM 0x00000016
1131+#define NV50TCL_ZETA_FORMAT_Z32_FLOAT_X24S8_UNORM 0x00000019
1132+#define NV50TCL_ZETA_TILE_MODE 0x00000fec
1133+#define NV50TCL_ZETA_UNK 0x00000ff0
1134+#define NV50TCL_SCREEN_SCISSOR_HORIZ 0x00000ff4
1135+#define NV50TCL_SCREEN_SCISSOR_HORIZ_W_SHIFT 16
1136+#define NV50TCL_SCREEN_SCISSOR_HORIZ_W_MASK 0xffff0000
1137+#define NV50TCL_SCREEN_SCISSOR_HORIZ_X_SHIFT 0
1138+#define NV50TCL_SCREEN_SCISSOR_HORIZ_X_MASK 0x0000ffff
1139+#define NV50TCL_SCREEN_SCISSOR_VERT 0x00000ff8
1140+#define NV50TCL_SCREEN_SCISSOR_VERT_H_SHIFT 16
1141+#define NV50TCL_SCREEN_SCISSOR_VERT_H_MASK 0xffff0000
1142+#define NV50TCL_SCREEN_SCISSOR_VERT_Y_SHIFT 0
1143+#define NV50TCL_SCREEN_SCISSOR_VERT_Y_MASK 0x0000ffff
1144+#define NV50TCL_UNK1080_OFFSET_HIGH(x) (0x00001080+((x)*8))
1145+#define NV50TCL_UNK1080_OFFSET_HIGH__SIZE 0x00000010
1146+#define NV50TCL_UNK1080_OFFSET_LOW(x) (0x00001084+((x)*8))
1147+#define NV50TCL_UNK1080_OFFSET_LOW__SIZE 0x00000010
1148+#define NV50TCL_ZETA_HORIZ 0x00001228
1149+#define NV50TCL_ZETA_VERT 0x0000122c
1150 #define NV50TCL_RT_HORIZ(x) (0x00001240+((x)*8))
1151 #define NV50TCL_RT_HORIZ__SIZE 0x00000008
1152 #define NV50TCL_RT_VERT(x) (0x00001244+((x)*8))
1153@@ -7396,6 +7610,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
1154 #define NV50TCL_CB_DEF_SET_SIZE_MASK 0x0000ffff
1155 #define NV50TCL_CB_DEF_SET_BUFFER_SHIFT 16
1156 #define NV50TCL_CB_DEF_SET_BUFFER_MASK 0xffff0000
1157+#define NV50TCL_STRMOUT_BUFFERS_CTRL 0x00001294
1158+#define NV50TCL_STRMOUT_BUFFERS_CTRL_INTERLEAVED (1 << 0)
1159+#define NV50TCL_STRMOUT_BUFFERS_CTRL_SEPARATE_SHIFT 4
1160+#define NV50TCL_STRMOUT_BUFFERS_CTRL_SEPARATE_MASK 0x000000f0
1161+#define NV50TCL_STRMOUT_BUFFERS_CTRL_STRIDE_SHIFT 8
1162+#define NV50TCL_STRMOUT_BUFFERS_CTRL_STRIDE_MASK 0x0000ff00
1163+#define NV50TCL_FP_RESULT_COUNT 0x00001298
1164 #define NV50TCL_DEPTH_TEST_ENABLE 0x000012cc
1165 #define NV50TCL_SHADE_MODEL 0x000012d4
1166 #define NV50TCL_SHADE_MODEL_FLAT 0x00001d00
1167@@ -7544,11 +7765,34 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
1168 #define NV50TCL_STENCIL_BACK_FUNC_REF 0x00001394
1169 #define NV50TCL_STENCIL_BACK_MASK 0x00001398
1170 #define NV50TCL_STENCIL_BACK_FUNC_MASK 0x0000139c
1171+#define NV50TCL_FRAG_COLOR_CLAMP_EN 0x000013a8
1172 #define NV50TCL_LINE_WIDTH 0x000013b0
1173+#define NV50TCL_POINT_COORD_REPLACE_MAP(x) (0x000013c0+((x)*4))
1174+#define NV50TCL_POINT_COORD_REPLACE_MAP__SIZE 0x00000008
1175 #define NV50TCL_VP_START_ID 0x0000140c
1176 #define NV50TCL_GP_START_ID 0x00001410
1177 #define NV50TCL_FP_START_ID 0x00001414
1178+#define NV50TCL_GP_VERTEX_OUTPUT_COUNT 0x00001420
1179+#define NV50TCL_SET_SAMPLER_TEX 0x00001458
1180+#define NV50TCL_SET_SAMPLER_TEX_SAMPLER_SHIFT 1
1181+#define NV50TCL_SET_SAMPLER_TEX_SAMPLER_MASK 0x000001fe
1182+#define NV50TCL_SET_SAMPLER_TEX_TIC_SHIFT 9
1183+#define NV50TCL_SET_SAMPLER_TEX_TIC_MASK 0x0001fe00
1184+#define NV50TCL_SET_SAMPLER_TEX_VALID (1 << 0)
1185+#define NV50TCL_STRMOUT_MAP(x) (0x00001480+((x)*4))
1186+#define NV50TCL_STRMOUT_MAP__SIZE 0x00000020
1187+#define NV50TCL_VP_CLIP_DISTANCE_ENABLE 0x00001510
1188+#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_0 (1 << 0)
1189+#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_1 (1 << 1)
1190+#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_2 (1 << 2)
1191+#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_3 (1 << 3)
1192+#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_4 (1 << 4)
1193+#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_5 (1 << 5)
1194 #define NV50TCL_POINT_SIZE 0x00001518
1195+#define NV50TCL_POINT_SPRITE_ENABLE 0x00001520
1196+#define NV50TCL_MULTISAMPLE_CTRL 0x0000153c
1197+#define NV50TCL_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE (1 << 0)
1198+#define NV50TCL_MULTISAMPLE_CTRL_ALPHA_TO_ONE (1 << 4)
1199 #define NV50TCL_TSC_ADDRESS_HIGH 0x0000155c
1200 #define NV50TCL_TSC_ADDRESS_LOW 0x00001560
1201 #define NV50TCL_POLYGON_OFFSET_FACTOR 0x0000156c
1202@@ -7594,6 +7838,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
1203 #define NV50TCL_STENCIL_FRONT_FUNC_FUNC_GEQUAL 0x00000206
1204 #define NV50TCL_STENCIL_FRONT_FUNC_FUNC_ALWAYS 0x00000207
1205 #define NV50TCL_POLYGON_OFFSET_UNITS 0x000015bc
1206+#define NV50TCL_MULTISAMPLE_SAMPLES_LOG2 0x000015d0
1207 #define NV50TCL_VERTEX_BEGIN 0x000015dc
1208 #define NV50TCL_VERTEX_BEGIN_POINTS 0x00000000
1209 #define NV50TCL_VERTEX_BEGIN_LINES 0x00000001
1210@@ -7605,8 +7850,14 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
1211 #define NV50TCL_VERTEX_BEGIN_QUADS 0x00000007
1212 #define NV50TCL_VERTEX_BEGIN_QUAD_STRIP 0x00000008
1213 #define NV50TCL_VERTEX_BEGIN_POLYGON 0x00000009
1214+#define NV50TCL_VERTEX_BEGIN_LINES_ADJACENCY 0x0000000a
1215+#define NV50TCL_VERTEX_BEGIN_LINE_STRIP_ADJACENCY 0x0000000b
1216+#define NV50TCL_VERTEX_BEGIN_TRIANGLES_ADJACENCY 0x0000000c
1217+#define NV50TCL_VERTEX_BEGIN_TRIANGLE_STRIP_ADJACENCY 0x0000000d
1218 #define NV50TCL_VERTEX_END 0x000015e0
1219 #define NV50TCL_VERTEX_DATA 0x00001640
1220+#define NV50TCL_PRIM_RESTART_ENABLE 0x00001644
1221+#define NV50TCL_PRIM_RESTART_INDEX 0x00001648
1222 #define NV50TCL_VP_ATTR_EN_0 0x00001650
1223 #define NV50TCL_VP_ATTR_EN_0_7_SHIFT 28
1224 #define NV50TCL_VP_ATTR_EN_0_7_MASK 0xf0000000
1225@@ -7897,29 +8148,87 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
1226 #define NV50TCL_VP_ATTR_EN_1_8_XNZW 0x0000000d
1227 #define NV50TCL_VP_ATTR_EN_1_8_NYZW 0x0000000e
1228 #define NV50TCL_VP_ATTR_EN_1_8_XYZW 0x0000000f
1229+#define NV50TCL_POINT_SPRITE_CTRL 0x00001660
1230 #define NV50TCL_LINE_STIPPLE_ENABLE 0x0000166c
1231 #define NV50TCL_LINE_STIPPLE_PATTERN 0x00001680
1232+#define NV50TCL_VERTEX_TWO_SIDE_ENABLE 0x00001688
1233 #define NV50TCL_POLYGON_STIPPLE_ENABLE 0x0000168c
1234-#define NV50TCL_VP_REG_HPOS 0x000016bc
1235-#define NV50TCL_VP_REG_HPOS_X_SHIFT 0
1236-#define NV50TCL_VP_REG_HPOS_X_MASK 0x000000ff
1237-#define NV50TCL_VP_REG_HPOS_Y_SHIFT 8
1238-#define NV50TCL_VP_REG_HPOS_Y_MASK 0x0000ff00
1239-#define NV50TCL_VP_REG_HPOS_Z_SHIFT 16
1240-#define NV50TCL_VP_REG_HPOS_Z_MASK 0x00ff0000
1241-#define NV50TCL_VP_REG_HPOS_W_SHIFT 24
1242-#define NV50TCL_VP_REG_HPOS_W_MASK 0xff000000
1243-#define NV50TCL_VP_REG_COL0 0x000016c0
1244-#define NV50TCL_VP_REG_COL0_X_SHIFT 0
1245-#define NV50TCL_VP_REG_COL0_X_MASK 0x000000ff
1246-#define NV50TCL_VP_REG_COL0_Y_SHIFT 8
1247-#define NV50TCL_VP_REG_COL0_Y_MASK 0x0000ff00
1248-#define NV50TCL_VP_REG_COL0_Z_SHIFT 16
1249-#define NV50TCL_VP_REG_COL0_Z_MASK 0x00ff0000
1250-#define NV50TCL_VP_REG_COL0_W_SHIFT 24
1251-#define NV50TCL_VP_REG_COL0_W_MASK 0xff000000
1252+#define NV50TCL_SET_PROGRAM_CB 0x00001694
1253+#define NV50TCL_SET_PROGRAM_CB_PROGRAM_SHIFT 4
1254+#define NV50TCL_SET_PROGRAM_CB_PROGRAM_MASK 0x000000f0
1255+#define NV50TCL_SET_PROGRAM_CB_PROGRAM_VERTEX 0x00000000
1256+#define NV50TCL_SET_PROGRAM_CB_PROGRAM_GEOMETRY 0x00000020
1257+#define NV50TCL_SET_PROGRAM_CB_PROGRAM_FRAGMENT 0x00000030
1258+#define NV50TCL_SET_PROGRAM_CB_INDEX_SHIFT 8
1259+#define NV50TCL_SET_PROGRAM_CB_INDEX_MASK 0x00000f00
1260+#define NV50TCL_SET_PROGRAM_CB_BUFFER_SHIFT 12
1261+#define NV50TCL_SET_PROGRAM_CB_BUFFER_MASK 0x000ff000
1262+#define NV50TCL_SET_PROGRAM_CB_VALID (1 << 0)
1263+#define NV50TCL_VP_RESULT_MAP_SIZE 0x000016ac
1264+#define NV50TCL_VP_REG_ALLOC_TEMP 0x000016b0
1265+#define NV50TCL_VP_REG_ALLOC_RESULT 0x000016b8
1266+#define NV50TCL_VP_RESULT_MAP(x) (0x000016bc+((x)*4))
1267+#define NV50TCL_VP_RESULT_MAP__SIZE 0x00000008
1268+#define NV50TCL_VP_RESULT_MAP_0_SHIFT 0
1269+#define NV50TCL_VP_RESULT_MAP_0_MASK 0x000000ff
1270+#define NV50TCL_VP_RESULT_MAP_1_SHIFT 8
1271+#define NV50TCL_VP_RESULT_MAP_1_MASK 0x0000ff00
1272+#define NV50TCL_VP_RESULT_MAP_2_SHIFT 16
1273+#define NV50TCL_VP_RESULT_MAP_2_MASK 0x00ff0000
1274+#define NV50TCL_VP_RESULT_MAP_3_SHIFT 24
1275+#define NV50TCL_VP_RESULT_MAP_3_MASK 0xff000000
1276 #define NV50TCL_POLYGON_STIPPLE_PATTERN(x) (0x00001700+((x)*4))
1277 #define NV50TCL_POLYGON_STIPPLE_PATTERN__SIZE 0x00000020
1278+#define NV50TCL_GP_ENABLE 0x00001798
1279+#define NV50TCL_GP_REG_ALLOC_TEMP 0x000017a0
1280+#define NV50TCL_GP_REG_ALLOC_RESULT 0x000017a8
1281+#define NV50TCL_GP_RESULT_MAP_SIZE 0x000017ac
1282+#define NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE 0x000017b0
1283+#define NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE_POINTS 0x00000001
1284+#define NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE_LINE_STRIP 0x00000002
1285+#define NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE_TRIANGLE_STRIP 0x00000003
1286+#define NV50TCL_RASTERIZE_ENABLE 0x000017b4
1287+#define NV50TCL_GP_RESULT_MAP(x) (0x000017fc+((x)*4))
1288+#define NV50TCL_GP_RESULT_MAP__SIZE 0x00000008
1289+#define NV50TCL_GP_RESULT_MAP_0_SHIFT 0
1290+#define NV50TCL_GP_RESULT_MAP_0_MASK 0x000000ff
1291+#define NV50TCL_GP_RESULT_MAP_1_SHIFT 8
1292+#define NV50TCL_GP_RESULT_MAP_1_MASK 0x0000ff00
1293+#define NV50TCL_GP_RESULT_MAP_2_SHIFT 16
1294+#define NV50TCL_GP_RESULT_MAP_2_MASK 0x00ff0000
1295+#define NV50TCL_GP_RESULT_MAP_3_SHIFT 24
1296+#define NV50TCL_GP_RESULT_MAP_3_MASK 0xff000000
1297+#define NV50TCL_MAP_SEMANTIC_0 0x00001904
1298+#define NV50TCL_MAP_SEMANTIC_0_FFC0_ID_SHIFT 0
1299+#define NV50TCL_MAP_SEMANTIC_0_FFC0_ID_MASK 0x000000ff
1300+#define NV50TCL_MAP_SEMANTIC_0_BFC0_ID_SHIFT 8
1301+#define NV50TCL_MAP_SEMANTIC_0_BFC0_ID_MASK 0x0000ff00
1302+#define NV50TCL_MAP_SEMANTIC_0_COLR_NR_SHIFT 16
1303+#define NV50TCL_MAP_SEMANTIC_0_COLR_NR_MASK 0x00ff0000
1304+#define NV50TCL_MAP_SEMANTIC_0_CLMP_EN_SHIFT 24
1305+#define NV50TCL_MAP_SEMANTIC_0_CLMP_EN_MASK 0xff000000
1306+#define NV50TCL_MAP_SEMANTIC_1 0x00001908
1307+#define NV50TCL_MAP_SEMANTIC_1_CLIP_LO_SHIFT 0
1308+#define NV50TCL_MAP_SEMANTIC_1_CLIP_LO_MASK 0x000000ff
1309+#define NV50TCL_MAP_SEMANTIC_1_CLIP_HI_SHIFT 8
1310+#define NV50TCL_MAP_SEMANTIC_1_CLIP_HI_MASK 0x0000ff00
1311+#define NV50TCL_MAP_SEMANTIC_1_UNKN_02_SHIFT 16
1312+#define NV50TCL_MAP_SEMANTIC_1_UNKN_02_MASK 0x00ff0000
1313+#define NV50TCL_MAP_SEMANTIC_1_UNKN_03_SHIFT 24
1314+#define NV50TCL_MAP_SEMANTIC_1_UNKN_03_MASK 0xff000000
1315+#define NV50TCL_MAP_SEMANTIC_2 0x0000190c
1316+#define NV50TCL_MAP_SEMANTIC_2_UNKN_00_SHIFT 0
1317+#define NV50TCL_MAP_SEMANTIC_2_UNKN_00_MASK 0x000000ff
1318+#define NV50TCL_MAP_SEMANTIC_2_UNKN_01_SHIFT 8
1319+#define NV50TCL_MAP_SEMANTIC_2_UNKN_01_MASK 0x0000ff00
1320+#define NV50TCL_MAP_SEMANTIC_2_UNKN_02_SHIFT 16
1321+#define NV50TCL_MAP_SEMANTIC_2_UNKN_02_MASK 0x00ff0000
1322+#define NV50TCL_MAP_SEMANTIC_2_UNKN_03_SHIFT 24
1323+#define NV50TCL_MAP_SEMANTIC_2_UNKN_03_MASK 0xff000000
1324+#define NV50TCL_MAP_SEMANTIC_3 0x00001910
1325+#define NV50TCL_MAP_SEMANTIC_3_PTSZ_EN (1 << 0)
1326+#define NV50TCL_MAP_SEMANTIC_3_PTSZ_ID_SHIFT 4
1327+#define NV50TCL_MAP_SEMANTIC_3_PTSZ_ID_MASK 0x00000ff0
1328 #define NV50TCL_CULL_FACE_ENABLE 0x00001918
1329 #define NV50TCL_FRONT_FACE 0x0000191c
1330 #define NV50TCL_FRONT_FACE_CW 0x00000900
1331@@ -7928,6 +8237,39 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
1332 #define NV50TCL_CULL_FACE_FRONT 0x00000404
1333 #define NV50TCL_CULL_FACE_BACK 0x00000405
1334 #define NV50TCL_CULL_FACE_FRONT_AND_BACK 0x00000408
1335+#define NV50TCL_VIEWPORT_TRANSFORM_EN 0x0000192c
1336+#define NV50TCL_VIEW_VOLUME_CLIP_CTRL 0x0000193c
1337+#define NV50TCL_FP_CTRL_UNK196C 0x0000196c
1338+#define NV50TCL_FP_INTERPOLANT_CTRL 0x00001988
1339+#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_SHIFT 24
1340+#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_MASK 0xff000000
1341+#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NONE 0x00000000
1342+#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XNNN 0x01000000
1343+#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NYNN 0x02000000
1344+#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XYNN 0x03000000
1345+#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NNZN 0x04000000
1346+#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XNZN 0x05000000
1347+#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NYZN 0x06000000
1348+#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XYZN 0x07000000
1349+#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NNNW 0x08000000
1350+#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XNNW 0x09000000
1351+#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NYNW 0x0a000000
1352+#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XYNW 0x0b000000
1353+#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NNZW 0x0c000000
1354+#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XNZW 0x0d000000
1355+#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NYZW 0x0e000000
1356+#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XYZW 0x0f000000
1357+#define NV50TCL_FP_INTERPOLANT_CTRL_COUNT_SHIFT 16
1358+#define NV50TCL_FP_INTERPOLANT_CTRL_COUNT_MASK 0x00ff0000
1359+#define NV50TCL_FP_INTERPOLANT_CTRL_OFFSET_SHIFT 8
1360+#define NV50TCL_FP_INTERPOLANT_CTRL_OFFSET_MASK 0x0000ff00
1361+#define NV50TCL_FP_INTERPOLANT_CTRL_COUNT_UNK_SHIFT 0
1362+#define NV50TCL_FP_INTERPOLANT_CTRL_COUNT_UNK_MASK 0x000000ff
1363+#define NV50TCL_FP_REG_ALLOC_TEMP 0x0000198c
1364+#define NV50TCL_FP_CTRL_UNK19A8 0x000019a8
1365+#define NV50TCL_FP_CTRL_UNK19A8_DEP (1 << 20)
1366+#define NV50TCL_FP_CTRL_UNK19A8_KIL (1 << 8)
1367+#define NV50TCL_DEPTH_BOUNDS_EN 0x000019bc
1368 #define NV50TCL_LOGIC_OP_ENABLE 0x000019c4
1369 #define NV50TCL_LOGIC_OP 0x000019c8
1370 #define NV50TCL_LOGIC_OP_CLEAR 0x00001500
1371@@ -7957,6 +8299,43 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
1372 #define NV50TCL_COLOR_MASK_B_MASK 0x00000f00
1373 #define NV50TCL_COLOR_MASK_A_SHIFT 12
1374 #define NV50TCL_COLOR_MASK_A_MASK 0x0000f000
1375+#define NV50TCL_STRMOUT_ADDRESS_HIGH(x) (0x00001a80+((x)*16))
1376+#define NV50TCL_STRMOUT_ADDRESS_HIGH__SIZE 0x00000004
1377+#define NV50TCL_STRMOUT_ADDRESS_LOW(x) (0x00001a84+((x)*16))
1378+#define NV50TCL_STRMOUT_ADDRESS_LOW__SIZE 0x00000004
1379+#define NV50TCL_STRMOUT_NUM_ATTRIBS(x) (0x00001a88+((x)*16))
1380+#define NV50TCL_STRMOUT_NUM_ATTRIBS__SIZE 0x00000004
1381+#define NV50TCL_VERTEX_ARRAY_ATTRIB(x) (0x00001ac0+((x)*4))
1382+#define NV50TCL_VERTEX_ARRAY_ATTRIB__SIZE 0x00000010
1383+#define NV50TCL_VERTEX_ARRAY_ATTRIB_BUFFER_SHIFT 0
1384+#define NV50TCL_VERTEX_ARRAY_ATTRIB_BUFFER_MASK 0x000000ff
1385+#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_SHIFT 16
1386+#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_MASK 0x00ff0000
1387+#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_32_32_32_32 0x00080000
1388+#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_32_32_32 0x00100000
1389+#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_32_32 0x00200000
1390+#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_32 0x00900000
1391+#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_16_16_16_16 0x00180000
1392+#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_16_16_16 0x00280000
1393+#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_16_16 0x00780000
1394+#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_16 0x00d80000
1395+#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_8_8_8_8 0x00500000
1396+#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_8_8_8 0x00980000
1397+#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_8_8 0x00c00000
1398+#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_8 0x00e80000
1399+#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_SHIFT 24
1400+#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_MASK 0xff000000
1401+#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_FLOAT 0x7e000000
1402+#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_UNORM 0x24000000
1403+#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_SNORM 0x12000000
1404+#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_USCALED 0x5a000000
1405+#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_SSCALED 0x6c000000
1406+#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_UINT 0x48000000
1407+#define NV50TCL_VERTEX_ARRAY_ATTRIB_TYPE_SINT 0x36000000
1408+#define NV50TCL_QUERY_ADDRESS_HIGH 0x00001b00
1409+#define NV50TCL_QUERY_ADDRESS_LOW 0x00001b04
1410+#define NV50TCL_QUERY_COUNTER 0x00001b08
1411+#define NV50TCL_QUERY_GET 0x00001b0c
1412
1413
1414 #define NV50_COMPUTE 0x000050c0
1415@@ -8003,4 +8382,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
1416
1417
1418
1419+#define NVA0TCL 0x00008397
1420+
1421+
1422+
1423 #endif /* NOUVEAU_REG_H */
1424diff --git a/libdrm/nouveau/nouveau_device.c b/libdrm/nouveau/nouveau_device.c
1425index 6b99e36..0982d3b 100644
1426--- a/libdrm/nouveau/nouveau_device.c
1427+++ b/libdrm/nouveau/nouveau_device.c
1428@@ -26,7 +26,7 @@
1429
1430 #include "nouveau_private.h"
1431
1432-#if NOUVEAU_DRM_HEADER_PATCHLEVEL != 14
1433+#if NOUVEAU_DRM_HEADER_PATCHLEVEL != 15
1434 #error nouveau_drm.h does not match expected patchlevel, update libdrm.
1435 #endif
1436
1437@@ -61,14 +61,6 @@ nouveau_device_open_existing(struct nouveau_device **dev, int close,
1438 }
1439
1440 ret = nouveau_device_get_param(&nvdev->base,
1441- NOUVEAU_GETPARAM_MM_ENABLED, &value);
1442- if (ret) {
1443- nouveau_device_close((void *)&nvdev);
1444- return ret;
1445- }
1446- nvdev->mm_enabled = value;
1447-
1448- ret = nouveau_device_get_param(&nvdev->base,
1449 NOUVEAU_GETPARAM_VM_VRAM_BASE, &value);
1450 if (ret) {
1451 nouveau_device_close((void *)&nvdev);
1452diff --git a/libdrm/nouveau/nouveau_dma.c b/libdrm/nouveau/nouveau_dma.c
1453deleted file mode 100644
1454index b084f70..0000000
1455--- a/libdrm/nouveau/nouveau_dma.c
1456+++ /dev/null
1457@@ -1,217 +0,0 @@
1458-/*
1459- * Copyright 2007 Nouveau Project
1460- *
1461- * Permission is hereby granted, free of charge, to any person obtaining a
1462- * copy of this software and associated documentation files (the "Software"),
1463- * to deal in the Software without restriction, including without limitation
1464- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
1465- * and/or sell copies of the Software, and to permit persons to whom the
1466- * Software is furnished to do so, subject to the following conditions:
1467- *
1468- * The above copyright notice and this permission notice shall be included in
1469- * all copies or substantial portions of the Software.
1470- *
1471- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1472- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1473- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
1474- * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
1475- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
1476- * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
1477- * SOFTWARE.
1478- */
1479-
1480-#include <stdint.h>
1481-#include <stdio.h>
1482-#include <assert.h>
1483-#include <errno.h>
1484-
1485-#include "nouveau_drmif.h"
1486-#include "nouveau_dma.h"
1487-
1488-static inline uint32_t
1489-READ_GET(struct nouveau_channel_priv *nvchan)
1490-{
1491- return *nvchan->get;
1492-}
1493-
1494-static inline void
1495-WRITE_PUT(struct nouveau_channel_priv *nvchan, uint32_t val)
1496-{
1497- uint32_t put = ((val << 2) + nvchan->dma->base);
1498- volatile int dum;
1499-
1500- NOUVEAU_DMA_BARRIER;
1501- dum = nvchan->pushbuf[0];
1502- dum = READ_GET(nvchan);
1503-
1504- *nvchan->put = put;
1505- nvchan->dma->put = val;
1506-#ifdef NOUVEAU_DMA_TRACE
1507- printf("WRITE_PUT %d/0x%08x\n", nvchan->drm.channel, put);
1508-#endif
1509-
1510- NOUVEAU_DMA_BARRIER;
1511-}
1512-
1513-static inline int
1514-LOCAL_GET(struct nouveau_dma_priv *dma, uint32_t *val)
1515-{
1516- uint32_t get = *val;
1517-
1518- if (get >= dma->base && get <= (dma->base + (dma->max << 2))) {
1519- *val = (get - dma->base) >> 2;
1520- return 1;
1521- }
1522-
1523- return 0;
1524-}
1525-
1526-void
1527-nouveau_dma_channel_init(struct nouveau_channel *chan)
1528-{
1529- struct nouveau_channel_priv *nvchan = nouveau_channel(chan);
1530- int i;
1531-
1532- nvchan->dma = &nvchan->struct_dma;
1533- nvchan->dma->base = nvchan->drm.put_base;
1534- nvchan->dma->cur = nvchan->dma->put = 0;
1535- nvchan->dma->max = (nvchan->drm.cmdbuf_size >> 2) - 2;
1536- nvchan->dma->free = nvchan->dma->max - nvchan->dma->cur;
1537-
1538- RING_SPACE_CH(chan, RING_SKIPS);
1539- for (i = 0; i < RING_SKIPS; i++)
1540- OUT_RING_CH(chan, 0);
1541-}
1542-
1543-#define CHECK_TIMEOUT() do { \
1544- if ((NOUVEAU_TIME_MSEC() - t_start) > NOUVEAU_DMA_TIMEOUT) \
1545- return - EBUSY; \
1546-} while(0)
1547-
1548-int
1549-nouveau_dma_wait(struct nouveau_channel *chan, unsigned size)
1550-{
1551- struct nouveau_channel_priv *nvchan = nouveau_channel(chan);
1552- struct nouveau_dma_priv *dma = nvchan->dma;
1553- uint32_t get, t_start;
1554-
1555- FIRE_RING_CH(chan);
1556-
1557- t_start = NOUVEAU_TIME_MSEC();
1558- while (dma->free < size) {
1559- CHECK_TIMEOUT();
1560-
1561- get = READ_GET(nvchan);
1562- if (!LOCAL_GET(dma, &get))
1563- continue;
1564-
1565- if (dma->put >= get) {
1566- dma->free = dma->max - dma->cur;
1567-
1568- if (dma->free < size) {
1569-#ifdef NOUVEAU_DMA_DEBUG
1570- dma->push_free = 1;
1571-#endif
1572- OUT_RING_CH(chan, 0x20000000 | dma->base);
1573- if (get <= RING_SKIPS) {
1574- /*corner case - will be idle*/
1575- if (dma->put <= RING_SKIPS)
1576- WRITE_PUT(nvchan,
1577- RING_SKIPS + 1);
1578-
1579- do {
1580- CHECK_TIMEOUT();
1581- get = READ_GET(nvchan);
1582- if (!LOCAL_GET(dma, &get))
1583- get = 0;
1584- } while (get <= RING_SKIPS);
1585- }
1586-
1587- WRITE_PUT(nvchan, RING_SKIPS);
1588- dma->cur = dma->put = RING_SKIPS;
1589- dma->free = get - (RING_SKIPS + 1);
1590- }
1591- } else {
1592- dma->free = get - dma->cur - 1;
1593- }
1594- }
1595-
1596- return 0;
1597-}
1598-
1599-#ifdef NOUVEAU_DMA_DUMP_POSTRELOC_PUSHBUF
1600-static void
1601-nouveau_dma_parse_pushbuf(struct nouveau_channel *chan, int get, int put)
1602-{
1603- struct nouveau_channel_priv *nvchan = nouveau_channel(chan);
1604- unsigned mthd_count = 0;
1605-
1606- while (get != put) {
1607- uint32_t gpuget = (get << 2) + nvchan->drm.put_base;
1608- uint32_t data;
1609-
1610- if (get < 0 || get >= nvchan->drm.cmdbuf_size)
1611- assert(0);
1612- data = nvchan->pushbuf[get++];
1613-
1614- if (mthd_count) {
1615- printf("0x%08x 0x%08x\n", gpuget, data);
1616- mthd_count--;
1617- continue;
1618- }
1619-
1620- switch (data & 0x60000000) {
1621- case 0x00000000:
1622- mthd_count = (data >> 18) & 0x7ff;
1623- printf("0x%08x 0x%08x MTHD "
1624- "Sc %d Mthd 0x%04x Size %d\n",
1625- gpuget, data, (data>>13) & 7, data & 0x1ffc,
1626- mthd_count);
1627- break;
1628- case 0x20000000:
1629- get = (data & 0x1ffffffc) >> 2;
1630- printf("0x%08x 0x%08x JUMP 0x%08x\n",
1631- gpuget, data, data & 0x1ffffffc);
1632- continue;
1633- case 0x40000000:
1634- mthd_count = (data >> 18) & 0x7ff;
1635- printf("0x%08x 0x%08x NINC "
1636- "Sc %d Mthd 0x%04x Size %d\n",
1637- gpuget, data, (data>>13) & 7, data & 0x1ffc,
1638- mthd_count);
1639- break;
1640- case 0x60000000:
1641- /* DMA_OPCODE_CALL apparently, doesn't seem to work on
1642- * my NV40 at least..
1643- */
1644- /* fall-through */
1645- default:
1646- printf("DMA_PUSHER 0x%08x 0x%08x\n", gpuget, data);
1647- assert(0);
1648- }
1649- }
1650-}
1651-#endif
1652-
1653-void
1654-nouveau_dma_kickoff(struct nouveau_channel *chan)
1655-{
1656- struct nouveau_channel_priv *nvchan = nouveau_channel(chan);
1657- struct nouveau_dma_priv *dma = nvchan->dma;
1658-
1659- if (dma->cur == dma->put)
1660- return;
1661-
1662-#ifdef NOUVEAU_DMA_DEBUG
1663- if (dma->push_free) {
1664- printf("Packet incomplete: %d left\n", dma->push_free);
1665- return;
1666- }
1667-#endif
1668-
1669-#ifdef NOUVEAU_DMA_DUMP_POSTRELOC_PUSHBUF
1670- nouveau_dma_parse_pushbuf(chan, dma->put, dma->cur);
1671-#endif
1672-
1673- WRITE_PUT(nvchan, dma->cur);
1674-}
1675diff --git a/libdrm/nouveau/nouveau_dma.h b/libdrm/nouveau/nouveau_dma.h
1676deleted file mode 100644
1677index 38fe1d6..0000000
1678--- a/libdrm/nouveau/nouveau_dma.h
1679+++ /dev/null
1680@@ -1,154 +0,0 @@
1681-/*
1682- * Copyright 2007 Nouveau Project
1683- *
1684- * Permission is hereby granted, free of charge, to any person obtaining a
1685- * copy of this software and associated documentation files (the "Software"),
1686- * to deal in the Software without restriction, including without limitation
1687- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
1688- * and/or sell copies of the Software, and to permit persons to whom the
1689- * Software is furnished to do so, subject to the following conditions:
1690- *
1691- * The above copyright notice and this permission notice shall be included in
1692- * all copies or substantial portions of the Software.
1693- *
1694- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1695- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1696- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
1697- * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
1698- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
1699- * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
1700- * SOFTWARE.
1701- */
1702-
1703-#ifndef __NOUVEAU_DMA_H__
1704-#define __NOUVEAU_DMA_H__
1705-
1706-#include <string.h>
1707-#include "nouveau_private.h"
1708-
1709-//#define NOUVEAU_DMA_DEBUG
1710-//#define NOUVEAU_DMA_TRACE
1711-//#define NOUVEAU_DMA_DUMP_POSTRELOC_PUSHBUF
1712-#if defined(__amd64__)
1713-#define NOUVEAU_DMA_BARRIER asm volatile("lock; addl $0,0(%%rsp)" ::: "memory")
1714-#elif defined(__i386__)
1715-#define NOUVEAU_DMA_BARRIER asm volatile("lock; addl $0,0(%%esp)" ::: "memory")
1716-#else
1717-#define NOUVEAU_DMA_BARRIER
1718-#endif
1719-#define NOUVEAU_DMA_TIMEOUT 2000
1720-#define NOUVEAU_TIME_MSEC() 0
1721-#define RING_SKIPS 8
1722-
1723-extern int nouveau_dma_wait(struct nouveau_channel *chan, unsigned size);
1724-extern void nouveau_dma_subc_bind(struct nouveau_grobj *);
1725-extern void nouveau_dma_channel_init(struct nouveau_channel *);
1726-extern void nouveau_dma_kickoff(struct nouveau_channel *);
1727-
1728-#ifdef NOUVEAU_DMA_DEBUG
1729-static char faulty[1024];
1730-#endif
1731-
1732-static inline void
1733-nouveau_dma_out(struct nouveau_channel *chan, uint32_t data)
1734-{
1735- struct nouveau_channel_priv *nvchan = nouveau_channel(chan);
1736- struct nouveau_dma_priv *dma = nvchan->dma;
1737-
1738-#ifdef NOUVEAU_DMA_DEBUG
1739- if (dma->push_free == 0) {
1740- printf("No space left in packet at %s\n", faulty);
1741- return;
1742- }
1743- dma->push_free--;
1744-#endif
1745-#ifdef NOUVEAU_DMA_TRACE
1746- {
1747- uint32_t offset = (dma->cur << 2) + dma->base;
1748- printf("\tOUT_RING %d/0x%08x -> 0x%08x\n",
1749- nvchan->drm.channel, offset, data);
1750- }
1751-#endif
1752- nvchan->pushbuf[dma->cur + (dma->base - nvchan->drm.put_base)/4] = data;
1753- dma->cur++;
1754-}
1755-
1756-static inline void
1757-nouveau_dma_outp(struct nouveau_channel *chan, uint32_t *ptr, int size)
1758-{
1759- struct nouveau_channel_priv *nvchan = nouveau_channel(chan);
1760- struct nouveau_dma_priv *dma = nvchan->dma;
1761- (void)dma;
1762-
1763-#ifdef NOUVEAU_DMA_DEBUG
1764- if (dma->push_free < size) {
1765- printf("Packet too small. Free=%d, Need=%d\n",
1766- dma->push_free, size);
1767- return;
1768- }
1769-#endif
1770-#ifdef NOUVEAU_DMA_TRACE
1771- while (size--) {
1772- nouveau_dma_out(chan, *ptr);
1773- ptr++;
1774- }
1775-#else
1776- memcpy(&nvchan->pushbuf[dma->cur], ptr, size << 2);
1777-#ifdef NOUVEAU_DMA_DEBUG
1778- dma->push_free -= size;
1779-#endif
1780- dma->cur += size;
1781-#endif
1782-}
1783-
1784-static inline void
1785-nouveau_dma_space(struct nouveau_channel *chan, unsigned size)
1786-{
1787- struct nouveau_channel_priv *nvchan = nouveau_channel(chan);
1788- struct nouveau_dma_priv *dma = nvchan->dma;
1789-
1790- if (dma->free < size) {
1791- if (nouveau_dma_wait(chan, size) && chan->hang_notify)
1792- chan->hang_notify(chan);
1793- }
1794- dma->free -= size;
1795-#ifdef NOUVEAU_DMA_DEBUG
1796- dma->push_free = size;
1797-#endif
1798-}
1799-
1800-static inline void
1801-nouveau_dma_begin(struct nouveau_channel *chan, struct nouveau_grobj *grobj,
1802- int method, int size, const char* file, int line)
1803-{
1804- struct nouveau_channel_priv *nvchan = nouveau_channel(chan);
1805- struct nouveau_dma_priv *dma = nvchan->dma;
1806- (void)dma;
1807-
1808-#ifdef NOUVEAU_DMA_TRACE
1809- printf("BEGIN_RING %d/%08x/%d/0x%04x/%d\n", nvchan->drm.channel,
1810- grobj->handle, grobj->subc, method, size);
1811-#endif
1812-
1813-#ifdef NOUVEAU_DMA_DEBUG
1814- if (dma->push_free) {
1815- printf("Previous packet incomplete: %d left at %s\n",
1816- dma->push_free, faulty);
1817- return;
1818- }
1819- sprintf(faulty,"%s:%d",file,line);
1820-#endif
1821-
1822- nouveau_dma_space(chan, (size + 1));
1823- nouveau_dma_out(chan, (size << 18) | (grobj->subc << 13) | method);
1824-}
1825-
1826-#define RING_SPACE_CH(ch,sz) nouveau_dma_space((ch), (sz))
1827-#define BEGIN_RING_CH(ch,gr,m,sz) nouveau_dma_begin((ch), (gr), (m), (sz), __FUNCTION__, __LINE__ )
1828-#define OUT_RING_CH(ch, data) nouveau_dma_out((ch), (data))
1829-#define OUT_RINGp_CH(ch,ptr,dwords) nouveau_dma_outp((ch), (void*)(ptr), \
1830- (dwords))
1831-#define FIRE_RING_CH(ch) nouveau_dma_kickoff((ch))
1832-#define WAIT_RING_CH(ch,sz) nouveau_dma_wait((ch), (sz))
1833-
1834-#endif
1835diff --git a/libdrm/nouveau/nouveau_drmif.h b/libdrm/nouveau/nouveau_drmif.h
1836index c21fba2..bc860d2 100644
1837--- a/libdrm/nouveau/nouveau_drmif.h
1838+++ b/libdrm/nouveau/nouveau_drmif.h
1839@@ -35,8 +35,6 @@ struct nouveau_device_priv {
1840 drm_context_t ctx;
1841 drmLock *lock;
1842 int needs_close;
1843-
1844- int mm_enabled;
1845 };
1846 #define nouveau_device(n) ((struct nouveau_device_priv *)(n))
1847
1848diff --git a/libdrm/nouveau/nouveau_fence.c b/libdrm/nouveau/nouveau_fence.c
1849deleted file mode 100644
1850index 3346616..0000000
1851--- a/libdrm/nouveau/nouveau_fence.c
1852+++ /dev/null
1853@@ -1,243 +0,0 @@
1854-/*
1855- * Copyright 2007 Nouveau Project
1856- *
1857- * Permission is hereby granted, free of charge, to any person obtaining a
1858- * copy of this software and associated documentation files (the "Software"),
1859- * to deal in the Software without restriction, including without limitation
1860- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
1861- * and/or sell copies of the Software, and to permit persons to whom the
1862- * Software is furnished to do so, subject to the following conditions:
1863- *
1864- * The above copyright notice and this permission notice shall be included in
1865- * all copies or substantial portions of the Software.
1866- *
1867- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1868- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1869- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
1870- * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
1871- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
1872- * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
1873- * SOFTWARE.
1874- */
1875-
1876-#include <stdio.h>
1877-#include <stdlib.h>
1878-#include <errno.h>
1879-#include <assert.h>
1880-
1881-#include "nouveau_private.h"
1882-#include "nouveau_dma.h"
1883-
1884-static void
1885-nouveau_fence_del_unsignalled(struct nouveau_fence *fence)
1886-{
1887- struct nouveau_channel_priv *nvchan = nouveau_channel(fence->channel);
1888- struct nouveau_fence *le;
1889-
1890- if (nvchan->fence_head == fence) {
1891- nvchan->fence_head = nouveau_fence(fence)->next;
1892- if (nvchan->fence_head == NULL)
1893- nvchan->fence_tail = NULL;
1894- return;
1895- }
1896-
1897- le = nvchan->fence_head;
1898- while (le && nouveau_fence(le)->next != fence)
1899- le = nouveau_fence(le)->next;
1900- assert(le && nouveau_fence(le)->next == fence);
1901- nouveau_fence(le)->next = nouveau_fence(fence)->next;
1902- if (nvchan->fence_tail == fence)
1903- nvchan->fence_tail = le;
1904-}
1905-
1906-static void
1907-nouveau_fence_del(struct nouveau_fence **fence)
1908-{
1909- struct nouveau_fence_priv *nvfence;
1910-
1911- if (!fence || !*fence)
1912- return;
1913- nvfence = nouveau_fence(*fence);
1914- *fence = NULL;
1915-
1916- if (--nvfence->refcount)
1917- return;
1918-
1919- if (nvfence->emitted && !nvfence->signalled) {
1920- if (nvfence->signal_cb) {
1921- nvfence->refcount++;
1922- nouveau_fence_wait((void *)&nvfence);
1923- return;
1924- }
1925-
1926- nouveau_fence_del_unsignalled(&nvfence->base);
1927- }
1928- free(nvfence);
1929-}
1930-
1931-int
1932-nouveau_fence_new(struct nouveau_channel *chan, struct nouveau_fence **fence)
1933-{
1934- struct nouveau_fence_priv *nvfence;
1935-
1936- if (!chan || !fence || *fence)
1937- return -EINVAL;
1938-
1939- nvfence = calloc(1, sizeof(struct nouveau_fence_priv));
1940- if (!nvfence)
1941- return -ENOMEM;
1942- nvfence->base.channel = chan;
1943- nvfence->refcount = 1;
1944-
1945- *fence = &nvfence->base;
1946- return 0;
1947-}
1948-
1949-int
1950-nouveau_fence_ref(struct nouveau_fence *ref, struct nouveau_fence **fence)
1951-{
1952- if (!fence)
1953- return -EINVAL;
1954-
1955- if (ref)
1956- nouveau_fence(ref)->refcount++;
1957-
1958- if (*fence)
1959- nouveau_fence_del(fence);
1960-
1961- *fence = ref;
1962- return 0;
1963-}
1964-
1965-int
1966-nouveau_fence_signal_cb(struct nouveau_fence *fence, void (*func)(void *),
1967- void *priv)
1968-{
1969- struct nouveau_fence_priv *nvfence = nouveau_fence(fence);
1970- struct nouveau_fence_cb *cb;
1971-
1972- if (!nvfence || !func)
1973- return -EINVAL;
1974-
1975- cb = malloc(sizeof(struct nouveau_fence_cb));
1976- if (!cb)
1977- return -ENOMEM;
1978-
1979- cb->func = func;
1980- cb->priv = priv;
1981- cb->next = nvfence->signal_cb;
1982- nvfence->signal_cb = cb;
1983- return 0;
1984-}
1985-
1986-void
1987-nouveau_fence_emit(struct nouveau_fence *fence)
1988-{
1989- struct nouveau_channel_priv *nvchan = nouveau_channel(fence->channel);
1990- struct nouveau_fence_priv *nvfence = nouveau_fence(fence);
1991-
1992- nvfence->emitted = 1;
1993- nvfence->sequence = ++nvchan->fence_sequence;
1994- if (nvfence->sequence == 0xffffffff)
1995- printf("AII wrap unhandled\n");
1996-
1997- if (!nvchan->fence_ntfy) {
1998- /*XXX: assumes subc 0 is populated */
1999- nouveau_dma_space(fence->channel, 2);
2000- nouveau_dma_out (fence->channel, 0x00040050);
2001- nouveau_dma_out (fence->channel, nvfence->sequence);
2002- }
2003- nouveau_dma_kickoff(fence->channel);
2004-
2005- if (nvchan->fence_tail) {
2006- nouveau_fence(nvchan->fence_tail)->next = fence;
2007- } else {
2008- nvchan->fence_head = fence;
2009- }
2010- nvchan->fence_tail = fence;
2011-}
2012-
2013-static void
2014-nouveau_fence_flush_seq(struct nouveau_channel *chan, uint32_t sequence)
2015-{
2016- struct nouveau_channel_priv *nvchan = nouveau_channel(chan);
2017-
2018- while (nvchan->fence_head) {
2019- struct nouveau_fence_priv *nvfence;
2020-
2021- nvfence = nouveau_fence(nvchan->fence_head);
2022- if (nvfence->sequence > sequence)
2023- break;
2024- nouveau_fence_del_unsignalled(&nvfence->base);
2025- nvfence->signalled = 1;
2026-
2027- if (nvfence->signal_cb) {
2028- struct nouveau_fence *fence = NULL;
2029-
2030- nouveau_fence_ref(&nvfence->base, &fence);
2031-
2032- while (nvfence->signal_cb) {
2033- struct nouveau_fence_cb *cb;
2034-
2035- cb = nvfence->signal_cb;
2036- nvfence->signal_cb = cb->next;
2037- cb->func(cb->priv);
2038- free(cb);
2039- }
2040-
2041- nouveau_fence_ref(NULL, &fence);
2042- }
2043- }
2044-}
2045-
2046-void
2047-nouveau_fence_flush(struct nouveau_channel *chan)
2048-{
2049- struct nouveau_channel_priv *nvchan = nouveau_channel(chan);
2050-
2051- if (!nvchan->fence_ntfy)
2052- nouveau_fence_flush_seq(chan, *nvchan->ref_cnt);
2053-}
2054-
2055-int
2056-nouveau_fence_wait(struct nouveau_fence **fence)
2057-{
2058- struct nouveau_fence_priv *nvfence;
2059- struct nouveau_channel_priv *nvchan;
2060-
2061- if (!fence)
2062- return -EINVAL;
2063-
2064- nvfence = nouveau_fence(*fence);
2065- if (!nvfence)
2066- return 0;
2067- nvchan = nouveau_channel(nvfence->base.channel);
2068-
2069- if (nvfence->emitted) {
2070- if (!nvfence->signalled && nvchan->fence_ntfy) {
2071- struct nouveau_channel *chan = &nvchan->base;
2072- int ret;
2073-
2074- /*XXX: NV04/NV05: Full sync + flush all fences */
2075- nouveau_notifier_reset(nvchan->fence_ntfy, 0);
2076- BEGIN_RING(chan, nvchan->fence_grobj, 0x0104, 1);
2077- OUT_RING (chan, 0);
2078- BEGIN_RING(chan, nvchan->fence_grobj, 0x0100, 1);
2079- OUT_RING (chan, 0);
2080- FIRE_RING (chan);
2081- ret = nouveau_notifier_wait_status(nvchan->fence_ntfy,
2082- 0, 0, 2.0);
2083- if (ret)
2084- return ret;
2085-
2086- nouveau_fence_flush_seq(chan, nvchan->fence_sequence);
2087- }
2088-
2089- while (!nvfence->signalled)
2090- nouveau_fence_flush(nvfence->base.channel);
2091- }
2092-
2093- nouveau_fence_ref(NULL, fence);
2094- return 0;
2095-}
2096-
2097diff --git a/libdrm/nouveau/nouveau_notifier.c b/libdrm/nouveau/nouveau_notifier.c
2098index 8f1d535..f8cfd8b 100644
2099--- a/libdrm/nouveau/nouveau_notifier.c
2100+++ b/libdrm/nouveau/nouveau_notifier.c
2101@@ -48,7 +48,7 @@ nouveau_notifier_alloc(struct nouveau_channel *chan, uint32_t handle,
2102
2103 nvnotify->drm.channel = chan->id;
2104 nvnotify->drm.handle = handle;
2105- nvnotify->drm.count = count;
2106+ nvnotify->drm.size = (count * 32);
2107 if ((ret = drmCommandWriteRead(nouveau_device(chan->device)->fd,
2108 DRM_NOUVEAU_NOTIFIEROBJ_ALLOC,
2109 &nvnotify->drm,
2110@@ -57,7 +57,7 @@ nouveau_notifier_alloc(struct nouveau_channel *chan, uint32_t handle,
2111 return ret;
2112 }
2113
2114- nvnotify->map = (char *)nouveau_channel(chan)->notifier_block +
2115+ nvnotify->map = (char *)nouveau_channel(chan)->notifier_bo->map +
2116 nvnotify->drm.offset;
2117 *notifier = &nvnotify->base;
2118 return 0;
2119diff --git a/libdrm/nouveau/nouveau_private.h b/libdrm/nouveau/nouveau_private.h
2120index e92cb1f..49dde5e 100644
2121--- a/libdrm/nouveau/nouveau_private.h
2122+++ b/libdrm/nouveau/nouveau_private.h
2123@@ -36,8 +36,6 @@
2124 #include "nouveau_resource.h"
2125 #include "nouveau_pushbuf.h"
2126
2127-#define NOUVEAU_PUSHBUF_MAX_BUFFERS 1024
2128-#define NOUVEAU_PUSHBUF_MAX_RELOCS 1024
2129 struct nouveau_pushbuf_priv {
2130 struct nouveau_pushbuf base;
2131
2132@@ -51,95 +49,23 @@ struct nouveau_pushbuf_priv {
2133 unsigned nr_buffers;
2134 struct drm_nouveau_gem_pushbuf_reloc *relocs;
2135 unsigned nr_relocs;
2136-
2137- /*XXX: nomm */
2138- struct nouveau_fence *fence;
2139 };
2140 #define nouveau_pushbuf(n) ((struct nouveau_pushbuf_priv *)(n))
2141
2142-#define pbbo_to_ptr(o) ((uint64_t)(unsigned long)(o))
2143-#define ptr_to_pbbo(h) ((struct nouveau_pushbuf_bo *)(unsigned long)(h))
2144-#define pbrel_to_ptr(o) ((uint64_t)(unsigned long)(o))
2145-#define ptr_to_pbrel(h) ((struct nouveau_pushbuf_reloc *)(unsigned long)(h))
2146-#define bo_to_ptr(o) ((uint64_t)(unsigned long)(o))
2147-#define ptr_to_bo(h) ((struct nouveau_bo_priv *)(unsigned long)(h))
2148-
2149 int
2150 nouveau_pushbuf_init(struct nouveau_channel *);
2151
2152-struct nouveau_dma_priv {
2153- uint32_t base;
2154- uint32_t max;
2155- uint32_t cur;
2156- uint32_t put;
2157- uint32_t free;
2158-
2159- int push_free;
2160-} dma;
2161-
2162 struct nouveau_channel_priv {
2163 struct nouveau_channel base;
2164
2165 struct drm_nouveau_channel_alloc drm;
2166
2167- void *notifier_block;
2168+ struct nouveau_bo *notifier_bo;
2169
2170 struct nouveau_pushbuf_priv pb;
2171-
2172- /*XXX: nomm */
2173- volatile uint32_t *user, *put, *get, *ref_cnt;
2174- uint32_t *pushbuf;
2175- struct nouveau_dma_priv struct_dma;
2176- struct nouveau_dma_priv *dma;
2177- struct nouveau_fence *fence_head;
2178- struct nouveau_fence *fence_tail;
2179- uint32_t fence_sequence;
2180- struct nouveau_grobj *fence_grobj;
2181- struct nouveau_notifier *fence_ntfy;
2182 };
2183 #define nouveau_channel(n) ((struct nouveau_channel_priv *)(n))
2184
2185-struct nouveau_fence {
2186- struct nouveau_channel *channel;
2187-};
2188-
2189-struct nouveau_fence_cb {
2190- struct nouveau_fence_cb *next;
2191- void (*func)(void *);
2192- void *priv;
2193-};
2194-
2195-struct nouveau_fence_priv {
2196- struct nouveau_fence base;
2197- int refcount;
2198-
2199- struct nouveau_fence *next;
2200- struct nouveau_fence_cb *signal_cb;
2201-
2202- uint32_t sequence;
2203- int emitted;
2204- int signalled;
2205-};
2206-#define nouveau_fence(n) ((struct nouveau_fence_priv *)(n))
2207-
2208-int
2209-nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **);
2210-
2211-int
2212-nouveau_fence_ref(struct nouveau_fence *, struct nouveau_fence **);
2213-
2214-int
2215-nouveau_fence_signal_cb(struct nouveau_fence *, void (*)(void *), void *);
2216-
2217-void
2218-nouveau_fence_emit(struct nouveau_fence *);
2219-
2220-int
2221-nouveau_fence_wait(struct nouveau_fence **);
2222-
2223-void
2224-nouveau_fence_flush(struct nouveau_channel *);
2225-
2226 struct nouveau_grobj_priv {
2227 struct nouveau_grobj base;
2228 };
2229@@ -181,10 +107,6 @@ struct nouveau_bo_priv {
2230 int pinned;
2231 uint64_t offset;
2232 uint32_t domain;
2233-
2234- /*XXX: nomm stuff */
2235- struct nouveau_fence *fence;
2236- struct nouveau_fence *wr_fence;
2237 };
2238 #define nouveau_bo(n) ((struct nouveau_bo_priv *)(n))
2239
2240@@ -197,8 +119,4 @@ nouveau_bo_takedown(struct nouveau_device *);
2241 struct drm_nouveau_gem_pushbuf_bo *
2242 nouveau_bo_emit_buffer(struct nouveau_channel *, struct nouveau_bo *);
2243
2244-int
2245-nouveau_bo_validate_nomm(struct nouveau_bo_priv *, uint32_t);
2246-
2247-#include "nouveau_dma.h"
2248 #endif
2249diff --git a/libdrm/nouveau/nouveau_pushbuf.c b/libdrm/nouveau/nouveau_pushbuf.c
2250index fded21b..2a242f7 100644
2251--- a/libdrm/nouveau/nouveau_pushbuf.c
2252+++ b/libdrm/nouveau/nouveau_pushbuf.c
2253@@ -26,19 +26,15 @@
2254 #include <assert.h>
2255
2256 #include "nouveau_private.h"
2257-#include "nouveau_dma.h"
2258
2259 #define PB_BUFMGR_DWORDS (4096 / 2)
2260 #define PB_MIN_USER_DWORDS 2048
2261
2262 static uint32_t
2263 nouveau_pushbuf_calc_reloc(struct drm_nouveau_gem_pushbuf_bo *pbbo,
2264- struct drm_nouveau_gem_pushbuf_reloc *r,
2265- int mm_enabled)
2266+ struct drm_nouveau_gem_pushbuf_reloc *r)
2267 {
2268 uint32_t push = 0;
2269- const unsigned is_vram = mm_enabled ? NOUVEAU_GEM_DOMAIN_VRAM :
2270- NOUVEAU_BO_VRAM;
2271
2272 if (r->flags & NOUVEAU_GEM_RELOC_LOW)
2273 push = (pbbo->presumed_offset + r->data);
2274@@ -49,7 +45,7 @@ nouveau_pushbuf_calc_reloc(struct drm_nouveau_gem_pushbuf_bo *pbbo,
2275 push = r->data;
2276
2277 if (r->flags & NOUVEAU_GEM_RELOC_OR) {
2278- if (pbbo->presumed_domain & is_vram)
2279+ if (pbbo->presumed_domain & NOUVEAU_GEM_DOMAIN_VRAM)
2280 push |= r->vor;
2281 else
2282 push |= r->tor;
2283@@ -69,7 +65,7 @@ nouveau_pushbuf_emit_reloc(struct nouveau_channel *chan, void *ptr,
2284 struct drm_nouveau_gem_pushbuf_bo *pbbo;
2285 uint32_t domains = 0;
2286
2287- if (nvpb->nr_relocs >= NOUVEAU_PUSHBUF_MAX_RELOCS)
2288+ if (nvpb->nr_relocs >= NOUVEAU_GEM_MAX_RELOCS)
2289 return -ENOMEM;
2290
2291 if (nouveau_bo(bo)->user && (flags & NOUVEAU_BO_WR)) {
2292@@ -88,14 +84,6 @@ nouveau_pushbuf_emit_reloc(struct nouveau_channel *chan, void *ptr,
2293 pbbo->valid_domains &= domains;
2294 assert(pbbo->valid_domains);
2295
2296- if (!nvdev->mm_enabled) {
2297- struct nouveau_bo_priv *nvbo = nouveau_bo(bo);
2298-
2299- nouveau_fence_ref(nvpb->fence, &nvbo->fence);
2300- if (flags & NOUVEAU_BO_WR)
2301- nouveau_fence_ref(nvpb->fence, &nvbo->wr_fence);
2302- }
2303-
2304 assert(flags & NOUVEAU_BO_RDWR);
2305 if (flags & NOUVEAU_BO_RD) {
2306 pbbo->read_domains |= domains;
2307@@ -120,7 +108,7 @@ nouveau_pushbuf_emit_reloc(struct nouveau_channel *chan, void *ptr,
2308 r->tor = tor;
2309
2310 *(uint32_t *)ptr = (flags & NOUVEAU_BO_DUMMY) ? 0 :
2311- nouveau_pushbuf_calc_reloc(pbbo, r, nvdev->mm_enabled);
2312+ nouveau_pushbuf_calc_reloc(pbbo, r);
2313 return 0;
2314 }
2315
2316@@ -142,11 +130,6 @@ nouveau_pushbuf_space(struct nouveau_channel *chan, unsigned min)
2317 nvpb->base.remaining = nvpb->size;
2318 nvpb->base.cur = nvpb->pushbuf;
2319
2320- if (!nouveau_device(chan->device)->mm_enabled) {
2321- nouveau_fence_ref(NULL, &nvpb->fence);
2322- nouveau_fence_new(chan, &nvpb->fence);
2323- }
2324-
2325 return 0;
2326 }
2327
2328@@ -158,63 +141,15 @@ nouveau_pushbuf_init(struct nouveau_channel *chan)
2329
2330 nouveau_pushbuf_space(chan, 0);
2331
2332- nvpb->buffers = calloc(NOUVEAU_PUSHBUF_MAX_BUFFERS,
2333+ nvpb->buffers = calloc(NOUVEAU_GEM_MAX_BUFFERS,
2334 sizeof(struct drm_nouveau_gem_pushbuf_bo));
2335- nvpb->relocs = calloc(NOUVEAU_PUSHBUF_MAX_RELOCS,
2336+ nvpb->relocs = calloc(NOUVEAU_GEM_MAX_RELOCS,
2337 sizeof(struct drm_nouveau_gem_pushbuf_reloc));
2338
2339 chan->pushbuf = &nvpb->base;
2340 return 0;
2341 }
2342
2343-static int
2344-nouveau_pushbuf_flush_nomm(struct nouveau_channel_priv *nvchan)
2345-{
2346- struct nouveau_pushbuf_priv *nvpb = &nvchan->pb;
2347- struct drm_nouveau_gem_pushbuf_bo *bo = nvpb->buffers;
2348- struct drm_nouveau_gem_pushbuf_reloc *reloc = nvpb->relocs;
2349- unsigned b, r;
2350- int ret;
2351-
2352- for (b = 0; b < nvpb->nr_buffers; b++) {
2353- struct nouveau_bo_priv *nvbo =
2354- (void *)(unsigned long)bo[b].user_priv;
2355- uint32_t flags = 0;
2356-
2357- if (bo[b].valid_domains & NOUVEAU_GEM_DOMAIN_VRAM)
2358- flags |= NOUVEAU_BO_VRAM;
2359- if (bo[b].valid_domains & NOUVEAU_GEM_DOMAIN_GART)
2360- flags |= NOUVEAU_BO_GART;
2361-
2362- ret = nouveau_bo_validate_nomm(nvbo, flags);
2363- if (ret)
2364- return ret;
2365-
2366- if (1 || bo[b].presumed_domain != nvbo->domain ||
2367- bo[b].presumed_offset != nvbo->offset) {
2368- bo[b].presumed_ok = 0;
2369- bo[b].presumed_domain = nvbo->domain;
2370- bo[b].presumed_offset = nvbo->offset;
2371- }
2372- }
2373-
2374- for (r = 0; r < nvpb->nr_relocs; r++, reloc++) {
2375- uint32_t push;
2376-
2377- if (bo[reloc->bo_index].presumed_ok)
2378- continue;
2379-
2380- push = nouveau_pushbuf_calc_reloc(&bo[reloc->bo_index], reloc, 0);
2381- nvpb->pushbuf[reloc->reloc_index] = push;
2382- }
2383-
2384- nouveau_dma_space(&nvchan->base, nvpb->size);
2385- nouveau_dma_outp (&nvchan->base, nvpb->pushbuf, nvpb->size);
2386- nouveau_fence_emit(nvpb->fence);
2387-
2388- return 0;
2389-}
2390-
2391 int
2392 nouveau_pushbuf_flush(struct nouveau_channel *chan, unsigned min)
2393 {
2394@@ -229,20 +164,15 @@ nouveau_pushbuf_flush(struct nouveau_channel *chan, unsigned min)
2395 return 0;
2396 nvpb->size -= nvpb->base.remaining;
2397
2398- if (nvdev->mm_enabled) {
2399- req.channel = chan->id;
2400- req.nr_dwords = nvpb->size;
2401- req.dwords = (uint64_t)(unsigned long)nvpb->pushbuf;
2402- req.nr_buffers = nvpb->nr_buffers;
2403- req.buffers = (uint64_t)(unsigned long)nvpb->buffers;
2404- req.nr_relocs = nvpb->nr_relocs;
2405- req.relocs = (uint64_t)(unsigned long)nvpb->relocs;
2406- ret = drmCommandWrite(nvdev->fd, DRM_NOUVEAU_GEM_PUSHBUF,
2407- &req, sizeof(req));
2408- } else {
2409- nouveau_fence_flush(chan);
2410- ret = nouveau_pushbuf_flush_nomm(nvchan);
2411- }
2412+ req.channel = chan->id;
2413+ req.nr_dwords = nvpb->size;
2414+ req.dwords = (uint64_t)(unsigned long)nvpb->pushbuf;
2415+ req.nr_buffers = nvpb->nr_buffers;
2416+ req.buffers = (uint64_t)(unsigned long)nvpb->buffers;
2417+ req.nr_relocs = nvpb->nr_relocs;
2418+ req.relocs = (uint64_t)(unsigned long)nvpb->relocs;
2419+ ret = drmCommandWrite(nvdev->fd, DRM_NOUVEAU_GEM_PUSHBUF,
2420+ &req, sizeof(req));
2421 assert(ret == 0);
2422
2423
2424diff --git a/shared-core/nouveau_drm.h b/shared-core/nouveau_drm.h
2425index dc6a194..3e52b24 100644
2426--- a/shared-core/nouveau_drm.h
2427+++ b/shared-core/nouveau_drm.h
2428@@ -25,7 +25,7 @@
2429 #ifndef __NOUVEAU_DRM_H__
2430 #define __NOUVEAU_DRM_H__
2431
2432-#define NOUVEAU_DRM_HEADER_PATCHLEVEL 14
2433+#define NOUVEAU_DRM_HEADER_PATCHLEVEL 15
2434
2435 struct drm_nouveau_channel_alloc {
2436 uint32_t fb_ctxdma_handle;
2437@@ -34,8 +34,7 @@ struct drm_nouveau_channel_alloc {
2438 int channel;
2439
2440 /* Notifier memory */
2441- drm_handle_t notifier;
2442- int notifier_size;
2443+ uint32_t notifier_handle;
2444
2445 /* DRM-enforced subchannel assignments */
2446 struct {
2447@@ -43,15 +42,6 @@ struct drm_nouveau_channel_alloc {
2448 uint32_t grclass;
2449 } subchan[8];
2450 uint32_t nr_subchan;
2451-
2452-/* !MM_ENABLED ONLY */
2453- uint32_t put_base;
2454- /* FIFO control regs */
2455- drm_handle_t ctrl;
2456- int ctrl_size;
2457- /* DMA command buffer */
2458- drm_handle_t cmdbuf;
2459- int cmdbuf_size;
2460 };
2461
2462 struct drm_nouveau_channel_free {
2463@@ -64,14 +54,10 @@ struct drm_nouveau_grobj_alloc {
2464 int class;
2465 };
2466
2467-#define NOUVEAU_MEM_ACCESS_RO 1
2468-#define NOUVEAU_MEM_ACCESS_WO 2
2469-#define NOUVEAU_MEM_ACCESS_RW 3
2470 struct drm_nouveau_notifierobj_alloc {
2471- int channel;
2472+ uint32_t channel;
2473 uint32_t handle;
2474- int count;
2475-
2476+ uint32_t size;
2477 uint32_t offset;
2478 };
2479
2480@@ -80,52 +66,6 @@ struct drm_nouveau_gpuobj_free {
2481 uint32_t handle;
2482 };
2483
2484-/* This is needed to avoid a race condition.
2485- * Otherwise you may be writing in the fetch area.
2486- * Is this large enough, as it's only 32 bytes, and the maximum fetch size is 256 bytes?
2487- */
2488-#define NOUVEAU_DMA_SKIPS 8
2489-
2490-#define NOUVEAU_MEM_FB 0x00000001
2491-#define NOUVEAU_MEM_AGP 0x00000002
2492-#define NOUVEAU_MEM_FB_ACCEPTABLE 0x00000004
2493-#define NOUVEAU_MEM_AGP_ACCEPTABLE 0x00000008
2494-#define NOUVEAU_MEM_PCI 0x00000010
2495-#define NOUVEAU_MEM_PCI_ACCEPTABLE 0x00000020
2496-#define NOUVEAU_MEM_PINNED 0x00000040
2497-#define NOUVEAU_MEM_USER_BACKED 0x00000080
2498-#define NOUVEAU_MEM_MAPPED 0x00000100
2499-#define NOUVEAU_MEM_TILE 0x00000200
2500-#define NOUVEAU_MEM_TILE_ZETA 0x00000400
2501-#define NOUVEAU_MEM_INSTANCE 0x01000000 /* internal */
2502-#define NOUVEAU_MEM_NOTIFIER 0x02000000 /* internal */
2503-#define NOUVEAU_MEM_NOVM 0x04000000 /* internal */
2504-#define NOUVEAU_MEM_USER 0x08000000 /* internal */
2505-#define NOUVEAU_MEM_INTERNAL (NOUVEAU_MEM_INSTANCE | \
2506- NOUVEAU_MEM_NOTIFIER | \
2507- NOUVEAU_MEM_NOVM | \
2508- NOUVEAU_MEM_USER)
2509-
2510-struct drm_nouveau_mem_alloc {
2511- int flags;
2512- int alignment;
2513- uint64_t size; // in bytes
2514- uint64_t offset;
2515- drm_handle_t map_handle;
2516-};
2517-
2518-struct drm_nouveau_mem_free {
2519- uint64_t offset;
2520- int flags;
2521-};
2522-
2523-struct drm_nouveau_mem_tile {
2524- uint64_t offset;
2525- uint64_t delta;
2526- uint64_t size;
2527- int flags;
2528-};
2529-
2530 /* FIXME : maybe unify {GET,SET}PARAMs */
2531 #define NOUVEAU_GETPARAM_PCI_VENDOR 3
2532 #define NOUVEAU_GETPARAM_PCI_DEVICE 4
2533@@ -136,15 +76,12 @@ struct drm_nouveau_mem_tile {
2534 #define NOUVEAU_GETPARAM_AGP_SIZE 9
2535 #define NOUVEAU_GETPARAM_PCI_PHYSICAL 10
2536 #define NOUVEAU_GETPARAM_CHIPSET_ID 11
2537-#define NOUVEAU_GETPARAM_MM_ENABLED 12
2538-#define NOUVEAU_GETPARAM_VM_VRAM_BASE 13
2539+#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
2540 struct drm_nouveau_getparam {
2541 uint64_t param;
2542 uint64_t value;
2543 };
2544
2545-#define NOUVEAU_SETPARAM_CMDBUF_LOCATION 1
2546-#define NOUVEAU_SETPARAM_CMDBUF_SIZE 2
2547 struct drm_nouveau_setparam {
2548 uint64_t param;
2549 uint64_t value;
2550@@ -228,8 +165,12 @@ struct drm_nouveau_gem_unpin {
2551 uint32_t handle;
2552 };
2553
2554+#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
2555+#define NOUVEAU_GEM_CPU_PREP_NOBLOCK 0x00000002
2556+#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
2557 struct drm_nouveau_gem_cpu_prep {
2558 uint32_t handle;
2559+ uint32_t flags;
2560 };
2561
2562 struct drm_nouveau_gem_cpu_fini {
2563@@ -238,38 +179,19 @@ struct drm_nouveau_gem_cpu_fini {
2564
2565 struct drm_nouveau_gem_tile {
2566 uint32_t handle;
2567- uint32_t delta;
2568+ uint32_t offset;
2569 uint32_t size;
2570- uint32_t flags;
2571-};
2572-
2573-enum nouveau_card_type {
2574- NV_UNKNOWN =0,
2575- NV_04 =4,
2576- NV_05 =5,
2577- NV_10 =10,
2578- NV_11 =11,
2579- NV_17 =17,
2580- NV_20 =20,
2581- NV_30 =30,
2582- NV_40 =40,
2583- NV_44 =44,
2584- NV_50 =50,
2585- NV_LAST =0xffff,
2586+ uint32_t tile_mode;
2587+ uint32_t tile_flags;
2588 };
2589
2590 enum nouveau_bus_type {
2591- NV_AGP =0,
2592- NV_PCI =1,
2593- NV_PCIE =2,
2594+ NV_AGP = 0,
2595+ NV_PCI = 1,
2596+ NV_PCIE = 2,
2597 };
2598
2599-#define NOUVEAU_MAX_SAREA_CLIPRECTS 16
2600-
2601 struct drm_nouveau_sarea {
2602- /* the cliprects */
2603- struct drm_clip_rect boxes[NOUVEAU_MAX_SAREA_CLIPRECTS];
2604- unsigned int nbox;
2605 };
2606
2607 #define DRM_NOUVEAU_CARD_INIT 0x00
2608@@ -280,19 +202,13 @@ struct drm_nouveau_sarea {
2609 #define DRM_NOUVEAU_GROBJ_ALLOC 0x05
2610 #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x06
2611 #define DRM_NOUVEAU_GPUOBJ_FREE 0x07
2612-#define DRM_NOUVEAU_MEM_ALLOC 0x08
2613-#define DRM_NOUVEAU_MEM_FREE 0x09
2614-#define DRM_NOUVEAU_MEM_TILE 0x0a
2615-#define DRM_NOUVEAU_SUSPEND 0x0b
2616-#define DRM_NOUVEAU_RESUME 0x0c
2617 #define DRM_NOUVEAU_GEM_NEW 0x40
2618 #define DRM_NOUVEAU_GEM_PUSHBUF 0x41
2619 #define DRM_NOUVEAU_GEM_PUSHBUF_CALL 0x42
2620-#define DRM_NOUVEAU_GEM_PIN 0x43
2621-#define DRM_NOUVEAU_GEM_UNPIN 0x44
2622+#define DRM_NOUVEAU_GEM_PIN 0x43 /* !KMS only */
2623+#define DRM_NOUVEAU_GEM_UNPIN 0x44 /* !KMS only */
2624 #define DRM_NOUVEAU_GEM_CPU_PREP 0x45
2625 #define DRM_NOUVEAU_GEM_CPU_FINI 0x46
2626-#define DRM_NOUVEAU_GEM_TILE 0x47
2627-#define DRM_NOUVEAU_GEM_INFO 0x48
2628+#define DRM_NOUVEAU_GEM_INFO 0x47
2629
2630 #endif /* __NOUVEAU_DRM_H__ */
Userspace interface to kernel DRM services
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