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40812fd2 JR |
1 | From c6cd2ee2d59111a07cd9199564c9bdcb2d11e5cf Mon Sep 17 00:00:00 2001 |
2 | From: Jani Nikula <jani.nikula@intel.com> | |
3 | Date: Mon, 21 Oct 2013 07:52:07 +0000 | |
4 | Subject: drm/i915/dp: workaround BIOS eDP bpp clamping issue | |
5 | ||
6 | This isn't a real fix to the problem, but rather a stopgap measure while | |
7 | trying to find a proper solution. | |
8 | ||
9 | There are several laptops out there that fail to light up the eDP panel | |
10 | in UEFI boot mode. They seem to be mostly IVB machines, including but | |
11 | apparently not limited to Dell XPS 13, Asus TX300, Asus UX31A, Asus | |
12 | UX32VD, Acer Aspire S7. They seem to work in CSM or legacy boot. | |
13 | ||
14 | The difference between UEFI and CSM is that the BIOS provides a | |
15 | different VBT to the kernel. The UEFI VBT typically specifies 18 bpp and | |
16 | 1.62 GHz link for eDP, while CSM VBT has 24 bpp and 2.7 GHz link. We end | |
17 | up clamping to 18 bpp in UEFI mode, which we can fit in the 1.62 Ghz | |
18 | link, and for reasons yet unknown fail to light up the panel. | |
19 | ||
20 | Dithering from 24 to 18 bpp itself seems to work; if we use 18 bpp with | |
21 | 2.7 GHz link, the eDP panel lights up. So essentially this is a link | |
22 | speed issue, and *not* a bpp clamping issue. | |
23 | ||
24 | The bug raised its head since | |
25 | commit 657445fe8660100ad174600ebfa61536392b7624 | |
26 | Author: Daniel Vetter <daniel.vetter@ffwll.ch> | |
27 | Date: Sat May 4 10:09:18 2013 +0200 | |
28 | ||
29 | Revert "drm/i915: revert eDP bpp clamping code changes" | |
30 | ||
31 | which started clamping bpp *before* computing the link requirements, and | |
32 | thus affecting the required bandwidth. Clamping after the computations | |
33 | kept the link at 2.7 GHz. | |
34 | ||
35 | Even though the BIOS tells us to use 18 bpp through the VBT, it happily | |
36 | boots up at 24 bpp and 2.7 GHz itself! Use this information to | |
37 | selectively ignore the VBT provided value. | |
38 | ||
39 | We can't ignore the VBT eDP bpp altogether, as there are other laptops | |
40 | that do require the clamping to be used due to EDID reporting higher bpp | |
41 | than the panel can support. | |
42 | ||
43 | Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=59841 | |
44 | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67950 | |
45 | Tested-by: Ulf Winkelvos <ulf@winkelvos.de> | |
46 | Tested-by: jkp <jkp@iki.fi> | |
47 | CC: stable@vger.kernel.org | |
48 | Signed-off-by: Jani Nikula <jani.nikula@intel.com> | |
49 | Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> | |
50 | --- | |
51 | diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c | |
52 | index 2c555f9..1a43137 100644 | |
53 | --- a/drivers/gpu/drm/i915/intel_dp.c | |
54 | +++ b/drivers/gpu/drm/i915/intel_dp.c | |
86931f4c JR |
55 | @@ -755,6 +755,26 @@ static void intel_dp_get_config(struct intel_encoder *encoder, |
56 | adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); | |
57 | pipe_config->pipe_bpp = bpp; | |
58 | pipe_config->pixel_target_clock = target_clock; | |
40812fd2 | 59 | + |
86931f4c JR |
60 | + if (is_edp(intel_dp) && dev_priv->edp.bpp && |
61 | + pipe_config->pipe_bpp > dev_priv->edp.bpp) { | |
40812fd2 JR |
62 | + /* |
63 | + * This is a big fat ugly hack. | |
64 | + * | |
65 | + * Some machines in UEFI boot mode provide us a VBT that has 18 | |
66 | + * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
67 | + * unknown we fail to light up. Yet the same BIOS boots up with | |
68 | + * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
69 | + * max, not what it tells us to use. | |
70 | + * | |
71 | + * Note: This will still be broken if the eDP panel is not lit | |
72 | + * up by the BIOS, and thus we can't get the mode at module | |
73 | + * load. | |
74 | + */ | |
75 | + DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
86931f4c JR |
76 | + pipe_config->pipe_bpp, dev_priv->edp.bpp); |
77 | + dev_priv->edp.bpp = pipe_config->pipe_bpp; | |
40812fd2 | 78 | + } |
40812fd2 | 79 | |
86931f4c JR |
80 | DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", |
81 | intel_dp->link_bw, intel_dp->lane_count, | |
40812fd2 JR |
82 | -- |
83 | cgit v0.9.2 |