- updated to 3.3.6

[packages/crossm68k-gcc.git] / crossm68k-gcc-zext.patch

#
# This patch can be found at http://www.uclinux.org/pub/uClinux/m68k-elf-tools/
#
diff -Naur gcc-2.95.3.org/gcc/config/m68k/m68k.md gcc-2.95.3/gcc/config/m68k/m68k.md
--- gcc-2.95.3.org/gcc/config/m68k/m68k.md	Thu Aug  5 16:22:05 1999
+++ gcc-2.95.3/gcc/config/m68k/m68k.md	Mon Dec 16 10:37:47 2002
@@ -1486,10 +1486,40 @@
 }")
 
 ;; this is the canonical form for (lshiftrt:DI x 32)
-(define_insn "zero_extendsidi2"
+(define_expand "zero_extendsidi2"
+  [(set (match_operand:DI 0 "nonimmediate_operand" "")
+    (zero_extend:DI (match_operand:SI 1 "general_operand" "")))]
+  ""
+  "")
+
+(define_insn "*zero_extendsidi2_cf"
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,m")
+    (zero_extend:DI (match_operand:SI 1 "general_operand" "rm,r")))]
+  "TARGET_5200"
+  "*
+{
+  CC_STATUS_INIT;
+  if (GET_CODE (operands[0]) == REG)
+    operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
+  else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
+    return \"move%.l %1,%0\;clr%.l %0\";
+  else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
+    return \"clr%.l %0\;move%.l %1,%0\";
+  else
+    operands[2] = adj_offsettable_operand (operands[0], 4);
+  if (GET_CODE (operands[1]) != REG || GET_CODE (operands[2]) != REG
+      || REGNO (operands[1]) != REGNO (operands[2]))
+    output_asm_insn (\"move%.l %1,%2\", operands);
+  if (ADDRESS_REG_P (operands[0]))
+    return \"sub%.l %0,%0\";
+  else
+    return \"clr%.l %0\";
+}")
+
+(define_insn "*zero_extendsidi2"
   [(set (match_operand:DI 0 "general_operand" "rm")
     (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
-  ""
+  "!TARGET_5200"
   "*
 {
   CC_STATUS_INIT;