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e18230dc 1--- XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/nv.orig/nv.man Tue Dec 18 05:52:33 2001
2+++ XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/nv/nv.man Sun Apr 14 15:59:41 2002
3@@ -39,12 +39,13 @@
4 NV10
5 .TP 22
6 .B GeForce2, QUADRO2
7-NV11 & NV15 (except GeForce2 Go, which is
8-.B NOT
9-supported)
10+NV11 & NV15
11 .TP 22
12 .B GeForce3
13 NV20
14+.TP 22
15+.B GeForce4, QUADRO4
16+NV17 & NV25
17 .SH CONFIGURATION DETAILS
18 Please refer to XF86Config(__filemansuffix__) for general configuration
19 details. This section only covers configuration details specific to this
20@@ -66,6 +67,19 @@
21 .BI "Option \*qUseFBDev\*q \*q" boolean \*q
22 Enable or disable use of on OS-specific fb interface (and is not supported
23 on all OSs). See fbdevhw(__drivermansuffix__) for further information.
24+Default: off.
25+.TP
26+.BI "Option \*qCrtcNumber\*q \*q" integer \*q
27+NV17 and NV25 can have two video outputs. The driver attempts to autodetect
28+which one the monitor is connected to. In the case that autodetection picks
29+the wrong one, this option may be used to force usage of a particular output.
30+The options are "0" or "1".
31+Default: autodetected.
32+.TP
33+.BI "Option \*qFlatPanel\*q \*q" boolean \*q
34+This driver has experimental flat panel support for some chips. The driver
35+cannot autodetect the presence of a flat panel so this option must be set
36+when used with a flat panel.
37 Default: off.
38 .TP
39 .BI "Option \*qRotate\*q \*qCW\*q"
40--- XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/nv.orig/nv_cursor.c Tue Dec 18 07:17:55 2001
41+++ XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/nv/nv_cursor.c Sun Apr 14 15:59:41 2002
42@@ -109,7 +109,7 @@
43 NVPtr pNv = NVPTR(pScrn);
44
45 pNv->riva.ShowHideCursor(&pNv->riva, 0);
46- *(pNv->riva.CURSORPOS) = (x & 0xFFFF) | (y << 16);
47+ pNv->riva.PRAMDAC[0x0000300/4] = (x & 0xFFFF) | (y << 16);
48 pNv->riva.ShowHideCursor(&pNv->riva, 1);
49 }
50
51@@ -123,8 +123,10 @@
52 back = ConvertToRGB555(bg);
53
54 #if X_BYTE_ORDER == X_BIG_ENDIAN
55- fore = (fore << 8) | (fore >> 8);
56- back = (back << 8) | (back >> 8);
57+ if((pNv->Chipset & 0x0ff0) == 0x0110) {
58+ fore = (fore << 8) | (fore >> 8);
59+ back = (back << 8) | (back >> 8);
60+ }
61 #endif
62
63 if (pNv->curFg != fore || pNv->curBg != back) {
64--- XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/nv.orig/nv_dac.c Wed Dec 12 04:42:01 2001
65+++ XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/nv/nv_dac.c Sun Apr 14 15:59:41 2002
66@@ -71,6 +71,15 @@
67 if(mode->Flags & V_INTERLACE)
68 vertTotal |= 1;
69
70+ if(pNv->FlatPanel == 1) {
71+ vertStart = vertTotal - 3;
72+ vertEnd = vertTotal - 2;
73+ vertBlankStart = vertStart;
74+ horizStart = horizTotal - 3;
75+ horizEnd = horizTotal - 2;
76+ horizBlankEnd = horizTotal + 4;
77+ }
78+
79 pVga->CRTC[0x0] = Set8Bits(horizTotal);
80 pVga->CRTC[0x1] = Set8Bits(horizDisplay);
81 pVga->CRTC[0x2] = Set8Bits(horizBlankStart);
82@@ -147,6 +156,8 @@
83 if(pNv->riva.Architecture >= NV_ARCH_10)
84 pNv->riva.CURSOR = (U032 *)(pNv->FbStart + pNv->riva.CursorStart);
85
86+ pNv->riva.LockUnlock(&pNv->riva, 0);
87+
88 pNv->riva.CalcStateExt(&pNv->riva,
89 nvReg,
90 i,
91@@ -156,21 +167,45 @@
92 mode->Clock,
93 mode->Flags);
94
95+ nvReg->scale = pNv->riva.PRAMDAC[0x00000848/4] & 0xfff000ff;
96+ if(pNv->FlatPanel == 1) {
97+ nvReg->pixel |= (1 << 7);
98+ nvReg->scale |= (1 << 8) ;
99+ }
100+ if(pNv->SecondCRTC) {
101+ nvReg->head = pNv->riva.PCRTC0[0x00000860/4] & ~0x00001000;
102+ nvReg->head2 = pNv->riva.PCRTC0[0x00002860/4] | 0x00001000;
103+ nvReg->crtcOwner = 3;
104+ nvReg->pllsel |= 0x20000800;
105+ nvReg->vpll2 = nvReg->vpll;
106+ } else
107+ if(pNv->riva.twoHeads) {
108+ nvReg->head = pNv->riva.PCRTC0[0x00000860/4] | 0x00001000;
109+ nvReg->head2 = pNv->riva.PCRTC0[0x00002860/4] & ~0x00001000;
110+ nvReg->crtcOwner = 0;
111+ nvReg->vpll2 = pNv->riva.PRAMDAC0[0x00000520/4];
112+ }
113+
114 return (TRUE);
115 }
116
117 void
118 NVDACRestore(ScrnInfoPtr pScrn, vgaRegPtr vgaReg, NVRegPtr nvReg,
119- Bool restoreFonts)
120+ Bool primary)
121 {
122 NVPtr pNv = NVPTR(pScrn);
123+ int restore = VGA_SR_MODE;
124+
125 DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NVDACRestore\n"));
126+
127+ if(primary) restore |= VGA_SR_CMAP | VGA_SR_FONTS;
128+ else if(pNv->Chipset == NV_CHIP_RIVA_128)
129+ restore |= VGA_SR_CMAP;
130 pNv->riva.LoadStateExt(&pNv->riva, nvReg);
131 #if defined(__powerpc__)
132- restoreFonts = FALSE;
133+ restore &= ~VGA_SR_FONTS;
134 #endif
135- vgaHWRestore(pScrn, vgaReg, VGA_SR_CMAP | VGA_SR_MODE |
136- (restoreFonts? VGA_SR_FONTS : 0));
137+ vgaHWRestore(pScrn, vgaReg, restore);
138 }
139
140 /*
141@@ -184,8 +219,17 @@
142 {
143 NVPtr pNv = NVPTR(pScrn);
144 DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NVDACSave\n"));
145- vgaHWSave(pScrn, vgaReg, VGA_SR_MODE | (saveFonts? VGA_SR_FONTS : 0));
146+
147+#if defined(__powerpc__)
148+ saveFonts = FALSE;
149+#endif
150+
151+ vgaHWSave(pScrn, vgaReg, VGA_SR_CMAP | VGA_SR_MODE |
152+ (saveFonts? VGA_SR_FONTS : 0));
153 pNv->riva.UnloadStateExt(&pNv->riva, nvReg);
154+
155+ if((pNv->Chipset & 0x0ff0) == 0x0110)
156+ nvReg->crtcOwner = ((pNv->Chipset & 0x0fff) == 0x0112) ? 3 : 0;
157 }
158
159 #define DEPTH_SHIFT(val, w) ((val << (8 - w)) | (val >> ((w << 1) - 8)))
160--- XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/nv.orig/nv_dga.c Tue Jan 23 06:32:36 2001
161+++ XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/nv/nv_dga.c Sun Apr 14 15:59:41 2002
162@@ -234,8 +234,8 @@
163
164 NVAdjustFrame(pScrn->pScreen->myNum, x, y, flags);
165
166- while(pNv->riva.PCIO[0x3da] & 0x08);
167- while(!(pNv->riva.PCIO[0x3da] & 0x08));
168+ while(VGA_RD08(pNv->riva.PCIO, 0x3da) & 0x08);
169+ while(!(VGA_RD08(pNv->riva.PCIO, 0x3da) & 0x08));
170
171 pNv->DGAViewportStatus = 0;
172 }
173--- XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/nv.orig/nv_driver.c Sat Jan 5 06:22:33 2002
174+++ XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/nv/nv_driver.c Sun Apr 14 15:59:41 2002
175@@ -87,81 +87,91 @@
176
177 /* Supported chipsets */
178 static SymTabRec NVChipsets[] = {
179- { NV_CHIP_RIVA128, "RIVA128" },
180- { NV_CHIP_TNT, "RIVA TNT" },
181- { NV_CHIP_TNT2, "RIVA TNT2" },
182- { NV_CHIP_UTNT2, "RIVA TNT2 Ultra" },
183- { NV_CHIP_VTNT2, "Vanta" },
184- { NV_CHIP_UVTNT2, "RIVA TNT2 M64" },
185- { NV_CHIP_ITNT2, "Aladdin TNT2" },
186- { NV_CHIP_GEFORCE256, "GeForce 256" },
187- { NV_CHIP_GEFORCEDDR, "GeForce DDR" },
188- { NV_CHIP_QUADRO, "Quadro" },
189- { NV_CHIP_GEFORCE2GTS, "GeForce2 GTS/Pro"},
190- { NV_CHIP_GEFORCE2GTS_1,"GeForce2 Ti"},
191- { NV_CHIP_GEFORCE2ULTRA,"GeForce2 Ultra"},
192- { NV_CHIP_QUADRO2PRO, "Quadro2 Pro"},
193- { NV_CHIP_GEFORCE2MX, "GeForce2 MX/MX 400"},
194- { NV_CHIP_GEFORCE2MXDDR, "GeForce2 MX 100/200"},
195- { NV_CHIP_0x0170, "0x0170" },
196- { NV_CHIP_0x0171, "0x0171" },
197- { NV_CHIP_0x0172, "0x0172" },
198- { NV_CHIP_0x0173, "0x0173" },
199- { NV_CHIP_0x0174, "0x0174" },
200- { NV_CHIP_0x0175, "0x0175" },
201- { NV_CHIP_0x0178, "0x0178" },
202- { NV_CHIP_0x017A, "0x017A" },
203- { NV_CHIP_0x017B, "0x017B" },
204- { NV_CHIP_0x017C, "0x017C" },
205- { NV_CHIP_IGEFORCE2, "GeForce2 Integrated"},
206- { NV_CHIP_QUADRO2MXR, "Quadro2 MXR"},
207- { NV_CHIP_GEFORCE2GO, "GeForce2 Go"},
208- { NV_CHIP_GEFORCE3, "GeForce3"},
209- { NV_CHIP_GEFORCE3_1, "GeForce3 Ti 200"},
210- { NV_CHIP_GEFORCE3_2, "GeForce3 Ti 500"},
211- { NV_CHIP_QUADRO_DDC, "Quadro DDC"},
212- { NV_CHIP_0x0250, "0x0250"},
213- { NV_CHIP_0x0258, "0x0258"},
214+ {NV_CHIP_RIVA_128, "RIVA 128"},
215+ {NV_CHIP_TNT, "RIVA TNT"},
216+ {NV_CHIP_TNT2, "RIVA TNT2/TNT2 Pro"},
217+ {NV_CHIP_UTNT2, "RIVA TNT2 Ultra"},
218+ {NV_CHIP_VTNT2, "Vanta"},
219+ {NV_CHIP_UVTNT2, "Riva TNT2 M64"},
220+ {NV_CHIP_ITNT2, "Aladdin TNT2"},
221+ {NV_CHIP_GEFORCE_256, "GeForce 256"},
222+ {NV_CHIP_GEFORCE_DDR, "GeForce DDR"},
223+ {NV_CHIP_QUADRO, "Quadro"},
224+ {NV_CHIP_GEFORCE2_MX, "GeForce2 MX/MX 400"},
225+ {NV_CHIP_GEFORCE2_MX_100, "GeForce2 MX 100/200"},
226+ {NV_CHIP_GEFORCE2_GO, "GeForce2 Go"},
227+ {NV_CHIP_QUADRO2_MXR, "Quadro2 MXR"},
228+ {NV_CHIP_GEFORCE2_GTS, "GeForce2 GTS/Pro"},
229+ {NV_CHIP_GEFORCE2_TI, "GeForce2 Ti"},
230+ {NV_CHIP_GEFORCE2_ULTRA, "GeForce2 Ultra"},
231+ {NV_CHIP_QUADRO2_PRO, "Quadro2 Pro"},
232+ {NV_CHIP_GEFORCE4_MX_460, "GeForce4 MX 460"},
233+ {NV_CHIP_GEFORCE4_MX_440, "GeForce4 MX 440"},
234+ {NV_CHIP_GEFORCE4_MX_420, "GeForce4 MX 420"},
235+ {NV_CHIP_GEFORCE4_440_GO, "GeForce4 440 Go"},
236+ {NV_CHIP_GEFORCE4_420_GO, "GeForce4 420 Go"},
237+ {NV_CHIP_GEFORCE4_420_GO_M32,"GeForce4 420 Go M32"},
238+ {NV_CHIP_QUADRO4_500XGL, "Quadro4 500XGL"},
239+ {NV_CHIP_GEFORCE4_440_GO_M64,"GeForce4 440 Go M64"},
240+ {NV_CHIP_QUADRO4_200, "Quadro4 200/400NVS"},
241+ {NV_CHIP_QUADRO4_550XGL, "Quadro4 550XGL"},
242+ {NV_CHIP_QUADRO4_500_GOGL, "Quadro4 GoGL"},
243+ {NV_CHIP_IGEFORCE2, "GeForce2 Integrated"},
244+ {NV_CHIP_GEFORCE3, "GeForce3"},
245+ {NV_CHIP_GEFORCE3_TI_200, "GeForce3 Ti 200"},
246+ {NV_CHIP_GEFORCE3_TI_500, "GeForce3 Ti 500"},
247+ {NV_CHIP_QUADRO_DCC, "Quadro DCC"},
248+ {NV_CHIP_GEFORCE4_TI_4600, "GeForce4 Ti 4600"},
249+ {NV_CHIP_GEFORCE4_TI_4400, "GeForce4 Ti 4400"},
250+ {NV_CHIP_GEFORCE4_TI_4200, "GeForce4 Ti 4200"},
251+ {NV_CHIP_QUADRO4_900XGL, "Quadro4 900 XGL"},
252+ {NV_CHIP_QUADRO4_750XGL, "Quadro4 750 XGL"},
253+ {NV_CHIP_QUADRO4_700XGL, "Quadro4 700 XGL"},
254 {-1, NULL }
255 };
256
257 static PciChipsets NVPciChipsets[] = {
258- { NV_CHIP_RIVA128, NV_CHIP_RIVA128, RES_SHARED_VGA },
259- { NV_CHIP_TNT, NV_CHIP_TNT, RES_SHARED_VGA },
260- { NV_CHIP_TNT2, NV_CHIP_TNT2, RES_SHARED_VGA },
261- { NV_CHIP_UTNT2, NV_CHIP_UTNT2, RES_SHARED_VGA },
262- { NV_CHIP_VTNT2, NV_CHIP_VTNT2, RES_SHARED_VGA },
263- { NV_CHIP_UVTNT2, NV_CHIP_UVTNT2, RES_SHARED_VGA },
264- { NV_CHIP_ITNT2, NV_CHIP_ITNT2, RES_SHARED_VGA },
265- { NV_CHIP_GEFORCE256, NV_CHIP_GEFORCE256, RES_SHARED_VGA },
266- { NV_CHIP_GEFORCEDDR, NV_CHIP_GEFORCEDDR, RES_SHARED_VGA },
267- { NV_CHIP_QUADRO, NV_CHIP_QUADRO, RES_SHARED_VGA },
268- { NV_CHIP_GEFORCE2GTS, NV_CHIP_GEFORCE2GTS, RES_SHARED_VGA },
269- { NV_CHIP_GEFORCE2GTS_1, NV_CHIP_GEFORCE2GTS_1, RES_SHARED_VGA },
270- { NV_CHIP_GEFORCE2ULTRA, NV_CHIP_GEFORCE2ULTRA, RES_SHARED_VGA },
271- { NV_CHIP_QUADRO2PRO, NV_CHIP_QUADRO2PRO, RES_SHARED_VGA },
272- { NV_CHIP_GEFORCE2MX, NV_CHIP_GEFORCE2MX, RES_SHARED_VGA },
273- { NV_CHIP_GEFORCE2MXDDR, NV_CHIP_GEFORCE2MXDDR, RES_SHARED_VGA },
274- { NV_CHIP_0x0170, NV_CHIP_0x0170, RES_SHARED_VGA },
275- { NV_CHIP_0x0171, NV_CHIP_0x0171, RES_SHARED_VGA },
276- { NV_CHIP_0x0172, NV_CHIP_0x0172, RES_SHARED_VGA },
277- { NV_CHIP_0x0173, NV_CHIP_0x0173, RES_SHARED_VGA },
278- { NV_CHIP_0x0174, NV_CHIP_0x0174, RES_SHARED_VGA },
279- { NV_CHIP_0x0175, NV_CHIP_0x0175, RES_SHARED_VGA },
280- { NV_CHIP_0x0178, NV_CHIP_0x0178, RES_SHARED_VGA },
281- { NV_CHIP_0x017A, NV_CHIP_0x017A, RES_SHARED_VGA },
282- { NV_CHIP_0x017B, NV_CHIP_0x017B, RES_SHARED_VGA },
283- { NV_CHIP_0x017C, NV_CHIP_0x017C, RES_SHARED_VGA },
284- { NV_CHIP_IGEFORCE2, NV_CHIP_IGEFORCE2, RES_SHARED_VGA },
285- { NV_CHIP_QUADRO2MXR, NV_CHIP_QUADRO2MXR, RES_SHARED_VGA },
286- { NV_CHIP_GEFORCE2GO, NV_CHIP_GEFORCE2GO, RES_SHARED_VGA },
287- { NV_CHIP_GEFORCE3, NV_CHIP_GEFORCE3, RES_SHARED_VGA },
288- { NV_CHIP_GEFORCE3_1, NV_CHIP_GEFORCE3_1, RES_SHARED_VGA },
289- { NV_CHIP_GEFORCE3_2, NV_CHIP_GEFORCE3_2, RES_SHARED_VGA },
290- { NV_CHIP_QUADRO_DDC, NV_CHIP_QUADRO_DDC, RES_SHARED_VGA },
291- { NV_CHIP_0x0250, NV_CHIP_0x0250, RES_SHARED_VGA },
292- { NV_CHIP_0x0258, NV_CHIP_0x0258, RES_SHARED_VGA },
293- { -1, -1, RES_UNDEFINED }
294+ {NV_CHIP_RIVA_128, NV_CHIP_RIVA_128, RES_SHARED_VGA},
295+ {NV_CHIP_TNT, NV_CHIP_TNT, RES_SHARED_VGA},
296+ {NV_CHIP_TNT2, NV_CHIP_TNT2, RES_SHARED_VGA},
297+ {NV_CHIP_UTNT2, NV_CHIP_UTNT2, RES_SHARED_VGA},
298+ {NV_CHIP_VTNT2, NV_CHIP_VTNT2, RES_SHARED_VGA},
299+ {NV_CHIP_UVTNT2, NV_CHIP_UVTNT2, RES_SHARED_VGA},
300+ {NV_CHIP_ITNT2, NV_CHIP_ITNT2, RES_SHARED_VGA},
301+ {NV_CHIP_GEFORCE_256, NV_CHIP_GEFORCE_256, RES_SHARED_VGA},
302+ {NV_CHIP_GEFORCE_DDR, NV_CHIP_GEFORCE_DDR, RES_SHARED_VGA},
303+ {NV_CHIP_QUADRO, NV_CHIP_QUADRO, RES_SHARED_VGA},
304+ {NV_CHIP_GEFORCE2_MX, NV_CHIP_GEFORCE2_MX, RES_SHARED_VGA},
305+ {NV_CHIP_GEFORCE2_MX_100, NV_CHIP_GEFORCE2_MX_100, RES_SHARED_VGA},
306+ {NV_CHIP_GEFORCE2_GO, NV_CHIP_GEFORCE2_GO, RES_SHARED_VGA},
307+ {NV_CHIP_QUADRO2_MXR, NV_CHIP_QUADRO2_MXR, RES_SHARED_VGA},
308+ {NV_CHIP_GEFORCE2_GTS, NV_CHIP_GEFORCE2_GTS, RES_SHARED_VGA},
309+ {NV_CHIP_GEFORCE2_TI, NV_CHIP_GEFORCE2_TI, RES_SHARED_VGA},
310+ {NV_CHIP_GEFORCE2_ULTRA, NV_CHIP_GEFORCE2_ULTRA, RES_SHARED_VGA},
311+ {NV_CHIP_QUADRO2_PRO, NV_CHIP_QUADRO2_PRO, RES_SHARED_VGA},
312+ {NV_CHIP_GEFORCE4_MX_460, NV_CHIP_GEFORCE4_MX_460, RES_SHARED_VGA},
313+ {NV_CHIP_GEFORCE4_MX_440, NV_CHIP_GEFORCE4_MX_440, RES_SHARED_VGA},
314+ {NV_CHIP_GEFORCE4_MX_420, NV_CHIP_GEFORCE4_MX_420, RES_SHARED_VGA},
315+ {NV_CHIP_GEFORCE4_440_GO, NV_CHIP_GEFORCE4_440_GO, RES_SHARED_VGA},
316+ {NV_CHIP_GEFORCE4_420_GO, NV_CHIP_GEFORCE4_420_GO, RES_SHARED_VGA},
317+ {NV_CHIP_GEFORCE4_420_GO_M32,NV_CHIP_GEFORCE4_420_GO_M32,RES_SHARED_VGA},
318+ {NV_CHIP_QUADRO4_500XGL, NV_CHIP_QUADRO4_500XGL, RES_SHARED_VGA},
319+ {NV_CHIP_GEFORCE4_440_GO_M64,NV_CHIP_GEFORCE4_440_GO_M64,RES_SHARED_VGA},
320+ {NV_CHIP_QUADRO4_200, NV_CHIP_QUADRO4_200, RES_SHARED_VGA},
321+ {NV_CHIP_QUADRO4_550XGL, NV_CHIP_QUADRO4_550XGL, RES_SHARED_VGA},
322+ {NV_CHIP_QUADRO4_500_GOGL, NV_CHIP_QUADRO4_500_GOGL, RES_SHARED_VGA},
323+ {NV_CHIP_IGEFORCE2, NV_CHIP_IGEFORCE2, RES_SHARED_VGA},
324+ {NV_CHIP_GEFORCE3, NV_CHIP_GEFORCE3, RES_SHARED_VGA},
325+ {NV_CHIP_GEFORCE3_TI_200, NV_CHIP_GEFORCE3_TI_200, RES_SHARED_VGA},
326+ {NV_CHIP_GEFORCE3_TI_500, NV_CHIP_GEFORCE3_TI_500, RES_SHARED_VGA},
327+ {NV_CHIP_QUADRO_DCC, NV_CHIP_QUADRO_DCC, RES_SHARED_VGA},
328+ {NV_CHIP_GEFORCE4_TI_4600, NV_CHIP_GEFORCE4_TI_4600, RES_SHARED_VGA},
329+ {NV_CHIP_GEFORCE4_TI_4400, NV_CHIP_GEFORCE4_TI_4400, RES_SHARED_VGA},
330+ {NV_CHIP_GEFORCE4_TI_4200, NV_CHIP_GEFORCE4_TI_4200, RES_SHARED_VGA},
331+ {NV_CHIP_QUADRO4_900XGL, NV_CHIP_QUADRO4_900XGL, RES_SHARED_VGA},
332+ {NV_CHIP_QUADRO4_750XGL, NV_CHIP_QUADRO4_750XGL, RES_SHARED_VGA},
333+ {NV_CHIP_QUADRO4_700XGL, NV_CHIP_QUADRO4_700XGL, RES_SHARED_VGA},
334+ { -1, -1, RES_UNDEFINED }
335 };
336
337 /*
338@@ -179,13 +189,11 @@
339 "vgaHWGetHWRec",
340 "vgaHWGetIndex",
341 "vgaHWInit",
342- "vgaHWLock",
343 "vgaHWMapMem",
344 "vgaHWProtect",
345 "vgaHWRestore",
346 "vgaHWSave",
347 "vgaHWSaveScreen",
348- "vgaHWUnlock",
349 "vgaHWddc1SetSpeed",
350 NULL
351 };
352@@ -305,7 +313,8 @@
353 OPTION_FBDEV,
354 OPTION_ROTATE,
355 OPTION_VIDEO_KEY,
356- OPTION_FLAT_PANEL
357+ OPTION_FLAT_PANEL,
358+ OPTION_CRTC_NUMBER
359 } NVOpts;
360
361
362@@ -319,6 +328,7 @@
363 { OPTION_ROTATE, "Rotate", OPTV_ANYSTR, {0}, FALSE },
364 { OPTION_VIDEO_KEY, "VideoKey", OPTV_INTEGER, {0}, FALSE },
365 { OPTION_FLAT_PANEL, "FlatPanel", OPTV_BOOLEAN, {0}, FALSE },
366+ { OPTION_CRTC_NUMBER, "CrtcNumber", OPTV_INTEGER, {0}, FALSE },
367 { -1, NULL, OPTV_NONE, {0}, FALSE }
368 };
369
370@@ -333,7 +343,7 @@
371 */
372 static NVRamdacRec DacInit = {
373 FALSE, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL,
374- 0, NULL, NULL, NULL, NULL, NULL
375+ 0, NULL, NULL, NULL, NULL
376 };
377
378
379@@ -565,13 +575,9 @@
380 NVEnterVT(int scrnIndex, int flags)
381 {
382 ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
383- NVPtr pNv = NVPTR(pScrn);
384- vgaHWPtr hwp = VGAHWPTR(pScrn);
385
386 DEBUG(xf86DrvMsg(scrnIndex, X_INFO, "NVEnterVT\n"));
387
388- vgaHWUnlock(hwp);
389- pNv->riva.LockUnlock(&pNv->riva, 0);
390 if (!NVModeInit(pScrn, pScrn->currentMode))
391 return FALSE;
392 NVAdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0);
393@@ -600,13 +606,11 @@
394 {
395 ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
396 NVPtr pNv = NVPTR(pScrn);
397- vgaHWPtr hwp = VGAHWPTR(pScrn);
398
399 DEBUG(xf86DrvMsg(scrnIndex, X_INFO, "NVLeaveVT\n"));
400
401 NVRestore(pScrn);
402 pNv->riva.LockUnlock(&pNv->riva, 1);
403- vgaHWLock(hwp);
404 }
405
406
407@@ -645,7 +649,6 @@
408 NVCloseScreen(int scrnIndex, ScreenPtr pScreen)
409 {
410 ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
411- vgaHWPtr hwp = VGAHWPTR(pScrn);
412 NVPtr pNv = NVPTR(pScrn);
413
414 DEBUG(xf86DrvMsg(scrnIndex, X_INFO, "NVCloseScreen\n"));
415@@ -653,7 +656,6 @@
416 if (pScrn->vtSema) {
417 NVRestore(pScrn);
418 pNv->riva.LockUnlock(&pNv->riva, 1);
419- vgaHWLock(hwp);
420 }
421
422 NVUnmapMem(pScrn);
423@@ -779,15 +781,13 @@
424
425
426 /* Internally used */
427-static xf86MonPtr
428+xf86MonPtr
429 NVdoDDC(ScrnInfoPtr pScrn)
430 {
431- vgaHWPtr hwp;
432 NVPtr pNv;
433 NVRamdacPtr NVdac;
434 xf86MonPtr MonInfo = NULL;
435
436- hwp = VGAHWPTR(pScrn);
437 pNv = NVPTR(pScrn);
438 NVdac = &pNv->Dac;
439
440@@ -800,7 +800,6 @@
441 /* if ((MonInfo = nvDoDDCVBE(pScrn))) return MonInfo; */
442
443 /* Enable access to extended registers */
444- vgaHWUnlock(hwp);
445 pNv->riva.LockUnlock(&pNv->riva, 0);
446 /* Save the current state */
447 NVSave(pScrn);
448@@ -814,7 +813,6 @@
449 /* Restore previous state */
450 NVRestore(pScrn);
451 pNv->riva.LockUnlock(&pNv->riva, 1);
452- vgaHWLock(hwp);
453
454 return MonInfo;
455 }
456@@ -972,7 +970,7 @@
457 /* OK */
458 break;
459 case 16:
460- if(pNv->Chipset == NV_CHIP_RIVA128) {
461+ if(pNv->Chipset == NV_CHIP_RIVA_128) {
462 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
463 "The Riva 128 chipset does not support depth 16. "
464 "Using depth 15 instead\n");
465@@ -1141,10 +1139,23 @@
466 (((pScrn->mask.blue >> pScrn->offset.blue) - 1) << pScrn->offset.blue);
467 }
468
469- if (xf86ReturnOptValBool(pNv->Options, OPTION_FLAT_PANEL, FALSE)) {
470- pNv->FlatPanel = TRUE;
471- xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "using flat panel\n");
472+ if (xf86GetOptValBool(pNv->Options, OPTION_FLAT_PANEL, &(pNv->FlatPanel))) {
473+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "forcing %s usage\n",
474+ pNv->FlatPanel ? "DFP" : "CRTC");
475+ } else {
476+ pNv->FlatPanel = -1; /* autodetect later */
477 }
478+
479+ if (xf86GetOptValInteger(pNv->Options, OPTION_CRTC_NUMBER,
480+ &pNv->forceCRTC))
481+ {
482+ if((pNv->forceCRTC < 0) || (pNv->forceCRTC > 1)) {
483+ pNv->forceCRTC = -1;
484+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
485+ "Invalid CRTC number. Must be 0 or 1\n");
486+ }
487+ } else pNv->forceCRTC = -1;
488+
489
490 if (pNv->pEnt->device->MemBase != 0) {
491 /* Require that the config file value matches one of the PCI values. */
492@@ -1233,12 +1244,6 @@
493 }
494
495 /*
496- * fill riva structure etc.
497- */
498- (*pNv->PreInit)(pScrn);
499-
500-
501- /*
502 * If the user has specified the amount of memory in the XF86Config
503 * file, we respect that setting.
504 */
505@@ -1258,42 +1263,6 @@
506
507 pNv->FbMapSize = pScrn->videoRam * 1024;
508
509-#if !defined(__powerpc__)
510- /* Read and print the Monitor DDC info */
511- pScrn->monitor->DDC = NVdoDDC(pScrn);
512-#endif
513-
514-#if 0
515- /*
516- * This code was for testing. It will be removed as soon
517- * as this is integrated into the common level.
518- */
519- if ((!pScrn->monitor->nHsync || !pScrn->monitor->nVrefresh)
520- && pScrn->monitor->DDC) {
521- int i;
522- int h = (!pScrn->monitor->nHsync) ? 0 : -1;
523- int v = (!pScrn->monitor->nVrefresh) ? 0 : -1;
524- xf86MonPtr pMon = (xf86MonPtr)pScrn->monitor->DDC;
525- for (i = 0; i < DET_TIMINGS; i++) {
526- if (pMon->det_mon[i].type == DS_RANGES) {
527- if (h != -1) {
528- pScrn->monitor->hsync[h].lo
529- = pMon->det_mon[i].section.ranges.min_h;
530- pScrn->monitor->hsync[h++].hi
531- = pMon->det_mon[i].section.ranges.max_h;
532- }
533- if (v != -1) {
534- pScrn->monitor->vrefresh[v].lo
535- = pMon->det_mon[i].section.ranges.min_v;
536- pScrn->monitor->vrefresh[v++].hi
537- = pMon->det_mon[i].section.ranges.max_v;
538- }
539- }
540- }
541- if (h != -1) pScrn->monitor->nHsync = h;
542- if (v != -1) pScrn->monitor->nVrefresh = v;
543- }
544-#endif
545 /*
546 * If the driver can do gamma correction, it should call xf86SetGamma()
547 * here.
548@@ -1318,6 +1287,7 @@
549 case NV_ARCH_04:
550 case NV_ARCH_10:
551 case NV_ARCH_20:
552+ default:
553 pNv->FbUsableSize -= 128 * 1024;
554 break;
555 }
556@@ -1344,6 +1314,11 @@
557 clockRanges->interlaceAllowed = FALSE;
558 clockRanges->doubleScanAllowed = TRUE;
559
560+ if(pNv->FlatPanel == 1) {
561+ clockRanges->interlaceAllowed = FALSE;
562+ clockRanges->doubleScanAllowed = FALSE;
563+ }
564+
565 /*
566 * xf86ValidateModes will check that the mode HTotal and VTotal values
567 * don't exceed the chipset's limit if pScrn->maxHValue and
568@@ -1538,9 +1513,7 @@
569
570
571 /*
572- * Initialise a new mode. This is currently still using the old
573- * "initialise struct, restore/write struct to HW" model. That could
574- * be changed.
575+ * Initialise a new mode.
576 */
577
578 static Bool
579@@ -1558,18 +1531,15 @@
580 return FALSE;
581 pScrn->vtSema = TRUE;
582
583- if ( pNv->ModeInit ) {
584- if (!(*pNv->ModeInit)(pScrn, mode))
585- return FALSE;
586- }
587+ if(!(*pNv->ModeInit)(pScrn, mode))
588+ return FALSE;
589
590 /* Program the registers */
591 vgaHWProtect(pScrn, TRUE);
592 vgaReg = &hwp->ModeReg;
593 nvReg = &pNv->ModeReg;
594
595- if ( pNv->Restore )
596- (*pNv->Restore)(pScrn, vgaReg, nvReg, FALSE);
597+ (*pNv->Restore)(pScrn, vgaReg, nvReg, FALSE);
598
599 #if X_BYTE_ORDER == X_BIG_ENDIAN
600 /* turn on LFB swapping */
601@@ -1606,10 +1576,7 @@
602 DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NVRestore\n"));
603 /* Only restore text mode fonts/text for the primary card */
604 vgaHWProtect(pScrn, TRUE);
605- if (pNv->Primary)
606- (*pNv->Restore)(pScrn, vgaReg, nvReg, TRUE);
607- else
608- vgaHWRestore(pScrn, vgaReg, VGA_SR_MODE);
609+ (*pNv->Restore)(pScrn, vgaReg, nvReg, pNv->Primary);
610 vgaHWProtect(pScrn, FALSE);
611 }
612
613@@ -1666,7 +1633,6 @@
614 return FALSE;
615 } else {
616 /* Save the current state */
617- vgaHWUnlock(hwp);
618 pNv->riva.LockUnlock(&pNv->riva, 0);
619 NVSave(pScrn);
620 /* Initialise the first mode */
621@@ -1897,12 +1863,6 @@
622 vgaRegPtr vgaReg = &pVga->SavedReg;
623
624 DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NVSave\n"));
625-#if defined(__powerpc__)
626- /* The console driver will have to save the fonts, we can't */
627- vgaHWSave(pScrn, vgaReg, VGA_SR_CMAP | VGA_SR_MODE);
628-#else
629- vgaHWSave(pScrn, vgaReg, VGA_SR_CMAP | VGA_SR_MODE | VGA_SR_FONTS);
630-#endif
631- pNv->riva.UnloadStateExt(&pNv->riva, nvReg);
632+ (*pNv->Save)(pScrn, vgaReg, nvReg, pNv->Primary);
633 }
634
635--- XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/nv.orig/nv_local.h Sat Nov 4 03:46:12 2000
636+++ XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/nv/nv_local.h Sun Apr 14 15:59:41 2002
637@@ -36,40 +36,39 @@
638 |* those rights set forth herein. *|
639 |* *|
640 \***************************************************************************/
641-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_local.h,v 1.6 2000/11/03 18:46:12 eich Exp $ */
642+/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_local.h,v 1.7 2002/01/25 21:56:06 tsi Exp $ */
643
644 #ifndef __NV_LOCAL_H__
645 #define __NV_LOCAL_H__
646+
647 /*
648- * This file includes any environment or machine specific values to access the HW.
649- * Put all affected includes, typdefs, etc. here so the riva_hw.* files can stay
650- * generic in nature.
651+ * This file includes any environment or machine specific values to access the
652+ * HW. Put all affected includes, typdefs, etc. here so the riva_hw.* files
653+ * can stay generic in nature.
654 */
655 #include "xf86_ansic.h"
656 #include "compiler.h"
657+#include "xf86_OSproc.h"
658+
659 /*
660 * Typedefs to force certain sized values.
661 */
662 typedef unsigned char U008;
663 typedef unsigned short U016;
664 typedef unsigned int U032;
665+
666 /*
667- * HW access macros.
668+ * HW access macros. These assume memory-mapped I/O, and not normal I/O space.
669 */
670-#include "xf86_OSproc.h"
671-/* these assume memory-mapped I/O, and not normal I/O space */
672 #define NV_WR08(p,i,d) MMIO_OUT8((volatile pointer)(p), (i), (d))
673 #define NV_RD08(p,i) MMIO_IN8((volatile pointer)(p), (i))
674 #define NV_WR16(p,i,d) MMIO_OUT16((volatile pointer)(p), (i), (d))
675 #define NV_RD16(p,i) MMIO_IN16((volatile pointer)(p), (i))
676 #define NV_WR32(p,i,d) MMIO_OUT32((volatile pointer)(p), (i), (d))
677 #define NV_RD32(p,i) MMIO_IN32((volatile pointer)(p), (i))
678-#if 1
679+
680+/* VGA I/O is now always done through MMIO */
681 #define VGA_WR08(p,i,d) NV_WR08(p,i,d)
682 #define VGA_RD08(p,i) NV_RD08(p,i)
683-#else
684-#define VGA_WR08(p,i,d) outb(i,d)
685-#define VGA_RD08(p,i) inb(i)
686-#endif
687-#endif /* __NV_LOCAL_H__ */
688
689+#endif /* __NV_LOCAL_H__ */
690--- XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/nv.orig/nv_proto.h Wed Mar 28 10:17:43 2001
691+++ XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/nv/nv_proto.h Sun Apr 14 15:59:41 2002
692@@ -6,6 +6,8 @@
693 /* in nv_driver.c */
694 Bool NVSwitchMode(int scrnIndex, DisplayModePtr mode, int flags);
695 void NVAdjustFrame(int scrnIndex, int x, int y, int flags);
696+xf86MonPtr NVdoDDC(ScrnInfoPtr pScrn);
697+
698
699 /* in nv_dac.c */
700 void NVRamdacInit(ScrnInfoPtr pScrn);
701--- XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/nv.orig/nv_setup.c Wed Oct 31 04:38:29 2001
702+++ XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/nv/nv_setup.c Sun Apr 14 15:59:41 2002
703@@ -155,6 +155,92 @@
704 return (VGA_RD08(pNv->riva.PDIO, VGA_DAC_DATA));
705 }
706
707+static Bool
708+NVIsConnected (ScrnInfoPtr pScrn, Bool second)
709+{
710+ NVPtr pNv = NVPTR(pScrn);
711+ volatile U032 *PRAMDAC = pNv->riva.PRAMDAC0;
712+ CARD32 reg52C, reg608;
713+ Bool present;
714+
715+ if(second) PRAMDAC += 0x800;
716+
717+ reg52C = PRAMDAC[0x052C/4];
718+ reg608 = PRAMDAC[0x0608/4];
719+
720+ PRAMDAC[0x0608/4] = reg608 & ~0x00010000;
721+
722+ PRAMDAC[0x052C/4] = reg52C & 0x0000FEEE;
723+ usleep(1000);
724+ PRAMDAC[0x052C/4] |= 1;
725+
726+ pNv->riva.PRAMDAC0[0x0610/4] = 0x94050140;
727+ pNv->riva.PRAMDAC0[0x0608/4] |= 0x00001000;
728+
729+ usleep(1000);
730+
731+ present = (PRAMDAC[0x0608/4] & (1 << 28)) ? TRUE : FALSE;
732+
733+ pNv->riva.PRAMDAC0[0x0608/4] &= 0x0000EFFF;
734+
735+ PRAMDAC[0x052C/4] = reg52C;
736+ PRAMDAC[0x0608/4] = reg608;
737+
738+ return present;
739+}
740+
741+static void
742+NVOverrideCRTC(ScrnInfoPtr pScrn)
743+{
744+ NVPtr pNv = NVPTR(pScrn);
745+
746+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
747+ "Detected CRTC controller %i being used\n",
748+ pNv->SecondCRTC ? 1 : 0);
749+
750+ if(pNv->forceCRTC != -1) {
751+ xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
752+ "Forcing usage of CRTC %i\n", pNv->forceCRTC);
753+ pNv->SecondCRTC = pNv->forceCRTC;
754+ }
755+}
756+
757+static void
758+NVIsSecond (ScrnInfoPtr pScrn)
759+{
760+ NVPtr pNv = NVPTR(pScrn);
761+
762+ if(pNv->FlatPanel == 1) {
763+ switch(pNv->Chipset) {
764+ case NV_CHIP_GEFORCE4_440_GO:
765+ case NV_CHIP_GEFORCE4_440_GO_M64:
766+ case NV_CHIP_GEFORCE4_420_GO:
767+ case NV_CHIP_GEFORCE4_420_GO_M32:
768+ case NV_CHIP_QUADRO4_500_GOGL:
769+ pNv->SecondCRTC = TRUE;
770+ break;
771+ default:
772+ pNv->SecondCRTC = FALSE;
773+ break;
774+ }
775+ } else {
776+ if(NVIsConnected(pScrn, 0)) {
777+ if(pNv->riva.PRAMDAC0[0x0000052C/4] & 0x100)
778+ pNv->SecondCRTC = TRUE;
779+ else
780+ pNv->SecondCRTC = FALSE;
781+ } else
782+ if (NVIsConnected(pScrn, 1)) {
783+ if(pNv->riva.PRAMDAC0[0x0000252C/4] & 0x100)
784+ pNv->SecondCRTC = TRUE;
785+ else
786+ pNv->SecondCRTC = FALSE;
787+ } else /* default */
788+ pNv->SecondCRTC = FALSE;
789+ }
790+
791+ NVOverrideCRTC(pScrn);
792+}
793
794 static void
795 NVCommonSetup(ScrnInfoPtr pScrn)
796@@ -168,7 +254,6 @@
797 DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "- Regbase %x\n", regBase));
798 DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "- riva %x\n", &pNv->riva));
799
800- pNv->PreInit = NVRamdacInit;
801 pNv->Save = NVDACSave;
802 pNv->Restore = NVDACRestore;
803 pNv->ModeInit = NVDACInit;
804@@ -216,9 +301,9 @@
805
806 mmioFlags = VIDMEM_MMIO | VIDMEM_READSIDEEFFECT;
807
808- pNv->riva.PRAMDAC = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag,
809+ pNv->riva.PRAMDAC0 = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag,
810 regBase+0x00680000, 0x00003000);
811- DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "- PRAMDAC %x\n", pNv->riva.PRAMDAC));
812+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "- PRAMDAC %x\n", pNv->riva.PRAMDAC0));
813 pNv->riva.PFB = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag,
814 regBase+0x00100000, 0x00001000);
815 DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "- PFB %x\n", pNv->riva.PFB));
816@@ -245,22 +330,88 @@
817 * These registers are read/write as 8 bit values. Probably have to map
818 * sparse on alpha.
819 */
820- pNv->riva.PCIO = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags,
821+ pNv->riva.PCIO0 = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags,
822 pNv->PciTag, regBase+0x00601000,
823- 0x00001000);
824- pNv->riva.PDIO = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags,
825+ 0x00003000);
826+ pNv->riva.PDIO0 = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags,
827 pNv->PciTag, regBase+0x00681000,
828- 0x00001000);
829+ 0x00003000);
830 pNv->riva.PVIO = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags,
831 pNv->PciTag, regBase+0x000C0000,
832 0x00001000);
833-
834+
835+ if(pNv->FlatPanel == -1) {
836+ switch(pNv->Chipset) {
837+ case NV_CHIP_GEFORCE4_440_GO:
838+ case NV_CHIP_GEFORCE4_440_GO_M64:
839+ case NV_CHIP_GEFORCE4_420_GO:
840+ case NV_CHIP_GEFORCE4_420_GO_M32:
841+ case NV_CHIP_QUADRO4_500_GOGL:
842+ case NV_CHIP_GEFORCE2_GO:
843+ xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
844+ "On a laptop. Assuming Digital Flat Panel\n");
845+ pNv->FlatPanel = 1;
846+ break;
847+ default:
848+ break;
849+ }
850+ }
851+
852+ switch(pNv->Chipset & 0x0ff0) {
853+ case 0x0110:
854+ if(pNv->Chipset == NV_CHIP_GEFORCE2_GO)
855+ pNv->SecondCRTC = TRUE;
856+#if defined(__powerpc__)
857+ else if(pNv->FlatPanel == 1)
858+ pNv->SecondCRTC = TRUE;
859+#endif
860+ NVOverrideCRTC(pScrn);
861+ break;
862+ case 0x0170:
863+ case 0x0250:
864+ NVIsSecond(pScrn);
865+ break;
866+ default:
867+ break;
868+ }
869+
870+ if(pNv->SecondCRTC) {
871+ pNv->riva.PCIO = pNv->riva.PCIO0 + 0x2000;
872+ pNv->riva.PCRTC = pNv->riva.PCRTC0 + 0x800;
873+ pNv->riva.PRAMDAC = pNv->riva.PRAMDAC0 + 0x800;
874+ pNv->riva.PDIO = pNv->riva.PDIO0 + 0x2000;
875+ } else {
876+ pNv->riva.PCIO = pNv->riva.PCIO0;
877+ pNv->riva.PCRTC = pNv->riva.PCRTC0;
878+ pNv->riva.PRAMDAC = pNv->riva.PRAMDAC0;
879+ pNv->riva.PDIO = pNv->riva.PDIO0;
880+ }
881+
882 RivaGetConfig(pNv);
883
884 pNv->Dac.maxPixelClock = pNv->riva.MaxVClockFreqKHz;
885
886- vgaHWUnlock(VGAHWPTR(pScrn));
887 pNv->riva.LockUnlock(&pNv->riva, 0);
888+
889+ NVRamdacInit(pScrn);
890+
891+#if !defined(__powerpc__)
892+ /* Read and print the Monitor DDC info */
893+ pScrn->monitor->DDC = NVdoDDC(pScrn);
894+#endif
895+ if(pNv->FlatPanel == -1) {
896+ pNv->FlatPanel = 0;
897+ if(pScrn->monitor->DDC) {
898+ xf86MonPtr ddc = (xf86MonPtr)pScrn->monitor->DDC;
899+
900+ if(ddc->features.input_type) {
901+ pNv->FlatPanel = 1;
902+ xf86DrvMsg(pScrn->scrnIndex, X_PROBED,
903+ "autodetected Digital Flat Panel\n");
904+ }
905+ }
906+ }
907+ pNv->riva.flatPanel = (pNv->FlatPanel > 0) ? TRUE : FALSE;
908 }
909
910 void
911@@ -289,6 +440,7 @@
912 frameBase+0x00C00000, 0x00008000);
913
914 NVCommonSetup(pScrn);
915+ pNv->riva.PCRTC = pNv->riva.PCRTC0 = pNv->riva.PGRAPH;
916 }
917
918 void
919@@ -307,11 +459,12 @@
920 mmioFlags = VIDMEM_MMIO | VIDMEM_READSIDEEFFECT;
921 pNv->riva.PRAMIN = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag,
922 regBase+0x00710000, 0x00010000);
923- pNv->riva.PCRTC = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag,
924+ pNv->riva.PCRTC0 = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag,
925 regBase+0x00600000, 0x00001000);
926
927 NVCommonSetup(pScrn);
928 }
929+
930 void
931 NV10Setup(ScrnInfoPtr pScrn)
932 {
933@@ -322,14 +475,11 @@
934 DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NV10Setup\n"));
935
936 pNv->riva.Architecture = 0x10;
937- /*
938- * Map chip-specific memory-mapped registers. This MUST be done in the OS specific driver code.
939- */
940 mmioFlags = VIDMEM_MMIO | VIDMEM_READSIDEEFFECT;
941 pNv->riva.PRAMIN = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag,
942 regBase+0x00710000, 0x00010000);
943- pNv->riva.PCRTC = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag,
944- regBase+0x00600000, 0x00001000);
945+ pNv->riva.PCRTC0 = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag,
946+ regBase+0x00600000, 0x00003000);
947
948 NVCommonSetup(pScrn);
949 }
950@@ -341,18 +491,14 @@
951 CARD32 regBase = pNv->IOAddress;
952 int mmioFlags;
953
954- DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NV10Setup\n"));
955+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NV20Setup\n"));
956
957 pNv->riva.Architecture = 0x20;
958- /*
959- * Map chip-specific memory-mapped registers. This MUST be done in the OS sp
960-ecific driver code.
961- */
962 mmioFlags = VIDMEM_MMIO | VIDMEM_READSIDEEFFECT;
963 pNv->riva.PRAMIN = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag,
964 regBase+0x00710000, 0x00010000);
965- pNv->riva.PCRTC = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag,
966- regBase+0x00600000, 0x00001000);
967+ pNv->riva.PCRTC0 = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag,
968+ regBase+0x00600000, 0x00003000);
969
970 NVCommonSetup(pScrn);
971 }
972--- XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/nv.orig/nv_type.h Fri Dec 7 09:09:56 2001
973+++ XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/nv/nv_type.h Sun Apr 14 15:59:41 2002
974@@ -32,7 +32,6 @@
975 void (*SetCursorColors)(ScrnInfoPtr, int, int);
976 long maxPixelClock;
977 void (*LoadPalette)(ScrnInfoPtr, int, int*, LOCO*, VisualPtr);
978- void (*PreInit)(ScrnInfoPtr);
979 void (*Save)(ScrnInfoPtr, vgaRegPtr, NVRegPtr, Bool);
980 void (*Restore)(ScrnInfoPtr, vgaRegPtr, NVRegPtr, Bool);
981 Bool (*ModeInit)(ScrnInfoPtr, DisplayModePtr);
982@@ -80,7 +79,6 @@
983 int numDGAModes;
984 Bool DGAactive;
985 int DGAViewportStatus;
986- void (*PreInit)(ScrnInfoPtr pScrn);
987 void (*Save)(ScrnInfoPtr, vgaRegPtr, NVRegPtr, Bool);
988 void (*Restore)(ScrnInfoPtr, vgaRegPtr, NVRegPtr, Bool);
989 Bool (*ModeInit)(ScrnInfoPtr, DisplayModePtr);
990@@ -113,7 +111,9 @@
991 void (*VideoTimerCallback)(ScrnInfoPtr, Time);
992 XF86VideoAdaptorPtr overlayAdaptor;
993 int videoKey;
994- Bool FlatPanel;
995+ int FlatPanel;
996+ Bool SecondCRTC;
997+ int forceCRTC;
998 OptionInfoPtr Options;
999 } NVRec, *NVPtr;
1000
1001@@ -127,40 +127,46 @@
1002
1003 int RivaGetConfig(NVPtr);
1004
1005-#define NV_CHIP_RIVA128 ((PCI_VENDOR_NVIDIA_SGS << 16)| PCI_CHIP_RIVA128)
1006-#define NV_CHIP_TNT ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_TNT)
1007-#define NV_CHIP_TNT2 ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_TNT2)
1008-#define NV_CHIP_UTNT2 ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_UTNT2)
1009-#define NV_CHIP_VTNT2 ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_VTNT2)
1010-#define NV_CHIP_UVTNT2 ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_UVTNT2)
1011-#define NV_CHIP_ITNT2 ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_ITNT2)
1012-#define NV_CHIP_GEFORCE256 ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_GEFORCE256)
1013-#define NV_CHIP_GEFORCEDDR ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_GEFORCEDDR)
1014-#define NV_CHIP_QUADRO ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_QUADRO)
1015-#define NV_CHIP_GEFORCE2MX ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE2MX)
1016-#define NV_CHIP_GEFORCE2MXDDR ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE2MXDDR)
1017-#define NV_CHIP_IGEFORCE2 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_IGEFORCE2)
1018-#define NV_CHIP_0x0170 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_0x0170)
1019-#define NV_CHIP_0x0171 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_0x0171)
1020-#define NV_CHIP_0x0172 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_0x0172)
1021-#define NV_CHIP_0x0173 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_0x0173)
1022-#define NV_CHIP_0x0174 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_0x0174)
1023-#define NV_CHIP_0x0175 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_0x0175)
1024-#define NV_CHIP_0x0178 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_0x0178)
1025-#define NV_CHIP_0x017A ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_0x017A)
1026-#define NV_CHIP_0x017B ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_0x017B)
1027-#define NV_CHIP_0x017C ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_0x017C)
1028-#define NV_CHIP_QUADRO2MXR ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_QUADRO2MXR)
1029-#define NV_CHIP_GEFORCE2GO ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE2GO)
1030-#define NV_CHIP_GEFORCE2GTS ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE2GTS)
1031-#define NV_CHIP_GEFORCE2GTS_1 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE2GTS_1)
1032-#define NV_CHIP_GEFORCE2ULTRA ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE2ULTRA)
1033-#define NV_CHIP_QUADRO2PRO ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_QUADRO2PRO)
1034-#define NV_CHIP_GEFORCE3 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE3)
1035-#define NV_CHIP_GEFORCE3_1 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE3_1)
1036-#define NV_CHIP_GEFORCE3_2 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE3_2)
1037-#define NV_CHIP_QUADRO_DDC ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_QUADRO_DDC)
1038-#define NV_CHIP_0x0250 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_0x0250)
1039-#define NV_CHIP_0x0258 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_0x0258)
1040+#define NV_CHIP_RIVA_128 ((PCI_VENDOR_NVIDIA_SGS << 16)| PCI_CHIP_RIVA128)
1041+#define NV_CHIP_TNT ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_TNT)
1042+#define NV_CHIP_TNT2 ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_TNT2)
1043+#define NV_CHIP_UTNT2 ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_UTNT2)
1044+#define NV_CHIP_VTNT2 ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_VTNT2)
1045+#define NV_CHIP_UVTNT2 ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_UVTNT2)
1046+#define NV_CHIP_ITNT2 ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_ITNT2)
1047+#define NV_CHIP_GEFORCE_256 ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_GEFORCE_256)
1048+#define NV_CHIP_GEFORCE_DDR ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_GEFORCE_DDR)
1049+#define NV_CHIP_QUADRO ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_QUADRO)
1050+#define NV_CHIP_GEFORCE2_MX ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE2_MX)
1051+#define NV_CHIP_GEFORCE2_MX_100 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE2_MX_100)
1052+#define NV_CHIP_QUADRO2_MXR ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_QUADRO2_MXR)
1053+#define NV_CHIP_GEFORCE2_GO ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE2_GO)
1054+#define NV_CHIP_GEFORCE2_GTS ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE2_GTS)
1055+#define NV_CHIP_GEFORCE2_TI ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE2_TI)
1056+#define NV_CHIP_GEFORCE2_ULTRA ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE2_ULTRA)
1057+#define NV_CHIP_QUADRO2_PRO ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_QUADRO2_PRO)
1058+#define NV_CHIP_GEFORCE4_MX_460 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE4_MX_460)
1059+#define NV_CHIP_GEFORCE4_MX_440 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE4_MX_440)
1060+#define NV_CHIP_GEFORCE4_MX_420 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE4_MX_420)
1061+#define NV_CHIP_GEFORCE4_440_GO ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE4_440_GO)
1062+#define NV_CHIP_GEFORCE4_420_GO ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE4_420_GO)
1063+#define NV_CHIP_GEFORCE4_420_GO_M32 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE4_420_GO_M32)
1064+#define NV_CHIP_QUADRO4_500XGL ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_QUADRO4_500XGL)
1065+#define NV_CHIP_GEFORCE4_440_GO_M64 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE4_440_GO_M64)
1066+#define NV_CHIP_QUADRO4_200 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_QUADRO4_200)
1067+#define NV_CHIP_QUADRO4_550XGL ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_QUADRO4_550XGL)
1068+#define NV_CHIP_QUADRO4_500_GOGL ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_QUADRO4_500_GOGL)
1069+#define NV_CHIP_IGEFORCE2 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_IGEFORCE2)
1070+#define NV_CHIP_GEFORCE3 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE3)
1071+#define NV_CHIP_GEFORCE3_TI_200 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE3_TI_200)
1072+#define NV_CHIP_GEFORCE3_TI_500 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE3_TI_500)
1073+#define NV_CHIP_QUADRO_DCC ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_QUADRO_DCC)
1074+#define NV_CHIP_GEFORCE4_TI_4600 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE4_TI_4600)
1075+#define NV_CHIP_GEFORCE4_TI_4400 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE4_TI_4400)
1076+#define NV_CHIP_GEFORCE4_TI_4200 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE4_TI_4200)
1077+#define NV_CHIP_QUADRO4_900XGL ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_QUADRO4_900XGL)
1078+#define NV_CHIP_QUADRO4_750XGL ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_QUADRO4_750XGL)
1079+#define NV_CHIP_QUADRO4_700XGL ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_QUADRO4_700XGL)
1080+
1081
1082 #endif /* __NV_STRUCT_H__ */
1083--- XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/nv.orig/nvreg.h Fri Nov 12 11:12:41 1999
1084+++ XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/nv/nvreg.h Sun Apr 14 15:59:41 2002
1085@@ -164,18 +164,9 @@
1086 (PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\
1087 (PDAC_Write(INDEX_DATA,(value))))
1088
1089-#define CRTC_Write(index,value) outb(0x3d4,(index));outb(0x3d5,value)
1090-#define CRTC_Read(index) (outb(0x3d4,index),inb(0x3d5))
1091-
1092-#define PCRTC_Write(index,value) CRTC_Write(NV_PCRTC_##index,value)
1093-#define PCRTC_Read(index) CRTC_Read(NV_PCRTC_##index)
1094-
1095 #define PCRTC_Def(mask,value) DEVICE_DEF(PCRTC,mask,value)
1096 #define PCRTC_Val(mask,value) DEVICE_VALUE(PCRTC,mask,value)
1097 #define PCRTC_Mask(mask) DEVICE_MASK(PCRTC,mask)
1098-
1099-#define SR_Write(index,value) outb(0x3c4,(index));outb(0x3c5,value)
1100-#define SR_Read(index) (outb(0x3c4,index),inb(0x3c5))
1101
1102
1103 /* These are the variables which actually point at the register blocks */
1104--- XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/nv.orig/riva_hw.c Tue Dec 18 07:17:55 2001
1105+++ XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.c Sun Apr 14 15:59:41 2002
1106@@ -70,34 +70,40 @@
1107 {
1108 return ((chip->Rop->FifoFree < chip->FifoEmptyCount) || (chip->PGRAPH[0x00000700/4] & 0x01));
1109 }
1110-static void nv3LockUnlock
1111+static void vgaLockUnlock
1112 (
1113 RIVA_HW_INST *chip,
1114- int LockUnlock
1115+ Bool Lock
1116 )
1117 {
1118- VGA_WR08(chip->PVIO, 0x3C4, 0x06);
1119- VGA_WR08(chip->PVIO, 0x3C5, LockUnlock ? 0x99 : 0x57);
1120+ CARD8 cr11;
1121+ VGA_WR08(chip->PCIO, 0x3D4, 0x11);
1122+ cr11 = VGA_RD08(chip->PCIO, 0x3D5);
1123+ if(Lock) cr11 |= 0x80;
1124+ else cr11 &= ~0x80;
1125+ VGA_WR08(chip->PCIO, 0x3D5, cr11);
1126 }
1127-static void nv4LockUnlock
1128+
1129+static void nv3LockUnlock
1130 (
1131 RIVA_HW_INST *chip,
1132- int LockUnlock
1133+ Bool Lock
1134 )
1135 {
1136- VGA_WR08(chip->PCIO, 0x3D4, 0x1F);
1137- VGA_WR08(chip->PCIO, 0x3D5, LockUnlock ? 0x99 : 0x57);
1138+ VGA_WR08(chip->PVIO, 0x3C4, 0x06);
1139+ VGA_WR08(chip->PVIO, 0x3C5, Lock ? 0x99 : 0x57);
1140+ vgaLockUnlock(chip, Lock);
1141 }
1142-static void nv10LockUnlock
1143+static void nv4LockUnlock
1144 (
1145 RIVA_HW_INST *chip,
1146- int LockUnlock
1147+ Bool Lock
1148 )
1149 {
1150 VGA_WR08(chip->PCIO, 0x3D4, 0x1F);
1151- VGA_WR08(chip->PCIO, 0x3D5, LockUnlock ? 0x99 : 0x57);
1152+ VGA_WR08(chip->PCIO, 0x3D5, Lock ? 0x99 : 0x57);
1153+ vgaLockUnlock(chip, Lock);
1154 }
1155-
1156 static int ShowHideCursor
1157 (
1158 RIVA_HW_INST *chip,
1159@@ -601,7 +607,7 @@
1160 nv3_sim_state sim_data;
1161 unsigned int M, N, P, pll, MClk;
1162
1163- pll = chip->PRAMDAC[0x00000504/4];
1164+ pll = chip->PRAMDAC0[0x00000504/4];
1165 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
1166 MClk = (N * chip->CrystalFreqKHz / M) >> P;
1167 sim_data.pix_bpp = (char)pixelDepth;
1168@@ -788,10 +794,10 @@
1169 nv4_sim_state sim_data;
1170 unsigned int M, N, P, pll, MClk, NVClk, cfg1;
1171
1172- pll = chip->PRAMDAC[0x00000504/4];
1173+ pll = chip->PRAMDAC0[0x00000504/4];
1174 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
1175 MClk = (N * chip->CrystalFreqKHz / M) >> P;
1176- pll = chip->PRAMDAC[0x00000500/4];
1177+ pll = chip->PRAMDAC0[0x00000500/4];
1178 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
1179 NVClk = (N * chip->CrystalFreqKHz / M) >> P;
1180 cfg1 = chip->PFB[0x00000204/4];
1181@@ -1049,10 +1055,10 @@
1182 nv10_sim_state sim_data;
1183 unsigned int M, N, P, pll, MClk, NVClk, cfg1;
1184
1185- pll = chip->PRAMDAC[0x00000504/4];
1186+ pll = chip->PRAMDAC0[0x00000504/4];
1187 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
1188 MClk = (N * chip->CrystalFreqKHz / M) >> P;
1189- pll = chip->PRAMDAC[0x00000500/4];
1190+ pll = chip->PRAMDAC0[0x00000500/4];
1191 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
1192 NVClk = (N * chip->CrystalFreqKHz / M) >> P;
1193 cfg1 = chip->PFB[0x00000204/4];
1194@@ -1078,6 +1084,66 @@
1195 }
1196 }
1197
1198+static void nForceUpdateArbitrationSettings
1199+(
1200+ unsigned VClk,
1201+ unsigned pixelDepth,
1202+ unsigned *burst,
1203+ unsigned *lwm,
1204+ RIVA_HW_INST *chip
1205+)
1206+{
1207+ nv10_fifo_info fifo_data;
1208+ nv10_sim_state sim_data;
1209+ unsigned int M, N, P, pll, MClk, NVClk;
1210+ unsigned int uMClkPostDiv, memctrl;
1211+
1212+ uMClkPostDiv = (pciReadLong(pciTag(0, 0, 3), 0x6C) >> 8) & 0xf;
1213+ if(!uMClkPostDiv) uMClkPostDiv = 4;
1214+ MClk = 400000 / uMClkPostDiv;
1215+
1216+ pll = chip->PRAMDAC0[0x00000500/4];
1217+ M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F;
1218+ NVClk = (N * chip->CrystalFreqKHz / M) >> P;
1219+ sim_data.pix_bpp = (char)pixelDepth;
1220+ sim_data.enable_video = 0;
1221+ sim_data.enable_mp = 0;
1222+ sim_data.memory_type = (pciReadLong(pciTag(0, 0, 1), 0x7C) >> 12) & 1;
1223+ sim_data.memory_width = 64;
1224+
1225+ memctrl = pciReadLong(pciTag(0, 0, 3), 0x00) >> 16;
1226+
1227+ if((memctrl == 0x1A9) || (memctrl == 0x1AB)) {
1228+ int dimm[3];
1229+
1230+ dimm[0] = (pciReadLong(pciTag(0, 0, 2), 0x40) >> 8) & 0x4F;
1231+ dimm[1] = (pciReadLong(pciTag(0, 0, 2), 0x44) >> 8) & 0x4F;
1232+ dimm[2] = (pciReadLong(pciTag(0, 0, 2), 0x48) >> 8) & 0x4F;
1233+
1234+ if((dimm[0] + dimm[1]) != dimm[2]) {
1235+ ErrorF("WARNING: "
1236+ "your nForce DIMMs are not arranged in optimal banks!\n");
1237+ }
1238+ }
1239+
1240+ sim_data.mem_latency = 3;
1241+ sim_data.mem_aligned = 1;
1242+ sim_data.mem_page_miss = 10;
1243+ sim_data.gr_during_vid = 0;
1244+ sim_data.pclk_khz = VClk;
1245+ sim_data.mclk_khz = MClk;
1246+ sim_data.nvclk_khz = NVClk;
1247+ nv10CalcArbitration(&fifo_data, &sim_data);
1248+ if (fifo_data.valid)
1249+ {
1250+ int b = fifo_data.graphics_burst_size >> 4;
1251+ *burst = 0;
1252+ while (b >>= 1) (*burst)++;
1253+ *lwm = fifo_data.graphics_lwm >> 3;
1254+ }
1255+}
1256+
1257+
1258 /****************************************************************************\
1259 * *
1260 * RIVA Mode State Routines *
1261@@ -1211,11 +1277,19 @@
1262 break;
1263 case NV_ARCH_10:
1264 case NV_ARCH_20:
1265- nv10UpdateArbitrationSettings(VClk,
1266+ if(chip->Chipset == NV_CHIP_IGEFORCE2) {
1267+ nForceUpdateArbitrationSettings(VClk,
1268+ pixelDepth * 8,
1269+ &(state->arbitration0),
1270+ &(state->arbitration1),
1271+ chip);
1272+ } else {
1273+ nv10UpdateArbitrationSettings(VClk,
1274 pixelDepth * 8,
1275 &(state->arbitration0),
1276 &(state->arbitration1),
1277 chip);
1278+ }
1279 state->cursor0 = 0x80 | (chip->CursorStart >> 17);
1280 state->cursor1 = (chip->CursorStart >> 11) << 2;
1281 state->cursor2 = chip->CursorStart >> 24;
1282@@ -1272,18 +1346,10 @@
1283 {
1284 case NV_ARCH_04:
1285 LOAD_FIXED_STATE(nv4,FIFO);
1286- chip->Tri03 = 0L;
1287- chip->Tri05 = (RivaTexturedTriangle05 *)&(chip->FIFO[0x0000E000/4]);
1288 break;
1289 case NV_ARCH_10:
1290 case NV_ARCH_20:
1291- /*
1292- * Initialize state for the RivaTriangle3D05 routines.
1293- */
1294- LOAD_FIXED_STATE(nv10tri05,PGRAPH);
1295 LOAD_FIXED_STATE(nv10,FIFO);
1296- chip->Tri03 = 0L;
1297- chip->Tri05 = (RivaTexturedTriangle05 *)&(chip->FIFO[0x0000E000/4]);
1298 break;
1299 }
1300 }
1301@@ -1316,19 +1382,16 @@
1302 case 16:
1303 LOAD_FIXED_STATE_15BPP(nv3,PRAMIN);
1304 LOAD_FIXED_STATE_15BPP(nv3,PGRAPH);
1305- chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]);
1306 break;
1307 case 24:
1308 case 32:
1309 LOAD_FIXED_STATE_32BPP(nv3,PRAMIN);
1310 LOAD_FIXED_STATE_32BPP(nv3,PGRAPH);
1311- chip->Tri03 = 0L;
1312 break;
1313 case 8:
1314 default:
1315 LOAD_FIXED_STATE_8BPP(nv3,PRAMIN);
1316 LOAD_FIXED_STATE_8BPP(nv3,PGRAPH);
1317- chip->Tri03 = 0L;
1318 break;
1319 }
1320 for (i = 0x00000; i < 0x00800; i++)
1321@@ -1355,24 +1418,20 @@
1322 case 15:
1323 LOAD_FIXED_STATE_15BPP(nv4,PRAMIN);
1324 LOAD_FIXED_STATE_15BPP(nv4,PGRAPH);
1325- chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]);
1326 break;
1327 case 16:
1328 LOAD_FIXED_STATE_16BPP(nv4,PRAMIN);
1329 LOAD_FIXED_STATE_16BPP(nv4,PGRAPH);
1330- chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]);
1331 break;
1332 case 24:
1333 case 32:
1334 LOAD_FIXED_STATE_32BPP(nv4,PRAMIN);
1335 LOAD_FIXED_STATE_32BPP(nv4,PGRAPH);
1336- chip->Tri03 = 0L;
1337 break;
1338 case 8:
1339 default:
1340 LOAD_FIXED_STATE_8BPP(nv4,PRAMIN);
1341 LOAD_FIXED_STATE_8BPP(nv4,PGRAPH);
1342- chip->Tri03 = 0L;
1343 break;
1344 }
1345 chip->PGRAPH[0x00000640/4] = state->offset0;
1346@@ -1386,6 +1445,12 @@
1347 break;
1348 case NV_ARCH_10:
1349 case NV_ARCH_20:
1350+ if(chip->twoHeads) {
1351+ VGA_WR08(chip->PCIO, 0x03D4, 0x44);
1352+ VGA_WR08(chip->PCIO, 0x03D5, state->crtcOwner);
1353+ chip->LockUnlock(chip, 0);
1354+ }
1355+
1356 LOAD_FIXED_STATE(nv10,PFIFO);
1357 LOAD_FIXED_STATE(nv10,PRAMIN);
1358 LOAD_FIXED_STATE(nv10,PGRAPH);
1359@@ -1394,24 +1459,20 @@
1360 case 15:
1361 LOAD_FIXED_STATE_15BPP(nv10,PRAMIN);
1362 LOAD_FIXED_STATE_15BPP(nv10,PGRAPH);
1363- chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]);
1364 break;
1365 case 16:
1366 LOAD_FIXED_STATE_16BPP(nv10,PRAMIN);
1367 LOAD_FIXED_STATE_16BPP(nv10,PGRAPH);
1368- chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]);
1369 break;
1370 case 24:
1371 case 32:
1372 LOAD_FIXED_STATE_32BPP(nv10,PRAMIN);
1373 LOAD_FIXED_STATE_32BPP(nv10,PGRAPH);
1374- chip->Tri03 = 0L;
1375 break;
1376 case 8:
1377 default:
1378 LOAD_FIXED_STATE_8BPP(nv10,PRAMIN);
1379 LOAD_FIXED_STATE_8BPP(nv10,PGRAPH);
1380- chip->Tri03 = 0L;
1381 break;
1382 }
1383
1384@@ -1438,11 +1499,12 @@
1385 chip->PGRAPH[0x00000864/4] = state->pitch3;
1386 chip->PGRAPH[0x000009A4/4] = chip->PFB[0x00000200/4];
1387 chip->PGRAPH[0x000009A8/4] = chip->PFB[0x00000204/4];
1388- chip->PRAMDAC[0x0000052C/4] = 0x00000101;
1389- chip->PRAMDAC[0x0000252C/4] = 0x00000001;
1390 }
1391+ if(chip->twoHeads) {
1392+ chip->PCRTC0[0x00000860/4] = state->head;
1393+ chip->PCRTC0[0x00002860/4] = state->head2;
1394+ }
1395 chip->PRAMDAC[0x00000404/4] |= (1 << 25);
1396- chip->PRAMDAC[0x00002404/4] |= (1 << 25);
1397
1398 chip->PMC[0x00008704/4] = 1;
1399 chip->PMC[0x00008140/4] = 0;
1400@@ -1450,6 +1512,7 @@
1401 chip->PMC[0x00008924/4] = 0;
1402 chip->PMC[0x00008908/4] = 0x01ffffff;
1403 chip->PMC[0x0000890C/4] = 0x01ffffff;
1404+ chip->PMC[0x00001588/4] = 0;
1405
1406 chip->PFB[0x00000240/4] = 0;
1407 chip->PFB[0x00000244/4] = 0;
1408@@ -1533,14 +1596,24 @@
1409 chip->PGRAPH[0x00000F50/4] = 0x00000040;
1410 for (i = 0; i < 4; i++)
1411 chip->PGRAPH[0x00000F54/4] = 0x00000000;
1412+
1413+ if(chip->flatPanel) {
1414+ VGA_WR08(chip->PCIO, 0x03D4, 0x53);
1415+ VGA_WR08(chip->PCIO, 0x03D5, 0);
1416+ VGA_WR08(chip->PCIO, 0x03D4, 0x54);
1417+ VGA_WR08(chip->PCIO, 0x03D5, 0);
1418+ VGA_WR08(chip->PCIO, 0x03D4, 0x21);
1419+ VGA_WR08(chip->PCIO, 0x03D5, 0xfa);
1420+ }
1421 break;
1422 }
1423+
1424 LOAD_FIXED_STATE(Riva,FIFO);
1425 UpdateFifoState(chip);
1426+
1427 /*
1428 * Load HW mode state.
1429 */
1430-
1431 VGA_WR08(chip->PCIO, 0x03D4, 0x19);
1432 VGA_WR08(chip->PCIO, 0x03D5, state->repaint0);
1433 VGA_WR08(chip->PCIO, 0x03D4, 0x1A);
1434@@ -1565,14 +1638,22 @@
1435 VGA_WR08(chip->PCIO, 0x03D5, state->interlace);
1436 VGA_WR08(chip->PCIO, 0x03D4, 0x41);
1437 VGA_WR08(chip->PCIO, 0x03D5, state->extra);
1438- chip->PRAMDAC[0x00000508/4] = state->vpll;
1439- chip->PRAMDAC[0x0000050C/4] = state->pllsel;
1440+
1441+ if(!chip->flatPanel) {
1442+ chip->PRAMDAC0[0x00000508/4] = state->vpll;
1443+ chip->PRAMDAC0[0x0000050C/4] = state->pllsel;
1444+ if(chip->twoHeads)
1445+ chip->PRAMDAC0[0x00000520/4] = state->vpll2;
1446+ } else {
1447+ chip->PRAMDAC[0x00000848/4] = state->scale;
1448+ }
1449 chip->PRAMDAC[0x00000600/4] = state->general;
1450+
1451 /*
1452 * Turn off VBlank enable and reset.
1453 */
1454- *(chip->VBLANKENABLE) = 0;
1455- *(chip->VBLANK) = chip->VBlankBit;
1456+ chip->PCRTC[0x00000140/4] = 0;
1457+ chip->PCRTC[0x00000100/4] = chip->VBlankBit;
1458 /*
1459 * Set interrupt enable.
1460 */
1461@@ -1588,6 +1669,7 @@
1462 /* Free count from first subchannel */
1463 chip->FifoEmptyCount = chip->Rop->FifoFree;
1464 }
1465+
1466 static void UnloadStateExt
1467 (
1468 RIVA_HW_INST *chip,
1469@@ -1621,10 +1703,13 @@
1470 state->interlace = VGA_RD08(chip->PCIO, 0x03D5);
1471 VGA_WR08(chip->PCIO, 0x03D4, 0x41);
1472 state->extra = VGA_RD08(chip->PCIO, 0x03D5);
1473- state->vpll = chip->PRAMDAC[0x00000508/4];
1474- state->pllsel = chip->PRAMDAC[0x0000050C/4];
1475+ state->vpll = chip->PRAMDAC0[0x00000508/4];
1476+ state->vpll2 = chip->PRAMDAC0[0x00000520/4];
1477+ state->pllsel = chip->PRAMDAC0[0x0000050C/4];
1478 state->general = chip->PRAMDAC[0x00000600/4];
1479+ state->scale = chip->PRAMDAC[0x00000848/4];
1480 state->config = chip->PFB[0x00000200/4];
1481+
1482 switch (chip->Architecture)
1483 {
1484 case NV_ARCH_03:
1485@@ -1657,6 +1742,13 @@
1486 state->pitch1 = chip->PGRAPH[0x00000674/4];
1487 state->pitch2 = chip->PGRAPH[0x00000678/4];
1488 state->pitch3 = chip->PGRAPH[0x0000067C/4];
1489+ if(chip->twoHeads) {
1490+ state->head = chip->PCRTC0[0x00000860/4];
1491+ state->head2 = chip->PCRTC0[0x00002860/4];
1492+ VGA_WR08(chip->PCIO, 0x03D4, 0x44);
1493+ state->crtcOwner = VGA_RD08(chip->PCIO, 0x03D5);
1494+ }
1495+
1496 break;
1497 }
1498 }
1499@@ -1666,6 +1758,15 @@
1500 unsigned start
1501 )
1502 {
1503+ chip->PCRTC[0x800/4] = start;
1504+}
1505+
1506+static void SetStartAddress3
1507+(
1508+ RIVA_HW_INST *chip,
1509+ unsigned start
1510+)
1511+{
1512 int offset = start >> 2;
1513 int pan = (start & 3) << 1;
1514 unsigned char tmp;
1515@@ -1692,99 +1793,6 @@
1516 VGA_WR08(chip->PCIO, 0x3C0, 0x13);
1517 VGA_WR08(chip->PCIO, 0x3C0, pan);
1518 }
1519-static void nv3SetSurfaces2D
1520-(
1521- RIVA_HW_INST *chip,
1522- unsigned surf0,
1523- unsigned surf1
1524-)
1525-{
1526- RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]);
1527-
1528- RIVA_FIFO_FREE(*chip,Tri03,5);
1529- chip->FIFO[0x00003800] = 0x80000003;
1530- Surface->Offset = surf0;
1531- chip->FIFO[0x00003800] = 0x80000004;
1532- Surface->Offset = surf1;
1533- chip->FIFO[0x00003800] = 0x80000013;
1534-}
1535-static void nv4SetSurfaces2D
1536-(
1537- RIVA_HW_INST *chip,
1538- unsigned surf0,
1539- unsigned surf1
1540-)
1541-{
1542- RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]);
1543-
1544- chip->FIFO[0x00003800] = 0x80000003;
1545- Surface->Offset = surf0;
1546- chip->FIFO[0x00003800] = 0x80000004;
1547- Surface->Offset = surf1;
1548- chip->FIFO[0x00003800] = 0x80000014;
1549-}
1550-static void nv10SetSurfaces2D
1551-(
1552- RIVA_HW_INST *chip,
1553- unsigned surf0,
1554- unsigned surf1
1555-)
1556-{
1557- RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]);
1558-
1559- chip->FIFO[0x00003800] = 0x80000003;
1560- Surface->Offset = surf0;
1561- chip->FIFO[0x00003800] = 0x80000004;
1562- Surface->Offset = surf1;
1563- chip->FIFO[0x00003800] = 0x80000014;
1564-}
1565-static void nv3SetSurfaces3D
1566-(
1567- RIVA_HW_INST *chip,
1568- unsigned surf0,
1569- unsigned surf1
1570-)
1571-{
1572- RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]);
1573-
1574- RIVA_FIFO_FREE(*chip,Tri03,5);
1575- chip->FIFO[0x00003800] = 0x80000005;
1576- Surface->Offset = surf0;
1577- chip->FIFO[0x00003800] = 0x80000006;
1578- Surface->Offset = surf1;
1579- chip->FIFO[0x00003800] = 0x80000013;
1580-}
1581-static void nv4SetSurfaces3D
1582-(
1583- RIVA_HW_INST *chip,
1584- unsigned surf0,
1585- unsigned surf1
1586-)
1587-{
1588- RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]);
1589-
1590- chip->FIFO[0x00003800] = 0x80000005;
1591- Surface->Offset = surf0;
1592- chip->FIFO[0x00003800] = 0x80000006;
1593- Surface->Offset = surf1;
1594- chip->FIFO[0x00003800] = 0x80000014;
1595-}
1596-static void nv10SetSurfaces3D
1597-(
1598- RIVA_HW_INST *chip,
1599- unsigned surf0,
1600- unsigned surf1
1601-)
1602-{
1603- RivaSurface3D *Surfaces3D = (RivaSurface3D *)&(chip->FIFO[0x0000E000/4]);
1604-
1605- RIVA_FIFO_FREE(*chip,Tri03,4);
1606- chip->FIFO[0x00003800] = 0x80000007;
1607- Surfaces3D->RenderBufferOffset = surf0;
1608- Surfaces3D->ZBufferOffset = surf1;
1609- chip->FIFO[0x00003800] = 0x80000014;
1610-}
1611-
1612 /****************************************************************************\
1613 * *
1614 * Probe RIVA Chip Configuration *
1615@@ -1848,9 +1856,6 @@
1616 }
1617 chip->CrystalFreqKHz = (chip->PEXTDEV[0x00000000/4] & 0x00000040) ? 14318 : 13500;
1618 chip->CURSOR = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]);
1619- chip->CURSORPOS = &(chip->PRAMDAC[0x0300/4]);
1620- chip->VBLANKENABLE = &(chip->PGRAPH[0x0140/4]);
1621- chip->VBLANK = &(chip->PGRAPH[0x0100/4]);
1622 chip->VBlankBit = 0x00000100;
1623 chip->MaxVClockFreqKHz = 256000;
1624 /*
1625@@ -1861,9 +1866,7 @@
1626 chip->CalcStateExt = CalcStateExt;
1627 chip->LoadStateExt = LoadStateExt;
1628 chip->UnloadStateExt = UnloadStateExt;
1629- chip->SetStartAddress = SetStartAddress;
1630- chip->SetSurfaces2D = nv3SetSurfaces2D;
1631- chip->SetSurfaces3D = nv3SetSurfaces3D;
1632+ chip->SetStartAddress = SetStartAddress3;
1633 chip->LockUnlock = nv3LockUnlock;
1634 }
1635 static void nv4GetConfig
1636@@ -1909,9 +1912,6 @@
1637 }
1638 chip->CrystalFreqKHz = (chip->PEXTDEV[0x00000000/4] & 0x00000040) ? 14318 : 13500;
1639 chip->CURSOR = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]);
1640- chip->CURSORPOS = &(chip->PRAMDAC[0x0300/4]);
1641- chip->VBLANKENABLE = &(chip->PCRTC[0x0140/4]);
1642- chip->VBLANK = &(chip->PCRTC[0x0100/4]);
1643 chip->VBlankBit = 0x00000001;
1644 chip->MaxVClockFreqKHz = 350000;
1645 /*
1646@@ -1923,8 +1923,6 @@
1647 chip->LoadStateExt = LoadStateExt;
1648 chip->UnloadStateExt = UnloadStateExt;
1649 chip->SetStartAddress = SetStartAddress;
1650- chip->SetSurfaces2D = nv4SetSurfaces2D;
1651- chip->SetSurfaces3D = nv4SetSurfaces3D;
1652 chip->LockUnlock = nv4LockUnlock;
1653 }
1654 static void nv10GetConfig
1655@@ -1989,9 +1987,6 @@
1656 13500;
1657 chip->CursorStart = (chip->RamAmountKBytes - 128) * 1024;
1658 chip->CURSOR = NULL; /* can't set this here */
1659- chip->CURSORPOS = &(chip->PRAMDAC[0x0300/4]);
1660- chip->VBLANKENABLE = &(chip->PCRTC[0x0140/4]);
1661- chip->VBLANK = &(chip->PCRTC[0x0100/4]);
1662 chip->VBlankBit = 0x00000001;
1663 chip->MaxVClockFreqKHz = 350000;
1664 /*
1665@@ -2003,9 +1998,18 @@
1666 chip->LoadStateExt = LoadStateExt;
1667 chip->UnloadStateExt = UnloadStateExt;
1668 chip->SetStartAddress = SetStartAddress;
1669- chip->SetSurfaces2D = nv10SetSurfaces2D;
1670- chip->SetSurfaces3D = nv10SetSurfaces3D;
1671- chip->LockUnlock = nv10LockUnlock;
1672+ chip->LockUnlock = nv4LockUnlock;
1673+
1674+ switch(pNv->Chipset & 0x0ff0) {
1675+ case 0x0110:
1676+ case 0x0170:
1677+ case 0x0250:
1678+ chip->twoHeads = TRUE;
1679+ break;
1680+ default:
1681+ chip->twoHeads = FALSE;
1682+ break;
1683+ }
1684 }
1685 int RivaGetConfig
1686 (
1687@@ -2035,6 +2039,7 @@
1688 default:
1689 return (-1);
1690 }
1691+ chip->Chipset = pNv->Chipset;
1692 /*
1693 * Fill in FIFO pointers.
1694 */
1695@@ -2045,7 +2050,6 @@
1696 chip->Blt = (RivaScreenBlt *)&(chip->FIFO[0x00008000/4]);
1697 chip->Bitmap = (RivaBitmap *)&(chip->FIFO[0x0000A000/4]);
1698 chip->Line = (RivaLine *)&(chip->FIFO[0x0000C000/4]);
1699- chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]);
1700 return (0);
1701 }
1702
1703--- XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/nv.orig/riva_hw.h Tue Oct 9 07:28:53 2001
1704+++ XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.h Sun Apr 14 15:59:41 2002
1705@@ -225,74 +225,6 @@
1706 U032 MonochromeData01E;
1707 } RivaBitmap;
1708 /*
1709- * 3D textured, Z buffered triangle.
1710- */
1711-typedef volatile struct
1712-{
1713- U032 reserved00[4];
1714-#if X_BYTE_ORDER == X_BIG_ENDIAN
1715- U032 FifoFree;
1716-#else
1717- U016 FifoFree;
1718- U016 Nop;
1719-#endif
1720- U032 reserved01[0x0BC];
1721- U032 TextureOffset;
1722- U032 TextureFormat;
1723- U032 TextureFilter;
1724- U032 FogColor;
1725-/* This is a problem on LynxOS */
1726-#ifdef Control
1727-#undef Control
1728-#endif
1729- U032 Control;
1730- U032 AlphaTest;
1731- U032 reserved02[0x339];
1732- U032 FogAndIndex;
1733- U032 Color;
1734- float ScreenX;
1735- float ScreenY;
1736- float ScreenZ;
1737- float EyeM;
1738- float TextureS;
1739- float TextureT;
1740-} RivaTexturedTriangle03;
1741-typedef volatile struct
1742-{
1743- U032 reserved00[4];
1744-#if X_BYTE_ORDER == X_BIG_ENDIAN
1745- U032 FifoFree;
1746-#else
1747- U016 FifoFree;
1748- U016 Nop;
1749-#endif
1750- U032 reserved01[0x0BB];
1751- U032 ColorKey;
1752- U032 TextureOffset;
1753- U032 TextureFormat;
1754- U032 TextureFilter;
1755- U032 Blend;
1756-/* This is a problem on LynxOS */
1757-#ifdef Control
1758-#undef Control
1759-#endif
1760- U032 Control;
1761- U032 FogColor;
1762- U032 reserved02[0x39];
1763- struct
1764- {
1765- float ScreenX;
1766- float ScreenY;
1767- float ScreenZ;
1768- float EyeM;
1769- U032 Color;
1770- U032 Specular;
1771- float TextureS;
1772- float TextureT;
1773- } Vertex[16];
1774- U032 DrawTriangle3D;
1775-} RivaTexturedTriangle05;
1776-/*
1777 * 2D line.
1778 */
1779 typedef volatile struct
1780@@ -375,6 +307,7 @@
1781 */
1782 U032 Architecture;
1783 U032 Version;
1784+ U032 Chipset;
1785 U032 CrystalFreqKHz;
1786 U032 RamAmountKBytes;
1787 U032 MaxVClockFreqKHz;
1788@@ -385,11 +318,14 @@
1789 U032 FifoFreeCount;
1790 U032 FifoEmptyCount;
1791 U032 CursorStart;
1792+ Bool flatPanel;
1793+ Bool twoHeads;
1794 /*
1795 * Non-FIFO registers.
1796 */
1797+ volatile U032 *PCRTC0;
1798 volatile U032 *PCRTC;
1799- volatile U032 *PRAMDAC;
1800+ volatile U032 *PRAMDAC0;
1801 volatile U032 *PFB;
1802 volatile U032 *PFIFO;
1803 volatile U032 *PGRAPH;
1804@@ -399,12 +335,12 @@
1805 volatile U032 *PRAMIN;
1806 volatile U032 *FIFO;
1807 volatile U032 *CURSOR;
1808- volatile U032 *CURSORPOS;
1809- volatile U032 *VBLANKENABLE;
1810- volatile U032 *VBLANK;
1811+ volatile U008 *PCIO0;
1812 volatile U008 *PCIO;
1813 volatile U008 *PVIO;
1814+ volatile U008 *PDIO0;
1815 volatile U008 *PDIO;
1816+ volatile U032 *PRAMDAC;
1817 /*
1818 * Common chip functions.
1819 */
1820@@ -413,8 +349,6 @@
1821 void (*LoadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *);
1822 void (*UnloadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *);
1823 void (*SetStartAddress)(struct _riva_hw_inst *,U032);
1824- void (*SetSurfaces2D)(struct _riva_hw_inst *,U032,U032);
1825- void (*SetSurfaces3D)(struct _riva_hw_inst *,U032,U032);
1826 int (*ShowHideCursor)(struct _riva_hw_inst *,int);
1827 void (*LockUnlock)(struct _riva_hw_inst *, int);
1828 /*
1829@@ -431,8 +365,6 @@
1830 RivaScreenBlt *Blt;
1831 RivaBitmap *Bitmap;
1832 RivaLine *Line;
1833- RivaTexturedTriangle03 *Tri03;
1834- RivaTexturedTriangle05 *Tri05;
1835 } RIVA_HW_INST;
1836 /*
1837 * Extended mode state information.
1838@@ -446,14 +378,19 @@
1839 U032 repaint0;
1840 U032 repaint1;
1841 U032 screen;
1842+ U032 scale;
1843 U032 extra;
1844 U032 pixel;
1845 U032 horiz;
1846 U032 arbitration0;
1847 U032 arbitration1;
1848 U032 vpll;
1849+ U032 vpll2;
1850 U032 pllsel;
1851 U032 general;
1852+ U032 crtcOwner;
1853+ U032 head;
1854+ U032 head2;
1855 U032 config;
1856 U032 cursor0;
1857 U032 cursor1;
1858--- XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/nv.orig/riva_tbl.h Thu Sep 20 08:40:06 2001
1859+++ XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/drivers/nv/riva_tbl.h Sun Apr 14 15:59:41 2002
1860@@ -633,180 +633,6 @@
1861 {0x000001C9, 0x0077D777},
1862 {0x00000186, 0x000070E5},
1863 {0x0000020C, 0x0E0D0D0D}
1864-};
1865-static unsigned nv10tri05TablePGRAPH[][2] =
1866-{
1867- {(0x00000E00/4), 0x00000000},
1868- {(0x00000E04/4), 0x00000000},
1869- {(0x00000E08/4), 0x00000000},
1870- {(0x00000E0C/4), 0x00000000},
1871- {(0x00000E10/4), 0x00001000},
1872- {(0x00000E14/4), 0x00001000},
1873- {(0x00000E18/4), 0x4003ff80},
1874- {(0x00000E1C/4), 0x00000000},
1875- {(0x00000E20/4), 0x00000000},
1876- {(0x00000E24/4), 0x00000000},
1877- {(0x00000E28/4), 0x00000000},
1878- {(0x00000E2C/4), 0x00000000},
1879- {(0x00000E30/4), 0x00080008},
1880- {(0x00000E34/4), 0x00080008},
1881- {(0x00000E38/4), 0x00000000},
1882- {(0x00000E3C/4), 0x00000000},
1883- {(0x00000E40/4), 0x00000000},
1884- {(0x00000E44/4), 0x00000000},
1885- {(0x00000E48/4), 0x00000000},
1886- {(0x00000E4C/4), 0x00000000},
1887- {(0x00000E50/4), 0x00000000},
1888- {(0x00000E54/4), 0x00000000},
1889- {(0x00000E58/4), 0x00000000},
1890- {(0x00000E5C/4), 0x00000000},
1891- {(0x00000E60/4), 0x00000000},
1892- {(0x00000E64/4), 0x10000000},
1893- {(0x00000E68/4), 0x00000000},
1894- {(0x00000E6C/4), 0x00000000},
1895- {(0x00000E70/4), 0x00000000},
1896- {(0x00000E74/4), 0x00000000},
1897- {(0x00000E78/4), 0x00000000},
1898- {(0x00000E7C/4), 0x00000000},
1899- {(0x00000E80/4), 0x00000000},
1900- {(0x00000E84/4), 0x00000000},
1901- {(0x00000E88/4), 0x08000000},
1902- {(0x00000E8C/4), 0x00000000},
1903- {(0x00000E90/4), 0x00000000},
1904- {(0x00000E94/4), 0x00000000},
1905- {(0x00000E98/4), 0x00000000},
1906- {(0x00000E9C/4), 0x4B7FFFFF},
1907- {(0x00000EA0/4), 0x00000000},
1908- {(0x00000EA4/4), 0x00000000},
1909- {(0x00000EA8/4), 0x00000000},
1910- {(0x00000F00/4), 0x07FF0800},
1911- {(0x00000F04/4), 0x07FF0800},
1912- {(0x00000F08/4), 0x07FF0800},
1913- {(0x00000F0C/4), 0x07FF0800},
1914- {(0x00000F10/4), 0x07FF0800},
1915- {(0x00000F14/4), 0x07FF0800},
1916- {(0x00000F18/4), 0x07FF0800},
1917- {(0x00000F1C/4), 0x07FF0800},
1918- {(0x00000F20/4), 0x07FF0800},
1919- {(0x00000F24/4), 0x07FF0800},
1920- {(0x00000F28/4), 0x07FF0800},
1921- {(0x00000F2C/4), 0x07FF0800},
1922- {(0x00000F30/4), 0x07FF0800},
1923- {(0x00000F34/4), 0x07FF0800},
1924- {(0x00000F38/4), 0x07FF0800},
1925- {(0x00000F3C/4), 0x07FF0800},
1926- {(0x00000F40/4), 0x10000000},
1927- {(0x00000F44/4), 0x00000000},
1928- {(0x00000F50/4), 0x00006740},
1929- {(0x00000F54/4), 0x00000000},
1930- {(0x00000F54/4), 0x00000000},
1931- {(0x00000F54/4), 0x00000000},
1932- {(0x00000F54/4), 0x3F800000},
1933- {(0x00000F50/4), 0x00006750},
1934- {(0x00000F54/4), 0x40000000},
1935- {(0x00000F54/4), 0x40000000},
1936- {(0x00000F54/4), 0x40000000},
1937- {(0x00000F54/4), 0x40000000},
1938- {(0x00000F50/4), 0x00006760},
1939- {(0x00000F54/4), 0x00000000},
1940- {(0x00000F54/4), 0x00000000},
1941- {(0x00000F54/4), 0x3F800000},
1942- {(0x00000F54/4), 0x00000000},
1943- {(0x00000F50/4), 0x00006770},
1944- {(0x00000F54/4), 0xC5000000},
1945- {(0x00000F54/4), 0xC5000000},
1946- {(0x00000F54/4), 0x00000000},
1947- {(0x00000F54/4), 0x00000000},
1948- {(0x00000F50/4), 0x00006780},
1949- {(0x00000F54/4), 0x00000000},
1950- {(0x00000F54/4), 0x00000000},
1951- {(0x00000F54/4), 0x3F800000},
1952- {(0x00000F54/4), 0x00000000},
1953- {(0x00000F50/4), 0x000067A0},
1954- {(0x00000F54/4), 0x3F800000},
1955- {(0x00000F54/4), 0x3F800000},
1956- {(0x00000F54/4), 0x3F800000},
1957- {(0x00000F54/4), 0x3F800000},
1958- {(0x00000F50/4), 0x00006AB0},
1959- {(0x00000F54/4), 0x3F800000},
1960- {(0x00000F54/4), 0x3F800000},
1961- {(0x00000F54/4), 0x3F800000},
1962- {(0x00000F50/4), 0x00006AC0},
1963- {(0x00000F54/4), 0x00000000},
1964- {(0x00000F54/4), 0x00000000},
1965- {(0x00000F54/4), 0x00000000},
1966- {(0x00000F50/4), 0x00006C10},
1967- {(0x00000F54/4), 0xBF800000},
1968- {(0x00000F50/4), 0x00007030},
1969- {(0x00000F54/4), 0x7149F2CA},
1970- {(0x00000F50/4), 0x00007040},
1971- {(0x00000F54/4), 0x7149F2CA},
1972- {(0x00000F50/4), 0x00007050},
1973- {(0x00000F54/4), 0x7149F2CA},
1974- {(0x00000F50/4), 0x00007060},
1975- {(0x00000F54/4), 0x7149F2CA},
1976- {(0x00000F50/4), 0x00007070},
1977- {(0x00000F54/4), 0x7149F2CA},
1978- {(0x00000F50/4), 0x00007080},
1979- {(0x00000F54/4), 0x7149F2CA},
1980- {(0x00000F50/4), 0x00007090},
1981- {(0x00000F54/4), 0x7149F2CA},
1982- {(0x00000F50/4), 0x000070A0},
1983- {(0x00000F54/4), 0x7149F2CA},
1984- {(0x00000F50/4), 0x00006A80},
1985- {(0x00000F54/4), 0x00000000},
1986- {(0x00000F54/4), 0x00000000},
1987- {(0x00000F54/4), 0x3F800000},
1988- {(0x00000F50/4), 0x00006AA0},
1989- {(0x00000F54/4), 0x00000000},
1990- {(0x00000F54/4), 0x00000000},
1991- {(0x00000F54/4), 0x00000000},
1992- {(0x00000F50/4), 0x00000040},
1993- {(0x00000F54/4), 0x00000005},
1994- {(0x00000F50/4), 0x00006400},
1995- {(0x00000F54/4), 0x3F800000},
1996- {(0x00000F54/4), 0x3F800000},
1997- {(0x00000F54/4), 0x4B7FFFFF},
1998- {(0x00000F54/4), 0x00000000},
1999- {(0x00000F50/4), 0x00006410},
2000- {(0x00000F54/4), 0xC5000000},
2001- {(0x00000F54/4), 0xC5000000},
2002- {(0x00000F54/4), 0x00000000},
2003- {(0x00000F54/4), 0x00000000},
2004- {(0x00000F50/4), 0x00006420},
2005- {(0x00000F54/4), 0x00000000},
2006- {(0x00000F54/4), 0x00000000},
2007- {(0x00000F54/4), 0x00000000},
2008- {(0x00000F54/4), 0x00000000},
2009- {(0x00000F50/4), 0x00006430},
2010- {(0x00000F54/4), 0x00000000},
2011- {(0x00000F54/4), 0x00000000},
2012- {(0x00000F54/4), 0x00000000},
2013- {(0x00000F54/4), 0x00000000},
2014- {(0x00000F50/4), 0x000064C0},
2015- {(0x00000F54/4), 0x3F800000},
2016- {(0x00000F54/4), 0x3F800000},
2017- {(0x00000F54/4), 0x477FFFFF},
2018- {(0x00000F54/4), 0x3F800000},
2019- {(0x00000F50/4), 0x000064D0},
2020- {(0x00000F54/4), 0xC5000000},
2021- {(0x00000F54/4), 0xC5000000},
2022- {(0x00000F54/4), 0x00000000},
2023- {(0x00000F54/4), 0x00000000},
2024- {(0x00000F50/4), 0x000064E0},
2025- {(0x00000F54/4), 0xC4FFF000},
2026- {(0x00000F54/4), 0xC4FFF000},
2027- {(0x00000F54/4), 0x00000000},
2028- {(0x00000F54/4), 0x00000000},
2029- {(0x00000F50/4), 0x000064F0},
2030- {(0x00000F54/4), 0x00000000},
2031- {(0x00000F54/4), 0x00000000},
2032- {(0x00000F54/4), 0x00000000},
2033- {(0x00000F54/4), 0x00000000},
2034- {(0x00000F40/4), 0x30000000},
2035- {(0x00000F44/4), 0x00000004},
2036- {(0x00000F48/4), 0x10000000},
2037- {(0x00000F4C/4), 0x00000000}
2038 };
2039 static unsigned nv10TablePRAMIN[][2] =
2040 {
2041--- XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/common/xf86PciInfo.h.orig Sun Apr 14 15:53:25 2002
2042+++ XFree86-4.2.0/xc/programs/Xserver/hw/xfree86/common/xf86PciInfo.h Sun Apr 14 16:02:42 2002
2043@@ -508,42 +508,47 @@
2044 #define PCI_CHIP_BT849 0x0351
2045
2046 /* NVIDIA */
2047-#define PCI_CHIP_NV1 0x0008
2048-#define PCI_CHIP_DAC64 0x0009
2049-#define PCI_CHIP_TNT 0x0020
2050-#define PCI_CHIP_TNT2 0x0028
2051-#define PCI_CHIP_UTNT2 0x0029
2052-#define PCI_CHIP_VTNT2 0x002C
2053-#define PCI_CHIP_UVTNT2 0x002D
2054-#define PCI_CHIP_ITNT2 0x00A0
2055-#define PCI_CHIP_GEFORCE256 0x0100
2056-#define PCI_CHIP_GEFORCEDDR 0x0101
2057-#define PCI_CHIP_QUADRO 0x0103
2058-#define PCI_CHIP_GEFORCE2MX 0x0110
2059-#define PCI_CHIP_GEFORCE2MXDDR 0x0111
2060-#define PCI_CHIP_GEFORCE2GO 0x0112
2061-#define PCI_CHIP_QUADRO2MXR 0x0113
2062-#define PCI_CHIP_GEFORCE2GTS 0x0150
2063-#define PCI_CHIP_GEFORCE2GTS_1 0x0151
2064-#define PCI_CHIP_GEFORCE2ULTRA 0x0152
2065-#define PCI_CHIP_QUADRO2PRO 0x0153
2066-#define PCI_CHIP_0x0170 0x0170
2067-#define PCI_CHIP_0x0171 0x0171
2068-#define PCI_CHIP_0x0172 0x0172
2069-#define PCI_CHIP_0x0173 0x0173
2070-#define PCI_CHIP_0x0174 0x0174
2071-#define PCI_CHIP_0x0175 0x0175
2072-#define PCI_CHIP_0x0178 0x0178
2073-#define PCI_CHIP_0x017A 0x017A
2074-#define PCI_CHIP_0x017B 0x017B
2075-#define PCI_CHIP_0x017C 0x017C
2076-#define PCI_CHIP_IGEFORCE2 0x01A0
2077-#define PCI_CHIP_GEFORCE3 0x0200
2078-#define PCI_CHIP_GEFORCE3_1 0x0201
2079-#define PCI_CHIP_GEFORCE3_2 0x0202
2080-#define PCI_CHIP_QUADRO_DDC 0x0203
2081-#define PCI_CHIP_0x0250 0x0250
2082-#define PCI_CHIP_0x0258 0x0258
2083+#define PCI_CHIP_NV1 0x0008
2084+#define PCI_CHIP_DAC64 0x0009
2085+#define PCI_CHIP_TNT 0x0020
2086+#define PCI_CHIP_TNT2 0x0028
2087+#define PCI_CHIP_UTNT2 0x0029
2088+#define PCI_CHIP_VTNT2 0x002C
2089+#define PCI_CHIP_UVTNT2 0x002D
2090+#define PCI_CHIP_ITNT2 0x00A0
2091+#define PCI_CHIP_GEFORCE_256 0x0100
2092+#define PCI_CHIP_GEFORCE_DDR 0x0101
2093+#define PCI_CHIP_QUADRO 0x0103
2094+#define PCI_CHIP_GEFORCE2_MX 0x0110
2095+#define PCI_CHIP_GEFORCE2_MX_100 0x0111
2096+#define PCI_CHIP_GEFORCE2_GO 0x0112
2097+#define PCI_CHIP_QUADRO2_MXR 0x0113
2098+#define PCI_CHIP_GEFORCE2_GTS 0x0150
2099+#define PCI_CHIP_GEFORCE2_TI 0x0151
2100+#define PCI_CHIP_GEFORCE2_ULTRA 0x0152
2101+#define PCI_CHIP_QUADRO2_PRO 0x0153
2102+#define PCI_CHIP_GEFORCE4_MX_460 0x0170
2103+#define PCI_CHIP_GEFORCE4_MX_440 0x0171
2104+#define PCI_CHIP_GEFORCE4_MX_420 0x0172
2105+#define PCI_CHIP_GEFORCE4_440_GO 0x0174
2106+#define PCI_CHIP_GEFORCE4_420_GO 0x0175
2107+#define PCI_CHIP_GEFORCE4_420_GO_M32 0x0176
2108+#define PCI_CHIP_QUADRO4_500XGL 0x0178
2109+#define PCI_CHIP_GEFORCE4_440_GO_M64 0x0179
2110+#define PCI_CHIP_QUADRO4_200 0x017A
2111+#define PCI_CHIP_QUADRO4_550XGL 0x017B
2112+#define PCI_CHIP_QUADRO4_500_GOGL 0x017C
2113+#define PCI_CHIP_IGEFORCE2 0x01A0
2114+#define PCI_CHIP_GEFORCE3 0x0200
2115+#define PCI_CHIP_GEFORCE3_TI_200 0x0201
2116+#define PCI_CHIP_GEFORCE3_TI_500 0x0202
2117+#define PCI_CHIP_QUADRO_DCC 0x0203
2118+#define PCI_CHIP_GEFORCE4_TI_4600 0x0250
2119+#define PCI_CHIP_GEFORCE4_TI_4400 0x0251
2120+#define PCI_CHIP_GEFORCE4_TI_4200 0x0253
2121+#define PCI_CHIP_QUADRO4_900XGL 0x0258
2122+#define PCI_CHIP_QUADRO4_750XGL 0x0259
2123+#define PCI_CHIP_QUADRO4_700XGL 0x025B
2124
2125 /* NVIDIA & SGS */
2126 #define PCI_CHIP_RIVA128 0x0018
2127@@ -1313,42 +1318,47 @@
2128 {0x0000, NULL,0}}},
2129 #endif
2130 {PCI_VENDOR_NVIDIA, {
2131- {PCI_CHIP_NV1, "NV1",0},
2132- {PCI_CHIP_DAC64, "DAC64",0},
2133- {PCI_CHIP_TNT, "RIVA TNT",0},
2134- {PCI_CHIP_TNT2, "RIVA TNT2/TNT2 Pro",0},
2135- {PCI_CHIP_UTNT2, "RIVA TNT2 Ultra",0},
2136- {PCI_CHIP_VTNT2, "Vanta",0},
2137- {PCI_CHIP_UVTNT2, "Riva TNT2 M64",0},
2138- {PCI_CHIP_ITNT2, "Aladdin TNT2",0},
2139- {PCI_CHIP_GEFORCE256, "GeForce 256",0},
2140- {PCI_CHIP_GEFORCEDDR, "GeForce DDR",0},
2141- {PCI_CHIP_QUADRO, "Quadro",0},
2142- {PCI_CHIP_GEFORCE2MX, "GeForce2 MX/MX 400",0},
2143- {PCI_CHIP_GEFORCE2MXDDR,"GeForce2 MX 100/200",0},
2144- {PCI_CHIP_GEFORCE2GO, "GeForce2 Go", 0},
2145- {PCI_CHIP_QUADRO2MXR, "Quadro2 MXR",0},
2146- {PCI_CHIP_GEFORCE2GTS, "GeForce2 GTS/Pro",0},
2147- {PCI_CHIP_GEFORCE2GTS_1,"GeForce2 Ti",0},
2148- {PCI_CHIP_GEFORCE2ULTRA,"GeForce2 Ultra",0},
2149- {PCI_CHIP_QUADRO2PRO, "Quadro2 Pro",0},
2150- {PCI_CHIP_0x0170, "0x0170",0},
2151- {PCI_CHIP_0x0171, "0x0171",0},
2152- {PCI_CHIP_0x0172, "0x0172",0},
2153- {PCI_CHIP_0x0173, "0x0173",0},
2154- {PCI_CHIP_0x0174, "0x0174",0},
2155- {PCI_CHIP_0x0175, "0x0175",0},
2156- {PCI_CHIP_0x0178, "0x0178",0},
2157- {PCI_CHIP_0x017A, "0x017A",0},
2158- {PCI_CHIP_0x017B, "0x017B",0},
2159- {PCI_CHIP_0x017C, "0x017C",0},
2160- {PCI_CHIP_IGEFORCE2, "GeForce2 Integrated",0},
2161- {PCI_CHIP_GEFORCE3, "GeForce3",0},
2162- {PCI_CHIP_GEFORCE3_1, "GeForce3 Ti 200",0},
2163- {PCI_CHIP_GEFORCE3_2, "GeForce3 Ti 500",0},
2164- {PCI_CHIP_QUADRO_DDC, "Quadro DDC",0},
2165- {PCI_CHIP_0x0250, "0x0250",0},
2166- {PCI_CHIP_0x0258, "0x0258",0},
2167+ {PCI_CHIP_NV1, "NV1",0},
2168+ {PCI_CHIP_DAC64, "DAC64",0},
2169+ {PCI_CHIP_TNT, "RIVA TNT",0},
2170+ {PCI_CHIP_TNT2, "RIVA TNT2/TNT2 Pro",0},
2171+ {PCI_CHIP_UTNT2, "RIVA TNT2 Ultra",0},
2172+ {PCI_CHIP_VTNT2, "Vanta",0},
2173+ {PCI_CHIP_UVTNT2, "Riva TNT2 M64",0},
2174+ {PCI_CHIP_ITNT2, "Aladdin TNT2",0},
2175+ {PCI_CHIP_GEFORCE_256, "GeForce 256",0},
2176+ {PCI_CHIP_GEFORCE_DDR, "GeForce DDR",0},
2177+ {PCI_CHIP_QUADRO, "Quadro",0},
2178+ {PCI_CHIP_GEFORCE2_MX, "GeForce2 MX/MX 400",0},
2179+ {PCI_CHIP_GEFORCE2_MX_100, "GeForce2 MX 100/200",0},
2180+ {PCI_CHIP_GEFORCE2_GO, "GeForce2 Go", 0},
2181+ {PCI_CHIP_QUADRO2_MXR, "Quadro2 MXR",0},
2182+ {PCI_CHIP_GEFORCE2_GTS, "GeForce2 GTS/Pro",0},
2183+ {PCI_CHIP_GEFORCE2_TI, "GeForce2 Ti",0},
2184+ {PCI_CHIP_GEFORCE2_ULTRA, "GeForce2 Ultra",0},
2185+ {PCI_CHIP_QUADRO2_PRO, "Quadro2 Pro",0},
2186+ {PCI_CHIP_GEFORCE4_MX_460, "GeForce4 MX 460",0},
2187+ {PCI_CHIP_GEFORCE4_MX_440, "GeForce4 MX 440",0},
2188+ {PCI_CHIP_GEFORCE4_MX_420, "GeForce4 MX 420",0},
2189+ {PCI_CHIP_GEFORCE4_440_GO, "GeForce4 440 Go",0},
2190+ {PCI_CHIP_GEFORCE4_420_GO, "GeForce4 420 Go",0},
2191+ {PCI_CHIP_GEFORCE4_420_GO_M32,"GeForce4 420 Go M32",0},
2192+ {PCI_CHIP_QUADRO4_500XGL, "Quadro4 500XGL",0},
2193+ {PCI_CHIP_GEFORCE4_440_GO_M64,"GeForce4 440 Go M64",0},
2194+ {PCI_CHIP_QUADRO4_200, "Quadro4 200/400NVS",0},
2195+ {PCI_CHIP_QUADRO4_550XGL, "Quadro4 550XGL",0},
2196+ {PCI_CHIP_QUADRO4_500_GOGL, "Quadro4 GoGL",0},
2197+ {PCI_CHIP_IGEFORCE2, "GeForce2 Integrated",0},
2198+ {PCI_CHIP_GEFORCE3, "GeForce3",0},
2199+ {PCI_CHIP_GEFORCE3_TI_200, "GeForce3 Ti 200",0},
2200+ {PCI_CHIP_GEFORCE3_TI_500, "GeForce3 Ti 500",0},
2201+ {PCI_CHIP_QUADRO_DCC, "Quadro DCC",0},
2202+ {PCI_CHIP_GEFORCE4_TI_4600, "GeForce4 Ti 4600",0},
2203+ {PCI_CHIP_GEFORCE4_TI_4400, "GeForce4 Ti 4400",0},
2204+ {PCI_CHIP_GEFORCE4_TI_4200, "GeForce4 Ti 4200",0},
2205+ {PCI_CHIP_QUADRO4_900XGL, "Quadro4 900 XGL",0},
2206+ {PCI_CHIP_QUADRO4_750XGL, "Quadro4 750 XGL",0},
2207+ {PCI_CHIP_QUADRO4_700XGL, "Quadro4 700 XGL",0},
2208 {0x0000, NULL,0}}},
2209 {PCI_VENDOR_IMS, {
2210 {PCI_CHIP_IMSTT128, "TwinTurbo 128", 0},
XFree86 Window System servers and basic programs
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